From ce06d1cf7baeb10aa3ffef90f51ee4c3a0b81a46 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Fri, 3 Aug 2012 08:53:02 +0000 Subject: [PATCH] [lantiq] cleanup patches git-svn-id: svn://svn.openwrt.org/openwrt/trunk@32953 3c298f89-4303-0410-b956-a3cf2f4a3e73 --- .../files/arch/mips/configs/ase_defconfig | 67 + .../files/arch/mips/configs/falcon_defconfig | 72 + .../files/arch/mips/configs/xway_defconfig | 66 + .../files/arch/mips/include/asm/clkdev.h | 25 + .../asm/mach-lantiq/falcon/falcon_irq.h | 268 + .../mips/include/asm/mach-lantiq/falcon/irq.h | 18 + .../asm/mach-lantiq/falcon/lantiq_soc.h | 152 + .../include/asm/mach-lantiq/lantiq_timer.h | 155 + .../include/asm/mach-lantiq/svip/base_reg.h | 56 + .../include/asm/mach-lantiq/svip/boot_reg.h | 37 + .../include/asm/mach-lantiq/svip/dma_reg.h | 308 + .../include/asm/mach-lantiq/svip/ebu_reg.h | 615 + .../include/asm/mach-lantiq/svip/es_reg.h | 2098 + .../mips/include/asm/mach-lantiq/svip/irq.h | 36 + .../include/asm/mach-lantiq/svip/lantiq_soc.h | 71 + .../include/asm/mach-lantiq/svip/mps_reg.h | 242 + .../include/asm/mach-lantiq/svip/port_reg.h | 3262 + .../include/asm/mach-lantiq/svip/ssc_reg.h | 624 + .../include/asm/mach-lantiq/svip/status_reg.h | 130 + .../include/asm/mach-lantiq/svip/svip_dma.h | 245 + .../include/asm/mach-lantiq/svip/svip_irq.h | 35 + .../include/asm/mach-lantiq/svip/svip_mux.h | 467 + .../include/asm/mach-lantiq/svip/svip_pms.h | 23 + .../include/asm/mach-lantiq/svip/sys0_reg.h | 165 + .../include/asm/mach-lantiq/svip/sys1_reg.h | 370 + .../include/asm/mach-lantiq/svip/sys2_reg.h | 494 + .../files/arch/mips/lantiq/falcon/Kconfig | 11 + .../files/arch/mips/lantiq/falcon/Makefile | 2 + .../files/arch/mips/lantiq/falcon/devices.c | 152 + .../files/arch/mips/lantiq/falcon/devices.h | 25 + .../files/arch/mips/lantiq/falcon/gpio.c | 409 + .../arch/mips/lantiq/falcon/mach-easy98000.c | 138 + .../files/arch/mips/lantiq/falcon/prom.c | 84 + .../files/arch/mips/lantiq/falcon/reset.c | 87 + .../files/arch/mips/lantiq/falcon/sysctrl.c | 211 + .../files/arch/mips/lantiq/svip/Kconfig | 16 + .../files/arch/mips/lantiq/svip/Makefile | 3 + .../files/arch/mips/lantiq/svip/clk-svip.c | 100 + .../files/arch/mips/lantiq/svip/devices.c | 385 + .../files/arch/mips/lantiq/svip/devices.h | 23 + .../lantiq/files/arch/mips/lantiq/svip/dma.c | 1206 + .../lantiq/files/arch/mips/lantiq/svip/gpio.c | 553 + .../arch/mips/lantiq/svip/mach-easy33016.c | 73 + .../arch/mips/lantiq/svip/mach-easy336.c | 221 + .../lantiq/files/arch/mips/lantiq/svip/mux.c | 187 + .../lantiq/files/arch/mips/lantiq/svip/pms.c | 101 + .../lantiq/files/arch/mips/lantiq/svip/prom.c | 73 + .../files/arch/mips/lantiq/svip/reset.c | 95 + .../arch/mips/lantiq/svip/switchip_setup.c | 666 + .../lantiq/files/arch/mips/lantiq/xway/clk.c | 329 + .../files/arch/mips/lantiq/xway/dev-ifxhcd.c | 45 + .../files/arch/mips/lantiq/xway/dev-ifxhcd.h | 17 + .../lantiq/files/arch/mips/lantiq/xway/gptu.c | 176 + .../arch/mips/lantiq/xway/mach-easy50601.c | 58 - .../arch/mips/lantiq/xway/mach-easy50712.c | 71 - .../lantiq/files/arch/mips/lantiq/xway/nand.c | 216 + .../lantiq/files/arch/mips/lantiq/xway/prom.c | 110 + .../files/arch/mips/lantiq/xway/sysctrl.c | 283 + .../files/arch/mips/lantiq/xway/timer.c | 846 + .../files/arch/mips/pci/fixup-lantiq-pcie.c | 81 + .../lantiq/files/arch/mips/pci/fixup-lantiq.c | 42 + .../files/arch/mips/pci/pcie-lantiq-msi.c | 399 + .../files/arch/mips/pci/pcie-lantiq-phy.c | 408 + .../lantiq/files/arch/mips/pci/pcie-lantiq.c | 1146 + .../lantiq/files/arch/mips/pci/pcie-lantiq.h | 1305 + .../files/drivers/i2c/busses/i2c-falcon.c | 1040 + .../drivers/net/ethernet/lantiq_vrx200.c | 1358 + .../files/drivers/net/ethernet/svip_eth.c | 636 + .../drivers/net/ethernet/svip_virtual_eth.c | 346 + .../lantiq/files/drivers/spi/spi-falcon.c | 483 + .../linux/lantiq/files/drivers/spi/spi-xway.c | 1070 + .../linux/lantiq/files/drivers/spi/spi_svip.c | 955 + .../lantiq/files/drivers/usb/dwc_otg/Kconfig | 37 + .../lantiq/files/drivers/usb/dwc_otg/Makefile | 39 + .../files/drivers/usb/dwc_otg/dwc_otg_attr.c | 802 + .../files/drivers/usb/dwc_otg/dwc_otg_attr.h | 67 + .../files/drivers/usb/dwc_otg/dwc_otg_cil.c | 3025 + .../files/drivers/usb/dwc_otg/dwc_otg_cil.h | 911 + .../drivers/usb/dwc_otg/dwc_otg_cil_ifx.h | 58 + .../drivers/usb/dwc_otg/dwc_otg_cil_intr.c | 708 + .../drivers/usb/dwc_otg/dwc_otg_driver.c | 1277 + .../drivers/usb/dwc_otg/dwc_otg_driver.h | 84 + .../files/drivers/usb/dwc_otg/dwc_otg_hcd.c | 2870 + .../files/drivers/usb/dwc_otg/dwc_otg_hcd.h | 676 + .../drivers/usb/dwc_otg/dwc_otg_hcd_intr.c | 1839 + .../drivers/usb/dwc_otg/dwc_otg_hcd_queue.c | 794 + .../files/drivers/usb/dwc_otg/dwc_otg_ifx.c | 103 + .../files/drivers/usb/dwc_otg/dwc_otg_ifx.h | 85 + .../files/drivers/usb/dwc_otg/dwc_otg_plat.h | 269 + .../files/drivers/usb/dwc_otg/dwc_otg_regs.h | 1797 + .../lantiq/files/drivers/usb/ifxhcd/Kconfig | 58 + .../lantiq/files/drivers/usb/ifxhcd/Makefile | 85 + .../files/drivers/usb/ifxhcd/TagHistory | 171 + .../lantiq/files/drivers/usb/ifxhcd/ifxhcd.c | 2523 + .../lantiq/files/drivers/usb/ifxhcd/ifxhcd.h | 628 + .../files/drivers/usb/ifxhcd/ifxhcd_es.c | 549 + .../files/drivers/usb/ifxhcd/ifxhcd_intr.c | 3742 + .../files/drivers/usb/ifxhcd/ifxhcd_queue.c | 418 + .../files/drivers/usb/ifxhcd/ifxusb_cif.c | 1458 + .../files/drivers/usb/ifxhcd/ifxusb_cif.h | 665 + .../files/drivers/usb/ifxhcd/ifxusb_cif_d.c | 458 + .../files/drivers/usb/ifxhcd/ifxusb_cif_h.c | 846 + .../files/drivers/usb/ifxhcd/ifxusb_ctl.c | 1385 + .../files/drivers/usb/ifxhcd/ifxusb_driver.c | 970 + .../files/drivers/usb/ifxhcd/ifxusb_plat.h | 1018 + .../files/drivers/usb/ifxhcd/ifxusb_regs.h | 1420 + .../files/drivers/usb/ifxhcd/ifxusb_version.h | 5 + .../lantiq/files/include/linux/svip_nat.h | 37 + .../lantiq/files/include/linux/svip_nat_io.h | 103 + target/linux/lantiq/files/net/ipv4/svip_nat.c | 1569 + ...001-MTD-add-m25p80-id-for-mx25l2005a.patch | 19 - .../patches-3.3/0001-falcon-support.patch | 25 + ...002-MIPS-lantiq-reorganize-xway-code.patch | 835 - .../patches-3.3/0002-xway-support.patch | 1586 + ...ange-ltq_request_gpio-call-signature.patch | 138 - .../lantiq/patches-3.3/0003-svip-hack.patch | 42 + ...antiq-make-irq.c-support-the-FALC-ON.patch | 69 - .../0004-lantiq-core-support.patch | 1009 + ...lantiq-add-basic-support-for-FALC-ON.patch | 1047 - .../lantiq/patches-3.3/0005-pci-support.patch | 355 + ...lantiq-add-support-for-FALC-ON-GPIOs.patch | 489 - .../lantiq/patches-3.3/0006-mtd-support.patch | 98 + ...support-for-the-EASY98000-evaluation.patch | 165 - .../lantiq/patches-3.3/0007-usb-support.patch | 71 + .../0008-MIPS-lantiq-fix-early-printk.patch | 61 - .../lantiq/patches-3.3/0008-spi-support.patch | 74 + ...0009-MIPS-lantiq-fix-cmdline-parsing.patch | 31 - .../patches-3.3/0009-ethernet-support.patch | 785 + ...0010-MIPS-lantiq-fix-STP-gpio-groups.patch | 37 - .../patches-3.3/0010-watchdog-support.patch | 74 + ...tiq-fix-pull-gpio-up-resistors-usage.patch | 43 - .../lantiq/patches-3.3/0011-i2c-support.patch | 46 + ...0012-MIPS-lantiq-add-default-configs.patch | 235 - .../lantiq/patches-3.3/0012-tty-support.patch | 90 + ...S-add-entry-for-Lantiq-related-files.patch | 33 - .../patches-3.3/0013-machtype-support.patch | 568 + ...le-oprofile-support-on-lantiq-target.patch | 46 - .../0014-import-compat-headers.patch | 82118 ++++++++++++++++ ...q-make-etop-ethernet-work-on-ase-ar9.patch | 396 - ...nsions.patch => 0015-VPE-extensions.patch} | 49 +- ...non-existing-phy-was-not-handled-gra.patch | 62 - ...og.patch => 0016-falcon-VPE-softdog.patch} | 13 +- ...return-value-of-request_irq-was-not-.patch | 66 - ...atch => 0017-udp-in-kernel-redirect.patch} | 29 +- ...MIPS-lantiq-use-devres-managed-gpios.patch | 259 - ...che-split.patch => 0018-cache-split.patch} | 21 +- .../patches-3.3/0019-MIPS-add-clkdev.h.patch | 43 - ..._split.patch => 0019-owrt-mtd-split.patch} | 95 +- ...q-helper-functions-for-SoC-detection.patch | 52 - ...202-owrt-atm.patch => 0020-owrt-atm.patch} | 57 +- ...21-MIPS-lantiq-convert-to-clkdev-api.patch | 285 - ...-cmdline.patch => 0021-owrt-cmdline.patch} | 16 +- ...PS-lantiq-convert-xway-to-clkdev-api.patch | 718 - ...g.patch => 0022-owrt-dm9000-polling.patch} | 22 +- ...-lantiq-convert-falcon-to-clkdev-api.patch | 235 - ...port.patch => 0023-owrt-gpio-export.patch} | 18 +- ...tiq-convert-dma-driver-to-clkdev-api.patch | 57 - ...ritz_ram.patch => 0024-fritzbox-ram.patch} | 14 + ...onvert-gpio_stp-driver-to-clkdev-api.patch | 55 - ...535-svip_cp1.patch => 0025-svip-cp1.patch} | 44 +- ...iq-convert-falcon-gpio-to-clkdev-api.patch | 66 - ...iq-convert-serial-driver-to-clkdev-a.patch | 36 - ...vert-falcon-debug-uart-to-clkdev-api.patch | 66 - ...iq-convert-etop-driver-to-clkdev-api.patch | 118 - ...convert-watchdog-driver-to-clkdev-ap.patch | 25 - ...031-MIPS-lantiq-unify-xway-prom-code.patch | 239 - .../0032-MIPS-lantiq-add-vr9-support.patch | 161 - ...q-add-ipi-handlers-to-make-vsmp-work.patch | 117 - ...4-MIPS-lantiq-add-additional-soc-ids.patch | 149 - ...I-MIPS-lantiq-add-FALC-ON-spi-driver.patch | 617 - ...PS-lantiq-add-FALC-ON-i2c-bus-master.patch | 1204 - ...037-MIPS-lantiq-add-xway-nand-driver.patch | 294 - .../0038-SPI-MIPS-lantiq-adds-spi-xway.patch | 1137 - ...-adds-driver-for-lantiq-vr9-ethernet.patch | 1454 - ...IPS-NET-several-fixes-to-etop-driver.patch | 440 - ...use-module_platform_driver-inside-la.patch | 59 - ...use-module_platform_driver-inside-la.patch | 56 - .../0043-MIPS-lantiq-adds-GPTU-driver.patch | 1039 - .../0044-MIPS-lantiq-adds-dwc_otg.patch | 15576 --- ...45-dwc_otg-remove-bogus-halt_channel.patch | 21 - .../patches-3.3/0046-MIPS-adds-ifxhcd.patch | 16604 ---- .../0047-MIPS-adds-gptu-driver.patch | 189 - ...PS-lantiq-pci-rename-variable-inside.patch | 70 - ...give-xway-pci-support-its-own-kbuild.patch | 38 - ...move-pcibios-code-into-fixup-lantiq..patch | 121 - ...051-MIPS-lantiq-pcie-add-pcie-driver.patch | 3475 - ...2-MIPS-lantiq-make-GPIO3-work-on-AR9.patch | 223 - .../0057-MIPS-clean-up-clock-code.patch | 308 - .../0058-MIPS-cleanup-reset-code.patch | 98 - ...0059-MIPS-lantiq-fixes-ar9-vr9-clock.patch | 107 - .../0060-MIPS-lantiq-fixes-danube-clock.patch | 52 - .../0061-MIPS-adds-dsl-clocks.patch | 61 - ...IPS-lantiq-dont-always-register-asc0.patch | 26 - ...0064-MIPS-lantiq-adds-bootsel-helper.patch | 59 - ...ds-USB_ARCH_HAS_HCD-to-CONFIG_LANTIQ.patch | 19 - ...S-lantiq-fixes-bad-PMU_USB0-0-define.patch | 20 - ...-MIPS-lantiq-fix-dwc_otg-usb-for-ase.patch | 51 - ...p-fix-for-ase-add-get-clock-disabled.patch | 83 - ...spi-for-ase-update-for-clkdev-and-pl.patch | 188 - .../patches-3.3/0070-icu-multi-base.patch | 233 - .../patches-3.3/0072-fix_i2c_clock.patch | 32 - .../patches-3.3/100-falcon_bsp_header.patch | 13633 --- .../lantiq/patches-3.3/101-sdk-compat.patch | 63 - .../105-falcon_header_update.patch | 11 - .../lantiq/patches-3.3/206-machtypes.patch | 321 - .../lantiq/patches-3.3/207-devices.patch | 191 - .../patches-3.3/208-fix-mach-easy98000.patch | 68 - .../lantiq/patches-3.3/300-svip_header.patch | 9518 -- .../lantiq/patches-3.3/310-svip_board.patch | 7636 -- 209 files changed, 146978 insertions(+), 82080 deletions(-) create mode 100644 target/linux/lantiq/files/arch/mips/configs/ase_defconfig create mode 100644 target/linux/lantiq/files/arch/mips/configs/falcon_defconfig create mode 100644 target/linux/lantiq/files/arch/mips/configs/xway_defconfig create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/clkdev.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/irq.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/lantiq_timer.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/base_reg.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/boot_reg.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/dma_reg.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ebu_reg.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/es_reg.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/irq.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/lantiq_soc.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/mps_reg.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/port_reg.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ssc_reg.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/status_reg.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_dma.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_mux.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_pms.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys0_reg.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys1_reg.h create mode 100644 target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys2_reg.h create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/falcon/Kconfig create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/falcon/Makefile create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/falcon/devices.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/falcon/devices.h create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/falcon/gpio.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/falcon/mach-easy98000.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/falcon/prom.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/falcon/reset.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/falcon/sysctrl.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/svip/Kconfig create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/svip/Makefile create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/svip/clk-svip.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/svip/devices.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/svip/devices.h create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/svip/dma.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/svip/gpio.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/svip/mach-easy33016.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/svip/mach-easy336.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/svip/mux.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/svip/pms.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/svip/prom.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/svip/reset.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/svip/switchip_setup.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/xway/clk.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/xway/dev-ifxhcd.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/xway/dev-ifxhcd.h create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/xway/gptu.c delete mode 100644 target/linux/lantiq/files/arch/mips/lantiq/xway/mach-easy50601.c delete mode 100644 target/linux/lantiq/files/arch/mips/lantiq/xway/mach-easy50712.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/xway/nand.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/xway/prom.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/xway/sysctrl.c create mode 100644 target/linux/lantiq/files/arch/mips/lantiq/xway/timer.c create mode 100644 target/linux/lantiq/files/arch/mips/pci/fixup-lantiq-pcie.c create mode 100644 target/linux/lantiq/files/arch/mips/pci/fixup-lantiq.c create mode 100644 target/linux/lantiq/files/arch/mips/pci/pcie-lantiq-msi.c create mode 100644 target/linux/lantiq/files/arch/mips/pci/pcie-lantiq-phy.c create mode 100644 target/linux/lantiq/files/arch/mips/pci/pcie-lantiq.c create mode 100644 target/linux/lantiq/files/arch/mips/pci/pcie-lantiq.h create mode 100644 target/linux/lantiq/files/drivers/i2c/busses/i2c-falcon.c create mode 100644 target/linux/lantiq/files/drivers/net/ethernet/lantiq_vrx200.c create mode 100644 target/linux/lantiq/files/drivers/net/ethernet/svip_eth.c create mode 100644 target/linux/lantiq/files/drivers/net/ethernet/svip_virtual_eth.c create mode 100644 target/linux/lantiq/files/drivers/spi/spi-falcon.c create mode 100644 target/linux/lantiq/files/drivers/spi/spi-xway.c create mode 100644 target/linux/lantiq/files/drivers/spi/spi_svip.c create mode 100644 target/linux/lantiq/files/drivers/usb/dwc_otg/Kconfig create mode 100644 target/linux/lantiq/files/drivers/usb/dwc_otg/Makefile create mode 100644 target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_attr.c create mode 100644 target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_attr.h create mode 100644 target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil.c create mode 100644 target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil.h create mode 100644 target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h create mode 100644 target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil_intr.c create mode 100644 target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_driver.c create mode 100644 target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_driver.h create mode 100644 target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_hcd.c create mode 100644 target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_hcd.h create mode 100644 target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c create mode 100644 target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c create mode 100644 target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_ifx.c create mode 100644 target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_ifx.h create mode 100644 target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_plat.h create mode 100644 target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_regs.h create mode 100644 target/linux/lantiq/files/drivers/usb/ifxhcd/Kconfig create mode 100644 target/linux/lantiq/files/drivers/usb/ifxhcd/Makefile create mode 100644 target/linux/lantiq/files/drivers/usb/ifxhcd/TagHistory create mode 100644 target/linux/lantiq/files/drivers/usb/ifxhcd/ifxhcd.c create mode 100644 target/linux/lantiq/files/drivers/usb/ifxhcd/ifxhcd.h create mode 100644 target/linux/lantiq/files/drivers/usb/ifxhcd/ifxhcd_es.c create mode 100644 target/linux/lantiq/files/drivers/usb/ifxhcd/ifxhcd_intr.c create mode 100644 target/linux/lantiq/files/drivers/usb/ifxhcd/ifxhcd_queue.c create mode 100644 target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_cif.c create mode 100644 target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_cif.h create mode 100644 target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_cif_d.c create mode 100644 target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_cif_h.c create mode 100644 target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_ctl.c create mode 100644 target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_driver.c create mode 100644 target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_plat.h create mode 100644 target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_regs.h create mode 100644 target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_version.h create mode 100644 target/linux/lantiq/files/include/linux/svip_nat.h create mode 100644 target/linux/lantiq/files/include/linux/svip_nat_io.h create mode 100644 target/linux/lantiq/files/net/ipv4/svip_nat.c delete mode 100644 target/linux/lantiq/patches-3.3/0001-MTD-add-m25p80-id-for-mx25l2005a.patch create mode 100644 target/linux/lantiq/patches-3.3/0001-falcon-support.patch delete mode 100644 target/linux/lantiq/patches-3.3/0002-MIPS-lantiq-reorganize-xway-code.patch create mode 100644 target/linux/lantiq/patches-3.3/0002-xway-support.patch delete mode 100644 target/linux/lantiq/patches-3.3/0003-MIPS-lantiq-change-ltq_request_gpio-call-signature.patch create mode 100644 target/linux/lantiq/patches-3.3/0003-svip-hack.patch delete mode 100644 target/linux/lantiq/patches-3.3/0004-MIPS-lantiq-make-irq.c-support-the-FALC-ON.patch create mode 100644 target/linux/lantiq/patches-3.3/0004-lantiq-core-support.patch delete mode 100644 target/linux/lantiq/patches-3.3/0005-MIPS-lantiq-add-basic-support-for-FALC-ON.patch create mode 100644 target/linux/lantiq/patches-3.3/0005-pci-support.patch delete mode 100644 target/linux/lantiq/patches-3.3/0006-MIPS-lantiq-add-support-for-FALC-ON-GPIOs.patch create mode 100644 target/linux/lantiq/patches-3.3/0006-mtd-support.patch delete mode 100644 target/linux/lantiq/patches-3.3/0007-MIPS-lantiq-add-support-for-the-EASY98000-evaluation.patch create mode 100644 target/linux/lantiq/patches-3.3/0007-usb-support.patch delete mode 100644 target/linux/lantiq/patches-3.3/0008-MIPS-lantiq-fix-early-printk.patch create mode 100644 target/linux/lantiq/patches-3.3/0008-spi-support.patch delete mode 100644 target/linux/lantiq/patches-3.3/0009-MIPS-lantiq-fix-cmdline-parsing.patch create mode 100644 target/linux/lantiq/patches-3.3/0009-ethernet-support.patch delete mode 100644 target/linux/lantiq/patches-3.3/0010-MIPS-lantiq-fix-STP-gpio-groups.patch create mode 100644 target/linux/lantiq/patches-3.3/0010-watchdog-support.patch delete mode 100644 target/linux/lantiq/patches-3.3/0011-MIPS-lantiq-fix-pull-gpio-up-resistors-usage.patch create mode 100644 target/linux/lantiq/patches-3.3/0011-i2c-support.patch delete mode 100644 target/linux/lantiq/patches-3.3/0012-MIPS-lantiq-add-default-configs.patch create mode 100644 target/linux/lantiq/patches-3.3/0012-tty-support.patch delete mode 100644 target/linux/lantiq/patches-3.3/0013-MAINTAINERS-add-entry-for-Lantiq-related-files.patch create mode 100644 target/linux/lantiq/patches-3.3/0013-machtype-support.patch delete mode 100644 target/linux/lantiq/patches-3.3/0014-MIPS-lantiq-enable-oprofile-support-on-lantiq-target.patch create mode 100644 target/linux/lantiq/patches-3.3/0014-import-compat-headers.patch delete mode 100644 target/linux/lantiq/patches-3.3/0015-NET-MIPS-lantiq-make-etop-ethernet-work-on-ase-ar9.patch rename target/linux/lantiq/patches-3.3/{0053-MIPS-lantiq-VPE-extensions.patch => 0015-VPE-extensions.patch} (94%) delete mode 100644 target/linux/lantiq/patches-3.3/0016-NET-MIPS-lantiq-non-existing-phy-was-not-handled-gra.patch rename target/linux/lantiq/patches-3.3/{0054-MIPS-lantiq-falcon-VPE-softdog.patch => 0016-falcon-VPE-softdog.patch} (93%) delete mode 100644 target/linux/lantiq/patches-3.3/0017-NET-MIPS-lantiq-return-value-of-request_irq-was-not-.patch rename target/linux/lantiq/patches-3.3/{0055-MIPS-lantiq-udp-in-kernel-redirect.patch => 0017-udp-in-kernel-redirect.patch} (91%) delete mode 100644 target/linux/lantiq/patches-3.3/0018-MIPS-lantiq-use-devres-managed-gpios.patch rename target/linux/lantiq/patches-3.3/{0056-MIPS-lantiq-cache-split.patch => 0018-cache-split.patch} (93%) delete mode 100644 target/linux/lantiq/patches-3.3/0019-MIPS-add-clkdev.h.patch rename target/linux/lantiq/patches-3.3/{201-owrt-mtd_split.patch => 0019-owrt-mtd-split.patch} (82%) delete mode 100644 target/linux/lantiq/patches-3.3/0020-MIPS-lantiq-helper-functions-for-SoC-detection.patch rename target/linux/lantiq/patches-3.3/{202-owrt-atm.patch => 0020-owrt-atm.patch} (56%) delete mode 100644 target/linux/lantiq/patches-3.3/0021-MIPS-lantiq-convert-to-clkdev-api.patch rename target/linux/lantiq/patches-3.3/{203-owrt-cmdline.patch => 0021-owrt-cmdline.patch} (64%) delete mode 100644 target/linux/lantiq/patches-3.3/0022-MIPS-lantiq-convert-xway-to-clkdev-api.patch rename target/linux/lantiq/patches-3.3/{204-owrt-dm9000-polling.patch => 0022-owrt-dm9000-polling.patch} (80%) delete mode 100644 target/linux/lantiq/patches-3.3/0023-MIPS-lantiq-convert-falcon-to-clkdev-api.patch rename target/linux/lantiq/patches-3.3/{205-owrt-gpio-export.patch => 0023-owrt-gpio-export.patch} (69%) delete mode 100644 target/linux/lantiq/patches-3.3/0024-MIPS-lantiq-convert-dma-driver-to-clkdev-api.patch rename target/linux/lantiq/patches-3.3/{209-fritz_ram.patch => 0024-fritzbox-ram.patch} (55%) delete mode 100644 target/linux/lantiq/patches-3.3/0025-MIPS-lantiq-convert-gpio_stp-driver-to-clkdev-api.patch rename target/linux/lantiq/patches-3.3/{535-svip_cp1.patch => 0025-svip-cp1.patch} (57%) delete mode 100644 target/linux/lantiq/patches-3.3/0026-MIPS-lantiq-convert-falcon-gpio-to-clkdev-api.patch delete mode 100644 target/linux/lantiq/patches-3.3/0027-SERIAL-MIPS-lantiq-convert-serial-driver-to-clkdev-a.patch delete mode 100644 target/linux/lantiq/patches-3.3/0028-MIPS-lantiq-convert-falcon-debug-uart-to-clkdev-api.patch delete mode 100644 target/linux/lantiq/patches-3.3/0029-NET-MIPS-lantiq-convert-etop-driver-to-clkdev-api.patch delete mode 100644 target/linux/lantiq/patches-3.3/0030-WDT-MIPS-lantiq-convert-watchdog-driver-to-clkdev-ap.patch delete mode 100644 target/linux/lantiq/patches-3.3/0031-MIPS-lantiq-unify-xway-prom-code.patch delete mode 100644 target/linux/lantiq/patches-3.3/0032-MIPS-lantiq-add-vr9-support.patch delete mode 100644 target/linux/lantiq/patches-3.3/0033-MIPS-lantiq-add-ipi-handlers-to-make-vsmp-work.patch delete mode 100644 target/linux/lantiq/patches-3.3/0034-MIPS-lantiq-add-additional-soc-ids.patch delete mode 100644 target/linux/lantiq/patches-3.3/0035-SPI-MIPS-lantiq-add-FALC-ON-spi-driver.patch delete mode 100644 target/linux/lantiq/patches-3.3/0036-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch delete mode 100644 target/linux/lantiq/patches-3.3/0037-MIPS-lantiq-add-xway-nand-driver.patch delete mode 100644 target/linux/lantiq/patches-3.3/0038-SPI-MIPS-lantiq-adds-spi-xway.patch delete mode 100644 target/linux/lantiq/patches-3.3/0039-NET-adds-driver-for-lantiq-vr9-ethernet.patch delete mode 100644 target/linux/lantiq/patches-3.3/0040-MIPS-NET-several-fixes-to-etop-driver.patch delete mode 100644 target/linux/lantiq/patches-3.3/0041-MTD-MIPS-lantiq-use-module_platform_driver-inside-la.patch delete mode 100644 target/linux/lantiq/patches-3.3/0042-WDT-MIPS-lantiq-use-module_platform_driver-inside-la.patch delete mode 100644 target/linux/lantiq/patches-3.3/0043-MIPS-lantiq-adds-GPTU-driver.patch delete mode 100644 target/linux/lantiq/patches-3.3/0044-MIPS-lantiq-adds-dwc_otg.patch delete mode 100644 target/linux/lantiq/patches-3.3/0045-dwc_otg-remove-bogus-halt_channel.patch delete mode 100644 target/linux/lantiq/patches-3.3/0046-MIPS-adds-ifxhcd.patch delete mode 100644 target/linux/lantiq/patches-3.3/0047-MIPS-adds-gptu-driver.patch delete mode 100644 target/linux/lantiq/patches-3.3/0048-MIPS-lantiq-pci-rename-variable-inside.patch delete mode 100644 target/linux/lantiq/patches-3.3/0049-MIPS-lantiq-pci-give-xway-pci-support-its-own-kbuild.patch delete mode 100644 target/linux/lantiq/patches-3.3/0050-MIPS-lantiq-pci-move-pcibios-code-into-fixup-lantiq..patch delete mode 100644 target/linux/lantiq/patches-3.3/0051-MIPS-lantiq-pcie-add-pcie-driver.patch delete mode 100644 target/linux/lantiq/patches-3.3/0052-MIPS-lantiq-make-GPIO3-work-on-AR9.patch delete mode 100644 target/linux/lantiq/patches-3.3/0057-MIPS-clean-up-clock-code.patch delete mode 100644 target/linux/lantiq/patches-3.3/0058-MIPS-cleanup-reset-code.patch delete mode 100644 target/linux/lantiq/patches-3.3/0059-MIPS-lantiq-fixes-ar9-vr9-clock.patch delete mode 100644 target/linux/lantiq/patches-3.3/0060-MIPS-lantiq-fixes-danube-clock.patch delete mode 100644 target/linux/lantiq/patches-3.3/0061-MIPS-adds-dsl-clocks.patch delete mode 100644 target/linux/lantiq/patches-3.3/0062-MIPS-lantiq-dont-always-register-asc0.patch delete mode 100644 target/linux/lantiq/patches-3.3/0064-MIPS-lantiq-adds-bootsel-helper.patch delete mode 100644 target/linux/lantiq/patches-3.3/0065-MIPS-lantiq-adds-USB_ARCH_HAS_HCD-to-CONFIG_LANTIQ.patch delete mode 100644 target/linux/lantiq/patches-3.3/0066-MIPS-lantiq-fixes-bad-PMU_USB0-0-define.patch delete mode 100644 target/linux/lantiq/patches-3.3/0067-MIPS-lantiq-fix-dwc_otg-usb-for-ase.patch delete mode 100644 target/linux/lantiq/patches-3.3/0068-MIPS-lantiq-stp-fix-for-ase-add-get-clock-disabled.patch delete mode 100644 target/linux/lantiq/patches-3.3/0069-MIPS-lantiq-fix-spi-for-ase-update-for-clkdev-and-pl.patch delete mode 100644 target/linux/lantiq/patches-3.3/0070-icu-multi-base.patch delete mode 100644 target/linux/lantiq/patches-3.3/0072-fix_i2c_clock.patch delete mode 100644 target/linux/lantiq/patches-3.3/100-falcon_bsp_header.patch delete mode 100644 target/linux/lantiq/patches-3.3/101-sdk-compat.patch delete mode 100644 target/linux/lantiq/patches-3.3/105-falcon_header_update.patch delete mode 100644 target/linux/lantiq/patches-3.3/206-machtypes.patch delete mode 100644 target/linux/lantiq/patches-3.3/207-devices.patch delete mode 100644 target/linux/lantiq/patches-3.3/208-fix-mach-easy98000.patch delete mode 100644 target/linux/lantiq/patches-3.3/300-svip_header.patch delete mode 100644 target/linux/lantiq/patches-3.3/310-svip_board.patch diff --git a/target/linux/lantiq/files/arch/mips/configs/ase_defconfig b/target/linux/lantiq/files/arch/mips/configs/ase_defconfig new file mode 100644 index 0000000000..5bb1d93ebd --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/configs/ase_defconfig @@ -0,0 +1,67 @@ +CONFIG_LANTIQ=y +CONFIG_SOC_AMAZON_SE=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_EXPERIMENTAL=y +CONFIG_DEFAULT_HOSTNAME="amazon_se" +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="../root-lantiq/ ../root-lantiq/initramfs-base-files.txt" +CONFIG_INITRAMFS_ROOT_UID=1000 +CONFIG_INITRAMFS_ROOT_GID=1000 ++# CONFIG_RD_GZIP is not set +CONFIG_RD_LZMA=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_DEFAULT_DEADLINE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_ARPD=y +CONFIG_SYN_COOKIES=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=y +CONFIG_NET_SCHED=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_LANTIQ=y +CONFIG_MISC_DEVICES=y +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_LANTIQ_ETOP=y +CONFIG_PHYLIB=y +CONFIG_SERIAL_LANTIQ=y +CONFIG_PINCTRL=y +CONFIG_GPIO_SYSFS=y +CONFIG_WATCHDOG=y +CONFIG_LANTIQ_WDT=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_XZ=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_DEBUG_FS=y diff --git a/target/linux/lantiq/files/arch/mips/configs/falcon_defconfig b/target/linux/lantiq/files/arch/mips/configs/falcon_defconfig new file mode 100644 index 0000000000..ce242a88ed --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/configs/falcon_defconfig @@ -0,0 +1,72 @@ +CONFIG_LANTIQ=y +CONFIG_SOC_FALCON=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_EXPERIMENTAL=y +CONFIG_DEFAULT_HOSTNAME="falcon" +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="../root-lantiq/ ../root-lantiq/initramfs-base-files.txt" +CONFIG_INITRAMFS_ROOT_UID=1000 +CONFIG_INITRAMFS_ROOT_GID=1000 ++# CONFIG_RD_GZIP is not set +CONFIG_RD_LZMA=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_DEFAULT_DEADLINE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_ARPD=y +CONFIG_SYN_COOKIES=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=y +CONFIG_NET_SCHED=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_LANTIQ=y +CONFIG_MTD_M25P80=y +CONFIG_MISC_DEVICES=y +CONFIG_EEPROM_AT24=y +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_PHYLIB=y +CONFIG_SERIAL_LANTIQ=y +CONFIG_I2C=y +CONFIG_I2C_FALCON=y +CONFIG_SPI=y +CONFIG_SPI_FALCON=y +CONFIG_PINCTRL=y +CONFIG_GPIO_SYSFS=y +CONFIG_WATCHDOG=y +CONFIG_LANTIQ_WDT=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_XZ=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_DEBUG_FS=y diff --git a/target/linux/lantiq/files/arch/mips/configs/xway_defconfig b/target/linux/lantiq/files/arch/mips/configs/xway_defconfig new file mode 100644 index 0000000000..510a9641d3 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/configs/xway_defconfig @@ -0,0 +1,66 @@ +CONFIG_LANTIQ=y +CONFIG_CPU_MIPS32_R2=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_EXPERIMENTAL=y +CONFIG_DEFAULT_HOSTNAME="danube" +CONFIG_SYSVIPC=y +CONFIG_LOG_BUF_SHIFT=14 +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="../root-lantiq/ ../root-lantiq/initramfs-base-files.txt" +CONFIG_INITRAMFS_ROOT_UID=1000 +CONFIG_INITRAMFS_ROOT_GID=1000 +# CONFIG_RD_GZIP is not set +CONFIG_RD_LZMA=y +CONFIG_EMBEDDED=y +CONFIG_SLAB=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_DEFAULT_DEADLINE=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_ARPD=y +CONFIG_SYN_COOKIES=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE=m +CONFIG_VLAN_8021Q=y +CONFIG_NET_SCHED=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_GEOMETRY=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_LANTIQ=y +CONFIG_MISC_DEVICES=y +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_LANTIQ_ETOP=y +CONFIG_PHYLIB=y +CONFIG_SERIAL_LANTIQ=y +CONFIG_PINCTRL=y +CONFIG_GPIO_SYSFS=y +CONFIG_WATCHDOG=y +CONFIG_LANTIQ_WDT=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_XZ=y +CONFIG_STRIP_ASM_SYMS=y +CONFIG_DEBUG_FS=y diff --git a/target/linux/lantiq/files/arch/mips/include/asm/clkdev.h b/target/linux/lantiq/files/arch/mips/include/asm/clkdev.h new file mode 100644 index 0000000000..262475414e --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/clkdev.h @@ -0,0 +1,25 @@ +/* + * based on arch/arm/include/asm/clkdev.h + * + * Copyright (C) 2008 Russell King. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Helper for the clk API to assist looking up a struct clk. + */ +#ifndef __ASM_CLKDEV_H +#define __ASM_CLKDEV_H + +#include + +#define __clk_get(clk) ({ 1; }) +#define __clk_put(clk) do { } while (0) + +static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) +{ + return kzalloc(size, GFP_KERNEL); +} + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h new file mode 100644 index 0000000000..4dc6466e84 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h @@ -0,0 +1,268 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 Thomas Langer + */ + +#ifndef _FALCON_IRQ__ +#define _FALCON_IRQ__ + +#define INT_NUM_IRQ0 8 +#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) +#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32) +#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32) +#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32) +#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32) +#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32) +#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0) + +#define MIPS_CPU_TIMER_IRQ 7 + +/* HOST IF Event Interrupt */ +#define FALCON_IRQ_HOST (INT_NUM_IM0_IRL0 + 0) +/* HOST IF Mailbox0 Receive Interrupt */ +#define FALCON_IRQ_HOST_MB0_RX (INT_NUM_IM0_IRL0 + 1) +/* HOST IF Mailbox0 Transmit Interrupt */ +#define FALCON_IRQ_HOST_MB0_TX (INT_NUM_IM0_IRL0 + 2) +/* HOST IF Mailbox1 Receive Interrupt */ +#define FALCON_IRQ_HOST_MB1_RX (INT_NUM_IM0_IRL0 + 3) +/* HOST IF Mailbox1 Transmit Interrupt */ +#define FALCON_IRQ_HOST_MB1_TX (INT_NUM_IM0_IRL0 + 4) +/* I2C Last Single Data Transfer Request */ +#define FALCON_IRQ_I2C_LSREQ (INT_NUM_IM0_IRL0 + 8) +/* I2C Single Data Transfer Request */ +#define FALCON_IRQ_I2C_SREQ (INT_NUM_IM0_IRL0 + 9) +/* I2C Last Burst Data Transfer Request */ +#define FALCON_IRQ_I2C_LBREQ (INT_NUM_IM0_IRL0 + 10) +/* I2C Burst Data Transfer Request */ +#define FALCON_IRQ_I2C_BREQ (INT_NUM_IM0_IRL0 + 11) +/* I2C Error Interrupt */ +#define FALCON_IRQ_I2C_I2C_ERR (INT_NUM_IM0_IRL0 + 12) +/* I2C Protocol Interrupt */ +#define FALCON_IRQ_I2C_I2C_P (INT_NUM_IM0_IRL0 + 13) +/* SSC Transmit Interrupt */ +#define FALCON_IRQ_SSC_T (INT_NUM_IM0_IRL0 + 14) +/* SSC Receive Interrupt */ +#define FALCON_IRQ_SSC_R (INT_NUM_IM0_IRL0 + 15) +/* SSC Error Interrupt */ +#define FALCON_IRQ_SSC_E (INT_NUM_IM0_IRL0 + 16) +/* SSC Frame Interrupt */ +#define FALCON_IRQ_SSC_F (INT_NUM_IM0_IRL0 + 17) +/* Advanced Encryption Standard Interrupt */ +#define FALCON_IRQ_AES_AES (INT_NUM_IM0_IRL0 + 27) +/* Secure Hash Algorithm Interrupt */ +#define FALCON_IRQ_SHA_HASH (INT_NUM_IM0_IRL0 + 28) +/* PCM Receive Interrupt */ +#define FALCON_IRQ_PCM_RX (INT_NUM_IM0_IRL0 + 29) +/* PCM Transmit Interrupt */ +#define FALCON_IRQ_PCM_TX (INT_NUM_IM0_IRL0 + 30) +/* PCM Transmit Crash Interrupt */ +#define FALCON_IRQ_PCM_HW2_CRASH (INT_NUM_IM0_IRL0 + 31) + +/* EBU Serial Flash Command Error */ +#define FALCON_IRQ_EBU_SF_CMDERR (INT_NUM_IM1_IRL0 + 0) +/* EBU Serial Flash Command Overwrite Error */ +#define FALCON_IRQ_EBU_SF_COVERR (INT_NUM_IM1_IRL0 + 1) +/* EBU Serial Flash Busy */ +#define FALCON_IRQ_EBU_SF_BUSY (INT_NUM_IM1_IRL0 + 2) +/* External Interrupt from GPIO P0 */ +#define FALCON_IRQ_GPIO_P0 (INT_NUM_IM1_IRL0 + 4) +/* External Interrupt from GPIO P1 */ +#define FALCON_IRQ_GPIO_P1 (INT_NUM_IM1_IRL0 + 5) +/* External Interrupt from GPIO P2 */ +#define FALCON_IRQ_GPIO_P2 (INT_NUM_IM1_IRL0 + 6) +/* External Interrupt from GPIO P3 */ +#define FALCON_IRQ_GPIO_P3 (INT_NUM_IM1_IRL0 + 7) +/* External Interrupt from GPIO P4 */ +#define FALCON_IRQ_GPIO_P4 (INT_NUM_IM1_IRL0 + 8) +/* 8kHz backup interrupt derived from core-PLL */ +#define FALCON_IRQ_FSC_BKP (INT_NUM_IM1_IRL0 + 10) +/* FSC Timer Interrupt 0 */ +#define FALCON_IRQ_FSCT_CMP0 (INT_NUM_IM1_IRL0 + 11) +/* FSC Timer Interrupt 1 */ +#define FALCON_IRQ_FSCT_CMP1 (INT_NUM_IM1_IRL0 + 12) +/* 8kHz root interrupt derived from GPON interface */ +#define FALCON_IRQ_FSC_ROOT (INT_NUM_IM1_IRL0 + 13) +/* Time of Day */ +#define FALCON_IRQ_TOD (INT_NUM_IM1_IRL0 + 14) +/* PMA Interrupt from IntNode of the 200MHz Domain */ +#define FALCON_IRQ_PMA_200M (INT_NUM_IM1_IRL0 + 15) +/* PMA Interrupt from IntNode of the TX Clk Domain */ +#define FALCON_IRQ_PMA_TX (INT_NUM_IM1_IRL0 + 16) +/* PMA Interrupt from IntNode of the RX Clk Domain */ +#define FALCON_IRQ_PMA_RX (INT_NUM_IM1_IRL0 + 17) +/* SYS1 Interrupt */ +#define FALCON_IRQ_SYS1 (INT_NUM_IM1_IRL0 + 20) +/* SYS GPE Interrupt */ +#define FALCON_IRQ_SYS_GPE (INT_NUM_IM1_IRL0 + 21) +/* Watchdog Access Error Interrupt */ +#define FALCON_IRQ_WDT_AEIR (INT_NUM_IM1_IRL0 + 24) +/* Watchdog Prewarning Interrupt */ +#define FALCON_IRQ_WDT_PIR (INT_NUM_IM1_IRL0 + 25) +/* SBIU interrupt */ +#define FALCON_IRQ_SBIU0 (INT_NUM_IM1_IRL0 + 27) +/* FPI Bus Control Unit Interrupt */ +#define FALCON_IRQ_BCU0 (INT_NUM_IM1_IRL0 + 29) +/* DDR Controller Interrupt */ +#define FALCON_IRQ_DDR (INT_NUM_IM1_IRL0 + 30) +/* Crossbar Error Interrupt */ +#define FALCON_IRQ_XBAR_ERROR (INT_NUM_IM1_IRL0 + 31) + +/* ICTRLL 0 Interrupt */ +#define FALCON_IRQ_ICTRLL0 (INT_NUM_IM2_IRL0 + 0) +/* ICTRLL 1 Interrupt */ +#define FALCON_IRQ_ICTRLL1 (INT_NUM_IM2_IRL0 + 1) +/* ICTRLL 2 Interrupt */ +#define FALCON_IRQ_ICTRLL2 (INT_NUM_IM2_IRL0 + 2) +/* ICTRLL 3 Interrupt */ +#define FALCON_IRQ_ICTRLL3 (INT_NUM_IM2_IRL0 + 3) +/* OCTRLL 0 Interrupt */ +#define FALCON_IRQ_OCTRLL0 (INT_NUM_IM2_IRL0 + 4) +/* OCTRLL 1 Interrupt */ +#define FALCON_IRQ_OCTRLL1 (INT_NUM_IM2_IRL0 + 5) +/* OCTRLL 2 Interrupt */ +#define FALCON_IRQ_OCTRLL2 (INT_NUM_IM2_IRL0 + 6) +/* OCTRLL 3 Interrupt */ +#define FALCON_IRQ_OCTRLL3 (INT_NUM_IM2_IRL0 + 7) +/* OCTRLG Interrupt */ +#define FALCON_IRQ_OCTRLG (INT_NUM_IM2_IRL0 + 9) +/* IQM Interrupt */ +#define FALCON_IRQ_IQM (INT_NUM_IM2_IRL0 + 10) +/* FSQM Interrupt */ +#define FALCON_IRQ_FSQM (INT_NUM_IM2_IRL0 + 11) +/* TMU Interrupt */ +#define FALCON_IRQ_TMU (INT_NUM_IM2_IRL0 + 12) +/* LINK1 Interrupt */ +#define FALCON_IRQ_LINK1 (INT_NUM_IM2_IRL0 + 14) +/* ICTRLC 0 Interrupt */ +#define FALCON_IRQ_ICTRLC0 (INT_NUM_IM2_IRL0 + 16) +/* ICTRLC 1 Interrupt */ +#define FALCON_IRQ_ICTRLC1 (INT_NUM_IM2_IRL0 + 17) +/* OCTRLC Interrupt */ +#define FALCON_IRQ_OCTRLC (INT_NUM_IM2_IRL0 + 18) +/* CONFIG Break Interrupt */ +#define FALCON_IRQ_CONFIG_BREAK (INT_NUM_IM2_IRL0 + 19) +/* CONFIG Interrupt */ +#define FALCON_IRQ_CONFIG (INT_NUM_IM2_IRL0 + 20) +/* Dispatcher Interrupt */ +#define FALCON_IRQ_DISP (INT_NUM_IM2_IRL0 + 21) +/* TBM Interrupt */ +#define FALCON_IRQ_TBM (INT_NUM_IM2_IRL0 + 22) +/* GTC Downstream Interrupt */ +#define FALCON_IRQ_GTC_DS (INT_NUM_IM2_IRL0 + 29) +/* GTC Upstream Interrupt */ +#define FALCON_IRQ_GTC_US (INT_NUM_IM2_IRL0 + 30) +/* EIM Interrupt */ +#define FALCON_IRQ_EIM (INT_NUM_IM2_IRL0 + 31) + +/* ASC0 Transmit Interrupt */ +#define FALCON_IRQ_ASC0_T (INT_NUM_IM3_IRL0 + 0) +/* ASC0 Receive Interrupt */ +#define FALCON_IRQ_ASC0_R (INT_NUM_IM3_IRL0 + 1) +/* ASC0 Error Interrupt */ +#define FALCON_IRQ_ASC0_E (INT_NUM_IM3_IRL0 + 2) +/* ASC0 Transmit Buffer Interrupt */ +#define FALCON_IRQ_ASC0_TB (INT_NUM_IM3_IRL0 + 3) +/* ASC0 Autobaud Start Interrupt */ +#define FALCON_IRQ_ASC0_ABST (INT_NUM_IM3_IRL0 + 4) +/* ASC0 Autobaud Detection Interrupt */ +#define FALCON_IRQ_ASC0_ABDET (INT_NUM_IM3_IRL0 + 5) +/* ASC1 Modem Status Interrupt */ +#define FALCON_IRQ_ASC0_MS (INT_NUM_IM3_IRL0 + 6) +/* ASC0 Soft Flow Control Interrupt */ +#define FALCON_IRQ_ASC0_SFC (INT_NUM_IM3_IRL0 + 7) +/* ASC1 Transmit Interrupt */ +#define FALCON_IRQ_ASC1_T (INT_NUM_IM3_IRL0 + 8) +/* ASC1 Receive Interrupt */ +#define FALCON_IRQ_ASC1_R (INT_NUM_IM3_IRL0 + 9) +/* ASC1 Error Interrupt */ +#define FALCON_IRQ_ASC1_E (INT_NUM_IM3_IRL0 + 10) +/* ASC1 Transmit Buffer Interrupt */ +#define FALCON_IRQ_ASC1_TB (INT_NUM_IM3_IRL0 + 11) +/* ASC1 Autobaud Start Interrupt */ +#define FALCON_IRQ_ASC1_ABST (INT_NUM_IM3_IRL0 + 12) +/* ASC1 Autobaud Detection Interrupt */ +#define FALCON_IRQ_ASC1_ABDET (INT_NUM_IM3_IRL0 + 13) +/* ASC1 Modem Status Interrupt */ +#define FALCON_IRQ_ASC1_MS (INT_NUM_IM3_IRL0 + 14) +/* ASC1 Soft Flow Control Interrupt */ +#define FALCON_IRQ_ASC1_SFC (INT_NUM_IM3_IRL0 + 15) +/* GPTC Timer/Counter 1A Interrupt */ +#define FALCON_IRQ_GPTC_TC1A (INT_NUM_IM3_IRL0 + 16) +/* GPTC Timer/Counter 1B Interrupt */ +#define FALCON_IRQ_GPTC_TC1B (INT_NUM_IM3_IRL0 + 17) +/* GPTC Timer/Counter 2A Interrupt */ +#define FALCON_IRQ_GPTC_TC2A (INT_NUM_IM3_IRL0 + 18) +/* GPTC Timer/Counter 2B Interrupt */ +#define FALCON_IRQ_GPTC_TC2B (INT_NUM_IM3_IRL0 + 19) +/* GPTC Timer/Counter 3A Interrupt */ +#define FALCON_IRQ_GPTC_TC3A (INT_NUM_IM3_IRL0 + 20) +/* GPTC Timer/Counter 3B Interrupt */ +#define FALCON_IRQ_GPTC_TC3B (INT_NUM_IM3_IRL0 + 21) +/* DFEV0, Channel 1 Transmit Interrupt */ +#define FALCON_IRQ_DFEV0_2TX (INT_NUM_IM3_IRL0 + 26) +/* DFEV0, Channel 1 Receive Interrupt */ +#define FALCON_IRQ_DFEV0_2RX (INT_NUM_IM3_IRL0 + 27) +/* DFEV0, Channel 1 General Purpose Interrupt */ +#define FALCON_IRQ_DFEV0_2GP (INT_NUM_IM3_IRL0 + 28) +/* DFEV0, Channel 0 Transmit Interrupt */ +#define FALCON_IRQ_DFEV0_1TX (INT_NUM_IM3_IRL0 + 29) +/* DFEV0, Channel 0 Receive Interrupt */ +#define FALCON_IRQ_DFEV0_1RX (INT_NUM_IM3_IRL0 + 30) +/* DFEV0, Channel 0 General Purpose Interrupt */ +#define FALCON_IRQ_DFEV0_1GP (INT_NUM_IM3_IRL0 + 31) + +/* ICTRLL 0 Error */ +#define FALCON_IRQ_ICTRLL0_ERR (INT_NUM_IM4_IRL0 + 0) +/* ICTRLL 1 Error */ +#define FALCON_IRQ_ICTRLL1_ERR (INT_NUM_IM4_IRL0 + 1) +/* ICTRLL 2 Error */ +#define FALCON_IRQ_ICTRLL2_ERR (INT_NUM_IM4_IRL0 + 2) +/* ICTRLL 3 Error */ +#define FALCON_IRQ_ICTRLL3_ERR (INT_NUM_IM4_IRL0 + 3) +/* OCTRLL 0 Error */ +#define FALCON_IRQ_OCTRLL0_ERR (INT_NUM_IM4_IRL0 + 4) +/* OCTRLL 1 Error */ +#define FALCON_IRQ_OCTRLL1_ERR (INT_NUM_IM4_IRL0 + 5) +/* OCTRLL 2 Error */ +#define FALCON_IRQ_OCTRLL2_ERR (INT_NUM_IM4_IRL0 + 6) +/* OCTRLL 3 Error */ +#define FALCON_IRQ_OCTRLL3_ERR (INT_NUM_IM4_IRL0 + 7) +/* ICTRLG Error */ +#define FALCON_IRQ_ICTRLG_ERR (INT_NUM_IM4_IRL0 + 8) +/* OCTRLG Error */ +#define FALCON_IRQ_OCTRLG_ERR (INT_NUM_IM4_IRL0 + 9) +/* IQM Error */ +#define FALCON_IRQ_IQM_ERR (INT_NUM_IM4_IRL0 + 10) +/* FSQM Error */ +#define FALCON_IRQ_FSQM_ERR (INT_NUM_IM4_IRL0 + 11) +/* TMU Error */ +#define FALCON_IRQ_TMU_ERR (INT_NUM_IM4_IRL0 + 12) +/* MPS Status Interrupt #0 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR0 (INT_NUM_IM4_IRL0 + 14) +/* MPS Status Interrupt #1 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR1 (INT_NUM_IM4_IRL0 + 15) +/* MPS Status Interrupt #2 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR2 (INT_NUM_IM4_IRL0 + 16) +/* MPS Status Interrupt #3 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR3 (INT_NUM_IM4_IRL0 + 17) +/* MPS Status Interrupt #4 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR4 (INT_NUM_IM4_IRL0 + 18) +/* MPS Status Interrupt #5 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR5 (INT_NUM_IM4_IRL0 + 19) +/* MPS Status Interrupt #6 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR6 (INT_NUM_IM4_IRL0 + 20) +/* MPS Status Interrupt #7 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR7 (INT_NUM_IM4_IRL0 + 21) +/* MPS Status Interrupt #8 (VPE1 to VPE0) */ +#define FALCON_IRQ_MPS_IR8 (INT_NUM_IM4_IRL0 + 22) +/* VPE0 Exception Level Flag Interrupt */ +#define FALCON_IRQ_VPE0_EXL (INT_NUM_IM4_IRL0 + 29) +/* VPE0 Error Level Flag Interrupt */ +#define FALCON_IRQ_VPE0_ERL (INT_NUM_IM4_IRL0 + 30) +/* VPE0 Performance Monitoring Counter Interrupt */ +#define FALCON_IRQ_VPE0_PMCIR (INT_NUM_IM4_IRL0 + 31) + +#endif /* _FALCON_IRQ__ */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/irq.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/irq.h new file mode 100644 index 0000000000..2caccd9f9d --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/irq.h @@ -0,0 +1,18 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + */ + +#ifndef __FALCON_IRQ_H +#define __FALCON_IRQ_H + +#include + +#define NR_IRQS 328 + +#include_next + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h new file mode 100644 index 0000000000..fff5ecdbea --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h @@ -0,0 +1,152 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LTQ_FALCON_H__ +#define _LTQ_FALCON_H__ + +#ifdef CONFIG_SOC_FALCON + +#include + +/* Chip IDs */ +#define SOC_ID_FALCON 0x01B8 + +/* SoC Types */ +#define SOC_TYPE_FALCON 0x01 + +/* ASC0/1 - serial port */ +#define LTQ_ASC0_BASE_ADDR 0x1E100C00 +#define LTQ_ASC1_BASE_ADDR 0x1E100B00 +#define LTQ_ASC_SIZE 0x100 + +#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8)) +#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1) +#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2) + +/* + * during early_printk no ioremap possible at this early stage + * lets use KSEG1 instead + */ +#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR) + +/* ICU - interrupt control unit */ +#define LTQ_ICU_BASE_ADDR 0x1F880200 +#define LTQ_ICU_SIZE 0x100 + +/* WDT */ +#define LTQ_WDT_BASE_ADDR 0x1F8803F0 +#define LTQ_WDT_SIZE 0x10 + +#define LTQ_RST_CAUSE_WDTRST 0x0002 + +/* EBU - external bus unit */ +#define LTQ_EBU_BASE_ADDR 0x18000000 +#define LTQ_EBU_SIZE 0x0100 + +#define LTQ_EBU_MODCON 0x000C + +/* GPIO */ +#define LTQ_GPIO0_BASE_ADDR 0x1D810000 +#define LTQ_GPIO0_SIZE 0x0080 +#define LTQ_GPIO1_BASE_ADDR 0x1E800100 +#define LTQ_GPIO1_SIZE 0x0080 +#define LTQ_GPIO2_BASE_ADDR 0x1D810100 +#define LTQ_GPIO2_SIZE 0x0080 +#define LTQ_GPIO3_BASE_ADDR 0x1E800200 +#define LTQ_GPIO3_SIZE 0x0080 +#define LTQ_GPIO4_BASE_ADDR 0x1E800300 +#define LTQ_GPIO4_SIZE 0x0080 +#define LTQ_PADCTRL0_BASE_ADDR 0x1DB01000 +#define LTQ_PADCTRL0_SIZE 0x0100 +#define LTQ_PADCTRL1_BASE_ADDR 0x1E800400 +#define LTQ_PADCTRL1_SIZE 0x0100 +#define LTQ_PADCTRL2_BASE_ADDR 0x1DB02000 +#define LTQ_PADCTRL2_SIZE 0x0100 +#define LTQ_PADCTRL3_BASE_ADDR 0x1E800500 +#define LTQ_PADCTRL3_SIZE 0x0100 +#define LTQ_PADCTRL4_BASE_ADDR 0x1E800600 +#define LTQ_PADCTRL4_SIZE 0x0100 + +/* I2C */ +#define GPON_I2C_BASE 0x1E200000 +#define GPON_I2C_SIZE 0x00010000 + +/* CHIP ID */ +#define LTQ_STATUS_BASE_ADDR 0x1E802000 + +#define LTQ_FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c)) +#define LTQ_FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38)) +#define LTQ_FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40)) + +/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */ +#define LTQ_SYS1_BASE_ADDR 0x1EF00000 +#define LTQ_SYS1_SIZE 0x0100 +#define LTQ_STATUS_BASE_ADDR 0x1E802000 +#define LTQ_STATUS_SIZE 0x0080 +#define LTQ_SYS_ETH_BASE_ADDR 0x1DB00000 +#define LTQ_SYS_ETH_SIZE 0x0100 +#define LTQ_SYS_GPE_BASE_ADDR 0x1D700000 +#define LTQ_SYS_GPE_SIZE 0x0100 + +#define SYSCTL_SYS1 0 +#define SYSCTL_SYSETH 1 +#define SYSCTL_SYSGPE 2 + +/* Activation Status Register */ +#define ACTS_ASC1_ACT 0x00000800 +#define ACTS_I2C_ACT 0x00004000 +#define ACTS_P0 0x00010000 +#define ACTS_P1 0x00010000 +#define ACTS_P2 0x00020000 +#define ACTS_P3 0x00020000 +#define ACTS_P4 0x00040000 +#define ACTS_PADCTRL0 0x00100000 +#define ACTS_PADCTRL1 0x00100000 +#define ACTS_PADCTRL2 0x00200000 +#define ACTS_PADCTRL3 0x00200000 +#define ACTS_PADCTRL4 0x00400000 +#define ACTS_I2C_ACT 0x00004000 + +/* global register ranges */ +extern __iomem void *ltq_ebu_membase; +extern __iomem void *ltq_sys1_membase; +#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) +#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) +#define ltq_ebu_w32_mask(clear, set, reg) \ + ltq_ebu_w32((ltq_ebu_r32(reg) & ~(clear)) | (set), reg) + +#define ltq_sys1_w32(x, y) ltq_w32((x), ltq_sys1_membase + (y)) +#define ltq_sys1_r32(x) ltq_r32(ltq_sys1_membase + (x)) +#define ltq_sys1_w32_mask(clear, set, reg) \ + ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg) + +/* gpio wrapper to help configure the pin muxing */ +extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux); + +/* to keep the irq code generic we need to define these to 0 as falcon + has no EIU/EBU */ +#define LTQ_EIU_BASE_ADDR 0 +#define LTQ_EBU_PCC_ISTAT 0 + +static inline int ltq_is_ar9(void) +{ + return 0; +} + +static inline int ltq_is_vr9(void) +{ + return 0; +} + +static inline int ltq_is_falcon(void) +{ + return 1; +} + +#endif /* CONFIG_SOC_FALCON */ +#endif /* _LTQ_XWAY_H__ */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/lantiq_timer.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/lantiq_timer.h new file mode 100644 index 0000000000..ef564abc3a --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/lantiq_timer.h @@ -0,0 +1,155 @@ +#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ +#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ + + +/****************************************************************************** + Copyright (c) 2002, Infineon Technologies. All rights reserved. + + No Warranty + Because the program is licensed free of charge, there is no warranty for + the program, to the extent permitted by applicable law. Except when + otherwise stated in writing the copyright holders and/or other parties + provide the program "as is" without warranty of any kind, either + expressed or implied, including, but not limited to, the implied + warranties of merchantability and fitness for a particular purpose. The + entire risk as to the quality and performance of the program is with + you. should the program prove defective, you assume the cost of all + necessary servicing, repair or correction. + + In no event unless required by applicable law or agreed to in writing + will any copyright holder, or any other party who may modify and/or + redistribute the program as permitted above, be liable to you for + damages, including any general, special, incidental or consequential + damages arising out of the use or inability to use the program + (including but not limited to loss of data or data being rendered + inaccurate or losses sustained by you or third parties or a failure of + the program to operate with any other programs), even if such holder or + other party has been advised of the possibility of such damages. +******************************************************************************/ + + +/* + * #################################### + * Definition + * #################################### + */ + +/* + * Available Timer/Counter Index + */ +#define TIMER(n, X) (n * 2 + (X ? 1 : 0)) +#define TIMER_ANY 0x00 +#define TIMER1A TIMER(1, 0) +#define TIMER1B TIMER(1, 1) +#define TIMER2A TIMER(2, 0) +#define TIMER2B TIMER(2, 1) +#define TIMER3A TIMER(3, 0) +#define TIMER3B TIMER(3, 1) + +/* + * Flag of Timer/Counter + * These flags specify the way in which timer is configured. + */ +/* Bit size of timer/counter. */ +#define TIMER_FLAG_16BIT 0x0000 +#define TIMER_FLAG_32BIT 0x0001 +/* Switch between timer and counter. */ +#define TIMER_FLAG_TIMER 0x0000 +#define TIMER_FLAG_COUNTER 0x0002 +/* Stop or continue when overflowing/underflowing. */ +#define TIMER_FLAG_ONCE 0x0000 +#define TIMER_FLAG_CYCLIC 0x0004 +/* Count up or counter down. */ +#define TIMER_FLAG_UP 0x0000 +#define TIMER_FLAG_DOWN 0x0008 +/* Count on specific level or edge. */ +#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000 +#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040 +#define TIMER_FLAG_RISE_EDGE 0x0010 +#define TIMER_FLAG_FALL_EDGE 0x0020 +#define TIMER_FLAG_ANY_EDGE 0x0030 +/* Signal is syncronous to module clock or not. */ +#define TIMER_FLAG_UNSYNC 0x0000 +#define TIMER_FLAG_SYNC 0x0080 +/* Different interrupt handle type. */ +#define TIMER_FLAG_NO_HANDLE 0x0000 +#if defined(__KERNEL__) + #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100 +#endif // defined(__KERNEL__) +#define TIMER_FLAG_SIGNAL 0x0300 +/* Internal clock source or external clock source */ +#define TIMER_FLAG_INT_SRC 0x0000 +#define TIMER_FLAG_EXT_SRC 0x1000 + + +/* + * ioctl Command + */ +#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */ +#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */ +#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */ +#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */ +#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */ +#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/ +#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */ +#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */ + +/* + * Data Type Used to Call ioctl + */ +struct gptu_ioctl_param { + unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * + * GPTU_SET_COUNTER, this field is ID of expected * + * timer/counter. If it's zero, a timer/counter would * + * be dynamically allocated and ID would be stored in * + * this field. * + * In command GPTU_GET_COUNT_VALUE, this field is * + * ignored. * + * In other command, this field is ID of timer/counter * + * allocated. */ + unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * + * GPTU_SET_COUNTER, this field contains flags to * + * specify how to configure timer/counter. * + * In command GPTU_START_TIMER, zero indicate start * + * and non-zero indicate resume timer/counter. * + * In other command, this field is ignored. */ + unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains * + * init/reload value. * + * In command GPTU_SET_TIMER, this field contains * + * frequency (0.001Hz) of timer. * + * In command GPTU_GET_COUNT_VALUE, current count * + * value would be stored in this field. * + * In command GPTU_CALCULATE_DIVIDER, this field * + * contains frequency wanted, and after calculation, * + * divider would be stored in this field to overwrite * + * the frequency. * + * In other command, this field is ignored. */ + int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * + * if signal is required, this field contains process * + * ID to which signal would be sent. * + * In other command, this field is ignored. */ + int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * + * if signal is required, this field contains signal * + * number which would be sent. * + * In other command, this field is ignored. */ +}; + +/* + * #################################### + * Data Type + * #################################### + */ +typedef void (*timer_callback)(unsigned long arg); + +extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long); +extern int lq_free_timer(unsigned int); +extern int lq_start_timer(unsigned int, int); +extern int lq_stop_timer(unsigned int); +extern int lq_reset_counter_flags(u32 timer, u32 flags); +extern int lq_get_count_value(unsigned int, unsigned long *); +extern u32 lq_cal_divider(unsigned long); +extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long); +extern int lq_set_counter(unsigned int timer, unsigned int flag, + u32 reload, unsigned long arg1, unsigned long arg2); + +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/base_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/base_reg.h new file mode 100644 index 0000000000..8149f1204e --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/base_reg.h @@ -0,0 +1,56 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __BASE_REG_H +#define __BASE_REG_H + +#ifndef KSEG1 +#define KSEG1 0xA0000000 +#endif + +#define LTQ_EBU_SEG1_BASE (KSEG1 + 0x10000000) +#define LTQ_EBU_SEG2_BASE (KSEG1 + 0x11000000) +#define LTQ_EBU_SEG3_BASE (KSEG1 + 0x12000000) +#define LTQ_EBU_SEG4_BASE (KSEG1 + 0x13000000) + +#define LTQ_ASC0_BASE (KSEG1 + 0x14100100) +#define LTQ_ASC1_BASE (KSEG1 + 0x14100200) + +#define LTQ_SSC0_BASE (0x14100300) +#define LTQ_SSC1_BASE (0x14100400) + +#define LTQ_PORT_P0_BASE (KSEG1 + 0x14100600) +#define LTQ_PORT_P1_BASE (KSEG1 + 0x14108100) +#define LTQ_PORT_P2_BASE (KSEG1 + 0x14100800) +#define LTQ_PORT_P3_BASE (KSEG1 + 0x14100900) +#define LTQ_PORT_P4_BASE (KSEG1 + 0x1E000400) + +#define LTQ_EBU_BASE (KSEG1 + 0x14102000) +#define LTQ_DMA_BASE (KSEG1 + 0x14104000) + +#define LTQ_ICU0_IM3_IM2_BASE (KSEG1 + 0x1E016000) +#define LTQ_ICU0_IM5_IM4_IM1_IM0_BASE (KSEG1 + 0x14106000) + +#define LTQ_ES_BASE (KSEG1 + 0x18000000) + +#define LTQ_SYS0_BASE (KSEG1 + 0x1C000000) +#define LTQ_SYS1_BASE (KSEG1 + 0x1C000800) +#define LTQ_SYS2_BASE (KSEG1 + 0x1E400000) + +#define LTQ_L2_SPRAM_BASE (KSEG1 + 0x1F1E8000) + +#define LTQ_SWINT_BASE (KSEG1 + 0x1E000100) +#define LTQ_MBS_BASE (KSEG1 + 0x1E000200) + +#define LTQ_STATUS_BASE (KSEG1 + 0x1E000500) + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/boot_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/boot_reg.h new file mode 100644 index 0000000000..9c33516e8a --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/boot_reg.h @@ -0,0 +1,37 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + +******************************************************************************/ + +#ifndef __BOOT_REG_H +#define __BOOT_REG_H + +#define LTQ_BOOT_CPU_OFFSET 0x20 + +#define LTQ_BOOT_RVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ + (cpu * LTQ_BOOT_CPU_OFFSET) + 0x00) +#define LTQ_BOOT_NVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ + (cpu * LTQ_BOOT_CPU_OFFSET) + 0x04) +#define LTQ_BOOT_EVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ + (cpu * LTQ_BOOT_CPU_OFFSET) + 0x08) +#define LTQ_BOOT_CP0_STATUS(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ + (cpu * LTQ_BOOT_CPU_OFFSET) + 0x0C) +#define LTQ_BOOT_CP0_EPC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ + (cpu * LTQ_BOOT_CPU_OFFSET) + 0x10) +#define LTQ_BOOT_CP0_EEPC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ + (cpu * LTQ_BOOT_CPU_OFFSET) + 0x14) +#define LTQ_BOOT_SIZE(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ + (cpu * LTQ_BOOT_CPU_OFFSET) + 0x18) /* only for CP1 */ +#define LTQ_BOOT_RCU_SR(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ + (cpu * LTQ_BOOT_CPU_OFFSET) + 0x18) /* only for CP0 */ +#define LTQ_BOOT_CFG_STAT(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ + (cpu * LTQ_BOOT_CPU_OFFSET) + 0x1C) + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/dma_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/dma_reg.h new file mode 100644 index 0000000000..9fde2f6dd3 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/dma_reg.h @@ -0,0 +1,308 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __DMA_REG_H +#define __DMA_REG_H + +#define dma_r32(reg) ltq_r32(&dma->reg) +#define dma_w32(val, reg) ltq_w32(val, &dma->reg) +#define dma_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &dma->reg) + +/** DMA register structure */ +struct svip_reg_dma { + volatile unsigned long clc; /* 0x00 */ + volatile unsigned long reserved0; /* 0x04 */ + volatile unsigned long id; /* 0x08 */ + volatile unsigned long reserved1; /* 0x0c */ + volatile unsigned long ctrl; /* 0x10 */ + volatile unsigned long cpoll; /* 0x14 */ + volatile unsigned long cs; /* 0x18 */ + volatile unsigned long cctrl; /* 0x1C */ + volatile unsigned long cdba; /* 0x20 */ + volatile unsigned long cdlen; /* 0x24 */ + volatile unsigned long cis; /* 0x28 */ + volatile unsigned long cie; /* 0x2C */ + volatile unsigned long cgbl; /* 0x30 */ + volatile unsigned long reserved2[3]; /* 0x34 */ + volatile unsigned long ps; /* 0x40 */ + volatile unsigned long pctrl; /* 0x44 */ + volatile unsigned long reserved3[43]; /* 0x48 */ + volatile unsigned long irnen; /* 0xF4 */ + volatile unsigned long irncr; /* 0xF8 */ + volatile unsigned long irnicr; /* 0xFC */ +}; + +/******************************************************************************* + * CLC Register + ******************************************************************************/ + +/* Fast Shut-Off Enable Bit (5) */ +#define DMA_CLC_FSOE (0x1 << 5) +#define DMA_CLC_FSOE_VAL(val) (((val) & 0x1) << 5) +#define DMA_CLC_FSOE_GET(val) ((((val) & DMA_CLC_FSOE) >> 5) & 0x1) +#define DMA_CLC_FSOE_SET(reg,val) (reg) = ((reg & ~DMA_CLC_FSOE) | (((val) & 0x1) << 5)) +/* Suspend Bit Write Enable for OCDS (4) */ +#define DMA_CLC_SBWE (0x1 << 4) +#define DMA_CLC_SBWE_VAL(val) (((val) & 0x1) << 4) +#define DMA_CLC_SBWE_SET(reg,val) (reg) = (((reg & ~DMA_CLC_SBWE) | (val) & 1) << 4) +/* External Request Disable (3) */ +#define DMA_CLC_EDIS (0x1 << 3) +#define DMA_CLC_EDIS_VAL(val) (((val) & 0x1) << 3) +#define DMA_CLC_EDIS_GET(val) ((((val) & DMA_CLC_EDIS) >> 3) & 0x1) +#define DMA_CLC_EDIS_SET(reg,val) (reg) = ((reg & ~DMA_CLC_EDIS) | (((val) & 0x1) << 3)) +/* Suspend Enable Bit for OCDS (2) */ +#define DMA_CLC_SPEN (0x1 << 2) +#define DMA_CLC_SPEN_VAL(val) (((val) & 0x1) << 2) +#define DMA_CLC_SPEN_GET(val) ((((val) & DMA_CLC_SPEN) >> 2) & 0x1) +#define DMA_CLC_SPEN_SET(reg,val) (reg) = ((reg & ~DMA_CLC_SPEN) | (((val) & 0x1) << 2)) +/* Disable Status Bit (1) */ +#define DMA_CLC_DISS (0x1 << 1) +#define DMA_CLC_DISS_GET(val) ((((val) & DMA_CLC_DISS) >> 1) & 0x1) +/* Disable Request Bit (0) */ +#define DMA_CLC_DISR (0x1) +#define DMA_CLC_DISR_VAL(val) (((val) & 0x1) << 0) +#define DMA_CLC_DISR_GET(val) ((((val) & DMA_CLC_DISR) >> 0) & 0x1) +#define DMA_CLC_DISR_SET(reg,val) (reg) = ((reg & ~DMA_CLC_DISR) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * ID Register + ******************************************************************************/ + +/* Number of Channels (25:20) */ +#define DMA_ID_CHNR (0x3f << 20) +#define DMA_ID_CHNR_GET(val) ((((val) & DMA_ID_CHNR) >> 20) & 0x3f) +/* Number of Ports (19:16) */ +#define DMA_ID_PRTNR (0xf << 16) +#define DMA_ID_PRTNR_GET(val) ((((val) & DMA_ID_PRTNR) >> 16) & 0xf) +/* Module ID (15:8) */ +#define DMA_ID_ID (0xff << 8) +#define DMA_ID_ID_GET(val) ((((val) & DMA_ID_ID) >> 8) & 0xff) +/* Revision (4:0) */ +#define DMA_ID_REV (0x1f) +#define DMA_ID_REV_GET(val) ((((val) & DMA_ID_REV) >> 0) & 0x1f) + +/******************************************************************************* + * Control Register + ******************************************************************************/ + +/* Global Software Reset (0) */ +#define DMA_CTRL_RST (0x1) +#define DMA_CTRL_RST_GET(val) ((((val) & DMA_CTRL_RST) >> 0) & 0x1) + +/******************************************************************************* + * Channel Polling Register + ******************************************************************************/ + +/* Enable (31) */ +#define DMA_CPOLL_EN (0x1 << 31) +#define DMA_CPOLL_EN_VAL(val) (((val) & 0x1) << 31) +#define DMA_CPOLL_EN_GET(val) ((((val) & DMA_CPOLL_EN) >> 31) & 0x1) +#define DMA_CPOLL_EN_SET(reg,val) (reg) = ((reg & ~DMA_CPOLL_EN) | (((val) & 0x1) << 31)) +/* Counter (15:4) */ +#define DMA_CPOLL_CNT (0xfff << 4) +#define DMA_CPOLL_CNT_VAL(val) (((val) & 0xfff) << 4) +#define DMA_CPOLL_CNT_GET(val) ((((val) & DMA_CPOLL_CNT) >> 4) & 0xfff) +#define DMA_CPOLL_CNT_SET(reg,val) (reg) = ((reg & ~DMA_CPOLL_CNT) | (((val) & 0xfff) << 4)) + +/******************************************************************************* + * Global Buffer Length Register + ******************************************************************************/ + +/* Global Buffer Length (15:0) */ +#define DMA_CGBL_GBL (0xffff) +#define DMA_CGBL_GBL_VAL(val) (((val) & 0xffff) << 0) +#define DMA_CGBL_GBL_GET(val) ((((val) & DMA_CGBL_GBL) >> 0) & 0xffff) +#define DMA_CGBL_GBL_SET(reg,val) (reg) = ((reg & ~DMA_CGBL_GBL) | (((val) & 0xffff) << 0)) + +/******************************************************************************* + * Channel Select Register + ******************************************************************************/ + +/* Channel Selection (4:0) */ +#define DMA_CS_CS (0x1f) +#define DMA_CS_CS_VAL(val) (((val) & 0x1f) << 0) +#define DMA_CS_CS_GET(val) ((((val) & DMA_CS_CS) >> 0) & 0x1f) +#define DMA_CS_CS_SET(reg,val) (reg) = ((reg & ~DMA_CS_CS) | (((val) & 0x1f) << 0)) + +/******************************************************************************* + * Channel Control Register + ******************************************************************************/ + +/* Peripheral to Peripheral Copy (24) */ +#define DMA_CCTRL_P2PCPY (0x1 << 24) +#define DMA_CCTRL_P2PCPY_VAL(val) (((val) & 0x1) << 24) +#define DMA_CCTRL_P2PCPY_GET(val) ((((val) & DMA_CCTRL_P2PCPY) >> 24) & 0x1) +#define DMA_CCTRL_P2PCPY_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_P2PCPY) | (((val) & 0x1) << 24)) +/* Channel Weight for Transmit Direction (17:16) */ +#define DMA_CCTRL_TXWGT (0x3 << 16) +#define DMA_CCTRL_TXWGT_VAL(val) (((val) & 0x3) << 16) +#define DMA_CCTRL_TXWGT_GET(val) ((((val) & DMA_CCTRL_TXWGT) >> 16) & 0x3) +#define DMA_CCTRL_TXWGT_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_TXWGT) | (((val) & 0x3) << 16)) +/* Port Assignment (13:11) */ +#define DMA_CCTRL_PRTNR (0x7 << 11) +#define DMA_CCTRL_PRTNR_GET(val) ((((val) & DMA_CCTRL_PRTNR) >> 11) & 0x7) +/* Class (10:9) */ +#define DMA_CCTRL_CLASS (0x3 << 9) +#define DMA_CCTRL_CLASS_VAL(val) (((val) & 0x3) << 9) +#define DMA_CCTRL_CLASS_GET(val) ((((val) & DMA_CCTRL_CLASS) >> 9) & 0x3) +#define DMA_CCTRL_CLASS_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_CLASS) | (((val) & 0x3) << 9)) +/* Direction (8) */ +#define DMA_CCTRL_DIR (0x1 << 8) +#define DMA_CCTRL_DIR_GET(val) ((((val) & DMA_CCTRL_DIR) >> 8) & 0x1) +/* Reset (1) */ +#define DMA_CCTRL_RST (0x1 << 1) +#define DMA_CCTRL_RST_VAL(val) (((val) & 0x1) << 1) +#define DMA_CCTRL_RST_GET(val) ((((val) & DMA_CCTRL_RST) >> 1) & 0x1) +#define DMA_CCTRL_RST_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_RST) | (((val) & 0x1) << 1)) +/* Channel On or Off (0) */ +#define DMA_CCTRL_ON_OFF (0x1) +#define DMA_CCTRL_ON_OFF_VAL(val) (((val) & 0x1) << 0) +#define DMA_CCTRL_ON_OFF_GET(val) ((((val) & DMA_CCTRL_ON_OFF) >> 0) & 0x1) +#define DMA_CCTRL_ON_OFF_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_ON_OFF) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Channel Descriptor Base Address Register + ******************************************************************************/ + +/* Channel Descriptor Base Address (29:3) */ +#define DMA_CDBA_CDBA (0x7ffffff << 3) +#define DMA_CDBA_CDBA_VAL(val) (((val) & 0x7ffffff) << 3) +#define DMA_CDBA_CDBA_GET(val) ((((val) & DMA_CDBA_CDBA) >> 3) & 0x7ffffff) +#define DMA_CDBA_CDBA_SET(reg,val) (reg) = ((reg & ~DMA_CDBA_CDBA) | (((val) & 0x7ffffff) << 3)) + +/******************************************************************************* + * Channel Descriptor Length Register + ******************************************************************************/ + +/* Channel Descriptor Length (7:0) */ +#define DMA_CDLEN_CDLEN (0xff) +#define DMA_CDLEN_CDLEN_VAL(val) (((val) & 0xff) << 0) +#define DMA_CDLEN_CDLEN_GET(val) ((((val) & DMA_CDLEN_CDLEN) >> 0) & 0xff) +#define DMA_CDLEN_CDLEN_SET(reg,val) (reg) = ((reg & ~DMA_CDLEN_CDLEN) | (((val) & 0xff) << 0)) + +/******************************************************************************* + * Channel Interrupt Status Register + ******************************************************************************/ + +/* SAI Read Error Interrupt (5) */ +#define DMA_CIS_RDERR (0x1 << 5) +#define DMA_CIS_RDERR_GET(val) ((((val) & DMA_CIS_RDERR) >> 5) & 0x1) +/* Channel Off Interrupt (4) */ +#define DMA_CIS_CHOFF (0x1 << 4) +#define DMA_CIS_CHOFF_GET(val) ((((val) & DMA_CIS_CHOFF) >> 4) & 0x1) +/* Descriptor Complete Interrupt (3) */ +#define DMA_CIS_DESCPT (0x1 << 3) +#define DMA_CIS_DESCPT_GET(val) ((((val) & DMA_CIS_DESCPT) >> 3) & 0x1) +/* Descriptor Under-Run Interrupt (2) */ +#define DMA_CIS_DUR (0x1 << 2) +#define DMA_CIS_DUR_GET(val) ((((val) & DMA_CIS_DUR) >> 2) & 0x1) +/* End of Packet Interrupt (1) */ +#define DMA_CIS_EOP (0x1 << 1) +#define DMA_CIS_EOP_GET(val) ((((val) & DMA_CIS_EOP) >> 1) & 0x1) + +/******************************************************************************* + * Channel Interrupt Enable Register + ******************************************************************************/ + +/* SAI Read Error Interrupt (5) */ +#define DMA_CIE_RDERR (0x1 << 5) +#define DMA_CIE_RDERR_GET(val) ((((val) & DMA_CIE_RDERR) >> 5) & 0x1) +/* Channel Off Interrupt (4) */ +#define DMA_CIE_CHOFF (0x1 << 4) +#define DMA_CIE_CHOFF_GET(val) ((((val) & DMA_CIE_CHOFF) >> 4) & 0x1) +/* Descriptor Complete Interrupt Enable (3) */ +#define DMA_CIE_DESCPT (0x1 << 3) +#define DMA_CIE_DESCPT_GET(val) ((((val) & DMA_CIE_DESCPT) >> 3) & 0x1) +/* Descriptor Under Run Interrupt Enable (2) */ +#define DMA_CIE_DUR (0x1 << 2) +#define DMA_CIE_DUR_GET(val) ((((val) & DMA_CIE_DUR) >> 2) & 0x1) +/* End of Packet Interrupt Enable (1) */ +#define DMA_CIE_EOP (0x1 << 1) +#define DMA_CIE_EOP_GET(val) ((((val) & DMA_CIE_EOP) >> 1) & 0x1) + +/******************************************************************************* + * Port Select Register + ******************************************************************************/ + +/* Port Selection (2:0) */ +#define DMA_PS_PS (0x7) +#define DMA_PS_PS_VAL(val) (((val) & 0x7) << 0) +#define DMA_PS_PS_GET(val) ((((val) & DMA_PS_PS) >> 0) & 0x7) +#define DMA_PS_PS_SET(reg,val) (reg) = ((reg & ~DMA_PS_PS) | (((val) & 0x7) << 0)) + +/******************************************************************************* + * Port Control Register + ******************************************************************************/ + +/* General Purpose Control (16) */ +#define DMA_PCTRL_GPC (0x1 << 16) +#define DMA_PCTRL_GPC_VAL(val) (((val) & 0x1) << 16) +#define DMA_PCTRL_GPC_GET(val) ((((val) & DMA_PCTRL_GPC) >> 16) & 0x1) +#define DMA_PCTRL_GPC_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_GPC) | (((val) & 0x1) << 16)) +/* Port Weight for Transmit Direction (14:12) */ +#define DMA_PCTRL_TXWGT (0x7 << 12) +#define DMA_PCTRL_TXWGT_VAL(val) (((val) & 0x7) << 12) +#define DMA_PCTRL_TXWGT_GET(val) ((((val) & DMA_PCTRL_TXWGT) >> 12) & 0x7) +#define DMA_PCTRL_TXWGT_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXWGT) | (((val) & 0x7) << 12)) +/* Endianness for Transmit Direction (11:10) */ +#define DMA_PCTRL_TXENDI (0x3 << 10) +#define DMA_PCTRL_TXENDI_VAL(val) (((val) & 0x3) << 10) +#define DMA_PCTRL_TXENDI_GET(val) ((((val) & DMA_PCTRL_TXENDI) >> 10) & 0x3) +#define DMA_PCTRL_TXENDI_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXENDI) | (((val) & 0x3) << 10)) +/* Endianness for Receive Direction (9:8) */ +#define DMA_PCTRL_RXENDI (0x3 << 8) +#define DMA_PCTRL_RXENDI_VAL(val) (((val) & 0x3) << 8) +#define DMA_PCTRL_RXENDI_GET(val) ((((val) & DMA_PCTRL_RXENDI) >> 8) & 0x3) +#define DMA_PCTRL_RXENDI_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_RXENDI) | (((val) & 0x3) << 8)) +/* Packet Drop Enable (6) */ +#define DMA_PCTRL_PDEN (0x1 << 6) +#define DMA_PCTRL_PDEN_VAL(val) (((val) & 0x1) << 6) +#define DMA_PCTRL_PDEN_GET(val) ((((val) & DMA_PCTRL_PDEN) >> 6) & 0x1) +#define DMA_PCTRL_PDEN_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_PDEN) | (((val) & 0x1) << 6)) +/* Burst Length for Transmit Direction (5:4) */ +#define DMA_PCTRL_TXBL (0x3 << 4) +#define DMA_PCTRL_TXBL_VAL(val) (((val) & 0x3) << 4) +#define DMA_PCTRL_TXBL_GET(val) ((((val) & DMA_PCTRL_TXBL) >> 4) & 0x3) +#define DMA_PCTRL_TXBL_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXBL) | (((val) & 0x3) << 4)) +/* Burst Length for Receive Direction (3:2) */ +#define DMA_PCTRL_RXBL (0x3 << 2) +#define DMA_PCTRL_RXBL_VAL(val) (((val) & 0x3) << 2) +#define DMA_PCTRL_RXBL_GET(val) ((((val) & DMA_PCTRL_RXBL) >> 2) & 0x3) +#define DMA_PCTRL_RXBL_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_RXBL) | (((val) & 0x3) << 2)) + +/******************************************************************************* + * DMA_IRNEN Register + ******************************************************************************/ + +/* Channel x Interrupt Request Enable (23) */ +#define DMA_IRNEN_CH23 (0x1 << 23) +#define DMA_IRNEN_CH23_VAL(val) (((val) & 0x1) << 23) +#define DMA_IRNEN_CH23_GET(val) ((((val) & DMA_IRNEN_CH23) >> 23) & 0x1) +#define DMA_IRNEN_CH23_SET(reg,val) (reg) = ((reg & ~DMA_IRNEN_CH23) | (((val) & 0x1) << 23)) + +/******************************************************************************* + * DMA_IRNCR Register + ******************************************************************************/ + +/* Channel x Interrupt (23) */ +#define DMA_IRNCR_CH23 (0x1 << 23) +#define DMA_IRNCR_CH23_GET(val) ((((val) & DMA_IRNCR_CH23) >> 23) & 0x1) + +/******************************************************************************* + * DMA_IRNICR Register + ******************************************************************************/ + +/* Channel x Interrupt Request (23) */ +#define DMA_IRNICR_CH23 (0x1 << 23) +#define DMA_IRNICR_CH23_GET(val) ((((val) & DMA_IRNICR_CH23) >> 23) & 0x1) + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ebu_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ebu_reg.h new file mode 100644 index 0000000000..4e00d01bae --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ebu_reg.h @@ -0,0 +1,615 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __EBU_REG_H +#define __EBU_REG_H + +#define ebu_r32(reg) ltq_r32(&ebu->reg) +#define ebu_w32(val, reg) ltq_w32(val, &ebu->reg) +#define ebu_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &ebu->reg) + +/** EBU register structure */ +struct svip_reg_ebu { + volatile unsigned long clc; /* 0x0000 */ + volatile unsigned long reserved0; /* 0x04 */ + volatile unsigned long id; /* 0x0008 */ + volatile unsigned long reserved1; /* 0x0c */ + volatile unsigned long con; /* 0x0010 */ + volatile unsigned long reserved2[3]; /* 0x14 */ + volatile unsigned long addr_sel_0; /* 0x0020 */ + volatile unsigned long addr_sel_1; /* 0x0024 */ + volatile unsigned long addr_sel_2; /* 0x0028 */ + volatile unsigned long addr_sel_3; /* 0x002c */ + volatile unsigned long reserved3[12]; /* 0x30 */ + volatile unsigned long con_0; /* 0x0060 */ + volatile unsigned long con_1; /* 0x0064 */ + volatile unsigned long con_2; /* 0x0068 */ + volatile unsigned long con_3; /* 0x006c */ + volatile unsigned long reserved4[4]; /* 0x70 */ + volatile unsigned long emu_addr; /* 0x0080 */ + volatile unsigned long emu_bc; /* 0x0084 */ + volatile unsigned long emu_con; /* 0x0088 */ + volatile unsigned long reserved5; /* 0x8c */ + volatile unsigned long pcc_con; /* 0x0090 */ + volatile unsigned long pcc_stat; /* 0x0094 */ + volatile unsigned long reserved6[2]; /* 0x98 */ + volatile unsigned long pcc_istat; /* 0x00A0 */ + volatile unsigned long pcc_ien; /* 0x00A4 */ + volatile unsigned long pcc_int_out; /* 0x00A8 */ + volatile unsigned long pcc_irs; /* 0x00AC */ + volatile unsigned long nand_con; /* 0x00B0 */ + volatile unsigned long nand_wait; /* 0x00B4 */ + volatile unsigned long nand_ecc0; /* 0x00B8 */ + volatile unsigned long nand_ecc_ac; /* 0x00BC */ +}; + +/******************************************************************************* + * EBU + ******************************************************************************/ +#define LTQ_EBU_CLC ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0000)) +#define LTQ_EBU_ID ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0008)) +#define LTQ_EBU_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0010)) +#define LTQ_EBU_ADDR_SEL_0 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0020)) +#define LTQ_EBU_ADDR_SEL_1 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0024)) +#define LTQ_EBU_ADDR_SEL_2 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0028)) +#define LTQ_EBU_ADDR_SEL_3 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x002c)) +#define LTQ_EBU_CON_0 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0060)) +#define LTQ_EBU_CON_1 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0064)) +#define LTQ_EBU_CON_2 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0068)) +#define LTQ_EBU_CON_3 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x006c)) +#define LTQ_EBU_EMU_BC ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0084)) +#define LTQ_EBU_PCC_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0090)) +#define LTQ_EBU_PCC_STAT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0094)) +#define LTQ_EBU_PCC_ISTAT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A0)) +#define LTQ_EBU_PCC_IEN ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A4)) +#define LTQ_EBU_PCC_INT_OUT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A8)) +#define LTQ_EBU_PCC_IRS ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00AC)) +#define LTQ_EBU_NAND_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B0)) +#define LTQ_EBU_NAND_WAIT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B4)) +#define LTQ_EBU_NAND_ECC0 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B8)) +#define LTQ_EBU_NAND_ECC_AC ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00BC)) +#define LTQ_EBU_EMU_ADDR ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0080)) +#define LTQ_EBU_EMU_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0088)) + +/******************************************************************************* + * EBU Clock Control Register + ******************************************************************************/ + +/* EBU Disable Status Bit (1) */ +#define LTQ_EBU_CLC_DISS (0x1 << 1) +#define LTQ_EBU_CLC_DISS_GET(val) ((((val) & LTQ_EBU_CLC_DISS) >> 1) & 0x1) +/* Used for Enable/disable Control of the EBU (0) */ +#define LTQ_EBU_CLC_DISR (0x1) +#define LTQ_EBU_CLC_DISR_VAL(val) (((val) & 0x1) << 0) +#define LTQ_EBU_CLC_DISR_GET(val) ((((val) & LTQ_EBU_CLC_DISR) >> 0) & 0x1) +#define LTQ_EBU_CLC_DISR_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CLC_DISR) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * EBU Identification Register (Internal) + ******************************************************************************/ + +/* Module Number (31:8) */ +#define LTQ_EBU_ID_MODNUM (0xffffff << 8) +#define LTQ_EBU_ID_MODNUM_GET(val) ((((val) & LTQ_EBU_ID_MODNUM) >> 8) & 0xffffff) +/* Revision Number (7:0) */ +#define LTQ_EBU_ID_REVNUM (0xff) +#define LTQ_EBU_ID_REVNUM_GET(val) ((((val) & LTQ_EBU_ID_REVNUM) >> 0) & 0xff) + +/******************************************************************************* + * External Bus Unit Control Register + ******************************************************************************/ + +/* Driver Turn-Around Control, Chip Select Triggered (22:20) */ +#define LTQ_EBU_CON_DTACS (0x7 << 20) +#define LTQ_EBU_CON_DTACS_VAL(val) (((val) & 0x7) << 20) +#define LTQ_EBU_CON_DTACS_GET(val) ((((val) & LTQ_EBU_CON_DTACS) >> 20) & 0x7) +#define LTQ_EBU_CON_DTACS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_DTACS) | (((val) & 0x7) << 20)) +/* Driver Turn-Around Control, Read-write Triggered (18:16) */ +#define LTQ_EBU_CON_DTARW (0x7 << 16) +#define LTQ_EBU_CON_DTARW_VAL(val) (((val) & 0x7) << 16) +#define LTQ_EBU_CON_DTARW_GET(val) ((((val) & LTQ_EBU_CON_DTARW) >> 16) & 0x7) +#define LTQ_EBU_CON_DTARW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_DTARW) | (((val) & 0x7) << 16)) +/* Time-Out Control (15:8) */ +#define LTQ_EBU_CON_TOUTC (0xff << 8) +#define LTQ_EBU_CON_TOUTC_VAL(val) (((val) & 0xff) << 8) +#define LTQ_EBU_CON_TOUTC_GET(val) ((((val) & LTQ_EBU_CON_TOUTC) >> 8) & 0xff) +#define LTQ_EBU_CON_TOUTC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_TOUTC) | (((val) & 0xff) << 8)) +/* Arbitration Mode (7:6) */ +#define LTQ_EBU_CON_ARBMODE (0x3 << 6) +#define LTQ_EBU_CON_ARBMODE_VAL(val) (((val) & 0x3) << 6) +#define LTQ_EBU_CON_ARBMODE_GET(val) ((((val) & LTQ_EBU_CON_ARBMODE) >> 6) & 0x3) +#define LTQ_EBU_CON_ARBMODE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_ARBMODE) | (((val) & 0x3) << 6)) +/* Arbitration Synchronization (5) */ +#define LTQ_EBU_CON_ARBSYNC (0x1 << 5) +#define LTQ_EBU_CON_ARBSYNC_VAL(val) (((val) & 0x1) << 5) +#define LTQ_EBU_CON_ARBSYNC_GET(val) ((((val) & LTQ_EBU_CON_ARBSYNC) >> 5) & 0x1) +#define LTQ_EBU_CON_ARBSYNC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_ARBSYNC) | (((val) & 0x1) << 5)) + +/******************************************************************************* + * Address Select Registers + ******************************************************************************/ + +/* Memory Region Base Address (31:12) */ +#define LTQ_EBU_ADDR_SEL_0_BASE (0xfffff << 12) +#define LTQ_EBU_ADDR_SEL_0_BASE_VAL(val) (((val) & 0xfffff) << 12) +#define LTQ_EBU_ADDR_SEL_0_BASE_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_BASE) >> 12) & 0xfffff) +#define LTQ_EBU_ADDR_SEL_0_BASE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_BASE) | (((val) & 0xfffff) << 12)) +/* Memory Region Address Mask (7:4) */ +#define LTQ_EBU_ADDR_SEL_0_MASK (0xf << 4) +#define LTQ_EBU_ADDR_SEL_0_MASK_VAL(val) (((val) & 0xf) << 4) +#define LTQ_EBU_ADDR_SEL_0_MASK_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_MASK) >> 4) & 0xf) +#define LTQ_EBU_ADDR_SEL_0_MASK_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_MASK) | (((val) & 0xf) << 4)) +/* Memory Region Mirror Enable Control (1) */ +#define LTQ_EBU_ADDR_SEL_0_MRME (0x1 << 1) +#define LTQ_EBU_ADDR_SEL_0_MRME_VAL(val) (((val) & 0x1) << 1) +#define LTQ_EBU_ADDR_SEL_0_MRME_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_MRME) >> 1) & 0x1) +#define LTQ_EBU_ADDR_SEL_0_MRME_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_MRME) | (((val) & 0x1) << 1)) +/* Memory Region Enable Control (0) */ +#define LTQ_EBU_ADDR_SEL_0_REGEN (0x1) +#define LTQ_EBU_ADDR_SEL_0_REGEN_VAL(val) (((val) & 0x1) << 0) +#define LTQ_EBU_ADDR_SEL_0_REGEN_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_REGEN) >> 0) & 0x1) +#define LTQ_EBU_ADDR_SEL_0_REGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_REGEN) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Bus Configuration Registers + ******************************************************************************/ + +/* Memory Region Write Protection (31) */ +#define LTQ_EBU_CON_0_WRDIS (0x1 << 31) +#define LTQ_EBU_CON_0_WRDIS_VAL(val) (((val) & 0x1) << 31) +#define LTQ_EBU_CON_0_WRDIS_GET(val) ((((val) & LTQ_EBU_CON_0_WRDIS) >> 31) & 0x1) +#define LTQ_EBU_CON_0_WRDIS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WRDIS) | (((val) & 0x1) << 31)) +/* Address Swapping (30) */ +#define LTQ_EBU_CON_0_ADSWP (0x1 << 30) +#define LTQ_EBU_CON_0_ADSWP_VAL(val) (((val) & 0x1) << 30) +#define LTQ_EBU_CON_0_ADSWP_GET(val) ((((val) & LTQ_EBU_CON_0_ADSWP) >> 30) & 0x1) +#define LTQ_EBU_CON_0_ADSWP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_ADSWP) | (((val) & 0x1) << 30)) +/* Address Generation Control (26:24) */ +#define LTQ_EBU_CON_0_AGEN (0x7 << 24) +#define LTQ_EBU_CON_0_AGEN_VAL(val) (((val) & 0x7) << 24) +#define LTQ_EBU_CON_0_AGEN_GET(val) ((((val) & LTQ_EBU_CON_0_AGEN) >> 24) & 0x7) +#define LTQ_EBU_CON_0_AGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_AGEN) | (((val) & 0x7) << 24)) +/* Extended Address Setup Control (22) */ +#define LTQ_EBU_CON_0_SETUP (0x1 << 22) +#define LTQ_EBU_CON_0_SETUP_VAL(val) (((val) & 0x1) << 22) +#define LTQ_EBU_CON_0_SETUP_GET(val) ((((val) & LTQ_EBU_CON_0_SETUP) >> 22) & 0x1) +#define LTQ_EBU_CON_0_SETUP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_SETUP) | (((val) & 0x1) << 22)) +/* Variable Wait-State Insertion Control (21:20) */ +#define LTQ_EBU_CON_0_WAIT (0x3 << 20) +#define LTQ_EBU_CON_0_WAIT_VAL(val) (((val) & 0x3) << 20) +#define LTQ_EBU_CON_0_WAIT_GET(val) ((((val) & LTQ_EBU_CON_0_WAIT) >> 20) & 0x3) +#define LTQ_EBU_CON_0_WAIT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAIT) | (((val) & 0x3) << 20)) +/* Active WAIT Level Control (19) */ +#define LTQ_EBU_CON_0_WINV (0x1 << 19) +#define LTQ_EBU_CON_0_WINV_VAL(val) (((val) & 0x1) << 19) +#define LTQ_EBU_CON_0_WINV_GET(val) ((((val) & LTQ_EBU_CON_0_WINV) >> 19) & 0x1) +#define LTQ_EBU_CON_0_WINV_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WINV) | (((val) & 0x1) << 19)) +/* External Device Data Width Control (17:16) */ +#define LTQ_EBU_CON_0_PW (0x3 << 16) +#define LTQ_EBU_CON_0_PW_VAL(val) (((val) & 0x3) << 16) +#define LTQ_EBU_CON_0_PW_GET(val) ((((val) & LTQ_EBU_CON_0_PW) >> 16) & 0x3) +#define LTQ_EBU_CON_0_PW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_PW) | (((val) & 0x3) << 16)) +/* Address Latch Enable ALE Duration Control (15:14) */ +#define LTQ_EBU_CON_0_ALEC (0x3 << 14) +#define LTQ_EBU_CON_0_ALEC_VAL(val) (((val) & 0x3) << 14) +#define LTQ_EBU_CON_0_ALEC_GET(val) ((((val) & LTQ_EBU_CON_0_ALEC) >> 14) & 0x3) +#define LTQ_EBU_CON_0_ALEC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_ALEC) | (((val) & 0x3) << 14)) +/* Byte Control Signal Timing Mode Control (13:12) */ +#define LTQ_EBU_CON_0_BCGEN (0x3 << 12) +#define LTQ_EBU_CON_0_BCGEN_VAL(val) (((val) & 0x3) << 12) +#define LTQ_EBU_CON_0_BCGEN_GET(val) ((((val) & LTQ_EBU_CON_0_BCGEN) >> 12) & 0x3) +#define LTQ_EBU_CON_0_BCGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_BCGEN) | (((val) & 0x3) << 12)) +/* Write Access Wait-State Control (10:8) */ +#define LTQ_EBU_CON_0_WAITWRC (0x7 << 8) +#define LTQ_EBU_CON_0_WAITWRC_VAL(val) (((val) & 0x7) << 8) +#define LTQ_EBU_CON_0_WAITWRC_GET(val) ((((val) & LTQ_EBU_CON_0_WAITWRC) >> 8) & 0x7) +#define LTQ_EBU_CON_0_WAITWRC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAITWRC) | (((val) & 0x7) << 8)) +/* Read Access Wait-State Control (7:6) */ +#define LTQ_EBU_CON_0_WAITRDC (0x3 << 6) +#define LTQ_EBU_CON_0_WAITRDC_VAL(val) (((val) & 0x3) << 6) +#define LTQ_EBU_CON_0_WAITRDC_GET(val) ((((val) & LTQ_EBU_CON_0_WAITRDC) >> 6) & 0x3) +#define LTQ_EBU_CON_0_WAITRDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAITRDC) | (((val) & 0x3) << 6)) +/* Hold/Pause Cycle Control (5:4) */ +#define LTQ_EBU_CON_0_HOLDC (0x3 << 4) +#define LTQ_EBU_CON_0_HOLDC_VAL(val) (((val) & 0x3) << 4) +#define LTQ_EBU_CON_0_HOLDC_GET(val) ((((val) & LTQ_EBU_CON_0_HOLDC) >> 4) & 0x3) +#define LTQ_EBU_CON_0_HOLDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_HOLDC) | (((val) & 0x3) << 4)) +/* Recovery Cycle Control (3:2) */ +#define LTQ_EBU_CON_0_RECOVC (0x3 << 2) +#define LTQ_EBU_CON_0_RECOVC_VAL(val) (((val) & 0x3) << 2) +#define LTQ_EBU_CON_0_RECOVC_GET(val) ((((val) & LTQ_EBU_CON_0_RECOVC) >> 2) & 0x3) +#define LTQ_EBU_CON_0_RECOVC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_RECOVC) | (((val) & 0x3) << 2)) +/* Wait Cycle Multiplier Control (1:0) */ +#define LTQ_EBU_CON_0_CMULT (0x3) +#define LTQ_EBU_CON_0_CMULT_VAL(val) (((val) & 0x3) << 0) +#define LTQ_EBU_CON_0_CMULT_GET(val) ((((val) & LTQ_EBU_CON_0_CMULT) >> 0) & 0x3) +#define LTQ_EBU_CON_0_CMULT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_CMULT) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * External Bus Unit Emulator Bus Configuration Register + ******************************************************************************/ + +/* Write Protection (31) */ +#define LTQ_EBU_EMU_BC_WRITE (0x1 << 31) +#define LTQ_EBU_EMU_BC_WRITE_VAL(val) (((val) & 0x1) << 31) +#define LTQ_EBU_EMU_BC_WRITE_GET(val) ((((val) & LTQ_EBU_EMU_BC_WRITE) >> 31) & 0x1) +#define LTQ_EBU_EMU_BC_WRITE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WRITE) | (((val) & 0x1) << 31)) +/* Address Generation Control (26:24) */ +#define LTQ_EBU_EMU_BC_AGEN (0x7 << 24) +#define LTQ_EBU_EMU_BC_AGEN_VAL(val) (((val) & 0x7) << 24) +#define LTQ_EBU_EMU_BC_AGEN_GET(val) ((((val) & LTQ_EBU_EMU_BC_AGEN) >> 24) & 0x7) +#define LTQ_EBU_EMU_BC_AGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_AGEN) | (((val) & 0x7) << 24)) +/* Extended Address Setup Control (22) */ +#define LTQ_EBU_EMU_BC_SETUP (0x1 << 22) +#define LTQ_EBU_EMU_BC_SETUP_VAL(val) (((val) & 0x1) << 22) +#define LTQ_EBU_EMU_BC_SETUP_GET(val) ((((val) & LTQ_EBU_EMU_BC_SETUP) >> 22) & 0x1) +#define LTQ_EBU_EMU_BC_SETUP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_SETUP) | (((val) & 0x1) << 22)) +/* Variable Waitstate Insertion Control (21:20) */ +#define LTQ_EBU_EMU_BC_WAIT (0x3 << 20) +#define LTQ_EBU_EMU_BC_WAIT_VAL(val) (((val) & 0x3) << 20) +#define LTQ_EBU_EMU_BC_WAIT_GET(val) ((((val) & LTQ_EBU_EMU_BC_WAIT) >> 20) & 0x3) +#define LTQ_EBU_EMU_BC_WAIT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAIT) | (((val) & 0x3) << 20)) +/* Active WAIT Level Control (19) */ +#define LTQ_EBU_EMU_BC_WINV (0x1 << 19) +#define LTQ_EBU_EMU_BC_WINV_VAL(val) (((val) & 0x1) << 19) +#define LTQ_EBU_EMU_BC_WINV_GET(val) ((((val) & LTQ_EBU_EMU_BC_WINV) >> 19) & 0x1) +#define LTQ_EBU_EMU_BC_WINV_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WINV) | (((val) & 0x1) << 19)) +/* External Device Data Width Control (17:16) */ +#define LTQ_EBU_EMU_BC_PORTW (0x3 << 16) +#define LTQ_EBU_EMU_BC_PORTW_VAL(val) (((val) & 0x3) << 16) +#define LTQ_EBU_EMU_BC_PORTW_GET(val) ((((val) & LTQ_EBU_EMU_BC_PORTW) >> 16) & 0x3) +#define LTQ_EBU_EMU_BC_PORTW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_PORTW) | (((val) & 0x3) << 16)) +/* Address Latch Enable Function (15:14) */ +#define LTQ_EBU_EMU_BC_ALEC (0x3 << 14) +#define LTQ_EBU_EMU_BC_ALEC_VAL(val) (((val) & 0x3) << 14) +#define LTQ_EBU_EMU_BC_ALEC_GET(val) ((((val) & LTQ_EBU_EMU_BC_ALEC) >> 14) & 0x3) +#define LTQ_EBU_EMU_BC_ALEC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_ALEC) | (((val) & 0x3) << 14)) +/* Byte Control Signal Timing Mode (13:12) */ +#define LTQ_EBU_EMU_BC_BCGEN (0x3 << 12) +#define LTQ_EBU_EMU_BC_BCGEN_VAL(val) (((val) & 0x3) << 12) +#define LTQ_EBU_EMU_BC_BCGEN_GET(val) ((((val) & LTQ_EBU_EMU_BC_BCGEN) >> 12) & 0x3) +#define LTQ_EBU_EMU_BC_BCGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_BCGEN) | (((val) & 0x3) << 12)) +/* Write Access Waitstate Control (10:8) */ +#define LTQ_EBU_EMU_BC_WAITWRC (0x7 << 8) +#define LTQ_EBU_EMU_BC_WAITWRC_VAL(val) (((val) & 0x7) << 8) +#define LTQ_EBU_EMU_BC_WAITWRC_GET(val) ((((val) & LTQ_EBU_EMU_BC_WAITWRC) >> 8) & 0x7) +#define LTQ_EBU_EMU_BC_WAITWRC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAITWRC) | (((val) & 0x7) << 8)) +/* Read Access Waitstate Control (7:6) */ +#define LTQ_EBU_EMU_BC_WAITRDC (0x3 << 6) +#define LTQ_EBU_EMU_BC_WAITRDC_VAL(val) (((val) & 0x3) << 6) +#define LTQ_EBU_EMU_BC_WAITRDC_GET(val) ((((val) & LTQ_EBU_EMU_BC_WAITRDC) >> 6) & 0x3) +#define LTQ_EBU_EMU_BC_WAITRDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAITRDC) | (((val) & 0x3) << 6)) +/* Hold/Pause Cycle Control (5:4) */ +#define LTQ_EBU_EMU_BC_HOLDC (0x3 << 4) +#define LTQ_EBU_EMU_BC_HOLDC_VAL(val) (((val) & 0x3) << 4) +#define LTQ_EBU_EMU_BC_HOLDC_GET(val) ((((val) & LTQ_EBU_EMU_BC_HOLDC) >> 4) & 0x3) +#define LTQ_EBU_EMU_BC_HOLDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_HOLDC) | (((val) & 0x3) << 4)) +/* Recovery Cycles Control (3:2) */ +#define LTQ_EBU_EMU_BC_RECOVC (0x3 << 2) +#define LTQ_EBU_EMU_BC_RECOVC_VAL(val) (((val) & 0x3) << 2) +#define LTQ_EBU_EMU_BC_RECOVC_GET(val) ((((val) & LTQ_EBU_EMU_BC_RECOVC) >> 2) & 0x3) +#define LTQ_EBU_EMU_BC_RECOVC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_RECOVC) | (((val) & 0x3) << 2)) +/* Cycle Multiplier Control (1:0) */ +#define LTQ_EBU_EMU_BC_CMULT (0x3) +#define LTQ_EBU_EMU_BC_CMULT_VAL(val) (((val) & 0x3) << 0) +#define LTQ_EBU_EMU_BC_CMULT_GET(val) ((((val) & LTQ_EBU_EMU_BC_CMULT) >> 0) & 0x3) +#define LTQ_EBU_EMU_BC_CMULT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_CMULT) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * PC-Card Control Register + ******************************************************************************/ + +/* External Interrupt Input IREQ (3:1) */ +#define LTQ_EBU_PCC_CON_IREQ (0x7 << 1) +#define LTQ_EBU_PCC_CON_IREQ_VAL(val) (((val) & 0x7) << 1) +#define LTQ_EBU_PCC_CON_IREQ_GET(val) ((((val) & LTQ_EBU_PCC_CON_IREQ) >> 1) & 0x7) +#define LTQ_EBU_PCC_CON_IREQ_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_CON_IREQ) | (((val) & 0x7) << 1)) +/* PC Card ON (0) */ +#define LTQ_EBU_PCC_CON_ON (0x1) +#define LTQ_EBU_PCC_CON_ON_VAL(val) (((val) & 0x1) << 0) +#define LTQ_EBU_PCC_CON_ON_GET(val) ((((val) & LTQ_EBU_PCC_CON_ON) >> 0) & 0x1) +#define LTQ_EBU_PCC_CON_ON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_CON_ON) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * PCC Status Register + ******************************************************************************/ + +/* Interrupt Request (6) */ +#define LTQ_EBU_PCC_STAT_IRQ (0x1 << 6) +#define LTQ_EBU_PCC_STAT_IRQ_GET(val) ((((val) & LTQ_EBU_PCC_STAT_IRQ) >> 6) & 0x1) +/* PC-Card Overcurrent (5) */ +#define LTQ_EBU_PCC_STAT_OC (0x1 << 5) +#define LTQ_EBU_PCC_STAT_OC_GET(val) ((((val) & LTQ_EBU_PCC_STAT_OC) >> 5) & 0x1) +/* PC-Card Socket Power On (4) */ +#define LTQ_EBU_PCC_STAT_SPON (0x1 << 4) +#define LTQ_EBU_PCC_STAT_SPON_GET(val) ((((val) & LTQ_EBU_PCC_STAT_SPON) >> 4) & 0x1) +/* Card Detect Status (1:0) */ +#define LTQ_EBU_PCC_STAT_CD (0x3) +#define LTQ_EBU_PCC_STAT_CD_GET(val) ((((val) & LTQ_EBU_PCC_STAT_CD) >> 0) & 0x3) + +/******************************************************************************* + * PCC Interrupt Status Register + ******************************************************************************/ + +/* Interrupt Request Active Interrupt (4) */ +#define LTQ_EBU_PCC_ISTAT_IREQ (0x1 << 4) +#define LTQ_EBU_PCC_ISTAT_IREQ_VAL(val) (((val) & 0x1) << 4) +#define LTQ_EBU_PCC_ISTAT_IREQ_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_IREQ) >> 4) & 0x1) +#define LTQ_EBU_PCC_ISTAT_IREQ_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_IREQ) | (((val) & 0x1) << 4)) +/* Over Current Status Change Interrupt (3) */ +#define LTQ_EBU_PCC_ISTAT_OC (0x1 << 3) +#define LTQ_EBU_PCC_ISTAT_OC_VAL(val) (((val) & 0x1) << 3) +#define LTQ_EBU_PCC_ISTAT_OC_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_OC) >> 3) & 0x1) +#define LTQ_EBU_PCC_ISTAT_OC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_OC) | (((val) & 0x1) << 3)) +/* Socket Power on Status Change Interrupt (2) */ +#define LTQ_EBU_PCC_ISTAT_SPON (0x1 << 2) +#define LTQ_EBU_PCC_ISTAT_SPON_VAL(val) (((val) & 0x1) << 2) +#define LTQ_EBU_PCC_ISTAT_SPON_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_SPON) >> 2) & 0x1) +#define LTQ_EBU_PCC_ISTAT_SPON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_SPON) | (((val) & 0x1) << 2)) +/* Voltage Sense Status Change Interrupt (1) */ +#define LTQ_EBU_PCC_ISTAT_VS (0x1 << 1) +#define LTQ_EBU_PCC_ISTAT_VS_VAL(val) (((val) & 0x1) << 1) +#define LTQ_EBU_PCC_ISTAT_VS_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_VS) >> 1) & 0x1) +#define LTQ_EBU_PCC_ISTAT_VS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_VS) | (((val) & 0x1) << 1)) +/* Card Detect Status Change Interrupt (0) */ +#define LTQ_EBU_PCC_ISTAT_CD (0x1) +#define LTQ_EBU_PCC_ISTAT_CD_VAL(val) (((val) & 0x1) << 0) +#define LTQ_EBU_PCC_ISTAT_CD_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_CD) >> 0) & 0x1) +#define LTQ_EBU_PCC_ISTAT_CD_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_CD) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * PCC Interrupt Enable Register + ******************************************************************************/ + +/* Enable of Interrupt Request IR (4) */ +#define LTQ_EBU_PCC_IEN_IR (0x1 << 4) +#define LTQ_EBU_PCC_IEN_IR_VAL(val) (((val) & 0x1) << 4) +#define LTQ_EBU_PCC_IEN_IR_GET(val) ((((val) & LTQ_EBU_PCC_IEN_IR) >> 4) & 0x1) +#define LTQ_EBU_PCC_IEN_IR_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_IR) | (((val) & 0x1) << 4)) +/* Enable of Interrupt Request OC event (3) */ +#define LTQ_EBU_PCC_IEN_OC (0x1 << 3) +#define LTQ_EBU_PCC_IEN_OC_VAL(val) (((val) & 0x1) << 3) +#define LTQ_EBU_PCC_IEN_OC_GET(val) ((((val) & LTQ_EBU_PCC_IEN_OC) >> 3) & 0x1) +#define LTQ_EBU_PCC_IEN_OC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_OC) | (((val) & 0x1) << 3)) +/* Enable of Interrupt Request Socket Power On (2) */ +#define LTQ_EBU_PCC_IEN_PWRON (0x1 << 2) +#define LTQ_EBU_PCC_IEN_PWRON_VAL(val) (((val) & 0x1) << 2) +#define LTQ_EBU_PCC_IEN_PWRON_GET(val) ((((val) & LTQ_EBU_PCC_IEN_PWRON) >> 2) & 0x1) +#define LTQ_EBU_PCC_IEN_PWRON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_PWRON) | (((val) & 0x1) << 2)) +/* Enable of Interrupt Request Voltage Sense (1) */ +#define LTQ_EBU_PCC_IEN_VS (0x1 << 1) +#define LTQ_EBU_PCC_IEN_VS_VAL(val) (((val) & 0x1) << 1) +#define LTQ_EBU_PCC_IEN_VS_GET(val) ((((val) & LTQ_EBU_PCC_IEN_VS) >> 1) & 0x1) +#define LTQ_EBU_PCC_IEN_VS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_VS) | (((val) & 0x1) << 1)) +/* Enable of Interrupt Request Card Detect (0) */ +#define LTQ_EBU_PCC_IEN_CD (0x1) +#define LTQ_EBU_PCC_IEN_CD_VAL(val) (((val) & 0x1) << 0) +#define LTQ_EBU_PCC_IEN_CD_GET(val) ((((val) & LTQ_EBU_PCC_IEN_CD) >> 0) & 0x1) +#define LTQ_EBU_PCC_IEN_CD_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_CD) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * PCC Interrupt Output Status Register + ******************************************************************************/ + +/* Status of Interrupt Request IR (4) */ +#define LTQ_EBU_PCC_INT_OUT_IR (0x1 << 4) +#define LTQ_EBU_PCC_INT_OUT_IR_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_IR) >> 4) & 0x1) +/* Status of Interrupt Request OC (3) */ +#define LTQ_EBU_PCC_INT_OUT_OC (0x1 << 3) +#define LTQ_EBU_PCC_INT_OUT_OC_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_OC) >> 3) & 0x1) +/* Status of Interrupt Request Socket Power On (2) */ +#define LTQ_EBU_PCC_INT_OUT_PWRON (0x1 << 2) +#define LTQ_EBU_PCC_INT_OUT_PWRON_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_PWRON) >> 2) & 0x1) +/* Status of Interrupt Request Voltage Sense (1) */ +#define LTQ_EBU_PCC_INT_OUT_VS (0x1 << 1) +#define LTQ_EBU_PCC_INT_OUT_VS_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_VS) >> 1) & 0x1) +/* Status of Interrupt Request Card Detect (0) */ +#define LTQ_EBU_PCC_INT_OUT_CD (0x1) +#define LTQ_EBU_PCC_INT_OUT_CD_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_CD) >> 0) & 0x1) + +/******************************************************************************* + * PCC Interrupt Request Set Register + ******************************************************************************/ + +/* Set Interrupt Request IR (4) */ +#define LTQ_EBU_PCC_IRS_IR (0x1 << 4) +#define LTQ_EBU_PCC_IRS_IR_VAL(val) (((val) & 0x1) << 4) +#define LTQ_EBU_PCC_IRS_IR_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_IR) | (val) & 1) << 4) +/* Set Interrupt Request OC (3) */ +#define LTQ_EBU_PCC_IRS_OC (0x1 << 3) +#define LTQ_EBU_PCC_IRS_OC_VAL(val) (((val) & 0x1) << 3) +#define LTQ_EBU_PCC_IRS_OC_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_OC) | (val) & 1) << 3) +/* Set Interrupt Request Socket Power On (2) */ +#define LTQ_EBU_PCC_IRS_PWRON (0x1 << 2) +#define LTQ_EBU_PCC_IRS_PWRON_VAL(val) (((val) & 0x1) << 2) +#define LTQ_EBU_PCC_IRS_PWRON_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_PWRON) | (val) & 1) << 2) +/* Set Interrupt Request Voltage Sense (1) */ +#define LTQ_EBU_PCC_IRS_VS (0x1 << 1) +#define LTQ_EBU_PCC_IRS_VS_VAL(val) (((val) & 0x1) << 1) +#define LTQ_EBU_PCC_IRS_VS_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_VS) | (val) & 1) << 1) +/* Set Interrupt Request Card Detect (0) */ +#define LTQ_EBU_PCC_IRS_CD (0x1) +#define LTQ_EBU_PCC_IRS_CD_VAL(val) (((val) & 0x1) << 0) +#define LTQ_EBU_PCC_IRS_CD_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_CD) | (val) & 1) << 0) + +/******************************************************************************* + * NAND Flash Control Register + ******************************************************************************/ + +/* ECC Enabling (31) */ +#define LTQ_EBU_NAND_CON_ECC_ON (0x1 << 31) +#define LTQ_EBU_NAND_CON_ECC_ON_VAL(val) (((val) & 0x1) << 31) +#define LTQ_EBU_NAND_CON_ECC_ON_GET(val) ((((val) & LTQ_EBU_NAND_CON_ECC_ON) >> 31) & 0x1) +#define LTQ_EBU_NAND_CON_ECC_ON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_ECC_ON) | (((val) & 0x1) << 31)) +/* Latch enable (23:18) */ +#define LTQ_EBU_NAND_CON_LAT_EN (0x3f << 18) +#define LTQ_EBU_NAND_CON_LAT_EN_VAL(val) (((val) & 0x3f) << 18) +#define LTQ_EBU_NAND_CON_LAT_EN_GET(val) ((((val) & LTQ_EBU_NAND_CON_LAT_EN) >> 18) & 0x3f) +#define LTQ_EBU_NAND_CON_LAT_EN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_LAT_EN) | (((val) & 0x3f) << 18)) +/* Output ChipSelect# Selection (11:10) */ +#define LTQ_EBU_NAND_CON_OUT_CS_S (0x3 << 10) +#define LTQ_EBU_NAND_CON_OUT_CS_S_VAL(val) (((val) & 0x3) << 10) +#define LTQ_EBU_NAND_CON_OUT_CS_S_GET(val) ((((val) & LTQ_EBU_NAND_CON_OUT_CS_S) >> 10) & 0x3) +#define LTQ_EBU_NAND_CON_OUT_CS_S_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_OUT_CS_S) | (((val) & 0x3) << 10)) +/* Input ChipSelect# Selection (9:8) */ +#define LTQ_EBU_NAND_CON_IN_CS_S (0x3 << 8) +#define LTQ_EBU_NAND_CON_IN_CS_S_VAL(val) (((val) & 0x3) << 8) +#define LTQ_EBU_NAND_CON_IN_CS_S_GET(val) ((((val) & LTQ_EBU_NAND_CON_IN_CS_S) >> 8) & 0x3) +#define LTQ_EBU_NAND_CON_IN_CS_S_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_IN_CS_S) | (((val) & 0x3) << 8)) +/* Set PRE (7) */ +#define LTQ_EBU_NAND_CON_PRE_P (0x1 << 7) +#define LTQ_EBU_NAND_CON_PRE_P_VAL(val) (((val) & 0x1) << 7) +#define LTQ_EBU_NAND_CON_PRE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_PRE_P) >> 7) & 0x1) +#define LTQ_EBU_NAND_CON_PRE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_PRE_P) | (((val) & 0x1) << 7)) +/* Set WP Active Polarity (6) */ +#define LTQ_EBU_NAND_CON_WP_P (0x1 << 6) +#define LTQ_EBU_NAND_CON_WP_P_VAL(val) (((val) & 0x1) << 6) +#define LTQ_EBU_NAND_CON_WP_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_WP_P) >> 6) & 0x1) +#define LTQ_EBU_NAND_CON_WP_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_WP_P) | (((val) & 0x1) << 6)) +/* Set SE Active Polarity (5) */ +#define LTQ_EBU_NAND_CON_SE_P (0x1 << 5) +#define LTQ_EBU_NAND_CON_SE_P_VAL(val) (((val) & 0x1) << 5) +#define LTQ_EBU_NAND_CON_SE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_SE_P) >> 5) & 0x1) +#define LTQ_EBU_NAND_CON_SE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_SE_P) | (((val) & 0x1) << 5)) +/* Set CS Active Polarity (4) */ +#define LTQ_EBU_NAND_CON_CS_P (0x1 << 4) +#define LTQ_EBU_NAND_CON_CS_P_VAL(val) (((val) & 0x1) << 4) +#define LTQ_EBU_NAND_CON_CS_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_CS_P) >> 4) & 0x1) +#define LTQ_EBU_NAND_CON_CS_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CS_P) | (((val) & 0x1) << 4)) +/* Set CLE Active Polarity (3) */ +#define LTQ_EBU_NAND_CON_CLE_P (0x1 << 3) +#define LTQ_EBU_NAND_CON_CLE_P_VAL(val) (((val) & 0x1) << 3) +#define LTQ_EBU_NAND_CON_CLE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_CLE_P) >> 3) & 0x1) +#define LTQ_EBU_NAND_CON_CLE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CLE_P) | (((val) & 0x1) << 3)) +/* Set ALE Active Polarity (2) */ +#define LTQ_EBU_NAND_CON_ALE_P (0x1 << 2) +#define LTQ_EBU_NAND_CON_ALE_P_VAL(val) (((val) & 0x1) << 2) +#define LTQ_EBU_NAND_CON_ALE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_ALE_P) >> 2) & 0x1) +#define LTQ_EBU_NAND_CON_ALE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_ALE_P) | (((val) & 0x1) << 2)) +/* NAND CS Mux with EBU CS Enable (1) */ +#define LTQ_EBU_NAND_CON_CSMUX_E (0x1 << 1) +#define LTQ_EBU_NAND_CON_CSMUX_E_VAL(val) (((val) & 0x1) << 1) +#define LTQ_EBU_NAND_CON_CSMUX_E_GET(val) ((((val) & LTQ_EBU_NAND_CON_CSMUX_E) >> 1) & 0x1) +#define LTQ_EBU_NAND_CON_CSMUX_E_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CSMUX_E) | (((val) & 0x1) << 1)) +/* NAND FLASH Mode Support (0) */ +#define LTQ_EBU_NAND_CON_NANDMODE (0x1) +#define LTQ_EBU_NAND_CON_NANDMODE_VAL(val) (((val) & 0x1) << 0) +#define LTQ_EBU_NAND_CON_NANDMODE_GET(val) ((((val) & LTQ_EBU_NAND_CON_NANDMODE) >> 0) & 0x1) +#define LTQ_EBU_NAND_CON_NANDMODE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_NANDMODE) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * NAND Flash State Register + ******************************************************************************/ + +/* Reserved (31:3) */ +#define LTQ_EBU_NAND_WAIT_RES (0x1fffffff << 3) +#define LTQ_EBU_NAND_WAIT_RES_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_RES) >> 3) & 0x1fffffff) +/* NAND Write Complete (3) */ +#define LTQ_EBU_NAND_WAIT_WR_C (0x1 << 3) +#define LTQ_EBU_NAND_WAIT_WR_C_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_WR_C) >> 3) & 0x1) +/* Record the RD Edge (rising ) (2) */ +#define LTQ_EBU_NAND_WAIT_RD_EDGE (0x1 << 2) +#define LTQ_EBU_NAND_WAIT_RD_EDGE_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_RD_EDGE) >> 2) & 0x1) +/* Record the BY# Edge (falling) (1) */ +#define LTQ_EBU_NAND_WAIT_BY_EDGE (0x1 << 1) +#define LTQ_EBU_NAND_WAIT_BY_EDGE_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_BY_EDGE) >> 1) & 0x1) +/* Rd/BY# value (0) */ +#define LTQ_EBU_NAND_WAIT_RDBY_VALUE (0x1) +#define LTQ_EBU_NAND_WAIT_RDBY_VALUE_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_RDBY_VALUE) >> 0) & 0x1) + +/******************************************************************************* + * NAND ECC Result Register 0 + ******************************************************************************/ + +/* Reserved (31:24) */ +#define LTQ_EBU_NAND_ECC0_RES (0xff << 24) +#define LTQ_EBU_NAND_ECC0_RES_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_RES) >> 24) & 0xff) +/* ECC value (23:16) */ +#define LTQ_EBU_NAND_ECC0_ECC_B2 (0xff << 16) +#define LTQ_EBU_NAND_ECC0_ECC_B2_VAL(val) (((val) & 0xff) << 16) +#define LTQ_EBU_NAND_ECC0_ECC_B2_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_ECC_B2) >> 16) & 0xff) +#define LTQ_EBU_NAND_ECC0_ECC_B2_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B2) | (((val) & 0xff) << 16)) +/* ECC value (15:8) */ +#define LTQ_EBU_NAND_ECC0_ECC_B1 (0xff << 8) +#define LTQ_EBU_NAND_ECC0_ECC_B1_VAL(val) (((val) & 0xff) << 8) +#define LTQ_EBU_NAND_ECC0_ECC_B1_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_ECC_B1) >> 8) & 0xff) +#define LTQ_EBU_NAND_ECC0_ECC_B1_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B1) | (((val) & 0xff) << 8)) +/* ECC value (7:0) */ +#define LTQ_EBU_NAND_ECC0_ECC_B0 (0xff) +#define LTQ_EBU_NAND_ECC0_ECC_B0_VAL(val) (((val) & 0xff) << 0) +#define LTQ_EBU_NAND_ECC0_ECC_B0_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_ECC_B0) >> 0) & 0xff) +#define LTQ_EBU_NAND_ECC0_ECC_B0_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B0) | (((val) & 0xff) << 0)) + +/******************************************************************************* + * NAND ECC Address Counter Register + ******************************************************************************/ + +/* Reserved (31:9) */ +#define LTQ_EBU_NAND_ECC_AC_RES (0x7fffff << 9) +#define LTQ_EBU_NAND_ECC_AC_RES_GET(val) ((((val) & LTQ_EBU_NAND_ECC_AC_RES) >> 9) & 0x7fffff) +/* ECC address counter (8:0) */ +#define LTQ_EBU_NAND_ECC_AC_ECC_AC (0x1ff) +#define LTQ_EBU_NAND_ECC_AC_ECC_AC_VAL(val) (((val) & 0x1ff) << 0) +#define LTQ_EBU_NAND_ECC_AC_ECC_AC_GET(val) ((((val) & LTQ_EBU_NAND_ECC_AC_ECC_AC) >> 0) & 0x1ff) +#define LTQ_EBU_NAND_ECC_AC_ECC_AC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC_AC_ECC_AC) | (((val) & 0x1ff) << 0)) + +/******************************************************************************* + * Internal Address Emulation Register + ******************************************************************************/ + +/* Memory Region Base Address (31:12) */ +#define LTQ_EBU_EMU_ADDR_BASE (0xfffff << 12) +#define LTQ_EBU_EMU_ADDR_BASE_VAL(val) (((val) & 0xfffff) << 12) +#define LTQ_EBU_EMU_ADDR_BASE_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_BASE) >> 12) & 0xfffff) +#define LTQ_EBU_EMU_ADDR_BASE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_BASE) | (((val) & 0xfffff) << 12)) +/* Memory Region Address Mask (7:4) */ +#define LTQ_EBU_EMU_ADDR_MASK (0xf << 4) +#define LTQ_EBU_EMU_ADDR_MASK_VAL(val) (((val) & 0xf) << 4) +#define LTQ_EBU_EMU_ADDR_MASK_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_MASK) >> 4) & 0xf) +#define LTQ_EBU_EMU_ADDR_MASK_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MASK) | (((val) & 0xf) << 4)) +/* Memory Region Mirror Segment B Control (1) */ +#define LTQ_EBU_EMU_ADDR_MRMB (0x1 << 1) +#define LTQ_EBU_EMU_ADDR_MRMB_VAL(val) (((val) & 0x1) << 1) +#define LTQ_EBU_EMU_ADDR_MRMB_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_MRMB) >> 1) & 0x1) +#define LTQ_EBU_EMU_ADDR_MRMB_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MRMB) | (((val) & 0x1) << 1)) +/* Memory Region Enable Control (0) */ +#define LTQ_EBU_EMU_ADDR_MREC (0x1) +#define LTQ_EBU_EMU_ADDR_MREC_VAL(val) (((val) & 0x1) << 0) +#define LTQ_EBU_EMU_ADDR_MREC_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_MREC) >> 0) & 0x1) +#define LTQ_EBU_EMU_ADDR_MREC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MREC) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * nternal Emulator Configuration Register + ******************************************************************************/ + +/* Overlay Memory Control Region 3 (3) */ +#define LTQ_EBU_EMU_CON_OVL3 (0x1 << 3) +#define LTQ_EBU_EMU_CON_OVL3_VAL(val) (((val) & 0x1) << 3) +#define LTQ_EBU_EMU_CON_OVL3_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL3) >> 3) & 0x1) +#define LTQ_EBU_EMU_CON_OVL3_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL3) | (((val) & 0x1) << 3)) +/* Overlay Memory Control Region 2 (2) */ +#define LTQ_EBU_EMU_CON_OVL2 (0x1 << 2) +#define LTQ_EBU_EMU_CON_OVL2_VAL(val) (((val) & 0x1) << 2) +#define LTQ_EBU_EMU_CON_OVL2_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL2) >> 2) & 0x1) +#define LTQ_EBU_EMU_CON_OVL2_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL2) | (((val) & 0x1) << 2)) +/* Overlay Memory Control Region 1 (1) */ +#define LTQ_EBU_EMU_CON_OVL1 (0x1 << 1) +#define LTQ_EBU_EMU_CON_OVL1_VAL(val) (((val) & 0x1) << 1) +#define LTQ_EBU_EMU_CON_OVL1_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL1) >> 1) & 0x1) +#define LTQ_EBU_EMU_CON_OVL1_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL1) | (((val) & 0x1) << 1)) +/* Overlay Memory Control Region 0 (0) */ +#define LTQ_EBU_EMU_CON_OVL0 (0x1) +#define LTQ_EBU_EMU_CON_OVL0_VAL(val) (((val) & 0x1) << 0) +#define LTQ_EBU_EMU_CON_OVL0_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL0) >> 0) & 0x1) +#define LTQ_EBU_EMU_CON_OVL0_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL0) | (((val) & 0x1) << 0)) + +#endif /* __LTQ_EBU_H */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/es_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/es_reg.h new file mode 100644 index 0000000000..da84900f5e --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/es_reg.h @@ -0,0 +1,2098 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __ES_REG_H +#define __ES_REG_H + +#define es_r32(reg) ltq_r32(&es->reg) +#define es_w32(val, reg) ltq_w32(val, &es->reg) +#define es_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &es->reg) + +/** ES register structure */ +struct svip_reg_es { + volatile unsigned long ps; /* 0x0000 */ + volatile unsigned long p0_ctl; /* 0x0004 */ + volatile unsigned long p1_ctl; /* 0x0008 */ + volatile unsigned long p2_ctl; /* 0x000C */ + volatile unsigned long p0_vlan; /* 0x0010 */ + volatile unsigned long p1_vlan; /* 0x0014 */ + volatile unsigned long p2_vlan; /* 0x0018 */ + volatile unsigned long reserved1[1]; /* 0x001C */ + volatile unsigned long p0_inctl; /* 0x0020 */ + volatile unsigned long p1_inctl; /* 0x0024 */ + volatile unsigned long p2_inctl; /* 0x0028 */ + volatile unsigned long reserved2[1]; /* 0x002C */ + volatile unsigned long p0_ecs_q32; /* 0x0030 */ + volatile unsigned long p0_ecs_q10; /* 0x0034 */ + volatile unsigned long p0_ecw_q32; /* 0x0038 */ + volatile unsigned long p0_ecw_q10; /* 0x003C */ + volatile unsigned long p1_ecs_q32; /* 0x0040 */ + volatile unsigned long p1_ecs_q10; /* 0x0044 */ + volatile unsigned long p1_ecw_q32; /* 0x0048 */ + volatile unsigned long p1_ecw_q10; /* 0x004C */ + volatile unsigned long p2_ecs_q32; /* 0x0050 */ + volatile unsigned long p2_ecs_q10; /* 0x0054 */ + volatile unsigned long p2_ecw_q32; /* 0x0058 */ + volatile unsigned long p2_ecw_q10; /* 0x005C */ + volatile unsigned long int_ena; /* 0x0060 */ + volatile unsigned long int_st; /* 0x0064 */ + volatile unsigned long sw_gctl0; /* 0x0068 */ + volatile unsigned long sw_gctl1; /* 0x006C */ + volatile unsigned long arp; /* 0x0070 */ + volatile unsigned long strm_ctl; /* 0x0074 */ + volatile unsigned long rgmii_ctl; /* 0x0078 */ + volatile unsigned long prt_1p; /* 0x007C */ + volatile unsigned long gbkt_szbs; /* 0x0080 */ + volatile unsigned long gbkt_szebs; /* 0x0084 */ + volatile unsigned long bf_th; /* 0x0088 */ + volatile unsigned long pmac_hd_ctl; /* 0x008C */ + volatile unsigned long pmac_sa1; /* 0x0090 */ + volatile unsigned long pmac_sa2; /* 0x0094 */ + volatile unsigned long pmac_da1; /* 0x0098 */ + volatile unsigned long pmac_da2; /* 0x009C */ + volatile unsigned long pmac_vlan; /* 0x00A0 */ + volatile unsigned long pmac_tx_ipg; /* 0x00A4 */ + volatile unsigned long pmac_rx_ipg; /* 0x00A8 */ + volatile unsigned long adr_tb_ctl0; /* 0x00AC */ + volatile unsigned long adr_tb_ctl1; /* 0x00B0 */ + volatile unsigned long adr_tb_ctl2; /* 0x00B4 */ + volatile unsigned long adr_tb_st0; /* 0x00B8 */ + volatile unsigned long adr_tb_st1; /* 0x00BC */ + volatile unsigned long adr_tb_st2; /* 0x00C0 */ + volatile unsigned long rmon_ctl; /* 0x00C4 */ + volatile unsigned long rmon_st; /* 0x00C8 */ + volatile unsigned long mdio_ctl; /* 0x00CC */ + volatile unsigned long mdio_data; /* 0x00D0 */ + volatile unsigned long tp_flt_act; /* 0x00D4 */ + volatile unsigned long prtcl_flt_act; /* 0x00D8 */ + volatile unsigned long reserved4[9]; /* 0xdc */ + volatile unsigned long vlan_flt0; /* 0x0100 */ + volatile unsigned long vlan_flt1; /* 0x0104 */ + volatile unsigned long vlan_flt2; /* 0x0108 */ + volatile unsigned long vlan_flt3; /* 0x010C */ + volatile unsigned long vlan_flt4; /* 0x0110 */ + volatile unsigned long vlan_flt5; /* 0x0114 */ + volatile unsigned long vlan_flt6; /* 0x0118 */ + volatile unsigned long vlan_flt7; /* 0x011C */ + volatile unsigned long vlan_flt8; /* 0x0120 */ + volatile unsigned long vlan_flt9; /* 0x0124 */ + volatile unsigned long vlan_flt10; /* 0x0128 */ + volatile unsigned long vlan_flt11; /* 0x012C */ + volatile unsigned long vlan_flt12; /* 0x0130 */ + volatile unsigned long vlan_flt13; /* 0x0134 */ + volatile unsigned long vlan_flt14; /* 0x0138 */ + volatile unsigned long vlan_flt15; /* 0x013C */ + volatile unsigned long tp_flt10; /* 0x0140 */ + volatile unsigned long tp_flt32; /* 0x0144 */ + volatile unsigned long tp_flt54; /* 0x0148 */ + volatile unsigned long tp_flt76; /* 0x014C */ + volatile unsigned long dfsrv_map0; /* 0x0150 */ + volatile unsigned long dfsrv_map1; /* 0x0154 */ + volatile unsigned long dfsrv_map2; /* 0x0158 */ + volatile unsigned long dfsrv_map3; /* 0x015C */ + volatile unsigned long tcp_pf0; /* 0x0160 */ + volatile unsigned long tcp_pf1; /* 0x0164 */ + volatile unsigned long tcp_pf2; /* 0x0168 */ + volatile unsigned long tcp_pf3; /* 0x016C */ + volatile unsigned long tcp_pf4; /* 0x0170 */ + volatile unsigned long tcp_pf5; /* 0x0174 */ + volatile unsigned long tcp_pf6; /* 0x0178 */ + volatile unsigned long tcp_pf7; /* 0x017C */ + volatile unsigned long ra_03_00; /* 0x0180 */ + volatile unsigned long ra_07_04; /* 0x0184 */ + volatile unsigned long ra_0b_08; /* 0x0188 */ + volatile unsigned long ra_0f_0c; /* 0x018C */ + volatile unsigned long ra_13_10; /* 0x0190 */ + volatile unsigned long ra_17_14; /* 0x0194 */ + volatile unsigned long ra_1b_18; /* 0x0198 */ + volatile unsigned long ra_1f_1c; /* 0x019C */ + volatile unsigned long ra_23_20; /* 0x01A0 */ + volatile unsigned long ra_27_24; /* 0x01A4 */ + volatile unsigned long ra_2b_28; /* 0x01A8 */ + volatile unsigned long ra_2f_2c; /* 0x01AC */ + volatile unsigned long prtcl_f0; /* 0x01B0 */ + volatile unsigned long prtcl_f1; /* 0x01B4 */ +}; + +/******************************************************************************* + * ES + ******************************************************************************/ +#define LTQ_ES_PS_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0000)) +#define LTQ_ES_P0_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0004)) +#define LTQ_ES_P1_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0008)) +#define LTQ_ES_P2_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x000C)) +#define LTQ_ES_P0_VLAN_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0010)) +#define LTQ_ES_P1_VLAN_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0014)) +#define LTQ_ES_P2_VLAN_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0010)) +#define LTQ_ES_P0_INCTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0020)) +#define LTQ_ES_P1_INCTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0024)) +#define LTQ_ES_P2_INCTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0028)) +#define LTQ_ES_P0_ECS_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0030)) +#define LTQ_ES_P0_ECS_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0034)) +#define LTQ_ES_P0_ECW_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0038)) +#define LTQ_ES_P0_ECW_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x003C)) +#define LTQ_ES_P1_ECS_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0030)) +#define LTQ_ES_P1_ECS_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0034)) +#define LTQ_ES_P1_ECW_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0038)) +#define LTQ_ES_P1_ECW_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x003C)) +#define LTQ_ES_P2_ECS_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0030)) +#define LTQ_ES_P2_ECS_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0034)) +#define LTQ_ES_P2_ECW_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0038)) +#define LTQ_ES_P2_ECW_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x003C)) +#define LTQ_ES_INT_ENA_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0060)) +#define LTQ_ES_INT_ST_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0064)) +#define LTQ_ES_SW_GCTL0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0068)) +#define LTQ_ES_SW_GCTL1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x006C)) +#define LTQ_ES_ARP_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0070)) +#define LTQ_ES_STRM_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0074)) +#define LTQ_ES_RGMII_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0078)) +#define LTQ_ES_PRT_1P_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x007C)) +#define LTQ_ES_GBKT_SZBS_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0080)) +#define LTQ_ES_GBKT_SZEBS_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0084)) +#define LTQ_ES_BF_TH_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0088)) +#define LTQ_ES_PMAC_HD_CTL ((volatile unsigned int*)(LTQ_ES_BASE + 0x008C)) +#define LTQ_ES_PMAC_SA1 ((volatile unsigned int*)(LTQ_ES_BASE + 0x0090)) +#define LTQ_ES_PMAC_SA2 ((volatile unsigned int*)(LTQ_ES_BASE + 0x0094)) +#define LTQ_ES_PMAC_DA1 ((volatile unsigned int*)(LTQ_ES_BASE + 0x0098)) +#define LTQ_ES_PMAC_DA2 ((volatile unsigned int*)(LTQ_ES_BASE + 0x009C)) +#define LTQ_ES_PMAC_VLAN ((volatile unsigned int*)(LTQ_ES_BASE + 0x00A0)) +#define LTQ_ES_PMAC_TX_IPG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00A4)) +#define LTQ_ES_PMAC_RX_IPG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00A8)) +#define LTQ_ES_ADR_TB_CTL0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00AC)) +#define LTQ_ES_ADR_TB_CTL1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00B0)) +#define LTQ_ES_ADR_TB_CTL2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00B4)) +#define LTQ_ES_ADR_TB_ST0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00B8)) +#define LTQ_ES_ADR_TB_ST1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00BC)) +#define LTQ_ES_ADR_TB_ST2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00C0)) +#define LTQ_ES_RMON_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00C4)) +#define LTQ_ES_RMON_ST_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00C8)) +#define LTQ_ES_MDIO_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00CC)) +#define LTQ_ES_MDIO_DATA_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00D0)) +#define LTQ_ES_TP_FLT_ACT_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00D4)) +#define LTQ_ES_PRTCL_FLT_ACT_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00D8)) +#define LTQ_ES_VLAN_FLT0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0100)) +#define LTQ_ES_VLAN_FLT1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0104)) +#define LTQ_ES_VLAN_FLT2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0108)) +#define LTQ_ES_VLAN_FLT3_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x010C)) +#define LTQ_ES_VLAN_FLT4_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0110)) +#define LTQ_ES_VLAN_FLT5_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0114)) +#define LTQ_ES_VLAN_FLT6_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0118)) +#define LTQ_ES_VLAN_FLT7_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x011C)) +#define LTQ_ES_VLAN_FLT8_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0120)) +#define LTQ_ES_VLAN_FLT9_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0124)) +#define LTQ_ES_VLAN_FLT10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0128)) +#define LTQ_ES_VLAN_FLT11_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x012C)) +#define LTQ_ES_VLAN_FLT12_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0130)) +#define LTQ_ES_VLAN_FLT13_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0134)) +#define LTQ_ES_VLAN_FLT14_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0138)) +#define LTQ_ES_VLAN_FLT15_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x013C)) +#define LTQ_ES_TP_FLT10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0140)) +#define LTQ_ES_TP_FLT32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0144)) +#define LTQ_ES_TP_FLT54_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0148)) +#define LTQ_ES_TP_FLT76_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x014C)) +#define LTQ_ES_DFSRV_MAP0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0150)) +#define LTQ_ES_DFSRV_MAP1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0154)) +#define LTQ_ES_DFSRV_MAP2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0158)) +#define LTQ_ES_DFSRV_MAP3_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x015C)) +#define LTQ_ES_TCP_PF0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0160)) +#define LTQ_ES_TCP_PF1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0164)) +#define LTQ_ES_TCP_PF2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0168)) +#define LTQ_ES_TCP_PF3_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x016C)) +#define LTQ_ES_TCP_PF4_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0170)) +#define LTQ_ES_TCP_PF5_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0174)) +#define LTQ_ES_TCP_PF6_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0178)) +#define LTQ_ES_TCP_PF7_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x017C)) +#define LTQ_ES_RA_03_00_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0180)) +#define LTQ_ES_RA_07_04_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0184)) +#define LTQ_ES_RA_0B_08_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0188)) +#define LTQ_ES_RA_0F_0C_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x018C)) +#define LTQ_ES_RA_13_10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0190)) +#define LTQ_ES_RA_17_14_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0194)) +#define LTQ_ES_RA_1B_18_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0198)) +#define LTQ_ES_RA_1F_1C_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x019C)) +#define LTQ_ES_RA_23_20_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01A0)) +#define LTQ_ES_RA_27_24_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01A4)) +#define LTQ_ES_RA_2B_28_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01A8)) +#define LTQ_ES_RA_2F_2C_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01AC)) +#define LTQ_ES_PRTCL_F0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01B0)) +#define LTQ_ES_PRTCL_F1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01B4)) + +/******************************************************************************* + * Port Status Register + ******************************************************************************/ + +/* Port 1 Flow Control Status (12) */ +#define LTQ_ES_PS_REG_P1FCS (0x1 << 12) +#define LTQ_ES_PS_REG_P1FCS_GET(val) ((((val) & LTQ_ES_PS_REG_P1FCS) >> 12) & 0x1) +/* Port 1 Duplex Status (11) */ +#define LTQ_ES_PS_REG_P1DS (0x1 << 11) +#define LTQ_ES_PS_REG_P1DS_GET(val) ((((val) & LTQ_ES_PS_REG_P1DS) >> 11) & 0x1) +/* Port 1 Speed High Status (10) */ +#define LTQ_ES_PS_REG_P1SHS (0x1 << 10) +#define LTQ_ES_PS_REG_P1SHS_GET(val) ((((val) & LTQ_ES_PS_REG_P1SHS) >> 10) & 0x1) +/* Port 1 Speed Status (9) */ +#define LTQ_ES_PS_REG_P1SS (0x1 << 9) +#define LTQ_ES_PS_REG_P1SS_GET(val) ((((val) & LTQ_ES_PS_REG_P1SS) >> 9) & 0x1) +/* Port 1 Link Status (8) */ +#define LTQ_ES_PS_REG_P1LS (0x1 << 8) +#define LTQ_ES_PS_REG_P1LS_GET(val) ((((val) & LTQ_ES_PS_REG_P1LS) >> 8) & 0x1) +/* Port 0 Flow Control Status (4) */ +#define LTQ_ES_PS_REG_P0FCS (0x1 << 4) +#define LTQ_ES_PS_REG_P0FCS_GET(val) ((((val) & LTQ_ES_PS_REG_P0FCS) >> 4) & 0x1) +/* Port 0 Duplex Status (3) */ +#define LTQ_ES_PS_REG_P0DS (0x1 << 3) +#define LTQ_ES_PS_REG_P0DS_GET(val) ((((val) & LTQ_ES_PS_REG_P0DS) >> 3) & 0x1) +/* Port 0 Speed High Status (2) */ +#define LTQ_ES_PS_REG_P0SHS (0x1 << 2) +#define LTQ_ES_PS_REG_P0SHS_GET(val) ((((val) & LTQ_ES_PS_REG_P0SHS) >> 2) & 0x1) +/* Port 0 Speed Status (1) */ +#define LTQ_ES_PS_REG_P0SS (0x1 << 1) +#define LTQ_ES_PS_REG_P0SS_GET(val) ((((val) & LTQ_ES_PS_REG_P0SS) >> 1) & 0x1) +/* Port 0 Link Status (0) */ +#define LTQ_ES_PS_REG_P0LS (0x1) +#define LTQ_ES_PS_REG_P0LS_GET(val) ((((val) & LTQ_ES_PS_REG_P0LS) >> 0) & 0x1) + +/******************************************************************************* + * P0 Control Register + ******************************************************************************/ + +/* STP/RSTP port state (31:30) */ +#define LTQ_ES_P0_CTL_REG_SPS (0x3 << 30) +#define LTQ_ES_P0_CTL_REG_SPS_VAL(val) (((val) & 0x3) << 30) +#define LTQ_ES_P0_CTL_REG_SPS_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_SPS) >> 30) & 0x3) +#define LTQ_ES_P0_CTL_REG_SPS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_SPS) | (((val) & 0x3) << 30)) +/* TCP/UDP PRIEN (29) */ +#define LTQ_ES_P0_CTL_REG_TCPE (0x1 << 29) +#define LTQ_ES_P0_CTL_REG_TCPE_VAL(val) (((val) & 0x1) << 29) +#define LTQ_ES_P0_CTL_REG_TCPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_TCPE) >> 29) & 0x1) +#define LTQ_ES_P0_CTL_REG_TCPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_TCPE) | (((val) & 0x1) << 29)) +/* IP over TCP/UDP (28) */ +#define LTQ_ES_P0_CTL_REG_IPOVTU (0x1 << 28) +#define LTQ_ES_P0_CTL_REG_IPOVTU_VAL(val) (((val) & 0x1) << 28) +#define LTQ_ES_P0_CTL_REG_IPOVTU_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_IPOVTU) >> 28) & 0x1) +#define LTQ_ES_P0_CTL_REG_IPOVTU_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_IPOVTU) | (((val) & 0x1) << 28)) +/* VLAN Priority Enable (27) */ +#define LTQ_ES_P0_CTL_REG_VPE (0x1 << 27) +#define LTQ_ES_P0_CTL_REG_VPE_VAL(val) (((val) & 0x1) << 27) +#define LTQ_ES_P0_CTL_REG_VPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_VPE) >> 27) & 0x1) +#define LTQ_ES_P0_CTL_REG_VPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_VPE) | (((val) & 0x1) << 27)) +/* Service Priority Enable (26) */ +#define LTQ_ES_P0_CTL_REG_SPE (0x1 << 26) +#define LTQ_ES_P0_CTL_REG_SPE_VAL(val) (((val) & 0x1) << 26) +#define LTQ_ES_P0_CTL_REG_SPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_SPE) >> 26) & 0x1) +#define LTQ_ES_P0_CTL_REG_SPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_SPE) | (((val) & 0x1) << 26)) +/* IP over VLAN PRI (25) */ +#define LTQ_ES_P0_CTL_REG_IPVLAN (0x1 << 25) +#define LTQ_ES_P0_CTL_REG_IPVLAN_VAL(val) (((val) & 0x1) << 25) +#define LTQ_ES_P0_CTL_REG_IPVLAN_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_IPVLAN) >> 25) & 0x1) +#define LTQ_ES_P0_CTL_REG_IPVLAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_IPVLAN) | (((val) & 0x1) << 25)) +/* Ether Type Priority Enable (24) */ +#define LTQ_ES_P0_CTL_REG_TPE (0x1 << 24) +#define LTQ_ES_P0_CTL_REG_TPE_VAL(val) (((val) & 0x1) << 24) +#define LTQ_ES_P0_CTL_REG_TPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_TPE) >> 24) & 0x1) +#define LTQ_ES_P0_CTL_REG_TPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_TPE) | (((val) & 0x1) << 24)) +/* Force Link Up (18) */ +#define LTQ_ES_P0_CTL_REG_FLP (0x1 << 18) +#define LTQ_ES_P0_CTL_REG_FLP_VAL(val) (((val) & 0x1) << 18) +#define LTQ_ES_P0_CTL_REG_FLP_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_FLP) >> 18) & 0x1) +#define LTQ_ES_P0_CTL_REG_FLP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_FLP) | (((val) & 0x1) << 18)) +/* Force Link Down (17) */ +#define LTQ_ES_P0_CTL_REG_FLD (0x1 << 17) +#define LTQ_ES_P0_CTL_REG_FLD_VAL(val) (((val) & 0x1) << 17) +#define LTQ_ES_P0_CTL_REG_FLD_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_FLD) >> 17) & 0x1) +#define LTQ_ES_P0_CTL_REG_FLD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_FLD) | (((val) & 0x1) << 17)) +/* Ratio Mode for WFQ (16) */ +#define LTQ_ES_P0_CTL_REG_RMWFQ (0x1 << 16) +#define LTQ_ES_P0_CTL_REG_RMWFQ_VAL(val) (((val) & 0x1) << 16) +#define LTQ_ES_P0_CTL_REG_RMWFQ_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_RMWFQ) >> 16) & 0x1) +#define LTQ_ES_P0_CTL_REG_RMWFQ_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_RMWFQ) | (((val) & 0x1) << 16)) +/* Aging Disable (15) */ +#define LTQ_ES_P0_CTL_REG_AD (0x1 << 15) +#define LTQ_ES_P0_CTL_REG_AD_VAL(val) (((val) & 0x1) << 15) +#define LTQ_ES_P0_CTL_REG_AD_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_AD) >> 15) & 0x1) +#define LTQ_ES_P0_CTL_REG_AD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_AD) | (((val) & 0x1) << 15)) +/* Learning Disable (14) */ +#define LTQ_ES_P0_CTL_REG_LD (0x1 << 14) +#define LTQ_ES_P0_CTL_REG_LD_VAL(val) (((val) & 0x1) << 14) +#define LTQ_ES_P0_CTL_REG_LD_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_LD) >> 14) & 0x1) +#define LTQ_ES_P0_CTL_REG_LD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_LD) | (((val) & 0x1) << 14)) +/* Maximum Number of Addresses (12:8) */ +#define LTQ_ES_P0_CTL_REG_MNA024 (0x1f << 8) +#define LTQ_ES_P0_CTL_REG_MNA024_VAL(val) (((val) & 0x1f) << 8) +#define LTQ_ES_P0_CTL_REG_MNA024_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_MNA024) >> 8) & 0x1f) +#define LTQ_ES_P0_CTL_REG_MNA024_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_MNA024) | (((val) & 0x1f) << 8)) +/* PPPOE Port Only (7) */ +#define LTQ_ES_P0_CTL_REG_PPPOEP (0x1 << 7) +#define LTQ_ES_P0_CTL_REG_PPPOEP_VAL(val) (((val) & 0x1) << 7) +#define LTQ_ES_P0_CTL_REG_PPPOEP_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_PPPOEP) >> 7) & 0x1) +#define LTQ_ES_P0_CTL_REG_PPPOEP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_PPPOEP) | (((val) & 0x1) << 7)) +/* PPPOE Manage (6) */ +#define LTQ_ES_P0_CTL_REG_PM (0x1 << 6) +#define LTQ_ES_P0_CTL_REG_PM_VAL(val) (((val) & 0x1) << 6) +#define LTQ_ES_P0_CTL_REG_PM_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_PM) >> 6) & 0x1) +#define LTQ_ES_P0_CTL_REG_PM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_PM) | (((val) & 0x1) << 6)) +/* Port Mirror Option (5:4) */ +#define LTQ_ES_P0_CTL_REG_IPMO (0x3 << 4) +#define LTQ_ES_P0_CTL_REG_IPMO_VAL(val) (((val) & 0x3) << 4) +#define LTQ_ES_P0_CTL_REG_IPMO_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_IPMO) >> 4) & 0x3) +#define LTQ_ES_P0_CTL_REG_IPMO_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_IPMO) | (((val) & 0x3) << 4)) +/* 802.1x Port Authorized state (3:2) */ +#define LTQ_ES_P0_CTL_REG_PAS (0x3 << 2) +#define LTQ_ES_P0_CTL_REG_PAS_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_P0_CTL_REG_PAS_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_PAS) >> 2) & 0x3) +#define LTQ_ES_P0_CTL_REG_PAS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_PAS) | (((val) & 0x3) << 2)) +/* Drop Scheme for voilation 802.1x (1) */ +#define LTQ_ES_P0_CTL_REG_DSV8021X (0x1 << 1) +#define LTQ_ES_P0_CTL_REG_DSV8021X_VAL(val) (((val) & 0x1) << 1) +#define LTQ_ES_P0_CTL_REG_DSV8021X_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_DSV8021X) >> 1) & 0x1) +#define LTQ_ES_P0_CTL_REG_DSV8021X_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_DSV8021X) | (((val) & 0x1) << 1)) +/* ByPass Mode for Output (0) */ +#define LTQ_ES_P0_CTL_REG_BYPASS (0x1) +#define LTQ_ES_P0_CTL_REG_BYPASS_VAL(val) (((val) & 0x1) << 0) +#define LTQ_ES_P0_CTL_REG_BYPASS_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_BYPASS) >> 0) & 0x1) +#define LTQ_ES_P0_CTL_REG_BYPASS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_BYPASS) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 0 VLAN Control Register + ******************************************************************************/ + +/* Default FID (31:30) */ +#define LTQ_ES_P0_VLAN_REG_DFID (0x3 << 30) +#define LTQ_ES_P0_VLAN_REG_DFID_VAL(val) (((val) & 0x3) << 30) +#define LTQ_ES_P0_VLAN_REG_DFID_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_DFID) >> 30) & 0x3) +#define LTQ_ES_P0_VLAN_REG_DFID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_DFID) | (((val) & 0x3) << 30)) +/* Tagged Base VLAN Enable (29) */ +#define LTQ_ES_P0_VLAN_REG_TBVE (0x1 << 29) +#define LTQ_ES_P0_VLAN_REG_TBVE_VAL(val) (((val) & 0x1) << 29) +#define LTQ_ES_P0_VLAN_REG_TBVE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_TBVE) >> 29) & 0x1) +#define LTQ_ES_P0_VLAN_REG_TBVE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_TBVE) | (((val) & 0x1) << 29)) +/* Input Force No TAG Enable (28) */ +#define LTQ_ES_P0_VLAN_REG_IFNTE (0x1 << 28) +#define LTQ_ES_P0_VLAN_REG_IFNTE_VAL(val) (((val) & 0x1) << 28) +#define LTQ_ES_P0_VLAN_REG_IFNTE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_IFNTE) >> 28) & 0x1) +#define LTQ_ES_P0_VLAN_REG_IFNTE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_IFNTE) | (((val) & 0x1) << 28)) +/* VID Check with the VID table (27) */ +#define LTQ_ES_P0_VLAN_REG_VC (0x1 << 27) +#define LTQ_ES_P0_VLAN_REG_VC_VAL(val) (((val) & 0x1) << 27) +#define LTQ_ES_P0_VLAN_REG_VC_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_VC) >> 27) & 0x1) +#define LTQ_ES_P0_VLAN_REG_VC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_VC) | (((val) & 0x1) << 27)) +/* VLAN Security Disable (26) */ +#define LTQ_ES_P0_VLAN_REG_VSD (0x1 << 26) +#define LTQ_ES_P0_VLAN_REG_VSD_VAL(val) (((val) & 0x1) << 26) +#define LTQ_ES_P0_VLAN_REG_VSD_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_VSD) >> 26) & 0x1) +#define LTQ_ES_P0_VLAN_REG_VSD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_VSD) | (((val) & 0x1) << 26)) +/* Admit Only VLAN_Tagged Packet (25) */ +#define LTQ_ES_P0_VLAN_REG_AOVTP (0x1 << 25) +#define LTQ_ES_P0_VLAN_REG_AOVTP_VAL(val) (((val) & 0x1) << 25) +#define LTQ_ES_P0_VLAN_REG_AOVTP_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_AOVTP) >> 25) & 0x1) +#define LTQ_ES_P0_VLAN_REG_AOVTP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_AOVTP) | (((val) & 0x1) << 25)) +/* VLAN Member Check Enable (24) */ +#define LTQ_ES_P0_VLAN_REG_VMCE (0x1 << 24) +#define LTQ_ES_P0_VLAN_REG_VMCE_VAL(val) (((val) & 0x1) << 24) +#define LTQ_ES_P0_VLAN_REG_VMCE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_VMCE) >> 24) & 0x1) +#define LTQ_ES_P0_VLAN_REG_VMCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_VMCE) | (((val) & 0x1) << 24)) +/* Reserved (23:19) */ +#define LTQ_ES_P0_VLAN_REG_RES (0x1f << 19) +#define LTQ_ES_P0_VLAN_REG_RES_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_RES) >> 19) & 0x1f) +/* Default VLAN Port Map (18:16) */ +#define LTQ_ES_P0_VLAN_REG_DVPM (0x7 << 16) +#define LTQ_ES_P0_VLAN_REG_DVPM_VAL(val) (((val) & 0x7) << 16) +#define LTQ_ES_P0_VLAN_REG_DVPM_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_DVPM) >> 16) & 0x7) +#define LTQ_ES_P0_VLAN_REG_DVPM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_DVPM) | (((val) & 0x7) << 16)) +/* Port Priority (15:14) */ +#define LTQ_ES_P0_VLAN_REG_PP (0x3 << 14) +#define LTQ_ES_P0_VLAN_REG_PP_VAL(val) (((val) & 0x3) << 14) +#define LTQ_ES_P0_VLAN_REG_PP_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PP) >> 14) & 0x3) +#define LTQ_ES_P0_VLAN_REG_PP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PP) | (((val) & 0x3) << 14)) +/* Port Priority Enable (13) */ +#define LTQ_ES_P0_VLAN_REG_PPE (0x1 << 13) +#define LTQ_ES_P0_VLAN_REG_PPE_VAL(val) (((val) & 0x1) << 13) +#define LTQ_ES_P0_VLAN_REG_PPE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PPE) >> 13) & 0x1) +#define LTQ_ES_P0_VLAN_REG_PPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PPE) | (((val) & 0x1) << 13)) +/* Portbase VLAN tag member for Port 0 (12) */ +#define LTQ_ES_P0_VLAN_REG_PVTAGMP (0x1 << 12) +#define LTQ_ES_P0_VLAN_REG_PVTAGMP_VAL(val) (((val) & 0x1) << 12) +#define LTQ_ES_P0_VLAN_REG_PVTAGMP_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PVTAGMP) >> 12) & 0x1) +#define LTQ_ES_P0_VLAN_REG_PVTAGMP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PVTAGMP) | (((val) & 0x1) << 12)) +/* PVID (11:0) */ +#define LTQ_ES_P0_VLAN_REG_PVID (0xfff) +#define LTQ_ES_P0_VLAN_REG_PVID_VAL(val) (((val) & 0xfff) << 0) +#define LTQ_ES_P0_VLAN_REG_PVID_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PVID) >> 0) & 0xfff) +#define LTQ_ES_P0_VLAN_REG_PVID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PVID) | (((val) & 0xfff) << 0)) + +/******************************************************************************* + * Port 0 Ingress Control Register + ******************************************************************************/ + +/* Reserved (31:13) */ +#define LTQ_ES_P0_INCTL_REG_RES (0x7ffff << 13) +#define LTQ_ES_P0_INCTL_REG_RES_GET(val) ((((val) & LTQ_ES_P0_INCTL_REG_RES) >> 13) & 0x7ffff) +/* Port 0 Ingress/Egress Timer Tick T selection (12:11) */ +#define LTQ_ES_P0_INCTL_REG_P0ITT (0x3 << 11) +#define LTQ_ES_P0_INCTL_REG_P0ITT_VAL(val) (((val) & 0x3) << 11) +#define LTQ_ES_P0_INCTL_REG_P0ITT_GET(val) ((((val) & LTQ_ES_P0_INCTL_REG_P0ITT) >> 11) & 0x3) +#define LTQ_ES_P0_INCTL_REG_P0ITT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_INCTL_REG_P0ITT) | (((val) & 0x3) << 11)) +/* Port 0 Igress Token R (10:0) */ +#define LTQ_ES_P0_INCTL_REG_P0ITR (0x7ff) +#define LTQ_ES_P0_INCTL_REG_P0ITR_VAL(val) (((val) & 0x7ff) << 0) +#define LTQ_ES_P0_INCTL_REG_P0ITR_GET(val) ((((val) & LTQ_ES_P0_INCTL_REG_P0ITR) >> 0) & 0x7ff) +#define LTQ_ES_P0_INCTL_REG_P0ITR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_INCTL_REG_P0ITR) | (((val) & 0x7ff) << 0)) + +/******************************************************************************* + * Port 0 Egress Control for Strict Q32 Register + ******************************************************************************/ + +/* Port 0 Egress Token R for Strict Priority Q3 (26:16) */ +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR (0x7ff << 16) +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR_VAL(val) (((val) & 0x7ff) << 16) +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR) >> 16) & 0x7ff) +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR) | (((val) & 0x7ff) << 16)) +/* Port 0 Egress Token R for Strict Priority Q2 (10:0) */ +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR (0x7ff) +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR_VAL(val) (((val) & 0x7ff) << 0) +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR) >> 0) & 0x7ff) +#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR) | (((val) & 0x7ff) << 0)) + +/******************************************************************************* + * Port 0 Egress Control for Strict Q10 Register + ******************************************************************************/ + +/* Reserved (31:27) */ +#define LTQ_ES_P0_ECS_Q10_REG_RES (0x1f << 27) +#define LTQ_ES_P0_ECS_Q10_REG_RES_GET(val) ((((val) & LTQ_ES_P0_ECS_Q10_REG_RES) >> 27) & 0x1f) +/* Port 0 Egress Token R for Strict Priority Q1 (26:16) */ +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR (0x7ff << 16) +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR_VAL(val) (((val) & 0x7ff) << 16) +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR) >> 16) & 0x7ff) +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR) | (((val) & 0x7ff) << 16)) +/* Port 0 Egress Token R for Strict Priority Q0 (10:0) */ +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR (0x7ff) +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR_VAL(val) (((val) & 0x7ff) << 0) +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR) >> 0) & 0x7ff) +#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR) | (((val) & 0x7ff) << 0)) + +/******************************************************************************* + * Port 0 Egress Control for WFQ Q32 Register + ******************************************************************************/ + +/* Reserved (31:27) */ +#define LTQ_ES_P0_ECW_Q32_REG_RES (0x1f << 27) +#define LTQ_ES_P0_ECW_Q32_REG_RES_GET(val) ((((val) & LTQ_ES_P0_ECW_Q32_REG_RES) >> 27) & 0x1f) +/* Port 0 Egress Token R for WFQ Q3 (26:16) */ +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR (0x7ff << 16) +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR_VAL(val) (((val) & 0x7ff) << 16) +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR) >> 16) & 0x7ff) +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR) | (((val) & 0x7ff) << 16)) +/* Port 0 Egress Token R for WFQ Q2 (10:0) */ +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR (0x7ff) +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR_VAL(val) (((val) & 0x7ff) << 0) +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR) >> 0) & 0x7ff) +#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR) | (((val) & 0x7ff) << 0)) + +/******************************************************************************* + * Port 0 Egress Control for WFQ Q10 Register + ******************************************************************************/ + +/* Reserved (31:27) */ +#define LTQ_ES_P0_ECW_Q10_REG_RES (0x1f << 27) +#define LTQ_ES_P0_ECW_Q10_REG_RES_GET(val) ((((val) & LTQ_ES_P0_ECW_Q10_REG_RES) >> 27) & 0x1f) +/* Port 0 Egress Token R for WFQ Q1 (26:16) */ +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR (0x7ff << 16) +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR_VAL(val) (((val) & 0x7ff) << 16) +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR) >> 16) & 0x7ff) +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR) | (((val) & 0x7ff) << 16)) +/* Port 0 Egress Token R for WFQ Q0 (10:0) */ +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR (0x7ff) +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR_VAL(val) (((val) & 0x7ff) << 0) +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR) >> 0) & 0x7ff) +#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR) | (((val) & 0x7ff) << 0)) + +/******************************************************************************* + * Interrupt Enable Register + ******************************************************************************/ + +/* Reserved (31:8) */ +#define LTQ_ES_INT_ENA_REG_RES (0xffffff << 8) +#define LTQ_ES_INT_ENA_REG_RES_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_RES) >> 8) & 0xffffff) +/* Data Buffer is Full Interrupt Enable (7) */ +#define LTQ_ES_INT_ENA_REG_DBFIE (0x1 << 7) +#define LTQ_ES_INT_ENA_REG_DBFIE_VAL(val) (((val) & 0x1) << 7) +#define LTQ_ES_INT_ENA_REG_DBFIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_DBFIE) >> 7) & 0x1) +#define LTQ_ES_INT_ENA_REG_DBFIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_DBFIE) | (((val) & 0x1) << 7)) +/* Data Buffer is nearly Full Interrupt Enable (6) */ +#define LTQ_ES_INT_ENA_REG_DBNFIE (0x1 << 6) +#define LTQ_ES_INT_ENA_REG_DBNFIE_VAL(val) (((val) & 0x1) << 6) +#define LTQ_ES_INT_ENA_REG_DBNFIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_DBNFIE) >> 6) & 0x1) +#define LTQ_ES_INT_ENA_REG_DBNFIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_DBNFIE) | (((val) & 0x1) << 6)) +/* Learning Table Full Interrupt Enable (5) */ +#define LTQ_ES_INT_ENA_REG_LTFIE (0x1 << 5) +#define LTQ_ES_INT_ENA_REG_LTFIE_VAL(val) (((val) & 0x1) << 5) +#define LTQ_ES_INT_ENA_REG_LTFIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_LTFIE) >> 5) & 0x1) +#define LTQ_ES_INT_ENA_REG_LTFIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_LTFIE) | (((val) & 0x1) << 5)) +/* Leaning Table Access Done Interrupt Enable (4) */ +#define LTQ_ES_INT_ENA_REG_LTADIE (0x1 << 4) +#define LTQ_ES_INT_ENA_REG_LTADIE_VAL(val) (((val) & 0x1) << 4) +#define LTQ_ES_INT_ENA_REG_LTADIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_LTADIE) >> 4) & 0x1) +#define LTQ_ES_INT_ENA_REG_LTADIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_LTADIE) | (((val) & 0x1) << 4)) +/* Port Security Violation Interrupt Enable (3:1) */ +#define LTQ_ES_INT_ENA_REG_PSVIE (0x7 << 1) +#define LTQ_ES_INT_ENA_REG_PSVIE_VAL(val) (((val) & 0x7) << 1) +#define LTQ_ES_INT_ENA_REG_PSVIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_PSVIE) >> 1) & 0x7) +#define LTQ_ES_INT_ENA_REG_PSVIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_PSVIE) | (((val) & 0x7) << 1)) +/* Port Status Change Interrupt Enable (0) */ +#define LTQ_ES_INT_ENA_REG_PSCIE (0x1) +#define LTQ_ES_INT_ENA_REG_PSCIE_VAL(val) (((val) & 0x1) << 0) +#define LTQ_ES_INT_ENA_REG_PSCIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_PSCIE) >> 0) & 0x1) +#define LTQ_ES_INT_ENA_REG_PSCIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_PSCIE) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Interrupt Status Register + ******************************************************************************/ + +/* Reserved (31:8) */ +#define LTQ_ES_INT_ST_REG_RES (0xffffff << 8) +#define LTQ_ES_INT_ST_REG_RES_GET(val) ((((val) & LTQ_ES_INT_ST_REG_RES) >> 8) & 0xffffff) +/* Data Buffer is Full (7) */ +#define LTQ_ES_INT_ST_REG_DBF (0x1 << 7) +#define LTQ_ES_INT_ST_REG_DBF_GET(val) ((((val) & LTQ_ES_INT_ST_REG_DBF) >> 7) & 0x1) +/* Data Buffer is nearly Full (6) */ +#define LTQ_ES_INT_ST_REG_DBNF (0x1 << 6) +#define LTQ_ES_INT_ST_REG_DBNF_GET(val) ((((val) & LTQ_ES_INT_ST_REG_DBNF) >> 6) & 0x1) +/* Learning Table Full (5) */ +#define LTQ_ES_INT_ST_REG_LTF (0x1 << 5) +#define LTQ_ES_INT_ST_REG_LTF_GET(val) ((((val) & LTQ_ES_INT_ST_REG_LTF) >> 5) & 0x1) +/* Leaning Table Access Done (4) */ +#define LTQ_ES_INT_ST_REG_LTAD (0x1 << 4) +#define LTQ_ES_INT_ST_REG_LTAD_GET(val) ((((val) & LTQ_ES_INT_ST_REG_LTAD) >> 4) & 0x1) +/* Port Security Violation (3:1) */ +#define LTQ_ES_INT_ST_REG_PSV (0x7 << 1) +#define LTQ_ES_INT_ST_REG_PSV_GET(val) ((((val) & LTQ_ES_INT_ST_REG_PSV) >> 1) & 0x7) +/* Port Status Change (0) */ +#define LTQ_ES_INT_ST_REG_PSC (0x1) +#define LTQ_ES_INT_ST_REG_PSC_GET(val) ((((val) & LTQ_ES_INT_ST_REG_PSC) >> 0) & 0x1) + +/******************************************************************************* + * Switch Global Control Register 0 + ******************************************************************************/ + +/* Switch Enable (31) */ +#define LTQ_ES_SW_GCTL0_REG_SE (0x1 << 31) +#define LTQ_ES_SW_GCTL0_REG_SE_VAL(val) (((val) & 0x1) << 31) +#define LTQ_ES_SW_GCTL0_REG_SE_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_SE) >> 31) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_SE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_SE) | (((val) & 0x1) << 31)) +/* CRC Check Disable (30) */ +#define LTQ_ES_SW_GCTL0_REG_ICRCCD (0x1 << 30) +#define LTQ_ES_SW_GCTL0_REG_ICRCCD_VAL(val) (((val) & 0x1) << 30) +#define LTQ_ES_SW_GCTL0_REG_ICRCCD_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_ICRCCD) >> 30) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_ICRCCD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_ICRCCD) | (((val) & 0x1) << 30)) +/* Replace VID0 (28) */ +#define LTQ_ES_SW_GCTL0_REG_RVID0 (0x1 << 28) +#define LTQ_ES_SW_GCTL0_REG_RVID0_VAL(val) (((val) & 0x1) << 28) +#define LTQ_ES_SW_GCTL0_REG_RVID0_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_RVID0) >> 28) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_RVID0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_RVID0) | (((val) & 0x1) << 28)) +/* Replace VID1 (27) */ +#define LTQ_ES_SW_GCTL0_REG_RVID1 (0x1 << 27) +#define LTQ_ES_SW_GCTL0_REG_RVID1_VAL(val) (((val) & 0x1) << 27) +#define LTQ_ES_SW_GCTL0_REG_RVID1_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_RVID1) >> 27) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_RVID1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_RVID1) | (((val) & 0x1) << 27)) +/* Replace VIDFFF (26) */ +#define LTQ_ES_SW_GCTL0_REG_RVIDFFF (0x1 << 26) +#define LTQ_ES_SW_GCTL0_REG_RVIDFFF_VAL(val) (((val) & 0x1) << 26) +#define LTQ_ES_SW_GCTL0_REG_RVIDFFF_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_RVIDFFF) >> 26) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_RVIDFFF_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_RVIDFFF) | (((val) & 0x1) << 26)) +/* Priority Change Rule (25) */ +#define LTQ_ES_SW_GCTL0_REG_PCR (0x1 << 25) +#define LTQ_ES_SW_GCTL0_REG_PCR_VAL(val) (((val) & 0x1) << 25) +#define LTQ_ES_SW_GCTL0_REG_PCR_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_PCR) >> 25) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_PCR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_PCR) | (((val) & 0x1) << 25)) +/* Priority Change Enable (24) */ +#define LTQ_ES_SW_GCTL0_REG_PCE (0x1 << 24) +#define LTQ_ES_SW_GCTL0_REG_PCE_VAL(val) (((val) & 0x1) << 24) +#define LTQ_ES_SW_GCTL0_REG_PCE_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_PCE) >> 24) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_PCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_PCE) | (((val) & 0x1) << 24)) +/* Transmit Short IPG Enable (23) */ +#define LTQ_ES_SW_GCTL0_REG_TSIPGE (0x1 << 23) +#define LTQ_ES_SW_GCTL0_REG_TSIPGE_VAL(val) (((val) & 0x1) << 23) +#define LTQ_ES_SW_GCTL0_REG_TSIPGE_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_TSIPGE) >> 23) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_TSIPGE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_TSIPGE) | (((val) & 0x1) << 23)) +/* PHY Base Address (22) */ +#define LTQ_ES_SW_GCTL0_REG_PHYBA (0x1 << 22) +#define LTQ_ES_SW_GCTL0_REG_PHYBA_VAL(val) (((val) & 0x1) << 22) +#define LTQ_ES_SW_GCTL0_REG_PHYBA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_PHYBA) >> 22) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_PHYBA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_PHYBA) | (((val) & 0x1) << 22)) +/* Drop Packet When Excessive Collision Happen (21) */ +#define LTQ_ES_SW_GCTL0_REG_DPWECH (0x1 << 21) +#define LTQ_ES_SW_GCTL0_REG_DPWECH_VAL(val) (((val) & 0x1) << 21) +#define LTQ_ES_SW_GCTL0_REG_DPWECH_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DPWECH) >> 21) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_DPWECH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DPWECH) | (((val) & 0x1) << 21)) +/* Aging Timer Select (20:18) */ +#define LTQ_ES_SW_GCTL0_REG_ATS (0x7 << 18) +#define LTQ_ES_SW_GCTL0_REG_ATS_VAL(val) (((val) & 0x7) << 18) +#define LTQ_ES_SW_GCTL0_REG_ATS_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_ATS) >> 18) & 0x7) +#define LTQ_ES_SW_GCTL0_REG_ATS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_ATS) | (((val) & 0x7) << 18)) +/* Mirror CRC Also (17) */ +#define LTQ_ES_SW_GCTL0_REG_MCA (0x1 << 17) +#define LTQ_ES_SW_GCTL0_REG_MCA_VAL(val) (((val) & 0x1) << 17) +#define LTQ_ES_SW_GCTL0_REG_MCA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MCA) >> 17) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_MCA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MCA) | (((val) & 0x1) << 17)) +/* Mirror RXER Also (16) */ +#define LTQ_ES_SW_GCTL0_REG_MRA (0x1 << 16) +#define LTQ_ES_SW_GCTL0_REG_MRA_VAL(val) (((val) & 0x1) << 16) +#define LTQ_ES_SW_GCTL0_REG_MRA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MRA) >> 16) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_MRA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MRA) | (((val) & 0x1) << 16)) +/* Mirror PAUSE Also (15) */ +#define LTQ_ES_SW_GCTL0_REG_MPA (0x1 << 15) +#define LTQ_ES_SW_GCTL0_REG_MPA_VAL(val) (((val) & 0x1) << 15) +#define LTQ_ES_SW_GCTL0_REG_MPA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MPA) >> 15) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_MPA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MPA) | (((val) & 0x1) << 15)) +/* Mirror Long Also (14) */ +#define LTQ_ES_SW_GCTL0_REG_MLA (0x1 << 14) +#define LTQ_ES_SW_GCTL0_REG_MLA_VAL(val) (((val) & 0x1) << 14) +#define LTQ_ES_SW_GCTL0_REG_MLA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MLA) >> 14) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_MLA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MLA) | (((val) & 0x1) << 14)) +/* Mirror Short Also (13) */ +#define LTQ_ES_SW_GCTL0_REG_MSA (0x1 << 13) +#define LTQ_ES_SW_GCTL0_REG_MSA_VAL(val) (((val) & 0x1) << 13) +#define LTQ_ES_SW_GCTL0_REG_MSA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MSA) >> 13) & 0x1) +#define LTQ_ES_SW_GCTL0_REG_MSA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MSA) | (((val) & 0x1) << 13)) +/* Sniffer port number (12:11) */ +#define LTQ_ES_SW_GCTL0_REG_SNIFFPN (0x3 << 11) +#define LTQ_ES_SW_GCTL0_REG_SNIFFPN_VAL(val) (((val) & 0x3) << 11) +#define LTQ_ES_SW_GCTL0_REG_SNIFFPN_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_SNIFFPN) >> 11) & 0x3) +#define LTQ_ES_SW_GCTL0_REG_SNIFFPN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_SNIFFPN) | (((val) & 0x3) << 11)) +/* Max Packet Length (MAXPKTLEN) (9:8) */ +#define LTQ_ES_SW_GCTL0_REG_MPL (0x3 << 8) +#define LTQ_ES_SW_GCTL0_REG_MPL_VAL(val) (((val) & 0x3) << 8) +#define LTQ_ES_SW_GCTL0_REG_MPL_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MPL) >> 8) & 0x3) +#define LTQ_ES_SW_GCTL0_REG_MPL_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MPL) | (((val) & 0x3) << 8)) +/* Discard Mode (Drop scheme for Packets Classified as Q3) (7:6) */ +#define LTQ_ES_SW_GCTL0_REG_DMQ3 (0x3 << 6) +#define LTQ_ES_SW_GCTL0_REG_DMQ3_VAL(val) (((val) & 0x3) << 6) +#define LTQ_ES_SW_GCTL0_REG_DMQ3_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ3) >> 6) & 0x3) +#define LTQ_ES_SW_GCTL0_REG_DMQ3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ3) | (((val) & 0x3) << 6)) +/* Discard Mode (Drop scheme for Packets Classified as Q2) (5:4) */ +#define LTQ_ES_SW_GCTL0_REG_DMQ2 (0x3 << 4) +#define LTQ_ES_SW_GCTL0_REG_DMQ2_VAL(val) (((val) & 0x3) << 4) +#define LTQ_ES_SW_GCTL0_REG_DMQ2_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ2) >> 4) & 0x3) +#define LTQ_ES_SW_GCTL0_REG_DMQ2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ2) | (((val) & 0x3) << 4)) +/* Discard Mode (Drop scheme for Packets Classified as Q1) (3:2) */ +#define LTQ_ES_SW_GCTL0_REG_DMQ1 (0x3 << 2) +#define LTQ_ES_SW_GCTL0_REG_DMQ1_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_SW_GCTL0_REG_DMQ1_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ1) >> 2) & 0x3) +#define LTQ_ES_SW_GCTL0_REG_DMQ1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ1) | (((val) & 0x3) << 2)) +/* Discard Mode (Drop scheme for Packets Classified as Q0) (1:0) */ +#define LTQ_ES_SW_GCTL0_REG_DMQ0 (0x3) +#define LTQ_ES_SW_GCTL0_REG_DMQ0_VAL(val) (((val) & 0x3) << 0) +#define LTQ_ES_SW_GCTL0_REG_DMQ0_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ0) >> 0) & 0x3) +#define LTQ_ES_SW_GCTL0_REG_DMQ0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ0) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * Switch Global Control Register 1 + ******************************************************************************/ + +/* BIST Done (27) */ +#define LTQ_ES_SW_GCTL1_REG_BISTDN (0x1 << 27) +#define LTQ_ES_SW_GCTL1_REG_BISTDN_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_BISTDN) >> 27) & 0x1) +/* Enable drop scheme of TX and RX (26) */ +#define LTQ_ES_SW_GCTL1_REG_EDSTX (0x1 << 26) +#define LTQ_ES_SW_GCTL1_REG_EDSTX_VAL(val) (((val) & 0x1) << 26) +#define LTQ_ES_SW_GCTL1_REG_EDSTX_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_EDSTX) >> 26) & 0x1) +#define LTQ_ES_SW_GCTL1_REG_EDSTX_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_EDSTX) | (((val) & 0x1) << 26)) +/* Congestion threshold for TX queue (25:24) */ +#define LTQ_ES_SW_GCTL1_REG_CTTX (0x3 << 24) +#define LTQ_ES_SW_GCTL1_REG_CTTX_VAL(val) (((val) & 0x3) << 24) +#define LTQ_ES_SW_GCTL1_REG_CTTX_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_CTTX) >> 24) & 0x3) +#define LTQ_ES_SW_GCTL1_REG_CTTX_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_CTTX) | (((val) & 0x3) << 24)) +/* Input Jam Threshold (23:21) */ +#define LTQ_ES_SW_GCTL1_REG_IJT (0x7 << 21) +#define LTQ_ES_SW_GCTL1_REG_IJT_VAL(val) (((val) & 0x7) << 21) +#define LTQ_ES_SW_GCTL1_REG_IJT_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_IJT) >> 21) & 0x7) +#define LTQ_ES_SW_GCTL1_REG_IJT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_IJT) | (((val) & 0x7) << 21)) +/* Do not Identify VLAN after SNAP (20) */ +#define LTQ_ES_SW_GCTL1_REG_DIVS (0x1 << 20) +#define LTQ_ES_SW_GCTL1_REG_DIVS_VAL(val) (((val) & 0x1) << 20) +#define LTQ_ES_SW_GCTL1_REG_DIVS_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIVS) >> 20) & 0x1) +#define LTQ_ES_SW_GCTL1_REG_DIVS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIVS) | (((val) & 0x1) << 20)) +/* Do not Identify IPV6 in PPPOE (19) */ +#define LTQ_ES_SW_GCTL1_REG_DII6P (0x1 << 19) +#define LTQ_ES_SW_GCTL1_REG_DII6P_VAL(val) (((val) & 0x1) << 19) +#define LTQ_ES_SW_GCTL1_REG_DII6P_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DII6P) >> 19) & 0x1) +#define LTQ_ES_SW_GCTL1_REG_DII6P_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DII6P) | (((val) & 0x1) << 19)) +/* Do not Identify IP in PPPOE after SNAP (18) */ +#define LTQ_ES_SW_GCTL1_REG_DIIPS (0x1 << 18) +#define LTQ_ES_SW_GCTL1_REG_DIIPS_VAL(val) (((val) & 0x1) << 18) +#define LTQ_ES_SW_GCTL1_REG_DIIPS_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIIPS) >> 18) & 0x1) +#define LTQ_ES_SW_GCTL1_REG_DIIPS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIIPS) | (((val) & 0x1) << 18)) +/* Do not Identify Ether-Type = 0x0800, IP VER = 6 as IPV6 packets (17) */ +#define LTQ_ES_SW_GCTL1_REG_DIE (0x1 << 17) +#define LTQ_ES_SW_GCTL1_REG_DIE_VAL(val) (((val) & 0x1) << 17) +#define LTQ_ES_SW_GCTL1_REG_DIE_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIE) >> 17) & 0x1) +#define LTQ_ES_SW_GCTL1_REG_DIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIE) | (((val) & 0x1) << 17)) +/* Do not Identify IP in PPPOE (16) */ +#define LTQ_ES_SW_GCTL1_REG_DIIP (0x1 << 16) +#define LTQ_ES_SW_GCTL1_REG_DIIP_VAL(val) (((val) & 0x1) << 16) +#define LTQ_ES_SW_GCTL1_REG_DIIP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIIP) >> 16) & 0x1) +#define LTQ_ES_SW_GCTL1_REG_DIIP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIIP) | (((val) & 0x1) << 16)) +/* Do not Identify SNAP (15) */ +#define LTQ_ES_SW_GCTL1_REG_DIS (0x1 << 15) +#define LTQ_ES_SW_GCTL1_REG_DIS_VAL(val) (((val) & 0x1) << 15) +#define LTQ_ES_SW_GCTL1_REG_DIS_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIS) >> 15) & 0x1) +#define LTQ_ES_SW_GCTL1_REG_DIS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIS) | (((val) & 0x1) << 15)) +/* Unicast Portmap (14:12) */ +#define LTQ_ES_SW_GCTL1_REG_UP (0x7 << 12) +#define LTQ_ES_SW_GCTL1_REG_UP_VAL(val) (((val) & 0x7) << 12) +#define LTQ_ES_SW_GCTL1_REG_UP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_UP) >> 12) & 0x7) +#define LTQ_ES_SW_GCTL1_REG_UP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_UP) | (((val) & 0x7) << 12)) +/* Broadcast Portmap (10:8) */ +#define LTQ_ES_SW_GCTL1_REG_BP (0x7 << 8) +#define LTQ_ES_SW_GCTL1_REG_BP_VAL(val) (((val) & 0x7) << 8) +#define LTQ_ES_SW_GCTL1_REG_BP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_BP) >> 8) & 0x7) +#define LTQ_ES_SW_GCTL1_REG_BP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_BP) | (((val) & 0x7) << 8)) +/* Multicast Portmap (6:4) */ +#define LTQ_ES_SW_GCTL1_REG_MP (0x7 << 4) +#define LTQ_ES_SW_GCTL1_REG_MP_VAL(val) (((val) & 0x7) << 4) +#define LTQ_ES_SW_GCTL1_REG_MP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_MP) >> 4) & 0x7) +#define LTQ_ES_SW_GCTL1_REG_MP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_MP) | (((val) & 0x7) << 4)) +/* Reserve Portmap (2:0) */ +#define LTQ_ES_SW_GCTL1_REG_RP (0x7) +#define LTQ_ES_SW_GCTL1_REG_RP_VAL(val) (((val) & 0x7) << 0) +#define LTQ_ES_SW_GCTL1_REG_RP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_RP) >> 0) & 0x7) +#define LTQ_ES_SW_GCTL1_REG_RP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_RP) | (((val) & 0x7) << 0)) + +/******************************************************************************* + * ARP/RARP Register + ******************************************************************************/ + +/* MAC Control Action (15:14) */ +#define LTQ_ES_ARP_REG_MACA (0x3 << 14) +#define LTQ_ES_ARP_REG_MACA_VAL(val) (((val) & 0x3) << 14) +#define LTQ_ES_ARP_REG_MACA_GET(val) ((((val) & LTQ_ES_ARP_REG_MACA) >> 14) & 0x3) +#define LTQ_ES_ARP_REG_MACA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_MACA) | (((val) & 0x3) << 14)) +/* Unicast packet Treated as Cross_VLAN packet (13) */ +#define LTQ_ES_ARP_REG_UPT (0x1 << 13) +#define LTQ_ES_ARP_REG_UPT_VAL(val) (((val) & 0x1) << 13) +#define LTQ_ES_ARP_REG_UPT_GET(val) ((((val) & LTQ_ES_ARP_REG_UPT) >> 13) & 0x1) +#define LTQ_ES_ARP_REG_UPT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_UPT) | (((val) & 0x1) << 13)) +/* RARP Packet Treated as Cross_VLAN Packet (12) */ +#define LTQ_ES_ARP_REG_RPT (0x1 << 12) +#define LTQ_ES_ARP_REG_RPT_VAL(val) (((val) & 0x1) << 12) +#define LTQ_ES_ARP_REG_RPT_GET(val) ((((val) & LTQ_ES_ARP_REG_RPT) >> 12) & 0x1) +#define LTQ_ES_ARP_REG_RPT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RPT) | (((val) & 0x1) << 12)) +/* RARP/ARP Packet Action (11:10) */ +#define LTQ_ES_ARP_REG_RAPA (0x3 << 10) +#define LTQ_ES_ARP_REG_RAPA_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_ARP_REG_RAPA_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPA) >> 10) & 0x3) +#define LTQ_ES_ARP_REG_RAPA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPA) | (((val) & 0x3) << 10)) +/* RARP/ARP Packet Priority Enable (9) */ +#define LTQ_ES_ARP_REG_RAPPE (0x1 << 9) +#define LTQ_ES_ARP_REG_RAPPE_VAL(val) (((val) & 0x1) << 9) +#define LTQ_ES_ARP_REG_RAPPE_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPPE) >> 9) & 0x1) +#define LTQ_ES_ARP_REG_RAPPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPPE) | (((val) & 0x1) << 9)) +/* RARP/ARP Packet Priority (8:7) */ +#define LTQ_ES_ARP_REG_RAPP (0x3 << 7) +#define LTQ_ES_ARP_REG_RAPP_VAL(val) (((val) & 0x3) << 7) +#define LTQ_ES_ARP_REG_RAPP_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPP) >> 7) & 0x3) +#define LTQ_ES_ARP_REG_RAPP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPP) | (((val) & 0x3) << 7)) +/* RARP/ARP Packet Output Tag Handle (6:5) */ +#define LTQ_ES_ARP_REG_RAPOTH (0x3 << 5) +#define LTQ_ES_ARP_REG_RAPOTH_VAL(val) (((val) & 0x3) << 5) +#define LTQ_ES_ARP_REG_RAPOTH_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPOTH) >> 5) & 0x3) +#define LTQ_ES_ARP_REG_RAPOTH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPOTH) | (((val) & 0x3) << 5)) +/* ARP Packet Treated as Cross _ VLAN Packet (4) */ +#define LTQ_ES_ARP_REG_APT (0x1 << 4) +#define LTQ_ES_ARP_REG_APT_VAL(val) (((val) & 0x1) << 4) +#define LTQ_ES_ARP_REG_APT_GET(val) ((((val) & LTQ_ES_ARP_REG_APT) >> 4) & 0x1) +#define LTQ_ES_ARP_REG_APT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_APT) | (((val) & 0x1) << 4)) +/* RARP/ARP Packet Treated as Management Packet (3) */ +#define LTQ_ES_ARP_REG_RAPTM (0x1 << 3) +#define LTQ_ES_ARP_REG_RAPTM_VAL(val) (((val) & 0x1) << 3) +#define LTQ_ES_ARP_REG_RAPTM_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPTM) >> 3) & 0x1) +#define LTQ_ES_ARP_REG_RAPTM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPTM) | (((val) & 0x1) << 3)) +/* RARP/ARP Packet Treated as Span Packet (2) */ +#define LTQ_ES_ARP_REG_TAPTS (0x1 << 2) +#define LTQ_ES_ARP_REG_TAPTS_VAL(val) (((val) & 0x1) << 2) +#define LTQ_ES_ARP_REG_TAPTS_GET(val) ((((val) & LTQ_ES_ARP_REG_TAPTS) >> 2) & 0x1) +#define LTQ_ES_ARP_REG_TAPTS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_TAPTS) | (((val) & 0x1) << 2)) +/* Trap ARP Packet (1) */ +#define LTQ_ES_ARP_REG_TAP (0x1 << 1) +#define LTQ_ES_ARP_REG_TAP_VAL(val) (((val) & 0x1) << 1) +#define LTQ_ES_ARP_REG_TAP_GET(val) ((((val) & LTQ_ES_ARP_REG_TAP) >> 1) & 0x1) +#define LTQ_ES_ARP_REG_TAP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_TAP) | (((val) & 0x1) << 1)) +/* Trap RARP Packet (0) */ +#define LTQ_ES_ARP_REG_TRP (0x1) +#define LTQ_ES_ARP_REG_TRP_VAL(val) (((val) & 0x1) << 0) +#define LTQ_ES_ARP_REG_TRP_GET(val) ((((val) & LTQ_ES_ARP_REG_TRP) >> 0) & 0x1) +#define LTQ_ES_ARP_REG_TRP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_TRP) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Storm control Register + ******************************************************************************/ + +/* Reserved (31:29) */ +#define LTQ_ES_STRM_CTL_REG_RES (0x7 << 29) +#define LTQ_ES_STRM_CTL_REG_RES_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_RES) >> 29) & 0x7) +/* 10M Threshold (28:16) */ +#define LTQ_ES_STRM_CTL_REG_STORM_10_TH (0x1fff << 16) +#define LTQ_ES_STRM_CTL_REG_STORM_10_TH_VAL(val) (((val) & 0x1fff) << 16) +#define LTQ_ES_STRM_CTL_REG_STORM_10_TH_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_10_TH) >> 16) & 0x1fff) +#define LTQ_ES_STRM_CTL_REG_STORM_10_TH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_10_TH) | (((val) & 0x1fff) << 16)) +/* Storm Enable for Broadcast Packets (15) */ +#define LTQ_ES_STRM_CTL_REG_STORM_B (0x1 << 15) +#define LTQ_ES_STRM_CTL_REG_STORM_B_VAL(val) (((val) & 0x1) << 15) +#define LTQ_ES_STRM_CTL_REG_STORM_B_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_B) >> 15) & 0x1) +#define LTQ_ES_STRM_CTL_REG_STORM_B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_B) | (((val) & 0x1) << 15)) +/* Storm Enable for Multicast Packets (14) */ +#define LTQ_ES_STRM_CTL_REG_STORM_M (0x1 << 14) +#define LTQ_ES_STRM_CTL_REG_STORM_M_VAL(val) (((val) & 0x1) << 14) +#define LTQ_ES_STRM_CTL_REG_STORM_M_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_M) >> 14) & 0x1) +#define LTQ_ES_STRM_CTL_REG_STORM_M_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_M) | (((val) & 0x1) << 14)) +/* Storm Enable for Un-learned Unicast Packets (13) */ +#define LTQ_ES_STRM_CTL_REG_STORM_U (0x1 << 13) +#define LTQ_ES_STRM_CTL_REG_STORM_U_VAL(val) (((val) & 0x1) << 13) +#define LTQ_ES_STRM_CTL_REG_STORM_U_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_U) >> 13) & 0x1) +#define LTQ_ES_STRM_CTL_REG_STORM_U_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_U) | (((val) & 0x1) << 13)) +/* 100M Threshold (12:0) */ +#define LTQ_ES_STRM_CTL_REG_STORM_100_TH (0x1fff) +#define LTQ_ES_STRM_CTL_REG_STORM_100_TH_VAL(val) (((val) & 0x1fff) << 0) +#define LTQ_ES_STRM_CTL_REG_STORM_100_TH_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_100_TH) >> 0) & 0x1fff) +#define LTQ_ES_STRM_CTL_REG_STORM_100_TH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_100_TH) | (((val) & 0x1fff) << 0)) + +/******************************************************************************* + * RGMII/GMII Port Control Register + ******************************************************************************/ + +/* Management Clock Select (31:24) */ +#define LTQ_ES_RGMII_CTL_REG_MCS (0xff << 24) +#define LTQ_ES_RGMII_CTL_REG_MCS_VAL(val) (((val) & 0xff) << 24) +#define LTQ_ES_RGMII_CTL_REG_MCS_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_MCS) >> 24) & 0xff) +#define LTQ_ES_RGMII_CTL_REG_MCS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_MCS) | (((val) & 0xff) << 24)) +/* Interface Selection (19:18) */ +#define LTQ_ES_RGMII_CTL_REG_IS (0x3 << 18) +#define LTQ_ES_RGMII_CTL_REG_IS_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_IS) >> 18) & 0x3) +/* Port 1 RGMII Rx Clock Delay (17:16) */ +#define LTQ_ES_RGMII_CTL_REG_P1RDLY (0x3 << 16) +#define LTQ_ES_RGMII_CTL_REG_P1RDLY_VAL(val) (((val) & 0x3) << 16) +#define LTQ_ES_RGMII_CTL_REG_P1RDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1RDLY) >> 16) & 0x3) +#define LTQ_ES_RGMII_CTL_REG_P1RDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1RDLY) | (((val) & 0x3) << 16)) +/* Port 1 RGMII Tx Clock Delay (15:14) */ +#define LTQ_ES_RGMII_CTL_REG_P1TDLY (0x3 << 14) +#define LTQ_ES_RGMII_CTL_REG_P1TDLY_VAL(val) (((val) & 0x3) << 14) +#define LTQ_ES_RGMII_CTL_REG_P1TDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1TDLY) >> 14) & 0x3) +#define LTQ_ES_RGMII_CTL_REG_P1TDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1TDLY) | (((val) & 0x3) << 14)) +/* Port 1 Speed (13:12) */ +#define LTQ_ES_RGMII_CTL_REG_P1SPD (0x3 << 12) +#define LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(val) (((val) & 0x3) << 12) +#define LTQ_ES_RGMII_CTL_REG_P1SPD_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1SPD) >> 12) & 0x3) +#define LTQ_ES_RGMII_CTL_REG_P1SPD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1SPD) | (((val) & 0x3) << 12)) +/* Port 1 Duplex mode (11) */ +#define LTQ_ES_RGMII_CTL_REG_P1DUP (0x1 << 11) +#define LTQ_ES_RGMII_CTL_REG_P1DUP_VAL(val) (((val) & 0x1) << 11) +#define LTQ_ES_RGMII_CTL_REG_P1DUP_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1DUP) >> 11) & 0x1) +#define LTQ_ES_RGMII_CTL_REG_P1DUP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1DUP) | (((val) & 0x1) << 11)) +/* Port 1 Flow Control Enable (10) */ +#define LTQ_ES_RGMII_CTL_REG_P1FCE (0x1 << 10) +#define LTQ_ES_RGMII_CTL_REG_P1FCE_VAL(val) (((val) & 0x1) << 10) +#define LTQ_ES_RGMII_CTL_REG_P1FCE_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1FCE) >> 10) & 0x1) +#define LTQ_ES_RGMII_CTL_REG_P1FCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1FCE) | (((val) & 0x1) << 10)) +/* Port 0 RGMII Rx Clock Delay (7:6) */ +#define LTQ_ES_RGMII_CTL_REG_P0RDLY (0x3 << 6) +#define LTQ_ES_RGMII_CTL_REG_P0RDLY_VAL(val) (((val) & 0x3) << 6) +#define LTQ_ES_RGMII_CTL_REG_P0RDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0RDLY) >> 6) & 0x3) +#define LTQ_ES_RGMII_CTL_REG_P0RDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0RDLY) | (((val) & 0x3) << 6)) +/* Port 0 RGMII Tx Clock Delay (5:4) */ +#define LTQ_ES_RGMII_CTL_REG_P0TDLY (0x3 << 4) +#define LTQ_ES_RGMII_CTL_REG_P0TDLY_VAL(val) (((val) & 0x3) << 4) +#define LTQ_ES_RGMII_CTL_REG_P0TDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0TDLY) >> 4) & 0x3) +#define LTQ_ES_RGMII_CTL_REG_P0TDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0TDLY) | (((val) & 0x3) << 4)) +/* Port 0 Speed (3:2) */ +#define LTQ_ES_RGMII_CTL_REG_P0SPD (0x3 << 2) +#define LTQ_ES_RGMII_CTL_REG_P0SPD_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_RGMII_CTL_REG_P0SPD_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0SPD) >> 2) & 0x3) +#define LTQ_ES_RGMII_CTL_REG_P0SPD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0SPD) | (((val) & 0x3) << 2)) +/* Port 0 Duplex mode (1) */ +#define LTQ_ES_RGMII_CTL_REG_P0DUP (0x1 << 1) +#define LTQ_ES_RGMII_CTL_REG_P0DUP_VAL(val) (((val) & 0x1) << 1) +#define LTQ_ES_RGMII_CTL_REG_P0DUP_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0DUP) >> 1) & 0x1) +#define LTQ_ES_RGMII_CTL_REG_P0DUP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0DUP) | (((val) & 0x1) << 1)) +/* Port 0 Flow Control Enable (0) */ +#define LTQ_ES_RGMII_CTL_REG_P0FCE (0x1) +#define LTQ_ES_RGMII_CTL_REG_P0FCE_VAL(val) (((val) & 0x1) << 0) +#define LTQ_ES_RGMII_CTL_REG_P0FCE_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0FCE) >> 0) & 0x1) +#define LTQ_ES_RGMII_CTL_REG_P0FCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0FCE) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * 802.1p Priority Map Register + ******************************************************************************/ + +/* Priority Queue 7 (15:14) */ +#define LTQ_ES_PRT_1P_REG_1PPQ7 (0x3 << 14) +#define LTQ_ES_PRT_1P_REG_1PPQ7_VAL(val) (((val) & 0x3) << 14) +#define LTQ_ES_PRT_1P_REG_1PPQ7_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ7) >> 14) & 0x3) +#define LTQ_ES_PRT_1P_REG_1PPQ7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ7) | (((val) & 0x3) << 14)) +/* Priority Queue 6 (13:12) */ +#define LTQ_ES_PRT_1P_REG_1PPQ6 (0x3 << 12) +#define LTQ_ES_PRT_1P_REG_1PPQ6_VAL(val) (((val) & 0x3) << 12) +#define LTQ_ES_PRT_1P_REG_1PPQ6_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ6) >> 12) & 0x3) +#define LTQ_ES_PRT_1P_REG_1PPQ6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ6) | (((val) & 0x3) << 12)) +/* Priority Queue 5 (11:10) */ +#define LTQ_ES_PRT_1P_REG_1PPQ5 (0x3 << 10) +#define LTQ_ES_PRT_1P_REG_1PPQ5_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_PRT_1P_REG_1PPQ5_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ5) >> 10) & 0x3) +#define LTQ_ES_PRT_1P_REG_1PPQ5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ5) | (((val) & 0x3) << 10)) +/* Priority Queue 4 (9:8) */ +#define LTQ_ES_PRT_1P_REG_1PPQ4 (0x3 << 8) +#define LTQ_ES_PRT_1P_REG_1PPQ4_VAL(val) (((val) & 0x3) << 8) +#define LTQ_ES_PRT_1P_REG_1PPQ4_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ4) >> 8) & 0x3) +#define LTQ_ES_PRT_1P_REG_1PPQ4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ4) | (((val) & 0x3) << 8)) +/* Priority Queue 3 (7:6) */ +#define LTQ_ES_PRT_1P_REG_1PPQ3 (0x3 << 6) +#define LTQ_ES_PRT_1P_REG_1PPQ3_VAL(val) (((val) & 0x3) << 6) +#define LTQ_ES_PRT_1P_REG_1PPQ3_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ3) >> 6) & 0x3) +#define LTQ_ES_PRT_1P_REG_1PPQ3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ3) | (((val) & 0x3) << 6)) +/* Priority Queue 2 (5:4) */ +#define LTQ_ES_PRT_1P_REG_1PPQ2 (0x3 << 4) +#define LTQ_ES_PRT_1P_REG_1PPQ2_VAL(val) (((val) & 0x3) << 4) +#define LTQ_ES_PRT_1P_REG_1PPQ2_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ2) >> 4) & 0x3) +#define LTQ_ES_PRT_1P_REG_1PPQ2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ2) | (((val) & 0x3) << 4)) +/* Priority Queue 1 (3:2) */ +#define LTQ_ES_PRT_1P_REG_1PPQ1 (0x3 << 2) +#define LTQ_ES_PRT_1P_REG_1PPQ1_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_PRT_1P_REG_1PPQ1_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ1) >> 2) & 0x3) +#define LTQ_ES_PRT_1P_REG_1PPQ1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ1) | (((val) & 0x3) << 2)) +/* Priority Queue 0 (1:0) */ +#define LTQ_ES_PRT_1P_REG_1PPQ0 (0x3) +#define LTQ_ES_PRT_1P_REG_1PPQ0_VAL(val) (((val) & 0x3) << 0) +#define LTQ_ES_PRT_1P_REG_1PPQ0_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ0) >> 0) & 0x3) +#define LTQ_ES_PRT_1P_REG_1PPQ0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ0) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * Global Bucket Size Base counter + ******************************************************************************/ + +/* Reserved (31:18) */ +#define LTQ_ES_GBKT_SZBS_REG_REV (0x3fff << 18) +#define LTQ_ES_GBKT_SZBS_REG_REV_GET(val) ((((val) & LTQ_ES_GBKT_SZBS_REG_REV) >> 18) & 0x3fff) +/* Base[17:0] (17:0) */ +#define LTQ_ES_GBKT_SZBS_REG_BASE17_0 (0x3ffff) +#define LTQ_ES_GBKT_SZBS_REG_BASE17_0_VAL(val) (((val) & 0x3ffff) << 0) +#define LTQ_ES_GBKT_SZBS_REG_BASE17_0_GET(val) ((((val) & LTQ_ES_GBKT_SZBS_REG_BASE17_0) >> 0) & 0x3ffff) +#define LTQ_ES_GBKT_SZBS_REG_BASE17_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_GBKT_SZBS_REG_BASE17_0) | (((val) & 0x3ffff) << 0)) + +/******************************************************************************* + * Global Bucket Size Extend Base Counter + ******************************************************************************/ + +/* Reserved (31:18) */ +#define LTQ_ES_GBKT_SZEBS_REG_REV (0x3fff << 18) +#define LTQ_ES_GBKT_SZEBS_REG_REV_GET(val) ((((val) & LTQ_ES_GBKT_SZEBS_REG_REV) >> 18) & 0x3fff) +/* Extend Base[17:0] (17:0) */ +#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0 (0x3ffff) +#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0_VAL(val) (((val) & 0x3ffff) << 0) +#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0_GET(val) ((((val) & LTQ_ES_GBKT_SZEBS_REG_EBASE17_0) >> 0) & 0x3ffff) +#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_GBKT_SZEBS_REG_EBASE17_0) | (((val) & 0x3ffff) << 0)) + +/******************************************************************************* + * Buffer Threshold Register + ******************************************************************************/ + +/* Port Unfull Offset 3 (31:30) */ +#define LTQ_ES_BF_TH_REG_PUO3 (0x3 << 30) +#define LTQ_ES_BF_TH_REG_PUO3_VAL(val) (((val) & 0x3) << 30) +#define LTQ_ES_BF_TH_REG_PUO3_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO3) >> 30) & 0x3) +#define LTQ_ES_BF_TH_REG_PUO3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO3) | (((val) & 0x3) << 30)) +/* Port Unfull Offset 2 (29:28) */ +#define LTQ_ES_BF_TH_REG_PUO2 (0x3 << 28) +#define LTQ_ES_BF_TH_REG_PUO2_VAL(val) (((val) & 0x3) << 28) +#define LTQ_ES_BF_TH_REG_PUO2_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO2) >> 28) & 0x3) +#define LTQ_ES_BF_TH_REG_PUO2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO2) | (((val) & 0x3) << 28)) +/* Port Unfull Offset 1 (27:26) */ +#define LTQ_ES_BF_TH_REG_PUO1 (0x3 << 26) +#define LTQ_ES_BF_TH_REG_PUO1_VAL(val) (((val) & 0x3) << 26) +#define LTQ_ES_BF_TH_REG_PUO1_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO1) >> 26) & 0x3) +#define LTQ_ES_BF_TH_REG_PUO1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO1) | (((val) & 0x3) << 26)) +/* Port Unfull Offset 0 (25:24) */ +#define LTQ_ES_BF_TH_REG_PUO0 (0x3 << 24) +#define LTQ_ES_BF_TH_REG_PUO0_VAL(val) (((val) & 0x3) << 24) +#define LTQ_ES_BF_TH_REG_PUO0_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO0) >> 24) & 0x3) +#define LTQ_ES_BF_TH_REG_PUO0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO0) | (((val) & 0x3) << 24)) +/* Port Full Offset 3 (23:22) */ +#define LTQ_ES_BF_TH_REG_PFO3 (0x3 << 22) +#define LTQ_ES_BF_TH_REG_PFO3_VAL(val) (((val) & 0x3) << 22) +#define LTQ_ES_BF_TH_REG_PFO3_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO3) >> 22) & 0x3) +#define LTQ_ES_BF_TH_REG_PFO3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO3) | (((val) & 0x3) << 22)) +/* Port Full Offset 2 (21:20) */ +#define LTQ_ES_BF_TH_REG_PFO2 (0x3 << 20) +#define LTQ_ES_BF_TH_REG_PFO2_VAL(val) (((val) & 0x3) << 20) +#define LTQ_ES_BF_TH_REG_PFO2_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO2) >> 20) & 0x3) +#define LTQ_ES_BF_TH_REG_PFO2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO2) | (((val) & 0x3) << 20)) +/* Port Full Offset 1 (19:18) */ +#define LTQ_ES_BF_TH_REG_PFO1 (0x3 << 18) +#define LTQ_ES_BF_TH_REG_PFO1_VAL(val) (((val) & 0x3) << 18) +#define LTQ_ES_BF_TH_REG_PFO1_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO1) >> 18) & 0x3) +#define LTQ_ES_BF_TH_REG_PFO1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO1) | (((val) & 0x3) << 18)) +/* Port Full Offset 0 (17:16) */ +#define LTQ_ES_BF_TH_REG_PFO0 (0x3 << 16) +#define LTQ_ES_BF_TH_REG_PFO0_VAL(val) (((val) & 0x3) << 16) +#define LTQ_ES_BF_TH_REG_PFO0_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO0) >> 16) & 0x3) +#define LTQ_ES_BF_TH_REG_PFO0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO0) | (((val) & 0x3) << 16)) +/* Reserved (15:14) */ +#define LTQ_ES_BF_TH_REG_RES (0x3 << 14) +#define LTQ_ES_BF_TH_REG_RES_GET(val) ((((val) & LTQ_ES_BF_TH_REG_RES) >> 14) & 0x3) +/* Total Low Add (13) */ +#define LTQ_ES_BF_TH_REG_TLA (0x1 << 13) +#define LTQ_ES_BF_TH_REG_TLA_VAL(val) (((val) & 0x1) << 13) +#define LTQ_ES_BF_TH_REG_TLA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_TLA) >> 13) & 0x1) +#define LTQ_ES_BF_TH_REG_TLA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_TLA) | (((val) & 0x1) << 13)) +/* Total High Add (12) */ +#define LTQ_ES_BF_TH_REG_THA (0x1 << 12) +#define LTQ_ES_BF_TH_REG_THA_VAL(val) (((val) & 0x1) << 12) +#define LTQ_ES_BF_TH_REG_THA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_THA) >> 12) & 0x1) +#define LTQ_ES_BF_TH_REG_THA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_THA) | (((val) & 0x1) << 12)) +/* Total Low Offset (11:10) */ +#define LTQ_ES_BF_TH_REG_TLO (0x3 << 10) +#define LTQ_ES_BF_TH_REG_TLO_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_BF_TH_REG_TLO_GET(val) ((((val) & LTQ_ES_BF_TH_REG_TLO) >> 10) & 0x3) +#define LTQ_ES_BF_TH_REG_TLO_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_TLO) | (((val) & 0x3) << 10)) +/* Total High Offset (9:8) */ +#define LTQ_ES_BF_TH_REG_THO (0x3 << 8) +#define LTQ_ES_BF_TH_REG_THO_VAL(val) (((val) & 0x3) << 8) +#define LTQ_ES_BF_TH_REG_THO_GET(val) ((((val) & LTQ_ES_BF_TH_REG_THO) >> 8) & 0x3) +#define LTQ_ES_BF_TH_REG_THO_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_THO) | (((val) & 0x3) << 8)) +/* Port Unfull Add (7:4) */ +#define LTQ_ES_BF_TH_REG_PUA (0xf << 4) +#define LTQ_ES_BF_TH_REG_PUA_VAL(val) (((val) & 0xf) << 4) +#define LTQ_ES_BF_TH_REG_PUA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUA) >> 4) & 0xf) +#define LTQ_ES_BF_TH_REG_PUA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUA) | (((val) & 0xf) << 4)) +/* Port Full Add (3:0) */ +#define LTQ_ES_BF_TH_REG_PFA (0xf) +#define LTQ_ES_BF_TH_REG_PFA_VAL(val) (((val) & 0xf) << 0) +#define LTQ_ES_BF_TH_REG_PFA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFA) >> 0) & 0xf) +#define LTQ_ES_BF_TH_REG_PFA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFA) | (((val) & 0xf) << 0)) + +/******************************************************************************* + * PMAC Header Control Register + ******************************************************************************/ + +/* Reserved (31:22) */ +#define LTQ_ES_PMAC_HD_CTL_RES (0x3ff << 22) +#define LTQ_ES_PMAC_HD_CTL_RES_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_RES) >> 22) & 0x3ff) +/* Remove Layer-2 Header from Packets Going from PMAC to DMA (21) */ +#define LTQ_ES_PMAC_HD_CTL_RL2 (0x1 << 21) +#define LTQ_ES_PMAC_HD_CTL_RL2_VAL(val) (((val) & 0x1) << 21) +#define LTQ_ES_PMAC_HD_CTL_RL2_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_RL2) >> 21) & 0x1) +#define LTQ_ES_PMAC_HD_CTL_RL2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_RL2) | (((val) & 0x1) << 21)) +/* Remove CRC from Packets Going from PMAC to DMA (20) */ +#define LTQ_ES_PMAC_HD_CTL_RC (0x1 << 20) +#define LTQ_ES_PMAC_HD_CTL_RC_VAL(val) (((val) & 0x1) << 20) +#define LTQ_ES_PMAC_HD_CTL_RC_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_RC) >> 20) & 0x1) +#define LTQ_ES_PMAC_HD_CTL_RC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_RC) | (((val) & 0x1) << 20)) +/* Status Header for Packets from PMAC to DMA (19) */ +#define LTQ_ES_PMAC_HD_CTL_AS (0x1 << 19) +#define LTQ_ES_PMAC_HD_CTL_AS_VAL(val) (((val) & 0x1) << 19) +#define LTQ_ES_PMAC_HD_CTL_AS_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_AS) >> 19) & 0x1) +#define LTQ_ES_PMAC_HD_CTL_AS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_AS) | (((val) & 0x1) << 19)) +/* Add CRC for packets from DMA to PMAC (18) */ +#define LTQ_ES_PMAC_HD_CTL_AC (0x1 << 18) +#define LTQ_ES_PMAC_HD_CTL_AC_VAL(val) (((val) & 0x1) << 18) +#define LTQ_ES_PMAC_HD_CTL_AC_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_AC) >> 18) & 0x1) +#define LTQ_ES_PMAC_HD_CTL_AC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_AC) | (((val) & 0x1) << 18)) +/* Contains the length/type value to the added to packets from DMA to PMAC (17:2) */ +#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN (0xffff << 2) +#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN_VAL(val) (((val) & 0xffff) << 2) +#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_TYPE_LEN) >> 2) & 0xffff) +#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_TYPE_LEN) | (((val) & 0xffff) << 2)) +/* Add TAG to Packets from DMA to PMAC (1) */ +#define LTQ_ES_PMAC_HD_CTL_TAG (0x1 << 1) +#define LTQ_ES_PMAC_HD_CTL_TAG_VAL(val) (((val) & 0x1) << 1) +#define LTQ_ES_PMAC_HD_CTL_TAG_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_TAG) >> 1) & 0x1) +#define LTQ_ES_PMAC_HD_CTL_TAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_TAG) | (((val) & 0x1) << 1)) +/* ADD Header to Packets from DMA to PMAC (0) */ +#define LTQ_ES_PMAC_HD_CTL_ADD (0x1) +#define LTQ_ES_PMAC_HD_CTL_ADD_VAL(val) (((val) & 0x1) << 0) +#define LTQ_ES_PMAC_HD_CTL_ADD_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_ADD) >> 0) & 0x1) +#define LTQ_ES_PMAC_HD_CTL_ADD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_ADD) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * PMAC Source Address Register 1 + ******************************************************************************/ + +/* Source Address to be inserted as a part of the Ethernet header. (15:0) */ +#define LTQ_ES_PMAC_SA1_SA_47_32 (0xffff) +#define LTQ_ES_PMAC_SA1_SA_47_32_VAL(val) (((val) & 0xffff) << 0) +#define LTQ_ES_PMAC_SA1_SA_47_32_GET(val) ((((val) & LTQ_ES_PMAC_SA1_SA_47_32) >> 0) & 0xffff) +#define LTQ_ES_PMAC_SA1_SA_47_32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_SA1_SA_47_32) | (((val) & 0xffff) << 0)) + +/******************************************************************************* + * PMAC Source Address Register 2 + ******************************************************************************/ + +/* Source Address (31:0) */ +#define LTQ_ES_PMAC_SA2_SA_31_0 (0xFFFFFFFFL) +#define LTQ_ES_PMAC_SA2_SA_31_0_VAL(val) (((val) & 0xFFFFFFFFL) << 0) +#define LTQ_ES_PMAC_SA2_SA_31_0_GET(val) ((((val) & LTQ_ES_PMAC_SA2_SA_31_0) >> 0) & 0xFFFFFFFFL) +#define LTQ_ES_PMAC_SA2_SA_31_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_SA2_SA_31_0) | (((val) & 0xFFFFFFFFL) << 0)) + +/******************************************************************************* + * PMAC Destination Address Register 1 + ******************************************************************************/ + +/* Destination Address (15:0) */ +#define LTQ_ES_PMAC_DA1_DA_47_32 (0xffff) +#define LTQ_ES_PMAC_DA1_DA_47_32_VAL(val) (((val) & 0xffff) << 0) +#define LTQ_ES_PMAC_DA1_DA_47_32_GET(val) ((((val) & LTQ_ES_PMAC_DA1_DA_47_32) >> 0) & 0xffff) +#define LTQ_ES_PMAC_DA1_DA_47_32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_DA1_DA_47_32) | (((val) & 0xffff) << 0)) + +/******************************************************************************* + * PMAC Destination Address Register 2 + ******************************************************************************/ + +/* Destination Address to be inserted as a part of the Ethernet header. (31:0) */ +#define LTQ_ES_PMAC_DA2_DA_31_0 (0xFFFFFFFFL) +#define LTQ_ES_PMAC_DA2_DA_31_0_VAL(val) (((val) & 0xFFFFFFFFL) << 0) +#define LTQ_ES_PMAC_DA2_DA_31_0_GET(val) ((((val) & LTQ_ES_PMAC_DA2_DA_31_0) >> 0) & 0xFFFFFFFFL) +#define LTQ_ES_PMAC_DA2_DA_31_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_DA2_DA_31_0) | (((val) & 0xFFFFFFFFL) << 0)) + +/******************************************************************************* + * PMAC VLAN Register + ******************************************************************************/ + +/* Priority to be inserted as a part of VLAN tag (15:13) */ +#define LTQ_ES_PMAC_VLAN_PRI (0x7 << 13) +#define LTQ_ES_PMAC_VLAN_PRI_VAL(val) (((val) & 0x7) << 13) +#define LTQ_ES_PMAC_VLAN_PRI_GET(val) ((((val) & LTQ_ES_PMAC_VLAN_PRI) >> 13) & 0x7) +#define LTQ_ES_PMAC_VLAN_PRI_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_VLAN_PRI) | (((val) & 0x7) << 13)) +/* CFI bit to be inserted as a part of VLAN tag (12) */ +#define LTQ_ES_PMAC_VLAN_CFI (0x1 << 12) +#define LTQ_ES_PMAC_VLAN_CFI_VAL(val) (((val) & 0x1) << 12) +#define LTQ_ES_PMAC_VLAN_CFI_GET(val) ((((val) & LTQ_ES_PMAC_VLAN_CFI) >> 12) & 0x1) +#define LTQ_ES_PMAC_VLAN_CFI_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_VLAN_CFI) | (((val) & 0x1) << 12)) +/* VLAN ID to be inserted as a part of VLAN tag (11:0) */ +#define LTQ_ES_PMAC_VLAN_VLAN_ID (0xfff) +#define LTQ_ES_PMAC_VLAN_VLAN_ID_VAL(val) (((val) & 0xfff) << 0) +#define LTQ_ES_PMAC_VLAN_VLAN_ID_GET(val) ((((val) & LTQ_ES_PMAC_VLAN_VLAN_ID) >> 0) & 0xfff) +#define LTQ_ES_PMAC_VLAN_VLAN_ID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_VLAN_VLAN ID) | (((val) & 0xfff) << 0)) + +/******************************************************************************* + * PMAC TX IPG Counter Register + ******************************************************************************/ + +/* IPG Counter (7:0) */ +#define LTQ_ES_PMAC_TX_IPG_IPG_CNT (0xff) +#define LTQ_ES_PMAC_TX_IPG_IPG_CNT_VAL(val) (((val) & 0xff) << 0) +#define LTQ_ES_PMAC_TX_IPG_IPG_CNT_GET(val) ((((val) & LTQ_ES_PMAC_TX_IPG_IPG_CNT) >> 0) & 0xff) +#define LTQ_ES_PMAC_TX_IPG_IPG_CNT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_TX_IPG_IPG_CNT) | (((val) & 0xff) << 0)) + +/******************************************************************************* + * PMAC RX IPG Counter Register + ******************************************************************************/ + +/* IPG Counter (7:0) */ +#define LTQ_ES_PMAC_RX_IPG_IPG_CNT (0xff) +#define LTQ_ES_PMAC_RX_IPG_IPG_CNT_VAL(val) (((val) & 0xff) << 0) +#define LTQ_ES_PMAC_RX_IPG_IPG_CNT_GET(val) ((((val) & LTQ_ES_PMAC_RX_IPG_IPG_CNT) >> 0) & 0xff) +#define LTQ_ES_PMAC_RX_IPG_IPG_CNT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_RX_IPG_IPG_CNT) | (((val) & 0xff) << 0)) + +/******************************************************************************* + * Address Table Control 0 Register + ******************************************************************************/ + +/* Address [31:0] (31:0) */ +#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0 (0xFFFFFFFFL) +#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0_VAL(val) (((val) & 0xFFFFFFFFL) << 0) +#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0) >> 0) & 0xFFFFFFFFL) +#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0) | (((val) & 0xFFFFFFFFL) << 0)) + +/******************************************************************************* + * Address Table Control 1 Register + ******************************************************************************/ + +/* Port Map (22:20) */ +#define LTQ_ES_ADR_TB_CTL1_REG_PMAP (0x7 << 20) +#define LTQ_ES_ADR_TB_CTL1_REG_PMAP_VAL(val) (((val) & 0x7) << 20) +#define LTQ_ES_ADR_TB_CTL1_REG_PMAP_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL1_REG_PMAP) >> 20) & 0x7) +#define LTQ_ES_ADR_TB_CTL1_REG_PMAP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL1_REG_PMAP) | (((val) & 0x7) << 20)) +/* FID group (17:16) */ +#define LTQ_ES_ADR_TB_CTL1_REG_FID (0x3 << 16) +#define LTQ_ES_ADR_TB_CTL1_REG_FID_VAL(val) (((val) & 0x3) << 16) +#define LTQ_ES_ADR_TB_CTL1_REG_FID_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL1_REG_FID) >> 16) & 0x3) +#define LTQ_ES_ADR_TB_CTL1_REG_FID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL1_REG_FID) | (((val) & 0x3) << 16)) +/* Address [47:32] (15:0) */ +#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32 (0xffff) +#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32_VAL(val) (((val) & 0xffff) << 0) +#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32) >> 0) & 0xffff) +#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32) | (((val) & 0xffff) << 0)) + +/******************************************************************************* + * Address Table Control 2 Register + ******************************************************************************/ + +/* Command (22:20) */ +#define LTQ_ES_ADR_TB_CTL2_REG_CMD (0x7 << 20) +#define LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(val) (((val) & 0x7) << 20) +#define LTQ_ES_ADR_TB_CTL2_REG_CMD_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_CMD) >> 20) & 0x7) +#define LTQ_ES_ADR_TB_CTL2_REG_CMD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_CMD) | (((val) & 0x7) << 20)) +/* Access Control (19:16) */ +#define LTQ_ES_ADR_TB_CTL2_REG_AC (0xf << 16) +#define LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(val) (((val) & 0xf) << 16) +#define LTQ_ES_ADR_TB_CTL2_REG_AC_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_AC) >> 16) & 0xf) +#define LTQ_ES_ADR_TB_CTL2_REG_AC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_AC) | (((val) & 0xf) << 16)) +/* Info Type: Static address (12) */ +#define LTQ_ES_ADR_TB_CTL2_REG_INFOT (0x1 << 12) +#define LTQ_ES_ADR_TB_CTL2_REG_INFOT_VAL(val) (((val) & 0x1) << 12) +#define LTQ_ES_ADR_TB_CTL2_REG_INFOT_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_INFOT) >> 12) & 0x1) +#define LTQ_ES_ADR_TB_CTL2_REG_INFOT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_INFOT) | (((val) & 0x1) << 12)) +/* Info_Ctrl/Age Timer (10:0) */ +#define LTQ_ES_ADR_TB_CTL2_REG_ITAT (0x7ff) +#define LTQ_ES_ADR_TB_CTL2_REG_ITAT_VAL(val) (((val) & 0x7ff) << 0) +#define LTQ_ES_ADR_TB_CTL2_REG_ITAT_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_ITAT) >> 0) & 0x7ff) +#define LTQ_ES_ADR_TB_CTL2_REG_ITAT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_ITAT) | (((val) & 0x7ff) << 0)) + +/******************************************************************************* + * Address Table Status 0 Register + ******************************************************************************/ + +/* Address [31:0] (31:0) */ +#define LTQ_ES_ADR_TB_ST0_REG_ADDRS31_0 (0xFFFFFFFFL) +#define LTQ_ES_ADR_TB_ST0_REG_ADDRS31_0_GET(val) ((((val) & LTQ_ES_ADR_TB_ST0_REG_ADDRS31_0) >> 0) & 0xFFFFFFFFL) + +/******************************************************************************* + * Address Table Status 1 Register + ******************************************************************************/ + +/* Port Map (22:20) */ +#define LTQ_ES_ADR_TB_ST1_REG_PMAPS (0x7 << 20) +#define LTQ_ES_ADR_TB_ST1_REG_PMAPS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST1_REG_PMAPS) >> 20) & 0x7) +/* FID group (17:16) */ +#define LTQ_ES_ADR_TB_ST1_REG_FIDS (0x3 << 16) +#define LTQ_ES_ADR_TB_ST1_REG_FIDS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST1_REG_FIDS) >> 16) & 0x3) +/* Address [47:32] (15:0) */ +#define LTQ_ES_ADR_TB_ST1_REG_ADDRS47_32 (0xffff) +#define LTQ_ES_ADR_TB_ST1_REG_ADDRS47_32_GET(val) ((((val) & LTQ_ES_ADR_TB_ST1_REG_ADDRS47_32) >> 0) & 0xffff) + +/******************************************************************************* + * Address Table Status 2 Register + ******************************************************************************/ + +/* Busy (31) */ +#define LTQ_ES_ADR_TB_ST2_REG_BUSY (0x1 << 31) +#define LTQ_ES_ADR_TB_ST2_REG_BUSY_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_BUSY) >> 31) & 0x1) +/* Result (30:28) */ +#define LTQ_ES_ADR_TB_ST2_REG_RSLT (0x7 << 28) +#define LTQ_ES_ADR_TB_ST2_REG_RSLT_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_RSLT) >> 28) & 0x7) +/* Command (22:20) */ +#define LTQ_ES_ADR_TB_ST2_REG_CMD (0x7 << 20) +#define LTQ_ES_ADR_TB_ST2_REG_CMD_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_CMD) >> 20) & 0x7) +/* Access Control (19:16) */ +#define LTQ_ES_ADR_TB_ST2_REG_AC (0xf << 16) +#define LTQ_ES_ADR_TB_ST2_REG_AC_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_AC) >> 16) & 0xf) +/* Bad Status (14) */ +#define LTQ_ES_ADR_TB_ST2_REG_BAD (0x1 << 14) +#define LTQ_ES_ADR_TB_ST2_REG_BAD_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_BAD) >> 14) & 0x1) +/* Occupy (13) */ +#define LTQ_ES_ADR_TB_ST2_REG_OCP (0x1 << 13) +#define LTQ_ES_ADR_TB_ST2_REG_OCP_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_OCP) >> 13) & 0x1) +/* Info Type: Static address (12) */ +#define LTQ_ES_ADR_TB_ST2_REG_INFOTS (0x1 << 12) +#define LTQ_ES_ADR_TB_ST2_REG_INFOTS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_INFOTS) >> 12) & 0x1) +/* Info_Ctrl/Age Timer Status (10:0) */ +#define LTQ_ES_ADR_TB_ST2_REG_ITATS (0x7ff) +#define LTQ_ES_ADR_TB_ST2_REG_ITATS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_ITATS) >> 0) & 0x7ff) + +/******************************************************************************* + * RMON Counter Control Register + ******************************************************************************/ + +/* Reserved (31:12) */ +#define LTQ_ES_RMON_CTL_REG_RES (0xfffff << 12) +#define LTQ_ES_RMON_CTL_REG_RES_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_RES) >> 12) & 0xfffff) +/* Busy/Access Start (11) */ +#define LTQ_ES_RMON_CTL_REG_BAS (0x1 << 11) +#define LTQ_ES_RMON_CTL_REG_BAS_VAL(val) (((val) & 0x1) << 11) +#define LTQ_ES_RMON_CTL_REG_BAS_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_BAS) >> 11) & 0x1) +#define LTQ_ES_RMON_CTL_REG_BAS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_BAS) | (((val) & 0x1) << 11)) +/* Command for access counter (10:9) */ +#define LTQ_ES_RMON_CTL_REG_CAC (0x3 << 9) +#define LTQ_ES_RMON_CTL_REG_CAC_VAL(val) (((val) & 0x3) << 9) +#define LTQ_ES_RMON_CTL_REG_CAC_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_CAC) >> 9) & 0x3) +#define LTQ_ES_RMON_CTL_REG_CAC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_CAC) | (((val) & 0x3) << 9)) +/* Port (8:6) */ +#define LTQ_ES_RMON_CTL_REG_PORTC (0x7 << 6) +#define LTQ_ES_RMON_CTL_REG_PORTC_VAL(val) (((val) & 0x7) << 6) +#define LTQ_ES_RMON_CTL_REG_PORTC_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_PORTC) >> 6) & 0x7) +#define LTQ_ES_RMON_CTL_REG_PORTC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_PORTC) | (((val) & 0x7) << 6)) +/* Counter Offset (5:0) */ +#define LTQ_ES_RMON_CTL_REG_OFFSET (0x3f) +#define LTQ_ES_RMON_CTL_REG_OFFSET_VAL(val) (((val) & 0x3f) << 0) +#define LTQ_ES_RMON_CTL_REG_OFFSET_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_OFFSET) >> 0) & 0x3f) +#define LTQ_ES_RMON_CTL_REG_OFFSET_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_OFFSET) | (((val) & 0x3f) << 0)) + +/******************************************************************************* + * RMON Counter Status Register + ******************************************************************************/ + +/* Counter [31:0] or Counter[63:32] for byte count (31:0) */ +#define LTQ_ES_RMON_ST_REG_COUNTER (0xFFFFFFFFL) +#define LTQ_ES_RMON_ST_REG_COUNTER_GET(val) ((((val) & LTQ_ES_RMON_ST_REG_COUNTER) >> 0) & 0xFFFFFFFFL) + +/******************************************************************************* + * MDIO Indirect Access Control + ******************************************************************************/ + +/* The Write Data to the MDIO register (31:16) */ +#define LTQ_ES_MDIO_CTL_REG_WD (0xffff << 16) +#define LTQ_ES_MDIO_CTL_REG_WD_VAL(val) (((val) & 0xffff) << 16) +#define LTQ_ES_MDIO_CTL_REG_WD_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_WD) >> 16) & 0xffff) +#define LTQ_ES_MDIO_CTL_REG_WD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_WD) | (((val) & 0xffff) << 16)) +/* Busy state (15) */ +#define LTQ_ES_MDIO_CTL_REG_MBUSY (0x1 << 15) +#define LTQ_ES_MDIO_CTL_REG_MBUSY_VAL(val) (((val) & 0x1) << 15) +#define LTQ_ES_MDIO_CTL_REG_MBUSY_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_MBUSY) >> 15) & 0x1) +#define LTQ_ES_MDIO_CTL_REG_MBUSY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_MBUSY) | (((val) & 0x1) << 15)) +/* Reserved (14:12) */ +#define LTQ_ES_MDIO_CTL_REG_RES (0x7 << 12) +#define LTQ_ES_MDIO_CTL_REG_RES_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_RES) >> 12) & 0x7) +/* Operation Code (11:10) */ +#define LTQ_ES_MDIO_CTL_REG_OP (0x3 << 10) +#define LTQ_ES_MDIO_CTL_REG_OP_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_MDIO_CTL_REG_OP_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_OP) >> 10) & 0x3) +#define LTQ_ES_MDIO_CTL_REG_OP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_OP) | (((val) & 0x3) << 10)) +/* PHY Address (9:5) */ +#define LTQ_ES_MDIO_CTL_REG_PHYAD (0x1f << 5) +#define LTQ_ES_MDIO_CTL_REG_PHYAD_VAL(val) (((val) & 0x1f) << 5) +#define LTQ_ES_MDIO_CTL_REG_PHYAD_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_PHYAD) >> 5) & 0x1f) +#define LTQ_ES_MDIO_CTL_REG_PHYAD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_PHYAD) | (((val) & 0x1f) << 5)) +/* Register Address (4:0) */ +#define LTQ_ES_MDIO_CTL_REG_REGAD (0x1f) +#define LTQ_ES_MDIO_CTL_REG_REGAD_VAL(val) (((val) & 0x1f) << 0) +#define LTQ_ES_MDIO_CTL_REG_REGAD_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_REGAD) >> 0) & 0x1f) +#define LTQ_ES_MDIO_CTL_REG_REGAD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_REGAD) | (((val) & 0x1f) << 0)) + +/******************************************************************************* + * MDIO Indirect Read Data + ******************************************************************************/ + +/* Reserved (31:16) */ +#define LTQ_ES_MDIO_DATA_REG_RES (0xffff << 16) +#define LTQ_ES_MDIO_DATA_REG_RES_GET(val) ((((val) & LTQ_ES_MDIO_DATA_REG_RES) >> 16) & 0xffff) +/* The Read Data (15:0) */ +#define LTQ_ES_MDIO_DATA_REG_RD (0xffff) +#define LTQ_ES_MDIO_DATA_REG_RD_GET(val) ((((val) & LTQ_ES_MDIO_DATA_REG_RD) >> 0) & 0xffff) + +/******************************************************************************* + * Type Filter Action + ******************************************************************************/ + +/* Destination Queue for Type Filter 7 (31:30) */ +#define LTQ_ES_TP_FLT_ACT_REG_QATF7 (0x3 << 30) +#define LTQ_ES_TP_FLT_ACT_REG_QATF7_VAL(val) (((val) & 0x3) << 30) +#define LTQ_ES_TP_FLT_ACT_REG_QATF7_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QATF7) >> 30) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_QATF7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QATF7) | (((val) & 0x3) << 30)) +/* Destination Queue for Type Filter 6 (29:28) */ +#define LTQ_ES_TP_FLT_ACT_REG_QATF6 (0x3 << 28) +#define LTQ_ES_TP_FLT_ACT_REG_QATF6_VAL(val) (((val) & 0x3) << 28) +#define LTQ_ES_TP_FLT_ACT_REG_QATF6_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QATF6) >> 28) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_QATF6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QATF6) | (((val) & 0x3) << 28)) +/* Destination Queue for Type Filter 5 (27:26) */ +#define LTQ_ES_TP_FLT_ACT_REG_QTF5 (0x3 << 26) +#define LTQ_ES_TP_FLT_ACT_REG_QTF5_VAL(val) (((val) & 0x3) << 26) +#define LTQ_ES_TP_FLT_ACT_REG_QTF5_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF5) >> 26) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_QTF5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF5) | (((val) & 0x3) << 26)) +/* Destination Queue for Type Filter 4 (25:24) */ +#define LTQ_ES_TP_FLT_ACT_REG_QTF4 (0x3 << 24) +#define LTQ_ES_TP_FLT_ACT_REG_QTF4_VAL(val) (((val) & 0x3) << 24) +#define LTQ_ES_TP_FLT_ACT_REG_QTF4_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF4) >> 24) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_QTF4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF4) | (((val) & 0x3) << 24)) +/* Destination Queue for Type Filter 3 (23:22) */ +#define LTQ_ES_TP_FLT_ACT_REG_QTF3 (0x3 << 22) +#define LTQ_ES_TP_FLT_ACT_REG_QTF3_VAL(val) (((val) & 0x3) << 22) +#define LTQ_ES_TP_FLT_ACT_REG_QTF3_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF3) >> 22) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_QTF3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF3) | (((val) & 0x3) << 22)) +/* Destination Queue for Type Filter 2 (21:20) */ +#define LTQ_ES_TP_FLT_ACT_REG_QTF2 (0x3 << 20) +#define LTQ_ES_TP_FLT_ACT_REG_QTF2_VAL(val) (((val) & 0x3) << 20) +#define LTQ_ES_TP_FLT_ACT_REG_QTF2_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF2) >> 20) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_QTF2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF2) | (((val) & 0x3) << 20)) +/* Destination Queue for Type Filter 1 (19:18) */ +#define LTQ_ES_TP_FLT_ACT_REG_QTF1 (0x3 << 18) +#define LTQ_ES_TP_FLT_ACT_REG_QTF1_VAL(val) (((val) & 0x3) << 18) +#define LTQ_ES_TP_FLT_ACT_REG_QTF1_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF1) >> 18) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_QTF1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF1) | (((val) & 0x3) << 18)) +/* Destination Queue for Type Filter 0 (17:16) */ +#define LTQ_ES_TP_FLT_ACT_REG_QTF0 (0x3 << 16) +#define LTQ_ES_TP_FLT_ACT_REG_QTF0_VAL(val) (((val) & 0x3) << 16) +#define LTQ_ES_TP_FLT_ACT_REG_QTF0_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF0) >> 16) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_QTF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF0) | (((val) & 0x3) << 16)) +/* Action for Type Filter 7 (15:14) */ +#define LTQ_ES_TP_FLT_ACT_REG_ATF7 (0x3 << 14) +#define LTQ_ES_TP_FLT_ACT_REG_ATF7_VAL(val) (((val) & 0x3) << 14) +#define LTQ_ES_TP_FLT_ACT_REG_ATF7_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF7) >> 14) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_ATF7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF7) | (((val) & 0x3) << 14)) +/* Action for Type Filter 6 (13:12) */ +#define LTQ_ES_TP_FLT_ACT_REG_ATF6 (0x3 << 12) +#define LTQ_ES_TP_FLT_ACT_REG_ATF6_VAL(val) (((val) & 0x3) << 12) +#define LTQ_ES_TP_FLT_ACT_REG_ATF6_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF6) >> 12) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_ATF6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF6) | (((val) & 0x3) << 12)) +/* Action for Type Filter 5 (11:10) */ +#define LTQ_ES_TP_FLT_ACT_REG_ATF5 (0x3 << 10) +#define LTQ_ES_TP_FLT_ACT_REG_ATF5_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_TP_FLT_ACT_REG_ATF5_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF5) >> 10) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_ATF5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF5) | (((val) & 0x3) << 10)) +/* Action for Type Filter 4 (9:8) */ +#define LTQ_ES_TP_FLT_ACT_REG_ATF4 (0x3 << 8) +#define LTQ_ES_TP_FLT_ACT_REG_ATF4_VAL(val) (((val) & 0x3) << 8) +#define LTQ_ES_TP_FLT_ACT_REG_ATF4_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF4) >> 8) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_ATF4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF4) | (((val) & 0x3) << 8)) +/* Action for Type Filter 3 (7:6) */ +#define LTQ_ES_TP_FLT_ACT_REG_ATF3 (0x3 << 6) +#define LTQ_ES_TP_FLT_ACT_REG_ATF3_VAL(val) (((val) & 0x3) << 6) +#define LTQ_ES_TP_FLT_ACT_REG_ATF3_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF3) >> 6) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_ATF3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF3) | (((val) & 0x3) << 6)) +/* Action for Type Filter 2 (5:4) */ +#define LTQ_ES_TP_FLT_ACT_REG_ATF2 (0x3 << 4) +#define LTQ_ES_TP_FLT_ACT_REG_ATF2_VAL(val) (((val) & 0x3) << 4) +#define LTQ_ES_TP_FLT_ACT_REG_ATF2_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF2) >> 4) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_ATF2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF2) | (((val) & 0x3) << 4)) +/* Action for Type Filter 1 (3:2) */ +#define LTQ_ES_TP_FLT_ACT_REG_ATF1 (0x3 << 2) +#define LTQ_ES_TP_FLT_ACT_REG_ATF1_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_TP_FLT_ACT_REG_ATF1_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF1) >> 2) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_ATF1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF1) | (((val) & 0x3) << 2)) +/* Action for Type Filter 0 (1:0) */ +#define LTQ_ES_TP_FLT_ACT_REG_ATF0 (0x3) +#define LTQ_ES_TP_FLT_ACT_REG_ATF0_VAL(val) (((val) & 0x3) << 0) +#define LTQ_ES_TP_FLT_ACT_REG_ATF0_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF0) >> 0) & 0x3) +#define LTQ_ES_TP_FLT_ACT_REG_ATF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF0) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * Protocol Filter Action + ******************************************************************************/ + +/* Action for Protocol Filter 7 (15:14) */ +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7 (0x3 << 14) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7_VAL(val) (((val) & 0x3) << 14) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF7) >> 14) & 0x3) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF7) | (((val) & 0x3) << 14)) +/* Action for Protocol Filter 6 (13:12) */ +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6 (0x3 << 12) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6_VAL(val) (((val) & 0x3) << 12) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF6) >> 12) & 0x3) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF6) | (((val) & 0x3) << 12)) +/* Action for Protocol Filter 5 (11:10) */ +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5 (0x3 << 10) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF5) >> 10) & 0x3) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF5) | (((val) & 0x3) << 10)) +/* Action for Protocol Filter 4 (9:8) */ +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4 (0x3 << 8) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4_VAL(val) (((val) & 0x3) << 8) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF4) >> 8) & 0x3) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF4) | (((val) & 0x3) << 8)) +/* Action for Protocol Filter 3 (7:6) */ +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3 (0x3 << 6) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3_VAL(val) (((val) & 0x3) << 6) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF3) >> 6) & 0x3) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF3) | (((val) & 0x3) << 6)) +/* Action for Protocol Filter 2 (5:4) */ +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2 (0x3 << 4) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2_VAL(val) (((val) & 0x3) << 4) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF2) >> 4) & 0x3) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF2) | (((val) & 0x3) << 4)) +/* Action for Protocol Filter 1 (3:2) */ +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1 (0x3 << 2) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF1) >> 2) & 0x3) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF1) | (((val) & 0x3) << 2)) +/* Action for Protocol Filter 0 (1:0) */ +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0 (0x3) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0_VAL(val) (((val) & 0x3) << 0) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF0) >> 0) & 0x3) +#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF0) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * VLAN Filter 0 + ******************************************************************************/ + +/* Res (31:24) */ +#define LTQ_ES_VLAN_FLT0_REG_RES (0xff << 24) +#define LTQ_ES_VLAN_FLT0_REG_RES_VAL(val) (((val) & 0xff) << 24) +#define LTQ_ES_VLAN_FLT0_REG_RES_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_RES) >> 24) & 0xff) +#define LTQ_ES_VLAN_FLT0_REG_RES_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_RES) | (((val) & 0xff) << 24)) +/* FID (23:22) */ +#define LTQ_ES_VLAN_FLT0_REG_FID (0x3 << 22) +#define LTQ_ES_VLAN_FLT0_REG_FID_VAL(val) (((val) & 0x3) << 22) +#define LTQ_ES_VLAN_FLT0_REG_FID_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_FID) >> 22) & 0x3) +#define LTQ_ES_VLAN_FLT0_REG_FID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_FID) | (((val) & 0x3) << 22)) +/* Tagged Member (21:19) */ +#define LTQ_ES_VLAN_FLT0_REG_TM (0x7 << 19) +#define LTQ_ES_VLAN_FLT0_REG_TM_VAL(val) (((val) & 0x7) << 19) +#define LTQ_ES_VLAN_FLT0_REG_TM_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_TM) >> 19) & 0x7) +#define LTQ_ES_VLAN_FLT0_REG_TM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_TM) | (((val) & 0x7) << 19)) +/* Member (18:16) */ +#define LTQ_ES_VLAN_FLT0_REG_M (0x7 << 16) +#define LTQ_ES_VLAN_FLT0_REG_M_VAL(val) (((val) & 0x7) << 16) +#define LTQ_ES_VLAN_FLT0_REG_M_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_M) >> 16) & 0x7) +#define LTQ_ES_VLAN_FLT0_REG_M_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_M) | (((val) & 0x7) << 16)) +/* VLAN_Valid (15) */ +#define LTQ_ES_VLAN_FLT0_REG_VV (0x1 << 15) +#define LTQ_ES_VLAN_FLT0_REG_VV_VAL(val) (((val) & 0x1) << 15) +#define LTQ_ES_VLAN_FLT0_REG_VV_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_VV) >> 15) & 0x1) +#define LTQ_ES_VLAN_FLT0_REG_VV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_VV) | (((val) & 0x1) << 15)) +/* VLAN PRI (14:12) */ +#define LTQ_ES_VLAN_FLT0_REG_VP (0x7 << 12) +#define LTQ_ES_VLAN_FLT0_REG_VP_VAL(val) (((val) & 0x7) << 12) +#define LTQ_ES_VLAN_FLT0_REG_VP_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_VP) >> 12) & 0x7) +#define LTQ_ES_VLAN_FLT0_REG_VP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_VP) | (((val) & 0x7) << 12)) +/* VID (11:0) */ +#define LTQ_ES_VLAN_FLT0_REG_VID (0xfff) +#define LTQ_ES_VLAN_FLT0_REG_VID_VAL(val) (((val) & 0xfff) << 0) +#define LTQ_ES_VLAN_FLT0_REG_VID_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_VID) >> 0) & 0xfff) +#define LTQ_ES_VLAN_FLT0_REG_VID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_VID) | (((val) & 0xfff) << 0)) + +/******************************************************************************* + * Type Filter 10 + ******************************************************************************/ + +/* Value 1 Compared with Ether-Type (31:16) */ +#define LTQ_ES_TP_FLT10_REG_VCET1 (0xffff << 16) +#define LTQ_ES_TP_FLT10_REG_VCET1_VAL(val) (((val) & 0xffff) << 16) +#define LTQ_ES_TP_FLT10_REG_VCET1_GET(val) ((((val) & LTQ_ES_TP_FLT10_REG_VCET1) >> 16) & 0xffff) +#define LTQ_ES_TP_FLT10_REG_VCET1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT10_REG_VCET1) | (((val) & 0xffff) << 16)) +/* Value 0 Compared with Ether-Type (15:0) */ +#define LTQ_ES_TP_FLT10_REG_VCET0 (0xffff) +#define LTQ_ES_TP_FLT10_REG_VCET0_VAL(val) (((val) & 0xffff) << 0) +#define LTQ_ES_TP_FLT10_REG_VCET0_GET(val) ((((val) & LTQ_ES_TP_FLT10_REG_VCET0) >> 0) & 0xffff) +#define LTQ_ES_TP_FLT10_REG_VCET0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT10_REG_VCET0) | (((val) & 0xffff) << 0)) + +/******************************************************************************* + * DiffServMapping 0 + ******************************************************************************/ + +/* Priority Queue F (31:30) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQF (0x3 << 30) +#define LTQ_ES_DFSRV_MAP0_REG_PQF_VAL(val) (((val) & 0x3) << 30) +#define LTQ_ES_DFSRV_MAP0_REG_PQF_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQF) >> 30) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQF_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQF) | (((val) & 0x3) << 30)) +/* Priority Queue E (29:28) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQE (0x3 << 28) +#define LTQ_ES_DFSRV_MAP0_REG_PQE_VAL(val) (((val) & 0x3) << 28) +#define LTQ_ES_DFSRV_MAP0_REG_PQE_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQE) >> 28) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQE) | (((val) & 0x3) << 28)) +/* Priority Queue D (27:26) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQD (0x3 << 26) +#define LTQ_ES_DFSRV_MAP0_REG_PQD_VAL(val) (((val) & 0x3) << 26) +#define LTQ_ES_DFSRV_MAP0_REG_PQD_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQD) >> 26) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQD) | (((val) & 0x3) << 26)) +/* Priority Queue C (25:24) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQC (0x3 << 24) +#define LTQ_ES_DFSRV_MAP0_REG_PQC_VAL(val) (((val) & 0x3) << 24) +#define LTQ_ES_DFSRV_MAP0_REG_PQC_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQC) >> 24) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQC) | (((val) & 0x3) << 24)) +/* Priority Queue B (23:22) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQB (0x3 << 22) +#define LTQ_ES_DFSRV_MAP0_REG_PQB_VAL(val) (((val) & 0x3) << 22) +#define LTQ_ES_DFSRV_MAP0_REG_PQB_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQB) >> 22) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQB_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQB) | (((val) & 0x3) << 22)) +/* Priority Queue A (21:20) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQA (0x3 << 20) +#define LTQ_ES_DFSRV_MAP0_REG_PQA_VAL(val) (((val) & 0x3) << 20) +#define LTQ_ES_DFSRV_MAP0_REG_PQA_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQA) >> 20) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQA) | (((val) & 0x3) << 20)) +/* Priority Queue 9 (19:18) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQ9 (0x3 << 18) +#define LTQ_ES_DFSRV_MAP0_REG_PQ9_VAL(val) (((val) & 0x3) << 18) +#define LTQ_ES_DFSRV_MAP0_REG_PQ9_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ9) >> 18) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ9_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ9) | (((val) & 0x3) << 18)) +/* Priority Queue 8 (17:16) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQ8 (0x3 << 16) +#define LTQ_ES_DFSRV_MAP0_REG_PQ8_VAL(val) (((val) & 0x3) << 16) +#define LTQ_ES_DFSRV_MAP0_REG_PQ8_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ8) >> 16) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ8_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ8) | (((val) & 0x3) << 16)) +/* Priority Queue 7 (15:14) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQ7 (0x3 << 14) +#define LTQ_ES_DFSRV_MAP0_REG_PQ7_VAL(val) (((val) & 0x3) << 14) +#define LTQ_ES_DFSRV_MAP0_REG_PQ7_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ7) >> 14) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ7) | (((val) & 0x3) << 14)) +/* Priority Queue 6 (13:12) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQ6 (0x3 << 12) +#define LTQ_ES_DFSRV_MAP0_REG_PQ6_VAL(val) (((val) & 0x3) << 12) +#define LTQ_ES_DFSRV_MAP0_REG_PQ6_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ6) >> 12) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ6) | (((val) & 0x3) << 12)) +/* Priority Queue 5 (11:10) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQ5 (0x3 << 10) +#define LTQ_ES_DFSRV_MAP0_REG_PQ5_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_DFSRV_MAP0_REG_PQ5_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ5) >> 10) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ5) | (((val) & 0x3) << 10)) +/* Priority Queue 4 (9:8) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQ4 (0x3 << 8) +#define LTQ_ES_DFSRV_MAP0_REG_PQ4_VAL(val) (((val) & 0x3) << 8) +#define LTQ_ES_DFSRV_MAP0_REG_PQ4_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ4) >> 8) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ4) | (((val) & 0x3) << 8)) +/* Priority Queue 3 (7:6) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQ3 (0x3 << 6) +#define LTQ_ES_DFSRV_MAP0_REG_PQ3_VAL(val) (((val) & 0x3) << 6) +#define LTQ_ES_DFSRV_MAP0_REG_PQ3_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ3) >> 6) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ3) | (((val) & 0x3) << 6)) +/* Priority Queue 2 (5:4) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQ2 (0x3 << 4) +#define LTQ_ES_DFSRV_MAP0_REG_PQ2_VAL(val) (((val) & 0x3) << 4) +#define LTQ_ES_DFSRV_MAP0_REG_PQ2_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ2) >> 4) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ2) | (((val) & 0x3) << 4)) +/* Priority Queue 1 (3:2) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQ1 (0x3 << 2) +#define LTQ_ES_DFSRV_MAP0_REG_PQ1_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_DFSRV_MAP0_REG_PQ1_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ1) >> 2) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ1) | (((val) & 0x3) << 2)) +/* Priority Queue 0 (1:0) */ +#define LTQ_ES_DFSRV_MAP0_REG_PQ0 (0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ0_VAL(val) (((val) & 0x3) << 0) +#define LTQ_ES_DFSRV_MAP0_REG_PQ0_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ0) >> 0) & 0x3) +#define LTQ_ES_DFSRV_MAP0_REG_PQ0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ0) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * DiffServMapping 1 + ******************************************************************************/ + +/* Priority Queue 1F (31:30) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ1F (0x3 << 30) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1F_VAL(val) (((val) & 0x3) << 30) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1F_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1F) >> 30) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1F_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1F) | (((val) & 0x3) << 30)) +/* Priority Queue 1E (29:28) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ1E (0x3 << 28) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1E_VAL(val) (((val) & 0x3) << 28) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1E_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1E) >> 28) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1E_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1E) | (((val) & 0x3) << 28)) +/* Priority Queue 1D (27:26) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ1D (0x3 << 26) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1D_VAL(val) (((val) & 0x3) << 26) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1D_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1D) >> 26) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1D_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1D) | (((val) & 0x3) << 26)) +/* Priority Queue 1C (25:24) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ1C (0x3 << 24) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1C_VAL(val) (((val) & 0x3) << 24) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1C_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1C) >> 24) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1C_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1C) | (((val) & 0x3) << 24)) +/* Priority Queue 1B (23:22) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ1B (0x3 << 22) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1B_VAL(val) (((val) & 0x3) << 22) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1B_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1B) >> 22) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1B) | (((val) & 0x3) << 22)) +/* Priority Queue 1A (21:20) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ1A (0x3 << 20) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1A_VAL(val) (((val) & 0x3) << 20) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1A_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1A) >> 20) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ1A_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1A) | (((val) & 0x3) << 20)) +/* Priority Queue 19 (19:18) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ19 (0x3 << 18) +#define LTQ_ES_DFSRV_MAP1_REG_PQ19_VAL(val) (((val) & 0x3) << 18) +#define LTQ_ES_DFSRV_MAP1_REG_PQ19_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ19) >> 18) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ19_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ19) | (((val) & 0x3) << 18)) +/* Priority Queue 18 (17:16) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ18 (0x3 << 16) +#define LTQ_ES_DFSRV_MAP1_REG_PQ18_VAL(val) (((val) & 0x3) << 16) +#define LTQ_ES_DFSRV_MAP1_REG_PQ18_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ18) >> 16) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ18_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ18) | (((val) & 0x3) << 16)) +/* Priority Queue 17 (15:14) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ17 (0x3 << 14) +#define LTQ_ES_DFSRV_MAP1_REG_PQ17_VAL(val) (((val) & 0x3) << 14) +#define LTQ_ES_DFSRV_MAP1_REG_PQ17_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ17) >> 14) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ17_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ17) | (((val) & 0x3) << 14)) +/* Priority Queue 16 (13:12) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ16 (0x3 << 12) +#define LTQ_ES_DFSRV_MAP1_REG_PQ16_VAL(val) (((val) & 0x3) << 12) +#define LTQ_ES_DFSRV_MAP1_REG_PQ16_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ16) >> 12) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ16_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ16) | (((val) & 0x3) << 12)) +/* Priority Queue 15 (11:10) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ15 (0x3 << 10) +#define LTQ_ES_DFSRV_MAP1_REG_PQ15_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_DFSRV_MAP1_REG_PQ15_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ15) >> 10) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ15_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ15) | (((val) & 0x3) << 10)) +/* Priority Queue 14 (9:8) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ14 (0x3 << 8) +#define LTQ_ES_DFSRV_MAP1_REG_PQ14_VAL(val) (((val) & 0x3) << 8) +#define LTQ_ES_DFSRV_MAP1_REG_PQ14_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ14) >> 8) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ14_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ14) | (((val) & 0x3) << 8)) +/* Priority Queue 13 (7:6) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ13 (0x3 << 6) +#define LTQ_ES_DFSRV_MAP1_REG_PQ13_VAL(val) (((val) & 0x3) << 6) +#define LTQ_ES_DFSRV_MAP1_REG_PQ13_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ13) >> 6) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ13_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ13) | (((val) & 0x3) << 6)) +/* Priority Queue 12 (5:4) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ12 (0x3 << 4) +#define LTQ_ES_DFSRV_MAP1_REG_PQ12_VAL(val) (((val) & 0x3) << 4) +#define LTQ_ES_DFSRV_MAP1_REG_PQ12_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ12) >> 4) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ12_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ12) | (((val) & 0x3) << 4)) +/* Priority Queue 11 (3:2) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ11 (0x3 << 2) +#define LTQ_ES_DFSRV_MAP1_REG_PQ11_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_DFSRV_MAP1_REG_PQ11_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ11) >> 2) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ11_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ11) | (((val) & 0x3) << 2)) +/* Priority Queue 10 (1:0) */ +#define LTQ_ES_DFSRV_MAP1_REG_PQ10 (0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ10_VAL(val) (((val) & 0x3) << 0) +#define LTQ_ES_DFSRV_MAP1_REG_PQ10_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ10) >> 0) & 0x3) +#define LTQ_ES_DFSRV_MAP1_REG_PQ10_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ10) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * DiffServMapping 2 + ******************************************************************************/ + +/* Priority Queue 2F (31:30) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ2F (0x3 << 30) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2F_VAL(val) (((val) & 0x3) << 30) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2F_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2F) >> 30) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2F_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2F) | (((val) & 0x3) << 30)) +/* Priority Queue 2E (29:28) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ2E (0x3 << 28) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2E_VAL(val) (((val) & 0x3) << 28) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2E_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2E) >> 28) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2E_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2E) | (((val) & 0x3) << 28)) +/* Priority Queue 2D (27:26) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ2D (0x3 << 26) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2D_VAL(val) (((val) & 0x3) << 26) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2D_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2D) >> 26) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2D_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2D) | (((val) & 0x3) << 26)) +/* Priority Queue 2C (25:24) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ2C (0x3 << 24) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2C_VAL(val) (((val) & 0x3) << 24) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2C_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2C) >> 24) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2C_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2C) | (((val) & 0x3) << 24)) +/* Priority Queue 2B (23:22) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ2B (0x3 << 22) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2B_VAL(val) (((val) & 0x3) << 22) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2B_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2B) >> 22) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2B) | (((val) & 0x3) << 22)) +/* Priority Queue 2A (21:20) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ2A (0x3 << 20) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2A_VAL(val) (((val) & 0x3) << 20) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2A_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2A) >> 20) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ2A_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2A) | (((val) & 0x3) << 20)) +/* Priority Queue 29 (19:18) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ29 (0x3 << 18) +#define LTQ_ES_DFSRV_MAP2_REG_PQ29_VAL(val) (((val) & 0x3) << 18) +#define LTQ_ES_DFSRV_MAP2_REG_PQ29_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ29) >> 18) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ29_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ29) | (((val) & 0x3) << 18)) +/* Priority Queue 28 (17:16) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ28 (0x3 << 16) +#define LTQ_ES_DFSRV_MAP2_REG_PQ28_VAL(val) (((val) & 0x3) << 16) +#define LTQ_ES_DFSRV_MAP2_REG_PQ28_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ28) >> 16) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ28_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ28) | (((val) & 0x3) << 16)) +/* Priority Queue 27 (15:14) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ27 (0x3 << 14) +#define LTQ_ES_DFSRV_MAP2_REG_PQ27_VAL(val) (((val) & 0x3) << 14) +#define LTQ_ES_DFSRV_MAP2_REG_PQ27_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ27) >> 14) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ27_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ27) | (((val) & 0x3) << 14)) +/* Priority Queue 26 (13:12) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ26 (0x3 << 12) +#define LTQ_ES_DFSRV_MAP2_REG_PQ26_VAL(val) (((val) & 0x3) << 12) +#define LTQ_ES_DFSRV_MAP2_REG_PQ26_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ26) >> 12) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ26_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ26) | (((val) & 0x3) << 12)) +/* Priority Queue 25 (11:10) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ25 (0x3 << 10) +#define LTQ_ES_DFSRV_MAP2_REG_PQ25_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_DFSRV_MAP2_REG_PQ25_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ25) >> 10) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ25_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ25) | (((val) & 0x3) << 10)) +/* Priority Queue 24 (9:8) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ24 (0x3 << 8) +#define LTQ_ES_DFSRV_MAP2_REG_PQ24_VAL(val) (((val) & 0x3) << 8) +#define LTQ_ES_DFSRV_MAP2_REG_PQ24_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ24) >> 8) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ24_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ24) | (((val) & 0x3) << 8)) +/* Priority Queue 23 (7:6) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ23 (0x3 << 6) +#define LTQ_ES_DFSRV_MAP2_REG_PQ23_VAL(val) (((val) & 0x3) << 6) +#define LTQ_ES_DFSRV_MAP2_REG_PQ23_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ23) >> 6) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ23_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ23) | (((val) & 0x3) << 6)) +/* Priority Queue 22 (5:4) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ22 (0x3 << 4) +#define LTQ_ES_DFSRV_MAP2_REG_PQ22_VAL(val) (((val) & 0x3) << 4) +#define LTQ_ES_DFSRV_MAP2_REG_PQ22_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ22) >> 4) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ22_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ22) | (((val) & 0x3) << 4)) +/* Priority Queue 21 (3:2) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ21 (0x3 << 2) +#define LTQ_ES_DFSRV_MAP2_REG_PQ21_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_DFSRV_MAP2_REG_PQ21_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ21) >> 2) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ21_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ21) | (((val) & 0x3) << 2)) +/* Priority Queue 20 (1:0) */ +#define LTQ_ES_DFSRV_MAP2_REG_PQ20 (0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ20_VAL(val) (((val) & 0x3) << 0) +#define LTQ_ES_DFSRV_MAP2_REG_PQ20_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ20) >> 0) & 0x3) +#define LTQ_ES_DFSRV_MAP2_REG_PQ20_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ20) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * DiffServMapping 3 + ******************************************************************************/ + +/* Priority Queue 3F (31:30) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ3F (0x3 << 30) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3F_VAL(val) (((val) & 0x3) << 30) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3F_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3F) >> 30) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3F_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3F) | (((val) & 0x3) << 30)) +/* Priority Queue 3E (29:28) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ3E (0x3 << 28) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3E_VAL(val) (((val) & 0x3) << 28) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3E_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3E) >> 28) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3E_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3E) | (((val) & 0x3) << 28)) +/* Priority Queue 3D (27:26) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ3D (0x3 << 26) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3D_VAL(val) (((val) & 0x3) << 26) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3D_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3D) >> 26) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3D_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3D) | (((val) & 0x3) << 26)) +/* Priority Queue 3C (25:24) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ3C (0x3 << 24) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3C_VAL(val) (((val) & 0x3) << 24) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3C_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3C) >> 24) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3C_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3C) | (((val) & 0x3) << 24)) +/* Priority Queue 3B (23:22) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ3B (0x3 << 22) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3B_VAL(val) (((val) & 0x3) << 22) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3B_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3B) >> 22) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3B) | (((val) & 0x3) << 22)) +/* Priority Queue 3A (21:20) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ3A (0x3 << 20) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3A_VAL(val) (((val) & 0x3) << 20) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3A_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3A) >> 20) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ3A_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3A) | (((val) & 0x3) << 20)) +/* Priority Queue 39 (19:18) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ39 (0x3 << 18) +#define LTQ_ES_DFSRV_MAP3_REG_PQ39_VAL(val) (((val) & 0x3) << 18) +#define LTQ_ES_DFSRV_MAP3_REG_PQ39_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ39) >> 18) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ39_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ39) | (((val) & 0x3) << 18)) +/* Priority Queue 38 (17:16) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ38 (0x3 << 16) +#define LTQ_ES_DFSRV_MAP3_REG_PQ38_VAL(val) (((val) & 0x3) << 16) +#define LTQ_ES_DFSRV_MAP3_REG_PQ38_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ38) >> 16) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ38_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ38) | (((val) & 0x3) << 16)) +/* Priority Queue 37 (15:14) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ37 (0x3 << 14) +#define LTQ_ES_DFSRV_MAP3_REG_PQ37_VAL(val) (((val) & 0x3) << 14) +#define LTQ_ES_DFSRV_MAP3_REG_PQ37_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ37) >> 14) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ37_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ37) | (((val) & 0x3) << 14)) +/* Priority Queue 36 (13:12) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ36 (0x3 << 12) +#define LTQ_ES_DFSRV_MAP3_REG_PQ36_VAL(val) (((val) & 0x3) << 12) +#define LTQ_ES_DFSRV_MAP3_REG_PQ36_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ36) >> 12) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ36_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ36) | (((val) & 0x3) << 12)) +/* Priority Queue 35 (11:10) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ35 (0x3 << 10) +#define LTQ_ES_DFSRV_MAP3_REG_PQ35_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_DFSRV_MAP3_REG_PQ35_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ35) >> 10) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ35_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ35) | (((val) & 0x3) << 10)) +/* Priority Queue 34 (9:8) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ34 (0x3 << 8) +#define LTQ_ES_DFSRV_MAP3_REG_PQ34_VAL(val) (((val) & 0x3) << 8) +#define LTQ_ES_DFSRV_MAP3_REG_PQ34_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ34) >> 8) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ34_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ34) | (((val) & 0x3) << 8)) +/* Priority Queue 33 (7:6) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ33 (0x3 << 6) +#define LTQ_ES_DFSRV_MAP3_REG_PQ33_VAL(val) (((val) & 0x3) << 6) +#define LTQ_ES_DFSRV_MAP3_REG_PQ33_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ33) >> 6) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ33_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ33) | (((val) & 0x3) << 6)) +/* Priority Queue 32 (5:4) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ32 (0x3 << 4) +#define LTQ_ES_DFSRV_MAP3_REG_PQ32_VAL(val) (((val) & 0x3) << 4) +#define LTQ_ES_DFSRV_MAP3_REG_PQ32_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ32) >> 4) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ32) | (((val) & 0x3) << 4)) +/* Priority Queue 31 (3:2) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ31 (0x3 << 2) +#define LTQ_ES_DFSRV_MAP3_REG_PQ31_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_DFSRV_MAP3_REG_PQ31_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ31) >> 2) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ31_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ31) | (((val) & 0x3) << 2)) +/* Priority Queue 30 (1:0) */ +#define LTQ_ES_DFSRV_MAP3_REG_PQ30 (0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ30_VAL(val) (((val) & 0x3) << 0) +#define LTQ_ES_DFSRV_MAP3_REG_PQ30_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ30) >> 0) & 0x3) +#define LTQ_ES_DFSRV_MAP3_REG_PQ30_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ30) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * TCP/UDP Port Filter 0 + ******************************************************************************/ + +/* Reserved (31:30) */ +#define LTQ_ES_TCP_PF0_REG_RES (0x3 << 30) +#define LTQ_ES_TCP_PF0_REG_RES_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_RES) >> 30) & 0x3) +/* Action for TCP/UDP Port Filter 0 (29:28) */ +#define LTQ_ES_TCP_PF0_REG_ATUF0 (0x3 << 28) +#define LTQ_ES_TCP_PF0_REG_ATUF0_VAL(val) (((val) & 0x3) << 28) +#define LTQ_ES_TCP_PF0_REG_ATUF0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_ATUF0) >> 28) & 0x3) +#define LTQ_ES_TCP_PF0_REG_ATUF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_ATUF0) | (((val) & 0x3) << 28)) +/* TCP/UDP PRI for TCP/UDP Port Filter 0 (27:26) */ +#define LTQ_ES_TCP_PF0_REG_TUPF0 (0x3 << 26) +#define LTQ_ES_TCP_PF0_REG_TUPF0_VAL(val) (((val) & 0x3) << 26) +#define LTQ_ES_TCP_PF0_REG_TUPF0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_TUPF0) >> 26) & 0x3) +#define LTQ_ES_TCP_PF0_REG_TUPF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_TUPF0) | (((val) & 0x3) << 26)) +/* Compare TCP/UDP Source Port or Destination Port (25:24) */ +#define LTQ_ES_TCP_PF0_REG_COMP0 (0x3 << 24) +#define LTQ_ES_TCP_PF0_REG_COMP0_VAL(val) (((val) & 0x3) << 24) +#define LTQ_ES_TCP_PF0_REG_COMP0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_COMP0) >> 24) & 0x3) +#define LTQ_ES_TCP_PF0_REG_COMP0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_COMP0) | (((val) & 0x3) << 24)) +/* Port Range in TCP/UDP (23:16) */ +#define LTQ_ES_TCP_PF0_REG_PRANGE0 (0xff << 16) +#define LTQ_ES_TCP_PF0_REG_PRANGE0_VAL(val) (((val) & 0xff) << 16) +#define LTQ_ES_TCP_PF0_REG_PRANGE0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_PRANGE0) >> 16) & 0xff) +#define LTQ_ES_TCP_PF0_REG_PRANGE0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_PRANGE0) | (((val) & 0xff) << 16)) +/* Base Port number 0 (15:0) */ +#define LTQ_ES_TCP_PF0_REG_BASEPT0 (0xffff) +#define LTQ_ES_TCP_PF0_REG_BASEPT0_VAL(val) (((val) & 0xffff) << 0) +#define LTQ_ES_TCP_PF0_REG_BASEPT0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_BASEPT0) >> 0) & 0xffff) +#define LTQ_ES_TCP_PF0_REG_BASEPT0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_BASEPT0) | (((val) & 0xffff) << 0)) + +/******************************************************************************* + * Reserved DA(0180C2000003~0180C2000000) control register + ******************************************************************************/ + +/* Valid bit for 0180C2000003 (31) */ +#define LTQ_ES_RA_03_00_REG_RA03_VALID (0x1 << 31) +#define LTQ_ES_RA_03_00_REG_RA03_VALID_VAL(val) (((val) & 0x1) << 31) +#define LTQ_ES_RA_03_00_REG_RA03_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_VALID) >> 31) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA03_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_VALID) | (((val) & 0x1) << 31)) +/* Span bit for 0180C2000003 (30) */ +#define LTQ_ES_RA_03_00_REG_RA03_SPAN (0x1 << 30) +#define LTQ_ES_RA_03_00_REG_RA03_SPAN_VAL(val) (((val) & 0x1) << 30) +#define LTQ_ES_RA_03_00_REG_RA03_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_SPAN) >> 30) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA03_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_SPAN) | (((val) & 0x1) << 30)) +/* Management bit for 0180C2000003 (29) */ +#define LTQ_ES_RA_03_00_REG_RA03_MG (0x1 << 29) +#define LTQ_ES_RA_03_00_REG_RA03_MG_VAL(val) (((val) & 0x1) << 29) +#define LTQ_ES_RA_03_00_REG_RA03_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_MG) >> 29) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA03_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_MG) | (((val) & 0x1) << 29)) +/* Cross_VLAN bit for 0180C2000003 (28) */ +#define LTQ_ES_RA_03_00_REG_RA03_CV (0x1 << 28) +#define LTQ_ES_RA_03_00_REG_RA03_CV_VAL(val) (((val) & 0x1) << 28) +#define LTQ_ES_RA_03_00_REG_RA03_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_CV) >> 28) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA03_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_CV) | (((val) & 0x1) << 28)) +/* TXTAG bit for 0180C2000003 (27:26) */ +#define LTQ_ES_RA_03_00_REG_RA03_TXTAG (0x3 << 26) +#define LTQ_ES_RA_03_00_REG_RA03_TXTAG_VAL(val) (((val) & 0x3) << 26) +#define LTQ_ES_RA_03_00_REG_RA03_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_TXTAG) >> 26) & 0x3) +#define LTQ_ES_RA_03_00_REG_RA03_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_TXTAG) | (((val) & 0x3) << 26)) +/* Action bit for 0180C2000003 (25:24) */ +#define LTQ_ES_RA_03_00_REG_RA03_ACT (0x3 << 24) +#define LTQ_ES_RA_03_00_REG_RA03_ACT_VAL(val) (((val) & 0x3) << 24) +#define LTQ_ES_RA_03_00_REG_RA03_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_ACT) >> 24) & 0x3) +#define LTQ_ES_RA_03_00_REG_RA03_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_ACT) | (((val) & 0x3) << 24)) +/* Valid bit for 0180C2000002 (23) */ +#define LTQ_ES_RA_03_00_REG_RA02_VALID (0x1 << 23) +#define LTQ_ES_RA_03_00_REG_RA02_VALID_VAL(val) (((val) & 0x1) << 23) +#define LTQ_ES_RA_03_00_REG_RA02_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_VALID) >> 23) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA02_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_VALID) | (((val) & 0x1) << 23)) +/* Span bit for 0180C2000002 (22) */ +#define LTQ_ES_RA_03_00_REG_RA02_SPAN (0x1 << 22) +#define LTQ_ES_RA_03_00_REG_RA02_SPAN_VAL(val) (((val) & 0x1) << 22) +#define LTQ_ES_RA_03_00_REG_RA02_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_SPAN) >> 22) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA02_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_SPAN) | (((val) & 0x1) << 22)) +/* Management bit for 0180C2000002 (21) */ +#define LTQ_ES_RA_03_00_REG_RA02_MG (0x1 << 21) +#define LTQ_ES_RA_03_00_REG_RA02_MG_VAL(val) (((val) & 0x1) << 21) +#define LTQ_ES_RA_03_00_REG_RA02_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_MG) >> 21) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA02_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_MG) | (((val) & 0x1) << 21)) +/* Cross_VLAN bit for 0180C2000002 (20) */ +#define LTQ_ES_RA_03_00_REG_RA02_CV (0x1 << 20) +#define LTQ_ES_RA_03_00_REG_RA02_CV_VAL(val) (((val) & 0x1) << 20) +#define LTQ_ES_RA_03_00_REG_RA02_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_CV) >> 20) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA02_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_CV) | (((val) & 0x1) << 20)) +/* TXTAG bit for 0180C2000002 (19:18) */ +#define LTQ_ES_RA_03_00_REG_RA02_TXTAG (0x3 << 18) +#define LTQ_ES_RA_03_00_REG_RA02_TXTAG_VAL(val) (((val) & 0x3) << 18) +#define LTQ_ES_RA_03_00_REG_RA02_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_TXTAG) >> 18) & 0x3) +#define LTQ_ES_RA_03_00_REG_RA02_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_TXTAG) | (((val) & 0x3) << 18)) +/* Action bit for 0180C2000002 (17:16) */ +#define LTQ_ES_RA_03_00_REG_RA02_ACT (0x3 << 16) +#define LTQ_ES_RA_03_00_REG_RA02_ACT_VAL(val) (((val) & 0x3) << 16) +#define LTQ_ES_RA_03_00_REG_RA02_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_ACT) >> 16) & 0x3) +#define LTQ_ES_RA_03_00_REG_RA02_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_ACT) | (((val) & 0x3) << 16)) +/* Valid bit for 0180C2000001 (15) */ +#define LTQ_ES_RA_03_00_REG_RA01_VALID (0x1 << 15) +#define LTQ_ES_RA_03_00_REG_RA01_VALID_VAL(val) (((val) & 0x1) << 15) +#define LTQ_ES_RA_03_00_REG_RA01_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_VALID) >> 15) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA01_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_VALID) | (((val) & 0x1) << 15)) +/* Span bit for 0180C2000001 (14) */ +#define LTQ_ES_RA_03_00_REG_RA01_SPAN (0x1 << 14) +#define LTQ_ES_RA_03_00_REG_RA01_SPAN_VAL(val) (((val) & 0x1) << 14) +#define LTQ_ES_RA_03_00_REG_RA01_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_SPAN) >> 14) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA01_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_SPAN) | (((val) & 0x1) << 14)) +/* Management bit for 0180C2000001 (13) */ +#define LTQ_ES_RA_03_00_REG_RA01_MG (0x1 << 13) +#define LTQ_ES_RA_03_00_REG_RA01_MG_VAL(val) (((val) & 0x1) << 13) +#define LTQ_ES_RA_03_00_REG_RA01_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_MG) >> 13) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA01_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_MG) | (((val) & 0x1) << 13)) +/* Cross_VLAN bit for 0180C2000001 (12) */ +#define LTQ_ES_RA_03_00_REG_RA01_CV (0x1 << 12) +#define LTQ_ES_RA_03_00_REG_RA01_CV_VAL(val) (((val) & 0x1) << 12) +#define LTQ_ES_RA_03_00_REG_RA01_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_CV) >> 12) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA01_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_CV) | (((val) & 0x1) << 12)) +/* TXTAG bit for 0180C2000001 (11:10) */ +#define LTQ_ES_RA_03_00_REG_RA01_TXTAG (0x3 << 10) +#define LTQ_ES_RA_03_00_REG_RA01_TXTAG_VAL(val) (((val) & 0x3) << 10) +#define LTQ_ES_RA_03_00_REG_RA01_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_TXTAG) >> 10) & 0x3) +#define LTQ_ES_RA_03_00_REG_RA01_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_TXTAG) | (((val) & 0x3) << 10)) +/* Action bit for 0180C2000001 (9:8) */ +#define LTQ_ES_RA_03_00_REG_RA01_ACT (0x3 << 8) +#define LTQ_ES_RA_03_00_REG_RA01_ACT_VAL(val) (((val) & 0x3) << 8) +#define LTQ_ES_RA_03_00_REG_RA01_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_ACT) >> 8) & 0x3) +#define LTQ_ES_RA_03_00_REG_RA01_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_ACT) | (((val) & 0x3) << 8)) +/* Valid bit for 0180C2000000 (7) */ +#define LTQ_ES_RA_03_00_REG_RA00_VALID (0x1 << 7) +#define LTQ_ES_RA_03_00_REG_RA00_VALID_VAL(val) (((val) & 0x1) << 7) +#define LTQ_ES_RA_03_00_REG_RA00_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_VALID) >> 7) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA00_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_VALID) | (((val) & 0x1) << 7)) +/* Span bit for 0180C2000000 (6) */ +#define LTQ_ES_RA_03_00_REG_RA00_SPAN (0x1 << 6) +#define LTQ_ES_RA_03_00_REG_RA00_SPAN_VAL(val) (((val) & 0x1) << 6) +#define LTQ_ES_RA_03_00_REG_RA00_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_SPAN) >> 6) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA00_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_SPAN) | (((val) & 0x1) << 6)) +/* Management bit for 0180C2000000 (5) */ +#define LTQ_ES_RA_03_00_REG_RA00_MG (0x1 << 5) +#define LTQ_ES_RA_03_00_REG_RA00_MG_VAL(val) (((val) & 0x1) << 5) +#define LTQ_ES_RA_03_00_REG_RA00_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_MG) >> 5) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA00_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_MG) | (((val) & 0x1) << 5)) +/* Cross_VLAN bit for 0180C2000000 (4) */ +#define LTQ_ES_RA_03_00_REG_RA00_CV (0x1 << 4) +#define LTQ_ES_RA_03_00_REG_RA00_CV_VAL(val) (((val) & 0x1) << 4) +#define LTQ_ES_RA_03_00_REG_RA00_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_CV) >> 4) & 0x1) +#define LTQ_ES_RA_03_00_REG_RA00_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_CV) | (((val) & 0x1) << 4)) +/* TXTAG bit for 0180C2000000 (3:2) */ +#define LTQ_ES_RA_03_00_REG_RA00_TXTAG (0x3 << 2) +#define LTQ_ES_RA_03_00_REG_RA00_TXTAG_VAL(val) (((val) & 0x3) << 2) +#define LTQ_ES_RA_03_00_REG_RA00_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_TXTAG) >> 2) & 0x3) +#define LTQ_ES_RA_03_00_REG_RA00_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_TXTAG) | (((val) & 0x3) << 2)) +/* Action bit for 0180C2000000 (1:0) */ +#define LTQ_ES_RA_03_00_REG_RA00_ACT (0x3) +#define LTQ_ES_RA_03_00_REG_RA00_ACT_VAL(val) (((val) & 0x3) << 0) +#define LTQ_ES_RA_03_00_REG_RA00_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_ACT) >> 0) & 0x3) +#define LTQ_ES_RA_03_00_REG_RA00_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_ACT) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * Protocol Filter 0 + ******************************************************************************/ + +/* Value Compared with Protocol in IP Header (31:24) */ +#define LTQ_ES_PRTCL_F0_REG_PFR3 (0xff << 24) +#define LTQ_ES_PRTCL_F0_REG_PFR3_VAL(val) (((val) & 0xff) << 24) +#define LTQ_ES_PRTCL_F0_REG_PFR3_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR3) >> 24) & 0xff) +#define LTQ_ES_PRTCL_F0_REG_PFR3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR3) | (((val) & 0xff) << 24)) +/* Value Compared with Protocol in IP Header (23:16) */ +#define LTQ_ES_PRTCL_F0_REG_PFR2 (0xff << 16) +#define LTQ_ES_PRTCL_F0_REG_PFR2_VAL(val) (((val) & 0xff) << 16) +#define LTQ_ES_PRTCL_F0_REG_PFR2_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR2) >> 16) & 0xff) +#define LTQ_ES_PRTCL_F0_REG_PFR2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR2) | (((val) & 0xff) << 16)) +/* Value Compared with Protocol in IP Header (15:8) */ +#define LTQ_ES_PRTCL_F0_REG_PFR1 (0xff << 8) +#define LTQ_ES_PRTCL_F0_REG_PFR1_VAL(val) (((val) & 0xff) << 8) +#define LTQ_ES_PRTCL_F0_REG_PFR1_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR1) >> 8) & 0xff) +#define LTQ_ES_PRTCL_F0_REG_PFR1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR1) | (((val) & 0xff) << 8)) +/* Value Compared with Protocol in IP Header (7:0) */ +#define LTQ_ES_PRTCL_F0_REG_PFR0 (0xff) +#define LTQ_ES_PRTCL_F0_REG_PFR0_VAL(val) (((val) & 0xff) << 0) +#define LTQ_ES_PRTCL_F0_REG_PFR0_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR0) >> 0) & 0xff) +#define LTQ_ES_PRTCL_F0_REG_PFR0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR0) | (((val) & 0xff) << 0)) + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/irq.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/irq.h new file mode 100644 index 0000000000..06dc173544 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/irq.h @@ -0,0 +1,36 @@ +/* + * arch/mips/include/asm/mach-lantiq/svip/irq.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2010 Lantiq + * + */ + +#ifndef __IRQ_H +#define __IRQ_H + +#include + +#define NR_IRQS 264 + +#include_next + +/* Functions for EXINT handling */ +extern int ifx_enable_external_int(u32 exint, u32 mode); +extern int ifx_disable_external_int(u32 exint); +extern int ifx_external_int_level(u32 exint); + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/lantiq_soc.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/lantiq_soc.h new file mode 100644 index 0000000000..697d672f36 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/lantiq_soc.h @@ -0,0 +1,71 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#ifndef _LTQ_SVIP_H__ +#define _LTQ_SVIP_H__ + +#ifdef CONFIG_SOC_SVIP + +#include + +/* Chip IDs */ +#define SOC_ID_SVIP 0x169 + +/* SoC Types */ +#define SOC_TYPE_SVIP 0x01 + +/* ASC0/1 - serial port */ +#define LTQ_ASC0_BASE_ADDR 0x14100100 +#define LTQ_ASC1_BASE_ADDR 0x14100200 +#define LTQ_ASC_SIZE 0x100 +#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR) + +#define LTQ_ASC_TIR(x) (INT_NUM_IM0_IRL0 + (x * 8)) +#define LTQ_ASC_RIR(x) (INT_NUM_IM0_IRL0 + (x * 8) + 2) +#define LTQ_ASC_EIR(x) (INT_NUM_IM0_IRL0 + (x * 8) + 3) + +/* ICU - interrupt control unit */ +#define LTQ_ICU_BASE_ADDR 0x14106000 +#define LTQ_ICU_BASE_ADDR1 0x14106028 +#define LTQ_ICU_BASE_ADDR2 0x1E016000 +#define LTQ_ICU_BASE_ADDR3 0x1E016028 +#define LTQ_ICU_BASE_ADDR4 0x14106050 +#define LTQ_ICU_BASE_ADDR5 0x14106078 +#define LTQ_ICU_SIZE 0x100 + +/* WDT */ +#define LTQ_WDT_BASE_ADDR 0x1F8803F0 +#define LTQ_WDT_SIZE 0x10 + +/* Status */ +#define LTQ_STATUS_BASE_ADDR (KSEG1 + 0x1E000500) +#define LTQ_STATUS_CHIPID ((u32 *)(LTQ_STATUS_BASE_ADDR + 0x000C)) + +#define LTQ_EIU_BASE_ADDR 0 + +#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) +#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) + +extern __iomem void *ltq_ebu_membase; + +extern void ltq_gpio_configure(int port, int pin, bool dirin, bool puen, + bool altsel0, bool altsel1); +extern int ltq_port_get_dir(unsigned int port, unsigned int pin); +extern int ltq_port_get_puden(unsigned int port, unsigned int pin); +extern int ltq_port_get_altsel0(unsigned int port, unsigned int pin); +extern int ltq_port_get_altsel1(unsigned int port, unsigned int pin); + +#define ltq_is_ar9() 0 +#define ltq_is_vr9() 0 +#define ltq_is_falcon() 0 + +#define BS_FLASH 0 +#define LTQ_RST_CAUSE_WDTRST 0x2 + +#endif /* CONFIG_SOC_SVIP */ +#endif /* _LTQ_SVIP_H__ */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/mps_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/mps_reg.h new file mode 100644 index 0000000000..79966b7be7 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/mps_reg.h @@ -0,0 +1,242 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __MPS_REG_H +#define __MPS_REG_H + +#define mbs_r32(reg) ltq_r32(&mbs->reg) +#define mbs_w32(val, reg) ltq_w32(val, &mbs->reg) +#define mbs_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &mbs->reg) + +/** MBS register structure */ +struct svip_reg_mbs { + unsigned long reserved0[4]; + unsigned long mbsr0; /* 0x0010 */ + unsigned long mbsr1; /* 0x0014 */ + unsigned long mbsr2; /* 0x0018 */ + unsigned long mbsr3; /* 0x001c */ + unsigned long mbsr4; /* 0x0020 */ + unsigned long mbsr5; /* 0x0024 */ + unsigned long mbsr6; /* 0x0028 */ + unsigned long mbsr7; /* 0x002c */ + unsigned long mbsr8; /* 0x0030 */ + unsigned long mbsr9; /* 0x0034 */ + unsigned long mbsr10; /* 0x0038 */ + unsigned long mbsr11; /* 0x003c */ + unsigned long mbsr12; /* 0x0040 */ + unsigned long mbsr13; /* 0x0044 */ + unsigned long mbsr14; /* 0x0048 */ + unsigned long mbsr15; /* 0x004c */ + unsigned long mbsr16; /* 0x0050 */ + unsigned long mbsr17; /* 0x0054 */ + unsigned long mbsr18; /* 0x0058 */ + unsigned long mbsr19; /* 0x005c */ + unsigned long mbsr20; /* 0x0060 */ + unsigned long mbsr21; /* 0x0064 */ + unsigned long mbsr22; /* 0x0068 */ + unsigned long mbsr23; /* 0x006c */ + unsigned long mbsr24; /* 0x0070 */ + unsigned long mbsr25; /* 0x0074 */ + unsigned long mbsr26; /* 0x0078 */ + unsigned long mbsr27; /* 0x007c */ + unsigned long mbsr28; /* 0x0080 */ +}; + +/** MPS register structure */ +struct svip_reg_mps { + volatile unsigned long mps_swirn0set; /* 0x0000 */ + volatile unsigned long mps_swirn0en; /* 0x0004 */ + volatile unsigned long mps_swirn0cr; /* 0x0008 */ + volatile unsigned long mps_swirn0icr; /* 0x000C */ + volatile unsigned long mps_swirn1set; /* 0x0010 */ + volatile unsigned long mps_swirn1en; /* 0x0014 */ + volatile unsigned long mps_swirn1cr; /* 0x0018 */ + volatile unsigned long mps_swirn1icr; /* 0x001C */ + volatile unsigned long mps_swirn2set; /* 0x0020 */ + volatile unsigned long mps_swirn2en; /* 0x0024 */ + volatile unsigned long mps_swirn2cr; /* 0x0028 */ + volatile unsigned long mps_swirn2icr; /* 0x002C */ + volatile unsigned long mps_swirn3set; /* 0x0030 */ + volatile unsigned long mps_swirn3en; /* 0x0034 */ + volatile unsigned long mps_swirn3cr; /* 0x0038 */ + volatile unsigned long mps_swirn3icr; /* 0x003C */ + volatile unsigned long mps_swirn4set; /* 0x0040 */ + volatile unsigned long mps_swirn4en; /* 0x0044 */ + volatile unsigned long mps_swirn4cr; /* 0x0048 */ + volatile unsigned long mps_swirn4icr; /* 0x004C */ + volatile unsigned long mps_swirn5set; /* 0x0050 */ + volatile unsigned long mps_swirn5en; /* 0x0054 */ + volatile unsigned long mps_swirn5cr; /* 0x0058 */ + volatile unsigned long mps_swirn5icr; /* 0x005C */ + volatile unsigned long mps_swirn6set; /* 0x0060 */ + volatile unsigned long mps_swirn6en; /* 0x0064 */ + volatile unsigned long mps_swirn6cr; /* 0x0068 */ + volatile unsigned long mps_swirn6icr; /* 0x006C */ + volatile unsigned long mps_swirn7set; /* 0x0070 */ + volatile unsigned long mps_swirn7en; /* 0x0074 */ + volatile unsigned long mps_swirn7cr; /* 0x0078 */ + volatile unsigned long mps_swirn7icr; /* 0x007C */ + volatile unsigned long mps_swirn8set; /* 0x0080 */ + volatile unsigned long mps_swirn8en; /* 0x0084 */ + volatile unsigned long mps_swirn8cr; /* 0x0088 */ + volatile unsigned long mps_swirn8icr; /* 0x008C */ +}; + +/* Software Interrupt */ +#define IFX_MPS_SWIRN0SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0000)) +#define IFX_MPS_SWIRN0EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0004)) +#define IFX_MPS_SWIRN0CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0008)) +#define IFX_MPS_SWIRN0ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x000C)) +#define IFX_MPS_SWIRN1SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0010)) +#define IFX_MPS_SWIRN1EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0014)) +#define IFX_MPS_SWIRN1CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0018)) +#define IFX_MPS_SWIRN1ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x001C)) +#define IFX_MPS_SWIRN2SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0020)) +#define IFX_MPS_SWIRN2EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0024)) +#define IFX_MPS_SWIRN2CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0028)) +#define IFX_MPS_SWIRN2ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x002C)) +#define IFX_MPS_SWIRN3SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0030)) +#define IFX_MPS_SWIRN3EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0034)) +#define IFX_MPS_SWIRN3CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0038)) +#define IFX_MPS_SWIRN3ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x003C)) +#define IFX_MPS_SWIRN4SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0040)) +#define IFX_MPS_SWIRN4EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0044)) +#define IFX_MPS_SWIRN4CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0048)) +#define IFX_MPS_SWIRN4ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x004C)) +#define IFX_MPS_SWIRN5SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0050)) +#define IFX_MPS_SWIRN5EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0054)) +#define IFX_MPS_SWIRN5CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0058)) +#define IFX_MPS_SWIRN5ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x005C)) +#define IFX_MPS_SWIRN6SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0060)) +#define IFX_MPS_SWIRN6EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0064)) +#define IFX_MPS_SWIRN6CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0068)) +#define IFX_MPS_SWIRN6ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x006C)) +#define IFX_MPS_SWIRN7SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0070)) +#define IFX_MPS_SWIRN7EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0074)) +#define IFX_MPS_SWIRN7CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0078)) +#define IFX_MPS_SWIRN7ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x007C)) +#define IFX_MPS_SWIRN8SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0080)) +#define IFX_MPS_SWIRN8EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0084)) +#define IFX_MPS_SWIRN8ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x008C)) +#define IFX_MPS_SWIRN8CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0088)) + +/******************************************************************************* + * MPS_SWIRNSET Register + ******************************************************************************/ + +/* Software Interrupt Request IR5 (5) */ +#define IFX_MPS_SWIRNSET_IR5 (0x1 << 5) +#define IFX_MPS_SWIRNSET_IR5_VAL(val) (((val) & 0x1) << 5) +#define IFX_MPS_SWIRNSET_IR5_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR5) | (val) & 1) << 5) +/* Software Interrupt Request IR4 (4) */ +#define IFX_MPS_SWIRNSET_IR4 (0x1 << 4) +#define IFX_MPS_SWIRNSET_IR4_VAL(val) (((val) & 0x1) << 4) +#define IFX_MPS_SWIRNSET_IR4_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR4) | (val) & 1) << 4) +/* Software Interrupt Request IR3 (3) */ +#define IFX_MPS_SWIRNSET_IR3 (0x1 << 3) +#define IFX_MPS_SWIRNSET_IR3_VAL(val) (((val) & 0x1) << 3) +#define IFX_MPS_SWIRNSET_IR3_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR3) | (val) & 1) << 3) +/* Software Interrupt Request IR2 (2) */ +#define IFX_MPS_SWIRNSET_IR2 (0x1 << 2) +#define IFX_MPS_SWIRNSET_IR2_VAL(val) (((val) & 0x1) << 2) +#define IFX_MPS_SWIRNSET_IR2_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR2) | (val) & 1) << 2) +/* Software Interrupt Request IR1 (1) */ +#define IFX_MPS_SWIRNSET_IR1 (0x1 << 1) +#define IFX_MPS_SWIRNSET_IR1_VAL(val) (((val) & 0x1) << 1) +#define IFX_MPS_SWIRNSET_IR1_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR1) | (val) & 1) << 1) +/* Software Interrupt Request IR0 (0) */ +#define IFX_MPS_SWIRNSET_IR0 (0x1) +#define IFX_MPS_SWIRNSET_IR0_VAL(val) (((val) & 0x1) << 0) +#define IFX_MPS_SWIRNSET_IR0_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR0) | (val) & 1) << 0) + +/******************************************************************************* + * MPS_SWIRNEN Register + ******************************************************************************/ + +/* Software Interrupt Request IR5 (5) */ +#define IFX_MPS_SWIRNEN_IR5 (0x1 << 5) +#define IFX_MPS_SWIRNEN_IR5_VAL(val) (((val) & 0x1) << 5) +#define IFX_MPS_SWIRNEN_IR5_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR5) >> 5) & 0x1) +#define IFX_MPS_SWIRNEN_IR5_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR5) | (((val) & 0x1) << 5)) +/* Software Interrupt Request IR4 (4) */ +#define IFX_MPS_SWIRNEN_IR4 (0x1 << 4) +#define IFX_MPS_SWIRNEN_IR4_VAL(val) (((val) & 0x1) << 4) +#define IFX_MPS_SWIRNEN_IR4_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR4) >> 4) & 0x1) +#define IFX_MPS_SWIRNEN_IR4_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR4) | (((val) & 0x1) << 4)) +/* Software Interrupt Request IR3 (3) */ +#define IFX_MPS_SWIRNEN_IR3 (0x1 << 3) +#define IFX_MPS_SWIRNEN_IR3_VAL(val) (((val) & 0x1) << 3) +#define IFX_MPS_SWIRNEN_IR3_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR3) >> 3) & 0x1) +#define IFX_MPS_SWIRNEN_IR3_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR3) | (((val) & 0x1) << 3)) +/* Software Interrupt Request IR2 (2) */ +#define IFX_MPS_SWIRNEN_IR2 (0x1 << 2) +#define IFX_MPS_SWIRNEN_IR2_VAL(val) (((val) & 0x1) << 2) +#define IFX_MPS_SWIRNEN_IR2_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR2) >> 2) & 0x1) +#define IFX_MPS_SWIRNEN_IR2_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR2) | (((val) & 0x1) << 2)) +/* Software Interrupt Request IR1 (1) */ +#define IFX_MPS_SWIRNEN_IR1 (0x1 << 1) +#define IFX_MPS_SWIRNEN_IR1_VAL(val) (((val) & 0x1) << 1) +#define IFX_MPS_SWIRNEN_IR1_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR1) >> 1) & 0x1) +#define IFX_MPS_SWIRNEN_IR1_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR1) | (((val) & 0x1) << 1)) +/* Software Interrupt Request IR0 (0) */ +#define IFX_MPS_SWIRNEN_IR0 (0x1) +#define IFX_MPS_SWIRNEN_IR0_VAL(val) (((val) & 0x1) << 0) +#define IFX_MPS_SWIRNEN_IR0_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR0) >> 0) & 0x1) +#define IFX_MPS_SWIRNEN_IR0_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * MPS_SWIRNICR Register + ******************************************************************************/ + +/* Software Interrupt Request IR5 (5) */ +#define IFX_MPS_SWIRNICR_IR5 (0x1 << 5) +#define IFX_MPS_SWIRNICR_IR5_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR5) >> 5) & 0x1) +/* Software Interrupt Request IR4 (4) */ +#define IFX_MPS_SWIRNICR_IR4 (0x1 << 4) +#define IFX_MPS_SWIRNICR_IR4_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR4) >> 4) & 0x1) +/* Software Interrupt Request IR3 (3) */ +#define IFX_MPS_SWIRNICR_IR3 (0x1 << 3) +#define IFX_MPS_SWIRNICR_IR3_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR3) >> 3) & 0x1) +/* Software Interrupt Request IR2 (2) */ +#define IFX_MPS_SWIRNICR_IR2 (0x1 << 2) +#define IFX_MPS_SWIRNICR_IR2_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR2) >> 2) & 0x1) +/* Software Interrupt Request IR1 (1) */ +#define IFX_MPS_SWIRNICR_IR1 (0x1 << 1) +#define IFX_MPS_SWIRNICR_IR1_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR1) >> 1) & 0x1) +/* Software Interrupt Request IR0 (0) */ +#define IFX_MPS_SWIRNICR_IR0 (0x1) +#define IFX_MPS_SWIRNICR_IR0_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR0) >> 0) & 0x1) + +/******************************************************************************* + * MPS_SWIRNCR Register + ******************************************************************************/ + +/* Software Interrupt Request IR5 (5) */ +#define IFX_MPS_SWIRNCR_IR5 (0x1 << 5) +#define IFX_MPS_SWIRNCR_IR5_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR5) >> 5) & 0x1) +/* Software Interrupt Request IR4 (4) */ +#define IFX_MPS_SWIRNCR_IR4 (0x1 << 4) +#define IFX_MPS_SWIRNCR_IR4_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR4) >> 4) & 0x1) +/* Software Interrupt Request IR3 (3) */ +#define IFX_MPS_SWIRNCR_IR3 (0x1 << 3) +#define IFX_MPS_SWIRNCR_IR3_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR3) >> 3) & 0x1) +/* Software Interrupt Request IR2 (2) */ +#define IFX_MPS_SWIRNCR_IR2 (0x1 << 2) +#define IFX_MPS_SWIRNCR_IR2_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR2) >> 2) & 0x1) +/* Software Interrupt Request IR1 (1) */ +#define IFX_MPS_SWIRNCR_IR1 (0x1 << 1) +#define IFX_MPS_SWIRNCR_IR1_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR1) >> 1) & 0x1) +/* Software Interrupt Request IR0 (0) */ +#define IFX_MPS_SWIRNCR_IR0 (0x1) +#define IFX_MPS_SWIRNCR_IR0_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR0) >> 0) & 0x1) + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/port_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/port_reg.h new file mode 100644 index 0000000000..57d04917fc --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/port_reg.h @@ -0,0 +1,3262 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __PORT_REG_H +#define __PORT_REG_H + +#define port_r32(reg) __raw_readl(®) +#define port_w32(val, reg) __raw_writel(val, ®) + +/** PORT register structure */ +struct svip_reg_port { + volatile u32 out; /* 0x0000 */ + volatile u32 in; /* 0x0004 */ + volatile u32 dir; /* 0x0008 */ + volatile u32 altsel0; /* 0x000C */ + volatile u32 altsel1; /* 0x0010 */ + volatile u32 puen; /* 0x0014 */ + volatile u32 exintcr0; /* 0x0018 */ + volatile u32 exintcr1; /* 0x001C */ + volatile u32 irncr; /* 0x0020 */ + volatile u32 irnicr; /* 0x0024 */ + volatile u32 irnen; /* 0x0028 */ + volatile u32 irncfg; /* 0x002C */ + volatile u32 irnenset; /* 0x0030 */ + volatile u32 irnenclr; /* 0x0034 */ +}; + +/******************************************************************************* + * Port 0 Data Output Register + ******************************************************************************/ + +/* Port 0 Pin # Output Value (19) */ +#define PORT_P0_OUT_P19 (0x1 << 19) +#define PORT_P0_OUT_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P0_OUT_P19_GET(val) ((((val) & PORT_P0_OUT_P19) >> 19) & 0x1) +#define PORT_P0_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P19) | (((val) & 0x1) << 19)) +/* Port 0 Pin # Output Value (18) */ +#define PORT_P0_OUT_P18 (0x1 << 18) +#define PORT_P0_OUT_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P0_OUT_P18_GET(val) ((((val) & PORT_P0_OUT_P18) >> 18) & 0x1) +#define PORT_P0_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P18) | (((val) & 0x1) << 18)) +/* Port 0 Pin # Output Value (17) */ +#define PORT_P0_OUT_P17 (0x1 << 17) +#define PORT_P0_OUT_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P0_OUT_P17_GET(val) ((((val) & PORT_P0_OUT_P17) >> 17) & 0x1) +#define PORT_P0_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P17) | (((val) & 0x1) << 17)) +/* Port 0 Pin # Output Value (16) */ +#define PORT_P0_OUT_P16 (0x1 << 16) +#define PORT_P0_OUT_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P0_OUT_P16_GET(val) ((((val) & PORT_P0_OUT_P16) >> 16) & 0x1) +#define PORT_P0_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P16) | (((val) & 0x1) << 16)) +/* Port 0 Pin # Output Value (15) */ +#define PORT_P0_OUT_P15 (0x1 << 15) +#define PORT_P0_OUT_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P0_OUT_P15_GET(val) ((((val) & PORT_P0_OUT_P15) >> 15) & 0x1) +#define PORT_P0_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P15) | (((val) & 0x1) << 15)) +/* Port 0 Pin # Output Value (14) */ +#define PORT_P0_OUT_P14 (0x1 << 14) +#define PORT_P0_OUT_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P0_OUT_P14_GET(val) ((((val) & PORT_P0_OUT_P14) >> 14) & 0x1) +#define PORT_P0_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P14) | (((val) & 0x1) << 14)) +/* Port 0 Pin # Output Value (13) */ +#define PORT_P0_OUT_P13 (0x1 << 13) +#define PORT_P0_OUT_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_OUT_P13_GET(val) ((((val) & PORT_P0_OUT_P13) >> 13) & 0x1) +#define PORT_P0_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P13) | (((val) & 0x1) << 13)) +/* Port 0 Pin # Output Value (12) */ +#define PORT_P0_OUT_P12 (0x1 << 12) +#define PORT_P0_OUT_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_OUT_P12_GET(val) ((((val) & PORT_P0_OUT_P12) >> 12) & 0x1) +#define PORT_P0_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P12) | (((val) & 0x1) << 12)) +/* Port 0 Pin # Output Value (11) */ +#define PORT_P0_OUT_P11 (0x1 << 11) +#define PORT_P0_OUT_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_OUT_P11_GET(val) ((((val) & PORT_P0_OUT_P11) >> 11) & 0x1) +#define PORT_P0_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P11) | (((val) & 0x1) << 11)) +/* Port 0 Pin # Output Value (10) */ +#define PORT_P0_OUT_P10 (0x1 << 10) +#define PORT_P0_OUT_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_OUT_P10_GET(val) ((((val) & PORT_P0_OUT_P10) >> 10) & 0x1) +#define PORT_P0_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P10) | (((val) & 0x1) << 10)) +/* Port 0 Pin # Output Value (9) */ +#define PORT_P0_OUT_P9 (0x1 << 9) +#define PORT_P0_OUT_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_OUT_P9_GET(val) ((((val) & PORT_P0_OUT_P9) >> 9) & 0x1) +#define PORT_P0_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P9) | (((val) & 0x1) << 9)) +/* Port 0 Pin # Output Value (8) */ +#define PORT_P0_OUT_P8 (0x1 << 8) +#define PORT_P0_OUT_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_OUT_P8_GET(val) ((((val) & PORT_P0_OUT_P8) >> 8) & 0x1) +#define PORT_P0_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P8) | (((val) & 0x1) << 8)) +/* Port 0 Pin # Output Value (7) */ +#define PORT_P0_OUT_P7 (0x1 << 7) +#define PORT_P0_OUT_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_OUT_P7_GET(val) ((((val) & PORT_P0_OUT_P7) >> 7) & 0x1) +#define PORT_P0_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P7) | (((val) & 0x1) << 7)) +/* Port 0 Pin # Output Value (6) */ +#define PORT_P0_OUT_P6 (0x1 << 6) +#define PORT_P0_OUT_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P0_OUT_P6_GET(val) ((((val) & PORT_P0_OUT_P6) >> 6) & 0x1) +#define PORT_P0_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P6) | (((val) & 0x1) << 6)) +/* Port 0 Pin # Output Value (5) */ +#define PORT_P0_OUT_P5 (0x1 << 5) +#define PORT_P0_OUT_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P0_OUT_P5_GET(val) ((((val) & PORT_P0_OUT_P5) >> 5) & 0x1) +#define PORT_P0_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P5) | (((val) & 0x1) << 5)) +/* Port 0 Pin # Output Value (4) */ +#define PORT_P0_OUT_P4 (0x1 << 4) +#define PORT_P0_OUT_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P0_OUT_P4_GET(val) ((((val) & PORT_P0_OUT_P4) >> 4) & 0x1) +#define PORT_P0_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P4) | (((val) & 0x1) << 4)) +/* Port 0 Pin # Output Value (3) */ +#define PORT_P0_OUT_P3 (0x1 << 3) +#define PORT_P0_OUT_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P0_OUT_P3_GET(val) ((((val) & PORT_P0_OUT_P3) >> 3) & 0x1) +#define PORT_P0_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P3) | (((val) & 0x1) << 3)) +/* Port 0 Pin # Output Value (2) */ +#define PORT_P0_OUT_P2 (0x1 << 2) +#define PORT_P0_OUT_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P0_OUT_P2_GET(val) ((((val) & PORT_P0_OUT_P2) >> 2) & 0x1) +#define PORT_P0_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P2) | (((val) & 0x1) << 2)) +/* Port 0 Pin # Output Value (1) */ +#define PORT_P0_OUT_P1 (0x1 << 1) +#define PORT_P0_OUT_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P0_OUT_P1_GET(val) ((((val) & PORT_P0_OUT_P1) >> 1) & 0x1) +#define PORT_P0_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P1) | (((val) & 0x1) << 1)) +/* Port 0 Pin # Output Value (0) */ +#define PORT_P0_OUT_P0 (0x1) +#define PORT_P0_OUT_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P0_OUT_P0_GET(val) ((((val) & PORT_P0_OUT_P0) >> 0) & 0x1) +#define PORT_P0_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 0 Data Input Register + ******************************************************************************/ + +/* Port 0 Pin # Latched Input Value (19) */ +#define PORT_P0_IN_P19 (0x1 << 19) +#define PORT_P0_IN_P19_GET(val) ((((val) & PORT_P0_IN_P19) >> 19) & 0x1) +/* Port 0 Pin # Latched Input Value (18) */ +#define PORT_P0_IN_P18 (0x1 << 18) +#define PORT_P0_IN_P18_GET(val) ((((val) & PORT_P0_IN_P18) >> 18) & 0x1) +/* Port 0 Pin # Latched Input Value (17) */ +#define PORT_P0_IN_P17 (0x1 << 17) +#define PORT_P0_IN_P17_GET(val) ((((val) & PORT_P0_IN_P17) >> 17) & 0x1) +/* Port 0 Pin # Latched Input Value (16) */ +#define PORT_P0_IN_P16 (0x1 << 16) +#define PORT_P0_IN_P16_GET(val) ((((val) & PORT_P0_IN_P16) >> 16) & 0x1) +/* Port 0 Pin # Latched Input Value (15) */ +#define PORT_P0_IN_P15 (0x1 << 15) +#define PORT_P0_IN_P15_GET(val) ((((val) & PORT_P0_IN_P15) >> 15) & 0x1) +/* Port 0 Pin # Latched Input Value (14) */ +#define PORT_P0_IN_P14 (0x1 << 14) +#define PORT_P0_IN_P14_GET(val) ((((val) & PORT_P0_IN_P14) >> 14) & 0x1) +/* Port 0 Pin # Latched Input Value (13) */ +#define PORT_P0_IN_P13 (0x1 << 13) +#define PORT_P0_IN_P13_GET(val) ((((val) & PORT_P0_IN_P13) >> 13) & 0x1) +/* Port 0 Pin # Latched Input Value (12) */ +#define PORT_P0_IN_P12 (0x1 << 12) +#define PORT_P0_IN_P12_GET(val) ((((val) & PORT_P0_IN_P12) >> 12) & 0x1) +/* Port 0 Pin # Latched Input Value (11) */ +#define PORT_P0_IN_P11 (0x1 << 11) +#define PORT_P0_IN_P11_GET(val) ((((val) & PORT_P0_IN_P11) >> 11) & 0x1) +/* Port 0 Pin # Latched Input Value (10) */ +#define PORT_P0_IN_P10 (0x1 << 10) +#define PORT_P0_IN_P10_GET(val) ((((val) & PORT_P0_IN_P10) >> 10) & 0x1) +/* Port 0 Pin # Latched Input Value (9) */ +#define PORT_P0_IN_P9 (0x1 << 9) +#define PORT_P0_IN_P9_GET(val) ((((val) & PORT_P0_IN_P9) >> 9) & 0x1) +/* Port 0 Pin # Latched Input Value (8) */ +#define PORT_P0_IN_P8 (0x1 << 8) +#define PORT_P0_IN_P8_GET(val) ((((val) & PORT_P0_IN_P8) >> 8) & 0x1) +/* Port 0 Pin # Latched Input Value (7) */ +#define PORT_P0_IN_P7 (0x1 << 7) +#define PORT_P0_IN_P7_GET(val) ((((val) & PORT_P0_IN_P7) >> 7) & 0x1) +/* Port 0 Pin # Latched Input Value (6) */ +#define PORT_P0_IN_P6 (0x1 << 6) +#define PORT_P0_IN_P6_GET(val) ((((val) & PORT_P0_IN_P6) >> 6) & 0x1) +/* Port 0 Pin # Latched Input Value (5) */ +#define PORT_P0_IN_P5 (0x1 << 5) +#define PORT_P0_IN_P5_GET(val) ((((val) & PORT_P0_IN_P5) >> 5) & 0x1) +/* Port 0 Pin # Latched Input Value (4) */ +#define PORT_P0_IN_P4 (0x1 << 4) +#define PORT_P0_IN_P4_GET(val) ((((val) & PORT_P0_IN_P4) >> 4) & 0x1) +/* Port 0 Pin # Latched Input Value (3) */ +#define PORT_P0_IN_P3 (0x1 << 3) +#define PORT_P0_IN_P3_GET(val) ((((val) & PORT_P0_IN_P3) >> 3) & 0x1) +/* Port 0 Pin # Latched Input Value (2) */ +#define PORT_P0_IN_P2 (0x1 << 2) +#define PORT_P0_IN_P2_GET(val) ((((val) & PORT_P0_IN_P2) >> 2) & 0x1) +/* Port 0 Pin # Latched Input Value (1) */ +#define PORT_P0_IN_P1 (0x1 << 1) +#define PORT_P0_IN_P1_GET(val) ((((val) & PORT_P0_IN_P1) >> 1) & 0x1) +/* Port 0 Pin # Latched Input Value (0) */ +#define PORT_P0_IN_P0 (0x1) +#define PORT_P0_IN_P0_GET(val) ((((val) & PORT_P0_IN_P0) >> 0) & 0x1) + +/******************************************************************************* + * Port 0 Direction Register + ******************************************************************************/ + +/* Port 0 Pin #Direction Control (19) */ +#define PORT_P0_DIR_P19 (0x1 << 19) +#define PORT_P0_DIR_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P0_DIR_P19_GET(val) ((((val) & PORT_P0_DIR_P19) >> 19) & 0x1) +#define PORT_P0_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P19) | (((val) & 0x1) << 19)) +/* Port 0 Pin #Direction Control (18) */ +#define PORT_P0_DIR_P18 (0x1 << 18) +#define PORT_P0_DIR_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P0_DIR_P18_GET(val) ((((val) & PORT_P0_DIR_P18) >> 18) & 0x1) +#define PORT_P0_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P18) | (((val) & 0x1) << 18)) +/* Port 0 Pin #Direction Control (17) */ +#define PORT_P0_DIR_P17 (0x1 << 17) +#define PORT_P0_DIR_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P0_DIR_P17_GET(val) ((((val) & PORT_P0_DIR_P17) >> 17) & 0x1) +#define PORT_P0_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P17) | (((val) & 0x1) << 17)) +/* Port 0 Pin #Direction Control (16) */ +#define PORT_P0_DIR_P16 (0x1 << 16) +#define PORT_P0_DIR_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P0_DIR_P16_GET(val) ((((val) & PORT_P0_DIR_P16) >> 16) & 0x1) +#define PORT_P0_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P16) | (((val) & 0x1) << 16)) +/* Port 0 Pin #Direction Control (15) */ +#define PORT_P0_DIR_P15 (0x1 << 15) +#define PORT_P0_DIR_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P0_DIR_P15_GET(val) ((((val) & PORT_P0_DIR_P15) >> 15) & 0x1) +#define PORT_P0_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P15) | (((val) & 0x1) << 15)) +/* Port 0 Pin #Direction Control (14) */ +#define PORT_P0_DIR_P14 (0x1 << 14) +#define PORT_P0_DIR_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P0_DIR_P14_GET(val) ((((val) & PORT_P0_DIR_P14) >> 14) & 0x1) +#define PORT_P0_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P14) | (((val) & 0x1) << 14)) +/* Port 0 Pin #Direction Control (13) */ +#define PORT_P0_DIR_P13 (0x1 << 13) +#define PORT_P0_DIR_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_DIR_P13_GET(val) ((((val) & PORT_P0_DIR_P13) >> 13) & 0x1) +#define PORT_P0_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P13) | (((val) & 0x1) << 13)) +/* Port 0 Pin #Direction Control (12) */ +#define PORT_P0_DIR_P12 (0x1 << 12) +#define PORT_P0_DIR_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_DIR_P12_GET(val) ((((val) & PORT_P0_DIR_P12) >> 12) & 0x1) +#define PORT_P0_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P12) | (((val) & 0x1) << 12)) +/* Port 0 Pin #Direction Control (11) */ +#define PORT_P0_DIR_P11 (0x1 << 11) +#define PORT_P0_DIR_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_DIR_P11_GET(val) ((((val) & PORT_P0_DIR_P11) >> 11) & 0x1) +#define PORT_P0_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P11) | (((val) & 0x1) << 11)) +/* Port 0 Pin #Direction Control (10) */ +#define PORT_P0_DIR_P10 (0x1 << 10) +#define PORT_P0_DIR_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_DIR_P10_GET(val) ((((val) & PORT_P0_DIR_P10) >> 10) & 0x1) +#define PORT_P0_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P10) | (((val) & 0x1) << 10)) +/* Port 0 Pin #Direction Control (9) */ +#define PORT_P0_DIR_P9 (0x1 << 9) +#define PORT_P0_DIR_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_DIR_P9_GET(val) ((((val) & PORT_P0_DIR_P9) >> 9) & 0x1) +#define PORT_P0_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P9) | (((val) & 0x1) << 9)) +/* Port 0 Pin #Direction Control (8) */ +#define PORT_P0_DIR_P8 (0x1 << 8) +#define PORT_P0_DIR_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_DIR_P8_GET(val) ((((val) & PORT_P0_DIR_P8) >> 8) & 0x1) +#define PORT_P0_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P8) | (((val) & 0x1) << 8)) +/* Port 0 Pin #Direction Control (7) */ +#define PORT_P0_DIR_P7 (0x1 << 7) +#define PORT_P0_DIR_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_DIR_P7_GET(val) ((((val) & PORT_P0_DIR_P7) >> 7) & 0x1) +#define PORT_P0_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P7) | (((val) & 0x1) << 7)) +/* Port 0 Pin #Direction Control (6) */ +#define PORT_P0_DIR_P6 (0x1 << 6) +#define PORT_P0_DIR_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P0_DIR_P6_GET(val) ((((val) & PORT_P0_DIR_P6) >> 6) & 0x1) +#define PORT_P0_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P6) | (((val) & 0x1) << 6)) +/* Port 0 Pin #Direction Control (5) */ +#define PORT_P0_DIR_P5 (0x1 << 5) +#define PORT_P0_DIR_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P0_DIR_P5_GET(val) ((((val) & PORT_P0_DIR_P5) >> 5) & 0x1) +#define PORT_P0_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P5) | (((val) & 0x1) << 5)) +/* Port 0 Pin #Direction Control (4) */ +#define PORT_P0_DIR_P4 (0x1 << 4) +#define PORT_P0_DIR_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P0_DIR_P4_GET(val) ((((val) & PORT_P0_DIR_P4) >> 4) & 0x1) +#define PORT_P0_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P4) | (((val) & 0x1) << 4)) +/* Port 0 Pin #Direction Control (3) */ +#define PORT_P0_DIR_P3 (0x1 << 3) +#define PORT_P0_DIR_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P0_DIR_P3_GET(val) ((((val) & PORT_P0_DIR_P3) >> 3) & 0x1) +#define PORT_P0_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P3) | (((val) & 0x1) << 3)) +/* Port 0 Pin #Direction Control (2) */ +#define PORT_P0_DIR_P2 (0x1 << 2) +#define PORT_P0_DIR_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P0_DIR_P2_GET(val) ((((val) & PORT_P0_DIR_P2) >> 2) & 0x1) +#define PORT_P0_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P2) | (((val) & 0x1) << 2)) +/* Port 0 Pin #Direction Control (1) */ +#define PORT_P0_DIR_P1 (0x1 << 1) +#define PORT_P0_DIR_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P0_DIR_P1_GET(val) ((((val) & PORT_P0_DIR_P1) >> 1) & 0x1) +#define PORT_P0_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P1) | (((val) & 0x1) << 1)) +/* Port 0 Pin #Direction Control (0) */ +#define PORT_P0_DIR_P0 (0x1) +#define PORT_P0_DIR_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P0_DIR_P0_GET(val) ((((val) & PORT_P0_DIR_P0) >> 0) & 0x1) +#define PORT_P0_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 0 Alternate Function Select Register 0 + ******************************************************************************/ + +/* Alternate Function at Port 0 Bit # (19) */ +#define PORT_P0_ALTSEL0_P19 (0x1 << 19) +#define PORT_P0_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P0_ALTSEL0_P19_GET(val) ((((val) & PORT_P0_ALTSEL0_P19) >> 19) & 0x1) +#define PORT_P0_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P19) | (((val) & 0x1) << 19)) +/* Alternate Function at Port 0 Bit # (18) */ +#define PORT_P0_ALTSEL0_P18 (0x1 << 18) +#define PORT_P0_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P0_ALTSEL0_P18_GET(val) ((((val) & PORT_P0_ALTSEL0_P18) >> 18) & 0x1) +#define PORT_P0_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P18) | (((val) & 0x1) << 18)) +/* Alternate Function at Port 0 Bit # (17) */ +#define PORT_P0_ALTSEL0_P17 (0x1 << 17) +#define PORT_P0_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P0_ALTSEL0_P17_GET(val) ((((val) & PORT_P0_ALTSEL0_P17) >> 17) & 0x1) +#define PORT_P0_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P17) | (((val) & 0x1) << 17)) +/* Alternate Function at Port 0 Bit # (16) */ +#define PORT_P0_ALTSEL0_P16 (0x1 << 16) +#define PORT_P0_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P0_ALTSEL0_P16_GET(val) ((((val) & PORT_P0_ALTSEL0_P16) >> 16) & 0x1) +#define PORT_P0_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P16) | (((val) & 0x1) << 16)) +/* Alternate Function at Port 0 Bit # (15) */ +#define PORT_P0_ALTSEL0_P15 (0x1 << 15) +#define PORT_P0_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P0_ALTSEL0_P15_GET(val) ((((val) & PORT_P0_ALTSEL0_P15) >> 15) & 0x1) +#define PORT_P0_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P15) | (((val) & 0x1) << 15)) +/* Alternate Function at Port 0 Bit # (14) */ +#define PORT_P0_ALTSEL0_P14 (0x1 << 14) +#define PORT_P0_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P0_ALTSEL0_P14_GET(val) ((((val) & PORT_P0_ALTSEL0_P14) >> 14) & 0x1) +#define PORT_P0_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P14) | (((val) & 0x1) << 14)) +/* Alternate Function at Port 0 Bit # (13) */ +#define PORT_P0_ALTSEL0_P13 (0x1 << 13) +#define PORT_P0_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_ALTSEL0_P13_GET(val) ((((val) & PORT_P0_ALTSEL0_P13) >> 13) & 0x1) +#define PORT_P0_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P13) | (((val) & 0x1) << 13)) +/* Alternate Function at Port 0 Bit # (12) */ +#define PORT_P0_ALTSEL0_P12 (0x1 << 12) +#define PORT_P0_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_ALTSEL0_P12_GET(val) ((((val) & PORT_P0_ALTSEL0_P12) >> 12) & 0x1) +#define PORT_P0_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P12) | (((val) & 0x1) << 12)) +/* Alternate Function at Port 0 Bit # (11) */ +#define PORT_P0_ALTSEL0_P11 (0x1 << 11) +#define PORT_P0_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_ALTSEL0_P11_GET(val) ((((val) & PORT_P0_ALTSEL0_P11) >> 11) & 0x1) +#define PORT_P0_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P11) | (((val) & 0x1) << 11)) +/* Alternate Function at Port 0 Bit # (10) */ +#define PORT_P0_ALTSEL0_P10 (0x1 << 10) +#define PORT_P0_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_ALTSEL0_P10_GET(val) ((((val) & PORT_P0_ALTSEL0_P10) >> 10) & 0x1) +#define PORT_P0_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P10) | (((val) & 0x1) << 10)) +/* Alternate Function at Port 0 Bit # (9) */ +#define PORT_P0_ALTSEL0_P9 (0x1 << 9) +#define PORT_P0_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_ALTSEL0_P9_GET(val) ((((val) & PORT_P0_ALTSEL0_P9) >> 9) & 0x1) +#define PORT_P0_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P9) | (((val) & 0x1) << 9)) +/* Alternate Function at Port 0 Bit # (8) */ +#define PORT_P0_ALTSEL0_P8 (0x1 << 8) +#define PORT_P0_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_ALTSEL0_P8_GET(val) ((((val) & PORT_P0_ALTSEL0_P8) >> 8) & 0x1) +#define PORT_P0_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P8) | (((val) & 0x1) << 8)) +/* Alternate Function at Port 0 Bit # (7) */ +#define PORT_P0_ALTSEL0_P7 (0x1 << 7) +#define PORT_P0_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_ALTSEL0_P7_GET(val) ((((val) & PORT_P0_ALTSEL0_P7) >> 7) & 0x1) +#define PORT_P0_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P7) | (((val) & 0x1) << 7)) +/* Alternate Function at Port 0 Bit # (6) */ +#define PORT_P0_ALTSEL0_P6 (0x1 << 6) +#define PORT_P0_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P0_ALTSEL0_P6_GET(val) ((((val) & PORT_P0_ALTSEL0_P6) >> 6) & 0x1) +#define PORT_P0_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P6) | (((val) & 0x1) << 6)) +/* Alternate Function at Port 0 Bit # (5) */ +#define PORT_P0_ALTSEL0_P5 (0x1 << 5) +#define PORT_P0_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P0_ALTSEL0_P5_GET(val) ((((val) & PORT_P0_ALTSEL0_P5) >> 5) & 0x1) +#define PORT_P0_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P5) | (((val) & 0x1) << 5)) +/* Alternate Function at Port 0 Bit # (4) */ +#define PORT_P0_ALTSEL0_P4 (0x1 << 4) +#define PORT_P0_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P0_ALTSEL0_P4_GET(val) ((((val) & PORT_P0_ALTSEL0_P4) >> 4) & 0x1) +#define PORT_P0_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P4) | (((val) & 0x1) << 4)) +/* Alternate Function at Port 0 Bit # (3) */ +#define PORT_P0_ALTSEL0_P3 (0x1 << 3) +#define PORT_P0_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P0_ALTSEL0_P3_GET(val) ((((val) & PORT_P0_ALTSEL0_P3) >> 3) & 0x1) +#define PORT_P0_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P3) | (((val) & 0x1) << 3)) +/* Alternate Function at Port 0 Bit # (2) */ +#define PORT_P0_ALTSEL0_P2 (0x1 << 2) +#define PORT_P0_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P0_ALTSEL0_P2_GET(val) ((((val) & PORT_P0_ALTSEL0_P2) >> 2) & 0x1) +#define PORT_P0_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P2) | (((val) & 0x1) << 2)) +/* Alternate Function at Port 0 Bit # (1) */ +#define PORT_P0_ALTSEL0_P1 (0x1 << 1) +#define PORT_P0_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P0_ALTSEL0_P1_GET(val) ((((val) & PORT_P0_ALTSEL0_P1) >> 1) & 0x1) +#define PORT_P0_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P1) | (((val) & 0x1) << 1)) +/* Alternate Function at Port 0 Bit # (0) */ +#define PORT_P0_ALTSEL0_P0 (0x1) +#define PORT_P0_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P0_ALTSEL0_P0_GET(val) ((((val) & PORT_P0_ALTSEL0_P0) >> 0) & 0x1) +#define PORT_P0_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 0 Alternate Function Select Register 1 + ******************************************************************************/ + +/* Alternate Function at Port 0 Bit # (13) */ +#define PORT_P0_ALTSEL1_P13 (0x1 << 13) +#define PORT_P0_ALTSEL1_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_ALTSEL1_P13_GET(val) ((((val) & PORT_P0_ALTSEL1_P13) >> 13) & 0x1) +#define PORT_P0_ALTSEL1_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P13) | (((val) & 0x1) << 13)) +/* Alternate Function at Port 0 Bit # (12) */ +#define PORT_P0_ALTSEL1_P12 (0x1 << 12) +#define PORT_P0_ALTSEL1_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_ALTSEL1_P12_GET(val) ((((val) & PORT_P0_ALTSEL1_P12) >> 12) & 0x1) +#define PORT_P0_ALTSEL1_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P12) | (((val) & 0x1) << 12)) +/* Alternate Function at Port 0 Bit # (11) */ +#define PORT_P0_ALTSEL1_P11 (0x1 << 11) +#define PORT_P0_ALTSEL1_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_ALTSEL1_P11_GET(val) ((((val) & PORT_P0_ALTSEL1_P11) >> 11) & 0x1) +#define PORT_P0_ALTSEL1_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P11) | (((val) & 0x1) << 11)) +/* Alternate Function at Port 0 Bit # (10) */ +#define PORT_P0_ALTSEL1_P10 (0x1 << 10) +#define PORT_P0_ALTSEL1_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_ALTSEL1_P10_GET(val) ((((val) & PORT_P0_ALTSEL1_P10) >> 10) & 0x1) +#define PORT_P0_ALTSEL1_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P10) | (((val) & 0x1) << 10)) +/* Alternate Function at Port 0 Bit # (9) */ +#define PORT_P0_ALTSEL1_P9 (0x1 << 9) +#define PORT_P0_ALTSEL1_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_ALTSEL1_P9_GET(val) ((((val) & PORT_P0_ALTSEL1_P9) >> 9) & 0x1) +#define PORT_P0_ALTSEL1_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P9) | (((val) & 0x1) << 9)) +/* Alternate Function at Port 0 Bit # (8) */ +#define PORT_P0_ALTSEL1_P8 (0x1 << 8) +#define PORT_P0_ALTSEL1_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_ALTSEL1_P8_GET(val) ((((val) & PORT_P0_ALTSEL1_P8) >> 8) & 0x1) +#define PORT_P0_ALTSEL1_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P8) | (((val) & 0x1) << 8)) +/* Alternate Function at Port 0 Bit # (7) */ +#define PORT_P0_ALTSEL1_P7 (0x1 << 7) +#define PORT_P0_ALTSEL1_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_ALTSEL1_P7_GET(val) ((((val) & PORT_P0_ALTSEL1_P7) >> 7) & 0x1) +#define PORT_P0_ALTSEL1_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P7) | (((val) & 0x1) << 7)) +/* Alternate Function at Port 0 Bit # (6) */ +#define PORT_P0_ALTSEL1_P6 (0x1 << 6) +#define PORT_P0_ALTSEL1_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P0_ALTSEL1_P6_GET(val) ((((val) & PORT_P0_ALTSEL1_P6) >> 6) & 0x1) +#define PORT_P0_ALTSEL1_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P6) | (((val) & 0x1) << 6)) +/* Alternate Function at Port 0 Bit # (3) */ +#define PORT_P0_ALTSEL1_P3 (0x1 << 3) +#define PORT_P0_ALTSEL1_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P0_ALTSEL1_P3_GET(val) ((((val) & PORT_P0_ALTSEL1_P3) >> 3) & 0x1) +#define PORT_P0_ALTSEL1_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P3) | (((val) & 0x1) << 3)) + +/******************************************************************************* + * Port 0 Pull Up Enable Register + ******************************************************************************/ + +/* Pull Up Device Enable at Port 0 Bit # (19) */ +#define PORT_P0_PUEN_P19 (0x1 << 19) +#define PORT_P0_PUEN_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P0_PUEN_P19_GET(val) ((((val) & PORT_P0_PUEN_P19) >> 19) & 0x1) +#define PORT_P0_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P19) | (((val) & 0x1) << 19)) +/* Pull Up Device Enable at Port 0 Bit # (18) */ +#define PORT_P0_PUEN_P18 (0x1 << 18) +#define PORT_P0_PUEN_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P0_PUEN_P18_GET(val) ((((val) & PORT_P0_PUEN_P18) >> 18) & 0x1) +#define PORT_P0_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P18) | (((val) & 0x1) << 18)) +/* Pull Up Device Enable at Port 0 Bit # (17) */ +#define PORT_P0_PUEN_P17 (0x1 << 17) +#define PORT_P0_PUEN_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P0_PUEN_P17_GET(val) ((((val) & PORT_P0_PUEN_P17) >> 17) & 0x1) +#define PORT_P0_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P17) | (((val) & 0x1) << 17)) +/* Pull Up Device Enable at Port 0 Bit # (16) */ +#define PORT_P0_PUEN_P16 (0x1 << 16) +#define PORT_P0_PUEN_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P0_PUEN_P16_GET(val) ((((val) & PORT_P0_PUEN_P16) >> 16) & 0x1) +#define PORT_P0_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P16) | (((val) & 0x1) << 16)) +/* Pull Up Device Enable at Port 0 Bit # (15) */ +#define PORT_P0_PUEN_P15 (0x1 << 15) +#define PORT_P0_PUEN_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P0_PUEN_P15_GET(val) ((((val) & PORT_P0_PUEN_P15) >> 15) & 0x1) +#define PORT_P0_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P15) | (((val) & 0x1) << 15)) +/* Pull Up Device Enable at Port 0 Bit # (14) */ +#define PORT_P0_PUEN_P14 (0x1 << 14) +#define PORT_P0_PUEN_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P0_PUEN_P14_GET(val) ((((val) & PORT_P0_PUEN_P14) >> 14) & 0x1) +#define PORT_P0_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P14) | (((val) & 0x1) << 14)) +/* Pull Up Device Enable at Port 0 Bit # (13) */ +#define PORT_P0_PUEN_P13 (0x1 << 13) +#define PORT_P0_PUEN_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_PUEN_P13_GET(val) ((((val) & PORT_P0_PUEN_P13) >> 13) & 0x1) +#define PORT_P0_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P13) | (((val) & 0x1) << 13)) +/* Pull Up Device Enable at Port 0 Bit # (12) */ +#define PORT_P0_PUEN_P12 (0x1 << 12) +#define PORT_P0_PUEN_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_PUEN_P12_GET(val) ((((val) & PORT_P0_PUEN_P12) >> 12) & 0x1) +#define PORT_P0_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P12) | (((val) & 0x1) << 12)) +/* Pull Up Device Enable at Port 0 Bit # (11) */ +#define PORT_P0_PUEN_P11 (0x1 << 11) +#define PORT_P0_PUEN_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_PUEN_P11_GET(val) ((((val) & PORT_P0_PUEN_P11) >> 11) & 0x1) +#define PORT_P0_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P11) | (((val) & 0x1) << 11)) +/* Pull Up Device Enable at Port 0 Bit # (10) */ +#define PORT_P0_PUEN_P10 (0x1 << 10) +#define PORT_P0_PUEN_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_PUEN_P10_GET(val) ((((val) & PORT_P0_PUEN_P10) >> 10) & 0x1) +#define PORT_P0_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P10) | (((val) & 0x1) << 10)) +/* Pull Up Device Enable at Port 0 Bit # (9) */ +#define PORT_P0_PUEN_P9 (0x1 << 9) +#define PORT_P0_PUEN_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_PUEN_P9_GET(val) ((((val) & PORT_P0_PUEN_P9) >> 9) & 0x1) +#define PORT_P0_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P9) | (((val) & 0x1) << 9)) +/* Pull Up Device Enable at Port 0 Bit # (8) */ +#define PORT_P0_PUEN_P8 (0x1 << 8) +#define PORT_P0_PUEN_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_PUEN_P8_GET(val) ((((val) & PORT_P0_PUEN_P8) >> 8) & 0x1) +#define PORT_P0_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P8) | (((val) & 0x1) << 8)) +/* Pull Up Device Enable at Port 0 Bit # (7) */ +#define PORT_P0_PUEN_P7 (0x1 << 7) +#define PORT_P0_PUEN_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_PUEN_P7_GET(val) ((((val) & PORT_P0_PUEN_P7) >> 7) & 0x1) +#define PORT_P0_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P7) | (((val) & 0x1) << 7)) +/* Pull Up Device Enable at Port 0 Bit # (6) */ +#define PORT_P0_PUEN_P6 (0x1 << 6) +#define PORT_P0_PUEN_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P0_PUEN_P6_GET(val) ((((val) & PORT_P0_PUEN_P6) >> 6) & 0x1) +#define PORT_P0_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P6) | (((val) & 0x1) << 6)) +/* Pull Up Device Enable at Port 0 Bit # (5) */ +#define PORT_P0_PUEN_P5 (0x1 << 5) +#define PORT_P0_PUEN_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P0_PUEN_P5_GET(val) ((((val) & PORT_P0_PUEN_P5) >> 5) & 0x1) +#define PORT_P0_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P5) | (((val) & 0x1) << 5)) +/* Pull Up Device Enable at Port 0 Bit # (4) */ +#define PORT_P0_PUEN_P4 (0x1 << 4) +#define PORT_P0_PUEN_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P0_PUEN_P4_GET(val) ((((val) & PORT_P0_PUEN_P4) >> 4) & 0x1) +#define PORT_P0_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P4) | (((val) & 0x1) << 4)) +/* Pull Up Device Enable at Port 0 Bit # (3) */ +#define PORT_P0_PUEN_P3 (0x1 << 3) +#define PORT_P0_PUEN_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P0_PUEN_P3_GET(val) ((((val) & PORT_P0_PUEN_P3) >> 3) & 0x1) +#define PORT_P0_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P3) | (((val) & 0x1) << 3)) +/* Pull Up Device Enable at Port 0 Bit # (2) */ +#define PORT_P0_PUEN_P2 (0x1 << 2) +#define PORT_P0_PUEN_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P0_PUEN_P2_GET(val) ((((val) & PORT_P0_PUEN_P2) >> 2) & 0x1) +#define PORT_P0_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P2) | (((val) & 0x1) << 2)) +/* Pull Up Device Enable at Port 0 Bit # (1) */ +#define PORT_P0_PUEN_P1 (0x1 << 1) +#define PORT_P0_PUEN_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P0_PUEN_P1_GET(val) ((((val) & PORT_P0_PUEN_P1) >> 1) & 0x1) +#define PORT_P0_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P1) | (((val) & 0x1) << 1)) +/* Pull Up Device Enable at Port 0 Bit # (0) */ +#define PORT_P0_PUEN_P0 (0x1) +#define PORT_P0_PUEN_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P0_PUEN_P0_GET(val) ((((val) & PORT_P0_PUEN_P0) >> 0) & 0x1) +#define PORT_P0_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * External Interrupt Control Register 0 + ******************************************************************************/ + +/* Type of Level or Edge Detection of EXINT16 (19) */ +#define PORT_P0_EXINTCR0_EXINT16 (0x1 << 19) +#define PORT_P0_EXINTCR0_EXINT16_VAL(val) (((val) & 0x1) << 19) +#define PORT_P0_EXINTCR0_EXINT16_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT16) >> 19) & 0x1) +#define PORT_P0_EXINTCR0_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT16) | (((val) & 0x1) << 19)) +/* Type of Level or Edge Detection of EXINT10 (17) */ +#define PORT_P0_EXINTCR0_EXINT10 (0x1 << 17) +#define PORT_P0_EXINTCR0_EXINT10_VAL(val) (((val) & 0x1) << 17) +#define PORT_P0_EXINTCR0_EXINT10_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT10) >> 17) & 0x1) +#define PORT_P0_EXINTCR0_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT10) | (((val) & 0x1) << 17)) +/* Type of Level or Edge Detection of EXINT9 (16) */ +#define PORT_P0_EXINTCR0_EXINT9 (0x1 << 16) +#define PORT_P0_EXINTCR0_EXINT9_VAL(val) (((val) & 0x1) << 16) +#define PORT_P0_EXINTCR0_EXINT9_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT9) >> 16) & 0x1) +#define PORT_P0_EXINTCR0_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT9) | (((val) & 0x1) << 16)) +/* Type of Level or Edge Detection of EXINT8 (15) */ +#define PORT_P0_EXINTCR0_EXINT8 (0x1 << 15) +#define PORT_P0_EXINTCR0_EXINT8_VAL(val) (((val) & 0x1) << 15) +#define PORT_P0_EXINTCR0_EXINT8_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT8) >> 15) & 0x1) +#define PORT_P0_EXINTCR0_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT8) | (((val) & 0x1) << 15)) +/* Type of Level or Edge Detection of EXINT7 (14) */ +#define PORT_P0_EXINTCR0_EXINT7 (0x1 << 14) +#define PORT_P0_EXINTCR0_EXINT7_VAL(val) (((val) & 0x1) << 14) +#define PORT_P0_EXINTCR0_EXINT7_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT7) >> 14) & 0x1) +#define PORT_P0_EXINTCR0_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT7) | (((val) & 0x1) << 14)) +/* Type of Level or Edge Detection of EXINT6 (13) */ +#define PORT_P0_EXINTCR0_EXINT6 (0x1 << 13) +#define PORT_P0_EXINTCR0_EXINT6_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_EXINTCR0_EXINT6_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT6) >> 13) & 0x1) +#define PORT_P0_EXINTCR0_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT6) | (((val) & 0x1) << 13)) +/* Type of Level or Edge Detection of EXINT5 (12) */ +#define PORT_P0_EXINTCR0_EXINT5 (0x1 << 12) +#define PORT_P0_EXINTCR0_EXINT5_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_EXINTCR0_EXINT5_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT5) >> 12) & 0x1) +#define PORT_P0_EXINTCR0_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT5) | (((val) & 0x1) << 12)) +/* Type of Level or Edge Detection of EXINT4 (11) */ +#define PORT_P0_EXINTCR0_EXINT4 (0x1 << 11) +#define PORT_P0_EXINTCR0_EXINT4_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_EXINTCR0_EXINT4_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT4) >> 11) & 0x1) +#define PORT_P0_EXINTCR0_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT4) | (((val) & 0x1) << 11)) +/* Type of Level or Edge Detection of EXINT3 (10) */ +#define PORT_P0_EXINTCR0_EXINT3 (0x1 << 10) +#define PORT_P0_EXINTCR0_EXINT3_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_EXINTCR0_EXINT3_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT3) >> 10) & 0x1) +#define PORT_P0_EXINTCR0_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT3) | (((val) & 0x1) << 10)) +/* Type of Level or Edge Detection of EXINT2 (9) */ +#define PORT_P0_EXINTCR0_EXINT2 (0x1 << 9) +#define PORT_P0_EXINTCR0_EXINT2_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_EXINTCR0_EXINT2_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT2) >> 9) & 0x1) +#define PORT_P0_EXINTCR0_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT2) | (((val) & 0x1) << 9)) +/* Type of Level or Edge Detection of EXINT1 (8) */ +#define PORT_P0_EXINTCR0_EXINT1 (0x1 << 8) +#define PORT_P0_EXINTCR0_EXINT1_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_EXINTCR0_EXINT1_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT1) >> 8) & 0x1) +#define PORT_P0_EXINTCR0_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT1) | (((val) & 0x1) << 8)) +/* Type of Level or Edge Detection of EXINT0 (7) */ +#define PORT_P0_EXINTCR0_EXINT0 (0x1 << 7) +#define PORT_P0_EXINTCR0_EXINT0_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_EXINTCR0_EXINT0_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT0) >> 7) & 0x1) +#define PORT_P0_EXINTCR0_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT0) | (((val) & 0x1) << 7)) + +/******************************************************************************* + * External Interrupt Control Register 1 + ******************************************************************************/ + +/* Type of Level or Edge Detection of EXINT16 (19) */ +#define PORT_P0_EXINTCR1_EXINT16 (0x1 << 19) +#define PORT_P0_EXINTCR1_EXINT16_VAL(val) (((val) & 0x1) << 19) +#define PORT_P0_EXINTCR1_EXINT16_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT16) >> 19) & 0x1) +#define PORT_P0_EXINTCR1_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT16) | (((val) & 0x1) << 19)) +/* Type of Level or Edge Detection of EXINT10 (17) */ +#define PORT_P0_EXINTCR1_EXINT10 (0x1 << 17) +#define PORT_P0_EXINTCR1_EXINT10_VAL(val) (((val) & 0x1) << 17) +#define PORT_P0_EXINTCR1_EXINT10_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT10) >> 17) & 0x1) +#define PORT_P0_EXINTCR1_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT10) | (((val) & 0x1) << 17)) +/* Type of Level or Edge Detection of EXINT9 (16) */ +#define PORT_P0_EXINTCR1_EXINT9 (0x1 << 16) +#define PORT_P0_EXINTCR1_EXINT9_VAL(val) (((val) & 0x1) << 16) +#define PORT_P0_EXINTCR1_EXINT9_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT9) >> 16) & 0x1) +#define PORT_P0_EXINTCR1_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT9) | (((val) & 0x1) << 16)) +/* Type of Level or Edge Detection of EXINT8 (15) */ +#define PORT_P0_EXINTCR1_EXINT8 (0x1 << 15) +#define PORT_P0_EXINTCR1_EXINT8_VAL(val) (((val) & 0x1) << 15) +#define PORT_P0_EXINTCR1_EXINT8_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT8) >> 15) & 0x1) +#define PORT_P0_EXINTCR1_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT8) | (((val) & 0x1) << 15)) +/* Type of Level or Edge Detection of EXINT7 (14) */ +#define PORT_P0_EXINTCR1_EXINT7 (0x1 << 14) +#define PORT_P0_EXINTCR1_EXINT7_VAL(val) (((val) & 0x1) << 14) +#define PORT_P0_EXINTCR1_EXINT7_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT7) >> 14) & 0x1) +#define PORT_P0_EXINTCR1_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT7) | (((val) & 0x1) << 14)) +/* Type of Level or Edge Detection of EXINT6 (13) */ +#define PORT_P0_EXINTCR1_EXINT6 (0x1 << 13) +#define PORT_P0_EXINTCR1_EXINT6_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_EXINTCR1_EXINT6_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT6) >> 13) & 0x1) +#define PORT_P0_EXINTCR1_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT6) | (((val) & 0x1) << 13)) +/* Type of Level or Edge Detection of EXINT5 (12) */ +#define PORT_P0_EXINTCR1_EXINT5 (0x1 << 12) +#define PORT_P0_EXINTCR1_EXINT5_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_EXINTCR1_EXINT5_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT5) >> 12) & 0x1) +#define PORT_P0_EXINTCR1_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT5) | (((val) & 0x1) << 12)) +/* Type of Level or Edge Detection of EXINT4 (11) */ +#define PORT_P0_EXINTCR1_EXINT4 (0x1 << 11) +#define PORT_P0_EXINTCR1_EXINT4_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_EXINTCR1_EXINT4_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT4) >> 11) & 0x1) +#define PORT_P0_EXINTCR1_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT4) | (((val) & 0x1) << 11)) +/* Type of Level or Edge Detection of EXINT3 (10) */ +#define PORT_P0_EXINTCR1_EXINT3 (0x1 << 10) +#define PORT_P0_EXINTCR1_EXINT3_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_EXINTCR1_EXINT3_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT3) >> 10) & 0x1) +#define PORT_P0_EXINTCR1_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT3) | (((val) & 0x1) << 10)) +/* Type of Level or Edge Detection of EXINT2 (9) */ +#define PORT_P0_EXINTCR1_EXINT2 (0x1 << 9) +#define PORT_P0_EXINTCR1_EXINT2_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_EXINTCR1_EXINT2_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT2) >> 9) & 0x1) +#define PORT_P0_EXINTCR1_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT2) | (((val) & 0x1) << 9)) +/* Type of Level or Edge Detection of EXINT1 (8) */ +#define PORT_P0_EXINTCR1_EXINT1 (0x1 << 8) +#define PORT_P0_EXINTCR1_EXINT1_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_EXINTCR1_EXINT1_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT1) >> 8) & 0x1) +#define PORT_P0_EXINTCR1_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT1) | (((val) & 0x1) << 8)) +/* Type of Level or Edge Detection of EXINT0 (7) */ +#define PORT_P0_EXINTCR1_EXINT0 (0x1 << 7) +#define PORT_P0_EXINTCR1_EXINT0_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_EXINTCR1_EXINT0_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT0) >> 7) & 0x1) +#define PORT_P0_EXINTCR1_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT0) | (((val) & 0x1) << 7)) + +/******************************************************************************* + * P0_IRNEN Register + ******************************************************************************/ + +/* EXINT16 Interrupt Request Enable (19) */ +#define PORT_P0_IRNEN_EXINT16 (0x1 << 19) +#define PORT_P0_IRNEN_EXINT16_VAL(val) (((val) & 0x1) << 19) +#define PORT_P0_IRNEN_EXINT16_GET(val) ((((val) & PORT_P0_IRNEN_EXINT16) >> 19) & 0x1) +#define PORT_P0_IRNEN_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT16) | (((val) & 0x1) << 19)) +/* EXINT10 Interrupt Request Enable (17) */ +#define PORT_P0_IRNEN_EXINT10 (0x1 << 17) +#define PORT_P0_IRNEN_EXINT10_VAL(val) (((val) & 0x1) << 17) +#define PORT_P0_IRNEN_EXINT10_GET(val) ((((val) & PORT_P0_IRNEN_EXINT10) >> 17) & 0x1) +#define PORT_P0_IRNEN_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT10) | (((val) & 0x1) << 17)) +/* EXINT9 Interrupt Request Enable (16) */ +#define PORT_P0_IRNEN_EXINT9 (0x1 << 16) +#define PORT_P0_IRNEN_EXINT9_VAL(val) (((val) & 0x1) << 16) +#define PORT_P0_IRNEN_EXINT9_GET(val) ((((val) & PORT_P0_IRNEN_EXINT9) >> 16) & 0x1) +#define PORT_P0_IRNEN_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT9) | (((val) & 0x1) << 16)) +/* EXINT8 Interrupt Request Enable (15) */ +#define PORT_P0_IRNEN_EXINT8 (0x1 << 15) +#define PORT_P0_IRNEN_EXINT8_VAL(val) (((val) & 0x1) << 15) +#define PORT_P0_IRNEN_EXINT8_GET(val) ((((val) & PORT_P0_IRNEN_EXINT8) >> 15) & 0x1) +#define PORT_P0_IRNEN_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT8) | (((val) & 0x1) << 15)) +/* EXINT7 Interrupt Request Enable (14) */ +#define PORT_P0_IRNEN_EXINT7 (0x1 << 14) +#define PORT_P0_IRNEN_EXINT7_VAL(val) (((val) & 0x1) << 14) +#define PORT_P0_IRNEN_EXINT7_GET(val) ((((val) & PORT_P0_IRNEN_EXINT7) >> 14) & 0x1) +#define PORT_P0_IRNEN_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT7) | (((val) & 0x1) << 14)) +/* EXINT6 Interrupt Request Enable (13) */ +#define PORT_P0_IRNEN_EXINT6 (0x1 << 13) +#define PORT_P0_IRNEN_EXINT6_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_IRNEN_EXINT6_GET(val) ((((val) & PORT_P0_IRNEN_EXINT6) >> 13) & 0x1) +#define PORT_P0_IRNEN_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT6) | (((val) & 0x1) << 13)) +/* EXINT5 Interrupt Request Enable (12) */ +#define PORT_P0_IRNEN_EXINT5 (0x1 << 12) +#define PORT_P0_IRNEN_EXINT5_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_IRNEN_EXINT5_GET(val) ((((val) & PORT_P0_IRNEN_EXINT5) >> 12) & 0x1) +#define PORT_P0_IRNEN_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT5) | (((val) & 0x1) << 12)) +/* EXINT4 Interrupt Request Enable (11) */ +#define PORT_P0_IRNEN_EXINT4 (0x1 << 11) +#define PORT_P0_IRNEN_EXINT4_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_IRNEN_EXINT4_GET(val) ((((val) & PORT_P0_IRNEN_EXINT4) >> 11) & 0x1) +#define PORT_P0_IRNEN_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT4) | (((val) & 0x1) << 11)) +/* EXINT3 Interrupt Request Enable (10) */ +#define PORT_P0_IRNEN_EXINT3 (0x1 << 10) +#define PORT_P0_IRNEN_EXINT3_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_IRNEN_EXINT3_GET(val) ((((val) & PORT_P0_IRNEN_EXINT3) >> 10) & 0x1) +#define PORT_P0_IRNEN_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT3) | (((val) & 0x1) << 10)) +/* EXINT2 Interrupt Request Enable (9) */ +#define PORT_P0_IRNEN_EXINT2 (0x1 << 9) +#define PORT_P0_IRNEN_EXINT2_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_IRNEN_EXINT2_GET(val) ((((val) & PORT_P0_IRNEN_EXINT2) >> 9) & 0x1) +#define PORT_P0_IRNEN_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT2) | (((val) & 0x1) << 9)) +/* EXINT1 Interrupt Request Enable (8) */ +#define PORT_P0_IRNEN_EXINT1 (0x1 << 8) +#define PORT_P0_IRNEN_EXINT1_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_IRNEN_EXINT1_GET(val) ((((val) & PORT_P0_IRNEN_EXINT1) >> 8) & 0x1) +#define PORT_P0_IRNEN_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT1) | (((val) & 0x1) << 8)) +/* EXINT0 Interrupt Request Enable (7) */ +#define PORT_P0_IRNEN_EXINT0 (0x1 << 7) +#define PORT_P0_IRNEN_EXINT0_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_IRNEN_EXINT0_GET(val) ((((val) & PORT_P0_IRNEN_EXINT0) >> 7) & 0x1) +#define PORT_P0_IRNEN_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT0) | (((val) & 0x1) << 7)) + +/******************************************************************************* + * P0_IRNICR Register + ******************************************************************************/ + +/* EXINT16 Interrupt Request (19) */ +#define PORT_P0_IRNICR_EXINT16 (0x1 << 19) +#define PORT_P0_IRNICR_EXINT16_GET(val) ((((val) & PORT_P0_IRNICR_EXINT16) >> 19) & 0x1) +/* EXINT10 Interrupt Request (17) */ +#define PORT_P0_IRNICR_EXINT10 (0x1 << 17) +#define PORT_P0_IRNICR_EXINT10_GET(val) ((((val) & PORT_P0_IRNICR_EXINT10) >> 17) & 0x1) +/* EXINT9 Interrupt Request (16) */ +#define PORT_P0_IRNICR_EXINT9 (0x1 << 16) +#define PORT_P0_IRNICR_EXINT9_GET(val) ((((val) & PORT_P0_IRNICR_EXINT9) >> 16) & 0x1) +/* EXINT8 Interrupt Request (15) */ +#define PORT_P0_IRNICR_EXINT8 (0x1 << 15) +#define PORT_P0_IRNICR_EXINT8_GET(val) ((((val) & PORT_P0_IRNICR_EXINT8) >> 15) & 0x1) +/* EXINT7 Interrupt Request (14) */ +#define PORT_P0_IRNICR_EXINT7 (0x1 << 14) +#define PORT_P0_IRNICR_EXINT7_GET(val) ((((val) & PORT_P0_IRNICR_EXINT7) >> 14) & 0x1) +/* EXINT6 Interrupt Request (13) */ +#define PORT_P0_IRNICR_EXINT6 (0x1 << 13) +#define PORT_P0_IRNICR_EXINT6_GET(val) ((((val) & PORT_P0_IRNICR_EXINT6) >> 13) & 0x1) +/* EXINT5 Interrupt Request (12) */ +#define PORT_P0_IRNICR_EXINT5 (0x1 << 12) +#define PORT_P0_IRNICR_EXINT5_GET(val) ((((val) & PORT_P0_IRNICR_EXINT5) >> 12) & 0x1) +/* EXINT4 Interrupt Request (11) */ +#define PORT_P0_IRNICR_EXINT4 (0x1 << 11) +#define PORT_P0_IRNICR_EXINT4_GET(val) ((((val) & PORT_P0_IRNICR_EXINT4) >> 11) & 0x1) +/* EXINT3 Interrupt Request (10) */ +#define PORT_P0_IRNICR_EXINT3 (0x1 << 10) +#define PORT_P0_IRNICR_EXINT3_GET(val) ((((val) & PORT_P0_IRNICR_EXINT3) >> 10) & 0x1) +/* EXINT2 Interrupt Request (9) */ +#define PORT_P0_IRNICR_EXINT2 (0x1 << 9) +#define PORT_P0_IRNICR_EXINT2_GET(val) ((((val) & PORT_P0_IRNICR_EXINT2) >> 9) & 0x1) +/* EXINT1 Interrupt Request (8) */ +#define PORT_P0_IRNICR_EXINT1 (0x1 << 8) +#define PORT_P0_IRNICR_EXINT1_GET(val) ((((val) & PORT_P0_IRNICR_EXINT1) >> 8) & 0x1) +/* EXINT0 Interrupt Request (7) */ +#define PORT_P0_IRNICR_EXINT0 (0x1 << 7) +#define PORT_P0_IRNICR_EXINT0_GET(val) ((((val) & PORT_P0_IRNICR_EXINT0) >> 7) & 0x1) + +/******************************************************************************* + * P0_IRNCR Register + ******************************************************************************/ + +/* EXINT16 Interrupt Request (19) */ +#define PORT_P0_IRNCR_EXINT16 (0x1 << 19) +#define PORT_P0_IRNCR_EXINT16_GET(val) ((((val) & PORT_P0_IRNCR_EXINT16) >> 19) & 0x1) +/* EXINT10 Interrupt Request (17) */ +#define PORT_P0_IRNCR_EXINT10 (0x1 << 17) +#define PORT_P0_IRNCR_EXINT10_GET(val) ((((val) & PORT_P0_IRNCR_EXINT10) >> 17) & 0x1) +/* EXINT9 Interrupt Request (16) */ +#define PORT_P0_IRNCR_EXINT9 (0x1 << 16) +#define PORT_P0_IRNCR_EXINT9_GET(val) ((((val) & PORT_P0_IRNCR_EXINT9) >> 16) & 0x1) +/* EXINT8 Interrupt Request (15) */ +#define PORT_P0_IRNCR_EXINT8 (0x1 << 15) +#define PORT_P0_IRNCR_EXINT8_GET(val) ((((val) & PORT_P0_IRNCR_EXINT8) >> 15) & 0x1) +/* EXINT7 Interrupt Request (14) */ +#define PORT_P0_IRNCR_EXINT7 (0x1 << 14) +#define PORT_P0_IRNCR_EXINT7_GET(val) ((((val) & PORT_P0_IRNCR_EXINT7) >> 14) & 0x1) +/* EXINT6 Interrupt Request (13) */ +#define PORT_P0_IRNCR_EXINT6 (0x1 << 13) +#define PORT_P0_IRNCR_EXINT6_GET(val) ((((val) & PORT_P0_IRNCR_EXINT6) >> 13) & 0x1) +/* EXINT5 Interrupt Request (12) */ +#define PORT_P0_IRNCR_EXINT5 (0x1 << 12) +#define PORT_P0_IRNCR_EXINT5_GET(val) ((((val) & PORT_P0_IRNCR_EXINT5) >> 12) & 0x1) +/* EXINT4 Interrupt Request (11) */ +#define PORT_P0_IRNCR_EXINT4 (0x1 << 11) +#define PORT_P0_IRNCR_EXINT4_GET(val) ((((val) & PORT_P0_IRNCR_EXINT4) >> 11) & 0x1) +/* EXINT3 Interrupt Request (10) */ +#define PORT_P0_IRNCR_EXINT3 (0x1 << 10) +#define PORT_P0_IRNCR_EXINT3_GET(val) ((((val) & PORT_P0_IRNCR_EXINT3) >> 10) & 0x1) +/* EXINT2 Interrupt Request (9) */ +#define PORT_P0_IRNCR_EXINT2 (0x1 << 9) +#define PORT_P0_IRNCR_EXINT2_GET(val) ((((val) & PORT_P0_IRNCR_EXINT2) >> 9) & 0x1) +/* EXINT1 Interrupt Request (8) */ +#define PORT_P0_IRNCR_EXINT1 (0x1 << 8) +#define PORT_P0_IRNCR_EXINT1_GET(val) ((((val) & PORT_P0_IRNCR_EXINT1) >> 8) & 0x1) +/* EXINT0 Interrupt Request (7) */ +#define PORT_P0_IRNCR_EXINT0 (0x1 << 7) +#define PORT_P0_IRNCR_EXINT0_GET(val) ((((val) & PORT_P0_IRNCR_EXINT0) >> 7) & 0x1) + +/******************************************************************************* + * P0 External Event Detection Configuration Register + ******************************************************************************/ + +/* EXINT16 configured for Edge or Level Detection (19) */ +#define PORT_P0_IRNCFG_EXINT16 (0x1 << 19) +#define PORT_P0_IRNCFG_EXINT16_VAL(val) (((val) & 0x1) << 19) +#define PORT_P0_IRNCFG_EXINT16_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT16) >> 19) & 0x1) +#define PORT_P0_IRNCFG_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT16) | (((val) & 0x1) << 19)) +/* EXINT10 configured for Edge or Level Detection (17) */ +#define PORT_P0_IRNCFG_EXINT10 (0x1 << 17) +#define PORT_P0_IRNCFG_EXINT10_VAL(val) (((val) & 0x1) << 17) +#define PORT_P0_IRNCFG_EXINT10_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT10) >> 17) & 0x1) +#define PORT_P0_IRNCFG_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT10) | (((val) & 0x1) << 17)) +/* EXINT9 configured for Edge or Level Detection (16) */ +#define PORT_P0_IRNCFG_EXINT9 (0x1 << 16) +#define PORT_P0_IRNCFG_EXINT9_VAL(val) (((val) & 0x1) << 16) +#define PORT_P0_IRNCFG_EXINT9_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT9) >> 16) & 0x1) +#define PORT_P0_IRNCFG_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT9) | (((val) & 0x1) << 16)) +/* EXINT8 configured for Edge or Level Detection (15) */ +#define PORT_P0_IRNCFG_EXINT8 (0x1 << 15) +#define PORT_P0_IRNCFG_EXINT8_VAL(val) (((val) & 0x1) << 15) +#define PORT_P0_IRNCFG_EXINT8_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT8) >> 15) & 0x1) +#define PORT_P0_IRNCFG_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT8) | (((val) & 0x1) << 15)) +/* EXINT7 configured for Edge or Level Detection (14) */ +#define PORT_P0_IRNCFG_EXINT7 (0x1 << 14) +#define PORT_P0_IRNCFG_EXINT7_VAL(val) (((val) & 0x1) << 14) +#define PORT_P0_IRNCFG_EXINT7_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT7) >> 14) & 0x1) +#define PORT_P0_IRNCFG_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT7) | (((val) & 0x1) << 14)) +/* EXINT6 configured for Edge or Level Detection (13) */ +#define PORT_P0_IRNCFG_EXINT6 (0x1 << 13) +#define PORT_P0_IRNCFG_EXINT6_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_IRNCFG_EXINT6_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT6) >> 13) & 0x1) +#define PORT_P0_IRNCFG_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT6) | (((val) & 0x1) << 13)) +/* EXINT5 configured for Edge or Level Detection (12) */ +#define PORT_P0_IRNCFG_EXINT5 (0x1 << 12) +#define PORT_P0_IRNCFG_EXINT5_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_IRNCFG_EXINT5_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT5) >> 12) & 0x1) +#define PORT_P0_IRNCFG_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT5) | (((val) & 0x1) << 12)) +/* EXINT4 configured for Edge or Level Detection (11) */ +#define PORT_P0_IRNCFG_EXINT4 (0x1 << 11) +#define PORT_P0_IRNCFG_EXINT4_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_IRNCFG_EXINT4_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT4) >> 11) & 0x1) +#define PORT_P0_IRNCFG_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT4) | (((val) & 0x1) << 11)) +/* EXINT3 configured for Edge or Level Detection (10) */ +#define PORT_P0_IRNCFG_EXINT3 (0x1 << 10) +#define PORT_P0_IRNCFG_EXINT3_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_IRNCFG_EXINT3_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT3) >> 10) & 0x1) +#define PORT_P0_IRNCFG_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT3) | (((val) & 0x1) << 10)) +/* EXINT2 configured for Edge or Level Detection (9) */ +#define PORT_P0_IRNCFG_EXINT2 (0x1 << 9) +#define PORT_P0_IRNCFG_EXINT2_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_IRNCFG_EXINT2_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT2) >> 9) & 0x1) +#define PORT_P0_IRNCFG_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT2) | (((val) & 0x1) << 9)) +/* EXINT1 configured for Edge or Level Detection (8) */ +#define PORT_P0_IRNCFG_EXINT1 (0x1 << 8) +#define PORT_P0_IRNCFG_EXINT1_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_IRNCFG_EXINT1_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT1) >> 8) & 0x1) +#define PORT_P0_IRNCFG_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT1) | (((val) & 0x1) << 8)) +/* EXINT0 configured for Edge or Level Detection (7) */ +#define PORT_P0_IRNCFG_EXINT0 (0x1 << 7) +#define PORT_P0_IRNCFG_EXINT0_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_IRNCFG_EXINT0_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT0) >> 7) & 0x1) +#define PORT_P0_IRNCFG_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT0) | (((val) & 0x1) << 7)) + +/******************************************************************************* + * P0_IRNENSET Register + ******************************************************************************/ + +/* Set Interrupt Node Enable Flag EXINT16 (19) */ +#define PORT_P0_IRNENSET_EXINT16 (0x1 << 19) +#define PORT_P0_IRNENSET_EXINT16_VAL(val) (((val) & 0x1) << 19) +#define PORT_P0_IRNENSET_EXINT16_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT16) | (val) & 1) << 19) +/* Set Interrupt Node Enable Flag EXINT10 (17) */ +#define PORT_P0_IRNENSET_EXINT10 (0x1 << 17) +#define PORT_P0_IRNENSET_EXINT10_VAL(val) (((val) & 0x1) << 17) +#define PORT_P0_IRNENSET_EXINT10_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT10) | (val) & 1) << 17) +/* Set Interrupt Node Enable Flag EXINT9 (16) */ +#define PORT_P0_IRNENSET_EXINT9 (0x1 << 16) +#define PORT_P0_IRNENSET_EXINT9_VAL(val) (((val) & 0x1) << 16) +#define PORT_P0_IRNENSET_EXINT9_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT9) | (val) & 1) << 16) +/* Set Interrupt Node Enable Flag EXINT8 (15) */ +#define PORT_P0_IRNENSET_EXINT8 (0x1 << 15) +#define PORT_P0_IRNENSET_EXINT8_VAL(val) (((val) & 0x1) << 15) +#define PORT_P0_IRNENSET_EXINT8_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT8) | (val) & 1) << 15) +/* Set Interrupt Node Enable Flag EXINT7 (14) */ +#define PORT_P0_IRNENSET_EXINT7 (0x1 << 14) +#define PORT_P0_IRNENSET_EXINT7_VAL(val) (((val) & 0x1) << 14) +#define PORT_P0_IRNENSET_EXINT7_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT7) | (val) & 1) << 14) +/* Set Interrupt Node Enable Flag EXINT6 (13) */ +#define PORT_P0_IRNENSET_EXINT6 (0x1 << 13) +#define PORT_P0_IRNENSET_EXINT6_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_IRNENSET_EXINT6_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT6) | (val) & 1) << 13) +/* Set Interrupt Node Enable Flag EXINT5 (12) */ +#define PORT_P0_IRNENSET_EXINT5 (0x1 << 12) +#define PORT_P0_IRNENSET_EXINT5_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_IRNENSET_EXINT5_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT5) | (val) & 1) << 12) +/* Set Interrupt Node Enable Flag EXINT4 (11) */ +#define PORT_P0_IRNENSET_EXINT4 (0x1 << 11) +#define PORT_P0_IRNENSET_EXINT4_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_IRNENSET_EXINT4_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT4) | (val) & 1) << 11) +/* Set Interrupt Node Enable Flag EXINT3 (10) */ +#define PORT_P0_IRNENSET_EXINT3 (0x1 << 10) +#define PORT_P0_IRNENSET_EXINT3_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_IRNENSET_EXINT3_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT3) | (val) & 1) << 10) +/* Set Interrupt Node Enable Flag EXINT2 (9) */ +#define PORT_P0_IRNENSET_EXINT2 (0x1 << 9) +#define PORT_P0_IRNENSET_EXINT2_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_IRNENSET_EXINT2_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT2) | (val) & 1) << 9) +/* Set Interrupt Node Enable Flag EXINT1 (8) */ +#define PORT_P0_IRNENSET_EXINT1 (0x1 << 8) +#define PORT_P0_IRNENSET_EXINT1_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_IRNENSET_EXINT1_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT1) | (val) & 1) << 8) +/* Set Interrupt Node Enable Flag EXINT0 (7) */ +#define PORT_P0_IRNENSET_EXINT0 (0x1 << 7) +#define PORT_P0_IRNENSET_EXINT0_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_IRNENSET_EXINT0_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT0) | (val) & 1) << 7) + +/******************************************************************************* + * P0_IRNENCLR Register + ******************************************************************************/ + +/* Clear Interrupt Node Enable Flag EXINT16 (19) */ +#define PORT_P0_IRNENCLR_EXINT16 (0x1 << 19) +#define PORT_P0_IRNENCLR_EXINT16_VAL(val) (((val) & 0x1) << 19) +#define PORT_P0_IRNENCLR_EXINT16_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT16) | (val) & 1) << 19) +/* Clear Interrupt Node Enable Flag EXINT10 (17) */ +#define PORT_P0_IRNENCLR_EXINT10 (0x1 << 17) +#define PORT_P0_IRNENCLR_EXINT10_VAL(val) (((val) & 0x1) << 17) +#define PORT_P0_IRNENCLR_EXINT10_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT10) | (val) & 1) << 17) +/* Clear Interrupt Node Enable Flag EXINT9 (16) */ +#define PORT_P0_IRNENCLR_EXINT9 (0x1 << 16) +#define PORT_P0_IRNENCLR_EXINT9_VAL(val) (((val) & 0x1) << 16) +#define PORT_P0_IRNENCLR_EXINT9_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT9) | (val) & 1) << 16) +/* Clear Interrupt Node Enable Flag EXINT8 (15) */ +#define PORT_P0_IRNENCLR_EXINT8 (0x1 << 15) +#define PORT_P0_IRNENCLR_EXINT8_VAL(val) (((val) & 0x1) << 15) +#define PORT_P0_IRNENCLR_EXINT8_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT8) | (val) & 1) << 15) +/* Clear Interrupt Node Enable Flag EXINT7 (14) */ +#define PORT_P0_IRNENCLR_EXINT7 (0x1 << 14) +#define PORT_P0_IRNENCLR_EXINT7_VAL(val) (((val) & 0x1) << 14) +#define PORT_P0_IRNENCLR_EXINT7_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT7) | (val) & 1) << 14) +/* Clear Interrupt Node Enable Flag EXINT6 (13) */ +#define PORT_P0_IRNENCLR_EXINT6 (0x1 << 13) +#define PORT_P0_IRNENCLR_EXINT6_VAL(val) (((val) & 0x1) << 13) +#define PORT_P0_IRNENCLR_EXINT6_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT6) | (val) & 1) << 13) +/* Clear Interrupt Node Enable Flag EXINT5 (12) */ +#define PORT_P0_IRNENCLR_EXINT5 (0x1 << 12) +#define PORT_P0_IRNENCLR_EXINT5_VAL(val) (((val) & 0x1) << 12) +#define PORT_P0_IRNENCLR_EXINT5_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT5) | (val) & 1) << 12) +/* Clear Interrupt Node Enable Flag EXINT4 (11) */ +#define PORT_P0_IRNENCLR_EXINT4 (0x1 << 11) +#define PORT_P0_IRNENCLR_EXINT4_VAL(val) (((val) & 0x1) << 11) +#define PORT_P0_IRNENCLR_EXINT4_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT4) | (val) & 1) << 11) +/* Clear Interrupt Node Enable Flag EXINT3 (10) */ +#define PORT_P0_IRNENCLR_EXINT3 (0x1 << 10) +#define PORT_P0_IRNENCLR_EXINT3_VAL(val) (((val) & 0x1) << 10) +#define PORT_P0_IRNENCLR_EXINT3_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT3) | (val) & 1) << 10) +/* Clear Interrupt Node Enable Flag EXINT2 (9) */ +#define PORT_P0_IRNENCLR_EXINT2 (0x1 << 9) +#define PORT_P0_IRNENCLR_EXINT2_VAL(val) (((val) & 0x1) << 9) +#define PORT_P0_IRNENCLR_EXINT2_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT2) | (val) & 1) << 9) +/* Clear Interrupt Node Enable Flag EXINT1 (8) */ +#define PORT_P0_IRNENCLR_EXINT1 (0x1 << 8) +#define PORT_P0_IRNENCLR_EXINT1_VAL(val) (((val) & 0x1) << 8) +#define PORT_P0_IRNENCLR_EXINT1_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT1) | (val) & 1) << 8) +/* Clear Interrupt Node Enable Flag EXINT0 (7) */ +#define PORT_P0_IRNENCLR_EXINT0 (0x1 << 7) +#define PORT_P0_IRNENCLR_EXINT0_VAL(val) (((val) & 0x1) << 7) +#define PORT_P0_IRNENCLR_EXINT0_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT0) | (val) & 1) << 7) + +/******************************************************************************* + * Port 1 Data Output Register + ******************************************************************************/ + +/* Port 1 Pin # Output Value (19) */ +#define PORT_P1_OUT_P19 (0x1 << 19) +#define PORT_P1_OUT_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P1_OUT_P19_GET(val) ((((val) & PORT_P1_OUT_P19) >> 19) & 0x1) +#define PORT_P1_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P19) | (((val) & 0x1) << 19)) +/* Port 1 Pin # Output Value (18) */ +#define PORT_P1_OUT_P18 (0x1 << 18) +#define PORT_P1_OUT_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P1_OUT_P18_GET(val) ((((val) & PORT_P1_OUT_P18) >> 18) & 0x1) +#define PORT_P1_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P18) | (((val) & 0x1) << 18)) +/* Port 1 Pin # Output Value (17) */ +#define PORT_P1_OUT_P17 (0x1 << 17) +#define PORT_P1_OUT_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P1_OUT_P17_GET(val) ((((val) & PORT_P1_OUT_P17) >> 17) & 0x1) +#define PORT_P1_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P17) | (((val) & 0x1) << 17)) +/* Port 1 Pin # Output Value (16) */ +#define PORT_P1_OUT_P16 (0x1 << 16) +#define PORT_P1_OUT_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P1_OUT_P16_GET(val) ((((val) & PORT_P1_OUT_P16) >> 16) & 0x1) +#define PORT_P1_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P16) | (((val) & 0x1) << 16)) +/* Port 1 Pin # Output Value (15) */ +#define PORT_P1_OUT_P15 (0x1 << 15) +#define PORT_P1_OUT_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P1_OUT_P15_GET(val) ((((val) & PORT_P1_OUT_P15) >> 15) & 0x1) +#define PORT_P1_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P15) | (((val) & 0x1) << 15)) +/* Port 1 Pin # Output Value (14) */ +#define PORT_P1_OUT_P14 (0x1 << 14) +#define PORT_P1_OUT_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P1_OUT_P14_GET(val) ((((val) & PORT_P1_OUT_P14) >> 14) & 0x1) +#define PORT_P1_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P14) | (((val) & 0x1) << 14)) +/* Port 1 Pin # Output Value (13) */ +#define PORT_P1_OUT_P13 (0x1 << 13) +#define PORT_P1_OUT_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P1_OUT_P13_GET(val) ((((val) & PORT_P1_OUT_P13) >> 13) & 0x1) +#define PORT_P1_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P13) | (((val) & 0x1) << 13)) +/* Port 1 Pin # Output Value (12) */ +#define PORT_P1_OUT_P12 (0x1 << 12) +#define PORT_P1_OUT_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P1_OUT_P12_GET(val) ((((val) & PORT_P1_OUT_P12) >> 12) & 0x1) +#define PORT_P1_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P12) | (((val) & 0x1) << 12)) +/* Port 1 Pin # Output Value (11) */ +#define PORT_P1_OUT_P11 (0x1 << 11) +#define PORT_P1_OUT_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P1_OUT_P11_GET(val) ((((val) & PORT_P1_OUT_P11) >> 11) & 0x1) +#define PORT_P1_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P11) | (((val) & 0x1) << 11)) +/* Port 1 Pin # Output Value (10) */ +#define PORT_P1_OUT_P10 (0x1 << 10) +#define PORT_P1_OUT_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P1_OUT_P10_GET(val) ((((val) & PORT_P1_OUT_P10) >> 10) & 0x1) +#define PORT_P1_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P10) | (((val) & 0x1) << 10)) +/* Port 1 Pin # Output Value (9) */ +#define PORT_P1_OUT_P9 (0x1 << 9) +#define PORT_P1_OUT_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P1_OUT_P9_GET(val) ((((val) & PORT_P1_OUT_P9) >> 9) & 0x1) +#define PORT_P1_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P9) | (((val) & 0x1) << 9)) +/* Port 1 Pin # Output Value (8) */ +#define PORT_P1_OUT_P8 (0x1 << 8) +#define PORT_P1_OUT_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P1_OUT_P8_GET(val) ((((val) & PORT_P1_OUT_P8) >> 8) & 0x1) +#define PORT_P1_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P8) | (((val) & 0x1) << 8)) +/* Port 1 Pin # Output Value (7) */ +#define PORT_P1_OUT_P7 (0x1 << 7) +#define PORT_P1_OUT_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P1_OUT_P7_GET(val) ((((val) & PORT_P1_OUT_P7) >> 7) & 0x1) +#define PORT_P1_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P7) | (((val) & 0x1) << 7)) +/* Port 1 Pin # Output Value (6) */ +#define PORT_P1_OUT_P6 (0x1 << 6) +#define PORT_P1_OUT_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P1_OUT_P6_GET(val) ((((val) & PORT_P1_OUT_P6) >> 6) & 0x1) +#define PORT_P1_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P6) | (((val) & 0x1) << 6)) +/* Port 1 Pin # Output Value (5) */ +#define PORT_P1_OUT_P5 (0x1 << 5) +#define PORT_P1_OUT_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P1_OUT_P5_GET(val) ((((val) & PORT_P1_OUT_P5) >> 5) & 0x1) +#define PORT_P1_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P5) | (((val) & 0x1) << 5)) +/* Port 1 Pin # Output Value (4) */ +#define PORT_P1_OUT_P4 (0x1 << 4) +#define PORT_P1_OUT_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P1_OUT_P4_GET(val) ((((val) & PORT_P1_OUT_P4) >> 4) & 0x1) +#define PORT_P1_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P4) | (((val) & 0x1) << 4)) +/* Port 1 Pin # Output Value (3) */ +#define PORT_P1_OUT_P3 (0x1 << 3) +#define PORT_P1_OUT_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P1_OUT_P3_GET(val) ((((val) & PORT_P1_OUT_P3) >> 3) & 0x1) +#define PORT_P1_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P3) | (((val) & 0x1) << 3)) +/* Port 1 Pin # Output Value (2) */ +#define PORT_P1_OUT_P2 (0x1 << 2) +#define PORT_P1_OUT_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P1_OUT_P2_GET(val) ((((val) & PORT_P1_OUT_P2) >> 2) & 0x1) +#define PORT_P1_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P2) | (((val) & 0x1) << 2)) +/* Port 1 Pin # Output Value (1) */ +#define PORT_P1_OUT_P1 (0x1 << 1) +#define PORT_P1_OUT_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P1_OUT_P1_GET(val) ((((val) & PORT_P1_OUT_P1) >> 1) & 0x1) +#define PORT_P1_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P1) | (((val) & 0x1) << 1)) +/* Port 1 Pin # Output Value (0) */ +#define PORT_P1_OUT_P0 (0x1) +#define PORT_P1_OUT_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P1_OUT_P0_GET(val) ((((val) & PORT_P1_OUT_P0) >> 0) & 0x1) +#define PORT_P1_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 1 Data Input Register + ******************************************************************************/ + +/* Port 1 Pin # Latched Input Value (19) */ +#define PORT_P1_IN_P19 (0x1 << 19) +#define PORT_P1_IN_P19_GET(val) ((((val) & PORT_P1_IN_P19) >> 19) & 0x1) +/* Port 1 Pin # Latched Input Value (18) */ +#define PORT_P1_IN_P18 (0x1 << 18) +#define PORT_P1_IN_P18_GET(val) ((((val) & PORT_P1_IN_P18) >> 18) & 0x1) +/* Port 1 Pin # Latched Input Value (17) */ +#define PORT_P1_IN_P17 (0x1 << 17) +#define PORT_P1_IN_P17_GET(val) ((((val) & PORT_P1_IN_P17) >> 17) & 0x1) +/* Port 1 Pin # Latched Input Value (16) */ +#define PORT_P1_IN_P16 (0x1 << 16) +#define PORT_P1_IN_P16_GET(val) ((((val) & PORT_P1_IN_P16) >> 16) & 0x1) +/* Port 1 Pin # Latched Input Value (15) */ +#define PORT_P1_IN_P15 (0x1 << 15) +#define PORT_P1_IN_P15_GET(val) ((((val) & PORT_P1_IN_P15) >> 15) & 0x1) +/* Port 1 Pin # Latched Input Value (14) */ +#define PORT_P1_IN_P14 (0x1 << 14) +#define PORT_P1_IN_P14_GET(val) ((((val) & PORT_P1_IN_P14) >> 14) & 0x1) +/* Port 1 Pin # Latched Input Value (13) */ +#define PORT_P1_IN_P13 (0x1 << 13) +#define PORT_P1_IN_P13_GET(val) ((((val) & PORT_P1_IN_P13) >> 13) & 0x1) +/* Port 1 Pin # Latched Input Value (12) */ +#define PORT_P1_IN_P12 (0x1 << 12) +#define PORT_P1_IN_P12_GET(val) ((((val) & PORT_P1_IN_P12) >> 12) & 0x1) +/* Port 1 Pin # Latched Input Value (11) */ +#define PORT_P1_IN_P11 (0x1 << 11) +#define PORT_P1_IN_P11_GET(val) ((((val) & PORT_P1_IN_P11) >> 11) & 0x1) +/* Port 1 Pin # Latched Input Value (10) */ +#define PORT_P1_IN_P10 (0x1 << 10) +#define PORT_P1_IN_P10_GET(val) ((((val) & PORT_P1_IN_P10) >> 10) & 0x1) +/* Port 1 Pin # Latched Input Value (9) */ +#define PORT_P1_IN_P9 (0x1 << 9) +#define PORT_P1_IN_P9_GET(val) ((((val) & PORT_P1_IN_P9) >> 9) & 0x1) +/* Port 1 Pin # Latched Input Value (8) */ +#define PORT_P1_IN_P8 (0x1 << 8) +#define PORT_P1_IN_P8_GET(val) ((((val) & PORT_P1_IN_P8) >> 8) & 0x1) +/* Port 1 Pin # Latched Input Value (7) */ +#define PORT_P1_IN_P7 (0x1 << 7) +#define PORT_P1_IN_P7_GET(val) ((((val) & PORT_P1_IN_P7) >> 7) & 0x1) +/* Port 1 Pin # Latched Input Value (6) */ +#define PORT_P1_IN_P6 (0x1 << 6) +#define PORT_P1_IN_P6_GET(val) ((((val) & PORT_P1_IN_P6) >> 6) & 0x1) +/* Port 1 Pin # Latched Input Value (5) */ +#define PORT_P1_IN_P5 (0x1 << 5) +#define PORT_P1_IN_P5_GET(val) ((((val) & PORT_P1_IN_P5) >> 5) & 0x1) +/* Port 1 Pin # Latched Input Value (4) */ +#define PORT_P1_IN_P4 (0x1 << 4) +#define PORT_P1_IN_P4_GET(val) ((((val) & PORT_P1_IN_P4) >> 4) & 0x1) +/* Port 1 Pin # Latched Input Value (3) */ +#define PORT_P1_IN_P3 (0x1 << 3) +#define PORT_P1_IN_P3_GET(val) ((((val) & PORT_P1_IN_P3) >> 3) & 0x1) +/* Port 1 Pin # Latched Input Value (2) */ +#define PORT_P1_IN_P2 (0x1 << 2) +#define PORT_P1_IN_P2_GET(val) ((((val) & PORT_P1_IN_P2) >> 2) & 0x1) +/* Port 1 Pin # Latched Input Value (1) */ +#define PORT_P1_IN_P1 (0x1 << 1) +#define PORT_P1_IN_P1_GET(val) ((((val) & PORT_P1_IN_P1) >> 1) & 0x1) +/* Port 1 Pin # Latched Input Value (0) */ +#define PORT_P1_IN_P0 (0x1) +#define PORT_P1_IN_P0_GET(val) ((((val) & PORT_P1_IN_P0) >> 0) & 0x1) + +/******************************************************************************* + * Port 1 Direction Register + ******************************************************************************/ + +/* Port 1 Pin #Direction Control (19) */ +#define PORT_P1_DIR_P19 (0x1 << 19) +#define PORT_P1_DIR_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P1_DIR_P19_GET(val) ((((val) & PORT_P1_DIR_P19) >> 19) & 0x1) +#define PORT_P1_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P19) | (((val) & 0x1) << 19)) +/* Port 1 Pin #Direction Control (18) */ +#define PORT_P1_DIR_P18 (0x1 << 18) +#define PORT_P1_DIR_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P1_DIR_P18_GET(val) ((((val) & PORT_P1_DIR_P18) >> 18) & 0x1) +#define PORT_P1_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P18) | (((val) & 0x1) << 18)) +/* Port 1 Pin #Direction Control (17) */ +#define PORT_P1_DIR_P17 (0x1 << 17) +#define PORT_P1_DIR_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P1_DIR_P17_GET(val) ((((val) & PORT_P1_DIR_P17) >> 17) & 0x1) +#define PORT_P1_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P17) | (((val) & 0x1) << 17)) +/* Port 1 Pin #Direction Control (16) */ +#define PORT_P1_DIR_P16 (0x1 << 16) +#define PORT_P1_DIR_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P1_DIR_P16_GET(val) ((((val) & PORT_P1_DIR_P16) >> 16) & 0x1) +#define PORT_P1_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P16) | (((val) & 0x1) << 16)) +/* Port 1 Pin #Direction Control (15) */ +#define PORT_P1_DIR_P15 (0x1 << 15) +#define PORT_P1_DIR_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P1_DIR_P15_GET(val) ((((val) & PORT_P1_DIR_P15) >> 15) & 0x1) +#define PORT_P1_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P15) | (((val) & 0x1) << 15)) +/* Port 1 Pin #Direction Control (14) */ +#define PORT_P1_DIR_P14 (0x1 << 14) +#define PORT_P1_DIR_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P1_DIR_P14_GET(val) ((((val) & PORT_P1_DIR_P14) >> 14) & 0x1) +#define PORT_P1_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P14) | (((val) & 0x1) << 14)) +/* Port 1 Pin #Direction Control (13) */ +#define PORT_P1_DIR_P13 (0x1 << 13) +#define PORT_P1_DIR_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P1_DIR_P13_GET(val) ((((val) & PORT_P1_DIR_P13) >> 13) & 0x1) +#define PORT_P1_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P13) | (((val) & 0x1) << 13)) +/* Port 1 Pin #Direction Control (12) */ +#define PORT_P1_DIR_P12 (0x1 << 12) +#define PORT_P1_DIR_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P1_DIR_P12_GET(val) ((((val) & PORT_P1_DIR_P12) >> 12) & 0x1) +#define PORT_P1_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P12) | (((val) & 0x1) << 12)) +/* Port 1 Pin #Direction Control (11) */ +#define PORT_P1_DIR_P11 (0x1 << 11) +#define PORT_P1_DIR_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P1_DIR_P11_GET(val) ((((val) & PORT_P1_DIR_P11) >> 11) & 0x1) +#define PORT_P1_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P11) | (((val) & 0x1) << 11)) +/* Port 1 Pin #Direction Control (10) */ +#define PORT_P1_DIR_P10 (0x1 << 10) +#define PORT_P1_DIR_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P1_DIR_P10_GET(val) ((((val) & PORT_P1_DIR_P10) >> 10) & 0x1) +#define PORT_P1_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P10) | (((val) & 0x1) << 10)) +/* Port 1 Pin #Direction Control (9) */ +#define PORT_P1_DIR_P9 (0x1 << 9) +#define PORT_P1_DIR_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P1_DIR_P9_GET(val) ((((val) & PORT_P1_DIR_P9) >> 9) & 0x1) +#define PORT_P1_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P9) | (((val) & 0x1) << 9)) +/* Port 1 Pin #Direction Control (8) */ +#define PORT_P1_DIR_P8 (0x1 << 8) +#define PORT_P1_DIR_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P1_DIR_P8_GET(val) ((((val) & PORT_P1_DIR_P8) >> 8) & 0x1) +#define PORT_P1_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P8) | (((val) & 0x1) << 8)) +/* Port 1 Pin #Direction Control (7) */ +#define PORT_P1_DIR_P7 (0x1 << 7) +#define PORT_P1_DIR_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P1_DIR_P7_GET(val) ((((val) & PORT_P1_DIR_P7) >> 7) & 0x1) +#define PORT_P1_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P7) | (((val) & 0x1) << 7)) +/* Port 1 Pin #Direction Control (6) */ +#define PORT_P1_DIR_P6 (0x1 << 6) +#define PORT_P1_DIR_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P1_DIR_P6_GET(val) ((((val) & PORT_P1_DIR_P6) >> 6) & 0x1) +#define PORT_P1_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P6) | (((val) & 0x1) << 6)) +/* Port 1 Pin #Direction Control (5) */ +#define PORT_P1_DIR_P5 (0x1 << 5) +#define PORT_P1_DIR_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P1_DIR_P5_GET(val) ((((val) & PORT_P1_DIR_P5) >> 5) & 0x1) +#define PORT_P1_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P5) | (((val) & 0x1) << 5)) +/* Port 1 Pin #Direction Control (4) */ +#define PORT_P1_DIR_P4 (0x1 << 4) +#define PORT_P1_DIR_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P1_DIR_P4_GET(val) ((((val) & PORT_P1_DIR_P4) >> 4) & 0x1) +#define PORT_P1_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P4) | (((val) & 0x1) << 4)) +/* Port 1 Pin #Direction Control (3) */ +#define PORT_P1_DIR_P3 (0x1 << 3) +#define PORT_P1_DIR_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P1_DIR_P3_GET(val) ((((val) & PORT_P1_DIR_P3) >> 3) & 0x1) +#define PORT_P1_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P3) | (((val) & 0x1) << 3)) +/* Port 1 Pin #Direction Control (2) */ +#define PORT_P1_DIR_P2 (0x1 << 2) +#define PORT_P1_DIR_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P1_DIR_P2_GET(val) ((((val) & PORT_P1_DIR_P2) >> 2) & 0x1) +#define PORT_P1_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P2) | (((val) & 0x1) << 2)) +/* Port 1 Pin #Direction Control (1) */ +#define PORT_P1_DIR_P1 (0x1 << 1) +#define PORT_P1_DIR_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P1_DIR_P1_GET(val) ((((val) & PORT_P1_DIR_P1) >> 1) & 0x1) +#define PORT_P1_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P1) | (((val) & 0x1) << 1)) +/* Port 1 Pin #Direction Control (0) */ +#define PORT_P1_DIR_P0 (0x1) +#define PORT_P1_DIR_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P1_DIR_P0_GET(val) ((((val) & PORT_P1_DIR_P0) >> 0) & 0x1) +#define PORT_P1_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 1 Alternate Function Select Register 0 + ******************************************************************************/ + +/* Alternate Function at Port 1 Bit # (19) */ +#define PORT_P1_ALTSEL0_P19 (0x1 << 19) +#define PORT_P1_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P1_ALTSEL0_P19_GET(val) ((((val) & PORT_P1_ALTSEL0_P19) >> 19) & 0x1) +#define PORT_P1_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P19) | (((val) & 0x1) << 19)) +/* Alternate Function at Port 1 Bit # (18) */ +#define PORT_P1_ALTSEL0_P18 (0x1 << 18) +#define PORT_P1_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P1_ALTSEL0_P18_GET(val) ((((val) & PORT_P1_ALTSEL0_P18) >> 18) & 0x1) +#define PORT_P1_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P18) | (((val) & 0x1) << 18)) +/* Alternate Function at Port 1 Bit # (17) */ +#define PORT_P1_ALTSEL0_P17 (0x1 << 17) +#define PORT_P1_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P1_ALTSEL0_P17_GET(val) ((((val) & PORT_P1_ALTSEL0_P17) >> 17) & 0x1) +#define PORT_P1_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P17) | (((val) & 0x1) << 17)) +/* Alternate Function at Port 1 Bit # (16) */ +#define PORT_P1_ALTSEL0_P16 (0x1 << 16) +#define PORT_P1_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P1_ALTSEL0_P16_GET(val) ((((val) & PORT_P1_ALTSEL0_P16) >> 16) & 0x1) +#define PORT_P1_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P16) | (((val) & 0x1) << 16)) +/* Alternate Function at Port 1 Bit # (15) */ +#define PORT_P1_ALTSEL0_P15 (0x1 << 15) +#define PORT_P1_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P1_ALTSEL0_P15_GET(val) ((((val) & PORT_P1_ALTSEL0_P15) >> 15) & 0x1) +#define PORT_P1_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P15) | (((val) & 0x1) << 15)) +/* Alternate Function at Port 1 Bit # (14) */ +#define PORT_P1_ALTSEL0_P14 (0x1 << 14) +#define PORT_P1_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P1_ALTSEL0_P14_GET(val) ((((val) & PORT_P1_ALTSEL0_P14) >> 14) & 0x1) +#define PORT_P1_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P14) | (((val) & 0x1) << 14)) +/* Alternate Function at Port 1 Bit # (13) */ +#define PORT_P1_ALTSEL0_P13 (0x1 << 13) +#define PORT_P1_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P1_ALTSEL0_P13_GET(val) ((((val) & PORT_P1_ALTSEL0_P13) >> 13) & 0x1) +#define PORT_P1_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P13) | (((val) & 0x1) << 13)) +/* Alternate Function at Port 1 Bit # (12) */ +#define PORT_P1_ALTSEL0_P12 (0x1 << 12) +#define PORT_P1_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P1_ALTSEL0_P12_GET(val) ((((val) & PORT_P1_ALTSEL0_P12) >> 12) & 0x1) +#define PORT_P1_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P12) | (((val) & 0x1) << 12)) +/* Alternate Function at Port 1 Bit # (11) */ +#define PORT_P1_ALTSEL0_P11 (0x1 << 11) +#define PORT_P1_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P1_ALTSEL0_P11_GET(val) ((((val) & PORT_P1_ALTSEL0_P11) >> 11) & 0x1) +#define PORT_P1_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P11) | (((val) & 0x1) << 11)) +/* Alternate Function at Port 1 Bit # (10) */ +#define PORT_P1_ALTSEL0_P10 (0x1 << 10) +#define PORT_P1_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P1_ALTSEL0_P10_GET(val) ((((val) & PORT_P1_ALTSEL0_P10) >> 10) & 0x1) +#define PORT_P1_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P10) | (((val) & 0x1) << 10)) +/* Alternate Function at Port 1 Bit # (9) */ +#define PORT_P1_ALTSEL0_P9 (0x1 << 9) +#define PORT_P1_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P1_ALTSEL0_P9_GET(val) ((((val) & PORT_P1_ALTSEL0_P9) >> 9) & 0x1) +#define PORT_P1_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P9) | (((val) & 0x1) << 9)) +/* Alternate Function at Port 1 Bit # (8) */ +#define PORT_P1_ALTSEL0_P8 (0x1 << 8) +#define PORT_P1_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P1_ALTSEL0_P8_GET(val) ((((val) & PORT_P1_ALTSEL0_P8) >> 8) & 0x1) +#define PORT_P1_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P8) | (((val) & 0x1) << 8)) +/* Alternate Function at Port 1 Bit # (7) */ +#define PORT_P1_ALTSEL0_P7 (0x1 << 7) +#define PORT_P1_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P1_ALTSEL0_P7_GET(val) ((((val) & PORT_P1_ALTSEL0_P7) >> 7) & 0x1) +#define PORT_P1_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P7) | (((val) & 0x1) << 7)) +/* Alternate Function at Port 1 Bit # (6) */ +#define PORT_P1_ALTSEL0_P6 (0x1 << 6) +#define PORT_P1_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P1_ALTSEL0_P6_GET(val) ((((val) & PORT_P1_ALTSEL0_P6) >> 6) & 0x1) +#define PORT_P1_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P6) | (((val) & 0x1) << 6)) +/* Alternate Function at Port 1 Bit # (5) */ +#define PORT_P1_ALTSEL0_P5 (0x1 << 5) +#define PORT_P1_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P1_ALTSEL0_P5_GET(val) ((((val) & PORT_P1_ALTSEL0_P5) >> 5) & 0x1) +#define PORT_P1_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P5) | (((val) & 0x1) << 5)) +/* Alternate Function at Port 1 Bit # (4) */ +#define PORT_P1_ALTSEL0_P4 (0x1 << 4) +#define PORT_P1_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P1_ALTSEL0_P4_GET(val) ((((val) & PORT_P1_ALTSEL0_P4) >> 4) & 0x1) +#define PORT_P1_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P4) | (((val) & 0x1) << 4)) +/* Alternate Function at Port 1 Bit # (3) */ +#define PORT_P1_ALTSEL0_P3 (0x1 << 3) +#define PORT_P1_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P1_ALTSEL0_P3_GET(val) ((((val) & PORT_P1_ALTSEL0_P3) >> 3) & 0x1) +#define PORT_P1_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P3) | (((val) & 0x1) << 3)) +/* Alternate Function at Port 1 Bit # (2) */ +#define PORT_P1_ALTSEL0_P2 (0x1 << 2) +#define PORT_P1_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P1_ALTSEL0_P2_GET(val) ((((val) & PORT_P1_ALTSEL0_P2) >> 2) & 0x1) +#define PORT_P1_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P2) | (((val) & 0x1) << 2)) +/* Alternate Function at Port 1 Bit # (1) */ +#define PORT_P1_ALTSEL0_P1 (0x1 << 1) +#define PORT_P1_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P1_ALTSEL0_P1_GET(val) ((((val) & PORT_P1_ALTSEL0_P1) >> 1) & 0x1) +#define PORT_P1_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P1) | (((val) & 0x1) << 1)) +/* Alternate Function at Port 1 Bit # (0) */ +#define PORT_P1_ALTSEL0_P0 (0x1) +#define PORT_P1_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P1_ALTSEL0_P0_GET(val) ((((val) & PORT_P1_ALTSEL0_P0) >> 0) & 0x1) +#define PORT_P1_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 1 Pull Up Device Enable Register + ******************************************************************************/ + +/* Pull Up Device Enable at Port 1 Bit # (19) */ +#define PORT_P1_PUEN_P19 (0x1 << 19) +#define PORT_P1_PUEN_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P1_PUEN_P19_GET(val) ((((val) & PORT_P1_PUEN_P19) >> 19) & 0x1) +#define PORT_P1_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P19) | (((val) & 0x1) << 19)) +/* Pull Up Device Enable at Port 1 Bit # (18) */ +#define PORT_P1_PUEN_P18 (0x1 << 18) +#define PORT_P1_PUEN_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P1_PUEN_P18_GET(val) ((((val) & PORT_P1_PUEN_P18) >> 18) & 0x1) +#define PORT_P1_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P18) | (((val) & 0x1) << 18)) +/* Pull Up Device Enable at Port 1 Bit # (17) */ +#define PORT_P1_PUEN_P17 (0x1 << 17) +#define PORT_P1_PUEN_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P1_PUEN_P17_GET(val) ((((val) & PORT_P1_PUEN_P17) >> 17) & 0x1) +#define PORT_P1_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P17) | (((val) & 0x1) << 17)) +/* Pull Up Device Enable at Port 1 Bit # (16) */ +#define PORT_P1_PUEN_P16 (0x1 << 16) +#define PORT_P1_PUEN_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P1_PUEN_P16_GET(val) ((((val) & PORT_P1_PUEN_P16) >> 16) & 0x1) +#define PORT_P1_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P16) | (((val) & 0x1) << 16)) +/* Pull Up Device Enable at Port 1 Bit # (15) */ +#define PORT_P1_PUEN_P15 (0x1 << 15) +#define PORT_P1_PUEN_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P1_PUEN_P15_GET(val) ((((val) & PORT_P1_PUEN_P15) >> 15) & 0x1) +#define PORT_P1_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P15) | (((val) & 0x1) << 15)) +/* Pull Up Device Enable at Port 1 Bit # (14) */ +#define PORT_P1_PUEN_P14 (0x1 << 14) +#define PORT_P1_PUEN_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P1_PUEN_P14_GET(val) ((((val) & PORT_P1_PUEN_P14) >> 14) & 0x1) +#define PORT_P1_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P14) | (((val) & 0x1) << 14)) +/* Pull Up Device Enable at Port 1 Bit # (13) */ +#define PORT_P1_PUEN_P13 (0x1 << 13) +#define PORT_P1_PUEN_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P1_PUEN_P13_GET(val) ((((val) & PORT_P1_PUEN_P13) >> 13) & 0x1) +#define PORT_P1_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P13) | (((val) & 0x1) << 13)) +/* Pull Up Device Enable at Port 1 Bit # (12) */ +#define PORT_P1_PUEN_P12 (0x1 << 12) +#define PORT_P1_PUEN_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P1_PUEN_P12_GET(val) ((((val) & PORT_P1_PUEN_P12) >> 12) & 0x1) +#define PORT_P1_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P12) | (((val) & 0x1) << 12)) +/* Pull Up Device Enable at Port 1 Bit # (11) */ +#define PORT_P1_PUEN_P11 (0x1 << 11) +#define PORT_P1_PUEN_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P1_PUEN_P11_GET(val) ((((val) & PORT_P1_PUEN_P11) >> 11) & 0x1) +#define PORT_P1_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P11) | (((val) & 0x1) << 11)) +/* Pull Up Device Enable at Port 1 Bit # (10) */ +#define PORT_P1_PUEN_P10 (0x1 << 10) +#define PORT_P1_PUEN_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P1_PUEN_P10_GET(val) ((((val) & PORT_P1_PUEN_P10) >> 10) & 0x1) +#define PORT_P1_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P10) | (((val) & 0x1) << 10)) +/* Pull Up Device Enable at Port 1 Bit # (9) */ +#define PORT_P1_PUEN_P9 (0x1 << 9) +#define PORT_P1_PUEN_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P1_PUEN_P9_GET(val) ((((val) & PORT_P1_PUEN_P9) >> 9) & 0x1) +#define PORT_P1_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P9) | (((val) & 0x1) << 9)) +/* Pull Up Device Enable at Port 1 Bit # (8) */ +#define PORT_P1_PUEN_P8 (0x1 << 8) +#define PORT_P1_PUEN_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P1_PUEN_P8_GET(val) ((((val) & PORT_P1_PUEN_P8) >> 8) & 0x1) +#define PORT_P1_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P8) | (((val) & 0x1) << 8)) +/* Pull Up Device Enable at Port 1 Bit # (7) */ +#define PORT_P1_PUEN_P7 (0x1 << 7) +#define PORT_P1_PUEN_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P1_PUEN_P7_GET(val) ((((val) & PORT_P1_PUEN_P7) >> 7) & 0x1) +#define PORT_P1_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P7) | (((val) & 0x1) << 7)) +/* Pull Up Device Enable at Port 1 Bit # (6) */ +#define PORT_P1_PUEN_P6 (0x1 << 6) +#define PORT_P1_PUEN_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P1_PUEN_P6_GET(val) ((((val) & PORT_P1_PUEN_P6) >> 6) & 0x1) +#define PORT_P1_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P6) | (((val) & 0x1) << 6)) +/* Pull Up Device Enable at Port 1 Bit # (5) */ +#define PORT_P1_PUEN_P5 (0x1 << 5) +#define PORT_P1_PUEN_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P1_PUEN_P5_GET(val) ((((val) & PORT_P1_PUEN_P5) >> 5) & 0x1) +#define PORT_P1_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P5) | (((val) & 0x1) << 5)) +/* Pull Up Device Enable at Port 1 Bit # (4) */ +#define PORT_P1_PUEN_P4 (0x1 << 4) +#define PORT_P1_PUEN_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P1_PUEN_P4_GET(val) ((((val) & PORT_P1_PUEN_P4) >> 4) & 0x1) +#define PORT_P1_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P4) | (((val) & 0x1) << 4)) +/* Pull Up Device Enable at Port 1 Bit # (3) */ +#define PORT_P1_PUEN_P3 (0x1 << 3) +#define PORT_P1_PUEN_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P1_PUEN_P3_GET(val) ((((val) & PORT_P1_PUEN_P3) >> 3) & 0x1) +#define PORT_P1_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P3) | (((val) & 0x1) << 3)) +/* Pull Up Device Enable at Port 1 Bit # (2) */ +#define PORT_P1_PUEN_P2 (0x1 << 2) +#define PORT_P1_PUEN_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P1_PUEN_P2_GET(val) ((((val) & PORT_P1_PUEN_P2) >> 2) & 0x1) +#define PORT_P1_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P2) | (((val) & 0x1) << 2)) +/* Pull Up Device Enable at Port 1 Bit # (1) */ +#define PORT_P1_PUEN_P1 (0x1 << 1) +#define PORT_P1_PUEN_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P1_PUEN_P1_GET(val) ((((val) & PORT_P1_PUEN_P1) >> 1) & 0x1) +#define PORT_P1_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P1) | (((val) & 0x1) << 1)) +/* Pull Up Device Enable at Port 1 Bit # (0) */ +#define PORT_P1_PUEN_P0 (0x1) +#define PORT_P1_PUEN_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P1_PUEN_P0_GET(val) ((((val) & PORT_P1_PUEN_P0) >> 0) & 0x1) +#define PORT_P1_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * External Interrupt Control Register 0 + ******************************************************************************/ + +/* Type of Level or Edge Detection of EXINT15 (19) */ +#define PORT_P1_EXINTCR0_EXINT15 (0x1 << 19) +#define PORT_P1_EXINTCR0_EXINT15_VAL(val) (((val) & 0x1) << 19) +#define PORT_P1_EXINTCR0_EXINT15_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT15) >> 19) & 0x1) +#define PORT_P1_EXINTCR0_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT15) | (((val) & 0x1) << 19)) +/* Type of Level or Edge Detection of EXINT11 (18) */ +#define PORT_P1_EXINTCR0_EXINT11 (0x1 << 18) +#define PORT_P1_EXINTCR0_EXINT11_VAL(val) (((val) & 0x1) << 18) +#define PORT_P1_EXINTCR0_EXINT11_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT11) >> 18) & 0x1) +#define PORT_P1_EXINTCR0_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT11) | (((val) & 0x1) << 18)) +/* Type of Level or Edge Detection of EXINT12 (17) */ +#define PORT_P1_EXINTCR0_EXINT12 (0x1 << 17) +#define PORT_P1_EXINTCR0_EXINT12_VAL(val) (((val) & 0x1) << 17) +#define PORT_P1_EXINTCR0_EXINT12_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT12) >> 17) & 0x1) +#define PORT_P1_EXINTCR0_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT12) | (((val) & 0x1) << 17)) +/* Type of Level or Edge Detection of EXINT13 (16) */ +#define PORT_P1_EXINTCR0_EXINT13 (0x1 << 16) +#define PORT_P1_EXINTCR0_EXINT13_VAL(val) (((val) & 0x1) << 16) +#define PORT_P1_EXINTCR0_EXINT13_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT13) >> 16) & 0x1) +#define PORT_P1_EXINTCR0_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT13) | (((val) & 0x1) << 16)) +/* Type of Level or Edge Detection of EXINT14 (15) */ +#define PORT_P1_EXINTCR0_EXINT14 (0x1 << 15) +#define PORT_P1_EXINTCR0_EXINT14_VAL(val) (((val) & 0x1) << 15) +#define PORT_P1_EXINTCR0_EXINT14_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT14) >> 15) & 0x1) +#define PORT_P1_EXINTCR0_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT14) | (((val) & 0x1) << 15)) + +/******************************************************************************* + * External Interrupt Control Register 1 + ******************************************************************************/ + +/* Type of Level or Edge Detection of EXINT15 (19) */ +#define PORT_P1_EXINTCR1_EXINT15 (0x1 << 19) +#define PORT_P1_EXINTCR1_EXINT15_VAL(val) (((val) & 0x1) << 19) +#define PORT_P1_EXINTCR1_EXINT15_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT15) >> 19) & 0x1) +#define PORT_P1_EXINTCR1_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT15) | (((val) & 0x1) << 19)) +/* Type of Level or Edge Detection of EXINT11 (18) */ +#define PORT_P1_EXINTCR1_EXINT11 (0x1 << 18) +#define PORT_P1_EXINTCR1_EXINT11_VAL(val) (((val) & 0x1) << 18) +#define PORT_P1_EXINTCR1_EXINT11_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT11) >> 18) & 0x1) +#define PORT_P1_EXINTCR1_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT11) | (((val) & 0x1) << 18)) +/* Type of Level or Edge Detection of EXINT12 (17) */ +#define PORT_P1_EXINTCR1_EXINT12 (0x1 << 17) +#define PORT_P1_EXINTCR1_EXINT12_VAL(val) (((val) & 0x1) << 17) +#define PORT_P1_EXINTCR1_EXINT12_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT12) >> 17) & 0x1) +#define PORT_P1_EXINTCR1_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT12) | (((val) & 0x1) << 17)) +/* Type of Level or Edge Detection of EXINT13 (16) */ +#define PORT_P1_EXINTCR1_EXINT13 (0x1 << 16) +#define PORT_P1_EXINTCR1_EXINT13_VAL(val) (((val) & 0x1) << 16) +#define PORT_P1_EXINTCR1_EXINT13_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT13) >> 16) & 0x1) +#define PORT_P1_EXINTCR1_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT13) | (((val) & 0x1) << 16)) +/* Type of Level or Edge Detection of EXINT14 (15) */ +#define PORT_P1_EXINTCR1_EXINT14 (0x1 << 15) +#define PORT_P1_EXINTCR1_EXINT14_VAL(val) (((val) & 0x1) << 15) +#define PORT_P1_EXINTCR1_EXINT14_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT14) >> 15) & 0x1) +#define PORT_P1_EXINTCR1_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT14) | (((val) & 0x1) << 15)) + +/******************************************************************************* + * P1_IRNEN Register + ******************************************************************************/ + +/* EXINT15 Interrupt Request Enable (19) */ +#define PORT_P1_IRNEN_EXINT15 (0x1 << 19) +#define PORT_P1_IRNEN_EXINT15_VAL(val) (((val) & 0x1) << 19) +#define PORT_P1_IRNEN_EXINT15_GET(val) ((((val) & PORT_P1_IRNEN_EXINT15) >> 19) & 0x1) +#define PORT_P1_IRNEN_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT15) | (((val) & 0x1) << 19)) +/* EXINT11 Interrupt Request Enable (18) */ +#define PORT_P1_IRNEN_EXINT11 (0x1 << 18) +#define PORT_P1_IRNEN_EXINT11_VAL(val) (((val) & 0x1) << 18) +#define PORT_P1_IRNEN_EXINT11_GET(val) ((((val) & PORT_P1_IRNEN_EXINT11) >> 18) & 0x1) +#define PORT_P1_IRNEN_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT11) | (((val) & 0x1) << 18)) +/* EXINT12 Interrupt Request Enable (17) */ +#define PORT_P1_IRNEN_EXINT12 (0x1 << 17) +#define PORT_P1_IRNEN_EXINT12_VAL(val) (((val) & 0x1) << 17) +#define PORT_P1_IRNEN_EXINT12_GET(val) ((((val) & PORT_P1_IRNEN_EXINT12) >> 17) & 0x1) +#define PORT_P1_IRNEN_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT12) | (((val) & 0x1) << 17)) +/* EXINT13 Interrupt Request Enable (16) */ +#define PORT_P1_IRNEN_EXINT13 (0x1 << 16) +#define PORT_P1_IRNEN_EXINT13_VAL(val) (((val) & 0x1) << 16) +#define PORT_P1_IRNEN_EXINT13_GET(val) ((((val) & PORT_P1_IRNEN_EXINT13) >> 16) & 0x1) +#define PORT_P1_IRNEN_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT13) | (((val) & 0x1) << 16)) +/* EXINT14 Interrupt Request Enable (15) */ +#define PORT_P1_IRNEN_EXINT14 (0x1 << 15) +#define PORT_P1_IRNEN_EXINT14_VAL(val) (((val) & 0x1) << 15) +#define PORT_P1_IRNEN_EXINT14_GET(val) ((((val) & PORT_P1_IRNEN_EXINT14) >> 15) & 0x1) +#define PORT_P1_IRNEN_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT14) | (((val) & 0x1) << 15)) + +/******************************************************************************* + * P1_IRNICR Register + ******************************************************************************/ + +/* EXINT15 Interrupt Request (19) */ +#define PORT_P1_IRNICR_EXINT15 (0x1 << 19) +#define PORT_P1_IRNICR_EXINT15_GET(val) ((((val) & PORT_P1_IRNICR_EXINT15) >> 19) & 0x1) +/* EXINT11 Interrupt Request (18) */ +#define PORT_P1_IRNICR_EXINT11 (0x1 << 18) +#define PORT_P1_IRNICR_EXINT11_GET(val) ((((val) & PORT_P1_IRNICR_EXINT11) >> 18) & 0x1) +/* EXINT12 Interrupt Request (17) */ +#define PORT_P1_IRNICR_EXINT12 (0x1 << 17) +#define PORT_P1_IRNICR_EXINT12_GET(val) ((((val) & PORT_P1_IRNICR_EXINT12) >> 17) & 0x1) +/* EXINT13 Interrupt Request (16) */ +#define PORT_P1_IRNICR_EXINT13 (0x1 << 16) +#define PORT_P1_IRNICR_EXINT13_GET(val) ((((val) & PORT_P1_IRNICR_EXINT13) >> 16) & 0x1) +/* EXINT14 Interrupt Request (15) */ +#define PORT_P1_IRNICR_EXINT14 (0x1 << 15) +#define PORT_P1_IRNICR_EXINT14_GET(val) ((((val) & PORT_P1_IRNICR_EXINT14) >> 15) & 0x1) + +/******************************************************************************* + * P1_IRNCR Register + ******************************************************************************/ + +/* EXINT15 Interrupt Request (19) */ +#define PORT_P1_IRNCR_EXINT15 (0x1 << 19) +#define PORT_P1_IRNCR_EXINT15_GET(val) ((((val) & PORT_P1_IRNCR_EXINT15) >> 19) & 0x1) +/* EXINT11 Interrupt Request (18) */ +#define PORT_P1_IRNCR_EXINT11 (0x1 << 18) +#define PORT_P1_IRNCR_EXINT11_GET(val) ((((val) & PORT_P1_IRNCR_EXINT11) >> 18) & 0x1) +/* EXINT12 Interrupt Request (17) */ +#define PORT_P1_IRNCR_EXINT12 (0x1 << 17) +#define PORT_P1_IRNCR_EXINT12_GET(val) ((((val) & PORT_P1_IRNCR_EXINT12) >> 17) & 0x1) +/* EXINT13 Interrupt Request (16) */ +#define PORT_P1_IRNCR_EXINT13 (0x1 << 16) +#define PORT_P1_IRNCR_EXINT13_GET(val) ((((val) & PORT_P1_IRNCR_EXINT13) >> 16) & 0x1) +/* EXINT14 Interrupt Request (15) */ +#define PORT_P1_IRNCR_EXINT14 (0x1 << 15) +#define PORT_P1_IRNCR_EXINT14_GET(val) ((((val) & PORT_P1_IRNCR_EXINT14) >> 15) & 0x1) + +/******************************************************************************* + * P1 External Event Detection Configuration Register + ******************************************************************************/ + +/* EXINT15 configured for Edge or Level Detection (19) */ +#define PORT_P1_IRNCFG_EXINT15 (0x1 << 19) +#define PORT_P1_IRNCFG_EXINT15_VAL(val) (((val) & 0x1) << 19) +#define PORT_P1_IRNCFG_EXINT15_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT15) >> 19) & 0x1) +#define PORT_P1_IRNCFG_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT15) | (((val) & 0x1) << 19)) +/* EXINT11 configured for Edge or Level Detection (18) */ +#define PORT_P1_IRNCFG_EXINT11 (0x1 << 18) +#define PORT_P1_IRNCFG_EXINT11_VAL(val) (((val) & 0x1) << 18) +#define PORT_P1_IRNCFG_EXINT11_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT11) >> 18) & 0x1) +#define PORT_P1_IRNCFG_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT11) | (((val) & 0x1) << 18)) +/* EXINT12 configured for Edge or Level Detection (17) */ +#define PORT_P1_IRNCFG_EXINT12 (0x1 << 17) +#define PORT_P1_IRNCFG_EXINT12_VAL(val) (((val) & 0x1) << 17) +#define PORT_P1_IRNCFG_EXINT12_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT12) >> 17) & 0x1) +#define PORT_P1_IRNCFG_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT12) | (((val) & 0x1) << 17)) +/* EXINT13 configured for Edge or Level Detection (16) */ +#define PORT_P1_IRNCFG_EXINT13 (0x1 << 16) +#define PORT_P1_IRNCFG_EXINT13_VAL(val) (((val) & 0x1) << 16) +#define PORT_P1_IRNCFG_EXINT13_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT13) >> 16) & 0x1) +#define PORT_P1_IRNCFG_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT13) | (((val) & 0x1) << 16)) +/* EXINT14 configured for Edge or Level Detection (15) */ +#define PORT_P1_IRNCFG_EXINT14 (0x1 << 15) +#define PORT_P1_IRNCFG_EXINT14_VAL(val) (((val) & 0x1) << 15) +#define PORT_P1_IRNCFG_EXINT14_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT14) >> 15) & 0x1) +#define PORT_P1_IRNCFG_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT14) | (((val) & 0x1) << 15)) + +/******************************************************************************* + * P1_IRNENSET Register + ******************************************************************************/ + +/* Set Interrupt Node Enable Flag EXINT15 (19) */ +#define PORT_P1_IRNENSET_EXINT15 (0x1 << 19) +#define PORT_P1_IRNENSET_EXINT15_VAL(val) (((val) & 0x1) << 19) +#define PORT_P1_IRNENSET_EXINT15_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT15) | (val) & 1) << 19) +/* Set Interrupt Node Enable Flag EXINT11 (18) */ +#define PORT_P1_IRNENSET_EXINT11 (0x1 << 18) +#define PORT_P1_IRNENSET_EXINT11_VAL(val) (((val) & 0x1) << 18) +#define PORT_P1_IRNENSET_EXINT11_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT11) | (val) & 1) << 18) +/* Set Interrupt Node Enable Flag EXINT12 (17) */ +#define PORT_P1_IRNENSET_EXINT12 (0x1 << 17) +#define PORT_P1_IRNENSET_EXINT12_VAL(val) (((val) & 0x1) << 17) +#define PORT_P1_IRNENSET_EXINT12_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT12) | (val) & 1) << 17) +/* Set Interrupt Node Enable Flag EXINT13 (16) */ +#define PORT_P1_IRNENSET_EXINT13 (0x1 << 16) +#define PORT_P1_IRNENSET_EXINT13_VAL(val) (((val) & 0x1) << 16) +#define PORT_P1_IRNENSET_EXINT13_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT13) | (val) & 1) << 16) +/* Set Interrupt Node Enable Flag EXINT14 (15) */ +#define PORT_P1_IRNENSET_EXINT14 (0x1 << 15) +#define PORT_P1_IRNENSET_EXINT14_VAL(val) (((val) & 0x1) << 15) +#define PORT_P1_IRNENSET_EXINT14_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT14) | (val) & 1) << 15) + +/******************************************************************************* + * P1_IRNENCLR Register + ******************************************************************************/ + +/* Clear Interrupt Node Enable Flag EXINT15 (19) */ +#define PORT_P1_IRNENCLR_EXINT15 (0x1 << 19) +#define PORT_P1_IRNENCLR_EXINT15_VAL(val) (((val) & 0x1) << 19) +#define PORT_P1_IRNENCLR_EXINT15_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT15) | (val) & 1) << 19) +/* Clear Interrupt Node Enable Flag EXINT11 (18) */ +#define PORT_P1_IRNENCLR_EXINT11 (0x1 << 18) +#define PORT_P1_IRNENCLR_EXINT11_VAL(val) (((val) & 0x1) << 18) +#define PORT_P1_IRNENCLR_EXINT11_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT11) | (val) & 1) << 18) +/* Clear Interrupt Node Enable Flag EXINT12 (17) */ +#define PORT_P1_IRNENCLR_EXINT12 (0x1 << 17) +#define PORT_P1_IRNENCLR_EXINT12_VAL(val) (((val) & 0x1) << 17) +#define PORT_P1_IRNENCLR_EXINT12_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT12) | (val) & 1) << 17) +/* Clear Interrupt Node Enable Flag EXINT13 (16) */ +#define PORT_P1_IRNENCLR_EXINT13 (0x1 << 16) +#define PORT_P1_IRNENCLR_EXINT13_VAL(val) (((val) & 0x1) << 16) +#define PORT_P1_IRNENCLR_EXINT13_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT13) | (val) & 1) << 16) +/* Clear Interrupt Node Enable Flag EXINT14 (15) */ +#define PORT_P1_IRNENCLR_EXINT14 (0x1 << 15) +#define PORT_P1_IRNENCLR_EXINT14_VAL(val) (((val) & 0x1) << 15) +#define PORT_P1_IRNENCLR_EXINT14_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT14) | (val) & 1) << 15) + +/******************************************************************************* + * Port 2 Data Output Register + ******************************************************************************/ + +/* Port 2 Pin # Output Value (19) */ +#define PORT_P2_OUT_P19 (0x1 << 19) +#define PORT_P2_OUT_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P2_OUT_P19_GET(val) ((((val) & PORT_P2_OUT_P19) >> 19) & 0x1) +#define PORT_P2_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P19) | (((val) & 0x1) << 19)) +/* Port 2 Pin # Output Value (18) */ +#define PORT_P2_OUT_P18 (0x1 << 18) +#define PORT_P2_OUT_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P2_OUT_P18_GET(val) ((((val) & PORT_P2_OUT_P18) >> 18) & 0x1) +#define PORT_P2_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P18) | (((val) & 0x1) << 18)) +/* Port 2 Pin # Output Value (17) */ +#define PORT_P2_OUT_P17 (0x1 << 17) +#define PORT_P2_OUT_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P2_OUT_P17_GET(val) ((((val) & PORT_P2_OUT_P17) >> 17) & 0x1) +#define PORT_P2_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P17) | (((val) & 0x1) << 17)) +/* Port 2 Pin # Output Value (16) */ +#define PORT_P2_OUT_P16 (0x1 << 16) +#define PORT_P2_OUT_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P2_OUT_P16_GET(val) ((((val) & PORT_P2_OUT_P16) >> 16) & 0x1) +#define PORT_P2_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P16) | (((val) & 0x1) << 16)) +/* Port 2 Pin # Output Value (15) */ +#define PORT_P2_OUT_P15 (0x1 << 15) +#define PORT_P2_OUT_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P2_OUT_P15_GET(val) ((((val) & PORT_P2_OUT_P15) >> 15) & 0x1) +#define PORT_P2_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P15) | (((val) & 0x1) << 15)) +/* Port 2 Pin # Output Value (14) */ +#define PORT_P2_OUT_P14 (0x1 << 14) +#define PORT_P2_OUT_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P2_OUT_P14_GET(val) ((((val) & PORT_P2_OUT_P14) >> 14) & 0x1) +#define PORT_P2_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P14) | (((val) & 0x1) << 14)) +/* Port 2 Pin # Output Value (13) */ +#define PORT_P2_OUT_P13 (0x1 << 13) +#define PORT_P2_OUT_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P2_OUT_P13_GET(val) ((((val) & PORT_P2_OUT_P13) >> 13) & 0x1) +#define PORT_P2_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P13) | (((val) & 0x1) << 13)) +/* Port 2 Pin # Output Value (12) */ +#define PORT_P2_OUT_P12 (0x1 << 12) +#define PORT_P2_OUT_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P2_OUT_P12_GET(val) ((((val) & PORT_P2_OUT_P12) >> 12) & 0x1) +#define PORT_P2_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P12) | (((val) & 0x1) << 12)) +/* Port 2 Pin # Output Value (11) */ +#define PORT_P2_OUT_P11 (0x1 << 11) +#define PORT_P2_OUT_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P2_OUT_P11_GET(val) ((((val) & PORT_P2_OUT_P11) >> 11) & 0x1) +#define PORT_P2_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P11) | (((val) & 0x1) << 11)) +/* Port 2 Pin # Output Value (10) */ +#define PORT_P2_OUT_P10 (0x1 << 10) +#define PORT_P2_OUT_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P2_OUT_P10_GET(val) ((((val) & PORT_P2_OUT_P10) >> 10) & 0x1) +#define PORT_P2_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P10) | (((val) & 0x1) << 10)) +/* Port 2 Pin # Output Value (9) */ +#define PORT_P2_OUT_P9 (0x1 << 9) +#define PORT_P2_OUT_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P2_OUT_P9_GET(val) ((((val) & PORT_P2_OUT_P9) >> 9) & 0x1) +#define PORT_P2_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P9) | (((val) & 0x1) << 9)) +/* Port 2 Pin # Output Value (8) */ +#define PORT_P2_OUT_P8 (0x1 << 8) +#define PORT_P2_OUT_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P2_OUT_P8_GET(val) ((((val) & PORT_P2_OUT_P8) >> 8) & 0x1) +#define PORT_P2_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P8) | (((val) & 0x1) << 8)) +/* Port 2 Pin # Output Value (7) */ +#define PORT_P2_OUT_P7 (0x1 << 7) +#define PORT_P2_OUT_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P2_OUT_P7_GET(val) ((((val) & PORT_P2_OUT_P7) >> 7) & 0x1) +#define PORT_P2_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P7) | (((val) & 0x1) << 7)) +/* Port 2 Pin # Output Value (6) */ +#define PORT_P2_OUT_P6 (0x1 << 6) +#define PORT_P2_OUT_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P2_OUT_P6_GET(val) ((((val) & PORT_P2_OUT_P6) >> 6) & 0x1) +#define PORT_P2_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P6) | (((val) & 0x1) << 6)) +/* Port 2 Pin # Output Value (5) */ +#define PORT_P2_OUT_P5 (0x1 << 5) +#define PORT_P2_OUT_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P2_OUT_P5_GET(val) ((((val) & PORT_P2_OUT_P5) >> 5) & 0x1) +#define PORT_P2_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P5) | (((val) & 0x1) << 5)) +/* Port 2 Pin # Output Value (4) */ +#define PORT_P2_OUT_P4 (0x1 << 4) +#define PORT_P2_OUT_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P2_OUT_P4_GET(val) ((((val) & PORT_P2_OUT_P4) >> 4) & 0x1) +#define PORT_P2_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P4) | (((val) & 0x1) << 4)) +/* Port 2 Pin # Output Value (3) */ +#define PORT_P2_OUT_P3 (0x1 << 3) +#define PORT_P2_OUT_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P2_OUT_P3_GET(val) ((((val) & PORT_P2_OUT_P3) >> 3) & 0x1) +#define PORT_P2_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P3) | (((val) & 0x1) << 3)) +/* Port 2 Pin # Output Value (2) */ +#define PORT_P2_OUT_P2 (0x1 << 2) +#define PORT_P2_OUT_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P2_OUT_P2_GET(val) ((((val) & PORT_P2_OUT_P2) >> 2) & 0x1) +#define PORT_P2_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P2) | (((val) & 0x1) << 2)) +/* Port 2 Pin # Output Value (1) */ +#define PORT_P2_OUT_P1 (0x1 << 1) +#define PORT_P2_OUT_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P2_OUT_P1_GET(val) ((((val) & PORT_P2_OUT_P1) >> 1) & 0x1) +#define PORT_P2_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P1) | (((val) & 0x1) << 1)) +/* Port 2 Pin # Output Value (0) */ +#define PORT_P2_OUT_P0 (0x1) +#define PORT_P2_OUT_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P2_OUT_P0_GET(val) ((((val) & PORT_P2_OUT_P0) >> 0) & 0x1) +#define PORT_P2_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 2 Data Input Register + ******************************************************************************/ + +/* Port 2 Pin # Latched Input Value (19) */ +#define PORT_P2_IN_P19 (0x1 << 19) +#define PORT_P2_IN_P19_GET(val) ((((val) & PORT_P2_IN_P19) >> 19) & 0x1) +/* Port 2 Pin # Latched Input Value (18) */ +#define PORT_P2_IN_P18 (0x1 << 18) +#define PORT_P2_IN_P18_GET(val) ((((val) & PORT_P2_IN_P18) >> 18) & 0x1) +/* Port 2 Pin # Latched Input Value (17) */ +#define PORT_P2_IN_P17 (0x1 << 17) +#define PORT_P2_IN_P17_GET(val) ((((val) & PORT_P2_IN_P17) >> 17) & 0x1) +/* Port 2 Pin # Latched Input Value (16) */ +#define PORT_P2_IN_P16 (0x1 << 16) +#define PORT_P2_IN_P16_GET(val) ((((val) & PORT_P2_IN_P16) >> 16) & 0x1) +/* Port 2 Pin # Latched Input Value (15) */ +#define PORT_P2_IN_P15 (0x1 << 15) +#define PORT_P2_IN_P15_GET(val) ((((val) & PORT_P2_IN_P15) >> 15) & 0x1) +/* Port 2 Pin # Latched Input Value (14) */ +#define PORT_P2_IN_P14 (0x1 << 14) +#define PORT_P2_IN_P14_GET(val) ((((val) & PORT_P2_IN_P14) >> 14) & 0x1) +/* Port 2 Pin # Latched Input Value (13) */ +#define PORT_P2_IN_P13 (0x1 << 13) +#define PORT_P2_IN_P13_GET(val) ((((val) & PORT_P2_IN_P13) >> 13) & 0x1) +/* Port 2 Pin # Latched Input Value (12) */ +#define PORT_P2_IN_P12 (0x1 << 12) +#define PORT_P2_IN_P12_GET(val) ((((val) & PORT_P2_IN_P12) >> 12) & 0x1) +/* Port 2 Pin # Latched Input Value (11) */ +#define PORT_P2_IN_P11 (0x1 << 11) +#define PORT_P2_IN_P11_GET(val) ((((val) & PORT_P2_IN_P11) >> 11) & 0x1) +/* Port 2 Pin # Latched Input Value (10) */ +#define PORT_P2_IN_P10 (0x1 << 10) +#define PORT_P2_IN_P10_GET(val) ((((val) & PORT_P2_IN_P10) >> 10) & 0x1) +/* Port 2 Pin # Latched Input Value (9) */ +#define PORT_P2_IN_P9 (0x1 << 9) +#define PORT_P2_IN_P9_GET(val) ((((val) & PORT_P2_IN_P9) >> 9) & 0x1) +/* Port 2 Pin # Latched Input Value (8) */ +#define PORT_P2_IN_P8 (0x1 << 8) +#define PORT_P2_IN_P8_GET(val) ((((val) & PORT_P2_IN_P8) >> 8) & 0x1) +/* Port 2 Pin # Latched Input Value (7) */ +#define PORT_P2_IN_P7 (0x1 << 7) +#define PORT_P2_IN_P7_GET(val) ((((val) & PORT_P2_IN_P7) >> 7) & 0x1) +/* Port 2 Pin # Latched Input Value (6) */ +#define PORT_P2_IN_P6 (0x1 << 6) +#define PORT_P2_IN_P6_GET(val) ((((val) & PORT_P2_IN_P6) >> 6) & 0x1) +/* Port 2 Pin # Latched Input Value (5) */ +#define PORT_P2_IN_P5 (0x1 << 5) +#define PORT_P2_IN_P5_GET(val) ((((val) & PORT_P2_IN_P5) >> 5) & 0x1) +/* Port 2 Pin # Latched Input Value (4) */ +#define PORT_P2_IN_P4 (0x1 << 4) +#define PORT_P2_IN_P4_GET(val) ((((val) & PORT_P2_IN_P4) >> 4) & 0x1) +/* Port 2 Pin # Latched Input Value (3) */ +#define PORT_P2_IN_P3 (0x1 << 3) +#define PORT_P2_IN_P3_GET(val) ((((val) & PORT_P2_IN_P3) >> 3) & 0x1) +/* Port 2 Pin # Latched Input Value (2) */ +#define PORT_P2_IN_P2 (0x1 << 2) +#define PORT_P2_IN_P2_GET(val) ((((val) & PORT_P2_IN_P2) >> 2) & 0x1) +/* Port 2 Pin # Latched Input Value (1) */ +#define PORT_P2_IN_P1 (0x1 << 1) +#define PORT_P2_IN_P1_GET(val) ((((val) & PORT_P2_IN_P1) >> 1) & 0x1) +/* Port 2 Pin # Latched Input Value (0) */ +#define PORT_P2_IN_P0 (0x1) +#define PORT_P2_IN_P0_GET(val) ((((val) & PORT_P2_IN_P0) >> 0) & 0x1) + +/******************************************************************************* + * Port 2 Direction Register + ******************************************************************************/ + +/* Port 2 Pin #Direction Control (19) */ +#define PORT_P2_DIR_P19 (0x1 << 19) +#define PORT_P2_DIR_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P2_DIR_P19_GET(val) ((((val) & PORT_P2_DIR_P19) >> 19) & 0x1) +#define PORT_P2_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P19) | (((val) & 0x1) << 19)) +/* Port 2 Pin #Direction Control (18) */ +#define PORT_P2_DIR_P18 (0x1 << 18) +#define PORT_P2_DIR_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P2_DIR_P18_GET(val) ((((val) & PORT_P2_DIR_P18) >> 18) & 0x1) +#define PORT_P2_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P18) | (((val) & 0x1) << 18)) +/* Port 2 Pin #Direction Control (17) */ +#define PORT_P2_DIR_P17 (0x1 << 17) +#define PORT_P2_DIR_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P2_DIR_P17_GET(val) ((((val) & PORT_P2_DIR_P17) >> 17) & 0x1) +#define PORT_P2_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P17) | (((val) & 0x1) << 17)) +/* Port 2 Pin #Direction Control (16) */ +#define PORT_P2_DIR_P16 (0x1 << 16) +#define PORT_P2_DIR_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P2_DIR_P16_GET(val) ((((val) & PORT_P2_DIR_P16) >> 16) & 0x1) +#define PORT_P2_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P16) | (((val) & 0x1) << 16)) +/* Port 2 Pin #Direction Control (15) */ +#define PORT_P2_DIR_P15 (0x1 << 15) +#define PORT_P2_DIR_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P2_DIR_P15_GET(val) ((((val) & PORT_P2_DIR_P15) >> 15) & 0x1) +#define PORT_P2_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P15) | (((val) & 0x1) << 15)) +/* Port 2 Pin #Direction Control (14) */ +#define PORT_P2_DIR_P14 (0x1 << 14) +#define PORT_P2_DIR_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P2_DIR_P14_GET(val) ((((val) & PORT_P2_DIR_P14) >> 14) & 0x1) +#define PORT_P2_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P14) | (((val) & 0x1) << 14)) +/* Port 2 Pin #Direction Control (13) */ +#define PORT_P2_DIR_P13 (0x1 << 13) +#define PORT_P2_DIR_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P2_DIR_P13_GET(val) ((((val) & PORT_P2_DIR_P13) >> 13) & 0x1) +#define PORT_P2_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P13) | (((val) & 0x1) << 13)) +/* Port 2 Pin #Direction Control (12) */ +#define PORT_P2_DIR_P12 (0x1 << 12) +#define PORT_P2_DIR_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P2_DIR_P12_GET(val) ((((val) & PORT_P2_DIR_P12) >> 12) & 0x1) +#define PORT_P2_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P12) | (((val) & 0x1) << 12)) +/* Port 2 Pin #Direction Control (11) */ +#define PORT_P2_DIR_P11 (0x1 << 11) +#define PORT_P2_DIR_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P2_DIR_P11_GET(val) ((((val) & PORT_P2_DIR_P11) >> 11) & 0x1) +#define PORT_P2_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P11) | (((val) & 0x1) << 11)) +/* Port 2 Pin #Direction Control (10) */ +#define PORT_P2_DIR_P10 (0x1 << 10) +#define PORT_P2_DIR_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P2_DIR_P10_GET(val) ((((val) & PORT_P2_DIR_P10) >> 10) & 0x1) +#define PORT_P2_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P10) | (((val) & 0x1) << 10)) +/* Port 2 Pin #Direction Control (9) */ +#define PORT_P2_DIR_P9 (0x1 << 9) +#define PORT_P2_DIR_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P2_DIR_P9_GET(val) ((((val) & PORT_P2_DIR_P9) >> 9) & 0x1) +#define PORT_P2_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P9) | (((val) & 0x1) << 9)) +/* Port 2 Pin #Direction Control (8) */ +#define PORT_P2_DIR_P8 (0x1 << 8) +#define PORT_P2_DIR_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P2_DIR_P8_GET(val) ((((val) & PORT_P2_DIR_P8) >> 8) & 0x1) +#define PORT_P2_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P8) | (((val) & 0x1) << 8)) +/* Port 2 Pin #Direction Control (7) */ +#define PORT_P2_DIR_P7 (0x1 << 7) +#define PORT_P2_DIR_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P2_DIR_P7_GET(val) ((((val) & PORT_P2_DIR_P7) >> 7) & 0x1) +#define PORT_P2_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P7) | (((val) & 0x1) << 7)) +/* Port 2 Pin #Direction Control (6) */ +#define PORT_P2_DIR_P6 (0x1 << 6) +#define PORT_P2_DIR_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P2_DIR_P6_GET(val) ((((val) & PORT_P2_DIR_P6) >> 6) & 0x1) +#define PORT_P2_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P6) | (((val) & 0x1) << 6)) +/* Port 2 Pin #Direction Control (5) */ +#define PORT_P2_DIR_P5 (0x1 << 5) +#define PORT_P2_DIR_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P2_DIR_P5_GET(val) ((((val) & PORT_P2_DIR_P5) >> 5) & 0x1) +#define PORT_P2_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P5) | (((val) & 0x1) << 5)) +/* Port 2 Pin #Direction Control (4) */ +#define PORT_P2_DIR_P4 (0x1 << 4) +#define PORT_P2_DIR_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P2_DIR_P4_GET(val) ((((val) & PORT_P2_DIR_P4) >> 4) & 0x1) +#define PORT_P2_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P4) | (((val) & 0x1) << 4)) +/* Port 2 Pin #Direction Control (3) */ +#define PORT_P2_DIR_P3 (0x1 << 3) +#define PORT_P2_DIR_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P2_DIR_P3_GET(val) ((((val) & PORT_P2_DIR_P3) >> 3) & 0x1) +#define PORT_P2_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P3) | (((val) & 0x1) << 3)) +/* Port 2 Pin #Direction Control (2) */ +#define PORT_P2_DIR_P2 (0x1 << 2) +#define PORT_P2_DIR_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P2_DIR_P2_GET(val) ((((val) & PORT_P2_DIR_P2) >> 2) & 0x1) +#define PORT_P2_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P2) | (((val) & 0x1) << 2)) +/* Port 2 Pin #Direction Control (1) */ +#define PORT_P2_DIR_P1 (0x1 << 1) +#define PORT_P2_DIR_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P2_DIR_P1_GET(val) ((((val) & PORT_P2_DIR_P1) >> 1) & 0x1) +#define PORT_P2_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P1) | (((val) & 0x1) << 1)) +/* Port 2 Pin #Direction Control (0) */ +#define PORT_P2_DIR_P0 (0x1) +#define PORT_P2_DIR_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P2_DIR_P0_GET(val) ((((val) & PORT_P2_DIR_P0) >> 0) & 0x1) +#define PORT_P2_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 2 Alternate Function Select Register 0 + ******************************************************************************/ + +/* Alternate Function at Port 2 Bit # (19) */ +#define PORT_P2_ALTSEL0_P19 (0x1 << 19) +#define PORT_P2_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P2_ALTSEL0_P19_GET(val) ((((val) & PORT_P2_ALTSEL0_P19) >> 19) & 0x1) +#define PORT_P2_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P19) | (((val) & 0x1) << 19)) +/* Alternate Function at Port 2 Bit # (18) */ +#define PORT_P2_ALTSEL0_P18 (0x1 << 18) +#define PORT_P2_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P2_ALTSEL0_P18_GET(val) ((((val) & PORT_P2_ALTSEL0_P18) >> 18) & 0x1) +#define PORT_P2_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P18) | (((val) & 0x1) << 18)) +/* Alternate Function at Port 2 Bit # (17) */ +#define PORT_P2_ALTSEL0_P17 (0x1 << 17) +#define PORT_P2_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P2_ALTSEL0_P17_GET(val) ((((val) & PORT_P2_ALTSEL0_P17) >> 17) & 0x1) +#define PORT_P2_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P17) | (((val) & 0x1) << 17)) +/* Alternate Function at Port 2 Bit # (16) */ +#define PORT_P2_ALTSEL0_P16 (0x1 << 16) +#define PORT_P2_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P2_ALTSEL0_P16_GET(val) ((((val) & PORT_P2_ALTSEL0_P16) >> 16) & 0x1) +#define PORT_P2_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P16) | (((val) & 0x1) << 16)) +/* Alternate Function at Port 2 Bit # (15) */ +#define PORT_P2_ALTSEL0_P15 (0x1 << 15) +#define PORT_P2_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P2_ALTSEL0_P15_GET(val) ((((val) & PORT_P2_ALTSEL0_P15) >> 15) & 0x1) +#define PORT_P2_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P15) | (((val) & 0x1) << 15)) +/* Alternate Function at Port 2 Bit # (14) */ +#define PORT_P2_ALTSEL0_P14 (0x1 << 14) +#define PORT_P2_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P2_ALTSEL0_P14_GET(val) ((((val) & PORT_P2_ALTSEL0_P14) >> 14) & 0x1) +#define PORT_P2_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P14) | (((val) & 0x1) << 14)) +/* Alternate Function at Port 2 Bit # (13) */ +#define PORT_P2_ALTSEL0_P13 (0x1 << 13) +#define PORT_P2_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P2_ALTSEL0_P13_GET(val) ((((val) & PORT_P2_ALTSEL0_P13) >> 13) & 0x1) +#define PORT_P2_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P13) | (((val) & 0x1) << 13)) +/* Alternate Function at Port 2 Bit # (12) */ +#define PORT_P2_ALTSEL0_P12 (0x1 << 12) +#define PORT_P2_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P2_ALTSEL0_P12_GET(val) ((((val) & PORT_P2_ALTSEL0_P12) >> 12) & 0x1) +#define PORT_P2_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P12) | (((val) & 0x1) << 12)) +/* Alternate Function at Port 2 Bit # (11) */ +#define PORT_P2_ALTSEL0_P11 (0x1 << 11) +#define PORT_P2_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P2_ALTSEL0_P11_GET(val) ((((val) & PORT_P2_ALTSEL0_P11) >> 11) & 0x1) +#define PORT_P2_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P11) | (((val) & 0x1) << 11)) +/* Alternate Function at Port 2 Bit # (10) */ +#define PORT_P2_ALTSEL0_P10 (0x1 << 10) +#define PORT_P2_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P2_ALTSEL0_P10_GET(val) ((((val) & PORT_P2_ALTSEL0_P10) >> 10) & 0x1) +#define PORT_P2_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P10) | (((val) & 0x1) << 10)) +/* Alternate Function at Port 2 Bit # (9) */ +#define PORT_P2_ALTSEL0_P9 (0x1 << 9) +#define PORT_P2_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P2_ALTSEL0_P9_GET(val) ((((val) & PORT_P2_ALTSEL0_P9) >> 9) & 0x1) +#define PORT_P2_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P9) | (((val) & 0x1) << 9)) +/* Alternate Function at Port 2 Bit # (8) */ +#define PORT_P2_ALTSEL0_P8 (0x1 << 8) +#define PORT_P2_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P2_ALTSEL0_P8_GET(val) ((((val) & PORT_P2_ALTSEL0_P8) >> 8) & 0x1) +#define PORT_P2_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P8) | (((val) & 0x1) << 8)) +/* Alternate Function at Port 2 Bit # (7) */ +#define PORT_P2_ALTSEL0_P7 (0x1 << 7) +#define PORT_P2_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P2_ALTSEL0_P7_GET(val) ((((val) & PORT_P2_ALTSEL0_P7) >> 7) & 0x1) +#define PORT_P2_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P7) | (((val) & 0x1) << 7)) +/* Alternate Function at Port 2 Bit # (6) */ +#define PORT_P2_ALTSEL0_P6 (0x1 << 6) +#define PORT_P2_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P2_ALTSEL0_P6_GET(val) ((((val) & PORT_P2_ALTSEL0_P6) >> 6) & 0x1) +#define PORT_P2_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P6) | (((val) & 0x1) << 6)) +/* Alternate Function at Port 2 Bit # (5) */ +#define PORT_P2_ALTSEL0_P5 (0x1 << 5) +#define PORT_P2_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P2_ALTSEL0_P5_GET(val) ((((val) & PORT_P2_ALTSEL0_P5) >> 5) & 0x1) +#define PORT_P2_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P5) | (((val) & 0x1) << 5)) +/* Alternate Function at Port 2 Bit # (4) */ +#define PORT_P2_ALTSEL0_P4 (0x1 << 4) +#define PORT_P2_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P2_ALTSEL0_P4_GET(val) ((((val) & PORT_P2_ALTSEL0_P4) >> 4) & 0x1) +#define PORT_P2_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P4) | (((val) & 0x1) << 4)) +/* Alternate Function at Port 2 Bit # (3) */ +#define PORT_P2_ALTSEL0_P3 (0x1 << 3) +#define PORT_P2_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P2_ALTSEL0_P3_GET(val) ((((val) & PORT_P2_ALTSEL0_P3) >> 3) & 0x1) +#define PORT_P2_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P3) | (((val) & 0x1) << 3)) +/* Alternate Function at Port 2 Bit # (2) */ +#define PORT_P2_ALTSEL0_P2 (0x1 << 2) +#define PORT_P2_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P2_ALTSEL0_P2_GET(val) ((((val) & PORT_P2_ALTSEL0_P2) >> 2) & 0x1) +#define PORT_P2_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P2) | (((val) & 0x1) << 2)) +/* Alternate Function at Port 2 Bit # (1) */ +#define PORT_P2_ALTSEL0_P1 (0x1 << 1) +#define PORT_P2_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P2_ALTSEL0_P1_GET(val) ((((val) & PORT_P2_ALTSEL0_P1) >> 1) & 0x1) +#define PORT_P2_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P1) | (((val) & 0x1) << 1)) +/* Alternate Function at Port 2 Bit # (0) */ +#define PORT_P2_ALTSEL0_P0 (0x1) +#define PORT_P2_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P2_ALTSEL0_P0_GET(val) ((((val) & PORT_P2_ALTSEL0_P0) >> 0) & 0x1) +#define PORT_P2_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 2 Pull Up Device Enable Register + ******************************************************************************/ + +/* Pull Up Device Enable at Port 2 Bit # (19) */ +#define PORT_P2_PUEN_P19 (0x1 << 19) +#define PORT_P2_PUEN_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P2_PUEN_P19_GET(val) ((((val) & PORT_P2_PUEN_P19) >> 19) & 0x1) +#define PORT_P2_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P19) | (((val) & 0x1) << 19)) +/* Pull Up Device Enable at Port 2 Bit # (18) */ +#define PORT_P2_PUEN_P18 (0x1 << 18) +#define PORT_P2_PUEN_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P2_PUEN_P18_GET(val) ((((val) & PORT_P2_PUEN_P18) >> 18) & 0x1) +#define PORT_P2_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P18) | (((val) & 0x1) << 18)) +/* Pull Up Device Enable at Port 2 Bit # (17) */ +#define PORT_P2_PUEN_P17 (0x1 << 17) +#define PORT_P2_PUEN_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P2_PUEN_P17_GET(val) ((((val) & PORT_P2_PUEN_P17) >> 17) & 0x1) +#define PORT_P2_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P17) | (((val) & 0x1) << 17)) +/* Pull Up Device Enable at Port 2 Bit # (16) */ +#define PORT_P2_PUEN_P16 (0x1 << 16) +#define PORT_P2_PUEN_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P2_PUEN_P16_GET(val) ((((val) & PORT_P2_PUEN_P16) >> 16) & 0x1) +#define PORT_P2_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P16) | (((val) & 0x1) << 16)) +/* Pull Up Device Enable at Port 2 Bit # (15) */ +#define PORT_P2_PUEN_P15 (0x1 << 15) +#define PORT_P2_PUEN_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P2_PUEN_P15_GET(val) ((((val) & PORT_P2_PUEN_P15) >> 15) & 0x1) +#define PORT_P2_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P15) | (((val) & 0x1) << 15)) +/* Pull Up Device Enable at Port 2 Bit # (14) */ +#define PORT_P2_PUEN_P14 (0x1 << 14) +#define PORT_P2_PUEN_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P2_PUEN_P14_GET(val) ((((val) & PORT_P2_PUEN_P14) >> 14) & 0x1) +#define PORT_P2_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P14) | (((val) & 0x1) << 14)) +/* Pull Up Device Enable at Port 2 Bit # (13) */ +#define PORT_P2_PUEN_P13 (0x1 << 13) +#define PORT_P2_PUEN_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P2_PUEN_P13_GET(val) ((((val) & PORT_P2_PUEN_P13) >> 13) & 0x1) +#define PORT_P2_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P13) | (((val) & 0x1) << 13)) +/* Pull Up Device Enable at Port 2 Bit # (12) */ +#define PORT_P2_PUEN_P12 (0x1 << 12) +#define PORT_P2_PUEN_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P2_PUEN_P12_GET(val) ((((val) & PORT_P2_PUEN_P12) >> 12) & 0x1) +#define PORT_P2_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P12) | (((val) & 0x1) << 12)) +/* Pull Up Device Enable at Port 2 Bit # (11) */ +#define PORT_P2_PUEN_P11 (0x1 << 11) +#define PORT_P2_PUEN_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P2_PUEN_P11_GET(val) ((((val) & PORT_P2_PUEN_P11) >> 11) & 0x1) +#define PORT_P2_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P11) | (((val) & 0x1) << 11)) +/* Pull Up Device Enable at Port 2 Bit # (10) */ +#define PORT_P2_PUEN_P10 (0x1 << 10) +#define PORT_P2_PUEN_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P2_PUEN_P10_GET(val) ((((val) & PORT_P2_PUEN_P10) >> 10) & 0x1) +#define PORT_P2_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P10) | (((val) & 0x1) << 10)) +/* Pull Up Device Enable at Port 2 Bit # (9) */ +#define PORT_P2_PUEN_P9 (0x1 << 9) +#define PORT_P2_PUEN_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P2_PUEN_P9_GET(val) ((((val) & PORT_P2_PUEN_P9) >> 9) & 0x1) +#define PORT_P2_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P9) | (((val) & 0x1) << 9)) +/* Pull Up Device Enable at Port 2 Bit # (8) */ +#define PORT_P2_PUEN_P8 (0x1 << 8) +#define PORT_P2_PUEN_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P2_PUEN_P8_GET(val) ((((val) & PORT_P2_PUEN_P8) >> 8) & 0x1) +#define PORT_P2_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P8) | (((val) & 0x1) << 8)) +/* Pull Up Device Enable at Port 2 Bit # (7) */ +#define PORT_P2_PUEN_P7 (0x1 << 7) +#define PORT_P2_PUEN_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P2_PUEN_P7_GET(val) ((((val) & PORT_P2_PUEN_P7) >> 7) & 0x1) +#define PORT_P2_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P7) | (((val) & 0x1) << 7)) +/* Pull Up Device Enable at Port 2 Bit # (6) */ +#define PORT_P2_PUEN_P6 (0x1 << 6) +#define PORT_P2_PUEN_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P2_PUEN_P6_GET(val) ((((val) & PORT_P2_PUEN_P6) >> 6) & 0x1) +#define PORT_P2_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P6) | (((val) & 0x1) << 6)) +/* Pull Up Device Enable at Port 2 Bit # (5) */ +#define PORT_P2_PUEN_P5 (0x1 << 5) +#define PORT_P2_PUEN_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P2_PUEN_P5_GET(val) ((((val) & PORT_P2_PUEN_P5) >> 5) & 0x1) +#define PORT_P2_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P5) | (((val) & 0x1) << 5)) +/* Pull Up Device Enable at Port 2 Bit # (4) */ +#define PORT_P2_PUEN_P4 (0x1 << 4) +#define PORT_P2_PUEN_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P2_PUEN_P4_GET(val) ((((val) & PORT_P2_PUEN_P4) >> 4) & 0x1) +#define PORT_P2_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P4) | (((val) & 0x1) << 4)) +/* Pull Up Device Enable at Port 2 Bit # (3) */ +#define PORT_P2_PUEN_P3 (0x1 << 3) +#define PORT_P2_PUEN_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P2_PUEN_P3_GET(val) ((((val) & PORT_P2_PUEN_P3) >> 3) & 0x1) +#define PORT_P2_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P3) | (((val) & 0x1) << 3)) +/* Pull Up Device Enable at Port 2 Bit # (2) */ +#define PORT_P2_PUEN_P2 (0x1 << 2) +#define PORT_P2_PUEN_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P2_PUEN_P2_GET(val) ((((val) & PORT_P2_PUEN_P2) >> 2) & 0x1) +#define PORT_P2_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P2) | (((val) & 0x1) << 2)) +/* Pull Up Device Enable at Port 2 Bit # (1) */ +#define PORT_P2_PUEN_P1 (0x1 << 1) +#define PORT_P2_PUEN_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P2_PUEN_P1_GET(val) ((((val) & PORT_P2_PUEN_P1) >> 1) & 0x1) +#define PORT_P2_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P1) | (((val) & 0x1) << 1)) +/* Pull Up Device Enable at Port 2 Bit # (0) */ +#define PORT_P2_PUEN_P0 (0x1) +#define PORT_P2_PUEN_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P2_PUEN_P0_GET(val) ((((val) & PORT_P2_PUEN_P0) >> 0) & 0x1) +#define PORT_P2_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 3 Data Output Register + ******************************************************************************/ + +/* Port 3 Pin # Output Value (19) */ +#define PORT_P3_OUT_P19 (0x1 << 19) +#define PORT_P3_OUT_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P3_OUT_P19_GET(val) ((((val) & PORT_P3_OUT_P19) >> 19) & 0x1) +#define PORT_P3_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P19) | (((val) & 0x1) << 19)) +/* Port 3 Pin # Output Value (18) */ +#define PORT_P3_OUT_P18 (0x1 << 18) +#define PORT_P3_OUT_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P3_OUT_P18_GET(val) ((((val) & PORT_P3_OUT_P18) >> 18) & 0x1) +#define PORT_P3_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P18) | (((val) & 0x1) << 18)) +/* Port 3 Pin # Output Value (17) */ +#define PORT_P3_OUT_P17 (0x1 << 17) +#define PORT_P3_OUT_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P3_OUT_P17_GET(val) ((((val) & PORT_P3_OUT_P17) >> 17) & 0x1) +#define PORT_P3_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P17) | (((val) & 0x1) << 17)) +/* Port 3 Pin # Output Value (16) */ +#define PORT_P3_OUT_P16 (0x1 << 16) +#define PORT_P3_OUT_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P3_OUT_P16_GET(val) ((((val) & PORT_P3_OUT_P16) >> 16) & 0x1) +#define PORT_P3_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P16) | (((val) & 0x1) << 16)) +/* Port 3 Pin # Output Value (15) */ +#define PORT_P3_OUT_P15 (0x1 << 15) +#define PORT_P3_OUT_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P3_OUT_P15_GET(val) ((((val) & PORT_P3_OUT_P15) >> 15) & 0x1) +#define PORT_P3_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P15) | (((val) & 0x1) << 15)) +/* Port 3 Pin # Output Value (14) */ +#define PORT_P3_OUT_P14 (0x1 << 14) +#define PORT_P3_OUT_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P3_OUT_P14_GET(val) ((((val) & PORT_P3_OUT_P14) >> 14) & 0x1) +#define PORT_P3_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P14) | (((val) & 0x1) << 14)) +/* Port 3 Pin # Output Value (13) */ +#define PORT_P3_OUT_P13 (0x1 << 13) +#define PORT_P3_OUT_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P3_OUT_P13_GET(val) ((((val) & PORT_P3_OUT_P13) >> 13) & 0x1) +#define PORT_P3_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P13) | (((val) & 0x1) << 13)) +/* Port 3 Pin # Output Value (12) */ +#define PORT_P3_OUT_P12 (0x1 << 12) +#define PORT_P3_OUT_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P3_OUT_P12_GET(val) ((((val) & PORT_P3_OUT_P12) >> 12) & 0x1) +#define PORT_P3_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P12) | (((val) & 0x1) << 12)) +/* Port 3 Pin # Output Value (11) */ +#define PORT_P3_OUT_P11 (0x1 << 11) +#define PORT_P3_OUT_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P3_OUT_P11_GET(val) ((((val) & PORT_P3_OUT_P11) >> 11) & 0x1) +#define PORT_P3_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P11) | (((val) & 0x1) << 11)) +/* Port 3 Pin # Output Value (10) */ +#define PORT_P3_OUT_P10 (0x1 << 10) +#define PORT_P3_OUT_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P3_OUT_P10_GET(val) ((((val) & PORT_P3_OUT_P10) >> 10) & 0x1) +#define PORT_P3_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P10) | (((val) & 0x1) << 10)) +/* Port 3 Pin # Output Value (9) */ +#define PORT_P3_OUT_P9 (0x1 << 9) +#define PORT_P3_OUT_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P3_OUT_P9_GET(val) ((((val) & PORT_P3_OUT_P9) >> 9) & 0x1) +#define PORT_P3_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P9) | (((val) & 0x1) << 9)) +/* Port 3 Pin # Output Value (8) */ +#define PORT_P3_OUT_P8 (0x1 << 8) +#define PORT_P3_OUT_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P3_OUT_P8_GET(val) ((((val) & PORT_P3_OUT_P8) >> 8) & 0x1) +#define PORT_P3_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P8) | (((val) & 0x1) << 8)) +/* Port 3 Pin # Output Value (7) */ +#define PORT_P3_OUT_P7 (0x1 << 7) +#define PORT_P3_OUT_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P3_OUT_P7_GET(val) ((((val) & PORT_P3_OUT_P7) >> 7) & 0x1) +#define PORT_P3_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P7) | (((val) & 0x1) << 7)) +/* Port 3 Pin # Output Value (6) */ +#define PORT_P3_OUT_P6 (0x1 << 6) +#define PORT_P3_OUT_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P3_OUT_P6_GET(val) ((((val) & PORT_P3_OUT_P6) >> 6) & 0x1) +#define PORT_P3_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P6) | (((val) & 0x1) << 6)) +/* Port 3 Pin # Output Value (5) */ +#define PORT_P3_OUT_P5 (0x1 << 5) +#define PORT_P3_OUT_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P3_OUT_P5_GET(val) ((((val) & PORT_P3_OUT_P5) >> 5) & 0x1) +#define PORT_P3_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P5) | (((val) & 0x1) << 5)) +/* Port 3 Pin # Output Value (4) */ +#define PORT_P3_OUT_P4 (0x1 << 4) +#define PORT_P3_OUT_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P3_OUT_P4_GET(val) ((((val) & PORT_P3_OUT_P4) >> 4) & 0x1) +#define PORT_P3_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P4) | (((val) & 0x1) << 4)) +/* Port 3 Pin # Output Value (3) */ +#define PORT_P3_OUT_P3 (0x1 << 3) +#define PORT_P3_OUT_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P3_OUT_P3_GET(val) ((((val) & PORT_P3_OUT_P3) >> 3) & 0x1) +#define PORT_P3_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P3) | (((val) & 0x1) << 3)) +/* Port 3 Pin # Output Value (2) */ +#define PORT_P3_OUT_P2 (0x1 << 2) +#define PORT_P3_OUT_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P3_OUT_P2_GET(val) ((((val) & PORT_P3_OUT_P2) >> 2) & 0x1) +#define PORT_P3_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P2) | (((val) & 0x1) << 2)) +/* Port 3 Pin # Output Value (1) */ +#define PORT_P3_OUT_P1 (0x1 << 1) +#define PORT_P3_OUT_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P3_OUT_P1_GET(val) ((((val) & PORT_P3_OUT_P1) >> 1) & 0x1) +#define PORT_P3_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P1) | (((val) & 0x1) << 1)) +/* Port 3 Pin # Output Value (0) */ +#define PORT_P3_OUT_P0 (0x1) +#define PORT_P3_OUT_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P3_OUT_P0_GET(val) ((((val) & PORT_P3_OUT_P0) >> 0) & 0x1) +#define PORT_P3_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 3 Data Input Register + ******************************************************************************/ + +/* Port 3 Pin # Latched Input Value (19) */ +#define PORT_P3_IN_P19 (0x1 << 19) +#define PORT_P3_IN_P19_GET(val) ((((val) & PORT_P3_IN_P19) >> 19) & 0x1) +/* Port 3 Pin # Latched Input Value (18) */ +#define PORT_P3_IN_P18 (0x1 << 18) +#define PORT_P3_IN_P18_GET(val) ((((val) & PORT_P3_IN_P18) >> 18) & 0x1) +/* Port 3 Pin # Latched Input Value (17) */ +#define PORT_P3_IN_P17 (0x1 << 17) +#define PORT_P3_IN_P17_GET(val) ((((val) & PORT_P3_IN_P17) >> 17) & 0x1) +/* Port 3 Pin # Latched Input Value (16) */ +#define PORT_P3_IN_P16 (0x1 << 16) +#define PORT_P3_IN_P16_GET(val) ((((val) & PORT_P3_IN_P16) >> 16) & 0x1) +/* Port 3 Pin # Latched Input Value (15) */ +#define PORT_P3_IN_P15 (0x1 << 15) +#define PORT_P3_IN_P15_GET(val) ((((val) & PORT_P3_IN_P15) >> 15) & 0x1) +/* Port 3 Pin # Latched Input Value (14) */ +#define PORT_P3_IN_P14 (0x1 << 14) +#define PORT_P3_IN_P14_GET(val) ((((val) & PORT_P3_IN_P14) >> 14) & 0x1) +/* Port 3 Pin # Latched Input Value (13) */ +#define PORT_P3_IN_P13 (0x1 << 13) +#define PORT_P3_IN_P13_GET(val) ((((val) & PORT_P3_IN_P13) >> 13) & 0x1) +/* Port 3 Pin # Latched Input Value (12) */ +#define PORT_P3_IN_P12 (0x1 << 12) +#define PORT_P3_IN_P12_GET(val) ((((val) & PORT_P3_IN_P12) >> 12) & 0x1) +/* Port 3 Pin # Latched Input Value (11) */ +#define PORT_P3_IN_P11 (0x1 << 11) +#define PORT_P3_IN_P11_GET(val) ((((val) & PORT_P3_IN_P11) >> 11) & 0x1) +/* Port 3 Pin # Latched Input Value (10) */ +#define PORT_P3_IN_P10 (0x1 << 10) +#define PORT_P3_IN_P10_GET(val) ((((val) & PORT_P3_IN_P10) >> 10) & 0x1) +/* Port 3 Pin # Latched Input Value (9) */ +#define PORT_P3_IN_P9 (0x1 << 9) +#define PORT_P3_IN_P9_GET(val) ((((val) & PORT_P3_IN_P9) >> 9) & 0x1) +/* Port 3 Pin # Latched Input Value (8) */ +#define PORT_P3_IN_P8 (0x1 << 8) +#define PORT_P3_IN_P8_GET(val) ((((val) & PORT_P3_IN_P8) >> 8) & 0x1) +/* Port 3 Pin # Latched Input Value (7) */ +#define PORT_P3_IN_P7 (0x1 << 7) +#define PORT_P3_IN_P7_GET(val) ((((val) & PORT_P3_IN_P7) >> 7) & 0x1) +/* Port 3 Pin # Latched Input Value (6) */ +#define PORT_P3_IN_P6 (0x1 << 6) +#define PORT_P3_IN_P6_GET(val) ((((val) & PORT_P3_IN_P6) >> 6) & 0x1) +/* Port 3 Pin # Latched Input Value (5) */ +#define PORT_P3_IN_P5 (0x1 << 5) +#define PORT_P3_IN_P5_GET(val) ((((val) & PORT_P3_IN_P5) >> 5) & 0x1) +/* Port 3 Pin # Latched Input Value (4) */ +#define PORT_P3_IN_P4 (0x1 << 4) +#define PORT_P3_IN_P4_GET(val) ((((val) & PORT_P3_IN_P4) >> 4) & 0x1) +/* Port 3 Pin # Latched Input Value (3) */ +#define PORT_P3_IN_P3 (0x1 << 3) +#define PORT_P3_IN_P3_GET(val) ((((val) & PORT_P3_IN_P3) >> 3) & 0x1) +/* Port 3 Pin # Latched Input Value (2) */ +#define PORT_P3_IN_P2 (0x1 << 2) +#define PORT_P3_IN_P2_GET(val) ((((val) & PORT_P3_IN_P2) >> 2) & 0x1) +/* Port 3 Pin # Latched Input Value (1) */ +#define PORT_P3_IN_P1 (0x1 << 1) +#define PORT_P3_IN_P1_GET(val) ((((val) & PORT_P3_IN_P1) >> 1) & 0x1) +/* Port 3 Pin # Latched Input Value (0) */ +#define PORT_P3_IN_P0 (0x1) +#define PORT_P3_IN_P0_GET(val) ((((val) & PORT_P3_IN_P0) >> 0) & 0x1) + +/******************************************************************************* + * Port 3 Direction Register + ******************************************************************************/ + +/* Port 3 Pin #Direction Control (19) */ +#define PORT_P3_DIR_P19 (0x1 << 19) +#define PORT_P3_DIR_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P3_DIR_P19_GET(val) ((((val) & PORT_P3_DIR_P19) >> 19) & 0x1) +#define PORT_P3_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P19) | (((val) & 0x1) << 19)) +/* Port 3 Pin #Direction Control (18) */ +#define PORT_P3_DIR_P18 (0x1 << 18) +#define PORT_P3_DIR_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P3_DIR_P18_GET(val) ((((val) & PORT_P3_DIR_P18) >> 18) & 0x1) +#define PORT_P3_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P18) | (((val) & 0x1) << 18)) +/* Port 3 Pin #Direction Control (17) */ +#define PORT_P3_DIR_P17 (0x1 << 17) +#define PORT_P3_DIR_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P3_DIR_P17_GET(val) ((((val) & PORT_P3_DIR_P17) >> 17) & 0x1) +#define PORT_P3_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P17) | (((val) & 0x1) << 17)) +/* Port 3 Pin #Direction Control (16) */ +#define PORT_P3_DIR_P16 (0x1 << 16) +#define PORT_P3_DIR_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P3_DIR_P16_GET(val) ((((val) & PORT_P3_DIR_P16) >> 16) & 0x1) +#define PORT_P3_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P16) | (((val) & 0x1) << 16)) +/* Port 3 Pin #Direction Control (15) */ +#define PORT_P3_DIR_P15 (0x1 << 15) +#define PORT_P3_DIR_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P3_DIR_P15_GET(val) ((((val) & PORT_P3_DIR_P15) >> 15) & 0x1) +#define PORT_P3_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P15) | (((val) & 0x1) << 15)) +/* Port 3 Pin #Direction Control (14) */ +#define PORT_P3_DIR_P14 (0x1 << 14) +#define PORT_P3_DIR_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P3_DIR_P14_GET(val) ((((val) & PORT_P3_DIR_P14) >> 14) & 0x1) +#define PORT_P3_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P14) | (((val) & 0x1) << 14)) +/* Port 3 Pin #Direction Control (13) */ +#define PORT_P3_DIR_P13 (0x1 << 13) +#define PORT_P3_DIR_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P3_DIR_P13_GET(val) ((((val) & PORT_P3_DIR_P13) >> 13) & 0x1) +#define PORT_P3_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P13) | (((val) & 0x1) << 13)) +/* Port 3 Pin #Direction Control (12) */ +#define PORT_P3_DIR_P12 (0x1 << 12) +#define PORT_P3_DIR_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P3_DIR_P12_GET(val) ((((val) & PORT_P3_DIR_P12) >> 12) & 0x1) +#define PORT_P3_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P12) | (((val) & 0x1) << 12)) +/* Port 3 Pin #Direction Control (11) */ +#define PORT_P3_DIR_P11 (0x1 << 11) +#define PORT_P3_DIR_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P3_DIR_P11_GET(val) ((((val) & PORT_P3_DIR_P11) >> 11) & 0x1) +#define PORT_P3_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P11) | (((val) & 0x1) << 11)) +/* Port 3 Pin #Direction Control (10) */ +#define PORT_P3_DIR_P10 (0x1 << 10) +#define PORT_P3_DIR_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P3_DIR_P10_GET(val) ((((val) & PORT_P3_DIR_P10) >> 10) & 0x1) +#define PORT_P3_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P10) | (((val) & 0x1) << 10)) +/* Port 3 Pin #Direction Control (9) */ +#define PORT_P3_DIR_P9 (0x1 << 9) +#define PORT_P3_DIR_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P3_DIR_P9_GET(val) ((((val) & PORT_P3_DIR_P9) >> 9) & 0x1) +#define PORT_P3_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P9) | (((val) & 0x1) << 9)) +/* Port 3 Pin #Direction Control (8) */ +#define PORT_P3_DIR_P8 (0x1 << 8) +#define PORT_P3_DIR_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P3_DIR_P8_GET(val) ((((val) & PORT_P3_DIR_P8) >> 8) & 0x1) +#define PORT_P3_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P8) | (((val) & 0x1) << 8)) +/* Port 3 Pin #Direction Control (7) */ +#define PORT_P3_DIR_P7 (0x1 << 7) +#define PORT_P3_DIR_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P3_DIR_P7_GET(val) ((((val) & PORT_P3_DIR_P7) >> 7) & 0x1) +#define PORT_P3_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P7) | (((val) & 0x1) << 7)) +/* Port 3 Pin #Direction Control (6) */ +#define PORT_P3_DIR_P6 (0x1 << 6) +#define PORT_P3_DIR_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P3_DIR_P6_GET(val) ((((val) & PORT_P3_DIR_P6) >> 6) & 0x1) +#define PORT_P3_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P6) | (((val) & 0x1) << 6)) +/* Port 3 Pin #Direction Control (5) */ +#define PORT_P3_DIR_P5 (0x1 << 5) +#define PORT_P3_DIR_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P3_DIR_P5_GET(val) ((((val) & PORT_P3_DIR_P5) >> 5) & 0x1) +#define PORT_P3_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P5) | (((val) & 0x1) << 5)) +/* Port 3 Pin #Direction Control (4) */ +#define PORT_P3_DIR_P4 (0x1 << 4) +#define PORT_P3_DIR_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P3_DIR_P4_GET(val) ((((val) & PORT_P3_DIR_P4) >> 4) & 0x1) +#define PORT_P3_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P4) | (((val) & 0x1) << 4)) +/* Port 3 Pin #Direction Control (3) */ +#define PORT_P3_DIR_P3 (0x1 << 3) +#define PORT_P3_DIR_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P3_DIR_P3_GET(val) ((((val) & PORT_P3_DIR_P3) >> 3) & 0x1) +#define PORT_P3_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P3) | (((val) & 0x1) << 3)) +/* Port 3 Pin #Direction Control (2) */ +#define PORT_P3_DIR_P2 (0x1 << 2) +#define PORT_P3_DIR_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P3_DIR_P2_GET(val) ((((val) & PORT_P3_DIR_P2) >> 2) & 0x1) +#define PORT_P3_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P2) | (((val) & 0x1) << 2)) +/* Port 3 Pin #Direction Control (1) */ +#define PORT_P3_DIR_P1 (0x1 << 1) +#define PORT_P3_DIR_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P3_DIR_P1_GET(val) ((((val) & PORT_P3_DIR_P1) >> 1) & 0x1) +#define PORT_P3_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P1) | (((val) & 0x1) << 1)) +/* Port 3 Pin #Direction Control (0) */ +#define PORT_P3_DIR_P0 (0x1) +#define PORT_P3_DIR_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P3_DIR_P0_GET(val) ((((val) & PORT_P3_DIR_P0) >> 0) & 0x1) +#define PORT_P3_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 3 Alternate Function Select Register 0 + ******************************************************************************/ + +/* Alternate Function at Port 3 Bit # (19) */ +#define PORT_P3_ALTSEL0_P19 (0x1 << 19) +#define PORT_P3_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P3_ALTSEL0_P19_GET(val) ((((val) & PORT_P3_ALTSEL0_P19) >> 19) & 0x1) +#define PORT_P3_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P19) | (((val) & 0x1) << 19)) +/* Alternate Function at Port 3 Bit # (18) */ +#define PORT_P3_ALTSEL0_P18 (0x1 << 18) +#define PORT_P3_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P3_ALTSEL0_P18_GET(val) ((((val) & PORT_P3_ALTSEL0_P18) >> 18) & 0x1) +#define PORT_P3_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P18) | (((val) & 0x1) << 18)) +/* Alternate Function at Port 3 Bit # (17) */ +#define PORT_P3_ALTSEL0_P17 (0x1 << 17) +#define PORT_P3_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P3_ALTSEL0_P17_GET(val) ((((val) & PORT_P3_ALTSEL0_P17) >> 17) & 0x1) +#define PORT_P3_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P17) | (((val) & 0x1) << 17)) +/* Alternate Function at Port 3 Bit # (16) */ +#define PORT_P3_ALTSEL0_P16 (0x1 << 16) +#define PORT_P3_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P3_ALTSEL0_P16_GET(val) ((((val) & PORT_P3_ALTSEL0_P16) >> 16) & 0x1) +#define PORT_P3_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P16) | (((val) & 0x1) << 16)) +/* Alternate Function at Port 3 Bit # (15) */ +#define PORT_P3_ALTSEL0_P15 (0x1 << 15) +#define PORT_P3_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P3_ALTSEL0_P15_GET(val) ((((val) & PORT_P3_ALTSEL0_P15) >> 15) & 0x1) +#define PORT_P3_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P15) | (((val) & 0x1) << 15)) +/* Alternate Function at Port 3 Bit # (14) */ +#define PORT_P3_ALTSEL0_P14 (0x1 << 14) +#define PORT_P3_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P3_ALTSEL0_P14_GET(val) ((((val) & PORT_P3_ALTSEL0_P14) >> 14) & 0x1) +#define PORT_P3_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P14) | (((val) & 0x1) << 14)) +/* Alternate Function at Port 3 Bit # (13) */ +#define PORT_P3_ALTSEL0_P13 (0x1 << 13) +#define PORT_P3_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P3_ALTSEL0_P13_GET(val) ((((val) & PORT_P3_ALTSEL0_P13) >> 13) & 0x1) +#define PORT_P3_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P13) | (((val) & 0x1) << 13)) +/* Alternate Function at Port 3 Bit # (12) */ +#define PORT_P3_ALTSEL0_P12 (0x1 << 12) +#define PORT_P3_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P3_ALTSEL0_P12_GET(val) ((((val) & PORT_P3_ALTSEL0_P12) >> 12) & 0x1) +#define PORT_P3_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P12) | (((val) & 0x1) << 12)) +/* Alternate Function at Port 3 Bit # (11) */ +#define PORT_P3_ALTSEL0_P11 (0x1 << 11) +#define PORT_P3_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P3_ALTSEL0_P11_GET(val) ((((val) & PORT_P3_ALTSEL0_P11) >> 11) & 0x1) +#define PORT_P3_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P11) | (((val) & 0x1) << 11)) +/* Alternate Function at Port 3 Bit # (10) */ +#define PORT_P3_ALTSEL0_P10 (0x1 << 10) +#define PORT_P3_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P3_ALTSEL0_P10_GET(val) ((((val) & PORT_P3_ALTSEL0_P10) >> 10) & 0x1) +#define PORT_P3_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P10) | (((val) & 0x1) << 10)) +/* Alternate Function at Port 3 Bit # (9) */ +#define PORT_P3_ALTSEL0_P9 (0x1 << 9) +#define PORT_P3_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P3_ALTSEL0_P9_GET(val) ((((val) & PORT_P3_ALTSEL0_P9) >> 9) & 0x1) +#define PORT_P3_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P9) | (((val) & 0x1) << 9)) +/* Alternate Function at Port 3 Bit # (8) */ +#define PORT_P3_ALTSEL0_P8 (0x1 << 8) +#define PORT_P3_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P3_ALTSEL0_P8_GET(val) ((((val) & PORT_P3_ALTSEL0_P8) >> 8) & 0x1) +#define PORT_P3_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P8) | (((val) & 0x1) << 8)) +/* Alternate Function at Port 3 Bit # (7) */ +#define PORT_P3_ALTSEL0_P7 (0x1 << 7) +#define PORT_P3_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P3_ALTSEL0_P7_GET(val) ((((val) & PORT_P3_ALTSEL0_P7) >> 7) & 0x1) +#define PORT_P3_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P7) | (((val) & 0x1) << 7)) +/* Alternate Function at Port 3 Bit # (6) */ +#define PORT_P3_ALTSEL0_P6 (0x1 << 6) +#define PORT_P3_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P3_ALTSEL0_P6_GET(val) ((((val) & PORT_P3_ALTSEL0_P6) >> 6) & 0x1) +#define PORT_P3_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P6) | (((val) & 0x1) << 6)) +/* Alternate Function at Port 3 Bit # (5) */ +#define PORT_P3_ALTSEL0_P5 (0x1 << 5) +#define PORT_P3_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P3_ALTSEL0_P5_GET(val) ((((val) & PORT_P3_ALTSEL0_P5) >> 5) & 0x1) +#define PORT_P3_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P5) | (((val) & 0x1) << 5)) +/* Alternate Function at Port 3 Bit # (4) */ +#define PORT_P3_ALTSEL0_P4 (0x1 << 4) +#define PORT_P3_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P3_ALTSEL0_P4_GET(val) ((((val) & PORT_P3_ALTSEL0_P4) >> 4) & 0x1) +#define PORT_P3_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P4) | (((val) & 0x1) << 4)) +/* Alternate Function at Port 3 Bit # (3) */ +#define PORT_P3_ALTSEL0_P3 (0x1 << 3) +#define PORT_P3_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P3_ALTSEL0_P3_GET(val) ((((val) & PORT_P3_ALTSEL0_P3) >> 3) & 0x1) +#define PORT_P3_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P3) | (((val) & 0x1) << 3)) +/* Alternate Function at Port 3 Bit # (2) */ +#define PORT_P3_ALTSEL0_P2 (0x1 << 2) +#define PORT_P3_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P3_ALTSEL0_P2_GET(val) ((((val) & PORT_P3_ALTSEL0_P2) >> 2) & 0x1) +#define PORT_P3_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P2) | (((val) & 0x1) << 2)) +/* Alternate Function at Port 3 Bit # (1) */ +#define PORT_P3_ALTSEL0_P1 (0x1 << 1) +#define PORT_P3_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P3_ALTSEL0_P1_GET(val) ((((val) & PORT_P3_ALTSEL0_P1) >> 1) & 0x1) +#define PORT_P3_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P1) | (((val) & 0x1) << 1)) +/* Alternate Function at Port 3 Bit # (0) */ +#define PORT_P3_ALTSEL0_P0 (0x1) +#define PORT_P3_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P3_ALTSEL0_P0_GET(val) ((((val) & PORT_P3_ALTSEL0_P0) >> 0) & 0x1) +#define PORT_P3_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 3 Pull Up Device Enable Register + ******************************************************************************/ + +/* Pull Up Device Enable at Port 3 Bit # (19) */ +#define PORT_P3_PUEN_P19 (0x1 << 19) +#define PORT_P3_PUEN_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P3_PUEN_P19_GET(val) ((((val) & PORT_P3_PUEN_P19) >> 19) & 0x1) +#define PORT_P3_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P19) | (((val) & 0x1) << 19)) +/* Pull Up Device Enable at Port 3 Bit # (18) */ +#define PORT_P3_PUEN_P18 (0x1 << 18) +#define PORT_P3_PUEN_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P3_PUEN_P18_GET(val) ((((val) & PORT_P3_PUEN_P18) >> 18) & 0x1) +#define PORT_P3_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P18) | (((val) & 0x1) << 18)) +/* Pull Up Device Enable at Port 3 Bit # (17) */ +#define PORT_P3_PUEN_P17 (0x1 << 17) +#define PORT_P3_PUEN_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P3_PUEN_P17_GET(val) ((((val) & PORT_P3_PUEN_P17) >> 17) & 0x1) +#define PORT_P3_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P17) | (((val) & 0x1) << 17)) +/* Pull Up Device Enable at Port 3 Bit # (16) */ +#define PORT_P3_PUEN_P16 (0x1 << 16) +#define PORT_P3_PUEN_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P3_PUEN_P16_GET(val) ((((val) & PORT_P3_PUEN_P16) >> 16) & 0x1) +#define PORT_P3_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P16) | (((val) & 0x1) << 16)) +/* Pull Up Device Enable at Port 3 Bit # (15) */ +#define PORT_P3_PUEN_P15 (0x1 << 15) +#define PORT_P3_PUEN_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P3_PUEN_P15_GET(val) ((((val) & PORT_P3_PUEN_P15) >> 15) & 0x1) +#define PORT_P3_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P15) | (((val) & 0x1) << 15)) +/* Pull Up Device Enable at Port 3 Bit # (14) */ +#define PORT_P3_PUEN_P14 (0x1 << 14) +#define PORT_P3_PUEN_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P3_PUEN_P14_GET(val) ((((val) & PORT_P3_PUEN_P14) >> 14) & 0x1) +#define PORT_P3_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P14) | (((val) & 0x1) << 14)) +/* Pull Up Device Enable at Port 3 Bit # (13) */ +#define PORT_P3_PUEN_P13 (0x1 << 13) +#define PORT_P3_PUEN_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P3_PUEN_P13_GET(val) ((((val) & PORT_P3_PUEN_P13) >> 13) & 0x1) +#define PORT_P3_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P13) | (((val) & 0x1) << 13)) +/* Pull Up Device Enable at Port 3 Bit # (12) */ +#define PORT_P3_PUEN_P12 (0x1 << 12) +#define PORT_P3_PUEN_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P3_PUEN_P12_GET(val) ((((val) & PORT_P3_PUEN_P12) >> 12) & 0x1) +#define PORT_P3_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P12) | (((val) & 0x1) << 12)) +/* Pull Up Device Enable at Port 3 Bit # (11) */ +#define PORT_P3_PUEN_P11 (0x1 << 11) +#define PORT_P3_PUEN_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P3_PUEN_P11_GET(val) ((((val) & PORT_P3_PUEN_P11) >> 11) & 0x1) +#define PORT_P3_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P11) | (((val) & 0x1) << 11)) +/* Pull Up Device Enable at Port 3 Bit # (10) */ +#define PORT_P3_PUEN_P10 (0x1 << 10) +#define PORT_P3_PUEN_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P3_PUEN_P10_GET(val) ((((val) & PORT_P3_PUEN_P10) >> 10) & 0x1) +#define PORT_P3_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P10) | (((val) & 0x1) << 10)) +/* Pull Up Device Enable at Port 3 Bit # (9) */ +#define PORT_P3_PUEN_P9 (0x1 << 9) +#define PORT_P3_PUEN_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P3_PUEN_P9_GET(val) ((((val) & PORT_P3_PUEN_P9) >> 9) & 0x1) +#define PORT_P3_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P9) | (((val) & 0x1) << 9)) +/* Pull Up Device Enable at Port 3 Bit # (8) */ +#define PORT_P3_PUEN_P8 (0x1 << 8) +#define PORT_P3_PUEN_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P3_PUEN_P8_GET(val) ((((val) & PORT_P3_PUEN_P8) >> 8) & 0x1) +#define PORT_P3_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P8) | (((val) & 0x1) << 8)) +/* Pull Up Device Enable at Port 3 Bit # (7) */ +#define PORT_P3_PUEN_P7 (0x1 << 7) +#define PORT_P3_PUEN_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P3_PUEN_P7_GET(val) ((((val) & PORT_P3_PUEN_P7) >> 7) & 0x1) +#define PORT_P3_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P7) | (((val) & 0x1) << 7)) +/* Pull Up Device Enable at Port 3 Bit # (6) */ +#define PORT_P3_PUEN_P6 (0x1 << 6) +#define PORT_P3_PUEN_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P3_PUEN_P6_GET(val) ((((val) & PORT_P3_PUEN_P6) >> 6) & 0x1) +#define PORT_P3_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P6) | (((val) & 0x1) << 6)) +/* Pull Up Device Enable at Port 3 Bit # (5) */ +#define PORT_P3_PUEN_P5 (0x1 << 5) +#define PORT_P3_PUEN_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P3_PUEN_P5_GET(val) ((((val) & PORT_P3_PUEN_P5) >> 5) & 0x1) +#define PORT_P3_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P5) | (((val) & 0x1) << 5)) +/* Pull Up Device Enable at Port 3 Bit # (4) */ +#define PORT_P3_PUEN_P4 (0x1 << 4) +#define PORT_P3_PUEN_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P3_PUEN_P4_GET(val) ((((val) & PORT_P3_PUEN_P4) >> 4) & 0x1) +#define PORT_P3_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P4) | (((val) & 0x1) << 4)) +/* Pull Up Device Enable at Port 3 Bit # (3) */ +#define PORT_P3_PUEN_P3 (0x1 << 3) +#define PORT_P3_PUEN_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P3_PUEN_P3_GET(val) ((((val) & PORT_P3_PUEN_P3) >> 3) & 0x1) +#define PORT_P3_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P3) | (((val) & 0x1) << 3)) +/* Pull Up Device Enable at Port 3 Bit # (2) */ +#define PORT_P3_PUEN_P2 (0x1 << 2) +#define PORT_P3_PUEN_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P3_PUEN_P2_GET(val) ((((val) & PORT_P3_PUEN_P2) >> 2) & 0x1) +#define PORT_P3_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P2) | (((val) & 0x1) << 2)) +/* Pull Up Device Enable at Port 3 Bit # (1) */ +#define PORT_P3_PUEN_P1 (0x1 << 1) +#define PORT_P3_PUEN_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P3_PUEN_P1_GET(val) ((((val) & PORT_P3_PUEN_P1) >> 1) & 0x1) +#define PORT_P3_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P1) | (((val) & 0x1) << 1)) +/* Pull Up Device Enable at Port 3 Bit # (0) */ +#define PORT_P3_PUEN_P0 (0x1) +#define PORT_P3_PUEN_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P3_PUEN_P0_GET(val) ((((val) & PORT_P3_PUEN_P0) >> 0) & 0x1) +#define PORT_P3_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 4 Data Output Register + ******************************************************************************/ + +/* Port 4 Pin # Output Value (23) */ +#define PORT_P4_OUT_P23 (0x1 << 23) +#define PORT_P4_OUT_P23_VAL(val) (((val) & 0x1) << 23) +#define PORT_P4_OUT_P23_GET(val) ((((val) & PORT_P4_OUT_P23) >> 23) & 0x1) +#define PORT_P4_OUT_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P23) | (((val) & 0x1) << 23)) +/* Port 4 Pin # Output Value (22) */ +#define PORT_P4_OUT_P22 (0x1 << 22) +#define PORT_P4_OUT_P22_VAL(val) (((val) & 0x1) << 22) +#define PORT_P4_OUT_P22_GET(val) ((((val) & PORT_P4_OUT_P22) >> 22) & 0x1) +#define PORT_P4_OUT_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P22) | (((val) & 0x1) << 22)) +/* Port 4 Pin # Output Value (21) */ +#define PORT_P4_OUT_P21 (0x1 << 21) +#define PORT_P4_OUT_P21_VAL(val) (((val) & 0x1) << 21) +#define PORT_P4_OUT_P21_GET(val) ((((val) & PORT_P4_OUT_P21) >> 21) & 0x1) +#define PORT_P4_OUT_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P21) | (((val) & 0x1) << 21)) +/* Port 4 Pin # Output Value (20) */ +#define PORT_P4_OUT_P20 (0x1 << 20) +#define PORT_P4_OUT_P20_VAL(val) (((val) & 0x1) << 20) +#define PORT_P4_OUT_P20_GET(val) ((((val) & PORT_P4_OUT_P20) >> 20) & 0x1) +#define PORT_P4_OUT_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P20) | (((val) & 0x1) << 20)) +/* Port 4 Pin # Output Value (19) */ +#define PORT_P4_OUT_P19 (0x1 << 19) +#define PORT_P4_OUT_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P4_OUT_P19_GET(val) ((((val) & PORT_P4_OUT_P19) >> 19) & 0x1) +#define PORT_P4_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P19) | (((val) & 0x1) << 19)) +/* Port 4 Pin # Output Value (18) */ +#define PORT_P4_OUT_P18 (0x1 << 18) +#define PORT_P4_OUT_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P4_OUT_P18_GET(val) ((((val) & PORT_P4_OUT_P18) >> 18) & 0x1) +#define PORT_P4_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P18) | (((val) & 0x1) << 18)) +/* Port 4 Pin # Output Value (17) */ +#define PORT_P4_OUT_P17 (0x1 << 17) +#define PORT_P4_OUT_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P4_OUT_P17_GET(val) ((((val) & PORT_P4_OUT_P17) >> 17) & 0x1) +#define PORT_P4_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P17) | (((val) & 0x1) << 17)) +/* Port 4 Pin # Output Value (16) */ +#define PORT_P4_OUT_P16 (0x1 << 16) +#define PORT_P4_OUT_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P4_OUT_P16_GET(val) ((((val) & PORT_P4_OUT_P16) >> 16) & 0x1) +#define PORT_P4_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P16) | (((val) & 0x1) << 16)) +/* Port 4 Pin # Output Value (15) */ +#define PORT_P4_OUT_P15 (0x1 << 15) +#define PORT_P4_OUT_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P4_OUT_P15_GET(val) ((((val) & PORT_P4_OUT_P15) >> 15) & 0x1) +#define PORT_P4_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P15) | (((val) & 0x1) << 15)) +/* Port 4 Pin # Output Value (14) */ +#define PORT_P4_OUT_P14 (0x1 << 14) +#define PORT_P4_OUT_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P4_OUT_P14_GET(val) ((((val) & PORT_P4_OUT_P14) >> 14) & 0x1) +#define PORT_P4_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P14) | (((val) & 0x1) << 14)) +/* Port 4 Pin # Output Value (13) */ +#define PORT_P4_OUT_P13 (0x1 << 13) +#define PORT_P4_OUT_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P4_OUT_P13_GET(val) ((((val) & PORT_P4_OUT_P13) >> 13) & 0x1) +#define PORT_P4_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P13) | (((val) & 0x1) << 13)) +/* Port 4 Pin # Output Value (12) */ +#define PORT_P4_OUT_P12 (0x1 << 12) +#define PORT_P4_OUT_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P4_OUT_P12_GET(val) ((((val) & PORT_P4_OUT_P12) >> 12) & 0x1) +#define PORT_P4_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P12) | (((val) & 0x1) << 12)) +/* Port 4 Pin # Output Value (11) */ +#define PORT_P4_OUT_P11 (0x1 << 11) +#define PORT_P4_OUT_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P4_OUT_P11_GET(val) ((((val) & PORT_P4_OUT_P11) >> 11) & 0x1) +#define PORT_P4_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P11) | (((val) & 0x1) << 11)) +/* Port 4 Pin # Output Value (10) */ +#define PORT_P4_OUT_P10 (0x1 << 10) +#define PORT_P4_OUT_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P4_OUT_P10_GET(val) ((((val) & PORT_P4_OUT_P10) >> 10) & 0x1) +#define PORT_P4_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P10) | (((val) & 0x1) << 10)) +/* Port 4 Pin # Output Value (9) */ +#define PORT_P4_OUT_P9 (0x1 << 9) +#define PORT_P4_OUT_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P4_OUT_P9_GET(val) ((((val) & PORT_P4_OUT_P9) >> 9) & 0x1) +#define PORT_P4_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P9) | (((val) & 0x1) << 9)) +/* Port 4 Pin # Output Value (8) */ +#define PORT_P4_OUT_P8 (0x1 << 8) +#define PORT_P4_OUT_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P4_OUT_P8_GET(val) ((((val) & PORT_P4_OUT_P8) >> 8) & 0x1) +#define PORT_P4_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P8) | (((val) & 0x1) << 8)) +/* Port 4 Pin # Output Value (7) */ +#define PORT_P4_OUT_P7 (0x1 << 7) +#define PORT_P4_OUT_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P4_OUT_P7_GET(val) ((((val) & PORT_P4_OUT_P7) >> 7) & 0x1) +#define PORT_P4_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P7) | (((val) & 0x1) << 7)) +/* Port 4 Pin # Output Value (6) */ +#define PORT_P4_OUT_P6 (0x1 << 6) +#define PORT_P4_OUT_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P4_OUT_P6_GET(val) ((((val) & PORT_P4_OUT_P6) >> 6) & 0x1) +#define PORT_P4_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P6) | (((val) & 0x1) << 6)) +/* Port 4 Pin # Output Value (5) */ +#define PORT_P4_OUT_P5 (0x1 << 5) +#define PORT_P4_OUT_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P4_OUT_P5_GET(val) ((((val) & PORT_P4_OUT_P5) >> 5) & 0x1) +#define PORT_P4_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P5) | (((val) & 0x1) << 5)) +/* Port 4 Pin # Output Value (4) */ +#define PORT_P4_OUT_P4 (0x1 << 4) +#define PORT_P4_OUT_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P4_OUT_P4_GET(val) ((((val) & PORT_P4_OUT_P4) >> 4) & 0x1) +#define PORT_P4_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P4) | (((val) & 0x1) << 4)) +/* Port 4 Pin # Output Value (3) */ +#define PORT_P4_OUT_P3 (0x1 << 3) +#define PORT_P4_OUT_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P4_OUT_P3_GET(val) ((((val) & PORT_P4_OUT_P3) >> 3) & 0x1) +#define PORT_P4_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P3) | (((val) & 0x1) << 3)) +/* Port 4 Pin # Output Value (2) */ +#define PORT_P4_OUT_P2 (0x1 << 2) +#define PORT_P4_OUT_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P4_OUT_P2_GET(val) ((((val) & PORT_P4_OUT_P2) >> 2) & 0x1) +#define PORT_P4_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P2) | (((val) & 0x1) << 2)) +/* Port 4 Pin # Output Value (1) */ +#define PORT_P4_OUT_P1 (0x1 << 1) +#define PORT_P4_OUT_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P4_OUT_P1_GET(val) ((((val) & PORT_P4_OUT_P1) >> 1) & 0x1) +#define PORT_P4_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P1) | (((val) & 0x1) << 1)) +/* Port 4 Pin # Output Value (0) */ +#define PORT_P4_OUT_P0 (0x1) +#define PORT_P4_OUT_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P4_OUT_P0_GET(val) ((((val) & PORT_P4_OUT_P0) >> 0) & 0x1) +#define PORT_P4_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 4 Data Input Register + ******************************************************************************/ + +/* Port 4 Pin # Latched Input Value (23) */ +#define PORT_P4_IN_P23 (0x1 << 23) +#define PORT_P4_IN_P23_GET(val) ((((val) & PORT_P4_IN_P23) >> 23) & 0x1) +/* Port 4 Pin # Latched Input Value (22) */ +#define PORT_P4_IN_P22 (0x1 << 22) +#define PORT_P4_IN_P22_GET(val) ((((val) & PORT_P4_IN_P22) >> 22) & 0x1) +/* Port 4 Pin # Latched Input Value (21) */ +#define PORT_P4_IN_P21 (0x1 << 21) +#define PORT_P4_IN_P21_GET(val) ((((val) & PORT_P4_IN_P21) >> 21) & 0x1) +/* Port 4 Pin # Latched Input Value (20) */ +#define PORT_P4_IN_P20 (0x1 << 20) +#define PORT_P4_IN_P20_GET(val) ((((val) & PORT_P4_IN_P20) >> 20) & 0x1) +/* Port 4 Pin # Latched Input Value (19) */ +#define PORT_P4_IN_P19 (0x1 << 19) +#define PORT_P4_IN_P19_GET(val) ((((val) & PORT_P4_IN_P19) >> 19) & 0x1) +/* Port 4 Pin # Latched Input Value (18) */ +#define PORT_P4_IN_P18 (0x1 << 18) +#define PORT_P4_IN_P18_GET(val) ((((val) & PORT_P4_IN_P18) >> 18) & 0x1) +/* Port 4 Pin # Latched Input Value (17) */ +#define PORT_P4_IN_P17 (0x1 << 17) +#define PORT_P4_IN_P17_GET(val) ((((val) & PORT_P4_IN_P17) >> 17) & 0x1) +/* Port 4 Pin # Latched Input Value (16) */ +#define PORT_P4_IN_P16 (0x1 << 16) +#define PORT_P4_IN_P16_GET(val) ((((val) & PORT_P4_IN_P16) >> 16) & 0x1) +/* Port 4 Pin # Latched Input Value (15) */ +#define PORT_P4_IN_P15 (0x1 << 15) +#define PORT_P4_IN_P15_GET(val) ((((val) & PORT_P4_IN_P15) >> 15) & 0x1) +/* Port 4 Pin # Latched Input Value (14) */ +#define PORT_P4_IN_P14 (0x1 << 14) +#define PORT_P4_IN_P14_GET(val) ((((val) & PORT_P4_IN_P14) >> 14) & 0x1) +/* Port 4 Pin # Latched Input Value (13) */ +#define PORT_P4_IN_P13 (0x1 << 13) +#define PORT_P4_IN_P13_GET(val) ((((val) & PORT_P4_IN_P13) >> 13) & 0x1) +/* Port 4 Pin # Latched Input Value (12) */ +#define PORT_P4_IN_P12 (0x1 << 12) +#define PORT_P4_IN_P12_GET(val) ((((val) & PORT_P4_IN_P12) >> 12) & 0x1) +/* Port 4 Pin # Latched Input Value (11) */ +#define PORT_P4_IN_P11 (0x1 << 11) +#define PORT_P4_IN_P11_GET(val) ((((val) & PORT_P4_IN_P11) >> 11) & 0x1) +/* Port 4 Pin # Latched Input Value (10) */ +#define PORT_P4_IN_P10 (0x1 << 10) +#define PORT_P4_IN_P10_GET(val) ((((val) & PORT_P4_IN_P10) >> 10) & 0x1) +/* Port 4 Pin # Latched Input Value (9) */ +#define PORT_P4_IN_P9 (0x1 << 9) +#define PORT_P4_IN_P9_GET(val) ((((val) & PORT_P4_IN_P9) >> 9) & 0x1) +/* Port 4 Pin # Latched Input Value (8) */ +#define PORT_P4_IN_P8 (0x1 << 8) +#define PORT_P4_IN_P8_GET(val) ((((val) & PORT_P4_IN_P8) >> 8) & 0x1) +/* Port 4 Pin # Latched Input Value (7) */ +#define PORT_P4_IN_P7 (0x1 << 7) +#define PORT_P4_IN_P7_GET(val) ((((val) & PORT_P4_IN_P7) >> 7) & 0x1) +/* Port 4 Pin # Latched Input Value (6) */ +#define PORT_P4_IN_P6 (0x1 << 6) +#define PORT_P4_IN_P6_GET(val) ((((val) & PORT_P4_IN_P6) >> 6) & 0x1) +/* Port 4 Pin # Latched Input Value (5) */ +#define PORT_P4_IN_P5 (0x1 << 5) +#define PORT_P4_IN_P5_GET(val) ((((val) & PORT_P4_IN_P5) >> 5) & 0x1) +/* Port 4 Pin # Latched Input Value (4) */ +#define PORT_P4_IN_P4 (0x1 << 4) +#define PORT_P4_IN_P4_GET(val) ((((val) & PORT_P4_IN_P4) >> 4) & 0x1) +/* Port 4 Pin # Latched Input Value (3) */ +#define PORT_P4_IN_P3 (0x1 << 3) +#define PORT_P4_IN_P3_GET(val) ((((val) & PORT_P4_IN_P3) >> 3) & 0x1) +/* Port 4 Pin # Latched Input Value (2) */ +#define PORT_P4_IN_P2 (0x1 << 2) +#define PORT_P4_IN_P2_GET(val) ((((val) & PORT_P4_IN_P2) >> 2) & 0x1) +/* Port 4 Pin # Latched Input Value (1) */ +#define PORT_P4_IN_P1 (0x1 << 1) +#define PORT_P4_IN_P1_GET(val) ((((val) & PORT_P4_IN_P1) >> 1) & 0x1) +/* Port 4 Pin # Latched Input Value (0) */ +#define PORT_P4_IN_P0 (0x1) +#define PORT_P4_IN_P0_GET(val) ((((val) & PORT_P4_IN_P0) >> 0) & 0x1) + +/******************************************************************************* + * Port 4 Direction Register + ******************************************************************************/ + +/* Port 4 Pin #Direction Control (23) */ +#define PORT_P4_DIR_P23 (0x1 << 23) +#define PORT_P4_DIR_P23_VAL(val) (((val) & 0x1) << 23) +#define PORT_P4_DIR_P23_GET(val) ((((val) & PORT_P4_DIR_P23) >> 23) & 0x1) +#define PORT_P4_DIR_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P23) | (((val) & 0x1) << 23)) +/* Port 4 Pin #Direction Control (22) */ +#define PORT_P4_DIR_P22 (0x1 << 22) +#define PORT_P4_DIR_P22_VAL(val) (((val) & 0x1) << 22) +#define PORT_P4_DIR_P22_GET(val) ((((val) & PORT_P4_DIR_P22) >> 22) & 0x1) +#define PORT_P4_DIR_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P22) | (((val) & 0x1) << 22)) +/* Port 4 Pin #Direction Control (21) */ +#define PORT_P4_DIR_P21 (0x1 << 21) +#define PORT_P4_DIR_P21_VAL(val) (((val) & 0x1) << 21) +#define PORT_P4_DIR_P21_GET(val) ((((val) & PORT_P4_DIR_P21) >> 21) & 0x1) +#define PORT_P4_DIR_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P21) | (((val) & 0x1) << 21)) +/* Port 4 Pin #Direction Control (20) */ +#define PORT_P4_DIR_P20 (0x1 << 20) +#define PORT_P4_DIR_P20_VAL(val) (((val) & 0x1) << 20) +#define PORT_P4_DIR_P20_GET(val) ((((val) & PORT_P4_DIR_P20) >> 20) & 0x1) +#define PORT_P4_DIR_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P20) | (((val) & 0x1) << 20)) +/* Port 4 Pin #Direction Control (19) */ +#define PORT_P4_DIR_P19 (0x1 << 19) +#define PORT_P4_DIR_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P4_DIR_P19_GET(val) ((((val) & PORT_P4_DIR_P19) >> 19) & 0x1) +#define PORT_P4_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P19) | (((val) & 0x1) << 19)) +/* Port 4 Pin #Direction Control (18) */ +#define PORT_P4_DIR_P18 (0x1 << 18) +#define PORT_P4_DIR_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P4_DIR_P18_GET(val) ((((val) & PORT_P4_DIR_P18) >> 18) & 0x1) +#define PORT_P4_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P18) | (((val) & 0x1) << 18)) +/* Port 4 Pin #Direction Control (17) */ +#define PORT_P4_DIR_P17 (0x1 << 17) +#define PORT_P4_DIR_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P4_DIR_P17_GET(val) ((((val) & PORT_P4_DIR_P17) >> 17) & 0x1) +#define PORT_P4_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P17) | (((val) & 0x1) << 17)) +/* Port 4 Pin #Direction Control (16) */ +#define PORT_P4_DIR_P16 (0x1 << 16) +#define PORT_P4_DIR_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P4_DIR_P16_GET(val) ((((val) & PORT_P4_DIR_P16) >> 16) & 0x1) +#define PORT_P4_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P16) | (((val) & 0x1) << 16)) +/* Port 4 Pin #Direction Control (15) */ +#define PORT_P4_DIR_P15 (0x1 << 15) +#define PORT_P4_DIR_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P4_DIR_P15_GET(val) ((((val) & PORT_P4_DIR_P15) >> 15) & 0x1) +#define PORT_P4_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P15) | (((val) & 0x1) << 15)) +/* Port 4 Pin #Direction Control (14) */ +#define PORT_P4_DIR_P14 (0x1 << 14) +#define PORT_P4_DIR_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P4_DIR_P14_GET(val) ((((val) & PORT_P4_DIR_P14) >> 14) & 0x1) +#define PORT_P4_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P14) | (((val) & 0x1) << 14)) +/* Port 4 Pin #Direction Control (13) */ +#define PORT_P4_DIR_P13 (0x1 << 13) +#define PORT_P4_DIR_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P4_DIR_P13_GET(val) ((((val) & PORT_P4_DIR_P13) >> 13) & 0x1) +#define PORT_P4_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P13) | (((val) & 0x1) << 13)) +/* Port 4 Pin #Direction Control (12) */ +#define PORT_P4_DIR_P12 (0x1 << 12) +#define PORT_P4_DIR_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P4_DIR_P12_GET(val) ((((val) & PORT_P4_DIR_P12) >> 12) & 0x1) +#define PORT_P4_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P12) | (((val) & 0x1) << 12)) +/* Port 4 Pin #Direction Control (11) */ +#define PORT_P4_DIR_P11 (0x1 << 11) +#define PORT_P4_DIR_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P4_DIR_P11_GET(val) ((((val) & PORT_P4_DIR_P11) >> 11) & 0x1) +#define PORT_P4_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P11) | (((val) & 0x1) << 11)) +/* Port 4 Pin #Direction Control (10) */ +#define PORT_P4_DIR_P10 (0x1 << 10) +#define PORT_P4_DIR_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P4_DIR_P10_GET(val) ((((val) & PORT_P4_DIR_P10) >> 10) & 0x1) +#define PORT_P4_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P10) | (((val) & 0x1) << 10)) +/* Port 4 Pin #Direction Control (9) */ +#define PORT_P4_DIR_P9 (0x1 << 9) +#define PORT_P4_DIR_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P4_DIR_P9_GET(val) ((((val) & PORT_P4_DIR_P9) >> 9) & 0x1) +#define PORT_P4_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P9) | (((val) & 0x1) << 9)) +/* Port 4 Pin #Direction Control (8) */ +#define PORT_P4_DIR_P8 (0x1 << 8) +#define PORT_P4_DIR_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P4_DIR_P8_GET(val) ((((val) & PORT_P4_DIR_P8) >> 8) & 0x1) +#define PORT_P4_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P8) | (((val) & 0x1) << 8)) +/* Port 4 Pin #Direction Control (7) */ +#define PORT_P4_DIR_P7 (0x1 << 7) +#define PORT_P4_DIR_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P4_DIR_P7_GET(val) ((((val) & PORT_P4_DIR_P7) >> 7) & 0x1) +#define PORT_P4_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P7) | (((val) & 0x1) << 7)) +/* Port 4 Pin #Direction Control (6) */ +#define PORT_P4_DIR_P6 (0x1 << 6) +#define PORT_P4_DIR_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P4_DIR_P6_GET(val) ((((val) & PORT_P4_DIR_P6) >> 6) & 0x1) +#define PORT_P4_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P6) | (((val) & 0x1) << 6)) +/* Port 4 Pin #Direction Control (5) */ +#define PORT_P4_DIR_P5 (0x1 << 5) +#define PORT_P4_DIR_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P4_DIR_P5_GET(val) ((((val) & PORT_P4_DIR_P5) >> 5) & 0x1) +#define PORT_P4_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P5) | (((val) & 0x1) << 5)) +/* Port 4 Pin #Direction Control (4) */ +#define PORT_P4_DIR_P4 (0x1 << 4) +#define PORT_P4_DIR_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P4_DIR_P4_GET(val) ((((val) & PORT_P4_DIR_P4) >> 4) & 0x1) +#define PORT_P4_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P4) | (((val) & 0x1) << 4)) +/* Port 4 Pin #Direction Control (3) */ +#define PORT_P4_DIR_P3 (0x1 << 3) +#define PORT_P4_DIR_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P4_DIR_P3_GET(val) ((((val) & PORT_P4_DIR_P3) >> 3) & 0x1) +#define PORT_P4_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P3) | (((val) & 0x1) << 3)) +/* Port 4 Pin #Direction Control (2) */ +#define PORT_P4_DIR_P2 (0x1 << 2) +#define PORT_P4_DIR_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P4_DIR_P2_GET(val) ((((val) & PORT_P4_DIR_P2) >> 2) & 0x1) +#define PORT_P4_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P2) | (((val) & 0x1) << 2)) +/* Port 4 Pin #Direction Control (1) */ +#define PORT_P4_DIR_P1 (0x1 << 1) +#define PORT_P4_DIR_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P4_DIR_P1_GET(val) ((((val) & PORT_P4_DIR_P1) >> 1) & 0x1) +#define PORT_P4_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P1) | (((val) & 0x1) << 1)) +/* Port 4 Pin #Direction Control (0) */ +#define PORT_P4_DIR_P0 (0x1) +#define PORT_P4_DIR_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P4_DIR_P0_GET(val) ((((val) & PORT_P4_DIR_P0) >> 0) & 0x1) +#define PORT_P4_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 4 Alternate Function Select Register 0 + ******************************************************************************/ + +/* Alternate Function at Port 4 Bit # (23) */ +#define PORT_P4_ALTSEL0_P23 (0x1 << 23) +#define PORT_P4_ALTSEL0_P23_VAL(val) (((val) & 0x1) << 23) +#define PORT_P4_ALTSEL0_P23_GET(val) ((((val) & PORT_P4_ALTSEL0_P23) >> 23) & 0x1) +#define PORT_P4_ALTSEL0_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P23) | (((val) & 0x1) << 23)) +/* Alternate Function at Port 4 Bit # (22) */ +#define PORT_P4_ALTSEL0_P22 (0x1 << 22) +#define PORT_P4_ALTSEL0_P22_VAL(val) (((val) & 0x1) << 22) +#define PORT_P4_ALTSEL0_P22_GET(val) ((((val) & PORT_P4_ALTSEL0_P22) >> 22) & 0x1) +#define PORT_P4_ALTSEL0_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P22) | (((val) & 0x1) << 22)) +/* Alternate Function at Port 4 Bit # (21) */ +#define PORT_P4_ALTSEL0_P21 (0x1 << 21) +#define PORT_P4_ALTSEL0_P21_VAL(val) (((val) & 0x1) << 21) +#define PORT_P4_ALTSEL0_P21_GET(val) ((((val) & PORT_P4_ALTSEL0_P21) >> 21) & 0x1) +#define PORT_P4_ALTSEL0_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P21) | (((val) & 0x1) << 21)) +/* Alternate Function at Port 4 Bit # (20) */ +#define PORT_P4_ALTSEL0_P20 (0x1 << 20) +#define PORT_P4_ALTSEL0_P20_VAL(val) (((val) & 0x1) << 20) +#define PORT_P4_ALTSEL0_P20_GET(val) ((((val) & PORT_P4_ALTSEL0_P20) >> 20) & 0x1) +#define PORT_P4_ALTSEL0_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P20) | (((val) & 0x1) << 20)) +/* Alternate Function at Port 4 Bit # (19) */ +#define PORT_P4_ALTSEL0_P19 (0x1 << 19) +#define PORT_P4_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P4_ALTSEL0_P19_GET(val) ((((val) & PORT_P4_ALTSEL0_P19) >> 19) & 0x1) +#define PORT_P4_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P19) | (((val) & 0x1) << 19)) +/* Alternate Function at Port 4 Bit # (18) */ +#define PORT_P4_ALTSEL0_P18 (0x1 << 18) +#define PORT_P4_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P4_ALTSEL0_P18_GET(val) ((((val) & PORT_P4_ALTSEL0_P18) >> 18) & 0x1) +#define PORT_P4_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P18) | (((val) & 0x1) << 18)) +/* Alternate Function at Port 4 Bit # (17) */ +#define PORT_P4_ALTSEL0_P17 (0x1 << 17) +#define PORT_P4_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P4_ALTSEL0_P17_GET(val) ((((val) & PORT_P4_ALTSEL0_P17) >> 17) & 0x1) +#define PORT_P4_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P17) | (((val) & 0x1) << 17)) +/* Alternate Function at Port 4 Bit # (16) */ +#define PORT_P4_ALTSEL0_P16 (0x1 << 16) +#define PORT_P4_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P4_ALTSEL0_P16_GET(val) ((((val) & PORT_P4_ALTSEL0_P16) >> 16) & 0x1) +#define PORT_P4_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P16) | (((val) & 0x1) << 16)) +/* Alternate Function at Port 4 Bit # (15) */ +#define PORT_P4_ALTSEL0_P15 (0x1 << 15) +#define PORT_P4_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P4_ALTSEL0_P15_GET(val) ((((val) & PORT_P4_ALTSEL0_P15) >> 15) & 0x1) +#define PORT_P4_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P15) | (((val) & 0x1) << 15)) +/* Alternate Function at Port 4 Bit # (14) */ +#define PORT_P4_ALTSEL0_P14 (0x1 << 14) +#define PORT_P4_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P4_ALTSEL0_P14_GET(val) ((((val) & PORT_P4_ALTSEL0_P14) >> 14) & 0x1) +#define PORT_P4_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P14) | (((val) & 0x1) << 14)) +/* Alternate Function at Port 4 Bit # (13) */ +#define PORT_P4_ALTSEL0_P13 (0x1 << 13) +#define PORT_P4_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P4_ALTSEL0_P13_GET(val) ((((val) & PORT_P4_ALTSEL0_P13) >> 13) & 0x1) +#define PORT_P4_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P13) | (((val) & 0x1) << 13)) +/* Alternate Function at Port 4 Bit # (12) */ +#define PORT_P4_ALTSEL0_P12 (0x1 << 12) +#define PORT_P4_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P4_ALTSEL0_P12_GET(val) ((((val) & PORT_P4_ALTSEL0_P12) >> 12) & 0x1) +#define PORT_P4_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P12) | (((val) & 0x1) << 12)) +/* Alternate Function at Port 4 Bit # (11) */ +#define PORT_P4_ALTSEL0_P11 (0x1 << 11) +#define PORT_P4_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P4_ALTSEL0_P11_GET(val) ((((val) & PORT_P4_ALTSEL0_P11) >> 11) & 0x1) +#define PORT_P4_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P11) | (((val) & 0x1) << 11)) +/* Alternate Function at Port 4 Bit # (10) */ +#define PORT_P4_ALTSEL0_P10 (0x1 << 10) +#define PORT_P4_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P4_ALTSEL0_P10_GET(val) ((((val) & PORT_P4_ALTSEL0_P10) >> 10) & 0x1) +#define PORT_P4_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P10) | (((val) & 0x1) << 10)) +/* Alternate Function at Port 4 Bit # (9) */ +#define PORT_P4_ALTSEL0_P9 (0x1 << 9) +#define PORT_P4_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P4_ALTSEL0_P9_GET(val) ((((val) & PORT_P4_ALTSEL0_P9) >> 9) & 0x1) +#define PORT_P4_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P9) | (((val) & 0x1) << 9)) +/* Alternate Function at Port 4 Bit # (8) */ +#define PORT_P4_ALTSEL0_P8 (0x1 << 8) +#define PORT_P4_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P4_ALTSEL0_P8_GET(val) ((((val) & PORT_P4_ALTSEL0_P8) >> 8) & 0x1) +#define PORT_P4_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P8) | (((val) & 0x1) << 8)) +/* Alternate Function at Port 4 Bit # (7) */ +#define PORT_P4_ALTSEL0_P7 (0x1 << 7) +#define PORT_P4_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P4_ALTSEL0_P7_GET(val) ((((val) & PORT_P4_ALTSEL0_P7) >> 7) & 0x1) +#define PORT_P4_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P7) | (((val) & 0x1) << 7)) +/* Alternate Function at Port 4 Bit # (6) */ +#define PORT_P4_ALTSEL0_P6 (0x1 << 6) +#define PORT_P4_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P4_ALTSEL0_P6_GET(val) ((((val) & PORT_P4_ALTSEL0_P6) >> 6) & 0x1) +#define PORT_P4_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P6) | (((val) & 0x1) << 6)) +/* Alternate Function at Port 4 Bit # (5) */ +#define PORT_P4_ALTSEL0_P5 (0x1 << 5) +#define PORT_P4_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P4_ALTSEL0_P5_GET(val) ((((val) & PORT_P4_ALTSEL0_P5) >> 5) & 0x1) +#define PORT_P4_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P5) | (((val) & 0x1) << 5)) +/* Alternate Function at Port 4 Bit # (4) */ +#define PORT_P4_ALTSEL0_P4 (0x1 << 4) +#define PORT_P4_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P4_ALTSEL0_P4_GET(val) ((((val) & PORT_P4_ALTSEL0_P4) >> 4) & 0x1) +#define PORT_P4_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P4) | (((val) & 0x1) << 4)) +/* Alternate Function at Port 4 Bit # (3) */ +#define PORT_P4_ALTSEL0_P3 (0x1 << 3) +#define PORT_P4_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P4_ALTSEL0_P3_GET(val) ((((val) & PORT_P4_ALTSEL0_P3) >> 3) & 0x1) +#define PORT_P4_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P3) | (((val) & 0x1) << 3)) +/* Alternate Function at Port 4 Bit # (2) */ +#define PORT_P4_ALTSEL0_P2 (0x1 << 2) +#define PORT_P4_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P4_ALTSEL0_P2_GET(val) ((((val) & PORT_P4_ALTSEL0_P2) >> 2) & 0x1) +#define PORT_P4_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P2) | (((val) & 0x1) << 2)) +/* Alternate Function at Port 4 Bit # (1) */ +#define PORT_P4_ALTSEL0_P1 (0x1 << 1) +#define PORT_P4_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P4_ALTSEL0_P1_GET(val) ((((val) & PORT_P4_ALTSEL0_P1) >> 1) & 0x1) +#define PORT_P4_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P1) | (((val) & 0x1) << 1)) +/* Alternate Function at Port 4 Bit # (0) */ +#define PORT_P4_ALTSEL0_P0 (0x1) +#define PORT_P4_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P4_ALTSEL0_P0_GET(val) ((((val) & PORT_P4_ALTSEL0_P0) >> 0) & 0x1) +#define PORT_P4_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * Port 4 Pull Up Device Enable Register + ******************************************************************************/ + +/* Pull Up Device Enable at Port 4 Bit # (23) */ +#define PORT_P4_PUEN_P23 (0x1 << 23) +#define PORT_P4_PUEN_P23_VAL(val) (((val) & 0x1) << 23) +#define PORT_P4_PUEN_P23_GET(val) ((((val) & PORT_P4_PUEN_P23) >> 23) & 0x1) +#define PORT_P4_PUEN_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P23) | (((val) & 0x1) << 23)) +/* Pull Up Device Enable at Port 4 Bit # (22) */ +#define PORT_P4_PUEN_P22 (0x1 << 22) +#define PORT_P4_PUEN_P22_VAL(val) (((val) & 0x1) << 22) +#define PORT_P4_PUEN_P22_GET(val) ((((val) & PORT_P4_PUEN_P22) >> 22) & 0x1) +#define PORT_P4_PUEN_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P22) | (((val) & 0x1) << 22)) +/* Pull Up Device Enable at Port 4 Bit # (21) */ +#define PORT_P4_PUEN_P21 (0x1 << 21) +#define PORT_P4_PUEN_P21_VAL(val) (((val) & 0x1) << 21) +#define PORT_P4_PUEN_P21_GET(val) ((((val) & PORT_P4_PUEN_P21) >> 21) & 0x1) +#define PORT_P4_PUEN_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P21) | (((val) & 0x1) << 21)) +/* Pull Up Device Enable at Port 4 Bit # (20) */ +#define PORT_P4_PUEN_P20 (0x1 << 20) +#define PORT_P4_PUEN_P20_VAL(val) (((val) & 0x1) << 20) +#define PORT_P4_PUEN_P20_GET(val) ((((val) & PORT_P4_PUEN_P20) >> 20) & 0x1) +#define PORT_P4_PUEN_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P20) | (((val) & 0x1) << 20)) +/* Pull Up Device Enable at Port 4 Bit # (19) */ +#define PORT_P4_PUEN_P19 (0x1 << 19) +#define PORT_P4_PUEN_P19_VAL(val) (((val) & 0x1) << 19) +#define PORT_P4_PUEN_P19_GET(val) ((((val) & PORT_P4_PUEN_P19) >> 19) & 0x1) +#define PORT_P4_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P19) | (((val) & 0x1) << 19)) +/* Pull Up Device Enable at Port 4 Bit # (18) */ +#define PORT_P4_PUEN_P18 (0x1 << 18) +#define PORT_P4_PUEN_P18_VAL(val) (((val) & 0x1) << 18) +#define PORT_P4_PUEN_P18_GET(val) ((((val) & PORT_P4_PUEN_P18) >> 18) & 0x1) +#define PORT_P4_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P18) | (((val) & 0x1) << 18)) +/* Pull Up Device Enable at Port 4 Bit # (17) */ +#define PORT_P4_PUEN_P17 (0x1 << 17) +#define PORT_P4_PUEN_P17_VAL(val) (((val) & 0x1) << 17) +#define PORT_P4_PUEN_P17_GET(val) ((((val) & PORT_P4_PUEN_P17) >> 17) & 0x1) +#define PORT_P4_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P17) | (((val) & 0x1) << 17)) +/* Pull Up Device Enable at Port 4 Bit # (16) */ +#define PORT_P4_PUEN_P16 (0x1 << 16) +#define PORT_P4_PUEN_P16_VAL(val) (((val) & 0x1) << 16) +#define PORT_P4_PUEN_P16_GET(val) ((((val) & PORT_P4_PUEN_P16) >> 16) & 0x1) +#define PORT_P4_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P16) | (((val) & 0x1) << 16)) +/* Pull Up Device Enable at Port 4 Bit # (15) */ +#define PORT_P4_PUEN_P15 (0x1 << 15) +#define PORT_P4_PUEN_P15_VAL(val) (((val) & 0x1) << 15) +#define PORT_P4_PUEN_P15_GET(val) ((((val) & PORT_P4_PUEN_P15) >> 15) & 0x1) +#define PORT_P4_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P15) | (((val) & 0x1) << 15)) +/* Pull Up Device Enable at Port 4 Bit # (14) */ +#define PORT_P4_PUEN_P14 (0x1 << 14) +#define PORT_P4_PUEN_P14_VAL(val) (((val) & 0x1) << 14) +#define PORT_P4_PUEN_P14_GET(val) ((((val) & PORT_P4_PUEN_P14) >> 14) & 0x1) +#define PORT_P4_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P14) | (((val) & 0x1) << 14)) +/* Pull Up Device Enable at Port 4 Bit # (13) */ +#define PORT_P4_PUEN_P13 (0x1 << 13) +#define PORT_P4_PUEN_P13_VAL(val) (((val) & 0x1) << 13) +#define PORT_P4_PUEN_P13_GET(val) ((((val) & PORT_P4_PUEN_P13) >> 13) & 0x1) +#define PORT_P4_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P13) | (((val) & 0x1) << 13)) +/* Pull Up Device Enable at Port 4 Bit # (12) */ +#define PORT_P4_PUEN_P12 (0x1 << 12) +#define PORT_P4_PUEN_P12_VAL(val) (((val) & 0x1) << 12) +#define PORT_P4_PUEN_P12_GET(val) ((((val) & PORT_P4_PUEN_P12) >> 12) & 0x1) +#define PORT_P4_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P12) | (((val) & 0x1) << 12)) +/* Pull Up Device Enable at Port 4 Bit # (11) */ +#define PORT_P4_PUEN_P11 (0x1 << 11) +#define PORT_P4_PUEN_P11_VAL(val) (((val) & 0x1) << 11) +#define PORT_P4_PUEN_P11_GET(val) ((((val) & PORT_P4_PUEN_P11) >> 11) & 0x1) +#define PORT_P4_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P11) | (((val) & 0x1) << 11)) +/* Pull Up Device Enable at Port 4 Bit # (10) */ +#define PORT_P4_PUEN_P10 (0x1 << 10) +#define PORT_P4_PUEN_P10_VAL(val) (((val) & 0x1) << 10) +#define PORT_P4_PUEN_P10_GET(val) ((((val) & PORT_P4_PUEN_P10) >> 10) & 0x1) +#define PORT_P4_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P10) | (((val) & 0x1) << 10)) +/* Pull Up Device Enable at Port 4 Bit # (9) */ +#define PORT_P4_PUEN_P9 (0x1 << 9) +#define PORT_P4_PUEN_P9_VAL(val) (((val) & 0x1) << 9) +#define PORT_P4_PUEN_P9_GET(val) ((((val) & PORT_P4_PUEN_P9) >> 9) & 0x1) +#define PORT_P4_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P9) | (((val) & 0x1) << 9)) +/* Pull Up Device Enable at Port 4 Bit # (8) */ +#define PORT_P4_PUEN_P8 (0x1 << 8) +#define PORT_P4_PUEN_P8_VAL(val) (((val) & 0x1) << 8) +#define PORT_P4_PUEN_P8_GET(val) ((((val) & PORT_P4_PUEN_P8) >> 8) & 0x1) +#define PORT_P4_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P8) | (((val) & 0x1) << 8)) +/* Pull Up Device Enable at Port 4 Bit # (7) */ +#define PORT_P4_PUEN_P7 (0x1 << 7) +#define PORT_P4_PUEN_P7_VAL(val) (((val) & 0x1) << 7) +#define PORT_P4_PUEN_P7_GET(val) ((((val) & PORT_P4_PUEN_P7) >> 7) & 0x1) +#define PORT_P4_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P7) | (((val) & 0x1) << 7)) +/* Pull Up Device Enable at Port 4 Bit # (6) */ +#define PORT_P4_PUEN_P6 (0x1 << 6) +#define PORT_P4_PUEN_P6_VAL(val) (((val) & 0x1) << 6) +#define PORT_P4_PUEN_P6_GET(val) ((((val) & PORT_P4_PUEN_P6) >> 6) & 0x1) +#define PORT_P4_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P6) | (((val) & 0x1) << 6)) +/* Pull Up Device Enable at Port 4 Bit # (5) */ +#define PORT_P4_PUEN_P5 (0x1 << 5) +#define PORT_P4_PUEN_P5_VAL(val) (((val) & 0x1) << 5) +#define PORT_P4_PUEN_P5_GET(val) ((((val) & PORT_P4_PUEN_P5) >> 5) & 0x1) +#define PORT_P4_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P5) | (((val) & 0x1) << 5)) +/* Pull Up Device Enable at Port 4 Bit # (4) */ +#define PORT_P4_PUEN_P4 (0x1 << 4) +#define PORT_P4_PUEN_P4_VAL(val) (((val) & 0x1) << 4) +#define PORT_P4_PUEN_P4_GET(val) ((((val) & PORT_P4_PUEN_P4) >> 4) & 0x1) +#define PORT_P4_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P4) | (((val) & 0x1) << 4)) +/* Pull Up Device Enable at Port 4 Bit # (3) */ +#define PORT_P4_PUEN_P3 (0x1 << 3) +#define PORT_P4_PUEN_P3_VAL(val) (((val) & 0x1) << 3) +#define PORT_P4_PUEN_P3_GET(val) ((((val) & PORT_P4_PUEN_P3) >> 3) & 0x1) +#define PORT_P4_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P3) | (((val) & 0x1) << 3)) +/* Pull Up Device Enable at Port 4 Bit # (2) */ +#define PORT_P4_PUEN_P2 (0x1 << 2) +#define PORT_P4_PUEN_P2_VAL(val) (((val) & 0x1) << 2) +#define PORT_P4_PUEN_P2_GET(val) ((((val) & PORT_P4_PUEN_P2) >> 2) & 0x1) +#define PORT_P4_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P2) | (((val) & 0x1) << 2)) +/* Pull Up Device Enable at Port 4 Bit # (1) */ +#define PORT_P4_PUEN_P1 (0x1 << 1) +#define PORT_P4_PUEN_P1_VAL(val) (((val) & 0x1) << 1) +#define PORT_P4_PUEN_P1_GET(val) ((((val) & PORT_P4_PUEN_P1) >> 1) & 0x1) +#define PORT_P4_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P1) | (((val) & 0x1) << 1)) +/* Pull Up Device Enable at Port 4 Bit # (0) */ +#define PORT_P4_PUEN_P0 (0x1) +#define PORT_P4_PUEN_P0_VAL(val) (((val) & 0x1) << 0) +#define PORT_P4_PUEN_P0_GET(val) ((((val) & PORT_P4_PUEN_P0) >> 0) & 0x1) +#define PORT_P4_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P0) | (((val) & 0x1) << 0)) + +#endif /* __PORT_H */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ssc_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ssc_reg.h new file mode 100644 index 0000000000..4ea2f5a685 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/ssc_reg.h @@ -0,0 +1,624 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __SSC_REG_H +#define __SSC_REG_H + +/** SSC register structure */ +struct svip_reg_ssc { + volatile unsigned long clc; /* 0x00 */ + volatile unsigned long pisel; /* 0x04 */ + volatile unsigned long id; /* 0x08 */ + volatile unsigned long reserved0; /* 0x0c */ + volatile unsigned long mcon; /* 0x10 */ + volatile unsigned long state; /* 0x14 */ + volatile unsigned long whbstate; /* 0x18 */ + volatile unsigned long reserved1; /* 0x1c */ + volatile unsigned long tb; /* 0x20 */ + volatile unsigned long rb; /* 0x24 */ + volatile unsigned long reserved2[2]; /* 0x28 */ + volatile unsigned long rxfcon; /* 0x30 */ + volatile unsigned long txfcon; /* 0x34 */ + volatile unsigned long fstat; /* 0x38 */ + volatile unsigned long reserved3; /* 0x3c */ + volatile unsigned long br; /* 0x40 */ + volatile unsigned long brstat; /* 0x44 */ + volatile unsigned long reserved4[6]; /* 0x48 */ + volatile unsigned long sfcon; /* 0x60 */ + volatile unsigned long sfstat; /* 0x64 */ + volatile unsigned long reserved5[2]; /* 0x68 */ + volatile unsigned long gpocon; /* 0x70 */ + volatile unsigned long gpostat; /* 0x74 */ + volatile unsigned long whbgpostat; /* 0x78 */ + volatile unsigned long reserved6; /* 0x7c */ + volatile unsigned long rxreq; /* 0x80 */ + volatile unsigned long rxcnt; /* 0x84 */ + volatile unsigned long reserved7[25]; /* 0x88 */ + volatile unsigned long dma_con; /* 0xEC */ + volatile unsigned long reserved8; /* 0xf0 */ + volatile unsigned long irnen; /* 0xF4 */ + volatile unsigned long irncr; /* 0xF8 */ + volatile unsigned long irnicr; /* 0xFC */ +}; + +/******************************************************************************* + * CLC Register + ******************************************************************************/ + +/* Clock Divider for Sleep Mode (23:16) */ +#define SSC_CLC_SMC (0xff << 16) +#define SSC_CLC_SMC_VAL(val) (((val) & 0xff) << 16) +#define SSC_CLC_SMC_GET(val) ((((val) & SSC_CLC_SMC) >> 16) & 0xff) +#define SSC_CLC_SMC_SET(reg,val) (reg) = ((reg & ~SSC_CLC_SMC) | (((val) & 0xff) << 16)) +/* Clock Divider for Normal Run Mode (15:8) */ +#define SSC_CLC_RMC (0xff << 8) +#define SSC_CLC_RMC_VAL(val) (((val) & 0xff) << 8) +#define SSC_CLC_RMC_GET(val) ((((val) & SSC_CLC_RMC) >> 8) & 0xff) +#define SSC_CLC_RMC_SET(reg,val) (reg) = ((reg & ~SSC_CLC_RMC) | (((val) & 0xff) << 8)) +/* Fast Shut-Off Enable Bit (5) */ +#define SSC_CLC_FSOE (0x1 << 5) +#define SSC_CLC_FSOE_VAL(val) (((val) & 0x1) << 5) +#define SSC_CLC_FSOE_GET(val) ((((val) & SSC_CLC_FSOE) >> 5) & 0x1) +#define SSC_CLC_FSOE_SET(reg,val) (reg) = ((reg & ~SSC_CLC_FSOE) | (((val) & 0x1) << 5)) +/* Suspend Bit Write Enable for OCDS (4) */ +#define SSC_CLC_SBWE (0x1 << 4) +#define SSC_CLC_SBWE_VAL(val) (((val) & 0x1) << 4) +#define SSC_CLC_SBWE_SET(reg,val) (reg) = (((reg & ~SSC_CLC_SBWE) | (val) & 1) << 4) +/* External Request Disable (3) */ +#define SSC_CLC_EDIS (0x1 << 3) +#define SSC_CLC_EDIS_VAL(val) (((val) & 0x1) << 3) +#define SSC_CLC_EDIS_GET(val) ((((val) & SSC_CLC_EDIS) >> 3) & 0x1) +#define SSC_CLC_EDIS_SET(reg,val) (reg) = ((reg & ~SSC_CLC_EDIS) | (((val) & 0x1) << 3)) +/* Suspend Enable Bit for OCDS (2) */ +#define SSC_CLC_SPEN (0x1 << 2) +#define SSC_CLC_SPEN_VAL(val) (((val) & 0x1) << 2) +#define SSC_CLC_SPEN_GET(val) ((((val) & SSC_CLC_SPEN) >> 2) & 0x1) +#define SSC_CLC_SPEN_SET(reg,val) (reg) = ((reg & ~SSC_CLC_SPEN) | (((val) & 0x1) << 2)) +/* Disable Status Bit (1) */ +#define SSC_CLC_DISS (0x1 << 1) +#define SSC_CLC_DISS_GET(val) ((((val) & SSC_CLC_DISS) >> 1) & 0x1) +/* Disable Request Bit (0) */ +#define SSC_CLC_DISR (0x1) +#define SSC_CLC_DISR_VAL(val) (((val) & 0x1) << 0) +#define SSC_CLC_DISR_GET(val) ((((val) & SSC_CLC_DISR) >> 0) & 0x1) +#define SSC_CLC_DISR_SET(reg,val) (reg) = ((reg & ~SSC_CLC_DISR) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * ID Register + ******************************************************************************/ + +/* Transmit FIFO Size (29:24) */ +#define SSC_ID_TXFS (0x3f << 24) +#define SSC_ID_TXFS_GET(val) ((((val) & SSC_ID_TXFS) >> 24) & 0x3f) +/* Receive FIFO Size (21:16) */ +#define SSC_ID_RXFS (0x3f << 16) +#define SSC_ID_RXFS_GET(val) ((((val) & SSC_ID_RXFS) >> 16) & 0x3f) +/* Module ID (15:8) */ +#define SSC_ID_ID (0xff << 8) +#define SSC_ID_ID_GET(val) ((((val) & SSC_ID_ID) >> 8) & 0xff) +/* Configuration (5) */ +#define SSC_ID_CFG (0x1 << 5) +#define SSC_ID_CFG_GET(val) ((((val) & SSC_ID_CFG) >> 5) & 0x1) +/* Revision (4:0) */ +#define SSC_ID_REV (0x1f) +#define SSC_ID_REV_GET(val) ((((val) & SSC_ID_REV) >> 0) & 0x1f) + +/******************************************************************************* + * MCON Register + ******************************************************************************/ + +/* Echo Mode (24) */ +#define SSC_MCON_EM (0x1 << 24) +#define SSC_MCON_EM_VAL(val) (((val) & 0x1) << 24) +#define SSC_MCON_EM_GET(val) ((((val) & SSC_MCON_EM) >> 24) & 0x1) +#define SSC_MCON_EM_SET(reg,val) (reg) = ((reg & ~SSC_MCON_EM) | (((val) & 0x1) << 24)) +/* Idle Bit Value (23) */ +#define SSC_MCON_IDLE (0x1 << 23) +#define SSC_MCON_IDLE_VAL(val) (((val) & 0x1) << 23) +#define SSC_MCON_IDLE_GET(val) ((((val) & SSC_MCON_IDLE) >> 23) & 0x1) +#define SSC_MCON_IDLE_SET(reg,val) (reg) = ((reg & ~SSC_MCON_IDLE) | (((val) & 0x1) << 23)) +/* Enable Byte Valid Control (22) */ +#define SSC_MCON_ENBV (0x1 << 22) +#define SSC_MCON_ENBV_VAL(val) (((val) & 0x1) << 22) +#define SSC_MCON_ENBV_GET(val) ((((val) & SSC_MCON_ENBV) >> 22) & 0x1) +#define SSC_MCON_ENBV_SET(reg,val) (reg) = ((reg & ~SSC_MCON_ENBV) | (((val) & 0x1) << 22)) +/* Data Width Selection (20:16) */ +#define SSC_MCON_BM (0x1f << 16) +#define SSC_MCON_BM_VAL(val) (((val) & 0x1f) << 16) +#define SSC_MCON_BM_GET(val) ((((val) & SSC_MCON_BM) >> 16) & 0x1f) +#define SSC_MCON_BM_SET(reg,val) (reg) = ((reg & ~SSC_MCON_BM) | (((val) & 0x1f) << 16)) +/* Receive Underflow Error Enable (12) */ +#define SSC_MCON_RUEN (0x1 << 12) +#define SSC_MCON_RUEN_VAL(val) (((val) & 0x1) << 12) +#define SSC_MCON_RUEN_GET(val) ((((val) & SSC_MCON_RUEN) >> 12) & 0x1) +#define SSC_MCON_RUEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_RUEN) | (((val) & 0x1) << 12)) +/* Transmit Underflow Error Enable (11) */ +#define SSC_MCON_TUEN (0x1 << 11) +#define SSC_MCON_TUEN_VAL(val) (((val) & 0x1) << 11) +#define SSC_MCON_TUEN_GET(val) ((((val) & SSC_MCON_TUEN) >> 11) & 0x1) +#define SSC_MCON_TUEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TUEN) | (((val) & 0x1) << 11)) +/* Abort Error Enable (10) */ +#define SSC_MCON_AEN (0x1 << 10) +#define SSC_MCON_AEN_VAL(val) (((val) & 0x1) << 10) +#define SSC_MCON_AEN_GET(val) ((((val) & SSC_MCON_AEN) >> 10) & 0x1) +#define SSC_MCON_AEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_AEN) | (((val) & 0x1) << 10)) +/* Receive Overflow Error Enable (9) */ +#define SSC_MCON_REN (0x1 << 9) +#define SSC_MCON_REN_VAL(val) (((val) & 0x1) << 9) +#define SSC_MCON_REN_GET(val) ((((val) & SSC_MCON_REN) >> 9) & 0x1) +#define SSC_MCON_REN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_REN) | (((val) & 0x1) << 9)) +/* Transmit Overflow Error Enable (8) */ +#define SSC_MCON_TEN (0x1 << 8) +#define SSC_MCON_TEN_VAL(val) (((val) & 0x1) << 8) +#define SSC_MCON_TEN_GET(val) ((((val) & SSC_MCON_TEN) >> 8) & 0x1) +#define SSC_MCON_TEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TEN) | (((val) & 0x1) << 8)) +/* Loop Back Control (7) */ +#define SSC_MCON_LB (0x1 << 7) +#define SSC_MCON_LB_VAL(val) (((val) & 0x1) << 7) +#define SSC_MCON_LB_GET(val) ((((val) & SSC_MCON_LB) >> 7) & 0x1) +#define SSC_MCON_LB_SET(reg,val) (reg) = ((reg & ~SSC_MCON_LB) | (((val) & 0x1) << 7)) +/* Clock Polarity Control (6) */ +#define SSC_MCON_PO (0x1 << 6) +#define SSC_MCON_PO_VAL(val) (((val) & 0x1) << 6) +#define SSC_MCON_PO_GET(val) ((((val) & SSC_MCON_PO) >> 6) & 0x1) +#define SSC_MCON_PO_SET(reg,val) (reg) = ((reg & ~SSC_MCON_PO) | (((val) & 0x1) << 6)) +/* Clock Phase Control (5) */ +#define SSC_MCON_PH (0x1 << 5) +#define SSC_MCON_PH_VAL(val) (((val) & 0x1) << 5) +#define SSC_MCON_PH_GET(val) ((((val) & SSC_MCON_PH) >> 5) & 0x1) +#define SSC_MCON_PH_SET(reg,val) (reg) = ((reg & ~SSC_MCON_PH) | (((val) & 0x1) << 5)) +/* Heading Control (4) */ +#define SSC_MCON_HB (0x1 << 4) +#define SSC_MCON_HB_VAL(val) (((val) & 0x1) << 4) +#define SSC_MCON_HB_GET(val) ((((val) & SSC_MCON_HB) >> 4) & 0x1) +#define SSC_MCON_HB_SET(reg,val) (reg) = ((reg & ~SSC_MCON_HB) | (((val) & 0x1) << 4)) +/* Chip Select Enable (3) */ +#define SSC_MCON_CSBEN (0x1 << 3) +#define SSC_MCON_CSBEN_VAL(val) (((val) & 0x1) << 3) +#define SSC_MCON_CSBEN_GET(val) ((((val) & SSC_MCON_CSBEN) >> 3) & 0x1) +#define SSC_MCON_CSBEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_CSBEN) | (((val) & 0x1) << 3)) +/* Chip Select Invert (2) */ +#define SSC_MCON_CSBINV (0x1 << 2) +#define SSC_MCON_CSBINV_VAL(val) (((val) & 0x1) << 2) +#define SSC_MCON_CSBINV_GET(val) ((((val) & SSC_MCON_CSBINV) >> 2) & 0x1) +#define SSC_MCON_CSBINV_SET(reg,val) (reg) = ((reg & ~SSC_MCON_CSBINV) | (((val) & 0x1) << 2)) +/* Receive Off (1) */ +#define SSC_MCON_RXOFF (0x1 << 1) +#define SSC_MCON_RXOFF_VAL(val) (((val) & 0x1) << 1) +#define SSC_MCON_RXOFF_GET(val) ((((val) & SSC_MCON_RXOFF) >> 1) & 0x1) +#define SSC_MCON_RXOFF_SET(reg,val) (reg) = ((reg & ~SSC_MCON_RXOFF) | (((val) & 0x1) << 1)) +/* Transmit Off (0) */ +#define SSC_MCON_TXOFF (0x1) +#define SSC_MCON_TXOFF_VAL(val) (((val) & 0x1) << 0) +#define SSC_MCON_TXOFF_GET(val) ((((val) & SSC_MCON_TXOFF) >> 0) & 0x1) +#define SSC_MCON_TXOFF_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TXOFF) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * STATE Register + ******************************************************************************/ + +/* Receive End-of-Message (31) */ +#define SSC_STATE_RXEOM (0x1 << 31) +#define SSC_STATE_RXEOM_GET(val) ((((val) & SSC_STATE_RXEOM) >> 31) & 0x1) +/* Receive Byte Valid (30:28) */ +#define SSC_STATE_RXBV (0x7 << 28) +#define SSC_STATE_RXBV_GET(val) ((((val) & SSC_STATE_RXBV) >> 28) & 0x7) +/* Transmit End-of-Message (27) */ +#define SSC_STATE_TXEOM (0x1 << 27) +#define SSC_STATE_TXEOM_GET(val) ((((val) & SSC_STATE_TXEOM) >> 27) & 0x1) +/* Transmit Byte Valid (26:24) */ +#define SSC_STATE_TXBV (0x7 << 24) +#define SSC_STATE_TXBV_GET(val) ((((val) & SSC_STATE_TXBV) >> 24) & 0x7) +/* Bit Count Field (20:16) */ +#define SSC_STATE_BC (0x1f << 16) +#define SSC_STATE_BC_GET(val) ((((val) & SSC_STATE_BC) >> 16) & 0x1f) +/* Busy Flag (13) */ +#define SSC_STATE_BSY (0x1 << 13) +#define SSC_STATE_BSY_GET(val) ((((val) & SSC_STATE_BSY) >> 13) & 0x1) +/* Receive Underflow Error Flag (12) */ +#define SSC_STATE_RUE (0x1 << 12) +#define SSC_STATE_RUE_GET(val) ((((val) & SSC_STATE_RUE) >> 12) & 0x1) +/* Transmit Underflow Error Flag (11) */ +#define SSC_STATE_TUE (0x1 << 11) +#define SSC_STATE_TUE_GET(val) ((((val) & SSC_STATE_TUE) >> 11) & 0x1) +/* Abort Error Flag (10) */ +#define SSC_STATE_AE (0x1 << 10) +#define SSC_STATE_AE_GET(val) ((((val) & SSC_STATE_AE) >> 10) & 0x1) +/* Receive Error Flag (9) */ +#define SSC_STATE_RE (0x1 << 9) +#define SSC_STATE_RE_GET(val) ((((val) & SSC_STATE_RE) >> 9) & 0x1) +/* Transmit Error Flag (8) */ +#define SSC_STATE_TE (0x1 << 8) +#define SSC_STATE_TE_GET(val) ((((val) & SSC_STATE_TE) >> 8) & 0x1) +/* Mode Error Flag (7) */ +#define SSC_STATE_ME (0x1 << 7) +#define SSC_STATE_ME_GET(val) ((((val) & SSC_STATE_ME) >> 7) & 0x1) +/* Slave Selected (2) */ +#define SSC_STATE_SSEL (0x1 << 2) +#define SSC_STATE_SSEL_GET(val) ((((val) & SSC_STATE_SSEL) >> 2) & 0x1) +/* Master Select Bit (1) */ +#define SSC_STATE_MS (0x1 << 1) +#define SSC_STATE_MS_GET(val) ((((val) & SSC_STATE_MS) >> 1) & 0x1) +/* Enable Bit (0) */ +#define SSC_STATE_EN (0x1) +#define SSC_STATE_EN_GET(val) ((((val) & SSC_STATE_EN) >> 0) & 0x1) + +/******************************************************************************* + * WHBSTATE Register + ******************************************************************************/ + +/* Set Transmit Underflow Error Flag Bit (15) */ +#define SSC_WHBSTATE_SETTUE (0x1 << 15) +#define SSC_WHBSTATE_SETTUE_VAL(val) (((val) & 0x1) << 15) +#define SSC_WHBSTATE_SETTUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETTUE) | (val) & 1) << 15) +/* Set Abort Error Flag Bit (14) */ +#define SSC_WHBSTATE_SETAE (0x1 << 14) +#define SSC_WHBSTATE_SETAE_VAL(val) (((val) & 0x1) << 14) +#define SSC_WHBSTATE_SETAE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETAE) | (val) & 1) << 14) +/* Set Receive Error Flag Bit (13) */ +#define SSC_WHBSTATE_SETRE (0x1 << 13) +#define SSC_WHBSTATE_SETRE_VAL(val) (((val) & 0x1) << 13) +#define SSC_WHBSTATE_SETRE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETRE) | (val) & 1) << 13) +/* Set Transmit Error Flag Bit (12) */ +#define SSC_WHBSTATE_SETTE (0x1 << 12) +#define SSC_WHBSTATE_SETTE_VAL(val) (((val) & 0x1) << 12) +#define SSC_WHBSTATE_SETTE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETTE) | (val) & 1) << 12) +/* Clear Transmit Underflow Error Flag Bit (11) */ +#define SSC_WHBSTATE_CLRTUE (0x1 << 11) +#define SSC_WHBSTATE_CLRTUE_VAL(val) (((val) & 0x1) << 11) +#define SSC_WHBSTATE_CLRTUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRTUE) | (val) & 1) << 11) +/* Clear Abort Error Flag Bit (10) */ +#define SSC_WHBSTATE_CLRAE (0x1 << 10) +#define SSC_WHBSTATE_CLRAE_VAL(val) (((val) & 0x1) << 10) +#define SSC_WHBSTATE_CLRAE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRAE) | (val) & 1) << 10) +/* Clear Receive Error Flag Bit (9) */ +#define SSC_WHBSTATE_CLRRE (0x1 << 9) +#define SSC_WHBSTATE_CLRRE_VAL(val) (((val) & 0x1) << 9) +#define SSC_WHBSTATE_CLRRE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRRE) | (val) & 1) << 9) +/* Clear Transmit Error Flag Bit (8) */ +#define SSC_WHBSTATE_CLRTE (0x1 << 8) +#define SSC_WHBSTATE_CLRTE_VAL(val) (((val) & 0x1) << 8) +#define SSC_WHBSTATE_CLRTE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRTE) | (val) & 1) << 8) +/* Set Mode Error Flag Bit (7) */ +#define SSC_WHBSTATE_SETME (0x1 << 7) +#define SSC_WHBSTATE_SETME_VAL(val) (((val) & 0x1) << 7) +#define SSC_WHBSTATE_SETME_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETME) | (val) & 1) << 7) +/* Clear Mode Error Flag Bit (6) */ +#define SSC_WHBSTATE_CLRME (0x1 << 6) +#define SSC_WHBSTATE_CLRME_VAL(val) (((val) & 0x1) << 6) +#define SSC_WHBSTATE_CLRME_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRME) | (val) & 1) << 6) +/* Set Receive Underflow Error Bit (5) */ +#define SSC_WHBSTATE_SETRUE (0x1 << 5) +#define SSC_WHBSTATE_SETRUE_VAL(val) (((val) & 0x1) << 5) +#define SSC_WHBSTATE_SETRUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETRUE) | (val) & 1) << 5) +/* Clear Receive Underflow Error Bit (4) */ +#define SSC_WHBSTATE_CLRRUE (0x1 << 4) +#define SSC_WHBSTATE_CLRRUE_VAL(val) (((val) & 0x1) << 4) +#define SSC_WHBSTATE_CLRRUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRRUE) | (val) & 1) << 4) +/* Set Master Select Bit (3) */ +#define SSC_WHBSTATE_SETMS (0x1 << 3) +#define SSC_WHBSTATE_SETMS_VAL(val) (((val) & 0x1) << 3) +#define SSC_WHBSTATE_SETMS_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETMS) | (val) & 1) << 3) +/* Clear Master Select Bit (2) */ +#define SSC_WHBSTATE_CLRMS (0x1 << 2) +#define SSC_WHBSTATE_CLRMS_VAL(val) (((val) & 0x1) << 2) +#define SSC_WHBSTATE_CLRMS_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRMS) | (val) & 1) << 2) +/* Set Enable Bit (1) */ +#define SSC_WHBSTATE_SETEN (0x1 << 1) +#define SSC_WHBSTATE_SETEN_VAL(val) (((val) & 0x1) << 1) +#define SSC_WHBSTATE_SETEN_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETEN) | (val) & 1) << 1) +/* Clear Enable Bit (0) */ +#define SSC_WHBSTATE_CLREN (0x1) +#define SSC_WHBSTATE_CLREN_VAL(val) (((val) & 0x1) << 0) +#define SSC_WHBSTATE_CLREN_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLREN) | (val) & 1) << 0) + +/******************************************************************************* + * TB Register + ******************************************************************************/ + +/* Transmit Data Register Value (31:0) */ +#define SSC_TB_TB_VAL (0xFFFFFFFFL) +#define SSC_TB_TB_VAL_VAL(val) (((val) & 0xFFFFFFFFL) << 0) +#define SSC_TB_TB_VAL_GET(val) ((((val) & SSC_TB_TB_VAL) >> 0) & 0xFFFFFFFFL) +#define SSC_TB_TB_VAL_SET(reg,val) (reg) = ((reg & ~SSC_TB_TB_VAL) | (((val) & 0xFFFFFFFFL) << 0)) + +/******************************************************************************* + * RB Register + ******************************************************************************/ + +/* Receive Data Register Value (31:0) */ +#define SSC_RB_RB_VAL (0xFFFFFFFFL) +#define SSC_RB_RB_VAL_GET(val) ((((val) & SSC_RB_RB_VAL) >> 0) & 0xFFFFFFFFL) + +/******************************************************************************* + * FSTAT Register + ******************************************************************************/ + +/* Transmit FIFO Filling Level (13:8) */ +#define SSC_FSTAT_TXFFL (0x3f << 8) +#define SSC_FSTAT_TXFFL_GET(val) ((((val) & SSC_FSTAT_TXFFL) >> 8) & 0x3f) +/* Receive FIFO Filling Level (5:0) */ +#define SSC_FSTAT_RXFFL (0x3f) +#define SSC_FSTAT_RXFFL_GET(val) ((((val) & SSC_FSTAT_RXFFL) >> 0) & 0x3f) + +/******************************************************************************* + * PISEL Register + ******************************************************************************/ + +/* Slave Mode Clock Input Select (2) */ +#define SSC_PISEL_CIS (0x1 << 2) +#define SSC_PISEL_CIS_VAL(val) (((val) & 0x1) << 2) +#define SSC_PISEL_CIS_GET(val) ((((val) & SSC_PISEL_CIS) >> 2) & 0x1) +#define SSC_PISEL_CIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_CIS) | (((val) & 0x1) << 2)) +/* Slave Mode Receiver Input Select (1) */ +#define SSC_PISEL_SIS (0x1 << 1) +#define SSC_PISEL_SIS_VAL(val) (((val) & 0x1) << 1) +#define SSC_PISEL_SIS_GET(val) ((((val) & SSC_PISEL_SIS) >> 1) & 0x1) +#define SSC_PISEL_SIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_SIS) | (((val) & 0x1) << 1)) +/* Master Mode Receiver Input Select (0) */ +#define SSC_PISEL_MIS (0x1) +#define SSC_PISEL_MIS_VAL(val) (((val) & 0x1) << 0) +#define SSC_PISEL_MIS_GET(val) ((((val) & SSC_PISEL_MIS) >> 0) & 0x1) +#define SSC_PISEL_MIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_MIS) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * RXFCON Register + ******************************************************************************/ + +/* Receive FIFO Interrupt Trigger Level (13:8) */ +#define SSC_RXFCON_RXFITL (0x3f << 8) +#define SSC_RXFCON_RXFITL_VAL(val) (((val) & 0x3f) << 8) +#define SSC_RXFCON_RXFITL_GET(val) ((((val) & SSC_RXFCON_RXFITL) >> 8) & 0x3f) +#define SSC_RXFCON_RXFITL_SET(reg,val) (reg) = ((reg & ~SSC_RXFCON_RXFITL) | (((val) & 0x3f) << 8)) +/* Receive FIFO Flush (1) */ +#define SSC_RXFCON_RXFLU (0x1 << 1) +#define SSC_RXFCON_RXFLU_VAL(val) (((val) & 0x1) << 1) +#define SSC_RXFCON_RXFLU_SET(reg,val) (reg) = (((reg & ~SSC_RXFCON_RXFLU) | (val) & 1) << 1) +/* Receive FIFO Enable (0) */ +#define SSC_RXFCON_RXFEN (0x1) +#define SSC_RXFCON_RXFEN_VAL(val) (((val) & 0x1) << 0) +#define SSC_RXFCON_RXFEN_GET(val) ((((val) & SSC_RXFCON_RXFEN) >> 0) & 0x1) +#define SSC_RXFCON_RXFEN_SET(reg,val) (reg) = ((reg & ~SSC_RXFCON_RXFEN) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * TXFCON Register + ******************************************************************************/ + +/* Transmit FIFO Interrupt Trigger Level (13:8) */ +#define SSC_TXFCON_TXFITL (0x3f << 8) +#define SSC_TXFCON_TXFITL_VAL(val) (((val) & 0x3f) << 8) +#define SSC_TXFCON_TXFITL_GET(val) ((((val) & SSC_TXFCON_TXFITL) >> 8) & 0x3f) +#define SSC_TXFCON_TXFITL_SET(reg,val) (reg) = ((reg & ~SSC_TXFCON_TXFITL) | (((val) & 0x3f) << 8)) +/* Transmit FIFO Flush (1) */ +#define SSC_TXFCON_TXFLU (0x1 << 1) +#define SSC_TXFCON_TXFLU_VAL(val) (((val) & 0x1) << 1) +#define SSC_TXFCON_TXFLU_SET(reg,val) (reg) = (((reg & ~SSC_TXFCON_TXFLU) | (val) & 1) << 1) +/* Transmit FIFO Enable (0) */ +#define SSC_TXFCON_TXFEN (0x1) +#define SSC_TXFCON_TXFEN_VAL(val) (((val) & 0x1) << 0) +#define SSC_TXFCON_TXFEN_GET(val) ((((val) & SSC_TXFCON_TXFEN) >> 0) & 0x1) +#define SSC_TXFCON_TXFEN_SET(reg,val) (reg) = ((reg & ~SSC_TXFCON_TXFEN) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * BR Register + ******************************************************************************/ + +/* Baudrate Timer Reload Register Value (15:0) */ +#define SSC_BR_BR_VAL (0xffff) +#define SSC_BR_BR_VAL_VAL(val) (((val) & 0xffff) << 0) +#define SSC_BR_BR_VAL_GET(val) ((((val) & SSC_BR_BR_VAL) >> 0) & 0xffff) +#define SSC_BR_BR_VAL_SET(reg,val) (reg) = ((reg & ~SSC_BR_BR_VAL) | (((val) & 0xffff) << 0)) + +/******************************************************************************* + * BRSTAT Register + ******************************************************************************/ + +/* Baudrate Timer Register Value (15:0) */ +#define SSC_BRSTAT_BT_VAL (0xffff) +#define SSC_BRSTAT_BT_VAL_GET(val) ((((val) & SSC_BRSTAT_BT_VAL) >> 0) & 0xffff) + +/******************************************************************************* + * SFCON Register + ******************************************************************************/ + +/* Pause Length (31:22) */ +#define SSC_SFCON_PLEN (0x3ff << 22) +#define SSC_SFCON_PLEN_VAL(val) (((val) & 0x3ff) << 22) +#define SSC_SFCON_PLEN_GET(val) ((((val) & SSC_SFCON_PLEN) >> 22) & 0x3ff) +#define SSC_SFCON_PLEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_PLEN) | (((val) & 0x3ff) << 22)) +/* Stop After Pause (20) */ +#define SSC_SFCON_STOP (0x1 << 20) +#define SSC_SFCON_STOP_VAL(val) (((val) & 0x1) << 20) +#define SSC_SFCON_STOP_GET(val) ((((val) & SSC_SFCON_STOP) >> 20) & 0x1) +#define SSC_SFCON_STOP_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_STOP) | (((val) & 0x1) << 20)) +/* Idle Clock Configuration (19:18) */ +#define SSC_SFCON_ICLK (0x3 << 18) +#define SSC_SFCON_ICLK_VAL(val) (((val) & 0x3) << 18) +#define SSC_SFCON_ICLK_GET(val) ((((val) & SSC_SFCON_ICLK) >> 18) & 0x3) +#define SSC_SFCON_ICLK_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_ICLK) | (((val) & 0x3) << 18)) +/* Idle Data Configuration (17:16) */ +#define SSC_SFCON_IDAT (0x3 << 16) +#define SSC_SFCON_IDAT_VAL(val) (((val) & 0x3) << 16) +#define SSC_SFCON_IDAT_GET(val) ((((val) & SSC_SFCON_IDAT) >> 16) & 0x3) +#define SSC_SFCON_IDAT_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IDAT) | (((val) & 0x3) << 16)) +/* Data Length (15:4) */ +#define SSC_SFCON_DLEN (0xfff << 4) +#define SSC_SFCON_DLEN_VAL(val) (((val) & 0xfff) << 4) +#define SSC_SFCON_DLEN_GET(val) ((((val) & SSC_SFCON_DLEN) >> 4) & 0xfff) +#define SSC_SFCON_DLEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_DLEN) | (((val) & 0xfff) << 4)) +/* Enable Interrupt After Pause (3) */ +#define SSC_SFCON_IAEN (0x1 << 3) +#define SSC_SFCON_IAEN_VAL(val) (((val) & 0x1) << 3) +#define SSC_SFCON_IAEN_GET(val) ((((val) & SSC_SFCON_IAEN) >> 3) & 0x1) +#define SSC_SFCON_IAEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IAEN) | (((val) & 0x1) << 3)) +/* Enable Interrupt Before Pause (2) */ +#define SSC_SFCON_IBEN (0x1 << 2) +#define SSC_SFCON_IBEN_VAL(val) (((val) & 0x1) << 2) +#define SSC_SFCON_IBEN_GET(val) ((((val) & SSC_SFCON_IBEN) >> 2) & 0x1) +#define SSC_SFCON_IBEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IBEN) | (((val) & 0x1) << 2)) +/* Serial Frame Enable (0) */ +#define SSC_SFCON_SFEN (0x1) +#define SSC_SFCON_SFEN_VAL(val) (((val) & 0x1) << 0) +#define SSC_SFCON_SFEN_GET(val) ((((val) & SSC_SFCON_SFEN) >> 0) & 0x1) +#define SSC_SFCON_SFEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_SFEN) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * SFSTAT Register + ******************************************************************************/ + +/* Pause Count (31:22) */ +#define SSC_SFSTAT_PCNT (0x3ff << 22) +#define SSC_SFSTAT_PCNT_GET(val) ((((val) & SSC_SFSTAT_PCNT) >> 22) & 0x3ff) +/* Data Bit Count (15:4) */ +#define SSC_SFSTAT_DCNT (0xfff << 4) +#define SSC_SFSTAT_DCNT_GET(val) ((((val) & SSC_SFSTAT_DCNT) >> 4) & 0xfff) +/* Pause Busy (1) */ +#define SSC_SFSTAT_PBSY (0x1 << 1) +#define SSC_SFSTAT_PBSY_GET(val) ((((val) & SSC_SFSTAT_PBSY) >> 1) & 0x1) +/* Data Busy (0) */ +#define SSC_SFSTAT_DBSY (0x1) +#define SSC_SFSTAT_DBSY_GET(val) ((((val) & SSC_SFSTAT_DBSY) >> 0) & 0x1) + +/******************************************************************************* + * GPOCON Register + ******************************************************************************/ + +/* Output OUTn Is Chip Select (15:8) */ +#define SSC_GPOCON_ISCSBN (0xff << 8) +#define SSC_GPOCON_ISCSBN_VAL(val) (((val) & 0xff) << 8) +#define SSC_GPOCON_ISCSBN_GET(val) ((((val) & SSC_GPOCON_ISCSBN) >> 8) & 0xff) +#define SSC_GPOCON_ISCSBN_SET(reg,val) (reg) = ((reg & ~SSC_GPOCON_ISCSBN) | (((val) & 0xff) << 8)) +/* Invert Output OUTn (7:0) */ +#define SSC_GPOCON_INVOUTN (0xff) +#define SSC_GPOCON_INVOUTN_VAL(val) (((val) & 0xff) << 0) +#define SSC_GPOCON_INVOUTN_GET(val) ((((val) & SSC_GPOCON_INVOUTN) >> 0) & 0xff) +#define SSC_GPOCON_INVOUTN_SET(reg,val) (reg) = ((reg & ~SSC_GPOCON_INVOUTN) | (((val) & 0xff) << 0)) + +/******************************************************************************* + * GPOSTAT Register + ******************************************************************************/ + +/* Output Register Bit n (7:0) */ +#define SSC_GPOSTAT_OUTN (0xff) +#define SSC_GPOSTAT_OUTN_GET(val) ((((val) & SSC_GPOSTAT_OUTN) >> 0) & 0xff) + +/******************************************************************************* + * WHBGPOSTAT + ******************************************************************************/ + +/* Set Output Register Bit n (15:8) */ +#define SSC_WHBGPOSTAT_SETOUTN (0xff << 8) +#define SSC_WHBGPOSTAT_SETOUTN_VAL(val) (((val) & 0xff) << 8) +#define SSC_WHBGPOSTAT_SETOUTN_SET(reg,val) (reg) = (((reg & ~SSC_WHBGPOSTAT_SETOUTN) | (val) & 1) << 8) +/* Clear Output Register Bit n (7:0) */ +#define SSC_WHBGPOSTAT_CLROUTN (0xff) +#define SSC_WHBGPOSTAT_CLROUTN_VAL(val) (((val) & 0xff) << 0) +#define SSC_WHBGPOSTAT_CLROUTN_SET(reg,val) (reg) = (((reg & ~SSC_WHBGPOSTAT_CLROUTN) | (val) & 1) << 0) + +/******************************************************************************* + * RXREQ Register + ******************************************************************************/ + +/* Receive Count Value (15:0) */ +#define SSC_RXREQ_RXCNT (0xffff) +#define SSC_RXREQ_RXCNT_VAL(val) (((val) & 0xffff) << 0) +#define SSC_RXREQ_RXCNT_GET(val) ((((val) & SSC_RXREQ_RXCNT) >> 0) & 0xffff) +#define SSC_RXREQ_RXCNT_SET(reg,val) (reg) = ((reg & ~SSC_RXREQ_RXCNT) | (((val) & 0xffff) << 0)) + +/******************************************************************************* + * RXCNT Register + ******************************************************************************/ + +/* Receive To Do Value (15:0) */ +#define SSC_RXCNT_TODO (0xffff) +#define SSC_RXCNT_TODO_GET(val) ((((val) & SSC_RXCNT_TODO) >> 0) & 0xffff) + +/******************************************************************************* + * DMA_CON Register + ******************************************************************************/ + +/* Receive Class (3:2) */ +#define SSC_DMA_CON_RXCLS (0x3 << 2) +#define SSC_DMA_CON_RXCLS_VAL(val) (((val) & 0x3) << 2) +#define SSC_DMA_CON_RXCLS_GET(val) ((((val) & SSC_DMA_CON_RXCLS) >> 2) & 0x3) +#define SSC_DMA_CON_RXCLS_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_RXCLS) | (((val) & 0x3) << 2)) +/* Transmit Path On (1) */ +#define SSC_DMA_CON_TXON (0x1 << 1) +#define SSC_DMA_CON_TXON_VAL(val) (((val) & 0x1) << 1) +#define SSC_DMA_CON_TXON_GET(val) ((((val) & SSC_DMA_CON_TXON) >> 1) & 0x1) +#define SSC_DMA_CON_TXON_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_TXON) | (((val) & 0x1) << 1)) +/* Receive Path On (0) */ +#define SSC_DMA_CON_RXON (0x1) +#define SSC_DMA_CON_RXON_VAL(val) (((val) & 0x1) << 0) +#define SSC_DMA_CON_RXON_GET(val) ((((val) & SSC_DMA_CON_RXON) >> 0) & 0x1) +#define SSC_DMA_CON_RXON_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_RXON) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * IRNEN Register + ******************************************************************************/ + +/* Frame End Interrupt Request Enable (3) */ +#define SSC_IRNEN_F (0x1 << 3) +#define SSC_IRNEN_F_VAL(val) (((val) & 0x1) << 3) +#define SSC_IRNEN_F_GET(val) ((((val) & SSC_IRNEN_F) >> 3) & 0x1) +#define SSC_IRNEN_F_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_F) | (((val) & 0x1) << 3)) +/* Error Interrupt Request Enable (2) */ +#define SSC_IRNEN_E (0x1 << 2) +#define SSC_IRNEN_E_VAL(val) (((val) & 0x1) << 2) +#define SSC_IRNEN_E_GET(val) ((((val) & SSC_IRNEN_E) >> 2) & 0x1) +#define SSC_IRNEN_E_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_E) | (((val) & 0x1) << 2)) +/* Receive Interrupt Request Enable (1) */ +#define SSC_IRNEN_R (0x1 << 1) +#define SSC_IRNEN_R_VAL(val) (((val) & 0x1) << 1) +#define SSC_IRNEN_R_GET(val) ((((val) & SSC_IRNEN_R) >> 1) & 0x1) +#define SSC_IRNEN_R_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_R) | (((val) & 0x1) << 1)) +/* Transmit Interrupt Request Enable (0) */ +#define SSC_IRNEN_T (0x1) +#define SSC_IRNEN_T_VAL(val) (((val) & 0x1) << 0) +#define SSC_IRNEN_T_GET(val) ((((val) & SSC_IRNEN_T) >> 0) & 0x1) +#define SSC_IRNEN_T_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_T) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * IRNICR Register + ******************************************************************************/ + +/* Frame End Interrupt Request (3) */ +#define SSC_IRNICR_F (0x1 << 3) +#define SSC_IRNICR_F_GET(val) ((((val) & SSC_IRNICR_F) >> 3) & 0x1) +/* Error Interrupt Request (2) */ +#define SSC_IRNICR_E (0x1 << 2) +#define SSC_IRNICR_E_GET(val) ((((val) & SSC_IRNICR_E) >> 2) & 0x1) +/* Receive Interrupt Request (1) */ +#define SSC_IRNICR_R (0x1 << 1) +#define SSC_IRNICR_R_GET(val) ((((val) & SSC_IRNICR_R) >> 1) & 0x1) +/* Transmit Interrupt Request (0) */ +#define SSC_IRNICR_T (0x1) +#define SSC_IRNICR_T_GET(val) ((((val) & SSC_IRNICR_T) >> 0) & 0x1) + +/******************************************************************************* + * IRNCR Register + ******************************************************************************/ + +/* Frame End Interrupt Request (3) */ +#define SSC_IRNCR_F (0x1 << 3) +#define SSC_IRNCR_F_GET(val) ((((val) & SSC_IRNCR_F) >> 3) & 0x1) +/* Error Interrupt Request (2) */ +#define SSC_IRNCR_E (0x1 << 2) +#define SSC_IRNCR_E_GET(val) ((((val) & SSC_IRNCR_E) >> 2) & 0x1) +/* Receive Interrupt Request (1) */ +#define SSC_IRNCR_R (0x1 << 1) +#define SSC_IRNCR_R_GET(val) ((((val) & SSC_IRNCR_R) >> 1) & 0x1) +/* Transmit Interrupt Request (0) */ +#define SSC_IRNCR_T (0x1) +#define SSC_IRNCR_T_GET(val) ((((val) & SSC_IRNCR_T) >> 0) & 0x1) + +#endif /* __SSC_H */ diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/status_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/status_reg.h new file mode 100644 index 0000000000..100230fa7c --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/status_reg.h @@ -0,0 +1,130 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __STATUS_REG_H +#define __STATUS_REG_H + +#define status_r32(reg) ltq_r32(&status->reg) +#define status_w32(val, reg) ltq_w32(val, &status->reg) +#define status_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &status->reg) + +/** STATUS register structure */ +struct svip_reg_status { + unsigned long fuse_deu; /* 0x0000 */ + unsigned long fuse_cpu; /* 0x0004 */ + unsigned long fuse_pll; /* 0x0008 */ + unsigned long chipid; /* 0x000C */ + unsigned long config; /* 0x0010 */ + unsigned long chip_loc; /* 0x0014 */ + unsigned long fuse_spare; /* 0x0018 */ +}; + +/******************************************************************************* + * Fuse for DEU Settings + ******************************************************************************/ + +/* Fuse for Enabling the TRNG (6) */ +#define STATUS_FUSE_DEU_TRNG (0x1 << 6) +#define STATUS_FUSE_DEU_TRNG_GET(val) ((((val) & STATUS_FUSE_DEU_TRNG) >> 6) & 0x1) +/* Fuse for Enabling the DES Submodule (5) */ +#define STATUS_FUSE_DEU_DES (0x1 << 5) +#define STATUS_FUSE_DEU_DES_GET(val) ((((val) & STATUS_FUSE_DEU_DES) >> 5) & 0x1) +/* Fuse for Enabling the 3DES Submodule (4) */ +#define STATUS_FUSE_DEU_3DES (0x1 << 4) +#define STATUS_FUSE_DEU_3DES_GET(val) ((((val) & STATUS_FUSE_DEU_3DES) >> 4) & 0x1) +/* Fuse for Enabling the AES Submodule (3) */ +#define STATUS_FUSE_DEU_AES (0x1 << 3) +#define STATUS_FUSE_DEU_AES_GET(val) ((((val) & STATUS_FUSE_DEU_AES) >> 3) & 0x1) +/* Fuse for Enabling the HASH Submodule (2) */ +#define STATUS_FUSE_DEU_HASH (0x1 << 2) +#define STATUS_FUSE_DEU_HASH_GET(val) ((((val) & STATUS_FUSE_DEU_HASH) >> 2) & 0x1) +/* Fuse for Enabling the ARC4 Submodule (1) */ +#define STATUS_FUSE_DEU_ARC4 (0x1 << 1) +#define STATUS_FUSE_DEU_ARC4_GET(val) ((((val) & STATUS_FUSE_DEU_ARC4) >> 1) & 0x1) +/* Fuse for Enabling the DEU Module (0) */ +#define STATUS_FUSE_DEU_DEU (0x1) +#define STATUS_FUSE_DEU_DEU_GET(val) ((((val) & STATUS_FUSE_DEU_DEU) >> 0) & 0x1) + +/******************************************************************************* + * Fuse for CPU Settings + ******************************************************************************/ + +/* Fuse for Enabling CPU5 (5) */ +#define STATUS_FUSE_CPU_CPU5 (0x1 << 5) +#define STATUS_FUSE_CPU_CPU5_GET(val) ((((val) & STATUS_FUSE_CPU_CPU5) >> 5) & 0x1) +/* Fuse for Enabling the CPU4 (4) */ +#define STATUS_FUSE_CPU_CPU4 (0x1 << 4) +#define STATUS_FUSE_CPU_CPU4_GET(val) ((((val) & STATUS_FUSE_CPU_CPU4) >> 4) & 0x1) +/* Fuse for Enabling the CPU3 (3) */ +#define STATUS_FUSE_CPU_CPU3 (0x1 << 3) +#define STATUS_FUSE_CPU_CPU3_GET(val) ((((val) & STATUS_FUSE_CPU_CPU3) >> 3) & 0x1) +/* Fuse for Enabling the CPU2 (2) */ +#define STATUS_FUSE_CPU_CPU2 (0x1 << 2) +#define STATUS_FUSE_CPU_CPU2_GET(val) ((((val) & STATUS_FUSE_CPU_CPU2) >> 2) & 0x1) +/* Fuse for Enabling the CPU1 (1) */ +#define STATUS_FUSE_CPU_CPU1 (0x1 << 1) +#define STATUS_FUSE_CPU_CPU1_GET(val) ((((val) & STATUS_FUSE_CPU_CPU1) >> 1) & 0x1) +/* Fuse for Enabling the CPU0 (0) */ +#define STATUS_FUSE_CPU_CPU0 (0x1) +#define STATUS_FUSE_CPU_CPU0_GET(val) ((((val) & STATUS_FUSE_CPU_CPU0) >> 0) & 0x1) + +/******************************************************************************* + * Fuse for PLL Settings + ******************************************************************************/ + +/* Fuse for Enabling PLL (7:0) */ +#define STATUS_FUSE_PLL_PLL (0xff) +#define STATUS_FUSE_PLL_PLL_GET(val) ((((val) & STATUS_FUSE_PLL_PLL) >> 0) & 0xff) + +/******************************************************************************* + * Chip Identification Register + ******************************************************************************/ + +/* Chip Version Number (31:28) */ +#define STATUS_CHIPID_VERSION (0xf << 28) +#define STATUS_CHIPID_VERSION_GET(val) ((((val) & STATUS_CHIPID_VERSION) >> 28) & 0xf) +/* Part Number (27:12) */ +#define STATUS_CHIPID_PART_NUMBER (0xffff << 12) +#define STATUS_CHIPID_PART_NUMBER_GET(val) ((((val) & STATUS_CHIPID_PART_NUMBER) >> 12) & 0xffff) +/* Manufacturer ID (11:1) */ +#define STATUS_CHIPID_MANID (0x7ff << 1) +#define STATUS_CHIPID_MANID_GET(val) ((((val) & STATUS_CHIPID_MANID) >> 1) & 0x7ff) + +/******************************************************************************* + * Chip Configuration Register + ******************************************************************************/ + +/* Number of Analog Channels (8:5) */ +#define STATUS_CONFIG_ANA_CHAN (0xf << 5) +#define STATUS_CONFIG_ANA_CHAN_GET(val) ((((val) & STATUS_CONFIG_ANA_CHAN) >> 5) & 0xf) +/* Clock Mode (4) */ +#define STATUS_CONFIG_CLK_MODE (0x1 << 1) +#define STATUS_CONFIG_CLK_MODE_GET(val) ((((val) & STATUS_CONFIG_CLK_MODE) >> 4) & 0x1) +/* Subversion Number (3:0) */ +#define STATUS_CONFIG_SUB_VERS (0xF) +#define STATUS_CONFIG_SUB_VERS_GET(val) ((((val) & STATUS_SUBVER_SUB_VERS) >> 0) & 0xF) + +/******************************************************************************* + * Chip Location Register + ******************************************************************************/ + +/* Chip Lot ID (31:16) */ +#define STATUS_CHIP_LOC_CHIP_LOT (0xffff << 16) +#define STATUS_CHIP_LOC_CHIP_LOT_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_LOT) >> 16) & 0xffff) +/* Chip X Coordinate (15:8) */ +#define STATUS_CHIP_LOC_CHIP_X (0xff << 8) +#define STATUS_CHIP_LOC_CHIP_X_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_X) >> 8) & 0xff) +/* Chip Y Coordinate (7:0) */ +#define STATUS_CHIP_LOC_CHIP_Y (0xff) +#define STATUS_CHIP_LOC_CHIP_Y_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_Y) >> 0) & 0xff) + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_dma.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_dma.h new file mode 100644 index 0000000000..5c34bb6902 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_dma.h @@ -0,0 +1,245 @@ +/************************************************************************ + * + * Copyright (c) 2007 + * Infineon Technologies AG + * St. Martin Strasse 53; 81669 Muenchen; Germany + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + ************************************************************************/ + +#ifndef __SVIP_DMA_H +#define __SVIP_DMA_H + +#define LTQ_DMA_CH_ON 1 +#define LTQ_DMA_CH_OFF 0 +#define LTQ_DMA_CH_DEFAULT_WEIGHT 100; + +#define DMA_OWN 1 +#define CPU_OWN 0 +#define DMA_MAJOR 250 + +/* Descriptors */ +#define DMA_DESC_OWN_CPU 0x0 +#define DMA_DESC_OWN_DMA 0x80000000 +#define DMA_DESC_CPT_SET 0x40000000 +#define DMA_DESC_SOP_SET 0x20000000 +#define DMA_DESC_EOP_SET 0x10000000 + +struct rx_desc { + union { + struct { +#ifdef CONFIG_CPU_LITTLE_ENDIAN + volatile u32 data_length:16; + volatile u32 reserve2:7; + volatile u32 byte_offset:2; + volatile u32 reserve1:3; + volatile u32 eop:1; + volatile u32 sop:1; + volatile u32 c:1; + volatile u32 own:1; +#else + volatile u32 own:1; + volatile u32 c:1; + volatile u32 sop:1; + volatile u32 eop:1; + volatile u32 reserve1:3; + volatile u32 byte_offset:2; + volatile u32 reserve2:7; + volatile u32 data_length:16; +#endif + } field; + + volatile u32 word; + } status; + + volatile u32 data_pointer; +}; + +struct tx_desc { + union { + struct { +#ifdef CONFIG_CPU_LITTLE_ENDIAN + volatile u32 data_length:16; + volatile u32 reserved:7; + volatile u32 byte_offset:5; + volatile u32 eop:1; + volatile u32 sop:1; + volatile u32 c:1; + volatile u32 own:1; +#else + volatile u32 own:1; + volatile u32 c:1; + volatile u32 sop:1; + volatile u32 eop:1; + volatile u32 byte_offset:5; + volatile u32 reserved:7; + volatile u32 data_length:16; +#endif + } field; + + volatile u32 word; + } status; + + volatile u32 data_pointer; +}; + +/* DMA pseudo interrupts notified to switch driver */ +#define RCV_INT 0x01 +#define TX_BUF_FULL_INT 0x02 +#define TRANSMIT_CPT_INT 0x04 +#define CHANNEL_CLOSED 0x10 + +/* Parameters for switch DMA device */ +#define DEFAULT_SW_CHANNEL_WEIGHT 3 +#define DEFAULT_SW_PORT_WEIGHT 7 + +#define DEFAULT_SW_TX_BURST_LEN 2 /* 2 words, 4 words, 8 words */ +#define DEFAULT_SW_RX_BURST_LEN 2 /* 2 words, 4 words, 8 words */ + +#define DEFAULT_SW_TX_CHANNEL_NUM 4 +#define DEFAULT_SW_RX_CHANNEL_NUM 4 + +#define DEFAULT_SW_TX_CHANNEL_DESCR_NUM 20 +#define DEFAULT_SW_RX_CHANNEL_DESCR_NUM 20 + +/* Parameters for SSC DMA device */ +#define DEFAULT_SSC_CHANNEL_WEIGHT 3 +#define DEFAULT_SSC_PORT_WEIGHT 7 + +#define DEFAULT_SSC_TX_CHANNEL_CLASS 3 +#define DEFAULT_SSC_RX_CHANNEL_CLASS 0 + +#define DEFAULT_SSC_TX_BURST_LEN 2 /* 2 words, 4 words, 8 words */ +#define DEFAULT_SSC_RX_BURST_LEN 2 /* 2 words, 4 words, 8 words */ + +#define DEFAULT_SSC0_TX_CHANNEL_NUM 1 +#define DEFAULT_SSC0_RX_CHANNEL_NUM 1 +#define DEFAULT_SSC1_TX_CHANNEL_NUM 1 +#define DEFAULT_SSC1_RX_CHANNEL_NUM 1 + +#define DEFAULT_SSC_TX_CHANNEL_DESCR_NUM 10 +#define DEFAULT_SSC_RX_CHANNEL_DESCR_NUM 10 + +/* Parameters for memory DMA device */ +#define DEFAULT_MEM_CHANNEL_WEIGHT 3 +#define DEFAULT_MEM_PORT_WEIGHT 7 + +#define DEFAULT_MEM_TX_BURST_LEN 4 /* 2 words, 4 words, 8 words */ +#define DEFAULT_MEM_RX_BURST_LEN 4 /* 2 words, 4 words, 8 words */ + +#define DEFAULT_MEM_TX_CHANNEL_NUM 1 +#define DEFAULT_MEM_RX_CHANNEL_NUM 1 + +#define DEFAULT_MEM_TX_CHANNEL_DESCR_NUM 2 +#define DEFAULT_MEM_RX_CHANNEL_DESCR_NUM 2 + +/* Parameters for DEU DMA device */ +#define DEFAULT_DEU_CHANNEL_WEIGHT 1 +#define DEFAULT_DEU_PORT_WEIGHT 1 + +#define DEFAULT_DEU_TX_BURST_LEN 4 /* 2 words, 4 words, 8 words */ +#define DEFAULT_DEU_RX_BURST_LEN 4 /* 2 words, 4 words, 8 words */ + +#define DEFAULT_DEU_TX_CHANNEL_DESCR_NUM 20 +#define DEFAULT_DEU_RX_CHANNEL_DESCR_NUM 20 + +#define DMA_DESCR_NUM 30 /* number of descriptors per channel */ + +enum dma_dir_t { + DIR_RX = 0, + DIR_TX = 1, +}; + +struct dma_device_info; + +struct dma_channel_info { + /*Pointer to the peripheral device who is using this channel*/ + /*const*/ struct dma_device_info *dma_dev; + /*direction*/ + const enum dma_dir_t dir; /*RX or TX*/ + /*class for this channel for QoS*/ + int pri; + /*irq number*/ + const int irq; + /*relative channel number*/ + const int rel_chan_no; + /*absolute channel number*/ + int abs_chan_no; + + /*specify byte_offset*/ + int byte_offset; + int tx_weight; + + /*descriptor parameter*/ + int desc_base; + int desc_len; + int curr_desc; + int prev_desc;/*only used if it is a tx channel*/ + + /*weight setting for WFQ algorithm*/ + int weight; + int default_weight; + + int packet_size; + + /*status of this channel*/ + int control; /*on or off*/ + int xfer_cnt; + int dur; /*descriptor underrun*/ + + /**optional information for the upper layer devices*/ + void *opt[DMA_DESCR_NUM]; + + /*channel operations*/ + int (*open)(struct dma_channel_info *ch); + int (*close)(struct dma_channel_info *ch); + int (*reset)(struct dma_channel_info *ch); + void (*enable_irq)(struct dma_channel_info *ch); + void (*disable_irq)(struct dma_channel_info *ch); +}; + + +struct dma_device_info { + /*device name of this peripheral*/ + const char device_name[16]; + const int max_rx_chan_num; + const int max_tx_chan_num; + int drop_enable; + + int reserved; + + int tx_burst_len; + int rx_burst_len; + int tx_weight; + + int current_tx_chan; + int current_rx_chan; + int num_tx_chan; + int num_rx_chan; + int tx_endianness_mode; + int rx_endianness_mode; + struct dma_channel_info *tx_chan[4]; + struct dma_channel_info *rx_chan[4]; + + /*functions, optional*/ + u8 *(*buffer_alloc)(int len,int *offset, void **opt); + void (*buffer_free)(u8 *dataptr, void *opt); + int (*intr_handler)(struct dma_device_info *dma_dev, int status); + + /* used by peripheral driver only */ + void *priv; +}; + +struct dma_device_info *dma_device_reserve(char *dev_name); +int dma_device_release(struct dma_device_info *dma_dev); +int dma_device_register(struct dma_device_info *dma_dev); +int dma_device_unregister(struct dma_device_info *dma_dev); +int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt); +int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, + int len, void *opt); + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h new file mode 100644 index 0000000000..bca8df9fd5 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h @@ -0,0 +1,35 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2010 Lantiq + */ +#ifndef __SVIP_IRQ_H +#define __SVIP_IRQ_H + +#define IM_NUM 6 + +#define INT_NUM_IRQ0 8 +#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) +#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32) +#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32) +#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32) +#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32) +#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32) +#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0) + +#define INT_NUM_IM5_IRL0 (INT_NUM_IRQ0 + 160) +#define MIPS_CPU_TIMER_IRQ (INT_NUM_IM5_IRL0 + 2) + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_mux.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_mux.h new file mode 100644 index 0000000000..8ca3285f2c --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_mux.h @@ -0,0 +1,467 @@ +/************************************************************************ + * + * Copyright (c) 2007 + * Infineon Technologies AG + * St. Martin Strasse 53; 81669 Muenchen; Germany + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + ************************************************************************/ + +#ifndef __SVIP_MUX_H +#define __SVIP_MUX_H + +#define LTQ_MUX_P0_PINS 20 +#define LTQ_MUX_P1_PINS 20 +#define LTQ_MUX_P2_PINS 19 +#define LTQ_MUX_P3_PINS 20 +#define LTQ_MUX_P4_PINS 24 + +struct ltq_mux_pin { + int dirin; + int puen; + int altsel0; + int altsel1; +}; + +struct ltq_mux_settings { + const struct ltq_mux_pin *mux_p0; + const struct ltq_mux_pin *mux_p1; + const struct ltq_mux_pin *mux_p2; + const struct ltq_mux_pin *mux_p3; + const struct ltq_mux_pin *mux_p4; +}; + +#define LTQ_MUX_P0_19_EXINT16 { 1, 0, 1, 0 } +#define LTQ_MUX_P0_19 { 0, 0, 1, 0 } + +#define LTQ_MUX_P0_18_EJ_BRKIN { 1, 0, 0, 0 } +#define LTQ_MUX_P0_18 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_18_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P0_17_EXINT10 { 1, 0, 0, 0 } +#define LTQ_MUX_P0_17 { 0, 0, 0, 0 } +#define LTQ_MUX_P0_17_ASC1_RXD { 1, 0, 1, 0 } + +#define LTQ_MUX_P0_16_EXINT9 { 1, 0, 0, 0 } +#define LTQ_MUX_P0_16 { 0, 0, 0, 0 } +#define LTQ_MUX_P0_16_ASC1_TXD { 0, 0, 1, 0 } + +#define LTQ_MUX_P0_15_EXINT8 { 1, 0, 0, 0 } +#define LTQ_MUX_P0_15 { 0, 0, 0, 0 } +#define LTQ_MUX_P0_15_ASC0_RXD { 1, 0, 1, 0 } + +#define LTQ_MUX_P0_14_EXINT7 { 1, 0, 0, 0 } +#define LTQ_MUX_P0_14 { 0, 0, 0, 0 } +#define LTQ_MUX_P0_14_ASC0_TXD { 1, 0, 1, 0 } + +#define LTQ_MUX_P0_13_SSC0_CS7 { 0, 1, 0, 0 } +#define LTQ_MUX_P0_13_EXINT6 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_13 { 1, 0, 1, 0 } +#define LTQ_MUX_P0_13_SSC1_CS7 { 0, 0, 0, 1 } +#define LTQ_MUX_P0_13_SSC1_INT { 0, 0, 1, 1 } + +#define LTQ_MUX_P0_12_SSC0_CS6 { 0, 1, 0, 0 } +#define LTQ_MUX_P0_12_EXINT5 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_12 { 1, 0, 1, 0 } +#define LTQ_MUX_P0_12_SSC1_CS6 { 0, 0, 0, 1 } + +#define LTQ_MUX_P0_11_SSC0_CS5 { 0, 1, 0, 0 } +#define LTQ_MUX_P0_11_EXINT4 { 1, 0, 1, 0 } +#define LTQ_MUX_P0_11 { 1, 0, 0, 0 } +#define LTQ_MUX_P0_11_SSC1_CS5 { 0, 0, 0, 1 } + +#define LTQ_MUX_P0_10_SSC0_CS4 { 0, 1, 0, 0 } +#define LTQ_MUX_P0_10_EXINT3 { 1, 0, 1, 0 } +#define LTQ_MUX_P0_10 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_10_SSC1_CS4 { 0, 0, 0, 1 } + +#define LTQ_MUX_P0_9_SSC0_CS3 { 0, 1, 0, 0 } +#define LTQ_MUX_P0_9_EXINT2 { 1, 0, 1, 0 } +#define LTQ_MUX_P0_9 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_9_SSC1_CS3 { 0, 0, 0, 1 } + +#define LTQ_MUX_P0_8_SSC0_CS2 { 0, 1, 0, 0 } +#define LTQ_MUX_P0_8_EXINT1 { 1, 0, 1, 0 } +#define LTQ_MUX_P0_8 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_8_SSC1_CS2 { 0, 0, 0, 1 } + +#define LTQ_MUX_P0_7_SSC0_CS1 { 0, 1, 0, 0 } +#define LTQ_MUX_P0_7_EXINT0 { 1, 0, 1, 0 } +#define LTQ_MUX_P0_7 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_7_SSC1_CS1 { 0, 0, 0, 1 } +#define LTQ_MUX_P0_7_SSC1_CS0 { 1, 0, 0, 1 } +#define LTQ_MUX_P0_7_SSC2_CS0 { 1, 0, 1, 1 } + +#define LTQ_MUX_P0_6_SSC0_CS0 { 0, 1, 0, 0 } +#define LTQ_MUX_P0_6 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_6_IN { 1, 0, 1, 0 } +#define LTQ_MUX_P0_6_SSC1_CS0 { 0, 0, 0, 1 } + +#define LTQ_MUX_P0_5_SSC1_SCLK { 0, 0, 0, 0 } +#define LTQ_MUX_P0_5 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_5_IN { 1, 0, 1, 0 } +#define LTQ_MUX_P0_5_SSC2_CLK { 1, 0, 0, 1 } + +#define LTQ_MUX_P0_4_SSC1_MRST { 1, 0, 0, 0 } +#define LTQ_MUX_P0_4 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_4_IN { 1, 0, 1, 0 } +#define LTQ_MUX_P0_4_SSC2_MRST { 0, 0, 0, 1 } + +#define LTQ_MUX_P0_3_SSC1_MTSR { 0, 0, 0, 0 } +#define LTQ_MUX_P0_3 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_3_IN { 1, 0, 1, 0 } +#define LTQ_MUX_P0_3_SSC2_MTSR { 0, 0, 0, 1 } + +#define LTQ_MUX_P0_2_SSC0_SCLK { 0, 0, 0, 0 } +#define LTQ_MUX_P0_2 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_2_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P0_1_SSC0_MRST { 1, 0, 0, 0 } +#define LTQ_MUX_P0_1 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_1_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P0_0_SSC0_MTSR { 0, 0, 0, 0 } +#define LTQ_MUX_P0_0 { 0, 0, 1, 0 } +#define LTQ_MUX_P0_0_IN { 1, 0, 1, 0 } + + +#define LTQ_MUX_P1_19_PCM3_TC1 { 0, 0, 0, 0 } +#define LTQ_MUX_P1_19_EXINT15 { 1, 0, 1, 0 } +#define LTQ_MUX_P1_19 { 0, 0, 1, 0 } + +#define LTQ_MUX_P1_18_PCM3_FSC { 0, 0, 0, 0 } +#define LTQ_MUX_P1_18_EXINT11 { 1, 0, 1, 0 } +#define LTQ_MUX_P1_18 { 0, 0, 1, 0 } + +#define LTQ_MUX_P1_17_PCM3_PCL { 0, 0, 0, 0 } +#define LTQ_MUX_P1_17_EXINT12 { 1, 0, 1, 0 } +#define LTQ_MUX_P1_17 { 0, 0, 1, 0 } + +#define LTQ_MUX_P1_16_PCM3_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P1_16_EXINT13 { 1, 0, 1, 0 } +#define LTQ_MUX_P1_16 { 0, 0, 1, 0 } + +#define LTQ_MUX_P1_15_PCM3_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P1_15_EXINT14 { 1, 0, 1, 0 } +#define LTQ_MUX_P1_15 { 0, 0, 1, 0 } + +#define LTQ_MUX_P1_14_PCM2_TC1 { 0, 0, 0, 0 } +#define LTQ_MUX_P1_14 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_14_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_13_PCM2_FSC { 0, 0, 0, 0 } +#define LTQ_MUX_P1_13 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_13_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_12_PCM2_PCL { 0, 0, 0, 0 } +#define LTQ_MUX_P1_12 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_12_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_11_PCM2_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P1_11 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_11_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_10_PCM2_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P1_10 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_10_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_9_PCM1_TC1 { 0, 0, 0, 0 } +#define LTQ_MUX_P1_9 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_9_IN { 0, 0, 1, 0 } + +#define LTQ_MUX_P1_8_PCM1_FSC { 0, 0, 0, 0 } +#define LTQ_MUX_P1_8 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_8_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_7_PCM1_PCL { 0, 0, 0, 0 } +#define LTQ_MUX_P1_7 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_7_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_6_PCM1_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P1_6 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_6_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_5_PCM1_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P1_5 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_5_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_4_PCM0_TC1 { 0, 0, 0, 0 } +#define LTQ_MUX_P1_4 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_4_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_3_PCM0_FSC { 0, 0, 0, 0 } +#define LTQ_MUX_P1_3 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_3_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_2_PCM0_PCL { 0, 0, 0, 0 } +#define LTQ_MUX_P1_2 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_2_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_1_PCM0_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P1_1 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_1_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P1_0_PCM0_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P1_0 { 0, 0, 1, 0 } +#define LTQ_MUX_P1_0_IN { 1, 0, 1, 0 } + + +#define LTQ_MUX_P2_18_EBU_BC1 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_18 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_18_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_17_EBU_BC0 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_17 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_17_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_16_EBU_RDBY { 1, 0, 0, 0 } +#define LTQ_MUX_P2_16 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_16_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_15_EBU_WAIT { 1, 0, 0, 0 } +#define LTQ_MUX_P2_15 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_15_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_14_EBU_ALE { 0, 0, 0, 0 } +#define LTQ_MUX_P2_14 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_14_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_13_EBU_WR { 0, 0, 0, 0 } +#define LTQ_MUX_P2_13 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_13_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_12_EBU_RD { 0, 0, 0, 0 } +#define LTQ_MUX_P2_12 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_12_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_11_EBU_A11 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_11 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_11_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_10_EBU_A10 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_10 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_10_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_9_EBU_A9 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_9 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_9_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_8_EBU_A8 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_8 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_8_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_7_EBU_A7 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_7 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_7_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_6_EBU_A6 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_6 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_6_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_5_EBU_A5 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_5 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_5_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_4_EBU_A4 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_4 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_4_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_3_EBU_A3 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_3 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_3_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_2_EBU_A2 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_2 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_2_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_1_EBU_A1 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_1 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_1_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P2_0_EBU_A0 { 0, 0, 0, 0 } +#define LTQ_MUX_P2_0 { 0, 0, 1, 0 } +#define LTQ_MUX_P2_0_IN { 1, 0, 1, 0 } + + +#define LTQ_MUX_P3_19_EBU_CS3 { 0, 0, 0, 0 } +#define LTQ_MUX_P3_19 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_19_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_18_EBU_CS2 { 0, 0, 0, 0 } +#define LTQ_MUX_P3_18 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_18_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_17_EBU_CS1 { 0, 0, 0, 0 } +#define LTQ_MUX_P3_17 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_17_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_16_EBU_CS0 { 0, 0, 0, 0 } +#define LTQ_MUX_P3_16 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_16_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_15_EBU_AD15 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_15 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_15_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_14_EBU_AD14 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_14 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_14_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_13_EBU_AD13 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_13 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_13_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_12_EBU_AD12 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_12 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_12_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_11_EBU_AD11 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_11 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_11_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_10_EBU_AD10 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_10 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_10_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_9_EBU_AD9 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_9 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_9_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_8_EBU_AD8 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_8 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_8_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_7_EBU_AD7 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_7 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_7_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_6_EBU_AD6 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_6 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_6_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_5_EBU_AD5 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_5 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_5_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_4_EBU_AD4 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_4 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_4_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_3_EBU_AD3 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_3 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_3_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_2_EBU_AD2 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_2 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_2_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_1_EBU_AD1 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_1 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_1_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P3_0_EBU_AD0 { 1, 0, 0, 0 } +#define LTQ_MUX_P3_0 { 0, 0, 1, 0 } +#define LTQ_MUX_P3_0_IN { 1, 0, 1, 0 } + + +#define LTQ_MUX_P4_23_SSLIC7_CLK { 0, 0, 0, 0 } +#define LTQ_MUX_P4_23 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_23_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_22_SSLIC7_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_22 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_22_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_21_SSLIC7_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_21 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_21_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_20_SSLIC6_CLK { 0, 0, 0, 0 } +#define LTQ_MUX_P4_20 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_20_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_19_SSLIC6_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_19 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_19_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_18_SSLIC6_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_18 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_18_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_17_SSLIC5_CLK { 0, 0, 0, 0 } +#define LTQ_MUX_P4_17 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_17_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_16_SSLIC5_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_16 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_16_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_15_SSLIC5_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_15 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_15_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_14_SSLIC4_CLK { 0, 0, 0, 0 } +#define LTQ_MUX_P4_14 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_14_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_13_SSLIC4_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_13 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_13_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_12_SSLIC4_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_12 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_12_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_11_SSLIC3_CLK { 0, 0, 0, 0 } +#define LTQ_MUX_P4_11 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_11_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_10_SSLIC3_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_10 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_10_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_9_SSLIC3_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_9 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_9_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_8_SSLIC2_CLK { 0, 0, 0, 0 } +#define LTQ_MUX_P4_8 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_8_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_7_SSLIC2_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_7 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_7_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_6_SSLIC2_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_6 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_6_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_5_SSLIC1_CLK { 0, 0, 0, 0 } +#define LTQ_MUX_P4_5 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_5_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_4_SSLIC1_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_4 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_4_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_3_SSLIC1_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_3 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_3_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_2_SSLIC0_CLK { 0, 0, 0, 0 } +#define LTQ_MUX_P4_2 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_2_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_1_SSLIC0_RX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_1 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_1_IN { 1, 0, 1, 0 } + +#define LTQ_MUX_P4_0_SSLIC0_TX { 0, 0, 0, 0 } +#define LTQ_MUX_P4_0 { 0, 0, 1, 0 } +#define LTQ_MUX_P4_0_IN { 1, 0, 1, 0 } + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_pms.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_pms.h new file mode 100644 index 0000000000..7329711858 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/svip_pms.h @@ -0,0 +1,23 @@ +/************************************************************************ + * + * Copyright (c) 2007 + * Infineon Technologies AG + * St. Martin Strasse 53; 81669 Muenchen; Germany + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + ************************************************************************/ + +#ifndef __SVIP_PMS_H +#define __SVIP_PMS_H + +void svip_sys1_clk_enable(u32 mask); +int svip_sys1_clk_is_enabled(u32 mask); + +void svip_sys2_clk_enable(u32 mask); +int svip_sys2_clk_is_enabled(u32 mask); + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys0_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys0_reg.h new file mode 100644 index 0000000000..7428cccc87 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys0_reg.h @@ -0,0 +1,165 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __SYS0_REG_H +#define __SYS0_REG_H + +#define sys0_r32(reg) ltq_r32(&sys0->reg) +#define sys0_w32(val, reg) ltq_w32(val, &sys0->reg) +#define sys0_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys0->reg) + +/** SYS0 register structure */ +struct svip_reg_sys0 { + unsigned long sr; /* 0x0000 */ + unsigned long bcr; /* 0x0004 */ + unsigned long pll1cr; /* 0x0008 */ + unsigned long pll2cr; /* 0x000c */ + unsigned long tscr; /* 0x0010 */ + unsigned long phyclkr; /* 0x0014 */ +}; + +/******************************************************************************* + * SYS0 Status Register + ******************************************************************************/ + +/* Endian select pin (31) */ +#define SYS0_SR_ESEL (0x1 << 31) +#define SYS0_SR_ESEL_GET(val) ((((val) & SYS0_SR_ESEL) >> 31) & 0x1) +/* Boot mode pins (27:24) */ +#define SYS0_SR_BMODE (0xf << 24) +#define SYS0_SR_BMODE_GET(val) ((((val) & SYS0_SR_BMODE) >> 24) & 0xf) +/* PLL2 Lock (18) */ +#define SYS0_SR_PLL2LOCK (0x1 << 18) +#define SYS0_SR_PLL2LOCK_GET(val) ((((val) & SYS0_SR_PLL2LOCK) >> 18) & 0x1) +/* PLL1 Lock (17) */ +#define SYS0_SR_PLL1LOCK (0x1 << 17) +#define SYS0_SR_PLL1LOCK_GET(val) ((((val) & SYS0_SR_PLL1LOCK) >> 17) & 0x1) +/* Discrete Timing Oscillator Lock (16) */ +#define SYS0_SR_DTOLOCK (0x1 << 16) +#define SYS0_SR_DTOLOCK_GET(val) ((((val) & SYS0_SR_DTOLOCK) >> 16) & 0x1) +/* Hardware Reset Indication (1) */ +#define SYS0_SR_HRSTIN (0x1 << 1) +#define SYS0_SR_HRSTIN_VAL(val) (((val) & 0x1) << 1) +#define SYS0_SR_HRSTIN_GET(val) ((((val) & SYS0_SR_HRSTIN) >> 1) & 0x1) +#define SYS0_SR_HRSTIN_SET(reg,val) (reg) = ((reg & ~SYS0_SR_HRSTIN) | (((val) & 0x1) << 1)) +/* Power-on Reset Indication (0) */ +#define SYS0_SR_POR (0x1 << 0) +#define SYS0_SR_POR_VAL(val) (((val) & 0x1) << 0) +#define SYS0_SR_POR_GET(val) ((((val) & SYS0_SR_POR) >> 0) & 0x1) +#define SYS0_SR_POR_SET(reg,val) (reg) = ((reg & ~SYS0_SR_POR) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * SYS0 Boot Control Register + ******************************************************************************/ + +/* Configuration of Boot Source for CPU5 (25) */ +#define SYS0_BCR_BMODECPU5 (0x1 << 25) +#define SYS0_BCR_BMODECPU5_VAL(val) (((val) & 0x1) << 25) +#define SYS0_BCR_BMODECPU5_GET(val) ((((val) & SYS0_BCR_BMODECPU5) >> 25) & 0x1) +#define SYS0_BCR_BMODECPU5_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU5) | (((val) & 0x1) << 25)) +/* Configuration of Boot Source for CPU4 (24) */ +#define SYS0_BCR_BMODECPU4 (0x1 << 24) +#define SYS0_BCR_BMODECPU4_VAL(val) (((val) & 0x1) << 24) +#define SYS0_BCR_BMODECPU4_GET(val) ((((val) & SYS0_BCR_BMODECPU4) >> 24) & 0x1) +#define SYS0_BCR_BMODECPU4_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU4) | (((val) & 0x1) << 24)) +/* Configuration of Boot Source for CPU3 (23) */ +#define SYS0_BCR_BMODECPU3 (0x1 << 23) +#define SYS0_BCR_BMODECPU3_VAL(val) (((val) & 0x1) << 23) +#define SYS0_BCR_BMODECPU3_GET(val) ((((val) & SYS0_BCR_BMODECPU3) >> 23) & 0x1) +#define SYS0_BCR_BMODECPU3_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU3) | (((val) & 0x1) << 23)) +/* Configuration of Boot Source for CPU2 (22) */ +#define SYS0_BCR_BMODECPU2 (0x1 << 22) +#define SYS0_BCR_BMODECPU2_VAL(val) (((val) & 0x1) << 22) +#define SYS0_BCR_BMODECPU2_GET(val) ((((val) & SYS0_BCR_BMODECPU2) >> 22) & 0x1) +#define SYS0_BCR_BMODECPU2_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU2) | (((val) & 0x1) << 22)) +/* Configuration of Boot Source for CPU1 (21) */ +#define SYS0_BCR_BMODECPU1 (0x1 << 21) +#define SYS0_BCR_BMODECPU1_VAL(val) (((val) & 0x1) << 21) +#define SYS0_BCR_BMODECPU1_GET(val) ((((val) & SYS0_BCR_BMODECPU1) >> 21) & 0x1) +#define SYS0_BCR_BMODECPU1_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU1) | (((val) & 0x1) << 21)) +/* Configuration of Boot Source for CPU0 (20:16) */ +#define SYS0_BCR_BMODECPU0 (0x1f << 16) +#define SYS0_BCR_BMODECPU0_VAL(val) (((val) & 0x1f) << 16) +#define SYS0_BCR_BMODECPU0_GET(val) ((((val) & SYS0_BCR_BMODECPU0) >> 16) & 0x1f) +#define SYS0_BCR_BMODECPU0_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU0) | (((val) & 0x1f) << 16)) +/* Configuration of Endianess for CPU5 (5) */ +#define SYS0_BCR_ESELCPU5 (0x1 << 5) +#define SYS0_BCR_ESELCPU5_VAL(val) (((val) & 0x1) << 5) +#define SYS0_BCR_ESELCPU5_GET(val) ((((val) & SYS0_BCR_ESELCPU5) >> 5) & 0x1) +#define SYS0_BCR_ESELCPU5_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU5) | (((val) & 0x1) << 5)) +/* Configuration of Endianess for CPU4 (4) */ +#define SYS0_BCR_ESELCPU4 (0x1 << 4) +#define SYS0_BCR_ESELCPU4_VAL(val) (((val) & 0x1) << 4) +#define SYS0_BCR_ESELCPU4_GET(val) ((((val) & SYS0_BCR_ESELCPU4) >> 4) & 0x1) +#define SYS0_BCR_ESELCPU4_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU4) | (((val) & 0x1) << 4)) +/* Configuration of Endianess for CPU3 (3) */ +#define SYS0_BCR_ESELCPU3 (0x1 << 3) +#define SYS0_BCR_ESELCPU3_VAL(val) (((val) & 0x1) << 3) +#define SYS0_BCR_ESELCPU3_GET(val) ((((val) & SYS0_BCR_ESELCPU3) >> 3) & 0x1) +#define SYS0_BCR_ESELCPU3_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU3) | (((val) & 0x1) << 3)) +/* Configuration of Endianess for CPU2 (2) */ +#define SYS0_BCR_ESELCPU2 (0x1 << 2) +#define SYS0_BCR_ESELCPU2_VAL(val) (((val) & 0x1) << 2) +#define SYS0_BCR_ESELCPU2_GET(val) ((((val) & SYS0_BCR_ESELCPU2) >> 2) & 0x1) +#define SYS0_BCR_ESELCPU2_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU2) | (((val) & 0x1) << 2)) +/* Configuration of Endianess for CPU1 (1) */ +#define SYS0_BCR_ESELCPU1 (0x1 << 1) +#define SYS0_BCR_ESELCPU1_VAL(val) (((val) & 0x1) << 1) +#define SYS0_BCR_ESELCPU1_GET(val) ((((val) & SYS0_BCR_ESELCPU1) >> 1) & 0x1) +#define SYS0_BCR_ESELCPU1_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU1) | (((val) & 0x1) << 1)) +/* Configuration of Endianess for CPU0 (0) */ +#define SYS0_BCR_ESELCPU0 (0x1) +#define SYS0_BCR_ESELCPU0_VAL(val) (((val) & 0x1) << 0) +#define SYS0_BCR_ESELCPU0_GET(val) ((((val) & SYS0_BCR_ESELCPU0) >> 0) & 0x1) +#define SYS0_BCR_ESELCPU0_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU0) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * PLL1 Control Register + ******************************************************************************/ + +/* PLL1 Bypass Enable (31) */ +#define SYS0_PLL1CR_OSCBYP (0x1 << 31) +#define SYS0_PLL1CR_OSCBYP_VAL(val) (((val) & 0x1) << 31) +#define SYS0_PLL1CR_OSCBYP_GET(val) ((((val) & SYS0_PLL1CR_OSCBYP) >> 31) & 0x1) +#define SYS0_PLL1CR_OSCBYP_SET(reg,val) (reg) = ((reg & ~SYS0_PLL1CR_OSCBYP) | (((val) & 0x1) << 31)) +/* PLL1 Divider Value (1:0) */ +#define SYS0_PLL1CR_PLLDIV (0x3) +#define SYS0_PLL1CR_PLLDIV_VAL(val) (((val) & 0x3) << 0) +#define SYS0_PLL1CR_PLLDIV_GET(val) ((((val) & SYS0_PLL1CR_PLLDIV) >> 0) & 0x3) +#define SYS0_PLL1CR_PLLDIV_SET(reg,val) (reg) = ((reg & ~SYS0_PLL1CR_PLLDIV) | (((val) & 0x3) << 0)) + +/******************************************************************************* + * PLL2 Control Register + ******************************************************************************/ + +/* PLL2 clear deepsleep (31) */ +#define SYS0_PLL2CR_CLRDS (0x1 << 31) +#define SYS0_PLL2CR_CLRDS_VAL(val) (((val) & 0x1) << 31) +#define SYS0_PLL2CR_CLRDS_GET(val) ((((val) & SYS0_PLL2CR_CLRDS) >> 31) & 0x1) +#define SYS0_PLL2CR_CLRDS_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_CLRDS) | (((val) & 0x1) << 31)) +/* PLL2 set deepsleep (30) */ +#define SYS0_PLL2CR_SETDS (0x1 << 30) +#define SYS0_PLL2CR_SETDS_VAL(val) (((val) & 0x1) << 30) +#define SYS0_PLL2CR_SETDS_GET(val) ((((val) & SYS0_PLL2CR_SETDS) >> 30) & 0x1) +#define SYS0_PLL2CR_SETDS_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_SETDS) | (((val) & 0x1) << 30)) +/* PLL2 Fractional division enable (16) */ +#define SYS0_PLL2CR_FRACTEN (0x1 << 16) +#define SYS0_PLL2CR_FRACTEN_VAL(val) (((val) & 0x1) << 16) +#define SYS0_PLL2CR_FRACTEN_GET(val) ((((val) & SYS0_PLL2CR_FRACTEN) >> 16) & 0x1) +#define SYS0_PLL2CR_FRACTEN_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_FRACTEN) | (((val) & 0x1) << 16)) +/* PLL2 Fractional division value (9:0) */ +#define SYS0_FRACTVAL (0x3f) +#define SYS0_FRACTVAL_VAL(val) (((val) & 0x3f) << 0) +#define SYS0_FRACTVAL_GET(val) ((((val) & SYS0_FRACTVAL) >> 0) & 0x3f) +#define SYS0_FRACTVAL_SET(reg,val) (reg) = ((reg & ~SYS0_FRACTVAL) | (((val) & 0x3f) << 0)) + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys1_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys1_reg.h new file mode 100644 index 0000000000..e0c2e84b1a --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys1_reg.h @@ -0,0 +1,370 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __SYS1_REG_H +#define __SYS1_REG_H + +#define sys1_r32(reg) ltq_r32(&sys1->reg) +#define sys1_w32(val, reg) ltq_w32(val, &sys1->reg) +#define sys1_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys1->reg) + +/** SYS1 register structure */ +struct svip_reg_sys1 { + unsigned long clksr; /* 0x0000 */ + unsigned long clkenr; /* 0x0004 */ + unsigned long clkclr; /* 0x0008 */ + unsigned long reserved0[1]; + unsigned long l2ccr; /* 0x0010 */ + unsigned long fpicr; /* 0x0014 */ + unsigned long wdtcr; /* 0x0018 */ + unsigned long reserved1[1]; + unsigned long cpucr[6]; /* 0x0020 */ + unsigned long reserved2[2]; + unsigned long rsr; /* 0x0040 */ + unsigned long rreqr; /* 0x0044 */ + unsigned long rrlsr; /* 0x0048 */ + unsigned long rbtr; /* 0x004c */ + unsigned long irncr; /* 0x0050 */ + unsigned long irnicr; /* 0x0054 */ + unsigned long irnen; /* 0x0058 */ + unsigned long reserved3[1]; + unsigned long cpursr[6]; /* 0x0060 */ + unsigned long reserved4[2]; + unsigned long cpusrssr[6]; /* 0x0080 */ + unsigned long reserved5[2]; + unsigned long cpuwrssr[6]; /* 0x00a0 */ +}; + +/******************************************************************************* + * SYS1 Clock Status Register + ******************************************************************************/ +/* (r) Clock Enable for L2C */ +#define SYS1_CLKSR_L2C (0x1 << 31) +/* (r) Clock Enable for DDR2 */ +#define SYS1_CLKSR_DDR2 (0x1 << 30) +/* (r) Clock Enable for SMI2 */ +#define SYS1_CLKSR_SMI2 (0x1 << 29) +/* (r) Clock Enable for SMI1 */ +#define SYS1_CLKSR_SMI1 (0x1 << 28) +/* (r) Clock Enable for SMI0 */ +#define SYS1_CLKSR_SMI0 (0x1 << 27) +/* (r) Clock Enable for FMI0 */ +#define SYS1_CLKSR_FMI0 (0x1 << 26) +/* (r) Clock Enable for PORT0 */ +#define SYS1_CLKSR_PORT0 (0x1 << 0) +/* (r) Clock Enable for PCM3 */ +#define SYS1_CLKSR_PCM3 (0x1 << 19) +/* (r) Clock Enable for PCM2 */ +#define SYS1_CLKSR_PCM2 (0x1 << 18) +/* (r) Clock Enable for PCM1 */ +#define SYS1_CLKSR_PCM1 (0x1 << 17) +/* (r) Clock Enable for PCM0 */ +#define SYS1_CLKSR_PCM0 (0x1 << 16) +/* (r) Clock Enable for ASC1 */ +#define SYS1_CLKSR_ASC1 (0x1 << 15) +/* (r) Clock Enable for ASC0 */ +#define SYS1_CLKSR_ASC0 (0x1 << 14) +/* (r) Clock Enable for SSC2 */ +#define SYS1_CLKSR_SSC2 (0x1 << 13) +/* (r) Clock Enable for SSC1 */ +#define SYS1_CLKSR_SSC1 (0x1 << 12) +/* (r) Clock Enable for SSC0 */ +#define SYS1_CLKSR_SSC0 (0x1 << 11) +/* (r) Clock Enable for GPTC */ +#define SYS1_CLKSR_GPTC (0x1 << 10) +/* (r) Clock Enable for DMA */ +#define SYS1_CLKSR_DMA (0x1 << 9) +/* (r) Clock Enable for FSCT */ +#define SYS1_CLKSR_FSCT (0x1 << 8) +/* (r) Clock Enable for ETHSW */ +#define SYS1_CLKSR_ETHSW (0x1 << 7) +/* (r) Clock Enable for EBU */ +#define SYS1_CLKSR_EBU (0x1 << 6) +/* (r) Clock Enable for TRNG */ +#define SYS1_CLKSR_TRNG (0x1 << 5) +/* (r) Clock Enable for DEU */ +#define SYS1_CLKSR_DEU (0x1 << 4) +/* (r) Clock Enable for PORT3 */ +#define SYS1_CLKSR_PORT3 (0x1 << 3) +/* (r) Clock Enable for PORT2 */ +#define SYS1_CLKSR_PORT2 (0x1 << 2) +/* (r) Clock Enable for PORT1 */ +#define SYS1_CLKSR_PORT1 (0x1 << 1) + +/******************************************************************************* + * SYS1 Clock Enable Register + ******************************************************************************/ +/* (w) Clock Enable Request for L2C */ +#define SYS1_CLKENR_L2C (0x1 << 31) +/* (w) Clock Enable Request for DDR2 */ +#define SYS1_CLKENR_DDR2 (0x1 << 30) +/* (w) Clock Enable Request for SMI2 */ +#define SYS1_CLKENR_SMI2 (0x1 << 29) +/* (w) Clock Enable Request for SMI1 */ +#define SYS1_CLKENR_SMI1 (0x1 << 28) +/* (w) Clock Enable Request for SMI0 */ +#define SYS1_CLKENR_SMI0 (0x1 << 27) +/* (w) Clock Enable Request for FMI0 */ +#define SYS1_CLKENR_FMI0 (0x1 << 26) +/* (w) Clock Enable Request for PORT0 */ +#define SYS1_CLKENR_PORT0 (0x1 << 0) +/* (w) Clock Enable Request for PCM3 */ +#define SYS1_CLKENR_PCM3 (0x1 << 19) +/* (w) Clock Enable Request for PCM2 */ +#define SYS1_CLKENR_PCM2 (0x1 << 18) +/* (w) Clock Enable Request for PCM1 */ +#define SYS1_CLKENR_PCM1 (0x1 << 17) +/* (w) Clock Enable Request for PCM0 */ +#define SYS1_CLKENR_PCM0 (0x1 << 16) +/* (w) Clock Enable Request for ASC1 */ +#define SYS1_CLKENR_ASC1 (0x1 << 15) +/* (w) Clock Enable Request for ASC0 */ +#define SYS1_CLKENR_ASC0 (0x1 << 14) +/* (w) Clock Enable Request for SSC2 */ +#define SYS1_CLKENR_SSC2 (0x1 << 13) +/* (w) Clock Enable Request for SSC1 */ +#define SYS1_CLKENR_SSC1 (0x1 << 12) +/* (w) Clock Enable Request for SSC0 */ +#define SYS1_CLKENR_SSC0 (0x1 << 11) +/* (w) Clock Enable Request for GPTC */ +#define SYS1_CLKENR_GPTC (0x1 << 10) +/* (w) Clock Enable Request for DMA */ +#define SYS1_CLKENR_DMA (0x1 << 9) +/* (w) Clock Enable Request for FSCT */ +#define SYS1_CLKENR_FSCT (0x1 << 8) +/* (w) Clock Enable Request for ETHSW */ +#define SYS1_CLKENR_ETHSW (0x1 << 7) +/* (w) Clock Enable Request for EBU */ +#define SYS1_CLKENR_EBU (0x1 << 6) +/* (w) Clock Enable Request for TRNG */ +#define SYS1_CLKENR_TRNG (0x1 << 5) +/* (w) Clock Enable Request for DEU */ +#define SYS1_CLKENR_DEU (0x1 << 4) +/* (w) Clock Enable Request for PORT3 */ +#define SYS1_CLKENR_PORT3 (0x1 << 3) +/* (w) Clock Enable Request for PORT2 */ +#define SYS1_CLKENR_PORT2 (0x1 << 2) +/* (w) Clock Enable Request for PORT1 */ +#define SYS1_CLKENR_PORT1 (0x1 << 1) + +/******************************************************************************* + * SYS1 Clock Clear Register + ******************************************************************************/ +/* (w) Clock Disable Request for L2C */ +#define SYS1_CLKCLR_L2C (0x1 << 31) +/* (w) Clock Disable Request for DDR2 */ +#define SYS1_CLKCLR_DDR2 (0x1 << 30) +/* (w) Clock Disable Request for SMI2 */ +#define SYS1_CLKCLR_SMI2 (0x1 << 29) +/* (w) Clock Disable Request for SMI1 */ +#define SYS1_CLKCLR_SMI1 (0x1 << 28) +/* (w) Clock Disable Request for SMI0 */ +#define SYS1_CLKCLR_SMI0 (0x1 << 27) +/* (w) Clock Disable Request for FMI0 */ +#define SYS1_CLKCLR_FMI0 (0x1 << 26) +/* (w) Clock Disable Request for PORT0 */ +#define SYS1_CLKCLR_PORT0 (0x1 << 0) +/* (w) Clock Disable Request for PCM3 */ +#define SYS1_CLKCLR_PCM3 (0x1 << 19) +/* (w) Clock Disable Request for PCM2 */ +#define SYS1_CLKCLR_PCM2 (0x1 << 18) +/* (w) Clock Disable Request for PCM1 */ +#define SYS1_CLKCLR_PCM1 (0x1 << 17) +/* (w) Clock Disable Request for PCM0 */ +#define SYS1_CLKCLR_PCM0 (0x1 << 16) +/* (w) Clock Disable Request for ASC1 */ +#define SYS1_CLKCLR_ASC1 (0x1 << 15) +/* (w) Clock Disable Request for ASC0 */ +#define SYS1_CLKCLR_ASC0 (0x1 << 14) +/* (w) Clock Disable Request for SSC2 */ +#define SYS1_CLKCLR_SSC2 (0x1 << 13) +/* (w) Clock Disable Request for SSC1 */ +#define SYS1_CLKCLR_SSC1 (0x1 << 12) +/* (w) Clock Disable Request for SSC0 */ +#define SYS1_CLKCLR_SSC0 (0x1 << 11) +/* (w) Clock Disable Request for GPTC */ +#define SYS1_CLKCLR_GPTC (0x1 << 10) +/* (w) Clock Disable Request for DMA */ +#define SYS1_CLKCLR_DMA (0x1 << 9) +/* (w) Clock Disable Request for FSCT */ +#define SYS1_CLKCLR_FSCT (0x1 << 8) +/* (w) Clock Disable Request for ETHSW */ +#define SYS1_CLKCLR_ETHSW (0x1 << 7) +/* (w) Clock Disable Request for EBU */ +#define SYS1_CLKCLR_EBU (0x1 << 6) +/* (w) Clock Disable Request for TRNG */ +#define SYS1_CLKCLR_TRNG (0x1 << 5) +/* (w) Clock Disable Request for DEU */ +#define SYS1_CLKCLR_DEU (0x1 << 4) +/* (w) Clock Disable Request for PORT3 */ +#define SYS1_CLKCLR_PORT3 (0x1 << 3) +/* (w) Clock Disable Request for PORT2 */ +#define SYS1_CLKCLR_PORT2 (0x1 << 2) +/* (w) Clock Disable Request for PORT1 */ +#define SYS1_CLKCLR_PORT1 (0x1 << 1) + +/******************************************************************************* + * SYS1 FPI Control Register + ******************************************************************************/ + +/* FPI Bus Clock divider (0) */ +#define SYS1_FPICR_FPIDIV (0x1) +#define SYS1_FPICR_FPIDIV_VAL(val) (((val) & 0x1) << 0) +#define SYS1_FPICR_FPIDIV_GET(val) ((((val) & SYS1_FPICR_FPIDIV) >> 0) & 0x1) +#define SYS1_FPICR_FPIDIV_SET(reg,val) (reg) = ((reg & ~SYS1_FPICR_FPIDIV) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * SYS1 Clock Control Register for CPUn + ******************************************************************************/ + +/* Enable bit for clock of CPUn (1) */ +#define SYS1_CPUCR_CPUCLKEN (0x1 << 1) +#define SYS1_CPUCR_CPUCLKEN_VAL(val) (((val) & 0x1) << 1) +#define SYS1_CPUCR_CPUCLKEN_GET(val) ((((val) & SYS1_CPUCR_CPUCLKEN) >> 1) & 0x1) +#define SYS1_CPUCR_CPUCLKEN_SET(reg,val) (reg) = ((reg & ~SYS1_CPUCR_CPUCLKEN) | (((val) & 0x1) << 1)) +/* Divider factor for clock of CPUn (0) */ +#define SYS1_CPUCR_CPUDIV (0x1) +#define SYS1_CPUCR_CPUDIV_VAL(val) (((val) & 0x1) << 0) +#define SYS1_CPUCR_CPUDIV_GET(val) ((((val) & SYS1_CPUCR_CPUDIV) >> 0) & 0x1) +#define SYS1_CPUCR_CPUDIV_SET(reg,val) (reg) = ((reg & ~SYS1_CPUCR_CPUDIV) | (((val) & 0x1) << 0)) + +/******************************************************************************* + * SYS1 Reset Request Register + ******************************************************************************/ + +/* HRSTOUT Reset Request (18) */ +#define SYS1_RREQ_HRSTOUT (0x1 << 18) +#define SYS1_RREQ_HRSTOUT_VAL(val) (((val) & 0x1) << 18) +#define SYS1_RREQ_HRSTOUT_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_HRSTOUT) | (((val) & 1) << 18)) + /* FBS0 Reset Request (17) */ +#define SYS1_RREQ_FBS0 (0x1 << 17) +#define SYS1_RREQ_FBS0_VAL(val) (((val) & 0x1) << 17) +#define SYS1_RREQ_FBS0_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_FBS0) | (((val) & 1) << 17)) + /* SUBSYS Reset Request (16) */ +#define SYS1_RREQ_SUBSYS (0x1 << 16) +#define SYS1_RREQ_SUBSYS_VAL(val) (((val) & 0x1) << 16) +#define SYS1_RREQ_SUBSYS_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_SUBSYS) | (((val) & 1) << 16)) + /* Watchdog5 Reset Request (13) */ +#define SYS1_RREQ_WDT5 (0x1 << 13) +#define SYS1_RREQ_WDT5_VAL(val) (((val) & 0x1) << 13) +#define SYS1_RREQ_WDT5_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT5) | (((val) & 1) << 13)) + /* Watchdog4 Reset Request (12) */ +#define SYS1_RREQ_WDT4 (0x1 << 12) +#define SYS1_RREQ_WDT4_VAL(val) (((val) & 0x1) << 12) +#define SYS1_RREQ_WDT4_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT4) | (((val) & 1) << 12)) + /* Watchdog3 Reset Request (11) */ +#define SYS1_RREQ_WDT3 (0x1 << 11) +#define SYS1_RREQ_WDT3_VAL(val) (((val) & 0x1) << 11) +#define SYS1_RREQ_WDT3_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT3) | (((val) & 1) << 11)) + /* Watchdog2 Reset Request (10) */ +#define SYS1_RREQ_WDT2 (0x1 << 10) +#define SYS1_RREQ_WDT2_VAL(val) (((val) & 0x1) << 10) +#define SYS1_RREQ_WDT2_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT2) | (((val) & 1) << 10)) + /* Watchdog1 Reset Request (9) */ +#define SYS1_RREQ_WDT1 (0x1 << 9) +#define SYS1_RREQ_WDT1_VAL(val) (((val) & 0x1) << 9) +#define SYS1_RREQ_WDT1_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT1) | (((val) & 1) << 9)) + /* Watchdog0 Reset Request (8) */ +#define SYS1_RREQ_WDT0 (0x1 << 8) +#define SYS1_RREQ_WDT0_VAL(val) (((val) & 0x1) << 8) +#define SYS1_RREQ_WDT0_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT0) | (((val) & 1) << 8)) + /* CPU5 Reset Request (5) */ +#define SYS1_RREQ_CPU5 (0x1 << 5) +#define SYS1_RREQ_CPU5_VAL(val) (((val) & 0x1) << 5) +#define SYS1_RREQ_CPU5_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU5) | (((val) & 1) << 5)) + /* CPU4 Reset Request (4) */ +#define SYS1_RREQ_CPU4 (0x1 << 4) +#define SYS1_RREQ_CPU4_VAL(val) (((val) & 0x1) << 4) +#define SYS1_RREQ_CPU4_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU4) | (((val) & 1) << 4)) + /* CPU3 Reset Request (3) */ +#define SYS1_RREQ_CPU3 (0x1 << 3) +#define SYS1_RREQ_CPU3_VAL(val) (((val) & 0x1) << 3) +#define SYS1_RREQ_CPU3_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU3) | (((val) & 1) << 3)) + /* CPU2 Reset Request (2) */ +#define SYS1_RREQ_CPU2 (0x1 << 2) +#define SYS1_RREQ_CPU2_VAL(val) (((val) & 0x1) << 2) +#define SYS1_RREQ_CPU2_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU2) | (((val) & 1) << 2)) + /* CPU1 Reset Request (1) */ +#define SYS1_RREQ_CPU1 (0x1 << 1) +#define SYS1_RREQ_CPU1_VAL(val) (((val) & 0x1) << 1) +#define SYS1_RREQ_CPU1_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU1) | (((val) & 1) << 1)) +/* CPU0 Reset Request (0) */ +#define SYS1_RREQ_CPU0 (0x1) +#define SYS1_RREQ_CPU0_VAL(val) (((val) & 0x1) << 0) +#define SYS1_RREQ_CPU0_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU0) | (((val) & 1) << 0)) + +/******************************************************************************* + * SYS1 Reset Release Register + ******************************************************************************/ + +/* HRSTOUT Reset Release (18) */ +#define SYS1_RRLSR_HRSTOUT (0x1 << 18) +#define SYS1_RRLSR_HRSTOUT_VAL(val) (((val) & 0x1) << 18) +#define SYS1_RRLSR_HRSTOUT_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_HRSTOUT) | (((val) & 1) << 18)) +/* FBS0 Reset Release (17) */ +#define SYS1_RRLSR_FBS0 (0x1 << 17) +#define SYS1_RRLSR_FBS0_VAL(val) (((val) & 0x1) << 17) +#define SYS1_RRLSR_FBS0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_FBS0) | (((val) & 1) << 17)) +/* SUBSYS Reset Release (16) */ +#define SYS1_RRLSR_SUBSYS (0x1 << 16) +#define SYS1_RRLSR_SUBSYS_VAL(val) (((val) & 0x1) << 16) +#define SYS1_RRLSR_SUBSYS_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_SUBSYS) | (((val) & 1) << 16)) +/* Watchdog5 Reset Release (13) */ +#define SYS1_RRLSR_WDT5 (0x1 << 13) +#define SYS1_RRLSR_WDT5_VAL(val) (((val) & 0x1) << 13) +#define SYS1_RRLSR_WDT5_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT5) | (((val) & 1) << 13)) +/* Watchdog4 Reset Release (12) */ +#define SYS1_RRLSR_WDT4 (0x1 << 12) +#define SYS1_RRLSR_WDT4_VAL(val) (((val) & 0x1) << 12) +#define SYS1_RRLSR_WDT4_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT4) | (((val) & 1) << 12)) +/* Watchdog3 Reset Release (11) */ +#define SYS1_RRLSR_WDT3 (0x1 << 11) +#define SYS1_RRLSR_WDT3_VAL(val) (((val) & 0x1) << 11) +#define SYS1_RRLSR_WDT3_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT3) | (((val) & 1) << 11)) +/* Watchdog2 Reset Release (10) */ +#define SYS1_RRLSR_WDT2 (0x1 << 10) +#define SYS1_RRLSR_WDT2_VAL(val) (((val) & 0x1) << 10) +#define SYS1_RRLSR_WDT2_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT2) | (((val) & 1) << 10)) +/* Watchdog1 Reset Release (9) */ +#define SYS1_RRLSR_WDT1 (0x1 << 9) +#define SYS1_RRLSR_WDT1_VAL(val) (((val) & 0x1) << 9) +#define SYS1_RRLSR_WDT1_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT1) | (((val) & 1) << 9)) +/* Watchdog0 Reset Release (8) */ +#define SYS1_RRLSR_WDT0 (0x1 << 8) +#define SYS1_RRLSR_WDT0_VAL(val) (((val) & 0x1) << 8) +#define SYS1_RRLSR_WDT0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT0) | (((val) & 1) << 8)) +/* CPU5 Reset Release (5) */ +#define SYS1_RRLSR_CPU5 (0x1 << 5) +#define SYS1_RRLSR_CPU5_VAL(val) (((val) & 0x1) << 5) +#define SYS1_RRLSR_CPU5_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU5) | (((val) & 1) << 5)) +/* CPU4 Reset Release (4) */ +#define SYS1_RRLSR_CPU4 (0x1 << 4) +#define SYS1_RRLSR_CPU4_VAL(val) (((val) & 0x1) << 4) +#define SYS1_RRLSR_CPU4_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU4) | (((val) & 1) << 4)) +/* CPU3 Reset Release (3) */ +#define SYS1_RRLSR_CPU3 (0x1 << 3) +#define SYS1_RRLSR_CPU3_VAL(val) (((val) & 0x1) << 3) +#define SYS1_RRLSR_CPU3_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU3) | (((val) & 1) << 3)) +/* CPU2 Reset Release (2) */ +#define SYS1_RRLSR_CPU2 (0x1 << 2) +#define SYS1_RRLSR_CPU2_VAL(val) (((val) & 0x1) << 2) +#define SYS1_RRLSR_CPU2_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU2) | (((val) & 1) << 2)) +/* CPU1 Reset Release (1) */ +#define SYS1_RRLSR_CPU1 (0x1 << 1) +#define SYS1_RRLSR_CPU1_VAL(val) (((val) & 0x1) << 1) +#define SYS1_RRLSR_CPU1_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU1) | (((val) & 1) << 1)) +/* CPU0 Reset Release (0) */ +#define SYS1_RRLSR_CPU0 (0x1) +#define SYS1_RRLSR_CPU0_VAL(val) (((val) & 0x1) << 0) +#define SYS1_RRLSR_CPU0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU0) | (((val) & 1) << 0)) + +#endif diff --git a/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys2_reg.h b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys2_reg.h new file mode 100644 index 0000000000..ff9f04b4d7 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/include/asm/mach-lantiq/svip/sys2_reg.h @@ -0,0 +1,494 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + St. Martin Strasse 53; 81669 Munich, Germany + + Any use of this Software is subject to the conclusion of a respective + License Agreement. Without such a License Agreement no rights to the + Software are granted. + + ******************************************************************************/ + +#ifndef __SYS2_REG_H +#define __SYS2_REG_H + +#define sys2_r32(reg) ltq_r32(&sys2->reg) +#define sys2_w32(val, reg) ltq_w32(val, &sys2->reg) +#define sys2_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys2->reg) + +/** SYS2 register structure */ +struct svip_reg_sys2 { + volatile unsigned long clksr; /* 0x0000 */ + volatile unsigned long clkenr; /* 0x0004 */ + volatile unsigned long clkclr; /* 0x0008 */ + volatile unsigned long reserved0[1]; + volatile unsigned long rsr; /* 0x0010 */ + volatile unsigned long rreqr; /* 0x0014 */ + volatile unsigned long rrlsr; /* 0x0018 */ +}; + +/******************************************************************************* + * SYS2 Clock Status Register + ******************************************************************************/ + +/* Clock Enable for PORT4 */ +#define SYS2_CLKSR_PORT4 (0x1 << 27) +#define SYS2_CLKSR_PORT4_VAL(val) (((val) & 0x1) << 27) +#define SYS2_CLKSR_PORT4_GET(val) (((val) & SYS2_CLKSR_PORT4) >> 27) +/* Clock Enable for HWSYNC */ +#define SYS2_CLKSR_HWSYNC (0x1 << 26) +#define SYS2_CLKSR_HWSYNC_VAL(val) (((val) & +#define SYS2_CLKSR_HWSYNC_GET(val) (((val) & SYS2_CLKSR_HWSYNC) >> 26) + /* Clock Enable for MBS */ +#define SYS2_CLKSR_MBS (0x1 << 25) +#define SYS2_CLKSR_MBS_VAL(val) (((val) & 0x1) << 25) +#define SYS2_CLKSR_MBS_GET(val) (((val) & SYS2_CLKSR_MBS) >> 25) + /* Clock Enable for SWINT */ +#define SYS2_CLKSR_SWINT (0x1 << 24) +#define SYS2_CLKSR_SWINT_VAL(val) (((val) & 0x1) << 24) +#define SYS2_CLKSR_SWINT_GET(val) (((val) & SYS2_CLKSR_SWINT) >> 24) + /* Clock Enable for HWACC3 */ +#define SYS2_CLKSR_HWACC3 (0x1 << 19) +#define SYS2_CLKSR_HWACC3_VAL(val) (((val) & +#define SYS2_CLKSR_HWACC3_GET(val) (((val) & SYS2_CLKSR_HWACC3) >> 19) + /* Clock Enable for HWACC2 */ +#define SYS2_CLKSR_HWACC2 (0x1 << 18) +#define SYS2_CLKSR_HWACC2_VAL(val) (((val) & +#define SYS2_CLKSR_HWACC2_GET(val) (((val) & SYS2_CLKSR_HWACC2) >> 18) + /* Clock Enable for HWACC1 */ +#define SYS2_CLKSR_HWACC1 (0x1 << 17) +#define SYS2_CLKSR_HWACC1_VAL(val) (((val) & +#define SYS2_CLKSR_HWACC1_GET(val) (((val) & SYS2_CLKSR_HWACC1) >> 17) + /* Clock Enable for HWACC0 */ +#define SYS2_CLKSR_HWACC0 (0x1 << 16) +#define SYS2_CLKSR_HWACC0_VAL(val) (((val) & +#define SYS2_CLKSR_HWACC0_GET(val) (((val) & SYS2_CLKSR_HWACC0) >> 16) + /* Clock Enable for SIF7 */ +#define SYS2_CLKSR_SIF7 (0x1 << 15) +#define SYS2_CLKSR_SIF7_VAL(val) (((val) & 0x1) << 15) +#define SYS2_CLKSR_SIF7_GET(val) (((val) & SYS2_CLKSR_SIF7) >> 15) + /* Clock Enable for SIF6 */ +#define SYS2_CLKSR_SIF6 (0x1 << 14) +#define SYS2_CLKSR_SIF6_VAL(val) (((val) & 0x1) << 14) +#define SYS2_CLKSR_SIF6_GET(val) (((val) & SYS2_CLKSR_SIF6) >> 14) + /* Clock Enable for SIF5 */ +#define SYS2_CLKSR_SIF5 (0x1 << 13) +#define SYS2_CLKSR_SIF5_VAL(val) (((val) & 0x1) << 13) +#define SYS2_CLKSR_SIF5_GET(val) (((val) & SYS2_CLKSR_SIF5) >> 13) + /* Clock Enable for SIF4 */ +#define SYS2_CLKSR_SIF4 (0x1 << 12) +#define SYS2_CLKSR_SIF4_VAL(val) (((val) & 0x1) << 12) +#define SYS2_CLKSR_SIF4_GET(val) (((val) & SYS2_CLKSR_SIF4) >> 12) + /* Clock Enable for SIF3 */ +#define SYS2_CLKSR_SIF3 (0x1 << 11) +#define SYS2_CLKSR_SIF3_VAL(val) (((val) & 0x1) << 11) +#define SYS2_CLKSR_SIF3_GET(val) (((val) & SYS2_CLKSR_SIF3) >> 11) +/* Clock Enable for SIF2 */ +#define SYS2_CLKSR_SIF2 (0x1 << 10) +#define SYS2_CLKSR_SIF2_VAL(val) (((val) & 0x1) << 10) +#define SYS2_CLKSR_SIF2_GET(val) (((val) & SYS2_CLKSR_SIF2) >> 10) +/* Clock Enable for SIF1 */ +#define SYS2_CLKSR_SIF1 (0x1 << 9) +#define SYS2_CLKSR_SIF1_VAL(val) (((val) & 0x1) << 9) +#define SYS2_CLKSR_SIF1_GET(val) (((val) & SYS2_CLKSR_SIF1) >> 9) +/* Clock Enable for SIF0 */ +#define SYS2_CLKSR_SIF0 (0x1 << 8) +#define SYS2_CLKSR_SIF0_VAL(val) (((val) & 0x1) << 8) +#define SYS2_CLKSR_SIF0_GET(val) (((val) & SYS2_CLKSR_SIF0) >> 8) +/* Clock Enable for DFEV7 */ +#define SYS2_CLKSR_DFEV7 (0x1 << 7) +#define SYS2_CLKSR_DFEV7_VAL(val) (((val) & 0x1) << 7) +#define SYS2_CLKSR_DFEV7_GET(val) (((val) & SYS2_CLKSR_DFEV7) >> 7) +/* Clock Enable for DFEV6 */ +#define SYS2_CLKSR_DFEV6 (0x1 << 6) +#define SYS2_CLKSR_DFEV6_VAL(val) (((val) & 0x1) << 6) +#define SYS2_CLKSR_DFEV6_GET(val) (((val) & SYS2_CLKSR_DFEV6) >> 6) +/* Clock Enable for DFEV5 */ +#define SYS2_CLKSR_DFEV5 (0x1 << 5) +#define SYS2_CLKSR_DFEV5_VAL(val) (((val) & 0x1) << 5) +#define SYS2_CLKSR_DFEV5_GET(val) (((val) & SYS2_CLKSR_DFEV5) >> 5) +/* Clock Enable for DFEV4 */ +#define SYS2_CLKSR_DFEV4 (0x1 << 4) +#define SYS2_CLKSR_DFEV4_VAL(val) (((val) & 0x1) << 4) +#define SYS2_CLKSR_DFEV4_GET(val) (((val) & SYS2_CLKSR_DFEV4) >> 4) +/* Clock Enable for DFEV3 */ +#define SYS2_CLKSR_DFEV3 (0x1 << 3) +#define SYS2_CLKSR_DFEV3_VAL(val) (((val) & 0x1) << 3) +#define SYS2_CLKSR_DFEV3_GET(val) (((val) & SYS2_CLKSR_DFEV3) >> 3) +/* Clock Enable for DFEV2 */ +#define SYS2_CLKSR_DFEV2 (0x1 << 2) +#define SYS2_CLKSR_DFEV2_VAL(val) (((val) & 0x1) << 2) +#define SYS2_CLKSR_DFEV2_GET(val) (((val) & SYS2_CLKSR_DFEV2) >> 2) +/* Clock Enable for DFEV1 */ +#define SYS2_CLKSR_DFEV1 (0x1 << 1) +#define SYS2_CLKSR_DFEV1_VAL(val) (((val) & 0x1) << 1) +#define SYS2_CLKSR_DFEV1_GET(val) (((val) & SYS2_CLKSR_DFEV1) >> 1) +/* Clock Enable for DFEV0 */ +#define SYS2_CLKSR_DFEV0 (0x1) +#define SYS2_CLKSR_DFEV0_VAL(val) (((val) & 0x1)) +#define SYS2_CLKSR_DFEV0_GET(val) ((val) & SYS2_CLKSR_DFEV0) + +/******************************************************************************* + * SYS2 Clock Enable Register + ******************************************************************************/ + +/* Clock Enable Request for PORT4 */ +#define SYS2_CLKENR_PORT4 (0x1 << 27) +#define SYS2_CLKENR_PORT4_VAL(val) (((val) & 0x1) << 27) +#define SYS2_CLKENR_PORT4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_PORT4) | ((val & 0x1) << 27)) +/* Clock Enable Request for HWSYNC */ +#define SYS2_CLKENR_HWSYNC (0x1 << 26) +#define SYS2_CLKENR_HWSYNC_VAL(val) (((val) & 0x1) << 26) +#define SYS2_CLKENR_HWSYNC_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWSYNC) | ((val & 0x1) << 26)) +/* Clock Enable Request for MBS */ +#define SYS2_CLKENR_MBS (0x1 << 25) +#define SYS2_CLKENR_MBS_VAL(val) (((val) & 0x1) << 25) +#define SYS2_CLKENR_MBS_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_MBS) | ((val & 0x1) << 25)) +/* Clock Enable Request for SWINT */ +#define SYS2_CLKENR_SWINT (0x1 << 24) +#define SYS2_CLKENR_SWINT_VAL(val) (((val) & 0x1) << 24) +#define SYS2_CLKENR_SWINT_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SWINT) | ((val & 0x1) << 24)) +/* Clock Enable Request for HWACC3 */ +#define SYS2_CLKENR_HWACC3 (0x1 << 19) +#define SYS2_CLKENR_HWACC3_VAL(val) (((val) & 0x1) << 19) +#define SYS2_CLKENR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC3) | ((val & 0x1) << 19)) +/* Clock Enable Request for HWACC2 */ +#define SYS2_CLKENR_HWACC2 (0x1 << 18) +#define SYS2_CLKENR_HWACC2_VAL(val) (((val) & 0x1) << 18) +#define SYS2_CLKENR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC2) | ((val & 0x1) << 18)) +/* Clock Enable Request for HWACC1 */ +#define SYS2_CLKENR_HWACC1 (0x1 << 17) +#define SYS2_CLKENR_HWACC1_VAL(val) (((val) & 0x1) << 17) +#define SYS2_CLKENR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC1) | ((val & 0x1) << 17)) +/* Clock Enable Request for HWACC0 */ +#define SYS2_CLKENR_HWACC0 (0x1 << 16) +#define SYS2_CLKENR_HWACC0_VAL(val) (((val) & 0x1) << 16) +#define SYS2_CLKENR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC0) | ((val & 0x1) << 16)) +/* Clock Enable Request for SIF7 */ +#define SYS2_CLKENR_SIF7 (0x1 << 15) +#define SYS2_CLKENR_SIF7_VAL(val) (((val) & 0x1) << 15) +#define SYS2_CLKENR_SIF7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF7) | ((val & 0x1) << 15)) +/* Clock Enable Request for SIF6 */ +#define SYS2_CLKENR_SIF6 (0x1 << 14) +#define SYS2_CLKENR_SIF6_VAL(val) (((val) & 0x1) << 14) +#define SYS2_CLKENR_SIF6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF6) | ((val & 0x1) << 14)) +/* Clock Enable Request for SIF5 */ +#define SYS2_CLKENR_SIF5 (0x1 << 13) +#define SYS2_CLKENR_SIF5_VAL(val) (((val) & 0x1) << 13) +#define SYS2_CLKENR_SIF5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF5) | ((val & 0x1) << 13)) +/* Clock Enable Request for SIF4 */ +#define SYS2_CLKENR_SIF4 (0x1 << 12) +#define SYS2_CLKENR_SIF4_VAL(val) (((val) & 0x1) << 12) +#define SYS2_CLKENR_SIF4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF4) | ((val & 0x1) << 12)) +/* Clock Enable Request for SIF3 */ +#define SYS2_CLKENR_SIF3 (0x1 << 11) +#define SYS2_CLKENR_SIF3_VAL(val) (((val) & 0x1) << 11) +#define SYS2_CLKENR_SIF3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF3) | ((val & 0x1) << 11)) +/* Clock Enable Request for SIF2 */ +#define SYS2_CLKENR_SIF2 (0x1 << 10) +#define SYS2_CLKENR_SIF2_VAL(val) (((val) & 0x1) << 10) +#define SYS2_CLKENR_SIF2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF2) | ((val & 0x1) << 10)) +/* Clock Enable Request for SIF1 */ +#define SYS2_CLKENR_SIF1 (0x1 << 9) +#define SYS2_CLKENR_SIF1_VAL(val) (((val) & 0x1) << 9) +#define SYS2_CLKENR_SIF1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF1) | ((val & 0x1) << 9)) +/* Clock Enable Request for SIF0 */ +#define SYS2_CLKENR_SIF0 (0x1 << 8) +#define SYS2_CLKENR_SIF0_VAL(val) (((val) & 0x1) << 8) +#define SYS2_CLKENR_SIF0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF0) | ((val & 0x1) << 8)) +/* Clock Enable Request for DFEV7 */ +#define SYS2_CLKENR_DFEV7 (0x1 << 7) +#define SYS2_CLKENR_DFEV7_VAL(val) (((val) & 0x1) << 7) +#define SYS2_CLKENR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV7) | ((val & 0x1) << 7)) +/* Clock Enable Request for DFEV6 */ +#define SYS2_CLKENR_DFEV6 (0x1 << 6) +#define SYS2_CLKENR_DFEV6_VAL(val) (((val) & 0x1) << 6) +#define SYS2_CLKENR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV6) | ((val & 0x1) << 6)) +/* Clock Enable Request for DFEV5 */ +#define SYS2_CLKENR_DFEV5 (0x1 << 5) +#define SYS2_CLKENR_DFEV5_VAL(val) (((val) & 0x1) << 5) +#define SYS2_CLKENR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV5) | ((val & 0x1) << 5)) +/* Clock Enable Request for DFEV4 */ +#define SYS2_CLKENR_DFEV4 (0x1 << 4) +#define SYS2_CLKENR_DFEV4_VAL(val) (((val) & 0x1) << 4) +#define SYS2_CLKENR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV4) | ((val & 0x1) << 4)) +/* Clock Enable Request for DFEV3 */ +#define SYS2_CLKENR_DFEV3 (0x1 << 3) +#define SYS2_CLKENR_DFEV3_VAL(val) (((val) & 0x1) << 3) +#define SYS2_CLKENR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV3) | ((val & 0x1) << 3)) +/* Clock Enable Request for DFEV2 */ +#define SYS2_CLKENR_DFEV2 (0x1 << 2) +#define SYS2_CLKENR_DFEV2_VAL(val) (((val) & 0x1) << 2) +#define SYS2_CLKENR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV2) | ((val & 0x1) << 2)) +/* Clock Enable Request for DFEV1 */ +#define SYS2_CLKENR_DFEV1 (0x1 << 1) +#define SYS2_CLKENR_DFEV1_VAL(val) (((val) & 0x1) << 1) +#define SYS2_CLKENR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV1) | ((val & 0x1) << 1)) +/* Clock Enable Request for DFEV0 */ +#define SYS2_CLKENR_DFEV0 (0x1) +#define SYS2_CLKENR_DFEV0_VAL(val) (((val) & 0x1)) +#define SYS2_CLKENR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV0) | ((val & 0x1))) + +/******************************************************************************* + * SYS2 Clock Clear Register + ******************************************************************************/ + +/* Clock Disable Request for PORT4 */ +#define SYS2_CLKCLR_PORT4 (0x1 << 27) +#define SYS2_CLKCLR_PORT4_VAL(val) (((val) & 0x1) << 27) +#define SYS2_CLKCLR_PORT4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_PORT4) | ((val & 0x1) << 27)) +/* Clock Disable Request for HWSYNC */ +#define SYS2_CLKCLR_HWSYNC (0x1 << 26) +#define SYS2_CLKCLR_HWSYNC_VAL(val) (((val) & 0x1) << 26) +#define SYS2_CLKCLR_HWSYNC_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWSYNC) | ((val & 0x1) << 26)) +/* Clock Disable Request for MBS */ +#define SYS2_CLKCLR_MBS (0x1 << 25) +#define SYS2_CLKCLR_MBS_VAL(val) (((val) & 0x1) << 25) +#define SYS2_CLKCLR_MBS_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_MBS) | ((val & 0x1) << 25)) +/* Clock Disable Request for SWINT */ +#define SYS2_CLKCLR_SWINT (0x1 << 24) +#define SYS2_CLKCLR_SWINT_VAL(val) (((val) & 0x1) << 24) +#define SYS2_CLKCLR_SWINT_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SWINT) | ((val & 0x1) << 24)) +/* Clock Disable Request for HWACC3 */ +#define SYS2_CLKCLR_HWACC3 (0x1 << 19) +#define SYS2_CLKCLR_HWACC3_VAL(val) (((val) & 0x1) << 19) +#define SYS2_CLKCLR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC3) | ((val & 0x1) << 19)) +/* Clock Disable Request for HWACC2 */ +#define SYS2_CLKCLR_HWACC2 (0x1 << 18) +#define SYS2_CLKCLR_HWACC2_VAL(val) (((val) & 0x1) << 18) +#define SYS2_CLKCLR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC2) | ((val & 0x1) << 18)) +/* Clock Disable Request for HWACC1 */ +#define SYS2_CLKCLR_HWACC1 (0x1 << 17) +#define SYS2_CLKCLR_HWACC1_VAL(val) (((val) & 0x1) << 17) +#define SYS2_CLKCLR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC1) | ((val & 0x1) << 17)) +/* Clock Disable Request for HWACC0 */ +#define SYS2_CLKCLR_HWACC0 (0x1 << 16) +#define SYS2_CLKCLR_HWACC0_VAL(val) (((val) & 0x1) << 16) +#define SYS2_CLKCLR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC0) | ((val & 0x1) << 16)) +/* Clock Disable Request for SIF7 */ +#define SYS2_CLKCLR_SIF7 (0x1 << 15) +#define SYS2_CLKCLR_SIF7_VAL(val) (((val) & 0x1) << 15) +#define SYS2_CLKCLR_SIF7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF7) | ((val & 0x1) << 15)) +/* Clock Disable Request for SIF6 */ +#define SYS2_CLKCLR_SIF6 (0x1 << 14) +#define SYS2_CLKCLR_SIF6_VAL(val) (((val) & 0x1) << 14) +#define SYS2_CLKCLR_SIF6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF6) | ((val & 0x1) << 14)) +/* Clock Disable Request for SIF5 */ +#define SYS2_CLKCLR_SIF5 (0x1 << 13) +#define SYS2_CLKCLR_SIF5_VAL(val) (((val) & 0x1) << 13) +#define SYS2_CLKCLR_SIF5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF5) | ((val & 0x1) << 13)) +/* Clock Disable Request for SIF4 */ +#define SYS2_CLKCLR_SIF4 (0x1 << 12) +#define SYS2_CLKCLR_SIF4_VAL(val) (((val) & 0x1) << 12) +#define SYS2_CLKCLR_SIF4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF4) | ((val & 0x1) << 12)) +/* Clock Disable Request for SIF3 */ +#define SYS2_CLKCLR_SIF3 (0x1 << 11) +#define SYS2_CLKCLR_SIF3_VAL(val) (((val) & 0x1) << 11) +#define SYS2_CLKCLR_SIF3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF3) | ((val & 0x1) << 11)) +/* Clock Disable Request for SIF2 */ +#define SYS2_CLKCLR_SIF2 (0x1 << 10) +#define SYS2_CLKCLR_SIF2_VAL(val) (((val) & 0x1) << 10) +#define SYS2_CLKCLR_SIF2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF2) | ((val & 0x1) << 10)) +/* Clock Disable Request for SIF1 */ +#define SYS2_CLKCLR_SIF1 (0x1 << 9) +#define SYS2_CLKCLR_SIF1_VAL(val) (((val) & 0x1) << 9) +#define SYS2_CLKCLR_SIF1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF1) | ((val & 0x1) << 9)) +/* Clock Disable Request for SIF0 */ +#define SYS2_CLKCLR_SIF0 (0x1 << 8) +#define SYS2_CLKCLR_SIF0_VAL(val) (((val) & 0x1) << 8) +#define SYS2_CLKCLR_SIF0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF0) | ((val & 0x1) << 8)) +/* Clock Disable Request for DFEV7 */ +#define SYS2_CLKCLR_DFEV7 (0x1 << 7) +#define SYS2_CLKCLR_DFEV7_VAL(val) (((val) & 0x1) << 7) +#define SYS2_CLKCLR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV7) | ((val & 0x1) << 7)) +/* Clock Disable Request for DFEV6 */ +#define SYS2_CLKCLR_DFEV6 (0x1 << 6) +#define SYS2_CLKCLR_DFEV6_VAL(val) (((val) & 0x1) << 6) +#define SYS2_CLKCLR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV6) | ((val & 0x1) << 6)) +/* Clock Disable Request for DFEV5 */ +#define SYS2_CLKCLR_DFEV5 (0x1 << 5) +#define SYS2_CLKCLR_DFEV5_VAL(val) (((val) & 0x1) << 5) +#define SYS2_CLKCLR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV5) | ((val & 0x1) << 5)) +/* Clock Disable Request for DFEV4 */ +#define SYS2_CLKCLR_DFEV4 (0x1 << 4) +#define SYS2_CLKCLR_DFEV4_VAL(val) (((val) & 0x1) << 4) +#define SYS2_CLKCLR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV4) | ((val & 0x1) << 4)) +/* Clock Disable Request for DFEV3 */ +#define SYS2_CLKCLR_DFEV3 (0x1 << 3) +#define SYS2_CLKCLR_DFEV3_VAL(val) (((val) & 0x1) << 3) +#define SYS2_CLKCLR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV3) | ((val & 0x1) << 3)) +/* Clock Disable Request for DFEV2 */ +#define SYS2_CLKCLR_DFEV2 (0x1 << 2) +#define SYS2_CLKCLR_DFEV2_VAL(val) (((val) & 0x1) << 2) +#define SYS2_CLKCLR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV2) | ((val & 0x1) << 2)) +/* Clock Disable Request for DFEV1 */ +#define SYS2_CLKCLR_DFEV1 (0x1 << 1) +#define SYS2_CLKCLR_DFEV1_VAL(val) (((val) & 0x1) << 1) +#define SYS2_CLKCLR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV1) | ((val & 0x1) << 1)) +/* Clock Disable Request for DFEV0 */ +#define SYS2_CLKCLR_DFEV0 (0x1) +#define SYS2_CLKCLR_DFEV0_VAL(val) (((val) & 0x1)) +#define SYS2_CLKCLR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV0) | ((val & 0x1))) + +/******************************************************************************* + * SYS2 Reset Status Register + ******************************************************************************/ + +/* HWACC3 Reset */ +#define SYS2_RSR_HWACC3 (0x1 << 11) +#define SYS2_RSR_HWACC3_VAL(val) (((val) & 0x1) << 11) +#define SYS2_RSR_HWACC3_GET(val) (((val) & SYS2_RSR_HWACC3) >> 11) +/* HWACC2 Reset */ +#define SYS2_RSR_HWACC2 (0x1 << 10) +#define SYS2_RSR_HWACC2_VAL(val) (((val) & 0x1) << 10) +#define SYS2_RSR_HWACC2_GET(val) (((val) & SYS2_RSR_HWACC2) >> 10) +/* HWACC1 Reset */ +#define SYS2_RSR_HWACC1 (0x1 << 9) +#define SYS2_RSR_HWACC1_VAL(val) (((val) & 0x1) << 9) +#define SYS2_RSR_HWACC1_GET(val) (((val) & SYS2_RSR_HWACC1) >> 9) +/* HWACC0 Reset */ +#define SYS2_RSR_HWACC0 (0x1 << 8) +#define SYS2_RSR_HWACC0_VAL(val) (((val) & 0x1) << 8) +#define SYS2_RSR_HWACC0_GET(val) (((val) & SYS2_RSR_HWACC0) >> 8) +/* DFEV7 Reset */ +#define SYS2_RSR_DFEV7 (0x1 << 7) +#define SYS2_RSR_DFEV7_VAL(val) (((val) & 0x1) << 7) +#define SYS2_RSR_DFEV7_GET(val) (((val) & SYS2_RSR_DFEV7) >> 7) +/* DFEV6 Reset */ +#define SYS2_RSR_DFEV6 (0x1 << 6) +#define SYS2_RSR_DFEV6_VAL(val) (((val) & 0x1) << 6) +#define SYS2_RSR_DFEV6_GET(val) (((val) & SYS2_RSR_DFEV6) >> 6) +/* DFEV5 Reset */ +#define SYS2_RSR_DFEV5 (0x1 << 5) +#define SYS2_RSR_DFEV5_VAL(val) (((val) & 0x1) << 5) +#define SYS2_RSR_DFEV5_GET(val) (((val) & SYS2_RSR_DFEV5) >> 5) +/* DFEV4 Reset */ +#define SYS2_RSR_DFEV4 (0x1 << 4) +#define SYS2_RSR_DFEV4_VAL(val) (((val) & 0x1) << 4) +#define SYS2_RSR_DFEV4_GET(val) (((val) & SYS2_RSR_DFEV4) >> 4) +/* DFEV3 Reset */ +#define SYS2_RSR_DFEV3 (0x1 << 3) +#define SYS2_RSR_DFEV3_VAL(val) (((val) & 0x1) << 3) +#define SYS2_RSR_DFEV3_GET(val) (((val) & SYS2_RSR_DFEV3) >> 3) +/* DFEV2 Reset */ +#define SYS2_RSR_DFEV2 (0x1 << 2) +#define SYS2_RSR_DFEV2_VAL(val) (((val) & 0x1) << 2) +#define SYS2_RSR_DFEV2_GET(val) (((val) & SYS2_RSR_DFEV2) >> 2) +/* DFEV1 Reset */ +#define SYS2_RSR_DFEV1 (0x1 << 1) +#define SYS2_RSR_DFEV1_VAL(val) (((val) & 0x1) << 1) +#define SYS2_RSR_DFEV1_GET(val) (((val) & SYS2_RSR_DFEV1) >> 1) +/* DFEV0 Reset */ +#define SYS2_RSR_DFEV0 (0x1) +#define SYS2_RSR_DFEV0_VAL(val) (((val) & 0x1)) +#define SYS2_RSR_DFEV0_GET(val) ((val) & SYS2_RSR_DFEV0) + +/****************************************************************************** + * SYS2 Reset Request Register + ******************************************************************************/ + +/* HWACC3 Reset Request */ +#define SYS2_RREQR_HWACC3 (0x1 << 11) +#define SYS2_RREQR_HWACC3_VAL(val) (((val) & 0x1) << 11) +#define SYS2_RREQR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC3) | ((val & 0x1) << 11)) +/* HWACC2 Reset Request */ +#define SYS2_RREQR_HWACC2 (0x1 << 10) +#define SYS2_RREQR_HWACC2_VAL(val) (((val) & 0x1) << 10) +#define SYS2_RREQR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC2) | ((val & 0x1) << 10)) +/* HWACC1 Reset Request */ +#define SYS2_RREQR_HWACC1 (0x1 << 9) +#define SYS2_RREQR_HWACC1_VAL(val) (((val) & 0x1) << 9) +#define SYS2_RREQR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC1) | ((val & 0x1) << 9)) +/* HWACC0 Reset Request */ +#define SYS2_RREQR_HWACC0 (0x1 << 8) +#define SYS2_RREQR_HWACC0_VAL(val) (((val) & 0x1) << 8) +#define SYS2_RREQR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC0) | ((val & 0x1) << 8)) +/* DFEV7 Reset Request */ +#define SYS2_RREQR_DFEV7 (0x1 << 7) +#define SYS2_RREQR_DFEV7_VAL(val) (((val) & 0x1) << 7) +#define SYS2_RREQR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV7) | ((val & 0x1) << 7)) +/* DFEV6 Reset Request */ +#define SYS2_RREQR_DFEV6 (0x1 << 6) +#define SYS2_RREQR_DFEV6_VAL(val) (((val) & 0x1) << 6) +#define SYS2_RREQR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV6) | ((val & 0x1) << 6)) +/* DFEV5 Reset Request */ +#define SYS2_RREQR_DFEV5 (0x1 << 5) +#define SYS2_RREQR_DFEV5_VAL(val) (((val) & 0x1) << 5) +#define SYS2_RREQR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV5) | ((val & 0x1) << 5)) +/* DFEV4 Reset Request */ +#define SYS2_RREQR_DFEV4 (0x1 << 4) +#define SYS2_RREQR_DFEV4_VAL(val) (((val) & 0x1) << 4) +#define SYS2_RREQR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV4) | ((val & 0x1) << 4)) +/* DFEV3 Reset Request */ +#define SYS2_RREQR_DFEV3 (0x1 << 3) +#define SYS2_RREQR_DFEV3_VAL(val) (((val) & 0x1) << 3) +#define SYS2_RREQR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV3) | ((val & 0x1) << 3)) +/* DFEV2 Reset Request */ +#define SYS2_RREQR_DFEV2 (0x1 << 2) +#define SYS2_RREQR_DFEV2_VAL(val) (((val) & 0x1) << 2) +#define SYS2_RREQR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV2) | ((val & 0x1) << 2)) +/* DFEV1 Reset Request */ +#define SYS2_RREQR_DFEV1 (0x1 << 1) +#define SYS2_RREQR_DFEV1_VAL(val) (((val) & 0x1) << 1) +#define SYS2_RREQR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV1) | ((val & 0x1) << 1)) +/* DFEV0 Reset Request */ +#define SYS2_RREQR_DFEV0 (0x1) +#define SYS2_RREQR_DFEV0_VAL(val) (((val) & 0x1)) +#define SYS2_RREQR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV0) | ((val & 0x1))) + +/******************************************************************************* + * SYS2 Reset Release Register + ******************************************************************************/ + +/* HWACC3 Reset Release */ +#define SYS2_RRLSR_HWACC3 (0x1 << 11) +#define SYS2_RRLSR_HWACC3_VAL(val) (((val) & 0x1) << 11) +#define SYS2_RRLSR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC3) | ((val & 0x1) << 11)) +/* HWACC2 Reset Release */ +#define SYS2_RRLSR_HWACC2 (0x1 << 10) +#define SYS2_RRLSR_HWACC2_VAL(val) (((val) & 0x1) << 10) +#define SYS2_RRLSR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC2) | ((val & 0x1) << 10)) +/* HWACC1 Reset Release */ +#define SYS2_RRLSR_HWACC1 (0x1 << 9) +#define SYS2_RRLSR_HWACC1_VAL(val) (((val) & 0x1) << 9) +#define SYS2_RRLSR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC1) | ((val & 0x1) << 9)) +/* HWACC0 Reset Release */ +#define SYS2_RRLSR_HWACC0 (0x1 << 8) +#define SYS2_RRLSR_HWACC0_VAL(val) (((val) & 0x1) << 8) +#define SYS2_RRLSR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC0) | ((val & 0x1) << 8)) +/* DFEV7 Reset Release */ +#define SYS2_RRLSR_DFEV7 (0x1 << 7) +#define SYS2_RRLSR_DFEV7_VAL(val) (((val) & 0x1) << 7) +#define SYS2_RRLSR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV7) | ((val & 0x1) << 7)) +/* DFEV6 Reset Release */ +#define SYS2_RRLSR_DFEV6 (0x1 << 6) +#define SYS2_RRLSR_DFEV6_VAL(val) (((val) & 0x1) << 6) +#define SYS2_RRLSR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV6) | ((val & 0x1) << 6)) +/* DFEV5 Reset Release */ +#define SYS2_RRLSR_DFEV5 (0x1 << 5) +#define SYS2_RRLSR_DFEV5_VAL(val) (((val) & 0x1) << 5) +#define SYS2_RRLSR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV5) | ((val & 0x1) << 5)) +/* DFEV4 Reset Release */ +#define SYS2_RRLSR_DFEV4 (0x1 << 4) +#define SYS2_RRLSR_DFEV4_VAL(val) (((val) & 0x1) << 4) +#define SYS2_RRLSR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV4) | ((val & 0x1) << 4)) +/* DFEV3 Reset Release */ +#define SYS2_RRLSR_DFEV3 (0x1 << 3) +#define SYS2_RRLSR_DFEV3_VAL(val) (((val) & 0x1) << 3) +#define SYS2_RRLSR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV3) | ((val & 0x1) << 3)) +/* DFEV2 Reset Release */ +#define SYS2_RRLSR_DFEV2 (0x1 << 2) +#define SYS2_RRLSR_DFEV2_VAL(val) (((val) & 0x1) << 2) +#define SYS2_RRLSR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV2) | ((val & 0x1) << 2)) +/* DFEV1 Reset Release */ +#define SYS2_RRLSR_DFEV1 (0x1 << 1) +#define SYS2_RRLSR_DFEV1_VAL(val) (((val) & 0x1) << 1) +#define SYS2_RRLSR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV1) | ((val & 0x1) << 1)) +/* DFEV0 Reset Release */ +#define SYS2_RRLSR_DFEV0 (0x1) +#define SYS2_RRLSR_DFEV0_VAL(val) (((val) & 0x1)) +#define SYS2_RRLSR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV0) | ((val & 0x1))) + +#endif /* __SYS2_H */ + diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/Kconfig b/target/linux/lantiq/files/arch/mips/lantiq/falcon/Kconfig new file mode 100644 index 0000000000..03e999d92e --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/falcon/Kconfig @@ -0,0 +1,11 @@ +if SOC_FALCON + +menu "MIPS Machine" + +config LANTIQ_MACH_EASY98000 + bool "Easy98000" + default y + +endmenu + +endif diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/Makefile b/target/linux/lantiq/files/arch/mips/lantiq/falcon/Makefile new file mode 100644 index 0000000000..3634154fb9 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/falcon/Makefile @@ -0,0 +1,2 @@ +obj-y := prom.o reset.o sysctrl.o devices.o gpio.o +obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/devices.c b/target/linux/lantiq/files/arch/mips/lantiq/falcon/devices.c new file mode 100644 index 0000000000..e684ed470f --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/falcon/devices.c @@ -0,0 +1,152 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include + +#include + +#include "devices.h" + +/* nand flash */ +/* address lines used for NAND control signals */ +#define NAND_ADDR_ALE 0x10000 +#define NAND_ADDR_CLE 0x20000 +/* Ready/Busy Status */ +#define MODCON_STS 0x0002 +/* Ready/Busy Status Edge */ +#define MODCON_STSEDGE 0x0004 + +static const char *part_probes[] = { "cmdlinepart", NULL }; + +static int +falcon_nand_ready(struct mtd_info *mtd) +{ + u32 modcon = ltq_ebu_r32(LTQ_EBU_MODCON); + + return (((modcon & (MODCON_STS | MODCON_STSEDGE)) == + (MODCON_STS | MODCON_STSEDGE))); +} + +static void +falcon_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; + + if (ctrl & NAND_CTRL_CHANGE) { + nandaddr &= ~(NAND_ADDR_ALE | NAND_ADDR_CLE); + + if (ctrl & NAND_CLE) + nandaddr |= NAND_ADDR_CLE; + if (ctrl & NAND_ALE) + nandaddr |= NAND_ADDR_ALE; + + this->IO_ADDR_W = (void __iomem *) nandaddr; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +static struct platform_nand_data falcon_flash_nand_data = { + .chip = { + .nr_chips = 1, + .chip_delay = 25, + .part_probe_types = part_probes, + }, + .ctrl = { + .cmd_ctrl = falcon_hwcontrol, + .dev_ready = falcon_nand_ready, + } +}; + +static struct resource ltq_nand_res = + MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX); + +static struct platform_device ltq_flash_nand = { + .name = "gen_nand", + .id = -1, + .num_resources = 1, + .resource = <q_nand_res, + .dev = { + .platform_data = &falcon_flash_nand_data, + }, +}; + +void __init +falcon_register_nand(void) +{ + platform_device_register(<q_flash_nand); +} + +/* gpio */ +#define DECLARE_GPIO_RES(port) \ +static struct resource falcon_gpio ## port ## _res[] = { \ + MEM_RES("gpio"#port, LTQ_GPIO ## port ## _BASE_ADDR, \ + LTQ_GPIO ## port ## _SIZE), \ + MEM_RES("padctrl"#port, LTQ_PADCTRL ## port ## _BASE_ADDR, \ + LTQ_PADCTRL ## port ## _SIZE), \ + IRQ_RES("gpio_mux"#port, FALCON_IRQ_GPIO_P ## port) \ +} +DECLARE_GPIO_RES(0); +DECLARE_GPIO_RES(1); +DECLARE_GPIO_RES(2); +DECLARE_GPIO_RES(3); +DECLARE_GPIO_RES(4); + +void __init +falcon_register_gpio(void) +{ + platform_device_register_simple("falcon_gpio", 0, + falcon_gpio0_res, ARRAY_SIZE(falcon_gpio0_res)); + platform_device_register_simple("falcon_gpio", 1, + falcon_gpio1_res, ARRAY_SIZE(falcon_gpio1_res)); + platform_device_register_simple("falcon_gpio", 2, + falcon_gpio2_res, ARRAY_SIZE(falcon_gpio2_res)); +} + +void __init +falcon_register_gpio_extra(void) +{ + platform_device_register_simple("falcon_gpio", 3, + falcon_gpio3_res, ARRAY_SIZE(falcon_gpio3_res)); + platform_device_register_simple("falcon_gpio", 4, + falcon_gpio4_res, ARRAY_SIZE(falcon_gpio4_res)); +} + +/* spi flash */ +static struct platform_device ltq_spi = { + .name = "falcon_spi", + .num_resources = 0, +}; + +void __init +falcon_register_spi_flash(struct spi_board_info *data) +{ + spi_register_board_info(data, 1); + platform_device_register(<q_spi); +} + +/* i2c */ +static struct resource falcon_i2c_resources[] = { + MEM_RES("i2c", GPON_I2C_BASE, GPON_I2C_SIZE), + IRQ_RES(i2c_lb, FALCON_IRQ_I2C_LBREQ), + IRQ_RES(i2c_b, FALCON_IRQ_I2C_BREQ), + IRQ_RES(i2c_err, FALCON_IRQ_I2C_I2C_ERR), + IRQ_RES(i2c_p, FALCON_IRQ_I2C_I2C_P), +}; + +void __init +falcon_register_i2c(void) +{ + platform_device_register_simple("i2c-falcon", 0, + falcon_i2c_resources, ARRAY_SIZE(falcon_i2c_resources)); +} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/devices.h b/target/linux/lantiq/files/arch/mips/lantiq/falcon/devices.h new file mode 100644 index 0000000000..d81edbe74e --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/falcon/devices.h @@ -0,0 +1,25 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#ifndef _FALCON_DEVICES_H__ +#define _FALCON_DEVICES_H__ + +#include +#include + +#include "../devices.h" + +extern void falcon_register_nand(void); +extern void falcon_register_gpio(void); +extern void falcon_register_gpio_extra(void); +extern void falcon_register_spi_flash(struct spi_board_info *data); +extern void falcon_register_i2c(void); + +#endif diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/gpio.c b/target/linux/lantiq/files/arch/mips/lantiq/falcon/gpio.c new file mode 100644 index 0000000000..4147d61c7d --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/falcon/gpio.c @@ -0,0 +1,409 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include +#include +#include +#include + +#include + +/* Multiplexer Control Register */ +#define LTQ_PADC_MUX(x) (x * 0x4) +/* Pad Control Availability Register */ +#define LTQ_PADC_AVAIL 0x000000F0 + +/* Data Output Register */ +#define LTQ_GPIO_OUT 0x00000000 +/* Data Input Register */ +#define LTQ_GPIO_IN 0x00000004 +/* Direction Register */ +#define LTQ_GPIO_DIR 0x00000008 +/* External Interrupt Control Register 0 */ +#define LTQ_GPIO_EXINTCR0 0x00000018 +/* External Interrupt Control Register 1 */ +#define LTQ_GPIO_EXINTCR1 0x0000001C +/* IRN Capture Register */ +#define LTQ_GPIO_IRNCR 0x00000020 +/* IRN Interrupt Configuration Register */ +#define LTQ_GPIO_IRNCFG 0x0000002C +/* IRN Interrupt Enable Set Register */ +#define LTQ_GPIO_IRNRNSET 0x00000030 +/* IRN Interrupt Enable Clear Register */ +#define LTQ_GPIO_IRNENCLR 0x00000034 +/* Output Set Register */ +#define LTQ_GPIO_OUTSET 0x00000040 +/* Output Cler Register */ +#define LTQ_GPIO_OUTCLR 0x00000044 +/* Direction Clear Register */ +#define LTQ_GPIO_DIRSET 0x00000048 +/* Direction Set Register */ +#define LTQ_GPIO_DIRCLR 0x0000004C + +/* turn a gpio_chip into a falcon_gpio_port */ +#define ctop(c) container_of(c, struct falcon_gpio_port, gpio_chip) +/* turn a irq_data into a falcon_gpio_port */ +#define itop(i) ((struct falcon_gpio_port *) irq_get_chip_data(i->irq)) + +#define ltq_pad_r32(p, reg) ltq_r32(p->pad + reg) +#define ltq_pad_w32(p, val, reg) ltq_w32(val, p->pad + reg) +#define ltq_pad_w32_mask(c, clear, set, reg) \ + ltq_pad_w32(c, (ltq_pad_r32(c, reg) & ~(clear)) | (set), reg) + +#define ltq_port_r32(p, reg) ltq_r32(p->port + reg) +#define ltq_port_w32(p, val, reg) ltq_w32(val, p->port + reg) +#define ltq_port_w32_mask(p, clear, set, reg) \ + ltq_port_w32(p, (ltq_port_r32(p, reg) & ~(clear)) | (set), reg) + +#define MAX_PORTS 5 +#define PINS_PER_PORT 32 + +struct falcon_gpio_port { + struct gpio_chip gpio_chip; + void __iomem *pad; + void __iomem *port; + unsigned int irq_base; + unsigned int chained_irq; + struct clk *clk; +}; + +static struct falcon_gpio_port ltq_gpio_port[MAX_PORTS]; + +int gpio_to_irq(unsigned int gpio) +{ + return __gpio_to_irq(gpio); +} +EXPORT_SYMBOL(gpio_to_irq); + +int ltq_gpio_mux_set(unsigned int pin, unsigned int mux) +{ + int port = pin / 100; + int offset = pin % 100; + struct falcon_gpio_port *gpio_port; + + if ((offset >= PINS_PER_PORT) || (port >= MAX_PORTS)) + return -EINVAL; + + gpio_port = <q_gpio_port[port]; + ltq_pad_w32(gpio_port, mux & 0x3, LTQ_PADC_MUX(offset)); + + return 0; +} +EXPORT_SYMBOL(ltq_gpio_mux_set); + +int ltq_gpio_request(struct device *dev, unsigned int pin, unsigned int mux, + unsigned int dir, const char *name) +{ + int port = pin / 100; + int offset = pin % 100; + + if (offset >= PINS_PER_PORT || port >= MAX_PORTS) + return -EINVAL; + + if (devm_gpio_request(dev, pin, name)) { + pr_err("failed to setup lantiq gpio: %s\n", name); + return -EBUSY; + } + + if (dir) + gpio_direction_output(pin, 1); + else + gpio_direction_input(pin); + + return ltq_gpio_mux_set(pin, mux); +} +EXPORT_SYMBOL(ltq_gpio_request); + +static int +falcon_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRCLR); + + return 0; +} + +static void +falcon_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + if (value) + ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTSET); + else + ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTCLR); +} + +static int +falcon_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + falcon_gpio_set(chip, offset, value); + ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRSET); + + return 0; +} + +static int +falcon_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + if ((ltq_port_r32(ctop(chip), LTQ_GPIO_DIR) >> offset) & 1) + return (ltq_port_r32(ctop(chip), LTQ_GPIO_OUT) >> offset) & 1; + else + return (ltq_port_r32(ctop(chip), LTQ_GPIO_IN) >> offset) & 1; +} + +static int +falcon_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) { + if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1) + return -EBUSY; + /* switch on gpio function */ + ltq_pad_w32(ctop(chip), 1, LTQ_PADC_MUX(offset)); + return 0; + } + + return -ENODEV; +} + +static void +falcon_gpio_free(struct gpio_chip *chip, unsigned offset) +{ + if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) { + if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1) + return; + /* switch off gpio function */ + ltq_pad_w32(ctop(chip), 0, LTQ_PADC_MUX(offset)); + } +} + +static int +falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset) +{ + return ctop(chip)->irq_base + offset; +} + +static void +falcon_gpio_disable_irq(struct irq_data *d) +{ + unsigned int offset = d->irq - itop(d)->irq_base; + + ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR); +} + +static void +falcon_gpio_enable_irq(struct irq_data *d) +{ + unsigned int offset = d->irq - itop(d)->irq_base; + + if (!ltq_pad_r32(itop(d), LTQ_PADC_MUX(offset)) < 1) + /* switch on gpio function */ + ltq_pad_w32(itop(d), 1, LTQ_PADC_MUX(offset)); + + ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNRNSET); +} + +static void +falcon_gpio_ack_irq(struct irq_data *d) +{ + unsigned int offset = d->irq - itop(d)->irq_base; + + ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR); +} + +static void +falcon_gpio_mask_and_ack_irq(struct irq_data *d) +{ + unsigned int offset = d->irq - itop(d)->irq_base; + + ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR); + ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR); +} + +static struct irq_chip falcon_gpio_irq_chip; +static int +falcon_gpio_irq_type(struct irq_data *d, unsigned int type) +{ + unsigned int offset = d->irq - itop(d)->irq_base; + unsigned int mask = 1 << offset; + + if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE) + return 0; + + if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) { + /* level triggered */ + ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_IRNCFG); + irq_set_chip_and_handler_name(d->irq, + &falcon_gpio_irq_chip, handle_level_irq, "mux"); + } else { + /* edge triggered */ + ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_IRNCFG); + irq_set_chip_and_handler_name(d->irq, + &falcon_gpio_irq_chip, handle_simple_irq, "mux"); + } + + if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { + ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0); + ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR1); + } else { + if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) != 0) + /* positive logic: rising edge, high level */ + ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0); + else + /* negative logic: falling edge, low level */ + ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR0); + ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR1); + } + + return gpio_direction_input(itop(d)->gpio_chip.base + offset); +} + +static void +falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc); + unsigned long irncr; + int offset; + + /* acknowledge interrupt */ + irncr = ltq_port_r32(gpio_port, LTQ_GPIO_IRNCR); + ltq_port_w32(gpio_port, irncr, LTQ_GPIO_IRNCR); + + desc->irq_data.chip->irq_ack(&desc->irq_data); + + for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio) + generic_handle_irq(gpio_port->irq_base + offset); +} + +static struct irq_chip falcon_gpio_irq_chip = { + .name = "gpio_irq_mux", + .irq_mask = falcon_gpio_disable_irq, + .irq_unmask = falcon_gpio_enable_irq, + .irq_ack = falcon_gpio_ack_irq, + .irq_mask_ack = falcon_gpio_mask_and_ack_irq, + .irq_set_type = falcon_gpio_irq_type, +}; + +static struct irqaction gpio_cascade = { + .handler = no_action, + .flags = IRQF_DISABLED, + .name = "gpio_cascade", +}; + +static int +falcon_gpio_probe(struct platform_device *pdev) +{ + struct falcon_gpio_port *gpio_port; + int ret, i; + struct resource *gpiores, *padres; + int irq; + + if (pdev->id >= MAX_PORTS) + return -ENODEV; + + gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0); + padres = platform_get_resource(pdev, IORESOURCE_MEM, 1); + irq = platform_get_irq(pdev, 0); + if (!gpiores || !padres) + return -ENODEV; + + gpio_port = <q_gpio_port[pdev->id]; + gpio_port->gpio_chip.label = "falcon-gpio"; + gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input; + gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output; + gpio_port->gpio_chip.get = falcon_gpio_get; + gpio_port->gpio_chip.set = falcon_gpio_set; + gpio_port->gpio_chip.request = falcon_gpio_request; + gpio_port->gpio_chip.free = falcon_gpio_free; + gpio_port->gpio_chip.base = 100 * pdev->id; + gpio_port->gpio_chip.ngpio = 32; + gpio_port->gpio_chip.dev = &pdev->dev; + + gpio_port->port = ltq_remap_resource(gpiores); + gpio_port->pad = ltq_remap_resource(padres); + + if (!gpio_port->port || !gpio_port->pad) { + dev_err(&pdev->dev, "Could not map io ranges\n"); + ret = -ENOMEM; + goto err; + } + + gpio_port->clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(gpio_port->clk)) { + dev_err(&pdev->dev, "Could not get clock\n"); + ret = PTR_ERR(gpio_port->clk);; + goto err; + } + clk_enable(gpio_port->clk); + + if (irq > 0) { + /* irq_chip support */ + gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq; + gpio_port->irq_base = INT_NUM_EXTRA_START + (32 * pdev->id); + + for (i = 0; i < 32; i++) { + irq_set_chip_and_handler_name(gpio_port->irq_base + i, + &falcon_gpio_irq_chip, handle_simple_irq, + "mux"); + irq_set_chip_data(gpio_port->irq_base + i, gpio_port); + /* set to negative logic (falling edge, low level) */ + ltq_port_w32_mask(gpio_port, 0, 1 << i, + LTQ_GPIO_EXINTCR0); + } + + gpio_port->chained_irq = irq; + setup_irq(irq, &gpio_cascade); + irq_set_handler_data(irq, gpio_port); + irq_set_chained_handler(irq, falcon_gpio_irq_handler); + } + + ret = gpiochip_add(&gpio_port->gpio_chip); + if (ret < 0) { + dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n", + pdev->id, ret); + goto err; + } + platform_set_drvdata(pdev, gpio_port); + return ret; + +err: + dev_err(&pdev->dev, "Error in gpio_probe %d, %d\n", pdev->id, ret); + if (gpiores) + release_resource(gpiores); + if (padres) + release_resource(padres); + + if (gpio_port->port) + iounmap(gpio_port->port); + if (gpio_port->pad) + iounmap(gpio_port->pad); + return ret; +} + +static struct platform_driver falcon_gpio_driver = { + .probe = falcon_gpio_probe, + .driver = { + .name = "falcon_gpio", + .owner = THIS_MODULE, + }, +}; + +int __init +falcon_gpio_init(void) +{ + int ret; + + pr_info("FALC(tm) ON GPIO Driver, (C) 2011 Lantiq Deutschland Gmbh\n"); + ret = platform_driver_register(&falcon_gpio_driver); + if (ret) + pr_err("falcon_gpio: Error registering platform driver!"); + return ret; +} + +postcore_initcall(falcon_gpio_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/mach-easy98000.c b/target/linux/lantiq/files/arch/mips/lantiq/falcon/mach-easy98000.c new file mode 100644 index 0000000000..fc5720d4ea --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/falcon/mach-easy98000.c @@ -0,0 +1,138 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include +#include +#include + +#include "../machtypes.h" + +#include "devices.h" + +static struct mtd_partition easy98000_nor_partitions[] = { + { + .name = "uboot", + .offset = 0x0, + .size = 0x40000, + }, + { + .name = "uboot_env", + .offset = 0x40000, + .size = 0x40000, /* 2 sectors for redundant env. */ + }, + { + .name = "linux", + .offset = 0x80000, + .size = 0xF80000, /* map only 16 MiB */ + }, +}; + +struct physmap_flash_data easy98000_nor_flash_data = { + .nr_parts = ARRAY_SIZE(easy98000_nor_partitions), + .parts = easy98000_nor_partitions, +}; + +static struct flash_platform_data easy98000_spi_flash_platform_data = { + .name = "sflash", + .parts = easy98000_nor_partitions, + .nr_parts = ARRAY_SIZE(easy98000_nor_partitions) +}; + +static struct spi_board_info easy98000_spi_flash_data __initdata = { + .modalias = "m25p80", + .bus_num = 0, + .chip_select = 0, + .max_speed_hz = 10 * 1000 * 1000, + .mode = SPI_MODE_3, + .platform_data = &easy98000_spi_flash_platform_data +}; + +/* setup gpio based spi bus/device for access to the eeprom on the board */ +#define SPI_GPIO_MRST 102 +#define SPI_GPIO_MTSR 103 +#define SPI_GPIO_CLK 104 +#define SPI_GPIO_CS0 105 +#define SPI_GPIO_CS1 106 +#define SPI_GPIO_BUS_NUM 1 + +static struct spi_gpio_platform_data easy98000_spi_gpio_data = { + .sck = SPI_GPIO_CLK, + .mosi = SPI_GPIO_MTSR, + .miso = SPI_GPIO_MRST, + .num_chipselect = 2, +}; + +static struct platform_device easy98000_spi_gpio_device = { + .name = "spi_gpio", + .id = SPI_GPIO_BUS_NUM, + .dev.platform_data = &easy98000_spi_gpio_data, +}; + +static struct spi_eeprom at25160n = { + .byte_len = 16 * 1024 / 8, + .name = "at25160n", + .page_size = 32, + .flags = EE_ADDR2, +}; + +static struct spi_board_info easy98000_spi_gpio_devices __initdata = { + .modalias = "at25", + .bus_num = SPI_GPIO_BUS_NUM, + .max_speed_hz = 1000 * 1000, + .mode = SPI_MODE_3, + .chip_select = 1, + .controller_data = (void *) SPI_GPIO_CS1, + .platform_data = &at25160n, +}; + +static void __init +easy98000_init_common(void) +{ + spi_register_board_info(&easy98000_spi_gpio_devices, 1); + platform_device_register(&easy98000_spi_gpio_device); + falcon_register_i2c(); +} + +static void __init +easy98000_init(void) +{ + easy98000_init_common(); + ltq_register_nor(&easy98000_nor_flash_data); +} + +static void __init +easy98000sf_init(void) +{ + easy98000_init_common(); + falcon_register_spi_flash(&easy98000_spi_flash_data); +} + +static void __init +easy98000nand_init(void) +{ + easy98000_init_common(); + falcon_register_nand(); +} + +MIPS_MACHINE(LANTIQ_MACH_EASY98000, + "EASY98000", + "EASY98000 Eval Board", + easy98000_init); + +MIPS_MACHINE(LANTIQ_MACH_EASY98000SF, + "EASY98000SF", + "EASY98000 Eval Board (Serial Flash)", + easy98000sf_init); + +MIPS_MACHINE(LANTIQ_MACH_EASY98000NAND, + "EASY98000NAND", + "EASY98000 Eval Board (NAND Flash)", + easy98000nand_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/prom.c b/target/linux/lantiq/files/arch/mips/lantiq/falcon/prom.c new file mode 100644 index 0000000000..2a4eea1782 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/falcon/prom.c @@ -0,0 +1,84 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#include + +#include "devices.h" + +#include "../prom.h" + +#define SOC_FALCON "Falcon" +#define SOC_FALCON_D "Falcon-D" +#define SOC_FALCON_V "Falcon-V" +#define SOC_FALCON_M "Falcon-M" + +#define PART_SHIFT 12 +#define PART_MASK 0x0FFFF000 +#define REV_SHIFT 28 +#define REV_MASK 0xF0000000 +#define SREV_SHIFT 22 +#define SREV_MASK 0x03C00000 +#define TYPE_SHIFT 26 +#define TYPE_MASK 0x3C000000 + +/* this parameter allows us enable/disable asc1 via commandline */ +static int register_asc1; +static int __init +ltq_parse_asc1(char *p) +{ + register_asc1 = 1; + return 0; +} +__setup("use_asc1", ltq_parse_asc1); + +void __init +ltq_soc_setup(void) +{ + ltq_register_asc(0); + ltq_register_wdt(); + falcon_register_gpio(); + if (register_asc1) + ltq_register_asc(1); +} + +void __init +ltq_soc_detect(struct ltq_soc_info *i) +{ + u32 type; + i->partnum = (ltq_r32(LTQ_FALCON_CHIPID) & PART_MASK) >> PART_SHIFT; + i->rev = (ltq_r32(LTQ_FALCON_CHIPID) & REV_MASK) >> REV_SHIFT; + i->srev = ((ltq_r32(LTQ_FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT); + sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'), + i->rev & 0x7, (i->srev & 0x3) + 1); + + switch (i->partnum) { + case SOC_ID_FALCON: + type = (ltq_r32(LTQ_FALCON_CHIPTYPE) & TYPE_MASK) >> TYPE_SHIFT; + switch (type) { + case 0: + i->name = SOC_FALCON_D; + break; + case 1: + i->name = SOC_FALCON_V; + break; + case 2: + i->name = SOC_FALCON_M; + break; + default: + i->name = SOC_FALCON; + break; + } + i->type = SOC_TYPE_FALCON; + break; + + default: + unreachable(); + break; + } +} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/reset.c b/target/linux/lantiq/files/arch/mips/lantiq/falcon/reset.c new file mode 100644 index 0000000000..cbcadc5c48 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/falcon/reset.c @@ -0,0 +1,87 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include +#include +#include + +#include + +/* CPU0 Reset Source Register */ +#define LTQ_SYS1_CPU0RS 0x0040 +/* reset cause mask */ +#define LTQ_CPU0RS_MASK 0x0003 + +int +ltq_reset_cause(void) +{ + return ltq_sys1_r32(LTQ_SYS1_CPU0RS) & LTQ_CPU0RS_MASK; +} +EXPORT_SYMBOL_GPL(ltq_reset_cause); + +#define BOOT_REG_BASE (KSEG1 | 0x1F200000) +#define BOOT_PW1_REG (BOOT_REG_BASE | 0x20) +#define BOOT_PW2_REG (BOOT_REG_BASE | 0x24) +#define BOOT_PW1 0x4C545100 +#define BOOT_PW2 0x0051544C + +#define WDT_REG_BASE (KSEG1 | 0x1F8803F0) +#define WDT_PW1 0x00BE0000 +#define WDT_PW2 0x00DC0000 + +static void +ltq_machine_restart(char *command) +{ + pr_notice("System restart\n"); + local_irq_disable(); + + /* reboot magic */ + ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */ + ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */ + ltq_w32(0, (void *)BOOT_REG_BASE); /* reset Bootreg RVEC */ + + /* watchdog magic */ + ltq_w32(WDT_PW1, (void *)WDT_REG_BASE); + ltq_w32(WDT_PW2 | + (0x3 << 26) | /* PWL */ + (0x2 << 24) | /* CLKDIV */ + (0x1 << 31) | /* enable */ + (1), /* reload */ + (void *)WDT_REG_BASE); + unreachable(); +} + +static void +ltq_machine_halt(void) +{ + pr_notice("System halted.\n"); + local_irq_disable(); + unreachable(); +} + +static void +ltq_machine_power_off(void) +{ + pr_notice("Please turn off the power now.\n"); + local_irq_disable(); + unreachable(); +} + +static int __init +mips_reboot_setup(void) +{ + _machine_restart = ltq_machine_restart; + _machine_halt = ltq_machine_halt; + pm_power_off = ltq_machine_power_off; + return 0; +} + +arch_initcall(mips_reboot_setup); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/falcon/sysctrl.c b/target/linux/lantiq/files/arch/mips/lantiq/falcon/sysctrl.c new file mode 100644 index 0000000000..f27d694826 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/falcon/sysctrl.c @@ -0,0 +1,211 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 Thomas Langer + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include +#include + +#include + +#include "devices.h" +#include "../clk.h" + +/* infrastructure control register */ +#define SYS1_INFRAC 0x00bc +/* Configuration fuses for drivers and pll */ +#define STATUS_CONFIG 0x0040 + +/* GPE frequency selection */ +#define GPPC_OFFSET 24 +#define GPEFREQ_MASK 0x00000C0 +#define GPEFREQ_OFFSET 10 +/* Clock status register */ +#define LTQ_SYSCTL_CLKS 0x0000 +/* Clock enable register */ +#define LTQ_SYSCTL_CLKEN 0x0004 +/* Clock clear register */ +#define LTQ_SYSCTL_CLKCLR 0x0008 +/* Activation Status Register */ +#define LTQ_SYSCTL_ACTS 0x0020 +/* Activation Register */ +#define LTQ_SYSCTL_ACT 0x0024 +/* Deactivation Register */ +#define LTQ_SYSCTL_DEACT 0x0028 +/* reboot Register */ +#define LTQ_SYSCTL_RBT 0x002c +/* CPU0 Clock Control Register */ +#define LTQ_SYS1_CPU0CC 0x0040 +/* clock divider bit */ +#define LTQ_CPU0CC_CPUDIV 0x0001 + +static struct resource ltq_sysctl_res[] = { + MEM_RES("sys1", LTQ_SYS1_BASE_ADDR, LTQ_SYS1_SIZE), + MEM_RES("syseth", LTQ_SYS_ETH_BASE_ADDR, LTQ_SYS_ETH_SIZE), + MEM_RES("sysgpe", LTQ_SYS_GPE_BASE_ADDR, LTQ_SYS_GPE_SIZE), +}; + +static struct resource ltq_status_res = + MEM_RES("status", LTQ_STATUS_BASE_ADDR, LTQ_STATUS_SIZE); +static struct resource ltq_ebu_res = + MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE); + +static void __iomem *ltq_sysctl[3]; +static void __iomem *ltq_status_membase; +void __iomem *ltq_sys1_membase; +void __iomem *ltq_ebu_membase; + +#define ltq_reg_w32(m, x, y) ltq_w32((x), ltq_sysctl[m] + (y)) +#define ltq_reg_r32(m, x) ltq_r32(ltq_sysctl[m] + (x)) +#define ltq_reg_w32_mask(m, clear, set, reg) \ + ltq_reg_w32(m, (ltq_reg_r32(m, reg) & ~(clear)) | (set), reg) + +#define ltq_status_w32(x, y) ltq_w32((x), ltq_status_membase + (y)) +#define ltq_status_r32(x) ltq_r32(ltq_status_membase + (x)) + +static inline void +ltq_sysctl_wait(struct clk *clk, + unsigned int test, unsigned int reg) +{ + int err = 1000000; + + do {} while (--err && ((ltq_reg_r32(clk->module, reg) + & clk->bits) != test)); + if (!err) + pr_err("module de/activation failed %d %08X %08X %08X\n", + clk->module, clk->bits, test, + ltq_reg_r32(clk->module, reg) & clk->bits); +} + +static int +ltq_sysctl_activate(struct clk *clk) +{ + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKEN); + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_ACT); + ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_ACTS); + return 0; +} + +static void +ltq_sysctl_deactivate(struct clk *clk) +{ + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKCLR); + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_DEACT); + ltq_sysctl_wait(clk, 0, LTQ_SYSCTL_ACTS); +} + +static int +ltq_sysctl_clken(struct clk *clk) +{ + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKEN); + ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_CLKS); + return 0; +} + +static void +ltq_sysctl_clkdis(struct clk *clk) +{ + ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKCLR); + ltq_sysctl_wait(clk, 0, LTQ_SYSCTL_CLKS); +} + +static void +ltq_sysctl_reboot(struct clk *clk) +{ + unsigned int act; + unsigned int bits; + + act = ltq_reg_r32(clk->module, LTQ_SYSCTL_ACT); + bits = ~act & clk->bits; + if (bits != 0) { + ltq_reg_w32(clk->module, bits, LTQ_SYSCTL_CLKEN); + ltq_reg_w32(clk->module, bits, LTQ_SYSCTL_ACT); + ltq_sysctl_wait(clk, bits, LTQ_SYSCTL_ACTS); + } + ltq_reg_w32(clk->module, act & clk->bits, LTQ_SYSCTL_RBT); + ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_ACTS); +} + +/* enable the ONU core */ +static void +ltq_gpe_enable(void) +{ + unsigned int freq; + unsigned int status; + + /* if if the clock is already enabled */ + status = ltq_reg_r32(SYSCTL_SYS1, SYS1_INFRAC); + if (status & (1 << (GPPC_OFFSET + 1))) + return; + + if (ltq_status_r32(STATUS_CONFIG) == 0) + freq = 1; /* use 625MHz on unfused chip */ + else + freq = (ltq_status_r32(STATUS_CONFIG) & + GPEFREQ_MASK) >> + GPEFREQ_OFFSET; + + /* apply new frequency */ + ltq_reg_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1), + freq << (GPPC_OFFSET + 2) , SYS1_INFRAC); + udelay(1); + + /* enable new frequency */ + ltq_reg_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC); + udelay(1); +} + +static inline void +clkdev_add_sys(const char *dev, unsigned int module, + unsigned int bits) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + + clk->cl.dev_id = dev; + clk->cl.con_id = NULL; + clk->cl.clk = clk; + clk->module = module; + clk->bits = bits; + clk->activate = ltq_sysctl_activate; + clk->deactivate = ltq_sysctl_deactivate; + clk->enable = ltq_sysctl_clken; + clk->disable = ltq_sysctl_clkdis; + clk->reboot = ltq_sysctl_reboot; + clkdev_add(&clk->cl); +} + +void __init +ltq_soc_init(void) +{ + int i; + + for (i = 0; i < 3; i++) + ltq_sysctl[i] = ltq_remap_resource(<q_sysctl_res[i]); + + ltq_sys1_membase = ltq_sysctl[0]; + ltq_status_membase = ltq_remap_resource(<q_status_res); + ltq_ebu_membase = ltq_remap_resource(<q_ebu_res); + + ltq_gpe_enable(); + + /* get our 3 static rates for cpu, fpi and io clocks */ + if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV) + clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M); + else + clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M); + + /* add our clock domains */ + clkdev_add_sys("falcon_gpio.0", SYSCTL_SYSETH, ACTS_PADCTRL0 | ACTS_P0); + clkdev_add_sys("falcon_gpio.1", SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1); + clkdev_add_sys("falcon_gpio.2", SYSCTL_SYSETH, ACTS_PADCTRL2 | ACTS_P2); + clkdev_add_sys("falcon_gpio.3", SYSCTL_SYS1, ACTS_PADCTRL3 | ACTS_P3); + clkdev_add_sys("falcon_gpio.4", SYSCTL_SYS1, ACTS_PADCTRL4 | ACTS_P4); + clkdev_add_sys("ltq_asc.1", SYSCTL_SYS1, ACTS_ASC1_ACT); + clkdev_add_sys("i2c-falcon.0", SYSCTL_SYS1, ACTS_I2C_ACT); +} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/Kconfig b/target/linux/lantiq/files/arch/mips/lantiq/svip/Kconfig new file mode 100644 index 0000000000..f351a189a7 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/svip/Kconfig @@ -0,0 +1,16 @@ +if SOC_SVIP + +menu "Mips Machine" + +config LANTIQ_MACH_EASY33016 + bool "Easy33016" + default y + +config LANTIQ_MACH_EASY336 + select SYS_SUPPORTS_LITTLE_ENDIAN + bool "Easy336" + default y + +endmenu + +endif diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/Makefile b/target/linux/lantiq/files/arch/mips/lantiq/svip/Makefile new file mode 100644 index 0000000000..405d652191 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/svip/Makefile @@ -0,0 +1,3 @@ +obj-y := devices.o prom.o reset.o clk-svip.o gpio.o dma.o switchip_setup.o pms.o mux.o +obj-$(CONFIG_LANTIQ_MACH_EASY33016) += mach-easy33016.o +obj-$(CONFIG_LANTIQ_MACH_EASY336) += mach-easy336.o diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/clk-svip.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/clk-svip.c new file mode 100644 index 0000000000..4a14df509f --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/svip/clk-svip.c @@ -0,0 +1,100 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include + +static struct svip_reg_status *const status = +(struct svip_reg_status *)LTQ_STATUS_BASE; +static struct svip_reg_sys0 *const sys0 = (struct svip_reg_sys0 *)LTQ_SYS0_BASE; +static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; + +unsigned int ltq_svip_io_region_clock(void) +{ + return 200000000; /* 200 MHz */ +} +EXPORT_SYMBOL(ltq_svip_io_region_clock); + +unsigned int ltq_svip_cpu_hz(void) +{ + /* Magic BootROM speed location... */ + if ((*(u32 *)0x9fc07ff0) == 1) + return *(u32 *)0x9fc07ff4; + + if (STATUS_CONFIG_CLK_MODE_GET(status_r32(config)) == 1) { + /* xT16 */ + return 393216000; + } else { + switch (SYS0_PLL1CR_PLLDIV_GET(sys0_r32(pll1cr))) { + case 3: + return 475000000; + case 2: + return 450000000; + case 1: + return 425000000; + default: + return 400000000; + } + } +} +EXPORT_SYMBOL(ltq_svip_cpu_hz); + +unsigned int ltq_svip_fpi_hz(void) +{ + u32 fbs0_div[2] = {4, 8}; + u32 div; + + div = SYS1_FPICR_FPIDIV_GET(sys1_r32(fpicr)); + return ltq_svip_cpu_hz()/fbs0_div[div]; +} +EXPORT_SYMBOL(ltq_svip_fpi_hz); + +unsigned int ltq_get_ppl_hz(void) +{ + /* Magic BootROM speed location... */ + if ((*(u32 *)0x9fc07ff0) == 1) + return *(u32 *)0x9fc07ff4; + + if (STATUS_CONFIG_CLK_MODE_GET(status_r32(config)) == 1) { + /* xT16 */ + return 393216000; + } else { + switch (SYS0_PLL1CR_PLLDIV_GET(sys0_r32(pll1cr))) { + case 3: + return 475000000; + case 2: + return 450000000; + case 1: + return 425000000; + default: + return 400000000; + } + } +} + +unsigned int ltq_get_fbs0_hz(void) +{ + u32 fbs0_div[2] = {4, 8}; + u32 div; + + div = SYS1_FPICR_FPIDIV_GET(sys1_r32(fpicr)); + return ltq_get_ppl_hz()/fbs0_div[div]; +} +EXPORT_SYMBOL(ltq_get_fbs0_hz); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/devices.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/devices.c new file mode 100644 index 0000000000..f1471169e5 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/svip/devices.c @@ -0,0 +1,385 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include +#include +#include + +#include "devices.h" + +#include +#include +#include + +/* ASC */ +void __init svip_register_asc(int port) +{ + switch (port) { + case 0: + ltq_register_asc(0); + svip_sys1_clk_enable(SYS1_CLKENR_ASC0); + break; + case 1: + ltq_register_asc(1); + svip_sys1_clk_enable(SYS1_CLKENR_ASC1); + break; + default: + break; + }; +} + +/* Ethernet */ +static unsigned char svip_ethaddr[6] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; + +static struct platform_device ltq_mii = { + .name = "ifxmips_mii0", + .dev = { + .platform_data = svip_ethaddr, + }, +}; + +static int __init svip_set_ethaddr(char *str) +{ + sscanf(str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", + &svip_ethaddr[0], &svip_ethaddr[1], &svip_ethaddr[2], + &svip_ethaddr[3], &svip_ethaddr[4], &svip_ethaddr[5]); + return 0; +} +__setup("ethaddr=", svip_set_ethaddr); + +void __init svip_register_eth(void) +{ + if (!is_valid_ether_addr(svip_ethaddr)) + random_ether_addr(svip_ethaddr); + + platform_device_register(<q_mii); + svip_sys1_clk_enable(SYS1_CLKENR_ETHSW); +} + +/* Virtual Ethernet */ +static struct platform_device ltq_ve = { + .name = "ifxmips_svip_ve", +}; + +void __init svip_register_virtual_eth(void) +{ + platform_device_register(<q_ve); +} + +/* SPI */ +static void __init ltq_register_ssc(int bus_num, unsigned long base, int irq_rx, + int irq_tx, int irq_err, int irq_frm) +{ + struct resource res[] = { + { + .name = "regs", + .start = base, + .end = base + 0x20 - 1, + .flags = IORESOURCE_MEM, + }, { + .name = "rx", + .start = irq_rx, + .flags = IORESOURCE_IRQ, + }, { + .name = "tx", + .start = irq_tx, + .flags = IORESOURCE_IRQ, + }, { + .name = "err", + .start = irq_err, + .flags = IORESOURCE_IRQ, + }, { + .name = "frm", + .start = irq_frm, + .flags = IORESOURCE_IRQ, + }, + }; + + platform_device_register_simple("ifx_ssc", bus_num, res, + ARRAY_SIZE(res)); +} + +static struct spi_board_info bdinfo[] __initdata = { + { + .modalias = "xt16", + .mode = SPI_MODE_3, + .irq = INT_NUM_IM5_IRL0 + 28, + .max_speed_hz = 1000000, + .bus_num = 0, + .chip_select = 1, + }, + { + .modalias = "xt16", + .mode = SPI_MODE_3, + .irq = INT_NUM_IM5_IRL0 + 19, + .max_speed_hz = 1000000, + .bus_num = 0, + .chip_select = 2, + }, + { + .modalias = "loop", + .mode = SPI_MODE_0 | SPI_LOOP, + .irq = -1, + .max_speed_hz = 10000000, + .bus_num = 0, + .chip_select = 3, + }, +}; + +void __init svip_register_spi(void) +{ + + ltq_register_ssc(0, LTQ_SSC0_BASE, INT_NUM_IM1_IRL0 + 6, + INT_NUM_IM1_IRL0 + 7, INT_NUM_IM1_IRL0 + 8, + INT_NUM_IM1_IRL0 + 9); + + ltq_register_ssc(1, LTQ_SSC1_BASE, INT_NUM_IM1_IRL0 + 10, + INT_NUM_IM1_IRL0 + 11, INT_NUM_IM1_IRL0 + 12, + INT_NUM_IM1_IRL0 + 13); + + spi_register_board_info(bdinfo, ARRAY_SIZE(bdinfo)); + + svip_sys1_clk_enable(SYS1_CLKENR_SSC0 | SYS1_CLKENR_SSC1); +} + +void __init svip_register_spi_flash(struct spi_board_info *bdinfo) +{ + spi_register_board_info(bdinfo, 1); +} + +/* GPIO */ +static struct platform_device ltq_gpio = { + .name = "ifxmips_gpio", +}; + +static struct platform_device ltq_gpiodev = { + .name = "GPIODEV", +}; + +void __init svip_register_gpio(void) +{ + platform_device_register(<q_gpio); + platform_device_register(<q_gpiodev); +} + +/* MUX */ +static struct ltq_mux_settings ltq_mux_settings; + +static struct platform_device ltq_mux = { + .name = "ltq_mux", + .dev = { + .platform_data = <q_mux_settings, + } +}; + +void __init svip_register_mux(const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS], + const struct ltq_mux_pin mux_p1[LTQ_MUX_P1_PINS], + const struct ltq_mux_pin mux_p2[LTQ_MUX_P2_PINS], + const struct ltq_mux_pin mux_p3[LTQ_MUX_P3_PINS], + const struct ltq_mux_pin mux_p4[LTQ_MUX_P4_PINS]) +{ + ltq_mux_settings.mux_p0 = mux_p0; + ltq_mux_settings.mux_p1 = mux_p1; + ltq_mux_settings.mux_p2 = mux_p2; + ltq_mux_settings.mux_p3 = mux_p3; + ltq_mux_settings.mux_p4 = mux_p4; + + if (mux_p0) + svip_sys1_clk_enable(SYS1_CLKENR_PORT0); + + if (mux_p1) + svip_sys1_clk_enable(SYS1_CLKENR_PORT1); + + if (mux_p2) + svip_sys1_clk_enable(SYS1_CLKENR_PORT2); + + if (mux_p3) + svip_sys1_clk_enable(SYS1_CLKENR_PORT3); + + if (mux_p4) + svip_sys2_clk_enable(SYS2_CLKENR_PORT4); + + platform_device_register(<q_mux); +} + +/* NAND */ +#define NAND_ADDR_REGION_BASE (LTQ_EBU_SEG1_BASE) +#define NAND_CLE_BIT (1 << 3) +#define NAND_ALE_BIT (1 << 2) + +static struct svip_reg_ebu *const ebu = (struct svip_reg_ebu *)LTQ_EBU_BASE; + +static int svip_nand_probe(struct platform_device *pdev) +{ + ebu_w32(LTQ_EBU_ADDR_SEL_0_BASE_VAL(CPHYSADDR(NAND_ADDR_REGION_BASE) + >> 12) + | LTQ_EBU_ADDR_SEL_0_MASK_VAL(15) + | LTQ_EBU_ADDR_SEL_0_MRME_VAL(0) + | LTQ_EBU_ADDR_SEL_0_REGEN_VAL(1), + addr_sel_0); + + ebu_w32(LTQ_EBU_CON_0_WRDIS_VAL(0) + | LTQ_EBU_CON_0_ADSWP_VAL(1) + | LTQ_EBU_CON_0_AGEN_VAL(0x00) + | LTQ_EBU_CON_0_SETUP_VAL(1) + | LTQ_EBU_CON_0_WAIT_VAL(0x00) + | LTQ_EBU_CON_0_WINV_VAL(0) + | LTQ_EBU_CON_0_PW_VAL(0x00) + | LTQ_EBU_CON_0_ALEC_VAL(0) + | LTQ_EBU_CON_0_BCGEN_VAL(0x01) + | LTQ_EBU_CON_0_WAITWRC_VAL(1) + | LTQ_EBU_CON_0_WAITRDC_VAL(1) + | LTQ_EBU_CON_0_HOLDC_VAL(1) + | LTQ_EBU_CON_0_RECOVC_VAL(0) + | LTQ_EBU_CON_0_CMULT_VAL(0x01), + con_0); + + /* + * ECC disabled + * CLE, ALE and CS are pulse, all other signal are latches based + * CLE and ALE are active high, PRE, WP, SE and CS/CE are active low + * OUT_CS_S is disabled + * NAND mode is disabled + */ + ebu_w32(LTQ_EBU_NAND_CON_ECC_ON_VAL(0) + | LTQ_EBU_NAND_CON_LAT_EN_VAL(0x38) + | LTQ_EBU_NAND_CON_OUT_CS_S_VAL(0) + | LTQ_EBU_NAND_CON_IN_CS_S_VAL(0) + | LTQ_EBU_NAND_CON_PRE_P_VAL(1) + | LTQ_EBU_NAND_CON_WP_P_VAL(1) + | LTQ_EBU_NAND_CON_SE_P_VAL(1) + | LTQ_EBU_NAND_CON_CS_P_VAL(1) + | LTQ_EBU_NAND_CON_CLE_P_VAL(0) + | LTQ_EBU_NAND_CON_ALE_P_VAL(0) + | LTQ_EBU_NAND_CON_CSMUX_E_VAL(0) + | LTQ_EBU_NAND_CON_NANDMODE_VAL(0), + nand_con); + + return 0; +} + +static void svip_nand_hwcontrol(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + unsigned long adr; + /* Coming here means to change either the enable state or + * the address for controlling ALE or CLE */ + + /* NAND_NCE: Select the chip by setting nCE to low. + * This is done in CON register */ + if (ctrl & NAND_NCE) + ebu_w32_mask(0, LTQ_EBU_NAND_CON_NANDMODE_VAL(1), + nand_con); + else + ebu_w32_mask(LTQ_EBU_NAND_CON_NANDMODE_VAL(1), + 0, nand_con); + + /* The addressing of CLE or ALE is done via different addresses. + We are now changing the address depending on the given action + SVIPs NAND_CLE_BIT = (1 << 3), NAND_CLE = 0x02 + NAND_ALE_BIT = (1 << 2) = NAND_ALE (0x04) */ + adr = (unsigned long)this->IO_ADDR_W; + adr &= ~(NAND_CLE_BIT | NAND_ALE_BIT); + adr |= (ctrl & NAND_CLE) << 2 | (ctrl & NAND_ALE); + this->IO_ADDR_W = (void __iomem *)adr; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +static int svip_nand_ready(struct mtd_info *mtd) +{ + return (ebu_r32(nand_wait) & 0x01) == 0x01; +} + +static inline void svip_nand_wait(void) +{ + static const int nops = 150; + int i; + + for (i = 0; i < nops; i++) + asm("nop"); +} + +static void svip_nand_write_buf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + + for (i = 0; i < len; i++) { + writeb(buf[i], this->IO_ADDR_W); + svip_nand_wait(); + } +} + +static void svip_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + + for (i = 0; i < len; i++) { + buf[i] = readb(this->IO_ADDR_R); + svip_nand_wait(); + } +} + +static const char *part_probes[] = { "cmdlinepart", NULL }; + +static struct platform_nand_data svip_flash_nand_data = { + .chip = { + .nr_chips = 1, + .part_probe_types = part_probes, + }, + .ctrl = { + .probe = svip_nand_probe, + .cmd_ctrl = svip_nand_hwcontrol, + .dev_ready = svip_nand_ready, + .write_buf = svip_nand_write_buf, + .read_buf = svip_nand_read_buf, + } +}; + +static struct resource svip_nand_resources[] = { + MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX), +}; + +static struct platform_device svip_flash_nand = { + .name = "gen_nand", + .id = -1, + .num_resources = ARRAY_SIZE(svip_nand_resources), + .resource = svip_nand_resources, + .dev = { + .platform_data = &svip_flash_nand_data, + }, +}; + +void __init svip_register_nand(void) +{ + platform_device_register(&svip_flash_nand); +} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/devices.h b/target/linux/lantiq/files/arch/mips/lantiq/svip/devices.h new file mode 100644 index 0000000000..a064e67ec1 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/svip/devices.h @@ -0,0 +1,23 @@ +#ifndef _SVIP_DEVICES_H__ +#define _SVIP_DEVICES_H__ + +#include +#include +#include +#include +#include "../devices.h" + +extern void __init svip_register_asc(int port); +extern void __init svip_register_eth(void); +extern void __init svip_register_virtual_eth(void); +extern void __init svip_register_spi(void); +extern void __init svip_register_spi_flash(struct spi_board_info *bdinfo); +extern void __init svip_register_gpio(void); +extern void __init svip_register_mux(const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS], + const struct ltq_mux_pin mux_p1[LTQ_MUX_P1_PINS], + const struct ltq_mux_pin mux_p2[LTQ_MUX_P2_PINS], + const struct ltq_mux_pin mux_p3[LTQ_MUX_P3_PINS], + const struct ltq_mux_pin mux_p4[LTQ_MUX_P4_PINS]); +extern void __init svip_register_nand(void); + +#endif diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/dma.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/dma.c new file mode 100644 index 0000000000..7464be1bd5 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/svip/dma.c @@ -0,0 +1,1206 @@ +/* + ** Copyright (C) 2005 Wu Qi Ming + ** + ** This program is free software; you can redistribute it and/or modify + ** it under the terms of the GNU General Public License as published by + ** the Free Software Foundation; either version 2 of the License, or + ** (at your option) any later version. + ** + ** This program is distributed in the hope that it will be useful, + ** but WITHOUT ANY WARRANTY; without even the implied warranty of + ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + ** GNU General Public License for more details. + ** + ** You should have received a copy of the GNU General Public License + ** along with this program; if not, write to the Free Software + ** Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +/* + * Description: + * Driver for SVIP DMA + * Author: Wu Qi Ming[Qi-Ming.Wu@infineon.com] + * Created: 26-September-2005 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; +static struct svip_reg_dma *const dma = (struct svip_reg_dma *)LTQ_DMA_BASE; +static struct svip_reg_mbs *const mbs = (struct svip_reg_mbs *)LTQ_MBS_BASE; + +#define DRV_NAME "ltq_dma" +extern void ltq_mask_and_ack_irq(struct irq_data *data); +extern void ltq_enable_irq(struct irq_data *data); + +static inline void mask_and_ack_irq(unsigned int irq_nr) +{ + static int i = 0; + struct irq_data data; + data.irq = irq_nr; + if ((i < 2) && (irq_nr == 137)) { + printk("eth delay hack\n"); + i++; + } + ltq_mask_and_ack_irq(&data); +} + +static inline void svip_enable_irq(unsigned int irq_nr) +{ + struct irq_data data; + data.irq = irq_nr; + ltq_enable_irq(&data); +} + +#define DMA_EMSG(fmt, args...) \ + printk(KERN_ERR "%s: " fmt, __func__, ## args) + +static inline void mbs_grab(void) +{ + while (mbs_r32(mbsr0) != 0); +} + +static inline void mbs_release(void) +{ + mbs_w32(0, mbsr0); + asm("sync"); +} + +/* max ports connecting to dma */ +#define LTQ_MAX_DMA_DEVICE_NUM ARRAY_SIZE(dma_devices) +/* max dma channels */ +#define LTQ_MAX_DMA_CHANNEL_NUM ARRAY_SIZE(dma_chan) + +/* bytes per descriptor */ +#define DMA_DESCR_SIZE 8 + +#define DMA_DESCR_CH_SIZE (DMA_DESCR_NUM * DMA_DESCR_SIZE) +#define DMA_DESCR_TOTAL_SIZE (LTQ_MAX_DMA_CHANNEL_NUM * DMA_DESCR_CH_SIZE) +#define DMA_DESCR_MEM_PAGES ((DMA_DESCR_TOTAL_SIZE / PAGE_SIZE) + \ + (((DMA_DESCR_TOTAL_SIZE % PAGE_SIZE) > 0))) + +/* budget for interrupt handling */ +#define DMA_INT_BUDGET 100 +/* set the correct counter value here! */ +#define DMA_POLL_COUNTER 32 + +struct proc_dir_entry *g_dma_dir; + +/* device_name | max_rx_chan_num | max_tx_chan_num | drop_enable */ +struct dma_device_info dma_devices[] = { + { "SW", 4, 4, 0 }, + { "DEU", 1, 1, 0 }, + { "SSC0", 1, 1, 0 }, + { "SSC1", 1, 1, 0 }, + { "MCTRL", 1, 1, 0 }, + { "PCM0", 1, 1, 0 }, + { "PCM1", 1, 1, 0 }, + { "PCM2", 1, 1, 0 }, + { "PCM3", 1, 1, 0 } +}; + +/* *dma_dev | dir | pri | irq | rel_chan_no */ +struct dma_channel_info dma_chan[] = { + { &dma_devices[0], DIR_RX, 0, INT_NUM_IM4_IRL0 + 0, 0 }, + { &dma_devices[0], DIR_TX, 0, INT_NUM_IM4_IRL0 + 1, 0 }, + { &dma_devices[0], DIR_RX, 1, INT_NUM_IM4_IRL0 + 2, 1 }, + { &dma_devices[0], DIR_TX, 1, INT_NUM_IM4_IRL0 + 3, 1 }, + { &dma_devices[0], DIR_RX, 2, INT_NUM_IM4_IRL0 + 4, 2 }, + { &dma_devices[0], DIR_TX, 2, INT_NUM_IM4_IRL0 + 5, 2 }, + { &dma_devices[0], DIR_RX, 3, INT_NUM_IM4_IRL0 + 6, 3 }, + { &dma_devices[0], DIR_TX, 3, INT_NUM_IM4_IRL0 + 7, 3 }, + { &dma_devices[1], DIR_RX, 0, INT_NUM_IM4_IRL0 + 8, 0 }, + { &dma_devices[1], DIR_TX, 0, INT_NUM_IM4_IRL0 + 9, 0 }, + { &dma_devices[2], DIR_RX, 0, INT_NUM_IM4_IRL0 + 10, 0 }, + { &dma_devices[2], DIR_TX, 0, INT_NUM_IM4_IRL0 + 11, 0 }, + { &dma_devices[3], DIR_RX, 0, INT_NUM_IM4_IRL0 + 12, 0 }, + { &dma_devices[3], DIR_TX, 0, INT_NUM_IM4_IRL0 + 13, 0 }, + { &dma_devices[4], DIR_RX, 0, INT_NUM_IM4_IRL0 + 14, 0 }, + { &dma_devices[4], DIR_TX, 0, INT_NUM_IM4_IRL0 + 15, 0 }, + { &dma_devices[5], DIR_RX, 0, INT_NUM_IM4_IRL0 + 16, 0 }, + { &dma_devices[5], DIR_TX, 0, INT_NUM_IM4_IRL0 + 17, 0 }, + { &dma_devices[6], DIR_RX, 1, INT_NUM_IM3_IRL0 + 18, 0 }, + { &dma_devices[6], DIR_TX, 1, INT_NUM_IM3_IRL0 + 19, 0 }, + { &dma_devices[7], DIR_RX, 2, INT_NUM_IM4_IRL0 + 20, 0 }, + { &dma_devices[7], DIR_TX, 2, INT_NUM_IM4_IRL0 + 21, 0 }, + { &dma_devices[8], DIR_RX, 3, INT_NUM_IM4_IRL0 + 22, 0 }, + { &dma_devices[8], DIR_TX, 3, INT_NUM_IM4_IRL0 + 23, 0 } +}; + +u64 *g_desc_list[DMA_DESCR_MEM_PAGES]; + +volatile u32 g_dma_int_status = 0; + +/* 0 - not in process, 1 - in process */ +volatile int g_dma_in_process; + +int ltq_dma_init(void); +void do_dma_tasklet(unsigned long); +DECLARE_TASKLET(dma_tasklet, do_dma_tasklet, 0); +irqreturn_t dma_interrupt(int irq, void *dev_id); + +u8 *common_buffer_alloc(int len, int *byte_offset, void **opt) +{ + u8 *buffer = kmalloc(len * sizeof(u8), GFP_KERNEL); + *byte_offset = 0; + return buffer; +} + +void common_buffer_free(u8 *dataptr, void *opt) +{ + kfree(dataptr); +} + +void enable_ch_irq(struct dma_channel_info *ch) +{ + int chan_no = (int)(ch - dma_chan); + unsigned long flag; + u32 val; + + if (ch->dir == DIR_RX) + val = DMA_CIE_DESCPT | DMA_CIE_DUR; + else + val = DMA_CIE_DESCPT; + + local_irq_save(flag); + mbs_grab(); + dma_w32(chan_no, cs); + dma_w32(val, cie); + dma_w32_mask(0, 1 << chan_no, irnen); + mbs_release(); + local_irq_restore(flag); + + svip_enable_irq(ch->irq); +} + +void disable_ch_irq(struct dma_channel_info *ch) +{ + unsigned long flag; + int chan_no = (int)(ch - dma_chan); + + local_irq_save(flag); + g_dma_int_status &= ~(1 << chan_no); + mbs_grab(); + dma_w32(chan_no, cs); + dma_w32(0, cie); + mbs_release(); + dma_w32_mask(1 << chan_no, 0, irnen); + local_irq_restore(flag); + + mask_and_ack_irq(ch->irq); +} + +int open_chan(struct dma_channel_info *ch) +{ + unsigned long flag; + int j; + int chan_no = (int)(ch - dma_chan); + u8 *buffer; + int byte_offset; + struct rx_desc *rx_desc_p; + struct tx_desc *tx_desc_p; + + if (ch->control == LTQ_DMA_CH_ON) + return -1; + + if (ch->dir == DIR_RX) { + for (j = 0; j < ch->desc_len; j++) { + rx_desc_p = (struct rx_desc *)ch->desc_base+j; + buffer = ch->dma_dev->buffer_alloc(ch->packet_size, + &byte_offset, + (void *)&ch->opt[j]); + if (!buffer) + return -ENOBUFS; + + rx_desc_p->data_pointer = (u32)CPHYSADDR((u32)buffer); + rx_desc_p->status.word = 0; + rx_desc_p->status.field.byte_offset = byte_offset; + rx_desc_p->status.field.data_length = ch->packet_size; + rx_desc_p->status.field.own = DMA_OWN; + } + } else { + for (j = 0; j < ch->desc_len; j++) { + tx_desc_p = (struct tx_desc *)ch->desc_base + j; + tx_desc_p->data_pointer = 0; + tx_desc_p->status.word = 0; + } + } + ch->xfer_cnt = 0; + + local_irq_save(flag); + mbs_grab(); + dma_w32(chan_no, cs); + dma_w32(ch->desc_len, cdlen); + dma_w32(0x7e, cis); + dma_w32(DMA_CCTRL_TXWGT_VAL(ch->tx_weight) + | DMA_CCTRL_CLASS_VAL(ch->pri) + | (ch->dir == DIR_RX ? DMA_CCTRL_ON_OFF : 0), cctrl); + mbs_release(); + ch->control = LTQ_DMA_CH_ON; + local_irq_restore(flag); + + if (request_irq(ch->irq, dma_interrupt, + IRQF_DISABLED, "dma-core", (void *)ch) != 0) { + printk(KERN_ERR "error, cannot get dma_irq!\n"); + return -EFAULT; + } + + enable_ch_irq(ch); + return 0; +} + +int close_chan(struct dma_channel_info *ch) +{ + unsigned long flag; + int j; + int chan_no = (int)(ch - dma_chan); + struct rx_desc *desc_p; + + if (ch->control == LTQ_DMA_CH_OFF) + return -1; + + local_irq_save(flag); + mbs_grab(); + dma_w32(chan_no, cs); + dma_w32_mask(DMA_CCTRL_ON_OFF, 0, cctrl); + mbs_release(); + disable_ch_irq(ch); + free_irq(ch->irq, (void *)ch); + ch->control = LTQ_DMA_CH_OFF; + local_irq_restore(flag); + + /* free descriptors in use */ + for (j = 0; j < ch->desc_len; j++) { + desc_p = (struct rx_desc *)ch->desc_base+j; + if ((desc_p->status.field.own == CPU_OWN && + desc_p->status.field.c) || + (desc_p->status.field.own == DMA_OWN)) { + if (desc_p->data_pointer) { + ch->dma_dev->buffer_free((u8 *)__va(desc_p->data_pointer), + (void *)ch->opt[j]); + desc_p->data_pointer = (u32)NULL; + } + } + } + + return 0; +} + +int reset_chan(struct dma_channel_info *ch) +{ + unsigned long flag; + int val; + int chan_no = (int)(ch - dma_chan); + + close_chan(ch); + + local_irq_save(flag); + mbs_grab(); + dma_w32(chan_no, cs); + dma_w32_mask(0, DMA_CCTRL_RST, cctrl); + mbs_release(); + local_irq_restore(flag); + + do { + local_irq_save(flag); + mbs_grab(); + dma_w32(chan_no, cs); + val = dma_r32(cctrl); + mbs_release(); + local_irq_restore(flag); + } while (val & DMA_CCTRL_RST); + + return 0; +} + +static inline void rx_chan_intr_handler(int chan_no) +{ + struct dma_device_info *dma_dev = (struct dma_device_info *) + dma_chan[chan_no].dma_dev; + struct dma_channel_info *ch = &dma_chan[chan_no]; + struct rx_desc *rx_desc_p; + unsigned long flag; + u32 val; + + local_irq_save(flag); + mbs_grab(); + dma_w32(chan_no, cs); + val = dma_r32(cis); + dma_w32(DMA_CIS_DESCPT, cis); + mbs_release(); + + /* handle command complete interrupt */ + rx_desc_p = (struct rx_desc *)ch->desc_base + ch->curr_desc; + if ((rx_desc_p->status.word & (DMA_DESC_OWN_DMA | DMA_DESC_CPT_SET)) == + DMA_DESC_CPT_SET) { + local_irq_restore(flag); + /* Every thing is correct, then we inform the upper layer */ + dma_dev->current_rx_chan = ch->rel_chan_no; + if (dma_dev->intr_handler) + dma_dev->intr_handler(dma_dev, RCV_INT); + ch->weight--; + } else { + g_dma_int_status &= ~(1 << chan_no); + local_irq_restore(flag); + svip_enable_irq(dma_chan[chan_no].irq); + } +} + +static inline void tx_chan_intr_handler(int chan_no) +{ + struct dma_device_info *dma_dev = (struct dma_device_info *) + dma_chan[chan_no].dma_dev; + struct dma_channel_info *ch = &dma_chan[chan_no]; + struct tx_desc *tx_desc_p; + unsigned long flag; + + local_irq_save(flag); + mbs_grab(); + dma_w32(chan_no, cs); + dma_w32(DMA_CIS_DESCPT, cis); + mbs_release(); + + tx_desc_p = (struct tx_desc *)ch->desc_base+ch->prev_desc; + if ((tx_desc_p->status.word & (DMA_DESC_OWN_DMA | DMA_DESC_CPT_SET)) == + DMA_DESC_CPT_SET) { + local_irq_restore(flag); + + dma_dev->buffer_free((u8 *)__va(tx_desc_p->data_pointer), + ch->opt[ch->prev_desc]); + memset(tx_desc_p, 0, sizeof(struct tx_desc)); + dma_dev->current_tx_chan = ch->rel_chan_no; + if (dma_dev->intr_handler) + dma_dev->intr_handler(dma_dev, TRANSMIT_CPT_INT); + ch->weight--; + + ch->prev_desc = (ch->prev_desc + 1) % (ch->desc_len); + } else { + g_dma_int_status &= ~(1 << chan_no); + local_irq_restore(flag); + svip_enable_irq(dma_chan[chan_no].irq); + } +} + +void do_dma_tasklet(unsigned long unused) +{ + int i; + int chan_no = 0; + int budget = DMA_INT_BUDGET; + int weight = 0; + unsigned long flag; + + while (g_dma_int_status) { + if (budget-- < 0) { + tasklet_schedule(&dma_tasklet); + return; + } + chan_no = -1; + weight = 0; + /* WFQ algorithm to select the channel */ + for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { + if (g_dma_int_status & (1 << i) && + dma_chan[i].weight > 0) { + if (dma_chan[i].weight > weight) { + chan_no = i; + weight = dma_chan[chan_no].weight; + } + } + } + if (chan_no >= 0) { + if (dma_chan[chan_no].dir == DIR_RX) + rx_chan_intr_handler(chan_no); + else + tx_chan_intr_handler(chan_no); + } else { + /* reset all the channels */ + for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) + dma_chan[i].weight = dma_chan[i].default_weight; + } + } + + local_irq_save(flag); + g_dma_in_process = 0; + if (g_dma_int_status) { + g_dma_in_process = 1; + tasklet_schedule(&dma_tasklet); + } + local_irq_restore(flag); +} + +irqreturn_t dma_interrupt(int irq, void *dev_id) +{ + struct dma_channel_info *ch; + int chan_no = 0; + + ch = (struct dma_channel_info *)dev_id; + chan_no = (int)(ch - dma_chan); + + if ((unsigned)chan_no >= LTQ_MAX_DMA_CHANNEL_NUM) { + printk(KERN_ERR "error: dma_interrupt irq=%d chan_no=%d\n", + irq, chan_no); + } + + g_dma_int_status |= 1 << chan_no; + dma_w32(1 << chan_no, irncr); + mask_and_ack_irq(irq); + + if (!g_dma_in_process) { + g_dma_in_process = 1; + tasklet_schedule(&dma_tasklet); + } + + return IRQ_RETVAL(1); +} + +struct dma_device_info *dma_device_reserve(char *dev_name) +{ + int i; + + ltq_dma_init(); + for (i = 0; i < LTQ_MAX_DMA_DEVICE_NUM; i++) { + if (strcmp(dev_name, dma_devices[i].device_name) == 0) { + if (dma_devices[i].reserved) + return NULL; + dma_devices[i].reserved = 1; + break; + } + } + + if (i == LTQ_MAX_DMA_DEVICE_NUM) + return NULL; + + return &dma_devices[i]; +} +EXPORT_SYMBOL(dma_device_reserve); + +int dma_device_release(struct dma_device_info *dma_dev) +{ + dma_dev->reserved = 0; + + return 0; +} +EXPORT_SYMBOL(dma_device_release); + +int dma_device_register(struct dma_device_info *dma_dev) +{ + int port_no = (int)(dma_dev - dma_devices); + int txbl, rxbl; + unsigned long flag; + + switch (dma_dev->tx_burst_len) { + case 8: + txbl = 3; + break; + case 4: + txbl = 2; + break; + default: + txbl = 1; + break; + } + + switch (dma_dev->rx_burst_len) { + case 8: + rxbl = 3; + break; + case 4: + rxbl = 2; + break; + default: + rxbl = 1; + } + + local_irq_save(flag); + mbs_grab(); + dma_w32(port_no, ps); + dma_w32(DMA_PCTRL_TXWGT_VAL(dma_dev->tx_weight) + | DMA_PCTRL_TXENDI_VAL(dma_dev->tx_endianness_mode) + | DMA_PCTRL_RXENDI_VAL(dma_dev->rx_endianness_mode) + | DMA_PCTRL_PDEN_VAL(dma_dev->drop_enable) + | DMA_PCTRL_TXBL_VAL(txbl) + | DMA_PCTRL_RXBL_VAL(rxbl), pctrl); + mbs_release(); + local_irq_restore(flag); + + return 0; +} +EXPORT_SYMBOL(dma_device_register); + +int dma_device_unregister(struct dma_device_info *dma_dev) +{ + int i; + int port_no = (int)(dma_dev - dma_devices); + unsigned long flag; + + /* flush memcopy module; has no effect for other ports */ + local_irq_save(flag); + mbs_grab(); + dma_w32(port_no, ps); + dma_w32_mask(0, DMA_PCTRL_GPC, pctrl); + mbs_release(); + local_irq_restore(flag); + + for (i = 0; i < dma_dev->max_tx_chan_num; i++) + reset_chan(dma_dev->tx_chan[i]); + + for (i = 0; i < dma_dev->max_rx_chan_num; i++) + reset_chan(dma_dev->rx_chan[i]); + + return 0; +} +EXPORT_SYMBOL(dma_device_unregister); + +/** + * Read Packet from DMA Rx channel. + * The function gets the data from the current rx descriptor assigned + * to the passed DMA device and passes it back to the caller. + * The function is called in the context of DMA interrupt. + * In detail the following actions are done: + * - get current receive descriptor + * - allocate memory via allocation callback function + * - pass data from descriptor to allocated memory + * - update channel weight + * - release descriptor + * - update current descriptor position + * + * \param *dma_dev - pointer to DMA device structure + * \param **dataptr - pointer to received data + * \param **opt + * \return packet length - length of received data + * \ingroup Internal + */ +int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt) +{ + u8 *buf; + int len; + int byte_offset = 0; + void *p = NULL; + + struct dma_channel_info *ch = + dma_dev->rx_chan[dma_dev->current_rx_chan]; + + struct rx_desc *rx_desc_p; + + /* get the rx data first */ + rx_desc_p = (struct rx_desc *)ch->desc_base+ch->curr_desc; + buf = (u8 *)__va(rx_desc_p->data_pointer); + *(u32 *)dataptr = (u32)buf; + len = rx_desc_p->status.field.data_length; +#ifndef CONFIG_MIPS_UNCACHED + dma_cache_inv((unsigned long)buf, len); +#endif + if (opt) + *(int *)opt = (int)ch->opt[ch->curr_desc]; + + /* replace with a new allocated buffer */ + buf = dma_dev->buffer_alloc(ch->packet_size, &byte_offset, &p); + if (buf) { + ch->opt[ch->curr_desc] = p; + + wmb(); + rx_desc_p->data_pointer = (u32)CPHYSADDR((u32)buf); + rx_desc_p->status.word = (DMA_OWN << 31) \ + |(byte_offset << 23) \ + | ch->packet_size; + + wmb(); + } else { + *(u32 *)dataptr = 0; + if (opt) + *(int *)opt = 0; + } + + ch->xfer_cnt++; + /* increase the curr_desc pointer */ + ch->curr_desc++; + if (ch->curr_desc == ch->desc_len) + ch->curr_desc = 0; + /* return the length of the received packet */ + return len; +} +EXPORT_SYMBOL(dma_device_read); + +/** + * Write Packet through DMA Tx channel to peripheral. + * + * \param *dma_dev - pointer to DMA device structure + * \param *dataptr - pointer to data to be sent + * \param len - amount of data bytes to be sent + * \param *opt + * \return len - length of transmitted data + * \ingroup Internal + */ +int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, int len, + void *opt) +{ + unsigned long flag; + u32 byte_offset; + struct dma_channel_info *ch; + int chan_no; + struct tx_desc *tx_desc_p; + local_irq_save(flag); + + ch = dma_dev->tx_chan[dma_dev->current_tx_chan]; + chan_no = (int)(ch - dma_chan); + + if (ch->control == LTQ_DMA_CH_OFF) { + local_irq_restore(flag); + printk(KERN_ERR "%s: dma channel %d not enabled!\n", + __func__, chan_no); + return 0; + } + + tx_desc_p = (struct tx_desc *)ch->desc_base+ch->curr_desc; + /* Check whether this descriptor is available */ + if (tx_desc_p->status.word & (DMA_DESC_OWN_DMA | DMA_DESC_CPT_SET)) { + /* if not , the tell the upper layer device */ + dma_dev->intr_handler(dma_dev, TX_BUF_FULL_INT); + local_irq_restore(flag); + return 0; + } + ch->opt[ch->curr_desc] = opt; + /* byte offset----to adjust the starting address of the data buffer, + * should be multiple of the burst length.*/ + byte_offset = ((u32)CPHYSADDR((u32)dataptr)) % + (dma_dev->tx_burst_len * 4); +#ifndef CONFIG_MIPS_UNCACHED + dma_cache_wback((unsigned long)dataptr, len); + wmb(); +#endif + tx_desc_p->data_pointer = (u32)CPHYSADDR((u32)dataptr) - byte_offset; + wmb(); + tx_desc_p->status.word = (DMA_OWN << 31) + | DMA_DESC_SOP_SET + | DMA_DESC_EOP_SET + | (byte_offset << 23) + | len; + wmb(); + + if (ch->xfer_cnt == 0) { + mbs_grab(); + dma_w32(chan_no, cs); + dma_w32_mask(0, DMA_CCTRL_ON_OFF, cctrl); + mbs_release(); + } + + ch->xfer_cnt++; + ch->curr_desc++; + if (ch->curr_desc == ch->desc_len) + ch->curr_desc = 0; + + local_irq_restore(flag); + return len; +} +EXPORT_SYMBOL(dma_device_write); + +/** + * Display descriptor list via proc file + * + * \param chan_no - logical channel number + * \ingroup Internal + */ +int desc_list_proc_read(char *buf, char **start, off_t offset, + int count, int *eof, void *data) +{ + int len = 0; + int i; + static int chan_no; + u32 *p; + + if ((chan_no == 0) && (offset > count)) { + *eof = 1; + return 0; + } + + if (chan_no != 0) { + *start = buf; + } else { + buf = buf + offset; + *start = buf; + } + + p = (u32 *)dma_chan[chan_no].desc_base; + + if (dma_chan[chan_no].dir == DIR_RX) + len += sprintf(buf + len, + "channel %d %s Rx descriptor list:\n", + chan_no, dma_chan[chan_no].dma_dev->device_name); + else + len += sprintf(buf + len, + "channel %d %s Tx descriptor list:\n", + chan_no, dma_chan[chan_no].dma_dev->device_name); + len += sprintf(buf + len, + " no address data pointer command bits " + "(Own, Complete, SoP, EoP, Offset) \n"); + len += sprintf(buf + len, + "----------------------------------------------" + "-----------------------------------\n"); + for (i = 0; i < dma_chan[chan_no].desc_len; i++) { + len += sprintf(buf + len, "%3d ", i); + len += sprintf(buf + len, "0x%08x ", (u32)(p + (i * 2))); + len += sprintf(buf + len, "%08x ", *(p + (i * 2 + 1))); + len += sprintf(buf + len, "%08x ", *(p + (i * 2))); + + if (*(p + (i * 2)) & 0x80000000) + len += sprintf(buf + len, "D "); + else + len += sprintf(buf + len, "C "); + if (*(p + (i * 2)) & 0x40000000) + len += sprintf(buf + len, "C "); + else + len += sprintf(buf + len, "c "); + if (*(p + (i * 2)) & 0x20000000) + len += sprintf(buf + len, "S "); + else + len += sprintf(buf + len, "s "); + if (*(p + (i * 2)) & 0x10000000) + len += sprintf(buf + len, "E "); + else + len += sprintf(buf + len, "e "); + + /* byte offset is different for rx and tx descriptors*/ + if (dma_chan[chan_no].dir == DIR_RX) { + len += sprintf(buf + len, "%01x ", + (*(p + (i * 2)) & 0x01800000) >> 23); + } else { + len += sprintf(buf + len, "%02x ", + (*(p + (i * 2)) & 0x0F800000) >> 23); + } + + if (dma_chan[chan_no].curr_desc == i) + len += sprintf(buf + len, "<- CURR"); + + if (dma_chan[chan_no].prev_desc == i) + len += sprintf(buf + len, "<- PREV"); + + len += sprintf(buf + len, "\n"); + + } + + len += sprintf(buf + len, "\n"); + chan_no++; + if (chan_no > LTQ_MAX_DMA_CHANNEL_NUM - 1) + chan_no = 0; + + *eof = 1; + return len; +} + +/** + * Displays the weight of all DMA channels via proc file + * + * + * + * \param *buf + * \param **start + * \param offset + * \param count + * \param *eof + * \param *data + * \return len - amount of bytes written to file + */ +int channel_weight_proc_read(char *buf, char **start, off_t offset, + int count, int *eof, void *data) +{ + int i; + int len = 0; + len += sprintf(buf + len, "Qos dma channel weight list\n"); + len += sprintf(buf + len, "channel_num default_weight " + "current_weight device Tx/Rx\n"); + len += sprintf(buf + len, "---------------------------" + "---------------------------------\n"); + for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { + struct dma_channel_info *ch = &dma_chan[i]; + + if (ch->dir == DIR_RX) { + len += sprintf(buf + len, + " %2d %08x " + "%08x %10s Rx\n", + i, ch->default_weight, ch->weight, + ch->dma_dev->device_name); + } else { + len += sprintf(buf + len, + " %2d %08x " + "%08x %10s Tx\n", + i, ch->default_weight, ch->weight, + ch->dma_dev->device_name); + } + } + + return len; +} + +/** + * Provides DMA Register Content to proc file + * This function reads the content of general DMA Registers, DMA Channel + * Registers and DMA Port Registers and performs a structures output to the + * DMA proc file + * + * \param *buf + * \param **start + * \param offset + * \param count + * \param *eof + * \param *data + * \return len - amount of bytes written to file + */ +int dma_register_proc_read(char *buf, char **start, off_t offset, + int count, int *eof, void *data) +{ + int len = 0; + int i; + int limit = count; + unsigned long flags; + static int blockcount; + static int channel_no; + + if ((blockcount == 0) && (offset > count)) { + *eof = 1; + return 0; + } + + switch (blockcount) { + case 0: + len += sprintf(buf + len, "\nGeneral DMA Registers\n"); + len += sprintf(buf + len, "-------------------------" + "----------------\n"); + len += sprintf(buf + len, "CLC= %08x\n", dma_r32(clc)); + len += sprintf(buf + len, "ID= %08x\n", dma_r32(id)); + len += sprintf(buf + len, "DMA_CPOLL= %08x\n", dma_r32(cpoll)); + len += sprintf(buf + len, "DMA_CS= %08x\n", dma_r32(cs)); + len += sprintf(buf + len, "DMA_PS= %08x\n", dma_r32(ps)); + len += sprintf(buf + len, "DMA_IRNEN= %08x\n", dma_r32(irnen)); + len += sprintf(buf + len, "DMA_IRNCR= %08x\n", dma_r32(irncr)); + len += sprintf(buf + len, "DMA_IRNICR= %08x\n", + dma_r32(irnicr)); + len += sprintf(buf + len, "\nDMA Channel Registers\n"); + blockcount = 1; + return len; + break; + case 1: + /* If we had an overflow start at beginning of buffer + * otherwise use offset */ + if (channel_no != 0) { + *start = buf; + } else { + buf = buf + offset; + *start = buf; + } + + local_irq_save(flags); + for (i = channel_no; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { + struct dma_channel_info *ch = &dma_chan[i]; + + if (len + 300 > limit) { + local_irq_restore(flags); + channel_no = i; + blockcount = 1; + return len; + } + len += sprintf(buf + len, "----------------------" + "-------------------\n"); + if (ch->dir == DIR_RX) { + len += sprintf(buf + len, + "Channel %d - Device %s Rx\n", + i, ch->dma_dev->device_name); + } else { + len += sprintf(buf + len, + "Channel %d - Device %s Tx\n", + i, ch->dma_dev->device_name); + } + dma_w32(i, cs); + len += sprintf(buf + len, "DMA_CCTRL= %08x\n", + dma_r32(cctrl)); + len += sprintf(buf + len, "DMA_CDBA= %08x\n", + dma_r32(cdba)); + len += sprintf(buf + len, "DMA_CIE= %08x\n", + dma_r32(cie)); + len += sprintf(buf + len, "DMA_CIS= %08x\n", + dma_r32(cis)); + len += sprintf(buf + len, "DMA_CDLEN= %08x\n", + dma_r32(cdlen)); + } + local_irq_restore(flags); + blockcount = 2; + channel_no = 0; + return len; + break; + case 2: + *start = buf; + /* + * display port dependent registers + */ + len += sprintf(buf + len, "\nDMA Port Registers\n"); + len += sprintf(buf + len, + "-----------------------------------------\n"); + local_irq_save(flags); + for (i = 0; i < LTQ_MAX_DMA_DEVICE_NUM; i++) { + dma_w32(i, ps); + len += sprintf(buf + len, + "Port %d DMA_PCTRL= %08x\n", + i, dma_r32(pctrl)); + } + local_irq_restore(flags); + blockcount = 0; + *eof = 1; + return len; + break; + } + + blockcount = 0; + *eof = 1; + return 0; +} + +/** + * Open Method of DMA Device Driver + * This function increments the device driver's use counter. + * + * + * \param + * \return + */ +static int dma_open(struct inode *inode, struct file *file) +{ + return 0; +} + +/** + * Release Method of DMA Device driver. + * This function decrements the device driver's use counter. + * + * + * \param + * \return + */ +static int dma_release(struct inode *inode, struct file *file) +{ + /* release the resources */ + return 0; +} + +/** + * Ioctl Interface to DMA Module + * + * \param None + * \return 0 - initialization successful + * <0 - failed initialization + */ +static long dma_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + int result = 0; + /* TODO: add some user controled functions here */ + return result; +} + +const static struct file_operations dma_fops = { + .owner = THIS_MODULE, + .open = dma_open, + .release = dma_release, + .unlocked_ioctl = dma_ioctl, +}; + +void map_dma_chan(struct dma_channel_info *map) +{ + int i; + + /* assign default values for channel settings */ + for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { + dma_chan[i].byte_offset = 0; + dma_chan[i].open = &open_chan; + dma_chan[i].close = &close_chan; + dma_chan[i].reset = &reset_chan; + dma_chan[i].enable_irq = enable_ch_irq; + dma_chan[i].disable_irq = disable_ch_irq; + dma_chan[i].tx_weight = 1; + dma_chan[i].control = 0; + dma_chan[i].default_weight = LTQ_DMA_CH_DEFAULT_WEIGHT; + dma_chan[i].weight = dma_chan[i].default_weight; + dma_chan[i].curr_desc = 0; + dma_chan[i].prev_desc = 0; + } + + /* assign default values for port settings */ + for (i = 0; i < LTQ_MAX_DMA_DEVICE_NUM; i++) { + /*set default tx channel number to be one*/ + dma_devices[i].num_tx_chan = 1; + /*set default rx channel number to be one*/ + dma_devices[i].num_rx_chan = 1; + dma_devices[i].buffer_alloc = common_buffer_alloc; + dma_devices[i].buffer_free = common_buffer_free; + dma_devices[i].intr_handler = NULL; + dma_devices[i].tx_burst_len = 4; + dma_devices[i].rx_burst_len = 4; +#ifdef CONFIG_CPU_LITTLE_ENDIAN + dma_devices[i].tx_endianness_mode = 0; + dma_devices[i].rx_endianness_mode = 0; +#else + dma_devices[i].tx_endianness_mode = 3; + dma_devices[i].rx_endianness_mode = 3; +#endif + } +} + +void dma_chip_init(void) +{ + int i; + + sys1_w32(SYS1_CLKENR_DMA, clkenr); + wmb(); + /* reset DMA */ + dma_w32(DMA_CTRL_RST, ctrl); + wmb(); + /* disable all the interrupts first */ + dma_w32(0, irnen); + + /* enable polling for all channels */ + dma_w32(DMA_CPOLL_EN | DMA_CPOLL_CNT_VAL(DMA_POLL_COUNTER), cpoll); + + /****************************************************/ + for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) + disable_ch_irq(&dma_chan[i]); +} + +int ltq_dma_init(void) +{ + int result = 0; + int i; + unsigned long flag; + static int dma_initialized; + + if (dma_initialized == 1) + return 0; + dma_initialized = 1; + + result = register_chrdev(DMA_MAJOR, "dma-core", &dma_fops); + if (result) { + DMA_EMSG("cannot register device dma-core!\n"); + return result; + } + + dma_chip_init(); + map_dma_chan(dma_chan); + + /* allocate DMA memory for buffer descriptors */ + for (i = 0; i < DMA_DESCR_MEM_PAGES; i++) { + g_desc_list[i] = (u64 *)__get_free_page(GFP_DMA); + if (g_desc_list[i] == NULL) { + DMA_EMSG("no memory for desriptor\n"); + return -ENOMEM; + } + g_desc_list[i] = (u64 *)KSEG1ADDR(g_desc_list[i]); + memset(g_desc_list[i], 0, PAGE_SIZE); + } + + for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { + int page_index, ch_per_page; + /* cross-link relative channels of a port to + * corresponding absolute channels */ + if (dma_chan[i].dir == DIR_RX) { + ((struct dma_device_info *)(dma_chan[i].dma_dev))-> + rx_chan[dma_chan[i].rel_chan_no] = &dma_chan[i]; + } else { + ((struct dma_device_info *)(dma_chan[i].dma_dev))-> + tx_chan[dma_chan[i].rel_chan_no] = &dma_chan[i]; + } + dma_chan[i].abs_chan_no = i; + + page_index = i * DMA_DESCR_CH_SIZE / PAGE_SIZE; + ch_per_page = PAGE_SIZE / DMA_DESCR_CH_SIZE + + ((PAGE_SIZE % DMA_DESCR_CH_SIZE) > 0); + dma_chan[i].desc_base = + (u32)g_desc_list[page_index] + + (i - page_index*ch_per_page) * DMA_DESCR_NUM*8; + dma_chan[i].curr_desc = 0; + dma_chan[i].desc_len = DMA_DESCR_NUM; + + local_irq_save(flag); + mbs_grab(); + dma_w32(i, cs); + dma_w32((u32)CPHYSADDR(dma_chan[i].desc_base), cdba); + mbs_release(); + local_irq_restore(flag); + } + + g_dma_dir = proc_mkdir("driver/" DRV_NAME, NULL); + + create_proc_read_entry("dma_register", + 0, + g_dma_dir, + dma_register_proc_read, + NULL); + + create_proc_read_entry("g_desc_list", + 0, + g_dma_dir, + desc_list_proc_read, + NULL); + + create_proc_read_entry("channel_weight", + 0, + g_dma_dir, + channel_weight_proc_read, + NULL); + + printk(KERN_NOTICE "SVIP DMA engine initialized\n"); + + return 0; +} + +/** + * Cleanup DMA device + * This function releases all resources used by the DMA device driver on + * module removal. + * + * + * \param None + * \return Nothing + */ +void dma_cleanup(void) +{ + int i; + unregister_chrdev(DMA_MAJOR, "dma-core"); + + for (i = 0; i < DMA_DESCR_MEM_PAGES; i++) + free_page(KSEG0ADDR((unsigned long)g_desc_list[i])); + remove_proc_entry("channel_weight", g_dma_dir); + remove_proc_entry("g_desc_list", g_dma_dir); + remove_proc_entry("dma_register", g_dma_dir); + remove_proc_entry("driver/" DRV_NAME, NULL); + /* release the resources */ + for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) + free_irq(dma_chan[i].irq, (void *)&dma_chan[i]); +} + +arch_initcall(ltq_dma_init); + +MODULE_LICENSE("GPL"); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/gpio.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/gpio.c new file mode 100644 index 0000000000..398339201e --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/svip/gpio.c @@ -0,0 +1,553 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define DRV_NAME "ifxmips_gpio" + +int gpio_to_irq(unsigned int gpio) +{ + return -EINVAL; +} +EXPORT_SYMBOL(gpio_to_irq); + +int irq_to_gpio(unsigned int gpio) +{ + return -EINVAL; +} +EXPORT_SYMBOL(irq_to_gpio); + +struct ltq_port_base { + struct svip_reg_port *base; + u32 pins; +}; + +/* Base addresses for ports */ +static const struct ltq_port_base ltq_port_base[] = { + { (struct svip_reg_port *)LTQ_PORT_P0_BASE, 20 }, + { (struct svip_reg_port *)LTQ_PORT_P1_BASE, 20 }, + { (struct svip_reg_port *)LTQ_PORT_P2_BASE, 19 }, + { (struct svip_reg_port *)LTQ_PORT_P3_BASE, 20 }, + { (struct svip_reg_port *)LTQ_PORT_P4_BASE, 24 } +}; + +#define MAX_PORTS ARRAY_SIZE(ltq_port_base) +#define PINS_PER_PORT(port) (ltq_port_base[port].pins) + +static inline +void ltq_port_set_exintcr0(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->exintcr0) | (1 << pin), + ltq_port_base[port].base->exintcr0); +} + +static inline +void ltq_port_clear_exintcr0(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->exintcr0) & ~(1 << pin), + ltq_port_base[port].base->exintcr0); +} + +static inline +void ltq_port_set_exintcr1(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->exintcr1) | (1 << pin), + ltq_port_base[port].base->exintcr1); +} + +static inline +void ltq_port_clear_exintcr1(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->exintcr1) & ~(1 << pin), + ltq_port_base[port].base->exintcr1); +} + +static inline +void ltq_port_set_irncfg(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->irncfg) | (1 << pin), + ltq_port_base[port].base->irncfg); +} + +static inline +void ltq_port_clear_irncfg(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->irncfg) & ~(1 << pin), + ltq_port_base[port].base->irncfg); +} + +static inline +void ltq_port_set_irnen(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(1 << pin, ltq_port_base[port].base->irnenset); +} + +static inline +void ltq_port_clear_irnen(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(1 << pin, ltq_port_base[port].base->irnenclr); +} + +static inline +void ltq_port_set_dir_out(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->dir) | (1 << pin), + ltq_port_base[port].base->dir); +} + +static inline +void ltq_port_set_dir_in(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->dir) & ~(1 << pin), + ltq_port_base[port].base->dir); +} + +static inline +void ltq_port_set_output(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->out) | (1 << pin), + ltq_port_base[port].base->out); +} + +static inline +void ltq_port_clear_output(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->out) & ~(1 << pin), + ltq_port_base[port].base->out); +} + +static inline +int ltq_port_get_input(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return -EINVAL; + + return (port_r32(ltq_port_base[port].base->in) & (1 << pin)) == 0; +} + +static inline +void ltq_port_set_puen(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->puen) | (1 << pin), + ltq_port_base[port].base->puen); +} + +static inline +void ltq_port_clear_puen(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->puen) & ~(1 << pin), + ltq_port_base[port].base->puen); +} + +static inline +void ltq_port_set_altsel0(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->altsel0) | (1 << pin), + ltq_port_base[port].base->altsel0); +} + +static inline +void ltq_port_clear_altsel0(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->altsel0) & ~(1 << pin), + ltq_port_base[port].base->altsel0); +} + +static inline +void ltq_port_set_altsel1(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->altsel1) | (1 << pin), + ltq_port_base[port].base->altsel1); +} + +static inline +void ltq_port_clear_altsel1(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return; + + port_w32(port_r32(ltq_port_base[port].base->altsel1) & ~(1 << pin), + ltq_port_base[port].base->altsel1); +} + +void ltq_gpio_configure(int port, int pin, bool dirin, bool puen, + bool altsel0, bool altsel1) +{ + if (dirin) + ltq_port_set_dir_in(port, pin); + else + ltq_port_set_dir_out(port, pin); + + if (puen) + ltq_port_set_puen(port, pin); + else + ltq_port_clear_puen(port, pin); + + if (altsel0) + ltq_port_set_altsel0(port, pin); + else + ltq_port_clear_altsel0(port, pin); + + if (altsel1) + ltq_port_set_altsel1(port, pin); + else + ltq_port_clear_altsel1(port, pin); +} + +int ltq_port_get_dir(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return -EINVAL; + + return (port_r32(ltq_port_base[port].base->dir) & (1 << pin)) != 0; +} + +int ltq_port_get_puden(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return -EINVAL; + + return (port_r32(ltq_port_base[port].base->puen) & (1 << pin)) != 0; +} + +int ltq_port_get_altsel0(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return -EINVAL; + + return (port_r32(ltq_port_base[port].base->altsel0) & (1 << pin)) != 0; +} + +int ltq_port_get_altsel1(unsigned int port, unsigned int pin) +{ + if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) + return -EINVAL; + + return (port_r32(ltq_port_base[port].base->altsel1) & (1 << pin)) != 0; +} + +struct ltq_gpio_port { + struct gpio_chip gpio_chip; + unsigned int irq_base; + unsigned int chained_irq; +}; + +static struct ltq_gpio_port ltq_gpio_port[MAX_PORTS]; + +static int gpio_exported; +static int __init gpio_export_setup(char *str) +{ + get_option(&str, &gpio_exported); + return 1; +} +__setup("gpio_exported=", gpio_export_setup); + +static inline unsigned int offset2port(unsigned int offset) +{ + unsigned int i; + unsigned int prev = 0; + + for (i = 0; i < ARRAY_SIZE(ltq_port_base); i++) { + if (offset >= prev && + offset < prev + ltq_port_base[i].pins) + return i; + + prev = ltq_port_base[i].pins; + } + + return 0; +} + +static inline unsigned int offset2pin(unsigned int offset) +{ + unsigned int i; + unsigned int prev = 0; + + for (i = 0; i < ARRAY_SIZE(ltq_port_base); i++) { + if (offset >= prev && + offset < prev + ltq_port_base[i].pins) + return offset - prev; + + prev = ltq_port_base[i].pins; + } + + return 0; +} + +static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) +{ + ltq_port_set_dir_in(offset2port(offset), offset2pin(offset)); + return 0; +} + +static int ltq_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + ltq_port_set_dir_out(offset2port(offset), offset2pin(offset)); + return 0; +} + +static int ltq_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + return ltq_port_get_input(offset2port(offset), offset2pin(offset)); +} + +static void ltq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) +{ + if (value) + ltq_port_set_output(offset2port(offset), offset2pin(offset)); + else + ltq_port_clear_output(offset2port(offset), offset2pin(offset)); +} + +static int svip_gpio_request(struct gpio_chip *chip, unsigned offset) +{ + return 0; +} + +static void ltq_gpio_free(struct gpio_chip *chip, unsigned offset) +{ +} + +static int ltq_gpio_probe(struct platform_device *pdev) +{ + int ret = 0; + struct ltq_gpio_port *gpio_port; + + if (pdev->id >= MAX_PORTS) + return -ENODEV; + + gpio_port = <q_gpio_port[pdev->id]; + gpio_port->gpio_chip.label = "ltq-gpio"; + + gpio_port->gpio_chip.direction_input = ltq_gpio_direction_input; + gpio_port->gpio_chip.direction_output = ltq_gpio_direction_output; + gpio_port->gpio_chip.get = ltq_gpio_get; + gpio_port->gpio_chip.set = ltq_gpio_set; + gpio_port->gpio_chip.request = svip_gpio_request; + gpio_port->gpio_chip.free = ltq_gpio_free; + gpio_port->gpio_chip.base = 100 * pdev->id; + gpio_port->gpio_chip.ngpio = 32; + gpio_port->gpio_chip.dev = &pdev->dev; + gpio_port->gpio_chip.exported = gpio_exported; + + ret = gpiochip_add(&gpio_port->gpio_chip); + if (ret < 0) { + dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n", + pdev->id, ret); + goto err; + } + platform_set_drvdata(pdev, gpio_port); + + return 0; + +err: + return ret; +} + +static int ltq_gpio_remove(struct platform_device *pdev) +{ + struct ltq_gpio_port *gpio_port = platform_get_drvdata(pdev); + int ret; + + ret = gpiochip_remove(&gpio_port->gpio_chip); + + return ret; +} + +static struct platform_driver ltq_gpio_driver = { + .probe = ltq_gpio_probe, + .remove = __devexit_p(ltq_gpio_remove), + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +int __init ltq_gpio_init(void) +{ + int ret = platform_driver_register(<q_gpio_driver); + if (ret) + printk(KERN_INFO DRV_NAME + ": Error registering platform driver!"); + return ret; +} + +postcore_initcall(ltq_gpio_init); + +/** + * Convert interrupt number to corresponding port/pin pair + * Returns the port/pin pair serving the selected external interrupt; + * needed since mapping not linear. + * + * \param exint External interrupt number + * \param port Pointer for resulting port + * \param pin Pointer for resutling pin + * \return -EINVAL Invalid exint + * \return 0 port/pin updated + * \ingroup API + */ +static int ltq_exint2port(u32 exint, int *port, int *pin) +{ + if ((exint >= 0) && (exint <= 10)) { + *port = 0; + *pin = exint + 7; + } else if ((exint >= 11) && (exint <= 14)) { + *port = 1; + *pin = 18 - (exint - 11) ; + } else if (exint == 15) { + *port = 1; + *pin = 19; + } else if (exint == 16) { + *port = 0; + *pin = 19; + } else { + return -EINVAL; + } + return 0; +} + +/** + * Enable external interrupt. + * This function enables an external interrupt and sets the given mode. + * valid values for mode are: + * - 0 = Interrupt generation disabled + * - 1 = Interrupt on rising edge + * - 2 = Interrupt on falling edge + * - 3 = Interrupt on rising and falling edge + * - 5 = Interrupt on high level detection + * - 6 = Interrupt on low level detection + * + * \param exint - Number of external interrupt + * \param mode - Trigger mode + * \return 0 on success + * \ingroup API + */ +int ifx_enable_external_int(u32 exint, u32 mode) +{ + int port; + int pin; + + if ((mode < 0) || (mode > 6)) + return -EINVAL; + + if (ltq_exint2port(exint, &port, &pin)) + return -EINVAL; + + ltq_port_clear_exintcr0(port, pin); + ltq_port_clear_exintcr1(port, pin); + ltq_port_clear_irncfg(port, pin); + + if (mode & 0x1) + ltq_port_set_exintcr0(port, pin); + if (mode & 0x2) + ltq_port_set_exintcr1(port, pin); + if (mode & 0x4) + ltq_port_set_irncfg(port, pin); + + ltq_port_set_irnen(port, pin); + return 0; +} +EXPORT_SYMBOL(ifx_enable_external_int); + +/** + * Disable external interrupt. + * This function disables an external interrupt and sets mode to 0x00. + * + * \param exint - Number of external interrupt + * \return 0 on success + * \ingroup API + */ +int ifx_disable_external_int(u32 exint) +{ + int port; + int pin; + + if (ltq_exint2port(exint, &port, &pin)) + return -EINVAL; + + ltq_port_clear_irnen(port, pin); + return 0; +} +EXPORT_SYMBOL(ifx_disable_external_int); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/mach-easy33016.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/mach-easy33016.c new file mode 100644 index 0000000000..c5993efd6d --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/svip/mach-easy33016.c @@ -0,0 +1,73 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../machtypes.h" + +#include +#include +#include + +#include "devices.h" + +static const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS] = { + LTQ_MUX_P0_0_SSC0_MTSR, + LTQ_MUX_P0_1_SSC0_MRST, + LTQ_MUX_P0_2_SSC0_SCLK, + LTQ_MUX_P0_3_SSC1_MTSR, + LTQ_MUX_P0_4_SSC1_MRST, + LTQ_MUX_P0_5_SSC1_SCLK, + LTQ_MUX_P0_6_SSC0_CS0, + LTQ_MUX_P0_7_SSC0_CS1, + LTQ_MUX_P0_8_SSC0_CS2, + LTQ_MUX_P0_9, + LTQ_MUX_P0_10, + LTQ_MUX_P0_11_EXINT4, + LTQ_MUX_P0_12, + LTQ_MUX_P0_13, + LTQ_MUX_P0_14_ASC0_TXD, + LTQ_MUX_P0_15_ASC0_RXD, + LTQ_MUX_P0_16_EXINT9, + LTQ_MUX_P0_17_EXINT10, + LTQ_MUX_P0_18_EJ_BRKIN, + LTQ_MUX_P0_19_EXINT16 +}; + +static void __init easy33016_init(void) +{ + svip_sys1_clk_enable(SYS1_CLKENR_L2C | + SYS1_CLKENR_DDR2 | + SYS1_CLKENR_SMI2 | + SYS1_CLKENR_SMI1 | + SYS1_CLKENR_SMI0 | + SYS1_CLKENR_FMI0 | + SYS1_CLKENR_DMA | + SYS1_CLKENR_SSC0 | + SYS1_CLKENR_SSC1 | + SYS1_CLKENR_EBU); + + svip_sys2_clk_enable(SYS2_CLKENR_HWSYNC | + SYS2_CLKENR_MBS | + SYS2_CLKENR_SWINT); + + svip_register_mux(mux_p0, NULL, NULL, NULL, NULL); + svip_register_asc(0); + svip_register_eth(); + svip_register_virtual_eth(); + ltq_register_wdt(); + svip_register_gpio(); + svip_register_spi(); + svip_register_nand(); +} + +MIPS_MACHINE(LANTIQ_MACH_EASY33016, + "EASY33016", + "EASY33016", + easy33016_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/mach-easy336.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/mach-easy336.c new file mode 100644 index 0000000000..460bb7d85d --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/svip/mach-easy336.c @@ -0,0 +1,221 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../machtypes.h" + +#include +#include +#include + +#include "devices.h" + +static struct mtd_partition easy336_sflash_partitions[] = { + { + .name = "SPI flash", + .size = MTDPART_SIZ_FULL, + .offset = 0, + }, +}; + +static struct flash_platform_data easy336_sflash_data = { + .name = "m25p32", + .parts = (void *)&easy336_sflash_partitions, + .nr_parts = ARRAY_SIZE(easy336_sflash_partitions), + .type = "m25p32", +}; + +static struct spi_board_info bdinfo[] __initdata = { + { + .modalias = "m25p80", + .platform_data = &easy336_sflash_data, + .mode = SPI_MODE_0, + .irq = -1, + .max_speed_hz = 25000000, + .bus_num = 0, + .chip_select = 0, + } +}; + +static struct mtd_partition easy336_partitions[] = { + { + .name = "uboot", + .offset = 0x0, + .size = 0x40000, + }, + { + .name = "uboot_env", + .offset = 0x40000, + .size = 0x20000, + }, + { + .name = "linux", + .offset = 0x60000, + .size = 0x1a0000, + }, + { + .name = "rootfs", + .offset = 0x200000, + .size = 0x500000, + }, +}; + +static struct physmap_flash_data easy336_flash_data = { + .nr_parts = ARRAY_SIZE(easy336_partitions), + .parts = easy336_partitions, +}; + +static const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS] = { + LTQ_MUX_P0_0_SSC0_MTSR, + LTQ_MUX_P0_1_SSC0_MRST, + LTQ_MUX_P0_2_SSC0_SCLK, + LTQ_MUX_P0_3_SSC1_MTSR, + LTQ_MUX_P0_4_SSC1_MRST, + LTQ_MUX_P0_5_SSC1_SCLK, + LTQ_MUX_P0_6_SSC0_CS0, + LTQ_MUX_P0_7_SSC0_CS1, + LTQ_MUX_P0_8_SSC0_CS2, + LTQ_MUX_P0_9_SSC0_CS3, + LTQ_MUX_P0_10_SSC0_CS4, + LTQ_MUX_P0_11_SSC0_CS5, + LTQ_MUX_P0_12_EXINT5, + LTQ_MUX_P0_13_EXINT6, + LTQ_MUX_P0_14_ASC0_TXD, + LTQ_MUX_P0_15_ASC0_RXD, + LTQ_MUX_P0_16_EXINT9, + LTQ_MUX_P0_17_EXINT10, + LTQ_MUX_P0_18_EJ_BRKIN, + LTQ_MUX_P0_19_EXINT16 +}; + +static const struct ltq_mux_pin mux_p2[LTQ_MUX_P2_PINS] = { + LTQ_MUX_P2_0_EBU_A0, + LTQ_MUX_P2_1_EBU_A1, + LTQ_MUX_P2_2_EBU_A2, + LTQ_MUX_P2_3_EBU_A3, + LTQ_MUX_P2_4_EBU_A4, + LTQ_MUX_P2_5_EBU_A5, + LTQ_MUX_P2_6_EBU_A6, + LTQ_MUX_P2_7_EBU_A7, + LTQ_MUX_P2_8_EBU_A8, + LTQ_MUX_P2_9_EBU_A9, + LTQ_MUX_P2_10_EBU_A10, + LTQ_MUX_P2_11_EBU_A11, + LTQ_MUX_P2_12_EBU_RD, + LTQ_MUX_P2_13_EBU_WR, + LTQ_MUX_P2_14_EBU_ALE, + LTQ_MUX_P2_15_EBU_WAIT, + LTQ_MUX_P2_16_EBU_RDBY, + LTQ_MUX_P2_17_EBU_BC0, + LTQ_MUX_P2_18_EBU_BC1 +}; + +static const struct ltq_mux_pin mux_p3[LTQ_MUX_P3_PINS] = { + LTQ_MUX_P3_0_EBU_AD0, + LTQ_MUX_P3_1_EBU_AD1, + LTQ_MUX_P3_2_EBU_AD2, + LTQ_MUX_P3_3_EBU_AD3, + LTQ_MUX_P3_4_EBU_AD4, + LTQ_MUX_P3_5_EBU_AD5, + LTQ_MUX_P3_6_EBU_AD6, + LTQ_MUX_P3_7_EBU_AD7, + LTQ_MUX_P3_8_EBU_AD8, + LTQ_MUX_P3_9_EBU_AD9, + LTQ_MUX_P3_10_EBU_AD10, + LTQ_MUX_P3_11_EBU_AD11, + LTQ_MUX_P3_12_EBU_AD12, + LTQ_MUX_P3_13_EBU_AD13, + LTQ_MUX_P3_14_EBU_AD14, + LTQ_MUX_P3_15_EBU_AD15, + LTQ_MUX_P3_16_EBU_CS0, + LTQ_MUX_P3_17_EBU_CS1, + LTQ_MUX_P3_18_EBU_CS2, + LTQ_MUX_P3_19_EBU_CS3 +}; + +static void __init easy336_init_common(void) +{ + svip_sys1_clk_enable(SYS1_CLKENR_L2C | + SYS1_CLKENR_DDR2 | + SYS1_CLKENR_SMI2 | + SYS1_CLKENR_SMI1 | + SYS1_CLKENR_SMI0 | + SYS1_CLKENR_FMI0 | + SYS1_CLKENR_DMA | + SYS1_CLKENR_GPTC | + SYS1_CLKENR_EBU); + + svip_sys2_clk_enable(SYS2_CLKENR_HWSYNC | + SYS2_CLKENR_MBS | + SYS2_CLKENR_SWINT | + SYS2_CLKENR_HWACC3 | + SYS2_CLKENR_HWACC2 | + SYS2_CLKENR_HWACC1 | + SYS2_CLKENR_HWACC0 | + SYS2_CLKENR_SIF7 | + SYS2_CLKENR_SIF6 | + SYS2_CLKENR_SIF5 | + SYS2_CLKENR_SIF4 | + SYS2_CLKENR_SIF3 | + SYS2_CLKENR_SIF2 | + SYS2_CLKENR_SIF1 | + SYS2_CLKENR_SIF0 | + SYS2_CLKENR_DFEV7 | + SYS2_CLKENR_DFEV6 | + SYS2_CLKENR_DFEV5 | + SYS2_CLKENR_DFEV4 | + SYS2_CLKENR_DFEV3 | + SYS2_CLKENR_DFEV2 | + SYS2_CLKENR_DFEV1 | + SYS2_CLKENR_DFEV0); + + svip_register_mux(mux_p0, NULL, mux_p2, mux_p3, NULL); + svip_register_asc(0); + svip_register_eth(); + svip_register_virtual_eth(); + /* ltq_register_wdt(); - conflicts with lq_switch */ + svip_register_gpio(); + svip_register_spi(); + ltq_register_tapi(); +} + +static void __init easy336_init(void) +{ + easy336_init_common(); + ltq_register_nor(&easy336_flash_data); +} + +static void __init easy336sf_init(void) +{ + easy336_init_common(); + svip_register_spi_flash(bdinfo); +} + +static void __init easy336nand_init(void) +{ + easy336_init_common(); + svip_register_nand(); +} + +MIPS_MACHINE(LANTIQ_MACH_EASY336, + "EASY336", + "EASY336", + easy336_init); + +MIPS_MACHINE(LANTIQ_MACH_EASY336SF, + "EASY336SF", + "EASY336 (Serial Flash)", + easy336sf_init); + +MIPS_MACHINE(LANTIQ_MACH_EASY336NAND, + "EASY336NAND", + "EASY336 (NAND Flash)", + easy336nand_init); + diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/mux.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/mux.c new file mode 100644 index 0000000000..56805e55bb --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/svip/mux.c @@ -0,0 +1,187 @@ +/************************************************************************ + * + * Copyright (c) 2007 + * Infineon Technologies AG + * St. Martin Strasse 53; 81669 Muenchen; Germany + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + ************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define DRV_NAME "ltq_mux" + +static void ltq_mux_port_init(const int port, + const struct ltq_mux_pin *pins, + const int pin_max) +{ + unsigned int i; + + for (i = 0; i < pin_max; i++) + ltq_gpio_configure(port, + i, + pins[i].dirin, + pins[i].puen, + pins[i].altsel0, + pins[i].altsel1); +} + +static int ltq_mux_probe(struct platform_device *pdev) +{ + struct ltq_mux_settings *mux_settings = dev_get_platdata(&pdev->dev); + + if (mux_settings->mux_p0) + ltq_mux_port_init(0, + mux_settings->mux_p0, + LTQ_MUX_P0_PINS); + + if (mux_settings->mux_p1) + ltq_mux_port_init(1, + mux_settings->mux_p1, + LTQ_MUX_P1_PINS); + + if (mux_settings->mux_p2) + ltq_mux_port_init(2, + mux_settings->mux_p2, + LTQ_MUX_P2_PINS); + + if (mux_settings->mux_p3) + ltq_mux_port_init(3, + mux_settings->mux_p3, + LTQ_MUX_P3_PINS); + + if (mux_settings->mux_p4) + ltq_mux_port_init(4, + mux_settings->mux_p4, + LTQ_MUX_P4_PINS); + + return 0; +} + +int ltq_mux_read_procmem(char *buf, char **start, off_t offset, + int count, int *eof, void *data) +{ + int len = 0; + int t = 0, i = 0; + u32 port_clk[5] = { + SYS1_CLKENR_PORT0, + SYS1_CLKENR_PORT1, + SYS1_CLKENR_PORT2, + SYS1_CLKENR_PORT3, + SYS2_CLKENR_PORT4, + }; + +#define PROC_PRINT(fmt, args...) \ + do { \ + int c_len = 0; \ + c_len = snprintf(buf + len, count - len, fmt, ## args); \ + if (c_len <= 0) \ + goto out; \ + if (c_len >= (count - len)) { \ + len += (count - len); \ + goto out; \ + } \ + len += c_len; \ + if (offset > 0) { \ + if (len > offset) { \ + len -= offset; \ + memmove(buf, buf + offset, len); \ + offset = 0; \ + } else { \ + offset -= len; \ + len = 0; \ + } \ + } \ + } while (0) + + PROC_PRINT("\nVINETIC-SVIP Multiplex Settings\n"); + PROC_PRINT(" 3 2 1 0\n"); + PROC_PRINT(" 10987654321098765432109876543210\n"); + PROC_PRINT(" --------------------------------\n"); + + for (i = 0; i < ARRAY_SIZE(port_clk); i++) { + if (i < 4) { + if (!svip_sys1_clk_is_enabled(port_clk[i])) + continue; + } else { + if (!svip_sys2_clk_is_enabled(port_clk[i])) + continue; + } + + PROC_PRINT("P%d.%-10s", i, "DIR:"); + + for (t = 31; t != -1; t--) + PROC_PRINT("%d", ltq_port_get_dir(i, t) == 1 ? 1 : 0); + PROC_PRINT("\n"); + + PROC_PRINT("P%d.%-10s", i, "PUEN:"); + for (t = 31; t != -1; t--) + PROC_PRINT("%d", ltq_port_get_puden(i, t) == 1 ? 1 : 0); + PROC_PRINT("\n"); + + PROC_PRINT("P%d.%-10s", i, "ALTSEL0:"); + for (t = 31; t != -1; t--) + PROC_PRINT("%d", + ltq_port_get_altsel0(i, t) == 1 ? 1 : 0); + PROC_PRINT("\n"); + + PROC_PRINT("P%d.%-10s", i, "ALTSEL1:"); + for (t = 31; t != -1; t--) + PROC_PRINT("%d", + ltq_port_get_altsel1(i, t) == 1 ? 1 : 0); + PROC_PRINT("\n\n"); + } + +out: + if (len < 0) { + len = 0; + *eof = 1; + } else if (len < count) { + *eof = 1; + } else { + len = count; + } + + *start = buf; + + return len; +} + +static struct platform_driver ltq_mux_driver = { + .probe = ltq_mux_probe, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +int __init ltq_mux_init(void) +{ + int ret = platform_driver_register(<q_mux_driver); + if (ret) { + printk(KERN_INFO DRV_NAME + ": Error registering platform driver!"); + return ret; + } + + return create_proc_read_entry("driver/ltq_mux", 0, NULL, + ltq_mux_read_procmem, NULL) == NULL; +} + +module_init(ltq_mux_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/pms.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/pms.c new file mode 100644 index 0000000000..5c0c808a04 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/svip/pms.c @@ -0,0 +1,101 @@ +/************************************************************************ + * + * Copyright (c) 2007 + * Infineon Technologies AG + * St. Martin Strasse 53; 81669 Muenchen; Germany + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + ************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; +static struct svip_reg_sys2 *const sys2 = (struct svip_reg_sys2 *)LTQ_SYS2_BASE; + +void svip_sys1_clk_enable(u32 mask) +{ + sys1_w32(sys1_r32(clksr) | mask, clkenr); + asm("sync;"); +} +EXPORT_SYMBOL(svip_sys1_clk_enable); + +int svip_sys1_clk_is_enabled(u32 mask) +{ + return (sys1_r32(clksr) & mask) != 0; +} +EXPORT_SYMBOL(svip_sys1_clk_is_enabled); + +void svip_sys2_clk_enable(u32 mask) +{ + sys2_w32(sys2_r32(clksr) | mask, clkenr); + asm("sync;"); +} +EXPORT_SYMBOL(svip_sys2_clk_enable); + +int svip_sys2_clk_is_enabled(u32 mask) +{ + return (sys2_r32(clksr) & mask) != 0; +} +EXPORT_SYMBOL(svip_sys2_clk_is_enabled); + +int ltq_pms_read_procmem(char *buf, char **start, off_t offset, + int count, int *eof, void *data) +{ + long len = 0; + int t = 0; + u32 bit = 0; + u32 reg_tmp, bits_tmp; + + len = sprintf(buf, "\nSVIP PMS Settings\n"); + len = len + sprintf(buf + len, + " 3 2 1 0\n"); + len = len + sprintf(buf + len, + " 210987654321098765432109876543210\n"); + len = len + sprintf(buf + len, + "---------------------------------------------\n"); + len = len + sprintf(buf + len, + "SYS1_CLKSR: "); + reg_tmp = sys1_r32(clksr); + bit = 0x80000000; + for (t = 31; t != -1; t--) { + bits_tmp = (reg_tmp & bit) >> t; + len = len + sprintf(buf + len, "%d", bits_tmp); + bit = bit >> 1; + } + len = len + sprintf(buf + len, "\n\n"); + len = len + sprintf(buf + len, "SYS2_CLKSR: "); + reg_tmp = sys2_r32(clksr); + bit = 0x80000000; + for (t = 31; t != -1; t--) { + bits_tmp = (reg_tmp & bit) >> t; + len = len + sprintf(buf + len, "%d", bits_tmp); + bit = bit >> 1; + } + len = len + sprintf(buf + len, "\n\n"); + + *eof = 1; + + return len; +} + +int __init ltq_pms_init_proc(void) +{ + return create_proc_read_entry("driver/ltq_pms", 0, NULL, + ltq_pms_read_procmem, NULL) == NULL; +} + +module_init(ltq_pms_init_proc); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/prom.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/prom.c new file mode 100644 index 0000000000..1c17531606 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/svip/prom.c @@ -0,0 +1,73 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include + +#include + +#include "../prom.h" +#include "../clk.h" +#include "../machtypes.h" + +#include +#include + +#define SOC_SVIP "SVIP" + +#define PART_SHIFT 12 +#define PART_MASK 0x0FFFF000 +#define REV_SHIFT 28 +#define REV_MASK 0xF0000000 + +static struct svip_reg_ebu *const ebu = (struct svip_reg_ebu *)LTQ_EBU_BASE; + +void __init ltq_soc_init(void) +{ + clkdev_add_static(ltq_svip_cpu_hz(), ltq_svip_fpi_hz(), + ltq_svip_io_region_clock()); +} + +void __init +ltq_soc_setup(void) +{ + if (mips_machtype == LANTIQ_MACH_EASY33016 || + mips_machtype == LANTIQ_MACH_EASY336) { + ebu_w32(0x120000f1, addr_sel_2); + ebu_w32(LTQ_EBU_CON_0_ADSWP | + LTQ_EBU_CON_0_SETUP | + LTQ_EBU_CON_0_BCGEN_VAL(0x02) | + LTQ_EBU_CON_0_WAITWRC_VAL(7) | + LTQ_EBU_CON_0_WAITRDC_VAL(3) | + LTQ_EBU_CON_0_HOLDC_VAL(3) | + LTQ_EBU_CON_0_RECOVC_VAL(3) | + LTQ_EBU_CON_0_CMULT_VAL(3), con_2); + } +} + +void __init +ltq_soc_detect(struct ltq_soc_info *i) +{ + i->partnum = (ltq_r32(LTQ_STATUS_CHIPID) & PART_MASK) >> PART_SHIFT; + i->rev = (ltq_r32(LTQ_STATUS_CHIPID) & REV_MASK) >> REV_SHIFT; + sprintf(i->rev_type, "1.%d", i->rev); + switch (i->partnum) { + case SOC_ID_SVIP: + i->name = SOC_SVIP; + i->type = SOC_TYPE_SVIP; + break; + + default: + printk(KERN_ERR "unknown partnum : 0x%08X\n", i->partnum); + while (1); + break; + } +} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/reset.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/reset.c new file mode 100644 index 0000000000..5551875da6 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/svip/reset.c @@ -0,0 +1,95 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include +#include +#include + +#include +#include "../machtypes.h" +#include +#include +#include +#include + +static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; +static struct svip_reg_ebu *const ebu = (struct svip_reg_ebu *)LTQ_EBU_BASE; + +#define CPLD_CMDREG3 ((volatile unsigned char*)(KSEG1 + 0x120000f3)) +extern void switchip_reset(void); + +static void ltq_machine_restart(char *command) +{ + printk(KERN_NOTICE "System restart\n"); + local_irq_disable(); + + if (mips_machtype == LANTIQ_MACH_EASY33016 || + mips_machtype == LANTIQ_MACH_EASY336) { + /* We just use the CPLD function to reset the entire system as a + workaround for the switch reset problem */ + local_irq_disable(); + ebu_w32(0x120000f1, addr_sel_2); + ebu_w32(0x404027ff, con_2); + + if (mips_machtype == LANTIQ_MACH_EASY336) + /* set bit 0 to reset SVIP */ + *CPLD_CMDREG3 = (1<<0); + else + /* set bit 7 to reset SVIP, set bit 3 to reset xT */ + *CPLD_CMDREG3 = (1<<7) | (1<<3); + } else { + *LTQ_BOOT_RVEC(0) = 0; + /* reset all except PER, SUBSYS and CPU0 */ + sys1_w32(0x00043F3E, rreqr); + /* release WDT0 reset */ + sys1_w32(0x00000100, rrlsr); + /* restore reset value for clock enables */ + sys1_w32(~0x0c000040, clkclr); + /* reset SUBSYS (incl. DDR2) and CPU0 */ + sys1_w32(0x00030001, rbtr); + } + + for (;;) + ; +} + +static void ltq_machine_halt(void) +{ + printk(KERN_NOTICE "System halted.\n"); + local_irq_disable(); + for (;;) + ; +} + +static void ltq_machine_power_off(void) +{ + printk(KERN_NOTICE "Please turn off the power now.\n"); + local_irq_disable(); + for (;;) + ; +} + +/* This function is used by the watchdog driver */ +int ltq_reset_cause(void) +{ + return 0; +} +EXPORT_SYMBOL_GPL(ltq_reset_cause); + +static int __init mips_reboot_setup(void) +{ + _machine_restart = ltq_machine_restart; + _machine_halt = ltq_machine_halt; + pm_power_off = ltq_machine_power_off; + return 0; +} + +arch_initcall(mips_reboot_setup); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/svip/switchip_setup.c b/target/linux/lantiq/files/arch/mips/lantiq/svip/switchip_setup.c new file mode 100644 index 0000000000..5da15327ea --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/svip/switchip_setup.c @@ -0,0 +1,666 @@ +/****************************************************************************** + Copyright (c) 2007, Infineon Technologies. All rights reserved. + + No Warranty + Because the program is licensed free of charge, there is no warranty for + the program, to the extent permitted by applicable law. Except when + otherwise stated in writing the copyright holders and/or other parties + provide the program "as is" without warranty of any kind, either + expressed or implied, including, but not limited to, the implied + warranties of merchantability and fitness for a particular purpose. The + entire risk as to the quality and performance of the program is with + you. should the program prove defective, you assume the cost of all + necessary servicing, repair or correction. + + In no event unless required by applicable law or agreed to in writing + will any copyright holder, or any other party who may modify and/or + redistribute the program as permitted above, be liable to you for + damages, including any general, special, incidental or consequential + damages arising out of the use or inability to use the program + (including but not limited to loss of data or data being rendered + inaccurate or losses sustained by you or third parties or a failure of + the program to operate with any other programs), even if such holder or + other party has been advised of the possibility of such damages. + ****************************************************************************** + Module : switchip_setup.c + Date : 2007-11-09 + Description : Basic setup of embedded ethernet switch "SwitchIP" + Remarks: andreas.schmidt@infineon.com + + *****************************************************************************/ + +/* TODO: get rid of #ifdef CONFIG_LANTIQ_MACH_EASY336 */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; +static struct svip_reg_es *const es = (struct svip_reg_es *)LTQ_ES_BASE; + +/* PHY Organizationally Unique Identifier (OUI) */ +#define PHY_OUI_PMC 0x00E004 +#define PHY_OUI_VITESSE 0x008083 +#define PHY_OUI_DEFAULT 0xFFFFFF + +unsigned short switchip_phy_read(unsigned int phyaddr, unsigned int regaddr); +void switchip_phy_write(unsigned int phyaddr, unsigned int regaddr, + unsigned short data); + +static int phy_address[2] = {0, 1}; +static u32 phy_oui; +static void switchip_mdio_poll_init(void); +static void _switchip_mdio_poll(struct work_struct *work); + +/* struct workqueue_struct mdio_poll_task; */ +static struct workqueue_struct *mdio_poll_workqueue; +DECLARE_DELAYED_WORK(mdio_poll_work, _switchip_mdio_poll); +static int old_link_status[2] = {-1, -1}; + +/** + * Autonegotiation check. + * This funtion checks for link changes. If a link change has occured it will + * update certain switch registers. + */ +static void _switchip_check_phy_status(int port) +{ + int new_link_status; + unsigned short reg1; + + reg1 = switchip_phy_read(phy_address[port], 1); + if ((reg1 == 0xFFFF) || (reg1 == 0x0000)) + return; /* no PHY connected */ + + new_link_status = reg1 & 4; + if (old_link_status[port] ^ new_link_status) { + /* link status change */ + if (!new_link_status) { + if (port == 0) + es_w32_mask(LTQ_ES_P0_CTL_REG_FLP, 0, p0_ctl); + else + es_w32_mask(LTQ_ES_P0_CTL_REG_FLP, 0, p1_ctl); + + /* read again; link bit is latched low! */ + reg1 = switchip_phy_read(phy_address[port], 1); + new_link_status = reg1 & 4; + } + + if (new_link_status) { + unsigned short reg0, reg4, reg5, reg9, reg10; + int phy_pause, phy_speed, phy_duplex; + int aneg_enable, aneg_cmpt; + + reg0 = switchip_phy_read(phy_address[port], 0); + reg4 = switchip_phy_read(phy_address[port], 4); + aneg_enable = reg0 & 0x1000; + aneg_cmpt = reg1 & 0x20; + + if (aneg_enable && aneg_cmpt) { + reg5 = switchip_phy_read(phy_address[port], 5); + switch (phy_oui) { +#ifdef CONFIG_LANTIQ_MACH_EASY336 + case PHY_OUI_PMC: + /* PMC Sierra supports 1Gigabit FD, + * only. On successful + * auto-negotiation, we are sure this + * is what the LP can. */ + phy_pause = ((reg4 & reg5) & 0x0080) >> 7; + phy_speed = 2; + phy_duplex = 1; + break; +#endif + case PHY_OUI_VITESSE: + case PHY_OUI_DEFAULT: + reg9 = switchip_phy_read(phy_address[port], 9); + reg10 = switchip_phy_read(phy_address[port], 10); + + /* Check if advertise and partner + * agree on pause */ + phy_pause = ((reg4 & reg5) & 0x0400) >> 10; + + /* Find the best mode both partners + * support + * Priority: 1GB-FD, 1GB-HD, 100MB-FD, + * 100MB-HD, 10MB-FD, 10MB-HD */ + phy_speed = ((((reg9<<2) & reg10) + & 0x0c00) >> 6) | + (((reg4 & reg5) & 0x01e0) >> 5); + + if (phy_speed >= 0x0020) { + phy_speed = 2; + phy_duplex = 1; + } else if (phy_speed >= 0x0010) { + phy_speed = 2; + phy_duplex = 0; + } else if (phy_speed >= 0x0008) { + phy_speed = 1; + phy_duplex = 1; + } else if (phy_speed >= 0x0004) { + phy_speed = 1; + phy_duplex = 0; + } else if (phy_speed >= 0x0002) { + phy_speed = 0; + phy_duplex = 1; + } else { + phy_speed = 0; + phy_duplex = 0; + } + break; + default: + phy_pause = (reg4 & 0x0400) >> 10; + phy_speed = (reg0 & 0x40 ? 2 : (reg0 >> 13)&1); + phy_duplex = (reg0 >> 8)&1; + break; + } + } else { + /* parallel detection or fixed speed */ + phy_pause = (reg4 & 0x0400) >> 10; + phy_speed = (reg0 & 0x40 ? 2 : (reg0 >> 13)&1); + phy_duplex = (reg0 >> 8)&1; + } + + if (port == 0) { + es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0SPD, + LTQ_ES_RGMII_CTL_REG_P0SPD_VAL(phy_speed), + rgmii_ctl); + es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0DUP, + LTQ_ES_RGMII_CTL_REG_P0DUP_VAL(phy_duplex), + rgmii_ctl); + es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0FCE, + LTQ_ES_RGMII_CTL_REG_P0FCE_VAL(phy_pause), + rgmii_ctl); + + es_w32_mask(0, LTQ_ES_P0_CTL_REG_FLP, p0_ctl); + } else { + es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1SPD, + LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(phy_speed), + rgmii_ctl); + es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1DUP, + LTQ_ES_RGMII_CTL_REG_P1DUP_VAL(phy_duplex), + rgmii_ctl); + es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1FCE, + LTQ_ES_RGMII_CTL_REG_P0FCE_VAL(phy_pause), + rgmii_ctl); + + es_w32_mask(1, LTQ_ES_P0_CTL_REG_FLP, p1_ctl); + } + } + } + old_link_status[port] = new_link_status; +} + +static void _switchip_mdio_poll(struct work_struct *work) +{ + if (es_r32(sw_gctl0) & LTQ_ES_SW_GCTL0_REG_SE) { + _switchip_check_phy_status(0); + _switchip_check_phy_status(1); + } + + queue_delayed_work(mdio_poll_workqueue, &mdio_poll_work, HZ/2); +} + +static void switchip_mdio_poll_init(void) +{ + mdio_poll_workqueue = create_workqueue("SVIP MDIP poll"); + INIT_DELAYED_WORK(&mdio_poll_work, _switchip_mdio_poll); + + queue_delayed_work(mdio_poll_workqueue, &mdio_poll_work, HZ/2); + +} + +unsigned short switchip_phy_read(unsigned int phyaddr, unsigned int regaddr) +{ + /* TODO: protect MDIO access with semaphore */ + es_w32(LTQ_ES_MDIO_CTL_REG_MBUSY + | LTQ_ES_MDIO_CTL_REG_OP_VAL(2) /* read operation */ + | LTQ_ES_MDIO_CTL_REG_PHYAD_VAL(phyaddr) + | LTQ_ES_MDIO_CTL_REG_REGAD_VAL(regaddr), mdio_ctl); + while (es_r32(mdio_ctl) & LTQ_ES_MDIO_CTL_REG_MBUSY); + + return es_r32(mdio_data) & 0xFFFF; +} +EXPORT_SYMBOL(switchip_phy_read); + +void switchip_phy_write(unsigned int phyaddr, unsigned int regaddr, + unsigned short data) +{ + /* TODO: protect MDIO access with semaphore */ + es_w32(LTQ_ES_MDIO_CTL_REG_WD_VAL(data) + | LTQ_ES_MDIO_CTL_REG_MBUSY + | LTQ_ES_MDIO_CTL_REG_OP_VAL(1) /* write operation */ + | LTQ_ES_MDIO_CTL_REG_PHYAD_VAL(phyaddr) + | LTQ_ES_MDIO_CTL_REG_REGAD_VAL(regaddr), mdio_ctl); + while (es_r32(mdio_ctl) & LTQ_ES_MDIO_CTL_REG_MBUSY); + + return; +} +EXPORT_SYMBOL(switchip_phy_write); + +const static u32 switch_reset_offset_000[] = { + /*b8000000:*/ 0xffffffff, 0x00000001, 0x00000001, 0x00000003, + /*b8000010:*/ 0x04070001, 0x04070001, 0x04070001, 0xffffffff, + /*b8000020:*/ 0x00001be8, 0x00001be8, 0x00001be8, 0xffffffff, + /*b8000030:*/ 0x00000000, 0x00000000, 0x00080004, 0x00020001, + /*b8000040:*/ 0x00000000, 0x00000000, 0x00080004, 0x00020001, + /*b8000050:*/ 0x00000000, 0x00000000, 0x00080004, 0x00020001, + /*b8000060:*/ 0x00000000, 0x00000000, 0x00081000, 0x001f7777, + /*b8000070:*/ 0x00000000, 0x00000000, 0x0c00ac2b, 0x0000fa50, + /*b8000080:*/ 0x00001000, 0x00001800, 0x00000000, 0x00000000, + /*b8000090:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b80000a0:*/ 0x00000000, 0x00000050, 0x00000010, 0x00000000, + /*b80000b0:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b80000c0:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b80000d0:*/ 0xffffffff, 0x00000000, 0x00000000 +}; +const static u32 switch_reset_offset_100[] = { + /*b8000100:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b8000110:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b8000120:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b8000130:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b8000140:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b8000150:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b8000160:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b8000170:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b8000180:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b8000190:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b80001a0:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /*b80001b0:*/ 0x00000000, 0x00000000 +}; + +/* + * Switch Reset. + */ +void switchip_reset(void) +{ + volatile unsigned int *reg; + volatile unsigned int rdreg; + int i; + + sys1_w32(SYS1_CLKENR_ETHSW, clkenr); + asm("sync"); + + /* disable P0 */ + es_w32_mask(0, LTQ_ES_P0_CTL_REG_SPS_VAL(1), p0_ctl); + /* disable P1 */ + es_w32_mask(0, LTQ_ES_P0_CTL_REG_SPS_VAL(1), p1_ctl); + /* disable P2 */ + es_w32_mask(0, LTQ_ES_P0_CTL_REG_SPS_VAL(1), p2_ctl); + + /************************************** + * BEGIN: Procedure to clear MAC table + **************************************/ + for (i = 0; i < 3; i++) { + int result; + + /* check if access engine is available */ + while (es_r32(adr_tb_st2) & LTQ_ES_ADR_TB_ST2_REG_BUSY); + + /* initialise to first address */ + es_w32(LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(3) + | LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(0), adr_tb_ctl2); + + /* wait while busy */ + while (es_r32(adr_tb_st2) & LTQ_ES_ADR_TB_ST2_REG_BUSY); + + /* setup the portmap */ + es_w32_mask(0, LTQ_ES_ADR_TB_CTL1_REG_PMAP_VAL(1 << i), + adr_tb_ctl1); + + do { + /* search for addresses by port */ + es_w32(LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(2) + | LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(9), adr_tb_ctl2); + + /* wait while busy */ + while (es_r32(adr_tb_st2) & LTQ_ES_ADR_TB_ST2_REG_BUSY); + + result = LTQ_ES_ADR_TB_ST2_REG_RSLT_GET(es_r32(adr_tb_st2)); + if (result == 0x101) { + printk(KERN_ERR "%s, cmd error\n", __func__); + return; + } + /* if Command OK, address found... */ + if (result == 0) { + unsigned char mac[6]; + + mac[5] = (es_r32(adr_tb_st0) >> 0) & 0xff; + mac[4] = (es_r32(adr_tb_st0) >> 8) & 0xff; + mac[3] = (es_r32(adr_tb_st0) >> 16) & 0xff; + mac[2] = (es_r32(adr_tb_st0) >> 24) & 0xff; + mac[1] = (es_r32(adr_tb_st1) >> 0) & 0xff; + mac[0] = (es_r32(adr_tb_st1) >> 8) & 0xff; + + /* setup address */ + es_w32((mac[5] << 0) | + (mac[4] << 8) | + (mac[3] << 16) | + (mac[2] << 24), adr_tb_ctl0); + es_w32(LTQ_ES_ADR_TB_CTL1_REG_PMAP_VAL(1<= LTQ_ES_ADR_TB_CTL0_REG && + reg <= LTQ_ES_ADR_TB_ST2_REG)) + continue; + + if (switch_reset_offset_000[i] != 0xFFFFFFFF) { + /* write reset value to register */ + *reg = switch_reset_offset_000[i]; + /* read register value back */ + rdreg = *reg; + if (reg == LTQ_ES_SW_GCTL1_REG) + rdreg &= ~LTQ_ES_SW_GCTL1_REG_BISTDN; + /* compare read value with written one */ + if (rdreg != switch_reset_offset_000[i]) { + printk(KERN_ERR "%s,%d: reg %08x mismatch " + "[has:%08x, expect:%08x]\n", + __func__, __LINE__, + (unsigned int)reg, rdreg, + switch_reset_offset_000[i]); + } + } + reg++; + } + + reg = LTQ_ES_VLAN_FLT0_REG; + for (i = 0; i < ARRAY_SIZE(switch_reset_offset_100); i++) { + *reg = switch_reset_offset_100[i]; + rdreg = *reg; + if (rdreg != switch_reset_offset_100[i]) { + printk(KERN_ERR "%s,%d: reg %08x mismatch " + "[has:%08x, expect:%08x]\n", __func__, __LINE__, + (unsigned int)reg, rdreg, + switch_reset_offset_100[i]); + } + reg++; + } +} +EXPORT_SYMBOL(switchip_reset); + +static u32 get_phy_oui(unsigned char phy_addr) +{ + u32 oui; + int i, bit, byte, shift, w; + u16 reg_id[2]; + + /* read PHY identifier registers 1 and 2 */ + reg_id[0] = switchip_phy_read(phy_addr, 2); + reg_id[1] = switchip_phy_read(phy_addr, 3); + + oui = 0; + w = 1; + shift = 7; + byte = 1; + for (i = 0, bit = 10; i <= 21; i++, bit++) { + oui |= ((reg_id[w] & (1< + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "../clk.h" + +static unsigned int ltq_ram_clocks[] = { + CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M }; +#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3] + +#define BASIC_FREQUENCY_1 35328000 +#define BASIC_FREQUENCY_2 36000000 +#define BASIS_REQUENCY_USB 12000000 + +#define GET_BITS(x, msb, lsb) \ + (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) + +/* legacy xway clock */ +#define LTQ_CGU_PLL0_CFG 0x0004 +#define LTQ_CGU_PLL1_CFG 0x0008 +#define LTQ_CGU_PLL2_CFG 0x000C +#define LTQ_CGU_SYS 0x0010 +#define LTQ_CGU_UPDATE 0x0014 +#define LTQ_CGU_IF_CLK 0x0018 +#define LTQ_CGU_OSC_CON 0x001C +#define LTQ_CGU_SMD 0x0020 +#define LTQ_CGU_CT1SR 0x0028 +#define LTQ_CGU_CT2SR 0x002C +#define LTQ_CGU_PCMCR 0x0030 +#define LTQ_CGU_PCI_CR 0x0034 +#define LTQ_CGU_PD_PC 0x0038 +#define LTQ_CGU_FMR 0x003C + +#define CGU_PLL0_PHASE_DIVIDER_ENABLE \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31)) +#define CGU_PLL0_BYPASS \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30)) +#define CGU_PLL0_CFG_DSMSEL \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28)) +#define CGU_PLL0_CFG_FRAC_EN \ + (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27)) +#define CGU_PLL1_SRC \ + (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31)) +#define CGU_PLL2_PHASE_DIVIDER_ENABLE \ + (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20)) +#define CGU_SYS_FPI_SEL (1 << 6) +#define CGU_SYS_DDR_SEL 0x3 +#define CGU_PLL0_SRC (1 << 29) + +#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17) +#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6) +#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2) +#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17) +#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13) + +/* vr9 clock */ +#define LTQ_CGU_SYS_VR9 0x0c +#define LTQ_CGU_IF_CLK_VR9 0x24 + + +static unsigned int ltq_get_pll0_fdiv(void); + +static inline unsigned int get_input_clock(int pll) +{ + switch (pll) { + case 0: + if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC) + return BASIS_REQUENCY_USB; + else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) + return BASIC_FREQUENCY_1; + else + return BASIC_FREQUENCY_2; + case 1: + if (CGU_PLL1_SRC) + return BASIS_REQUENCY_USB; + else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) + return BASIC_FREQUENCY_1; + else + return BASIC_FREQUENCY_2; + case 2: + switch (CGU_PLL2_SRC) { + case 0: + return ltq_get_pll0_fdiv(); + case 1: + return CGU_PLL2_PHASE_DIVIDER_ENABLE ? + BASIC_FREQUENCY_1 : + BASIC_FREQUENCY_2; + case 2: + return BASIS_REQUENCY_USB; + } + default: + return 0; + } +} + +static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den) +{ + u64 res, clock = get_input_clock(pll); + + res = num * clock; + do_div(res, den); + return res; +} + +static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N, + unsigned int K) +{ + unsigned int num = ((N + 1) << 10) + K; + unsigned int den = (M + 1) << 10; + + return cal_dsm(pll, num, den); +} + +static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N, + unsigned int K) +{ + unsigned int num = ((N + 1) << 11) + K + 512; + unsigned int den = (M + 1) << 11; + + return cal_dsm(pll, num, den); +} + +static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N, + unsigned int K) +{ + unsigned int num = K >= 512 ? + ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584; + unsigned int den = (M + 1) << 12; + + return cal_dsm(pll, num, den); +} + +static inline unsigned int dsm(int pll, unsigned int M, unsigned int N, + unsigned int K, unsigned int dsmsel, unsigned int phase_div_en) +{ + if (!dsmsel) + return mash_dsm(pll, M, N, K); + else if (!phase_div_en) + return mash_dsm(pll, M, N, K); + else + return ssff_dsm_2(pll, M, N, K); +} + +static inline unsigned int ltq_get_pll0_fosc(void) +{ + if (CGU_PLL0_BYPASS) + return get_input_clock(0); + else + return !CGU_PLL0_CFG_FRAC_EN + ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, + CGU_PLL0_CFG_DSMSEL, + CGU_PLL0_PHASE_DIVIDER_ENABLE) + : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, + CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL, + CGU_PLL0_PHASE_DIVIDER_ENABLE); +} + +static unsigned int ltq_get_pll0_fdiv(void) +{ + unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1; + + return (ltq_get_pll0_fosc() + (div >> 1)) / div; +} + +unsigned long ltq_danube_io_region_clock(void) +{ + unsigned int ret = ltq_get_pll0_fosc(); + + switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0x3) { + default: + case 0: + return (ret + 1) / 2; + case 1: + return (ret * 2 + 2) / 5; + case 2: + return (ret + 1) / 3; + case 3: + return (ret + 2) / 4; + } +} + +unsigned long ltq_danube_fpi_bus_clock(int fpi) +{ + unsigned long ret = ltq_danube_io_region_clock(); + + if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL)) + ret >>= 1; + return ret; +} + +unsigned long ltq_danube_fpi_hz(void) +{ + unsigned long ddr_clock = DDR_HZ; + + if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40) + return ddr_clock >> 1; + return ddr_clock; +} + +unsigned long ltq_danube_cpu_hz(void) +{ + switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) { + case 0: + return CLOCK_333M; + case 4: + return DDR_HZ; + case 8: + return DDR_HZ << 1; + default: + return DDR_HZ >> 1; + } +} + +unsigned long ltq_ar9_sys_hz(void) +{ + if (((ltq_cgu_r32(LTQ_CGU_SYS) >> 3) & 0x3) == 0x2) + return CLOCK_393M; + return CLOCK_333M; +} + +unsigned long ltq_ar9_fpi_hz(void) +{ + unsigned long sys = ltq_ar9_sys_hz(); + + if (ltq_cgu_r32(LTQ_CGU_SYS) & BIT(0)) + return sys; + return sys >> 1; +} + +unsigned long ltq_ar9_cpu_hz(void) +{ + if (ltq_cgu_r32(LTQ_CGU_SYS) & BIT(2)) + return ltq_ar9_fpi_hz(); + else + return ltq_ar9_sys_hz(); +} + +unsigned long ltq_vr9_cpu_hz(void) +{ + unsigned int cpu_sel; + unsigned long clk; + + cpu_sel = (ltq_cgu_r32(LTQ_CGU_SYS_VR9) >> 4) & 0xf; + + switch (cpu_sel) { + case 0: + clk = CLOCK_600M; + break; + case 1: + clk = CLOCK_500M; + break; + case 2: + clk = CLOCK_393M; + break; + case 3: + clk = CLOCK_333M; + break; + case 5: + case 6: + clk = CLOCK_196_608M; + break; + case 7: + clk = CLOCK_167M; + break; + case 4: + case 8: + case 9: + clk = CLOCK_125M; + break; + default: + clk = 0; + break; + } + + return clk; +} + +unsigned long ltq_vr9_fpi_hz(void) +{ + unsigned int ocp_sel, cpu_clk; + unsigned long clk; + + cpu_clk = ltq_vr9_cpu_hz(); + ocp_sel = ltq_cgu_r32(LTQ_CGU_SYS_VR9) & 0x3; + + switch (ocp_sel) { + case 0: + /* OCP ratio 1 */ + clk = cpu_clk; + break; + case 2: + /* OCP ratio 2 */ + clk = cpu_clk / 2; + break; + case 3: + /* OCP ratio 2.5 */ + clk = (cpu_clk * 2) / 5; + break; + case 4: + /* OCP ratio 3 */ + clk = cpu_clk / 3; + break; + default: + clk = 0; + break; + } + + return clk; +} + +unsigned long ltq_vr9_fpi_bus_clock(int fpi) +{ + return ltq_vr9_fpi_hz(); +} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-ifxhcd.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-ifxhcd.c new file mode 100644 index 0000000000..ea08a359ff --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-ifxhcd.c @@ -0,0 +1,45 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Copyright (C) 2012 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +static u64 dmamask = (u32)0x1fffffff; + +static struct platform_device platform_dev = { + .name = "ifxusb_hcd", + .dev.dma_mask = &dmamask, +}; + +int __init +xway_register_hcd(int *pins) +{ + platform_dev.dev.platform_data = pins; + return platform_device_register(&platform_dev); +} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-ifxhcd.h b/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-ifxhcd.h new file mode 100644 index 0000000000..18b3d2dae4 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/xway/dev-ifxhcd.h @@ -0,0 +1,17 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Copyright (C) 2012 John Crispin + */ + +#ifndef _LTQ_DEV_HCD_H__ +#define _LTQ_DEV_HCD_H__ + +#include + +extern void __init xway_register_hcd(int *pin); + +#endif diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/gptu.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/gptu.c new file mode 100644 index 0000000000..ac82c37eba --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/xway/gptu.c @@ -0,0 +1,176 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2012 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "../clk.h" + +#include "../devices.h" + +#define ltq_gptu_w32(x, y) ltq_w32((x), ltq_gptu_membase + (y)) +#define ltq_gptu_r32(x) ltq_r32(ltq_gptu_membase + (x)) + + +/* the magic ID byte of the core */ +#define GPTU_MAGIC 0x59 +/* clock control register */ +#define GPTU_CLC 0x00 +/* id register */ +#define GPTU_ID 0x08 +/* interrupt node enable */ +#define GPTU_IRNEN 0xf4 +/* interrupt control register */ +#define GPTU_IRCR 0xf8 +/* interrupt capture register */ +#define GPTU_IRNCR 0xfc +/* there are 3 identical blocks of 2 timers. calculate register offsets */ +#define GPTU_SHIFT(x) (x % 2 ? 4 : 0) +#define GPTU_BASE(x) (((x >> 1) * 0x20) + 0x10) +/* timer control register */ +#define GPTU_CON(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x00) +/* timer auto reload register */ +#define GPTU_RUN(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x08) +/* timer manual reload register */ +#define GPTU_RLD(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x10) +/* timer count register */ +#define GPTU_CNT(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x18) + +/* GPTU_CON(x) */ +#define CON_CNT BIT(2) +#define CON_EDGE_FALL BIT(7) +#define CON_SYNC BIT(8) +#define CON_CLK_INT BIT(10) + +/* GPTU_RUN(x) */ +#define RUN_SEN BIT(0) +#define RUN_RL BIT(2) + +/* set clock to runmode */ +#define CLC_RMC BIT(8) +/* bring core out of suspend */ +#define CLC_SUSPEND BIT(4) +/* the disable bit */ +#define CLC_DISABLE BIT(0) + +#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) + +enum gptu_timer { + TIMER1A = 0, + TIMER1B, + TIMER2A, + TIMER2B, + TIMER3A, + TIMER3B +}; + +static struct resource ltq_gptu_resource = + MEM_RES("GPTU", LTQ_GPTU_BASE_ADDR, LTQ_GPTU_SIZE); + +static void __iomem *ltq_gptu_membase; + +static irqreturn_t timer_irq_handler(int irq, void *priv) +{ + int timer = irq - TIMER_INTERRUPT; + ltq_gptu_w32(1 << timer, GPTU_IRNCR); + return IRQ_HANDLED; +} + +static void gptu_hwinit(void) +{ + struct clk *clk = clk_get_sys("ltq_gptu", NULL); + clk_enable(clk); + ltq_gptu_w32(0x00, GPTU_IRNEN); + ltq_gptu_w32(0xff, GPTU_IRNCR); + ltq_gptu_w32(CLC_RMC | CLC_SUSPEND, GPTU_CLC); +} + +static void gptu_hwexit(void) +{ + ltq_gptu_w32(0x00, GPTU_IRNEN); + ltq_gptu_w32(0xff, GPTU_IRNCR); + ltq_gptu_w32(CLC_DISABLE, GPTU_CLC); +} + +static int ltq_gptu_enable(struct clk *clk) +{ + int ret = request_irq(TIMER_INTERRUPT + clk->bits, timer_irq_handler, + IRQF_TIMER, "timer", NULL); + if (ret) { + pr_err("gptu: failed to request irq\n"); + return ret; + } + + ltq_gptu_w32(CON_CNT | CON_EDGE_FALL | CON_SYNC | CON_CLK_INT, + GPTU_CON(clk->bits)); + ltq_gptu_w32(1, GPTU_RLD(clk->bits)); + ltq_gptu_w32(ltq_gptu_r32(GPTU_IRNEN) | clk->bits, GPTU_IRNEN); + ltq_gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits)); + return 0; +} + +static void ltq_gptu_disable(struct clk *clk) +{ + ltq_gptu_w32(0, GPTU_RUN(clk->bits)); + ltq_gptu_w32(0, GPTU_CON(clk->bits)); + ltq_gptu_w32(0, GPTU_RLD(clk->bits)); + ltq_gptu_w32(ltq_gptu_r32(GPTU_IRNEN) & ~clk->bits, GPTU_IRNEN); + free_irq(TIMER_INTERRUPT + clk->bits, NULL); +} + +static inline void clkdev_add_gptu(const char *con, unsigned int timer) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + + clk->cl.dev_id = "ltq_gptu"; + clk->cl.con_id = con; + clk->cl.clk = clk; + clk->enable = ltq_gptu_enable; + clk->disable = ltq_gptu_disable; + clk->bits = timer; + clkdev_add(&clk->cl); +} + +static int __init gptu_setup(void) +{ + /* remap gptu register range */ + ltq_gptu_membase = ltq_remap_resource(<q_gptu_resource); + if (!ltq_gptu_membase) + panic("Failed to remap gptu memory"); + + /* power up the core */ + gptu_hwinit(); + + /* the gptu has a ID register */ + if (((ltq_gptu_r32(GPTU_ID) >> 8) & 0xff) != GPTU_MAGIC) { + pr_err("gptu: failed to find magic\n"); + gptu_hwexit(); + return -ENAVAIL; + } + + /* register the clocks */ + clkdev_add_gptu("timer1a", TIMER1A); + clkdev_add_gptu("timer1b", TIMER1B); + clkdev_add_gptu("timer2a", TIMER2A); + clkdev_add_gptu("timer2b", TIMER2B); + clkdev_add_gptu("timer3a", TIMER3A); + clkdev_add_gptu("timer3b", TIMER3B); + + pr_info("gptu: 6 timers loaded\n"); + + return 0; +} + +arch_initcall(gptu_setup); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-easy50601.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-easy50601.c deleted file mode 100644 index e76c29a99c..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-easy50601.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include -#include -#include -#include - -#include - -#include "../machtypes.h" -#include "devices.h" - -static struct mtd_partition easy50601_partitions[] = { - { - .name = "uboot", - .offset = 0x0, - .size = 0x10000, - }, - { - .name = "uboot_env", - .offset = 0x10000, - .size = 0x10000, - }, - { - .name = "linux", - .offset = 0x20000, - .size = 0x3d0000, - }, -}; - -static struct physmap_flash_data easy50601_flash_data = { - .nr_parts = ARRAY_SIZE(easy50601_partitions), - .parts = easy50601_partitions, -}; - -static struct ltq_eth_data ltq_eth_data = { - .mii_mode = -1, /* use EPHY */ -}; - -static void __init -easy50601_init(void) -{ - ltq_register_nor(&easy50601_flash_data); - ltq_register_etop(<q_eth_data); -} - -MIPS_MACHINE(LTQ_MACH_EASY50601, - "EASY50601", - "EASY50601 Eval Board", - easy50601_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-easy50712.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-easy50712.c deleted file mode 100644 index 581aa76831..0000000000 --- a/target/linux/lantiq/files/arch/mips/lantiq/xway/mach-easy50712.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - * - * Copyright (C) 2010 John Crispin - */ - -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "../machtypes.h" -#include "devices.h" - -static struct mtd_partition easy50712_partitions[] = { - { - .name = "uboot", - .offset = 0x0, - .size = 0x10000, - }, - { - .name = "uboot_env", - .offset = 0x10000, - .size = 0x10000, - }, - { - .name = "linux", - .offset = 0x20000, - .size = 0x3d0000, - }, -}; - -static struct physmap_flash_data easy50712_flash_data = { - .nr_parts = ARRAY_SIZE(easy50712_partitions), - .parts = easy50712_partitions, -}; - -static struct ltq_pci_data ltq_pci_data = { - .clock = PCI_CLOCK_INT, - .gpio = PCI_GNT1 | PCI_REQ1, - .irq = { - [14] = INT_NUM_IM0_IRL0 + 22, - }, -}; - -static struct ltq_eth_data ltq_eth_data = { - .mii_mode = PHY_INTERFACE_MODE_MII, -}; - -static void __init -easy50712_init(void) -{ - ltq_register_gpio_stp(); - ltq_register_nor(&easy50712_flash_data); - ltq_register_pci(<q_pci_data); - ltq_register_etop(<q_eth_data); - ltq_register_tapi(); -} - -MIPS_MACHINE(LTQ_MACH_EASY50712, - "EASY50712", - "EASY50712 Eval Board", - easy50712_init); diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/nand.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/nand.c new file mode 100644 index 0000000000..9ab91d8819 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/xway/nand.c @@ -0,0 +1,216 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include "devices.h" + +/* nand registers */ +#define LTQ_EBU_NAND_WAIT 0xB4 +#define LTQ_EBU_NAND_ECC0 0xB8 +#define LTQ_EBU_NAND_ECC_AC 0xBC +#define LTQ_EBU_NAND_CON 0xB0 +#define LTQ_EBU_ADDSEL1 0x24 + +/* gpio definitions */ +#define PIN_ALE 13 +#define PIN_CLE 24 +#define PIN_CS1 23 +#define PIN_RDY 48 /* NFLASH_READY */ +#define PIN_RD 49 /* NFLASH_READ_N */ + +#define NAND_CMD_ALE (1 << 2) +#define NAND_CMD_CLE (1 << 3) +#define NAND_CMD_CS (1 << 4) +#define NAND_WRITE_CMD_RESET 0xff +#define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE) +#define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE) +#define NAND_WRITE_DATA (NAND_CMD_CS) +#define NAND_READ_DATA (NAND_CMD_CS) +#define NAND_WAIT_WR_C (1 << 3) +#define NAND_WAIT_RD (0x1) + +#define ADDSEL1_MASK(x) (x << 4) +#define ADDSEL1_REGEN 1 +#define BUSCON1_SETUP (1 << 22) +#define BUSCON1_BCGEN_RES (0x3 << 12) +#define BUSCON1_WAITWRC2 (2 << 8) +#define BUSCON1_WAITRDC2 (2 << 6) +#define BUSCON1_HOLDC1 (1 << 4) +#define BUSCON1_RECOVC1 (1 << 2) +#define BUSCON1_CMULT4 1 +#define NAND_CON_NANDM 1 +#define NAND_CON_CSMUX (1 << 1) +#define NAND_CON_CS_P (1 << 4) +#define NAND_CON_SE_P (1 << 5) +#define NAND_CON_WP_P (1 << 6) +#define NAND_CON_PRE_P (1 << 7) +#define NAND_CON_IN_CS0 0 +#define NAND_CON_OUT_CS0 0 +#define NAND_CON_IN_CS1 (1 << 8) +#define NAND_CON_OUT_CS1 (1 << 10) +#define NAND_CON_CE (1 << 20) + +#define NAND_BASE_ADDRESS (KSEG1 | 0x14000000) + +static const char *part_probes[] = { "cmdlinepart", NULL }; + +static void xway_select_chip(struct mtd_info *mtd, int chip) +{ + switch (chip) { + case -1: + ltq_ebu_w32_mask(NAND_CON_CE, 0, LTQ_EBU_NAND_CON); + ltq_ebu_w32_mask(NAND_CON_NANDM, 0, LTQ_EBU_NAND_CON); + break; + case 0: + ltq_ebu_w32_mask(0, NAND_CON_NANDM, LTQ_EBU_NAND_CON); + ltq_ebu_w32_mask(0, NAND_CON_CE, LTQ_EBU_NAND_CON); + /* reset the nand chip */ + while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; + ltq_w32(NAND_WRITE_CMD_RESET, + ((u32 *) (NAND_BASE_ADDRESS | NAND_WRITE_CMD))); + break; + default: + BUG(); + } +} + +static void xway_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + + if (ctrl & NAND_CTRL_CHANGE) { + if (ctrl & NAND_CLE) + this->IO_ADDR_W = (void __iomem *) + (NAND_BASE_ADDRESS | NAND_WRITE_CMD); + else if (ctrl & NAND_ALE) + this->IO_ADDR_W = (void __iomem *) + (NAND_BASE_ADDRESS | NAND_WRITE_ADDR); + } + + if (data != NAND_CMD_NONE) { + *(volatile u8*) ((u32) this->IO_ADDR_W) = data; + while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; + } +} + +static int xway_dev_ready(struct mtd_info *mtd) +{ + return ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_RD; +} + +void nand_write(unsigned int addr, unsigned int val) +{ + ltq_w32(val, ((u32 *) (NAND_BASE_ADDRESS | addr))); + while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; +} + +unsigned char xway_read_byte(struct mtd_info *mtd) +{ + return ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA))); +} + +static void xway_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) + { + unsigned char res8 = ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA))); + buf[i] = res8; + } +} + +static void xway_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) +{ + int i; + + for (i = 0; i < len; i++) + { + ltq_w8(buf[i], ((u32*)(NAND_BASE_ADDRESS | (NAND_WRITE_DATA)))); + while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0); + } +} + +int xway_probe(struct platform_device *pdev) +{ + /* might need this later ? + ltq_gpio_request(PIN_CS1, 2, 1, "NAND_CS1"); + */ + ltq_gpio_request(&pdev->dev, PIN_CLE, 2, 1, "NAND_CLE"); + ltq_gpio_request(&pdev->dev, PIN_ALE, 2, 1, "NAND_ALE"); + if (ltq_is_ar9() || ltq_is_vr9()) { + ltq_gpio_request(&pdev->dev, PIN_RDY, 2, 0, "NAND_BSY"); + ltq_gpio_request(&pdev->dev, PIN_RD, 2, 1, "NAND_RD"); + } + + ltq_ebu_w32((NAND_BASE_ADDRESS & 0x1fffff00) + | ADDSEL1_MASK(3) | ADDSEL1_REGEN, LTQ_EBU_ADDSEL1); + + ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2 + | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1 + | BUSCON1_CMULT4, LTQ_EBU_BUSCON1); + + ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P + | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P + | NAND_CON_IN_CS0 | NAND_CON_OUT_CS0, LTQ_EBU_NAND_CON); + + ltq_w32(NAND_WRITE_CMD_RESET, + ((u32 *) (NAND_BASE_ADDRESS | NAND_WRITE_CMD))); + while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) + ; + + return 0; +} + +static struct platform_nand_data falcon_flash_nand_data = { + .chip = { + .nr_chips = 1, + .chip_delay = 30, + .part_probe_types = part_probes, + }, + .ctrl = { + .probe = xway_probe, + .cmd_ctrl = xway_cmd_ctrl, + .dev_ready = xway_dev_ready, + .select_chip = xway_select_chip, + .read_byte = xway_read_byte, + .read_buf = xway_read_buf, + .write_buf = xway_write_buf, + } +}; + +static struct resource ltq_nand_res = + MEM_RES("nand", 0x14000000, 0x7ffffff); + +static struct platform_device ltq_flash_nand = { + .name = "gen_nand", + .id = -1, + .num_resources = 1, + .resource = <q_nand_res, + .dev = { + .platform_data = &falcon_flash_nand_data, + }, +}; + +void __init xway_register_nand(struct mtd_partition *parts, int count) +{ + falcon_flash_nand_data.chip.partitions = parts; + falcon_flash_nand_data.chip.nr_partitions = count; + platform_device_register(<q_flash_nand); +} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/prom.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/prom.c new file mode 100644 index 0000000000..f776d5a914 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/xway/prom.c @@ -0,0 +1,110 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 John Crispin + */ + +#include +#include +#include +#include + +#include + +#include "../prom.h" +#include "devices.h" + +#define SOC_DANUBE "Danube" +#define SOC_TWINPASS "Twinpass" +#define SOC_AMAZON_SE "Amazon_SE" +#define SOC_AR9 "AR9" +#define SOC_GR9 "GR9" +#define SOC_VR9 "VR9" + +#define PART_SHIFT 12 +#define PART_MASK 0x0FFFFFFF +#define REV_SHIFT 28 +#define REV_MASK 0xF0000000 + + +void __init ltq_soc_detect(struct ltq_soc_info *i) +{ + i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; + i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; + sprintf(i->rev_type, "1.%d", i->rev); + switch (i->partnum) { + case SOC_ID_DANUBE1: + case SOC_ID_DANUBE2: + i->name = SOC_DANUBE; + i->type = SOC_TYPE_DANUBE; + break; + + case SOC_ID_TWINPASS: + i->name = SOC_TWINPASS; + i->type = SOC_TYPE_DANUBE; + break; + + case SOC_ID_ARX188: + case SOC_ID_ARX168_1: + case SOC_ID_ARX168_2: + case SOC_ID_ARX182: + i->name = SOC_AR9; + i->type = SOC_TYPE_AR9; + break; + + case SOC_ID_GRX188: + case SOC_ID_GRX168: + i->name = SOC_GR9; + i->type = SOC_TYPE_AR9; + break; + + case SOC_ID_AMAZON_SE_1: + case SOC_ID_AMAZON_SE_2: + i->name = SOC_AMAZON_SE; + i->type = SOC_TYPE_AMAZON_SE; +#ifdef CONFIG_PCI + panic("ase is only supported for non pci kernels"); +#endif + break; + + case SOC_ID_VRX282: + case SOC_ID_VRX268: + case SOC_ID_VRX288: + i->name = SOC_VR9; + i->type = SOC_TYPE_VR9_1; + break; + + case SOC_ID_GRX268: + case SOC_ID_GRX288: + i->name = SOC_GR9; + i->type = SOC_TYPE_VR9_1; + break; + + case SOC_ID_VRX268_2: + case SOC_ID_VRX288_2: + i->name = SOC_VR9; + i->type = SOC_TYPE_VR9_2; + break; + + case SOC_ID_GRX282_2: + case SOC_ID_GRX288_2: + i->name = SOC_GR9; + i->type = SOC_TYPE_VR9_2; + + default: + unreachable(); + break; + } +} + +void __init ltq_soc_setup(void) +{ + if (ltq_is_ase()) + ltq_register_ase_asc(); + else + ltq_register_asc(1); + ltq_register_gpio(); + ltq_register_wdt(); +} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/sysctrl.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/sysctrl.c new file mode 100644 index 0000000000..de4ce8f1cb --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/xway/sysctrl.c @@ -0,0 +1,283 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include + +#include + +#include "../clk.h" +#include "../devices.h" + +/* clock control register */ +#define CGU_IFCCR 0x0018 +/* system clock register */ +#define CGU_SYS 0x0010 +/* pci control register */ +#define CGU_PCICR 0x0034 +/* ephy configuration register */ +#define CGU_EPHY 0x10 +/* power control register */ +#define PMU_PWDCR 0x1C +/* power status register */ +#define PMU_PWDSR 0x20 +/* power control register */ +#define PMU_PWDCR1 0x24 +/* power status register */ +#define PMU_PWDSR1 0x28 +/* power control register */ +#define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR)) +/* power status register */ +#define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR)) + +/* PMU - power management unit */ +#define PMU_USB0_P BIT(0) +#define PMU_PCI BIT(4) +#define PMU_DMA BIT(5) +#define PMU_USB0 BIT(6) +#define PMU_EPHY BIT(7) /* ase */ +#define PMU_SPI BIT(8) +#define PMU_DFE BIT(9) +#define PMU_EBU BIT(10) +#define PMU_STP BIT(11) +#define PMU_GPT BIT(12) +#define PMU_PPE BIT(13) +#define PMU_AHBS BIT(13) /* vr9 */ +#define PMU_FPI BIT(14) +#define PMU_AHBM BIT(15) +#define PMU_PPE_QSB BIT(18) +#define PMU_PPE_SLL01 BIT(19) +#define PMU_PPE_TC BIT(21) +#define PMU_PPE_EMA BIT(22) +#define PMU_PPE_DPLUM BIT(23) +#define PMU_PPE_DPLUS BIT(24) +#define PMU_USB1_P BIT(26) +#define PMU_USB1 BIT(27) +#define PMU_SWITCH BIT(28) +#define PMU_PPE_TOP BIT(29) +#define PMU_GPHY BIT(30) +#define PMU_PCIE_CLK BIT(31) + +#define PMU1_PCIE_PHY BIT(0) +#define PMU1_PCIE_CTL BIT(1) +#define PMU1_PCIE_PDI BIT(4) +#define PMU1_PCIE_MSI BIT(5) + +#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y)) +#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x)) + +static struct resource ltq_cgu_resource = + MEM_RES("cgu", LTQ_CGU_BASE_ADDR, LTQ_CGU_SIZE); + +static struct resource ltq_pmu_resource = + MEM_RES("pmu", LTQ_PMU_BASE_ADDR, LTQ_PMU_SIZE); + +static struct resource ltq_ebu_resource = + MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE); + +void __iomem *ltq_cgu_membase; +void __iomem *ltq_ebu_membase; +static void __iomem *ltq_pmu_membase; + +static int ltq_cgu_enable(struct clk *clk) +{ + ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | clk->bits, CGU_IFCCR); + return 0; +} + +static void ltq_cgu_disable(struct clk *clk) +{ + ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~clk->bits, CGU_IFCCR); +} + +static int ltq_pmu_enable(struct clk *clk) +{ + int err = 1000000; + + ltq_pmu_w32(ltq_pmu_r32(PWDCR(clk->module)) & ~clk->bits, + PWDCR(clk->module)); + do {} while (--err && (ltq_pmu_r32(PWDSR(clk->module)) & clk->bits)); + + if (!err) + panic("activating PMU module failed!\n"); + + return 0; +} + +static void ltq_pmu_disable(struct clk *clk) +{ + ltq_pmu_w32(ltq_pmu_r32(PWDCR(clk->module)) | clk->bits, + PWDCR(clk->module)); +} + +static int ltq_pci_enable(struct clk *clk) +{ + unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR); + /* set clock bus speed */ + if (ltq_is_ar9()) { + ifccr &= ~0x1f00000; + if (clk->rate == CLOCK_33M) + ifccr |= 0xe00000; + else + ifccr |= 0x700000; /* 62.5M */ + } else { + ifccr &= ~0xf00000; + if (clk->rate == CLOCK_33M) + ifccr |= 0x800000; + else + ifccr |= 0x400000; /* 62.5M */ + } + ltq_cgu_w32(ifccr, CGU_IFCCR); + return 0; +} + +static int ltq_pci_ext_enable(struct clk *clk) +{ + /* enable external pci clock */ + ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~(1 << 16), + CGU_IFCCR); + ltq_cgu_w32((1 << 30), CGU_PCICR); + return 0; +} + +static void ltq_pci_ext_disable(struct clk *clk) +{ + /* disable external pci clock (internal) */ + ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16), + CGU_IFCCR); + ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR); +} + +/* manage the clock gates via PMU */ +static inline void clkdev_add_pmu(const char *dev, const char *con, + unsigned int module, unsigned int bits) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + + clk->cl.dev_id = dev; + clk->cl.con_id = con; + clk->cl.clk = clk; + clk->enable = ltq_pmu_enable; + clk->disable = ltq_pmu_disable; + clk->module = module; + clk->bits = bits; + clkdev_add(&clk->cl); +} + +/* manage the clock generator */ +static inline void clkdev_add_cgu(const char *dev, const char *con, + unsigned int bits) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + + clk->cl.dev_id = dev; + clk->cl.con_id = con; + clk->cl.clk = clk; + clk->enable = ltq_cgu_enable; + clk->disable = ltq_cgu_disable; + clk->bits = bits; + clkdev_add(&clk->cl); +} + +/* pci needs its own enable function */ +static inline void clkdev_add_pci(void) +{ + struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); + struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL); + + /* main pci clock */ + clk->cl.dev_id = "ltq_pci"; + clk->cl.con_id = NULL; + clk->cl.clk = clk; + clk->rate = CLOCK_33M; + clk->enable = ltq_pci_enable; + clk->disable = ltq_pmu_disable; + clk->module = 0; + clk->bits = PMU_PCI; + clkdev_add(&clk->cl); + + /* use internal/external bus clock */ + clk_ext->cl.dev_id = "ltq_pci"; + clk_ext->cl.con_id = "external"; + clk_ext->cl.clk = clk_ext; + clk_ext->enable = ltq_pci_ext_enable; + clk_ext->disable = ltq_pci_ext_disable; + clkdev_add(&clk_ext->cl); + +} + +void __init ltq_soc_init(void) +{ + ltq_pmu_membase = ltq_remap_resource(<q_pmu_resource); + if (!ltq_pmu_membase) + panic("Failed to remap pmu memory\n"); + + ltq_cgu_membase = ltq_remap_resource(<q_cgu_resource); + if (!ltq_cgu_membase) + panic("Failed to remap cgu memory\n"); + + ltq_ebu_membase = ltq_remap_resource(<q_ebu_resource); + if (!ltq_ebu_membase) + panic("Failed to remap ebu memory\n"); + + /* make sure to unprotect the memory region where flash is located */ + ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); + + /* add our clocks */ + clkdev_add_pmu("ltq_fpi", NULL, 0, PMU_FPI); + clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA); + clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP); + clkdev_add_pmu("ltq_spi.0", NULL, 0, PMU_SPI); + clkdev_add_pmu("ltq_gptu", NULL, 0, PMU_GPT); + clkdev_add_pmu("ltq_ebu", NULL, 0, PMU_EBU); + if (!ltq_is_vr9()) + clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE); + if (!ltq_is_ase()) + clkdev_add_pci(); + if (ltq_is_ase()) { + if (ltq_cgu_r32(CGU_SYS) & (1 << 5)) + clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M); + else + clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M); + clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY), + clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY); + clkdev_add_pmu("ltq_dsl", NULL, 0, + PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | + PMU_AHBS | PMU_DFE); + } else if (ltq_is_vr9()) { + clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(), + ltq_vr9_fpi_hz()); + clkdev_add_pmu("ltq_pcie", "phy", 1, PMU1_PCIE_PHY); + clkdev_add_pmu("ltq_pcie", "bus", 0, PMU_PCIE_CLK); + clkdev_add_pmu("ltq_pcie", "msi", 1, PMU1_PCIE_MSI); + clkdev_add_pmu("ltq_pcie", "pdi", 1, PMU1_PCIE_PDI); + clkdev_add_pmu("ltq_pcie", "ctl", 1, PMU1_PCIE_CTL); + clkdev_add_pmu("ltq_pcie", "ahb", 0, PMU_AHBM | PMU_AHBS); + clkdev_add_pmu("usb0", NULL, 0, PMU_USB0 | PMU_USB0_P); + clkdev_add_pmu("usb1", NULL, 0, PMU_USB1 | PMU_USB1_P); + clkdev_add_pmu("ltq_vrx200", NULL, 0, + PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM | + PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | + PMU_PPE_QSB); + clkdev_add_pmu("ltq_dsl", NULL, 0, PMU_DFE | PMU_AHBS); + } else if (ltq_is_ar9()) { + clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), + ltq_ar9_fpi_hz()); + clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH); + clkdev_add_pmu("ltq_dsl", NULL, 0, + PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | + PMU_PPE_QSB | PMU_AHBS | PMU_DFE); + } else { + clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(), + ltq_danube_io_region_clock()); + clkdev_add_pmu("ltq_dsl", NULL, 0, + PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | + PMU_PPE_QSB | PMU_AHBS | PMU_DFE); + } +} diff --git a/target/linux/lantiq/files/arch/mips/lantiq/xway/timer.c b/target/linux/lantiq/files/arch/mips/lantiq/xway/timer.c new file mode 100644 index 0000000000..9794c87c73 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/lantiq/xway/timer.c @@ -0,0 +1,846 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "../clk.h" + +#include +#include +#include + +#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6 + +#ifdef TIMER1A +#define FIRST_TIMER TIMER1A +#else +#define FIRST_TIMER 2 +#endif + +/* + * GPTC divider is set or not. + */ +#define GPTU_CLC_RMC_IS_SET 0 + +/* + * Timer Interrupt (IRQ) + */ +/* Must be adjusted when ICU driver is available */ +#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) + +/* + * Bits Operation + */ +#define GET_BITS(x, msb, lsb) \ + (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) +#define SET_BITS(x, msb, lsb, value) \ + (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \ + (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) + +/* + * GPTU Register Mapping + */ +#define LQ_GPTU (KSEG1 + 0x1E100A00) +#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000)) +#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008)) +#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ +#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ +#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ +#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ +#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4)) +#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8)) +#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC)) + +/* + * Clock Control Register + */ +#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16) +#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8) +#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5)) +#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3)) +#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2)) +#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1)) +#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0)) + +#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value)) +#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value)) +#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0) +#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0) +#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0) +#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0) +#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0) + +/* + * ID Register + */ +#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8) +#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5) +#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0) + +/* + * Control Register of Timer/Counter nX + * n is the index of block (1 based index) + * X is either A or B + */ +#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10)) +#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9)) +#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8)) +#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6) +#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5)) +#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */ +#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3)) +#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2)) +#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1)) +#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0)) + +#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10)) +#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0) +#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0) +#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value)) +#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0) +#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0) +#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0) +#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0) +#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0) + +#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0) +#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0) +#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0) + +#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) +#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) + +#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001) +#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002) +#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004) +#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008) +#define TIMER_FLAG_NONE_EDGE 0x0000 +#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030) +#define TIMER_FLAG_REAL 0x0000 +#define TIMER_FLAG_INVERT 0x0040 +#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040) +#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070) +#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080) +#define TIMER_FLAG_CALLBACK_IN_HB 0x0200 +#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300) +#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000) + +struct timer_dev_timer { + unsigned int f_irq_on; + unsigned int irq; + unsigned int flag; + unsigned long arg1; + unsigned long arg2; +}; + +struct timer_dev { + struct mutex gptu_mutex; + unsigned int number_of_timers; + unsigned int occupation; + unsigned int f_gptu_on; + struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2]; +}; + +unsigned long ltq_danube_fpi_bus_clock(int fpi); +unsigned long ltq_vr9_fpi_bus_clock(int fpi); + +unsigned int ltq_get_fpi_bus_clock(int fpi) { + if (ltq_is_ase()) + return CLOCK_133M; + else if (ltq_is_vr9()) + return ltq_vr9_fpi_bus_clock(fpi); + + return ltq_danube_fpi_bus_clock(fpi); +} + + +static long gptu_ioctl(struct file *, unsigned int, unsigned long); +static int gptu_open(struct inode *, struct file *); +static int gptu_release(struct inode *, struct file *); + +static struct file_operations gptu_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = gptu_ioctl, + .open = gptu_open, + .release = gptu_release +}; + +static struct miscdevice gptu_miscdev = { + .minor = MISC_DYNAMIC_MINOR, + .name = "gptu", + .fops = &gptu_fops, +}; + +static struct timer_dev timer_dev; + +static irqreturn_t timer_irq_handler(int irq, void *p) +{ + unsigned int timer; + unsigned int flag; + struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p; + + timer = irq - TIMER_INTERRUPT; + if (timer < timer_dev.number_of_timers + && dev_timer == &timer_dev.timer[timer]) { + /* Clear interrupt. */ + ltq_w32(1 << timer, LQ_GPTU_IRNCR); + + /* Call user hanler or signal. */ + flag = dev_timer->flag; + if (!(timer & 0x01) + || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { + /* 16-bit timer or timer A of 32-bit timer */ + switch (TIMER_FLAG_MASK_HANDLE(flag)) { + case TIMER_FLAG_CALLBACK_IN_IRQ: + case TIMER_FLAG_CALLBACK_IN_HB: + if (dev_timer->arg1) + (*(timer_callback)dev_timer->arg1)(dev_timer->arg2); + break; + case TIMER_FLAG_SIGNAL: + send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0); + break; + } + } + } + return IRQ_HANDLED; +} + +static inline void lq_enable_gptu(void) +{ + struct clk *clk = clk_get_sys("ltq_gptu", NULL); + clk_enable(clk); + + //ltq_pmu_enable(PMU_GPT); + + /* Set divider as 1, disable write protection for SPEN, enable module. */ + *LQ_GPTU_CLC = + GPTU_CLC_SMC_SET(0x00) | + GPTU_CLC_RMC_SET(0x01) | + GPTU_CLC_FSOE_SET(0) | + GPTU_CLC_SBWE_SET(1) | + GPTU_CLC_EDIS_SET(0) | + GPTU_CLC_SPEN_SET(0) | + GPTU_CLC_DISR_SET(0); +} + +static inline void lq_disable_gptu(void) +{ + struct clk *clk = clk_get_sys("ltq_gptu", NULL); + ltq_w32(0x00, LQ_GPTU_IRNEN); + ltq_w32(0xfff, LQ_GPTU_IRNCR); + + /* Set divider as 0, enable write protection for SPEN, disable module. */ + *LQ_GPTU_CLC = + GPTU_CLC_SMC_SET(0x00) | + GPTU_CLC_RMC_SET(0x00) | + GPTU_CLC_FSOE_SET(0) | + GPTU_CLC_SBWE_SET(0) | + GPTU_CLC_EDIS_SET(0) | + GPTU_CLC_SPEN_SET(0) | + GPTU_CLC_DISR_SET(1); + + clk_enable(clk); +} + +int lq_request_timer(unsigned int timer, unsigned int flag, + unsigned long value, unsigned long arg1, unsigned long arg2) +{ + int ret = 0; + unsigned int con_reg, irnen_reg; + int n, X; + + if (timer >= FIRST_TIMER + timer_dev.number_of_timers) + return -EINVAL; + + printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...", + timer, flag, value); + + if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) + value &= 0xFFFF; + else + timer &= ~0x01; + + mutex_lock(&timer_dev.gptu_mutex); + + /* + * Allocate timer. + */ + if (timer < FIRST_TIMER) { + unsigned int mask; + unsigned int shift; + /* This takes care of TIMER1B which is the only choice for Voice TAPI system */ + unsigned int offset = TIMER2A; + + /* + * Pick up a free timer. + */ + if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { + mask = 1 << offset; + shift = 1; + } else { + mask = 3 << offset; + shift = 2; + } + for (timer = offset; + timer < offset + timer_dev.number_of_timers; + timer += shift, mask <<= shift) + if (!(timer_dev.occupation & mask)) { + timer_dev.occupation |= mask; + break; + } + if (timer >= offset + timer_dev.number_of_timers) { + printk("failed![%d]\n", __LINE__); + mutex_unlock(&timer_dev.gptu_mutex); + return -EINVAL; + } else + ret = timer; + } else { + register unsigned int mask; + + /* + * Check if the requested timer is free. + */ + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; + if ((timer_dev.occupation & mask)) { + printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", + __LINE__, mask, timer_dev.occupation); + mutex_unlock(&timer_dev.gptu_mutex); + return -EBUSY; + } else { + timer_dev.occupation |= mask; + ret = 0; + } + } + + /* + * Prepare control register value. + */ + switch (TIMER_FLAG_MASK_EDGE(flag)) { + default: + case TIMER_FLAG_NONE_EDGE: + con_reg = GPTU_CON_EDGE_SET(0x00); + break; + case TIMER_FLAG_RISE_EDGE: + con_reg = GPTU_CON_EDGE_SET(0x01); + break; + case TIMER_FLAG_FALL_EDGE: + con_reg = GPTU_CON_EDGE_SET(0x02); + break; + case TIMER_FLAG_ANY_EDGE: + con_reg = GPTU_CON_EDGE_SET(0x03); + break; + } + if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER) + con_reg |= + TIMER_FLAG_MASK_SRC(flag) == + TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : + GPTU_CON_SRC_EXT_SET(0); + else + con_reg |= + TIMER_FLAG_MASK_SRC(flag) == + TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : + GPTU_CON_SRC_EG_SET(0); + con_reg |= + TIMER_FLAG_MASK_SYNC(flag) == + TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : + GPTU_CON_SYNC_SET(1); + con_reg |= + TIMER_FLAG_MASK_INVERT(flag) == + TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); + con_reg |= + TIMER_FLAG_MASK_SIZE(flag) == + TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : + GPTU_CON_EXT_SET(1); + con_reg |= + TIMER_FLAG_MASK_STOP(flag) == + TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); + con_reg |= + TIMER_FLAG_MASK_TYPE(flag) == + TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : + GPTU_CON_CNT_SET(1); + con_reg |= + TIMER_FLAG_MASK_DIR(flag) == + TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); + + /* + * Fill up running data. + */ + timer_dev.timer[timer - FIRST_TIMER].flag = flag; + timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1; + timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2; + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) + timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag; + + /* + * Enable GPTU module. + */ + if (!timer_dev.f_gptu_on) { + lq_enable_gptu(); + timer_dev.f_gptu_on = 1; + } + + /* + * Enable IRQ. + */ + if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) { + if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL) + timer_dev.timer[timer - FIRST_TIMER].arg1 = + (unsigned long) find_task_by_vpid((int) arg1); + + irnen_reg = 1 << (timer - FIRST_TIMER); + + if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL + || (TIMER_FLAG_MASK_HANDLE(flag) == + TIMER_FLAG_CALLBACK_IN_IRQ + && timer_dev.timer[timer - FIRST_TIMER].arg1)) { + enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); + timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1; + } + } else + irnen_reg = 0; + + /* + * Write config register, reload value and enable interrupt. + */ + n = timer >> 1; + X = timer & 0x01; + *LQ_GPTU_CON(n, X) = con_reg; + *LQ_GPTU_RELOAD(n, X) = value; + /* printk("reload value = %d\n", (u32)value); */ + *LQ_GPTU_IRNEN |= irnen_reg; + + mutex_unlock(&timer_dev.gptu_mutex); + printk("successful!\n"); + return ret; +} +EXPORT_SYMBOL(lq_request_timer); + +int lq_free_timer(unsigned int timer) +{ + unsigned int flag; + unsigned int mask; + int n, X; + + if (!timer_dev.f_gptu_on) + return -EINVAL; + + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) + return -EINVAL; + + mutex_lock(&timer_dev.gptu_mutex); + + flag = timer_dev.timer[timer - FIRST_TIMER].flag; + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) + timer &= ~0x01; + + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; + if (((timer_dev.occupation & mask) ^ mask)) { + mutex_unlock(&timer_dev.gptu_mutex); + return -EINVAL; + } + + n = timer >> 1; + X = timer & 0x01; + + if (GPTU_CON_EN(n, X)) + *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); + + *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1); + *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1); + + if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) { + disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); + timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0; + } + + timer_dev.occupation &= ~mask; + if (!timer_dev.occupation && timer_dev.f_gptu_on) { + lq_disable_gptu(); + timer_dev.f_gptu_on = 0; + } + + mutex_unlock(&timer_dev.gptu_mutex); + + return 0; +} +EXPORT_SYMBOL(lq_free_timer); + +int lq_start_timer(unsigned int timer, int is_resume) +{ + unsigned int flag; + unsigned int mask; + int n, X; + + if (!timer_dev.f_gptu_on) + return -EINVAL; + + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) + return -EINVAL; + + mutex_lock(&timer_dev.gptu_mutex); + + flag = timer_dev.timer[timer - FIRST_TIMER].flag; + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) + timer &= ~0x01; + + mask = (TIMER_FLAG_MASK_SIZE(flag) == + TIMER_FLAG_16BIT ? 1 : 3) << timer; + if (((timer_dev.occupation & mask) ^ mask)) { + mutex_unlock(&timer_dev.gptu_mutex); + return -EINVAL; + } + + n = timer >> 1; + X = timer & 0x01; + + *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1); + + mutex_unlock(&timer_dev.gptu_mutex); + + return 0; +} +EXPORT_SYMBOL(lq_start_timer); + +int lq_stop_timer(unsigned int timer) +{ + unsigned int flag; + unsigned int mask; + int n, X; + + if (!timer_dev.f_gptu_on) + return -EINVAL; + + if (timer < FIRST_TIMER + || timer >= FIRST_TIMER + timer_dev.number_of_timers) + return -EINVAL; + + mutex_lock(&timer_dev.gptu_mutex); + + flag = timer_dev.timer[timer - FIRST_TIMER].flag; + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) + timer &= ~0x01; + + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; + if (((timer_dev.occupation & mask) ^ mask)) { + mutex_unlock(&timer_dev.gptu_mutex); + return -EINVAL; + } + + n = timer >> 1; + X = timer & 0x01; + + *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); + + mutex_unlock(&timer_dev.gptu_mutex); + + return 0; +} +EXPORT_SYMBOL(lq_stop_timer); + +int lq_reset_counter_flags(u32 timer, u32 flags) +{ + unsigned int oflag; + unsigned int mask, con_reg; + int n, X; + + if (!timer_dev.f_gptu_on) + return -EINVAL; + + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) + return -EINVAL; + + mutex_lock(&timer_dev.gptu_mutex); + + oflag = timer_dev.timer[timer - FIRST_TIMER].flag; + if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT) + timer &= ~0x01; + + mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; + if (((timer_dev.occupation & mask) ^ mask)) { + mutex_unlock(&timer_dev.gptu_mutex); + return -EINVAL; + } + + switch (TIMER_FLAG_MASK_EDGE(flags)) { + default: + case TIMER_FLAG_NONE_EDGE: + con_reg = GPTU_CON_EDGE_SET(0x00); + break; + case TIMER_FLAG_RISE_EDGE: + con_reg = GPTU_CON_EDGE_SET(0x01); + break; + case TIMER_FLAG_FALL_EDGE: + con_reg = GPTU_CON_EDGE_SET(0x02); + break; + case TIMER_FLAG_ANY_EDGE: + con_reg = GPTU_CON_EDGE_SET(0x03); + break; + } + if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER) + con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0); + else + con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0); + con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1); + con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); + con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1); + con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); + con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1); + con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); + + timer_dev.timer[timer - FIRST_TIMER].flag = flags; + if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT) + timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags; + + n = timer >> 1; + X = timer & 0x01; + + *LQ_GPTU_CON(n, X) = con_reg; + smp_wmb(); + printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *LQ_GPTU_CON(n, X)); + mutex_unlock(&timer_dev.gptu_mutex); + return 0; +} +EXPORT_SYMBOL(lq_reset_counter_flags); + +int lq_get_count_value(unsigned int timer, unsigned long *value) +{ + unsigned int flag; + unsigned int mask; + int n, X; + + if (!timer_dev.f_gptu_on) + return -EINVAL; + + if (timer < FIRST_TIMER + || timer >= FIRST_TIMER + timer_dev.number_of_timers) + return -EINVAL; + + mutex_lock(&timer_dev.gptu_mutex); + + flag = timer_dev.timer[timer - FIRST_TIMER].flag; + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) + timer &= ~0x01; + + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; + if (((timer_dev.occupation & mask) ^ mask)) { + mutex_unlock(&timer_dev.gptu_mutex); + return -EINVAL; + } + + n = timer >> 1; + X = timer & 0x01; + + *value = *LQ_GPTU_COUNT(n, X); + + mutex_unlock(&timer_dev.gptu_mutex); + + return 0; +} +EXPORT_SYMBOL(lq_get_count_value); + +u32 lq_cal_divider(unsigned long freq) +{ + u64 module_freq, fpi = ltq_get_fpi_bus_clock(2); + u32 clock_divider = 1; + module_freq = fpi * 1000; + do_div(module_freq, clock_divider * freq); + return module_freq; +} +EXPORT_SYMBOL(lq_cal_divider); + +int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic, + int is_ext_src, unsigned int handle_flag, unsigned long arg1, + unsigned long arg2) +{ + unsigned long divider; + unsigned int flag; + + divider = lq_cal_divider(freq); + if (divider == 0) + return -EINVAL; + flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT) + | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE) + | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC) + | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN + | TIMER_FLAG_MASK_HANDLE(handle_flag); + + printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n", + timer, freq, divider); + return lq_request_timer(timer, flag, divider, arg1, arg2); +} +EXPORT_SYMBOL(lq_set_timer); + +int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload, + unsigned long arg1, unsigned long arg2) +{ + printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload); + return lq_request_timer(timer, flag, reload, arg1, arg2); +} +EXPORT_SYMBOL(lq_set_counter); + +static long gptu_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + int ret; + struct gptu_ioctl_param param; + + if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param))) + return -EFAULT; + copy_from_user(¶m, (void *) arg, sizeof(param)); + + if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER + || GPTU_SET_COUNTER) && param.timer < 2) + || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER) + && !access_ok(VERIFY_WRITE, arg, + sizeof(struct gptu_ioctl_param))) + return -EFAULT; + + switch (cmd) { + case GPTU_REQUEST_TIMER: + ret = lq_request_timer(param.timer, param.flag, param.value, + (unsigned long) param.pid, + (unsigned long) param.sig); + if (ret > 0) { + copy_to_user(&((struct gptu_ioctl_param *) arg)-> + timer, &ret, sizeof(&ret)); + ret = 0; + } + break; + case GPTU_FREE_TIMER: + ret = lq_free_timer(param.timer); + break; + case GPTU_START_TIMER: + ret = lq_start_timer(param.timer, param.flag); + break; + case GPTU_STOP_TIMER: + ret = lq_stop_timer(param.timer); + break; + case GPTU_GET_COUNT_VALUE: + ret = lq_get_count_value(param.timer, ¶m.value); + if (!ret) + copy_to_user(&((struct gptu_ioctl_param *) arg)-> + value, ¶m.value, + sizeof(param.value)); + break; + case GPTU_CALCULATE_DIVIDER: + param.value = lq_cal_divider(param.value); + if (param.value == 0) + ret = -EINVAL; + else { + copy_to_user(&((struct gptu_ioctl_param *) arg)-> + value, ¶m.value, + sizeof(param.value)); + ret = 0; + } + break; + case GPTU_SET_TIMER: + ret = lq_set_timer(param.timer, param.value, + TIMER_FLAG_MASK_STOP(param.flag) != + TIMER_FLAG_ONCE ? 1 : 0, + TIMER_FLAG_MASK_SRC(param.flag) == + TIMER_FLAG_EXT_SRC ? 1 : 0, + TIMER_FLAG_MASK_HANDLE(param.flag) == + TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL : + TIMER_FLAG_NO_HANDLE, + (unsigned long) param.pid, + (unsigned long) param.sig); + if (ret > 0) { + copy_to_user(&((struct gptu_ioctl_param *) arg)-> + timer, &ret, sizeof(&ret)); + ret = 0; + } + break; + case GPTU_SET_COUNTER: + lq_set_counter(param.timer, param.flag, param.value, 0, 0); + if (ret > 0) { + copy_to_user(&((struct gptu_ioctl_param *) arg)-> + timer, &ret, sizeof(&ret)); + ret = 0; + } + break; + default: + ret = -ENOTTY; + } + + return ret; +} + +static int gptu_open(struct inode *inode, struct file *file) +{ + return 0; +} + +static int gptu_release(struct inode *inode, struct file *file) +{ + return 0; +} + +int __init lq_gptu_init(void) +{ + int ret; + unsigned int i; + + ltq_w32(0, LQ_GPTU_IRNEN); + ltq_w32(0xfff, LQ_GPTU_IRNCR); + + memset(&timer_dev, 0, sizeof(timer_dev)); + mutex_init(&timer_dev.gptu_mutex); + + lq_enable_gptu(); + timer_dev.number_of_timers = GPTU_ID_CFG * 2; + lq_disable_gptu(); + if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2) + timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2; + printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers); + + ret = misc_register(&gptu_miscdev); + if (ret) { + printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret); + return ret; + } else { + printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor); + } + + for (i = 0; i < timer_dev.number_of_timers; i++) { + ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]); + if (ret) { + for (; i >= 0; i--) + free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]); + misc_deregister(&gptu_miscdev); + printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret); + return ret; + } else { + timer_dev.timer[i].irq = TIMER_INTERRUPT + i; + disable_irq(timer_dev.timer[i].irq); + printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq); + } + } + + return 0; +} + +void __exit lq_gptu_exit(void) +{ + unsigned int i; + + for (i = 0; i < timer_dev.number_of_timers; i++) { + if (timer_dev.timer[i].f_irq_on) + disable_irq(timer_dev.timer[i].irq); + free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); + } + lq_disable_gptu(); + misc_deregister(&gptu_miscdev); +} + +module_init(lq_gptu_init); +module_exit(lq_gptu_exit); diff --git a/target/linux/lantiq/files/arch/mips/pci/fixup-lantiq-pcie.c b/target/linux/lantiq/files/arch/mips/pci/fixup-lantiq-pcie.c new file mode 100644 index 0000000000..84517dfbc3 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/pci/fixup-lantiq-pcie.c @@ -0,0 +1,81 @@ +/****************************************************************************** +** +** FILE NAME : ifxmips_fixup_pcie.c +** PROJECT : IFX UEIP for VRX200 +** MODULES : PCIe +** +** DATE : 02 Mar 2009 +** AUTHOR : Lei Chuanhua +** DESCRIPTION : PCIe Root Complex Driver +** COPYRIGHT : Copyright (c) 2009 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** HISTORY +** $Version $Date $Author $Comment +** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version +*******************************************************************************/ +/*! + \file ifxmips_fixup_pcie.c + \ingroup IFX_PCIE + \brief PCIe Fixup functions source file +*/ +#include +#include +#include + +#include + +#include "pcie-lantiq.h" + +#define PCI_VENDOR_ID_INFINEON 0x15D1 +#define PCI_DEVICE_ID_INFINEON_DANUBE 0x000F +#define PCI_DEVICE_ID_INFINEON_PCIE 0x0011 +#define PCI_VENDOR_ID_LANTIQ 0x1BEF +#define PCI_DEVICE_ID_LANTIQ_PCIE 0x0011 + + + +static void __devinit +ifx_pcie_fixup_resource(struct pci_dev *dev) +{ + u32 reg; + + IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); + + IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s: fixup host controller %s (%04x:%04x)\n", + __func__, pci_name(dev), dev->vendor, dev->device); + + /* Setup COMMAND register */ + reg = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER /* | + PCI_COMMAND_INTX_DISABLE */| PCI_COMMAND_SERR; + pci_write_config_word(dev, PCI_COMMAND, reg); + IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ifx_pcie_fixup_resource); +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_VENDOR_ID_LANTIQ, ifx_pcie_fixup_resource); + +static void __devinit +ifx_pcie_rc_class_early_fixup(struct pci_dev *dev) +{ + IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); + + if (dev->devfn == PCI_DEVFN(0, 0) && + (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { + + dev->class = (PCI_CLASS_BRIDGE_PCI << 8) | (dev->class & 0xff); + + printk(KERN_INFO "%s: fixed pcie host bridge to pci-pci bridge\n", __func__); + } + IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); +} + +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, + ifx_pcie_rc_class_early_fixup); + +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_DEVICE_ID_LANTIQ_PCIE, + ifx_pcie_rc_class_early_fixup); diff --git a/target/linux/lantiq/files/arch/mips/pci/fixup-lantiq.c b/target/linux/lantiq/files/arch/mips/pci/fixup-lantiq.c new file mode 100644 index 0000000000..daf5ae9e42 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/pci/fixup-lantiq.c @@ -0,0 +1,42 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2012 John Crispin + */ + +#include +#include + +int (*ltqpci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin) = NULL; +int (*ltqpci_plat_arch_init)(struct pci_dev *dev) = NULL; +int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL; +int *ltq_pci_irq_map; + +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + if (ltqpci_plat_arch_init) + return ltqpci_plat_arch_init(dev); + + if (ltqpci_plat_dev_init) + return ltqpci_plat_dev_init(dev); + + return 0; +} + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + if (ltqpci_map_irq) + return ltqpci_map_irq(dev, slot, pin); + if (ltq_pci_irq_map[slot]) { + dev_info(&dev->dev, "SLOT:%d PIN:%d IRQ:%d\n", slot, pin, ltq_pci_irq_map[slot]); + return ltq_pci_irq_map[slot]; + } + printk(KERN_ERR "lq_pci: trying to map irq for unknown slot %d\n", + slot); + + return 0; +} + + diff --git a/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq-msi.c b/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq-msi.c new file mode 100644 index 0000000000..9cbf639bb1 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq-msi.c @@ -0,0 +1,399 @@ +/****************************************************************************** +** +** FILE NAME : ifxmips_pcie_msi.c +** PROJECT : IFX UEIP for VRX200 +** MODULES : PCI MSI sub module +** +** DATE : 02 Mar 2009 +** AUTHOR : Lei Chuanhua +** DESCRIPTION : PCIe MSI Driver +** COPYRIGHT : Copyright (c) 2009 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** HISTORY +** $Date $Author $Comment +** 02 Mar,2009 Lei Chuanhua Initial version +*******************************************************************************/ +/*! + \defgroup IFX_PCIE_MSI MSI OS APIs + \ingroup IFX_PCIE + \brief PCIe bus driver OS interface functions +*/ + +/*! + \file ifxmips_pcie_msi.c + \ingroup IFX_PCIE + \brief PCIe MSI OS interface file +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-lantiq.h" + +#define IFX_MSI_IRQ_NUM 16 +#define SM(_v, _f) (((_v) << _f##_S) & (_f)) + +#define IFX_MSI_PIC_REG_BASE (KSEG1 | 0x1F700000) +#define IFX_PCIE_MSI_IR0 (INT_NUM_IM4_IRL0 + 27) +#define IFX_PCIE_MSI_IR1 (INT_NUM_IM4_IRL0 + 28) +#define IFX_PCIE_MSI_IR2 (INT_NUM_IM4_IRL0 + 29) +#define IFX_PCIE_MSI_IR3 (INT_NUM_IM0_IRL0 + 30) + +#define IFX_MSI_PCI_INT_DISABLE 0x80000000 +#define IFX_MSI_PIC_INT_LINE 0x30000000 +#define IFX_MSI_PIC_MSG_ADDR 0x0FFF0000 +#define IFX_MSI_PIC_MSG_DATA 0x0000FFFF +#define IFX_MSI_PIC_BIG_ENDIAN 1 +#define IFX_MSI_PIC_INT_LINE_S 28 +#define IFX_MSI_PIC_MSG_ADDR_S 16 +#define IFX_MSI_PIC_MSG_DATA_S 0x0 + +enum { + IFX_PCIE_MSI_IDX0 = 0, + IFX_PCIE_MSI_IDX1, + IFX_PCIE_MSI_IDX2, + IFX_PCIE_MSI_IDX3, +}; + +typedef struct ifx_msi_irq_idx { + const int irq; + const int idx; +}ifx_msi_irq_idx_t; + +struct ifx_msi_pic { + volatile u32 pic_table[IFX_MSI_IRQ_NUM]; + volatile u32 pic_endian; /* 0x40 */ +}; +typedef struct ifx_msi_pic *ifx_msi_pic_t; + +typedef struct ifx_msi_irq { + const volatile ifx_msi_pic_t msi_pic_p; + const u32 msi_phy_base; + const ifx_msi_irq_idx_t msi_irq_idx[IFX_MSI_IRQ_NUM]; + /* + * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is + * in use. + */ + u16 msi_free_irq_bitmask; + + /* + * Each bit in msi_multiple_irq_bitmask tells that the device using + * this bit in msi_free_irq_bitmask is also using the next bit. This + * is used so we can disable all of the MSI interrupts when a device + * uses multiple. + */ + u16 msi_multiple_irq_bitmask; +}ifx_msi_irq_t; + +static ifx_msi_irq_t msi_irqs[IFX_PCIE_CORE_NR] = { + { + .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI_PIC_REG_BASE, + .msi_phy_base = PCIE_MSI_PHY_BASE, + .msi_irq_idx = { + {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, + {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, + {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, + {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, + {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, + {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, + {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, + {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, + }, + .msi_free_irq_bitmask = 0, + .msi_multiple_irq_bitmask= 0, + }, +#ifdef CONFIG_IFX_PCIE_2ND_CORE + { + .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI1_PIC_REG_BASE, + .msi_phy_base = PCIE1_MSI_PHY_BASE, + .msi_irq_idx = { + {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, + {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, + {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, + {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, + {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, + {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, + {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, + {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, + }, + .msi_free_irq_bitmask = 0, + .msi_multiple_irq_bitmask= 0, + + }, +#endif /* CONFIG_IFX_PCIE_2ND_CORE */ +}; + +/* + * This lock controls updates to msi_free_irq_bitmask, + * msi_multiple_irq_bitmask and pic register settting + */ +static DEFINE_SPINLOCK(ifx_pcie_msi_lock); + +void pcie_msi_pic_init(int pcie_port) +{ + spin_lock(&ifx_pcie_msi_lock); + msi_irqs[pcie_port].msi_pic_p->pic_endian = IFX_MSI_PIC_BIG_ENDIAN; + spin_unlock(&ifx_pcie_msi_lock); +} + +/** + * \fn int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) + * \brief Called when a driver request MSI interrupts instead of the + * legacy INT A-D. This routine will allocate multiple interrupts + * for MSI devices that support them. A device can override this by + * programming the MSI control bits [6:4] before calling + * pci_enable_msi(). + * + * \param[in] pdev Device requesting MSI interrupts + * \param[in] desc MSI descriptor + * + * \return -EINVAL Invalid pcie root port or invalid msi bit + * \return 0 OK + * \ingroup IFX_PCIE_MSI + */ +int +arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) +{ + int irq, pos; + u16 control; + int irq_idx; + int irq_step; + int configured_private_bits; + int request_private_bits; + struct msi_msg msg; + u16 search_mask; + struct ifx_pci_controller *ctrl = pdev->bus->sysdata; + int pcie_port = ctrl->port; + + IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s %s enter\n", __func__, pci_name(pdev)); + + /* XXX, skip RC MSI itself */ + if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) { + IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s RC itself doesn't use MSI interrupt\n", __func__); + return -EINVAL; + } + + /* + * Read the MSI config to figure out how many IRQs this device + * wants. Most devices only want 1, which will give + * configured_private_bits and request_private_bits equal 0. + */ + pci_read_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &control); + + /* + * If the number of private bits has been configured then use + * that value instead of the requested number. This gives the + * driver the chance to override the number of interrupts + * before calling pci_enable_msi(). + */ + configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4; + if (configured_private_bits == 0) { + /* Nothing is configured, so use the hardware requested size */ + request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1; + } + else { + /* + * Use the number of configured bits, assuming the + * driver wanted to override the hardware request + * value. + */ + request_private_bits = configured_private_bits; + } + + /* + * The PCI 2.3 spec mandates that there are at most 32 + * interrupts. If this device asks for more, only give it one. + */ + if (request_private_bits > 5) { + request_private_bits = 0; + } +again: + /* + * The IRQs have to be aligned on a power of two based on the + * number being requested. + */ + irq_step = (1 << request_private_bits); + + /* Mask with one bit for each IRQ */ + search_mask = (1 << irq_step) - 1; + + /* + * We're going to search msi_free_irq_bitmask_lock for zero + * bits. This represents an MSI interrupt number that isn't in + * use. + */ + spin_lock(&ifx_pcie_msi_lock); + for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos += irq_step) { + if ((msi_irqs[pcie_port].msi_free_irq_bitmask & (search_mask << pos)) == 0) { + msi_irqs[pcie_port].msi_free_irq_bitmask |= search_mask << pos; + msi_irqs[pcie_port].msi_multiple_irq_bitmask |= (search_mask >> 1) << pos; + break; + } + } + spin_unlock(&ifx_pcie_msi_lock); + + /* Make sure the search for available interrupts didn't fail */ + if (pos >= IFX_MSI_IRQ_NUM) { + if (request_private_bits) { + IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s: Unable to find %d free " + "interrupts, trying just one", __func__, 1 << request_private_bits); + request_private_bits = 0; + goto again; + } + else { + printk(KERN_ERR "%s: Unable to find a free MSI interrupt\n", __func__); + return -EINVAL; + } + } + irq = msi_irqs[pcie_port].msi_irq_idx[pos].irq; + irq_idx = msi_irqs[pcie_port].msi_irq_idx[pos].idx; + + IFX_PCIE_PRINT(PCIE_MSG_MSI, "pos %d, irq %d irq_idx %d\n", pos, irq, irq_idx); + + /* + * Initialize MSI. This has to match the memory-write endianess from the device + * Address bits [23:12] + */ + spin_lock(&ifx_pcie_msi_lock); + msi_irqs[pcie_port].msi_pic_p->pic_table[pos] = SM(irq_idx, IFX_MSI_PIC_INT_LINE) | + SM((msi_irqs[pcie_port].msi_phy_base >> 12), IFX_MSI_PIC_MSG_ADDR) | + SM((1 << pos), IFX_MSI_PIC_MSG_DATA); + + /* Enable this entry */ + msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~IFX_MSI_PCI_INT_DISABLE; + spin_unlock(&ifx_pcie_msi_lock); + + IFX_PCIE_PRINT(PCIE_MSG_MSI, "pic_table[%d]: 0x%08x\n", + pos, msi_irqs[pcie_port].msi_pic_p->pic_table[pos]); + + /* Update the number of IRQs the device has available to it */ + control &= ~PCI_MSI_FLAGS_QSIZE; + control |= (request_private_bits << 4); + pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, control); + + irq_set_msi_desc(irq, desc); + msg.address_hi = 0x0; + msg.address_lo = msi_irqs[pcie_port].msi_phy_base; + msg.data = SM((1 << pos), IFX_MSI_PIC_MSG_DATA); + IFX_PCIE_PRINT(PCIE_MSG_MSI, "msi_data: pos %d 0x%08x\n", pos, msg.data); + + write_msi_msg(irq, &msg); + IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); + return 0; +} + +static int +pcie_msi_irq_to_port(unsigned int irq, int *port) +{ + int ret = 0; + + if (irq == IFX_PCIE_MSI_IR0 || irq == IFX_PCIE_MSI_IR1 || + irq == IFX_PCIE_MSI_IR2 || irq == IFX_PCIE_MSI_IR3) { + *port = IFX_PCIE_PORT0; + } +#ifdef CONFIG_IFX_PCIE_2ND_CORE + else if (irq == IFX_PCIE1_MSI_IR0 || irq == IFX_PCIE1_MSI_IR1 || + irq == IFX_PCIE1_MSI_IR2 || irq == IFX_PCIE1_MSI_IR3) { + *port = IFX_PCIE_PORT1; + } +#endif /* CONFIG_IFX_PCIE_2ND_CORE */ + else { + printk(KERN_ERR "%s: Attempted to teardown illegal " + "MSI interrupt (%d)\n", __func__, irq); + ret = -EINVAL; + } + return ret; +} + +/** + * \fn void arch_teardown_msi_irq(unsigned int irq) + * \brief Called when a device no longer needs its MSI interrupts. All + * MSI interrupts for the device are freed. + * + * \param irq The devices first irq number. There may be multple in sequence. + * \return none + * \ingroup IFX_PCIE_MSI + */ +void +arch_teardown_msi_irq(unsigned int irq) +{ + int pos; + int number_irqs; + u16 bitmask; + int pcie_port; + + IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s enter\n", __func__); + + BUG_ON(irq > (INT_NUM_IM4_IRL0 + 31)); + + if (pcie_msi_irq_to_port(irq, &pcie_port) != 0) { + return; + } + + /* Shift the mask to the correct bit location, not always correct + * Probally, the first match will be chosen. + */ + for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos++) { + if ((msi_irqs[pcie_port].msi_irq_idx[pos].irq == irq) + && (msi_irqs[pcie_port].msi_free_irq_bitmask & ( 1 << pos))) { + break; + } + } + if (pos >= IFX_MSI_IRQ_NUM) { + printk(KERN_ERR "%s: Unable to find a matched MSI interrupt\n", __func__); + return; + } + spin_lock(&ifx_pcie_msi_lock); + /* Disable this entry */ + msi_irqs[pcie_port].msi_pic_p->pic_table[pos] |= IFX_MSI_PCI_INT_DISABLE; + msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~(IFX_MSI_PIC_INT_LINE | IFX_MSI_PIC_MSG_ADDR | IFX_MSI_PIC_MSG_DATA); + spin_unlock(&ifx_pcie_msi_lock); + /* + * Count the number of IRQs we need to free by looking at the + * msi_multiple_irq_bitmask. Each bit set means that the next + * IRQ is also owned by this device. + */ + number_irqs = 0; + while (((pos + number_irqs) < IFX_MSI_IRQ_NUM) && + (msi_irqs[pcie_port].msi_multiple_irq_bitmask & (1 << (pos + number_irqs)))) { + number_irqs++; + } + number_irqs++; + + /* Mask with one bit for each IRQ */ + bitmask = (1 << number_irqs) - 1; + + bitmask <<= pos; + if ((msi_irqs[pcie_port].msi_free_irq_bitmask & bitmask) != bitmask) { + printk(KERN_ERR "%s: Attempted to teardown MSI " + "interrupt (%d) not in use\n", __func__, irq); + return; + } + /* Checks are done, update the in use bitmask */ + spin_lock(&ifx_pcie_msi_lock); + msi_irqs[pcie_port].msi_free_irq_bitmask &= ~bitmask; + msi_irqs[pcie_port].msi_multiple_irq_bitmask &= ~(bitmask >> 1); + spin_unlock(&ifx_pcie_msi_lock); + IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); +} + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); +MODULE_SUPPORTED_DEVICE("Infineon PCIe IP builtin MSI PIC module"); +MODULE_DESCRIPTION("Infineon PCIe IP builtin MSI PIC driver"); + diff --git a/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq-phy.c b/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq-phy.c new file mode 100644 index 0000000000..9f5027d7cc --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq-phy.c @@ -0,0 +1,408 @@ +/****************************************************************************** +** +** FILE NAME : ifxmips_pcie_phy.c +** PROJECT : IFX UEIP for VRX200 +** MODULES : PCIe PHY sub module +** +** DATE : 14 May 2009 +** AUTHOR : Lei Chuanhua +** DESCRIPTION : PCIe Root Complex Driver +** COPYRIGHT : Copyright (c) 2009 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** HISTORY +** $Version $Date $Author $Comment +** 0.0.1 14 May,2009 Lei Chuanhua Initial version +*******************************************************************************/ +/*! + \file ifxmips_pcie_phy.c + \ingroup IFX_PCIE + \brief PCIe PHY PLL register programming source file +*/ +#include +#include +#include +#include + +#include "pcie-lantiq.h" + +/* PCIe PDI only supports 16 bit operation */ + +#define IFX_PCIE_PHY_REG_WRITE16(__addr, __data) \ + ((*(volatile u16 *) (__addr)) = (__data)) + +#define IFX_PCIE_PHY_REG_READ16(__addr) \ + (*(volatile u16 *) (__addr)) + +#define IFX_PCIE_PHY_REG16(__addr) \ + (*(volatile u16 *) (__addr)) + +#define IFX_PCIE_PHY_REG(__reg, __value, __mask) do { \ + u16 read_data; \ + u16 write_data; \ + read_data = IFX_PCIE_PHY_REG_READ16((__reg)); \ + write_data = (read_data & ((u16)~(__mask))) | (((u16)(__value)) & ((u16)(__mask)));\ + IFX_PCIE_PHY_REG_WRITE16((__reg), write_data); \ +} while (0) + +#define IFX_PCIE_PLL_TIMEOUT 1000 /* Tunnable */ + +static void +pcie_phy_comm_setup(int pcie_port) +{ + /* PLL Setting */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); + + /* increase the bias reference voltage */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); + + /* Endcnt */ + IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); + IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); + + /* force */ + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); + + /* predrv_ser_en */ + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); + + /* ctrl_lim */ + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); + + /* ctrl */ + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); + + /* predrv_ser_en */ + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); + + /* RTERM*/ + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); + + /* Improved 100MHz clock output */ + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); + + /* Reduced CDR BW to avoid glitches */ + IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); +} + +#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE +static void +pcie_phy_36mhz_mode_setup(int pcie_port) +{ + IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); + + /* en_ext_mmd_div_ratio */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); + + /* ext_mmd_div_ratio*/ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); + + /* pll_ensdm */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); + + /* en_const_sdm */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); + + /* mmd */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); + + /* lf_mode */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); + + /* const_sdm */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); + + /* const sdm */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); + + /* pllmod */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); + + IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); +} +#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ + +#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE +static void +pcie_phy_36mhz_ssc_mode_setup(int pcie_port) +{ + IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); + + /* PLL Setting */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); + + /* Increase the bias reference voltage */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); + + /* Endcnt */ + IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); + IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); + + /* Force */ + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); + + /* Predrv_ser_en */ + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); + + /* ctrl_lim */ + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); + + /* ctrl */ + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); + + /* predrv_ser_en */ + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); + + /* RTERM*/ + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); + + /* en_ext_mmd_div_ratio */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); + + /* ext_mmd_div_ratio*/ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); + + /* pll_ensdm */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0400, 0x0400); + + /* en_const_sdm */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); + + /* mmd */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); + + /* lf_mode */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); + + /* const_sdm */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); + + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0100); + /* const sdm */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); + + /* pllmod */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1c72, 0xFFFF); + + /* improved 100MHz clock output */ + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); + + /* reduced CDR BW to avoid glitches */ + IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); + + IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); +} +#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE */ + +#ifdef CONFIG_IFX_PCIE_PHY_25MHZ_MODE +static void +pcie_phy_25mhz_mode_setup(int pcie_port) +{ + IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); + /* en_const_sdm */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); + + /* pll_ensdm */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0200); + + /* en_ext_mmd_div_ratio*/ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0002, 0x0002); + + /* ext_mmd_div_ratio*/ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0040, 0x0070); + + /* mmd */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x6000, 0xe000); + + /* lf_mode */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x4000, 0x4000); + + IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); +} +#endif /* CONFIG_IFX_PCIE_PHY_25MHZ_MODE */ + +#ifdef CONFIG_IFX_PCIE_PHY_100MHZ_MODE +static void +pcie_phy_100mhz_mode_setup(int pcie_port) +{ + IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); + /* en_ext_mmd_div_ratio */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); + + /* ext_mmd_div_ratio*/ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); + + /* pll_ensdm */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); + + /* en_const_sdm */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); + + /* mmd */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); + + /* lf_mode */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); + + /* const_sdm */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); + + /* const sdm */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); + + /* pllmod */ + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); + IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); + + IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); +} +#endif /* CONFIG_IFX_PCIE_PHY_100MHZ_MODE */ + +static int +pcie_phy_wait_startup_ready(int pcie_port) +{ + int i; + + for (i = 0; i < IFX_PCIE_PLL_TIMEOUT; i++) { + if ((IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)) & 0x0040) != 0) { + break; + } + udelay(10); + } + if (i >= IFX_PCIE_PLL_TIMEOUT) { + printk(KERN_ERR "%s PLL Link timeout\n", __func__); + return -1; + } + return 0; +} + +static void +pcie_phy_load_enable(int pcie_port, int slice) +{ + /* Set the load_en of tx/rx slice to '1' */ + switch (slice) { + case 1: + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0010, 0x0010); + break; + case 2: + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0010, 0x0010); + break; + case 3: + IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0002, 0x0002); + break; + } +} + +static void +pcie_phy_load_disable(int pcie_port, int slice) +{ + /* set the load_en of tx/rx slice to '0' */ + switch (slice) { + case 1: + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0000, 0x0010); + break; + case 2: + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0000, 0x0010); + break; + case 3: + IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0000, 0x0002); + break; + } +} + +static void pcie_phy_load_war(int pcie_port) +{ + int slice; + + for (slice = 1; slice < 4; slice++) { + pcie_phy_load_enable(pcie_port, slice); + udelay(1); + pcie_phy_load_disable(pcie_port, slice); + } +} + +static void pcie_phy_tx2_modulation(int pcie_port) +{ + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD1(pcie_port), 0x1FFE, 0xFFFF); + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD2(pcie_port), 0xFFFE, 0xFFFF); + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0601, 0xFFFF); + mdelay(1); + IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0001, 0xFFFF); +} + +static void pcie_phy_tx1_modulation(int pcie_port) +{ + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD1(pcie_port), 0x1FFE, 0xFFFF); + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD2(pcie_port), 0xFFFE, 0xFFFF); + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0601, 0xFFFF); + mdelay(1); + IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0001, 0xFFFF); +} + +static void pcie_phy_tx_modulation_war(int pcie_port) +{ + int i; +#define PCIE_PHY_MODULATION_NUM 5 + for (i = 0; i < PCIE_PHY_MODULATION_NUM; i++) { + pcie_phy_tx2_modulation(pcie_port); + pcie_phy_tx1_modulation(pcie_port); + } +#undef PCIE_PHY_MODULATION_NUM +} + +void pcie_phy_clock_mode_setup(int pcie_port) +{ + pcie_pdi_big_endian(pcie_port); + + /* Enable PDI to access PCIe PHY register */ + pcie_pdi_pmu_enable(pcie_port); + + /* Configure PLL and PHY clock */ + pcie_phy_comm_setup(pcie_port); + +#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE + pcie_phy_36mhz_mode_setup(pcie_port); +#elif defined(CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE) + pcie_phy_36mhz_ssc_mode_setup(pcie_port); +#elif defined(CONFIG_IFX_PCIE_PHY_25MHZ_MODE) + pcie_phy_25mhz_mode_setup(pcie_port); +#elif defined (CONFIG_IFX_PCIE_PHY_100MHZ_MODE) + pcie_phy_100mhz_mode_setup(pcie_port); +#else + #error "PCIE PHY Clock Mode must be chosen first!!!!" +#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ + + /* Enable PCIe PHY and make PLL setting take effect */ + pcie_phy_pmu_enable(pcie_port); + + /* Check if we are in startup_ready status */ + pcie_phy_wait_startup_ready(pcie_port); + + pcie_phy_load_war(pcie_port); + + /* Apply TX modulation workarounds */ + pcie_phy_tx_modulation_war(pcie_port); + +#ifdef IFX_PCI_PHY_REG_DUMP + IFX_PCIE_PRINT(PCIE_MSG_PHY, "Modified PHY register dump\n"); + pcie_phy_reg_dump(pcie_port); +#endif +} + diff --git a/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq.c b/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq.c new file mode 100644 index 0000000000..1df55b5c02 --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq.c @@ -0,0 +1,1146 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CONFIG_IFX_PCIE_1ST_CORE + +#include "pcie-lantiq.h" + +#define IFX_PCIE_IR (INT_NUM_IM4_IRL0 + 25) +#define IFX_PCIE_INTA (INT_NUM_IM4_IRL0 + 8) +#define IFX_PCIE_INTB (INT_NUM_IM4_IRL0 + 9) +#define IFX_PCIE_INTC (INT_NUM_IM4_IRL0 + 10) +#define IFX_PCIE_INTD (INT_NUM_IM4_IRL0 + 11) +#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) +#define SM(_v, _f) (((_v) << _f##_S) & (_f)) +#define IFX_REG_SET_BIT(_f, _r) \ + IFX_REG_W32((IFX_REG_R32((_r)) &~ (_f)) | (_f), (_r)) +#define IFX_PCIE_LTSSM_ENABLE_TIMEOUT 10 +#define IFX_PCIE_PHY_LINK_UP_TIMEOUT 1000 +#define IFX_PCIE_PHY_LOOP_CNT 5 + +static DEFINE_SPINLOCK(ifx_pcie_lock); + +int pcibios_1st_host_bus_nr(void); + +unsigned int g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG); + +static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = { + { + .ir_irq = { + .irq = IFX_PCIE_IR, + .name = "ifx_pcie_rc0", + }, + + .legacy_irq = { + { + .irq_bit = PCIE_IRN_INTA, + .irq = IFX_PCIE_INTA, + }, + { + .irq_bit = PCIE_IRN_INTB, + .irq = IFX_PCIE_INTB, + }, + { + .irq_bit = PCIE_IRN_INTC, + .irq = IFX_PCIE_INTC, + }, + { + .irq_bit = PCIE_IRN_INTD, + .irq = IFX_PCIE_INTD, + }, + }, + }, +}; + +static inline int pcie_ltssm_enable(int pcie_port) +{ + int i; + + IFX_REG_W32(PCIE_RC_CCR_LTSSM_ENABLE, PCIE_RC_CCR(pcie_port)); /* Enable LTSSM */ + + /* Wait for the link to come up */ + for (i = 0; i < IFX_PCIE_LTSSM_ENABLE_TIMEOUT; i++) { + if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_RETRAIN_PENDING)) { + break; + } + udelay(10); + } + if (i >= IFX_PCIE_LTSSM_ENABLE_TIMEOUT) { + IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s link timeout!!!!!\n", __func__); + return -1; + } + return 0; +} + +static inline void pcie_status_register_clear(int pcie_port) +{ + IFX_REG_W32(0, PCIE_RC_DR(pcie_port)); + IFX_REG_W32(0, PCIE_PCICMDSTS(pcie_port)); + IFX_REG_W32(0, PCIE_DCTLSTS(pcie_port)); + IFX_REG_W32(0, PCIE_LCTLSTS(pcie_port)); + IFX_REG_W32(0, PCIE_SLCTLSTS(pcie_port)); + IFX_REG_W32(0, PCIE_RSTS(pcie_port)); + IFX_REG_W32(0, PCIE_UES_R(pcie_port)); + IFX_REG_W32(0, PCIE_UEMR(pcie_port)); + IFX_REG_W32(0, PCIE_UESR(pcie_port)); + IFX_REG_W32(0, PCIE_CESR(pcie_port)); + IFX_REG_W32(0, PCIE_CEMR(pcie_port)); + IFX_REG_W32(0, PCIE_RESR(pcie_port)); + IFX_REG_W32(0, PCIE_PVCCRSR(pcie_port)); + IFX_REG_W32(0, PCIE_VC0_RSR0(pcie_port)); + IFX_REG_W32(0, PCIE_TPFCS(pcie_port)); + IFX_REG_W32(0, PCIE_TNPFCS(pcie_port)); + IFX_REG_W32(0, PCIE_TCFCS(pcie_port)); + IFX_REG_W32(0, PCIE_QSR(pcie_port)); + IFX_REG_W32(0, PCIE_IOBLSECS(pcie_port)); +} + +static inline int ifx_pcie_link_up(int pcie_port) +{ + return (IFX_REG_R32(PCIE_PHY_SR(pcie_port)) & PCIE_PHY_SR_PHY_LINK_UP) ? 1 : 0; +} + +static inline void pcie_mem_io_setup(int pcie_port) +{ + unsigned int reg; + /* + * BAR[0:1] readonly register + * RC contains only minimal BARs for packets mapped to this device + * Mem/IO filters defines a range of memory occupied by memory mapped IO devices that + * reside on the downstream side fo the bridge. + */ + reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_MBML_MEM_LIMIT_ADDR) + | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_MBML_MEM_BASE_ADDR); + IFX_REG_W32(reg, PCIE_MBML(pcie_port)); + + /* PCIe_PBML, same as MBML */ + IFX_REG_W32(IFX_REG_R32(PCIE_MBML(pcie_port)), PCIE_PMBL(pcie_port)); + + /* IO Address Range */ + reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 12), PCIE_IOBLSECS_IO_LIMIT_ADDR) + | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 12), PCIE_IOBLSECS_IO_BASE_ADDR); + reg |= PCIE_IOBLSECS_32BIT_IO_ADDR; + IFX_REG_W32(reg, PCIE_IOBLSECS(pcie_port)); + + reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT) + | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_BASE); + IFX_REG_W32(reg, PCIE_IO_BANDL(pcie_port)); +} + +static inline void pcie_msi_setup(int pcie_port) +{ + unsigned int reg; + + /* XXX, MSI stuff should only apply to EP */ + /* MSI Capability: Only enable 32-bit addresses */ + reg = IFX_REG_R32(PCIE_MCAPR(pcie_port)); + reg &= ~PCIE_MCAPR_ADDR64_CAP; + reg |= PCIE_MCAPR_MSI_ENABLE; + + /* Disable multiple message */ + reg &= ~(PCIE_MCAPR_MULTI_MSG_CAP | PCIE_MCAPR_MULTI_MSG_ENABLE); + IFX_REG_W32(reg, PCIE_MCAPR(pcie_port)); +} + +static inline void pcie_pm_setup(int pcie_port) +{ + unsigned int reg; + + /* Enable PME, Soft reset enabled */ + reg = IFX_REG_R32(PCIE_PM_CSR(pcie_port)); + reg |= PCIE_PM_CSR_PME_ENABLE | PCIE_PM_CSR_SW_RST; + IFX_REG_W32(reg, PCIE_PM_CSR(pcie_port)); +} + +static inline void pcie_bus_setup(int pcie_port) +{ + unsigned int reg; + + reg = SM(0, PCIE_BNR_PRIMARY_BUS_NUM) | SM(1, PCIE_PNR_SECONDARY_BUS_NUM) | SM(0xFF, PCIE_PNR_SUB_BUS_NUM); + IFX_REG_W32(reg, PCIE_BNR(pcie_port)); +} + +static inline void pcie_device_setup(int pcie_port) +{ + unsigned int reg; + + /* Device capability register, set up Maximum payload size */ + reg = IFX_REG_R32(PCIE_DCAP(pcie_port)); + reg |= PCIE_DCAP_ROLE_BASE_ERR_REPORT; + reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCAP_MAX_PAYLOAD_SIZE); + + /* Only available for EP */ + reg &= ~(PCIE_DCAP_EP_L0S_LATENCY | PCIE_DCAP_EP_L1_LATENCY); + IFX_REG_W32(reg, PCIE_DCAP(pcie_port)); + + /* Device control and status register */ + /* Set Maximum Read Request size for the device as a Requestor */ + reg = IFX_REG_R32(PCIE_DCTLSTS(pcie_port)); + + /* + * Request size can be larger than the MPS used, but the completions returned + * for the read will be bounded by the MPS size. + * In our system, Max request size depends on AHB burst size. It is 64 bytes. + * but we set it as 128 as minimum one. + */ + reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_READ_SIZE) + | SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_PAYLOAD_SIZE); + + /* Enable relaxed ordering, no snoop, and all kinds of errors */ + reg |= PCIE_DCTLSTS_RELAXED_ORDERING_EN | PCIE_DCTLSTS_ERR_EN | PCIE_DCTLSTS_NO_SNOOP_EN; + + IFX_REG_W32(reg, PCIE_DCTLSTS(pcie_port)); +} + +static inline void pcie_link_setup(int pcie_port) +{ + unsigned int reg; + + /* + * XXX, Link capability register, bit 18 for EP CLKREQ# dynamic clock management for L1, L2/3 CPM + * L0s is reported during link training via TS1 order set by N_FTS + */ + reg = IFX_REG_R32(PCIE_LCAP(pcie_port)); + reg &= ~PCIE_LCAP_L0S_EIXT_LATENCY; + reg |= SM(3, PCIE_LCAP_L0S_EIXT_LATENCY); + IFX_REG_W32(reg, PCIE_LCAP(pcie_port)); + + /* Link control and status register */ + reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); + + /* Link Enable, ASPM enabled */ + reg &= ~PCIE_LCTLSTS_LINK_DISABLE; + +#ifdef CONFIG_PCIEASPM + /* + * We use the same physical reference clock that the platform provides on the connector + * It paved the way for ASPM to calculate the new exit Latency + */ + reg |= PCIE_LCTLSTS_SLOT_CLK_CFG; + reg |= PCIE_LCTLSTS_COM_CLK_CFG; + /* + * We should disable ASPM by default except that we have dedicated power management support + * Enable ASPM will cause the system hangup/instability, performance degration + */ + reg |= PCIE_LCTLSTS_ASPM_ENABLE; +#else + reg &= ~PCIE_LCTLSTS_ASPM_ENABLE; +#endif /* CONFIG_PCIEASPM */ + + /* + * The maximum size of any completion with data packet is bounded by the MPS setting + * in device control register + */ + /* RCB may cause multiple split transactions, two options available, we use 64 byte RCB */ + reg &= ~ PCIE_LCTLSTS_RCB128; + IFX_REG_W32(reg, PCIE_LCTLSTS(pcie_port)); +} + +static inline void pcie_error_setup(int pcie_port) +{ + unsigned int reg; + + /* + * Forward ERR_COR, ERR_NONFATAL, ERR_FATAL to the backbone + * Poisoned write TLPs and completions indicating poisoned TLPs will set the PCIe_PCICMDSTS.MDPE + */ + reg = IFX_REG_R32(PCIE_INTRBCTRL(pcie_port)); + reg |= PCIE_INTRBCTRL_SERR_ENABLE | PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE; + + IFX_REG_W32(reg, PCIE_INTRBCTRL(pcie_port)); + + /* Uncorrectable Error Mask Register, Unmask all bits in PCIE_UESR */ + reg = IFX_REG_R32(PCIE_UEMR(pcie_port)); + reg &= ~PCIE_ALL_UNCORRECTABLE_ERR; + IFX_REG_W32(reg, PCIE_UEMR(pcie_port)); + + /* Uncorrectable Error Severity Register, ALL errors are FATAL */ + IFX_REG_W32(PCIE_ALL_UNCORRECTABLE_ERR, PCIE_UESR(pcie_port)); + + /* Correctable Error Mask Register, unmask all bits */ + reg = IFX_REG_R32(PCIE_CEMR(pcie_port)); + reg &= ~PCIE_CORRECTABLE_ERR; + IFX_REG_W32(reg, PCIE_CEMR(pcie_port)); + + /* Advanced Error Capabilities and Control Registr */ + reg = IFX_REG_R32(PCIE_AECCR(pcie_port)); + reg |= PCIE_AECCR_ECRC_CHECK_EN | PCIE_AECCR_ECRC_GEN_EN; + IFX_REG_W32(reg, PCIE_AECCR(pcie_port)); + + /* Root Error Command Register, Report all types of errors */ + reg = IFX_REG_R32(PCIE_RECR(pcie_port)); + reg |= PCIE_RECR_ERR_REPORT_EN; + IFX_REG_W32(reg, PCIE_RECR(pcie_port)); + + /* Clear the Root status register */ + reg = IFX_REG_R32(PCIE_RESR(pcie_port)); + IFX_REG_W32(reg, PCIE_RESR(pcie_port)); +} + +static inline void pcie_root_setup(int pcie_port) +{ + unsigned int reg; + + /* Root control and capabilities register */ + reg = IFX_REG_R32(PCIE_RCTLCAP(pcie_port)); + reg |= PCIE_RCTLCAP_SERR_ENABLE | PCIE_RCTLCAP_PME_INT_EN; + IFX_REG_W32(reg, PCIE_RCTLCAP(pcie_port)); +} + +static inline void pcie_vc_setup(int pcie_port) +{ + unsigned int reg; + + /* Port VC Capability Register 2 */ + reg = IFX_REG_R32(PCIE_PVC2(pcie_port)); + reg &= ~PCIE_PVC2_VC_ARB_WRR; + reg |= PCIE_PVC2_VC_ARB_16P_FIXED_WRR; + IFX_REG_W32(reg, PCIE_PVC2(pcie_port)); + + /* VC0 Resource Capability Register */ + reg = IFX_REG_R32(PCIE_VC0_RC(pcie_port)); + reg &= ~PCIE_VC0_RC_REJECT_SNOOP; + IFX_REG_W32(reg, PCIE_VC0_RC(pcie_port)); +} + +static inline void pcie_port_logic_setup(int pcie_port) +{ + unsigned int reg; + + /* FTS number, default 12, increase to 63, may increase time from/to L0s to L0 */ + reg = IFX_REG_R32(PCIE_AFR(pcie_port)); + reg &= ~(PCIE_AFR_FTS_NUM | PCIE_AFR_COM_FTS_NUM); + reg |= SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_FTS_NUM) + | SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_COM_FTS_NUM); + /* L0s and L1 entry latency */ + reg &= ~(PCIE_AFR_L0S_ENTRY_LATENCY | PCIE_AFR_L1_ENTRY_LATENCY); + reg |= SM(PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L0S_ENTRY_LATENCY) + | SM(PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L1_ENTRY_LATENCY); + IFX_REG_W32(reg, PCIE_AFR(pcie_port)); + + /* Port Link Control Register */ + reg = IFX_REG_R32(PCIE_PLCR(pcie_port)); + reg |= PCIE_PLCR_DLL_LINK_EN; /* Enable the DLL link */ + IFX_REG_W32(reg, PCIE_PLCR(pcie_port)); + + /* Lane Skew Register */ + reg = IFX_REG_R32(PCIE_LSR(pcie_port)); + /* Enable ACK/NACK and FC */ + reg &= ~(PCIE_LSR_ACKNAK_DISABLE | PCIE_LSR_FC_DISABLE); + IFX_REG_W32(reg, PCIE_LSR(pcie_port)); + + /* Symbol Timer Register and Filter Mask Register 1 */ + reg = IFX_REG_R32(PCIE_STRFMR(pcie_port)); + + /* Default SKP interval is very accurate already, 5us */ + /* Enable IO/CFG transaction */ + reg |= PCIE_STRFMR_RX_CFG_TRANS_ENABLE | PCIE_STRFMR_RX_IO_TRANS_ENABLE; + /* Disable FC WDT */ + reg &= ~PCIE_STRFMR_FC_WDT_DISABLE; + IFX_REG_W32(reg, PCIE_STRFMR(pcie_port)); + + /* Filter Masker Register 2 */ + reg = IFX_REG_R32(PCIE_FMR2(pcie_port)); + reg |= PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 | PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1; + IFX_REG_W32(reg, PCIE_FMR2(pcie_port)); + + /* VC0 Completion Receive Queue Control Register */ + reg = IFX_REG_R32(PCIE_VC0_CRQCR(pcie_port)); + reg &= ~PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE; + reg |= SM(PCIE_VC0_TLP_QUEUE_MODE_BYPASS, PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE); + IFX_REG_W32(reg, PCIE_VC0_CRQCR(pcie_port)); +} + +static inline void pcie_rc_cfg_reg_setup(int pcie_port) +{ + /* diable ltssm */ + IFX_REG_W32(0, PCIE_RC_CCR(pcie_port)); + + pcie_mem_io_setup(pcie_port); + pcie_msi_setup(pcie_port); + pcie_pm_setup(pcie_port); + pcie_bus_setup(pcie_port); + pcie_device_setup(pcie_port); + pcie_link_setup(pcie_port); + pcie_error_setup(pcie_port); + pcie_root_setup(pcie_port); + pcie_vc_setup(pcie_port); + pcie_port_logic_setup(pcie_port); +} + +static int ifx_pcie_wait_phy_link_up(int pcie_port) +{ + int i; + + /* Wait for PHY link is up */ + for (i = 0; i < IFX_PCIE_PHY_LINK_UP_TIMEOUT; i++) { + if (ifx_pcie_link_up(pcie_port)) { + break; + } + udelay(100); + } + if (i >= IFX_PCIE_PHY_LINK_UP_TIMEOUT) { + printk(KERN_ERR "%s timeout\n", __func__); + return -1; + } + + /* Check data link up or not */ + if (!(IFX_REG_R32(PCIE_RC_DR(pcie_port)) & PCIE_RC_DR_DLL_UP)) { + printk(KERN_ERR "%s DLL link is still down\n", __func__); + return -1; + } + + /* Check Data link active or not */ + if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_DLL_ACTIVE)) { + printk(KERN_ERR "%s DLL is not active\n", __func__); + return -1; + } + return 0; +} + +static inline int pcie_app_loigc_setup(int pcie_port) +{ + IFX_REG_W32(PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS, PCIE_AHB_CTRL(pcie_port)); + + /* Pull PCIe EP out of reset */ + pcie_device_rst_deassert(pcie_port); + + /* Start LTSSM training between RC and EP */ + pcie_ltssm_enable(pcie_port); + + /* Check PHY status after enabling LTSSM */ + if (ifx_pcie_wait_phy_link_up(pcie_port) != 0) { + return -1; + } + return 0; +} + +/* + * Must be done after ltssm due to based on negotiated link + * width and payload size + * Update the Replay Time Limit. Empirically, some PCIe + * devices take a little longer to respond than expected under + * load. As a workaround for this we configure the Replay Time + * Limit to the value expected for a 512 byte MPS instead of + * our actual 128 byte MPS. The numbers below are directly + * from the PCIe spec table 3-4/5. + */ +static inline void pcie_replay_time_update(int pcie_port) +{ + unsigned int reg; + int nlw; + int rtl; + + reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); + + nlw = MS(reg, PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH); + switch (nlw) { + case PCIE_MAX_LENGTH_WIDTH_X1: + rtl = 1677; + break; + case PCIE_MAX_LENGTH_WIDTH_X2: + rtl = 867; + break; + case PCIE_MAX_LENGTH_WIDTH_X4: + rtl = 462; + break; + case PCIE_MAX_LENGTH_WIDTH_X8: + rtl = 258; + break; + default: + rtl = 1677; + break; + } + reg = IFX_REG_R32(PCIE_ALTRT(pcie_port)); + reg &= ~PCIE_ALTRT_REPLAY_TIME_LIMIT; + reg |= SM(rtl, PCIE_ALTRT_REPLAY_TIME_LIMIT); + IFX_REG_W32(reg, PCIE_ALTRT(pcie_port)); + + IFX_PCIE_PRINT(PCIE_MSG_REG, "%s PCIE_ALTRT 0x%08x\n", + __func__, IFX_REG_R32(PCIE_ALTRT(pcie_port))); +} + +/* + * Table 359 Enhanced Configuration Address Mapping1) + * 1) This table is defined in Table 7-1, page 341, PCI Express Base Specification v1.1 + * Memory Address PCI Express Configuration Space + * A[(20+n-1):20] Bus Number 1 < n < 8 + * A[19:15] Device Number + * A[14:12] Function Number + * A[11:8] Extended Register Number + * A[7:2] Register Number + * A[1:0] Along with size of the access, used to generate Byte Enables + * For VR9, only the address bits [22:0] are mapped to the configuration space: + * . Address bits [22:20] select the target bus (1-of-8)1) + * . Address bits [19:15] select the target device (1-of-32) on the bus + * . Address bits [14:12] select the target function (1-of-8) within the device. + * . Address bits [11:2] selects the target dword (1-of-1024) within the selected function.s configuration space + * . Address bits [1:0] define the start byte location within the selected dword. + */ +static inline unsigned int pcie_bus_addr(u8 bus_num, u16 devfn, int where) +{ + unsigned int addr; + u8 bus; + + if (!bus_num) { + /* type 0 */ + addr = ((PCI_SLOT(devfn) & 0x1F) << 15) | ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF)& ~3); + } else { + bus = bus_num; + /* type 1, only support 8 buses */ + addr = ((bus & 0x7) << 20) | ((PCI_SLOT(devfn) & 0x1F) << 15) | + ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF) & ~3); + } + IFX_PCIE_PRINT(PCIE_MSG_CFG, "%s: bus addr : %02x:%02x.%01x/%02x, addr=%08x\n", + __func__, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn), where, addr); + return addr; +} + +static int pcie_valid_config(int pcie_port, int bus, int dev) +{ + /* RC itself */ + if ((bus == 0) && (dev == 0)) + return 1; + + /* No physical link */ + if (!ifx_pcie_link_up(pcie_port)) + return 0; + + /* Bus zero only has RC itself + * XXX, check if EP will be integrated + */ + if ((bus == 0) && (dev != 0)) + return 0; + + /* Maximum 8 buses supported for VRX */ + if (bus > 9) + return 0; + + /* + * PCIe is PtP link, one bus only supports only one device + * except bus zero and PCIe switch which is virtual bus device + * The following two conditions really depends on the system design + * and attached the device. + * XXX, how about more new switch + */ + if ((bus == 1) && (dev != 0)) + return 0; + + if ((bus >= 3) && (dev != 0)) + return 0; + return 1; +} + +static inline unsigned int ifx_pcie_cfg_rd(int pcie_port, unsigned int reg) +{ + return IFX_REG_R32((volatile unsigned int *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); +} + +static inline void ifx_pcie_cfg_wr(int pcie_port, unsigned int reg, unsigned int val) +{ + IFX_REG_W32( val, (volatile unsigned int *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); +} + +static inline unsigned int ifx_pcie_rc_cfg_rd(int pcie_port, unsigned int reg) +{ + return IFX_REG_R32((volatile unsigned int *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); +} + +static inline void ifx_pcie_rc_cfg_wr(int pcie_port, unsigned int reg, unsigned int val) +{ + IFX_REG_W32(val, (volatile unsigned int *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); +} + +unsigned int ifx_pcie_bus_enum_read_hack(int where, unsigned int value) +{ + unsigned int tvalue = value; + + if (where == PCI_PRIMARY_BUS) { + u8 primary, secondary, subordinate; + + primary = tvalue & 0xFF; + secondary = (tvalue >> 8) & 0xFF; + subordinate = (tvalue >> 16) & 0xFF; + primary += pcibios_1st_host_bus_nr(); + secondary += pcibios_1st_host_bus_nr(); + subordinate += pcibios_1st_host_bus_nr(); + tvalue = (tvalue & 0xFF000000) | (unsigned int)primary | (unsigned int)(secondary << 8) | (unsigned int)(subordinate << 16); + } + return tvalue; +} + +unsigned int ifx_pcie_bus_enum_write_hack(int where, unsigned int value) +{ + unsigned int tvalue = value; + + if (where == PCI_PRIMARY_BUS) { + u8 primary, secondary, subordinate; + + primary = tvalue & 0xFF; + secondary = (tvalue >> 8) & 0xFF; + subordinate = (tvalue >> 16) & 0xFF; + if (primary > 0 && primary != 0xFF) + primary -= pcibios_1st_host_bus_nr(); + if (secondary > 0 && secondary != 0xFF) + secondary -= pcibios_1st_host_bus_nr(); + if (subordinate > 0 && subordinate != 0xFF) + subordinate -= pcibios_1st_host_bus_nr(); + tvalue = (tvalue & 0xFF000000) | (unsigned int)primary | (unsigned int)(secondary << 8) | (unsigned int)(subordinate << 16); + } else if (where == PCI_SUBORDINATE_BUS) { + u8 subordinate = tvalue & 0xFF; + subordinate = subordinate > 0 ? subordinate - pcibios_1st_host_bus_nr() : 0; + tvalue = subordinate; + } + return tvalue; +} + +/** + * \fn static int ifx_pcie_read_config(struct pci_bus *bus, unsigned int devfn, + * int where, int size, unsigned int *value) + * \brief Read a value from configuration space + * + * \param[in] bus Pointer to pci bus + * \param[in] devfn PCI device function number + * \param[in] where PCI register number + * \param[in] size Register read size + * \param[out] value Pointer to return value + * \return PCIBIOS_BAD_REGISTER_NUMBER Invalid register number + * \return PCIBIOS_FUNC_NOT_SUPPORTED PCI function not supported + * \return PCIBIOS_DEVICE_NOT_FOUND PCI device not found + * \return PCIBIOS_SUCCESSFUL OK + * \ingroup IFX_PCIE_OS + */ +static int ifx_pcie_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, unsigned int *value) +{ + unsigned int data = 0; + int bus_number = bus->number; + static const unsigned int mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0}; + int ret = PCIBIOS_SUCCESSFUL; + struct ifx_pci_controller *ctrl = bus->sysdata; + int pcie_port = ctrl->port; + + if (unlikely(size != 1 && size != 2 && size != 4)){ + ret = PCIBIOS_BAD_REGISTER_NUMBER; + goto out; + } + + /* Make sure the address is aligned to natural boundary */ + if (unlikely(((size - 1) & where))) { + ret = PCIBIOS_BAD_REGISTER_NUMBER; + goto out; + } + + /* + * If we are second controller, we have to cheat OS so that it assume + * its bus number starts from 0 in host controller + */ + bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); + + /* + * We need to force the bus number to be zero on the root + * bus. Linux numbers the 2nd root bus to start after all + * busses on root 0. + */ + if (bus->parent == NULL) + bus_number = 0; + + /* + * PCIe only has a single device connected to it. It is + * always device ID 0. Don't bother doing reads for other + * device IDs on the first segment. + */ + if ((bus_number == 0) && (PCI_SLOT(devfn) != 0)) { + ret = PCIBIOS_FUNC_NOT_SUPPORTED; + goto out; + } + + if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { + *value = 0xffffffff; + ret = PCIBIOS_DEVICE_NOT_FOUND; + goto out; + } + + IFX_PCIE_PRINT(PCIE_MSG_READ_CFG, "%s: %02x:%02x.%01x/%02x:%01d\n", __func__, bus_number, + PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); + + PCIE_IRQ_LOCK(ifx_pcie_lock); + if (bus_number == 0) { /* RC itself */ + unsigned int t; + + t = (where & ~3); + data = ifx_pcie_rc_cfg_rd(pcie_port, t); + IFX_PCIE_PRINT(PCIE_MSG_READ_CFG, "%s: rd local cfg, offset:%08x, data:%08x\n", + __func__, t, data); + } else { + unsigned int addr = pcie_bus_addr(bus_number, devfn, where); + + data = ifx_pcie_cfg_rd(pcie_port, addr); + if (pcie_port == IFX_PCIE_PORT0) { +#ifdef CONFIG_IFX_PCIE_HW_SWAP + data = le32_to_cpu(data); +#endif /* CONFIG_IFX_PCIE_HW_SWAP */ + } else { +#ifdef CONFIG_IFX_PCIE1_HW_SWAP + data = le32_to_cpu(data); +#endif /* CONFIG_IFX_PCIE_HW_SWAP */ + } + } + /* To get a correct PCI topology, we have to restore the bus number to OS */ + data = ifx_pcie_bus_enum_hack(bus, devfn, where, data, pcie_port, 1); + + PCIE_IRQ_UNLOCK(ifx_pcie_lock); + IFX_PCIE_PRINT(PCIE_MSG_READ_CFG, "%s: read config: data=%08x raw=%08x\n", + __func__, (data >> (8 * (where & 3))) & mask[size & 7], data); + + *value = (data >> (8 * (where & 3))) & mask[size & 7]; +out: + return ret; +} + +static unsigned int ifx_pcie_size_to_value(int where, int size, unsigned int data, unsigned int value) +{ + unsigned int shift; + unsigned int tdata = data; + + switch (size) { + case 1: + shift = (where & 0x3) << 3; + tdata &= ~(0xffU << shift); + tdata |= ((value & 0xffU) << shift); + break; + case 2: + shift = (where & 3) << 3; + tdata &= ~(0xffffU << shift); + tdata |= ((value & 0xffffU) << shift); + break; + case 4: + tdata = value; + break; + } + return tdata; +} + +/** + * \fn static static int ifx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, + * int where, int size, unsigned int value) + * \brief Write a value to PCI configuration space + * + * \param[in] bus Pointer to pci bus + * \param[in] devfn PCI device function number + * \param[in] where PCI register number + * \param[in] size The register size to be written + * \param[in] value The valule to be written + * \return PCIBIOS_BAD_REGISTER_NUMBER Invalid register number + * \return PCIBIOS_DEVICE_NOT_FOUND PCI device not found + * \return PCIBIOS_SUCCESSFUL OK + * \ingroup IFX_PCIE_OS + */ +static int ifx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, unsigned int value) +{ + int bus_number = bus->number; + int ret = PCIBIOS_SUCCESSFUL; + struct ifx_pci_controller *ctrl = bus->sysdata; + int pcie_port = ctrl->port; + unsigned int tvalue = value; + unsigned int data; + + /* Make sure the address is aligned to natural boundary */ + if (unlikely(((size - 1) & where))) { + ret = PCIBIOS_BAD_REGISTER_NUMBER; + goto out; + } + /* + * If we are second controller, we have to cheat OS so that it assume + * its bus number starts from 0 in host controller + */ + bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); + + /* + * We need to force the bus number to be zero on the root + * bus. Linux numbers the 2nd root bus to start after all + * busses on root 0. + */ + if (bus->parent == NULL) + bus_number = 0; + + if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { + ret = PCIBIOS_DEVICE_NOT_FOUND; + goto out; + } + + IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG, "%s: %02x:%02x.%01x/%02x:%01d value=%08x\n", __func__, + bus_number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, value); + + /* XXX, some PCIe device may need some delay */ + PCIE_IRQ_LOCK(ifx_pcie_lock); + + /* + * To configure the correct bus topology using native way, we have to cheat Os so that + * it can configure the PCIe hardware correctly. + */ + tvalue = ifx_pcie_bus_enum_hack(bus, devfn, where, value, pcie_port, 0); + + if (bus_number == 0) { /* RC itself */ + unsigned int t; + + t = (where & ~3); + IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG,"%s: wr local cfg, offset:%08x, fill:%08x\n", __func__, t, value); + data = ifx_pcie_rc_cfg_rd(pcie_port, t); + IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG,"%s: rd local cfg, offset:%08x, data:%08x\n", __func__, t, data); + + data = ifx_pcie_size_to_value(where, size, data, tvalue); + + IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG,"%s: wr local cfg, offset:%08x, value:%08x\n", __func__, t, data); + ifx_pcie_rc_cfg_wr(pcie_port, t, data); + IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG,"%s: rd local cfg, offset:%08x, value:%08x\n", + __func__, t, ifx_pcie_rc_cfg_rd(pcie_port, t)); + } else { + unsigned int addr = pcie_bus_addr(bus_number, devfn, where); + + IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG,"%s: wr cfg, offset:%08x, fill:%08x\n", __func__, addr, value); + data = ifx_pcie_cfg_rd(pcie_port, addr); + if (pcie_port == IFX_PCIE_PORT0) { +#ifdef CONFIG_IFX_PCIE_HW_SWAP + data = le32_to_cpu(data); +#endif /* CONFIG_IFX_PCIE_HW_SWAP */ + } else { +#ifdef CONFIG_IFX_PCIE1_HW_SWAP + data = le32_to_cpu(data); +#endif /* CONFIG_IFX_PCIE_HW_SWAP */ + } + IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG,"%s: rd cfg, offset:%08x, data:%08x\n", __func__, addr, data); + + data = ifx_pcie_size_to_value(where, size, data, tvalue); + if (pcie_port == IFX_PCIE_PORT0) { +#ifdef CONFIG_IFX_PCIE_HW_SWAP + data = cpu_to_le32(data); +#endif /* CONFIG_IFX_PCIE_HW_SWAP */ + } else { +#ifdef CONFIG_IFX_PCIE1_HW_SWAP + data = cpu_to_le32(data); +#endif /* CONFIG_IFX_PCIE_HW_SWAP */ + } + IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG, "%s: wr cfg, offset:%08x, value:%08x\n", __func__, addr, data); + ifx_pcie_cfg_wr(pcie_port, addr, data); + IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG, "%s: rd cfg, offset:%08x, value:%08x\n", + __func__, addr, ifx_pcie_cfg_rd(pcie_port, addr)); + } + PCIE_IRQ_UNLOCK(ifx_pcie_lock); +out: + return ret; +} + +static struct resource ifx_pcie_io_resource = { + .name = "PCIe0 I/O space", + .start = PCIE_IO_PHY_BASE, + .end = PCIE_IO_PHY_END, + .flags = IORESOURCE_IO, +}; + +static struct resource ifx_pcie_mem_resource = { + .name = "PCIe0 Memory space", + .start = PCIE_MEM_PHY_BASE, + .end = PCIE_MEM_PHY_END, + .flags = IORESOURCE_MEM, +}; + +static struct pci_ops ifx_pcie_ops = { + .read = ifx_pcie_read_config, + .write = ifx_pcie_write_config, +}; + +static struct ifx_pci_controller ifx_pcie_controller[IFX_PCIE_CORE_NR] = { + { + .pcic = { + .pci_ops = &ifx_pcie_ops, + .mem_resource = &ifx_pcie_mem_resource, + .io_resource = &ifx_pcie_io_resource, + }, + .port = IFX_PCIE_PORT0, + }, +}; + +static inline void pcie_core_int_clear_all(int pcie_port) +{ + unsigned int reg; + reg = IFX_REG_R32(PCIE_IRNCR(pcie_port)); + reg &= PCIE_RC_CORE_COMBINED_INT; + IFX_REG_W32(reg, PCIE_IRNCR(pcie_port)); +} + +static irqreturn_t pcie_rc_core_isr(int irq, void *dev_id) +{ + struct ifx_pci_controller *ctrl = (struct ifx_pci_controller *)dev_id; + int pcie_port = ctrl->port; + + IFX_PCIE_PRINT(PCIE_MSG_ISR, "PCIe RC error intr %d\n", irq); + pcie_core_int_clear_all(pcie_port); + return IRQ_HANDLED; +} + +static int pcie_rc_core_int_init(int pcie_port) +{ + int ret; + + /* Enable core interrupt */ + IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNEN(pcie_port)); + + /* Clear it first */ + IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNCR(pcie_port)); + ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, IRQF_DISABLED, + pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]); + if (ret) + printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR); + + return ret; +} + +int ifx_pcie_bios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + unsigned int irq_bit = 0; + int irq = 0; + struct ifx_pci_controller *ctrl = dev->bus->sysdata; + int pcie_port = ctrl->port; + + IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s port %d dev %s slot %d pin %d \n", __func__, pcie_port, pci_name(dev), slot, pin); + + if ((pin == PCIE_LEGACY_DISABLE) || (pin > PCIE_LEGACY_INT_MAX)) { + printk(KERN_WARNING "WARNING: dev %s: invalid interrupt pin %d\n", pci_name(dev), pin); + return -1; + } + /* Pin index so minus one */ + irq_bit = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq_bit; + irq = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq; + IFX_REG_SET_BIT(irq_bit, PCIE_IRNEN(pcie_port)); + IFX_REG_SET_BIT(irq_bit, PCIE_IRNCR(pcie_port)); + IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s irq %d assigned\n", __func__, pci_name(dev), irq); + return irq; +} + +/** + * \fn int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev) + * \brief Called to perform platform specific PCI setup + * + * \param[in] dev The Linux PCI device structure for the device to map + * \return OK + * \ingroup IFX_PCIE_OS + */ +int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev) +{ + u16 config; + unsigned int dconfig; + int pos; + /* Enable reporting System errors and parity errors on all devices */ + /* Enable parity checking and error reporting */ + pci_read_config_word(dev, PCI_COMMAND, &config); + config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR /*| PCI_COMMAND_INVALIDATE | + PCI_COMMAND_FAST_BACK*/; + pci_write_config_word(dev, PCI_COMMAND, config); + + if (dev->subordinate) { + /* Set latency timers on sub bridges */ + pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 0x40); /* XXX, */ + /* More bridge error detection */ + pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); + config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; + pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config); + } + /* Enable the PCIe normal error reporting */ + pos = pci_find_capability(dev, PCI_CAP_ID_EXP); + if (pos) { + /* Disable system error generation in response to error messages */ + pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &config); + config &= ~(PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | PCI_EXP_RTCTL_SEFEE); + pci_write_config_word(dev, pos + PCI_EXP_RTCTL, config); + + /* Clear PCIE Capability's Device Status */ + pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &config); + pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, config); + + /* Update Device Control */ + pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); + /* Correctable Error Reporting */ + config |= PCI_EXP_DEVCTL_CERE; + /* Non-Fatal Error Reporting */ + config |= PCI_EXP_DEVCTL_NFERE; + /* Fatal Error Reporting */ + config |= PCI_EXP_DEVCTL_FERE; + /* Unsupported Request */ + config |= PCI_EXP_DEVCTL_URRE; + pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); + } + + /* Find the Advanced Error Reporting capability */ + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); + if (pos) { + /* Clear Uncorrectable Error Status */ + pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &dconfig); + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, dconfig); + /* Enable reporting of all uncorrectable errors */ + /* Uncorrectable Error Mask - turned on bits disable errors */ + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0); + /* + * Leave severity at HW default. This only controls if + * errors are reported as uncorrectable or + * correctable, not if the error is reported. + */ + /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ + /* Clear Correctable Error Status */ + pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig); + pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig); + /* Enable reporting of all correctable errors */ + /* Correctable Error Mask - turned on bits disable errors */ + pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0); + /* Advanced Error Capabilities */ + pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig); + /* ECRC Generation Enable */ + if (dconfig & PCI_ERR_CAP_ECRC_GENC) + dconfig |= PCI_ERR_CAP_ECRC_GENE; + /* ECRC Check Enable */ + if (dconfig & PCI_ERR_CAP_ECRC_CHKC) + dconfig |= PCI_ERR_CAP_ECRC_CHKE; + pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig); + + /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */ + /* Enable Root Port's interrupt in response to error messages */ + pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, + PCI_ERR_ROOT_CMD_COR_EN | + PCI_ERR_ROOT_CMD_NONFATAL_EN | + PCI_ERR_ROOT_CMD_FATAL_EN); + /* Clear the Root status register */ + pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig); + pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig); + } + /* WAR, only 128 MRRS is supported, force all EPs to support this value */ + pcie_set_readrq(dev, 128); + return 0; +} + +static void pcie_phy_rst(int pcie_port) +{ + pcie_phy_rst_assert(pcie_port); + pcie_phy_rst_deassert(pcie_port); + /* Make sure PHY PLL is stable */ + udelay(20); +} + +static int pcie_rc_initialize(int pcie_port) +{ + int i; + + pcie_rcu_endian_setup(pcie_port); + + pcie_ep_gpio_rst_init(pcie_port); + + /* + * XXX, PCIe elastic buffer bug will cause not to be detected. One more + * reset PCIe PHY will solve this issue + */ + for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) { + /* Disable PCIe PHY Analog part for sanity check */ + pcie_phy_pmu_disable(pcie_port); + pcie_phy_rst(pcie_port); + /* PCIe Core reset enabled, low active, sw programmed */ + pcie_core_rst_assert(pcie_port); + /* Put PCIe EP in reset status */ + pcie_device_rst_assert(pcie_port); + /* PCI PHY & Core reset disabled, high active, sw programmed */ + pcie_core_rst_deassert(pcie_port); + /* Already in a quiet state, program PLL, enable PHY, check ready bit */ + pcie_phy_clock_mode_setup(pcie_port); + /* Enable PCIe PHY and Clock */ + pcie_core_pmu_setup(pcie_port); + /* Clear status registers */ + pcie_status_register_clear(pcie_port); +#ifdef CONFIG_PCI_MSI + pcie_msi_init(pcie_port); +#endif /* CONFIG_PCI_MSI */ + pcie_rc_cfg_reg_setup(pcie_port); + + /* Once link is up, break out */ + if (pcie_app_loigc_setup(pcie_port) == 0) + break; + } + if (i >= IFX_PCIE_PHY_LOOP_CNT) { + printk(KERN_ERR "%s link up failed!!!!!\n", __func__); + return -EIO; + } + /* NB, don't increase ACK/NACK timer timeout value, which will cause a lot of COR errors */ + pcie_replay_time_update(pcie_port); + return 0; +} + +static int inline ifx_pcie_startup_port_nr(void) +{ + int pcie_port = IFX_PCIE_PORT0; + + pcie_port = IFX_PCIE_PORT0; + return pcie_port; +} + +/** + * \fn static int __init ifx_pcie_bios_init(void) + * \brief Initialize the IFX PCIe controllers + * + * \return -EIO PCIe PHY link is not up + * \return -ENOMEM Configuration/IO space failed to map + * \return 0 OK + * \ingroup IFX_PCIE_OS + */ +extern int (*ltqpci_plat_arch_init)(struct pci_dev *dev); +extern int (*ltqpci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin); +static int __devinit ltq_pcie_probe(struct platform_device *pdev) +{ + char ver_str[128] = {0}; + void __iomem *io_map_base; + int pcie_port; + int startup_port; + ltqpci_map_irq = ifx_pcie_bios_map_irq; + ltqpci_plat_arch_init = ifx_pcie_bios_plat_dev_init; + /* Enable AHB Master/ Slave */ + pcie_ahb_pmu_setup(); + + startup_port = ifx_pcie_startup_port_nr(); + + ltq_gpio_request(&pdev->dev, IFX_PCIE_GPIO_RESET, 0, 1, "pcie-reset"); + + for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){ + if (pcie_rc_initialize(pcie_port) == 0) { + /* Otherwise, warning will pop up */ + io_map_base = ioremap(PCIE_IO_PHY_PORT_TO_BASE(pcie_port), PCIE_IO_SIZE); + if (io_map_base == NULL) + return -ENOMEM; + ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base; + register_pci_controller(&ifx_pcie_controller[pcie_port].pcic); + /* XXX, clear error status */ + pcie_rc_core_int_init(pcie_port); + } + } + + printk(KERN_INFO "%s", ver_str); +return 0; +} + +static struct platform_driver ltq_pcie_driver = { + .probe = ltq_pcie_probe, + .driver = { + .name = "pcie-xway", + .owner = THIS_MODULE, + }, +}; + +int __init pciebios_init(void) +{ + return platform_driver_register(<q_pcie_driver); +} + +arch_initcall(pciebios_init); diff --git a/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq.h b/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq.h new file mode 100644 index 0000000000..d877c23a8a --- /dev/null +++ b/target/linux/lantiq/files/arch/mips/pci/pcie-lantiq.h @@ -0,0 +1,1305 @@ +/****************************************************************************** +** +** FILE NAME : ifxmips_pcie_reg.h +** PROJECT : IFX UEIP for VRX200 +** MODULES : PCIe module +** +** DATE : 02 Mar 2009 +** AUTHOR : Lei Chuanhua +** DESCRIPTION : PCIe Root Complex Driver +** COPYRIGHT : Copyright (c) 2009 +** Infineon Technologies AG +** Am Campeon 1-12, 85579 Neubiberg, Germany +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** HISTORY +** $Version $Date $Author $Comment +** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version +*******************************************************************************/ +#ifndef IFXMIPS_PCIE_REG_H +#define IFXMIPS_PCIE_REG_H +#include +#include +#include +#include +/*! + \file ifxmips_pcie_reg.h + \ingroup IFX_PCIE + \brief header file for PCIe module register definition +*/ +/* PCIe Address Mapping Base */ +#define PCIE_CFG_PHY_BASE 0x1D000000UL +#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) +#define PCIE_CFG_SIZE (8 * 1024 * 1024) + +#define PCIE_MEM_PHY_BASE 0x1C000000UL +#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) +#define PCIE_MEM_SIZE (16 * 1024 * 1024) +#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) + +#define PCIE_IO_PHY_BASE 0x1D800000UL +#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) +#define PCIE_IO_SIZE (1 * 1024 * 1024) +#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) + +#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) +#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) +#define PCIE_MSI_PHY_BASE 0x1F600000UL + +#define PCIE_PDI_PHY_BASE 0x1F106800UL +#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) +#define PCIE_PDI_SIZE 0x400 + +#define PCIE1_CFG_PHY_BASE 0x19000000UL +#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) +#define PCIE1_CFG_SIZE (8 * 1024 * 1024) + +#define PCIE1_MEM_PHY_BASE 0x18000000UL +#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) +#define PCIE1_MEM_SIZE (16 * 1024 * 1024) +#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) + +#define PCIE1_IO_PHY_BASE 0x19800000UL +#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) +#define PCIE1_IO_SIZE (1 * 1024 * 1024) +#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) + +#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) +#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) +#define PCIE1_MSI_PHY_BASE 0x1F400000UL + +#define PCIE1_PDI_PHY_BASE 0x1F700400UL +#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) +#define PCIE1_PDI_SIZE 0x400 + +#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) +#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) +#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) +#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) +#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) +#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) +#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) +#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) +#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) +#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) + +/* PCIe Application Logic Register */ +/* RC Core Control Register */ +#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) +/* This should be enabled after initializing configuratin registers + * Also should check link status retraining bit + */ +#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ + +/* RC Core Debug Register */ +#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) +#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ +#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ +#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 +#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ +#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 + +#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ +#define PCIE_RC_DR_PM_DEV_STATE_S 9 + +#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ +#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ +#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ + +/* Current Power State Definition */ +enum { + PCIE_RC_DR_D0 = 0, + PCIE_RC_DR_D1, /* Not supported */ + PCIE_RC_DR_D2, /* Not supported */ + PCIE_RC_DR_D3, + PCIE_RC_DR_UN, +}; + +/* PHY Link Status Register */ +#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) +#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ + +/* Electromechanical Control Register */ +#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) +#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ +#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ +#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ +#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ +#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ +#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ +#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ +#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ + +/* Interrupt Status Register */ +#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) +#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ +#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ +#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ +#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ +#define PCIE_IR_SR_AHB_LU_ERR_S 4 +#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ +#define PCIE_IR_SR_INT_MSG_NUM_S 9 +#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ +#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 + +/* Message Control Register */ +#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) +#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ +#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ + +#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) + +/* Vendor-Defined Message Requester ID Register */ +#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) +#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF +#define PCIE_VDM_RID_VDMRID_S 0 + +/* ASPM Control Register */ +#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) +#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ +#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ +#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ + +/* Vendor Message DW0 Register */ +#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) +#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ +#define PCIE_VM_MSG_DW0_TYPE_S 0 +#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ +#define PCIE_VM_MSG_DW0_FORMAT_S 5 +#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ +#define PCIE_VM_MSG_DW0_TC_S 12 +#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ +#define PCIE_VM_MSG_DW0_ATTR_S 18 +#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ +#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ +#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ +#define PCIE_VM_MSG_DW0_LEN_S 22 + +/* Format Definition */ +enum { + PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ + PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ + PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ + PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ +}; + +/* Traffic Class Definition */ +enum { + PCIE_VM_MSG_TC0 = 0, + PCIE_VM_MSG_TC1, + PCIE_VM_MSG_TC2, + PCIE_VM_MSG_TC3, + PCIE_VM_MSG_TC4, + PCIE_VM_MSG_TC5, + PCIE_VM_MSG_TC6, + PCIE_VM_MSG_TC7, +}; + +/* Attributes Definition */ +enum { + PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ + PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ + PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ + PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ +}; + +/* Payload Size Definition */ +#define PCIE_VM_MSG_LEN_MIN 0 +#define PCIE_VM_MSG_LEN_MAX 1024 + +/* Vendor Message DW1 Register */ +#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) +#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ +#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 +#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ +#define PCIE_VM_MSG_DW1_CODE_S 16 +#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ +#define PCIE_VM_MSG_DW1_TAG_S 24 + +#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) +#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) + +/* Vendor Message Request Register */ +#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) +#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ + + +/* AHB Slave Side Band Control Register */ +#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) +#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ +#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ +#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ +#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ +#define PCIE_AHB_SSB_REQ_ATTR_S 3 +#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ +#define PCIE_AHB_SSB_REQ_TC_S 5 + +/* AHB Master SideBand Ctrl Register */ +#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) +#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ +#define PCIE_AHB_MSB_RESP_ATTR_S 0 +#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ +#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ +#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ +#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ +#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ +#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 + +/* AHB Control Register, fixed bus enumeration exception */ +#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) +#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 + +/* Interrupt Enalbe Register */ +#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) +#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) +#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) + +/* PCIe interrupt enable/control/capture register definition */ +#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ +#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ +#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ +#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ +#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ +#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ +#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ +#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ +#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ +#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ +#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ +#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ +#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ +#define PCIE_IRN_INTA 0x00002000 /* INTA */ +#define PCIE_IRN_INTB 0x00004000 /* INTB */ +#define PCIE_IRN_INTC 0x00008000 /* INTC */ +#define PCIE_IRN_INTD 0x00010000 /* INTD */ +#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ + +#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ + PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ + PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ + PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ + PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) +/* PCIe RC Configuration Register */ +#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) + +/* Bit definition from pci_reg.h */ +#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) +#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) +#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ +/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ +#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ +#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ + +#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ +/* Bus Number Register bits */ +#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF +#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 +#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 +#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 +#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 +#define PCIE_PNR_SUB_BUS_NUM_S 16 + +/* IO Base/Limit Register bits */ +#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ +#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 +#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 +#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 +#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 +#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 +#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 + +/* Non-prefetchable Memory Base/Limit Register bit */ +#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ +#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 +#define PCIE_MBML_MEM_BASE_ADDR_S 4 +#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 +#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 + +/* Prefetchable Memory Base/Limit Register bit */ +#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ +#define PCIE_PMBL_64BIT_ADDR 0x00000001 +#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 +#define PCIE_PMBL_UPPER_12BIT_S 4 +#define PCIE_PMBL_E64MA 0x00010000 +#define PCIE_PMBL_END_ADDR 0xFFF00000 +#define PCIE_PMBL_END_ADDR_S 20 +#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ +#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ + +/* I/O Base/Limit Upper 16 bits register */ +#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ +#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF +#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 +#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 +#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 + +#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) +#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) + +/* Interrupt and Secondary Bridge Control Register */ +#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) + +#define PCIE_INTRBCTRL_INT_LINE 0x000000FF +#define PCIE_INTRBCTRL_INT_LINE_S 0 +#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 +#define PCIE_INTRBCTRL_INT_PIN_S 8 +#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ +#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ +#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ +#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ +#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ +#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ +/* Others are read only */ +enum { + PCIE_INTRBCTRL_INT_NON = 0, + PCIE_INTRBCTRL_INTA, + PCIE_INTRBCTRL_INTB, + PCIE_INTRBCTRL_INTC, + PCIE_INTRBCTRL_INTD, +}; + +#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) + +/* Power Management Control and Status Register */ +#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) + +#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ +#define PCIE_PM_CSR_POWER_STATE_S 0 +#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ +#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ +#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ + +/* MSI Capability Register for EP */ +#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) + +#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ +#define PCIE_MCAPR_MSI_CAP_ID_S 0 +#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ +#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 +#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ +#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ +#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 +#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ +#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 +#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ + +/* MSI Message Address Register */ +#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) + +#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ + +/* MSI Message Upper Address Register */ +#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) + +/* MSI Message Data Register */ +#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) + +#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ +#define PCIE_MD_DATA_S 0 + +/* PCI Express Capability Register */ +#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) + +#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ +#define PCIE_XCAP_ID_S 0 +#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ +#define PCIE_XCAP_NEXT_CAP_S 8 +#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ +#define PCIE_XCAP_VER_S 16 +#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ +#define PCIE_XCAP_DEV_PORT_TYPE_S 20 +#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ +#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ +#define PCIE_XCAP_MSG_INT_NUM_S 25 + +/* Device Capability Register */ +#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) + +#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ +#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 +#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ +#define PCIE_DCAP_PHANTOM_FUNC_S 3 +#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ +#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ +#define PCIE_DCAP_EP_L0S_LATENCY_S 6 +#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ +#define PCIE_DCAP_EP_L1_LATENCY_S 9 +#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ + +/* Maximum payload size supported */ +enum { + PCIE_MAX_PAYLOAD_128 = 0, + PCIE_MAX_PAYLOAD_256, + PCIE_MAX_PAYLOAD_512, + PCIE_MAX_PAYLOAD_1024, + PCIE_MAX_PAYLOAD_2048, + PCIE_MAX_PAYLOAD_4096, +}; + +/* Device Control and Status Register */ +#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) + +#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ +#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ +#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ +#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ +#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ +#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ +#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 +#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ +#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ +#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ +#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ +#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ +#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 +#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ +#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ +#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ +#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ +#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ +#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ + +#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ + PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ + PCIE_DCTLSYS_UR_REQ_EN) + +/* Link Capability Register */ +#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) +#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ +#define PCIE_LCAP_MAX_LINK_SPEED_S 0 +#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ +#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 +#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ +#define PCIE_LCAP_ASPM_LEVEL_S 10 +#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ +#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 +#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ +#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 +#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ +#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ +#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ +#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ +#define PCIE_LCAP_PORT_NUM_S 24 + +/* Maximum Length width definition */ +#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 +#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ +#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 +#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 +#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 +#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C +#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 +#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 + +/* Active State Link PM definition */ +enum { + PCIE_ASPM_RES0 = 0, + PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ + PCIE_ASPM_RES1, + PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ +}; + +/* L0s Exit Latency definition */ +enum { + PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ + PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ + PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ + PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ + PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ + PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ + PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ + PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ +}; + +/* L1 Exit Latency definition */ +enum { + PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ + PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ + PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ + PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ + PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ + PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ + PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ + PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ +}; + +/* Link Control and Status Register */ +#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) +#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ +#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 +#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ +#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ +#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ +#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ +#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ +#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ +#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ +#define PCIE_LCTLSTS_LINK_SPEED_S 16 +#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ +#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 +#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ +#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ +#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ + +/* Slot Capabilities Register */ +#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) + +/* Slot Capabilities */ +#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) + +/* Root Control and Capability Register */ +#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) +#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ +#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ +#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ +#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ +#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ + PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) +/* Root Status Register */ +#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) +#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ +#define PCIE_RSTS_PME_REQ_ID_S 0 +#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ +#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ + +/* PCI Express Enhanced Capability Header */ +#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) +#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ +#define PCIE_ENHANCED_CAP_ID_S 0 +#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ +#define PCIE_ENHANCED_CAP_VER_S 16 +#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ +#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 + +/* Uncorrectable Error Status Register */ +#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) +#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ +#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ +#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ +#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ +#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ +#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ +#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ +#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ +#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ +#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ +#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ +#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ + PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ + PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ + PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) + +/* Uncorrectable Error Mask Register, Mask means no report */ +#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) + +/* Uncorrectable Error Severity Register */ +#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) + +/* Correctable Error Status Register */ +#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) +#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ +#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ +#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ +#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ +#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ +#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ +#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ + PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) + +/* Correctable Error Mask Register */ +#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) + +/* Advanced Error Capabilities and Control Register */ +#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) +#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ +#define PCIE_AECCR_FIRST_ERR_PTR_S 0 +#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ +#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ +#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ +#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ + +/* Header Log Register 1 */ +#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) + +/* Header Log Register 2 */ +#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) + +/* Header Log Register 3 */ +#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) + +/* Header Log Register 4 */ +#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) + +/* Root Error Command Register */ +#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) +#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ +#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ +#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ +#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ + PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) + +/* Root Error Status Register */ +#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) +#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ +#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ +#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ +#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ +#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ +#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ +#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ +#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ +#define PCIE_RESR_AER_INT_MSG_NUM_S 27 + +/* Error Source Indentification Register */ +#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) +#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF +#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 +#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 +#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 + +/* VC Enhanced Capability Header */ +#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) + +/* Port VC Capability Register */ +#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) +#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ +#define PCIE_PVC1_EXT_VC_CNT_S 0 +#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ +#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 +#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ +#define PCIE_PVC1_REF_CLK_S 8 +#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ +#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 + +/* Extended Virtual Channel Count Defintion */ +#define PCIE_EXT_VC_CNT_MIN 0 +#define PCIE_EXT_VC_CNT_MAX 7 + +/* Port Arbitration Table Entry Size Definition */ +enum { + PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, + PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, + PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, + PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, +}; + +/* Port VC Capability Register 2 */ +#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) +#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ +#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ +#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ +#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ +#define PCIE_PVC2_VC_ARB_WRR 0x0000000F +#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ +#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 + +/* Port VC Control and Status Register */ +#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) +#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ +#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ +#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 +#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ + +/* VC0 Resource Capability Register */ +#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) +#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ +#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ +#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ +#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ +#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ +#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ +#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ + PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ + PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) + +#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ +#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ +#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 +#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ +#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 + +/* VC0 Resource Control Register */ +#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) +#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ +#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ +#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ +#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ +#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ +#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ +#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ +#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ +#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ + +#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ +#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ +#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 +#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ +#define PCIE_VC0_RC0_VC_ID_S 24 +#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ + +/* VC0 Resource Status Register */ +#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) +#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ +#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ + +/* Ack Latency Timer and Replay Timer Register */ +#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) +#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ +#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 +#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ +#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 + +/* Other Message Register */ +#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) + +/* Port Force Link Register */ +#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) +#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ +#define PCIE_PFLR_LINK_NUM_S 0 +#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ +#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ +#define PCIE_PFLR_LINK_STATE_S 16 +#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ +#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 + +/* Ack Frequency Register */ +#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) +#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ +#define PCIE_AFR_AF_S 0 +#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ +#define PCIE_AFR_FTS_NUM_S 8 +#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ +#define PCIE_AFR_COM_FTS_NUM_S 16 +#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ +#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 +#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ +#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 +#define PCIE_AFR_FTS_NUM_DEFAULT 32 +#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 +#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 + +/* Port Link Control Register */ +#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) +#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ +#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ +#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ +#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ +#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ +#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ +#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ +#define PCIE_PLCR_LINK_MODE_S 16 +#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ + +/* Lane Skew Register */ +#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) +#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ +#define PCIE_LSR_LANE_SKEW_NUM_S 0 +#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ +#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ +#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ + +/* Symbol Number Register */ +#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) +#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ +#define PCIE_SNR_TS_S 0 +#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ +#define PCIE_SNR_SKP_S 8 +#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ +#define PCIE_SNR_REPLAY_TIMER_S 14 +#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ +#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 +#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ +#define PCIE_SNR_FC_TIMER_S 28 + +/* Symbol Timer Register and Filter Mask Register 1 */ +#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) +#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ +#define PCIE_STRFMR_SKP_INTERVAL_S 0 +#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ +#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ +#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ +#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ +#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ +#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ +#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ +#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ +#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ +#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ +#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ +#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ +#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ +#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ +#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ +#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ +#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ + +#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ + +/* Filter Masker Register 2 */ +#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) +#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ +#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ + +/* Debug Register 0 */ +#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) + +/* Debug Register 1 */ +#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) + +/* Transmit Posted FC Credit Status Register */ +#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) +#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ +#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 +#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ +#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 + +/* Transmit Non-Posted FC Credit Status */ +#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) +#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ +#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 +#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ +#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 + +/* Transmit Complete FC Credit Status Register */ +#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) +#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ +#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 +#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ +#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 + +/* Queue Status Register */ +#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) +#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ +#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ +#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ + +/* VC Transmit Arbitration Register 1 */ +#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) +#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ +#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ +#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ +#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ + +/* VC Transmit Arbitration Register 2 */ +#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) +#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ +#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ +#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ +#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ + +/* VC0 Posted Receive Queue Control Register */ +#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) +#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ +#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 +#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ +#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 +#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ +#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 +#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ +#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ + +/* VC0 Non-Posted Receive Queue Control */ +#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) +#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ +#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 +#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ +#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 +#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ +#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 + +/* VC0 Completion Receive Queue Control */ +#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) +#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ +#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 +#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ +#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 +#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ +#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 + +/* Applicable to the above three registers */ +enum { + PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, + PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, + PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, +}; + +/* VC0 Posted Buffer Depth Register */ +#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) +#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ +#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 +#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ +#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 + +/* VC0 Non-Posted Buffer Depth Register */ +#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) +#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ +#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 +#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ +#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 + +/* VC0 Completion Buffer Depth Register */ +#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) +#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ +#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 +#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ +#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 + +/* PHY Status Register, all zeros in VR9 */ +#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) + +/* PHY Control Register, all zeros in VR9 */ +#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) + +/* + * PCIe PDI PHY register definition, suppose all the following + * stuff is confidential. + * XXX, detailed bit definition + */ +#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) +#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) +#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) +#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) +#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) +#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) +#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) +#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) +#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) +#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) +#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) + +#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) +#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) +#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) +#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) +#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) +#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) +#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) +#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) + +#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) +#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) +#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) +#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) +#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) +#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) +#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) + +#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) +#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) +#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) +#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) +#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) + +/* Interrupt related stuff */ +#define PCIE_LEGACY_DISABLE 0 +#define PCIE_LEGACY_INTA 1 +#define PCIE_LEGACY_INTB 2 +#define PCIE_LEGACY_INTC 3 +#define PCIE_LEGACY_INTD 4 +#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD + +#define PCIE_IRQ_LOCK(lock) do { \ + unsigned long flags; \ + spin_lock_irqsave(&(lock), flags); +#define PCIE_IRQ_UNLOCK(lock) \ + spin_unlock_irqrestore(&(lock), flags); \ +} while (0) + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) +#define IRQF_SHARED SA_SHIRQ +#endif + +#define PCIE_MSG_MSI 0x00000001 +#define PCIE_MSG_ISR 0x00000002 +#define PCIE_MSG_FIXUP 0x00000004 +#define PCIE_MSG_READ_CFG 0x00000008 +#define PCIE_MSG_WRITE_CFG 0x00000010 +#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) +#define PCIE_MSG_REG 0x00000020 +#define PCIE_MSG_INIT 0x00000040 +#define PCIE_MSG_ERR 0x00000080 +#define PCIE_MSG_PHY 0x00000100 +#define PCIE_MSG_ANY 0x000001ff + +#define IFX_PCIE_PORT0 0 +#define IFX_PCIE_PORT1 1 + +#ifdef CONFIG_IFX_PCIE_2ND_CORE +#define IFX_PCIE_CORE_NR 2 +#else +#define IFX_PCIE_CORE_NR 1 +#endif + +//#define IFX_PCIE_ERROR_INT + +//#define IFX_PCIE_DBG + +#if defined(IFX_PCIE_DBG) +#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ + if (g_pcie_debug_flag & (_m)) { \ + ifx_pcie_debug((_fmt), ##args); \ + } \ +} while (0) + +#define INLINE +#else +#define IFX_PCIE_PRINT(_m, _fmt, args...) \ + do {} while(0) +#define INLINE inline +#endif + +struct ifx_pci_controller { + struct pci_controller pcic; + + /* RC specific, per host bus information */ + u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ +}; + +typedef struct ifx_pcie_ir_irq { + const unsigned int irq; + const char name[16]; +}ifx_pcie_ir_irq_t; + +typedef struct ifx_pcie_legacy_irq{ + const u32 irq_bit; + const int irq; +}ifx_pcie_legacy_irq_t; + +typedef struct ifx_pcie_irq { + ifx_pcie_ir_irq_t ir_irq; + ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; +}ifx_pcie_irq_t; + +extern u32 g_pcie_debug_flag; +extern void ifx_pcie_debug(const char *fmt, ...); +extern void pcie_phy_clock_mode_setup(int pcie_port); +extern void pcie_msi_pic_init(int pcie_port); +extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); +extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); + + +#include +#include +#include +#include + +#include + +#define IFX_PCIE_GPIO_RESET 38 +#define IFX_REG_R32 ltq_r32 +#define IFX_REG_W32 ltq_w32 +#define CONFIG_IFX_PCIE_HW_SWAP +#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) +#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) +#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ + +#define IFX_RCU (KSEG1 | 0x1F203000) +#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ +#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ +#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ +#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE + +#define IFX_PMU1_MODULE_PCIE_PHY (0) +#define IFX_PMU1_MODULE_PCIE_CTRL (1) +#define IFX_PMU1_MODULE_PDI (4) +#define IFX_PMU1_MODULE_MSI (5) + +#define IFX_PMU_MODULE_PCIE_L0_CLK (31) + + +static inline void pcie_ep_gpio_rst_init(int pcie_port) +{ +} + +static inline void pcie_ahb_pmu_setup(void) +{ + struct clk *clk; + clk = clk_get_sys("ltq_pcie", "ahb"); + clk_enable(clk); + //ltq_pmu_enable(PMU_AHBM | PMU_AHBS); +} + +static inline void pcie_rcu_endian_setup(int pcie_port) +{ + u32 reg; + + reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); +#ifdef CONFIG_IFX_PCIE_HW_SWAP + reg |= IFX_RCU_AHB_BE_PCIE_M; + reg |= IFX_RCU_AHB_BE_PCIE_S; + reg &= ~IFX_RCU_AHB_BE_XBAR_M; +#else + reg |= IFX_RCU_AHB_BE_PCIE_M; + reg &= ~IFX_RCU_AHB_BE_PCIE_S; + reg &= ~IFX_RCU_AHB_BE_XBAR_M; +#endif /* CONFIG_IFX_PCIE_HW_SWAP */ + IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); + IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); +} + +static inline void pcie_phy_pmu_enable(int pcie_port) +{ + struct clk *clk; + clk = clk_get_sys("ltq_pcie", "phy"); + clk_enable(clk); + //ltq_pmu1_enable(1<PCIe and PDI endianness */ + reg |= IFX_RCU_AHB_BE_PCIE_PDI; + IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); +} + +static inline void pcie_pdi_pmu_enable(int pcie_port) +{ + struct clk *clk; + clk = clk_get_sys("ltq_pcie", "pdi"); + clk_enable(clk); + //ltq_pmu1_enable(1< 1) { + tbus_number -= pcibios_1st_host_bus_nr(); + } +#endif /* CONFIG_IFX_PCI */ + return tbus_number; +} + +static inline u32 +ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) +{ + struct pci_dev *pdev; + u32 tvalue = value; + + /* Sanity check */ + pdev = pci_get_slot(bus, devfn); + if (pdev == NULL) { + return tvalue; + } + + /* Only care about PCI bridge */ + if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { + return tvalue; + } + + if (read) { /* Read hack */ + #ifdef CONFIG_IFX_PCI + if (pcibios_host_nr() > 1) { + tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); + } + #endif /* CONFIG_IFX_PCI */ + } + else { /* Write hack */ + #ifdef CONFIG_IFX_PCI + if (pcibios_host_nr() > 1) { + tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); + } + #endif + } + return tvalue; +} + +#endif /* IFXMIPS_PCIE_VR9_H */ + diff --git a/target/linux/lantiq/files/drivers/i2c/busses/i2c-falcon.c b/target/linux/lantiq/files/drivers/i2c/busses/i2c-falcon.c new file mode 100644 index 0000000000..f97ddb601a --- /dev/null +++ b/target/linux/lantiq/files/drivers/i2c/busses/i2c-falcon.c @@ -0,0 +1,1040 @@ +/* + * Lantiq FALC(tm) ON - I2C bus adapter + * + * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Copyright (C) 2010 Thomas Langer + */ + +/* + * CURRENT ISSUES: + * - no high speed support + * - supports only master mode + * - ten bit mode is not tested (no slave devices) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* I2C Identification Register */ +/* Module ID */ +#define I2C_ID_ID_MASK 0x0000FF00 +/* field offset */ +#define I2C_ID_ID_OFFSET 8 +/* Revision */ +#define I2C_ID_REV_MASK 0x000000FF +/* field offset */ +#define I2C_ID_REV_OFFSET 0 + +/* I2C Error Interrupt Request Source Status Register */ +/* TXF_OFL */ +#define I2C_ERR_IRQSS_TXF_OFL 0x00000008 +/* TXF_UFL */ +#define I2C_ERR_IRQSS_TXF_UFL 0x00000004 +/* RXF_OFL */ +#define I2C_ERR_IRQSS_RXF_OFL 0x00000002 +/* RXF_UFL */ +#define I2C_ERR_IRQSS_RXF_UFL 0x00000001 + +/* I2C Bus Status Register */ +/* Bus Status */ +#define I2C_BUS_STAT_BS_MASK 0x00000003 +/* I2C Bus is free. */ +#define I2C_BUS_STAT_BS_FREE 0x00000000 +/* + * The device is working as master and has claimed the control + * on the I2C-bus (busy master). + */ +#define I2C_BUS_STAT_BS_BM 0x00000002 + +/* I2C Interrupt Clear Register */ +/* Clear */ +#define I2C_ICR_BREQ_INT_CLR 0x00000008 +/* Clear */ +#define I2C_ICR_LBREQ_INT_CLR 0x00000004 + +/* I2C RUN Control Register */ +/* Enable */ +#define I2C_RUN_CTRL_RUN_EN 0x00000001 + +/* I2C Kernel Clock Control Register */ +/* field offset */ +#define I2C_CLC_RMC_OFFSET 8 +/* Enable */ +#define I2C_IMSC_I2C_P_INT_EN 0x00000020 +/* Enable */ +#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010 +/* Enable */ +#define I2C_IMSC_BREQ_INT_EN 0x00000008 +/* Enable */ +#define I2C_IMSC_LBREQ_INT_EN 0x00000004 + +/* I2C Fractional Divider Configuration Register */ +/* field offset */ +#define I2C_FDIV_CFG_INC_OFFSET 16 +/* field offset */ +#define I2C_FDIV_CFG_DEC_OFFSET 0 + +/* I2C Fractional Divider (highspeed mode) Configuration Register */ +/* field offset */ +#define I2C_FDIV_HIGH_CFG_INC_OFFSET 16 +/* field offset */ +#define I2C_FDIV_HIGH_CFG_DEC_OFFSET 0 + +/* I2C Address Register */ +/* Enable */ +#define I2C_ADDR_CFG_SOPE_EN 0x00200000 +/* Enable */ +#define I2C_ADDR_CFG_SONA_EN 0x00100000 +/* Enable */ +#define I2C_ADDR_CFG_MnS_EN 0x00080000 + +/* I2C Protocol Interrupt Request Source Status Register */ +/* RX */ +#define I2C_P_IRQSS_RX 0x00000040 +/* TX_END */ +#define I2C_P_IRQSS_TX_END 0x00000020 +/* NACK */ +#define I2C_P_IRQSS_NACK 0x00000010 +/* AL */ +#define I2C_P_IRQSS_AL 0x00000008 + +/* I2C Raw Interrupt Status Register */ +/* Read: Interrupt occurred. */ +#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020 +/* Read: Interrupt occurred. */ +#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010 + +/* I2C End Data Control Register */ +/* + * Set End of Transmission - Note: Do not write '1' to this bit when bus is + * free. This will cause an abort after the first byte when a new transfer + * is started. + */ +#define I2C_ENDD_CTRL_SETEND 0x00000002 +/* TX FIFO Flow Control */ +#define I2C_FIFO_CFG_TXFC 0x00020000 +/* RX FIFO Flow Control */ +#define I2C_FIFO_CFG_RXFC 0x00010000 +/* Word aligned (character alignment of four characters) */ +#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000 +/* Word aligned (character alignment of four characters) */ +#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200 +/* 1 word */ +#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000 +/* 1 word */ +#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000 + + +/* I2C register structure */ +struct gpon_reg_i2c { + /* I2C Kernel Clock Control Register */ + unsigned int clc; /* 0x00000000 */ + /* Reserved */ + unsigned int res_0; /* 0x00000004 */ + /* I2C Identification Register */ + unsigned int id; /* 0x00000008 */ + /* Reserved */ + unsigned int res_1; /* 0x0000000C */ + /* + * I2C RUN Control Register - This register enables and disables the I2C + * peripheral. Before enabling, the I2C has to be configured properly. + * After enabling no configuration is possible + */ + unsigned int run_ctrl; /* 0x00000010 */ + /* + * I2C End Data Control Register - This register is used to either turn + * around the data transmission direction or to address another slave + * without sending a stop condition. Also the software can stop the + * slave-transmitter by sending a not-accolade when working as + * master-receiver or even stop data transmission immediately when + * operating as master-transmitter. The writing to the bits of this + * control register is only effective when in MASTER RECEIVES BYTES, + * MASTER TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state + */ + unsigned int endd_ctrl; /* 0x00000014 */ + /* + * I2C Fractional Divider Configuration Register - These register is + * used to program the fractional divider of the I2C bus. Before the + * peripheral is switched on by setting the RUN-bit the two (fixed) + * values for the two operating frequencies are programmed into these + * (configuration) registers. The Register FDIV_HIGH_CFG has the same + * layout as I2C_FDIV_CFG. + */ + unsigned int fdiv_cfg; /* 0x00000018 */ + /* + * I2C Fractional Divider (highspeed mode) Configuration Register + * These register is used to program the fractional divider of the I2C + * bus. Before the peripheral is switched on by setting the RUN-bit the + * two (fixed) values for the two operating frequencies are programmed + * into these (configuration) registers. The Register FDIV_CFG has the + * same layout as I2C_FDIV_CFG. + */ + unsigned int fdiv_high_cfg; /* 0x0000001C */ + /* I2C Address Configuration Register */ + unsigned int addr_cfg; /* 0x00000020 */ + /* + * I2C Bus Status Register - This register gives a status information + * of the I2C. This additional information can be used by the software + * to start proper actions. + */ + unsigned int bus_stat; /* 0x00000024 */ + /* I2C FIFO Configuration Register */ + unsigned int fifo_cfg; /* 0x00000028 */ + /* I2C Maximum Received Packet Size Register */ + unsigned int mrps_ctrl; /* 0x0000002C */ + /* I2C Received Packet Size Status Register */ + unsigned int rps_stat; /* 0x00000030 */ + /* I2C Transmit Packet Size Register */ + unsigned int tps_ctrl; /* 0x00000034 */ + /* I2C Filled FIFO Stages Status Register */ + unsigned int ffs_stat; /* 0x00000038 */ + /* Reserved */ + unsigned int res_2; /* 0x0000003C */ + /* I2C Timing Configuration Register */ + unsigned int tim_cfg; /* 0x00000040 */ + /* Reserved */ + unsigned int res_3[7]; /* 0x00000044 */ + /* I2C Error Interrupt Request Source Mask Register */ + unsigned int err_irqsm; /* 0x00000060 */ + /* I2C Error Interrupt Request Source Status Register */ + unsigned int err_irqss; /* 0x00000064 */ + /* I2C Error Interrupt Request Source Clear Register */ + unsigned int err_irqsc; /* 0x00000068 */ + /* Reserved */ + unsigned int res_4; /* 0x0000006C */ + /* I2C Protocol Interrupt Request Source Mask Register */ + unsigned int p_irqsm; /* 0x00000070 */ + /* I2C Protocol Interrupt Request Source Status Register */ + unsigned int p_irqss; /* 0x00000074 */ + /* I2C Protocol Interrupt Request Source Clear Register */ + unsigned int p_irqsc; /* 0x00000078 */ + /* Reserved */ + unsigned int res_5; /* 0x0000007C */ + /* I2C Raw Interrupt Status Register */ + unsigned int ris; /* 0x00000080 */ + /* I2C Interrupt Mask Control Register */ + unsigned int imsc; /* 0x00000084 */ + /* I2C Masked Interrupt Status Register */ + unsigned int mis; /* 0x00000088 */ + /* I2C Interrupt Clear Register */ + unsigned int icr; /* 0x0000008C */ + /* I2C Interrupt Set Register */ + unsigned int isr; /* 0x00000090 */ + /* I2C DMA Enable Register */ + unsigned int dmae; /* 0x00000094 */ + /* Reserved */ + unsigned int res_6[8154]; /* 0x00000098 */ + /* I2C Transmit Data Register */ + unsigned int txd; /* 0x00008000 */ + /* Reserved */ + unsigned int res_7[4095]; /* 0x00008004 */ + /* I2C Receive Data Register */ + unsigned int rxd; /* 0x0000C000 */ + /* Reserved */ + unsigned int res_8[4095]; /* 0x0000C004 */ +}; + +/* mapping for access macros */ +#define i2c ((struct gpon_reg_i2c *)priv->membase) +#define reg_r32(reg) __raw_readl(reg) +#define reg_w32(val, reg) __raw_writel(val, reg) +#define reg_w32_mask(clear, set, reg) \ + reg_w32((reg_r32(reg) & ~(clear)) | (set), reg) +#define reg_r32_table(reg, idx) reg_r32(&((uint32_t *)®)[idx]) +#define reg_w32_table(val, reg, idx) reg_w32(val, &((uint32_t *)®)[idx]) + +#define i2c_r32(reg) reg_r32(&i2c->reg) +#define i2c_w32(val, reg) reg_w32(val, &i2c->reg) +#define i2c_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &i2c->reg) + +#define DRV_NAME "i2c-falcon" +#define DRV_VERSION "1.01" + +#define FALCON_I2C_BUSY_TIMEOUT 20 /* ms */ + +#ifdef DEBUG +#define FALCON_I2C_XFER_TIMEOUT (25 * HZ) +#else +#define FALCON_I2C_XFER_TIMEOUT HZ +#endif +#if defined(DEBUG) && 0 +#define PRINTK(arg...) pr_info(arg) +#else +#define PRINTK(arg...) do {} while (0) +#endif + +#define FALCON_I2C_IMSC_DEFAULT_MASK (I2C_IMSC_I2C_P_INT_EN | \ + I2C_IMSC_I2C_ERR_INT_EN) + +#define FALCON_I2C_ARB_LOST (1 << 0) +#define FALCON_I2C_NACK (1 << 1) +#define FALCON_I2C_RX_UFL (1 << 2) +#define FALCON_I2C_RX_OFL (1 << 3) +#define FALCON_I2C_TX_UFL (1 << 4) +#define FALCON_I2C_TX_OFL (1 << 5) + +struct falcon_i2c { + struct mutex mutex; + + enum { + FALCON_I2C_MODE_100 = 1, + FALCON_I2C_MODE_400 = 2, + FALCON_I2C_MODE_3400 = 3 + } mode; /* current speed mode */ + + struct clk *clk; /* clock input for i2c hardware block */ + struct gpon_reg_i2c __iomem *membase; /* base of mapped registers */ + int irq_lb, irq_b, irq_err, irq_p; /* last burst, burst, error, + protocol IRQs */ + + struct i2c_adapter adap; + struct device *dev; + + struct completion cmd_complete; + + /* message transfer data */ + /* current message */ + struct i2c_msg *current_msg; + /* number of messages to handle */ + int msgs_num; + /* current buffer */ + u8 *msg_buf; + /* remaining length of current buffer */ + u32 msg_buf_len; + /* error status of the current transfer */ + int msg_err; + + /* master status codes */ + enum { + STATUS_IDLE, + STATUS_ADDR, /* address phase */ + STATUS_WRITE, + STATUS_READ, + STATUS_READ_END, + STATUS_STOP + } status; +}; + +static irqreturn_t falcon_i2c_isr(int irq, void *dev_id); + +static inline void enable_burst_irq(struct falcon_i2c *priv) +{ + i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc); +} +static inline void disable_burst_irq(struct falcon_i2c *priv) +{ + i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc); +} + +static void prepare_msg_send_addr(struct falcon_i2c *priv) +{ + struct i2c_msg *msg = priv->current_msg; + int rd = !!(msg->flags & I2C_M_RD); + u16 addr = msg->addr; + + /* new i2c_msg */ + priv->msg_buf = msg->buf; + priv->msg_buf_len = msg->len; + if (rd) + priv->status = STATUS_READ; + else + priv->status = STATUS_WRITE; + + /* send slave address */ + if (msg->flags & I2C_M_TEN) { + i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd); + i2c_w32(addr & 0xff, txd); + } else + i2c_w32((addr & 0x7f) << 1 | rd, txd); +} + +static void set_tx_len(struct falcon_i2c *priv) +{ + struct i2c_msg *msg = priv->current_msg; + int len = (msg->flags & I2C_M_TEN) ? 2 : 1; + + PRINTK("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? ('R') : ('T')); + + priv->status = STATUS_ADDR; + + if (!(msg->flags & I2C_M_RD)) { + len += msg->len; + } else { + /* set maximum received packet size (before rx int!) */ + i2c_w32(msg->len, mrps_ctrl); + } + i2c_w32(len, tps_ctrl); + enable_burst_irq(priv); +} + +static int falcon_i2c_hw_init(struct i2c_adapter *adap) +{ + struct falcon_i2c *priv = i2c_get_adapdata(adap); + + /* disable bus */ + i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); + +#ifndef DEBUG + /* set normal operation clock divider */ + i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc); +#else + /* for debugging a higher divider value! */ + i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc); +#endif + + /* set frequency */ + if (priv->mode == FALCON_I2C_MODE_100) { + dev_dbg(priv->dev, "set standard mode (100 kHz)\n"); + i2c_w32(0, fdiv_high_cfg); + i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET) | + (499 << I2C_FDIV_CFG_DEC_OFFSET), + fdiv_cfg); + } else if (priv->mode == FALCON_I2C_MODE_400) { + dev_dbg(priv->dev, "set fast mode (400 kHz)\n"); + i2c_w32(0, fdiv_high_cfg); + i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET) | + (124 << I2C_FDIV_CFG_DEC_OFFSET), + fdiv_cfg); + } else if (priv->mode == FALCON_I2C_MODE_3400) { + dev_dbg(priv->dev, "set high mode (3.4 MHz)\n"); + i2c_w32(0, fdiv_cfg); + /* TODO recalculate value for 100MHz input */ + i2c_w32((41 << I2C_FDIV_HIGH_CFG_INC_OFFSET) | + (152 << I2C_FDIV_HIGH_CFG_DEC_OFFSET), + fdiv_high_cfg); + } else { + dev_warn(priv->dev, "unknown mode\n"); + return -ENODEV; + } + + /* configure fifo */ + i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */ + I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */ + I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */ + I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */ + I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */ + I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */ + fifo_cfg); + + /* configure address */ + i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data + in the fifo */ + I2C_ADDR_CFG_SONA_EN | /* generate stop when NA received */ + I2C_ADDR_CFG_MnS_EN | /* we are master device */ + 0, /* our slave address (not used!) */ + addr_cfg); + + /* enable bus */ + i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl); + + return 0; +} + +static int falcon_i2c_wait_bus_not_busy(struct falcon_i2c *priv) +{ + int timeout = FALCON_I2C_BUSY_TIMEOUT; + + while ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) + != I2C_BUS_STAT_BS_FREE) { + if (timeout <= 0) { + dev_warn(priv->dev, "timeout waiting for bus ready\n"); + return -ETIMEDOUT; + } + timeout--; + mdelay(1); + } + + return 0; +} + +static void falcon_i2c_tx(struct falcon_i2c *priv, int last) +{ + if (priv->msg_buf_len && priv->msg_buf) { + i2c_w32(*priv->msg_buf, txd); + + if (--priv->msg_buf_len) + priv->msg_buf++; + else + priv->msg_buf = NULL; + } else + last = 1; + + if (last) + disable_burst_irq(priv); +} + +static void falcon_i2c_rx(struct falcon_i2c *priv, int last) +{ + u32 fifo_stat, timeout; + if (priv->msg_buf_len && priv->msg_buf) { + timeout = 5000000; + do { + fifo_stat = i2c_r32(ffs_stat); + } while (!fifo_stat && --timeout); + if (!timeout) { + last = 1; + PRINTK("\nrx timeout\n"); + goto err; + } + while (fifo_stat) { + *priv->msg_buf = i2c_r32(rxd); + if (--priv->msg_buf_len) + priv->msg_buf++; + else { + priv->msg_buf = NULL; + last = 1; + break; + } + #if 0 + fifo_stat = i2c_r32(ffs_stat); + #else + /* do not read more than burst size, otherwise no "last + burst" is generated and the transaction is blocked! */ + fifo_stat = 0; + #endif + } + } else { + last = 1; + } +err: + if (last) { + disable_burst_irq(priv); + + if (priv->status == STATUS_READ_END) { + /* do the STATUS_STOP and complete() here, as sometimes + the tx_end is already seen before this is finished */ + priv->status = STATUS_STOP; + complete(&priv->cmd_complete); + } else { + i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); + priv->status = STATUS_READ_END; + } + } +} + +static void falcon_i2c_xfer_init(struct falcon_i2c *priv) +{ + /* enable interrupts */ + i2c_w32(FALCON_I2C_IMSC_DEFAULT_MASK, imsc); + + /* trigger transfer of first msg */ + set_tx_len(priv); +} + +static void dump_msgs(struct i2c_msg msgs[], int num, int rx) +{ +#if defined(DEBUG) + int i, j; + pr_info("Messages %d %s\n", num, rx ? "out" : "in"); + for (i = 0; i < num; i++) { + pr_info("%2d %cX Msg(%d) addr=0x%X: ", i, + (msgs[i].flags & I2C_M_RD) ? ('R') : ('T'), + msgs[i].len, msgs[i].addr); + if (!(msgs[i].flags & I2C_M_RD) || rx) { + for (j = 0; j < msgs[i].len; j++) + printk("%02X ", msgs[i].buf[j]); + } + printk("\n"); + } +#endif +} + +static void falcon_i2c_release_bus(struct falcon_i2c *priv) +{ + if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM) + i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); +} + +static int falcon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], + int num) +{ + struct falcon_i2c *priv = i2c_get_adapdata(adap); + int ret; + + dev_dbg(priv->dev, "xfer %u messages\n", num); + dump_msgs(msgs, num, 0); + + mutex_lock(&priv->mutex); + + INIT_COMPLETION(priv->cmd_complete); + priv->current_msg = msgs; + priv->msgs_num = num; + priv->msg_err = 0; + priv->status = STATUS_IDLE; + + /* wait for the bus to become ready */ + ret = falcon_i2c_wait_bus_not_busy(priv); + if (ret) + goto done; + + while (priv->msgs_num) { + /* start the transfers */ + falcon_i2c_xfer_init(priv); + + /* wait for transfers to complete */ + ret = wait_for_completion_interruptible_timeout( + &priv->cmd_complete, FALCON_I2C_XFER_TIMEOUT); + if (ret == 0) { + dev_err(priv->dev, "controller timed out\n"); + falcon_i2c_hw_init(adap); + ret = -ETIMEDOUT; + goto done; + } else if (ret < 0) + goto done; + + if (priv->msg_err) { + if (priv->msg_err & FALCON_I2C_NACK) + ret = -ENXIO; + else + ret = -EREMOTEIO; + goto done; + } + if (--priv->msgs_num) + priv->current_msg++; + } + /* no error? */ + ret = num; + +done: + falcon_i2c_release_bus(priv); + + mutex_unlock(&priv->mutex); + + if (ret >= 0) + dump_msgs(msgs, num, 1); + + PRINTK("XFER ret %d\n", ret); + return ret; +} + +static irqreturn_t falcon_i2c_isr_burst(int irq, void *dev_id) +{ + struct falcon_i2c *priv = dev_id; + struct i2c_msg *msg = priv->current_msg; + int last = (irq == priv->irq_lb); + + if (last) + PRINTK("LB "); + else + PRINTK("B "); + + if (msg->flags & I2C_M_RD) { + switch (priv->status) { + case STATUS_ADDR: + PRINTK("X"); + prepare_msg_send_addr(priv); + disable_burst_irq(priv); + break; + case STATUS_READ: + case STATUS_READ_END: + PRINTK("R"); + falcon_i2c_rx(priv, last); + break; + default: + disable_burst_irq(priv); + PRINTK("Status R %d\n", priv->status); + break; + } + } else { + switch (priv->status) { + case STATUS_ADDR: + PRINTK("x"); + prepare_msg_send_addr(priv); + break; + case STATUS_WRITE: + PRINTK("w"); + falcon_i2c_tx(priv, last); + break; + default: + disable_burst_irq(priv); + PRINTK("Status W %d\n", priv->status); + break; + } + } + + i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr); + return IRQ_HANDLED; +} + +static void falcon_i2c_isr_prot(struct falcon_i2c *priv) +{ + u32 i_pro = i2c_r32(p_irqss); + + PRINTK("i2c-p"); + + /* not acknowledge */ + if (i_pro & I2C_P_IRQSS_NACK) { + priv->msg_err |= FALCON_I2C_NACK; + PRINTK(" nack"); + } + + /* arbitration lost */ + if (i_pro & I2C_P_IRQSS_AL) { + priv->msg_err |= FALCON_I2C_ARB_LOST; + PRINTK(" arb-lost"); + } + /* tx -> rx switch */ + if (i_pro & I2C_P_IRQSS_RX) + PRINTK(" rx"); + + /* tx end */ + if (i_pro & I2C_P_IRQSS_TX_END) + PRINTK(" txend"); + PRINTK("\n"); + + if (!priv->msg_err) { + /* tx -> rx switch */ + if (i_pro & I2C_P_IRQSS_RX) { + priv->status = STATUS_READ; + enable_burst_irq(priv); + } + if (i_pro & I2C_P_IRQSS_TX_END) { + if (priv->status == STATUS_READ) + priv->status = STATUS_READ_END; + else { + disable_burst_irq(priv); + priv->status = STATUS_STOP; + } + } + } + + i2c_w32(i_pro, p_irqsc); +} + +static irqreturn_t falcon_i2c_isr(int irq, void *dev_id) +{ + u32 i_raw, i_err = 0; + struct falcon_i2c *priv = dev_id; + + i_raw = i2c_r32(mis); + PRINTK("i_raw 0x%08X\n", i_raw); + + /* error interrupt */ + if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) { + i_err = i2c_r32(err_irqss); + PRINTK("i_err 0x%08X bus_stat 0x%04X\n", + i_err, i2c_r32(bus_stat)); + + /* tx fifo overflow (8) */ + if (i_err & I2C_ERR_IRQSS_TXF_OFL) + priv->msg_err |= FALCON_I2C_TX_OFL; + + /* tx fifo underflow (4) */ + if (i_err & I2C_ERR_IRQSS_TXF_UFL) + priv->msg_err |= FALCON_I2C_TX_UFL; + + /* rx fifo overflow (2) */ + if (i_err & I2C_ERR_IRQSS_RXF_OFL) + priv->msg_err |= FALCON_I2C_RX_OFL; + + /* rx fifo underflow (1) */ + if (i_err & I2C_ERR_IRQSS_RXF_UFL) + priv->msg_err |= FALCON_I2C_RX_UFL; + + i2c_w32(i_err, err_irqsc); + } + + /* protocol interrupt */ + if (i_raw & I2C_RIS_I2C_P_INT_INTOCC) + falcon_i2c_isr_prot(priv); + + if ((priv->msg_err) || (priv->status == STATUS_STOP)) + complete(&priv->cmd_complete); + + return IRQ_HANDLED; +} + +static u32 falcon_i2c_functionality(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | + I2C_FUNC_10BIT_ADDR | + I2C_FUNC_SMBUS_EMUL; +} + +static struct i2c_algorithm falcon_i2c_algorithm = { + .master_xfer = falcon_i2c_xfer, + .functionality = falcon_i2c_functionality, +}; + +static int __devinit falcon_i2c_probe(struct platform_device *pdev) +{ + int ret = 0; + struct falcon_i2c *priv; + struct i2c_adapter *adap; + struct resource *mmres, *ioarea, + *irqres_lb, *irqres_b, *irqres_err, *irqres_p; + struct clk *clk; + + dev_dbg(&pdev->dev, "probing\n"); + + mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irqres_lb = platform_get_resource_byname(pdev, IORESOURCE_IRQ, + "i2c_lb"); + irqres_b = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_b"); + irqres_err = platform_get_resource_byname(pdev, IORESOURCE_IRQ, + "i2c_err"); + irqres_p = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_p"); + + if (!mmres || !irqres_lb || !irqres_b || !irqres_err || !irqres_p) { + dev_err(&pdev->dev, "no resources\n"); + return -ENODEV; + } + + clk = clk_get_fpi(); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "failed to get fpi clk\n"); + return -ENOENT; + } + + if (clk_get_rate(clk) != 100000000) { + dev_err(&pdev->dev, "input clock is not 100MHz\n"); + return -ENOENT; + } + clk = clk_get(&pdev->dev, NULL); + if (IS_ERR(clk)) { + dev_err(&pdev->dev, "failed to get i2c clk\n"); + return -ENOENT; + } + clk_activate(clk); + /* allocate private data */ + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) { + dev_err(&pdev->dev, "can't allocate private data\n"); + return -ENOMEM; + } + + adap = &priv->adap; + i2c_set_adapdata(adap, priv); + adap->owner = THIS_MODULE; + adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; + strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name)); + adap->algo = &falcon_i2c_algorithm; + + priv->mode = FALCON_I2C_MODE_100; + priv->clk = clk; + priv->dev = &pdev->dev; + + init_completion(&priv->cmd_complete); + mutex_init(&priv->mutex); + + if (ltq_gpio_request(&pdev->dev, 107, 0, 0, DRV_NAME":sda") || + ltq_gpio_request(&pdev->dev, 108, 0, 0, DRV_NAME":scl")) + { + dev_err(&pdev->dev, "I2C gpios not available\n"); + ret = -ENXIO; + goto err_free_priv; + } + + ioarea = request_mem_region(mmres->start, resource_size(mmres), + pdev->name); + + if (ioarea == NULL) { + dev_err(&pdev->dev, "I2C region already claimed\n"); + ret = -ENXIO; + goto err_free_gpio; + } + + /* map memory */ + priv->membase = ioremap_nocache(mmres->start & ~KSEG1, + resource_size(mmres)); + if (priv->membase == NULL) { + ret = -ENOMEM; + goto err_release_region; + } + + priv->irq_lb = irqres_lb->start; + ret = request_irq(priv->irq_lb, falcon_i2c_isr_burst, IRQF_DISABLED, + irqres_lb->name, priv); + if (ret) { + dev_err(&pdev->dev, "can't get last burst IRQ %d\n", + irqres_lb->start); + ret = -ENODEV; + goto err_unmap_mem; + } + + priv->irq_b = irqres_b->start; + ret = request_irq(priv->irq_b, falcon_i2c_isr_burst, IRQF_DISABLED, + irqres_b->name, priv); + if (ret) { + dev_err(&pdev->dev, "can't get burst IRQ %d\n", + irqres_b->start); + ret = -ENODEV; + goto err_free_lb_irq; + } + + priv->irq_err = irqres_err->start; + ret = request_irq(priv->irq_err, falcon_i2c_isr, IRQF_DISABLED, + irqres_err->name, priv); + if (ret) { + dev_err(&pdev->dev, "can't get error IRQ %d\n", + irqres_err->start); + ret = -ENODEV; + goto err_free_b_irq; + } + + priv->irq_p = irqres_p->start; + ret = request_irq(priv->irq_p, falcon_i2c_isr, IRQF_DISABLED, + irqres_p->name, priv); + if (ret) { + dev_err(&pdev->dev, "can't get protocol IRQ %d\n", + irqres_p->start); + ret = -ENODEV; + goto err_free_err_irq; + } + + dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase); + dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres_lb->start, + irqres_b->start, irqres_err->start, irqres_p->start); + + /* add our adapter to the i2c stack */ + ret = i2c_add_numbered_adapter(adap); + if (ret) { + dev_err(&pdev->dev, "can't register I2C adapter\n"); + goto err_free_p_irq; + } + + platform_set_drvdata(pdev, priv); + i2c_set_adapdata(adap, priv); + + /* print module version information */ + dev_dbg(&pdev->dev, "module id=%u revision=%u\n", + (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET, + (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET); + + /* initialize HW */ + ret = falcon_i2c_hw_init(adap); + if (ret) { + dev_err(&pdev->dev, "can't configure adapter\n"); + goto err_remove_adapter; + } + + dev_info(&pdev->dev, "version %s\n", DRV_VERSION); + + return 0; + +err_remove_adapter: + i2c_del_adapter(adap); + platform_set_drvdata(pdev, NULL); + +err_free_p_irq: + free_irq(priv->irq_p, priv); + +err_free_err_irq: + free_irq(priv->irq_err, priv); + +err_free_b_irq: + free_irq(priv->irq_b, priv); + +err_free_lb_irq: + free_irq(priv->irq_lb, priv); + +err_unmap_mem: + iounmap(priv->membase); + +err_release_region: + release_mem_region(mmres->start, resource_size(mmres)); + +err_free_gpio: + gpio_free(108); + gpio_free(107); + +err_free_priv: + kfree(priv); + + return ret; +} + +static int __devexit falcon_i2c_remove(struct platform_device *pdev) +{ + struct falcon_i2c *priv = platform_get_drvdata(pdev); + struct resource *mmres; + + /* disable bus */ + i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); + + /* remove driver */ + platform_set_drvdata(pdev, NULL); + i2c_del_adapter(&priv->adap); + + free_irq(priv->irq_lb, priv); + free_irq(priv->irq_b, priv); + free_irq(priv->irq_err, priv); + free_irq(priv->irq_p, priv); + + iounmap(priv->membase); + + gpio_free(108); + gpio_free(107); + + kfree(priv); + + mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(mmres->start, resource_size(mmres)); + + dev_dbg(&pdev->dev, "removed\n"); + + return 0; +} + +static struct platform_driver falcon_i2c_driver = { + .probe = falcon_i2c_probe, + .remove = __devexit_p(falcon_i2c_remove), + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init falcon_i2c_init(void) +{ + int ret; + + ret = platform_driver_register(&falcon_i2c_driver); + + if (ret) + pr_debug(DRV_NAME ": can't register platform driver\n"); + + return ret; +} + +static void __exit falcon_i2c_exit(void) +{ + platform_driver_unregister(&falcon_i2c_driver); +} + +module_init(falcon_i2c_init); +module_exit(falcon_i2c_exit); + +MODULE_DESCRIPTION("Lantiq FALC(tm) ON - I2C bus adapter"); +MODULE_ALIAS("platform:" DRV_NAME); +MODULE_LICENSE("GPL"); +MODULE_VERSION(DRV_VERSION); diff --git a/target/linux/lantiq/files/drivers/net/ethernet/lantiq_vrx200.c b/target/linux/lantiq/files/drivers/net/ethernet/lantiq_vrx200.c new file mode 100644 index 0000000000..d79d3803cc --- /dev/null +++ b/target/linux/lantiq/files/drivers/net/ethernet/lantiq_vrx200.c @@ -0,0 +1,1358 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2011 John Crispin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include + +#define LTQ_SWITCH_BASE 0x1E108000 +#define LTQ_SWITCH_CORE_BASE LTQ_SWITCH_BASE +#define LTQ_SWITCH_TOP_PDI_BASE LTQ_SWITCH_CORE_BASE +#define LTQ_SWITCH_BM_PDI_BASE (LTQ_SWITCH_CORE_BASE + 4 * 0x40) +#define LTQ_SWITCH_MAC_PDI_0_BASE (LTQ_SWITCH_CORE_BASE + 4 * 0x900) +#define LTQ_SWITCH_MAC_PDI_X_BASE(x) (LTQ_SWITCH_MAC_PDI_0_BASE + x * 0x30) +#define LTQ_SWITCH_TOPLEVEL_BASE (LTQ_SWITCH_BASE + 4 * 0xC40) +#define LTQ_SWITCH_MDIO_PDI_BASE (LTQ_SWITCH_TOPLEVEL_BASE) +#define LTQ_SWITCH_MII_PDI_BASE (LTQ_SWITCH_TOPLEVEL_BASE + 4 * 0x36) +#define LTQ_SWITCH_PMAC_PDI_BASE (LTQ_SWITCH_TOPLEVEL_BASE + 4 * 0x82) + +#define LTQ_ETHSW_MAC_CTRL0_PADEN (1 << 8) +#define LTQ_ETHSW_MAC_CTRL0_FCS (1 << 7) +#define LTQ_ETHSW_MAC_CTRL1_SHORTPRE (1 << 8) +#define LTQ_ETHSW_MAC_CTRL2_MLEN (1 << 3) +#define LTQ_ETHSW_MAC_CTRL2_LCHKL (1 << 2) +#define LTQ_ETHSW_MAC_CTRL2_LCHKS_DIS 0 +#define LTQ_ETHSW_MAC_CTRL2_LCHKS_UNTAG 1 +#define LTQ_ETHSW_MAC_CTRL2_LCHKS_TAG 2 +#define LTQ_ETHSW_MAC_CTRL6_RBUF_DLY_WP_SHIFT 9 +#define LTQ_ETHSW_MAC_CTRL6_RXBUF_BYPASS (1 << 6) +#define LTQ_ETHSW_GLOB_CTRL_SE (1 << 15) +#define LTQ_ETHSW_MDC_CFG1_MCEN (1 << 8) +#define LTQ_ETHSW_PMAC_HD_CTL_FC (1 << 10) +#define LTQ_ETHSW_PMAC_HD_CTL_RC (1 << 4) +#define LTQ_ETHSW_PMAC_HD_CTL_AC (1 << 2) +#define ADVERTIZE_MPD (1 << 10) + +#define MDIO_DEVAD_NONE (-1) + +#define LTQ_ETH_RX_BUFFER_CNT PKTBUFSRX + +#define LTQ_MDIO_DRV_NAME "ltq-mdio" +#define LTQ_ETH_DRV_NAME "ltq-eth" + +#define LTQ_ETHSW_MAX_GMAC 1 +#define LTQ_ETHSW_PMAC 1 + +#define ltq_setbits(a, set) \ + ltq_w32(ltq_r32(a) | (set), a) + +enum ltq_reset_modules { + LTQ_RESET_CORE, + LTQ_RESET_DMA, + LTQ_RESET_ETH, + LTQ_RESET_PHY, + LTQ_RESET_HARD, + LTQ_RESET_SOFT, +}; + +static inline void +dbg_ltq_writel(void *a, unsigned int b) +{ + ltq_w32(b, a); +} + +int ltq_reset_once(enum ltq_reset_modules module, ulong usec); + +struct ltq_ethsw_mac_pdi_x_regs { + u32 pstat; /* Port status */ + u32 pisr; /* Interrupt status */ + u32 pier; /* Interrupt enable */ + u32 ctrl_0; /* Control 0 */ + u32 ctrl_1; /* Control 1 */ + u32 ctrl_2; /* Control 2 */ + u32 ctrl_3; /* Control 3 */ + u32 ctrl_4; /* Control 4 */ + u32 ctrl_5; /* Control 5 */ + u32 ctrl_6; /* Control 6 */ + u32 bufst; /* TX/RX buffer control */ + u32 testen; /* Test enable */ +}; + +struct ltq_ethsw_mac_pdi_regs { + struct ltq_ethsw_mac_pdi_x_regs mac[12]; +}; + +struct ltq_ethsw_mdio_pdi_regs { + u32 glob_ctrl; /* Global control 0 */ + u32 rsvd0[7]; + u32 mdio_ctrl; /* MDIO control */ + u32 mdio_read; /* MDIO read data */ + u32 mdio_write; /* MDIO write data */ + u32 mdc_cfg_0; /* MDC clock configuration 0 */ + u32 mdc_cfg_1; /* MDC clock configuration 1 */ + u32 rsvd[3]; + u32 phy_addr_5; /* PHY address port 5 */ + u32 phy_addr_4; /* PHY address port 4 */ + u32 phy_addr_3; /* PHY address port 3 */ + u32 phy_addr_2; /* PHY address port 2 */ + u32 phy_addr_1; /* PHY address port 1 */ + u32 phy_addr_0; /* PHY address port 0 */ + u32 mdio_stat_0; /* MDIO PHY polling status port 0 */ + u32 mdio_stat_1; /* MDIO PHY polling status port 1 */ + u32 mdio_stat_2; /* MDIO PHY polling status port 2 */ + u32 mdio_stat_3; /* MDIO PHY polling status port 3 */ + u32 mdio_stat_4; /* MDIO PHY polling status port 4 */ + u32 mdio_stat_5; /* MDIO PHY polling status port 5 */ +}; + +struct ltq_ethsw_mii_pdi_regs { + u32 mii_cfg0; /* xMII port 0 configuration */ + u32 pcdu0; /* Port 0 clock delay configuration */ + u32 mii_cfg1; /* xMII port 1 configuration */ + u32 pcdu1; /* Port 1 clock delay configuration */ + u32 mii_cfg2; /* xMII port 2 configuration */ + u32 rsvd0; + u32 mii_cfg3; /* xMII port 3 configuration */ + u32 rsvd1; + u32 mii_cfg4; /* xMII port 4 configuration */ + u32 rsvd2; + u32 mii_cfg5; /* xMII port 5 configuration */ + u32 pcdu5; /* Port 5 clock delay configuration */ +}; + +struct ltq_ethsw_pmac_pdi_regs { + u32 hd_ctl; /* PMAC header control */ + u32 tl; /* PMAC type/length */ + u32 sa1; /* PMAC source address 1 */ + u32 sa2; /* PMAC source address 2 */ + u32 sa3; /* PMAC source address 3 */ + u32 da1; /* PMAC destination address 1 */ + u32 da2; /* PMAC destination address 2 */ + u32 da3; /* PMAC destination address 3 */ + u32 vlan; /* PMAC VLAN */ + u32 rx_ipg; /* PMAC interpacket gap in RX direction */ + u32 st_etype; /* PMAC special tag ethertype */ + u32 ewan; /* PMAC ethernet WAN group */ +}; + +struct ltq_mdio_phy_addr_reg { + union { + struct { + unsigned rsvd:1; + unsigned lnkst:2; /* Link status control */ + unsigned speed:2; /* Speed control */ + unsigned fdup:2; /* Full duplex control */ + unsigned fcontx:2; /* Flow control mode TX */ + unsigned fconrx:2; /* Flow control mode RX */ + unsigned addr:5; /* PHY address */ + } bits; + u16 val; + }; +}; + +enum ltq_mdio_phy_addr_lnkst { + LTQ_MDIO_PHY_ADDR_LNKST_AUTO = 0, + LTQ_MDIO_PHY_ADDR_LNKST_UP = 1, + LTQ_MDIO_PHY_ADDR_LNKST_DOWN = 2, +}; + +enum ltq_mdio_phy_addr_speed { + LTQ_MDIO_PHY_ADDR_SPEED_M10 = 0, + LTQ_MDIO_PHY_ADDR_SPEED_M100 = 1, + LTQ_MDIO_PHY_ADDR_SPEED_G1 = 2, + LTQ_MDIO_PHY_ADDR_SPEED_AUTO = 3, +}; + +enum ltq_mdio_phy_addr_fdup { + LTQ_MDIO_PHY_ADDR_FDUP_AUTO = 0, + LTQ_MDIO_PHY_ADDR_FDUP_ENABLE = 1, + LTQ_MDIO_PHY_ADDR_FDUP_DISABLE = 3, +}; + +enum ltq_mdio_phy_addr_fcon { + LTQ_MDIO_PHY_ADDR_FCON_AUTO = 0, + LTQ_MDIO_PHY_ADDR_FCON_ENABLE = 1, + LTQ_MDIO_PHY_ADDR_FCON_DISABLE = 3, +}; + +struct ltq_mii_mii_cfg_reg { + union { + struct { + unsigned res:1; /* Hardware reset */ + unsigned en:1; /* xMII interface enable */ + unsigned isol:1; /* xMII interface isolate */ + unsigned ldclkdis:1; /* Link down clock disable */ + unsigned rsvd:1; + unsigned crs:2; /* CRS sensitivity config */ + unsigned rgmii_ibs:1; /* RGMII In Band status */ + unsigned rmii:1; /* RMII ref clock direction */ + unsigned miirate:3; /* xMII interface clock rate */ + unsigned miimode:4; /* xMII interface mode */ + } bits; + u16 val; + }; +}; + +enum ltq_mii_mii_cfg_miirate { + LTQ_MII_MII_CFG_MIIRATE_M2P5 = 0, + LTQ_MII_MII_CFG_MIIRATE_M25 = 1, + LTQ_MII_MII_CFG_MIIRATE_M125 = 2, + LTQ_MII_MII_CFG_MIIRATE_M50 = 3, + LTQ_MII_MII_CFG_MIIRATE_AUTO = 4, +}; + +enum ltq_mii_mii_cfg_miimode { + LTQ_MII_MII_CFG_MIIMODE_MIIP = 0, + LTQ_MII_MII_CFG_MIIMODE_MIIM = 1, + LTQ_MII_MII_CFG_MIIMODE_RMIIP = 2, + LTQ_MII_MII_CFG_MIIMODE_RMIIM = 3, + LTQ_MII_MII_CFG_MIIMODE_RGMII = 4, +}; + +struct ltq_eth_priv { + struct ltq_dma_device *dma_dev; + struct mii_dev *bus; + struct eth_device *dev; + struct phy_device *phymap[LTQ_ETHSW_MAX_GMAC]; + int rx_num; +}; + +enum ltq_mdio_mbusy { + LTQ_MDIO_MBUSY_IDLE = 0, + LTQ_MDIO_MBUSY_BUSY = 1, +}; + +enum ltq_mdio_op { + LTQ_MDIO_OP_WRITE = 1, + LTQ_MDIO_OP_READ = 2, +}; + +struct ltq_mdio_access { + union { + struct { + unsigned rsvd:3; + unsigned mbusy:1; + unsigned op:2; + unsigned phyad:5; + unsigned regad:5; + } bits; + u16 val; + }; +}; + +enum LTQ_ETH_PORT_FLAGS { + LTQ_ETH_PORT_NONE = 0, + LTQ_ETH_PORT_PHY = 1, + LTQ_ETH_PORT_SWITCH = (1 << 1), + LTQ_ETH_PORT_MAC = (1 << 2), +}; + +struct ltq_eth_port_config { + u8 num; + u8 phy_addr; + u16 flags; + phy_interface_t phy_if; +}; + +struct ltq_eth_board_config { + const struct ltq_eth_port_config *ports; + int num_ports; +}; + +static const struct ltq_eth_port_config eth_port_config[] = { + /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */ + { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, + /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */ + { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, +}; + +static const struct ltq_eth_board_config board_config = { + .ports = eth_port_config, + .num_ports = ARRAY_SIZE(eth_port_config), +}; + +static struct ltq_ethsw_mac_pdi_regs *ltq_ethsw_mac_pdi_regs = + (struct ltq_ethsw_mac_pdi_regs *) CKSEG1ADDR(LTQ_SWITCH_MAC_PDI_0_BASE); + +static struct ltq_ethsw_mdio_pdi_regs *ltq_ethsw_mdio_pdi_regs = + (struct ltq_ethsw_mdio_pdi_regs *) CKSEG1ADDR(LTQ_SWITCH_MDIO_PDI_BASE); + +static struct ltq_ethsw_mii_pdi_regs *ltq_ethsw_mii_pdi_regs = + (struct ltq_ethsw_mii_pdi_regs *) CKSEG1ADDR(LTQ_SWITCH_MII_PDI_BASE); + +static struct ltq_ethsw_pmac_pdi_regs *ltq_ethsw_pmac_pdi_regs = + (struct ltq_ethsw_pmac_pdi_regs *) CKSEG1ADDR(LTQ_SWITCH_PMAC_PDI_BASE); + + +#define MAX_DMA_CHAN 0x8 +#define MAX_DMA_CRC_LEN 0x4 +#define MAX_DMA_DATA_LEN 0x600 + +/* use 2 static channels for TX/RX + depending on the SoC we need to use different DMA channels for ethernet */ +#define LTQ_ETOP_TX_CHANNEL 1 +#define LTQ_ETOP_RX_CHANNEL 0 + +#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) +#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) + +#define DRV_VERSION "1.0" + +static void __iomem *ltq_vrx200_membase; + +struct ltq_vrx200_chan { + int idx; + int tx_free; + struct net_device *netdev; + struct napi_struct napi; + struct ltq_dma_channel dma; + struct sk_buff *skb[LTQ_DESC_NUM]; +}; + +struct ltq_vrx200_priv { + struct net_device *netdev; + struct ltq_eth_data *pldata; + struct resource *res; + + struct mii_bus *mii_bus; + struct phy_device *phydev; + + struct ltq_vrx200_chan ch[MAX_DMA_CHAN]; + int tx_free[MAX_DMA_CHAN >> 1]; + + spinlock_t lock; + + struct clk *clk_ppe; +}; + +static int ltq_vrx200_mdio_wr(struct mii_bus *bus, int phy_addr, + int phy_reg, u16 phy_data); + +static int +ltq_vrx200_alloc_skb(struct ltq_vrx200_chan *ch) +{ + ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN); + if (!ch->skb[ch->dma.desc]) + return -ENOMEM; + ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL, + ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN, + DMA_FROM_DEVICE); + ch->dma.desc_base[ch->dma.desc].addr = + CPHYSADDR(ch->skb[ch->dma.desc]->data); + ch->dma.desc_base[ch->dma.desc].ctl = + LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | + MAX_DMA_DATA_LEN; + skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN); + return 0; +} + +static void +ltq_vrx200_hw_receive(struct ltq_vrx200_chan *ch) +{ + struct ltq_vrx200_priv *priv = netdev_priv(ch->netdev); + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; + struct sk_buff *skb = ch->skb[ch->dma.desc]; + int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN; + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + if (ltq_vrx200_alloc_skb(ch)) { + netdev_err(ch->netdev, + "failed to allocate new rx buffer, stopping DMA\n"); + ltq_dma_close(&ch->dma); + } + ch->dma.desc++; + ch->dma.desc %= LTQ_DESC_NUM; + spin_unlock_irqrestore(&priv->lock, flags); + + skb_put(skb, len); + skb->dev = ch->netdev; + skb->protocol = eth_type_trans(skb, ch->netdev); + netif_receive_skb(skb); +} + +static int +ltq_vrx200_poll_rx(struct napi_struct *napi, int budget) +{ + struct ltq_vrx200_chan *ch = container_of(napi, + struct ltq_vrx200_chan, napi); + struct ltq_vrx200_priv *priv = netdev_priv(ch->netdev); + int rx = 0; + int complete = 0; + unsigned long flags; + + while ((rx < budget) && !complete) { + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; + + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { + ltq_vrx200_hw_receive(ch); + rx++; + } else { + complete = 1; + } + } + if (complete || !rx) { + napi_complete(&ch->napi); + spin_lock_irqsave(&priv->lock, flags); + ltq_dma_ack_irq(&ch->dma); + spin_unlock_irqrestore(&priv->lock, flags); + } + return rx; +} + +static int +ltq_vrx200_poll_tx(struct napi_struct *napi, int budget) +{ + struct ltq_vrx200_chan *ch = + container_of(napi, struct ltq_vrx200_chan, napi); + struct ltq_vrx200_priv *priv = netdev_priv(ch->netdev); + struct netdev_queue *txq = + netdev_get_tx_queue(ch->netdev, ch->idx >> 1); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); + while ((ch->dma.desc_base[ch->tx_free].ctl & + (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { + dev_kfree_skb_any(ch->skb[ch->tx_free]); + ch->skb[ch->tx_free] = NULL; + memset(&ch->dma.desc_base[ch->tx_free], 0, + sizeof(struct ltq_dma_desc)); + ch->tx_free++; + ch->tx_free %= LTQ_DESC_NUM; + } + spin_unlock_irqrestore(&priv->lock, flags); + + if (netif_tx_queue_stopped(txq)) + netif_tx_start_queue(txq); + napi_complete(&ch->napi); + spin_lock_irqsave(&priv->lock, flags); + ltq_dma_ack_irq(&ch->dma); + spin_unlock_irqrestore(&priv->lock, flags); + return 1; +} + +static irqreturn_t +ltq_vrx200_dma_irq(int irq, void *_priv) +{ + struct ltq_vrx200_priv *priv = _priv; + int ch = irq - LTQ_DMA_ETOP; + + napi_schedule(&priv->ch[ch].napi); + return IRQ_HANDLED; +} + +static void +ltq_vrx200_free_channel(struct net_device *dev, struct ltq_vrx200_chan *ch) +{ + struct ltq_vrx200_priv *priv = netdev_priv(dev); + + ltq_dma_free(&ch->dma); + if (ch->dma.irq) + free_irq(ch->dma.irq, priv); + if (IS_RX(ch->idx)) { + int desc; + for (desc = 0; desc < LTQ_DESC_NUM; desc++) + dev_kfree_skb_any(ch->skb[ch->dma.desc]); + } +} + +static void +ltq_vrx200_hw_exit(struct net_device *dev) +{ + struct ltq_vrx200_priv *priv = netdev_priv(dev); + int i; + + clk_disable(priv->clk_ppe); + + for (i = 0; i < MAX_DMA_CHAN; i++) + if (IS_TX(i) || IS_RX(i)) + ltq_vrx200_free_channel(dev, &priv->ch[i]); +} + +static void *ltq_eth_phy_addr_reg(int num) +{ + switch (num) { + case 0: + return <q_ethsw_mdio_pdi_regs->phy_addr_0; + case 1: + return <q_ethsw_mdio_pdi_regs->phy_addr_1; + case 2: + return <q_ethsw_mdio_pdi_regs->phy_addr_2; + case 3: + return <q_ethsw_mdio_pdi_regs->phy_addr_3; + case 4: + return <q_ethsw_mdio_pdi_regs->phy_addr_4; + case 5: + return <q_ethsw_mdio_pdi_regs->phy_addr_5; + } + + return NULL; +} + +static void *ltq_eth_mii_cfg_reg(int num) +{ + switch (num) { + case 0: + return <q_ethsw_mii_pdi_regs->mii_cfg0; + case 1: + return <q_ethsw_mii_pdi_regs->mii_cfg1; + case 2: + return <q_ethsw_mii_pdi_regs->mii_cfg2; + case 3: + return <q_ethsw_mii_pdi_regs->mii_cfg3; + case 4: + return <q_ethsw_mii_pdi_regs->mii_cfg4; + case 5: + return <q_ethsw_mii_pdi_regs->mii_cfg5; + } + + return NULL; +} + +static void ltq_eth_gmac_update(struct phy_device *phydev, int num) +{ + struct ltq_mdio_phy_addr_reg phy_addr_reg; + struct ltq_mii_mii_cfg_reg mii_cfg_reg; + void *phy_addr = ltq_eth_phy_addr_reg(num); + void *mii_cfg = ltq_eth_mii_cfg_reg(num); + + phy_addr_reg.val = ltq_r32(phy_addr); + mii_cfg_reg.val = ltq_r32(mii_cfg); + + phy_addr_reg.bits.addr = phydev->addr; + + if (phydev->link) + phy_addr_reg.bits.lnkst = LTQ_MDIO_PHY_ADDR_LNKST_UP; + else + phy_addr_reg.bits.lnkst = LTQ_MDIO_PHY_ADDR_LNKST_DOWN; + + switch (phydev->speed) { + case SPEED_1000: + phy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_G1; + mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M125; + break; + case SPEED_100: + phy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_M100; + switch (mii_cfg_reg.bits.miimode) { + case LTQ_MII_MII_CFG_MIIMODE_RMIIM: + case LTQ_MII_MII_CFG_MIIMODE_RMIIP: + mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M50; + break; + default: + mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M25; + break; + } + break; + default: + phy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_M10; + mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M2P5; + break; + } + + if (phydev->duplex == DUPLEX_FULL) + phy_addr_reg.bits.fdup = LTQ_MDIO_PHY_ADDR_FDUP_ENABLE; + else + phy_addr_reg.bits.fdup = LTQ_MDIO_PHY_ADDR_FDUP_DISABLE; + + dbg_ltq_writel(phy_addr, phy_addr_reg.val); + dbg_ltq_writel(mii_cfg, mii_cfg_reg.val); + udelay(1); +} + + +static void ltq_eth_port_config(struct ltq_vrx200_priv *priv, + const struct ltq_eth_port_config *port) +{ + struct ltq_mii_mii_cfg_reg mii_cfg_reg; + void *mii_cfg = ltq_eth_mii_cfg_reg(port->num); + int setup_gpio = 0; + + mii_cfg_reg.val = ltq_r32(mii_cfg); + + + switch (port->num) { + case 0: /* xMII0 */ + case 1: /* xMII1 */ + switch (port->phy_if) { + case PHY_INTERFACE_MODE_MII: + if (port->flags & LTQ_ETH_PORT_PHY) + /* MII MAC mode, connected to external PHY */ + mii_cfg_reg.bits.miimode = + LTQ_MII_MII_CFG_MIIMODE_MIIM; + else + /* MII PHY mode, connected to external MAC */ + mii_cfg_reg.bits.miimode = + LTQ_MII_MII_CFG_MIIMODE_MIIP; + setup_gpio = 1; + break; + case PHY_INTERFACE_MODE_RMII: + if (port->flags & LTQ_ETH_PORT_PHY) + /* RMII MAC mode, connected to external PHY */ + mii_cfg_reg.bits.miimode = + LTQ_MII_MII_CFG_MIIMODE_RMIIM; + else + /* RMII PHY mode, connected to external MAC */ + mii_cfg_reg.bits.miimode = + LTQ_MII_MII_CFG_MIIMODE_RMIIP; + setup_gpio = 1; + break; + case PHY_INTERFACE_MODE_RGMII: + /* RGMII MAC mode, connected to external PHY */ + mii_cfg_reg.bits.miimode = + LTQ_MII_MII_CFG_MIIMODE_RGMII; + setup_gpio = 1; + break; + default: + break; + } + break; + case 2: /* internal GPHY0 */ + case 3: /* internal GPHY0 */ + case 4: /* internal GPHY1 */ + switch (port->phy_if) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: + /* MII MAC mode, connected to internal GPHY */ + mii_cfg_reg.bits.miimode = + LTQ_MII_MII_CFG_MIIMODE_MIIM; + setup_gpio = 1; + break; + default: + break; + } + break; + case 5: /* internal GPHY1 or xMII2 */ + switch (port->phy_if) { + case PHY_INTERFACE_MODE_MII: + /* MII MAC mode, connected to internal GPHY */ + mii_cfg_reg.bits.miimode = + LTQ_MII_MII_CFG_MIIMODE_MIIM; + setup_gpio = 1; + break; + case PHY_INTERFACE_MODE_RGMII: + /* RGMII MAC mode, connected to external PHY */ + mii_cfg_reg.bits.miimode = + LTQ_MII_MII_CFG_MIIMODE_RGMII; + setup_gpio = 1; + break; + default: + break; + } + break; + default: + break; + } + + /* Enable MII interface */ + mii_cfg_reg.bits.en = port->flags ? 1 : 0; + dbg_ltq_writel(mii_cfg, mii_cfg_reg.val); + +} + +static void ltq_eth_gmac_init(int num) +{ + struct ltq_mdio_phy_addr_reg phy_addr_reg; + struct ltq_mii_mii_cfg_reg mii_cfg_reg; + void *phy_addr = ltq_eth_phy_addr_reg(num); + void *mii_cfg = ltq_eth_mii_cfg_reg(num); + struct ltq_ethsw_mac_pdi_x_regs *mac_pdi_regs; + + mac_pdi_regs = <q_ethsw_mac_pdi_regs->mac[num]; + + /* Reset PHY status to link down */ + phy_addr_reg.val = ltq_r32(phy_addr); + phy_addr_reg.bits.addr = num; + phy_addr_reg.bits.lnkst = LTQ_MDIO_PHY_ADDR_LNKST_DOWN; + phy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_M10; + phy_addr_reg.bits.fdup = LTQ_MDIO_PHY_ADDR_FDUP_DISABLE; + dbg_ltq_writel(phy_addr, phy_addr_reg.val); + + /* Reset and disable MII interface */ + mii_cfg_reg.val = ltq_r32(mii_cfg); + mii_cfg_reg.bits.en = 0; + mii_cfg_reg.bits.res = 1; + mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M2P5; + dbg_ltq_writel(mii_cfg, mii_cfg_reg.val); + + /* + * Enable padding of short frames, enable frame checksum generation + * in transmit direction + */ + dbg_ltq_writel(&mac_pdi_regs->ctrl_0, LTQ_ETHSW_MAC_CTRL0_PADEN | + LTQ_ETHSW_MAC_CTRL0_FCS); + + /* Set inter packet gap size to 12 bytes */ + dbg_ltq_writel(&mac_pdi_regs->ctrl_1, 12); + + /* + * Configure frame length checks: + * - allow jumbo frames + * - enable long length check + * - enable short length without VLAN tags + */ + dbg_ltq_writel(&mac_pdi_regs->ctrl_2, LTQ_ETHSW_MAC_CTRL2_MLEN | + LTQ_ETHSW_MAC_CTRL2_LCHKL | + LTQ_ETHSW_MAC_CTRL2_LCHKS_UNTAG); +} + + +static void ltq_eth_pmac_init(void) +{ + struct ltq_ethsw_mac_pdi_x_regs *mac_pdi_regs; + + mac_pdi_regs = <q_ethsw_mac_pdi_regs->mac[LTQ_ETHSW_PMAC]; + + /* + * Enable padding of short frames, enable frame checksum generation + * in transmit direction + */ + dbg_ltq_writel(&mac_pdi_regs->ctrl_0, LTQ_ETHSW_MAC_CTRL0_PADEN | + LTQ_ETHSW_MAC_CTRL0_FCS); + + /* + * Configure frame length checks: + * - allow jumbo frames + * - enable long length check + * - enable short length without VLAN tags + */ + dbg_ltq_writel(&mac_pdi_regs->ctrl_2, LTQ_ETHSW_MAC_CTRL2_MLEN | + LTQ_ETHSW_MAC_CTRL2_LCHKL | + LTQ_ETHSW_MAC_CTRL2_LCHKS_UNTAG); + + /* + * Apply workaround for buffer congestion: + * - shorten preambel to 1 byte + * - set minimum inter packet gap size to 7 bytes + * - enable receive buffer bypass mode + */ + dbg_ltq_writel(&mac_pdi_regs->ctrl_1, LTQ_ETHSW_MAC_CTRL1_SHORTPRE | 7); + dbg_ltq_writel(&mac_pdi_regs->ctrl_6, + (6 << LTQ_ETHSW_MAC_CTRL6_RBUF_DLY_WP_SHIFT) | + LTQ_ETHSW_MAC_CTRL6_RXBUF_BYPASS); + + /* Set request assertion threshold to 8, IPG counter to 11 */ + dbg_ltq_writel(<q_ethsw_pmac_pdi_regs->rx_ipg, 0x8B); + + /* + * Configure frame header control: + * - enable reaction on pause frames (flow control) + * - remove CRC for packets from PMAC to DMA + * - add CRC for packets from DMA to PMAC + */ + dbg_ltq_writel(<q_ethsw_pmac_pdi_regs->hd_ctl, LTQ_ETHSW_PMAC_HD_CTL_FC | + /*LTQ_ETHSW_PMAC_HD_CTL_RC | */LTQ_ETHSW_PMAC_HD_CTL_AC); +} + +static int +ltq_vrx200_hw_init(struct net_device *dev) +{ + struct ltq_vrx200_priv *priv = netdev_priv(dev); + int err = 0; + int i; + + netdev_info(dev, "setting up dma\n"); + ltq_dma_init_port(DMA_PORT_ETOP); + + netdev_info(dev, "setting up pmu\n"); + clk_enable(priv->clk_ppe); + + /* Reset ethernet and switch subsystems */ + netdev_info(dev, "reset core\n"); + ltq_reset_once(BIT(8), 10); + + /* Enable switch macro */ + ltq_setbits(<q_ethsw_mdio_pdi_regs->glob_ctrl, + LTQ_ETHSW_GLOB_CTRL_SE); + + /* Disable MDIO auto-polling for all ports */ + dbg_ltq_writel(<q_ethsw_mdio_pdi_regs->mdc_cfg_0, 0); + + /* + * Enable and set MDIO management clock to 2.5 MHz. This is the + * maximum clock for FE PHYs. + * Formula for clock is: + * + * 50 MHz + * x = ----------- - 1 + * 2 * f_MDC + */ + dbg_ltq_writel(<q_ethsw_mdio_pdi_regs->mdc_cfg_1, + LTQ_ETHSW_MDC_CFG1_MCEN | 9); + + /* Init MAC connected to CPU */ + ltq_eth_pmac_init(); + + /* Init MACs connected to external MII interfaces */ + for (i = 0; i < LTQ_ETHSW_MAX_GMAC; i++) + ltq_eth_gmac_init(i); + + for (i = 0; i < MAX_DMA_CHAN && !err; i++) { + int irq = LTQ_DMA_ETOP + i; + struct ltq_vrx200_chan *ch = &priv->ch[i]; + + ch->idx = ch->dma.nr = i; + + if (IS_TX(i)) { + ltq_dma_alloc_tx(&ch->dma); + err = request_irq(irq, ltq_vrx200_dma_irq, IRQF_DISABLED, + "vrx200_tx", priv); + } else if (IS_RX(i)) { + ltq_dma_alloc_rx(&ch->dma); + for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; + ch->dma.desc++) + if (ltq_vrx200_alloc_skb(ch)) + err = -ENOMEM; + ch->dma.desc = 0; + err = request_irq(irq, ltq_vrx200_dma_irq, IRQF_DISABLED, + "vrx200_rx", priv); + } + if (!err) + ch->dma.irq = irq; + } + for (i = 0; i < board_config.num_ports; i++) + ltq_eth_port_config(priv, &board_config.ports[i]); + return err; +} + +static void +ltq_vrx200_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) +{ + strcpy(info->driver, "Lantiq ETOP"); + strcpy(info->bus_info, "internal"); + strcpy(info->version, DRV_VERSION); +} + +static int +ltq_vrx200_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) +{ + struct ltq_vrx200_priv *priv = netdev_priv(dev); + + return phy_ethtool_gset(priv->phydev, cmd); +} + +static int +ltq_vrx200_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) +{ + struct ltq_vrx200_priv *priv = netdev_priv(dev); + + return phy_ethtool_sset(priv->phydev, cmd); +} + +static int +ltq_vrx200_nway_reset(struct net_device *dev) +{ + struct ltq_vrx200_priv *priv = netdev_priv(dev); + + return phy_start_aneg(priv->phydev); +} + +static const struct ethtool_ops ltq_vrx200_ethtool_ops = { + .get_drvinfo = ltq_vrx200_get_drvinfo, + .get_settings = ltq_vrx200_get_settings, + .set_settings = ltq_vrx200_set_settings, + .nway_reset = ltq_vrx200_nway_reset, +}; + +static inline int ltq_mdio_poll(struct mii_bus *bus) +{ + struct ltq_mdio_access acc; + unsigned cnt = 10000; + + while (likely(cnt--)) { + acc.val = ltq_r32(<q_ethsw_mdio_pdi_regs->mdio_ctrl); + if (!acc.bits.mbusy) + return 0; + } + + return 1; +} + +static int +ltq_vrx200_mdio_wr(struct mii_bus *bus, int addr, int regnum, u16 val) +{ + struct ltq_mdio_access acc; + int ret; + + acc.val = 0; + acc.bits.mbusy = LTQ_MDIO_MBUSY_BUSY; + acc.bits.op = LTQ_MDIO_OP_WRITE; + acc.bits.phyad = addr; + acc.bits.regad = regnum; + + ret = ltq_mdio_poll(bus); + if (ret) + return ret; + + dbg_ltq_writel(<q_ethsw_mdio_pdi_regs->mdio_write, val); + dbg_ltq_writel(<q_ethsw_mdio_pdi_regs->mdio_ctrl, acc.val); + + return 0; +} + +static int +ltq_vrx200_mdio_rd(struct mii_bus *bus, int addr, int regnum) +{ + struct ltq_mdio_access acc; + int ret; + + acc.val = 0; + acc.bits.mbusy = LTQ_MDIO_MBUSY_BUSY; + acc.bits.op = LTQ_MDIO_OP_READ; + acc.bits.phyad = addr; + acc.bits.regad = regnum; + + ret = ltq_mdio_poll(bus); + if (ret) + goto timeout; + + dbg_ltq_writel(<q_ethsw_mdio_pdi_regs->mdio_ctrl, acc.val); + + ret = ltq_mdio_poll(bus); + if (ret) + goto timeout; + + ret = ltq_r32(<q_ethsw_mdio_pdi_regs->mdio_read); + + return ret; +timeout: + return -1; +} + +static void +ltq_vrx200_mdio_link(struct net_device *dev) +{ + struct ltq_vrx200_priv *priv = netdev_priv(dev); + ltq_eth_gmac_update(priv->phydev, 0); +} + +static int +ltq_vrx200_mdio_probe(struct net_device *dev) +{ + struct ltq_vrx200_priv *priv = netdev_priv(dev); + struct phy_device *phydev = NULL; + int val; + + phydev = priv->mii_bus->phy_map[0]; + + if (!phydev) { + netdev_err(dev, "no PHY found\n"); + return -ENODEV; + } + + phydev = phy_connect(dev, dev_name(&phydev->dev), <q_vrx200_mdio_link, + 0, 0); + + if (IS_ERR(phydev)) { + netdev_err(dev, "Could not attach to PHY\n"); + return PTR_ERR(phydev); + } + + phydev->supported &= (SUPPORTED_10baseT_Half + | SUPPORTED_10baseT_Full + | SUPPORTED_100baseT_Half + | SUPPORTED_100baseT_Full + | SUPPORTED_1000baseT_Half + | SUPPORTED_1000baseT_Full + | SUPPORTED_Autoneg + | SUPPORTED_MII + | SUPPORTED_TP); + phydev->advertising = phydev->supported; + priv->phydev = phydev; + + pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n", + dev->name, phydev->drv->name, + dev_name(&phydev->dev), phydev->irq); + + val = ltq_vrx200_mdio_rd(priv->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000); + val |= ADVERTIZE_MPD; + ltq_vrx200_mdio_wr(priv->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000, val); + ltq_vrx200_mdio_wr(priv->mii_bus, 0, 0, 0x1040); + + phy_start_aneg(phydev); + + return 0; +} + +static int +ltq_vrx200_mdio_init(struct net_device *dev) +{ + struct ltq_vrx200_priv *priv = netdev_priv(dev); + int i; + int err; + + priv->mii_bus = mdiobus_alloc(); + if (!priv->mii_bus) { + netdev_err(dev, "failed to allocate mii bus\n"); + err = -ENOMEM; + goto err_out; + } + + priv->mii_bus->priv = dev; + priv->mii_bus->read = ltq_vrx200_mdio_rd; + priv->mii_bus->write = ltq_vrx200_mdio_wr; + priv->mii_bus->name = "ltq_mii"; + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0); + priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); + if (!priv->mii_bus->irq) { + err = -ENOMEM; + goto err_out_free_mdiobus; + } + + for (i = 0; i < PHY_MAX_ADDR; ++i) + priv->mii_bus->irq[i] = PHY_POLL; + + if (mdiobus_register(priv->mii_bus)) { + err = -ENXIO; + goto err_out_free_mdio_irq; + } + + if (ltq_vrx200_mdio_probe(dev)) { + err = -ENXIO; + goto err_out_unregister_bus; + } + return 0; + +err_out_unregister_bus: + mdiobus_unregister(priv->mii_bus); +err_out_free_mdio_irq: + kfree(priv->mii_bus->irq); +err_out_free_mdiobus: + mdiobus_free(priv->mii_bus); +err_out: + return err; +} + +static void +ltq_vrx200_mdio_cleanup(struct net_device *dev) +{ + struct ltq_vrx200_priv *priv = netdev_priv(dev); + + phy_disconnect(priv->phydev); + mdiobus_unregister(priv->mii_bus); + kfree(priv->mii_bus->irq); + mdiobus_free(priv->mii_bus); +} + +void phy_dump(struct net_device *dev) +{ + struct ltq_vrx200_priv *priv = netdev_priv(dev); + int i; + for (i = 0; i < 0x1F; i++) { + unsigned int val = ltq_vrx200_mdio_rd(priv->mii_bus, 0, i); + printk("%d %4X\n", i, val); + } +} + +static int +ltq_vrx200_open(struct net_device *dev) +{ + struct ltq_vrx200_priv *priv = netdev_priv(dev); + int i; + unsigned long flags; + + for (i = 0; i < MAX_DMA_CHAN; i++) { + struct ltq_vrx200_chan *ch = &priv->ch[i]; + + if (!IS_TX(i) && (!IS_RX(i))) + continue; + napi_enable(&ch->napi); + spin_lock_irqsave(&priv->lock, flags); + ltq_dma_open(&ch->dma); + spin_unlock_irqrestore(&priv->lock, flags); + } + if (priv->phydev) { + phy_start(priv->phydev); + phy_dump(dev); + } + netif_tx_start_all_queues(dev); + return 0; +} + +static int +ltq_vrx200_stop(struct net_device *dev) +{ + struct ltq_vrx200_priv *priv = netdev_priv(dev); + int i; + unsigned long flags; + + netif_tx_stop_all_queues(dev); + if (priv->phydev) + phy_stop(priv->phydev); + for (i = 0; i < MAX_DMA_CHAN; i++) { + struct ltq_vrx200_chan *ch = &priv->ch[i]; + + if (!IS_RX(i) && !IS_TX(i)) + continue; + napi_disable(&ch->napi); + spin_lock_irqsave(&priv->lock, flags); + ltq_dma_close(&ch->dma); + spin_unlock_irqrestore(&priv->lock, flags); + } + return 0; +} + +static int +ltq_vrx200_tx(struct sk_buff *skb, struct net_device *dev) +{ + int queue = skb_get_queue_mapping(skb); + struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); + struct ltq_vrx200_priv *priv = netdev_priv(dev); + struct ltq_vrx200_chan *ch = &priv->ch[(queue << 1) | 1]; + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; + unsigned long flags; + u32 byte_offset; + int len; + + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; + + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { + netdev_err(dev, "tx ring full\n"); + netif_tx_stop_queue(txq); + return NETDEV_TX_BUSY; + } + + /* dma needs to start on a 16 byte aligned address */ + byte_offset = CPHYSADDR(skb->data) % 16; + ch->skb[ch->dma.desc] = skb; + + dev->trans_start = jiffies; + + spin_lock_irqsave(&priv->lock, flags); + desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len, + DMA_TO_DEVICE)) - byte_offset; + wmb(); + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | + LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); + ch->dma.desc++; + ch->dma.desc %= LTQ_DESC_NUM; + spin_unlock_irqrestore(&priv->lock, flags); + + if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) + netif_tx_stop_queue(txq); + + return NETDEV_TX_OK; +} + +static int +ltq_vrx200_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) +{ + struct ltq_vrx200_priv *priv = netdev_priv(dev); + + /* TODO: mii-toll reports "No MII transceiver present!." ?!*/ + return phy_mii_ioctl(priv->phydev, rq, cmd); +} + +static u16 +ltq_vrx200_select_queue(struct net_device *dev, struct sk_buff *skb) +{ + /* we are currently only using the first queue */ + return 0; +} + +static int +ltq_vrx200_init(struct net_device *dev) +{ + struct ltq_vrx200_priv *priv = netdev_priv(dev); + struct sockaddr mac; + int err; + + ether_setup(dev); + dev->watchdog_timeo = 10 * HZ; + + err = ltq_vrx200_hw_init(dev); + if (err) + goto err_hw; + + memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); + if (!is_valid_ether_addr(mac.sa_data)) { + pr_warn("vrx200: invalid MAC, using random\n"); + random_ether_addr(mac.sa_data); + } + eth_mac_addr(dev, &mac); + + if (!ltq_vrx200_mdio_init(dev)) + dev->ethtool_ops = <q_vrx200_ethtool_ops; + else + pr_warn("vrx200: mdio probe failed\n");; + return 0; + +err_hw: + ltq_vrx200_hw_exit(dev); + return err; +} + +static void +ltq_vrx200_tx_timeout(struct net_device *dev) +{ + int err; + + ltq_vrx200_hw_exit(dev); + err = ltq_vrx200_hw_init(dev); + if (err) + goto err_hw; + dev->trans_start = jiffies; + netif_wake_queue(dev); + return; + +err_hw: + ltq_vrx200_hw_exit(dev); + netdev_err(dev, "failed to restart vrx200 after TX timeout\n"); +} + +static const struct net_device_ops ltq_eth_netdev_ops = { + .ndo_open = ltq_vrx200_open, + .ndo_stop = ltq_vrx200_stop, + .ndo_start_xmit = ltq_vrx200_tx, + .ndo_change_mtu = eth_change_mtu, + .ndo_do_ioctl = ltq_vrx200_ioctl, + .ndo_set_mac_address = eth_mac_addr, + .ndo_validate_addr = eth_validate_addr, + .ndo_select_queue = ltq_vrx200_select_queue, + .ndo_init = ltq_vrx200_init, + .ndo_tx_timeout = ltq_vrx200_tx_timeout, +}; + +static int __devinit +ltq_vrx200_probe(struct platform_device *pdev) +{ + struct net_device *dev; + struct ltq_vrx200_priv *priv; + struct resource *res; + int err; + int i; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get vrx200 resource\n"); + err = -ENOENT; + goto err_out; + } + + res = devm_request_mem_region(&pdev->dev, res->start, + resource_size(res), dev_name(&pdev->dev)); + if (!res) { + dev_err(&pdev->dev, "failed to request vrx200 resource\n"); + err = -EBUSY; + goto err_out; + } + + ltq_vrx200_membase = devm_ioremap_nocache(&pdev->dev, + res->start, resource_size(res)); + if (!ltq_vrx200_membase) { + dev_err(&pdev->dev, "failed to remap vrx200 engine %d\n", + pdev->id); + err = -ENOMEM; + goto err_out; + } + + if (ltq_gpio_request(&pdev->dev, 42, 2, 1, "MDIO") || + ltq_gpio_request(&pdev->dev, 43, 2, 1, "MDC")) { + dev_err(&pdev->dev, "failed to request MDIO gpios\n"); + err = -EBUSY; + goto err_out; + } + + dev = alloc_etherdev_mq(sizeof(struct ltq_vrx200_priv), 4); + strcpy(dev->name, "eth%d"); + dev->netdev_ops = <q_eth_netdev_ops; + priv = netdev_priv(dev); + priv->res = res; + priv->pldata = dev_get_platdata(&pdev->dev); + priv->netdev = dev; + + priv->clk_ppe = clk_get(&pdev->dev, NULL); + if (IS_ERR(priv->clk_ppe)) + return PTR_ERR(priv->clk_ppe); + + spin_lock_init(&priv->lock); + + for (i = 0; i < MAX_DMA_CHAN; i++) { + if (IS_TX(i)) + netif_napi_add(dev, &priv->ch[i].napi, + ltq_vrx200_poll_tx, 8); + else if (IS_RX(i)) + netif_napi_add(dev, &priv->ch[i].napi, + ltq_vrx200_poll_rx, 32); + priv->ch[i].netdev = dev; + } + + err = register_netdev(dev); + if (err) + goto err_free; + + platform_set_drvdata(pdev, dev); + return 0; + +err_free: + kfree(dev); +err_out: + return err; +} + +static int __devexit +ltq_vrx200_remove(struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + + if (dev) { + netif_tx_stop_all_queues(dev); + ltq_vrx200_hw_exit(dev); + ltq_vrx200_mdio_cleanup(dev); + unregister_netdev(dev); + } + return 0; +} + +static struct platform_driver ltq_mii_driver = { + .probe = ltq_vrx200_probe, + .remove = __devexit_p(ltq_vrx200_remove), + .driver = { + .name = "ltq_vrx200", + .owner = THIS_MODULE, + }, +}; + +module_platform_driver(ltq_mii_driver); + +MODULE_AUTHOR("John Crispin "); +MODULE_DESCRIPTION("Lantiq SoC ETOP"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/lantiq/files/drivers/net/ethernet/svip_eth.c b/target/linux/lantiq/files/drivers/net/ethernet/svip_eth.c new file mode 100644 index 0000000000..1e25795a2a --- /dev/null +++ b/target/linux/lantiq/files/drivers/net/ethernet/svip_eth.c @@ -0,0 +1,636 @@ +/************************************************************************ + * + * Copyright (c) 2005 + * Infineon Technologies AG + * St. Martin Strasse 53; 81669 Muenchen; Germany + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + ************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if 1 /** TODO: MOVE TO APPROPRIATE PLACE */ + +#define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600 +#define REV_MII_MODE 2 + +#endif + +#define DRV_NAME "ifxmips_mii0" + +#include +#include + +#ifdef CONFIG_DEBUG_MINI_BOOT +#define IKOS_MINI_BOOT +#endif + +/* debugging */ +#undef INCAIP2_SW_DUMP + +#define INCAIP2_SW_EMSG(fmt,args...) printk("%s: " fmt, __FUNCTION__ , ##args) + +#define INCAIP2_SW_CHIP_NO 1 +#define INCAIP2_SW_CHIP_ID 0 +#define INCAIP2_SW_DEVICE_NO 1 + +#ifdef INCAIP2_SW_DEBUG_MSG +#define INCAIP2_SW_DMSG(fmt,args...) printk("%s: " fmt, __FUNCTION__ , ##args) +#else +#define INCAIP2_SW_DMSG(fmt,args...) +#endif + +/************************** Module Parameters *****************************/ +static char *mode = "bridge"; +module_param(mode, charp, 0000); +MODULE_PARM_DESC(mode, ""); + +#ifdef HAVE_TX_TIMEOUT +static int timeout = 10*HZ; +module_param(timeout, int, 0); +MODULE_PARM_DESC(timeout, "Transmission watchdog timeout in seconds>"); +#endif + +#ifdef IKOS_MINI_BOOT +#ifdef CONFIG_INCAIP2 +extern s32 incaip2_sw_to_mbx(struct sk_buff* skb); +#endif +extern s32 svip_sw_to_mbx(struct sk_buff* skb); +#endif + +struct svip_mii_priv { + struct net_device_stats stats; + struct dma_device_info *dma_device; + struct sk_buff *skb; +}; + +static struct net_device *svip_mii0_dev; +static unsigned char mac_addr[MAX_ADDR_LEN]; +static unsigned char my_ethaddr[MAX_ADDR_LEN]; + +/** + * Initialize MAC address. + * This function copies the ethernet address from kernel command line. + * + * \param line Pointer to parameter + * \return 0 OK + * \ingroup Internal + */ +static int __init svip_eth_ethaddr_setup(char *line) +{ + char *ep; + int i; + + memset(my_ethaddr, 0, MAX_ADDR_LEN); + /* there should really be routines to do this stuff */ + for (i = 0; i < 6; i++) + { + my_ethaddr[i] = line ? simple_strtoul(line, &ep, 16) : 0; + if (line) + line = (*ep) ? ep+1 : ep; + } + INCAIP2_SW_DMSG("mac address %2x-%2x-%2x-%2x-%2x-%2x \n" + ,my_ethaddr[0] + ,my_ethaddr[1] + ,my_ethaddr[2] + ,my_ethaddr[3] + ,my_ethaddr[4] + ,my_ethaddr[5]); + return 0; +} +__setup("ethaddr=", svip_eth_ethaddr_setup); + + +/** + * Open RX DMA channels. + * This function opens all DMA rx channels. + * + * \param dma_dev pointer to DMA device information + * \ingroup Internal + */ +static void svip_eth_open_rx_dma(struct dma_device_info *dma_dev) +{ + int i; + + for(i=0; inum_rx_chan; i++) + { + dma_dev->rx_chan[i]->open(dma_dev->rx_chan[i]); + } +} + + +/** + * Open TX DMA channels. + * This function opens all DMA tx channels. + * + * \param dev pointer to net device structure that comprises + * DMA device information pointed to by it's priv field. + * \ingroup Internal + */ +static void svip_eth_open_tx_dma(struct dma_device_info *dma_dev) +{ + int i; + + for (i=0; inum_tx_chan; i++) + { + dma_dev->tx_chan[i]->open(dma_dev->tx_chan[i]); + } +} + + +#ifdef CONFIG_NET_HW_FLOWCONTROL +/** + * Enable receiving DMA. + * This function enables the receiving DMA channel. + * + * \param dev pointer to net device structure that comprises + * DMA device information pointed to by it's priv field. + * \ingroup Internal + */ +void svip_eth_xon(struct net_device *dev) +{ + struct switch_priv *sw_dev = (struct switch_priv *)dev->priv; + struct dma_device_info* dma_dev = + (struct dma_device_info *)sw_dev->dma_device; + unsigned long flag; + + local_irq_save(flag); + + INCAIP2_SW_DMSG("wakeup\n"); + svip_eth_open_rx_dma(dma_dev); + + local_irq_restore(flag); +} +#endif /* CONFIG_NET_HW_FLOWCONTROL */ + + +/** + * Open network device. + * This functions opens the network device and starts the interface queue. + * + * \param dev Device structure for Ethernet device + * \return 0 OK, device opened + * \return -1 Error, registering DMA device + * \ingroup API + */ +int svip_mii_open(struct net_device *dev) +{ + struct svip_mii_priv *priv = netdev_priv(dev); + struct dma_device_info *dma_dev = priv->dma_device; + + svip_eth_open_rx_dma(dma_dev); + svip_eth_open_tx_dma(dma_dev); + + netif_start_queue(dev); + return 0; +} + + +/** + * Close network device. + * This functions closes the network device, which will also stop the interface + * queue. + * + * \param dev Device structure for Ethernet device + * \return 0 OK, device closed (cannot fail) + * \ingroup API + */ +int svip_mii_release(struct net_device *dev) +{ + struct svip_mii_priv *priv = netdev_priv(dev); + struct dma_device_info *dma_dev = priv->dma_device; + int i; + + for (i = 0; i < dma_dev->max_rx_chan_num; i++) + dma_dev->rx_chan[i]->close(dma_dev->rx_chan[i]); + netif_stop_queue(dev); + return 0; +} + + +/** + * Read data from DMA device. + * This function reads data from the DMA device. The function is called by + * the switch/DMA pseudo interrupt handler dma_intr_handler on occurence of + * a DMA receive interrupt. + * + * \param dev Pointer to network device structure + * \param dma_dev Pointer to dma device structure + * \return OK In case of successful data reception from dma + * -EIO Incorrect opt pointer provided by device + * \ingroup Internal + */ +int svip_mii_hw_receive(struct net_device *dev, struct dma_device_info *dma_dev) +{ + struct svip_mii_priv *priv = netdev_priv(dev); + unsigned char *buf = NULL; + struct sk_buff *skb = NULL; + int len = 0; + + len = dma_device_read(dma_dev, &buf, (void **)&skb); + + if (len >= ETHERNET_PACKET_DMA_BUFFER_SIZE) { + printk(KERN_INFO DRV_NAME ": packet too large %d\n", len); + goto mii_hw_receive_err_exit; + } + + if (skb == NULL) { + printk(KERN_INFO DRV_NAME ": cannot restore pointer\n"); + goto mii_hw_receive_err_exit; + } + + if (len > (skb->end - skb->tail)) { + printk(KERN_INFO DRV_NAME ": BUG, len:%d end:%p tail:%p\n", + len, skb->end, skb->tail); + goto mii_hw_receive_err_exit; + } + + skb_put(skb, len); + skb->dev = dev; + skb->protocol = eth_type_trans(skb, dev); + netif_rx(skb); + + priv->stats.rx_packets++; + priv->stats.rx_bytes += len; + return 0; + +mii_hw_receive_err_exit: + if (len == 0) { + if (skb) + dev_kfree_skb_any(skb); + priv->stats.rx_errors++; + priv->stats.rx_dropped++; + return -EIO; + } else { + return len; + } +} + + +/** + * Write data to Ethernet switch. + * This function writes the data comprised in skb structure via DMA to the + * Ethernet Switch. It is installed as the switch driver's hard_start_xmit + * method. + * + * \param skb Pointer to socket buffer structure that contains the data + * to be sent + * \param dev Pointer to network device structure which is used for + * data transmission + * \return 1 Transmission error + * \return 0 OK, successful data transmission + * \ingroup API + */ +static int svip_mii_hw_tx(char *buf, int len, struct net_device *dev) +{ + int ret = 0; + struct svip_mii_priv *priv = netdev_priv(dev); + struct dma_device_info *dma_dev = priv->dma_device; + ret = dma_device_write(dma_dev, buf, len, priv->skb); + return ret; +} + +static int svip_mii_tx(struct sk_buff *skb, struct net_device *dev) +{ + int len; + char *data; + struct svip_mii_priv *priv = netdev_priv(dev); + struct dma_device_info *dma_dev = priv->dma_device; + + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; + data = skb->data; + priv->skb = skb; + dev->trans_start = jiffies; + /* TODO: we got more than 1 dma channel, + so we should do something intelligent here to select one */ + dma_dev->current_tx_chan = 0; + + wmb(); + + if (svip_mii_hw_tx(data, len, dev) != len) { + dev_kfree_skb_any(skb); + priv->stats.tx_errors++; + priv->stats.tx_dropped++; + } else { + priv->stats.tx_packets++; + priv->stats.tx_bytes += len; + } + + return 0; +} + + +/** + * Transmission timeout callback. + * This functions is called when a trasmission timeout occurs. It will wake up + * the interface queue again. + * + * \param dev Device structure for Ethernet device + * \ingroup API + */ +void svip_mii_tx_timeout(struct net_device *dev) +{ + int i; + struct svip_mii_priv *priv = netdev_priv(dev); + + priv->stats.tx_errors++; + for (i = 0; i < priv->dma_device->max_tx_chan_num; i++) + priv->dma_device->tx_chan[i]->disable_irq(priv->dma_device->tx_chan[i]); + netif_wake_queue(dev); + return; +} + + +/** + * Get device statistics. + * This functions returns the device statistics, stored in the device structure. + * + * \param dev Device structure for Ethernet device + * \return stats Pointer to statistics structure + * \ingroup API + */ +static struct net_device_stats *svip_get_stats(struct net_device *dev) +{ + struct svip_mii_priv *priv = netdev_priv(dev); + return &priv->stats; +} + + +/** + * Pseudo Interrupt handler for DMA. + * This function processes DMA interrupts notified to the switch device driver. + * The function is installed at the DMA core as interrupt handler for the + * switch dma device. + * It handles the following DMA interrupts: + * passes received data to the upper layer in case of rx interrupt, + * In case of a dma receive interrupt the received data is passed to the upper layer. + * In case of a transmit buffer full interrupt the transmit queue is stopped. + * In case of a transmission complete interrupt the transmit queue is restarted. + * + * \param dma_dev pointer to dma device structure + * \param status type of interrupt being notified (RCV_INT: dma receive + * interrupt, TX_BUF_FULL_INT: transmit buffer full interrupt, + * TRANSMIT_CPT_INT: transmission complete interrupt) + * \return OK In case of successful data reception from dma + * \ingroup Internal + */ +int dma_intr_handler(struct dma_device_info *dma_dev, int status) +{ + int i; + + switch (status) { + case RCV_INT: + svip_mii_hw_receive(svip_mii0_dev, dma_dev); + break; + + case TX_BUF_FULL_INT: + printk(KERN_INFO DRV_NAME ": tx buffer full\n"); + netif_stop_queue(svip_mii0_dev); + for (i = 0; i < dma_dev->max_tx_chan_num; i++) { + if ((dma_dev->tx_chan[i])->control == LTQ_DMA_CH_ON) + dma_dev->tx_chan[i]->enable_irq(dma_dev->tx_chan[i]); + } + break; + + case TRANSMIT_CPT_INT: + +#if 0 + for (i = 0; i < dma_dev->max_tx_chan_num; i++) +#if 0 + dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i]); +#else + dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i], (char *)__FUNCTION__); +#endif + netif_wake_queue(svip_mii0_dev); +#endif + break; + } + + return 0; +} + + +/** + * Allocates buffer sufficient for Ethernet Frame. + * This function is installed as DMA callback function to be called on DMA + * receive interrupt. + * + * \param len Unused + * \param *byte_offset Pointer to byte offset + * \param **opt pointer to skb structure + * \return NULL In case of buffer allocation fails + * buffer Pointer to allocated memory + * \ingroup Internal + */ +unsigned char *svip_etop_dma_buffer_alloc(int len, int *byte_offset, void **opt) +{ + unsigned char *buffer = NULL; + struct sk_buff *skb = NULL; + + skb = dev_alloc_skb(ETHERNET_PACKET_DMA_BUFFER_SIZE); + if (skb == NULL) + return NULL; + + buffer = (unsigned char *)(skb->data); + skb_reserve(skb, 2); + *(int *)opt = (int)skb; + *byte_offset = 2; + + return buffer; +} + + +/** + * Free DMA buffer. + * This function frees a buffer, which can be either a data buffer or an + * skb structure. + * + * \param *dataptr Pointer to data buffer + * \param *opt Pointer to skb structure + * \return 0 OK + * \ingroup Internal + */ +void svip_etop_dma_buffer_free(unsigned char *dataptr, void *opt) +{ + struct sk_buff *skb = NULL; + + if (opt == NULL) { + kfree(dataptr); + } else { + skb = (struct sk_buff *)opt; + dev_kfree_skb_any(skb); + } +} + +static int svip_mii_dev_init(struct net_device *dev); + +static const struct net_device_ops svip_eth_netdev_ops = { + .ndo_init = svip_mii_dev_init, + .ndo_open = svip_mii_open, + .ndo_stop = svip_mii_release, + .ndo_start_xmit = svip_mii_tx, + .ndo_get_stats = svip_get_stats, + .ndo_tx_timeout = svip_mii_tx_timeout, +}; + +//#include + +/** + * Initialize switch driver. + * This functions initializes the switch driver structures and registers the + * Ethernet device. + * + * \param dev Device structure for Ethernet device + * \return 0 OK + * \return ENOMEM No memory for structures available + * \return -1 Error during DMA init or Ethernet address configuration. + * \ingroup API + */ +static int svip_mii_dev_init(struct net_device *dev) +{ + int i; + struct svip_mii_priv *priv = netdev_priv(dev); + + + ether_setup(dev); + printk(KERN_INFO DRV_NAME ": %s is up\n", dev->name); + dev->watchdog_timeo = 10 * HZ; + memset(priv, 0, sizeof(*priv)); + priv->dma_device = dma_device_reserve("SW"); + if (!priv->dma_device) { + BUG(); + return -ENODEV; + } + priv->dma_device->buffer_alloc = svip_etop_dma_buffer_alloc; + priv->dma_device->buffer_free = svip_etop_dma_buffer_free; + priv->dma_device->intr_handler = dma_intr_handler; + + for (i = 0; i < priv->dma_device->max_rx_chan_num; i++) + priv->dma_device->rx_chan[i]->packet_size = + ETHERNET_PACKET_DMA_BUFFER_SIZE; + + for (i = 0; i < priv->dma_device->max_tx_chan_num; i++) { + priv->dma_device->tx_chan[i]->tx_weight=DEFAULT_SW_CHANNEL_WEIGHT; + priv->dma_device->tx_chan[i]->packet_size = + ETHERNET_PACKET_DMA_BUFFER_SIZE; + } + + dma_device_register(priv->dma_device); + + printk(KERN_INFO DRV_NAME ": using mac="); + + for (i = 0; i < 6; i++) { + dev->dev_addr[i] = mac_addr[i]; + printk("%02X%c", dev->dev_addr[i], (i == 5) ? ('\n') : (':')); + } + + return 0; +} + +static void svip_mii_chip_init(int mode) +{ +} + +static int svip_mii_probe(struct platform_device *dev) +{ + int result = 0; + unsigned char *mac = (unsigned char *)dev->dev.platform_data; + svip_mii0_dev = alloc_etherdev(sizeof(struct svip_mii_priv)); + svip_mii0_dev->netdev_ops = &svip_eth_netdev_ops; + memcpy(mac_addr, mac, 6); + strcpy(svip_mii0_dev->name, "eth%d"); + svip_mii_chip_init(REV_MII_MODE); + result = register_netdev(svip_mii0_dev); + if (result) { + printk(KERN_INFO DRV_NAME + ": error %i registering device \"%s\"\n", + result, svip_mii0_dev->name); + goto out; + } + printk(KERN_INFO DRV_NAME ": driver loaded!\n"); + +out: + return result; +} + +static int svip_mii_remove(struct platform_device *dev) +{ + struct svip_mii_priv *priv = netdev_priv(svip_mii0_dev); + + printk(KERN_INFO DRV_NAME ": cleanup\n"); + + dma_device_unregister(priv->dma_device); + dma_device_release(priv->dma_device); + kfree(priv->dma_device); + unregister_netdev(svip_mii0_dev); + free_netdev(svip_mii0_dev); + return 0; +} + + +static struct platform_driver svip_mii_driver = { + .probe = svip_mii_probe, + .remove = svip_mii_remove, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + + +/** + * Initialize switch driver as module. + * This functions initializes the switch driver structures and registers the + * Ethernet device for module usage. + * + * \return 0 OK + * \return ENODEV An error occured during initialization + * \ingroup API + */ +int __init svip_mii_init(void) +{ + int ret = platform_driver_register(&svip_mii_driver); + if (ret) + printk(KERN_INFO DRV_NAME + ": Error registering platfom driver!\n"); + return ret; +} + + +/** + * Remove driver module. + * This functions removes the driver and unregisters all devices. + * + * \ingroup API + */ +static void __exit svip_mii_cleanup(void) +{ + platform_driver_unregister(&svip_mii_driver); +} + +module_init(svip_mii_init); +module_exit(svip_mii_cleanup); + +MODULE_LICENSE("GPL"); diff --git a/target/linux/lantiq/files/drivers/net/ethernet/svip_virtual_eth.c b/target/linux/lantiq/files/drivers/net/ethernet/svip_virtual_eth.c new file mode 100644 index 0000000000..6de0cfab8b --- /dev/null +++ b/target/linux/lantiq/files/drivers/net/ethernet/svip_virtual_eth.c @@ -0,0 +1,346 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + Am Campeon 1-12; 81726 Munich, Germany + + THE DELIVERY OF THIS SOFTWARE AS WELL AS THE HEREBY GRANTED NON-EXCLUSIVE, + WORLDWIDE LICENSE TO USE, COPY, MODIFY, DISTRIBUTE AND SUBLICENSE THIS + SOFTWARE IS FREE OF CHARGE. + + THE LICENSED SOFTWARE IS PROVIDED "AS IS" AND INFINEON EXPRESSLY DISCLAIMS + ALL REPRESENTATIONS AND WARRANTIES, WHETHER EXPRESS OR IMPLIED, INCLUDING + WITHOUT LIMITATION, WARRANTIES OR REPRESENTATIONS OF WORKMANSHIP, + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, DURABILITY, THAT THE + OPERATING OF THE LICENSED SOFTWARE WILL BE ERROR FREE OR FREE OF ANY THIRD + PARTY CLAIMS, INCLUDING WITHOUT LIMITATION CLAIMS OF THIRD PARTY INTELLECTUAL + PROPERTY INFRINGEMENT. + + EXCEPT FOR ANY LIABILITY DUE TO WILFUL ACTS OR GROSS NEGLIGENCE AND EXCEPT + FOR ANY PERSONAL INJURY INFINEON SHALL IN NO EVENT BE LIABLE FOR ANY CLAIM + OR DAMAGES OF ANY KIND, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + + **************************************************************************** +Module : svip_virtual_eth.c + +Description : This file contains network driver implementation for a +Virtual Ethernet interface. The Virtual Ethernet interface +is part of Infineon's VINETIC-SVIP Linux BSP. + *******************************************************************************/ +#include +#include +#include +#include +#include +#include + +#define SVIP_VETH_VER_STR "3.0" +#define SVIP_VETH_INFO_STR \ + "@(#)SVIP virtual ethernet interface, version " SVIP_VETH_VER_STR + +/****************************************************************************** + * Local define/macro definitions + ******************************************************************************/ +struct svip_ve_priv +{ + struct net_device_stats stats; +}; + +/****************************************************************************** + * Global function declarations + ******************************************************************************/ +int svip_ve_rx(struct sk_buff *skb); + +/****************************************************************************** + * Local variable declarations + ******************************************************************************/ +static struct net_device *svip_ve_dev; +static int watchdog_timeout = 10*HZ; +static int (*svip_ve_mps_xmit)(struct sk_buff *skb) = NULL; + + +/****************************************************************************** + * Global function declarations + ******************************************************************************/ + +/** + * Called by MPS driver to register a transmit routine called for each outgoing + * VoFW0 message. + * + * \param mps_xmit pointer to transmit routine + * + * \return none + * + * \ingroup Internal + */ +void register_mps_xmit_routine(int (*mps_xmit)(struct sk_buff *skb)) +{ + svip_ve_mps_xmit = mps_xmit; +} +EXPORT_SYMBOL(register_mps_xmit_routine); + +/** + * Returns a pointer to the routine used to deliver an incoming packet/message + * from the MPS mailbox to the networking layer. This routine is called by MPS + * driver during initialisation time. + * + * \param skb pointer to incoming socket buffer + * + * \return svip_ve_rx pointer to incoming messages delivering routine + * + * \ingroup Internal + */ +int (*register_mps_recv_routine(void)) (struct sk_buff *skb) +{ + return svip_ve_rx; +} + +/** + * Used to deliver outgoing packets to VoFW0 module through the MPS driver. + * Upon loading/initialisation the MPS driver is registering a transmitting + * routine, which is called here to deliver the packet to the VoFW0 module. + * + * \param skb pointer to skb containing outgoing data + * \param dev pointer to this networking device's data + * + * \return 0 on success + * \return non-zero on error + * + * \ingroup Internal + */ +static int svip_ve_xmit(struct sk_buff *skb, struct net_device *dev) +{ + int err; + struct svip_ve_priv *priv = netdev_priv(dev); + struct net_device_stats *stats = &priv->stats; + + stats->tx_packets++; + stats->tx_bytes += skb->len; + + if (svip_ve_mps_xmit) + { + err = svip_ve_mps_xmit(skb); + if (err) + stats->tx_errors++; + dev->trans_start = jiffies; + return err; + } + else + printk(KERN_ERR "%s: MPS driver not registered, outgoing packet not delivered\n", dev->name); + + dev_kfree_skb(skb); + + return -1; +} + +/** + * Called by MPS driver upon receipt of a new message from VoFW0 module in + * the data inbox. The packet is pushed up the IP module for further processing. + * + * \param skb pointer to skb containing the incoming message + * + * \return 0 on success + * \return non-zero on error + * + * \ingroup Internal + */ +int svip_ve_rx(struct sk_buff *skb) +{ + int err; + struct svip_ve_priv *priv = netdev_priv(svip_ve_dev); + struct net_device_stats *stats = &priv->stats; + + skb->dev = svip_ve_dev; + skb->protocol = eth_type_trans(skb, svip_ve_dev); + + stats->rx_packets++; + stats->rx_bytes += skb->len; + + err = netif_rx(skb); + switch (err) + { + case NET_RX_SUCCESS: + return 0; + break; + case NET_RX_DROP: + default: + stats->rx_dropped++; + break; + } + + return 1; +} +EXPORT_SYMBOL(svip_ve_rx); + +/** + * Returns a pointer to the device's networking statistics data + * + * \param dev pointer to this networking device's data + * + * \return stats pointer to this network device's statistics data + * + * \ingroup Internal + */ +static struct net_device_stats *svip_ve_get_stats(struct net_device *dev) +{ + struct svip_ve_priv *priv = netdev_priv(dev); + + return &priv->stats; +} + +static void svip_ve_tx_timeout(struct net_device *dev) +{ + struct svip_ve_priv *priv = netdev_priv(dev); + + priv->stats.tx_errors++; + netif_wake_queue(dev); +} + +/** + * Device open routine. Called e.g. upon setting of an IP address using, + * 'ifconfig veth0 YYY.YYY.YYY.YYY netmask ZZZ.ZZZ.ZZZ.ZZZ' or + * 'ifconfig veth0 up' + * + * \param dev pointer to this network device's data + * + * \return 0 on success + * \return non-zero on error + * + * \ingroup Internal + */ +int svip_ve_open(struct net_device *dev) +{ + netif_start_queue(dev); + return 0; +} + +/** + * Device close routine. Called e.g. upon calling + * 'ifconfig veth0 down' + * + * \param dev pointer to this network device's data + * + * \return 0 on success + * \return non-zero on error + * + * \ingroup Internal + */ + +int svip_ve_release(struct net_device *dev) +{ + netif_stop_queue(dev); + return 0; +} + +static int svip_ve_dev_init(struct net_device *dev); + +static const struct net_device_ops svip_virtual_eth_netdev_ops = { + .ndo_init = svip_ve_dev_init, + .ndo_open = svip_ve_open, + .ndo_stop = svip_ve_release, + .ndo_start_xmit = svip_ve_xmit, + .ndo_get_stats = svip_ve_get_stats, + .ndo_tx_timeout = svip_ve_tx_timeout, +}; + + +/** + * Device initialisation routine which registers device interface routines. + * It is called upon execution of 'register_netdev' routine. + * + * \param dev pointer to this network device's data + * + * \return 0 on success + * \return non-zero on error + * + * \ingroup Internal + */ +static int svip_ve_dev_init(struct net_device *dev) +{ + ether_setup(dev); /* assign some of the fields */ + + dev->watchdog_timeo = watchdog_timeout; + memset(netdev_priv(dev), 0, sizeof(struct svip_ve_priv)); + dev->flags |= IFF_NOARP|IFF_PROMISC; + dev->flags &= ~IFF_MULTICAST; + + /* dedicated MAC address to veth0, 00:03:19:00:15:80 */ + dev->dev_addr[0] = 0x00; + dev->dev_addr[1] = 0x03; + dev->dev_addr[2] = 0x19; + dev->dev_addr[3] = 0x00; + dev->dev_addr[4] = 0x15; + dev->dev_addr[5] = 0x80; + + return 0; +} + +static int svip_ve_probe(struct platform_device *dev) +{ + int result = 0; + + svip_ve_dev = alloc_etherdev(sizeof(struct svip_ve_priv)); + svip_ve_dev->netdev_ops = &svip_virtual_eth_netdev_ops; + + strcpy(svip_ve_dev->name, "veth%d"); + + result = register_netdev(svip_ve_dev); + if (result) + { + printk(KERN_INFO "error %i registering device \"%s\"\n", result, svip_ve_dev->name); + goto out; + } + + printk (KERN_INFO "%s, (c) 2009, Lantiq Deutschland GmbH\n", &SVIP_VETH_INFO_STR[4]); + +out: + return result; +} + +static int svip_ve_remove(struct platform_device *dev) +{ + unregister_netdev(svip_ve_dev); + free_netdev(svip_ve_dev); + + printk(KERN_INFO "%s removed\n", svip_ve_dev->name); + return 0; +} + +static struct platform_driver svip_ve_driver = { + .probe = svip_ve_probe, + .remove = svip_ve_remove, + .driver = { + .name = "ifxmips_svip_ve", + .owner = THIS_MODULE, + }, +}; + +/** + * Module/driver entry routine + */ +static int __init svip_ve_init_module(void) +{ + int ret; + + ret = platform_driver_register(&svip_ve_driver); + if (ret) + printk(KERN_INFO "SVIP: error(%d) registering virtual Ethernet driver!\n", ret); + return ret; +} + +/** + * Module exit routine (never called for statically linked driver) + */ +static void __exit svip_ve_cleanup_module(void) +{ + platform_driver_unregister(&svip_ve_driver); +} + +module_init(svip_ve_init_module); +module_exit(svip_ve_cleanup_module); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("virtual ethernet driver for LANTIQ SVIP system"); + +EXPORT_SYMBOL(register_mps_recv_routine); diff --git a/target/linux/lantiq/files/drivers/spi/spi-falcon.c b/target/linux/lantiq/files/drivers/spi/spi-falcon.c new file mode 100644 index 0000000000..447bbaaa34 --- /dev/null +++ b/target/linux/lantiq/files/drivers/spi/spi-falcon.c @@ -0,0 +1,483 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Copyright (C) 2010 Thomas Langer + */ + +#include +#include +#include +#include +#include +#include + +#include + +#define DRV_NAME "falcon_spi" + +#define FALCON_SPI_XFER_BEGIN (1 << 0) +#define FALCON_SPI_XFER_END (1 << 1) + +/* Bus Read Configuration Register0 */ +#define LTQ_BUSRCON0 0x00000010 +/* Bus Write Configuration Register0 */ +#define LTQ_BUSWCON0 0x00000018 +/* Serial Flash Configuration Register */ +#define LTQ_SFCON 0x00000080 +/* Serial Flash Time Register */ +#define LTQ_SFTIME 0x00000084 +/* Serial Flash Status Register */ +#define LTQ_SFSTAT 0x00000088 +/* Serial Flash Command Register */ +#define LTQ_SFCMD 0x0000008C +/* Serial Flash Address Register */ +#define LTQ_SFADDR 0x00000090 +/* Serial Flash Data Register */ +#define LTQ_SFDATA 0x00000094 +/* Serial Flash I/O Control Register */ +#define LTQ_SFIO 0x00000098 +/* EBU Clock Control Register */ +#define LTQ_EBUCC 0x000000C4 + +/* Dummy Phase Length */ +#define SFCMD_DUMLEN_OFFSET 16 +#define SFCMD_DUMLEN_MASK 0x000F0000 +/* Chip Select */ +#define SFCMD_CS_OFFSET 24 +#define SFCMD_CS_MASK 0x07000000 +/* field offset */ +#define SFCMD_ALEN_OFFSET 20 +#define SFCMD_ALEN_MASK 0x00700000 +/* SCK Rise-edge Position */ +#define SFTIME_SCKR_POS_OFFSET 8 +#define SFTIME_SCKR_POS_MASK 0x00000F00 +/* SCK Period */ +#define SFTIME_SCK_PER_OFFSET 0 +#define SFTIME_SCK_PER_MASK 0x0000000F +/* SCK Fall-edge Position */ +#define SFTIME_SCKF_POS_OFFSET 12 +#define SFTIME_SCKF_POS_MASK 0x0000F000 +/* Device Size */ +#define SFCON_DEV_SIZE_A23_0 0x03000000 +#define SFCON_DEV_SIZE_MASK 0x0F000000 +/* Read Data Position */ +#define SFTIME_RD_POS_MASK 0x000F0000 +/* Data Output */ +#define SFIO_UNUSED_WD_MASK 0x0000000F +/* Command Opcode mask */ +#define SFCMD_OPC_MASK 0x000000FF +/* dlen bytes of data to write */ +#define SFCMD_DIR_WRITE 0x00000100 +/* Data Length offset */ +#define SFCMD_DLEN_OFFSET 9 +/* Command Error */ +#define SFSTAT_CMD_ERR 0x20000000 +/* Access Command Pending */ +#define SFSTAT_CMD_PEND 0x00400000 +/* Frequency set to 100MHz. */ +#define EBUCC_EBUDIV_SELF100 0x00000001 +/* Serial Flash */ +#define BUSRCON0_AGEN_SERIAL_FLASH 0xF0000000 +/* 8-bit multiplexed */ +#define BUSRCON0_PORTW_8_BIT_MUX 0x00000000 +/* Serial Flash */ +#define BUSWCON0_AGEN_SERIAL_FLASH 0xF0000000 +/* Chip Select after opcode */ +#define SFCMD_KEEP_CS_KEEP_SELECTED 0x00008000 + +struct falcon_spi { + u32 sfcmd; /* for caching of opcode, direction, ... */ + struct spi_master *master; +}; + +int +falcon_spi_xfer(struct spi_device *spi, + struct spi_transfer *t, + unsigned long flags) +{ + struct device *dev = &spi->dev; + struct falcon_spi *priv = spi_master_get_devdata(spi->master); + const u8 *txp = t->tx_buf; + u8 *rxp = t->rx_buf; + unsigned int bytelen = ((8 * t->len + 7) / 8); + unsigned int len, alen, dumlen; + u32 val; + enum { + state_init, + state_command_prepare, + state_write, + state_read, + state_disable_cs, + state_end + } state = state_init; + + do { + switch (state) { + case state_init: /* detect phase of upper layer sequence */ + { + /* initial write ? */ + if (flags & FALCON_SPI_XFER_BEGIN) { + if (!txp) { + dev_err(dev, + "BEGIN without tx data!\n"); + return -1; + } + /* + * Prepare the parts of the sfcmd register, + * which should not + * change during a sequence! + * Only exception are the length fields, + * especially alen and dumlen. + */ + + priv->sfcmd = ((spi->chip_select + << SFCMD_CS_OFFSET) + & SFCMD_CS_MASK); + priv->sfcmd |= SFCMD_KEEP_CS_KEEP_SELECTED; + priv->sfcmd |= *txp; + txp++; + bytelen--; + if (bytelen) { + /* + * more data: + * maybe address and/or dummy + */ + state = state_command_prepare; + break; + } else { + dev_dbg(dev, "write cmd %02X\n", + priv->sfcmd & SFCMD_OPC_MASK); + } + } + /* continued write ? */ + if (txp && bytelen) { + state = state_write; + break; + } + /* read data? */ + if (rxp && bytelen) { + state = state_read; + break; + } + /* end of sequence? */ + if (flags & FALCON_SPI_XFER_END) + state = state_disable_cs; + else + state = state_end; + break; + } + /* collect tx data for address and dummy phase */ + case state_command_prepare: + { + /* txp is valid, already checked */ + val = 0; + alen = 0; + dumlen = 0; + while (bytelen > 0) { + if (alen < 3) { + val = (val<<8)|(*txp++); + alen++; + } else if ((dumlen < 15) && (*txp == 0)) { + /* + * assume dummy bytes are set to 0 + * from upper layer + */ + dumlen++; + txp++; + } else + break; + bytelen--; + } + priv->sfcmd &= ~(SFCMD_ALEN_MASK | SFCMD_DUMLEN_MASK); + priv->sfcmd |= (alen << SFCMD_ALEN_OFFSET) | + (dumlen << SFCMD_DUMLEN_OFFSET); + if (alen > 0) + ltq_ebu_w32(val, LTQ_SFADDR); + + dev_dbg(dev, "write cmd %02X, alen=%d " + "(addr=%06X) dumlen=%d\n", + priv->sfcmd & SFCMD_OPC_MASK, + alen, val, dumlen); + + if (bytelen > 0) { + /* continue with write */ + state = state_write; + } else if (flags & FALCON_SPI_XFER_END) { + /* end of sequence? */ + state = state_disable_cs; + } else { + /* + * go to end and expect another + * call (read or write) + */ + state = state_end; + } + break; + } + case state_write: + { + /* txp still valid */ + priv->sfcmd |= SFCMD_DIR_WRITE; + len = 0; + val = 0; + do { + if (bytelen--) + val |= (*txp++) << (8 * len++); + if ((flags & FALCON_SPI_XFER_END) + && (bytelen == 0)) { + priv->sfcmd &= + ~SFCMD_KEEP_CS_KEEP_SELECTED; + } + if ((len == 4) || (bytelen == 0)) { + ltq_ebu_w32(val, LTQ_SFDATA); + ltq_ebu_w32(priv->sfcmd + | (len<sfcmd &= ~(SFCMD_ALEN_MASK + | SFCMD_DUMLEN_MASK); + } + } while (bytelen); + state = state_end; + break; + } + case state_read: + { + /* read data */ + priv->sfcmd &= ~SFCMD_DIR_WRITE; + do { + if ((flags & FALCON_SPI_XFER_END) + && (bytelen <= 4)) { + priv->sfcmd &= + ~SFCMD_KEEP_CS_KEEP_SELECTED; + } + len = (bytelen > 4) ? 4 : bytelen; + bytelen -= len; + ltq_ebu_w32(priv->sfcmd + |(len<sfcmd &= ~(SFCMD_ALEN_MASK + | SFCMD_DUMLEN_MASK); + do { + val = ltq_ebu_r32(LTQ_SFSTAT); + if (val & SFSTAT_CMD_ERR) { + /* reset error status */ + dev_err(dev, "SFSTAT: CMD_ERR " + "(%x)\n", val); + ltq_ebu_w32(SFSTAT_CMD_ERR, + LTQ_SFSTAT); + return -1; + } + } while (val & SFSTAT_CMD_PEND); + val = ltq_ebu_r32(LTQ_SFDATA); + do { + *rxp = (val & 0xFF); + rxp++; + val >>= 8; + len--; + } while (len); + } while (bytelen); + state = state_end; + break; + } + case state_disable_cs: + { + priv->sfcmd &= ~SFCMD_KEEP_CS_KEEP_SELECTED; + ltq_ebu_w32(priv->sfcmd | (0 << SFCMD_DLEN_OFFSET), + LTQ_SFCMD); + val = ltq_ebu_r32(LTQ_SFSTAT); + if (val & SFSTAT_CMD_ERR) { + /* reset error status */ + dev_err(dev, "SFSTAT: CMD_ERR (%x)\n", val); + ltq_ebu_w32(SFSTAT_CMD_ERR, LTQ_SFSTAT); + return -1; + } + state = state_end; + break; + } + case state_end: + break; + } + } while (state != state_end); + + return 0; +} + +static int +falcon_spi_setup(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + const u32 ebuclk = 100000000; + unsigned int i; + unsigned long flags; + + dev_dbg(dev, "setup\n"); + + if (spi->master->bus_num > 0 || spi->chip_select > 0) + return -ENODEV; + + spin_lock_irqsave(&ebu_lock, flags); + + if (ebuclk < spi->max_speed_hz) { + /* set EBU clock to 100 MHz */ + ltq_sys1_w32_mask(0, EBUCC_EBUDIV_SELF100, LTQ_EBUCC); + i = 1; /* divider */ + } else { + /* set EBU clock to 50 MHz */ + ltq_sys1_w32_mask(EBUCC_EBUDIV_SELF100, 0, LTQ_EBUCC); + + /* search for suitable divider */ + for (i = 1; i < 7; i++) { + if (ebuclk / i <= spi->max_speed_hz) + break; + } + } + + /* setup period of serial clock */ + ltq_ebu_w32_mask(SFTIME_SCKF_POS_MASK + | SFTIME_SCKR_POS_MASK + | SFTIME_SCK_PER_MASK, + (i << SFTIME_SCKR_POS_OFFSET) + | (i << (SFTIME_SCK_PER_OFFSET + 1)), + LTQ_SFTIME); + + /* + * set some bits of unused_wd, to not trigger HOLD/WP + * signals on non QUAD flashes + */ + ltq_ebu_w32((SFIO_UNUSED_WD_MASK & (0x8 | 0x4)), LTQ_SFIO); + + ltq_ebu_w32(BUSRCON0_AGEN_SERIAL_FLASH | BUSRCON0_PORTW_8_BIT_MUX, + LTQ_BUSRCON0); + ltq_ebu_w32(BUSWCON0_AGEN_SERIAL_FLASH, LTQ_BUSWCON0); + /* set address wrap around to maximum for 24-bit addresses */ + ltq_ebu_w32_mask(SFCON_DEV_SIZE_MASK, SFCON_DEV_SIZE_A23_0, LTQ_SFCON); + + spin_unlock_irqrestore(&ebu_lock, flags); + + return 0; +} + +static int +falcon_spi_transfer(struct spi_device *spi, struct spi_message *m) +{ + struct falcon_spi *priv = spi_master_get_devdata(spi->master); + struct spi_transfer *t; + unsigned long spi_flags; + unsigned long flags; + int ret = 0; + + priv->sfcmd = 0; + m->actual_length = 0; + + spi_flags = FALCON_SPI_XFER_BEGIN; + list_for_each_entry(t, &m->transfers, transfer_list) { + if (list_is_last(&t->transfer_list, &m->transfers)) + spi_flags |= FALCON_SPI_XFER_END; + + spin_lock_irqsave(&ebu_lock, flags); + ret = falcon_spi_xfer(spi, t, spi_flags); + spin_unlock_irqrestore(&ebu_lock, flags); + + if (ret) + break; + + m->actual_length += t->len; + + if (t->delay_usecs || t->cs_change) + BUG(); + + spi_flags = 0; + } + + m->status = ret; + m->complete(m->context); + + return 0; +} + +static void +falcon_spi_cleanup(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + + dev_dbg(dev, "cleanup\n"); +} + +static int __devinit +falcon_spi_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct falcon_spi *priv; + struct spi_master *master; + int ret; + + dev_dbg(dev, "probing\n"); + + master = spi_alloc_master(&pdev->dev, sizeof(*priv)); + if (!master) { + dev_err(dev, "no memory for spi_master\n"); + return -ENOMEM; + } + + priv = spi_master_get_devdata(master); + priv->master = master; + + master->mode_bits = SPI_MODE_3; + master->num_chipselect = 1; + master->bus_num = 0; + + master->setup = falcon_spi_setup; + master->transfer = falcon_spi_transfer; + master->cleanup = falcon_spi_cleanup; + + platform_set_drvdata(pdev, priv); + + ret = spi_register_master(master); + if (ret) + spi_master_put(master); + + return ret; +} + +static int __devexit +falcon_spi_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct falcon_spi *priv = platform_get_drvdata(pdev); + + dev_dbg(dev, "removed\n"); + + spi_unregister_master(priv->master); + + return 0; +} + +static struct platform_driver falcon_spi_driver = { + .probe = falcon_spi_probe, + .remove = __devexit_p(falcon_spi_remove), + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE + } +}; + +static int __init +falcon_spi_init(void) +{ + return platform_driver_register(&falcon_spi_driver); +} + +static void __exit +falcon_spi_exit(void) +{ + platform_driver_unregister(&falcon_spi_driver); +} + +module_init(falcon_spi_init); +module_exit(falcon_spi_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Lantiq Falcon SPI controller driver"); diff --git a/target/linux/lantiq/files/drivers/spi/spi-xway.c b/target/linux/lantiq/files/drivers/spi/spi-xway.c new file mode 100644 index 0000000000..be5c25b1fe --- /dev/null +++ b/target/linux/lantiq/files/drivers/spi/spi-xway.c @@ -0,0 +1,1070 @@ +/* + * Lantiq SoC SPI controller + * + * Copyright (C) 2011 Daniel Schwierzeck + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define LTQ_SPI_CLC 0x00 /* Clock control */ +#define LTQ_SPI_PISEL 0x04 /* Port input select */ +#define LTQ_SPI_ID 0x08 /* Identification */ +#define LTQ_SPI_CON 0x10 /* Control */ +#define LTQ_SPI_STAT 0x14 /* Status */ +#define LTQ_SPI_WHBSTATE 0x18 /* Write HW modified state */ +#define LTQ_SPI_TB 0x20 /* Transmit buffer */ +#define LTQ_SPI_RB 0x24 /* Receive buffer */ +#define LTQ_SPI_RXFCON 0x30 /* Receive FIFO control */ +#define LTQ_SPI_TXFCON 0x34 /* Transmit FIFO control */ +#define LTQ_SPI_FSTAT 0x38 /* FIFO status */ +#define LTQ_SPI_BRT 0x40 /* Baudrate timer */ +#define LTQ_SPI_BRSTAT 0x44 /* Baudrate timer status */ +#define LTQ_SPI_SFCON 0x60 /* Serial frame control */ +#define LTQ_SPI_SFSTAT 0x64 /* Serial frame status */ +#define LTQ_SPI_GPOCON 0x70 /* General purpose output control */ +#define LTQ_SPI_GPOSTAT 0x74 /* General purpose output status */ +#define LTQ_SPI_FGPO 0x78 /* Forced general purpose output */ +#define LTQ_SPI_RXREQ 0x80 /* Receive request */ +#define LTQ_SPI_RXCNT 0x84 /* Receive count */ +#define LTQ_SPI_DMACON 0xEC /* DMA control */ +#define LTQ_SPI_IRNEN 0xF4 /* Interrupt node enable */ +#define LTQ_SPI_IRNICR 0xF8 /* Interrupt node interrupt capture */ +#define LTQ_SPI_IRNCR 0xFC /* Interrupt node control */ + +#define LTQ_SPI_CLC_SMC_SHIFT 16 /* Clock divider for sleep mode */ +#define LTQ_SPI_CLC_SMC_MASK 0xFF +#define LTQ_SPI_CLC_RMC_SHIFT 8 /* Clock divider for normal run mode */ +#define LTQ_SPI_CLC_RMC_MASK 0xFF +#define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */ +#define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */ + +#define LTQ_SPI_ID_TXFS_SHIFT 24 /* Implemented TX FIFO size */ +#define LTQ_SPI_ID_TXFS_MASK 0x3F +#define LTQ_SPI_ID_RXFS_SHIFT 16 /* Implemented RX FIFO size */ +#define LTQ_SPI_ID_RXFS_MASK 0x3F +#define LTQ_SPI_ID_REV_MASK 0x1F /* Hardware revision number */ +#define LTQ_SPI_ID_CFG BIT(5) /* DMA interface support */ + +#define LTQ_SPI_CON_BM_SHIFT 16 /* Data width selection */ +#define LTQ_SPI_CON_BM_MASK 0x1F +#define LTQ_SPI_CON_EM BIT(24) /* Echo mode */ +#define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */ +#define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */ +#define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */ +#define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */ +#define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */ +#define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */ +#define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */ +#define LTQ_SPI_CON_LB BIT(7) /* Loopback control */ +#define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */ +#define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */ +#define LTQ_SPI_CON_HB BIT(4) /* Heading control */ +#define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */ +#define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */ + +#define LTQ_SPI_STAT_RXBV_MASK 0x7 +#define LTQ_SPI_STAT_RXBV_SHIFT 28 +#define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */ +#define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */ +#define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */ +#define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */ +#define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */ +#define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */ +#define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */ +#define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */ + +#define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */ +#define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */ +#define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */ +#define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */ +#define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */ +#define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */ +#define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */ +#define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */ +#define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */ +#define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */ +#define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */ +#define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */ +#define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */ +#define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */ +#define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */ +#define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */ +#define LTQ_SPI_WHBSTATE_CLR_ERRORS 0x0F50 + +#define LTQ_SPI_RXFCON_RXFITL_SHIFT 8 /* FIFO interrupt trigger level */ +#define LTQ_SPI_RXFCON_RXFITL_MASK 0x3F +#define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */ +#define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */ + +#define LTQ_SPI_TXFCON_TXFITL_SHIFT 8 /* FIFO interrupt trigger level */ +#define LTQ_SPI_TXFCON_TXFITL_MASK 0x3F +#define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */ +#define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */ + +#define LTQ_SPI_FSTAT_RXFFL_MASK 0x3f +#define LTQ_SPI_FSTAT_RXFFL_SHIFT 0 +#define LTQ_SPI_FSTAT_TXFFL_MASK 0x3f +#define LTQ_SPI_FSTAT_TXFFL_SHIFT 8 + +#define LTQ_SPI_GPOCON_ISCSBN_SHIFT 8 +#define LTQ_SPI_GPOCON_INVOUTN_SHIFT 0 + +#define LTQ_SPI_FGPO_SETOUTN_SHIFT 8 +#define LTQ_SPI_FGPO_CLROUTN_SHIFT 0 + +#define LTQ_SPI_RXREQ_RXCNT_MASK 0xFFFF /* Receive count value */ +#define LTQ_SPI_RXCNT_TODO_MASK 0xFFFF /* Recevie to-do value */ + +#define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */ +#define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */ +#define LTQ_SPI_IRNEN_T BIT(1) /* Transmit end interrupt request */ +#define LTQ_SPI_IRNEN_R BIT(0) /* Receive end interrupt request */ +#define LTQ_SPI_IRNEN_ALL 0xF + +/* Hard-wired GPIOs used by SPI controller */ +#define LTQ_SPI_GPIO_DI (ltq_is_ase()? 8 : 16) +#define LTQ_SPI_GPIO_DO (ltq_is_ase()? 9 : 17) +#define LTQ_SPI_GPIO_CLK (ltq_is_ase()? 10 : 18) + +struct ltq_spi { + struct spi_bitbang bitbang; + struct completion done; + spinlock_t lock; + + struct device *dev; + void __iomem *base; + struct clk *fpiclk; + struct clk *spiclk; + + int status; + int irq[3]; + + const u8 *tx; + u8 *rx; + u32 tx_cnt; + u32 rx_cnt; + u32 len; + struct spi_transfer *curr_transfer; + + u32 (*get_tx) (struct ltq_spi *); + + u16 txfs; + u16 rxfs; + unsigned dma_support:1; + unsigned cfg_mode:1; + +}; + +struct ltq_spi_controller_state { + void (*cs_activate) (struct spi_device *); + void (*cs_deactivate) (struct spi_device *); +}; + +struct ltq_spi_irq_map { + char *name; + irq_handler_t handler; +}; + +struct ltq_spi_cs_gpio_map { + unsigned gpio; + unsigned mux; +}; + +static inline struct ltq_spi *ltq_spi_to_hw(struct spi_device *spi) +{ + return spi_master_get_devdata(spi->master); +} + +static inline u32 ltq_spi_reg_read(struct ltq_spi *hw, u32 reg) +{ + return ioread32be(hw->base + reg); +} + +static inline void ltq_spi_reg_write(struct ltq_spi *hw, u32 val, u32 reg) +{ + iowrite32be(val, hw->base + reg); +} + +static inline void ltq_spi_reg_setbit(struct ltq_spi *hw, u32 bits, u32 reg) +{ + u32 val; + + val = ltq_spi_reg_read(hw, reg); + val |= bits; + ltq_spi_reg_write(hw, val, reg); +} + +static inline void ltq_spi_reg_clearbit(struct ltq_spi *hw, u32 bits, u32 reg) +{ + u32 val; + + val = ltq_spi_reg_read(hw, reg); + val &= ~bits; + ltq_spi_reg_write(hw, val, reg); +} + +static void ltq_spi_hw_enable(struct ltq_spi *hw) +{ + u32 clc; + + /* Power-up mdule */ + clk_enable(hw->spiclk); + + /* + * Set clock divider for run mode to 1 to + * run at same frequency as FPI bus + */ + clc = (1 << LTQ_SPI_CLC_RMC_SHIFT); + ltq_spi_reg_write(hw, clc, LTQ_SPI_CLC); +} + +static void ltq_spi_hw_disable(struct ltq_spi *hw) +{ + /* Set clock divider to 0 and set module disable bit */ + ltq_spi_reg_write(hw, LTQ_SPI_CLC_DISS, LTQ_SPI_CLC); + + /* Power-down mdule */ + clk_disable(hw->spiclk); +} + +static void ltq_spi_reset_fifos(struct ltq_spi *hw) +{ + u32 val; + + /* + * Enable and flush FIFOs. Set interrupt trigger level to + * half of FIFO count implemented in hardware. + */ + if (hw->txfs > 1) { + val = hw->txfs << (LTQ_SPI_TXFCON_TXFITL_SHIFT - 1); + val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU; + ltq_spi_reg_write(hw, val, LTQ_SPI_TXFCON); + } + + if (hw->rxfs > 1) { + val = hw->rxfs << (LTQ_SPI_RXFCON_RXFITL_SHIFT - 1); + val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU; + ltq_spi_reg_write(hw, val, LTQ_SPI_RXFCON); + } +} + +static inline int ltq_spi_wait_ready(struct ltq_spi *hw) +{ + u32 stat; + unsigned long timeout; + + timeout = jiffies + msecs_to_jiffies(200); + + do { + stat = ltq_spi_reg_read(hw, LTQ_SPI_STAT); + if (!(stat & LTQ_SPI_STAT_BSY)) + return 0; + + cond_resched(); + } while (!time_after_eq(jiffies, timeout)); + + dev_err(hw->dev, "SPI wait ready timed out stat: %x\n", stat); + + return -ETIMEDOUT; +} + +static void ltq_spi_config_mode_set(struct ltq_spi *hw) +{ + if (hw->cfg_mode) + return; + + /* + * Putting the SPI module in config mode is only safe if no + * transfer is in progress as indicated by busy flag STATE.BSY. + */ + if (ltq_spi_wait_ready(hw)) { + ltq_spi_reset_fifos(hw); + hw->status = -ETIMEDOUT; + } + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE); + + hw->cfg_mode = 1; +} + +static void ltq_spi_run_mode_set(struct ltq_spi *hw) +{ + if (!hw->cfg_mode) + return; + + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE); + + hw->cfg_mode = 0; +} + +static u32 ltq_spi_tx_word_u8(struct ltq_spi *hw) +{ + const u8 *tx = hw->tx; + u32 data = *tx++; + + hw->tx_cnt++; + hw->tx++; + + return data; +} + +static u32 ltq_spi_tx_word_u16(struct ltq_spi *hw) +{ + const u16 *tx = (u16 *) hw->tx; + u32 data = *tx++; + + hw->tx_cnt += 2; + hw->tx += 2; + + return data; +} + +static u32 ltq_spi_tx_word_u32(struct ltq_spi *hw) +{ + const u32 *tx = (u32 *) hw->tx; + u32 data = *tx++; + + hw->tx_cnt += 4; + hw->tx += 4; + + return data; +} + +static void ltq_spi_bits_per_word_set(struct spi_device *spi) +{ + struct ltq_spi *hw = ltq_spi_to_hw(spi); + u32 bm; + u8 bits_per_word = spi->bits_per_word; + + /* + * Use either default value of SPI device or value + * from current transfer. + */ + if (hw->curr_transfer && hw->curr_transfer->bits_per_word) + bits_per_word = hw->curr_transfer->bits_per_word; + + if (bits_per_word <= 8) + hw->get_tx = ltq_spi_tx_word_u8; + else if (bits_per_word <= 16) + hw->get_tx = ltq_spi_tx_word_u16; + else if (bits_per_word <= 32) + hw->get_tx = ltq_spi_tx_word_u32; + + /* CON.BM value = bits_per_word - 1 */ + bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_SHIFT; + + ltq_spi_reg_clearbit(hw, LTQ_SPI_CON_BM_MASK << + LTQ_SPI_CON_BM_SHIFT, LTQ_SPI_CON); + ltq_spi_reg_setbit(hw, bm, LTQ_SPI_CON); +} + +static void ltq_spi_speed_set(struct spi_device *spi) +{ + struct ltq_spi *hw = ltq_spi_to_hw(spi); + u32 br, max_speed_hz, spi_clk; + u32 speed_hz = spi->max_speed_hz; + + /* + * Use either default value of SPI device or value + * from current transfer. + */ + if (hw->curr_transfer && hw->curr_transfer->speed_hz) + speed_hz = hw->curr_transfer->speed_hz; + + /* + * SPI module clock is derived from FPI bus clock dependent on + * divider value in CLC.RMS which is always set to 1. + */ + spi_clk = clk_get_rate(hw->fpiclk); + + /* + * Maximum SPI clock frequency in master mode is half of + * SPI module clock frequency. Maximum reload value of + * baudrate generator BR is 2^16. + */ + max_speed_hz = spi_clk / 2; + if (speed_hz >= max_speed_hz) + br = 0; + else + br = (max_speed_hz / speed_hz) - 1; + + if (br > 0xFFFF) + br = 0xFFFF; + + ltq_spi_reg_write(hw, br, LTQ_SPI_BRT); +} + +static void ltq_spi_clockmode_set(struct spi_device *spi) +{ + struct ltq_spi *hw = ltq_spi_to_hw(spi); + u32 con; + + con = ltq_spi_reg_read(hw, LTQ_SPI_CON); + + /* + * SPI mode mapping in CON register: + * Mode CPOL CPHA CON.PO CON.PH + * 0 0 0 0 1 + * 1 0 1 0 0 + * 2 1 0 1 1 + * 3 1 1 1 0 + */ + if (spi->mode & SPI_CPHA) + con &= ~LTQ_SPI_CON_PH; + else + con |= LTQ_SPI_CON_PH; + + if (spi->mode & SPI_CPOL) + con |= LTQ_SPI_CON_PO; + else + con &= ~LTQ_SPI_CON_PO; + + /* Set heading control */ + if (spi->mode & SPI_LSB_FIRST) + con &= ~LTQ_SPI_CON_HB; + else + con |= LTQ_SPI_CON_HB; + + ltq_spi_reg_write(hw, con, LTQ_SPI_CON); +} + +static void ltq_spi_xmit_set(struct ltq_spi *hw, struct spi_transfer *t) +{ + u32 con; + + con = ltq_spi_reg_read(hw, LTQ_SPI_CON); + + if (t) { + if (t->tx_buf && t->rx_buf) { + con &= ~(LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF); + } else if (t->rx_buf) { + con &= ~LTQ_SPI_CON_RXOFF; + con |= LTQ_SPI_CON_TXOFF; + } else if (t->tx_buf) { + con &= ~LTQ_SPI_CON_TXOFF; + con |= LTQ_SPI_CON_RXOFF; + } + } else + con |= (LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF); + + ltq_spi_reg_write(hw, con, LTQ_SPI_CON); +} + +static void ltq_spi_gpio_cs_activate(struct spi_device *spi) +{ + struct ltq_spi_controller_data *cdata = spi->controller_data; + int val = spi->mode & SPI_CS_HIGH ? 1 : 0; + + gpio_set_value(cdata->gpio, val); +} + +static void ltq_spi_gpio_cs_deactivate(struct spi_device *spi) +{ + struct ltq_spi_controller_data *cdata = spi->controller_data; + int val = spi->mode & SPI_CS_HIGH ? 0 : 1; + + gpio_set_value(cdata->gpio, val); +} + +static void ltq_spi_internal_cs_activate(struct spi_device *spi) +{ + struct ltq_spi *hw = ltq_spi_to_hw(spi); + u32 fgpo; + + fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_CLROUTN_SHIFT)); + ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO); +} + +static void ltq_spi_internal_cs_deactivate(struct spi_device *spi) +{ + struct ltq_spi *hw = ltq_spi_to_hw(spi); + u32 fgpo; + + fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT)); + ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO); +} + +static void ltq_spi_chipselect(struct spi_device *spi, int cs) +{ + struct ltq_spi *hw = ltq_spi_to_hw(spi); + struct ltq_spi_controller_state *cstate = spi->controller_state; + + switch (cs) { + case BITBANG_CS_ACTIVE: + ltq_spi_bits_per_word_set(spi); + ltq_spi_speed_set(spi); + ltq_spi_clockmode_set(spi); + ltq_spi_run_mode_set(hw); + + cstate->cs_activate(spi); + break; + + case BITBANG_CS_INACTIVE: + cstate->cs_deactivate(spi); + + ltq_spi_config_mode_set(hw); + + break; + } +} + +static int ltq_spi_setup_transfer(struct spi_device *spi, + struct spi_transfer *t) +{ + struct ltq_spi *hw = ltq_spi_to_hw(spi); + u8 bits_per_word = spi->bits_per_word; + + hw->curr_transfer = t; + + if (t && t->bits_per_word) + bits_per_word = t->bits_per_word; + + if (bits_per_word > 32) + return -EINVAL; + + ltq_spi_config_mode_set(hw); + + return 0; +} + +static const struct ltq_spi_cs_gpio_map ltq_spi_cs[] = { + { 15, 2 }, + { 22, 2 }, + { 13, 1 }, + { 10, 1 }, + { 9, 1 }, + { 11, 3 }, +}; + +static const struct ltq_spi_cs_gpio_map ltq_spi_cs_ase[] = { + { 7, 2 }, + { 15, 1 }, + { 14, 1 }, +}; + +static int ltq_spi_setup(struct spi_device *spi) +{ + struct ltq_spi *hw = ltq_spi_to_hw(spi); + struct ltq_spi_controller_data *cdata = spi->controller_data; + struct ltq_spi_controller_state *cstate; + u32 gpocon, fgpo; + int ret; + + /* Set default word length to 8 if not set */ + if (!spi->bits_per_word) + spi->bits_per_word = 8; + + if (spi->bits_per_word > 32) + return -EINVAL; + + if (!spi->controller_state) { + cstate = kzalloc(sizeof(struct ltq_spi_controller_state), + GFP_KERNEL); + if (!cstate) + return -ENOMEM; + + spi->controller_state = cstate; + } else + return 0; + + /* + * Up to six GPIOs can be connected to the SPI module + * via GPIO alternate function to control the chip select lines. + * For more flexibility in board layout this driver can also control + * the CS lines via GPIO API. If GPIOs should be used, board setup code + * have to register the SPI device with struct ltq_spi_controller_data + * attached. + */ + if (cdata && cdata->gpio) { + ret = gpio_request(cdata->gpio, "spi-cs"); + if (ret) + return -EBUSY; + + ret = spi->mode & SPI_CS_HIGH ? 0 : 1; + gpio_direction_output(cdata->gpio, ret); + + cstate->cs_activate = ltq_spi_gpio_cs_activate; + cstate->cs_deactivate = ltq_spi_gpio_cs_deactivate; + } else { + struct ltq_spi_cs_gpio_map *cs_map = + ltq_is_ase() ? ltq_spi_cs_ase : ltq_spi_cs; + ret = ltq_gpio_request(&spi->dev, cs_map[spi->chip_select].gpio, + cs_map[spi->chip_select].mux, + 1, "spi-cs"); + if (ret) + return -EBUSY; + + gpocon = (1 << (spi->chip_select + + LTQ_SPI_GPOCON_ISCSBN_SHIFT)); + + if (spi->mode & SPI_CS_HIGH) + gpocon |= (1 << spi->chip_select); + + fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT)); + + ltq_spi_reg_setbit(hw, gpocon, LTQ_SPI_GPOCON); + ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO); + + cstate->cs_activate = ltq_spi_internal_cs_activate; + cstate->cs_deactivate = ltq_spi_internal_cs_deactivate; + } + + return 0; +} + +static void ltq_spi_cleanup(struct spi_device *spi) +{ + struct ltq_spi_controller_data *cdata = spi->controller_data; + struct ltq_spi_controller_state *cstate = spi->controller_state; + unsigned gpio; + + if (cdata && cdata->gpio) + gpio = cdata->gpio; + else + gpio = ltq_is_ase() ? ltq_spi_cs_ase[spi->chip_select].gpio : + ltq_spi_cs[spi->chip_select].gpio; + + gpio_free(gpio); + kfree(cstate); +} + +static void ltq_spi_txfifo_write(struct ltq_spi *hw) +{ + u32 fstat, data; + u16 fifo_space; + + /* Determine how much FIFOs are free for TX data */ + fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT); + fifo_space = hw->txfs - ((fstat >> LTQ_SPI_FSTAT_TXFFL_SHIFT) & + LTQ_SPI_FSTAT_TXFFL_MASK); + + if (!fifo_space) + return; + + while (hw->tx_cnt < hw->len && fifo_space) { + data = hw->get_tx(hw); + ltq_spi_reg_write(hw, data, LTQ_SPI_TB); + fifo_space--; + } +} + +static void ltq_spi_rxfifo_read(struct ltq_spi *hw) +{ + u32 fstat, data, *rx32; + u16 fifo_fill; + u8 rxbv, shift, *rx8; + + /* Determine how much FIFOs are filled with RX data */ + fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT); + fifo_fill = ((fstat >> LTQ_SPI_FSTAT_RXFFL_SHIFT) + & LTQ_SPI_FSTAT_RXFFL_MASK); + + if (!fifo_fill) + return; + + /* + * The 32 bit FIFO is always used completely independent from the + * bits_per_word value. Thus four bytes have to be read at once + * per FIFO. + */ + rx32 = (u32 *) hw->rx; + while (hw->len - hw->rx_cnt >= 4 && fifo_fill) { + *rx32++ = ltq_spi_reg_read(hw, LTQ_SPI_RB); + hw->rx_cnt += 4; + hw->rx += 4; + fifo_fill--; + } + + /* + * If there are remaining bytes, read byte count from STAT.RXBV + * register and read the data byte-wise. + */ + while (fifo_fill && hw->rx_cnt < hw->len) { + rxbv = (ltq_spi_reg_read(hw, LTQ_SPI_STAT) >> + LTQ_SPI_STAT_RXBV_SHIFT) & LTQ_SPI_STAT_RXBV_MASK; + data = ltq_spi_reg_read(hw, LTQ_SPI_RB); + + shift = (rxbv - 1) * 8; + rx8 = hw->rx; + + while (rxbv) { + *rx8++ = (data >> shift) & 0xFF; + rxbv--; + shift -= 8; + hw->rx_cnt++; + hw->rx++; + } + + fifo_fill--; + } +} + +static void ltq_spi_rxreq_set(struct ltq_spi *hw) +{ + u32 rxreq, rxreq_max, rxtodo; + + rxtodo = ltq_spi_reg_read(hw, LTQ_SPI_RXCNT) & LTQ_SPI_RXCNT_TODO_MASK; + + /* + * In RX-only mode the serial clock is activated only after writing + * the expected amount of RX bytes into RXREQ register. + * To avoid receive overflows at high clocks it is better to request + * only the amount of bytes that fits into all FIFOs. This value + * depends on the FIFO size implemented in hardware. + */ + rxreq = hw->len - hw->rx_cnt; + rxreq_max = hw->rxfs << 2; + rxreq = min(rxreq_max, rxreq); + + if (!rxtodo && rxreq) + ltq_spi_reg_write(hw, rxreq, LTQ_SPI_RXREQ); +} + +static inline void ltq_spi_complete(struct ltq_spi *hw) +{ + complete(&hw->done); +} + +irqreturn_t ltq_spi_tx_irq(int irq, void *data) +{ + struct ltq_spi *hw = data; + unsigned long flags; + int completed = 0; + + spin_lock_irqsave(&hw->lock, flags); + + if (hw->tx_cnt < hw->len) + ltq_spi_txfifo_write(hw); + + if (hw->tx_cnt == hw->len) + completed = 1; + + spin_unlock_irqrestore(&hw->lock, flags); + + if (completed) + ltq_spi_complete(hw); + + return IRQ_HANDLED; +} + +irqreturn_t ltq_spi_rx_irq(int irq, void *data) +{ + struct ltq_spi *hw = data; + unsigned long flags; + int completed = 0; + + spin_lock_irqsave(&hw->lock, flags); + + if (hw->rx_cnt < hw->len) { + ltq_spi_rxfifo_read(hw); + + if (hw->tx && hw->tx_cnt < hw->len) + ltq_spi_txfifo_write(hw); + } + + if (hw->rx_cnt == hw->len) + completed = 1; + else if (!hw->tx) + ltq_spi_rxreq_set(hw); + + spin_unlock_irqrestore(&hw->lock, flags); + + if (completed) + ltq_spi_complete(hw); + + return IRQ_HANDLED; +} + +irqreturn_t ltq_spi_err_irq(int irq, void *data) +{ + struct ltq_spi *hw = data; + unsigned long flags; + + spin_lock_irqsave(&hw->lock, flags); + + /* Disable all interrupts */ + ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN); + + /* Clear all error flags */ + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); + + /* Flush FIFOs */ + ltq_spi_reg_setbit(hw, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON); + ltq_spi_reg_setbit(hw, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON); + + hw->status = -EIO; + spin_unlock_irqrestore(&hw->lock, flags); + + ltq_spi_complete(hw); + + return IRQ_HANDLED; +} + +static int ltq_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) +{ + struct ltq_spi *hw = ltq_spi_to_hw(spi); + u32 irq_flags = 0; + + hw->tx = t->tx_buf; + hw->rx = t->rx_buf; + hw->len = t->len; + hw->tx_cnt = 0; + hw->rx_cnt = 0; + hw->status = 0; + INIT_COMPLETION(hw->done); + + ltq_spi_xmit_set(hw, t); + + /* Enable error interrupts */ + ltq_spi_reg_setbit(hw, LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN); + + if (hw->tx) { + /* Initially fill TX FIFO with as much data as possible */ + ltq_spi_txfifo_write(hw); + irq_flags |= LTQ_SPI_IRNEN_T; + + /* Always enable RX interrupt in Full Duplex mode */ + if (hw->rx) + irq_flags |= LTQ_SPI_IRNEN_R; + } else if (hw->rx) { + /* Start RX clock */ + ltq_spi_rxreq_set(hw); + + /* Enable RX interrupt to receive data from RX FIFOs */ + irq_flags |= LTQ_SPI_IRNEN_R; + } + + /* Enable TX or RX interrupts */ + ltq_spi_reg_setbit(hw, irq_flags, LTQ_SPI_IRNEN); + wait_for_completion_interruptible(&hw->done); + + /* Disable all interrupts */ + ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN); + + /* + * Return length of current transfer for bitbang utility code if + * no errors occured during transmission. + */ + if (!hw->status) + hw->status = hw->len; + + return hw->status; +} + +static const struct ltq_spi_irq_map ltq_spi_irqs[] = { + { "spi_tx", ltq_spi_tx_irq }, + { "spi_rx", ltq_spi_rx_irq }, + { "spi_err", ltq_spi_err_irq }, +}; + +static int __devinit +ltq_spi_probe(struct platform_device *pdev) +{ + struct spi_master *master; + struct resource *r; + struct ltq_spi *hw; + struct ltq_spi_platform_data *pdata = pdev->dev.platform_data; + int ret, i; + u32 data, id; + + master = spi_alloc_master(&pdev->dev, sizeof(struct ltq_spi)); + if (!master) { + dev_err(&pdev->dev, "spi_alloc_master\n"); + ret = -ENOMEM; + goto err; + } + + hw = spi_master_get_devdata(master); + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (r == NULL) { + dev_err(&pdev->dev, "platform_get_resource\n"); + ret = -ENOENT; + goto err_master; + } + + r = devm_request_mem_region(&pdev->dev, r->start, resource_size(r), + pdev->name); + if (!r) { + dev_err(&pdev->dev, "devm_request_mem_region\n"); + ret = -ENXIO; + goto err_master; + } + + hw->base = devm_ioremap_nocache(&pdev->dev, r->start, resource_size(r)); + if (!hw->base) { + dev_err(&pdev->dev, "devm_ioremap_nocache\n"); + ret = -ENXIO; + goto err_master; + } + + hw->fpiclk = clk_get_fpi(); + if (IS_ERR(hw->fpiclk)) { + dev_err(&pdev->dev, "fpi clk\n"); + ret = PTR_ERR(hw->fpiclk); + goto err_master; + } + + hw->spiclk = clk_get(&pdev->dev, NULL); + if (IS_ERR(hw->spiclk)) { + dev_err(&pdev->dev, "spi clk\n"); + ret = PTR_ERR(hw->spiclk); + goto err_master; + } + + memset(hw->irq, 0, sizeof(hw->irq)); + for (i = 0; i < ARRAY_SIZE(ltq_spi_irqs); i++) { + ret = platform_get_irq_byname(pdev, ltq_spi_irqs[i].name); + if (0 > ret) { + dev_err(&pdev->dev, "platform_get_irq_byname\n"); + goto err_irq; + } + + hw->irq[i] = ret; + ret = request_irq(hw->irq[i], ltq_spi_irqs[i].handler, + 0, ltq_spi_irqs[i].name, hw); + if (ret) { + dev_err(&pdev->dev, "request_irq\n"); + goto err_irq; + } + } + + hw->bitbang.master = spi_master_get(master); + hw->bitbang.chipselect = ltq_spi_chipselect; + hw->bitbang.setup_transfer = ltq_spi_setup_transfer; + hw->bitbang.txrx_bufs = ltq_spi_txrx_bufs; + + master->bus_num = pdev->id; + master->num_chipselect = pdata->num_chipselect; + master->setup = ltq_spi_setup; + master->cleanup = ltq_spi_cleanup; + + hw->dev = &pdev->dev; + init_completion(&hw->done); + spin_lock_init(&hw->lock); + + /* Set GPIO alternate functions to SPI */ + ltq_gpio_request(&pdev->dev, LTQ_SPI_GPIO_DI, 2, 0, "spi-di"); + ltq_gpio_request(&pdev->dev, LTQ_SPI_GPIO_DO, 2, 1, "spi-do"); + ltq_gpio_request(&pdev->dev, LTQ_SPI_GPIO_CLK, 2, 1, "spi-clk"); + + ltq_spi_hw_enable(hw); + + /* Read module capabilities */ + id = ltq_spi_reg_read(hw, LTQ_SPI_ID); + hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK; + hw->rxfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK; + hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0; + + ltq_spi_config_mode_set(hw); + + /* Enable error checking, disable TX/RX, set idle value high */ + data = LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN | + LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN | + LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF | LTQ_SPI_CON_IDLE; + ltq_spi_reg_write(hw, data, LTQ_SPI_CON); + + /* Enable master mode and clear error flags */ + ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETMS | + LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); + + /* Reset GPIO/CS registers */ + ltq_spi_reg_write(hw, 0x0, LTQ_SPI_GPOCON); + ltq_spi_reg_write(hw, 0xFF00, LTQ_SPI_FGPO); + + /* Enable and flush FIFOs */ + ltq_spi_reset_fifos(hw); + + ret = spi_bitbang_start(&hw->bitbang); + if (ret) { + dev_err(&pdev->dev, "spi_bitbang_start\n"); + goto err_bitbang; + } + + platform_set_drvdata(pdev, hw); + + pr_info("Lantiq SoC SPI controller rev %u (TXFS %u, RXFS %u, DMA %u)\n", + id & LTQ_SPI_ID_REV_MASK, hw->txfs, hw->rxfs, hw->dma_support); + + return 0; + +err_bitbang: + ltq_spi_hw_disable(hw); + +err_irq: + clk_put(hw->fpiclk); + + for (; i > 0; i--) + free_irq(hw->irq[i], hw); + +err_master: + spi_master_put(master); + +err: + return ret; +} + +static int __devexit +ltq_spi_remove(struct platform_device *pdev) +{ + struct ltq_spi *hw = platform_get_drvdata(pdev); + int ret, i; + + ret = spi_bitbang_stop(&hw->bitbang); + if (ret) + return ret; + + platform_set_drvdata(pdev, NULL); + + ltq_spi_config_mode_set(hw); + ltq_spi_hw_disable(hw); + + for (i = 0; i < ARRAY_SIZE(hw->irq); i++) + if (0 < hw->irq[i]) + free_irq(hw->irq[i], hw); + + gpio_free(LTQ_SPI_GPIO_DI); + gpio_free(LTQ_SPI_GPIO_DO); + gpio_free(LTQ_SPI_GPIO_CLK); + + clk_put(hw->fpiclk); + spi_master_put(hw->bitbang.master); + + return 0; +} + +static struct platform_driver ltq_spi_driver = { + .probe = ltq_spi_probe, + .remove = __devexit_p(ltq_spi_remove), + .driver = { + .name = "ltq_spi", + .owner = THIS_MODULE, + }, +}; + +module_platform_driver(ltq_spi_driver); + +MODULE_DESCRIPTION("Lantiq SoC SPI controller driver"); +MODULE_AUTHOR("Daniel Schwierzeck "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:ltq-spi"); diff --git a/target/linux/lantiq/files/drivers/spi/spi_svip.c b/target/linux/lantiq/files/drivers/spi/spi_svip.c new file mode 100644 index 0000000000..ae25c20b3a --- /dev/null +++ b/target/linux/lantiq/files/drivers/spi/spi_svip.c @@ -0,0 +1,955 @@ +/************************************************************************ + * + * Copyright (c) 2008 + * Infineon Technologies AG + * St. Martin Strasse 53; 81669 Muenchen; Germany + * + * Inspired by Atmel AT32/AT91 SPI Controller driver + * Copyright (c) 2006 Atmel Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + ************************************************************************/ +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +#define SFRAME_SIZE 512 /* bytes */ +#define FIFO_HEADROOM 2 /* words */ + +#define SVIP_SSC_RFIFO_WORDS 8 + +enum svip_ssc_dir { + SSC_RXTX, + SSC_RX, + SSC_TX, + SSC_UNDEF +}; + +/* + * The core SPI transfer engine just talks to a register bank to set up + * DMA transfers; transfer queue progress is driven by IRQs. The clock + * framework provides the base clock, subdivided for each spi_device. + */ +struct svip_ssc_device { + struct svip_reg_ssc *regs; + enum svip_ssc_dir bus_dir; + struct spi_device *stay; + + u8 stopping; + struct list_head queue; + struct spi_transfer *current_transfer; + int remaining_bytes; + int rx_bytes; + int tx_bytes; + + char intname[4][16]; + + spinlock_t lock; +}; + +static int svip_ssc_setup(struct spi_device *spi); + +extern unsigned int ltq_get_fbs0_hz(void); + +static void cs_activate(struct svip_ssc_device *ssc_dev, struct spi_device *spi) +{ + ssc_dev->regs->whbgpostat = 0x0001 << spi->chip_select; /* activate the chip select */ +} + +static void cs_deactivate(struct svip_ssc_device *ssc_dev, struct spi_device *spi) +{ + ssc_dev->regs->whbgpostat = 0x0100 << spi->chip_select; /* deactivate the chip select */ +} + +/* + * "Normally" returns Byte Valid = 4. + * If the unaligned remainder of the packet is 3 bytes, these have to be + * transferred as a combination of a 16-bit and a 8-bit FPI transfer. For + * 2 or 1 remaining bytes a single 16-bit or 8-bit transfer will do. + */ +static int inline _estimate_bv(int byte_pos, int bytelen) +{ + int remainder = bytelen % 4; + + if (byte_pos < (bytelen - remainder)) + return 4; + + if (remainder == 3) + { + if (byte_pos == (bytelen - remainder)) + return 2; + else + return 1; + } + return remainder; +} + +/* + * Submit next transfer. + * lock is held, spi irq is blocked + */ +static void svip_ssc_next_xfer(struct spi_master *master, + struct spi_message *msg) +{ + struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); + struct spi_transfer *xfer; + unsigned char *buf_ptr; + + xfer = ssc_dev->current_transfer; + if (!xfer || ssc_dev->remaining_bytes == 0) { + if (xfer) + xfer = list_entry(xfer->transfer_list.next, + struct spi_transfer, transfer_list); + else + xfer = list_entry(msg->transfers.next, + struct spi_transfer, transfer_list); + ssc_dev->remaining_bytes = xfer->len; + ssc_dev->rx_bytes = 0; + ssc_dev->tx_bytes = 0; + ssc_dev->current_transfer = xfer; + ssc_dev->regs->sfcon = 0; /* reset Serial Framing */ + + /* enable and flush RX/TX FIFO */ + ssc_dev->regs->rxfcon = + SSC_RXFCON_RXFITL_VAL(SVIP_SSC_RFIFO_WORDS-FIFO_HEADROOM) | + SSC_RXFCON_RXFLU | /* Receive FIFO Flush */ + SSC_RXFCON_RXFEN; /* Receive FIFO Enable */ + + ssc_dev->regs->txfcon = + SSC_TXFCON_TXFITL_VAL(FIFO_HEADROOM) | + SSC_TXFCON_TXFLU | /* Transmit FIFO Flush */ + SSC_TXFCON_TXFEN; /* Transmit FIFO Enable */ + + asm("sync"); + + /* select mode RXTX, RX or TX */ + if (xfer->rx_buf && xfer->tx_buf) /* RX and TX */ + { + if (ssc_dev->bus_dir != SSC_RXTX) + { + ssc_dev->regs->mcon &= ~(SSC_MCON_RXOFF | SSC_MCON_TXOFF); + ssc_dev->bus_dir = SSC_RXTX; + ssc_dev->regs->irnen = SSC_IRNEN_T | SSC_IRNEN_F | SSC_IRNEN_E; + } + ssc_dev->regs->sfcon = + SSC_SFCON_PLEN_VAL(0) | + SSC_SFCON_DLEN_VAL(((xfer->len-1)%SFRAME_SIZE)*8+7) | + SSC_SFCON_STOP | + SSC_SFCON_ICLK_VAL(2) | + SSC_SFCON_IDAT_VAL(2) | + SSC_SFCON_IAEN | + SSC_SFCON_SFEN; + + } + else if (xfer->rx_buf) /* RX only */ + { + if (ssc_dev->bus_dir != SSC_RX) + { + ssc_dev->regs->mcon = + (ssc_dev->regs->mcon | SSC_MCON_TXOFF) & ~SSC_MCON_RXOFF; + + ssc_dev->bus_dir = SSC_RX; + + ssc_dev->regs->irnen = SSC_IRNEN_R | SSC_IRNEN_E; + } + /* Initiate clock generation for Rx-Only Transfer. In case of RX-only transfer, + * rx_bytes represents the number of already requested bytes. + */ + ssc_dev->rx_bytes = min(xfer->len, (unsigned)(SVIP_SSC_RFIFO_WORDS*4)); + ssc_dev->regs->rxreq = ssc_dev->rx_bytes; + } + else /* TX only */ + { + if (ssc_dev->bus_dir != SSC_TX) + { + ssc_dev->regs->mcon = + (ssc_dev->regs->mcon | SSC_MCON_RXOFF) & ~SSC_MCON_TXOFF; + + ssc_dev->bus_dir = SSC_TX; + + ssc_dev->regs->irnen = + SSC_IRNEN_T | SSC_IRNEN_F | SSC_IRNEN_E; + } + ssc_dev->regs->sfcon = + SSC_SFCON_PLEN_VAL(0) | + SSC_SFCON_DLEN_VAL(((xfer->len-1)%SFRAME_SIZE)*8+7) | + SSC_SFCON_STOP | + SSC_SFCON_ICLK_VAL(2) | + SSC_SFCON_IDAT_VAL(2) | + SSC_SFCON_IAEN | + SSC_SFCON_SFEN; + } + } + + if (xfer->tx_buf) + { + int outstanding; + int i; + int fstat = ssc_dev->regs->fstat; + int txffl = SSC_FSTAT_TXFFL_GET(fstat); + int rxffl = SSC_FSTAT_RXFFL_GET(fstat); + + outstanding = txffl; + + if (xfer->rx_buf) + { + outstanding += rxffl; + if (SSC_STATE_BSY_GET(ssc_dev->regs->state)) + outstanding++; + + while (rxffl) /* is 0 in TX-Only mode */ + { + unsigned int rb; + int rxbv = _estimate_bv(ssc_dev->rx_bytes, xfer->len); + rb = ssc_dev->regs->rb; + for (i=0; irx_buf)[ssc_dev->rx_bytes] = + (rb >> ((rxbv-i-1)*8)) & 0xFF; + + ssc_dev->rx_bytes++; + } + rxffl--; + outstanding--; + } + ssc_dev->remaining_bytes = xfer->len - ssc_dev->rx_bytes; + } + + /* for last Tx cycle set TxFifo threshold to 0 */ + if ((xfer->len - ssc_dev->tx_bytes) <= + (4*(SVIP_SSC_RFIFO_WORDS-1-outstanding))) + { + ssc_dev->regs->txfcon = SSC_TXFCON_TXFITL_VAL(0) | + SSC_TXFCON_TXFEN; + } + + while ((ssc_dev->tx_bytes < xfer->len) && + (outstanding < (SVIP_SSC_RFIFO_WORDS-1))) + { + unsigned int tb = 0; + int txbv = _estimate_bv(ssc_dev->tx_bytes, xfer->len); + + for (i=0; itx_buf)[ssc_dev->tx_bytes] << + ((txbv-i-1)*8); + + ssc_dev->tx_bytes++; + } + switch(txbv) + { +#ifdef __BIG_ENDIAN + case 1: + *((unsigned char *)(&(ssc_dev->regs->tb))+3) = tb & 0xFF; + break; + case 2: + *((unsigned short *)(&(ssc_dev->regs->tb))+1) = tb & 0xFFFF; + break; +#else /* __LITTLE_ENDIAN */ + case 1: + *((unsigned char *)(&(ssc_dev->regs->tb))) = tb & 0xFF; + break; + case 2: + *((unsigned short *)(&(ssc_dev->regs->tb))) = tb & 0xFFFF; + break; +#endif + default: + ssc_dev->regs->tb = tb; + } + outstanding++; + } + } + else /* xfer->tx_buf == NULL -> RX only! */ + { + int j; + int rxffl = SSC_FSTAT_RXFFL_GET(ssc_dev->regs->fstat); + int rxbv = 0; + unsigned int rbuf; + + buf_ptr = (unsigned char*)xfer->rx_buf + + (xfer->len - ssc_dev->remaining_bytes); + + for (j = 0; j < rxffl; j++) + { + rxbv = SSC_STATE_RXBV_GET(ssc_dev->regs->state); + rbuf = ssc_dev->regs->rb; + + if (rxbv == 4) + { + *((unsigned int*)buf_ptr+j) = ntohl(rbuf); + } + else + { + int b; +#ifdef __BIG_ENDIAN + for (b = 0; b < rxbv; b++) + { + buf_ptr[4*j+b] = ((unsigned char*)(&rbuf))[4-rxbv+b]; + } +#else /* __LITTLE_ENDIAN */ + for (b = 0; b < rxbv; b++) + { + buf_ptr[4*j+b] = ((unsigned char*)(&rbuf))[rxbv-1-b]; + } +#endif + } + ssc_dev->remaining_bytes -= rxbv; + } + if ((ssc_dev->rx_bytes < xfer->len) && + !SSC_STATE_BSY_GET(ssc_dev->regs->state)) + { + int rxreq = min(xfer->len - ssc_dev->rx_bytes, + (unsigned)(SVIP_SSC_RFIFO_WORDS*4)); + + ssc_dev->rx_bytes += rxreq; + ssc_dev->regs->rxreq = rxreq; + } + + if (ssc_dev->remaining_bytes < 0) + { + printk("ssc_dev->remaining_bytes = %d! xfer->len = %d, " + "rxffl=%d, rxbv=%d\n", ssc_dev->remaining_bytes, xfer->len, + rxffl, rxbv); + + ssc_dev->remaining_bytes = 0; + } + } +} + +/* + * Submit next message. + * lock is held + */ +static void svip_ssc_next_message(struct spi_master *master) +{ + struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); + struct spi_message *msg; + struct spi_device *spi; + + BUG_ON(ssc_dev->current_transfer); + + msg = list_entry(ssc_dev->queue.next, struct spi_message, queue); + spi = msg->spi; + + dev_dbg(master->dev.parent, "start message %p on %p\n", msg, spi); + + /* select chip if it's not still active */ + if (ssc_dev->stay) { + if (ssc_dev->stay != spi) { + cs_deactivate(ssc_dev, ssc_dev->stay); + svip_ssc_setup(spi); + cs_activate(ssc_dev, spi); + } + ssc_dev->stay = NULL; + } + else { + svip_ssc_setup(spi); + cs_activate(ssc_dev, spi); + } + + svip_ssc_next_xfer(master, msg); +} + +/* + * Report message completion. + * lock is held + */ +static void +svip_ssc_msg_done(struct spi_master *master, struct svip_ssc_device *ssc_dev, + struct spi_message *msg, int status, int stay) +{ + if (!stay || status < 0) + cs_deactivate(ssc_dev, msg->spi); + else + ssc_dev->stay = msg->spi; + + list_del(&msg->queue); + msg->status = status; + + dev_dbg(master->dev.parent, + "xfer complete: %u bytes transferred\n", + msg->actual_length); + + spin_unlock(&ssc_dev->lock); + msg->complete(msg->context); + spin_lock(&ssc_dev->lock); + + ssc_dev->current_transfer = NULL; + + /* continue if needed */ + if (list_empty(&ssc_dev->queue) || ssc_dev->stopping) + ; /* TODO: disable hardware */ + else + svip_ssc_next_message(master); +} + +static irqreturn_t svip_ssc_eir_handler(int irq, void *dev_id) +{ + struct platform_device *pdev = (struct platform_device*)dev_id; + struct spi_master *master = platform_get_drvdata(pdev); + struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); + + dev_err (&pdev->dev, "ERROR: errirq. STATE = 0x%0lx\n", + ssc_dev->regs->state); + return IRQ_HANDLED; +} + +static irqreturn_t svip_ssc_rir_handler(int irq, void *dev_id) +{ + struct platform_device *pdev = (struct platform_device*)dev_id; + struct spi_master *master = platform_get_drvdata(pdev); + struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); + struct spi_message *msg; + struct spi_transfer *xfer; + + xfer = ssc_dev->current_transfer; + msg = list_entry(ssc_dev->queue.next, struct spi_message, queue); + + /* Tx and Rx Interrupts are fairly unpredictable. Just leave interrupt + * handler for spurious Interrupts! + */ + if (!xfer) { + dev_dbg(master->dev.parent, + "%s(%d): xfer = NULL\n", __FUNCTION__, irq); + goto out; + } + if ( !(xfer->rx_buf) ) { + dev_dbg(master->dev.parent, + "%s(%d): xfer->rx_buf = NULL\n", __FUNCTION__, irq); + goto out; + } + if (ssc_dev->remaining_bytes > 0) + { + /* + * Keep going, we still have data to send in + * the current transfer. + */ + svip_ssc_next_xfer(master, msg); + } + + if (ssc_dev->remaining_bytes == 0) + { + msg->actual_length += xfer->len; + + if (msg->transfers.prev == &xfer->transfer_list) { + /* report completed message */ + svip_ssc_msg_done(master, ssc_dev, msg, 0, + xfer->cs_change); + } + else { + if (xfer->cs_change) { + cs_deactivate(ssc_dev, msg->spi); + udelay(1); /* not nice in interrupt context */ + cs_activate(ssc_dev, msg->spi); + } + + /* Not done yet. Submit the next transfer. */ + svip_ssc_next_xfer(master, msg); + } + } +out: + return IRQ_HANDLED; +} + +static irqreturn_t svip_ssc_tir_handler(int irq, void *dev_id) +{ + struct platform_device *pdev = (struct platform_device*)dev_id; + struct spi_master *master = platform_get_drvdata(pdev); + struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); + struct spi_message *msg; + struct spi_transfer *xfer; + int tx_remain; + + xfer = ssc_dev->current_transfer; + msg = list_entry(ssc_dev->queue.next, struct spi_message, queue); + + /* Tx and Rx Interrupts are fairly unpredictable. Just leave interrupt + * handler for spurious Interrupts! + */ + if (!xfer) { + dev_dbg(master->dev.parent, + "%s(%d): xfer = NULL\n", __FUNCTION__, irq); + goto out; + } + if ( !(xfer->tx_buf) ) { + dev_dbg(master->dev.parent, + "%s(%d): xfer->tx_buf = NULL\n", __FUNCTION__, irq); + goto out; + } + + if (ssc_dev->remaining_bytes > 0) + { + tx_remain = xfer->len - ssc_dev->tx_bytes; + if ( tx_remain == 0 ) + { + dev_dbg(master->dev.parent, + "%s(%d): tx_remain = 0\n", __FUNCTION__, irq); + } + else + /* + * Keep going, we still have data to send in + * the current transfer. + */ + svip_ssc_next_xfer(master, msg); + } +out: + return IRQ_HANDLED; +} + +static irqreturn_t svip_ssc_fir_handler(int irq, void *dev_id) +{ + struct platform_device *pdev = (struct platform_device*)dev_id; + struct spi_master *master = platform_get_drvdata(pdev); + struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); + struct spi_message *msg; + struct spi_transfer *xfer; + + xfer = ssc_dev->current_transfer; + msg = list_entry(ssc_dev->queue.next, struct spi_message, queue); + + /* Tx and Rx Interrupts are fairly unpredictable. Just leave interrupt + * handler for spurious Interrupts! + */ + if (!xfer) { + dev_dbg(master->dev.parent, + "%s(%d): xfer = NULL\n", __FUNCTION__, irq); + goto out; + } + if ( !(xfer->tx_buf) ) { + dev_dbg(master->dev.parent, + "%s(%d): xfer->tx_buf = NULL\n", __FUNCTION__, irq); + goto out; + } + + if (ssc_dev->remaining_bytes > 0) + { + int tx_remain = xfer->len - ssc_dev->tx_bytes; + + if (tx_remain == 0) + { + /* Frame interrupt gets raised _before_ last Rx interrupt */ + if (xfer->rx_buf) + { + svip_ssc_next_xfer(master, msg); + if (ssc_dev->remaining_bytes) + printk("expected RXTX transfer to be complete!\n"); + } + ssc_dev->remaining_bytes = 0; + } + else + { + ssc_dev->regs->sfcon = SSC_SFCON_PLEN_VAL(0) | + SSC_SFCON_DLEN_VAL(SFRAME_SIZE*8-1) | + SSC_SFCON_STOP | + SSC_SFCON_ICLK_VAL(2) | + SSC_SFCON_IDAT_VAL(2) | + SSC_SFCON_IAEN | + SSC_SFCON_SFEN; + } + } + + if (ssc_dev->remaining_bytes == 0) + { + msg->actual_length += xfer->len; + + if (msg->transfers.prev == &xfer->transfer_list) { + /* report completed message */ + svip_ssc_msg_done(master, ssc_dev, msg, 0, + xfer->cs_change); + } + else { + if (xfer->cs_change) { + cs_deactivate(ssc_dev, msg->spi); + udelay(1); /* not nice in interrupt context */ + cs_activate(ssc_dev, msg->spi); + } + + /* Not done yet. Submit the next transfer. */ + svip_ssc_next_xfer(master, msg); + } + } + +out: + return IRQ_HANDLED; +} + +/* the spi->mode bits understood by this driver: */ +#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP) + +static int svip_ssc_setup(struct spi_device *spi) +{ + struct spi_master *master = spi->master; + struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); + unsigned int bits = spi->bits_per_word; + unsigned int br, sck_hz = spi->max_speed_hz; + unsigned long flags; + + if (ssc_dev->stopping) + return -ESHUTDOWN; + + if (spi->chip_select >= master->num_chipselect) { + dev_dbg(&spi->dev, + "setup: invalid chipselect %u (%u defined)\n", + spi->chip_select, master->num_chipselect); + return -EINVAL; + } + + if (bits == 0) + bits = 8; + if (bits != 8) { + dev_dbg(&spi->dev, + "setup: invalid bits_per_word %u (expect 8)\n", + bits); + return -EINVAL; + } + + if (spi->mode & ~MODEBITS) { + dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", + spi->mode & ~MODEBITS); + return -EINVAL; + } + + /* Disable SSC */ + ssc_dev->regs->whbstate = SSC_WHBSTATE_CLREN; + + if (sck_hz == 0) + sck_hz = 10000; + + br = ltq_get_fbs0_hz()/(2 *sck_hz); + if (ltq_get_fbs0_hz()%(2 *sck_hz) == 0) + br = br -1; + ssc_dev->regs->br = br; + + /* set Control Register */ + ssc_dev->regs->mcon = SSC_MCON_ENBV | + SSC_MCON_RUEN | + SSC_MCON_TUEN | + SSC_MCON_AEN | + SSC_MCON_REN | + SSC_MCON_TEN | + (spi->mode & SPI_CPOL ? SSC_MCON_PO : 0) | /* Clock Polarity */ + (spi->mode & SPI_CPHA ? 0 : SSC_MCON_PH) | /* Tx on trailing edge */ + (spi->mode & SPI_LOOP ? SSC_MCON_LB : 0) | /* Loopback */ + (spi->mode & SPI_LSB_FIRST ? 0 : SSC_MCON_HB); /* MSB first */ + ssc_dev->bus_dir = SSC_UNDEF; + + /* Enable SSC */ + ssc_dev->regs->whbstate = SSC_WHBSTATE_SETEN; + asm("sync"); + + spin_lock_irqsave(&ssc_dev->lock, flags); + if (ssc_dev->stay == spi) + ssc_dev->stay = NULL; + cs_deactivate(ssc_dev, spi); + spin_unlock_irqrestore(&ssc_dev->lock, flags); + + dev_dbg(&spi->dev, + "setup: %u Hz bpw %u mode 0x%02x cs %u\n", + sck_hz, bits, spi->mode, spi->chip_select); + + return 0; +} + +static int svip_ssc_transfer(struct spi_device *spi, struct spi_message *msg) +{ + struct spi_master *master = spi->master; + struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); + struct spi_transfer *xfer; + unsigned long flags; + + dev_dbg(&spi->dev, "new message %p submitted\n", msg); + + if (unlikely(list_empty(&msg->transfers) + || !spi->max_speed_hz)) { + return -EINVAL; + } + + if (ssc_dev->stopping) + return -ESHUTDOWN; + + list_for_each_entry(xfer, &msg->transfers, transfer_list) { + if (!(xfer->tx_buf || xfer->rx_buf) || (xfer->len == 0)) { + dev_dbg(&spi->dev, "missing rx or tx buf\n"); + return -EINVAL; + } + + /* FIXME implement these protocol options!! */ + if (xfer->bits_per_word || xfer->speed_hz) { + dev_dbg(&spi->dev, "no protocol options yet\n"); + return -ENOPROTOOPT; + } + +#ifdef VERBOSE + dev_dbg(spi->dev, + " xfer %p: len %u tx %p/%08x rx %p/%08x\n", + xfer, xfer->len, + xfer->tx_buf, xfer->tx_dma, + xfer->rx_buf, xfer->rx_dma); +#endif + } + + msg->status = -EINPROGRESS; + msg->actual_length = 0; + + spin_lock_irqsave(&ssc_dev->lock, flags); + list_add_tail(&msg->queue, &ssc_dev->queue); + if (!ssc_dev->current_transfer) + { + /* start transmission machine, if not started yet */ + svip_ssc_next_message(master); + } + spin_unlock_irqrestore(&ssc_dev->lock, flags); + + return 0; +} + +static void svip_ssc_cleanup(struct spi_device *spi) +{ + struct svip_ssc_device *ssc_dev = spi_master_get_devdata(spi->master); + unsigned long flags; + + if (!spi->controller_state) + return; + + spin_lock_irqsave(&ssc_dev->lock, flags); + if (ssc_dev->stay == spi) { + ssc_dev->stay = NULL; + cs_deactivate(ssc_dev, spi); + } + spin_unlock_irqrestore(&ssc_dev->lock, flags); +} + +/*-------------------------------------------------------------------------*/ + +static int __init svip_ssc_probe(struct platform_device *pdev) +{ + int ret; + struct spi_master *master; + struct svip_ssc_device *ssc_dev; + struct resource *res_regs; + int irq; + + ret = -ENOMEM; + + /* setup spi core then atmel-specific driver state */ + master = spi_alloc_master(&pdev->dev, sizeof (*ssc_dev)); + if (!master) + { + dev_err (&pdev->dev, "ERROR: no memory for master spi\n"); + goto errout; + } + + ssc_dev = spi_master_get_devdata(master); + platform_set_drvdata(pdev, master); + + master->bus_num = pdev->id; + master->num_chipselect = 8; + master->mode_bits = MODEBITS; + master->setup = svip_ssc_setup; + master->transfer = svip_ssc_transfer; + master->cleanup = svip_ssc_cleanup; + + spin_lock_init(&ssc_dev->lock); + INIT_LIST_HEAD(&ssc_dev->queue); + + /* retrive register configration */ + res_regs = platform_get_resource_byname (pdev, IORESOURCE_MEM, "regs"); + if (NULL == res_regs) + { + dev_err (&pdev->dev, "ERROR: missed 'regs' resource\n"); + goto spierr; + } + + ssc_dev->regs = (struct svip_reg_ssc*)KSEG1ADDR(res_regs->start); + + irq = platform_get_irq_byname (pdev, "tx"); + if (irq < 0) + goto irqerr; + sprintf(ssc_dev->intname[0], "%s_tx", pdev->name); + ret = devm_request_irq(&pdev->dev, irq, svip_ssc_tir_handler, + IRQF_DISABLED, ssc_dev->intname[0], pdev); + if (ret != 0) + goto irqerr; + + irq = platform_get_irq_byname (pdev, "rx"); + if (irq < 0) + goto irqerr; + sprintf(ssc_dev->intname[1], "%s_rx", pdev->name); + ret = devm_request_irq(&pdev->dev, irq, svip_ssc_rir_handler, + IRQF_DISABLED, ssc_dev->intname[1], pdev); + if (ret != 0) + goto irqerr; + + irq = platform_get_irq_byname (pdev, "err"); + if (irq < 0) + goto irqerr; + sprintf(ssc_dev->intname[2], "%s_err", pdev->name); + ret = devm_request_irq(&pdev->dev, irq, svip_ssc_eir_handler, + IRQF_DISABLED, ssc_dev->intname[2], pdev); + if (ret != 0) + goto irqerr; + + irq = platform_get_irq_byname (pdev, "frm"); + if (irq < 0) + goto irqerr; + sprintf(ssc_dev->intname[3], "%s_frm", pdev->name); + ret = devm_request_irq(&pdev->dev, irq, svip_ssc_fir_handler, + IRQF_DISABLED, ssc_dev->intname[3], pdev); + if (ret != 0) + goto irqerr; + + /* + * Initialize the Hardware + */ + + /* Clear enable bit, i.e. put SSC into configuration mode */ + ssc_dev->regs->whbstate = SSC_WHBSTATE_CLREN; + /* enable SSC core to run at fpi clock */ + ssc_dev->regs->clc = SSC_CLC_RMC_VAL(1); + asm("sync"); + + /* GPIO CS */ + ssc_dev->regs->gpocon = SSC_GPOCON_ISCSBN_VAL(0xFF); + ssc_dev->regs->whbgpostat = SSC_WHBGPOSTAT_SETOUTN_VAL(0xFF); /* CS to high */ + + /* Set Master mode */ + ssc_dev->regs->whbstate = SSC_WHBSTATE_SETMS; + + /* enable and flush RX/TX FIFO */ + ssc_dev->regs->rxfcon = SSC_RXFCON_RXFITL_VAL(SVIP_SSC_RFIFO_WORDS-FIFO_HEADROOM) | + SSC_RXFCON_RXFLU | /* Receive FIFO Flush */ + SSC_RXFCON_RXFEN; /* Receive FIFO Enable */ + + ssc_dev->regs->txfcon = SSC_TXFCON_TXFITL_VAL(FIFO_HEADROOM) | + SSC_TXFCON_TXFLU | /* Transmit FIFO Flush */ + SSC_TXFCON_TXFEN; /* Transmit FIFO Enable */ + asm("sync"); + + /* enable IRQ */ + ssc_dev->regs->irnen = SSC_IRNEN_E; + + dev_info(&pdev->dev, "controller at 0x%08lx (irq %d)\n", + (unsigned long)ssc_dev->regs, platform_get_irq_byname (pdev, "rx")); + + ret = spi_register_master(master); + if (ret) + goto out_reset_hw; + + return 0; + +out_reset_hw: + +irqerr: + devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "tx"), pdev); + devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "rx"), pdev); + devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "err"), pdev); + devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "frm"), pdev); + +spierr: + + spi_master_put(master); + +errout: + return ret; +} + +static int __exit svip_ssc_remove(struct platform_device *pdev) +{ + struct spi_master *master = platform_get_drvdata(pdev); + struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); + struct spi_message *msg; + + /* reset the hardware and block queue progress */ + spin_lock_irq(&ssc_dev->lock); + ssc_dev->stopping = 1; + /* TODO: shutdown hardware */ + spin_unlock_irq(&ssc_dev->lock); + + /* Terminate remaining queued transfers */ + list_for_each_entry(msg, &ssc_dev->queue, queue) { + /* REVISIT unmapping the dma is a NOP on ARM and AVR32 + * but we shouldn't depend on that... + */ + msg->status = -ESHUTDOWN; + msg->complete(msg->context); + } + + devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "tx"), pdev); + devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "rx"), pdev); + devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "err"), pdev); + devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "frm"), pdev); + + spi_unregister_master(master); + platform_set_drvdata(pdev, NULL); + spi_master_put(master); + return 0; +} + +#ifdef CONFIG_PM +static int svip_ssc_suspend(struct platform_device *pdev, pm_message_t mesg) +{ + struct spi_master *master = platform_get_drvdata(pdev); + struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); + + clk_disable(ssc_dev->clk); + return 0; +} + +static int svip_ssc_resume(struct platform_device *pdev) +{ + struct spi_master *master = platform_get_drvdata(pdev); + struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); + + clk_enable(ssc_dev->clk); + return 0; +} +#endif + +static struct platform_driver svip_ssc_driver = { + .driver = { + .name = "ifx_ssc", + .owner = THIS_MODULE, + }, + .probe = svip_ssc_probe, +#ifdef CONFIG_PM + .suspend = svip_ssc_suspend, + .resume = svip_ssc_resume, +#endif + .remove = __exit_p(svip_ssc_remove) +}; + +int __init svip_ssc_init(void) +{ + return platform_driver_register(&svip_ssc_driver); +} + +void __exit svip_ssc_exit(void) +{ + platform_driver_unregister(&svip_ssc_driver); +} + +module_init(svip_ssc_init); +module_exit(svip_ssc_exit); + +MODULE_ALIAS("platform:ifx_ssc"); +MODULE_DESCRIPTION("Lantiq SSC Controller driver"); +MODULE_AUTHOR("Andreas Schmidt "); +MODULE_AUTHOR("Jevgenijs Grigorjevs "); +MODULE_LICENSE("GPL"); diff --git a/target/linux/lantiq/files/drivers/usb/dwc_otg/Kconfig b/target/linux/lantiq/files/drivers/usb/dwc_otg/Kconfig new file mode 100644 index 0000000000..e018490fa3 --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/dwc_otg/Kconfig @@ -0,0 +1,37 @@ +config DWC_OTG + tristate "Synopsis DWC_OTG support" + depends on USB + help + This driver supports Synopsis DWC_OTG IP core + embebbed on many SOCs (ralink, infineon, etc) + +choice + prompt "USB Operation Mode" + depends on DWC_OTG + default DWC_OTG_HOST_ONLY + +config DWC_OTG_HOST_ONLY + bool "HOST ONLY MODE" + depends on DWC_OTG + +#config DWC_OTG_DEVICE_ONLY +# bool "DEVICE ONLY MODE" +# depends on DWC_OTG +endchoice + +choice + prompt "Platform" + depends on DWC_OTG + default DWC_OTG_LANTIQ + +config DWC_OTG_LANTIQ + bool "Lantiq" + depends on LANTIQ + help + Danube USB Host Controller + platform support +endchoice + +config DWC_OTG_DEBUG + bool "Enable debug mode" + depends on DWC_OTG diff --git a/target/linux/lantiq/files/drivers/usb/dwc_otg/Makefile b/target/linux/lantiq/files/drivers/usb/dwc_otg/Makefile new file mode 100644 index 0000000000..d4d23554a1 --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/dwc_otg/Makefile @@ -0,0 +1,39 @@ +# +# Makefile for DWC_otg Highspeed USB controller driver +# + +ifeq ($(CONFIG_DWC_OTG_DEBUG),y) +EXTRA_CFLAGS += -DDEBUG +endif + +# Use one of the following flags to compile the software in host-only or +# device-only mode based on the configuration selected by the user +ifeq ($(CONFIG_DWC_OTG_HOST_ONLY),y) + EXTRA_CFLAGS += -DDWC_OTG_HOST_ONLY -DDWC_HOST_ONLY + EXTRA_CFLAGS += -DDWC_OTG_EN_ISOC -DDWC_EN_ISOC +else ifeq ($(CONFIG_DWC_OTG_DEVICE_ONLY),y) + EXTRA_CFLAGS += -DDWC_OTG_DEVICE_ONLY +else + EXTRA_CFLAGS += -DDWC_OTG_MODE +endif + +# EXTRA_CFLAGS += -DDWC_HS_ELECT_TST +# EXTRA_CFLAGS += -DDWC_OTG_EXT_CHG_PUMP + +ifeq ($(CONFIG_DWC_OTG_LANTIQ),y) + EXTRA_CFLAGS += -Dlinux -D__LINUX__ -DDWC_OTG_IFX -DDWC_OTG_HOST_ONLY -DDWC_HOST_ONLY -D__KERNEL__ +endif +ifeq ($(CONFIG_DWC_OTG_LANTIQ),m) + EXTRA_CFLAGS += -Dlinux -D__LINUX__ -DDWC_OTG_IFX -DDWC_HOST_ONLY -DMODULE -D__KERNEL__ -DDEBUG +endif + +obj-$(CONFIG_DWC_OTG) := dwc_otg.o +dwc_otg-objs := dwc_otg_hcd.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o +#dwc_otg-objs += dwc_otg_pcd.o dwc_otg_pcd_intr.o +dwc_otg-objs += dwc_otg_attr.o +dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o +dwc_otg-objs += dwc_otg_ifx.o +dwc_otg-objs += dwc_otg_driver.o + +#obj-$(CONFIG_DWC_OTG_IFX) := dwc_otg_ifx.o +#dwc_otg_ifx-objs := dwc_otg_ifx.o diff --git a/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_attr.c b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_attr.c new file mode 100644 index 0000000000..4675a5cc7d --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_attr.c @@ -0,0 +1,802 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_attr.c $ + * $Revision: 1.1.1.1 $ + * $Date: 2009-04-17 06:15:34 $ + * $Change: 537387 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ + +/** @file + * + * The diagnostic interface will provide access to the controller for + * bringing up the hardware and testing. The Linux driver attributes + * feature will be used to provide the Linux Diagnostic + * Interface. These attributes are accessed through sysfs. + */ + +/** @page "Linux Module Attributes" + * + * The Linux module attributes feature is used to provide the Linux + * Diagnostic Interface. These attributes are accessed through sysfs. + * The diagnostic interface will provide access to the controller for + * bringing up the hardware and testing. + + + The following table shows the attributes. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Description Access
mode Returns the current mode: 0 for device mode, 1 for host mode Read
hnpcapable Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register. + Read returns the current value. Read/Write
srpcapable Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register. + Read returns the current value. Read/Write
hnp Initiates the Host Negotiation Protocol. Read returns the status. Read/Write
srp Initiates the Session Request Protocol. Read returns the status. Read/Write
buspower Gets or sets the Power State of the bus (0 - Off or 1 - On) Read/Write
bussuspend Suspends the USB bus. Read/Write
busconnected Gets the connection status of the bus Read
gotgctl Gets or sets the Core Control Status Register. Read/Write
gusbcfg Gets or sets the Core USB Configuration Register Read/Write
grxfsiz Gets or sets the Receive FIFO Size Register Read/Write
gnptxfsiz Gets or sets the non-periodic Transmit Size Register Read/Write
gpvndctl Gets or sets the PHY Vendor Control Register Read/Write
ggpio Gets the value in the lower 16-bits of the General Purpose IO Register + or sets the upper 16 bits. Read/Write
guid Gets or sets the value of the User ID Register Read/Write
gsnpsid Gets the value of the Synopsys ID Regester Read
devspeed Gets or sets the device speed setting in the DCFG register Read/Write
enumspeed Gets the device enumeration Speed. Read
hptxfsiz Gets the value of the Host Periodic Transmit FIFO Read
hprt0 Gets or sets the value in the Host Port Control and Status Register Read/Write
regoffset Sets the register offset for the next Register Access Read/Write
regvalue Gets or sets the value of the register at the offset in the regoffset attribute. Read/Write
remote_wakeup On read, shows the status of Remote Wakeup. On write, initiates a remote + wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote + Wakeup signalling bit in the Device Control Register is set for 1 + milli-second. Read/Write
regdump Dumps the contents of core registers. Read
hcddump Dumps the current HCD state. Read
hcd_frrem Shows the average value of the Frame Remaining + field in the Host Frame Number/Frame Remaining register when an SOF interrupt + occurs. This can be used to determine the average interrupt latency. Also + shows the average Frame Remaining value for start_transfer and the "a" and + "b" sample points. The "a" and "b" sample points may be used during debugging + bto determine how long it takes to execute a section of the HCD code. Read
rd_reg_test Displays the time required to read the GNPTXFSIZ register many times + (the output shows the number of times the register is read). + Read
wr_reg_test Displays the time required to write the GNPTXFSIZ register many times + (the output shows the number of times the register is written). + Read
+ + Example usage: + To get the current mode: + cat /sys/devices/lm0/mode + + To power down the USB: + echo 0 > /sys/devices/lm0/buspower + */ +#include +#include +#include +#include +#include +#include +#include +#include /* permission constants */ + +#include + +#include "dwc_otg_plat.h" +#include "dwc_otg_attr.h" +#include "dwc_otg_driver.h" +// #include "dwc_otg_pcd.h" +#include "dwc_otg_hcd.h" + +// 20070316, winder added. +#ifndef SZ_256K +#define SZ_256K 0x00040000 +#endif + +/* + * MACROs for defining sysfs attribute + */ +#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ +{ \ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\ + uint32_t val; \ + val = dwc_read_reg32 (_addr_); \ + val = (val & (_mask_)) >> _shift_; \ + return sprintf (buf, "%s = 0x%x\n", _string_, val); \ +} +#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count) \ +{ \ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\ + uint32_t set = simple_strtoul(buf, NULL, 16); \ + uint32_t clear = set; \ + clear = ((~clear) << _shift_) & _mask_; \ + set = (set << _shift_) & _mask_; \ + dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \ + dwc_modify_reg32(_addr_, clear, set); \ + return count; \ +} + +#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ +DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ +DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ +DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store); + +#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ +DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ +DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL); + +/* + * MACROs for defining sysfs attribute for 32-bit registers + */ +#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \ +static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ +{ \ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\ + uint32_t val; \ + val = dwc_read_reg32 (_addr_); \ + return sprintf (buf, "%s = 0x%08x\n", _string_, val); \ +} +#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \ +static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count) \ +{ \ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\ + uint32_t val = simple_strtoul(buf, NULL, 16); \ + dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \ + dwc_write_reg32(_addr_, val); \ + return count; \ +} + +#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \ +DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \ +DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \ +DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store); + +#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \ +DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \ +DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL); + + +/** @name Functions for Show/Store of Attributes */ +/**@{*/ + +/** + * Show the register offset of the Register Access. + */ +static ssize_t regoffset_show( struct device *_dev, struct device_attribute *attr, char *buf) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + return snprintf(buf, sizeof("0xFFFFFFFF\n")+1,"0x%08x\n", otg_dev->reg_offset); +} + +/** + * Set the register offset for the next Register Access Read/Write + */ +static ssize_t regoffset_store( struct device *_dev, struct device_attribute *attr, const char *buf, + size_t count ) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + uint32_t offset = simple_strtoul(buf, NULL, 16); + //dev_dbg(_dev, "Offset=0x%08x\n", offset); + if (offset < SZ_256K ) { + otg_dev->reg_offset = offset; + } + else { + dev_err( _dev, "invalid offset\n" ); + } + + return count; +} +DEVICE_ATTR(regoffset, S_IRUGO|S_IWUSR, regoffset_show, regoffset_store); + +/** + * Show the value of the register at the offset in the reg_offset + * attribute. + */ +static ssize_t regvalue_show( struct device *_dev, struct device_attribute *attr, char *buf) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + uint32_t val; + volatile uint32_t *addr; + + if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) { + /* Calculate the address */ + addr = (uint32_t*)(otg_dev->reg_offset + + (uint8_t*)otg_dev->base); + //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr); + val = dwc_read_reg32( addr ); + return snprintf(buf, sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n")+1, + "Reg@0x%06x = 0x%08x\n", + otg_dev->reg_offset, val); + } + else { + dev_err(_dev, "Invalid offset (0x%0x)\n", + otg_dev->reg_offset); + return sprintf(buf, "invalid offset\n" ); + } +} + +/** + * Store the value in the register at the offset in the reg_offset + * attribute. + * + */ +static ssize_t regvalue_store( struct device *_dev, struct device_attribute *attr, const char *buf, + size_t count ) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + volatile uint32_t * addr; + uint32_t val = simple_strtoul(buf, NULL, 16); + //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val); + if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) { + /* Calculate the address */ + addr = (uint32_t*)(otg_dev->reg_offset + + (uint8_t*)otg_dev->base); + //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr); + dwc_write_reg32( addr, val ); + } + else { + dev_err(_dev, "Invalid Register Offset (0x%08x)\n", + otg_dev->reg_offset); + } + return count; +} +DEVICE_ATTR(regvalue, S_IRUGO|S_IWUSR, regvalue_show, regvalue_store); + +/* + * Attributes + */ +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<20),20,"Mode"); +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<9),9,"Mode"); +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<8),8,"Mode"); + +//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); +//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected,otg_dev->core_if->host_if->hprt0,0x01,0,"Bus Connected"); + +DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl,&(otg_dev->core_if->core_global_regs->gotgctl),"GOTGCTL"); +DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,&(otg_dev->core_if->core_global_regs->gusbcfg),"GUSBCFG"); +DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,&(otg_dev->core_if->core_global_regs->grxfsiz),"GRXFSIZ"); +DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,&(otg_dev->core_if->core_global_regs->gnptxfsiz),"GNPTXFSIZ"); +DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,&(otg_dev->core_if->core_global_regs->gpvndctl),"GPVNDCTL"); +DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,&(otg_dev->core_if->core_global_regs->ggpio),"GGPIO"); +DWC_OTG_DEVICE_ATTR_REG32_RW(guid,&(otg_dev->core_if->core_global_regs->guid),"GUID"); +DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,&(otg_dev->core_if->core_global_regs->gsnpsid),"GSNPSID"); +DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dcfg),0x3,0,"Device Speed"); +DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dsts),0x6,1,"Device Enumeration Speed"); + +DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,&(otg_dev->core_if->core_global_regs->hptxfsiz),"HPTXFSIZ"); +DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0,otg_dev->core_if->host_if->hprt0,"HPRT0"); + + +/** + * @todo Add code to initiate the HNP. + */ +/** + * Show the HNP status bit + */ +static ssize_t hnp_show( struct device *_dev, struct device_attribute *attr, char *buf) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + gotgctl_data_t val; + val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl)); + return sprintf (buf, "HstNegScs = 0x%x\n", val.b.hstnegscs); +} + +/** + * Set the HNP Request bit + */ +static ssize_t hnp_store( struct device *_dev, struct device_attribute *attr, const char *buf, + size_t count ) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + uint32_t in = simple_strtoul(buf, NULL, 16); + uint32_t *addr = (uint32_t *)&(otg_dev->core_if->core_global_regs->gotgctl); + gotgctl_data_t mem; + mem.d32 = dwc_read_reg32(addr); + mem.b.hnpreq = in; + dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32); + dwc_write_reg32(addr, mem.d32); + return count; +} +DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store); + +/** + * @todo Add code to initiate the SRP. + */ +/** + * Show the SRP status bit + */ +static ssize_t srp_show( struct device *_dev, struct device_attribute *attr, char *buf) +{ +#ifndef DWC_HOST_ONLY + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + gotgctl_data_t val; + val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl)); + return sprintf (buf, "SesReqScs = 0x%x\n", val.b.sesreqscs); +#else + return sprintf(buf, "Host Only Mode!\n"); +#endif +} + +/** + * Set the SRP Request bit + */ +static ssize_t srp_store( struct device *_dev, struct device_attribute *attr, const char *buf, + size_t count ) +{ +#ifndef DWC_HOST_ONLY + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + dwc_otg_pcd_initiate_srp(otg_dev->pcd); +#endif + return count; +} +DEVICE_ATTR(srp, 0644, srp_show, srp_store); + +/** + * @todo Need to do more for power on/off? + */ +/** + * Show the Bus Power status + */ +static ssize_t buspower_show( struct device *_dev, struct device_attribute *attr, char *buf) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + hprt0_data_t val; + val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0); + return sprintf (buf, "Bus Power = 0x%x\n", val.b.prtpwr); +} + + +/** + * Set the Bus Power status + */ +static ssize_t buspower_store( struct device *_dev, struct device_attribute *attr, const char *buf, + size_t count ) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + uint32_t on = simple_strtoul(buf, NULL, 16); + uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0; + hprt0_data_t mem; + + mem.d32 = dwc_read_reg32(addr); + mem.b.prtpwr = on; + + //dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32); + dwc_write_reg32(addr, mem.d32); + + return count; +} +DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store); + +/** + * @todo Need to do more for suspend? + */ +/** + * Show the Bus Suspend status + */ +static ssize_t bussuspend_show( struct device *_dev, struct device_attribute *attr, char *buf) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + hprt0_data_t val; + val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0); + return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp); +} + +/** + * Set the Bus Suspend status + */ +static ssize_t bussuspend_store( struct device *_dev, struct device_attribute *attr, const char *buf, + size_t count ) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + uint32_t in = simple_strtoul(buf, NULL, 16); + uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0; + hprt0_data_t mem; + mem.d32 = dwc_read_reg32(addr); + mem.b.prtsusp = in; + dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32); + dwc_write_reg32(addr, mem.d32); + return count; +} +DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store); + +/** + * Show the status of Remote Wakeup. + */ +static ssize_t remote_wakeup_show( struct device *_dev, struct device_attribute *attr, char *buf) +{ +#ifndef DWC_HOST_ONLY + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + dctl_data_t val; + val.d32 = dwc_read_reg32( &otg_dev->core_if->dev_if->dev_global_regs->dctl); + return sprintf( buf, "Remote Wakeup = %d Enabled = %d\n", + val.b.rmtwkupsig, otg_dev->pcd->remote_wakeup_enable); +#else + return sprintf(buf, "Host Only Mode!\n"); +#endif +} + +/** + * Initiate a remote wakeup of the host. The Device control register + * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable + * flag is set. + * + */ +static ssize_t remote_wakeup_store( struct device *_dev, struct device_attribute *attr, const char *buf, + size_t count ) +{ +#ifndef DWC_HOST_ONLY + uint32_t val = simple_strtoul(buf, NULL, 16); + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + if (val&1) { + dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1); + } + else { + dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0); + } +#endif + return count; +} +DEVICE_ATTR(remote_wakeup, S_IRUGO|S_IWUSR, remote_wakeup_show, + remote_wakeup_store); + +/** + * Dump global registers and either host or device registers (depending on the + * current mode of the core). + */ +static ssize_t regdump_show( struct device *_dev, struct device_attribute *attr, char *buf) +{ +#ifdef DEBUG + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + printk("%s otg_dev=0x%p\n", __FUNCTION__, otg_dev); + + dwc_otg_dump_global_registers( otg_dev->core_if); + if (dwc_otg_is_host_mode(otg_dev->core_if)) { + dwc_otg_dump_host_registers( otg_dev->core_if); + } else { + dwc_otg_dump_dev_registers( otg_dev->core_if); + } +#endif + + return sprintf( buf, "Register Dump\n" ); +} + +DEVICE_ATTR(regdump, S_IRUGO|S_IWUSR, regdump_show, 0); + +/** + * Dump the current hcd state. + */ +static ssize_t hcddump_show( struct device *_dev, struct device_attribute *attr, char *buf) +{ +#ifndef DWC_DEVICE_ONLY + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + dwc_otg_hcd_dump_state(otg_dev->hcd); +#endif + return sprintf( buf, "HCD Dump\n" ); +} + +DEVICE_ATTR(hcddump, S_IRUGO|S_IWUSR, hcddump_show, 0); + +/** + * Dump the average frame remaining at SOF. This can be used to + * determine average interrupt latency. Frame remaining is also shown for + * start transfer and two additional sample points. + */ +static ssize_t hcd_frrem_show( struct device *_dev, struct device_attribute *attr, char *buf) +{ +#ifndef DWC_DEVICE_ONLY + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + dwc_otg_hcd_dump_frrem(otg_dev->hcd); +#endif + return sprintf( buf, "HCD Dump Frame Remaining\n" ); +} + +DEVICE_ATTR(hcd_frrem, S_IRUGO|S_IWUSR, hcd_frrem_show, 0); + +/** + * Displays the time required to read the GNPTXFSIZ register many times (the + * output shows the number of times the register is read). + */ +#define RW_REG_COUNT 10000000 +#define MSEC_PER_JIFFIE 1000/HZ +static ssize_t rd_reg_test_show( struct device *_dev, struct device_attribute *attr, char *buf) +{ + int i; + int time; + int start_jiffies; + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + + printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n", + HZ, MSEC_PER_JIFFIE, loops_per_jiffy); + start_jiffies = jiffies; + for (i = 0; i < RW_REG_COUNT; i++) { + dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz); + } + time = jiffies - start_jiffies; + return sprintf( buf, "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n", + RW_REG_COUNT, time * MSEC_PER_JIFFIE, time ); +} + +DEVICE_ATTR(rd_reg_test, S_IRUGO|S_IWUSR, rd_reg_test_show, 0); + +/** + * Displays the time required to write the GNPTXFSIZ register many times (the + * output shows the number of times the register is written). + */ +static ssize_t wr_reg_test_show( struct device *_dev, struct device_attribute *attr, char *buf) +{ + int i; + int time; + int start_jiffies; + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + uint32_t reg_val; + + printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n", + HZ, MSEC_PER_JIFFIE, loops_per_jiffy); + reg_val = dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz); + start_jiffies = jiffies; + for (i = 0; i < RW_REG_COUNT; i++) { + dwc_write_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz, reg_val); + } + time = jiffies - start_jiffies; + return sprintf( buf, "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n", + RW_REG_COUNT, time * MSEC_PER_JIFFIE, time); +} + +DEVICE_ATTR(wr_reg_test, S_IRUGO|S_IWUSR, wr_reg_test_show, 0); +/**@}*/ + +/** + * Create the device files + */ +void dwc_otg_attr_create (struct device *_dev) +{ + int retval; + + retval = device_create_file(_dev, &dev_attr_regoffset); + retval += device_create_file(_dev, &dev_attr_regvalue); + retval += device_create_file(_dev, &dev_attr_mode); + retval += device_create_file(_dev, &dev_attr_hnpcapable); + retval += device_create_file(_dev, &dev_attr_srpcapable); + retval += device_create_file(_dev, &dev_attr_hnp); + retval += device_create_file(_dev, &dev_attr_srp); + retval += device_create_file(_dev, &dev_attr_buspower); + retval += device_create_file(_dev, &dev_attr_bussuspend); + retval += device_create_file(_dev, &dev_attr_busconnected); + retval += device_create_file(_dev, &dev_attr_gotgctl); + retval += device_create_file(_dev, &dev_attr_gusbcfg); + retval += device_create_file(_dev, &dev_attr_grxfsiz); + retval += device_create_file(_dev, &dev_attr_gnptxfsiz); + retval += device_create_file(_dev, &dev_attr_gpvndctl); + retval += device_create_file(_dev, &dev_attr_ggpio); + retval += device_create_file(_dev, &dev_attr_guid); + retval += device_create_file(_dev, &dev_attr_gsnpsid); + retval += device_create_file(_dev, &dev_attr_devspeed); + retval += device_create_file(_dev, &dev_attr_enumspeed); + retval += device_create_file(_dev, &dev_attr_hptxfsiz); + retval += device_create_file(_dev, &dev_attr_hprt0); + retval += device_create_file(_dev, &dev_attr_remote_wakeup); + retval += device_create_file(_dev, &dev_attr_regdump); + retval += device_create_file(_dev, &dev_attr_hcddump); + retval += device_create_file(_dev, &dev_attr_hcd_frrem); + retval += device_create_file(_dev, &dev_attr_rd_reg_test); + retval += device_create_file(_dev, &dev_attr_wr_reg_test); + + if(retval != 0) + { + DWC_PRINT("cannot create sysfs device files.\n"); + // DWC_PRINT("killing own sysfs device files!\n"); + dwc_otg_attr_remove(_dev); + } +} + +/** + * Remove the device files + */ +void dwc_otg_attr_remove (struct device *_dev) +{ + device_remove_file(_dev, &dev_attr_regoffset); + device_remove_file(_dev, &dev_attr_regvalue); + device_remove_file(_dev, &dev_attr_mode); + device_remove_file(_dev, &dev_attr_hnpcapable); + device_remove_file(_dev, &dev_attr_srpcapable); + device_remove_file(_dev, &dev_attr_hnp); + device_remove_file(_dev, &dev_attr_srp); + device_remove_file(_dev, &dev_attr_buspower); + device_remove_file(_dev, &dev_attr_bussuspend); + device_remove_file(_dev, &dev_attr_busconnected); + device_remove_file(_dev, &dev_attr_gotgctl); + device_remove_file(_dev, &dev_attr_gusbcfg); + device_remove_file(_dev, &dev_attr_grxfsiz); + device_remove_file(_dev, &dev_attr_gnptxfsiz); + device_remove_file(_dev, &dev_attr_gpvndctl); + device_remove_file(_dev, &dev_attr_ggpio); + device_remove_file(_dev, &dev_attr_guid); + device_remove_file(_dev, &dev_attr_gsnpsid); + device_remove_file(_dev, &dev_attr_devspeed); + device_remove_file(_dev, &dev_attr_enumspeed); + device_remove_file(_dev, &dev_attr_hptxfsiz); + device_remove_file(_dev, &dev_attr_hprt0); + device_remove_file(_dev, &dev_attr_remote_wakeup); + device_remove_file(_dev, &dev_attr_regdump); + device_remove_file(_dev, &dev_attr_hcddump); + device_remove_file(_dev, &dev_attr_hcd_frrem); + device_remove_file(_dev, &dev_attr_rd_reg_test); + device_remove_file(_dev, &dev_attr_wr_reg_test); +} diff --git a/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_attr.h b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_attr.h new file mode 100644 index 0000000000..4bbf7df02d --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_attr.h @@ -0,0 +1,67 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_attr.h $ + * $Revision: 1.1.1.1 $ + * $Date: 2009-04-17 06:15:34 $ + * $Change: 510275 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ + +#if !defined(__DWC_OTG_ATTR_H__) +#define __DWC_OTG_ATTR_H__ + +/** @file + * This file contains the interface to the Linux device attributes. + */ +extern struct device_attribute dev_attr_regoffset; +extern struct device_attribute dev_attr_regvalue; + +extern struct device_attribute dev_attr_mode; +extern struct device_attribute dev_attr_hnpcapable; +extern struct device_attribute dev_attr_srpcapable; +extern struct device_attribute dev_attr_hnp; +extern struct device_attribute dev_attr_srp; +extern struct device_attribute dev_attr_buspower; +extern struct device_attribute dev_attr_bussuspend; +extern struct device_attribute dev_attr_busconnected; +extern struct device_attribute dev_attr_gotgctl; +extern struct device_attribute dev_attr_gusbcfg; +extern struct device_attribute dev_attr_grxfsiz; +extern struct device_attribute dev_attr_gnptxfsiz; +extern struct device_attribute dev_attr_gpvndctl; +extern struct device_attribute dev_attr_ggpio; +extern struct device_attribute dev_attr_guid; +extern struct device_attribute dev_attr_gsnpsid; +extern struct device_attribute dev_attr_devspeed; +extern struct device_attribute dev_attr_enumspeed; +extern struct device_attribute dev_attr_hptxfsiz; +extern struct device_attribute dev_attr_hprt0; + +void dwc_otg_attr_create (struct device *_dev); +void dwc_otg_attr_remove (struct device *_dev); + +#endif diff --git a/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil.c b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil.c new file mode 100644 index 0000000000..42c69eba48 --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil.c @@ -0,0 +1,3025 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil.c $ + * $Revision: 1.1.1.1 $ + * $Date: 2009-04-17 06:15:34 $ + * $Change: 631780 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ + +/** @file + * + * The Core Interface Layer provides basic services for accessing and + * managing the DWC_otg hardware. These services are used by both the + * Host Controller Driver and the Peripheral Controller Driver. + * + * The CIL manages the memory map for the core so that the HCD and PCD + * don't have to do this separately. It also handles basic tasks like + * reading/writing the registers and data FIFOs in the controller. + * Some of the data access functions provide encapsulation of several + * operations required to perform a task, such as writing multiple + * registers to start a transfer. Finally, the CIL performs basic + * services that are not specific to either the host or device modes + * of operation. These services include management of the OTG Host + * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A + * Diagnostic API is also provided to allow testing of the controller + * hardware. + * + * The Core Interface Layer has the following requirements: + * - Provides basic controller operations. + * - Minimal use of OS services. + * - The OS services used will be abstracted by using inline functions + * or macros. + * + */ +#include + +#ifdef DEBUG +#include +#endif + +#include "dwc_otg_plat.h" + +#include "dwc_otg_regs.h" +#include "dwc_otg_cil.h" + +/** + * This function is called to initialize the DWC_otg CSR data + * structures. The register addresses in the device and host + * structures are initialized from the base address supplied by the + * caller. The calling function must make the OS calls to get the + * base address of the DWC_otg controller registers. The core_params + * argument holds the parameters that specify how the core should be + * configured. + * + * @param[in] _reg_base_addr Base address of DWC_otg core registers + * @param[in] _core_params Pointer to the core configuration parameters + * + */ +dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr, + dwc_otg_core_params_t *_core_params) +{ + dwc_otg_core_if_t *core_if = 0; + dwc_otg_dev_if_t *dev_if = 0; + dwc_otg_host_if_t *host_if = 0; + uint8_t *reg_base = (uint8_t *)_reg_base_addr; + int i = 0; + + DWC_DEBUGPL(DBG_CILV, "%s(%p,%p)\n", __func__, _reg_base_addr, _core_params); + + core_if = kmalloc( sizeof(dwc_otg_core_if_t), GFP_KERNEL); + if (core_if == 0) { + DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_core_if_t failed\n"); + return 0; + } + memset(core_if, 0, sizeof(dwc_otg_core_if_t)); + + core_if->core_params = _core_params; + core_if->core_global_regs = (dwc_otg_core_global_regs_t *)reg_base; + /* + * Allocate the Device Mode structures. + */ + dev_if = kmalloc( sizeof(dwc_otg_dev_if_t), GFP_KERNEL); + if (dev_if == 0) { + DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n"); + kfree( core_if ); + return 0; + } + + dev_if->dev_global_regs = + (dwc_otg_device_global_regs_t *)(reg_base + DWC_DEV_GLOBAL_REG_OFFSET); + + for (i=0; iin_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *) + (reg_base + DWC_DEV_IN_EP_REG_OFFSET + + (i * DWC_EP_REG_OFFSET)); + + dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *) + (reg_base + DWC_DEV_OUT_EP_REG_OFFSET + + (i * DWC_EP_REG_OFFSET)); + DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n", + i, &dev_if->in_ep_regs[i]->diepctl); + DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n", + i, &dev_if->out_ep_regs[i]->doepctl); + } + dev_if->speed = 0; // unknown + //dev_if->num_eps = MAX_EPS_CHANNELS; + //dev_if->num_perio_eps = 0; + + core_if->dev_if = dev_if; + /* + * Allocate the Host Mode structures. + */ + host_if = kmalloc( sizeof(dwc_otg_host_if_t), GFP_KERNEL); + if (host_if == 0) { + DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_host_if_t failed\n"); + kfree( dev_if ); + kfree( core_if ); + return 0; + } + + host_if->host_global_regs = (dwc_otg_host_global_regs_t *) + (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET); + host_if->hprt0 = (uint32_t*)(reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET); + for (i=0; ihc_regs[i] = (dwc_otg_hc_regs_t *) + (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET + + (i * DWC_OTG_CHAN_REGS_OFFSET)); + DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n", + i, &host_if->hc_regs[i]->hcchar); + } + host_if->num_host_channels = MAX_EPS_CHANNELS; + core_if->host_if = host_if; + + for (i=0; idata_fifo[i] = + (uint32_t *)(reg_base + DWC_OTG_DATA_FIFO_OFFSET + + (i * DWC_OTG_DATA_FIFO_SIZE)); + DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n", + i, (unsigned)core_if->data_fifo[i]); + } // for loop. + + core_if->pcgcctl = (uint32_t*)(reg_base + DWC_OTG_PCGCCTL_OFFSET); + + /* + * Store the contents of the hardware configuration registers here for + * easy access later. + */ + core_if->hwcfg1.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg1); + core_if->hwcfg2.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg2); + core_if->hwcfg3.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg3); + core_if->hwcfg4.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg4); + + DWC_DEBUGPL(DBG_CILV,"hwcfg1=%08x\n",core_if->hwcfg1.d32); + DWC_DEBUGPL(DBG_CILV,"hwcfg2=%08x\n",core_if->hwcfg2.d32); + DWC_DEBUGPL(DBG_CILV,"hwcfg3=%08x\n",core_if->hwcfg3.d32); + DWC_DEBUGPL(DBG_CILV,"hwcfg4=%08x\n",core_if->hwcfg4.d32); + + + DWC_DEBUGPL(DBG_CILV,"op_mode=%0x\n",core_if->hwcfg2.b.op_mode); + DWC_DEBUGPL(DBG_CILV,"arch=%0x\n",core_if->hwcfg2.b.architecture); + DWC_DEBUGPL(DBG_CILV,"num_dev_ep=%d\n",core_if->hwcfg2.b.num_dev_ep); + DWC_DEBUGPL(DBG_CILV,"num_host_chan=%d\n",core_if->hwcfg2.b.num_host_chan); + DWC_DEBUGPL(DBG_CILV,"nonperio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.nonperio_tx_q_depth); + DWC_DEBUGPL(DBG_CILV,"host_perio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.host_perio_tx_q_depth); + DWC_DEBUGPL(DBG_CILV,"dev_token_q_depth=0x%0x\n",core_if->hwcfg2.b.dev_token_q_depth); + + DWC_DEBUGPL(DBG_CILV,"Total FIFO SZ=%d\n", core_if->hwcfg3.b.dfifo_depth); + DWC_DEBUGPL(DBG_CILV,"xfer_size_cntr_width=%0x\n", core_if->hwcfg3.b.xfer_size_cntr_width); + + /* + * Set the SRP sucess bit for FS-I2c + */ + core_if->srp_success = 0; + core_if->srp_timer_started = 0; + + return core_if; +} +/** + * This function frees the structures allocated by dwc_otg_cil_init(). + * + * @param[in] _core_if The core interface pointer returned from + * dwc_otg_cil_init(). + * + */ +void dwc_otg_cil_remove( dwc_otg_core_if_t *_core_if ) +{ + /* Disable all interrupts */ + dwc_modify_reg32( &_core_if->core_global_regs->gahbcfg, 1, 0); + dwc_write_reg32( &_core_if->core_global_regs->gintmsk, 0); + + if ( _core_if->dev_if ) { + kfree( _core_if->dev_if ); + } + if ( _core_if->host_if ) { + kfree( _core_if->host_if ); + } + kfree( _core_if ); +} + +/** + * This function enables the controller's Global Interrupt in the AHB Config + * register. + * + * @param[in] _core_if Programming view of DWC_otg controller. + */ +extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if ) +{ + gahbcfg_data_t ahbcfg = { .d32 = 0}; + ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ + dwc_modify_reg32(&_core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32); +} +/** + * This function disables the controller's Global Interrupt in the AHB Config + * register. + * + * @param[in] _core_if Programming view of DWC_otg controller. + */ +extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if ) +{ + gahbcfg_data_t ahbcfg = { .d32 = 0}; + ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ + dwc_modify_reg32(&_core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0); +} + +/** + * This function initializes the commmon interrupts, used in both + * device and host modes. + * + * @param[in] _core_if Programming view of the DWC_otg controller + * + */ +static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t *_core_if) +{ + dwc_otg_core_global_regs_t *global_regs = + _core_if->core_global_regs; + gintmsk_data_t intr_mask = { .d32 = 0}; + /* Clear any pending OTG Interrupts */ + dwc_write_reg32( &global_regs->gotgint, 0xFFFFFFFF); + /* Clear any pending interrupts */ + dwc_write_reg32( &global_regs->gintsts, 0xFFFFFFFF); + /* + * Enable the interrupts in the GINTMSK. + */ + intr_mask.b.modemismatch = 1; + intr_mask.b.otgintr = 1; + if (!_core_if->dma_enable) { + intr_mask.b.rxstsqlvl = 1; + } + intr_mask.b.conidstschng = 1; + intr_mask.b.wkupintr = 1; + intr_mask.b.disconnect = 1; + intr_mask.b.usbsuspend = 1; + intr_mask.b.sessreqintr = 1; + dwc_write_reg32( &global_regs->gintmsk, intr_mask.d32); +} + +/** + * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY + * type. + */ +static void init_fslspclksel(dwc_otg_core_if_t *_core_if) +{ + uint32_t val; + hcfg_data_t hcfg; + + if (((_core_if->hwcfg2.b.hs_phy_type == 2) && + (_core_if->hwcfg2.b.fs_phy_type == 1) && + (_core_if->core_params->ulpi_fs_ls)) || + (_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) + { + /* Full speed PHY */ + val = DWC_HCFG_48_MHZ; + } else { + /* High speed PHY running at full speed or high speed */ + val = DWC_HCFG_30_60_MHZ; + } + + DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val); + hcfg.d32 = dwc_read_reg32(&_core_if->host_if->host_global_regs->hcfg); + hcfg.b.fslspclksel = val; + dwc_write_reg32(&_core_if->host_if->host_global_regs->hcfg, hcfg.d32); +} + +/** + * Initializes the DevSpd field of the DCFG register depending on the PHY type + * and the enumeration speed of the device. + */ +static void init_devspd(dwc_otg_core_if_t *_core_if) +{ + uint32_t val; + dcfg_data_t dcfg; + + if (((_core_if->hwcfg2.b.hs_phy_type == 2) && + (_core_if->hwcfg2.b.fs_phy_type == 1) && + (_core_if->core_params->ulpi_fs_ls)) || + (_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) + { + /* Full speed PHY */ + val = 0x3; + } else if (_core_if->core_params->speed == DWC_SPEED_PARAM_FULL) { + /* High speed PHY running at full speed */ + val = 0x1; + } else { + /* High speed PHY running at high speed */ + val = 0x0; + } + + DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val); + dcfg.d32 = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->dcfg); + dcfg.b.devspd = val; + dwc_write_reg32(&_core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); +} + +/** + * This function calculates the number of IN EPS + * using GHWCFG1 and GHWCFG2 registers values + * + * @param _pcd the pcd structure. + */ +static uint32_t calc_num_in_eps(dwc_otg_core_if_t * _core_if) +{ + uint32_t num_in_eps = 0; + uint32_t num_eps = _core_if->hwcfg2.b.num_dev_ep; + uint32_t hwcfg1 = _core_if->hwcfg1.d32 >> 2; + uint32_t num_tx_fifos = _core_if->hwcfg4.b.num_in_eps; + int i; + for (i = 0; i < num_eps; ++i) { + if (!(hwcfg1 & 0x1)) + num_in_eps++; + hwcfg1 >>= 2; + } + if (_core_if->hwcfg4.b.ded_fifo_en) { + num_in_eps = (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps; + } + return num_in_eps; +} + + +/** + * This function calculates the number of OUT EPS + * using GHWCFG1 and GHWCFG2 registers values + * + * @param _pcd the pcd structure. + */ +static uint32_t calc_num_out_eps(dwc_otg_core_if_t * _core_if) +{ + uint32_t num_out_eps = 0; + uint32_t num_eps = _core_if->hwcfg2.b.num_dev_ep; + uint32_t hwcfg1 = _core_if->hwcfg1.d32 >> 2; + int i; + for (i = 0; i < num_eps; ++i) { + if (!(hwcfg1 & 0x2)) + num_out_eps++; + hwcfg1 >>= 2; + } + return num_out_eps; +} +/** + * This function initializes the DWC_otg controller registers and + * prepares the core for device mode or host mode operation. + * + * @param _core_if Programming view of the DWC_otg controller + * + */ +void dwc_otg_core_init(dwc_otg_core_if_t *_core_if) +{ + dwc_otg_core_global_regs_t * global_regs = _core_if->core_global_regs; + dwc_otg_dev_if_t *dev_if = _core_if->dev_if; + int i = 0; + gahbcfg_data_t ahbcfg = { .d32 = 0}; + gusbcfg_data_t usbcfg = { .d32 = 0 }; + gi2cctl_data_t i2cctl = {.d32 = 0}; + + DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n",_core_if); + + /* Common Initialization */ + + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); + DWC_DEBUGPL(DBG_CIL, "USB config register: 0x%08x\n", usbcfg.d32); + + /* Program the ULPI External VBUS bit if needed */ + //usbcfg.b.ulpi_ext_vbus_drv = 1; + //usbcfg.b.ulpi_ext_vbus_drv = 0; + usbcfg.b.ulpi_ext_vbus_drv = + (_core_if->core_params->phy_ulpi_ext_vbus == DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0; + + /* Set external TS Dline pulsing */ + usbcfg.b.term_sel_dl_pulse = (_core_if->core_params->ts_dline == 1) ? 1 : 0; + dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32); + + /* Reset the Controller */ + dwc_otg_core_reset( _core_if ); + + /* Initialize parameters from Hardware configuration registers. */ +#if 0 + dev_if->num_eps = _core_if->hwcfg2.b.num_dev_ep; + dev_if->num_perio_eps = _core_if->hwcfg4.b.num_dev_perio_in_ep; +#else + dev_if->num_in_eps = calc_num_in_eps(_core_if); + dev_if->num_out_eps = calc_num_out_eps(_core_if); +#endif + DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n", + _core_if->hwcfg4.b.num_dev_perio_in_ep); + DWC_DEBUGPL(DBG_CIL, "Is power optimization enabled? %s\n", + _core_if->hwcfg4.b.power_optimiz ? "Yes" : "No"); + DWC_DEBUGPL(DBG_CIL, "vbus_valid filter enabled? %s\n", + _core_if->hwcfg4.b.vbus_valid_filt_en ? "Yes" : "No"); + DWC_DEBUGPL(DBG_CIL, "iddig filter enabled? %s\n", + _core_if->hwcfg4.b.iddig_filt_en ? "Yes" : "No"); + + DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",_core_if->hwcfg4.b.num_dev_perio_in_ep); + for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++) { + dev_if->perio_tx_fifo_size[i] = + dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16; + DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n", i, + dev_if->perio_tx_fifo_size[i]); + } + for (i = 0; i < _core_if->hwcfg4.b.num_in_eps; i++) { + dev_if->tx_fifo_size[i] = + dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16; + DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n", i, + dev_if->perio_tx_fifo_size[i]); + } + + _core_if->total_fifo_size = _core_if->hwcfg3.b.dfifo_depth; + _core_if->rx_fifo_size = dwc_read_reg32(&global_regs->grxfsiz); + _core_if->nperio_tx_fifo_size = dwc_read_reg32(&global_regs->gnptxfsiz) >> 16; + + DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", _core_if->total_fifo_size); + DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", _core_if->rx_fifo_size); + DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n", _core_if->nperio_tx_fifo_size); + + /* This programming sequence needs to happen in FS mode before any other + * programming occurs */ + if ((_core_if->core_params->speed == DWC_SPEED_PARAM_FULL) && + (_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) { + /* If FS mode with FS PHY */ + + /* core_init() is now called on every switch so only call the + * following for the first time through. */ + if (!_core_if->phy_init_done) { + _core_if->phy_init_done = 1; + DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n"); + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); + usbcfg.b.physel = 1; + dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32); + + /* Reset after a PHY select */ + dwc_otg_core_reset( _core_if ); + } + + /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also + * do this on HNP Dev/Host mode switches (done in dev_init and + * host_init). */ + if (dwc_otg_is_host_mode(_core_if)) { + DWC_DEBUGPL(DBG_CIL, "host mode\n"); + init_fslspclksel(_core_if); + } else { + DWC_DEBUGPL(DBG_CIL, "device mode\n"); + init_devspd(_core_if); + } + + if (_core_if->core_params->i2c_enable) { + DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n"); + /* Program GUSBCFG.OtgUtmifsSel to I2C */ + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); + usbcfg.b.otgutmifssel = 1; + dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32); + + /* Program GI2CCTL.I2CEn */ + i2cctl.d32 = dwc_read_reg32(&global_regs->gi2cctl); + i2cctl.b.i2cdevaddr = 1; + i2cctl.b.i2cen = 0; + dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32); + i2cctl.b.i2cen = 1; + dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32); + } + + } /* endif speed == DWC_SPEED_PARAM_FULL */ + else { + /* High speed PHY. */ + if (!_core_if->phy_init_done) { + _core_if->phy_init_done = 1; + DWC_DEBUGPL(DBG_CIL, "High spped PHY\n"); + /* HS PHY parameters. These parameters are preserved + * during soft reset so only program the first time. Do + * a soft reset immediately after setting phyif. */ + usbcfg.b.ulpi_utmi_sel = _core_if->core_params->phy_type; + if (usbcfg.b.ulpi_utmi_sel == 2) { // winder + DWC_DEBUGPL(DBG_CIL, "ULPI\n"); + /* ULPI interface */ + usbcfg.b.phyif = 0; + usbcfg.b.ddrsel = _core_if->core_params->phy_ulpi_ddr; + } else { + /* UTMI+ interface */ + if (_core_if->core_params->phy_utmi_width == 16) { + usbcfg.b.phyif = 1; + DWC_DEBUGPL(DBG_CIL, "UTMI+ 16\n"); + } else { + DWC_DEBUGPL(DBG_CIL, "UTMI+ 8\n"); + usbcfg.b.phyif = 0; + } + } + dwc_write_reg32( &global_regs->gusbcfg, usbcfg.d32); + + /* Reset after setting the PHY parameters */ + dwc_otg_core_reset( _core_if ); + } + } + + if ((_core_if->hwcfg2.b.hs_phy_type == 2) && + (_core_if->hwcfg2.b.fs_phy_type == 1) && + (_core_if->core_params->ulpi_fs_ls)) + { + DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n"); + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); + usbcfg.b.ulpi_fsls = 1; + usbcfg.b.ulpi_clk_sus_m = 1; + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); + } else { + DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS=0\n"); + usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); + usbcfg.b.ulpi_fsls = 0; + usbcfg.b.ulpi_clk_sus_m = 0; + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); + } + + /* Program the GAHBCFG Register.*/ + switch (_core_if->hwcfg2.b.architecture){ + + case DWC_SLAVE_ONLY_ARCH: + DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n"); + ahbcfg.b.nptxfemplvl_txfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY; + ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY; + _core_if->dma_enable = 0; + break; + + case DWC_EXT_DMA_ARCH: + DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n"); + ahbcfg.b.hburstlen = _core_if->core_params->dma_burst_size; + _core_if->dma_enable = (_core_if->core_params->dma_enable != 0); + break; + + case DWC_INT_DMA_ARCH: + DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n"); + //ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR; + ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR4; + _core_if->dma_enable = (_core_if->core_params->dma_enable != 0); + break; + } + ahbcfg.b.dmaenable = _core_if->dma_enable; + dwc_write_reg32(&global_regs->gahbcfg, ahbcfg.d32); + _core_if->en_multiple_tx_fifo = _core_if->hwcfg4.b.ded_fifo_en; + + /* + * Program the GUSBCFG register. + */ + usbcfg.d32 = dwc_read_reg32( &global_regs->gusbcfg ); + + switch (_core_if->hwcfg2.b.op_mode) { + case DWC_MODE_HNP_SRP_CAPABLE: + usbcfg.b.hnpcap = (_core_if->core_params->otg_cap == + DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE); + usbcfg.b.srpcap = (_core_if->core_params->otg_cap != + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); + break; + + case DWC_MODE_SRP_ONLY_CAPABLE: + usbcfg.b.hnpcap = 0; + usbcfg.b.srpcap = (_core_if->core_params->otg_cap != + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); + break; + + case DWC_MODE_NO_HNP_SRP_CAPABLE: + usbcfg.b.hnpcap = 0; + usbcfg.b.srpcap = 0; + break; + + case DWC_MODE_SRP_CAPABLE_DEVICE: + usbcfg.b.hnpcap = 0; + usbcfg.b.srpcap = (_core_if->core_params->otg_cap != + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); + break; + + case DWC_MODE_NO_SRP_CAPABLE_DEVICE: + usbcfg.b.hnpcap = 0; + usbcfg.b.srpcap = 0; + break; + + case DWC_MODE_SRP_CAPABLE_HOST: + usbcfg.b.hnpcap = 0; + usbcfg.b.srpcap = (_core_if->core_params->otg_cap != + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); + break; + + case DWC_MODE_NO_SRP_CAPABLE_HOST: + usbcfg.b.hnpcap = 0; + usbcfg.b.srpcap = 0; + break; + } + + dwc_write_reg32( &global_regs->gusbcfg, usbcfg.d32); + + /* Enable common interrupts */ + dwc_otg_enable_common_interrupts( _core_if ); + + /* Do device or host intialization based on mode during PCD + * and HCD initialization */ + if (dwc_otg_is_host_mode( _core_if )) { + DWC_DEBUGPL(DBG_ANY, "Host Mode\n" ); + _core_if->op_state = A_HOST; + } else { + DWC_DEBUGPL(DBG_ANY, "Device Mode\n" ); + _core_if->op_state = B_PERIPHERAL; +#ifdef DWC_DEVICE_ONLY + dwc_otg_core_dev_init( _core_if ); +#endif + } +} + + +/** + * This function enables the Device mode interrupts. + * + * @param _core_if Programming view of DWC_otg controller + */ +void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if) +{ + gintmsk_data_t intr_mask = { .d32 = 0}; + dwc_otg_core_global_regs_t * global_regs = _core_if->core_global_regs; + + DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__); + + /* Disable all interrupts. */ + dwc_write_reg32( &global_regs->gintmsk, 0); + + /* Clear any pending interrupts */ + dwc_write_reg32( &global_regs->gintsts, 0xFFFFFFFF); + + /* Enable the common interrupts */ + dwc_otg_enable_common_interrupts( _core_if ); + + /* Enable interrupts */ + intr_mask.b.usbreset = 1; + intr_mask.b.enumdone = 1; + //intr_mask.b.epmismatch = 1; + intr_mask.b.inepintr = 1; + intr_mask.b.outepintr = 1; + intr_mask.b.erlysuspend = 1; + if (_core_if->en_multiple_tx_fifo == 0) { + intr_mask.b.epmismatch = 1; + } + + /** @todo NGS: Should this be a module parameter? */ + intr_mask.b.isooutdrop = 1; + intr_mask.b.eopframe = 1; + intr_mask.b.incomplisoin = 1; + intr_mask.b.incomplisoout = 1; + + dwc_modify_reg32( &global_regs->gintmsk, intr_mask.d32, intr_mask.d32); + + DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, + dwc_read_reg32( &global_regs->gintmsk)); +} + +/** + * This function initializes the DWC_otg controller registers for + * device mode. + * + * @param _core_if Programming view of DWC_otg controller + * + */ +void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if) +{ + dwc_otg_core_global_regs_t *global_regs = + _core_if->core_global_regs; + dwc_otg_dev_if_t *dev_if = _core_if->dev_if; + dwc_otg_core_params_t *params = _core_if->core_params; + dcfg_data_t dcfg = {.d32 = 0}; + grstctl_t resetctl = { .d32=0 }; + int i; + uint32_t rx_fifo_size; + fifosize_data_t nptxfifosize; + fifosize_data_t txfifosize; + dthrctl_data_t dthrctl; + + fifosize_data_t ptxfifosize; + + /* Restart the Phy Clock */ + dwc_write_reg32(_core_if->pcgcctl, 0); + + /* Device configuration register */ + init_devspd(_core_if); + dcfg.d32 = dwc_read_reg32( &dev_if->dev_global_regs->dcfg); + dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80; + dwc_write_reg32( &dev_if->dev_global_regs->dcfg, dcfg.d32 ); + + /* Configure data FIFO sizes */ + if ( _core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo ) { + + DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", _core_if->total_fifo_size); + DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", params->dev_rx_fifo_size); + DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", params->dev_nperio_tx_fifo_size); + + /* Rx FIFO */ + DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n", + dwc_read_reg32(&global_regs->grxfsiz)); + rx_fifo_size = params->dev_rx_fifo_size; + dwc_write_reg32( &global_regs->grxfsiz, rx_fifo_size ); + DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n", + dwc_read_reg32(&global_regs->grxfsiz)); + + /** Set Periodic Tx FIFO Mask all bits 0 */ + _core_if->p_tx_msk = 0; + + /** Set Tx FIFO Mask all bits 0 */ + _core_if->tx_msk = 0; + if (_core_if->en_multiple_tx_fifo == 0) { + /* Non-periodic Tx FIFO */ + DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", + dwc_read_reg32(&global_regs->gnptxfsiz)); + nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; + nptxfifosize.b.startaddr = params->dev_rx_fifo_size; + dwc_write_reg32( &global_regs->gnptxfsiz, nptxfifosize.d32 ); + DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", + dwc_read_reg32(&global_regs->gnptxfsiz)); + + + /**@todo NGS: Fix Periodic FIFO Sizing! */ + /* + * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15. + * Indexes of the FIFO size module parameters in the + * dev_perio_tx_fifo_size array and the FIFO size registers in + * the dptxfsiz array run from 0 to 14. + */ + /** @todo Finish debug of this */ + ptxfifosize.b.startaddr = + nptxfifosize.b.startaddr + nptxfifosize.b.depth; + for (i = 0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep;i++) { + ptxfifosize.b.depth = params->dev_perio_tx_fifo_size[i]; + DWC_DEBUGPL(DBG_CIL,"initial dptxfsiz_dieptxf[%d]=%08x\n", + i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i])); + dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i],ptxfifosize.d32); + DWC_DEBUGPL(DBG_CIL,"new dptxfsiz_dieptxf[%d]=%08x\n", + i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i])); + ptxfifosize.b.startaddr += ptxfifosize.b.depth; + } + } else { + + /* + * Tx FIFOs These FIFOs are numbered from 1 to 15. + * Indexes of the FIFO size module parameters in the + * dev_tx_fifo_size array and the FIFO size registers in + * the dptxfsiz_dieptxf array run from 0 to 14. + */ + + /* Non-periodic Tx FIFO */ + DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", + dwc_read_reg32(&global_regs->gnptxfsiz)); + nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; + nptxfifosize.b.startaddr = params->dev_rx_fifo_size; + dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32); + DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", + dwc_read_reg32(&global_regs->gnptxfsiz)); + txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; + for (i = 1;i < _core_if->hwcfg4.b.num_dev_perio_in_ep;i++) { + txfifosize.b.depth = params->dev_tx_fifo_size[i]; + DWC_DEBUGPL(DBG_CIL,"initial dptxfsiz_dieptxf[%d]=%08x\n", + i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i])); + dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i - 1],txfifosize.d32); + DWC_DEBUGPL(DBG_CIL,"new dptxfsiz_dieptxf[%d]=%08x\n", + i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i-1])); + txfifosize.b.startaddr += txfifosize.b.depth; + } + } + } + /* Flush the FIFOs */ + dwc_otg_flush_tx_fifo(_core_if, 0x10); /* all Tx FIFOs */ + dwc_otg_flush_rx_fifo(_core_if); + + /* Flush the Learning Queue. */ + resetctl.b.intknqflsh = 1; + dwc_write_reg32( &_core_if->core_global_regs->grstctl, resetctl.d32); + + /* Clear all pending Device Interrupts */ + dwc_write_reg32( &dev_if->dev_global_regs->diepmsk, 0 ); + dwc_write_reg32( &dev_if->dev_global_regs->doepmsk, 0 ); + dwc_write_reg32( &dev_if->dev_global_regs->daint, 0xFFFFFFFF ); + dwc_write_reg32( &dev_if->dev_global_regs->daintmsk, 0 ); + + for (i = 0; i <= dev_if->num_in_eps; i++) { + depctl_data_t depctl; + depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl); + if (depctl.b.epena) { + depctl.d32 = 0; + depctl.b.epdis = 1; + depctl.b.snak = 1; + } else { + depctl.d32 = 0; + } + dwc_write_reg32( &dev_if->in_ep_regs[i]->diepctl, depctl.d32); + + dwc_write_reg32(&dev_if->in_ep_regs[i]->dieptsiz, 0); + dwc_write_reg32(&dev_if->in_ep_regs[i]->diepdma, 0); + dwc_write_reg32(&dev_if->in_ep_regs[i]->diepint, 0xFF); + } + for (i = 0; i <= dev_if->num_out_eps; i++) { + depctl_data_t depctl; + depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl); + if (depctl.b.epena) { + depctl.d32 = 0; + depctl.b.epdis = 1; + depctl.b.snak = 1; + } else { + depctl.d32 = 0; + } + dwc_write_reg32( &dev_if->out_ep_regs[i]->doepctl, depctl.d32); + + //dwc_write_reg32( &dev_if->in_ep_regs[i]->dieptsiz, 0); + dwc_write_reg32( &dev_if->out_ep_regs[i]->doeptsiz, 0); + //dwc_write_reg32( &dev_if->in_ep_regs[i]->diepdma, 0); + dwc_write_reg32( &dev_if->out_ep_regs[i]->doepdma, 0); + //dwc_write_reg32( &dev_if->in_ep_regs[i]->diepint, 0xFF); + dwc_write_reg32( &dev_if->out_ep_regs[i]->doepint, 0xFF); + } + + if (_core_if->en_multiple_tx_fifo && _core_if->dma_enable) { + dev_if->non_iso_tx_thr_en = _core_if->core_params->thr_ctl & 0x1; + dev_if->iso_tx_thr_en = (_core_if->core_params->thr_ctl >> 1) & 0x1; + dev_if->rx_thr_en = (_core_if->core_params->thr_ctl >> 2) & 0x1; + dev_if->rx_thr_length = _core_if->core_params->rx_thr_length; + dev_if->tx_thr_length = _core_if->core_params->tx_thr_length; + dthrctl.d32 = 0; + dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en; + dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en; + dthrctl.b.tx_thr_len = dev_if->tx_thr_length; + dthrctl.b.rx_thr_en = dev_if->rx_thr_en; + dthrctl.b.rx_thr_len = dev_if->rx_thr_length; + dwc_write_reg32(&dev_if->dev_global_regs->dtknqr3_dthrctl,dthrctl.d32); + DWC_DEBUGPL(DBG_CIL, "Non ISO Tx Thr - %d\nISO Tx Thr - %d\n" + "Rx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n", + dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en, + dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len, + dthrctl.b.rx_thr_len); + } + dwc_otg_enable_device_interrupts( _core_if ); + { + diepmsk_data_t msk = {.d32 = 0}; + msk.b.txfifoundrn = 1; + dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk, msk.d32,msk.d32); +} +} + +/** + * This function enables the Host mode interrupts. + * + * @param _core_if Programming view of DWC_otg controller + */ +void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if) +{ + dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs; + gintmsk_data_t intr_mask = {.d32 = 0}; + + DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__); + + /* Disable all interrupts. */ + dwc_write_reg32(&global_regs->gintmsk, 0); + + /* Clear any pending interrupts. */ + dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF); + + /* Enable the common interrupts */ + dwc_otg_enable_common_interrupts(_core_if); + + /* + * Enable host mode interrupts without disturbing common + * interrupts. + */ + intr_mask.b.sofintr = 1; + intr_mask.b.portintr = 1; + intr_mask.b.hcintr = 1; + + //dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); + //dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32); + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); +} + +/** + * This function disables the Host Mode interrupts. + * + * @param _core_if Programming view of DWC_otg controller + */ +void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if) +{ + dwc_otg_core_global_regs_t *global_regs = + _core_if->core_global_regs; + gintmsk_data_t intr_mask = {.d32 = 0}; + + DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__); + + /* + * Disable host mode interrupts without disturbing common + * interrupts. + */ + intr_mask.b.sofintr = 1; + intr_mask.b.portintr = 1; + intr_mask.b.hcintr = 1; + intr_mask.b.ptxfempty = 1; + intr_mask.b.nptxfempty = 1; + + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0); +} + +#if 0 +/* currently not used, keep it here as if needed later */ +static int phy_read(dwc_otg_core_if_t * _core_if, int addr) +{ + u32 val; + int timeout = 10; + + dwc_write_reg32(&_core_if->core_global_regs->gpvndctl, + 0x02000000 | (addr << 16)); + val = dwc_read_reg32(&_core_if->core_global_regs->gpvndctl); + while (((val & 0x08000000) == 0) && (timeout--)) { + udelay(1000); + val = dwc_read_reg32(&_core_if->core_global_regs->gpvndctl); + } + val = dwc_read_reg32(&_core_if->core_global_regs->gpvndctl); + printk("%s: addr=%02x regval=%02x\n", __func__, addr, val & 0x000000ff); + + return 0; +} +#endif + +/** + * This function initializes the DWC_otg controller registers for + * host mode. + * + * This function flushes the Tx and Rx FIFOs and it flushes any entries in the + * request queues. Host channels are reset to ensure that they are ready for + * performing transfers. + * + * @param _core_if Programming view of DWC_otg controller + * + */ +void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if) +{ + dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs; + dwc_otg_host_if_t *host_if = _core_if->host_if; + dwc_otg_core_params_t *params = _core_if->core_params; + hprt0_data_t hprt0 = {.d32 = 0}; + fifosize_data_t nptxfifosize; + fifosize_data_t ptxfifosize; + int i; + hcchar_data_t hcchar; + hcfg_data_t hcfg; + dwc_otg_hc_regs_t *hc_regs; + int num_channels; + gotgctl_data_t gotgctl = {.d32 = 0}; + + DWC_DEBUGPL(DBG_CILV,"%s(%p)\n", __func__, _core_if); + + /* Restart the Phy Clock */ + dwc_write_reg32(_core_if->pcgcctl, 0); + + /* Initialize Host Configuration Register */ + init_fslspclksel(_core_if); + if (_core_if->core_params->speed == DWC_SPEED_PARAM_FULL) { + hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg); + hcfg.b.fslssupp = 1; + dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32); + } + + /* Configure data FIFO sizes */ + if (_core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { + DWC_DEBUGPL(DBG_CIL,"Total FIFO Size=%d\n", _core_if->total_fifo_size); + DWC_DEBUGPL(DBG_CIL,"Rx FIFO Size=%d\n", params->host_rx_fifo_size); + DWC_DEBUGPL(DBG_CIL,"NP Tx FIFO Size=%d\n", params->host_nperio_tx_fifo_size); + DWC_DEBUGPL(DBG_CIL,"P Tx FIFO Size=%d\n", params->host_perio_tx_fifo_size); + + /* Rx FIFO */ + DWC_DEBUGPL(DBG_CIL,"initial grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz)); + dwc_write_reg32(&global_regs->grxfsiz, params->host_rx_fifo_size); + DWC_DEBUGPL(DBG_CIL,"new grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz)); + + /* Non-periodic Tx FIFO */ + DWC_DEBUGPL(DBG_CIL,"initial gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz)); + nptxfifosize.b.depth = params->host_nperio_tx_fifo_size; + nptxfifosize.b.startaddr = params->host_rx_fifo_size; + dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32); + DWC_DEBUGPL(DBG_CIL,"new gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz)); + + /* Periodic Tx FIFO */ + DWC_DEBUGPL(DBG_CIL,"initial hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz)); + ptxfifosize.b.depth = params->host_perio_tx_fifo_size; + ptxfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; + dwc_write_reg32(&global_regs->hptxfsiz, ptxfifosize.d32); + DWC_DEBUGPL(DBG_CIL,"new hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz)); + } + + /* Clear Host Set HNP Enable in the OTG Control Register */ + gotgctl.b.hstsethnpen = 1; + dwc_modify_reg32( &global_regs->gotgctl, gotgctl.d32, 0); + + /* Make sure the FIFOs are flushed. */ + dwc_otg_flush_tx_fifo(_core_if, 0x10 /* all Tx FIFOs */); + dwc_otg_flush_rx_fifo(_core_if); + + /* Flush out any leftover queued requests. */ + num_channels = _core_if->core_params->host_channels; + for (i = 0; i < num_channels; i++) { + hc_regs = _core_if->host_if->hc_regs[i]; + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hcchar.b.chen = 0; + hcchar.b.chdis = 1; + hcchar.b.epdir = 0; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + } + + /* Halt all channels to put them into a known state. */ + for (i = 0; i < num_channels; i++) { + int count = 0; + hc_regs = _core_if->host_if->hc_regs[i]; + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hcchar.b.chen = 1; + hcchar.b.chdis = 1; + hcchar.b.epdir = 0; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i); + do { + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + if (++count > 200) { + DWC_ERROR("%s: Unable to clear halt on channel %d\n", + __func__, i); + break; + } + udelay(100); + } while (hcchar.b.chen); + } + + /* Turn on the vbus power. */ + DWC_PRINT("Init: Port Power? op_state=%d\n", _core_if->op_state); + if (_core_if->op_state == A_HOST){ + hprt0.d32 = dwc_otg_read_hprt0(_core_if); + DWC_PRINT("Init: Power Port (%d)\n", hprt0.b.prtpwr); + if (hprt0.b.prtpwr == 0 ) { + hprt0.b.prtpwr = 1; + dwc_write_reg32(host_if->hprt0, hprt0.d32); + } + } + + dwc_otg_enable_host_interrupts( _core_if ); +} + +/** + * Prepares a host channel for transferring packets to/from a specific + * endpoint. The HCCHARn register is set up with the characteristics specified + * in _hc. Host channel interrupts that may need to be serviced while this + * transfer is in progress are enabled. + * + * @param _core_if Programming view of DWC_otg controller + * @param _hc Information needed to initialize the host channel + */ +void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) +{ + uint32_t intr_enable; + hcintmsk_data_t hc_intr_mask; + gintmsk_data_t gintmsk = {.d32 = 0}; + hcchar_data_t hcchar; + hcsplt_data_t hcsplt; + + uint8_t hc_num = _hc->hc_num; + dwc_otg_host_if_t *host_if = _core_if->host_if; + dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num]; + + /* Clear old interrupt conditions for this host channel. */ + hc_intr_mask.d32 = 0xFFFFFFFF; + hc_intr_mask.b.reserved = 0; + dwc_write_reg32(&hc_regs->hcint, hc_intr_mask.d32); + + /* Enable channel interrupts required for this transfer. */ + hc_intr_mask.d32 = 0; + hc_intr_mask.b.chhltd = 1; + if (_core_if->dma_enable) { + hc_intr_mask.b.ahberr = 1; + if (_hc->error_state && !_hc->do_split && + _hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { + hc_intr_mask.b.ack = 1; + if (_hc->ep_is_in) { + hc_intr_mask.b.datatglerr = 1; + if (_hc->ep_type != DWC_OTG_EP_TYPE_INTR) { + hc_intr_mask.b.nak = 1; + } + } + } + } else { + switch (_hc->ep_type) { + case DWC_OTG_EP_TYPE_CONTROL: + case DWC_OTG_EP_TYPE_BULK: + hc_intr_mask.b.xfercompl = 1; + hc_intr_mask.b.stall = 1; + hc_intr_mask.b.xacterr = 1; + hc_intr_mask.b.datatglerr = 1; + if (_hc->ep_is_in) { + hc_intr_mask.b.bblerr = 1; + } else { + hc_intr_mask.b.nak = 1; + hc_intr_mask.b.nyet = 1; + if (_hc->do_ping) { + hc_intr_mask.b.ack = 1; + } + } + + if (_hc->do_split) { + hc_intr_mask.b.nak = 1; + if (_hc->complete_split) { + hc_intr_mask.b.nyet = 1; + } + else { + hc_intr_mask.b.ack = 1; + } + } + + if (_hc->error_state) { + hc_intr_mask.b.ack = 1; + } + break; + case DWC_OTG_EP_TYPE_INTR: + hc_intr_mask.b.xfercompl = 1; + hc_intr_mask.b.nak = 1; + hc_intr_mask.b.stall = 1; + hc_intr_mask.b.xacterr = 1; + hc_intr_mask.b.datatglerr = 1; + hc_intr_mask.b.frmovrun = 1; + + if (_hc->ep_is_in) { + hc_intr_mask.b.bblerr = 1; + } + if (_hc->error_state) { + hc_intr_mask.b.ack = 1; + } + if (_hc->do_split) { + if (_hc->complete_split) { + hc_intr_mask.b.nyet = 1; + } + else { + hc_intr_mask.b.ack = 1; + } + } + break; + case DWC_OTG_EP_TYPE_ISOC: + hc_intr_mask.b.xfercompl = 1; + hc_intr_mask.b.frmovrun = 1; + hc_intr_mask.b.ack = 1; + + if (_hc->ep_is_in) { + hc_intr_mask.b.xacterr = 1; + hc_intr_mask.b.bblerr = 1; + } + break; + } + } + dwc_write_reg32(&hc_regs->hcintmsk, hc_intr_mask.d32); + + /* Enable the top level host channel interrupt. */ + intr_enable = (1 << hc_num); + dwc_modify_reg32(&host_if->host_global_regs->haintmsk, 0, intr_enable); + + /* Make sure host channel interrupts are enabled. */ + gintmsk.b.hcintr = 1; + dwc_modify_reg32(&_core_if->core_global_regs->gintmsk, 0, gintmsk.d32); + + /* + * Program the HCCHARn register with the endpoint characteristics for + * the current transfer. + */ + hcchar.d32 = 0; + hcchar.b.devaddr = _hc->dev_addr; + hcchar.b.epnum = _hc->ep_num; + hcchar.b.epdir = _hc->ep_is_in; + hcchar.b.lspddev = (_hc->speed == DWC_OTG_EP_SPEED_LOW); + hcchar.b.eptype = _hc->ep_type; + hcchar.b.mps = _hc->max_packet; + + dwc_write_reg32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32); + + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num); + DWC_DEBUGPL(DBG_HCDV, " Dev Addr: %d\n", hcchar.b.devaddr); + DWC_DEBUGPL(DBG_HCDV, " Ep Num: %d\n", hcchar.b.epnum); + DWC_DEBUGPL(DBG_HCDV, " Is In: %d\n", hcchar.b.epdir); + DWC_DEBUGPL(DBG_HCDV, " Is Low Speed: %d\n", hcchar.b.lspddev); + DWC_DEBUGPL(DBG_HCDV, " Ep Type: %d\n", hcchar.b.eptype); + DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps); + DWC_DEBUGPL(DBG_HCDV, " Multi Cnt: %d\n", hcchar.b.multicnt); + + /* + * Program the HCSPLIT register for SPLITs + */ + hcsplt.d32 = 0; + if (_hc->do_split) { + DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n", _hc->hc_num, + _hc->complete_split ? "CSPLIT" : "SSPLIT"); + hcsplt.b.compsplt = _hc->complete_split; + hcsplt.b.xactpos = _hc->xact_pos; + hcsplt.b.hubaddr = _hc->hub_addr; + hcsplt.b.prtaddr = _hc->port_addr; + DWC_DEBUGPL(DBG_HCDV, " comp split %d\n", _hc->complete_split); + DWC_DEBUGPL(DBG_HCDV, " xact pos %d\n", _hc->xact_pos); + DWC_DEBUGPL(DBG_HCDV, " hub addr %d\n", _hc->hub_addr); + DWC_DEBUGPL(DBG_HCDV, " port addr %d\n", _hc->port_addr); + DWC_DEBUGPL(DBG_HCDV, " is_in %d\n", _hc->ep_is_in); + DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps); + DWC_DEBUGPL(DBG_HCDV, " xferlen: %d\n", _hc->xfer_len); + } + dwc_write_reg32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32); + +} + +/** + * Attempts to halt a host channel. This function should only be called in + * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under + * normal circumstances in DMA mode, the controller halts the channel when the + * transfer is complete or a condition occurs that requires application + * intervention. + * + * In slave mode, checks for a free request queue entry, then sets the Channel + * Enable and Channel Disable bits of the Host Channel Characteristics + * register of the specified channel to intiate the halt. If there is no free + * request queue entry, sets only the Channel Disable bit of the HCCHARn + * register to flush requests for this channel. In the latter case, sets a + * flag to indicate that the host channel needs to be halted when a request + * queue slot is open. + * + * In DMA mode, always sets the Channel Enable and Channel Disable bits of the + * HCCHARn register. The controller ensures there is space in the request + * queue before submitting the halt request. + * + * Some time may elapse before the core flushes any posted requests for this + * host channel and halts. The Channel Halted interrupt handler completes the + * deactivation of the host channel. + * + * @param _core_if Controller register interface. + * @param _hc Host channel to halt. + * @param _halt_status Reason for halting the channel. + */ +void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if, + dwc_hc_t *_hc, + dwc_otg_halt_status_e _halt_status) +{ + gnptxsts_data_t nptxsts; + hptxsts_data_t hptxsts; + hcchar_data_t hcchar; + dwc_otg_hc_regs_t *hc_regs; + dwc_otg_core_global_regs_t *global_regs; + dwc_otg_host_global_regs_t *host_global_regs; + + hc_regs = _core_if->host_if->hc_regs[_hc->hc_num]; + global_regs = _core_if->core_global_regs; + host_global_regs = _core_if->host_if->host_global_regs; + + WARN_ON(_halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS); + + if (_halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE || + _halt_status == DWC_OTG_HC_XFER_AHB_ERR) { + /* + * Disable all channel interrupts except Ch Halted. The QTD + * and QH state associated with this transfer has been cleared + * (in the case of URB_DEQUEUE), so the channel needs to be + * shut down carefully to prevent crashes. + */ + hcintmsk_data_t hcintmsk; + hcintmsk.d32 = 0; + hcintmsk.b.chhltd = 1; + dwc_write_reg32(&hc_regs->hcintmsk, hcintmsk.d32); + + /* + * Make sure no other interrupts besides halt are currently + * pending. Handling another interrupt could cause a crash due + * to the QTD and QH state. + */ + dwc_write_reg32(&hc_regs->hcint, ~hcintmsk.d32); + + /* + * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR + * even if the channel was already halted for some other + * reason. + */ + _hc->halt_status = _halt_status; + + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + if (hcchar.b.chen == 0) { + /* + * The channel is either already halted or it hasn't + * started yet. In DMA mode, the transfer may halt if + * it finishes normally or a condition occurs that + * requires driver intervention. Don't want to halt + * the channel again. In either Slave or DMA mode, + * it's possible that the transfer has been assigned + * to a channel, but not started yet when an URB is + * dequeued. Don't want to halt a channel that hasn't + * started yet. + */ + return; + } + } + + if (_hc->halt_pending) { + /* + * A halt has already been issued for this channel. This might + * happen when a transfer is aborted by a higher level in + * the stack. + */ +#ifdef DEBUG + DWC_PRINT("*** %s: Channel %d, _hc->halt_pending already set ***\n", + __func__, _hc->hc_num); + +/* dwc_otg_dump_global_registers(_core_if); */ +/* dwc_otg_dump_host_registers(_core_if); */ +#endif + return; + } + + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hcchar.b.chen = 1; + hcchar.b.chdis = 1; + + if (!_core_if->dma_enable) { + /* Check for space in the request queue to issue the halt. */ + if (_hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || + _hc->ep_type == DWC_OTG_EP_TYPE_BULK) { + nptxsts.d32 = dwc_read_reg32(&global_regs->gnptxsts); + if (nptxsts.b.nptxqspcavail == 0) { + hcchar.b.chen = 0; + } + } else { + hptxsts.d32 = dwc_read_reg32(&host_global_regs->hptxsts); + if ((hptxsts.b.ptxqspcavail == 0) || (_core_if->queuing_high_bandwidth)) { + hcchar.b.chen = 0; + } + } + } + + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + + _hc->halt_status = _halt_status; + + if (hcchar.b.chen) { + _hc->halt_pending = 1; + _hc->halt_on_queue = 0; + } else { + _hc->halt_on_queue = 1; + } + + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num); + DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32); + DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", _hc->halt_pending); + DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", _hc->halt_on_queue); + DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", _hc->halt_status); + + return; +} + +/** + * Clears the transfer state for a host channel. This function is normally + * called after a transfer is done and the host channel is being released. + * + * @param _core_if Programming view of DWC_otg controller. + * @param _hc Identifies the host channel to clean up. + */ +void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) +{ + dwc_otg_hc_regs_t *hc_regs; + + _hc->xfer_started = 0; + + /* + * Clear channel interrupt enables and any unhandled channel interrupt + * conditions. + */ + hc_regs = _core_if->host_if->hc_regs[_hc->hc_num]; + dwc_write_reg32(&hc_regs->hcintmsk, 0); + dwc_write_reg32(&hc_regs->hcint, 0xFFFFFFFF); + +#ifdef DEBUG + del_timer(&_core_if->hc_xfer_timer[_hc->hc_num]); + { + hcchar_data_t hcchar; + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + if (hcchar.b.chdis) { + DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", + __func__, _hc->hc_num, hcchar.d32); + } + } +#endif +} + +/** + * Sets the channel property that indicates in which frame a periodic transfer + * should occur. This is always set to the _next_ frame. This function has no + * effect on non-periodic transfers. + * + * @param _core_if Programming view of DWC_otg controller. + * @param _hc Identifies the host channel to set up and its properties. + * @param _hcchar Current value of the HCCHAR register for the specified host + * channel. + */ +static inline void hc_set_even_odd_frame(dwc_otg_core_if_t *_core_if, + dwc_hc_t *_hc, + hcchar_data_t *_hcchar) +{ + if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR || + _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { + hfnum_data_t hfnum; + hfnum.d32 = dwc_read_reg32(&_core_if->host_if->host_global_regs->hfnum); + /* 1 if _next_ frame is odd, 0 if it's even */ + _hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1; +#ifdef DEBUG + if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR && _hc->do_split && !_hc->complete_split) { + switch (hfnum.b.frnum & 0x7) { + case 7: + _core_if->hfnum_7_samples++; + _core_if->hfnum_7_frrem_accum += hfnum.b.frrem; + break; + case 0: + _core_if->hfnum_0_samples++; + _core_if->hfnum_0_frrem_accum += hfnum.b.frrem; + break; + default: + _core_if->hfnum_other_samples++; + _core_if->hfnum_other_frrem_accum += hfnum.b.frrem; + break; + } + } +#endif + } +} + +#ifdef DEBUG +static void hc_xfer_timeout(unsigned long _ptr) +{ + hc_xfer_info_t *xfer_info = (hc_xfer_info_t *)_ptr; + int hc_num = xfer_info->hc->hc_num; + DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num); + DWC_WARN(" start_hcchar_val 0x%08x\n", xfer_info->core_if->start_hcchar_val[hc_num]); +} +#endif + +/* + * This function does the setup for a data transfer for a host channel and + * starts the transfer. May be called in either Slave mode or DMA mode. In + * Slave mode, the caller must ensure that there is sufficient space in the + * request queue and Tx Data FIFO. + * + * For an OUT transfer in Slave mode, it loads a data packet into the + * appropriate FIFO. If necessary, additional data packets will be loaded in + * the Host ISR. + * + * For an IN transfer in Slave mode, a data packet is requested. The data + * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, + * additional data packets are requested in the Host ISR. + * + * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ + * register along with a packet count of 1 and the channel is enabled. This + * causes a single PING transaction to occur. Other fields in HCTSIZ are + * simply set to 0 since no data transfer occurs in this case. + * + * For a PING transfer in DMA mode, the HCTSIZ register is initialized with + * all the information required to perform the subsequent data transfer. In + * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the + * controller performs the entire PING protocol, then starts the data + * transfer. + * + * @param _core_if Programming view of DWC_otg controller. + * @param _hc Information needed to initialize the host channel. The xfer_len + * value may be reduced to accommodate the max widths of the XferSize and + * PktCnt fields in the HCTSIZn register. The multi_count value may be changed + * to reflect the final xfer_len value. + */ +void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) +{ + hcchar_data_t hcchar; + hctsiz_data_t hctsiz; + uint16_t num_packets; + uint32_t max_hc_xfer_size = _core_if->core_params->max_transfer_size; + uint16_t max_hc_pkt_count = _core_if->core_params->max_packet_count; + dwc_otg_hc_regs_t *hc_regs = _core_if->host_if->hc_regs[_hc->hc_num]; + + hctsiz.d32 = 0; + + if (_hc->do_ping) { + if (!_core_if->dma_enable) { + dwc_otg_hc_do_ping(_core_if, _hc); + _hc->xfer_started = 1; + return; + } else { + hctsiz.b.dopng = 1; + } + } + + if (_hc->do_split) { + num_packets = 1; + + if (_hc->complete_split && !_hc->ep_is_in) { + /* For CSPLIT OUT Transfer, set the size to 0 so the + * core doesn't expect any data written to the FIFO */ + _hc->xfer_len = 0; + } else if (_hc->ep_is_in || (_hc->xfer_len > _hc->max_packet)) { + _hc->xfer_len = _hc->max_packet; + } else if (!_hc->ep_is_in && (_hc->xfer_len > 188)) { + _hc->xfer_len = 188; + } + + hctsiz.b.xfersize = _hc->xfer_len; + } else { + /* + * Ensure that the transfer length and packet count will fit + * in the widths allocated for them in the HCTSIZn register. + */ + if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR || + _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { + /* + * Make sure the transfer size is no larger than one + * (micro)frame's worth of data. (A check was done + * when the periodic transfer was accepted to ensure + * that a (micro)frame's worth of data can be + * programmed into a channel.) + */ + uint32_t max_periodic_len = _hc->multi_count * _hc->max_packet; + if (_hc->xfer_len > max_periodic_len) { + _hc->xfer_len = max_periodic_len; + } else { + } + } else if (_hc->xfer_len > max_hc_xfer_size) { + /* Make sure that xfer_len is a multiple of max packet size. */ + _hc->xfer_len = max_hc_xfer_size - _hc->max_packet + 1; + } + + if (_hc->xfer_len > 0) { + num_packets = (_hc->xfer_len + _hc->max_packet - 1) / _hc->max_packet; + if (num_packets > max_hc_pkt_count) { + num_packets = max_hc_pkt_count; + _hc->xfer_len = num_packets * _hc->max_packet; + } + } else { + /* Need 1 packet for transfer length of 0. */ + num_packets = 1; + } + + if (_hc->ep_is_in) { + /* Always program an integral # of max packets for IN transfers. */ + _hc->xfer_len = num_packets * _hc->max_packet; + } + + if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR || + _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { + /* + * Make sure that the multi_count field matches the + * actual transfer length. + */ + _hc->multi_count = num_packets; + + } + + if (_hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { + /* Set up the initial PID for the transfer. */ + if (_hc->speed == DWC_OTG_EP_SPEED_HIGH) { + if (_hc->ep_is_in) { + if (_hc->multi_count == 1) { + _hc->data_pid_start = DWC_OTG_HC_PID_DATA0; + } else if (_hc->multi_count == 2) { + _hc->data_pid_start = DWC_OTG_HC_PID_DATA1; + } else { + _hc->data_pid_start = DWC_OTG_HC_PID_DATA2; + } + } else { + if (_hc->multi_count == 1) { + _hc->data_pid_start = DWC_OTG_HC_PID_DATA0; + } else { + _hc->data_pid_start = DWC_OTG_HC_PID_MDATA; + } + } + } else { + _hc->data_pid_start = DWC_OTG_HC_PID_DATA0; + } + } + + hctsiz.b.xfersize = _hc->xfer_len; + } + + _hc->start_pkt_count = num_packets; + hctsiz.b.pktcnt = num_packets; + hctsiz.b.pid = _hc->data_pid_start; + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); + + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num); + DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize); + DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt); + DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid); + + if (_core_if->dma_enable) { +#ifdef DEBUG +if(((uint32_t)_hc->xfer_buff)%4) +printk("dwc_otg_hc_start_transfer _hc->xfer_buff not 4 byte alignment\n"); +#endif + dwc_write_reg32(&hc_regs->hcdma, (uint32_t)_hc->xfer_buff); + } + + /* Start the split */ + if (_hc->do_split) { + hcsplt_data_t hcsplt; + hcsplt.d32 = dwc_read_reg32 (&hc_regs->hcsplt); + hcsplt.b.spltena = 1; + dwc_write_reg32(&hc_regs->hcsplt, hcsplt.d32); + } + + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hcchar.b.multicnt = _hc->multi_count; + hc_set_even_odd_frame(_core_if, _hc, &hcchar); +#ifdef DEBUG + _core_if->start_hcchar_val[_hc->hc_num] = hcchar.d32; + if (hcchar.b.chdis) { + DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", + __func__, _hc->hc_num, hcchar.d32); + } +#endif + + /* Set host channel enable after all other setup is complete. */ + hcchar.b.chen = 1; + hcchar.b.chdis = 0; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + + _hc->xfer_started = 1; + _hc->requests++; + + if (!_core_if->dma_enable && !_hc->ep_is_in && _hc->xfer_len > 0) { + /* Load OUT packet into the appropriate Tx FIFO. */ + dwc_otg_hc_write_packet(_core_if, _hc); + } + +#ifdef DEBUG + /* Start a timer for this transfer. */ + _core_if->hc_xfer_timer[_hc->hc_num].function = hc_xfer_timeout; + _core_if->hc_xfer_info[_hc->hc_num].core_if = _core_if; + _core_if->hc_xfer_info[_hc->hc_num].hc = _hc; + _core_if->hc_xfer_timer[_hc->hc_num].data = (unsigned long)(&_core_if->hc_xfer_info[_hc->hc_num]); + _core_if->hc_xfer_timer[_hc->hc_num].expires = jiffies + (HZ*10); + add_timer(&_core_if->hc_xfer_timer[_hc->hc_num]); +#endif +} + +/** + * This function continues a data transfer that was started by previous call + * to dwc_otg_hc_start_transfer. The caller must ensure there is + * sufficient space in the request queue and Tx Data FIFO. This function + * should only be called in Slave mode. In DMA mode, the controller acts + * autonomously to complete transfers programmed to a host channel. + * + * For an OUT transfer, a new data packet is loaded into the appropriate FIFO + * if there is any data remaining to be queued. For an IN transfer, another + * data packet is always requested. For the SETUP phase of a control transfer, + * this function does nothing. + * + * @return 1 if a new request is queued, 0 if no more requests are required + * for this transfer. + */ +int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) +{ + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num); + + if (_hc->do_split) { + /* SPLITs always queue just once per channel */ + return 0; + } else if (_hc->data_pid_start == DWC_OTG_HC_PID_SETUP) { + /* SETUPs are queued only once since they can't be NAKed. */ + return 0; + } else if (_hc->ep_is_in) { + /* + * Always queue another request for other IN transfers. If + * back-to-back INs are issued and NAKs are received for both, + * the driver may still be processing the first NAK when the + * second NAK is received. When the interrupt handler clears + * the NAK interrupt for the first NAK, the second NAK will + * not be seen. So we can't depend on the NAK interrupt + * handler to requeue a NAKed request. Instead, IN requests + * are issued each time this function is called. When the + * transfer completes, the extra requests for the channel will + * be flushed. + */ + hcchar_data_t hcchar; + dwc_otg_hc_regs_t *hc_regs = _core_if->host_if->hc_regs[_hc->hc_num]; + + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hc_set_even_odd_frame(_core_if, _hc, &hcchar); + hcchar.b.chen = 1; + hcchar.b.chdis = 0; + DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n", hcchar.d32); + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + _hc->requests++; + return 1; + } else { + /* OUT transfers. */ + if (_hc->xfer_count < _hc->xfer_len) { + if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR || + _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { + hcchar_data_t hcchar; + dwc_otg_hc_regs_t *hc_regs; + hc_regs = _core_if->host_if->hc_regs[_hc->hc_num]; + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hc_set_even_odd_frame(_core_if, _hc, &hcchar); + } + + /* Load OUT packet into the appropriate Tx FIFO. */ + dwc_otg_hc_write_packet(_core_if, _hc); + _hc->requests++; + return 1; + } else { + return 0; + } + } +} + +/** + * Starts a PING transfer. This function should only be called in Slave mode. + * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled. + */ +void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) +{ + hcchar_data_t hcchar; + hctsiz_data_t hctsiz; + dwc_otg_hc_regs_t *hc_regs = _core_if->host_if->hc_regs[_hc->hc_num]; + + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num); + + hctsiz.d32 = 0; + hctsiz.b.dopng = 1; + hctsiz.b.pktcnt = 1; + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); + + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hcchar.b.chen = 1; + hcchar.b.chdis = 0; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); +} + +/* + * This function writes a packet into the Tx FIFO associated with the Host + * Channel. For a channel associated with a non-periodic EP, the non-periodic + * Tx FIFO is written. For a channel associated with a periodic EP, the + * periodic Tx FIFO is written. This function should only be called in Slave + * mode. + * + * Upon return the xfer_buff and xfer_count fields in _hc are incremented by + * then number of bytes written to the Tx FIFO. + */ +void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) +{ + uint32_t i; + uint32_t remaining_count; + uint32_t byte_count; + uint32_t dword_count; + + uint32_t *data_buff = (uint32_t *)(_hc->xfer_buff); + uint32_t *data_fifo = _core_if->data_fifo[_hc->hc_num]; + + remaining_count = _hc->xfer_len - _hc->xfer_count; + if (remaining_count > _hc->max_packet) { + byte_count = _hc->max_packet; + } else { + byte_count = remaining_count; + } + + dword_count = (byte_count + 3) / 4; + + if ((((unsigned long)data_buff) & 0x3) == 0) { + /* xfer_buff is DWORD aligned. */ + for (i = 0; i < dword_count; i++, data_buff++) { + dwc_write_reg32(data_fifo, *data_buff); + } + } else { + /* xfer_buff is not DWORD aligned. */ + for (i = 0; i < dword_count; i++, data_buff++) { + dwc_write_reg32(data_fifo, get_unaligned(data_buff)); + } + } + + _hc->xfer_count += byte_count; + _hc->xfer_buff += byte_count; +} + +/** + * Gets the current USB frame number. This is the frame number from the last + * SOF packet. + */ +uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if) +{ + dsts_data_t dsts; + dsts.d32 = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->dsts); + + /* read current frame/microfreme number from DSTS register */ + return dsts.b.soffn; +} + +/** + * This function reads a setup packet from the Rx FIFO into the destination + * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl) + * Interrupt routine when a SETUP packet has been received in Slave mode. + * + * @param _core_if Programming view of DWC_otg controller. + * @param _dest Destination buffer for packet data. + */ +void dwc_otg_read_setup_packet(dwc_otg_core_if_t *_core_if, uint32_t *_dest) +{ + /* Get the 8 bytes of a setup transaction data */ + + /* Pop 2 DWORDS off the receive data FIFO into memory */ + _dest[0] = dwc_read_reg32(_core_if->data_fifo[0]); + _dest[1] = dwc_read_reg32(_core_if->data_fifo[0]); + //_dest[0] = dwc_read_datafifo32(_core_if->data_fifo[0]); + //_dest[1] = dwc_read_datafifo32(_core_if->data_fifo[0]); +} + + +/** + * This function enables EP0 OUT to receive SETUP packets and configures EP0 + * IN for transmitting packets. It is normally called when the + * "Enumeration Done" interrupt occurs. + * + * @param _core_if Programming view of DWC_otg controller. + * @param _ep The EP0 data. + */ +void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) +{ + dwc_otg_dev_if_t *dev_if = _core_if->dev_if; + dsts_data_t dsts; + depctl_data_t diepctl; + depctl_data_t doepctl; + dctl_data_t dctl ={.d32=0}; + + /* Read the Device Status and Endpoint 0 Control registers */ + dsts.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dsts); + diepctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl); + doepctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl); + + /* Set the MPS of the IN EP based on the enumeration speed */ + switch (dsts.b.enumspd) { + case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: + case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: + case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ: + diepctl.b.mps = DWC_DEP0CTL_MPS_64; + break; + case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ: + diepctl.b.mps = DWC_DEP0CTL_MPS_8; + break; + } + + dwc_write_reg32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); + + /* Enable OUT EP for receive */ + doepctl.b.epena = 1; + dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32); + +#ifdef VERBOSE + DWC_DEBUGPL(DBG_PCDV,"doepctl0=%0x\n", + dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl)); + DWC_DEBUGPL(DBG_PCDV,"diepctl0=%0x\n", + dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl)); +#endif + dctl.b.cgnpinnak = 1; + dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); + DWC_DEBUGPL(DBG_PCDV,"dctl=%0x\n", + dwc_read_reg32(&dev_if->dev_global_regs->dctl)); +} + +/** + * This function activates an EP. The Device EP control register for + * the EP is configured as defined in the ep structure. Note: This + * function is not used for EP0. + * + * @param _core_if Programming view of DWC_otg controller. + * @param _ep The EP to activate. + */ +void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) +{ + dwc_otg_dev_if_t *dev_if = _core_if->dev_if; + depctl_data_t depctl; + volatile uint32_t *addr; + daint_data_t daintmsk = {.d32=0}; + + DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, _ep->num, + (_ep->is_in?"IN":"OUT")); + + /* Read DEPCTLn register */ + if (_ep->is_in == 1) { + addr = &dev_if->in_ep_regs[_ep->num]->diepctl; + daintmsk.ep.in = 1<<_ep->num; + } else { + addr = &dev_if->out_ep_regs[_ep->num]->doepctl; + daintmsk.ep.out = 1<<_ep->num; + } + + /* If the EP is already active don't change the EP Control + * register. */ + depctl.d32 = dwc_read_reg32(addr); + if (!depctl.b.usbactep) { + depctl.b.mps = _ep->maxpacket; + depctl.b.eptype = _ep->type; + depctl.b.txfnum = _ep->tx_fifo_num; + + if (_ep->type == DWC_OTG_EP_TYPE_ISOC) { + depctl.b.setd0pid = 1; // ??? + } else { + depctl.b.setd0pid = 1; + } + depctl.b.usbactep = 1; + + dwc_write_reg32(addr, depctl.d32); + DWC_DEBUGPL(DBG_PCDV,"DEPCTL=%08x\n", dwc_read_reg32(addr)); + } + + + /* Enable the Interrupt for this EP */ + dwc_modify_reg32(&dev_if->dev_global_regs->daintmsk, + 0, daintmsk.d32); + DWC_DEBUGPL(DBG_PCDV,"DAINTMSK=%0x\n", + dwc_read_reg32(&dev_if->dev_global_regs->daintmsk)); + _ep->stall_clear_flag = 0; + return; +} + +/** + * This function deactivates an EP. This is done by clearing the USB Active + * EP bit in the Device EP control register. Note: This function is not used + * for EP0. EP0 cannot be deactivated. + * + * @param _core_if Programming view of DWC_otg controller. + * @param _ep The EP to deactivate. + */ +void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) +{ + depctl_data_t depctl ={.d32 = 0}; + volatile uint32_t *addr; + daint_data_t daintmsk = {.d32=0}; + + /* Read DEPCTLn register */ + if (_ep->is_in == 1) { + addr = &_core_if->dev_if->in_ep_regs[_ep->num]->diepctl; + daintmsk.ep.in = 1<<_ep->num; + } else { + addr = &_core_if->dev_if->out_ep_regs[_ep->num]->doepctl; + daintmsk.ep.out = 1<<_ep->num; + } + + depctl.b.usbactep = 0; + dwc_write_reg32(addr, depctl.d32); + + /* Disable the Interrupt for this EP */ + dwc_modify_reg32(&_core_if->dev_if->dev_global_regs->daintmsk, + daintmsk.d32, 0); + + return; +} + +/** + * This function does the setup for a data transfer for an EP and + * starts the transfer. For an IN transfer, the packets will be + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, + * the packets are unloaded from the Rx FIFO in the ISR. the ISR. + * + * @param _core_if Programming view of DWC_otg controller. + * @param _ep The EP to start the transfer on. + */ +void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) +{ + /** @todo Refactor this funciton to check the transfer size + * count value does not execed the number bits in the Transfer + * count register. */ + depctl_data_t depctl; + deptsiz_data_t deptsiz; + gintmsk_data_t intr_mask = { .d32 = 0}; + +#ifdef CHECK_PACKET_COUNTER_WIDTH + const uint32_t MAX_XFER_SIZE = + _core_if->core_params->max_transfer_size; + const uint32_t MAX_PKT_COUNT = + _core_if->core_params->max_packet_count; + uint32_t num_packets; + uint32_t transfer_len; + dwc_otg_dev_out_ep_regs_t *out_regs = + _core_if->dev_if->out_ep_regs[_ep->num]; + dwc_otg_dev_in_ep_regs_t *in_regs = + _core_if->dev_if->in_ep_regs[_ep->num]; + gnptxsts_data_t txstatus; + + int lvl = SET_DEBUG_LEVEL(DBG_PCD); + + + DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d " + "xfer_buff=%p start_xfer_buff=%p\n", + _ep->num, (_ep->is_in?"IN":"OUT"), _ep->xfer_len, + _ep->xfer_count, _ep->xfer_buff, _ep->start_xfer_buff); + + transfer_len = _ep->xfer_len - _ep->xfer_count; + if (transfer_len > MAX_XFER_SIZE) { + transfer_len = MAX_XFER_SIZE; + } + if (transfer_len == 0) { + num_packets = 1; + /* OUT EP to recieve Zero-length packet set transfer + * size to maxpacket size. */ + if (!_ep->is_in) { + transfer_len = _ep->maxpacket; + } + } else { + num_packets = + (transfer_len + _ep->maxpacket - 1) / _ep->maxpacket; + if (num_packets > MAX_PKT_COUNT) { + num_packets = MAX_PKT_COUNT; + } + } + DWC_DEBUGPL(DBG_PCD, "transfer_len=%d #pckt=%d\n", transfer_len, + num_packets); + + deptsiz.b.xfersize = transfer_len; + deptsiz.b.pktcnt = num_packets; + + /* IN endpoint */ + if (_ep->is_in == 1) { + depctl.d32 = dwc_read_reg32(&in_regs->diepctl); + } else {/* OUT endpoint */ + depctl.d32 = dwc_read_reg32(&out_regs->doepctl); + } + + /* EP enable, IN data in FIFO */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + /* IN endpoint */ + if (_ep->is_in == 1) { + txstatus.d32 = + dwc_read_reg32(&_core_if->core_global_regs->gnptxsts); + if (txstatus.b.nptxqspcavail == 0) { + DWC_DEBUGPL(DBG_ANY, "TX Queue Full (0x%0x)\n", + txstatus.d32); + return; + } + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); + dwc_write_reg32(&in_regs->diepctl, depctl.d32); + /** + * Enable the Non-Periodic Tx FIFO empty interrupt, the + * data will be written into the fifo by the ISR. + */ + if (_core_if->dma_enable) { + dwc_write_reg32(&in_regs->diepdma, (uint32_t) _ep->xfer_buff); + } else { + if (_core_if->en_multiple_tx_fifo == 0) { + intr_mask.b.nptxfempty = 1; + dwc_modify_reg32( &_core_if->core_global_regs->gintsts, + intr_mask.d32, 0); + dwc_modify_reg32( &_core_if->core_global_regs->gintmsk, + intr_mask.d32, intr_mask.d32); + } else { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (_ep->xfer_len > 0 && + _ep->type != DWC_OTG_EP_TYPE_ISOC) { + uint32_t fifoemptymsk = 0; + fifoemptymsk = (0x1 << _ep->num); + dwc_modify_reg32(&_core_if->dev_if->dev_global_regs-> + dtknqr4_fifoemptymsk,0, fifoemptymsk); + } + } + } + } else { /* OUT endpoint */ + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); + dwc_write_reg32(&out_regs->doepctl, depctl.d32); + if (_core_if->dma_enable) { + dwc_write_reg32(&out_regs->doepdma,(uint32_t) _ep->xfer_buff); + } + } + DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n", + dwc_read_reg32(&out_regs->doepctl), + dwc_read_reg32(&out_regs->doeptsiz)); + DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n", + dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk), + dwc_read_reg32(&_core_if->core_global_regs->gintmsk)); + + SET_DEBUG_LEVEL(lvl); +#endif + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__); + + DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d " + "xfer_buff=%p start_xfer_buff=%p\n", + _ep->num, (_ep->is_in?"IN":"OUT"), _ep->xfer_len, + _ep->xfer_count, _ep->xfer_buff, _ep->start_xfer_buff); + + /* IN endpoint */ + if (_ep->is_in == 1) { + dwc_otg_dev_in_ep_regs_t * in_regs = _core_if->dev_if->in_ep_regs[_ep->num]; + gnptxsts_data_t gtxstatus; + gtxstatus.d32 = dwc_read_reg32(&_core_if->core_global_regs->gnptxsts); + if (_core_if->en_multiple_tx_fifo == 0 && + gtxstatus.b.nptxqspcavail == 0) { +#ifdef DEBUG + DWC_PRINT("TX Queue Full (0x%0x)\n", gtxstatus.d32); +#endif + //return; + MDELAY(100); //james + } + + depctl.d32 = dwc_read_reg32(&(in_regs->diepctl)); + deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz)); + + /* Zero Length Packet? */ + if (_ep->xfer_len == 0) { + deptsiz.b.xfersize = 0; + deptsiz.b.pktcnt = 1; + } else { + + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + deptsiz.b.xfersize = _ep->xfer_len; + deptsiz.b.pktcnt = (_ep->xfer_len - 1 + _ep->maxpacket) / _ep->maxpacket; + } + + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); + + /* Write the DMA register */ + if (_core_if->dma_enable) { +#if 1 // winder + dma_cache_wback_inv((unsigned long) _ep->xfer_buff, _ep->xfer_len); // winder + dwc_write_reg32 (&(in_regs->diepdma), + CPHYSADDR((uint32_t)_ep->xfer_buff)); // winder +#else + dwc_write_reg32 (&(in_regs->diepdma), + (uint32_t)_ep->dma_addr); +#endif + } else { + if (_ep->type != DWC_OTG_EP_TYPE_ISOC) { + /** + * Enable the Non-Periodic Tx FIFO empty interrupt, + * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, + * the data will be written into the fifo by the ISR. + */ + if (_core_if->en_multiple_tx_fifo == 0) { + intr_mask.b.nptxfempty = 1; + dwc_modify_reg32( &_core_if->core_global_regs->gintsts, + intr_mask.d32, 0); + dwc_modify_reg32( &_core_if->core_global_regs->gintmsk, + intr_mask.d32, intr_mask.d32); + } else { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (_ep->xfer_len > 0) { + uint32_t fifoemptymsk = 0; + fifoemptymsk = 1 << _ep->num; + dwc_modify_reg32(&_core_if->dev_if->dev_global_regs-> + dtknqr4_fifoemptymsk,0,fifoemptymsk); + } + } + } + } + + /* EP enable, IN data in FIFO */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + dwc_write_reg32(&in_regs->diepctl, depctl.d32); + + if (_core_if->dma_enable) { + depctl.d32 = dwc_read_reg32 (&_core_if->dev_if->in_ep_regs[0]->diepctl); + depctl.b.nextep = _ep->num; + dwc_write_reg32 (&_core_if->dev_if->in_ep_regs[0]->diepctl, depctl.d32); + + } + } else { + /* OUT endpoint */ + dwc_otg_dev_out_ep_regs_t * out_regs = _core_if->dev_if->out_ep_regs[_ep->num]; + + depctl.d32 = dwc_read_reg32(&(out_regs->doepctl)); + deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz)); + + /* Program the transfer size and packet count as follows: + * + * pktcnt = N + * xfersize = N * maxpacket + */ + if (_ep->xfer_len == 0) { + /* Zero Length Packet */ + deptsiz.b.xfersize = _ep->maxpacket; + deptsiz.b.pktcnt = 1; + } else { + deptsiz.b.pktcnt = (_ep->xfer_len + (_ep->maxpacket - 1)) / _ep->maxpacket; + deptsiz.b.xfersize = deptsiz.b.pktcnt * _ep->maxpacket; + } + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); + + DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n", + _ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt); + + if (_core_if->dma_enable) { +#if 1 // winder + dwc_write_reg32 (&(out_regs->doepdma), + CPHYSADDR((uint32_t)_ep->xfer_buff)); // winder +#else + dwc_write_reg32 (&(out_regs->doepdma), + (uint32_t)_ep->dma_addr); +#endif + } + + if (_ep->type == DWC_OTG_EP_TYPE_ISOC) { + /** @todo NGS: dpid is read-only. Use setd0pid + * or setd1pid. */ + if (_ep->even_odd_frame) { + depctl.b.setd1pid = 1; + } else { + depctl.b.setd0pid = 1; + } + } + + /* EP enable */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + + dwc_write_reg32(&out_regs->doepctl, depctl.d32); + + DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n", + dwc_read_reg32(&out_regs->doepctl), + dwc_read_reg32(&out_regs->doeptsiz)); + DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n", + dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk), + dwc_read_reg32(&_core_if->core_global_regs->gintmsk)); + } +} + + +/** + * This function does the setup for a data transfer for EP0 and starts + * the transfer. For an IN transfer, the packets will be loaded into + * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are + * unloaded from the Rx FIFO in the ISR. + * + * @param _core_if Programming view of DWC_otg controller. + * @param _ep The EP0 data. + */ +void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) +{ + volatile depctl_data_t depctl; + volatile deptsiz0_data_t deptsiz; + gintmsk_data_t intr_mask = { .d32 = 0}; + + DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d " + "xfer_buff=%p start_xfer_buff=%p total_len=%d\n", + _ep->num, (_ep->is_in?"IN":"OUT"), _ep->xfer_len, + _ep->xfer_count, _ep->xfer_buff, _ep->start_xfer_buff, + _ep->total_len); + _ep->total_len = _ep->xfer_len; + + /* IN endpoint */ + if (_ep->is_in == 1) { + dwc_otg_dev_in_ep_regs_t * in_regs = _core_if->dev_if->in_ep_regs[0]; + gnptxsts_data_t gtxstatus; + gtxstatus.d32 = dwc_read_reg32(&_core_if->core_global_regs->gnptxsts); + if (_core_if->en_multiple_tx_fifo == 0 && + gtxstatus.b.nptxqspcavail == 0) { +#ifdef DEBUG + deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz); + DWC_DEBUGPL(DBG_PCD,"DIEPCTL0=%0x\n", + dwc_read_reg32(&in_regs->diepctl)); + DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n", + deptsiz.d32, deptsiz.b.xfersize,deptsiz.b.pktcnt); + DWC_PRINT("TX Queue or FIFO Full (0x%0x)\n", gtxstatus.d32); +#endif /* */ + printk("TX Queue or FIFO Full!!!!\n"); // test-only + //return; + MDELAY(100); //james + } + + depctl.d32 = dwc_read_reg32(&in_regs->diepctl); + deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz); + + /* Zero Length Packet? */ + if (_ep->xfer_len == 0) { + deptsiz.b.xfersize = 0; + deptsiz.b.pktcnt = 1; + } else { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + if (_ep->xfer_len > _ep->maxpacket) { + _ep->xfer_len = _ep->maxpacket; + deptsiz.b.xfersize = _ep->maxpacket; + } + else { + deptsiz.b.xfersize = _ep->xfer_len; + } + deptsiz.b.pktcnt = 1; + + } + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); + DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", + _ep->xfer_len, deptsiz.b.xfersize,deptsiz.b.pktcnt, deptsiz.d32); + + /* Write the DMA register */ + if (_core_if->dma_enable) { + dwc_write_reg32(&(in_regs->diepdma), (uint32_t) _ep->dma_addr); + } + + /* EP enable, IN data in FIFO */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + dwc_write_reg32(&in_regs->diepctl, depctl.d32); + + /** + * Enable the Non-Periodic Tx FIFO empty interrupt, the + * data will be written into the fifo by the ISR. + */ + if (!_core_if->dma_enable) { + if (_core_if->en_multiple_tx_fifo == 0) { + intr_mask.b.nptxfempty = 1; + dwc_modify_reg32(&_core_if->core_global_regs->gintsts, intr_mask.d32, 0); + dwc_modify_reg32(&_core_if->core_global_regs->gintmsk, intr_mask.d32, + intr_mask.d32); + } else { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (_ep->xfer_len > 0) { + uint32_t fifoemptymsk = 0; + fifoemptymsk |= 1 << _ep->num; + dwc_modify_reg32(&_core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk, + 0, fifoemptymsk); + } + + } + } + } else { + /* OUT endpoint */ + dwc_otg_dev_out_ep_regs_t * out_regs = _core_if->dev_if->out_ep_regs[_ep->num]; + + depctl.d32 = dwc_read_reg32(&out_regs->doepctl); + deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz); + + /* Program the transfer size and packet count as follows: + * xfersize = N * (maxpacket + 4 - (maxpacket % 4)) + * pktcnt = N */ + if (_ep->xfer_len == 0) { + /* Zero Length Packet */ + deptsiz.b.xfersize = _ep->maxpacket; + deptsiz.b.pktcnt = 1; + } else { + deptsiz.b.pktcnt = (_ep->xfer_len + (_ep->maxpacket - 1)) / _ep->maxpacket; + deptsiz.b.xfersize = deptsiz.b.pktcnt * _ep->maxpacket; + } + + dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); + DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n", + _ep->xfer_len, deptsiz.b.xfersize,deptsiz.b.pktcnt); + + if (_core_if->dma_enable) { + dwc_write_reg32(&(out_regs->doepdma), (uint32_t) _ep->dma_addr); + } + + /* EP enable */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + dwc_write_reg32 (&(out_regs->doepctl), depctl.d32); + } +} + +/** + * This function continues control IN transfers started by + * dwc_otg_ep0_start_transfer, when the transfer does not fit in a + * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one + * bit for the packet count. + * + * @param _core_if Programming view of DWC_otg controller. + * @param _ep The EP0 data. + */ +void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) +{ + depctl_data_t depctl; + deptsiz0_data_t deptsiz; + gintmsk_data_t intr_mask = { .d32 = 0}; + + if (_ep->is_in == 1) { + dwc_otg_dev_in_ep_regs_t *in_regs = + _core_if->dev_if->in_ep_regs[0]; + gnptxsts_data_t tx_status = {.d32 = 0}; + + tx_status.d32 = dwc_read_reg32( &_core_if->core_global_regs->gnptxsts ); + /** @todo Should there be check for room in the Tx + * Status Queue. If not remove the code above this comment. */ + + depctl.d32 = dwc_read_reg32(&in_regs->diepctl); + deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz); + + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + deptsiz.b.xfersize = (_ep->total_len - _ep->xfer_count) > _ep->maxpacket ? _ep->maxpacket : + (_ep->total_len - _ep->xfer_count); + deptsiz.b.pktcnt = 1; + _ep->xfer_len += deptsiz.b.xfersize; + + dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); + DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", + _ep->xfer_len, + deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32); + + /* Write the DMA register */ + if (_core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) { + dwc_write_reg32 (&(in_regs->diepdma), + CPHYSADDR((uint32_t)_ep->dma_addr)); // winder + } + + /* EP enable, IN data in FIFO */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + dwc_write_reg32(&in_regs->diepctl, depctl.d32); + + /** + * Enable the Non-Periodic Tx FIFO empty interrupt, the + * data will be written into the fifo by the ISR. + */ + if (!_core_if->dma_enable) { + /* First clear it from GINTSTS */ + intr_mask.b.nptxfempty = 1; + dwc_write_reg32( &_core_if->core_global_regs->gintsts, + intr_mask.d32 ); + + dwc_modify_reg32( &_core_if->core_global_regs->gintmsk, + intr_mask.d32, intr_mask.d32); + } + + } + +} + +#ifdef DEBUG +void dump_msg(const u8 *buf, unsigned int length) +{ + unsigned int start, num, i; + char line[52], *p; + + if (length >= 512) + return; + start = 0; + while (length > 0) { + num = min(length, 16u); + p = line; + for (i = 0; i < num; ++i) { + if (i == 8) + *p++ = ' '; + sprintf(p, " %02x", buf[i]); + p += 3; + } + *p = 0; + DWC_PRINT( "%6x: %s\n", start, line); + buf += num; + start += num; + length -= num; + } +} +#else +static inline void dump_msg(const u8 *buf, unsigned int length) +{ +} +#endif + +/** + * This function writes a packet into the Tx FIFO associated with the + * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For + * periodic EPs the periodic Tx FIFO associated with the EP is written + * with all packets for the next micro-frame. + * + * @param _core_if Programming view of DWC_otg controller. + * @param _ep The EP to write packet for. + * @param _dma Indicates if DMA is being used. + */ +void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma) +{ + /** + * The buffer is padded to DWORD on a per packet basis in + * slave/dma mode if the MPS is not DWORD aligned. The last + * packet, if short, is also padded to a multiple of DWORD. + * + * ep->xfer_buff always starts DWORD aligned in memory and is a + * multiple of DWORD in length + * + * ep->xfer_len can be any number of bytes + * + * ep->xfer_count is a multiple of ep->maxpacket until the last + * packet + * + * FIFO access is DWORD */ + + uint32_t i; + uint32_t byte_count; + uint32_t dword_count; + uint32_t *fifo; + uint32_t *data_buff = (uint32_t *)_ep->xfer_buff; + + //DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, _core_if, _ep); + if (_ep->xfer_count >= _ep->xfer_len) { + DWC_WARN("%s() No data for EP%d!!!\n", __func__, _ep->num); + return; + } + + /* Find the byte length of the packet either short packet or MPS */ + if ((_ep->xfer_len - _ep->xfer_count) < _ep->maxpacket) { + byte_count = _ep->xfer_len - _ep->xfer_count; + } + else { + byte_count = _ep->maxpacket; + } + + /* Find the DWORD length, padded by extra bytes as neccessary if MPS + * is not a multiple of DWORD */ + dword_count = (byte_count + 3) / 4; + +#ifdef VERBOSE + dump_msg(_ep->xfer_buff, byte_count); +#endif + if (_ep->type == DWC_OTG_EP_TYPE_ISOC) { + /**@todo NGS Where are the Periodic Tx FIFO addresses + * intialized? What should this be? */ + fifo = _core_if->data_fifo[_ep->tx_fifo_num]; + } else { + fifo = _core_if->data_fifo[_ep->num]; + } + + DWC_DEBUGPL((DBG_PCDV|DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n", + fifo, data_buff, *data_buff, byte_count); + + + if (!_dma) { + for (i=0; ixfer_count += byte_count; + _ep->xfer_buff += byte_count; +#if 1 // winder, why do we need this?? + _ep->dma_addr += byte_count; +#endif +} + +/** + * Set the EP STALL. + * + * @param _core_if Programming view of DWC_otg controller. + * @param _ep The EP to set the stall on. + */ +void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) +{ + depctl_data_t depctl; + volatile uint32_t *depctl_addr; + + DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _ep->num, + (_ep->is_in?"IN":"OUT")); + + if (_ep->is_in == 1) { + depctl_addr = &(_core_if->dev_if->in_ep_regs[_ep->num]->diepctl); + depctl.d32 = dwc_read_reg32(depctl_addr); + + /* set the disable and stall bits */ + if (depctl.b.epena) { + depctl.b.epdis = 1; + } + depctl.b.stall = 1; + dwc_write_reg32(depctl_addr, depctl.d32); + + } else { + depctl_addr = &(_core_if->dev_if->out_ep_regs[_ep->num]->doepctl); + depctl.d32 = dwc_read_reg32(depctl_addr); + + /* set the stall bit */ + depctl.b.stall = 1; + dwc_write_reg32(depctl_addr, depctl.d32); + } + DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr)); + return; +} + +/** + * Clear the EP STALL. + * + * @param _core_if Programming view of DWC_otg controller. + * @param _ep The EP to clear stall from. + */ +void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) +{ + depctl_data_t depctl; + volatile uint32_t *depctl_addr; + + DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _ep->num, + (_ep->is_in?"IN":"OUT")); + + if (_ep->is_in == 1) { + depctl_addr = &(_core_if->dev_if->in_ep_regs[_ep->num]->diepctl); + } else { + depctl_addr = &(_core_if->dev_if->out_ep_regs[_ep->num]->doepctl); + } + + depctl.d32 = dwc_read_reg32(depctl_addr); + + /* clear the stall bits */ + depctl.b.stall = 0; + + /* + * USB Spec 9.4.5: For endpoints using data toggle, regardless + * of whether an endpoint has the Halt feature set, a + * ClearFeature(ENDPOINT_HALT) request always results in the + * data toggle being reinitialized to DATA0. + */ + if (_ep->type == DWC_OTG_EP_TYPE_INTR || + _ep->type == DWC_OTG_EP_TYPE_BULK) { + depctl.b.setd0pid = 1; /* DATA0 */ + } + + dwc_write_reg32(depctl_addr, depctl.d32); + DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr)); + return; +} + +/** + * This function reads a packet from the Rx FIFO into the destination + * buffer. To read SETUP data use dwc_otg_read_setup_packet. + * + * @param _core_if Programming view of DWC_otg controller. + * @param _dest Destination buffer for the packet. + * @param _bytes Number of bytes to copy to the destination. + */ +void dwc_otg_read_packet(dwc_otg_core_if_t *_core_if, + uint8_t *_dest, + uint16_t _bytes) +{ + int i; + int word_count = (_bytes + 3) / 4; + + volatile uint32_t *fifo = _core_if->data_fifo[0]; + uint32_t *data_buff = (uint32_t *)_dest; + + /** + * @todo Account for the case where _dest is not dword aligned. This + * requires reading data from the FIFO into a uint32_t temp buffer, + * then moving it into the data buffer. + */ + + DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__, + _core_if, _dest, _bytes); + + for (i=0; idev_if->dev_global_regs->dcfg; + DWC_PRINT("DCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->dev_if->dev_global_regs->dctl; + DWC_PRINT("DCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->dev_if->dev_global_regs->dsts; + DWC_PRINT("DSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->dev_if->dev_global_regs->diepmsk; + DWC_PRINT("DIEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->dev_if->dev_global_regs->doepmsk; + DWC_PRINT("DOEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->dev_if->dev_global_regs->daint; + DWC_PRINT("DAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->dev_if->dev_global_regs->dtknqr1; + DWC_PRINT("DTKNQR1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + if (_core_if->hwcfg2.b.dev_token_q_depth > 6) { + addr=&_core_if->dev_if->dev_global_regs->dtknqr2; + DWC_PRINT("DTKNQR2 @0x%08X : 0x%08X\n", + (uint32_t)addr,dwc_read_reg32(addr)); + } + + addr=&_core_if->dev_if->dev_global_regs->dvbusdis; + DWC_PRINT("DVBUSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + + addr=&_core_if->dev_if->dev_global_regs->dvbuspulse; + DWC_PRINT("DVBUSPULSE @0x%08X : 0x%08X\n", + (uint32_t)addr,dwc_read_reg32(addr)); + + if (_core_if->hwcfg2.b.dev_token_q_depth > 14) { + addr = &_core_if->dev_if->dev_global_regs->dtknqr3_dthrctl; + DWC_PRINT("DTKNQR3 @0x%08X : 0x%08X\n", + (uint32_t)addr, dwc_read_reg32(addr)); + } + + if (_core_if->hwcfg2.b.dev_token_q_depth > 22) { + addr = &_core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk; + DWC_PRINT("DTKNQR4 @0x%08X : 0x%08X\n", (uint32_t) addr, + dwc_read_reg32(addr)); + } + for (i = 0; i <= _core_if->dev_if->num_in_eps; i++) { + DWC_PRINT("Device IN EP %d Registers\n", i); + addr=&_core_if->dev_if->in_ep_regs[i]->diepctl; + DWC_PRINT("DIEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->dev_if->in_ep_regs[i]->diepint; + DWC_PRINT("DIEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->dev_if->in_ep_regs[i]->dieptsiz; + DWC_PRINT("DIETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->dev_if->in_ep_regs[i]->diepdma; + DWC_PRINT("DIEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + +addr = &_core_if->dev_if->in_ep_regs[i]->dtxfsts; + DWC_PRINT("DTXFSTS @0x%08X : 0x%08X\n", (uint32_t) addr, + dwc_read_reg32(addr)); + } + for (i = 0; i <= _core_if->dev_if->num_out_eps; i++) { + DWC_PRINT("Device OUT EP %d Registers\n", i); + addr=&_core_if->dev_if->out_ep_regs[i]->doepctl; + DWC_PRINT("DOEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->dev_if->out_ep_regs[i]->doepfn; + DWC_PRINT("DOEPFN @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->dev_if->out_ep_regs[i]->doepint; + DWC_PRINT("DOEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->dev_if->out_ep_regs[i]->doeptsiz; + DWC_PRINT("DOETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->dev_if->out_ep_regs[i]->doepdma; + DWC_PRINT("DOEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + } + return; +} + +/** + * This function reads the host registers and prints them + * + * @param _core_if Programming view of DWC_otg controller. + */ +void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if) +{ + int i; + volatile uint32_t *addr; + + DWC_PRINT("Host Global Registers\n"); + addr=&_core_if->host_if->host_global_regs->hcfg; + DWC_PRINT("HCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->host_if->host_global_regs->hfir; + DWC_PRINT("HFIR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->host_if->host_global_regs->hfnum; + DWC_PRINT("HFNUM @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->host_if->host_global_regs->hptxsts; + DWC_PRINT("HPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->host_if->host_global_regs->haint; + DWC_PRINT("HAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->host_if->host_global_regs->haintmsk; + DWC_PRINT("HAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=_core_if->host_if->hprt0; + DWC_PRINT("HPRT0 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + + for (i=0; i<_core_if->core_params->host_channels; i++) { + DWC_PRINT("Host Channel %d Specific Registers\n", i); + addr=&_core_if->host_if->hc_regs[i]->hcchar; + DWC_PRINT("HCCHAR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->host_if->hc_regs[i]->hcsplt; + DWC_PRINT("HCSPLT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->host_if->hc_regs[i]->hcint; + DWC_PRINT("HCINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->host_if->hc_regs[i]->hcintmsk; + DWC_PRINT("HCINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->host_if->hc_regs[i]->hctsiz; + DWC_PRINT("HCTSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->host_if->hc_regs[i]->hcdma; + DWC_PRINT("HCDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + + } + return; +} + +/** + * This function reads the core global registers and prints them + * + * @param _core_if Programming view of DWC_otg controller. + */ +void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if) +{ + int i; + volatile uint32_t *addr; + + DWC_PRINT("Core Global Registers\n"); + addr=&_core_if->core_global_regs->gotgctl; + DWC_PRINT("GOTGCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->core_global_regs->gotgint; + DWC_PRINT("GOTGINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->core_global_regs->gahbcfg; + DWC_PRINT("GAHBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->core_global_regs->gusbcfg; + DWC_PRINT("GUSBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->core_global_regs->grstctl; + DWC_PRINT("GRSTCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->core_global_regs->gintsts; + DWC_PRINT("GINTSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->core_global_regs->gintmsk; + DWC_PRINT("GINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->core_global_regs->grxstsr; + DWC_PRINT("GRXSTSR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + //addr=&_core_if->core_global_regs->grxstsp; + //DWC_PRINT("GRXSTSP @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->core_global_regs->grxfsiz; + DWC_PRINT("GRXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->core_global_regs->gnptxfsiz; + DWC_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->core_global_regs->gnptxsts; + DWC_PRINT("GNPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->core_global_regs->gi2cctl; + DWC_PRINT("GI2CCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->core_global_regs->gpvndctl; + DWC_PRINT("GPVNDCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->core_global_regs->ggpio; + DWC_PRINT("GGPIO @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->core_global_regs->guid; + DWC_PRINT("GUID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->core_global_regs->gsnpsid; + DWC_PRINT("GSNPSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->core_global_regs->ghwcfg1; + DWC_PRINT("GHWCFG1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->core_global_regs->ghwcfg2; + DWC_PRINT("GHWCFG2 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->core_global_regs->ghwcfg3; + DWC_PRINT("GHWCFG3 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->core_global_regs->ghwcfg4; + DWC_PRINT("GHWCFG4 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + addr=&_core_if->core_global_regs->hptxfsiz; + DWC_PRINT("HPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); + + for (i=0; i<_core_if->hwcfg4.b.num_dev_perio_in_ep; i++) { + addr=&_core_if->core_global_regs->dptxfsiz_dieptxf[i]; + DWC_PRINT("DPTXFSIZ[%d] @0x%08X : 0x%08X\n",i,(uint32_t)addr,dwc_read_reg32(addr)); + } + +} +#endif + +/** + * Flush a Tx FIFO. + * + * @param _core_if Programming view of DWC_otg controller. + * @param _num Tx FIFO to flush. + */ +extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if, + const int _num ) +{ + dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs; + volatile grstctl_t greset = { .d32 = 0}; + int count = 0; + + DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "Flush Tx FIFO %d\n", _num); + + greset.b.txfflsh = 1; + greset.b.txfnum = _num; + dwc_write_reg32( &global_regs->grstctl, greset.d32 ); + + do { + greset.d32 = dwc_read_reg32( &global_regs->grstctl); + if (++count > 10000){ + DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", + __func__, greset.d32, + dwc_read_reg32( &global_regs->gnptxsts)); + break; + } + + udelay(1); + } while (greset.b.txfflsh == 1); + /* Wait for 3 PHY Clocks*/ + UDELAY(1); +} + +/** + * Flush Rx FIFO. + * + * @param _core_if Programming view of DWC_otg controller. + */ +extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if ) +{ + dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs; + volatile grstctl_t greset = { .d32 = 0}; + int count = 0; + + DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__); + /* + * + */ + greset.b.rxfflsh = 1; + dwc_write_reg32( &global_regs->grstctl, greset.d32 ); + + do { + greset.d32 = dwc_read_reg32( &global_regs->grstctl); + if (++count > 10000){ + DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, + greset.d32); + break; + } + } while (greset.b.rxfflsh == 1); + /* Wait for 3 PHY Clocks*/ + UDELAY(1); +} + +/** + * Do core a soft reset of the core. Be careful with this because it + * resets all the internal state machines of the core. + */ + +void dwc_otg_core_reset(dwc_otg_core_if_t *_core_if) +{ + dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs; + volatile grstctl_t greset = { .d32 = 0}; + int count = 0; + + DWC_DEBUGPL(DBG_CILV, "%s\n", __func__); + /* Wait for AHB master IDLE state. */ + do { + UDELAY(10); + greset.d32 = dwc_read_reg32( &global_regs->grstctl); + if (++count > 100000){ + DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x %x\n", __func__, + greset.d32, greset.b.ahbidle); + return; + } + } while (greset.b.ahbidle == 0); + +// winder add. +#if 1 + /* Note: Actually, I don't exactly why we need to put delay here. */ + MDELAY(100); +#endif + /* Core Soft Reset */ + count = 0; + greset.b.csftrst = 1; + dwc_write_reg32( &global_regs->grstctl, greset.d32 ); +// winder add. +#if 1 + /* Note: Actually, I don't exactly why we need to put delay here. */ + MDELAY(100); +#endif + do { + greset.d32 = dwc_read_reg32( &global_regs->grstctl); + if (++count > 10000){ + DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", __func__, + greset.d32); + break; + } + udelay(1); + } while (greset.b.csftrst == 1); + /* Wait for 3 PHY Clocks*/ + //DWC_PRINT("100ms\n"); + MDELAY(100); +} + + + +/** + * Register HCD callbacks. The callbacks are used to start and stop + * the HCD for interrupt processing. + * + * @param _core_if Programming view of DWC_otg controller. + * @param _cb the HCD callback structure. + * @param _p pointer to be passed to callback function (usb_hcd*). + */ +extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if, + dwc_otg_cil_callbacks_t *_cb, + void *_p) +{ + _core_if->hcd_cb = _cb; + _cb->p = _p; +} + +/** + * Register PCD callbacks. The callbacks are used to start and stop + * the PCD for interrupt processing. + * + * @param _core_if Programming view of DWC_otg controller. + * @param _cb the PCD callback structure. + * @param _p pointer to be passed to callback function (pcd*). + */ +extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if, + dwc_otg_cil_callbacks_t *_cb, + void *_p) +{ + _core_if->pcd_cb = _cb; + _cb->p = _p; +} + diff --git a/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil.h b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil.h new file mode 100644 index 0000000000..bbb9516b85 --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil.h @@ -0,0 +1,911 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil.h $ + * $Revision: 1.1.1.1 $ + * $Date: 2009-04-17 06:15:34 $ + * $Change: 631780 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ + +#if !defined(__DWC_CIL_H__) +#define __DWC_CIL_H__ + +#include "dwc_otg_plat.h" + +#include "dwc_otg_regs.h" +#ifdef DEBUG +#include "linux/timer.h" +#endif + +/* the OTG capabilities. */ +#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0 +#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1 +#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 +/* the maximum speed of operation in host and device mode. */ +#define DWC_SPEED_PARAM_HIGH 0 +#define DWC_SPEED_PARAM_FULL 1 +/* the PHY clock rate in low power mode when connected to a + * Low Speed device in host mode. */ +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 +/* the type of PHY interface to use. */ +#define DWC_PHY_TYPE_PARAM_FS 0 +#define DWC_PHY_TYPE_PARAM_UTMI 1 +#define DWC_PHY_TYPE_PARAM_ULPI 2 +/* whether to use the internal or external supply to + * drive the vbus with a ULPI phy. */ +#define DWC_PHY_ULPI_INTERNAL_VBUS 0 +#define DWC_PHY_ULPI_EXTERNAL_VBUS 1 +/* EP type. */ + +/** + * @file + * This file contains the interface to the Core Interface Layer. + */ + +/** + * The dwc_ep structure represents the state of a single + * endpoint when acting in device mode. It contains the data items + * needed for an endpoint to be activated and transfer packets. + */ +typedef struct dwc_ep { + /** EP number used for register address lookup */ + uint8_t num; + /** EP direction 0 = OUT */ + unsigned is_in : 1; + /** EP active. */ + unsigned active : 1; + + /** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO + If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/ + unsigned tx_fifo_num : 4; + /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */ + unsigned type : 2; +#define DWC_OTG_EP_TYPE_CONTROL 0 +#define DWC_OTG_EP_TYPE_ISOC 1 +#define DWC_OTG_EP_TYPE_BULK 2 +#define DWC_OTG_EP_TYPE_INTR 3 + + /** DATA start PID for INTR and BULK EP */ + unsigned data_pid_start : 1; + /** Frame (even/odd) for ISOC EP */ + unsigned even_odd_frame : 1; + /** Max Packet bytes */ + unsigned maxpacket : 11; + + /** @name Transfer state */ + /** @{ */ + + /** + * Pointer to the beginning of the transfer buffer -- do not modify + * during transfer. + */ + + uint32_t dma_addr; + + uint8_t *start_xfer_buff; + /** pointer to the transfer buffer */ + uint8_t *xfer_buff; + /** Number of bytes to transfer */ + unsigned xfer_len : 19; + /** Number of bytes transferred. */ + unsigned xfer_count : 19; + /** Sent ZLP */ + unsigned sent_zlp : 1; + /** Total len for control transfer */ + unsigned total_len : 19; + + /** stall clear flag */ + unsigned stall_clear_flag : 1; + + /** @} */ +} dwc_ep_t; + +/* + * Reasons for halting a host channel. + */ +typedef enum dwc_otg_halt_status { + DWC_OTG_HC_XFER_NO_HALT_STATUS, + DWC_OTG_HC_XFER_COMPLETE, + DWC_OTG_HC_XFER_URB_COMPLETE, + DWC_OTG_HC_XFER_ACK, + DWC_OTG_HC_XFER_NAK, + DWC_OTG_HC_XFER_NYET, + DWC_OTG_HC_XFER_STALL, + DWC_OTG_HC_XFER_XACT_ERR, + DWC_OTG_HC_XFER_FRAME_OVERRUN, + DWC_OTG_HC_XFER_BABBLE_ERR, + DWC_OTG_HC_XFER_DATA_TOGGLE_ERR, + DWC_OTG_HC_XFER_AHB_ERR, + DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE, + DWC_OTG_HC_XFER_URB_DEQUEUE +} dwc_otg_halt_status_e; + +/** + * Host channel descriptor. This structure represents the state of a single + * host channel when acting in host mode. It contains the data items needed to + * transfer packets to an endpoint via a host channel. + */ +typedef struct dwc_hc { + /** Host channel number used for register address lookup */ + uint8_t hc_num; + + /** Device to access */ + unsigned dev_addr : 7; + + /** EP to access */ + unsigned ep_num : 4; + + /** EP direction. 0: OUT, 1: IN */ + unsigned ep_is_in : 1; + + /** + * EP speed. + * One of the following values: + * - DWC_OTG_EP_SPEED_LOW + * - DWC_OTG_EP_SPEED_FULL + * - DWC_OTG_EP_SPEED_HIGH + */ + unsigned speed : 2; +#define DWC_OTG_EP_SPEED_LOW 0 +#define DWC_OTG_EP_SPEED_FULL 1 +#define DWC_OTG_EP_SPEED_HIGH 2 + + /** + * Endpoint type. + * One of the following values: + * - DWC_OTG_EP_TYPE_CONTROL: 0 + * - DWC_OTG_EP_TYPE_ISOC: 1 + * - DWC_OTG_EP_TYPE_BULK: 2 + * - DWC_OTG_EP_TYPE_INTR: 3 + */ + unsigned ep_type : 2; + + /** Max packet size in bytes */ + unsigned max_packet : 11; + + /** + * PID for initial transaction. + * 0: DATA0,
+ * 1: DATA2,
+ * 2: DATA1,
+ * 3: MDATA (non-Control EP), + * SETUP (Control EP) + */ + unsigned data_pid_start : 2; +#define DWC_OTG_HC_PID_DATA0 0 +#define DWC_OTG_HC_PID_DATA2 1 +#define DWC_OTG_HC_PID_DATA1 2 +#define DWC_OTG_HC_PID_MDATA 3 +#define DWC_OTG_HC_PID_SETUP 3 + + /** Number of periodic transactions per (micro)frame */ + unsigned multi_count: 2; + + /** @name Transfer State */ + /** @{ */ + + /** Pointer to the current transfer buffer position. */ + uint8_t *xfer_buff; + /** Total number of bytes to transfer. */ + uint32_t xfer_len; + /** Number of bytes transferred so far. */ + uint32_t xfer_count; + /** Packet count at start of transfer.*/ + uint16_t start_pkt_count; + + /** + * Flag to indicate whether the transfer has been started. Set to 1 if + * it has been started, 0 otherwise. + */ + uint8_t xfer_started; + + /** + * Set to 1 to indicate that a PING request should be issued on this + * channel. If 0, process normally. + */ + uint8_t do_ping; + + /** + * Set to 1 to indicate that the error count for this transaction is + * non-zero. Set to 0 if the error count is 0. + */ + uint8_t error_state; + + /** + * Set to 1 to indicate that this channel should be halted the next + * time a request is queued for the channel. This is necessary in + * slave mode if no request queue space is available when an attempt + * is made to halt the channel. + */ + uint8_t halt_on_queue; + + /** + * Set to 1 if the host channel has been halted, but the core is not + * finished flushing queued requests. Otherwise 0. + */ + uint8_t halt_pending; + + /** + * Reason for halting the host channel. + */ + dwc_otg_halt_status_e halt_status; + + /* + * Split settings for the host channel + */ + uint8_t do_split; /**< Enable split for the channel */ + uint8_t complete_split; /**< Enable complete split */ + uint8_t hub_addr; /**< Address of high speed hub */ + + uint8_t port_addr; /**< Port of the low/full speed device */ + /** Split transaction position + * One of the following values: + * - DWC_HCSPLIT_XACTPOS_MID + * - DWC_HCSPLIT_XACTPOS_BEGIN + * - DWC_HCSPLIT_XACTPOS_END + * - DWC_HCSPLIT_XACTPOS_ALL */ + uint8_t xact_pos; + + /** Set when the host channel does a short read. */ + uint8_t short_read; + + /** + * Number of requests issued for this channel since it was assigned to + * the current transfer (not counting PINGs). + */ + uint8_t requests; + + /** + * Queue Head for the transfer being processed by this channel. + */ + struct dwc_otg_qh *qh; + + /** @} */ + + /** Entry in list of host channels. */ + struct list_head hc_list_entry; +} dwc_hc_t; + +/** + * The following parameters may be specified when starting the module. These + * parameters define how the DWC_otg controller should be configured. + * Parameter values are passed to the CIL initialization function + * dwc_otg_cil_init. + */ + +typedef struct dwc_otg_core_params +{ + int32_t opt; +//#define dwc_param_opt_default 1 + /** + * Specifies the OTG capabilities. The driver will automatically + * detect the value for this parameter if none is specified. + * 0 - HNP and SRP capable (default) + * 1 - SRP Only capable + * 2 - No HNP/SRP capable + */ + int32_t otg_cap; +#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0 +#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1 +#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 +//#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE + /** + * Specifies whether to use slave or DMA mode for accessing the data + * FIFOs. The driver will automatically detect the value for this + * parameter if none is specified. + * 0 - Slave + * 1 - DMA (default, if available) + */ + int32_t dma_enable; +//#define dwc_param_dma_enable_default 1 + /** The DMA Burst size (applicable only for External DMA + * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32) + */ + int32_t dma_burst_size; /* Translate this to GAHBCFG values */ +//#define dwc_param_dma_burst_size_default 32 + /** + * Specifies the maximum speed of operation in host and device mode. + * The actual speed depends on the speed of the attached device and + * the value of phy_type. The actual speed depends on the speed of the + * attached device. + * 0 - High Speed (default) + * 1 - Full Speed + */ + int32_t speed; +//#define dwc_param_speed_default 0 +#define DWC_SPEED_PARAM_HIGH 0 +#define DWC_SPEED_PARAM_FULL 1 + + /** Specifies whether low power mode is supported when attached + * to a Full Speed or Low Speed device in host mode. + * 0 - Don't support low power mode (default) + * 1 - Support low power mode + */ + int32_t host_support_fs_ls_low_power; +//#define dwc_param_host_support_fs_ls_low_power_default 0 + /** Specifies the PHY clock rate in low power mode when connected to a + * Low Speed device in host mode. This parameter is applicable only if + * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS + * then defaults to 6 MHZ otherwise 48 MHZ. + * + * 0 - 48 MHz + * 1 - 6 MHz + */ + int32_t host_ls_low_power_phy_clk; +//#define dwc_param_host_ls_low_power_phy_clk_default 0 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 +#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 + /** + * 0 - Use cC FIFO size parameters + * 1 - Allow dynamic FIFO sizing (default) + */ + int32_t enable_dynamic_fifo; +//#define dwc_param_enable_dynamic_fifo_default 1 + /** Total number of 4-byte words in the data FIFO memory. This + * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic + * Tx FIFOs. + * 32 to 32768 (default 8192) + * Note: The total FIFO memory depth in the FPGA configuration is 8192. + */ + int32_t data_fifo_size; +//#define dwc_param_data_fifo_size_default 8192 + /** Number of 4-byte words in the Rx FIFO in device mode when dynamic + * FIFO sizing is enabled. + * 16 to 32768 (default 1064) + */ + int32_t dev_rx_fifo_size; +//#define dwc_param_dev_rx_fifo_size_default 1064 + /** Number of 4-byte words in the non-periodic Tx FIFO in device mode + * when dynamic FIFO sizing is enabled. + * 16 to 32768 (default 1024) + */ + int32_t dev_nperio_tx_fifo_size; +//#define dwc_param_dev_nperio_tx_fifo_size_default 1024 + /** Number of 4-byte words in each of the periodic Tx FIFOs in device + * mode when dynamic FIFO sizing is enabled. + * 4 to 768 (default 256) + */ + uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS]; +//#define dwc_param_dev_perio_tx_fifo_size_default 256 + /** Number of 4-byte words in the Rx FIFO in host mode when dynamic + * FIFO sizing is enabled. + * 16 to 32768 (default 1024) + */ + int32_t host_rx_fifo_size; +//#define dwc_param_host_rx_fifo_size_default 1024 + /** Number of 4-byte words in the non-periodic Tx FIFO in host mode + * when Dynamic FIFO sizing is enabled in the core. + * 16 to 32768 (default 1024) + */ + int32_t host_nperio_tx_fifo_size; +//#define dwc_param_host_nperio_tx_fifo_size_default 1024 + /** Number of 4-byte words in the host periodic Tx FIFO when dynamic + * FIFO sizing is enabled. + * 16 to 32768 (default 1024) + */ + int32_t host_perio_tx_fifo_size; +//#define dwc_param_host_perio_tx_fifo_size_default 1024 + /** The maximum transfer size supported in bytes. + * 2047 to 65,535 (default 65,535) + */ + int32_t max_transfer_size; +//#define dwc_param_max_transfer_size_default 65535 + /** The maximum number of packets in a transfer. + * 15 to 511 (default 511) + */ + int32_t max_packet_count; +//#define dwc_param_max_packet_count_default 511 + /** The number of host channel registers to use. + * 1 to 16 (default 12) + * Note: The FPGA configuration supports a maximum of 12 host channels. + */ + int32_t host_channels; +//#define dwc_param_host_channels_default 12 + /** The number of endpoints in addition to EP0 available for device + * mode operations. + * 1 to 15 (default 6 IN and OUT) + * Note: The FPGA configuration supports a maximum of 6 IN and OUT + * endpoints in addition to EP0. + */ + int32_t dev_endpoints; +//#define dwc_param_dev_endpoints_default 6 + /** + * Specifies the type of PHY interface to use. By default, the driver + * will automatically detect the phy_type. + * + * 0 - Full Speed PHY + * 1 - UTMI+ (default) + * 2 - ULPI + */ + int32_t phy_type; +#define DWC_PHY_TYPE_PARAM_FS 0 +#define DWC_PHY_TYPE_PARAM_UTMI 1 +#define DWC_PHY_TYPE_PARAM_ULPI 2 +//#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI + /** + * Specifies the UTMI+ Data Width. This parameter is + * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI + * PHY_TYPE, this parameter indicates the data width between + * the MAC and the ULPI Wrapper.) Also, this parameter is + * applicable only if the OTG_HSPHY_WIDTH cC parameter was set + * to "8 and 16 bits", meaning that the core has been + * configured to work at either data path width. + * + * 8 or 16 bits (default 16) + */ + int32_t phy_utmi_width; +//#define dwc_param_phy_utmi_width_default 16 + /** + * Specifies whether the ULPI operates at double or single + * data rate. This parameter is only applicable if PHY_TYPE is + * ULPI. + * + * 0 - single data rate ULPI interface with 8 bit wide data + * bus (default) + * 1 - double data rate ULPI interface with 4 bit wide data + * bus + */ + int32_t phy_ulpi_ddr; +//#define dwc_param_phy_ulpi_ddr_default 0 + /** + * Specifies whether to use the internal or external supply to + * drive the vbus with a ULPI phy. + */ + int32_t phy_ulpi_ext_vbus; +#define DWC_PHY_ULPI_INTERNAL_VBUS 0 +#define DWC_PHY_ULPI_EXTERNAL_VBUS 1 +//#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS + /** + * Specifies whether to use the I2Cinterface for full speed PHY. This + * parameter is only applicable if PHY_TYPE is FS. + * 0 - No (default) + * 1 - Yes + */ + int32_t i2c_enable; +//#define dwc_param_i2c_enable_default 0 + + int32_t ulpi_fs_ls; +//#define dwc_param_ulpi_fs_ls_default 0 + + int32_t ts_dline; +//#define dwc_param_ts_dline_default 0 + + /** + * Specifies whether dedicated transmit FIFOs are + * enabled for non periodic IN endpoints in device mode + * 0 - No + * 1 - Yes + */ + int32_t en_multiple_tx_fifo; +#define dwc_param_en_multiple_tx_fifo_default 1 + + /** Number of 4-byte words in each of the Tx FIFOs in device + * mode when dynamic FIFO sizing is enabled. + * 4 to 768 (default 256) + */ + uint32_t dev_tx_fifo_size[MAX_TX_FIFOS]; +#define dwc_param_dev_tx_fifo_size_default 256 + + /** Thresholding enable flag- + * bit 0 - enable non-ISO Tx thresholding + * bit 1 - enable ISO Tx thresholding + * bit 2 - enable Rx thresholding + */ + uint32_t thr_ctl; +#define dwc_param_thr_ctl_default 0 + + /** Thresholding length for Tx + * FIFOs in 32 bit DWORDs + */ + uint32_t tx_thr_length; +#define dwc_param_tx_thr_length_default 64 + + /** Thresholding length for Rx + * FIFOs in 32 bit DWORDs + */ + uint32_t rx_thr_length; +#define dwc_param_rx_thr_length_default 64 +} dwc_otg_core_params_t; + +#ifdef DEBUG +struct dwc_otg_core_if; +typedef struct hc_xfer_info +{ + struct dwc_otg_core_if *core_if; + dwc_hc_t *hc; +} hc_xfer_info_t; +#endif + +/** + * The dwc_otg_core_if structure contains information needed to manage + * the DWC_otg controller acting in either host or device mode. It + * represents the programming view of the controller as a whole. + */ +typedef struct dwc_otg_core_if +{ + /** Parameters that define how the core should be configured.*/ + dwc_otg_core_params_t *core_params; + + /** Core Global registers starting at offset 000h. */ + dwc_otg_core_global_regs_t *core_global_regs; + + /** Device-specific information */ + dwc_otg_dev_if_t *dev_if; + /** Host-specific information */ + dwc_otg_host_if_t *host_if; + + /* + * Set to 1 if the core PHY interface bits in USBCFG have been + * initialized. + */ + uint8_t phy_init_done; + + /* + * SRP Success flag, set by srp success interrupt in FS I2C mode + */ + uint8_t srp_success; + uint8_t srp_timer_started; + + /* Common configuration information */ + /** Power and Clock Gating Control Register */ + volatile uint32_t *pcgcctl; +#define DWC_OTG_PCGCCTL_OFFSET 0xE00 + + /** Push/pop addresses for endpoints or host channels.*/ + uint32_t *data_fifo[MAX_EPS_CHANNELS]; +#define DWC_OTG_DATA_FIFO_OFFSET 0x1000 +#define DWC_OTG_DATA_FIFO_SIZE 0x1000 + + /** Total RAM for FIFOs (Bytes) */ + uint16_t total_fifo_size; + /** Size of Rx FIFO (Bytes) */ + uint16_t rx_fifo_size; + /** Size of Non-periodic Tx FIFO (Bytes) */ + uint16_t nperio_tx_fifo_size; + + /** 1 if DMA is enabled, 0 otherwise. */ + uint8_t dma_enable; + + /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */ + uint8_t en_multiple_tx_fifo; + + /** Set to 1 if multiple packets of a high-bandwidth transfer is in + * process of being queued */ + uint8_t queuing_high_bandwidth; + + /** Hardware Configuration -- stored here for convenience.*/ + hwcfg1_data_t hwcfg1; + hwcfg2_data_t hwcfg2; + hwcfg3_data_t hwcfg3; + hwcfg4_data_t hwcfg4; + + /** The operational State, during transations + * (a_host>>a_peripherial and b_device=>b_host) this may not + * match the core but allows the software to determine + * transitions. + */ + uint8_t op_state; + + /** + * Set to 1 if the HCD needs to be restarted on a session request + * interrupt. This is required if no connector ID status change has + * occurred since the HCD was last disconnected. + */ + uint8_t restart_hcd_on_session_req; + + /** HCD callbacks */ + /** A-Device is a_host */ +#define A_HOST (1) + /** A-Device is a_suspend */ +#define A_SUSPEND (2) + /** A-Device is a_peripherial */ +#define A_PERIPHERAL (3) + /** B-Device is operating as a Peripheral. */ +#define B_PERIPHERAL (4) + /** B-Device is operating as a Host. */ +#define B_HOST (5) + + /** HCD callbacks */ + struct dwc_otg_cil_callbacks *hcd_cb; + /** PCD callbacks */ + struct dwc_otg_cil_callbacks *pcd_cb; + + /** Device mode Periodic Tx FIFO Mask */ + uint32_t p_tx_msk; + /** Device mode Periodic Tx FIFO Mask */ + uint32_t tx_msk; + +#ifdef DEBUG + uint32_t start_hcchar_val[MAX_EPS_CHANNELS]; + + hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS]; + struct timer_list hc_xfer_timer[MAX_EPS_CHANNELS]; + +#if 1 // winder + uint32_t hfnum_7_samples; + uint32_t hfnum_7_frrem_accum; + uint32_t hfnum_0_samples; + uint32_t hfnum_0_frrem_accum; + uint32_t hfnum_other_samples; + uint32_t hfnum_other_frrem_accum; +#else + uint32_t hfnum_7_samples; + uint64_t hfnum_7_frrem_accum; + uint32_t hfnum_0_samples; + uint64_t hfnum_0_frrem_accum; + uint32_t hfnum_other_samples; + uint64_t hfnum_other_frrem_accum; +#endif + resource_size_t phys_addr; /* Added to support PLB DMA : phys-virt mapping */ +#endif + +} dwc_otg_core_if_t; + +/* + * The following functions support initialization of the CIL driver component + * and the DWC_otg controller. + */ +extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr, + dwc_otg_core_params_t *_core_params); +extern void dwc_otg_cil_remove(dwc_otg_core_if_t *_core_if); +extern void dwc_otg_core_init(dwc_otg_core_if_t *_core_if); +extern void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if); +extern void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if); +extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if ); +extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if ); + +/** @name Device CIL Functions + * The following functions support managing the DWC_otg controller in device + * mode. + */ +/**@{*/ +extern void dwc_otg_wakeup(dwc_otg_core_if_t *_core_if); +extern void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest); +extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if); +extern void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); +extern void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); +extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); +extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); +extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); +extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); +extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma); +extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); +extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); +extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if); +extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if); +/**@}*/ + +/** @name Host CIL Functions + * The following functions support managing the DWC_otg controller in host + * mode. + */ +/**@{*/ +extern void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); +extern void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if, + dwc_hc_t *_hc, + dwc_otg_halt_status_e _halt_status); +extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); +extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); +extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); +extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); +extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); +extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if); +extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if); + +/** + * This function Reads HPRT0 in preparation to modify. It keeps the + * WC bits 0 so that if they are read as 1, they won't clear when you + * write it back + */ +static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t *_core_if) +{ + hprt0_data_t hprt0; + hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0); + hprt0.b.prtena = 0; + hprt0.b.prtconndet = 0; + hprt0.b.prtenchng = 0; + hprt0.b.prtovrcurrchng = 0; + return hprt0.d32; +} + +extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if); +/**@}*/ + +/** @name Common CIL Functions + * The following functions support managing the DWC_otg controller in either + * device or host mode. + */ +/**@{*/ + +extern void dwc_otg_read_packet(dwc_otg_core_if_t *core_if, + uint8_t *dest, + uint16_t bytes); + +extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if); + +extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if, + const int _num ); +extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if ); +extern void dwc_otg_core_reset( dwc_otg_core_if_t *_core_if ); + +#define NP_TXFIFO_EMPTY -1 +#define MAX_NP_TXREQUEST_Q_SLOTS 8 +/** + * This function returns the endpoint number of the request at + * the top of non-periodic TX FIFO, or -1 if the request FIFO is + * empty. + */ +static inline int dwc_otg_top_nptxfifo_epnum(dwc_otg_core_if_t *_core_if) { + gnptxsts_data_t txstatus = {.d32 = 0}; + + txstatus.d32 = dwc_read_reg32(&_core_if->core_global_regs->gnptxsts); + return (txstatus.b.nptxqspcavail == MAX_NP_TXREQUEST_Q_SLOTS ? + -1 : txstatus.b.nptxqtop_chnep); +} +/** + * This function returns the Core Interrupt register. + */ +static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t *_core_if) { + return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) & + dwc_read_reg32(&_core_if->core_global_regs->gintmsk)); +} + +/** + * This function returns the OTG Interrupt register. + */ +static inline uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *_core_if) { + return (dwc_read_reg32 (&_core_if->core_global_regs->gotgint)); +} + +/** + * This function reads the Device All Endpoints Interrupt register and + * returns the IN endpoint interrupt bits. + */ +static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *_core_if) { + uint32_t v; + v = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daint) & + dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk); + return (v & 0xffff); + +} + +/** + * This function reads the Device All Endpoints Interrupt register and + * returns the OUT endpoint interrupt bits. + */ +static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *_core_if) { + uint32_t v; + v = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daint) & + dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk); + return ((v & 0xffff0000) >> 16); +} + +/** + * This function returns the Device IN EP Interrupt register + */ +static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t *_core_if, + dwc_ep_t *_ep) +{ + dwc_otg_dev_if_t *dev_if = _core_if->dev_if; + uint32_t v, msk, emp; + msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk); + emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk); + msk |= ((emp >> _ep->num) & 0x1) << 7; + v = dwc_read_reg32(&dev_if->in_ep_regs[_ep->num]->diepint) & msk; +/* + dwc_otg_dev_if_t *dev_if = _core_if->dev_if; + uint32_t v; + v = dwc_read_reg32(&dev_if->in_ep_regs[_ep->num]->diepint) & + dwc_read_reg32(&dev_if->dev_global_regs->diepmsk); +*/ + return v; +} +/** + * This function returns the Device OUT EP Interrupt register + */ +static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *_core_if, + dwc_ep_t *_ep) +{ + dwc_otg_dev_if_t *dev_if = _core_if->dev_if; + uint32_t v; + v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) & + dwc_read_reg32(&dev_if->dev_global_regs->doepmsk); + return v; +} + +/** + * This function returns the Host All Channel Interrupt register + */ +static inline uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if) +{ + return (dwc_read_reg32 (&_core_if->host_if->host_global_regs->haint)); +} + +static inline uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) +{ + return (dwc_read_reg32 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint)); +} + + +/** + * This function returns the mode of the operation, host or device. + * + * @return 0 - Device Mode, 1 - Host Mode + */ +static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t *_core_if) { + return (dwc_read_reg32( &_core_if->core_global_regs->gintsts ) & 0x1); +} + +static inline uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t *_core_if) +{ + return (dwc_otg_mode(_core_if) != DWC_HOST_MODE); +} +static inline uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t *_core_if) +{ + return (dwc_otg_mode(_core_if) == DWC_HOST_MODE); +} + +extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if ); + + +/**@}*/ + +/** + * DWC_otg CIL callback structure. This structure allows the HCD and + * PCD to register functions used for starting and stopping the PCD + * and HCD for role change on for a DRD. + */ +typedef struct dwc_otg_cil_callbacks +{ + /** Start function for role change */ + int (*start) (void *_p); + /** Stop Function for role change */ + int (*stop) (void *_p); + /** Disconnect Function for role change */ + int (*disconnect) (void *_p); + /** Resume/Remote wakeup Function */ + int (*resume_wakeup) (void *_p); + /** Suspend function */ + int (*suspend) (void *_p); + /** Session Start (SRP) */ + int (*session_start) (void *_p); + /** Pointer passed to start() and stop() */ + void *p; +} dwc_otg_cil_callbacks_t; + + + +extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if, + dwc_otg_cil_callbacks_t *_cb, + void *_p); +extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if, + dwc_otg_cil_callbacks_t *_cb, + void *_p); + + +#endif diff --git a/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h new file mode 100644 index 0000000000..b0298ec2ea --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h @@ -0,0 +1,58 @@ +/****************************************************************************** +** +** FILE NAME : dwc_otg_cil_ifx.h +** PROJECT : Twinpass/Danube +** MODULES : DWC OTG USB +** +** DATE : 07 Sep. 2007 +** AUTHOR : Sung Winder +** DESCRIPTION : Default param value. +** COPYRIGHT : Copyright (c) 2007 +** Infineon Technologies AG +** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park, +** Hsin-chu City, 300 Taiwan. +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 12 April 2007 Sung Winder Initiate Version +*******************************************************************************/ +#if !defined(__DWC_OTG_CIL_IFX_H__) +#define __DWC_OTG_CIL_IFX_H__ + +/* ================ Default param value ================== */ +#define dwc_param_opt_default 1 +#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE +#define dwc_param_dma_enable_default 1 +#define dwc_param_dma_burst_size_default 32 +#define dwc_param_speed_default DWC_SPEED_PARAM_HIGH +#define dwc_param_host_support_fs_ls_low_power_default 0 +#define dwc_param_host_ls_low_power_phy_clk_default DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ +#define dwc_param_enable_dynamic_fifo_default 1 +#define dwc_param_data_fifo_size_default 2048 +#define dwc_param_dev_rx_fifo_size_default 1024 +#define dwc_param_dev_nperio_tx_fifo_size_default 1024 +#define dwc_param_dev_perio_tx_fifo_size_default 768 +#define dwc_param_host_rx_fifo_size_default 640 +#define dwc_param_host_nperio_tx_fifo_size_default 640 +#define dwc_param_host_perio_tx_fifo_size_default 768 +#define dwc_param_max_transfer_size_default 65535 +#define dwc_param_max_packet_count_default 511 +#define dwc_param_host_channels_default 16 +#define dwc_param_dev_endpoints_default 6 +#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI +#define dwc_param_phy_utmi_width_default 16 +#define dwc_param_phy_ulpi_ddr_default 0 +#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS +#define dwc_param_i2c_enable_default 0 +#define dwc_param_ulpi_fs_ls_default 0 +#define dwc_param_ts_dline_default 0 + +/* ======================================================= */ + +#endif // __DWC_OTG_CIL_IFX_H__ + diff --git a/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil_intr.c b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil_intr.c new file mode 100644 index 0000000000..d469ab46b0 --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_cil_intr.c @@ -0,0 +1,708 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil_intr.c $ + * $Revision: 1.1.1.1 $ + * $Date: 2009-04-17 06:15:34 $ + * $Change: 553126 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ + +/** @file + * + * The Core Interface Layer provides basic services for accessing and + * managing the DWC_otg hardware. These services are used by both the + * Host Controller Driver and the Peripheral Controller Driver. + * + * This file contains the Common Interrupt handlers. + */ +#include "dwc_otg_plat.h" +#include "dwc_otg_regs.h" +#include "dwc_otg_cil.h" + +#ifdef DEBUG +inline const char *op_state_str( dwc_otg_core_if_t *_core_if ) +{ + return (_core_if->op_state==A_HOST?"a_host": + (_core_if->op_state==A_SUSPEND?"a_suspend": + (_core_if->op_state==A_PERIPHERAL?"a_peripheral": + (_core_if->op_state==B_PERIPHERAL?"b_peripheral": + (_core_if->op_state==B_HOST?"b_host": + "unknown"))))); +} +#endif + +/** This function will log a debug message + * + * @param _core_if Programming view of DWC_otg controller. + */ +int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *_core_if) +{ + gintsts_data_t gintsts; + DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n", + dwc_otg_mode(_core_if) ? "Host" : "Device"); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.modemismatch = 1; + dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32); + return 1; +} + +/** Start the HCD. Helper function for using the HCD callbacks. + * + * @param _core_if Programming view of DWC_otg controller. + */ +static inline void hcd_start( dwc_otg_core_if_t *_core_if ) +{ + if (_core_if->hcd_cb && _core_if->hcd_cb->start) { + _core_if->hcd_cb->start( _core_if->hcd_cb->p ); + } +} +/** Stop the HCD. Helper function for using the HCD callbacks. + * + * @param _core_if Programming view of DWC_otg controller. + */ +static inline void hcd_stop( dwc_otg_core_if_t *_core_if ) +{ + if (_core_if->hcd_cb && _core_if->hcd_cb->stop) { + _core_if->hcd_cb->stop( _core_if->hcd_cb->p ); + } +} +/** Disconnect the HCD. Helper function for using the HCD callbacks. + * + * @param _core_if Programming view of DWC_otg controller. + */ +static inline void hcd_disconnect( dwc_otg_core_if_t *_core_if ) +{ + if (_core_if->hcd_cb && _core_if->hcd_cb->disconnect) { + _core_if->hcd_cb->disconnect( _core_if->hcd_cb->p ); + } +} +/** Inform the HCD the a New Session has begun. Helper function for + * using the HCD callbacks. + * + * @param _core_if Programming view of DWC_otg controller. + */ +static inline void hcd_session_start( dwc_otg_core_if_t *_core_if ) +{ + if (_core_if->hcd_cb && _core_if->hcd_cb->session_start) { + _core_if->hcd_cb->session_start( _core_if->hcd_cb->p ); + } +} + +/** Start the PCD. Helper function for using the PCD callbacks. + * + * @param _core_if Programming view of DWC_otg controller. + */ +static inline void pcd_start( dwc_otg_core_if_t *_core_if ) +{ + if (_core_if->pcd_cb && _core_if->pcd_cb->start ) { + _core_if->pcd_cb->start( _core_if->pcd_cb->p ); + } +} +/** Stop the PCD. Helper function for using the PCD callbacks. + * + * @param _core_if Programming view of DWC_otg controller. + */ +static inline void pcd_stop( dwc_otg_core_if_t *_core_if ) +{ + if (_core_if->pcd_cb && _core_if->pcd_cb->stop ) { + _core_if->pcd_cb->stop( _core_if->pcd_cb->p ); + } +} +/** Suspend the PCD. Helper function for using the PCD callbacks. + * + * @param _core_if Programming view of DWC_otg controller. + */ +static inline void pcd_suspend( dwc_otg_core_if_t *_core_if ) +{ + if (_core_if->pcd_cb && _core_if->pcd_cb->suspend ) { + _core_if->pcd_cb->suspend( _core_if->pcd_cb->p ); + } +} +/** Resume the PCD. Helper function for using the PCD callbacks. + * + * @param _core_if Programming view of DWC_otg controller. + */ +static inline void pcd_resume( dwc_otg_core_if_t *_core_if ) +{ + if (_core_if->pcd_cb && _core_if->pcd_cb->resume_wakeup ) { + _core_if->pcd_cb->resume_wakeup( _core_if->pcd_cb->p ); + } +} + +/** + * This function handles the OTG Interrupts. It reads the OTG + * Interrupt Register (GOTGINT) to determine what interrupt has + * occurred. + * + * @param _core_if Programming view of DWC_otg controller. + */ +int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t *_core_if) +{ + dwc_otg_core_global_regs_t *global_regs = + _core_if->core_global_regs; + gotgint_data_t gotgint; + gotgctl_data_t gotgctl; + gintmsk_data_t gintmsk; + + gotgint.d32 = dwc_read_reg32( &global_regs->gotgint); + gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl); + DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32, + op_state_str(_core_if)); + //DWC_DEBUGPL(DBG_CIL, "gotgctl=%08x\n", gotgctl.d32 ); + + if (gotgint.b.sesenddet) { + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " + "Session End Detected++ (%s)\n", + op_state_str(_core_if)); + gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl); + + if (_core_if->op_state == B_HOST) { + pcd_start( _core_if ); + _core_if->op_state = B_PERIPHERAL; + } else { + /* If not B_HOST and Device HNP still set. HNP + * Did not succeed!*/ + if (gotgctl.b.devhnpen) { + DWC_DEBUGPL(DBG_ANY, "Session End Detected\n"); + DWC_ERROR( "Device Not Connected/Responding!\n" ); + } + + /* If Session End Detected the B-Cable has + * been disconnected. */ + /* Reset PCD and Gadget driver to a + * clean state. */ + pcd_stop(_core_if); + } + gotgctl.d32 = 0; + gotgctl.b.devhnpen = 1; + dwc_modify_reg32( &global_regs->gotgctl, + gotgctl.d32, 0); + } + if (gotgint.b.sesreqsucstschng) { + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " + "Session Reqeust Success Status Change++\n"); + gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl); + if (gotgctl.b.sesreqscs) { + if ((_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) && + (_core_if->core_params->i2c_enable)) { + _core_if->srp_success = 1; + } + else { + pcd_resume( _core_if ); + /* Clear Session Request */ + gotgctl.d32 = 0; + gotgctl.b.sesreq = 1; + dwc_modify_reg32( &global_regs->gotgctl, + gotgctl.d32, 0); + } + } + } + if (gotgint.b.hstnegsucstschng) { + /* Print statements during the HNP interrupt handling + * can cause it to fail.*/ + gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); + if (gotgctl.b.hstnegscs) { + if (dwc_otg_is_host_mode(_core_if) ) { + _core_if->op_state = B_HOST; + /* + * Need to disable SOF interrupt immediately. + * When switching from device to host, the PCD + * interrupt handler won't handle the + * interrupt if host mode is already set. The + * HCD interrupt handler won't get called if + * the HCD state is HALT. This means that the + * interrupt does not get handled and Linux + * complains loudly. + */ + gintmsk.d32 = 0; + gintmsk.b.sofintr = 1; + dwc_modify_reg32(&global_regs->gintmsk, + gintmsk.d32, 0); + pcd_stop(_core_if); + /* + * Initialize the Core for Host mode. + */ + hcd_start( _core_if ); + _core_if->op_state = B_HOST; + } + } else { + gotgctl.d32 = 0; + gotgctl.b.hnpreq = 1; + gotgctl.b.devhnpen = 1; + dwc_modify_reg32( &global_regs->gotgctl, + gotgctl.d32, 0); + DWC_DEBUGPL( DBG_ANY, "HNP Failed\n"); + DWC_ERROR( "Device Not Connected/Responding\n" ); + } + } + if (gotgint.b.hstnegdet) { + /* The disconnect interrupt is set at the same time as + * Host Negotiation Detected. During the mode + * switch all interrupts are cleared so the disconnect + * interrupt handler will not get executed. + */ + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " + "Host Negotiation Detected++ (%s)\n", + (dwc_otg_is_host_mode(_core_if)?"Host":"Device")); + if (dwc_otg_is_device_mode(_core_if)){ + DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",_core_if->op_state); + hcd_disconnect( _core_if ); + pcd_start( _core_if ); + _core_if->op_state = A_PERIPHERAL; + } else { + /* + * Need to disable SOF interrupt immediately. When + * switching from device to host, the PCD interrupt + * handler won't handle the interrupt if host mode is + * already set. The HCD interrupt handler won't get + * called if the HCD state is HALT. This means that + * the interrupt does not get handled and Linux + * complains loudly. + */ + gintmsk.d32 = 0; + gintmsk.b.sofintr = 1; + dwc_modify_reg32(&global_regs->gintmsk, + gintmsk.d32, 0); + pcd_stop( _core_if ); + hcd_start( _core_if ); + _core_if->op_state = A_HOST; + } + } + if (gotgint.b.adevtoutchng) { + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " + "A-Device Timeout Change++\n"); + } + if (gotgint.b.debdone) { + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " + "Debounce Done++\n"); + } + + /* Clear GOTGINT */ + dwc_write_reg32 (&_core_if->core_global_regs->gotgint, gotgint.d32); + + return 1; +} + +/** + * This function handles the Connector ID Status Change Interrupt. It + * reads the OTG Interrupt Register (GOTCTL) to determine whether this + * is a Device to Host Mode transition or a Host Mode to Device + * Transition. + * + * This only occurs when the cable is connected/removed from the PHY + * connector. + * + * @param _core_if Programming view of DWC_otg controller. + */ +int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t *_core_if) +{ + uint32_t count = 0; + + gintsts_data_t gintsts = { .d32 = 0 }; + gintmsk_data_t gintmsk = { .d32 = 0 }; + gotgctl_data_t gotgctl = { .d32 = 0 }; + + /* + * Need to disable SOF interrupt immediately. If switching from device + * to host, the PCD interrupt handler won't handle the interrupt if + * host mode is already set. The HCD interrupt handler won't get + * called if the HCD state is HALT. This means that the interrupt does + * not get handled and Linux complains loudly. + */ + gintmsk.b.sofintr = 1; + dwc_modify_reg32(&_core_if->core_global_regs->gintmsk, gintmsk.d32, 0); + + DWC_DEBUGPL(DBG_CIL, " ++Connector ID Status Change Interrupt++ (%s)\n", + (dwc_otg_is_host_mode(_core_if)?"Host":"Device")); + gotgctl.d32 = dwc_read_reg32(&_core_if->core_global_regs->gotgctl); + DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32); + DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts); + + /* B-Device connector (Device Mode) */ + if (gotgctl.b.conidsts) { + /* Wait for switch to device mode. */ + while (!dwc_otg_is_device_mode(_core_if) ){ + DWC_PRINT("Waiting for Peripheral Mode, Mode=%s\n", + (dwc_otg_is_host_mode(_core_if)?"Host":"Peripheral")); + MDELAY(100); + if (++count > 10000) *(uint32_t*)NULL=0; + } + _core_if->op_state = B_PERIPHERAL; + dwc_otg_core_init(_core_if); + dwc_otg_enable_global_interrupts(_core_if); + pcd_start( _core_if ); + } else { + /* A-Device connector (Host Mode) */ + while (!dwc_otg_is_host_mode(_core_if) ) { + DWC_PRINT("Waiting for Host Mode, Mode=%s\n", + (dwc_otg_is_host_mode(_core_if)?"Host":"Peripheral")); + MDELAY(100); + if (++count > 10000) *(uint32_t*)NULL=0; + } + _core_if->op_state = A_HOST; + /* + * Initialize the Core for Host mode. + */ + dwc_otg_core_init(_core_if); + dwc_otg_enable_global_interrupts(_core_if); + hcd_start( _core_if ); + } + + /* Set flag and clear interrupt */ + gintsts.b.conidstschng = 1; + dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32); + + return 1; +} + +/** + * This interrupt indicates that a device is initiating the Session + * Request Protocol to request the host to turn on bus power so a new + * session can begin. The handler responds by turning on bus power. If + * the DWC_otg controller is in low power mode, the handler brings the + * controller out of low power mode before turning on bus power. + * + * @param _core_if Programming view of DWC_otg controller. + */ +int32_t dwc_otg_handle_session_req_intr( dwc_otg_core_if_t *_core_if ) +{ +#ifndef DWC_HOST_ONLY // winder + hprt0_data_t hprt0; +#endif + gintsts_data_t gintsts; + +#ifndef DWC_HOST_ONLY + DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n"); + + if (dwc_otg_is_device_mode(_core_if) ) { + DWC_PRINT("SRP: Device mode\n"); + } else { + DWC_PRINT("SRP: Host mode\n"); + + /* Turn on the port power bit. */ + hprt0.d32 = dwc_otg_read_hprt0( _core_if ); + hprt0.b.prtpwr = 1; + dwc_write_reg32(_core_if->host_if->hprt0, hprt0.d32); + + /* Start the Connection timer. So a message can be displayed + * if connect does not occur within 10 seconds. */ + hcd_session_start( _core_if ); + } +#endif + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.sessreqintr = 1; + dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32); + + return 1; +} + +/** + * This interrupt indicates that the DWC_otg controller has detected a + * resume or remote wakeup sequence. If the DWC_otg controller is in + * low power mode, the handler must brings the controller out of low + * power mode. The controller automatically begins resume + * signaling. The handler schedules a time to stop resume signaling. + */ +int32_t dwc_otg_handle_wakeup_detected_intr( dwc_otg_core_if_t *_core_if ) +{ + gintsts_data_t gintsts; + + DWC_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n"); + + if (dwc_otg_is_device_mode(_core_if) ) { + dctl_data_t dctl = {.d32=0}; + DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", + dwc_read_reg32( &_core_if->dev_if->dev_global_regs->dsts)); +#ifdef PARTIAL_POWER_DOWN + if (_core_if->hwcfg4.b.power_optimiz) { + pcgcctl_data_t power = {.d32=0}; + + power.d32 = dwc_read_reg32( _core_if->pcgcctl ); + DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", power.d32); + + power.b.stoppclk = 0; + dwc_write_reg32( _core_if->pcgcctl, power.d32); + + power.b.pwrclmp = 0; + dwc_write_reg32( _core_if->pcgcctl, power.d32); + + power.b.rstpdwnmodule = 0; + dwc_write_reg32( _core_if->pcgcctl, power.d32); + } +#endif + /* Clear the Remote Wakeup Signalling */ + dctl.b.rmtwkupsig = 1; + dwc_modify_reg32( &_core_if->dev_if->dev_global_regs->dctl, + dctl.d32, 0 ); + + if (_core_if->pcd_cb && _core_if->pcd_cb->resume_wakeup) { + _core_if->pcd_cb->resume_wakeup( _core_if->pcd_cb->p ); + } + + } else { + /* + * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms + * so that OPT tests pass with all PHYs). + */ + hprt0_data_t hprt0 = {.d32=0}; + pcgcctl_data_t pcgcctl = {.d32=0}; + /* Restart the Phy Clock */ + pcgcctl.b.stoppclk = 1; + dwc_modify_reg32(_core_if->pcgcctl, pcgcctl.d32, 0); + UDELAY(10); + + /* Now wait for 70 ms. */ + hprt0.d32 = dwc_otg_read_hprt0( _core_if ); + DWC_DEBUGPL(DBG_ANY,"Resume: HPRT0=%0x\n", hprt0.d32); + MDELAY(70); + hprt0.b.prtres = 0; /* Resume */ + dwc_write_reg32(_core_if->host_if->hprt0, hprt0.d32); + DWC_DEBUGPL(DBG_ANY,"Clear Resume: HPRT0=%0x\n", dwc_read_reg32(_core_if->host_if->hprt0)); + } + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.wkupintr = 1; + dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32); + + return 1; +} + +/** + * This interrupt indicates that a device has been disconnected from + * the root port. + */ +int32_t dwc_otg_handle_disconnect_intr( dwc_otg_core_if_t *_core_if) +{ + gintsts_data_t gintsts; + + DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n", + (dwc_otg_is_host_mode(_core_if)?"Host":"Device"), + op_state_str(_core_if)); + +/** @todo Consolidate this if statement. */ +#ifndef DWC_HOST_ONLY + if (_core_if->op_state == B_HOST) { + /* If in device mode Disconnect and stop the HCD, then + * start the PCD. */ + hcd_disconnect( _core_if ); + pcd_start( _core_if ); + _core_if->op_state = B_PERIPHERAL; + } else if (dwc_otg_is_device_mode(_core_if)) { + gotgctl_data_t gotgctl = { .d32 = 0 }; + gotgctl.d32 = dwc_read_reg32(&_core_if->core_global_regs->gotgctl); + if (gotgctl.b.hstsethnpen==1) { + /* Do nothing, if HNP in process the OTG + * interrupt "Host Negotiation Detected" + * interrupt will do the mode switch. + */ + } else if (gotgctl.b.devhnpen == 0) { + /* If in device mode Disconnect and stop the HCD, then + * start the PCD. */ + hcd_disconnect( _core_if ); + pcd_start( _core_if ); + _core_if->op_state = B_PERIPHERAL; + } else { + DWC_DEBUGPL(DBG_ANY,"!a_peripheral && !devhnpen\n"); + } + } else { + if (_core_if->op_state == A_HOST) { + /* A-Cable still connected but device disconnected. */ + hcd_disconnect( _core_if ); + } + } +#endif +/* Without OTG, we should use the disconnect function!? winder added.*/ +#if 1 // NO OTG, so host only!! + hcd_disconnect( _core_if ); +#endif + + gintsts.d32 = 0; + gintsts.b.disconnect = 1; + dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32); + return 1; +} +/** + * This interrupt indicates that SUSPEND state has been detected on + * the USB. + * + * For HNP the USB Suspend interrupt signals the change from + * "a_peripheral" to "a_host". + * + * When power management is enabled the core will be put in low power + * mode. + */ +int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t *_core_if ) +{ + dsts_data_t dsts; + gintsts_data_t gintsts; + + //805141:.removed DWC_DEBUGPL(DBG_ANY,"USB SUSPEND\n"); + + if (dwc_otg_is_device_mode( _core_if ) ) { + /* Check the Device status register to determine if the Suspend + * state is active. */ + dsts.d32 = dwc_read_reg32( &_core_if->dev_if->dev_global_regs->dsts); + DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32); + DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d " + "HWCFG4.power Optimize=%d\n", + dsts.b.suspsts, _core_if->hwcfg4.b.power_optimiz); + + +#ifdef PARTIAL_POWER_DOWN +/** @todo Add a module parameter for power management. */ + + if (dsts.b.suspsts && _core_if->hwcfg4.b.power_optimiz) { + pcgcctl_data_t power = {.d32=0}; + DWC_DEBUGPL(DBG_CIL, "suspend\n"); + + power.b.pwrclmp = 1; + dwc_write_reg32( _core_if->pcgcctl, power.d32); + + power.b.rstpdwnmodule = 1; + dwc_modify_reg32( _core_if->pcgcctl, 0, power.d32); + + power.b.stoppclk = 1; + dwc_modify_reg32( _core_if->pcgcctl, 0, power.d32); + + } else { + DWC_DEBUGPL(DBG_ANY,"disconnect?\n"); + } +#endif + /* PCD callback for suspend. */ + pcd_suspend(_core_if); + } else { + if (_core_if->op_state == A_PERIPHERAL) { + DWC_DEBUGPL(DBG_ANY,"a_peripheral->a_host\n"); + /* Clear the a_peripheral flag, back to a_host. */ + pcd_stop( _core_if ); + hcd_start( _core_if ); + _core_if->op_state = A_HOST; + } + } + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.usbsuspend = 1; + dwc_write_reg32( &_core_if->core_global_regs->gintsts, gintsts.d32); + + return 1; +} + + +/** + * This function returns the Core Interrupt register. + */ +static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t *_core_if) +{ + gintsts_data_t gintsts; + gintmsk_data_t gintmsk; + gintmsk_data_t gintmsk_common = {.d32=0}; + gintmsk_common.b.wkupintr = 1; + gintmsk_common.b.sessreqintr = 1; + gintmsk_common.b.conidstschng = 1; + gintmsk_common.b.otgintr = 1; + gintmsk_common.b.modemismatch = 1; + gintmsk_common.b.disconnect = 1; + gintmsk_common.b.usbsuspend = 1; + /** @todo: The port interrupt occurs while in device + * mode. Added code to CIL to clear the interrupt for now! + */ + gintmsk_common.b.portintr = 1; + + gintsts.d32 = dwc_read_reg32(&_core_if->core_global_regs->gintsts); + gintmsk.d32 = dwc_read_reg32(&_core_if->core_global_regs->gintmsk); +#ifdef DEBUG + /* if any common interrupts set */ + if (gintsts.d32 & gintmsk_common.d32) { + DWC_DEBUGPL(DBG_ANY, "gintsts=%08x gintmsk=%08x\n", + gintsts.d32, gintmsk.d32); + } +#endif + + return ((gintsts.d32 & gintmsk.d32 ) & gintmsk_common.d32); + +} + +/** + * Common interrupt handler. + * + * The common interrupts are those that occur in both Host and Device mode. + * This handler handles the following interrupts: + * - Mode Mismatch Interrupt + * - Disconnect Interrupt + * - OTG Interrupt + * - Connector ID Status Change Interrupt + * - Session Request Interrupt. + * - Resume / Remote Wakeup Detected Interrupt. + * + */ +extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if ) +{ + int retval = 0; + gintsts_data_t gintsts; + + gintsts.d32 = dwc_otg_read_common_intr(_core_if); + + if (gintsts.b.modemismatch) { + retval |= dwc_otg_handle_mode_mismatch_intr( _core_if ); + } + if (gintsts.b.otgintr) { + retval |= dwc_otg_handle_otg_intr( _core_if ); + } + if (gintsts.b.conidstschng) { + retval |= dwc_otg_handle_conn_id_status_change_intr( _core_if ); + } + if (gintsts.b.disconnect) { + retval |= dwc_otg_handle_disconnect_intr( _core_if ); + } + if (gintsts.b.sessreqintr) { + retval |= dwc_otg_handle_session_req_intr( _core_if ); + } + if (gintsts.b.wkupintr) { + retval |= dwc_otg_handle_wakeup_detected_intr( _core_if ); + } + if (gintsts.b.usbsuspend) { + retval |= dwc_otg_handle_usb_suspend_intr( _core_if ); + } + if (gintsts.b.portintr && dwc_otg_is_device_mode(_core_if)) { + /* The port interrupt occurs while in device mode with HPRT0 + * Port Enable/Disable. + */ + gintsts.d32 = 0; + gintsts.b.portintr = 1; + dwc_write_reg32(&_core_if->core_global_regs->gintsts, + gintsts.d32); + retval |= 1; + + } + return retval; +} diff --git a/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_driver.c b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_driver.c new file mode 100644 index 0000000000..5c64ebbe0d --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_driver.c @@ -0,0 +1,1277 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.c $ + * $Revision: 1.1.1.1 $ + * $Date: 2009-04-17 06:15:34 $ + * $Change: 631780 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ + +/** @file + * The dwc_otg_driver module provides the initialization and cleanup entry + * points for the DWC_otg driver. This module will be dynamically installed + * after Linux is booted using the insmod command. When the module is + * installed, the dwc_otg_init function is called. When the module is + * removed (using rmmod), the dwc_otg_cleanup function is called. + * + * This module also defines a data structure for the dwc_otg_driver, which is + * used in conjunction with the standard ARM lm_device structure. These + * structures allow the OTG driver to comply with the standard Linux driver + * model in which devices and drivers are registered with a bus driver. This + * has the benefit that Linux can expose attributes of the driver and device + * in its special sysfs file system. Users can then read or write files in + * this file system to perform diagnostics on the driver components or the + * device. + */ + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include /* permission constants */ +#include +#include + +#include "dwc_otg_plat.h" +#include "dwc_otg_attr.h" +#include "dwc_otg_driver.h" +#include "dwc_otg_cil.h" +#include "dwc_otg_cil_ifx.h" + +// #include "dwc_otg_pcd.h" // device +#include "dwc_otg_hcd.h" // host + +#include "dwc_otg_ifx.h" // for Infineon platform specific. + +#define DWC_DRIVER_VERSION "2.60a 22-NOV-2006" +#define DWC_DRIVER_DESC "HS OTG USB Controller driver" + +const char dwc_driver_name[] = "dwc_otg"; + +static unsigned long dwc_iomem_base = IFX_USB_IOMEM_BASE; +int dwc_irq = LTQ_USB_INT; +//int dwc_irq = 54; +//int dwc_irq = IFXMIPS_USB_OC_INT; + +extern int ifx_usb_hc_init(unsigned long base_addr, int irq); +extern void ifx_usb_hc_remove(void); + +/*-------------------------------------------------------------------------*/ +/* Encapsulate the module parameter settings */ + +static dwc_otg_core_params_t dwc_otg_module_params = { + .opt = -1, + .otg_cap = -1, + .dma_enable = -1, + .dma_burst_size = -1, + .speed = -1, + .host_support_fs_ls_low_power = -1, + .host_ls_low_power_phy_clk = -1, + .enable_dynamic_fifo = -1, + .data_fifo_size = -1, + .dev_rx_fifo_size = -1, + .dev_nperio_tx_fifo_size = -1, + .dev_perio_tx_fifo_size = /* dev_perio_tx_fifo_size_1 */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 15 */ + .host_rx_fifo_size = -1, + .host_nperio_tx_fifo_size = -1, + .host_perio_tx_fifo_size = -1, + .max_transfer_size = -1, + .max_packet_count = -1, + .host_channels = -1, + .dev_endpoints = -1, + .phy_type = -1, + .phy_utmi_width = -1, + .phy_ulpi_ddr = -1, + .phy_ulpi_ext_vbus = -1, + .i2c_enable = -1, + .ulpi_fs_ls = -1, + .ts_dline = -1, + .en_multiple_tx_fifo = -1, + .dev_tx_fifo_size = { /* dev_tx_fifo_size */ + -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 + }, /* 15 */ + .thr_ctl = -1, + .tx_thr_length = -1, + .rx_thr_length = -1, +}; + +/** + * This function shows the Driver Version. + */ +static ssize_t version_show(struct device_driver *dev, char *buf) +{ + return snprintf(buf, sizeof(DWC_DRIVER_VERSION)+2,"%s\n", + DWC_DRIVER_VERSION); +} +static DRIVER_ATTR(version, S_IRUGO, version_show, NULL); + +/** + * Global Debug Level Mask. + */ +uint32_t g_dbg_lvl = 0xff; /* OFF */ + +/** + * This function shows the driver Debug Level. + */ +static ssize_t dbg_level_show(struct device_driver *_drv, char *_buf) +{ + return sprintf(_buf, "0x%0x\n", g_dbg_lvl); +} +/** + * This function stores the driver Debug Level. + */ +static ssize_t dbg_level_store(struct device_driver *_drv, const char *_buf, + size_t _count) +{ + g_dbg_lvl = simple_strtoul(_buf, NULL, 16); + return _count; +} +static DRIVER_ATTR(debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store); + +/** + * This function is called during module intialization to verify that + * the module parameters are in a valid state. + */ +static int check_parameters(dwc_otg_core_if_t *core_if) +{ + int i; + int retval = 0; + +/* Checks if the parameter is outside of its valid range of values */ +#define DWC_OTG_PARAM_TEST(_param_,_low_,_high_) \ + ((dwc_otg_module_params._param_ < (_low_)) || \ + (dwc_otg_module_params._param_ > (_high_))) + +/* If the parameter has been set by the user, check that the parameter value is + * within the value range of values. If not, report a module error. */ +#define DWC_OTG_PARAM_ERR(_param_,_low_,_high_,_string_) \ + do { \ + if (dwc_otg_module_params._param_ != -1) { \ + if (DWC_OTG_PARAM_TEST(_param_,(_low_),(_high_))) { \ + DWC_ERROR("`%d' invalid for parameter `%s'\n", \ + dwc_otg_module_params._param_, _string_); \ + dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \ + retval ++; \ + } \ + } \ + } while (0) + + DWC_OTG_PARAM_ERR(opt,0,1,"opt"); + DWC_OTG_PARAM_ERR(otg_cap,0,2,"otg_cap"); + DWC_OTG_PARAM_ERR(dma_enable,0,1,"dma_enable"); + DWC_OTG_PARAM_ERR(speed,0,1,"speed"); + DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power,0,1,"host_support_fs_ls_low_power"); + DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk,0,1,"host_ls_low_power_phy_clk"); + DWC_OTG_PARAM_ERR(enable_dynamic_fifo,0,1,"enable_dynamic_fifo"); + DWC_OTG_PARAM_ERR(data_fifo_size,32,32768,"data_fifo_size"); + DWC_OTG_PARAM_ERR(dev_rx_fifo_size,16,32768,"dev_rx_fifo_size"); + DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size,16,32768,"dev_nperio_tx_fifo_size"); + DWC_OTG_PARAM_ERR(host_rx_fifo_size,16,32768,"host_rx_fifo_size"); + DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size,16,32768,"host_nperio_tx_fifo_size"); + DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size,16,32768,"host_perio_tx_fifo_size"); + DWC_OTG_PARAM_ERR(max_transfer_size,2047,524288,"max_transfer_size"); + DWC_OTG_PARAM_ERR(max_packet_count,15,511,"max_packet_count"); + DWC_OTG_PARAM_ERR(host_channels,1,16,"host_channels"); + DWC_OTG_PARAM_ERR(dev_endpoints,1,15,"dev_endpoints"); + DWC_OTG_PARAM_ERR(phy_type,0,2,"phy_type"); + DWC_OTG_PARAM_ERR(phy_ulpi_ddr,0,1,"phy_ulpi_ddr"); + DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus,0,1,"phy_ulpi_ext_vbus"); + DWC_OTG_PARAM_ERR(i2c_enable,0,1,"i2c_enable"); + DWC_OTG_PARAM_ERR(ulpi_fs_ls,0,1,"ulpi_fs_ls"); + DWC_OTG_PARAM_ERR(ts_dline,0,1,"ts_dline"); + + if (dwc_otg_module_params.dma_burst_size != -1) { + if (DWC_OTG_PARAM_TEST(dma_burst_size,1,1) && + DWC_OTG_PARAM_TEST(dma_burst_size,4,4) && + DWC_OTG_PARAM_TEST(dma_burst_size,8,8) && + DWC_OTG_PARAM_TEST(dma_burst_size,16,16) && + DWC_OTG_PARAM_TEST(dma_burst_size,32,32) && + DWC_OTG_PARAM_TEST(dma_burst_size,64,64) && + DWC_OTG_PARAM_TEST(dma_burst_size,128,128) && + DWC_OTG_PARAM_TEST(dma_burst_size,256,256)) + { + DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n", + dwc_otg_module_params.dma_burst_size); + dwc_otg_module_params.dma_burst_size = 32; + retval ++; + } + } + + if (dwc_otg_module_params.phy_utmi_width != -1) { + if (DWC_OTG_PARAM_TEST(phy_utmi_width,8,8) && + DWC_OTG_PARAM_TEST(phy_utmi_width,16,16)) + { + DWC_ERROR("`%d' invalid for parameter `phy_utmi_width'\n", + dwc_otg_module_params.phy_utmi_width); + //dwc_otg_module_params.phy_utmi_width = 16; + dwc_otg_module_params.phy_utmi_width = 8; + retval ++; + } + } + + for (i=0; i<15; i++) { + /** @todo should be like above */ + //DWC_OTG_PARAM_ERR(dev_perio_tx_fifo_size[i],4,768,"dev_perio_tx_fifo_size"); + if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) { + if (DWC_OTG_PARAM_TEST(dev_perio_tx_fifo_size[i],4,768)) { + DWC_ERROR("`%d' invalid for parameter `%s_%d'\n", + dwc_otg_module_params.dev_perio_tx_fifo_size[i], "dev_perio_tx_fifo_size", i); + dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default; + retval ++; + } + } + } + + DWC_OTG_PARAM_ERR(en_multiple_tx_fifo, 0, 1, "en_multiple_tx_fifo"); + for (i = 0; i < 15; i++) { + /** @todo should be like above */ + //DWC_OTG_PARAM_ERR(dev_tx_fifo_size[i],4,768,"dev_tx_fifo_size"); + if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) { + if (DWC_OTG_PARAM_TEST(dev_tx_fifo_size[i], 4, 768)) { + DWC_ERROR("`%d' invalid for parameter `%s_%d'\n", + dwc_otg_module_params.dev_tx_fifo_size[i], + "dev_tx_fifo_size", i); + dwc_otg_module_params.dev_tx_fifo_size[i] = + dwc_param_dev_tx_fifo_size_default; + retval++; + } + } + } + DWC_OTG_PARAM_ERR(thr_ctl, 0, 7, "thr_ctl"); + DWC_OTG_PARAM_ERR(tx_thr_length, 8, 128, "tx_thr_length"); + DWC_OTG_PARAM_ERR(rx_thr_length, 8, 128, "rx_thr_length"); + + /* At this point, all module parameters that have been set by the user + * are valid, and those that have not are left unset. Now set their + * default values and/or check the parameters against the hardware + * configurations of the OTG core. */ + + + +/* This sets the parameter to the default value if it has not been set by the + * user */ +#define DWC_OTG_PARAM_SET_DEFAULT(_param_) \ + ({ \ + int changed = 1; \ + if (dwc_otg_module_params._param_ == -1) { \ + changed = 0; \ + dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \ + } \ + changed; \ + }) + +/* This checks the macro agains the hardware configuration to see if it is + * valid. It is possible that the default value could be invalid. In this + * case, it will report a module error if the user touched the parameter. + * Otherwise it will adjust the value without any error. */ +#define DWC_OTG_PARAM_CHECK_VALID(_param_,_str_,_is_valid_,_set_valid_) \ + ({ \ + int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \ + int error = 0; \ + if (!(_is_valid_)) { \ + if (changed) { \ + DWC_ERROR("`%d' invalid for parameter `%s'. Check HW configuration.\n", dwc_otg_module_params._param_,_str_); \ + error = 1; \ + } \ + dwc_otg_module_params._param_ = (_set_valid_); \ + } \ + error; \ + }) + + /* OTG Cap */ + retval += DWC_OTG_PARAM_CHECK_VALID(otg_cap,"otg_cap", + ({ + int valid; + valid = 1; + switch (dwc_otg_module_params.otg_cap) { + case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE: + if (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) valid = 0; + break; + case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE: + if ((core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) && + (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) && + (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) && + (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) + { + valid = 0; + } + break; + case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE: + /* always valid */ + break; + } + valid; + }), + (((core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) || + (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) || + (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) || + (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ? + DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE : + DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE)); + + retval += DWC_OTG_PARAM_CHECK_VALID(dma_enable,"dma_enable", + ((dwc_otg_module_params.dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1, + 0); + + retval += DWC_OTG_PARAM_CHECK_VALID(opt,"opt", + 1, + 0); + + DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size); + + retval += DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power, + "host_support_fs_ls_low_power", + 1, 0); + + retval += DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo, + "enable_dynamic_fifo", + ((dwc_otg_module_params.enable_dynamic_fifo == 0) || + (core_if->hwcfg2.b.dynamic_fifo == 1)), 0); + + + retval += DWC_OTG_PARAM_CHECK_VALID(data_fifo_size, + "data_fifo_size", + (dwc_otg_module_params.data_fifo_size <= core_if->hwcfg3.b.dfifo_depth), + core_if->hwcfg3.b.dfifo_depth); + + retval += DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size, + "dev_rx_fifo_size", + (dwc_otg_module_params.dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)), + dwc_read_reg32(&core_if->core_global_regs->grxfsiz)); + + retval += DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size, + "dev_nperio_tx_fifo_size", + (dwc_otg_module_params.dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)), + (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)); + + retval += DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size, + "host_rx_fifo_size", + (dwc_otg_module_params.host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)), + dwc_read_reg32(&core_if->core_global_regs->grxfsiz)); + + + retval += DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size, + "host_nperio_tx_fifo_size", + (dwc_otg_module_params.host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)), + (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)); + + retval += DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size, + "host_perio_tx_fifo_size", + (dwc_otg_module_params.host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))), + ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))); + + retval += DWC_OTG_PARAM_CHECK_VALID(max_transfer_size, + "max_transfer_size", + (dwc_otg_module_params.max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))), + ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1)); + + retval += DWC_OTG_PARAM_CHECK_VALID(max_packet_count, + "max_packet_count", + (dwc_otg_module_params.max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))), + ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1)); + + retval += DWC_OTG_PARAM_CHECK_VALID(host_channels, + "host_channels", + (dwc_otg_module_params.host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)), + (core_if->hwcfg2.b.num_host_chan + 1)); + + retval += DWC_OTG_PARAM_CHECK_VALID(dev_endpoints, + "dev_endpoints", + (dwc_otg_module_params.dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)), + core_if->hwcfg2.b.num_dev_ep); + +/* + * Define the following to disable the FS PHY Hardware checking. This is for + * internal testing only. + * + * #define NO_FS_PHY_HW_CHECKS + */ + +#ifdef NO_FS_PHY_HW_CHECKS + retval += DWC_OTG_PARAM_CHECK_VALID(phy_type, + "phy_type", 1, 0); +#else + retval += DWC_OTG_PARAM_CHECK_VALID(phy_type, + "phy_type", + ({ + int valid = 0; + if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_UTMI) && + ((core_if->hwcfg2.b.hs_phy_type == 1) || + (core_if->hwcfg2.b.hs_phy_type == 3))) + { + valid = 1; + } + else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_ULPI) && + ((core_if->hwcfg2.b.hs_phy_type == 2) || + (core_if->hwcfg2.b.hs_phy_type == 3))) + { + valid = 1; + } + else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) && + (core_if->hwcfg2.b.fs_phy_type == 1)) + { + valid = 1; + } + valid; + }), + ({ + int set = DWC_PHY_TYPE_PARAM_FS; + if (core_if->hwcfg2.b.hs_phy_type) { + if ((core_if->hwcfg2.b.hs_phy_type == 3) || + (core_if->hwcfg2.b.hs_phy_type == 1)) { + set = DWC_PHY_TYPE_PARAM_UTMI; + } + else { + set = DWC_PHY_TYPE_PARAM_ULPI; + } + } + set; + })); +#endif + + retval += DWC_OTG_PARAM_CHECK_VALID(speed,"speed", + (dwc_otg_module_params.speed == 0) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1, + dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS ? 1 : 0); + + retval += DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk, + "host_ls_low_power_phy_clk", + ((dwc_otg_module_params.host_ls_low_power_phy_clk == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1), + ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)); + + DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr); + DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus); + DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width); + DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls); + DWC_OTG_PARAM_SET_DEFAULT(ts_dline); + +#ifdef NO_FS_PHY_HW_CHECKS + retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable, + "i2c_enable", 1, 0); +#else + retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable, + "i2c_enable", + (dwc_otg_module_params.i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1, + 0); +#endif + + for (i=0; i<16; i++) { + + int changed = 1; + int error = 0; + + if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] == -1) { + changed = 0; + dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default; + } + if (!(dwc_otg_module_params.dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) { + if (changed) { + DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_perio_tx_fifo_size[i],i); + error = 1; + } + dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]); + } + retval += error; + } + + retval += DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo, + "en_multiple_tx_fifo", + ((dwc_otg_module_params.en_multiple_tx_fifo == 1) && + (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1, 0); + + for (i = 0; i < 16; i++) { + int changed = 1; + int error = 0; + if (dwc_otg_module_params.dev_tx_fifo_size[i] == -1) { + changed = 0; + dwc_otg_module_params.dev_tx_fifo_size[i] = + dwc_param_dev_tx_fifo_size_default; + } + if (!(dwc_otg_module_params.dev_tx_fifo_size[i] <= + (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) { + if (changed) { + DWC_ERROR("%d' invalid for parameter `dev_perio_fifo_size_%d'." + "Check HW configuration.\n",dwc_otg_module_params.dev_tx_fifo_size[i],i); + error = 1; + } + dwc_otg_module_params.dev_tx_fifo_size[i] = + dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]); + } + retval += error; + } + DWC_OTG_PARAM_SET_DEFAULT(thr_ctl); + DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length); + DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length); + return retval; +} // check_parameters + + +/** + * This function is the top level interrupt handler for the Common + * (Device and host modes) interrupts. + */ +static irqreturn_t dwc_otg_common_irq(int _irq, void *_dev) +{ + dwc_otg_device_t *otg_dev = _dev; + int32_t retval = IRQ_NONE; + + retval = dwc_otg_handle_common_intr( otg_dev->core_if ); + + mask_and_ack_ifx_irq (_irq); + + return IRQ_RETVAL(retval); +} + + +/** + * This function is called when a DWC_OTG device is unregistered with the + * dwc_otg_driver. This happens, for example, when the rmmod command is + * executed. The device may or may not be electrically present. If it is + * present, the driver stops device processing. Any resources used on behalf + * of this device are freed. + * + * @return + */ +static int +dwc_otg_driver_remove(struct platform_device *_dev) +{ + //dwc_otg_device_t *otg_dev = dev_get_drvdata(&_dev->dev); + dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev); + + DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev); + + if (otg_dev == NULL) { + /* Memory allocation for the dwc_otg_device failed. */ + return 0; + } + + /* + * Free the IRQ + */ + if (otg_dev->common_irq_installed) { + free_irq( otg_dev->irq, otg_dev ); + } + +#ifndef DWC_DEVICE_ONLY + if (otg_dev->hcd != NULL) { + dwc_otg_hcd_remove(&_dev->dev); + } +#endif + printk("after removehcd\n"); + +// Note: Integrate HOST and DEVICE(Gadget) is not planned yet. +#ifndef DWC_HOST_ONLY + if (otg_dev->pcd != NULL) { + dwc_otg_pcd_remove(otg_dev); + } +#endif + if (otg_dev->core_if != NULL) { + dwc_otg_cil_remove( otg_dev->core_if ); + } + printk("after removecil\n"); + + /* + * Remove the device attributes + */ + dwc_otg_attr_remove(&_dev->dev); + printk("after removeattr\n"); + + /* + * Return the memory. + */ + if (otg_dev->base != NULL) { + iounmap(otg_dev->base); + } + if (otg_dev->phys_addr != 0) { + release_mem_region(otg_dev->phys_addr, otg_dev->base_len); + } + kfree(otg_dev); + + /* + * Clear the drvdata pointer. + */ + //dev_set_drvdata(&_dev->dev, 0); + platform_set_drvdata(_dev, 0); + return 0; +} + +/** + * This function is called when an DWC_OTG device is bound to a + * dwc_otg_driver. It creates the driver components required to + * control the device (CIL, HCD, and PCD) and it initializes the + * device. The driver components are stored in a dwc_otg_device + * structure. A reference to the dwc_otg_device is saved in the + * lm_device. This allows the driver to access the dwc_otg_device + * structure on subsequent calls to driver methods for this device. + * + * @return + */ +static int __devinit +dwc_otg_driver_probe(struct platform_device *_dev) +{ + int retval = 0; + dwc_otg_device_t *dwc_otg_device; + int pin = (int)_dev->dev.platform_data; + int32_t snpsid; + struct resource *res; + gusbcfg_data_t usbcfg = {.d32 = 0}; + + // GPIOs + if(pin >= 0) + { + gpio_request(pin, "usb_power"); + gpio_direction_output(pin, 1); + gpio_set_value(pin, 1); + gpio_export(pin, 0); + } + dev_dbg(&_dev->dev, "dwc_otg_driver_probe (%p)\n", _dev); + + dwc_otg_device = kmalloc(sizeof(dwc_otg_device_t), GFP_KERNEL); + if (dwc_otg_device == 0) { + dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n"); + retval = -ENOMEM; + goto fail; + } + memset(dwc_otg_device, 0, sizeof(*dwc_otg_device)); + dwc_otg_device->reg_offset = 0xFFFFFFFF; + + /* + * Retrieve the memory and IRQ resources. + */ + dwc_otg_device->irq = platform_get_irq(_dev, 0); + if (dwc_otg_device->irq == 0) { + dev_err(&_dev->dev, "no device irq\n"); + retval = -ENODEV; + goto fail; + } + dev_dbg(&_dev->dev, "OTG - device irq: %d\n", dwc_otg_device->irq); + res = platform_get_resource(_dev, IORESOURCE_MEM, 0); + if (res == NULL) { + dev_err(&_dev->dev, "no CSR address\n"); + retval = -ENODEV; + goto fail; + } + dev_dbg(&_dev->dev, "OTG - ioresource_mem start0x%08x: end:0x%08x\n", + (unsigned)res->start, (unsigned)res->end); + dwc_otg_device->phys_addr = res->start; + dwc_otg_device->base_len = res->end - res->start + 1; + if (request_mem_region(dwc_otg_device->phys_addr, dwc_otg_device->base_len, + dwc_driver_name) == NULL) { + dev_err(&_dev->dev, "request_mem_region failed\n"); + retval = -EBUSY; + goto fail; + } + + /* + * Map the DWC_otg Core memory into virtual address space. + */ + dwc_otg_device->base = ioremap_nocache(dwc_otg_device->phys_addr, dwc_otg_device->base_len); + if (dwc_otg_device->base == NULL) { + dev_err(&_dev->dev, "ioremap() failed\n"); + retval = -ENOMEM; + goto fail; + } + dev_dbg(&_dev->dev, "mapped base=0x%08x\n", (unsigned)dwc_otg_device->base); + + /* + * Attempt to ensure this device is really a DWC_otg Controller. + * Read and verify the SNPSID register contents. The value should be + * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX". + */ + snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)dwc_otg_device->base + 0x40)); + if ((snpsid & 0xFFFFF000) != 0x4F542000) { + dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n", snpsid); + retval = -EINVAL; + goto fail; + } + + /* + * Initialize driver data to point to the global DWC_otg + * Device structure. + */ + platform_set_drvdata(_dev, dwc_otg_device); + dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device); + dwc_otg_device->core_if = dwc_otg_cil_init( dwc_otg_device->base, &dwc_otg_module_params); + if (dwc_otg_device->core_if == 0) { + dev_err(&_dev->dev, "CIL initialization failed!\n"); + retval = -ENOMEM; + goto fail; + } + + /* + * Validate parameter values. + */ + if (check_parameters(dwc_otg_device->core_if) != 0) { + retval = -EINVAL; + goto fail; + } + + /* Added for PLB DMA phys virt mapping */ + //dwc_otg_device->core_if->phys_addr = dwc_otg_device->phys_addr; + /* + * Create Device Attributes in sysfs + */ + dwc_otg_attr_create (&_dev->dev); + + /* + * Disable the global interrupt until all the interrupt + * handlers are installed. + */ + dwc_otg_disable_global_interrupts( dwc_otg_device->core_if ); + /* + * Install the interrupt handler for the common interrupts before + * enabling common interrupts in core_init below. + */ + DWC_DEBUGPL( DBG_CIL, "registering (common) handler for irq%d\n", dwc_otg_device->irq); + + retval = request_irq((unsigned int)dwc_otg_device->irq, dwc_otg_common_irq, + //SA_INTERRUPT|SA_SHIRQ, "dwc_otg", (void *)dwc_otg_device ); + IRQF_SHARED, "dwc_otg", (void *)dwc_otg_device ); + //IRQF_DISABLED, "dwc_otg", (void *)dwc_otg_device ); + if (retval != 0) { + DWC_ERROR("request of irq%d failed retval: %d\n", dwc_otg_device->irq, retval); + retval = -EBUSY; + goto fail; + } else { + dwc_otg_device->common_irq_installed = 1; + } + + /* + * Initialize the DWC_otg core. + */ + dwc_otg_core_init( dwc_otg_device->core_if ); + + +#ifndef DWC_HOST_ONLY // otg device mode. (gadget.) + /* + * Initialize the PCD + */ + retval = dwc_otg_pcd_init(dwc_otg_device); + if (retval != 0) { + DWC_ERROR("dwc_otg_pcd_init failed\n"); + dwc_otg_device->pcd = NULL; + goto fail; + } +#endif // DWC_HOST_ONLY + +#ifndef DWC_DEVICE_ONLY // otg host mode. (HCD) + /* + * Initialize the HCD + */ +#if 1 /*fscz*/ + /* force_host_mode */ + usbcfg.d32 = dwc_read_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg); + usbcfg.b.force_host_mode = 1; + dwc_write_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg, usbcfg.d32); +#endif + retval = dwc_otg_hcd_init(&_dev->dev, dwc_otg_device); + if (retval != 0) { + DWC_ERROR("dwc_otg_hcd_init failed\n"); + dwc_otg_device->hcd = NULL; + goto fail; + } +#endif // DWC_DEVICE_ONLY + + /* + * Enable the global interrupt after all the interrupt + * handlers are installed. + */ + dwc_otg_enable_global_interrupts( dwc_otg_device->core_if ); +#if 0 /*fscz*/ + usbcfg.d32 = dwc_read_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg); + usbcfg.b.force_host_mode = 0; + dwc_write_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg, usbcfg.d32); +#endif + + + return 0; + +fail: + dwc_otg_driver_remove(_dev); + return retval; +} + +/** + * This structure defines the methods to be called by a bus driver + * during the lifecycle of a device on that bus. Both drivers and + * devices are registered with a bus driver. The bus driver matches + * devices to drivers based on information in the device and driver + * structures. + * + * The probe function is called when the bus driver matches a device + * to this driver. The remove function is called when a device is + * unregistered with the bus driver. + */ +struct platform_driver dwc_otg_driver = { + .probe = dwc_otg_driver_probe, + .remove = dwc_otg_driver_remove, +// .suspend = dwc_otg_driver_suspend, +// .resume = dwc_otg_driver_resume, + .driver = { + .name = dwc_driver_name, + .owner = THIS_MODULE, + }, +}; +EXPORT_SYMBOL(dwc_otg_driver); + +/** + * This function is called when the dwc_otg_driver is installed with the + * insmod command. It registers the dwc_otg_driver structure with the + * appropriate bus driver. This will cause the dwc_otg_driver_probe function + * to be called. In addition, the bus driver will automatically expose + * attributes defined for the device and driver in the special sysfs file + * system. + * + * @return + */ +static int __init dwc_otg_init(void) +{ + int retval = 0; + + printk(KERN_INFO "%s: version %s\n", dwc_driver_name, DWC_DRIVER_VERSION); + + if (ltq_is_ase()) + dwc_irq = LTQ_USB_ASE_INT; + + // ifxmips setup + retval = ifx_usb_hc_init(dwc_iomem_base, dwc_irq); + if (retval < 0) + { + printk(KERN_ERR "%s retval=%d\n", __func__, retval); + return retval; + } + dwc_otg_power_on(); // ifx only!! + + + retval = platform_driver_register(&dwc_otg_driver); + + if (retval < 0) { + printk(KERN_ERR "%s retval=%d\n", __func__, retval); + goto error1; + } + + retval = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version); + if (retval < 0) + { + printk(KERN_ERR "%s retval=%d\n", __func__, retval); + goto error2; + } + retval = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel); + if (retval < 0) + { + printk(KERN_ERR "%s retval=%d\n", __func__, retval); + goto error3; + } + return retval; + + +error3: + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version); +error2: + driver_unregister(&dwc_otg_driver.driver); +error1: + ifx_usb_hc_remove(); + return retval; +} +module_init(dwc_otg_init); + +/** + * This function is called when the driver is removed from the kernel + * with the rmmod command. The driver unregisters itself with its bus + * driver. + * + */ +static void __exit dwc_otg_cleanup(void) +{ + printk(KERN_DEBUG "dwc_otg_cleanup()\n"); + + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel); + driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version); + + platform_driver_unregister(&dwc_otg_driver); + ifx_usb_hc_remove(); + + printk(KERN_INFO "%s module removed\n", dwc_driver_name); +} +module_exit(dwc_otg_cleanup); + +MODULE_DESCRIPTION(DWC_DRIVER_DESC); +MODULE_AUTHOR("Synopsys Inc."); +MODULE_LICENSE("GPL"); + +module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444); +MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None"); +module_param_named(opt, dwc_otg_module_params.opt, int, 0444); +MODULE_PARM_DESC(opt, "OPT Mode"); +module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444); +MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled"); +module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444); +MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256"); +module_param_named(speed, dwc_otg_module_params.speed, int, 0444); +MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed"); +module_param_named(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444); +MODULE_PARM_DESC(host_support_fs_ls_low_power, "Support Low Power w/FS or LS 0=Support 1=Don't Support"); +module_param_named(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444); +MODULE_PARM_DESC(host_ls_low_power_phy_clk, "Low Speed Low Power Clock 0=48Mhz 1=6Mhz"); +module_param_named(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444); +MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing"); +module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444); +MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768"); +module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444); +MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); +module_param_named(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444); +MODULE_PARM_DESC(dev_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768"); +module_param_named(dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444); +MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO 4-768"); +module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444); +MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); +module_param_named(host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444); +MODULE_PARM_DESC(host_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768"); +module_param_named(host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444); +MODULE_PARM_DESC(host_perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768"); +module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444); +/** @todo Set the max to 512K, modify checks */ +MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535"); +module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444); +MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511"); +module_param_named(host_channels, dwc_otg_module_params.host_channels, int, 0444); +MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16"); +module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444); +MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15"); +module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444); +MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI"); +module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444); +MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits"); +module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444); +MODULE_PARM_DESC(phy_ulpi_ddr, "ULPI at double or single data rate 0=Single 1=Double"); +module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444); +MODULE_PARM_DESC(phy_ulpi_ext_vbus, "ULPI PHY using internal or external vbus 0=Internal"); +module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444); +MODULE_PARM_DESC(i2c_enable, "FS PHY Interface"); +module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444); +MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only"); +module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444); +MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs"); +module_param_named(debug, g_dbg_lvl, int, 0444); +MODULE_PARM_DESC(debug, "0"); +module_param_named(en_multiple_tx_fifo, + dwc_otg_module_params.en_multiple_tx_fifo, int, 0444); +MODULE_PARM_DESC(en_multiple_tx_fifo, + "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled"); +module_param_named(dev_tx_fifo_size_1, + dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_2, + dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_3, + dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_4, + dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_5, + dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_6, + dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_7, + dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_8, + dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_9, + dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_10, + dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_11, + dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_12, + dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_13, + dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_14, + dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768"); +module_param_named(dev_tx_fifo_size_15, + dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444); +MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768"); +module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444); +MODULE_PARM_DESC(thr_ctl, "Thresholding enable flag bit" + "0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled"); +module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444); +MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs"); +module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444); +MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs"); +module_param_named (iomem_base, dwc_iomem_base, ulong, 0444); +MODULE_PARM_DESC (dwc_iomem_base, "The base address of the DWC_OTG register."); +module_param_named (irq, dwc_irq, int, 0444); +MODULE_PARM_DESC (dwc_irq, "The interrupt number"); + +/** @page "Module Parameters" + * + * The following parameters may be specified when starting the module. + * These parameters define how the DWC_otg controller should be + * configured. Parameter values are passed to the CIL initialization + * function dwc_otg_cil_init + * + * Example: modprobe dwc_otg speed=1 otg_cap=1 + * + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +*/ diff --git a/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_driver.h b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_driver.h new file mode 100644 index 0000000000..7e6940dd13 --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_driver.h @@ -0,0 +1,84 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.h $ + * $Revision: 1.1.1.1 $ + * $Date: 2009-04-17 06:15:34 $ + * $Change: 510275 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ + +#if !defined(__DWC_OTG_DRIVER_H__) +#define __DWC_OTG_DRIVER_H__ + +/** @file + * This file contains the interface to the Linux driver. + */ +#include "dwc_otg_cil.h" + +/* Type declarations */ +struct dwc_otg_pcd; +struct dwc_otg_hcd; + +/** + * This structure is a wrapper that encapsulates the driver components used to + * manage a single DWC_otg controller. + */ +typedef struct dwc_otg_device +{ + /** Base address returned from ioremap() */ + void *base; + + /** Pointer to the core interface structure. */ + dwc_otg_core_if_t *core_if; + + /** Register offset for Diagnostic API.*/ + uint32_t reg_offset; + + /** Pointer to the PCD structure. */ + struct dwc_otg_pcd *pcd; + + /** Pointer to the HCD structure. */ + struct dwc_otg_hcd *hcd; + + /** Flag to indicate whether the common IRQ handler is installed. */ + uint8_t common_irq_installed; + + /** Interrupt request number. */ + unsigned int irq; + + /** Physical address of Control and Status registers, used by + * release_mem_region(). + */ + resource_size_t phys_addr; + + /** Length of memory region, used by release_mem_region(). */ + unsigned long base_len; +} dwc_otg_device_t; + +//#define dev_dbg(fake, format, arg...) printk(KERN_CRIT __FILE__ ":%d: " format "\n" , __LINE__, ## arg) + +#endif diff --git a/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_hcd.c b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_hcd.c new file mode 100644 index 0000000000..ad6bc72ce8 --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_hcd.c @@ -0,0 +1,2870 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd.c $ + * $Revision: 1.1.1.1 $ + * $Date: 2009-04-17 06:15:34 $ + * $Change: 631780 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ +#ifndef DWC_DEVICE_ONLY + +/** + * @file + * + * This file contains the implementation of the HCD. In Linux, the HCD + * implements the hc_driver API. + */ +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include + +#include "dwc_otg_driver.h" +#include "dwc_otg_hcd.h" +#include "dwc_otg_regs.h" + +#include +#include "dwc_otg_ifx.h" // for Infineon platform specific. +extern atomic_t release_later; + +static u64 dma_mask = DMA_BIT_MASK(32); + +static const char dwc_otg_hcd_name [] = "dwc_otg_hcd"; +static const struct hc_driver dwc_otg_hc_driver = +{ + .description = dwc_otg_hcd_name, + .product_desc = "DWC OTG Controller", + .hcd_priv_size = sizeof(dwc_otg_hcd_t), + .irq = dwc_otg_hcd_irq, + .flags = HCD_MEMORY | HCD_USB2, + //.reset = + .start = dwc_otg_hcd_start, + //.suspend = + //.resume = + .stop = dwc_otg_hcd_stop, + .urb_enqueue = dwc_otg_hcd_urb_enqueue, + .urb_dequeue = dwc_otg_hcd_urb_dequeue, + .endpoint_disable = dwc_otg_hcd_endpoint_disable, + .get_frame_number = dwc_otg_hcd_get_frame_number, + .hub_status_data = dwc_otg_hcd_hub_status_data, + .hub_control = dwc_otg_hcd_hub_control, + //.hub_suspend = + //.hub_resume = +}; + + +/** + * Work queue function for starting the HCD when A-Cable is connected. + * The dwc_otg_hcd_start() must be called in a process context. + */ +static void hcd_start_func(struct work_struct *work) +{ + struct dwc_otg_hcd *priv = + container_of(work, struct dwc_otg_hcd, start_work); + struct usb_hcd *usb_hcd = (struct usb_hcd *)priv->_p; + DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, usb_hcd); + if (usb_hcd) { + dwc_otg_hcd_start(usb_hcd); + } +} + + +/** + * HCD Callback function for starting the HCD when A-Cable is + * connected. + * + * @param _p void pointer to the struct usb_hcd + */ +static int32_t dwc_otg_hcd_start_cb(void *_p) +{ + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_p); + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; + hprt0_data_t hprt0; + if (core_if->op_state == B_HOST) { + /* + * Reset the port. During a HNP mode switch the reset + * needs to occur within 1ms and have a duration of at + * least 50ms. + */ + hprt0.d32 = dwc_otg_read_hprt0 (core_if); + hprt0.b.prtrst = 1; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + ((struct usb_hcd *)_p)->self.is_b_host = 1; + } else { + ((struct usb_hcd *)_p)->self.is_b_host = 0; + } + /* Need to start the HCD in a non-interrupt context. */ + INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func); + dwc_otg_hcd->_p = _p; + schedule_work(&dwc_otg_hcd->start_work); + return 1; +} + + +/** + * HCD Callback function for stopping the HCD. + * + * @param _p void pointer to the struct usb_hcd + */ +static int32_t dwc_otg_hcd_stop_cb( void *_p ) +{ + struct usb_hcd *usb_hcd = (struct usb_hcd *)_p; + DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p); + dwc_otg_hcd_stop( usb_hcd ); + return 1; +} +static void del_xfer_timers(dwc_otg_hcd_t *_hcd) +{ +#ifdef DEBUG + int i; + int num_channels = _hcd->core_if->core_params->host_channels; + for (i = 0; i < num_channels; i++) { + del_timer(&_hcd->core_if->hc_xfer_timer[i]); + } +#endif /* */ +} + +static void del_timers(dwc_otg_hcd_t *_hcd) +{ + del_xfer_timers(_hcd); + del_timer(&_hcd->conn_timer); +} + +/** + * Processes all the URBs in a single list of QHs. Completes them with + * -ETIMEDOUT and frees the QTD. + */ +static void kill_urbs_in_qh_list(dwc_otg_hcd_t * _hcd, + struct list_head *_qh_list) +{ + struct list_head *qh_item; + dwc_otg_qh_t *qh; + struct list_head *qtd_item; + dwc_otg_qtd_t *qtd; + + list_for_each(qh_item, _qh_list) { + qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry); + for (qtd_item = qh->qtd_list.next; qtd_item != &qh->qtd_list; + qtd_item = qh->qtd_list.next) { + qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry); + if (qtd->urb != NULL) { + dwc_otg_hcd_complete_urb(_hcd, qtd->urb,-ETIMEDOUT); + } + dwc_otg_hcd_qtd_remove_and_free(qtd); + } + } +} + +/** + * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic + * and periodic schedules. The QTD associated with each URB is removed from + * the schedule and freed. This function may be called when a disconnect is + * detected or when the HCD is being stopped. + */ +static void kill_all_urbs(dwc_otg_hcd_t *_hcd) +{ + kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_deferred); + kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_inactive); + kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_active); + kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_inactive); + kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_ready); + kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_assigned); + kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_queued); +} + +/** + * HCD Callback function for disconnect of the HCD. + * + * @param _p void pointer to the struct usb_hcd + */ +static int32_t dwc_otg_hcd_disconnect_cb( void *_p ) +{ + gintsts_data_t intr; + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p); + + DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p); + + /* + * Set status flags for the hub driver. + */ + dwc_otg_hcd->flags.b.port_connect_status_change = 1; + dwc_otg_hcd->flags.b.port_connect_status = 0; + + /* + * Shutdown any transfers in process by clearing the Tx FIFO Empty + * interrupt mask and status bits and disabling subsequent host + * channel interrupts. + */ + intr.d32 = 0; + intr.b.nptxfempty = 1; + intr.b.ptxfempty = 1; + intr.b.hcintr = 1; + dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0); + dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0); + + del_timers(dwc_otg_hcd); + + /* + * Turn off the vbus power only if the core has transitioned to device + * mode. If still in host mode, need to keep power on to detect a + * reconnection. + */ + if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) { + if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) { + hprt0_data_t hprt0 = { .d32=0 }; + DWC_PRINT("Disconnect: PortPower off\n"); + hprt0.b.prtpwr = 0; + dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32); + } + + dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if ); + } + + /* Respond with an error status to all URBs in the schedule. */ + kill_all_urbs(dwc_otg_hcd); + + if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) { + /* Clean up any host channels that were in use. */ + int num_channels; + int i; + dwc_hc_t *channel; + dwc_otg_hc_regs_t *hc_regs; + hcchar_data_t hcchar; + + num_channels = dwc_otg_hcd->core_if->core_params->host_channels; + + if (!dwc_otg_hcd->core_if->dma_enable) { + /* Flush out any channel requests in slave mode. */ + for (i = 0; i < num_channels; i++) { + channel = dwc_otg_hcd->hc_ptr_array[i]; + if (list_empty(&channel->hc_list_entry)) { + hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i]; + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + if (hcchar.b.chen) { + hcchar.b.chen = 0; + hcchar.b.chdis = 1; + hcchar.b.epdir = 0; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + } + } + } + } + + for (i = 0; i < num_channels; i++) { + channel = dwc_otg_hcd->hc_ptr_array[i]; + if (list_empty(&channel->hc_list_entry)) { + hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i]; + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + if (hcchar.b.chen) { + /* Halt the channel. */ + hcchar.b.chdis = 1; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + } + + dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, channel); + list_add_tail(&channel->hc_list_entry, + &dwc_otg_hcd->free_hc_list); + } + } + } + + /* A disconnect will end the session so the B-Device is no + * longer a B-host. */ + ((struct usb_hcd *)_p)->self.is_b_host = 0; + + return 1; +} + +/** + * Connection timeout function. An OTG host is required to display a + * message if the device does not connect within 10 seconds. + */ +void dwc_otg_hcd_connect_timeout( unsigned long _ptr ) +{ + DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int)_ptr); + DWC_PRINT( "Connect Timeout\n"); + DWC_ERROR( "Device Not Connected/Responding\n" ); +} + +/** + * Start the connection timer. An OTG host is required to display a + * message if the device does not connect within 10 seconds. The + * timer is deleted if a port connect interrupt occurs before the + * timer expires. + */ +static void dwc_otg_hcd_start_connect_timer( dwc_otg_hcd_t *_hcd) +{ + init_timer( &_hcd->conn_timer ); + _hcd->conn_timer.function = dwc_otg_hcd_connect_timeout; + _hcd->conn_timer.data = (unsigned long)0; + _hcd->conn_timer.expires = jiffies + (HZ*10); + add_timer( &_hcd->conn_timer ); +} + +/** + * HCD Callback function for disconnect of the HCD. + * + * @param _p void pointer to the struct usb_hcd + */ +static int32_t dwc_otg_hcd_session_start_cb( void *_p ) +{ + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p); + DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p); + dwc_otg_hcd_start_connect_timer( dwc_otg_hcd ); + return 1; +} + +/** + * HCD Callback structure for handling mode switching. + */ +static dwc_otg_cil_callbacks_t hcd_cil_callbacks = { + .start = dwc_otg_hcd_start_cb, + .stop = dwc_otg_hcd_stop_cb, + .disconnect = dwc_otg_hcd_disconnect_cb, + .session_start = dwc_otg_hcd_session_start_cb, + .p = 0, +}; + + +/** + * Reset tasklet function + */ +static void reset_tasklet_func (unsigned long data) +{ + dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t*)data; + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; + hprt0_data_t hprt0; + + DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n"); + + hprt0.d32 = dwc_otg_read_hprt0 (core_if); + hprt0.b.prtrst = 1; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + mdelay (60); + + hprt0.b.prtrst = 0; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + dwc_otg_hcd->flags.b.port_reset_change = 1; + + return; +} + +static struct tasklet_struct reset_tasklet = { + .next = NULL, + .state = 0, + .count = ATOMIC_INIT(0), + .func = reset_tasklet_func, + .data = 0, +}; + +/** + * Initializes the HCD. This function allocates memory for and initializes the + * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the + * USB bus with the core and calls the hc_driver->start() function. It returns + * a negative error on failure. + */ +int init_hcd_usecs(dwc_otg_hcd_t *_hcd); + +int __devinit dwc_otg_hcd_init(struct device *_dev, dwc_otg_device_t * dwc_otg_device) +{ + struct usb_hcd *hcd = NULL; + dwc_otg_hcd_t *dwc_otg_hcd = NULL; + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + + int num_channels; + int i; + dwc_hc_t *channel; + + int retval = 0; + + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n"); + + /* + * Allocate memory for the base HCD plus the DWC OTG HCD. + * Initialize the base HCD. + */ + hcd = usb_create_hcd(&dwc_otg_hc_driver, _dev, dev_name(_dev)); + if (hcd == NULL) { + retval = -ENOMEM; + goto error1; + } + dev_set_drvdata(_dev, dwc_otg_device); /* fscz restore */ + hcd->regs = otg_dev->base; + hcd->rsrc_start = (int)otg_dev->base; + + hcd->self.otg_port = 1; + + /* Initialize the DWC OTG HCD. */ + dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); + dwc_otg_hcd->core_if = otg_dev->core_if; + otg_dev->hcd = dwc_otg_hcd; + + /* Register the HCD CIL Callbacks */ + dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if, + &hcd_cil_callbacks, hcd); + + /* Initialize the non-periodic schedule. */ + INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive); + INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active); + INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_deferred); + + /* Initialize the periodic schedule. */ + INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive); + INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready); + INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned); + INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued); + + /* + * Create a host channel descriptor for each host channel implemented + * in the controller. Initialize the channel descriptor array. + */ + INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list); + num_channels = dwc_otg_hcd->core_if->core_params->host_channels; + for (i = 0; i < num_channels; i++) { + channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL); + if (channel == NULL) { + retval = -ENOMEM; + DWC_ERROR("%s: host channel allocation failed\n", __func__); + goto error2; + } + memset(channel, 0, sizeof(dwc_hc_t)); + channel->hc_num = i; + dwc_otg_hcd->hc_ptr_array[i] = channel; +#ifdef DEBUG + init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]); +#endif + + DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel); + } + + /* Initialize the Connection timeout timer. */ + init_timer( &dwc_otg_hcd->conn_timer ); + + /* Initialize reset tasklet. */ + reset_tasklet.data = (unsigned long) dwc_otg_hcd; + dwc_otg_hcd->reset_tasklet = &reset_tasklet; + + /* Set device flags indicating whether the HCD supports DMA. */ + if (otg_dev->core_if->dma_enable) { + DWC_PRINT("Using DMA mode\n"); + //_dev->dma_mask = (void *)~0; + //_dev->coherent_dma_mask = ~0; + _dev->dma_mask = &dma_mask; + _dev->coherent_dma_mask = DMA_BIT_MASK(32); + } else { + DWC_PRINT("Using Slave mode\n"); + _dev->dma_mask = (void *)0; + _dev->coherent_dma_mask = 0; + } + + init_hcd_usecs(dwc_otg_hcd); + /* + * Finish generic HCD initialization and start the HCD. This function + * allocates the DMA buffer pool, registers the USB bus, requests the + * IRQ line, and calls dwc_otg_hcd_start method. + */ + retval = usb_add_hcd(hcd, otg_dev->irq, IRQF_SHARED); + if (retval < 0) { + goto error2; + } + + /* + * Allocate space for storing data on status transactions. Normally no + * data is sent, but this space acts as a bit bucket. This must be + * done after usb_add_hcd since that function allocates the DMA buffer + * pool. + */ + if (otg_dev->core_if->dma_enable) { + dwc_otg_hcd->status_buf = + dma_alloc_coherent(_dev, + DWC_OTG_HCD_STATUS_BUF_SIZE, + &dwc_otg_hcd->status_buf_dma, + GFP_KERNEL | GFP_DMA); + } else { + dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE, + GFP_KERNEL); + } + if (dwc_otg_hcd->status_buf == NULL) { + retval = -ENOMEM; + DWC_ERROR("%s: status_buf allocation failed\n", __func__); + goto error3; + } + + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n", + dev_name(_dev), hcd->self.busnum); + + return 0; + + /* Error conditions */ +error3: + usb_remove_hcd(hcd); +error2: + dwc_otg_hcd_free(hcd); + usb_put_hcd(hcd); +error1: + return retval; +} + +/** + * Removes the HCD. + * Frees memory and resources associated with the HCD and deregisters the bus. + */ +void dwc_otg_hcd_remove(struct device *_dev) +{ + dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); + dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd; + struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd); + + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n"); + + /* Turn off all interrupts */ + dwc_write_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0); + dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0); + + usb_remove_hcd(hcd); + + dwc_otg_hcd_free(hcd); + + usb_put_hcd(hcd); + + return; +} + + +/* ========================================================================= + * Linux HC Driver Functions + * ========================================================================= */ + +/** + * Initializes dynamic portions of the DWC_otg HCD state. + */ +static void hcd_reinit(dwc_otg_hcd_t *_hcd) +{ + struct list_head *item; + int num_channels; + int i; + dwc_hc_t *channel; + + _hcd->flags.d32 = 0; + + _hcd->non_periodic_qh_ptr = &_hcd->non_periodic_sched_active; + _hcd->available_host_channels = _hcd->core_if->core_params->host_channels; + + /* + * Put all channels in the free channel list and clean up channel + * states. + */ + item = _hcd->free_hc_list.next; + while (item != &_hcd->free_hc_list) { + list_del(item); + item = _hcd->free_hc_list.next; + } + num_channels = _hcd->core_if->core_params->host_channels; + for (i = 0; i < num_channels; i++) { + channel = _hcd->hc_ptr_array[i]; + list_add_tail(&channel->hc_list_entry, &_hcd->free_hc_list); + dwc_otg_hc_cleanup(_hcd->core_if, channel); + } + + /* Initialize the DWC core for host mode operation. */ + dwc_otg_core_host_init(_hcd->core_if); +} + +/** Initializes the DWC_otg controller and its root hub and prepares it for host + * mode operation. Activates the root port. Returns 0 on success and a negative + * error code on failure. */ +int dwc_otg_hcd_start(struct usb_hcd *_hcd) +{ + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd); + dwc_otg_core_if_t * core_if = dwc_otg_hcd->core_if; + struct usb_bus *bus; + + // int retval; + + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n"); + + bus = hcd_to_bus(_hcd); + + /* Initialize the bus state. If the core is in Device Mode + * HALT the USB bus and return. */ + if (dwc_otg_is_device_mode (core_if)) { + _hcd->state = HC_STATE_HALT; + return 0; + } + _hcd->state = HC_STATE_RUNNING; + + /* Initialize and connect root hub if one is not already attached */ + if (bus->root_hub) { + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n"); + /* Inform the HUB driver to resume. */ + usb_hcd_resume_root_hub(_hcd); + } + else { +#if 0 + struct usb_device *udev; + udev = usb_alloc_dev(NULL, bus, 0); + if (!udev) { + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n"); + return -ENODEV; + } + udev->speed = USB_SPEED_HIGH; + /* Not needed - VJ + if ((retval = usb_hcd_register_root_hub(udev, _hcd)) != 0) { + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error registering %d\n", retval); + return -ENODEV; + } + */ +#else + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n"); +#endif + } + + hcd_reinit(dwc_otg_hcd); + + return 0; +} + +static void qh_list_free(dwc_otg_hcd_t *_hcd, struct list_head *_qh_list) +{ + struct list_head *item; + dwc_otg_qh_t *qh; + + if (_qh_list->next == NULL) { + /* The list hasn't been initialized yet. */ + return; + } + + /* Ensure there are no QTDs or URBs left. */ + kill_urbs_in_qh_list(_hcd, _qh_list); + + for (item = _qh_list->next; item != _qh_list; item = _qh_list->next) { + qh = list_entry(item, dwc_otg_qh_t, qh_list_entry); + dwc_otg_hcd_qh_remove_and_free(_hcd, qh); + } +} + +/** + * Halts the DWC_otg host mode operations in a clean manner. USB transfers are + * stopped. + */ +void dwc_otg_hcd_stop(struct usb_hcd *_hcd) +{ + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd); + hprt0_data_t hprt0 = { .d32=0 }; + + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n"); + + /* Turn off all host-specific interrupts. */ + dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if ); + + /* + * The root hub should be disconnected before this function is called. + * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) + * and the QH lists (via ..._hcd_endpoint_disable). + */ + + /* Turn off the vbus power */ + DWC_PRINT("PortPower off\n"); + hprt0.b.prtpwr = 0; + dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32); + + return; +} + + +/** Returns the current frame number. */ +int dwc_otg_hcd_get_frame_number(struct usb_hcd *_hcd) +{ + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd); + hfnum_data_t hfnum; + + hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if-> + host_if->host_global_regs->hfnum); + +#ifdef DEBUG_SOF + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", hfnum.b.frnum); +#endif + return hfnum.b.frnum; +} + +/** + * Frees secondary storage associated with the dwc_otg_hcd structure contained + * in the struct usb_hcd field. + */ +void dwc_otg_hcd_free(struct usb_hcd *_hcd) +{ + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd); + int i; + + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n"); + + del_timers(dwc_otg_hcd); + + /* Free memory for QH/QTD lists */ + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive); + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_deferred); + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active); + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive); + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready); + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned); + qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued); + + /* Free memory for the host channels. */ + for (i = 0; i < MAX_EPS_CHANNELS; i++) { + dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i]; + if (hc != NULL) { + DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", i, hc); + kfree(hc); + } + } + + if (dwc_otg_hcd->core_if->dma_enable) { + if (dwc_otg_hcd->status_buf_dma) { + dma_free_coherent(_hcd->self.controller, + DWC_OTG_HCD_STATUS_BUF_SIZE, + dwc_otg_hcd->status_buf, + dwc_otg_hcd->status_buf_dma); + } + } else if (dwc_otg_hcd->status_buf != NULL) { + kfree(dwc_otg_hcd->status_buf); + } + + return; +} + + +#ifdef DEBUG +static void dump_urb_info(struct urb *_urb, char* _fn_name) +{ + DWC_PRINT("%s, urb %p\n", _fn_name, _urb); + DWC_PRINT(" Device address: %d\n", usb_pipedevice(_urb->pipe)); + DWC_PRINT(" Endpoint: %d, %s\n", usb_pipeendpoint(_urb->pipe), + (usb_pipein(_urb->pipe) ? "IN" : "OUT")); + DWC_PRINT(" Endpoint type: %s\n", + ({char *pipetype; + switch (usb_pipetype(_urb->pipe)) { + case PIPE_CONTROL: pipetype = "CONTROL"; break; + case PIPE_BULK: pipetype = "BULK"; break; + case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break; + case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break; + default: pipetype = "UNKNOWN"; break; + }; pipetype;})); + DWC_PRINT(" Speed: %s\n", + ({char *speed; + switch (_urb->dev->speed) { + case USB_SPEED_HIGH: speed = "HIGH"; break; + case USB_SPEED_FULL: speed = "FULL"; break; + case USB_SPEED_LOW: speed = "LOW"; break; + default: speed = "UNKNOWN"; break; + }; speed;})); + DWC_PRINT(" Max packet size: %d\n", + usb_maxpacket(_urb->dev, _urb->pipe, usb_pipeout(_urb->pipe))); + DWC_PRINT(" Data buffer length: %d\n", _urb->transfer_buffer_length); + DWC_PRINT(" Transfer buffer: %p, Transfer DMA: %p\n", + _urb->transfer_buffer, (void *)_urb->transfer_dma); + DWC_PRINT(" Setup buffer: %p, Setup DMA: %p\n", + _urb->setup_packet, (void *)_urb->setup_dma); + DWC_PRINT(" Interval: %d\n", _urb->interval); + if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) { + int i; + for (i = 0; i < _urb->number_of_packets; i++) { + DWC_PRINT(" ISO Desc %d:\n", i); + DWC_PRINT(" offset: %d, length %d\n", + _urb->iso_frame_desc[i].offset, + _urb->iso_frame_desc[i].length); + } + } +} + +static void dump_channel_info(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *qh) +{ + if (qh->channel != NULL) { + dwc_hc_t *hc = qh->channel; + struct list_head *item; + dwc_otg_qh_t *qh_item; + int num_channels = _hcd->core_if->core_params->host_channels; + int i; + + dwc_otg_hc_regs_t *hc_regs; + hcchar_data_t hcchar; + hcsplt_data_t hcsplt; + hctsiz_data_t hctsiz; + uint32_t hcdma; + + hc_regs = _hcd->core_if->host_if->hc_regs[hc->hc_num]; + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt); + hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); + hcdma = dwc_read_reg32(&hc_regs->hcdma); + + DWC_PRINT(" Assigned to channel %p:\n", hc); + DWC_PRINT(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32); + DWC_PRINT(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma); + DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n", + hc->dev_addr, hc->ep_num, hc->ep_is_in); + DWC_PRINT(" ep_type: %d\n", hc->ep_type); + DWC_PRINT(" max_packet: %d\n", hc->max_packet); + DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start); + DWC_PRINT(" xfer_started: %d\n", hc->xfer_started); + DWC_PRINT(" halt_status: %d\n", hc->halt_status); + DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff); + DWC_PRINT(" xfer_len: %d\n", hc->xfer_len); + DWC_PRINT(" qh: %p\n", hc->qh); + DWC_PRINT(" NP inactive sched:\n"); + list_for_each(item, &_hcd->non_periodic_sched_inactive) { + qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry); + DWC_PRINT(" %p\n", qh_item); + } DWC_PRINT(" NP active sched:\n"); + list_for_each(item, &_hcd->non_periodic_sched_deferred) { + qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry); + DWC_PRINT(" %p\n", qh_item); + } DWC_PRINT(" NP deferred sched:\n"); + list_for_each(item, &_hcd->non_periodic_sched_active) { + qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry); + DWC_PRINT(" %p\n", qh_item); + } DWC_PRINT(" Channels: \n"); + for (i = 0; i < num_channels; i++) { + dwc_hc_t *hc = _hcd->hc_ptr_array[i]; + DWC_PRINT(" %2d: %p\n", i, hc); + } + } +} +#endif // DEBUG + +/** Starts processing a USB transfer request specified by a USB Request Block + * (URB). mem_flags indicates the type of memory allocation to use while + * processing this URB. */ +int dwc_otg_hcd_urb_enqueue(struct usb_hcd *_hcd, + struct urb *_urb, + gfp_t _mem_flags) +{ + unsigned long flags; + int retval; + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd); + dwc_otg_qtd_t *qtd; + + local_irq_save(flags); + retval = usb_hcd_link_urb_to_ep(_hcd, _urb); + if (retval) { + local_irq_restore(flags); + return retval; + } +#ifdef DEBUG + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { + dump_urb_info(_urb, "dwc_otg_hcd_urb_enqueue"); + } +#endif // DEBUG + if (!dwc_otg_hcd->flags.b.port_connect_status) { + /* No longer connected. */ + local_irq_restore(flags); + return -ENODEV; + } + + qtd = dwc_otg_hcd_qtd_create (_urb); + if (qtd == NULL) { + local_irq_restore(flags); + DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n"); + return -ENOMEM; + } + + retval = dwc_otg_hcd_qtd_add (qtd, dwc_otg_hcd); + if (retval < 0) { + DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. " + "Error status %d\n", retval); + dwc_otg_hcd_qtd_free(qtd); + } + + local_irq_restore (flags); + return retval; +} + +/** Aborts/cancels a USB transfer request. Always returns 0 to indicate + * success. */ +int dwc_otg_hcd_urb_dequeue(struct usb_hcd *_hcd, struct urb *_urb, int _status) +{ + unsigned long flags; + dwc_otg_hcd_t *dwc_otg_hcd; + dwc_otg_qtd_t *urb_qtd; + dwc_otg_qh_t *qh; + int retval; + //struct usb_host_endpoint *_ep = NULL; + + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n"); + + local_irq_save(flags); + + retval = usb_hcd_check_unlink_urb(_hcd, _urb, _status); + if (retval) { + local_irq_restore(flags); + return retval; + } + + dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd); + urb_qtd = (dwc_otg_qtd_t *)_urb->hcpriv; + if (urb_qtd == NULL) { + printk("urb_qtd is NULL for _urb %08x\n",(unsigned)_urb); + goto done; + } + qh = (dwc_otg_qh_t *) urb_qtd->qtd_qh_ptr; + if (qh == NULL) { + goto done; + } + +#ifdef DEBUG + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { + dump_urb_info(_urb, "dwc_otg_hcd_urb_dequeue"); + if (urb_qtd == qh->qtd_in_process) { + dump_channel_info(dwc_otg_hcd, qh); + } + } +#endif // DEBUG + + if (urb_qtd == qh->qtd_in_process) { + /* The QTD is in process (it has been assigned to a channel). */ + + if (dwc_otg_hcd->flags.b.port_connect_status) { + /* + * If still connected (i.e. in host mode), halt the + * channel so it can be used for other transfers. If + * no longer connected, the host registers can't be + * written to halt the channel since the core is in + * device mode. + */ + dwc_otg_hc_halt(dwc_otg_hcd->core_if, qh->channel, + DWC_OTG_HC_XFER_URB_DEQUEUE); + } + } + + /* + * Free the QTD and clean up the associated QH. Leave the QH in the + * schedule if it has any remaining QTDs. + */ + dwc_otg_hcd_qtd_remove_and_free(urb_qtd); + if (urb_qtd == qh->qtd_in_process) { + dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0); + qh->channel = NULL; + qh->qtd_in_process = NULL; + } else if (list_empty(&qh->qtd_list)) { + dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh); + } + +done: + local_irq_restore(flags); + _urb->hcpriv = NULL; + + /* Higher layer software sets URB status. */ + usb_hcd_unlink_urb_from_ep(_hcd, _urb); + usb_hcd_giveback_urb(_hcd, _urb, _status); + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { + DWC_PRINT("Called usb_hcd_giveback_urb()\n"); + DWC_PRINT(" urb->status = %d\n", _urb->status); + } + + return 0; +} + + +/** Frees resources in the DWC_otg controller related to a given endpoint. Also + * clears state in the HCD related to the endpoint. Any URBs for the endpoint + * must already be dequeued. */ +void dwc_otg_hcd_endpoint_disable(struct usb_hcd *_hcd, + struct usb_host_endpoint *_ep) + +{ + dwc_otg_qh_t *qh; + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd); + + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, " + "endpoint=%d\n", _ep->desc.bEndpointAddress, + dwc_ep_addr_to_endpoint(_ep->desc.bEndpointAddress)); + + qh = (dwc_otg_qh_t *)(_ep->hcpriv); + if (qh != NULL) { +#ifdef DEBUG + /** Check that the QTD list is really empty */ + if (!list_empty(&qh->qtd_list)) { + DWC_WARN("DWC OTG HCD EP DISABLE:" + " QTD List for this endpoint is not empty\n"); + } +#endif // DEBUG + + dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh); + _ep->hcpriv = NULL; + } + + return; +} +extern int dwc_irq; +/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if + * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid + * interrupt. + * + * This function is called by the USB core when an interrupt occurs */ +irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *_hcd) +{ + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd); + + mask_and_ack_ifx_irq (dwc_irq); + return IRQ_RETVAL(dwc_otg_hcd_handle_intr(dwc_otg_hcd)); +} + +/** Creates Status Change bitmap for the root hub and root port. The bitmap is + * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 + * is the status change indicator for the single root port. Returns 1 if either + * change indicator is 1, otherwise returns 0. */ +int dwc_otg_hcd_hub_status_data(struct usb_hcd *_hcd, char *_buf) +{ + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd); + + _buf[0] = 0; + _buf[0] |= (dwc_otg_hcd->flags.b.port_connect_status_change || + dwc_otg_hcd->flags.b.port_reset_change || + dwc_otg_hcd->flags.b.port_enable_change || + dwc_otg_hcd->flags.b.port_suspend_change || + dwc_otg_hcd->flags.b.port_over_current_change) << 1; + +#ifdef DEBUG + if (_buf[0]) { + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:" + " Root port status changed\n"); + DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n", + dwc_otg_hcd->flags.b.port_connect_status_change); + DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n", + dwc_otg_hcd->flags.b.port_reset_change); + DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n", + dwc_otg_hcd->flags.b.port_enable_change); + DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n", + dwc_otg_hcd->flags.b.port_suspend_change); + DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n", + dwc_otg_hcd->flags.b.port_over_current_change); + } +#endif // DEBUG + return (_buf[0] != 0); +} + +#ifdef DWC_HS_ELECT_TST +/* + * Quick and dirty hack to implement the HS Electrical Test + * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature. + * + * This code was copied from our userspace app "hset". It sends a + * Get Device Descriptor control sequence in two parts, first the + * Setup packet by itself, followed some time later by the In and + * Ack packets. Rather than trying to figure out how to add this + * functionality to the normal driver code, we just hijack the + * hardware, using these two function to drive the hardware + * directly. + */ + +dwc_otg_core_global_regs_t *global_regs; +dwc_otg_host_global_regs_t *hc_global_regs; +dwc_otg_hc_regs_t *hc_regs; +uint32_t *data_fifo; + +static void do_setup(void) +{ + gintsts_data_t gintsts; + hctsiz_data_t hctsiz; + hcchar_data_t hcchar; + haint_data_t haint; + hcint_data_t hcint; + + /* Enable HAINTs */ + dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001); + + /* Enable HCINTs */ + dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* Read HAINT */ + haint.d32 = dwc_read_reg32(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + dwc_write_reg32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + dwc_write_reg32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* + * Send Setup packet (Get Device Descriptor) + */ + + /* Make sure channel is disabled */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + if (hcchar.b.chen) { + //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32); + hcchar.b.chdis = 1; + // hcchar.b.chen = 1; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + //sleep(1); + MDELAY(1000); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* Read HAINT */ + haint.d32 = dwc_read_reg32(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + dwc_write_reg32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + dwc_write_reg32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //if (hcchar.b.chen) { + // fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32); + //} + } + + /* Set HCTSIZ */ + hctsiz.d32 = 0; + hctsiz.b.xfersize = 8; + hctsiz.b.pktcnt = 1; + hctsiz.b.pid = DWC_OTG_HC_PID_SETUP; + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); + + /* Set HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; + hcchar.b.epdir = 0; + hcchar.b.epnum = 0; + hcchar.b.mps = 8; + hcchar.b.chen = 1; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + + /* Fill FIFO with Setup data for Get Device Descriptor */ + data_fifo = (uint32_t *)((char *)global_regs + 0x1000); + dwc_write_reg32(data_fifo++, 0x01000680); + dwc_write_reg32(data_fifo++, 0x00080000); + + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32); + + /* Wait for host channel interrupt */ + do { + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + } while (gintsts.b.hcintr == 0); + + //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32); + + /* Disable HCINTs */ + dwc_write_reg32(&hc_regs->hcintmsk, 0x0000); + + /* Disable HAINTs */ + dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000); + + /* Read HAINT */ + haint.d32 = dwc_read_reg32(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + dwc_write_reg32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + dwc_write_reg32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); +} + +static void do_in_ack(void) +{ + gintsts_data_t gintsts; + hctsiz_data_t hctsiz; + hcchar_data_t hcchar; + haint_data_t haint; + hcint_data_t hcint; + host_grxsts_data_t grxsts; + + /* Enable HAINTs */ + dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001); + + /* Enable HCINTs */ + dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* Read HAINT */ + haint.d32 = dwc_read_reg32(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + dwc_write_reg32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + dwc_write_reg32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* + * Receive Control In packet + */ + + /* Make sure channel is disabled */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + if (hcchar.b.chen) { + //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32); + hcchar.b.chdis = 1; + hcchar.b.chen = 1; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + //sleep(1); + MDELAY(1000); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* Read HAINT */ + haint.d32 = dwc_read_reg32(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + dwc_write_reg32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + dwc_write_reg32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //if (hcchar.b.chen) { + // fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32); + //} + } + + /* Set HCTSIZ */ + hctsiz.d32 = 0; + hctsiz.b.xfersize = 8; + hctsiz.b.pktcnt = 1; + hctsiz.b.pid = DWC_OTG_HC_PID_DATA1; + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); + + /* Set HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; + hcchar.b.epdir = 1; + hcchar.b.epnum = 0; + hcchar.b.mps = 8; + hcchar.b.chen = 1; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32); + + /* Wait for receive status queue interrupt */ + do { + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + } while (gintsts.b.rxstsqlvl == 0); + + //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32); + + /* Read RXSTS */ + grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp); + //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32); + + /* Clear RXSTSQLVL in GINTSTS */ + gintsts.d32 = 0; + gintsts.b.rxstsqlvl = 1; + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + switch (grxsts.b.pktsts) { + case DWC_GRXSTS_PKTSTS_IN: + /* Read the data into the host buffer */ + if (grxsts.b.bcnt > 0) { + int i; + int word_count = (grxsts.b.bcnt + 3) / 4; + + data_fifo = (uint32_t *)((char *)global_regs + 0x1000); + + for (i = 0; i < word_count; i++) { + (void)dwc_read_reg32(data_fifo++); + } + } + + //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.b.bcnt); + break; + + default: + //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n"); + break; + } + + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32); + + /* Wait for receive status queue interrupt */ + do { + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + } while (gintsts.b.rxstsqlvl == 0); + + //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32); + + /* Read RXSTS */ + grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp); + //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32); + + /* Clear RXSTSQLVL in GINTSTS */ + gintsts.d32 = 0; + gintsts.b.rxstsqlvl = 1; + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + switch (grxsts.b.pktsts) { + case DWC_GRXSTS_PKTSTS_IN_XFER_COMP: + break; + + default: + //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n"); + break; + } + + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32); + + /* Wait for host channel interrupt */ + do { + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + } while (gintsts.b.hcintr == 0); + + //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32); + + /* Read HAINT */ + haint.d32 = dwc_read_reg32(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + dwc_write_reg32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + dwc_write_reg32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + // usleep(100000); + // mdelay(100); + MDELAY(1); + + /* + * Send handshake packet + */ + + /* Read HAINT */ + haint.d32 = dwc_read_reg32(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + dwc_write_reg32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + dwc_write_reg32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* Make sure channel is disabled */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + if (hcchar.b.chen) { + //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32); + hcchar.b.chdis = 1; + hcchar.b.chen = 1; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + //sleep(1); + MDELAY(1000); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* Read HAINT */ + haint.d32 = dwc_read_reg32(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + dwc_write_reg32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + dwc_write_reg32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //if (hcchar.b.chen) { + // fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32); + //} + } + + /* Set HCTSIZ */ + hctsiz.d32 = 0; + hctsiz.b.xfersize = 0; + hctsiz.b.pktcnt = 1; + hctsiz.b.pid = DWC_OTG_HC_PID_DATA1; + dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); + + /* Set HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; + hcchar.b.epdir = 0; + hcchar.b.epnum = 0; + hcchar.b.mps = 8; + hcchar.b.chen = 1; + dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); + + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32); + + /* Wait for host channel interrupt */ + do { + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + } while (gintsts.b.hcintr == 0); + + //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32); + + /* Disable HCINTs */ + dwc_write_reg32(&hc_regs->hcintmsk, 0x0000); + + /* Disable HAINTs */ + dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000); + + /* Read HAINT */ + haint.d32 = dwc_read_reg32(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + dwc_write_reg32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + dwc_write_reg32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + dwc_write_reg32(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ + gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); +} +#endif /* DWC_HS_ELECT_TST */ + +/** Handles hub class-specific requests.*/ +int dwc_otg_hcd_hub_control(struct usb_hcd *_hcd, + u16 _typeReq, + u16 _wValue, + u16 _wIndex, + char *_buf, + u16 _wLength) +{ + int retval = 0; + + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd); + dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd (_hcd)->core_if; + struct usb_hub_descriptor *desc; + hprt0_data_t hprt0 = {.d32 = 0}; + + uint32_t port_status; + + switch (_typeReq) { + case ClearHubFeature: + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "ClearHubFeature 0x%x\n", _wValue); + switch (_wValue) { + case C_HUB_LOCAL_POWER: + case C_HUB_OVER_CURRENT: + /* Nothing required here */ + break; + default: + retval = -EINVAL; + DWC_ERROR ("DWC OTG HCD - " + "ClearHubFeature request %xh unknown\n", _wValue); + } + break; + case ClearPortFeature: + if (!_wIndex || _wIndex > 1) + goto error; + + switch (_wValue) { + case USB_PORT_FEAT_ENABLE: + DWC_DEBUGPL (DBG_ANY, "DWC OTG HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); + hprt0.d32 = dwc_otg_read_hprt0 (core_if); + hprt0.b.prtena = 1; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + break; + case USB_PORT_FEAT_SUSPEND: + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); + hprt0.d32 = dwc_otg_read_hprt0 (core_if); + hprt0.b.prtres = 1; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + /* Clear Resume bit */ + mdelay (100); + hprt0.b.prtres = 0; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + break; + case USB_PORT_FEAT_POWER: + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_POWER\n"); + hprt0.d32 = dwc_otg_read_hprt0 (core_if); + hprt0.b.prtpwr = 0; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + break; + case USB_PORT_FEAT_INDICATOR: + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); + /* Port inidicator not supported */ + break; + case USB_PORT_FEAT_C_CONNECTION: + /* Clears drivers internal connect status change + * flag */ + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); + dwc_otg_hcd->flags.b.port_connect_status_change = 0; + break; + case USB_PORT_FEAT_C_RESET: + /* Clears the driver's internal Port Reset Change + * flag */ + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); + dwc_otg_hcd->flags.b.port_reset_change = 0; + break; + case USB_PORT_FEAT_C_ENABLE: + /* Clears the driver's internal Port + * Enable/Disable Change flag */ + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); + dwc_otg_hcd->flags.b.port_enable_change = 0; + break; + case USB_PORT_FEAT_C_SUSPEND: + /* Clears the driver's internal Port Suspend + * Change flag, which is set when resume signaling on + * the host port is complete */ + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); + dwc_otg_hcd->flags.b.port_suspend_change = 0; + break; + case USB_PORT_FEAT_C_OVER_CURRENT: + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); + dwc_otg_hcd->flags.b.port_over_current_change = 0; + break; + default: + retval = -EINVAL; + DWC_ERROR ("DWC OTG HCD - " + "ClearPortFeature request %xh " + "unknown or unsupported\n", _wValue); + } + break; + case GetHubDescriptor: + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "GetHubDescriptor\n"); + desc = (struct usb_hub_descriptor *)_buf; + desc->bDescLength = 9; + desc->bDescriptorType = 0x29; + desc->bNbrPorts = 1; + desc->wHubCharacteristics = 0x08; + desc->bPwrOn2PwrGood = 1; + desc->bHubContrCurrent = 0; + desc->u.hs.DeviceRemovable[0] = 0; + desc->u.hs.DeviceRemovable[1] = 0xff; + break; + case GetHubStatus: + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "GetHubStatus\n"); + memset (_buf, 0, 4); + break; + case GetPortStatus: + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "GetPortStatus\n"); + + if (!_wIndex || _wIndex > 1) + goto error; + + port_status = 0; + + if (dwc_otg_hcd->flags.b.port_connect_status_change) + port_status |= (1 << USB_PORT_FEAT_C_CONNECTION); + + if (dwc_otg_hcd->flags.b.port_enable_change) + port_status |= (1 << USB_PORT_FEAT_C_ENABLE); + + if (dwc_otg_hcd->flags.b.port_suspend_change) + port_status |= (1 << USB_PORT_FEAT_C_SUSPEND); + + if (dwc_otg_hcd->flags.b.port_reset_change) + port_status |= (1 << USB_PORT_FEAT_C_RESET); + + if (dwc_otg_hcd->flags.b.port_over_current_change) { + DWC_ERROR("Device Not Supported\n"); + port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT); + } + + if (!dwc_otg_hcd->flags.b.port_connect_status) { + printk("DISCONNECTED PORT\n"); + /* + * The port is disconnected, which means the core is + * either in device mode or it soon will be. Just + * return 0's for the remainder of the port status + * since the port register can't be read if the core + * is in device mode. + */ +#if 1 // winder. + *((u32 *) _buf) = cpu_to_le32(port_status); +#else + *((__le32 *) _buf) = cpu_to_le32(port_status); +#endif + break; + } + + hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0); + DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32); + + if (hprt0.b.prtconnsts) + port_status |= (1 << USB_PORT_FEAT_CONNECTION); + + if (hprt0.b.prtena) + port_status |= (1 << USB_PORT_FEAT_ENABLE); + + if (hprt0.b.prtsusp) + port_status |= (1 << USB_PORT_FEAT_SUSPEND); + + if (hprt0.b.prtovrcurract) + port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT); + + if (hprt0.b.prtrst) + port_status |= (1 << USB_PORT_FEAT_RESET); + + if (hprt0.b.prtpwr) + port_status |= (1 << USB_PORT_FEAT_POWER); + + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) + port_status |= USB_PORT_STAT_HIGH_SPEED; + + else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED) + port_status |= (1 << USB_PORT_FEAT_LOWSPEED); + + if (hprt0.b.prttstctl) + port_status |= (1 << USB_PORT_FEAT_TEST); + + /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ +#if 1 // winder. + *((u32 *) _buf) = cpu_to_le32(port_status); +#else + *((__le32 *) _buf) = cpu_to_le32(port_status); +#endif + + break; + case SetHubFeature: + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "SetHubFeature\n"); + /* No HUB features supported */ + break; + case SetPortFeature: + if (_wValue != USB_PORT_FEAT_TEST && (!_wIndex || _wIndex > 1)) + goto error; + + if (!dwc_otg_hcd->flags.b.port_connect_status) { + /* + * The port is disconnected, which means the core is + * either in device mode or it soon will be. Just + * return without doing anything since the port + * register can't be written if the core is in device + * mode. + */ + break; + } + + switch (_wValue) { + case USB_PORT_FEAT_SUSPEND: + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); + if (_hcd->self.otg_port == _wIndex + && _hcd->self.b_hnp_enable) { + gotgctl_data_t gotgctl = {.d32=0}; + gotgctl.b.hstsethnpen = 1; + dwc_modify_reg32(&core_if->core_global_regs-> + gotgctl, 0, gotgctl.d32); + core_if->op_state = A_SUSPEND; + } + hprt0.d32 = dwc_otg_read_hprt0 (core_if); + hprt0.b.prtsusp = 1; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + //DWC_PRINT( "SUSPEND: HPRT0=%0x\n", hprt0.d32); + /* Suspend the Phy Clock */ + { + pcgcctl_data_t pcgcctl = {.d32=0}; + pcgcctl.b.stoppclk = 1; + dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32); + } + + /* For HNP the bus must be suspended for at least 200ms.*/ + if (_hcd->self.b_hnp_enable) { + mdelay(200); + //DWC_PRINT( "SUSPEND: wait complete! (%d)\n", _hcd->state); + } + break; + case USB_PORT_FEAT_POWER: + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "SetPortFeature - USB_PORT_FEAT_POWER\n"); + hprt0.d32 = dwc_otg_read_hprt0 (core_if); + hprt0.b.prtpwr = 1; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + break; + case USB_PORT_FEAT_RESET: + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "SetPortFeature - USB_PORT_FEAT_RESET\n"); + hprt0.d32 = dwc_otg_read_hprt0 (core_if); + /* TODO: Is this for OTG protocol?? + * We shoudl remove OTG totally for Danube system. + * But, in the future, maybe we need this. + */ +#if 1 // winder + hprt0.b.prtrst = 1; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); +#else + /* When B-Host the Port reset bit is set in + * the Start HCD Callback function, so that + * the reset is started within 1ms of the HNP + * success interrupt. */ + if (!_hcd->self.is_b_host) { + hprt0.b.prtrst = 1; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + } +#endif + /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ + MDELAY (60); + hprt0.b.prtrst = 0; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + break; + +#ifdef DWC_HS_ELECT_TST + case USB_PORT_FEAT_TEST: + { + uint32_t t; + gintmsk_data_t gintmsk; + + t = (_wIndex >> 8); /* MSB wIndex USB */ + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t); + printk("USB_PORT_FEAT_TEST %d\n", t); + if (t < 6) { + hprt0.d32 = dwc_otg_read_hprt0 (core_if); + hprt0.b.prttstctl = t; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + } else { + /* Setup global vars with reg addresses (quick and + * dirty hack, should be cleaned up) + */ + global_regs = core_if->core_global_regs; + hc_global_regs = core_if->host_if->host_global_regs; + hc_regs = (dwc_otg_hc_regs_t *)((char *)global_regs + 0x500); + data_fifo = (uint32_t *)((char *)global_regs + 0x1000); + + if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */ + /* Save current interrupt mask */ + gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); + + /* Disable all interrupts while we muck with + * the hardware directly + */ + dwc_write_reg32(&global_regs->gintmsk, 0); + + /* 15 second delay per the test spec */ + mdelay(15000); + + /* Drive suspend on the root port */ + hprt0.d32 = dwc_otg_read_hprt0 (core_if); + hprt0.b.prtsusp = 1; + hprt0.b.prtres = 0; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + + /* 15 second delay per the test spec */ + mdelay(15000); + + /* Drive resume on the root port */ + hprt0.d32 = dwc_otg_read_hprt0 (core_if); + hprt0.b.prtsusp = 0; + hprt0.b.prtres = 1; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + mdelay(100); + + /* Clear the resume bit */ + hprt0.b.prtres = 0; + dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); + + /* Restore interrupts */ + dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); + } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */ + /* Save current interrupt mask */ + gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); + + /* Disable all interrupts while we muck with + * the hardware directly + */ + dwc_write_reg32(&global_regs->gintmsk, 0); + + /* 15 second delay per the test spec */ + mdelay(15000); + + /* Send the Setup packet */ + do_setup(); + + /* 15 second delay so nothing else happens for awhile */ + mdelay(15000); + + /* Restore interrupts */ + dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); + } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */ + /* Save current interrupt mask */ + gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); + + /* Disable all interrupts while we muck with + * the hardware directly + */ + dwc_write_reg32(&global_regs->gintmsk, 0); + + /* Send the Setup packet */ + do_setup(); + + /* 15 second delay so nothing else happens for awhile */ + mdelay(15000); + + /* Send the In and Ack packets */ + do_in_ack(); + + /* 15 second delay so nothing else happens for awhile */ + mdelay(15000); + + /* Restore interrupts */ + dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); + } + } + break; + } +#endif /* DWC_HS_ELECT_TST */ + + case USB_PORT_FEAT_INDICATOR: + DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); + /* Not supported */ + break; + default: + retval = -EINVAL; + DWC_ERROR ("DWC OTG HCD - " + "SetPortFeature request %xh " + "unknown or unsupported\n", _wValue); + break; + } + break; + default: +error: + retval = -EINVAL; + DWC_WARN ("DWC OTG HCD - " + "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n", + _typeReq, _wIndex, _wValue); + break; + } + + return retval; +} + + +/** + * Assigns transactions from a QTD to a free host channel and initializes the + * host channel to perform the transactions. The host channel is removed from + * the free list. + * + * @param _hcd The HCD state structure. + * @param _qh Transactions from the first QTD for this QH are selected and + * assigned to a free host channel. + */ +static void assign_and_init_hc(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh) +{ + dwc_hc_t *hc; + dwc_otg_qtd_t *qtd; + struct urb *urb; + + DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, _hcd, _qh); + + hc = list_entry(_hcd->free_hc_list.next, dwc_hc_t, hc_list_entry); + + /* Remove the host channel from the free list. */ + list_del_init(&hc->hc_list_entry); + + qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); + urb = qtd->urb; + _qh->channel = hc; + _qh->qtd_in_process = qtd; + + /* + * Use usb_pipedevice to determine device address. This address is + * 0 before the SET_ADDRESS command and the correct address afterward. + */ + hc->dev_addr = usb_pipedevice(urb->pipe); + hc->ep_num = usb_pipeendpoint(urb->pipe); + + if (urb->dev->speed == USB_SPEED_LOW) { + hc->speed = DWC_OTG_EP_SPEED_LOW; + } else if (urb->dev->speed == USB_SPEED_FULL) { + hc->speed = DWC_OTG_EP_SPEED_FULL; + } else { + hc->speed = DWC_OTG_EP_SPEED_HIGH; + } + hc->max_packet = dwc_max_packet(_qh->maxp); + + hc->xfer_started = 0; + hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS; + hc->error_state = (qtd->error_count > 0); + hc->halt_on_queue = 0; + hc->halt_pending = 0; + hc->requests = 0; + + /* + * The following values may be modified in the transfer type section + * below. The xfer_len value may be reduced when the transfer is + * started to accommodate the max widths of the XferSize and PktCnt + * fields in the HCTSIZn register. + */ + hc->do_ping = _qh->ping_state; + hc->ep_is_in = (usb_pipein(urb->pipe) != 0); + hc->data_pid_start = _qh->data_toggle; + hc->multi_count = 1; + + if (_hcd->core_if->dma_enable) { + hc->xfer_buff = (uint8_t *)(u32)urb->transfer_dma + urb->actual_length; + } else { + hc->xfer_buff = (uint8_t *)urb->transfer_buffer + urb->actual_length; + } + hc->xfer_len = urb->transfer_buffer_length - urb->actual_length; + hc->xfer_count = 0; + + /* + * Set the split attributes + */ + hc->do_split = 0; + if (_qh->do_split) { + hc->do_split = 1; + hc->xact_pos = qtd->isoc_split_pos; + hc->complete_split = qtd->complete_split; + hc->hub_addr = urb->dev->tt->hub->devnum; + hc->port_addr = urb->dev->ttport; + } + + switch (usb_pipetype(urb->pipe)) { + case PIPE_CONTROL: + hc->ep_type = DWC_OTG_EP_TYPE_CONTROL; + switch (qtd->control_phase) { + case DWC_OTG_CONTROL_SETUP: + DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n"); + hc->do_ping = 0; + hc->ep_is_in = 0; + hc->data_pid_start = DWC_OTG_HC_PID_SETUP; + if (_hcd->core_if->dma_enable) { + hc->xfer_buff = (uint8_t *)(u32)urb->setup_dma; + } else { + hc->xfer_buff = (uint8_t *)urb->setup_packet; + } + hc->xfer_len = 8; + break; + case DWC_OTG_CONTROL_DATA: + DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n"); + hc->data_pid_start = qtd->data_toggle; + break; + case DWC_OTG_CONTROL_STATUS: + /* + * Direction is opposite of data direction or IN if no + * data. + */ + DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n"); + if (urb->transfer_buffer_length == 0) { + hc->ep_is_in = 1; + } else { + hc->ep_is_in = (usb_pipein(urb->pipe) != USB_DIR_IN); + } + if (hc->ep_is_in) { + hc->do_ping = 0; + } + hc->data_pid_start = DWC_OTG_HC_PID_DATA1; + hc->xfer_len = 0; + if (_hcd->core_if->dma_enable) { + hc->xfer_buff = (uint8_t *)_hcd->status_buf_dma; + } else { + hc->xfer_buff = (uint8_t *)_hcd->status_buf; + } + break; + } + break; + case PIPE_BULK: + hc->ep_type = DWC_OTG_EP_TYPE_BULK; + break; + case PIPE_INTERRUPT: + hc->ep_type = DWC_OTG_EP_TYPE_INTR; + break; + case PIPE_ISOCHRONOUS: + { + struct usb_iso_packet_descriptor *frame_desc; + frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index]; + hc->ep_type = DWC_OTG_EP_TYPE_ISOC; + if (_hcd->core_if->dma_enable) { + hc->xfer_buff = (uint8_t *)(u32)urb->transfer_dma; + } else { + hc->xfer_buff = (uint8_t *)urb->transfer_buffer; + } + hc->xfer_buff += frame_desc->offset + qtd->isoc_split_offset; + hc->xfer_len = frame_desc->length - qtd->isoc_split_offset; + + if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) { + if (hc->xfer_len <= 188) { + hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL; + } + else { + hc->xact_pos = DWC_HCSPLIT_XACTPOS_BEGIN; + } + } + } + break; + } + + if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { + /* + * This value may be modified when the transfer is started to + * reflect the actual transfer length. + */ + hc->multi_count = dwc_hb_mult(_qh->maxp); + } + + dwc_otg_hc_init(_hcd->core_if, hc); + hc->qh = _qh; +} +#define DEBUG_HOST_CHANNELS +#ifdef DEBUG_HOST_CHANNELS +static int last_sel_trans_num_per_scheduled = 0; +module_param(last_sel_trans_num_per_scheduled, int, 0444); + +static int last_sel_trans_num_nonper_scheduled = 0; +module_param(last_sel_trans_num_nonper_scheduled, int, 0444); + +static int last_sel_trans_num_avail_hc_at_start = 0; +module_param(last_sel_trans_num_avail_hc_at_start, int, 0444); + +static int last_sel_trans_num_avail_hc_at_end = 0; +module_param(last_sel_trans_num_avail_hc_at_end, int, 0444); +#endif /* DEBUG_HOST_CHANNELS */ + +/** + * This function selects transactions from the HCD transfer schedule and + * assigns them to available host channels. It is called from HCD interrupt + * handler functions. + * + * @param _hcd The HCD state structure. + * + * @return The types of new transactions that were assigned to host channels. + */ +dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *_hcd) +{ + struct list_head *qh_ptr; + dwc_otg_qh_t *qh; + int num_channels; + unsigned long flags; + dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE; + +#ifdef DEBUG_SOF + DWC_DEBUGPL(DBG_HCD, " Select Transactions\n"); +#endif /* */ + +#ifdef DEBUG_HOST_CHANNELS + last_sel_trans_num_per_scheduled = 0; + last_sel_trans_num_nonper_scheduled = 0; + last_sel_trans_num_avail_hc_at_start = _hcd->available_host_channels; +#endif /* DEBUG_HOST_CHANNELS */ + + /* Process entries in the periodic ready list. */ + num_channels = _hcd->core_if->core_params->host_channels; + qh_ptr = _hcd->periodic_sched_ready.next; + while (qh_ptr != &_hcd->periodic_sched_ready + && !list_empty(&_hcd->free_hc_list)) { + + // Make sure we leave one channel for non periodic transactions. + local_irq_save(flags); + if (_hcd->available_host_channels <= 1) { + local_irq_restore(flags); + break; + } + _hcd->available_host_channels--; + local_irq_restore(flags); +#ifdef DEBUG_HOST_CHANNELS + last_sel_trans_num_per_scheduled++; +#endif /* DEBUG_HOST_CHANNELS */ + + qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry); + assign_and_init_hc(_hcd, qh); + + /* + * Move the QH from the periodic ready schedule to the + * periodic assigned schedule. + */ + qh_ptr = qh_ptr->next; + local_irq_save(flags); + list_move(&qh->qh_list_entry, &_hcd->periodic_sched_assigned); + local_irq_restore(flags); + ret_val = DWC_OTG_TRANSACTION_PERIODIC; + } + + /* + * Process entries in the deferred portion of the non-periodic list. + * A NAK put them here and, at the right time, they need to be + * placed on the sched_inactive list. + */ + qh_ptr = _hcd->non_periodic_sched_deferred.next; + while (qh_ptr != &_hcd->non_periodic_sched_deferred) { + uint16_t frame_number = + dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd)); + qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry); + qh_ptr = qh_ptr->next; + + if (dwc_frame_num_le(qh->sched_frame, frame_number)) { + // NAK did this + /* + * Move the QH from the non periodic deferred schedule to + * the non periodic inactive schedule. + */ + local_irq_save(flags); + list_move(&qh->qh_list_entry, + &_hcd->non_periodic_sched_inactive); + local_irq_restore(flags); + } + } + + /* + * Process entries in the inactive portion of the non-periodic + * schedule. Some free host channels may not be used if they are + * reserved for periodic transfers. + */ + qh_ptr = _hcd->non_periodic_sched_inactive.next; + num_channels = _hcd->core_if->core_params->host_channels; + while (qh_ptr != &_hcd->non_periodic_sched_inactive + && !list_empty(&_hcd->free_hc_list)) { + + local_irq_save(flags); + if (_hcd->available_host_channels < 1) { + local_irq_restore(flags); + break; + } + _hcd->available_host_channels--; + local_irq_restore(flags); +#ifdef DEBUG_HOST_CHANNELS + last_sel_trans_num_nonper_scheduled++; +#endif /* DEBUG_HOST_CHANNELS */ + + qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry); + assign_and_init_hc(_hcd, qh); + + /* + * Move the QH from the non-periodic inactive schedule to the + * non-periodic active schedule. + */ + qh_ptr = qh_ptr->next; + local_irq_save(flags); + list_move(&qh->qh_list_entry, &_hcd->non_periodic_sched_active); + local_irq_restore(flags); + + if (ret_val == DWC_OTG_TRANSACTION_NONE) { + ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC; + } else { + ret_val = DWC_OTG_TRANSACTION_ALL; + } + + } +#ifdef DEBUG_HOST_CHANNELS + last_sel_trans_num_avail_hc_at_end = _hcd->available_host_channels; +#endif /* DEBUG_HOST_CHANNELS */ + + return ret_val; +} + +/** + * Attempts to queue a single transaction request for a host channel + * associated with either a periodic or non-periodic transfer. This function + * assumes that there is space available in the appropriate request queue. For + * an OUT transfer or SETUP transaction in Slave mode, it checks whether space + * is available in the appropriate Tx FIFO. + * + * @param _hcd The HCD state structure. + * @param _hc Host channel descriptor associated with either a periodic or + * non-periodic transfer. + * @param _fifo_dwords_avail Number of DWORDs available in the periodic Tx + * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic + * transfers. + * + * @return 1 if a request is queued and more requests may be needed to + * complete the transfer, 0 if no more requests are required for this + * transfer, -1 if there is insufficient space in the Tx FIFO. + */ +static int queue_transaction(dwc_otg_hcd_t *_hcd, + dwc_hc_t *_hc, + uint16_t _fifo_dwords_avail) +{ + int retval; + + if (_hcd->core_if->dma_enable) { + if (!_hc->xfer_started) { + dwc_otg_hc_start_transfer(_hcd->core_if, _hc); + _hc->qh->ping_state = 0; + } + retval = 0; + } else if (_hc->halt_pending) { + /* Don't queue a request if the channel has been halted. */ + retval = 0; + } else if (_hc->halt_on_queue) { + dwc_otg_hc_halt(_hcd->core_if, _hc, _hc->halt_status); + retval = 0; + } else if (_hc->do_ping) { + if (!_hc->xfer_started) { + dwc_otg_hc_start_transfer(_hcd->core_if, _hc); + } + retval = 0; + } else if (!_hc->ep_is_in || + _hc->data_pid_start == DWC_OTG_HC_PID_SETUP) { + if ((_fifo_dwords_avail * 4) >= _hc->max_packet) { + if (!_hc->xfer_started) { + dwc_otg_hc_start_transfer(_hcd->core_if, _hc); + retval = 1; + } else { + retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc); + } + } else { + retval = -1; + } + } else { + if (!_hc->xfer_started) { + dwc_otg_hc_start_transfer(_hcd->core_if, _hc); + retval = 1; + } else { + retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc); + } + } + + return retval; +} + +/** + * Processes active non-periodic channels and queues transactions for these + * channels to the DWC_otg controller. After queueing transactions, the NP Tx + * FIFO Empty interrupt is enabled if there are more transactions to queue as + * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx + * FIFO Empty interrupt is disabled. + */ +static void process_non_periodic_channels(dwc_otg_hcd_t *_hcd) +{ + gnptxsts_data_t tx_status; + struct list_head *orig_qh_ptr; + dwc_otg_qh_t *qh; + int status; + int no_queue_space = 0; + int no_fifo_space = 0; + int more_to_do = 0; + + dwc_otg_core_global_regs_t *global_regs = _hcd->core_if->core_global_regs; + + DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n"); +#ifdef DEBUG + tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); + DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (before queue): %d\n", + tx_status.b.nptxqspcavail); + DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n", + tx_status.b.nptxfspcavail); +#endif + /* + * Keep track of the starting point. Skip over the start-of-list + * entry. + */ + if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) { + _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next; + } + orig_qh_ptr = _hcd->non_periodic_qh_ptr; + + /* + * Process once through the active list or until no more space is + * available in the request queue or the Tx FIFO. + */ + do { + tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); + if (!_hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) { + no_queue_space = 1; + break; + } + + qh = list_entry(_hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry); + status = queue_transaction(_hcd, qh->channel, tx_status.b.nptxfspcavail); + + if (status > 0) { + more_to_do = 1; + } else if (status < 0) { + no_fifo_space = 1; + break; + } + + /* Advance to next QH, skipping start-of-list entry. */ + _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next; + if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) { + _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next; + } + + } while (_hcd->non_periodic_qh_ptr != orig_qh_ptr); + + if (!_hcd->core_if->dma_enable) { + gintmsk_data_t intr_mask = {.d32 = 0}; + intr_mask.b.nptxfempty = 1; + +#ifdef DEBUG + tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); + DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (after queue): %d\n", + tx_status.b.nptxqspcavail); + DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (after queue): %d\n", + tx_status.b.nptxfspcavail); +#endif + if (more_to_do || no_queue_space || no_fifo_space) { + /* + * May need to queue more transactions as the request + * queue or Tx FIFO empties. Enable the non-periodic + * Tx FIFO empty interrupt. (Always use the half-empty + * level to ensure that new requests are loaded as + * soon as possible.) + */ + dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32); + } else { + /* + * Disable the Tx FIFO empty interrupt since there are + * no more transactions that need to be queued right + * now. This function is called from interrupt + * handlers to queue more transactions as transfer + * states change. + */ + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0); + } + } +} + +/** + * Processes periodic channels for the next frame and queues transactions for + * these channels to the DWC_otg controller. After queueing transactions, the + * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions + * to queue as Periodic Tx FIFO or request queue space becomes available. + * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. + */ +static void process_periodic_channels(dwc_otg_hcd_t *_hcd) +{ + hptxsts_data_t tx_status; + struct list_head *qh_ptr; + dwc_otg_qh_t *qh; + int status; + int no_queue_space = 0; + int no_fifo_space = 0; + + dwc_otg_host_global_regs_t *host_regs; + host_regs = _hcd->core_if->host_if->host_global_regs; + + DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n"); +#ifdef DEBUG + tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); + DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (before queue): %d\n", + tx_status.b.ptxqspcavail); + DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n", + tx_status.b.ptxfspcavail); +#endif + + qh_ptr = _hcd->periodic_sched_assigned.next; + while (qh_ptr != &_hcd->periodic_sched_assigned) { + tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); + if (tx_status.b.ptxqspcavail == 0) { + no_queue_space = 1; + break; + } + + qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry); + + /* + * Set a flag if we're queuing high-bandwidth in slave mode. + * The flag prevents any halts to get into the request queue in + * the middle of multiple high-bandwidth packets getting queued. + */ + if ((!_hcd->core_if->dma_enable) && + (qh->channel->multi_count > 1)) + { + _hcd->core_if->queuing_high_bandwidth = 1; + } + + status = queue_transaction(_hcd, qh->channel, tx_status.b.ptxfspcavail); + if (status < 0) { + no_fifo_space = 1; + break; + } + + /* + * In Slave mode, stay on the current transfer until there is + * nothing more to do or the high-bandwidth request count is + * reached. In DMA mode, only need to queue one request. The + * controller automatically handles multiple packets for + * high-bandwidth transfers. + */ + if (_hcd->core_if->dma_enable || + (status == 0 || + qh->channel->requests == qh->channel->multi_count)) { + qh_ptr = qh_ptr->next; + /* + * Move the QH from the periodic assigned schedule to + * the periodic queued schedule. + */ + list_move(&qh->qh_list_entry, &_hcd->periodic_sched_queued); + + /* done queuing high bandwidth */ + _hcd->core_if->queuing_high_bandwidth = 0; + } + } + + if (!_hcd->core_if->dma_enable) { + dwc_otg_core_global_regs_t *global_regs; + gintmsk_data_t intr_mask = {.d32 = 0}; + + global_regs = _hcd->core_if->core_global_regs; + intr_mask.b.ptxfempty = 1; +#ifdef DEBUG + tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); + DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (after queue): %d\n", + tx_status.b.ptxqspcavail); + DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (after queue): %d\n", + tx_status.b.ptxfspcavail); +#endif + if (!(list_empty(&_hcd->periodic_sched_assigned)) || + no_queue_space || no_fifo_space) { + /* + * May need to queue more transactions as the request + * queue or Tx FIFO empties. Enable the periodic Tx + * FIFO empty interrupt. (Always use the half-empty + * level to ensure that new requests are loaded as + * soon as possible.) + */ + dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32); + } else { + /* + * Disable the Tx FIFO empty interrupt since there are + * no more transactions that need to be queued right + * now. This function is called from interrupt + * handlers to queue more transactions as transfer + * states change. + */ + dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0); + } + } +} + +/** + * This function processes the currently active host channels and queues + * transactions for these channels to the DWC_otg controller. It is called + * from HCD interrupt handler functions. + * + * @param _hcd The HCD state structure. + * @param _tr_type The type(s) of transactions to queue (non-periodic, + * periodic, or both). + */ +void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *_hcd, + dwc_otg_transaction_type_e _tr_type) +{ +#ifdef DEBUG_SOF + DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n"); +#endif + /* Process host channels associated with periodic transfers. */ + if ((_tr_type == DWC_OTG_TRANSACTION_PERIODIC || + _tr_type == DWC_OTG_TRANSACTION_ALL) && + !list_empty(&_hcd->periodic_sched_assigned)) { + + process_periodic_channels(_hcd); + } + + /* Process host channels associated with non-periodic transfers. */ + if ((_tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC || + _tr_type == DWC_OTG_TRANSACTION_ALL)) { + if (!list_empty(&_hcd->non_periodic_sched_active)) { + process_non_periodic_channels(_hcd); + } else { + /* + * Ensure NP Tx FIFO empty interrupt is disabled when + * there are no non-periodic transfers to process. + */ + gintmsk_data_t gintmsk = {.d32 = 0}; + gintmsk.b.nptxfempty = 1; + dwc_modify_reg32(&_hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0); + } + } +} + +/** + * Sets the final status of an URB and returns it to the device driver. Any + * required cleanup of the URB is performed. + */ +void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t * _hcd, struct urb *_urb, + int _status) + __releases(_hcd->lock) +__acquires(_hcd->lock) +{ +#ifdef DEBUG + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { + DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n", + __func__, _urb, usb_pipedevice(_urb->pipe), + usb_pipeendpoint(_urb->pipe), + usb_pipein(_urb->pipe) ? "IN" : "OUT", _status); + if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) { + int i; + for (i = 0; i < _urb->number_of_packets; i++) { + DWC_PRINT(" ISO Desc %d status: %d\n", + i, _urb->iso_frame_desc[i].status); + } + } + } +#endif + + _urb->status = _status; + _urb->hcpriv = NULL; + usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(_hcd), _urb); + spin_unlock(&_hcd->lock); + usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(_hcd), _urb, _status); + spin_lock(&_hcd->lock); +} + +/* + * Returns the Queue Head for an URB. + */ +dwc_otg_qh_t *dwc_urb_to_qh(struct urb *_urb) +{ + struct usb_host_endpoint *ep = dwc_urb_to_endpoint(_urb); + return (dwc_otg_qh_t *)ep->hcpriv; +} + +#ifdef DEBUG +void dwc_print_setup_data (uint8_t *setup) +{ + int i; + if (CHK_DEBUG_LEVEL(DBG_HCD)){ + DWC_PRINT("Setup Data = MSB "); + for (i=7; i>=0; i--) DWC_PRINT ("%02x ", setup[i]); + DWC_PRINT("\n"); + DWC_PRINT(" bmRequestType Tranfer = %s\n", (setup[0]&0x80) ? "Device-to-Host" : "Host-to-Device"); + DWC_PRINT(" bmRequestType Type = "); + switch ((setup[0]&0x60) >> 5) { + case 0: DWC_PRINT("Standard\n"); break; + case 1: DWC_PRINT("Class\n"); break; + case 2: DWC_PRINT("Vendor\n"); break; + case 3: DWC_PRINT("Reserved\n"); break; + } + DWC_PRINT(" bmRequestType Recipient = "); + switch (setup[0]&0x1f) { + case 0: DWC_PRINT("Device\n"); break; + case 1: DWC_PRINT("Interface\n"); break; + case 2: DWC_PRINT("Endpoint\n"); break; + case 3: DWC_PRINT("Other\n"); break; + default: DWC_PRINT("Reserved\n"); break; + } + DWC_PRINT(" bRequest = 0x%0x\n", setup[1]); + DWC_PRINT(" wValue = 0x%0x\n", *((uint16_t *)&setup[2])); + DWC_PRINT(" wIndex = 0x%0x\n", *((uint16_t *)&setup[4])); + DWC_PRINT(" wLength = 0x%0x\n\n", *((uint16_t *)&setup[6])); + } +} +#endif + +void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *_hcd) { +#ifdef DEBUG +#if 0 + DWC_PRINT("Frame remaining at SOF:\n"); + DWC_PRINT(" samples %u, accum %llu, avg %llu\n", + _hcd->frrem_samples, _hcd->frrem_accum, + (_hcd->frrem_samples > 0) ? + _hcd->frrem_accum/_hcd->frrem_samples : 0); + + DWC_PRINT("\n"); + DWC_PRINT("Frame remaining at start_transfer (uframe 7):\n"); + DWC_PRINT(" samples %u, accum %u, avg %u\n", + _hcd->core_if->hfnum_7_samples, _hcd->core_if->hfnum_7_frrem_accum, + (_hcd->core_if->hfnum_7_samples > 0) ? + _hcd->core_if->hfnum_7_frrem_accum/_hcd->core_if->hfnum_7_samples : 0); + DWC_PRINT("Frame remaining at start_transfer (uframe 0):\n"); + DWC_PRINT(" samples %u, accum %u, avg %u\n", + _hcd->core_if->hfnum_0_samples, _hcd->core_if->hfnum_0_frrem_accum, + (_hcd->core_if->hfnum_0_samples > 0) ? + _hcd->core_if->hfnum_0_frrem_accum/_hcd->core_if->hfnum_0_samples : 0); + DWC_PRINT("Frame remaining at start_transfer (uframe 1-6):\n"); + DWC_PRINT(" samples %u, accum %u, avg %u\n", + _hcd->core_if->hfnum_other_samples, _hcd->core_if->hfnum_other_frrem_accum, + (_hcd->core_if->hfnum_other_samples > 0) ? + _hcd->core_if->hfnum_other_frrem_accum/_hcd->core_if->hfnum_other_samples : 0); + + DWC_PRINT("\n"); + DWC_PRINT("Frame remaining at sample point A (uframe 7):\n"); + DWC_PRINT(" samples %u, accum %llu, avg %llu\n", + _hcd->hfnum_7_samples_a, _hcd->hfnum_7_frrem_accum_a, + (_hcd->hfnum_7_samples_a > 0) ? + _hcd->hfnum_7_frrem_accum_a/_hcd->hfnum_7_samples_a : 0); + DWC_PRINT("Frame remaining at sample point A (uframe 0):\n"); + DWC_PRINT(" samples %u, accum %llu, avg %llu\n", + _hcd->hfnum_0_samples_a, _hcd->hfnum_0_frrem_accum_a, + (_hcd->hfnum_0_samples_a > 0) ? + _hcd->hfnum_0_frrem_accum_a/_hcd->hfnum_0_samples_a : 0); + DWC_PRINT("Frame remaining at sample point A (uframe 1-6):\n"); + DWC_PRINT(" samples %u, accum %llu, avg %llu\n", + _hcd->hfnum_other_samples_a, _hcd->hfnum_other_frrem_accum_a, + (_hcd->hfnum_other_samples_a > 0) ? + _hcd->hfnum_other_frrem_accum_a/_hcd->hfnum_other_samples_a : 0); + + DWC_PRINT("\n"); + DWC_PRINT("Frame remaining at sample point B (uframe 7):\n"); + DWC_PRINT(" samples %u, accum %llu, avg %llu\n", + _hcd->hfnum_7_samples_b, _hcd->hfnum_7_frrem_accum_b, + (_hcd->hfnum_7_samples_b > 0) ? + _hcd->hfnum_7_frrem_accum_b/_hcd->hfnum_7_samples_b : 0); + DWC_PRINT("Frame remaining at sample point B (uframe 0):\n"); + DWC_PRINT(" samples %u, accum %llu, avg %llu\n", + _hcd->hfnum_0_samples_b, _hcd->hfnum_0_frrem_accum_b, + (_hcd->hfnum_0_samples_b > 0) ? + _hcd->hfnum_0_frrem_accum_b/_hcd->hfnum_0_samples_b : 0); + DWC_PRINT("Frame remaining at sample point B (uframe 1-6):\n"); + DWC_PRINT(" samples %u, accum %llu, avg %llu\n", + _hcd->hfnum_other_samples_b, _hcd->hfnum_other_frrem_accum_b, + (_hcd->hfnum_other_samples_b > 0) ? + _hcd->hfnum_other_frrem_accum_b/_hcd->hfnum_other_samples_b : 0); +#endif +#endif +} + +void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *_hcd) +{ +#ifdef DEBUG + int num_channels; + int i; + gnptxsts_data_t np_tx_status; + hptxsts_data_t p_tx_status; + + num_channels = _hcd->core_if->core_params->host_channels; + DWC_PRINT("\n"); + DWC_PRINT("************************************************************\n"); + DWC_PRINT("HCD State:\n"); + DWC_PRINT(" Num channels: %d\n", num_channels); + for (i = 0; i < num_channels; i++) { + dwc_hc_t *hc = _hcd->hc_ptr_array[i]; + DWC_PRINT(" Channel %d:\n", i); + DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n", + hc->dev_addr, hc->ep_num, hc->ep_is_in); + DWC_PRINT(" speed: %d\n", hc->speed); + DWC_PRINT(" ep_type: %d\n", hc->ep_type); + DWC_PRINT(" max_packet: %d\n", hc->max_packet); + DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start); + DWC_PRINT(" multi_count: %d\n", hc->multi_count); + DWC_PRINT(" xfer_started: %d\n", hc->xfer_started); + DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff); + DWC_PRINT(" xfer_len: %d\n", hc->xfer_len); + DWC_PRINT(" xfer_count: %d\n", hc->xfer_count); + DWC_PRINT(" halt_on_queue: %d\n", hc->halt_on_queue); + DWC_PRINT(" halt_pending: %d\n", hc->halt_pending); + DWC_PRINT(" halt_status: %d\n", hc->halt_status); + DWC_PRINT(" do_split: %d\n", hc->do_split); + DWC_PRINT(" complete_split: %d\n", hc->complete_split); + DWC_PRINT(" hub_addr: %d\n", hc->hub_addr); + DWC_PRINT(" port_addr: %d\n", hc->port_addr); + DWC_PRINT(" xact_pos: %d\n", hc->xact_pos); + DWC_PRINT(" requests: %d\n", hc->requests); + DWC_PRINT(" qh: %p\n", hc->qh); + if (hc->xfer_started) { + hfnum_data_t hfnum; + hcchar_data_t hcchar; + hctsiz_data_t hctsiz; + hcint_data_t hcint; + hcintmsk_data_t hcintmsk; + hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); + hcchar.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcchar); + hctsiz.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hctsiz); + hcint.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcint); + hcintmsk.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcintmsk); + DWC_PRINT(" hfnum: 0x%08x\n", hfnum.d32); + DWC_PRINT(" hcchar: 0x%08x\n", hcchar.d32); + DWC_PRINT(" hctsiz: 0x%08x\n", hctsiz.d32); + DWC_PRINT(" hcint: 0x%08x\n", hcint.d32); + DWC_PRINT(" hcintmsk: 0x%08x\n", hcintmsk.d32); + } + if (hc->xfer_started && (hc->qh != NULL) && (hc->qh->qtd_in_process != NULL)) { + dwc_otg_qtd_t *qtd; + struct urb *urb; + qtd = hc->qh->qtd_in_process; + urb = qtd->urb; + DWC_PRINT(" URB Info:\n"); + DWC_PRINT(" qtd: %p, urb: %p\n", qtd, urb); + if (urb != NULL) { + DWC_PRINT(" Dev: %d, EP: %d %s\n", + usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe), + usb_pipein(urb->pipe) ? "IN" : "OUT"); + DWC_PRINT(" Max packet size: %d\n", + usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); + DWC_PRINT(" transfer_buffer: %p\n", urb->transfer_buffer); + DWC_PRINT(" transfer_dma: %p\n", (void *)urb->transfer_dma); + DWC_PRINT(" transfer_buffer_length: %d\n", urb->transfer_buffer_length); + DWC_PRINT(" actual_length: %d\n", urb->actual_length); + } + } + } + //DWC_PRINT(" non_periodic_channels: %d\n", _hcd->non_periodic_channels); + //DWC_PRINT(" periodic_channels: %d\n", _hcd->periodic_channels); + DWC_PRINT(" available_channels: %d\n", _hcd->available_host_channels); + DWC_PRINT(" periodic_usecs: %d\n", _hcd->periodic_usecs); + np_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->core_global_regs->gnptxsts); + DWC_PRINT(" NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail); + DWC_PRINT(" NP Tx FIFO Space Avail: %d\n", np_tx_status.b.nptxfspcavail); + p_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hptxsts); + DWC_PRINT(" P Tx Req Queue Space Avail: %d\n", p_tx_status.b.ptxqspcavail); + DWC_PRINT(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail); + dwc_otg_hcd_dump_frrem(_hcd); + dwc_otg_dump_global_registers(_hcd->core_if); + dwc_otg_dump_host_registers(_hcd->core_if); + DWC_PRINT("************************************************************\n"); + DWC_PRINT("\n"); +#endif +} +#endif /* DWC_DEVICE_ONLY */ diff --git a/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_hcd.h b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_hcd.h new file mode 100644 index 0000000000..8a20dffa0a --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_hcd.h @@ -0,0 +1,676 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd.h $ + * $Revision: 1.1.1.1 $ + * $Date: 2009-04-17 06:15:34 $ + * $Change: 537387 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ +#ifndef DWC_DEVICE_ONLY +#if !defined(__DWC_HCD_H__) +#define __DWC_HCD_H__ + +#include +#include +#include + +struct lm_device; +struct dwc_otg_device; + +#include "dwc_otg_cil.h" +//#include "dwc_otg_ifx.h" // winder + + +/** + * @file + * + * This file contains the structures, constants, and interfaces for + * the Host Contoller Driver (HCD). + * + * The Host Controller Driver (HCD) is responsible for translating requests + * from the USB Driver into the appropriate actions on the DWC_otg controller. + * It isolates the USBD from the specifics of the controller by providing an + * API to the USBD. + */ + +/** + * Phases for control transfers. + */ +typedef enum dwc_otg_control_phase { + DWC_OTG_CONTROL_SETUP, + DWC_OTG_CONTROL_DATA, + DWC_OTG_CONTROL_STATUS +} dwc_otg_control_phase_e; + +/** Transaction types. */ +typedef enum dwc_otg_transaction_type { + DWC_OTG_TRANSACTION_NONE, + DWC_OTG_TRANSACTION_PERIODIC, + DWC_OTG_TRANSACTION_NON_PERIODIC, + DWC_OTG_TRANSACTION_ALL +} dwc_otg_transaction_type_e; + +/** + * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, + * interrupt, or isochronous transfer. A single QTD is created for each URB + * (of one of these types) submitted to the HCD. The transfer associated with + * a QTD may require one or multiple transactions. + * + * A QTD is linked to a Queue Head, which is entered in either the + * non-periodic or periodic schedule for execution. When a QTD is chosen for + * execution, some or all of its transactions may be executed. After + * execution, the state of the QTD is updated. The QTD may be retired if all + * its transactions are complete or if an error occurred. Otherwise, it + * remains in the schedule so more transactions can be executed later. + */ +struct dwc_otg_qh; +typedef struct dwc_otg_qtd { + /** + * Determines the PID of the next data packet for the data phase of + * control transfers. Ignored for other transfer types.
+ * One of the following values: + * - DWC_OTG_HC_PID_DATA0 + * - DWC_OTG_HC_PID_DATA1 + */ + uint8_t data_toggle; + + /** Current phase for control transfers (Setup, Data, or Status). */ + dwc_otg_control_phase_e control_phase; + + /** Keep track of the current split type + * for FS/LS endpoints on a HS Hub */ + uint8_t complete_split; + + /** How many bytes transferred during SSPLIT OUT */ + uint32_t ssplit_out_xfer_count; + + /** + * Holds the number of bus errors that have occurred for a transaction + * within this transfer. + */ + uint8_t error_count; + + /** + * Index of the next frame descriptor for an isochronous transfer. A + * frame descriptor describes the buffer position and length of the + * data to be transferred in the next scheduled (micro)frame of an + * isochronous transfer. It also holds status for that transaction. + * The frame index starts at 0. + */ + int isoc_frame_index; + + /** Position of the ISOC split on full/low speed */ + uint8_t isoc_split_pos; + + /** Position of the ISOC split in the buffer for the current frame */ + uint16_t isoc_split_offset; + + /** URB for this transfer */ + struct urb *urb; + + /** This list of QTDs */ + struct list_head qtd_list_entry; + + /* Field to track the qh pointer */ + struct dwc_otg_qh *qtd_qh_ptr; +} dwc_otg_qtd_t; + +/** + * A Queue Head (QH) holds the static characteristics of an endpoint and + * maintains a list of transfers (QTDs) for that endpoint. A QH structure may + * be entered in either the non-periodic or periodic schedule. + */ +typedef struct dwc_otg_qh { + /** + * Endpoint type. + * One of the following values: + * - USB_ENDPOINT_XFER_CONTROL + * - USB_ENDPOINT_XFER_ISOC + * - USB_ENDPOINT_XFER_BULK + * - USB_ENDPOINT_XFER_INT + */ + uint8_t ep_type; + uint8_t ep_is_in; + + /** wMaxPacketSize Field of Endpoint Descriptor. */ + uint16_t maxp; + + /** + * Determines the PID of the next data packet for non-control + * transfers. Ignored for control transfers.
+ * One of the following values: + * - DWC_OTG_HC_PID_DATA0 + * - DWC_OTG_HC_PID_DATA1 + */ + uint8_t data_toggle; + + /** Ping state if 1. */ + uint8_t ping_state; + + /** + * List of QTDs for this QH. + */ + struct list_head qtd_list; + + /** Host channel currently processing transfers for this QH. */ + dwc_hc_t *channel; + + /** QTD currently assigned to a host channel for this QH. */ + dwc_otg_qtd_t *qtd_in_process; + + /** Full/low speed endpoint on high-speed hub requires split. */ + uint8_t do_split; + + /** @name Periodic schedule information */ + /** @{ */ + + /** Bandwidth in microseconds per (micro)frame. */ + uint8_t usecs; + + /** Interval between transfers in (micro)frames. */ + uint16_t interval; + + /** + * (micro)frame to initialize a periodic transfer. The transfer + * executes in the following (micro)frame. + */ + uint16_t sched_frame; + + /** (micro)frame at which last start split was initialized. */ + uint16_t start_split_frame; + + /** @} */ + + uint16_t speed; + uint16_t frame_usecs[8]; + /** Entry for QH in either the periodic or non-periodic schedule. */ + struct list_head qh_list_entry; +} dwc_otg_qh_t; + +/** + * This structure holds the state of the HCD, including the non-periodic and + * periodic schedules. + */ +typedef struct dwc_otg_hcd { + spinlock_t lock; + + /** DWC OTG Core Interface Layer */ + dwc_otg_core_if_t *core_if; + + /** Internal DWC HCD Flags */ + volatile union dwc_otg_hcd_internal_flags { + uint32_t d32; + struct { + unsigned port_connect_status_change : 1; + unsigned port_connect_status : 1; + unsigned port_reset_change : 1; + unsigned port_enable_change : 1; + unsigned port_suspend_change : 1; + unsigned port_over_current_change : 1; + unsigned reserved : 27; + } b; + } flags; + + /** + * Inactive items in the non-periodic schedule. This is a list of + * Queue Heads. Transfers associated with these Queue Heads are not + * currently assigned to a host channel. + */ + struct list_head non_periodic_sched_inactive; + + /** + * Deferred items in the non-periodic schedule. This is a list of + * Queue Heads. Transfers associated with these Queue Heads are not + * currently assigned to a host channel. + * When we get an NAK, the QH goes here. + */ + struct list_head non_periodic_sched_deferred; + + /** + * Active items in the non-periodic schedule. This is a list of + * Queue Heads. Transfers associated with these Queue Heads are + * currently assigned to a host channel. + */ + struct list_head non_periodic_sched_active; + + /** + * Pointer to the next Queue Head to process in the active + * non-periodic schedule. + */ + struct list_head *non_periodic_qh_ptr; + + /** + * Inactive items in the periodic schedule. This is a list of QHs for + * periodic transfers that are _not_ scheduled for the next frame. + * Each QH in the list has an interval counter that determines when it + * needs to be scheduled for execution. This scheduling mechanism + * allows only a simple calculation for periodic bandwidth used (i.e. + * must assume that all periodic transfers may need to execute in the + * same frame). However, it greatly simplifies scheduling and should + * be sufficient for the vast majority of OTG hosts, which need to + * connect to a small number of peripherals at one time. + * + * Items move from this list to periodic_sched_ready when the QH + * interval counter is 0 at SOF. + */ + struct list_head periodic_sched_inactive; + + /** + * List of periodic QHs that are ready for execution in the next + * frame, but have not yet been assigned to host channels. + * + * Items move from this list to periodic_sched_assigned as host + * channels become available during the current frame. + */ + struct list_head periodic_sched_ready; + + /** + * List of periodic QHs to be executed in the next frame that are + * assigned to host channels. + * + * Items move from this list to periodic_sched_queued as the + * transactions for the QH are queued to the DWC_otg controller. + */ + struct list_head periodic_sched_assigned; + + /** + * List of periodic QHs that have been queued for execution. + * + * Items move from this list to either periodic_sched_inactive or + * periodic_sched_ready when the channel associated with the transfer + * is released. If the interval for the QH is 1, the item moves to + * periodic_sched_ready because it must be rescheduled for the next + * frame. Otherwise, the item moves to periodic_sched_inactive. + */ + struct list_head periodic_sched_queued; + + /** + * Total bandwidth claimed so far for periodic transfers. This value + * is in microseconds per (micro)frame. The assumption is that all + * periodic transfers may occur in the same (micro)frame. + */ + uint16_t periodic_usecs; + + /** + * Total bandwidth claimed so far for all periodic transfers + * in a frame. + * This will include a mixture of HS and FS transfers. + * Units are microseconds per (micro)frame. + * We have a budget per frame and have to schedule + * transactions accordingly. + * Watch out for the fact that things are actually scheduled for the + * "next frame". + */ + uint16_t frame_usecs[8]; + + /** + * Frame number read from the core at SOF. The value ranges from 0 to + * DWC_HFNUM_MAX_FRNUM. + */ + uint16_t frame_number; + + /** + * Free host channels in the controller. This is a list of + * dwc_hc_t items. + */ + struct list_head free_hc_list; + + /** + * Number of available host channels. + */ + int available_host_channels; + + /** + * Array of pointers to the host channel descriptors. Allows accessing + * a host channel descriptor given the host channel number. This is + * useful in interrupt handlers. + */ + dwc_hc_t *hc_ptr_array[MAX_EPS_CHANNELS]; + + /** + * Buffer to use for any data received during the status phase of a + * control transfer. Normally no data is transferred during the status + * phase. This buffer is used as a bit bucket. + */ + uint8_t *status_buf; + + /** + * DMA address for status_buf. + */ + dma_addr_t status_buf_dma; +#define DWC_OTG_HCD_STATUS_BUF_SIZE 64 + + /** + * Structure to allow starting the HCD in a non-interrupt context + * during an OTG role change. + */ + struct work_struct start_work; + struct usb_hcd *_p; + + /** + * Connection timer. An OTG host must display a message if the device + * does not connect. Started when the VBus power is turned on via + * sysfs attribute "buspower". + */ + struct timer_list conn_timer; + + /* Tasket to do a reset */ + struct tasklet_struct *reset_tasklet; + +#ifdef DEBUG + uint32_t frrem_samples; + uint64_t frrem_accum; + + uint32_t hfnum_7_samples_a; + uint64_t hfnum_7_frrem_accum_a; + uint32_t hfnum_0_samples_a; + uint64_t hfnum_0_frrem_accum_a; + uint32_t hfnum_other_samples_a; + uint64_t hfnum_other_frrem_accum_a; + + uint32_t hfnum_7_samples_b; + uint64_t hfnum_7_frrem_accum_b; + uint32_t hfnum_0_samples_b; + uint64_t hfnum_0_frrem_accum_b; + uint32_t hfnum_other_samples_b; + uint64_t hfnum_other_frrem_accum_b; +#endif + +} dwc_otg_hcd_t; + +/** Gets the dwc_otg_hcd from a struct usb_hcd */ +static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd) +{ + return (dwc_otg_hcd_t *)(hcd->hcd_priv); +} + +/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */ +static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd) +{ + return container_of((void *)dwc_otg_hcd, struct usb_hcd, hcd_priv); +} + +/** @name HCD Create/Destroy Functions */ +/** @{ */ +extern int __devinit dwc_otg_hcd_init(struct device *_dev, dwc_otg_device_t * dwc_otg_device); +extern void dwc_otg_hcd_remove(struct device *_dev); +/** @} */ + +/** @name Linux HC Driver API Functions */ +/** @{ */ + +extern int dwc_otg_hcd_start(struct usb_hcd *hcd); +extern void dwc_otg_hcd_stop(struct usb_hcd *hcd); +extern int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd); +extern void dwc_otg_hcd_free(struct usb_hcd *hcd); + +extern int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd, + struct urb *urb, + gfp_t mem_flags); +extern int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd, + struct urb *urb, + int status); +extern irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd); + +extern void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd, + struct usb_host_endpoint *ep); + +extern int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd, + char *buf); +extern int dwc_otg_hcd_hub_control(struct usb_hcd *hcd, + u16 typeReq, + u16 wValue, + u16 wIndex, + char *buf, + u16 wLength); + +/** @} */ + +/** @name Transaction Execution Functions */ +/** @{ */ +extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *_hcd); +extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *_hcd, + dwc_otg_transaction_type_e _tr_type); +extern void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *_hcd, struct urb *_urb, + int _status); +/** @} */ + +/** @name Interrupt Handler Functions */ +/** @{ */ +extern int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *_dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *_dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *_dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *_dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *_dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr (dwc_otg_hcd_t *_dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_disconnect_intr (dwc_otg_hcd_t *_dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *_dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *_dwc_otg_hcd, uint32_t _num); +extern int32_t dwc_otg_hcd_handle_session_req_intr (dwc_otg_hcd_t *_dwc_otg_hcd); +extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr (dwc_otg_hcd_t *_dwc_otg_hcd); +/** @} */ + + +/** @name Schedule Queue Functions */ +/** @{ */ + +/* Implemented in dwc_otg_hcd_queue.c */ +extern dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *_hcd, struct urb *_urb); +extern void dwc_otg_hcd_qh_init (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, struct urb *_urb); +extern void dwc_otg_hcd_qh_free (dwc_otg_qh_t *_qh); +extern int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh); +extern void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh); +extern void dwc_otg_hcd_qh_deactivate (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int sched_csplit); +extern int dwc_otg_hcd_qh_deferr (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int delay); + +/** Remove and free a QH */ +static inline void dwc_otg_hcd_qh_remove_and_free (dwc_otg_hcd_t *_hcd, + dwc_otg_qh_t *_qh) +{ + dwc_otg_hcd_qh_remove (_hcd, _qh); + dwc_otg_hcd_qh_free (_qh); +} + +/** Allocates memory for a QH structure. + * @return Returns the memory allocate or NULL on error. */ +static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc (void) +{ +#ifdef _SC_BUILD_ + return (dwc_otg_qh_t *) kmalloc (sizeof(dwc_otg_qh_t), GFP_ATOMIC); +#else + return (dwc_otg_qh_t *) kmalloc (sizeof(dwc_otg_qh_t), GFP_KERNEL); +#endif +} + +extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *urb); +extern void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, struct urb *urb); +extern int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd); + +/** Allocates memory for a QTD structure. + * @return Returns the memory allocate or NULL on error. */ +static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc (void) +{ +#ifdef _SC_BUILD_ + return (dwc_otg_qtd_t *) kmalloc (sizeof(dwc_otg_qtd_t), GFP_ATOMIC); +#else + return (dwc_otg_qtd_t *) kmalloc (sizeof(dwc_otg_qtd_t), GFP_KERNEL); +#endif +} + +/** Frees the memory for a QTD structure. QTD should already be removed from + * list. + * @param[in] _qtd QTD to free.*/ +static inline void dwc_otg_hcd_qtd_free (dwc_otg_qtd_t *_qtd) +{ + kfree (_qtd); +} + +/** Removes a QTD from list. + * @param[in] _qtd QTD to remove from list. */ +static inline void dwc_otg_hcd_qtd_remove (dwc_otg_qtd_t *_qtd) +{ + unsigned long flags; + local_irq_save (flags); + list_del (&_qtd->qtd_list_entry); + local_irq_restore (flags); +} + +/** Remove and free a QTD */ +static inline void dwc_otg_hcd_qtd_remove_and_free (dwc_otg_qtd_t *_qtd) +{ + dwc_otg_hcd_qtd_remove (_qtd); + dwc_otg_hcd_qtd_free (_qtd); +} + +/** @} */ + + +/** @name Internal Functions */ +/** @{ */ +dwc_otg_qh_t *dwc_urb_to_qh(struct urb *_urb); +void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *_hcd); +void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *_hcd); +/** @} */ + + +/** Gets the usb_host_endpoint associated with an URB. */ +static inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *_urb) +{ + struct usb_device *dev = _urb->dev; + int ep_num = usb_pipeendpoint(_urb->pipe); + if (usb_pipein(_urb->pipe)) + return dev->ep_in[ep_num]; + else + return dev->ep_out[ep_num]; +} + +/** + * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is + * qualified with its direction (possible 32 endpoints per device). + */ +#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) \ + ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \ + ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4) + +/** Gets the QH that contains the list_head */ +#define dwc_list_to_qh(_list_head_ptr_) (container_of(_list_head_ptr_,dwc_otg_qh_t,qh_list_entry)) + +/** Gets the QTD that contains the list_head */ +#define dwc_list_to_qtd(_list_head_ptr_) (container_of(_list_head_ptr_,dwc_otg_qtd_t,qtd_list_entry)) + +/** Check if QH is non-periodic */ +#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == USB_ENDPOINT_XFER_BULK) || \ + (_qh_ptr_->ep_type == USB_ENDPOINT_XFER_CONTROL)) + +/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */ +#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03)) + +/** Packet size for any kind of endpoint descriptor */ +#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) + +/** + * Returns true if _frame1 is less than or equal to _frame2. The comparison is + * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the + * frame number when the max frame number is reached. + */ +static inline int dwc_frame_num_le(uint16_t _frame1, uint16_t _frame2) +{ + return ((_frame2 - _frame1) & DWC_HFNUM_MAX_FRNUM) <= + (DWC_HFNUM_MAX_FRNUM >> 1); +} + +/** + * Returns true if _frame1 is greater than _frame2. The comparison is done + * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame + * number when the max frame number is reached. + */ +static inline int dwc_frame_num_gt(uint16_t _frame1, uint16_t _frame2) +{ + return (_frame1 != _frame2) && + (((_frame1 - _frame2) & DWC_HFNUM_MAX_FRNUM) < + (DWC_HFNUM_MAX_FRNUM >> 1)); +} + +/** + * Increments _frame by the amount specified by _inc. The addition is done + * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value. + */ +static inline uint16_t dwc_frame_num_inc(uint16_t _frame, uint16_t _inc) +{ + return (_frame + _inc) & DWC_HFNUM_MAX_FRNUM; +} + +static inline uint16_t dwc_full_frame_num (uint16_t _frame) +{ + return ((_frame) & DWC_HFNUM_MAX_FRNUM) >> 3; +} + +static inline uint16_t dwc_micro_frame_num (uint16_t _frame) +{ + return (_frame) & 0x7; +} + +#ifdef DEBUG +/** + * Macro to sample the remaining PHY clocks left in the current frame. This + * may be used during debugging to determine the average time it takes to + * execute sections of code. There are two possible sample points, "a" and + * "b", so the _letter argument must be one of these values. + * + * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For + * example, "cat /sys/devices/lm0/hcd_frrem". + */ +#define dwc_sample_frrem(_hcd, _qh, _letter) \ +{ \ + hfnum_data_t hfnum; \ + dwc_otg_qtd_t *qtd; \ + qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \ + if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \ + hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \ + switch (hfnum.b.frnum & 0x7) { \ + case 7: \ + _hcd->hfnum_7_samples_##_letter++; \ + _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \ + break; \ + case 0: \ + _hcd->hfnum_0_samples_##_letter++; \ + _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \ + break; \ + default: \ + _hcd->hfnum_other_samples_##_letter++; \ + _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \ + break; \ + } \ + } \ +} +#else // DEBUG +#define dwc_sample_frrem(_hcd, _qh, _letter) +#endif // DEBUG +#endif // __DWC_HCD_H__ +#endif /* DWC_DEVICE_ONLY */ diff --git a/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c new file mode 100644 index 0000000000..f6f3f3dc8d --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c @@ -0,0 +1,1839 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_intr.c $ + * $Revision: 1.1.1.1 $ + * $Date: 2009-04-17 06:15:34 $ + * $Change: 553126 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ +#ifndef DWC_DEVICE_ONLY + +#include "dwc_otg_driver.h" +#include "dwc_otg_hcd.h" +#include "dwc_otg_regs.h" + +const int erratum_usb09_patched = 0; +const int deferral_on = 1; +const int nak_deferral_delay = 8; +const int nyet_deferral_delay = 1; +/** @file + * This file contains the implementation of the HCD Interrupt handlers. + */ + +/** This function handles interrupts for the HCD. */ +int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *_dwc_otg_hcd) +{ + int retval = 0; + + dwc_otg_core_if_t *core_if = _dwc_otg_hcd->core_if; + gintsts_data_t gintsts; +#ifdef DEBUG + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; +#endif + + /* Check if HOST Mode */ + if (dwc_otg_is_host_mode(core_if)) { + gintsts.d32 = dwc_otg_read_core_intr(core_if); + if (!gintsts.d32) { + return 0; + } + +#ifdef DEBUG + /* Don't print debug message in the interrupt handler on SOF */ +# ifndef DEBUG_SOF + if (gintsts.d32 != DWC_SOF_INTR_MASK) +# endif + DWC_DEBUGPL (DBG_HCD, "\n"); +#endif + +#ifdef DEBUG +# ifndef DEBUG_SOF + if (gintsts.d32 != DWC_SOF_INTR_MASK) +# endif + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n", gintsts.d32); +#endif + + if (gintsts.b.sofintr) { + retval |= dwc_otg_hcd_handle_sof_intr (_dwc_otg_hcd); + } + if (gintsts.b.rxstsqlvl) { + retval |= dwc_otg_hcd_handle_rx_status_q_level_intr (_dwc_otg_hcd); + } + if (gintsts.b.nptxfempty) { + retval |= dwc_otg_hcd_handle_np_tx_fifo_empty_intr (_dwc_otg_hcd); + } + if (gintsts.b.i2cintr) { + /** @todo Implement i2cintr handler. */ + } + if (gintsts.b.portintr) { + retval |= dwc_otg_hcd_handle_port_intr (_dwc_otg_hcd); + } + if (gintsts.b.hcintr) { + retval |= dwc_otg_hcd_handle_hc_intr (_dwc_otg_hcd); + } + if (gintsts.b.ptxfempty) { + retval |= dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (_dwc_otg_hcd); + } +#ifdef DEBUG +# ifndef DEBUG_SOF + if (gintsts.d32 != DWC_SOF_INTR_MASK) +# endif + { + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Finished Servicing Interrupts\n"); + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n", + dwc_read_reg32(&global_regs->gintsts)); + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n", + dwc_read_reg32(&global_regs->gintmsk)); + } +#endif + +#ifdef DEBUG +# ifndef DEBUG_SOF + if (gintsts.d32 != DWC_SOF_INTR_MASK) +# endif + DWC_DEBUGPL (DBG_HCD, "\n"); +#endif + + } + + return retval; +} + +#ifdef DWC_TRACK_MISSED_SOFS +#warning Compiling code to track missed SOFs +#define FRAME_NUM_ARRAY_SIZE 1000 +/** + * This function is for debug only. + */ +static inline void track_missed_sofs(uint16_t _curr_frame_number) { + static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE]; + static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE]; + static int frame_num_idx = 0; + static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM; + static int dumped_frame_num_array = 0; + + if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) { + if ((((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) != _curr_frame_number)) { + frame_num_array[frame_num_idx] = _curr_frame_number; + last_frame_num_array[frame_num_idx++] = last_frame_num; + } + } else if (!dumped_frame_num_array) { + int i; + printk(KERN_EMERG USB_DWC "Frame Last Frame\n"); + printk(KERN_EMERG USB_DWC "----- ----------\n"); + for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) { + printk(KERN_EMERG USB_DWC "0x%04x 0x%04x\n", + frame_num_array[i], last_frame_num_array[i]); + } + dumped_frame_num_array = 1; + } + last_frame_num = _curr_frame_number; +} +#endif + +/** + * Handles the start-of-frame interrupt in host mode. Non-periodic + * transactions may be queued to the DWC_otg controller for the current + * (micro)frame. Periodic transactions may be queued to the controller for the + * next (micro)frame. + */ +int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *_hcd) +{ + hfnum_data_t hfnum; + struct list_head *qh_entry; + dwc_otg_qh_t *qh; + dwc_otg_transaction_type_e tr_type; + gintsts_data_t gintsts = {.d32 = 0}; + + hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); + +#ifdef DEBUG_SOF + DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n"); +#endif + + _hcd->frame_number = hfnum.b.frnum; + +#ifdef DEBUG + _hcd->frrem_accum += hfnum.b.frrem; + _hcd->frrem_samples++; +#endif + +#ifdef DWC_TRACK_MISSED_SOFS + track_missed_sofs(_hcd->frame_number); +#endif + + /* Determine whether any periodic QHs should be executed. */ + qh_entry = _hcd->periodic_sched_inactive.next; + while (qh_entry != &_hcd->periodic_sched_inactive) { + qh = list_entry(qh_entry, dwc_otg_qh_t, qh_list_entry); + qh_entry = qh_entry->next; + if (dwc_frame_num_le(qh->sched_frame, _hcd->frame_number)) { + /* + * Move QH to the ready list to be executed next + * (micro)frame. + */ + list_move(&qh->qh_list_entry, &_hcd->periodic_sched_ready); + } + } + + tr_type = dwc_otg_hcd_select_transactions(_hcd); + if (tr_type != DWC_OTG_TRANSACTION_NONE) { + dwc_otg_hcd_queue_transactions(_hcd, tr_type); + } + + /* Clear interrupt */ + gintsts.b.sofintr = 1; + dwc_write_reg32(&_hcd->core_if->core_global_regs->gintsts, gintsts.d32); + + return 1; +} + +/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at + * least one packet in the Rx FIFO. The packets are moved from the FIFO to + * memory if the DWC_otg controller is operating in Slave mode. */ +int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *_dwc_otg_hcd) +{ + host_grxsts_data_t grxsts; + dwc_hc_t *hc = NULL; + + DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n"); + + grxsts.d32 = dwc_read_reg32(&_dwc_otg_hcd->core_if->core_global_regs->grxstsp); + + hc = _dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum]; + + /* Packet Status */ + DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum); + DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt); + DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid, hc->data_pid_start); + DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts); + + switch (grxsts.b.pktsts) { + case DWC_GRXSTS_PKTSTS_IN: + /* Read the data into the host buffer. */ + if (grxsts.b.bcnt > 0) { + dwc_otg_read_packet(_dwc_otg_hcd->core_if, + hc->xfer_buff, + grxsts.b.bcnt); + + /* Update the HC fields for the next packet received. */ + hc->xfer_count += grxsts.b.bcnt; + hc->xfer_buff += grxsts.b.bcnt; + } + + case DWC_GRXSTS_PKTSTS_IN_XFER_COMP: + case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR: + case DWC_GRXSTS_PKTSTS_CH_HALTED: + /* Handled in interrupt, just ignore data */ + break; + default: + DWC_ERROR ("RX_STS_Q Interrupt: Unknown status %d\n", grxsts.b.pktsts); + break; + } + + return 1; +} + +/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More + * data packets may be written to the FIFO for OUT transfers. More requests + * may be written to the non-periodic request queue for IN transfers. This + * interrupt is enabled only in Slave mode. */ +int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd) +{ + DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n"); + dwc_otg_hcd_queue_transactions(_dwc_otg_hcd, + DWC_OTG_TRANSACTION_NON_PERIODIC); + return 1; +} + +/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data + * packets may be written to the FIFO for OUT transfers. More requests may be + * written to the periodic request queue for IN transfers. This interrupt is + * enabled only in Slave mode. */ +int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd) +{ + DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n"); + dwc_otg_hcd_queue_transactions(_dwc_otg_hcd, + DWC_OTG_TRANSACTION_PERIODIC); + return 1; +} + +/** There are multiple conditions that can cause a port interrupt. This function + * determines which interrupt conditions have occurred and handles them + * appropriately. */ +int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *_dwc_otg_hcd) +{ + int retval = 0; + hprt0_data_t hprt0; + hprt0_data_t hprt0_modify; + + hprt0.d32 = dwc_read_reg32(_dwc_otg_hcd->core_if->host_if->hprt0); + hprt0_modify.d32 = dwc_read_reg32(_dwc_otg_hcd->core_if->host_if->hprt0); + + /* Clear appropriate bits in HPRT0 to clear the interrupt bit in + * GINTSTS */ + + hprt0_modify.b.prtena = 0; + hprt0_modify.b.prtconndet = 0; + hprt0_modify.b.prtenchng = 0; + hprt0_modify.b.prtovrcurrchng = 0; + + /* Port Connect Detected + * Set flag and clear if detected */ + if (hprt0.b.prtconndet) { + DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x " + "Port Connect Detected--\n", hprt0.d32); + _dwc_otg_hcd->flags.b.port_connect_status_change = 1; + _dwc_otg_hcd->flags.b.port_connect_status = 1; + hprt0_modify.b.prtconndet = 1; + + /* B-Device has connected, Delete the connection timer. */ + del_timer( &_dwc_otg_hcd->conn_timer ); + + /* The Hub driver asserts a reset when it sees port connect + * status change flag */ + retval |= 1; + } + + /* Port Enable Changed + * Clear if detected - Set internal flag if disabled */ + if (hprt0.b.prtenchng) { + DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " + "Port Enable Changed--\n", hprt0.d32); + hprt0_modify.b.prtenchng = 1; + if (hprt0.b.prtena == 1) { + int do_reset = 0; + dwc_otg_core_params_t *params = _dwc_otg_hcd->core_if->core_params; + dwc_otg_core_global_regs_t *global_regs = _dwc_otg_hcd->core_if->core_global_regs; + dwc_otg_host_if_t *host_if = _dwc_otg_hcd->core_if->host_if; + + /* Check if we need to adjust the PHY clock speed for + * low power and adjust it */ + if (params->host_support_fs_ls_low_power) + { + gusbcfg_data_t usbcfg; + + usbcfg.d32 = dwc_read_reg32 (&global_regs->gusbcfg); + + if ((hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED) || + (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED)) + { + /* + * Low power + */ + hcfg_data_t hcfg; + if (usbcfg.b.phylpwrclksel == 0) { + /* Set PHY low power clock select for FS/LS devices */ + usbcfg.b.phylpwrclksel = 1; + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); + do_reset = 1; + } + + hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg); + + if ((hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED) && + (params->host_ls_low_power_phy_clk == + DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) + { + /* 6 MHZ */ + DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 6 MHz (Low Power)\n"); + if (hcfg.b.fslspclksel != DWC_HCFG_6_MHZ) { + hcfg.b.fslspclksel = DWC_HCFG_6_MHZ; + dwc_write_reg32(&host_if->host_global_regs->hcfg, + hcfg.d32); + do_reset = 1; + } + } + else { + /* 48 MHZ */ + DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 48 MHz ()\n"); + if (hcfg.b.fslspclksel != DWC_HCFG_48_MHZ) { + hcfg.b.fslspclksel = DWC_HCFG_48_MHZ; + dwc_write_reg32(&host_if->host_global_regs->hcfg, + hcfg.d32); + do_reset = 1; + } + } + } + else { + /* + * Not low power + */ + if (usbcfg.b.phylpwrclksel == 1) { + usbcfg.b.phylpwrclksel = 0; + dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); + do_reset = 1; + } + } + + if (do_reset) { + tasklet_schedule(_dwc_otg_hcd->reset_tasklet); + } + } + + if (!do_reset) { + /* Port has been enabled set the reset change flag */ + _dwc_otg_hcd->flags.b.port_reset_change = 1; + } + + } else { + _dwc_otg_hcd->flags.b.port_enable_change = 1; + } + retval |= 1; + } + + /** Overcurrent Change Interrupt */ + if (hprt0.b.prtovrcurrchng) { + DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " + "Port Overcurrent Changed--\n", hprt0.d32); + _dwc_otg_hcd->flags.b.port_over_current_change = 1; + hprt0_modify.b.prtovrcurrchng = 1; + retval |= 1; + } + + /* Clear Port Interrupts */ + dwc_write_reg32(_dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32); + + return retval; +} + + +/** This interrupt indicates that one or more host channels has a pending + * interrupt. There are multiple conditions that can cause each host channel + * interrupt. This function determines which conditions have occurred for each + * host channel interrupt and handles them appropriately. */ +int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *_dwc_otg_hcd) +{ + int i; + int retval = 0; + haint_data_t haint; + + /* Clear appropriate bits in HCINTn to clear the interrupt bit in + * GINTSTS */ + + haint.d32 = dwc_otg_read_host_all_channels_intr(_dwc_otg_hcd->core_if); + + for (i=0; i<_dwc_otg_hcd->core_if->core_params->host_channels; i++) { + if (haint.b2.chint & (1 << i)) { + retval |= dwc_otg_hcd_handle_hc_n_intr (_dwc_otg_hcd, i); + } + } + + return retval; +} + +/* Macro used to clear one channel interrupt */ +#define clear_hc_int(_hc_regs_,_intr_) \ +do { \ + hcint_data_t hcint_clear = {.d32 = 0}; \ + hcint_clear.b._intr_ = 1; \ + dwc_write_reg32(&((_hc_regs_)->hcint), hcint_clear.d32); \ +} while (0) + +/* + * Macro used to disable one channel interrupt. Channel interrupts are + * disabled when the channel is halted or released by the interrupt handler. + * There is no need to handle further interrupts of that type until the + * channel is re-assigned. In fact, subsequent handling may cause crashes + * because the channel structures are cleaned up when the channel is released. + */ +#define disable_hc_int(_hc_regs_,_intr_) \ +do { \ + hcintmsk_data_t hcintmsk = {.d32 = 0}; \ + hcintmsk.b._intr_ = 1; \ + dwc_modify_reg32(&((_hc_regs_)->hcintmsk), hcintmsk.d32, 0); \ +} while (0) + +/** + * Gets the actual length of a transfer after the transfer halts. _halt_status + * holds the reason for the halt. + * + * For IN transfers where _halt_status is DWC_OTG_HC_XFER_COMPLETE, + * *_short_read is set to 1 upon return if less than the requested + * number of bytes were transferred. Otherwise, *_short_read is set to 0 upon + * return. _short_read may also be NULL on entry, in which case it remains + * unchanged. + */ +static uint32_t get_actual_xfer_length(dwc_hc_t *_hc, + dwc_otg_hc_regs_t *_hc_regs, + dwc_otg_qtd_t *_qtd, + dwc_otg_halt_status_e _halt_status, + int *_short_read) +{ + hctsiz_data_t hctsiz; + uint32_t length; + + if (_short_read != NULL) { + *_short_read = 0; + } + hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz); + + if (_halt_status == DWC_OTG_HC_XFER_COMPLETE) { + if (_hc->ep_is_in) { + length = _hc->xfer_len - hctsiz.b.xfersize; + if (_short_read != NULL) { + *_short_read = (hctsiz.b.xfersize != 0); + } + } else if (_hc->qh->do_split) { + length = _qtd->ssplit_out_xfer_count; + } else { + length = _hc->xfer_len; + } + } else { + /* + * Must use the hctsiz.pktcnt field to determine how much data + * has been transferred. This field reflects the number of + * packets that have been transferred via the USB. This is + * always an integral number of packets if the transfer was + * halted before its normal completion. (Can't use the + * hctsiz.xfersize field because that reflects the number of + * bytes transferred via the AHB, not the USB). + */ + length = (_hc->start_pkt_count - hctsiz.b.pktcnt) * _hc->max_packet; + } + + return length; +} + +/** + * Updates the state of the URB after a Transfer Complete interrupt on the + * host channel. Updates the actual_length field of the URB based on the + * number of bytes transferred via the host channel. Sets the URB status + * if the data transfer is finished. + * + * @return 1 if the data transfer specified by the URB is completely finished, + * 0 otherwise. + */ +static int update_urb_state_xfer_comp(dwc_hc_t *_hc, + dwc_otg_hc_regs_t * _hc_regs, struct urb *_urb, + dwc_otg_qtd_t * _qtd, int *status) +{ + int xfer_done = 0; + int short_read = 0; + + _urb->actual_length += get_actual_xfer_length(_hc, _hc_regs, _qtd, + DWC_OTG_HC_XFER_COMPLETE, + &short_read); + + if (short_read || (_urb->actual_length == _urb->transfer_buffer_length)) { + xfer_done = 1; + if (short_read && (_urb->transfer_flags & URB_SHORT_NOT_OK)) { + *status = -EREMOTEIO; + } else { + *status = 0; + } + } + +#ifdef DEBUG + { + hctsiz_data_t hctsiz; + hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz); + DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n", + __func__, (_hc->ep_is_in ? "IN" : "OUT"), _hc->hc_num); + DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", _hc->xfer_len); + DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n", hctsiz.b.xfersize); + DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n", + _urb->transfer_buffer_length); + DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", _urb->actual_length); + DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n", + short_read, xfer_done); + } +#endif + + return xfer_done; +} + +/* + * Save the starting data toggle for the next transfer. The data toggle is + * saved in the QH for non-control transfers and it's saved in the QTD for + * control transfers. + */ +static void save_data_toggle(dwc_hc_t *_hc, + dwc_otg_hc_regs_t *_hc_regs, + dwc_otg_qtd_t *_qtd) +{ + hctsiz_data_t hctsiz; + hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz); + + if (_hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) { + dwc_otg_qh_t *qh = _hc->qh; + if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) { + qh->data_toggle = DWC_OTG_HC_PID_DATA0; + } else { + qh->data_toggle = DWC_OTG_HC_PID_DATA1; + } + } else { + if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) { + _qtd->data_toggle = DWC_OTG_HC_PID_DATA0; + } else { + _qtd->data_toggle = DWC_OTG_HC_PID_DATA1; + } + } +} + +/** + * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic + * QHs, removes the QH from the active non-periodic schedule. If any QTDs are + * still linked to the QH, the QH is added to the end of the inactive + * non-periodic schedule. For periodic QHs, removes the QH from the periodic + * schedule if no more QTDs are linked to the QH. + */ +static void deactivate_qh(dwc_otg_hcd_t *_hcd, + dwc_otg_qh_t *_qh, + int free_qtd) +{ + int continue_split = 0; + dwc_otg_qtd_t *qtd; + + DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, _hcd, _qh, free_qtd); + + qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); + + if (qtd->complete_split) { + continue_split = 1; + } + else if ((qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID) || + (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END)) + { + continue_split = 1; + } + + if (free_qtd) { + /* + * Note that this was previously a call to + * dwc_otg_hcd_qtd_remove_and_free(qtd), which frees the qtd. + * However, that call frees the qtd memory, and we continue in the + * interrupt logic to access it many more times, including writing + * to it. With slub debugging on, it is clear that we were writing + * to memory we had freed. + * Call this instead, and now I have moved the freeing of the memory to + * the end of processing this interrupt. + */ + //dwc_otg_hcd_qtd_remove_and_free(qtd); + dwc_otg_hcd_qtd_remove(qtd); + + continue_split = 0; + } + + _qh->channel = NULL; + _qh->qtd_in_process = NULL; + dwc_otg_hcd_qh_deactivate(_hcd, _qh, continue_split); +} + +/** + * Updates the state of an Isochronous URB when the transfer is stopped for + * any reason. The fields of the current entry in the frame descriptor array + * are set based on the transfer state and the input _halt_status. Completes + * the Isochronous URB if all the URB frames have been completed. + * + * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be + * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE. + */ +static dwc_otg_halt_status_e +update_isoc_urb_state(dwc_otg_hcd_t *_hcd, + dwc_hc_t *_hc, + dwc_otg_hc_regs_t *_hc_regs, + dwc_otg_qtd_t *_qtd, + dwc_otg_halt_status_e _halt_status) +{ + struct urb *urb = _qtd->urb; + dwc_otg_halt_status_e ret_val = _halt_status; + struct usb_iso_packet_descriptor *frame_desc; + + frame_desc = &urb->iso_frame_desc[_qtd->isoc_frame_index]; + switch (_halt_status) { + case DWC_OTG_HC_XFER_COMPLETE: + frame_desc->status = 0; + frame_desc->actual_length = + get_actual_xfer_length(_hc, _hc_regs, _qtd, + _halt_status, NULL); + break; + case DWC_OTG_HC_XFER_FRAME_OVERRUN: + urb->error_count++; + if (_hc->ep_is_in) { + frame_desc->status = -ENOSR; + } else { + frame_desc->status = -ECOMM; + } + frame_desc->actual_length = 0; + break; + case DWC_OTG_HC_XFER_BABBLE_ERR: + urb->error_count++; + frame_desc->status = -EOVERFLOW; + /* Don't need to update actual_length in this case. */ + break; + case DWC_OTG_HC_XFER_XACT_ERR: + urb->error_count++; + frame_desc->status = -EPROTO; + frame_desc->actual_length = + get_actual_xfer_length(_hc, _hc_regs, _qtd, + _halt_status, NULL); + default: + DWC_ERROR("%s: Unhandled _halt_status (%d)\n", __func__, + _halt_status); + BUG(); + break; + } + + if (++_qtd->isoc_frame_index == urb->number_of_packets) { + /* + * urb->status is not used for isoc transfers. + * The individual frame_desc statuses are used instead. + */ + dwc_otg_hcd_complete_urb(_hcd, urb, 0); + ret_val = DWC_OTG_HC_XFER_URB_COMPLETE; + } else { + ret_val = DWC_OTG_HC_XFER_COMPLETE; + } + + return ret_val; +} + +/** + * Releases a host channel for use by other transfers. Attempts to select and + * queue more transactions since at least one host channel is available. + * + * @param _hcd The HCD state structure. + * @param _hc The host channel to release. + * @param _qtd The QTD associated with the host channel. This QTD may be freed + * if the transfer is complete or an error has occurred. + * @param _halt_status Reason the channel is being released. This status + * determines the actions taken by this function. + */ +static void release_channel(dwc_otg_hcd_t *_hcd, + dwc_hc_t *_hc, + dwc_otg_qtd_t *_qtd, + dwc_otg_halt_status_e _halt_status, + int *must_free) +{ + dwc_otg_transaction_type_e tr_type; + int free_qtd; + dwc_otg_qh_t * _qh; + int deact = 1; + int retry_delay = 1; + unsigned long flags; + + DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d\n", __func__, + _hc->hc_num, _halt_status); + + switch (_halt_status) { + case DWC_OTG_HC_XFER_NYET: + case DWC_OTG_HC_XFER_NAK: + if (_halt_status == DWC_OTG_HC_XFER_NYET) { + retry_delay = nyet_deferral_delay; + } else { + retry_delay = nak_deferral_delay; + } + free_qtd = 0; + if (deferral_on && _hc->do_split) { + _qh = _hc->qh; + if (_qh) { + deact = dwc_otg_hcd_qh_deferr(_hcd, _qh , retry_delay); + } + } + break; + case DWC_OTG_HC_XFER_URB_COMPLETE: + free_qtd = 1; + break; + case DWC_OTG_HC_XFER_AHB_ERR: + case DWC_OTG_HC_XFER_STALL: + case DWC_OTG_HC_XFER_BABBLE_ERR: + free_qtd = 1; + break; + case DWC_OTG_HC_XFER_XACT_ERR: + if (_qtd->error_count >= 3) { + DWC_DEBUGPL(DBG_HCDV, " Complete URB with transaction error\n"); + free_qtd = 1; + //_qtd->urb->status = -EPROTO; + dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EPROTO); + } else { + free_qtd = 0; + } + break; + case DWC_OTG_HC_XFER_URB_DEQUEUE: + /* + * The QTD has already been removed and the QH has been + * deactivated. Don't want to do anything except release the + * host channel and try to queue more transfers. + */ + goto cleanup; + case DWC_OTG_HC_XFER_NO_HALT_STATUS: + DWC_ERROR("%s: No halt_status, channel %d\n", __func__, _hc->hc_num); + free_qtd = 0; + break; + default: + free_qtd = 0; + break; + } + if (free_qtd) { + /* Only change must_free to true (do not set to zero here -- it is + * pre-initialized to zero). + */ + *must_free = 1; + } + if (deact) { + deactivate_qh(_hcd, _hc->qh, free_qtd); + } + cleanup: + /* + * Release the host channel for use by other transfers. The cleanup + * function clears the channel interrupt enables and conditions, so + * there's no need to clear the Channel Halted interrupt separately. + */ + dwc_otg_hc_cleanup(_hcd->core_if, _hc); + list_add_tail(&_hc->hc_list_entry, &_hcd->free_hc_list); + + local_irq_save(flags); + _hcd->available_host_channels++; + local_irq_restore(flags); + /* Try to queue more transfers now that there's a free channel, */ + /* unless erratum_usb09_patched is set */ + if (!erratum_usb09_patched) { + tr_type = dwc_otg_hcd_select_transactions(_hcd); + if (tr_type != DWC_OTG_TRANSACTION_NONE) { + dwc_otg_hcd_queue_transactions(_hcd, tr_type); + } + } +} + +/** + * Halts a host channel. If the channel cannot be halted immediately because + * the request queue is full, this function ensures that the FIFO empty + * interrupt for the appropriate queue is enabled so that the halt request can + * be queued when there is space in the request queue. + * + * This function may also be called in DMA mode. In that case, the channel is + * simply released since the core always halts the channel automatically in + * DMA mode. + */ +static void halt_channel(dwc_otg_hcd_t *_hcd, + dwc_hc_t *_hc, + dwc_otg_qtd_t *_qtd, + dwc_otg_halt_status_e _halt_status, int *must_free) +{ + if (_hcd->core_if->dma_enable) { + release_channel(_hcd, _hc, _qtd, _halt_status, must_free); + return; + } + + /* Slave mode processing... */ + dwc_otg_hc_halt(_hcd->core_if, _hc, _halt_status); + + if (_hc->halt_on_queue) { + gintmsk_data_t gintmsk = {.d32 = 0}; + dwc_otg_core_global_regs_t *global_regs; + global_regs = _hcd->core_if->core_global_regs; + + if (_hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || + _hc->ep_type == DWC_OTG_EP_TYPE_BULK) { + /* + * Make sure the Non-periodic Tx FIFO empty interrupt + * is enabled so that the non-periodic schedule will + * be processed. + */ + gintmsk.b.nptxfempty = 1; + dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32); + } else { + /* + * Move the QH from the periodic queued schedule to + * the periodic assigned schedule. This allows the + * halt to be queued when the periodic schedule is + * processed. + */ + list_move(&_hc->qh->qh_list_entry, + &_hcd->periodic_sched_assigned); + + /* + * Make sure the Periodic Tx FIFO Empty interrupt is + * enabled so that the periodic schedule will be + * processed. + */ + gintmsk.b.ptxfempty = 1; + dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32); + } + } +} + +/** + * Performs common cleanup for non-periodic transfers after a Transfer + * Complete interrupt. This function should be called after any endpoint type + * specific handling is finished to release the host channel. + */ +static void complete_non_periodic_xfer(dwc_otg_hcd_t *_hcd, + dwc_hc_t *_hc, + dwc_otg_hc_regs_t *_hc_regs, + dwc_otg_qtd_t *_qtd, + dwc_otg_halt_status_e _halt_status, int *must_free) +{ + hcint_data_t hcint; + + _qtd->error_count = 0; + + hcint.d32 = dwc_read_reg32(&_hc_regs->hcint); + if (hcint.b.nyet) { + /* + * Got a NYET on the last transaction of the transfer. This + * means that the endpoint should be in the PING state at the + * beginning of the next transfer. + */ + _hc->qh->ping_state = 1; + clear_hc_int(_hc_regs,nyet); + } + + /* + * Always halt and release the host channel to make it available for + * more transfers. There may still be more phases for a control + * transfer or more data packets for a bulk transfer at this point, + * but the host channel is still halted. A channel will be reassigned + * to the transfer when the non-periodic schedule is processed after + * the channel is released. This allows transactions to be queued + * properly via dwc_otg_hcd_queue_transactions, which also enables the + * Tx FIFO Empty interrupt if necessary. + */ + if (_hc->ep_is_in) { + /* + * IN transfers in Slave mode require an explicit disable to + * halt the channel. (In DMA mode, this call simply releases + * the channel.) + */ + halt_channel(_hcd, _hc, _qtd, _halt_status, must_free); + } else { + /* + * The channel is automatically disabled by the core for OUT + * transfers in Slave mode. + */ + release_channel(_hcd, _hc, _qtd, _halt_status, must_free); + } +} + +/** + * Performs common cleanup for periodic transfers after a Transfer Complete + * interrupt. This function should be called after any endpoint type specific + * handling is finished to release the host channel. + */ +static void complete_periodic_xfer(dwc_otg_hcd_t *_hcd, + dwc_hc_t *_hc, + dwc_otg_hc_regs_t *_hc_regs, + dwc_otg_qtd_t *_qtd, + dwc_otg_halt_status_e _halt_status, int *must_free) +{ + hctsiz_data_t hctsiz; + _qtd->error_count = 0; + + hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz); + if (!_hc->ep_is_in || hctsiz.b.pktcnt == 0) { + /* Core halts channel in these cases. */ + release_channel(_hcd, _hc, _qtd, _halt_status, must_free); + } else { + /* Flush any outstanding requests from the Tx queue. */ + halt_channel(_hcd, _hc, _qtd, _halt_status, must_free); + } +} + +/** + * Handles a host channel Transfer Complete interrupt. This handler may be + * called in either DMA mode or Slave mode. + */ +static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t *_hcd, + dwc_hc_t *_hc, + dwc_otg_hc_regs_t *_hc_regs, + dwc_otg_qtd_t *_qtd, int *must_free) +{ + int urb_xfer_done; + dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE; + struct urb *urb = _qtd->urb; + int pipe_type = usb_pipetype(urb->pipe); + int status = -EINPROGRESS; + + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "Transfer Complete--\n", _hc->hc_num); + + /* + * Handle xfer complete on CSPLIT. + */ + if (_hc->qh->do_split) { + _qtd->complete_split = 0; + } + + /* Update the QTD and URB states. */ + switch (pipe_type) { + case PIPE_CONTROL: + switch (_qtd->control_phase) { + case DWC_OTG_CONTROL_SETUP: + if (urb->transfer_buffer_length > 0) { + _qtd->control_phase = DWC_OTG_CONTROL_DATA; + } else { + _qtd->control_phase = DWC_OTG_CONTROL_STATUS; + } + DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n"); + halt_status = DWC_OTG_HC_XFER_COMPLETE; + break; + case DWC_OTG_CONTROL_DATA: { + urb_xfer_done = update_urb_state_xfer_comp(_hc, _hc_regs,urb, _qtd, &status); + if (urb_xfer_done) { + _qtd->control_phase = DWC_OTG_CONTROL_STATUS; + DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n"); + } else { + save_data_toggle(_hc, _hc_regs, _qtd); + } + halt_status = DWC_OTG_HC_XFER_COMPLETE; + break; + } + case DWC_OTG_CONTROL_STATUS: + DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n"); + if (status == -EINPROGRESS) { + status = 0; + } + dwc_otg_hcd_complete_urb(_hcd, urb, status); + halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; + break; + } + + complete_non_periodic_xfer(_hcd, _hc, _hc_regs, _qtd, + halt_status, must_free); + break; + case PIPE_BULK: + DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n"); + urb_xfer_done = update_urb_state_xfer_comp(_hc, _hc_regs, urb, _qtd, &status); + if (urb_xfer_done) { + dwc_otg_hcd_complete_urb(_hcd, urb, status); + halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; + } else { + halt_status = DWC_OTG_HC_XFER_COMPLETE; + } + + save_data_toggle(_hc, _hc_regs, _qtd); + complete_non_periodic_xfer(_hcd, _hc, _hc_regs, _qtd,halt_status, must_free); + break; + case PIPE_INTERRUPT: + DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n"); + update_urb_state_xfer_comp(_hc, _hc_regs, urb, _qtd, &status); + + /* + * Interrupt URB is done on the first transfer complete + * interrupt. + */ + dwc_otg_hcd_complete_urb(_hcd, urb, status); + save_data_toggle(_hc, _hc_regs, _qtd); + complete_periodic_xfer(_hcd, _hc, _hc_regs, _qtd, + DWC_OTG_HC_XFER_URB_COMPLETE, must_free); + break; + case PIPE_ISOCHRONOUS: + DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n"); + if (_qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) + { + halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd, + DWC_OTG_HC_XFER_COMPLETE); + } + complete_periodic_xfer(_hcd, _hc, _hc_regs, _qtd, halt_status, must_free); + break; + } + + disable_hc_int(_hc_regs,xfercompl); + + return 1; +} + +/** + * Handles a host channel STALL interrupt. This handler may be called in + * either DMA mode or Slave mode. + */ +static int32_t handle_hc_stall_intr(dwc_otg_hcd_t *_hcd, + dwc_hc_t *_hc, + dwc_otg_hc_regs_t *_hc_regs, + dwc_otg_qtd_t *_qtd, int *must_free) +{ + struct urb *urb = _qtd->urb; + int pipe_type = usb_pipetype(urb->pipe); + + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "STALL Received--\n", _hc->hc_num); + + if (pipe_type == PIPE_CONTROL) { + dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EPIPE); + } + + if (pipe_type == PIPE_BULK || pipe_type == PIPE_INTERRUPT) { + dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EPIPE); + /* + * USB protocol requires resetting the data toggle for bulk + * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT) + * setup command is issued to the endpoint. Anticipate the + * CLEAR_FEATURE command since a STALL has occurred and reset + * the data toggle now. + */ + _hc->qh->data_toggle = 0; + } + + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_STALL, must_free); + disable_hc_int(_hc_regs,stall); + + return 1; +} + +/* + * Updates the state of the URB when a transfer has been stopped due to an + * abnormal condition before the transfer completes. Modifies the + * actual_length field of the URB to reflect the number of bytes that have + * actually been transferred via the host channel. + */ +static void update_urb_state_xfer_intr(dwc_hc_t *_hc, + dwc_otg_hc_regs_t *_hc_regs, + struct urb *_urb, + dwc_otg_qtd_t *_qtd, + dwc_otg_halt_status_e _halt_status) +{ + uint32_t bytes_transferred = get_actual_xfer_length(_hc, _hc_regs, _qtd, + _halt_status, NULL); + _urb->actual_length += bytes_transferred; + +#ifdef DEBUG + { + hctsiz_data_t hctsiz; + hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz); + DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n", + __func__, (_hc->ep_is_in ? "IN" : "OUT"), _hc->hc_num); + DWC_DEBUGPL(DBG_HCDV, " _hc->start_pkt_count %d\n", _hc->start_pkt_count); + DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt); + DWC_DEBUGPL(DBG_HCDV, " _hc->max_packet %d\n", _hc->max_packet); + DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n", bytes_transferred); + DWC_DEBUGPL(DBG_HCDV, " _urb->actual_length %d\n", _urb->actual_length); + DWC_DEBUGPL(DBG_HCDV, " _urb->transfer_buffer_length %d\n", + _urb->transfer_buffer_length); + } +#endif +} + +/** + * Handles a host channel NAK interrupt. This handler may be called in either + * DMA mode or Slave mode. + */ +static int32_t handle_hc_nak_intr(dwc_otg_hcd_t *_hcd, + dwc_hc_t *_hc, + dwc_otg_hc_regs_t *_hc_regs, + dwc_otg_qtd_t *_qtd, int *must_free) +{ + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "NAK Received--\n", _hc->hc_num); + + /* + * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and + * interrupt. Re-start the SSPLIT transfer. + */ + if (_hc->do_split) { + if (_hc->complete_split) { + _qtd->error_count = 0; + } + _qtd->complete_split = 0; + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NAK, must_free); + goto handle_nak_done; + } + + switch (usb_pipetype(_qtd->urb->pipe)) { + case PIPE_CONTROL: + case PIPE_BULK: + if (_hcd->core_if->dma_enable && _hc->ep_is_in) { + /* + * NAK interrupts are enabled on bulk/control IN + * transfers in DMA mode for the sole purpose of + * resetting the error count after a transaction error + * occurs. The core will continue transferring data. + */ + _qtd->error_count = 0; + goto handle_nak_done; + } + + /* + * NAK interrupts normally occur during OUT transfers in DMA + * or Slave mode. For IN transfers, more requests will be + * queued as request queue space is available. + */ + _qtd->error_count = 0; + + if (!_hc->qh->ping_state) { + update_urb_state_xfer_intr(_hc, _hc_regs, _qtd->urb, + _qtd, DWC_OTG_HC_XFER_NAK); + save_data_toggle(_hc, _hc_regs, _qtd); + if (_qtd->urb->dev->speed == USB_SPEED_HIGH) { + _hc->qh->ping_state = 1; + } + } + + /* + * Halt the channel so the transfer can be re-started from + * the appropriate point or the PING protocol will + * start/continue. + */ + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NAK, must_free); + break; + case PIPE_INTERRUPT: + _qtd->error_count = 0; + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NAK, must_free); + break; + case PIPE_ISOCHRONOUS: + /* Should never get called for isochronous transfers. */ + BUG(); + break; + } + + handle_nak_done: + disable_hc_int(_hc_regs,nak); + + return 1; +} + +/** + * Handles a host channel ACK interrupt. This interrupt is enabled when + * performing the PING protocol in Slave mode, when errors occur during + * either Slave mode or DMA mode, and during Start Split transactions. + */ +static int32_t handle_hc_ack_intr(dwc_otg_hcd_t *_hcd, + dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) +{ + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "ACK Received--\n", _hc->hc_num); + + if (_hc->do_split) { + /* + * Handle ACK on SSPLIT. + * ACK should not occur in CSPLIT. + */ + if ((!_hc->ep_is_in) && (_hc->data_pid_start != DWC_OTG_HC_PID_SETUP)) { + _qtd->ssplit_out_xfer_count = _hc->xfer_len; + } + if (!(_hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !_hc->ep_is_in)) { + /* Don't need complete for isochronous out transfers. */ + _qtd->complete_split = 1; + } + + /* ISOC OUT */ + if ((_hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && !_hc->ep_is_in) { + switch (_hc->xact_pos) { + case DWC_HCSPLIT_XACTPOS_ALL: + break; + case DWC_HCSPLIT_XACTPOS_END: + _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL; + _qtd->isoc_split_offset = 0; + break; + case DWC_HCSPLIT_XACTPOS_BEGIN: + case DWC_HCSPLIT_XACTPOS_MID: + /* + * For BEGIN or MID, calculate the length for + * the next microframe to determine the correct + * SSPLIT token, either MID or END. + */ + do { + struct usb_iso_packet_descriptor *frame_desc; + + frame_desc = &_qtd->urb->iso_frame_desc[_qtd->isoc_frame_index]; + _qtd->isoc_split_offset += 188; + + if ((frame_desc->length - _qtd->isoc_split_offset) <= 188) { + _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_END; + } + else { + _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_MID; + } + + } while(0); + break; + } + } else { + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_ACK, must_free); + } + } else { + _qtd->error_count = 0; + + if (_hc->qh->ping_state) { + _hc->qh->ping_state = 0; + /* + * Halt the channel so the transfer can be re-started + * from the appropriate point. This only happens in + * Slave mode. In DMA mode, the ping_state is cleared + * when the transfer is started because the core + * automatically executes the PING, then the transfer. + */ + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_ACK, must_free); + } + } + + /* + * If the ACK occurred when _not_ in the PING state, let the channel + * continue transferring data after clearing the error count. + */ + + disable_hc_int(_hc_regs,ack); + + return 1; +} + +/** + * Handles a host channel NYET interrupt. This interrupt should only occur on + * Bulk and Control OUT endpoints and for complete split transactions. If a + * NYET occurs at the same time as a Transfer Complete interrupt, it is + * handled in the xfercomp interrupt handler, not here. This handler may be + * called in either DMA mode or Slave mode. + */ +static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t *_hcd, + dwc_hc_t *_hc, + dwc_otg_hc_regs_t *_hc_regs, + dwc_otg_qtd_t *_qtd, int *must_free) +{ + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "NYET Received--\n", _hc->hc_num); + + /* + * NYET on CSPLIT + * re-do the CSPLIT immediately on non-periodic + */ + if ((_hc->do_split) && (_hc->complete_split)) { + if ((_hc->ep_type == DWC_OTG_EP_TYPE_INTR) || + (_hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) { + int frnum = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd)); + + if (dwc_full_frame_num(frnum) != + dwc_full_frame_num(_hc->qh->sched_frame)) { + /* + * No longer in the same full speed frame. + * Treat this as a transaction error. + */ +#if 0 + /** @todo Fix system performance so this can + * be treated as an error. Right now complete + * splits cannot be scheduled precisely enough + * due to other system activity, so this error + * occurs regularly in Slave mode. + */ + _qtd->error_count++; +#endif + _qtd->complete_split = 0; + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_XACT_ERR, must_free); + /** @todo add support for isoc release */ + goto handle_nyet_done; + } + } + + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NYET, must_free); + goto handle_nyet_done; + } + + _hc->qh->ping_state = 1; + _qtd->error_count = 0; + + update_urb_state_xfer_intr(_hc, _hc_regs, _qtd->urb, _qtd, + DWC_OTG_HC_XFER_NYET); + save_data_toggle(_hc, _hc_regs, _qtd); + + /* + * Halt the channel and re-start the transfer so the PING + * protocol will start. + */ + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NYET, must_free); + +handle_nyet_done: + disable_hc_int(_hc_regs,nyet); + clear_hc_int(_hc_regs, nyet); + return 1; +} + +/** + * Handles a host channel babble interrupt. This handler may be called in + * either DMA mode or Slave mode. + */ +static int32_t handle_hc_babble_intr(dwc_otg_hcd_t *_hcd, + dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) +{ + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "Babble Error--\n", _hc->hc_num); + if (_hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { + dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EOVERFLOW); + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_BABBLE_ERR, must_free); + } else { + dwc_otg_halt_status_e halt_status; + halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd, + DWC_OTG_HC_XFER_BABBLE_ERR); + halt_channel(_hcd, _hc, _qtd, halt_status, must_free); + } + disable_hc_int(_hc_regs,bblerr); + return 1; +} + +/** + * Handles a host channel AHB error interrupt. This handler is only called in + * DMA mode. + */ +static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t *_hcd, + dwc_hc_t *_hc, + dwc_otg_hc_regs_t *_hc_regs, + dwc_otg_qtd_t *_qtd) +{ + hcchar_data_t hcchar; + hcsplt_data_t hcsplt; + hctsiz_data_t hctsiz; + uint32_t hcdma; + struct urb *urb = _qtd->urb; + + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "AHB Error--\n", _hc->hc_num); + + hcchar.d32 = dwc_read_reg32(&_hc_regs->hcchar); + hcsplt.d32 = dwc_read_reg32(&_hc_regs->hcsplt); + hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz); + hcdma = dwc_read_reg32(&_hc_regs->hcdma); + + DWC_ERROR("AHB ERROR, Channel %d\n", _hc->hc_num); + DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32); + DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma); + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n"); + DWC_ERROR(" Device address: %d\n", usb_pipedevice(urb->pipe)); + DWC_ERROR(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe), + (usb_pipein(urb->pipe) ? "IN" : "OUT")); + DWC_ERROR(" Endpoint type: %s\n", + ({char *pipetype; + switch (usb_pipetype(urb->pipe)) { + case PIPE_CONTROL: pipetype = "CONTROL"; break; + case PIPE_BULK: pipetype = "BULK"; break; + case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break; + case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break; + default: pipetype = "UNKNOWN"; break; + }; pipetype;})); + DWC_ERROR(" Speed: %s\n", + ({char *speed; + switch (urb->dev->speed) { + case USB_SPEED_HIGH: speed = "HIGH"; break; + case USB_SPEED_FULL: speed = "FULL"; break; + case USB_SPEED_LOW: speed = "LOW"; break; + default: speed = "UNKNOWN"; break; + }; speed;})); + DWC_ERROR(" Max packet size: %d\n", + usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); + DWC_ERROR(" Data buffer length: %d\n", urb->transfer_buffer_length); + DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n", + urb->transfer_buffer, (void *)(u32)urb->transfer_dma); + DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n", + urb->setup_packet, (void *)(u32)urb->setup_dma); + DWC_ERROR(" Interval: %d\n", urb->interval); + + dwc_otg_hcd_complete_urb(_hcd, urb, -EIO); + + /* + * Force a channel halt. Don't call halt_channel because that won't + * write to the HCCHARn register in DMA mode to force the halt. + */ + dwc_otg_hc_halt(_hcd->core_if, _hc, DWC_OTG_HC_XFER_AHB_ERR); + + disable_hc_int(_hc_regs,ahberr); + return 1; +} + +/** + * Handles a host channel transaction error interrupt. This handler may be + * called in either DMA mode or Slave mode. + */ +static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t *_hcd, + dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) +{ + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "Transaction Error--\n", _hc->hc_num); + + switch (usb_pipetype(_qtd->urb->pipe)) { + case PIPE_CONTROL: + case PIPE_BULK: + _qtd->error_count++; + if (!_hc->qh->ping_state) { + update_urb_state_xfer_intr(_hc, _hc_regs, _qtd->urb, + _qtd, DWC_OTG_HC_XFER_XACT_ERR); + save_data_toggle(_hc, _hc_regs, _qtd); + if (!_hc->ep_is_in && _qtd->urb->dev->speed == USB_SPEED_HIGH) { + _hc->qh->ping_state = 1; + } + } + + /* + * Halt the channel so the transfer can be re-started from + * the appropriate point or the PING protocol will start. + */ + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_XACT_ERR, must_free); + break; + case PIPE_INTERRUPT: + _qtd->error_count++; + if ((_hc->do_split) && (_hc->complete_split)) { + _qtd->complete_split = 0; + } + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_XACT_ERR, must_free); + break; + case PIPE_ISOCHRONOUS: + { + dwc_otg_halt_status_e halt_status; + halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd, + DWC_OTG_HC_XFER_XACT_ERR); + + halt_channel(_hcd, _hc, _qtd, halt_status, must_free); + } + break; + } + + + disable_hc_int(_hc_regs,xacterr); + + return 1; +} + +/** + * Handles a host channel frame overrun interrupt. This handler may be called + * in either DMA mode or Slave mode. + */ +static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t *_hcd, + dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) +{ + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "Frame Overrun--\n", _hc->hc_num); + + switch (usb_pipetype(_qtd->urb->pipe)) { + case PIPE_CONTROL: + case PIPE_BULK: + break; + case PIPE_INTERRUPT: + halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN, must_free); + break; + case PIPE_ISOCHRONOUS: + { + dwc_otg_halt_status_e halt_status; + halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd, + DWC_OTG_HC_XFER_FRAME_OVERRUN); + + halt_channel(_hcd, _hc, _qtd, halt_status, must_free); + } + break; + } + + disable_hc_int(_hc_regs,frmovrun); + + return 1; +} + +/** + * Handles a host channel data toggle error interrupt. This handler may be + * called in either DMA mode or Slave mode. + */ +static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t *_hcd, + dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) +{ + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "Data Toggle Error--\n", _hc->hc_num); + + if (_hc->ep_is_in) { + _qtd->error_count = 0; + } else { + DWC_ERROR("Data Toggle Error on OUT transfer," + "channel %d\n", _hc->hc_num); + } + + disable_hc_int(_hc_regs,datatglerr); + + return 1; +} + +#ifdef DEBUG +/** + * This function is for debug only. It checks that a valid halt status is set + * and that HCCHARn.chdis is clear. If there's a problem, corrective action is + * taken and a warning is issued. + * @return 1 if halt status is ok, 0 otherwise. + */ +static inline int halt_status_ok(dwc_otg_hcd_t *_hcd, + dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) +{ + hcchar_data_t hcchar; + hctsiz_data_t hctsiz; + hcint_data_t hcint; + hcintmsk_data_t hcintmsk; + hcsplt_data_t hcsplt; + + if (_hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) { + /* + * This code is here only as a check. This condition should + * never happen. Ignore the halt if it does occur. + */ + hcchar.d32 = dwc_read_reg32(&_hc_regs->hcchar); + hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz); + hcint.d32 = dwc_read_reg32(&_hc_regs->hcint); + hcintmsk.d32 = dwc_read_reg32(&_hc_regs->hcintmsk); + hcsplt.d32 = dwc_read_reg32(&_hc_regs->hcsplt); + DWC_WARN("%s: _hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, " + "channel %d, hcchar 0x%08x, hctsiz 0x%08x, " + "hcint 0x%08x, hcintmsk 0x%08x, " + "hcsplt 0x%08x, qtd->complete_split %d\n", + __func__, _hc->hc_num, hcchar.d32, hctsiz.d32, + hcint.d32, hcintmsk.d32, + hcsplt.d32, _qtd->complete_split); + + DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n", + __func__, _hc->hc_num); + DWC_WARN("\n"); + clear_hc_int(_hc_regs,chhltd); + return 0; + } + + /* + * This code is here only as a check. hcchar.chdis should + * never be set when the halt interrupt occurs. Halt the + * channel again if it does occur. + */ + hcchar.d32 = dwc_read_reg32(&_hc_regs->hcchar); + if (hcchar.b.chdis) { + DWC_WARN("%s: hcchar.chdis set unexpectedly, " + "hcchar 0x%08x, trying to halt again\n", + __func__, hcchar.d32); + clear_hc_int(_hc_regs,chhltd); + _hc->halt_pending = 0; + halt_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free); + return 0; + } + + return 1; +} +#endif + +/** + * Handles a host Channel Halted interrupt in DMA mode. This handler + * determines the reason the channel halted and proceeds accordingly. + */ +static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *_hcd, + dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) +{ + hcint_data_t hcint; + hcintmsk_data_t hcintmsk; + + if (_hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE || + _hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR) { + /* + * Just release the channel. A dequeue can happen on a + * transfer timeout. In the case of an AHB Error, the channel + * was forced to halt because there's no way to gracefully + * recover. + */ + release_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free); + return; + } + + /* Read the HCINTn register to determine the cause for the halt. */ + hcint.d32 = dwc_read_reg32(&_hc_regs->hcint); + hcintmsk.d32 = dwc_read_reg32(&_hc_regs->hcintmsk); + + if (hcint.b.xfercomp) { + /** @todo This is here because of a possible hardware bug. Spec + * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT + * interrupt w/ACK bit set should occur, but I only see the + * XFERCOMP bit, even with it masked out. This is a workaround + * for that behavior. Should fix this when hardware is fixed. + */ + if ((_hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && (!_hc->ep_is_in)) { + handle_hc_ack_intr(_hcd, _hc, _hc_regs, _qtd, must_free); + } + handle_hc_xfercomp_intr(_hcd, _hc, _hc_regs, _qtd, must_free); + } else if (hcint.b.stall) { + handle_hc_stall_intr(_hcd, _hc, _hc_regs, _qtd, must_free); + } else if (hcint.b.xacterr) { + /* + * Must handle xacterr before nak or ack. Could get a xacterr + * at the same time as either of these on a BULK/CONTROL OUT + * that started with a PING. The xacterr takes precedence. + */ + handle_hc_xacterr_intr(_hcd, _hc, _hc_regs, _qtd, must_free); + } else if (hcint.b.nyet) { + /* + * Must handle nyet before nak or ack. Could get a nyet at the + * same time as either of those on a BULK/CONTROL OUT that + * started with a PING. The nyet takes precedence. + */ + handle_hc_nyet_intr(_hcd, _hc, _hc_regs, _qtd, must_free); + } else if (hcint.b.bblerr) { + handle_hc_babble_intr(_hcd, _hc, _hc_regs, _qtd, must_free); + } else if (hcint.b.frmovrun) { + handle_hc_frmovrun_intr(_hcd, _hc, _hc_regs, _qtd, must_free); + } else if (hcint.b.datatglerr) { + handle_hc_datatglerr_intr(_hcd, _hc, _hc_regs, _qtd, must_free); + _hc->qh->data_toggle = 0; + halt_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free); + } else if (hcint.b.nak && !hcintmsk.b.nak) { + /* + * If nak is not masked, it's because a non-split IN transfer + * is in an error state. In that case, the nak is handled by + * the nak interrupt handler, not here. Handle nak here for + * BULK/CONTROL OUT transfers, which halt on a NAK to allow + * rewinding the buffer pointer. + */ + handle_hc_nak_intr(_hcd, _hc, _hc_regs, _qtd, must_free); + } else if (hcint.b.ack && !hcintmsk.b.ack) { + /* + * If ack is not masked, it's because a non-split IN transfer + * is in an error state. In that case, the ack is handled by + * the ack interrupt handler, not here. Handle ack here for + * split transfers. Start splits halt on ACK. + */ + handle_hc_ack_intr(_hcd, _hc, _hc_regs, _qtd, must_free); + } else { + if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR || + _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { + /* + * A periodic transfer halted with no other channel + * interrupts set. Assume it was halted by the core + * because it could not be completed in its scheduled + * (micro)frame. + */ +#ifdef DEBUG + DWC_PRINT("%s: Halt channel %d (assume incomplete periodic transfer)\n", + __func__, _hc->hc_num); +#endif /* */ + halt_channel(_hcd, _hc, _qtd, + DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE, must_free); + } else { +#ifdef DEBUG + DWC_ERROR("%s: Channel %d, DMA Mode -- ChHltd set, but reason " + "for halting is unknown, nyet %d, hcint 0x%08x, intsts 0x%08x\n", + __func__, _hc->hc_num, hcint.b.nyet, hcint.d32, + dwc_read_reg32(&_hcd->core_if->core_global_regs->gintsts)); +#endif + halt_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free); + } + } +} + +/** + * Handles a host channel Channel Halted interrupt. + * + * In slave mode, this handler is called only when the driver specifically + * requests a halt. This occurs during handling other host channel interrupts + * (e.g. nak, xacterr, stall, nyet, etc.). + * + * In DMA mode, this is the interrupt that occurs when the core has finished + * processing a transfer on a channel. Other host channel interrupts (except + * ahberr) are disabled in DMA mode. + */ +static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t *_hcd, + dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) +{ + DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "Channel Halted--\n", _hc->hc_num); + + if (_hcd->core_if->dma_enable) { + handle_hc_chhltd_intr_dma(_hcd, _hc, _hc_regs, _qtd, must_free); + } else { +#ifdef DEBUG + if (!halt_status_ok(_hcd, _hc, _hc_regs, _qtd, must_free)) { + return 1; + } +#endif /* */ + release_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free); + } + + return 1; +} + +/** Handles interrupt for a specific Host Channel */ +int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *_dwc_otg_hcd, uint32_t _num) +{ + int must_free = 0; + int retval = 0; + hcint_data_t hcint; + hcintmsk_data_t hcintmsk; + dwc_hc_t *hc; + dwc_otg_hc_regs_t *hc_regs; + dwc_otg_qtd_t *qtd; + + DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", _num); + + hc = _dwc_otg_hcd->hc_ptr_array[_num]; + hc_regs = _dwc_otg_hcd->core_if->host_if->hc_regs[_num]; + qtd = list_entry(hc->qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); + + hcint.d32 = dwc_read_reg32(&hc_regs->hcint); + hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk); + DWC_DEBUGPL(DBG_HCDV, " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n", + hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32)); + hcint.d32 = hcint.d32 & hcintmsk.d32; + + if (!_dwc_otg_hcd->core_if->dma_enable) { + if ((hcint.b.chhltd) && (hcint.d32 != 0x2)) { + hcint.b.chhltd = 0; + } + } + + if (hcint.b.xfercomp) { + retval |= handle_hc_xfercomp_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); + /* + * If NYET occurred at same time as Xfer Complete, the NYET is + * handled by the Xfer Complete interrupt handler. Don't want + * to call the NYET interrupt handler in this case. + */ + hcint.b.nyet = 0; + } + if (hcint.b.chhltd) { + retval |= handle_hc_chhltd_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); + } + if (hcint.b.ahberr) { + retval |= handle_hc_ahberr_intr(_dwc_otg_hcd, hc, hc_regs, qtd); + } + if (hcint.b.stall) { + retval |= handle_hc_stall_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); + } + if (hcint.b.nak) { + retval |= handle_hc_nak_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); + } + if (hcint.b.ack) { + retval |= handle_hc_ack_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); + } + if (hcint.b.nyet) { + retval |= handle_hc_nyet_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); + } + if (hcint.b.xacterr) { + retval |= handle_hc_xacterr_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); + } + if (hcint.b.bblerr) { + retval |= handle_hc_babble_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); + } + if (hcint.b.frmovrun) { + retval |= handle_hc_frmovrun_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); + } + if (hcint.b.datatglerr) { + retval |= handle_hc_datatglerr_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); + } + + /* + * Logic to free the qtd here, at the end of the hc intr + * processing, if the handling of this interrupt determined + * that it needs to be freed. + */ + if (must_free) { + /* Free the qtd here now that we are done using it. */ + dwc_otg_hcd_qtd_free(qtd); + } + return retval; +} + +#endif /* DWC_DEVICE_ONLY */ diff --git a/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c new file mode 100644 index 0000000000..fcb5ce634a --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c @@ -0,0 +1,794 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_queue.c $ + * $Revision: 1.1.1.1 $ + * $Date: 2009-04-17 06:15:34 $ + * $Change: 537387 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ +#ifndef DWC_DEVICE_ONLY + +/** + * @file + * + * This file contains the functions to manage Queue Heads and Queue + * Transfer Descriptors. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dwc_otg_driver.h" +#include "dwc_otg_hcd.h" +#include "dwc_otg_regs.h" + +/** + * This function allocates and initializes a QH. + * + * @param _hcd The HCD state structure for the DWC OTG controller. + * @param[in] _urb Holds the information about the device/endpoint that we need + * to initialize the QH. + * + * @return Returns pointer to the newly allocated QH, or NULL on error. */ +dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *_hcd, struct urb *_urb) +{ + dwc_otg_qh_t *qh; + + /* Allocate memory */ + /** @todo add memflags argument */ + qh = dwc_otg_hcd_qh_alloc (); + if (qh == NULL) { + return NULL; + } + + dwc_otg_hcd_qh_init (_hcd, qh, _urb); + return qh; +} + +/** Free each QTD in the QH's QTD-list then free the QH. QH should already be + * removed from a list. QTD list should already be empty if called from URB + * Dequeue. + * + * @param[in] _qh The QH to free. + */ +void dwc_otg_hcd_qh_free (dwc_otg_qh_t *_qh) +{ + dwc_otg_qtd_t *qtd; + struct list_head *pos; + unsigned long flags; + + /* Free each QTD in the QTD list */ + local_irq_save (flags); + for (pos = _qh->qtd_list.next; + pos != &_qh->qtd_list; + pos = _qh->qtd_list.next) + { + list_del (pos); + qtd = dwc_list_to_qtd (pos); + dwc_otg_hcd_qtd_free (qtd); + } + local_irq_restore (flags); + + kfree (_qh); + return; +} + +/** Initializes a QH structure. + * + * @param[in] _hcd The HCD state structure for the DWC OTG controller. + * @param[in] _qh The QH to init. + * @param[in] _urb Holds the information about the device/endpoint that we need + * to initialize the QH. */ +#define SCHEDULE_SLOP 10 +void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, struct urb *_urb) +{ + memset (_qh, 0, sizeof (dwc_otg_qh_t)); + + /* Initialize QH */ + switch (usb_pipetype(_urb->pipe)) { + case PIPE_CONTROL: + _qh->ep_type = USB_ENDPOINT_XFER_CONTROL; + break; + case PIPE_BULK: + _qh->ep_type = USB_ENDPOINT_XFER_BULK; + break; + case PIPE_ISOCHRONOUS: + _qh->ep_type = USB_ENDPOINT_XFER_ISOC; + break; + case PIPE_INTERRUPT: + _qh->ep_type = USB_ENDPOINT_XFER_INT; + break; + } + + _qh->ep_is_in = usb_pipein(_urb->pipe) ? 1 : 0; + + _qh->data_toggle = DWC_OTG_HC_PID_DATA0; + _qh->maxp = usb_maxpacket(_urb->dev, _urb->pipe, !(usb_pipein(_urb->pipe))); + INIT_LIST_HEAD(&_qh->qtd_list); + INIT_LIST_HEAD(&_qh->qh_list_entry); + _qh->channel = NULL; + + /* FS/LS Enpoint on HS Hub + * NOT virtual root hub */ + _qh->do_split = 0; + _qh->speed = _urb->dev->speed; + if (((_urb->dev->speed == USB_SPEED_LOW) || + (_urb->dev->speed == USB_SPEED_FULL)) && + (_urb->dev->tt) && (_urb->dev->tt->hub) && (_urb->dev->tt->hub->devnum != 1)) { + DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n", + usb_pipeendpoint(_urb->pipe), _urb->dev->tt->hub->devnum, + _urb->dev->ttport); + _qh->do_split = 1; + } + + if (_qh->ep_type == USB_ENDPOINT_XFER_INT || + _qh->ep_type == USB_ENDPOINT_XFER_ISOC) { + /* Compute scheduling parameters once and save them. */ + hprt0_data_t hprt; + + /** @todo Account for split transfers in the bus time. */ + int bytecount = dwc_hb_mult(_qh->maxp) * dwc_max_packet(_qh->maxp); + _qh->usecs = NS_TO_US(usb_calc_bus_time(_urb->dev->speed, + usb_pipein(_urb->pipe), + (_qh->ep_type == USB_ENDPOINT_XFER_ISOC),bytecount)); + + /* Start in a slightly future (micro)frame. */ + _qh->sched_frame = dwc_frame_num_inc(_hcd->frame_number, SCHEDULE_SLOP); + _qh->interval = _urb->interval; +#if 0 + /* Increase interrupt polling rate for debugging. */ + if (_qh->ep_type == USB_ENDPOINT_XFER_INT) { + _qh->interval = 8; + } +#endif + hprt.d32 = dwc_read_reg32(_hcd->core_if->host_if->hprt0); + if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) && + ((_urb->dev->speed == USB_SPEED_LOW) || + (_urb->dev->speed == USB_SPEED_FULL))) + { + _qh->interval *= 8; + _qh->sched_frame |= 0x7; + _qh->start_split_frame = _qh->sched_frame; + } + } + + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n"); + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", _qh); + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n", + _urb->dev->devnum); + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n", + usb_pipeendpoint(_urb->pipe), + usb_pipein(_urb->pipe) == USB_DIR_IN ? "IN" : "OUT"); + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", + ({ char *speed; switch (_urb->dev->speed) { + case USB_SPEED_LOW: speed = "low"; break; + case USB_SPEED_FULL: speed = "full"; break; + case USB_SPEED_HIGH: speed = "high"; break; + default: speed = "?"; break; + }; speed;})); + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n", + ({ char *type; switch (_qh->ep_type) { + case USB_ENDPOINT_XFER_ISOC: type = "isochronous"; break; + case USB_ENDPOINT_XFER_INT: type = "interrupt"; break; + case USB_ENDPOINT_XFER_CONTROL: type = "control"; break; + case USB_ENDPOINT_XFER_BULK: type = "bulk"; break; + default: type = "?"; break; + }; type;})); +#ifdef DEBUG + if (_qh->ep_type == USB_ENDPOINT_XFER_INT) { + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n", + _qh->usecs); + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n", + _qh->interval); + } +#endif + + return; +} + +/** + * Microframe scheduler + * track the total use in hcd->frame_usecs + * keep each qh use in qh->frame_usecs + * when surrendering the qh then donate the time back + */ +const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 }; + +/* + * called from dwc_otg_hcd.c:dwc_otg_hcd_init + */ +int init_hcd_usecs(dwc_otg_hcd_t *_hcd) +{ + int i; + for (i=0; i<8; i++) { + _hcd->frame_usecs[i] = max_uframe_usecs[i]; + } + return 0; +} + +static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) +{ + int i; + unsigned short utime; + int t_left; + int ret; + int done; + + ret = -1; + utime = _qh->usecs; + t_left = utime; + i = 0; + done = 0; + while (done == 0) { + /* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */ + if (utime <= _hcd->frame_usecs[i]) { + _hcd->frame_usecs[i] -= utime; + _qh->frame_usecs[i] += utime; + t_left -= utime; + ret = i; + done = 1; + return ret; + } else { + i++; + if (i == 8) { + done = 1; + ret = -1; + } + } + } + return ret; +} + +/* + * use this for FS apps that can span multiple uframes + */ +static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) +{ + int i; + int j; + unsigned short utime; + int t_left; + int ret; + int done; + unsigned short xtime; + + ret = -1; + utime = _qh->usecs; + t_left = utime; + i = 0; + done = 0; +loop: + while (done == 0) { + if(_hcd->frame_usecs[i] <= 0) { + i++; + if (i == 8) { + done = 1; + ret = -1; + } + goto loop; + } + + /* + * we need n consequtive slots + * so use j as a start slot j plus j+1 must be enough time (for now) + */ + xtime= _hcd->frame_usecs[i]; + for (j = i+1 ; j < 8 ; j++ ) { + /* + * if we add this frame remaining time to xtime we may + * be OK, if not we need to test j for a complete frame + */ + if ((xtime+_hcd->frame_usecs[j]) < utime) { + if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) { + j = 8; + ret = -1; + continue; + } + } + if (xtime >= utime) { + ret = i; + j = 8; /* stop loop with a good value ret */ + continue; + } + /* add the frame time to x time */ + xtime += _hcd->frame_usecs[j]; + /* we must have a fully available next frame or break */ + if ((xtime < utime) + && (_hcd->frame_usecs[j] == max_uframe_usecs[j])) { + ret = -1; + j = 8; /* stop loop with a bad value ret */ + continue; + } + } + if (ret >= 0) { + t_left = utime; + for (j = i; (t_left>0) && (j < 8); j++ ) { + t_left -= _hcd->frame_usecs[j]; + if ( t_left <= 0 ) { + _qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left; + _hcd->frame_usecs[j]= -t_left; + ret = i; + done = 1; + } else { + _qh->frame_usecs[j] += _hcd->frame_usecs[j]; + _hcd->frame_usecs[j] = 0; + } + } + } else { + i++; + if (i == 8) { + done = 1; + ret = -1; + } + } + } + return ret; +} + +static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) +{ + int ret; + ret = -1; + + if (_qh->speed == USB_SPEED_HIGH) { + /* if this is a hs transaction we need a full frame */ + ret = find_single_uframe(_hcd, _qh); + } else { + /* if this is a fs transaction we may need a sequence of frames */ + ret = find_multi_uframe(_hcd, _qh); + } + return ret; +} + +/** + * Checks that the max transfer size allowed in a host channel is large enough + * to handle the maximum data transfer in a single (micro)frame for a periodic + * transfer. + * + * @param _hcd The HCD state structure for the DWC OTG controller. + * @param _qh QH for a periodic endpoint. + * + * @return 0 if successful, negative error code otherwise. + */ +static int check_max_xfer_size(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh) +{ + int status; + uint32_t max_xfer_size; + uint32_t max_channel_xfer_size; + + status = 0; + + max_xfer_size = dwc_max_packet(_qh->maxp) * dwc_hb_mult(_qh->maxp); + max_channel_xfer_size = _hcd->core_if->core_params->max_transfer_size; + + if (max_xfer_size > max_channel_xfer_size) { + DWC_NOTICE("%s: Periodic xfer length %d > " + "max xfer length for channel %d\n", + __func__, max_xfer_size, max_channel_xfer_size); + status = -ENOSPC; + } + + return status; +} + +/** + * Schedules an interrupt or isochronous transfer in the periodic schedule. + * + * @param _hcd The HCD state structure for the DWC OTG controller. + * @param _qh QH for the periodic transfer. The QH should already contain the + * scheduling information. + * + * @return 0 if successful, negative error code otherwise. + */ +static int schedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh) +{ + int status = 0; + + int frame; + status = find_uframe(_hcd, _qh); + frame = -1; + if (status == 0) { + frame = 7; + } else { + if (status > 0 ) + frame = status-1; + } + + /* Set the new frame up */ + if (frame > -1) { + _qh->sched_frame &= ~0x7; + _qh->sched_frame |= (frame & 7); + } + + if (status != -1 ) + status = 0; + if (status) { + DWC_NOTICE("%s: Insufficient periodic bandwidth for " + "periodic transfer.\n", __func__); + return status; + } + + status = check_max_xfer_size(_hcd, _qh); + if (status) { + DWC_NOTICE("%s: Channel max transfer size too small " + "for periodic transfer.\n", __func__); + return status; + } + + /* Always start in the inactive schedule. */ + list_add_tail(&_qh->qh_list_entry, &_hcd->periodic_sched_inactive); + + + /* Update claimed usecs per (micro)frame. */ + _hcd->periodic_usecs += _qh->usecs; + + /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */ + hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated += _qh->usecs / _qh->interval; + if (_qh->ep_type == USB_ENDPOINT_XFER_INT) { + hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs++; + DWC_DEBUGPL(DBG_HCD, "Scheduled intr: qh %p, usecs %d, period %d\n", + _qh, _qh->usecs, _qh->interval); + } else { + hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs++; + DWC_DEBUGPL(DBG_HCD, "Scheduled isoc: qh %p, usecs %d, period %d\n", + _qh, _qh->usecs, _qh->interval); + } + + return status; +} + +/** + * This function adds a QH to either the non periodic or periodic schedule if + * it is not already in the schedule. If the QH is already in the schedule, no + * action is taken. + * + * @return 0 if successful, negative error code otherwise. + */ +int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh) +{ + unsigned long flags; + int status = 0; + + local_irq_save(flags); + + if (!list_empty(&_qh->qh_list_entry)) { + /* QH already in a schedule. */ + goto done; + } + + /* Add the new QH to the appropriate schedule */ + if (dwc_qh_is_non_per(_qh)) { + /* Always start in the inactive schedule. */ + list_add_tail(&_qh->qh_list_entry, &_hcd->non_periodic_sched_inactive); + } else { + status = schedule_periodic(_hcd, _qh); + } + + done: + local_irq_restore(flags); + + return status; +} + +/** + * This function adds a QH to the non periodic deferred schedule. + * + * @return 0 if successful, negative error code otherwise. + */ +int dwc_otg_hcd_qh_add_deferred(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) +{ + unsigned long flags; + local_irq_save(flags); + if (!list_empty(&_qh->qh_list_entry)) { + /* QH already in a schedule. */ + goto done; + } + + /* Add the new QH to the non periodic deferred schedule */ + if (dwc_qh_is_non_per(_qh)) { + list_add_tail(&_qh->qh_list_entry, + &_hcd->non_periodic_sched_deferred); + } +done: + local_irq_restore(flags); + return 0; +} + +/** + * Removes an interrupt or isochronous transfer from the periodic schedule. + * + * @param _hcd The HCD state structure for the DWC OTG controller. + * @param _qh QH for the periodic transfer. + */ +static void deschedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh) +{ + int i; + list_del_init(&_qh->qh_list_entry); + + + /* Update claimed usecs per (micro)frame. */ + _hcd->periodic_usecs -= _qh->usecs; + + for (i = 0; i < 8; i++) { + _hcd->frame_usecs[i] += _qh->frame_usecs[i]; + _qh->frame_usecs[i] = 0; + } + /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */ + hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated -= _qh->usecs / _qh->interval; + + if (_qh->ep_type == USB_ENDPOINT_XFER_INT) { + hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs--; + DWC_DEBUGPL(DBG_HCD, "Descheduled intr: qh %p, usecs %d, period %d\n", + _qh, _qh->usecs, _qh->interval); + } else { + hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs--; + DWC_DEBUGPL(DBG_HCD, "Descheduled isoc: qh %p, usecs %d, period %d\n", + _qh, _qh->usecs, _qh->interval); + } +} + +/** + * Removes a QH from either the non-periodic or periodic schedule. Memory is + * not freed. + * + * @param[in] _hcd The HCD state structure. + * @param[in] _qh QH to remove from schedule. */ +void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh) +{ + unsigned long flags; + + local_irq_save(flags); + + if (list_empty(&_qh->qh_list_entry)) { + /* QH is not in a schedule. */ + goto done; + } + + if (dwc_qh_is_non_per(_qh)) { + if (_hcd->non_periodic_qh_ptr == &_qh->qh_list_entry) { + _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next; + } + list_del_init(&_qh->qh_list_entry); + } else { + deschedule_periodic(_hcd, _qh); + } + + done: + local_irq_restore(flags); +} + +/** + * Defers a QH. For non-periodic QHs, removes the QH from the active + * non-periodic schedule. The QH is added to the deferred non-periodic + * schedule if any QTDs are still attached to the QH. + */ +int dwc_otg_hcd_qh_deferr(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh, int delay) +{ + int deact = 1; + unsigned long flags; + local_irq_save(flags); + if (dwc_qh_is_non_per(_qh)) { + _qh->sched_frame = + dwc_frame_num_inc(_hcd->frame_number, + delay); + _qh->channel = NULL; + _qh->qtd_in_process = NULL; + deact = 0; + dwc_otg_hcd_qh_remove(_hcd, _qh); + if (!list_empty(&_qh->qtd_list)) { + /* Add back to deferred non-periodic schedule. */ + dwc_otg_hcd_qh_add_deferred(_hcd, _qh); + } + } + local_irq_restore(flags); + return deact; +} + +/** + * Deactivates a QH. For non-periodic QHs, removes the QH from the active + * non-periodic schedule. The QH is added to the inactive non-periodic + * schedule if any QTDs are still attached to the QH. + * + * For periodic QHs, the QH is removed from the periodic queued schedule. If + * there are any QTDs still attached to the QH, the QH is added to either the + * periodic inactive schedule or the periodic ready schedule and its next + * scheduled frame is calculated. The QH is placed in the ready schedule if + * the scheduled frame has been reached already. Otherwise it's placed in the + * inactive schedule. If there are no QTDs attached to the QH, the QH is + * completely removed from the periodic schedule. + */ +void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int sched_next_periodic_split) +{ + unsigned long flags; + local_irq_save(flags); + + if (dwc_qh_is_non_per(_qh)) { + dwc_otg_hcd_qh_remove(_hcd, _qh); + if (!list_empty(&_qh->qtd_list)) { + /* Add back to inactive non-periodic schedule. */ + dwc_otg_hcd_qh_add(_hcd, _qh); + } + } else { + uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd)); + + if (_qh->do_split) { + /* Schedule the next continuing periodic split transfer */ + if (sched_next_periodic_split) { + + _qh->sched_frame = frame_number; + if (dwc_frame_num_le(frame_number, + dwc_frame_num_inc(_qh->start_split_frame, 1))) { + /* + * Allow one frame to elapse after start + * split microframe before scheduling + * complete split, but DONT if we are + * doing the next start split in the + * same frame for an ISOC out. + */ + if ((_qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (_qh->ep_is_in != 0)) { + _qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, 1); + } + } + } else { + _qh->sched_frame = dwc_frame_num_inc(_qh->start_split_frame, + _qh->interval); + if (dwc_frame_num_le(_qh->sched_frame, frame_number)) { + _qh->sched_frame = frame_number; + } + _qh->sched_frame |= 0x7; + _qh->start_split_frame = _qh->sched_frame; + } + } else { + _qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, _qh->interval); + if (dwc_frame_num_le(_qh->sched_frame, frame_number)) { + _qh->sched_frame = frame_number; + } + } + + if (list_empty(&_qh->qtd_list)) { + dwc_otg_hcd_qh_remove(_hcd, _qh); + } else { + /* + * Remove from periodic_sched_queued and move to + * appropriate queue. + */ + if (dwc_frame_num_le(_qh->sched_frame, frame_number)) { + list_move(&_qh->qh_list_entry, + &_hcd->periodic_sched_ready); + } else { + list_move(&_qh->qh_list_entry, + &_hcd->periodic_sched_inactive); + } + } + } + + local_irq_restore(flags); +} + +/** + * This function allocates and initializes a QTD. + * + * @param[in] _urb The URB to create a QTD from. Each URB-QTD pair will end up + * pointing to each other so each pair should have a unique correlation. + * + * @return Returns pointer to the newly allocated QTD, or NULL on error. */ +dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *_urb) +{ + dwc_otg_qtd_t *qtd; + + qtd = dwc_otg_hcd_qtd_alloc (); + if (qtd == NULL) { + return NULL; + } + + dwc_otg_hcd_qtd_init (qtd, _urb); + return qtd; +} + +/** + * Initializes a QTD structure. + * + * @param[in] _qtd The QTD to initialize. + * @param[in] _urb The URB to use for initialization. */ +void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *_qtd, struct urb *_urb) +{ + memset (_qtd, 0, sizeof (dwc_otg_qtd_t)); + _qtd->urb = _urb; + if (usb_pipecontrol(_urb->pipe)) { + /* + * The only time the QTD data toggle is used is on the data + * phase of control transfers. This phase always starts with + * DATA1. + */ + _qtd->data_toggle = DWC_OTG_HC_PID_DATA1; + _qtd->control_phase = DWC_OTG_CONTROL_SETUP; + } + + /* start split */ + _qtd->complete_split = 0; + _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL; + _qtd->isoc_split_offset = 0; + + /* Store the qtd ptr in the urb to reference what QTD. */ + _urb->hcpriv = _qtd; + return; +} + +/** + * This function adds a QTD to the QTD-list of a QH. It will find the correct + * QH to place the QTD into. If it does not find a QH, then it will create a + * new QH. If the QH to which the QTD is added is not currently scheduled, it + * is placed into the proper schedule based on its EP type. + * + * @param[in] _qtd The QTD to add + * @param[in] _dwc_otg_hcd The DWC HCD structure + * + * @return 0 if successful, negative error code otherwise. + */ +int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * _qtd, dwc_otg_hcd_t * _dwc_otg_hcd) +{ + struct usb_host_endpoint *ep; + dwc_otg_qh_t *qh; + unsigned long flags; + int retval = 0; + struct urb *urb = _qtd->urb; + + local_irq_save(flags); + + /* + * Get the QH which holds the QTD-list to insert to. Create QH if it + * doesn't exist. + */ + ep = dwc_urb_to_endpoint(urb); + qh = (dwc_otg_qh_t *)ep->hcpriv; + if (qh == NULL) { + qh = dwc_otg_hcd_qh_create (_dwc_otg_hcd, urb); + if (qh == NULL) { + retval = -1; + goto done; + } + ep->hcpriv = qh; + } + + _qtd->qtd_qh_ptr = qh; + retval = dwc_otg_hcd_qh_add(_dwc_otg_hcd, qh); + if (retval == 0) { + list_add_tail(&_qtd->qtd_list_entry, &qh->qtd_list); + } + + done: + local_irq_restore(flags); + return retval; +} + +#endif /* DWC_DEVICE_ONLY */ diff --git a/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_ifx.c b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_ifx.c new file mode 100644 index 0000000000..e45da853ea --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_ifx.c @@ -0,0 +1,103 @@ +/****************************************************************************** +** +** FILE NAME : dwc_otg_ifx.c +** PROJECT : Twinpass/Danube +** MODULES : DWC OTG USB +** +** DATE : 12 Auguest 2007 +** AUTHOR : Sung Winder +** DESCRIPTION : Platform specific initialization. +** COPYRIGHT : Copyright (c) 2007 +** Infineon Technologies AG +** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park, +** Hsin-chu City, 300 Taiwan. +** +** This program is free software; you can redistribute it and/or modify +** it under the terms of the GNU General Public License as published by +** the Free Software Foundation; either version 2 of the License, or +** (at your option) any later version. +** +** HISTORY +** $Date $Author $Comment +** 12 Auguest 2007 Sung Winder Initiate Version +*******************************************************************************/ +#include "dwc_otg_ifx.h" + +#include +#include +#include +#include + +#include +//#include +#include + +#define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00) + +#define IFXMIPS_GPIO_P0_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0010)) +#define IFXMIPS_GPIO_P1_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0040)) +#define IFXMIPS_GPIO_P0_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0014)) +#define IFXMIPS_GPIO_P1_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0044)) +#define IFXMIPS_GPIO_P0_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0018)) +#define IFXMIPS_GPIO_P1_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0048)) +#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x001C)) +#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x004C)) +#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0020)) +#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0050)) +#define IFXMIPS_GPIO_P0_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0024)) +#define IFXMIPS_GPIO_P1_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0054)) +#define IFXMIPS_GPIO_P0_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0028)) +#define IFXMIPS_GPIO_P1_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0058)) +#define IFXMIPS_GPIO_P0_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x002C)) +#define IFXMIPS_GPIO_P1_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x005C)) +#define IFXMIPS_GPIO_P0_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0030)) +#define IFXMIPS_GPIO_P1_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0060)) + + +#define writel ltq_w32 +#define readl ltq_r32 +void dwc_otg_power_on (void) +{ + // clear power + writel(readl(DANUBE_PMU_PWDCR) | 0x41, DANUBE_PMU_PWDCR); + // set clock gating + if (ltq_is_ase()) + writel(readl(DANUBE_CGU_IFCCR) & ~0x20, DANUBE_CGU_IFCCR); + else + writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR); + // set power + writel(readl(DANUBE_PMU_PWDCR) & ~0x1, DANUBE_PMU_PWDCR); + writel(readl(DANUBE_PMU_PWDCR) & ~0x40, DANUBE_PMU_PWDCR); + writel(readl(DANUBE_PMU_PWDCR) & ~0x8000, DANUBE_PMU_PWDCR); + +#if 1//defined (DWC_HOST_ONLY) + // make the hardware be a host controller (default) + //clear_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG); + writel(readl(DANUBE_RCU_UBSCFG) & ~(1< +#include + +// 20070316, winder added. +#ifndef SZ_256K +#define SZ_256K 0x00040000 +#endif + +extern void dwc_otg_power_on (void); + +/* FIXME: The current Linux-2.6 do not have these header files, but anyway, we need these. */ +// #include +// #include + +/* winder, I used the Danube parameter as default. * + * We could change this through module param. */ +#define IFX_USB_IOMEM_BASE 0x1e101000 +#define IFX_USB_IOMEM_SIZE SZ_256K +#define IFX_USB_IRQ LTQ_USB_INT + +/** + * This function is called to set correct clock gating and power. + * For Twinpass/Danube board. + */ +#ifndef DANUBE_RCU_BASE_ADDR +#define DANUBE_RCU_BASE_ADDR (0xBF203000) +#endif + +#ifndef DANUBE_CGU +#define DANUBE_CGU (0xBF103000) +#endif +#ifndef DANUBE_CGU_IFCCR +/***CGU Interface Clock Control Register***/ +#define DANUBE_CGU_IFCCR ((volatile u32*)(DANUBE_CGU+ 0x0018)) +#endif + +#ifndef DANUBE_PMU +#define DANUBE_PMU (KSEG1+0x1F102000) +#endif +#ifndef DANUBE_PMU_PWDCR +/* PMU Power down Control Register */ +#define DANUBE_PMU_PWDCR ((volatile u32*)(DANUBE_PMU+0x001C)) +#endif + + +#define DANUBE_RCU_UBSCFG ((volatile u32*)(DANUBE_RCU_BASE_ADDR + 0x18)) +#define DANUBE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device +#define DANUBE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end +#define DANUBE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end + +extern void ltq_mask_and_ack_irq(struct irq_data *d); + +static void inline mask_and_ack_ifx_irq(int x) +{ + struct irq_data d; + d.irq = x; + ltq_mask_and_ack_irq(&d); +} +#endif //__DWC_OTG_IFX_H__ diff --git a/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_plat.h b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_plat.h new file mode 100644 index 0000000000..727d0c4a52 --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_plat.h @@ -0,0 +1,269 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/platform/dwc_otg_plat.h $ + * $Revision: 1.1.1.1 $ + * $Date: 2009-04-17 06:15:34 $ + * $Change: 510301 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ + +#if !defined(__DWC_OTG_PLAT_H__) +#define __DWC_OTG_PLAT_H__ + +#include +#include +#include +#include +#include + +/** + * @file + * + * This file contains the Platform Specific constants, interfaces + * (functions and macros) for Linux. + * + */ +/*#if !defined(__LINUX__) +#error "The contents of this file is Linux specific!!!" +#endif +*/ +#include +#define writel ltq_w32 +#define readl ltq_r32 + +/** + * Reads the content of a register. + * + * @param _reg address of register to read. + * @return contents of the register. + * + + * Usage:
+ * uint32_t dev_ctl = dwc_read_reg32(&dev_regs->dctl); + */ +static __inline__ uint32_t dwc_read_reg32( volatile uint32_t *_reg) +{ + return readl(_reg); +}; + +/** + * Writes a register with a 32 bit value. + * + * @param _reg address of register to read. + * @param _value to write to _reg. + * + * Usage:
+ * dwc_write_reg32(&dev_regs->dctl, 0); + */ +static __inline__ void dwc_write_reg32( volatile uint32_t *_reg, const uint32_t _value) +{ + writel( _value, _reg ); +}; + +/** + * This function modifies bit values in a register. Using the + * algorithm: (reg_contents & ~clear_mask) | set_mask. + * + * @param _reg address of register to read. + * @param _clear_mask bit mask to be cleared. + * @param _set_mask bit mask to be set. + * + * Usage:
+ * // Clear the SOF Interrupt Mask bit and
+ * // set the OTG Interrupt mask bit, leaving all others as they were. + * dwc_modify_reg32(&dev_regs->gintmsk, DWC_SOF_INT, DWC_OTG_INT); + */ +static __inline__ + void dwc_modify_reg32( volatile uint32_t *_reg, const uint32_t _clear_mask, const uint32_t _set_mask) +{ + writel( (readl(_reg) & ~_clear_mask) | _set_mask, _reg ); +}; + + +/** + * Wrapper for the OS micro-second delay function. + * @param[in] _usecs Microseconds of delay + */ +static __inline__ void UDELAY( const uint32_t _usecs ) +{ + udelay( _usecs ); +} + +/** + * Wrapper for the OS milli-second delay function. + * @param[in] _msecs milliseconds of delay + */ +static __inline__ void MDELAY( const uint32_t _msecs ) +{ + mdelay( _msecs ); +} + +/** + * Wrapper for the Linux spin_lock. On the ARM (Integrator) + * spin_lock() is a nop. + * + * @param _lock Pointer to the spinlock. + */ +static __inline__ void SPIN_LOCK( spinlock_t *_lock ) +{ + spin_lock(_lock); +} + +/** + * Wrapper for the Linux spin_unlock. On the ARM (Integrator) + * spin_lock() is a nop. + * + * @param _lock Pointer to the spinlock. + */ +static __inline__ void SPIN_UNLOCK( spinlock_t *_lock ) +{ + spin_unlock(_lock); +} + +/** + * Wrapper (macro) for the Linux spin_lock_irqsave. On the ARM + * (Integrator) spin_lock() is a nop. + * + * @param _l Pointer to the spinlock. + * @param _f unsigned long for irq flags storage. + */ +#define SPIN_LOCK_IRQSAVE( _l, _f ) { \ + spin_lock_irqsave(_l,_f); \ + } + +/** + * Wrapper (macro) for the Linux spin_unlock_irqrestore. On the ARM + * (Integrator) spin_lock() is a nop. + * + * @param _l Pointer to the spinlock. + * @param _f unsigned long for irq flags storage. + */ +#define SPIN_UNLOCK_IRQRESTORE( _l,_f ) {\ + spin_unlock_irqrestore(_l,_f); \ + } + + +/* + * Debugging support vanishes in non-debug builds. + */ + + +/** + * The Debug Level bit-mask variable. + */ +extern uint32_t g_dbg_lvl; +/** + * Set the Debug Level variable. + */ +static inline uint32_t SET_DEBUG_LEVEL( const uint32_t _new ) +{ + uint32_t old = g_dbg_lvl; + g_dbg_lvl = _new; + return old; +} + +/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */ +#define DBG_CIL (0x2) +/** When debug level has the DBG_CILV bit set, display CIL Verbose debug + * messages */ +#define DBG_CILV (0x20) +/** When debug level has the DBG_PCD bit set, display PCD (Device) debug + * messages */ +#define DBG_PCD (0x4) +/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug + * messages */ +#define DBG_PCDV (0x40) +/** When debug level has the DBG_HCD bit set, display Host debug messages */ +#define DBG_HCD (0x8) +/** When debug level has the DBG_HCDV bit set, display Verbose Host debug + * messages */ +#define DBG_HCDV (0x80) +/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host + * mode. */ +#define DBG_HCD_URB (0x800) + +/** When debug level has any bit set, display debug messages */ +#define DBG_ANY (0xFF) + +/** All debug messages off */ +#define DBG_OFF 0 + +/** Prefix string for DWC_DEBUG print macros. */ +#define USB_DWC "DWC_otg: " + +/** + * Print a debug message when the Global debug level variable contains + * the bit defined in lvl. + * + * @param[in] lvl - Debug level, use one of the DBG_ constants above. + * @param[in] x - like printf + * + * Example:

+ * + * DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr); + * + *
+ * results in:
+ * + * usb-DWC_otg: dwc_otg_cil_init(ca867000) + * + */ +#ifdef DEBUG + +# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)printk( KERN_DEBUG USB_DWC x ); }while(0) +# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x ) + +# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl) + +#else + +# define DWC_DEBUGPL(lvl, x...) do{}while(0) +# define DWC_DEBUGP(x...) + +# define CHK_DEBUG_LEVEL(level) (0) + +#endif /*DEBUG*/ + +/** + * Print an Error message. + */ +#define DWC_ERROR(x...) printk( KERN_ERR USB_DWC x ) +/** + * Print a Warning message. + */ +#define DWC_WARN(x...) printk( KERN_WARNING USB_DWC x ) +/** + * Print a notice (normal but significant message). + */ +#define DWC_NOTICE(x...) printk( KERN_NOTICE USB_DWC x ) +/** + * Basic message printing. + */ +#define DWC_PRINT(x...) printk( KERN_INFO USB_DWC x ) + +#endif + diff --git a/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_regs.h b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_regs.h new file mode 100644 index 0000000000..397a954f39 --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/dwc_otg/dwc_otg_regs.h @@ -0,0 +1,1797 @@ +/* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_regs.h $ + * $Revision: 1.1.1.1 $ + * $Date: 2009-04-17 06:15:34 $ + * $Change: 631780 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. + * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and + * redistribute this Software in source and binary forms, with or without + * modification, provided that redistributions of source code must retain this + * notice. You may not view, use, disclose, copy or distribute this file or + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. + * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================== */ + +#ifndef __DWC_OTG_REGS_H__ +#define __DWC_OTG_REGS_H__ + +/** + * @file + * + * This file contains the data structures for accessing the DWC_otg core registers. + * + * The application interfaces with the HS OTG core by reading from and + * writing to the Control and Status Register (CSR) space through the + * AHB Slave interface. These registers are 32 bits wide, and the + * addresses are 32-bit-block aligned. + * CSRs are classified as follows: + * - Core Global Registers + * - Device Mode Registers + * - Device Global Registers + * - Device Endpoint Specific Registers + * - Host Mode Registers + * - Host Global Registers + * - Host Port CSRs + * - Host Channel Specific Registers + * + * Only the Core Global registers can be accessed in both Device and + * Host modes. When the HS OTG core is operating in one mode, either + * Device or Host, the application must not access registers from the + * other mode. When the core switches from one mode to another, the + * registers in the new mode of operation must be reprogrammed as they + * would be after a power-on reset. + */ + +/****************************************************************************/ +/** DWC_otg Core registers . + * The dwc_otg_core_global_regs structure defines the size + * and relative field offsets for the Core Global registers. + */ +typedef struct dwc_otg_core_global_regs +{ + /** OTG Control and Status Register. Offset: 000h */ + volatile uint32_t gotgctl; + /** OTG Interrupt Register. Offset: 004h */ + volatile uint32_t gotgint; + /**Core AHB Configuration Register. Offset: 008h */ + volatile uint32_t gahbcfg; +#define DWC_GLBINTRMASK 0x0001 +#define DWC_DMAENABLE 0x0020 +#define DWC_NPTXEMPTYLVL_EMPTY 0x0080 +#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000 +#define DWC_PTXEMPTYLVL_EMPTY 0x0100 +#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000 + + + /**Core USB Configuration Register. Offset: 00Ch */ + volatile uint32_t gusbcfg; + /**Core Reset Register. Offset: 010h */ + volatile uint32_t grstctl; + /**Core Interrupt Register. Offset: 014h */ + volatile uint32_t gintsts; + /**Core Interrupt Mask Register. Offset: 018h */ + volatile uint32_t gintmsk; + /**Receive Status Queue Read Register (Read Only). Offset: 01Ch */ + volatile uint32_t grxstsr; + /**Receive Status Queue Read & POP Register (Read Only). Offset: 020h*/ + volatile uint32_t grxstsp; + /**Receive FIFO Size Register. Offset: 024h */ + volatile uint32_t grxfsiz; + /**Non Periodic Transmit FIFO Size Register. Offset: 028h */ + volatile uint32_t gnptxfsiz; + /**Non Periodic Transmit FIFO/Queue Status Register (Read + * Only). Offset: 02Ch */ + volatile uint32_t gnptxsts; + /**I2C Access Register. Offset: 030h */ + volatile uint32_t gi2cctl; + /**PHY Vendor Control Register. Offset: 034h */ + volatile uint32_t gpvndctl; + /**General Purpose Input/Output Register. Offset: 038h */ + volatile uint32_t ggpio; + /**User ID Register. Offset: 03Ch */ + volatile uint32_t guid; + /**Synopsys ID Register (Read Only). Offset: 040h */ + volatile uint32_t gsnpsid; + /**User HW Config1 Register (Read Only). Offset: 044h */ + volatile uint32_t ghwcfg1; + /**User HW Config2 Register (Read Only). Offset: 048h */ + volatile uint32_t ghwcfg2; +#define DWC_SLAVE_ONLY_ARCH 0 +#define DWC_EXT_DMA_ARCH 1 +#define DWC_INT_DMA_ARCH 2 + +#define DWC_MODE_HNP_SRP_CAPABLE 0 +#define DWC_MODE_SRP_ONLY_CAPABLE 1 +#define DWC_MODE_NO_HNP_SRP_CAPABLE 2 +#define DWC_MODE_SRP_CAPABLE_DEVICE 3 +#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4 +#define DWC_MODE_SRP_CAPABLE_HOST 5 +#define DWC_MODE_NO_SRP_CAPABLE_HOST 6 + + /**User HW Config3 Register (Read Only). Offset: 04Ch */ + volatile uint32_t ghwcfg3; + /**User HW Config4 Register (Read Only). Offset: 050h*/ + volatile uint32_t ghwcfg4; + /** Reserved Offset: 054h-0FFh */ + uint32_t reserved[43]; + /** Host Periodic Transmit FIFO Size Register. Offset: 100h */ + volatile uint32_t hptxfsiz; + /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, + otherwise Device Transmit FIFO#n Register. + * Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15). */ + //volatile uint32_t dptxfsiz[15]; + volatile uint32_t dptxfsiz_dieptxf[15]; +} dwc_otg_core_global_regs_t; + +/** + * This union represents the bit fields of the Core OTG Control + * and Status Register (GOTGCTL). Set the bits using the bit + * fields then write the d32 value to the register. + */ +typedef union gotgctl_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned reserved31_21 : 11; + unsigned currmod : 1; + unsigned bsesvld : 1; + unsigned asesvld : 1; + unsigned reserved17 : 1; + unsigned conidsts : 1; + unsigned reserved15_12 : 4; + unsigned devhnpen : 1; + unsigned hstsethnpen : 1; + unsigned hnpreq : 1; + unsigned hstnegscs : 1; + unsigned reserved7_2 : 6; + unsigned sesreq : 1; + unsigned sesreqscs : 1; + } b; +} gotgctl_data_t; + +/** + * This union represents the bit fields of the Core OTG Interrupt Register + * (GOTGINT). Set/clear the bits using the bit fields then write the d32 + * value to the register. + */ +typedef union gotgint_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** Current Mode */ + unsigned reserved31_20 : 12; + /** Debounce Done */ + unsigned debdone : 1; + /** A-Device Timeout Change */ + unsigned adevtoutchng : 1; + /** Host Negotiation Detected */ + unsigned hstnegdet : 1; + unsigned reserver16_10 : 7; + /** Host Negotiation Success Status Change */ + unsigned hstnegsucstschng : 1; + /** Session Request Success Status Change */ + unsigned sesreqsucstschng : 1; + unsigned reserved3_7 : 5; + /** Session End Detected */ + unsigned sesenddet : 1; + /** Current Mode */ + unsigned reserved1_0 : 2; + } b; +} gotgint_data_t; + + +/** + * This union represents the bit fields of the Core AHB Configuration + * Register (GAHBCFG). Set/clear the bits using the bit fields then + * write the d32 value to the register. + */ +typedef union gahbcfg_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { +#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1 +#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 + unsigned reserved9_31 : 23; + unsigned ptxfemplvl : 1; + unsigned nptxfemplvl_txfemplvl : 1; +#define DWC_GAHBCFG_DMAENABLE 1 + unsigned reserved : 1; + unsigned dmaenable : 1; +#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5 +#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7 + unsigned hburstlen : 4; + unsigned glblintrmsk : 1; +#define DWC_GAHBCFG_GLBINT_ENABLE 1 + + } b; +} gahbcfg_data_t; + +/** + * This union represents the bit fields of the Core USB Configuration + * Register (GUSBCFG). Set the bits using the bit fields then write + * the d32 value to the register. + */ +typedef union gusbcfg_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned corrupt_tx_packet: 1; /*fscz*/ + unsigned force_device_mode: 1; + unsigned force_host_mode: 1; + unsigned reserved23_28 : 6; + unsigned term_sel_dl_pulse : 1; + unsigned ulpi_int_vbus_indicator : 1; + unsigned ulpi_ext_vbus_drv : 1; + unsigned ulpi_clk_sus_m : 1; + unsigned ulpi_auto_res : 1; + unsigned ulpi_fsls : 1; + unsigned otgutmifssel : 1; + unsigned phylpwrclksel : 1; + unsigned nptxfrwnden : 1; + unsigned usbtrdtim : 4; + unsigned hnpcap : 1; + unsigned srpcap : 1; + unsigned ddrsel : 1; + unsigned physel : 1; + unsigned fsintf : 1; + unsigned ulpi_utmi_sel : 1; + unsigned phyif : 1; + unsigned toutcal : 3; + } b; +} gusbcfg_data_t; + +/** + * This union represents the bit fields of the Core Reset Register + * (GRSTCTL). Set/clear the bits using the bit fields then write the + * d32 value to the register. + */ +typedef union grstctl_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + /** AHB Master Idle. Indicates the AHB Master State + * Machine is in IDLE condition. */ + unsigned ahbidle : 1; + /** DMA Request Signal. Indicated DMA request is in + * probress. Used for debug purpose. */ + unsigned dmareq : 1; + /** Reserved */ + unsigned reserved29_11 : 19; + /** TxFIFO Number (TxFNum) (Device and Host). + * + * This is the FIFO number which needs to be flushed, + * using the TxFIFO Flush bit. This field should not + * be changed until the TxFIFO Flush bit is cleared by + * the core. + * - 0x0 : Non Periodic TxFIFO Flush + * - 0x1 : Periodic TxFIFO #1 Flush in device mode + * or Periodic TxFIFO in host mode + * - 0x2 : Periodic TxFIFO #2 Flush in device mode. + * - ... + * - 0xF : Periodic TxFIFO #15 Flush in device mode + * - 0x10: Flush all the Transmit NonPeriodic and + * Transmit Periodic FIFOs in the core + */ + unsigned txfnum : 5; + /** TxFIFO Flush (TxFFlsh) (Device and Host). + * + * This bit is used to selectively flush a single or + * all transmit FIFOs. The application must first + * ensure that the core is not in the middle of a + * transaction.

The application should write into + * this bit, only after making sure that neither the + * DMA engine is writing into the TxFIFO nor the MAC + * is reading the data out of the FIFO.

The + * application should wait until the core clears this + * bit, before performing any operations. This bit + * will takes 8 clocks (slowest of PHY or AHB clock) + * to clear. + */ + unsigned txfflsh : 1; + /** RxFIFO Flush (RxFFlsh) (Device and Host) + * + * The application can flush the entire Receive FIFO + * using this bit.

The application must first + * ensure that the core is not in the middle of a + * transaction.

The application should write into + * this bit, only after making sure that neither the + * DMA engine is reading from the RxFIFO nor the MAC + * is writing the data in to the FIFO.

The + * application should wait until the bit is cleared + * before performing any other operations. This bit + * will takes 8 clocks (slowest of PHY or AHB clock) + * to clear. + */ + unsigned rxfflsh : 1; + /** In Token Sequence Learning Queue Flush + * (INTknQFlsh) (Device Only) + */ + unsigned intknqflsh : 1; + /** Host Frame Counter Reset (Host Only)
+ * + * The application can reset the (micro)frame number + * counter inside the core, using this bit. When the + * (micro)frame counter is reset, the subsequent SOF + * sent out by the core, will have a (micro)frame + * number of 0. + */ + unsigned hstfrm : 1; + /** Hclk Soft Reset + * + * The application uses this bit to reset the control logic in + * the AHB clock domain. Only AHB clock domain pipelines are + * reset. + */ + unsigned hsftrst : 1; + /** Core Soft Reset (CSftRst) (Device and Host) + * + * The application can flush the control logic in the + * entire core using this bit. This bit resets the + * pipelines in the AHB Clock domain as well as the + * PHY Clock domain. + * + * The state machines are reset to an IDLE state, the + * control bits in the CSRs are cleared, all the + * transmit FIFOs and the receive FIFO are flushed. + * + * The status mask bits that control the generation of + * the interrupt, are cleared, to clear the + * interrupt. The interrupt status bits are not + * cleared, so the application can get the status of + * any events that occurred in the core after it has + * set this bit. + * + * Any transactions on the AHB are terminated as soon + * as possible following the protocol. Any + * transactions on the USB are terminated immediately. + * + * The configuration settings in the CSRs are + * unchanged, so the software doesn't have to + * reprogram these registers (Device + * Configuration/Host Configuration/Core System + * Configuration/Core PHY Configuration). + * + * The application can write to this bit, any time it + * wants to reset the core. This is a self clearing + * bit and the core clears this bit after all the + * necessary logic is reset in the core, which may + * take several clocks, depending on the current state + * of the core. + */ + unsigned csftrst : 1; + } b; +} grstctl_t; + + +/** + * This union represents the bit fields of the Core Interrupt Mask + * Register (GINTMSK). Set/clear the bits using the bit fields then + * write the d32 value to the register. + */ +typedef union gintmsk_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct + { + unsigned wkupintr : 1; + unsigned sessreqintr : 1; + unsigned disconnect : 1; + unsigned conidstschng : 1; + unsigned reserved27 : 1; + unsigned ptxfempty : 1; + unsigned hcintr : 1; + unsigned portintr : 1; + unsigned reserved22_23 : 2; + unsigned incomplisoout : 1; + unsigned incomplisoin : 1; + unsigned outepintr : 1; + unsigned inepintr : 1; + unsigned epmismatch : 1; + unsigned reserved16 : 1; + unsigned eopframe : 1; + unsigned isooutdrop : 1; + unsigned enumdone : 1; + unsigned usbreset : 1; + unsigned usbsuspend : 1; + unsigned erlysuspend : 1; + unsigned i2cintr : 1; + unsigned reserved8 : 1; + unsigned goutnakeff : 1; + unsigned ginnakeff : 1; + unsigned nptxfempty : 1; + unsigned rxstsqlvl : 1; + unsigned sofintr : 1; + unsigned otgintr : 1; + unsigned modemismatch : 1; + unsigned reserved0 : 1; + } b; +} gintmsk_data_t; +/** + * This union represents the bit fields of the Core Interrupt Register + * (GINTSTS). Set/clear the bits using the bit fields then write the + * d32 value to the register. + */ +typedef union gintsts_data +{ + /** raw register data */ + uint32_t d32; +#define DWC_SOF_INTR_MASK 0x0008 + /** register bits */ + struct + { +#define DWC_HOST_MODE 1 + unsigned wkupintr : 1; + unsigned sessreqintr : 1; + unsigned disconnect : 1; + unsigned conidstschng : 1; + unsigned reserved27 : 1; + unsigned ptxfempty : 1; + unsigned hcintr : 1; + unsigned portintr : 1; + unsigned reserved22_23 : 2; + unsigned incomplisoout : 1; + unsigned incomplisoin : 1; + unsigned outepintr : 1; + unsigned inepint: 1; + unsigned epmismatch : 1; + unsigned intokenrx : 1; + unsigned eopframe : 1; + unsigned isooutdrop : 1; + unsigned enumdone : 1; + unsigned usbreset : 1; + unsigned usbsuspend : 1; + unsigned erlysuspend : 1; + unsigned i2cintr : 1; + unsigned reserved8 : 1; + unsigned goutnakeff : 1; + unsigned ginnakeff : 1; + unsigned nptxfempty : 1; + unsigned rxstsqlvl : 1; + unsigned sofintr : 1; + unsigned otgintr : 1; + unsigned modemismatch : 1; + unsigned curmode : 1; + } b; +} gintsts_data_t; + + +/** + * This union represents the bit fields in the Device Receive Status Read and + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 + * element then read out the bits using the bit elements. + */ +typedef union device_grxsts_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved : 7; + unsigned fn : 4; +#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet +#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete + +#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK +#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete +#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet + unsigned pktsts : 4; + unsigned dpid : 2; + unsigned bcnt : 11; + unsigned epnum : 4; + } b; +} device_grxsts_data_t; + +/** + * This union represents the bit fields in the Host Receive Status Read and + * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 + * element then read out the bits using the bit elements. + */ +typedef union host_grxsts_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved31_21 : 11; +#define DWC_GRXSTS_PKTSTS_IN 0x2 +#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3 +#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5 +#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7 + unsigned pktsts : 4; + unsigned dpid : 2; + unsigned bcnt : 11; + unsigned chnum : 4; + } b; +} host_grxsts_data_t; + +/** + * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, + * GNPTXFSIZ, DPTXFSIZn). Read the register into the d32 element then + * read out the bits using the bit elements. + */ +typedef union fifosize_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned depth : 16; + unsigned startaddr : 16; + } b; +} fifosize_data_t; + +/** + * This union represents the bit fields in the Non-Periodic Transmit + * FIFO/Queue Status Register (GNPTXSTS). Read the register into the + * d32 element then read out the bits using the bit + * elements. + */ +typedef union gnptxsts_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved : 1; + /** Top of the Non-Periodic Transmit Request Queue + * - bits 30:27 - Channel/EP Number + * - bits 26:25 - Token Type + * - bit 24 - Terminate (Last entry for the selected + * channel/EP) + * - 2'b00 - IN/OUT + * - 2'b01 - Zero Length OUT + * - 2'b10 - PING/Complete Split + * - 2'b11 - Channel Halt + + */ + unsigned nptxqtop_chnep : 4; + unsigned nptxqtop_token : 2; + unsigned nptxqtop_terminate : 1; + unsigned nptxqspcavail : 8; + unsigned nptxfspcavail : 16; + } b; +} gnptxsts_data_t; + +/** + * This union represents the bit fields in the Transmit + * FIFO Status Register (DTXFSTS). Read the register into the + * d32 element then read out the bits using the bit + * elements. + */ +typedef union dtxfsts_data /* fscz */ //* +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved : 16; + unsigned txfspcavail : 16; + } b; +} dtxfsts_data_t; + +/** + * This union represents the bit fields in the I2C Control Register + * (I2CCTL). Read the register into the d32 element then read out the + * bits using the bit elements. + */ +typedef union gi2cctl_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned bsydne : 1; + unsigned rw : 1; + unsigned reserved : 2; + unsigned i2cdevaddr : 2; + unsigned i2csuspctl : 1; + unsigned ack : 1; + unsigned i2cen : 1; + unsigned addr : 7; + unsigned regaddr : 8; + unsigned rwdata : 8; + } b; +} gi2cctl_data_t; + +/** + * This union represents the bit fields in the User HW Config1 + * Register. Read the register into the d32 element then read + * out the bits using the bit elements. + */ +typedef union hwcfg1_data { + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned ep_dir15 : 2; + unsigned ep_dir14 : 2; + unsigned ep_dir13 : 2; + unsigned ep_dir12 : 2; + unsigned ep_dir11 : 2; + unsigned ep_dir10 : 2; + unsigned ep_dir9 : 2; + unsigned ep_dir8 : 2; + unsigned ep_dir7 : 2; + unsigned ep_dir6 : 2; + unsigned ep_dir5 : 2; + unsigned ep_dir4 : 2; + unsigned ep_dir3 : 2; + unsigned ep_dir2 : 2; + unsigned ep_dir1 : 2; + unsigned ep_dir0 : 2; + } b; +} hwcfg1_data_t; + +/** + * This union represents the bit fields in the User HW Config2 + * Register. Read the register into the d32 element then read + * out the bits using the bit elements. + */ +typedef union hwcfg2_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /* GHWCFG2 */ + unsigned reserved31 : 1; + unsigned dev_token_q_depth : 5; + unsigned host_perio_tx_q_depth : 2; + unsigned nonperio_tx_q_depth : 2; + unsigned rx_status_q_depth : 2; + unsigned dynamic_fifo : 1; + unsigned perio_ep_supported : 1; + unsigned num_host_chan : 4; + unsigned num_dev_ep : 4; + unsigned fs_phy_type : 2; +#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1 +#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2 +#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 + unsigned hs_phy_type : 2; + unsigned point2point : 1; + unsigned architecture : 2; +#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0 +#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1 +#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 +#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 +#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 + unsigned op_mode : 3; + } b; +} hwcfg2_data_t; + +/** + * This union represents the bit fields in the User HW Config3 + * Register. Read the register into the d32 element then read + * out the bits using the bit elements. + */ +typedef union hwcfg3_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /* GHWCFG3 */ + unsigned dfifo_depth : 16; + unsigned reserved15_13 : 3; + unsigned ahb_phy_clock_synch : 1; + unsigned synch_reset_type : 1; + unsigned optional_features : 1; + unsigned vendor_ctrl_if : 1; + unsigned i2c : 1; + unsigned otg_func : 1; + unsigned packet_size_cntr_width : 3; + unsigned xfer_size_cntr_width : 4; + } b; +} hwcfg3_data_t; + +/** + * This union represents the bit fields in the User HW Config4 + * Register. Read the register into the d32 element then read + * out the bits using the bit elements. + */ +typedef union hwcfg4_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { +unsigned reserved31_30 : 2; /* fscz */ + unsigned num_in_eps : 4; + unsigned ded_fifo_en : 1; + + unsigned session_end_filt_en : 1; + unsigned b_valid_filt_en : 1; + unsigned a_valid_filt_en : 1; + unsigned vbus_valid_filt_en : 1; + unsigned iddig_filt_en : 1; + unsigned num_dev_mode_ctrl_ep : 4; + unsigned utmi_phy_data_width : 2; + unsigned min_ahb_freq : 9; + unsigned power_optimiz : 1; + unsigned num_dev_perio_in_ep : 4; + } b; +} hwcfg4_data_t; + +//////////////////////////////////////////// +// Device Registers +/** + * Device Global Registers. Offsets 800h-BFFh + * + * The following structures define the size and relative field offsets + * for the Device Mode Registers. + * + * These registers are visible only in Device mode and must not be + * accessed in Host mode, as the results are unknown. + */ +typedef struct dwc_otg_dev_global_regs +{ + /** Device Configuration Register. Offset 800h */ + volatile uint32_t dcfg; + /** Device Control Register. Offset: 804h */ + volatile uint32_t dctl; + /** Device Status Register (Read Only). Offset: 808h */ + volatile uint32_t dsts; + /** Reserved. Offset: 80Ch */ + uint32_t unused; + /** Device IN Endpoint Common Interrupt Mask + * Register. Offset: 810h */ + volatile uint32_t diepmsk; + /** Device OUT Endpoint Common Interrupt Mask + * Register. Offset: 814h */ + volatile uint32_t doepmsk; + /** Device All Endpoints Interrupt Register. Offset: 818h */ + volatile uint32_t daint; + /** Device All Endpoints Interrupt Mask Register. Offset: + * 81Ch */ + volatile uint32_t daintmsk; + /** Device IN Token Queue Read Register-1 (Read Only). + * Offset: 820h */ + volatile uint32_t dtknqr1; + /** Device IN Token Queue Read Register-2 (Read Only). + * Offset: 824h */ + volatile uint32_t dtknqr2; + /** Device VBUS discharge Register. Offset: 828h */ + volatile uint32_t dvbusdis; + /** Device VBUS Pulse Register. Offset: 82Ch */ + volatile uint32_t dvbuspulse; + /** Device IN Token Queue Read Register-3 (Read Only). + * Device Thresholding control register (Read/Write) + * Offset: 830h */ + volatile uint32_t dtknqr3_dthrctl; + /** Device IN Token Queue Read Register-4 (Read Only). / + * Device IN EPs empty Inr. Mask Register (Read/Write) + * Offset: 834h */ + volatile uint32_t dtknqr4_fifoemptymsk; +} dwc_otg_device_global_regs_t; + +/** + * This union represents the bit fields in the Device Configuration + * Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. Write the + * d32 member to the dcfg register. + */ +typedef union dcfg_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved31_23 : 9; + /** In Endpoint Mis-match count */ + unsigned epmscnt : 5; + unsigned reserved13_17 : 5; + /** Periodic Frame Interval */ +#define DWC_DCFG_FRAME_INTERVAL_80 0 +#define DWC_DCFG_FRAME_INTERVAL_85 1 +#define DWC_DCFG_FRAME_INTERVAL_90 2 +#define DWC_DCFG_FRAME_INTERVAL_95 3 + unsigned perfrint : 2; + /** Device Addresses */ + unsigned devaddr : 7; + unsigned reserved3 : 1; + /** Non Zero Length Status OUT Handshake */ +#define DWC_DCFG_SEND_STALL 1 + unsigned nzstsouthshk : 1; + /** Device Speed */ + unsigned devspd : 2; + } b; +} dcfg_data_t; + +/** + * This union represents the bit fields in the Device Control + * Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union dctl_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved : 20; + /** Power-On Programming Done */ + unsigned pwronprgdone : 1; + /** Clear Global OUT NAK */ + unsigned cgoutnak : 1; + /** Set Global OUT NAK */ + unsigned sgoutnak : 1; + /** Clear Global Non-Periodic IN NAK */ + unsigned cgnpinnak : 1; + /** Set Global Non-Periodic IN NAK */ + unsigned sgnpinnak : 1; + /** Test Control */ + unsigned tstctl : 3; + /** Global OUT NAK Status */ + unsigned goutnaksts : 1; + /** Global Non-Periodic IN NAK Status */ + unsigned gnpinnaksts : 1; + /** Soft Disconnect */ + unsigned sftdiscon : 1; + /** Remote Wakeup */ + unsigned rmtwkupsig : 1; + } b; +} dctl_data_t; + +/** + * This union represents the bit fields in the Device Status + * Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union dsts_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved22_31 : 10; + /** Frame or Microframe Number of the received SOF */ + unsigned soffn : 14; + unsigned reserved4_7: 4; + /** Erratic Error */ + unsigned errticerr : 1; + /** Enumerated Speed */ +#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 +#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 +#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2 +#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3 + unsigned enumspd : 2; + /** Suspend Status */ + unsigned suspsts : 1; + } b; +} dsts_data_t; + + +/** + * This union represents the bit fields in the Device IN EP Interrupt + * Register and the Device IN EP Common Mask Register. + * + * - Read the register into the d32 member then set/clear the + * bits using the bit elements. + */ +typedef union diepint_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved07_31 : 23; + unsigned txfifoundrn : 1; + /** IN Endpoint HAK Effective mask */ + unsigned emptyintr : 1; + /** IN Endpoint NAK Effective mask */ + unsigned inepnakeff : 1; + /** IN Token Received with EP mismatch mask */ + unsigned intknepmis : 1; + /** IN Token received with TxF Empty mask */ + unsigned intktxfemp : 1; + /** TimeOUT Handshake mask (non-ISOC EPs) */ + unsigned timeout : 1; + /** AHB Error mask */ + unsigned ahberr : 1; + /** Endpoint disable mask */ + unsigned epdisabled : 1; + /** Transfer complete mask */ + unsigned xfercompl : 1; + } b; +} diepint_data_t; +/** + * This union represents the bit fields in the Device IN EP Common + * Interrupt Mask Register. + */ +typedef union diepint_data diepmsk_data_t; + +/** + * This union represents the bit fields in the Device OUT EP Interrupt + * Registerand Device OUT EP Common Interrupt Mask Register. + * + * - Read the register into the d32 member then set/clear the + * bits using the bit elements. + */ +typedef union doepint_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved04_31 : 27; + /** OUT Token Received when Endpoint Disabled */ + unsigned outtknepdis : 1; + /** Setup Phase Done (contorl EPs) */ + unsigned setup : 1; + /** AHB Error */ + unsigned ahberr : 1; + /** Endpoint disable */ + unsigned epdisabled : 1; + /** Transfer complete */ + unsigned xfercompl : 1; + } b; +} doepint_data_t; +/** + * This union represents the bit fields in the Device OUT EP Common + * Interrupt Mask Register. + */ +typedef union doepint_data doepmsk_data_t; + + +/** + * This union represents the bit fields in the Device All EP Interrupt + * and Mask Registers. + * - Read the register into the d32 member then set/clear the + * bits using the bit elements. + */ +typedef union daint_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** OUT Endpoint bits */ + unsigned out : 16; + /** IN Endpoint bits */ + unsigned in : 16; + } ep; + struct { + /** OUT Endpoint bits */ + unsigned outep15 : 1; + unsigned outep14 : 1; + unsigned outep13 : 1; + unsigned outep12 : 1; + unsigned outep11 : 1; + unsigned outep10 : 1; + unsigned outep9 : 1; + unsigned outep8 : 1; + unsigned outep7 : 1; + unsigned outep6 : 1; + unsigned outep5 : 1; + unsigned outep4 : 1; + unsigned outep3 : 1; + unsigned outep2 : 1; + unsigned outep1 : 1; + unsigned outep0 : 1; + /** IN Endpoint bits */ + unsigned inep15 : 1; + unsigned inep14 : 1; + unsigned inep13 : 1; + unsigned inep12 : 1; + unsigned inep11 : 1; + unsigned inep10 : 1; + unsigned inep9 : 1; + unsigned inep8 : 1; + unsigned inep7 : 1; + unsigned inep6 : 1; + unsigned inep5 : 1; + unsigned inep4 : 1; + unsigned inep3 : 1; + unsigned inep2 : 1; + unsigned inep1 : 1; + unsigned inep0 : 1; + } b; +} daint_data_t; + +/** + * This union represents the bit fields in the Device IN Token Queue + * Read Registers. + * - Read the register into the d32 member. + * - READ-ONLY Register + */ +typedef union dtknq1_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** EP Numbers of IN Tokens 0 ... 4 */ + unsigned epnums0_5 : 24; + /** write pointer has wrapped. */ + unsigned wrap_bit : 1; + /** Reserved */ + unsigned reserved05_06 : 2; + /** In Token Queue Write Pointer */ + unsigned intknwptr : 5; + }b; +} dtknq1_data_t; + +/** + * This union represents Threshold control Register + * - Read and write the register into the d32 member. + * - READ-WRITABLE Register + */ +typedef union dthrctl_data //* /*fscz */ +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Reserved */ + unsigned reserved26_31 : 6; + /** Rx Thr. Length */ + unsigned rx_thr_len : 9; + /** Rx Thr. Enable */ + unsigned rx_thr_en : 1; + /** Reserved */ + unsigned reserved11_15 : 5; + /** Tx Thr. Length */ + unsigned tx_thr_len : 9; + /** ISO Tx Thr. Enable */ + unsigned iso_thr_en : 1; + /** non ISO Tx Thr. Enable */ + unsigned non_iso_thr_en : 1; + + }b; +} dthrctl_data_t; + +/** + * Device Logical IN Endpoint-Specific Registers. Offsets + * 900h-AFCh + * + * There will be one set of endpoint registers per logical endpoint + * implemented. + * + * These registers are visible only in Device mode and must not be + * accessed in Host mode, as the results are unknown. + */ +typedef struct dwc_otg_dev_in_ep_regs +{ + /** Device IN Endpoint Control Register. Offset:900h + + * (ep_num * 20h) + 00h */ + volatile uint32_t diepctl; + /** Reserved. Offset:900h + (ep_num * 20h) + 04h */ + uint32_t reserved04; + /** Device IN Endpoint Interrupt Register. Offset:900h + + * (ep_num * 20h) + 08h */ + volatile uint32_t diepint; + /** Reserved. Offset:900h + (ep_num * 20h) + 0Ch */ + uint32_t reserved0C; + /** Device IN Endpoint Transfer Size + * Register. Offset:900h + (ep_num * 20h) + 10h */ + volatile uint32_t dieptsiz; + /** Device IN Endpoint DMA Address Register. Offset:900h + + * (ep_num * 20h) + 14h */ + volatile uint32_t diepdma; + /** Reserved. Offset:900h + (ep_num * 20h) + 18h - 900h + + * (ep_num * 20h) + 1Ch*/ + volatile uint32_t dtxfsts; + /** Reserved. Offset:900h + (ep_num * 20h) + 1Ch - 900h + + * (ep_num * 20h) + 1Ch*/ + uint32_t reserved18; +} dwc_otg_dev_in_ep_regs_t; + +/** + * Device Logical OUT Endpoint-Specific Registers. Offsets: + * B00h-CFCh + * + * There will be one set of endpoint registers per logical endpoint + * implemented. + * + * These registers are visible only in Device mode and must not be + * accessed in Host mode, as the results are unknown. + */ +typedef struct dwc_otg_dev_out_ep_regs +{ + /** Device OUT Endpoint Control Register. Offset:B00h + + * (ep_num * 20h) + 00h */ + volatile uint32_t doepctl; + /** Device OUT Endpoint Frame number Register. Offset: + * B00h + (ep_num * 20h) + 04h */ + volatile uint32_t doepfn; + /** Device OUT Endpoint Interrupt Register. Offset:B00h + + * (ep_num * 20h) + 08h */ + volatile uint32_t doepint; + /** Reserved. Offset:B00h + (ep_num * 20h) + 0Ch */ + uint32_t reserved0C; + /** Device OUT Endpoint Transfer Size Register. Offset: + * B00h + (ep_num * 20h) + 10h */ + volatile uint32_t doeptsiz; + /** Device OUT Endpoint DMA Address Register. Offset:B00h + * + (ep_num * 20h) + 14h */ + volatile uint32_t doepdma; + /** Reserved. Offset:B00h + (ep_num * 20h) + 18h - B00h + + * (ep_num * 20h) + 1Ch */ + uint32_t unused[2]; +} dwc_otg_dev_out_ep_regs_t; + +/** + * This union represents the bit fields in the Device EP Control + * Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union depctl_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Endpoint Enable */ + unsigned epena : 1; + /** Endpoint Disable */ + unsigned epdis : 1; + /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) + * Writing to this field sets the Endpoint DPID (DPID) + * field in this register to DATA1 Set Odd + * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) + * Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to odd (micro) frame. + */ + unsigned setd1pid : 1; + /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) + * Writing to this field sets the Endpoint DPID (DPID) + * field in this register to DATA0. Set Even + * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) + * Writing to this field sets the Even/Odd + * (micro)frame (EO_FrNum) field to even (micro) + * frame. + */ + unsigned setd0pid : 1; + /** Set NAK */ + unsigned snak : 1; + /** Clear NAK */ + unsigned cnak : 1; + /** Tx Fifo Number + * IN EPn/IN EP0 + * OUT EPn/OUT EP0 - reserved */ + unsigned txfnum : 4; + /** Stall Handshake */ + unsigned stall : 1; + /** Snoop Mode + * OUT EPn/OUT EP0 + * IN EPn/IN EP0 - reserved */ + unsigned snp : 1; + /** Endpoint Type + * 2'b00: Control + * 2'b01: Isochronous + * 2'b10: Bulk + * 2'b11: Interrupt */ + unsigned eptype : 2; + /** NAK Status */ + unsigned naksts : 1; + /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) + * This field contains the PID of the packet going to + * be received or transmitted on this endpoint. The + * application should program the PID of the first + * packet going to be received or transmitted on this + * endpoint , after the endpoint is + * activated. Application use the SetD1PID and + * SetD0PID fields of this register to program either + * D0 or D1 PID. + * + * The encoding for this field is + * - 0: D0 + * - 1: D1 + */ + unsigned dpid : 1; + /** USB Active Endpoint */ + unsigned usbactep : 1; + /** Next Endpoint + * IN EPn/IN EP0 + * OUT EPn/OUT EP0 - reserved */ + unsigned nextep : 4; + /** Maximum Packet Size + * IN/OUT EPn + * IN/OUT EP0 - 2 bits + * 2'b00: 64 Bytes + * 2'b01: 32 + * 2'b10: 16 + * 2'b11: 8 */ +#define DWC_DEP0CTL_MPS_64 0 +#define DWC_DEP0CTL_MPS_32 1 +#define DWC_DEP0CTL_MPS_16 2 +#define DWC_DEP0CTL_MPS_8 3 + unsigned mps : 11; + } b; +} depctl_data_t; + +/** + * This union represents the bit fields in the Device EP Transfer + * Size Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union deptsiz_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved : 1; + /** Multi Count - Periodic IN endpoints */ + unsigned mc : 2; + /** Packet Count */ + unsigned pktcnt : 10; + /** Transfer size */ + unsigned xfersize : 19; + } b; +} deptsiz_data_t; + +/** + * This union represents the bit fields in the Device EP 0 Transfer + * Size Register. Read the register into the d32 member then + * set/clear the bits using the bit elements. + */ +typedef union deptsiz0_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved31 : 1; + /**Setup Packet Count (DOEPTSIZ0 Only) */ + unsigned supcnt : 2; + /** Reserved */ + unsigned reserved28_20 : 9; + /** Packet Count */ + unsigned pktcnt : 1; + /** Reserved */ + unsigned reserved18_7 : 12; + /** Transfer size */ + unsigned xfersize : 7; + } b; +} deptsiz0_data_t; + + +/** Maximum number of Periodic FIFOs */ +#define MAX_PERIO_FIFOS 15 +/** Maximum number of TX FIFOs */ +#define MAX_TX_FIFOS 15 +/** Maximum number of Endpoints/HostChannels */ +#define MAX_EPS_CHANNELS 16 +//#define MAX_EPS_CHANNELS 4 + +/** + * The dwc_otg_dev_if structure contains information needed to manage + * the DWC_otg controller acting in device mode. It represents the + * programming view of the device-specific aspects of the controller. + */ +typedef struct dwc_otg_dev_if { + /** Pointer to device Global registers. + * Device Global Registers starting at offset 800h + */ + dwc_otg_device_global_regs_t *dev_global_regs; +#define DWC_DEV_GLOBAL_REG_OFFSET 0x800 + + /** + * Device Logical IN Endpoint-Specific Registers 900h-AFCh + */ + dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; +#define DWC_DEV_IN_EP_REG_OFFSET 0x900 +#define DWC_EP_REG_OFFSET 0x20 + + /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */ + dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS]; +#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00 + + /* Device configuration information*/ + uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */ + //uint8_t num_eps; /**< Number of EPs range: 0-16 (includes EP0) */ + //uint8_t num_perio_eps; /**< # of Periodic EP range: 0-15 */ + /*fscz */ + uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */ + uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/ + + /** Size of periodic FIFOs (Bytes) */ + uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS]; + + /** Size of Tx FIFOs (Bytes) */ + uint16_t tx_fifo_size[MAX_TX_FIFOS]; + + /** Thresholding enable flags and length varaiables **/ + uint16_t rx_thr_en; + uint16_t iso_tx_thr_en; + uint16_t non_iso_tx_thr_en; + + uint16_t rx_thr_length; + uint16_t tx_thr_length; +} dwc_otg_dev_if_t; + +/** + * This union represents the bit fields in the Power and Clock Gating Control + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. + */ +typedef union pcgcctl_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + unsigned reserved31_05 : 27; + /** PHY Suspended */ + unsigned physuspended : 1; + /** Reset Power Down Modules */ + unsigned rstpdwnmodule : 1; + /** Power Clamp */ + unsigned pwrclmp : 1; + /** Gate Hclk */ + unsigned gatehclk : 1; + /** Stop Pclk */ + unsigned stoppclk : 1; + } b; +} pcgcctl_data_t; + +///////////////////////////////////////////////// +// Host Mode Register Structures +// +/** + * The Host Global Registers structure defines the size and relative + * field offsets for the Host Mode Global Registers. Host Global + * Registers offsets 400h-7FFh. +*/ +typedef struct dwc_otg_host_global_regs +{ + /** Host Configuration Register. Offset: 400h */ + volatile uint32_t hcfg; + /** Host Frame Interval Register. Offset: 404h */ + volatile uint32_t hfir; + /** Host Frame Number / Frame Remaining Register. Offset: 408h */ + volatile uint32_t hfnum; + /** Reserved. Offset: 40Ch */ + uint32_t reserved40C; + /** Host Periodic Transmit FIFO/ Queue Status Register. Offset: 410h */ + volatile uint32_t hptxsts; + /** Host All Channels Interrupt Register. Offset: 414h */ + volatile uint32_t haint; + /** Host All Channels Interrupt Mask Register. Offset: 418h */ + volatile uint32_t haintmsk; +} dwc_otg_host_global_regs_t; + +/** + * This union represents the bit fields in the Host Configuration Register. + * Read the register into the d32 member then set/clear the bits using + * the bit elements. Write the d32 member to the hcfg register. + */ +typedef union hcfg_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + /** Reserved */ + //unsigned reserved31_03 : 29; + /** FS/LS Only Support */ + unsigned fslssupp : 1; + /** FS/LS Phy Clock Select */ +#define DWC_HCFG_30_60_MHZ 0 +#define DWC_HCFG_48_MHZ 1 +#define DWC_HCFG_6_MHZ 2 + unsigned fslspclksel : 2; + } b; +} hcfg_data_t; + +/** + * This union represents the bit fields in the Host Frame Remaing/Number + * Register. + */ +typedef union hfir_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + unsigned reserved : 16; + unsigned frint : 16; + } b; +} hfir_data_t; + +/** + * This union represents the bit fields in the Host Frame Remaing/Number + * Register. + */ +typedef union hfnum_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + unsigned frrem : 16; +#define DWC_HFNUM_MAX_FRNUM 0x3FFF + unsigned frnum : 16; + } b; +} hfnum_data_t; + +typedef union hptxsts_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + /** Top of the Periodic Transmit Request Queue + * - bit 24 - Terminate (last entry for the selected channel) + * - bits 26:25 - Token Type + * - 2'b00 - Zero length + * - 2'b01 - Ping + * - 2'b10 - Disable + * - bits 30:27 - Channel Number + * - bit 31 - Odd/even microframe + */ + unsigned ptxqtop_odd : 1; + unsigned ptxqtop_chnum : 4; + unsigned ptxqtop_token : 2; + unsigned ptxqtop_terminate : 1; + unsigned ptxqspcavail : 8; + unsigned ptxfspcavail : 16; + } b; +} hptxsts_data_t; + +/** + * This union represents the bit fields in the Host Port Control and Status + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. Write the d32 member to the + * hprt0 register. + */ +typedef union hprt0_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved19_31 : 13; +#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0 +#define DWC_HPRT0_PRTSPD_FULL_SPEED 1 +#define DWC_HPRT0_PRTSPD_LOW_SPEED 2 + unsigned prtspd : 2; + unsigned prttstctl : 4; + unsigned prtpwr : 1; + unsigned prtlnsts : 2; + unsigned reserved9 : 1; + unsigned prtrst : 1; + unsigned prtsusp : 1; + unsigned prtres : 1; + unsigned prtovrcurrchng : 1; + unsigned prtovrcurract : 1; + unsigned prtenchng : 1; + unsigned prtena : 1; + unsigned prtconndet : 1; + unsigned prtconnsts : 1; + } b; +} hprt0_data_t; + +/** + * This union represents the bit fields in the Host All Interrupt + * Register. + */ +typedef union haint_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved : 16; + unsigned ch15 : 1; + unsigned ch14 : 1; + unsigned ch13 : 1; + unsigned ch12 : 1; + unsigned ch11 : 1; + unsigned ch10 : 1; + unsigned ch9 : 1; + unsigned ch8 : 1; + unsigned ch7 : 1; + unsigned ch6 : 1; + unsigned ch5 : 1; + unsigned ch4 : 1; + unsigned ch3 : 1; + unsigned ch2 : 1; + unsigned ch1 : 1; + unsigned ch0 : 1; + } b; + struct { + unsigned reserved : 16; + unsigned chint : 16; + } b2; +} haint_data_t; + +/** + * This union represents the bit fields in the Host All Interrupt + * Register. + */ +typedef union haintmsk_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + unsigned reserved : 16; + unsigned ch15 : 1; + unsigned ch14 : 1; + unsigned ch13 : 1; + unsigned ch12 : 1; + unsigned ch11 : 1; + unsigned ch10 : 1; + unsigned ch9 : 1; + unsigned ch8 : 1; + unsigned ch7 : 1; + unsigned ch6 : 1; + unsigned ch5 : 1; + unsigned ch4 : 1; + unsigned ch3 : 1; + unsigned ch2 : 1; + unsigned ch1 : 1; + unsigned ch0 : 1; + } b; + struct { + unsigned reserved : 16; + unsigned chint : 16; + } b2; +} haintmsk_data_t; + +/** + * Host Channel Specific Registers. 500h-5FCh + */ +typedef struct dwc_otg_hc_regs +{ + /** Host Channel 0 Characteristic Register. Offset: 500h + (chan_num * 20h) + 00h */ + volatile uint32_t hcchar; + /** Host Channel 0 Split Control Register. Offset: 500h + (chan_num * 20h) + 04h */ + volatile uint32_t hcsplt; + /** Host Channel 0 Interrupt Register. Offset: 500h + (chan_num * 20h) + 08h */ + volatile uint32_t hcint; + /** Host Channel 0 Interrupt Mask Register. Offset: 500h + (chan_num * 20h) + 0Ch */ + volatile uint32_t hcintmsk; + /** Host Channel 0 Transfer Size Register. Offset: 500h + (chan_num * 20h) + 10h */ + volatile uint32_t hctsiz; + /** Host Channel 0 DMA Address Register. Offset: 500h + (chan_num * 20h) + 14h */ + volatile uint32_t hcdma; + /** Reserved. Offset: 500h + (chan_num * 20h) + 18h - 500h + (chan_num * 20h) + 1Ch */ + uint32_t reserved[2]; +} dwc_otg_hc_regs_t; + +/** + * This union represents the bit fields in the Host Channel Characteristics + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. Write the d32 member to the + * hcchar register. + */ +typedef union hcchar_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + /** Channel enable */ + unsigned chen : 1; + /** Channel disable */ + unsigned chdis : 1; + /** + * Frame to transmit periodic transaction. + * 0: even, 1: odd + */ + unsigned oddfrm : 1; + /** Device address */ + unsigned devaddr : 7; + /** Packets per frame for periodic transfers. 0 is reserved. */ + unsigned multicnt : 2; + /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */ + unsigned eptype : 2; + /** 0: Full/high speed device, 1: Low speed device */ + unsigned lspddev : 1; + unsigned reserved : 1; + /** 0: OUT, 1: IN */ + unsigned epdir : 1; + /** Endpoint number */ + unsigned epnum : 4; + /** Maximum packet size in bytes */ + unsigned mps : 11; + } b; +} hcchar_data_t; + +typedef union hcsplt_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + /** Split Enble */ + unsigned spltena : 1; + /** Reserved */ + unsigned reserved : 14; + /** Do Complete Split */ + unsigned compsplt : 1; + /** Transaction Position */ +#define DWC_HCSPLIT_XACTPOS_MID 0 +#define DWC_HCSPLIT_XACTPOS_END 1 +#define DWC_HCSPLIT_XACTPOS_BEGIN 2 +#define DWC_HCSPLIT_XACTPOS_ALL 3 + unsigned xactpos : 2; + /** Hub Address */ + unsigned hubaddr : 7; + /** Port Address */ + unsigned prtaddr : 7; + } b; +} hcsplt_data_t; + + +/** + * This union represents the bit fields in the Host All Interrupt + * Register. + */ +typedef union hcint_data +{ + /** raw register data */ + uint32_t d32; + /** register bits */ + struct { + /** Reserved */ + unsigned reserved : 21; + /** Data Toggle Error */ + unsigned datatglerr : 1; + /** Frame Overrun */ + unsigned frmovrun : 1; + /** Babble Error */ + unsigned bblerr : 1; + /** Transaction Err */ + unsigned xacterr : 1; + /** NYET Response Received */ + unsigned nyet : 1; + /** ACK Response Received */ + unsigned ack : 1; + /** NAK Response Received */ + unsigned nak : 1; + /** STALL Response Received */ + unsigned stall : 1; + /** AHB Error */ + unsigned ahberr : 1; + /** Channel Halted */ + unsigned chhltd : 1; + /** Transfer Complete */ + unsigned xfercomp : 1; + } b; +} hcint_data_t; + +/** + * This union represents the bit fields in the Host Channel Transfer Size + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. Write the d32 member to the + * hcchar register. + */ +typedef union hctsiz_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + /** Do PING protocol when 1 */ + unsigned dopng : 1; + /** + * Packet ID for next data packet + * 0: DATA0 + * 1: DATA2 + * 2: DATA1 + * 3: MDATA (non-Control), SETUP (Control) + */ +#define DWC_HCTSIZ_DATA0 0 +#define DWC_HCTSIZ_DATA1 2 +#define DWC_HCTSIZ_DATA2 1 +#define DWC_HCTSIZ_MDATA 3 +#define DWC_HCTSIZ_SETUP 3 + unsigned pid : 2; + /** Data packets to transfer */ + unsigned pktcnt : 10; + /** Total transfer size in bytes */ + unsigned xfersize : 19; + } b; +} hctsiz_data_t; + +/** + * This union represents the bit fields in the Host Channel Interrupt Mask + * Register. Read the register into the d32 member then set/clear the + * bits using the bit elements. Write the d32 member to the + * hcintmsk register. + */ +typedef union hcintmsk_data +{ + /** raw register data */ + uint32_t d32; + + /** register bits */ + struct { + unsigned reserved : 21; + unsigned datatglerr : 1; + unsigned frmovrun : 1; + unsigned bblerr : 1; + unsigned xacterr : 1; + unsigned nyet : 1; + unsigned ack : 1; + unsigned nak : 1; + unsigned stall : 1; + unsigned ahberr : 1; + unsigned chhltd : 1; + unsigned xfercompl : 1; + } b; +} hcintmsk_data_t; + +/** OTG Host Interface Structure. + * + * The OTG Host Interface Structure structure contains information + * needed to manage the DWC_otg controller acting in host mode. It + * represents the programming view of the host-specific aspects of the + * controller. + */ +typedef struct dwc_otg_host_if { + /** Host Global Registers starting at offset 400h.*/ + dwc_otg_host_global_regs_t *host_global_regs; +#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400 + + /** Host Port 0 Control and Status Register */ + volatile uint32_t *hprt0; +#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440 + + + /** Host Channel Specific Registers at offsets 500h-5FCh. */ + dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; +#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500 +#define DWC_OTG_CHAN_REGS_OFFSET 0x20 + + + /* Host configuration information */ + /** Number of Host Channels (range: 1-16) */ + uint8_t num_host_channels; + /** Periodic EPs supported (0: no, 1: yes) */ + uint8_t perio_eps_supported; + /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */ + uint16_t perio_tx_fifo_size; + +} dwc_otg_host_if_t; + +#endif diff --git a/target/linux/lantiq/files/drivers/usb/ifxhcd/Kconfig b/target/linux/lantiq/files/drivers/usb/ifxhcd/Kconfig new file mode 100644 index 0000000000..7eb8cebf42 --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/ifxhcd/Kconfig @@ -0,0 +1,58 @@ + +config USB_HOST_IFX + tristate "Infineon USB Host Controller Driver" + depends on USB + default n + help + Infineon USB Host Controller + +config USB_HOST_IFX_B + bool "USB host mode on core 1 and 2" + depends on USB_HOST_IFX + help + Both cores run as host + +#config USB_HOST_IFX_1 +#config USB_HOST_IFX_2 + +#config IFX_DANUBE +#config IFX_AMAZON_SE +config IFX_AR9 + depends on USB_HOST_IFX + bool "AR9" + +config IFX_VR9 + depends on USB_HOST_IFX + bool "VR9" + +#config USB_HOST_IFX_FORCE_USB11 +# bool "Forced USB1.1" +# depends on USB_HOST_IFX +# default n +# help +# force to be USB 1.1 + +#config USB_HOST_IFX_WITH_HS_ELECT_TST +# bool "With HS_Electrical Test" +# depends on USB_HOST_IFX +# default n +# help +# With USBIF HSET routines + +#config USB_HOST_IFX_WITH_ISO +# bool "With ISO transfer" +# depends on USB_HOST_IFX +# default n +# help +# With USBIF ISO transfer + +config USB_HOST_IFX_UNALIGNED_ADJ + bool "Adjust" + depends on USB_HOST_IFX + help + USB_HOST_IFX_UNALIGNED_ADJ + +#config USB_HOST_IFX_UNALIGNED_CHK +#config USB_HOST_IFX_UNALIGNED_NONE + + diff --git a/target/linux/lantiq/files/drivers/usb/ifxhcd/Makefile b/target/linux/lantiq/files/drivers/usb/ifxhcd/Makefile new file mode 100644 index 0000000000..0a2ac99380 --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/ifxhcd/Makefile @@ -0,0 +1,85 @@ + +# +# Makefile for USB Core files and filesystem +# + ifxusb_host-objs := ifxusb_driver.o + ifxusb_host-objs += ifxusb_ctl.o + ifxusb_host-objs += ifxusb_cif.o + ifxusb_host-objs += ifxusb_cif_h.o + ifxusb_host-objs += ifxhcd.o + ifxusb_host-objs += ifxhcd_es.o + ifxusb_host-objs += ifxhcd_intr.o + ifxusb_host-objs += ifxhcd_queue.o + +ifeq ($(CONFIG_IFX_TWINPASS),y) + EXTRA_CFLAGS += -D__IS_TWINPASS__ +endif +ifeq ($(CONFIG_IFX_DANUBE),y) + EXTRA_CFLAGS += -D__IS_DANUBE__ +endif +ifeq ($(CONFIG_IFX_AMAZON_SE),y) + EXTRA_CFLAGS += -D__IS_AMAZON_SE__ +endif +ifeq ($(CONFIG_IFX_AR9),y) + EXTRA_CFLAGS += -D__IS_AR9__ +endif +ifeq ($(CONFIG_IFX_AMAZON_S),y) + EXTRA_CFLAGS += -D__IS_AR9__ +endif +ifeq ($(CONFIG_IFX_VR9),y) + EXTRA_CFLAGS += -D__IS_VR9__ +endif + +ifeq ($(CONFIG_USB_HOST_IFX),y) + EXTRA_CFLAGS += -Dlinux -D__LINUX__ + EXTRA_CFLAGS += -D__IS_HOST__ + EXTRA_CFLAGS += -D__KERNEL__ +endif + +ifeq ($(CONFIG_USB_HOST_IFX),m) + EXTRA_CFLAGS += -Dlinux -D__LINUX__ + EXTRA_CFLAGS += -D__IS_HOST__ + EXTRA_CFLAGS += -D__KERNEL__ +endif + +ifeq ($(CONFIG_USB_DEBUG),y) + EXTRA_CFLAGS += -D__DEBUG__ + EXTRA_CFLAGS += -D__ENABLE_DUMP__ +endif + +ifeq ($(CONFIG_USB_HOST_IFX_B),y) + EXTRA_CFLAGS += -D__IS_DUAL__ +endif +ifeq ($(CONFIG_USB_HOST_IFX_1),y) + EXTRA_CFLAGS += -D__IS_FIRST__ +endif +ifeq ($(CONFIG_USB_HOST_IFX_2),y) + EXTRA_CFLAGS += -D__IS_SECOND__ +endif + +ifeq ($(CONFIG_USB_HOST_IFX_FORCE_USB11),y) + EXTRA_CFLAGS += -D__FORCE_USB11__ +endif +ifeq ($(CONFIG_USB_HOST_IFX_WITH_HS_ELECT_TST),y) + EXTRA_CFLAGS += -D__WITH_HS_ELECT_TST__ +endif +ifeq ($(CONFIG_USB_HOST_IFX_WITH_ISO),y) + EXTRA_CFLAGS += -D__EN_ISOC__ +endif +ifeq ($(CONFIG_USB_HOST_IFX_UNALIGNED_ADJ),y) + EXTRA_CFLAGS += -D__UNALIGNED_BUFFER_ADJ__ +endif +ifeq ($(CONFIG_USB_HOST_IFX_UNALIGNED_CHK),y) + EXTRA_CFLAGS += -D__UNALIGNED_BUFFER_CHK__ +endif + +# EXTRA_CFLAGS += -D__DYN_SOF_INTR__ + EXTRA_CFLAGS += -D__UEIP__ +# EXTRA_CFLAGS += -D__EN_ISOC__ +# EXTRA_CFLAGS += -D__EN_ISOC_SPLIT__ + +## 20110628 AVM/WK New flag for less SOF IRQs + EXTRA_CFLAGS += -D__USE_TIMER_4_SOF__ + +obj-$(CONFIG_USB_HOST_IFX) += ifxusb_host.o + diff --git a/target/linux/lantiq/files/drivers/usb/ifxhcd/TagHistory b/target/linux/lantiq/files/drivers/usb/ifxhcd/TagHistory new file mode 100644 index 0000000000..3820d70b7a --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/ifxhcd/TagHistory @@ -0,0 +1,171 @@ + + ++----------------------------------------------------------------------+ +| TAG: svn://embeddedvm/home/SVN/drivers/usb_host20/tags/5.18-r240-non_musb_ar9_vr9-SOF_Timer_Fixed +| Erzeugt mit SVN-Tagger Version 3.74. ++----------------------------------------------------------------------+ +FIX - Korrektur bei der SOF-Timer/IRQ Steuerung. (Bug in Tag 5.17) +FIX - Fehlerbehandlung an mehreren Stellen korrigiert bzw. eingebaut. + + + ++----------------------------------------------------------------------+ +| TAG: svn://embeddedvm/home/SVN/drivers/usb_host20/tags/5.17-r237-non_musb_ar9_vr9-2_6_32_41_Kompatibel +| Erzeugt mit SVN-Tagger Version 3.73. ++----------------------------------------------------------------------+ +FIX - Kompatiblität zum Update auf Kernel 2.6.32-41. Weiterhin für 28er geeignet. +ENH - Reduktion der Interrruptlast durch Nutzung eines hrtimers anstatt SOF-IRQ. + + + ++----------------------------------------------------------------------+ +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.16-r208-non_musb_ar9_vr9-20110421_Zero_Paket_Optimiert +| Erzeugt mit SVN-Tagger Version 3.66. ++----------------------------------------------------------------------+ + +FIX - VR9 / AR9 - Zero Packet. Optimierung korrigiert. + + + ++----------------------------------------------------------------------+ +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.15-r205-non_musb_ar9_vr9-20110421_Zero_Paket_WA_funktioniert +| Erzeugt mit SVN-Tagger Version 3.66. ++----------------------------------------------------------------------+ + +FIX - VR9 / AR9 - "Zero Packet" funktioniert nun wirklich. Letzter Tag hatte einen Bug. + + + ++----------------------------------------------------------------------+ +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.14-r202-non_musb_ar9_vr9-20110420_Zero_Paket_WA +| Erzeugt mit SVN-Tagger Version 3.66. ++----------------------------------------------------------------------+ + +FIX - VR9 / AR9 - Zero Packet Workaround: ZLP wird nun geschickt wenn URB_ZERO_PACKET aktiv ist. + Wird von LTE Altair Firmware benoetig. + + + ++----------------------------------------------------------------------+ +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.13-r199-non_musb_ar9_vr9-20110310_Init_Fix +| Erzeugt mit SVN-Tagger Version 3.64. ++----------------------------------------------------------------------+ + +FIX - VR9 / AR9 - Timing der Initialisierungsphase angepasst zum Kernel 2.6.28 mit UGW-4.3.1. + + + ++----------------------------------------------------------------------+ +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.12-r184-non_musb_ar9_vr9-20110118_Full_Speed_Fix +| Erzeugt mit SVN-Tagger Version 3.58. ++----------------------------------------------------------------------+ +AR9/VR9 (3370,6840,7320): +Makefile - FIX - (Workaround) Debug Modus hilft gegen Enumerationsfehler bei Full Speed Drucker. + + + ++----------------------------------------------------------------------+ +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.11-r175-non_musb_ar9_vr9-20101220_VR9_2_Ports_DMA_Fix +| Erzeugt mit SVN-Tagger Version 3.58. ++----------------------------------------------------------------------+ + +FIX - VR9 - Workaround DMA Burst Size. Wenn beiden USB Ports benutzt werden, geht der USB Host nicht mehr. + + + ++----------------------------------------------------------------------+ +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.10-r169-non_musb_ar9_vr9-Fix_Spontan_Reboot +| Erzeugt mit SVN-Tagger Version 3.58. ++----------------------------------------------------------------------+ + +FIX - Endlosschleife führte zu einem spontanen Reboot. + + + ++----------------------------------------------------------------------+ +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.9-r166-non_musb_ar9_vr9-20101112_deferred_completion +| Erzeugt mit SVN-Tagger Version 3.58. ++----------------------------------------------------------------------+ + +ENH - Deferred URB Completion Mechanismus eingebaut. Nun ca. 10% schneller bei usb-storage. + +FIX - PING Flow Control gefixt. +FIX - Channel Halt wird nun immer angerufen. (Split Transaction wurde nicht erfolgreich gestoppt). +FIX - Spinlock Benutzung verbessert. Mehr Stabilitaet. + +CHG - Ubersetztungsoption __DEBUG__ ist nun abhaengig von CONFIG_USB_DEBUG + + + ++----------------------------------------------------------------------+ +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.8-r149-non_musb_ar9_vr9-20100827_LTE_Interrupt_EP_Fix +| Erzeugt mit SVN-Tagger Version 3.57. ++----------------------------------------------------------------------+ +AR9/VR9 - FIX - Interrupt Packets gingen verloren, wegen falschem Timing beim OddFrame Bit. + + + ++----------------------------------------------------------------------+ +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.7-r142-non_musb_ar9_vr9-20100728_Unaligned_Buf_Fix +| Erzeugt mit SVN-Tagger Version 3.57. ++----------------------------------------------------------------------+ +FIX - "Unaligned Data" Flag wieder nach Transfer geloescht. + + + ++----------------------------------------------------------------------+ +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.6-r133-non_musb_ar9_vr9-20100714_Toggle_Datenverlust_Fix +| Erzeugt mit SVN-Tagger Version 3.57. ++----------------------------------------------------------------------+ +TL5508 - Einige UMTS Modems funktionierten nicht korrekt an der 7320 (AR9). +FIX - USB Data Toggle des usbcore benutzen. Datenverlust nach EP-Halt. + + + ++----------------------------------------------------------------------+ +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.5-r130-non_musb_ar9_vr9-20100712_USB_Ports_abschaltbar +| Erzeugt mit SVN-Tagger Version 3.57. ++----------------------------------------------------------------------+ +Power - Fix - Beide USB Port abschaltbar bei rmmod. +rmmod - FIX - URB_Dequeue funktionierte beim Entladen des Treibers nicht (mehrere Ursachen). + + + ++----------------------------------------------------------------------+ +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.4-r126-non_musb_ar9_vr9-20100701_Lost_Interrupt_Workaround +| Erzeugt mit SVN-Tagger Version 3.57. ++----------------------------------------------------------------------+ +FIX - Workaround wegen verpasstem Interrupt, bei Full-Speed Interrupt EP. + + ++----------------------------------------------------------------------+ +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.3-r123-non_musb_ar9_vr9-20100630_UMTS_Fixes +| Erzeugt mit SVN-Tagger Version 3.57. ++----------------------------------------------------------------------+ +FIX - Full-Speed Interrupt Endpoint hinter Hi-Speed Hub funktioniert nun (UMTS Modems) +FIX - usb_hcd_link_urb_from_ep API von USBCore muss benutzt werden. +FIX - Interrupt URBs nicht bei NAK completen. + + ++----------------------------------------------------------------------+ +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.2-r114-non_musb_ar9_vr9-20100520_StickAndSurf_funktioniert +| Erzeugt mit SVN-Tagger Version 3.56. ++----------------------------------------------------------------------+ +- Merge mit neuen LANTIQ Sourcen "3.0alpha B100312" +- Fix - Spin_lock eingebaut, Stick&Surf funktioniert nun + +- DEP - CONFIG_USB_HOST_IFX_WITH_ISO wird nicht unterstuetzt: In der Kernel Config deaktivieren. + + + ++----------------------------------------------------------------------+ +| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.1-r107-non_musb_ar9_vr9-20100505_IFXUSB_Host_mit_Energiemonitor +| Erzeugt mit SVN-Tagger Version 3.56. ++----------------------------------------------------------------------+ +USB Host Treiber für AR9 und VR9 +-------------------------------- +FIX - Toggle Error nach STALL - Einfacher Workaround - Nun werden Massenspeicherpartitionen erkannt! +AVM_POWERMETER - USB Energiemonitor Support. + +Bekanntes Problem: Stick and Surf funktioniert nur sporadisch, weil CONTROL_IRQ manchmal ausbleibt. + diff --git a/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxhcd.c b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxhcd.c new file mode 100644 index 0000000000..d2ae1250bb --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxhcd.c @@ -0,0 +1,2523 @@ +/***************************************************************************** + ** FILE NAME : ifxhcd.c + ** PROJECT : IFX USB sub-system V3 + ** MODULES : IFX USB sub-system Host and Device driver + ** SRC VERSION : 1.0 + ** DATE : 1/Jan/2009 + ** AUTHOR : Chen, Howard + ** DESCRIPTION : This file contains the structures, constants, and interfaces for + ** the Host Contoller Driver (HCD). + ** + ** The Host Controller Driver (HCD) is responsible for translating requests + ** from the USB Driver into the appropriate actions on the IFXUSB controller. + ** It isolates the USBD from the specifics of the controller by providing an + ** API to the USBD. + *****************************************************************************/ + +/*! + \file ifxhcd.c + \ingroup IFXUSB_DRIVER_V3 + \brief This file contains the implementation of the HCD. In Linux, + the HCD implements the hc_driver API. +*/ + +#include +#include "ifxusb_version.h" + +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include + + +#include "ifxusb_plat.h" +#include "ifxusb_regs.h" +#include "ifxusb_cif.h" +#include "ifxhcd.h" + +#include + +#ifdef CONFIG_AVM_POWERMETER +#include +#endif /*--- #ifdef CONFIG_AVM_POWERMETER ---*/ + +#ifdef __DEBUG__ + static void dump_urb_info(struct urb *_urb, char* _fn_name); + static void dump_channel_info(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh); +#endif + + +/*! + \brief Sets the final status of an URB and returns it to the device driver. Any + required cleanup of the URB is performed. + */ +void ifxhcd_complete_urb(ifxhcd_hcd_t *_ifxhcd, ifxhcd_urbd_t *_urbd, int _status) +{ + struct urb *urb=NULL; + unsigned long flags = 0; + + /*== AVM/BC 20101111 Function called with Lock ==*/ + //SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags); + + if (!list_empty(&_urbd->urbd_list_entry)) + list_del_init (&_urbd->urbd_list_entry); + + if(!_urbd->urb) + { + IFX_ERROR("%s: invalid urb\n",__func__); + /*== AVM/BC 20101111 Function called with Lock ==*/ + //SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); + return; + } + + urb=_urbd->urb; + + #ifdef __DEBUG__ + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) + { + IFX_PRINT("%s: _urbd %p, urb %p, device %d, ep %d %s/%s, status=%d\n", + __func__, _urbd,_urbd->urb, usb_pipedevice(_urbd->urb->pipe), + usb_pipeendpoint(_urbd->urb->pipe), + usb_pipein(_urbd->urb->pipe) ? "IN" : "OUT", + (_urbd->is_in) ? "IN" : "OUT", + _status); + if (_urbd->epqh->ep_type == IFXUSB_EP_TYPE_ISOC) + { + int i; + for (i = 0; i < _urbd->urb->number_of_packets; i++) + IFX_PRINT(" ISO Desc %d status: %d\n", i, _urbd->urb->iso_frame_desc[i].status); + } + } + #endif + + if (!_urbd->epqh) + IFX_ERROR("%s: invalid epqd\n",__func__); + + #if defined(__UNALIGNED_BUFFER_ADJ__) + else if(_urbd->is_active) + { + if( _urbd->epqh->aligned_checked && + _urbd->epqh->using_aligned_buf && + _urbd->xfer_buff && + _urbd->is_in ) + memcpy(_urbd->xfer_buff,_urbd->epqh->aligned_buf,_urbd->xfer_len); + _urbd->epqh->using_aligned_buf=0; + _urbd->epqh->using_aligned_setup=0; + _urbd->epqh->aligned_checked=0; + } + #endif + + urb->status = _status; + urb->hcpriv=NULL; + kfree(_urbd); + + usb_hcd_unlink_urb_from_ep(ifxhcd_to_syshcd(_ifxhcd), urb); + SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); + +// usb_hcd_giveback_urb(ifxhcd_to_syshcd(_ifxhcd), urb); + usb_hcd_giveback_urb(ifxhcd_to_syshcd(_ifxhcd), urb, _status); + + /*== AVM/BC 20100630 - 2.6.28 needs HCD link/unlink URBs ==*/ + SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags); +} + +/*== AVM/BC 20101111 URB Complete deferred + * Must be called with Spinlock + */ + +/*! + \brief Inserts an urbd structur in the completion list. The urbd will be + later completed by select_eps_sub + */ +void defer_ifxhcd_complete_urb(ifxhcd_hcd_t *_ifxhcd, ifxhcd_urbd_t *_urbd, int _status) +{ + + _urbd->status = _status; + + //Unlink Urbd from epqh / Insert it into the complete list + list_move_tail(&_urbd->urbd_list_entry, &_ifxhcd->urbd_complete_list); + +} + +/*! + \brief Processes all the URBs in a single EPQHs. Completes them with + status and frees the URBD. + */ +//static +void kill_all_urbs_in_epqh(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh, int _status) +{ + struct list_head *urbd_item; + ifxhcd_urbd_t *urbd; + + if(!_epqh) + return; + + for (urbd_item = _epqh->urbd_list.next; + urbd_item != &_epqh->urbd_list; + urbd_item = _epqh->urbd_list.next) + { + urbd = list_entry(urbd_item, ifxhcd_urbd_t, urbd_list_entry); + ifxhcd_complete_urb(_ifxhcd, urbd, _status); + } +} + + +/*! + \brief Free all EPS in one Processes all the URBs in a single list of EPQHs. Completes them with + -ETIMEDOUT and frees the URBD. + */ +//static +void epqh_list_free(ifxhcd_hcd_t *_ifxhcd, struct list_head *_epqh_list) +{ + struct list_head *item; + ifxhcd_epqh_t *epqh; + + if (!_epqh_list) + return; + if (_epqh_list->next == NULL) /* The list hasn't been initialized yet. */ + return; + + /* Ensure there are no URBDs or URBs left. */ + for (item = _epqh_list->next; item != _epqh_list; item = _epqh_list->next) + { + epqh = list_entry(item, ifxhcd_epqh_t, epqh_list_entry); + kill_all_urbs_in_epqh(_ifxhcd, epqh, -ETIMEDOUT); + ifxhcd_epqh_free(epqh); + } +} + + + +//static +void epqh_list_free_all(ifxhcd_hcd_t *_ifxhcd) +{ + unsigned long flags; + + /*== AVM/BC 20101111 - 2.6.28 Needs Spinlock ==*/ + SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags); + + epqh_list_free(_ifxhcd, &_ifxhcd->epqh_np_active ); + epqh_list_free(_ifxhcd, &_ifxhcd->epqh_np_ready ); + epqh_list_free(_ifxhcd, &_ifxhcd->epqh_intr_active ); + epqh_list_free(_ifxhcd, &_ifxhcd->epqh_intr_ready ); + #ifdef __EN_ISOC__ + epqh_list_free(_ifxhcd, &_ifxhcd->epqh_isoc_active ); + epqh_list_free(_ifxhcd, &_ifxhcd->epqh_isoc_ready ); + #endif + epqh_list_free(_ifxhcd, &_ifxhcd->epqh_stdby ); + + SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); + +} + + +/*! + \brief This function is called to handle the disconnection of host port. + */ +int32_t ifxhcd_disconnect(ifxhcd_hcd_t *_ifxhcd) +{ + IFX_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _ifxhcd); + + /* Set status flags for the hub driver. */ + _ifxhcd->flags.b.port_connect_status_change = 1; + _ifxhcd->flags.b.port_connect_status = 0; + + /* + * Shutdown any transfers in process by clearing the Tx FIFO Empty + * interrupt mask and status bits and disabling subsequent host + * channel interrupts. + */ + { + gint_data_t intr = { .d32 = 0 }; + intr.b.nptxfempty = 1; + intr.b.ptxfempty = 1; + intr.b.hcintr = 1; + ifxusb_mreg (&_ifxhcd->core_if.core_global_regs->gintmsk, intr.d32, 0); + ifxusb_mreg (&_ifxhcd->core_if.core_global_regs->gintsts, intr.d32, 0); + } + + /* Respond with an error status to all URBs in the schedule. */ + epqh_list_free_all(_ifxhcd); + + /* Clean up any host channels that were in use. */ + { + int num_channels; + ifxhcd_hc_t *channel; + ifxusb_hc_regs_t *hc_regs; + hcchar_data_t hcchar; + int i; + + num_channels = _ifxhcd->core_if.params.host_channels; + + for (i = 0; i < num_channels; i++) + { + channel = &_ifxhcd->ifxhc[i]; + if (list_empty(&channel->hc_list_entry)) + { + hc_regs = _ifxhcd->core_if.hc_regs[i]; + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + if (hcchar.b.chen) + { + /* Halt the channel. */ + hcchar.b.chdis = 1; + ifxusb_wreg(&hc_regs->hcchar, hcchar.d32); + } + list_add_tail(&channel->hc_list_entry, &_ifxhcd->free_hc_list); + ifxhcd_hc_cleanup(&_ifxhcd->core_if, channel); + } + } + } + return 1; +} + + +/*! + \brief Frees secondary storage associated with the ifxhcd_hcd structure contained + in the struct usb_hcd field. + */ +static void ifxhcd_freeextra(struct usb_hcd *_syshcd) +{ + ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd(_syshcd); + + IFX_DEBUGPL(DBG_HCD, "IFXUSB HCD FREE\n"); + + /* Free memory for EPQH/URBD lists */ + epqh_list_free_all(ifxhcd); + + /* Free memory for the host channels. */ + ifxusb_free_buf(ifxhcd->status_buf); + return; +} +#ifdef __USE_TIMER_4_SOF__ +static enum hrtimer_restart ifxhcd_timer_func(struct hrtimer *timer) { + ifxhcd_hcd_t *ifxhcd = container_of(timer, ifxhcd_hcd_t, hr_timer); + + ifxhcd_handle_intr(ifxhcd); + + return HRTIMER_NORESTART; +} +#endif + +/*! + \brief Initializes the HCD. This function allocates memory for and initializes the + static parts of the usb_hcd and ifxhcd_hcd structures. It also registers the + USB bus with the core and calls the hc_driver->start() function. It returns + a negative error on failure. + */ +int ifxhcd_init(ifxhcd_hcd_t *_ifxhcd) +{ + int retval = 0; + struct usb_hcd *syshcd = NULL; + + IFX_DEBUGPL(DBG_HCD, "IFX USB HCD INIT\n"); + + spin_lock_init(&_ifxhcd->lock); +#ifdef __USE_TIMER_4_SOF__ + hrtimer_init(&_ifxhcd->hr_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); + _ifxhcd->hr_timer.function = ifxhcd_timer_func; +#endif + _ifxhcd->hc_driver.description = _ifxhcd->core_if.core_name; + _ifxhcd->hc_driver.product_desc = "IFX USB Controller"; + //_ifxhcd->hc_driver.hcd_priv_size = sizeof(ifxhcd_hcd_t); + _ifxhcd->hc_driver.hcd_priv_size = sizeof(unsigned long); + _ifxhcd->hc_driver.irq = ifxhcd_irq; + _ifxhcd->hc_driver.flags = HCD_MEMORY | HCD_USB2; + _ifxhcd->hc_driver.start = ifxhcd_start; + _ifxhcd->hc_driver.stop = ifxhcd_stop; + //_ifxhcd->hc_driver.reset = + //_ifxhcd->hc_driver.suspend = + //_ifxhcd->hc_driver.resume = + _ifxhcd->hc_driver.urb_enqueue = ifxhcd_urb_enqueue; + _ifxhcd->hc_driver.urb_dequeue = ifxhcd_urb_dequeue; + _ifxhcd->hc_driver.endpoint_disable = ifxhcd_endpoint_disable; + _ifxhcd->hc_driver.get_frame_number = ifxhcd_get_frame_number; + _ifxhcd->hc_driver.hub_status_data = ifxhcd_hub_status_data; + _ifxhcd->hc_driver.hub_control = ifxhcd_hub_control; + //_ifxhcd->hc_driver.hub_suspend = + //_ifxhcd->hc_driver.hub_resume = + + /* Allocate memory for and initialize the base HCD and */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) + syshcd = usb_create_hcd(&_ifxhcd->hc_driver, _ifxhcd->dev, _ifxhcd->core_if.core_name); +#else + syshcd = usb_create_hcd(&_ifxhcd->hc_driver, _ifxhcd->dev, _ifxhcd->dev->bus_id); +#endif + + if (syshcd == NULL) + { + retval = -ENOMEM; + goto error1; + } + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) + syshcd->has_tt = 1; +#endif + + syshcd->rsrc_start = (unsigned long)_ifxhcd->core_if.core_global_regs; + syshcd->regs = (void *)_ifxhcd->core_if.core_global_regs; + syshcd->self.otg_port = 0; + + //*((unsigned long *)(&(syshcd->hcd_priv)))=(unsigned long)_ifxhcd; + //*((unsigned long *)(&(syshcd->hcd_priv[0])))=(unsigned long)_ifxhcd; + syshcd->hcd_priv[0]=(unsigned long)_ifxhcd; + _ifxhcd->syshcd=syshcd; + + INIT_LIST_HEAD(&_ifxhcd->epqh_np_active ); + INIT_LIST_HEAD(&_ifxhcd->epqh_np_ready ); + INIT_LIST_HEAD(&_ifxhcd->epqh_intr_active ); + INIT_LIST_HEAD(&_ifxhcd->epqh_intr_ready ); + #ifdef __EN_ISOC__ + INIT_LIST_HEAD(&_ifxhcd->epqh_isoc_active ); + INIT_LIST_HEAD(&_ifxhcd->epqh_isoc_ready ); + #endif + INIT_LIST_HEAD(&_ifxhcd->epqh_stdby ); + INIT_LIST_HEAD(&_ifxhcd->urbd_complete_list); + + /* + * Create a host channel descriptor for each host channel implemented + * in the controller. Initialize the channel descriptor array. + */ + INIT_LIST_HEAD(&_ifxhcd->free_hc_list); + { + int num_channels = _ifxhcd->core_if.params.host_channels; + int i; + for (i = 0; i < num_channels; i++) + { + _ifxhcd->ifxhc[i].hc_num = i; + IFX_DEBUGPL(DBG_HCDV, "HCD Added channel #%d\n", i); + } + } + + /* Set device flags indicating whether the HCD supports DMA. */ + if(_ifxhcd->dev->dma_mask) + *(_ifxhcd->dev->dma_mask) = ~0; + _ifxhcd->dev->coherent_dma_mask = ~0; + + /* + * Finish generic HCD initialization and start the HCD. This function + * allocates the DMA buffer pool, registers the USB bus, requests the + * IRQ line, and calls ifxusb_hcd_start method. + */ +// retval = usb_add_hcd(syshcd, _ifxhcd->core_if.irq, SA_INTERRUPT|SA_SHIRQ); + retval = usb_add_hcd(syshcd, _ifxhcd->core_if.irq, IRQF_DISABLED | IRQF_SHARED ); + if (retval < 0) + goto error2; + + /* + * Allocate space for storing data on status transactions. Normally no + * data is sent, but this space acts as a bit bucket. This must be + * done after usb_add_hcd since that function allocates the DMA buffer + * pool. + */ + _ifxhcd->status_buf = ifxusb_alloc_buf(IFXHCD_STATUS_BUF_SIZE, 1); + + if (_ifxhcd->status_buf) + { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) + IFX_DEBUGPL(DBG_HCD, "IFX USB HCD Initialized, bus=%s, usbbus=%d\n", _ifxhcd->core_if.core_name, syshcd->self.busnum); +#else + IFX_DEBUGPL(DBG_HCD, "IFX USB HCD Initialized, bus=%s, usbbus=%d\n", _ifxhcd->dev->bus_id, syshcd->self.busnum); +#endif + return 0; + } + IFX_ERROR("%s: status_buf allocation failed\n", __func__); + + /* Error conditions */ + usb_remove_hcd(syshcd); +error2: + ifxhcd_freeextra(syshcd); + usb_put_hcd(syshcd); +error1: + return retval; +} + +/*! + \brief Removes the HCD. + Frees memory and resources associated with the HCD and deregisters the bus. + */ +void ifxhcd_remove(ifxhcd_hcd_t *_ifxhcd) +{ + struct usb_hcd *syshcd = ifxhcd_to_syshcd(_ifxhcd); + + IFX_DEBUGPL(DBG_HCD, "IFX USB HCD REMOVE\n"); + +/* == AVM/WK 20100709 - Fix: Order changed, disable IRQs not before remove_hcd == */ + + usb_remove_hcd(syshcd); + + /* Turn off all interrupts */ + ifxusb_wreg (&_ifxhcd->core_if.core_global_regs->gintmsk, 0); + ifxusb_mreg (&_ifxhcd->core_if.core_global_regs->gahbcfg, 1, 0); + + ifxhcd_freeextra(syshcd); + + usb_put_hcd(syshcd); + + return; +} + + +/* ========================================================================= + * Linux HC Driver Functions + * ========================================================================= */ + +/*! + \brief Initializes the IFXUSB controller and its root hub and prepares it for host + mode operation. Activates the root port. Returns 0 on success and a negative + error code on failure. + Called by USB stack. + */ +int ifxhcd_start(struct usb_hcd *_syshcd) +{ + ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd (_syshcd); + ifxusb_core_if_t *core_if = &ifxhcd->core_if; + struct usb_bus *bus; + + IFX_DEBUGPL(DBG_HCD, "IFX USB HCD START\n"); + + bus = hcd_to_bus(_syshcd); + + /* Initialize the bus state. */ + _syshcd->state = HC_STATE_RUNNING; + + /* Initialize and connect root hub if one is not already attached */ + if (bus->root_hub) + { + IFX_DEBUGPL(DBG_HCD, "IFX USB HCD Has Root Hub\n"); + /* Inform the HUB driver to resume. */ + usb_hcd_resume_root_hub(_syshcd); + } + + ifxhcd->flags.d32 = 0; + + /* Put all channels in the free channel list and clean up channel states.*/ + { + struct list_head *item; + item = ifxhcd->free_hc_list.next; + while (item != &ifxhcd->free_hc_list) + { + list_del(item); + item = ifxhcd->free_hc_list.next; + } + } + { + int num_channels = ifxhcd->core_if.params.host_channels; + int i; + for (i = 0; i < num_channels; i++) + { + ifxhcd_hc_t *channel; + channel = &ifxhcd->ifxhc[i]; + list_add_tail(&channel->hc_list_entry, &ifxhcd->free_hc_list); + ifxhcd_hc_cleanup(&ifxhcd->core_if, channel); + } + } + /* Initialize the USB core for host mode operation. */ + + ifxusb_host_enable_interrupts(core_if); + ifxusb_enable_global_interrupts(core_if); + ifxusb_phy_power_on (core_if); + + ifxusb_vbus_init(core_if); + + /* Turn on the vbus power. */ + { + hprt0_data_t hprt0; + hprt0.d32 = ifxusb_read_hprt0(core_if); + + IFX_PRINT("Init: Power Port (%d)\n", hprt0.b.prtpwr); + if (hprt0.b.prtpwr == 0 ) + { + hprt0.b.prtpwr = 1; + ifxusb_wreg(core_if->hprt0, hprt0.d32); + ifxusb_vbus_on(core_if); + } + } + return 0; +} + + +/*! + \brief Halts the IFXUSB host mode operations in a clean manner. USB transfers are + stopped. + */ +void ifxhcd_stop(struct usb_hcd *_syshcd) +{ + ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd(_syshcd); + hprt0_data_t hprt0 = { .d32=0 }; + + IFX_DEBUGPL(DBG_HCD, "IFX USB HCD STOP\n"); + + /* Turn off all interrupts. */ + ifxusb_disable_global_interrupts(&ifxhcd->core_if ); + ifxusb_host_disable_interrupts(&ifxhcd->core_if ); +#ifdef __USE_TIMER_4_SOF__ + hrtimer_cancel(&ifxhcd->hr_timer); +#endif + /* + * The root hub should be disconnected before this function is called. + * The disconnect will clear the URBD lists (via ..._hcd_urb_dequeue) + * and the EPQH lists (via ..._hcd_endpoint_disable). + */ + + /* Turn off the vbus power */ + IFX_PRINT("PortPower off\n"); + + ifxusb_vbus_off(&ifxhcd->core_if ); + + ifxusb_vbus_free(&ifxhcd->core_if ); + + hprt0.b.prtpwr = 0; + ifxusb_wreg(ifxhcd->core_if.hprt0, hprt0.d32); + return; +} + +/*! + \brief Returns the current frame number + */ +int ifxhcd_get_frame_number(struct usb_hcd *_syshcd) +{ + ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd(_syshcd); + hfnum_data_t hfnum; + + hfnum.d32 = ifxusb_rreg(&ifxhcd->core_if.host_global_regs->hfnum); + + return hfnum.b.frnum; +} + +/*! + \brief Starts processing a USB transfer request specified by a USB Request Block + (URB). mem_flags indicates the type of memory allocation to use while + processing this URB. + */ +int ifxhcd_urb_enqueue( struct usb_hcd *_syshcd, + /*--- struct usb_host_endpoint *_sysep, Parameter im 2.6.28 entfallen ---*/ + struct urb *_urb, + gfp_t _mem_flags) +{ + int retval = 0; + ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd (_syshcd); + struct usb_host_endpoint *_sysep = ifxhcd_urb_to_endpoint(_urb); + ifxhcd_epqh_t *epqh; + + #ifdef __DEBUG__ + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) + dump_urb_info(_urb, "ifxusb_hcd_urb_enqueue"); + #endif //__DEBUG__ + + if (!ifxhcd->flags.b.port_connect_status) /* No longer connected. */ + return -ENODEV; + + #ifndef __EN_ISOC__ + if(usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) + { + IFX_ERROR("ISOC transfer not supported!!!\n"); + return -ENODEV; + } + #endif + + retval=ifxhcd_urbd_create (ifxhcd,_urb); + + if (retval) + { + IFX_ERROR("IFXUSB HCD URB Enqueue failed creating URBD\n"); + return retval; + } + epqh = (ifxhcd_epqh_t *) _sysep->hcpriv; + ifxhcd_epqh_ready(ifxhcd, epqh); + + select_eps(ifxhcd); + //enable_sof(ifxhcd); + { + gint_data_t gintsts; + gintsts.d32=0; + gintsts.b.sofintr = 1; + ifxusb_mreg(&ifxhcd->core_if.core_global_regs->gintmsk, 0,gintsts.d32); + } + + return retval; +} + +/*! + \brief Aborts/cancels a USB transfer request. Always returns 0 to indicate + success. + */ +int ifxhcd_urb_dequeue( struct usb_hcd *_syshcd, + struct urb *_urb, int status /* Parameter neu in 2.6.28 */) +{ + unsigned long flags; + ifxhcd_hcd_t *ifxhcd; + ifxhcd_urbd_t *urbd; + ifxhcd_epqh_t *epqh; + int is_active=0; + int rc; + + struct usb_host_endpoint *_sysep; + + IFX_DEBUGPL(DBG_HCD, "IFXUSB HCD URB Dequeue\n"); + + #ifndef __EN_ISOC__ + if(usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) + return 0; + #endif + + _sysep = ifxhcd_urb_to_endpoint(_urb); + + ifxhcd = syshcd_to_ifxhcd(_syshcd); + + SPIN_LOCK_IRQSAVE(&ifxhcd->lock, flags); + + /*== AVM/BC 20100630 - 2.6.28 needs HCD link/unlink URBs ==*/ + rc = usb_hcd_check_unlink_urb(_syshcd, _urb, status); + if (rc) { + SPIN_UNLOCK_IRQRESTORE(&ifxhcd->lock, flags); + return rc; + } + + urbd = (ifxhcd_urbd_t *) _urb->hcpriv; + + if(_sysep) + epqh = (ifxhcd_epqh_t *) _sysep->hcpriv; + else + epqh = (ifxhcd_epqh_t *) urbd->epqh; + + if(epqh!=urbd->epqh) + IFX_ERROR("%s inconsistant epqh %p %p\n",__func__,epqh,urbd->epqh); + + #ifdef __DEBUG__ + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) + { + dump_urb_info(_urb, "ifxhcd_urb_dequeue"); + if (epqh->is_active) + dump_channel_info(ifxhcd, epqh); + } + #endif //__DEBUG__ + + if(!epqh->hc) + epqh->is_active=0; + else if (!ifxhcd->flags.b.port_connect_status) + epqh->is_active=0; + else if (epqh->is_active && urbd->is_active) + { + /*== AVM/WK 20100709 - halt channel only if really started ==*/ + //if (epqh->hc->xfer_started && !epqh->hc->wait_for_sof) { + /*== AVM/WK 20101112 - halt channel if started ==*/ + if (epqh->hc->xfer_started) { + /* + * If still connected (i.e. in host mode), halt the + * channel so it can be used for other transfers. If + * no longer connected, the host registers can't be + * written to halt the channel since the core is in + * device mode. + */ + /* == 20110803 AVM/WK FIX propagate status == */ + if (_urb->status == -EINPROGRESS) { + _urb->status = status; + } + ifxhcd_hc_halt(&ifxhcd->core_if, epqh->hc, HC_XFER_URB_DEQUEUE); + epqh->hc = NULL; + is_active=1; + } + } + + if(is_active) + { + SPIN_UNLOCK_IRQRESTORE(&ifxhcd->lock, flags); + } + else + { + list_del_init(&urbd->urbd_list_entry); + kfree (urbd); + + /*== AVM/BC 20100630 - 2.6.28 needs HCD link/unlink URBs ==*/ + usb_hcd_unlink_urb_from_ep(_syshcd, _urb); + + SPIN_UNLOCK_IRQRESTORE(&ifxhcd->lock, flags); + _urb->hcpriv = NULL; +// usb_hcd_giveback_urb(_syshcd, _urb); + usb_hcd_giveback_urb(_syshcd, _urb, status /* neu in 2.6.28 */); + select_eps(ifxhcd); + } + + return 0; +} + + + +/*! + \brief Frees resources in the IFXUSB controller related to a given endpoint. Also + clears state in the HCD related to the endpoint. Any URBs for the endpoint + must already be dequeued. + */ +void ifxhcd_endpoint_disable( struct usb_hcd *_syshcd, + struct usb_host_endpoint *_sysep) +{ + ifxhcd_epqh_t *epqh; + ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd(_syshcd); + unsigned long flags; + + int retry = 0; + + IFX_DEBUGPL(DBG_HCD, "IFXUSB HCD EP DISABLE: _bEndpointAddress=0x%02x, " + "endpoint=%d\n", _sysep->desc.bEndpointAddress, + ifxhcd_ep_addr_to_endpoint(_sysep->desc.bEndpointAddress)); + + SPIN_LOCK_IRQSAVE(&ifxhcd->lock, flags); + if((uint32_t)_sysep>=0x80000000 && (uint32_t)_sysep->hcpriv>=(uint32_t)0x80000000) + { + epqh = (ifxhcd_epqh_t *)(_sysep->hcpriv); + if (epqh && epqh->sysep==_sysep) + { + +#if 1 /*== AVM/BC 20101111 CHG Option active: Kill URBs when disabling EP ==*/ + while (!list_empty(&epqh->urbd_list)) + { + if (retry++ > 250) + { + IFX_WARN("IFXUSB HCD EP DISABLE:" + " URBD List for this endpoint is not empty\n"); + break; + } + kill_all_urbs_in_epqh(ifxhcd, epqh, -ETIMEDOUT); + } +#else + while (!list_empty(&epqh->urbd_list)) + { + /** Check that the QTD list is really empty */ + if (retry++ > 250) + { + IFX_WARN("IFXUSB HCD EP DISABLE:" + " URBD List for this endpoint is not empty\n"); + break; + } + SPIN_UNLOCK_IRQRESTORE(&ifxhcd->lock, flags); + schedule_timeout_uninterruptible(1); + SPIN_LOCK_IRQSAVE(&ifxhcd->lock, flags); + } +#endif + + ifxhcd_epqh_free(epqh); + _sysep->hcpriv = NULL; + } + } + SPIN_UNLOCK_IRQRESTORE(&ifxhcd->lock, flags); +} + + +/*! + \brief Handles host mode interrupts for the IFXUSB controller. Returns IRQ_NONE if + * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid + * interrupt. + * + * This function is called by the USB core when an interrupt occurs + */ +irqreturn_t ifxhcd_irq(struct usb_hcd *_syshcd) +{ + ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd (_syshcd); + int32_t retval=0; + + //mask_and_ack_ifx_irq (ifxhcd->core_if.irq); + retval = ifxhcd_handle_intr(ifxhcd); + return IRQ_RETVAL(retval); +} + + +/*! + \brief Handles host mode Over Current Interrupt + */ +irqreturn_t ifxhcd_oc_irq(int _irq , void *_dev) +{ + ifxhcd_hcd_t *ifxhcd = _dev; + int32_t retval=1; + + ifxhcd->flags.b.port_over_current_change = 1; + ifxusb_vbus_off(&ifxhcd->core_if); + IFX_DEBUGP("OC INTERRUPT # %d\n",ifxhcd->core_if.core_no); + + //mask_and_ack_ifx_irq (_irq); + return IRQ_RETVAL(retval); +} + +/*! + \brief Creates Status Change bitmap for the root hub and root port. The bitmap is + returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 + is the status change indicator for the single root port. Returns 1 if either + change indicator is 1, otherwise returns 0. + */ +int ifxhcd_hub_status_data(struct usb_hcd *_syshcd, char *_buf) +{ + ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd (_syshcd); + + _buf[0] = 0; + _buf[0] |= (ifxhcd->flags.b.port_connect_status_change || + ifxhcd->flags.b.port_reset_change || + ifxhcd->flags.b.port_enable_change || + ifxhcd->flags.b.port_suspend_change || + ifxhcd->flags.b.port_over_current_change) << 1; + + #ifdef __DEBUG__ + if (_buf[0]) + { + IFX_DEBUGPL(DBG_HCD, "IFXUSB HCD HUB STATUS DATA:" + " Root port status changed\n"); + IFX_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n", + ifxhcd->flags.b.port_connect_status_change); + IFX_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n", + ifxhcd->flags.b.port_reset_change); + IFX_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n", + ifxhcd->flags.b.port_enable_change); + IFX_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n", + ifxhcd->flags.b.port_suspend_change); + IFX_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n", + ifxhcd->flags.b.port_over_current_change); + } + #endif //__DEBUG__ + return (_buf[0] != 0); +} + +#ifdef __WITH_HS_ELECT_TST__ + extern void do_setup(ifxusb_core_if_t *_core_if) ; + extern void do_in_ack(ifxusb_core_if_t *_core_if); +#endif //__WITH_HS_ELECT_TST__ + +/*! + \brief Handles hub class-specific requests. + */ +int ifxhcd_hub_control( struct usb_hcd *_syshcd, + u16 _typeReq, + u16 _wValue, + u16 _wIndex, + char *_buf, + u16 _wLength) +{ + int retval = 0; + + ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd (_syshcd); + ifxusb_core_if_t *core_if = &ifxhcd->core_if; + struct usb_hub_descriptor *desc; + hprt0_data_t hprt0 = {.d32 = 0}; + + uint32_t port_status; + + switch (_typeReq) + { + case ClearHubFeature: + IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " + "ClearHubFeature 0x%x\n", _wValue); + switch (_wValue) + { + case C_HUB_LOCAL_POWER: + case C_HUB_OVER_CURRENT: + /* Nothing required here */ + break; + default: + retval = -EINVAL; + IFX_ERROR ("IFXUSB HCD - " + "ClearHubFeature request %xh unknown\n", _wValue); + } + break; + case ClearPortFeature: + if (!_wIndex || _wIndex > 1) + goto error; + + switch (_wValue) + { + case USB_PORT_FEAT_ENABLE: + IFX_DEBUGPL (DBG_ANY, "IFXUSB HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); + hprt0.d32 = ifxusb_read_hprt0 (core_if); + hprt0.b.prtena = 1; + ifxusb_wreg(core_if->hprt0, hprt0.d32); + break; + case USB_PORT_FEAT_SUSPEND: + IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); + hprt0.d32 = ifxusb_read_hprt0 (core_if); + hprt0.b.prtres = 1; + ifxusb_wreg(core_if->hprt0, hprt0.d32); + /* Clear Resume bit */ + mdelay (100); + hprt0.b.prtres = 0; + ifxusb_wreg(core_if->hprt0, hprt0.d32); + break; + case USB_PORT_FEAT_POWER: + IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_POWER\n"); + #ifdef __IS_DUAL__ + ifxusb_vbus_off(core_if); + #else + ifxusb_vbus_off(core_if); + #endif + hprt0.d32 = ifxusb_read_hprt0 (core_if); + hprt0.b.prtpwr = 0; + ifxusb_wreg(core_if->hprt0, hprt0.d32); + break; + case USB_PORT_FEAT_INDICATOR: + IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); + /* Port inidicator not supported */ + break; + case USB_PORT_FEAT_C_CONNECTION: + /* Clears drivers internal connect status change + * flag */ + IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); + ifxhcd->flags.b.port_connect_status_change = 0; + break; + case USB_PORT_FEAT_C_RESET: + /* Clears the driver's internal Port Reset Change + * flag */ + IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); + ifxhcd->flags.b.port_reset_change = 0; + break; + case USB_PORT_FEAT_C_ENABLE: + /* Clears the driver's internal Port + * Enable/Disable Change flag */ + IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); + ifxhcd->flags.b.port_enable_change = 0; + break; + case USB_PORT_FEAT_C_SUSPEND: + /* Clears the driver's internal Port Suspend + * Change flag, which is set when resume signaling on + * the host port is complete */ + IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); + ifxhcd->flags.b.port_suspend_change = 0; + break; + case USB_PORT_FEAT_C_OVER_CURRENT: + IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); + ifxhcd->flags.b.port_over_current_change = 0; + break; + default: + retval = -EINVAL; + IFX_ERROR ("IFXUSB HCD - " + "ClearPortFeature request %xh " + "unknown or unsupported\n", _wValue); + } + break; + case GetHubDescriptor: + IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " + "GetHubDescriptor\n"); + desc = (struct usb_hub_descriptor *)_buf; + desc->bDescLength = 9; + desc->bDescriptorType = 0x29; + desc->bNbrPorts = 1; + desc->wHubCharacteristics = 0x08; + desc->bPwrOn2PwrGood = 1; + desc->bHubContrCurrent = 0; +// desc->bitmap[0] = 0; +// desc->bitmap[1] = 0xff; + break; + case GetHubStatus: + IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " + "GetHubStatus\n"); + memset (_buf, 0, 4); + break; + case GetPortStatus: + IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " + "GetPortStatus\n"); + if (!_wIndex || _wIndex > 1) + goto error; + +# ifdef CONFIG_AVM_POWERMETER + { + /* first port only, but 2 Hosts */ + static unsigned char ucOldPower1 = 255; + static unsigned char ucOldPower2 = 255; + + unsigned char ucNewPower = 0; + struct usb_device *childdev = _syshcd->self.root_hub->children[0]; + + if (childdev != NULL) { + ucNewPower = (childdev->actconfig != NULL) + ? childdev->actconfig->desc.bMaxPower + : 50;/* default: 50 means 100 mA*/ + } + if (_syshcd->self.busnum == 1) { + if (ucOldPower1 != ucNewPower) { + ucOldPower1 = ucNewPower; + printk (KERN_INFO "IFXHCD#1: AVM Powermeter changed to %u mA\n", ucNewPower*2); + PowerManagmentRessourceInfo(powerdevice_usb_host, ucNewPower*2); + } + } else { + if (ucOldPower2 != ucNewPower) { + ucOldPower2 = ucNewPower; + printk (KERN_INFO "IFXHCD#2: AVM Powermeter changed to %u mA\n", ucNewPower*2); + PowerManagmentRessourceInfo(powerdevice_usb_host2, ucNewPower*2); + } + } + } +# endif /*--- #ifdef CONFIG_AVM_POWERMETER ---*/ + + port_status = 0; + if (ifxhcd->flags.b.port_connect_status_change) + port_status |= (1 << USB_PORT_FEAT_C_CONNECTION); + if (ifxhcd->flags.b.port_enable_change) + port_status |= (1 << USB_PORT_FEAT_C_ENABLE); + if (ifxhcd->flags.b.port_suspend_change) + port_status |= (1 << USB_PORT_FEAT_C_SUSPEND); + if (ifxhcd->flags.b.port_reset_change) + port_status |= (1 << USB_PORT_FEAT_C_RESET); + if (ifxhcd->flags.b.port_over_current_change) + { + IFX_ERROR("Device Not Supported\n"); + port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT); + } + if (!ifxhcd->flags.b.port_connect_status) + { + /* + * The port is disconnected, which means the core is + * either in device mode or it soon will be. Just + * return 0's for the remainder of the port status + * since the port register can't be read if the core + * is in device mode. + */ + *((u32 *) _buf) = cpu_to_le32(port_status); + break; + } + + hprt0.d32 = ifxusb_rreg(core_if->hprt0); + IFX_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32); + if (hprt0.b.prtconnsts) + port_status |= (1 << USB_PORT_FEAT_CONNECTION); + if (hprt0.b.prtena) + port_status |= (1 << USB_PORT_FEAT_ENABLE); + if (hprt0.b.prtsusp) + port_status |= (1 << USB_PORT_FEAT_SUSPEND); + if (hprt0.b.prtovrcurract) + port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT); + if (hprt0.b.prtrst) + port_status |= (1 << USB_PORT_FEAT_RESET); + if (hprt0.b.prtpwr) + port_status |= (1 << USB_PORT_FEAT_POWER); +/* if (hprt0.b.prtspd == IFXUSB_HPRT0_PRTSPD_HIGH_SPEED) + port_status |= (1 << USB_PORT_FEAT_HIGHSPEED); + else if (hprt0.b.prtspd == IFXUSB_HPRT0_PRTSPD_LOW_SPEED) + port_status |= (1 << USB_PORT_FEAT_LOWSPEED);*/ + if (hprt0.b.prttstctl) + port_status |= (1 << USB_PORT_FEAT_TEST); + /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ + *((u32 *) _buf) = cpu_to_le32(port_status); + break; + case SetHubFeature: + IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " + "SetHubFeature\n"); + /* No HUB features supported */ + break; + case SetPortFeature: + if (_wValue != USB_PORT_FEAT_TEST && (!_wIndex || _wIndex > 1)) + goto error; + /* + * The port is disconnected, which means the core is + * either in device mode or it soon will be. Just + * return without doing anything since the port + * register can't be written if the core is in device + * mode. + */ + if (!ifxhcd->flags.b.port_connect_status) + break; + switch (_wValue) + { + case USB_PORT_FEAT_SUSPEND: + IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " + "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); + hprt0.d32 = ifxusb_read_hprt0 (core_if); + hprt0.b.prtsusp = 1; + ifxusb_wreg(core_if->hprt0, hprt0.d32); + //IFX_PRINT( "SUSPEND: HPRT0=%0x\n", hprt0.d32); + /* Suspend the Phy Clock */ + { + pcgcctl_data_t pcgcctl = {.d32=0}; + pcgcctl.b.stoppclk = 1; + ifxusb_wreg(core_if->pcgcctl, pcgcctl.d32); + } + break; + case USB_PORT_FEAT_POWER: + IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " + "SetPortFeature - USB_PORT_FEAT_POWER\n"); + ifxusb_vbus_on (core_if); + hprt0.d32 = ifxusb_read_hprt0 (core_if); + hprt0.b.prtpwr = 1; + ifxusb_wreg(core_if->hprt0, hprt0.d32); + break; + case USB_PORT_FEAT_RESET: + IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " + "SetPortFeature - USB_PORT_FEAT_RESET\n"); + hprt0.d32 = ifxusb_read_hprt0 (core_if); + hprt0.b.prtrst = 1; + ifxusb_wreg(core_if->hprt0, hprt0.d32); + /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ + MDELAY (60); + hprt0.b.prtrst = 0; + ifxusb_wreg(core_if->hprt0, hprt0.d32); + break; + #ifdef __WITH_HS_ELECT_TST__ + case USB_PORT_FEAT_TEST: + { + uint32_t t; + gint_data_t gintmsk; + t = (_wIndex >> 8); /* MSB wIndex USB */ + IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " + "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t); + warn("USB_PORT_FEAT_TEST %d\n", t); + if (t < 6) + { + hprt0.d32 = ifxusb_read_hprt0 (core_if); + hprt0.b.prttstctl = t; + ifxusb_wreg(core_if->hprt0, hprt0.d32); + } + else if (t == 6) /* HS_HOST_PORT_SUSPEND_RESUME */ + { + /* Save current interrupt mask */ + gintmsk.d32 = ifxusb_rreg(&core_if->core_global_regs->gintmsk); + + /* Disable all interrupts while we muck with + * the hardware directly + */ + ifxusb_wreg(&core_if->core_global_regs->gintmsk, 0); + + /* 15 second delay per the test spec */ + mdelay(15000); + + /* Drive suspend on the root port */ + hprt0.d32 = ifxusb_read_hprt0 (core_if); + hprt0.b.prtsusp = 1; + hprt0.b.prtres = 0; + ifxusb_wreg(core_if->hprt0, hprt0.d32); + + /* 15 second delay per the test spec */ + mdelay(15000); + + /* Drive resume on the root port */ + hprt0.d32 = ifxusb_read_hprt0 (core_if); + hprt0.b.prtsusp = 0; + hprt0.b.prtres = 1; + ifxusb_wreg(core_if->hprt0, hprt0.d32); + mdelay(100); + + /* Clear the resume bit */ + hprt0.b.prtres = 0; + ifxusb_wreg(core_if->hprt0, hprt0.d32); + + /* Restore interrupts */ + ifxusb_wreg(&core_if->core_global_regs->gintmsk, gintmsk.d32); + } + else if (t == 7) /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */ + { + /* Save current interrupt mask */ + gintmsk.d32 = ifxusb_rreg(&core_if->core_global_regs->gintmsk); + + /* Disable all interrupts while we muck with + * the hardware directly + */ + ifxusb_wreg(&core_if->core_global_regs->gintmsk, 0); + + /* 15 second delay per the test spec */ + mdelay(15000); + + /* Send the Setup packet */ + do_setup(core_if); + + /* 15 second delay so nothing else happens for awhile */ + mdelay(15000); + + /* Restore interrupts */ + ifxusb_wreg(&core_if->core_global_regs->gintmsk, gintmsk.d32); + } + + else if (t == 8) /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */ + { + /* Save current interrupt mask */ + gintmsk.d32 = ifxusb_rreg(&core_if->core_global_regs->gintmsk); + + /* Disable all interrupts while we muck with + * the hardware directly + */ + ifxusb_wreg(&core_if->core_global_regs->gintmsk, 0); + + /* Send the Setup packet */ + do_setup(core_if); + + /* 15 second delay so nothing else happens for awhile */ + mdelay(15000); + + /* Send the In and Ack packets */ + do_in_ack(core_if); + + /* 15 second delay so nothing else happens for awhile */ + mdelay(15000); + + /* Restore interrupts */ + ifxusb_wreg(&core_if->core_global_regs->gintmsk, gintmsk.d32); + } + } + break; + #endif //__WITH_HS_ELECT_TST__ + case USB_PORT_FEAT_INDICATOR: + IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " + "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); + /* Not supported */ + break; + default: + retval = -EINVAL; + IFX_ERROR ("IFXUSB HCD - " + "SetPortFeature request %xh " + "unknown or unsupported\n", _wValue); + } + break; + default: + error: + retval = -EINVAL; + IFX_WARN ("IFXUSB HCD - " + "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n", + _typeReq, _wIndex, _wValue); + } + return retval; +} + + +/*! + \brief Assigns transactions from a URBD to a free host channel and initializes the + host channel to perform the transactions. The host channel is removed from + the free list. + \param _ifxhcd The HCD state structure. + \param _epqh Transactions from the first URBD for this EPQH are selected and assigned to a free host channel. + */ +static int assign_and_init_hc(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh) +{ + ifxhcd_hc_t *ifxhc; + ifxhcd_urbd_t *urbd; + struct urb *urb; + + IFX_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, _ifxhcd, _epqh); + + if(list_empty(&_epqh->urbd_list)) + return 0; + + ifxhc = list_entry(_ifxhcd->free_hc_list.next, ifxhcd_hc_t, hc_list_entry); + /* Remove the host channel from the free list. */ + list_del_init(&ifxhc->hc_list_entry); + + urbd = list_entry(_epqh->urbd_list.next, ifxhcd_urbd_t, urbd_list_entry); + urb = urbd->urb; + + _epqh->hc = ifxhc; + _epqh->urbd = urbd; + ifxhc->epqh = _epqh; + + urbd->is_active=1; + + /* + * Use usb_pipedevice to determine device address. This address is + * 0 before the SET_ADDRESS command and the correct address afterward. + */ + ifxhc->dev_addr = usb_pipedevice(urb->pipe); + ifxhc->ep_num = usb_pipeendpoint(urb->pipe); + + ifxhc->xfer_started = 0; + + if (urb->dev->speed == USB_SPEED_LOW) ifxhc->speed = IFXUSB_EP_SPEED_LOW; + else if (urb->dev->speed == USB_SPEED_FULL) ifxhc->speed = IFXUSB_EP_SPEED_FULL; + else ifxhc->speed = IFXUSB_EP_SPEED_HIGH; + + ifxhc->mps = _epqh->mps; + ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; + + ifxhc->ep_type = _epqh->ep_type; + + if(_epqh->ep_type==IFXUSB_EP_TYPE_CTRL) + { + ifxhc->control_phase=IFXHCD_CONTROL_SETUP; + ifxhc->is_in = 0; + ifxhc->data_pid_start = IFXUSB_HC_PID_SETUP; + ifxhc->xfer_buff = urbd->setup_buff; + ifxhc->xfer_len = 8; + ifxhc->xfer_count = 0; + ifxhc->short_rw =(urb->transfer_flags & URB_ZERO_PACKET)?1:0; + } + else + { + ifxhc->is_in = urbd->is_in; + ifxhc->xfer_buff = urbd->xfer_buff; + ifxhc->xfer_len = urbd->xfer_len; + ifxhc->xfer_count = 0; + /* == AVM/WK 20100710 Fix - Use toggle of usbcore ==*/ + //ifxhc->data_pid_start = _epqh->data_toggle; + ifxhc->data_pid_start = usb_gettoggle (urb->dev, usb_pipeendpoint(urb->pipe), usb_pipeout (urb->pipe)) + ? IFXUSB_HC_PID_DATA1 + : IFXUSB_HC_PID_DATA0; + if(ifxhc->is_in) + ifxhc->short_rw =0; + else + ifxhc->short_rw =(urb->transfer_flags & URB_ZERO_PACKET)?1:0; + + #ifdef __EN_ISOC__ + if(_epqh->ep_type==IFXUSB_EP_TYPE_ISOC) + { + struct usb_iso_packet_descriptor *frame_desc; + frame_desc = &urb->iso_frame_desc[urbd->isoc_frame_index]; + ifxhc->xfer_buff += frame_desc->offset + urbd->isoc_split_offset; + ifxhc->xfer_len = frame_desc->length - urbd->isoc_split_offset; + if (ifxhc->isoc_xact_pos == IFXUSB_HCSPLIT_XACTPOS_ALL) + { + if (ifxhc->xfer_len <= 188) + ifxhc->isoc_xact_pos = IFXUSB_HCSPLIT_XACTPOS_ALL; + else + ifxhc->isoc_xact_pos = IFXUSB_HCSPLIT_XACTPOS_BEGIN; + } + } + #endif + } + + ifxhc->do_ping=0; + if (_ifxhcd->core_if.snpsid < 0x4f54271a && ifxhc->speed == IFXUSB_EP_SPEED_HIGH) + ifxhc->do_ping=1; + + + /* Set the split attributes */ + ifxhc->split = 0; + if (_epqh->need_split) { + ifxhc->split = 1; + ifxhc->hub_addr = urb->dev->tt->hub->devnum; + ifxhc->port_addr = urb->dev->ttport; + } + + //ifxhc->uint16_t pkt_count_limit + + { + hcint_data_t hc_intr_mask; + uint8_t hc_num = ifxhc->hc_num; + ifxusb_hc_regs_t *hc_regs = _ifxhcd->core_if.hc_regs[hc_num]; + + /* Clear old interrupt conditions for this host channel. */ + hc_intr_mask.d32 = 0xFFFFFFFF; + hc_intr_mask.b.reserved = 0; + ifxusb_wreg(&hc_regs->hcint, hc_intr_mask.d32); + + /* Enable channel interrupts required for this transfer. */ + hc_intr_mask.d32 = 0; + hc_intr_mask.b.chhltd = 1; + hc_intr_mask.b.ahberr = 1; + + ifxusb_wreg(&hc_regs->hcintmsk, hc_intr_mask.d32); + + /* Enable the top level host channel interrupt. */ + { + uint32_t intr_enable; + intr_enable = (1 << hc_num); + ifxusb_mreg(&_ifxhcd->core_if.host_global_regs->haintmsk, 0, intr_enable); + } + + /* Make sure host channel interrupts are enabled. */ + { + gint_data_t gintmsk ={.d32 = 0}; + gintmsk.b.hcintr = 1; + ifxusb_mreg(&_ifxhcd->core_if.core_global_regs->gintmsk, 0, gintmsk.d32); + } + + /* + * Program the HCCHARn register with the endpoint characteristics for + * the current transfer. + */ + { + hcchar_data_t hcchar; + + hcchar.d32 = 0; + hcchar.b.devaddr = ifxhc->dev_addr; + hcchar.b.epnum = ifxhc->ep_num; + hcchar.b.lspddev = (ifxhc->speed == IFXUSB_EP_SPEED_LOW); + hcchar.b.eptype = ifxhc->ep_type; + hcchar.b.mps = ifxhc->mps; + ifxusb_wreg(&hc_regs->hcchar, hcchar.d32); + + IFX_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, ifxhc->hc_num); + IFX_DEBUGPL(DBG_HCDV, " Dev Addr: %d\n" , hcchar.b.devaddr); + IFX_DEBUGPL(DBG_HCDV, " Ep Num: %d\n" , hcchar.b.epnum); + IFX_DEBUGPL(DBG_HCDV, " Is Low Speed: %d\n", hcchar.b.lspddev); + IFX_DEBUGPL(DBG_HCDV, " Ep Type: %d\n" , hcchar.b.eptype); + IFX_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n" , hcchar.b.mps); + IFX_DEBUGPL(DBG_HCDV, " Multi Cnt: %d\n" , hcchar.b.multicnt); + } + /* Program the HCSPLIT register for SPLITs */ + { + hcsplt_data_t hcsplt; + + hcsplt.d32 = 0; + if (ifxhc->split) + { + IFX_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n", ifxhc->hc_num, + (ifxhc->split==2) ? "CSPLIT" : "SSPLIT"); + hcsplt.b.spltena = 1; + hcsplt.b.compsplt = (ifxhc->split==2); + #ifdef __EN_ISOC__ + if(_epqh->ep_type==IFXUSB_EP_TYPE_ISOC) + hcsplt.b.xactpos = ifxhc->isoc_xact_pos; + else + #endif + hcsplt.b.xactpos = IFXUSB_HCSPLIT_XACTPOS_ALL; + hcsplt.b.hubaddr = ifxhc->hub_addr; + hcsplt.b.prtaddr = ifxhc->port_addr; + IFX_DEBUGPL(DBG_HCDV, " comp split %d\n" , hcsplt.b.compsplt); + IFX_DEBUGPL(DBG_HCDV, " xact pos %d\n" , hcsplt.b.xactpos); + IFX_DEBUGPL(DBG_HCDV, " hub addr %d\n" , hcsplt.b.hubaddr); + IFX_DEBUGPL(DBG_HCDV, " port addr %d\n" , hcsplt.b.prtaddr); + IFX_DEBUGPL(DBG_HCDV, " is_in %d\n" , ifxhc->is_in); + IFX_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n" , ifxhc->mps); + IFX_DEBUGPL(DBG_HCDV, " xferlen: %d\n" , ifxhc->xfer_len); + } + ifxusb_wreg(&hc_regs->hcsplt, hcsplt.d32); + } + } + + ifxhc->nak_retry_r=ifxhc->nak_retry=0; + ifxhc->nak_countdown_r=ifxhc->nak_countdown=0; + + if (ifxhc->split) + { + if(ifxhc->is_in) + { + } + else + { + } + } + else if(_epqh->ep_type==IFXUSB_EP_TYPE_CTRL) + { + if(ifxhc->is_in) + { + } + else + { + } + } + else if(_epqh->ep_type==IFXUSB_EP_TYPE_BULK) + { + if(ifxhc->is_in) + { +// ifxhc->nak_retry_r=ifxhc->nak_retry=nak_retry_max; +// ifxhc->nak_countdown_r=ifxhc->nak_countdown=nak_countdown_max; + } + else + { + } + } + else if(_epqh->ep_type==IFXUSB_EP_TYPE_INTR) + { + if(ifxhc->is_in) + { + } + else + { + } + } + else if(_epqh->ep_type==IFXUSB_EP_TYPE_ISOC) + { + if(ifxhc->is_in) + { + } + else + { + } + } + + return 1; +} + +/*! + \brief This function selects transactions from the HCD transfer schedule and + assigns them to available host channels. It is called from HCD interrupt + handler functions. + */ +static void select_eps_sub(ifxhcd_hcd_t *_ifxhcd) +{ + struct list_head *epqh_ptr; + struct list_head *urbd_ptr; + ifxhcd_epqh_t *epqh; + ifxhcd_urbd_t *urbd; + int ret_val=0; + + /*== AVM/BC 20101111 Function called with Lock ==*/ + +// #ifdef __DEBUG__ +// IFX_DEBUGPL(DBG_HCD, " ifxhcd_select_ep\n"); +// #endif + + /* Process entries in the periodic ready list. */ + #ifdef __EN_ISOC__ + epqh_ptr = _ifxhcd->epqh_isoc_ready.next; + while (epqh_ptr != &_ifxhcd->epqh_isoc_ready && !list_empty(&_ifxhcd->free_hc_list)) + { + epqh = list_entry(epqh_ptr, ifxhcd_epqh_t, epqh_list_entry); + epqh_ptr = epqh_ptr->next; + if(epqh->period_do) + { + if(assign_and_init_hc(_ifxhcd, epqh)) + { + IFX_DEBUGPL(DBG_HCD, " select_eps ISOC\n"); + list_move_tail(&epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_active); + epqh->is_active=1; + ret_val=1; + epqh->period_do=0; + } + } + } + #endif + + epqh_ptr = _ifxhcd->epqh_intr_ready.next; + while (epqh_ptr != &_ifxhcd->epqh_intr_ready && !list_empty(&_ifxhcd->free_hc_list)) + { + epqh = list_entry(epqh_ptr, ifxhcd_epqh_t, epqh_list_entry); + epqh_ptr = epqh_ptr->next; + if(epqh->period_do) + { + if(assign_and_init_hc(_ifxhcd, epqh)) + { + IFX_DEBUGPL(DBG_HCD, " select_eps INTR\n"); + list_move_tail(&epqh->epqh_list_entry, &_ifxhcd->epqh_intr_active); + epqh->is_active=1; + ret_val=1; + epqh->period_do=0; + } + } + } + + epqh_ptr = _ifxhcd->epqh_np_ready.next; + while (epqh_ptr != &_ifxhcd->epqh_np_ready && !list_empty(&_ifxhcd->free_hc_list)) // may need to preserve at lease one for period + { + epqh = list_entry(epqh_ptr, ifxhcd_epqh_t, epqh_list_entry); + epqh_ptr = epqh_ptr->next; + if(assign_and_init_hc(_ifxhcd, epqh)) + { + IFX_DEBUGPL(DBG_HCD, " select_eps CTRL/BULK\n"); + list_move_tail(&epqh->epqh_list_entry, &_ifxhcd->epqh_np_active); + epqh->is_active=1; + ret_val=1; + } + } + if(ret_val) + /*== AVM/BC 20101111 Function called with Lock ==*/ + process_channels_sub(_ifxhcd); + + /* AVM/BC 20101111 Urbds completion loop */ + while (!list_empty(&_ifxhcd->urbd_complete_list)) + { + urbd_ptr = _ifxhcd->urbd_complete_list.next; + list_del_init(urbd_ptr); + + urbd = list_entry(urbd_ptr, ifxhcd_urbd_t, urbd_list_entry); + + ifxhcd_complete_urb(_ifxhcd, urbd, urbd->status); + + } + +} + +static void select_eps_func(unsigned long data) +{ + unsigned long flags; + + ifxhcd_hcd_t *ifxhcd; + ifxhcd=((ifxhcd_hcd_t *)data); + + /* AVM/BC 20101111 select_eps_in_use flag removed */ + + SPIN_LOCK_IRQSAVE(&ifxhcd->lock, flags); + + /*if(ifxhcd->select_eps_in_use){ + SPIN_UNLOCK_IRQRESTORE(&ifxhcd->lock, flags); + return; + } + ifxhcd->select_eps_in_use=1; + */ + + select_eps_sub(ifxhcd); + + //ifxhcd->select_eps_in_use=0; + + SPIN_UNLOCK_IRQRESTORE(&ifxhcd->lock, flags); +} + +void select_eps(ifxhcd_hcd_t *_ifxhcd) +{ + if(in_irq()) + { + if(!_ifxhcd->select_eps.func) + { + _ifxhcd->select_eps.next = NULL; + _ifxhcd->select_eps.state = 0; + atomic_set( &_ifxhcd->select_eps.count, 0); + _ifxhcd->select_eps.func = select_eps_func; + _ifxhcd->select_eps.data = (unsigned long)_ifxhcd; + } + tasklet_schedule(&_ifxhcd->select_eps); + } + else + { + unsigned long flags; + + /* AVM/BC 20101111 select_eps_in_use flag removed */ + + SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags); + + /*if(_ifxhcd->select_eps_in_use){ + printk ("select_eps non_irq: busy\n"); + SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); + return; + } + _ifxhcd->select_eps_in_use=1; + */ + + select_eps_sub(_ifxhcd); + + //_ifxhcd->select_eps_in_use=0; + + SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); + } +} + +/*! + \brief + */ +static void process_unaligned( ifxhcd_epqh_t *_epqh) +{ + #if defined(__UNALIGNED_BUFFER_ADJ__) + if(!_epqh->aligned_checked) + { + uint32_t xfer_len; + xfer_len=_epqh->urbd->xfer_len; + if(_epqh->urbd->is_in && xfer_len<_epqh->mps) + xfer_len = _epqh->mps; + _epqh->using_aligned_buf=0; + + if(xfer_len > 0 && ((unsigned long)_epqh->urbd->xfer_buff) & 3) + { + if( _epqh->aligned_buf + && _epqh->aligned_buf_len > 0 + && _epqh->aligned_buf_len < xfer_len + ) + { + ifxusb_free_buf(_epqh->aligned_buf); + _epqh->aligned_buf=NULL; + _epqh->aligned_buf_len=0; + } + if(! _epqh->aligned_buf || ! _epqh->aligned_buf_len) + { + _epqh->aligned_buf = ifxusb_alloc_buf(xfer_len, _epqh->urbd->is_in); + if(_epqh->aligned_buf) + _epqh->aligned_buf_len = xfer_len; + } + if(_epqh->aligned_buf) + { + if(!_epqh->urbd->is_in) + memcpy(_epqh->aligned_buf, _epqh->urbd->xfer_buff, xfer_len); + _epqh->using_aligned_buf=1; + _epqh->hc->xfer_buff = _epqh->aligned_buf; + } + else + IFX_WARN("%s():%d\n",__func__,__LINE__); + } + if(_epqh->ep_type==IFXUSB_EP_TYPE_CTRL) + { + _epqh->using_aligned_setup=0; + if(((unsigned long)_epqh->urbd->setup_buff) & 3) + { + if(! _epqh->aligned_setup) + _epqh->aligned_setup = ifxusb_alloc_buf(8,0); + if(_epqh->aligned_setup) + { + memcpy(_epqh->aligned_setup, _epqh->urbd->setup_buff, 8); + _epqh->using_aligned_setup=1; + } + else + IFX_WARN("%s():%d\n",__func__,__LINE__); + _epqh->hc->xfer_buff = _epqh->aligned_setup; + } + } + } + #elif defined(__UNALIGNED_BUFFER_CHK__) + if(!_epqh->aligned_checked) + { + if(_epqh->urbd->is_in) + { + if(_epqh->urbd->xfer_len==0) + IFX_WARN("%s():%d IN xfer while length is zero \n",__func__,__LINE__); + else{ + if(_epqh->urbd->xfer_len < _epqh->mps) + IFX_WARN("%s():%d IN xfer while length < mps \n",__func__,__LINE__); + + if(((unsigned long)_epqh->urbd->xfer_buff) & 3) + IFX_WARN("%s():%d IN xfer Buffer UNALIGNED\n",__func__,__LINE__); + } + } + else + { + if(_epqh->urbd->xfer_len > 0 && (((unsigned long)_epqh->urbd->xfer_buff) & 3) ) + IFX_WARN("%s():%d OUT xfer Buffer UNALIGNED\n",__func__,__LINE__); + } + + if(_epqh->ep_type==IFXUSB_EP_TYPE_CTRL) + { + if(((unsigned long)_epqh->urbd->setup_buff) & 3) + IFX_WARN("%s():%d SETUP xfer Buffer UNALIGNED\n",__func__,__LINE__); + } + } + #endif + _epqh->aligned_checked=1; +} + + +/*! + \brief + */ +void process_channels_sub(ifxhcd_hcd_t *_ifxhcd) +{ + ifxhcd_epqh_t *epqh; + struct list_head *epqh_item; + struct ifxhcd_hc *hc; + + #ifdef __EN_ISOC__ + if (!list_empty(&_ifxhcd->epqh_isoc_active)) + { + for (epqh_item = _ifxhcd->epqh_isoc_active.next; + epqh_item != &_ifxhcd->epqh_isoc_active; + ) + { + epqh = list_entry(epqh_item, ifxhcd_epqh_t, epqh_list_entry); + epqh_item = epqh_item->next; + hc=epqh->hc; + if(hc && !hc->xfer_started && epqh->period_do) + { + if(hc->split==0 + || hc->split==1 + ) + { + //epqh->ping_state = 0; + process_unaligned(epqh); + hc->wait_for_sof=epqh->wait_for_sof; + epqh->wait_for_sof=0; + ifxhcd_hc_start(&_ifxhcd->core_if, hc); + epqh->period_do=0; + { + gint_data_t gintsts = {.d32 = 0}; + gintsts.b.sofintr = 1; + ifxusb_mreg(&_ifxhcd->core_if.core_global_regs->gintmsk,0, gintsts.d32); + } + } + } + } + } + #endif + + if (!list_empty(&_ifxhcd->epqh_intr_active)) + { + for (epqh_item = _ifxhcd->epqh_intr_active.next; + epqh_item != &_ifxhcd->epqh_intr_active; + ) + { + epqh = list_entry(epqh_item, ifxhcd_epqh_t, epqh_list_entry); + epqh_item = epqh_item->next; + hc=epqh->hc; + if(hc && !hc->xfer_started && epqh->period_do) + { + if(hc->split==0 + || hc->split==1 + ) + { + //epqh->ping_state = 0; + process_unaligned(epqh); + hc->wait_for_sof=epqh->wait_for_sof; + epqh->wait_for_sof=0; + ifxhcd_hc_start(&_ifxhcd->core_if, hc); + epqh->period_do=0; +#ifdef __USE_TIMER_4_SOF__ + /* AVM/WK change: let hc_start decide, if irq is needed */ +#else + { + gint_data_t gintsts = {.d32 = 0}; + gintsts.b.sofintr = 1; + ifxusb_mreg(&_ifxhcd->core_if.core_global_regs->gintmsk,0, gintsts.d32); + } +#endif + } + } + + } + } + + if (!list_empty(&_ifxhcd->epqh_np_active)) + { + for (epqh_item = _ifxhcd->epqh_np_active.next; + epqh_item != &_ifxhcd->epqh_np_active; + ) + { + epqh = list_entry(epqh_item, ifxhcd_epqh_t, epqh_list_entry); + epqh_item = epqh_item->next; + hc=epqh->hc; + if(hc) + { + if(!hc->xfer_started) + { + if(hc->split==0 + || hc->split==1 + //|| hc->split_counter == 0 + ) + { + //epqh->ping_state = 0; + process_unaligned(epqh); + hc->wait_for_sof=epqh->wait_for_sof; + epqh->wait_for_sof=0; + ifxhcd_hc_start(&_ifxhcd->core_if, hc); + } + } + } + } + } +} + +void process_channels(ifxhcd_hcd_t *_ifxhcd) +{ + unsigned long flags; + + /* AVM/WK Fix: use spin_lock instead busy flag + **/ + SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags); + + //if(_ifxhcd->process_channels_in_use) + // return; + //_ifxhcd->process_channels_in_use=1; + + process_channels_sub(_ifxhcd); + //_ifxhcd->process_channels_in_use=0; + SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); +} + + +#ifdef __HC_XFER_TIMEOUT__ + static void hc_xfer_timeout(unsigned long _ptr) + { + hc_xfer_info_t *xfer_info = (hc_xfer_info_t *)_ptr; + int hc_num = xfer_info->hc->hc_num; + IFX_WARN("%s: timeout on channel %d\n", __func__, hc_num); + IFX_WARN(" start_hcchar_val 0x%08x\n", xfer_info->hc->start_hcchar_val); + } +#endif + +void ifxhcd_hc_dumb_rx(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc,uint8_t *dump_buf) +{ + ifxusb_hc_regs_t *hc_regs = _core_if->hc_regs[_ifxhc->hc_num]; + hctsiz_data_t hctsiz= { .d32=0 }; + hcchar_data_t hcchar; + + + _ifxhc->xfer_len = _ifxhc->mps; + hctsiz.b.xfersize = _ifxhc->mps; + hctsiz.b.pktcnt = 0; + hctsiz.b.pid = _ifxhc->data_pid_start; + ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32); + + ifxusb_wreg(&hc_regs->hcdma, (uint32_t)(CPHYSADDR( ((uint32_t)(dump_buf))))); + + { + hcint_data_t hcint= { .d32=0 }; +// hcint.b.nak =1; +// hcint.b.nyet=1; +// hcint.b.ack =1; + hcint.d32 =0xFFFFFFFF; + ifxusb_wreg(&hc_regs->hcint, hcint.d32); + } + + /* Set host channel enable after all other setup is complete. */ + hcchar.b.chen = 1; + hcchar.b.chdis = 0; + hcchar.b.epdir = 1; + IFX_DEBUGPL(DBG_HCDV, " HCCHART: 0x%08x\n", hcchar.d32); + ifxusb_wreg(&hc_regs->hcchar, hcchar.d32); +} + +/*! + \brief This function trigger a data transfer for a host channel and + starts the transfer. + + For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ + register along with a packet count of 1 and the channel is enabled. This + causes a single PING transaction to occur. Other fields in HCTSIZ are + simply set to 0 since no data transfer occurs in this case. + + For a PING transfer in DMA mode, the HCTSIZ register is initialized with + all the information required to perform the subsequent data transfer. In + addition, the Do Ping bit is set in the HCTSIZ register. In this case, the + controller performs the entire PING protocol, then starts the data + transfer. + \param _core_if Pointer of core_if structure + \param _ifxhc Information needed to initialize the host channel. The xfer_len + value may be reduced to accommodate the max widths of the XferSize and + PktCnt fields in the HCTSIZn register. The multi_count value may be changed + to reflect the final xfer_len value. + */ +void ifxhcd_hc_start(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc) +{ + hctsiz_data_t hctsiz= { .d32=0 }; + hcchar_data_t hcchar; + uint32_t max_hc_xfer_size = _core_if->params.max_transfer_size; + uint16_t max_hc_pkt_count = _core_if->params.max_packet_count; + ifxusb_hc_regs_t *hc_regs = _core_if->hc_regs[_ifxhc->hc_num]; + hfnum_data_t hfnum; + + hctsiz.b.dopng = 0; +// if(_ifxhc->do_ping && !_ifxhc->is_in) hctsiz.b.dopng = 1; + + _ifxhc->nak_countdown=_ifxhc->nak_countdown_r; + + /* AVM/BC 20101111 Workaround: Always PING if HI-Speed Out and xfer_len > 0 */ + if(/*_ifxhc->do_ping &&*/ + (!_ifxhc->is_in) && + (_ifxhc->speed == IFXUSB_EP_SPEED_HIGH) && + ((_ifxhc->ep_type == IFXUSB_EP_TYPE_BULK) || ((_ifxhc->ep_type == IFXUSB_EP_TYPE_CTRL) && (_ifxhc->control_phase != IFXHCD_CONTROL_SETUP))) && + _ifxhc->xfer_len + ) + hctsiz.b.dopng = 1; + + _ifxhc->xfer_started = 1; + + if(_ifxhc->epqh->pkt_count_limit > 0 && _ifxhc->epqh->pkt_count_limit < max_hc_pkt_count ) + { + max_hc_pkt_count=_ifxhc->epqh->pkt_count_limit; + if(max_hc_pkt_count * _ifxhc->mps < max_hc_xfer_size) + max_hc_xfer_size = max_hc_pkt_count * _ifxhc->mps; + } + if (_ifxhc->split > 0) + { + { + gint_data_t gintsts = {.d32 = 0}; + gintsts.b.sofintr = 1; + ifxusb_mreg(&_core_if->core_global_regs->gintmsk,0, gintsts.d32); + } + + _ifxhc->start_pkt_count = 1; + if(!_ifxhc->is_in && _ifxhc->split>1) // OUT CSPLIT + _ifxhc->xfer_len = 0; + if (_ifxhc->xfer_len > _ifxhc->mps) + _ifxhc->xfer_len = _ifxhc->mps; + if (_ifxhc->xfer_len > 188) + _ifxhc->xfer_len = 188; + } + else if(_ifxhc->is_in) + { + _ifxhc->short_rw = 0; + if (_ifxhc->xfer_len > 0) + { + if (_ifxhc->xfer_len > max_hc_xfer_size) + _ifxhc->xfer_len = max_hc_xfer_size - _ifxhc->mps + 1; + _ifxhc->start_pkt_count = (_ifxhc->xfer_len + _ifxhc->mps - 1) / _ifxhc->mps; + if (_ifxhc->start_pkt_count > max_hc_pkt_count) + _ifxhc->start_pkt_count = max_hc_pkt_count; + } + else /* Need 1 packet for transfer length of 0. */ + _ifxhc->start_pkt_count = 1; + _ifxhc->xfer_len = _ifxhc->start_pkt_count * _ifxhc->mps; + } + else //non-split out + { + if (_ifxhc->xfer_len == 0) + { + /*== AVM/BC WK 20110421 ZERO PACKET Workaround: Is not an error ==*/ + //if(_ifxhc->short_rw==0) + // printk(KERN_INFO "%s() line %d: ZLP write without short_rw set!\n",__func__,__LINE__); + _ifxhc->start_pkt_count = 1; + } + else + { + if (_ifxhc->xfer_len > max_hc_xfer_size) + { + _ifxhc->start_pkt_count = (max_hc_xfer_size / _ifxhc->mps); + _ifxhc->xfer_len = _ifxhc->start_pkt_count * _ifxhc->mps; + } + else + { + _ifxhc->start_pkt_count = (_ifxhc->xfer_len+_ifxhc->mps-1) / _ifxhc->mps; +// if(_ifxhc->start_pkt_count * _ifxhc->mps == _ifxhc->xfer_len ) +// _ifxhc->start_pkt_count += _ifxhc->short_rw; + /*== AVM/BC WK 20110421 ZERO PACKET Workaround / check if short_rw is needed ==*/ + if(_ifxhc->start_pkt_count * _ifxhc->mps != _ifxhc->xfer_len ) + _ifxhc->short_rw = 0; + } + } + } + + #ifdef __EN_ISOC__ + if (_ifxhc->ep_type == IFXUSB_EP_TYPE_ISOC) + { + /* Set up the initial PID for the transfer. */ + #if 1 + _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0; + #else + if (_ifxhc->speed == IFXUSB_EP_SPEED_HIGH) + { + if (_ifxhc->is_in) + { + if (_ifxhc->multi_count == 1) + _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0; + else if (_ifxhc->multi_count == 2) + _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1; + else + _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA2; + } + else + { + if (_ifxhc->multi_count == 1) + _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0; + else + _ifxhc->data_pid_start = IFXUSB_HC_PID_MDATA; + } + } + else + _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0; + #endif + } + #endif + + hctsiz.b.xfersize = _ifxhc->xfer_len; + hctsiz.b.pktcnt = _ifxhc->start_pkt_count; + hctsiz.b.pid = _ifxhc->data_pid_start; + + ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32); + + + IFX_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _ifxhc->hc_num); + IFX_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize); + IFX_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n" , hctsiz.b.pktcnt); + IFX_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid); + IFX_DEBUGPL(DBG_HCDV, " DMA: 0x%08x\n", (uint32_t)(CPHYSADDR( ((uint32_t)(_ifxhc->xfer_buff))+ _ifxhc->xfer_count ))); + ifxusb_wreg(&hc_regs->hcdma, (uint32_t)(CPHYSADDR( ((uint32_t)(_ifxhc->xfer_buff))+ _ifxhc->xfer_count ))); + + /* Start the split */ + if (_ifxhc->split>0) + { + hcsplt_data_t hcsplt; + hcsplt.d32 = ifxusb_rreg (&hc_regs->hcsplt); + hcsplt.b.spltena = 1; + if (_ifxhc->split>1) + hcsplt.b.compsplt = 1; + else + hcsplt.b.compsplt = 0; + + #ifdef __EN_ISOC__ + if (_ifxhc->ep_type == IFXUSB_EP_TYPE_ISOC) + hcsplt.b.xactpos = _ifxhc->isoc_xact_pos; + else + #endif + hcsplt.b.xactpos = IFXUSB_HCSPLIT_XACTPOS_ALL;// if not ISO + ifxusb_wreg(&hc_regs->hcsplt, hcsplt.d32); + IFX_DEBUGPL(DBG_HCDV, " SPLIT: XACT_POS:0x%08x\n", hcsplt.d32); + } + + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); +// hcchar.b.multicnt = _ifxhc->multi_count; + hcchar.b.multicnt = 1; + + #ifdef __DEBUG__ + _ifxhc->start_hcchar_val = hcchar.d32; + if (hcchar.b.chdis) + IFX_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", + __func__, _ifxhc->hc_num, hcchar.d32); + #endif + + /* Set host channel enable after all other setup is complete. */ + hcchar.b.chen = 1; + hcchar.b.chdis = 0; + hcchar.b.epdir = _ifxhc->is_in; + _ifxhc->hcchar=hcchar.d32; + + IFX_DEBUGPL(DBG_HCDV, " HCCHART: 0x%08x\n", _ifxhc->hcchar); + + /* == 20110901 AVM/WK Fix: Clear IRQ flags in any case ==*/ + { + hcint_data_t hcint= { .d32=0 }; + hcint.d32 =0xFFFFFFFF; + ifxusb_wreg(&hc_regs->hcint, hcint.d32); + } + + if(_ifxhc->wait_for_sof==0) + { + hcint_data_t hcint; + + hcint.d32=ifxusb_rreg(&hc_regs->hcintmsk); + + hcint.b.nak =0; + hcint.b.ack =0; + /* == 20110901 AVM/WK Fix: We don't need NOT YET IRQ ==*/ + hcint.b.nyet=0; + if(_ifxhc->nak_countdown_r) + hcint.b.nak =1; + ifxusb_wreg(&hc_regs->hcintmsk, hcint.d32); + + /* AVM WK / BC 20100827 + * MOVED. Oddframe updated inmediatly before write HCChar Register. + */ + if (_ifxhc->ep_type == IFXUSB_EP_TYPE_INTR || _ifxhc->ep_type == IFXUSB_EP_TYPE_ISOC) + { + hfnum.d32 = ifxusb_rreg(&_core_if->host_global_regs->hfnum); + /* 1 if _next_ frame is odd, 0 if it's even */ + hcchar.b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1; + _ifxhc->hcchar=hcchar.d32; + } + + ifxusb_wreg(&hc_regs->hcchar, _ifxhc->hcchar); +#ifdef __USE_TIMER_4_SOF__ + } else { + //activate SOF IRQ + gint_data_t gintsts = {.d32 = 0}; + gintsts.b.sofintr = 1; + ifxusb_mreg(&_core_if->core_global_regs->gintmsk,0, gintsts.d32); +#endif + } + + #ifdef __HC_XFER_TIMEOUT__ + /* Start a timer for this transfer. */ + init_timer(&_ifxhc->hc_xfer_timer); + _ifxhc->hc_xfer_timer.function = hc_xfer_timeout; + _ifxhc->hc_xfer_timer.core_if = _core_if; + _ifxhc->hc_xfer_timer.hc = _ifxhc; + _ifxhc->hc_xfer_timer.data = (unsigned long)(&_ifxhc->hc_xfer_info); + _ifxhc->hc_xfer_timer.expires = jiffies + (HZ*10); + add_timer(&_ifxhc->hc_xfer_timer); + #endif +} + +/*! + \brief Attempts to halt a host channel. This function should only be called + to abort a transfer in DMA mode. Under normal circumstances in DMA mode, the + controller halts the channel when the transfer is complete or a condition + occurs that requires application intervention. + + In DMA mode, always sets the Channel Enable and Channel Disable bits of the + HCCHARn register. The controller ensures there is space in the request + queue before submitting the halt request. + + Some time may elapse before the core flushes any posted requests for this + host channel and halts. The Channel Halted interrupt handler completes the + deactivation of the host channel. + */ +void ifxhcd_hc_halt(ifxusb_core_if_t *_core_if, + ifxhcd_hc_t *_ifxhc, + ifxhcd_halt_status_e _halt_status) +{ + hcchar_data_t hcchar; + ifxusb_hc_regs_t *hc_regs; + + hc_regs = _core_if->hc_regs[_ifxhc->hc_num]; + + WARN_ON(_halt_status == HC_XFER_NO_HALT_STATUS); + + if (_halt_status == HC_XFER_URB_DEQUEUE || + _halt_status == HC_XFER_AHB_ERR) + { + /* + * Disable all channel interrupts except Ch Halted. The URBD + * and EPQH state associated with this transfer has been cleared + * (in the case of URB_DEQUEUE), so the channel needs to be + * shut down carefully to prevent crashes. + */ + hcint_data_t hcintmsk; + hcintmsk.d32 = 0; + hcintmsk.b.chhltd = 1; + ifxusb_wreg(&hc_regs->hcintmsk, hcintmsk.d32); + + /* + * Make sure no other interrupts besides halt are currently + * pending. Handling another interrupt could cause a crash due + * to the URBD and EPQH state. + */ + ifxusb_wreg(&hc_regs->hcint, ~hcintmsk.d32); + + /* + * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR + * even if the channel was already halted for some other + * reason. + */ + _ifxhc->halt_status = _halt_status; + + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + if (hcchar.b.chen == 0) + { + /* + * The channel is either already halted or it hasn't + * started yet. In DMA mode, the transfer may halt if + * it finishes normally or a condition occurs that + * requires driver intervention. Don't want to halt + * the channel again. In either Slave or DMA mode, + * it's possible that the transfer has been assigned + * to a channel, but not started yet when an URB is + * dequeued. Don't want to halt a channel that hasn't + * started yet. + */ + return; + } + } + + if (_ifxhc->halting) + { + /* + * A halt has already been issued for this channel. This might + * happen when a transfer is aborted by a higher level in + * the stack. + */ + #ifdef __DEBUG__ + IFX_PRINT("*** %s: Channel %d, _hc->halting already set ***\n", + __func__, _ifxhc->hc_num); + #endif + //ifxusb_dump_global_registers(_core_if); */ + //ifxusb_dump_host_registers(_core_if); */ + return; + } + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + /* == AVM/WK 20100709 halt channel only if enabled ==*/ + if (hcchar.b.chen) { + _ifxhc->halting = 1; + hcchar.b.chdis = 1; + + ifxusb_wreg(&hc_regs->hcchar, hcchar.d32); + _ifxhc->halt_status = _halt_status; + } + + IFX_DEBUGPL(DBG_HCDV, "%s: Channel %d\n" , __func__, _ifxhc->hc_num); + IFX_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n" , hcchar.d32); + IFX_DEBUGPL(DBG_HCDV, " halting: %d\n" , _ifxhc->halting); + IFX_DEBUGPL(DBG_HCDV, " halt_status: %d\n" , _ifxhc->halt_status); + + return; +} + +/*! + \brief Clears a host channel. + */ +void ifxhcd_hc_cleanup(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc) +{ + ifxusb_hc_regs_t *hc_regs; + + _ifxhc->xfer_started = 0; + /* + * Clear channel interrupt enables and any unhandled channel interrupt + * conditions. + */ + hc_regs = _core_if->hc_regs[_ifxhc->hc_num]; + ifxusb_wreg(&hc_regs->hcintmsk, 0); + ifxusb_wreg(&hc_regs->hcint, 0xFFFFFFFF); + + #ifdef __HC_XFER_TIMEOUT__ + del_timer(&_ifxhc->hc_xfer_timer); + #endif + #ifdef __DEBUG__ + { + hcchar_data_t hcchar; + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + if (hcchar.b.chdis) + IFX_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", __func__, _ifxhc->hc_num, hcchar.d32); + } + #endif +} + + + + + + + + +#ifdef __DEBUG__ + static void dump_urb_info(struct urb *_urb, char* _fn_name) + { + IFX_PRINT("%s, urb %p\n" , _fn_name, _urb); + IFX_PRINT(" Device address: %d\n", usb_pipedevice(_urb->pipe)); + IFX_PRINT(" Endpoint: %d, %s\n" , usb_pipeendpoint(_urb->pipe), + (usb_pipein(_urb->pipe) ? "IN" : "OUT")); + IFX_PRINT(" Endpoint type: %s\n", + ({ char *pipetype; + switch (usb_pipetype(_urb->pipe)) { + case PIPE_CONTROL: pipetype = "CONTROL"; break; + case PIPE_BULK: pipetype = "BULK"; break; + case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break; + case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break; + default: pipetype = "UNKNOWN"; break; + }; + pipetype; + })); + IFX_PRINT(" Speed: %s\n", + ({ char *speed; + switch (_urb->dev->speed) { + case USB_SPEED_HIGH: speed = "HIGH"; break; + case USB_SPEED_FULL: speed = "FULL"; break; + case USB_SPEED_LOW: speed = "LOW"; break; + default: speed = "UNKNOWN"; break; + }; + speed; + })); + IFX_PRINT(" Max packet size: %d\n", + usb_maxpacket(_urb->dev, _urb->pipe, usb_pipeout(_urb->pipe))); + IFX_PRINT(" Data buffer length: %d\n", _urb->transfer_buffer_length); + IFX_PRINT(" Transfer buffer: %p, Transfer DMA: %p\n", + _urb->transfer_buffer, (void *)_urb->transfer_dma); + IFX_PRINT(" Setup buffer: %p, Setup DMA: %p\n", + _urb->setup_packet, (void *)_urb->setup_dma); + IFX_PRINT(" Interval: %d\n", _urb->interval); + if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) + { + int i; + for (i = 0; i < _urb->number_of_packets; i++) + { + IFX_PRINT(" ISO Desc %d:\n", i); + IFX_PRINT(" offset: %d, length %d\n", + _urb->iso_frame_desc[i].offset, + _urb->iso_frame_desc[i].length); + } + } + } + + static void dump_channel_info(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh) + { + if (_epqh->hc != NULL) + { + ifxhcd_hc_t *hc = _epqh->hc; + struct list_head *item; + ifxhcd_epqh_t *epqh_item; + + ifxusb_hc_regs_t *hc_regs; + + hcchar_data_t hcchar; + hcsplt_data_t hcsplt; + hctsiz_data_t hctsiz; + uint32_t hcdma; + + hc_regs = _ifxhcd->core_if.hc_regs[hc->hc_num]; + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + hcsplt.d32 = ifxusb_rreg(&hc_regs->hcsplt); + hctsiz.d32 = ifxusb_rreg(&hc_regs->hctsiz); + hcdma = ifxusb_rreg(&hc_regs->hcdma); + + IFX_PRINT(" Assigned to channel %d:\n" , hc->hc_num); + IFX_PRINT(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32); + IFX_PRINT(" hctsiz 0x%08x, hcdma 0x%08x\n" , hctsiz.d32, hcdma); + IFX_PRINT(" dev_addr: %d, ep_num: %d, is_in: %d\n", + hc->dev_addr, hc->ep_num, hc->is_in); + IFX_PRINT(" ep_type: %d\n" , hc->ep_type); + IFX_PRINT(" max_packet_size: %d\n", hc->mps); + IFX_PRINT(" data_pid_start: %d\n" , hc->data_pid_start); + IFX_PRINT(" xfer_started: %d\n" , hc->xfer_started); + IFX_PRINT(" halt_status: %d\n" , hc->halt_status); + IFX_PRINT(" xfer_buff: %p\n" , hc->xfer_buff); + IFX_PRINT(" xfer_len: %d\n" , hc->xfer_len); + IFX_PRINT(" epqh: %p\n" , hc->epqh); + IFX_PRINT(" NP Active:\n"); + list_for_each(item, &_ifxhcd->epqh_np_active) + { + epqh_item = list_entry(item, ifxhcd_epqh_t, epqh_list_entry); + IFX_PRINT(" %p\n", epqh_item); + } + IFX_PRINT(" NP Ready:\n"); + list_for_each(item, &_ifxhcd->epqh_np_ready) + { + epqh_item = list_entry(item, ifxhcd_epqh_t, epqh_list_entry); + IFX_PRINT(" %p\n", epqh_item); + } + IFX_PRINT(" INTR Active:\n"); + list_for_each(item, &_ifxhcd->epqh_intr_active) + { + epqh_item = list_entry(item, ifxhcd_epqh_t, epqh_list_entry); + IFX_PRINT(" %p\n", epqh_item); + } + IFX_PRINT(" INTR Ready:\n"); + list_for_each(item, &_ifxhcd->epqh_intr_ready) + { + epqh_item = list_entry(item, ifxhcd_epqh_t, epqh_list_entry); + IFX_PRINT(" %p\n", epqh_item); + } + #ifdef __EN_ISOC__ + IFX_PRINT(" ISOC Active:\n"); + list_for_each(item, &_ifxhcd->epqh_isoc_active) + { + epqh_item = list_entry(item, ifxhcd_epqh_t, epqh_list_entry); + IFX_PRINT(" %p\n", epqh_item); + } + IFX_PRINT(" ISOC Ready:\n"); + list_for_each(item, &_ifxhcd->epqh_isoc_ready) + { + epqh_item = list_entry(item, ifxhcd_epqh_t, epqh_list_entry); + IFX_PRINT(" %p\n", epqh_item); + } + #endif + IFX_PRINT(" Standby:\n"); + list_for_each(item, &_ifxhcd->epqh_stdby) + { + epqh_item = list_entry(item, ifxhcd_epqh_t, epqh_list_entry); + IFX_PRINT(" %p\n", epqh_item); + } + } + } +#endif //__DEBUG__ + + +/*! + \brief This function writes a packet into the Tx FIFO associated with the Host + Channel. For a channel associated with a non-periodic EP, the non-periodic + Tx FIFO is written. For a channel associated with a periodic EP, the + periodic Tx FIFO is written. This function should only be called in Slave + mode. + + Upon return the xfer_buff and xfer_count fields in _hc are incremented by + then number of bytes written to the Tx FIFO. + */ + +#ifdef __ENABLE_DUMP__ + void ifxhcd_dump_state(ifxhcd_hcd_t *_ifxhcd) + { + int num_channels; + int i; + num_channels = _ifxhcd->core_if.params.host_channels; + IFX_PRINT("\n"); + IFX_PRINT("************************************************************\n"); + IFX_PRINT("HCD State:\n"); + IFX_PRINT(" Num channels: %d\n", num_channels); + for (i = 0; i < num_channels; i++) { + ifxhcd_hc_t *hc = &_ifxhcd->ifxhc[i]; + IFX_PRINT(" Channel %d:\n", hc->hc_num); + IFX_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n", + hc->dev_addr, hc->ep_num, hc->is_in); + IFX_PRINT(" speed: %d\n" , hc->speed); + IFX_PRINT(" ep_type: %d\n" , hc->ep_type); + IFX_PRINT(" mps: %d\n", hc->mps); + IFX_PRINT(" data_pid_start: %d\n" , hc->data_pid_start); + IFX_PRINT(" xfer_started: %d\n" , hc->xfer_started); + IFX_PRINT(" xfer_buff: %p\n" , hc->xfer_buff); + IFX_PRINT(" xfer_len: %d\n" , hc->xfer_len); + IFX_PRINT(" xfer_count: %d\n" , hc->xfer_count); + IFX_PRINT(" halting: %d\n" , hc->halting); + IFX_PRINT(" halt_status: %d\n" , hc->halt_status); + IFX_PRINT(" split: %d\n" , hc->split); + IFX_PRINT(" hub_addr: %d\n" , hc->hub_addr); + IFX_PRINT(" port_addr: %d\n" , hc->port_addr); + #ifdef __EN_ISOC__ + IFX_PRINT(" isoc_xact_pos: %d\n" , hc->isoc_xact_pos); + #endif + IFX_PRINT(" epqh: %p\n" , hc->epqh); + IFX_PRINT(" short_rw: %d\n" , hc->short_rw); + IFX_PRINT(" do_ping: %d\n" , hc->do_ping); + IFX_PRINT(" control_phase: %d\n" , hc->control_phase); + IFX_PRINT(" pkt_count_limit: %d\n", hc->epqh->pkt_count_limit); + IFX_PRINT(" start_pkt_count: %d\n" , hc->start_pkt_count); + } + IFX_PRINT("************************************************************\n"); + IFX_PRINT("\n"); + } +#endif //__ENABLE_DUMP__ + diff --git a/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxhcd.h b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxhcd.h new file mode 100644 index 0000000000..3a408513ce --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxhcd.h @@ -0,0 +1,628 @@ +/***************************************************************************** + ** FILE NAME : ifxhcd.h + ** PROJECT : IFX USB sub-system V3 + ** MODULES : IFX USB sub-system Host and Device driver + ** SRC VERSION : 1.0 + ** DATE : 1/Jan/2009 + ** AUTHOR : Chen, Howard + ** DESCRIPTION : This file contains the structures, constants, and interfaces for + ** the Host Contoller Driver (HCD). + ** + ** The Host Controller Driver (HCD) is responsible for translating requests + ** from the USB Driver into the appropriate actions on the IFXUSB controller. + ** It isolates the USBD from the specifics of the controller by providing an + ** API to the USBD. + ** FUNCTIONS : + ** COMPILER : gcc + ** REFERENCE : Synopsys DWC-OTG Driver 2.7 + ** COPYRIGHT : + ** Version Control Section ** + ** $Author$ + ** $Date$ + ** $Revisions$ + ** $Log$ Revision history +*****************************************************************************/ + +/*! + \defgroup IFXUSB_HCD HCD Interface + \ingroup IFXUSB_DRIVER_V3 + \brief The Host Controller Driver (HCD) is responsible for translating requests + from the USB Driver into the appropriate actions on the IFXUSB controller. + It isolates the USBD from the specifics of the controller by providing an + API to the USBD. + */ + + +/*! + \file ifxhcd.h + \ingroup IFXUSB_DRIVER_V3 + \brief This file contains the structures, constants, and interfaces for + the Host Contoller Driver (HCD). + */ + +#if !defined(__IFXHCD_H__) +#define __IFXHCD_H__ + +#include +#include + +#ifdef __USE_TIMER_4_SOF__ +#include +#endif +#include + +#include "ifxusb_cif.h" +#include "ifxusb_plat.h" + + + +/*! + \addtogroup IFXUSB_HCD + */ +/*@{*/ + +/* Phases for control transfers.*/ +typedef enum ifxhcd_control_phase { + IFXHCD_CONTROL_SETUP, + IFXHCD_CONTROL_DATA, + IFXHCD_CONTROL_STATUS +} ifxhcd_control_phase_e; + +/* Reasons for halting a host channel. */ +typedef enum ifxhcd_halt_status +{ + HC_XFER_NO_HALT_STATUS, // Initial + HC_XFER_COMPLETE, // Xact complete without error, upward + HC_XFER_URB_COMPLETE, // Xfer complete without error, short upward + HC_XFER_STALL, // HC stopped abnormally, upward/downward + HC_XFER_XACT_ERR, // HC stopped abnormally, upward + HC_XFER_FRAME_OVERRUN, // HC stopped abnormally, upward + HC_XFER_BABBLE_ERR, // HC stopped abnormally, upward + HC_XFER_AHB_ERR, // HC stopped abnormally, upward + HC_XFER_DATA_TOGGLE_ERR, + HC_XFER_URB_DEQUEUE, // HC stopper manually, downward + HC_XFER_NAK // HC stopped by nak monitor, downward +} ifxhcd_halt_status_e; + +struct ifxhcd_urbd; +struct ifxhcd_hc ; +struct ifxhcd_epqh ; +struct ifxhcd_hcd; + +/*! + \brief A URB Descriptor (URBD) holds the state of a bulk, control, + interrupt, or isochronous transfer. A single URBD is created for each URB + (of one of these types) submitted to the HCD. The transfer associated with + a URBD may require one or multiple transactions. + + A URBD is linked to a EP Queue Head, which is entered in either the + isoc, intr or non-periodic schedule for execution. When a URBD is chosen for + execution, some or all of its transactions may be executed. After + execution, the state of the URBD is updated. The URBD may be retired if all + its transactions are complete or if an error occurred. Otherwise, it + remains in the schedule so more transactions can be executed later. + */ +typedef struct ifxhcd_urbd { + struct list_head urbd_list_entry; // Hook for EPQH->urbd_list and ifxhcd->urbd_complete_list + struct urb *urb; /*!< URB for this transfer */ + //struct urb { + // struct list_head urb_list; + // struct list_head anchor_list; + // struct usb_anchor * anchor; + // struct usb_device * dev; + // struct usb_host_endpoint * ep; + // unsigned int pipe; + // int status; + // unsigned int transfer_flags; + // void * transfer_buffer; + // dma_addr_t transfer_dma; + // u32 transfer_buffer_length; + // u32 actual_length; + // unsigned char * setup_packet; + // dma_addr_t setup_dma; + // int start_frame; + // int number_of_packets; + // int interval; + // int error_count; + // void * context; + // usb_complete_t complete; + // struct usb_iso_packet_descriptor iso_frame_desc[0]; + //}; + //urb_list For use by current owner of the URB. + //anchor_list membership in the list of an anchor + //anchor to anchor URBs to a common mooring + //dev Identifies the USB device to perform the request. + //ep Points to the endpoint's data structure. Will + // eventually replace pipe. + //pipe Holds endpoint number, direction, type, and more. + // Create these values with the eight macros available; u + // sb_{snd,rcv}TYPEpipe(dev,endpoint), where the TYPE is + // "ctrl", "bulk", "int" or "iso". For example + // usb_sndbulkpipe or usb_rcvintpipe. Endpoint numbers + // range from zero to fifteen. Note that "in" endpoint two + // is a different endpoint (and pipe) from "out" endpoint + // two. The current configuration controls the existence, + // type, and maximum packet size of any given endpoint. + //status This is read in non-iso completion functions to get + // the status of the particular request. ISO requests + // only use it to tell whether the URB was unlinked; + // detailed status for each frame is in the fields of + // the iso_frame-desc. + //transfer_flags A variety of flags may be used to affect how URB + // submission, unlinking, or operation are handled. + // Different kinds of URB can use different flags. + // URB_SHORT_NOT_OK + // URB_ISO_ASAP + // URB_NO_TRANSFER_DMA_MAP + // URB_NO_SETUP_DMA_MAP + // URB_NO_FSBR + // URB_ZERO_PACKET + // URB_NO_INTERRUPT + //transfer_buffer This identifies the buffer to (or from) which the I/O + // request will be performed (unless URB_NO_TRANSFER_DMA_MAP + // is set). This buffer must be suitable for DMA; allocate it + // with kmalloc or equivalent. For transfers to "in" + // endpoints, contents of this buffer will be modified. This + // buffer is used for the data stage of control transfers. + //transfer_dma When transfer_flags includes URB_NO_TRANSFER_DMA_MAP, the + // device driver is saying that it provided this DMA address, + // which the host controller driver should use in preference + // to the transfer_buffer. + //transfer_buffer_length How big is transfer_buffer. The transfer may be broken + // up into chunks according to the current maximum packet size + // for the endpoint, which is a function of the configuration + // and is encoded in the pipe. When the length is zero, neither + // transfer_buffer nor transfer_dma is used. + //actual_length This is read in non-iso completion functions, and it tells + // how many bytes (out of transfer_buffer_length) were transferred. + // It will normally be the same as requested, unless either an error + // was reported or a short read was performed. The URB_SHORT_NOT_OK + // transfer flag may be used to make such short reads be reported + // as errors. + //setup_packet Only used for control transfers, this points to eight bytes of + // setup data. Control transfers always start by sending this data + // to the device. Then transfer_buffer is read or written, if needed. + //setup_dma For control transfers with URB_NO_SETUP_DMA_MAP set, the device + // driver has provided this DMA address for the setup packet. The + // host controller driver should use this in preference to setup_packet. + //start_frame Returns the initial frame for isochronous transfers. + //number_of_packets Lists the number of ISO transfer buffers. + //interval Specifies the polling interval for interrupt or isochronous transfers. + // The units are frames (milliseconds) for for full and low speed devices, + // and microframes (1/8 millisecond) for highspeed ones. + //error_count Returns the number of ISO transfers that reported errors. + //context For use in completion functions. This normally points to request-specific + // driver context. + //complete Completion handler. This URB is passed as the parameter to the completion + // function. The completion function may then do what it likes with the URB, + // including resubmitting or freeing it. + //iso_frame_desc[0] Used to provide arrays of ISO transfer buffers and to collect the transfer + // status for each buffer. + + struct ifxhcd_epqh *epqh; + // Actual data portion, not SETUP or STATUS in case of CTRL XFER + // DMA adjusted + uint8_t *setup_buff; /*!< Pointer to the entire transfer buffer. (CPU accessable)*/ + uint8_t *xfer_buff; /*!< Pointer to the entire transfer buffer. (CPU accessable)*/ + uint32_t xfer_len; /*!< Total number of bytes to transfer in this xfer. */ + unsigned is_in :1; + unsigned is_active:1; + + // For ALL XFER + uint8_t error_count; /*!< Holds the number of bus errors that have occurred for a transaction + within this transfer. + */ + /*== AVM/BC 20101111 Needed for URB Complete List ==*/ + int status; + // For ISOC XFER only + #ifdef __EN_ISOC__ + int isoc_frame_index; /*!< Index of the next frame descriptor for an isochronous transfer. A + frame descriptor describes the buffer position and length of the + data to be transferred in the next scheduled (micro)frame of an + isochronous transfer. It also holds status for that transaction. + The frame index starts at 0. + */ + // For SPLITed ISOC XFER only + uint8_t isoc_split_pos; /*!< Position of the ISOC split on full/low speed */ + uint16_t isoc_split_offset;/*!< Position of the ISOC split in the buffer for the current frame */ + #endif +} ifxhcd_urbd_t; + +/*! + \brief A EP Queue Head (EPQH) holds the static characteristics of an endpoint and + maintains a list of transfers (URBDs) for that endpoint. A EPQH structure may + be entered in either the isoc, intr or non-periodic schedule. + */ + +typedef struct ifxhcd_epqh { + struct list_head epqh_list_entry; // Hook for EP Queues + struct list_head urbd_list; /*!< List of URBDs for this EPQH. */ + struct ifxhcd_hc *hc; /*!< Host channel currently processing transfers for this EPQH. */ + struct ifxhcd_urbd *urbd; /*!< URBD currently assigned to a host channel for this EPQH. */ + struct usb_host_endpoint *sysep; + uint8_t ep_type; /*!< Endpoint type. One of the following values: + - IFXUSB_EP_TYPE_CTRL + - IFXUSB_EP_TYPE_ISOC + - IFXUSB_EP_TYPE_BULK + - IFXUSB_EP_TYPE_INTR + */ + uint16_t mps; /*!< wMaxPacketSize Field of Endpoint Descriptor. */ + + /* == AVM/WK 20100710 Fix - Use toggle of usbcore ==*/ + /*uint8_t data_toggle;*/ /*!< Determines the PID of the next data packet + One of the following values: + - IFXHCD_HC_PID_DATA0 + - IFXHCD_HC_PID_DATA1 + */ + uint8_t is_active; + + uint8_t pkt_count_limit; + #ifdef __EPQD_DESTROY_TIMEOUT__ + struct timer_list destroy_timer; + #endif + + uint16_t wait_for_sof; + uint8_t need_split; /*!< Full/low speed endpoint on high-speed hub requires split. */ + uint16_t interval; /*!< Interval between transfers in (micro)frames. (for INTR)*/ + + uint16_t period_counter; /*!< Interval between transfers in (micro)frames. */ + uint8_t period_do; + + uint8_t aligned_checked; + + #if defined(__UNALIGNED_BUFFER_ADJ__) + uint8_t using_aligned_setup; + uint8_t *aligned_setup; + uint8_t using_aligned_buf; + uint8_t *aligned_buf; + unsigned aligned_buf_len : 19; + #endif + + uint8_t *dump_buf; +} ifxhcd_epqh_t; + + +#if defined(__HC_XFER_TIMEOUT__) + struct ifxusb_core_if; + struct ifxhcd_hc; + typedef struct hc_xfer_info + { + struct ifxusb_core_if *core_if; + struct ifxhcd_hc *hc; + } hc_xfer_info_t; +#endif //defined(__HC_XFER_TIMEOUT__) + + +/*! + \brief Host channel descriptor. This structure represents the state of a single + host channel when acting in host mode. It contains the data items needed to + transfer packets to an endpoint via a host channel. + */ +typedef struct ifxhcd_hc +{ + struct list_head hc_list_entry ; // Hook to free hc + struct ifxhcd_epqh *epqh ; /*!< EP Queue Head for the transfer being processed by this channel. */ + + uint8_t hc_num ; /*!< Host channel number used for register address lookup */ + uint8_t *xfer_buff ; /*!< Pointer to the entire transfer buffer. */ + uint32_t xfer_count ; /*!< Number of bytes transferred so far. The offset of the begin of the buf */ + uint32_t xfer_len ; /*!< Total number of bytes to transfer in this xfer. */ + uint16_t start_pkt_count ; /*!< Packet count at start of transfer. Used to calculate the actual xfer size*/ + ifxhcd_halt_status_e halt_status; /*!< Reason for halting the host channel. */ + + unsigned dev_addr : 7; /*!< Device to access */ + unsigned ep_num : 4; /*!< EP to access */ + unsigned is_in : 1; /*!< EP direction. 0: OUT, 1: IN */ + unsigned speed : 2; /*!< EP speed. */ + unsigned ep_type : 2; /*!< Endpoint type. */ + unsigned mps :11; /*!< Max packet size in bytes */ + unsigned data_pid_start : 2; /*!< PID for initial transaction. */ + unsigned do_ping : 1; /*!< Set to 1 to indicate that a PING request should be issued on this + channel. If 0, process normally. + */ + + unsigned xfer_started : 1; /*!< Flag to indicate whether the transfer has been started. Set to 1 if + it has been started, 0 otherwise. + */ + unsigned halting : 1; /*!< Set to 1 if the host channel has been halted, but the core is not + finished flushing queued requests. Otherwise 0. + */ + unsigned short_rw : 1; /*!< When Tx, means termination needed. + When Rx, indicate Short Read */ + /* Split settings for the host channel */ + unsigned split : 2; /*!< Split: 0-Non Split, 1-SSPLIT, 2&3 CSPLIT */ + + /*== AVM/BC 20100701 - Workaround FullSpeed Interrupts with HiSpeed Hub ==*/ + unsigned nyet_count; + + /* nak monitor */ + unsigned nak_retry_r : 16; + unsigned nak_retry : 16; + #define nak_retry_max 40000 + unsigned nak_countdown : 8; + unsigned nak_countdown_r: 8; + #define nak_countdown_max 1 + + uint16_t wait_for_sof; + ifxhcd_control_phase_e control_phase; /*!< Current phase for control transfers (Setup, Data, or Status). */ + uint32_t ssplit_out_xfer_count; /*!< How many bytes transferred during SSPLIT OUT */ + #ifdef __DEBUG__ + uint32_t start_hcchar_val; + #endif + #ifdef __HC_XFER_TIMEOUT__ + hc_xfer_info_t hc_xfer_info; + struct timer_list hc_xfer_timer; + #endif + uint32_t hcchar; + + /* Split settings for the host channel */ + uint8_t hub_addr; /*!< Address of high speed hub */ + uint8_t port_addr; /*!< Port of the low/full speed device */ + #ifdef __EN_ISOC__ + uint8_t isoc_xact_pos; /*!< Split transaction position */ + #endif +} ifxhcd_hc_t; + + +/*! + \brief This structure holds the state of the HCD, including the non-periodic and + periodic schedules. + */ +typedef struct ifxhcd_hcd +{ + struct device *dev; + struct hc_driver hc_driver; + ifxusb_core_if_t core_if; /*!< Pointer to the core interface structure. */ + struct usb_hcd *syshcd; + + volatile union ifxhcd_internal_flags + { + uint32_t d32; + struct + { + unsigned port_connect_status_change : 1; + unsigned port_connect_status : 1; + unsigned port_reset_change : 1; + unsigned port_enable_change : 1; + unsigned port_suspend_change : 1; + unsigned port_over_current_change : 1; + unsigned reserved : 27; + } b; + } flags; /*!< Internal HCD Flags */ + + struct ifxhcd_hc ifxhc[MAX_EPS_CHANNELS]; /*!< Array of pointers to the host channel descriptors. Allows accessing + a host channel descriptor given the host channel number. This is + useful in interrupt handlers. + */ + struct list_head free_hc_list; /*!< Free host channels in the controller. This is a list of ifxhcd_hc_t items. */ + uint8_t *status_buf; /*!< Buffer to use for any data received during the status phase of a + control transfer. Normally no data is transferred during the status + phase. This buffer is used as a bit bucket. + */ + #define IFXHCD_STATUS_BUF_SIZE 64 + + struct list_head epqh_np_active; // with URBD, with HC + struct list_head epqh_np_ready; // with URBD, No HC + + struct list_head epqh_intr_active; // with URBD, with HC + struct list_head epqh_intr_ready; // with URBD, no pass, No HC + + #ifdef __EN_ISOC__ + struct list_head epqh_isoc_active; // with URBD, with HC + struct list_head epqh_isoc_ready; // with URBD, no pass, No HC + #endif + + /*== AVM/BC 20101111 URB Complete List ==*/ + struct list_head urbd_complete_list; + + struct list_head epqh_stdby; + + /* AVM/BC 20101111 flags removed */ + //unsigned process_channels_in_use : 1; + //unsigned select_eps_in_use : 1; + + struct tasklet_struct select_eps; /*!< Tasket to do a reset */ + uint32_t lastframe; + spinlock_t lock; +#ifdef __USE_TIMER_4_SOF__ + struct hrtimer hr_timer; +#endif +} ifxhcd_hcd_t; + +/* Gets the ifxhcd_hcd from a struct usb_hcd */ +static inline ifxhcd_hcd_t *syshcd_to_ifxhcd(struct usb_hcd *syshcd) +{ + return (ifxhcd_hcd_t *)(syshcd->hcd_priv[0]); +} + +/* Gets the struct usb_hcd that contains a ifxhcd_hcd_t. */ +static inline struct usb_hcd *ifxhcd_to_syshcd(ifxhcd_hcd_t *ifxhcd) +{ + return (struct usb_hcd *)(ifxhcd->syshcd); +} + +/*! \brief HCD Create/Destroy Functions */ +/*@{*/ + extern int ifxhcd_init (ifxhcd_hcd_t *_ifxhcd); + extern void ifxhcd_remove(ifxhcd_hcd_t *_ifxhcd); +/*@}*/ + +/*! \brief Linux HC Driver API Functions */ +/*@{*/ +extern int ifxhcd_start(struct usb_hcd *hcd); +extern void ifxhcd_stop (struct usb_hcd *hcd); +extern int ifxhcd_get_frame_number(struct usb_hcd *hcd); + + +/*! + \brief This function does the setup for a data transfer for a host channel and + starts the transfer. May be called in either Slave mode or DMA mode. In + Slave mode, the caller must ensure that there is sufficient space in the + request queue and Tx Data FIFO. + + For an OUT transfer in Slave mode, it loads a data packet into the + appropriate FIFO. If necessary, additional data packets will be loaded in + the Host ISR. + + For an IN transfer in Slave mode, a data packet is requested. The data + packets are unloaded from the Rx FIFO in the Host ISR. If necessary, + additional data packets are requested in the Host ISR. + + For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ + register along with a packet count of 1 and the channel is enabled. This + causes a single PING transaction to occur. Other fields in HCTSIZ are + simply set to 0 since no data transfer occurs in this case. + + For a PING transfer in DMA mode, the HCTSIZ register is initialized with + all the information required to perform the subsequent data transfer. In + addition, the Do Ping bit is set in the HCTSIZ register. In this case, the + controller performs the entire PING protocol, then starts the data + transfer. + + @param _ifxhc Information needed to initialize the host channel. The xfer_len + value may be reduced to accommodate the max widths of the XferSize and + PktCnt fields in the HCTSIZn register. The multi_count value may be changed + to reflect the final xfer_len value. + */ +extern void ifxhcd_hc_start(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc); + +//extern int ifxhcd_urb_enqueue(struct usb_hcd *_syshcd, struct usb_host_endpoint *_sysep, struct urb *_urb, gfp_t mem_flags); +//extern int ifxhcd_urb_dequeue(struct usb_hcd *_syshcd, struct urb *_urb); +extern irqreturn_t ifxhcd_irq(struct usb_hcd *_syshcd); +int ifxhcd_urb_enqueue( struct usb_hcd *_syshcd, + /*--- struct usb_host_endpoint *_sysep, Parameter im 2.6.28 entfallen ---*/ + struct urb *_urb, + gfp_t _mem_flags); +int ifxhcd_urb_dequeue( struct usb_hcd *_syshcd, + struct urb *_urb, int status /* Parameter neu in 2.6.28 */); + +extern void ifxhcd_endpoint_disable(struct usb_hcd *_syshcd, struct usb_host_endpoint *_sysep); + +extern int ifxhcd_hub_status_data(struct usb_hcd *_syshcd, char *_buf); +extern int ifxhcd_hub_control( struct usb_hcd *_syshcd, + u16 _typeReq, + u16 _wValue, + u16 _wIndex, + char *_buf, + u16 _wLength); + +/*@}*/ + +/*! \brief Transaction Execution Functions */ +/*@{*/ +extern void ifxhcd_complete_urb (ifxhcd_hcd_t *_ifxhcd, ifxhcd_urbd_t *_urbd, int _status); + +/*@}*/ + +/*! \brief Deferred Transaction Execution Functions */ +/*@{*/ + +/*== AVM/BC 20101111 URB Complete List ==*/ +extern void defer_ifxhcd_complete_urb (ifxhcd_hcd_t *_ifxhcd, ifxhcd_urbd_t *_urbd, int _status); + +/*! + \brief Clears the transfer state for a host channel. This function is normally + called after a transfer is done and the host channel is being released. + */ +extern void ifxhcd_hc_cleanup(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc); + +/*! + \brief Attempts to halt a host channel. This function should only be called in + Slave mode or to abort a transfer in either Slave mode or DMA mode. Under + normal circumstances in DMA mode, the controller halts the channel when the + transfer is complete or a condition occurs that requires application + intervention. + + In slave mode, checks for a free request queue entry, then sets the Channel + Enable and Channel Disable bits of the Host Channel Characteristics + register of the specified channel to intiate the halt. If there is no free + request queue entry, sets only the Channel Disable bit of the HCCHARn + register to flush requests for this channel. In the latter case, sets a + flag to indicate that the host channel needs to be halted when a request + queue slot is open. + + In DMA mode, always sets the Channel Enable and Channel Disable bits of the + HCCHARn register. The controller ensures there is space in the request + queue before submitting the halt request. + + Some time may elapse before the core flushes any posted requests for this + host channel and halts. The Channel Halted interrupt handler completes the + deactivation of the host channel. + */ +extern void ifxhcd_hc_halt(ifxusb_core_if_t *_core_if, + ifxhcd_hc_t *_ifxhc, + ifxhcd_halt_status_e _halt_status); + +/*! + \brief Prepares a host channel for transferring packets to/from a specific + endpoint. The HCCHARn register is set up with the characteristics specified + in _ifxhc. Host channel interrupts that may need to be serviced while this + transfer is in progress are enabled. + */ +extern void ifxhcd_hc_init(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc); + +/*! + \brief This function is called to handle the disconnection of host port. + */ +int32_t ifxhcd_disconnect(ifxhcd_hcd_t *_ifxhcd); +/*@}*/ + +/*! \brief Interrupt Handler Functions */ +/*@{*/ +extern irqreturn_t ifxhcd_oc_irq(int _irq, void *_dev); + +extern int32_t ifxhcd_handle_oc_intr(ifxhcd_hcd_t *_ifxhcd); +extern int32_t ifxhcd_handle_intr (ifxhcd_hcd_t *_ifxhcd); +/*@}*/ + + +/*! \brief Schedule Queue Functions */ +/*@{*/ +extern ifxhcd_epqh_t *ifxhcd_epqh_create (ifxhcd_hcd_t *_ifxhcd, struct urb *_urb); +extern void ifxhcd_epqh_free ( ifxhcd_epqh_t *_epqh); +extern void select_eps (ifxhcd_hcd_t *_ifxhcd); +extern void process_channels(ifxhcd_hcd_t *_ifxhcd); +extern void process_channels_sub(ifxhcd_hcd_t *_ifxhcd); +extern void complete_channel(ifxhcd_hcd_t *_ifxhcd, ifxhcd_hc_t *_ifxhc, ifxhcd_urbd_t *_urbd); +extern void ifxhcd_epqh_ready(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh); +extern void ifxhcd_epqh_active(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh); +extern void ifxhcd_epqh_idle(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh); +extern void ifxhcd_epqh_idle_periodic(ifxhcd_epqh_t *_epqh); +extern int ifxhcd_urbd_create (ifxhcd_hcd_t *_ifxhcd,struct urb *_urb); +/*@}*/ + +/*! \brief Gets the usb_host_endpoint associated with an URB. */ +static inline struct usb_host_endpoint *ifxhcd_urb_to_endpoint(struct urb *_urb) +{ + struct usb_device *dev = _urb->dev; + int ep_num = usb_pipeendpoint(_urb->pipe); + + return (usb_pipein(_urb->pipe))?(dev->ep_in[ep_num]):(dev->ep_out[ep_num]); +} + +/*! + * \brief Gets the endpoint number from a _bEndpointAddress argument. The endpoint is + * qualified with its direction (possible 32 endpoints per device). + */ +#define ifxhcd_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \ + ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4) + + +/* AVM/WK: not needed? + +extern struct usb_device *usb_alloc_dev (struct usb_device *parent, struct usb_bus *, unsigned port); +extern int usb_add_hcd (struct usb_hcd *syshcd, unsigned int irqnum, unsigned long irqflags); +extern void usb_remove_hcd (struct usb_hcd *syshcd); +extern struct usb_hcd *usb_create_hcd (const struct hc_driver *driver, struct device *dev, char *bus_name); +extern void usb_hcd_giveback_urb (struct usb_hcd *syshcd, struct urb *urb); +extern void usb_put_hcd (struct usb_hcd *syshcd); +extern long usb_calc_bus_time (int speed, int is_input, int isoc, int bytecount); + +*/ +/** Internal Functions */ +void ifxhcd_dump_state(ifxhcd_hcd_t *_ifxhcd); +extern char *syserr(int errno); + +/*@}*//*IFXUSB_HCD*/ + +#endif // __IFXHCD_H__ diff --git a/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxhcd_es.c b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxhcd_es.c new file mode 100644 index 0000000000..ef9e8c05ef --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxhcd_es.c @@ -0,0 +1,549 @@ +/***************************************************************************** + ** FILE NAME : ifxhcd_es.c + ** PROJECT : IFX USB sub-system V3 + ** MODULES : IFX USB sub-system Host and Device driver + ** SRC VERSION : 1.0 + ** DATE : 1/Jan/2009 + ** AUTHOR : Chen, Howard + ** DESCRIPTION : The file contain function to enable host mode USB-IF Electrical Test function. + *****************************************************************************/ + +/*! + \file ifxhcd_es.c + \ingroup IFXUSB_DRIVER_V3 + \brief The file contain function to enable host mode USB-IF Electrical Test function. +*/ + +#include +#include "ifxusb_version.h" + +#include + +#include + +#include + +#include "ifxusb_plat.h" +#include "ifxusb_regs.h" +#include "ifxusb_cif.h" +#include "ifxhcd.h" + + +#ifdef __WITH_HS_ELECT_TST__ + /* + * Quick and dirty hack to implement the HS Electrical Test + * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature. + * + * This code was copied from our userspace app "hset". It sends a + * Get Device Descriptor control sequence in two parts, first the + * Setup packet by itself, followed some time later by the In and + * Ack packets. Rather than trying to figure out how to add this + * functionality to the normal driver code, we just hijack the + * hardware, using these two function to drive the hardware + * directly. + */ + + + void do_setup(ifxusb_core_if_t *_core_if) + { + + ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; + ifxusb_host_global_regs_t *hc_global_regs = _core_if->host_global_regs; + ifxusb_hc_regs_t *hc_regs = _core_if->hc_regs[0]; + uint32_t *data_fifo = _core_if->data_fifo[0]; + + gint_data_t gintsts; + hctsiz_data_t hctsiz; + hcchar_data_t hcchar; + haint_data_t haint; + hcint_data_t hcint; + + + /* Enable HAINTs */ + ifxusb_wreg(&hc_global_regs->haintmsk, 0x0001); + + /* Enable HCINTs */ + ifxusb_wreg(&hc_regs->hcintmsk, 0x04a3); + + /* Read GINTSTS */ + gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* Read HAINT */ + haint.d32 = ifxusb_rreg(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = ifxusb_rreg(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + ifxusb_wreg(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + ifxusb_wreg(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + ifxusb_wreg(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ + gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* + * Send Setup packet (Get Device Descriptor) + */ + + /* Make sure channel is disabled */ + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + if (hcchar.b.chen) { + //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32); + hcchar.b.chdis = 1; + // hcchar.b.chen = 1; + ifxusb_wreg(&hc_regs->hcchar, hcchar.d32); + //sleep(1); + mdelay(1000); + + /* Read GINTSTS */ + gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* Read HAINT */ + haint.d32 = ifxusb_rreg(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = ifxusb_rreg(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + ifxusb_wreg(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + ifxusb_wreg(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + ifxusb_wreg(&global_regs->gintsts, gintsts.d32); + + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + //if (hcchar.b.chen) { + // fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32); + //} + } + + /* Set HCTSIZ */ + hctsiz.d32 = 0; + hctsiz.b.xfersize = 8; + hctsiz.b.pktcnt = 1; + hctsiz.b.pid = IFXUSB_HC_PID_SETUP; + ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32); + + /* Set HCCHAR */ + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + hcchar.b.eptype = IFXUSB_EP_TYPE_CTRL; + hcchar.b.epdir = 0; + hcchar.b.epnum = 0; + hcchar.b.mps = 8; + hcchar.b.chen = 1; + ifxusb_wreg(&hc_regs->hcchar, hcchar.d32); + + /* Fill FIFO with Setup data for Get Device Descriptor */ + ifxusb_wreg(data_fifo++, 0x01000680); + ifxusb_wreg(data_fifo++, 0x00080000); + + gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); + //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32); + + /* Wait for host channel interrupt */ + do { + gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); + } while (gintsts.b.hcintr == 0); + + //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32); + + /* Disable HCINTs */ + ifxusb_wreg(&hc_regs->hcintmsk, 0x0000); + + /* Disable HAINTs */ + ifxusb_wreg(&hc_global_regs->haintmsk, 0x0000); + + /* Read HAINT */ + haint.d32 = ifxusb_rreg(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = ifxusb_rreg(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + ifxusb_wreg(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + ifxusb_wreg(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + ifxusb_wreg(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ + gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + } + + void do_in_ack(ifxusb_core_if_t *_core_if) + { + + ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; + ifxusb_host_global_regs_t *hc_global_regs = _core_if->host_global_regs; + ifxusb_hc_regs_t *hc_regs = _core_if->hc_regs[0]; + uint32_t *data_fifo = _core_if->data_fifo[0]; + + gint_data_t gintsts; + hctsiz_data_t hctsiz; + hcchar_data_t hcchar; + haint_data_t haint; + hcint_data_t hcint; + grxsts_data_t grxsts; + + /* Enable HAINTs */ + ifxusb_wreg(&hc_global_regs->haintmsk, 0x0001); + + /* Enable HCINTs */ + ifxusb_wreg(&hc_regs->hcintmsk, 0x04a3); + + /* Read GINTSTS */ + gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* Read HAINT */ + haint.d32 = ifxusb_rreg(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = ifxusb_rreg(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + ifxusb_wreg(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + ifxusb_wreg(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + ifxusb_wreg(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ + gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* + * Receive Control In packet + */ + + /* Make sure channel is disabled */ + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + if (hcchar.b.chen) { + //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32); + hcchar.b.chdis = 1; + hcchar.b.chen = 1; + ifxusb_wreg(&hc_regs->hcchar, hcchar.d32); + //sleep(1); + mdelay(1000); + + /* Read GINTSTS */ + gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* Read HAINT */ + haint.d32 = ifxusb_rreg(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = ifxusb_rreg(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + ifxusb_wreg(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + ifxusb_wreg(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + ifxusb_wreg(&global_regs->gintsts, gintsts.d32); + + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + //if (hcchar.b.chen) { + // fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32); + //} + } + + /* Set HCTSIZ */ + hctsiz.d32 = 0; + hctsiz.b.xfersize = 8; + hctsiz.b.pktcnt = 1; + hctsiz.b.pid = IFXUSB_HC_PID_DATA1; + ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32); + + /* Set HCCHAR */ + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + hcchar.b.eptype = IFXUSB_EP_TYPE_CTRL; + hcchar.b.epdir = 1; + hcchar.b.epnum = 0; + hcchar.b.mps = 8; + hcchar.b.chen = 1; + ifxusb_wreg(&hc_regs->hcchar, hcchar.d32); + + gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); + //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32); + + /* Wait for receive status queue interrupt */ + do { + gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); + } while (gintsts.b.rxstsqlvl == 0); + + //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32); + + /* Read RXSTS */ + grxsts.d32 = ifxusb_rreg(&global_regs->grxstsp); + //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32); + + /* Clear RXSTSQLVL in GINTSTS */ + gintsts.d32 = 0; + gintsts.b.rxstsqlvl = 1; + ifxusb_wreg(&global_regs->gintsts, gintsts.d32); + + switch (grxsts.hb.pktsts) { + case IFXUSB_HSTS_DATA_UPDT: + /* Read the data into the host buffer */ + if (grxsts.hb.bcnt > 0) { + int i; + int word_count = (grxsts.hb.bcnt + 3) / 4; + + for (i = 0; i < word_count; i++) { + (void)ifxusb_rreg(data_fifo++); + } + } + + //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.hb.bcnt); + break; + + default: + //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n"); + break; + } + + gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); + //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32); + + /* Wait for receive status queue interrupt */ + do { + gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); + } while (gintsts.b.rxstsqlvl == 0); + + //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32); + + /* Read RXSTS */ + grxsts.d32 = ifxusb_rreg(&global_regs->grxstsp); + //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32); + + /* Clear RXSTSQLVL in GINTSTS */ + gintsts.d32 = 0; + gintsts.b.rxstsqlvl = 1; + ifxusb_wreg(&global_regs->gintsts, gintsts.d32); + + switch (grxsts.hb.pktsts) { + case IFXUSB_HSTS_XFER_COMP: + break; + + default: + //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n"); + break; + } + + gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); + //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32); + + /* Wait for host channel interrupt */ + do { + gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); + } while (gintsts.b.hcintr == 0); + + //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32); + + /* Read HAINT */ + haint.d32 = ifxusb_rreg(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = ifxusb_rreg(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + ifxusb_wreg(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + ifxusb_wreg(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + ifxusb_wreg(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ + gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + // usleep(100000); + // mdelay(100); + mdelay(1); + + /* + * Send handshake packet + */ + + /* Read HAINT */ + haint.d32 = ifxusb_rreg(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = ifxusb_rreg(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + ifxusb_wreg(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + ifxusb_wreg(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + ifxusb_wreg(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ + gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* Make sure channel is disabled */ + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + if (hcchar.b.chen) { + //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32); + hcchar.b.chdis = 1; + hcchar.b.chen = 1; + ifxusb_wreg(&hc_regs->hcchar, hcchar.d32); + //sleep(1); + mdelay(1000); + + /* Read GINTSTS */ + gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + + /* Read HAINT */ + haint.d32 = ifxusb_rreg(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = ifxusb_rreg(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + ifxusb_wreg(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + ifxusb_wreg(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + ifxusb_wreg(&global_regs->gintsts, gintsts.d32); + + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + //if (hcchar.b.chen) { + // fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32); + //} + } + + /* Set HCTSIZ */ + hctsiz.d32 = 0; + hctsiz.b.xfersize = 0; + hctsiz.b.pktcnt = 1; + hctsiz.b.pid = IFXUSB_HC_PID_DATA1; + ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32); + + /* Set HCCHAR */ + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + hcchar.b.eptype = IFXUSB_EP_TYPE_CTRL; + hcchar.b.epdir = 0; + hcchar.b.epnum = 0; + hcchar.b.mps = 8; + hcchar.b.chen = 1; + ifxusb_wreg(&hc_regs->hcchar, hcchar.d32); + + gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); + //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32); + + /* Wait for host channel interrupt */ + do { + gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); + } while (gintsts.b.hcintr == 0); + + //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32); + + /* Disable HCINTs */ + ifxusb_wreg(&hc_regs->hcintmsk, 0x0000); + + /* Disable HAINTs */ + ifxusb_wreg(&hc_global_regs->haintmsk, 0x0000); + + /* Read HAINT */ + haint.d32 = ifxusb_rreg(&hc_global_regs->haint); + //fprintf(stderr, "HAINT: %08x\n", haint.d32); + + /* Read HCINT */ + hcint.d32 = ifxusb_rreg(&hc_regs->hcint); + //fprintf(stderr, "HCINT: %08x\n", hcint.d32); + + /* Read HCCHAR */ + hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); + //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); + + /* Clear HCINT */ + ifxusb_wreg(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ + ifxusb_wreg(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ + ifxusb_wreg(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ + gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); + //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); + } +#endif //__WITH_HS_ELECT_TST__ + diff --git a/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxhcd_intr.c b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxhcd_intr.c new file mode 100644 index 0000000000..76fe602c76 --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxhcd_intr.c @@ -0,0 +1,3742 @@ +/***************************************************************************** + ** FILE NAME : ifxhcd_intr.c + ** PROJECT : IFX USB sub-system V3 + ** MODULES : IFX USB sub-system Host and Device driver + ** SRC VERSION : 1.0 + ** DATE : 1/Jan/2009 + ** AUTHOR : Chen, Howard + ** DESCRIPTION : This file contains the implementation of the HCD Interrupt handlers. + *****************************************************************************/ + +/*! + \file ifxhcd_intr.c + \ingroup IFXUSB_DRIVER_V3 + \brief This file contains the implementation of the HCD Interrupt handlers. +*/ + + +#include +#include "ifxusb_version.h" + +#include "ifxusb_plat.h" +#include "ifxusb_regs.h" +#include "ifxusb_cif.h" + +#include "ifxhcd.h" + +/* AVM/WK 20100520*/ +#ifdef __EN_ISOC__ +#error AVM/WK: CONFIG_USB_HOST_IFX_WITH_ISO currently not supported! +#endif + +/* Macro used to clear one channel interrupt */ +#define clear_hc_int(_hc_regs_,_intr_) \ + do { \ + hcint_data_t hcint_clear = {.d32 = 0}; \ + hcint_clear.b._intr_ = 1; \ + ifxusb_wreg(&((_hc_regs_)->hcint), hcint_clear.d32); \ + } while (0) + +/* + * Macro used to disable one channel interrupt. Channel interrupts are + * disabled when the channel is halted or released by the interrupt handler. + * There is no need to handle further interrupts of that type until the + * channel is re-assigned. In fact, subsequent handling may cause crashes + * because the channel structures are cleaned up when the channel is released. + */ +#define disable_hc_int(_hc_regs_,_intr_) \ + do { \ + hcint_data_t hcintmsk = {.d32 = 0}; \ + hcintmsk.b._intr_ = 1; \ + ifxusb_mreg(&((_hc_regs_)->hcintmsk), hcintmsk.d32, 0); \ + } while (0) + +#define enable_hc_int(_hc_regs_,_intr_) \ + do { \ + hcint_data_t hcintmsk = {.d32 = 0}; \ + hcintmsk.b._intr_ = 1; \ + ifxusb_mreg(&((_hc_regs_)->hcintmsk),0, hcintmsk.d32); \ + } while (0) + +/* + * Save the starting data toggle for the next transfer. The data toggle is + * saved in the QH for non-control transfers and it's saved in the QTD for + * control transfers. + */ +uint8_t read_data_toggle(ifxusb_hc_regs_t *_hc_regs) +{ + hctsiz_data_t hctsiz; + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + return(hctsiz.b.pid); +} + + +static void release_channel_dump(ifxhcd_hc_t *ifxhc, + struct urb *urb, + ifxhcd_epqh_t *epqh, + ifxhcd_urbd_t *urbd, + ifxhcd_halt_status_e halt_status) +{ + #ifdef __DEBUG__ + printk(KERN_INFO); + switch (halt_status) + { + case HC_XFER_NO_HALT_STATUS: + printk("HC_XFER_NO_HALT_STATUS");break; + case HC_XFER_URB_COMPLETE: + printk("HC_XFER_URB_COMPLETE");break; + case HC_XFER_AHB_ERR: + printk("HC_XFER_AHB_ERR");break; + case HC_XFER_STALL: + printk("HC_XFER_STALL");break; + case HC_XFER_BABBLE_ERR: + printk("HC_XFER_BABBLE_ERR");break; + case HC_XFER_XACT_ERR: + printk("HC_XFER_XACT_ERR");break; + case HC_XFER_URB_DEQUEUE: + printk("HC_XFER_URB_DEQUEUE");break; + case HC_XFER_FRAME_OVERRUN: + printk("HC_XFER_FRAME_OVERRUN");break; + case HC_XFER_DATA_TOGGLE_ERR: + printk("HC_XFER_DATA_TOGGLE_ERR");break; + case HC_XFER_NAK: + printk("HC_XFER_NAK");break; + case HC_XFER_COMPLETE: + printk("HC_XFER_COMPLETE");break; + default: + printk("KNOWN");break; + } + if(ifxhc) + printk("Ch %d %s%s S%d " , ifxhc->hc_num + ,(ifxhc->ep_type == IFXUSB_EP_TYPE_CTRL)?"CTRL-": + ((ifxhc->ep_type == IFXUSB_EP_TYPE_BULK)?"BULK-": + ((ifxhc->ep_type == IFXUSB_EP_TYPE_INTR)?"INTR-": + ((ifxhc->ep_type == IFXUSB_EP_TYPE_ISOC)?"ISOC-":"????" + ) + ) + ) + ,(ifxhc->is_in)?"IN":"OUT" + ,(ifxhc->split) + ); + else + printk(" [NULL HC] "); + printk("urb=%p epqh=%p urbd=%p\n",urb,epqh,urbd); + + if(urb) + { + printk(KERN_INFO " Device address: %d\n", usb_pipedevice(urb->pipe)); + printk(KERN_INFO " Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe), + (usb_pipein(urb->pipe) ? "IN" : "OUT")); + printk(KERN_INFO " Endpoint type: %s\n", + ({char *pipetype; + switch (usb_pipetype(urb->pipe)) { + case PIPE_CONTROL: pipetype = "CTRL"; break; + case PIPE_BULK: pipetype = "BULK"; break; + case PIPE_INTERRUPT: pipetype = "INTR"; break; + case PIPE_ISOCHRONOUS: pipetype = "ISOC"; break; + default: pipetype = "????"; break; + }; pipetype;})); + printk(KERN_INFO " Speed: %s\n", + ({char *speed; + switch (urb->dev->speed) { + case USB_SPEED_HIGH: speed = "HS"; break; + case USB_SPEED_FULL: speed = "FS"; break; + case USB_SPEED_LOW: speed = "LS"; break; + default: speed = "????"; break; + }; speed;})); + printk(KERN_INFO " Max packet size: %d\n", + usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); + printk(KERN_INFO " Data buffer length: %d\n", urb->transfer_buffer_length); + printk(KERN_INFO " Transfer buffer: %p, Transfer DMA: %p\n", + urb->transfer_buffer, (void *)urb->transfer_dma); + printk(KERN_INFO " Setup buffer: %p, Setup DMA: %p\n", + urb->setup_packet, (void *)urb->setup_dma); + printk(KERN_INFO " Interval: %d\n", urb->interval); + switch (urb->status) + { + case HC_XFER_NO_HALT_STATUS: + printk(KERN_INFO " STATUS:HC_XFER_NO_HALT_STATUS\n");break; + case HC_XFER_URB_COMPLETE: + printk(KERN_INFO " STATUS:HC_XFER_URB_COMPLETE\n");break; + case HC_XFER_AHB_ERR: + printk(KERN_INFO " STATUS:HC_XFER_AHB_ERR\n");break; + case HC_XFER_STALL: + printk(KERN_INFO " STATUS:HC_XFER_STALL\n");break; + case HC_XFER_BABBLE_ERR: + printk(KERN_INFO " STATUS:HC_XFER_BABBLE_ERR\n");break; + case HC_XFER_XACT_ERR: + printk(KERN_INFO " STATUS:HC_XFER_XACT_ERR\n");break; + case HC_XFER_URB_DEQUEUE: + printk(KERN_INFO " STATUS:HC_XFER_URB_DEQUEUE\n");break; + case HC_XFER_FRAME_OVERRUN: + printk(KERN_INFO " STATUS:HC_XFER_FRAME_OVERRUN\n");break; + case HC_XFER_DATA_TOGGLE_ERR: + printk(KERN_INFO " STATUS:HC_XFER_DATA_TOGGLE_ERR\n");break; + case HC_XFER_COMPLETE: + printk(KERN_INFO " STATUS:HC_XFER_COMPLETE\n");break; + default: + printk(KERN_INFO " STATUS:KNOWN\n");break; + } + } + #endif +} + + +static void release_channel(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxhcd_halt_status_e _halt_status) +{ + ifxusb_hc_regs_t *hc_regs = _ifxhcd->core_if.hc_regs[_ifxhc->hc_num]; + struct urb *urb = NULL; + ifxhcd_epqh_t *epqh = NULL; + ifxhcd_urbd_t *urbd = NULL; + + IFX_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d\n", + __func__, _ifxhc->hc_num, _halt_status); + + epqh=_ifxhc->epqh; + + if(!epqh) + IFX_ERROR("%s epqh=null\n",__func__); + else + { + urbd=epqh->urbd; + if(!urbd) + IFX_ERROR("%s urbd=null\n",__func__); + else + { + urb=urbd->urb; + if(!urb) + IFX_ERROR("%s urb =null\n",__func__); + else { + /* == AVM/WK 20100710 Fix - Use toggle of usbcore ==*/ + unsigned toggle = (read_data_toggle(hc_regs) == IFXUSB_HC_PID_DATA0)? 0: 1; + usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe), usb_pipeout(urb->pipe), toggle); + } + } + //epqh->data_toggle = read_data_toggle(hc_regs); + + } + + switch (_halt_status) + { + case HC_XFER_NO_HALT_STATUS: + IFX_ERROR("%s: No halt_status, channel %d\n", __func__, _ifxhc->hc_num); + break; + case HC_XFER_COMPLETE: + IFX_ERROR("%s: Inavalid halt_status HC_XFER_COMPLETE, channel %d\n", __func__, _ifxhc->hc_num); + break; + case HC_XFER_URB_COMPLETE: + case HC_XFER_URB_DEQUEUE: + case HC_XFER_AHB_ERR: + case HC_XFER_XACT_ERR: + case HC_XFER_FRAME_OVERRUN: + if(urbd && urb) { + /* == 20110803 AVM/WK FIX set status, if still in progress == */ + if (urb->status == -EINPROGRESS) { + switch (_halt_status) { + case HC_XFER_URB_COMPLETE: + urb->status = 0; + break; + case HC_XFER_URB_DEQUEUE: + urb->status = -ECONNRESET; + break; + case HC_XFER_AHB_ERR: + case HC_XFER_XACT_ERR: + case HC_XFER_FRAME_OVERRUN: + urb->status = -EPROTO; + break; + default: + break; + } + } + /*== AVM/BC 20101111 Deferred Complete ==*/ + defer_ifxhcd_complete_urb(_ifxhcd, urbd, urb->status); + } + else + { + IFX_WARN("WARNING %s():%d urbd=%p urb=%p\n",__func__,__LINE__,urbd,urb); + release_channel_dump(_ifxhc,urb,epqh,urbd,_halt_status); + } + if(epqh) + ifxhcd_epqh_idle(_ifxhcd, epqh); + else + { + IFX_WARN("WARNING %s():%d epqh=%p\n",__func__,__LINE__,epqh); + release_channel_dump(_ifxhc,urb,epqh,urbd,_halt_status); + } + + list_add_tail(&_ifxhc->hc_list_entry, &_ifxhcd->free_hc_list); + ifxhcd_hc_cleanup(&_ifxhcd->core_if, _ifxhc); + break; + case HC_XFER_STALL: + release_channel_dump(_ifxhc,urb,epqh,urbd,_halt_status); + if(urbd) + /*== AVM/BC 20101111 Deferred Complete ==*/ + defer_ifxhcd_complete_urb(_ifxhcd, urbd, -EPIPE); + else + IFX_WARN("WARNING %s():%d urbd=%p urb=%p\n",__func__,__LINE__,urbd,urb); + if(epqh) + { +// epqh->data_toggle = 0; + ifxhcd_epqh_idle(_ifxhcd, epqh); + } + else + IFX_WARN("WARNING %s():%d epqh=%p\n",__func__,__LINE__,epqh); + list_add_tail(&_ifxhc->hc_list_entry, &_ifxhcd->free_hc_list); + ifxhcd_hc_cleanup(&_ifxhcd->core_if, _ifxhc); + break; + case HC_XFER_NAK: + release_channel_dump(_ifxhc,urb,epqh,urbd,_halt_status); + if(urbd) + { + //ifxhcd_complete_urb(_ifxhcd, urbd, -ETIMEDOUT); + urb->status = 0; + /*== AVM/BC 20101111 Deferred Complete ==*/ + defer_ifxhcd_complete_urb(_ifxhcd, urbd, urb->status); + } + else + IFX_WARN("WARNING %s():%d urbd=%p urb=%p\n",__func__,__LINE__,urbd,urb); + if(epqh) + ifxhcd_epqh_idle(_ifxhcd, epqh); + else + IFX_WARN("WARNING %s():%d epqh=%p\n",__func__,__LINE__,epqh); + list_add_tail(&_ifxhc->hc_list_entry, &_ifxhcd->free_hc_list); + ifxhcd_hc_cleanup(&_ifxhcd->core_if, _ifxhc); + break; + case HC_XFER_BABBLE_ERR: + case HC_XFER_DATA_TOGGLE_ERR: + release_channel_dump(_ifxhc,urb,epqh,urbd,_halt_status); + if(urbd) + /*== AVM/BC 20101111 Deferred Complete ==*/ + defer_ifxhcd_complete_urb(_ifxhcd, urbd, -EOVERFLOW); + else + IFX_WARN("WARNING %s():%d urbd=%p urb=%p\n",__func__,__LINE__,urbd,urb); + if(epqh) + ifxhcd_epqh_idle(_ifxhcd, epqh); + else + IFX_WARN("WARNING %s():%d epqh=%p\n",__func__,__LINE__,epqh); + list_add_tail(&_ifxhc->hc_list_entry, &_ifxhcd->free_hc_list); + ifxhcd_hc_cleanup(&_ifxhcd->core_if, _ifxhc); + break; + } + select_eps(_ifxhcd); +} + +/* + * Updates the state of the URB after a Transfer Complete interrupt on the + * host channel. Updates the actual_length field of the URB based on the + * number of bytes transferred via the host channel. Sets the URB status + * if the data transfer is finished. + * + * @return 1 if the data transfer specified by the URB is completely finished, + * 0 otherwise. + */ +static int update_urb_state_xfer_comp(ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + struct urb *_urb, + ifxhcd_urbd_t *_urbd) +{ + int xfer_done = 0; + + if (_ifxhc->is_in) + { + hctsiz_data_t hctsiz; + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + _urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); + if ((hctsiz.b.xfersize != 0) || (_urb->actual_length >= _urb->transfer_buffer_length)) + { + xfer_done = 1; + _urb->status = 0; + /* 20110805 AVM/WK Workaround: catch overflow error here, hardware does not */ + if (_urb->actual_length > _urb->transfer_buffer_length) { + _urb->status = -EOVERFLOW; + } + #if 0 + if (_urb->actual_length < _urb->transfer_buffer_length && _urb->transfer_flags & URB_SHORT_NOT_OK) + _urb->status = -EREMOTEIO; + #endif + } + + } + else + { + if (_ifxhc->split) + _urb->actual_length += _ifxhc->ssplit_out_xfer_count; + else + _urb->actual_length += _ifxhc->xfer_len; + + if (_urb->actual_length >= _urb->transfer_buffer_length) + { + /*== AVM/BC WK 20110421 ZERO PACKET Workaround ==*/ + if ((_ifxhc->short_rw == 1) && ( _ifxhc->xfer_len > 0) && ( _ifxhc->xfer_len % _ifxhc->mps == 0 )) + { + _ifxhc->short_rw = 0; + //Transfer not finished. Another iteration for ZLP. + } + else + { + xfer_done = 1; + } + _urb->status = 0; + } + } + + #ifdef __DEBUG__ + { + hctsiz_data_t hctsiz; + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + IFX_DEBUGPL(DBG_HCDV, "IFXUSB: %s: %s, channel %d\n", + __func__, (_ifxhc->is_in ? "IN" : "OUT"), _ifxhc->hc_num); + IFX_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", _ifxhc->xfer_len); + IFX_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n", hctsiz.b.xfersize); + IFX_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n", + _urb->transfer_buffer_length); + IFX_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", _urb->actual_length); + } + #endif + return xfer_done; +} + +/*== AVM/BC 20101111 Function called with Lock ==*/ + +void complete_channel(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxhcd_urbd_t *_urbd) +{ + ifxusb_hc_regs_t *hc_regs = _ifxhcd->core_if.hc_regs[_ifxhc->hc_num]; + struct urb *urb = NULL; + ifxhcd_epqh_t *epqh = NULL; + int urb_xfer_done; + + IFX_DEBUGPL(DBG_HCD, "--Complete Channel %d : \n", _ifxhc->hc_num); + + if(!_urbd) + { + IFX_ERROR("ERROR %s():%d urbd=%p\n",__func__,__LINE__,_urbd); + return; + } + + urb = _urbd->urb; + epqh = _urbd->epqh; + + if(!urb || !epqh) + { + IFX_ERROR("ERROR %s():%d urb=%p epqh=%p\n",__func__,__LINE__,urb,epqh); + return; + } + + _ifxhc->do_ping=0; + + if (_ifxhc->split) + _ifxhc->split = 1; + + switch (epqh->ep_type) + { + case IFXUSB_EP_TYPE_CTRL: + switch (_ifxhc->control_phase) + { + case IFXHCD_CONTROL_SETUP: + IFX_DEBUGPL(DBG_HCDV, " Control setup transaction done\n"); + if (_urbd->xfer_len > 0) + { + _ifxhc->control_phase = IFXHCD_CONTROL_DATA; + _ifxhc->is_in = _urbd->is_in; + _ifxhc->xfer_len = _urbd->xfer_len; + #if defined(__UNALIGNED_BUFFER_ADJ__) + if(epqh->using_aligned_buf) + _ifxhc->xfer_buff = epqh->aligned_buf; + else + #endif + _ifxhc->xfer_buff = _urbd->xfer_buff; + } + else + { + _ifxhc->control_phase = IFXHCD_CONTROL_STATUS; + _ifxhc->is_in = 1; + _ifxhc->xfer_len = 0; + _ifxhc->xfer_buff = _ifxhcd->status_buf; + } + if(_ifxhc->is_in) + _ifxhc->short_rw =0; + else + _ifxhc->short_rw =(urb->transfer_flags & URB_ZERO_PACKET)?1:0; + _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1; + _ifxhc->xfer_count = 0; + _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; + /*== AVM/BC 20101111 Lock not needed ==*/ + process_channels_sub(_ifxhcd); + break; + case IFXHCD_CONTROL_DATA: + urb_xfer_done = update_urb_state_xfer_comp(_ifxhc, hc_regs, urb, _urbd); + if (urb_xfer_done) + { + _ifxhc->control_phase = IFXHCD_CONTROL_STATUS; + _ifxhc->is_in = (_urbd->is_in)?0:1; + _ifxhc->xfer_len = 0; + _ifxhc->xfer_count = 0; + _ifxhc->xfer_buff = _ifxhcd->status_buf; + _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; + _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1; + if(_ifxhc->is_in) + _ifxhc->short_rw =0; + else + _ifxhc->short_rw =1; + } + else // continue + { + _ifxhc->xfer_len = _urbd->xfer_len - urb->actual_length; + _ifxhc->xfer_count = urb->actual_length; + _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; + _ifxhc->data_pid_start = read_data_toggle(hc_regs); + } + /*== AVM/BC 20101111 Lock not needed ==*/ + process_channels_sub(_ifxhcd); + break; + case IFXHCD_CONTROL_STATUS: + if (urb->status == -EINPROGRESS) + urb->status = 0; + release_channel(_ifxhcd,_ifxhc,HC_XFER_URB_COMPLETE); + break; + } + break; + case IFXUSB_EP_TYPE_BULK: + IFX_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n"); + urb_xfer_done = update_urb_state_xfer_comp(_ifxhc, hc_regs, urb, _urbd); + if (urb_xfer_done) + release_channel(_ifxhcd,_ifxhc,HC_XFER_URB_COMPLETE); + else + { + _ifxhc->xfer_len = _urbd->xfer_len - urb->actual_length; + _ifxhc->xfer_count = urb->actual_length; + _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; + _ifxhc->data_pid_start = read_data_toggle(hc_regs); + /*== AVM/BC 20101111 Lock not needed ==*/ + process_channels_sub(_ifxhcd); + } + break; + case IFXUSB_EP_TYPE_INTR: + urb_xfer_done = update_urb_state_xfer_comp(_ifxhc, hc_regs, urb, _urbd); + release_channel(_ifxhcd,_ifxhc,HC_XFER_URB_COMPLETE); + break; + case IFXUSB_EP_TYPE_ISOC: +// if (_urbd->isoc_split_pos == IFXUSB_HCSPLIT_XACTPOS_ALL) +// halt_status = update_isoc_urb_state(_ifxhcd, _ifxhc, hc_regs, _urbd, HC_XFER_COMPLETE); +// complete_periodic_xfer(_ifxhcd, _ifxhc, hc_regs, _urbd, halt_status); + urb_xfer_done = update_urb_state_xfer_comp(_ifxhc, hc_regs, urb, _urbd); + release_channel(_ifxhcd,_ifxhc,HC_XFER_URB_COMPLETE); + break; + } +} + + + +void showint(uint32_t val_hcint + ,uint32_t val_hcintmsk + ,uint32_t val_hctsiz) +{ +#ifdef __DEBUG__ + hcint_data_t hcint = {.d32 = val_hcint}; + hcint_data_t hcintmsk = {.d32 = val_hcintmsk}; + + printk(KERN_INFO " WITH FLAG: Sz:%08x I:%08X/M:%08X %s%s%s%s%s%s%s%s%s%s\n" + ,val_hctsiz,hcint.d32 ,hcintmsk.d32 + ,(hcint.b.datatglerr || hcintmsk.b.datatglerr)? + ( + (hcint.b.datatglerr && hcintmsk.b.datatglerr)?"datatglerr[*/*] ": + ( + (hcint.b.datatglerr)?"datatglerr[*/] ":"datatglerr[/*] " + ) + ) + :"" + ,(hcint.b.frmovrun || hcintmsk.b.frmovrun)? + ( + (hcint.b.frmovrun && hcintmsk.b.frmovrun)?"frmovrun[*/*] ": + ( + (hcint.b.frmovrun)?"frmovrun[*/] ":"frmovrun[/*] " + ) + ) + :"" + ,(hcint.b.bblerr || hcintmsk.b.bblerr)? + ( + (hcint.b.bblerr && hcintmsk.b.bblerr)?"bblerr[*/*] ": + ( + (hcint.b.bblerr)?"bblerr[*/] ":"bblerr[/*] " + ) + ) + :"" + ,(hcint.b.xacterr || hcintmsk.b.xacterr)? + ( + (hcint.b.xacterr && hcintmsk.b.xacterr)?"xacterr[*/*] ": + ( + (hcint.b.xacterr)?"xacterr[*/] ":"xacterr[/*] " + ) + ) + :"" + ,(hcint.b.nyet || hcintmsk.b.nyet)? + ( + (hcint.b.nyet && hcintmsk.b.nyet)?"nyet[*/*] ": + ( + (hcint.b.nyet)?"nyet[*/] ":"nyet[/*] " + ) + ) + :"" + ,(hcint.b.nak || hcintmsk.b.nak)? + ( + (hcint.b.nak && hcintmsk.b.nak)?"nak[*/*] ": + ( + (hcint.b.nak)?"nak[*/] ":"nak[/*] " + ) + ) + :"" + ,(hcint.b.ack || hcintmsk.b.ack)? + ( + (hcint.b.ack && hcintmsk.b.ack)?"ack[*/*] ": + ( + (hcint.b.ack)?"ack[*/] ":"ack[/*] " + ) + ) + :"" + ,(hcint.b.stall || hcintmsk.b.stall)? + ( + (hcint.b.stall && hcintmsk.b.stall)?"stall[*/*] ": + ( + (hcint.b.stall)?"stall[*/] ":"stall[/*] " + ) + ) + :"" + ,(hcint.b.ahberr || hcintmsk.b.ahberr)? + ( + (hcint.b.ahberr && hcintmsk.b.ahberr)?"ahberr[*/*] ": + ( + (hcint.b.ahberr)?"ahberr[*/] ":"ahberr[/*] " + ) + ) + :"" + ,(hcint.b.xfercomp || hcintmsk.b.xfercomp)? + ( + (hcint.b.xfercomp && hcintmsk.b.xfercomp)?"xfercomp[*/*] ": + ( + (hcint.b.xfercomp)?"xfercomp[*/] ":"xfercomp[/*] " + ) + ) + :"" + ); +#endif +} + + +extern void ifxhcd_hc_dumb_rx(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc,uint8_t *dump_buf); + +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +static int32_t chhltd_ctrlbulk_rx_nonsplit(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + hcint_data_t hcint; + hcint_data_t hcintmsk; + hctsiz_data_t hctsiz; + + hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); + hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nak); + disable_hc_int(_hc_regs,nyet); + _ifxhc->do_ping = 0; + + if(_ifxhc->halt_status == HC_XFER_NAK) + { + if(_ifxhc->nak_retry_r) + { + _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); + _ifxhc->nak_retry--; + if(_ifxhc->nak_retry) + { + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + _ifxhc->data_pid_start = read_data_toggle(_hc_regs); + _ifxhc->wait_for_sof = 1; + _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + else + { + _ifxhc->wait_for_sof = 0; + release_channel(_ifxhcd, _ifxhc, _ifxhc->halt_status); + } + } + else + { + _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + _ifxhc->data_pid_start = read_data_toggle(_hc_regs); + _ifxhc->wait_for_sof = 1; + _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + return 1; + } + + if (hcint.b.xfercomp) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + complete_channel(_ifxhcd, _ifxhc, _urbd); + return 1; + } + else if (hcint.b.stall) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + // ZLP shortcut + #if 0 + if(hctsiz.b.pktcnt==0) + complete_channel(_ifxhcd, _ifxhc, _urbd); + else + #endif + { + // Stall FIFO compensation. + #if 0 + int sz1,sz2; + sz2=_ifxhc->start_pkt_count - hctsiz.b.pktcnt; + sz2*=_ifxhc->mps; + sz1=_ifxhc->xfer_len - hctsiz.b.xfersize; + sz2-=sz1; + if(sz2) + ifxhcd_hc_dumb_rx(&_ifxhcd->core_if, _ifxhc,_ifxhc->epqh->dump_buf); + #endif + _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); + release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); + } + return 1; + } + else if (hcint.b.bblerr) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + + // ZLP shortcut + #if 0 + if(hctsiz.b.pktcnt==0) + complete_channel(_ifxhcd, _ifxhc, _urbd); + else + #endif + _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); + release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); + return 1; + } + else if (hcint.b.xacterr) + { + // ZLP shortcut + #if 1 + if(hctsiz.b.pktcnt==0) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + complete_channel(_ifxhcd, _ifxhc, _urbd); + } + else + #endif + { + _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + _ifxhc->data_pid_start = read_data_toggle(_hc_regs); + + /* 20110803 AVM/WK FIX: Reset error count on any handshake */ + if (hcint.b.nak || hcint.b.nyet || hcint.b.ack) { + _urbd->error_count = 1; + } else { + _urbd->error_count++; + } + + if (_urbd->error_count >= 3) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); + } + else + { + _ifxhc->wait_for_sof = 1; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + } + return 1; + } + else if(hcint.b.datatglerr ) + { + _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); + #if 1 + if(_ifxhc->data_pid_start == IFXUSB_HC_PID_DATA0) + _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1; + else + _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0; + _ifxhc->wait_for_sof = 1; + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + #else + release_channel(_ifxhcd, _ifxhc, HC_XFER_DATA_TOGGLE_ERR); + #endif + return 1; + } + else if(hcint.b.frmovrun ) + { +IFX_WARN("%s() %d Warning CTRLBULK IN SPLIT0 FRMOVRUN [should be Period only]\n",__func__,__LINE__); +showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN); + return 1; + } + else if(hcint.b.nyet ) + { +IFX_WARN("%s() %d Warning CTRLBULK IN SPLIT0 NYET [should be Out only]\n",__func__,__LINE__); +showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + } + return 0; +} +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +static int32_t chhltd_ctrlbulk_tx_nonsplit(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + hcint_data_t hcint; + hcint_data_t hcintmsk; + hctsiz_data_t hctsiz; + int out_nak_enh = 0; + +#ifdef __DEBUG__ +static int first=0; +#endif + + if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH) + out_nak_enh = 1; + + hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); + hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + +#ifdef __DEBUG__ +if(!first&& _ifxhc->ep_type == IFXUSB_EP_TYPE_BULK + &&(hcint.b.stall || hcint.b.datatglerr || hcint.b.frmovrun || hcint.b.bblerr || hcint.b.xacterr) && !hcint.b.ack) +{ + showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + first=1; + printk(KERN_INFO " [%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X] \n" + ,*(_ifxhc->xfer_buff+ 0),*(_ifxhc->xfer_buff+ 1),*(_ifxhc->xfer_buff+ 2),*(_ifxhc->xfer_buff+ 3) + ,*(_ifxhc->xfer_buff+ 4),*(_ifxhc->xfer_buff+ 5),*(_ifxhc->xfer_buff+ 6),*(_ifxhc->xfer_buff+ 7) + ,*(_ifxhc->xfer_buff+ 8),*(_ifxhc->xfer_buff+ 9),*(_ifxhc->xfer_buff+10),*(_ifxhc->xfer_buff+11) + ,*(_ifxhc->xfer_buff+12),*(_ifxhc->xfer_buff+13),*(_ifxhc->xfer_buff+14),*(_ifxhc->xfer_buff+15)); + + printk(KERN_INFO " [_urbd->urb->actual_length:%08X _ifxhc->start_pkt_count:%08X hctsiz.b.pktcnt:%08X ,_urbd->xfer_len:%08x] \n" + ,_urbd->urb->actual_length + ,_ifxhc->start_pkt_count + ,hctsiz.b.pktcnt + ,_urbd->xfer_len); +} +#endif + + if(_ifxhc->halt_status == HC_XFER_NAK) + { + if(_ifxhc->nak_retry_r) + { + _ifxhc->nak_retry--; + if(_ifxhc->nak_retry) + { + if(_ifxhc->xfer_len!=0) + _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + _ifxhc->data_pid_start = read_data_toggle(_hc_regs); + _ifxhc->wait_for_sof = 1; + _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + else + { + _ifxhc->wait_for_sof = 0; + release_channel(_ifxhcd, _ifxhc, _ifxhc->halt_status); + } + } + else + { + if(_ifxhc->xfer_len!=0) + _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + _ifxhc->data_pid_start = read_data_toggle(_hc_regs); + _ifxhc->wait_for_sof = 1; + _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + return 1; + } + + if (hcint.b.xfercomp) + { + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nak); + disable_hc_int(_hc_regs,nyet); + _urbd->error_count =0; + if(_ifxhc->xfer_len==0 && !hcint.b.ack && hcint.b.nak) + { + // Walkaround: When sending ZLP and receive NAK but also issue CMPT intr + // Solution: NoSplit: Resend at next SOF + // Split : Resend at next SOF with SSPLIT + if(hcint.b.nyet && !out_nak_enh) + _ifxhc->do_ping = 1; + else + _ifxhc->do_ping = 0; + _ifxhc->xfer_len = 0; + _ifxhc->xfer_count = 0; + _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; + _ifxhc->wait_for_sof = 1; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + else + { + _ifxhc->wait_for_sof = 0; + _ifxhc->do_ping = 0; + complete_channel(_ifxhcd, _ifxhc, _urbd); + } + return 1; + } + else if (hcint.b.stall) + { + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nak); + disable_hc_int(_hc_regs,nyet); + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + _ifxhc->do_ping =0; + + // ZLP shortcut + #if 1 + if(hctsiz.b.pktcnt==0) + complete_channel(_ifxhcd, _ifxhc, _urbd); + else + #endif + { + if(_ifxhc->xfer_len!=0) + _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); + release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); + } + return 1; + } + else if (hcint.b.xacterr) + { + // ZLP shortcut + #if 1 + if(hctsiz.b.pktcnt==0) + { + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nak); + disable_hc_int(_hc_regs,nyet); + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + _ifxhc->do_ping =0; + complete_channel(_ifxhcd, _ifxhc, _urbd); + } + else + #endif + { + if(_ifxhc->xfer_len!=0) + _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + _ifxhc->data_pid_start = read_data_toggle(_hc_regs); + + if (hcint.b.nak || hcint.b.nyet || hcint.b.ack) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof =1; + enable_hc_int(_hc_regs,ack); + enable_hc_int(_hc_regs,nak); + enable_hc_int(_hc_regs,nyet); + if(!out_nak_enh) + _ifxhc->do_ping =1; + else + _ifxhc->do_ping =0; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + else + { + _urbd->error_count ++ ; + if (_urbd->error_count == 3) + { + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nak); + disable_hc_int(_hc_regs,nyet); + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + _ifxhc->do_ping =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); + } + else + { + enable_hc_int(_hc_regs,ack); + enable_hc_int(_hc_regs,nak); + enable_hc_int(_hc_regs,nyet); + _ifxhc->wait_for_sof =1; + if(!out_nak_enh) + _ifxhc->do_ping =1; + else + _ifxhc->do_ping =0; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + } + } + return 1; + } + else if(hcint.b.bblerr ) + { +IFX_WARN("%s() %d Warning CTRLBULK OUT SPLIT0 BABBLE [should be IN only]\n",__func__,__LINE__); +showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + _ifxhc->do_ping = 0; + if(_ifxhc->xfer_len!=0) + _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); + release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); + return 1; + } + else if(hcint.b.nak || hcint.b.nyet) + { + if(!out_nak_enh) + { + // ZLP shortcut + #if 1 + if(hctsiz.b.pktcnt==0) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + _ifxhc->do_ping =0; + complete_channel(_ifxhcd, _ifxhc, _urbd); + } + else + #endif + { + if(!out_nak_enh) + _ifxhc->do_ping =1; + else + _ifxhc->do_ping =0; + if(_ifxhc->xfer_len!=0) + { + _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + } + _ifxhc->data_pid_start = read_data_toggle(_hc_regs); + _ifxhc->wait_for_sof = 1; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + return 1; + } + } + else if(hcint.b.datatglerr ) + { +IFX_WARN("%s() %d Warning CTRLBULK OUT SPLIT0 DATATGLERR [should be IN only]\n",__func__,__LINE__); +showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + _ifxhc->do_ping =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_DATA_TOGGLE_ERR); + return 1; + } + else if(hcint.b.frmovrun ) + { +IFX_WARN("%s() %d Warning CTRLBULK OUT SPLIT0 FRMOVRUN [should be PERIODIC only]\n",__func__,__LINE__); +showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + _ifxhc->do_ping =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN); + return 1; + } + return 0; +} +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +static int32_t chhltd_intr_rx_nonsplit(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + hcint_data_t hcint; + hcint_data_t hcintmsk; + hctsiz_data_t hctsiz; + + hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); + hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nak); + disable_hc_int(_hc_regs,nyet); + _ifxhc->do_ping =0; + + if(_ifxhc->halt_status == HC_XFER_NAK) + { + if(_ifxhc->nak_retry_r) + { + _ifxhc->nak_retry--; + if(_ifxhc->nak_retry) + { + if(_ifxhc->xfer_len!=0) + _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + _ifxhc->data_pid_start = read_data_toggle(_hc_regs); + _ifxhc->wait_for_sof = 1; + _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + else + { + _ifxhc->wait_for_sof = 0; + release_channel(_ifxhcd, _ifxhc, _ifxhc->halt_status); + } + } + else + { + if(_ifxhc->xfer_len!=0) + _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + _ifxhc->data_pid_start = read_data_toggle(_hc_regs); + _ifxhc->wait_for_sof = 1; + _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + return 1; + } + + if(hcint.b.xfercomp ) + { + _urbd->error_count =0; + //restart INTR immediately + #if 1 + if(hctsiz.b.pktcnt>0) + { + // TODO Re-initialize Channel (in next b_interval - 1 uF/F) + _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; + if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + else + #endif + { + _ifxhc->wait_for_sof =0; + complete_channel(_ifxhcd, _ifxhc, _urbd); + } + return 1; + } + else if (hcint.b.stall) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + + // Don't care shortcut + #if 0 + if(hctsiz.b.pktcnt==0) + complete_channel(_ifxhcd, _ifxhc, _urbd); + else + #endif + { + // Stall FIFO compensation. + #if 0 + int sz1,sz2; + sz2=_ifxhc->start_pkt_count - hctsiz.b.pktcnt; + sz2*=_ifxhc->mps; + sz1=_ifxhc->xfer_len - hctsiz.b.xfersize; + sz2-=sz1; + if(sz2) + ifxhcd_hc_dumb_rx(&_ifxhcd->core_if, _ifxhc,_ifxhc->epqh->dump_buf); + #endif + _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); + release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); + } + return 1; + } + + + else if (hcint.b.bblerr) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + + // Don't care shortcut + #if 0 + if(hctsiz.b.pktcnt==0) + complete_channel(_ifxhcd, _ifxhc, _urbd); + else + #endif + { + _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); + release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); + } + return 1; + } + else if (hcint.b.nak || hcint.b.datatglerr || hcint.b.frmovrun) + { + _urbd->error_count =0; + //restart INTR immediately + #if 1 + if(hctsiz.b.pktcnt>0) + { + // TODO Re-initialize Channel (in next b_interval - 1 uF/F) + _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; + if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + else + #endif + { + _ifxhc->wait_for_sof =0; + complete_channel(_ifxhcd, _ifxhc, _urbd); + } + return 1; + } + else if (hcint.b.xacterr) + { + // ZLP shortcut + #if 1 + if(hctsiz.b.pktcnt==0) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + complete_channel(_ifxhcd, _ifxhc, _urbd); + } + else + #endif + { + /* 20110803 AVM/WK FIX: Reset error count on any handshake */ + if (hcint.b.nak || hcint.b.nyet || hcint.b.ack) { + _urbd->error_count = 1; + } else { + _urbd->error_count++; + } + + if(_urbd->error_count>=3) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); + } + else + { + _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + } + return 1; + } + else if(hcint.b.nyet ) + { +IFX_WARN("%s() %d Warning INTR IN SPLIT0 NYET [should be OUT only]\n",__func__,__LINE__); +showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + return 1; + } + return 0; +} +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +static int32_t chhltd_intr_tx_nonsplit(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + hcint_data_t hcint; + hcint_data_t hcintmsk; + hctsiz_data_t hctsiz; + int out_nak_enh = 0; + + if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH) + out_nak_enh = 1; + + hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); + hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + + if(_ifxhc->halt_status == HC_XFER_NAK) + { + if(_ifxhc->nak_retry_r) + { + _ifxhc->nak_retry--; + if(_ifxhc->nak_retry) + { + if(_ifxhc->xfer_len!=0) + _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + _ifxhc->data_pid_start = read_data_toggle(_hc_regs); + _ifxhc->wait_for_sof = 1; + _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + else + { + _ifxhc->wait_for_sof = 0; + release_channel(_ifxhcd, _ifxhc, _ifxhc->halt_status); + } + } + else + { + if(_ifxhc->xfer_len!=0) + _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + _ifxhc->data_pid_start = read_data_toggle(_hc_regs); + _ifxhc->wait_for_sof = 1; + _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + return 1; + } + + if(hcint.b.xfercomp ) + { + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nak); + disable_hc_int(_hc_regs,nyet); + _urbd->error_count =0; + //restart INTR immediately + #if 0 + if(hctsiz.b.pktcnt>0) + { + // TODO Re-initialize Channel (in next b_interval - 1 uF/F) + _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; + if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; + if(hcint.b.nyet && !out_nak_enh ) + _ifxhc->do_ping =1; + else + _ifxhc->do_ping =0; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + else + #endif + { + _ifxhc->wait_for_sof =0; + _ifxhc->do_ping =0; + complete_channel(_ifxhcd, _ifxhc, _urbd); + } + return 1; + } + else if (hcint.b.stall) + { + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nyet); + disable_hc_int(_hc_regs,nak); + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + _ifxhc->do_ping =0; + + // Don't care shortcut + #if 0 + if(hctsiz.b.pktcnt==0) + complete_channel(_ifxhcd, _ifxhc, _urbd); + else + #endif + { + if(_ifxhc->xfer_len!=0)// !_ifxhc->is_in + _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); + release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); + } + return 1; + } + else if(hcint.b.nak || hcint.b.frmovrun ) + { + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nyet); + disable_hc_int(_hc_regs,nak); + _urbd->error_count =0; + //restart INTR immediately + #if 0 + if(hctsiz.b.pktcnt>0) + { + // TODO Re-initialize Channel (in next b_interval - 1 uF/F) + _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; + if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; + if(!out_nak_enh ) + _ifxhc->do_ping =1; + else + _ifxhc->do_ping =0; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + else + #endif + { + _ifxhc->wait_for_sof =0; + _ifxhc->do_ping =0; + complete_channel(_ifxhcd, _ifxhc, _urbd); + } + return 1; + } + else if(hcint.b.xacterr ) + { + // ZLP shortcut + #if 1 + if(hctsiz.b.pktcnt==0) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + _ifxhc->do_ping =0; + complete_channel(_ifxhcd, _ifxhc, _urbd); + } + else + #endif + { + /* 20110803 AVM/WK FIX: Reset error count on any handshake */ + if (hcint.b.nak || hcint.b.nyet || hcint.b.ack) { + _urbd->error_count = 1; + } else { + _urbd->error_count++; + } + + if(_urbd->error_count>=3) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + _ifxhc->do_ping =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); + } + else + { + //_ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; + //if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; + _ifxhc->wait_for_sof=1; + if(!out_nak_enh ) + _ifxhc->do_ping =1; + else + _ifxhc->do_ping =0; + + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + } + return 1; + } + else if(hcint.b.bblerr ) + { +IFX_WARN("%s() %d Warning INTR OUT SPLIT0 BABBLEERR [should be IN only]\n",__func__,__LINE__); +showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + _ifxhc->do_ping =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); + return 1; + } + else if(hcint.b.datatglerr ) + { +IFX_WARN("%s() %d Warning INTR OUT SPLIT0 DATATGLERR\n",__func__,__LINE__); +showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + _ifxhc->do_ping =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_DATA_TOGGLE_ERR); + return 1; + } + return 0; +} +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +static int32_t chhltd_isoc_rx_nonsplit(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + #if defined(__EN_ISOC__) + hcint_data_t hcint; + hcint_data_t hcintmsk; + hctsiz_data_t hctsiz; + + hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); + hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + + if (hcint.b.xfercomp || hcint.b.frmovrun) + { + _urbd->error_count=0; + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nak); + disable_hc_int(_hc_regs,nyet); + _ifxhc->wait_for_sof = 0; + if (hcint.b.xfercomp) + complete_channel(_ifxhcd, _ifxhc, _urbd); + else + release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN); + } + else if (hcint.b.xacterr || hcint.b.bblerr) + { + #ifndef VR9Skip + if(hctsiz.b.pktcnt==0) + { + complete_channel(_ifxhcd, _ifxhc, _urbd); + } + else + { + int sz1,sz2; + sz2=_ifxhc->start_pkt_count - hctsiz.b.pktcnt; + sz2*=_ifxhc->mps; + sz1=_ifxhc->xfer_len - hctsiz.b.xfersize; + sz2-=sz1; + if(sz2) + ifxhcd_hc_dumb_rx(&_ifxhcd->core_if, _ifxhc,_ifxhc->epqh->dump_buf); + _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + _ifxhc->data_pid_start = read_data_toggle(_hc_regs); + _urbd->error_count++; + if(_urbd->error_count>=3) + { + _urbd->error_count=0; + _ifxhc->wait_for_sof = 0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); + release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); + } + else + { + _ifxhc->wait_for_sof = 1; + enable_hc_int(_hc_regs,ack); + enable_hc_int(_hc_regs,nak); + enable_hc_int(_hc_regs,nyet); + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + } + #endif + } + else if(hcint.b.datatglerr ) + { + warning + } + else if(hcint.b.stall ) + { + warning + } + #else + #endif + return 0; +} +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +static int32_t chhltd_isoc_tx_nonsplit(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + #if defined(__EN_ISOC__) + hcint_data_t hcint; + hcint_data_t hcintmsk; + hctsiz_data_t hctsiz; + int out_nak_enh = 0; + + if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH) + out_nak_enh = 1; + + hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); + hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + + if (hcint.b.xfercomp) + { + _urbd->error_count=0; + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nak); + disable_hc_int(_hc_regs,nyet); + _ifxhc->wait_for_sof = 0; + complete_channel(_ifxhcd, _ifxhc, _urbd); + return 1; + } + else if (hcint.b.frmovrun) + { + #ifndef VR9Skip + _urbd->error_count=0; + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nak); + disable_hc_int(_hc_regs,nyet); + _ifxhc->wait_for_sof = 0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN); + #endif + } + else if(hcint.b.datatglerr ) + { + warning + } + else if(hcint.b.bblerr ) + { + #ifndef VR9Skip + if(hctsiz.b.pktcnt==0) + { + complete_channel(_ifxhcd, _ifxhc, _urbd); + } + else + { + int sz1,sz2; + sz2=_ifxhc->start_pkt_count - hctsiz.b.pktcnt; + sz2*=_ifxhc->mps; + sz1=_ifxhc->xfer_len - hctsiz.b.xfersize; + sz2-=sz1; + if(sz2) + ifxhcd_hc_dumb_rx(&_ifxhcd->core_if, _ifxhc,_ifxhc->epqh->dump_buf); + _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + _ifxhc->data_pid_start = read_data_toggle(_hc_regs); + _urbd->error_count++; + if(_urbd->error_count>=3) + { + _urbd->error_count=0; + _ifxhc->wait_for_sof = 0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); + } + else + { + _ifxhc->wait_for_sof = 1; + enable_hc_int(_hc_regs,ack); + enable_hc_int(_hc_regs,nak); + enable_hc_int(_hc_regs,nyet); + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + } + #endif + } + else if(hcint.b.xacterr ) + { + if(hctsiz.b.pktcnt==0) + { + complete_channel(_ifxhcd, _ifxhc, _urbd); + return 1; + } + _urbd->error_count++; + if(_urbd->error_count>=3) + { + _urbd->error_count=0; + _ifxhc->wait_for_sof = 0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); + } + else + { + _ifxhc->wait_for_sof = 1; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + return 1; + } + else if(hcint.b.stall ) + { + warning + } + #else + #endif + return 0; +} +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +static int32_t chhltd_ctrlbulk_rx_ssplit(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + hcint_data_t hcint; + hcint_data_t hcintmsk; + hctsiz_data_t hctsiz; + + hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); + hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nak); + disable_hc_int(_hc_regs,nyet); + + _ifxhc->do_ping =0; + + if (hcint.b.ack) + { + _urbd->error_count=0; + _ifxhc->split=2; + _ifxhc->wait_for_sof = 8; + _ifxhc->data_pid_start = read_data_toggle(_hc_regs); + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if (hcint.b.nak) + { + _ifxhc->wait_for_sof = 1; + _urbd->error_count = 0; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if (hcint.b.xacterr) + { + _urbd->error_count++; + if(_urbd->error_count>=3) + { + _urbd->error_count=0; + _ifxhc->wait_for_sof =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); + } + else + { + _ifxhc->wait_for_sof =1; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + return 1; + } + else if(hcint.b.bblerr ) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); + return 1; + } + else if(hcint.b.stall ) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); + return 1; + } + else if(hcint.b.datatglerr ) + { +IFX_WARN("%s() %d Warning CTRLBULK IN SPLIT1 HC_XFER_DATA_TOGGLE_ERR\n",__func__,__LINE__); +showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_DATA_TOGGLE_ERR); + return 1; + } + else if(hcint.b.frmovrun ) + { +IFX_WARN("%s() %d Warning CTRLBULK IN SPLIT1 HC_XFER_FRAME_OVERRUN\n",__func__,__LINE__); +showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN); + return 1; + } + else if(hcint.b.nyet ) + { +IFX_WARN("%s() %d Warning CTRLBULK IN SPLIT1 NYET\n",__func__,__LINE__); +showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + } + else if(hcint.b.xfercomp ) + { +IFX_WARN("%s() %d Warning CTRLBULK IN SPLIT1 COMPLETE\n",__func__,__LINE__); +showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + } + return 0; +} +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +static int32_t chhltd_ctrlbulk_tx_ssplit(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + hcint_data_t hcint; + hcint_data_t hcintmsk; + hctsiz_data_t hctsiz; + int out_nak_enh = 0; + +#ifdef __DEBUG__ +static int first=0; +#endif + + if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH) + out_nak_enh = 1; + + hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); + hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nak); + disable_hc_int(_hc_regs,nyet); + +#ifdef __DEBUG__ + if(!first&& _ifxhc->ep_type == IFXUSB_EP_TYPE_BULK + &&(hcint.b.stall || hcint.b.datatglerr || hcint.b.frmovrun || hcint.b.bblerr || hcint.b.xacterr) && !hcint.b.ack) + { + showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + first=1; + printk(KERN_INFO " [%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X] \n" + ,*(_ifxhc->xfer_buff+ 0),*(_ifxhc->xfer_buff+ 1),*(_ifxhc->xfer_buff+ 2),*(_ifxhc->xfer_buff+ 3) + ,*(_ifxhc->xfer_buff+ 4),*(_ifxhc->xfer_buff+ 5),*(_ifxhc->xfer_buff+ 6),*(_ifxhc->xfer_buff+ 7) + ,*(_ifxhc->xfer_buff+ 8),*(_ifxhc->xfer_buff+ 9),*(_ifxhc->xfer_buff+10),*(_ifxhc->xfer_buff+11) + ,*(_ifxhc->xfer_buff+12),*(_ifxhc->xfer_buff+13),*(_ifxhc->xfer_buff+14),*(_ifxhc->xfer_buff+15)); + + printk(KERN_INFO " [_urbd->urb->actual_length:%08X _ifxhc->start_pkt_count:%08X hctsiz.b.pktcnt:%08X ,_urbd->xfer_len:%08x] \n" + ,_urbd->urb->actual_length + ,_ifxhc->start_pkt_count + ,hctsiz.b.pktcnt + ,_urbd->xfer_len); + } +#endif + + if (hcint.b.ack ) + { + _urbd->error_count=0; + if (_ifxhc->ep_type == IFXUSB_EP_TYPE_BULK || _ifxhc->control_phase != IFXHCD_CONTROL_SETUP) + _ifxhc->ssplit_out_xfer_count = _ifxhc->xfer_len; + _ifxhc->split=2; + _ifxhc->wait_for_sof =8; + _ifxhc->data_pid_start =read_data_toggle(_hc_regs); + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.nyet) + { +IFX_WARN("%s() %d Warning CTRLBULK OUT SPLIT1 NYET\n",__func__,__LINE__); +showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + _urbd->error_count=0; + if (_ifxhc->ep_type == IFXUSB_EP_TYPE_BULK || _ifxhc->control_phase != IFXHCD_CONTROL_SETUP) + _ifxhc->ssplit_out_xfer_count = _ifxhc->xfer_len; + _ifxhc->split=2; + _ifxhc->wait_for_sof =1; + _ifxhc->data_pid_start =read_data_toggle(_hc_regs); + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.nak ) + { + _ifxhc->wait_for_sof =1; + if(!out_nak_enh ) + _ifxhc->do_ping =1; + else + _ifxhc->do_ping =0; + _urbd->error_count =0; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.xacterr ) + { + _urbd->error_count++; + if(_urbd->error_count>=3) + { + _urbd->error_count=0; + _ifxhc->wait_for_sof =0; + _ifxhc->do_ping =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); + } + else + { + _ifxhc->wait_for_sof =1; + _ifxhc->do_ping =1; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + return 1; + } + else if(hcint.b.datatglerr ) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + _ifxhc->do_ping =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_DATA_TOGGLE_ERR); + return 1; + } + else if(hcint.b.bblerr ) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + _ifxhc->do_ping =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); + return 1; + } + else if(hcint.b.stall ) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + _ifxhc->do_ping =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); + return 1; + } + else if(hcint.b.frmovrun ) + { +IFX_WARN("%s() %d Warning CTRLBULK OUT SPLIT1 HC_XFER_FRAME_OVERRUN\n",__func__,__LINE__); +showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + _ifxhc->do_ping =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN); + return 1; + } + else if(hcint.b.xfercomp ) + { + printk(KERN_INFO "%s() %d Warning CTRLBULK OUT SPLIT1 COMPLETE\n",__func__,__LINE__); + } + return 0; +} +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +static int32_t chhltd_intr_rx_ssplit(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + hcint_data_t hcint; + hcint_data_t hcintmsk; + hctsiz_data_t hctsiz; + + hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); + hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nak); + disable_hc_int(_hc_regs,nyet); + + _ifxhc->do_ping =0; + + if (hcint.b.ack ) + { + /*== AVM/BC 20100701 - Workaround FullSpeed Interrupts with HiSpeed Hub ==*/ + _ifxhc->nyet_count=0; + + _urbd->error_count=0; + _ifxhc->split=2; + _ifxhc->wait_for_sof = 0; + _ifxhc->data_pid_start = read_data_toggle(_hc_regs); + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.nak ) + { + _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; + if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; + _urbd->error_count=0; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.xacterr ) + { + hcchar_data_t hcchar; + hcchar.d32 = ifxusb_rreg(&_hc_regs->hcchar); + _urbd->error_count=hcchar.b.multicnt; + if(_urbd->error_count>=3) + { + _urbd->error_count=0; + _ifxhc->wait_for_sof = 0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); + } + else + { + _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; + if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + return 1; + } + else if(hcint.b.stall ) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); + return 1; + } + else if(hcint.b.bblerr ) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); + return 1; + } + else if(hcint.b.frmovrun ) + { + _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; + if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.datatglerr ) + { +IFX_WARN( "%s() %d Warning INTR IN SPLIT1 DATATGLERR\n",__func__,__LINE__); +showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_DATA_TOGGLE_ERR); + return 1; + } + else if(hcint.b.xfercomp ) + { +IFX_WARN("%s() %d Warning INTR IN SPLIT1 COMPLETE\n",__func__,__LINE__); +showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + } + return 0; +} +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +static int32_t chhltd_intr_tx_ssplit(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + hcint_data_t hcint; + hcint_data_t hcintmsk; + hctsiz_data_t hctsiz; + int out_nak_enh = 0; + + if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH) + out_nak_enh = 1; + + hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); + hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nak); + disable_hc_int(_hc_regs,nyet); + + if (hcint.b.ack ) + { + /*== AVM/BC 20100701 - Workaround FullSpeed Interrupts with HiSpeed Hub ==*/ + _ifxhc->nyet_count=0; + + _urbd->error_count=0; + _ifxhc->ssplit_out_xfer_count = _ifxhc->xfer_len; + _ifxhc->split=2; + _ifxhc->wait_for_sof = 0; + _ifxhc->data_pid_start = read_data_toggle(_hc_regs); + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.nyet) + { +IFX_WARN("%s() %d Warning INTR OUT SPLIT1 NYET\n",__func__,__LINE__); +showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + _urbd->error_count=0; + _ifxhc->ssplit_out_xfer_count = _ifxhc->xfer_len; + _ifxhc->split=2; + _ifxhc->wait_for_sof = 0; + _ifxhc->data_pid_start = read_data_toggle(_hc_regs); + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.nak ) + { + _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; + if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; + _urbd->error_count =0; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.frmovrun ) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; + if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.xacterr ) + { + hcchar_data_t hcchar; + hcchar.d32 = ifxusb_rreg(&_hc_regs->hcchar); + _urbd->error_count=hcchar.b.multicnt; + if(_urbd->error_count>=3) + { + _urbd->error_count=0; + _ifxhc->wait_for_sof =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); + } + else + { + enable_hc_int(_hc_regs,ack); + enable_hc_int(_hc_regs,nak); + enable_hc_int(_hc_regs,nyet); + _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; + if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + return 1; + } + else if(hcint.b.datatglerr ) + { +IFX_WARN("%s() %d Warning INTR IN SPLIT1 DATATGLERR\n",__func__,__LINE__); +showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_DATA_TOGGLE_ERR); + return 1; + } + else if(hcint.b.bblerr ) + { +IFX_WARN("%s() %d Warning INTR IN SPLIT1 BABBLEERR\n",__func__,__LINE__); +showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); + return 1; + } + else if(hcint.b.stall ) + { +IFX_WARN("%s() %d Warning INTR IN SPLIT1 STALL\n",__func__,__LINE__); +showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + _urbd->error_count =0; + _ifxhc->wait_for_sof =0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); + return 1; + } + else if(hcint.b.xfercomp ) + { +IFX_WARN("%s() %d Warning INTR IN SPLIT1 COMPLETE\n",__func__,__LINE__); +showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + } + return 0; +} +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +static int32_t chhltd_isoc_rx_ssplit(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + #if defined(__EN_ISOC__) && defined(__EN_ISOC_SPLIT__) + hcint_data_t hcint; + hcint_data_t hcintmsk; + hctsiz_data_t hctsiz; + + hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); + hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + if (hcint.b.ack ) + { + Do Complete Split + } + else if(hcint.b.frmovrun ) + { + Rewind Buffer Pointers + Retry Start Split (in next b_interval ¡V 1 uF) + } + else if(hcint.b.datatglerr ) + { + warning + } + else if(hcint.b.bblerr ) + { + warning + } + else if(hcint.b.xacterr ) + { + warning + } + else if(hcint.b.stall ) + { + warning + } + else if(hcint.b.nak ) + { + warning + } + else if(hcint.b.xfercomp ) + { + warning + } + else if(hcint.b.nyet) + { + warning + } + #endif + return 0; +} +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +static int32_t chhltd_isoc_tx_ssplit(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + #if defined(__EN_ISOC__) && defined(__EN_ISOC_SPLIT__) + hcint_data_t hcint; + hcint_data_t hcintmsk; + hctsiz_data_t hctsiz; + int out_nak_enh = 0; + + if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH) + out_nak_enh = 1; + + hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); + hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + if (hcint.b.ack ) + { + Do Next Start Split (in next b_interval ¡V 1 uF) + } + else if(hcint.b.frmovrun ) + { + Do Next Transaction in next frame. + } + else if(hcint.b.datatglerr ) + { + warning + } + else if(hcint.b.bblerr ) + { + warning + } + else if(hcint.b.xacterr ) + { + warning + } + else if(hcint.b.stall ) + { + warning + } + else if(hcint.b.nak ) + { + warning + } + else if(hcint.b.xfercomp ) + { + warning + } + else if(hcint.b.nyet) + { + warning + } + #endif + return 0; +} +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +static int32_t chhltd_ctrlbulk_rx_csplit(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + hcint_data_t hcint; + hcint_data_t hcintmsk; + hctsiz_data_t hctsiz; + + hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); + hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nak); + disable_hc_int(_hc_regs,nyet); + + _ifxhc->do_ping = 0; + + if (hcint.b.xfercomp) + { + _urbd->error_count =0; + _ifxhc->wait_for_sof = 0; + _ifxhc->split=1; + complete_channel(_ifxhcd, _ifxhc, _urbd); + return 1; + } + else if (hcint.b.nak) + { + _urbd->error_count=0; + + _ifxhc->split = 1; + _ifxhc->wait_for_sof = 1; + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.nyet) + { + _urbd->error_count=0; + _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; + _ifxhc->wait_for_sof = 1; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.stall || hcint.b.bblerr ) + { + _urbd->error_count=0; + _ifxhc->wait_for_sof = 0; + if (hcint.b.stall) + release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); + else if(hcint.b.bblerr ) + release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); + return 1; + } + else if(hcint.b.xacterr ) + { + _urbd->error_count++; + if(_urbd->error_count>=3) + { + _urbd->error_count=0; + _ifxhc->wait_for_sof = 0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); + } + else + { + _ifxhc->split=1; + _ifxhc->wait_for_sof = 1; + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + return 1; + } + else if(hcint.b.datatglerr ) + { + if(_ifxhc->data_pid_start == IFXUSB_HC_PID_DATA0) + _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1; + else + _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0; + _ifxhc->split=1; + _ifxhc->wait_for_sof = 1; + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.frmovrun ) + { + _urbd->error_count=0; + _ifxhc->wait_for_sof = 0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN); + return 1; + } + return 0; +} +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +static int32_t chhltd_ctrlbulk_tx_csplit(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + hcint_data_t hcint; + hcint_data_t hcintmsk; + hctsiz_data_t hctsiz; + int out_nak_enh = 0; + +#if 1 +static int first=0; +#endif + + if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH) + out_nak_enh = 1; + + hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); + hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nak); + disable_hc_int(_hc_regs,nyet); + +#if 1 + if(!first&& _ifxhc->ep_type == IFXUSB_EP_TYPE_BULK + &&(hcint.b.stall || hcint.b.datatglerr || hcint.b.frmovrun || hcint.b.bblerr || hcint.b.xacterr) && !hcint.b.ack) + { + showint( hcint.d32,hcintmsk.d32,hctsiz.d32); + first=1; + printk(KERN_INFO " [%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X] \n" + ,*(_ifxhc->xfer_buff+ 0),*(_ifxhc->xfer_buff+ 1),*(_ifxhc->xfer_buff+ 2),*(_ifxhc->xfer_buff+ 3) + ,*(_ifxhc->xfer_buff+ 4),*(_ifxhc->xfer_buff+ 5),*(_ifxhc->xfer_buff+ 6),*(_ifxhc->xfer_buff+ 7) + ,*(_ifxhc->xfer_buff+ 8),*(_ifxhc->xfer_buff+ 9),*(_ifxhc->xfer_buff+10),*(_ifxhc->xfer_buff+11) + ,*(_ifxhc->xfer_buff+12),*(_ifxhc->xfer_buff+13),*(_ifxhc->xfer_buff+14),*(_ifxhc->xfer_buff+15)); + + printk(KERN_INFO " [_urbd->urb->actual_length:%08X _ifxhc->start_pkt_count:%08X hctsiz.b.pktcnt:%08X ,_urbd->xfer_len:%08x] \n" + ,_urbd->urb->actual_length + ,_ifxhc->start_pkt_count + ,hctsiz.b.pktcnt + ,_urbd->xfer_len); + } +#endif + + if(hcint.b.xfercomp ) + { + _urbd->error_count=0; + _ifxhc->split=1; + _ifxhc->do_ping= 0; + #if 0 + if(_ifxhc->xfer_len==0 && !hcint.b.ack && (hcint.b.nak || hcint.b.nyet)) + { + // Walkaround: When sending ZLP and receive NYEY or NAK but also issue CMPT intr + // Solution: NoSplit: Resend at next SOF + // Split : Resend at next SOF with SSPLIT + _ifxhc->xfer_len = 0; + _ifxhc->xfer_count = 0; + _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; + _ifxhc->wait_for_sof = 1; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + else + #endif + { + _ifxhc->wait_for_sof = 0; + complete_channel(_ifxhcd, _ifxhc, _urbd); + } + return 1; + } + else if(hcint.b.nak ) + { + _urbd->error_count=0; + + _ifxhc->split = 1; + _ifxhc->wait_for_sof = 1; + if(!out_nak_enh ) + _ifxhc->do_ping =1; + else + _ifxhc->do_ping =0; + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.nyet) + { + //Retry Complete Split + // Issue Retry instantly on next SOF, without gothrough process_channels + _urbd->error_count=0; + _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; + _ifxhc->wait_for_sof = 1; + _ifxhc->do_ping = 0; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.stall ) + { + _urbd->error_count=0; + _ifxhc->wait_for_sof = 0; + _ifxhc->do_ping = 0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); + return 1; + } + else if(hcint.b.xacterr ) + { + _urbd->error_count++; + if(_urbd->error_count>=3) + { + _urbd->error_count=0; + _ifxhc->wait_for_sof = 0; + _ifxhc->do_ping = 0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); + } + else + { + _ifxhc->split=1; + _ifxhc->wait_for_sof = 1; + if(!out_nak_enh ) + _ifxhc->do_ping =1; + else + _ifxhc->do_ping =0; + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + return 1; + } + else if(hcint.b.datatglerr ) + { + if(_ifxhc->data_pid_start == IFXUSB_HC_PID_DATA0) + _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1; + else + _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0; + _ifxhc->split=1; + _ifxhc->wait_for_sof = 1; + if(!out_nak_enh ) + _ifxhc->do_ping =1; + else + _ifxhc->do_ping =0; + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.frmovrun ) + { + _urbd->error_count=0; + _ifxhc->wait_for_sof = 0; + _ifxhc->do_ping = 0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN); + return 1; + } + else if(hcint.b.bblerr ) + { + _urbd->error_count=0; + _ifxhc->wait_for_sof = 0; + _ifxhc->do_ping = 0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); + return 1; + } + return 0; +} +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +static int32_t chhltd_intr_rx_csplit(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + hcint_data_t hcint; + hcint_data_t hcintmsk; + hctsiz_data_t hctsiz; + + hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); + hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nak); + disable_hc_int(_hc_regs,nyet); + _ifxhc->do_ping = 0; + + if (hcint.b.xfercomp ) + { + _urbd->error_count=0; + _ifxhc->wait_for_sof = 0; + _ifxhc->split=1; + complete_channel(_ifxhcd, _ifxhc, _urbd); + return 1; + } + else if(hcint.b.nak ) + { + _urbd->error_count=0; + _ifxhc->split = 1; + _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; + if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.nyet) + { + _urbd->error_count=0; + _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; + _ifxhc->wait_for_sof = 0; + + /*== AVM/BC 20100701 - Workaround FullSpeed Interrupts with HiSpeed Hub ==*/ + _ifxhc->nyet_count++; + if(_ifxhc->nyet_count > 2) { + _ifxhc->split = 1; + _ifxhc->nyet_count = 0; + _ifxhc->wait_for_sof = 5; + } + + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.frmovrun || hcint.b.bblerr || hcint.b.stall ) + { + _urbd->error_count=0; + _ifxhc->wait_for_sof = 0; + if (hcint.b.stall) + release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); + else if(hcint.b.bblerr ) + release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); + else if(hcint.b.frmovrun ) + release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN); + return 1; + } + else if(hcint.b.xacterr ) + { + hcchar_data_t hcchar; + hcchar.d32 = ifxusb_rreg(&_hc_regs->hcchar); + _urbd->error_count=hcchar.b.multicnt; + if(_urbd->error_count>=3) + { + _urbd->error_count=0; + _ifxhc->wait_for_sof = 0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); + } + else + { + _ifxhc->split=1; + _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; + if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + return 1; + } + else if(hcint.b.datatglerr ) + { + if(_ifxhc->data_pid_start == IFXUSB_HC_PID_DATA0) + _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1; + else + _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0; + _ifxhc->split=1; + _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; + if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + return 0; +} +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +static int32_t chhltd_intr_tx_csplit(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + hcint_data_t hcint; + hcint_data_t hcintmsk; + hctsiz_data_t hctsiz; + int out_nak_enh = 0; + + if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH) + out_nak_enh = 1; + + hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); + hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nak); + disable_hc_int(_hc_regs,nyet); + + if(hcint.b.xfercomp ) + { + _urbd->error_count=0; + _ifxhc->wait_for_sof = 0; + _ifxhc->split=1; + _ifxhc->do_ping = 0; + complete_channel(_ifxhcd, _ifxhc, _urbd); + return 1; + } + else if(hcint.b.nak ) + { + _urbd->error_count=0; + _ifxhc->split = 1; + _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; + if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; + if(!out_nak_enh ) + _ifxhc->do_ping =1; + else + _ifxhc->do_ping =0; + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.nyet) + { + _urbd->error_count=0; + _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; + _ifxhc->wait_for_sof = 0; + _ifxhc->do_ping = 0; + + /*== AVM/BC 20100701 - Workaround FullSpeed Interrupts with HiSpeed Hub ==*/ + _ifxhc->nyet_count++; + if(_ifxhc->nyet_count > 2) { + _ifxhc->split = 1; + _ifxhc->nyet_count = 0; + _ifxhc->wait_for_sof = 5; + } + + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.stall || hcint.b.frmovrun) + { + _urbd->error_count=0; + _ifxhc->wait_for_sof = 0; + _ifxhc->do_ping = 0; + if (hcint.b.stall) + release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); + else if(hcint.b.frmovrun ) + release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN); + return 1; + } + else if(hcint.b.xacterr ) + { + hcchar_data_t hcchar; + hcchar.d32 = ifxusb_rreg(&_hc_regs->hcchar); + _urbd->error_count=hcchar.b.multicnt; + if(_urbd->error_count>=3) + { + _urbd->error_count=0; + _ifxhc->wait_for_sof = 0; + _ifxhc->do_ping = 0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); + } + else + { + _ifxhc->split=1; + _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; + if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; + if(!out_nak_enh ) + _ifxhc->do_ping =1; + else + _ifxhc->do_ping =0; + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + } + return 1; + } + else if(hcint.b.datatglerr ) + { + if(_ifxhc->data_pid_start == IFXUSB_HC_PID_DATA0) + _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1; + else + _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0; + _ifxhc->split=1; + if(!out_nak_enh ) + _ifxhc->do_ping =1; + else + _ifxhc->do_ping =0; + _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; + _ifxhc->xfer_count = _urbd->urb->actual_length; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.bblerr ) + { + _urbd->error_count=0; + _ifxhc->wait_for_sof = 0; + _ifxhc->do_ping = 0; + release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); + return 1; + } + return 0; +} +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +static int32_t chhltd_isoc_rx_csplit(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + #if defined(__EN_ISOC__) && defined(__EN_ISOC_SPLIT__) + hcint_data_t hcint; + hcint_data_t hcintmsk; + hctsiz_data_t hctsiz; + + hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); + hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + if(hcint.b.xfercomp ) + { + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nak); + disable_hc_int(_hc_regs,nyet); + _urbd->error_count=0; + _ifxhc->wait_for_sof = 0; + _ifxhc->split=1; + complete_channel(_ifxhcd, _ifxhc, _urbd); + return 1; + } + else if(hcint.b.nak ) + { + Retry Start Split (in next b_interval ¡V 1 uF) + } + else if(hcint.b.nyet) + { + //Do Next Complete Split + // Issue Retry instantly on next SOF, without gothrough process_channels + _urbd->error_count=0; + //disable_hc_int(_hc_regs,ack); + //disable_hc_int(_hc_regs,nak); + //disable_hc_int(_hc_regs,datatglerr); + _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; + _ifxhc->wait_for_sof = 1; + ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); + return 1; + } + else if(hcint.b.frmovrun || hcint.b.stall || hcint.b.bblerr) + { + _urbd->error_count=0; + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nyet); + disable_hc_int(_hc_regs,nak); + _ifxhc->wait_for_sof = 0; + + //if(hctsiz.b.pktcnt==0) + //{ + // complete_channel(_ifxhcd, _ifxhc, _urbd); + // return 1; + //} + //else + // _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); + if (hcint.b.stall) + release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); + else if(hcint.b.frmovrun ) + else if(hcint.b.bblerr ) + return 1; + } + else if(hcint.b.xacterr ) + { + Rewind Buffer Pointers + if (HCCHARn.EC = = 3) // ERR response received + { + Record ERR error + Do Next Start Split (in next frame) + } + else + { + De-allocate Channel + } + } + else if(hcint.b.datatglerr ) + { + warning + } + else if(hcint.b.ack ) + { + warning + } + #endif + return 0; +} +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +static int32_t chhltd_isoc_tx_csplit(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + #if defined(__EN_ISOC__) && defined(__EN_ISOC_SPLIT__) + hcint_data_t hcint; + hcint_data_t hcintmsk; + hctsiz_data_t hctsiz; + int out_nak_enh = 0; + + if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH) + out_nak_enh = 1; + + hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); + hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + warning + #endif + return 0; +} +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +static int32_t handle_hc_chhltd_intr(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + IFX_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: Channel Halted--\n", _ifxhc->hc_num); + + _ifxhc->halting = 0; + _ifxhc->xfer_started = 0; + + if (_ifxhc->halt_status == HC_XFER_URB_DEQUEUE || + _ifxhc->halt_status == HC_XFER_AHB_ERR) { + /* + * Just release the channel. A dequeue can happen on a + * transfer timeout. In the case of an AHB Error, the channel + * was forced to halt because there's no way to gracefully + * recover. + */ + release_channel(_ifxhcd, _ifxhc, _ifxhc->halt_status); + return 1; + } + + if (_ifxhc->ep_type == IFXUSB_EP_TYPE_CTRL || _ifxhc->ep_type == IFXUSB_EP_TYPE_BULK) + { + if (_ifxhc->split==0) + { + if(_ifxhc->is_in) + return (chhltd_ctrlbulk_rx_nonsplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); + else + return (chhltd_ctrlbulk_tx_nonsplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); + } + else if(_ifxhc->split==1) + { + if(_ifxhc->is_in) + return (chhltd_ctrlbulk_rx_ssplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); + else + return (chhltd_ctrlbulk_tx_ssplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); + } + else if(_ifxhc->split==2) + { + if(_ifxhc->is_in) + return (chhltd_ctrlbulk_rx_csplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); + else + return (chhltd_ctrlbulk_tx_csplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); + } + } + else if(_ifxhc->ep_type == IFXUSB_EP_TYPE_INTR) + { + if (_ifxhc->split==0) + { + if(_ifxhc->is_in) + return (chhltd_intr_rx_nonsplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); + else + return (chhltd_intr_tx_nonsplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); + } + else if(_ifxhc->split==1) + { + if(_ifxhc->is_in) + return (chhltd_intr_rx_ssplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); + else + return (chhltd_intr_tx_ssplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); + } + else if(_ifxhc->split==2) + { + if(_ifxhc->is_in) + return (chhltd_intr_rx_csplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); + else + return (chhltd_intr_tx_csplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); + } + } + else if(_ifxhc->ep_type == IFXUSB_EP_TYPE_ISOC) + { + if (_ifxhc->split==0) + { + if(_ifxhc->is_in) + return (chhltd_isoc_rx_nonsplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); + else + return (chhltd_isoc_tx_nonsplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); + } + else if(_ifxhc->split==1) + { + if(_ifxhc->is_in) + return (chhltd_isoc_rx_ssplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); + else + return (chhltd_isoc_tx_ssplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); + } + else if(_ifxhc->split==2) + { + if(_ifxhc->is_in) + return (chhltd_isoc_rx_csplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); + else + return (chhltd_isoc_tx_csplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); + } + } + return 0; +} + +/* + * Handles a host channel AHB error interrupt. This handler is only called in + * DMA mode. + */ +static void hc_other_intr_dump(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + #ifdef __DEBUG__ + hcchar_data_t hcchar; + hcsplt_data_t hcsplt; + hctsiz_data_t hctsiz; + uint32_t hcdma; + struct urb *urb = _urbd->urb; + hcchar.d32 = ifxusb_rreg(&_hc_regs->hcchar); + hcsplt.d32 = ifxusb_rreg(&_hc_regs->hcsplt); + hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); + hcdma = ifxusb_rreg(&_hc_regs->hcdma); + + IFX_ERROR("Channel %d\n", _ifxhc->hc_num); + IFX_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32); + IFX_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma); + IFX_ERROR(" Device address: %d\n", usb_pipedevice(urb->pipe)); + IFX_ERROR(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe), + (usb_pipein(urb->pipe) ? "IN" : "OUT")); + IFX_ERROR(" Endpoint type: %s\n", + ({char *pipetype; + switch (usb_pipetype(urb->pipe)) { + case PIPE_CONTROL: pipetype = "CTRL"; break; + case PIPE_BULK: pipetype = "BULK"; break; + case PIPE_INTERRUPT: pipetype = "INTR"; break; + case PIPE_ISOCHRONOUS: pipetype = "ISOC"; break; + default: pipetype = "????"; break; + }; pipetype;})); + IFX_ERROR(" Speed: %s\n", + ({char *speed; + switch (urb->dev->speed) { + case USB_SPEED_HIGH: speed = "HS"; break; + case USB_SPEED_FULL: speed = "FS"; break; + case USB_SPEED_LOW: speed = "LS"; break; + default: speed = "????"; break; + }; speed;})); + IFX_ERROR(" Max packet size: %d\n", + usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); + IFX_ERROR(" Data buffer length: %d\n", urb->transfer_buffer_length); + IFX_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n", + urb->transfer_buffer, (void *)urb->transfer_dma); + IFX_ERROR(" Setup buffer: %p, Setup DMA: %p\n", + urb->setup_packet, (void *)urb->setup_dma); + IFX_ERROR(" Interval: %d\n", urb->interval); + #endif //__DEBUG__ +} + +/* + * Handles a host channel ACK interrupt. This interrupt is enabled when + * errors occur, and during Start Split transactions. + */ +static int32_t handle_hc_ack_intr(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + _urbd->error_count=0; + if(_ifxhc->nak_countdown_r) + { + _ifxhc->nak_retry=_ifxhc->nak_retry_r; + _ifxhc->nak_countdown=_ifxhc->nak_countdown_r; + } + else + disable_hc_int(_hc_regs,nak); + disable_hc_int(_hc_regs,ack); + return 1; +} + +/* + * Handles a host channel ACK interrupt. This interrupt is enabled when + * errors occur, and during Start Split transactions. + */ +static int32_t handle_hc_nak_intr(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + + _urbd->error_count=0; + + if(_ifxhc->nak_countdown_r) + { + _ifxhc->nak_countdown--; + if(!_ifxhc->nak_countdown) + { + _ifxhc->nak_countdown=_ifxhc->nak_countdown_r; + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nak); + ifxhcd_hc_halt(&_ifxhcd->core_if, _ifxhc, HC_XFER_NAK); + } + else + enable_hc_int(_hc_regs,ack); + } + else + { + disable_hc_int(_hc_regs,ack); + disable_hc_int(_hc_regs,nak); + } + return 1; +} + +/* + * Handles a host channel AHB error interrupt. This handler is only called in + * DMA mode. + */ +static int32_t handle_hc_ahberr_intr(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + IFX_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " + "AHB Error--\n", _ifxhc->hc_num); + hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd); + + ifxhcd_hc_halt(&_ifxhcd->core_if, _ifxhc, HC_XFER_AHB_ERR); + return 1; +} + +/* + * Datatoggle + */ +static int32_t handle_hc_datatglerr_intr(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + IFX_ERROR( "--Host Channel %d Interrupt: " + "DATATOGGLE Error--\n", _ifxhc->hc_num); + hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd); + disable_hc_int(_hc_regs,datatglerr); + return 1; +} + + + +/* + * Interrupts which should not been triggered + */ +static int32_t handle_hc_frmovrun_intr(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + IFX_ERROR( "--Host Channel %d Interrupt: " + "FrameOverRun Error--\n", _ifxhc->hc_num); + hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd); + disable_hc_int(_hc_regs,frmovrun); + return 1; +} + +static int32_t handle_hc_bblerr_intr(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + IFX_ERROR( "--Host Channel %d Interrupt: " + "BBL Error--\n", _ifxhc->hc_num); + hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd); + disable_hc_int(_hc_regs,bblerr); + return 1; +} + +static int32_t handle_hc_xacterr_intr(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + IFX_ERROR( "--Host Channel %d Interrupt: " + "XACT Error--\n", _ifxhc->hc_num); + hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd); + disable_hc_int(_hc_regs,xacterr); + return 1; +} + +static int32_t handle_hc_nyet_intr(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + IFX_ERROR( "--Host Channel %d Interrupt: " + "NYET--\n", _ifxhc->hc_num); + hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd); + _urbd->error_count=0; + disable_hc_int(_hc_regs,nyet); + return 1; +} + +static int32_t handle_hc_stall_intr(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + IFX_ERROR( "--Host Channel %d Interrupt: " + "STALL--\n", _ifxhc->hc_num); + hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd); + disable_hc_int(_hc_regs,stall); + return 1; +} + +static int32_t handle_hc_xfercomp_intr(ifxhcd_hcd_t *_ifxhcd, + ifxhcd_hc_t *_ifxhc, + ifxusb_hc_regs_t *_hc_regs, + ifxhcd_urbd_t *_urbd) +{ + IFX_ERROR( "--Host Channel %d Interrupt: " + "XFERCOMP--\n", _ifxhc->hc_num); + hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd); + disable_hc_int(_hc_regs,xfercomp); + return 1; +} + + + +/* This interrupt indicates that the specified host channels has a pending + * interrupt. There are multiple conditions that can cause each host channel + * interrupt. This function determines which conditions have occurred for this + * host channel interrupt and handles them appropriately. */ +static int32_t handle_hc_n_intr (ifxhcd_hcd_t *_ifxhcd, uint32_t _num) +{ + uint32_t hcintval,hcintmsk; + hcint_data_t hcint; + ifxhcd_hc_t *ifxhc; + ifxusb_hc_regs_t *hc_regs; + ifxhcd_urbd_t *urbd; + unsigned long flags; + + int retval = 0; + + IFX_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", _num); + + /*== AVM/BC 20101111 Lock needed ==*/ + SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags); + + ifxhc = &_ifxhcd->ifxhc[_num]; + hc_regs = _ifxhcd->core_if.hc_regs[_num]; + + hcintval = ifxusb_rreg(&hc_regs->hcint); + hcintmsk = ifxusb_rreg(&hc_regs->hcintmsk); + hcint.d32 = hcintval & hcintmsk; + IFX_DEBUGPL(DBG_HCDV, " 0x%08x & 0x%08x = 0x%08x\n", + hcintval, hcintmsk, hcint.d32); + + urbd = list_entry(ifxhc->epqh->urbd_list.next, ifxhcd_urbd_t, urbd_list_entry); + + if (hcint.b.datatglerr) + retval |= handle_hc_datatglerr_intr(_ifxhcd, ifxhc, hc_regs, urbd); + if (hcint.b.frmovrun) + retval |= handle_hc_frmovrun_intr(_ifxhcd, ifxhc, hc_regs, urbd); + if (hcint.b.bblerr) + retval |= handle_hc_bblerr_intr(_ifxhcd, ifxhc, hc_regs, urbd); + if (hcint.b.xacterr) + retval |= handle_hc_xacterr_intr(_ifxhcd, ifxhc, hc_regs, urbd); + if (hcint.b.nyet) + retval |= handle_hc_nyet_intr(_ifxhcd, ifxhc, hc_regs, urbd); + if (hcint.b.ack) + retval |= handle_hc_ack_intr(_ifxhcd, ifxhc, hc_regs, urbd); + if (hcint.b.nak) + retval |= handle_hc_nak_intr(_ifxhcd, ifxhc, hc_regs, urbd); + if (hcint.b.stall) + retval |= handle_hc_stall_intr(_ifxhcd, ifxhc, hc_regs, urbd); + if (hcint.b.ahberr) { + clear_hc_int(hc_regs, ahberr); + retval |= handle_hc_ahberr_intr(_ifxhcd, ifxhc, hc_regs, urbd); + } + if (hcint.b.chhltd) { + /* == 20110901 AVM/WK Fix: Flag must not be cleared after restart of channel ==*/ + clear_hc_int(hc_regs, chhltd); + retval |= handle_hc_chhltd_intr(_ifxhcd, ifxhc, hc_regs, urbd); + } + if (hcint.b.xfercomp) + retval |= handle_hc_xfercomp_intr(_ifxhcd, ifxhc, hc_regs, urbd); + + /* == 20110901 AVM/WK Fix: Never clear possibly new intvals ==*/ + //ifxusb_wreg(&hc_regs->hcint,hcintval); + + SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); + + return retval; +} + + + + + + +static uint8_t update_interval_counter(ifxhcd_epqh_t *_epqh,uint32_t _diff) +{ + if(_diff>=_epqh->period_counter) + { + _epqh->period_do=1; + if(_diff>_epqh->interval) + _epqh->period_counter=1; + else + _epqh->period_counter=_epqh->period_counter+_epqh->interval-_diff; + return 1; + } + _epqh->period_counter=_epqh->period_counter-_diff; + return 0; +} + + + + +/* + * Handles the start-of-frame interrupt in host mode. Non-periodic + * transactions may be queued to the DWC_otg controller for the current + * (micro)frame. Periodic transactions may be queued to the controller for the + * next (micro)frame. + */ +static int32_t handle_sof_intr (ifxhcd_hcd_t *_ifxhcd) +{ + #ifdef __DYN_SOF_INTR__ + uint8_t with_count_down=0; + #endif + uint8_t active_on=0; + uint8_t ready_on=0; + struct list_head *epqh_entry; + ifxhcd_epqh_t *epqh; + hfnum_data_t hfnum; + uint32_t fndiff; + + unsigned long flags; +#ifdef __USE_TIMER_4_SOF__ + uint32_t wait_for_sof = 0x10000; +#endif + + SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags); + + { + int num_channels; + ifxusb_hc_regs_t *hc_regs; + int i; + num_channels = _ifxhcd->core_if.params.host_channels; + +// AVM/WK moved block here due to use of SOF timer + hfnum.d32 = ifxusb_rreg(&_ifxhcd->core_if.host_global_regs->hfnum); + fndiff = hfnum.b.frnum; + fndiff+= 0x00004000; + fndiff-= _ifxhcd->lastframe ; + fndiff&= 0x00003FFF; + if(!fndiff) fndiff =1; + + for (i = 0; i < num_channels; i++) + { + if(_ifxhcd->ifxhc[i].wait_for_sof && _ifxhcd->ifxhc[i].xfer_started) + { +#ifdef __USE_TIMER_4_SOF__ + if (_ifxhcd->ifxhc[i].wait_for_sof > fndiff) { + _ifxhcd->ifxhc[i].wait_for_sof -= fndiff; + } else { + _ifxhcd->ifxhc[i].wait_for_sof = 0; + } +#else + _ifxhcd->ifxhc[i].wait_for_sof--; +#endif + if(_ifxhcd->ifxhc[i].wait_for_sof==0) + { + hcint_data_t hcint= { .d32=0 }; + hc_regs = _ifxhcd->core_if.hc_regs[i]; + + hcint.d32 =0xFFFFFFFF; + ifxusb_wreg(&hc_regs->hcint, hcint.d32); + + hcint.d32=ifxusb_rreg(&hc_regs->hcintmsk); + hcint.b.nak =0; + hcint.b.ack =0; + /* == 20110901 AVM/WK Fix: We don't need NOT YET IRQ ==*/ + hcint.b.nyet=0; + _ifxhcd->ifxhc[i].nak_countdown=_ifxhcd->ifxhc[i].nak_countdown_r; + if(_ifxhcd->ifxhc[i].nak_countdown_r) + hcint.b.nak =1; + ifxusb_wreg(&hc_regs->hcintmsk, hcint.d32); + + /* AVM WK / BC 20100827 + * FIX: Packet was ignored because of wrong Oddframe bit + */ + if (_ifxhcd->ifxhc[i].ep_type == IFXUSB_EP_TYPE_INTR || _ifxhcd->ifxhc[i].ep_type == IFXUSB_EP_TYPE_ISOC) + { + hcchar_data_t hcchar; + hcchar.d32 = _ifxhcd->ifxhc[i].hcchar; + hfnum.d32 = ifxusb_rreg(&_ifxhcd->core_if.host_global_regs->hfnum); + /* 1 if _next_ frame is odd, 0 if it's even */ + hcchar.b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1; + _ifxhcd->ifxhc[i].hcchar = hcchar.d32; + } + + ifxusb_wreg(&hc_regs->hcchar, _ifxhcd->ifxhc[i].hcchar); + + } + } + else + _ifxhcd->ifxhc[i].wait_for_sof=0; + +#ifdef __USE_TIMER_4_SOF__ + if (_ifxhcd->ifxhc[i].wait_for_sof && (wait_for_sof > _ifxhcd->ifxhc[i].wait_for_sof)) { + wait_for_sof = _ifxhcd->ifxhc[i].wait_for_sof; + } +#endif + } + } + + // ISOC Active + #ifdef __EN_ISOC__ + #error ISOC not supported: missing SOF code + epqh_entry = _ifxhcd->epqh_isoc_active.next; + while (epqh_entry != &_ifxhcd->epqh_isoc_active) + { + epqh = list_entry(epqh_entry, ifxhcd_epqh_t, epqh_list_entry); + epqh_entry = epqh_entry->next; + #ifdef __DYN_SOF_INTR__ + with_count_down=1; + #endif + active_on+=update_interval_counter(epqh,fndiff); + } + + // ISOC Ready + epqh_entry = _ifxhcd->epqh_isoc_ready.next; + while (epqh_entry != &_ifxhcd->epqh_isoc_ready) + { + epqh = list_entry(epqh_entry, ifxhcd_epqh_t, epqh_list_entry); + epqh_entry = epqh_entry->next; + #ifdef __DYN_SOF_INTR__ + with_count_down=1; + #endif + ready_on+=update_interval_counter(epqh,fndiff); + } + #endif + + // INTR Active + epqh_entry = _ifxhcd->epqh_intr_active.next; + while (epqh_entry != &_ifxhcd->epqh_intr_active) + { + epqh = list_entry(epqh_entry, ifxhcd_epqh_t, epqh_list_entry); + epqh_entry = epqh_entry->next; + #ifdef __DYN_SOF_INTR__ + with_count_down=1; + #endif +#ifdef __USE_TIMER_4_SOF__ + if (update_interval_counter(epqh,fndiff)) { + active_on ++; + wait_for_sof = 1; + } else { + if (epqh->period_counter && (wait_for_sof > epqh->period_counter)) { + wait_for_sof = epqh->period_counter; + } + } +#else + active_on+=update_interval_counter(epqh,fndiff); +#endif + } + + // INTR Ready + epqh_entry = _ifxhcd->epqh_intr_ready.next; + while (epqh_entry != &_ifxhcd->epqh_intr_ready) + { + epqh = list_entry(epqh_entry, ifxhcd_epqh_t, epqh_list_entry); + epqh_entry = epqh_entry->next; + #ifdef __DYN_SOF_INTR__ + with_count_down=1; + #endif +#ifdef __USE_TIMER_4_SOF__ + if (update_interval_counter(epqh,fndiff)) { + ready_on ++; + wait_for_sof = 1; + } else { + if (epqh->period_counter && (wait_for_sof > epqh->period_counter)) { + wait_for_sof = epqh->period_counter; + } + } +#else + ready_on+=update_interval_counter(epqh,fndiff); +#endif + } + + // Stdby + epqh_entry = _ifxhcd->epqh_stdby.next; + while (epqh_entry != &_ifxhcd->epqh_stdby) + { + epqh = list_entry(epqh_entry, ifxhcd_epqh_t, epqh_list_entry); + epqh_entry = epqh_entry->next; + if(epqh->period_counter > 0 ) { +#ifdef __USE_TIMER_4_SOF__ + if (epqh->period_counter > fndiff) { + epqh->period_counter -= fndiff; + } else { + epqh->period_counter = 0; + } +#else + epqh->period_counter --; +#endif + #ifdef __DYN_SOF_INTR__ + with_count_down=1; + #endif + } + if(epqh->period_counter == 0) { + ifxhcd_epqh_idle_periodic(epqh); + } +#ifdef __USE_TIMER_4_SOF__ + else { + if (wait_for_sof > epqh->period_counter) { + wait_for_sof = epqh->period_counter; + } + } +#endif + } + SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); + + if(ready_on) + select_eps(_ifxhcd); + else if(active_on) + process_channels(_ifxhcd); + + /* Clear interrupt */ + { + gint_data_t gintsts; + gintsts.d32=0; + gintsts.b.sofintr = 1; + ifxusb_wreg(&_ifxhcd->core_if.core_global_regs->gintsts, gintsts.d32); + + #ifdef __DYN_SOF_INTR__ + if(!with_count_down) + ifxusb_mreg(&_ifxhcd->core_if.core_global_regs->gintmsk, gintsts.d32,0); + #endif +#ifdef __USE_TIMER_4_SOF__ + wait_for_sof &= 0xFFFF; // reduce to 16 Bits. + + if(wait_for_sof == 1) { + // enable SOF + gint_data_t gintsts; + gintsts.d32=0; + gintsts.b.sofintr = 1; + ifxusb_mreg(&_ifxhcd->core_if.core_global_regs->gintmsk, 0,gintsts.d32); + } else { + // disable SOF + ifxusb_mreg(&_ifxhcd->core_if.core_global_regs->gintmsk, gintsts.d32,0); + if (wait_for_sof > 1) { + // use timer, not SOF IRQ + hprt0_data_t hprt0; + ktime_t ktime; + hprt0.d32 = ifxusb_read_hprt0 (&_ifxhcd->core_if); + if (hprt0.b.prtspd == IFXUSB_HPRT0_PRTSPD_HIGH_SPEED) { + ktime = ktime_set(0, wait_for_sof * 125 * 1000); /*--- wakeup in n*125usec ---*/ + } else { + ktime = ktime_set(0, wait_for_sof * (1000*1000)); /*--- wakeup in n*1000usec ---*/ + } + hrtimer_start(&_ifxhcd->hr_timer, ktime, HRTIMER_MODE_REL); + } + } +#endif + } + _ifxhcd->lastframe=hfnum.b.frnum; + return 1; +} + + + +/* There are multiple conditions that can cause a port interrupt. This function + * determines which interrupt conditions have occurred and handles them + * appropriately. */ +static int32_t handle_port_intr (ifxhcd_hcd_t *_ifxhcd) +{ + int retval = 0; + hprt0_data_t hprt0; + hprt0_data_t hprt0_modify; + + hprt0.d32 = + hprt0_modify.d32 = ifxusb_rreg(_ifxhcd->core_if.hprt0); + + /* Clear appropriate bits in HPRT0 to clear the interrupt bit in + * GINTSTS */ + + hprt0_modify.b.prtena = 0; + hprt0_modify.b.prtconndet = 0; + hprt0_modify.b.prtenchng = 0; + hprt0_modify.b.prtovrcurrchng = 0; + + /* Port Connect Detected + * Set flag and clear if detected */ + if (hprt0.b.prtconndet) { + IFX_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x " + "Port Connect Detected--\n", hprt0.d32); + _ifxhcd->flags.b.port_connect_status_change = 1; + _ifxhcd->flags.b.port_connect_status = 1; + hprt0_modify.b.prtconndet = 1; + + /* The Hub driver asserts a reset when it sees port connect + * status change flag */ + retval |= 1; + } + + /* Port Enable Changed + * Clear if detected - Set internal flag if disabled */ + if (hprt0.b.prtenchng) { + + IFX_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " + "Port Enable Changed--\n", hprt0.d32); + hprt0_modify.b.prtenchng = 1; + if (hprt0.b.prtena == 1) + /* Port has been enabled set the reset change flag */ + _ifxhcd->flags.b.port_reset_change = 1; + else + _ifxhcd->flags.b.port_enable_change = 1; + retval |= 1; + } + + /* Overcurrent Change Interrupt */ + + if (hprt0.b.prtovrcurrchng) { + IFX_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " + "Port Overcurrent Changed--\n", hprt0.d32); + _ifxhcd->flags.b.port_over_current_change = 1; + hprt0_modify.b.prtovrcurrchng = 1; + retval |= 1; + } + + /* Clear Port Interrupts */ + ifxusb_wreg(_ifxhcd->core_if.hprt0, hprt0_modify.d32); + return retval; +} + +/* + * This interrupt indicates that SUSPEND state has been detected on + * the USB. + * No Functioning in Host Mode + */ +static int32_t handle_usb_suspend_intr(ifxhcd_hcd_t *_ifxhcd) +{ + gint_data_t gintsts; + IFX_DEBUGP("USB SUSPEND RECEIVED!\n"); + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.usbsuspend = 1; + ifxusb_wreg(&_ifxhcd->core_if.core_global_regs->gintsts, gintsts.d32); + return 1; +} + +/* + * This interrupt indicates that the IFXUSB controller has detected a + * resume or remote wakeup sequence. If the IFXUSB controller is in + * low power mode, the handler must brings the controller out of low + * power mode. The controller automatically begins resume + * signaling. The handler schedules a time to stop resume signaling. + */ +static int32_t handle_wakeup_detected_intr(ifxhcd_hcd_t *_ifxhcd) +{ + gint_data_t gintsts; + hprt0_data_t hprt0 = {.d32=0}; + pcgcctl_data_t pcgcctl = {.d32=0}; + ifxusb_core_if_t *core_if = &_ifxhcd->core_if; + + IFX_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n"); + + /* + * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms + * so that OPT tests pass with all PHYs). + */ + /* Restart the Phy Clock */ + pcgcctl.b.stoppclk = 1; + ifxusb_mreg(core_if->pcgcctl, pcgcctl.d32, 0); + UDELAY(10); + + /* Now wait for 70 ms. */ + hprt0.d32 = ifxusb_read_hprt0( core_if ); + IFX_DEBUGPL(DBG_ANY,"Resume: HPRT0=%0x\n", hprt0.d32); + MDELAY(70); + hprt0.b.prtres = 0; /* Resume */ + ifxusb_wreg(core_if->hprt0, hprt0.d32); + IFX_DEBUGPL(DBG_ANY,"Clear Resume: HPRT0=%0x\n", ifxusb_rreg(core_if->hprt0)); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.wkupintr = 1; + ifxusb_wreg(&core_if->core_global_regs->gintsts, gintsts.d32); + return 1; +} + +/* + * This interrupt indicates that a device is initiating the Session + * Request Protocol to request the host to turn on bus power so a new + * session can begin. The handler responds by turning on bus power. If + * the DWC_otg controller is in low power mode, the handler brings the + * controller out of low power mode before turning on bus power. + */ +static int32_t handle_session_req_intr(ifxhcd_hcd_t *_ifxhcd) +{ + /* Clear interrupt */ + gint_data_t gintsts = { .d32 = 0 }; + gintsts.b.sessreqintr = 1; + ifxusb_wreg(&_ifxhcd->core_if.core_global_regs->gintsts, gintsts.d32); + return 1; +} + +/* + * This interrupt indicates that a device has been disconnected from + * the root port. + */ +static int32_t handle_disconnect_intr(ifxhcd_hcd_t *_ifxhcd) +{ + gint_data_t gintsts; + + ifxhcd_disconnect(_ifxhcd); + + gintsts.d32 = 0; + gintsts.b.disconnect = 1; + ifxusb_wreg(&_ifxhcd->core_if.core_global_regs->gintsts, gintsts.d32); + return 1; +} + +/* + * This function handles the Connector ID Status Change Interrupt. It + * reads the OTG Interrupt Register (GOTCTL) to determine whether this + * is a Device to Host Mode transition or a Host Mode to Device + * Transition. + * This only occurs when the cable is connected/removed from the PHY + * connector. + */ +static int32_t handle_conn_id_status_change_intr(ifxhcd_hcd_t *_ifxhcd) +{ + gint_data_t gintsts; + + IFX_WARN("ID Status Change Interrupt: currently in %s mode\n", + ifxusb_mode(&_ifxhcd->core_if) ? "Host" : "Device"); + + gintsts.d32 = 0; + gintsts.b.conidstschng = 1; + ifxusb_wreg(&_ifxhcd->core_if.core_global_regs->gintsts, gintsts.d32); + return 1; +} + +static int32_t handle_otg_intr(ifxhcd_hcd_t *_ifxhcd) +{ + ifxusb_core_global_regs_t *global_regs = _ifxhcd->core_if.core_global_regs; + gotgint_data_t gotgint; + gotgint.d32 = ifxusb_rreg( &global_regs->gotgint); + /* Clear GOTGINT */ + ifxusb_wreg (&global_regs->gotgint, gotgint.d32); + return 1; +} + +/** This function will log a debug message */ +static int32_t handle_mode_mismatch_intr(ifxhcd_hcd_t *_ifxhcd) +{ + gint_data_t gintsts; + + IFX_WARN("Mode Mismatch Interrupt: currently in %s mode\n", + ifxusb_mode(&_ifxhcd->core_if) ? "Host" : "Device"); + gintsts.d32 = 0; + gintsts.b.modemismatch = 1; + ifxusb_wreg(&_ifxhcd->core_if.core_global_regs->gintsts, gintsts.d32); + return 1; +} + +/** This function handles interrupts for the HCD. */ +int32_t ifxhcd_handle_intr (ifxhcd_hcd_t *_ifxhcd) +{ + int retval = 0; + + ifxusb_core_if_t *core_if = &_ifxhcd->core_if; + /* AVM/BC 20101111 Unnecesary variable removed*/ + //gint_data_t gintsts,gintsts2; + gint_data_t gintsts; + + /* Check if HOST Mode */ + if (ifxusb_is_device_mode(core_if)) + { + IFX_ERROR("%s() CRITICAL! IN DEVICE MODE\n", __func__); + return 0; + } + + gintsts.d32 = ifxusb_read_core_intr(core_if); + + if (!gintsts.d32) + return 0; + + //Common INT + if (gintsts.b.modemismatch) + { + retval |= handle_mode_mismatch_intr(_ifxhcd); + gintsts.b.modemismatch=0; + } + if (gintsts.b.otgintr) + { + retval |= handle_otg_intr(_ifxhcd); + gintsts.b.otgintr=0; + } + if (gintsts.b.conidstschng) + { + retval |= handle_conn_id_status_change_intr(_ifxhcd); + gintsts.b.conidstschng=0; + } + if (gintsts.b.disconnect) + { + retval |= handle_disconnect_intr(_ifxhcd); + gintsts.b.disconnect=0; + } + if (gintsts.b.sessreqintr) + { + retval |= handle_session_req_intr(_ifxhcd); + gintsts.b.sessreqintr=0; + } + if (gintsts.b.wkupintr) + { + retval |= handle_wakeup_detected_intr(_ifxhcd); + gintsts.b.wkupintr=0; + } + if (gintsts.b.usbsuspend) + { + retval |= handle_usb_suspend_intr(_ifxhcd); + gintsts.b.usbsuspend=0; + } + + //Host Int + if (gintsts.b.sofintr) + { + retval |= handle_sof_intr (_ifxhcd); + gintsts.b.sofintr=0; + } + if (gintsts.b.portintr) + { + retval |= handle_port_intr (_ifxhcd); + gintsts.b.portintr=0; + } + if (gintsts.b.hcintr) + { + int i; + haint_data_t haint; + haint.d32 = ifxusb_read_host_all_channels_intr(core_if); + for (i=0; i< core_if->params.host_channels; i++) + if (haint.b2.chint & (1 << i)) + retval |= handle_hc_n_intr (_ifxhcd, i); + gintsts.b.hcintr=0; + } + return retval; +} diff --git a/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxhcd_queue.c b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxhcd_queue.c new file mode 100644 index 0000000000..8f9dd25745 --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxhcd_queue.c @@ -0,0 +1,418 @@ +/***************************************************************************** + ** FILE NAME : ifxhcd_queue.c + ** PROJECT : IFX USB sub-system V3 + ** MODULES : IFX USB sub-system Host and Device driver + ** SRC VERSION : 1.0 + ** DATE : 1/Jan/2009 + ** AUTHOR : Chen, Howard + ** DESCRIPTION : This file contains the functions to manage Queue Heads and Queue + ** Transfer Descriptors. + *****************************************************************************/ + +/*! + \file ifxhcd_queue.c + \ingroup IFXUSB_DRIVER_V3 + \brief This file contains the functions to manage Queue Heads and Queue + Transfer Descriptors. +*/ +#include +#include "ifxusb_version.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ifxusb_plat.h" +#include "ifxusb_regs.h" +#include "ifxusb_cif.h" +#include "ifxhcd.h" + +#ifdef __EPQD_DESTROY_TIMEOUT__ + #define epqh_self_destroy_timeout 5 + static void eqph_destroy_func(unsigned long _ptr) + { + ifxhcd_epqh_t *epqh=(ifxhcd_epqh_t *)_ptr; + if(epqh) + { + ifxhcd_epqh_free (epqh); + } + } +#endif + +#define SCHEDULE_SLOP 10 + +/*! + \brief This function allocates and initializes a EPQH. + + \param _ifxhcd The HCD state structure for the USB Host controller. + \param[in] _urb Holds the information about the device/endpoint that we need + to initialize the EPQH. + + \return Returns pointer to the newly allocated EPQH, or NULL on error. + */ +ifxhcd_epqh_t *ifxhcd_epqh_create (ifxhcd_hcd_t *_ifxhcd, struct urb *_urb) +{ + ifxhcd_epqh_t *epqh; + + hprt0_data_t hprt0; + struct usb_host_endpoint *sysep = ifxhcd_urb_to_endpoint(_urb); + + /* Allocate memory */ +// epqh=(ifxhcd_epqh_t *) kmalloc (sizeof(ifxhcd_epqh_t), GFP_KERNEL); + epqh=(ifxhcd_epqh_t *) kmalloc (sizeof(ifxhcd_epqh_t), GFP_ATOMIC); + + if(epqh == NULL) + return NULL; + + memset (epqh, 0, sizeof (ifxhcd_epqh_t)); + + epqh->sysep=sysep; + + /* Initialize EPQH */ + switch (usb_pipetype(_urb->pipe)) + { + case PIPE_CONTROL : epqh->ep_type = IFXUSB_EP_TYPE_CTRL; break; + case PIPE_BULK : epqh->ep_type = IFXUSB_EP_TYPE_BULK; break; + case PIPE_ISOCHRONOUS: epqh->ep_type = IFXUSB_EP_TYPE_ISOC; break; + case PIPE_INTERRUPT : epqh->ep_type = IFXUSB_EP_TYPE_INTR; break; + } + + //epqh->data_toggle = IFXUSB_HC_PID_DATA0; + + epqh->mps = usb_maxpacket(_urb->dev, _urb->pipe, !(usb_pipein(_urb->pipe))); + + hprt0.d32 = ifxusb_read_hprt0 (&_ifxhcd->core_if); + + INIT_LIST_HEAD(&epqh->urbd_list); + INIT_LIST_HEAD(&epqh->epqh_list_entry); + epqh->hc = NULL; + + epqh->dump_buf = ifxusb_alloc_buf(epqh->mps, 0); + + /* FS/LS Enpoint on HS Hub + * NOT virtual root hub */ + epqh->need_split = 0; + epqh->pkt_count_limit=0; + if(epqh->ep_type == IFXUSB_EP_TYPE_BULK && !(usb_pipein(_urb->pipe)) ) + epqh->pkt_count_limit=4; + if (hprt0.b.prtspd == IFXUSB_HPRT0_PRTSPD_HIGH_SPEED && + ((_urb->dev->speed == USB_SPEED_LOW) || + (_urb->dev->speed == USB_SPEED_FULL)) && + (_urb->dev->tt) && (_urb->dev->tt->hub->devnum != 1)) + { + IFX_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n", + usb_pipeendpoint(_urb->pipe), _urb->dev->tt->hub->devnum, + _urb->dev->ttport); + epqh->need_split = 1; + epqh->pkt_count_limit=1; + } + + if (epqh->ep_type == IFXUSB_EP_TYPE_INTR || + epqh->ep_type == IFXUSB_EP_TYPE_ISOC) + { + /* Compute scheduling parameters once and save them. */ + epqh->interval = _urb->interval; + if(epqh->need_split) + epqh->interval *= 8; + } + + epqh->period_counter=0; + epqh->is_active=0; + + #ifdef __EPQD_DESTROY_TIMEOUT__ + /* Start a timer for this transfer. */ + init_timer(&epqh->destroy_timer); + epqh->destroy_timer.function = eqph_destroy_func; + epqh->destroy_timer.data = (unsigned long)(epqh); + #endif + + #ifdef __DEBUG__ + IFX_DEBUGPL(DBG_HCD , "IFXUSB HCD EPQH Initialized\n"); + IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - epqh = %p\n", epqh); + IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - Device Address = %d EP %d, %s\n", + _urb->dev->devnum, + usb_pipeendpoint(_urb->pipe), + usb_pipein(_urb->pipe) == USB_DIR_IN ? "IN" : "OUT"); + IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - Speed = %s\n", + ({ char *speed; switch (_urb->dev->speed) { + case USB_SPEED_LOW: speed = "low" ; break; + case USB_SPEED_FULL: speed = "full"; break; + case USB_SPEED_HIGH: speed = "high"; break; + default: speed = "?"; break; + }; speed;})); + IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - Type = %s\n", + ({ + char *type; switch (epqh->ep_type) + { + case IFXUSB_EP_TYPE_ISOC: type = "isochronous"; break; + case IFXUSB_EP_TYPE_INTR: type = "interrupt" ; break; + case IFXUSB_EP_TYPE_CTRL: type = "control" ; break; + case IFXUSB_EP_TYPE_BULK: type = "bulk" ; break; + default: type = "?"; break; + }; + type; + })); + if (epqh->ep_type == IFXUSB_EP_TYPE_INTR) + IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - interval = %d\n", epqh->interval); + #endif + + return epqh; +} + + + + + + +/*! + \brief Free the EPQH. EPQH should already be removed from a list. + URBD list should already be empty if called from URB Dequeue. + + \param[in] _epqh The EPQH to free. + */ +void ifxhcd_epqh_free (ifxhcd_epqh_t *_epqh) +{ + unsigned long flags; + + if(_epqh->sysep) _epqh->sysep->hcpriv=NULL; + _epqh->sysep=NULL; + + if(!_epqh) + return; + + /* Free each QTD in the QTD list */ + local_irq_save (flags); + if (!list_empty(&_epqh->urbd_list)) + IFX_WARN("%s() invalid epqh state\n",__func__); + + #if defined(__UNALIGNED_BUFFER_ADJ__) + if(_epqh->aligned_buf) + ifxusb_free_buf(_epqh->aligned_buf); + if(_epqh->aligned_setup) + ifxusb_free_buf(_epqh->aligned_setup); + #endif + + if (!list_empty(&_epqh->epqh_list_entry)) + list_del_init(&_epqh->epqh_list_entry); + + #ifdef __EPQD_DESTROY_TIMEOUT__ + del_timer(&_epqh->destroy_timer); + #endif + if(_epqh->dump_buf) + ifxusb_free_buf(_epqh->dump_buf); + _epqh->dump_buf=0; + + + kfree (_epqh); + local_irq_restore (flags); +} + +/*! + \brief This function adds a EPQH to + + \return 0 if successful, negative error code otherwise. + */ +void ifxhcd_epqh_ready(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh) +{ + unsigned long flags; + local_irq_save(flags); + if (list_empty(&_epqh->epqh_list_entry)) + { + #ifdef __EN_ISOC__ + if (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC) + list_add_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_ready); + else + #endif + if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR) + list_add_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_ready); + else + list_add_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_ready); + _epqh->is_active=0; + } + else if(!_epqh->is_active) + { + #ifdef __EN_ISOC__ + if (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC) + list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_ready); + else + #endif + if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR) + list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_ready); + else + list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_ready); + } + #ifdef __EPQD_DESTROY_TIMEOUT__ + del_timer(&_epqh->destroy_timer); + #endif + local_irq_restore(flags); +} + +void ifxhcd_epqh_active(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh) +{ + unsigned long flags; + local_irq_save(flags); + if (list_empty(&_epqh->epqh_list_entry)) + IFX_WARN("%s() invalid epqh state\n",__func__); + #ifdef __EN_ISOC__ + if (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC) + list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_active); + else + #endif + if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR) + list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_active); + else + list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_active); + _epqh->is_active=1; + #ifdef __EPQD_DESTROY_TIMEOUT__ + del_timer(&_epqh->destroy_timer); + #endif + local_irq_restore(flags); +} + +void ifxhcd_epqh_idle(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh) +{ + unsigned long flags; + local_irq_save(flags); + + if (list_empty(&_epqh->urbd_list)) + { + if(_epqh->ep_type == IFXUSB_EP_TYPE_ISOC || _epqh->ep_type == IFXUSB_EP_TYPE_INTR) + { + list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_stdby); + } + else + { + list_del_init(&_epqh->epqh_list_entry); + #ifdef __EPQD_DESTROY_TIMEOUT__ + del_timer(&_epqh->destroy_timer); + _epqh->destroy_timer.expires = jiffies + (HZ*epqh_self_destroy_timeout); + add_timer(&_epqh->destroy_timer ); + #endif + } + } + else + { + #ifdef __EN_ISOC__ + if (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC) + list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_ready); + else + #endif + if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR) + list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_ready); + else + list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_ready); + } + _epqh->is_active=0; + local_irq_restore(flags); +} + + +void ifxhcd_epqh_idle_periodic(ifxhcd_epqh_t *_epqh) +{ + unsigned long flags; + if(_epqh->ep_type != IFXUSB_EP_TYPE_ISOC && _epqh->ep_type != IFXUSB_EP_TYPE_INTR) + return; + + local_irq_save(flags); + + if (list_empty(&_epqh->epqh_list_entry)) + IFX_WARN("%s() invalid epqh state\n",__func__); + if (!list_empty(&_epqh->urbd_list)) + IFX_WARN("%s() invalid epqh state(not empty)\n",__func__); + + _epqh->is_active=0; + list_del_init(&_epqh->epqh_list_entry); + #ifdef __EPQD_DESTROY_TIMEOUT__ + del_timer(&_epqh->destroy_timer); + _epqh->destroy_timer.expires = jiffies + (HZ*epqh_self_destroy_timeout); + add_timer(&_epqh->destroy_timer ); + #endif + + local_irq_restore(flags); +} + + +int ifxhcd_urbd_create (ifxhcd_hcd_t *_ifxhcd,struct urb *_urb) +{ + ifxhcd_urbd_t *urbd; + struct usb_host_endpoint *sysep; + ifxhcd_epqh_t *epqh; + unsigned long flags; + /* == AVM/WK 20100714 retval correctly initialized ==*/ + int retval = -ENOMEM; + + /*== AVM/BC 20100630 - Spinlock ==*/ + //local_irq_save(flags); + SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags); + +// urbd = (ifxhcd_urbd_t *) kmalloc (sizeof(ifxhcd_urbd_t), GFP_KERNEL); + urbd = (ifxhcd_urbd_t *) kmalloc (sizeof(ifxhcd_urbd_t), GFP_ATOMIC); + if (urbd != NULL) /* Initializes a QTD structure.*/ + { + retval = 0; + memset (urbd, 0, sizeof (ifxhcd_urbd_t)); + + sysep = ifxhcd_urb_to_endpoint(_urb); + epqh = (ifxhcd_epqh_t *)sysep->hcpriv; + if (epqh == NULL) + { + epqh = ifxhcd_epqh_create (_ifxhcd, _urb); + if (epqh == NULL) + { + retval = -ENOSPC; + kfree(urbd); + //local_irq_restore (flags); + SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); + return retval; + } + sysep->hcpriv = epqh; + } + + INIT_LIST_HEAD(&urbd->urbd_list_entry); + + /*== AVM/BC 20100630 - 2.6.28 needs HCD link/unlink URBs ==*/ + retval = usb_hcd_link_urb_to_ep(ifxhcd_to_syshcd(_ifxhcd), _urb); + + if (unlikely(retval)){ + kfree(urbd); + kfree(epqh); + SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); + return retval; + } + + list_add_tail(&urbd->urbd_list_entry, &epqh->urbd_list); + urbd->urb = _urb; + _urb->hcpriv = urbd; + + urbd->epqh=epqh; + urbd->is_in=usb_pipein(_urb->pipe) ? 1 : 0;; + + urbd->xfer_len=_urb->transfer_buffer_length; +#define URB_NO_SETUP_DMA_MAP 0 + + if(urbd->xfer_len>0) + { + if(_urb->transfer_flags && URB_NO_TRANSFER_DMA_MAP) + urbd->xfer_buff = (uint8_t *) (KSEG1ADDR((uint32_t *)_urb->transfer_dma)); + else + urbd->xfer_buff = (uint8_t *) _urb->transfer_buffer; + } + if(epqh->ep_type == IFXUSB_EP_TYPE_CTRL) + { + if(_urb->transfer_flags && URB_NO_SETUP_DMA_MAP) + urbd->setup_buff = (uint8_t *) (KSEG1ADDR((uint32_t *)_urb->setup_dma)); + else + urbd->setup_buff = (uint8_t *) _urb->setup_packet; + } + } + //local_irq_restore (flags); + SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); + return retval; +} + diff --git a/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_cif.c b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_cif.c new file mode 100644 index 0000000000..10b12927cf --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_cif.c @@ -0,0 +1,1458 @@ +/***************************************************************************** + ** FILE NAME : ifxusb_cif.c + ** PROJECT : IFX USB sub-system V3 + ** MODULES : IFX USB sub-system Host and Device driver + ** SRC VERSION : 1.0 + ** DATE : 1/Jan/2009 + ** AUTHOR : Chen, Howard + ** DESCRIPTION : The Core Interface provides basic services for accessing and + ** managing the IFX USB hardware. These services are used by both the + ** Host Controller Driver and the Peripheral Controller Driver. + *****************************************************************************/ + +/*! + \file ifxusb_cif.c + \ingroup IFXUSB_DRIVER_V3 + \brief This file contains the interface to the IFX USB Core. +*/ + +#include +#include +#include "ifxusb_version.h" + +#include +#include + + +#include +#include +#include +#include + +#if defined(__UEIP__) +// #include +// #include +#endif + + +#include "ifxusb_plat.h" +#include "ifxusb_regs.h" +#include "ifxusb_cif.h" + + +#ifdef __IS_DEVICE__ + #include "ifxpcd.h" +#endif + +#ifdef __IS_HOST__ + #include "ifxhcd.h" +#endif + +#include + +#include + +#if defined(__UEIP__) +// #include + //#include +#endif + +//#include +//#include +#if defined(__UEIP__) +// #include + //#include +#endif + + + +#if defined(__UEIP__) + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) + #ifndef USB_CTRL_PMU_SETUP + #define USB_CTRL_PMU_SETUP(__x) USB0_CTRL_PMU_SETUP(__x) + #endif + #ifndef USB_PHY_PMU_SETUP + #define USB_PHY_PMU_SETUP(__x) USB0_PHY_PMU_SETUP(__x) + #endif + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) +#endif // defined(__UEIP__) + +/*! + \brief This function is called to allocate buffer of specified size. + The allocated buffer is mapped into DMA accessable address. + \param size Size in BYTE to be allocated + \param clear 0: don't do clear after buffer allocated, other: do clear to zero + \return 0/NULL: Fail; uncached pointer of allocated buffer + */ +void *ifxusb_alloc_buf(size_t size, int clear) +{ + uint32_t *cached,*uncached; + uint32_t totalsize,page; + + if(!size) + return 0; + + size=(size+3)&0xFFFFFFFC; + totalsize=size + 12; + page=get_order(totalsize); + + cached = (void *) __get_free_pages(( GFP_ATOMIC | GFP_DMA), page); + + if(!cached) + { + IFX_PRINT("%s Allocation Failed size:%d\n",__func__,size); + return NULL; + } + + uncached = (uint32_t *)(KSEG1ADDR(cached)); + if(clear) + memset(uncached, 0, totalsize); + + *(uncached+0)=totalsize; + *(uncached+1)=page; + *(uncached+2)=(uint32_t)cached; + return (void *)(uncached+3); +} + + +/*! + \brief This function is called to free allocated buffer. + \param vaddr the uncached pointer of the buffer + */ +void ifxusb_free_buf(void *vaddr) +{ + uint32_t totalsize,page; + uint32_t *cached,*uncached; + + if(vaddr != NULL) + { + uncached=vaddr; + uncached-=3; + totalsize=*(uncached+0); + page=*(uncached+1); + cached=(uint32_t *)(*(uncached+2)); + if(totalsize && page==get_order(totalsize) && cached==(uint32_t *)(KSEG0ADDR(uncached))) + { + free_pages((unsigned long)cached, page); + return; + } + // the memory is not allocated by ifxusb_alloc_buf. Allowed but must be careful. + return; + } +} + + + +/*! + \brief This function is called to initialize the IFXUSB CSR data + structures. The register addresses in the device and host + structures are initialized from the base address supplied by the + caller. The calling function must make the OS calls to get the + base address of the IFXUSB controller registers. + + \param _core_if Pointer of core_if structure + \param _irq irq number + \param _reg_base_addr Base address of IFXUSB core registers + \param _fifo_base_addr Fifo base address + \param _fifo_dbg_addr Fifo debug address + \return 0: success; + */ +int ifxusb_core_if_init(ifxusb_core_if_t *_core_if, + int _irq, + uint32_t _reg_base_addr, + uint32_t _fifo_base_addr, + uint32_t _fifo_dbg_addr) +{ + int retval = 0; + uint32_t *reg_base =NULL; + uint32_t *fifo_base =NULL; + uint32_t *fifo_dbg =NULL; + + int i; + + IFX_DEBUGPL(DBG_CILV, "%s(%p,%d,0x%08X,0x%08X,0x%08X)\n", __func__, + _core_if, + _irq, + _reg_base_addr, + _fifo_base_addr, + _fifo_dbg_addr); + + if( _core_if == NULL) + { + IFX_ERROR("%s() invalid _core_if\n", __func__); + retval = -ENOMEM; + goto fail; + } + + //memset(_core_if, 0, sizeof(ifxusb_core_if_t)); + + _core_if->irq=_irq; + + reg_base =ioremap_nocache(_reg_base_addr , IFXUSB_IOMEM_SIZE ); + fifo_base =ioremap_nocache(_fifo_base_addr, IFXUSB_FIFOMEM_SIZE); + fifo_dbg =ioremap_nocache(_fifo_dbg_addr , IFXUSB_FIFODBG_SIZE); + if( reg_base == NULL || fifo_base == NULL || fifo_dbg == NULL) + { + IFX_ERROR("%s() usb ioremap() failed\n", __func__); + retval = -ENOMEM; + goto fail; + } + + _core_if->core_global_regs = (ifxusb_core_global_regs_t *)reg_base; + + /* + * Attempt to ensure this device is really a IFXUSB Controller. + * Read and verify the SNPSID register contents. The value should be + * 0x45F42XXX + */ + { + int32_t snpsid; + snpsid = ifxusb_rreg(&_core_if->core_global_regs->gsnpsid); + if ((snpsid & 0xFFFFF000) != 0x4F542000) + { + IFX_ERROR("%s() snpsid error(0x%08x) failed\n", __func__,snpsid); + retval = -EINVAL; + goto fail; + } + _core_if->snpsid=snpsid; + } + + #ifdef __IS_HOST__ + _core_if->host_global_regs = (ifxusb_host_global_regs_t *) + ((uint32_t)reg_base + IFXUSB_HOST_GLOBAL_REG_OFFSET); + _core_if->hprt0 = (uint32_t*)((uint32_t)reg_base + IFXUSB_HOST_PORT_REGS_OFFSET); + + for (i=0; ihc_regs[i] = (ifxusb_hc_regs_t *) + ((uint32_t)reg_base + IFXUSB_HOST_CHAN_REGS_OFFSET + + (i * IFXUSB_CHAN_REGS_OFFSET)); + IFX_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n", + i, &_core_if->hc_regs[i]->hcchar); + } + #endif //__IS_HOST__ + + #ifdef __IS_DEVICE__ + _core_if->dev_global_regs = + (ifxusb_device_global_regs_t *)((uint32_t)reg_base + IFXUSB_DEV_GLOBAL_REG_OFFSET); + + for (i=0; iin_ep_regs[i] = (ifxusb_dev_in_ep_regs_t *) + ((uint32_t)reg_base + IFXUSB_DEV_IN_EP_REG_OFFSET + + (i * IFXUSB_EP_REG_OFFSET)); + _core_if->out_ep_regs[i] = (ifxusb_dev_out_ep_regs_t *) + ((uint32_t)reg_base + IFXUSB_DEV_OUT_EP_REG_OFFSET + + (i * IFXUSB_EP_REG_OFFSET)); + IFX_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p/%p %p/0x%08X/0x%08X\n", + i, &_core_if->in_ep_regs[i]->diepctl, _core_if->in_ep_regs[i], + reg_base,IFXUSB_DEV_IN_EP_REG_OFFSET,(i * IFXUSB_EP_REG_OFFSET) + ); + IFX_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p/%p %p/0x%08X/0x%08X\n", + i, &_core_if->out_ep_regs[i]->doepctl, _core_if->out_ep_regs[i], + reg_base,IFXUSB_DEV_OUT_EP_REG_OFFSET,(i * IFXUSB_EP_REG_OFFSET) + ); + } + #endif //__IS_DEVICE__ + + /* Setting the FIFO and other Address. */ + for (i=0; idata_fifo[i] = fifo_base + (i * IFXUSB_DATA_FIFO_SIZE); + IFX_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n", + i, (unsigned)_core_if->data_fifo[i]); + } + + _core_if->data_fifo_dbg = fifo_dbg; + _core_if->pcgcctl = (uint32_t*)(((uint32_t)reg_base) + IFXUSB_PCGCCTL_OFFSET); + + /* + * Store the contents of the hardware configuration registers here for + * easy access later. + */ + _core_if->hwcfg1.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg1); + _core_if->hwcfg2.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg2); + _core_if->hwcfg3.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg3); + _core_if->hwcfg4.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg4); + + IFX_DEBUGPL(DBG_CILV,"hwcfg1=%08x\n",_core_if->hwcfg1.d32); + IFX_DEBUGPL(DBG_CILV,"hwcfg2=%08x\n",_core_if->hwcfg2.d32); + IFX_DEBUGPL(DBG_CILV,"hwcfg3=%08x\n",_core_if->hwcfg3.d32); + IFX_DEBUGPL(DBG_CILV,"hwcfg4=%08x\n",_core_if->hwcfg4.d32); + + + #ifdef __DED_FIFO__ + IFX_PRINT("Waiting for PHY Clock Lock!\n"); + while(!( ifxusb_rreg(&_core_if->core_global_regs->grxfsiz) & (1<<9))) + { + } + IFX_PRINT("PHY Clock Locked!\n"); + //ifxusb_clean_spram(_core_if,128*1024/4); + #endif + + /* Create new workqueue and init works */ +#if 0 + _core_if->wq_usb = create_singlethread_workqueue(_core_if->core_name); + + if(_core_if->wq_usb == 0) + { + IFX_DEBUGPL(DBG_CIL, "Creation of wq_usb failed\n"); + retval = -EINVAL; + goto fail; + } + + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change, core_if); + INIT_WORK(&core_if->w_wkp, w_wakeup_detected, core_if); + #else + INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change); + INIT_DELAYED_WORK(&core_if->w_wkp, w_wakeup_detected); + #endif +#endif + return 0; + +fail: + if( reg_base != NULL) iounmap(reg_base ); + if( fifo_base != NULL) iounmap(fifo_base); + if( fifo_dbg != NULL) iounmap(fifo_dbg ); + return retval; +} + +/*! + \brief This function free the mapped address in the IFXUSB CSR data structures. + \param _core_if Pointer of core_if structure + */ +void ifxusb_core_if_remove(ifxusb_core_if_t *_core_if) +{ + /* Disable all interrupts */ + if( _core_if->core_global_regs != NULL) + { + ifxusb_mreg( &_core_if->core_global_regs->gahbcfg, 1, 0); + ifxusb_wreg( &_core_if->core_global_regs->gintmsk, 0); + } + + if( _core_if->core_global_regs != NULL) iounmap(_core_if->core_global_regs ); + if( _core_if->data_fifo[0] != NULL) iounmap(_core_if->data_fifo[0] ); + if( _core_if->data_fifo_dbg != NULL) iounmap(_core_if->data_fifo_dbg ); + +#if 0 + if (_core_if->wq_usb) + destroy_workqueue(_core_if->wq_usb); +#endif + memset(_core_if, 0, sizeof(ifxusb_core_if_t)); +} + + + + +/*! + \brief This function enbles the controller's Global Interrupt in the AHB Config register. + \param _core_if Pointer of core_if structure + */ +void ifxusb_enable_global_interrupts( ifxusb_core_if_t *_core_if ) +{ + gahbcfg_data_t ahbcfg ={ .d32 = 0}; + ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ + ifxusb_mreg(&_core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32); +} + +/*! + \brief This function disables the controller's Global Interrupt in the AHB Config register. + \param _core_if Pointer of core_if structure + */ +void ifxusb_disable_global_interrupts( ifxusb_core_if_t *_core_if ) +{ + gahbcfg_data_t ahbcfg ={ .d32 = 0}; + ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ + ifxusb_mreg(&_core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0); +} + + + + +/*! + \brief Flush Tx and Rx FIFO. + \param _core_if Pointer of core_if structure + */ +void ifxusb_flush_both_fifo( ifxusb_core_if_t *_core_if ) +{ + ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; + volatile grstctl_t greset ={ .d32 = 0}; + int count = 0; + + IFX_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__); + greset.b.rxfflsh = 1; + greset.b.txfflsh = 1; + greset.b.txfnum = 0x10; + greset.b.intknqflsh=1; + greset.b.hstfrm=1; + ifxusb_wreg( &global_regs->grstctl, greset.d32 ); + + do + { + greset.d32 = ifxusb_rreg( &global_regs->grstctl); + if (++count > 10000) + { + IFX_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, greset.d32); + break; + } + } while (greset.b.rxfflsh == 1 || greset.b.txfflsh == 1); + /* Wait for 3 PHY Clocks*/ + UDELAY(1); +} + +/*! + \brief Flush a Tx FIFO. + \param _core_if Pointer of core_if structure + \param _num Tx FIFO to flush. ( 0x10 for ALL TX FIFO ) + */ +void ifxusb_flush_tx_fifo( ifxusb_core_if_t *_core_if, const int _num ) +{ + ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; + volatile grstctl_t greset ={ .d32 = 0}; + int count = 0; + + IFX_DEBUGPL((DBG_CIL|DBG_PCDV), "Flush Tx FIFO %d\n", _num); + + greset.b.intknqflsh=1; + greset.b.txfflsh = 1; + greset.b.txfnum = _num; + ifxusb_wreg( &global_regs->grstctl, greset.d32 ); + + do + { + greset.d32 = ifxusb_rreg( &global_regs->grstctl); + if (++count > 10000&&(_num==0 ||_num==0x10)) + { + IFX_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", + __func__, greset.d32, + ifxusb_rreg( &global_regs->gnptxsts)); + break; + } + } while (greset.b.txfflsh == 1); + /* Wait for 3 PHY Clocks*/ + UDELAY(1); +} + + +/*! + \brief Flush Rx FIFO. + \param _core_if Pointer of core_if structure + */ +void ifxusb_flush_rx_fifo( ifxusb_core_if_t *_core_if ) +{ + ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; + volatile grstctl_t greset ={ .d32 = 0}; + int count = 0; + + IFX_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__); + greset.b.rxfflsh = 1; + ifxusb_wreg( &global_regs->grstctl, greset.d32 ); + + do + { + greset.d32 = ifxusb_rreg( &global_regs->grstctl); + if (++count > 10000) + { + IFX_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, greset.d32); + break; + } + } while (greset.b.rxfflsh == 1); + /* Wait for 3 PHY Clocks*/ + UDELAY(1); +} + + +#define SOFT_RESET_DELAY 100 + +/*! + \brief Do a soft reset of the core. Be careful with this because it + resets all the internal state machines of the core. + \param _core_if Pointer of core_if structure + */ +int ifxusb_core_soft_reset(ifxusb_core_if_t *_core_if) +{ + ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; + volatile grstctl_t greset ={ .d32 = 0}; + int count = 0; + + IFX_DEBUGPL(DBG_CILV, "%s\n", __func__); + /* Wait for AHB master IDLE state. */ + do + { + UDELAY(10); + greset.d32 = ifxusb_rreg( &global_regs->grstctl); + if (++count > 100000) + { + IFX_WARN("%s() HANG! AHB Idle GRSTCTL=%0x %x\n", __func__, + greset.d32, greset.b.ahbidle); + break; + } + } while (greset.b.ahbidle == 0); + + UDELAY(1); + + /* Core Soft Reset */ + count = 0; + greset.b.csftrst = 1; + ifxusb_wreg( &global_regs->grstctl, greset.d32 ); + + #ifdef SOFT_RESET_DELAY + MDELAY(SOFT_RESET_DELAY); + #endif + + do + { + UDELAY(10); + greset.d32 = ifxusb_rreg( &global_regs->grstctl); + if (++count > 100000) + { + IFX_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", __func__, greset.d32); + return -1; + } + } while (greset.b.csftrst == 1); + + #ifdef SOFT_RESET_DELAY + MDELAY(SOFT_RESET_DELAY); + #endif + + + #if defined(__IS_VR9__) + if(_core_if->core_no==0) + { + set_bit (4, VR9_RCU_USBRESET2); + MDELAY(50); + clear_bit (4, VR9_RCU_USBRESET2); + } + else + { + set_bit (5, VR9_RCU_USBRESET2); + MDELAY(50); + clear_bit (5, VR9_RCU_USBRESET2); + } + MDELAY(50); + #endif //defined(__IS_VR9__) + + IFX_PRINT("USB core #%d soft-reset\n",_core_if->core_no); + + return 0; +} + +/*! + \brief Turn on the USB Core Power + \param _core_if Pointer of core_if structure +*/ +void ifxusb_power_on (ifxusb_core_if_t *_core_if) +{ + struct clk *clk0 = clk_get_sys("usb0", NULL); + struct clk *clk1 = clk_get_sys("usb1", NULL); + // set clock gating + IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); + #if defined(__UEIP__) + + #if defined(__IS_TWINPASS) || defined(__IS_DANUBE__) + set_bit (4, (volatile unsigned long *)DANUBE_CGU_IFCCR); + set_bit (5, (volatile unsigned long *)DANUBE_CGU_IFCCR); + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined(__IS_AMAZON_SE__) + // clear_bit (4, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR); + clear_bit (5, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR); + #endif //defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) + set_bit (0, (volatile unsigned long *)AR9_CGU_IFCCR); + set_bit (1, (volatile unsigned long *)AR9_CGU_IFCCR); + #endif //defined(__IS_AR9__) + #if defined(__IS_VR9__) +// set_bit (0, (volatile unsigned long *)VR9_CGU_IFCCR); +// set_bit (1, (volatile unsigned long *)VR9_CGU_IFCCR); + #endif //defined(__IS_VR9__) + + MDELAY(50); + + // set power + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) + USB_CTRL_PMU_SETUP(IFX_PMU_ENABLE); + //#if defined(__IS_TWINPASS__) + // ifxusb_enable_afe_oc(); + //#endif + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) || defined(__IS_VR9__) + if(_core_if->core_no==0) + clk_enable(clk0); +// USB0_CTRL_PMU_SETUP(IFX_PMU_ENABLE); + else + clk_enable(clk1); +// USB1_CTRL_PMU_SETUP(IFX_PMU_ENABLE); + #endif //defined(__IS_AR9__) || defined(__IS_VR9__) + + if(_core_if->core_global_regs) + { + // PHY configurations. + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined(__IS_AMAZON_SE__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_AR9__) + #if defined(__IS_VR9__) + //ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_VR9__) + } + #else //defined(__UEIP__) + #if defined(__IS_TWINPASS) || defined(__IS_DANUBE__) + set_bit (4, (volatile unsigned long *)DANUBE_CGU_IFCCR); + set_bit (5, (volatile unsigned long *)DANUBE_CGU_IFCCR); + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined(__IS_AMAZON_SE__) + // clear_bit (4, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR); + clear_bit (5, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR); + #endif //defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) + set_bit (0, (volatile unsigned long *)AMAZON_S_CGU_IFCCR); + set_bit (1, (volatile unsigned long *)AMAZON_S_CGU_IFCCR); + #endif //defined(__IS_AR9__) + + MDELAY(50); + + // set power + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + clear_bit (6, (volatile unsigned long *)DANUBE_PMU_PWDCR);//USB + clear_bit (9, (volatile unsigned long *)DANUBE_PMU_PWDCR);//DSL + clear_bit (15, (volatile unsigned long *)DANUBE_PMU_PWDCR);//AHB + #if defined(__IS_TWINPASS__) + ifxusb_enable_afe_oc(); + #endif + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined(__IS_AMAZON_SE__) + clear_bit (6, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR); + clear_bit (9, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR); + clear_bit (15, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR); + #endif //defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) + if(_core_if->core_no==0) + clear_bit (6, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB + else + clear_bit (27, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB + clear_bit (9, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//DSL + clear_bit (15, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//AHB + #endif //defined(__IS_AR9__) + + if(_core_if->core_global_regs) + { + // PHY configurations. + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined(__IS_AMAZON_SE__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_AR9__) + } + + #endif //defined(__UEIP__) +} + +/*! + \brief Turn off the USB Core Power + \param _core_if Pointer of core_if structure +*/ +void ifxusb_power_off (ifxusb_core_if_t *_core_if) +{ + struct clk *clk0 = clk_get_sys("usb0", NULL); + struct clk *clk1 = clk_get_sys("usb1", NULL); + ifxusb_phy_power_off (_core_if); + + // set power + #if defined(__UEIP__) + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) + USB_CTRL_PMU_SETUP(IFX_PMU_DISABLE); + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) || defined(__IS_VR9__) + if(_core_if->core_no==0) + clk_disable(clk0); + //USB0_CTRL_PMU_SETUP(IFX_PMU_DISABLE); + else + clk_disable(clk1); + //USB1_CTRL_PMU_SETUP(IFX_PMU_DISABLE); + #endif //defined(__IS_AR9__) || defined(__IS_VR9__) + #else //defined(__UEIP__) + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + set_bit (6, (volatile unsigned long *)DANUBE_PMU_PWDCR);//USB + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined(__IS_AMAZON_SE__) + set_bit (6, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);//USB + #endif //defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) + if(_core_if->core_no==0) + set_bit (6, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB + else + set_bit (27, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB + #endif //defined(__IS_AR9__) + #endif //defined(__UEIP__) +} + +/*! + \brief Turn on the USB PHY Power + \param _core_if Pointer of core_if structure +*/ +void ifxusb_phy_power_on (ifxusb_core_if_t *_core_if) +{ + struct clk *clk0 = clk_get_sys("usb0", NULL); + struct clk *clk1 = clk_get_sys("usb1", NULL); + #if defined(__UEIP__) + if(_core_if->core_global_regs) + { + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined(__IS_AMAZON_SE__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_AR9__) + #if defined(__IS_VR9_S__) + if(_core_if->core_no==0) + set_bit (0, VR9_RCU_USB_ANA_CFG1A); + else + set_bit (0, VR9_RCU_USB_ANA_CFG1B); + #endif //defined(__IS_VR9__) + } + + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) + USB_PHY_PMU_SETUP(IFX_PMU_ENABLE); + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) || defined(__IS_VR9__) + if(_core_if->core_no==0) + clk_enable(clk0); + //USB0_PHY_PMU_SETUP(IFX_PMU_ENABLE); + else + clk_enable(clk1); + //USB1_PHY_PMU_SETUP(IFX_PMU_ENABLE); + #endif //defined(__IS_AR9__) || defined(__IS_VR9__) + + // PHY configurations. + if(_core_if->core_global_regs) + { + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined(__IS_AMAZON_SE__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_AR9__) + #if defined(__IS_VR9_S__) + if(_core_if->core_no==0) + set_bit (0, VR9_RCU_USB_ANA_CFG1A); + else + set_bit (0, VR9_RCU_USB_ANA_CFG1B); + #endif //defined(__IS_VR9__) + } + #else //defined(__UEIP__) + // PHY configurations. + if(_core_if->core_global_regs) + { + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined(__IS_AMAZON_SE__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_AR9__) + } + + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + clear_bit (0, (volatile unsigned long *)DANUBE_PMU_PWDCR);//PHY + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined(__IS_AMAZON_SE__) + clear_bit (0, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR); + #endif //defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) + if(_core_if->core_no==0) + clear_bit (0, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY + else + clear_bit (26, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY + #endif //defined(__IS_AR9__) + + // PHY configurations. + if(_core_if->core_global_regs) + { + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined(__IS_AMAZON_SE__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_AR9__) + } + #endif //defined(__UEIP__) +} + + +/*! + \brief Turn off the USB PHY Power + \param _core_if Pointer of core_if structure +*/ +void ifxusb_phy_power_off (ifxusb_core_if_t *_core_if) +{ + struct clk *clk0 = clk_get_sys("usb0", NULL); + struct clk *clk1 = clk_get_sys("usb1", NULL); + #if defined(__UEIP__) + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) + USB_PHY_PMU_SETUP(IFX_PMU_DISABLE); + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) || defined(__IS_VR9__) + if(_core_if->core_no==0) + clk_disable(clk0); + //USB0_PHY_PMU_SETUP(IFX_PMU_DISABLE); + else + clk_disable(clk1); + //USB1_PHY_PMU_SETUP(IFX_PMU_DISABLE); + #endif // defined(__IS_AR9__) || defined(__IS_VR9__) + #else //defined(__UEIP__) + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + set_bit (0, (volatile unsigned long *)DANUBE_PMU_PWDCR);//PHY + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined(__IS_AMAZON_SE__) + set_bit (0, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);//PHY + #endif //defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) + if(_core_if->core_no==0) + set_bit (0, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY + else + set_bit (26, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY + #endif //defined(__IS_AR9__) + #endif //defined(__UEIP__) +} + + +/*! + \brief Reset on the USB Core RCU + \param _core_if Pointer of core_if structure + */ +#if defined(__IS_VR9__) + int already_hard_reset=0; +#endif +void ifxusb_hard_reset(ifxusb_core_if_t *_core_if) +{ + #if defined(__UEIP__) + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined (__IS_HOST__) + clear_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); + #elif defined (__IS_DEVICE__) + set_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); + #endif + #endif //defined(__IS_AMAZON_SE__) + + #if defined(__IS_AMAZON_SE__) + #if defined (__IS_HOST__) + clear_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); + #elif defined (__IS_DEVICE__) + set_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); + #endif + #endif //defined(__IS_AMAZON_SE__) + + #if defined(__IS_AR9__) + if(_core_if->core_no==0) + { + #if defined (__IS_HOST__) + clear_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG); + #elif defined (__IS_DEVICE__) + set_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG); + #endif + } + else + { + #if defined (__IS_HOST__) + clear_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG); + #elif defined (__IS_DEVICE__) + set_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG); + #endif + } + #endif //defined(__IS_AR9__) + + #if defined(__IS_VR9__) + if(_core_if->core_no==0) + { + #if defined (__IS_HOST__) + clear_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG); + #elif defined (__IS_DEVICE__) + set_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG); + #endif + } + else + { + #if defined (__IS_HOST__) + clear_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG); + #elif defined (__IS_DEVICE__) + set_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG); + #endif + } + #endif //defined(__IS_VR9__) + + + // set the HC's byte-order to big-endian + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + set_bit (DANUBE_USBCFG_HOST_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); + clear_bit (DANUBE_USBCFG_SLV_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined(__IS_AMAZON_SE__) + set_bit (AMAZON_SE_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); + clear_bit (AMAZON_SE_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); + #endif //defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) + if(_core_if->core_no==0) + { + set_bit (AR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG); + clear_bit (AR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG); + } + else + { + set_bit (AR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG); + clear_bit (AR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG); + } + #endif //defined(__IS_AR9__) + #if defined(__IS_VR9__) + if(_core_if->core_no==0) + { + set_bit (VR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG); + clear_bit (VR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG); + } + else + { + set_bit (VR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG); + clear_bit (VR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG); + } + #endif //defined(__IS_VR9__) + + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + set_bit (4, DANUBE_RCU_RESET); + MDELAY(500); + clear_bit (4, DANUBE_RCU_RESET); + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + + #if defined(__IS_AMAZON_SE__) + set_bit (4, AMAZON_SE_RCU_RESET); + MDELAY(500); + clear_bit (4, AMAZON_SE_RCU_RESET); + MDELAY(500); + #endif //defined(__IS_AMAZON_SE__) + + #if defined(__IS_AR9__) + if(_core_if->core_no==0) + { + set_bit (4, AR9_RCU_USBRESET); + MDELAY(500); + clear_bit (4, AR9_RCU_USBRESET); + } + else + { + set_bit (28, AR9_RCU_USBRESET); + MDELAY(500); + clear_bit (28, AR9_RCU_USBRESET); + } + MDELAY(500); + #endif //defined(__IS_AR9__) + #if defined(__IS_VR9__) + if(!already_hard_reset) + { + set_bit (4, VR9_RCU_USBRESET); + MDELAY(500); + clear_bit (4, VR9_RCU_USBRESET); + MDELAY(500); + already_hard_reset=1; + } + #endif //defined(__IS_VR9__) + + #if defined(__IS_TWINPASS__) + ifxusb_enable_afe_oc(); + #endif + + if(_core_if->core_global_regs) + { + // PHY configurations. + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined(__IS_AMAZON_SE__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_AR9__) + #if defined(__IS_VR9__) + // ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_VR9__) + } + #else //defined(__UEIP__) + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined (__IS_HOST__) + clear_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); + #elif defined (__IS_DEVICE__) + set_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); + #endif + #endif //defined(__IS_AMAZON_SE__) + + #if defined(__IS_AMAZON_SE__) + #if defined (__IS_HOST__) + clear_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); + #elif defined (__IS_DEVICE__) + set_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); + #endif + #endif //defined(__IS_AMAZON_SE__) + + #if defined(__IS_AR9__) + if(_core_if->core_no==0) + { + #if defined (__IS_HOST__) + clear_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG); + #elif defined (__IS_DEVICE__) + set_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG); + #endif + } + else + { + #if defined (__IS_HOST__) + clear_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG); + #elif defined (__IS_DEVICE__) + set_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG); + #endif + } + #endif //defined(__IS_AR9__) + + // set the HC's byte-order to big-endian + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + set_bit (DANUBE_USBCFG_HOST_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); + clear_bit (DANUBE_USBCFG_SLV_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined(__IS_AMAZON_SE__) + set_bit (AMAZON_SE_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); + clear_bit (AMAZON_SE_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); + #endif //defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) + if(_core_if->core_no==0) + { + set_bit (AMAZON_S_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG); + clear_bit (AMAZON_S_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG); + } + else + { + set_bit (AMAZON_S_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG); + clear_bit (AMAZON_S_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG); + } + #endif //defined(__IS_AR9__) + + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + set_bit (4, DANUBE_RCU_RESET); + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined(__IS_AMAZON_SE__) + set_bit (4, AMAZON_SE_RCU_RESET); + #endif //defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) + if(_core_if->core_no==0) + { + set_bit (4, AMAZON_S_RCU_USBRESET); + } + else + { + set_bit (28, AMAZON_S_RCU_USBRESET); + } + #endif //defined(__IS_AR9__) + + MDELAY(500); + + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + clear_bit (4, DANUBE_RCU_RESET); + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined(__IS_AMAZON_SE__) + clear_bit (4, AMAZON_SE_RCU_RESET); + #endif //defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) + if(_core_if->core_no==0) + { + clear_bit (4, AMAZON_S_RCU_USBRESET); + } + else + { + clear_bit (28, AMAZON_S_RCU_USBRESET); + } + #endif //defined(__IS_AR9__) + + MDELAY(500); + + #if defined(__IS_TWINPASS__) + ifxusb_enable_afe_oc(); + #endif + + if(_core_if->core_global_regs) + { + // PHY configurations. + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined(__IS_AMAZON_SE__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) + ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); + #endif //defined(__IS_AR9__) + } + #endif //defined(__UEIP__) +} + +#if defined(__GADGET_LED__) || defined(__HOST_LED__) + #if defined(__UEIP__) + static void *g_usb_led_trigger = NULL; + #endif + + void ifxusb_led_init(ifxusb_core_if_t *_core_if) + { + #if defined(__UEIP__) + if ( !g_usb_led_trigger ) + { + ifx_led_trigger_register("usb_link", &g_usb_led_trigger); + if ( g_usb_led_trigger != NULL ) + { + struct ifx_led_trigger_attrib attrib = {0}; + attrib.delay_on = 250; + attrib.delay_off = 250; + attrib.timeout = 2000; + attrib.def_value = 1; + attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE; + IFX_DEBUGP("Reg USB LED!!\n"); + ifx_led_trigger_set_attrib(g_usb_led_trigger, &attrib); + } + } + #endif //defined(__UEIP__) + } + + void ifxusb_led_free(ifxusb_core_if_t *_core_if) + { + #if defined(__UEIP__) + if ( g_usb_led_trigger ) + { + ifx_led_trigger_deregister(g_usb_led_trigger); + g_usb_led_trigger = NULL; + } + #endif //defined(__UEIP__) + } + + /*! + \brief Turn off the USB 5V VBus Power + \param _core_if Pointer of core_if structure + */ + void ifxusb_led(ifxusb_core_if_t *_core_if) + { + #if defined(__UEIP__) + if(g_usb_led_trigger) + ifx_led_trigger_activate(g_usb_led_trigger); + #else + #endif //defined(__UEIP__) + } +#endif // defined(__GADGET_LED__) || defined(__HOST_LED__) + + + +#if defined(__IS_HOST__) && defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__) +/*! + \brief Turn on the OC Int + */ + void ifxusb_oc_int_on() + { + #if defined(__UEIP__) + #else + #if defined(__IS_TWINPASS__) + irq_enable(DANUBE_USB_OC_INT); + #endif + #endif //defined(__UEIP__) + } +/*! + \brief Turn off the OC Int + */ + void ifxusb_oc_int_off() + { + #if defined(__UEIP__) + #else + #if defined(__IS_TWINPASS__) + irq_disable(DANUBE_USB_OC_INT); + #endif + #endif //defined(__UEIP__) + } +#endif //defined(__IS_HOST__) && defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__) + +/* internal routines for debugging */ +void ifxusb_dump_msg(const u8 *buf, unsigned int length) +{ +#ifdef __DEBUG__ + unsigned int start, num, i; + char line[52], *p; + + if (length >= 512) + return; + start = 0; + while (length > 0) + { + num = min(length, 16u); + p = line; + for (i = 0; i < num; ++i) + { + if (i == 8) + *p++ = ' '; + sprintf(p, " %02x", buf[i]); + p += 3; + } + *p = 0; + IFX_PRINT( "%6x: %s\n", start, line); + buf += num; + start += num; + length -= num; + } +#endif +} + +/* This functions reads the SPRAM and prints its content */ +void ifxusb_dump_spram(ifxusb_core_if_t *_core_if) +{ +#ifdef __ENABLE_DUMP__ + volatile uint8_t *addr, *start_addr, *end_addr; + uint32_t size; + IFX_PRINT("SPRAM Data:\n"); + start_addr = (void*)_core_if->core_global_regs; + IFX_PRINT("Base Address: 0x%8X\n", (uint32_t)start_addr); + + start_addr = (void*)_core_if->data_fifo_dbg; + IFX_PRINT("Starting Address: 0x%8X\n", (uint32_t)start_addr); + + size=_core_if->hwcfg3.b.dfifo_depth; + size<<=2; + size+=0x200; + size&=0x0003FFFC; + + end_addr = (void*)_core_if->data_fifo_dbg; + end_addr += size; + + for(addr = start_addr; addr < end_addr; addr+=16) + { + IFX_PRINT("0x%8X:\t%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", (uint32_t)addr, + addr[ 0], addr[ 1], addr[ 2], addr[ 3], + addr[ 4], addr[ 5], addr[ 6], addr[ 7], + addr[ 8], addr[ 9], addr[10], addr[11], + addr[12], addr[13], addr[14], addr[15] + ); + } + return; +#endif //__ENABLE_DUMP__ +} + + + + +/* This function reads the core global registers and prints them */ +void ifxusb_dump_registers(ifxusb_core_if_t *_core_if) +{ +#ifdef __ENABLE_DUMP__ + int i; + volatile uint32_t *addr; + #ifdef __IS_DEVICE__ + volatile uint32_t *addri,*addro; + #endif + + IFX_PRINT("Core Global Registers\n"); + addr=&_core_if->core_global_regs->gotgctl; + IFX_PRINT("GOTGCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->core_global_regs->gotgint; + IFX_PRINT("GOTGINT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->core_global_regs->gahbcfg; + IFX_PRINT("GAHBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->core_global_regs->gusbcfg; + IFX_PRINT("GUSBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->core_global_regs->grstctl; + IFX_PRINT("GRSTCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->core_global_regs->gintsts; + IFX_PRINT("GINTSTS @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->core_global_regs->gintmsk; + IFX_PRINT("GINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->core_global_regs->gi2cctl; + IFX_PRINT("GI2CCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->core_global_regs->gpvndctl; + IFX_PRINT("GPVNDCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->core_global_regs->ggpio; + IFX_PRINT("GGPIO @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->core_global_regs->guid; + IFX_PRINT("GUID @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->core_global_regs->gsnpsid; + IFX_PRINT("GSNPSID @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->core_global_regs->ghwcfg1; + IFX_PRINT("GHWCFG1 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->core_global_regs->ghwcfg2; + IFX_PRINT("GHWCFG2 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->core_global_regs->ghwcfg3; + IFX_PRINT("GHWCFG3 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->core_global_regs->ghwcfg4; + IFX_PRINT("GHWCFG4 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + + addr=_core_if->pcgcctl; + IFX_PRINT("PCGCCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + + addr=&_core_if->core_global_regs->grxfsiz; + IFX_PRINT("GRXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + + #ifdef __IS_HOST__ + addr=&_core_if->core_global_regs->gnptxfsiz; + IFX_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->core_global_regs->hptxfsiz; + IFX_PRINT("HPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + #endif //__IS_HOST__ + + #ifdef __IS_DEVICE__ + #ifdef __DED_FIFO__ + addr=&_core_if->core_global_regs->gnptxfsiz; + IFX_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + for (i=0; i<= _core_if->hwcfg4.b.num_in_eps; i++) + { + addr=&_core_if->core_global_regs->dptxfsiz_dieptxf[i]; + IFX_PRINT("DPTXFSIZ[%d] @0x%08X : 0x%08X\n",i,(uint32_t)addr,ifxusb_rreg(addr)); + } + #else + addr=&_core_if->core_global_regs->gnptxfsiz; + IFX_PRINT("TXFSIZ[00] @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + for (i=0; i< _core_if->hwcfg4.b.num_dev_perio_in_ep; i++) + { + addr=&_core_if->core_global_regs->dptxfsiz_dieptxf[i]; + IFX_PRINT("TXFSIZ[%02d] @0x%08X : 0x%08X\n",i+1,(uint32_t)addr,ifxusb_rreg(addr)); + } + #endif + #endif //__IS_DEVICE__ + + #ifdef __IS_HOST__ + IFX_PRINT("Host Global Registers\n"); + addr=&_core_if->host_global_regs->hcfg; + IFX_PRINT("HCFG @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->host_global_regs->hfir; + IFX_PRINT("HFIR @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->host_global_regs->hfnum; + IFX_PRINT("HFNUM @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->host_global_regs->hptxsts; + IFX_PRINT("HPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->host_global_regs->haint; + IFX_PRINT("HAINT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->host_global_regs->haintmsk; + IFX_PRINT("HAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr= _core_if->hprt0; + IFX_PRINT("HPRT0 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + + for (i=0; ihc_regs[i]->hcchar; + IFX_PRINT("HCCHAR @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->hc_regs[i]->hcsplt; + IFX_PRINT("HCSPLT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->hc_regs[i]->hcint; + IFX_PRINT("HCINT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->hc_regs[i]->hcintmsk; + IFX_PRINT("HCINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->hc_regs[i]->hctsiz; + IFX_PRINT("HCTSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->hc_regs[i]->hcdma; + IFX_PRINT("HCDMA @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + } + #endif //__IS_HOST__ + + #ifdef __IS_DEVICE__ + IFX_PRINT("Device Global Registers\n"); + addr=&_core_if->dev_global_regs->dcfg; + IFX_PRINT("DCFG @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->dev_global_regs->dctl; + IFX_PRINT("DCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->dev_global_regs->dsts; + IFX_PRINT("DSTS @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->dev_global_regs->diepmsk; + IFX_PRINT("DIEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->dev_global_regs->doepmsk; + IFX_PRINT("DOEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->dev_global_regs->daintmsk; + IFX_PRINT("DAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->dev_global_regs->daint; + IFX_PRINT("DAINT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->dev_global_regs->dvbusdis; + IFX_PRINT("DVBUSID @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + addr=&_core_if->dev_global_regs->dvbuspulse; + IFX_PRINT("DVBUSPULSE @0x%08X : 0x%08X\n", (uint32_t)addr,ifxusb_rreg(addr)); + + addr=&_core_if->dev_global_regs->dtknqr1; + IFX_PRINT("DTKNQR1 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); + if (_core_if->hwcfg2.b.dev_token_q_depth > 6) { + addr=&_core_if->dev_global_regs->dtknqr2; + IFX_PRINT("DTKNQR2 @0x%08X : 0x%08X\n", (uint32_t)addr,ifxusb_rreg(addr)); + } + + if (_core_if->hwcfg2.b.dev_token_q_depth > 14) + { + addr=&_core_if->dev_global_regs->dtknqr3_dthrctl; + IFX_PRINT("DTKNQR3_DTHRCTL @0x%08X : 0x%08X\n", (uint32_t)addr, ifxusb_rreg(addr)); + } + + if (_core_if->hwcfg2.b.dev_token_q_depth > 22) + { + addr=&_core_if->dev_global_regs->dtknqr4_fifoemptymsk; + IFX_PRINT("DTKNQR4 @0x%08X : 0x%08X\n", (uint32_t)addr, ifxusb_rreg(addr)); + } + + //for (i=0; i<= MAX_EPS_CHANNELS; i++) + //for (i=0; i<= 10; i++) + for (i=0; i<= 3; i++) + { + IFX_PRINT("Device EP %d Registers\n", i); + addri=&_core_if->in_ep_regs[i]->diepctl;addro=&_core_if->out_ep_regs[i]->doepctl; + IFX_PRINT("DEPCTL I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro)); + addro=&_core_if->out_ep_regs[i]->doepfn; + IFX_PRINT("DEPFN I: O: 0x%08X\n",ifxusb_rreg(addro)); + addri=&_core_if->in_ep_regs[i]->diepint;addro=&_core_if->out_ep_regs[i]->doepint; + IFX_PRINT("DEPINT I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro)); + addri=&_core_if->in_ep_regs[i]->dieptsiz;addro=&_core_if->out_ep_regs[i]->doeptsiz; + IFX_PRINT("DETSIZ I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro)); + addri=&_core_if->in_ep_regs[i]->diepdma;addro=&_core_if->out_ep_regs[i]->doepdma; + IFX_PRINT("DEPDMA I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro)); + addri=&_core_if->in_ep_regs[i]->dtxfsts; + IFX_PRINT("DTXFSTS I: 0x%08X\n",ifxusb_rreg(addri) ); + addri=&_core_if->in_ep_regs[i]->diepdmab;addro=&_core_if->out_ep_regs[i]->doepdmab; + IFX_PRINT("DEPDMAB I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro)); + } + #endif //__IS_DEVICE__ +#endif //__ENABLE_DUMP__ +} + +void ifxusb_clean_spram(ifxusb_core_if_t *_core_if,uint32_t dwords) +{ + volatile uint32_t *addr1,*addr2, *start_addr, *end_addr; + + if(!dwords) + return; + + start_addr = (uint32_t *)_core_if->data_fifo_dbg; + + end_addr = (uint32_t *)_core_if->data_fifo_dbg; + end_addr += dwords; + + IFX_PRINT("Clearning SPRAM: 0x%8X-0x%8X\n", (uint32_t)start_addr,(uint32_t)end_addr); + for(addr1 = start_addr; addr1 < end_addr; addr1+=4) + { + for(addr2 = addr1; addr2 < addr1+4; addr2++) + *addr2=0x00000000; + } + IFX_PRINT("Clearning SPRAM: 0x%8X-0x%8X Done\n", (uint32_t)start_addr,(uint32_t)end_addr); + return; +} + diff --git a/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_cif.h b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_cif.h new file mode 100644 index 0000000000..191781f623 --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_cif.h @@ -0,0 +1,665 @@ +/***************************************************************************** + ** FILE NAME : ifxusb_cif.h + ** PROJECT : IFX USB sub-system V3 + ** MODULES : IFX USB sub-system Host and Device driver + ** SRC VERSION : 1.0 + ** DATE : 1/Jan/2009 + ** AUTHOR : Chen, Howard + ** DESCRIPTION : The Core Interface provides basic services for accessing and + ** managing the IFX USB hardware. These services are used by both the + ** Host Controller Driver and the Peripheral Controller Driver. + ** FUNCTIONS : + ** COMPILER : gcc + ** REFERENCE : IFX hardware ref handbook for each plateforms + ** COPYRIGHT : + ** Version Control Section ** + ** $Author$ + ** $Date$ + ** $Revisions$ + ** $Log$ Revision history +*****************************************************************************/ + +/*! + \defgroup IFXUSB_DRIVER_V3 IFX USB SS Project + \brief IFX USB subsystem V3.x + */ + +/*! + \defgroup IFXUSB_CIF Core Interface APIs + \ingroup IFXUSB_DRIVER_V3 + \brief The Core Interface provides basic services for accessing and + managing the IFXUSB hardware. These services are used by both the + Host Controller Driver and the Peripheral Controller Driver. + */ + + +/*! + \file ifxusb_cif.h + \ingroup IFXUSB_DRIVER_V3 + \brief This file contains the interface to the IFX USB Core. + */ + +#if !defined(__IFXUSB_CIF_H__) +#define __IFXUSB_CIF_H__ + +#include + +#include +#include + +#include "ifxusb_plat.h" +#include "ifxusb_regs.h" + +#ifdef __DEBUG__ + #include "linux/timer.h" +#endif + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#define IFXUSB_PARAM_SPEED_HIGH 0 +#define IFXUSB_PARAM_SPEED_FULL 1 + +#define IFXUSB_EP_SPEED_LOW 0 +#define IFXUSB_EP_SPEED_FULL 1 +#define IFXUSB_EP_SPEED_HIGH 2 + +#define IFXUSB_EP_TYPE_CTRL 0 +#define IFXUSB_EP_TYPE_ISOC 1 +#define IFXUSB_EP_TYPE_BULK 2 +#define IFXUSB_EP_TYPE_INTR 3 + +#define IFXUSB_HC_PID_DATA0 0 +#define IFXUSB_HC_PID_DATA2 1 +#define IFXUSB_HC_PID_DATA1 2 +#define IFXUSB_HC_PID_MDATA 3 +#define IFXUSB_HC_PID_SETUP 3 + + +/*! + \addtogroup IFXUSB_CIF + */ +/*@{*/ + +/*! + \struct ifxusb_params + \brief IFXUSB Parameters structure. + This structure is used for both importing from insmod stage and run-time storage. + These parameters define how the IFXUSB controller should be configured. + */ +typedef struct ifxusb_params +{ + int32_t dma_burst_size; /*!< The DMA Burst size (applicable only for Internal DMA + Mode). 0(for single), 1(incr), 4(incr4), 8(incr8) 16(incr16) + */ + /* Translate this to GAHBCFG values */ + int32_t speed; /*!< Specifies the maximum speed of operation in host and device mode. + The actual speed depends on the speed of the attached device and + the value of phy_type. The actual speed depends on the speed of the + attached device. + 0 - High Speed (default) + 1 - Full Speed + */ + + int32_t data_fifo_size; /*!< Total number of dwords in the data FIFO memory. This + memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic + Tx FIFOs. + 32 to 32768 + */ + #ifdef __IS_DEVICE__ + int32_t rx_fifo_size; /*!< Number of dwords in the Rx FIFO in device mode. + 16 to 32768 + */ + + + int32_t tx_fifo_size[MAX_EPS_CHANNELS]; /*!< Number of dwords in each of the Tx FIFOs in device mode. + 4 to 768 + */ + #ifdef __DED_FIFO__ + int32_t thr_ctl; /*!< Threshold control on/off */ + int32_t tx_thr_length; /*!< Threshold length for Tx */ + int32_t rx_thr_length; /*!< Threshold length for Rx*/ + #endif + #else //__IS_HOST__ + int32_t host_channels; /*!< The number of host channel registers to use. + 1 to 16 + */ + + int32_t rx_fifo_size; /*!< Number of dwords in the Rx FIFO in host mode. + 16 to 32768 + */ + + int32_t nperio_tx_fifo_size;/*!< Number of dwords in the non-periodic Tx FIFO in host mode. + 16 to 32768 + */ + + int32_t perio_tx_fifo_size; /*!< Number of dwords in the host periodic Tx FIFO. + 16 to 32768 + */ + #endif //__IS_HOST__ + + int32_t max_transfer_size; /*!< The maximum transfer size supported in bytes. + 2047 to 65,535 + */ + + int32_t max_packet_count; /*!< The maximum number of packets in a transfer. + 15 to 511 (default 511) + */ + int32_t phy_utmi_width; /*!< Specifies the UTMI+ Data Width. + 8 or 16 bits (default 16) + */ + + int32_t turn_around_time_hs; /*!< Specifies the Turn-Around time at HS*/ + int32_t turn_around_time_fs; /*!< Specifies the Turn-Around time at FS*/ + + int32_t timeout_cal_hs; /*!< Specifies the Timeout_Calibration at HS*/ + int32_t timeout_cal_fs; /*!< Specifies the Timeout_Calibration at FS*/ +} ifxusb_params_t; + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +/*! + \struct ifxusb_core_if + \brief The ifx_core_if structure contains information needed to manage + the IFX USB controller acting in either host or device mode. It + represents the programming view of the controller as a whole. + */ +typedef struct ifxusb_core_if +{ + ifxusb_params_t params; /*!< Run-time Parameters */ + + uint8_t core_no; /*!< core number (used as id when multi-core case */ + char *core_name; /*!< core name used for registration and informative purpose*/ + int irq; /*!< irq number this core is hooked */ + + /***************************************************************** + * Structures and pointers to physical register interface. + *****************************************************************/ + /** Core Global registers starting at offset 000h. */ + ifxusb_core_global_regs_t *core_global_regs; /*!< pointer to Core Global Registers, offset at 000h */ + + /** Host-specific registers */ + #ifdef __IS_HOST__ + /** Host Global Registers starting at offset 400h.*/ + ifxusb_host_global_regs_t *host_global_regs; /*!< pointer to Host Global Registers, offset at 400h */ + #define IFXUSB_HOST_GLOBAL_REG_OFFSET 0x400 + /** Host Port 0 Control and Status Register */ + volatile uint32_t *hprt0; /*!< pointer to HPRT0 Registers, offset at 440h */ + #define IFXUSB_HOST_PORT_REGS_OFFSET 0x440 + /** Host Channel Specific Registers at offsets 500h-5FCh. */ + ifxusb_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; /*!< pointer to Host-Channel n Registers, offset at 500h */ + #define IFXUSB_HOST_CHAN_REGS_OFFSET 0x500 + #define IFXUSB_CHAN_REGS_OFFSET 0x20 + #endif + + /** Device-specific registers */ + #ifdef __IS_DEVICE__ + /** Device Global Registers starting at offset 800h */ + ifxusb_device_global_regs_t *dev_global_regs; /*!< pointer to Device Global Registers, offset at 800h */ + #define IFXUSB_DEV_GLOBAL_REG_OFFSET 0x800 + + /** Device Logical IN Endpoint-Specific Registers 900h-AFCh */ + ifxusb_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; /*!< pointer to Device IN-EP Registers, offset at 900h */ + #define IFXUSB_DEV_IN_EP_REG_OFFSET 0x900 + #define IFXUSB_EP_REG_OFFSET 0x20 + /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */ + ifxusb_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];/*!< pointer to Device OUT-EP Registers, offset at 900h */ + #define IFXUSB_DEV_OUT_EP_REG_OFFSET 0xB00 + #endif + + /** Power and Clock Gating Control Register */ + volatile uint32_t *pcgcctl; /*!< pointer to Power and Clock Gating Control Registers, offset at E00h */ + #define IFXUSB_PCGCCTL_OFFSET 0xE00 + + /** Push/pop addresses for endpoints or host channels.*/ + uint32_t *data_fifo[MAX_EPS_CHANNELS]; /*!< pointer to FIFO access windows, offset at 1000h */ + #define IFXUSB_DATA_FIFO_OFFSET 0x1000 + #define IFXUSB_DATA_FIFO_SIZE 0x1000 + + uint32_t *data_fifo_dbg; /*!< pointer to FIFO debug windows, offset at 1000h */ + + /** Hardware Configuration -- stored here for convenience.*/ + hwcfg1_data_t hwcfg1; /*!< preserved Hardware Configuration 1 */ + hwcfg2_data_t hwcfg2; /*!< preserved Hardware Configuration 2 */ + hwcfg3_data_t hwcfg3; /*!< preserved Hardware Configuration 3 */ + hwcfg4_data_t hwcfg4; /*!< preserved Hardware Configuration 3 */ + uint32_t snpsid; /*!< preserved SNPSID */ + + /***************************************************************** + * Run-time informations. + *****************************************************************/ + /* Set to 1 if the core PHY interface bits in USBCFG have been initialized. */ + uint8_t phy_init_done; /*!< indicated PHY is initialized. */ + + #ifdef __IS_HOST__ + uint8_t queuing_high_bandwidth; /*!< Host mode, Queueing High Bandwidth. */ + #endif +} ifxusb_core_if_t; + +/*@}*//*IFXUSB_CIF*/ + + +/*! + \fn void *ifxusb_alloc_buf(size_t size, int clear) + \brief This function is called to allocate buffer of specified size. + The allocated buffer is mapped into DMA accessable address. + \param size Size in BYTE to be allocated + \param clear 0: don't do clear after buffer allocated, other: do clear to zero + \return 0/NULL: Fail; uncached pointer of allocated buffer + \ingroup IFXUSB_CIF + */ +extern void *ifxusb_alloc_buf(size_t size, int clear); + +/*! + \fn void ifxusb_free_buf(void *vaddr) + \brief This function is called to free allocated buffer. + \param vaddr the uncached pointer of the buffer + \ingroup IFXUSB_CIF + */ +extern void ifxusb_free_buf(void *vaddr); + +/*! + \fn int ifxusb_core_if_init(ifxusb_core_if_t *_core_if, + int _irq, + uint32_t _reg_base_addr, + uint32_t _fifo_base_addr, + uint32_t _fifo_dbg_addr) + \brief This function is called to initialize the IFXUSB CSR data + structures. The register addresses in the device and host + structures are initialized from the base address supplied by the + caller. The calling function must make the OS calls to get the + base address of the IFXUSB controller registers. + \param _core_if Pointer of core_if structure + \param _irq irq number + \param _reg_base_addr Base address of IFXUSB core registers + \param _fifo_base_addr Fifo base address + \param _fifo_dbg_addr Fifo debug address + \return 0: success; + \ingroup IFXUSB_CIF + */ +extern int ifxusb_core_if_init(ifxusb_core_if_t *_core_if, + int _irq, + uint32_t _reg_base_addr, + uint32_t _fifo_base_addr, + uint32_t _fifo_dbg_addr); + + +/*! + \fn void ifxusb_core_if_remove(ifxusb_core_if_t *_core_if) + \brief This function free the mapped address in the IFXUSB CSR data structures. + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF + */ +extern void ifxusb_core_if_remove(ifxusb_core_if_t *_core_if); + +/*! + \fn void ifxusb_enable_global_interrupts( ifxusb_core_if_t *_core_if ) + \brief This function enbles the controller's Global Interrupt in the AHB Config register. + \param _core_if Pointer of core_if structure + */ +extern void ifxusb_enable_global_interrupts( ifxusb_core_if_t *_core_if ); + +/*! + \fn void ifxusb_disable_global_interrupts( ifxusb_core_if_t *_core_if ) + \brief This function disables the controller's Global Interrupt in the AHB Config register. + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF + */ +extern void ifxusb_disable_global_interrupts( ifxusb_core_if_t *_core_if ); + +/*! + \fn void ifxusb_flush_tx_fifo( ifxusb_core_if_t *_core_if, const int _num ) + \brief Flush a Tx FIFO. + \param _core_if Pointer of core_if structure + \param _num Tx FIFO to flush. ( 0x10 for ALL TX FIFO ) + \ingroup IFXUSB_CIF + */ +extern void ifxusb_flush_tx_fifo( ifxusb_core_if_t *_core_if, const int _num ); + +/*! + \fn void ifxusb_flush_rx_fifo( ifxusb_core_if_t *_core_if ) + \brief Flush Rx FIFO. + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF + */ +extern void ifxusb_flush_rx_fifo( ifxusb_core_if_t *_core_if ); + +/*! + \fn void ifxusb_flush_both_fifo( ifxusb_core_if_t *_core_if ) + \brief Flush ALL Rx and Tx FIFO. + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF + */ +extern void ifxusb_flush_both_fifo( ifxusb_core_if_t *_core_if ); + + +/*! + \fn int ifxusb_core_soft_reset(ifxusb_core_if_t *_core_if) + \brief Do core a soft reset of the core. Be careful with this because it + resets all the internal state machines of the core. + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF + */ +extern int ifxusb_core_soft_reset(ifxusb_core_if_t *_core_if); + + +/*! + \brief Turn on the USB Core Power + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF +*/ +extern void ifxusb_power_on (ifxusb_core_if_t *_core_if); + +/*! + \fn void ifxusb_power_off (ifxusb_core_if_t *_core_if) + \brief Turn off the USB Core Power + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF +*/ +extern void ifxusb_power_off (ifxusb_core_if_t *_core_if); + +/*! + \fn void ifxusb_phy_power_on (ifxusb_core_if_t *_core_if) + \brief Turn on the USB PHY Power + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF +*/ +extern void ifxusb_phy_power_on (ifxusb_core_if_t *_core_if); + +/*! + \fn void ifxusb_phy_power_off (ifxusb_core_if_t *_core_if) + \brief Turn off the USB PHY Power + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF +*/ +extern void ifxusb_phy_power_off (ifxusb_core_if_t *_core_if); + +/*! + \fn void ifxusb_hard_reset(ifxusb_core_if_t *_core_if) + \brief Reset on the USB Core RCU + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF + */ +extern void ifxusb_hard_reset(ifxusb_core_if_t *_core_if); + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + + +#ifdef __IS_HOST__ + /*! + \fn void ifxusb_host_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params) + \brief This function initializes the IFXUSB controller registers for Host mode. + This function flushes the Tx and Rx FIFOs and it flushes any entries in the + request queues. + \param _core_if Pointer of core_if structure + \param _params parameters to be set + \ingroup IFXUSB_CIF + */ + extern void ifxusb_host_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params); + + /*! + \fn void ifxusb_host_enable_interrupts(ifxusb_core_if_t *_core_if) + \brief This function enables the Host mode interrupts. + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF + */ + extern void ifxusb_host_enable_interrupts(ifxusb_core_if_t *_core_if); + + /*! + \fn void ifxusb_host_disable_interrupts(ifxusb_core_if_t *_core_if) + \brief This function disables the Host mode interrupts. + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF + */ + extern void ifxusb_host_disable_interrupts(ifxusb_core_if_t *_core_if); + + #if defined(__IS_TWINPASS__) + extern void ifxusb_enable_afe_oc(void); + #endif + + /*! + \fn void ifxusb_vbus_init(ifxusb_core_if_t *_core_if) + \brief This function init the VBUS control. + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF + */ + extern void ifxusb_vbus_init(ifxusb_core_if_t *_core_if); + + /*! + \fn void ifxusb_vbus_free(ifxusb_core_if_t *_core_if) + \brief This function free the VBUS control. + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF + */ + extern void ifxusb_vbus_free(ifxusb_core_if_t *_core_if); + + /*! + \fn void ifxusb_vbus_on(ifxusb_core_if_t *_core_if) + \brief Turn on the USB 5V VBus Power + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF + */ + extern void ifxusb_vbus_on(ifxusb_core_if_t *_core_if); + + /*! + \fn void ifxusb_vbus_off(ifxusb_core_if_t *_core_if) + \brief Turn off the USB 5V VBus Power + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF + */ + extern void ifxusb_vbus_off(ifxusb_core_if_t *_core_if); + + /*! + \fn int ifxusb_vbus(ifxusb_core_if_t *_core_if) + \brief Read Current VBus status + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF + */ + extern int ifxusb_vbus(ifxusb_core_if_t *_core_if); + + #if defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__) + /*! + \fn void ifxusb_oc_int_on(void) + \brief Turn on the OC interrupt + \ingroup IFXUSB_CIF + */ + extern void ifxusb_oc_int_on(void); + + /*! + \fn void ifxusb_oc_int_off(void) + \brief Turn off the OC interrupt + \ingroup IFXUSB_CIF + */ + extern void ifxusb_oc_int_off(void); + #endif //defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__) +#endif + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + + +#ifdef __IS_DEVICE__ + /*! + \fn void ifxusb_dev_enable_interrupts(ifxusb_core_if_t *_core_if) + \brief This function enables the Device mode interrupts. + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF + */ + extern void ifxusb_dev_enable_interrupts(ifxusb_core_if_t *_core_if); + + /*! + \fn uint32_t ifxusb_dev_get_frame_number(ifxusb_core_if_t *_core_if) + \brief Gets the current USB frame number. This is the frame number from the last SOF packet. + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF + */ + extern uint32_t ifxusb_dev_get_frame_number(ifxusb_core_if_t *_core_if); + + /*! + \fn void ifxusb_dev_ep_set_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _is_in) + \brief Set the EP STALL. + \param _core_if Pointer of core_if structure + \param _epno EP number + \param _is_in 1: is IN transfer + \ingroup IFXUSB_CIF + */ + extern void ifxusb_dev_ep_set_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _is_in); + + /*! + \fn void ifxusb_dev_ep_clear_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _ep_type, uint8_t _is_in) + \brief Set the EP STALL. + \param _core_if Pointer of core_if structure + \param _epno EP number + \param _ep_type EP Type + \ingroup IFXUSB_CIF + */ + extern void ifxusb_dev_ep_clear_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _ep_type, uint8_t _is_in); + + /*! + \fn void ifxusb_dev_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params) + \brief This function initializes the IFXUSB controller registers for Device mode. + This function flushes the Tx and Rx FIFOs and it flushes any entries in the + request queues. + This function validate the imported parameters and store the result in the CIF structure. + After + \param _core_if Pointer of core_if structure + \param _params structure of inported parameters + \ingroup IFXUSB_CIF + */ + extern void ifxusb_dev_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params); +#endif + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(__GADGET_LED__) || defined(__HOST_LED__) + /*! + \fn void ifxusb_led_init(ifxusb_core_if_t *_core_if) + \brief This function init the LED control. + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF + */ + extern void ifxusb_led_init(ifxusb_core_if_t *_core_if); + + /*! + \fn void ifxusb_led_free(ifxusb_core_if_t *_core_if) + \brief This function free the LED control. + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF + */ + extern void ifxusb_led_free(ifxusb_core_if_t *_core_if); + + /*! + \fn void ifxusb_led(ifxusb_core_if_t *_core_if) + \brief This function trigger the LED access. + \param _core_if Pointer of core_if structure + \ingroup IFXUSB_CIF + */ + extern void ifxusb_led(ifxusb_core_if_t *_core_if); +#endif + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +/* internal routines for debugging */ +extern void ifxusb_dump_msg(const u8 *buf, unsigned int length); +extern void ifxusb_dump_spram(ifxusb_core_if_t *_core_if); +extern void ifxusb_dump_registers(ifxusb_core_if_t *_core_if); +extern void ifxusb_clean_spram(ifxusb_core_if_t *_core_if,uint32_t dwords); + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +static inline uint32_t ifxusb_read_core_intr(ifxusb_core_if_t *_core_if) +{ + return (ifxusb_rreg(&_core_if->core_global_regs->gintsts) & + (ifxusb_rreg(&_core_if->core_global_regs->gintmsk) +#ifdef __USE_TIMER_4_SOF__ + | IFXUSB_SOF_INTR_MASK +#endif + )); +} + +static inline uint32_t ifxusb_read_otg_intr (ifxusb_core_if_t *_core_if) +{ + return (ifxusb_rreg (&_core_if->core_global_regs->gotgint)); +} + +static inline uint32_t ifxusb_mode(ifxusb_core_if_t *_core_if) +{ + return (ifxusb_rreg( &_core_if->core_global_regs->gintsts ) & 0x1); +} +static inline uint8_t ifxusb_is_device_mode(ifxusb_core_if_t *_core_if) +{ + return (ifxusb_mode(_core_if) != 1); +} +static inline uint8_t ifxusb_is_host_mode(ifxusb_core_if_t *_core_if) +{ + return (ifxusb_mode(_core_if) == 1); +} + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#ifdef __IS_HOST__ + static inline uint32_t ifxusb_read_hprt0(ifxusb_core_if_t *_core_if) + { + hprt0_data_t hprt0; + hprt0.d32 = ifxusb_rreg(_core_if->hprt0); + hprt0.b.prtena = 0; + hprt0.b.prtconndet = 0; + hprt0.b.prtenchng = 0; + hprt0.b.prtovrcurrchng = 0; + return hprt0.d32; + } + + static inline uint32_t ifxusb_read_host_all_channels_intr (ifxusb_core_if_t *_core_if) + { + return (ifxusb_rreg (&_core_if->host_global_regs->haint)); + } + + static inline uint32_t ifxusb_read_host_channel_intr (ifxusb_core_if_t *_core_if, int hc_num) + { + return (ifxusb_rreg (&_core_if->hc_regs[hc_num]->hcint)); + } +#endif + +#ifdef __IS_DEVICE__ + static inline uint32_t ifxusb_read_dev_all_in_ep_intr(ifxusb_core_if_t *_core_if) + { + uint32_t v; + v = ifxusb_rreg(&_core_if->dev_global_regs->daint) & + ifxusb_rreg(&_core_if->dev_global_regs->daintmsk); + return (v & 0xffff); + } + + static inline uint32_t ifxusb_read_dev_all_out_ep_intr(ifxusb_core_if_t *_core_if) + { + uint32_t v; + v = ifxusb_rreg(&_core_if->dev_global_regs->daint) & + ifxusb_rreg(&_core_if->dev_global_regs->daintmsk); + return ((v & 0xffff0000) >> 16); + } + + static inline uint32_t ifxusb_read_dev_in_ep_intr(ifxusb_core_if_t *_core_if, int _ep_num) + { + uint32_t v; + v = ifxusb_rreg(&_core_if->in_ep_regs[_ep_num]->diepint) & + ifxusb_rreg(&_core_if->dev_global_regs->diepmsk); + return v; + } + + static inline uint32_t ifxusb_read_dev_out_ep_intr(ifxusb_core_if_t *_core_if, int _ep_num) + { + uint32_t v; + v = ifxusb_rreg(&_core_if->out_ep_regs[_ep_num]->doepint) & + ifxusb_rreg(&_core_if->dev_global_regs->doepmsk); + return v; + } + +#endif + +extern void ifxusb_attr_create (void *_dev); + +extern void ifxusb_attr_remove (void *_dev); + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#endif // !defined(__IFXUSB_CIF_H__) + + diff --git a/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_cif_d.c b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_cif_d.c new file mode 100644 index 0000000000..36ab0e75bf --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_cif_d.c @@ -0,0 +1,458 @@ +/***************************************************************************** + ** FILE NAME : ifxusb_cif_d.c + ** PROJECT : IFX USB sub-system V3 + ** MODULES : IFX USB sub-system Host and Device driver + ** SRC VERSION : 1.0 + ** DATE : 1/Jan/2009 + ** AUTHOR : Chen, Howard + ** DESCRIPTION : The Core Interface provides basic services for accessing and + ** managing the IFX USB hardware. These services are used by the + ** Peripheral Controller Driver only. + *****************************************************************************/ + +/*! + \file ifxusb_cif_d.c + \ingroup IFXUSB_DRIVER_V3 + \brief This file contains the interface to the IFX USB Core. +*/ + +#include +#include "ifxusb_version.h" + + +#include +#include + +#ifdef __DEBUG__ + #include +#endif + +#include "ifxusb_plat.h" +#include "ifxusb_regs.h" +#include "ifxusb_cif.h" + +#include "ifxpcd.h" + + + +/*! + \brief Initializes the DevSpd field of the DCFG register depending on the PHY type + and the enumeration speed of the device. + \param _core_if Pointer of core_if structure + */ +void ifxusb_dev_init_spd(ifxusb_core_if_t *_core_if) +{ + uint32_t val; + dcfg_data_t dcfg; + + IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); + if (_core_if->params.speed == IFXUSB_PARAM_SPEED_FULL) + /* High speed PHY running at full speed */ + val = 0x1; + else + /* High speed PHY running at high speed and full speed*/ + val = 0x0; + + IFX_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val); + dcfg.d32 = ifxusb_rreg(&_core_if->dev_global_regs->dcfg); + dcfg.b.devspd = val; + ifxusb_wreg(&_core_if->dev_global_regs->dcfg, dcfg.d32); +} + + +/*! + \brief This function enables the Device mode interrupts. + \param _core_if Pointer of core_if structure + */ +void ifxusb_dev_enable_interrupts(ifxusb_core_if_t *_core_if) +{ + gint_data_t intr_mask ={ .d32 = 0}; + ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; + + IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); + IFX_DEBUGPL(DBG_CIL, "%s()\n", __func__); + + /* Clear any pending OTG Interrupts */ + ifxusb_wreg( &global_regs->gotgint, 0xFFFFFFFF); + + /* Clear any pending interrupts */ + ifxusb_wreg( &global_regs->gintsts, 0xFFFFFFFF); + + /* Enable the interrupts in the GINTMSK.*/ + intr_mask.b.modemismatch = 1; + intr_mask.b.conidstschng = 1; + intr_mask.b.wkupintr = 1; + intr_mask.b.disconnect = 1; + intr_mask.b.usbsuspend = 1; + + intr_mask.b.usbreset = 1; + intr_mask.b.enumdone = 1; + intr_mask.b.inepintr = 1; + intr_mask.b.outepintr = 1; + intr_mask.b.erlysuspend = 1; + #ifndef __DED_FIFO__ +// intr_mask.b.epmismatch = 1; + #endif + + ifxusb_mreg( &global_regs->gintmsk, intr_mask.d32, intr_mask.d32); + IFX_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, ifxusb_rreg( &global_regs->gintmsk)); +} + +/*! + \brief Gets the current USB frame number. This is the frame number from the last SOF packet. + \param _core_if Pointer of core_if structure + */ +uint32_t ifxusb_dev_get_frame_number(ifxusb_core_if_t *_core_if) +{ + dsts_data_t dsts; + IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); + dsts.d32 = ifxusb_rreg(&_core_if->dev_global_regs->dsts); + /* read current frame/microfreme number from DSTS register */ + return dsts.b.soffn; +} + + +/*! + \brief Set the EP STALL. + */ +void ifxusb_dev_ep_set_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _is_in) +{ + depctl_data_t depctl; + volatile uint32_t *depctl_addr; + + IFX_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _epno, (_is_in?"IN":"OUT")); + + depctl_addr = (_is_in)? (&(_core_if->in_ep_regs [_epno]->diepctl)): + (&(_core_if->out_ep_regs[_epno]->doepctl)); + depctl.d32 = ifxusb_rreg(depctl_addr); + depctl.b.stall = 1; + + if (_is_in && depctl.b.epena) + depctl.b.epdis = 1; + + ifxusb_wreg(depctl_addr, depctl.d32); + IFX_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",ifxusb_rreg(depctl_addr)); + return; +} + +/*! +\brief Clear the EP STALL. + */ +void ifxusb_dev_ep_clear_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _ep_type, uint8_t _is_in) +{ + depctl_data_t depctl; + volatile uint32_t *depctl_addr; + + IFX_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _epno, (_is_in?"IN":"OUT")); + + depctl_addr = (_is_in)? (&(_core_if->in_ep_regs [_epno]->diepctl)): + (&(_core_if->out_ep_regs[_epno]->doepctl)); + + depctl.d32 = ifxusb_rreg(depctl_addr); + /* clear the stall bits */ + depctl.b.stall = 0; + + /* + * USB Spec 9.4.5: For endpoints using data toggle, regardless + * of whether an endpoint has the Halt feature set, a + * ClearFeature(ENDPOINT_HALT) request always results in the + * data toggle being reinitialized to DATA0. + */ + if (_ep_type == IFXUSB_EP_TYPE_INTR || _ep_type == IFXUSB_EP_TYPE_BULK) + depctl.b.setd0pid = 1; /* DATA0 */ + + ifxusb_wreg(depctl_addr, depctl.d32); + IFX_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",ifxusb_rreg(depctl_addr)); + return; +} + +/*! + \brief This function initializes the IFXUSB controller registers for Device mode. + This function flushes the Tx and Rx FIFOs and it flushes any entries in the + request queues. + \param _core_if Pointer of core_if structure + \param _params parameters to be set + */ +void ifxusb_dev_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params) +{ + ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; + + gusbcfg_data_t usbcfg ={.d32 = 0}; + gahbcfg_data_t ahbcfg ={.d32 = 0}; + dcfg_data_t dcfg ={.d32 = 0}; + grstctl_t resetctl ={.d32 = 0}; + gotgctl_data_t gotgctl ={.d32 = 0}; + + uint32_t dir; + int i; + + IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); + IFX_DEBUGPL(DBG_CILV, "%s(%p)\n",__func__,_core_if); + + /* Copy Params */ + _core_if->params.dma_burst_size = _params->dma_burst_size; + _core_if->params.speed = _params->speed; + if(_params->max_transfer_size < 2048 || _params->max_transfer_size > ((1 << (_core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1) ) + _core_if->params.max_transfer_size = ((1 << (_core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1); + else + _core_if->params.max_transfer_size = _params->max_transfer_size; + + if(_params->max_packet_count < 16 || _params->max_packet_count > ((1 << (_core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1) ) + _core_if->params.max_packet_count= ((1 << (_core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1); + else + _core_if->params.max_packet_count= _params->max_packet_count; + _core_if->params.phy_utmi_width = _params->phy_utmi_width; + _core_if->params.turn_around_time_hs = _params->turn_around_time_hs; + _core_if->params.turn_around_time_fs = _params->turn_around_time_fs; + _core_if->params.timeout_cal_hs = _params->timeout_cal_hs; + _core_if->params.timeout_cal_fs = _params->timeout_cal_fs; + + #ifdef __DED_FIFO__ + _core_if->params.thr_ctl = _params->thr_ctl; + _core_if->params.tx_thr_length = _params->tx_thr_length; + _core_if->params.rx_thr_length = _params->rx_thr_length; + #endif + + /* Reset the Controller */ + do + { + while(ifxusb_core_soft_reset( _core_if )) + ifxusb_hard_reset(_core_if); + } while (ifxusb_is_host_mode(_core_if)); + + usbcfg.d32 = ifxusb_rreg(&global_regs->gusbcfg); + #if 0 + #if defined(__DED_FIFO__) + usbcfg.b.ForceDevMode = 1; + usbcfg.b.ForceHstMode = 0; + #endif + #endif + usbcfg.b.term_sel_dl_pulse = 0; + ifxusb_wreg (&global_regs->gusbcfg, usbcfg.d32); + + /* This programming sequence needs to happen in FS mode before any other + * programming occurs */ + /* High speed PHY. */ + if (!_core_if->phy_init_done) + { + _core_if->phy_init_done = 1; + /* HS PHY parameters. These parameters are preserved + * during soft reset so only program the first time. Do + * a soft reset immediately after setting phyif. */ + usbcfg.b.ulpi_utmi_sel = 0; //UTMI+ + usbcfg.b.phyif = ( _core_if->params.phy_utmi_width == 16)?1:0; + ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32); + /* Reset after setting the PHY parameters */ + ifxusb_core_soft_reset( _core_if ); + } + + /* Program the GAHBCFG Register.*/ + switch (_core_if->params.dma_burst_size) + { + case 0 : + ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_SINGLE; + break; + case 1 : + ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR; + break; + case 4 : + ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR4; + break; + case 8 : + ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR8; + break; + case 16: + ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR16; + break; + } + ahbcfg.b.dmaenable = 1; + ifxusb_wreg(&global_regs->gahbcfg, ahbcfg.d32); + + /* Program the GUSBCFG register. */ + usbcfg.d32 = ifxusb_rreg( &global_regs->gusbcfg ); + usbcfg.b.hnpcap = 0; + usbcfg.b.srpcap = 0; + ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32); + + /* Restart the Phy Clock */ + ifxusb_wreg(_core_if->pcgcctl, 0); + + /* Device configuration register */ + ifxusb_dev_init_spd(_core_if); + dcfg.d32 = ifxusb_rreg( &_core_if->dev_global_regs->dcfg); + dcfg.b.perfrint = IFXUSB_DCFG_FRAME_INTERVAL_80; + #if defined(__DED_FIFO__) + #if defined(__DESC_DMA__) + dcfg.b.descdma = 1; + #else + dcfg.b.descdma = 0; + #endif + #endif + + ifxusb_wreg( &_core_if->dev_global_regs->dcfg, dcfg.d32 ); + + /* Configure data FIFO sizes */ + _core_if->params.data_fifo_size = _core_if->hwcfg3.b.dfifo_depth; + _core_if->params.rx_fifo_size = ifxusb_rreg(&global_regs->grxfsiz); + IFX_DEBUGPL(DBG_CIL, "Initial: FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size); + IFX_DEBUGPL(DBG_CIL, " Rx FIFO Size=0x%06X\n", _core_if->params.rx_fifo_size); + + _core_if->params.tx_fifo_size[0]= ifxusb_rreg(&global_regs->gnptxfsiz) >> 16; + + #ifdef __DED_FIFO__ + for (i=1; i <= _core_if->hwcfg4.b.num_in_eps; i++) + _core_if->params.tx_fifo_size[i] = + ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i-1]) >> 16; + #else + for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++) + _core_if->params.tx_fifo_size[i+1] = + ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i]) >> 16; + #endif + + #ifdef __DEBUG__ + #ifdef __DED_FIFO__ + for (i=0; i <= _core_if->hwcfg4.b.num_in_eps; i++) + IFX_DEBUGPL(DBG_CIL, " Tx[%02d] FIFO Size=0x%06X\n",i, _core_if->params.tx_fifo_size[i]); + #else + IFX_DEBUGPL(DBG_CIL, " NPTx FIFO Size=0x%06X\n", _core_if->params.tx_fifo_size[0]); + for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++) + IFX_DEBUGPL(DBG_CIL, " PTx[%02d] FIFO Size=0x%06X\n",i, _core_if->params.tx_fifo_size[i+1]); + #endif + #endif + + { + fifosize_data_t txfifosize; + if(_params->data_fifo_size >=0 && _params->data_fifo_size < _core_if->params.data_fifo_size) + _core_if->params.data_fifo_size = _params->data_fifo_size; + + + if(_params->rx_fifo_size >=0 && _params->rx_fifo_size < _core_if->params.rx_fifo_size) + _core_if->params.rx_fifo_size = _params->rx_fifo_size; + if(_core_if->params.data_fifo_size < _core_if->params.rx_fifo_size) + _core_if->params.rx_fifo_size = _core_if->params.data_fifo_size; + ifxusb_wreg( &global_regs->grxfsiz, _core_if->params.rx_fifo_size); + + for (i=0; i < MAX_EPS_CHANNELS; i++) + if(_params->tx_fifo_size[i] >=0 && _params->tx_fifo_size[i] < _core_if->params.tx_fifo_size[i]) + _core_if->params.tx_fifo_size[i] = _params->tx_fifo_size[i]; + + txfifosize.b.startaddr = _core_if->params.rx_fifo_size; + #ifdef __DED_FIFO__ + if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[0] > _core_if->params.data_fifo_size) + _core_if->params.tx_fifo_size[0]= _core_if->params.data_fifo_size - txfifosize.b.startaddr; + txfifosize.b.depth=_core_if->params.tx_fifo_size[0]; + ifxusb_wreg( &global_regs->gnptxfsiz, txfifosize.d32); + txfifosize.b.startaddr += _core_if->params.tx_fifo_size[0]; + for (i=1; i <= _core_if->hwcfg4.b.num_in_eps; i++) + { + if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[i] > _core_if->params.data_fifo_size) + _core_if->params.tx_fifo_size[i]= _core_if->params.data_fifo_size - txfifosize.b.startaddr; + txfifosize.b.depth=_core_if->params.tx_fifo_size[i]; + ifxusb_wreg( &global_regs->dptxfsiz_dieptxf[i-1], txfifosize.d32); + txfifosize.b.startaddr += _core_if->params.tx_fifo_size[i]; + } + #else + if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[0] > _core_if->params.data_fifo_size) + _core_if->params.tx_fifo_size[0]= _core_if->params.data_fifo_size - txfifosize.b.startaddr; + txfifosize.b.depth=_core_if->params.tx_fifo_size[0]; + ifxusb_wreg( &global_regs->gnptxfsiz, txfifosize.d32); + txfifosize.b.startaddr += _core_if->params.tx_fifo_size[0]; + for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++) + { + if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[i+1] > _core_if->params.data_fifo_size) + _core_if->params.tx_fifo_size[i+1]= _core_if->params.data_fifo_size - txfifosize.b.startaddr; + //txfifosize.b.depth=_core_if->params.tx_fifo_size[i+1]; + ifxusb_wreg( &global_regs->dptxfsiz_dieptxf[i], txfifosize.d32); + txfifosize.b.startaddr += _core_if->params.tx_fifo_size[i+1]; + } + #endif + } + + #ifdef __DEBUG__ + { + fifosize_data_t fifosize; + IFX_DEBUGPL(DBG_CIL, "Result : FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size); + + IFX_DEBUGPL(DBG_CIL, " Rx FIFO =0x%06X Sz=0x%06X\n", 0,ifxusb_rreg(&global_regs->grxfsiz)); + #ifdef __DED_FIFO__ + fifosize.d32=ifxusb_rreg(&global_regs->gnptxfsiz); + IFX_DEBUGPL(DBG_CIL, " Tx[00] FIFO =0x%06X Sz=0x%06X\n", fifosize.b.startaddr,fifosize.b.depth); + for (i=1; i <= _core_if->hwcfg4.b.num_in_eps; i++) + { + fifosize.d32=ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i-1]); + IFX_DEBUGPL(DBG_CIL, " Tx[%02d] FIFO 0x%06X Sz=0x%06X\n",i, fifosize.b.startaddr,fifosize.b.depth); + } + #else + fifosize.d32=ifxusb_rreg(&global_regs->gnptxfsiz); + IFX_DEBUGPL(DBG_CIL, " NPTx FIFO =0x%06X Sz=0x%06X\n", fifosize.b.startaddr,fifosize.b.depth); + for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++) + { + fifosize.d32=ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i]); + IFX_DEBUGPL(DBG_CIL, " PTx[%02d] FIFO 0x%06X Sz=0x%06X\n",i, fifosize.b.startaddr,fifosize.b.depth); + } + #endif + } + #endif + + /* Clear Host Set HNP Enable in the OTG Control Register */ + gotgctl.b.hstsethnpen = 1; + ifxusb_mreg( &global_regs->gotgctl, gotgctl.d32, 0); + + /* Flush the FIFOs */ + ifxusb_flush_tx_fifo(_core_if, 0x10); /* all Tx FIFOs */ + ifxusb_flush_rx_fifo(_core_if); + + /* Flush the Learning Queue. */ + resetctl.b.intknqflsh = 1; + ifxusb_wreg( &global_regs->grstctl, resetctl.d32); + + /* Clear all pending Device Interrupts */ + ifxusb_wreg( &_core_if->dev_global_regs->diepmsk , 0 ); + ifxusb_wreg( &_core_if->dev_global_regs->doepmsk , 0 ); + ifxusb_wreg( &_core_if->dev_global_regs->daint , 0xFFFFFFFF ); + ifxusb_wreg( &_core_if->dev_global_regs->daintmsk, 0 ); + + dir=_core_if->hwcfg1.d32; + for (i=0; i <= _core_if->hwcfg2.b.num_dev_ep ; i++,dir>>=2) + { + depctl_data_t depctl; + if((dir&0x03)==0 || (dir&0x03) ==1) + { + depctl.d32 = ifxusb_rreg(&_core_if->in_ep_regs[i]->diepctl); + if (depctl.b.epena) + { + depctl.d32 = 0; + depctl.b.epdis = 1; + depctl.b.snak = 1; + } + else + depctl.d32 = 0; + ifxusb_wreg( &_core_if->in_ep_regs[i]->diepctl, depctl.d32); + #ifndef __DESC_DMA__ + ifxusb_wreg( &_core_if->in_ep_regs[i]->dieptsiz, 0); + #endif + ifxusb_wreg( &_core_if->in_ep_regs[i]->diepdma, 0); + ifxusb_wreg( &_core_if->in_ep_regs[i]->diepint, 0xFF); + } + + if((dir&0x03)==0 || (dir&0x03) ==2) + { + depctl.d32 = ifxusb_rreg(&_core_if->out_ep_regs[i]->doepctl); + if (depctl.b.epena) + { + depctl.d32 = 0; + depctl.b.epdis = 1; + depctl.b.snak = 1; + } + else + depctl.d32 = 0; + ifxusb_wreg( &_core_if->out_ep_regs[i]->doepctl, depctl.d32); + #ifndef __DESC_DMA__ + ifxusb_wreg( &_core_if->out_ep_regs[i]->doeptsiz, 0); + #endif + ifxusb_wreg( &_core_if->out_ep_regs[i]->doepdma, 0); + ifxusb_wreg( &_core_if->out_ep_regs[i]->doepint, 0xFF); + } + } +} + diff --git a/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_cif_h.c b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_cif_h.c new file mode 100644 index 0000000000..0f47ecd1ab --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_cif_h.c @@ -0,0 +1,846 @@ +/***************************************************************************** + ** FILE NAME : ifxusb_cif_h.c + ** PROJECT : IFX USB sub-system V3 + ** MODULES : IFX USB sub-system Host and Device driver + ** SRC VERSION : 1.0 + ** DATE : 1/Jan/2009 + ** AUTHOR : Chen, Howard + ** DESCRIPTION : The Core Interface provides basic services for accessing and + ** managing the IFX USB hardware. These services are used by the + ** Host Controller Driver only. + *****************************************************************************/ + +/*! + \file ifxusb_cif_h.c + \ingroup IFXUSB_DRIVER_V3 + \brief This file contains the interface to the IFX USB Core. +*/ +#include +#include "ifxusb_version.h" + +#include +#include + +#ifdef __DEBUG__ + #include +#endif +#include +#include +#include +#if defined(__UEIP__) +// #include +#endif + +//#include +#if defined(__UEIP__) +// #include +#endif + +#include "ifxusb_plat.h" +#include "ifxusb_regs.h" +#include "ifxusb_cif.h" + +#include "ifxhcd.h" + +#if !defined(__UEIP__) + #undef __USING_LED_AS_GPIO__ +#endif + + +/*! + \brief This function enables the Host mode interrupts. + \param _core_if Pointer of core_if structure + */ +void ifxusb_host_enable_interrupts(ifxusb_core_if_t *_core_if) +{ + gint_data_t intr_mask ={ .d32 = 0}; + ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; + + IFX_DEBUGPL(DBG_CIL, "%s()\n", __func__); + + /* Clear any pending OTG Interrupts */ + ifxusb_wreg( &global_regs->gotgint, 0xFFFFFFFF); + + /* Clear any pending interrupts */ + ifxusb_wreg( &global_regs->gintsts, 0xFFFFFFFF); + + /* Enable the interrupts in the GINTMSK.*/ + + /* Common interrupts */ + intr_mask.b.modemismatch = 1; + intr_mask.b.conidstschng = 1; + intr_mask.b.wkupintr = 1; + intr_mask.b.disconnect = 1; + intr_mask.b.usbsuspend = 1; + + /* Host interrupts */ + intr_mask.b.sofintr = 1; + intr_mask.b.portintr = 1; + intr_mask.b.hcintr = 1; + + ifxusb_mreg( &global_regs->gintmsk, intr_mask.d32, intr_mask.d32); + IFX_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, ifxusb_rreg( &global_regs->gintmsk)); +} + +/*! + \brief This function disables the Host mode interrupts. + \param _core_if Pointer of core_if structure + */ +void ifxusb_host_disable_interrupts(ifxusb_core_if_t *_core_if) +{ + ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; + + IFX_DEBUGPL(DBG_CILV, "%s()\n", __func__); + + #if 1 + ifxusb_wreg( &global_regs->gintmsk, 0); + #else + /* Common interrupts */ + { + gint_data_t intr_mask ={.d32 = 0}; + intr_mask.b.modemismatch = 1; + intr_mask.b.rxstsqlvl = 1; + intr_mask.b.conidstschng = 1; + intr_mask.b.wkupintr = 1; + intr_mask.b.disconnect = 1; + intr_mask.b.usbsuspend = 1; + + /* Host interrupts */ + intr_mask.b.sofintr = 1; + intr_mask.b.portintr = 1; + intr_mask.b.hcintr = 1; + intr_mask.b.ptxfempty = 1; + intr_mask.b.nptxfempty = 1; + ifxusb_mreg(&global_regs->gintmsk, intr_mask.d32, 0); + } + #endif +} + +/*! + \brief This function initializes the IFXUSB controller registers for Host mode. + This function flushes the Tx and Rx FIFOs and it flushes any entries in the + request queues. + \param _core_if Pointer of core_if structure + \param _params parameters to be set + */ +void ifxusb_host_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params) +{ + ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; + + gusbcfg_data_t usbcfg ={.d32 = 0}; + gahbcfg_data_t ahbcfg ={.d32 = 0}; + gotgctl_data_t gotgctl ={.d32 = 0}; + + int i; + + IFX_DEBUGPL(DBG_CILV, "%s(%p)\n",__func__,_core_if); + + /* Copy Params */ + + _core_if->params.dma_burst_size = _params->dma_burst_size; + _core_if->params.speed = _params->speed; + _core_if->params.max_transfer_size = _params->max_transfer_size; + _core_if->params.max_packet_count = _params->max_packet_count; + _core_if->params.phy_utmi_width = _params->phy_utmi_width; + _core_if->params.turn_around_time_hs = _params->turn_around_time_hs; + _core_if->params.turn_around_time_fs = _params->turn_around_time_fs; + _core_if->params.timeout_cal_hs = _params->timeout_cal_hs; + _core_if->params.timeout_cal_fs = _params->timeout_cal_fs; + + /* Reset the Controller */ + do + { + while(ifxusb_core_soft_reset( _core_if )) + ifxusb_hard_reset(_core_if); + } while (ifxusb_is_device_mode(_core_if)); + + usbcfg.d32 = ifxusb_rreg(&global_regs->gusbcfg); +// usbcfg.b.ulpi_ext_vbus_drv = 1; + usbcfg.b.term_sel_dl_pulse = 0; + ifxusb_wreg (&global_regs->gusbcfg, usbcfg.d32); + + /* This programming sequence needs to happen in FS mode before any other + * programming occurs */ + /* High speed PHY. */ + if (!_core_if->phy_init_done) + { + _core_if->phy_init_done = 1; + /* HS PHY parameters. These parameters are preserved + * during soft reset so only program the first time. Do + * a soft reset immediately after setting phyif. */ + usbcfg.b.ulpi_utmi_sel = 0; //UTMI+ + usbcfg.b.phyif = ( _core_if->params.phy_utmi_width == 16)?1:0; + ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32); + /* Reset after setting the PHY parameters */ + ifxusb_core_soft_reset( _core_if ); + } + + usbcfg.d32 = ifxusb_rreg(&global_regs->gusbcfg); +// usbcfg.b.ulpi_fsls = 0; +// usbcfg.b.ulpi_clk_sus_m = 0; + ifxusb_wreg(&global_regs->gusbcfg, usbcfg.d32); + + /* Program the GAHBCFG Register.*/ + switch (_core_if->params.dma_burst_size) + { + case 0 : + ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_SINGLE; + break; + case 1 : + ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR; + break; + case 4 : + ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR4; + break; + case 8 : + ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR8; + break; + case 16: + ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR16; + break; + } + ahbcfg.b.dmaenable = 1; + ifxusb_wreg(&global_regs->gahbcfg, ahbcfg.d32); + + /* Program the GUSBCFG register. */ + usbcfg.d32 = ifxusb_rreg( &global_regs->gusbcfg ); + usbcfg.b.hnpcap = 0; + usbcfg.b.srpcap = 0; + ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32); + + /* Restart the Phy Clock */ + ifxusb_wreg(_core_if->pcgcctl, 0); + + /* Initialize Host Configuration Register */ + { + hcfg_data_t hcfg; + hcfg.d32 = ifxusb_rreg(&_core_if->host_global_regs->hcfg); + hcfg.b.fslspclksel = IFXUSB_HCFG_30_60_MHZ; + if (_params->speed == IFXUSB_PARAM_SPEED_FULL) + hcfg.b.fslssupp = 1; + ifxusb_wreg(&_core_if->host_global_regs->hcfg, hcfg.d32); + } + + _core_if->params.host_channels=(_core_if->hwcfg2.b.num_host_chan + 1); + + if(_params->host_channels>0 && _params->host_channels < _core_if->params.host_channels) + _core_if->params.host_channels = _params->host_channels; + + /* Configure data FIFO sizes */ + _core_if->params.data_fifo_size = _core_if->hwcfg3.b.dfifo_depth; + _core_if->params.rx_fifo_size = ifxusb_rreg(&global_regs->grxfsiz); + _core_if->params.nperio_tx_fifo_size= ifxusb_rreg(&global_regs->gnptxfsiz) >> 16; + _core_if->params.perio_tx_fifo_size = ifxusb_rreg(&global_regs->hptxfsiz) >> 16; + IFX_DEBUGPL(DBG_CIL, "Initial: FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size); + IFX_DEBUGPL(DBG_CIL, " Rx FIFO Size=0x%06X\n", _core_if->params.rx_fifo_size); + IFX_DEBUGPL(DBG_CIL, " NPTx FIFO Size=0x%06X\n", _core_if->params.nperio_tx_fifo_size); + IFX_DEBUGPL(DBG_CIL, " PTx FIFO Size=0x%06X\n", _core_if->params.perio_tx_fifo_size); + + { + fifosize_data_t txfifosize; + if(_params->data_fifo_size >=0 && _params->data_fifo_size < _core_if->params.data_fifo_size) + _core_if->params.data_fifo_size = _params->data_fifo_size; + + if( _params->rx_fifo_size >= 0 && _params->rx_fifo_size < _core_if->params.rx_fifo_size) + _core_if->params.rx_fifo_size = _params->rx_fifo_size; + if( _params->nperio_tx_fifo_size >=0 && _params->nperio_tx_fifo_size < _core_if->params.nperio_tx_fifo_size) + _core_if->params.nperio_tx_fifo_size = _params->nperio_tx_fifo_size; + if( _params->perio_tx_fifo_size >=0 && _params->perio_tx_fifo_size < _core_if->params.perio_tx_fifo_size) + _core_if->params.perio_tx_fifo_size = _params->perio_tx_fifo_size; + + if(_core_if->params.data_fifo_size < _core_if->params.rx_fifo_size) + _core_if->params.rx_fifo_size = _core_if->params.data_fifo_size; + ifxusb_wreg( &global_regs->grxfsiz, _core_if->params.rx_fifo_size); + txfifosize.b.startaddr = _core_if->params.rx_fifo_size; + + if(txfifosize.b.startaddr + _core_if->params.nperio_tx_fifo_size > _core_if->params.data_fifo_size) + _core_if->params.nperio_tx_fifo_size = _core_if->params.data_fifo_size - txfifosize.b.startaddr; + txfifosize.b.depth=_core_if->params.nperio_tx_fifo_size; + ifxusb_wreg( &global_regs->gnptxfsiz, txfifosize.d32); + txfifosize.b.startaddr += _core_if->params.nperio_tx_fifo_size; + + if(txfifosize.b.startaddr + _core_if->params.perio_tx_fifo_size > _core_if->params.data_fifo_size) + _core_if->params.perio_tx_fifo_size = _core_if->params.data_fifo_size - txfifosize.b.startaddr; + txfifosize.b.depth=_core_if->params.perio_tx_fifo_size; + ifxusb_wreg( &global_regs->hptxfsiz, txfifosize.d32); + txfifosize.b.startaddr += _core_if->params.perio_tx_fifo_size; + } + + #ifdef __DEBUG__ + { + fifosize_data_t fifosize; + IFX_DEBUGPL(DBG_CIL, "Result : FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size); + + fifosize.d32=ifxusb_rreg(&global_regs->grxfsiz); + IFX_DEBUGPL(DBG_CIL, " Rx FIFO =0x%06X 0x%06X\n", fifosize.b.startaddr,fifosize.b.depth); + fifosize.d32=ifxusb_rreg(&global_regs->gnptxfsiz); + IFX_DEBUGPL(DBG_CIL, " NPTx FIFO =0x%06X 0x%06X\n", fifosize.b.startaddr,fifosize.b.depth); + fifosize.d32=ifxusb_rreg(&global_regs->hptxfsiz); + IFX_DEBUGPL(DBG_CIL, " PTx FIFO =0x%06X 0x%06X\n", fifosize.b.startaddr,fifosize.b.depth); + } + #endif + + /* Clear Host Set HNP Enable in the OTG Control Register */ + gotgctl.b.hstsethnpen = 1; + ifxusb_mreg( &global_regs->gotgctl, gotgctl.d32, 0); + + /* Flush the FIFOs */ + ifxusb_flush_tx_fifo(_core_if, 0x10); /* all Tx FIFOs */ + ifxusb_flush_rx_fifo(_core_if); + + for (i = 0; i < _core_if->hwcfg2.b.num_host_chan + 1; i++) + { + hcchar_data_t hcchar; + hcchar.d32 = ifxusb_rreg(&_core_if->hc_regs[i]->hcchar); + hcchar.b.chen = 0; + hcchar.b.chdis = 1; + hcchar.b.epdir = 0; + ifxusb_wreg(&_core_if->hc_regs[i]->hcchar, hcchar.d32); + } + /* Halt all channels to put them into a known state. */ + for (i = 0; i < _core_if->hwcfg2.b.num_host_chan + 1; i++) + { + hcchar_data_t hcchar; + int count = 0; + + hcchar.d32 = ifxusb_rreg(&_core_if->hc_regs[i]->hcchar); + hcchar.b.chen = 1; + hcchar.b.chdis = 1; + hcchar.b.epdir = 0; + ifxusb_wreg(&_core_if->hc_regs[i]->hcchar, hcchar.d32); + + IFX_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i); + do{ + hcchar.d32 = ifxusb_rreg(&_core_if->hc_regs[i]->hcchar); + if (++count > 1000) + { + IFX_ERROR("%s: Unable to clear halt on channel %d\n", __func__, i); + break; + } + } while (hcchar.b.chen); + } +} + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +#if defined(__UEIP__) + #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS) + int ifxusb_vbus_status =-1; + #endif + + #if defined(IFX_GPIO_USB_VBUS1) || defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1) + int ifxusb_vbus1_status =-1; + #endif + + #if defined(IFX_GPIO_USB_VBUS2) || defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2) + int ifxusb_vbus2_status =-1; + #endif + + #if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS) + static void *g_usb_vbus_trigger = NULL; + #endif + #if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1) + static void *g_usb_vbus1_trigger = NULL; + #endif + #if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2) + static void *g_usb_vbus2_trigger = NULL; + #endif + + #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) + int ifxusb_vbus_gpio_inited=0; + #endif + +#else //defined(__UEIP__) + int ifxusb_vbus_gpio_inited=0; +#endif + +////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +void ifxusb_vbus_init(ifxusb_core_if_t *_core_if) +{ + #if defined(__UEIP__) + #if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS) + if ( !g_usb_vbus_trigger ) + { + ifx_led_trigger_register("USB_VBUS", &g_usb_vbus_trigger); + if ( g_usb_vbus_trigger != NULL ) + { + struct ifx_led_trigger_attrib attrib = {0}; + attrib.delay_on = 0; + attrib.delay_off = 0; + attrib.timeout = 0; + attrib.def_value = 0; + attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE; + IFX_DEBUGP("Reg USB power!!\n"); + ifx_led_trigger_set_attrib(g_usb_vbus_trigger, &attrib); + ifxusb_vbus_status =0; + } + } + #endif + #if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1) + if(_core_if->core_no==0 && !g_usb_vbus1_trigger ) + { + ifx_led_trigger_register("USB_VBUS1", &g_usb_vbus1_trigger); + if ( g_usb_vbus1_trigger != NULL ) + { + struct ifx_led_trigger_attrib attrib = {0}; + attrib.delay_on = 0; + attrib.delay_off = 0; + attrib.timeout = 0; + attrib.def_value = 0; + attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE; + IFX_DEBUGP("Reg USB1 power!!\n"); + ifx_led_trigger_set_attrib(g_usb_vbus1_trigger, &attrib); + ifxusb_vbus1_status =0; + } + } + #endif + #if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2) + if(_core_if->core_no==1 && !g_usb_vbus2_trigger ) + { + ifx_led_trigger_register("USB_VBUS2", &g_usb_vbus2_trigger); + if ( g_usb_vbus2_trigger != NULL ) + { + struct ifx_led_trigger_attrib attrib = {0}; + attrib.delay_on = 0; + attrib.delay_off = 0; + attrib.timeout = 0; + attrib.def_value = 0; + attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE; + IFX_DEBUGP("Reg USB2 power!!\n"); + ifx_led_trigger_set_attrib(g_usb_vbus2_trigger, &attrib); + ifxusb_vbus2_status =0; + } + } + #endif + + #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) + /* == 20100712 AVM/WK use gpio_inited as bitmask == */ + if(ifxusb_vbus_gpio_inited == 0) + { + if(!ifx_gpio_register(IFX_GPIO_MODULE_USB)) + { + IFX_DEBUGP("Register USB VBus through GPIO OK!!\n"); + #ifdef IFX_GPIO_USB_VBUS + ifxusb_vbus_status =0; + #endif //IFX_GPIO_USB_VBUS + #ifdef IFX_GPIO_USB_VBUS1 + ifxusb_vbus1_status=0; + #endif //IFX_GPIO_USB_VBUS1 + #ifdef IFX_GPIO_USB_VBUS2 + ifxusb_vbus2_status=0; + #endif //IFX_GPIO_USB_VBUS2 + ifxusb_vbus_gpio_inited|= (1<<_core_if->core_no); + } + else + IFX_PRINT("Register USB VBus Failed!!\n"); + } else { + ifxusb_vbus_gpio_inited|= (1<<_core_if->core_no); + } + #endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) + #endif //defined(__UEIP__) +} + +void ifxusb_vbus_free(ifxusb_core_if_t *_core_if) +{ + #if defined(__UEIP__) + #if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS) + if ( g_usb_vbus_trigger ) + { + ifx_led_trigger_deregister(g_usb_vbus_trigger); + g_usb_vbus_trigger = NULL; + ifxusb_vbus_status =-1; + } + #endif + #if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1) + if(_core_if->core_no==0 && g_usb_vbus1_trigger ) + { + ifx_led_trigger_deregister(g_usb_vbus1_trigger); + g_usb_vbus1_trigger = NULL; + ifxusb_vbus1_status =-1; + } + #endif + #if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2) + if(_core_if->core_no==1 && g_usb_vbus2_trigger ) + { + ifx_led_trigger_deregister(g_usb_vbus2_trigger); + g_usb_vbus2_trigger = NULL; + ifxusb_vbus2_status =-1; + } + #endif + + #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) + /* == 20100712 AVM/WK use gpio_inited as bitmask == */ + if((ifxusb_vbus_gpio_inited & (1<<_core_if->core_no)) == ifxusb_vbus_gpio_inited) + { + ifx_gpio_deregister(IFX_GPIO_MODULE_USB); + #ifdef IFX_GPIO_USB_VBUS + ifxusb_vbus_status =-1; + #endif //IFX_GPIO_USB_VBUS + #ifdef IFX_GPIO_USB_VBUS1 + ifxusb_vbus1_status=-1; + #endif //IFX_GPIO_USB_VBUS1 + #ifdef IFX_GPIO_USB_VBUS2 + ifxusb_vbus2_status=-1; + #endif //IFX_GPIO_USB_VBUS2 + } + ifxusb_vbus_gpio_inited &= ~(1<<_core_if->core_no); + #endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) + #endif //defined(__UEIP__) +} + + +/*! + \brief Turn on the USB 5V VBus Power + \param _core_if Pointer of core_if structure + */ +void ifxusb_vbus_on(ifxusb_core_if_t *_core_if) +{ + IFX_DEBUGP("SENDING VBus POWER UP\n"); + #if defined(__UEIP__) + #if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS) + if ( g_usb_vbus_trigger && ifxusb_vbus_status==0) + { + ifx_led_trigger_activate(g_usb_vbus_trigger); + IFX_DEBUGP("Enable USB power!!\n"); + ifxusb_vbus_status=1; + } + #endif + #if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1) + if(_core_if->core_no==0 && g_usb_vbus1_trigger && ifxusb_vbus1_status==0) + { + ifx_led_trigger_activate(g_usb_vbus1_trigger); + IFX_DEBUGP("Enable USB1 power!!\n"); + ifxusb_vbus1_status=1; + } + #endif + #if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2) + if(_core_if->core_no==1 && g_usb_vbus2_trigger && ifxusb_vbus2_status==0) + { + ifx_led_trigger_activate(g_usb_vbus2_trigger); + IFX_DEBUGP("Enable USB2 power!!\n"); + ifxusb_vbus2_status=1; + } + #endif + + #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) + if(ifxusb_vbus_gpio_inited) + { + #if defined(IFX_GPIO_USB_VBUS) + if(ifxusb_vbus_status==0) + { + ifx_gpio_output_set(IFX_GPIO_USB_VBUS,IFX_GPIO_MODULE_USB); + ifxusb_vbus_status=1; + } + #endif + #if defined(IFX_GPIO_USB_VBUS1) + if(_core_if->core_no==0 && ifxusb_vbus1_status==0) + { + ifx_gpio_output_set(IFX_GPIO_USB_VBUS1,IFX_GPIO_MODULE_USB); + ifxusb_vbus1_status=1; + } + #endif + #if defined(IFX_GPIO_USB_VBUS2) + if(_core_if->core_no==1 && ifxusb_vbus2_status==0) + { + ifx_gpio_output_set(IFX_GPIO_USB_VBUS2,IFX_GPIO_MODULE_USB); + ifxusb_vbus2_status=1; + } + #endif + } + #endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) + #else + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + ifxusb_vbus_status=1; + //usb_set_vbus_on(); + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined(__IS_AMAZON_SE__) + set_bit (4, (volatile unsigned long *)AMAZON_SE_GPIO_P0_OUT); + ifxusb_vbus_status=1; + #endif //defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) + if(_core_if->core_no==0) + { + if (bsp_port_reserve_pin(1, 13, PORT_MODULE_USB) != 0) + { + IFX_PRINT("Can't enable USB1 5.5V power!!\n"); + return; + } + bsp_port_clear_altsel0(1, 13, PORT_MODULE_USB); + bsp_port_clear_altsel1(1, 13, PORT_MODULE_USB); + bsp_port_set_dir_out(1, 13, PORT_MODULE_USB); + bsp_port_set_pudsel(1, 13, PORT_MODULE_USB); + bsp_port_set_puden(1, 13, PORT_MODULE_USB); + bsp_port_set_output(1, 13, PORT_MODULE_USB); + IFX_DEBUGP("Enable USB1 power!!\n"); + ifxusb_vbus1_status=1; + } + else + { + if (bsp_port_reserve_pin(3, 4, PORT_MODULE_USB) != 0) + { + IFX_PRINT("Can't enable USB2 5.5V power!!\n"); + return; + } + bsp_port_clear_altsel0(3, 4, PORT_MODULE_USB); + bsp_port_clear_altsel1(3, 4, PORT_MODULE_USB); + bsp_port_set_dir_out(3, 4, PORT_MODULE_USB); + bsp_port_set_pudsel(3, 4, PORT_MODULE_USB); + bsp_port_set_puden(3, 4, PORT_MODULE_USB); + bsp_port_set_output(3, 4, PORT_MODULE_USB); + IFX_DEBUGP("Enable USB2 power!!\n"); + ifxusb_vbus2_status=1; + } + #endif //defined(__IS_AR9__) + #if defined(__IS_VR9__) + if(_core_if->core_no==0) + { + ifxusb_vbus1_status=1; + } + else + { + ifxusb_vbus2_status=1; + } + #endif //defined(__IS_VR9__) + #endif //defined(__UEIP__) +} + + +/*! + \brief Turn off the USB 5V VBus Power + \param _core_if Pointer of core_if structure + */ +void ifxusb_vbus_off(ifxusb_core_if_t *_core_if) +{ + IFX_DEBUGP("SENDING VBus POWER OFF\n"); + + #if defined(__UEIP__) + #if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS) + if ( g_usb_vbus_trigger && ifxusb_vbus_status==1) + { + ifx_led_trigger_deactivate(g_usb_vbus_trigger); + IFX_DEBUGP("Disable USB power!!\n"); + ifxusb_vbus_status=0; + } + #endif + #if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1) + if(_core_if->core_no==0 && g_usb_vbus1_trigger && ifxusb_vbus1_status==1) + { + ifx_led_trigger_deactivate(g_usb_vbus1_trigger); + IFX_DEBUGP("Disable USB1 power!!\n"); + ifxusb_vbus1_status=0; + } + #endif + #if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2) + if(_core_if->core_no==1 && g_usb_vbus2_trigger && ifxusb_vbus2_status==1) + { + ifx_led_trigger_deactivate(g_usb_vbus2_trigger); + IFX_DEBUGP("Disable USB2 power!!\n"); + ifxusb_vbus2_status=0; + } + #endif + + #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) + if(ifxusb_vbus_gpio_inited) + { + #if defined(IFX_GPIO_USB_VBUS) + if(ifxusb_vbus_status==1) + { + ifx_gpio_output_clear(IFX_GPIO_USB_VBUS,IFX_GPIO_MODULE_USB); + ifxusb_vbus_status=0; + } + #endif + #if defined(IFX_GPIO_USB_VBUS1) + if(_core_if->core_no==0 && ifxusb_vbus1_status==1) + { + ifx_gpio_output_clear(IFX_GPIO_USB_VBUS1,IFX_GPIO_MODULE_USB); + ifxusb_vbus1_status=0; + } + #endif + #if defined(IFX_GPIO_USB_VBUS2) + if(_core_if->core_no==1 && ifxusb_vbus2_status==1) + { + ifx_gpio_output_clear(IFX_GPIO_USB_VBUS2,IFX_GPIO_MODULE_USB); + ifxusb_vbus2_status=0; + } + #endif + } + #endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) + #else + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + ifxusb_vbus_status=0; + //usb_set_vbus_on(); + #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) + #if defined(__IS_AMAZON_SE__) + clear_bit (4, (volatile unsigned long *)AMAZON_SE_GPIO_P0_OUT); + ifxusb_vbus_status=0; + #endif //defined(__IS_AMAZON_SE__) + #if defined(__IS_AR9__) + if(_core_if->core_no==0) + { + if (bsp_port_reserve_pin(1, 13, PORT_MODULE_USB) != 0) { + IFX_PRINT("Can't Disable USB1 5.5V power!!\n"); + return; + } + bsp_port_clear_altsel0(1, 13, PORT_MODULE_USB); + bsp_port_clear_altsel1(1, 13, PORT_MODULE_USB); + bsp_port_set_dir_out(1, 13, PORT_MODULE_USB); + bsp_port_set_pudsel(1, 13, PORT_MODULE_USB); + bsp_port_set_puden(1, 13, PORT_MODULE_USB); + bsp_port_clear_output(1, 13, PORT_MODULE_USB); + IFX_DEBUGP("Disable USB1 power!!\n"); + ifxusb_vbus1_status=0; + } + else + { + if (bsp_port_reserve_pin(3, 4, PORT_MODULE_USB) != 0) { + IFX_PRINT("Can't Disable USB2 5.5V power!!\n"); + return; + } + bsp_port_clear_altsel0(3, 4, PORT_MODULE_USB); + bsp_port_clear_altsel1(3, 4, PORT_MODULE_USB); + bsp_port_set_dir_out(3, 4, PORT_MODULE_USB); + bsp_port_set_pudsel(3, 4, PORT_MODULE_USB); + bsp_port_set_puden(3, 4, PORT_MODULE_USB); + bsp_port_clear_output(3, 4, PORT_MODULE_USB); + IFX_DEBUGP("Disable USB2 power!!\n"); + + ifxusb_vbus2_status=0; + } + #endif //defined(__IS_AR9__) + #if defined(__IS_VR9__) + if(_core_if->core_no==0) + { + ifxusb_vbus1_status=0; + } + else + { + ifxusb_vbus2_status=0; + } + #endif //defined(__IS_VR9__) + #endif //defined(__UEIP__) +} + + + +/*! + \brief Read Current VBus status + \param _core_if Pointer of core_if structure + */ +int ifxusb_vbus(ifxusb_core_if_t *_core_if) +{ +#if defined(__UEIP__) + #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS) + return (ifxusb_vbus_status); + #endif + + #if defined(IFX_GPIO_USB_VBUS1) || defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1) + if(_core_if->core_no==0) + return (ifxusb_vbus1_status); + #endif + + #if defined(IFX_GPIO_USB_VBUS2) || defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2) + if(_core_if->core_no==1) + return (ifxusb_vbus2_status); + #endif +#else //defined(__UEIP__) +#endif + return -1; +} + +#if defined(__UEIP__) +#else + #if defined(__IS_TWINPASS__) + #define ADSL_BASE 0x20000 + #define CRI_BASE 0x31F00 + #define CRI_CCR0 CRI_BASE + 0x00 + #define CRI_CCR1 CRI_BASE + 0x01*4 + #define CRI_CDC0 CRI_BASE + 0x02*4 + #define CRI_CDC1 CRI_BASE + 0x03*4 + #define CRI_RST CRI_BASE + 0x04*4 + #define CRI_MASK0 CRI_BASE + 0x05*4 + #define CRI_MASK1 CRI_BASE + 0x06*4 + #define CRI_MASK2 CRI_BASE + 0x07*4 + #define CRI_STATUS0 CRI_BASE + 0x08*4 + #define CRI_STATUS1 CRI_BASE + 0x09*4 + #define CRI_STATUS2 CRI_BASE + 0x0A*4 + #define CRI_AMASK0 CRI_BASE + 0x0B*4 + #define CRI_AMASK1 CRI_BASE + 0x0C*4 + #define CRI_UPDCTL CRI_BASE + 0x0D*4 + #define CRI_MADST CRI_BASE + 0x0E*4 + // 0x0f is missing + #define CRI_EVENT0 CRI_BASE + 0x10*4 + #define CRI_EVENT1 CRI_BASE + 0x11*4 + #define CRI_EVENT2 CRI_BASE + 0x12*4 + + #define IRI_I_ENABLE 0x32000 + #define STY_SMODE 0x3c004 + #define AFE_TCR_0 0x3c0dc + #define AFE_ADDR_ADDR 0x3c0e8 + #define AFE_RDATA_ADDR 0x3c0ec + #define AFE_WDATA_ADDR 0x3c0f0 + #define AFE_CONFIG 0x3c0f4 + #define AFE_SERIAL_CFG 0x3c0fc + + #define DFE_BASE_ADDR 0xBE116000 + //#define DFE_BASE_ADDR 0x9E116000 + + #define MEI_FR_ARCINT_C (DFE_BASE_ADDR + 0x0000001C) + #define MEI_DBG_WADDR_C (DFE_BASE_ADDR + 0x00000024) + #define MEI_DBG_RADDR_C (DFE_BASE_ADDR + 0x00000028) + #define MEI_DBG_DATA_C (DFE_BASE_ADDR + 0x0000002C) + #define MEI_DBG_DECO_C (DFE_BASE_ADDR + 0x00000030) + #define MEI_DBG_MASTER_C (DFE_BASE_ADDR + 0x0000003C) + + static void WriteARCmem(uint32_t addr, uint32_t data) + { + writel(1 ,(volatile uint32_t *)MEI_DBG_MASTER_C); + writel(1 ,(volatile uint32_t *)MEI_DBG_DECO_C ); + writel(addr ,(volatile uint32_t *)MEI_DBG_WADDR_C ); + writel(data ,(volatile uint32_t *)MEI_DBG_DATA_C ); + while( (ifxusb_rreg((volatile uint32_t *)MEI_FR_ARCINT_C) & 0x20) != 0x20 ){}; + writel(0 ,(volatile uint32_t *)MEI_DBG_MASTER_C); + IFX_DEBUGP("WriteARCmem %08x %08x\n",addr,data); + }; + + static uint32_t ReadARCmem(uint32_t addr) + { + u32 data; + writel(1 ,(volatile uint32_t *)MEI_DBG_MASTER_C); + writel(1 ,(volatile uint32_t *)MEI_DBG_DECO_C ); + writel(addr ,(volatile uint32_t *)MEI_DBG_RADDR_C ); + while( (ifxusb_rreg((volatile uint32_t *)MEI_FR_ARCINT_C) & 0x20) != 0x20 ){}; + data = ifxusb_rreg((volatile uint32_t *)MEI_DBG_DATA_C ); + writel(0 ,(volatile uint32_t *)MEI_DBG_MASTER_C); + IFX_DEBUGP("ReadARCmem %08x %08x\n",addr,data); + return data; + }; + + void ifxusb_enable_afe_oc(void) + { + /* Start the clock */ + WriteARCmem(CRI_UPDCTL ,0x00000008); + WriteARCmem(CRI_CCR0 ,0x00000014); + WriteARCmem(CRI_CCR1 ,0x00000500); + WriteARCmem(AFE_CONFIG ,0x000001c8); + WriteARCmem(AFE_SERIAL_CFG,0x00000016); // (DANUBE_PCI_CFG_BASE+(1< +#include "ifxusb_version.h" + + +#include +#include +#include +#include + +#include "ifxusb_plat.h" +#include "ifxusb_regs.h" +#include "ifxusb_cif.h" + +#ifdef __IS_DEVICE__ + #include "ifxpcd.h" +#endif + +#ifdef __IS_HOST__ + #include "ifxhcd.h" +#endif + +#include +#include +#include + + +#ifdef __IS_HOST__ + extern char ifxusb_driver_name[]; + + #ifdef __IS_DUAL__ + extern ifxhcd_hcd_t ifxusb_hcd_1; + extern ifxhcd_hcd_t ifxusb_hcd_2; + extern char ifxusb_hcd_name_1[]; + extern char ifxusb_hcd_name_2[]; + #else + extern ifxhcd_hcd_t ifxusb_hcd; + extern char ifxusb_hcd_name[]; + #endif + +#endif + +#ifdef __IS_DEVICE__ + extern char ifxusb_driver_name[]; + + extern ifxpcd_pcd_t ifxusb_pcd; + extern char ifxusb_pcd_name[]; +#endif + + +//Attributes for sysfs (for 2.6 only) + +extern struct device_attribute dev_attr_dbglevel; + +#ifdef __IS_DUAL__ + extern struct device_attribute dev_attr_dump_params_1; + extern struct device_attribute dev_attr_dump_params_2; +#else + extern struct device_attribute dev_attr_dump_params; +#endif + +#ifdef __IS_DUAL__ + extern struct device_attribute dev_attr_mode_1; + extern struct device_attribute dev_attr_mode_2; +#else + extern struct device_attribute dev_attr_mode; +#endif + +#ifdef __IS_HOST__ + #ifdef __IS_DUAL__ + extern struct device_attribute dev_attr_buspower_1; + extern struct device_attribute dev_attr_buspower_2; + extern struct device_attribute dev_attr_bussuspend_1; + extern struct device_attribute dev_attr_bussuspend_2; + extern struct device_attribute dev_attr_busconnected_1; + extern struct device_attribute dev_attr_busconnected_2; + extern struct device_attribute dev_attr_connectspeed_1; + extern struct device_attribute dev_attr_connectspeed_1; + #else + extern struct device_attribute dev_attr_buspower; + extern struct device_attribute dev_attr_bussuspend; + extern struct device_attribute dev_attr_busconnected; + extern struct device_attribute dev_attr_connectspeed; + #endif +#endif //__IS_HOST__ + +#ifdef __IS_DEVICE__ + extern struct device_attribute dev_attr_devspeed; + extern struct device_attribute dev_attr_enumspeed; +#endif //__IS_DEVICE__ + +#ifdef __ENABLE_DUMP__ + #ifdef __IS_DUAL__ + extern struct device_attribute dev_attr_dump_reg_1; + extern struct device_attribute dev_attr_dump_reg_2; + extern struct device_attribute dev_attr_dump_spram_1; + extern struct device_attribute dev_attr_dump_spram_2; + #ifdef __IS_HOST__ + extern struct device_attribute dev_attr_dump_host_state_1; + extern struct device_attribute dev_attr_dump_host_state_2; + #else + #endif + #else + extern struct device_attribute dev_attr_dump_reg; + extern struct device_attribute dev_attr_dump_spram; + #ifdef __IS_HOST__ + extern struct device_attribute dev_attr_dump_host_state; + #else + #endif + #endif +#endif //__ENABLE_DUMP__ + + +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// + +static ssize_t procfs_dbglevel_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) +{ + #ifdef __IS_HOST__ + return sprintf( buf, "%08X\n",h_dbg_lvl ); + #else + return sprintf( buf, "%08X\n",d_dbg_lvl ); + #endif +} + +static ssize_t procfs_dbglevel_store(struct file *file, const char *buffer, unsigned long count, void *data) +{ + char buf[10]; + int i = 0; + uint32_t value; + if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1)) + return -EFAULT; + value = simple_strtoul(buf, NULL, 16); + #ifdef __IS_HOST__ + h_dbg_lvl =value; + #else + d_dbg_lvl =value; + #endif + //turn on and off power + return count; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_dbglevel_show( struct device *_dev, struct device_attribute *attr,char *buf) +#else + static ssize_t sysfs_dbglevel_show( struct device *_dev, char *buf) +#endif +{ + #ifdef __IS_HOST__ + return sprintf( buf, "%08X\n",h_dbg_lvl ); + #else + return sprintf( buf, "%08X\n",d_dbg_lvl ); + #endif +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_dbglevel_store( struct device *_dev, struct device_attribute *attr,const char *buffer, size_t count ) +#else + static ssize_t sysfs_dbglevel_store( struct device *_dev, const char *buffer, size_t count ) +#endif +{ + char buf[10]; + int i = 0; + uint32_t value; + if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1)) + return -EFAULT; + value = simple_strtoul(buf, NULL, 16); + #ifdef __IS_HOST__ + h_dbg_lvl =value; + #else + d_dbg_lvl =value; + #endif + //turn on and off power + return count; +} + +DEVICE_ATTR(dbglevel, S_IRUGO|S_IWUSR, sysfs_dbglevel_show, sysfs_dbglevel_store); + + +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// + +static void ifxusb_dump_params(ifxusb_core_if_t *_core_if); + +#ifdef __IS_DUAL__ + static void dump_params_1(void) + { + ifxusb_dump_params(&ifxusb_hcd_1.core_if); + } + static void dump_params_2(void) + { + ifxusb_dump_params(&ifxusb_hcd_2.core_if); + } + + static ssize_t procfs_dump_params_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + dump_params_1(); + return 0; + } + static ssize_t procfs_dump_params_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + dump_params_2(); + return 0; + } + + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_dump_params_show_1( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_dump_params_show_1( struct device *_dev,char *buf) + #endif + { + dump_params_1(); + return 0; + } + DEVICE_ATTR(dump_params_1, S_IRUGO|S_IWUSR, sysfs_dump_params_show_1, NULL); + + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_dump_params_show_2( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_dump_params_show_2( struct device *_dev,char *buf) + #endif + { + dump_params_2(); + return 0; + } + + DEVICE_ATTR(dump_params_2, S_IRUGO|S_IWUSR, sysfs_dump_params_show_2, NULL); +#else + static void dump_params(void) + { + #ifdef __IS_HOST__ + ifxusb_dump_params(&ifxusb_hcd.core_if); + #else + ifxusb_dump_params(&ifxusb_pcd.core_if); + #endif + } + + static ssize_t procfs_dump_params_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + dump_params(); + return 0; + } + + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_dump_params_show( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_dump_params_show( struct device *_dev,char *buf) + #endif + { + dump_params(); + return 0; + } + DEVICE_ATTR(dump_params, S_IRUGO|S_IWUSR, sysfs_dump_params_show, NULL); +#endif + +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// + +#ifdef __IS_DUAL__ + static ssize_t mode_show_1(char *buf) + { + if((ifxusb_rreg(&ifxusb_hcd_1.core_if.core_global_regs->gintsts ) & 0x1) == 1) + return sprintf( buf, "HOST\n" ); + else + return sprintf( buf, "DEVICE(INCORRECT!)\n" ); + } + + static ssize_t mode_show_2(char *buf) + { + if((ifxusb_rreg(&ifxusb_hcd_2.core_if.core_global_regs->gintsts ) & 0x1) == 1) + return sprintf( buf, "HOST\n" ); + else + return sprintf( buf, "DEVICE(INCORRECT!)\n" ); + } + + static ssize_t procfs_mode_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + return mode_show_1(buf); + } + static ssize_t procfs_mode_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + return mode_show_2(buf); + } + + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_mode_show_1( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_mode_show_1( struct device *_dev,char *buf) + #endif + { + return mode_show_1(buf); + } + + DEVICE_ATTR(mode_1, S_IRUGO|S_IWUSR, sysfs_mode_show_1, 0); + + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_mode_show_2( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_mode_show_2( struct device *_dev,char *buf) + #endif + { + return mode_show_2(buf); + } + DEVICE_ATTR(mode_2, S_IRUGO|S_IWUSR, sysfs_mode_show_2, NULL); +#else + static ssize_t mode_show(char *buf) + { + #ifdef __IS_HOST__ + if((ifxusb_rreg(&ifxusb_hcd.core_if.core_global_regs->gintsts ) & 0x1) == 1) + return sprintf( buf, "HOST\n" ); + else + return sprintf( buf, "DEVICE(INCORRECT!)\n" ); + #else + if((ifxusb_rreg(&ifxusb_pcd.core_if.core_global_regs->gintsts ) & 0x1) != 1) + return sprintf( buf, "DEVICE\n" ); + else + return sprintf( buf, "HOST(INCORRECT!)\n" ); + #endif + } + static ssize_t procfs_mode_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + return mode_show(buf); + } + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_mode_show( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_mode_show( struct device *_dev, char *buf) + #endif + { + return mode_show(buf); + } + DEVICE_ATTR(mode, S_IRUGO|S_IWUSR, sysfs_mode_show, NULL); +#endif + +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// + +#ifdef __IS_HOST__ + #ifdef __IS_DUAL__ + static ssize_t buspower_show_1(char *buf) + { + if(ifxusb_vbus (&ifxusb_hcd_1.core_if)==1) return sprintf( buf, "1\n" ); + if(ifxusb_vbus (&ifxusb_hcd_1.core_if)==0) return sprintf( buf, "0\n" ); + return sprintf( buf, "UNKNOWN\n" ); + } + static void buspower_store_1(uint32_t value) + { + if (value==1) ifxusb_vbus_on (&ifxusb_hcd_1.core_if); + else if(value==0) ifxusb_vbus_off(&ifxusb_hcd_1.core_if); + } + static ssize_t buspower_show_2(char *buf) + { + if(ifxusb_vbus (&ifxusb_hcd_2.core_if)==1) return sprintf( buf, "1\n" ); + if(ifxusb_vbus (&ifxusb_hcd_2.core_if)==0) return sprintf( buf, "0\n" ); + return sprintf( buf, "UNKNOWN\n" ); + } + static void buspower_store_2(uint32_t value) + { + if (value==1) ifxusb_vbus_on (&ifxusb_hcd_2.core_if); + else if(value==0) ifxusb_vbus_off(&ifxusb_hcd_2.core_if); + } + static ssize_t procfs_buspower_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + return buspower_show_1(buf); + } + static ssize_t procfs_buspower_store_1(struct file *file, const char *buffer, unsigned long count, void *data) + { + char buf[10]; + int i = 0; + uint32_t value; + if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1)) + return -EFAULT; + value = simple_strtoul(buf, NULL, 16); + buspower_store_1(value); + return count; + } + static ssize_t procfs_buspower_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + return buspower_show_2(buf); + } + static ssize_t procfs_buspower_store_2(struct file *file, const char *buffer, unsigned long count, void *data) + { + char buf[10]; + int i = 0; + uint32_t value; + if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1)) + return -EFAULT; + value = simple_strtoul(buf, NULL, 16); + buspower_store_2(value); + return count; + } + + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_buspower_show_1( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_buspower_show_1( struct device *_dev,char *buf) + #endif + { + return buspower_show_1(buf); + } + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_buspower_store_1( struct device *_dev, struct device_attribute *attr,const char *buffer, size_t count ) + #else + static ssize_t sysfs_buspower_store_1( struct device *_dev, const char *buffer, size_t count ) + #endif + { + char buf[10]; + int i = 0; + uint32_t value; + if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1)) + return -EFAULT; + value = simple_strtoul(buf, NULL, 16); + buspower_store_1(value); + return count; + } + DEVICE_ATTR(buspower_1, S_IRUGO|S_IWUSR, sysfs_buspower_show_1, sysfs_buspower_store_1); + + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_buspower_show_2( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_buspower_show_2( struct device *_dev,char *buf) + #endif + { + return buspower_show_2(buf); + } + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_buspower_store_2( struct device *_dev, struct device_attribute *attr,const char *buffer, size_t count ) + #else + static ssize_t sysfs_buspower_store_2( struct device *_dev, const char *buffer, size_t count ) + #endif + { + char buf[10]; + int i = 0; + uint32_t value; + if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1)) + return -EFAULT; + value = simple_strtoul(buf, NULL, 16); + buspower_store_2(value); + return count; + } + DEVICE_ATTR(buspower_2, S_IRUGO|S_IWUSR, sysfs_buspower_show_2, sysfs_buspower_store_2); + #else + static ssize_t buspower_show(char *buf) + { + if(ifxusb_vbus (&ifxusb_hcd.core_if)==1) return sprintf( buf, "1\n" ); + if(ifxusb_vbus (&ifxusb_hcd.core_if)==0) return sprintf( buf, "0\n" ); + return sprintf( buf, "UNKNOWN\n" ); + } + static void buspower_store(uint32_t value) + { + if (value==1) ifxusb_vbus_on (&ifxusb_hcd.core_if); + else if(value==0) ifxusb_vbus_off(&ifxusb_hcd.core_if); + } + static ssize_t procfs_buspower_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + return buspower_show(buf); + } + static ssize_t procfs_buspower_store(struct file *file, const char *buffer, unsigned long count, void *data) + { + char buf[10]; + int i = 0; + uint32_t value; + if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1)) + return -EFAULT; + value = simple_strtoul(buf, NULL, 16); + buspower_store(value); + return count; + } + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_buspower_show( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_buspower_show( struct device *_dev, char *buf) + #endif + { + return buspower_show(buf); + } + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_buspower_store( struct device *_dev, struct device_attribute *attr,const char *buffer, size_t count ) + #else + static ssize_t sysfs_buspower_store( struct device *_dev, const char *buffer, size_t count ) + #endif + { + char buf[10]; + int i = 0; + uint32_t value; + if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1)) + return -EFAULT; + value = simple_strtoul(buf, NULL, 16); + buspower_store(value); + return count; + } + DEVICE_ATTR(buspower, S_IRUGO|S_IWUSR, sysfs_buspower_show, sysfs_buspower_store); + #endif + +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// + + + #ifdef __IS_DUAL__ + static ssize_t bussuspend_show_1(char *buf) + { + hprt0_data_t val; + val.d32 = ifxusb_rreg(ifxusb_hcd_1.core_if.hprt0); + return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp); + } + static ssize_t bussuspend_show_2(char *buf) + { + hprt0_data_t val; + val.d32 = ifxusb_rreg(ifxusb_hcd_2.core_if.hprt0); + return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp); + } + + static ssize_t procfs_bussuspend_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + return bussuspend_show_1(buf); + } + static ssize_t procfs_bussuspend_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + return bussuspend_show_2(buf); + } + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_bussuspend_show_1( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_bussuspend_show_1( struct device *_dev,char *buf) + #endif + { + return bussuspend_show_1(buf); + } + DEVICE_ATTR(bussuspend_1, S_IRUGO|S_IWUSR, sysfs_bussuspend_show_1, 0); + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_bussuspend_show_2( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_bussuspend_show_2( struct device *_dev,char *buf) + #endif + { + return bussuspend_show_2(buf); + } + DEVICE_ATTR(bussuspend_2, S_IRUGO|S_IWUSR, sysfs_bussuspend_show_2, 0); + #else + static ssize_t bussuspend_show(char *buf) + { + hprt0_data_t val; + val.d32 = ifxusb_rreg(ifxusb_hcd.core_if.hprt0); + return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp); + } + static ssize_t procfs_bussuspend_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + return bussuspend_show(buf); + } + + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_bussuspend_show( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_bussuspend_show( struct device *_dev, char *buf) + #endif + { + return bussuspend_show(buf); + } + DEVICE_ATTR(bussuspend, S_IRUGO|S_IWUSR, sysfs_bussuspend_show, 0); + #endif + +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// + + #ifdef __IS_DUAL__ + static ssize_t busconnected_show_1(char *buf) + { + hprt0_data_t val; + val.d32 = ifxusb_rreg(ifxusb_hcd_1.core_if.hprt0); + return sprintf (buf, "Bus Connected = 0x%x\n", val.b.prtconnsts); + } + static ssize_t busconnected_show_2(char *buf) + { + hprt0_data_t val; + val.d32 = ifxusb_rreg(ifxusb_hcd_2.core_if.hprt0); + return sprintf (buf, "Bus Connected = 0x%x\n", val.b.prtconnsts); + } + + static ssize_t procfs_busconnected_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + return busconnected_show_1(buf); + } + static ssize_t procfs_busconnected_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + return busconnected_show_2(buf); + } + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_busconnected_show_1( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_busconnected_show_1( struct device *_dev,char *buf) + #endif + { + return busconnected_show_1(buf); + } + DEVICE_ATTR(busconnected_1, S_IRUGO|S_IWUSR, sysfs_busconnected_show_1, 0); + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_busconnected_show_2( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_busconnected_show_2( struct device *_dev,char *buf) + #endif + { + return busconnected_show_2(buf); + } + DEVICE_ATTR(busconnected_2, S_IRUGO|S_IWUSR, sysfs_busconnected_show_2, 0); + #else + static ssize_t busconnected_show(char *buf) + { + hprt0_data_t val; + val.d32 = ifxusb_rreg(ifxusb_hcd.core_if.hprt0); + return sprintf (buf, "Bus Connected = 0x%x\n", val.b.prtconnsts); + } + static ssize_t procfs_busconnected_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + return busconnected_show(buf); + } + + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_busconnected_show( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_busconnected_show( struct device *_dev, char *buf) + #endif + { + return busconnected_show(buf); + } + DEVICE_ATTR(busconnected, S_IRUGO|S_IWUSR, sysfs_busconnected_show, 0); + #endif + +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// + + #ifdef __IS_DUAL__ + static ssize_t connectspeed_show_1(char *buf) + { + hprt0_data_t val; + val.d32 = ifxusb_rreg(ifxusb_hcd_1.core_if.hprt0); + if( val.b.prtspd ==0) return sprintf (buf, "Bus Speed = High (%d)\n", val.b.prtspd); + if( val.b.prtspd ==1) return sprintf (buf, "Bus Speed = Full (%d)\n", val.b.prtspd); + if( val.b.prtspd ==2) return sprintf (buf, "Bus Speed = Low (%d)\n", val.b.prtspd); + return sprintf (buf, "Bus Speed = Unknown (%d)\n", val.b.prtspd); + } + static ssize_t connectspeed_show_2(char *buf) + { + hprt0_data_t val; + val.d32 = ifxusb_rreg(ifxusb_hcd_2.core_if.hprt0); + if( val.b.prtspd ==0) return sprintf (buf, "Bus Speed = High (%d)\n", val.b.prtspd); + if( val.b.prtspd ==1) return sprintf (buf, "Bus Speed = Full (%d)\n", val.b.prtspd); + if( val.b.prtspd ==2) return sprintf (buf, "Bus Speed = Low (%d)\n", val.b.prtspd); + return sprintf (buf, "Bus Speed = Unknown (%d)\n", val.b.prtspd); + } + + static ssize_t procfs_connectspeed_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + return connectspeed_show_1(buf); + } + static ssize_t procfs_connectspeed_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + return connectspeed_show_2(buf); + } + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_connectspeed_show_1( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_connectspeed_show_1( struct device *_dev,char *buf) + #endif + { + return connectspeed_show_1(buf); + } + DEVICE_ATTR(connectspeed_1, S_IRUGO|S_IWUSR, sysfs_connectspeed_show_1, 0); + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_connectspeed_show_2( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_connectspeed_show_2( struct device *_dev,char *buf) + #endif + { + return connectspeed_show_2(buf); + } + DEVICE_ATTR(connectspeed_2, S_IRUGO|S_IWUSR, sysfs_connectspeed_show_2, 0); + #else + static ssize_t connectspeed_show(char *buf) + { + hprt0_data_t val; + val.d32 = ifxusb_rreg(ifxusb_hcd.core_if.hprt0); + if( val.b.prtspd ==0) return sprintf (buf, "Bus Speed = High (%d)\n", val.b.prtspd); + if( val.b.prtspd ==1) return sprintf (buf, "Bus Speed = Full (%d)\n", val.b.prtspd); + if( val.b.prtspd ==2) return sprintf (buf, "Bus Speed = Low (%d)\n", val.b.prtspd); + return sprintf (buf, "Bus Speed = Unknown (%d)\n", val.b.prtspd); + } + + static ssize_t procfs_connectspeed_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + return connectspeed_show(buf); + } + + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_connectspeed_show( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_connectspeed_show( struct device *_dev, char *buf) + #endif + { + return connectspeed_show(buf); + } + DEVICE_ATTR(connectspeed, S_IRUGO|S_IWUSR, sysfs_connectspeed_show, 0); + #endif +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// +#endif + + +#ifdef __IS_DEVICE__ +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// + static ssize_t devspeed_show(char *buf) + { + dcfg_data_t val; + val.d32 = ifxusb_rreg(&ifxusb_pcd.core_if.dev_global_regs->dcfg); + if( val.b.devspd ==0) return sprintf (buf, "Dev Speed = High (%d)\n", val.b.devspd); + if( val.b.devspd ==1) return sprintf (buf, "Dev Speed = Full (%d)\n", val.b.devspd); + if( val.b.devspd ==3) return sprintf (buf, "Dev Speed = Full (%d)\n", val.b.devspd); + return sprintf (buf, "Dev Speed = Unknown (%d)\n", val.b.devspd); + } + + static ssize_t procfs_devspeed_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + return devspeed_show(buf); + } + + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_devspeed_show( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_devspeed_show( struct device *_dev, char *buf) + #endif + { + return devspeed_show(buf); + } + DEVICE_ATTR(devspeed, S_IRUGO|S_IWUSR, sysfs_devspeed_show, 0); + + static ssize_t enumspeed_show(char *buf) + { + dsts_data_t val; + val.d32 = ifxusb_rreg(&ifxusb_pcd.core_if.dev_global_regs->dsts); + if( val.b.enumspd ==0) return sprintf (buf, "Enum Speed = High (%d)\n", val.b.enumspd); + if( val.b.enumspd ==1) return sprintf (buf, "Enum Speed = Full (%d)\n", val.b.enumspd); + if( val.b.enumspd ==2) return sprintf (buf, "Enum Speed = Low (%d)\n", val.b.enumspd); + return sprintf (buf, "Enum Speed = invalid(%d)\n", val.b.enumspd); + } + + static ssize_t procfs_enumspeed_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + return enumspeed_show(buf); + } + + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_enumspeed_show( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_enumspeed_show( struct device *_dev, char *buf) + #endif + { + return enumspeed_show(buf); + } + DEVICE_ATTR(enumspeed, S_IRUGO|S_IWUSR, sysfs_enumspeed_show, 0); +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// +#endif + + +////////////////////////////////////////////////////////////////////////////////// +#ifdef __ENABLE_DUMP__ + + #ifdef __IS_DUAL__ + static void dump_reg_1(void) + { + ifxusb_dump_registers(&ifxusb_hcd_1.core_if); + } + static void dump_reg_2(void) + { + ifxusb_dump_registers(&ifxusb_hcd_2.core_if); + } + + static ssize_t procfs_dump_reg_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + dump_reg_1(); + return 0; + } + static ssize_t procfs_dump_reg_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + dump_reg_2(); + return 0; + } + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_dump_reg_show_1( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_dump_reg_show_1( struct device *_dev,char *buf) + #endif + { + dump_reg_1(); + return 0; + } + DEVICE_ATTR(dump_reg_1, S_IRUGO|S_IWUSR, sysfs_dump_reg_show_1, 0); + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_dump_reg_show_2( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_dump_reg_show_2( struct device *_dev,char *buf) + #endif + { + dump_reg_2(); + return 0; + } + DEVICE_ATTR(dump_reg_2, S_IRUGO|S_IWUSR, sysfs_dump_reg_show_2, 0); + #else + static void dump_reg(void) + { + #ifdef __IS_HOST__ + ifxusb_dump_registers(&ifxusb_hcd.core_if); + #endif + #ifdef __IS_DEVICE__ + ifxusb_dump_registers(&ifxusb_pcd.core_if); + #endif + } + static ssize_t procfs_dump_reg_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + dump_reg(); + return 0; + } + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_dump_reg_show( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_dump_reg_show( struct device *_dev,char *buf) + #endif + { + dump_reg(); + return 0; + } + DEVICE_ATTR(dump_reg, S_IRUGO|S_IWUSR, sysfs_dump_reg_show, 0); + #endif + + +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// + + #ifdef __IS_DUAL__ + static void dump_spram_1(void) + { + ifxusb_dump_spram(&ifxusb_hcd_1.core_if); + } + static void dump_spram_2(void) + { + ifxusb_dump_spram(&ifxusb_hcd_2.core_if); + } + + static ssize_t procfs_dump_spram_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + dump_spram_1(); + return 0; + } + static ssize_t procfs_dump_spram_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + dump_spram_2(); + return 0; + } + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_dump_spram_show_1( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_dump_spram_show_1( struct device *_dev,char *buf) + #endif + { + dump_spram_1(); + return 0; + } + DEVICE_ATTR(dump_spram_1, S_IRUGO|S_IWUSR, sysfs_dump_spram_show_1, 0); + + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_dump_spram_show_2( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_dump_spram_show_2( struct device *_dev,char *buf) + #endif + { + dump_spram_2(); + return 0; + } + DEVICE_ATTR(dump_spram_2, S_IRUGO|S_IWUSR, sysfs_dump_spram_show_2, 0); + #else + static void dump_spram(void) + { + #ifdef __IS_HOST__ + ifxusb_dump_spram(&ifxusb_hcd.core_if); + #endif + #ifdef __IS_DEVICE__ + ifxusb_dump_spram(&ifxusb_pcd.core_if); + #endif + } + static ssize_t procfs_dump_spram_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + dump_spram(); + return 0; + } + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_dump_spram_show( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_dump_spram_show( struct device *_dev,char *buf) + #endif + { + dump_spram(); + return 0; + } + DEVICE_ATTR(dump_spram, S_IRUGO|S_IWUSR, sysfs_dump_spram_show, 0); + #endif +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// + + #ifdef __IS_HOST__ + #ifdef __IS_DUAL__ + static ssize_t procfs_dump_host_state_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + ifxhcd_dump_state(&ifxusb_hcd_1); + return 0; + } + static ssize_t procfs_dump_host_state_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + ifxhcd_dump_state(&ifxusb_hcd_2); + return 0; + } + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_dump_host_state_show_1( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_dump_host_state_show_1( struct device *_dev,char *buf) + #endif + { + ifxhcd_dump_state(&ifxusb_hcd_1); + return 0; + } + DEVICE_ATTR(dump_host_state_1, S_IRUGO|S_IWUSR, sysfs_dump_host_state_show_1, 0); + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_dump_host_state_show_2( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_dump_host_state_show_2( struct device *_dev,char *buf) + #endif + { + ifxhcd_dump_state(&ifxusb_hcd_2); + return 0; + } + DEVICE_ATTR(dump_host_state_2, S_IRUGO|S_IWUSR, sysfs_dump_host_state_show_2, 0); + #else + static ssize_t procfs_dump_host_state_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) + { + ifxhcd_dump_state(&ifxusb_hcd); + return 0; + } + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + static ssize_t sysfs_dump_host_state_show( struct device *_dev, struct device_attribute *attr,char *buf) + #else + static ssize_t sysfs_dump_host_state_show( struct device *_dev,char *buf) + #endif + { + ifxhcd_dump_state(&ifxusb_hcd); + return 0; + } + DEVICE_ATTR(dump_host_state, S_IRUGO|S_IWUSR, sysfs_dump_host_state_show, 0); + #endif + +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// +///////////////////////////////////////////////////////////////////////////////////////////////////// + + #endif //IS_HOST_ + +#endif //__ENABLE_DUMP__ + +////////////////////////////////////////////////////////////////////////////////// + +static int ifx_proc_addproc(char *funcname, read_proc_t *hookfuncr, write_proc_t *hookfuncw); +static void ifx_proc_delproc(char *funcname); + +////////////////////////////////////////////////////////////////////////////////// + +/*! + \brief This function create the sysfs and procfs entries + \param[in] _dev Pointer of device structure, if applied + */ +void ifxusb_attr_create (void *_dev) +{ + int error; + + struct device *dev = (struct device *) _dev; + + IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); + error = ifx_proc_addproc("dbglevel", procfs_dbglevel_show, procfs_dbglevel_store); + error = device_create_file(dev, &dev_attr_dbglevel); + + #ifdef __IS_DUAL__ + error = ifx_proc_addproc("dump_params_1", procfs_dump_params_show_1, NULL); + error = ifx_proc_addproc("dump_params_2", procfs_dump_params_show_2, NULL); + error = device_create_file(dev, &dev_attr_dump_params_1); + error = device_create_file(dev, &dev_attr_dump_params_2); + #else + error = ifx_proc_addproc("dump_params", procfs_dump_params_show, NULL); + error = device_create_file(dev, &dev_attr_dump_params); + #endif + + #ifdef __IS_DUAL__ + error = ifx_proc_addproc("mode_1", procfs_mode_show_1, NULL); + error = ifx_proc_addproc("mode_2", procfs_mode_show_2, NULL); + error = device_create_file(dev, &dev_attr_mode_1); + error = device_create_file(dev, &dev_attr_mode_2); + #else + error = ifx_proc_addproc("mode", procfs_mode_show, NULL); + error = device_create_file(dev, &dev_attr_mode); + #endif + + #ifdef __IS_HOST__ + #ifdef __IS_DUAL__ + error = ifx_proc_addproc("buspower_1", procfs_buspower_show_1, procfs_buspower_store_1); + error = ifx_proc_addproc("buspower_2", procfs_buspower_show_2, procfs_buspower_store_2); + error = device_create_file(dev, &dev_attr_buspower_1); + error = device_create_file(dev, &dev_attr_buspower_2); + #else + error = ifx_proc_addproc("buspower", procfs_buspower_show, procfs_buspower_store); + error = device_create_file(dev, &dev_attr_buspower); + #endif + + #ifdef __IS_DUAL__ + error = ifx_proc_addproc("bussuspend_1", procfs_bussuspend_show_1, NULL); + error = ifx_proc_addproc("bussuspend_2", procfs_bussuspend_show_2, NULL); + error = device_create_file(dev, &dev_attr_bussuspend_1); + error = device_create_file(dev, &dev_attr_bussuspend_2); + #else + error = ifx_proc_addproc("bussuspend", procfs_bussuspend_show, NULL); + error = device_create_file(dev, &dev_attr_bussuspend); + #endif + + #ifdef __IS_DUAL__ + error = ifx_proc_addproc("busconnected_1", procfs_busconnected_show_1, NULL); + error = ifx_proc_addproc("busconnected_2", procfs_busconnected_show_2, NULL); + error = device_create_file(dev, &dev_attr_busconnected_1); + error = device_create_file(dev, &dev_attr_busconnected_2); + #else + error = ifx_proc_addproc("busconnected", procfs_busconnected_show, NULL); + error = device_create_file(dev, &dev_attr_busconnected); + #endif + + #ifdef __IS_DUAL__ + error = ifx_proc_addproc("connectspeed_1", procfs_connectspeed_show_1, NULL); + error = ifx_proc_addproc("connectspeed_2", procfs_connectspeed_show_2, NULL); + error = device_create_file(dev, &dev_attr_connectspeed_1); + error = device_create_file(dev, &dev_attr_connectspeed_2); + #else + error = ifx_proc_addproc("connectspeed", procfs_connectspeed_show, NULL); + error = device_create_file(dev, &dev_attr_connectspeed); + #endif + #endif + + #ifdef __IS_DEVICE__ + error = ifx_proc_addproc("devspeed", procfs_devspeed_show, NULL); + error = device_create_file(dev, &dev_attr_devspeed); + error = ifx_proc_addproc("enumspeed", procfs_enumspeed_show, NULL); + error = device_create_file(dev, &dev_attr_enumspeed); + #endif + + ////////////////////////////////////////////////////// + #ifdef __ENABLE_DUMP__ + #ifdef __IS_DUAL__ + error = ifx_proc_addproc("dump_reg_1", procfs_dump_reg_show_1, NULL); + error = ifx_proc_addproc("dump_reg_2", procfs_dump_reg_show_2, NULL); + error = device_create_file(dev, &dev_attr_dump_reg_1); + error = device_create_file(dev, &dev_attr_dump_reg_2); + #else + error = ifx_proc_addproc("dump_reg", procfs_dump_reg_show, NULL); + error = device_create_file(dev, &dev_attr_dump_reg); + #endif + + #ifdef __IS_DUAL__ + error = ifx_proc_addproc("dump_spram_1", procfs_dump_spram_show_1, NULL); + error = ifx_proc_addproc("dump_spram_2", procfs_dump_spram_show_2, NULL); + error = device_create_file(dev, &dev_attr_dump_spram_1); + error = device_create_file(dev, &dev_attr_dump_spram_2); + #else + error = ifx_proc_addproc("dump_spram", procfs_dump_spram_show, NULL); + error = device_create_file(dev, &dev_attr_dump_spram); + #endif + + #ifdef __IS_HOST__ + #ifdef __IS_DUAL__ + error = ifx_proc_addproc("dump_host_state_1", procfs_dump_host_state_show_1, NULL); + error = ifx_proc_addproc("dump_host_state_2", procfs_dump_host_state_show_2, NULL); + error = device_create_file(dev, &dev_attr_dump_host_state_1); + error = device_create_file(dev, &dev_attr_dump_host_state_2); + #else + error = ifx_proc_addproc("dump_host_state", procfs_dump_host_state_show, NULL); + error = device_create_file(dev, &dev_attr_dump_host_state); + #endif + #endif + #endif //__ENABLE_DUMP__ + ////////////////////////////////////////////////////// +} + + +/*! + \brief This function remove the sysfs and procfs entries + \param[in] _dev Pointer of device structure, if applied + */ +void ifxusb_attr_remove (void *_dev) +{ + struct device *dev = (struct device *) _dev; + + IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); + ifx_proc_delproc("dbglevel"); + device_remove_file(dev, &dev_attr_dbglevel); + + #ifdef __IS_DUAL__ + ifx_proc_delproc("dump_params_1"); + ifx_proc_delproc("dump_params_2"); + device_remove_file(dev, &dev_attr_dump_params_1); + device_remove_file(dev, &dev_attr_dump_params_2); + #else + ifx_proc_delproc("dump_params"); + device_remove_file(dev, &dev_attr_dump_params); + #endif + + #ifdef __IS_DUAL__ + ifx_proc_delproc("mode_1"); + ifx_proc_delproc("mode_2"); + device_remove_file(dev, &dev_attr_mode_1); + device_remove_file(dev, &dev_attr_mode_2); + #else + ifx_proc_delproc("mode"); + device_remove_file(dev, &dev_attr_mode); + #endif + + #ifdef __IS_HOST__ + #ifdef __IS_DUAL__ + ifx_proc_delproc("buspower_1"); + ifx_proc_delproc("buspower_2"); + device_remove_file(dev, &dev_attr_buspower_1); + device_remove_file(dev, &dev_attr_buspower_2); + #else + ifx_proc_delproc("buspower"); + device_remove_file(dev, &dev_attr_buspower); + #endif + + #ifdef __IS_DUAL__ + ifx_proc_delproc("bussuspend_1"); + ifx_proc_delproc("bussuspend_2"); + device_remove_file(dev, &dev_attr_bussuspend_1); + device_remove_file(dev, &dev_attr_bussuspend_2); + #else + ifx_proc_delproc("bussuspend"); + device_remove_file(dev, &dev_attr_bussuspend); + #endif + + #ifdef __IS_DUAL__ + ifx_proc_delproc("busconnected_1"); + ifx_proc_delproc("busconnected_2"); + device_remove_file(dev, &dev_attr_busconnected_1); + device_remove_file(dev, &dev_attr_busconnected_2); + #else + ifx_proc_delproc("busconnected"); + device_remove_file(dev, &dev_attr_busconnected); + #endif + + #ifdef __IS_DUAL__ + ifx_proc_delproc("connectspeed_1"); + ifx_proc_delproc("connectspeed_2"); + device_remove_file(dev, &dev_attr_connectspeed_1); + device_remove_file(dev, &dev_attr_connectspeed_2); + #else + ifx_proc_delproc("connectspeed"); + device_remove_file(dev, &dev_attr_connectspeed); + #endif + #endif + + #ifdef __IS_DEVICE__ + ifx_proc_delproc("devspeed"); + device_remove_file(dev, &dev_attr_devspeed); + ifx_proc_delproc("enumspeed"); + device_remove_file(dev, &dev_attr_enumspeed); + #endif + + #ifdef __ENABLE_DUMP__ + #ifdef __IS_DUAL__ + ifx_proc_delproc("dump_reg_1"); + ifx_proc_delproc("dump_reg_2"); + device_remove_file(dev, &dev_attr_dump_reg_1); + device_remove_file(dev, &dev_attr_dump_reg_2); + #else + ifx_proc_delproc("dump_reg"); + device_remove_file(dev, &dev_attr_dump_reg); + #endif + + #ifdef __IS_DUAL__ + ifx_proc_delproc("dump_spram_1"); + ifx_proc_delproc("dump_spram_2"); + device_remove_file(dev, &dev_attr_dump_spram_1); + device_remove_file(dev, &dev_attr_dump_spram_2); + #else + ifx_proc_delproc("dump_spram"); + device_remove_file(dev, &dev_attr_dump_spram); + #endif + + #ifdef __IS_HOST__ + #ifdef __IS_DUAL__ + ifx_proc_delproc("dump_host_state_1"); + ifx_proc_delproc("dump_host_state_2"); + device_remove_file(dev, &dev_attr_dump_host_state_1); + device_remove_file(dev, &dev_attr_dump_host_state_2); + #else + ifx_proc_delproc("dump_host_state"); + device_remove_file(dev, &dev_attr_dump_host_state); + #endif + #endif + #endif //__ENABLE_DUMP__ + /* AVM/WK fix: del IFXUSB root dir*/ + ifx_proc_delproc(NULL); +} + +static struct proc_dir_entry * proc_ifx_root = NULL; + +/* initialize the proc file system and make a dir named /proc/[name] */ +static void ifx_proc_init(void) +{ + IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); + proc_ifx_root = proc_mkdir(ifxusb_driver_name, (void *)0); + if (!proc_ifx_root){ + IFX_PRINT("%s proc initialization failed! \n", ifxusb_driver_name); + return; + } +} + +/* proc file system add function for debugging. */ +static int ifx_proc_addproc(char *funcname, read_proc_t *hookfuncr, write_proc_t *hookfuncw) +{ + struct proc_dir_entry *pe; + IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); + if (!proc_ifx_root) + ifx_proc_init(); + + if (hookfuncw == NULL) + { + pe = create_proc_read_entry(funcname, S_IRUGO, proc_ifx_root, hookfuncr, NULL); + if (!pe) + { + IFX_PRINT("ERROR in creating read proc entry (%s)! \n", funcname); + return -1; + } + } + else + { + pe = create_proc_entry(funcname, S_IRUGO | S_IWUGO, proc_ifx_root); + if (pe) + { + pe->read_proc = hookfuncr; + pe->write_proc = hookfuncw; + } + else + { + IFX_PRINT("ERROR in creating proc entry (%s)! \n", funcname); + return -1; + } + } + return 0; +} + + +/* proc file system del function for removing module. */ +static void ifx_proc_delproc(char *funcname) +{ +/* AVM/WK Fix*/ + if (funcname != NULL) { + remove_proc_entry(funcname, proc_ifx_root); + } else { + remove_proc_entry(ifxusb_driver_name, NULL); + proc_ifx_root = NULL; + } +} + +static void ifxusb_dump_params(ifxusb_core_if_t *_core_if) +{ + ifxusb_params_t *params=&_core_if->params; + + #ifdef __IS_HOST__ + IFX_PRINT("IFXUSB Dump Parameters ( Host Mode) \n"); + #endif //__IS_HOST__ + #ifdef __IS_DEVICE__ + IFX_PRINT("IFXUSB Dump Parameters ( Device Mode) \n"); + #endif //__IS_DEVICE__ + + #ifdef __DESC_DMA__ + IFX_PRINT("DMA: Hermes DMA\n"); + #else + IFX_PRINT("DMA: Non-Desc DMA\n"); + #endif + IFX_PRINT(" Burst size: %d\n",params->dma_burst_size); + + if (params->speed==1) + IFX_PRINT("Full Speed only\n"); + else if(params->speed==0) + IFX_PRINT("Full/Hign Speed\n"); + else + IFX_PRINT("Unkonwn setting (%d) for Speed\n",params->speed); + + IFX_PRINT("Total Data FIFO size: %d(0x%06X) DWord, %d(0x%06X) Bytes\n", + params->data_fifo_size,params->data_fifo_size, + params->data_fifo_size*4, params->data_fifo_size*4 + ); + + #ifdef __IS_DEVICE__ + IFX_PRINT("Rx FIFO size: %d(0x%06X) DWord, %d(0x%06X) Bytes\n", + params->rx_fifo_size,params->rx_fifo_size, + params->rx_fifo_size*4, params->rx_fifo_size*4 + ); + { + int i; + for(i=0;itx_fifo_size[i],params->tx_fifo_size[i], + params->tx_fifo_size[i]*4, params->tx_fifo_size[i]*4 + ); + } + } + #ifdef __DED_FIFO__ + IFX_PRINT("Treshold : %s Rx:%d Tx:%d \n", + (params->thr_ctl)?"On":"Off",params->tx_thr_length,params->rx_thr_length); + #endif + #else //__IS_HOST__ + IFX_PRINT("Host Channels: %d\n",params->host_channels); + + IFX_PRINT("Rx FIFO size: %d(0x%06X) DWord, %d(0x%06X) Bytes\n", + params->data_fifo_size,params->data_fifo_size, + params->data_fifo_size*4, params->data_fifo_size*4 + ); + + IFX_PRINT("NP Tx FIFO size: %d(0x%06X) DWord, %d(0x%06X) Bytes\n", + params->nperio_tx_fifo_size,params->nperio_tx_fifo_size, + params->nperio_tx_fifo_size*4, params->nperio_tx_fifo_size*4 + ); + + IFX_PRINT(" P Tx FIFO size: %d(0x%06X) DWord, %d(0x%06X) Bytes\n", + params->perio_tx_fifo_size,params->perio_tx_fifo_size, + params->perio_tx_fifo_size*4, params->perio_tx_fifo_size*4 + ); + #endif //__IS_HOST__ + + IFX_PRINT("Max Transfer size: %d(0x%06X) Bytes\n", + params->max_transfer_size,params->max_transfer_size + ); + IFX_PRINT("Max Packet Count: %d(0x%06X)\n", + params->max_packet_count,params->max_packet_count + ); + + IFX_PRINT("PHY UTMI Width: %d\n",params->phy_utmi_width); + + IFX_PRINT("Turn Around Time: HS:%d FS:%d\n",params->turn_around_time_hs,params->turn_around_time_fs); + IFX_PRINT("Timeout Calibration: HS:%d FS:%d\n",params->timeout_cal_hs,params->timeout_cal_fs); + + + IFX_PRINT("==================================================\n"); + IFX_PRINT("End of Parameters Dump\n"); + IFX_PRINT("==================================================\n"); +} + + diff --git a/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_driver.c b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_driver.c new file mode 100644 index 0000000000..23349059f4 --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_driver.c @@ -0,0 +1,970 @@ +/***************************************************************************** + ** FILE NAME : ifxusb_driver.c + ** PROJECT : IFX USB sub-system V3 + ** MODULES : IFX USB sub-system Host and Device driver + ** SRC VERSION : 1.0 + ** DATE : 1/Jan/2009 + ** AUTHOR : Chen, Howard + ** DESCRIPTION : The provides the initialization and cleanup entry + ** points for the IFX USB driver. This module can be + ** dynamically loaded with insmod command or built-in + ** with kernel. When loaded or executed the ifxusb_driver_init + ** function is called. When the module is removed (using rmmod), + ** the ifxusb_driver_cleanup function is called. + *****************************************************************************/ + +/*! + \file ifxusb_driver.c + \brief This file contains the loading/unloading interface to the Linux driver. +*/ + +#include +#include "ifxusb_version.h" + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include /* permission constants */ +#include +#include + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) + #include +#endif + +#include + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) + #include +#endif + +#include "ifxusb_plat.h" + +#include "ifxusb_cif.h" + +#ifdef __IS_HOST__ + #include "ifxhcd.h" + + #define USB_DRIVER_DESC "IFX USB HCD driver" + const char ifxusb_driver_name[] = "ifxusb_hcd"; + + #ifdef __IS_DUAL__ + ifxhcd_hcd_t ifxusb_hcd_1; + ifxhcd_hcd_t ifxusb_hcd_2; + const char ifxusb_hcd_name_1[] = "ifxusb_hcd_1"; + const char ifxusb_hcd_name_2[] = "ifxusb_hcd_2"; + #else + ifxhcd_hcd_t ifxusb_hcd; + const char ifxusb_hcd_name[] = "ifxusb_hcd"; + #endif + + #if defined(__DO_OC_INT__) + static unsigned int oc_int_installed=0; + static ifxhcd_hcd_t *oc_int_id=NULL; + #endif +#endif + +#ifdef __IS_DEVICE__ + #include "ifxpcd.h" + + #define USB_DRIVER_DESC "IFX USB PCD driver" + const char ifxusb_driver_name[] = "ifxusb_pcd"; + + ifxpcd_pcd_t ifxusb_pcd; + const char ifxusb_pcd_name[] = "ifxusb_pcd"; +#endif + +/* Global Debug Level Mask. */ +#ifdef __IS_HOST__ + uint32_t h_dbg_lvl = 0x00; +#endif + +#ifdef __IS_DEVICE__ + uint32_t d_dbg_lvl = 0x00; +#endif + +ifxusb_params_t ifxusb_module_params; + +static void parse_parms(void); + + +#include +#define IFX_USB0_IR (INT_NUM_IM1_IRL0 + 22) +#define IFX_USB1_IR (INT_NUM_IM2_IRL0 + 19) + +/*! + \brief This function is called when a driver is unregistered. This happens when + the rmmod command is executed. The device may or may not be electrically + present. If it is present, the driver stops device processing. Any resources + used on behalf of this device are freed. +*/ +static int ifxusb_driver_remove(struct platform_device *_dev) +{ + IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); + #ifdef __IS_HOST__ + #if defined(__DO_OC_INT__) + #if defined(__DO_OC_INT_ENABLE__) + ifxusb_oc_int_off(); + #endif + + if(oc_int_installed && oc_int_id) + free_irq((unsigned int)IFXUSB_OC_IRQ, oc_int_id ); + oc_int_installed=0; + oc_int_id=NULL; + #endif + + #if defined(__IS_DUAL__) + ifxhcd_remove(&ifxusb_hcd_1); + ifxusb_core_if_remove(&ifxusb_hcd_1.core_if ); + ifxhcd_remove(&ifxusb_hcd_2); + ifxusb_core_if_remove(&ifxusb_hcd_2.core_if ); + #else + ifxhcd_remove(&ifxusb_hcd); + ifxusb_core_if_remove(&ifxusb_hcd.core_if ); + #endif + #endif + + #ifdef __IS_DEVICE__ + ifxpcd_remove(); + ifxusb_core_if_remove(&ifxusb_pcd.core_if ); + #endif + + /* Remove the device attributes */ + + ifxusb_attr_remove(&_dev->dev); + + return 0; +} + + +/* Function to setup the structures to control one usb core running as host*/ +#ifdef __IS_HOST__ +/*! + \brief inlined by ifxusb_driver_probe(), handling host mode probing. Run at each host core. +*/ + static inline int ifxusb_driver_probe_h(ifxhcd_hcd_t *_hcd, + int _irq, + uint32_t _iobase, + uint32_t _fifomem, + uint32_t _fifodbg + ) + { + int retval = 0; + + IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); + +#ifdef __DEV_NEW__ + ifxusb_power_off (&_hcd->core_if); + ifxusb_phy_power_off (&_hcd->core_if); // Test + mdelay(500); +#endif //__DEV_NEW__ + ifxusb_power_on (&_hcd->core_if); + mdelay(50); + ifxusb_phy_power_on (&_hcd->core_if); // Test + mdelay(50); + ifxusb_hard_reset(&_hcd->core_if); + retval =ifxusb_core_if_init(&_hcd->core_if, + _irq, + _iobase, + _fifomem, + _fifodbg); + if(retval) + return retval; + + ifxusb_host_core_init(&_hcd->core_if,&ifxusb_module_params); + + ifxusb_disable_global_interrupts( &_hcd->core_if); + + /* The driver is now initialized and need to be registered into Linux USB sub-system */ + + retval = ifxhcd_init(_hcd); // hook the hcd into usb ss + + if (retval != 0) + { + IFX_ERROR("_hcd_init failed\n"); + return retval; + } + + //ifxusb_enable_global_interrupts( _hcd->core_if ); // this should be done at hcd_start , including hcd_interrupt + return 0; + } +#endif //__IS_HOST__ + +#ifdef __IS_DEVICE__ +/*! + \brief inlined by ifxusb_driver_probe(), handling device mode probing. +*/ + static inline int ifxusb_driver_probe_d(ifxpcd_pcd_t *_pcd, + int _irq, + uint32_t _iobase, + uint32_t _fifomem, + uint32_t _fifodbg + ) + { + int retval = 0; + + IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); +#ifdef __DEV_NEW__ + ifxusb_power_off (&_pcd->core_if); + ifxusb_phy_power_off (&_pcd->core_if); // Test + mdelay(500); +#endif // __DEV_NEW__ + ifxusb_power_on (&_pcd->core_if); + mdelay(50); + ifxusb_phy_power_on (&_pcd->core_if); // Test + mdelay(50); + ifxusb_hard_reset(&_pcd->core_if); + retval =ifxusb_core_if_init(&_pcd->core_if, + _irq, + _iobase, + _fifomem, + _fifodbg); + if(retval) + return retval; + + IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); + ifxusb_dev_core_init(&_pcd->core_if,&ifxusb_module_params); + + IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); + ifxusb_disable_global_interrupts( &_pcd->core_if); + + /* The driver is now initialized and need to be registered into + Linux USB Gadget sub-system + */ + retval = ifxpcd_init(); + IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); + + if (retval != 0) + { + IFX_ERROR("_pcd_init failed\n"); + return retval; + } + //ifxusb_enable_global_interrupts( _pcd->core_if ); // this should be done at gadget bind or start + return 0; + } +#endif //__IS_DEVICE__ + + + +/*! + \brief This function is called by module management in 2.6 kernel or by ifxusb_driver_init with 2.4 kernel + It is to probe and setup IFXUSB core(s). +*/ +static int ifxusb_driver_probe(struct platform_device *_dev) +{ + int retval = 0; + int *pins = _dev->dev.platform_data; + if (ltq_is_vr9()) { + gpio_request(6, "id1"); + gpio_request(9, "id2"); + gpio_direction_input(6); + gpio_direction_input(9); + } + if (pins) { + if (pins[0]) { + gpio_request(pins[0], "vbus1"); + gpio_direction_output(pins[0], 1); + } + if (pins[1] && ltq_is_vr9()) { + gpio_request(pins[1], "vbus2"); + gpio_direction_output(pins[1], 1); + } + } + // Parsing and store the parameters + IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); + parse_parms(); + + #ifdef __IS_HOST__ + #if defined(__IS_DUAL__) + memset(&ifxusb_hcd_1, 0, sizeof(ifxhcd_hcd_t)); + memset(&ifxusb_hcd_2, 0, sizeof(ifxhcd_hcd_t)); + + ifxusb_hcd_1.core_if.core_no=0; + ifxusb_hcd_2.core_if.core_no=1; + ifxusb_hcd_1.core_if.core_name=(char *)ifxusb_hcd_name_1; + ifxusb_hcd_2.core_if.core_name=(char *)ifxusb_hcd_name_2; + + ifxusb_hcd_1.dev=&_dev->dev; + ifxusb_hcd_2.dev=&_dev->dev; + + retval = ifxusb_driver_probe_h(&ifxusb_hcd_1, + IFX_USB0_IR, + IFXUSB1_IOMEM_BASE, + IFXUSB1_FIFOMEM_BASE, + IFXUSB1_FIFODBG_BASE + ); + if(retval) + goto ifxusb_driver_probe_fail; + + retval = ifxusb_driver_probe_h(&ifxusb_hcd_2, + IFX_USB1_IR, + IFXUSB2_IOMEM_BASE, + IFXUSB2_FIFOMEM_BASE, + IFXUSB2_FIFODBG_BASE + ); + if(retval) + goto ifxusb_driver_probe_fail; + + #elif defined(__IS_FIRST__) + memset(&ifxusb_hcd, 0, sizeof(ifxhcd_hcd_t)); + + ifxusb_hcd.core_if.core_no=0; + ifxusb_hcd.core_if.core_name=(char *)ifxusb_hcd_name; + + ifxusb_hcd.dev=&_dev->dev; + + retval = ifxusb_driver_probe_h(&ifxusb_hcd, + IFX_USB0_IR, + IFXUSB1_IOMEM_BASE, + IFXUSB1_FIFOMEM_BASE, + IFXUSB1_FIFODBG_BASE + ); + if(retval) + goto ifxusb_driver_probe_fail; + + #elif defined(__IS_SECOND__) + memset(&ifxusb_hcd, 0, sizeof(ifxhcd_hcd_t)); + + ifxusb_hcd.core_if.core_no=1; + ifxusb_hcd.core_if.core_name=(char *)ifxusb_hcd_name; + + ifxusb_hcd.dev=&_dev->dev; + + retval = ifxusb_driver_probe_h(&ifxusb_hcd, + IFX_USB1_IR, + IFXUSB2_IOMEM_BASE, + IFXUSB2_FIFOMEM_BASE, + IFXUSB2_FIFODBG_BASE + ); + if(retval) + goto ifxusb_driver_probe_fail; + + #else + memset(&ifxusb_hcd, 0, sizeof(ifxhcd_hcd_t)); + + ifxusb_hcd.core_if.core_no=0; + ifxusb_hcd.core_if.core_name=(char *)ifxusb_hcd_name; + + ifxusb_hcd.dev=&_dev->dev; + + retval = ifxusb_driver_probe_h(&ifxusb_hcd, + IFXUSB_IRQ, + IFXUSB_IOMEM_BASE, + IFXUSB_FIFOMEM_BASE, + IFXUSB_FIFODBG_BASE + ); + if(retval) + goto ifxusb_driver_probe_fail; + #endif + + #if defined(__DO_OC_INT__) + IFXUSB_DEBUGPL( DBG_CIL, "registering (overcurrent) handler for irq%d\n", IFXUSB_OC_IRQ); + #if defined(__IS_DUAL__) + request_irq((unsigned int)IFXUSB_OC_IRQ, &ifx_hcd_oc_irq, +// SA_INTERRUPT|SA_SHIRQ, "ifxusb_oc", (void *)&ifxusb_hcd_1); + IRQF_DISABLED | IRQF_SHARED, "ifxusb_oc", (void *)&ifxusb_hcd_1); + oc_int_id=&ifxusb_hcd_1; + #else + request_irq((unsigned int)IFXUSB_OC_IRQ, &ifx_hcd_oc_irq, +// SA_INTERRUPT|SA_SHIRQ, "ifxusb_oc", (void *)&ifxusb_hcd); + IRQF_DISABLED | IRQF_SHARED, "ifxusb_oc", (void *)&ifxusb_hcd); + oc_int_id=&ifxusb_hcd; + #endif + oc_int_installed=1; + + #if defined(__DO_OC_INT_ENABLE__) + ifxusb_oc_int_on(); + #endif + #endif + + #endif + + #ifdef __IS_DEVICE__ + memset(&ifxusb_pcd, 0, sizeof(ifxpcd_pcd_t)); + ifxusb_pcd.core_if.core_name=(char *)&ifxusb_pcd_name[0]; + + ifxusb_pcd.dev=&_dev->dev; + + #if defined(__IS_FIRST__) + ifxusb_pcd.core_if.core_no=0; + retval = ifxusb_driver_probe_d(&ifxusb_pcd, + IFXUSB1_IRQ, + IFXUSB1_IOMEM_BASE, + IFXUSB1_FIFOMEM_BASE, + IFXUSB1_FIFODBG_BASE + ); + #elif defined(__IS_SECOND__) + ifxusb_pcd.core_if.core_no=1; + retval = ifxusb_driver_probe_d(&ifxusb_pcd, + IFXUSB2_IRQ, + IFXUSB2_IOMEM_BASE, + IFXUSB2_FIFOMEM_BASE, + IFXUSB2_FIFODBG_BASE + ); + #else + ifxusb_pcd.core_if.core_no=0; + retval = ifxusb_driver_probe_d(&ifxusb_pcd, + IFXUSB_IRQ, + IFXUSB_IOMEM_BASE, + IFXUSB_FIFOMEM_BASE, + IFXUSB_FIFODBG_BASE + ); + #endif + if(retval) + goto ifxusb_driver_probe_fail; + #endif + + ifxusb_attr_create(&_dev->dev); + + return 0; + +ifxusb_driver_probe_fail: + ifxusb_driver_remove(_dev); + return retval; +} + + + +/*! + \brief This function is called when the ifxusb_driver is installed with the insmod command. +*/ + + +static struct platform_driver ifxusb_driver = { + .driver = { + .name = ifxusb_driver_name, + .owner = THIS_MODULE, + }, + .probe = ifxusb_driver_probe, + .remove = ifxusb_driver_remove, +}; + +int __init ifxusb_driver_init(void) +{ + int retval = 0; + + IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); + IFX_PRINT("%s: version %s\n", ifxusb_driver_name, IFXUSB_VERSION); + + retval = platform_driver_register(&ifxusb_driver); + + if (retval < 0) { + IFX_ERROR("%s retval=%d\n", __func__, retval); + return retval; + } + return retval; +} + +#if 0 // 2.4 + int __init ifxusb_driver_init(void) + { + int retval = 0; + IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); + IFX_PRINT("%s: version %s\n", ifxusb_driver_name, IFXUSB_VERSION); + retval = ifxusb_driver_probe(); + + if (retval < 0) { + IFX_ERROR("%s retval=%d\n", __func__, retval); + return retval; + } + + return retval; + } +#endif + +module_init(ifxusb_driver_init); + + +/*! + \brief This function is called when the driver is removed from the kernel + with the rmmod command. The driver unregisters itself with its bus + driver. +*/ + +void __exit ifxusb_driver_cleanup(void) +{ + IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); + + platform_driver_unregister(&ifxusb_driver); + + IFX_PRINT("%s module removed\n", ifxusb_driver_name); +} +#if 0 + void __exit ifxusb_driver_cleanup(void) + { + IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); + ifxusb_driver_remove(); + IFX_PRINT("%s module removed\n", ifxusb_driver_name); + } +#endif +module_exit(ifxusb_driver_cleanup); + + + +MODULE_DESCRIPTION(USB_DRIVER_DESC); +MODULE_AUTHOR("Infineon"); +MODULE_LICENSE("GPL"); + + + +// Parameters set when loaded +//static long dbg_lvl =0xFFFFFFFF; +static long dbg_lvl =0; +static short dma_burst_size =-1; +static short speed =-1; +static long data_fifo_size =-1; +#ifdef __IS_DEVICE__ + static long rx_fifo_size =-1; + #ifdef __DED_FIFO__ + static long tx_fifo_size_00 =-1; + static long tx_fifo_size_01 =-1; + static long tx_fifo_size_02 =-1; + static long tx_fifo_size_03 =-1; + static long tx_fifo_size_04 =-1; + static long tx_fifo_size_05 =-1; + static long tx_fifo_size_06 =-1; + static long tx_fifo_size_07 =-1; + static long tx_fifo_size_08 =-1; + static long tx_fifo_size_09 =-1; + static long tx_fifo_size_10 =-1; + static long tx_fifo_size_11 =-1; + static long tx_fifo_size_12 =-1; + static long tx_fifo_size_13 =-1; + static long tx_fifo_size_14 =-1; + static long tx_fifo_size_15 =-1; + static short thr_ctl=-1; + static long tx_thr_length =-1; + static long rx_thr_length =-1; + #else + static long nperio_tx_fifo_size =-1; + static long perio_tx_fifo_size_01 =-1; + static long perio_tx_fifo_size_02 =-1; + static long perio_tx_fifo_size_03 =-1; + static long perio_tx_fifo_size_04 =-1; + static long perio_tx_fifo_size_05 =-1; + static long perio_tx_fifo_size_06 =-1; + static long perio_tx_fifo_size_07 =-1; + static long perio_tx_fifo_size_08 =-1; + static long perio_tx_fifo_size_09 =-1; + static long perio_tx_fifo_size_10 =-1; + static long perio_tx_fifo_size_11 =-1; + static long perio_tx_fifo_size_12 =-1; + static long perio_tx_fifo_size_13 =-1; + static long perio_tx_fifo_size_14 =-1; + static long perio_tx_fifo_size_15 =-1; + #endif + static short dev_endpoints =-1; +#endif + +#ifdef __IS_HOST__ + static long rx_fifo_size =-1; + static long nperio_tx_fifo_size =-1; + static long perio_tx_fifo_size =-1; + static short host_channels =-1; +#endif + +static long max_transfer_size =-1; +static long max_packet_count =-1; +static long phy_utmi_width =-1; +static long turn_around_time_hs =-1; +static long turn_around_time_fs =-1; +static long timeout_cal_hs =-1; +static long timeout_cal_fs =-1; + +/*! + \brief Parsing the parameters taken when module load +*/ +static void parse_parms(void) +{ + + IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); + #ifdef __IS_HOST__ + h_dbg_lvl=dbg_lvl; + #endif + #ifdef __IS_DEVICE__ + d_dbg_lvl=dbg_lvl; + #endif + + switch(dma_burst_size) + { + case 0: + case 1: + case 4: + case 8: + case 16: + ifxusb_module_params.dma_burst_size=dma_burst_size; + break; + default: + ifxusb_module_params.dma_burst_size=default_param_dma_burst_size; + } + + if(speed==0 || speed==1) + ifxusb_module_params.speed=speed; + else + ifxusb_module_params.speed=default_param_speed; + + if(max_transfer_size>=2048 && max_transfer_size<=65535) + ifxusb_module_params.max_transfer_size=max_transfer_size; + else + ifxusb_module_params.max_transfer_size=default_param_max_transfer_size; + + if(max_packet_count>=15 && max_packet_count<=511) + ifxusb_module_params.max_packet_count=max_packet_count; + else + ifxusb_module_params.max_packet_count=default_param_max_packet_count; + + switch(phy_utmi_width) + { + case 8: + case 16: + ifxusb_module_params.phy_utmi_width=phy_utmi_width; + break; + default: + ifxusb_module_params.phy_utmi_width=default_param_phy_utmi_width; + } + + if(turn_around_time_hs>=0 && turn_around_time_hs<=7) + ifxusb_module_params.turn_around_time_hs=turn_around_time_hs; + else + ifxusb_module_params.turn_around_time_hs=default_param_turn_around_time_hs; + + if(turn_around_time_fs>=0 && turn_around_time_fs<=7) + ifxusb_module_params.turn_around_time_fs=turn_around_time_fs; + else + ifxusb_module_params.turn_around_time_fs=default_param_turn_around_time_fs; + + if(timeout_cal_hs>=0 && timeout_cal_hs<=7) + ifxusb_module_params.timeout_cal_hs=timeout_cal_hs; + else + ifxusb_module_params.timeout_cal_hs=default_param_timeout_cal_hs; + + if(timeout_cal_fs>=0 && timeout_cal_fs<=7) + ifxusb_module_params.timeout_cal_fs=timeout_cal_fs; + else + ifxusb_module_params.timeout_cal_fs=default_param_timeout_cal_fs; + + if(data_fifo_size>=32 && data_fifo_size<=32768) + ifxusb_module_params.data_fifo_size=data_fifo_size; + else + ifxusb_module_params.data_fifo_size=default_param_data_fifo_size; + + #ifdef __IS_HOST__ + if(host_channels>=1 && host_channels<=16) + ifxusb_module_params.host_channels=host_channels; + else + ifxusb_module_params.host_channels=default_param_host_channels; + + if(rx_fifo_size>=16 && rx_fifo_size<=32768) + ifxusb_module_params.rx_fifo_size=rx_fifo_size; + else + ifxusb_module_params.rx_fifo_size=default_param_rx_fifo_size; + + if(nperio_tx_fifo_size>=16 && nperio_tx_fifo_size<=32768) + ifxusb_module_params.nperio_tx_fifo_size=nperio_tx_fifo_size; + else + ifxusb_module_params.nperio_tx_fifo_size=default_param_nperio_tx_fifo_size; + + if(perio_tx_fifo_size>=16 && perio_tx_fifo_size<=32768) + ifxusb_module_params.perio_tx_fifo_size=perio_tx_fifo_size; + else + ifxusb_module_params.perio_tx_fifo_size=default_param_perio_tx_fifo_size; + #endif //__IS_HOST__ + + #ifdef __IS_DEVICE__ + if(rx_fifo_size>=16 && rx_fifo_size<=32768) + ifxusb_module_params.rx_fifo_size=rx_fifo_size; + else + ifxusb_module_params.rx_fifo_size=default_param_rx_fifo_size; + #ifdef __DED_FIFO__ + if(tx_fifo_size_00>=16 && tx_fifo_size_00<=32768) + ifxusb_module_params.tx_fifo_size[ 0]=tx_fifo_size_00; + else + ifxusb_module_params.tx_fifo_size[ 0]=default_param_tx_fifo_size_00; + if(tx_fifo_size_01>=0 && tx_fifo_size_01<=32768) + ifxusb_module_params.tx_fifo_size[ 1]=tx_fifo_size_01; + else + ifxusb_module_params.tx_fifo_size[ 1]=default_param_tx_fifo_size_01; + if(tx_fifo_size_02>=0 && tx_fifo_size_02<=32768) + ifxusb_module_params.tx_fifo_size[ 2]=tx_fifo_size_02; + else + ifxusb_module_params.tx_fifo_size[ 2]=default_param_tx_fifo_size_02; + if(tx_fifo_size_03>=0 && tx_fifo_size_03<=32768) + ifxusb_module_params.tx_fifo_size[ 3]=tx_fifo_size_03; + else + ifxusb_module_params.tx_fifo_size[ 3]=default_param_tx_fifo_size_03; + if(tx_fifo_size_04>=0 && tx_fifo_size_04<=32768) + ifxusb_module_params.tx_fifo_size[ 4]=tx_fifo_size_04; + else + ifxusb_module_params.tx_fifo_size[ 4]=default_param_tx_fifo_size_04; + if(tx_fifo_size_05>=0 && tx_fifo_size_05<=32768) + ifxusb_module_params.tx_fifo_size[ 5]=tx_fifo_size_05; + else + ifxusb_module_params.tx_fifo_size[ 5]=default_param_tx_fifo_size_05; + if(tx_fifo_size_06>=0 && tx_fifo_size_06<=32768) + ifxusb_module_params.tx_fifo_size[ 6]=tx_fifo_size_06; + else + ifxusb_module_params.tx_fifo_size[ 6]=default_param_tx_fifo_size_06; + if(tx_fifo_size_07>=0 && tx_fifo_size_07<=32768) + ifxusb_module_params.tx_fifo_size[ 7]=tx_fifo_size_07; + else + ifxusb_module_params.tx_fifo_size[ 7]=default_param_tx_fifo_size_07; + if(tx_fifo_size_08>=0 && tx_fifo_size_08<=32768) + ifxusb_module_params.tx_fifo_size[ 8]=tx_fifo_size_08; + else + ifxusb_module_params.tx_fifo_size[ 8]=default_param_tx_fifo_size_08; + if(tx_fifo_size_09>=0 && tx_fifo_size_09<=32768) + ifxusb_module_params.tx_fifo_size[ 9]=tx_fifo_size_09; + else + ifxusb_module_params.tx_fifo_size[ 9]=default_param_tx_fifo_size_09; + if(tx_fifo_size_10>=0 && tx_fifo_size_10<=32768) + ifxusb_module_params.tx_fifo_size[10]=tx_fifo_size_10; + else + ifxusb_module_params.tx_fifo_size[10]=default_param_tx_fifo_size_10; + if(tx_fifo_size_11>=0 && tx_fifo_size_11<=32768) + ifxusb_module_params.tx_fifo_size[11]=tx_fifo_size_11; + else + ifxusb_module_params.tx_fifo_size[11]=default_param_tx_fifo_size_11; + if(tx_fifo_size_12>=0 && tx_fifo_size_12<=32768) + ifxusb_module_params.tx_fifo_size[12]=tx_fifo_size_12; + else + ifxusb_module_params.tx_fifo_size[12]=default_param_tx_fifo_size_12; + if(tx_fifo_size_13>=0 && tx_fifo_size_13<=32768) + ifxusb_module_params.tx_fifo_size[13]=tx_fifo_size_13; + else + ifxusb_module_params.tx_fifo_size[13]=default_param_tx_fifo_size_13; + if(tx_fifo_size_14>=0 && tx_fifo_size_14<=32768) + ifxusb_module_params.tx_fifo_size[14]=tx_fifo_size_14; + else + ifxusb_module_params.tx_fifo_size[14]=default_param_tx_fifo_size_14; + if(tx_fifo_size_15>=0 && tx_fifo_size_15<=32768) + ifxusb_module_params.tx_fifo_size[15]=tx_fifo_size_15; + else + ifxusb_module_params.tx_fifo_size[15]=default_param_tx_fifo_size_15; + if(thr_ctl==0 || thr_ctl==1) + ifxusb_module_params.thr_ctl=thr_ctl; + else + ifxusb_module_params.thr_ctl=default_param_thr_ctl; + if(tx_thr_length>=16 && tx_thr_length<=511) + ifxusb_module_params.tx_thr_length=tx_thr_length; + else + ifxusb_module_params.tx_thr_length=default_param_tx_thr_length; + if(rx_thr_length>=16 && rx_thr_length<=511) + ifxusb_module_params.rx_thr_length=rx_thr_length; + else + ifxusb_module_params.rx_thr_length=default_param_rx_thr_length; + #else //__DED_FIFO__ + if(nperio_tx_fifo_size>=16 && nperio_tx_fifo_size<=32768) + ifxusb_module_params.tx_fifo_size[ 0]=nperio_tx_fifo_size; + else + ifxusb_module_params.tx_fifo_size[ 0]=default_param_nperio_tx_fifo_size; + if(perio_tx_fifo_size_01>=0 && perio_tx_fifo_size_01<=32768) + ifxusb_module_params.tx_fifo_size[ 1]=perio_tx_fifo_size_01; + else + ifxusb_module_params.tx_fifo_size[ 1]=default_param_perio_tx_fifo_size_01; + if(perio_tx_fifo_size_02>=0 && perio_tx_fifo_size_02<=32768) + ifxusb_module_params.tx_fifo_size[ 2]=perio_tx_fifo_size_02; + else + ifxusb_module_params.tx_fifo_size[ 2]=default_param_perio_tx_fifo_size_02; + if(perio_tx_fifo_size_03>=0 && perio_tx_fifo_size_03<=32768) + ifxusb_module_params.tx_fifo_size[ 3]=perio_tx_fifo_size_03; + else + ifxusb_module_params.tx_fifo_size[ 3]=default_param_perio_tx_fifo_size_03; + if(perio_tx_fifo_size_04>=0 && perio_tx_fifo_size_04<=32768) + ifxusb_module_params.tx_fifo_size[ 4]=perio_tx_fifo_size_04; + else + ifxusb_module_params.tx_fifo_size[ 4]=default_param_perio_tx_fifo_size_04; + if(perio_tx_fifo_size_05>=0 && perio_tx_fifo_size_05<=32768) + ifxusb_module_params.tx_fifo_size[ 5]=perio_tx_fifo_size_05; + else + ifxusb_module_params.tx_fifo_size[ 5]=default_param_perio_tx_fifo_size_05; + if(perio_tx_fifo_size_06>=0 && perio_tx_fifo_size_06<=32768) + ifxusb_module_params.tx_fifo_size[ 6]=perio_tx_fifo_size_06; + else + ifxusb_module_params.tx_fifo_size[ 6]=default_param_perio_tx_fifo_size_06; + if(perio_tx_fifo_size_07>=0 && perio_tx_fifo_size_07<=32768) + ifxusb_module_params.tx_fifo_size[ 7]=perio_tx_fifo_size_07; + else + ifxusb_module_params.tx_fifo_size[ 7]=default_param_perio_tx_fifo_size_07; + if(perio_tx_fifo_size_08>=0 && perio_tx_fifo_size_08<=32768) + ifxusb_module_params.tx_fifo_size[ 8]=perio_tx_fifo_size_08; + else + ifxusb_module_params.tx_fifo_size[ 8]=default_param_perio_tx_fifo_size_08; + if(perio_tx_fifo_size_09>=0 && perio_tx_fifo_size_09<=32768) + ifxusb_module_params.tx_fifo_size[ 9]=perio_tx_fifo_size_09; + else + ifxusb_module_params.tx_fifo_size[ 9]=default_param_perio_tx_fifo_size_09; + if(perio_tx_fifo_size_10>=0 && perio_tx_fifo_size_10<=32768) + ifxusb_module_params.tx_fifo_size[10]=perio_tx_fifo_size_10; + else + ifxusb_module_params.tx_fifo_size[10]=default_param_perio_tx_fifo_size_10; + if(perio_tx_fifo_size_11>=0 && perio_tx_fifo_size_11<=32768) + ifxusb_module_params.tx_fifo_size[11]=perio_tx_fifo_size_11; + else + ifxusb_module_params.tx_fifo_size[11]=default_param_perio_tx_fifo_size_11; + if(perio_tx_fifo_size_12>=0 && perio_tx_fifo_size_12<=32768) + ifxusb_module_params.tx_fifo_size[12]=perio_tx_fifo_size_12; + else + ifxusb_module_params.tx_fifo_size[12]=default_param_perio_tx_fifo_size_12; + if(perio_tx_fifo_size_13>=0 && perio_tx_fifo_size_13<=32768) + ifxusb_module_params.tx_fifo_size[13]=perio_tx_fifo_size_13; + else + ifxusb_module_params.tx_fifo_size[13]=default_param_perio_tx_fifo_size_13; + if(perio_tx_fifo_size_14>=0 && perio_tx_fifo_size_14<=32768) + ifxusb_module_params.tx_fifo_size[14]=perio_tx_fifo_size_14; + else + ifxusb_module_params.tx_fifo_size[14]=default_param_perio_tx_fifo_size_14; + if(perio_tx_fifo_size_15>=0 && perio_tx_fifo_size_15<=32768) + ifxusb_module_params.tx_fifo_size[15]=perio_tx_fifo_size_15; + else + ifxusb_module_params.tx_fifo_size[15]=default_param_perio_tx_fifo_size_15; + #endif //__DED_FIFO__ + #endif //__IS_DEVICE__ +} + + + + + + + +module_param(dbg_lvl, long, 0444); +MODULE_PARM_DESC(dbg_lvl, "Debug level."); + +module_param(dma_burst_size, short, 0444); +MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 0, 1, 4, 8, 16"); + +module_param(speed, short, 0444); +MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed"); + +module_param(data_fifo_size, long, 0444); +MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768"); + +#ifdef __IS_DEVICE__ + module_param(rx_fifo_size, long, 0444); + MODULE_PARM_DESC(rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); + + #ifdef __DED_FIFO__ + module_param(tx_fifo_size_00, long, 0444); + MODULE_PARM_DESC(tx_fifo_size_00, "Number of words in the Tx FIFO #00 16-32768"); + module_param(tx_fifo_size_01, long, 0444); + MODULE_PARM_DESC(tx_fifo_size_01, "Number of words in the Tx FIFO #01 0-32768"); + module_param(tx_fifo_size_02, long, 0444); + MODULE_PARM_DESC(tx_fifo_size_02, "Number of words in the Tx FIFO #02 0-32768"); + module_param(tx_fifo_size_03, long, 0444); + MODULE_PARM_DESC(tx_fifo_size_03, "Number of words in the Tx FIFO #03 0-32768"); + module_param(tx_fifo_size_04, long, 0444); + MODULE_PARM_DESC(tx_fifo_size_04, "Number of words in the Tx FIFO #04 0-32768"); + module_param(tx_fifo_size_05, long, 0444); + MODULE_PARM_DESC(tx_fifo_size_05, "Number of words in the Tx FIFO #05 0-32768"); + module_param(tx_fifo_size_06, long, 0444); + MODULE_PARM_DESC(tx_fifo_size_06, "Number of words in the Tx FIFO #06 0-32768"); + module_param(tx_fifo_size_07, long, 0444); + MODULE_PARM_DESC(tx_fifo_size_07, "Number of words in the Tx FIFO #07 0-32768"); + module_param(tx_fifo_size_08, long, 0444); + MODULE_PARM_DESC(tx_fifo_size_08, "Number of words in the Tx FIFO #08 0-32768"); + module_param(tx_fifo_size_09, long, 0444); + MODULE_PARM_DESC(tx_fifo_size_09, "Number of words in the Tx FIFO #09 0-32768"); + module_param(tx_fifo_size_10, long, 0444); + MODULE_PARM_DESC(tx_fifo_size_10, "Number of words in the Tx FIFO #10 0-32768"); + module_param(tx_fifo_size_11, long, 0444); + MODULE_PARM_DESC(tx_fifo_size_11, "Number of words in the Tx FIFO #11 0-32768"); + module_param(tx_fifo_size_12, long, 0444); + MODULE_PARM_DESC(tx_fifo_size_12, "Number of words in the Tx FIFO #12 0-32768"); + module_param(tx_fifo_size_13, long, 0444); + MODULE_PARM_DESC(tx_fifo_size_13, "Number of words in the Tx FIFO #13 0-32768"); + module_param(tx_fifo_size_14, long, 0444); + MODULE_PARM_DESC(tx_fifo_size_14, "Number of words in the Tx FIFO #14 0-32768"); + module_param(tx_fifo_size_15, long, 0444); + MODULE_PARM_DESC(tx_fifo_size_15, "Number of words in the Tx FIFO #15 0-32768"); + + module_param(thr_ctl, short, 0444); + MODULE_PARM_DESC(thr_ctl, "0=Without 1=With Theshold Ctrl"); + + module_param(tx_thr_length, long, 0444); + MODULE_PARM_DESC(tx_thr_length, "TX Threshold length"); + + module_param(rx_thr_length, long, 0444); + MODULE_PARM_DESC(rx_thr_length, "RX Threshold length"); + + #else + module_param(nperio_tx_fifo_size, long, 0444); + MODULE_PARM_DESC(nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768"); + + module_param(perio_tx_fifo_size_01, long, 0444); + MODULE_PARM_DESC(perio_tx_fifo_size_01, "Number of words in the periodic Tx FIFO #01 0-32768"); + module_param(perio_tx_fifo_size_02, long, 0444); + MODULE_PARM_DESC(perio_tx_fifo_size_02, "Number of words in the periodic Tx FIFO #02 0-32768"); + module_param(perio_tx_fifo_size_03, long, 0444); + MODULE_PARM_DESC(perio_tx_fifo_size_03, "Number of words in the periodic Tx FIFO #03 0-32768"); + module_param(perio_tx_fifo_size_04, long, 0444); + MODULE_PARM_DESC(perio_tx_fifo_size_04, "Number of words in the periodic Tx FIFO #04 0-32768"); + module_param(perio_tx_fifo_size_05, long, 0444); + MODULE_PARM_DESC(perio_tx_fifo_size_05, "Number of words in the periodic Tx FIFO #05 0-32768"); + module_param(perio_tx_fifo_size_06, long, 0444); + MODULE_PARM_DESC(perio_tx_fifo_size_06, "Number of words in the periodic Tx FIFO #06 0-32768"); + module_param(perio_tx_fifo_size_07, long, 0444); + MODULE_PARM_DESC(perio_tx_fifo_size_07, "Number of words in the periodic Tx FIFO #07 0-32768"); + module_param(perio_tx_fifo_size_08, long, 0444); + MODULE_PARM_DESC(perio_tx_fifo_size_08, "Number of words in the periodic Tx FIFO #08 0-32768"); + module_param(perio_tx_fifo_size_09, long, 0444); + MODULE_PARM_DESC(perio_tx_fifo_size_09, "Number of words in the periodic Tx FIFO #09 0-32768"); + module_param(perio_tx_fifo_size_10, long, 0444); + MODULE_PARM_DESC(perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO #10 0-32768"); + module_param(perio_tx_fifo_size_11, long, 0444); + MODULE_PARM_DESC(perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO #11 0-32768"); + module_param(perio_tx_fifo_size_12, long, 0444); + MODULE_PARM_DESC(perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO #12 0-32768"); + module_param(perio_tx_fifo_size_13, long, 0444); + MODULE_PARM_DESC(perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO #13 0-32768"); + module_param(perio_tx_fifo_size_14, long, 0444); + MODULE_PARM_DESC(perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO #14 0-32768"); + module_param(perio_tx_fifo_size_15, long, 0444); + MODULE_PARM_DESC(perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO #15 0-32768"); + #endif//__DED_FIFO__ + module_param(dev_endpoints, short, 0444); + MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15"); +#endif + +#ifdef __IS_HOST__ + module_param(rx_fifo_size, long, 0444); + MODULE_PARM_DESC(rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); + + module_param(nperio_tx_fifo_size, long, 0444); + MODULE_PARM_DESC(nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768"); + + module_param(perio_tx_fifo_size, long, 0444); + MODULE_PARM_DESC(perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768"); + + module_param(host_channels, short, 0444); + MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16"); +#endif + +module_param(max_transfer_size, long, 0444); +MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535"); + +module_param(max_packet_count, long, 0444); +MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511"); + +module_param(phy_utmi_width, long, 0444); +MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits"); + +module_param(turn_around_time_hs, long, 0444); +MODULE_PARM_DESC(turn_around_time_hs, "Turn-Around time for HS"); + +module_param(turn_around_time_fs, long, 0444); +MODULE_PARM_DESC(turn_around_time_fs, "Turn-Around time for FS"); + +module_param(timeout_cal_hs, long, 0444); +MODULE_PARM_DESC(timeout_cal_hs, "Timeout Cal for HS"); + +module_param(timeout_cal_fs, long, 0444); +MODULE_PARM_DESC(timeout_cal_fs, "Timeout Cal for FS"); + + diff --git a/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_plat.h b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_plat.h new file mode 100644 index 0000000000..a50294fdcf --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_plat.h @@ -0,0 +1,1018 @@ +/***************************************************************************** + ** FILE NAME : ifxusb_plat.h + ** PROJECT : IFX USB sub-system V3 + ** MODULES : IFX USB sub-system Host and Device driver + ** SRC VERSION : 1.0 + ** DATE : 1/Jan/2009 + ** AUTHOR : Chen, Howard + ** DESCRIPTION : This file contains the Platform Specific constants, interfaces + ** (functions and macros). + ** FUNCTIONS : + ** COMPILER : gcc + ** REFERENCE : IFX hardware ref handbook for each plateforms + ** COPYRIGHT : + ** Version Control Section ** + ** $Author$ + ** $Date$ + ** $Revisions$ + ** $Log$ Revision history + *****************************************************************************/ + + +/*! + \defgroup IFXUSB_PLATEFORM_DEFINITION Platform Specific constants, interfaces (functions and macros). + \ingroup IFXUSB_DRIVER_V3 + \brief Maintain plateform specific definitions and macros in this file. + Each plateform has its own definition zone. + */ + +/*! + \defgroup IFXUSB_PLATEFORM_MEM_ADDR Definition of memory address and size and default parameters + \ingroup IFXUSB_PLATEFORM_DEFINITION + */ + +/*! + \defgroup IFXUSB_DBG_ROUTINE Routines for debug message + \ingroup IFXUSB_PLATEFORM_DEFINITION + */ + + +/*! \file ifxusb_plat.h + \ingroup IFXUSB_DRIVER_V3 + \brief This file contains the Platform Specific constants, interfaces (functions and macros). +*/ + +#if !defined(__IFXUSB_PLAT_H__) +#define __IFXUSB_PLAT_H__ + + +#include +#include +#include +#include +#include + + +#define IFXUSB_IOMEM_SIZE 0x00001000 +#define IFXUSB_FIFOMEM_SIZE 0x00010000 +#define IFXUSB_FIFODBG_SIZE 0x00020000 + + + +/*! + \addtogroup IFXUSB_PLATEFORM_MEM_ADDR + */ +/*@{*/ +#if defined(__UEIP__) + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) +// #define IFXUSB_IRQ 54 + #define IFXUSB_IOMEM_BASE 0x1e101000 + #define IFXUSB_FIFOMEM_BASE 0x1e120000 + #define IFXUSB_FIFODBG_BASE 0x1e140000 +// #define IFXUSB_OC_IRQ 151 + + #ifndef DANUBE_RCU_BASE_ADDR + #define DANUBE_RCU_BASE_ADDR (0xBF203000) + #endif + + #ifndef DANUBE_CGU + #define DANUBE_CGU (0xBF103000) + #endif + #ifndef DANUBE_CGU_IFCCR + #define DANUBE_CGU_IFCCR ((volatile unsigned long *)(DANUBE_CGU+ 0x0018)) + #endif + #ifndef DANUBE_PMU + #define DANUBE_PMU (KSEG1+0x1F102000) + #endif + #ifndef DANUBE_PMU_PWDCR + #define DANUBE_PMU_PWDCR ((volatile unsigned long *)(DANUBE_PMU+0x001C)) + #endif + + #ifndef DANUBE_GPIO_P0_OUT + #define DANUBE_GPIO_P0_OUT (0xBF103000+0x10) + #define DANUBE_GPIO_P0_DIR (0xBF103000+0x18) + #define DANUBE_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) + #define DANUBE_GPIO_P0_ALTSEL1 (0xBF103000+0x20) + #define DANUBE_GPIO_P0_OD (0xBF103000+0x24) + #define DANUBE_GPIO_P0_PUDSEL (0xBF103000+0x2C) + #define DANUBE_GPIO_P0_PUDEN (0xBF103000+0x30) + #define DANUBE_GPIO_P1_OUT (0xBF103000+0x40) + #define DANUBE_GPIO_P1_DIR (0xBF103000+0x48) + #define DANUBE_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) + #define DANUBE_GPIO_P1_ALTSEL1 (0xBF103000+0x50) + #define DANUBE_GPIO_P1_OD (0xBF103000+0x54) + #define DANUBE_GPIO_P1_PUDSEL (0xBF103000+0x5C) + #define DANUBE_GPIO_P1_PUDEN (0xBF103000+0x60) + #endif + + #define DANUBE_RCU_USBCFG ((volatile unsigned long *)(DANUBE_RCU_BASE_ADDR + 0x18)) + #define DANUBE_RCU_RESET ((volatile unsigned long *)(DANUBE_RCU_BASE_ADDR + 0x10)) + #define DANUBE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device + #define DANUBE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end + #define DANUBE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end + + #define default_param_dma_burst_size 4 + + #define default_param_speed IFXUSB_PARAM_SPEED_HIGH + + #define default_param_max_transfer_size -1 //(Max, hwcfg) + #define default_param_max_packet_count -1 //(Max, hwcfg) + #define default_param_phy_utmi_width 16 + + #define default_param_turn_around_time_hs 4 + #define default_param_turn_around_time_fs 4 + #define default_param_timeout_cal_hs -1 //(NoChange) + #define default_param_timeout_cal_fs -1 //(NoChange) + + #define default_param_data_fifo_size -1 //(Max, hwcfg) + + #ifdef __IS_HOST__ + #define default_param_host_channels -1 //(Max, hwcfg) + #define default_param_rx_fifo_size 640 + #define default_param_nperio_tx_fifo_size 640 + #define default_param_perio_tx_fifo_size 768 + #endif //__IS_HOST__ + + #ifdef __IS_DEVICE__ + #ifdef __DED_INTR__ + #define default_param_rx_fifo_size 1024 + #define default_param_nperio_tx_fifo_size 1016 + #define default_param_perio_tx_fifo_size_01 8 + #else + #define default_param_rx_fifo_size 1024 + #define default_param_nperio_tx_fifo_size 1024 + #define default_param_perio_tx_fifo_size_01 0 + #endif + #define default_param_perio_tx_fifo_size_02 0 + #define default_param_perio_tx_fifo_size_03 0 + #define default_param_perio_tx_fifo_size_04 0 + #define default_param_perio_tx_fifo_size_05 0 + #define default_param_perio_tx_fifo_size_06 0 + #define default_param_perio_tx_fifo_size_07 0 + #define default_param_perio_tx_fifo_size_08 0 + #define default_param_perio_tx_fifo_size_09 0 + #define default_param_perio_tx_fifo_size_10 0 + #define default_param_perio_tx_fifo_size_11 0 + #define default_param_perio_tx_fifo_size_12 0 + #define default_param_perio_tx_fifo_size_13 0 + #define default_param_perio_tx_fifo_size_14 0 + #define default_param_perio_tx_fifo_size_15 0 + #endif //__IS_DEVICE__ + + #elif defined(__IS_AMAZON_SE__) + //#include + //#include + +// #define IFXUSB_IRQ 31 + #define IFXUSB_IOMEM_BASE 0x1e101000 + #define IFXUSB_FIFOMEM_BASE 0x1e120000 + #define IFXUSB_FIFODBG_BASE 0x1e140000 +// #define IFXUSB_OC_IRQ 20 + + #ifndef AMAZON_SE_RCU_BASE_ADDR + #define AMAZON_SE_RCU_BASE_ADDR (0xBF203000) + #endif + #define AMAZON_SE_RCU_USBCFG ((volatile unsigned long *)(AMAZON_SE_RCU_BASE_ADDR + 0x18)) + #define AMAZON_SE_RCU_RESET ((volatile unsigned long *)(AMAZON_SE_RCU_BASE_ADDR + 0x10)) + #define AMAZON_SE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device + #define AMAZON_SE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end + #define AMAZON_SE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end + + #ifndef AMAZON_SE_GPIO_P0_OUT + #define AMAZON_SE_GPIO_P0_OUT (0xBF103000+0x10) + #define AMAZON_SE_GPIO_P0_DIR (0xBF103000+0x18) + #define AMAZON_SE_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) + #define AMAZON_SE_GPIO_P0_ALTSEL1 (0xBF103000+0x20) + #define AMAZON_SE_GPIO_P0_OD (0xBF103000+0x24) + #define AMAZON_SE_GPIO_P0_PUDSEL (0xBF103000+0x2C) + #define AMAZON_SE_GPIO_P0_PUDEN (0xBF103000+0x30) + #define AMAZON_SE_GPIO_P1_OUT (0xBF103000+0x40) + #define AMAZON_SE_GPIO_P1_DIR (0xBF103000+0x48) + #define AMAZON_SE_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) + #define AMAZON_SE_GPIO_P1_ALTSEL1 (0xBF103000+0x50) + #define AMAZON_SE_GPIO_P1_OD (0xBF103000+0x54) + #define AMAZON_SE_GPIO_P1_PUDSEL (0xBF103000+0x5C) + #define AMAZON_SE_GPIO_P1_PUDEN (0xBF103000+0x60) + #endif + + #ifndef AMAZON_SE_CGU + #define AMAZON_SE_CGU (0xBF103000) + #endif + #ifndef AMAZON_SE_CGU_IFCCR + #define AMAZON_SE_CGU_IFCCR ((volatile unsigned long *)(AMAZON_SE_CGU+ 0x0018)) + #endif + #ifndef AMAZON_SE_PMU + #define AMAZON_SE_PMU (KSEG1+0x1F102000) + #endif + #ifndef AMAZON_SE_PMU_PWDCR + #define AMAZON_SE_PMU_PWDCR ((volatile unsigned long *)(AMAZON_SE_PMU+0x001C)) + #endif + + #define default_param_dma_burst_size 4 + + #define default_param_speed IFXUSB_PARAM_SPEED_HIGH + + #define default_param_max_transfer_size -1 //(Max, hwcfg) + #define default_param_max_packet_count -1 //(Max, hwcfg) + #define default_param_phy_utmi_width 16 + + #define default_param_turn_around_time_hs 4 //(NoChange) + #define default_param_turn_around_time_fs 4 //(NoChange) + #define default_param_timeout_cal_hs -1 //(NoChange) + #define default_param_timeout_cal_fs -1 //(NoChange) + + #define default_param_data_fifo_size -1 //(Max, hwcfg) + + #ifdef __IS_HOST__ + #define default_param_host_channels -1 //(Max, hwcfg) + #define default_param_rx_fifo_size 240 + #define default_param_nperio_tx_fifo_size 240 + #define default_param_perio_tx_fifo_size 32 + #endif //__IS_HOST__ + #ifdef __IS_DEVICE__ + #ifdef __DED_INTR__ + #define default_param_rx_fifo_size 256 + #define default_param_nperio_tx_fifo_size 248 + #define default_param_perio_tx_fifo_size_01 8 + #else + #define default_param_rx_fifo_size 256 + #define default_param_nperio_tx_fifo_size 256 + #define default_param_perio_tx_fifo_size_01 0 + #endif + #define default_param_perio_tx_fifo_size_02 0 + #define default_param_perio_tx_fifo_size_03 0 + #define default_param_perio_tx_fifo_size_04 0 + #define default_param_perio_tx_fifo_size_05 0 + #define default_param_perio_tx_fifo_size_06 0 + #define default_param_perio_tx_fifo_size_07 0 + #define default_param_perio_tx_fifo_size_08 0 + #define default_param_perio_tx_fifo_size_09 0 + #define default_param_perio_tx_fifo_size_10 0 + #define default_param_perio_tx_fifo_size_11 0 + #define default_param_perio_tx_fifo_size_12 0 + #define default_param_perio_tx_fifo_size_13 0 + #define default_param_perio_tx_fifo_size_14 0 + #define default_param_perio_tx_fifo_size_15 0 + #endif //__IS_DEVICE__ + + #elif defined(__IS_AR9__) +// #define IFXUSB1_IRQ 54 + #define IFXUSB1_IOMEM_BASE 0x1E101000 + #define IFXUSB1_FIFOMEM_BASE 0x1E120000 + #define IFXUSB1_FIFODBG_BASE 0x1E140000 + +// #define IFXUSB2_IRQ 83 + #define IFXUSB2_IOMEM_BASE 0x1E106000 + #define IFXUSB2_FIFOMEM_BASE 0x1E1E0000 + #define IFXUSB2_FIFODBG_BASE 0x1E1C0000 + +// #define IFXUSB_OC_IRQ 60 + + #ifndef AR9_RCU_BASE_ADDR + #define AR9_RCU_BASE_ADDR (0xBF203000) + #endif + + #ifndef AR9_CGU + #define AR9_CGU (0xBF103000) + #endif + #ifndef AR9_CGU_IFCCR + #define AR9_CGU_IFCCR ((volatile unsigned long *)(AR9_CGU+ 0x0018)) + #endif + + #ifndef AR9_PMU + #define AR9_PMU (KSEG1+0x1F102000) + #endif + #ifndef AR9_PMU_PWDCR + #define AR9_PMU_PWDCR ((volatile unsigned long *)(AR9_PMU+0x001C)) + #endif + + #ifndef AR9_GPIO_P0_OUT + #define AR9_GPIO_P0_OUT (0xBF103000+0x10) + #define AR9_GPIO_P0_DIR (0xBF103000+0x18) + #define AR9_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) + #define AR9_GPIO_P0_ALTSEL1 (0xBF103000+0x20) + #define AR9_GPIO_P0_OD (0xBF103000+0x24) + #define AR9_GPIO_P0_PUDSEL (0xBF103000+0x2C) + #define AR9_GPIO_P0_PUDEN (0xBF103000+0x30) + #define AR9_GPIO_P1_OUT (0xBF103000+0x40) + #define AR9_GPIO_P1_DIR (0xBF103000+0x48) + #define AR9_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) + #define AR9_GPIO_P1_ALTSEL1 (0xBF103000+0x50) + #define AR9_GPIO_P1_OD (0xBF103000+0x54) + #define AR9_GPIO_P1_PUDSEL (0xBF103000+0x5C) + #define AR9_GPIO_P1_PUDEN (0xBF103000+0x60) + #endif + + #define AR9_RCU_USB1CFG ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x18)) + #define AR9_RCU_USB2CFG ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x34)) + #define AR9_RCU_USBRESET ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x10)) + #define AR9_USBCFG_ARB 7 // + #define AR9_USBCFG_HDSEL_BIT 11 // 0:host, 1:device + #define AR9_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end + #define AR9_USBCFG_SLV_END_BIT 17 // 0:little_end, 1:big_end + + #define default_param_dma_burst_size 4 + + #define default_param_speed IFXUSB_PARAM_SPEED_HIGH + + #define default_param_max_transfer_size -1 //(Max, hwcfg) + #define default_param_max_packet_count -1 //(Max, hwcfg) + #define default_param_phy_utmi_width 16 + + #define default_param_turn_around_time_hs 4 //(NoChange) + #define default_param_turn_around_time_fs 4 //(NoChange) + #define default_param_timeout_cal_hs -1 //(NoChange) + #define default_param_timeout_cal_fs -1 //(NoChange) + + #define default_param_data_fifo_size -1 //(Max, hwcfg) + + #ifdef __IS_HOST__ + #define default_param_host_channels -1 //(Max, hwcfg) + #define default_param_rx_fifo_size 240 + #define default_param_nperio_tx_fifo_size 240 + #define default_param_perio_tx_fifo_size 32 + #endif //__IS_HOST__ + #ifdef __IS_DEVICE__ + #ifdef __DED_INTR__ + #define default_param_rx_fifo_size 256 +// #define default_param_nperio_tx_fifo_size 248 +// #define default_param_perio_tx_fifo_size_01 8 + #define default_param_nperio_tx_fifo_size 252 + #define default_param_perio_tx_fifo_size_01 4 + #else + #define default_param_rx_fifo_size 256 + #define default_param_nperio_tx_fifo_size 256 + #define default_param_perio_tx_fifo_size_01 0 + #endif + #define default_param_perio_tx_fifo_size_02 0 + #define default_param_perio_tx_fifo_size_03 0 + #define default_param_perio_tx_fifo_size_04 0 + #define default_param_perio_tx_fifo_size_05 0 + #define default_param_perio_tx_fifo_size_06 0 + #define default_param_perio_tx_fifo_size_07 0 + #define default_param_perio_tx_fifo_size_08 0 + #define default_param_perio_tx_fifo_size_09 0 + #define default_param_perio_tx_fifo_size_10 0 + #define default_param_perio_tx_fifo_size_11 0 + #define default_param_perio_tx_fifo_size_12 0 + #define default_param_perio_tx_fifo_size_13 0 + #define default_param_perio_tx_fifo_size_14 0 + #define default_param_perio_tx_fifo_size_15 0 + #endif //__IS_DEVICE__ + + #elif defined(__IS_VR9__) +// #define IFXUSB1_IRQ 54 + #define IFXUSB1_IOMEM_BASE 0x1E101000 + #define IFXUSB1_FIFOMEM_BASE 0x1E120000 + #define IFXUSB1_FIFODBG_BASE 0x1E140000 + +// #define IFXUSB2_IRQ 83 + #define IFXUSB2_IOMEM_BASE 0x1E106000 + #define IFXUSB2_FIFOMEM_BASE 0x1E1E0000 + #define IFXUSB2_FIFODBG_BASE 0x1E1C0000 +// #define IFXUSB_OC_IRQ 60 + + #ifndef VR9_RCU_BASE_ADDR + #define VR9_RCU_BASE_ADDR (0xBF203000) + #endif + + #ifndef VR9_CGU + #define VR9_CGU (0xBF103000) + #endif + #ifndef VR9_CGU_IFCCR + #define VR9_CGU_IFCCR ((volatile unsigned long *)(VR9_CGU+ 0x0018)) + #endif + + #ifndef VR9_PMU + #define VR9_PMU (KSEG1+0x1F102000) + #endif + #ifndef VR9_PMU_PWDCR + #define VR9_PMU_PWDCR ((volatile unsigned long *)(VR9_PMU+0x001C)) + #endif + + #ifndef VR9_GPIO_P0_OUT + #define VR9_GPIO_P0_OUT (0xBF103000+0x10) + #define VR9_GPIO_P0_DIR (0xBF103000+0x18) + #define VR9_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) + #define VR9_GPIO_P0_ALTSEL1 (0xBF103000+0x20) + #define VR9_GPIO_P0_OD (0xBF103000+0x24) + #define VR9_GPIO_P0_PUDSEL (0xBF103000+0x2C) + #define VR9_GPIO_P0_PUDEN (0xBF103000+0x30) + #define VR9_GPIO_P1_OUT (0xBF103000+0x40) + #define VR9_GPIO_P1_DIR (0xBF103000+0x48) + #define VR9_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) + #define VR9_GPIO_P1_ALTSEL1 (0xBF103000+0x50) + #define VR9_GPIO_P1_OD (0xBF103000+0x54) + #define VR9_GPIO_P1_PUDSEL (0xBF103000+0x5C) + #define VR9_GPIO_P1_PUDEN (0xBF103000+0x60) + #endif + + #define VR9_RCU_USB1CFG ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x18)) + #define VR9_RCU_USB2CFG ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x34)) + #define VR9_RCU_USB_ANA_CFG1A ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x38)) + #define VR9_RCU_USB_ANA_CFG1B ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x3C)) + #define VR9_RCU_USBRESET ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x10)) + #define VR9_RCU_USBRESET2 ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x48)) + #define VR9_USBCFG_ARB 7 // + #define VR9_USBCFG_HDSEL_BIT 11 // 0:host, 1:device + #define VR9_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end + #define VR9_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end + + /*== AVM/BC 20101220 Workaround VR9 DMA burst size == + * Using 2 Devices in diferent ports cause a general USB Host Error. + * Workaround found in UGW4.3 + */ +// #define default_param_dma_burst_size 4 //(ALL) + //WA for AHB + #define default_param_dma_burst_size 0 //(ALL) + + #define default_param_speed IFXUSB_PARAM_SPEED_HIGH + + #define default_param_max_transfer_size -1 //(Max, hwcfg) + #define default_param_max_packet_count -1 //(Max, hwcfg) + #define default_param_phy_utmi_width 16 + + #define default_param_turn_around_time_hs 6 //(NoChange) snpsid >= 0x4f54260a + #define default_param_turn_around_time_fs 6 //(NoChange) snpsid >= 0x4f54260a + #define default_param_timeout_cal_hs -1 //(NoChange) + #define default_param_timeout_cal_fs -1 //(NoChange) + + #define default_param_data_fifo_size -1 //(Max, hwcfg) + + #ifdef __IS_HOST__ + #define default_param_host_channels -1 //(Max, hwcfg) + #define default_param_rx_fifo_size 240 + #define default_param_nperio_tx_fifo_size 240 + #define default_param_perio_tx_fifo_size 32 + #endif //__IS_HOST__ + #ifdef __IS_DEVICE__ +#if 0 + #define default_param_rx_fifo_size 256 + #define default_param_tx_fifo_size_00 -1 + #define default_param_tx_fifo_size_01 -1 + #define default_param_tx_fifo_size_02 -1 +#else + #define default_param_rx_fifo_size 256 + #define default_param_tx_fifo_size_00 32 + #define default_param_tx_fifo_size_01 200 + #define default_param_tx_fifo_size_02 8 +#endif + #define default_param_tx_fifo_size_03 -1 + #define default_param_tx_fifo_size_04 -1 + #define default_param_tx_fifo_size_05 -1 + #define default_param_tx_fifo_size_06 -1 + #define default_param_tx_fifo_size_07 -1 + #define default_param_tx_fifo_size_08 -1 + #define default_param_tx_fifo_size_09 -1 + #define default_param_tx_fifo_size_10 -1 + #define default_param_tx_fifo_size_11 -1 + #define default_param_tx_fifo_size_12 -1 + #define default_param_tx_fifo_size_13 -1 + #define default_param_tx_fifo_size_14 -1 + #define default_param_tx_fifo_size_15 -1 + #define default_param_dma_unalgned_tx -1 + #define default_param_dma_unalgned_rx -1 + #define default_param_thr_ctl -1 + #define default_param_tx_thr_length -1 + #define default_param_rx_thr_length -1 + #endif //__IS_DEVICE__ + #else // __IS_VR9__ + #error "Please choose one platform!!" + #endif // __IS_VR9__ + +#else //UEIP + #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) +// #define IFXUSB_IRQ 54 + #define IFXUSB_IOMEM_BASE 0x1e101000 + #define IFXUSB_FIFOMEM_BASE 0x1e120000 + #define IFXUSB_FIFODBG_BASE 0x1e140000 +// #define IFXUSB_OC_IRQ 151 + + + #ifndef DANUBE_RCU_BASE_ADDR + #define DANUBE_RCU_BASE_ADDR (0xBF203000) + #endif + + #ifndef DANUBE_CGU + #define DANUBE_CGU (0xBF103000) + #endif + #ifndef DANUBE_CGU_IFCCR + #define DANUBE_CGU_IFCCR ((volatile unsigned long *)(DANUBE_CGU+ 0x0018)) + #endif + #ifndef DANUBE_PMU + #define DANUBE_PMU (KSEG1+0x1F102000) + #endif + #ifndef DANUBE_PMU_PWDCR + #define DANUBE_PMU_PWDCR ((volatile unsigned long *)(DANUBE_PMU+0x001C)) + #endif + + #ifndef DANUBE_GPIO_P0_OUT + #define DANUBE_GPIO_P0_OUT (0xBF103000+0x10) + #define DANUBE_GPIO_P0_DIR (0xBF103000+0x18) + #define DANUBE_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) + #define DANUBE_GPIO_P0_ALTSEL1 (0xBF103000+0x20) + #define DANUBE_GPIO_P0_OD (0xBF103000+0x24) + #define DANUBE_GPIO_P0_PUDSEL (0xBF103000+0x2C) + #define DANUBE_GPIO_P0_PUDEN (0xBF103000+0x30) + #define DANUBE_GPIO_P1_OUT (0xBF103000+0x40) + #define DANUBE_GPIO_P1_DIR (0xBF103000+0x48) + #define DANUBE_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) + #define DANUBE_GPIO_P1_ALTSEL1 (0xBF103000+0x50) + #define DANUBE_GPIO_P1_OD (0xBF103000+0x54) + #define DANUBE_GPIO_P1_PUDSEL (0xBF103000+0x5C) + #define DANUBE_GPIO_P1_PUDEN (0xBF103000+0x60) + #endif + + + #define DANUBE_RCU_USBCFG ((volatile unsigned long *)(DANUBE_RCU_BASE_ADDR + 0x18)) + #define DANUBE_RCU_RESET ((volatile unsigned long *)(DANUBE_RCU_BASE_ADDR + 0x10)) + #define DANUBE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device + #define DANUBE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end + #define DANUBE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end + + #define default_param_dma_burst_size 4 + + #define default_param_speed IFXUSB_PARAM_SPEED_HIGH + + #define default_param_max_transfer_size -1 //(Max, hwcfg) + #define default_param_max_packet_count -1 //(Max, hwcfg) + #define default_param_phy_utmi_width 16 + + #define default_param_turn_around_time_hs 4 //(NoChange) + #define default_param_turn_around_time_fs 4 //(NoChange) + #define default_param_timeout_cal_hs -1 //(NoChange) + #define default_param_timeout_cal_fs -1 //(NoChange) + + #define default_param_data_fifo_size -1 //(Max, hwcfg) + #ifdef __IS_HOST__ + #define default_param_host_channels -1 //(Max, hwcfg) + #define default_param_rx_fifo_size 640 + #define default_param_nperio_tx_fifo_size 640 + #define default_param_perio_tx_fifo_size 768 + #endif //__IS_HOST__ + + #ifdef __IS_DEVICE__ + #ifdef __DED_INTR__ + #define default_param_rx_fifo_size 1024 + #define default_param_nperio_tx_fifo_size 1016 + #define default_param_perio_tx_fifo_size_01 8 + #else + #define default_param_rx_fifo_size 1024 + #define default_param_nperio_tx_fifo_size 1024 + #define default_param_perio_tx_fifo_size_01 0 + #endif + #define default_param_perio_tx_fifo_size_02 0 + #define default_param_perio_tx_fifo_size_03 0 + #define default_param_perio_tx_fifo_size_04 0 + #define default_param_perio_tx_fifo_size_05 0 + #define default_param_perio_tx_fifo_size_06 0 + #define default_param_perio_tx_fifo_size_07 0 + #define default_param_perio_tx_fifo_size_08 0 + #define default_param_perio_tx_fifo_size_09 0 + #define default_param_perio_tx_fifo_size_10 0 + #define default_param_perio_tx_fifo_size_11 0 + #define default_param_perio_tx_fifo_size_12 0 + #define default_param_perio_tx_fifo_size_13 0 + #define default_param_perio_tx_fifo_size_14 0 + #define default_param_perio_tx_fifo_size_15 0 + #endif //__IS_DEVICE__ + + #elif defined(__IS_AMAZON_SE__) + #include + //#include + +// #define IFXUSB_IRQ 31 + #define IFXUSB_IOMEM_BASE 0x1e101000 + #define IFXUSB_FIFOMEM_BASE 0x1e120000 + #define IFXUSB_FIFODBG_BASE 0x1e140000 +// #define IFXUSB_OC_IRQ 20 + + #define AMAZON_SE_RCU_USBCFG ((volatile unsigned long *)(AMAZON_SE_RCU_BASE_ADDR + 0x18)) + #define AMAZON_SE_RCU_RESET ((volatile unsigned long *)(AMAZON_SE_RCU_BASE_ADDR + 0x10)) + #define AMAZON_SE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device + #define AMAZON_SE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end + #define AMAZON_SE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end + + #ifndef AMAZON_SE_GPIO_P0_OUT + #define AMAZON_SE_GPIO_P0_OUT (0xBF103000+0x10) + #define AMAZON_SE_GPIO_P0_DIR (0xBF103000+0x18) + #define AMAZON_SE_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) + #define AMAZON_SE_GPIO_P0_ALTSEL1 (0xBF103000+0x20) + #define AMAZON_SE_GPIO_P0_OD (0xBF103000+0x24) + #define AMAZON_SE_GPIO_P0_PUDSEL (0xBF103000+0x2C) + #define AMAZON_SE_GPIO_P0_PUDEN (0xBF103000+0x30) + #define AMAZON_SE_GPIO_P1_OUT (0xBF103000+0x40) + #define AMAZON_SE_GPIO_P1_DIR (0xBF103000+0x48) + #define AMAZON_SE_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) + #define AMAZON_SE_GPIO_P1_ALTSEL1 (0xBF103000+0x50) + #define AMAZON_SE_GPIO_P1_OD (0xBF103000+0x54) + #define AMAZON_SE_GPIO_P1_PUDSEL (0xBF103000+0x5C) + #define AMAZON_SE_GPIO_P1_PUDEN (0xBF103000+0x60) + #endif + + + #ifndef AMAZON_SE_CGU + #define AMAZON_SE_CGU (0xBF103000) + #endif + #ifndef AMAZON_SE_CGU_IFCCR + #define AMAZON_SE_CGU_IFCCR ((volatile unsigned long *)(AMAZON_SE_CGU+ 0x0018)) + #endif + #ifndef AMAZON_SE_PMU + #define AMAZON_SE_PMU (KSEG1+0x1F102000) + #endif + #ifndef AMAZON_SE_PMU_PWDCR + #define AMAZON_SE_PMU_PWDCR ((volatile unsigned long *)(AMAZON_SE_PMU+0x001C)) + #endif + + #define default_param_dma_burst_size 4 + + #define default_param_speed IFXUSB_PARAM_SPEED_HIGH + + #define default_param_max_transfer_size -1 //(Max, hwcfg) + #define default_param_max_packet_count -1 //(Max, hwcfg) + #define default_param_phy_utmi_width 16 + + #define default_param_turn_around_time_hs 4 //(NoChange) + #define default_param_turn_around_time_fs 4 //(NoChange) + #define default_param_timeout_cal_hs -1 //(NoChange) + #define default_param_timeout_cal_fs -1 //(NoChange) + + #define default_param_data_fifo_size -1 //(Max, hwcfg) + + #ifdef __IS_HOST__ + #define default_param_host_channels -1 //(Max, hwcfg) + #define default_param_rx_fifo_size 240 + #define default_param_nperio_tx_fifo_size 240 + #define default_param_perio_tx_fifo_size 32 + #endif //__IS_HOST__ + #ifdef __IS_DEVICE__ + #ifdef __DED_INTR__ + #define default_param_rx_fifo_size 256 + #define default_param_nperio_tx_fifo_size 248 + #define default_param_perio_tx_fifo_size_01 8 + #else + #define default_param_rx_fifo_size 256 + #define default_param_nperio_tx_fifo_size 256 + #define default_param_perio_tx_fifo_size_01 0 + #endif + #define default_param_perio_tx_fifo_size_02 0 + #define default_param_perio_tx_fifo_size_03 0 + #define default_param_perio_tx_fifo_size_04 0 + #define default_param_perio_tx_fifo_size_05 0 + #define default_param_perio_tx_fifo_size_06 0 + #define default_param_perio_tx_fifo_size_07 0 + #define default_param_perio_tx_fifo_size_08 0 + #define default_param_perio_tx_fifo_size_09 0 + #define default_param_perio_tx_fifo_size_10 0 + #define default_param_perio_tx_fifo_size_11 0 + #define default_param_perio_tx_fifo_size_12 0 + #define default_param_perio_tx_fifo_size_13 0 + #define default_param_perio_tx_fifo_size_14 0 + #define default_param_perio_tx_fifo_size_15 0 + #endif //__IS_DEVICE__ + + #elif defined(__IS_AR9__) +// #define IFXUSB1_IRQ 54 + #define IFXUSB1_IOMEM_BASE 0x1E101000 + #define IFXUSB1_FIFOMEM_BASE 0x1E120000 + #define IFXUSB1_FIFODBG_BASE 0x1E140000 + +// #define IFXUSB2_IRQ 83 + #define IFXUSB2_IOMEM_BASE 0x1E106000 + #define IFXUSB2_FIFOMEM_BASE 0x1E1E0000 + #define IFXUSB2_FIFODBG_BASE 0x1E1C0000 + +// #define IFXUSB_OC_IRQ 60 + + #ifndef AMAZON_S_RCU_BASE_ADDR + #define AMAZON_S_RCU_BASE_ADDR (0xBF203000) + #endif + + #ifndef AMAZON_S_CGU + #define AMAZON_S_CGU (0xBF103000) + #endif + #ifndef AMAZON_S_CGU_IFCCR + #define AMAZON_S_CGU_IFCCR ((volatile unsigned long *)(AMAZON_S_CGU+ 0x0018)) + #endif + + #ifndef AMAZON_S_PMU + #define AMAZON_S_PMU (KSEG1+0x1F102000) + #endif + #ifndef AMAZON_S_PMU_PWDCR + #define AMAZON_S_PMU_PWDCR ((volatile unsigned long *)(AMAZON_S_PMU+0x001C)) + #endif + + #ifndef AMAZON_S_GPIO_P0_OUT + #define AMAZON_S_GPIO_P0_OUT (0xBF103000+0x10) + #define AMAZON_S_GPIO_P0_DIR (0xBF103000+0x18) + #define AMAZON_S_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) + #define AMAZON_S_GPIO_P0_ALTSEL1 (0xBF103000+0x20) + #define AMAZON_S_GPIO_P0_OD (0xBF103000+0x24) + #define AMAZON_S_GPIO_P0_PUDSEL (0xBF103000+0x2C) + #define AMAZON_S_GPIO_P0_PUDEN (0xBF103000+0x30) + #define AMAZON_S_GPIO_P1_OUT (0xBF103000+0x40) + #define AMAZON_S_GPIO_P1_DIR (0xBF103000+0x48) + #define AMAZON_S_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) + #define AMAZON_S_GPIO_P1_ALTSEL1 (0xBF103000+0x50) + #define AMAZON_S_GPIO_P1_OD (0xBF103000+0x54) + #define AMAZON_S_GPIO_P1_PUDSEL (0xBF103000+0x5C) + #define AMAZON_S_GPIO_P1_PUDEN (0xBF103000+0x60) + #endif + + #define AMAZON_S_RCU_USB1CFG ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x18)) + #define AMAZON_S_RCU_USB2CFG ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x34)) + #define AMAZON_S_RCU_USBRESET ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x10)) + #define AMAZON_S_USBCFG_ARB 7 // + #define AMAZON_S_USBCFG_HDSEL_BIT 11 // 0:host, 1:device + #define AMAZON_S_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end + #define AMAZON_S_USBCFG_SLV_END_BIT 17 // 0:little_end, 1:big_end + + #define default_param_dma_burst_size 4 + + #define default_param_speed IFXUSB_PARAM_SPEED_HIGH + + #define default_param_max_transfer_size -1 //(Max, hwcfg) + #define default_param_max_packet_count -1 //(Max, hwcfg) + #define default_param_phy_utmi_width 16 + + #define default_param_turn_around_time_hs 4 //(NoChange) + #define default_param_turn_around_time_fs 4 //(NoChange) + #define default_param_timeout_cal_hs -1 //(NoChange) + #define default_param_timeout_cal_fs -1 //(NoChange) + + #define default_param_data_fifo_size -1 //(Max, hwcfg) + + #ifdef __IS_HOST__ + #define default_param_host_channels -1 //(Max, hwcfg) + #define default_param_rx_fifo_size 240 + #define default_param_nperio_tx_fifo_size 240 + #define default_param_perio_tx_fifo_size 32 + #endif //__IS_HOST__ + #ifdef __IS_DEVICE__ + #ifdef __DED_INTR__ + #define default_param_rx_fifo_size 256 + #define default_param_nperio_tx_fifo_size 248 + #define default_param_perio_tx_fifo_size_01 8 + #else + #define default_param_rx_fifo_size 256 + #define default_param_nperio_tx_fifo_size 256 + #define default_param_perio_tx_fifo_size_01 0 + #endif + #define default_param_perio_tx_fifo_size_02 0 + #define default_param_perio_tx_fifo_size_03 0 + #define default_param_perio_tx_fifo_size_04 0 + #define default_param_perio_tx_fifo_size_05 0 + #define default_param_perio_tx_fifo_size_06 0 + #define default_param_perio_tx_fifo_size_07 0 + #define default_param_perio_tx_fifo_size_08 0 + #define default_param_perio_tx_fifo_size_09 0 + #define default_param_perio_tx_fifo_size_10 0 + #define default_param_perio_tx_fifo_size_11 0 + #define default_param_perio_tx_fifo_size_12 0 + #define default_param_perio_tx_fifo_size_13 0 + #define default_param_perio_tx_fifo_size_14 0 + #define default_param_perio_tx_fifo_size_15 0 + #endif //__IS_DEVICE__ + + #elif defined(__IS_VR9__) +// #define IFXUSB1_IRQ 54 + #define IFXUSB1_IOMEM_BASE 0x1E101000 + #define IFXUSB1_FIFOMEM_BASE 0x1E120000 + #define IFXUSB1_FIFODBG_BASE 0x1E140000 + +// #define IFXUSB2_IRQ 83 + #define IFXUSB2_IOMEM_BASE 0x1E106000 + #define IFXUSB2_FIFOMEM_BASE 0x1E1E0000 + #define IFXUSB2_FIFODBG_BASE 0x1E1C0000 +// #define IFXUSB_OC_IRQ 60 + + #ifndef AMAZON_S_RCU_BASE_ADDR + #define AMAZON_S_RCU_BASE_ADDR (0xBF203000) + #endif + + #ifndef AMAZON_S_CGU + #define AMAZON_S_CGU (0xBF103000) + #endif + #ifndef AMAZON_S_CGU_IFCCR + #define AMAZON_S_CGU_IFCCR ((volatile unsigned long *)(AMAZON_S_CGU+ 0x0018)) + #endif + + #ifndef AMAZON_S_PMU + #define AMAZON_S_PMU (KSEG1+0x1F102000) + #endif + #ifndef AMAZON_S_PMU_PWDCR + #define AMAZON_S_PMU_PWDCR ((volatile unsigned long *)(AMAZON_S_PMU+0x001C)) + #endif + + #ifndef AMAZON_S_GPIO_P0_OUT + #define AMAZON_S_GPIO_P0_OUT (0xBF103000+0x10) + #define AMAZON_S_GPIO_P0_DIR (0xBF103000+0x18) + #define AMAZON_S_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) + #define AMAZON_S_GPIO_P0_ALTSEL1 (0xBF103000+0x20) + #define AMAZON_S_GPIO_P0_OD (0xBF103000+0x24) + #define AMAZON_S_GPIO_P0_PUDSEL (0xBF103000+0x2C) + #define AMAZON_S_GPIO_P0_PUDEN (0xBF103000+0x30) + #define AMAZON_S_GPIO_P1_OUT (0xBF103000+0x40) + #define AMAZON_S_GPIO_P1_DIR (0xBF103000+0x48) + #define AMAZON_S_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) + #define AMAZON_S_GPIO_P1_ALTSEL1 (0xBF103000+0x50) + #define AMAZON_S_GPIO_P1_OD (0xBF103000+0x54) + #define AMAZON_S_GPIO_P1_PUDSEL (0xBF103000+0x5C) + #define AMAZON_S_GPIO_P1_PUDEN (0xBF103000+0x60) + #endif + + #define AMAZON_S_RCU_USB1CFG ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x18)) + #define AMAZON_S_RCU_USB2CFG ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x34)) + #define AMAZON_S_RCU_USBRESET ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x10)) + #define AMAZON_S_USBCFG_ARB 7 // + #define AMAZON_S_USBCFG_HDSEL_BIT 11 // 0:host, 1:device + #define AMAZON_S_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end + #define AMAZON_S_USBCFG_SLV_END_BIT 17 // 0:little_end, 1:big_end + + #define default_param_dma_burst_size 4 //(ALL) + + #define default_param_speed IFXUSB_PARAM_SPEED_HIGH + + #define default_param_max_transfer_size -1 //(Max, hwcfg) + #define default_param_max_packet_count -1 //(Max, hwcfg) + #define default_param_phy_utmi_width 16 + + #define default_param_turn_around_time_hs 6 //(NoChange) snpsid >= 0x4f54260a + #define default_param_turn_around_time_fs 6 //(NoChange) snpsid >= 0x4f54260a + #define default_param_timeout_cal_hs -1 //(NoChange) + #define default_param_timeout_cal_fs -1 //(NoChange) + + #define default_param_data_fifo_size -1 //(Max, hwcfg) + + #ifdef __IS_HOST__ + #define default_param_host_channels -1 //(Max, hwcfg) + #define default_param_rx_fifo_size 240 + #define default_param_nperio_tx_fifo_size 240 + #define default_param_perio_tx_fifo_size 32 + #endif //__IS_HOST__ + #ifdef __IS_DEVICE__ + #define default_param_rx_fifo_size 256 + #define default_param_tx_fifo_size_00 -1 + #define default_param_tx_fifo_size_01 -1 + #define default_param_tx_fifo_size_02 -1 + #define default_param_tx_fifo_size_03 -1 + #define default_param_tx_fifo_size_04 -1 + #define default_param_tx_fifo_size_05 -1 + #define default_param_tx_fifo_size_06 -1 + #define default_param_tx_fifo_size_07 -1 + #define default_param_tx_fifo_size_08 -1 + #define default_param_tx_fifo_size_09 -1 + #define default_param_tx_fifo_size_10 -1 + #define default_param_tx_fifo_size_11 -1 + #define default_param_tx_fifo_size_12 -1 + #define default_param_tx_fifo_size_13 -1 + #define default_param_tx_fifo_size_14 -1 + #define default_param_tx_fifo_size_15 -1 + #define default_param_dma_unalgned_tx -1 + #define default_param_dma_unalgned_rx -1 + #define default_param_thr_ctl -1 + #define default_param_tx_thr_length -1 + #define default_param_rx_thr_length -1 + #endif //__IS_DEVICE__ + #else // __IS_VR9__ + #error "Please choose one platform!!" + #endif // __IS_VR9__ +#endif //UEIP + +/*@}*//*IFXUSB_PLATEFORM_MEM_ADDR*/ + +///////////////////////////////////////////////////////////////////////// + +#ifdef __IS_HOST__ + #ifdef CONFIG_USB_HOST_IFX_FORCE_USB11 + #undef default_param_speed + #define default_param_speed IFXUSB_PARAM_SPEED_FULL + #endif +#endif +#ifdef __IS_DEVICE__ + #ifndef CONFIG_USB_GADGET_DUALSPEED + #undef default_param_speed + #define default_param_speed IFXUSB_PARAM_SPEED_FULL + #endif +#endif + +///////////////////////////////////////////////////////////////////////// + +static __inline__ void UDELAY( const uint32_t _usecs ) +{ + udelay( _usecs ); +} + +static __inline__ void MDELAY( const uint32_t _msecs ) +{ + mdelay( _msecs ); +} + +static __inline__ void SPIN_LOCK( spinlock_t *_lock ) +{ + spin_lock(_lock); +} + +static __inline__ void SPIN_UNLOCK( spinlock_t *_lock ) +{ + spin_unlock(_lock); +} + +#define SPIN_LOCK_IRQSAVE( _l, _f ) \ + { \ + spin_lock_irqsave(_l,_f); \ + } + +#define SPIN_UNLOCK_IRQRESTORE( _l,_f ) \ + { \ + spin_unlock_irqrestore(_l,_f); \ + } + +///////////////////////////////////////////////////////////////////////// +/*! + \addtogroup IFXUSB_DBG_ROUTINE + */ +/*@{*/ +#ifdef __IS_HOST__ + extern uint32_t h_dbg_lvl; +#endif + +#ifdef __IS_DEVICE__ + extern uint32_t d_dbg_lvl; +#endif + +/*! \brief When debug level has the DBG_CIL bit set, display CIL Debug messages. */ +#define DBG_CIL (0x2) +/*! \brief When debug level has the DBG_CILV bit set, display CIL Verbose debug messages */ +#define DBG_CILV (0x20) +/*! \brief When debug level has the DBG_PCD bit set, display PCD (Device) debug messages */ +#define DBG_PCD (0x4) +/*! \brief When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug messages */ +#define DBG_PCDV (0x40) +/*! \brief When debug level has the DBG_HCD bit set, display Host debug messages */ +#define DBG_HCD (0x8) +/*! \brief When debug level has the DBG_HCDV bit set, display Verbose Host debug messages */ +#define DBG_HCDV (0x80) +/*! \brief When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host mode. */ +#define DBG_HCD_URB (0x800) +/*! \brief When debug level has any bit set, display debug messages */ +#define DBG_ANY (0xFF) +/*! \brief All debug messages off */ +#define DBG_OFF 0 + +#define DBG_ENTRY (0x8000) + +#define IFXUSB "IFXUSB: " + +/*! + \fn inline uint32_t SET_DEBUG_LEVEL( const uint32_t _new ) + \brief Set the Debug Level variable. + \param _new 32-bit mask of debug level. + \return previous debug level + */ +static inline uint32_t SET_DEBUG_LEVEL( const uint32_t _new ) +{ + #ifdef __IS_HOST__ + uint32_t old = h_dbg_lvl; + h_dbg_lvl = _new; + #endif + + #ifdef __IS_DEVICE__ + uint32_t old = d_dbg_lvl; + d_dbg_lvl = _new; + #endif + return old; +} + +#ifdef __DEBUG__ + #ifdef __IS_HOST__ + # define IFX_DEBUGPL(lvl, x...) do{ if ((lvl)&h_dbg_lvl)printk( KERN_DEBUG IFXUSB x ); }while(0) + # define CHK_DEBUG_LEVEL(level) ((level) & h_dbg_lvl) + #endif + + #ifdef __IS_DEVICE__ + # define IFX_DEBUGPL(lvl, x...) do{ if ((lvl)&d_dbg_lvl)printk( KERN_DEBUG IFXUSB x ); }while(0) + # define CHK_DEBUG_LEVEL(level) ((level) & d_dbg_lvl) + #endif + + # define IFX_DEBUGP(x...) IFX_DEBUGPL(DBG_ANY, x ) +#else + # define IFX_DEBUGPL(lvl, x...) do{}while(0) + # define IFX_DEBUGP(x...) + # define CHK_DEBUG_LEVEL(level) (0) +#endif //__DEBUG__ + +/* Print an Error message. */ +#define IFX_ERROR(x...) printk( KERN_ERR IFXUSB x ) +/* Print a Warning message. */ +#define IFX_WARN(x...) printk( KERN_WARNING IFXUSB x ) +/* Print a notice (normal but significant message). */ +#define IFX_NOTICE(x...) printk( KERN_NOTICE IFXUSB x ) +/* Basic message printing. */ +#define IFX_PRINT(x...) printk( KERN_INFO IFXUSB x ) + +/*@}*//*IFXUSB_DBG_ROUTINE*/ + + +#endif //__IFXUSB_PLAT_H__ + diff --git a/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_regs.h b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_regs.h new file mode 100644 index 0000000000..014c6dbcfd --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_regs.h @@ -0,0 +1,1420 @@ +/***************************************************************************** + ** FILE NAME : ifxusb_regs.h + ** PROJECT : IFX USB sub-system V3 + ** MODULES : IFX USB sub-system Host and Device driver + ** SRC VERSION : 1.0 + ** DATE : 1/Jan/2009 + ** AUTHOR : Chen, Howard + ** DESCRIPTION : This file contains the data structures for accessing the IFXUSB core + ** registers. + ** The application interfaces with the USB core by reading from and + ** writing to the Control and Status Register (CSR) space through the + ** AHB Slave interface. These registers are 32 bits wide, and the + ** addresses are 32-bit-block aligned. + ** CSRs are classified as follows: + ** - Core Global Registers + ** - Device Mode Registers + ** - Device Global Registers + ** - Device Endpoint Specific Registers + ** - Host Mode Registers + ** - Host Global Registers + ** - Host Port CSRs + ** - Host Channel Specific Registers + ** + ** Only the Core Global registers can be accessed in both Device and + ** Host modes. When the USB core is operating in one mode, either + ** Device or Host, the application must not access registers from the + ** other mode. When the core switches from one mode to another, the + ** registers in the new mode of operation must be reprogrammed as they + ** would be after a power-on reset. + ** FUNCTIONS : + ** COMPILER : gcc + ** REFERENCE : Synopsys DWC-OTG Driver 2.7 + ** COPYRIGHT : + ** Version Control Section ** + ** $Author$ + ** $Date$ + ** $Revisions$ + ** $Log$ Revision history +*****************************************************************************/ + + + +/*! + \defgroup IFXUSB_CSR_DEFINITION Control and Status Register bit-map definition + \ingroup IFXUSB_DRIVER_V3 + \brief Data structures for accessing the IFXUSB core registers. + The application interfaces with the USB core by reading from and + writing to the Control and Status Register (CSR) space through the + AHB Slave interface. These registers are 32 bits wide, and the + addresses are 32-bit-block aligned. + CSRs are classified as follows: + - Core Global Registers + - Device Mode Registers + - Device Global Registers + - Device Endpoint Specific Registers + - Host Mode Registers + - Host Global Registers + - Host Port CSRs + - Host Channel Specific Registers + + Only the Core Global registers can be accessed in both Device andHost modes. + When the USB core is operating in one mode, either Device or Host, the + application must not access registers from the other mode. When the core + switches from one mode to another, the registers in the new mode of operation + must be reprogrammed as they would be after a power-on reset. + */ + +/*! + \defgroup IFXUSB_CSR_DEVICE_GLOBAL_REG Device Mode Registers + \ingroup IFXUSB_CSR_DEFINITION + \brief Bit-mapped structure to access Device Mode Global Registers + */ + +/*! + \defgroup IFXUSB_CSR_DEVICE_EP_REG Device Mode EP Registers + \ingroup IFXUSB_CSR_DEFINITION + \brief Bit-mapped structure to access Device Mode EP Registers + There will be one set of endpoint registers per logical endpoint + implemented. + These registers are visible only in Device mode and must not be + accessed in Host mode, as the results are unknown. + */ + +/*! + \defgroup IFXUSB_CSR_DEVICE_DMA_DESC Device mode scatter dma descriptor strusture + \ingroup IFXUSB_CSR_DEFINITION + \brief Bit-mapped structure to DMA descriptor + */ + + +/*! + \defgroup IFXUSB_CSR_HOST_GLOBAL_REG Host Mode Registers + \ingroup IFXUSB_CSR_DEFINITION + \brief Bit-mapped structure to access Host Mode Global Registers + */ + +/*! + \defgroup IFXUSB_CSR_HOST_HC_REG Host Mode HC Registers + \ingroup IFXUSB_CSR_DEFINITION + \brief Bit-mapped structure to access Host Mode Host Channel Registers + There will be one set of endpoint registers per host channel + implemented. + These registers are visible only in Host mode and must not be + accessed in Device mode, as the results are unknown. + */ + +/*! + \defgroup IFXUSB_CSR_PWR_CLK_GATING_REG Power and Clock Gating Control Register + \ingroup IFXUSB_CSR_DEFINITION + \brief Bit-mapped structure to Power and Clock Gating Control Register + */ + + + + + + + + +/*! + \defgroup IFXUSB_CSR_CORE_GLOBAL_REG Core Global Registers + \ingroup IFXUSB_CSR_DEFINITION + \brief Bit-mapped structure to access Core Global Registers + */ +/*! + \defgroup IFXUSB_CSR_CORE_GLOBAL_REG Core Global Registers + \ingroup IFXUSB_CSR_DEFINITION + \brief Bit-mapped structure to access Core Global Registers + */ + + + + + + + + + +/*! + \file ifxusb_regs.h + \ingroup IFXUSB_DRIVER_V3 + \brief This file contains the data structures for accessing the IFXUSB core registers. + */ + + +#ifndef __IFXUSB_REGS_H__ +#define __IFXUSB_REGS_H__ + +/****************************************************************************/ + +#define MAX_PERIO_FIFOS 15 /** Maximum number of Periodic FIFOs */ +#define MAX_TX_FIFOS 15 /** Maximum number of Periodic FIFOs */ +#define MAX_EPS_CHANNELS 16 /** Maximum number of Endpoints/HostChannels */ + +/****************************************************************************/ + +/*! + \addtogroup IFXUSB_CSR_ACCESS_MACROS + */ +/*@{*/ + +//#define RecordRegRW + +/*! + \fn static __inline__ uint32_t ifxusb_rreg( volatile uint32_t *_reg) + \brief Reads the content of a register. + \param _reg address of register to read. + \return contents of the register. + */ +static __inline__ uint32_t ifxusb_rreg( volatile uint32_t *_reg) +{ + #ifdef RecordRegRW + uint32_t r; + r=*(_reg); + return (r); + #else + return (*(_reg)); + #endif +}; + + +/*! + \fn static __inline__ void ifxusb_wreg( volatile uint32_t *_reg, const uint32_t _value) + \brief Writes a register with a 32 bit value. + \param _reg address of register to write. + \param _value value to write to _reg. + */ +static __inline__ void ifxusb_wreg( volatile uint32_t *_reg, const uint32_t _value) +{ + #ifdef RecordRegRW + printk(KERN_INFO "[W %p<-%08X]\n",_reg,_value); + #else + *(_reg)=_value; + #endif +}; + +/*! + \fn static __inline__ void ifxusb_mreg( volatile uint32_t *_reg, const uint32_t _clear_mask, const uint32_t _set_mask) + \brief Modifies bit values in a register. Using the + algorithm: (reg_contents & ~clear_mask) | set_mask. + \param _reg address of register to modify. + \param _clear_mask bit mask to be cleared. + \param _set_mask bit mask to be set. + */ +static __inline__ void ifxusb_mreg( volatile uint32_t *_reg, const uint32_t _clear_mask, const uint32_t _set_mask) +{ + uint32_t v; + #ifdef RecordRegRW + uint32_t r; + v= *(_reg); + r=v; + r&=(~_clear_mask); + r|= _set_mask; + *(_reg)=r ; + printk(KERN_INFO "[M %p->%08X+%08X/%08X<-%08X]\n",_reg,r,_clear_mask,_set_mask,r); + #else + v= *(_reg); + v&=(~_clear_mask); + v|= _set_mask; + *(_reg)=v ; + #endif +}; + +/*@}*//*IFXUSB_CSR_ACCESS_MACROS*/ +/****************************************************************************/ + +/*! + \addtogroup IFXUSB_CSR_CORE_GLOBAL_REG + */ +/*@{*/ + +/*! + \struct ifxusb_core_global_regs + \brief IFXUSB Core registers . + The ifxusb_core_global_regs structure defines the size + and relative field offsets for the Core Global registers. + */ +typedef struct ifxusb_core_global_regs +{ + volatile uint32_t gotgctl; /*!< 000h OTG Control and Status Register. */ + volatile uint32_t gotgint; /*!< 004h OTG Interrupt Register. */ + volatile uint32_t gahbcfg; /*!< 008h Core AHB Configuration Register. */ + volatile uint32_t gusbcfg; /*!< 00Ch Core USB Configuration Register. */ + volatile uint32_t grstctl; /*!< 010h Core Reset Register. */ + volatile uint32_t gintsts; /*!< 014h Core Interrupt Register. */ + volatile uint32_t gintmsk; /*!< 018h Core Interrupt Mask Register. */ + volatile uint32_t grxstsr; /*!< 01Ch Receive Status Queue Read Register (Read Only). */ + volatile uint32_t grxstsp; /*!< 020h Receive Status Queue Read & POP Register (Read Only). */ + volatile uint32_t grxfsiz; /*!< 024h Receive FIFO Size Register. */ + volatile uint32_t gnptxfsiz; /*!< 028h Non Periodic Transmit FIFO Size Register. */ + volatile uint32_t gnptxsts; /*!< 02Ch Non Periodic Transmit FIFO/Queue Status Register (Read Only). */ + volatile uint32_t gi2cctl; /*!< 030h I2C Access Register. */ + volatile uint32_t gpvndctl; /*!< 034h PHY Vendor Control Register. */ + volatile uint32_t ggpio; /*!< 038h General Purpose Input/Output Register. */ + volatile uint32_t guid; /*!< 03Ch User ID Register. */ + volatile uint32_t gsnpsid; /*!< 040h Synopsys ID Register (Read Only). */ + volatile uint32_t ghwcfg1; /*!< 044h User HW Config1 Register (Read Only). */ + volatile uint32_t ghwcfg2; /*!< 048h User HW Config2 Register (Read Only). */ + volatile uint32_t ghwcfg3; /*!< 04Ch User HW Config3 Register (Read Only). */ + volatile uint32_t ghwcfg4; /*!< 050h User HW Config4 Register (Read Only). */ + volatile uint32_t reserved[43]; /*!< 054h Reserved 054h-0FFh */ + volatile uint32_t hptxfsiz; /*!< 100h Host Periodic Transmit FIFO Size Register. */ + volatile uint32_t dptxfsiz_dieptxf[15];/*!< 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15. + Device Periodic Transmit FIFO#n Register if dedicated + fifos are disabled, otherwise Device Transmit FIFO#n + Register. + */ +} ifxusb_core_global_regs_t; + +/*! + \brief Bits of the Core OTG Control and Status Register (GOTGCTL). + */ +typedef union gotgctl_data +{ + uint32_t d32; + struct{ + unsigned reserved21_31 : 11; + unsigned currmod : 1 ; /*!< 20 */ + unsigned bsesvld : 1 ; /*!< 19 */ + unsigned asesvld : 1 ; /*!< 18 */ + unsigned reserved17 : 1 ; + unsigned conidsts : 1 ; /*!< 16 */ + unsigned reserved12_15 : 4 ; + unsigned devhnpen : 1 ; /*!< 11 */ + unsigned hstsethnpen : 1 ; /*!< 10 */ + unsigned hnpreq : 1 ; /*!< 09 */ + unsigned hstnegscs : 1 ; /*!< 08 */ + unsigned reserved2_7 : 6 ; + unsigned sesreq : 1 ; /*!< 01 */ + unsigned sesreqscs : 1 ; /*!< 00 */ + } b; +} gotgctl_data_t; + +/*! + \brief Bit fields of the Core OTG Interrupt Register (GOTGINT). + */ +typedef union gotgint_data +{ + uint32_t d32; + struct + { + unsigned reserved31_20 : 12; + unsigned debdone : 1 ; /*!< 19 Debounce Done */ + unsigned adevtoutchng : 1 ; /*!< 18 A-Device Timeout Change */ + unsigned hstnegdet : 1 ; /*!< 17 Host Negotiation Detected */ + unsigned reserver10_16 : 7 ; + unsigned hstnegsucstschng : 1 ; /*!< 09 Host Negotiation Success Status Change */ + unsigned sesreqsucstschng : 1 ; /*!< 08 Session Request Success Status Change */ + unsigned reserved3_7 : 5 ; + unsigned sesenddet : 1 ; /*!< 02 Session End Detected */ + unsigned reserved0_1 : 2 ; + } b; +} gotgint_data_t; + +/*! + \brief Bit fields of the Core AHB Configuration Register (GAHBCFG). + */ +typedef union gahbcfg_data +{ + uint32_t d32; + struct + { + unsigned reserved9_31 : 23; + unsigned ptxfemplvl : 1 ; /*!< 08 Periodic FIFO empty level trigger condition*/ + unsigned nptxfemplvl : 1 ; /*!< 07 Non-Periodic FIFO empty level trigger condition*/ + #define IFXUSB_GAHBCFG_TXFEMPTYLVL_EMPTY 1 + #define IFXUSB_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 + unsigned reserved : 1 ; + unsigned dmaenable : 1 ; /*!< 05 DMA enable*/ + #define IFXUSB_GAHBCFG_DMAENABLE 1 + unsigned hburstlen : 4 ; /*!< 01-04 DMA Burst-length*/ + #define IFXUSB_GAHBCFG_INT_DMA_BURST_SINGLE 0 + #define IFXUSB_GAHBCFG_INT_DMA_BURST_INCR 1 + #define IFXUSB_GAHBCFG_INT_DMA_BURST_INCR4 3 + #define IFXUSB_GAHBCFG_INT_DMA_BURST_INCR8 5 + #define IFXUSB_GAHBCFG_INT_DMA_BURST_INCR16 7 + unsigned glblintrmsk : 1 ; /*!< 00 USB Global Interrupt Enable */ + #define IFXUSB_GAHBCFG_GLBINT_ENABLE 1 + } b; +} gahbcfg_data_t; + +/*! + \brief Bit fields of the Core USB Configuration Register (GUSBCFG). +*/ +typedef union gusbcfg_data +{ + uint32_t d32; + struct + { + unsigned reserved31 : 1; + unsigned ForceDevMode : 1; /*!< 30 Force Device Mode */ + unsigned ForceHstMode : 1; /*!< 29 Force Host Mode */ + unsigned TxEndDelay : 1; /*!< 28 Tx End Delay */ + unsigned reserved2723 : 5; + unsigned term_sel_dl_pulse : 1; /*!< 22 TermSel DLine Pulsing Selection */ + unsigned reserved2117 : 5; + unsigned otgutmifssel : 1; /*!< 16 UTMIFS Select */ + unsigned phylpwrclksel : 1; /*!< 15 PHY Low-Power Clock Select */ + unsigned reserved14 : 1; + unsigned usbtrdtim : 4; /*!< 13-10 USB Turnaround Time */ + unsigned hnpcap : 1; /*!< 09 HNP-Capable */ + unsigned srpcap : 1; /*!< 08 SRP-Capable */ + unsigned reserved07 : 1; + unsigned physel : 1; /*!< 06 USB 2.0 High-Speed PHY or + USB 1.1 Full-Speed Serial + Transceiver Select */ + unsigned fsintf : 1; /*!< 05 Full-Speed Serial Interface Select */ + unsigned ulpi_utmi_sel : 1; /*!< 04 ULPI or UTMI+ Select */ + unsigned phyif : 1; /*!< 03 PHY Interface */ + unsigned toutcal : 3; /*!< 00-02 HS/FS Timeout Calibration */ + }b; +} gusbcfg_data_t; + +/*! + \brief Bit fields of the Core Reset Register (GRSTCTL). + */ +typedef union grstctl_data +{ + uint32_t d32; + struct + { + unsigned ahbidle : 1; /*!< 31 AHB Master Idle. Indicates the AHB Master State + Machine is in IDLE condition. */ + unsigned dmareq : 1; /*!< 30 DMA Request Signal. Indicated DMA request is in + probress. Used for debug purpose. */ + unsigned reserved11_29 :19; + unsigned txfnum : 5; /*!< 10-06 TxFIFO Number (TxFNum) to be flushed. + 0x00: Non Periodic TxFIFO Flush or TxFIFO 0 + 0x01-0x0F: Periodic TxFIFO Flush or TxFIFO n + 0x10: Flush all TxFIFO + */ + unsigned txfflsh : 1; /*!< 05 TxFIFO Flush */ + unsigned rxfflsh : 1; /*!< 04 RxFIFO Flush */ + unsigned intknqflsh : 1; /*!< 03 In Token Sequence Learning Queue Flush (Device Only) */ + unsigned hstfrm : 1; /*!< 02 Host Frame Counter Reset (Host Only) */ + unsigned hsftrst : 1; /*!< 01 Hclk Soft Reset */ + + unsigned csftrst : 1; /*!< 00 Core Soft Reset + The application can flush the control logic in the + entire core using this bit. This bit resets the + pipelines in the AHB Clock domain as well as the + PHY Clock domain. + The state machines are reset to an IDLE state, the + control bits in the CSRs are cleared, all the + transmit FIFOs and the receive FIFO are flushed. + The status mask bits that control the generation of + the interrupt, are cleared, to clear the + interrupt. The interrupt status bits are not + cleared, so the application can get the status of + any events that occurred in the core after it has + set this bit. + Any transactions on the AHB are terminated as soon + as possible following the protocol. Any + transactions on the USB are terminated immediately. + The configuration settings in the CSRs are + unchanged, so the software doesn't have to + reprogram these registers (Device + Configuration/Host Configuration/Core System + Configuration/Core PHY Configuration). + The application can write to this bit, any time it + wants to reset the core. This is a self clearing + bit and the core clears this bit after all the + necessary logic is reset in the core, which may + take several clocks, depending on the current state + of the core. + */ + }b; +} grstctl_t; + +/*! + \brief Bit fields of the Core Interrupt Mask Register (GINTMSK) and + Core Interrupt Register (GINTSTS). + */ +typedef union gint_data +{ + uint32_t d32; + #define IFXUSB_SOF_INTR_MASK 0x0008 + struct + { + unsigned wkupintr : 1; /*!< 31 Resume/Remote Wakeup Detected Interrupt */ + unsigned sessreqintr : 1; /*!< 30 Session Request/New Session Detected Interrupt */ + unsigned disconnect : 1; /*!< 29 Disconnect Detected Interrupt */ + unsigned conidstschng : 1; /*!< 28 Connector ID Status Change */ + unsigned reserved27 : 1; + unsigned ptxfempty : 1; /*!< 26 Periodic TxFIFO Empty */ + unsigned hcintr : 1; /*!< 25 Host Channels Interrupt */ + unsigned portintr : 1; /*!< 24 Host Port Interrupt */ + unsigned reserved23 : 1; + unsigned fetsuspmsk : 1; /*!< 22 Data Fetch Suspended */ + unsigned incomplisoout : 1; /*!< 21 Incomplete IsochronousOUT/Period Transfer */ + unsigned incomplisoin : 1; /*!< 20 Incomplete Isochronous IN Transfer */ + unsigned outepintr : 1; /*!< 19 OUT Endpoints Interrupt */ + unsigned inepintr : 1; /*!< 18 IN Endpoints Interrupt */ + unsigned epmismatch : 1; /*!< 17 Endpoint Mismatch Interrupt */ + unsigned reserved16 : 1; + unsigned eopframe : 1; /*!< 15 End of Periodic Frame Interrupt */ + unsigned isooutdrop : 1; /*!< 14 Isochronous OUT Packet Dropped Interrupt */ + unsigned enumdone : 1; /*!< 13 Enumeration Done */ + unsigned usbreset : 1; /*!< 12 USB Reset */ + unsigned usbsuspend : 1; /*!< 11 USB Suspend */ + unsigned erlysuspend : 1; /*!< 10 Early Suspend */ + unsigned i2cintr : 1; /*!< 09 I2C Interrupt */ + unsigned reserved8 : 1; + unsigned goutnakeff : 1; /*!< 07 Global OUT NAK Effective */ + unsigned ginnakeff : 1; /*!< 06 Global Non-periodic IN NAK Effective */ + unsigned nptxfempty : 1; /*!< 05 Non-periodic TxFIFO Empty */ + unsigned rxstsqlvl : 1; /*!< 04 Receive FIFO Non-Empty */ + unsigned sofintr : 1; /*!< 03 Start of (u)Frame */ + unsigned otgintr : 1; /*!< 02 OTG Interrupt */ + unsigned modemismatch : 1; /*!< 01 Mode Mismatch Interrupt */ + unsigned reserved0 : 1; + } b; +} gint_data_t; + +/*! + \brief Bit fields in the Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) + */ +typedef union grxsts_data +{ + uint32_t d32; + struct + { + unsigned reserved : 7; + unsigned fn : 4; /*!< 24-21 Frame Number */ + unsigned pktsts : 4; /*!< 20-17 Packet Status */ + #define IFXUSB_DSTS_DATA_UPDT 0x2 // OUT Data Packet + #define IFXUSB_DSTS_XFER_COMP 0x3 // OUT Data Transfer Complete + #define IFXUSB_DSTS_GOUT_NAK 0x1 // Global OUT NAK + #define IFXUSB_DSTS_SETUP_COMP 0x4 // Setup Phase Complete + #define IFXUSB_DSTS_SETUP_UPDT 0x6 // SETUP Packet + unsigned dpid : 2; /*!< 16-15 Data PID */ + unsigned bcnt :11; /*!< 14-04 Byte Count */ + unsigned epnum : 4; /*!< 03-00 Endpoint Number */ + } db; + struct + { + unsigned reserved :11; + unsigned pktsts : 4; /*!< 20-17 Packet Status */ + #define IFXUSB_HSTS_DATA_UPDT 0x2 // OUT Data Packet + #define IFXUSB_HSTS_XFER_COMP 0x3 // OUT Data Transfer Complete + #define IFXUSB_HSTS_DATA_TOGGLE_ERR 0x5 // DATA TOGGLE Error + #define IFXUSB_HSTS_CH_HALTED 0x7 // Channel Halted + unsigned dpid : 2; /*!< 16-15 Data PID */ + unsigned bcnt :11; /*!< 14-04 Byte Count */ + unsigned chnum : 4; /*!< 03-00 Channel Number */ + } hb; +} grxsts_data_t; + +/*! + \brief Bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn). + */ +typedef union fifosize_data +{ + uint32_t d32; + struct + { + unsigned depth : 16; /*!< 31-16 TxFIFO Depth (in DWord)*/ + unsigned startaddr : 16; /*!< 15-00 RAM Starting address */ + } b; +} fifosize_data_t; + +/*! + \brief Bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS). + */ + +typedef union gnptxsts_data +{ + uint32_t d32; + struct + { + unsigned reserved : 1; + unsigned nptxqtop_chnep : 4; /*!< 30-27 Channel/EP Number of top of the Non-Periodic + Transmit Request Queue + */ + unsigned nptxqtop_token : 2; /*!< 26-25 Token Type top of the Non-Periodic + Transmit Request Queue + 0 - IN/OUT + 1 - Zero Length OUT + 2 - PING/Complete Split + 3 - Channel Halt + */ + unsigned nptxqtop_terminate : 1; /*!< 24 Terminate (Last entry for the selected + channel/EP)*/ + unsigned nptxqspcavail : 8; /*!< 23-16 Transmit Request Queue Space Available */ + unsigned nptxfspcavail :16; /*!< 15-00 TxFIFO Space Avail (in DWord)*/ + }b; +} gnptxsts_data_t; + + +/*! + \brief Bit fields in the Transmit FIFO Status Register (DTXFSTS). + */ +typedef union dtxfsts_data +{ + uint32_t d32; + struct + { + unsigned reserved : 16; + unsigned txfspcavail : 16; /*!< 15-00 TxFIFO Space Avail (in DWord)*/ + }b; +} dtxfsts_data_t; + + +/*! + \brief Bit fields in the I2C Control Register (I2CCTL). + */ +typedef union gi2cctl_data +{ + uint32_t d32; + struct + { + unsigned bsydne : 1; /*!< 31 I2C Busy/Done*/ + unsigned rw : 1; /*!< 30 Read/Write Indicator */ + unsigned reserved : 2; + unsigned i2cdevaddr : 2; /*!< 27-26 I2C Device Address */ + unsigned i2csuspctl : 1; /*!< 25 I2C Suspend Control */ + unsigned ack : 1; /*!< 24 I2C ACK */ + unsigned i2cen : 1; /*!< 23 I2C Enable */ + unsigned addr : 7; /*!< 22-16 I2C Address */ + unsigned regaddr : 8; /*!< 15-08 I2C Register Addr */ + unsigned rwdata : 8; /*!< I2C Read/Write Data */ + } b; +} gi2cctl_data_t; + + +/*! + \brief Bit fields in the User HW Config1 Register. + */ +typedef union hwcfg1_data +{ + uint32_t d32; + struct + { + unsigned ep_dir15 : 2; /*!< Direction of each EP + 0: BIDIR (IN and OUT) endpoint + 1: IN endpoint + 2: OUT endpoint + 3: Reserved + */ + unsigned ep_dir14 : 2; + unsigned ep_dir13 : 2; + unsigned ep_dir12 : 2; + unsigned ep_dir11 : 2; + unsigned ep_dir10 : 2; + unsigned ep_dir09 : 2; + unsigned ep_dir08 : 2; + unsigned ep_dir07 : 2; + unsigned ep_dir06 : 2; + unsigned ep_dir05 : 2; + unsigned ep_dir04 : 2; + unsigned ep_dir03 : 2; + unsigned ep_dir02 : 2; + unsigned ep_dir01 : 2; + unsigned ep_dir00 : 2; + }b; +} hwcfg1_data_t; + +/*! + \brief Bit fields in the User HW Config2 Register. + */ +typedef union hwcfg2_data +{ + uint32_t d32; + struct + { + unsigned reserved31 : 1; + unsigned dev_token_q_depth : 5; /*!< 30-26 Device Mode IN Token Sequence Learning Queue Depth */ + unsigned host_perio_tx_q_depth : 2; /*!< 25-24 Host Mode Periodic Request Queue Depth */ + unsigned nonperio_tx_q_depth : 2; /*!< 23-22 Non-periodic Request Queue Depth */ + unsigned rx_status_q_depth : 2; /*!< 21-20 Multi Processor Interrupt Enabled */ + unsigned dynamic_fifo : 1; /*!< 19 Dynamic FIFO Sizing Enabled */ + unsigned perio_ep_supported : 1; /*!< 18 Periodic OUT Channels Supported in Host Mode */ + unsigned num_host_chan : 4; /*!< 17-14 Number of Host Channels */ + unsigned num_dev_ep : 4; /*!< 13-10 Number of Device Endpoints */ + unsigned fs_phy_type : 2; /*!< 09-08 Full-Speed PHY Interface Type */ + #define IFXUSB_HWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0 + #define IFXUSB_HWCFG2_FS_PHY_TYPE_DEDICATE 1 + #define IFXUSB_HWCFG2_FS_PHY_TYPE_UTMI 2 + #define IFXUSB_HWCFG2_FS_PHY_TYPE_ULPI 3 + unsigned hs_phy_type : 2; /*!< 07-06 High-Speed PHY Interface Type */ + #define IFXUSB_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 + #define IFXUSB_HWCFG2_HS_PHY_TYPE_UTMI 1 + #define IFXUSB_HWCFG2_HS_PHY_TYPE_ULPI 2 + #define IFXUSB_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 + unsigned point2point : 1; /*!< 05 Point-to-Point */ + unsigned architecture : 2; /*!< 04-03 Architecture */ + #define IFXUSB_HWCFG2_ARCH_SLAVE_ONLY 0 + #define IFXUSB_HWCFG2_ARCH_EXT_DMA 1 + #define IFXUSB_HWCFG2_ARCH_INT_DMA 2 + unsigned op_mode : 3; /*!< 02-00 Mode of Operation */ + #define IFXUSB_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0 + #define IFXUSB_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1 + #define IFXUSB_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2 + #define IFXUSB_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 + #define IFXUSB_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 + #define IFXUSB_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 + #define IFXUSB_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 + } b; +} hwcfg2_data_t; + +/*! + \brief Bit fields in the User HW Config3 Register. + */ +typedef union hwcfg3_data +{ + uint32_t d32; + struct + { + unsigned dfifo_depth :16; /*!< 31-16 DFIFO Depth */ + unsigned reserved15_12 : 4; + unsigned synch_reset_type : 1; /*!< 11 Reset Style for Clocked always Blocks in RTL */ + unsigned optional_features : 1; /*!< 10 Optional Features Removed */ + unsigned vendor_ctrl_if : 1; /*!< 09 Vendor Control Interface Support */ + unsigned i2c : 1; /*!< 08 I2C Selection */ + unsigned otg_func : 1; /*!< 07 OTG Function Enabled */ + unsigned packet_size_cntr_width : 3; /*!< 06-04 Width of Packet Size Counters */ + unsigned xfer_size_cntr_width : 4; /*!< 03-00 Width of Transfer Size Counters */ + } b; +} hwcfg3_data_t; + +/*! + \brief Bit fields in the User HW Config4 + * Register. Read the register into the d32 element then read + * out the bits using the bit elements. + */ +typedef union hwcfg4_data +{ + uint32_t d32; + struct + { + unsigned desc_dma_dyn : 1; /*!< 31 Scatter/Gather DMA */ + unsigned desc_dma : 1; /*!< 30 Scatter/Gather DMA configuration */ + unsigned num_in_eps : 4; /*!< 29-26 Number of Device Mode IN Endpoints Including Control Endpoints */ + unsigned ded_fifo_en : 1; /*!< 25 Enable Dedicated Transmit FIFO for device IN Endpoints */ + unsigned session_end_filt_en : 1; /*!< 24 session_end Filter Enabled */ + unsigned b_valid_filt_en : 1; /*!< 23 b_valid Filter Enabled */ + unsigned a_valid_filt_en : 1; /*!< 22 a_valid Filter Enabled */ + unsigned vbus_valid_filt_en : 1; /*!< 21 vbus_valid Filter Enabled */ + unsigned iddig_filt_en : 1; /*!< 20 iddig Filter Enable */ + unsigned num_dev_mode_ctrl_ep : 4; /*!< 19-16 Number of Device Mode Control Endpoints in Addition to Endpoint 0 */ + unsigned utmi_phy_data_width : 2; /*!< 15-14 UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width */ + unsigned reserved13_06 : 8; + unsigned min_ahb_freq : 1; /*!< 05 Minimum AHB Frequency Less Than 60 MHz */ + unsigned power_optimiz : 1; /*!< 04 Enable Power Optimization? */ + unsigned num_dev_perio_in_ep : 4; /*!< 03-00 Number of Device Mode Periodic IN Endpoints */ + } b; +} hwcfg4_data_t; + +/*@}*//*IFXUSB_CSR_CORE_GLOBAL_REG*/ + +/****************************************************************************/ +/*! + \addtogroup IFXUSB_CSR_DEVICE_GLOBAL_REG + */ +/*@{*/ + +/*! + \struct ifxusb_dev_global_regs + \brief IFXUSB Device Mode Global registers. Offsets 800h-BFFh + The ifxusb_dev_global_regs structure defines the size + and relative field offsets for the Device Global registers. + These registers are visible only in Device mode and must not be + accessed in Host mode, as the results are unknown. + */ +typedef struct ifxusb_dev_global_regs +{ + volatile uint32_t dcfg; /*!< 800h Device Configuration Register. */ + volatile uint32_t dctl; /*!< 804h Device Control Register. */ + volatile uint32_t dsts; /*!< 808h Device Status Register (Read Only). */ + uint32_t unused; + volatile uint32_t diepmsk; /*!< 810h Device IN Endpoint Common Interrupt Mask Register. */ + volatile uint32_t doepmsk; /*!< 814h Device OUT Endpoint Common Interrupt Mask Register. */ + volatile uint32_t daint; /*!< 818h Device All Endpoints Interrupt Register. */ + volatile uint32_t daintmsk; /*!< 81Ch Device All Endpoints Interrupt Mask Register. */ + volatile uint32_t dtknqr1; /*!< 820h Device IN Token Queue Read Register-1 (Read Only). */ + volatile uint32_t dtknqr2; /*!< 824h Device IN Token Queue Read Register-2 (Read Only). */ + volatile uint32_t dvbusdis; /*!< 828h Device VBUS discharge Register.*/ + volatile uint32_t dvbuspulse; /*!< 82Ch Device VBUS Pulse Register. */ + volatile uint32_t dtknqr3_dthrctl; /*!< 830h Device IN Token Queue Read Register-3 (Read Only). + Device Thresholding control register (Read/Write) + */ + volatile uint32_t dtknqr4_fifoemptymsk; /*!< 834h Device IN Token Queue Read Register-4 (Read Only). + Device IN EPs empty Inr. Mask Register (Read/Write) + */ +} ifxusb_device_global_regs_t; + +/*! + \brief Bit fields in the Device Configuration Register. + */ + +typedef union dcfg_data +{ + uint32_t d32; + struct + { + unsigned reserved31_26 : 6; + unsigned perschintvl : 2; /*!< 25-24 Periodic Scheduling Interval */ + unsigned descdma : 1; /*!< 23 Enable Descriptor DMA in Device mode */ + unsigned epmscnt : 5; /*!< 22-18 In Endpoint Mis-match count */ + unsigned reserved13_17 : 5; + unsigned perfrint : 2; /*!< 12-11 Periodic Frame Interval */ + #define IFXUSB_DCFG_FRAME_INTERVAL_80 0 + #define IFXUSB_DCFG_FRAME_INTERVAL_85 1 + #define IFXUSB_DCFG_FRAME_INTERVAL_90 2 + #define IFXUSB_DCFG_FRAME_INTERVAL_95 3 + unsigned devaddr : 7; /*!< 10-04 Device Addresses */ + unsigned reserved3 : 1; + unsigned nzstsouthshk : 1; /*!< 02 Non Zero Length Status OUT Handshake */ + #define IFXUSB_DCFG_SEND_STALL 1 + unsigned devspd : 2; /*!< 01-00 Device Speed */ + } b; +} dcfg_data_t; + +/*! + \brief Bit fields in the Device Control Register. + */ +typedef union dctl_data +{ + uint32_t d32; + struct + { + unsigned reserved16_31 :16; + unsigned ifrmnum : 1; /*!< 15 Ignore Frame Number for ISOC EPs */ + unsigned gmc : 2; /*!< 14-13 Global Multi Count */ + unsigned gcontbna : 1; /*!< 12 Global Continue on BNA */ + unsigned pwronprgdone : 1; /*!< 11 Power-On Programming Done */ + unsigned cgoutnak : 1; /*!< 10 Clear Global OUT NAK */ + unsigned sgoutnak : 1; /*!< 09 Set Global OUT NAK */ + unsigned cgnpinnak : 1; /*!< 08 Clear Global Non-Periodic IN NAK */ + unsigned sgnpinnak : 1; /*!< 07 Set Global Non-Periodic IN NAK */ + unsigned tstctl : 3; /*!< 06-04 Test Control */ + unsigned goutnaksts : 1; /*!< 03 Global OUT NAK Status */ + unsigned gnpinnaksts : 1; /*!< 02 Global Non-Periodic IN NAK Status */ + unsigned sftdiscon : 1; /*!< 01 Soft Disconnect */ + unsigned rmtwkupsig : 1; /*!< 00 Remote Wakeup */ + } b; +} dctl_data_t; + + +/*! + \brief Bit fields in the Device Status Register. + */ +typedef union dsts_data +{ + uint32_t d32; + struct + { + unsigned reserved22_31 :10; + unsigned soffn :14; /*!< 21-08 Frame or Microframe Number of the received SOF */ + unsigned reserved4_7 : 4; + unsigned errticerr : 1; /*!< 03 Erratic Error */ + unsigned enumspd : 2; /*!< 02-01 Enumerated Speed */ + #define IFXUSB_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 + #define IFXUSB_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 + #define IFXUSB_DSTS_ENUMSPD_LS_PHY_6MHZ 2 + #define IFXUSB_DSTS_ENUMSPD_FS_PHY_48MHZ 3 + unsigned suspsts : 1; /*!< 00 Suspend Status */ + } b; +} dsts_data_t; + +/*! + \brief Bit fields in the Device IN EP Interrupt Register + and the Device IN EP Common Mask Register. + */ +typedef union diepint_data +{ + uint32_t d32; + struct + { + unsigned reserved14_31 :18; + unsigned nakmsk : 1; /*!< 13 NAK interrupt Mask */ + unsigned reserved10_12 : 3; + unsigned bna : 1; /*!< 09 BNA Interrupt mask */ + unsigned txfifoundrn : 1; /*!< 08 Fifo Underrun Mask */ + unsigned emptyintr : 1; /*!< 07 IN Endpoint HAK Effective mask */ + unsigned inepnakeff : 1; /*!< 06 IN Endpoint HAK Effective mask */ + unsigned intknepmis : 1; /*!< 05 IN Token Received with EP mismatch mask */ + unsigned intktxfemp : 1; /*!< 04 IN Token received with TxF Empty mask */ + unsigned timeout : 1; /*!< 03 TimeOUT Handshake mask (non-ISOC EPs) */ + unsigned ahberr : 1; /*!< 02 AHB Error mask */ + unsigned epdisabled : 1; /*!< 01 Endpoint disable mask */ + unsigned xfercompl : 1; /*!< 00 Transfer complete mask */ + } b; +} diepint_data_t; + + +/*! + \brief Bit fields in the Device OUT EP Interrupt Register and + Device OUT EP Common Interrupt Mask Register. + */ +typedef union doepint_data +{ + uint32_t d32; + struct + { + unsigned reserved15_31 :17; + unsigned nyetmsk : 1; /*!< 14 NYET Interrupt */ + unsigned nakmsk : 1; /*!< 13 NAK Interrupt */ + unsigned bbleerrmsk : 1; /*!< 12 Babble Interrupt */ + unsigned reserved10_11 : 2; + unsigned bna : 1; /*!< 09 BNA Interrupt */ + unsigned outpkterr : 1; /*!< 08 OUT packet Error */ + unsigned reserved07 : 1; + unsigned back2backsetup : 1; /*!< 06 Back-to-Back SETUP Packets Received */ + unsigned stsphsercvd : 1; /*!< 05 */ + unsigned outtknepdis : 1; /*!< 04 OUT Token Received when Endpoint Disabled */ + unsigned setup : 1; /*!< 03 Setup Phase Done (contorl EPs) */ + unsigned ahberr : 1; /*!< 02 AHB Error */ + unsigned epdisabled : 1; /*!< 01 Endpoint disable */ + unsigned xfercompl : 1; /*!< 00 Transfer complete */ + } b; +} doepint_data_t; + + +/*! + \brief Bit fields in the Device All EP Interrupt Registers. + */ +typedef union daint_data +{ + uint32_t d32; + struct + { + unsigned out : 16; /*!< 31-16 OUT Endpoint bits */ + unsigned in : 16; /*!< 15-00 IN Endpoint bits */ + } eps; + struct + { + /** OUT Endpoint bits */ + unsigned outep15 : 1; + unsigned outep14 : 1; + unsigned outep13 : 1; + unsigned outep12 : 1; + unsigned outep11 : 1; + unsigned outep10 : 1; + unsigned outep09 : 1; + unsigned outep08 : 1; + unsigned outep07 : 1; + unsigned outep06 : 1; + unsigned outep05 : 1; + unsigned outep04 : 1; + unsigned outep03 : 1; + unsigned outep02 : 1; + unsigned outep01 : 1; + unsigned outep00 : 1; + /** IN Endpoint bits */ + unsigned inep15 : 1; + unsigned inep14 : 1; + unsigned inep13 : 1; + unsigned inep12 : 1; + unsigned inep11 : 1; + unsigned inep10 : 1; + unsigned inep09 : 1; + unsigned inep08 : 1; + unsigned inep07 : 1; + unsigned inep06 : 1; + unsigned inep05 : 1; + unsigned inep04 : 1; + unsigned inep03 : 1; + unsigned inep02 : 1; + unsigned inep01 : 1; + unsigned inep00 : 1; + } ep; +} daint_data_t; + + +/*! + \brief Bit fields in the Device IN Token Queue Read Registers. + */ +typedef union dtknq1_data +{ + uint32_t d32; + struct + { + unsigned epnums0_5 :24; /*!< 31-08 EP Numbers of IN Tokens 0 ... 4 */ + unsigned wrap_bit : 1; /*!< 07 write pointer has wrapped */ + unsigned reserved05_06 : 2; + unsigned intknwptr : 5; /*!< 04-00 In Token Queue Write Pointer */ + }b; +} dtknq1_data_t; + + +/*! + \brief Bit fields in Threshold control Register + */ +typedef union dthrctl_data +{ + uint32_t d32; + struct + { + unsigned reserved26_31 : 6; + unsigned rx_thr_len : 9; /*!< 25-17 Rx Thr. Length */ + unsigned rx_thr_en : 1; /*!< 16 Rx Thr. Enable */ + unsigned reserved11_15 : 5; + unsigned tx_thr_len : 9; /*!< 10-02 Tx Thr. Length */ + unsigned iso_thr_en : 1; /*!< 01 ISO Tx Thr. Enable */ + unsigned non_iso_thr_en : 1; /*!< 00 non ISO Tx Thr. Enable */ + } b; +} dthrctl_data_t; + +/*@}*//*IFXUSB_CSR_DEVICE_GLOBAL_REG*/ + +/****************************************************************************/ + +/*! + \addtogroup IFXUSB_CSR_DEVICE_EP_REG + */ +/*@{*/ + +/*! + \struct ifxusb_dev_in_ep_regs + \brief Device Logical IN Endpoint-Specific Registers. + There will be one set of endpoint registers per logical endpoint + implemented. + each EP's IN EP Register are offset at : + 900h + * (ep_num * 20h) + */ + +typedef struct ifxusb_dev_in_ep_regs +{ + volatile uint32_t diepctl; /*!< 00h: Endpoint Control Register */ + uint32_t reserved04; /*!< 04h: */ + volatile uint32_t diepint; /*!< 08h: Endpoint Interrupt Register */ + uint32_t reserved0C; /*!< 0Ch: */ + volatile uint32_t dieptsiz; /*!< 10h: Endpoint Transfer Size Register.*/ + volatile uint32_t diepdma; /*!< 14h: Endpoint DMA Address Register. */ + volatile uint32_t dtxfsts; /*!< 18h: Endpoint Transmit FIFO Status Register. */ + volatile uint32_t diepdmab; /*!< 1Ch: Endpoint DMA Buffer Register. */ +} ifxusb_dev_in_ep_regs_t; + +/*! + \brief Device Logical OUT Endpoint-Specific Registers. + There will be one set of endpoint registers per logical endpoint + implemented. + each EP's OUT EP Register are offset at : + B00h + * (ep_num * 20h) + 00h + */ +typedef struct ifxusb_dev_out_ep_regs +{ + volatile uint32_t doepctl; /*!< 00h: Endpoint Control Register */ + volatile uint32_t doepfn; /*!< 04h: Endpoint Frame number Register */ + volatile uint32_t doepint; /*!< 08h: Endpoint Interrupt Register */ + uint32_t reserved0C; /*!< 0Ch: */ + volatile uint32_t doeptsiz; /*!< 10h: Endpoint Transfer Size Register.*/ + volatile uint32_t doepdma; /*!< 14h: Endpoint DMA Address Register. */ + uint32_t reserved18; /*!< 18h: */ + volatile uint32_t doepdmab; /*!< 1Ch: Endpoint DMA Buffer Register. */ +} ifxusb_dev_out_ep_regs_t; + + +/*! + \brief Bit fields in the Device EP Control + Register. + */ +typedef union depctl_data +{ + uint32_t d32; + struct + { + unsigned epena : 1; /*!< 31 Endpoint Enable */ + unsigned epdis : 1; /*!< 30 Endpoint Disable */ + unsigned setd1pid : 1; /*!< 29 Set DATA1 PID (INTR/Bulk IN and OUT endpoints) */ + unsigned setd0pid : 1; /*!< 28 Set DATA0 PID (INTR/Bulk IN and OUT endpoints) */ + unsigned snak : 1; /*!< 27 Set NAK */ + unsigned cnak : 1; /*!< 26 Clear NAK */ + unsigned txfnum : 4; /*!< 25-22 Tx Fifo Number */ + unsigned stall : 1; /*!< 21 Stall Handshake */ + unsigned snp : 1; /*!< 20 Snoop Mode */ + unsigned eptype : 2; /*!< 19-18 Endpoint Type + 0: Control + 1: Isochronous + 2: Bulk + 3: Interrupt + */ + unsigned naksts : 1; /*!< 17 NAK Status */ + unsigned dpid : 1; /*!< 16 Endpoint DPID (INTR/Bulk IN and OUT endpoints) */ + unsigned usbactep : 1; /*!< 15 USB Active Endpoint */ + unsigned nextep : 4; /*!< 14-11 Next Endpoint */ + unsigned mps :11; /*!< 10-00 Maximum Packet Size */ + #define IFXUSB_DEP0CTL_MPS_64 0 + #define IFXUSB_DEP0CTL_MPS_32 1 + #define IFXUSB_DEP0CTL_MPS_16 2 + #define IFXUSB_DEP0CTL_MPS_8 3 + } b; +} depctl_data_t; + + +/*! + \brief Bit fields in the Device EP Transfer Size Register. (EP0 and EPn) + */ +typedef union deptsiz_data +{ + uint32_t d32; + struct + { + unsigned reserved31 : 1; + unsigned supcnt : 2; /*!< 30-29 Setup Packet Count */ + unsigned reserved20_28 : 9; + unsigned pktcnt : 1; /*!< 19 Packet Count */ + unsigned reserved7_18 :12; + unsigned xfersize : 7; /*!< 06-00 Transfer size */ + }b0; + struct + { + unsigned reserved : 1; + unsigned mc : 2; /*!< 30-29 Multi Count */ + unsigned pktcnt :10; /*!< 28-19 Packet Count */ + unsigned xfersize :19; /*!< 18-00 Transfer size */ + } b; +} deptsiz_data_t; + +/*@}*//*IFXUSB_CSR_DEVICE_EP_REG*/ +/****************************************************************************/ + +/*! + \addtogroup IFXUSB_CSR_DEVICE_DMA_DESC + */ +/*@{*/ +/*! + \struct desc_sts_data + \brief Bit fields in the DMA Descriptor status quadlet. + */ +typedef union desc_sts_data +{ + struct + { + unsigned bs : 2; /*!< 31-30 Buffer Status */ + #define BS_HOST_READY 0x0 + #define BS_DMA_BUSY 0x1 + #define BS_DMA_DONE 0x2 + #define BS_HOST_BUSY 0x3 + unsigned sts : 2; /*!< 29-28 Receive/Trasmit Status */ + #define RTS_SUCCESS 0x0 + #define RTS_BUFFLUSH 0x1 + #define RTS_RESERVED 0x2 + #define RTS_BUFERR 0x3 + unsigned l : 1; /*!< 27 Last */ + unsigned sp : 1; /*!< 26 Short Packet */ + unsigned ioc : 1; /*!< 25 Interrupt On Complete */ + unsigned sr : 1; /*!< 24 Setup Packet received */ + unsigned mtrf : 1; /*!< 23 Multiple Transfer */ + unsigned reserved16_22 : 7; + unsigned bytes :16; /*!< 15-00 Transfer size in bytes */ + } b; + uint32_t d32; /*!< DMA Descriptor data buffer pointer */ +} desc_sts_data_t; + +/*@}*//*IFXUSB_CSR_DEVICE_DMA_DESC*/ +/****************************************************************************/ + +/*! + \addtogroup IFXUSB_CSR_HOST_GLOBAL_REG + */ +/*@{*/ +/*! + \struct ifxusb_host_global_regs + \brief IFXUSB Host Mode Global registers. Offsets 400h-7FFh + The ifxusb_host_global_regs structure defines the size + and relative field offsets for the Host Global registers. + These registers are visible only in Host mode and must not be + accessed in Device mode, as the results are unknown. + */ +typedef struct ifxusb_host_global_regs +{ + volatile uint32_t hcfg; /*!< 400h Host Configuration Register. */ + volatile uint32_t hfir; /*!< 404h Host Frame Interval Register. */ + volatile uint32_t hfnum; /*!< 408h Host Frame Number / Frame Remaining Register. */ + uint32_t reserved40C; + volatile uint32_t hptxsts; /*!< 410h Host Periodic Transmit FIFO/ Queue Status Register. */ + volatile uint32_t haint; /*!< 414h Host All Channels Interrupt Register. */ + volatile uint32_t haintmsk; /*!< 418h Host All Channels Interrupt Mask Register. */ +} ifxusb_host_global_regs_t; + +/*! + \brief Bit fields in the Host Configuration Register. + */ +typedef union hcfg_data +{ + uint32_t d32; + struct + { + unsigned reserved31_03 :29; + unsigned fslssupp : 1; /*!< 02 FS/LS Only Support */ + unsigned fslspclksel : 2; /*!< 01-00 FS/LS Phy Clock Select */ + #define IFXUSB_HCFG_30_60_MHZ 0 + #define IFXUSB_HCFG_48_MHZ 1 + #define IFXUSB_HCFG_6_MHZ 2 + } b; +} hcfg_data_t; + +/*! + \brief Bit fields in the Host Frame Interval Register. + */ +typedef union hfir_data +{ + uint32_t d32; + struct + { + unsigned reserved : 16; + unsigned frint : 16; /*!< 15-00 Frame Interval */ + } b; +} hfir_data_t; + +/*! + \brief Bit fields in the Host Frame Time Remaing/Number Register. + */ +typedef union hfnum_data +{ + uint32_t d32; + struct + { + unsigned frrem : 16; /*!< 31-16 Frame Time Remaining */ + unsigned frnum : 16; /*!< 15-00 Frame Number*/ + #define IFXUSB_HFNUM_MAX_FRNUM 0x3FFF + } b; +} hfnum_data_t; + +/*! + \brief Bit fields in the Host Periodic Transmit FIFO/Queue Status Register + */ +typedef union hptxsts_data +{ + /** raw register data */ + uint32_t d32; + struct + { + /** Top of the Periodic Transmit Request Queue + * - bit 24 - Terminate (last entry for the selected channel) + */ + unsigned ptxqtop_odd : 1; /*!< 31 Top of the Periodic Transmit Request + Queue Odd/even microframe*/ + unsigned ptxqtop_chnum : 4; /*!< 30-27 Top of the Periodic Transmit Request + Channel Number */ + unsigned ptxqtop_token : 2; /*!< 26-25 Top of the Periodic Transmit Request + Token Type + 0 - Zero length + 1 - Ping + 2 - Disable + */ + unsigned ptxqtop_terminate : 1; /*!< 24 Top of the Periodic Transmit Request + Terminate (last entry for the selected channel)*/ + unsigned ptxqspcavail : 8; /*!< 23-16 Periodic Transmit Request Queue Space Available */ + unsigned ptxfspcavail :16; /*!< 15-00 Periodic Transmit Data FIFO Space Available */ + } b; +} hptxsts_data_t; + +/*! + \brief Bit fields in the Host Port Control and Status Register. + */ +typedef union hprt0_data +{ + uint32_t d32; + struct + { + unsigned reserved19_31 :13; + unsigned prtspd : 2; /*!< 18-17 Port Speed */ + #define IFXUSB_HPRT0_PRTSPD_HIGH_SPEED 0 + #define IFXUSB_HPRT0_PRTSPD_FULL_SPEED 1 + #define IFXUSB_HPRT0_PRTSPD_LOW_SPEED 2 + unsigned prttstctl : 4; /*!< 16-13 Port Test Control */ + unsigned prtpwr : 1; /*!< 12 Port Power */ + unsigned prtlnsts : 2; /*!< 11-10 Port Line Status */ + unsigned reserved9 : 1; + unsigned prtrst : 1; /*!< 08 Port Reset */ + unsigned prtsusp : 1; /*!< 07 Port Suspend */ + unsigned prtres : 1; /*!< 06 Port Resume */ + unsigned prtovrcurrchng : 1; /*!< 05 Port Overcurrent Change */ + unsigned prtovrcurract : 1; /*!< 04 Port Overcurrent Active */ + unsigned prtenchng : 1; /*!< 03 Port Enable/Disable Change */ + unsigned prtena : 1; /*!< 02 Port Enable */ + unsigned prtconndet : 1; /*!< 01 Port Connect Detected */ + unsigned prtconnsts : 1; /*!< 00 Port Connect Status */ + }b; +} hprt0_data_t; + +/*! + \brief Bit fields in the Host All Interrupt Register. + */ +typedef union haint_data +{ + uint32_t d32; + struct + { + unsigned reserved : 16; + unsigned ch15 : 1; + unsigned ch14 : 1; + unsigned ch13 : 1; + unsigned ch12 : 1; + unsigned ch11 : 1; + unsigned ch10 : 1; + unsigned ch09 : 1; + unsigned ch08 : 1; + unsigned ch07 : 1; + unsigned ch06 : 1; + unsigned ch05 : 1; + unsigned ch04 : 1; + unsigned ch03 : 1; + unsigned ch02 : 1; + unsigned ch01 : 1; + unsigned ch00 : 1; + } b; + struct + { + unsigned reserved : 16; + unsigned chint : 16; + } b2; +} haint_data_t; +/*@}*//*IFXUSB_CSR_HOST_GLOBAL_REG*/ +/****************************************************************************/ +/*! + \addtogroup IFXUSB_CSR_HOST_HC_REG + */ +/*@{*/ +/*! + \brief Host Channel Specific Registers + There will be one set of hc registers per host channelimplemented. + each HC's Register are offset at : + 500h + * (hc_num * 20h) + */ +typedef struct ifxusb_hc_regs +{ + volatile uint32_t hcchar; /*!< 00h Host Channel Characteristic Register.*/ + volatile uint32_t hcsplt; /*!< 04h Host Channel Split Control Register.*/ + volatile uint32_t hcint; /*!< 08h Host Channel Interrupt Register. */ + volatile uint32_t hcintmsk; /*!< 0Ch Host Channel Interrupt Mask Register. */ + volatile uint32_t hctsiz; /*!< 10h Host Channel Transfer Size Register. */ + volatile uint32_t hcdma; /*!< 14h Host Channel DMA Address Register. */ + uint32_t reserved[2]; /*!< 18h Reserved. */ +} ifxusb_hc_regs_t; + + +/*! + \brief Bit fields in the Host Channel Characteristics Register. + */ +typedef union hcchar_data +{ + uint32_t d32; + struct + { + unsigned chen : 1; /*!< 31 Channel enable */ + unsigned chdis : 1; /*!< 30 Channel disable */ + unsigned oddfrm : 1; /*!< 29 Frame to transmit periodic transaction */ + unsigned devaddr : 7; /*!< 28-22 Device address */ + unsigned multicnt : 2; /*!< 21-20 Packets per frame for periodic transfers */ + unsigned eptype : 2; /*!< 19-18 0: Control, 1: Isoc, 2: Bulk, 3: Intr */ + unsigned lspddev : 1; /*!< 17 0: Full/high speed device, 1: Low speed device */ + unsigned reserved : 1; + unsigned epdir : 1; /*!< 15 0: OUT, 1: IN */ + unsigned epnum : 4; /*!< 14-11 Endpoint number */ + unsigned mps :11; /*!< 10-00 Maximum packet size in bytes */ + } b; +} hcchar_data_t; + +/*! + \brief Bit fields in the Host Channel Split Control Register + */ +typedef union hcsplt_data +{ + uint32_t d32; + struct + { + unsigned spltena : 1; /*!< 31 Split Enble */ + unsigned reserved :14; + unsigned compsplt : 1; /*!< 16 Do Complete Split */ + unsigned xactpos : 2; /*!< 15-14 Transaction Position */ + #define IFXUSB_HCSPLIT_XACTPOS_MID 0 + #define IFXUSB_HCSPLIT_XACTPOS_END 1 + #define IFXUSB_HCSPLIT_XACTPOS_BEGIN 2 + #define IFXUSB_HCSPLIT_XACTPOS_ALL 3 + unsigned hubaddr : 7; /*!< 13-07 Hub Address */ + unsigned prtaddr : 7; /*!< 06-00 Port Address */ + } b; +} hcsplt_data_t; + +/*! + \brief Bit fields in the Host Interrupt Register. + */ +typedef union hcint_data +{ + uint32_t d32; + struct + { + unsigned reserved :21; + unsigned datatglerr : 1; /*!< 10 Data Toggle Error */ + unsigned frmovrun : 1; /*!< 09 Frame Overrun */ + unsigned bblerr : 1; /*!< 08 Babble Error */ + unsigned xacterr : 1; /*!< 07 Transaction Err */ + unsigned nyet : 1; /*!< 06 NYET Response Received */ + unsigned ack : 1; /*!< 05 ACK Response Received */ + unsigned nak : 1; /*!< 04 NAK Response Received */ + unsigned stall : 1; /*!< 03 STALL Response Received */ + unsigned ahberr : 1; /*!< 02 AHB Error */ + unsigned chhltd : 1; /*!< 01 Channel Halted */ + unsigned xfercomp : 1; /*!< 00 Channel Halted */ + }b; +} hcint_data_t; + + +/*! + \brief Bit fields in the Host Channel Transfer Size + Register. + */ +typedef union hctsiz_data +{ + uint32_t d32; + struct + { + /** */ + unsigned dopng : 1; /*!< 31 Do PING protocol when 1 */ + /** + * Packet ID for next data packet + * 0: DATA0 + * 1: DATA2 + * 2: DATA1 + * 3: MDATA (non-Control), SETUP (Control) + */ + unsigned pid : 2; /*!< 30-29 Packet ID for next data packet + 0: DATA0 + 1: DATA2 + 2: DATA1 + 3: MDATA (non-Control), SETUP (Control) + */ + #define IFXUSB_HCTSIZ_DATA0 0 + #define IFXUSB_HCTSIZ_DATA1 2 + #define IFXUSB_HCTSIZ_DATA2 1 + #define IFXUSB_HCTSIZ_MDATA 3 + #define IFXUSB_HCTSIZ_SETUP 3 + unsigned pktcnt :10; /*!< 28-19 Data packets to transfer */ + unsigned xfersize :19; /*!< 18-00 Total transfer size in bytes */ + }b; +} hctsiz_data_t; + +/*@}*//*IFXUSB_CSR_HOST_HC_REG*/ + +/****************************************************************************/ + +/*! + \addtogroup IFXUSB_CSR_PWR_CLK_GATING_REG + */ +/*@{*/ +/*! + \brief Bit fields in the Power and Clock Gating Control Register + */ +typedef union pcgcctl_data +{ + uint32_t d32; + struct + { + unsigned reserved : 27; + unsigned physuspended : 1; /*!< 04 PHY Suspended */ + unsigned rstpdwnmodule : 1; /*!< 03 Reset Power Down Modules */ + unsigned pwrclmp : 1; /*!< 02 Power Clamp */ + unsigned gatehclk : 1; /*!< 01 Gate Hclk */ + unsigned stoppclk : 1; /*!< 00 Stop Pclk */ + } b; +} pcgcctl_data_t; +/*@}*//*IFXUSB_CSR_PWR_CLK_GATING_REG*/ + +/****************************************************************************/ + +#endif //__IFXUSB_REGS_H__ diff --git a/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_version.h b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_version.h new file mode 100644 index 0000000000..2dff7354e5 --- /dev/null +++ b/target/linux/lantiq/files/drivers/usb/ifxhcd/ifxusb_version.h @@ -0,0 +1,5 @@ + +#ifndef IFXUSB_VERSION +#define IFXUSB_VERSION "3.0alpha B100312" +#endif + diff --git a/target/linux/lantiq/files/include/linux/svip_nat.h b/target/linux/lantiq/files/include/linux/svip_nat.h new file mode 100644 index 0000000000..6563c38d58 --- /dev/null +++ b/target/linux/lantiq/files/include/linux/svip_nat.h @@ -0,0 +1,37 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + Am Campeon 1-12; 81726 Munich, Germany + + THE DELIVERY OF THIS SOFTWARE AS WELL AS THE HEREBY GRANTED NON-EXCLUSIVE, + WORLDWIDE LICENSE TO USE, COPY, MODIFY, DISTRIBUTE AND SUBLICENSE THIS + SOFTWARE IS FREE OF CHARGE. + + THE LICENSED SOFTWARE IS PROVIDED "AS IS" AND INFINEON EXPRESSLY DISCLAIMS + ALL REPRESENTATIONS AND WARRANTIES, WHETHER EXPRESS OR IMPLIED, INCLUDING + WITHOUT LIMITATION, WARRANTIES OR REPRESENTATIONS OF WORKMANSHIP, + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, DURABILITY, THAT THE + OPERATING OF THE LICENSED SOFTWARE WILL BE ERROR FREE OR FREE OF ANY THIRD + PARTY CLAIMS, INCLUDING WITHOUT LIMITATION CLAIMS OF THIRD PARTY INTELLECTUAL + PROPERTY INFRINGEMENT. + + EXCEPT FOR ANY LIABILITY DUE TO WILFUL ACTS OR GROSS NEGLIGENCE AND EXCEPT + FOR ANY PERSONAL INJURY INFINEON SHALL IN NO EVENT BE LIABLE FOR ANY CLAIM + OR DAMAGES OF ANY KIND, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. +*******************************************************************************/ +#ifndef _SVIP_NAT_H +#define _SVIP_NAT_H + +/* The declarations here have to be in a header file, because + * they need to be known both to the kernel module + * (in chardev.c) and the process calling ioctl (ioctl.c) + */ +#include + +#define SVIP_NAT_VERSION "3.1" +extern int do_SVIP_NAT(struct sk_buff *); + +#endif diff --git a/target/linux/lantiq/files/include/linux/svip_nat_io.h b/target/linux/lantiq/files/include/linux/svip_nat_io.h new file mode 100644 index 0000000000..bf42dd4ee3 --- /dev/null +++ b/target/linux/lantiq/files/include/linux/svip_nat_io.h @@ -0,0 +1,103 @@ +/****************************************************************************** + + Copyright (c) 2007 + Infineon Technologies AG + Am Campeon 1-12; 81726 Munich, Germany + + THE DELIVERY OF THIS SOFTWARE AS WELL AS THE HEREBY GRANTED NON-EXCLUSIVE, + WORLDWIDE LICENSE TO USE, COPY, MODIFY, DISTRIBUTE AND SUBLICENSE THIS + SOFTWARE IS FREE OF CHARGE. + + THE LICENSED SOFTWARE IS PROVIDED "AS IS" AND INFINEON EXPRESSLY DISCLAIMS + ALL REPRESENTATIONS AND WARRANTIES, WHETHER EXPRESS OR IMPLIED, INCLUDING + WITHOUT LIMITATION, WARRANTIES OR REPRESENTATIONS OF WORKMANSHIP, + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, DURABILITY, THAT THE + OPERATING OF THE LICENSED SOFTWARE WILL BE ERROR FREE OR FREE OF ANY THIRD + PARTY CLAIMS, INCLUDING WITHOUT LIMITATION CLAIMS OF THIRD PARTY INTELLECTUAL + PROPERTY INFRINGEMENT. + + EXCEPT FOR ANY LIABILITY DUE TO WILFUL ACTS OR GROSS NEGLIGENCE AND EXCEPT + FOR ANY PERSONAL INJURY INFINEON SHALL IN NO EVENT BE LIABLE FOR ANY CLAIM + OR DAMAGES OF ANY KIND, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + *******************************************************************************/ +#ifndef _SVIP_NAT_IO_H_ +#define _SVIP_NAT_IO_H_ + +#include + +#define SVIP_NAT_DEVICE_NAME "svip_nat" +#define PATH_SVIP_NAT_DEVICE_NAME "/dev/"SVIP_NAT_DEVICE_NAME + +#define MAJOR_NUM_SVIP_NAT 10 +#define MINOR_NUM_SVIP_NAT 120 + +/** maximum SVIP devices supported on a Line card system */ +#define SVIP_SYS_NUM 12 + +/** maximum voice packet channels possible per SVIP device */ +#define SVIP_CODEC_NUM 16 + +/** start UDP port number of the SVIP Linecard System */ +#define SVIP_UDP_FROM 50000 + +/** @defgroup SVIP_NATAPI SVIP Custom NAT ioctl interface. + An ioctl interface is provided to add a rule into the SVIP NAT table and + to respectively remove the rule form it. The ioctl interface is accessible + using the fd issued upon opening the special device node /dev/svip_nat. + @{ */ + +/** Used to add a new rule to the SVIP Custom NAT table. If a rule already + exists for the target UDP port, that rule shall be overwritten. + + \param SVIP_NAT_IO_Rule_t* The parameter points to a + \ref SVIP_NAT_IO_Rule_t structure. + */ +#define FIO_SVIP_NAT_RULE_ADD \ + _IOW(MAJOR_NUM_SVIP_NAT, 1, SVIP_NAT_IO_Rule_t) + +/** Used to remove a rule from the SVIP Custom NAT table. No check is + performed whether the rule already exists or not. The remove operation is + performed as long as the target UDP port is within the defined port range. + + \param SVIP_NAT_IO_Rule_t* The parameter points to a + \ref SVIP_NAT_IO_Rule_t structure. + */ +#define FIO_SVIP_NAT_RULE_REMOVE \ + _IOW(MAJOR_NUM_SVIP_NAT, 2, SVIP_NAT_IO_Rule_t) + +/** Used to list all rules in the SVIP Custom NAT table. + + \param + */ +#define FIO_SVIP_NAT_RULE_LIST \ + _IO(MAJOR_NUM_SVIP_NAT, 3) + +/** IP address in network-byte order */ +typedef u32 SVIP_IP_ADDR_t; +/** UDP port in network-byte order */ +typedef u16 SVIP_UDP_PORT_t; + +#ifndef ETH_ALEN +#define ETH_ALEN 6 /* Octets in one ethernet address */ +#endif + +/** NAT parameters part of the NAT table. + These paramters are configurable through the NAT API. */ +typedef struct SVIP_NAT_IO_Rule +{ + /** Remote peer, IP address */ + SVIP_IP_ADDR_t remIP; + /** Remote peer, MAC address */ + u8 remMAC[ETH_ALEN]; + /** Target SVIP, IP address (local peer) */ + SVIP_IP_ADDR_t locIP; + /** Target SVIP, MAC address */ + u8 locMAC[ETH_ALEN]; + /** Target SVIP, UDP port number */ + SVIP_UDP_PORT_t locUDP; +} SVIP_NAT_IO_Rule_t; + +/** @} */ +#endif diff --git a/target/linux/lantiq/files/net/ipv4/svip_nat.c b/target/linux/lantiq/files/net/ipv4/svip_nat.c new file mode 100644 index 0000000000..04a0d223a2 --- /dev/null +++ b/target/linux/lantiq/files/net/ipv4/svip_nat.c @@ -0,0 +1,1569 @@ +/****************************************************************************** + + Copyright (c) 2009 + Lantiq Deutschland GmbH + Am Campeon 3; 81726 Munich, Germany + + THE DELIVERY OF THIS SOFTWARE AS WELL AS THE HEREBY GRANTED NON-EXCLUSIVE, + WORLDWIDE LICENSE TO USE, COPY, MODIFY, DISTRIBUTE AND SUBLICENSE THIS + SOFTWARE IS FREE OF CHARGE. + + THE LICENSED SOFTWARE IS PROVIDED "AS IS" AND INFINEON EXPRESSLY DISCLAIMS + ALL REPRESENTATIONS AND WARRANTIES, WHETHER EXPRESS OR IMPLIED, INCLUDING + WITHOUT LIMITATION, WARRANTIES OR REPRESENTATIONS OF WORKMANSHIP, + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, DURABILITY, THAT THE + OPERATING OF THE LICENSED SOFTWARE WILL BE ERROR FREE OR FREE OF ANY THIRD + PARTY CLAIMS, INCLUDING WITHOUT LIMITATION CLAIMS OF THIRD PARTY INTELLECTUAL + PROPERTY INFRINGEMENT. + + EXCEPT FOR ANY LIABILITY DUE TO WILFUL ACTS OR GROSS NEGLIGENCE AND EXCEPT + FOR ANY PERSONAL INJURY INFINEON SHALL IN NO EVENT BE LIABLE FOR ANY CLAIM + OR DAMAGES OF ANY KIND, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + + **************************************************************************** + +Description : This file contains implementation of Custom NAT function +for Infineon's VINETIC-SVIP16 + *******************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /* just to shut up a warning */ +#include +#include + +#include + +MODULE_AUTHOR("Lantiq Deutschland GmbH"); +MODULE_DESCRIPTION("SVIP Network Address Translation module"); +MODULE_LICENSE("GPL"); + +#define SVIP_NAT_INFO_STR "@(#)SVIP NAT, version "SVIP_NAT_VERSION + +/** maximum voice packet channels possible on the SVIP LC system + (equals maximum number of Codec channels possible) */ +#define SVIP_SYS_CODEC_NUM ((SVIP_SYS_NUM) * (SVIP_CODEC_NUM)) + +/** end UDP port number of the SVIP Linecard System */ +#define SVIP_UDP_TO ((SVIP_UDP_FROM) + (SVIP_SYS_CODEC_NUM) - 1) + +/** end UDP port number of the Master SVIP in SVIP Linecard System */ +#define SVIP_UDP_TO_VOFW0 ((SVIP_UDP_FROM) + (SVIP_CODEC_NUM) - 1) + +#define SVIP_PORT_INRANGE(nPort) \ + ((nPort) >= (SVIP_UDP_FROM) && (nPort) <= (SVIP_UDP_TO)) + +#define SVIP_PORT_INDEX(nPort) (nPort - SVIP_UDP_FROM) + +#define SVIP_NET_DEV_ETH0_IDX 0 +#define SVIP_NET_DEV_VETH0_IDX 1 +#define SVIP_NET_DEV_LO_IDX 2 + +#define SVIP_NET_DEV_ETH0_NAME "eth0" +#define SVIP_NET_DEV_ETH1_NAME "eth1" +#define SVIP_NET_DEV_VETH1_NAME "veth0" +#define SVIP_NET_DEV_LO_NAME "lo" + +#define SVIP_NAT_STATS_LOC2REM 0 +#define SVIP_NAT_STATS_REM2LOC 1 +#define SVIP_NAT_STATS_TYPES 2 + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) +#define SVIP_NAT_FOR_EACH_NETDEV(d) for_each_netdev(&init_net, dev) +#define SVIP_NAT_IP_HDR(ethhdr) ip_hdr(ethhdr) +#else +#define SVIP_NAT_FOR_EACH_NETDEV(d) for(d=dev_base; dev; dev = dev->next) +#define SVIP_NAT_IP_HDR(ethhdr) (ethhdr)->nh.iph +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) +#define SVIP_NAT_SKB_MAC_HEADER(ethhdr) (ethhdr)->mac.ethernet +#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) +#define SVIP_NAT_SKB_MAC_HEADER(ethhdr) (ethhdr)->mac.raw +#else +#define SVIP_NAT_SKB_MAC_HEADER(ethhdr) skb_mac_header(ethhdr) +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) +#define VLAN_DEV_REAL_DEV(dev) vlan_dev_real_dev(dev) +#define VLAN_DEV_VLAN_ID(dev) vlan_dev_vlan_id(dev) +#else +#define VLAN_DEV_REAL_DEV(dev) (VLAN_DEV_INFO(dev)->real_dev) +#define VLAN_DEV_VLAN_ID(dev) (VLAN_DEV_INFO(dev)->vlan_id) +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) */ + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) +#define MOD_INC_USE_COUNT +#define MOD_DEC_USE_COUNT +#endif + +#if ! ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) && \ + (defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE))) +#define VLAN_8021Q_UNUSED +#endif + + +extern spinlock_t vlan_group_lock; +extern struct net_device *__vlan_find_dev_deep(struct net_device *real_dev, unsigned short VID); + +typedef struct SVIP_NAT_stats +{ + unsigned long inPackets; + unsigned long outPackets; + unsigned long outErrors; +} SVIP_NAT_stats_t; + +typedef struct SVIP_NAT_table_entry +{ + SVIP_NAT_IO_Rule_t natRule; + SVIP_NAT_stats_t natStats[SVIP_NAT_STATS_TYPES]; +} SVIP_NAT_table_entry_t; + +/* pointer to the SVIP NAT table */ +static SVIP_NAT_table_entry_t *pNatTable = NULL; + +struct net_device *net_devs[3]; +static u32 *paddr_eth0; +static u32 *paddr_eth0_0; +static u32 *paddr_veth0; +static u32 *pmask_veth0; + +static struct semaphore *sem_nat_tbl_access; +static int proc_read_in_progress = 0; + +static int nDeviceOpen = 0; + +/* saves the NAT table index between subsequent invocation */ +static int nProcReadIdx = 0; + +static long SVIP_NAT_device_ioctl(struct file *,unsigned int ,unsigned long); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0) +static int SVIP_NAT_device_release (struct inode *,struct file *); +#else +static void SVIP_NAT_device_release (struct inode *,struct file *); +#endif +static int SVIP_NAT_device_open (struct inode *,struct file *); + +/* This structure holds the interface functions supported by + the SVIP NAT configuration device. */ +struct file_operations SVIP_NAT_Fops = { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) +owner: THIS_MODULE, +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) */ + llseek: NULL, /* seek */ + read: NULL, + write: NULL, + readdir: NULL, /* readdir */ + poll: NULL, /* select */ + unlocked_ioctl: SVIP_NAT_device_ioctl, /* ioctl */ + mmap: NULL, /* mmap */ + open: SVIP_NAT_device_open, /* open, */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0) + flush: NULL, /* flush */ +#endif + release: SVIP_NAT_device_release /* close */ +}; + +/** Structure holding MISC module operations */ +static struct miscdevice SVIP_NAT_miscdev = +{ +minor: MINOR_NUM_SVIP_NAT, + name: SVIP_NAT_DEVICE_NAME, + fops: &SVIP_NAT_Fops +}; + +#ifdef CONFIG_SVIP_FW_PKT_SNIFFER +int nSVIP_NAT_Sniffer; +unsigned char pSVIP_NAT_SnifferMAC[ETH_ALEN]; +int nSVIP_NAT_SnifferMacSet; +#endif + +/******************************************************************************/ +/** + Function to read /proc/net/svip_nat/nat proc entry + + \arguments + page - pointer to page buffer + start - pointer to start address pointer + off - offset + count - maximum data length to read + eof - end of file flag + data - proc read data (provided by the function + pointed to by data) + + \return + length of read data + + \remarks: + Each call of this routine forces a copy_to_user of the data returned by + 'fn'. This routine will be called by the user until 'len = 0'. + ****************************************************************************/ +static int SVIP_NAT_ProcRead (char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + unsigned long flags; + int (*fn)(char *buf, int size); + int len; + + /* If the NAT table index is negative, the reading has completed */ + if (nProcReadIdx < 0) + { + nProcReadIdx = 0; + *eof = 1; + proc_read_in_progress = 0; + up(sem_nat_tbl_access); + return 0; + } + + local_irq_save(flags); + if (!proc_read_in_progress) + { + proc_read_in_progress = 1; + local_irq_restore(flags); + /* we use this semaphore in order to ensure no other party(could be ioctl + FIO_SVIP_NAT_RULE_LIST), uses function SVIP_NAT_ProcReadNAT(), during + the time read of the proc file takes place */ + down(sem_nat_tbl_access); + } + else + { + local_irq_restore(flags); + } + + if (data != NULL) + { + fn = data; + len = fn (page, count); + /* In this setup each read of the proc entries returns the read data by + 'fn' to the user. The user keeps issuing read requests as long as the + returned value of 'len' is greater than zero. */ + *eof = 1; + *start = page; + } + else + { + len = 0; + } + + return len; +} + +#ifdef CONFIG_SVIP_FW_PKT_SNIFFER +/** + Function to read remaining proc entries + */ +static int SVIP_NAT_ProcReadGen (char *page, char **start, off_t off, + int count, int *eof, void *data) +{ + int (*fn)(char *buf, int size); + int len = 0; + + MOD_INC_USE_COUNT; + + if (data == NULL) + { + MOD_DEC_USE_COUNT; + return 0; + } + + fn = data; + len = fn (page, count); + + if (len <= off + count) + { + *eof = 1; + } + *start = page + off; + len -= off; + if (len > count) + { + len = count; + } + if (len < 0) + { + len = 0; + } + + MOD_DEC_USE_COUNT; + + return len; +} +#endif + +/******************************************************************************/ +/** + Function for setting up /proc/net/svip_nat read data + + \arguments + buf - pointer to read buffer + count - size of read buffer + + \return + length of read data into buffer + + \remarks: + The global variable 'nProcReadIdx' is used to save the table index where + the reading of the NAT table stopped. Reading is stopped when the end of + the read buffer is approached. On the next itteration the reading continues + from the saved index. + *******************************************************************************/ +static int SVIP_NAT_ProcReadNAT(char *buf, int count) +{ + int i, j; + int len = 0; + SVIP_NAT_IO_Rule_t *pNatRule; + + if (nProcReadIdx == -1) + { + nProcReadIdx = 0; + return 0; + } + + if (nProcReadIdx == 0) + { + len = sprintf(buf+len, + "Remote host IP " /* 16 char */ + "Remote host MAC " /* 19 char */ + "Local host IP " /* 15 char */ + "Local host MAC " /* 19 char */ + "Local host UDP " /* 16 char */ + "Loc->Rem(in/out/err) " /* 22 char */ + "Rem->Loc(in/out/err)\n\r"); + } + + for (i = nProcReadIdx; i < SVIP_SYS_CODEC_NUM; i++) + { + int slen; + + pNatRule = &pNatTable[i].natRule; + + if (pNatRule->remIP != 0) + { + /* make sure not to overwrite the buffer */ + if (count < len+120) + break; + + /* remIP */ + slen = sprintf(buf+len, "%d.%d.%d.%d", + (int)((pNatRule->remIP >> 24) & 0xff), + (int)((pNatRule->remIP >> 16) & 0xff), + (int)((pNatRule->remIP >> 8) & 0xff), + (int)((pNatRule->remIP >> 0) & 0xff)); + len += slen; + for (j = 0; j < (16-slen); j++) + len += sprintf(buf+len, " "); + + /* remMAC */ + slen = 0; + for (j = 0; j < ETH_ALEN; j++) + { + slen += sprintf(buf+len+slen, "%02x%s", + pNatRule->remMAC[j], j < ETH_ALEN-1 ? ":" : " "); + } + len += slen; + for (j = 0; j < (19-slen); j++) + len += sprintf(buf+len, " "); + + /* locIP */ + slen = sprintf(buf+len, "%d.%d.%d.%d", + (int)((pNatRule->locIP >> 24) & 0xff), + (int)((pNatRule->locIP >> 16) & 0xff), + (int)((pNatRule->locIP >> 8) & 0xff), + (int)((pNatRule->locIP >> 0) & 0xff)); + len += slen; + for (j = 0; j < (15-slen); j++) + len += sprintf(buf+len, " "); + + /* locMAC */ + slen = 0; + for (j = 0; j < ETH_ALEN; j++) + { + slen += sprintf(buf+len+slen, "%02x%s", + pNatRule->locMAC[j], j < ETH_ALEN-1 ? ":" : " "); + } + len += slen; + for (j = 0; j < (19-slen); j++) + len += sprintf(buf+len, " "); + + /* locUDP */ + slen = sprintf(buf+len, "%d", pNatRule->locUDP); + len += slen; + for (j = 0; j < (16-slen); j++) + len += sprintf(buf+len, " "); + + /* NAT statistics, Local to Remote translation */ + slen = sprintf(buf+len, "(%ld/%ld/%ld)", + pNatTable[i].natStats[SVIP_NAT_STATS_LOC2REM].inPackets, + pNatTable[i].natStats[SVIP_NAT_STATS_LOC2REM].outPackets, + pNatTable[i].natStats[SVIP_NAT_STATS_LOC2REM].outErrors); + len += slen; + for (j = 0; j < (22-slen); j++) + len += sprintf(buf+len, " "); + + /* NAT statistics, Remote to Local translation */ + len += sprintf(buf+len, "(%ld/%ld/%ld)\n\r", + pNatTable[i].natStats[SVIP_NAT_STATS_REM2LOC].inPackets, + pNatTable[i].natStats[SVIP_NAT_STATS_REM2LOC].outPackets, + pNatTable[i].natStats[SVIP_NAT_STATS_REM2LOC].outErrors); + } + } + if (i == SVIP_SYS_CODEC_NUM) + nProcReadIdx = -1; /* reading completed */ + else + nProcReadIdx = i; /* reading still in process, buffer was full */ + + return len; +} + +#ifdef CONFIG_SVIP_FW_PKT_SNIFFER +/** + Converts MAC address from ascii to hex respesentaion + */ +static int SVIP_NAT_MacAsciiToHex(const char *pMacStr, unsigned char *pMacHex) +{ + int i=0, c=0, b=0, n=0; + + memset(pMacHex, 0, ETH_ALEN); + while (pMacStr[i] != '\0') + { + if (n >= 0) + { + unsigned char nToHex = 0; + + /* check for hex digit */ + if (pMacStr[i] >= '0' && pMacStr[i] <= '9') + nToHex = 0x30; + else if (pMacStr[i] >= 'a' && pMacStr[i] <= 'f') + nToHex = 0x57; + else if (pMacStr[i] >= 'A' && pMacStr[i] <= 'F') + nToHex = 0x37; + else + { + if (n != 0) + { + printk(KERN_ERR "SVIP NAT: invalid MAC address format[%s]\n", pMacStr); + return -1; + } + i++; + continue; + } + n^=1; + pMacHex[b] |= ((pMacStr[i] - nToHex)&0xf) << (4*n); + if (n == 0) + { + /* advance to next byte, check if complete */ + if (++b >= ETH_ALEN) + return 0; + /* byte completed, next we expect a colon... */ + c = 1; + /* and, do not check for hex digit */ + n = -1; + } + i++; + continue; + } + if (c == 1) + { + if (pMacStr[i] == ':') + { + /* next we expect hex digit, again */ + n = 0; + } + else + { + printk(KERN_ERR "SVIP NAT: invalid MAC address format[%s]\n", pMacStr); + return -1; + } + } + i++; + } + return 0; +} + +/** + Used to set the destination MAC address of a host where incoming + SVIP VoFW packets are to be addressed. In case the address is set + to 00:00:00:00:00:00 (the default case), the packets will written + out to eth0 with its original MAC addess. + + \remark +usage: 'echo "00:03:19:00:15:D1" > cat /proc/net/svip_nat/snifferMAC' +*/ +int SVIP_NAT_ProcWriteSnifferMAC (struct file *file, const char *buffer, + unsigned long count, void *data) +{ + /* at least strlen("xx:xx:xx:xx:xx:xx") characters, followed by '\0' */ + if (count >= 18) + { + int ret; + + ret = SVIP_NAT_MacAsciiToHex(buffer, pSVIP_NAT_SnifferMAC); + + if (ret != 0) + return 0; + + if (!(pSVIP_NAT_SnifferMAC[0]==0 && pSVIP_NAT_SnifferMAC[1]==0 && + pSVIP_NAT_SnifferMAC[2]==0 && pSVIP_NAT_SnifferMAC[3]==0 && + pSVIP_NAT_SnifferMAC[4]==0 && pSVIP_NAT_SnifferMAC[5]==0)) + { + nSVIP_NAT_SnifferMacSet = 1; + } + } + return count; +} + +/** + Used to read the destination MAC address of a sniffer host + */ +int SVIP_NAT_ProcReadSnifferMAC (char *buf, int count) +{ + int len = 0; + + len = snprintf(buf, count, "%02x:%02x:%02x:%02x:%02x:%02x\n", + pSVIP_NAT_SnifferMAC[0], pSVIP_NAT_SnifferMAC[1], + pSVIP_NAT_SnifferMAC[2], pSVIP_NAT_SnifferMAC[3], + pSVIP_NAT_SnifferMAC[4], pSVIP_NAT_SnifferMAC[5]); + + if (len > count) + { + printk(KERN_ERR "SVIP NAT: Only part of the text could be put into the buffer\n"); + return count; + } + + return len; +} + +/** + Used to switch VoFW message sniffer on/off + + \remark +usage: 'echo "1" > cat /proc/net/svip_nat/snifferOnOff' +*/ +int SVIP_NAT_ProcWriteSnifferOnOff (struct file *file, const char *buffer, + unsigned long count, void *data) +{ + /* at least one digit expected, followed by '\0' */ + if (count >= 2) + { + int ret, nSnifferOnOff; + + ret = sscanf(buffer, "%d", &nSnifferOnOff); + + if (ret != 1) + return count; + + if (nSnifferOnOff > 0) + nSnifferOnOff = 1; + + nSVIP_NAT_Sniffer = nSnifferOnOff; + } + return count; +} + +/** + Used to read the VoFW message sniffer configuration (on/off) + */ +int SVIP_NAT_ProcReadSnifferOnOff (char *buf, int count) +{ + int len = 0; + + len = snprintf(buf, count, "%d\n", nSVIP_NAT_Sniffer); + + if (len > count) + { + printk(KERN_ERR "SVIP NAT: Only part of the text could be put into the buffer\n"); + return count; + } + + return len; +} +#endif + +/******************************************************************************/ +/** + Creates proc read/write entries + + \return + 0 on success, -1 on error + */ +/******************************************************************************/ +static int SVIP_NAT_ProcInstall(void) +{ + struct proc_dir_entry *pProcParentDir, *pProcDir; + struct proc_dir_entry *pProcNode; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) + pProcParentDir = proc_net; +#else + pProcParentDir = init_net.proc_net; +#endif + pProcDir = proc_mkdir(SVIP_NAT_DEVICE_NAME, pProcParentDir); + if (pProcDir == NULL) + { + printk(KERN_ERR "SVIP NAT: cannot create proc dir %s/%s\n\r", + pProcParentDir->name, SVIP_NAT_DEVICE_NAME); + return -1; + } + + pProcNode = create_proc_read_entry("nat", S_IFREG|S_IRUGO, pProcDir, + SVIP_NAT_ProcRead, (void *)SVIP_NAT_ProcReadNAT); + if (pProcNode == NULL) + { + printk(KERN_ERR "SVIP NAT: cannot create proc entry %s/%s", + pProcDir->name, "nat"); + return -1; + } + +#ifdef CONFIG_SVIP_FW_PKT_SNIFFER + nSVIP_NAT_Sniffer = 0; + /* creates proc entry for switching on/off sniffer to VoFW messages */ + pProcNode = create_proc_read_entry("snifferOnOff", S_IFREG|S_IRUGO|S_IWUGO, + pProcDir, SVIP_NAT_ProcReadGen, (void *)SVIP_NAT_ProcReadSnifferOnOff); + if (pProcNode == NULL) + { + printk(KERN_ERR "SVIP NAT: cannot create proc entry %s/%s\n\r", + pProcDir->name, "snifferOnOff"); + return -1; + } + pProcNode->write_proc = SVIP_NAT_ProcWriteSnifferOnOff; + + memset (pSVIP_NAT_SnifferMAC, 0, ETH_ALEN); + nSVIP_NAT_SnifferMacSet = 0; + /* creates proc entry for setting MAC address of sniffer host to VoFW messages */ + pProcNode = create_proc_read_entry("snifferMAC", S_IFREG|S_IRUGO|S_IWUGO, + pProcDir, SVIP_NAT_ProcReadGen, (void *)SVIP_NAT_ProcReadSnifferMAC); + if (pProcNode == NULL) + { + printk(KERN_ERR "SVIP NAT: cannot create proc entry %s/%s\n\r", + pProcDir->name, "snifferMAC"); + return -1; + } + pProcNode->write_proc = SVIP_NAT_ProcWriteSnifferMAC; +#endif + + return 0; +} + +/******************************************************************************/ +/** + No actions done here, simply a check is performed if an open has already + been performed. Currently only a single open is allowed as it is a sufficient + to have hat a single process configuring the SVIP NAT at one time. + + \arguments + inode - pointer to disk file data + file - pointer to device file data + + \return + 0 on success, else -1 + */ +/******************************************************************************/ +static int SVIP_NAT_device_open(struct inode *inode, struct file *file) +{ + unsigned long flags; + struct in_device *in_dev; + struct in_ifaddr *ifa; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + local_irq_save(flags); +#else + local_save_flags(flags); +#endif + + if (nDeviceOpen) + { + MOD_INC_USE_COUNT; + local_irq_restore(flags); + nDeviceOpen++; + return 0; + } + + /* find pointer to IP address of eth0 */ + if ((in_dev=in_dev_get(net_devs[SVIP_NET_DEV_ETH0_IDX])) != NULL) + { + for (ifa = in_dev->ifa_list; ifa != NULL; ifa = ifa->ifa_next) + { + if (!paddr_eth0 && ifa->ifa_address != 0) + { + paddr_eth0 = &ifa->ifa_address; + continue; + } + if (paddr_eth0 && ifa->ifa_address != 0) + { + paddr_eth0_0 = &ifa->ifa_address; + break; + } + } + in_dev_put(in_dev); + } + if (paddr_eth0 == NULL || paddr_eth0_0 == NULL) + { + local_irq_restore(flags); + return -ENODATA; + } + + /* find pointer to IP address of veth0 */ + if ((in_dev=in_dev_get(net_devs[SVIP_NET_DEV_VETH0_IDX])) != NULL) + { + for (ifa = in_dev->ifa_list; ifa != NULL; ifa = ifa->ifa_next) + { + if (ifa->ifa_address != 0) + { + paddr_veth0 = &ifa->ifa_address; + pmask_veth0 = &ifa->ifa_mask; + break; + } + } + in_dev_put(in_dev); + } + if (paddr_veth0 == NULL) + { + local_irq_restore(flags); + return -ENODATA; + } + + MOD_INC_USE_COUNT; + nDeviceOpen++; + local_irq_restore(flags); + + return 0; +} + + +/******************************************************************************/ +/** + This function is called when a process closes the SVIP NAT device file + + \arguments + inode - pointer to disk file data + file - pointer to device file data + + \return + 0 on success, else -1 + +*/ +/******************************************************************************/ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0) +static int SVIP_NAT_device_release(struct inode *inode, + struct file *file) +#else +static void SVIP_NAT_device_release(struct inode *inode, + struct file *file) +#endif +{ + unsigned long flags; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + save_flags(flags); + cli(); +#else + local_save_flags(flags); +#endif + + /* The device can now be openned by the next caller */ + nDeviceOpen--; + + MOD_DEC_USE_COUNT; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + restore_flags(flags); +#else + local_irq_restore(flags); +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0) + return 0; +#endif +} + + +/******************************************************************************/ +/** + This function is called when a process closes the SVIP NAT device file + + \arguments + inode - pointer to disk file data + file - pointer to device file data + ioctl_num - ioctl number requested + ioctl_param - pointer to data related to the ioctl number + + \return + 0 on success, else -1 + +*/ +/******************************************************************************/ +long SVIP_NAT_device_ioctl (struct file *file, + unsigned int ioctl_num, unsigned long ioctl_param) +{ + int ret = 0; + SVIP_NAT_IO_Rule_t *pNatRule, *pNatRuleIn; + SVIP_UDP_PORT_t nPort; + int nNatIdx; + int bWrite = 0; + int bRead = 0; + unsigned char *pData = 0; + int nSize; + + if (_IOC_DIR(ioctl_num) & _IOC_WRITE) + bWrite = 1; + if (_IOC_DIR(ioctl_num) & _IOC_READ) + bRead = 1; + nSize = _IOC_SIZE(ioctl_num); + + if (nSize > sizeof(int)) + { + if (bRead || bWrite) + { + pData = kmalloc (nSize, GFP_KERNEL); + if (bWrite) + { + if (copy_from_user ((void *)pData, (void *)ioctl_param, nSize) != 0) + { + printk(KERN_ERR "SVIP NAT: ioctl %x: copy_from_user() failed!\n", ioctl_num); + ret = -1; + goto error; + } + } + } + } + + switch (ioctl_num) + { + case FIO_SVIP_NAT_RULE_ADD: + + pNatRuleIn = (SVIP_NAT_IO_Rule_t *)pData; + + /* check if destination UDP port is within range */ + nPort = ntohs(pNatRuleIn->locUDP); + + if (!SVIP_PORT_INRANGE(nPort)) + { + printk(KERN_ERR "SVIP NAT: Error, UDP port(%d) is out of range(%d..%d)\n", + nPort, SVIP_UDP_FROM, SVIP_UDP_TO); + ret = -1; + goto error; + } + nNatIdx = SVIP_PORT_INDEX(nPort); + + down(sem_nat_tbl_access); + pNatRule = &pNatTable[nNatIdx].natRule; + + /* add rule to the NAT table */ + pNatRule->remIP = pNatRuleIn->remIP; + memcpy((char *)pNatRule->remMAC, (char *)pNatRuleIn->remMAC, ETH_ALEN); + pNatRule->locIP = pNatRuleIn->locIP; + memcpy((char *)pNatRule->locMAC, (char *)pNatRuleIn->locMAC, ETH_ALEN); + pNatRule->locUDP = pNatRuleIn->locUDP; + + memset(pNatTable[nNatIdx].natStats, 0, + sizeof(SVIP_NAT_stats_t)*SVIP_NAT_STATS_TYPES); + up(sem_nat_tbl_access); + break; + + case FIO_SVIP_NAT_RULE_REMOVE: + + pNatRuleIn = (SVIP_NAT_IO_Rule_t *)pData; + + /* check if destination UDP port is within range */ + nPort = ntohs(pNatRuleIn->locUDP); + if (!SVIP_PORT_INRANGE(nPort)) + { + printk(KERN_ERR "SVIP NAT: Error, UDP port(%d) is out of range(%d..%d)\n", + nPort, SVIP_UDP_FROM, SVIP_UDP_TO); + ret = -1; + goto error; + } + nNatIdx = SVIP_PORT_INDEX(nPort); + down(sem_nat_tbl_access); + /* remove rule from the NAT table */ + memset(&pNatTable[nNatIdx], 0, sizeof(SVIP_NAT_table_entry_t)); + up(sem_nat_tbl_access); + break; + + case FIO_SVIP_NAT_RULE_LIST: + { + int len; + char buf[256]; + + down(sem_nat_tbl_access); + while (nProcReadIdx != -1) + { + len = SVIP_NAT_ProcReadNAT(buf, 256); + if (len > 0) + printk("%s", buf); + } + nProcReadIdx = 0; + up(sem_nat_tbl_access); + break; + } + + default: + printk(KERN_ERR "SVIP NAT: unsupported ioctl (%x) command for device %s\n", + ioctl_num, PATH_SVIP_NAT_DEVICE_NAME); + ret = -1; + goto error; + } + + if (nSize > sizeof(int)) + { + if (bRead) + { + if (copy_to_user ((void *)ioctl_param, (void *)pData, nSize) != 0) + { + printk(KERN_ERR "SVIP NAT: ioctl %x: copy_to_user() failed!\n", ioctl_num); + ret = -1; + goto error; + } + } + } + +error: + if (pData) + kfree(pData); + + return ret; +} + +#if 0 +void dump_msg(unsigned char *pData, unsigned int nLen) +{ + int i; + + for (i=0; i> 16) + sum = (sum & 0xffff)+((sum >> 16) & 0xffff); + + /* one's complement the result */ + sum = ~sum; + + return (u16)(sum & 0xffff); +} + + +/******************************************************************************/ +/** + Returns a pointer to an ipv4 address assigned to device dev. The ipv4 + instance checked is pointed to by ifa_start. The function is suited for + itterative calls. + + \arguments + dev - pointer to network interface + ifa_start - pointer to ipv4 instance to return ipv4 address assigned + to, NULL for the first one + ppifa_addr - output parameter + + \return + pointer to the next ipv4 instance, which can be null if ifa_start was + the last instance present + */ +/******************************************************************************/ +static struct in_ifaddr *get_ifaddr(struct net_device *dev, + struct in_ifaddr *ifa_start, unsigned int **ppifa_addr) +{ + struct in_device *in_dev; + struct in_ifaddr *ifa = NULL; + + if ((in_dev=in_dev_get(dev)) != NULL) + { + if (ifa_start == NULL) + ifa = in_dev->ifa_list; + else + ifa = ifa_start; + if (ifa) + { + *ppifa_addr = &ifa->ifa_address; + ifa = ifa->ifa_next; + } + in_dev_put(in_dev); + return ifa; + } + *ppifa_addr = NULL; + return NULL; +} + +/******************************************************************************/ +/** + This function performs IP NAT for received packets satisfying the + following requirements: + + - packet is destined to local IP host + - transport protocol type is UDP + - destination UDP port is within range + + \arguments + skb - pointer to the receiving socket buffer + + \return + returns 1 on performed SVIP NAT, else returns 0 + + \remarks + When function returns 0, it indicates the caller to pass the + packet up the IP stack to make further decision about it + */ +/******************************************************************************/ +int do_SVIP_NAT (struct sk_buff *skb) +{ + struct net_device *real_dev; + struct iphdr *iph; + struct udphdr *udph; + SVIP_NAT_IO_Rule_t *pNatRule; + int nNatIdx, in_eth0, nDir; +#ifndef VLAN_8021Q_UNUSED + int vlan; + unsigned short vid; +#endif /* ! VLAN_8021Q_UNUSED */ + SVIP_UDP_PORT_t nPort; + u32 orgSrcIp, orgDstIp, *pSrcIp, *pDstIp; + struct ethhdr *ethh; + + /* do not consider if SVIP NAT device not open. */ + if (!nDeviceOpen) + { + return 0; + } + + /* consider only UDP packets. */ + iph = SVIP_NAT_IP_HDR(skb); + if (iph->protocol != IPPROTO_UDP) + { + return 0; + } + + udph = (struct udphdr *)((u_int32_t *)iph + iph->ihl); + /* consider only packets which UDP port numbers reside within + the predefined SVIP NAT UDP port range. */ + if ((!SVIP_PORT_INRANGE(ntohs(udph->dest))) && + (!SVIP_PORT_INRANGE(ntohs(udph->source)))) + { + return 0; + } + +#ifndef VLAN_8021Q_UNUSED + /* check if packet delivered over VLAN. VLAN packets will be routed over + the VLAN interfaces of the respective real Ethernet interface, if one + exists(VIDs must match). Else, the packet will be send out as IEEE 802.3 + Ethernet frame */ + if (skb->dev->priv_flags & IFF_802_1Q_VLAN) + { + vlan = 1; + vid = VLAN_DEV_VLAN_ID(skb->dev); + real_dev = VLAN_DEV_REAL_DEV(skb->dev); + } + else + { + vlan = 0; + vid = 0; + real_dev = skb->dev; + } +#endif /* ! VLAN_8021Q_UNUSED */ + +#ifdef CONFIG_SVIP_FW_PKT_SNIFFER + /** Debugging feature which can be enabled by writing, + 'echo 1 > /proc/net/svip_nat/snifferOnOff'. + It copies all packets received on veth0 and, sends them out over eth0. + When a destination MAC address is specified through + /proc/net/svip_nat/snifferMAC, this MAC addess will substitute the + original MAC address of the packet. + It is recommended to specify a MAC address of some host where Wireshark + runs and sniffs for this traffic, else you may flood your LAN with + undeliverable traffic. + +NOTE: In case of VLAN traffic the VLAN header information is lost. */ + if (nSVIP_NAT_Sniffer) + { + if (real_dev == net_devs[SVIP_NET_DEV_VETH0_IDX]) + { + struct sk_buff *copied_skb; + + /* gain the Ethernet header from the skb */ + skb_push(skb, ETH_HLEN); + + copied_skb = skb_copy (skb, GFP_ATOMIC); + + if (nSVIP_NAT_SnifferMacSet == 1) + { + ethh = (struct ethhdr *)SVIP_NAT_SKB_MAC_HEADER(copied_skb); + memcpy((char *)ethh->h_dest, (char *)pSVIP_NAT_SnifferMAC, ETH_ALEN); + } + copied_skb->dev = net_devs[SVIP_NET_DEV_ETH0_IDX]; + dev_queue_xmit(copied_skb); + + /* skip the ETH header again */ + skb_pull(skb, ETH_HLEN); + } + } +#endif + + + /* check if packet arrived on eth0 */ + if (real_dev == net_devs[SVIP_NET_DEV_ETH0_IDX]) + { + /* check if destination IP address equals the primary assigned IP address + of interface eth0. This is the case of packets originating from a + remote peer that are to be delivered to a channel residing on THIS + voice linecard system. This is typical SVIP NAT case, therefore this + rule is placed on top. */ + if (iph->daddr == *paddr_eth0) + { + nPort = ntohs(udph->dest); + nDir = SVIP_NAT_STATS_REM2LOC; + } + /* check if destination IP address equals the secondary assigned IP address + of interface eth0. This is not a typical SVIP NAT case. It is basically + there, as someone might like for debugging purpose to use the LCC to route + Slave SVIP packets which are part of voice/fax streaming. */ + else if (iph->daddr == *paddr_eth0_0) + { + nPort = ntohs(udph->source); + nDir = SVIP_NAT_STATS_LOC2REM; + } +#ifndef VLAN_8021Q_UNUSED + /* when the packet did not hit the top two rules, here we check if the packet + has addressed any of the IP addresses assigned to the VLAN interface attached + to eth0. This is not recommended approach because of the CPU cost incurred. */ + else if (vlan) + { + unsigned int *pifa_addr; + struct in_ifaddr *ifa_start = NULL; + int i = 0; + + do + { + ifa_start = get_ifaddr(skb->dev, ifa_start, &pifa_addr); + if (!pifa_addr) + { + /* VLAN packet received on vlan interface attached to eth0, + however no IP address assigned to the interface. + The packet is ignored. */ + return 0; + } + if (iph->daddr == *pifa_addr) + { + /* packet destined to... */ + break; + } + if (!ifa_start) + { + return 0; + } + i++; + } while (ifa_start); + if (!i) + { + /* ...primary assigned IP address to the VLAN interface. */ + nPort = ntohs(udph->dest); + nDir = SVIP_NAT_STATS_REM2LOC; + } + else + { + /* ...secondary assigned IP address to the VLAN interface. */ + nPort = ntohs(udph->source); + nDir = SVIP_NAT_STATS_LOC2REM; + } + } +#endif /* ! VLAN_8021Q_UNUSED */ + else + { + return 0; + } + in_eth0 = 1; + } + /* check if packet arrived on veth0 */ + else if (real_dev == net_devs[SVIP_NET_DEV_VETH0_IDX]) + { + nPort = ntohs(udph->source); + nDir = SVIP_NAT_STATS_LOC2REM; + in_eth0 = 0; + } + else + { + /* packet arrived neither on eth0, nor veth0 */ + return 0; + } + + /* calculate the respective index of the NAT table */ + nNatIdx = SVIP_PORT_INDEX(nPort); + /* process the packet if a respective NAT rule exists */ + pNatRule = &pNatTable[nNatIdx].natRule; + + ethh = (struct ethhdr *)SVIP_NAT_SKB_MAC_HEADER(skb); + + /* copy packet's original source and destination IP addresses to use + later on to perform efficient checksum recalculation */ + orgSrcIp = iph->saddr; + orgDstIp = iph->daddr; + + if (in_eth0) + { + u8 *pDstMac; + + /* Process packet arrived on eth0 */ + + if (nDir == SVIP_NAT_STATS_REM2LOC && iph->saddr == pNatRule->remIP) + { + pDstIp = &pNatRule->locIP; + pDstMac = pNatRule->locMAC; + } + else if (nDir == SVIP_NAT_STATS_LOC2REM && iph->saddr == pNatRule->locIP) + { + pDstIp = &pNatRule->remIP; + pDstMac = pNatRule->remMAC; + } + else + { + /* Rule check failed. The packet is passed up the layers, + it will be dropped by UDP */ + return 0; + } + + if ((*pDstIp & *pmask_veth0) == (*paddr_veth0 & *pmask_veth0)) + { +#ifndef VLAN_8021Q_UNUSED + if (vlan) + { + struct net_device *vlan_dev; + + spin_lock_bh(&vlan_group_lock); + vlan_dev = __vlan_find_dev_deep(net_devs[SVIP_NET_DEV_VETH0_IDX], vid); + spin_unlock_bh(&vlan_group_lock); + if (vlan_dev) + { +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + struct vlan_ethhdr *vethh; + + skb_push(skb, VLAN_ETH_HLEN); + /* reconstruct the VLAN header. +NOTE: priority information is lost */ + vethh = (struct vlan_ethhdr *)skb->data; + vethh->h_vlan_proto = htons(ETH_P_8021Q); + vethh->h_vlan_TCI = htons(vid); + vethh->h_vlan_encapsulated_proto = htons(ETH_P_IP); + ethh = (struct ethhdr *)vethh; +#else + skb_push(skb, ETH_HLEN); +#endif + skb->dev = vlan_dev; + } + else + { + skb->dev = net_devs[SVIP_NET_DEV_VETH0_IDX]; + skb_push(skb, ETH_HLEN); + } + } + else +#endif /* ! VLAN_8021Q_UNUSED */ + { + skb->dev = net_devs[SVIP_NET_DEV_VETH0_IDX]; + skb_push(skb, ETH_HLEN); + } + pSrcIp = paddr_veth0; + } + else + { +#ifndef VLAN_8021Q_UNUSED +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + if (vlan) + { + struct vlan_ethhdr *vethh; + + /* reconstruct the VLAN header. +NOTE: priority information is lost */ + skb_push(skb, VLAN_ETH_HLEN); + vethh = (struct vlan_ethhdr *)skb->data; + vethh->h_vlan_proto = htons(ETH_P_8021Q); + vethh->h_vlan_TCI = htons(vid); + vethh->h_vlan_encapsulated_proto = htons(ETH_P_IP); + ethh = (struct ethhdr *)vethh; + } + else +#endif +#endif /* ! VLAN_8021Q_UNUSED */ + { + skb_push(skb, ETH_HLEN); + } + /* source IP address equals the destination IP address + of the incoming packet */ + pSrcIp = &iph->daddr; + } + iph->saddr = *pSrcIp; + memcpy((char *)ethh->h_source, (char *)skb->dev->dev_addr, ETH_ALEN); + iph->daddr = *pDstIp; + memcpy((char *)ethh->h_dest, (char *)pDstMac, ETH_ALEN); + } + else + { + /* Process packet arrived on veth0 */ + + if (iph->saddr != pNatRule->locIP) + { + /* Rule check failed. The packet is passed up the layers, + it will be dropped by UDP */ + return 0; + } + + if (!((pNatRule->remIP & *pmask_veth0) == (*paddr_veth0 & *pmask_veth0))) + { +#ifndef VLAN_8021Q_UNUSED + if (vlan) + { + struct net_device *vlan_dev; + + spin_lock_bh(&vlan_group_lock); + vlan_dev = __vlan_find_dev_deep(net_devs[SVIP_NET_DEV_ETH0_IDX], vid); + spin_unlock_bh(&vlan_group_lock); + if (vlan_dev) + { + unsigned int *pifa_addr; +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + struct vlan_ethhdr *vethh; + + skb_push(skb, VLAN_ETH_HLEN); + /* construct the VLAN header, note priority information is lost */ + vethh = (struct vlan_ethhdr *)skb->data; + vethh->h_vlan_proto = htons(ETH_P_8021Q); + vethh->h_vlan_TCI = htons(vid); + vethh->h_vlan_encapsulated_proto = htons(ETH_P_IP); + ethh = (struct ethhdr *)vethh; +#else + skb_push(skb, ETH_HLEN); +#endif + skb->dev = vlan_dev; + + get_ifaddr(skb->dev, NULL, &pifa_addr); + if (pifa_addr) + { + pSrcIp = pifa_addr; + } + else + { + pSrcIp = paddr_eth0; + } + } + else + { + skb->dev = net_devs[SVIP_NET_DEV_ETH0_IDX]; + pSrcIp = paddr_eth0; + skb_push(skb, ETH_HLEN); + } + } + else +#endif /* ! VLAN_8021Q_UNUSED */ + { + skb->dev = net_devs[SVIP_NET_DEV_ETH0_IDX]; + pSrcIp = paddr_eth0; + skb_push(skb, ETH_HLEN); + } + } + else + { + pSrcIp = paddr_veth0; +#ifndef VLAN_8021Q_UNUSED +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) + if (vlan) + { + struct vlan_ethhdr *vethh; + + skb_push(skb, VLAN_ETH_HLEN); + /* reconstruct the VLAN header. +NOTE: priority information is lost. */ + vethh = (struct vlan_ethhdr *)skb->data; + vethh->h_vlan_proto = htons(ETH_P_8021Q); + vethh->h_vlan_TCI = htons(vid); + vethh->h_vlan_encapsulated_proto = htons(ETH_P_IP); + ethh = (struct ethhdr *)vethh; + } + else +#endif +#endif /* ! VLAN_8021Q_UNUSED */ + { + skb_push(skb, ETH_HLEN); + } + } + iph->saddr = *pSrcIp; + memcpy((char *)ethh->h_source, (char *)skb->dev->dev_addr, ETH_ALEN); + iph->daddr = pNatRule->remIP; + memcpy((char *)ethh->h_dest, (char *)pNatRule->remMAC, ETH_ALEN); + } + pNatTable[nNatIdx].natStats[nDir].inPackets++; + + iph->check = ip_udp_quick_csum(iph->check, (u16 *)&orgSrcIp, (u16 *)&iph->saddr, + (u16 *)&orgDstIp, (u16 *)&iph->daddr); + if (udph->check != 0) + { + udph->check = ip_udp_quick_csum(udph->check, (u16 *)&orgSrcIp, (u16 *)&iph->saddr, + (u16 *)&orgDstIp, (u16 *)&iph->daddr); + } + + /* write the packet out, directly to the network device */ + if (dev_queue_xmit(skb) < 0) + pNatTable[nNatIdx].natStats[nDir].outErrors++; + else + pNatTable[nNatIdx].natStats[nDir].outPackets++; + + return 1; +} + +/******************************************************************************/ +/** + Function executed upon unloading of the SVIP NAT module. It unregisters the + SVIP NAT configuration device and frees the memory used for the NAT table. + + \remarks: + Currently the SVIP NAT module is statically linked into the Linux kernel + therefore this routine cannot be executed. + *******************************************************************************/ +static int __init init(void) +{ + int ret = 0; + struct net_device *dev; + + if (misc_register(&SVIP_NAT_miscdev) != 0) + { + printk(KERN_ERR "%s: cannot register SVIP NAT device node.\n", + SVIP_NAT_miscdev.name); + return -EIO; + } + + /* allocation of memory for NAT table */ + pNatTable = (SVIP_NAT_table_entry_t *)kmalloc( + sizeof(SVIP_NAT_table_entry_t) * SVIP_SYS_CODEC_NUM, GFP_ATOMIC); + if (pNatTable == NULL) + { + printk (KERN_ERR "SVIP NAT: Error(%d), allocating memory for NAT table\n", ret); + return -1; + } + + /* clear the NAT table */ + memset((void *)pNatTable, 0, sizeof(SVIP_NAT_table_entry_t) * SVIP_SYS_CODEC_NUM); + + if ((sem_nat_tbl_access = kmalloc(sizeof(struct semaphore), GFP_KERNEL))) + { + sema_init(sem_nat_tbl_access, 1); + } + + SVIP_NAT_ProcInstall(); + + /* find pointers to 'struct net_device' of eth0 and veth0, respectevely */ + read_lock(&dev_base_lock); + SVIP_NAT_FOR_EACH_NETDEV(dev) + { + if (!strcmp(dev->name, SVIP_NET_DEV_ETH0_NAME)) + { + net_devs[SVIP_NET_DEV_ETH0_IDX] = dev; + } + if (!strcmp(dev->name, SVIP_NET_DEV_VETH1_NAME)) + { + net_devs[SVIP_NET_DEV_VETH0_IDX] = dev; + } + else if (!strcmp(dev->name, SVIP_NET_DEV_ETH1_NAME)) + { + net_devs[SVIP_NET_DEV_VETH0_IDX] = dev; + } + } + read_unlock(&dev_base_lock); + + if (net_devs[SVIP_NET_DEV_ETH0_IDX] == NULL || + net_devs[SVIP_NET_DEV_VETH0_IDX] == NULL) + { + printk (KERN_ERR "SVIP NAT: Error, unable to locate eth0 and veth0 interfaces\n"); + return -1; + } + + printk ("%s, (c) 2009, Lantiq Deutschland GmbH\n", &SVIP_NAT_INFO_STR[4]); + + return ret; +} + +/******************************************************************************/ +/** + Function executed upon unloading of the SVIP NAT module. It unregisters the + SVIP NAT configuration device and frees the memory used for the NAT table. + + \remarks: + Currently the SVIP NAT module is statically linked into the Linux kernel + therefore this routine cannot be executed. + *******************************************************************************/ +static void __exit fini(void) +{ + MOD_DEC_USE_COUNT; + + /* unregister SVIP NAT configuration device */ + misc_deregister(&SVIP_NAT_miscdev); + + /* release memory of SVIP NAT table */ + if (pNatTable != NULL) + { + kfree (pNatTable); + } +} + +module_init(init); +module_exit(fini); diff --git a/target/linux/lantiq/patches-3.3/0001-MTD-add-m25p80-id-for-mx25l2005a.patch b/target/linux/lantiq/patches-3.3/0001-MTD-add-m25p80-id-for-mx25l2005a.patch deleted file mode 100644 index a7e2546a3b..0000000000 --- a/target/linux/lantiq/patches-3.3/0001-MTD-add-m25p80-id-for-mx25l2005a.patch +++ /dev/null @@ -1,19 +0,0 @@ -From 1e54b748744aa6a6dbb86cdbdb9ea775609da7e1 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 13 Mar 2012 18:03:33 +0100 -Subject: [PATCH 01/70] MTD: add m25p80 id for mx25l2005a - ---- - drivers/mtd/devices/m25p80.c | 1 + - 1 files changed, 1 insertions(+), 0 deletions(-) - ---- a/drivers/mtd/devices/m25p80.c -+++ b/drivers/mtd/devices/m25p80.c -@@ -684,6 +684,7 @@ static const struct spi_device_id m25p_i - { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, - - /* Macronix */ -+ { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 8, SECT_4K) }, - { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, - { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, - { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) }, diff --git a/target/linux/lantiq/patches-3.3/0001-falcon-support.patch b/target/linux/lantiq/patches-3.3/0001-falcon-support.patch new file mode 100644 index 0000000000..de7cc8ae1a --- /dev/null +++ b/target/linux/lantiq/patches-3.3/0001-falcon-support.patch @@ -0,0 +1,25 @@ +From f4458a1e4807a6f6163a9473aed4a2166272a611 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 10:13:06 +0200 +Subject: [PATCH 01/25] falcon support + +--- + .../include/asm/mach-lantiq/falcon/falcon_irq.h | 2 ++ + 1 files changed, 2 insertions(+), 0 deletions(-) + +diff --git a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h +index 4dc6466..b024653 100644 +--- a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h ++++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h +@@ -9,6 +9,8 @@ + #ifndef _FALCON_IRQ__ + #define _FALCON_IRQ__ + ++#define IM_NUM 5 ++ + #define INT_NUM_IRQ0 8 + #define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) + #define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32) +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0002-MIPS-lantiq-reorganize-xway-code.patch b/target/linux/lantiq/patches-3.3/0002-MIPS-lantiq-reorganize-xway-code.patch deleted file mode 100644 index 6c99f2c7f8..0000000000 --- a/target/linux/lantiq/patches-3.3/0002-MIPS-lantiq-reorganize-xway-code.patch +++ /dev/null @@ -1,835 +0,0 @@ -From ebbdb83f27aad0eec162c24f32d8dd852e460584 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Wed, 10 Aug 2011 14:57:04 +0200 -Subject: [PATCH 02/70] MIPS: lantiq: reorganize xway code - -Inside the folder arch/mips/lantiq/xway, there were alot of small files with -lots of duplicated code. This patch adds a wrapper function for inserting and -requesting resources and unifies the small files into one bigger file. - -This patch makes the xway code consistent with the falcon support added later -in this series. - -Signed-off-by: John Crispin ---- - arch/mips/include/asm/mach-lantiq/lantiq.h | 14 +--- - .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 14 ++++ - arch/mips/lantiq/clk.c | 25 +------ - arch/mips/lantiq/devices.c | 30 ++------ - arch/mips/lantiq/devices.h | 4 + - arch/mips/lantiq/prom.c | 51 +++++++++++-- - arch/mips/lantiq/prom.h | 4 + - arch/mips/lantiq/xway/Makefile | 6 +- - arch/mips/lantiq/xway/devices.c | 42 ++--------- - arch/mips/lantiq/xway/dma.c | 21 +---- - arch/mips/lantiq/xway/ebu.c | 52 ------------- - arch/mips/lantiq/xway/pmu.c | 69 ----------------- - arch/mips/lantiq/xway/prom-ase.c | 9 ++ - arch/mips/lantiq/xway/prom-xway.c | 10 +++ - arch/mips/lantiq/xway/reset.c | 21 +---- - arch/mips/lantiq/xway/setup-ase.c | 19 ----- - arch/mips/lantiq/xway/setup-xway.c | 20 ----- - arch/mips/lantiq/xway/sysctrl.c | 78 ++++++++++++++++++++ - drivers/watchdog/lantiq_wdt.c | 2 +- - 19 files changed, 199 insertions(+), 292 deletions(-) - delete mode 100644 arch/mips/lantiq/xway/ebu.c - delete mode 100644 arch/mips/lantiq/xway/pmu.c - delete mode 100644 arch/mips/lantiq/xway/setup-ase.c - delete mode 100644 arch/mips/lantiq/xway/setup-xway.c - create mode 100644 arch/mips/lantiq/xway/sysctrl.c - ---- a/arch/mips/include/asm/mach-lantiq/lantiq.h -+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h -@@ -9,6 +9,7 @@ - #define _LANTIQ_H__ - - #include -+#include - - /* generic reg access functions */ - #define ltq_r32(reg) __raw_readl(reg) -@@ -18,15 +19,6 @@ - #define ltq_r8(reg) __raw_readb(reg) - #define ltq_w8(val, reg) __raw_writeb(val, reg) - --/* register access macros for EBU and CGU */ --#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) --#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) --#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y)) --#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x)) -- --extern __iomem void *ltq_ebu_membase; --extern __iomem void *ltq_cgu_membase; -- - extern unsigned int ltq_get_cpu_ver(void); - extern unsigned int ltq_get_soc_type(void); - -@@ -51,7 +43,9 @@ extern void ltq_enable_irq(struct irq_da - - /* find out what caused the last cpu reset */ - extern int ltq_reset_cause(void); --#define LTQ_RST_CAUSE_WDTRST 0x20 -+ -+/* helper for requesting and remapping resources */ -+extern void __iomem *ltq_remap_resource(struct resource *res); - - #define IOPORT_RESOURCE_START 0x10000000 - #define IOPORT_RESOURCE_END 0xffffffff ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -@@ -61,6 +61,8 @@ - #define LTQ_CGU_BASE_ADDR 0x1F103000 - #define LTQ_CGU_SIZE 0x1000 - -+#define CGU_EPHY 0x10 -+ - /* ICU - interrupt control unit */ - #define LTQ_ICU_BASE_ADDR 0x1F880200 - #define LTQ_ICU_SIZE 0x100 -@@ -97,6 +99,8 @@ - #define LTQ_WDT_BASE_ADDR 0x1F8803F0 - #define LTQ_WDT_SIZE 0x10 - -+#define LTQ_RST_CAUSE_WDTRST 0x20 -+ - /* STP - serial to parallel conversion unit */ - #define LTQ_STP_BASE_ADDR 0x1E100BB0 - #define LTQ_STP_SIZE 0x40 -@@ -121,11 +125,21 @@ - #define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000) - #define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344)) - -+/* register access macros for EBU and CGU */ -+#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) -+#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) -+#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y)) -+#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x)) -+ -+extern __iomem void *ltq_ebu_membase; -+extern __iomem void *ltq_cgu_membase; -+ - /* request a non-gpio and set the PIO config */ - extern int ltq_gpio_request(unsigned int pin, unsigned int alt0, - unsigned int alt1, unsigned int dir, const char *name); - extern void ltq_pmu_enable(unsigned int module); - extern void ltq_pmu_disable(unsigned int module); -+extern void ltq_cgu_enable(unsigned int clk); - - static inline int ltq_is_ar9(void) - { ---- a/arch/mips/lantiq/clk.c -+++ b/arch/mips/lantiq/clk.c -@@ -22,6 +22,7 @@ - #include - - #include "clk.h" -+#include "prom.h" - - struct clk { - const char *name; -@@ -46,16 +47,6 @@ static struct clk cpu_clk_generic[] = { - }, - }; - --static struct resource ltq_cgu_resource = { -- .name = "cgu", -- .start = LTQ_CGU_BASE_ADDR, -- .end = LTQ_CGU_BASE_ADDR + LTQ_CGU_SIZE - 1, -- .flags = IORESOURCE_MEM, --}; -- --/* remapped clock register range */ --void __iomem *ltq_cgu_membase; -- - void clk_init(void) - { - cpu_clk = cpu_clk_generic; -@@ -133,21 +124,11 @@ void __init plat_time_init(void) - { - struct clk *clk; - -- if (insert_resource(&iomem_resource, <q_cgu_resource) < 0) -- panic("Failed to insert cgu memory"); -+ ltq_soc_init(); - -- if (request_mem_region(ltq_cgu_resource.start, -- resource_size(<q_cgu_resource), "cgu") < 0) -- panic("Failed to request cgu memory"); -- -- ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start, -- resource_size(<q_cgu_resource)); -- if (!ltq_cgu_membase) { -- pr_err("Failed to remap cgu memory\n"); -- unreachable(); -- } - clk = clk_get(0, "cpu"); - mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution(); - write_c0_compare(read_c0_count()); -+ pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); - clk_put(clk); - } ---- a/arch/mips/lantiq/devices.c -+++ b/arch/mips/lantiq/devices.c -@@ -27,12 +27,8 @@ - #include "devices.h" - - /* nor flash */ --static struct resource ltq_nor_resource = { -- .name = "nor", -- .start = LTQ_FLASH_START, -- .end = LTQ_FLASH_START + LTQ_FLASH_MAX - 1, -- .flags = IORESOURCE_MEM, --}; -+static struct resource ltq_nor_resource = -+ MEM_RES("nor", LTQ_FLASH_START, LTQ_FLASH_MAX); - - static struct platform_device ltq_nor = { - .name = "ltq_nor", -@@ -47,12 +43,8 @@ void __init ltq_register_nor(struct phys - } - - /* watchdog */ --static struct resource ltq_wdt_resource = { -- .name = "watchdog", -- .start = LTQ_WDT_BASE_ADDR, -- .end = LTQ_WDT_BASE_ADDR + LTQ_WDT_SIZE - 1, -- .flags = IORESOURCE_MEM, --}; -+static struct resource ltq_wdt_resource = -+ MEM_RES("watchdog", LTQ_WDT_BASE_ADDR, LTQ_WDT_SIZE); - - void __init ltq_register_wdt(void) - { -@@ -61,24 +53,14 @@ void __init ltq_register_wdt(void) - - /* asc ports */ - static struct resource ltq_asc0_resources[] = { -- { -- .name = "asc0", -- .start = LTQ_ASC0_BASE_ADDR, -- .end = LTQ_ASC0_BASE_ADDR + LTQ_ASC_SIZE - 1, -- .flags = IORESOURCE_MEM, -- }, -+ MEM_RES("asc0", LTQ_ASC0_BASE_ADDR, LTQ_ASC_SIZE), - IRQ_RES(tx, LTQ_ASC_TIR(0)), - IRQ_RES(rx, LTQ_ASC_RIR(0)), - IRQ_RES(err, LTQ_ASC_EIR(0)), - }; - - static struct resource ltq_asc1_resources[] = { -- { -- .name = "asc1", -- .start = LTQ_ASC1_BASE_ADDR, -- .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1, -- .flags = IORESOURCE_MEM, -- }, -+ MEM_RES("asc1", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE), - IRQ_RES(tx, LTQ_ASC_TIR(1)), - IRQ_RES(rx, LTQ_ASC_RIR(1)), - IRQ_RES(err, LTQ_ASC_EIR(1)), ---- a/arch/mips/lantiq/devices.h -+++ b/arch/mips/lantiq/devices.h -@@ -14,6 +14,10 @@ - - #define IRQ_RES(resname, irq) \ - {.name = #resname, .start = (irq), .flags = IORESOURCE_IRQ} -+#define MEM_RES(resname, adr_start, adr_size) \ -+ { .name = resname, .flags = IORESOURCE_MEM, \ -+ .start = ((adr_start) & ~KSEG1), \ -+ .end = ((adr_start + adr_size - 1) & ~KSEG1) } - - extern void ltq_register_nor(struct physmap_flash_data *data); - extern void ltq_register_wdt(void); ---- a/arch/mips/lantiq/prom.c -+++ b/arch/mips/lantiq/prom.c -@@ -16,6 +16,10 @@ - #include "prom.h" - #include "clk.h" - -+/* access to the ebu needs to be locked between different drivers */ -+DEFINE_SPINLOCK(ebu_lock); -+EXPORT_SYMBOL_GPL(ebu_lock); -+ - static struct ltq_soc_info soc_info; - - unsigned int ltq_get_cpu_ver(void) -@@ -55,16 +59,51 @@ static void __init prom_init_cmdline(voi - } - } - --void __init prom_init(void) -+void __iomem *ltq_remap_resource(struct resource *res) - { -- struct clk *clk; -+ __iomem void *ret = NULL; -+ struct resource *lookup = lookup_resource(&iomem_resource, res->start); - -+ if (lookup && strcmp(lookup->name, res->name)) { -+ pr_err("conflicting memory range %s\n", res->name); -+ return NULL; -+ } -+ if (!lookup) { -+ if (insert_resource(&iomem_resource, res) < 0) { -+ pr_err("Failed to insert %s memory\n", res->name); -+ return NULL; -+ } -+ } -+ if (request_mem_region(res->start, -+ resource_size(res), res->name) < 0) { -+ pr_err("Failed to request %s memory\n", res->name); -+ goto err_res; -+ } -+ -+ ret = ioremap_nocache(res->start, resource_size(res)); -+ if (!ret) -+ goto err_mem; -+ -+ pr_debug("remap: 0x%08X-0x%08X : \"%s\"\n", -+ res->start, res->end, res->name); -+ return ret; -+ -+err_mem: -+ panic("Failed to remap %s memory\n", res->name); -+ release_mem_region(res->start, resource_size(res)); -+ -+err_res: -+ release_resource(res); -+ return NULL; -+} -+EXPORT_SYMBOL(ltq_remap_resource); -+ -+void __init prom_init(void) -+{ - ltq_soc_detect(&soc_info); - clk_init(); -- clk = clk_get(0, "cpu"); -- snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev1.%d", -- soc_info.name, soc_info.rev); -- clk_put(clk); -+ snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s", -+ soc_info.name, soc_info.rev_type); - soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; - pr_info("SoC: %s\n", soc_info.sys_type); - prom_init_cmdline(); ---- a/arch/mips/lantiq/prom.h -+++ b/arch/mips/lantiq/prom.h -@@ -9,17 +9,21 @@ - #ifndef _LTQ_PROM_H__ - #define _LTQ_PROM_H__ - -+#define LTQ_SYS_REV_LEN 0x10 - #define LTQ_SYS_TYPE_LEN 0x100 - - struct ltq_soc_info { - unsigned char *name; - unsigned int rev; -+ unsigned char rev_type[LTQ_SYS_REV_LEN]; -+ unsigned int srev; - unsigned int partnum; - unsigned int type; - unsigned char sys_type[LTQ_SYS_TYPE_LEN]; - }; - - extern void ltq_soc_detect(struct ltq_soc_info *i); -+extern void ltq_soc_init(void); - extern void ltq_soc_setup(void); - - #endif ---- a/arch/mips/lantiq/xway/Makefile -+++ b/arch/mips/lantiq/xway/Makefile -@@ -1,7 +1,7 @@ --obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o -+obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o - --obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o --obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o -+obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o -+obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o - - obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o - obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o ---- a/arch/mips/lantiq/xway/devices.c -+++ b/arch/mips/lantiq/xway/devices.c -@@ -31,22 +31,9 @@ - - /* gpio */ - static struct resource ltq_gpio_resource[] = { -- { -- .name = "gpio0", -- .start = LTQ_GPIO0_BASE_ADDR, -- .end = LTQ_GPIO0_BASE_ADDR + LTQ_GPIO_SIZE - 1, -- .flags = IORESOURCE_MEM, -- }, { -- .name = "gpio1", -- .start = LTQ_GPIO1_BASE_ADDR, -- .end = LTQ_GPIO1_BASE_ADDR + LTQ_GPIO_SIZE - 1, -- .flags = IORESOURCE_MEM, -- }, { -- .name = "gpio2", -- .start = LTQ_GPIO2_BASE_ADDR, -- .end = LTQ_GPIO2_BASE_ADDR + LTQ_GPIO_SIZE - 1, -- .flags = IORESOURCE_MEM, -- } -+ MEM_RES("gpio0", LTQ_GPIO0_BASE_ADDR, LTQ_GPIO_SIZE), -+ MEM_RES("gpio1", LTQ_GPIO1_BASE_ADDR, LTQ_GPIO_SIZE), -+ MEM_RES("gpio2", LTQ_GPIO2_BASE_ADDR, LTQ_GPIO_SIZE), - }; - - void __init ltq_register_gpio(void) -@@ -64,12 +51,8 @@ void __init ltq_register_gpio(void) - } - - /* serial to parallel conversion */ --static struct resource ltq_stp_resource = { -- .name = "stp", -- .start = LTQ_STP_BASE_ADDR, -- .end = LTQ_STP_BASE_ADDR + LTQ_STP_SIZE - 1, -- .flags = IORESOURCE_MEM, --}; -+static struct resource ltq_stp_resource = -+ MEM_RES("stp", LTQ_STP_BASE_ADDR, LTQ_STP_SIZE); - - void __init ltq_register_gpio_stp(void) - { -@@ -78,12 +61,7 @@ void __init ltq_register_gpio_stp(void) - - /* asc ports - amazon se has its own serial mapping */ - static struct resource ltq_ase_asc_resources[] = { -- { -- .name = "asc0", -- .start = LTQ_ASC1_BASE_ADDR, -- .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1, -- .flags = IORESOURCE_MEM, -- }, -+ MEM_RES("asc0", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE), - IRQ_RES(tx, LTQ_ASC_ASE_TIR), - IRQ_RES(rx, LTQ_ASC_ASE_RIR), - IRQ_RES(err, LTQ_ASC_ASE_EIR), -@@ -96,12 +74,8 @@ void __init ltq_register_ase_asc(void) - } - - /* ethernet */ --static struct resource ltq_etop_resources = { -- .name = "etop", -- .start = LTQ_ETOP_BASE_ADDR, -- .end = LTQ_ETOP_BASE_ADDR + LTQ_ETOP_SIZE - 1, -- .flags = IORESOURCE_MEM, --}; -+static struct resource ltq_etop_resources = -+ MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE); - - static struct platform_device ltq_etop = { - .name = "ltq_etop", ---- a/arch/mips/lantiq/xway/dma.c -+++ b/arch/mips/lantiq/xway/dma.c -@@ -24,6 +24,8 @@ - #include - #include - -+#include "../devices.h" -+ - #define LTQ_DMA_CTRL 0x10 - #define LTQ_DMA_CPOLL 0x14 - #define LTQ_DMA_CS 0x18 -@@ -55,12 +57,8 @@ - #define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \ - ltq_dma_membase + (z)) - --static struct resource ltq_dma_resource = { -- .name = "dma", -- .start = LTQ_DMA_BASE_ADDR, -- .end = LTQ_DMA_BASE_ADDR + LTQ_DMA_SIZE - 1, -- .flags = IORESOURCE_MEM, --}; -+static struct resource ltq_dma_resource = -+ MEM_RES("dma", LTQ_DMA_BASE_ADDR, LTQ_DMA_SIZE); - - static void __iomem *ltq_dma_membase; - -@@ -220,17 +218,8 @@ ltq_dma_init(void) - { - int i; - -- /* insert and request the memory region */ -- if (insert_resource(&iomem_resource, <q_dma_resource) < 0) -- panic("Failed to insert dma memory"); -- -- if (request_mem_region(ltq_dma_resource.start, -- resource_size(<q_dma_resource), "dma") < 0) -- panic("Failed to request dma memory"); -- - /* remap dma register range */ -- ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start, -- resource_size(<q_dma_resource)); -+ ltq_dma_membase = ltq_remap_resource(<q_dma_resource); - if (!ltq_dma_membase) - panic("Failed to remap dma memory"); - ---- a/arch/mips/lantiq/xway/ebu.c -+++ /dev/null -@@ -1,52 +0,0 @@ --/* -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- * -- * EBU - the external bus unit attaches PCI, NOR and NAND -- * -- * Copyright (C) 2010 John Crispin -- */ -- --#include --#include --#include -- --#include -- --/* all access to the ebu must be locked */ --DEFINE_SPINLOCK(ebu_lock); --EXPORT_SYMBOL_GPL(ebu_lock); -- --static struct resource ltq_ebu_resource = { -- .name = "ebu", -- .start = LTQ_EBU_BASE_ADDR, -- .end = LTQ_EBU_BASE_ADDR + LTQ_EBU_SIZE - 1, -- .flags = IORESOURCE_MEM, --}; -- --/* remapped base addr of the clock unit and external bus unit */ --void __iomem *ltq_ebu_membase; -- --static int __init lantiq_ebu_init(void) --{ -- /* insert and request the memory region */ -- if (insert_resource(&iomem_resource, <q_ebu_resource) < 0) -- panic("Failed to insert ebu memory"); -- -- if (request_mem_region(ltq_ebu_resource.start, -- resource_size(<q_ebu_resource), "ebu") < 0) -- panic("Failed to request ebu memory"); -- -- /* remap ebu register range */ -- ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start, -- resource_size(<q_ebu_resource)); -- if (!ltq_ebu_membase) -- panic("Failed to remap ebu memory"); -- -- /* make sure to unprotect the memory region where flash is located */ -- ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); -- return 0; --} -- --postcore_initcall(lantiq_ebu_init); ---- a/arch/mips/lantiq/xway/pmu.c -+++ /dev/null -@@ -1,69 +0,0 @@ --/* -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- * -- * Copyright (C) 2010 John Crispin -- */ -- --#include --#include --#include -- --#include -- --/* PMU - the power management unit allows us to turn part of the core -- * on and off -- */ -- --/* the enable / disable registers */ --#define LTQ_PMU_PWDCR 0x1C --#define LTQ_PMU_PWDSR 0x20 -- --#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y)) --#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x)) -- --static struct resource ltq_pmu_resource = { -- .name = "pmu", -- .start = LTQ_PMU_BASE_ADDR, -- .end = LTQ_PMU_BASE_ADDR + LTQ_PMU_SIZE - 1, -- .flags = IORESOURCE_MEM, --}; -- --static void __iomem *ltq_pmu_membase; -- --void ltq_pmu_enable(unsigned int module) --{ -- int err = 1000000; -- -- ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR); -- do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module)); -- -- if (!err) -- panic("activating PMU module failed!"); --} --EXPORT_SYMBOL(ltq_pmu_enable); -- --void ltq_pmu_disable(unsigned int module) --{ -- ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR); --} --EXPORT_SYMBOL(ltq_pmu_disable); -- --int __init ltq_pmu_init(void) --{ -- if (insert_resource(&iomem_resource, <q_pmu_resource) < 0) -- panic("Failed to insert pmu memory"); -- -- if (request_mem_region(ltq_pmu_resource.start, -- resource_size(<q_pmu_resource), "pmu") < 0) -- panic("Failed to request pmu memory"); -- -- ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start, -- resource_size(<q_pmu_resource)); -- if (!ltq_pmu_membase) -- panic("Failed to remap pmu memory"); -- return 0; --} -- --core_initcall(ltq_pmu_init); ---- a/arch/mips/lantiq/xway/prom-ase.c -+++ b/arch/mips/lantiq/xway/prom-ase.c -@@ -13,6 +13,7 @@ - - #include - -+#include "devices.h" - #include "../prom.h" - - #define SOC_AMAZON_SE "Amazon_SE" -@@ -26,6 +27,7 @@ void __init ltq_soc_detect(struct ltq_so - { - i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; - i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; -+ sprintf(i->rev_type, "1.%d", i->rev); - switch (i->partnum) { - case SOC_ID_AMAZON_SE: - i->name = SOC_AMAZON_SE; -@@ -37,3 +39,10 @@ void __init ltq_soc_detect(struct ltq_so - break; - } - } -+ -+void __init ltq_soc_setup(void) -+{ -+ ltq_register_ase_asc(); -+ ltq_register_gpio(); -+ ltq_register_wdt(); -+} ---- a/arch/mips/lantiq/xway/prom-xway.c -+++ b/arch/mips/lantiq/xway/prom-xway.c -@@ -13,6 +13,7 @@ - - #include - -+#include "devices.h" - #include "../prom.h" - - #define SOC_DANUBE "Danube" -@@ -28,6 +29,7 @@ void __init ltq_soc_detect(struct ltq_so - { - i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; - i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; -+ sprintf(i->rev_type, "1.%d", i->rev); - switch (i->partnum) { - case SOC_ID_DANUBE1: - case SOC_ID_DANUBE2: -@@ -52,3 +54,11 @@ void __init ltq_soc_detect(struct ltq_so - break; - } - } -+ -+void __init ltq_soc_setup(void) -+{ -+ ltq_register_asc(0); -+ ltq_register_asc(1); -+ ltq_register_gpio(); -+ ltq_register_wdt(); -+} ---- a/arch/mips/lantiq/xway/reset.c -+++ b/arch/mips/lantiq/xway/reset.c -@@ -15,6 +15,8 @@ - - #include - -+#include "../devices.h" -+ - #define ltq_rcu_w32(x, y) ltq_w32((x), ltq_rcu_membase + (y)) - #define ltq_rcu_r32(x) ltq_r32(ltq_rcu_membase + (x)) - -@@ -25,12 +27,8 @@ - #define LTQ_RCU_RST_STAT 0x0014 - #define LTQ_RCU_STAT_SHIFT 26 - --static struct resource ltq_rcu_resource = { -- .name = "rcu", -- .start = LTQ_RCU_BASE_ADDR, -- .end = LTQ_RCU_BASE_ADDR + LTQ_RCU_SIZE - 1, -- .flags = IORESOURCE_MEM, --}; -+static struct resource ltq_rcu_resource = -+ MEM_RES("rcu", LTQ_RCU_BASE_ADDR, LTQ_RCU_SIZE); - - /* remapped base addr of the reset control unit */ - static void __iomem *ltq_rcu_membase; -@@ -67,17 +65,8 @@ static void ltq_machine_power_off(void) - - static int __init mips_reboot_setup(void) - { -- /* insert and request the memory region */ -- if (insert_resource(&iomem_resource, <q_rcu_resource) < 0) -- panic("Failed to insert rcu memory"); -- -- if (request_mem_region(ltq_rcu_resource.start, -- resource_size(<q_rcu_resource), "rcu") < 0) -- panic("Failed to request rcu memory"); -- - /* remap rcu register range */ -- ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start, -- resource_size(<q_rcu_resource)); -+ ltq_rcu_membase = ltq_remap_resource(<q_rcu_resource); - if (!ltq_rcu_membase) - panic("Failed to remap rcu memory"); - ---- a/arch/mips/lantiq/xway/setup-ase.c -+++ /dev/null -@@ -1,19 +0,0 @@ --/* -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- * -- * Copyright (C) 2011 John Crispin -- */ -- --#include -- --#include "../prom.h" --#include "devices.h" -- --void __init ltq_soc_setup(void) --{ -- ltq_register_ase_asc(); -- ltq_register_gpio(); -- ltq_register_wdt(); --} ---- a/arch/mips/lantiq/xway/setup-xway.c -+++ /dev/null -@@ -1,20 +0,0 @@ --/* -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- * -- * Copyright (C) 2011 John Crispin -- */ -- --#include -- --#include "../prom.h" --#include "devices.h" -- --void __init ltq_soc_setup(void) --{ -- ltq_register_asc(0); -- ltq_register_asc(1); -- ltq_register_gpio(); -- ltq_register_wdt(); --} ---- /dev/null -+++ b/arch/mips/lantiq/xway/sysctrl.c -@@ -0,0 +1,78 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2011 John Crispin -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "../devices.h" -+ -+/* clock control register */ -+#define LTQ_CGU_IFCCR 0x0018 -+ -+/* the enable / disable registers */ -+#define LTQ_PMU_PWDCR 0x1C -+#define LTQ_PMU_PWDSR 0x20 -+ -+#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y)) -+#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x)) -+ -+static struct resource ltq_cgu_resource = -+ MEM_RES("cgu", LTQ_CGU_BASE_ADDR, LTQ_CGU_SIZE); -+ -+static struct resource ltq_pmu_resource = -+ MEM_RES("pmu", LTQ_PMU_BASE_ADDR, LTQ_PMU_SIZE); -+ -+static struct resource ltq_ebu_resource = -+ MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE); -+ -+void __iomem *ltq_cgu_membase; -+void __iomem *ltq_ebu_membase; -+static void __iomem *ltq_pmu_membase; -+ -+void ltq_cgu_enable(unsigned int clk) -+{ -+ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk, LTQ_CGU_IFCCR); -+} -+ -+void ltq_pmu_enable(unsigned int module) -+{ -+ int err = 1000000; -+ -+ ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR); -+ do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module)); -+ -+ if (!err) -+ panic("activating PMU module failed!\n"); -+} -+EXPORT_SYMBOL(ltq_pmu_enable); -+ -+void ltq_pmu_disable(unsigned int module) -+{ -+ ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR); -+} -+EXPORT_SYMBOL(ltq_pmu_disable); -+ -+void __init ltq_soc_init(void) -+{ -+ ltq_pmu_membase = ltq_remap_resource(<q_pmu_resource); -+ if (!ltq_pmu_membase) -+ panic("Failed to remap pmu memory\n"); -+ -+ ltq_cgu_membase = ltq_remap_resource(<q_cgu_resource); -+ if (!ltq_cgu_membase) -+ panic("Failed to remap cgu memory\n"); -+ -+ ltq_ebu_membase = ltq_remap_resource(<q_ebu_resource); -+ if (!ltq_ebu_membase) -+ panic("Failed to remap ebu memory\n"); -+ -+ /* make sure to unprotect the memory region where flash is located */ -+ ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); -+} ---- a/drivers/watchdog/lantiq_wdt.c -+++ b/drivers/watchdog/lantiq_wdt.c -@@ -16,7 +16,7 @@ - #include - #include - --#include -+#include - - /* Section 3.4 of the datasheet - * The password sequence protects the WDT control register from unintended diff --git a/target/linux/lantiq/patches-3.3/0002-xway-support.patch b/target/linux/lantiq/patches-3.3/0002-xway-support.patch new file mode 100644 index 0000000000..b3b9599eea --- /dev/null +++ b/target/linux/lantiq/patches-3.3/0002-xway-support.patch @@ -0,0 +1,1586 @@ +From cf678877a86e03302686d0364c982d573daa6e2c Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 09:49:04 +0200 +Subject: [PATCH 02/25] xway support + +--- + .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 31 +-- + .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 96 +++++++-- + arch/mips/lantiq/xway/Kconfig | 21 ++ + arch/mips/lantiq/xway/Makefile | 5 +- + arch/mips/lantiq/xway/clk-ase.c | 48 ----- + arch/mips/lantiq/xway/clk-xway.c | 223 -------------------- + arch/mips/lantiq/xway/devices.c | 72 ++++--- + arch/mips/lantiq/xway/devices.h | 2 + + arch/mips/lantiq/xway/dma.c | 27 +-- + arch/mips/lantiq/xway/ebu.c | 52 ----- + arch/mips/lantiq/xway/gpio.c | 92 +++++++-- + arch/mips/lantiq/xway/gpio_ebu.c | 3 +- + arch/mips/lantiq/xway/gpio_stp.c | 49 +++-- + arch/mips/lantiq/xway/mach-easy50601.c | 15 +- + arch/mips/lantiq/xway/mach-easy50712.c | 17 +- + arch/mips/lantiq/xway/pmu.c | 69 ------ + arch/mips/lantiq/xway/prom-ase.c | 39 ---- + arch/mips/lantiq/xway/prom-xway.c | 54 ----- + arch/mips/lantiq/xway/reset.c | 92 ++++++--- + arch/mips/lantiq/xway/setup-ase.c | 19 -- + arch/mips/lantiq/xway/setup-xway.c | 20 -- + 21 files changed, 349 insertions(+), 697 deletions(-) + delete mode 100644 arch/mips/lantiq/xway/clk-ase.c + delete mode 100644 arch/mips/lantiq/xway/clk-xway.c + delete mode 100644 arch/mips/lantiq/xway/ebu.c + delete mode 100644 arch/mips/lantiq/xway/pmu.c + delete mode 100644 arch/mips/lantiq/xway/prom-ase.c + delete mode 100644 arch/mips/lantiq/xway/prom-xway.c + delete mode 100644 arch/mips/lantiq/xway/setup-ase.c + delete mode 100644 arch/mips/lantiq/xway/setup-xway.c + +diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h +index b4465a8..4f69ff0 100644 +--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h +@@ -9,6 +9,8 @@ + #ifndef _LANTIQ_XWAY_IRQ_H__ + #define _LANTIQ_XWAY_IRQ_H__ + ++#define IM_NUM 5 ++ + #define INT_NUM_IRQ0 8 + #define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) + #define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32) +@@ -27,37 +29,26 @@ + + #define LTQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15) + #define LTQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14) ++#define LTQ_SSC_TIR_AR9 (INT_NUM_IM0_IRL0 + 14) ++#define LTQ_SSC_RIR_AR9 (INT_NUM_IM0_IRL0 + 15) + #define LTQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16) ++#define LTQ_SSC_RIR_ASE (INT_NUM_IM0_IRL0 + 16) ++#define LTQ_SSC_TIR_ASE (INT_NUM_IM0_IRL0 + 17) ++#define LTQ_SSC_EIR_ASE (INT_NUM_IM0_IRL0 + 18) ++#define LTQ_SSC_FIR_ASE (INT_NUM_IM0_IRL0 + 19) + + #define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21) + #define LTQ_MEI_INT (INT_NUM_IM1_IRL0 + 23) + + #define LTQ_TIMER6_INT (INT_NUM_IM1_IRL0 + 23) + #define LTQ_USB_INT (INT_NUM_IM1_IRL0 + 22) ++#define LTQ_USB_ASE_INT (INT_NUM_IM0_IRL0 + 31) + #define LTQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23) + + #define MIPS_CPU_TIMER_IRQ 7 + +-#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0) +-#define LTQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1) +-#define LTQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2) +-#define LTQ_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3) +-#define LTQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4) +-#define LTQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5) +-#define LTQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6) +-#define LTQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7) +-#define LTQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8) +-#define LTQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9) +-#define LTQ_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10) +-#define LTQ_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11) +-#define LTQ_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25) +-#define LTQ_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26) +-#define LTQ_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27) +-#define LTQ_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28) +-#define LTQ_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29) +-#define LTQ_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30) +-#define LTQ_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16) +-#define LTQ_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21) ++#define LTQ_DMA_ETOP ((ltq_is_ase()) ? \ ++ (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0)) + + #define LTQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24) + +diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +index 8a3c6be..1ec8f2a 100644 +--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +@@ -17,23 +17,44 @@ + #define SOC_ID_DANUBE1 0x129 + #define SOC_ID_DANUBE2 0x12B + #define SOC_ID_TWINPASS 0x12D +-#define SOC_ID_AMAZON_SE 0x152 ++#define SOC_ID_AMAZON_SE_1 0x152 /* 50601 */ ++#define SOC_ID_AMAZON_SE_2 0x153 /* 50600 */ + #define SOC_ID_ARX188 0x16C +-#define SOC_ID_ARX168 0x16D ++#define SOC_ID_ARX168_1 0x16D ++#define SOC_ID_ARX168_2 0x16E + #define SOC_ID_ARX182 0x16F ++#define SOC_ID_GRX188 0x170 ++#define SOC_ID_GRX168 0x171 ++ ++#define SOC_ID_VRX288 0x1C0 /* v1.1 */ ++#define SOC_ID_VRX282 0x1C1 /* v1.1 */ ++#define SOC_ID_VRX268 0x1C2 /* v1.1 */ ++#define SOC_ID_GRX268 0x1C8 /* v1.1 */ ++#define SOC_ID_GRX288 0x1C9 /* v1.1 */ ++#define SOC_ID_VRX288_2 0x00B /* v1.2 */ ++#define SOC_ID_VRX268_2 0x00C /* v1.2 */ ++#define SOC_ID_GRX288_2 0x00D /* v1.2 */ ++#define SOC_ID_GRX282_2 0x00E /* v1.2 */ + + /* SoC Types */ + #define SOC_TYPE_DANUBE 0x01 + #define SOC_TYPE_TWINPASS 0x02 + #define SOC_TYPE_AR9 0x03 +-#define SOC_TYPE_VR9 0x04 +-#define SOC_TYPE_AMAZON_SE 0x05 ++#define SOC_TYPE_VR9_1 0x04 /* v1.1 */ ++#define SOC_TYPE_VR9_2 0x05 /* v1.2 */ ++#define SOC_TYPE_AMAZON_SE 0x06 + + /* ASC0/1 - serial port */ + #define LTQ_ASC0_BASE_ADDR 0x1E100400 + #define LTQ_ASC1_BASE_ADDR 0x1E100C00 + #define LTQ_ASC_SIZE 0x400 + ++/* ++ * during early_printk no ioremap is possible ++ * lets use KSEG1 instead ++ */ ++#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR) ++ + /* RCU - reset control unit */ + #define LTQ_RCU_BASE_ADDR 0x1F203000 + #define LTQ_RCU_SIZE 0x1000 +@@ -61,6 +82,8 @@ + #define LTQ_CGU_BASE_ADDR 0x1F103000 + #define LTQ_CGU_SIZE 0x1000 + ++#define CGU_EPHY 0x10 ++ + /* ICU - interrupt control unit */ + #define LTQ_ICU_BASE_ADDR 0x1F880200 + #define LTQ_ICU_SIZE 0x100 +@@ -73,18 +96,14 @@ + #define LTQ_PMU_BASE_ADDR 0x1F102000 + #define LTQ_PMU_SIZE 0x1000 + +-#define PMU_DMA 0x0020 +-#define PMU_USB 0x8041 +-#define PMU_LED 0x0800 +-#define PMU_GPT 0x1000 +-#define PMU_PPE 0x2000 +-#define PMU_FPI 0x4000 +-#define PMU_SWITCH 0x10000000 +- + /* ETOP - ethernet */ + #define LTQ_ETOP_BASE_ADDR 0x1E180000 + #define LTQ_ETOP_SIZE 0x40000 + ++/* GBIT - gigabit switch */ ++#define LTQ_GBIT_BASE_ADDR 0x1E108000 ++#define LTQ_GBIT_SIZE 0x4000 ++ + /* DMA */ + #define LTQ_DMA_BASE_ADDR 0x1E104100 + #define LTQ_DMA_SIZE 0x800 +@@ -97,6 +116,8 @@ + #define LTQ_WDT_BASE_ADDR 0x1F8803F0 + #define LTQ_WDT_SIZE 0x10 + ++#define LTQ_RST_CAUSE_WDTRST 0x20 ++ + /* STP - serial to parallel conversion unit */ + #define LTQ_STP_BASE_ADDR 0x1E100BB0 + #define LTQ_STP_SIZE 0x40 +@@ -105,7 +126,9 @@ + #define LTQ_GPIO0_BASE_ADDR 0x1E100B10 + #define LTQ_GPIO1_BASE_ADDR 0x1E100B40 + #define LTQ_GPIO2_BASE_ADDR 0x1E100B70 ++#define LTQ_GPIO3_BASE_ADDR 0x1E100BA0 + #define LTQ_GPIO_SIZE 0x30 ++#define LTQ_GPIO3_SIZE 0x10 + + /* SSC */ + #define LTQ_SSC_BASE_ADDR 0x1e100800 +@@ -121,20 +144,57 @@ + #define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000) + #define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344)) + +-/* request a non-gpio and set the PIO config */ +-extern int ltq_gpio_request(unsigned int pin, unsigned int alt0, +- unsigned int alt1, unsigned int dir, const char *name); +-extern void ltq_pmu_enable(unsigned int module); +-extern void ltq_pmu_disable(unsigned int module); ++/* BOOT_SEL - find what boot media we have */ ++#define BS_EXT_ROM 0x0 ++#define BS_FLASH 0x1 ++#define BS_MII0 0x2 ++#define BS_PCI 0x3 ++#define BS_UART1 0x4 ++#define BS_SPI 0x5 ++#define BS_NAND 0x6 ++#define BS_RMII0 0x7 ++ ++extern unsigned char ltq_boot_select(void); ++ ++/* register access macros for EBU and CGU */ ++#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) ++#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) ++#define ltq_ebu_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, ltq_ebu_membase + (z)) ++#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y)) ++#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x)) ++ ++extern __iomem void *ltq_ebu_membase; ++extern __iomem void *ltq_cgu_membase; ++ ++static inline int ltq_is_ase(void) ++{ ++ return (ltq_get_soc_type() == SOC_TYPE_AMAZON_SE); ++} + + static inline int ltq_is_ar9(void) + { + return (ltq_get_soc_type() == SOC_TYPE_AR9); + } + ++static inline int ltq_is_vr9_1(void) ++{ ++ return (ltq_get_soc_type() == SOC_TYPE_VR9_1); ++} ++ ++static inline int ltq_is_vr9_2(void) ++{ ++ return (ltq_get_soc_type() == SOC_TYPE_VR9_2); ++} ++ + static inline int ltq_is_vr9(void) + { +- return (ltq_get_soc_type() == SOC_TYPE_VR9); ++ return (ltq_is_vr9_1() || ltq_is_vr9_2()); ++} ++ ++static inline int ltq_is_falcon(void) ++{ ++ return 0; + } + + #endif /* CONFIG_SOC_TYPE_XWAY */ +diff --git a/arch/mips/lantiq/xway/Kconfig b/arch/mips/lantiq/xway/Kconfig +index 2b857de..54a51ff 100644 +--- a/arch/mips/lantiq/xway/Kconfig ++++ b/arch/mips/lantiq/xway/Kconfig +@@ -8,6 +8,27 @@ config LANTIQ_MACH_EASY50712 + + endmenu + ++choice ++ prompt "PCI" ++ default PCI_LANTIQ_NONE ++ ++config PCI_LANTIQ_NONE ++ bool "None" ++ ++config PCI_LANTIQ ++ bool "PCI Support" ++ depends on PCI ++ ++config PCIE_LANTIQ ++ bool "PCIE Support" ++ select ARCH_SUPPORTS_MSI ++ ++endchoice ++ ++config PCIE_LANTIQ_MSI ++ bool ++ depends on PCIE_LANTIQ && PCI_MSI ++ default y + endif + + if SOC_AMAZON_SE +diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile +index c517f2e..c9baf91 100644 +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -1,7 +1,4 @@ +-obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o +- +-obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o +-obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o ++obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o timer.o dev-ifxhcd.o + + obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o + obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o +diff --git a/arch/mips/lantiq/xway/clk-ase.c b/arch/mips/lantiq/xway/clk-ase.c +deleted file mode 100644 +index 6522583..0000000 +--- a/arch/mips/lantiq/xway/clk-ase.c ++++ /dev/null +@@ -1,48 +0,0 @@ +-/* +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- * +- * Copyright (C) 2011 John Crispin +- */ +- +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +- +-#include +- +-/* cgu registers */ +-#define LTQ_CGU_SYS 0x0010 +- +-unsigned int ltq_get_io_region_clock(void) +-{ +- return CLOCK_133M; +-} +-EXPORT_SYMBOL(ltq_get_io_region_clock); +- +-unsigned int ltq_get_fpi_bus_clock(int fpi) +-{ +- return CLOCK_133M; +-} +-EXPORT_SYMBOL(ltq_get_fpi_bus_clock); +- +-unsigned int ltq_get_cpu_hz(void) +-{ +- if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5)) +- return CLOCK_266M; +- else +- return CLOCK_133M; +-} +-EXPORT_SYMBOL(ltq_get_cpu_hz); +- +-unsigned int ltq_get_fpi_hz(void) +-{ +- return CLOCK_133M; +-} +-EXPORT_SYMBOL(ltq_get_fpi_hz); +diff --git a/arch/mips/lantiq/xway/clk-xway.c b/arch/mips/lantiq/xway/clk-xway.c +deleted file mode 100644 +index 696b1a3..0000000 +--- a/arch/mips/lantiq/xway/clk-xway.c ++++ /dev/null +@@ -1,223 +0,0 @@ +-/* +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- * +- * Copyright (C) 2010 John Crispin +- */ +- +-#include +-#include +-#include +-#include +- +-#include +-#include +-#include +- +-#include +- +-static unsigned int ltq_ram_clocks[] = { +- CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M }; +-#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3] +- +-#define BASIC_FREQUENCY_1 35328000 +-#define BASIC_FREQUENCY_2 36000000 +-#define BASIS_REQUENCY_USB 12000000 +- +-#define GET_BITS(x, msb, lsb) \ +- (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) +- +-#define LTQ_CGU_PLL0_CFG 0x0004 +-#define LTQ_CGU_PLL1_CFG 0x0008 +-#define LTQ_CGU_PLL2_CFG 0x000C +-#define LTQ_CGU_SYS 0x0010 +-#define LTQ_CGU_UPDATE 0x0014 +-#define LTQ_CGU_IF_CLK 0x0018 +-#define LTQ_CGU_OSC_CON 0x001C +-#define LTQ_CGU_SMD 0x0020 +-#define LTQ_CGU_CT1SR 0x0028 +-#define LTQ_CGU_CT2SR 0x002C +-#define LTQ_CGU_PCMCR 0x0030 +-#define LTQ_CGU_PCI_CR 0x0034 +-#define LTQ_CGU_PD_PC 0x0038 +-#define LTQ_CGU_FMR 0x003C +- +-#define CGU_PLL0_PHASE_DIVIDER_ENABLE \ +- (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31)) +-#define CGU_PLL0_BYPASS \ +- (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30)) +-#define CGU_PLL0_CFG_DSMSEL \ +- (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28)) +-#define CGU_PLL0_CFG_FRAC_EN \ +- (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27)) +-#define CGU_PLL1_SRC \ +- (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31)) +-#define CGU_PLL2_PHASE_DIVIDER_ENABLE \ +- (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20)) +-#define CGU_SYS_FPI_SEL (1 << 6) +-#define CGU_SYS_DDR_SEL 0x3 +-#define CGU_PLL0_SRC (1 << 29) +- +-#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17) +-#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6) +-#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2) +-#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17) +-#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13) +- +-static unsigned int ltq_get_pll0_fdiv(void); +- +-static inline unsigned int get_input_clock(int pll) +-{ +- switch (pll) { +- case 0: +- if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC) +- return BASIS_REQUENCY_USB; +- else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) +- return BASIC_FREQUENCY_1; +- else +- return BASIC_FREQUENCY_2; +- case 1: +- if (CGU_PLL1_SRC) +- return BASIS_REQUENCY_USB; +- else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) +- return BASIC_FREQUENCY_1; +- else +- return BASIC_FREQUENCY_2; +- case 2: +- switch (CGU_PLL2_SRC) { +- case 0: +- return ltq_get_pll0_fdiv(); +- case 1: +- return CGU_PLL2_PHASE_DIVIDER_ENABLE ? +- BASIC_FREQUENCY_1 : +- BASIC_FREQUENCY_2; +- case 2: +- return BASIS_REQUENCY_USB; +- } +- default: +- return 0; +- } +-} +- +-static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den) +-{ +- u64 res, clock = get_input_clock(pll); +- +- res = num * clock; +- do_div(res, den); +- return res; +-} +- +-static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N, +- unsigned int K) +-{ +- unsigned int num = ((N + 1) << 10) + K; +- unsigned int den = (M + 1) << 10; +- +- return cal_dsm(pll, num, den); +-} +- +-static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N, +- unsigned int K) +-{ +- unsigned int num = ((N + 1) << 11) + K + 512; +- unsigned int den = (M + 1) << 11; +- +- return cal_dsm(pll, num, den); +-} +- +-static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N, +- unsigned int K) +-{ +- unsigned int num = K >= 512 ? +- ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584; +- unsigned int den = (M + 1) << 12; +- +- return cal_dsm(pll, num, den); +-} +- +-static inline unsigned int dsm(int pll, unsigned int M, unsigned int N, +- unsigned int K, unsigned int dsmsel, unsigned int phase_div_en) +-{ +- if (!dsmsel) +- return mash_dsm(pll, M, N, K); +- else if (!phase_div_en) +- return mash_dsm(pll, M, N, K); +- else +- return ssff_dsm_2(pll, M, N, K); +-} +- +-static inline unsigned int ltq_get_pll0_fosc(void) +-{ +- if (CGU_PLL0_BYPASS) +- return get_input_clock(0); +- else +- return !CGU_PLL0_CFG_FRAC_EN +- ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, +- CGU_PLL0_CFG_DSMSEL, +- CGU_PLL0_PHASE_DIVIDER_ENABLE) +- : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, +- CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL, +- CGU_PLL0_PHASE_DIVIDER_ENABLE); +-} +- +-static unsigned int ltq_get_pll0_fdiv(void) +-{ +- unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1; +- +- return (ltq_get_pll0_fosc() + (div >> 1)) / div; +-} +- +-unsigned int ltq_get_io_region_clock(void) +-{ +- unsigned int ret = ltq_get_pll0_fosc(); +- +- switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) { +- default: +- case 0: +- return (ret + 1) / 2; +- case 1: +- return (ret * 2 + 2) / 5; +- case 2: +- return (ret + 1) / 3; +- case 3: +- return (ret + 2) / 4; +- } +-} +-EXPORT_SYMBOL(ltq_get_io_region_clock); +- +-unsigned int ltq_get_fpi_bus_clock(int fpi) +-{ +- unsigned int ret = ltq_get_io_region_clock(); +- +- if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL)) +- ret >>= 1; +- return ret; +-} +-EXPORT_SYMBOL(ltq_get_fpi_bus_clock); +- +-unsigned int ltq_get_cpu_hz(void) +-{ +- switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) { +- case 0: +- return CLOCK_333M; +- case 4: +- return DDR_HZ; +- case 8: +- return DDR_HZ << 1; +- default: +- return DDR_HZ >> 1; +- } +-} +-EXPORT_SYMBOL(ltq_get_cpu_hz); +- +-unsigned int ltq_get_fpi_hz(void) +-{ +- unsigned int ddr_clock = DDR_HZ; +- +- if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40) +- return ddr_clock >> 1; +- return ddr_clock; +-} +-EXPORT_SYMBOL(ltq_get_fpi_hz); +diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c +index d614aa7..5d4650d 100644 +--- a/arch/mips/lantiq/xway/devices.c ++++ b/arch/mips/lantiq/xway/devices.c +@@ -31,22 +31,10 @@ + + /* gpio */ + static struct resource ltq_gpio_resource[] = { +- { +- .name = "gpio0", +- .start = LTQ_GPIO0_BASE_ADDR, +- .end = LTQ_GPIO0_BASE_ADDR + LTQ_GPIO_SIZE - 1, +- .flags = IORESOURCE_MEM, +- }, { +- .name = "gpio1", +- .start = LTQ_GPIO1_BASE_ADDR, +- .end = LTQ_GPIO1_BASE_ADDR + LTQ_GPIO_SIZE - 1, +- .flags = IORESOURCE_MEM, +- }, { +- .name = "gpio2", +- .start = LTQ_GPIO2_BASE_ADDR, +- .end = LTQ_GPIO2_BASE_ADDR + LTQ_GPIO_SIZE - 1, +- .flags = IORESOURCE_MEM, +- } ++ MEM_RES("gpio0", LTQ_GPIO0_BASE_ADDR, LTQ_GPIO_SIZE), ++ MEM_RES("gpio1", LTQ_GPIO1_BASE_ADDR, LTQ_GPIO_SIZE), ++ MEM_RES("gpio2", LTQ_GPIO2_BASE_ADDR, LTQ_GPIO_SIZE), ++ MEM_RES("gpio3", LTQ_GPIO3_BASE_ADDR, LTQ_GPIO3_SIZE), + }; + + void __init ltq_register_gpio(void) +@@ -60,30 +48,23 @@ void __init ltq_register_gpio(void) + if (ltq_is_ar9() || ltq_is_vr9()) { + platform_device_register_simple("ltq_gpio", 2, + <q_gpio_resource[2], 1); ++ platform_device_register_simple("ltq_gpio", 3, ++ <q_gpio_resource[3], 1); + } + } + + /* serial to parallel conversion */ +-static struct resource ltq_stp_resource = { +- .name = "stp", +- .start = LTQ_STP_BASE_ADDR, +- .end = LTQ_STP_BASE_ADDR + LTQ_STP_SIZE - 1, +- .flags = IORESOURCE_MEM, +-}; ++static struct resource ltq_stp_resource = ++ MEM_RES("stp", LTQ_STP_BASE_ADDR, LTQ_STP_SIZE); + + void __init ltq_register_gpio_stp(void) + { +- platform_device_register_simple("ltq_stp", 0, <q_stp_resource, 1); ++ platform_device_register_simple("ltq_stp", -1, <q_stp_resource, 1); + } + + /* asc ports - amazon se has its own serial mapping */ + static struct resource ltq_ase_asc_resources[] = { +- { +- .name = "asc0", +- .start = LTQ_ASC1_BASE_ADDR, +- .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1, +- .flags = IORESOURCE_MEM, +- }, ++ MEM_RES("asc0", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE), + IRQ_RES(tx, LTQ_ASC_ASE_TIR), + IRQ_RES(rx, LTQ_ASC_ASE_RIR), + IRQ_RES(err, LTQ_ASC_ASE_EIR), +@@ -96,24 +77,45 @@ void __init ltq_register_ase_asc(void) + } + + /* ethernet */ +-static struct resource ltq_etop_resources = { +- .name = "etop", +- .start = LTQ_ETOP_BASE_ADDR, +- .end = LTQ_ETOP_BASE_ADDR + LTQ_ETOP_SIZE - 1, +- .flags = IORESOURCE_MEM, ++static struct resource ltq_etop_resources[] = { ++ MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE), ++ MEM_RES("gbit", LTQ_GBIT_BASE_ADDR, LTQ_GBIT_SIZE), + }; + + static struct platform_device ltq_etop = { + .name = "ltq_etop", +- .resource = <q_etop_resources, ++ .resource = ltq_etop_resources, + .num_resources = 1, ++ .id = -1, + }; + + void __init + ltq_register_etop(struct ltq_eth_data *eth) + { ++ /* only register the gphy on socs that have one */ ++ if (ltq_is_ar9() | ltq_is_vr9()) ++ ltq_etop.num_resources = 2; + if (eth) { + ltq_etop.dev.platform_data = eth; + platform_device_register(<q_etop); + } + } ++ ++/* ethernet */ ++static struct resource ltq_vrx200_resources[] = { ++ MEM_RES("gbit", LTQ_GBIT_BASE_ADDR, LTQ_GBIT_SIZE), ++}; ++ ++static struct platform_device ltq_vrx200 = { ++ .name = "ltq_vrx200", ++ .resource = ltq_vrx200_resources, ++ .num_resources = 1, ++ .id = -1, ++}; ++ ++void __init ++ltq_register_vrx200(struct ltq_eth_data *eth) ++{ ++ ltq_vrx200.dev.platform_data = eth; ++ platform_device_register(<q_vrx200); ++} +diff --git a/arch/mips/lantiq/xway/devices.h b/arch/mips/lantiq/xway/devices.h +index e904934..08befd9 100644 +--- a/arch/mips/lantiq/xway/devices.h ++++ b/arch/mips/lantiq/xway/devices.h +@@ -16,5 +16,7 @@ extern void ltq_register_gpio(void); + extern void ltq_register_gpio_stp(void); + extern void ltq_register_ase_asc(void); + extern void ltq_register_etop(struct ltq_eth_data *eth); ++extern void xway_register_nand(struct mtd_partition *parts, int count); ++extern void ltq_register_vrx200(struct ltq_eth_data *eth); + + #endif +diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c +index b210e93..ce86529 100644 +--- a/arch/mips/lantiq/xway/dma.c ++++ b/arch/mips/lantiq/xway/dma.c +@@ -20,10 +20,13 @@ + #include + #include + #include ++#include + + #include + #include + ++#include "../devices.h" ++ + #define LTQ_DMA_CTRL 0x10 + #define LTQ_DMA_CPOLL 0x14 + #define LTQ_DMA_CS 0x18 +@@ -55,12 +58,8 @@ + #define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \ + ltq_dma_membase + (z)) + +-static struct resource ltq_dma_resource = { +- .name = "dma", +- .start = LTQ_DMA_BASE_ADDR, +- .end = LTQ_DMA_BASE_ADDR + LTQ_DMA_SIZE - 1, +- .flags = IORESOURCE_MEM, +-}; ++static struct resource ltq_dma_resource = ++ MEM_RES("dma", LTQ_DMA_BASE_ADDR, LTQ_DMA_SIZE); + + static void __iomem *ltq_dma_membase; + +@@ -218,24 +217,18 @@ EXPORT_SYMBOL_GPL(ltq_dma_init_port); + int __init + ltq_dma_init(void) + { ++ struct clk *clk; + int i; + +- /* insert and request the memory region */ +- if (insert_resource(&iomem_resource, <q_dma_resource) < 0) +- panic("Failed to insert dma memory"); +- +- if (request_mem_region(ltq_dma_resource.start, +- resource_size(<q_dma_resource), "dma") < 0) +- panic("Failed to request dma memory"); +- + /* remap dma register range */ +- ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start, +- resource_size(<q_dma_resource)); ++ ltq_dma_membase = ltq_remap_resource(<q_dma_resource); + if (!ltq_dma_membase) + panic("Failed to remap dma memory"); + + /* power up and reset the dma engine */ +- ltq_pmu_enable(PMU_DMA); ++ clk = clk_get_sys("ltq_dma", NULL); ++ WARN_ON(!clk); ++ clk_enable(clk); + ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL); + + /* disable all interrupts */ +diff --git a/arch/mips/lantiq/xway/ebu.c b/arch/mips/lantiq/xway/ebu.c +deleted file mode 100644 +index 862e3e8..0000000 +--- a/arch/mips/lantiq/xway/ebu.c ++++ /dev/null +@@ -1,52 +0,0 @@ +-/* +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- * +- * EBU - the external bus unit attaches PCI, NOR and NAND +- * +- * Copyright (C) 2010 John Crispin +- */ +- +-#include +-#include +-#include +- +-#include +- +-/* all access to the ebu must be locked */ +-DEFINE_SPINLOCK(ebu_lock); +-EXPORT_SYMBOL_GPL(ebu_lock); +- +-static struct resource ltq_ebu_resource = { +- .name = "ebu", +- .start = LTQ_EBU_BASE_ADDR, +- .end = LTQ_EBU_BASE_ADDR + LTQ_EBU_SIZE - 1, +- .flags = IORESOURCE_MEM, +-}; +- +-/* remapped base addr of the clock unit and external bus unit */ +-void __iomem *ltq_ebu_membase; +- +-static int __init lantiq_ebu_init(void) +-{ +- /* insert and request the memory region */ +- if (insert_resource(&iomem_resource, <q_ebu_resource) < 0) +- panic("Failed to insert ebu memory"); +- +- if (request_mem_region(ltq_ebu_resource.start, +- resource_size(<q_ebu_resource), "ebu") < 0) +- panic("Failed to request ebu memory"); +- +- /* remap ebu register range */ +- ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start, +- resource_size(<q_ebu_resource)); +- if (!ltq_ebu_membase) +- panic("Failed to remap ebu memory"); +- +- /* make sure to unprotect the memory region where flash is located */ +- ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); +- return 0; +-} +- +-postcore_initcall(lantiq_ebu_init); +diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c +index d2fa98f..375329b 100644 +--- a/arch/mips/lantiq/xway/gpio.c ++++ b/arch/mips/lantiq/xway/gpio.c +@@ -21,9 +21,19 @@ + #define LTQ_GPIO_ALTSEL0 0x0C + #define LTQ_GPIO_ALTSEL1 0x10 + #define LTQ_GPIO_OD 0x14 +- ++#define LTQ_GPIO_PUDSEL 0x1C ++#define LTQ_GPIO_PUDEN 0x20 ++#define LTQ_GPIO3_OD 0x24 ++#define LTQ_GPIO3_ALTSEL1 0x24 ++#define LTQ_GPIO3_PUDSEL 0x28 ++#define LTQ_GPIO3_PUDEN 0x2C ++ ++/* PORT3 only has 8 pins and its register layout ++ is slightly different */ + #define PINS_PER_PORT 16 +-#define MAX_PORTS 3 ++#define PINS_PORT3 8 ++#define MAX_PORTS 4 ++#define MAX_PIN 56 + + #define ltq_gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p))) + #define ltq_gpio_setbit(m, r, p) ltq_w32_mask(0, (1 << p), m + r) +@@ -48,14 +58,14 @@ int irq_to_gpio(unsigned int gpio) + } + EXPORT_SYMBOL(irq_to_gpio); + +-int ltq_gpio_request(unsigned int pin, unsigned int alt0, +- unsigned int alt1, unsigned int dir, const char *name) ++int ltq_gpio_request(struct device *dev, unsigned int pin, unsigned int mux, ++ unsigned int dir, const char *name) + { + int id = 0; + +- if (pin >= (MAX_PORTS * PINS_PER_PORT)) ++ if (pin >= MAX_PIN) + return -EINVAL; +- if (gpio_request(pin, name)) { ++ if (devm_gpio_request(dev, pin, name)) { + pr_err("failed to setup lantiq gpio: %s\n", name); + return -EBUSY; + } +@@ -67,18 +77,27 @@ int ltq_gpio_request(unsigned int pin, unsigned int alt0, + pin -= PINS_PER_PORT; + id++; + } +- if (alt0) ++ if (mux & 0x2) + ltq_gpio_setbit(ltq_gpio_port[id].membase, + LTQ_GPIO_ALTSEL0, pin); + else + ltq_gpio_clearbit(ltq_gpio_port[id].membase, + LTQ_GPIO_ALTSEL0, pin); +- if (alt1) +- ltq_gpio_setbit(ltq_gpio_port[id].membase, +- LTQ_GPIO_ALTSEL1, pin); +- else +- ltq_gpio_clearbit(ltq_gpio_port[id].membase, +- LTQ_GPIO_ALTSEL1, pin); ++ if (id == 3) { ++ if (mux & 0x1) ++ ltq_gpio_setbit(ltq_gpio_port[1].membase, ++ LTQ_GPIO3_ALTSEL1, pin); ++ else ++ ltq_gpio_clearbit(ltq_gpio_port[1].membase, ++ LTQ_GPIO3_ALTSEL1, pin); ++ } else { ++ if (mux & 0x1) ++ ltq_gpio_setbit(ltq_gpio_port[id].membase, ++ LTQ_GPIO_ALTSEL1, pin); ++ else ++ ltq_gpio_clearbit(ltq_gpio_port[id].membase, ++ LTQ_GPIO_ALTSEL1, pin); ++ } + return 0; + } + EXPORT_SYMBOL(ltq_gpio_request); +@@ -104,7 +123,18 @@ static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) + { + struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); + +- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); ++ if (chip->ngpio == PINS_PORT3) { ++ ltq_gpio_clearbit(ltq_gpio_port[0].membase, ++ LTQ_GPIO3_OD, offset); ++ ltq_gpio_setbit(ltq_gpio_port[0].membase, ++ LTQ_GPIO3_PUDSEL, offset); ++ ltq_gpio_setbit(ltq_gpio_port[0].membase, ++ LTQ_GPIO3_PUDEN, offset); ++ } else { ++ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); ++ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset); ++ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset); ++ } + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); + + return 0; +@@ -115,7 +145,18 @@ static int ltq_gpio_direction_output(struct gpio_chip *chip, + { + struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); + +- ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); ++ if (chip->ngpio == PINS_PORT3) { ++ ltq_gpio_setbit(ltq_gpio_port[0].membase, ++ LTQ_GPIO3_OD, offset); ++ ltq_gpio_clearbit(ltq_gpio_port[0].membase, ++ LTQ_GPIO3_PUDSEL, offset); ++ ltq_gpio_clearbit(ltq_gpio_port[0].membase, ++ LTQ_GPIO3_PUDEN, offset); ++ } else { ++ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); ++ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset); ++ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset); ++ } + ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); + ltq_gpio_set(chip, offset, value); + +@@ -127,7 +168,11 @@ static int ltq_gpio_req(struct gpio_chip *chip, unsigned offset) + struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); + + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL0, offset); +- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset); ++ if (chip->ngpio == PINS_PORT3) ++ ltq_gpio_clearbit(ltq_gpio_port[1].membase, ++ LTQ_GPIO3_ALTSEL1, offset); ++ else ++ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset); + return 0; + } + +@@ -140,6 +185,16 @@ static int ltq_gpio_probe(struct platform_device *pdev) + pdev->id); + return -EINVAL; + } ++ ++ /* dirty hack - The registers of port3 are not mapped linearly. ++ Port 3 may only load if Port 1/2 are mapped */ ++ if ((pdev->id == 3) && (!ltq_gpio_port[1].membase ++ || !ltq_gpio_port[2].membase)) { ++ dev_err(&pdev->dev, ++ "ports 1/2 need to be loaded before port 3 works\n"); ++ return -ENOMEM; ++ } ++ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get memory for gpio port %d\n", +@@ -169,7 +224,10 @@ static int ltq_gpio_probe(struct platform_device *pdev) + ltq_gpio_port[pdev->id].chip.set = ltq_gpio_set; + ltq_gpio_port[pdev->id].chip.request = ltq_gpio_req; + ltq_gpio_port[pdev->id].chip.base = PINS_PER_PORT * pdev->id; +- ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT; ++ if (pdev->id == 3) ++ ltq_gpio_port[pdev->id].chip.ngpio = PINS_PORT3; ++ else ++ ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT; + platform_set_drvdata(pdev, <q_gpio_port[pdev->id]); + return gpiochip_add(<q_gpio_port[pdev->id].chip); + } +diff --git a/arch/mips/lantiq/xway/gpio_ebu.c b/arch/mips/lantiq/xway/gpio_ebu.c +index b91c7f1..bc5696b 100644 +--- a/arch/mips/lantiq/xway/gpio_ebu.c ++++ b/arch/mips/lantiq/xway/gpio_ebu.c +@@ -61,9 +61,8 @@ static struct gpio_chip ltq_ebu_chip = { + .label = "ltq_ebu", + .direction_output = ltq_ebu_direction_output, + .set = ltq_ebu_set, +- .base = 72, ++ .base = 100, + .ngpio = 16, +- .can_sleep = 1, + .owner = THIS_MODULE, + }; + +diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c +index ff9991c..791beeb 100644 +--- a/arch/mips/lantiq/xway/gpio_stp.c ++++ b/arch/mips/lantiq/xway/gpio_stp.c +@@ -15,6 +15,8 @@ + #include + #include + #include ++#include ++#include + + #include + +@@ -25,6 +27,7 @@ + #define LTQ_STP_AR 0x10 + + #define LTQ_STP_CON_SWU (1 << 31) ++#define LTQ_STP_SWU_MASK (1 << 31) + #define LTQ_STP_2HZ 0 + #define LTQ_STP_4HZ (1 << 23) + #define LTQ_STP_8HZ (2 << 23) +@@ -35,6 +38,8 @@ + #define LTQ_STP_ADSL_SRC (3 << 24) + + #define LTQ_STP_GROUP0 (1 << 0) ++#define LTQ_STP_GROUP1 (1 << 1) ++#define LTQ_STP_GROUP2 (1 << 2) + + #define LTQ_STP_RISING 0 + #define LTQ_STP_FALLING (1 << 26) +@@ -56,6 +61,12 @@ static void ltq_stp_set(struct gpio_chip *chip, unsigned offset, int value) + else + ltq_stp_shadow &= ~(1 << offset); + ltq_stp_w32(ltq_stp_shadow, LTQ_STP_CPU0); ++ ltq_stp_w32_mask(LTQ_STP_SWU_MASK, LTQ_STP_CON_SWU, LTQ_STP_CON0); ++} ++ ++static int ltq_stp_get(struct gpio_chip *chip, unsigned offset) ++{ ++ return !!(ltq_stp_r32(LTQ_STP_CPU0) & (1<dev, "failed to remap STP memory\n"); + return -ENOMEM; + } ++ ++ /* the 3 pins used to control the external stp */ ++ pin = ltq_is_ase() ? 1 : 4; ++ if (ltq_gpio_request(&pdev->dev, pin, 2, 1, "stp-st") || ++ ltq_gpio_request(&pdev->dev, pin+1, 2, 1, "stp-d") || ++ ltq_gpio_request(&pdev->dev, pin+2, 2, 1, "stp-sh")) { ++ dev_err(&pdev->dev, "failed to request needed gpios\n"); ++ return -EBUSY; ++ } + ret = gpiochip_add(<q_stp_chip); + if (!ret) +- ret = ltq_stp_hw_init(); ++ ret = ltq_stp_hw_init(&pdev->dev); + + return ret; + } +diff --git a/arch/mips/lantiq/xway/mach-easy50601.c b/arch/mips/lantiq/xway/mach-easy50601.c +index d5aaf63..e76c29a 100644 +--- a/arch/mips/lantiq/xway/mach-easy50601.c ++++ b/arch/mips/lantiq/xway/mach-easy50601.c +@@ -32,12 +32,7 @@ static struct mtd_partition easy50601_partitions[] = { + { + .name = "linux", + .offset = 0x20000, +- .size = 0xE0000, +- }, +- { +- .name = "rootfs", +- .offset = 0x100000, +- .size = 0x300000, ++ .size = 0x3d0000, + }, + }; + +@@ -46,9 +41,15 @@ static struct physmap_flash_data easy50601_flash_data = { + .parts = easy50601_partitions, + }; + +-static void __init easy50601_init(void) ++static struct ltq_eth_data ltq_eth_data = { ++ .mii_mode = -1, /* use EPHY */ ++}; ++ ++static void __init ++easy50601_init(void) + { + ltq_register_nor(&easy50601_flash_data); ++ ltq_register_etop(<q_eth_data); + } + + MIPS_MACHINE(LTQ_MACH_EASY50601, +diff --git a/arch/mips/lantiq/xway/mach-easy50712.c b/arch/mips/lantiq/xway/mach-easy50712.c +index ea5027b..581aa76 100644 +--- a/arch/mips/lantiq/xway/mach-easy50712.c ++++ b/arch/mips/lantiq/xway/mach-easy50712.c +@@ -34,12 +34,7 @@ static struct mtd_partition easy50712_partitions[] = { + { + .name = "linux", + .offset = 0x20000, +- .size = 0xe0000, +- }, +- { +- .name = "rootfs", +- .offset = 0x100000, +- .size = 0x300000, ++ .size = 0x3d0000, + }, + }; + +@@ -60,15 +55,17 @@ static struct ltq_eth_data ltq_eth_data = { + .mii_mode = PHY_INTERFACE_MODE_MII, + }; + +-static void __init easy50712_init(void) ++static void __init ++easy50712_init(void) + { + ltq_register_gpio_stp(); + ltq_register_nor(&easy50712_flash_data); + ltq_register_pci(<q_pci_data); + ltq_register_etop(<q_eth_data); ++ ltq_register_tapi(); + } + + MIPS_MACHINE(LTQ_MACH_EASY50712, +- "EASY50712", +- "EASY50712 Eval Board", +- easy50712_init); ++ "EASY50712", ++ "EASY50712 Eval Board", ++ easy50712_init); +diff --git a/arch/mips/lantiq/xway/pmu.c b/arch/mips/lantiq/xway/pmu.c +deleted file mode 100644 +index fe85361..0000000 +--- a/arch/mips/lantiq/xway/pmu.c ++++ /dev/null +@@ -1,69 +0,0 @@ +-/* +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- * +- * Copyright (C) 2010 John Crispin +- */ +- +-#include +-#include +-#include +- +-#include +- +-/* PMU - the power management unit allows us to turn part of the core +- * on and off +- */ +- +-/* the enable / disable registers */ +-#define LTQ_PMU_PWDCR 0x1C +-#define LTQ_PMU_PWDSR 0x20 +- +-#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y)) +-#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x)) +- +-static struct resource ltq_pmu_resource = { +- .name = "pmu", +- .start = LTQ_PMU_BASE_ADDR, +- .end = LTQ_PMU_BASE_ADDR + LTQ_PMU_SIZE - 1, +- .flags = IORESOURCE_MEM, +-}; +- +-static void __iomem *ltq_pmu_membase; +- +-void ltq_pmu_enable(unsigned int module) +-{ +- int err = 1000000; +- +- ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR); +- do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module)); +- +- if (!err) +- panic("activating PMU module failed!"); +-} +-EXPORT_SYMBOL(ltq_pmu_enable); +- +-void ltq_pmu_disable(unsigned int module) +-{ +- ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR); +-} +-EXPORT_SYMBOL(ltq_pmu_disable); +- +-int __init ltq_pmu_init(void) +-{ +- if (insert_resource(&iomem_resource, <q_pmu_resource) < 0) +- panic("Failed to insert pmu memory"); +- +- if (request_mem_region(ltq_pmu_resource.start, +- resource_size(<q_pmu_resource), "pmu") < 0) +- panic("Failed to request pmu memory"); +- +- ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start, +- resource_size(<q_pmu_resource)); +- if (!ltq_pmu_membase) +- panic("Failed to remap pmu memory"); +- return 0; +-} +- +-core_initcall(ltq_pmu_init); +diff --git a/arch/mips/lantiq/xway/prom-ase.c b/arch/mips/lantiq/xway/prom-ase.c +deleted file mode 100644 +index ae4959a..0000000 +--- a/arch/mips/lantiq/xway/prom-ase.c ++++ /dev/null +@@ -1,39 +0,0 @@ +-/* +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- * +- * Copyright (C) 2010 John Crispin +- */ +- +-#include +-#include +-#include +-#include +- +-#include +- +-#include "../prom.h" +- +-#define SOC_AMAZON_SE "Amazon_SE" +- +-#define PART_SHIFT 12 +-#define PART_MASK 0x0FFFFFFF +-#define REV_SHIFT 28 +-#define REV_MASK 0xF0000000 +- +-void __init ltq_soc_detect(struct ltq_soc_info *i) +-{ +- i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; +- i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; +- switch (i->partnum) { +- case SOC_ID_AMAZON_SE: +- i->name = SOC_AMAZON_SE; +- i->type = SOC_TYPE_AMAZON_SE; +- break; +- +- default: +- unreachable(); +- break; +- } +-} +diff --git a/arch/mips/lantiq/xway/prom-xway.c b/arch/mips/lantiq/xway/prom-xway.c +deleted file mode 100644 +index 2228133..0000000 +--- a/arch/mips/lantiq/xway/prom-xway.c ++++ /dev/null +@@ -1,54 +0,0 @@ +-/* +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- * +- * Copyright (C) 2010 John Crispin +- */ +- +-#include +-#include +-#include +-#include +- +-#include +- +-#include "../prom.h" +- +-#define SOC_DANUBE "Danube" +-#define SOC_TWINPASS "Twinpass" +-#define SOC_AR9 "AR9" +- +-#define PART_SHIFT 12 +-#define PART_MASK 0x0FFFFFFF +-#define REV_SHIFT 28 +-#define REV_MASK 0xF0000000 +- +-void __init ltq_soc_detect(struct ltq_soc_info *i) +-{ +- i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; +- i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; +- switch (i->partnum) { +- case SOC_ID_DANUBE1: +- case SOC_ID_DANUBE2: +- i->name = SOC_DANUBE; +- i->type = SOC_TYPE_DANUBE; +- break; +- +- case SOC_ID_TWINPASS: +- i->name = SOC_TWINPASS; +- i->type = SOC_TYPE_DANUBE; +- break; +- +- case SOC_ID_ARX188: +- case SOC_ID_ARX168: +- case SOC_ID_ARX182: +- i->name = SOC_AR9; +- i->type = SOC_TYPE_AR9; +- break; +- +- default: +- unreachable(); +- break; +- } +-} +diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c +index 8b66bd8..970ca17 100644 +--- a/arch/mips/lantiq/xway/reset.c ++++ b/arch/mips/lantiq/xway/reset.c +@@ -11,26 +11,62 @@ + #include + #include + #include ++#include + #include + + #include + ++#include "../devices.h" ++ + #define ltq_rcu_w32(x, y) ltq_w32((x), ltq_rcu_membase + (y)) + #define ltq_rcu_r32(x) ltq_r32(ltq_rcu_membase + (x)) + +-/* register definitions */ +-#define LTQ_RCU_RST 0x0010 +-#define LTQ_RCU_RST_ALL 0x40000000 +- +-#define LTQ_RCU_RST_STAT 0x0014 +-#define LTQ_RCU_STAT_SHIFT 26 +- +-static struct resource ltq_rcu_resource = { +- .name = "rcu", +- .start = LTQ_RCU_BASE_ADDR, +- .end = LTQ_RCU_BASE_ADDR + LTQ_RCU_SIZE - 1, +- .flags = IORESOURCE_MEM, +-}; ++/* reset request register */ ++#define RCU_RST_REQ 0x0010 ++/* reset status register */ ++#define RCU_RST_STAT 0x0014 ++ ++/* reset cause */ ++#define RCU_STAT_SHIFT 26 ++/* boot selection */ ++#define RCU_BOOT_SEL_SHIFT 26 ++#define RCU_BOOT_SEL_MASK 0x7 ++ ++/* Global SW Reset */ ++#define RCU_RD_SRST BIT(30) ++/* Memory Controller */ ++#define RCU_RD_MC BIT(14) ++/* PCI core */ ++#define RCU_RD_PCI BIT(13) ++/* Voice DFE/AFE */ ++#define RCU_RD_DFE_AFE BIT(12) ++/* DSL AFE */ ++#define RCU_RD_DSL_AFE BIT(11) ++/* SDIO core */ ++#define RCU_RD_SDIO BIT(10) ++/* DMA core */ ++#define RCU_RD_DMA BIT(9) ++/* PPE core */ ++#define RCU_RD_PPE BIT(8) ++/* ARC/DFE core */ ++#define RCU_RD_ARC_DFE BIT(7) ++/* AHB bus */ ++#define RCU_RD_AHB BIT(6) ++/* Ethernet MAC1 */ ++#define RCU_RD_ENET_MAC1 BIT(5) ++/* USB and Phy core */ ++#define RCU_RD_USB BIT(4) ++/* CPU1 subsystem */ ++#define RCU_RD_CPU1 BIT(3) ++/* FPI bus */ ++#define RCU_RD_FPI BIT(2) ++/* CPU0 subsystem */ ++#define RCU_RD_CPU0 BIT(1) ++/* HW reset via HRST pin */ ++#define RCU_RD_HRST BIT(0) ++ ++static struct resource ltq_rcu_resource = ++ MEM_RES("rcu", LTQ_RCU_BASE_ADDR, LTQ_RCU_SIZE); + + /* remapped base addr of the reset control unit */ + static void __iomem *ltq_rcu_membase; +@@ -38,16 +74,29 @@ static void __iomem *ltq_rcu_membase; + /* This function is used by the watchdog driver */ + int ltq_reset_cause(void) + { +- u32 val = ltq_rcu_r32(LTQ_RCU_RST_STAT); +- return val >> LTQ_RCU_STAT_SHIFT; ++ u32 val = ltq_rcu_r32(RCU_RST_STAT); ++ return val >> RCU_STAT_SHIFT; + } + EXPORT_SYMBOL_GPL(ltq_reset_cause); + ++unsigned char ltq_boot_select(void) ++{ ++ u32 val = ltq_rcu_r32(RCU_RST_STAT); ++ return (val >> RCU_BOOT_SEL_SHIFT) & RCU_BOOT_SEL_MASK; ++} ++ ++void ltq_reset_once(unsigned int module, ulong usec) ++{ ++ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ); ++ udelay(usec); ++ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ); ++} ++ + static void ltq_machine_restart(char *command) + { + pr_notice("System restart\n"); + local_irq_disable(); +- ltq_rcu_w32(ltq_rcu_r32(LTQ_RCU_RST) | LTQ_RCU_RST_ALL, LTQ_RCU_RST); ++ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | RCU_RD_SRST, RCU_RST_REQ); + unreachable(); + } + +@@ -67,17 +116,8 @@ static void ltq_machine_power_off(void) + + static int __init mips_reboot_setup(void) + { +- /* insert and request the memory region */ +- if (insert_resource(&iomem_resource, <q_rcu_resource) < 0) +- panic("Failed to insert rcu memory"); +- +- if (request_mem_region(ltq_rcu_resource.start, +- resource_size(<q_rcu_resource), "rcu") < 0) +- panic("Failed to request rcu memory"); +- + /* remap rcu register range */ +- ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start, +- resource_size(<q_rcu_resource)); ++ ltq_rcu_membase = ltq_remap_resource(<q_rcu_resource); + if (!ltq_rcu_membase) + panic("Failed to remap rcu memory"); + +diff --git a/arch/mips/lantiq/xway/setup-ase.c b/arch/mips/lantiq/xway/setup-ase.c +deleted file mode 100644 +index f6f3267..0000000 +--- a/arch/mips/lantiq/xway/setup-ase.c ++++ /dev/null +@@ -1,19 +0,0 @@ +-/* +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- * +- * Copyright (C) 2011 John Crispin +- */ +- +-#include +- +-#include "../prom.h" +-#include "devices.h" +- +-void __init ltq_soc_setup(void) +-{ +- ltq_register_ase_asc(); +- ltq_register_gpio(); +- ltq_register_wdt(); +-} +diff --git a/arch/mips/lantiq/xway/setup-xway.c b/arch/mips/lantiq/xway/setup-xway.c +deleted file mode 100644 +index c292f64..0000000 +--- a/arch/mips/lantiq/xway/setup-xway.c ++++ /dev/null +@@ -1,20 +0,0 @@ +-/* +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- * +- * Copyright (C) 2011 John Crispin +- */ +- +-#include +- +-#include "../prom.h" +-#include "devices.h" +- +-void __init ltq_soc_setup(void) +-{ +- ltq_register_asc(0); +- ltq_register_asc(1); +- ltq_register_gpio(); +- ltq_register_wdt(); +-} +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0003-MIPS-lantiq-change-ltq_request_gpio-call-signature.patch b/target/linux/lantiq/patches-3.3/0003-MIPS-lantiq-change-ltq_request_gpio-call-signature.patch deleted file mode 100644 index f807c5848d..0000000000 --- a/target/linux/lantiq/patches-3.3/0003-MIPS-lantiq-change-ltq_request_gpio-call-signature.patch +++ /dev/null @@ -1,138 +0,0 @@ -From 834353ea867a84649d452bac03b97ce32dc6e318 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 11 Nov 2011 12:45:24 +0100 -Subject: [PATCH 03/70] MIPS: lantiq: change ltq_request_gpio() call signature - -ltq_request_gpio() was using alt0/1 to multiplex the function of GPIO pins. -This was XWAY specific. In order to also accomodate SoCs that require more bits -we use a 32bit mask instead. This way the call signature is consistent between -XWAY and FALC-ON. - -Signed-off-by: John Crispin -Signed-off-by: Thomas Langer ---- - .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 4 +- - arch/mips/lantiq/xway/gpio.c | 8 ++-- - arch/mips/lantiq/xway/gpio_stp.c | 6 ++-- - arch/mips/pci/pci-lantiq.c | 36 +++++++++---------- - 4 files changed, 26 insertions(+), 28 deletions(-) - ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -@@ -135,8 +135,8 @@ extern __iomem void *ltq_ebu_membase; - extern __iomem void *ltq_cgu_membase; - - /* request a non-gpio and set the PIO config */ --extern int ltq_gpio_request(unsigned int pin, unsigned int alt0, -- unsigned int alt1, unsigned int dir, const char *name); -+extern int ltq_gpio_request(unsigned int pin, unsigned int mux, -+ unsigned int dir, const char *name); - extern void ltq_pmu_enable(unsigned int module); - extern void ltq_pmu_disable(unsigned int module); - extern void ltq_cgu_enable(unsigned int clk); ---- a/arch/mips/lantiq/xway/gpio.c -+++ b/arch/mips/lantiq/xway/gpio.c -@@ -48,8 +48,8 @@ int irq_to_gpio(unsigned int gpio) - } - EXPORT_SYMBOL(irq_to_gpio); - --int ltq_gpio_request(unsigned int pin, unsigned int alt0, -- unsigned int alt1, unsigned int dir, const char *name) -+int ltq_gpio_request(unsigned int pin, unsigned int mux, -+ unsigned int dir, const char *name) - { - int id = 0; - -@@ -67,13 +67,13 @@ int ltq_gpio_request(unsigned int pin, u - pin -= PINS_PER_PORT; - id++; - } -- if (alt0) -+ if (mux & 0x2) - ltq_gpio_setbit(ltq_gpio_port[id].membase, - LTQ_GPIO_ALTSEL0, pin); - else - ltq_gpio_clearbit(ltq_gpio_port[id].membase, - LTQ_GPIO_ALTSEL0, pin); -- if (alt1) -+ if (mux & 0x1) - ltq_gpio_setbit(ltq_gpio_port[id].membase, - LTQ_GPIO_ALTSEL1, pin); - else ---- a/arch/mips/lantiq/xway/gpio_stp.c -+++ b/arch/mips/lantiq/xway/gpio_stp.c -@@ -79,9 +79,9 @@ static struct gpio_chip ltq_stp_chip = { - static int ltq_stp_hw_init(void) - { - /* the 3 pins used to control the external stp */ -- ltq_gpio_request(4, 1, 0, 1, "stp-st"); -- ltq_gpio_request(5, 1, 0, 1, "stp-d"); -- ltq_gpio_request(6, 1, 0, 1, "stp-sh"); -+ ltq_gpio_request(4, 2, 1, "stp-st"); -+ ltq_gpio_request(5, 2, 1, "stp-d"); -+ ltq_gpio_request(6, 2, 1, "stp-sh"); - - /* sane defaults */ - ltq_stp_w32(0, LTQ_STP_AR); ---- a/arch/mips/pci/pci-lantiq.c -+++ b/arch/mips/pci/pci-lantiq.c -@@ -70,28 +70,27 @@ - - struct ltq_pci_gpio_map { - int pin; -- int alt0; -- int alt1; -+ int mux; - int dir; - char *name; - }; - - /* the pci core can make use of the following gpios */ - static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = { -- { 0, 1, 0, 0, "pci-exin0" }, -- { 1, 1, 0, 0, "pci-exin1" }, -- { 2, 1, 0, 0, "pci-exin2" }, -- { 39, 1, 0, 0, "pci-exin3" }, -- { 10, 1, 0, 0, "pci-exin4" }, -- { 9, 1, 0, 0, "pci-exin5" }, -- { 30, 1, 0, 1, "pci-gnt1" }, -- { 23, 1, 0, 1, "pci-gnt2" }, -- { 19, 1, 0, 1, "pci-gnt3" }, -- { 38, 1, 0, 1, "pci-gnt4" }, -- { 29, 1, 0, 0, "pci-req1" }, -- { 31, 1, 0, 0, "pci-req2" }, -- { 3, 1, 0, 0, "pci-req3" }, -- { 37, 1, 0, 0, "pci-req4" }, -+ { 0, 2, 0, "pci-exin0" }, -+ { 1, 2, 0, "pci-exin1" }, -+ { 2, 2, 0, "pci-exin2" }, -+ { 39, 2, 0, "pci-exin3" }, -+ { 10, 2, 0, "pci-exin4" }, -+ { 9, 2, 0, "pci-exin5" }, -+ { 30, 2, 1, "pci-gnt1" }, -+ { 23, 2, 1, "pci-gnt2" }, -+ { 19, 2, 1, "pci-gnt3" }, -+ { 38, 2, 1, "pci-gnt4" }, -+ { 29, 2, 0, "pci-req1" }, -+ { 31, 2, 0, "pci-req2" }, -+ { 3, 2, 0, "pci-req3" }, -+ { 37, 2, 0, "pci-req4" }, - }; - - __iomem void *ltq_pci_mapped_cfg; -@@ -157,13 +156,12 @@ static void ltq_pci_setup_gpio(int gpio) - for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) { - if (gpio & (1 << i)) { - ltq_gpio_request(ltq_pci_gpio_map[i].pin, -- ltq_pci_gpio_map[i].alt0, -- ltq_pci_gpio_map[i].alt1, -+ ltq_pci_gpio_map[i].mux, - ltq_pci_gpio_map[i].dir, - ltq_pci_gpio_map[i].name); - } - } -- ltq_gpio_request(21, 0, 0, 1, "pci-reset"); -+ ltq_gpio_request(21, 0, 1, "pci-reset"); - ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK; - } - diff --git a/target/linux/lantiq/patches-3.3/0003-svip-hack.patch b/target/linux/lantiq/patches-3.3/0003-svip-hack.patch new file mode 100644 index 0000000000..7ac92e132e --- /dev/null +++ b/target/linux/lantiq/patches-3.3/0003-svip-hack.patch @@ -0,0 +1,42 @@ +From 03de60e7fd96c0d78d293dc859a2a9ad2d2f16c4 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 10:22:41 +0200 +Subject: [PATCH 03/25] svip hack + +--- + arch/mips/kernel/cevt-r4k.c | 2 ++ + arch/mips/mm/c-r4k.c | 3 +++ + 2 files changed, 5 insertions(+), 0 deletions(-) + +diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c +index 51095dd..db9070c 100644 +--- a/arch/mips/kernel/cevt-r4k.c ++++ b/arch/mips/kernel/cevt-r4k.c +@@ -171,8 +171,10 @@ int __cpuinit r4k_clockevent_init(void) + if (!cpu_has_counter || !mips_hpt_frequency) + return -ENXIO; + ++#ifndef CONFIG_SOC_SVIP + if (!c0_compare_int_usable()) + return -ENXIO; ++#endif + + /* + * With vectored interrupts things are getting platform specific. +diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c +index 4f9eb0b..de3475e 100644 +--- a/arch/mips/mm/c-r4k.c ++++ b/arch/mips/mm/c-r4k.c +@@ -1252,6 +1252,9 @@ static void __cpuinit setup_scache(void) + way_string[c->scache.ways], c->scache.linesz); + } + #else ++#ifdef CONFIG_SOC_SVIP ++ return; ++#endif + if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) + panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); + #endif +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0004-MIPS-lantiq-make-irq.c-support-the-FALC-ON.patch b/target/linux/lantiq/patches-3.3/0004-MIPS-lantiq-make-irq.c-support-the-FALC-ON.patch deleted file mode 100644 index 1ca446ef03..0000000000 --- a/target/linux/lantiq/patches-3.3/0004-MIPS-lantiq-make-irq.c-support-the-FALC-ON.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 9eabaa2969af9aa157d50b7cfbb447f65db95f06 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 11 Aug 2011 12:25:55 +0200 -Subject: [PATCH 04/70] MIPS: lantiq: make irq.c support the FALC-ON - -There are minor differences in how irqs work on xway and falcon socs. -Xway needs 2 quirks that we need to disable for falcon to also work with -this code. - -* EBU irq does not need to send a special ack to the EBU -* The EIU does not exist - -Signed-off-by: Thomas Langer -Signed-off-by: John Crispin ---- - arch/mips/lantiq/irq.c | 24 +++++++++++++----------- - 1 files changed, 13 insertions(+), 11 deletions(-) - ---- a/arch/mips/lantiq/irq.c -+++ b/arch/mips/lantiq/irq.c -@@ -195,7 +195,7 @@ static void ltq_hw_irqdispatch(int modul - do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module)); - - /* if this is a EBU irq, we need to ack it or get a deadlock */ -- if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0)) -+ if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT) - ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10, - LTQ_EBU_PCC_ISTAT); - } -@@ -259,17 +259,19 @@ void __init arch_init_irq(void) - if (!ltq_icu_membase) - panic("Failed to remap icu memory"); - -- if (insert_resource(&iomem_resource, <q_eiu_resource) < 0) -- panic("Failed to insert eiu memory"); -+ if (LTQ_EIU_BASE_ADDR) { -+ if (insert_resource(&iomem_resource, <q_eiu_resource) < 0) -+ panic("Failed to insert eiu memory\n"); -+ -+ if (request_mem_region(ltq_eiu_resource.start, -+ resource_size(<q_eiu_resource), "eiu") < 0) -+ panic("Failed to request eiu memory\n"); - -- if (request_mem_region(ltq_eiu_resource.start, -- resource_size(<q_eiu_resource), "eiu") < 0) -- panic("Failed to request eiu memory"); -- -- ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start, -+ ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start, - resource_size(<q_eiu_resource)); -- if (!ltq_eiu_membase) -- panic("Failed to remap eiu memory"); -+ if (!ltq_eiu_membase) -+ panic("Failed to remap eiu memory\n"); -+ } - - /* make sure all irqs are turned off by default */ - for (i = 0; i < 5; i++) -@@ -295,8 +297,8 @@ void __init arch_init_irq(void) - - for (i = INT_NUM_IRQ0; - i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++) -- if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) || -- (i == LTQ_EIU_IR2)) -+ if (((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) || -+ (i == LTQ_EIU_IR2)) && LTQ_EIU_BASE_ADDR) - irq_set_chip_and_handler(i, <q_eiu_type, - handle_level_irq); - /* EIU3-5 only exist on ar9 and vr9 */ diff --git a/target/linux/lantiq/patches-3.3/0004-lantiq-core-support.patch b/target/linux/lantiq/patches-3.3/0004-lantiq-core-support.patch new file mode 100644 index 0000000000..d048988ebb --- /dev/null +++ b/target/linux/lantiq/patches-3.3/0004-lantiq-core-support.patch @@ -0,0 +1,1009 @@ +From 94a0ad7aea40f0143670cfb6d5794f2f4b6b1aa7 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 09:51:32 +0200 +Subject: [PATCH 04/25] lantiq core support + +--- + arch/mips/Kconfig | 6 +- + arch/mips/lantiq/Kconfig | 10 ++ + arch/mips/lantiq/Makefile | 2 + + arch/mips/lantiq/Platform | 2 + + arch/mips/lantiq/clk.c | 136 +++++++++++---------- + arch/mips/lantiq/clk.h | 59 ++++++++- + arch/mips/lantiq/devices.c | 30 +---- + arch/mips/lantiq/devices.h | 4 + + arch/mips/lantiq/early_printk.c | 14 ++- + arch/mips/lantiq/irq.c | 262 +++++++++++++++++++++++++++++++-------- + arch/mips/lantiq/machtypes.h | 5 + + arch/mips/lantiq/prom.c | 63 ++++++++-- + arch/mips/lantiq/prom.h | 4 + + 13 files changed, 435 insertions(+), 162 deletions(-) + +diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig +index cffcae6..0e2ce5d 100644 +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -228,8 +228,11 @@ config LANTIQ + select ARCH_REQUIRE_GPIOLIB + select SWAP_IO_SPACE + select BOOT_RAW +- select HAVE_CLK ++ select HAVE_MACH_CLKDEV ++ select CLKDEV_LOOKUP ++ select HAVE_OPROFILE + select MIPS_MACHINE ++ select USB_ARCH_HAS_HCD + + config LASAT + bool "LASAT Networks platforms" +@@ -2391,6 +2394,7 @@ config PCI_DOMAINS + bool + + source "drivers/pci/Kconfig" ++source "drivers/pci/pcie/Kconfig" + + # + # ISA support is now enabled via select. Too many systems still have the one +diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig +index 3fccf21..b7ba0fe 100644 +--- a/arch/mips/lantiq/Kconfig ++++ b/arch/mips/lantiq/Kconfig +@@ -16,8 +16,18 @@ config SOC_XWAY + bool "XWAY" + select SOC_TYPE_XWAY + select HW_HAS_PCI ++ ++config SOC_FALCON ++ bool "FALCON" ++ ++config SOC_SVIP ++ bool "SVIP" ++ select MIPS_CPU_SCACHE ++ + endchoice + + source "arch/mips/lantiq/xway/Kconfig" ++source "arch/mips/lantiq/falcon/Kconfig" ++source "arch/mips/lantiq/svip/Kconfig" + + endif +diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile +index e5dae0e..db1ce50 100644 +--- a/arch/mips/lantiq/Makefile ++++ b/arch/mips/lantiq/Makefile +@@ -9,3 +9,5 @@ obj-y := irq.o setup.o clk.o prom.o devices.o + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + + obj-$(CONFIG_SOC_TYPE_XWAY) += xway/ ++obj-$(CONFIG_SOC_FALCON) += falcon/ ++obj-$(CONFIG_SOC_SVIP) += svip/ +diff --git a/arch/mips/lantiq/Platform b/arch/mips/lantiq/Platform +index f3dff05..857548c 100644 +--- a/arch/mips/lantiq/Platform ++++ b/arch/mips/lantiq/Platform +@@ -6,3 +6,5 @@ platform-$(CONFIG_LANTIQ) += lantiq/ + cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq + load-$(CONFIG_LANTIQ) = 0xffffffff80002000 + cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway ++cflags-$(CONFIG_SOC_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon ++cflags-$(CONFIG_SOC_SVIP) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/svip +diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c +index 412814f..6c95f5e 100644 +--- a/arch/mips/lantiq/clk.c ++++ b/arch/mips/lantiq/clk.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -22,44 +23,32 @@ + #include + + #include "clk.h" ++#include "prom.h" + +-struct clk { +- const char *name; +- unsigned long rate; +- unsigned long (*get_rate) (void); +-}; ++/* lantiq socs have 3 static clocks */ ++static struct clk cpu_clk_generic[3]; + +-static struct clk *cpu_clk; +-static int cpu_clk_cnt; ++void clkdev_add_static(unsigned long cpu, unsigned long fpi, unsigned long io) ++{ ++ cpu_clk_generic[0].rate = cpu; ++ cpu_clk_generic[1].rate = fpi; ++ cpu_clk_generic[2].rate = io; ++} + +-/* lantiq socs have 3 static clocks */ +-static struct clk cpu_clk_generic[] = { +- { +- .name = "cpu", +- .get_rate = ltq_get_cpu_hz, +- }, { +- .name = "fpi", +- .get_rate = ltq_get_fpi_hz, +- }, { +- .name = "io", +- .get_rate = ltq_get_io_region_clock, +- }, +-}; +- +-static struct resource ltq_cgu_resource = { +- .name = "cgu", +- .start = LTQ_CGU_BASE_ADDR, +- .end = LTQ_CGU_BASE_ADDR + LTQ_CGU_SIZE - 1, +- .flags = IORESOURCE_MEM, +-}; +- +-/* remapped clock register range */ +-void __iomem *ltq_cgu_membase; +- +-void clk_init(void) ++struct clk *clk_get_cpu(void) + { +- cpu_clk = cpu_clk_generic; +- cpu_clk_cnt = ARRAY_SIZE(cpu_clk_generic); ++ return &cpu_clk_generic[0]; ++} ++ ++struct clk *clk_get_fpi(void) ++{ ++ return &cpu_clk_generic[1]; ++} ++EXPORT_SYMBOL_GPL(clk_get_fpi); ++ ++struct clk *clk_get_io(void) ++{ ++ return &cpu_clk_generic[2]; + } + + static inline int clk_good(struct clk *clk) +@@ -82,37 +71,60 @@ unsigned long clk_get_rate(struct clk *clk) + } + EXPORT_SYMBOL(clk_get_rate); + +-struct clk *clk_get(struct device *dev, const char *id) ++int clk_set_rate(struct clk *clk, unsigned long rate) + { +- int i; +- +- for (i = 0; i < cpu_clk_cnt; i++) +- if (!strcmp(id, cpu_clk[i].name)) +- return &cpu_clk[i]; +- BUG(); +- return ERR_PTR(-ENOENT); +-} +-EXPORT_SYMBOL(clk_get); ++ if (unlikely(!clk_good(clk))) ++ return 0; + +-void clk_put(struct clk *clk) +-{ +- /* not used */ ++ clk->rate = rate; ++ return 0; + } +-EXPORT_SYMBOL(clk_put); ++EXPORT_SYMBOL(clk_set_rate); + + int clk_enable(struct clk *clk) + { +- /* not used */ +- return 0; ++ if (unlikely(!clk_good(clk))) ++ return -1; ++ ++ if (clk->enable) ++ return clk->enable(clk); ++ ++ return -1; + } + EXPORT_SYMBOL(clk_enable); + + void clk_disable(struct clk *clk) + { +- /* not used */ ++ if (unlikely(!clk_good(clk))) ++ return; ++ ++ if (clk->disable) ++ clk->disable(clk); + } + EXPORT_SYMBOL(clk_disable); + ++int clk_activate(struct clk *clk) ++{ ++ if (unlikely(!clk_good(clk))) ++ return -1; ++ ++ if (clk->activate) ++ return clk->activate(clk); ++ ++ return -1; ++} ++EXPORT_SYMBOL(clk_activate); ++ ++void clk_deactivate(struct clk *clk) ++{ ++ if (unlikely(!clk_good(clk))) ++ return; ++ ++ if (clk->deactivate) ++ clk->deactivate(clk); ++} ++EXPORT_SYMBOL(clk_deactivate); ++ + static inline u32 ltq_get_counter_resolution(void) + { + u32 res; +@@ -133,21 +145,17 @@ void __init plat_time_init(void) + { + struct clk *clk; + +- if (insert_resource(&iomem_resource, <q_cgu_resource) < 0) +- panic("Failed to insert cgu memory"); +- +- if (request_mem_region(ltq_cgu_resource.start, +- resource_size(<q_cgu_resource), "cgu") < 0) +- panic("Failed to request cgu memory"); ++ ltq_soc_init(); + +- ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start, +- resource_size(<q_cgu_resource)); +- if (!ltq_cgu_membase) { +- pr_err("Failed to remap cgu memory\n"); +- unreachable(); +- } +- clk = clk_get(0, "cpu"); ++ clk = clk_get_cpu(); + mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution(); ++#ifdef CONFIG_SOC_SVIP ++ write_c0_count(0); ++ write_c0_compare(mips_hpt_frequency / HZ); ++ enable_irq(MIPS_CPU_TIMER_IRQ); ++#else + write_c0_compare(read_c0_count()); ++#endif ++ pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); + clk_put(clk); + } +diff --git a/arch/mips/lantiq/clk.h b/arch/mips/lantiq/clk.h +index 3328925..564ef03 100644 +--- a/arch/mips/lantiq/clk.h ++++ b/arch/mips/lantiq/clk.h +@@ -9,10 +9,61 @@ + #ifndef _LTQ_CLK_H__ + #define _LTQ_CLK_H__ + +-extern void clk_init(void); ++#include + +-extern unsigned long ltq_get_cpu_hz(void); +-extern unsigned long ltq_get_fpi_hz(void); +-extern unsigned long ltq_get_io_region_clock(void); ++/* clock speeds */ ++#define CLOCK_33M 33333333 ++#define CLOCK_60M 60000000 ++#define CLOCK_62_5M 62500000 ++#define CLOCK_83M 83333333 ++#define CLOCK_83_5M 83500000 ++#define CLOCK_98_304M 98304000 ++#define CLOCK_100M 100000000 ++#define CLOCK_111M 111111111 ++#define CLOCK_125M 125000000 ++#define CLOCK_133M 133333333 ++#define CLOCK_150M 150000000 ++#define CLOCK_166M 166666666 ++#define CLOCK_167M 166666667 ++#define CLOCK_196_608M 196608000 ++#define CLOCK_200M 200000000 ++#define CLOCK_250M 250000000 ++#define CLOCK_266M 266666666 ++#define CLOCK_300M 300000000 ++#define CLOCK_333M 333333333 ++#define CLOCK_393M 393215332 ++#define CLOCK_400M 400000000 ++#define CLOCK_500M 500000000 ++#define CLOCK_600M 600000000 ++ ++struct clk { ++ struct clk_lookup cl; ++ unsigned long rate; ++ unsigned int module; ++ unsigned int bits; ++ unsigned long (*get_rate) (void); ++ int (*enable) (struct clk *clk); ++ void (*disable) (struct clk *clk); ++ int (*activate) (struct clk *clk); ++ void (*deactivate) (struct clk *clk); ++ void (*reboot) (struct clk *clk); ++}; ++ ++extern void clkdev_add_static(unsigned long cpu, unsigned long fpi, ++ unsigned long io); ++ ++extern unsigned long ltq_danube_cpu_hz(void); ++extern unsigned long ltq_danube_fpi_hz(void); ++extern unsigned long ltq_danube_io_region_clock(void); ++ ++extern unsigned long ltq_svip_cpu_hz(void); ++extern unsigned long ltq_svip_fpi_hz(void); ++extern unsigned long ltq_svip_io_region_clock(void); ++ ++extern unsigned long ltq_ar9_cpu_hz(void); ++extern unsigned long ltq_ar9_fpi_hz(void); ++ ++extern unsigned long ltq_vr9_cpu_hz(void); ++extern unsigned long ltq_vr9_fpi_hz(void); + + #endif +diff --git a/arch/mips/lantiq/devices.c b/arch/mips/lantiq/devices.c +index de1cb2b..7193d78 100644 +--- a/arch/mips/lantiq/devices.c ++++ b/arch/mips/lantiq/devices.c +@@ -27,12 +27,8 @@ + #include "devices.h" + + /* nor flash */ +-static struct resource ltq_nor_resource = { +- .name = "nor", +- .start = LTQ_FLASH_START, +- .end = LTQ_FLASH_START + LTQ_FLASH_MAX - 1, +- .flags = IORESOURCE_MEM, +-}; ++static struct resource ltq_nor_resource = ++ MEM_RES("nor", LTQ_FLASH_START, LTQ_FLASH_MAX); + + static struct platform_device ltq_nor = { + .name = "ltq_nor", +@@ -47,12 +43,8 @@ void __init ltq_register_nor(struct physmap_flash_data *data) + } + + /* watchdog */ +-static struct resource ltq_wdt_resource = { +- .name = "watchdog", +- .start = LTQ_WDT_BASE_ADDR, +- .end = LTQ_WDT_BASE_ADDR + LTQ_WDT_SIZE - 1, +- .flags = IORESOURCE_MEM, +-}; ++static struct resource ltq_wdt_resource = ++ MEM_RES("watchdog", LTQ_WDT_BASE_ADDR, LTQ_WDT_SIZE); + + void __init ltq_register_wdt(void) + { +@@ -61,24 +53,14 @@ void __init ltq_register_wdt(void) + + /* asc ports */ + static struct resource ltq_asc0_resources[] = { +- { +- .name = "asc0", +- .start = LTQ_ASC0_BASE_ADDR, +- .end = LTQ_ASC0_BASE_ADDR + LTQ_ASC_SIZE - 1, +- .flags = IORESOURCE_MEM, +- }, ++ MEM_RES("asc0", LTQ_ASC0_BASE_ADDR, LTQ_ASC_SIZE), + IRQ_RES(tx, LTQ_ASC_TIR(0)), + IRQ_RES(rx, LTQ_ASC_RIR(0)), + IRQ_RES(err, LTQ_ASC_EIR(0)), + }; + + static struct resource ltq_asc1_resources[] = { +- { +- .name = "asc1", +- .start = LTQ_ASC1_BASE_ADDR, +- .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1, +- .flags = IORESOURCE_MEM, +- }, ++ MEM_RES("asc1", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE), + IRQ_RES(tx, LTQ_ASC_TIR(1)), + IRQ_RES(rx, LTQ_ASC_RIR(1)), + IRQ_RES(err, LTQ_ASC_EIR(1)), +diff --git a/arch/mips/lantiq/devices.h b/arch/mips/lantiq/devices.h +index 2947bb1..a03c23f 100644 +--- a/arch/mips/lantiq/devices.h ++++ b/arch/mips/lantiq/devices.h +@@ -14,6 +14,10 @@ + + #define IRQ_RES(resname, irq) \ + {.name = #resname, .start = (irq), .flags = IORESOURCE_IRQ} ++#define MEM_RES(resname, adr_start, adr_size) \ ++ { .name = resname, .flags = IORESOURCE_MEM, \ ++ .start = ((adr_start) & ~KSEG1), \ ++ .end = ((adr_start + adr_size - 1) & ~KSEG1) } + + extern void ltq_register_nor(struct physmap_flash_data *data); + extern void ltq_register_wdt(void); +diff --git a/arch/mips/lantiq/early_printk.c b/arch/mips/lantiq/early_printk.c +index 972e05f..5089075 100644 +--- a/arch/mips/lantiq/early_printk.c ++++ b/arch/mips/lantiq/early_printk.c +@@ -12,11 +12,13 @@ + #include + #include + +-/* no ioremap possible at this early stage, lets use KSEG1 instead */ +-#define LTQ_ASC_BASE KSEG1ADDR(LTQ_ASC1_BASE_ADDR) + #define ASC_BUF 1024 +-#define LTQ_ASC_FSTAT ((u32 *)(LTQ_ASC_BASE + 0x0048)) +-#define LTQ_ASC_TBUF ((u32 *)(LTQ_ASC_BASE + 0x0020)) ++#define LTQ_ASC_FSTAT ((u32 *)(LTQ_EARLY_ASC + 0x0048)) ++#ifdef __BIG_ENDIAN ++#define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020 + 3)) ++#else ++#define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020)) ++#endif + #define TXMASK 0x3F00 + #define TXOFFSET 8 + +@@ -27,7 +29,7 @@ void prom_putchar(char c) + local_irq_save(flags); + do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET); + if (c == '\n') +- ltq_w32('\r', LTQ_ASC_TBUF); +- ltq_w32(c, LTQ_ASC_TBUF); ++ ltq_w8('\r', LTQ_ASC_TBUF); ++ ltq_w8(c, LTQ_ASC_TBUF); + local_irq_restore(flags); + } +diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c +index d673731..63dbb83 100644 +--- a/arch/mips/lantiq/irq.c ++++ b/arch/mips/lantiq/irq.c +@@ -9,12 +9,17 @@ + + #include + #include ++#include + + #include + #include + + #include + #include ++#ifdef CONFIG_SOC_SVIP ++#include ++#include ++#endif + + /* register definitions */ + #define LTQ_ICU_IM0_ISR 0x0000 +@@ -40,17 +45,28 @@ + + #define MAX_EIU 6 + ++/* the performance counter */ ++#define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31) ++ + /* irqs generated by device attached to the EBU need to be acked in + * a special manner + */ + #define LTQ_ICU_EBU_IRQ 22 + +-#define ltq_icu_w32(x, y) ltq_w32((x), ltq_icu_membase + (y)) +-#define ltq_icu_r32(x) ltq_r32(ltq_icu_membase + (x)) ++#define ltq_icu_w32(x, y, m) ltq_w32((x), ltq_icu_membase[m] + (y)) ++#define ltq_icu_r32(x, m) ltq_r32(ltq_icu_membase[m] + (x)) + + #define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y)) + #define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x)) + ++/* our 2 ipi interrupts for VSMP */ ++#define MIPS_CPU_IPI_RESCHED_IRQ 0 ++#define MIPS_CPU_IPI_CALL_IRQ 1 ++ ++#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) ++int gic_present; ++#endif ++ + static unsigned short ltq_eiu_irq[MAX_EIU] = { + LTQ_EIU_IR0, + LTQ_EIU_IR1, +@@ -60,11 +76,78 @@ static unsigned short ltq_eiu_irq[MAX_EIU] = { + LTQ_EIU_IR5, + }; + +-static struct resource ltq_icu_resource = { +- .name = "icu", +- .start = LTQ_ICU_BASE_ADDR, +- .end = LTQ_ICU_BASE_ADDR + LTQ_ICU_SIZE - 1, +- .flags = IORESOURCE_MEM, ++static struct resource ltq_icu_resource[IM_NUM] = { ++{ ++ .name = "icu_im0", ++ .start = LTQ_ICU_BASE_ADDR, ++ .end = LTQ_ICU_BASE_ADDR + LTQ_ICU_OFFSET - 1, ++ .flags = IORESOURCE_MEM, ++}, ++#if IM_NUM >= 2 ++{ ++ .name = "icu_im1", ++#ifdef LTQ_ICU_BASE_ADDR1 ++ .start = LTQ_ICU_BASE_ADDR1, ++ .end = LTQ_ICU_BASE_ADDR1 + LTQ_ICU_OFFSET - 1, ++#else ++ .start = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 1), ++ .end = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 2) - 1, ++#endif ++ .flags = IORESOURCE_MEM, ++}, ++#endif ++#if IM_NUM >= 3 ++{ ++ .name = "icu_im2", ++#ifdef LTQ_ICU_BASE_ADDR2 ++ .start = LTQ_ICU_BASE_ADDR2, ++ .end = LTQ_ICU_BASE_ADDR2 + LTQ_ICU_OFFSET - 1, ++#else ++ .start = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 2), ++ .end = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 3) - 1, ++#endif ++ .flags = IORESOURCE_MEM, ++}, ++#endif ++#if IM_NUM >= 4 ++{ ++ .name = "icu_im3", ++#ifdef LTQ_ICU_BASE_ADDR3 ++ .start = LTQ_ICU_BASE_ADDR3, ++ .end = LTQ_ICU_BASE_ADDR3 + LTQ_ICU_OFFSET - 1, ++#else ++ .start = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 3), ++ .end = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 4) - 1, ++#endif ++ .flags = IORESOURCE_MEM, ++}, ++#endif ++#if IM_NUM >= 5 ++{ ++ .name = "icu_im4", ++#ifdef LTQ_ICU_BASE_ADDR4 ++ .start = LTQ_ICU_BASE_ADDR4, ++ .end = LTQ_ICU_BASE_ADDR4 + LTQ_ICU_OFFSET - 1, ++#else ++ .start = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 4), ++ .end = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 5) - 1, ++#endif ++ .flags = IORESOURCE_MEM, ++}, ++#endif ++#if IM_NUM >= 6 ++{ ++ .name = "icu_im5", ++#ifdef LTQ_ICU_BASE_ADDR5 ++ .start = LTQ_ICU_BASE_ADDR5, ++ .end = LTQ_ICU_BASE_ADDR5 + LTQ_ICU_OFFSET - 1, ++#else ++ .start = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 5), ++ .end = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 6) - 1, ++#endif ++ .flags = IORESOURCE_MEM, ++}, ++#endif + }; + + static struct resource ltq_eiu_resource = { +@@ -74,50 +157,53 @@ static struct resource ltq_eiu_resource = { + .flags = IORESOURCE_MEM, + }; + +-static void __iomem *ltq_icu_membase; ++static void __iomem *ltq_icu_membase[IM_NUM]; + static void __iomem *ltq_eiu_membase; + + void ltq_disable_irq(struct irq_data *d) + { +- u32 ier = LTQ_ICU_IM0_IER; + int irq_nr = d->irq - INT_NUM_IRQ0; ++ unsigned int im_nr; + +- ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); ++ im_nr = (irq_nr / INT_NUM_IM_OFFSET); + irq_nr %= INT_NUM_IM_OFFSET; +- ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier); ++ ++ ltq_icu_w32(ltq_icu_r32(LTQ_ICU_IM0_IER, im_nr) & ~(1 << irq_nr), ++ LTQ_ICU_IM0_IER, im_nr); + } + + void ltq_mask_and_ack_irq(struct irq_data *d) + { +- u32 ier = LTQ_ICU_IM0_IER; +- u32 isr = LTQ_ICU_IM0_ISR; + int irq_nr = d->irq - INT_NUM_IRQ0; ++ unsigned int im_nr; + +- ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); +- isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); ++ im_nr = (irq_nr / INT_NUM_IM_OFFSET); + irq_nr %= INT_NUM_IM_OFFSET; +- ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier); +- ltq_icu_w32((1 << irq_nr), isr); ++ ++ ltq_icu_w32(ltq_icu_r32(LTQ_ICU_IM0_IER, im_nr) & ~(1 << irq_nr), LTQ_ICU_IM0_IER, im_nr); ++ ltq_icu_w32((1 << irq_nr), LTQ_ICU_IM0_ISR, im_nr); + } + + static void ltq_ack_irq(struct irq_data *d) + { +- u32 isr = LTQ_ICU_IM0_ISR; + int irq_nr = d->irq - INT_NUM_IRQ0; ++ unsigned int im_nr; + +- isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); ++ im_nr = (irq_nr / INT_NUM_IM_OFFSET); + irq_nr %= INT_NUM_IM_OFFSET; +- ltq_icu_w32((1 << irq_nr), isr); ++ ++ ltq_icu_w32((1 << irq_nr), LTQ_ICU_IM0_ISR, im_nr); + } + + void ltq_enable_irq(struct irq_data *d) + { +- u32 ier = LTQ_ICU_IM0_IER; + int irq_nr = d->irq - INT_NUM_IRQ0; ++ unsigned int im_nr; + +- ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); ++ im_nr = (irq_nr / INT_NUM_IM_OFFSET); + irq_nr %= INT_NUM_IM_OFFSET; +- ltq_icu_w32(ltq_icu_r32(ier) | (1 << irq_nr), ier); ++ ++ ltq_icu_w32(ltq_icu_r32(LTQ_ICU_IM0_IER, im_nr) | (1 << irq_nr), LTQ_ICU_IM0_IER, im_nr); + } + + static unsigned int ltq_startup_eiu_irq(struct irq_data *d) +@@ -184,7 +270,7 @@ static void ltq_hw_irqdispatch(int module) + { + u32 irq; + +- irq = ltq_icu_r32(LTQ_ICU_IM0_IOSR + (module * LTQ_ICU_OFFSET)); ++ irq = ltq_icu_r32(LTQ_ICU_IM0_IOSR, module); + if (irq == 0) + return; + +@@ -194,10 +280,12 @@ static void ltq_hw_irqdispatch(int module) + irq = __fls(irq); + do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module)); + ++#ifndef CONFIG_SOC_SVIP + /* if this is a EBU irq, we need to ack it or get a deadlock */ +- if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0)) ++ if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT) + ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10, + LTQ_EBU_PCC_ISTAT); ++#endif + } + + #define DEFINE_HWx_IRQDISPATCH(x) \ +@@ -211,21 +299,66 @@ DEFINE_HWx_IRQDISPATCH(2) + DEFINE_HWx_IRQDISPATCH(3) + DEFINE_HWx_IRQDISPATCH(4) + ++#if MIPS_CPU_TIMER_IRQ == 7 + static void ltq_hw5_irqdispatch(void) + { + do_IRQ(MIPS_CPU_TIMER_IRQ); + } ++#else ++DEFINE_HWx_IRQDISPATCH(5) ++#endif ++ ++#ifdef CONFIG_MIPS_MT_SMP ++void __init arch_init_ipiirq(int irq, struct irqaction *action) ++{ ++ setup_irq(irq, action); ++ irq_set_handler(irq, handle_percpu_irq); ++} ++ ++static void ltq_sw0_irqdispatch(void) ++{ ++ do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ); ++} ++ ++static void ltq_sw1_irqdispatch(void) ++{ ++ do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); ++} ++static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) ++{ ++ scheduler_ipi(); ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) ++{ ++ smp_call_function_interrupt(); ++ return IRQ_HANDLED; ++} ++ ++static struct irqaction irq_resched = { ++ .handler = ipi_resched_interrupt, ++ .flags = IRQF_PERCPU, ++ .name = "IPI_resched" ++}; ++ ++static struct irqaction irq_call = { ++ .handler = ipi_call_interrupt, ++ .flags = IRQF_PERCPU, ++ .name = "IPI_call" ++}; ++#endif + + asmlinkage void plat_irq_dispatch(void) + { + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; + unsigned int i; + +- if (pending & CAUSEF_IP7) { ++ if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) { + do_IRQ(MIPS_CPU_TIMER_IRQ); + goto out; + } else { +- for (i = 0; i < 5; i++) { ++ for (i = 0; i < IM_NUM; i++) { + if (pending & (CAUSEF_IP2 << i)) { + ltq_hw_irqdispatch(i); + goto out; +@@ -247,41 +380,45 @@ void __init arch_init_irq(void) + { + int i; + +- if (insert_resource(&iomem_resource, <q_icu_resource) < 0) +- panic("Failed to insert icu memory"); ++ for (i=0; i < IM_NUM; i++) { ++ if (insert_resource(&iomem_resource, <q_icu_resource[i]) < 0) ++ panic("Failed to insert icu memory\n"); + +- if (request_mem_region(ltq_icu_resource.start, +- resource_size(<q_icu_resource), "icu") < 0) +- panic("Failed to request icu memory"); ++ if (request_mem_region(ltq_icu_resource[i].start, ++ resource_size(<q_icu_resource[i]), "icu") < 0) ++ panic("Failed to request icu memory\n"); + +- ltq_icu_membase = ioremap_nocache(ltq_icu_resource.start, +- resource_size(<q_icu_resource)); +- if (!ltq_icu_membase) +- panic("Failed to remap icu memory"); ++ ltq_icu_membase[i] = ioremap_nocache(ltq_icu_resource[i].start, ++ resource_size(<q_icu_resource[i])); ++ if (!ltq_icu_membase[i]) ++ panic("Failed to remap icu memory\n"); ++ } + +- if (insert_resource(&iomem_resource, <q_eiu_resource) < 0) +- panic("Failed to insert eiu memory"); ++ if (LTQ_EIU_BASE_ADDR) { ++ if (insert_resource(&iomem_resource, <q_eiu_resource) < 0) ++ panic("Failed to insert eiu memory\n"); + +- if (request_mem_region(ltq_eiu_resource.start, +- resource_size(<q_eiu_resource), "eiu") < 0) +- panic("Failed to request eiu memory"); ++ if (request_mem_region(ltq_eiu_resource.start, ++ resource_size(<q_eiu_resource), "eiu") < 0) ++ panic("Failed to request eiu memory\n"); + +- ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start, ++ ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start, + resource_size(<q_eiu_resource)); +- if (!ltq_eiu_membase) +- panic("Failed to remap eiu memory"); ++ if (!ltq_eiu_membase) ++ panic("Failed to remap eiu memory\n"); ++ } + + /* make sure all irqs are turned off by default */ +- for (i = 0; i < 5; i++) +- ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET)); +- +- /* clear all possibly pending interrupts */ +- ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET)); ++ for (i = 0; i < IM_NUM; i++) { ++ ltq_icu_w32(0, LTQ_ICU_IM0_IER, i); ++ /* clear all possibly pending interrupts */ ++ ltq_icu_w32(~0, LTQ_ICU_IM0_ISR, i); ++ } + + mips_cpu_irq_init(); + +- for (i = 2; i <= 6; i++) +- setup_irq(i, &cascade); ++ for (i = 0; i < IM_NUM; i++) ++ setup_irq(i + 2, &cascade); + + if (cpu_has_vint) { + pr_info("Setting up vectored interrupts\n"); +@@ -294,9 +431,9 @@ void __init arch_init_irq(void) + } + + for (i = INT_NUM_IRQ0; +- i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++) +- if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) || +- (i == LTQ_EIU_IR2)) ++ i <= (INT_NUM_IRQ0 + (IM_NUM * INT_NUM_IM_OFFSET)); i++) ++ if (((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) || ++ (i == LTQ_EIU_IR2)) && LTQ_EIU_BASE_ADDR) + irq_set_chip_and_handler(i, <q_eiu_type, + handle_level_irq); + /* EIU3-5 only exist on ar9 and vr9 */ +@@ -308,6 +445,17 @@ void __init arch_init_irq(void) + irq_set_chip_and_handler(i, <q_irq_type, + handle_level_irq); + ++#if defined(CONFIG_MIPS_MT_SMP) ++ if (cpu_has_vint) { ++ pr_info("Setting up IPI vectored interrupts\n"); ++ set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch); ++ set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch); ++ } ++ arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ, ++ &irq_resched); ++ arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call); ++#endif ++ + #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC) + set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | + IE_IRQ3 | IE_IRQ4 | IE_IRQ5); +@@ -315,9 +463,15 @@ void __init arch_init_irq(void) + set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 | + IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5); + #endif ++ ++ cp0_perfcount_irq = LTQ_PERF_IRQ; + } + + unsigned int __cpuinit get_c0_compare_int(void) + { ++#ifdef CONFIG_SOC_SVIP ++ return MIPS_CPU_TIMER_IRQ; ++#else + return CP0_LEGACY_COMPARE_IRQ; ++#endif + } +diff --git a/arch/mips/lantiq/machtypes.h b/arch/mips/lantiq/machtypes.h +index 7e01b8c..dfc6af7 100644 +--- a/arch/mips/lantiq/machtypes.h ++++ b/arch/mips/lantiq/machtypes.h +@@ -15,6 +15,11 @@ enum lantiq_mach_type { + LTQ_MACH_GENERIC = 0, + LTQ_MACH_EASY50712, /* Danube evaluation board */ + LTQ_MACH_EASY50601, /* Amazon SE evaluation board */ ++ ++ /* FALCON */ ++ LANTIQ_MACH_EASY98000, /* Falcon Eval Board, NOR Flash */ ++ LANTIQ_MACH_EASY98000SF, /* Falcon Eval Board, Serial Flash */ ++ LANTIQ_MACH_EASY98000NAND, /* Falcon Eval Board, NAND Flash */ + }; + + #endif +diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c +index e34fcfd..00ad59c 100644 +--- a/arch/mips/lantiq/prom.c ++++ b/arch/mips/lantiq/prom.c +@@ -16,6 +16,10 @@ + #include "prom.h" + #include "clk.h" + ++/* access to the ebu needs to be locked between different drivers */ ++DEFINE_SPINLOCK(ebu_lock); ++EXPORT_SYMBOL_GPL(ebu_lock); ++ + static struct ltq_soc_info soc_info; + + unsigned int ltq_get_cpu_ver(void) +@@ -45,27 +49,68 @@ static void __init prom_init_cmdline(void) + char **argv = (char **) KSEG1ADDR(fw_arg1); + int i; + ++ arcs_cmdline[0] = '\0'; ++ + for (i = 0; i < argc; i++) { +- char *p = (char *) KSEG1ADDR(argv[i]); ++ char *p = (char *) KSEG1ADDR(argv[i]); + +- if (p && *p) { ++ if (CPHYSADDR(p) && *p) { + strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); + strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); + } + } + } + +-void __init prom_init(void) ++void __iomem *ltq_remap_resource(struct resource *res) + { +- struct clk *clk; ++ __iomem void *ret = NULL; ++ struct resource *lookup = lookup_resource(&iomem_resource, res->start); ++ ++ if (lookup && strcmp(lookup->name, res->name)) { ++ pr_err("conflicting memory range %s\n", res->name); ++ return NULL; ++ } ++ if (!lookup) { ++ if (insert_resource(&iomem_resource, res) < 0) { ++ pr_err("Failed to insert %s memory\n", res->name); ++ return NULL; ++ } ++ } ++ if (request_mem_region(res->start, ++ resource_size(res), res->name) < 0) { ++ pr_err("Failed to request %s memory\n", res->name); ++ goto err_res; ++ } + ++ ret = ioremap_nocache(res->start, resource_size(res)); ++ if (!ret) ++ goto err_mem; ++ ++ pr_debug("remap: 0x%08X-0x%08X : \"%s\"\n", ++ res->start, res->end, res->name); ++ return ret; ++ ++err_mem: ++ panic("Failed to remap %s memory\n", res->name); ++ release_mem_region(res->start, resource_size(res)); ++ ++err_res: ++ release_resource(res); ++ return NULL; ++} ++EXPORT_SYMBOL(ltq_remap_resource); ++ ++void __init prom_init(void) ++{ + ltq_soc_detect(&soc_info); +- clk_init(); +- clk = clk_get(0, "cpu"); +- snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev1.%d", +- soc_info.name, soc_info.rev); +- clk_put(clk); ++ snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s", ++ soc_info.name, soc_info.rev_type); + soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; + pr_info("SoC: %s\n", soc_info.sys_type); + prom_init_cmdline(); ++ ++#if defined(CONFIG_MIPS_MT_SMP) ++ if (register_vsmp_smp_ops()) ++ panic("failed to register_vsmp_smp_ops()"); ++#endif + } +diff --git a/arch/mips/lantiq/prom.h b/arch/mips/lantiq/prom.h +index b4229d9..51dba1b 100644 +--- a/arch/mips/lantiq/prom.h ++++ b/arch/mips/lantiq/prom.h +@@ -9,17 +9,21 @@ + #ifndef _LTQ_PROM_H__ + #define _LTQ_PROM_H__ + ++#define LTQ_SYS_REV_LEN 0x10 + #define LTQ_SYS_TYPE_LEN 0x100 + + struct ltq_soc_info { + unsigned char *name; + unsigned int rev; ++ unsigned char rev_type[LTQ_SYS_REV_LEN]; ++ unsigned int srev; + unsigned int partnum; + unsigned int type; + unsigned char sys_type[LTQ_SYS_TYPE_LEN]; + }; + + extern void ltq_soc_detect(struct ltq_soc_info *i); ++extern void ltq_soc_init(void); + extern void ltq_soc_setup(void); + + #endif +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0005-MIPS-lantiq-add-basic-support-for-FALC-ON.patch b/target/linux/lantiq/patches-3.3/0005-MIPS-lantiq-add-basic-support-for-FALC-ON.patch deleted file mode 100644 index 602953bffb..0000000000 --- a/target/linux/lantiq/patches-3.3/0005-MIPS-lantiq-add-basic-support-for-FALC-ON.patch +++ /dev/null @@ -1,1047 +0,0 @@ -From 53e05f3689ec846c2a89d16d3f74bac6c7de81ee Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 11 Aug 2011 14:33:04 +0200 -Subject: [PATCH 05/70] MIPS: lantiq: add basic support for FALC-ON - -Adds support for the FALC-ON SoC. This SoC is from the FTTH/GPON SoC family. - -Signed-off-by: Thomas Langer -Signed-off-by: John Crispin ---- - .../include/asm/mach-lantiq/falcon/falcon_irq.h | 268 ++++++++++++++++++++ - arch/mips/include/asm/mach-lantiq/falcon/irq.h | 18 ++ - .../include/asm/mach-lantiq/falcon/lantiq_soc.h | 143 +++++++++++ - arch/mips/include/asm/mach-lantiq/lantiq.h | 1 + - arch/mips/lantiq/Kconfig | 4 + - arch/mips/lantiq/Makefile | 1 + - arch/mips/lantiq/Platform | 1 + - arch/mips/lantiq/falcon/Makefile | 1 + - arch/mips/lantiq/falcon/clk.c | 44 ++++ - arch/mips/lantiq/falcon/devices.c | 87 +++++++ - arch/mips/lantiq/falcon/devices.h | 18 ++ - arch/mips/lantiq/falcon/prom.c | 93 +++++++ - arch/mips/lantiq/falcon/reset.c | 87 +++++++ - arch/mips/lantiq/falcon/sysctrl.c | 183 +++++++++++++ - 14 files changed, 949 insertions(+), 0 deletions(-) - create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h - create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/irq.h - create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h - create mode 100644 arch/mips/lantiq/falcon/Makefile - create mode 100644 arch/mips/lantiq/falcon/clk.c - create mode 100644 arch/mips/lantiq/falcon/devices.c - create mode 100644 arch/mips/lantiq/falcon/devices.h - create mode 100644 arch/mips/lantiq/falcon/prom.c - create mode 100644 arch/mips/lantiq/falcon/reset.c - create mode 100644 arch/mips/lantiq/falcon/sysctrl.c - ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h -@@ -0,0 +1,268 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2010 Thomas Langer -+ */ -+ -+#ifndef _FALCON_IRQ__ -+#define _FALCON_IRQ__ -+ -+#define INT_NUM_IRQ0 8 -+#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) -+#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32) -+#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32) -+#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32) -+#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32) -+#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32) -+#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0) -+ -+#define MIPS_CPU_TIMER_IRQ 7 -+ -+/* HOST IF Event Interrupt */ -+#define FALCON_IRQ_HOST (INT_NUM_IM0_IRL0 + 0) -+/* HOST IF Mailbox0 Receive Interrupt */ -+#define FALCON_IRQ_HOST_MB0_RX (INT_NUM_IM0_IRL0 + 1) -+/* HOST IF Mailbox0 Transmit Interrupt */ -+#define FALCON_IRQ_HOST_MB0_TX (INT_NUM_IM0_IRL0 + 2) -+/* HOST IF Mailbox1 Receive Interrupt */ -+#define FALCON_IRQ_HOST_MB1_RX (INT_NUM_IM0_IRL0 + 3) -+/* HOST IF Mailbox1 Transmit Interrupt */ -+#define FALCON_IRQ_HOST_MB1_TX (INT_NUM_IM0_IRL0 + 4) -+/* I2C Last Single Data Transfer Request */ -+#define FALCON_IRQ_I2C_LSREQ (INT_NUM_IM0_IRL0 + 8) -+/* I2C Single Data Transfer Request */ -+#define FALCON_IRQ_I2C_SREQ (INT_NUM_IM0_IRL0 + 9) -+/* I2C Last Burst Data Transfer Request */ -+#define FALCON_IRQ_I2C_LBREQ (INT_NUM_IM0_IRL0 + 10) -+/* I2C Burst Data Transfer Request */ -+#define FALCON_IRQ_I2C_BREQ (INT_NUM_IM0_IRL0 + 11) -+/* I2C Error Interrupt */ -+#define FALCON_IRQ_I2C_I2C_ERR (INT_NUM_IM0_IRL0 + 12) -+/* I2C Protocol Interrupt */ -+#define FALCON_IRQ_I2C_I2C_P (INT_NUM_IM0_IRL0 + 13) -+/* SSC Transmit Interrupt */ -+#define FALCON_IRQ_SSC_T (INT_NUM_IM0_IRL0 + 14) -+/* SSC Receive Interrupt */ -+#define FALCON_IRQ_SSC_R (INT_NUM_IM0_IRL0 + 15) -+/* SSC Error Interrupt */ -+#define FALCON_IRQ_SSC_E (INT_NUM_IM0_IRL0 + 16) -+/* SSC Frame Interrupt */ -+#define FALCON_IRQ_SSC_F (INT_NUM_IM0_IRL0 + 17) -+/* Advanced Encryption Standard Interrupt */ -+#define FALCON_IRQ_AES_AES (INT_NUM_IM0_IRL0 + 27) -+/* Secure Hash Algorithm Interrupt */ -+#define FALCON_IRQ_SHA_HASH (INT_NUM_IM0_IRL0 + 28) -+/* PCM Receive Interrupt */ -+#define FALCON_IRQ_PCM_RX (INT_NUM_IM0_IRL0 + 29) -+/* PCM Transmit Interrupt */ -+#define FALCON_IRQ_PCM_TX (INT_NUM_IM0_IRL0 + 30) -+/* PCM Transmit Crash Interrupt */ -+#define FALCON_IRQ_PCM_HW2_CRASH (INT_NUM_IM0_IRL0 + 31) -+ -+/* EBU Serial Flash Command Error */ -+#define FALCON_IRQ_EBU_SF_CMDERR (INT_NUM_IM1_IRL0 + 0) -+/* EBU Serial Flash Command Overwrite Error */ -+#define FALCON_IRQ_EBU_SF_COVERR (INT_NUM_IM1_IRL0 + 1) -+/* EBU Serial Flash Busy */ -+#define FALCON_IRQ_EBU_SF_BUSY (INT_NUM_IM1_IRL0 + 2) -+/* External Interrupt from GPIO P0 */ -+#define FALCON_IRQ_GPIO_P0 (INT_NUM_IM1_IRL0 + 4) -+/* External Interrupt from GPIO P1 */ -+#define FALCON_IRQ_GPIO_P1 (INT_NUM_IM1_IRL0 + 5) -+/* External Interrupt from GPIO P2 */ -+#define FALCON_IRQ_GPIO_P2 (INT_NUM_IM1_IRL0 + 6) -+/* External Interrupt from GPIO P3 */ -+#define FALCON_IRQ_GPIO_P3 (INT_NUM_IM1_IRL0 + 7) -+/* External Interrupt from GPIO P4 */ -+#define FALCON_IRQ_GPIO_P4 (INT_NUM_IM1_IRL0 + 8) -+/* 8kHz backup interrupt derived from core-PLL */ -+#define FALCON_IRQ_FSC_BKP (INT_NUM_IM1_IRL0 + 10) -+/* FSC Timer Interrupt 0 */ -+#define FALCON_IRQ_FSCT_CMP0 (INT_NUM_IM1_IRL0 + 11) -+/* FSC Timer Interrupt 1 */ -+#define FALCON_IRQ_FSCT_CMP1 (INT_NUM_IM1_IRL0 + 12) -+/* 8kHz root interrupt derived from GPON interface */ -+#define FALCON_IRQ_FSC_ROOT (INT_NUM_IM1_IRL0 + 13) -+/* Time of Day */ -+#define FALCON_IRQ_TOD (INT_NUM_IM1_IRL0 + 14) -+/* PMA Interrupt from IntNode of the 200MHz Domain */ -+#define FALCON_IRQ_PMA_200M (INT_NUM_IM1_IRL0 + 15) -+/* PMA Interrupt from IntNode of the TX Clk Domain */ -+#define FALCON_IRQ_PMA_TX (INT_NUM_IM1_IRL0 + 16) -+/* PMA Interrupt from IntNode of the RX Clk Domain */ -+#define FALCON_IRQ_PMA_RX (INT_NUM_IM1_IRL0 + 17) -+/* SYS1 Interrupt */ -+#define FALCON_IRQ_SYS1 (INT_NUM_IM1_IRL0 + 20) -+/* SYS GPE Interrupt */ -+#define FALCON_IRQ_SYS_GPE (INT_NUM_IM1_IRL0 + 21) -+/* Watchdog Access Error Interrupt */ -+#define FALCON_IRQ_WDT_AEIR (INT_NUM_IM1_IRL0 + 24) -+/* Watchdog Prewarning Interrupt */ -+#define FALCON_IRQ_WDT_PIR (INT_NUM_IM1_IRL0 + 25) -+/* SBIU interrupt */ -+#define FALCON_IRQ_SBIU0 (INT_NUM_IM1_IRL0 + 27) -+/* FPI Bus Control Unit Interrupt */ -+#define FALCON_IRQ_BCU0 (INT_NUM_IM1_IRL0 + 29) -+/* DDR Controller Interrupt */ -+#define FALCON_IRQ_DDR (INT_NUM_IM1_IRL0 + 30) -+/* Crossbar Error Interrupt */ -+#define FALCON_IRQ_XBAR_ERROR (INT_NUM_IM1_IRL0 + 31) -+ -+/* ICTRLL 0 Interrupt */ -+#define FALCON_IRQ_ICTRLL0 (INT_NUM_IM2_IRL0 + 0) -+/* ICTRLL 1 Interrupt */ -+#define FALCON_IRQ_ICTRLL1 (INT_NUM_IM2_IRL0 + 1) -+/* ICTRLL 2 Interrupt */ -+#define FALCON_IRQ_ICTRLL2 (INT_NUM_IM2_IRL0 + 2) -+/* ICTRLL 3 Interrupt */ -+#define FALCON_IRQ_ICTRLL3 (INT_NUM_IM2_IRL0 + 3) -+/* OCTRLL 0 Interrupt */ -+#define FALCON_IRQ_OCTRLL0 (INT_NUM_IM2_IRL0 + 4) -+/* OCTRLL 1 Interrupt */ -+#define FALCON_IRQ_OCTRLL1 (INT_NUM_IM2_IRL0 + 5) -+/* OCTRLL 2 Interrupt */ -+#define FALCON_IRQ_OCTRLL2 (INT_NUM_IM2_IRL0 + 6) -+/* OCTRLL 3 Interrupt */ -+#define FALCON_IRQ_OCTRLL3 (INT_NUM_IM2_IRL0 + 7) -+/* OCTRLG Interrupt */ -+#define FALCON_IRQ_OCTRLG (INT_NUM_IM2_IRL0 + 9) -+/* IQM Interrupt */ -+#define FALCON_IRQ_IQM (INT_NUM_IM2_IRL0 + 10) -+/* FSQM Interrupt */ -+#define FALCON_IRQ_FSQM (INT_NUM_IM2_IRL0 + 11) -+/* TMU Interrupt */ -+#define FALCON_IRQ_TMU (INT_NUM_IM2_IRL0 + 12) -+/* LINK1 Interrupt */ -+#define FALCON_IRQ_LINK1 (INT_NUM_IM2_IRL0 + 14) -+/* ICTRLC 0 Interrupt */ -+#define FALCON_IRQ_ICTRLC0 (INT_NUM_IM2_IRL0 + 16) -+/* ICTRLC 1 Interrupt */ -+#define FALCON_IRQ_ICTRLC1 (INT_NUM_IM2_IRL0 + 17) -+/* OCTRLC Interrupt */ -+#define FALCON_IRQ_OCTRLC (INT_NUM_IM2_IRL0 + 18) -+/* CONFIG Break Interrupt */ -+#define FALCON_IRQ_CONFIG_BREAK (INT_NUM_IM2_IRL0 + 19) -+/* CONFIG Interrupt */ -+#define FALCON_IRQ_CONFIG (INT_NUM_IM2_IRL0 + 20) -+/* Dispatcher Interrupt */ -+#define FALCON_IRQ_DISP (INT_NUM_IM2_IRL0 + 21) -+/* TBM Interrupt */ -+#define FALCON_IRQ_TBM (INT_NUM_IM2_IRL0 + 22) -+/* GTC Downstream Interrupt */ -+#define FALCON_IRQ_GTC_DS (INT_NUM_IM2_IRL0 + 29) -+/* GTC Upstream Interrupt */ -+#define FALCON_IRQ_GTC_US (INT_NUM_IM2_IRL0 + 30) -+/* EIM Interrupt */ -+#define FALCON_IRQ_EIM (INT_NUM_IM2_IRL0 + 31) -+ -+/* ASC0 Transmit Interrupt */ -+#define FALCON_IRQ_ASC0_T (INT_NUM_IM3_IRL0 + 0) -+/* ASC0 Receive Interrupt */ -+#define FALCON_IRQ_ASC0_R (INT_NUM_IM3_IRL0 + 1) -+/* ASC0 Error Interrupt */ -+#define FALCON_IRQ_ASC0_E (INT_NUM_IM3_IRL0 + 2) -+/* ASC0 Transmit Buffer Interrupt */ -+#define FALCON_IRQ_ASC0_TB (INT_NUM_IM3_IRL0 + 3) -+/* ASC0 Autobaud Start Interrupt */ -+#define FALCON_IRQ_ASC0_ABST (INT_NUM_IM3_IRL0 + 4) -+/* ASC0 Autobaud Detection Interrupt */ -+#define FALCON_IRQ_ASC0_ABDET (INT_NUM_IM3_IRL0 + 5) -+/* ASC1 Modem Status Interrupt */ -+#define FALCON_IRQ_ASC0_MS (INT_NUM_IM3_IRL0 + 6) -+/* ASC0 Soft Flow Control Interrupt */ -+#define FALCON_IRQ_ASC0_SFC (INT_NUM_IM3_IRL0 + 7) -+/* ASC1 Transmit Interrupt */ -+#define FALCON_IRQ_ASC1_T (INT_NUM_IM3_IRL0 + 8) -+/* ASC1 Receive Interrupt */ -+#define FALCON_IRQ_ASC1_R (INT_NUM_IM3_IRL0 + 9) -+/* ASC1 Error Interrupt */ -+#define FALCON_IRQ_ASC1_E (INT_NUM_IM3_IRL0 + 10) -+/* ASC1 Transmit Buffer Interrupt */ -+#define FALCON_IRQ_ASC1_TB (INT_NUM_IM3_IRL0 + 11) -+/* ASC1 Autobaud Start Interrupt */ -+#define FALCON_IRQ_ASC1_ABST (INT_NUM_IM3_IRL0 + 12) -+/* ASC1 Autobaud Detection Interrupt */ -+#define FALCON_IRQ_ASC1_ABDET (INT_NUM_IM3_IRL0 + 13) -+/* ASC1 Modem Status Interrupt */ -+#define FALCON_IRQ_ASC1_MS (INT_NUM_IM3_IRL0 + 14) -+/* ASC1 Soft Flow Control Interrupt */ -+#define FALCON_IRQ_ASC1_SFC (INT_NUM_IM3_IRL0 + 15) -+/* GPTC Timer/Counter 1A Interrupt */ -+#define FALCON_IRQ_GPTC_TC1A (INT_NUM_IM3_IRL0 + 16) -+/* GPTC Timer/Counter 1B Interrupt */ -+#define FALCON_IRQ_GPTC_TC1B (INT_NUM_IM3_IRL0 + 17) -+/* GPTC Timer/Counter 2A Interrupt */ -+#define FALCON_IRQ_GPTC_TC2A (INT_NUM_IM3_IRL0 + 18) -+/* GPTC Timer/Counter 2B Interrupt */ -+#define FALCON_IRQ_GPTC_TC2B (INT_NUM_IM3_IRL0 + 19) -+/* GPTC Timer/Counter 3A Interrupt */ -+#define FALCON_IRQ_GPTC_TC3A (INT_NUM_IM3_IRL0 + 20) -+/* GPTC Timer/Counter 3B Interrupt */ -+#define FALCON_IRQ_GPTC_TC3B (INT_NUM_IM3_IRL0 + 21) -+/* DFEV0, Channel 1 Transmit Interrupt */ -+#define FALCON_IRQ_DFEV0_2TX (INT_NUM_IM3_IRL0 + 26) -+/* DFEV0, Channel 1 Receive Interrupt */ -+#define FALCON_IRQ_DFEV0_2RX (INT_NUM_IM3_IRL0 + 27) -+/* DFEV0, Channel 1 General Purpose Interrupt */ -+#define FALCON_IRQ_DFEV0_2GP (INT_NUM_IM3_IRL0 + 28) -+/* DFEV0, Channel 0 Transmit Interrupt */ -+#define FALCON_IRQ_DFEV0_1TX (INT_NUM_IM3_IRL0 + 29) -+/* DFEV0, Channel 0 Receive Interrupt */ -+#define FALCON_IRQ_DFEV0_1RX (INT_NUM_IM3_IRL0 + 30) -+/* DFEV0, Channel 0 General Purpose Interrupt */ -+#define FALCON_IRQ_DFEV0_1GP (INT_NUM_IM3_IRL0 + 31) -+ -+/* ICTRLL 0 Error */ -+#define FALCON_IRQ_ICTRLL0_ERR (INT_NUM_IM4_IRL0 + 0) -+/* ICTRLL 1 Error */ -+#define FALCON_IRQ_ICTRLL1_ERR (INT_NUM_IM4_IRL0 + 1) -+/* ICTRLL 2 Error */ -+#define FALCON_IRQ_ICTRLL2_ERR (INT_NUM_IM4_IRL0 + 2) -+/* ICTRLL 3 Error */ -+#define FALCON_IRQ_ICTRLL3_ERR (INT_NUM_IM4_IRL0 + 3) -+/* OCTRLL 0 Error */ -+#define FALCON_IRQ_OCTRLL0_ERR (INT_NUM_IM4_IRL0 + 4) -+/* OCTRLL 1 Error */ -+#define FALCON_IRQ_OCTRLL1_ERR (INT_NUM_IM4_IRL0 + 5) -+/* OCTRLL 2 Error */ -+#define FALCON_IRQ_OCTRLL2_ERR (INT_NUM_IM4_IRL0 + 6) -+/* OCTRLL 3 Error */ -+#define FALCON_IRQ_OCTRLL3_ERR (INT_NUM_IM4_IRL0 + 7) -+/* ICTRLG Error */ -+#define FALCON_IRQ_ICTRLG_ERR (INT_NUM_IM4_IRL0 + 8) -+/* OCTRLG Error */ -+#define FALCON_IRQ_OCTRLG_ERR (INT_NUM_IM4_IRL0 + 9) -+/* IQM Error */ -+#define FALCON_IRQ_IQM_ERR (INT_NUM_IM4_IRL0 + 10) -+/* FSQM Error */ -+#define FALCON_IRQ_FSQM_ERR (INT_NUM_IM4_IRL0 + 11) -+/* TMU Error */ -+#define FALCON_IRQ_TMU_ERR (INT_NUM_IM4_IRL0 + 12) -+/* MPS Status Interrupt #0 (VPE1 to VPE0) */ -+#define FALCON_IRQ_MPS_IR0 (INT_NUM_IM4_IRL0 + 14) -+/* MPS Status Interrupt #1 (VPE1 to VPE0) */ -+#define FALCON_IRQ_MPS_IR1 (INT_NUM_IM4_IRL0 + 15) -+/* MPS Status Interrupt #2 (VPE1 to VPE0) */ -+#define FALCON_IRQ_MPS_IR2 (INT_NUM_IM4_IRL0 + 16) -+/* MPS Status Interrupt #3 (VPE1 to VPE0) */ -+#define FALCON_IRQ_MPS_IR3 (INT_NUM_IM4_IRL0 + 17) -+/* MPS Status Interrupt #4 (VPE1 to VPE0) */ -+#define FALCON_IRQ_MPS_IR4 (INT_NUM_IM4_IRL0 + 18) -+/* MPS Status Interrupt #5 (VPE1 to VPE0) */ -+#define FALCON_IRQ_MPS_IR5 (INT_NUM_IM4_IRL0 + 19) -+/* MPS Status Interrupt #6 (VPE1 to VPE0) */ -+#define FALCON_IRQ_MPS_IR6 (INT_NUM_IM4_IRL0 + 20) -+/* MPS Status Interrupt #7 (VPE1 to VPE0) */ -+#define FALCON_IRQ_MPS_IR7 (INT_NUM_IM4_IRL0 + 21) -+/* MPS Status Interrupt #8 (VPE1 to VPE0) */ -+#define FALCON_IRQ_MPS_IR8 (INT_NUM_IM4_IRL0 + 22) -+/* VPE0 Exception Level Flag Interrupt */ -+#define FALCON_IRQ_VPE0_EXL (INT_NUM_IM4_IRL0 + 29) -+/* VPE0 Error Level Flag Interrupt */ -+#define FALCON_IRQ_VPE0_ERL (INT_NUM_IM4_IRL0 + 30) -+/* VPE0 Performance Monitoring Counter Interrupt */ -+#define FALCON_IRQ_VPE0_PMCIR (INT_NUM_IM4_IRL0 + 31) -+ -+#endif /* _FALCON_IRQ__ */ ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/irq.h -@@ -0,0 +1,18 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2011 Thomas Langer -+ */ -+ -+#ifndef __FALCON_IRQ_H -+#define __FALCON_IRQ_H -+ -+#include -+ -+#define NR_IRQS 328 -+ -+#include_next -+ -+#endif ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h -@@ -0,0 +1,143 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2010 John Crispin -+ */ -+ -+#ifndef _LTQ_FALCON_H__ -+#define _LTQ_FALCON_H__ -+ -+#ifdef CONFIG_SOC_FALCON -+ -+#include -+ -+/* Chip IDs */ -+#define SOC_ID_FALCON 0x01B8 -+ -+/* SoC Types */ -+#define SOC_TYPE_FALCON 0x01 -+ -+/* ASC0/1 - serial port */ -+#define LTQ_ASC0_BASE_ADDR 0x1E100C00 -+#define LTQ_ASC1_BASE_ADDR 0x1E100B00 -+#define LTQ_ASC_SIZE 0x100 -+ -+#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8)) -+#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1) -+#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2) -+ -+/* -+ * during early_printk no ioremap possible at this early stage -+ * lets use KSEG1 instead -+ */ -+#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR) -+ -+/* ICU - interrupt control unit */ -+#define LTQ_ICU_BASE_ADDR 0x1F880200 -+#define LTQ_ICU_SIZE 0x100 -+ -+/* WDT */ -+#define LTQ_WDT_BASE_ADDR 0x1F8803F0 -+#define LTQ_WDT_SIZE 0x10 -+ -+#define LTQ_RST_CAUSE_WDTRST 0x0002 -+ -+/* EBU - external bus unit */ -+#define LTQ_EBU_BASE_ADDR 0x18000000 -+#define LTQ_EBU_SIZE 0x0100 -+ -+#define LTQ_EBU_MODCON 0x000C -+ -+/* GPIO */ -+#define LTQ_GPIO0_BASE_ADDR 0x1D810000 -+#define LTQ_GPIO0_SIZE 0x0080 -+#define LTQ_GPIO1_BASE_ADDR 0x1E800100 -+#define LTQ_GPIO1_SIZE 0x0080 -+#define LTQ_GPIO2_BASE_ADDR 0x1D810100 -+#define LTQ_GPIO2_SIZE 0x0080 -+#define LTQ_GPIO3_BASE_ADDR 0x1E800200 -+#define LTQ_GPIO3_SIZE 0x0080 -+#define LTQ_GPIO4_BASE_ADDR 0x1E800300 -+#define LTQ_GPIO4_SIZE 0x0080 -+#define LTQ_PADCTRL0_BASE_ADDR 0x1DB01000 -+#define LTQ_PADCTRL0_SIZE 0x0100 -+#define LTQ_PADCTRL1_BASE_ADDR 0x1E800400 -+#define LTQ_PADCTRL1_SIZE 0x0100 -+#define LTQ_PADCTRL2_BASE_ADDR 0x1DB02000 -+#define LTQ_PADCTRL2_SIZE 0x0100 -+#define LTQ_PADCTRL3_BASE_ADDR 0x1E800500 -+#define LTQ_PADCTRL3_SIZE 0x0100 -+#define LTQ_PADCTRL4_BASE_ADDR 0x1E800600 -+#define LTQ_PADCTRL4_SIZE 0x0100 -+ -+/* CHIP ID */ -+#define LTQ_STATUS_BASE_ADDR 0x1E802000 -+ -+#define LTQ_FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c)) -+#define LTQ_FALCON_CHIPTYPE ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x38)) -+#define LTQ_FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40)) -+ -+/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */ -+#define LTQ_SYS1_BASE_ADDR 0x1EF00000 -+#define LTQ_SYS1_SIZE 0x0100 -+#define LTQ_STATUS_BASE_ADDR 0x1E802000 -+#define LTQ_STATUS_SIZE 0x0080 -+#define LTQ_SYS_ETH_BASE_ADDR 0x1DB00000 -+#define LTQ_SYS_ETH_SIZE 0x0100 -+#define LTQ_SYS_GPE_BASE_ADDR 0x1D700000 -+#define LTQ_SYS_GPE_SIZE 0x0100 -+ -+#define SYSCTL_SYS1 0 -+#define SYSCTL_SYSETH 1 -+#define SYSCTL_SYSGPE 2 -+ -+/* Activation Status Register */ -+#define ACTS_ASC1_ACT 0x00000800 -+#define ACTS_P0 0x00010000 -+#define ACTS_P1 0x00010000 -+#define ACTS_P2 0x00020000 -+#define ACTS_P3 0x00020000 -+#define ACTS_P4 0x00040000 -+#define ACTS_PADCTRL0 0x00100000 -+#define ACTS_PADCTRL1 0x00100000 -+#define ACTS_PADCTRL2 0x00200000 -+#define ACTS_PADCTRL3 0x00200000 -+#define ACTS_PADCTRL4 0x00400000 -+ -+extern void ltq_sysctl_activate(int module, unsigned int mask); -+extern void ltq_sysctl_deactivate(int module, unsigned int mask); -+extern void ltq_sysctl_clken(int module, unsigned int mask); -+extern void ltq_sysctl_clkdis(int module, unsigned int mask); -+extern void ltq_sysctl_reboot(int module, unsigned int mask); -+extern int ltq_gpe_is_activated(unsigned int mask); -+ -+/* global register ranges */ -+extern __iomem void *ltq_ebu_membase; -+extern __iomem void *ltq_sys1_membase; -+#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) -+#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) -+#define ltq_ebu_w32_mask(clear, set, reg) \ -+ ltq_ebu_w32((ltq_ebu_r32(reg) & ~(clear)) | (set), reg) -+ -+#define ltq_sys1_w32(x, y) ltq_w32((x), ltq_sys1_membase + (y)) -+#define ltq_sys1_r32(x) ltq_r32(ltq_sys1_membase + (x)) -+#define ltq_sys1_w32_mask(clear, set, reg) \ -+ ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg) -+ -+/* gpio_request wrapper to help configure the pin */ -+extern int ltq_gpio_request(unsigned int pin, unsigned int mux, -+ unsigned int dir, const char *name); -+extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux); -+ -+/* to keep the irq code generic we need to define these to 0 as falcon -+ has no EIU/EBU */ -+#define LTQ_EIU_BASE_ADDR 0 -+#define LTQ_EBU_PCC_ISTAT 0 -+ -+#define ltq_is_ar9() 0 -+#define ltq_is_vr9() 0 -+ -+#endif /* CONFIG_SOC_FALCON */ -+#endif /* _LTQ_XWAY_H__ */ ---- a/arch/mips/include/asm/mach-lantiq/lantiq.h -+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h -@@ -25,6 +25,7 @@ extern unsigned int ltq_get_soc_type(voi - /* clock speeds */ - #define CLOCK_60M 60000000 - #define CLOCK_83M 83333333 -+#define CLOCK_100M 100000000 - #define CLOCK_111M 111111111 - #define CLOCK_133M 133333333 - #define CLOCK_167M 166666667 ---- a/arch/mips/lantiq/Kconfig -+++ b/arch/mips/lantiq/Kconfig -@@ -16,8 +16,12 @@ config SOC_XWAY - bool "XWAY" - select SOC_TYPE_XWAY - select HW_HAS_PCI -+ -+config SOC_FALCON -+ bool "FALCON" - endchoice - - source "arch/mips/lantiq/xway/Kconfig" -+source "arch/mips/lantiq/falcon/Kconfig" - - endif ---- a/arch/mips/lantiq/Makefile -+++ b/arch/mips/lantiq/Makefile -@@ -9,3 +9,4 @@ obj-y := irq.o setup.o clk.o prom.o devi - obj-$(CONFIG_EARLY_PRINTK) += early_printk.o - - obj-$(CONFIG_SOC_TYPE_XWAY) += xway/ -+obj-$(CONFIG_SOC_FALCON) += falcon/ ---- a/arch/mips/lantiq/Platform -+++ b/arch/mips/lantiq/Platform -@@ -6,3 +6,4 @@ platform-$(CONFIG_LANTIQ) += lantiq/ - cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq - load-$(CONFIG_LANTIQ) = 0xffffffff80002000 - cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway -+cflags-$(CONFIG_SOC_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon ---- /dev/null -+++ b/arch/mips/lantiq/falcon/Makefile -@@ -0,0 +1 @@ -+obj-y := clk.o prom.o reset.o sysctrl.o devices.o ---- /dev/null -+++ b/arch/mips/lantiq/falcon/clk.c -@@ -0,0 +1,44 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2011 Thomas Langer -+ * Copyright (C) 2011 John Crispin -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "devices.h" -+ -+/* CPU0 Clock Control Register */ -+#define LTQ_SYS1_CPU0CC 0x0040 -+/* clock divider bit */ -+#define LTQ_CPU0CC_CPUDIV 0x0001 -+ -+unsigned int -+ltq_get_io_region_clock(void) -+{ -+ return CLOCK_200M; -+} -+EXPORT_SYMBOL(ltq_get_io_region_clock); -+ -+unsigned int -+ltq_get_cpu_hz(void) -+{ -+ if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV) -+ return CLOCK_200M; -+ else -+ return CLOCK_400M; -+} -+EXPORT_SYMBOL(ltq_get_cpu_hz); -+ -+unsigned int -+ltq_get_fpi_hz(void) -+{ -+ return CLOCK_100M; -+} -+EXPORT_SYMBOL(ltq_get_fpi_hz); ---- /dev/null -+++ b/arch/mips/lantiq/falcon/devices.c -@@ -0,0 +1,87 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2011 Thomas Langer -+ * Copyright (C) 2011 John Crispin -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "devices.h" -+ -+/* nand flash */ -+/* address lines used for NAND control signals */ -+#define NAND_ADDR_ALE 0x10000 -+#define NAND_ADDR_CLE 0x20000 -+/* Ready/Busy Status */ -+#define MODCON_STS 0x0002 -+/* Ready/Busy Status Edge */ -+#define MODCON_STSEDGE 0x0004 -+ -+static const char *part_probes[] = { "cmdlinepart", NULL }; -+ -+static int -+falcon_nand_ready(struct mtd_info *mtd) -+{ -+ u32 modcon = ltq_ebu_r32(LTQ_EBU_MODCON); -+ -+ return (((modcon & (MODCON_STS | MODCON_STSEDGE)) == -+ (MODCON_STS | MODCON_STSEDGE))); -+} -+ -+static void -+falcon_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -+{ -+ struct nand_chip *this = mtd->priv; -+ unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; -+ -+ if (ctrl & NAND_CTRL_CHANGE) { -+ nandaddr &= ~(NAND_ADDR_ALE | NAND_ADDR_CLE); -+ -+ if (ctrl & NAND_CLE) -+ nandaddr |= NAND_ADDR_CLE; -+ if (ctrl & NAND_ALE) -+ nandaddr |= NAND_ADDR_ALE; -+ -+ this->IO_ADDR_W = (void __iomem *) nandaddr; -+ } -+ -+ if (cmd != NAND_CMD_NONE) -+ writeb(cmd, this->IO_ADDR_W); -+} -+ -+static struct platform_nand_data falcon_flash_nand_data = { -+ .chip = { -+ .nr_chips = 1, -+ .chip_delay = 25, -+ .part_probe_types = part_probes, -+ }, -+ .ctrl = { -+ .cmd_ctrl = falcon_hwcontrol, -+ .dev_ready = falcon_nand_ready, -+ } -+}; -+ -+static struct resource ltq_nand_res = -+ MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX); -+ -+static struct platform_device ltq_flash_nand = { -+ .name = "gen_nand", -+ .id = -1, -+ .num_resources = 1, -+ .resource = <q_nand_res, -+ .dev = { -+ .platform_data = &falcon_flash_nand_data, -+ }, -+}; -+ -+void __init -+falcon_register_nand(void) -+{ -+ platform_device_register(<q_flash_nand); -+} ---- /dev/null -+++ b/arch/mips/lantiq/falcon/devices.h -@@ -0,0 +1,18 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * Copyright (C) 2011 Thomas Langer -+ * Copyright (C) 2011 John Crispin -+ */ -+ -+#ifndef _FALCON_DEVICES_H__ -+#define _FALCON_DEVICES_H__ -+ -+#include "../devices.h" -+ -+extern void falcon_register_nand(void); -+ -+#endif ---- /dev/null -+++ b/arch/mips/lantiq/falcon/prom.c -@@ -0,0 +1,93 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2011 Thomas Langer -+ * Copyright (C) 2011 John Crispin -+ */ -+ -+#include -+ -+#include "devices.h" -+ -+#include "../prom.h" -+ -+#define SOC_FALCON "Falcon" -+#define SOC_FALCON_D "Falcon-D" -+#define SOC_FALCON_V "Falcon-V" -+#define SOC_FALCON_M "Falcon-M" -+ -+#define PART_SHIFT 12 -+#define PART_MASK 0x0FFFF000 -+#define REV_SHIFT 28 -+#define REV_MASK 0xF0000000 -+#define SREV_SHIFT 22 -+#define SREV_MASK 0x03C00000 -+#define TYPE_SHIFT 26 -+#define TYPE_MASK 0x3C000000 -+ -+#define MUXC_SIF_RX_PIN 112 -+#define MUXC_SIF_TX_PIN 113 -+ -+/* this parameter allows us enable/disable asc1 via commandline */ -+static int register_asc1; -+static int __init -+ltq_parse_asc1(char *p) -+{ -+ register_asc1 = 1; -+ return 0; -+} -+__setup("use_asc1", ltq_parse_asc1); -+ -+void __init -+ltq_soc_setup(void) -+{ -+ ltq_register_asc(0); -+ ltq_register_wdt(); -+ falcon_register_gpio(); -+ if (register_asc1) { -+ ltq_register_asc(1); -+ if (ltq_gpio_request(MUXC_SIF_RX_PIN, 3, 0, "asc1-rx")) -+ pr_err("failed to request asc1-rx"); -+ if (ltq_gpio_request(MUXC_SIF_TX_PIN, 3, 1, "asc1-tx")) -+ pr_err("failed to request asc1-tx"); -+ ltq_sysctl_activate(SYSCTL_SYS1, ACTS_ASC1_ACT); -+ } -+} -+ -+void __init -+ltq_soc_detect(struct ltq_soc_info *i) -+{ -+ u32 type; -+ i->partnum = (ltq_r32(LTQ_FALCON_CHIPID) & PART_MASK) >> PART_SHIFT; -+ i->rev = (ltq_r32(LTQ_FALCON_CHIPID) & REV_MASK) >> REV_SHIFT; -+ i->srev = ((ltq_r32(LTQ_FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT); -+ sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'), -+ i->rev & 0x7, (i->srev & 0x3) + 1); -+ -+ switch (i->partnum) { -+ case SOC_ID_FALCON: -+ type = (ltq_r32(LTQ_FALCON_CHIPTYPE) & TYPE_MASK) >> TYPE_SHIFT; -+ switch (type) { -+ case 0: -+ i->name = SOC_FALCON_D; -+ break; -+ case 1: -+ i->name = SOC_FALCON_V; -+ break; -+ case 2: -+ i->name = SOC_FALCON_M; -+ break; -+ default: -+ i->name = SOC_FALCON; -+ break; -+ } -+ i->type = SOC_TYPE_FALCON; -+ break; -+ -+ default: -+ unreachable(); -+ break; -+ } -+} ---- /dev/null -+++ b/arch/mips/lantiq/falcon/reset.c -@@ -0,0 +1,87 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2011 Thomas Langer -+ * Copyright (C) 2011 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+/* CPU0 Reset Source Register */ -+#define LTQ_SYS1_CPU0RS 0x0040 -+/* reset cause mask */ -+#define LTQ_CPU0RS_MASK 0x0003 -+ -+int -+ltq_reset_cause(void) -+{ -+ return ltq_sys1_r32(LTQ_SYS1_CPU0RS) & LTQ_CPU0RS_MASK; -+} -+EXPORT_SYMBOL_GPL(ltq_reset_cause); -+ -+#define BOOT_REG_BASE (KSEG1 | 0x1F200000) -+#define BOOT_PW1_REG (BOOT_REG_BASE | 0x20) -+#define BOOT_PW2_REG (BOOT_REG_BASE | 0x24) -+#define BOOT_PW1 0x4C545100 -+#define BOOT_PW2 0x0051544C -+ -+#define WDT_REG_BASE (KSEG1 | 0x1F8803F0) -+#define WDT_PW1 0x00BE0000 -+#define WDT_PW2 0x00DC0000 -+ -+static void -+ltq_machine_restart(char *command) -+{ -+ pr_notice("System restart\n"); -+ local_irq_disable(); -+ -+ /* reboot magic */ -+ ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */ -+ ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */ -+ ltq_w32(0, (void *)BOOT_REG_BASE); /* reset Bootreg RVEC */ -+ -+ /* watchdog magic */ -+ ltq_w32(WDT_PW1, (void *)WDT_REG_BASE); -+ ltq_w32(WDT_PW2 | -+ (0x3 << 26) | /* PWL */ -+ (0x2 << 24) | /* CLKDIV */ -+ (0x1 << 31) | /* enable */ -+ (1), /* reload */ -+ (void *)WDT_REG_BASE); -+ unreachable(); -+} -+ -+static void -+ltq_machine_halt(void) -+{ -+ pr_notice("System halted.\n"); -+ local_irq_disable(); -+ unreachable(); -+} -+ -+static void -+ltq_machine_power_off(void) -+{ -+ pr_notice("Please turn off the power now.\n"); -+ local_irq_disable(); -+ unreachable(); -+} -+ -+static int __init -+mips_reboot_setup(void) -+{ -+ _machine_restart = ltq_machine_restart; -+ _machine_halt = ltq_machine_halt; -+ pm_power_off = ltq_machine_power_off; -+ return 0; -+} -+ -+arch_initcall(mips_reboot_setup); ---- /dev/null -+++ b/arch/mips/lantiq/falcon/sysctrl.c -@@ -0,0 +1,183 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2011 Thomas Langer -+ * Copyright (C) 2011 John Crispin -+ */ -+ -+#include -+#include -+#include -+ -+#include -+ -+#include "devices.h" -+ -+/* infrastructure control register */ -+#define SYS1_INFRAC 0x00bc -+/* Configuration fuses for drivers and pll */ -+#define STATUS_CONFIG 0x0040 -+ -+/* GPE frequency selection */ -+#define GPPC_OFFSET 24 -+#define GPEFREQ_MASK 0x00000C0 -+#define GPEFREQ_OFFSET 10 -+/* Clock status register */ -+#define LTQ_SYSCTL_CLKS 0x0000 -+/* Clock enable register */ -+#define LTQ_SYSCTL_CLKEN 0x0004 -+/* Clock clear register */ -+#define LTQ_SYSCTL_CLKCLR 0x0008 -+/* Activation Status Register */ -+#define LTQ_SYSCTL_ACTS 0x0020 -+/* Activation Register */ -+#define LTQ_SYSCTL_ACT 0x0024 -+/* Deactivation Register */ -+#define LTQ_SYSCTL_DEACT 0x0028 -+/* reboot Register */ -+#define LTQ_SYSCTL_RBT 0x002c -+ -+static struct resource ltq_sysctl_res[] = { -+ MEM_RES("sys1", LTQ_SYS1_BASE_ADDR, LTQ_SYS1_SIZE), -+ MEM_RES("syseth", LTQ_SYS_ETH_BASE_ADDR, LTQ_SYS_ETH_SIZE), -+ MEM_RES("sysgpe", LTQ_SYS_GPE_BASE_ADDR, LTQ_SYS_GPE_SIZE), -+}; -+ -+static struct resource ltq_status_res = -+ MEM_RES("status", LTQ_STATUS_BASE_ADDR, LTQ_STATUS_SIZE); -+static struct resource ltq_ebu_res = -+ MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE); -+ -+static void __iomem *ltq_sysctl[3]; -+static void __iomem *ltq_status_membase; -+void __iomem *ltq_sys1_membase; -+void __iomem *ltq_ebu_membase; -+ -+#define ltq_reg_w32(m, x, y) ltq_w32((x), ltq_sysctl[m] + (y)) -+#define ltq_reg_r32(m, x) ltq_r32(ltq_sysctl[m] + (x)) -+#define ltq_reg_w32_mask(m, clear, set, reg) \ -+ ltq_reg_w32(m, (ltq_reg_r32(m, reg) & ~(clear)) | (set), reg) -+ -+#define ltq_status_w32(x, y) ltq_w32((x), ltq_status_membase + (y)) -+#define ltq_status_r32(x) ltq_r32(ltq_status_membase + (x)) -+ -+static inline void -+ltq_sysctl_wait(int module, unsigned int mask, -+ unsigned int test, unsigned int reg) -+{ -+ int err = 1000000; -+ -+ do {} while (--err && ((ltq_reg_r32(module, reg) -+ & mask) != test)); -+ if (!err) -+ pr_err("module de/activation failed %d %08X %08X\n", -+ module, mask, test); -+} -+ -+void -+ltq_sysctl_activate(int module, unsigned int mask) -+{ -+ if (module > SYSCTL_SYSGPE) -+ return; -+ -+ ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN); -+ ltq_reg_w32(module, mask, LTQ_SYSCTL_ACT); -+ ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS); -+} -+EXPORT_SYMBOL(ltq_sysctl_activate); -+ -+void -+ltq_sysctl_deactivate(int module, unsigned int mask) -+{ -+ if (module > SYSCTL_SYSGPE) -+ return; -+ -+ ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR); -+ ltq_reg_w32(module, mask, LTQ_SYSCTL_DEACT); -+ ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_ACTS); -+} -+EXPORT_SYMBOL(ltq_sysctl_deactivate); -+ -+void -+ltq_sysctl_clken(int module, unsigned int mask) -+{ -+ if (module > SYSCTL_SYSGPE) -+ return; -+ -+ ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN); -+ ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_CLKS); -+} -+EXPORT_SYMBOL(ltq_sysctl_clken); -+ -+void -+ltq_sysctl_clkdis(int module, unsigned int mask) -+{ -+ if (module > SYSCTL_SYSGPE) -+ return; -+ -+ ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR); -+ ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_CLKS); -+} -+EXPORT_SYMBOL(ltq_sysctl_clkdis); -+ -+void -+ltq_sysctl_reboot(int module, unsigned int mask) -+{ -+ unsigned int act; -+ -+ if (module > SYSCTL_SYSGPE) -+ return; -+ -+ act = ltq_reg_r32(module, LTQ_SYSCTL_ACT); -+ if ((~act & mask) != 0) -+ ltq_sysctl_activate(module, ~act & mask); -+ ltq_reg_w32(module, act & mask, LTQ_SYSCTL_RBT); -+ ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS); -+} -+EXPORT_SYMBOL(ltq_sysctl_reboot); -+ -+/* enable the ONU core */ -+static void -+ltq_gpe_enable(void) -+{ -+ unsigned int freq; -+ unsigned int status; -+ -+ /* if if the clock is already enabled */ -+ status = ltq_reg_r32(SYSCTL_SYS1, SYS1_INFRAC); -+ if (status & (1 << (GPPC_OFFSET + 1))) -+ return; -+ -+ if (ltq_status_r32(STATUS_CONFIG) == 0) -+ freq = 1; /* use 625MHz on unfused chip */ -+ else -+ freq = (ltq_status_r32(STATUS_CONFIG) & -+ GPEFREQ_MASK) >> -+ GPEFREQ_OFFSET; -+ -+ /* apply new frequency */ -+ ltq_reg_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1), -+ freq << (GPPC_OFFSET + 2) , SYS1_INFRAC); -+ udelay(1); -+ -+ /* enable new frequency */ -+ ltq_reg_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC); -+ udelay(1); -+} -+ -+void __init -+ltq_soc_init(void) -+{ -+ int i; -+ -+ for (i = 0; i < 3; i++) -+ ltq_sysctl[i] = ltq_remap_resource(<q_sysctl_res[i]); -+ -+ ltq_sys1_membase = ltq_sysctl[0]; -+ ltq_status_membase = ltq_remap_resource(<q_status_res); -+ ltq_ebu_membase = ltq_remap_resource(<q_ebu_res); -+ -+ ltq_gpe_enable(); -+} diff --git a/target/linux/lantiq/patches-3.3/0005-pci-support.patch b/target/linux/lantiq/patches-3.3/0005-pci-support.patch new file mode 100644 index 0000000000..bdc8901f41 --- /dev/null +++ b/target/linux/lantiq/patches-3.3/0005-pci-support.patch @@ -0,0 +1,355 @@ +From b80a5236053be899421417871d1be8016912e94b Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 09:52:10 +0200 +Subject: [PATCH 05/25] pci support + +--- + arch/mips/include/asm/mach-lantiq/lantiq.h | 37 ++++----- + .../mips/include/asm/mach-lantiq/lantiq_platform.h | 9 ++ + arch/mips/pci/Makefile | 5 +- + arch/mips/pci/ops-lantiq.c | 6 +- + arch/mips/pci/pci-lantiq.c | 82 ++++++++------------ + arch/mips/pci/pci-lantiq.h | 2 +- + arch/mips/pci/pci.c | 25 ++++++ + 7 files changed, 89 insertions(+), 77 deletions(-) + +diff --git a/arch/mips/include/asm/mach-lantiq/lantiq.h b/arch/mips/include/asm/mach-lantiq/lantiq.h +index ce2f029..622847f 100644 +--- a/arch/mips/include/asm/mach-lantiq/lantiq.h ++++ b/arch/mips/include/asm/mach-lantiq/lantiq.h +@@ -9,6 +9,8 @@ + #define _LANTIQ_H__ + + #include ++#include ++#include + + /* generic reg access functions */ + #define ltq_r32(reg) __raw_readl(reg) +@@ -18,40 +20,33 @@ + #define ltq_r8(reg) __raw_readb(reg) + #define ltq_w8(val, reg) __raw_writeb(val, reg) + +-/* register access macros for EBU and CGU */ +-#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) +-#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) +-#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y)) +-#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x)) +- +-extern __iomem void *ltq_ebu_membase; +-extern __iomem void *ltq_cgu_membase; +- + extern unsigned int ltq_get_cpu_ver(void); + extern unsigned int ltq_get_soc_type(void); + +-/* clock speeds */ +-#define CLOCK_60M 60000000 +-#define CLOCK_83M 83333333 +-#define CLOCK_111M 111111111 +-#define CLOCK_133M 133333333 +-#define CLOCK_167M 166666667 +-#define CLOCK_200M 200000000 +-#define CLOCK_266M 266666666 +-#define CLOCK_333M 333333333 +-#define CLOCK_400M 400000000 +- + /* spinlock all ebu i/o */ + extern spinlock_t ebu_lock; + ++/* request a non-gpio and set the PIO config */ ++extern int ltq_gpio_request(struct device *dev, unsigned int pin, ++ unsigned int mux, unsigned int dir, const char *name); ++ + /* some irq helpers */ + extern void ltq_disable_irq(struct irq_data *data); + extern void ltq_mask_and_ack_irq(struct irq_data *data); + extern void ltq_enable_irq(struct irq_data *data); + ++/* clock handling */ ++extern int clk_activate(struct clk *clk); ++extern void clk_deactivate(struct clk *clk); ++extern struct clk *clk_get_cpu(void); ++extern struct clk *clk_get_fpi(void); ++extern struct clk *clk_get_io(void); ++ + /* find out what caused the last cpu reset */ + extern int ltq_reset_cause(void); +-#define LTQ_RST_CAUSE_WDTRST 0x20 ++ ++/* helper for requesting and remapping resources */ ++extern void __iomem *ltq_remap_resource(struct resource *res); + + #define IOPORT_RESOURCE_START 0x10000000 + #define IOPORT_RESOURCE_END 0xffffffff +diff --git a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h +index a305f1d..38ed938 100644 +--- a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h ++++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h +@@ -50,4 +50,13 @@ struct ltq_eth_data { + int mii_mode; + }; + ++ ++struct ltq_spi_platform_data { ++ u16 num_chipselect; ++}; ++ ++struct ltq_spi_controller_data { ++ unsigned gpio; ++}; ++ + #endif +diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile +index c3ac4b0..31e70c5 100644 +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -41,7 +41,10 @@ obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1250.o pci-sb1250.o + obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o + obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o + obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o +-obj-$(CONFIG_SOC_XWAY) += pci-lantiq.o ops-lantiq.o ++obj-$(CONFIG_LANTIQ) += fixup-lantiq.o ++obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o ++obj-$(CONFIG_PCIE_LANTIQ) += pcie-lantiq-phy.o pcie-lantiq.o fixup-lantiq-pcie.o ++obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o + obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o + obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o + obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o +diff --git a/arch/mips/pci/ops-lantiq.c b/arch/mips/pci/ops-lantiq.c +index 1f2afb5..5cbb0cf 100644 +--- a/arch/mips/pci/ops-lantiq.c ++++ b/arch/mips/pci/ops-lantiq.c +@@ -41,7 +41,7 @@ static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus, + + spin_lock_irqsave(&ebu_lock, flags); + +- cfg_base = (unsigned long) ltq_pci_mapped_cfg; ++ cfg_base = (unsigned long) ltq_pci_cfgbase; + cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn << + LTQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3); + +@@ -55,11 +55,11 @@ static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus, + wmb(); + + /* clean possible Master abort */ +- cfg_base = (unsigned long) ltq_pci_mapped_cfg; ++ cfg_base = (unsigned long) ltq_pci_cfgbase; + cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4; + temp = ltq_r32(((u32 *)(cfg_base))); + temp = swab32(temp); +- cfg_base = (unsigned long) ltq_pci_mapped_cfg; ++ cfg_base = (unsigned long) ltq_pci_cfgbase; + cfg_base |= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4; + ltq_w32(temp, ((u32 *)cfg_base)); + +diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c +index be1e1af..7a29738 100644 +--- a/arch/mips/pci/pci-lantiq.c ++++ b/arch/mips/pci/pci-lantiq.c +@@ -65,45 +65,42 @@ + #define ltq_pci_w32(x, y) ltq_w32((x), ltq_pci_membase + (y)) + #define ltq_pci_r32(x) ltq_r32(ltq_pci_membase + (x)) + +-#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y)) +-#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x)) ++#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_cfgbase + (y)) ++#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_cfgbase + (x)) + + struct ltq_pci_gpio_map { + int pin; +- int alt0; +- int alt1; ++ int mux; + int dir; + char *name; + }; + + /* the pci core can make use of the following gpios */ + static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = { +- { 0, 1, 0, 0, "pci-exin0" }, +- { 1, 1, 0, 0, "pci-exin1" }, +- { 2, 1, 0, 0, "pci-exin2" }, +- { 39, 1, 0, 0, "pci-exin3" }, +- { 10, 1, 0, 0, "pci-exin4" }, +- { 9, 1, 0, 0, "pci-exin5" }, +- { 30, 1, 0, 1, "pci-gnt1" }, +- { 23, 1, 0, 1, "pci-gnt2" }, +- { 19, 1, 0, 1, "pci-gnt3" }, +- { 38, 1, 0, 1, "pci-gnt4" }, +- { 29, 1, 0, 0, "pci-req1" }, +- { 31, 1, 0, 0, "pci-req2" }, +- { 3, 1, 0, 0, "pci-req3" }, +- { 37, 1, 0, 0, "pci-req4" }, ++ { 0, 2, 0, "pci-exin0" }, ++ { 1, 2, 0, "pci-exin1" }, ++ { 2, 2, 0, "pci-exin2" }, ++ { 39, 2, 0, "pci-exin3" }, ++ { 10, 2, 0, "pci-exin4" }, ++ { 9, 2, 0, "pci-exin5" }, ++ { 30, 2, 1, "pci-gnt1" }, ++ { 23, 2, 1, "pci-gnt2" }, ++ { 19, 2, 1, "pci-gnt3" }, ++ { 38, 2, 1, "pci-gnt4" }, ++ { 29, 2, 0, "pci-req1" }, ++ { 31, 2, 0, "pci-req2" }, ++ { 3, 2, 0, "pci-req3" }, ++ { 37, 2, 0, "pci-req4" }, + }; + +-__iomem void *ltq_pci_mapped_cfg; ++__iomem void *ltq_pci_cfgbase; + static __iomem void *ltq_pci_membase; + +-int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL; +- + /* Since the PCI REQ pins can be reused for other functionality, make it + possible to exclude those from interpretation by the PCI controller */ + static int ltq_pci_req_mask = 0xf; + +-static int *ltq_pci_irq_map; ++extern int *ltq_pci_irq_map; + + struct pci_ops ltq_pci_ops = { + .read = ltq_pci_read_config_dword, +@@ -132,14 +129,6 @@ static struct pci_controller ltq_pci_controller = { + .io_offset = 0x00000000UL, + }; + +-int pcibios_plat_dev_init(struct pci_dev *dev) +-{ +- if (ltqpci_plat_dev_init) +- return ltqpci_plat_dev_init(dev); +- +- return 0; +-} +- + static u32 ltq_calc_bar11mask(void) + { + u32 mem, bar11mask; +@@ -151,25 +140,26 @@ static u32 ltq_calc_bar11mask(void) + return bar11mask; + } + +-static void ltq_pci_setup_gpio(int gpio) ++static void ltq_pci_setup_gpio(struct device *dev) + { ++ struct ltq_pci_data *conf = (struct ltq_pci_data *) dev->platform_data; + int i; + for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) { +- if (gpio & (1 << i)) { +- ltq_gpio_request(ltq_pci_gpio_map[i].pin, +- ltq_pci_gpio_map[i].alt0, +- ltq_pci_gpio_map[i].alt1, ++ if (conf->gpio & (1 << i)) { ++ ltq_gpio_request(dev, ltq_pci_gpio_map[i].pin, ++ ltq_pci_gpio_map[i].mux, + ltq_pci_gpio_map[i].dir, + ltq_pci_gpio_map[i].name); + } + } +- ltq_gpio_request(21, 0, 0, 1, "pci-reset"); +- ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK; ++ ltq_gpio_request(dev, 21, 0, 1, "pci-reset"); ++ ltq_pci_req_mask = (conf->gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK; + } + +-static int __devinit ltq_pci_startup(struct ltq_pci_data *conf) ++static int __devinit ltq_pci_startup(struct device *dev) + { + u32 temp_buffer; ++ struct ltq_pci_data *conf = (struct ltq_pci_data *) dev->platform_data; + + /* set clock to 33Mhz */ + if (ltq_is_ar9()) { +@@ -192,7 +182,7 @@ static int __devinit ltq_pci_startup(struct ltq_pci_data *conf) + } + + /* setup pci clock and gpis used by pci */ +- ltq_pci_setup_gpio(conf->gpio); ++ ltq_pci_setup_gpio(dev); + + /* enable auto-switching between PCI and EBU */ + ltq_pci_w32(0xa, PCI_CR_CLK_CTRL); +@@ -256,16 +246,6 @@ static int __devinit ltq_pci_startup(struct ltq_pci_data *conf) + return 0; + } + +-int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +-{ +- if (ltq_pci_irq_map[slot]) +- return ltq_pci_irq_map[slot]; +- printk(KERN_ERR "lq_pci: trying to map irq for unknown slot %d\n", +- slot); +- +- return 0; +-} +- + static int __devinit ltq_pci_probe(struct platform_device *pdev) + { + struct ltq_pci_data *ltq_pci_data = +@@ -273,11 +253,11 @@ static int __devinit ltq_pci_probe(struct platform_device *pdev) + pci_probe_only = 0; + ltq_pci_irq_map = ltq_pci_data->irq; + ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE); +- ltq_pci_mapped_cfg = ++ ltq_pci_cfgbase = + ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE); + ltq_pci_controller.io_map_base = + (unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1); +- ltq_pci_startup(ltq_pci_data); ++ ltq_pci_startup(&pdev->dev); + register_pci_controller(<q_pci_controller); + + return 0; +diff --git a/arch/mips/pci/pci-lantiq.h b/arch/mips/pci/pci-lantiq.h +index 66bf6cd..c4721b4 100644 +--- a/arch/mips/pci/pci-lantiq.h ++++ b/arch/mips/pci/pci-lantiq.h +@@ -9,7 +9,7 @@ + #ifndef _LTQ_PCI_H__ + #define _LTQ_PCI_H__ + +-extern __iomem void *ltq_pci_mapped_cfg; ++extern __iomem void *ltq_pci_cfgbase; + extern int ltq_pci_read_config_dword(struct pci_bus *bus, + unsigned int devfn, int where, int size, u32 *val); + extern int ltq_pci_write_config_dword(struct pci_bus *bus, +diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c +index 1552150..cd034a9 100644 +--- a/arch/mips/pci/pci.c ++++ b/arch/mips/pci/pci.c +@@ -201,6 +201,31 @@ static int __init pcibios_init(void) + + subsys_initcall(pcibios_init); + ++int pcibios_host_nr(void) ++{ ++ int count; ++ struct pci_controller *hose; ++ for (count = 0, hose = hose_head; hose; hose = hose->next, count++) { ++ ; ++ } ++ return count; ++} ++EXPORT_SYMBOL(pcibios_host_nr); ++ ++int pcibios_1st_host_bus_nr(void) ++{ ++ int bus_nr = 0; ++ struct pci_controller *hose = hose_head; ++ ++ if (hose != NULL) { ++ if (hose->bus != NULL) { ++ bus_nr = hose->bus->subordinate + 1; ++ } ++ } ++ return bus_nr; ++} ++EXPORT_SYMBOL(pcibios_1st_host_bus_nr); ++ + static int pcibios_enable_resources(struct pci_dev *dev, int mask) + { + u16 cmd, old_cmd; +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0006-MIPS-lantiq-add-support-for-FALC-ON-GPIOs.patch b/target/linux/lantiq/patches-3.3/0006-MIPS-lantiq-add-support-for-FALC-ON-GPIOs.patch deleted file mode 100644 index fed60a90d8..0000000000 --- a/target/linux/lantiq/patches-3.3/0006-MIPS-lantiq-add-support-for-FALC-ON-GPIOs.patch +++ /dev/null @@ -1,489 +0,0 @@ -From 92cd0e8b6247ac8c0db5cdc570543c6caa51b1ab Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 11 Aug 2011 14:35:02 +0200 -Subject: [PATCH 06/70] MIPS: lantiq: add support for FALC-ON GPIOs - -FALC-ON uses a different GPIO core than the other Lantiq SoCs. This patch adds -the new driver. - -Signed-off-by: Thomas Langer -Signed-off-by: John Crispin ---- - arch/mips/lantiq/falcon/Makefile | 2 +- - arch/mips/lantiq/falcon/devices.c | 41 ++++ - arch/mips/lantiq/falcon/devices.h | 2 + - arch/mips/lantiq/falcon/gpio.c | 399 +++++++++++++++++++++++++++++++++++++ - 4 files changed, 443 insertions(+), 1 deletions(-) - create mode 100644 arch/mips/lantiq/falcon/gpio.c - ---- a/arch/mips/lantiq/falcon/Makefile -+++ b/arch/mips/lantiq/falcon/Makefile -@@ -1 +1 @@ --obj-y := clk.o prom.o reset.o sysctrl.o devices.o -+obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o ---- a/arch/mips/lantiq/falcon/devices.c -+++ b/arch/mips/lantiq/falcon/devices.c -@@ -9,6 +9,7 @@ - - #include - #include -+#include - - #include - -@@ -85,3 +86,43 @@ falcon_register_nand(void) - { - platform_device_register(<q_flash_nand); - } -+ -+/* gpio */ -+#define DECLARE_GPIO_RES(port) \ -+static struct resource falcon_gpio ## port ## _res[] = { \ -+ MEM_RES("gpio"#port, LTQ_GPIO ## port ## _BASE_ADDR, \ -+ LTQ_GPIO ## port ## _SIZE), \ -+ MEM_RES("padctrl"#port, LTQ_PADCTRL ## port ## _BASE_ADDR, \ -+ LTQ_PADCTRL ## port ## _SIZE), \ -+ IRQ_RES("gpio_mux"#port, FALCON_IRQ_GPIO_P ## port) \ -+} -+DECLARE_GPIO_RES(0); -+DECLARE_GPIO_RES(1); -+DECLARE_GPIO_RES(2); -+DECLARE_GPIO_RES(3); -+DECLARE_GPIO_RES(4); -+ -+void __init -+falcon_register_gpio(void) -+{ -+ platform_device_register_simple("falcon_gpio", 0, -+ falcon_gpio0_res, ARRAY_SIZE(falcon_gpio0_res)); -+ platform_device_register_simple("falcon_gpio", 1, -+ falcon_gpio1_res, ARRAY_SIZE(falcon_gpio1_res)); -+ platform_device_register_simple("falcon_gpio", 2, -+ falcon_gpio2_res, ARRAY_SIZE(falcon_gpio2_res)); -+ ltq_sysctl_activate(SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1); -+ ltq_sysctl_activate(SYSCTL_SYSETH, ACTS_PADCTRL0 | -+ ACTS_PADCTRL2 | ACTS_P0 | ACTS_P2); -+} -+ -+void __init -+falcon_register_gpio_extra(void) -+{ -+ platform_device_register_simple("falcon_gpio", 3, -+ falcon_gpio3_res, ARRAY_SIZE(falcon_gpio3_res)); -+ platform_device_register_simple("falcon_gpio", 4, -+ falcon_gpio4_res, ARRAY_SIZE(falcon_gpio4_res)); -+ ltq_sysctl_activate(SYSCTL_SYS1, -+ ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4); -+} ---- a/arch/mips/lantiq/falcon/devices.h -+++ b/arch/mips/lantiq/falcon/devices.h -@@ -14,5 +14,7 @@ - #include "../devices.h" - - extern void falcon_register_nand(void); -+extern void falcon_register_gpio(void); -+extern void falcon_register_gpio_extra(void); - - #endif ---- /dev/null -+++ b/arch/mips/lantiq/falcon/gpio.c -@@ -0,0 +1,399 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2011 Thomas Langer -+ * Copyright (C) 2011 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+/* Multiplexer Control Register */ -+#define LTQ_PADC_MUX(x) (x * 0x4) -+/* Pad Control Availability Register */ -+#define LTQ_PADC_AVAIL 0x000000F0 -+ -+/* Data Output Register */ -+#define LTQ_GPIO_OUT 0x00000000 -+/* Data Input Register */ -+#define LTQ_GPIO_IN 0x00000004 -+/* Direction Register */ -+#define LTQ_GPIO_DIR 0x00000008 -+/* External Interrupt Control Register 0 */ -+#define LTQ_GPIO_EXINTCR0 0x00000018 -+/* External Interrupt Control Register 1 */ -+#define LTQ_GPIO_EXINTCR1 0x0000001C -+/* IRN Capture Register */ -+#define LTQ_GPIO_IRNCR 0x00000020 -+/* IRN Interrupt Configuration Register */ -+#define LTQ_GPIO_IRNCFG 0x0000002C -+/* IRN Interrupt Enable Set Register */ -+#define LTQ_GPIO_IRNRNSET 0x00000030 -+/* IRN Interrupt Enable Clear Register */ -+#define LTQ_GPIO_IRNENCLR 0x00000034 -+/* Output Set Register */ -+#define LTQ_GPIO_OUTSET 0x00000040 -+/* Output Cler Register */ -+#define LTQ_GPIO_OUTCLR 0x00000044 -+/* Direction Clear Register */ -+#define LTQ_GPIO_DIRSET 0x00000048 -+/* Direction Set Register */ -+#define LTQ_GPIO_DIRCLR 0x0000004C -+ -+/* turn a gpio_chip into a falcon_gpio_port */ -+#define ctop(c) container_of(c, struct falcon_gpio_port, gpio_chip) -+/* turn a irq_data into a falcon_gpio_port */ -+#define itop(i) ((struct falcon_gpio_port *) irq_get_chip_data(i->irq)) -+ -+#define ltq_pad_r32(p, reg) ltq_r32(p->pad + reg) -+#define ltq_pad_w32(p, val, reg) ltq_w32(val, p->pad + reg) -+#define ltq_pad_w32_mask(c, clear, set, reg) \ -+ ltq_pad_w32(c, (ltq_pad_r32(c, reg) & ~(clear)) | (set), reg) -+ -+#define ltq_port_r32(p, reg) ltq_r32(p->port + reg) -+#define ltq_port_w32(p, val, reg) ltq_w32(val, p->port + reg) -+#define ltq_port_w32_mask(p, clear, set, reg) \ -+ ltq_port_w32(p, (ltq_port_r32(p, reg) & ~(clear)) | (set), reg) -+ -+#define MAX_PORTS 5 -+#define PINS_PER_PORT 32 -+ -+struct falcon_gpio_port { -+ struct gpio_chip gpio_chip; -+ void __iomem *pad; -+ void __iomem *port; -+ unsigned int irq_base; -+ unsigned int chained_irq; -+}; -+ -+static struct falcon_gpio_port ltq_gpio_port[MAX_PORTS]; -+ -+int gpio_to_irq(unsigned int gpio) -+{ -+ return __gpio_to_irq(gpio); -+} -+EXPORT_SYMBOL(gpio_to_irq); -+ -+int ltq_gpio_mux_set(unsigned int pin, unsigned int mux) -+{ -+ int port = pin / 100; -+ int offset = pin % 100; -+ struct falcon_gpio_port *gpio_port; -+ -+ if ((offset >= PINS_PER_PORT) || (port >= MAX_PORTS)) -+ return -EINVAL; -+ -+ gpio_port = <q_gpio_port[port]; -+ ltq_pad_w32(gpio_port, mux & 0x3, LTQ_PADC_MUX(offset)); -+ -+ return 0; -+} -+EXPORT_SYMBOL(ltq_gpio_mux_set); -+ -+int ltq_gpio_request(unsigned int pin, unsigned int mux, -+ unsigned int dir, const char *name) -+{ -+ int port = pin / 100; -+ int offset = pin % 100; -+ -+ if (offset >= PINS_PER_PORT || port >= MAX_PORTS) -+ return -EINVAL; -+ -+ if (gpio_request(pin, name)) { -+ pr_err("failed to setup lantiq gpio: %s\n", name); -+ return -EBUSY; -+ } -+ -+ if (dir) -+ gpio_direction_output(pin, 1); -+ else -+ gpio_direction_input(pin); -+ -+ return ltq_gpio_mux_set(pin, mux); -+} -+EXPORT_SYMBOL(ltq_gpio_request); -+ -+static int -+falcon_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) -+{ -+ ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRCLR); -+ -+ return 0; -+} -+ -+static void -+falcon_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) -+{ -+ if (value) -+ ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTSET); -+ else -+ ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTCLR); -+} -+ -+static int -+falcon_gpio_direction_output(struct gpio_chip *chip, -+ unsigned int offset, int value) -+{ -+ falcon_gpio_set(chip, offset, value); -+ ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRSET); -+ -+ return 0; -+} -+ -+static int -+falcon_gpio_get(struct gpio_chip *chip, unsigned int offset) -+{ -+ if ((ltq_port_r32(ctop(chip), LTQ_GPIO_DIR) >> offset) & 1) -+ return (ltq_port_r32(ctop(chip), LTQ_GPIO_OUT) >> offset) & 1; -+ else -+ return (ltq_port_r32(ctop(chip), LTQ_GPIO_IN) >> offset) & 1; -+} -+ -+static int -+falcon_gpio_request(struct gpio_chip *chip, unsigned offset) -+{ -+ if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) { -+ if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1) -+ return -EBUSY; -+ /* switch on gpio function */ -+ ltq_pad_w32(ctop(chip), 1, LTQ_PADC_MUX(offset)); -+ return 0; -+ } -+ -+ return -ENODEV; -+} -+ -+static void -+falcon_gpio_free(struct gpio_chip *chip, unsigned offset) -+{ -+ if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) { -+ if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1) -+ return; -+ /* switch off gpio function */ -+ ltq_pad_w32(ctop(chip), 0, LTQ_PADC_MUX(offset)); -+ } -+} -+ -+static int -+falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset) -+{ -+ return ctop(chip)->irq_base + offset; -+} -+ -+static void -+falcon_gpio_disable_irq(struct irq_data *d) -+{ -+ unsigned int offset = d->irq - itop(d)->irq_base; -+ -+ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR); -+} -+ -+static void -+falcon_gpio_enable_irq(struct irq_data *d) -+{ -+ unsigned int offset = d->irq - itop(d)->irq_base; -+ -+ if (!ltq_pad_r32(itop(d), LTQ_PADC_MUX(offset)) < 1) -+ /* switch on gpio function */ -+ ltq_pad_w32(itop(d), 1, LTQ_PADC_MUX(offset)); -+ -+ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNRNSET); -+} -+ -+static void -+falcon_gpio_ack_irq(struct irq_data *d) -+{ -+ unsigned int offset = d->irq - itop(d)->irq_base; -+ -+ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR); -+} -+ -+static void -+falcon_gpio_mask_and_ack_irq(struct irq_data *d) -+{ -+ unsigned int offset = d->irq - itop(d)->irq_base; -+ -+ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR); -+ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR); -+} -+ -+static struct irq_chip falcon_gpio_irq_chip; -+static int -+falcon_gpio_irq_type(struct irq_data *d, unsigned int type) -+{ -+ unsigned int offset = d->irq - itop(d)->irq_base; -+ unsigned int mask = 1 << offset; -+ -+ if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE) -+ return 0; -+ -+ if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) { -+ /* level triggered */ -+ ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_IRNCFG); -+ irq_set_chip_and_handler_name(d->irq, -+ &falcon_gpio_irq_chip, handle_level_irq, "mux"); -+ } else { -+ /* edge triggered */ -+ ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_IRNCFG); -+ irq_set_chip_and_handler_name(d->irq, -+ &falcon_gpio_irq_chip, handle_simple_irq, "mux"); -+ } -+ -+ if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { -+ ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0); -+ ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR1); -+ } else { -+ if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) != 0) -+ /* positive logic: rising edge, high level */ -+ ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0); -+ else -+ /* negative logic: falling edge, low level */ -+ ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR0); -+ ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR1); -+ } -+ -+ return gpio_direction_input(itop(d)->gpio_chip.base + offset); -+} -+ -+static void -+falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) -+{ -+ struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc); -+ unsigned long irncr; -+ int offset; -+ -+ /* acknowledge interrupt */ -+ irncr = ltq_port_r32(gpio_port, LTQ_GPIO_IRNCR); -+ ltq_port_w32(gpio_port, irncr, LTQ_GPIO_IRNCR); -+ -+ desc->irq_data.chip->irq_ack(&desc->irq_data); -+ -+ for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio) -+ generic_handle_irq(gpio_port->irq_base + offset); -+} -+ -+static struct irq_chip falcon_gpio_irq_chip = { -+ .name = "gpio_irq_mux", -+ .irq_mask = falcon_gpio_disable_irq, -+ .irq_unmask = falcon_gpio_enable_irq, -+ .irq_ack = falcon_gpio_ack_irq, -+ .irq_mask_ack = falcon_gpio_mask_and_ack_irq, -+ .irq_set_type = falcon_gpio_irq_type, -+}; -+ -+static struct irqaction gpio_cascade = { -+ .handler = no_action, -+ .flags = IRQF_DISABLED, -+ .name = "gpio_cascade", -+}; -+ -+static int -+falcon_gpio_probe(struct platform_device *pdev) -+{ -+ struct falcon_gpio_port *gpio_port; -+ int ret, i; -+ struct resource *gpiores, *padres; -+ int irq; -+ -+ if (pdev->id >= MAX_PORTS) -+ return -ENODEV; -+ -+ gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ padres = platform_get_resource(pdev, IORESOURCE_MEM, 1); -+ irq = platform_get_irq(pdev, 0); -+ if (!gpiores || !padres) -+ return -ENODEV; -+ -+ gpio_port = <q_gpio_port[pdev->id]; -+ gpio_port->gpio_chip.label = "falcon-gpio"; -+ gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input; -+ gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output; -+ gpio_port->gpio_chip.get = falcon_gpio_get; -+ gpio_port->gpio_chip.set = falcon_gpio_set; -+ gpio_port->gpio_chip.request = falcon_gpio_request; -+ gpio_port->gpio_chip.free = falcon_gpio_free; -+ gpio_port->gpio_chip.base = 100 * pdev->id; -+ gpio_port->gpio_chip.ngpio = 32; -+ gpio_port->gpio_chip.dev = &pdev->dev; -+ -+ gpio_port->port = ltq_remap_resource(gpiores); -+ gpio_port->pad = ltq_remap_resource(padres); -+ -+ if (!gpio_port->port || !gpio_port->pad) { -+ dev_err(&pdev->dev, "Could not map io ranges\n"); -+ ret = -ENOMEM; -+ goto err; -+ } -+ -+ if (irq > 0) { -+ /* irq_chip support */ -+ gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq; -+ gpio_port->irq_base = INT_NUM_EXTRA_START + (32 * pdev->id); -+ -+ for (i = 0; i < 32; i++) { -+ irq_set_chip_and_handler_name(gpio_port->irq_base + i, -+ &falcon_gpio_irq_chip, handle_simple_irq, -+ "mux"); -+ irq_set_chip_data(gpio_port->irq_base + i, gpio_port); -+ /* set to negative logic (falling edge, low level) */ -+ ltq_port_w32_mask(gpio_port, 0, 1 << i, -+ LTQ_GPIO_EXINTCR0); -+ } -+ -+ gpio_port->chained_irq = irq; -+ setup_irq(irq, &gpio_cascade); -+ irq_set_handler_data(irq, gpio_port); -+ irq_set_chained_handler(irq, falcon_gpio_irq_handler); -+ } -+ -+ ret = gpiochip_add(&gpio_port->gpio_chip); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n", -+ pdev->id, ret); -+ goto err; -+ } -+ platform_set_drvdata(pdev, gpio_port); -+ return ret; -+ -+err: -+ dev_err(&pdev->dev, "Error in gpio_probe %d, %d\n", pdev->id, ret); -+ if (gpiores) -+ release_resource(gpiores); -+ if (padres) -+ release_resource(padres); -+ -+ if (gpio_port->port) -+ iounmap(gpio_port->port); -+ if (gpio_port->pad) -+ iounmap(gpio_port->pad); -+ return ret; -+} -+ -+static struct platform_driver falcon_gpio_driver = { -+ .probe = falcon_gpio_probe, -+ .driver = { -+ .name = "falcon_gpio", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+int __init -+falcon_gpio_init(void) -+{ -+ int ret; -+ -+ pr_info("FALC(tm) ON GPIO Driver, (C) 2011 Lantiq Deutschland Gmbh\n"); -+ ret = platform_driver_register(&falcon_gpio_driver); -+ if (ret) -+ pr_err("falcon_gpio: Error registering platform driver!"); -+ return ret; -+} -+ -+postcore_initcall(falcon_gpio_init); diff --git a/target/linux/lantiq/patches-3.3/0006-mtd-support.patch b/target/linux/lantiq/patches-3.3/0006-mtd-support.patch new file mode 100644 index 0000000000..a783a6d8a4 --- /dev/null +++ b/target/linux/lantiq/patches-3.3/0006-mtd-support.patch @@ -0,0 +1,98 @@ +From 4bd56362cd1780530d981e2e9f3793c4d7da7e02 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 09:53:27 +0200 +Subject: [PATCH 06/25] mtd support + +--- + drivers/mtd/devices/m25p80.c | 1 + + drivers/mtd/maps/lantiq-flash.c | 22 +++------------------- + drivers/mtd/nand/plat_nand.c | 1 + + include/linux/mtd/nand.h | 1 + + 4 files changed, 6 insertions(+), 19 deletions(-) + +diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c +index b06f46c..33bfd9b 100644 +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -684,6 +684,7 @@ static const struct spi_device_id m25p_ids[] = { + { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, + + /* Macronix */ ++ { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 8, SECT_4K) }, + { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, + { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, + { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) }, +diff --git a/drivers/mtd/maps/lantiq-flash.c b/drivers/mtd/maps/lantiq-flash.c +index cf7a3cd..ccc6954 100644 +--- a/drivers/mtd/maps/lantiq-flash.c ++++ b/drivers/mtd/maps/lantiq-flash.c +@@ -108,7 +108,7 @@ ltq_copy_to(struct map_info *map, unsigned long to, + spin_unlock_irqrestore(&ebu_lock, flags); + } + +-static int __init ++static int __devinit + ltq_mtd_probe(struct platform_device *pdev) + { + struct physmap_flash_data *ltq_mtd_data = dev_get_platdata(&pdev->dev); +@@ -204,6 +204,7 @@ ltq_mtd_remove(struct platform_device *pdev) + } + + static struct platform_driver ltq_mtd_driver = { ++ .probe = ltq_mtd_probe, + .remove = __devexit_p(ltq_mtd_remove), + .driver = { + .name = "ltq_nor", +@@ -211,24 +212,7 @@ static struct platform_driver ltq_mtd_driver = { + }, + }; + +-static int __init +-init_ltq_mtd(void) +-{ +- int ret = platform_driver_probe(<q_mtd_driver, ltq_mtd_probe); +- +- if (ret) +- pr_err("ltq_nor: error registering platform driver"); +- return ret; +-} +- +-static void __exit +-exit_ltq_mtd(void) +-{ +- platform_driver_unregister(<q_mtd_driver); +-} +- +-module_init(init_ltq_mtd); +-module_exit(exit_ltq_mtd); ++module_platform_driver(ltq_mtd_driver); + + MODULE_LICENSE("GPL"); + MODULE_AUTHOR("John Crispin "); +diff --git a/drivers/mtd/nand/plat_nand.c b/drivers/mtd/nand/plat_nand.c +index 10f142d..4cb118b 100644 +--- a/drivers/mtd/nand/plat_nand.c ++++ b/drivers/mtd/nand/plat_nand.c +@@ -75,6 +75,7 @@ static int __devinit plat_nand_probe(struct platform_device *pdev) + data->chip.select_chip = pdata->ctrl.select_chip; + data->chip.write_buf = pdata->ctrl.write_buf; + data->chip.read_buf = pdata->ctrl.read_buf; ++ data->chip.read_byte = pdata->ctrl.read_byte; + data->chip.chip_delay = pdata->chip.chip_delay; + data->chip.options |= pdata->chip.options; + data->chip.bbt_options |= pdata->chip.bbt_options; +diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h +index c2761fd..5e44cda 100644 +--- a/include/linux/mtd/nand.h ++++ b/include/linux/mtd/nand.h +@@ -652,6 +652,7 @@ struct platform_nand_ctrl { + void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); + void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); + void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); ++ unsigned char (*read_byte)(struct mtd_info *mtd); + void *priv; + }; + +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0007-MIPS-lantiq-add-support-for-the-EASY98000-evaluation.patch b/target/linux/lantiq/patches-3.3/0007-MIPS-lantiq-add-support-for-the-EASY98000-evaluation.patch deleted file mode 100644 index fb20dc73cc..0000000000 --- a/target/linux/lantiq/patches-3.3/0007-MIPS-lantiq-add-support-for-the-EASY98000-evaluation.patch +++ /dev/null @@ -1,165 +0,0 @@ -From fd86db6e998953a8574cfc2f1112343f9cddaccf Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 11 Aug 2011 14:09:35 +0200 -Subject: [PATCH 07/70] MIPS: lantiq: add support for the EASY98000 evaluation - board - -This patch adds the machine code for the EASY9800 evaluation board. - -Signed-off-by: Thomas Langer -Signed-off-by: John Crispin ---- - arch/mips/lantiq/falcon/Kconfig | 11 +++ - arch/mips/lantiq/falcon/Makefile | 1 + - arch/mips/lantiq/falcon/mach-easy98000.c | 110 ++++++++++++++++++++++++++++++ - arch/mips/lantiq/machtypes.h | 5 ++ - 4 files changed, 127 insertions(+), 0 deletions(-) - create mode 100644 arch/mips/lantiq/falcon/Kconfig - create mode 100644 arch/mips/lantiq/falcon/mach-easy98000.c - ---- /dev/null -+++ b/arch/mips/lantiq/falcon/Kconfig -@@ -0,0 +1,11 @@ -+if SOC_FALCON -+ -+menu "MIPS Machine" -+ -+config LANTIQ_MACH_EASY98000 -+ bool "Easy98000" -+ default y -+ -+endmenu -+ -+endif ---- a/arch/mips/lantiq/falcon/Makefile -+++ b/arch/mips/lantiq/falcon/Makefile -@@ -1 +1,2 @@ - obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o -+obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o ---- /dev/null -+++ b/arch/mips/lantiq/falcon/mach-easy98000.c -@@ -0,0 +1,110 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2011 Thomas Langer -+ * Copyright (C) 2011 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "../machtypes.h" -+ -+#include "devices.h" -+ -+static struct mtd_partition easy98000_nor_partitions[] = { -+ { -+ .name = "uboot", -+ .offset = 0x0, -+ .size = 0x40000, -+ }, -+ { -+ .name = "uboot_env", -+ .offset = 0x40000, -+ .size = 0x40000, /* 2 sectors for redundant env. */ -+ }, -+ { -+ .name = "linux", -+ .offset = 0x80000, -+ .size = 0xF80000, /* map only 16 MiB */ -+ }, -+}; -+ -+struct physmap_flash_data easy98000_nor_flash_data = { -+ .nr_parts = ARRAY_SIZE(easy98000_nor_partitions), -+ .parts = easy98000_nor_partitions, -+}; -+ -+/* setup gpio based spi bus/device for access to the eeprom on the board */ -+#define SPI_GPIO_MRST 102 -+#define SPI_GPIO_MTSR 103 -+#define SPI_GPIO_CLK 104 -+#define SPI_GPIO_CS0 105 -+#define SPI_GPIO_CS1 106 -+#define SPI_GPIO_BUS_NUM 1 -+ -+static struct spi_gpio_platform_data easy98000_spi_gpio_data = { -+ .sck = SPI_GPIO_CLK, -+ .mosi = SPI_GPIO_MTSR, -+ .miso = SPI_GPIO_MRST, -+ .num_chipselect = 2, -+}; -+ -+static struct platform_device easy98000_spi_gpio_device = { -+ .name = "spi_gpio", -+ .id = SPI_GPIO_BUS_NUM, -+ .dev.platform_data = &easy98000_spi_gpio_data, -+}; -+ -+static struct spi_eeprom at25160n = { -+ .byte_len = 16 * 1024 / 8, -+ .name = "at25160n", -+ .page_size = 32, -+ .flags = EE_ADDR2, -+}; -+ -+static struct spi_board_info easy98000_spi_gpio_devices __initdata = { -+ .modalias = "at25", -+ .bus_num = SPI_GPIO_BUS_NUM, -+ .max_speed_hz = 1000 * 1000, -+ .mode = SPI_MODE_3, -+ .chip_select = 1, -+ .controller_data = (void *) SPI_GPIO_CS1, -+ .platform_data = &at25160n, -+}; -+ -+static void __init -+easy98000_init_common(void) -+{ -+ spi_register_board_info(&easy98000_spi_gpio_devices, 1); -+ platform_device_register(&easy98000_spi_gpio_device); -+} -+ -+static void __init -+easy98000_init(void) -+{ -+ easy98000_init_common(); -+ ltq_register_nor(&easy98000_nor_flash_data); -+} -+ -+static void __init -+easy98000nand_init(void) -+{ -+ easy98000_init_common(); -+ falcon_register_nand(); -+} -+ -+MIPS_MACHINE(LANTIQ_MACH_EASY98000, -+ "EASY98000", -+ "EASY98000 Eval Board", -+ easy98000_init); -+ -+MIPS_MACHINE(LANTIQ_MACH_EASY98000NAND, -+ "EASY98000NAND", -+ "EASY98000 Eval Board (NAND Flash)", -+ easy98000nand_init); ---- a/arch/mips/lantiq/machtypes.h -+++ b/arch/mips/lantiq/machtypes.h -@@ -15,6 +15,11 @@ enum lantiq_mach_type { - LTQ_MACH_GENERIC = 0, - LTQ_MACH_EASY50712, /* Danube evaluation board */ - LTQ_MACH_EASY50601, /* Amazon SE evaluation board */ -+ -+ /* FALCON */ -+ LANTIQ_MACH_EASY98000, /* Falcon Eval Board, NOR Flash */ -+ LANTIQ_MACH_EASY98000SF, /* Falcon Eval Board, Serial Flash */ -+ LANTIQ_MACH_EASY98000NAND, /* Falcon Eval Board, NAND Flash */ - }; - - #endif diff --git a/target/linux/lantiq/patches-3.3/0007-usb-support.patch b/target/linux/lantiq/patches-3.3/0007-usb-support.patch new file mode 100644 index 0000000000..88217b4533 --- /dev/null +++ b/target/linux/lantiq/patches-3.3/0007-usb-support.patch @@ -0,0 +1,71 @@ +From a2089c84bb5c8ceab9a2ede7a87a97e37c308f8e Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 09:53:45 +0200 +Subject: [PATCH 07/25] usb support + +--- + drivers/usb/Kconfig | 4 ++++ + drivers/usb/Makefile | 4 ++++ + drivers/usb/core/hub.c | 4 ++-- + 3 files changed, 10 insertions(+), 2 deletions(-) + +diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig +index 75823a1..f69cc4a 100644 +--- a/drivers/usb/Kconfig ++++ b/drivers/usb/Kconfig +@@ -130,6 +130,8 @@ source "drivers/usb/wusbcore/Kconfig" + + source "drivers/usb/host/Kconfig" + ++source "drivers/usb/dwc_otg/Kconfig" ++ + source "drivers/usb/musb/Kconfig" + + source "drivers/usb/renesas_usbhs/Kconfig" +@@ -182,4 +184,6 @@ source "drivers/usb/gadget/Kconfig" + + source "drivers/usb/otg/Kconfig" + ++source "drivers/usb/ifxhcd/Kconfig" ++ + endif # USB_SUPPORT +diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile +index 53a7bc0..7068e99 100644 +--- a/drivers/usb/Makefile ++++ b/drivers/usb/Makefile +@@ -32,6 +32,8 @@ obj-$(CONFIG_USB_C67X00_HCD) += c67x00/ + + obj-$(CONFIG_USB_WUSB) += wusbcore/ + ++obj-$(CONFIG_DWC_OTG) += dwc_otg/ ++ + obj-$(CONFIG_USB_ACM) += class/ + obj-$(CONFIG_USB_PRINTER) += class/ + obj-$(CONFIG_USB_WDM) += class/ +@@ -56,3 +58,5 @@ obj-$(CONFIG_USB_RENESAS_USBHS) += renesas_usbhs/ + obj-$(CONFIG_USB_GADGET) += gadget/ + + obj-$(CONFIG_USB_COMMON) += usb-common.o ++ ++obj-$(CONFIG_USB_HOST_IFX) += ifxhcd/ +diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c +index ce5e147..463da23 100644 +--- a/drivers/usb/core/hub.c ++++ b/drivers/usb/core/hub.c +@@ -2939,11 +2939,11 @@ hub_port_init (struct usb_hub *hub, struct usb_device *udev, int port1, + udev->ttport = hdev->ttport; + } else if (udev->speed != USB_SPEED_HIGH + && hdev->speed == USB_SPEED_HIGH) { +- if (!hub->tt.hub) { ++/* if (!hub->tt.hub) { + dev_err(&udev->dev, "parent hub has no TT\n"); + retval = -EINVAL; + goto fail; +- } ++ }*/ + udev->tt = &hub->tt; + udev->ttport = port1; + } +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0008-MIPS-lantiq-fix-early-printk.patch b/target/linux/lantiq/patches-3.3/0008-MIPS-lantiq-fix-early-printk.patch deleted file mode 100644 index d0d74733e2..0000000000 --- a/target/linux/lantiq/patches-3.3/0008-MIPS-lantiq-fix-early-printk.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 4e06715641d992bb9d94e0b37d22241b9ec074c6 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sat, 20 Aug 2011 18:55:13 +0200 -Subject: [PATCH 08/70] MIPS: lantiq: fix early printk - -The code was using a 32bit write operations in the early_printk code. This -resulted in 3 zero bytes also being written to the serial port. This patch -changes the memory access to 8bit. - -Signed-off-by: Thomas Langer -Signed-off-by: John Crispin ---- - .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 6 ++++++ - arch/mips/lantiq/early_printk.c | 14 ++++++++------ - 2 files changed, 14 insertions(+), 6 deletions(-) - ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -@@ -34,6 +34,12 @@ - #define LTQ_ASC1_BASE_ADDR 0x1E100C00 - #define LTQ_ASC_SIZE 0x400 - -+/* -+ * during early_printk no ioremap is possible -+ * lets use KSEG1 instead -+ */ -+#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR) -+ - /* RCU - reset control unit */ - #define LTQ_RCU_BASE_ADDR 0x1F203000 - #define LTQ_RCU_SIZE 0x1000 ---- a/arch/mips/lantiq/early_printk.c -+++ b/arch/mips/lantiq/early_printk.c -@@ -12,11 +12,13 @@ - #include - #include - --/* no ioremap possible at this early stage, lets use KSEG1 instead */ --#define LTQ_ASC_BASE KSEG1ADDR(LTQ_ASC1_BASE_ADDR) - #define ASC_BUF 1024 --#define LTQ_ASC_FSTAT ((u32 *)(LTQ_ASC_BASE + 0x0048)) --#define LTQ_ASC_TBUF ((u32 *)(LTQ_ASC_BASE + 0x0020)) -+#define LTQ_ASC_FSTAT ((u32 *)(LTQ_EARLY_ASC + 0x0048)) -+#ifdef __BIG_ENDIAN -+#define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020 + 3)) -+#else -+#define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020)) -+#endif - #define TXMASK 0x3F00 - #define TXOFFSET 8 - -@@ -27,7 +29,7 @@ void prom_putchar(char c) - local_irq_save(flags); - do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET); - if (c == '\n') -- ltq_w32('\r', LTQ_ASC_TBUF); -- ltq_w32(c, LTQ_ASC_TBUF); -+ ltq_w8('\r', LTQ_ASC_TBUF); -+ ltq_w8(c, LTQ_ASC_TBUF); - local_irq_restore(flags); - } diff --git a/target/linux/lantiq/patches-3.3/0008-spi-support.patch b/target/linux/lantiq/patches-3.3/0008-spi-support.patch new file mode 100644 index 0000000000..c988d1fe77 --- /dev/null +++ b/target/linux/lantiq/patches-3.3/0008-spi-support.patch @@ -0,0 +1,74 @@ +From 8fd28bca39e31be5a05cb9cf89335a207e8b031f Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 09:53:54 +0200 +Subject: [PATCH 08/25] spi support + +--- + drivers/spi/Kconfig | 17 +++++++++++++++++ + drivers/spi/Makefile | 3 +++ + 2 files changed, 20 insertions(+), 0 deletions(-) + +diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig +index f62424f..7e8146e 100644 +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -188,6 +188,10 @@ config SPI_MPC52xx + This drivers supports the MPC52xx SPI controller in master SPI + mode. + ++config SPI_FALCON ++ tristate "Falcon SPI controller support" ++ depends on SOC_FALCON ++ + config SPI_MPC52xx_PSC + tristate "Freescale MPC52xx PSC SPI controller" + depends on PPC_MPC52xx && EXPERIMENTAL +@@ -362,6 +366,11 @@ config SPI_TOPCLIFF_PCH + This driver also supports the ML7213/ML7223/ML7831, a companion chip + for the Atom E6xx series and compatible with the Intel EG20T PCH. + ++config SPI_SVIP ++ tristate "SVIP SPI controller" ++ depends on SOC_SVIP ++ default y ++ + config SPI_TXX9 + tristate "Toshiba TXx9 SPI controller" + depends on GENERIC_GPIO && CPU_TX49XX +@@ -387,6 +396,14 @@ config SPI_NUC900 + help + SPI driver for Nuvoton NUC900 series ARM SoCs + ++config SPI_XWAY ++ tristate "Lantiq XWAY SPI controller" ++ depends on LANTIQ && SOC_TYPE_XWAY ++ select SPI_BITBANG ++ help ++ This driver supports the Lantiq SoC SPI controller in master ++ mode. ++ + # + # Add new SPI master controllers in alphabetical order above this line + # +diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile +index 1514c1d..71e7655 100644 +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -25,6 +25,7 @@ obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o + obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o + spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o + obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o ++obj-$(CONFIG_SPI_FALCON) += spi-falcon.o + obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-lib.o + obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o + obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o +@@ -59,4 +60,6 @@ obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x0.o + obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o + obj-$(CONFIG_SPI_TXX9) += spi-txx9.o + obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o ++obj-$(CONFIG_SPI_XWAY) += spi-xway.o ++obj-$(CONFIG_SPI_SVIP) += spi_svip.o + +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0009-MIPS-lantiq-fix-cmdline-parsing.patch b/target/linux/lantiq/patches-3.3/0009-MIPS-lantiq-fix-cmdline-parsing.patch deleted file mode 100644 index acd0988c23..0000000000 --- a/target/linux/lantiq/patches-3.3/0009-MIPS-lantiq-fix-cmdline-parsing.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 3ea88c1089b88b4860919a9cdea0cc5da4d09e2c Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 12 Aug 2011 16:27:38 +0200 -Subject: [PATCH 09/70] MIPS: lantiq: fix cmdline parsing - -The code tested if the KSEG1 mapped address of argv was != 0. We need to use -CPHYSADDR instead to make the conditional actually work. - -Signed-off-by: Thomas Langer -Signed-off-by: John Crispin ---- - arch/mips/lantiq/prom.c | 6 ++++-- - 1 files changed, 4 insertions(+), 2 deletions(-) - ---- a/arch/mips/lantiq/prom.c -+++ b/arch/mips/lantiq/prom.c -@@ -49,10 +49,12 @@ static void __init prom_init_cmdline(voi - char **argv = (char **) KSEG1ADDR(fw_arg1); - int i; - -+ arcs_cmdline[0] = '\0'; -+ - for (i = 0; i < argc; i++) { -- char *p = (char *) KSEG1ADDR(argv[i]); -+ char *p = (char *) KSEG1ADDR(argv[i]); - -- if (p && *p) { -+ if (CPHYSADDR(p) && *p) { - strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); - strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); - } diff --git a/target/linux/lantiq/patches-3.3/0009-ethernet-support.patch b/target/linux/lantiq/patches-3.3/0009-ethernet-support.patch new file mode 100644 index 0000000000..9c8a1d82c1 --- /dev/null +++ b/target/linux/lantiq/patches-3.3/0009-ethernet-support.patch @@ -0,0 +1,785 @@ +From a19b113fc05b46605f9ff57c2d15b047d6c392aa Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 09:54:02 +0200 +Subject: [PATCH 09/25] ethernet support + +--- + drivers/net/ethernet/Kconfig | 18 ++ + drivers/net/ethernet/Makefile | 3 + + drivers/net/ethernet/lantiq_etop.c | 419 ++++++++++++++++++++++++++---------- + net/ipv4/Kconfig | 7 + + net/ipv4/Makefile | 1 + + 5 files changed, 332 insertions(+), 116 deletions(-) + +diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig +index 3474a61..1d91eb6 100644 +--- a/drivers/net/ethernet/Kconfig ++++ b/drivers/net/ethernet/Kconfig +@@ -85,6 +85,24 @@ config LANTIQ_ETOP + ---help--- + Support for the MII0 inside the Lantiq SoC + ++config LANTIQ_VRX200 ++ tristate "Lantiq SoC vrx200 driver" ++ depends on SOC_TYPE_XWAY ++ ---help--- ++ Support for the MII0 inside the Lantiq SoC ++ ++config LANTIQ_SVIP_ETH ++ default y ++ tristate "Lantiq SoC SVIP Ethernet driver" ++ depends on SOC_SVIP ++ help ++ Support for the MII0 inside the Lantiq SVIP SoC ++ ++config LANTIQ_SVIP_VIRTUAL_ETH ++ default y ++ tristate "Lantiq SoC SVIP Virtual Ethernet driver" ++ depends on SOC_SVIP ++ + source "drivers/net/ethernet/marvell/Kconfig" + source "drivers/net/ethernet/mellanox/Kconfig" + source "drivers/net/ethernet/micrel/Kconfig" +diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile +index 08d5f03..c8fb1b3 100644 +--- a/drivers/net/ethernet/Makefile ++++ b/drivers/net/ethernet/Makefile +@@ -36,6 +36,9 @@ obj-$(CONFIG_IP1000) += icplus/ + obj-$(CONFIG_JME) += jme.o + obj-$(CONFIG_KORINA) += korina.o + obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o ++obj-$(CONFIG_LANTIQ_VRX200) += lantiq_vrx200.o ++obj-$(CONFIG_LANTIQ_SVIP_ETH) += svip_eth.o ++obj-$(CONFIG_LANTIQ_SVIP_VIRTUAL_ETH) += svip_virtual_eth.o + obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/ + obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/ + obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/ +diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c +index 85e2c6c..97ddb09 100644 +--- a/drivers/net/ethernet/lantiq_etop.c ++++ b/drivers/net/ethernet/lantiq_etop.c +@@ -36,6 +36,7 @@ + #include + #include + #include ++#include + + #include + +@@ -71,25 +72,55 @@ + #define ETOP_MII_REVERSE 0xe + #define ETOP_PLEN_UNDER 0x40 + #define ETOP_CGEN 0x800 +- +-/* use 2 static channels for TX/RX */ +-#define LTQ_ETOP_TX_CHANNEL 1 +-#define LTQ_ETOP_RX_CHANNEL 6 +-#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) +-#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) ++#define ETOP_CFG_MII0 0x01 ++ ++#define LTQ_GBIT_MDIO_CTL 0xCC ++#define LTQ_GBIT_MDIO_DATA 0xd0 ++#define LTQ_GBIT_GCTL0 0x68 ++#define LTQ_GBIT_PMAC_HD_CTL 0x8c ++#define LTQ_GBIT_P0_CTL 0x4 ++#define LTQ_GBIT_PMAC_RX_IPG 0xa8 ++ ++#define PMAC_HD_CTL_AS (1 << 19) ++#define PMAC_HD_CTL_RXSH (1 << 22) ++ ++/* Switch Enable (0=disable, 1=enable) */ ++#define GCTL0_SE 0x80000000 ++/* Disable MDIO auto polling (0=disable, 1=enable) */ ++#define PX_CTL_DMDIO 0x00400000 ++ ++/* register information for the gbit's MDIO bus */ ++#define MDIO_XR9_REQUEST 0x00008000 ++#define MDIO_XR9_READ 0x00000800 ++#define MDIO_XR9_WRITE 0x00000400 ++#define MDIO_XR9_REG_MASK 0x1f ++#define MDIO_XR9_ADDR_MASK 0x1f ++#define MDIO_XR9_RD_MASK 0xffff ++#define MDIO_XR9_REG_OFFSET 0 ++#define MDIO_XR9_ADDR_OFFSET 5 ++#define MDIO_XR9_WR_OFFSET 16 ++ ++/* the newer xway socks have a embedded 3/7 port gbit multiplexer */ ++#define ltq_has_gbit() (ltq_is_ar9() || ltq_is_vr9()) + + #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) + #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) + #define ltq_etop_w32_mask(x, y, z) \ + ltq_w32_mask(x, y, ltq_etop_membase + (z)) + ++#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x)) ++#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y)) ++#define ltq_gbit_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, ltq_gbit_membase + (z)) ++ + #define DRV_VERSION "1.0" + + static void __iomem *ltq_etop_membase; ++static void __iomem *ltq_gbit_membase; + + struct ltq_etop_chan { +- int idx; + int tx_free; ++ int irq; + struct net_device *netdev; + struct napi_struct napi; + struct ltq_dma_channel dma; +@@ -105,12 +136,20 @@ struct ltq_etop_priv { + struct mii_bus *mii_bus; + struct phy_device *phydev; + +- struct ltq_etop_chan ch[MAX_DMA_CHAN]; +- int tx_free[MAX_DMA_CHAN >> 1]; ++ struct ltq_etop_chan txch; ++ struct ltq_etop_chan rxch; + + spinlock_t lock; ++ ++ struct clk *clk_ppe; ++ struct clk *clk_switch; ++ struct clk *clk_ephy; ++ struct clk *clk_ephycgu; + }; + ++static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, ++ int phy_reg, u16 phy_data); ++ + static int + ltq_etop_alloc_skb(struct ltq_etop_chan *ch) + { +@@ -159,8 +198,10 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget) + { + struct ltq_etop_chan *ch = container_of(napi, + struct ltq_etop_chan, napi); ++ struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + int rx = 0; + int complete = 0; ++ unsigned long flags; + + while ((rx < budget) && !complete) { + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; +@@ -174,7 +215,9 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget) + } + if (complete || !rx) { + napi_complete(&ch->napi); ++ spin_lock_irqsave(&priv->lock, flags); + ltq_dma_ack_irq(&ch->dma); ++ spin_unlock_irqrestore(&priv->lock, flags); + } + return rx; + } +@@ -186,7 +229,7 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget) + container_of(napi, struct ltq_etop_chan, napi); + struct ltq_etop_priv *priv = netdev_priv(ch->netdev); + struct netdev_queue *txq = +- netdev_get_tx_queue(ch->netdev, ch->idx >> 1); ++ netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1); + unsigned long flags; + + spin_lock_irqsave(&priv->lock, flags); +@@ -204,7 +247,9 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget) + if (netif_tx_queue_stopped(txq)) + netif_tx_start_queue(txq); + napi_complete(&ch->napi); ++ spin_lock_irqsave(&priv->lock, flags); + ltq_dma_ack_irq(&ch->dma); ++ spin_unlock_irqrestore(&priv->lock, flags); + return 1; + } + +@@ -212,9 +257,10 @@ static irqreturn_t + ltq_etop_dma_irq(int irq, void *_priv) + { + struct ltq_etop_priv *priv = _priv; +- int ch = irq - LTQ_DMA_CH0_INT; +- +- napi_schedule(&priv->ch[ch].napi); ++ if (irq == priv->txch.dma.irq) ++ napi_schedule(&priv->txch.napi); ++ else ++ napi_schedule(&priv->rxch.napi); + return IRQ_HANDLED; + } + +@@ -226,7 +272,7 @@ ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch) + ltq_dma_free(&ch->dma); + if (ch->dma.irq) + free_irq(ch->dma.irq, priv); +- if (IS_RX(ch->idx)) { ++ if (ch == &priv->txch) { + int desc; + for (desc = 0; desc < LTQ_DESC_NUM; desc++) + dev_kfree_skb_any(ch->skb[ch->dma.desc]); +@@ -237,23 +283,56 @@ static void + ltq_etop_hw_exit(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; + +- ltq_pmu_disable(PMU_PPE); +- for (i = 0; i < MAX_DMA_CHAN; i++) +- if (IS_TX(i) || IS_RX(i)) +- ltq_etop_free_channel(dev, &priv->ch[i]); ++ clk_disable(priv->clk_ppe); ++ ++ if (ltq_has_gbit()) ++ clk_disable(priv->clk_switch); ++ ++ if (ltq_is_ase()) { ++ clk_disable(priv->clk_ephy); ++ clk_disable(priv->clk_ephycgu); ++ } ++ ++ ltq_etop_free_channel(dev, &priv->txch); ++ ltq_etop_free_channel(dev, &priv->rxch); ++} ++ ++static void ++ltq_etop_gbit_init(struct net_device *dev) ++{ ++ struct ltq_etop_priv *priv = netdev_priv(dev); ++ ++ clk_enable(priv->clk_switch); ++ ++ ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); ++ /** Disable MDIO auto polling mode */ ++ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL); ++ /* set 1522 packet size */ ++ ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0); ++ /* disable pmac & dmac headers */ ++ ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0, ++ LTQ_GBIT_PMAC_HD_CTL); ++ /* Due to traffic halt when burst length 8, ++ replace default IPG value with 0x3B */ ++ ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG); + } + + static int + ltq_etop_hw_init(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; ++ unsigned int mii_mode = priv->pldata->mii_mode; + +- ltq_pmu_enable(PMU_PPE); ++ clk_enable(priv->clk_ppe); + +- switch (priv->pldata->mii_mode) { ++ if (ltq_has_gbit()) { ++ ltq_etop_gbit_init(dev); ++ /* force the etops link to the gbit to MII */ ++ mii_mode = PHY_INTERFACE_MODE_MII; ++ } ++ ++ switch (mii_mode) { + case PHY_INTERFACE_MODE_RMII: + ltq_etop_w32_mask(ETOP_MII_MASK, + ETOP_MII_REVERSE, LTQ_ETOP_CFG); +@@ -265,6 +344,18 @@ ltq_etop_hw_init(struct net_device *dev) + break; + + default: ++ if (ltq_is_ase()) { ++ clk_enable(priv->clk_ephy); ++ /* disable external MII */ ++ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG); ++ /* enable clock for internal PHY */ ++ clk_enable(priv->clk_ephycgu); ++ /* we need to write this magic to the internal phy to ++ make it work */ ++ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020); ++ pr_info("Selected EPHY mode\n"); ++ break; ++ } + netdev_err(dev, "unknown mii mode %d\n", + priv->pldata->mii_mode); + return -ENOTSUPP; +@@ -273,31 +364,51 @@ ltq_etop_hw_init(struct net_device *dev) + /* enable crc generation */ + ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); + ++ return 0; ++} ++ ++static int ++ltq_etop_dma_init(struct net_device *dev) ++{ ++ struct ltq_etop_priv *priv = netdev_priv(dev); ++ int tx = 1; ++ int rx = ((ltq_is_ase()) ? (5) : \ ++ ((ltq_is_ar9()) ? (0) : (6))); ++ int tx_irq = LTQ_DMA_ETOP + tx; ++ int rx_irq = LTQ_DMA_ETOP + rx; ++ int err; ++ + ltq_dma_init_port(DMA_PORT_ETOP); + +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- int irq = LTQ_DMA_CH0_INT + i; +- struct ltq_etop_chan *ch = &priv->ch[i]; +- +- ch->idx = ch->dma.nr = i; +- +- if (IS_TX(i)) { +- ltq_dma_alloc_tx(&ch->dma); +- request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, +- "etop_tx", priv); +- } else if (IS_RX(i)) { +- ltq_dma_alloc_rx(&ch->dma); +- for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; +- ch->dma.desc++) +- if (ltq_etop_alloc_skb(ch)) +- return -ENOMEM; +- ch->dma.desc = 0; +- request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, +- "etop_rx", priv); ++ priv->txch.dma.nr = tx; ++ ltq_dma_alloc_tx(&priv->txch.dma); ++ err = request_irq(tx_irq, ltq_etop_dma_irq, IRQF_DISABLED, ++ "eth_tx", priv); ++ if (err) { ++ netdev_err(dev, "failed to allocate tx irq\n"); ++ goto err_out; ++ } ++ priv->txch.dma.irq = tx_irq; ++ ++ priv->rxch.dma.nr = rx; ++ ltq_dma_alloc_rx(&priv->rxch.dma); ++ for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM; ++ priv->rxch.dma.desc++) { ++ if (ltq_etop_alloc_skb(&priv->rxch)) { ++ netdev_err(dev, "failed to allocate skbs\n"); ++ err = -ENOMEM; ++ goto err_out; + } +- ch->dma.irq = irq; + } +- return 0; ++ priv->rxch.dma.desc = 0; ++ err = request_irq(rx_irq, ltq_etop_dma_irq, IRQF_DISABLED, ++ "eth_rx", priv); ++ if (err) ++ netdev_err(dev, "failed to allocate rx irq\n"); ++ else ++ priv->rxch.dma.irq = rx_irq; ++err_out: ++ return err; + } + + static void +@@ -313,7 +424,10 @@ ltq_etop_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) + { + struct ltq_etop_priv *priv = netdev_priv(dev); + +- return phy_ethtool_gset(priv->phydev, cmd); ++ if (priv->phydev) ++ return phy_ethtool_gset(priv->phydev, cmd); ++ else ++ return 0; + } + + static int +@@ -321,7 +435,10 @@ ltq_etop_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) + { + struct ltq_etop_priv *priv = netdev_priv(dev); + +- return phy_ethtool_sset(priv->phydev, cmd); ++ if (priv->phydev) ++ return phy_ethtool_sset(priv->phydev, cmd); ++ else ++ return 0; + } + + static int +@@ -329,7 +446,10 @@ ltq_etop_nway_reset(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); + +- return phy_start_aneg(priv->phydev); ++ if (priv->phydev) ++ return phy_start_aneg(priv->phydev); ++ else ++ return 0; + } + + static const struct ethtool_ops ltq_etop_ethtool_ops = { +@@ -340,6 +460,39 @@ static const struct ethtool_ops ltq_etop_ethtool_ops = { + }; + + static int ++ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr, ++ int phy_reg, u16 phy_data) ++{ ++ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE | ++ (phy_data << MDIO_XR9_WR_OFFSET) | ++ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | ++ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); ++ ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ return 0; ++} ++ ++static int ++ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg) ++{ ++ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ | ++ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | ++ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); ++ ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK; ++ return val; ++} ++ ++static int + ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) + { + u32 val = MDIO_REQUEST | +@@ -380,14 +533,11 @@ ltq_etop_mdio_probe(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); + struct phy_device *phydev = NULL; +- int phy_addr; + +- for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { +- if (priv->mii_bus->phy_map[phy_addr]) { +- phydev = priv->mii_bus->phy_map[phy_addr]; +- break; +- } +- } ++ if (ltq_is_ase()) ++ phydev = priv->mii_bus->phy_map[8]; ++ else ++ phydev = priv->mii_bus->phy_map[0]; + + if (!phydev) { + netdev_err(dev, "no PHY found\n"); +@@ -409,6 +559,9 @@ ltq_etop_mdio_probe(struct net_device *dev) + | SUPPORTED_Autoneg + | SUPPORTED_MII + | SUPPORTED_TP); ++ if (ltq_has_gbit()) ++ phydev->supported &= SUPPORTED_1000baseT_Half ++ | SUPPORTED_1000baseT_Full; + + phydev->advertising = phydev->supported; + priv->phydev = phydev; +@@ -434,8 +587,13 @@ ltq_etop_mdio_init(struct net_device *dev) + } + + priv->mii_bus->priv = dev; +- priv->mii_bus->read = ltq_etop_mdio_rd; +- priv->mii_bus->write = ltq_etop_mdio_wr; ++ if (ltq_has_gbit()) { ++ priv->mii_bus->read = ltq_etop_mdio_rd_xr9; ++ priv->mii_bus->write = ltq_etop_mdio_wr_xr9; ++ } else { ++ priv->mii_bus->read = ltq_etop_mdio_rd; ++ priv->mii_bus->write = ltq_etop_mdio_wr; ++ } + priv->mii_bus->name = "ltq_mii"; + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", + priv->pdev->name, priv->pdev->id); +@@ -484,17 +642,19 @@ static int + ltq_etop_open(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; ++ unsigned long flags; + +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- struct ltq_etop_chan *ch = &priv->ch[i]; ++ napi_enable(&priv->txch.napi); ++ napi_enable(&priv->rxch.napi); ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ ltq_dma_open(&priv->txch.dma); ++ ltq_dma_open(&priv->rxch.dma); ++ spin_unlock_irqrestore(&priv->lock, flags); ++ ++ if (priv->phydev) ++ phy_start(priv->phydev); + +- if (!IS_TX(i) && (!IS_RX(i))) +- continue; +- ltq_dma_open(&ch->dma); +- napi_enable(&ch->napi); +- } +- phy_start(priv->phydev); + netif_tx_start_all_queues(dev); + return 0; + } +@@ -503,18 +663,19 @@ static int + ltq_etop_stop(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); +- int i; ++ unsigned long flags; + + netif_tx_stop_all_queues(dev); +- phy_stop(priv->phydev); +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- struct ltq_etop_chan *ch = &priv->ch[i]; ++ if (priv->phydev) ++ phy_stop(priv->phydev); ++ napi_disable(&priv->txch.napi); ++ napi_disable(&priv->rxch.napi); ++ ++ spin_lock_irqsave(&priv->lock, flags); ++ ltq_dma_close(&priv->txch.dma); ++ ltq_dma_close(&priv->rxch.dma); ++ spin_unlock_irqrestore(&priv->lock, flags); + +- if (!IS_RX(i) && !IS_TX(i)) +- continue; +- napi_disable(&ch->napi); +- ltq_dma_close(&ch->dma); +- } + return 0; + } + +@@ -524,16 +685,16 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) + int queue = skb_get_queue_mapping(skb); + struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); + struct ltq_etop_priv *priv = netdev_priv(dev); +- struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; +- struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; +- int len; ++ struct ltq_dma_desc *desc = ++ &priv->txch.dma.desc_base[priv->txch.dma.desc]; + unsigned long flags; + u32 byte_offset; ++ int len; + + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; + +- if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { +- dev_kfree_skb_any(skb); ++ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ++ priv->txch.skb[priv->txch.dma.desc]) { + netdev_err(dev, "tx ring full\n"); + netif_tx_stop_queue(txq); + return NETDEV_TX_BUSY; +@@ -541,7 +702,7 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) + + /* dma needs to start on a 16 byte aligned address */ + byte_offset = CPHYSADDR(skb->data) % 16; +- ch->skb[ch->dma.desc] = skb; ++ priv->txch.skb[priv->txch.dma.desc] = skb; + + dev->trans_start = jiffies; + +@@ -551,11 +712,11 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev) + wmb(); + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | + LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); +- ch->dma.desc++; +- ch->dma.desc %= LTQ_DESC_NUM; ++ priv->txch.dma.desc++; ++ priv->txch.dma.desc %= LTQ_DESC_NUM; + spin_unlock_irqrestore(&priv->lock, flags); + +- if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) ++ if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN) + netif_tx_stop_queue(txq); + + return NETDEV_TX_OK; +@@ -640,6 +801,10 @@ ltq_etop_init(struct net_device *dev) + err = ltq_etop_hw_init(dev); + if (err) + goto err_hw; ++ err = ltq_etop_dma_init(dev); ++ if (err) ++ goto err_hw; ++ + ltq_etop_change_mtu(dev, 1500); + + memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); +@@ -652,9 +817,10 @@ ltq_etop_init(struct net_device *dev) + if (err) + goto err_netdev; + ltq_etop_set_multicast_list(dev); +- err = ltq_etop_mdio_init(dev); +- if (err) +- goto err_netdev; ++ if (!ltq_etop_mdio_init(dev)) ++ dev->ethtool_ops = <q_etop_ethtool_ops; ++ else ++ pr_warn("etop: mdio probe failed\n");; + return 0; + + err_netdev: +@@ -674,6 +840,9 @@ ltq_etop_tx_timeout(struct net_device *dev) + err = ltq_etop_hw_init(dev); + if (err) + goto err_hw; ++ err = ltq_etop_dma_init(dev); ++ if (err) ++ goto err_hw; + dev->trans_start = jiffies; + netif_wake_queue(dev); + return; +@@ -697,14 +866,13 @@ static const struct net_device_ops ltq_eth_netdev_ops = { + .ndo_tx_timeout = ltq_etop_tx_timeout, + }; + +-static int __init ++static int __devinit + ltq_etop_probe(struct platform_device *pdev) + { + struct net_device *dev; + struct ltq_etop_priv *priv; +- struct resource *res; ++ struct resource *res, *gbit_res; + int err; +- int i; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { +@@ -730,27 +898,62 @@ ltq_etop_probe(struct platform_device *pdev) + goto err_out; + } + ++ if (ltq_has_gbit()) { ++ gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (!gbit_res) { ++ dev_err(&pdev->dev, "failed to get gbit resource\n"); ++ err = -ENOENT; ++ goto err_out; ++ } ++ ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev, ++ gbit_res->start, resource_size(gbit_res)); ++ if (!ltq_gbit_membase) { ++ dev_err(&pdev->dev, "failed to remap gigabit switch %d\n", ++ pdev->id); ++ err = -ENOMEM; ++ goto err_out; ++ } ++ if (ltq_gpio_request(&pdev->dev, 42, 2, 1, "MDIO") || ++ ltq_gpio_request(&pdev->dev, 43, 2, 1, "MDC")) { ++ dev_err(&pdev->dev, "failed to request MDIO gpios\n"); ++ err = -EBUSY; ++ goto err_out; ++ } ++ } ++ + dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); + strcpy(dev->name, "eth%d"); + dev->netdev_ops = <q_eth_netdev_ops; +- dev->ethtool_ops = <q_etop_ethtool_ops; + priv = netdev_priv(dev); + priv->res = res; + priv->pdev = pdev; + priv->pldata = dev_get_platdata(&pdev->dev); + priv->netdev = dev; +- spin_lock_init(&priv->lock); + +- for (i = 0; i < MAX_DMA_CHAN; i++) { +- if (IS_TX(i)) +- netif_napi_add(dev, &priv->ch[i].napi, +- ltq_etop_poll_tx, 8); +- else if (IS_RX(i)) +- netif_napi_add(dev, &priv->ch[i].napi, +- ltq_etop_poll_rx, 32); +- priv->ch[i].netdev = dev; ++ priv->clk_ppe = clk_get(&pdev->dev, NULL); ++ if (IS_ERR(priv->clk_ppe)) ++ return PTR_ERR(priv->clk_ppe); ++ if (ltq_has_gbit()) { ++ priv->clk_switch = clk_get(&pdev->dev, "switch"); ++ if (IS_ERR(priv->clk_switch)) ++ return PTR_ERR(priv->clk_switch); ++ } ++ if (ltq_is_ase()) { ++ priv->clk_ephy = clk_get(&pdev->dev, "ephy"); ++ if (IS_ERR(priv->clk_ephy)) ++ return PTR_ERR(priv->clk_ephy); ++ priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu"); ++ if (IS_ERR(priv->clk_ephycgu)) ++ return PTR_ERR(priv->clk_ephycgu); + } + ++ spin_lock_init(&priv->lock); ++ ++ netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8); ++ netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32); ++ priv->txch.netdev = dev; ++ priv->rxch.netdev = dev; ++ + err = register_netdev(dev); + if (err) + goto err_free; +@@ -779,6 +982,7 @@ ltq_etop_remove(struct platform_device *pdev) + } + + static struct platform_driver ltq_mii_driver = { ++ .probe = ltq_etop_probe, + .remove = __devexit_p(ltq_etop_remove), + .driver = { + .name = "ltq_etop", +@@ -786,24 +990,7 @@ static struct platform_driver ltq_mii_driver = { + }, + }; + +-int __init +-init_ltq_etop(void) +-{ +- int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); +- +- if (ret) +- pr_err("ltq_etop: Error registering platfom driver!"); +- return ret; +-} +- +-static void __exit +-exit_ltq_etop(void) +-{ +- platform_driver_unregister(<q_mii_driver); +-} +- +-module_init(init_ltq_etop); +-module_exit(exit_ltq_etop); ++module_platform_driver(ltq_mii_driver); + + MODULE_AUTHOR("John Crispin "); + MODULE_DESCRIPTION("Lantiq SoC ETOP"); +diff --git a/net/ipv4/Kconfig b/net/ipv4/Kconfig +index d183262..7d444e0 100644 +--- a/net/ipv4/Kconfig ++++ b/net/ipv4/Kconfig +@@ -630,3 +630,10 @@ config TCP_MD5SIG + on the Internet. + + If unsure, say N. ++ ++config SVIP_NAT ++ bool "Include SVIP NAT" ++ depends on SOC_SVIP ++ default y ++ ---help--- ++ Include the SVIP NAT. +diff --git a/net/ipv4/Makefile b/net/ipv4/Makefile +index ff75d3b..1d57fe0 100644 +--- a/net/ipv4/Makefile ++++ b/net/ipv4/Makefile +@@ -53,3 +53,4 @@ obj-$(CONFIG_NETLABEL) += cipso_ipv4.o + + obj-$(CONFIG_XFRM) += xfrm4_policy.o xfrm4_state.o xfrm4_input.o \ + xfrm4_output.o ++obj-$(CONFIG_SVIP_NAT) += svip_nat.o +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0010-MIPS-lantiq-fix-STP-gpio-groups.patch b/target/linux/lantiq/patches-3.3/0010-MIPS-lantiq-fix-STP-gpio-groups.patch deleted file mode 100644 index 504caa9d66..0000000000 --- a/target/linux/lantiq/patches-3.3/0010-MIPS-lantiq-fix-STP-gpio-groups.patch +++ /dev/null @@ -1,37 +0,0 @@ -From 8da3264153de296b0d378befd4eb711f20d7843c Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 27 Oct 2011 20:06:05 +0200 -Subject: [PATCH 10/70] MIPS: lantiq: fix STP gpio groups - -The STP engine has 3 groups of 8 pins. Only the first was activated by default. -This patch activates the 2 missing groups. - -Signed-off-by: Matti Laakso -Signed-off-by: John Crispin ---- - arch/mips/lantiq/xway/gpio_stp.c | 7 +++++-- - 1 files changed, 5 insertions(+), 2 deletions(-) - ---- a/arch/mips/lantiq/xway/gpio_stp.c -+++ b/arch/mips/lantiq/xway/gpio_stp.c -@@ -35,6 +35,8 @@ - #define LTQ_STP_ADSL_SRC (3 << 24) - - #define LTQ_STP_GROUP0 (1 << 0) -+#define LTQ_STP_GROUP1 (1 << 1) -+#define LTQ_STP_GROUP2 (1 << 2) - - #define LTQ_STP_RISING 0 - #define LTQ_STP_FALLING (1 << 26) -@@ -93,8 +95,9 @@ static int ltq_stp_hw_init(void) - /* rising or falling edge */ - ltq_stp_w32_mask(LTQ_STP_EDGE_MASK, LTQ_STP_FALLING, LTQ_STP_CON0); - -- /* per default stp 15-0 are set */ -- ltq_stp_w32_mask(0, LTQ_STP_GROUP0, LTQ_STP_CON1); -+ /* enable all three led groups */ -+ ltq_stp_w32_mask(0, LTQ_STP_GROUP0 | LTQ_STP_GROUP1 | LTQ_STP_GROUP2, -+ LTQ_STP_CON1); - - /* stp are update periodically by the FPI bus */ - ltq_stp_w32_mask(LTQ_STP_UPD_MASK, LTQ_STP_UPD_FPI, LTQ_STP_CON1); diff --git a/target/linux/lantiq/patches-3.3/0010-watchdog-support.patch b/target/linux/lantiq/patches-3.3/0010-watchdog-support.patch new file mode 100644 index 0000000000..2a17107880 --- /dev/null +++ b/target/linux/lantiq/patches-3.3/0010-watchdog-support.patch @@ -0,0 +1,74 @@ +From 8b0fb3cc6548fa4b531a26a605a0e213962bb889 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 09:54:14 +0200 +Subject: [PATCH 10/25] watchdog support + +--- + drivers/watchdog/lantiq_wdt.c | 23 +++++------------------ + 1 files changed, 5 insertions(+), 18 deletions(-) + +diff --git a/drivers/watchdog/lantiq_wdt.c b/drivers/watchdog/lantiq_wdt.c +index d3a63be..70127b3 100644 +--- a/drivers/watchdog/lantiq_wdt.c ++++ b/drivers/watchdog/lantiq_wdt.c +@@ -16,7 +16,7 @@ + #include + #include + +-#include ++#include + + /* Section 3.4 of the datasheet + * The password sequence protects the WDT control register from unintended +@@ -182,7 +182,7 @@ static struct miscdevice ltq_wdt_miscdev = { + .fops = <q_wdt_fops, + }; + +-static int __init ++static int __devinit + ltq_wdt_probe(struct platform_device *pdev) + { + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); +@@ -206,7 +206,7 @@ ltq_wdt_probe(struct platform_device *pdev) + } + + /* we do not need to enable the clock as it is always running */ +- clk = clk_get(&pdev->dev, "io"); ++ clk = clk_get_io(); + WARN_ON(!clk); + ltq_io_region_clk_rate = clk_get_rate(clk); + clk_put(clk); +@@ -227,6 +227,7 @@ ltq_wdt_remove(struct platform_device *pdev) + + + static struct platform_driver ltq_wdt_driver = { ++ .probe = ltq_wdt_probe, + .remove = __devexit_p(ltq_wdt_remove), + .driver = { + .name = "ltq_wdt", +@@ -234,21 +235,7 @@ static struct platform_driver ltq_wdt_driver = { + }, + }; + +-static int __init +-init_ltq_wdt(void) +-{ +- return platform_driver_probe(<q_wdt_driver, ltq_wdt_probe); +-} +- +-static void __exit +-exit_ltq_wdt(void) +-{ +- return platform_driver_unregister(<q_wdt_driver); +-} +- +-module_init(init_ltq_wdt); +-module_exit(exit_ltq_wdt); +- ++module_platform_driver(ltq_wdt_driver); + module_param(nowayout, int, 0); + MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"); + +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0011-MIPS-lantiq-fix-pull-gpio-up-resistors-usage.patch b/target/linux/lantiq/patches-3.3/0011-MIPS-lantiq-fix-pull-gpio-up-resistors-usage.patch deleted file mode 100644 index 8a24001aa8..0000000000 --- a/target/linux/lantiq/patches-3.3/0011-MIPS-lantiq-fix-pull-gpio-up-resistors-usage.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 784e85cf7ce5032c9e5de35505fcc209f2a7891e Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 27 Oct 2011 20:06:30 +0200 -Subject: [PATCH 11/70] MIPS: lantiq: fix pull gpio up resistors usage - -The register that enables a gpios internal pullups was not used. This patch -makes sure the pullups are activated correctly. - -Signed-off-by: Matti Laakso -Signed-off-by: John Crispin ---- - arch/mips/lantiq/xway/gpio.c | 6 ++++++ - 1 files changed, 6 insertions(+), 0 deletions(-) - ---- a/arch/mips/lantiq/xway/gpio.c -+++ b/arch/mips/lantiq/xway/gpio.c -@@ -21,6 +21,8 @@ - #define LTQ_GPIO_ALTSEL0 0x0C - #define LTQ_GPIO_ALTSEL1 0x10 - #define LTQ_GPIO_OD 0x14 -+#define LTQ_GPIO_PUDSEL 0x1C -+#define LTQ_GPIO_PUDEN 0x20 - - #define PINS_PER_PORT 16 - #define MAX_PORTS 3 -@@ -106,6 +108,8 @@ static int ltq_gpio_direction_input(stru - - ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); - ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); -+ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset); -+ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset); - - return 0; - } -@@ -117,6 +121,8 @@ static int ltq_gpio_direction_output(str - - ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); - ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); -+ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset); -+ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset); - ltq_gpio_set(chip, offset, value); - - return 0; diff --git a/target/linux/lantiq/patches-3.3/0011-i2c-support.patch b/target/linux/lantiq/patches-3.3/0011-i2c-support.patch new file mode 100644 index 0000000000..5d8bc279d0 --- /dev/null +++ b/target/linux/lantiq/patches-3.3/0011-i2c-support.patch @@ -0,0 +1,46 @@ +From 5a39e76b3ea2f7dbf04f7dd2210536068583eaf6 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 09:54:22 +0200 +Subject: [PATCH 11/25] i2c support + +--- + drivers/i2c/busses/Kconfig | 10 ++++++++++ + drivers/i2c/busses/Makefile | 1 + + 2 files changed, 11 insertions(+), 0 deletions(-) + +diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig +index 3101dd5..e8d149d 100644 +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -369,6 +369,16 @@ config I2C_DESIGNWARE_PCI + This driver can also be built as a module. If so, the module + will be called i2c-designware-pci. + ++config I2C_FALCON ++ tristate "Falcon I2C interface" ++ depends on SOC_FALCON ++ help ++ If you say yes to this option, support will be included for the ++ Lantiq FALC-ON I2C core. ++ ++ This driver can also be built as a module. If so, the module ++ will be called i2c-falcon. ++ + config I2C_GPIO + tristate "GPIO-based bitbanging I2C" + depends on GENERIC_GPIO +diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile +index fba6da6..36239c8 100644 +--- a/drivers/i2c/busses/Makefile ++++ b/drivers/i2c/busses/Makefile +@@ -37,6 +37,7 @@ obj-$(CONFIG_I2C_DESIGNWARE_PLATFORM) += i2c-designware-platform.o + i2c-designware-platform-objs := i2c-designware-platdrv.o i2c-designware-core.o + obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o + i2c-designware-pci-objs := i2c-designware-pcidrv.o i2c-designware-core.o ++obj-$(CONFIG_I2C_FALCON) += i2c-falcon.o + obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o + obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o + obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0012-MIPS-lantiq-add-default-configs.patch b/target/linux/lantiq/patches-3.3/0012-MIPS-lantiq-add-default-configs.patch deleted file mode 100644 index 5f9a86caca..0000000000 --- a/target/linux/lantiq/patches-3.3/0012-MIPS-lantiq-add-default-configs.patch +++ /dev/null @@ -1,235 +0,0 @@ -From fe45fbd99c5b5815a08eccb81ef7fa16d60517cc Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 11 Nov 2011 22:02:27 +0100 -Subject: [PATCH 12/70] MIPS: lantiq: add default configs - -This patch adds the default config for 3 Lantiq SoCs - -* Danube/AR9 (xway) -* Amazon-SE -* Falc-ON - -Signed-off-by: John Crispin ---- - arch/mips/configs/ase_defconfig | 67 +++++++++++++++++++++++++++++++++ - arch/mips/configs/falcon_defconfig | 72 ++++++++++++++++++++++++++++++++++++ - arch/mips/configs/xway_defconfig | 66 +++++++++++++++++++++++++++++++++ - 3 files changed, 205 insertions(+), 0 deletions(-) - create mode 100644 arch/mips/configs/ase_defconfig - create mode 100644 arch/mips/configs/falcon_defconfig - create mode 100644 arch/mips/configs/xway_defconfig - ---- /dev/null -+++ b/arch/mips/configs/ase_defconfig -@@ -0,0 +1,67 @@ -+CONFIG_LANTIQ=y -+CONFIG_SOC_AMAZON_SE=y -+CONFIG_CPU_MIPS32_R2=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_EXPERIMENTAL=y -+CONFIG_DEFAULT_HOSTNAME="amazon_se" -+CONFIG_SYSVIPC=y -+CONFIG_LOG_BUF_SHIFT=14 -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_INITRAMFS_SOURCE="../root-lantiq/ ../root-lantiq/initramfs-base-files.txt" -+CONFIG_INITRAMFS_ROOT_UID=1000 -+CONFIG_INITRAMFS_ROOT_GID=1000 -++# CONFIG_RD_GZIP is not set -+CONFIG_RD_LZMA=y -+CONFIG_EMBEDDED=y -+CONFIG_SLAB=y -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_DEFAULT_DEADLINE=y -+CONFIG_NET=y -+CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_ADVANCED_ROUTER=y -+CONFIG_IP_MULTIPLE_TABLES=y -+CONFIG_IP_ROUTE_MULTIPATH=y -+CONFIG_IP_ROUTE_VERBOSE=y -+CONFIG_IP_MROUTE=y -+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y -+CONFIG_ARPD=y -+CONFIG_SYN_COOKIES=y -+CONFIG_NETFILTER=y -+CONFIG_BRIDGE=m -+CONFIG_VLAN_8021Q=y -+CONFIG_NET_SCHED=y -+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -+CONFIG_MTD=y -+CONFIG_MTD_CMDLINE_PARTS=y -+CONFIG_MTD_CHAR=y -+CONFIG_MTD_BLOCK=y -+CONFIG_MTD_CFI=y -+CONFIG_MTD_CFI_ADV_OPTIONS=y -+CONFIG_MTD_CFI_GEOMETRY=y -+CONFIG_MTD_CFI_INTELEXT=y -+CONFIG_MTD_CFI_AMDSTD=y -+CONFIG_MTD_COMPLEX_MAPPINGS=y -+CONFIG_MTD_LANTIQ=y -+CONFIG_MISC_DEVICES=y -+CONFIG_NETDEVICES=y -+CONFIG_MII=y -+CONFIG_LANTIQ_ETOP=y -+CONFIG_PHYLIB=y -+CONFIG_SERIAL_LANTIQ=y -+CONFIG_PINCTRL=y -+CONFIG_GPIO_SYSFS=y -+CONFIG_WATCHDOG=y -+CONFIG_LANTIQ_WDT=y -+CONFIG_TMPFS=y -+CONFIG_JFFS2_FS=y -+CONFIG_JFFS2_SUMMARY=y -+CONFIG_JFFS2_FS_XATTR=y -+CONFIG_JFFS2_COMPRESSION_OPTIONS=y -+CONFIG_SQUASHFS=y -+CONFIG_SQUASHFS_XZ=y -+CONFIG_STRIP_ASM_SYMS=y -+CONFIG_DEBUG_FS=y ---- /dev/null -+++ b/arch/mips/configs/falcon_defconfig -@@ -0,0 +1,72 @@ -+CONFIG_LANTIQ=y -+CONFIG_SOC_FALCON=y -+CONFIG_CPU_MIPS32_R2=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_EXPERIMENTAL=y -+CONFIG_DEFAULT_HOSTNAME="falcon" -+CONFIG_SYSVIPC=y -+CONFIG_LOG_BUF_SHIFT=14 -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_INITRAMFS_SOURCE="../root-lantiq/ ../root-lantiq/initramfs-base-files.txt" -+CONFIG_INITRAMFS_ROOT_UID=1000 -+CONFIG_INITRAMFS_ROOT_GID=1000 -++# CONFIG_RD_GZIP is not set -+CONFIG_RD_LZMA=y -+CONFIG_EMBEDDED=y -+CONFIG_SLAB=y -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_DEFAULT_DEADLINE=y -+CONFIG_NET=y -+CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_ADVANCED_ROUTER=y -+CONFIG_IP_MULTIPLE_TABLES=y -+CONFIG_IP_ROUTE_MULTIPATH=y -+CONFIG_IP_ROUTE_VERBOSE=y -+CONFIG_IP_MROUTE=y -+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y -+CONFIG_ARPD=y -+CONFIG_SYN_COOKIES=y -+CONFIG_NETFILTER=y -+CONFIG_BRIDGE=m -+CONFIG_VLAN_8021Q=y -+CONFIG_NET_SCHED=y -+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -+CONFIG_MTD=y -+CONFIG_MTD_CMDLINE_PARTS=y -+CONFIG_MTD_CHAR=y -+CONFIG_MTD_BLOCK=y -+CONFIG_MTD_CFI=y -+CONFIG_MTD_CFI_ADV_OPTIONS=y -+CONFIG_MTD_CFI_GEOMETRY=y -+CONFIG_MTD_CFI_INTELEXT=y -+CONFIG_MTD_CFI_AMDSTD=y -+CONFIG_MTD_COMPLEX_MAPPINGS=y -+CONFIG_MTD_LANTIQ=y -+CONFIG_MTD_M25P80=y -+CONFIG_MISC_DEVICES=y -+CONFIG_EEPROM_AT24=y -+CONFIG_NETDEVICES=y -+CONFIG_MII=y -+CONFIG_PHYLIB=y -+CONFIG_SERIAL_LANTIQ=y -+CONFIG_I2C=y -+CONFIG_I2C_FALCON=y -+CONFIG_SPI=y -+CONFIG_SPI_FALCON=y -+CONFIG_PINCTRL=y -+CONFIG_GPIO_SYSFS=y -+CONFIG_WATCHDOG=y -+CONFIG_LANTIQ_WDT=y -+CONFIG_TMPFS=y -+CONFIG_JFFS2_FS=y -+CONFIG_JFFS2_SUMMARY=y -+CONFIG_JFFS2_FS_XATTR=y -+CONFIG_JFFS2_COMPRESSION_OPTIONS=y -+CONFIG_SQUASHFS=y -+CONFIG_SQUASHFS_XZ=y -+CONFIG_STRIP_ASM_SYMS=y -+CONFIG_DEBUG_FS=y ---- /dev/null -+++ b/arch/mips/configs/xway_defconfig -@@ -0,0 +1,66 @@ -+CONFIG_LANTIQ=y -+CONFIG_CPU_MIPS32_R2=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_EXPERIMENTAL=y -+CONFIG_DEFAULT_HOSTNAME="danube" -+CONFIG_SYSVIPC=y -+CONFIG_LOG_BUF_SHIFT=14 -+CONFIG_BLK_DEV_INITRD=y -+CONFIG_INITRAMFS_SOURCE="../root-lantiq/ ../root-lantiq/initramfs-base-files.txt" -+CONFIG_INITRAMFS_ROOT_UID=1000 -+CONFIG_INITRAMFS_ROOT_GID=1000 -+# CONFIG_RD_GZIP is not set -+CONFIG_RD_LZMA=y -+CONFIG_EMBEDDED=y -+CONFIG_SLAB=y -+CONFIG_MODULES=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_DEFAULT_DEADLINE=y -+CONFIG_NET=y -+CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_INET=y -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_ADVANCED_ROUTER=y -+CONFIG_IP_MULTIPLE_TABLES=y -+CONFIG_IP_ROUTE_MULTIPATH=y -+CONFIG_IP_ROUTE_VERBOSE=y -+CONFIG_IP_MROUTE=y -+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y -+CONFIG_ARPD=y -+CONFIG_SYN_COOKIES=y -+CONFIG_NETFILTER=y -+CONFIG_BRIDGE=m -+CONFIG_VLAN_8021Q=y -+CONFIG_NET_SCHED=y -+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -+CONFIG_MTD=y -+CONFIG_MTD_CMDLINE_PARTS=y -+CONFIG_MTD_CHAR=y -+CONFIG_MTD_BLOCK=y -+CONFIG_MTD_CFI=y -+CONFIG_MTD_CFI_ADV_OPTIONS=y -+CONFIG_MTD_CFI_GEOMETRY=y -+CONFIG_MTD_CFI_INTELEXT=y -+CONFIG_MTD_CFI_AMDSTD=y -+CONFIG_MTD_COMPLEX_MAPPINGS=y -+CONFIG_MTD_LANTIQ=y -+CONFIG_MISC_DEVICES=y -+CONFIG_NETDEVICES=y -+CONFIG_MII=y -+CONFIG_LANTIQ_ETOP=y -+CONFIG_PHYLIB=y -+CONFIG_SERIAL_LANTIQ=y -+CONFIG_PINCTRL=y -+CONFIG_GPIO_SYSFS=y -+CONFIG_WATCHDOG=y -+CONFIG_LANTIQ_WDT=y -+CONFIG_TMPFS=y -+CONFIG_JFFS2_FS=y -+CONFIG_JFFS2_SUMMARY=y -+CONFIG_JFFS2_FS_XATTR=y -+CONFIG_JFFS2_COMPRESSION_OPTIONS=y -+CONFIG_SQUASHFS=y -+CONFIG_SQUASHFS_XZ=y -+CONFIG_STRIP_ASM_SYMS=y -+CONFIG_DEBUG_FS=y diff --git a/target/linux/lantiq/patches-3.3/0012-tty-support.patch b/target/linux/lantiq/patches-3.3/0012-tty-support.patch new file mode 100644 index 0000000000..52bd9de87c --- /dev/null +++ b/target/linux/lantiq/patches-3.3/0012-tty-support.patch @@ -0,0 +1,90 @@ +From 3b11721314a100e40634a80062d0d2cce1dc83dc Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 09:54:27 +0200 +Subject: [PATCH 12/25] tty support + +--- + drivers/tty/serial/lantiq.c | 25 +++++++++++++++++++++---- + 1 files changed, 21 insertions(+), 4 deletions(-) + +diff --git a/drivers/tty/serial/lantiq.c b/drivers/tty/serial/lantiq.c +index 96c1cac..82956de 100644 +--- a/drivers/tty/serial/lantiq.c ++++ b/drivers/tty/serial/lantiq.c +@@ -107,6 +107,9 @@ + #define ASCFSTAT_TXFREEMASK 0x3F000000 + #define ASCFSTAT_TXFREEOFF 24 + ++#define MUXC_SIF_RX_PIN 112 ++#define MUXC_SIF_TX_PIN 113 ++ + static void lqasc_tx_chars(struct uart_port *port); + static struct ltq_uart_port *lqasc_port[MAXPORTS]; + static struct uart_driver lqasc_reg; +@@ -114,6 +117,7 @@ static DEFINE_SPINLOCK(ltq_asc_lock); + + struct ltq_uart_port { + struct uart_port port; ++ struct clk *fpiclk; + struct clk *clk; + unsigned int tx_irq; + unsigned int rx_irq; +@@ -316,7 +320,7 @@ lqasc_startup(struct uart_port *port) + struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); + int retval; + +- port->uartclk = clk_get_rate(ltq_port->clk); ++ port->uartclk = clk_get_rate(ltq_port->fpiclk); + + ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), + port->membase + LTQ_ASC_CLC); +@@ -529,6 +533,19 @@ lqasc_request_port(struct uart_port *port) + if (port->membase == NULL) + return -ENOMEM; + } ++ if (ltq_is_falcon() && (port->line == 1)) { ++ struct ltq_uart_port *ltq_port = lqasc_port[pdev->id]; ++ if (ltq_gpio_request(&pdev->dev, MUXC_SIF_RX_PIN, ++ 3, 0, "asc1-rx")) ++ return -EBUSY; ++ if (ltq_gpio_request(&pdev->dev, MUXC_SIF_TX_PIN, ++ 3, 1, "asc1-tx")) ++ return -EBUSY; ++ ltq_port->clk = clk_get(&pdev->dev, NULL); ++ if (IS_ERR(ltq_port->clk)) ++ return PTR_ERR(ltq_port->clk); ++ clk_enable(ltq_port->clk); ++ } + return 0; + } + +@@ -630,7 +647,7 @@ lqasc_console_setup(struct console *co, char *options) + + port = <q_port->port; + +- port->uartclk = clk_get_rate(ltq_port->clk); ++ port->uartclk = clk_get_rate(ltq_port->fpiclk); + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); +@@ -686,7 +703,7 @@ lqasc_probe(struct platform_device *pdev) + if (lqasc_port[pdev->id] != NULL) + return -EBUSY; + +- clk = clk_get(&pdev->dev, "fpi"); ++ clk = clk_get_fpi(); + if (IS_ERR(clk)) { + pr_err("failed to get fpi clk\n"); + return -ENOENT; +@@ -715,7 +732,7 @@ lqasc_probe(struct platform_device *pdev) + port->irq = tx_irq; /* unused, just to be backward-compatibe */ + port->mapbase = mmres->start; + +- ltq_port->clk = clk; ++ ltq_port->fpiclk = clk; + + ltq_port->tx_irq = tx_irq; + ltq_port->rx_irq = rx_irq; +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0013-MAINTAINERS-add-entry-for-Lantiq-related-files.patch b/target/linux/lantiq/patches-3.3/0013-MAINTAINERS-add-entry-for-Lantiq-related-files.patch deleted file mode 100644 index c81e3530c4..0000000000 --- a/target/linux/lantiq/patches-3.3/0013-MAINTAINERS-add-entry-for-Lantiq-related-files.patch +++ /dev/null @@ -1,33 +0,0 @@ -From adb6262219beb9ba1986dc0216911e2611a6a996 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 10 Nov 2011 19:32:37 +0100 -Subject: [PATCH 13/70] MAINTAINERS: add entry for Lantiq related files - -Adds new entry to MAINTAINERS file for Lantiq SoC related code. - -Signed-off-by: John Crispin ---- - MAINTAINERS | 12 ++++++++++++ - 1 files changed, 12 insertions(+), 0 deletions(-) - ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -4397,6 +4397,18 @@ S: Supported - F: Documentation/mips/ - F: arch/mips/ - -+MIPS/LANTIQ -+M: John Crispin -+M: Thomas Langer -+S: Maintained -+F: arch/mips/lantiq/* -+F: drivers/i2c/busses/i2c-falcon.c -+F: drivers/mtd/maps/lantiq-flash.c -+F: drivers/net/ethernet/lantiq_etop.c -+F: drivers/spi/spi-falcon.c -+F: drivers/tty/serial/lantiq.c -+F: drivers/watchdog/lantiq_wdt.c -+ - MISCELLANEOUS MCA-SUPPORT - M: James Bottomley - S: Maintained diff --git a/target/linux/lantiq/patches-3.3/0013-machtype-support.patch b/target/linux/lantiq/patches-3.3/0013-machtype-support.patch new file mode 100644 index 0000000000..87f592338b --- /dev/null +++ b/target/linux/lantiq/patches-3.3/0013-machtype-support.patch @@ -0,0 +1,568 @@ +From f1c9b41720476cd660a852134b0e8a8acd601441 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 10:23:08 +0200 +Subject: [PATCH 13/25] machtype support + +--- + arch/mips/lantiq/Makefile | 2 +- + arch/mips/lantiq/devices.c | 18 ++++ + arch/mips/lantiq/devices.h | 1 + + arch/mips/lantiq/falcon/Kconfig | 8 ++ + arch/mips/lantiq/falcon/Makefile | 4 + + arch/mips/lantiq/falcon/mach-easy98000.c | 162 ++++++++++++++++++++++++++--- + arch/mips/lantiq/machtypes.h | 42 ++++++++ + arch/mips/lantiq/xway/Kconfig | 32 ++++++ + arch/mips/lantiq/xway/Makefile | 11 ++ + arch/mips/lantiq/xway/devices.c | 95 +++++++++++++++++ + arch/mips/lantiq/xway/devices.h | 6 + + 11 files changed, 363 insertions(+), 18 deletions(-) + +diff --git a/arch/mips/lantiq/Makefile b/arch/mips/lantiq/Makefile +index db1ce50..4f245d8 100644 +--- a/arch/mips/lantiq/Makefile ++++ b/arch/mips/lantiq/Makefile +@@ -4,7 +4,7 @@ + # under the terms of the GNU General Public License version 2 as published + # by the Free Software Foundation. + +-obj-y := irq.o setup.o clk.o prom.o devices.o ++obj-y := irq.o setup.o clk.o prom.o devices.o dev-gpio-leds.o dev-gpio-buttons.o + + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + +diff --git a/arch/mips/lantiq/devices.c b/arch/mips/lantiq/devices.c +index 7193d78..2d7c46a 100644 +--- a/arch/mips/lantiq/devices.c ++++ b/arch/mips/lantiq/devices.c +@@ -18,6 +18,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -100,3 +101,20 @@ void __init ltq_register_pci(struct ltq_pci_data *data) + pr_err("kernel is compiled without PCI support\n"); + } + #endif ++ ++static unsigned int *cp1_base = 0; ++unsigned int* ++ltq_get_cp1_base(void) ++{ ++ return cp1_base; ++} ++EXPORT_SYMBOL(ltq_get_cp1_base); ++ ++void __init ++ltq_register_tapi(void) ++{ ++#define CP1_SIZE (1 << 20) ++ dma_addr_t dma; ++ cp1_base = ++ (void*)CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE, &dma, GFP_ATOMIC)); ++} +diff --git a/arch/mips/lantiq/devices.h b/arch/mips/lantiq/devices.h +index a03c23f..59d904c 100644 +--- a/arch/mips/lantiq/devices.h ++++ b/arch/mips/lantiq/devices.h +@@ -23,5 +23,6 @@ extern void ltq_register_nor(struct physmap_flash_data *data); + extern void ltq_register_wdt(void); + extern void ltq_register_asc(int port); + extern void ltq_register_pci(struct ltq_pci_data *data); ++extern void ltq_register_tapi(void); + + #endif +diff --git a/arch/mips/lantiq/falcon/Kconfig b/arch/mips/lantiq/falcon/Kconfig +index 03e999d..2e3e59c 100644 +--- a/arch/mips/lantiq/falcon/Kconfig ++++ b/arch/mips/lantiq/falcon/Kconfig +@@ -6,6 +6,14 @@ config LANTIQ_MACH_EASY98000 + bool "Easy98000" + default y + ++config LANTIQ_MACH_EASY98020 ++ bool "Easy98020" ++ default y ++ ++config LANTIQ_MACH_95C3AM1 ++ bool "95C3AM1" ++ default y ++ + endmenu + + endif +diff --git a/arch/mips/lantiq/falcon/Makefile b/arch/mips/lantiq/falcon/Makefile +index 3634154..aa1fc69 100644 +--- a/arch/mips/lantiq/falcon/Makefile ++++ b/arch/mips/lantiq/falcon/Makefile +@@ -1,2 +1,6 @@ + obj-y := prom.o reset.o sysctrl.o devices.o gpio.o ++obj-$(CONFIG_LANTIQ_MACH_EASY98000) += addon-easy98000.o ++obj-$(CONFIG_LANTIQ_MACH_EASY98000) += dev-leds-easy98000-cpld.o + obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o ++obj-$(CONFIG_LANTIQ_MACH_EASY98020) += mach-easy98020.o ++obj-$(CONFIG_LANTIQ_MACH_95C3AM1) += mach-95C3AM1.o +diff --git a/arch/mips/lantiq/falcon/mach-easy98000.c b/arch/mips/lantiq/falcon/mach-easy98000.c +index fc5720d..adf6b5d 100644 +--- a/arch/mips/lantiq/falcon/mach-easy98000.c ++++ b/arch/mips/lantiq/falcon/mach-easy98000.c +@@ -1,23 +1,48 @@ +-/* +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- * +- * Copyright (C) 2011 Thomas Langer +- * Copyright (C) 2011 John Crispin +- */ +- ++#include + #include ++#include ++#include ++#include ++#include ++#include + #include ++#include ++#include ++#include ++#include ++#include ++#include + #include + #include + #include ++#include ++ ++#include + + #include "../machtypes.h" + + #include "devices.h" + +-static struct mtd_partition easy98000_nor_partitions[] = { ++#define EASY98000_GPIO_LED_0 9 ++#define EASY98000_GPIO_LED_1 10 ++#define EASY98000_GPIO_LED_2 11 ++#define EASY98000_GPIO_LED_3 12 ++#define EASY98000_GPIO_LED_4 13 ++#define EASY98000_GPIO_LED_5 14 ++ ++static unsigned char ltq_ethaddr[6] = {0}; ++ ++static int __init falcon_set_ethaddr(char *str) ++{ ++ sscanf(str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", ++ <q_ethaddr[0], <q_ethaddr[1], <q_ethaddr[2], ++ <q_ethaddr[3], <q_ethaddr[4], <q_ethaddr[5]); ++ return 0; ++} ++__setup("ethaddr=", falcon_set_ethaddr); ++ ++static struct mtd_partition easy98000_nor_partitions[] = ++{ + { + .name = "uboot", + .offset = 0x0, +@@ -35,7 +60,7 @@ static struct mtd_partition easy98000_nor_partitions[] = { + }, + }; + +-struct physmap_flash_data easy98000_nor_flash_data = { ++static struct physmap_flash_data easy98000_nor_flash_data = { + .nr_parts = ARRAY_SIZE(easy98000_nor_partitions), + .parts = easy98000_nor_partitions, + }; +@@ -55,12 +80,104 @@ static struct spi_board_info easy98000_spi_flash_data __initdata = { + .platform_data = &easy98000_spi_flash_platform_data + }; + ++static struct gpio_led easy98000_gpio_leds[] __initdata = { ++ { ++ .name = "easy98000:green:0", ++ .gpio = EASY98000_GPIO_LED_0, ++ .active_low = 0, ++ }, { ++ .name = "easy98000:green:1", ++ .gpio = EASY98000_GPIO_LED_1, ++ .active_low = 0, ++ }, { ++ .name = "easy98000:green:2", ++ .gpio = EASY98000_GPIO_LED_2, ++ .active_low = 0, ++ }, { ++ .name = "easy98000:green:3", ++ .gpio = EASY98000_GPIO_LED_3, ++ .active_low = 0, ++ }, { ++ .name = "easy98000:green:4", ++ .gpio = EASY98000_GPIO_LED_4, ++ .active_low = 0, ++ }, { ++ .name = "easy98000:green:5", ++ .gpio = EASY98000_GPIO_LED_5, ++ .active_low = 0, ++ } ++}; ++ ++#define CONFIG_DM9000_BASE 0x14000000 ++#define DM9000_IO (CONFIG_DM9000_BASE + 3) ++#define DM9000_DATA (CONFIG_DM9000_BASE + 1) ++ ++static struct dm9000_plat_data dm9000_plat_data = { ++ .flags = DM9000_PLATF_8BITONLY, ++}; ++ ++static struct resource dm9000_resources[] = { ++ MEM_RES("dm9000_io", DM9000_IO, 1), ++ MEM_RES("dm9000_data", DM9000_DATA, 1), ++ [2] = { ++ /* with irq (210 -> gpio 110) the driver is very unreliable */ ++ .start = -1, /* use polling */ ++ .end = -1, ++ .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, ++ }, ++}; ++ ++static struct platform_device dm9000_platform = { ++ .name = "dm9000", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(dm9000_resources), ++ .resource = dm9000_resources, ++ .dev = { ++ .platform_data = (void *) &dm9000_plat_data, ++ } ++}; ++ ++extern int easy98000_addon_has_dm9000(void); ++static void __init register_davicom(void) ++{ ++ if (!easy98000_addon_has_dm9000()) ++ return; ++ ++ if (!is_valid_ether_addr(ltq_ethaddr)) ++ random_ether_addr(dm9000_plat_data.dev_addr); ++ else { ++ memcpy(dm9000_plat_data.dev_addr, ltq_ethaddr, 6); ++ /* change to "Locally Administered Address" */ ++ dm9000_plat_data.dev_addr[0] |= 0x2; ++ } ++ platform_device_register(&dm9000_platform); ++} ++ ++static struct i2c_gpio_platform_data easy98000_i2c_gpio_data = { ++ .sda_pin = 107, ++ .scl_pin = 108, ++}; ++ ++static struct platform_device easy98000_i2c_gpio_device = { ++ .name = "i2c-gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = &easy98000_i2c_gpio_data, ++ } ++}; ++ ++void __init register_easy98000_cpld(void) ++{ ++ platform_device_register_simple("easy98000_cpld_led", 0, NULL, 0); ++ platform_device_register_simple("easy98000_addon", 0, NULL, 0); ++} ++ + /* setup gpio based spi bus/device for access to the eeprom on the board */ +-#define SPI_GPIO_MRST 102 +-#define SPI_GPIO_MTSR 103 +-#define SPI_GPIO_CLK 104 +-#define SPI_GPIO_CS0 105 +-#define SPI_GPIO_CS1 106 ++#define SPI_GPIO_MRST 102 ++#define SPI_GPIO_MTSR 103 ++#define SPI_GPIO_CLK 104 ++#define SPI_GPIO_CS0 105 ++#define SPI_GPIO_CS1 106 + #define SPI_GPIO_BUS_NUM 1 + + static struct spi_gpio_platform_data easy98000_spi_gpio_data = { +@@ -94,11 +211,22 @@ static struct spi_board_info easy98000_spi_gpio_devices __initdata = { + }; + + static void __init +-easy98000_init_common(void) ++easy98000_spi_gpio_init(void) + { + spi_register_board_info(&easy98000_spi_gpio_devices, 1); + platform_device_register(&easy98000_spi_gpio_device); ++} ++ ++static void __init ++easy98000_init_common(void) ++{ + falcon_register_i2c(); ++ platform_device_register(&easy98000_i2c_gpio_device); ++ register_davicom(); ++ ltq_add_device_gpio_leds(-1, ARRAY_SIZE(easy98000_gpio_leds), ++ easy98000_gpio_leds); ++ register_easy98000_cpld(); ++ easy98000_spi_gpio_init(); + } + + static void __init +diff --git a/arch/mips/lantiq/machtypes.h b/arch/mips/lantiq/machtypes.h +index dfc6af7..7690f6a 100644 +--- a/arch/mips/lantiq/machtypes.h ++++ b/arch/mips/lantiq/machtypes.h +@@ -16,10 +16,52 @@ enum lantiq_mach_type { + LTQ_MACH_EASY50712, /* Danube evaluation board */ + LTQ_MACH_EASY50601, /* Amazon SE evaluation board */ + ++ /* SVIP */ ++ LANTIQ_MACH_EASY33016, /* SVIP Easy33016 */ ++ LANTIQ_MACH_EASY336, /* SVIP Easy336, NOR Flash */ ++ LANTIQ_MACH_EASY336SF, /* SVIP Easy336, Serial Flash */ ++ LANTIQ_MACH_EASY336NAND, /* SVIP Easy336, NAND Flash */ ++ + /* FALCON */ + LANTIQ_MACH_EASY98000, /* Falcon Eval Board, NOR Flash */ + LANTIQ_MACH_EASY98000SF, /* Falcon Eval Board, Serial Flash */ + LANTIQ_MACH_EASY98000NAND, /* Falcon Eval Board, NAND Flash */ ++ LANTIQ_MACH_EASY98020, /* EASY98020 Eval Board */ ++ LANTIQ_MACH_EASY98020_1LAN, /* EASY98020 Eval Board (1 LAN port) */ ++ LANTIQ_MACH_EASY98020_2LAN, /* EASY98020 Eval Board (2 LAN port) */ ++ LANTIQ_MACH_95C3AM1, /* 95C3AM1 Eval Board */ ++ ++ /* Arcadyan */ ++ LANTIQ_MACH_ARV3527P, /* Arcor easybox a401 */ ++ LANTIQ_MACH_ARV4510PW, /* Wippies Homebox */ ++ LANTIQ_MACH_ARV4518PW, /* Airties WAV-221, SMC-7908A-ISP */ ++ LANTIQ_MACH_ARV4519PW, /* Vodafone, Pirelli */ ++ LANTIQ_MACH_ARV4520PW, /* Airties WAV-281, Arcor EasyboxA800 */ ++ LANTIQ_MACH_ARV452CPW, /* Arcor EasyboxA801 */ ++ LANTIQ_MACH_ARV4525PW, /* Speedport W502V */ ++ LANTIQ_MACH_ARV7525PW, /* Speedport W303V */ ++ LANTIQ_MACH_ARV752DPW, /* Arcor easybox a802 */ ++ LANTIQ_MACH_ARV752DPW22, /* Arcor easybox a803 */ ++ LANTIQ_MACH_ARV7518PW, /* ASTORIA */ ++ ++ /* Netgear */ ++ LANTIQ_MACH_DGN3500B, /* Netgear DGN3500 */ ++ ++ /* FRITZ!BOX */ ++ LANTIQ_MACH_FRITZ3370, /* FRITZ!BOX 3370 vdsl cpe */ ++ LANTIQ_MACH_FRITZ7320, /* FRITZ!BOX 7320 1&1 homeserver */ ++ ++ /* Gigaset */ ++ LANTIQ_MACH_GIGASX76X, /* Gigaset SX76x */ ++ ++ /* Buffalo */ ++ LANTIQ_MACH_WBMR, /* WBMR-HP-G300H */ ++ ++ /* ZyXEL */ ++ LANTIQ_MACH_P2601HNFX, /* ZyXEL P-2601HN-Fx */ ++ ++ /* ZTE */ ++ LANTIQ_MACH_H201L, /* ZTE ZXV10 H201L */ + }; + + #endif +diff --git a/arch/mips/lantiq/xway/Kconfig b/arch/mips/lantiq/xway/Kconfig +index 54a51ff..8ad481c 100644 +--- a/arch/mips/lantiq/xway/Kconfig ++++ b/arch/mips/lantiq/xway/Kconfig +@@ -6,6 +6,38 @@ config LANTIQ_MACH_EASY50712 + bool "Easy50712 - Danube" + default y + ++config LANTIQ_MACH_ARV ++ bool "ARV" ++ default y ++ ++config LANTIQ_MACH_NETGEAR ++ bool "Netgear" ++ default y ++ ++config LANTIQ_MACH_GIGASX76X ++ bool "GIGASX76X" ++ default y ++ ++config LANTIQ_MACH_WBMR ++ bool "WBMR-HP-G300H" ++ default y ++ ++config LANTIQ_MACH_P2601HNFX ++ bool "P2601HNFX" ++ default y ++ ++config LANTIQ_MACH_H201L ++ bool "H201L" ++ default y ++ ++config LANTIQ_MACH_FRITZ_VR9 ++ bool "FRITZ3370" ++ default y ++ ++config LANTIQ_MACH_FRITZ_AR9 ++ bool "FRITZ7320" ++ default y ++ + endmenu + + choice +diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile +index c9baf91..d9f3685 100644 +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -1,4 +1,15 @@ + obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o timer.o dev-ifxhcd.o + ++obj-y += dev-dwc_otg.o ++obj-$(CONFIG_PCI) += dev-wifi-rt2x00.o dev-wifi-athxk.o pci-ath-fixup.o ++ + obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o + obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o ++obj-$(CONFIG_LANTIQ_MACH_ARV) += mach-arv.o ++obj-$(CONFIG_LANTIQ_MACH_FRITZ_AR9) += mach-fritz_ar9.o ++obj-$(CONFIG_LANTIQ_MACH_FRITZ_VR9) += mach-fritz_vr9.o ++obj-$(CONFIG_LANTIQ_MACH_GIGASX76X) += mach-gigasx76x.o ++obj-$(CONFIG_LANTIQ_MACH_NETGEAR) += mach-netgear.o ++obj-$(CONFIG_LANTIQ_MACH_WBMR) += mach-wbmr.o ++obj-$(CONFIG_LANTIQ_MACH_P2601HNFX) += mach-p2601hnfx.o ++obj-$(CONFIG_LANTIQ_MACH_H201L) += mach-h201l.o +diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c +index 5d4650d..64fe713 100644 +--- a/arch/mips/lantiq/xway/devices.c ++++ b/arch/mips/lantiq/xway/devices.c +@@ -19,6 +19,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -119,3 +120,97 @@ ltq_register_vrx200(struct ltq_eth_data *eth) + ltq_vrx200.dev.platform_data = eth; + platform_device_register(<q_vrx200); + } ++ ++/* ebu */ ++static struct resource ltq_ebu_resource = ++{ ++ .name = "gpio_ebu", ++ .start = LTQ_EBU_GPIO_START, ++ .end = LTQ_EBU_GPIO_START + LTQ_EBU_GPIO_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device ltq_ebu = ++{ ++ .name = "ltq_ebu", ++ .resource = <q_ebu_resource, ++ .num_resources = 1, ++}; ++ ++void __init ++ltq_register_gpio_ebu(unsigned int value) ++{ ++ ltq_ebu.dev.platform_data = (void*) value; ++ platform_device_register(<q_ebu); ++} ++ ++/* gpio buttons */ ++static struct gpio_buttons_platform_data ltq_gpio_buttons_platform_data; ++ ++static struct platform_device ltq_gpio_buttons_platform_device = ++{ ++ .name = "gpio-buttons", ++ .id = 0, ++ .dev = { ++ .platform_data = (void *) <q_gpio_buttons_platform_data, ++ }, ++}; ++ ++void __init ++ltq_register_gpio_buttons(struct gpio_button *buttons, int cnt) ++{ ++ ltq_gpio_buttons_platform_data.buttons = buttons; ++ ltq_gpio_buttons_platform_data.nbuttons = cnt; ++ platform_device_register(<q_gpio_buttons_platform_device); ++} ++ ++static struct resource ltq_spi_resources[] = { ++ { ++ .start = LTQ_SSC_BASE_ADDR, ++ .end = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ IRQ_RES(spi_tx, LTQ_SSC_TIR), ++ IRQ_RES(spi_rx, LTQ_SSC_RIR), ++ IRQ_RES(spi_err, LTQ_SSC_EIR), ++}; ++ ++static struct resource ltq_spi_resources_ar9[] = { ++ { ++ .start = LTQ_SSC_BASE_ADDR, ++ .end = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ IRQ_RES(spi_tx, LTQ_SSC_TIR_AR9), ++ IRQ_RES(spi_rx, LTQ_SSC_RIR_AR9), ++ IRQ_RES(spi_err, LTQ_SSC_EIR), ++}; ++ ++static struct resource ltq_spi_resources_ase[] = { ++ { ++ .start = LTQ_SSC_BASE_ADDR, ++ .end = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ IRQ_RES(spi_tx, LTQ_SSC_TIR_ASE), ++ IRQ_RES(spi_rx, LTQ_SSC_RIR_ASE), ++ IRQ_RES(spi_err, LTQ_SSC_EIR_ASE), ++}; ++ ++static struct platform_device ltq_spi = { ++ .name = "ltq_spi", ++ .resource = ltq_spi_resources, ++ .num_resources = ARRAY_SIZE(ltq_spi_resources), ++}; ++ ++void __init ltq_register_spi(struct ltq_spi_platform_data *pdata, ++ struct spi_board_info const *info, unsigned n) ++{ ++ if (ltq_is_ar9()) ++ ltq_spi.resource = ltq_spi_resources_ar9; ++ else if (ltq_is_ase()) ++ ltq_spi.resource = ltq_spi_resources_ase; ++ spi_register_board_info(info, n); ++ ltq_spi.dev.platform_data = pdata; ++ platform_device_register(<q_spi); ++} +diff --git a/arch/mips/lantiq/xway/devices.h b/arch/mips/lantiq/xway/devices.h +index 08befd9..dcf2a14 100644 +--- a/arch/mips/lantiq/xway/devices.h ++++ b/arch/mips/lantiq/xway/devices.h +@@ -11,6 +11,8 @@ + + #include "../devices.h" + #include ++#include ++#include + + extern void ltq_register_gpio(void); + extern void ltq_register_gpio_stp(void); +@@ -18,5 +20,9 @@ extern void ltq_register_ase_asc(void); + extern void ltq_register_etop(struct ltq_eth_data *eth); + extern void xway_register_nand(struct mtd_partition *parts, int count); + extern void ltq_register_vrx200(struct ltq_eth_data *eth); ++extern void ltq_register_gpio_ebu(unsigned int value); ++extern void ltq_register_spi(struct ltq_spi_platform_data *pdata, ++ struct spi_board_info const *info, unsigned n); ++extern void ltq_register_gpio_buttons(struct gpio_button *buttons, int cnt); + + #endif +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0014-MIPS-lantiq-enable-oprofile-support-on-lantiq-target.patch b/target/linux/lantiq/patches-3.3/0014-MIPS-lantiq-enable-oprofile-support-on-lantiq-target.patch deleted file mode 100644 index 409eba9a5e..0000000000 --- a/target/linux/lantiq/patches-3.3/0014-MIPS-lantiq-enable-oprofile-support-on-lantiq-target.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 4a6b5278deced0bd79df1521df291fe744c260b5 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Wed, 24 Aug 2011 13:28:55 +0200 -Subject: [PATCH 14/70] MIPS: lantiq: enable oprofile support on lantiq - targets - -This patch sets the performance counters irq and HAVE_OPROFILE flag for Lantiq -SoCs. - -Signed-off-by: John Crispin ---- - arch/mips/Kconfig | 1 + - arch/mips/lantiq/irq.c | 5 +++++ - 2 files changed, 6 insertions(+), 0 deletions(-) - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -229,6 +229,7 @@ config LANTIQ - select SWAP_IO_SPACE - select BOOT_RAW - select HAVE_CLK -+ select HAVE_OPROFILE - select MIPS_MACHINE - - config LASAT ---- a/arch/mips/lantiq/irq.c -+++ b/arch/mips/lantiq/irq.c -@@ -40,6 +40,9 @@ - - #define MAX_EIU 6 - -+/* the performance counter */ -+#define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31) -+ - /* irqs generated by device attached to the EBU need to be acked in - * a special manner - */ -@@ -317,6 +320,8 @@ void __init arch_init_irq(void) - set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 | - IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5); - #endif -+ -+ cp0_perfcount_irq = LTQ_PERF_IRQ; - } - - unsigned int __cpuinit get_c0_compare_int(void) diff --git a/target/linux/lantiq/patches-3.3/0014-import-compat-headers.patch b/target/linux/lantiq/patches-3.3/0014-import-compat-headers.patch new file mode 100644 index 0000000000..34c31bfac5 --- /dev/null +++ b/target/linux/lantiq/patches-3.3/0014-import-compat-headers.patch @@ -0,0 +1,82118 @@ +From a34f44106e933def9f66bfe0a806d7daa27ce387 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 6 Jul 2012 14:46:44 +0200 +Subject: [PATCH 14/25] import compat headers + +--- + arch/mips/include/asm/ifx/amazon_se/amazon_se.h | 1167 +++ + .../include/asm/ifx/amazon_se/amazon_se_admmod.h | 248 + + .../mips/include/asm/ifx/amazon_se/boards/Makefile | 13 + + .../asm/ifx/amazon_se/boards/amazon_se_admmod.c | 722 ++ + .../asm/ifx/amazon_se/boards/amazon_se_admmod.h | 248 + + .../asm/ifx/amazon_se/boards/amazon_se_ref_board.c | 437 ++ + .../asm/ifx/amazon_se/boards/amazon_se_ref_board.h | 55 + + .../mips/include/asm/ifx/amazon_se/boards/boards.h | 4 + + arch/mips/include/asm/ifx/amazon_se/irq.h | 116 + + arch/mips/include/asm/ifx/amazon_se/model.h | 54 + + arch/mips/include/asm/ifx/ar10/ar10.h | 1705 ++++ + arch/mips/include/asm/ifx/ar10/ar10_ref_board.h | 54 + + arch/mips/include/asm/ifx/ar10/emulation.h | 46 + + arch/mips/include/asm/ifx/ar10/irq.h | 214 + + arch/mips/include/asm/ifx/ar10/model.h | 54 + + arch/mips/include/asm/ifx/ar9/ar9.h | 1327 ++++ + arch/mips/include/asm/ifx/ar9/ar9_ref_board.h | 48 + + arch/mips/include/asm/ifx/ar9/irq.h | 176 + + arch/mips/include/asm/ifx/ar9/model.h | 54 + + arch/mips/include/asm/ifx/common_routines.h | 221 + + arch/mips/include/asm/ifx/danube/danube.h | 1442 ++++ + .../mips/include/asm/ifx/danube/danube_ref_board.h | 37 + + arch/mips/include/asm/ifx/danube/irq.h | 152 + + arch/mips/include/asm/ifx/danube/model.h | 54 + + arch/mips/include/asm/ifx/hn1/emulation.h | 40 + + arch/mips/include/asm/ifx/hn1/hn1.h | 1293 +++ + arch/mips/include/asm/ifx/hn1/hn1_eval_board.h | 36 + + arch/mips/include/asm/ifx/hn1/hn1_ref_board.h | 36 + + arch/mips/include/asm/ifx/hn1/irq.h | 183 + + arch/mips/include/asm/ifx/hn1/model.h | 28 + + arch/mips/include/asm/ifx/ifx_atm.h | 196 + + arch/mips/include/asm/ifx/ifx_board.h | 52 + + arch/mips/include/asm/ifx/ifx_clk.h | 140 + + arch/mips/include/asm/ifx/ifx_dcdc.h | 255 + + arch/mips/include/asm/ifx/ifx_dma_core.h | 316 + + arch/mips/include/asm/ifx/ifx_ebu_led.h | 76 + + arch/mips/include/asm/ifx/ifx_eth_framework.h | 90 + + arch/mips/include/asm/ifx/ifx_gpio.h | 428 + + arch/mips/include/asm/ifx/ifx_gptu.h | 239 + + arch/mips/include/asm/ifx/ifx_led.h | 331 + + arch/mips/include/asm/ifx/ifx_ledc.h | 351 + + arch/mips/include/asm/ifx/ifx_mmc_wlan.h | 311 + + arch/mips/include/asm/ifx/ifx_pmcu.h | 417 + + arch/mips/include/asm/ifx/ifx_pmon.h | 204 + + arch/mips/include/asm/ifx/ifx_pmu.h | 776 ++ + arch/mips/include/asm/ifx/ifx_ptm.h | 203 + + arch/mips/include/asm/ifx/ifx_rcu.h | 298 + + arch/mips/include/asm/ifx/ifx_regs.h | 262 + + arch/mips/include/asm/ifx/ifx_si.h | 246 + + arch/mips/include/asm/ifx/ifx_ssc.h | 242 + + arch/mips/include/asm/ifx/ifx_types.h | 217 + + arch/mips/include/asm/ifx/ifx_usif_spi.h | 247 + + arch/mips/include/asm/ifx/ifx_wdt.h | 118 + + arch/mips/include/asm/ifx/irq.h | 256 + + arch/mips/include/asm/ifx/model.h | 50 + + arch/mips/include/asm/ifx/vr9/emulation.h | 46 + + arch/mips/include/asm/ifx/vr9/irq.h | 196 + + arch/mips/include/asm/ifx/vr9/model.h | 54 + + arch/mips/include/asm/ifx/vr9/vr9.h | 1785 +++++ + arch/mips/include/asm/ifx/vr9/vr9_ref_board.h | 46 + + arch/mips/include/asm/ifx/war.h | 25 + + .../asm/mach-lantiq/falcon/cpu-feature-overrides.h | 58 + + arch/mips/include/asm/mach-lantiq/falcon/ebu_reg.h | 1520 ++++ + .../include/asm/mach-lantiq/falcon/gpon_reg_base.h | 376 + + arch/mips/include/asm/mach-lantiq/falcon/i2c_reg.h | 830 ++ + .../mips/include/asm/mach-lantiq/falcon/icu0_reg.h | 4324 ++++++++++ + .../include/asm/mach-lantiq/falcon/status_reg.h | 529 ++ + .../mips/include/asm/mach-lantiq/falcon/sys1_reg.h | 2008 +++++ + .../include/asm/mach-lantiq/falcon/sys_eth_reg.h | 1132 +++ + .../include/asm/mach-lantiq/falcon/sys_gpe_reg.h | 2829 +++++++ + arch/mips/include/asm/mach-lantiq/falcon/sysctrl.h | 60 + + include/linux/atm.h | 5 + + include/linux/pci.h | 1 + + include/linux/pci_ids.h | 8 + + include/net/ifx_ppa_api.h | 2606 +++++++ + include/net/ifx_ppa_api_common.h | 47 + + include/net/ifx_ppa_api_directpath.h | 301 + + include/net/ifx_ppa_hook.h | 1150 +++ + include/net/ifx_ppa_ppe_hal.h | 317 + + include/net/ifx_ppa_stack_al.h | 1559 ++++ + include/net/ipv6.h | 5 + + include/switch_api/AR9.h | 4342 +++++++++++ + include/switch_api/Tantos3G.h | 5882 ++++++++++++++ + include/switch_api/VR9_switch.h | 2637 +++++++ + include/switch_api/VR9_top.h | 798 ++ + include/switch_api/commonReg.h | 1312 ++++ + include/switch_api/gphy_fw.h | 20 + + include/switch_api/gphy_fw_fe.h | 8217 ++++++++++++++++++++ + include/switch_api/gphy_fw_ge.h | 8216 +++++++++++++++++++ + include/switch_api/ifx_ethsw.h | 3820 +++++++++ + include/switch_api/ifx_ethsw_PSB6970.h | 647 ++ + include/switch_api/ifx_ethsw_PSB6970_core.h | 182 + + include/switch_api/ifx_ethsw_PSB6970_ll.h | 1722 ++++ + include/switch_api/ifx_ethsw_api.h | 172 + + include/switch_api/ifx_ethsw_core_platform.h | 94 + + include/switch_api/ifx_ethsw_flow.h | 845 ++ + include/switch_api/ifx_ethsw_flow_core.h | 254 + + include/switch_api/ifx_ethsw_flow_ll.h | 2015 +++++ + include/switch_api/ifx_ethsw_init.h | 29 + + include/switch_api/ifx_ethsw_kernel_api.h | 80 + + include/switch_api/ifx_ethsw_linux.h | 64 + + include/switch_api/ifx_ethsw_ll_fkt.h | 41 + + include/switch_api/ifx_ethsw_pce.h | 385 + + include/switch_api/ifx_ethsw_pm.h | 63 + + include/switch_api/ifx_ethsw_pm_plat.h | 63 + + include/switch_api/ifx_ethsw_pm_pmcu.h | 36 + + include/switch_api/ifx_ethsw_ral.h | 56 + + include/switch_api/ifx_ethsw_reg_access.h | 38 + + include/switch_api/ifx_ethsw_rml.h | 49 + + include/switch_api/ifx_ethsw_vr9_reg_access.h | 23 + + include/switch_api/ifx_switch_ll.h | 101 + + include/switch_api/ifx_types.h | 118 + + include/switch_api/ifxmips_gphy_sw.h | 124 + + include/switch_api/ifxmips_sw_reg.h | 300 + + include/switch_api/regmapper.h | 27 + + 115 files changed, 81174 insertions(+), 0 deletions(-) + create mode 100644 arch/mips/include/asm/ifx/amazon_se/amazon_se.h + create mode 100644 arch/mips/include/asm/ifx/amazon_se/amazon_se_admmod.h + create mode 100644 arch/mips/include/asm/ifx/amazon_se/boards/Makefile + create mode 100644 arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_admmod.c + create mode 100644 arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_admmod.h + create mode 100644 arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_ref_board.c + create mode 100644 arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_ref_board.h + create mode 100644 arch/mips/include/asm/ifx/amazon_se/boards/boards.h + create mode 100644 arch/mips/include/asm/ifx/amazon_se/irq.h + create mode 100644 arch/mips/include/asm/ifx/amazon_se/model.h + create mode 100644 arch/mips/include/asm/ifx/ar10/ar10.h + create mode 100644 arch/mips/include/asm/ifx/ar10/ar10_ref_board.h + create mode 100644 arch/mips/include/asm/ifx/ar10/emulation.h + create mode 100644 arch/mips/include/asm/ifx/ar10/irq.h + create mode 100644 arch/mips/include/asm/ifx/ar10/model.h + create mode 100644 arch/mips/include/asm/ifx/ar9/ar9.h + create mode 100644 arch/mips/include/asm/ifx/ar9/ar9_ref_board.h + create mode 100644 arch/mips/include/asm/ifx/ar9/irq.h + create mode 100644 arch/mips/include/asm/ifx/ar9/model.h + create mode 100644 arch/mips/include/asm/ifx/common_routines.h + create mode 100644 arch/mips/include/asm/ifx/danube/danube.h + create mode 100644 arch/mips/include/asm/ifx/danube/danube_ref_board.h + create mode 100644 arch/mips/include/asm/ifx/danube/irq.h + create mode 100644 arch/mips/include/asm/ifx/danube/model.h + create mode 100644 arch/mips/include/asm/ifx/hn1/emulation.h + create mode 100644 arch/mips/include/asm/ifx/hn1/hn1.h + create mode 100644 arch/mips/include/asm/ifx/hn1/hn1_eval_board.h + create mode 100644 arch/mips/include/asm/ifx/hn1/hn1_ref_board.h + create mode 100644 arch/mips/include/asm/ifx/hn1/irq.h + create mode 100644 arch/mips/include/asm/ifx/hn1/model.h + create mode 100644 arch/mips/include/asm/ifx/ifx_atm.h + create mode 100644 arch/mips/include/asm/ifx/ifx_board.h + create mode 100644 arch/mips/include/asm/ifx/ifx_clk.h + create mode 100644 arch/mips/include/asm/ifx/ifx_dcdc.h + create mode 100644 arch/mips/include/asm/ifx/ifx_dma_core.h + create mode 100644 arch/mips/include/asm/ifx/ifx_ebu_led.h + create mode 100644 arch/mips/include/asm/ifx/ifx_eth_framework.h + create mode 100644 arch/mips/include/asm/ifx/ifx_gpio.h + create mode 100644 arch/mips/include/asm/ifx/ifx_gptu.h + create mode 100644 arch/mips/include/asm/ifx/ifx_led.h + create mode 100644 arch/mips/include/asm/ifx/ifx_ledc.h + create mode 100644 arch/mips/include/asm/ifx/ifx_mmc_wlan.h + create mode 100644 arch/mips/include/asm/ifx/ifx_pmcu.h + create mode 100644 arch/mips/include/asm/ifx/ifx_pmon.h + create mode 100644 arch/mips/include/asm/ifx/ifx_pmu.h + create mode 100644 arch/mips/include/asm/ifx/ifx_ptm.h + create mode 100644 arch/mips/include/asm/ifx/ifx_rcu.h + create mode 100644 arch/mips/include/asm/ifx/ifx_regs.h + create mode 100644 arch/mips/include/asm/ifx/ifx_si.h + create mode 100644 arch/mips/include/asm/ifx/ifx_ssc.h + create mode 100644 arch/mips/include/asm/ifx/ifx_types.h + create mode 100644 arch/mips/include/asm/ifx/ifx_usif_spi.h + create mode 100644 arch/mips/include/asm/ifx/ifx_wdt.h + create mode 100644 arch/mips/include/asm/ifx/irq.h + create mode 100644 arch/mips/include/asm/ifx/model.h + create mode 100644 arch/mips/include/asm/ifx/vr9/emulation.h + create mode 100644 arch/mips/include/asm/ifx/vr9/irq.h + create mode 100644 arch/mips/include/asm/ifx/vr9/model.h + create mode 100644 arch/mips/include/asm/ifx/vr9/vr9.h + create mode 100644 arch/mips/include/asm/ifx/vr9/vr9_ref_board.h + create mode 100644 arch/mips/include/asm/ifx/war.h + create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h + create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/ebu_reg.h + create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/gpon_reg_base.h + create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/i2c_reg.h + create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/icu0_reg.h + create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/status_reg.h + create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/sys1_reg.h + create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/sys_eth_reg.h + create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/sys_gpe_reg.h + create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/sysctrl.h + create mode 100644 include/net/ifx_ppa_api.h + create mode 100644 include/net/ifx_ppa_api_common.h + create mode 100644 include/net/ifx_ppa_api_directpath.h + create mode 100644 include/net/ifx_ppa_hook.h + create mode 100644 include/net/ifx_ppa_ppe_hal.h + create mode 100644 include/net/ifx_ppa_stack_al.h + create mode 100644 include/switch_api/AR9.h + create mode 100644 include/switch_api/Tantos3G.h + create mode 100644 include/switch_api/VR9_switch.h + create mode 100644 include/switch_api/VR9_top.h + create mode 100644 include/switch_api/commonReg.h + create mode 100644 include/switch_api/gphy_fw.h + create mode 100644 include/switch_api/gphy_fw_fe.h + create mode 100644 include/switch_api/gphy_fw_ge.h + create mode 100644 include/switch_api/ifx_ethsw.h + create mode 100644 include/switch_api/ifx_ethsw_PSB6970.h + create mode 100644 include/switch_api/ifx_ethsw_PSB6970_core.h + create mode 100644 include/switch_api/ifx_ethsw_PSB6970_ll.h + create mode 100644 include/switch_api/ifx_ethsw_api.h + create mode 100644 include/switch_api/ifx_ethsw_core_platform.h + create mode 100644 include/switch_api/ifx_ethsw_flow.h + create mode 100644 include/switch_api/ifx_ethsw_flow_core.h + create mode 100644 include/switch_api/ifx_ethsw_flow_ll.h + create mode 100644 include/switch_api/ifx_ethsw_init.h + create mode 100644 include/switch_api/ifx_ethsw_kernel_api.h + create mode 100644 include/switch_api/ifx_ethsw_linux.h + create mode 100644 include/switch_api/ifx_ethsw_ll_fkt.h + create mode 100644 include/switch_api/ifx_ethsw_pce.h + create mode 100644 include/switch_api/ifx_ethsw_pm.h + create mode 100644 include/switch_api/ifx_ethsw_pm_plat.h + create mode 100644 include/switch_api/ifx_ethsw_pm_pmcu.h + create mode 100644 include/switch_api/ifx_ethsw_ral.h + create mode 100644 include/switch_api/ifx_ethsw_reg_access.h + create mode 100644 include/switch_api/ifx_ethsw_rml.h + create mode 100644 include/switch_api/ifx_ethsw_vr9_reg_access.h + create mode 100644 include/switch_api/ifx_switch_ll.h + create mode 100644 include/switch_api/ifx_types.h + create mode 100644 include/switch_api/ifxmips_gphy_sw.h + create mode 100644 include/switch_api/ifxmips_sw_reg.h + create mode 100644 include/switch_api/regmapper.h + +diff --git a/arch/mips/include/asm/ifx/amazon_se/amazon_se.h b/arch/mips/include/asm/ifx/amazon_se/amazon_se.h +new file mode 100644 +index 0000000..af1c692 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/amazon_se/amazon_se.h +@@ -0,0 +1,1167 @@ ++/****************************************************************************** ++** ++** FILE NAME : amazon_se.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : header file for Amazon-SE ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef AMAZON_SE_H ++#define AMAZON_SE_H ++#include ++/****************************************************************************** ++ Copyright (c) 2002, Infineon Technologies. All rights reserved. ++ ++ No Warranty ++ Because the program is licensed free of charge, there is no warranty for ++ the program, to the extent permitted by applicable law. Except when ++ otherwise stated in writing the copyright holders and/or other parties ++ provide the program "as is" without warranty of any kind, either ++ expressed or implied, including, but not limited to, the implied ++ warranties of merchantability and fitness for a particular purpose. The ++ entire risk as to the quality and performance of the program is with ++ you. should the program prove defective, you assume the cost of all ++ necessary servicing, repair or correction. ++ ++ In no event unless required by applicable law or agreed to in writing ++ will any copyright holder, or any other party who may modify and/or ++ redistribute the program as permitted above, be liable to you for ++ damages, including any general, special, incidental or consequential ++ damages arising out of the use or inability to use the program ++ (including but not limited to loss of data or data being rendered ++ inaccurate or losses sustained by you or third parties or a failure of ++ the program to operate with any other programs), even if such holder or ++ other party has been advised of the possibility of such damages. ++******************************************************************************/ ++#define MACH_GROUP_IFX MACH_GROUP_AMAZON_SE ++#define MACH_TYPE_IFX MACH_AMAZON_SE ++ ++ ++#define IFX_MC_BASE (KSEG1 | 0x1F800000) ++#define IFX_MC_ERRCAUSE ((volatile u32*)(IFX_MC_BASE + 0x10)) ++#define IFX_MC_ERRADD ((volatile u32*)(IFX_MC_BASE + 0x20)) ++#define IFX_MC_PRIO ((volatile u32*)(IFX_MC_BASE + 0x50)) ++#define IFX_MC_CON ((volatile u32*)(IFX_MC_BASE + 0x60)) ++#define IFX_MC_SRAM0 ((volatile u32*)(IFX_MC_BASE + 0x100)) ++ ++/* This defers from Amazon_SE Hardware Users Manual Revision 1.0.pdf which is wrong */ ++#define IFX_MC_PRIO_AHB_SHIFT 6 ++#define IFX_MC_PRIO_FPI_SHIFT 8 ++#define IFX_MC_PRIO_DMA_SHIFT 2 ++#define IFX_MC_PRIO_2NDPRIOPORT_SHIFT 4 ++#define IFX_MC_PRIO_CPU0_SHIFT 0 ++ ++#define IFX_MC_PRIO_0 0 ++#define IFX_MC_PRIO_1 1 ++#define IFX_MC_PRIO_2 2 ++#define IFX_MC_PRIO_3 3 ++ ++ ++ ++/***********************************************************************/ ++/* Module : WDT register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_WDT (KSEG1 | 0x1F880000) ++ ++/***Watchdog Timer Control Register ***/ ++#define IFX_WDT_CR ((volatile u32*)(IFX_WDT + 0x03F0)) ++#define IFX_WDT_CR_GEN (1 << 31) ++#define IFX_WDT_CR_DSEN (1 << 30) ++#define IFX_WDT_CR_LPEN (1 << 29) ++#define IFX_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1)) ++#define IFX_WDT_CR_PWL_SET(value) (((( 1 << 2) - 1) & (value)) << 26) ++#define IFX_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1)) ++#define IFX_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24) ++#define IFX_WDT_CR_PW_GET(value) (((value) >> 16) & ((1 << 8) - 1)) ++#define IFX_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16) ++#define IFX_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1)) ++#define IFX_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0) ++ ++/***Watchdog Timer Status Register***/ ++#define IFX_WDT_SR ((volatile u32*)(IFX_WDT + 0x03F8)) ++#define IFX_WDT_SR_EN (1 << 31) ++#define IFX_WDT_SR_AE (1 << 30) ++#define IFX_WDT_SR_PRW (1 << 29) ++#define IFX_WDT_SR_EXP (1 << 28) ++#define IFX_WDT_SR_PWD (1 << 27) ++#define IFX_WDT_SR_DS (1 << 26) ++#define IFX_WDT_SR_VALUE_GET(value) (((value) >> 0) & ((1 << 16) - 1)) ++#define IFX_WDT_SR_VALUE_SET(value) (((( 1 << 16) - 1) & (value)) << 0) ++ ++/***********************************************************************/ ++/* Module : RCU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_RCU (KSEG1 | 0x1F203000) ++ ++#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) ++#define IFX_RCU_RST_STAT ((volatile u32*)(IFX_RCU + 0x0014)) ++#define IFX_USB_CFG ((volatile u32*)(IFX_RCU + 0x0018)) ++ ++#define IFX_RST_ALL (1 << 30) ++#define IFX_RCU_ARC_DFE_RESET (1 << 7) ++#define IFX_RCU_AHB_RESET (1 << 6) ++#define IFX_RCU_PPE_RESET (1 << 8) ++ ++/***Reset Request Register***/ ++#define IFX_RCU_RST_REQ_CPU0 (1 << 31) ++#define IFX_RCU_RST_REQ_CPU1 (1 << 3) ++#define IFX_RCU_RST_REQ_CPUSUB (1 << 29) ++#define IFX_RCU_RST_REQ_HRST (1 << 28) ++#define IFX_RCU_RST_REQ_WDT0 (1 << 27) ++#define IFX_RCU_RST_REQ_WDT1 (1 << 26) ++#define IFX_RCU_RST_REQ_CFG_GET(value) (((value) >> 23) & ((1 << 3) - 1)) ++#define IFX_RCU_RST_REQ_CFG_SET(value) (((( 1 << 3) - 1) & (value)) << 23) ++#define IFX_RCU_RST_REQ_MUX_ARC (1 << 23) ++#define IFX_RCU_RST_REQ_SWTBOOT (1 << 22) ++#define IFX_RCU_RST_REQ_DMA (1 << 21) ++#define IFX_RCU_RST_REQ_ARC_JTAG (1 << 29) ++#define IFX_RCU_RST_REQ_ETHPHY0 (1 << 19) ++#define IFX_RCU_RST_REQ_CPU0_BR (1 << 18) ++ ++#define IFX_RCU_RST_REQ_AFE (1 << 11) ++#define IFX_RCU_RST_REQ_DFE (1 << 7) ++ ++/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */ ++#define IFX_RCU_RST_REQ_ALL IFX_RST_ALL ++ ++ ++ ++/***********************************************************************/ ++/* Module : BCU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_BCU_BASE_ADDR (KSEG1 | 0x1E100000) ++#define IFX_SLAVE_BCU_BASE_ADDR (KSEG1 | 0x1C200400) ++ ++/***BCU Control Register (0010H)***/ ++#define IFX_BCU_CON ((volatile u32*)(0x0010 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_CON ((volatile u32*)(0x0010 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_STARVATION_MASK (0xFF << 24) ++#define IFX_BCU_STARVATION_SHIFT 24 ++#define IFX_BCU_TOUT_MASK 0xFFFF ++#define IFX_BCU_CON_SPC(value) (((( 1 << 8) - 1) & (value)) << 24) ++#define IFX_BCU_CON_SPE (1 << 19) ++#define IFX_BCU_CON_PSE (1 << 18) ++#define IFX_BCU_CON_DBG (1 << 16) ++#define IFX_BCU_CON_TOUT(value) (((( 1 << 16) - 1) & (value)) << 0) ++ ++ ++/***BCU Error Control Capture Register (0020H)***/ ++#define IFX_BCU_ECON ((volatile u32*)(0x0020 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_ECON ((volatile u32*)(0x0020 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_ECON_TAG(value) (((( 1 << 4) - 1) & (value)) << 24) ++#define IFX_BCU_ECON_RDN (1 << 23) ++#define IFX_BCU_ECON_WRN (1 << 22) ++#define IFX_BCU_ECON_SVM (1 << 21) ++#define IFX_BCU_ECON_ACK(value) (((( 1 << 2) - 1) & (value)) << 19) ++#define IFX_BCU_ECON_ABT (1 << 18) ++#define IFX_BCU_ECON_RDY (1 << 17) ++#define IFX_BCU_ECON_TOUT (1 << 16) ++#define IFX_BCU_ECON_ERRCNT(value) (((( 1 << 16) - 1) & (value)) << 0) ++#define IFX_BCU_ECON_OPC(value) (((( 1 << 4) - 1) & (value)) << 28) ++ ++/***BCU Error Address Capture Register (0024 H)***/ ++#define IFX_BCU_EADD ((volatile u32*)(0x0024 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_EADD ((volatile u32*)(0x0024 + IFX_SLAVE_BCU_BASE_ADDR)) ++ ++/***BCU Error Data Capture Register (0028H)***/ ++#define IFX_BCU_EDAT ((volatile u32*)(0x0028 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_EDAT ((volatile u32*)(0x0028 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_IRNICR ((volatile u32*)(0x00F8 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_IRNICR ((volatile u32*)(0x00F8 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_IRNCR ((volatile u32*)(0x00FC + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_IRNCR ((volatile u32*)(0x00FC + IFX_SLAVE_BCU_BASE_ADDR)) ++ ++ ++ ++/***********************************************************************/ ++/* Module : MEI register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_MEI_SPACE_ACCESS (KSEG1 | 0x1E116000) ++#define IFX_DFE_LDST_BASE_ADDR (KSEG1 | 0x1EF00000) ++ ++/*All mei related registers are defined in amazon_se_mei_bsp.h */ ++ ++ ++/***********************************************************************/ ++/* Module : GPIO register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_GPIO (KSEG1 | 0x1E100B00) ++ ++#define IFX_GPIO_Pn_BASE(n) (IFX_GPIO + 0x0010 + 0x0030 * (n)) ++ ++/***Port 0 Data Output Register (0010H)***/ ++#define IFX_GPIO_P0_OUT ((volatile u32 *)(IFX_GPIO + 0x0010)) ++/***Port 1 Data Output Register (0040H)***/ ++#define IFX_GPIO_P1_OUT ((volatile u32 *)(IFX_GPIO + 0x0040)) ++/***Port 0 Data Input Register (0014H)***/ ++#define IFX_GPIO_P0_IN ((volatile u32 *)(IFX_GPIO + 0x0014)) ++/***Port 1 Data Input Register (0044H)***/ ++#define IFX_GPIO_P1_IN ((volatile u32 *)(IFX_GPIO + 0x0044)) ++/***Port 0 Direction Register (0018H)***/ ++#define IFX_GPIO_P0_DIR ((volatile u32 *)(IFX_GPIO + 0x0018)) ++/***Port 1 Direction Register (0048H)***/ ++#define IFX_GPIO_P1_DIR ((volatile u32 *)(IFX_GPIO + 0x0048)) ++/***Port 0 Alternate Function Select Register 0 (001C H) ***/ ++#define IFX_GPIO_P0_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x001C)) ++/***Port 1 Alternate Function Select Register 0 (004C H) ***/ ++#define IFX_GPIO_P1_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x004C)) ++/***Port 0 Alternate Function Select Register 1 (0020 H) ***/ ++#define IFX_GPIO_P0_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0020)) ++/***Port 1 Alternate Function Select Register 0 (0050 H) ***/ ++#define IFX_GPIO_P1_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0050)) ++/***Port 0 Open Drain Control Register (0024H)***/ ++#define IFX_GPIO_P0_OD ((volatile u32 *)(IFX_GPIO + 0x0024)) ++/***Port 1 Open Drain Control Register (0054H)***/ ++#define IFX_GPIO_P1_OD ((volatile u32 *)(IFX_GPIO + 0x0054)) ++/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/ ++#define IFX_GPIO_P0_STOFF ((volatile u32 *)(IFX_GPIO + 0x0028)) ++/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/ ++#define IFX_GPIO_P1_STOFF ((volatile u32 *)(IFX_GPIO + 0x0058)) ++/***Port 0 Pull Up/Pull Down Select Register (002C H)***/ ++#define IFX_GPIO_P0_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x002C)) ++/***Port 1 Pull Up/Pull Down Select Register (005C H)***/ ++#define IFX_GPIO_P1_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x005C)) ++/***Port 0 Pull Up Device Enable Register (0030 H)***/ ++#define IFX_GPIO_P0_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0030)) ++/***Port 1 Pull Up Device Enable Register (0060 H)***/ ++#define IFX_GPIO_P1_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0060)) ++ ++ ++ ++/***********************************************************************/ ++/* Module : CGU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_CGU (KSEG1 | 0x1F103000) ++ ++/***CGU Clock PLL0 ***/ ++#define IFX_CGU_PLL0_CFG ((volatile u32*)(IFX_CGU + 0x0004)) ++/***CGU Clock PLL1 ***/ ++#define IFX_CGU_PLL1_CFG ((volatile u32*)(IFX_CGU + 0x0008)) ++/***CGU Clock PLL2 ***/ ++#define IFX_CGU_PLL2_CFG ((volatile u32*)(IFX_CGU + 0x000C)) ++/***CGU Clock SYS Mux Register***/ ++#define IFX_CGU_SYS ((volatile u32*)(IFX_CGU + 0x0010)) ++/***CGU Interface Clock Control Register***/ ++#define IFX_CGU_IF_CLK ((volatile u32*)(IFX_CGU + 0x0018)) ++/***CGU Osc Control ***/ ++#define IFX_CGU_OSC_CON ((volatile u32*)(IFX_CGU + 0x001c)) ++ ++#define IFX_CGU_PCI_CR ((volatile u32*)(IFX_CGU + 0x0034)) ++ ++ ++ ++/***********************************************************************/ ++/* Module : MCD register address and bits */ ++/***********************************************************************/ ++#define IFX_MCD (KSEG1 | 0x1F106000) ++ ++/***Manufacturer Identification Register***/ ++#define IFX_MCD_MANID ((volatile u32*)(IFX_MCD+ 0x0024)) ++#define IFX_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5) ++ ++/***Chip Identification Register***/ ++#define IFX_MCD_CHIPID ((volatile u32*)(IFX_MCD+ 0x0028)) ++#define IFX_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) ++#define IFX_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) ++#define IFX_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1)) ++#define IFX_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12) ++#define IFX_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1)) ++#define IFX_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1) ++ ++#define IFX_CHIPID_STANDARD 0x00EB ++#define IFX_CHIPID_YANGTSE 0x00ED ++ ++/***Redesign Tracing Identification Register***/ ++#define IFX_MCD_RTID ((volatile u32*)(IFX_MCD+ 0x002C)) ++#define IFX_MCD_RTID_LC (1 << 15) ++#define IFX_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0) ++ ++#define IFX_FUSE_BASE_ADDR (KSEG1 | 0x1F107354) ++ ++ ++/***********************************************************************/ ++/* Module : EBU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_EBU (KSEG1 | 0x1E105300) ++ ++/***EBU Clock Control Register***/ ++#define IFX_EBU_CLC ((volatile u32*)(IFX_EBU + 0x0000)) ++#define IFX_EBU_CLC_DISS (1 << 1) ++#define IFX_EBU_CLC_DISR (1 << 0) ++ ++/***EBU Global Control Register***/ ++#define IFX_EBU_CON ((volatile u32 *)(IFX_EBU + 0x0010)) ++#define IFX_EBU_CON0 ((volatile u32 *)(IFX_EBU + 0x0060)) ++#define IFX_EBU_CON1 ((volatile u32 *)(IFX_EBU + 0x0064)) ++ ++#define IFX_EBU_CON_EBU_TA_MASK 7 ++#define IFX_EBU_CON_EBU_TA_SHIFT 29 ++#define IFX_EBU_CON_DTACS(value) (((( 1 << 3) - 1) & (value)) << 20) ++#define IFX_EBU_CON_DTARW(value) (((( 1 << 3) - 1) & (value)) << 16) ++#define IFX_EBU_CON_TOUTC(value) (((( 1 << 8) - 1) & (value)) << 8) ++#define IFX_EBU_CON_ARBMODE(value) (((( 1 << 2) - 1) & (value)) << 6) ++#define IFX_EBU_CON_ARBSYNC (1 << 5) ++#define IFX_EBU_CON_1 (1 << 3) ++ ++/* IFX_EBU_CON0 */ ++#define IFX_EBU_CON0_WAITWRC_MASK 0xF00 ++#define IFX_EBU_CON0_WAITWRC_SHIFT 8 ++#define IFX_EBU_CON0_WAITRDC_MASK 0xC0 ++#define IFX_EBU_CON0_WAITRDC_SHIFT 6 ++#define IFX_EBU_CON0_RECOVC_MASK 0xC ++#define IFX_EBU_CON0_CMULT_MASK 3 ++#define IFX_EBU_CON0_CMULT_SHIFT 0 ++#define IFX_EBU_CON0_WRDIS (1 << 31) ++ ++/***EBU Address Select Register 0***/ ++#define IFX_EBU_ADDSEL0 ((volatile u32*)(IFX_EBU + 0x0020)) ++#define IFX_EBU_ADDSEL0_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) ++#define IFX_EBU_ADDSEL0_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_EBU_ADDSEL0_MIRRORE (1 << 1) ++#define IFX_EBU_ADDSEL0_REGEN (1 << 0) ++ ++/***EBU Address Select Register 1***/ ++#define IFX_EBU_ADDSEL1 ((volatile u32*)(IFX_EBU + 0x0024)) ++#define IFX_EBU_ADDSEL1_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) ++#define IFX_EBU_ADDSEL1_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_EBU_ADDSEL1_MIRRORE (1 << 1) ++#define IFX_EBU_ADDSEL1_REGEN (1 << 0) ++ ++/***EBU Address Select Register 2***/ ++#define IFX_EBU_ADDSEL2 ((volatile u32*)(IFX_EBU + 0x0028)) ++#define IFX_EBU_ADDSEL2_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) ++#define IFX_EBU_ADDSEL2_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_EBU_ADDSEL2_MIRRORE (1 << 1) ++#define IFX_EBU_ADDSEL2_REGEN (1 << 0) ++ ++/***EBU Address Select Register 3***/ ++#define IFX_EBU_ADDSEL3 ((volatile u32*)(IFX_EBU + 0x0028)) ++#define IFX_EBU_ADDSEL3_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) ++#define IFX_EBU_ADDSEL3_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_EBU_ADDSEL3_MIRRORE (1 << 1) ++#define IFX_EBU_ADDSEL3_REGEN (1 << 0) ++ ++/***EBU Bus Configuration Register 0***/ ++#define IFX_EBU_BUSCON0 ((volatile u32*)(IFX_EBU + 0x0060)) ++#define IFX_EBU_BUSCON0_CMULT 0x00000003 ++#define IFX_EBU_BUSCON0_CMULT_S 0 ++enum { ++ IFX_EBU_BUSCON0_CMULT1 = 0, ++ IFX_EBU_BUSCON0_CMULT4, ++ IFX_EBU_BUSCON0_CMULT8, ++ IFX_EBU_BUSCON0_CMULT16, /* Default after reset */ ++}; ++ ++#define IFX_EBU_BUSCON0_RECOVC 0x00000000c ++#define IFX_EBU_BUSCON0_RECOVC_S 2 ++enum { ++ IFX_EBU_BUSCON0_RECOVC0 = 0, ++ IFX_EBU_BUSCON0_RECOVC1, ++ IFX_EBU_BUSCON0_RECOVC2, ++ IFX_EBU_BUSCON0_RECOVC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON0_HOLDC 0x00000030 ++#define IFX_EBU_BUSCON0_HOLDC_S 4 ++enum { ++ IFX_EBU_BUSCON0_HOLDC0 = 0, ++ IFX_EBU_BUSCON0_HOLDC1, ++ IFX_EBU_BUSCON0_HOLDC2, ++ IFX_EBU_BUSCON0_HOLDC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON0_WAITRDC 0x000000c0 ++#define IFX_EBU_BUSCON0_WAITRDC_S 6 ++enum { ++ IFX_EBU_BUSCON0_WAITRDC0 = 0, ++ IFX_EBU_BUSCON0_WAITRDC1, ++ IFX_EBU_BUSCON0_WAITRDC2, ++ IFX_EBU_BUSCON0_WAITRDC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON0_WAITWRC 0x00000700 ++#define IFX_EBU_BUSCON0_WAITWRC_S 8 ++enum { ++ IFX_EBU_BUSCON0_WAITWRC0 = 0, ++ IFX_EBU_BUSCON0_WAITWRC1, ++ IFX_EBU_BUSCON0_WAITWRC2, ++ IFX_EBU_BUSCON0_WAITWRC3, ++ IFX_EBU_BUSCON0_WAITWRC4, ++ IFX_EBU_BUSCON0_WAITWRC5, ++ IFX_EBU_BUSCON0_WAITWRC6, ++ IFX_EBU_BUSCON0_WAITWRC7, /* Default */ ++}; ++ ++#define IFX_EBU_BUSCON0_BCGEN 0x00003000 ++#define IFX_EBU_BUSCON0_BCGEN_S 12 ++enum { ++ IFX_EBU_BUSCON0_BCGEN_CS = 0, ++ IFX_EBU_BUSCON0_BCGEN_INTEL, /* Default */ ++ IFX_EBU_BUSCON0_BCGEN_MOTOROLA, ++ IFX_EBU_BUSCON0_BCGEN_RES, ++}; ++ ++#define IFX_EBU_BUSCON0_ALEC 0x0000c000 ++#define IFX_EBU_BUSCON0_ALEC_S 14 ++enum { ++ IFX_EBU_BUSCON0_ALEC0 = 0, ++ IFX_EBU_BUSCON0_ALEC1, ++ IFX_EBU_BUSCON0_ALEC2, ++ IFX_EBU_BUSCON0_ALEC3, /* Default */ ++}; ++ ++#define IFX_EBU_BUSCON0_XDM 0x00030000 ++#define IFX_EBU_BUSCON0_XDM_S 16 ++enum { ++ IFX_EBU_BUSCON0_XDM8 = 0, ++ IFX_EBU_BUSCON0_XDM16, /* Default */ ++}; ++ ++#define IFX_EBU_BUSCON0_VN_EN 0x00040000 ++ ++#define IFX_EBU_BUSCON0_WAITINV_HI 0x00080000 /* low by default */ ++ ++#define IFX_EBU_BUSCON0_WAIT 0x00300000 ++#define IFX_EBU_BUSCON0_WAIT_S 20 ++enum { ++ IFX_EBU_BUSCON0_WAIT_DISABLE = 0, ++ IFX_EBU_BUSCON0_WAIT_ASYNC, ++ IFX_EBU_BUSCON0_WAIT_SYNC, ++}; ++#define IFX_EBU_BUSCON0_SETUP_EN 0x00400000 /* Disable by default */ ++ ++#define IFX_EBU_BUSCON0_AGEN 0x07000000 ++#define IFX_EBU_BUSCON0_AGEN_S 24 ++enum { ++ IFX_EBU_BUSCON0_AGEN_DEMUX = 0, /* Default */ ++ IFX_EBU_BUSCON0_AGEN_RES, ++ IFX_EBU_BUSCON0_AGEN_MUX, ++}; ++ ++#define IFX_EBU_BUSCON0_PG_EN 0x20000000 ++#define IFX_EBU_BUSCON0_ADSWP 0x40000000 /* Disable by default */ ++#define IFX_EBU_BUSCON0_WRDIS 0x80000000 /* Disable by default */ ++ ++ ++/***EBU Bus Configuration Register 1***/ ++#define IFX_EBU_BUSCON1 ((volatile u32*)(IFX_EBU + 0x0064)) ++#define IFX_EBU_BUSCON1_WRDIS (1 << 31) ++//#define IFX_EBU_BUSCON1_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) ++//#define IFX_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) ++//#define IFX_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) ++//#define IFX_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) ++//#define IFX_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) ++//#define IFX_EBU_BUSCON1_WAITINV (1 << 19) ++//#define IFX_EBU_BUSCON1_SETUP (1 << 18) ++//#define IFX_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) ++//#define IFX_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) ++//#define IFX_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) ++//#define IFX_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) ++//#define IFX_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) ++//#define IFX_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) ++#define IFX_EBU_BUSCON1_SETUP (1 << 22) ++#define IFX_EBU_BUSCON1_CMULT 0x00000003 ++#define IFX_EBU_BUSCON1_CMULT_S 0 ++enum { ++ IFX_EBU_BUSCON1_CMULT1 = 0, ++ IFX_EBU_BUSCON1_CMULT4, ++ IFX_EBU_BUSCON1_CMULT8, ++ IFX_EBU_BUSCON1_CMULT16, /* Default after reset */ ++ }; ++ ++#define IFX_EBU_BUSCON1_RECOVC 0x00000000c ++#define IFX_EBU_BUSCON1_RECOVC_S 2 ++enum { ++ IFX_EBU_BUSCON1_RECOVC0 = 0, ++ IFX_EBU_BUSCON1_RECOVC1, ++ IFX_EBU_BUSCON1_RECOVC2, ++ IFX_EBU_BUSCON1_RECOVC3, /* Default */ ++ }; ++ ++#define IFX_EBU_BUSCON1_HOLDC 0x00000030 ++#define IFX_EBU_BUSCON1_HOLDC_S 4 ++enum { ++ IFX_EBU_BUSCON1_HOLDC0 = 0, ++ IFX_EBU_BUSCON1_HOLDC1, ++ IFX_EBU_BUSCON1_HOLDC2, ++ IFX_EBU_BUSCON1_HOLDC3, /* Default */ ++ }; ++ ++ ++#define IFX_EBU_BUSCON1_WAITRDC 0x000000c0 ++#define IFX_EBU_BUSCON1_WAITRDC_S 6 ++enum { ++ IFX_EBU_BUSCON1_WAITRDC0 = 0, ++ IFX_EBU_BUSCON1_WAITRDC1, ++ IFX_EBU_BUSCON1_WAITRDC2, ++ IFX_EBU_BUSCON1_WAITRDC3, /* Default */ ++ }; ++#define IFX_EBU_BUSCON1_WAITWRC 0x00000700 ++#define IFX_EBU_BUSCON1_WAITWRC_S 8 ++enum { ++ IFX_EBU_BUSCON1_WAITWRC0 = 0, ++ IFX_EBU_BUSCON1_WAITWRC1, ++ IFX_EBU_BUSCON1_WAITWRC2, ++ IFX_EBU_BUSCON1_WAITWRC3, ++ IFX_EBU_BUSCON1_WAITWRC4, ++ IFX_EBU_BUSCON1_WAITWRC5, ++ IFX_EBU_BUSCON1_WAITWRC6, ++ IFX_EBU_BUSCON1_WAITWRC7, /* Default */ ++ }; ++ ++#define IFX_EBU_BUSCON1_BCGEN 0x00003000 ++#define IFX_EBU_BUSCON1_BCGEN_S 12 ++enum { ++ IFX_EBU_BUSCON1_BCGEN_CS = 0, ++ IFX_EBU_BUSCON1_BCGEN_INTEL, /* Default */ ++ IFX_EBU_BUSCON1_BCGEN_MOTOROLA, ++ IFX_EBU_BUSCON1_BCGEN_RES, ++ }; ++ ++ ++#define IFX_EBU_BUSCON1_ALEC 0x0000c000 ++#define IFX_EBU_BUSCON1_ALEC_S 14 ++enum { ++ IFX_EBU_BUSCON1_ALEC0 = 0, ++ IFX_EBU_BUSCON1_ALEC1, ++ IFX_EBU_BUSCON1_ALEC2, ++ IFX_EBU_BUSCON1_ALEC3, /* Default */ ++ }; ++ ++ ++ ++ ++/***EBU Bus Configuration Register 2***/ ++#define IFX_EBU_BUSCON2 ((volatile u32*)(IFX_EBU + 0x0068)) ++#define IFX_EBU_BUSCON2_WRDIS (1 << 31) ++#define IFX_EBU_BUSCON2_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) ++#define IFX_EBU_BUSCON2_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) ++#define IFX_EBU_BUSCON2_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) ++#define IFX_EBU_BUSCON2_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) ++#define IFX_EBU_BUSCON2_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) ++#define IFX_EBU_BUSCON2_WAITINV (1 << 19) ++#define IFX_EBU_BUSCON2_SETUP (1 << 18) ++#define IFX_EBU_BUSCON2_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) ++#define IFX_EBU_BUSCON2_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) ++#define IFX_EBU_BUSCON2_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) ++#define IFX_EBU_BUSCON2_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) ++#define IFX_EBU_BUSCON2_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) ++#define IFX_EBU_BUSCON2_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) ++ ++#define IFX_EBU_PCC_CON ((volatile u32*)(IFX_EBU + 0x0090)) ++#define IFX_EBU_PCC_STAT ((volatile u32*)(IFX_EBU + 0x0094)) ++#define IFX_EBU_PCC_ISTAT ((volatile u32*)(IFX_EBU + 0x00A0)) ++#define IFX_EBU_PCC_IEN ((volatile u32*)(IFX_EBU + 0x00A4)) ++ ++ ++/* NAND Flash Controller control Register */ ++#define IFX_EBU_NAND_CON (volatile u32*)(IFX_EBU + 0xB0) ++#define IFX_EBU_NAND_CON_NANDM (1<<0) ++#define IFX_EBU_NAND_CON_NANDM_S 0 ++ ++enum { ++ IFX_EBU_NAND_CON_NANDM_DISABLE = 0,/* Default after reset */ ++ IFX_EBU_NAND_CON_NANDM_ENABLE, ++ }; ++ ++#define IFX_EBU_NAND_CON_CSMUX_E (1<<1) ++#define IFX_EBU_NAND_CON_CSMUX_E_S 1 ++enum { ++ IFX_EBU_NAND_CON_CSMUX_E_DISABLE = 0,/* Default after reset */ ++ IFX_EBU_NAND_CON_CSMUX_E_ENABLE, ++ }; ++ ++#define IFX_EBU_NAND_CON_CS_P (1<<4) ++#define IFX_EBU_NAND_CON_CS_P_S 4 ++enum { ++ IFX_EBU_NAND_CON_CS_P_HIGH = 0, ++ IFX_EBU_NAND_CON_CS_P_LOW, /* Default after reset */ ++ }; ++ ++#define IFX_EBU_NAND_CON_SE_P (1<<5) ++#define IFX_EBU_NAND_CON_SE_P_S 5 ++enum { ++ IFX_EBU_NAND_CON_SE_P_HIGH = 0, ++ IFX_EBU_NAND_CON_SE_P_LOW, /* Default after reset */ ++ }; ++ ++#define IFX_EBU_NAND_CON_WP_P (1<<6) ++#define IFX_EBU_NAND_CON_WP_P_S 6 ++enum { ++ IFX_EBU_NAND_CON_WP_P_HIGH = 0, ++ IFX_EBU_NAND_CON_WP_P_LOW, /* Default after reset */ ++ }; ++ ++#define IFX_EBU_NAND_CON_PRE_P (1<<7) ++#define IFX_EBU_NAND_CON_PRE_P_S 7 ++enum { ++ IFX_EBU_NAND_CON_PRE_P_HIGH = 0, ++ IFX_EBU_NAND_CON_PRE_P_LOW, /* Default after reset */ ++ }; ++ ++#define IFX_EBU_NAND_CON_IN_CS (3<<8) ++#define IFX_EBU_NAND_CON_IN_CS_S 8 ++enum { ++ IFX_EBU_NAND_CON_IN_CS0 = 0, /* Default after reset */ ++ IFX_EBU_NAND_CON_IN_CS1, ++ }; ++ ++#define IFX_EBU_NAND_CON_OUT_CS (3<<10) ++#define IFX_EBU_NAND_CON_OUT_CS_S 10 ++enum { ++ IFX_EBU_NAND_CON_OUT_CS0 = 0, /* Default after reset */ ++ IFX_EBU_NAND_CON_OUT_CS1, ++ }; ++ ++ ++ ++/* NAND Flash Device RD/BY State Register */ ++#define IFX_EBU_NAND_WAIT (volatile u32*)(IFX_EBU + 0xB4) ++#define IFX_EBU_NAND_WAIT_RD (0x1) ++#define IFX_EBU_NAND_WAIT_BY_E (1<<1) ++#define IFX_EBU_NAND_WAIT_RD_E (1<<2) ++#define IFX_EBU_NAND_WAIT_WR_C (1<<3) ++ ++#define IFX_EBU_NAND_ECC0 (volatile u32*)(IFX_EBU + 0xB8) ++#define IFX_EBU_NAND_ECC_AC (volatile u32*)(IFX_EBU + 0xBC) ++ ++ ++ ++ ++/***********************************************************************/ ++/* Module : SDRAM register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_SDRAM (KSEG1 | 0x1F800000) ++ ++/***MC Access Error Cause Register***/ ++#define IFX_SDRAM_MC_ERRCAUSE ((volatile u32*)(IFX_SDRAM + 0x0100)) ++#define IFX_SDRAM_MC_ERRCAUSE_ERR (1 << 31) ++#define IFX_SDRAM_MC_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16) ++#define IFX_SDRAM_MC_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_ERRCAUSE_Res(value) (((( 1 << NaN) - 1) & (value)) << NaN) ++ ++/***MC Access Error Address Register***/ ++#define IFX_SDRAM_MC_ERRADDR ((volatile u32*)(IFX_SDRAM + 0x0108)) ++ ++/***MC I/O General Purpose Register***/ ++#define IFX_SDRAM_MC_IOGP ((volatile u32*)(IFX_SDRAM + 0x0800)) ++#define IFX_SDRAM_MC_IOGP_GPR6(value) (((( 1 << 4) - 1) & (value)) << 28) ++#define IFX_SDRAM_MC_IOGP_GPR5(value) (((( 1 << 4) - 1) & (value)) << 24) ++#define IFX_SDRAM_MC_IOGP_GPR4(value) (((( 1 << 4) - 1) & (value)) << 20) ++#define IFX_SDRAM_MC_IOGP_GPR3(value) (((( 1 << 4) - 1) & (value)) << 16) ++#define IFX_SDRAM_MC_IOGP_GPR2(value) (((( 1 << 4) - 1) & (value)) << 12) ++#define IFX_SDRAM_MC_IOGP_CPS (1 << 11) ++#define IFX_SDRAM_MC_IOGP_CLKDELAY(value) (((( 1 << 3) - 1) & (value)) << 8) ++#define IFX_SDRAM_MC_IOGP_CLKRAT(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_IOGP_RDDEL(value) (((( 1 << 4) - 1) & (value)) << 0) ++ ++/***MC Self Refresh Register***/ ++#define IFX_SDRAM_MC_SELFRFSH ((volatile u32*)(IFX_SDRAM + 0x0A00)) ++#define IFX_SDRAM_MC_SELFRFSH_PWDS (1 << 1) ++#define IFX_SDRAM_MC_SELFRFSH_PWD (1 << 0) ++#define IFX_SDRAM_MC_SELFRFSH_Res(value) (((( 1 << 30) - 1) & (value)) << 2) ++ ++/***MC Enable Register***/ ++#define IFX_SDRAM_MC_CTRLENA ((volatile u32*)(IFX_SDRAM + 0x1000)) ++#define IFX_SDRAM_MC_CTRLENA_ENA (1 << 0) ++#define IFX_SDRAM_MC_CTRLENA_Res(value) (((( 1 << 31) - 1) & (value)) << 1) ++ ++/***MC Mode Register Setup Code***/ ++#define IFX_SDRAM_MC_MRSCODE ((volatile u32*)(IFX_SDRAM + 0x1008)) ++#define IFX_SDRAM_MC_MRSCODE_UMC(value) (((( 1 << 5) - 1) & (value)) << 7) ++#define IFX_SDRAM_MC_MRSCODE_CL(value) (((( 1 << 3) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_MRSCODE_WT (1 << 3) ++#define IFX_SDRAM_MC_MRSCODE_BL(value) (((( 1 << 3) - 1) & (value)) << 0) ++ ++/***MC Configuration Data-word Width Register***/ ++#define IFX_SDRAM_MC_CFGDW ((volatile u32*)(IFX_SDRAM + 0x1010)) ++#define IFX_SDRAM_MC_CFGDW_DW(value) (((( 1 << 4) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_CFGDW_Res(value) (((( 1 << 28) - 1) & (value)) << 4) ++ ++/***MC Configuration Physical Bank 0 Register***/ ++#define IFX_SDRAM_MC_CFGPB0 ((volatile u32*)(IFX_SDRAM + 0x1018)) ++#define IFX_SDRAM_MC_CFGPB0_MCSEN0(value) (((( 1 << 4) - 1) & (value)) << 12) ++#define IFX_SDRAM_MC_CFGPB0_BANKN0(value) (((( 1 << 4) - 1) & (value)) << 8) ++#define IFX_SDRAM_MC_CFGPB0_ROWW0(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_CFGPB0_COLW0(value) (((( 1 << 4) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_CFGPB0_Res(value) (((( 1 << 16) - 1) & (value)) << 16) ++ ++/***MC Latency Register***/ ++#define IFX_SDRAM_MC_LATENCY ((volatile u32*)(IFX_SDRAM + 0x1038)) ++#define IFX_SDRAM_MC_LATENCY_TRP(value) (((( 1 << 4) - 1) & (value)) << 16) ++#define IFX_SDRAM_MC_LATENCY_TRAS(value) (((( 1 << 4) - 1) & (value)) << 12) ++#define IFX_SDRAM_MC_LATENCY_TRCD(value) (((( 1 << 4) - 1) & (value)) << 8) ++#define IFX_SDRAM_MC_LATENCY_TDPL(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_LATENCY_TDAL(value) (((( 1 << 4) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_LATENCY_Res(value) (((( 1 << 12) - 1) & (value)) << 20) ++ ++/***MC Refresh Cycle Time Register***/ ++#define IFX_SDRAM_MC_TREFRESH ((volatile u32*)(IFX_SDRAM + 0x1040)) ++#define IFX_SDRAM_MC_TREFRESH_TREF(value) (((( 1 << 13) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_TREFRESH_Res(value) (((( 1 << 19) - 1) & (value)) << 13) ++ ++/***********************************************************************/ ++/* Module : ASC1 register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_ASC1 (KSEG1 | 0x1E100C00) ++ ++/***ASC Clock Control Register***/ ++#define IFX_ASC1_CLC ((volatile u32*)(IFX_ASC1 + 0x0000)) ++#define IFX_ASC1_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) ++#define IFX_ASC1_CLC_DISS (1 << 1) ++#define IFX_ASC1_CLC_DISR (1 << 0) ++ ++/***ASC Port Input Select Register***/ ++#define IFX_ASC1_PISEL ((volatile u32*)(IFX_ASC1 + 0x0004)) ++#define IFX_ASC1_PISEL ((volatile u32*)(IFX_ASC1 + 0x0004)) ++#define IFX_ASC1_PISEL_RIS (1 << 0) ++ ++/***ASC Control Register***/ ++#define IFX_ASC1_CON ((volatile u32*)(IFX_ASC1 + 0x0010)) ++#define IFX_ASC1_CON_BEN (1 << 20) ++#define IFX_ASC1_CON_TOEN (1 << 20) ++#define IFX_ASC1_CON_ROEN (1 << 19) ++#define IFX_ASC1_CON_RUEN (1 << 18) ++#define IFX_ASC1_CON_FEN (1 << 17) ++#define IFX_ASC1_CON_PAL (1 << 16) ++#define IFX_ASC1_CON_R (1 << 15) ++#define IFX_ASC1_CON_ACO (1 << 14) ++#define IFX_ASC1_CON_LB (1 << 13) ++#define IFX_ASC1_CON_ERCLK (1 << 10) ++#define IFX_ASC1_CON_FDE (1 << 9) ++#define IFX_ASC1_CON_BRS (1 << 8) ++#define IFX_ASC1_CON_STP (1 << 7) ++#define IFX_ASC1_CON_SP (1 << 6) ++#define IFX_ASC1_CON_ODD (1 << 5) ++#define IFX_ASC1_CON_PEN (1 << 4) ++#define IFX_ASC1_CON_M(value) (((( 1 << 3) - 1) & (value)) << 0) ++ ++/***ASC Staus Register***/ ++#define IFX_ASC1_STATE ((volatile u32*)(IFX_ASC1 + 0x0014)) ++/***ASC Write Hardware Modified Control Register***/ ++#define IFX_ASC1_WHBSTATE ((volatile u32*)(IFX_ASC1 + 0x0018)) ++#define IFX_ASC1_WHBSTATE_SETBE (1 << 113) ++#define IFX_ASC1_WHBSTATE_SETTOE (1 << 12) ++#define IFX_ASC1_WHBSTATE_SETROE (1 << 11) ++#define IFX_ASC1_WHBSTATE_SETRUE (1 << 10) ++#define IFX_ASC1_WHBSTATE_SETFE (1 << 19) ++#define IFX_ASC1_WHBSTATE_SETPE (1 << 18) ++#define IFX_ASC1_WHBSTATE_CLRBE (1 << 17) ++#define IFX_ASC1_WHBSTATE_CLRTOE (1 << 6) ++#define IFX_ASC1_WHBSTATE_CLRROE (1 << 5) ++#define IFX_ASC1_WHBSTATE_CLRRUE (1 << 4) ++#define IFX_ASC1_WHBSTATE_CLRFE (1 << 3) ++#define IFX_ASC1_WHBSTATE_CLRPE (1 << 2) ++#define IFX_ASC1_WHBSTATE_SETREN (1 << 1) ++#define IFX_ASC1_WHBSTATE_CLRREN (1 << 0) ++ ++/***ASC Baudrate Timer/Reload Register***/ ++#define IFX_ASC1_BG ((volatile u32*)(IFX_ASC1 + 0x0050)) ++#define IFX_ASC1_BG_BR_VALUE(value) (((( 1 << 13) - 1) & (value)) << 0) ++ ++/***ASC Fractional Divider Register***/ ++#define IFX_ASC1_FDV ((volatile u32*)(IFX_ASC1 + 0x0018)) ++#define IFX_ASC1_FDV_FD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) ++ ++/***ASC Transmit Buffer Register***/ ++#define IFX_ASC1_TBUF ((volatile u32*)(IFX_ASC1 + 0x0020)) ++#define IFX_ASC1_TBUF_TD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) ++ ++/***ASC Receive Buffer Register***/ ++#define IFX_ASC1_RBUF ((volatile u32*)(IFX_ASC1 + 0x0024)) ++#define IFX_ASC1_RBUF_RD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) ++ ++/***ASC Autobaud Control Register***/ ++#define IFX_ASC1_ABCON ((volatile u32*)(IFX_ASC1 + 0x0030)) ++#define IFX_ASC1_ABCON_RXINV (1 << 11) ++#define IFX_ASC1_ABCON_TXINV (1 << 10) ++#define IFX_ASC1_ABCON_ABEM(value) (((( 1 << 2) - 1) & (value)) << 8) ++#define IFX_ASC1_ABCON_FCDETEN (1 << 4) ++#define IFX_ASC1_ABCON_ABDETEN (1 << 3) ++#define IFX_ASC1_ABCON_ABSTEN (1 << 2) ++#define IFX_ASC1_ABCON_AUREN (1 << 1) ++#define IFX_ASC1_ABCON_ABEN (1 << 0) ++ ++/***Receive FIFO Control Register***/ ++#define IFX_ASC1_RXFCON ((volatile u32*)(IFX_ASC1 + 0x0040)) ++#define IFX_ASC1_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) ++#define IFX_ASC1_RXFCON_RXFFLU (1 << 1) ++#define IFX_ASC1_RXFCON_RXFEN (1 << 0) ++ ++/***Transmit FIFO Control Register***/ ++#define IFX_ASC1_TXFCON ((volatile u32*)(IFX_ASC1 + 0x0044)) ++#define IFX_ASC1_TXFCON_TXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) ++#define IFX_ASC1_TXFCON_TXFFLU (1 << 1) ++#define IFX_ASC1_TXFCON_TXFEN (1 << 0) ++ ++/***FIFO Status Register***/ ++#define IFX_ASC1_FSTAT ((volatile u32*)(IFX_ASC1 + 0x0048)) ++#define IFX_ASC1_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8) ++#define IFX_ASC1_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0) ++#define IFX_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) ++#define IFX_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) ++#define IFX_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) ++#define IFX_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) ++#define IFX_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) ++#define IFX_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) ++#define IFX_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) ++#define IFX_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) ++ ++ ++/***ASC Autobaud Status Register***/ ++#define IFX_ASC1_ABSTAT ((volatile u32*)(IFX_ASC1 + 0x0034)) ++#define IFX_ASC1_ABSTAT_DETWAIT (1 << 4) ++#define IFX_ASC1_ABSTAT_SCCDET (1 << 3) ++#define IFX_ASC1_ABSTAT_SCSDET (1 << 2) ++#define IFX_ASC1_ABSTAT_FCCDET (1 << 1) ++#define IFX_ASC1_ABSTAT_FCSDET (1 << 0) ++ ++/***ASC Write HW Modified Autobaud Status Register***/ ++#define IFX_ASC1_WHBABSTAT ((volatile u32*)(IFX_ASC1 + 0x003C)) ++#define IFX_ASC1_WHBABSTAT_SETDETWAIT (1 << 9) ++#define IFX_ASC1_WHBABSTAT_CLRDETWAIT (1 << 8) ++#define IFX_ASC1_WHBABSTAT_SETSCCDET (1 << 7) ++#define IFX_ASC1_WHBABSTAT_CLRSCCDET (1 << 6) ++#define IFX_ASC1_WHBABSTAT_SETSCSDET (1 << 5) ++#define IFX_ASC1_WHBABSTAT_CLRSCSDET (1 << 4) ++#define IFX_ASC1_WHBABSTAT_SETFCCDET (1 << 3) ++#define IFX_ASC1_WHBABSTAT_CLRFCCDET (1 << 2) ++#define IFX_ASC1_WHBABSTAT_SETFCSDET (1 << 1) ++#define IFX_ASC1_WHBABSTAT_CLRFCSDET (1 << 0) ++ ++/***ASC IRNCR0 **/ ++#define IFX_ASC1_IRNREN ((volatile u32*)(IFX_ASC1 + 0x00F4)) ++#define IFX_ASC1_IRNICR ((volatile u32*)(IFX_ASC1 + 0x00FC)) ++/***ASC IRNCR1 **/ ++#define IFX_ASC1_IRNCR ((volatile u32*)(IFX_ASC1 + 0x00F8)) ++#define IFX_ASC_IRNCR_TIR 0x1 ++#define IFX_ASC_IRNCR_RIR 0x2 ++#define IFX_ASC_IRNCR_EIR 0x4 ++ ++ ++ ++/***********************************************************************/ ++/* Module : DMA register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_DMA (KSEG1 | 0x1E104100) ++ ++#define IFX_DMA_BASE IFX_DMA ++#define IFX_DMA_CLC (volatile u32*)IFX_DMA_BASE ++#define IFX_DMA_ID (volatile u32*)(IFX_DMA_BASE + 0x08) ++#define IFX_DMA_CTRL (volatile u32*)(IFX_DMA_BASE + 0x10) ++#define IFX_DMA_CPOLL (volatile u32*)(IFX_DMA_BASE + 0x14) ++#define IFX_DMA_CS (volatile u32*)(IFX_DMA_BASE + 0x18) ++#define IFX_DMA_CCTRL (volatile u32*)(IFX_DMA_BASE + 0x1C) ++#define IFX_DMA_CDBA (volatile u32*)(IFX_DMA_BASE + 0x20) ++#define IFX_DMA_CDLEN (volatile u32*)(IFX_DMA_BASE + 0x24) ++#define IFX_DMA_CIS (volatile u32*)(IFX_DMA_BASE + 0x28) ++#define IFX_DMA_CIE (volatile u32*)(IFX_DMA_BASE + 0x2C) ++#define IFX_DMA_CGBL (volatile u32*)(IFX_DMA_BASE + 0x30) ++#define IFX_DMA_PS (volatile u32*)(IFX_DMA_BASE + 0x40) ++#define IFX_DMA_PCTRL (volatile u32*)(IFX_DMA_BASE + 0x44) ++ ++#define IFX_DMA_IRNEN (volatile u32*)(IFX_DMA_BASE + 0xf4) ++#define IFX_DMA_IRNCR (volatile u32*)(IFX_DMA_BASE + 0xf8) ++#define IFX_DMA_IRNICR (volatile u32*)(IFX_DMA_BASE + 0xfc) ++ ++ ++ ++/***********************************************************************/ ++/* Module : Debug register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_Debug (KSEG1 | 0x1F106000) ++ ++/***MCD Break Bus Switch Register***/ ++#define IFX_Debug_MCD_BBS ((volatile u32*)(IFX_Debug + 0x0000)) ++#define IFX_Debug_MCD_BBS_BTP1 (1 << 19) ++#define IFX_Debug_MCD_BBS_BTP0 (1 << 18) ++#define IFX_Debug_MCD_BBS_BSP1 (1 << 17) ++#define IFX_Debug_MCD_BBS_BSP0 (1 << 16) ++#define IFX_Debug_MCD_BBS_BT5EN (1 << 15) ++#define IFX_Debug_MCD_BBS_BT4EN (1 << 14) ++#define IFX_Debug_MCD_BBS_BT5 (1 << 13) ++#define IFX_Debug_MCD_BBS_BT4 (1 << 12) ++#define IFX_Debug_MCD_BBS_BS5EN (1 << 7) ++#define IFX_Debug_MCD_BBS_BS4EN (1 << 6) ++#define IFX_Debug_MCD_BBS_BS5 (1 << 5) ++#define IFX_Debug_MCD_BBS_BS4 (1 << 4) ++ ++/***MCD Multiplexer Control Register***/ ++#define IFX_Debug_MCD_MCR ((volatile u32*)(IFX_Debug + 0x0008)) ++#define IFX_Debug_MCD_MCR_MUX5 (1 << 4) ++#define IFX_Debug_MCD_MCR_MUX4 (1 << 3) ++#define IFX_Debug_MCD_MCR_MUX1 (1 << 0) ++ ++ ++ ++/***********************************************************************/ ++/* Module : ICU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_ICU (KSEG1 | 0x1F880200) ++ ++#define IFX_ICU_IM0_ISR ((volatile u32*)(IFX_ICU + 0x0000)) ++#define IFX_ICU_IM0_IER ((volatile u32*)(IFX_ICU + 0x0008)) ++#define IFX_ICU_IM0_IOSR ((volatile u32*)(IFX_ICU + 0x0010)) ++#define IFX_ICU_IM0_IRSR ((volatile u32*)(IFX_ICU + 0x0018)) ++#define IFX_ICU_IM0_IMR ((volatile u32*)(IFX_ICU + 0x0020)) ++#define IFX_ICU_IM0_IMR_IID (1 << 31) ++#define IFX_ICU_IM0_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) ++#define IFX_ICU_IM0_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) ++#define IFX_ICU_IM0_IR(value) (1 << (value)) ++ ++#define IFX_ICU_IM1_ISR ((volatile u32*)(IFX_ICU + 0x0028)) ++#define IFX_ICU_IM1_IER ((volatile u32*)(IFX_ICU + 0x0030)) ++#define IFX_ICU_IM1_IOSR ((volatile u32*)(IFX_ICU + 0x0038)) ++#define IFX_ICU_IM1_IRSR ((volatile u32*)(IFX_ICU + 0x0040)) ++#define IFX_ICU_IM1_IMR ((volatile u32*)(IFX_ICU + 0x0048)) ++#define IFX_ICU_IM1_IMR_IID (1 << 31) ++#define IFX_ICU_IM1_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) ++#define IFX_ICU_IM1_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) ++#define IFX_ICU_IM1_IR(value) (1 << (value)) ++ ++#define IFX_ICU_IM2_ISR ((volatile u32*)(IFX_ICU + 0x0050)) ++#define IFX_ICU_IM2_IER ((volatile u32*)(IFX_ICU + 0x0058)) ++#define IFX_ICU_IM2_IOSR ((volatile u32*)(IFX_ICU + 0x0060)) ++#define IFX_ICU_IM2_IRSR ((volatile u32*)(IFX_ICU + 0x0068)) ++#define IFX_ICU_IM2_IMR ((volatile u32*)(IFX_ICU + 0x0070)) ++#define IFX_ICU_IM2_IMR_IID (1 << 31) ++#define IFX_ICU_IM2_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) ++#define IFX_ICU_IM2_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) ++#define IFX_ICU_IM2_IR(value) (1 << (value)) ++ ++#define IFX_ICU_IM3_ISR ((volatile u32*)(IFX_ICU + 0x0078)) ++#define IFX_ICU_IM3_IER ((volatile u32*)(IFX_ICU + 0x0080)) ++#define IFX_ICU_IM3_IOSR ((volatile u32*)(IFX_ICU + 0x0088)) ++#define IFX_ICU_IM3_IRSR ((volatile u32*)(IFX_ICU + 0x0090)) ++#define IFX_ICU_IM3_IMR ((volatile u32*)(IFX_ICU + 0x0098)) ++#define IFX_ICU_IM3_IMR_IID (1 << 31) ++#define IFX_ICU_IM3_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) ++#define IFX_ICU_IM3_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) ++#define IFX_ICU_IM3_IR(value) (1 << (value)) ++ ++#define IFX_ICU_IM4_ISR ((volatile u32*)(IFX_ICU + 0x00A0)) ++#define IFX_ICU_IM4_IER ((volatile u32*)(IFX_ICU + 0x00A8)) ++#define IFX_ICU_IM4_IOSR ((volatile u32*)(IFX_ICU + 0x00B0)) ++#define IFX_ICU_IM4_IRSR ((volatile u32*)(IFX_ICU + 0x00B8)) ++#define IFX_ICU_IM4_IMR ((volatile u32*)(IFX_ICU + 0x00C0)) ++#define IFX_ICU_IM4_IMR_IID (1 << 31) ++#define IFX_ICU_IM4_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) ++#define IFX_ICU_IM4_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) ++#define IFX_ICU_IM4_IR(value) (1 << (value)) ++ ++#define IFX_ICU_IM5_ISR ((volatile u32*)(IFX_ICU + 0x00C8)) ++#define IFX_ICU_IM5_IER ((volatile u32*)(IFX_ICU + 0x00D0)) ++#define IFX_ICU_IM5_IOSR ((volatile u32*)(IFX_ICU + 0x00D8)) ++#define IFX_ICU_IM5_IRSR ((volatile u32*)(IFX_ICU + 0x00E0)) ++#define IFX_ICU_IM5_IMR ((volatile u32*)(IFX_ICU + 0x00E8)) ++#define IFX_ICU_IM5_IMR_IID (1 << 31) ++#define IFX_ICU_IM5_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) ++#define IFX_ICU_IM5_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) ++#define IFX_ICU_IM5_IR(value) (1 << (value)) ++ ++/***Interrupt Vector Value Register***/ ++#define IFX_ICU_IM_VEC ((volatile u32*)(IFX_ICU+ 0x00f8)) ++ ++/***Interrupt Vector Value Mask***/ ++#define IFX_ICU_IM0_VEC_MASK 0x0000003f ++#define IFX_ICU_IM1_VEC_MASK 0x00000fc0 ++#define IFX_ICU_IM2_VEC_MASK 0x0003f000 ++#define IFX_ICU_IM3_VEC_MASK 0x00fc0000 ++#define IFX_ICU_IM4_VEC_MASK 0x3f000000 ++ ++#define IFX_ICU_IM0_ISR_IR(value) (1<<(value)) ++#define IFX_ICU_IM0_IER_IR(value) (1<<(value)) ++#define IFX_ICU_IM1_ISR_IR(value) (1<<(value)) ++#define IFX_ICU_IM1_IER_IR(value) (1<<(value)) ++#define IFX_ICU_IM2_ISR_IR(value) (1<<(value)) ++#define IFX_ICU_IM2_IER_IR(value) (1<<(value)) ++#define IFX_ICU_IM3_ISR_IR(value) (1<<(value)) ++#define IFX_ICU_IM3_IER_IR(value) (1<<(value)) ++#define IFX_ICU_IM4_ISR_IR(value) (1<<(value)) ++#define IFX_ICU_IM4_IER_IR(value) (1<<(value)) ++#define IFX_ICU_IM5_ISR_IR(value) (1<<(value)) ++#define IFX_ICU_IM5_IER_IR(value) (1<<(value)) ++ ++/***External Interrupt Control Register***/ ++#define IFX_ICU_EIU (KSEG1+0x1f101000) ++#define IFX_ICU_EIU_EXIN_C ((volatile u32*)(IFX_ICU_EIU + 0x0000)) ++#define IFX_ICU_EIU_INIC ((volatile u32*)(IFX_ICU_EIU + 0x0004)) ++#define IFX_ICU_EIU_INC ((volatile u32*)(IFX_ICU_EIU + 0x0008)) ++#define IFX_ICU_EIU_INEN ((volatile u32*)(IFX_ICU_EIU + 0x000c)) ++ ++/***********************************************************************/ ++/* Module : MPS register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_MPS (KSEG1 | 0x1F107000) ++ ++#define IFX_MPS_CHIPID ((volatile u32*)(IFX_MPS + 0x0344)) ++#define IFX_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & 0xF) ++#define IFX_MPS_CHIPID_VERSION_SET(value) (((value) & 0xF) << 28) ++#define IFX_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & 0xFFFF) ++#define IFX_MPS_CHIPID_PARTNUM_SET(value) (((value) & 0xFFFF) << 12) ++#define IFX_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & 0x7FF) ++#define IFX_MPS_CHIPID_MANID_SET(value) (((value) & 0x7FF) << 1) ++ ++ ++ ++/************************************************************************/ ++/* Module : DEU register address and bits */ ++/************************************************************************/ ++ ++#define IFX_DEU_BASE_ADDR (KSEG1 | 0x1E103100) ++ ++/* DEU Control Register */ ++#define IFX_DEU_CLK ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0000)) ++#define IFX_DEU_ID ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0008)) ++ ++/* DEU control register */ ++#define IFX_DES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0010)) ++#define IFX_DES_IHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0014)) ++#define IFX_DES_ILR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0018)) ++#define IFX_DES_K1HR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x001C)) ++#define IFX_DES_K1LR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0020)) ++#define IFX_DES_K3HR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0024)) ++#define IFX_DES_K3LR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0028)) ++#define IFX_DES_IVHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x002C)) ++#define IFX_DES_IVLR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0030)) ++#define IFX_DES_OHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0040)) ++#define IFX_DES_OLR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050)) ++ ++/* AES DEU register */ ++#define IFX_AES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050)) ++#define IFX_AES_ID3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0054)) ++#define IFX_AES_ID2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0058)) ++#define IFX_AES_ID1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x005C)) ++#define IFX_AES_ID0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0060)) ++ ++/* AES Key register */ ++#define IFX_AES_K7R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0064)) ++#define IFX_AES_K6R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0068)) ++#define IFX_AES_K5R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x006C)) ++#define IFX_AES_K4R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0070)) ++#define IFX_AES_K3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0074)) ++#define IFX_AES_K2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0078)) ++#define IFX_AES_K1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x007C)) ++#define IFX_AES_K0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0080)) ++ ++/* AES vector register */ ++#define IFX_AES_IV3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0084)) ++#define IFX_AES_IV2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0088)) ++#define IFX_AES_IV1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x008C)) ++#define IFX_AES_IV0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0090)) ++#define IFX_AES_0D3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0094)) ++#define IFX_AES_0D2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0098)) ++#define IFX_AES_OD1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x009C)) ++#define IFX_AES_OD0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00A0)) ++ ++/* hash control registe */ ++#define IFX_HASH_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B0)) ++#define IFX_HASH_MR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B4)) ++#define IFX_HASH_D1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B8 )) ++#define IFX_HASH_D2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00BC )) ++#define IFX_HASH_D3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C0 )) ++#define IFX_HASH_D4R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C4)) ++#define IFX_HASH_D5R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C8)) ++ ++#define IFX_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00EC)) ++ ++#define IFX_DEU_IRNEN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00F4)) ++#define IFX_DEU_IRNCR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00F8)) ++#define IFX_DEU_IRNICR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00FC)) ++ ++ ++ ++/************************************************************************/ ++/* Module : PPE register address and bits */ ++/************************************************************************/ ++ ++#define IFX_PPE32_BASE (KSEG1 | 0x1E180000) ++#define IFX_PPE32_DEBUG_BREAK_TRACE_REG (IFX_PPE32_BASE + (0x0000 * 4)) ++#define IFX_PPE32_INT_MASK_STATUS_REG (IFX_PPE32_BASE + (0x0030 * 4)) ++#define IFX_PPE32_INT_RESOURCE_REG (IFX_PPE32_BASE + (0x0040 * 4)) ++#define IFX_PPE32_CDM_CODE_MEM_B0 (IFX_PPE32_BASE + (0x1000 * 4)) ++#define IFX_PPE32_CDM_CODE_MEM_B1 (IFX_PPE32_BASE + (0x2000 * 4)) ++#define IFX_PPE32_DATA_MEM_MAP_REG_BASE (IFX_PPE32_BASE + (0x4000 * 4)) ++ ++#define IFX_PPE32_SRST (IFX_PPE32_BASE + 0x10080) ++ ++/* ++ * ETOP MDIO Registers ++ */ ++#define IFX_PP32_ETOP_MDIO_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4))) ++#define IFX_PP32_ETOP_MDIO_ACC ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4))) ++#define IFX_PP32_ETOP_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4))) ++#define IFX_PP32_ETOP_IG_VLAN_COS ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4))) ++#define IFX_PP32_ETOP_IG_DSCP_COS3 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4))) ++#define IFX_PP32_ETOP_IG_DSCP_COS2 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4))) ++#define IFX_PP32_ETOP_IG_DSCP_COS1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4))) ++#define IFX_PP32_ETOP_IG_DSCP_COS0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4))) ++#define IFX_PP32_ETOP_IG_PLEN_CTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4))) ++#define IFX_PP32_ETOP_ISR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4))) ++#define IFX_PP32_ETOP_IER ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4))) ++#define IFX_PP32_ETOP_VPID ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4))) ++#define IFX_PP32_ENET_MAC_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4))) ++#define IFX_PP32_ENETS_DBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4))) ++#define IFX_PP32_ENETS_CBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4))) ++#define IFX_PP32_ENETS_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4))) ++#define IFX_PP32_ENETS_PGCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4))) ++#define IFX_PP32_ENETS_PKTCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4))) ++#define IFX_PP32_ENETS_BUF_CTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4))) ++#define IFX_PP32_ENETS_COS_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4))) ++#define IFX_PP32_ENETS_IGDROP ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4))) ++#define IFX_PP32_ENETS_IGERR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4))) ++#define IFX_PP32_ENET_MAC_DA0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4))) ++#define IFX_PP32_ENET_MAC_DA1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4))) ++ ++#define IFX_PP32_ENETF_DBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0630 * 4))) ++#define IFX_PP32_ENETF_CBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0631 * 4))) ++#define IFX_PP32_ENETF_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0632 * 4))) ++#define IFX_PP32_ENETF_PGCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0633 * 4))) ++#define IFX_PP32_ENETF_PKTCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0634 * 4))) ++#define IFX_PP32_ENETF_HFCTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0635 * 4))) ++#define IFX_PP32_ENETF_TXCTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0636 * 4))) ++ ++#define IFX_PP32_ENETF_VLCOS0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0638 * 4))) ++#define IFX_PP32_ENETF_VLCOS1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0639 * 4))) ++#define IFX_PP32_ENETF_VLCOS2 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063A * 4))) ++#define IFX_PP32_ENETF_VLCOS3 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063B * 4))) ++#define IFX_PP32_ENETF_EGERR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063C * 4))) ++#define IFX_PP32_ENETF_EGDROP ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063D * 4))) ++ ++ ++/* Sharebuff SB RAM2 control data */ ++#define IFX_PP32_SB2_DATABASE ((IFX_PPE32_BASE + (0x8C00 * 4))) ++#define IFX_PP32_SB2_CTRLBASE ((IFX_PPE32_BASE + (0x92E0 * 4))) ++ ++ ++ ++#endif //IFX_H +diff --git a/arch/mips/include/asm/ifx/amazon_se/amazon_se_admmod.h b/arch/mips/include/asm/ifx/amazon_se/amazon_se_admmod.h +new file mode 100644 +index 0000000..7f98fd3 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/amazon_se/amazon_se_admmod.h +@@ -0,0 +1,248 @@ ++/****************************************************************************** ++ Copyright (c) 2004, Infineon Technologies. All rights reserved. ++ ++ No Warranty ++ Because the program is licensed free of charge, there is no warranty for ++ the program, to the extent permitted by applicable law. Except when ++ otherwise stated in writing the copyright holders and/or other parties ++ provide the program "as is" without warranty of any kind, either ++ expressed or implied, including, but not limited to, the implied ++ warranties of merchantability and fitness for a particular purpose. The ++ entire risk as to the quality and performance of the program is with ++ you. should the program prove defective, you assume the cost of all ++ necessary servicing, repair or correction. ++ ++ In no event unless required by applicable law or agreed to in writing ++ will any copyright holder, or any other party who may modify and/or ++ redistribute the program as permitted above, be liable to you for ++ damages, including any general, special, incidental or consequential ++ damages arising out of the use or inability to use the program ++ (including but not limited to loss of data or data being rendered ++ inaccurate or losses sustained by you or third parties or a failure of ++ the program to operate with any other programs), even if such holder or ++ other party has been advised of the possibility of such damages. ++ ****************************************************************************** ++ Module : ifx_swdrv.h ++ Date : 2004-09-01 ++ Description : JoeLin ++ Remarks: ++ *****************************************************************************/ ++/****************************************************************************** ++** 2009/12/17 Lantiq Inc. Revised by Richard Hsu ++** Rename to amazon_se_admmod.h. ++** We use GPIO to simulate MDIO/MDC operations on AmazonSE WAVE board. ++** ASE WAVE board uses PHY2PHY connection to Tantos 0G ++** ++*******************************************************************************/ ++ ++ ++ ++ ++#ifndef _ADM_6996_MODULE_H_ ++#define _ADM_6996_MODULE_H_ ++ ++#include ++ ++//Wrapper for ASE GPIO setting ++#define AMAZON_SE_GPIO_P1_OUT IFX_GPIO_P1_OUT ++#define AMAZON_SE_GPIO_P1_ALTSEL0 IFX_GPIO_P1_ALTSEL0 ++#define AMAZON_SE_GPIO_P1_ALTSEL1 IFX_GPIO_P1_ALTSEL1 ++#define AMAZON_SE_GPIO_P1_DIR IFX_GPIO_P1_DIR ++#define AMAZON_SE_GPIO_P1_IN IFX_GPIO_P1_IN ++ ++#define ifx_printf(x) printk x ++ ++/* command codes */ ++#define ADM_SW_SMI_READ 0x02 ++#define ADM_SW_SMI_WRITE 0x01 ++#define ADM_SW_SMI_START 0x01 ++ ++#define ADM_SW_EEPROM_WRITE 0x01 ++#define ADM_SW_EEPROM_WRITE_ENABLE 0x03 ++#define ADM_SW_EEPROM_WRITE_DISABLE 0x00 ++#define EEPROM_TYPE 8 /* for 93C66 */ ++ ++/* bit masks */ ++#define ADM_SW_BIT_MASK_1 0x00000001 ++#define ADM_SW_BIT_MASK_2 0x00000002 ++#define ADM_SW_BIT_MASK_4 0x00000008 ++#define ADM_SW_BIT_MASK_10 0x00000200 ++#define ADM_SW_BIT_MASK_16 0x00008000 ++#define ADM_SW_BIT_MASK_32 0x80000000 ++ ++/* delay timers */ ++#define ADM_SW_MDC_DOWN_DELAY 5 ++#define ADM_SW_MDC_UP_DELAY 5 ++#define ADM_SW_CS_DELAY 5 ++ ++/* MDIO modes */ ++#define ADM_SW_MDIO_OUTPUT 1 ++#define ADM_SW_MDIO_INPUT 0 ++ ++#define ADM_SW_MAX_PORT_NUM 5 ++#define ADM_SW_MAX_VLAN_NUM 15 ++ ++/* registers */ ++#define ADM_SW_PORT0_CONF 0x1 ++#define ADM_SW_PORT1_CONF 0x3 ++#define ADM_SW_PORT2_CONF 0x5 ++#define ADM_SW_PORT3_CONF 0x7 ++#define ADM_SW_PORT4_CONF 0x8 ++#define ADM_SW_PORT5_CONF 0x9 ++#define ADM_SW_VLAN_MODE 0x11 ++#define ADM_SW_MAC_LOCK 0x12 ++#define ADM_SW_VLAN0_CONF 0x13 ++#define ADM_SW_PORT0_PVID 0x28 ++#define ADM_SW_PORT1_PVID 0x29 ++#define ADM_SW_PORT2_PVID 0x2a ++#define ADM_SW_PORT34_PVID 0x2b ++#define ADM_SW_PORT5_PVID 0x2c ++#define ADM_SW_PHY_RESET 0x2f ++#define ADM_SW_MISC_CONF 0x30 ++#define ADM_SW_BNDWDH_CTL0 0x31 ++#define ADM_SW_BNDWDH_CTL1 0x32 ++#define ADM_SW_BNDWDH_CTL_ENA 0x33 ++ ++/* port modes */ ++#define ADM_SW_PORT_FLOWCTL 0x1 /* 802.3x flow control */ ++#define ADM_SW_PORT_AN 0x2 /* auto negotiation */ ++#define ADM_SW_PORT_100M 0x4 /* 100M */ ++#define ADM_SW_PORT_FULL 0x8 /* full duplex */ ++#define ADM_SW_PORT_TAG 0x10 /* output tag on */ ++#define ADM_SW_PORT_DISABLE 0x20 /* disable port */ ++#define ADM_SW_PORT_TOS 0x40 /* TOS first */ ++#define ADM_SW_PORT_PPRI 0x80 /* port based priority first */ ++#define ADM_SW_PORT_MDIX 0x8000 /* auto MDIX on */ ++#define ADM_SW_PORT_PVID_SHIFT 10 ++#define ADM_SW_PORT_PVID_BITS 4 ++ ++/* VLAN */ ++#define ADM_SW_VLAN_PORT0 0x1 ++#define ADM_SW_VLAN_PORT1 0x2 ++#define ADM_SW_VLAN_PORT2 0x10 ++#define ADM_SW_VLAN_PORT3 0x40 ++#define ADM_SW_VLAN_PORT4 0x80 ++#define ADM_SW_VLAN_PORT5 0x100 ++ ++ ++/* GPIO 012 enabled, output mode */ ++#define GPIO_ENABLEBITS 0x000700f8 ++ ++/* ++ define AMAZON GPIO port to ADM6996 EEPROM interface ++ MDIO -> EEDI GPIO 16, AMAZON GPIO P1.0, bi-direction ++ MDC -> EESK GPIO 17, AMAZON GPIO P1.1, output only ++ MDCS -> EECS GPIO 18, AMAZON GPIO P1.2, output only ++ EEDO GPIO 15, AMAZON GPIO P0.15, do not need this one! */ ++ ++#define GPIO_MDIO 1 //P1.0 ++#define GPIO_MDC 2 //P1.1 ++#define GPIO_MDCS 4 //P1.2 ++ ++//joelin #define GPIO_MDIO 0 ++//joelin #define GPIO_MDC 5 /* PORT 0 GPIO5 */ ++//joelin #define GPIO_MDCS 6 /* PORT 0 GPIO6 */ ++ ++ ++#define MDIO_INPUT 0x00000001 ++#define MDIO_OUTPUT_EN 0x00010000 ++ ++ ++/* type definitions */ ++typedef unsigned char U8; ++typedef unsigned short U16; ++typedef unsigned int U32; ++ ++typedef struct _REGRW_ ++{ ++ unsigned int addr; ++ unsigned int value; ++ unsigned int mode; ++}REGRW, *PREGRW; ++ ++//joelin adm6996i ++typedef struct _MACENTRY_ ++{ ++ unsigned char mac_addr[6]; ++ unsigned long fid:4; ++ unsigned long portmap:6; ++ union { ++ unsigned long age_timer:9; ++ unsigned long info_ctrl:9; ++ } ctrl; ++ unsigned long occupy:1; ++ unsigned long info_type:1; ++ unsigned long bad:1; ++ unsigned long result:3;//000:command ok ,001:all entry used,010:Entry Not found ,011:try next entry ,101:command error ++ ++ }MACENTRY, *PMACENTRY; ++typedef struct _PROTOCOLFILTER_ ++{ ++ int protocol_filter_num;//[0~7] ++ int ip_p; //Value Compared with Protocol in IP Heade[7:0] ++ char action:2;//Action for protocol Filter . ++//00 = Protocol Portmap is Default Output Ports. ++//01 = Protocol Portmap is 6'b0. ++//10 = Protocol Portmap is the CPU port if the incoming port ++//is not the CPU port. But if the incoming port is the CPU port, then Type Portmap contains Default Output Ports, excluding the CPU port. ++ }PROTOCOLFILTER, *PPROTOCOLFILTER; ++ ++//joelin adm6996i ++ ++/* Santosh: for IGMP proxy/snooping */ ++ ++//050614:fchang int adm_process_mac_table_request (unsigned int cmd, struct _MACENTRY_ *mac); ++//050614:fchang int adm_process_protocol_filter_request (unsigned int cmd, struct _PROTOCOLFILTER_ *filter); ++ ++ ++/* IOCTL keys */ ++#define KEY_IOCTL_ADM_REGRW 0x01 ++#define KEY_IOCTL_ADM_SW_REGRW 0x02 ++#define KEY_IOCTL_ADM_SW_PORTSTS 0x03 ++#define KEY_IOCTL_ADM_SW_INIT 0x04 ++//for adm6996i-start ++#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_ADD 0x05 ++#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_DEL 0x06 ++#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_INIT 0x07 ++#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_MORE 0x08 ++#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_ADD 0x09 ++#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_DEL 0x0a ++#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_GET 0x0b ++ ++//adm6996i #define KEY_IOCTL_MAX_KEY 0x05 ++#define KEY_IOCTL_MAX_KEY 0x0c ++//for adm6996i-end ++/* IOCTL MAGIC */ ++#define ADM_MAGIC ('a'|'d'|'m'|'t'|'e'|'k') ++ ++/* IOCTL parameters */ ++#define ADM_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_REGRW, REGRW) ++#define ADM_SW_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_REGRW, REGRW) ++#define ADM_SW_IOCTL_PORTSTS _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_PORTSTS, NULL) ++#define ADM_SW_IOCTL_INIT _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_INIT, NULL) ++ ++ ++//6996i-stat ++#define ADM_SW_IOCTL_MACENTRY_ADD _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_ADD,MACENTRY) ++#define ADM_SW_IOCTL_MACENTRY_DEL _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_DEL,MACENTRY) ++#define ADM_SW_IOCTL_MACENTRY_GET_INIT _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_INIT,MACENTRY) ++#define ADM_SW_IOCTL_MACENTRY_GET_MORE _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_MORE,MACENTRY) ++#define ADM_SW_IOCTL_FILTER_ADD _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_ADD,PROTOCOLFILTER) ++#define ADM_SW_IOCTL_FILTER_DEL _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_DEL,PROTOCOLFILTER) ++#define ADM_SW_IOCTL_FILTER_GET _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_GET,PROTOCOLFILTER) ++ ++//6996i-end ++ ++ ++#define REG_READ 0x0 ++#define REG_WRITE 0x1 ++ ++/* undefine symbol */ ++//#define AMAZON_SW_REG(reg) *((volatile U32*)(reg)) ++//#define GPIO0_INPUT_MASK 0 ++//#define GPIO_conf0_REG 0x12345678 ++//#define GPIO_SET_HI ++//#define GPIO_SET_LOW ++ ++#endif ++/* _ADM_6996_MODULE_H_ */ +diff --git a/arch/mips/include/asm/ifx/amazon_se/boards/Makefile b/arch/mips/include/asm/ifx/amazon_se/boards/Makefile +new file mode 100644 +index 0000000..f731c7e +--- /dev/null ++++ b/arch/mips/include/asm/ifx/amazon_se/boards/Makefile +@@ -0,0 +1,13 @@ ++# ++# Makefile for the platform specific kernel interface routines under Linux. ++# ++ ++all: ifxmips_amazon_se_boards.a ++ ++obj-$(CONFIG_AMAZON_SE_REF_BOARD) += amazon_se_ref_board.o ++ ++EXTRA_AFLAGS := $(CFLAGS) ++ ++clean: ++ rm -f *.o *.a ++ +diff --git a/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_admmod.c b/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_admmod.c +new file mode 100644 +index 0000000..cfdce24 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_admmod.c +@@ -0,0 +1,722 @@ ++/****************************************************************************** ++** ++** FILE NAME : admmod.c ++** PROJECT : Danube ++** MODULES : ADM6996 ++** ++** DATE : 1 SEP 2004 ++** AUTHOR : Joe Lin ++** DESCRIPTION : ADM6996 Switch Driver ++** COPYRIGHT : Copyright (c) 2006 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++*******************************************************************************/ ++ ++/****************************************************************************** ++** 2009/12/17 Lantiq Inc. Revised by Richard Hsu ++** Rename to amazon_se_admmod.c. ++** We use GPIO to simulate MDIO/MDC operations on AmazonSE WAVE board. ++** ASE WAVE board uses PHY2PHY connection to Tantos 0G ++** ++*******************************************************************************/ ++ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#include ++#include ++ ++// Using GPIO to access Tantos as default ++#define CONFIG_SWITCH_GPIO_ACCESS ++ ++#ifdef CONFIG_SWITCH_GPIO_ACCESS ++ #undef CONFIG_SWITCH_ADM6996_MDIO ++#endif ++ ++#define ADM_SW_IOCTL_PORTSTS _IO(ADM_MAGIC, KEY_IOCTL_ADM_SW_PORTSTS) ++#define ADM_SW_IOCTL_INIT _IO(ADM_MAGIC, KEY_IOCTL_ADM_SW_INIT) ++ ++/* ++ initialize GPIO pins. ++ output mode, low ++*/ ++ ++// We use GPIO24/27 on ASE WAVE board for simulation ++#define ASE_TANTOS_MDIO 0x00000100 ++#define ASE_TANTOS_MDC 0x00000800 ++ ++#define ASE_TANTOS_MDIO_COMPLEMENT 0xfffffeff ++#define ASE_TANTOS_MDC_COMPLEMENT 0xfffff7ff ++#define TANTOS_SW_MDC_UP_DELAY 5 ++#define TANTOS_SW_MDC_DOWN_DELAY 5 ++ ++void ifx_gpio_init(void) ++{ ++ //GPIO24: MDIO P1.8 ++ //GPIO27: MDC P1.11 ++ ++/* ++ P1.8 as GPIO Out: ++ AMAZON_SE_GPIO_P1_ALTSEL0.8=0 ++ AMAZON_SE_GPIO_P1_ALTSEL1.8=0 ++ AMAZON_SE_GPIO_P1_DIR.8 = 1 ++ ++ P1.8 as MDIO pin: ++ AMAZON_SE_GPIO_P1_ALTSEL0.8=1 ++ AMAZON_SE_GPIO_P1_ALTSEL1.8=1 ++ AMAZON_SE_GPIO_P1_DIR.8 =1 ++ ++P1.11 as GPIO Out: ++ AMAZON_SE_GPIO_P1_ALTSEL0.8=0 ++ AMAZON_SE_GPIO_P1_ALTSEL1.8=0 ++ AMAZON_SE_GPIO_P1_DIR.8 =1 ++ ++P1.11 as MDC pin: ++ AMAZON_SE_GPIO_P1_ALTSEL0.8=1 ++ AMAZON_SE_GPIO_P1_ALTSEL1.8=1 ++ AMAZON_SE_GPIO_P1_DIR.8 =1 ++*/ ++ ++ ++ *(AMAZON_SE_GPIO_P1_OUT) |= (ASE_TANTOS_MDC|ASE_TANTOS_MDIO); ++ *(AMAZON_SE_GPIO_P1_ALTSEL0) &= ASE_TANTOS_MDC_COMPLEMENT; ++ *(AMAZON_SE_GPIO_P1_ALTSEL0) &= ASE_TANTOS_MDIO_COMPLEMENT; ++ *(AMAZON_SE_GPIO_P1_ALTSEL1) &= ASE_TANTOS_MDC_COMPLEMENT; ++ *(AMAZON_SE_GPIO_P1_ALTSEL1) &= ASE_TANTOS_MDIO_COMPLEMENT; ++ *(AMAZON_SE_GPIO_P1_DIR) |= (ASE_TANTOS_MDC|ASE_TANTOS_MDIO); ++ ++} ++ ++void gpio_info() ++{ ++/* ++ printk("*(AMAZON_SE_GPIO_P1_ALTSEL0) is %04x\n",*(AMAZON_SE_GPIO_P1_ALTSEL0)); ++ printk("*(AMAZON_SE_GPIO_P1_ALTSEL1) is %04x\n",*(AMAZON_SE_GPIO_P1_ALTSEL1)); ++ printk("*(AMAZON_SE_GPIO_P1_DIR) is %04x\n\n",*(AMAZON_SE_GPIO_P1_DIR)); ++*/ ++} ++/* read one bit from mdio port */ ++int ifx_sw_mdio_readbit(void) ++{ ++ //GPIO24 as MDIO ++ return *(AMAZON_SE_GPIO_P1_IN)& 0x0100 ; ++} ++ ++/* ++ MDIO mode selection ++ 1 -> output ++ 0 -> input ++ ++ switch input/output mode of GPIO 0 ++*/ ++void ifx_mdio_mode(int mode) ++{ ++ if (mode) ++ {*(AMAZON_SE_GPIO_P1_DIR) |= ASE_TANTOS_MDIO;} ++ else ++ {*(AMAZON_SE_GPIO_P1_DIR) &= ASE_TANTOS_MDIO_COMPLEMENT;} ++} ++ ++void ifx_mdc_hi(void) ++{ ++ *AMAZON_SE_GPIO_P1_OUT |= (ASE_TANTOS_MDC); ++} ++ ++void ifx_mdio_hi(void) ++{ ++ *AMAZON_SE_GPIO_P1_OUT |= (ASE_TANTOS_MDIO); ++} ++ ++void ifx_mdcs_hi(void) ++{ ++} ++ ++void ifx_mdc_lo(void) ++{ ++ *AMAZON_SE_GPIO_P1_OUT &= (ASE_TANTOS_MDC_COMPLEMENT); ++} ++ ++void ifx_mdio_lo(void) ++{ ++ *AMAZON_SE_GPIO_P1_OUT &= (ASE_TANTOS_MDIO_COMPLEMENT); ++} ++ ++void ifx_mdcs_lo(void) ++{ ++} ++ ++/* ++ mdc pulse ++ 0 -> 1 -> 0 ++*/ ++static void ifx_sw_mdc_pulse(void) ++{ ++ ++ ifx_mdc_lo(); ++ udelay(TANTOS_SW_MDC_DOWN_DELAY); ++ ifx_mdc_hi(); ++ udelay(TANTOS_SW_MDC_DOWN_DELAY); ++ ifx_mdc_lo(); ++ ++} ++ ++/* ++ mdc toggle ++ 1 -> 0 ++*/ ++static void ifx_sw_mdc_toggle(void) ++{ ++ ++ ifx_mdc_hi(); ++ udelay(TANTOS_SW_MDC_DOWN_DELAY); ++ ifx_mdc_lo(); ++ udelay(TANTOS_SW_MDC_DOWN_DELAY); ++ ++} ++ ++/* ++ enable eeprom write ++ For ATC 93C66 type EEPROM; accessing ADM6996 internal EEPROM type registers ++*/ ++static void ifx_sw_eeprom_write_enable(void) ++{ ++ // no need for ASE WAVE board ++} ++ ++/* ++ disable eeprom write ++*/ ++static void ifx_sw_eeprom_write_disable(void) ++{ ++} ++ ++ ++ ++#ifdef CONFIG_SWITCH_ADM6996_MDIO //605112:fchang.added ++static int ifx_sw_read_adm6996_smi(unsigned int addr, unsigned int *dat) ++{ ++//060620:henryhsu modify for vlan addr=((addr<<16)|(1<<21))&0x3ff0000; ++ addr=(addr<<16)&0x3ff0000; ++ *AMAZON_SE_PPE32_ETOP_MDIO_ACC =(0xC0000000|addr); ++ while ((*AMAZON_SE_PPE32_ETOP_MDIO_ACC)&0x80000000){}; ++ *dat=((*AMAZON_SE_PPE32_ETOP_MDIO_ACC)&0x0FFFF); ++ return 0; ++} ++#endif ++ ++ ++static int ifx_sw_read_tantos(unsigned int addr, unsigned int *dat) ++{ ++ unsigned int op; ++ ifx_gpio_init(); ++ ++ ifx_mdcs_hi(); ++ udelay(ADM_SW_CS_DELAY); ++ ++ ifx_mdcs_lo(); ++ ifx_mdc_lo(); ++ ifx_mdio_lo(); ++ ++ udelay(ADM_SW_CS_DELAY); ++ ++ /* preamble, 32 bit 1 */ ++ ifx_mdio_hi(); ++ op = ADM_SW_BIT_MASK_32; ++ while (op) ++ { ++ ifx_sw_mdc_pulse(); ++ op >>= 1; ++ } ++ ++ /* command start (01b) */ ++ op = ADM_SW_BIT_MASK_2; ++ while (op) ++ { ++ if (op & ADM_SW_SMI_START) ++ ifx_mdio_hi(); ++ else ++ ifx_mdio_lo(); ++ ++ ifx_sw_mdc_pulse(); ++ op >>= 1; ++ } ++ ++ /* read command (10b) */ ++ op = ADM_SW_BIT_MASK_2; ++ while (op) ++ { ++ if (op & ADM_SW_SMI_READ) ++ ifx_mdio_hi(); ++ else ++ ifx_mdio_lo(); ++ ++ ifx_sw_mdc_pulse(); ++ op >>= 1; ++ } ++ ++ /* send address A9 ~ A0 */ ++ op = ADM_SW_BIT_MASK_10; ++ while (op) ++ { ++ if (op & addr) ++ ifx_mdio_hi(); ++ else ++ ifx_mdio_lo(); ++ ++ ifx_sw_mdc_pulse(); ++ op >>= 1; ++ } ++ ++ /* turnaround bits */ ++ op = ADM_SW_BIT_MASK_2; ++ ifx_mdio_hi(); ++ while (op) ++ { ++ ifx_sw_mdc_pulse(); ++ op >>= 1; ++ } ++ ++ udelay(ADM_SW_MDC_DOWN_DELAY); ++ ++ /* set MDIO pin to input mode */ ++ ++ ifx_mdio_mode(ADM_SW_MDIO_INPUT); ++ ++ /* start read data */ ++ ++ *dat = 0; ++ op = ADM_SW_BIT_MASK_32; ++ while (op) ++ { ++ *dat <<= 1; ++ if (ifx_sw_mdio_readbit()) *dat |= 1; ++ ifx_sw_mdc_toggle(); ++ ++ op >>= 1; ++ } ++ ++ /* set MDIO to output mode */ ++ ifx_mdio_mode(ADM_SW_MDIO_OUTPUT); ++ ++ /* dummy clock */ ++ op = ADM_SW_BIT_MASK_4; ++ ifx_mdio_lo(); ++ while(op) ++ { ++ ifx_sw_mdc_pulse(); ++ op >>= 1; ++ } ++ ++ ifx_mdc_lo(); ++ ifx_mdio_lo(); ++ ifx_mdcs_hi(); ++ ++ /* EEPROM registers */ ++ *dat >>= 16; ++ ++ return 0; ++} ++ ++int ifx_sw_read(unsigned int addr, unsigned int *dat) ++{ ++//printk("ifx_sw_read\n"); ++//605112:fchang.removed #ifdef ADM6996_MDC_MDIO_MODE //smi mode ////000001.joelin ++#ifdef CONFIG_SWITCH_ADM6996_MDIO //605112:fchang.added ++ ifx_sw_read_adm6996_smi(addr,dat); ++#else ++ #ifdef CONFIG_SWITCH_GPIO_ACCESS //605112:fchang.added ++ ifx_sw_read_tantos(addr,dat); ++ #endif ++#endif ++ return 0; ++} ++ ++/* ++ write register to ADM6996 eeprom registers ++*/ ++//for adm6996i -start ++//605112:fchang.removed #ifdef ADM6996_MDC_MDIO_MODE //smi mode //000001.joelin ++#ifdef CONFIG_SWITCH_ADM6996_MDIO //605112:fchang.added ++static int ifx_sw_write_adm6996_smi(unsigned int addr, unsigned int dat) ++{ ++//060620:henryhsu modify for vlan *DANUBE_PPE32_ETOP_MDIO_ACC = (((addr<<16)|(1<<21))&0x3ff0000)|dat|0x80000000; ++ *AMAZON_SE_PPE32_ETOP_MDIO_ACC = ((addr<<16) &0x3ff0000)|dat|0x80000000; ++ while ((*AMAZON_SE_PPE32_ETOP_MDIO_ACC )&0x80000000){}; ++ return 0; ++} ++#endif //ADM6996_MDC_MDIO_MODE //000001.joelin ++ ++static int ifx_sw_write_tantos(unsigned int addr, unsigned int dat) ++{ ++#if 1 ++ unsigned int op; ++ ++ ifx_gpio_init(); ++ ++ ifx_mdcs_hi(); ++ udelay(ADM_SW_CS_DELAY); ++ ++ ifx_mdcs_lo(); ++ ifx_mdc_lo(); ++ ifx_mdio_lo(); ++ ++ udelay(ADM_SW_CS_DELAY); ++ ++ /* preamble, 32 bit 1 */ ++ ifx_mdio_hi(); ++ op = ADM_SW_BIT_MASK_32; ++ while (op) ++ { ++ ifx_sw_mdc_pulse(); ++ op >>= 1; ++ } ++ ++ /* command start (01b) */ ++ op = ADM_SW_BIT_MASK_2; ++ while (op) ++ { ++ if (op & ADM_SW_SMI_START) ++ ifx_mdio_hi(); ++ else ++ ifx_mdio_lo(); ++ ++ ifx_sw_mdc_pulse(); ++ op >>= 1; ++ } ++ ++ /* write command (01b) */ ++ op = ADM_SW_BIT_MASK_2; ++ while (op) ++ { ++ if (op & ADM_SW_SMI_WRITE) ++ ifx_mdio_hi(); ++ else ++ ifx_mdio_lo(); ++ ++ ifx_sw_mdc_pulse(); ++ op >>= 1; ++ } ++ ++ /* send address A9 ~ A0 */ ++ op = ADM_SW_BIT_MASK_10; ++ while (op) ++ { ++ if (op & addr) ++ ifx_mdio_hi(); ++ else ++ ifx_mdio_lo(); ++ ++ ifx_sw_mdc_pulse(); ++ op >>= 1; ++ } ++ ++ /* turnaround bits */ ++ op = ADM_SW_BIT_MASK_2; ++ ifx_mdio_hi(); ++ while (op) ++ { ++ ifx_sw_mdc_pulse(); ++ op >>= 1; ++ } ++ ++ udelay(ADM_SW_MDC_DOWN_DELAY); ++ ++ /* set MDIO pin to output mode */ ++ ifx_mdio_mode(ADM_SW_MDIO_OUTPUT); ++ ++ ++ /* start write data */ ++ op = ADM_SW_BIT_MASK_16; ++ while (op) ++ { ++ if (op & dat) ++ ifx_mdio_hi(); ++ else ++ ifx_mdio_lo(); ++ ++ ifx_sw_mdc_toggle(); ++ op >>= 1; ++ } ++ ++ // /* set MDIO to output mode */ ++ // ifx_mdio_mode(ADM_SW_MDIO_OUTPUT); ++ ++ /* dummy clock */ ++ op = ADM_SW_BIT_MASK_4; ++ ifx_mdio_lo(); ++ while(op) ++ { ++ ifx_sw_mdc_pulse(); ++ op >>= 1; ++ } ++ ++ ifx_mdc_lo(); ++ ifx_mdio_lo(); ++ ifx_mdcs_hi(); ++ ++#endif ++ return 0; ++} ++ ++int ifx_sw_write(unsigned int addr, unsigned int dat) ++{ ++//605112:fchang.removed #ifdef ADM6996_MDC_MDIO_MODE //smi mode ////000001.joelin ++#ifdef CONFIG_SWITCH_ADM6996_MDIO //605112:fchang.added ++ ifx_sw_write_adm6996_smi(addr,dat); ++#else //000001.joelin ++ #ifdef CONFIG_SWITCH_GPIO_ACCESS //605112:fchang.added ++ ifx_sw_write_tantos(addr,dat); ++ #endif //605112:fchang.added ++#endif //000001.joelin ++ return 0; ++} ++ ++/* ++ do switch PHY reset ++*/ ++int ifx_sw_reset(void) ++{ ++ /* reset PHY */ ++ ifx_sw_write(ADM_SW_PHY_RESET, 0); ++ return 0; ++} ++ ++ ++static int ifx_sw_init(void) ++{ ++ ifx_printf(("Setting default ADM6996 registers... \n")); ++ /* ++ ifx_sw_write(0x11,0xe300); ++ ifx_sw_write(0x2e,0); ++ ifx_sw_write(0x13,0x1d5); ++ ifx_sw_write(0x14,0x1d5); ++ ifx_sw_write(0x15,0x1d5); ++ ifx_sw_write(0x16,0x1d5); ++ ifx_sw_write(0x17,0x1d5); ++ ifx_sw_write(0x19,0xffd5); ++ ifx_sw_write(0x1a,0xffd5); ++ ifx_sw_write(0x1b,0xffd5); ++ */ ++ return 0; ++} ++ ++ ++int adm_open(struct inode *node, struct file *filp) ++{ ++ //MOD_INC_USE_COUNT; ++ return 0; ++} ++ ++ssize_t adm_read(struct file *filep, char *buf, size_t count, loff_t *ppos) ++{ ++ return count; ++} ++ ++ssize_t adm_write(struct file *filep, const char *buf, size_t count, loff_t *ppos) ++{ ++ return count; ++} ++ ++/* close */ ++int adm_release(struct inode *inode, struct file *filp) ++{ ++ //MOD_DEC_USE_COUNT; ++ return 0; ++} ++ ++/* IOCTL function */ ++int adm_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long args) ++{ ++ ++ PREGRW uREGRW; ++ unsigned int rtval; ++ unsigned int val; ++ unsigned int control[6] ; ++ unsigned int status[6] ; ++ ++ if (_IOC_TYPE(cmd) != ADM_MAGIC) ++ { ++ printk("adm_ioctl: IOC_TYPE(%x) != ADM_MAGIC(%x)! \n", _IOC_TYPE(cmd), ADM_MAGIC); ++ return (-EINVAL); ++ } ++ ++ if(_IOC_NR(cmd) >= KEY_IOCTL_MAX_KEY) ++ { ++ printk(KERN_WARNING "adm_ioctl: IOC_NR(%x) invalid! \n", _IOC_NR(cmd)); ++ return (-EINVAL); ++ } ++ ++ switch (cmd) ++ { ++ case ADM_IOCTL_REGRW: ++ { ++ uREGRW = (PREGRW)kmalloc(sizeof(REGRW), GFP_KERNEL); ++ rtval = copy_from_user(uREGRW, (PREGRW)args, sizeof(REGRW)); ++ if (rtval != 0) ++ { ++ printk("ADM_IOCTL_REGRW: copy from user FAILED!! \n"); ++ return (-EFAULT); ++ } ++ ++ switch(uREGRW->mode) ++ { ++ case REG_READ: ++ uREGRW->value = 0x12345678;//inl(uREGRW->addr); ++ copy_to_user((PREGRW)args, uREGRW, sizeof(REGRW)); ++ break; ++ case REG_WRITE: ++ //outl(uREGRW->value, uREGRW->addr); ++ break; ++ ++ default: ++ printk("No such Register Read/Write function!! \n"); ++ return (-EFAULT); ++ } ++ kfree(uREGRW); ++ break; ++ } ++ ++ case ADM_SW_IOCTL_REGRW: ++ { ++ unsigned int val = 0xff; ++ ++ uREGRW = (PREGRW)kmalloc(sizeof(REGRW), GFP_KERNEL); ++ rtval = copy_from_user(uREGRW, (PREGRW)args, sizeof(REGRW)); ++ if (rtval != 0) ++ { ++ printk("ADM_IOCTL_REGRW: copy from user FAILED!! \n"); ++ return (-EFAULT); ++ } ++ ++ switch(uREGRW->mode) ++ { ++ case REG_READ: ++ ifx_sw_read(uREGRW->addr, &val); ++ uREGRW->value = val; ++ copy_to_user((PREGRW)args, uREGRW, sizeof(REGRW)); ++ break; ++ ++ case REG_WRITE: ++ ifx_sw_write(uREGRW->addr, uREGRW->value); ++ break; ++ default: ++ printk("No such Register Read/Write function!! \n"); ++ return (-EFAULT); ++ } ++ kfree(uREGRW); ++ break; ++ } ++ ++ //case ADM_SW_IOCTL_INIT: ++ // ifx_sw_init(); ++ // break; ++ ++ // others ++ default: ++ return -EFAULT; ++ } ++ // end of switch ++ ++ return 0; ++} ++ ++struct file_operations adm_ops = ++{ ++ read: adm_read, ++ write: adm_write, ++ open: adm_open, ++ release: adm_release, ++ ioctl: adm_ioctl ++}; ++ ++int adm_proc(char *buf, char **start, off_t offset, int count, int *eof, void *data) ++{ ++ int len = 0; ++ ++ len += sprintf(buf+len, " ************ Registers ************ \n"); ++ *eof = 1; ++ return len; ++} ++ ++ ++ ++int __init init_adm6996_module(void) ++{ ++ unsigned int val = 000; ++ unsigned int val1 = 000; ++ ++ ifx_sw_init(); ++ ++//605112:fchang.removed #ifdef ADM6996_MDC_MDIO_MODE //smi mode //000001.joelin ++#ifdef CONFIG_SWITCH_ADM6996_MDIO //605112:fchang.added ++ register_chrdev(69, "adm6996", &adm_ops); ++ *AMAZON_SE_PPE32_ETOP_MDIO_CFG=0; ++ *AMAZON_SE_PPE32_ENET_MAC_CFG &= ~0x18; //ENET0 MAC Configuration ++ ifx_sw_read(0xa0, &val); ++ ifx_sw_read(0xa1, &val1); ++ val=((val1&0x0f)<<16)|val; ++ printk ("\n6996I SMI Mode-"); ++ printk ("Chip ID:%5x \n ", val); ++ //ADM6996_MDC_MDIO_MODE //smi mode //000001.joelin ++#endif ++ ++#ifdef CONFIG_SWITCH_GPIO_ACCESS //605112:fchang.added ++ printk("Loading Tantos 0G GPIO driver\n"); ++ ifx_gpio_init(); ++ register_chrdev(69, "adm6996", &adm_ops); ++#endif //605112:fchang.added ++ return 0; ++} ++ ++void __exit cleanup_adm6996_module(void) ++{ ++ printk("Free 6996 device driver... \n"); ++ unregister_chrdev(69, "adm6996"); ++} ++ ++ ++static int ifx_hw_reset(void) ++{ ++ printk("Free 6996 device driver... \n"); ++ unregister_chrdev(69, "adm6996"); ++ udelay(200000); ++ ifx_sw_init(); ++ udelay(200000); ++ return init_adm6996_module(); ++} ++ ++ ++//int (*adm6996_hw_reset)(void) = ifx_hw_reset; ++//EXPORT_SYMBOL(adm6996_hw_reset); ++//int (*adm6996_sw_read)(unsigned int addr, unsigned int *data) = ifx_sw_read; ++//EXPORT_SYMBOL(adm6996_sw_read); ++//int (*adm6996_sw_write)(unsigned int addr, unsigned int data) = ifx_sw_write; ++//EXPORT_SYMBOL(adm6996_sw_write); ++ ++//EXPORT_SYMBOL(switch_model); ++EXPORT_SYMBOL(ifx_sw_read); ++EXPORT_SYMBOL(ifx_sw_write); ++ ++ ++MODULE_DESCRIPTION("ADMtek 6996 Driver"); ++MODULE_AUTHOR("Joe Lin "); ++MODULE_LICENSE("GPL"); ++ ++module_init(init_adm6996_module); ++module_exit(cleanup_adm6996_module); ++ +diff --git a/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_admmod.h b/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_admmod.h +new file mode 100644 +index 0000000..7f98fd3 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_admmod.h +@@ -0,0 +1,248 @@ ++/****************************************************************************** ++ Copyright (c) 2004, Infineon Technologies. All rights reserved. ++ ++ No Warranty ++ Because the program is licensed free of charge, there is no warranty for ++ the program, to the extent permitted by applicable law. Except when ++ otherwise stated in writing the copyright holders and/or other parties ++ provide the program "as is" without warranty of any kind, either ++ expressed or implied, including, but not limited to, the implied ++ warranties of merchantability and fitness for a particular purpose. The ++ entire risk as to the quality and performance of the program is with ++ you. should the program prove defective, you assume the cost of all ++ necessary servicing, repair or correction. ++ ++ In no event unless required by applicable law or agreed to in writing ++ will any copyright holder, or any other party who may modify and/or ++ redistribute the program as permitted above, be liable to you for ++ damages, including any general, special, incidental or consequential ++ damages arising out of the use or inability to use the program ++ (including but not limited to loss of data or data being rendered ++ inaccurate or losses sustained by you or third parties or a failure of ++ the program to operate with any other programs), even if such holder or ++ other party has been advised of the possibility of such damages. ++ ****************************************************************************** ++ Module : ifx_swdrv.h ++ Date : 2004-09-01 ++ Description : JoeLin ++ Remarks: ++ *****************************************************************************/ ++/****************************************************************************** ++** 2009/12/17 Lantiq Inc. Revised by Richard Hsu ++** Rename to amazon_se_admmod.h. ++** We use GPIO to simulate MDIO/MDC operations on AmazonSE WAVE board. ++** ASE WAVE board uses PHY2PHY connection to Tantos 0G ++** ++*******************************************************************************/ ++ ++ ++ ++ ++#ifndef _ADM_6996_MODULE_H_ ++#define _ADM_6996_MODULE_H_ ++ ++#include ++ ++//Wrapper for ASE GPIO setting ++#define AMAZON_SE_GPIO_P1_OUT IFX_GPIO_P1_OUT ++#define AMAZON_SE_GPIO_P1_ALTSEL0 IFX_GPIO_P1_ALTSEL0 ++#define AMAZON_SE_GPIO_P1_ALTSEL1 IFX_GPIO_P1_ALTSEL1 ++#define AMAZON_SE_GPIO_P1_DIR IFX_GPIO_P1_DIR ++#define AMAZON_SE_GPIO_P1_IN IFX_GPIO_P1_IN ++ ++#define ifx_printf(x) printk x ++ ++/* command codes */ ++#define ADM_SW_SMI_READ 0x02 ++#define ADM_SW_SMI_WRITE 0x01 ++#define ADM_SW_SMI_START 0x01 ++ ++#define ADM_SW_EEPROM_WRITE 0x01 ++#define ADM_SW_EEPROM_WRITE_ENABLE 0x03 ++#define ADM_SW_EEPROM_WRITE_DISABLE 0x00 ++#define EEPROM_TYPE 8 /* for 93C66 */ ++ ++/* bit masks */ ++#define ADM_SW_BIT_MASK_1 0x00000001 ++#define ADM_SW_BIT_MASK_2 0x00000002 ++#define ADM_SW_BIT_MASK_4 0x00000008 ++#define ADM_SW_BIT_MASK_10 0x00000200 ++#define ADM_SW_BIT_MASK_16 0x00008000 ++#define ADM_SW_BIT_MASK_32 0x80000000 ++ ++/* delay timers */ ++#define ADM_SW_MDC_DOWN_DELAY 5 ++#define ADM_SW_MDC_UP_DELAY 5 ++#define ADM_SW_CS_DELAY 5 ++ ++/* MDIO modes */ ++#define ADM_SW_MDIO_OUTPUT 1 ++#define ADM_SW_MDIO_INPUT 0 ++ ++#define ADM_SW_MAX_PORT_NUM 5 ++#define ADM_SW_MAX_VLAN_NUM 15 ++ ++/* registers */ ++#define ADM_SW_PORT0_CONF 0x1 ++#define ADM_SW_PORT1_CONF 0x3 ++#define ADM_SW_PORT2_CONF 0x5 ++#define ADM_SW_PORT3_CONF 0x7 ++#define ADM_SW_PORT4_CONF 0x8 ++#define ADM_SW_PORT5_CONF 0x9 ++#define ADM_SW_VLAN_MODE 0x11 ++#define ADM_SW_MAC_LOCK 0x12 ++#define ADM_SW_VLAN0_CONF 0x13 ++#define ADM_SW_PORT0_PVID 0x28 ++#define ADM_SW_PORT1_PVID 0x29 ++#define ADM_SW_PORT2_PVID 0x2a ++#define ADM_SW_PORT34_PVID 0x2b ++#define ADM_SW_PORT5_PVID 0x2c ++#define ADM_SW_PHY_RESET 0x2f ++#define ADM_SW_MISC_CONF 0x30 ++#define ADM_SW_BNDWDH_CTL0 0x31 ++#define ADM_SW_BNDWDH_CTL1 0x32 ++#define ADM_SW_BNDWDH_CTL_ENA 0x33 ++ ++/* port modes */ ++#define ADM_SW_PORT_FLOWCTL 0x1 /* 802.3x flow control */ ++#define ADM_SW_PORT_AN 0x2 /* auto negotiation */ ++#define ADM_SW_PORT_100M 0x4 /* 100M */ ++#define ADM_SW_PORT_FULL 0x8 /* full duplex */ ++#define ADM_SW_PORT_TAG 0x10 /* output tag on */ ++#define ADM_SW_PORT_DISABLE 0x20 /* disable port */ ++#define ADM_SW_PORT_TOS 0x40 /* TOS first */ ++#define ADM_SW_PORT_PPRI 0x80 /* port based priority first */ ++#define ADM_SW_PORT_MDIX 0x8000 /* auto MDIX on */ ++#define ADM_SW_PORT_PVID_SHIFT 10 ++#define ADM_SW_PORT_PVID_BITS 4 ++ ++/* VLAN */ ++#define ADM_SW_VLAN_PORT0 0x1 ++#define ADM_SW_VLAN_PORT1 0x2 ++#define ADM_SW_VLAN_PORT2 0x10 ++#define ADM_SW_VLAN_PORT3 0x40 ++#define ADM_SW_VLAN_PORT4 0x80 ++#define ADM_SW_VLAN_PORT5 0x100 ++ ++ ++/* GPIO 012 enabled, output mode */ ++#define GPIO_ENABLEBITS 0x000700f8 ++ ++/* ++ define AMAZON GPIO port to ADM6996 EEPROM interface ++ MDIO -> EEDI GPIO 16, AMAZON GPIO P1.0, bi-direction ++ MDC -> EESK GPIO 17, AMAZON GPIO P1.1, output only ++ MDCS -> EECS GPIO 18, AMAZON GPIO P1.2, output only ++ EEDO GPIO 15, AMAZON GPIO P0.15, do not need this one! */ ++ ++#define GPIO_MDIO 1 //P1.0 ++#define GPIO_MDC 2 //P1.1 ++#define GPIO_MDCS 4 //P1.2 ++ ++//joelin #define GPIO_MDIO 0 ++//joelin #define GPIO_MDC 5 /* PORT 0 GPIO5 */ ++//joelin #define GPIO_MDCS 6 /* PORT 0 GPIO6 */ ++ ++ ++#define MDIO_INPUT 0x00000001 ++#define MDIO_OUTPUT_EN 0x00010000 ++ ++ ++/* type definitions */ ++typedef unsigned char U8; ++typedef unsigned short U16; ++typedef unsigned int U32; ++ ++typedef struct _REGRW_ ++{ ++ unsigned int addr; ++ unsigned int value; ++ unsigned int mode; ++}REGRW, *PREGRW; ++ ++//joelin adm6996i ++typedef struct _MACENTRY_ ++{ ++ unsigned char mac_addr[6]; ++ unsigned long fid:4; ++ unsigned long portmap:6; ++ union { ++ unsigned long age_timer:9; ++ unsigned long info_ctrl:9; ++ } ctrl; ++ unsigned long occupy:1; ++ unsigned long info_type:1; ++ unsigned long bad:1; ++ unsigned long result:3;//000:command ok ,001:all entry used,010:Entry Not found ,011:try next entry ,101:command error ++ ++ }MACENTRY, *PMACENTRY; ++typedef struct _PROTOCOLFILTER_ ++{ ++ int protocol_filter_num;//[0~7] ++ int ip_p; //Value Compared with Protocol in IP Heade[7:0] ++ char action:2;//Action for protocol Filter . ++//00 = Protocol Portmap is Default Output Ports. ++//01 = Protocol Portmap is 6'b0. ++//10 = Protocol Portmap is the CPU port if the incoming port ++//is not the CPU port. But if the incoming port is the CPU port, then Type Portmap contains Default Output Ports, excluding the CPU port. ++ }PROTOCOLFILTER, *PPROTOCOLFILTER; ++ ++//joelin adm6996i ++ ++/* Santosh: for IGMP proxy/snooping */ ++ ++//050614:fchang int adm_process_mac_table_request (unsigned int cmd, struct _MACENTRY_ *mac); ++//050614:fchang int adm_process_protocol_filter_request (unsigned int cmd, struct _PROTOCOLFILTER_ *filter); ++ ++ ++/* IOCTL keys */ ++#define KEY_IOCTL_ADM_REGRW 0x01 ++#define KEY_IOCTL_ADM_SW_REGRW 0x02 ++#define KEY_IOCTL_ADM_SW_PORTSTS 0x03 ++#define KEY_IOCTL_ADM_SW_INIT 0x04 ++//for adm6996i-start ++#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_ADD 0x05 ++#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_DEL 0x06 ++#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_INIT 0x07 ++#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_MORE 0x08 ++#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_ADD 0x09 ++#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_DEL 0x0a ++#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_GET 0x0b ++ ++//adm6996i #define KEY_IOCTL_MAX_KEY 0x05 ++#define KEY_IOCTL_MAX_KEY 0x0c ++//for adm6996i-end ++/* IOCTL MAGIC */ ++#define ADM_MAGIC ('a'|'d'|'m'|'t'|'e'|'k') ++ ++/* IOCTL parameters */ ++#define ADM_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_REGRW, REGRW) ++#define ADM_SW_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_REGRW, REGRW) ++#define ADM_SW_IOCTL_PORTSTS _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_PORTSTS, NULL) ++#define ADM_SW_IOCTL_INIT _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_INIT, NULL) ++ ++ ++//6996i-stat ++#define ADM_SW_IOCTL_MACENTRY_ADD _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_ADD,MACENTRY) ++#define ADM_SW_IOCTL_MACENTRY_DEL _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_DEL,MACENTRY) ++#define ADM_SW_IOCTL_MACENTRY_GET_INIT _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_INIT,MACENTRY) ++#define ADM_SW_IOCTL_MACENTRY_GET_MORE _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_MORE,MACENTRY) ++#define ADM_SW_IOCTL_FILTER_ADD _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_ADD,PROTOCOLFILTER) ++#define ADM_SW_IOCTL_FILTER_DEL _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_DEL,PROTOCOLFILTER) ++#define ADM_SW_IOCTL_FILTER_GET _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_GET,PROTOCOLFILTER) ++ ++//6996i-end ++ ++ ++#define REG_READ 0x0 ++#define REG_WRITE 0x1 ++ ++/* undefine symbol */ ++//#define AMAZON_SW_REG(reg) *((volatile U32*)(reg)) ++//#define GPIO0_INPUT_MASK 0 ++//#define GPIO_conf0_REG 0x12345678 ++//#define GPIO_SET_HI ++//#define GPIO_SET_LOW ++ ++#endif ++/* _ADM_6996_MODULE_H_ */ +diff --git a/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_ref_board.c b/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_ref_board.c +new file mode 100644 +index 0000000..847d25d +--- /dev/null ++++ b/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_ref_board.c +@@ -0,0 +1,437 @@ ++/****************************************************************************** ++** ++** FILE NAME : amazon_se_ref_board.c ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : source file for Amazon-SE ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* ++struct ifx_si_eiu_config g_si_eiu_config = { ++ .irq = -1, // no serial input ++ .intsync = 0, ++ .sampling_clk = 0, ++ .shift_clk = 0, ++ .group = 0, ++ .active_high = 0, ++}; ++*/ ++ ++#if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDGPIO_USB_VBUS2) ++ #undef IFX_GPIO_USB_VBUS ++ #undef IFX_GPIO_USB_VBUS1 ++ #undef IFX_GPIO_USB_VBUS2 ++#endif ++ ++// GPIO PIN to Module Mapping and default PIN configuration ++struct ifx_gpio_ioctl_pin_config g_board_gpio_pin_map[] = { ++ // module_id of last item must be IFX_GPIO_PIN_AVAILABLE ++ {IFX_GPIO_MODULE_SSC, IFX_GPIO_PIN_ID(0, 8), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_IN | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR}, ++ {IFX_GPIO_MODULE_SSC, IFX_GPIO_PIN_ID(0, 9), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, ++ {IFX_GPIO_MODULE_SSC, IFX_GPIO_PIN_ID(0, 10), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, ++ ++ {IFX_GPIO_MODULE_SPI_FLASH, IFX_GPIO_PIN_ID(0, 7), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, ++ ++ // XWAY ASE WAVE board doesn't support shift register ++ //{IFX_GPIO_MODULE_LEDC, IFX_GPIO_PIN_ID(0, 1), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, ++ //{IFX_GPIO_MODULE_LEDC, IFX_GPIO_PIN_ID(0, 2), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, ++ //{IFX_GPIO_MODULE_LEDC, IFX_GPIO_PIN_ID(0, 3), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, ++ ++ /* ++ * GPIO LEDs (Amazon-SE Reference Board use GPIO to control LEDs) ++ */ ++ ++ // XWAY ASE WAVE board support only 2 LED. ++ // GPIO2 for ADSL_DAT , GPIO3 for ADSL_LINK ++ //{IFX_GPIO_MODULE_LED, IFX_GPIO_PIN_ID(0, 1), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, ++ {IFX_GPIO_MODULE_LED, IFX_GPIO_PIN_ID(0, 2), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, ++ {IFX_GPIO_MODULE_LED, IFX_GPIO_PIN_ID(0, 3), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, ++ //{IFX_GPIO_MODULE_LED, IFX_GPIO_PIN_ID(0, 4), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, ++ //{IFX_GPIO_MODULE_LED, IFX_GPIO_PIN_ID(0, 12), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, ++ //{IFX_GPIO_MODULE_LED, IFX_GPIO_PIN_ID(0, 13), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, ++ //{IFX_GPIO_MODULE_LED, IFX_GPIO_PIN_ID(1, 8), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, ++ //{IFX_GPIO_MODULE_LED, IFX_GPIO_PIN_ID(1, 11), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, ++ ++ /* ++ * USB ++ */ ++ #if defined(CONFIG_USB_HOST_IFX) || defined(CONFIG_USB_HOST_IFX_MODULE) ++ #if defined(IFX_LEDGPIO_USB_VBUS) ++ {IFX_GPIO_MODULE_LED, IFX_LEDGPIO_USB_VBUS, IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_PUDSEL_SET | IFX_GPIO_IOCTL_PIN_CONFIG_PUDEN_SET}, ++ #endif ++ #if defined(IFX_GPIO_USB_VBUS) ++ {IFX_GPIO_MODULE_USB, IFX_GPIO_USB_VBUS, IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_PUDSEL_SET | IFX_GPIO_IOCTL_PIN_CONFIG_PUDEN_SET}, ++ #endif ++ #endif ++ #if (defined(CONFIG_USB_HOST_IFX) || defined(CONFIG_USB_HOST_IFX_MODULE)) && defined(CONFIG_USB_HOST_IFX_LED) ++ {IFX_GPIO_MODULE_LED, IFX_LEDGPIO_USB_LED, IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, ++ #elif (defined(CONFIG_USB_GADGET_IFX) || defined(CONFIG_USB_GADGET_IFX_MODULE)) && defined(CONFIG_USB_GADGET_IFX_LED) ++// {IFX_GPIO_MODULE_LED, IFX_LEDGPIO_USB_LED, IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, ++ #endif ++ {IFX_GPIO_PIN_AVAILABLE, 0, 0}, ++}; ++EXPORT_SYMBOL(g_board_gpio_pin_map); ++ ++struct ifx_ledc_config_param g_board_ledc_hw_config = { ++ .operation_mask = IFX_LEDC_CFG_OP_UPDATE_SOURCE | IFX_LEDC_CFG_OP_BLINK | IFX_LEDC_CFG_OP_UPDATE_CLOCK | IFX_LEDC_CFG_OP_STORE_MODE | IFX_LEDC_CFG_OP_SHIFT_CLOCK | IFX_LEDC_CFG_OP_DATA_OFFSET | IFX_LEDC_CFG_OP_NUMBER_OF_LED | IFX_LEDC_CFG_OP_DATA | IFX_LEDC_CFG_OP_DATA_CLOCK_EDGE, ++ .source_mask = 3, ++ .source = 0, // by default all LEDs controlled by LEDC DATA ++ .blink_mask = (1 << 16) - 1, ++ .blink = 0, // disable blink for all LEDs ++ .update_clock = LED_CON1_UPDATE_SRC_SOFTWARE, ++ .fpid = 0, ++ .store_mode = 0, // single store ++ .fpis = 0, ++ .data_offset = 0, ++ .number_of_enabled_led = 0, // disable LEDC ++ .data_mask = (1 << 16) - 1, ++ .data = (1 << 2), // LED2 - Power LED turn on by default ++ .mips0_access_mask = (1 << 16) - 1, ++ .mips0_access = (1 << 16) - 1, ++ .f_data_clock_on_rising = 0, // falling edge ++}; ++EXPORT_SYMBOL(g_board_ledc_hw_config); ++ ++struct ifx_led_device g_board_led_hw_config[] = { ++#if defined(CONFIG_USB_HOST_IFX) || defined(CONFIG_USB_HOST_IFX_MODULE) ++ #if defined(IFX_LEDGPIO_USB_VBUS) ++ { ++ .name = "USB_VBUS", ++ .default_trigger = "USB_VBUS", ++ .phys_id = IFX_LEDGPIO_USB_VBUS, ++ .value_on = 1, ++ .value_off = 0, ++ .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, ++ }, ++ #endif ++#endif ++#if (defined(CONFIG_USB_HOST_IFX) || defined(CONFIG_USB_HOST_IFX_MODULE)) && defined(CONFIG_USB_HOST_IFX_LED) ++ { ++ .default_trigger = IFX_LED_TRIGGER_USB_LINK, ++ .phys_id = IFX_LEDGPIO_USB_LED, ++ .value_on = 0, ++ .value_off = 1, ++ .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, ++ }, ++#elif (defined(CONFIG_USB_GADGET_IFX) || defined(CONFIG_USB_GADGET_IFX_MODULE)) && defined(CONFIG_USB_GADGET_IFX_LED) ++ { ++// .default_trigger = IFX_LED_TRIGGER_USB_LINK, ++// .phys_id = IFX_LEDGPIO_USB_LED, ++// .value_on = 0, ++// .value_off = 1, ++// .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, ++ }, ++#endif ++ { ++ .name = "broadband_led", ++ //.default_trigger = IFX_LED_TRIGGER_DSL_LINK, ++ .default_trigger = NULL, ++ .phys_id = 3, ++ .value_on = 1, ++ .value_off = 0, ++ .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, ++ }, ++ { ++ .name = "internet_led", ++ //.default_trigger = IFX_LED_TRIGGER_DSL_DATA, ++ .default_trigger = NULL, ++ .phys_id = 2, ++ .value_on = 1, ++ .value_off = 0, ++ .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, ++ }, ++ // XWAY ASE WAVE board supports only 2 LEDs. ++/* ++ { ++ .default_trigger = IFX_LED_TRIGGER_EPHY_LINK, ++ .phys_id = 3, ++ .value_on = 1, ++ .value_off = 0, ++ .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, ++ }, ++ { ++ .default_trigger = IFX_LED_TRIGGER_EPHY_SPEED, ++ .phys_id = 4, ++ .value_on = 1, ++ .value_off = 0, ++ .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, ++ }, ++ { ++ .default_trigger = IFX_LED_TRIGGER_WAN_STATUS, ++ .phys_id = 12, ++ .value_on = 0, ++ .value_off = 1, ++ .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, ++ }, ++ { ++ .default_trigger = IFX_LED_TRIGGER_POWER_ON, ++ .phys_id = 13, ++ .value_on = 0, ++ .value_off = 1, ++ .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, ++ }, ++ { ++ .default_trigger = IFX_LED_TRIGGER_WARNING, ++ .phys_id = 24, ++ .value_on = 0, ++ .value_off = 1, ++ .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, ++ }, ++ { ++ .default_trigger = IFX_LED_TRIGGER_USB_LINK, ++ .phys_id = 27, ++ .value_on = 0, ++ .value_off = 1, ++ .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, ++ }, ++*/ ++ { ++ .flags = IFX_LED_DEVICE_FLAG_INVALID, ++ } ++}; ++EXPORT_SYMBOL(g_board_led_hw_config); ++ ++ ++#ifdef CONFIG_MTD_IFX_NOR ++ ++#if (CONFIG_MTD_IFX_NOR_FLASH_SIZE == 2) ++#define IFX_MTD_NOR_PARTITION_SIZE 0x001B0000 ++const struct mtd_partition g_ifx_mtd_nor_partitions[] = { ++ { ++ .name = "U-Boot", /* U-Boot firmware */ ++ .offset = 0x00000000, ++ .size = 0x00020000, //128K ++/* .mask_flags = MTD_WRITEABLE, force read-only */ ++ }, ++ { ++ .name = "firmware", /* firmware */ ++ .offset = 0x00020000, ++ .size = 0x00030000, //192K ++/* .mask_flags = MTD_WRITEABLE, force read-only */ ++ }, ++ { ++ .name = "rootfs,kernel,Data,Environment", /* default partition */ ++ .offset = 0x00050000, ++ .size = IFX_MTD_NOR_PARTITION_SIZE, ++/* .mask_flags = MTD_WRITEABLE, force read-only */ ++ }, ++}; ++#elif (CONFIG_MTD_IFX_NOR_FLASH_SIZE == 4) ++#define IFX_MTD_NOR_PARTITION_SIZE 0x003C0000 ++const struct mtd_partition g_ifx_mtd_nor_partitions[] = { ++ { ++ .name = "U-Boot", ++ .offset = 0x00000000, ++ .size = 0x00010000, ++/* .mask_flags = MTD_WRITEABLE, force read-only */ ++ }, ++ { ++ .name = "Firmware", ++ .offset = 0x00010000, ++ .size = 0x00030000, ++/* .mask_flags = MTD_WRITEABLE, force read-only */ ++ }, ++ { ++ .name = "RootFS,Kernel,Data,Environment", /* default partition */ ++ .offset = 0x00040000, ++ .size = IFX_MTD_NOR_PARTITION_SIZE, ++/* .mask_flags = MTD_WRITEABLE, force read-only */ ++ }, ++}; ++#elif (CONFIG_MTD_IFX_NOR_FLASH_SIZE == 8) ++#define IFX_MTD_NOR_PARTITION_SIZE 0x007A0000 ++const struct mtd_partition g_ifx_mtd_nor_partitions[] = { ++ { ++ .name = "U-Boot", /* U-Boot firmware */ ++ .offset = 0x00000000, ++ .size = 0x00020000, //128K ++/* .mask_flags = MTD_WRITEABLE, force read-only */ ++ }, ++ { ++ .name = "firmware", /* firmware */ ++ .offset = 0x00020000, ++ .size = 0x00040000, //256K ++/* .mask_flags = MTD_WRITEABLE, force read-only */ ++ }, ++ { ++ .name = "rootfs,kernel,Data,Environment", /* default partition */ ++ .offset = 0x00060000, ++ .size = IFX_MTD_NOR_PARTITION_SIZE, ++/* .mask_flags = MTD_WRITEABLE, force read-only */ ++ }, ++}; ++#else ++#error "Configure MTD NOR flash size first!!" ++#endif ++const int g_ifx_mtd_partion_num = ARRAY_SIZE(g_ifx_mtd_nor_partitions); ++ ++EXPORT_SYMBOL(g_ifx_mtd_nor_partitions); ++EXPORT_SYMBOL(g_ifx_mtd_partion_num); ++#endif /* CONFIG_IFX_MTD_NOR */ ++/*fix me, need more concept to define the partitions, and need add partition for 2M*/ ++#if defined(CONFIG_MTD_IFX_NAND) && !defined(CONFIG_MTD_CMDLINE_PARTS) ++ ++const struct mtd_partition g_ifx_mtd_nand_partitions[] = { ++#if (CONFIG_MTD_IFX_NAND_FLASH_SIZE == 4) ++ { ++ .name = "U-Boot", ++ .offset = 0x00000000, ++ .size = 0x00008000, ++ }, ++ { ++ .name = "kernel", ++ .offset = 0x00080000, ++ .size = 0x00100000, ++ }, ++ { ++ .name = "rootfs", ++ .offset = 0x00180000, ++ .size = 0x00220000, ++ }, ++ ++#elif (CONFIG_MTD_IFX_NAND_FLASH_SIZE == 8) ++ { ++ .name = "U-Boot", ++ .offset = 0x00000000, ++ .size = 0x00080000, ++ }, ++ { ++ .name = "kernel", ++ .offset = 0x00080000, ++ .size = 0x00200000, ++ }, ++ { ++ .name = "rootfs", ++ .offset = 0x00280000, ++ .size = 0x00510000, ++ }, ++#endif ++}; ++const int g_ifx_mtd_nand_partion_num = ARRAY_SIZE(g_ifx_mtd_nand_partitions); ++EXPORT_SYMBOL(g_ifx_mtd_nand_partion_num); ++EXPORT_SYMBOL(g_ifx_mtd_nand_partitions); ++#endif /* CONFIG_MTD_IFX_NAND */ ++ ++#if defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) ++/* ++ * spi flash partition information ++ * Here are partition information for all known series devices. ++ * See include/linux/mtd/partitions.h for definition of the mtd_partition ++ * structure. ++ */ ++#define IFX_MTD_SPI_PARTITION_2MB_SIZE 0x001B0000 ++#define IFX_MTD_SPI_PARTITION_4MB_SIZE 0x003A0000 ++ ++const struct mtd_partition g_ifx_mtd_spi_partitions[IFX_SPI_FLASH_MAX][IFX_MTD_SPI_PART_NB] = { ++ {{0, 0, 0}}, ++ ++/* 256K Byte */ ++ {{ ++ .name = "spi-boot", /* U-Boot firmware */ ++ .offset = 0x00000000, ++ .size = 0x00040000, /* 256 */ ++ /* mask_flags: MTD_WRITEABLE, force read-only */ ++ }, {0}, {0}, ++ }, ++ ++/* 512K Byte */ ++ {{0, 0, 0}}, ++ ++/* 1M Byte */ ++ {{ ++ .name = "spi-boot", /* U-Boot firmware */ ++ .offset = 0x00000000, ++ .size = 0x00010000, /* 64K */ ++ /* mask_flags: MTD_WRITEABLE, force read-only */ ++ }, ++ { ++ .name = "spi-firmware", /* firmware */ ++ .offset = 0x00010000, ++ .size = 0x00030000, /* 64K */ ++ /* mask_flags: MTD_WRITEABLE, force read-only */ ++ }, ++ { ++ .name = "spi-rootfs,kernel,Data,Environment", /* default partition */ ++ .offset = 0x00030000, ++ .size = 0x000C0000, ++ /* mask_flags: MTD_WRITEABLE, force read-only */ ++ }}, ++ ++/* 2M Byte */ ++ {{ ++ .name = "spi-boot", /* U-Boot firmware */ ++ .offset = 0x00000000, ++ .size = 0x00020000, /* 128K */ ++ /* mask_flags: MTD_WRITEABLE, force read-only */ ++ }, ++ { ++ .name = "spi-firmware", /* firmware */ ++ .offset = 0x00020000, ++ .size = 0x00030000, /* 192K */ ++ /* mask_flags: MTD_WRITEABLE, force read-only */ ++ }, ++ { ++ .name = "spi-rootfs,kernel,Data,Environment", /* default partition */ ++ .offset = 0x00050000, ++ .size = IFX_MTD_SPI_PARTITION_2MB_SIZE, ++ /* mask_flags: MTD_WRITEABLE, force read-only */ ++ }}, ++ ++/* 4M Byte */ ++ {{ ++ .name = "spi-boot", /* U-Boot firmware */ ++ .offset = 0x00000000, ++ .size = 0x00020000, /* 128K */ ++ /* mask_flags: MTD_WRITEABLE, force read-only */ ++ }, ++ { ++ .name = "spi-firmware", /* firmware */ ++ .offset = 0x00020000, ++ .size = 0x00040000, /* 256K */ ++ /* mask_flags: MTD_WRITEABLE, force read-only */ ++ }, ++ { ++ .name = "spi-rootfs,kernel,Data,Environment", /* default partition */ ++ .offset = 0x00060000, ++ .size = IFX_MTD_SPI_PARTITION_4MB_SIZE, ++ /* mask_flags: MTD_WRITEABLE, force read-only */ ++ }}, ++}; ++EXPORT_SYMBOL(g_ifx_mtd_spi_partitions); ++ ++#endif /* defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) */ ++ +diff --git a/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_ref_board.h b/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_ref_board.h +new file mode 100644 +index 0000000..1f193b1 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_ref_board.h +@@ -0,0 +1,55 @@ ++/****************************************************************************** ++** ++** FILE NAME : amazon_se_ref_board.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : header file for Amazon-SE ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef AMAZON_SE_REF_BOARD_H ++#define AMAZON_SE_REF_BOARD_H ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++ ++ ++#if defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) ++#define IFX_MTD_SPI_PART_NB 3 ++#define IFX_SPI_FLASH_MAX 6 ++#endif /* defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) */ ++ ++#if defined(CONFIG_USB_HOST_IFX) || defined(CONFIG_USB_HOST_IFX_MODULE) ++ #if 1 // Control VBus through LED abstract layer ++ #define IFX_LEDGPIO_USB_VBUS IFX_GPIO_PIN_ID(1, 7) ++ #else // Control VBus through GPIO driver directly ++ #define IFX_GPIO_USB_VBUS IFX_GPIO_PIN_ID(1, 7) ++ #endif ++#endif ++ ++#if (defined(CONFIG_USB_HOST_IFX) || defined(CONFIG_USB_HOST_IFX_MODULE)) && defined(CONFIG_USB_HOST_IFX_LED) ++// #define IFX_LEDGPIO_USB_LED IFX_GPIO_PIN_ID(1, 11) ++#elif (defined(CONFIG_USB_GADGET_IFX) || defined(CONFIG_USB_GADGET_IFX_MODULE)) && defined(CONFIG_USB_GADGET_IFX_LED) ++// #define IFX_LEDGPIO_USB_LED IFX_GPIO_PIN_ID(1, 11) ++#endif ++ ++ ++ ++#endif /* AMAZON_SE_REF_BOARD_H */ ++ +diff --git a/arch/mips/include/asm/ifx/amazon_se/boards/boards.h b/arch/mips/include/asm/ifx/amazon_se/boards/boards.h +new file mode 100644 +index 0000000..3a31400 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/amazon_se/boards/boards.h +@@ -0,0 +1,4 @@ ++#if defined(CONFIG_AMAZON_SE_REF_BOARD) ++# include "./amazon_se_ref_board.h" ++#endif ++ +diff --git a/arch/mips/include/asm/ifx/amazon_se/irq.h b/arch/mips/include/asm/ifx/amazon_se/irq.h +new file mode 100644 +index 0000000..885b8d2 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/amazon_se/irq.h +@@ -0,0 +1,116 @@ ++/****************************************************************************** ++** ++** FILE NAME : irq.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : header file for Amazon-SE ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef AMAZON_SE_IRQ ++#define AMAZON_SE_IRQ ++ ++ ++ ++/****** Interrupt Assigments ***********/ ++ ++#define IFX_ASC1_TIR INT_NUM_IM2_IRL0 // INT_NUM_IM0_IRL0 ++#define IFX_ASC1_TBIR INT_NUM_IM2_IRL1 // INT_NUM_IM0_IRL1 ++#define IFX_ASC1_RIR INT_NUM_IM2_IRL2 // INT_NUM_IM0_IRL2 ++#define IFX_ASC1_EIR INT_NUM_IM2_IRL3 // INT_NUM_IM0_IRL3 ++#define IFX_ASC1_ABSTIR INT_NUM_IM2_IRL4 // INT_NUM_IM0_IRL4 ++#define IFX_ASC1_ABDETIR INT_NUM_IM2_IRL5 // INT_NUM_IM0_IRL5 ++#define IFX_ASC1_SFCIR INT_NUM_IM2_IRL6 // INT_NUM_IM0_IRL6 ++ ++#define IFX_FPI_SLAVE_BCU0_IR INT_NUM_IM2_IRL7 // INT_NUM_IM0_IRL7 ++#define IFX_FPI_MASTER_COSBCU_IR INT_NUM_IM2_IRL8 // INT_NUM_IM0_IRL8 ++#define IFX_FPI_SLAVE_BCU_IRQ IFX_FPI_SLAVE_BCU0_IR ++#define IFX_FPI_MASTER_BCU_IRQ IFX_FPI_MASTER_COSBCU_IR ++ ++#define IFX_DSL_DFE_IR INT_NUM_IM2_IRL9 // INT_NUM_IM0_IRL9 ++#define IFX_DSL_AFEOVL_IR INT_NUM_IM2_IRL10 // INT_NUM_IM0_IRL10 ++#define IFX_DSL_DYING_GASP_INT INT_NUM_IM2_IRL11 // INT_NUM_IM0_IRL11 ++#define IFX_DSL_DFE_INT0IR INT_NUM_IM1_IRL16 // INT_NUM_IM3_IRL16 ++#define IFX_DSL_DFE_INT1IR INT_NUM_IM1_IRL17 // INT_NUM_IM3_IRL17 ++#define IFX_DSL_DFE_INT2IR INT_NUM_IM1_IRL18 // INT_NUM_IM3_IRL18 ++#define IFX_DSL_DFE_INT3IR INT_NUM_IM1_IRL19 // INT_NUM_IM3_IRL19 ++#define IFX_MEI_INT IFX_DSL_DFE_IR ++#define IFX_MEI_DYING_GASP_INT IFX_DSL_DYING_GASP_INT ++#define IFX_DSL_DFE_TXIR IFX_DSL_DFE_INT0IR ++#define IFX_DSL_DFE_RXIR IFX_DSL_DFE_INT1IR ++ ++#define IFX_DMA_CH0_INT INT_NUM_IM3_IRL0 // INT_NUM_IM1_IRL0 ++#define IFX_DMA_CH1_INT INT_NUM_IM3_IRL1 // INT_NUM_IM1_IRL1 ++#define IFX_DMA_CH2_INT INT_NUM_IM3_IRL2 // INT_NUM_IM1_IRL2 ++#define IFX_DMA_CH3_INT INT_NUM_IM3_IRL3 // INT_NUM_IM1_IRL3 ++#define IFX_DMA_CH4_INT INT_NUM_IM3_IRL4 // INT_NUM_IM1_IRL4 ++#define IFX_DMA_CH5_INT INT_NUM_IM3_IRL5 // INT_NUM_IM1_IRL5 ++#define IFX_DMA_CH6_INT INT_NUM_IM3_IRL6 // INT_NUM_IM1_IRL6 ++#define IFX_DMA_CH7_INT INT_NUM_IM3_IRL7 // INT_NUM_IM1_IRL7 ++#define IFX_DMA_CH8_INT INT_NUM_IM3_IRL8 // INT_NUM_IM1_IRL8 ++#define IFX_DMA_CH9_INT INT_NUM_IM3_IRL9 // INT_NUM_IM1_IRL9 ++ ++#define IFX_PPE_MBOX_INT0 INT_NUM_IM2_IRL12 // INT_NUM_IM0_IRL12 ++#define IFX_PPE_MBOX_INT1 INT_NUM_IM2_IRL13 // INT_NUM_IM0_IRL13 ++#define IFX_PPE_MBOX_INT2 INT_NUM_IM2_IRL14 // INT_NUM_IM0_IRL14 ++#define IFX_PPE_QSB_INT INT_NUM_IM2_IRL15 // INT_NUM_IM0_IRL15 ++ ++#define IFX_EPHY_INT INT_NUM_IM3_IRL29 // INT_NUM_IM1_IRL29 ++ ++#define IFX_EIU_IR0 INT_NUM_IM2_IRL21 // INT_NUM_IM0_IRL21 ++#define IFX_EIU_IR1 INT_NUM_IM0_IRL22 // INT_NUM_IM2_IRL22 ++#define IFX_EIU_IR2 INT_NUM_IM2_IRL23 // INT_NUM_IM0_IRL23 ++ ++#define IFX_GPTU_TC1A INT_NUM_IM2_IRL25 // INT_NUM_IM0_IRL25 ++#define IFX_GPTU_TC1B INT_NUM_IM2_IRL26 // INT_NUM_IM0_IRL26 ++#define IFX_GPTU_TC2A INT_NUM_IM2_IRL27 // INT_NUM_IM0_IRL27 ++#define IFX_GPTU_TC2B INT_NUM_IM2_IRL28 // INT_NUM_IM0_IRL28 ++#define IFX_GPTU_TC3A INT_NUM_IM2_IRL29 // INT_NUM_IM0_IRL29 ++#define IFX_GPTU_TC3B INT_NUM_IM2_IRL30 // INT_NUM_IM0_IRL30 ++ ++#define IFX_MC_IR INT_NUM_IM3_IRL24 // INT_NUM_IM1_IRL24 ++ ++#define IFX_EBU_IR INT_NUM_IM2_IRL24 // INT_NUM_IM0_IRL24 ++ ++#define IFX_PMC_HIT_IR INT_NUM_IM3_IRL25 // INT_NUM_IM1_IRL25 ++#define IFX_PMC_MISS_IR INT_NUM_IM3_IRL23 // INT_NUM_IM1_IRL23 ++#define IFX_PMCIR IFX_PMC_HIT_IR ++ ++#define IFX_SBIU_ERRIR INT_NUM_IM3_IRL26 // INT_NUM_IM1_IRL26 ++ ++#define IFX_SSC_RIR INT_NUM_IM2_IRL16 // INT_NUM_IM0_IRL16 ++#define IFX_SSC_TIR INT_NUM_IM2_IRL17 // INT_NUM_IM0_IRL17 ++#define IFX_SSC_EIR INT_NUM_IM2_IRL18 // INT_NUM_IM0_IRL18 ++#define IFX_SSC_FIR INT_NUM_IM2_IRL19 // INT_NUM_IM0_IRL19 ++ ++#define IFX_MMC_CONTROLLER_INTR0_IRQ INT_NUM_IM1_IRL20 // INT_NUM_IM3_IRL20 ++#define IFX_MMC_CONTROLLER_INTR1_IRQ INT_NUM_IM1_IRL21 // INT_NUM_IM3_IRL21 ++#define IFX_MMC_CONTROLLER_SDIO_I_IRQ INT_NUM_IM1_IRL22 // INT_NUM_IM3_IRL22 ++ ++#define IFX_USB0_IR INT_NUM_IM2_IRL31 // INT_NUM_IM0_IRL31 ++#define IFX_USB0_OCIR INT_NUM_IM2_IRL20 // INT_NUM_IM0_IRL20 ++#define IFX_USB_INT IFX_USB0_IR ++#define IFX_USB_OC_INT IFX_USB0_OCIR ++ ++#define IFX_WDT_PIR INT_NUM_IM3_IRL27 // INT_NUM_IM1_IRL27 ++#define IFX_WDT_AEIR INT_NUM_IM3_IRL28 // INT_NUM_IM1_IRL28 ++ ++ ++ ++#endif // AMAZON_SE_IRQ +diff --git a/arch/mips/include/asm/ifx/amazon_se/model.h b/arch/mips/include/asm/ifx/amazon_se/model.h +new file mode 100644 +index 0000000..58fd0c8 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/amazon_se/model.h +@@ -0,0 +1,54 @@ ++/****************************************************************************** ++** ++** FILE NAME : model.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : header file for Amazon-SE ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef AMAZON_SE_MODEL_H ++#define AMAZON_SE_MODEL_H ++/****************************************************************************** ++ Copyright (c) 2002, Infineon Technologies. All rights reserved. ++ ++ No Warranty ++ Because the program is licensed free of charge, there is no warranty for ++ the program, to the extent permitted by applicable law. Except when ++ otherwise stated in writing the copyright holders and/or other parties ++ provide the program "as is" without warranty of any kind, either ++ expressed or implied, including, but not limited to, the implied ++ warranties of merchantability and fitness for a particular purpose. The ++ entire risk as to the quality and performance of the program is with ++ you. should the program prove defective, you assume the cost of all ++ necessary servicing, repair or correction. ++ ++ In no event unless required by applicable law or agreed to in writing ++ will any copyright holder, or any other party who may modify and/or ++ redistribute the program as permitted above, be liable to you for ++ damages, including any general, special, incidental or consequential ++ damages arising out of the use or inability to use the program ++ (including but not limited to loss of data or data being rendered ++ inaccurate or losses sustained by you or third parties or a failure of ++ the program to operate with any other programs), even if such holder or ++ other party has been advised of the possibility of such damages. ++******************************************************************************/ ++#define BOARD_SYSTEM_TYPE "Amazon-SE" ++#define SYSTEM_MODEL_NAME "Amazon-SE Reference Board" ++#endif +diff --git a/arch/mips/include/asm/ifx/ar10/ar10.h b/arch/mips/include/asm/ifx/ar10/ar10.h +new file mode 100644 +index 0000000..2da2d82 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ar10/ar10.h +@@ -0,0 +1,1705 @@ ++/****************************************************************************** ++** ++** FILE NAME : ar10.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : header file for AR10 ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef AR10_H ++#define AR10_H ++ ++#include ++/****************************************************************************** ++ Copyright (c) 2002, Infineon Technologies. All rights reserved. ++ ++ No Warranty ++ Because the program is licensed free of charge, there is no warranty for ++ the program, to the extent permitted by applicable law. Except when ++ otherwise stated in writing the copyright holders and/or other parties ++ provide the program "as is" without warranty of any kind, either ++ expressed or implied, including, but not limited to, the implied ++ warranties of merchantability and fitness for a particular purpose. The ++ entire risk as to the quality and performance of the program is with ++ you. should the program prove defective, you assume the cost of all ++ necessary servicing, repair or correction. ++ ++ In no event unless required by applicable law or agreed to in writing ++ will any copyright holder, or any other party who may modify and/or ++ redistribute the program as permitted above, be liable to you for ++ damages, including any general, special, incidental or consequential ++ damages arising out of the use or inability to use the program ++ (including but not limited to loss of data or data being rendered ++ inaccurate or losses sustained by you or third parties or a failure of ++ the program to operate with any other programs), even if such holder or ++ other party has been advised of the possibility of such damages. ++******************************************************************************/ ++#define MACH_GROUP_IFX MACH_GROUP_AR10 ++#define MACH_TYPE_IFX MACH_AR10 ++ ++ ++/***********************************************************************/ ++/* Module : WDT register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_WDT (KSEG1 | 0x1F880000) ++ ++/***Watchdog Timer Control Register ***/ ++#define IFX_WDT_CR ((volatile u32*)(IFX_WDT + 0x03F0)) ++#define IFX_WDT_CR_GEN (1 << 31) ++#define IFX_WDT_CR_DSEN (1 << 30) ++#define IFX_WDT_CR_LPEN (1 << 29) ++#define IFX_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1)) ++#define IFX_WDT_CR_PWL_SET(value) (((( 1 << 2) - 1) & (value)) << 26) ++#define IFX_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1)) ++#define IFX_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24) ++#define IFX_WDT_CR_PW_GET(value) (((value) >> 16) & ((1 << 8) - 1)) ++#define IFX_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16) ++#define IFX_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1)) ++#define IFX_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0) ++ ++/***Watchdog Timer Status Register***/ ++#define IFX_WDT_SR ((volatile u32*)(IFX_WDT + 0x03F8)) ++#define IFX_WDT_SR_EN (1 << 31) ++#define IFX_WDT_SR_AE (1 << 30) ++#define IFX_WDT_SR_PRW (1 << 29) ++#define IFX_WDT_SR_EXP (1 << 28) ++#define IFX_WDT_SR_PWD (1 << 27) ++#define IFX_WDT_SR_DS (1 << 26) ++#define IFX_WDT_SR_VALUE_GET(value) (((value) >> 0) & ((1 << 16) - 1)) ++#define IFX_WDT_SR_VALUE_SET(value) (((( 1 << 16) - 1) & (value)) << 0) ++ ++ ++ ++/***********************************************************************/ ++/* Module : RCU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_RCU (KSEG1 | 0x1F203000) ++ ++/* Reset Request Register */ ++#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) ++#define IFX_RCU_RST_REQ_HOT_RST 0x00000001 /* Hot reset, domain 0*/ ++ ++#define IFX_RCU_RST_STAT ((volatile u32*)(IFX_RCU + 0x0014)) ++#define IFX_RCU_USB0_CFG ((volatile u32*)(IFX_RCU + 0x0018)) ++#define IFX_RCU_GPIO_STRAP ((volatile u32*)(IFX_RCU + 0x001C)) ++#define IFX_RCU_GPHY0_FW_ADDR ((volatile u32*)(IFX_RCU + 0x0020)) ++#define IFX_RCU_SLIC_USB_RST_STAT ((volatile u32*)(IFX_RCU + 0x0024)) ++#define IFX_RCU_PCI_BOOT_READY ((volatile u32*)(IFX_RCU + 0x0028)) ++#define IFX_RCU_PPE_CONF ((volatile u32*)(IFX_RCU + 0x002C)) ++#define IFX_RCU_PCIE_PHY_CON_STAT ((volatile u32*)(IFX_RCU + 0x0030)) ++#define IFX_RCU_USB1_CFG ((volatile u32*)(IFX_RCU + 0x0034)) ++#define IFX_RCU_USB_AFE_CFG_1A ((volatile u32*)(IFX_RCU + 0x0038)) ++#define IFX_RCU_USB_AFE_CFG_1B ((volatile u32*)(IFX_RCU + 0x003C)) ++#define IFX_RCU_USB_AFE_CFG_2A ((volatile u32*)(IFX_RCU + 0x0040)) ++#define IFX_RCU_USB_AFE_CFG_2B ((volatile u32*)(IFX_RCU + 0x0044)) ++#define IFX_RCU_SLIC_USB_RST_REQ ((volatile u32*)(IFX_RCU + 0x0048)) ++ ++/* AHB Endian Register */ ++#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) ++ ++#define IFX_RCU_BE_AHB4S 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ ++#define IFX_RCU_BE_AHB3M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ ++#define IFX_RCU_BE_USIF 0x00000004 /* Configure AHB slave port that connects to USIF in big endian */ ++#define IFX_RCU_BE_AHB2S 0x00000008 /* Configure AHB slave port that connects to XBAR in big endian */ ++#define IFX_RCU_BE_PCIE0S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in big endian */ ++#define IFX_RCU_BE_PCIE0_DBI 0x00000020 /* Configure DBI module in big endian */ ++#define IFX_RCU_BE_DCDC_PDI 0x00000040 /* Configure DC PDI module in big endian */ ++#define IFX_RCU_BE_PCIE0_PDI 0x00000080 /* Configure PCIE PDI module in big endian */ ++#define IFX_RCU_BE_PCIE1S 0x00000100 /* Configure AHB slave port that connects to PCIe1 RC in big endian */ ++#define IFX_RCU_BE_PCIE1_DBI 0x00000200 /* Configure DBI1 module in big endian */ ++#define IFX_RCU_BE_PCIE1_PDI 0x00000400 /* Configure PCIE1 PDI module in big endian */ ++#define IFX_RCU_BE_AHB1S 0x00000800 /* Configure PCIE1 PDI module in big endian */ ++#define IFX_RCU_BE_PCIE0M 0x00001000 /* RC0 Master as big endian */ ++#define IFX_RCU_BE_PCIE1M 0x00002000 /* RC1 Master as big endian */ ++ ++#define IFX_RCU_CPU_CFG ((volatile u32*)(IFX_RCU + 0x0060)) ++#define IFX_RCU_GPHY1_FW_ADDR ((volatile u32*)(IFX_RCU + 0x0068)) ++ ++/* Reset Request Register */ ++#define IFX_RCU_RST_REQ_SRST (1 << 30) ++ ++/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */ ++#define IFX_RCU_RST_REQ_ALL IFX_RCU_RST_REQ_SRST ++ ++#define IFX_RCU_RST_REQ_DFE (1 << 7) ++#define IFX_RCU_RST_REQ_AFE (1 << 11) ++#define IFX_RCU_RST_REQ_ARC_JTAG (1 << 20) ++ ++ ++/***********************************************************************/ ++/* Module : BCU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_BCU_BASE_ADDR (KSEG1 | 0x1E100000) ++#define IFX_SLAVE_BCU_BASE_ADDR (KSEG1 | 0x1C200400) ++ ++/***BCU Control Register (0010H)***/ ++#define IFX_BCU_CON ((volatile u32*)(0x0010 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_CON ((volatile u32*)(0x0010 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_STARVATION_MASK (0xFF << 24) ++#define IFX_BCU_STARVATION_SHIFT 24 ++#define IFX_BCU_TOUT_MASK 0xFFFF ++#define IFX_BCU_CON_SPC(value) (((( 1 << 8) - 1) & (value)) << 24) ++#define IFX_BCU_CON_SPE (1 << 19) ++#define IFX_BCU_CON_PSE (1 << 18) ++#define IFX_BCU_CON_DBG (1 << 16) ++#define IFX_BCU_CON_TOUT(value) (((( 1 << 16) - 1) & (value)) << 0) ++ ++/***BCU Error Control Capture Register (0020H)***/ ++#define IFX_BCU_ECON ((volatile u32*)(0x0020 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_ECON ((volatile u32*)(0x0020 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_ECON_TAG(value) (((( 1 << 4) - 1) & (value)) << 24) ++#define IFX_BCU_ECON_RDN (1 << 23) ++#define IFX_BCU_ECON_WRN (1 << 22) ++#define IFX_BCU_ECON_SVM (1 << 21) ++#define IFX_BCU_ECON_ACK(value) (((( 1 << 2) - 1) & (value)) << 19) ++#define IFX_BCU_ECON_ABT (1 << 18) ++#define IFX_BCU_ECON_RDY (1 << 17) ++#define IFX_BCU_ECON_TOUT (1 << 16) ++#define IFX_BCU_ECON_ERRCNT(value) (((( 1 << 16) - 1) & (value)) << 0) ++#define IFX_BCU_ECON_OPC(value) (((( 1 << 4) - 1) & (value)) << 28) ++ ++/***BCU Error Address Capture Register (0024 H)***/ ++#define IFX_BCU_EADD ((volatile u32*)(0x0024 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_EADD ((volatile u32*)(0x0024 + IFX_SLAVE_BCU_BASE_ADDR)) ++ ++/***BCU Error Data Capture Register (0028H)***/ ++#define IFX_BCU_EDAT ((volatile u32*)(0x0028 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_EDAT ((volatile u32*)(0x0028 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_IRNICR ((volatile u32*)(0x00F8 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_IRNICR ((volatile u32*)(0x00F8 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_IRNCR ((volatile u32*)(0x00FC + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_IRNCR ((volatile u32*)(0x00FC + IFX_SLAVE_BCU_BASE_ADDR)) ++ ++ ++ ++/***********************************************************************/ ++/* Module : MEI register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_MEI_SPACE_ACCESS (KSEG1 | 0x1E116000) ++#define IFX_DFE_LDST_BASE_ADDR (KSEG1 | 0x1EF00000) ++ ++/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/ ++#if 0 ++#define MEI_DATA_XFR ((volatile u32*)(0x0000 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_VERSION ((volatile u32*)(0x0004 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_ARC_GP_STAT ((volatile u32*)(0x0008 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_DATA_XFR_STAT ((volatile u32*)(0x000C + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XFR_ADDR ((volatile u32*)(0x0010 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_MAX_WAIT ((volatile u32*)(0x0014 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_TO_ARC_INT ((volatile u32*)(0x0018 + IFX_MEI_SPACE_ACCESS)) ++#define ARC_TO_MEI_INT ((volatile u32*)(0x0004 + IFX_MEI_SPACE_ACCESS)) ++#define ARC_TO_MEI_INT_MASK ((volatile u32*)(0x0020 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_DEBUG_WAD ((volatile u32*)(0x0024 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_DEBUG_RAD ((volatile u32*)(0x0028 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_DEBUG_DATA ((volatile u32*)(0x002C + IFX_MEI_SPACE_ACCESS)) ++#define MEI_DEBUG_DEC ((volatile u32*)(0x0030 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_CONFIG ((volatile u32*)(0x0034 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_RST_CONTROL ((volatile u32*)(0x0038 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_DBG_MASTER ((volatile u32*)(0x003C + IFX_MEI_SPACE_ACCESS)) ++#define MEI_CLK_CONTROL ((volatile u32*)(0x0040 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_BIST_CONTROL ((volatile u32*)(0x0044 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_BIST_STAT ((volatile u32*)(0x0048 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XDATA_BASE_SH ((volatile u32*)(0x004c + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XDATA_BASE ((volatile u32*)(0x0050 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR_BASE ((volatile u32*)(0x0054 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR0 ((volatile u32*)(0x0054 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR1 ((volatile u32*)(0x0058 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR2 ((volatile u32*)(0x005C + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR3 ((volatile u32*)(0x0060 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR4 ((volatile u32*)(0x0064 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR5 ((volatile u32*)(0x0068 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR6 ((volatile u32*)(0x006C + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR7 ((volatile u32*)(0x0070 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR8 ((volatile u32*)(0x0074 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR9 ((volatile u32*)(0x0078 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR10 ((volatile u32*)(0x007C + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR11 ((volatile u32*)(0x0080 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR12 ((volatile u32*)(0x0084 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR13 ((volatile u32*)(0x0088 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR14 ((volatile u32*)(0x008C + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR15 ((volatile u32*)(0x0090 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR16 ((volatile u32*)(0x0094 + IFX_MEI_SPACE_ACCESS)) ++ ++ ++#define MEI_VERSION ((volatile u32*)(0x0000 + IFX_MEI_SPACE_ACCESS)) ++#define ARC_TO_MEI_INT ((volatile u32*)(0x0004 + IFX_MEI_SPACE_ACCESS)) ++#define ARC_TO_MEI_INT_MASK ((volatile u32*)(0x0008 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_TO_ARC_INT ((volatile u32*)(0x000C + IFX_MEI_SPACE_ACCESS)) ++#define ME_ME2ARC_STAT ((volatile u32*)(0x0010 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_CLK_CONTROL ((volatile u32*)(0x0014 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_RST_CONTROL ((volatile u32*)(0x0018 + IFX_MEI_SPACE_ACCESS)) ++#define ME_CHIP_CONFIG ((volatile u32*)(0x001C + IFX_MEI_SPACE_ACCESS)) ++#define MEI_DBG_MASTER ((volatile u32*)(0x0020 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_DEBUG_DEC ((volatile u32*)(0x0024 + IFX_MEI_SPACE_ACCESS)) ++#define ME_DBG_PORT_SEL ((volatile u32*)(0x0028 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_DEBUG_RAD ((volatile u32*)(0x002C + IFX_MEI_SPACE_ACCESS)) ++#define MEI_DEBUG_WAD ((volatile u32*)(0x0030 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_DEBUG_DATA ((volatile u32*)(0x0034 + IFX_MEI_SPACE_ACCESS)) ++#define ME_DX_PORT_SEL ((volatile u32*)(0x0038 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XFR_ADDR ((volatile u32*)(0x003C + IFX_MEI_SPACE_ACCESS)) ++#define MEI_DATA_XFR ((volatile u32*)(0x0040 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_DATA_XFR_STAT ((volatile u32*)(0x0044 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_MAX_WAIT ((volatile u32*)(0x0048 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_ARC_GP_STAT ((volatile u32*)(0x004C + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XDATA_BASE_SH ((volatile u32*)(0x0050 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XDATA_BASE ((volatile u32*)(0x0054 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR_BASE ((volatile u32*)(0x0058 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR0 ((volatile u32*)(0x0058 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR1 ((volatile u32*)(0x005C + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR2 ((volatile u32*)(0x0060 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR3 ((volatile u32*)(0x0064 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR4 ((volatile u32*)(0x0068 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR5 ((volatile u32*)(0x006C + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR6 ((volatile u32*)(0x0070 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR7 ((volatile u32*)(0x0074 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR8 ((volatile u32*)(0x0078 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR9 ((volatile u32*)(0x007C + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR10 ((volatile u32*)(0x0080 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR11 ((volatile u32*)(0x0084 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR12 ((volatile u32*)(0x0088 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR13 ((volatile u32*)(0x008C + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR14 ((volatile u32*)(0x0090 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR15 ((volatile u32*)(0x0094 + IFX_MEI_SPACE_ACCESS)) ++#define MEI_XMEM_BAR16 ((volatile u32*)(0x0098 + IFX_MEI_SPACE_ACCESS)) ++//#else ++#define ME_VERSION ((volatile u32*)(0x0000 + IFX_MEI_SPACE_ACCESS)) ++#define ME_ARC2ME_STAT ((volatile u32*)(0x0004 + IFX_MEI_SPACE_ACCESS)) ++#define ME_ARC2ME_MASK ((volatile u32*)(0x0008 + IFX_MEI_SPACE_ACCESS)) ++#define ME_ME2ARC_INT ((volatile u32*)(0x000C + IFX_MEI_SPACE_ACCESS)) ++#define ME_ME2ARC_STAT ((volatile u32*)(0x0010 + IFX_MEI_SPACE_ACCESS)) ++#define ME_CLK_CTRL ((volatile u32*)(0x0014 + IFX_MEI_SPACE_ACCESS)) ++#define ME_RST_CTRL ((volatile u32*)(0x0018 + IFX_MEI_SPACE_ACCESS)) ++#define ME_CHIP_CONFIG ((volatile u32*)(0x001C + IFX_MEI_SPACE_ACCESS)) ++#define ME_DBG_MASTER ((volatile u32*)(0x0020 + IFX_MEI_SPACE_ACCESS)) ++#define ME_DBG_DECODE ((volatile u32*)(0x0024 + IFX_MEI_SPACE_ACCESS)) ++#define ME_DBG_PORT_SEL ((volatile u32*)(0x0028 + IFX_MEI_SPACE_ACCESS)) ++#define ME_DBG_RD_AD ((volatile u32*)(0x002C + IFX_MEI_SPACE_ACCESS)) ++#define ME_DBG_WR_AD ((volatile u32*)(0x0030 + IFX_MEI_SPACE_ACCESS)) ++#define ME_DBG_DATA ((volatile u32*)(0x0034 + IFX_MEI_SPACE_ACCESS)) ++#define ME_DX_PORT_SEL ((volatile u32*)(0x0038 + IFX_MEI_SPACE_ACCESS)) ++#define ME_DX_AD ((volatile u32*)(0x003C + IFX_MEI_SPACE_ACCESS)) ++#define ME_DX_DATA ((volatile u32*)(0x0040 + IFX_MEI_SPACE_ACCESS)) ++#define ME_DX_STAT ((volatile u32*)(0x0044 + IFX_MEI_SPACE_ACCESS)) ++#define ME_DX_MWS ((volatile u32*)(0x0048 + IFX_MEI_SPACE_ACCESS)) ++#define ME_ARC_GP_STAT ((volatile u32*)(0x004C + IFX_MEI_SPACE_ACCESS)) ++#define ME_XDATA_BASE_SH ((volatile u32*)(0x0050 + IFX_MEI_SPACE_ACCESS)) ++#define ME_XDATA_BASE ((volatile u32*)(0x0054 + IFX_MEI_SPACE_ACCESS)) ++#define ME_XMEM_BAR_BASE ((volatile u32*)(0x0058 + IFX_MEI_SPACE_ACCESS)) ++#define ME_XMEM_BAR0 ((volatile u32*)(0x0058 + IFX_MEI_SPACE_ACCESS)) ++#define ME_XMEM_BAR1 ((volatile u32*)(0x005C + IFX_MEI_SPACE_ACCESS)) ++#define ME_XMEM_BAR2 ((volatile u32*)(0x0060 + IFX_MEI_SPACE_ACCESS)) ++#define ME_XMEM_BAR3 ((volatile u32*)(0x0064 + IFX_MEI_SPACE_ACCESS)) ++#define ME_XMEM_BAR4 ((volatile u32*)(0x0068 + IFX_MEI_SPACE_ACCESS)) ++#define ME_XMEM_BAR5 ((volatile u32*)(0x006C + IFX_MEI_SPACE_ACCESS)) ++#define ME_XMEM_BAR6 ((volatile u32*)(0x0070 + IFX_MEI_SPACE_ACCESS)) ++#define ME_XMEM_BAR7 ((volatile u32*)(0x0074 + IFX_MEI_SPACE_ACCESS)) ++#define ME_XMEM_BAR8 ((volatile u32*)(0x0078 + IFX_MEI_SPACE_ACCESS)) ++#define ME_XMEM_BAR9 ((volatile u32*)(0x007C + IFX_MEI_SPACE_ACCESS)) ++#define ME_XMEM_BAR10 ((volatile u32*)(0x0080 + IFX_MEI_SPACE_ACCESS)) ++#define ME_XMEM_BAR11 ((volatile u32*)(0x0084 + IFX_MEI_SPACE_ACCESS)) ++#define ME_XMEM_BAR12 ((volatile u32*)(0x0088 + IFX_MEI_SPACE_ACCESS)) ++#define ME_XMEM_BAR13 ((volatile u32*)(0x008C + IFX_MEI_SPACE_ACCESS)) ++#define ME_XMEM_BAR14 ((volatile u32*)(0x0090 + IFX_MEI_SPACE_ACCESS)) ++#define ME_XMEM_BAR15 ((volatile u32*)(0x0094 + IFX_MEI_SPACE_ACCESS)) ++#define ME_XMEM_BAR16 ((volatile u32*)(0x0098 + IFX_MEI_SPACE_ACCESS)) ++#endif ++ ++ ++/***********************************************************************/ ++/* Module : GPIO register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_GPIO (KSEG1 | 0x1E100B00) ++ ++/***Port 0 Data Output Register (0010H)***/ ++#define IFX_GPIO_P0_OUT ((volatile u32 *)(IFX_GPIO + 0x0010)) ++/***Port 1 Data Output Register (0040H)***/ ++#define IFX_GPIO_P1_OUT ((volatile u32 *)(IFX_GPIO + 0x0040)) ++/***Port 2 Data Output Register (0070H)***/ ++#define IFX_GPIO_P2_OUT ((volatile u32 *)(IFX_GPIO + 0x0070)) ++/***Port 3 Data Output Register (00A0H)***/ ++#define IFX_GPIO_P3_OUT ((volatile u32 *)(IFX_GPIO + 0x00A0)) ++/***Port 0 Data Input Register (0014H)***/ ++#define IFX_GPIO_P0_IN ((volatile u32 *)(IFX_GPIO + 0x0014)) ++/***Port 1 Data Input Register (0044H)***/ ++#define IFX_GPIO_P1_IN ((volatile u32 *)(IFX_GPIO + 0x0044)) ++/***Port 2 Data Input Register (0074H)***/ ++#define IFX_GPIO_P2_IN ((volatile u32 *)(IFX_GPIO + 0x0074)) ++/***Port 3 Data Input Register (00A4H)***/ ++#define IFX_GPIO_P3_IN ((volatile u32 *)(IFX_GPIO + 0x00A4)) ++/***Port 0 Direction Register (0018H)***/ ++#define IFX_GPIO_P0_DIR ((volatile u32 *)(IFX_GPIO + 0x0018)) ++/***Port 1 Direction Register (0048H)***/ ++#define IFX_GPIO_P1_DIR ((volatile u32 *)(IFX_GPIO + 0x0048)) ++/***Port 2 Direction Register (0078H)***/ ++#define IFX_GPIO_P2_DIR ((volatile u32 *)(IFX_GPIO + 0x0078)) ++/***Port 3 Direction Register (0048H)***/ ++#define IFX_GPIO_P3_DIR ((volatile u32 *)(IFX_GPIO + 0x00A8)) ++/***Port 0 Alternate Function Select Register 0 (001C H) ***/ ++#define IFX_GPIO_P0_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x001C)) ++/***Port 1 Alternate Function Select Register 0 (004C H) ***/ ++#define IFX_GPIO_P1_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x004C)) ++/***Port 2 Alternate Function Select Register 0 (007C H) ***/ ++#define IFX_GPIO_P2_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x007C)) ++/***Port 3 Alternate Function Select Register 0 (00AC H) ***/ ++#define IFX_GPIO_P3_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x00AC)) ++/***Port 0 Alternate Function Select Register 1 (0020 H) ***/ ++#define IFX_GPIO_P0_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0020)) ++/***Port 1 Alternate Function Select Register 0 (0050 H) ***/ ++#define IFX_GPIO_P1_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0050)) ++/***Port 2 Alternate Function Select Register 0 (0080 H) ***/ ++#define IFX_GPIO_P2_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0080)) ++/***Port 3 Alternate Function Select Register 0 (0064 H) ***/ ++#define IFX_GPIO_P3_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0064)) ++/***Port 0 Open Drain Control Register (0024H)***/ ++#define IFX_GPIO_P0_OD ((volatile u32 *)(IFX_GPIO + 0x0024)) ++/***Port 1 Open Drain Control Register (0054H)***/ ++#define IFX_GPIO_P1_OD ((volatile u32 *)(IFX_GPIO + 0x0054)) ++/***Port 2 Open Drain Control Register (0084H)***/ ++#define IFX_GPIO_P2_OD ((volatile u32 *)(IFX_GPIO + 0x0084)) ++/***Port 3 Open Drain Control Register (0034H)***/ ++#define IFX_GPIO_P3_OD ((volatile u32 *)(IFX_GPIO + 0x0034)) ++/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/ ++#define IFX_GPIO_P0_STOFF ((volatile u32 *)(IFX_GPIO + 0x0028)) ++/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/ ++#define IFX_GPIO_P1_STOFF ((volatile u32 *)(IFX_GPIO + 0x0058)) ++/***Port 2 Input Schmitt-Trigger Off Register (0088 H) ***/ ++#define IFX_GPIO_P2_STOFF ((volatile u32 *)(IFX_GPIO + 0x0088)) ++/***Port 3 Input Schmitt-Trigger Off Register (0094 H) ***/ ++ ++/***Port 0 Pull Up/Pull Down Select Register (002C H)***/ ++#define IFX_GPIO_P0_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x002C)) ++/***Port 1 Pull Up/Pull Down Select Register (005C H)***/ ++#define IFX_GPIO_P1_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x005C)) ++/***Port 2 Pull Up/Pull Down Select Register (008C H)***/ ++#define IFX_GPIO_P2_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x008C)) ++/***Port 3 Pull Up/Pull Down Select Register (0038 H)***/ ++#define IFX_GPIO_P3_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x0038)) ++/***Port 0 Pull Up Device Enable Register (0030 H)***/ ++#define IFX_GPIO_P0_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0030)) ++/***Port 1 Pull Up Device Enable Register (0060 H)***/ ++#define IFX_GPIO_P1_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0060)) ++/***Port 2 Pull Up Device Enable Register (0090 H)***/ ++#define IFX_GPIO_P2_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0090)) ++/***Port 3 Pull Up Device Enable Register (003c H)***/ ++#define IFX_GPIO_P3_PUDEN ((volatile u32 *)(IFX_GPIO + 0x003C)) ++ ++ ++ ++/***********************************************************************/ ++/* Module : CGU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_CGU (KSEG1 | 0x1F103000) ++ ++/***CGU Clock PLL0 ***/ ++#define IFX_CGU_PLL0_CFG ((volatile u32*)(IFX_CGU + 0x0004)) ++/***CGU Clock PLL1 ***/ ++#define IFX_CGU_PLL1_CFG ((volatile u32*)(IFX_CGU + 0x0008)) ++/***CGU Clock PLL2 ***/ ++#define IFX_CGU_PLL2_CFG ((volatile u32*)(IFX_CGU + 0x0060)) ++/***CGU Clock SYS Mux Register***/ ++#define IFX_CGU_SYS ((volatile u32*)(IFX_CGU + 0x000C)) ++/***CGU CGU Clock Frequency Select Register***/ ++#define IFX_CGU_CLKFSR ((volatile u32*)(IFX_CGU + 0x0010)) ++/**Update CGU Register***/ ++#define IFX_CGU_UPDATE ((volatile u32*)(IFX_CGU + 0x0020)) ++/***CGU Interface Clock Control Register***/ ++#define IFX_CGU_IF_CLK ((volatile u32*)(IFX_CGU + 0x0024)) ++/***CGU PCI Clock Control Register**/ ++#define IFX_CGU_PCI_CR ((volatile u32*)(IFX_CGU + 0x0038)) ++ ++#define IFX_PCI_CLK_SHIFT 20 ++#define IFX_PCI_CLK_MASK (0x1F << IFX_PCI_CLK_SHIFT) ++#define IFX_PCI_33MHZ (0xe << IFX_PCI_CLK_SHIFT) ++#define IFX_PCI_60MHZ (0x7 << IFX_PCI_CLK_SHIFT) ++#define IFX_PCI_INTERNAL_CLK_SRC 0x00010000 /* Internal means output */ ++ ++#define IFX_PCI_CLK_FROM_CGU 0x80000000 ++#define IFX_PCI_CLK_RESET_FROM_CGU 0x40000000 ++#define IFX_PCI_DELAY_SHIFT 21 ++#define IFX_PCI_DELAY_MASK (0x7 << IFX_PCI_DELAY_SHIFT) ++ ++ ++/***********************************************************************/ ++/* Module : MCD register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_MCD (KSEG1 | 0x1F106000) ++ ++/***Manufacturer Identification Register***/ ++#define IFX_MCD_MANID ((volatile u32*)(IFX_MCD + 0x0024)) ++#define IFX_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5) ++ ++/***Chip Identification Register***/ ++#define IFX_MCD_CHIPID ((volatile u32*)(IFX_MCD + 0x0028)) ++#define IFX_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) ++#define IFX_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) ++#define IFX_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1)) ++#define IFX_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12) ++#define IFX_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1)) ++#define IFX_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1) ++ ++#define IFX_CHIPID_STANDARD 0x00EB ++#define IFX_CHIPID_YANGTSE 0x00ED ++ ++/***Redesign Tracing Identification Register***/ ++#define IFX_MCD_RTID ((volatile u32*)(IFX_MCD + 0x002C)) ++#define IFX_MCD_RTID_LC (1 << 15) ++#define IFX_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0) ++ ++ ++ ++/***********************************************************************/ ++/* Module : EBU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_EBU (KSEG1 | 0x16000000) ++ ++/***EBU Clock Control Register***/ ++#define IFX_EBU_CLC ((volatile u32*)(IFX_EBU + 0x0000)) ++#define IFX_EBU_CLC_DISS (1 << 1) ++#define IFX_EBU_CLC_DISR (1 << 0) ++ ++#define IFX_EBU_ID ((volatile u32*)(IFX_EBU + 0x0008)) ++ ++/***EBU Global Control Register***/ ++#define IFX_EBU_CON ((volatile u32*)(IFX_EBU + 0x0010)) ++#define IFX_EBU_CON_DTACS(value) (((( 1 << 3) - 1) & (value)) << 20) ++#define IFX_EBU_CON_DTARW(value) (((( 1 << 3) - 1) & (value)) << 16) ++#define IFX_EBU_CON_TOUTC(value) (((( 1 << 8) - 1) & (value)) << 8) ++#define IFX_EBU_CON_ARBMODE(value) (((( 1 << 2) - 1) & (value)) << 6) ++#define IFX_EBU_CON_ARBSYNC (1 << 5) ++ ++/***EBU Address Select Register 0***/ ++#define IFX_EBU_ADDSEL0 ((volatile u32*)(IFX_EBU + 0x0020)) ++#define IFX_EBU_ADDSEL0_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) ++#define IFX_EBU_ADDSEL0_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_EBU_ADDSEL0_MIRRORE (1 << 1) ++#define IFX_EBU_ADDSEL0_REGEN (1 << 0) ++ ++/***EBU Address Select Register 1***/ ++#define IFX_EBU_ADDSEL1 ((volatile u32*)(IFX_EBU + 0x0024)) ++#define IFX_EBU_ADDSEL1_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) ++#define IFX_EBU_ADDSEL1_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_EBU_ADDSEL1_MIRRORE (1 << 1) ++#define IFX_EBU_ADDSEL1_REGEN (1 << 0) ++ ++/***EBU Address Select Register 2***/ ++#define IFX_EBU_ADDSEL2 ((volatile u32*)(IFX_EBU + 0x0028)) ++#define IFX_EBU_ADDSEL2_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) ++#define IFX_EBU_ADDSEL2_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_EBU_ADDSEL2_MIRRORE (1 << 1) ++#define IFX_EBU_ADDSEL2_REGEN (1 << 0) ++ ++/***EBU Address Select Register 3***/ ++#define IFX_EBU_ADDSEL3 ((volatile u32*)(IFX_EBU + 0x002C)) ++#define IFX_EBU_ADDSEL3_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) ++#define IFX_EBU_ADDSEL3_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_EBU_ADDSEL3_MIRRORE (1 << 1) ++#define IFX_EBU_ADDSEL3_REGEN (1 << 0) ++ ++ ++/***EBU Bus Configuration Register 0***/ ++#define IFX_EBU_BUSCON0 ((volatile u32*)(IFX_EBU+ 0x0060)) ++ ++#define IFX_EBU_BUSCON0_CMULT 0x00000003 ++#define IFX_EBU_BUSCON0_CMULT_S 0 ++enum { ++ IFX_EBU_BUSCON0_CMULT1 = 0, ++ IFX_EBU_BUSCON0_CMULT4, ++ IFX_EBU_BUSCON0_CMULT8, ++ IFX_EBU_BUSCON0_CMULT16, /* Default after reset */ ++}; ++ ++#define IFX_EBU_BUSCON0_RECOVC 0x00000000c ++#define IFX_EBU_BUSCON0_RECOVC_S 2 ++enum { ++ IFX_EBU_BUSCON0_RECOVC0 = 0, ++ IFX_EBU_BUSCON0_RECOVC1, ++ IFX_EBU_BUSCON0_RECOVC2, ++ IFX_EBU_BUSCON0_RECOVC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON0_HOLDC 0x00000030 ++#define IFX_EBU_BUSCON0_HOLDC_S 4 ++enum { ++ IFX_EBU_BUSCON0_HOLDC0 = 0, ++ IFX_EBU_BUSCON0_HOLDC1, ++ IFX_EBU_BUSCON0_HOLDC2, ++ IFX_EBU_BUSCON0_HOLDC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON0_WAITRDC 0x000000c0 ++#define IFX_EBU_BUSCON0_WAITRDC_S 6 ++enum { ++ IFX_EBU_BUSCON0_WAITRDC0 = 0, ++ IFX_EBU_BUSCON0_WAITRDC1, ++ IFX_EBU_BUSCON0_WAITRDC2, ++ IFX_EBU_BUSCON0_WAITRDC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON0_WAITWRC 0x00000700 ++#define IFX_EBU_BUSCON0_WAITWRC_S 8 ++enum { ++ IFX_EBU_BUSCON0_WAITWRC0 = 0, ++ IFX_EBU_BUSCON0_WAITWRC1, ++ IFX_EBU_BUSCON0_WAITWRC2, ++ IFX_EBU_BUSCON0_WAITWRC3, ++ IFX_EBU_BUSCON0_WAITWRC4, ++ IFX_EBU_BUSCON0_WAITWRC5, ++ IFX_EBU_BUSCON0_WAITWRC6, ++ IFX_EBU_BUSCON0_WAITWRC7, /* Default */ ++}; ++ ++#define IFX_EBU_BUSCON0_BCGEN 0x00003000 ++#define IFX_EBU_BUSCON0_BCGEN_S 12 ++enum { ++ IFX_EBU_BUSCON0_BCGEN_CS = 0, ++ IFX_EBU_BUSCON0_BCGEN_INTEL, /* Default */ ++ IFX_EBU_BUSCON0_BCGEN_MOTOROLA, ++ IFX_EBU_BUSCON0_BCGEN_RES, ++}; ++ ++#define IFX_EBU_BUSCON0_ALEC 0x0000c000 ++#define IFX_EBU_BUSCON0_ALEC_S 14 ++enum { ++ IFX_EBU_BUSCON0_ALEC0 = 0, ++ IFX_EBU_BUSCON0_ALEC1, ++ IFX_EBU_BUSCON0_ALEC2, ++ IFX_EBU_BUSCON0_ALEC3, /* Default */ ++}; ++ ++#define IFX_EBU_BUSCON0_XDM 0x00030000 ++#define IFX_EBU_BUSCON0_XDM_S 16 ++enum { ++ IFX_EBU_BUSCON0_XDM8 = 0, ++ IFX_EBU_BUSCON0_XDM16, /* Default */ ++}; ++ ++#define IFX_EBU_BUSCON0_VN_EN 0x00040000 ++ ++#define IFX_EBU_BUSCON0_WAITINV_HI 0x00080000 /* low by default */ ++ ++#define IFX_EBU_BUSCON0_WAIT 0x00300000 ++#define IFX_EBU_BUSCON0_WAIT_S 20 ++enum { ++ IFX_EBU_BUSCON0_WAIT_DISABLE = 0, ++ IFX_EBU_BUSCON0_WAIT_ASYNC, ++ IFX_EBU_BUSCON0_WAIT_SYNC, ++}; ++#define IFX_EBU_BUSCON0_SETUP_EN 0x00400000 /* Disable by default */ ++#define IFX_EBU_BUSCON1_SETUP_EN 0x00400000 /* Disable by default */ ++ ++#define IFX_EBU_BUSCON0_AGEN 0x07000000 ++#define IFX_EBU_BUSCON0_AGEN_S 24 ++enum { ++ IFX_EBU_BUSCON0_AGEN_DEMUX = 0, /* Default */ ++ IFX_EBU_BUSCON0_AGEN_RES, ++ IFX_EBU_BUSCON0_AGEN_MUX, ++}; ++ ++#define IFX_EBU_BUSCON0_PG_EN 0x20000000 ++#define IFX_EBU_BUSCON0_ADSWP 0x40000000 /* Disable by default */ ++#define IFX_EBU_BUSCON0_WRDIS 0x80000000 /* Disable by default */ ++ ++/***EBU Bus Configuration Register 1***/ ++#define IFX_EBU_BUSCON1 ((volatile u32*)(IFX_EBU + 0x0064)) ++#define IFX_EBU_BUSCON1_CMULT 0x00000003 ++#define IFX_EBU_BUSCON1_CMULT_S 0 ++enum { ++ IFX_EBU_BUSCON1_CMULT1 = 0, ++ IFX_EBU_BUSCON1_CMULT4, ++ IFX_EBU_BUSCON1_CMULT8, ++ IFX_EBU_BUSCON1_CMULT16, /* Default after reset */ ++ }; ++ ++#define IFX_EBU_BUSCON1_RECOVC 0x00000000c ++#define IFX_EBU_BUSCON1_RECOVC_S 2 ++enum { ++ IFX_EBU_BUSCON1_RECOVC0 = 0, ++ IFX_EBU_BUSCON1_RECOVC1, ++ IFX_EBU_BUSCON1_RECOVC2, ++ IFX_EBU_BUSCON1_RECOVC3, /* Default */ ++ }; ++#define IFX_EBU_BUSCON1_HOLDC 0x00000030 ++#define IFX_EBU_BUSCON1_HOLDC_S 4 ++enum { ++ IFX_EBU_BUSCON1_HOLDC0 = 0, ++ IFX_EBU_BUSCON1_HOLDC1, ++ IFX_EBU_BUSCON1_HOLDC2, ++ IFX_EBU_BUSCON1_HOLDC3, /* Default */ ++ }; ++#define IFX_EBU_BUSCON1_WAITRDC 0x000000c0 ++#define IFX_EBU_BUSCON1_WAITRDC_S 6 ++enum { ++ IFX_EBU_BUSCON1_WAITRDC0 = 0, ++ IFX_EBU_BUSCON1_WAITRDC1, ++ IFX_EBU_BUSCON1_WAITRDC2, ++ IFX_EBU_BUSCON1_WAITRDC3, /* Default */ ++ }; ++#define IFX_EBU_BUSCON1_WAITWRC 0x00000700 ++#define IFX_EBU_BUSCON1_WAITWRC_S 8 ++enum { ++ IFX_EBU_BUSCON1_WAITWRC0 = 0, ++ IFX_EBU_BUSCON1_WAITWRC1, ++ IFX_EBU_BUSCON1_WAITWRC2, ++ IFX_EBU_BUSCON1_WAITWRC3, ++ IFX_EBU_BUSCON1_WAITWRC4, ++ IFX_EBU_BUSCON1_WAITWRC5, ++ IFX_EBU_BUSCON1_WAITWRC6, ++ IFX_EBU_BUSCON1_WAITWRC7, /* Default */ ++ }; ++#define IFX_EBU_BUSCON1_BCGEN 0x00003000 ++#define IFX_EBU_BUSCON1_BCGEN_S 12 ++enum { ++ IFX_EBU_BUSCON1_BCGEN_CS = 0, ++ IFX_EBU_BUSCON1_BCGEN_INTEL, /* Default */ ++ IFX_EBU_BUSCON1_BCGEN_MOTOROLA, ++ IFX_EBU_BUSCON1_BCGEN_RES, ++ }; ++#define IFX_EBU_BUSCON1_ALEC 0x0000c000 ++#define IFX_EBU_BUSCON1_ALEC_S 14 ++enum { ++ IFX_EBU_BUSCON1_ALEC0 = 0, ++ IFX_EBU_BUSCON1_ALEC1, ++ IFX_EBU_BUSCON1_ALEC2, ++ IFX_EBU_BUSCON1_ALEC3, /* Default */ ++ }; ++ ++#define IFX_EBU_BUSCON1_SETUP (1 << 22) ++ ++#define IFX_EBU_BUSCON1_WRDIS (1 << 31) ++//#define IFX_EBU_BUSCON1_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) ++//#define IFX_EBU_BUSCON1_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) ++//#define IFX_EBU_BUSCON1_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) ++//#define IFX_EBU_BUSCON1_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) ++//#define IFX_EBU_BUSCON1_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) ++//#define IFX_EBU_BUSCON1_WAITINV (1 << 19) ++//#define IFX_EBU_BUSCON1_SETUP (1 << 18) ++//#define IFX_EBU_BUSCON1_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) ++//#define IFX_EBU_BUSCON1_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) ++//#define IFX_EBU_BUSCON1_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) ++//#define IFX_EBU_BUSCON1_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) ++//#define IFX_EBU_BUSCON1_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) ++//#define IFX_EBU_BUSCON1_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) ++ ++/***EBU Bus Configuration Register 2***/ ++#define IFX_EBU_BUSCON2 ((volatile u32*)(IFX_EBU + 0x0068)) ++#define IFX_EBU_BUSCON2_WRDIS (1 << 31) ++#define IFX_EBU_BUSCON2_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) ++#define IFX_EBU_BUSCON2_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) ++#define IFX_EBU_BUSCON2_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) ++#define IFX_EBU_BUSCON2_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) ++#define IFX_EBU_BUSCON2_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) ++#define IFX_EBU_BUSCON2_WAITINV (1 << 19) ++#define IFX_EBU_BUSCON2_SETUP (1 << 18) ++#define IFX_EBU_BUSCON2_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) ++#define IFX_EBU_BUSCON2_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) ++#define IFX_EBU_BUSCON2_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) ++#define IFX_EBU_BUSCON2_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) ++#define IFX_EBU_BUSCON2_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) ++#define IFX_EBU_BUSCON2_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) ++ ++/***EBU Bus Configuration Register 2***/ ++#define IFX_EBU_BUSCON3 ((volatile u32*)(IFX_EBU + 0x006C)) ++#define IFX_EBU_BUSCON3_WRDIS (1 << 31) ++#define IFX_EBU_BUSCON3_ADSWP(value) (1 << 30) ++#define IFX_EBU_BUSCON3_PG_EN(value) (1 << 29) ++#define IFX_EBU_BUSCON3_AGEN(value) (((( 1 << 3) - 1) & (value)) << 24) ++#define IFX_EBU_BUSCON3_SETUP (1 << 22) ++#define IFX_EBU_BUSCON3_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) ++#define IFX_EBU_BUSCON3_WAITINV (1 << 19) ++#define IFX_EBU_BUSCON3_VN_EN (1 << 18) ++#define IFX_EBU_BUSCON3_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) ++#define IFX_EBU_BUSCON3_ALEC(value) (((( 1 << 2) - 1) & (value)) << 14) ++#define IFX_EBU_BUSCON3_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 12) ++#define IFX_EBU_BUSCON3_WAITWDC(value) (((( 1 << 4) - 1) & (value)) << 8) ++#define IFX_EBU_BUSCON3_WAITRRC(value) (((( 1 << 2) - 1) & (value)) << 6) ++#define IFX_EBU_BUSCON3_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) ++#define IFX_EBU_BUSCON3_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) ++#define IFX_EBU_BUSCON3_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) ++ ++/* PC-Card Configuration */ ++#define IFX_EBU_PCC_CON ((volatile u32*)(IFX_EBU+ 0x0090)) ++#define IFX_EBU_PCC_CON_PCCARD_ON 0x00000001 ++#define IFX_EBU_PCC_CON_IREQ_RISING_EDGE 0x00000002 ++#define IFX_EBU_PCC_CON_IREQ_FALLING_EDGE 0x00000004 ++#define IFX_EBU_PCC_CON_IREQ_BOTH_EDGE 0x00000006 ++#define IFX_EBU_PCC_CON_IREQ_DIS 0x00000008 ++#define IFX_EBU_PCC_CON_IREQ_HIGH_LEVEL_DETECT 0x0000000A ++#define IFX_EBU_PCC_CON_IREQ_LOW_LEVEL_DETECT 0x0000000C ++ ++#define IFX_EBU_PCC_STAT ((volatile u32*)(IFX_EBU+ 0x0094)) ++#define IFX_EBU_PCC_ISTAT ((volatile u32*)(IFX_EBU+ 0x00A0)) ++#define IFX_EBU_PCC_IEN ((volatile u32*)(IFX_EBU+ 0x00A4)) ++#define IFX_EBU_PCC_IEN_PCI_EN 0x00000010 ++ ++#define IFX_EBU_PCC_INT_OUT ((volatile u32*)(IFX_EBU+ 0x00A8)) ++#define IFX_EBU_PCC_IRS ((volatile u32*)(IFX_EBU+ 0x00AC)) ++ ++#define IFX_EBU_NAND_CON (volatile u32*)(IFX_EBU + 0xB0) ++#define IFX_EBU_NAND_WAIT (volatile u32*)(IFX_EBU + 0xB4) ++#define IFX_EBU_NAND_ECC0 (volatile u32*)(IFX_EBU + 0xB8) ++#define IFX_EBU_NAND_ECC_AC (volatile u32*)(IFX_EBU + 0xBC) ++#define IFX_EBU_NAND_CON_NANDM (1<<0) ++#define IFX_EBU_NAND_CON_NANDM_S 0 ++enum { ++ IFX_EBU_NAND_CON_NANDM_DISABLE = 0,/* Default after reset */ ++ IFX_EBU_NAND_CON_NANDM_ENABLE, ++ }; ++ ++#define IFX_EBU_NAND_CON_CSMUX_E (1<<1) ++#define IFX_EBU_NAND_CON_CSMUX_E_S 1 ++enum { ++ IFX_EBU_NAND_CON_CSMUX_E_DISABLE = 0,/* Default after reset */ ++ IFX_EBU_NAND_CON_CSMUX_E_ENALBE, ++ }; ++ ++#define IFX_EBU_NAND_CON_CS_P (1<<4) ++#define IFX_EBU_NAND_CON_CS_P_S 4 ++enum { ++ IFX_EBU_NAND_CON_CS_P_HIGH = 0, ++ IFX_EBU_NAND_CON_CS_P_LOW, /* Default after reset */ ++ }; ++ ++#define IFX_EBU_NAND_CON_SE_P (1<<5) ++#define IFX_EBU_NAND_CON_SE_P_S 5 ++enum { ++ IFX_EBU_NAND_CON_SE_P_HIGH = 0, ++ IFX_EBU_NAND_CON_SE_P_LOW, /* Default after reset */ ++ }; ++#define IFX_EBU_NAND_CON_WP_P (1<<6) ++#define IFX_EBU_NAND_CON_WP_P_S 6 ++enum { ++ IFX_EBU_NAND_CON_WP_P_HIGH = 0, ++ IFX_EBU_NAND_CON_WP_P_LOW, /* Default after reset */ ++ }; ++ ++#define IFX_EBU_NAND_CON_PRE_P (1<<7) ++#define IFX_EBU_NAND_CON_PRE_P_S 7 ++enum { ++ IFX_EBU_NAND_CON_PRE_P_HIGH = 0, ++ IFX_EBU_NAND_CON_PRE_P_LOW, /* Default after reset */ ++ }; ++ ++#define IFX_EBU_NAND_CON_IN_CS (3<<8) ++#define IFX_EBU_NAND_CON_IN_CS_S 8 ++enum { ++ IFX_EBU_NAND_CON_IN_CS0 = 0, /* Default after reset */ ++ IFX_EBU_NAND_CON_IN_CS1, ++ }; ++ ++#define IFX_EBU_NAND_CON_OUT_CS (3<<10) ++#define IFX_EBU_NAND_CON_OUT_CS_S 10 ++enum { ++ IFX_EBU_NAND_CON_OUT_CS0 = 0, /* Default after reset */ ++ IFX_EBU_NAND_CON_OUT_CS1, ++ }; ++ ++#define IFX_EBU_NAND_WAIT_RD (0x1) ++#define IFX_EBU_NAND_WAIT_BY_E (1<<1) ++#define IFX_EBU_NAND_WAIT_RD_E (1<<2) ++#define IFX_EBU_NAND_WAIT_WR_C (1<<3) ++ ++#define IFX_EBU_NAND_ECC0 (volatile u32*)(IFX_EBU + 0xB8) ++#define IFX_EBU_NAND_ECC_AC (volatile u32*)(IFX_EBU + 0xBC) ++ ++/***********************************************************************/ ++/* Module : HSNAND register address and bits */ ++/***********************************************************************/ ++#define IFX_NAND (KSEG1 | 0x16000100) ++ ++#define IFX_NDAC_CTL_1 (volatile u32 *)(IFX_NAND + 0x0010) ++#define IFX_NDAC_CTL_2 (volatile u32 *)(IFX_NAND + 0x0014) ++#define EBU_INT_MSK_CTL (volatile u32 *)(IFX_NAND + 0x0024) ++#define EBU_INT_STAT (volatile u32 *)(IFX_NAND + 0x0028) ++#define IFX_HSMD_CTL (volatile u32 *)(IFX_NAND + 0x0030) ++#define IFX_ND_PARA0 (volatile u32 *)(IFX_NAND + 0x003C) ++#define IFX_ND_ODD_ECC (volatile u32 *)(IFX_NAND + 0x0040) ++#define IFX_ND_ODD_ECC1 (volatile u32 *)(IFX_NAND + 0x0044) ++#define IFX_ND_EVEN_ECC (volatile u32 *)(IFX_NAND + 0x0048) ++#define IFX_ND_EVEN_ECC1 (volatile u32 *)(IFX_NAND + 0x004C) ++ ++#define IFX_NAND_TYPE_S 18 ++#define IFX_NAND_TYPE 0x00040000 ++#define IFX_NAND_PCOUNT_S 10 ++#define IFX_NAND_PCOUNT 0x0003FC00 ++#define IFX_NAND_PLANE_MODE_S 9 ++#define IFX_NAND_PLANE_MODE 0x00000200 ++#define IFX_NAND_ECC_MODE_S 8 ++#define IFX_NAND_ECC_MODE 0x00000100 ++#define IFX_NAND_ECC_LOC_S 7 ++#define IFX_NAND_ECC_LOC 0x00000080 ++#define IFX_NAND_ECC_STRENGTH_S 6 ++#define IFX_NAND_ECC_STRENGTH 0x00000040 ++#define IFX_NAND_PIB_S 4 ++#define IFX_NAND_PIB 0x00000030 ++#define IFX_NAND_PAGE_SIZE_S 0 ++#define IFX_NAND_PAGE_SIZE 0x0000000F ++ ++/***********************************************************************/ ++/* Module : SDRAM register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_SDRAM (KSEG1 | 0x1F800000) ++ ++/***MC Access Error Cause Register***/ ++#define IFX_SDRAM_MC_ERRCAUSE ((volatile u32*)(IFX_SDRAM + 0x0100)) ++#define IFX_SDRAM_MC_ERRCAUSE_ERR (1 << 31) ++#define IFX_SDRAM_MC_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16) ++#define IFX_SDRAM_MC_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_ERRCAUSE_Res(value) (((( 1 << NaN) - 1) & (value)) << NaN) ++ ++/***MC Access Error Address Register***/ ++#define IFX_SDRAM_MC_ERRADDR ((volatile u32*)(IFX_SDRAM + 0x0108)) ++ ++/***MC I/O General Purpose Register***/ ++#define IFX_SDRAM_MC_IOGP ((volatile u32*)(IFX_SDRAM + 0x0800)) ++#define IFX_SDRAM_MC_IOGP_GPR6(value) (((( 1 << 4) - 1) & (value)) << 28) ++#define IFX_SDRAM_MC_IOGP_GPR5(value) (((( 1 << 4) - 1) & (value)) << 24) ++#define IFX_SDRAM_MC_IOGP_GPR4(value) (((( 1 << 4) - 1) & (value)) << 20) ++#define IFX_SDRAM_MC_IOGP_GPR3(value) (((( 1 << 4) - 1) & (value)) << 16) ++#define IFX_SDRAM_MC_IOGP_GPR2(value) (((( 1 << 4) - 1) & (value)) << 12) ++#define IFX_SDRAM_MC_IOGP_CPS (1 << 11) ++#define IFX_SDRAM_MC_IOGP_CLKDELAY(value) (((( 1 << 3) - 1) & (value)) << 8) ++#define IFX_SDRAM_MC_IOGP_CLKRAT(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_IOGP_RDDEL(value) (((( 1 << 4) - 1) & (value)) << 0) ++ ++/***MC Self Refresh Register***/ ++#define IFX_SDRAM_MC_SELFRFSH ((volatile u32*)(IFX_SDRAM + 0x0A00)) ++#define IFX_SDRAM_MC_SELFRFSH_PWDS (1 << 1) ++#define IFX_SDRAM_MC_SELFRFSH_PWD (1 << 0) ++#define IFX_SDRAM_MC_SELFRFSH_Res(value) (((( 1 << 30) - 1) & (value)) << 2) ++ ++/***MC Enable Register***/ ++#define IFX_SDRAM_MC_CTRLENA ((volatile u32*)(IFX_SDRAM + 0x1000)) ++#define IFX_SDRAM_MC_CTRLENA_ENA (1 << 0) ++#define IFX_SDRAM_MC_CTRLENA_Res(value) (((( 1 << 31) - 1) & (value)) << 1) ++ ++/***MC Mode Register Setup Code***/ ++#define IFX_SDRAM_MC_MRSCODE ((volatile u32*)(IFX_SDRAM + 0x1008)) ++#define IFX_SDRAM_MC_MRSCODE_UMC(value) (((( 1 << 5) - 1) & (value)) << 7) ++#define IFX_SDRAM_MC_MRSCODE_CL(value) (((( 1 << 3) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_MRSCODE_WT (1 << 3) ++#define IFX_SDRAM_MC_MRSCODE_BL(value) (((( 1 << 3) - 1) & (value)) << 0) ++ ++/***MC Configuration Data-word Width Register***/ ++#define IFX_SDRAM_MC_CFGDW ((volatile u32*)(IFX_SDRAM + 0x1010)) ++#define IFX_SDRAM_MC_CFGDW_DW(value) (((( 1 << 4) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_CFGDW_Res(value) (((( 1 << 28) - 1) & (value)) << 4) ++ ++/***MC Configuration Physical Bank 0 Register***/ ++#define IFX_SDRAM_MC_CFGPB0 ((volatile u32*)(IFX_SDRAM + 0x1018)) ++#define IFX_SDRAM_MC_CFGPB0_MCSEN0(value) (((( 1 << 4) - 1) & (value)) << 12) ++#define IFX_SDRAM_MC_CFGPB0_BANKN0(value) (((( 1 << 4) - 1) & (value)) << 8) ++#define IFX_SDRAM_MC_CFGPB0_ROWW0(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_CFGPB0_COLW0(value) (((( 1 << 4) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_CFGPB0_Res(value) (((( 1 << 16) - 1) & (value)) << 16) ++ ++/***MC Latency Register***/ ++#define IFX_SDRAM_MC_LATENCY ((volatile u32*)(IFX_SDRAM + 0x1038)) ++#define IFX_SDRAM_MC_LATENCY_TRP(value) (((( 1 << 4) - 1) & (value)) << 16) ++#define IFX_SDRAM_MC_LATENCY_TRAS(value) (((( 1 << 4) - 1) & (value)) << 12) ++#define IFX_SDRAM_MC_LATENCY_TRCD(value) (((( 1 << 4) - 1) & (value)) << 8) ++#define IFX_SDRAM_MC_LATENCY_TDPL(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_LATENCY_TDAL(value) (((( 1 << 4) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_LATENCY_Res(value) (((( 1 << 12) - 1) & (value)) << 20) ++ ++/***MC Refresh Cycle Time Register***/ ++#define IFX_SDRAM_MC_TREFRESH ((volatile u32*)(IFX_SDRAM + 0x1040)) ++#define IFX_SDRAM_MC_TREFRESH_TREF(value) (((( 1 << 13) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_TREFRESH_Res(value) (((( 1 << 19) - 1) & (value)) << 13) ++ ++/***MC Status Register***/ ++#define IFX_SDRAM_MC_STAT ((volatile u32*)(IFX_SDRAM + 0x0070)) ++ ++/***MC DDR Control Register 00***/ ++#define IFX_DDR_MC_DC00 ((volatile u32*)(IFX_SDRAM + 0x1000)) ++/***MC DDR Control Register 03***/ ++#define IFX_DDR_MC_DC03 ((volatile u32*)(IFX_SDRAM + 0x1030)) ++/***MC DDR Control Register 17***/ ++#define IFX_DDR_MC_DC17 ((volatile u32*)(IFX_SDRAM + 0x1110)) ++ ++/***********************************************************************/ ++/* Module : ASC1 register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_ASC1 (KSEG1 | 0x1E100C00) ++ ++/***ASC Clock Control Register***/ ++#define IFX_ASC1_CLC ((volatile u32*)(IFX_ASC1 + 0x0000)) ++#define IFX_ASC1_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) ++#define IFX_ASC1_CLC_DISS (1 << 1) ++#define IFX_ASC1_CLC_DISR (1 << 0) ++ ++/***ASC Port Input Select Register***/ ++#define IFX_ASC1_PISEL ((volatile u32*)(IFX_ASC1 + 0x0004)) ++#define IFX_ASC1_PISEL ((volatile u32*)(IFX_ASC1 + 0x0004)) ++#define IFX_ASC1_PISEL_RIS (1 << 0) ++ ++/***ASC Control Register***/ ++#define IFX_ASC1_CON ((volatile u32*)(IFX_ASC1 + 0x0010)) ++#define IFX_ASC1_CON_BEN (1 << 20) ++#define IFX_ASC1_CON_TOEN (1 << 20) ++#define IFX_ASC1_CON_ROEN (1 << 19) ++#define IFX_ASC1_CON_RUEN (1 << 18) ++#define IFX_ASC1_CON_FEN (1 << 17) ++#define IFX_ASC1_CON_PAL (1 << 16) ++#define IFX_ASC1_CON_R (1 << 15) ++#define IFX_ASC1_CON_ACO (1 << 14) ++#define IFX_ASC1_CON_LB (1 << 13) ++#define IFX_ASC1_CON_ERCLK (1 << 10) ++#define IFX_ASC1_CON_FDE (1 << 9) ++#define IFX_ASC1_CON_BRS (1 << 8) ++#define IFX_ASC1_CON_STP (1 << 7) ++#define IFX_ASC1_CON_SP (1 << 6) ++#define IFX_ASC1_CON_ODD (1 << 5) ++#define IFX_ASC1_CON_PEN (1 << 4) ++#define IFX_ASC1_CON_M(value) (((( 1 << 3) - 1) & (value)) << 0) ++ ++/***ASC Staus Register***/ ++#define IFX_ASC1_STATE ((volatile u32*)(IFX_ASC1 + 0x0014)) ++/***ASC Write Hardware Modified Control Register***/ ++#define IFX_ASC1_WHBSTATE ((volatile u32*)(IFX_ASC1 + 0x0018)) ++#define IFX_ASC1_WHBSTATE_SETBE (1 << 113) ++#define IFX_ASC1_WHBSTATE_SETTOE (1 << 12) ++#define IFX_ASC1_WHBSTATE_SETROE (1 << 11) ++#define IFX_ASC1_WHBSTATE_SETRUE (1 << 10) ++#define IFX_ASC1_WHBSTATE_SETFE (1 << 19) ++#define IFX_ASC1_WHBSTATE_SETPE (1 << 18) ++#define IFX_ASC1_WHBSTATE_CLRBE (1 << 17) ++#define IFX_ASC1_WHBSTATE_CLRTOE (1 << 6) ++#define IFX_ASC1_WHBSTATE_CLRROE (1 << 5) ++#define IFX_ASC1_WHBSTATE_CLRRUE (1 << 4) ++#define IFX_ASC1_WHBSTATE_CLRFE (1 << 3) ++#define IFX_ASC1_WHBSTATE_CLRPE (1 << 2) ++#define IFX_ASC1_WHBSTATE_SETREN (1 << 1) ++#define IFX_ASC1_WHBSTATE_CLRREN (1 << 0) ++ ++/***ASC Baudrate Timer/Reload Register***/ ++#define IFX_ASC1_BG ((volatile u32*)(IFX_ASC1 + 0x0050)) ++#define IFX_ASC1_BG_BR_VALUE(value) (((( 1 << 13) - 1) & (value)) << 0) ++ ++/***ASC Fractional Divider Register***/ ++#define IFX_ASC1_FDV ((volatile u32*)(IFX_ASC1 + 0x0018)) ++#define IFX_ASC1_FDV_FD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) ++ ++/***ASC Transmit Buffer Register***/ ++#define IFX_ASC1_TBUF ((volatile u32*)(IFX_ASC1 + 0x0020)) ++#define IFX_ASC1_TBUF_TD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) ++ ++/***ASC Receive Buffer Register***/ ++#define IFX_ASC1_RBUF ((volatile u32*)(IFX_ASC1 + 0x0024)) ++#define IFX_ASC1_RBUF_RD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) ++ ++/***ASC Autobaud Control Register***/ ++#define IFX_ASC1_ABCON ((volatile u32*)(IFX_ASC1 + 0x0030)) ++#define IFX_ASC1_ABCON_RXINV (1 << 11) ++#define IFX_ASC1_ABCON_TXINV (1 << 10) ++#define IFX_ASC1_ABCON_ABEM(value) (((( 1 << 2) - 1) & (value)) << 8) ++#define IFX_ASC1_ABCON_FCDETEN (1 << 4) ++#define IFX_ASC1_ABCON_ABDETEN (1 << 3) ++#define IFX_ASC1_ABCON_ABSTEN (1 << 2) ++#define IFX_ASC1_ABCON_AUREN (1 << 1) ++#define IFX_ASC1_ABCON_ABEN (1 << 0) ++ ++/***Receive FIFO Control Register***/ ++#define IFX_ASC1_RXFCON ((volatile u32*)(IFX_ASC1 + 0x0040)) ++#define IFX_ASC1_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) ++#define IFX_ASC1_RXFCON_RXFFLU (1 << 1) ++#define IFX_ASC1_RXFCON_RXFEN (1 << 0) ++ ++/***Transmit FIFO Control Register***/ ++#define IFX_ASC1_TXFCON ((volatile u32*)(IFX_ASC1 + 0x0044)) ++#define IFX_ASC1_TXFCON_TXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) ++#define IFX_ASC1_TXFCON_TXFFLU (1 << 1) ++#define IFX_ASC1_TXFCON_TXFEN (1 << 0) ++ ++/***FIFO Status Register***/ ++#define IFX_ASC1_FSTAT ((volatile u32*)(IFX_ASC1 + 0x0048)) ++#define IFX_ASC1_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8) ++#define IFX_ASC1_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0) ++#define IFX_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) ++#define IFX_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) ++#define IFX_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) ++#define IFX_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) ++#define IFX_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) ++#define IFX_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) ++#define IFX_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) ++#define IFX_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) ++ ++ ++/***ASC Autobaud Status Register***/ ++#define IFX_ASC1_ABSTAT ((volatile u32*)(IFX_ASC1 + 0x0034)) ++#define IFX_ASC1_ABSTAT_DETWAIT (1 << 4) ++#define IFX_ASC1_ABSTAT_SCCDET (1 << 3) ++#define IFX_ASC1_ABSTAT_SCSDET (1 << 2) ++#define IFX_ASC1_ABSTAT_FCCDET (1 << 1) ++#define IFX_ASC1_ABSTAT_FCSDET (1 << 0) ++ ++/***ASC Write HW Modified Autobaud Status Register***/ ++#define IFX_ASC1_WHBABSTAT ((volatile u32*)(IFX_ASC1 + 0x003C)) ++#define IFX_ASC1_WHBABSTAT_SETDETWAIT (1 << 9) ++#define IFX_ASC1_WHBABSTAT_CLRDETWAIT (1 << 8) ++#define IFX_ASC1_WHBABSTAT_SETSCCDET (1 << 7) ++#define IFX_ASC1_WHBABSTAT_CLRSCCDET (1 << 6) ++#define IFX_ASC1_WHBABSTAT_SETSCSDET (1 << 5) ++#define IFX_ASC1_WHBABSTAT_CLRSCSDET (1 << 4) ++#define IFX_ASC1_WHBABSTAT_SETFCCDET (1 << 3) ++#define IFX_ASC1_WHBABSTAT_CLRFCCDET (1 << 2) ++#define IFX_ASC1_WHBABSTAT_SETFCSDET (1 << 1) ++#define IFX_ASC1_WHBABSTAT_CLRFCSDET (1 << 0) ++ ++/***ASC IRNCR0 **/ ++#define IFX_ASC1_IRNREN ((volatile u32*)(IFX_ASC1 + 0x00F4)) ++#define IFX_ASC1_IRNICR ((volatile u32*)(IFX_ASC1 + 0x00FC)) ++/***ASC IRNCR1 **/ ++#define IFX_ASC1_IRNCR ((volatile u32*)(IFX_ASC1 + 0x00F8)) ++#define IFX_ASC_IRNCR_TIR 0x1 ++#define IFX_ASC_IRNCR_RIR 0x2 ++#define IFX_ASC_IRNCR_EIR 0x4 ++ ++ ++ ++/***********************************************************************/ ++/* Module : DMA register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_DMA (KSEG1 | 0x1E104100) ++ ++#define IFX_DMA_BASE IFX_DMA ++#define IFX_DMA_CLC (volatile u32*)(IFX_DMA_BASE + 0x00) ++#define IFX_DMA_ID (volatile u32*)(IFX_DMA_BASE + 0x08) ++#define IFX_DMA_CTRL (volatile u32*)(IFX_DMA_BASE + 0x10) ++#define IFX_DMA_CPOLL (volatile u32*)(IFX_DMA_BASE + 0x14) ++ ++#define IFX_DMA_CS(i) (volatile u32*)(IFX_DMA_BASE + 0x18 + 0x38 * (i)) ++#define IFX_DMA_CCTRL(i) (volatile u32*)(IFX_DMA_BASE + 0x1C + 0x38 * (i)) ++#define IFX_DMA_CDBA(i) (volatile u32*)(IFX_DMA_BASE + 0x20 + 0x38 * (i)) ++#define IFX_DMA_CDLEN(i) (volatile u32*)(IFX_DMA_BASE + 0x24 + 0x38 * (i)) ++#define IFX_DMA_CIS(i) (volatile u32*)(IFX_DMA_BASE + 0x28 + 0x38 * (i)) ++#define IFX_DMA_CIE(i) (volatile u32*)(IFX_DMA_BASE + 0x2C + 0x38 * (i)) ++ ++#define IFX_DMA_CGBL (volatile u32*)(IFX_DMA_BASE + 0x30) ++ ++#define IFX_DMA_PS(i) (volatile u32*)(IFX_DMA_BASE + 0x40 + 0x30 * (i)) ++#define IFX_DMA_PCTRL(i) (volatile u32*)(IFX_DMA_BASE + 0x44 + 0x30 * (i)) ++ ++#define IFX_DMA_IRNEN (volatile u32*)(IFX_DMA_BASE + 0xf4) ++#define IFX_DMA_IRNCR (volatile u32*)(IFX_DMA_BASE + 0xf8) ++#define IFX_DMA_IRNICR (volatile u32*)(IFX_DMA_BASE + 0xfc) ++/* Global Software Reset (0) */ ++#define IFX_DMA_CTRL_RST (0x1) ++ ++/* Channel Polling Register */ ++ ++/* Enable (31) */ ++#define IFX_DMA_CPOLL_EN (0x1 << 31) ++#define IFX_DMA_CPOLL_EN_VAL(val) (((val) & 0x1) << 31) ++ ++/* Counter (15:4) */ ++#define IFX_DMA_CPOLL_CNT (0xfff << 4) ++#define IFX_DMA_CPOLL_CNT_VAL(val) (((val) & 0xfff) << 4) ++ ++/* Channel Control Register */ ++ ++/* Peripheral to Peripheral Copy (24) */ ++#define IFX_DMA_CCTRL_P2PCPY (0x1 << 24) ++#define IFX_DMA_CCTRL_P2PCPY_VAL(val) (((val) & 0x1) << 24) ++#define IFX_DMA_CCTRL_P2PCPY_GET(val) ((((val) & IFX_DMA_CCTRL_P2PCPY) >> 24) & 0x1) ++ ++/* Channel Weight for Transmit Direction (17:16) */ ++#define IFX_DMA_CCTRL_TXWGT (0x3 << 16) ++#define IFX_DMA_CCTRL_TXWGT_VAL(val) (((val) & 0x3) << 16) ++#define IFX_DMA_CCTRL_TXWGT_GET(val) ((((val) & IFX_DMA_CCTRL_TXWGT) >> 16) & 0x3) ++ ++/* Port Assignment (13:11) */ ++#define IFX_DMA_CCTRL_PRTNR (0x7 << 11) ++#define IFX_DMA_CCTRL_PRTNR_GET(val) ((((val) & IFX_DMA_CCTRL_PRTNR) >> 11) & 0x7) ++ ++/* Class (10:9) */ ++#define IFX_DMA_CCTRL_CLASS (0x3 << 9) ++#define IFX_DMA_CCTRL_CLASS_VAL(val) (((val) & 0x3) << 9) ++#define IFX_DMA_CCTRL_CLASS_GET(val) ((((val) & IFX_DMA_CCTRL_CLASS) >> 9) & 0x3) ++ ++/* Direction (8) */ ++#define IFX_DMA_CCTRL_DIR (0x1 << 8) ++/* Reset (1) */ ++#define IFX_DMA_CCTRL_RST (0x1 << 1) ++/* Channel On or Off (0) */ ++#define IFX_DMA_CCTRL_ON (0x1) ++ ++/* Channel Interrupt Status Register */ ++ ++/* SAI Read Error Interrupt (5) */ ++#define IFX_DMA_CIS_RDERR (0x1 << 5) ++/* Channel Off Interrupt (4) */ ++#define IFX_DMA_CIS_CHOFF (0x1 << 4) ++/* Descriptor Complete Interrupt (3) */ ++#define IFX_DMA_CIS_DESCPT (0x1 << 3) ++/* Descriptor Under-Run Interrupt (2) */ ++#define IFX_DMA_CIS_DUR (0x1 << 2) ++/* End of Packet Interrupt (1) */ ++#define IFX_DMA_CIS_EOP (0x1 << 1) ++ ++#define IFX_DMA_CIS_ALL (IFX_DMA_CIS_RDERR | IFX_DMA_CIS_CHOFF| \ ++ IFX_DMA_CIS_DESCPT | IFX_DMA_CIS_DUR | \ ++ IFX_DMA_CIS_EOP) ++ ++/* Channel Interrupt Enable Register */ ++ ++/* SAI Read Error Interrupt (5) */ ++#define IFX_DMA_CIE_RDERR (0x1 << 5) ++/* Channel Off Interrupt (4) */ ++#define IFX_DMA_CIE_CHOFF (0x1 << 4) ++/* Descriptor Complete Interrupt Enable (3) */ ++#define IFX_DMA_CIE_DESCPT (0x1 << 3) ++/* Descriptor Under Run Interrupt Enable (2) */ ++#define IFX_DMA_CIE_DUR (0x1 << 2) ++/* End of Packet Interrupt Enable (1) */ ++#define IFX_DMA_CIE_EOP (0x1 << 1) ++ ++#define IFX_DMA_CIE_DEFAULT (IFX_DMA_CIE_DESCPT | IFX_DMA_CIE_EOP) ++ ++/* Port Select Register */ ++ ++/* Port Selection (2:0) */ ++#define IFX_DMA_PS_PS (0x7) ++#define IFX_DMA_PS_PS_VAL(val) (((val) & 0x7) << 0) ++ ++/* Port Control Register */ ++ ++/* General Purpose Control (16) */ ++#define IFX_DMA_PCTRL_GPC (0x1 << 16) ++#define IFX_DMA_PCTRL_GPC_VAL(val) (((val) & 0x1) << 16) ++ ++/* Port Weight for Transmit Direction (14:12) */ ++#define IFX_DMA_PCTRL_TXWGT (0x7 << 12) ++#define IFX_DMA_PCTRL_TXWGT_VAL(val) (((val) & 0x7) << 12) ++/* Endianness for Transmit Direction (11:10) */ ++#define IFX_DMA_PCTRL_TXENDI (0x3 << 10) ++#define IFX_DMA_PCTRL_TXENDI_VAL(val) (((val) & 0x3) << 10) ++/* Endianness for Receive Direction (9:8) */ ++#define IFX_DMA_PCTRL_RXENDI (0x3 << 8) ++#define IFX_DMA_PCTRL_RXENDI_VAL(val) (((val) & 0x3) << 8) ++/* Packet Drop Enable (6) */ ++#define IFX_DMA_PCTRL_PDEN (0x1 << 6) ++#define IFX_DMA_PCTRL_PDEN_VAL(val) (((val) & 0x1) << 6) ++/* Burst Length for Transmit Direction (5:4) */ ++#define IFX_DMA_PCTRL_TXBL (0x3 << 4) ++#define IFX_DMA_PCTRL_TXBL_VAL(val) (((val) & 0x3) << 4) ++/* Burst Length for Receive Direction (3:2) */ ++#define IFX_DMA_PCTRL_RXBL (0x3 << 2) ++#define IFX_DMA_PCTRL_RXBL_VAL(val) (((val) & 0x3) << 2) ++ ++ ++ ++/***********************************************************************/ ++/* Module : Debug register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_Debug (KSEG1 | 0x1F106000) ++ ++/***MCD Break Bus Switch Register***/ ++#define IFX_Debug_MCD_BBS ((volatile u32*)(IFX_Debug + 0x0000)) ++#define IFX_Debug_MCD_BBS_BTP1 (1 << 19) ++#define IFX_Debug_MCD_BBS_BTP0 (1 << 18) ++#define IFX_Debug_MCD_BBS_BSP1 (1 << 17) ++#define IFX_Debug_MCD_BBS_BSP0 (1 << 16) ++#define IFX_Debug_MCD_BBS_BT5EN (1 << 15) ++#define IFX_Debug_MCD_BBS_BT4EN (1 << 14) ++#define IFX_Debug_MCD_BBS_BT5 (1 << 13) ++#define IFX_Debug_MCD_BBS_BT4 (1 << 12) ++#define IFX_Debug_MCD_BBS_BS5EN (1 << 7) ++#define IFX_Debug_MCD_BBS_BS4EN (1 << 6) ++#define IFX_Debug_MCD_BBS_BS5 (1 << 5) ++#define IFX_Debug_MCD_BBS_BS4 (1 << 4) ++ ++/***MCD Multiplexer Control Register***/ ++#define IFX_Debug_MCD_MCR ((volatile u32*)(IFX_Debug+ 0x0008)) ++#define IFX_Debug_MCD_MCR_MUX5 (1 << 4) ++#define IFX_Debug_MCD_MCR_MUX4 (1 << 3) ++#define IFX_Debug_MCD_MCR_MUX1 (1 << 0) ++ ++ ++ ++/***********************************************************************/ ++/* Module : ICU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_ICU (KSEG1 | 0x1F880200) ++ ++#define IFX_ICU_IM0_ISR ((volatile u32*)(IFX_ICU + 0x0000)) ++#define IFX_ICU_IM0_IER ((volatile u32*)(IFX_ICU + 0x0008)) ++#define IFX_ICU_IM0_IOSR ((volatile u32*)(IFX_ICU + 0x0010)) ++#define IFX_ICU_IM0_IRSR ((volatile u32*)(IFX_ICU + 0x0018)) ++#define IFX_ICU_IM0_IMR ((volatile u32*)(IFX_ICU + 0x0020)) ++ ++#define IFX_ICU_IM1_ISR ((volatile u32*)(IFX_ICU + 0x0028)) ++#define IFX_ICU_IM1_IER ((volatile u32*)(IFX_ICU + 0x0030)) ++#define IFX_ICU_IM1_IOSR ((volatile u32*)(IFX_ICU + 0x0038)) ++#define IFX_ICU_IM1_IRSR ((volatile u32*)(IFX_ICU + 0x0040)) ++#define IFX_ICU_IM1_IMR ((volatile u32*)(IFX_ICU + 0x0048)) ++ ++#define IFX_ICU_IM2_ISR ((volatile u32*)(IFX_ICU + 0x0050)) ++#define IFX_ICU_IM2_IER ((volatile u32*)(IFX_ICU + 0x0058)) ++#define IFX_ICU_IM2_IOSR ((volatile u32*)(IFX_ICU + 0x0060)) ++#define IFX_ICU_IM2_IRSR ((volatile u32*)(IFX_ICU + 0x0068)) ++#define IFX_ICU_IM2_IMR ((volatile u32*)(IFX_ICU + 0x0070)) ++ ++#define IFX_ICU_IM3_ISR ((volatile u32*)(IFX_ICU + 0x0078)) ++#define IFX_ICU_IM3_IER ((volatile u32*)(IFX_ICU + 0x0080)) ++#define IFX_ICU_IM3_IOSR ((volatile u32*)(IFX_ICU + 0x0088)) ++#define IFX_ICU_IM3_IRSR ((volatile u32*)(IFX_ICU + 0x0090)) ++#define IFX_ICU_IM3_IMR ((volatile u32*)(IFX_ICU + 0x0098)) ++ ++#define IFX_ICU_IM4_ISR ((volatile u32*)(IFX_ICU + 0x00A0)) ++#define IFX_ICU_IM4_IER ((volatile u32*)(IFX_ICU + 0x00A8)) ++#define IFX_ICU_IM4_IOSR ((volatile u32*)(IFX_ICU + 0x00B0)) ++#define IFX_ICU_IM4_IRSR ((volatile u32*)(IFX_ICU + 0x00B8)) ++#define IFX_ICU_IM4_IMR ((volatile u32*)(IFX_ICU + 0x00C0)) ++ ++/***Interrupt Vector Value Register***/ ++#define IFX_ICU_IM_VEC_5 ((volatile u32*)(IFX_ICU + 0x00C8)) ++#define IFX_ICU_IM_VEC ((volatile u32*)(IFX_ICU + 0x00D0)) ++ ++/***********************************************************************/ ++ ++#define IFX_ICU_VPE1 (KSEG1 | 0x1F880300) ++#define IFX_ICU1 IFX_ICU_VPE1 ++ ++#define IFX_ICU_VPE1_IM0_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0000)) ++#define IFX_ICU_VPE1_IM0_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0008)) ++#define IFX_ICU_VPE1_IM0_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0010)) ++#define IFX_ICU_VPE1_IM0_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0018)) ++#define IFX_ICU_VPE1_IM0_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0020)) ++ ++#define IFX_ICU_VPE1_IM1_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0028)) ++#define IFX_ICU_VPE1_IM1_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0030)) ++#define IFX_ICU_VPE1_IM1_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0038)) ++#define IFX_ICU_VPE1_IM1_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0040)) ++#define IFX_ICU_VPE1_IM1_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0048)) ++ ++#define IFX_ICU_VPE1_IM2_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0050)) ++#define IFX_ICU_VPE1_IM2_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0058)) ++#define IFX_ICU_VPE1_IM2_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0060)) ++#define IFX_ICU_VPE1_IM2_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0068)) ++#define IFX_ICU_VPE1_IM2_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0070)) ++ ++#define IFX_ICU_VPE1_IM3_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0078)) ++#define IFX_ICU_VPE1_IM3_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0080)) ++#define IFX_ICU_VPE1_IM3_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0088)) ++#define IFX_ICU_VPE1_IM3_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0090)) ++#define IFX_ICU_VPE1_IM3_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0098)) ++ ++#define IFX_ICU_VPE1_IM4_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x00A0)) ++#define IFX_ICU_VPE1_IM4_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x00A8)) ++#define IFX_ICU_VPE1_IM4_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x00B0)) ++#define IFX_ICU_VPE1_IM4_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x00B8)) ++#define IFX_ICU_VPE1_IM4_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x00C0)) ++ ++/***Interrupt Vector Value Register***/ ++#define IFX_ICU_VPE1_IM_VEC_5 ((volatile u32*)(IFX_ICU_VPE1 + 0x00C8)) ++#define IFX_ICU_VPE1_IM_VEC ((volatile u32*)(IFX_ICU_VPE1 + 0x00D0)) ++#define IFX_ICU_IM_VEC1 IFX_ICU_VPE1_IM_VEC ++ ++/* MSI PIC */ ++#define IFX_MSI_PIC_REG_BASE (KSEG1 | 0x1F700000) ++ ++#define IFX_MSI1_PIC_REG_BASE (KSEG1 | 0x1F500000) ++ ++#define IFX_MSI_PIC_BIG_ENDIAN 1 ++#define IFX_MSI_PIC_LITTLE_ENDIAN 0 ++ ++#define IFX_MSI_PCI_INT_DISABLE 0x80000000 ++#define IFX_MSI_PIC_INT_LINE 0x30000000 ++#define IFX_MSI_PIC_INT_LINE_S 28 ++#define IFX_MSI_PIC_MSG_ADDR 0x0FFF0000 ++#define IFX_MSI_PIC_MSG_ADDR_S 16 ++#define IFX_MSI_PIC_MSG_DATA 0x0000FFFF ++#define IFX_MSI_PIC_MSG_DATA_S 0x0 ++ ++/***Interrupt Vector Value Mask***/ ++#define IFX_ICU_IM0_VEC_MASK (0x3F << 0) ++#define IFX_ICU_IM1_VEC_MASK (0x3F << 6) ++#define IFX_ICU_IM2_VEC_MASK (0x3F << 12) ++#define IFX_ICU_IM3_VEC_MASK (0x3F << 18) ++#define IFX_ICU_IM4_VEC_MASK (0x3F << 24) ++ ++/***External Interrupt Control Register***/ ++#define IFX_ICU_EIU (KSEG1 | 0x1F101000) ++#define IFX_ICU_EIU_EXIN_C ((volatile u32 *)(IFX_ICU_EIU + 0x0000)) ++#define IFX_ICU_EIU_INIC ((volatile u32 *)(IFX_ICU_EIU + 0x0004)) ++#define IFX_ICU_EIU_INC ((volatile u32 *)(IFX_ICU_EIU + 0x0008)) ++#define IFX_ICU_EIU_INEN ((volatile u32 *)(IFX_ICU_EIU + 0x000C)) ++#define IFX_YIELDEN(n) ((volatile u32 *)(IFX_ICU_EIU + 0x0010 + (n) * 4) ++#define IFX_NMI_CR ((volatile u32 *)(IFX_ICU_EIU + 0x00F0)) ++#define IFX_NMI_SR ((volatile u32 *)(IFX_ICU_EIU + 0x00F4)) ++ ++ ++ ++/***********************************************************************/ ++/* Module : MPS register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_MPS (KSEG1 | 0x1F107000) ++ ++#define IFX_MPS_CHIPID ((volatile u32*)(IFX_MPS + 0x0344)) ++#define IFX_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) ++#define IFX_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) ++#define IFX_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) ++#define IFX_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12) ++#define IFX_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) ++#define IFX_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1) ++ ++ ++/* voice channel 0 ... 3 interrupt enable register */ ++#define IFX_MPS_VC0ENR ((volatile u32*)(IFX_MPS + 0x0000)) ++#define IFX_MPS_VC1ENR ((volatile u32*)(IFX_MPS + 0x0004)) ++#define IFX_MPS_VC2ENR ((volatile u32*)(IFX_MPS + 0x0008)) ++#define IFX_MPS_VC3ENR ((volatile u32*)(IFX_MPS + 0x000C)) ++/* voice channel 0 ... 3 interrupt status read register */ ++#define IFX_MPS_RVC0SR ((volatile u32*)(IFX_MPS + 0x0010)) ++#define IFX_MPS_RVC1SR ((volatile u32*)(IFX_MPS + 0x0014)) ++#define IFX_MPS_RVC2SR ((volatile u32*)(IFX_MPS + 0x0018)) ++#define IFX_MPS_RVC3SR ((volatile u32*)(IFX_MPS + 0x001C)) ++/* voice channel 0 ... 3 interrupt status set register */ ++#define IFX_MPS_SVC0SR ((volatile u32*)(IFX_MPS + 0x0020)) ++#define IFX_MPS_SVC1SR ((volatile u32*)(IFX_MPS + 0x0024)) ++#define IFX_MPS_SVC2SR ((volatile u32*)(IFX_MPS + 0x0028)) ++#define IFX_MPS_SVC3SR ((volatile u32*)(IFX_MPS + 0x002C)) ++/* voice channel 0 ... 3 interrupt status clear register */ ++#define IFX_MPS_CVC0SR ((volatile u32*)(IFX_MPS + 0x0030)) ++#define IFX_MPS_CVC1SR ((volatile u32*)(IFX_MPS + 0x0034)) ++#define IFX_MPS_CVC2SR ((volatile u32*)(IFX_MPS + 0x0038)) ++#define IFX_MPS_CVC3SR ((volatile u32*)(IFX_MPS + 0x003C)) ++/* common status 0 and 1 read register */ ++#define IFX_MPS_RAD0SR ((volatile u32*)(IFX_MPS + 0x0040)) ++#define IFX_MPS_RAD1SR ((volatile u32*)(IFX_MPS + 0x0044)) ++/* common status 0 and 1 set register */ ++#define IFX_MPS_SAD0SR ((volatile u32*)(IFX_MPS + 0x0048)) ++#define IFX_MPS_SAD1SR ((volatile u32*)(IFX_MPS + 0x004C)) ++/* common status 0 and 1 clear register */ ++#define IFX_MPS_CAD0SR ((volatile u32*)(IFX_MPS + 0x0050)) ++#define IFX_MPS_CAD1SR ((volatile u32*)(IFX_MPS + 0x0054)) ++/* common status 0 and 1 enable register */ ++#define IFX_MPS_AD0ENR ((volatile u32*)(IFX_MPS + 0x0058)) ++#define IFX_MPS_AD1ENR ((volatile u32*)(IFX_MPS + 0x005C)) ++/* notification enable register */ ++#define IFX_MPS_CPU0_NFER ((volatile u32*)(IFX_MPS + 0x0060)) ++#define IFX_MPS_CPU1_NFER ((volatile u32*)(IFX_MPS + 0x0064)) ++/* CPU to CPU interrup request register */ ++#define IFX_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(IFX_MPS + 0x0070)) ++#define IFX_MPS_CPU0_2_CPU1_IER ((volatile u32*)(IFX_MPS + 0x0074)) ++/* Global interrupt request and request enable register */ ++#define IFX_MPS_GIRR ((volatile u32*)(IFX_MPS + 0x0078)) ++#define IFX_MPS_GIER ((volatile u32*)(IFX_MPS + 0x007C)) ++ ++#define IFX_MPS_SRAM ((volatile u32*)(KSEG1 | 0x1F200000)) ++ ++#define IFX_MPS_VCPU_FW_AD ((volatile u32*)(KSEG1 | 0x1F2001E0)) ++ ++#define IFX_FUSE_ID_CFG ((volatile u32*)(KSEG1 | 0x1F107350)) ++#define IFX_FUSE_BASE_ADDR (KSEG1 | 0x1F107354) ++ ++ ++ ++/************************************************************************/ ++/* Module : DEU register address and bits */ ++/************************************************************************/ ++ ++#define IFX_DEU_BASE_ADDR (KSEG1 | 0x1E103100) ++ ++/* DEU Control Register */ ++#define IFX_DEU_CLK ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0000)) ++#define IFX_DEU_ID ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0008)) ++ ++/* DEU control register */ ++#define IFX_DES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0010)) ++#define IFX_DES_IHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0014)) ++#define IFX_DES_ILR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0018)) ++#define IFX_DES_K1HR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x001C)) ++#define IFX_DES_K1LR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0020)) ++#define IFX_DES_K3HR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0024)) ++#define IFX_DES_K3LR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0028)) ++#define IFX_DES_IVHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x002C)) ++#define IFX_DES_IVLR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0030)) ++#define IFX_DES_OHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0040)) ++#define IFX_DES_OLR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050)) ++ ++/* AES DEU register */ ++#define IFX_AES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050)) ++#define IFX_AES_ID3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0054)) ++#define IFX_AES_ID2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0058)) ++#define IFX_AES_ID1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x005C)) ++#define IFX_AES_ID0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0060)) ++ ++/* AES Key register */ ++#define IFX_AES_K7R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0064)) ++#define IFX_AES_K6R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0068)) ++#define IFX_AES_K5R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x006C)) ++#define IFX_AES_K4R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0070)) ++#define IFX_AES_K3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0074)) ++#define IFX_AES_K2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0078)) ++#define IFX_AES_K1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x007C)) ++#define IFX_AES_K0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0080)) ++ ++/* AES vector register */ ++#define IFX_AES_IV3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0084)) ++#define IFX_AES_IV2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0088)) ++#define IFX_AES_IV1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x008C)) ++#define IFX_AES_IV0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0090)) ++#define IFX_AES_0D3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0094)) ++#define IFX_AES_0D2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0098)) ++#define IFX_AES_OD1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x009C)) ++#define IFX_AES_OD0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00A0)) ++ ++/* ARC4 DEU register */ ++#define IFX_ARC4_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0100)) ++#define IFX_ARC4_IDLEN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0114)) ++#define IFX_ARC4_ID3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0118)) ++#define IFX_ARC4_ID2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x011C)) ++#define IFX_ARC4_ID1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0120)) ++#define IFX_ARC4_ID0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0124)) ++ ++/* ARC4 Key register */ ++#define IFX_ARC4_K3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0104)) ++#define IFX_ARC4_K2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0108)) ++#define IFX_ARC4_K1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x010C)) ++#define IFX_ARC4_K0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0110)) ++ ++/* ARC4 vector register */ ++#define IFX_ARC4_OD3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0128)) ++#define IFX_ARC4_OD2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x012C)) ++#define IFX_ARC4_OD1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0130)) ++#define IFX_ARC4_OD0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0134)) ++ ++/* hash control register */ ++#define IFX_HASH_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B0)) ++#define IFX_HASH_MR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B4)) ++#define IFX_HASH_D1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B8)) ++#define IFX_HASH_D2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00BC)) ++#define IFX_HASH_D3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C0)) ++#define IFX_HASH_D4R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C4)) ++#define IFX_HASH_D5R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C8)) ++ ++#define IFX_HMAC_KIDX ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00D0)) ++#define IFX_HMAC_KEY ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00D4)) ++#define IFX_HMAC_DBN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00D8)) ++ ++#define IFX_DEU_DMA_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00EC)) ++ ++#define IFX_DEU_IRNEN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00F4)) ++#define IFX_DEU_IRNCR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00F8)) ++#define IFX_DEU_IRNICR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00FC)) ++ ++ ++ ++/************************************************************************/ ++/* Module : PPE register address and bits */ ++/************************************************************************/ ++ ++#define IFX_PPE32_BASE (KSEG1 | 0x1E200000) ++#define IFX_PPE32_DEBUG_BREAK_TRACE_REG (IFX_PPE32_BASE + (0x0000 * 4)) ++#define IFX_PPE32_INT_MASK_STATUS_REG (IFX_PPE32_BASE + (0x0030 * 4)) ++#define IFX_PPE32_INT_RESOURCE_REG (IFX_PPE32_BASE + (0x0040 * 4)) ++#define IFX_PPE32_CDM_CODE_MEM_B0 (IFX_PPE32_BASE + (0x1000 * 4)) ++#define IFX_PPE32_CDM_CODE_MEM_B1 (IFX_PPE32_BASE + (0x2000 * 4)) ++#define IFX_PPE32_DATA_MEM_MAP_REG_BASE (IFX_PPE32_BASE + (0x4000 * 4)) ++ ++#define IFX_PPE32_SRST (IFX_PPE32_BASE + 0x10080) ++ ++/* ++ * ETOP MDIO Registers ++ */ ++#define IFX_PP32_ETOP_MDIO_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4))) ++#define IFX_PP32_ETOP_MDIO_ACC ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4))) ++#define IFX_PP32_ETOP_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4))) ++#define IFX_PP32_ETOP_IG_VLAN_COS ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4))) ++#define IFX_PP32_ETOP_IG_DSCP_COS3 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4))) ++#define IFX_PP32_ETOP_IG_DSCP_COS2 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4))) ++#define IFX_PP32_ETOP_IG_DSCP_COS1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4))) ++#define IFX_PP32_ETOP_IG_DSCP_COS0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4))) ++#define IFX_PP32_ETOP_IG_PLEN_CTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4))) ++#define IFX_PP32_ETOP_ISR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4))) ++#define IFX_PP32_ETOP_IER ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4))) ++#define IFX_PP32_ETOP_VPID ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4))) ++#define IFX_PP32_ENET_MAC_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4))) ++#define IFX_PP32_ENETS_DBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4))) ++#define IFX_PP32_ENETS_CBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4))) ++#define IFX_PP32_ENETS_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4))) ++#define IFX_PP32_ENETS_PGCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4))) ++#define IFX_PP32_ENETS_PKTCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4))) ++#define IFX_PP32_ENETS_BUF_CTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4))) ++#define IFX_PP32_ENETS_COS_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4))) ++#define IFX_PP32_ENETS_IGDROP ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4))) ++#define IFX_PP32_ENETS_IGERR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4))) ++#define IFX_PP32_ENET_MAC_DA0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4))) ++#define IFX_PP32_ENET_MAC_DA1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4))) ++ ++#define IFX_PP32_ENETF_DBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0630 * 4))) ++#define IFX_PP32_ENETF_CBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0631 * 4))) ++#define IFX_PP32_ENETF_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0632 * 4))) ++#define IFX_PP32_ENETF_PGCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0633 * 4))) ++#define IFX_PP32_ENETF_PKTCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0634 * 4))) ++#define IFX_PP32_ENETF_HFCTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0635 * 4))) ++#define IFX_PP32_ENETF_TXCTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0636 * 4))) ++ ++#define IFX_PP32_ENETF_VLCOS0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0638 * 4))) ++#define IFX_PP32_ENETF_VLCOS1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0639 * 4))) ++#define IFX_PP32_ENETF_VLCOS2 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063A * 4))) ++#define IFX_PP32_ENETF_VLCOS3 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063B * 4))) ++#define IFX_PP32_ENETF_EGERR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063C * 4))) ++#define IFX_PP32_ENETF_EGDROP ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063D * 4))) ++ ++ ++/* Sharebuff SB RAM2 control data */ ++#define IFX_PP32_SB2_DATABASE ((IFX_PPE32_BASE + (0x8C00 * 4))) ++#define IFX_PP32_SB2_CTRLBASE ((IFX_PPE32_BASE + (0x92E0 * 4))) ++ ++ ++#if 0 // AR10 has 7 port switch inherited from VR9 ++/************************************************************************/ ++/* Module : 3-port Switch register address and bits */ ++/************************************************************************/ ++ ++#define IFX_SW (KSEG1 | 0x1E108000) ++ ++#define IFX_SW_PS (IFX_SW + 0x000) ++#define IFX_SW_P0_CTL (IFX_SW + 0x004) ++#define IFX_SW_P1_CTL (IFX_SW + 0x008) ++#define IFX_SW_P2_CTL (IFX_SW + 0x00C) ++#define IFX_SW_P0_VLAN (IFX_SW + 0x010) ++#define IFX_SW_P1_VLAN (IFX_SW + 0x014) ++#define IFX_SW_P2_VLAN (IFX_SW + 0x018) ++#define IFX_SW_P0_INCTL (IFX_SW + 0x020) ++#define IFX_SW_P1_INCTL (IFX_SW + 0x024) ++#define IFX_SW_P2_INCTL (IFX_SW + 0x028) ++#define IFX_SW_DF_PORTMAP (IFX_SW + 0x02C) ++#define IFX_SW_P0_ECS_Q32 (IFX_SW + 0x030) ++#define IFX_SW_P0_ECS_Q10 (IFX_SW + 0x034) ++#define IFX_SW_P0_ECW_Q32 (IFX_SW + 0x038) ++#define IFX_SW_P0_ECW_Q10 (IFX_SW + 0x03C) ++#define IFX_SW_P1_ECS_Q32 (IFX_SW + 0x040) ++#define IFX_SW_P1_ECS_Q10 (IFX_SW + 0x044) ++#define IFX_SW_P1_ECW_Q32 (IFX_SW + 0x048) ++#define IFX_SW_P1_ECW_Q10 (IFX_SW + 0x04C) ++#define IFX_SW_P2_ECS_Q32 (IFX_SW + 0x050) ++#define IFX_SW_P2_ECS_Q10 (IFX_SW + 0x054) ++#define IFX_SW_P2_ECW_Q32 (IFX_SW + 0x058) ++#define IFX_SW_P2_ECW_Q10 (IFX_SW + 0x05C) ++#define IFX_SW_INT_ENA (IFX_SW + 0x060) ++#define IFX_SW_INT_ST (IFX_SW + 0x064) ++#define IFX_SW_GCTL0 (IFX_SW + 0x068) ++#define IFX_SW_GCTL1 (IFX_SW + 0x06C) ++#define IFX_SW_ARP (IFX_SW + 0x070) ++#define IFX_SW_STRM_CTL (IFX_SW + 0x074) ++#define IFX_SW_RGMII_CTL (IFX_SW + 0x078) ++#define IFX_SW_1P_PRT (IFX_SW + 0x07C) ++#define IFX_SW_GBKT_SZBS (IFX_SW + 0x080) ++#define IFX_SW_GBKT_SZEBS (IFX_SW + 0x084) ++#define IFX_SW_BF_TH (IFX_SW + 0x088) ++#define IFX_SW_PMAC_HD_CTL (IFX_SW + 0x08C) ++#define IFX_SW_PMAC_SA1 (IFX_SW + 0x090) ++#define IFX_SW_PMAC_SA2 (IFX_SW + 0x094) ++#define IFX_SW_PMAC_DA1 (IFX_SW + 0x098) ++#define IFX_SW_PMAC_DA2 (IFX_SW + 0x09C) ++#define IFX_SW_PMAC_VLAN (IFX_SW + 0x0A0) ++#define IFX_SW_PMAC_TX_IPG (IFX_SW + 0x0A4) ++#define IFX_SW_PMAC_RX_IPG (IFX_SW + 0x0A8) ++#define IFX_SW_ADR_TB_CTL0 (IFX_SW + 0x0AC) ++#define IFX_SW_ADR_TB_CTL1 (IFX_SW + 0x0B0) ++#define IFX_SW_ADR_TB_CTL2 (IFX_SW + 0x0B4) ++#define IFX_SW_ADR_TB_ST0 (IFX_SW + 0x0B8) ++#define IFX_SW_ADR_TB_ST1 (IFX_SW + 0x0BC) ++#define IFX_SW_ADR_TB_ST2 (IFX_SW + 0x0C0) ++#define IFX_SW_RMON_CTL (IFX_SW + 0x0C4) ++#define IFX_SW_RMON_ST (IFX_SW + 0x0C8) ++#define IFX_SW_MDIO_CTL (IFX_SW + 0x0CC) ++#define IFX_SW_MDIO_DATA (IFX_SW + 0x0D0) ++#define IFX_SW_TP_FLT_ACT (IFX_SW + 0x0D4) ++#define IFX_SW_PRTCL_FLT_ACT (IFX_SW + 0x0D8) ++#define IFX_SW_VLAN_FLT0 (IFX_SW + 0x100) ++#define IFX_SW_VLAN_FLT1 (IFX_SW + 0x104) ++#define IFX_SW_VLAN_FLT2 (IFX_SW + 0x108) ++#define IFX_SW_VLAN_FLT3 (IFX_SW + 0x10C) ++#define IFX_SW_VLAN_FLT4 (IFX_SW + 0x110) ++#define IFX_SW_VLAN_FLT5 (IFX_SW + 0x114) ++#define IFX_SW_VLAN_FLT6 (IFX_SW + 0x118) ++#define IFX_SW_VLAN_FLT7 (IFX_SW + 0x11C) ++#define IFX_SW_VLAN_FLT8 (IFX_SW + 0x120) ++#define IFX_SW_VLAN_FLT9 (IFX_SW + 0x124) ++#define IFX_SW_VLAN_FLT10 (IFX_SW + 0x128) ++#define IFX_SW_VLAN_FLT11 (IFX_SW + 0x12C) ++#define IFX_SW_VLAN_FLT12 (IFX_SW + 0x130) ++#define IFX_SW_VLAN_FLT13 (IFX_SW + 0x134) ++#define IFX_SW_VLAN_FLT14 (IFX_SW + 0x138) ++#define IFX_SW_VLAN_FLT15 (IFX_SW + 0x13C) ++#define IFX_SW_TP_FLT10 (IFX_SW + 0x140) ++#define IFX_SW_TP_FLT32 (IFX_SW + 0x144) ++#define IFX_SW_TP_FLT54 (IFX_SW + 0x148) ++#define IFX_SW_TP_FLT76 (IFX_SW + 0x14C) ++#define IFX_SW_DFSRV_MAP0 (IFX_SW + 0x150) ++#define IFX_SW_DFSRV_MAP1 (IFX_SW + 0x154) ++#define IFX_SW_DFSRV_MAP2 (IFX_SW + 0x158) ++#define IFX_SW_DFSRV_MAP3 (IFX_SW + 0x15C) ++#define IFX_SW_TCP_PF0 (IFX_SW + 0x160) ++#define IFX_SW_TCP_PF1 (IFX_SW + 0x164) ++#define IFX_SW_TCP_PF2 (IFX_SW + 0x168) ++#define IFX_SW_TCP_PF3 (IFX_SW + 0x16C) ++#define IFX_SW_TCP_PF4 (IFX_SW + 0x170) ++#define IFX_SW_TCP_PF5 (IFX_SW + 0x174) ++#define IFX_SW_TCP_PF6 (IFX_SW + 0x178) ++#define IFX_SW_TCP_PF7 (IFX_SW + 0x17C) ++#define IFX_SW_RA_03_00 (IFX_SW + 0x180) ++#define IFX_SW_RA_07_04 (IFX_SW + 0x184) ++#define IFX_SW_RA_0B_08 (IFX_SW + 0x188) ++#define IFX_SW_RA_0F_0C (IFX_SW + 0x18C) ++#define IFX_SW_RA_13_10 (IFX_SW + 0x190) ++#define IFX_SW_RA_17_14 (IFX_SW + 0x194) ++#define IFX_SW_RA_1B_18 (IFX_SW + 0x198) ++#define IFX_SW_RA_1F_1C (IFX_SW + 0x19C) ++#define IFX_SW_RA_23_20 (IFX_SW + 0x1A0) ++#define IFX_SW_RA_27_24 (IFX_SW + 0x1A4) ++#define IFX_SW_RA_2B_28 (IFX_SW + 0x1A8) ++#define IFX_SW_RA_2F_2C (IFX_SW + 0x1AC) ++#define IFX_SW_F0 (IFX_SW + 0x1B0) ++#define IFX_SW_F1 (IFX_SW + 0x1B4) ++#endif ++ ++/************************************************************************/ ++/* Module : XBAR Register definition */ ++/************************************************************************/ ++#define IFX_XBAR_REG_BASE (KSEG1 | 0x1F400000) ++ ++#define IFX_XBAR_ALWAYS_LAST (volatile u32*)(IFX_XBAR_REG_BASE + 0x430) ++#define IFX_XBAR_FPI_BURST_EN 0x00000002 ++#define IFX_XBAR_AHB_BURST_EN 0x00000004 ++ ++/* ++ * Routine for Voice ++ */ ++extern const void (*ifx_bsp_basic_mps_decrypt)(unsigned int addr, int n); ++ ++#endif /* AR10_H */ +diff --git a/arch/mips/include/asm/ifx/ar10/ar10_ref_board.h b/arch/mips/include/asm/ifx/ar10/ar10_ref_board.h +new file mode 100644 +index 0000000..12fcac7 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ar10/ar10_ref_board.h +@@ -0,0 +1,54 @@ ++/****************************************************************************** ++** ++** FILE NAME : ar10_ref_board.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : header file for AR10 ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef AR10_REF_BOARD_H ++#define AR10_REF_BOARD_H ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++ ++#if defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) \ ++ || defined(CONFIG_IFX_USIF_SPI_FLASH) || defined (CONFIG_IFX_USIF_SPI_FLASH_MODULE) ++#define IFX_MTD_SPI_PART_NB 3 ++#define IFX_SPI_FLASH_MAX 8 ++#endif /* defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) */ ++ ++#if defined(CONFIG_USB_HOST_IFX) || defined(CONFIG_USB_HOST_IFX_MODULE) ++#if defined(CONFIG_AR10_FAMILY_BOARD_1_1) ++ #define IFX_LEDLED_USB_VBUS1 19 ++ #define IFX_LEDLED_USB_VBUS2 16 ++#endif ++ ++#if defined(CONFIG_AR10_FAMILY_BOARD_1_2) ++ #define IFX_LEDLED_USB_VBUS1 4 ++ #define IFX_LEDLED_USB_VBUS2 7 ++#endif ++ ++#endif ++ ++ ++ ++#endif /* AR10_REF_BOARD_H */ ++ +diff --git a/arch/mips/include/asm/ifx/ar10/emulation.h b/arch/mips/include/asm/ifx/ar10/emulation.h +new file mode 100644 +index 0000000..e26ea1f +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ar10/emulation.h +@@ -0,0 +1,46 @@ ++/****************************************************************************** ++** ++** FILE NAME : emulation.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Lei Chuan Hua ++** DESCRIPTION : header file for AR10 ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Lei Chuan Hua The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef EMULATION_H ++#define EMULATION_H ++ ++#ifdef CONFIG_USE_EMULATOR ++ ++#ifdef CONFIG_USE_VENUS ++ #define EMULATOR_CPU_SPEED 4000000 //3333333 ++ #define PLL0_CLK_SPEED 2500000 ++#elif defined(CONFIG_USE_PALLADIUM) ++ #define EMULATOR_CPU_SPEED 120000 ++ #define PLL0_CLK_SPEED 120000 ++#else ++ #define EMULATOR_CPU_SPEED 25000 ++ #define PLL0_CLK_SPEED 25000 ++#endif /* CONFIG_USE_VENUS */ ++#else /* Real chip */ ++ #define PLL0_CLK_SPEED 1000000000 ++#endif /* CONFIG_USE_EMULATOR */ ++#endif /* */ ++ /* EMULATION_H */ ++ +diff --git a/arch/mips/include/asm/ifx/ar10/irq.h b/arch/mips/include/asm/ifx/ar10/irq.h +new file mode 100644 +index 0000000..1af143e +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ar10/irq.h +@@ -0,0 +1,214 @@ ++/****************************************************************************** ++** ++** FILE NAME : irq.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : header file for AR10 ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef AR10_IRQ_H ++#define AR10_IRQ_H ++ ++ ++ ++/****** Interrupt Assigments ***********/ ++ ++#define IFX_ASC1_TIR INT_NUM_IM3_IRL7 /* TX interrupt */ ++#define IFX_ASC1_TBIR INT_NUM_IM3_IRL8 /* TX buffer interrupt */ ++#define IFX_ASC1_RIR INT_NUM_IM3_IRL9 /* RX interrupt */ ++#define IFX_ASC1_EIR INT_NUM_IM3_IRL10 /* ERROR interrupt */ ++#define IFX_ASC1_ABSTIR INT_NUM_IM3_IRL11 ++#define IFX_ASC1_ABDETIR INT_NUM_IM3_IRL12 ++#define IFX_ASC1_SFCIR INT_NUM_IM3_IRL13 ++ ++#define IFX_FPI_SLAVE_BCU0_IR INT_NUM_IM1_IRL25 ++#define IFX_FPI_MASTER_COSBCU_IR INT_NUM_IM0_IRL25 ++#define IFX_CROSSBAR_ERR_IR INT_NUM_IM4_IRL23 ++#define IFX_FPI_SLAVE_BCU_IRQ IFX_FPI_SLAVE_BCU0_IR ++#define IFX_FPI_MASTER_BCU_IRQ IFX_FPI_MASTER_COSBCU_IR ++ ++#define IFX_DSL_DFE_IR INT_NUM_IM1_IRL23 ++#define IFX_DSL_AFEOVL_IR INT_NUM_IM1_IRL24 ++#define IFX_DSL_DYING_GASP_INT INT_NUM_IM1_IRL21 ++#define IFX_DSL_DFE_INT0IR INT_NUM_IM2_IRL12 ++#define IFX_DSL_DFE_INT1IR INT_NUM_IM2_IRL13 ++#define IFX_DSL_DFE_INT2IR INT_NUM_IM2_IRL14 ++#define IFX_DSL_DFE_INT3IR INT_NUM_IM2_IRL15 ++#define IFX_DSL_SI INT_NUM_IM2_IRL20 ++#define IFX_DSL_WAKEUP INT_NUM_IM2_IRL22 ++#define IFX_MEI_INT IFX_DSL_DFE_IR ++#define IFX_MEI_DYING_GASP_INT IFX_DSL_DYING_GASP_INT ++#define IFX_DSL_DFE_TXIR IFX_DSL_DFE_INT0IR ++#define IFX_DSL_DFE_RXIR IFX_DSL_DFE_INT1IR ++ ++#define IFX_PCIE_INTA INT_NUM_IM4_IRL8 ++#define IFX_PCIE_INTB INT_NUM_IM4_IRL9 ++#define IFX_PCIE_INTC INT_NUM_IM4_IRL10 ++#define IFX_PCIE_INTD INT_NUM_IM4_IRL11 ++#define IFX_PCIE_IR INT_NUM_IM4_IRL25 ++#define IFX_PCIE_WAKE INT_NUM_IM4_IRL26 ++#define IFX_PCIE_MSI_IR0 INT_NUM_IM4_IRL27 ++#define IFX_PCIE_MSI_IR1 INT_NUM_IM4_IRL28 ++#define IFX_PCIE_MSI_IR2 INT_NUM_IM4_IRL29 ++#define IFX_PCIE_MSI_IR3 INT_NUM_IM0_IRL30 ++#define IFX_PCIE_L3_INT INT_NUM_IM3_IRL16 ++ ++#define IFX_PCIE1_INTA INT_NUM_IM0_IRL9 ++#define IFX_PCIE1_INTB INT_NUM_IM0_IRL10 ++#define IFX_PCIE1_INTC INT_NUM_IM0_IRL11 ++#define IFX_PCIE1_INTD INT_NUM_IM0_IRL12 ++#define IFX_PCIE1_IR INT_NUM_IM1_IRL17 ++#define IFX_PCIE1_WAKE INT_NUM_IM1_IRL18 ++#define IFX_PCIE1_MSI_IR0 INT_NUM_IM1_IRL9 ++#define IFX_PCIE1_MSI_IR1 INT_NUM_IM1_IRL10 ++#define IFX_PCIE1_MSI_IR2 INT_NUM_IM1_IRL11 ++#define IFX_PCIE1_MSI_IR3 INT_NUM_IM1_IRL12 ++#define IFX_PCIE1_L3_INT INT_NUM_IM1_IRL13 ++ ++#define IFX_VOICE_DFE0_CH0_RX INT_NUM_IM4_IRL12 ++#define IFX_VOICE_DFE0_CH0_TX INT_NUM_IM4_IRL13 ++#define IFX_VOICE_DFE0_CH0_GP INT_NUM_IM0_IRL31 ++#define IFX_VOICE_DFE0_CH1_RX INT_NUM_IM3_IRL19 ++#define IFX_VOICE_DFE0_CH1_TX INT_NUM_IM3_IRL20 ++#define IFX_VOICE_DFE0_CH1_GP INT_NUM_IM3_IRL14 ++#define IFX_VOICE_DFE1_CH0_RX INT_NUM_IM1_IRL3 ++#define IFX_VOICE_DFE1_CH0_TX INT_NUM_IM1_IRL4 ++#define IFX_VOICE_DFE1_CH0_GP INT_NUM_IM1_IRL5 ++#define IFX_VOICE_DFE1_CH1_RX INT_NUM_IM1_IRL6 ++#define IFX_VOICE_DFE1_CH1_TX INT_NUM_IM1_IRL7 ++#define IFX_VOICE_DFE1_CH1_GP INT_NUM_IM1_IRL8 ++ ++#define IFX_DEU_DESIR INT_NUM_IM0_IRL27 ++#define IFX_DEU_AESIR INT_NUM_IM0_IRL28 ++#define IFX_DEU_HASHIR INT_NUM_IM0_IRL29 ++#define IFX_DEU_ARCIR INT_NUM_IM0_IRL26 ++ ++#define IFX_DMA_CH0_INT INT_NUM_IM2_IRL0 ++#define IFX_DMA_CH1_INT INT_NUM_IM2_IRL1 ++#define IFX_DMA_CH2_INT INT_NUM_IM2_IRL2 ++#define IFX_DMA_CH3_INT INT_NUM_IM2_IRL3 ++#define IFX_DMA_CH4_INT INT_NUM_IM2_IRL4 ++#define IFX_DMA_CH5_INT INT_NUM_IM2_IRL5 ++#define IFX_DMA_CH6_INT INT_NUM_IM2_IRL6 ++#define IFX_DMA_CH7_INT INT_NUM_IM2_IRL7 ++#define IFX_DMA_CH8_INT INT_NUM_IM2_IRL8 ++#define IFX_DMA_CH9_INT INT_NUM_IM2_IRL9 ++#define IFX_DMA_CH10_INT INT_NUM_IM2_IRL10 ++#define IFX_DMA_CH11_INT INT_NUM_IM2_IRL11 ++#define IFX_DMA_CH12_INT INT_NUM_IM2_IRL25 ++#define IFX_DMA_CH13_INT INT_NUM_IM2_IRL26 ++#define IFX_DMA_CH14_INT INT_NUM_IM2_IRL27 ++#define IFX_DMA_CH15_INT INT_NUM_IM2_IRL28 ++#define IFX_DMA_CH16_INT INT_NUM_IM2_IRL29 ++#define IFX_DMA_CH17_INT INT_NUM_IM1_IRL30 ++#define IFX_DMA_CH18_INT INT_NUM_IM2_IRL16 ++#define IFX_DMA_CH19_INT INT_NUM_IM2_IRL21 ++#define IFX_DMA_CH20_INT INT_NUM_IM4_IRL0 ++#define IFX_DMA_CH21_INT INT_NUM_IM4_IRL1 ++#define IFX_DMA_CH22_INT INT_NUM_IM4_IRL2 ++#define IFX_DMA_CH23_INT INT_NUM_IM4_IRL3 ++#define IFX_DMA_CH24_INT INT_NUM_IM4_IRL4 ++#define IFX_DMA_CH25_INT INT_NUM_IM4_IRL5 ++#define IFX_DMA_CH26_INT INT_NUM_IM4_IRL6 ++#define IFX_DMA_CH27_INT INT_NUM_IM4_IRL7 ++#define IFX_DMA_FCC_INT INT_NUM_IM0_IRL13 ++ ++#define IFX_PPE_MBOX_INT0 INT_NUM_IM2_IRL23 ++#define IFX_PPE_MBOX_INT1 INT_NUM_IM2_IRL24 ++#define IFX_PPE_MBOX_INT2 INT_NUM_IM1_IRL29 ++#define IFX_PPE_QSB_INT INT_NUM_IM1_IRL31 ++ ++#define IFX_GE_SW_INT INT_NUM_IM1_IRL16 ++ ++#define IFX_GPHY_CD_INT INT_NUM_IM3_IRL17 ++#define IFX_GPHY_INT INT_NUM_IM3_IRL18 ++ ++#define IFX_EIU_IR0 INT_NUM_IM4_IRL30 /* 158 */ ++#define IFX_EIU_IR1 INT_NUM_IM3_IRL31 /* 127 */ ++#define IFX_EIU_IR2 INT_NUM_IM1_IRL26 /* 58 */ ++#define IFX_EIU_IR3 INT_NUM_IM1_IRL1 /* 33 */ ++#define IFX_EIU_IR4 INT_NUM_IM1_IRL2 /* 34 */ ++ ++#define IFX_MPS_IR0 INT_NUM_IM4_IRL14 ++#define IFX_MPS_IR1 INT_NUM_IM4_IRL15 ++#define IFX_MPS_IR2 INT_NUM_IM4_IRL16 ++#define IFX_MPS_IR3 INT_NUM_IM4_IRL17 ++#define IFX_MPS_IR4 INT_NUM_IM4_IRL18 ++#define IFX_MPS_IR5 INT_NUM_IM4_IRL19 ++#define IFX_MPS_IR6 INT_NUM_IM4_IRL20 ++#define IFX_MPS_IR7 INT_NUM_IM4_IRL21 ++#define IFX_MPS_IR8 INT_NUM_IM4_IRL22 ++#define IFX_MPS_SEMAPHORE_IR IFX_MPS_IR7 ++#define IFX_MPS_GLOBAL_IR IFX_MPS_IR8 ++ ++#define IFX_RTI_8KHZ_IR INT_NUM_IM2_IRL31 ++ ++#define IFX_GPTU_TC1A INT_NUM_IM3_IRL22 ++#define IFX_GPTU_TC1B INT_NUM_IM3_IRL23 ++#define IFX_GPTU_TC2A INT_NUM_IM3_IRL24 ++#define IFX_GPTU_TC2B INT_NUM_IM3_IRL25 ++#define IFX_GPTU_TC3A INT_NUM_IM3_IRL26 ++#define IFX_GPTU_TC3B INT_NUM_IM3_IRL27 ++ ++#define IFX_MC_IR INT_NUM_IM3_IRL28 ++ ++#define IFX_EBU_IR INT_NUM_IM0_IRL22 ++ ++#define IFX_PCI_IR INT_NUM_IM1_IRL17 ++#define IFX_PCI_WRIR INT_NUM_IM1_IRL18 ++ ++#define IFX_PCM_TXIR INT_NUM_IM1_IRL19 ++#define IFX_PCM_RXIR INT_NUM_IM1_IRL20 ++ ++#define IFX_PMCIR INT_NUM_IM4_IRL31 ++ ++#define IFX_SBIU_ERRIR INT_NUM_IM1_IRL27 ++ ++#define IFX_SSC_RIR INT_NUM_IM0_IRL14 ++#define IFX_SSC_TIR INT_NUM_IM0_IRL15 ++#define IFX_SSC_EIR INT_NUM_IM0_IRL16 ++#define IFX_SSC_FIR INT_NUM_IM0_IRL17 ++ ++#define IFX_MMC_CONTROLLER_INTR0_IRQ INT_NUM_IM0_IRL18 ++#define IFX_MMC_CONTROLLER_INTR1_IRQ INT_NUM_IM0_IRL19 ++#define IFX_MMC_CONTROLLER_SDIO_I_IRQ INT_NUM_IM0_IRL20 ++ ++#define IFX_USB0_IR INT_NUM_IM1_IRL22 ++#define IFX_USB1_IR INT_NUM_IM1_IRL16 ++#define IFX_USB0_OCIR INT_NUM_IM1_IRL28 ++#define IFX_USB1_OCIR INT_NUM_IM1_IRL24 // same as IFX_DSL_AFEOVL_IR ++#define IFX_USB_INT IFX_USB0_IR ++#define IFX_USB_OC_INT IFX_USB0_OCIR ++ ++#define IFX_WDT_AEIR INT_NUM_IM4_IRL24 ++ ++#define IFX_OVD_INT INT_NUM_IM3_IRL15 ++#define IFX_PSU_INT INT_NUM_IM3_IRL30 ++ ++#define IFX_USIF_EIR_INT INT_NUM_IM3_IRL3 ++#define IFX_USIF_STA_INT INT_NUM_IM3_IRL4 ++#define IFX_USIF_AB_INT INT_NUM_IM3_IRL5 ++#define IFX_USIF_WKP_INT INT_NUM_IM3_IRL6 ++#define IFX_USIF_TX_INT INT_NUM_IM0_IRL21 ++#define IFX_USIF_RX_INT INT_NUM_IM3_IRL21 ++ ++ ++#endif // AR10_IRQ_H ++ +diff --git a/arch/mips/include/asm/ifx/ar10/model.h b/arch/mips/include/asm/ifx/ar10/model.h +new file mode 100644 +index 0000000..9ddcba0 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ar10/model.h +@@ -0,0 +1,54 @@ ++/****************************************************************************** ++** ++** FILE NAME : model.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : header file for AR10 ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef AR10_MODEL_H ++#define AR10_MODEL_H ++/****************************************************************************** ++ Copyright (c) 2002, Infineon Technologies. All rights reserved. ++ ++ No Warranty ++ Because the program is licensed free of charge, there is no warranty for ++ the program, to the extent permitted by applicable law. Except when ++ otherwise stated in writing the copyright holders and/or other parties ++ provide the program "as is" without warranty of any kind, either ++ expressed or implied, including, but not limited to, the implied ++ warranties of merchantability and fitness for a particular purpose. The ++ entire risk as to the quality and performance of the program is with ++ you. should the program prove defective, you assume the cost of all ++ necessary servicing, repair or correction. ++ ++ In no event unless required by applicable law or agreed to in writing ++ will any copyright holder, or any other party who may modify and/or ++ redistribute the program as permitted above, be liable to you for ++ damages, including any general, special, incidental or consequential ++ damages arising out of the use or inability to use the program ++ (including but not limited to loss of data or data being rendered ++ inaccurate or losses sustained by you or third parties or a failure of ++ the program to operate with any other programs), even if such holder or ++ other party has been advised of the possibility of such damages. ++******************************************************************************/ ++#define BOARD_SYSTEM_TYPE "AR10" ++#define SYSTEM_MODEL_NAME "AR10 First Version" ++#endif +diff --git a/arch/mips/include/asm/ifx/ar9/ar9.h b/arch/mips/include/asm/ifx/ar9/ar9.h +new file mode 100644 +index 0000000..f359985 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ar9/ar9.h +@@ -0,0 +1,1327 @@ ++/****************************************************************************** ++** ++** FILE NAME : ar9.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : header file for AR9 ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef AR9_H ++#define AR9_H ++#include ++/****************************************************************************** ++ Copyright (c) 2002, Infineon Technologies. All rights reserved. ++ ++ No Warranty ++ Because the program is licensed free of charge, there is no warranty for ++ the program, to the extent permitted by applicable law. Except when ++ otherwise stated in writing the copyright holders and/or other parties ++ provide the program "as is" without warranty of any kind, either ++ expressed or implied, including, but not limited to, the implied ++ warranties of merchantability and fitness for a particular purpose. The ++ entire risk as to the quality and performance of the program is with ++ you. should the program prove defective, you assume the cost of all ++ necessary servicing, repair or correction. ++ ++ In no event unless required by applicable law or agreed to in writing ++ will any copyright holder, or any other party who may modify and/or ++ redistribute the program as permitted above, be liable to you for ++ damages, including any general, special, incidental or consequential ++ damages arising out of the use or inability to use the program ++ (including but not limited to loss of data or data being rendered ++ inaccurate or losses sustained by you or third parties or a failure of ++ the program to operate with any other programs), even if such holder or ++ other party has been advised of the possibility of such damages. ++******************************************************************************/ ++#define MACH_GROUP_IFX MACH_GROUP_AR9 ++#define MACH_TYPE_IFX MACH_AR9 ++ ++ ++/***********************************************************************/ ++/* Module : WDT register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_WDT (KSEG1 | 0x1F880000) ++ ++/***Watchdog Timer Control Register ***/ ++#define IFX_WDT_CR ((volatile u32*)(IFX_WDT + 0x03F0)) ++#define IFX_WDT_CR_GEN (1 << 31) ++#define IFX_WDT_CR_DSEN (1 << 30) ++#define IFX_WDT_CR_LPEN (1 << 29) ++#define IFX_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1)) ++#define IFX_WDT_CR_PWL_SET(value) (((( 1 << 2) - 1) & (value)) << 26) ++#define IFX_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1)) ++#define IFX_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24) ++#define IFX_WDT_CR_PW_GET(value) (((value) >> 16) & ((1 << 8) - 1)) ++#define IFX_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16) ++#define IFX_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1)) ++#define IFX_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0) ++ ++/***Watchdog Timer Status Register***/ ++#define IFX_WDT_SR ((volatile u32*)(IFX_WDT + 0x03F8)) ++#define IFX_WDT_SR_EN (1 << 31) ++#define IFX_WDT_SR_AE (1 << 30) ++#define IFX_WDT_SR_PRW (1 << 29) ++#define IFX_WDT_SR_EXP (1 << 28) ++#define IFX_WDT_SR_PWD (1 << 27) ++#define IFX_WDT_SR_DS (1 << 26) ++#define IFX_WDT_SR_VALUE_GET(value) (((value) >> 0) & ((1 << 16) - 1)) ++#define IFX_WDT_SR_VALUE_SET(value) (((( 1 << 16) - 1) & (value)) << 0) ++ ++/***********************************************************************/ ++/* Module : RCU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_RCU (KSEG1 | 0x1F203000) ++ ++#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) ++#define IFX_RCU_RST_STAT ((volatile u32*)(IFX_RCU + 0x0014)) ++#define IFX_USB_CFG ((volatile u32*)(IFX_RCU + 0x0018)) ++#define IFX_RCU_PPE_CONF ((volatile u32*)(IFX_RCU + 0x002C)) ++ ++/***Reset Request Register***/ ++#define IFX_RCU_RST_REQ_SRST (1 << 30) ++#define IFX_RCU_RST_REQ_ARC_JTAG (1 << 20) ++#define IFX_RCU_RST_REQ_AFE (1 << 11) ++#define IFX_RCU_RST_REQ_PPE (1 << 8) ++#define IFX_RCU_RST_REQ_DFE (1 << 7) ++ ++/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */ ++#define IFX_RCU_RST_REQ_ALL IFX_RCU_RST_REQ_SRST ++ ++ ++ ++/***********************************************************************/ ++/* Module : BCU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_BCU_BASE_ADDR (KSEG1 | 0x1E100000) ++#define IFX_SLAVE_BCU_BASE_ADDR (KSEG1 | 0x1C200400) ++ ++/***BCU Control Register (0010H)***/ ++#define IFX_BCU_CON ((volatile u32*)(0x0010 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_CON ((volatile u32*)(0x0010 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_STARVATION_MASK (0xFF << 24) ++#define IFX_BCU_STARVATION_SHIFT 24 ++#define IFX_BCU_TOUT_MASK 0xFFFF ++#define IFX_BCU_CON_SPC(value) (((( 1 << 8) - 1) & (value)) << 24) ++#define IFX_BCU_CON_SPE (1 << 19) ++#define IFX_BCU_CON_PSE (1 << 18) ++#define IFX_BCU_CON_DBG (1 << 16) ++#define IFX_BCU_CON_TOUT(value) (((( 1 << 16) - 1) & (value)) << 0) ++ ++/***BCU Error Control Capture Register (0020H)***/ ++#define IFX_BCU_ECON ((volatile u32*)(0x0020 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_ECON ((volatile u32*)(0x0020 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_ECON_TAG(value) (((( 1 << 4) - 1) & (value)) << 24) ++#define IFX_BCU_ECON_RDN (1 << 23) ++#define IFX_BCU_ECON_WRN (1 << 22) ++#define IFX_BCU_ECON_SVM (1 << 21) ++#define IFX_BCU_ECON_ACK(value) (((( 1 << 2) - 1) & (value)) << 19) ++#define IFX_BCU_ECON_ABT (1 << 18) ++#define IFX_BCU_ECON_RDY (1 << 17) ++#define IFX_BCU_ECON_TOUT (1 << 16) ++#define IFX_BCU_ECON_ERRCNT(value) (((( 1 << 16) - 1) & (value)) << 0) ++#define IFX_BCU_ECON_OPC(value) (((( 1 << 4) - 1) & (value)) << 28) ++ ++/***BCU Error Address Capture Register (0024 H)***/ ++#define IFX_BCU_EADD ((volatile u32*)(0x0024 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_EADD ((volatile u32*)(0x0024 + IFX_SLAVE_BCU_BASE_ADDR)) ++ ++/***BCU Error Data Capture Register (0028H)***/ ++#define IFX_BCU_EDAT ((volatile u32*)(0x0028 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_EDAT ((volatile u32*)(0x0028 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_IRNICR ((volatile u32*)(0x00F8 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_IRNICR ((volatile u32*)(0x00F8 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_IRNCR ((volatile u32*)(0x00FC + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_IRNCR ((volatile u32*)(0x00FC + IFX_SLAVE_BCU_BASE_ADDR)) ++ ++ ++ ++/***********************************************************************/ ++/* Module : MEI register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_MEI_SPACE_ACCESS (KSEG1 | 0x1E116000) ++#define IFX_DFE_LDST_BASE_ADDR (KSEG1 | 0x1EF00000) ++ ++/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/ ++#define IFX_MEI_DATA_XFR ((volatile u32*)(0x0000 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_VERSION ((volatile u32*)(0x0004 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_ARC_GP_STAT ((volatile u32*)(0x0008 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_DATA_XFR_STAT ((volatile u32*)(0x000C + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XFR_ADDR ((volatile u32*)(0x0010 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_MAX_WAIT ((volatile u32*)(0x0014 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_TO_ARC_INT ((volatile u32*)(0x0018 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_ARC_TO_MEI_INT ((volatile u32*)(0x001C + IFX_MEI_SPACE_ACCESS)) ++#define IFX_ARC_TO_MEI_INT_MASK ((volatile u32*)(0x0020 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_DEBUG_WAD ((volatile u32*)(0x0024 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_DEBUG_RAD ((volatile u32*)(0x0028 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_DEBUG_DATA ((volatile u32*)(0x002C + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_DEBUG_DEC ((volatile u32*)(0x0030 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_CONFIG ((volatile u32*)(0x0034 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_RST_CONTROL ((volatile u32*)(0x0038 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_DBG_MASTER ((volatile u32*)(0x003C + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_CLK_CONTROL ((volatile u32*)(0x0040 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_BIST_CONTROL ((volatile u32*)(0x0044 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_BIST_STAT ((volatile u32*)(0x0048 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XDATA_BASE_SH ((volatile u32*)(0x004c + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XDATA_BASE ((volatile u32*)(0x0050 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR_BASE ((volatile u32*)(0x0054 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR0 ((volatile u32*)(0x0054 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR1 ((volatile u32*)(0x0058 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR2 ((volatile u32*)(0x005C + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR3 ((volatile u32*)(0x0060 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR4 ((volatile u32*)(0x0064 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR5 ((volatile u32*)(0x0068 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR6 ((volatile u32*)(0x006C + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR7 ((volatile u32*)(0x0070 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR8 ((volatile u32*)(0x0074 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR9 ((volatile u32*)(0x0078 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR10 ((volatile u32*)(0x007C + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR11 ((volatile u32*)(0x0080 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR12 ((volatile u32*)(0x0084 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR13 ((volatile u32*)(0x0088 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR14 ((volatile u32*)(0x008C + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR15 ((volatile u32*)(0x0090 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR16 ((volatile u32*)(0x0094 + IFX_MEI_SPACE_ACCESS)) ++ ++ ++/***********************************************************************/ ++/* Module : GPIO register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_GPIO (KSEG1 | 0x1E100B00) ++ ++#define IFX_GPIO_Pn_BASE(n) (IFX_GPIO + 0x0010 + 0x0030 * (n)) // only valid for first 3 ports (0-2) ++ ++/***Port 0 Data Output Register (0010H)***/ ++#define IFX_GPIO_P0_OUT ((volatile u32 *)(IFX_GPIO + 0x0010)) ++/***Port 1 Data Output Register (0040H)***/ ++#define IFX_GPIO_P1_OUT ((volatile u32 *)(IFX_GPIO + 0x0040)) ++/***Port 2 Data Output Register (0070H)***/ ++#define IFX_GPIO_P2_OUT ((volatile u32 *)(IFX_GPIO + 0x0070)) ++/***Port 3 Data Output Register (00A0H)***/ ++#define IFX_GPIO_P3_OUT ((volatile u32 *)(IFX_GPIO + 0x00A0)) ++/***Port 0 Data Input Register (0014H)***/ ++#define IFX_GPIO_P0_IN ((volatile u32 *)(IFX_GPIO + 0x0014)) ++/***Port 1 Data Input Register (0044H)***/ ++#define IFX_GPIO_P1_IN ((volatile u32 *)(IFX_GPIO + 0x0044)) ++/***Port 2 Data Input Register (0074H)***/ ++#define IFX_GPIO_P2_IN ((volatile u32 *)(IFX_GPIO + 0x0074)) ++/***Port 3 Data Input Register (00A4H)***/ ++#define IFX_GPIO_P3_IN ((volatile u32 *)(IFX_GPIO + 0x00A4)) ++/***Port 0 Direction Register (0018H)***/ ++#define IFX_GPIO_P0_DIR ((volatile u32 *)(IFX_GPIO + 0x0018)) ++/***Port 1 Direction Register (0048H)***/ ++#define IFX_GPIO_P1_DIR ((volatile u32 *)(IFX_GPIO + 0x0048)) ++/***Port 2 Direction Register (0078H)***/ ++#define IFX_GPIO_P2_DIR ((volatile u32 *)(IFX_GPIO + 0x0078)) ++/***Port 3 Direction Register (0048H)***/ ++#define IFX_GPIO_P3_DIR ((volatile u32 *)(IFX_GPIO + 0x00A8)) ++/***Port 0 Alternate Function Select Register 0 (001C H) ***/ ++#define IFX_GPIO_P0_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x001C)) ++/***Port 1 Alternate Function Select Register 0 (004C H) ***/ ++#define IFX_GPIO_P1_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x004C)) ++/***Port 2 Alternate Function Select Register 0 (007C H) ***/ ++#define IFX_GPIO_P2_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x007C)) ++/***Port 3 Alternate Function Select Register 0 (00AC H) ***/ ++#define IFX_GPIO_P3_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x00AC)) ++/***Port 0 Alternate Function Select Register 1 (0020 H) ***/ ++#define IFX_GPIO_P0_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0020)) ++/***Port 1 Alternate Function Select Register 0 (0050 H) ***/ ++#define IFX_GPIO_P1_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0050)) ++/***Port 2 Alternate Function Select Register 0 (0080 H) ***/ ++#define IFX_GPIO_P2_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0080)) ++/***Port 3 Alternate Function Select Register 0 (0064 H) ***/ ++#define IFX_GPIO_P3_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0064)) ++/***Port 0 Open Drain Control Register (0024H)***/ ++#define IFX_GPIO_P0_OD ((volatile u32 *)(IFX_GPIO + 0x0024)) ++/***Port 1 Open Drain Control Register (0054H)***/ ++#define IFX_GPIO_P1_OD ((volatile u32 *)(IFX_GPIO + 0x0054)) ++/***Port 2 Open Drain Control Register (0084H)***/ ++#define IFX_GPIO_P2_OD ((volatile u32 *)(IFX_GPIO + 0x0084)) ++/***Port 3 Open Drain Control Register (0034H)***/ ++#define IFX_GPIO_P3_OD ((volatile u32 *)(IFX_GPIO + 0x0034)) ++/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/ ++#define IFX_GPIO_P0_STOFF ((volatile u32 *)(IFX_GPIO + 0x0028)) ++/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/ ++#define IFX_GPIO_P1_STOFF ((volatile u32 *)(IFX_GPIO + 0x0058)) ++/***Port 2 Input Schmitt-Trigger Off Register (0088 H) ***/ ++#define IFX_GPIO_P2_STOFF ((volatile u32 *)(IFX_GPIO + 0x0088)) ++/***Port 3 Input Schmitt-Trigger Off Register (0094 H) ***/ ++// not available ++/***Port 0 Pull Up/Pull Down Select Register (002C H)***/ ++#define IFX_GPIO_P0_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x002C)) ++/***Port 1 Pull Up/Pull Down Select Register (005C H)***/ ++#define IFX_GPIO_P1_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x005C)) ++/***Port 2 Pull Up/Pull Down Select Register (008C H)***/ ++#define IFX_GPIO_P2_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x008C)) ++/***Port 3 Pull Up/Pull Down Select Register (0038 H)***/ ++#define IFX_GPIO_P3_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x0038)) ++/***Port 0 Pull Up Device Enable Register (0030 H)***/ ++#define IFX_GPIO_P0_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0030)) ++/***Port 1 Pull Up Device Enable Register (0060 H)***/ ++#define IFX_GPIO_P1_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0060)) ++/***Port 2 Pull Up Device Enable Register (0090 H)***/ ++#define IFX_GPIO_P2_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0090)) ++/***Port 3 Pull Up Device Enable Register (003c H)***/ ++#define IFX_GPIO_P3_PUDEN ((volatile u32 *)(IFX_GPIO + 0x003C)) ++ ++ ++ ++/***********************************************************************/ ++/* Module : CGU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_CGU (KSEG1 | 0x1F103000) ++ ++/***CGU Clock PLL0 ***/ ++#define IFX_CGU_PLL0_CFG ((volatile u32*)(IFX_CGU + 0x0004)) ++/***CGU Clock PLL1 ***/ ++#define IFX_CGU_PLL1_CFG ((volatile u32*)(IFX_CGU + 0x0008)) ++/***CGU Clock PLL2 ***/ ++#define IFX_CGU_PLL2_CFG ((volatile u32*)(IFX_CGU + 0x000C)) ++/***CGU Clock SYS Mux Register***/ ++#define IFX_CGU_SYS ((volatile u32*)(IFX_CGU + 0x0010)) ++ ++#define IFX_CGU_SYS_SEL 0x00000018 ++#define IFX_CGU_SYS_SEL_S 3 ++#define IFX_CGU_SYS_SEL_333 0 ++#define IFX_CGU_SYS_SEL_393 2 ++ ++/**Update CGU Register***/ ++#define IFX_CGU_UPDATE ((volatile u32*)(IFX_CGU + 0x0014)) ++/***CGU Interface Clock Register***/ ++#define IFX_CGU_IF_CLK ((volatile u32*)(IFX_CGU + 0x0018)) ++/***CGU SDRAM Memory Control Register***/ ++#define IFX_CGU_SMD ((volatile u32*)(IFX_CGU + 0x0020)) ++/***CGU CT Status Register 1***/ ++#define IFX_CGU_CT1SR ((volatile u32*)(IFX_CGU + 0x0028)) ++/***CGU CT Kval Register***/ ++#define IFX_CGU_CT_KVAL ((volatile u32*)(IFX_CGU + 0x002C)) ++/***CGU PCM Control Register***/ ++#define IFX_CGU_PCMCR ((volatile u32*)(IFX_CGU + 0x0030)) ++/***CGU PCI Clock Control Register***/ ++#define IFX_CGU_PCI_CR ((volatile u32*)(IFX_CGU + 0x0034)) ++ ++#define IFX_PCI_CLK_SHIFT 20 ++#define IFX_PCI_CLK_MASK (0x1F << IFX_PCI_CLK_SHIFT) ++#define IFX_PCI_33MHZ (0xe << IFX_PCI_CLK_SHIFT) ++#define IFX_PCI_60MHZ (0x7 << IFX_PCI_CLK_SHIFT) ++#define IFX_PCI_INTERNAL_CLK_SRC 0x00010000 /* Internal means output */ ++ ++#define IFX_PCI_CLK_FROM_CGU 0x80000000 ++#define IFX_PCI_CLK_RESET_FROM_CGU 0x40000000 ++#define IFX_PCI_DELAY_SHIFT 21 ++#define IFX_PCI_DELAY_MASK (0x7 << IFX_PCI_DELAY_SHIFT) ++ ++/***********************************************************************/ ++/* Module : MCD register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_MCD (KSEG1 | 0x1F106000) ++ ++/***Manufacturer Identification Register***/ ++#define IFX_MCD_MANID ((volatile u32*)(IFX_MCD + 0x0024)) ++#define IFX_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5) ++ ++/***Chip Identification Register***/ ++#define IFX_MCD_CHIPID ((volatile u32*)(IFX_MCD + 0x0028)) ++#define IFX_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) ++#define IFX_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) ++#define IFX_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1)) ++#define IFX_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12) ++#define IFX_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1)) ++#define IFX_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1) ++ ++#define IFX_CHIPID_STANDARD 0x00EB ++#define IFX_CHIPID_YANGTSE 0x00ED ++ ++/***Redesign Tracing Identification Register***/ ++#define IFX_MCD_RTID ((volatile u32*)(IFX_MCD + 0x002C)) ++#define IFX_MCD_RTID_LC (1 << 15) ++#define IFX_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0) ++ ++ ++ ++/***********************************************************************/ ++/* Module : EBU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_EBU (KSEG1 | 0x1E105300) ++ ++/***EBU Clock Control Register***/ ++#define IFX_EBU_CLC ((volatile u32*)(IFX_EBU + 0x0000)) ++#define IFX_EBU_CLC_DISS (1 << 1) ++#define IFX_EBU_CLC_DISR (1 << 0) ++ ++#define IFX_EBU_ID ((volatile u32*)(IFX_EBU + 0x0008)) ++ ++/***EBU Global Control Register***/ ++#define IFX_EBU_CON ((volatile u32*)(IFX_EBU + 0x0010)) ++#define IFX_EBU_CON_DTACS(value) (((( 1 << 3) - 1) & (value)) << 20) ++#define IFX_EBU_CON_DTARW(value) (((( 1 << 3) - 1) & (value)) << 16) ++#define IFX_EBU_CON_TOUTC(value) (((( 1 << 8) - 1) & (value)) << 8) ++#define IFX_EBU_CON_ARBMODE(value) (((( 1 << 2) - 1) & (value)) << 6) ++#define IFX_EBU_CON_ARBSYNC (1 << 5) ++ ++/***EBU Address Select Register 0***/ ++#define IFX_EBU_ADDSEL0 ((volatile u32*)(IFX_EBU + 0x0020)) ++#define IFX_EBU_ADDSEL0_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) ++#define IFX_EBU_ADDSEL0_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_EBU_ADDSEL0_MIRRORE (1 << 1) ++#define IFX_EBU_ADDSEL0_REGEN (1 << 0) ++ ++/***EBU Address Select Register 1***/ ++#define IFX_EBU_ADDSEL1 ((volatile u32*)(IFX_EBU + 0x0024)) ++#define IFX_EBU_ADDSEL1_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) ++#define IFX_EBU_ADDSEL1_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_EBU_ADDSEL1_MIRRORE (1 << 1) ++#define IFX_EBU_ADDSEL1_REGEN (1 << 0) ++ ++/***EBU Address Select Register 2***/ ++#define IFX_EBU_ADDSEL2 ((volatile u32*)(IFX_EBU + 0x0028)) ++#define IFX_EBU_ADDSEL2_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) ++#define IFX_EBU_ADDSEL2_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_EBU_ADDSEL2_MIRRORE (1 << 1) ++#define IFX_EBU_ADDSEL2_REGEN (1 << 0) ++ ++/***EBU Address Select Register 3***/ ++#define IFX_EBU_ADDSEL3 ((volatile u32*)(IFX_EBU + 0x002C)) ++#define IFX_EBU_ADDSEL3_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) ++#define IFX_EBU_ADDSEL3_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_EBU_ADDSEL3_MIRRORE (1 << 1) ++#define IFX_EBU_ADDSEL3_REGEN (1 << 0) ++ ++/***EBU Bus Configuration Register 0***/ ++#define IFX_EBU_BUSCON0 ((volatile u32*)(IFX_EBU + 0x0060)) ++ ++#define IFX_EBU_BUSCON0_CMULT 0x00000003 ++#define IFX_EBU_BUSCON0_CMULT_S 0 ++enum { ++ IFX_EBU_BUSCON0_CMULT1 = 0, ++ IFX_EBU_BUSCON0_CMULT4, ++ IFX_EBU_BUSCON0_CMULT8, ++ IFX_EBU_BUSCON0_CMULT16, /* Default after reset */ ++}; ++ ++#define IFX_EBU_BUSCON0_RECOVC 0x00000000c ++#define IFX_EBU_BUSCON0_RECOVC_S 2 ++enum { ++ IFX_EBU_BUSCON0_RECOVC0 = 0, ++ IFX_EBU_BUSCON0_RECOVC1, ++ IFX_EBU_BUSCON0_RECOVC2, ++ IFX_EBU_BUSCON0_RECOVC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON0_HOLDC 0x00000030 ++#define IFX_EBU_BUSCON0_HOLDC_S 4 ++enum { ++ IFX_EBU_BUSCON0_HOLDC0 = 0, ++ IFX_EBU_BUSCON0_HOLDC1, ++ IFX_EBU_BUSCON0_HOLDC2, ++ IFX_EBU_BUSCON0_HOLDC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON0_WAITRDC 0x000000c0 ++#define IFX_EBU_BUSCON0_WAITRDC_S 6 ++enum { ++ IFX_EBU_BUSCON0_WAITRDC0 = 0, ++ IFX_EBU_BUSCON0_WAITRDC1, ++ IFX_EBU_BUSCON0_WAITRDC2, ++ IFX_EBU_BUSCON0_WAITRDC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON0_WAITWRC 0x00000700 ++#define IFX_EBU_BUSCON0_WAITWRC_S 8 ++enum { ++ IFX_EBU_BUSCON0_WAITWRC0 = 0, ++ IFX_EBU_BUSCON0_WAITWRC1, ++ IFX_EBU_BUSCON0_WAITWRC2, ++ IFX_EBU_BUSCON0_WAITWRC3, ++ IFX_EBU_BUSCON0_WAITWRC4, ++ IFX_EBU_BUSCON0_WAITWRC5, ++ IFX_EBU_BUSCON0_WAITWRC6, ++ IFX_EBU_BUSCON0_WAITWRC7, /* Default */ ++}; ++ ++#define IFX_EBU_BUSCON0_BCGEN 0x00003000 ++#define IFX_EBU_BUSCON0_BCGEN_S 12 ++enum { ++ IFX_EBU_BUSCON0_BCGEN_CS = 0, ++ IFX_EBU_BUSCON0_BCGEN_INTEL, /* Default */ ++ IFX_EBU_BUSCON0_BCGEN_MOTOROLA, ++ IFX_EBU_BUSCON0_BCGEN_RES, ++}; ++ ++#define IFX_EBU_BUSCON0_ALEC 0x0000c000 ++#define IFX_EBU_BUSCON0_ALEC_S 14 ++enum { ++ IFX_EBU_BUSCON0_ALEC0 = 0, ++ IFX_EBU_BUSCON0_ALEC1, ++ IFX_EBU_BUSCON0_ALEC2, ++ IFX_EBU_BUSCON0_ALEC3, /* Default */ ++}; ++ ++#define IFX_EBU_BUSCON0_XDM 0x00030000 ++#define IFX_EBU_BUSCON0_XDM_S 16 ++enum { ++ IFX_EBU_BUSCON0_XDM8 = 0, ++ IFX_EBU_BUSCON0_XDM16, /* Default */ ++}; ++ ++#define IFX_EBU_BUSCON0_VN_EN 0x00040000 ++ ++#define IFX_EBU_BUSCON0_WAITINV_HI 0x00080000 /* low by default */ ++ ++#define IFX_EBU_BUSCON0_WAIT 0x00300000 ++#define IFX_EBU_BUSCON0_WAIT_S 20 ++enum { ++ IFX_EBU_BUSCON0_WAIT_DISABLE = 0, ++ IFX_EBU_BUSCON0_WAIT_ASYNC, ++ IFX_EBU_BUSCON0_WAIT_SYNC, ++}; ++#define IFX_EBU_BUSCON0_SETUP_EN 0x00400000 /* Disable by default */ ++ ++#define IFX_EBU_BUSCON0_AGEN 0x07000000 ++#define IFX_EBU_BUSCON0_AGEN_S 24 ++enum { ++ IFX_EBU_BUSCON0_AGEN_DEMUX = 0, /* Default */ ++ IFX_EBU_BUSCON0_AGEN_RES, ++ IFX_EBU_BUSCON0_AGEN_MUX, ++}; ++ ++#define IFX_EBU_BUSCON0_PG_EN 0x20000000 ++#define IFX_EBU_BUSCON0_ADSWP 0x40000000 /* Disable by default */ ++#define IFX_EBU_BUSCON0_WRDIS 0x80000000 /* Disable by default */ ++ ++/***EBU Bus Configuration Register 1***/ ++#define IFX_EBU_BUSCON1 ((volatile u32*)(IFX_EBU + 0x0064)) ++#define IFX_EBU_BUSCON1_CMULT 0x00000003 ++#define IFX_EBU_BUSCON1_CMULT_S 0 ++enum { ++ IFX_EBU_BUSCON1_CMULT1 = 0, ++ IFX_EBU_BUSCON1_CMULT4, ++ IFX_EBU_BUSCON1_CMULT8, ++ IFX_EBU_BUSCON1_CMULT16, /* Default after reset */ ++}; ++ ++#define IFX_EBU_BUSCON1_RECOVC 0x00000000c ++#define IFX_EBU_BUSCON1_RECOVC_S 2 ++enum { ++ IFX_EBU_BUSCON1_RECOVC0 = 0, ++ IFX_EBU_BUSCON1_RECOVC1, ++ IFX_EBU_BUSCON1_RECOVC2, ++ IFX_EBU_BUSCON1_RECOVC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON1_HOLDC 0x00000030 ++#define IFX_EBU_BUSCON1_HOLDC_S 4 ++enum { ++ IFX_EBU_BUSCON1_HOLDC0 = 0, ++ IFX_EBU_BUSCON1_HOLDC1, ++ IFX_EBU_BUSCON1_HOLDC2, ++ IFX_EBU_BUSCON1_HOLDC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON1_WAITRDC 0x000000c0 ++#define IFX_EBU_BUSCON1_WAITRDC_S 6 ++enum { ++ IFX_EBU_BUSCON1_WAITRDC0 = 0, ++ IFX_EBU_BUSCON1_WAITRDC1, ++ IFX_EBU_BUSCON1_WAITRDC2, ++ IFX_EBU_BUSCON1_WAITRDC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON1_WAITWRC 0x00000700 ++#define IFX_EBU_BUSCON1_WAITWRC_S 8 ++enum { ++ IFX_EBU_BUSCON1_WAITWRC0 = 0, ++ IFX_EBU_BUSCON1_WAITWRC1, ++ IFX_EBU_BUSCON1_WAITWRC2, ++ IFX_EBU_BUSCON1_WAITWRC3, ++ IFX_EBU_BUSCON1_WAITWRC4, ++ IFX_EBU_BUSCON1_WAITWRC5, ++ IFX_EBU_BUSCON1_WAITWRC6, ++ IFX_EBU_BUSCON1_WAITWRC7, /* Default */ ++}; ++#define IFX_EBU_BUSCON1_BCGEN 0x00003000 ++#define IFX_EBU_BUSCON1_BCGEN_S 12 ++enum { ++ IFX_EBU_BUSCON1_BCGEN_CS = 0, ++ IFX_EBU_BUSCON1_BCGEN_INTEL, /* Default */ ++ IFX_EBU_BUSCON1_BCGEN_MOTOROLA, ++ IFX_EBU_BUSCON1_BCGEN_RES, ++}; ++#define IFX_EBU_BUSCON1_ALEC 0x0000c000 ++#define IFX_EBU_BUSCON1_ALEC_S 14 ++enum { ++ IFX_EBU_BUSCON1_ALEC0 = 0, ++ IFX_EBU_BUSCON1_ALEC1, ++ IFX_EBU_BUSCON1_ALEC2, ++ IFX_EBU_BUSCON1_ALEC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON1_SETUP (1 << 22) ++#define IFX_EBU_BUSCON1_WRDIS (1 << 31) ++//#define IFX_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) ++//#define IFX_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) ++#define IFX_EBU_BUSCON1_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) ++#define IFX_EBU_BUSCON1_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) ++#define IFX_EBU_BUSCON1_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) ++#define IFX_EBU_BUSCON1_WAITINV (1 << 19) ++#define IFX_EBU_BUSCON1_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) ++//#define IFX_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) ++//#define IFX_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) ++//#define IFX_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) ++//#define IFX_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) ++//#define IFX_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) ++ ++/***EBU Bus Configuration Register 2***/ ++#define IFX_EBU_BUSCON2 ((volatile u32*)(IFX_EBU + 0x0068)) ++#define IFX_EBU_BUSCON2_WRDIS (1 << 31) ++#define IFX_EBU_BUSCON2_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) ++#define IFX_EBU_BUSCON2_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) ++#define IFX_EBU_BUSCON2_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) ++#define IFX_EBU_BUSCON2_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) ++#define IFX_EBU_BUSCON2_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) ++#define IFX_EBU_BUSCON2_WAITINV (1 << 19) ++#define IFX_EBU_BUSCON2_SETUP (1 << 18) ++#define IFX_EBU_BUSCON2_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) ++#define IFX_EBU_BUSCON2_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) ++#define IFX_EBU_BUSCON2_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) ++#define IFX_EBU_BUSCON2_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) ++#define IFX_EBU_BUSCON2_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) ++#define IFX_EBU_BUSCON2_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) ++ ++/***EBU Bus Configuration Register 2***/ ++#define IFX_EBU_BUSCON3 ((volatile u32*)(IFX_EBU + 0x006C)) ++#define IFX_EBU_BUSCON3_WRDIS (1 << 31) ++#define IFX_EBU_BUSCON3_ADSWP(value) (1 << 30) ++#define IFX_EBU_BUSCON3_PG_EN(value) (1 << 29) ++#define IFX_EBU_BUSCON3_AGEN(value) (((( 1 << 3) - 1) & (value)) << 24) ++#define IFX_EBU_BUSCON3_SETUP (1 << 22) ++#define IFX_EBU_BUSCON3_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) ++#define IFX_EBU_BUSCON3_WAITINV (1 << 19) ++#define IFX_EBU_BUSCON3_VN_EN (1 << 18) ++#define IFX_EBU_BUSCON3_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) ++#define IFX_EBU_BUSCON3_ALEC(value) (((( 1 << 2) - 1) & (value)) << 14) ++#define IFX_EBU_BUSCON3_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 12) ++#define IFX_EBU_BUSCON3_WAITWDC(value) (((( 1 << 4) - 1) & (value)) << 8) ++#define IFX_EBU_BUSCON3_WAITRRC(value) (((( 1 << 2) - 1) & (value)) << 6) ++#define IFX_EBU_BUSCON3_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) ++#define IFX_EBU_BUSCON3_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) ++#define IFX_EBU_BUSCON3_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) ++ ++/* PC Card Control Register */ ++#define IFX_EBU_PCC_CON ((volatile u32*)(IFX_EBU+ 0x0090)) ++#define IFX_EBU_PCC_CON_PCCARD_ON 0x00000001 ++#define IFX_EBU_PCC_CON_IREQ_RISING_EDGE 0x00000002 ++#define IFX_EBU_PCC_CON_IREQ_FALLING_EDGE 0x00000004 ++#define IFX_EBU_PCC_CON_IREQ_BOTH_EDGE 0x00000006 ++#define IFX_EBU_PCC_CON_IREQ_DIS 0x00000008 ++#define IFX_EBU_PCC_CON_IREQ_HIGH_LEVEL_DETECT 0x0000000A ++#define IFX_EBU_PCC_CON_IREQ_LOW_LEVEL_DETECT 0x0000000C ++ ++#define IFX_EBU_PCC_STAT ((volatile u32*)(IFX_EBU+ 0x0094)) ++#define IFX_EBU_PCC_ISTAT ((volatile u32*)(IFX_EBU+ 0x00A0)) ++#define IFX_EBU_PCC_IEN ((volatile u32*)(IFX_EBU+ 0x00A4)) ++#define IFX_EBU_PCC_IEN_PCI_EN 0x00000010 ++ ++#define IFX_EBU_PCC_INT_OUT ((volatile u32*)(IFX_EBU+ 0x00A8)) ++#define IFX_EBU_PCC_IRS ((volatile u32*)(IFX_EBU+ 0x00AC)) ++ ++#define IFX_EBU_NAND_CON (volatile u32*)(IFX_EBU + 0xB0) ++#define IFX_EBU_NAND_CON_NANDM (1<<0) ++#define IFX_EBU_NAND_CON_NANDM_S 0 ++enum { ++ IFX_EBU_NAND_CON_NANDM_DISABLE = 0,/* Default after reset */ ++ IFX_EBU_NAND_CON_NANDM_ENABLE, ++}; ++ ++#define IFX_EBU_NAND_CON_CSMUX_E (1<<1) ++#define IFX_EBU_NAND_CON_CSMUX_E_S 1 ++enum { ++ IFX_EBU_NAND_CON_CSMUX_E_DISABLE = 0,/* Default after reset */ ++ IFX_EBU_NAND_CON_CSMUX_E_ENABLE, ++}; ++ ++#define IFX_EBU_NAND_CON_CS_P (1<<4) ++#define IFX_EBU_NAND_CON_CS_P_S 4 ++enum { ++ IFX_EBU_NAND_CON_CS_P_HIGH = 0, ++ IFX_EBU_NAND_CON_CS_P_LOW, /* Default after reset */ ++}; ++ ++#define IFX_EBU_NAND_CON_SE_P (1<<5) ++#define IFX_EBU_NAND_CON_SE_P_S 5 ++enum { ++ IFX_EBU_NAND_CON_SE_P_HIGH = 0, ++ IFX_EBU_NAND_CON_SE_P_LOW, /* Default after reset */ ++}; ++ ++#define IFX_EBU_NAND_CON_WP_P (1<<6) ++#define IFX_EBU_NAND_CON_WP_P_S 6 ++enum { ++ IFX_EBU_NAND_CON_WP_P_HIGH = 0, ++ IFX_EBU_NAND_CON_WP_P_LOW, /* Default after reset */ ++}; ++ ++#define IFX_EBU_NAND_CON_PRE_P (1<<7) ++#define IFX_EBU_NAND_CON_PRE_P_S 7 ++enum { ++ IFX_EBU_NAND_CON_PRE_P_HIGH = 0, ++ IFX_EBU_NAND_CON_PRE_P_LOW, /* Default after reset */ ++}; ++ ++#define IFX_EBU_NAND_CON_IN_CS (3<<8) ++#define IFX_EBU_NAND_CON_IN_CS_S 8 ++enum { ++ IFX_EBU_NAND_CON_IN_CS0 = 0, /* Default after reset */ ++ IFX_EBU_NAND_CON_IN_CS1, ++}; ++ ++#define IFX_EBU_NAND_CON_OUT_CS (3<<10) ++#define IFX_EBU_NAND_CON_OUT_CS_S 10 ++enum { ++ IFX_EBU_NAND_CON_OUT_CS0 = 0, /* Default after reset */ ++ IFX_EBU_NAND_CON_OUT_CS1, ++}; ++#define IFX_EBU_NAND_WAIT (volatile u32*)(IFX_EBU + 0xB4) ++#define IFX_EBU_NAND_WAIT_RD (0x1) ++#define IFX_EBU_NAND_WAIT_BY_E (1<<1) ++#define IFX_EBU_NAND_WAIT_RD_E (1<<2) ++#define IFX_EBU_NAND_WAIT_WR_C (1<<3) ++ ++#define IFX_EBU_NAND_ECC0 (volatile u32*)(IFX_EBU + 0xB8) ++#define IFX_EBU_NAND_ECC_AC (volatile u32*)(IFX_EBU + 0xBC) ++ ++ ++ ++ ++/***********************************************************************/ ++/* Module : SDRAM register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_SDRAM (KSEG1 | 0x1F800000) ++ ++/***MC Access Error Cause Register***/ ++#define IFX_SDRAM_MC_ERRCAUSE ((volatile u32*)(IFX_SDRAM + 0x0100)) ++#define IFX_SDRAM_MC_ERRCAUSE_ERR (1 << 31) ++#define IFX_SDRAM_MC_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16) ++#define IFX_SDRAM_MC_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_ERRCAUSE_Res(value) (((( 1 << NaN) - 1) & (value)) << NaN) ++ ++/***MC Access Error Address Register***/ ++#define IFX_SDRAM_MC_ERRADDR ((volatile u32*)(IFX_SDRAM + 0x0108)) ++ ++/***MC I/O General Purpose Register***/ ++#define IFX_SDRAM_MC_IOGP ((volatile u32*)(IFX_SDRAM + 0x0800)) ++#define IFX_SDRAM_MC_IOGP_GPR6(value) (((( 1 << 4) - 1) & (value)) << 28) ++#define IFX_SDRAM_MC_IOGP_GPR5(value) (((( 1 << 4) - 1) & (value)) << 24) ++#define IFX_SDRAM_MC_IOGP_GPR4(value) (((( 1 << 4) - 1) & (value)) << 20) ++#define IFX_SDRAM_MC_IOGP_GPR3(value) (((( 1 << 4) - 1) & (value)) << 16) ++#define IFX_SDRAM_MC_IOGP_GPR2(value) (((( 1 << 4) - 1) & (value)) << 12) ++#define IFX_SDRAM_MC_IOGP_CPS (1 << 11) ++#define IFX_SDRAM_MC_IOGP_CLKDELAY(value) (((( 1 << 3) - 1) & (value)) << 8) ++#define IFX_SDRAM_MC_IOGP_CLKRAT(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_IOGP_RDDEL(value) (((( 1 << 4) - 1) & (value)) << 0) ++ ++/***MC Self Refresh Register***/ ++#define IFX_SDRAM_MC_SELFRFSH ((volatile u32*)(IFX_SDRAM + 0x0A00)) ++#define IFX_SDRAM_MC_SELFRFSH_PWDS (1 << 1) ++#define IFX_SDRAM_MC_SELFRFSH_PWD (1 << 0) ++#define IFX_SDRAM_MC_SELFRFSH_Res(value) (((( 1 << 30) - 1) & (value)) << 2) ++ ++/***MC Enable Register***/ ++#define IFX_SDRAM_MC_CTRLENA ((volatile u32*)(IFX_SDRAM + 0x1000)) ++#define IFX_SDRAM_MC_CTRLENA_ENA (1 << 0) ++#define IFX_SDRAM_MC_CTRLENA_Res(value) (((( 1 << 31) - 1) & (value)) << 1) ++ ++/***MC Mode Register Setup Code***/ ++#define IFX_SDRAM_MC_MRSCODE ((volatile u32*)(IFX_SDRAM + 0x1008)) ++#define IFX_SDRAM_MC_MRSCODE_UMC(value) (((( 1 << 5) - 1) & (value)) << 7) ++#define IFX_SDRAM_MC_MRSCODE_CL(value) (((( 1 << 3) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_MRSCODE_WT (1 << 3) ++#define IFX_SDRAM_MC_MRSCODE_BL(value) (((( 1 << 3) - 1) & (value)) << 0) ++ ++/***MC Configuration Data-word Width Register***/ ++#define IFX_SDRAM_MC_CFGDW ((volatile u32*)(IFX_SDRAM + 0x1010)) ++#define IFX_SDRAM_MC_CFGDW_DW(value) (((( 1 << 4) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_CFGDW_Res(value) (((( 1 << 28) - 1) & (value)) << 4) ++ ++/***MC Configuration Physical Bank 0 Register***/ ++#define IFX_SDRAM_MC_CFGPB0 ((volatile u32*)(IFX_SDRAM + 0x1018)) ++#define IFX_SDRAM_MC_CFGPB0_MCSEN0(value) (((( 1 << 4) - 1) & (value)) << 12) ++#define IFX_SDRAM_MC_CFGPB0_BANKN0(value) (((( 1 << 4) - 1) & (value)) << 8) ++#define IFX_SDRAM_MC_CFGPB0_ROWW0(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_CFGPB0_COLW0(value) (((( 1 << 4) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_CFGPB0_Res(value) (((( 1 << 16) - 1) & (value)) << 16) ++ ++/***MC Latency Register***/ ++#define IFX_SDRAM_MC_LATENCY ((volatile u32*)(IFX_SDRAM + 0x1038)) ++#define IFX_SDRAM_MC_LATENCY_TRP(value) (((( 1 << 4) - 1) & (value)) << 16) ++#define IFX_SDRAM_MC_LATENCY_TRAS(value) (((( 1 << 4) - 1) & (value)) << 12) ++#define IFX_SDRAM_MC_LATENCY_TRCD(value) (((( 1 << 4) - 1) & (value)) << 8) ++#define IFX_SDRAM_MC_LATENCY_TDPL(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_LATENCY_TDAL(value) (((( 1 << 4) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_LATENCY_Res(value) (((( 1 << 12) - 1) & (value)) << 20) ++ ++/***MC Refresh Cycle Time Register***/ ++#define IFX_SDRAM_MC_TREFRESH ((volatile u32*)(IFX_SDRAM + 0x1040)) ++#define IFX_SDRAM_MC_TREFRESH_TREF(value) (((( 1 << 13) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_TREFRESH_Res(value) (((( 1 << 19) - 1) & (value)) << 13) ++ ++/***MC Status Register***/ ++#define IFX_SDRAM_MC_STAT ((volatile u32*)(IFX_SDRAM + 0x0070)) ++ ++/***MC DDR Control Register 00***/ ++#define IFX_DDR_MC_DC00 ((volatile u32*)(IFX_SDRAM + 0x1000)) ++/***MC DDR Control Register 03***/ ++#define IFX_DDR_MC_DC03 ((volatile u32*)(IFX_SDRAM + 0x1030)) ++/***MC DDR Control Register 17***/ ++#define IFX_DDR_MC_DC17 ((volatile u32*)(IFX_SDRAM + 0x1110)) ++ ++ ++/***********************************************************************/ ++/* Module : ASC0 register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_ASC0 (KSEG1 | 0x1E100400) ++ ++#define IFX_ASC0_TBUF ((volatile u32*)(IFX_ASC0 + 0x0020)) ++#define IFX_ASC0_RBUF ((volatile u32*)(IFX_ASC0 + 0x0024)) ++#define IFX_ASC0_FSTAT ((volatile u32*)(IFX_ASC0 + 0x0048)) ++ ++ ++ ++/***********************************************************************/ ++/* Module : ASC1 register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_ASC1 (KSEG1 | 0x1E100C00) ++ ++#define IFX_ASC1_TBUF ((volatile u32*)(IFX_ASC1 + 0x0020)) ++#define IFX_ASC1_RBUF ((volatile u32*)(IFX_ASC1 + 0x0024)) ++#define IFX_ASC1_FSTAT ((volatile u32*)(IFX_ASC1 + 0x0048)) ++ ++ ++ ++/***********************************************************************/ ++/* Module : DMA register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_DMA (KSEG1 | 0x1E104100) ++ ++#define IFX_DMA_BASE IFX_DMA ++#define IFX_DMA_CLC (volatile u32*)(IFX_DMA_BASE + 0x00) ++#define IFX_DMA_ID (volatile u32*)(IFX_DMA_BASE + 0x08) ++#define IFX_DMA_CTRL (volatile u32*)(IFX_DMA_BASE + 0x10) ++#define IFX_DMA_CPOLL (volatile u32*)(IFX_DMA_BASE + 0x14) ++ ++#define IFX_DMA_CS(i) (volatile u32*)(IFX_DMA_BASE + 0x18 + 0x38 * (i)) ++#define IFX_DMA_CCTRL(i) (volatile u32*)(IFX_DMA_BASE + 0x1C + 0x38 * (i)) ++#define IFX_DMA_CDBA(i) (volatile u32*)(IFX_DMA_BASE + 0x20 + 0x38 * (i)) ++#define IFX_DMA_CDLEN(i) (volatile u32*)(IFX_DMA_BASE + 0x24 + 0x38 * (i)) ++#define IFX_DMA_CIS(i) (volatile u32*)(IFX_DMA_BASE + 0x28 + 0x38 * (i)) ++#define IFX_DMA_CIE(i) (volatile u32*)(IFX_DMA_BASE + 0x2C + 0x38 * (i)) ++ ++#define IFX_DMA_CGBL (volatile u32*)(IFX_DMA_BASE + 0x30) ++ ++#define IFX_DMA_PS(i) (volatile u32*)(IFX_DMA_BASE + 0x40 + 0x30 * (i)) ++#define IFX_DMA_PCTRL(i) (volatile u32*)(IFX_DMA_BASE + 0x44 + 0x30 * (i)) ++ ++#define IFX_DMA_IRNEN (volatile u32*)(IFX_DMA_BASE + 0xf4) ++#define IFX_DMA_IRNCR (volatile u32*)(IFX_DMA_BASE + 0xf8) ++#define IFX_DMA_IRNICR (volatile u32*)(IFX_DMA_BASE + 0xfc) ++ ++ ++ ++/***********************************************************************/ ++/* Module : Debug register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_Debug (KSEG1 | 0x1F106000) ++ ++/***MCD Break Bus Switch Register***/ ++#define IFX_Debug_MCD_BBS ((volatile u32*)(IFX_Debug + 0x0000)) ++#define IFX_Debug_MCD_BBS_BTP1 (1 << 19) ++#define IFX_Debug_MCD_BBS_BTP0 (1 << 18) ++#define IFX_Debug_MCD_BBS_BSP1 (1 << 17) ++#define IFX_Debug_MCD_BBS_BSP0 (1 << 16) ++#define IFX_Debug_MCD_BBS_BT5EN (1 << 15) ++#define IFX_Debug_MCD_BBS_BT4EN (1 << 14) ++#define IFX_Debug_MCD_BBS_BT5 (1 << 13) ++#define IFX_Debug_MCD_BBS_BT4 (1 << 12) ++#define IFX_Debug_MCD_BBS_BS5EN (1 << 7) ++#define IFX_Debug_MCD_BBS_BS4EN (1 << 6) ++#define IFX_Debug_MCD_BBS_BS5 (1 << 5) ++#define IFX_Debug_MCD_BBS_BS4 (1 << 4) ++ ++/***MCD Multiplexer Control Register***/ ++#define IFX_Debug_MCD_MCR ((volatile u32*)(IFX_Debug+ 0x0008)) ++#define IFX_Debug_MCD_MCR_MUX5 (1 << 4) ++#define IFX_Debug_MCD_MCR_MUX4 (1 << 3) ++#define IFX_Debug_MCD_MCR_MUX1 (1 << 0) ++ ++ ++ ++/***********************************************************************/ ++/* Module : ICU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_ICU (KSEG1 | 0x1F880200) ++ ++#define IFX_ICU_IM0_ISR ((volatile u32*)(IFX_ICU + 0x0000)) ++#define IFX_ICU_IM0_IER ((volatile u32*)(IFX_ICU + 0x0008)) ++#define IFX_ICU_IM0_IOSR ((volatile u32*)(IFX_ICU + 0x0010)) ++#define IFX_ICU_IM0_IRSR ((volatile u32*)(IFX_ICU + 0x0018)) ++#define IFX_ICU_IM0_IMR ((volatile u32*)(IFX_ICU + 0x0020)) ++ ++#define IFX_ICU_IM1_ISR ((volatile u32*)(IFX_ICU + 0x0028)) ++#define IFX_ICU_IM1_IER ((volatile u32*)(IFX_ICU + 0x0030)) ++#define IFX_ICU_IM1_IOSR ((volatile u32*)(IFX_ICU + 0x0038)) ++#define IFX_ICU_IM1_IRSR ((volatile u32*)(IFX_ICU + 0x0040)) ++#define IFX_ICU_IM1_IMR ((volatile u32*)(IFX_ICU + 0x0048)) ++ ++#define IFX_ICU_IM2_ISR ((volatile u32*)(IFX_ICU + 0x0050)) ++#define IFX_ICU_IM2_IER ((volatile u32*)(IFX_ICU + 0x0058)) ++#define IFX_ICU_IM2_IOSR ((volatile u32*)(IFX_ICU + 0x0060)) ++#define IFX_ICU_IM2_IRSR ((volatile u32*)(IFX_ICU + 0x0068)) ++#define IFX_ICU_IM2_IMR ((volatile u32*)(IFX_ICU + 0x0070)) ++ ++#define IFX_ICU_IM3_ISR ((volatile u32*)(IFX_ICU + 0x0078)) ++#define IFX_ICU_IM3_IER ((volatile u32*)(IFX_ICU + 0x0080)) ++#define IFX_ICU_IM3_IOSR ((volatile u32*)(IFX_ICU + 0x0088)) ++#define IFX_ICU_IM3_IRSR ((volatile u32*)(IFX_ICU + 0x0090)) ++#define IFX_ICU_IM3_IMR ((volatile u32*)(IFX_ICU + 0x0098)) ++ ++#define IFX_ICU_IM4_ISR ((volatile u32*)(IFX_ICU + 0x00A0)) ++#define IFX_ICU_IM4_IER ((volatile u32*)(IFX_ICU + 0x00A8)) ++#define IFX_ICU_IM4_IOSR ((volatile u32*)(IFX_ICU + 0x00B0)) ++#define IFX_ICU_IM4_IRSR ((volatile u32*)(IFX_ICU + 0x00B8)) ++#define IFX_ICU_IM4_IMR ((volatile u32*)(IFX_ICU + 0x00C0)) ++ ++/***Interrupt Vector Value Register***/ ++#define IFX_ICU_IM_VEC_5 ((volatile u32*)(IFX_ICU + 0x00C8)) ++#define IFX_ICU_IM_VEC ((volatile u32*)(IFX_ICU + 0x00D0)) ++ ++/***********************************************************************/ ++ ++#define IFX_ICU_VPE1 (KSEG1 | 0x1F880300) ++#define IFX_ICU1 IFX_ICU_VPE1 ++ ++#define IFX_ICU_VPE1_IM0_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0000)) ++#define IFX_ICU_VPE1_IM0_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0008)) ++#define IFX_ICU_VPE1_IM0_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0010)) ++#define IFX_ICU_VPE1_IM0_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0018)) ++#define IFX_ICU_VPE1_IM0_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0020)) ++ ++#define IFX_ICU_VPE1_IM1_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0028)) ++#define IFX_ICU_VPE1_IM1_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0030)) ++#define IFX_ICU_VPE1_IM1_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0038)) ++#define IFX_ICU_VPE1_IM1_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0040)) ++#define IFX_ICU_VPE1_IM1_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0048)) ++ ++#define IFX_ICU_VPE1_IM2_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0050)) ++#define IFX_ICU_VPE1_IM2_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0058)) ++#define IFX_ICU_VPE1_IM2_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0060)) ++#define IFX_ICU_VPE1_IM2_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0068)) ++#define IFX_ICU_VPE1_IM2_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0070)) ++ ++#define IFX_ICU_VPE1_IM3_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0078)) ++#define IFX_ICU_VPE1_IM3_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0080)) ++#define IFX_ICU_VPE1_IM3_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0088)) ++#define IFX_ICU_VPE1_IM3_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0090)) ++#define IFX_ICU_VPE1_IM3_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0098)) ++ ++#define IFX_ICU_VPE1_IM4_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x00A0)) ++#define IFX_ICU_VPE1_IM4_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x00A8)) ++#define IFX_ICU_VPE1_IM4_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x00B0)) ++#define IFX_ICU_VPE1_IM4_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x00B8)) ++#define IFX_ICU_VPE1_IM4_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x00C0)) ++ ++/***Interrupt Vector Value Register***/ ++#define IFX_ICU_VPE1_IM_VEC_5 ((volatile u32*)(IFX_ICU_VPE1 + 0x00C8)) ++#define IFX_ICU_VPE1_IM_VEC ((volatile u32*)(IFX_ICU_VPE1 + 0x00D0)) ++ ++/***Interrupt Vector Value Mask***/ ++#define IFX_ICU_IM0_VEC_MASK (0x3F << 0) ++#define IFX_ICU_IM1_VEC_MASK (0x3F << 6) ++#define IFX_ICU_IM2_VEC_MASK (0x3F << 12) ++#define IFX_ICU_IM3_VEC_MASK (0x3F << 18) ++#define IFX_ICU_IM4_VEC_MASK (0x3F << 24) ++ ++#define IFX_ICU_IM0_ISR_IR(value) (1 << (value)) ++#define IFX_ICU_IM0_IER_IR(value) (1 << (value)) ++#define IFX_ICU_IM1_ISR_IR(value) (1 << (value)) ++#define IFX_ICU_IM1_IER_IR(value) (1 << (value)) ++#define IFX_ICU_IM2_ISR_IR(value) (1 << (value)) ++#define IFX_ICU_IM2_IER_IR(value) (1 << (value)) ++#define IFX_ICU_IM3_ISR_IR(value) (1 << (value)) ++#define IFX_ICU_IM3_IER_IR(value) (1 << (value)) ++#define IFX_ICU_IM4_ISR_IR(value) (1 << (value)) ++#define IFX_ICU_IM4_IER_IR(value) (1 << (value)) ++#define IFX_ICU_IM5_ISR_IR(value) (1 << (value)) ++#define IFX_ICU_IM5_IER_IR(value) (1 << (value)) ++ ++/***External Interrupt Control Register***/ ++#define IFX_ICU_EIU (KSEG1 | 0x1F101000) ++#define IFX_ICU_EIU_EXIN_C ((volatile u32 *)(IFX_ICU_EIU + 0x0000)) ++#define IFX_ICU_EIU_INIC ((volatile u32 *)(IFX_ICU_EIU + 0x0004)) ++#define IFX_ICU_EIU_INC ((volatile u32 *)(IFX_ICU_EIU + 0x0008)) ++#define IFX_ICU_EIU_INEN ((volatile u32 *)(IFX_ICU_EIU + 0x000C)) ++#define IFX_YIELDEN(n) ((volatile u32 *)(IFX_ICU_EIU + 0x0010 + (n) * 4) ++#define IFX_NMI_CR ((volatile u32 *)(IFX_ICU_EIU + 0x00F0)) ++#define IFX_NMI_SR ((volatile u32 *)(IFX_ICU_EIU + 0x00F4)) ++ ++ ++ ++/***********************************************************************/ ++/* Module : MPS register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_MPS (KSEG1 | 0x1F107000) ++ ++#define IFX_MPS_CHIPID ((volatile u32*)(IFX_MPS + 0x0344)) ++#define IFX_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) ++#define IFX_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) ++#define IFX_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) ++#define IFX_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12) ++#define IFX_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) ++#define IFX_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1) ++ ++ ++/* voice channel 0 ... 3 interrupt enable register */ ++#define IFX_MPS_VC0ENR ((volatile u32*)(IFX_MPS + 0x0000)) ++#define IFX_MPS_VC1ENR ((volatile u32*)(IFX_MPS + 0x0004)) ++#define IFX_MPS_VC2ENR ((volatile u32*)(IFX_MPS + 0x0008)) ++#define IFX_MPS_VC3ENR ((volatile u32*)(IFX_MPS + 0x000C)) ++/* voice channel 0 ... 3 interrupt status read register */ ++#define IFX_MPS_RVC0SR ((volatile u32*)(IFX_MPS + 0x0010)) ++#define IFX_MPS_RVC1SR ((volatile u32*)(IFX_MPS + 0x0014)) ++#define IFX_MPS_RVC2SR ((volatile u32*)(IFX_MPS + 0x0018)) ++#define IFX_MPS_RVC3SR ((volatile u32*)(IFX_MPS + 0x001C)) ++/* voice channel 0 ... 3 interrupt status set register */ ++#define IFX_MPS_SVC0SR ((volatile u32*)(IFX_MPS + 0x0020)) ++#define IFX_MPS_SVC1SR ((volatile u32*)(IFX_MPS + 0x0024)) ++#define IFX_MPS_SVC2SR ((volatile u32*)(IFX_MPS + 0x0028)) ++#define IFX_MPS_SVC3SR ((volatile u32*)(IFX_MPS + 0x002C)) ++/* voice channel 0 ... 3 interrupt status clear register */ ++#define IFX_MPS_CVC0SR ((volatile u32*)(IFX_MPS + 0x0030)) ++#define IFX_MPS_CVC1SR ((volatile u32*)(IFX_MPS + 0x0034)) ++#define IFX_MPS_CVC2SR ((volatile u32*)(IFX_MPS + 0x0038)) ++#define IFX_MPS_CVC3SR ((volatile u32*)(IFX_MPS + 0x003C)) ++/* common status 0 and 1 read register */ ++#define IFX_MPS_RAD0SR ((volatile u32*)(IFX_MPS + 0x0040)) ++#define IFX_MPS_RAD1SR ((volatile u32*)(IFX_MPS + 0x0044)) ++/* common status 0 and 1 set register */ ++#define IFX_MPS_SAD0SR ((volatile u32*)(IFX_MPS + 0x0048)) ++#define IFX_MPS_SAD1SR ((volatile u32*)(IFX_MPS + 0x004C)) ++/* common status 0 and 1 clear register */ ++#define IFX_MPS_CAD0SR ((volatile u32*)(IFX_MPS + 0x0050)) ++#define IFX_MPS_CAD1SR ((volatile u32*)(IFX_MPS + 0x0054)) ++/* common status 0 and 1 enable register */ ++#define IFX_MPS_AD0ENR ((volatile u32*)(IFX_MPS + 0x0058)) ++#define IFX_MPS_AD1ENR ((volatile u32*)(IFX_MPS + 0x005C)) ++/* notification enable register */ ++#define IFX_MPS_CPU0_NFER ((volatile u32*)(IFX_MPS + 0x0060)) ++#define IFX_MPS_CPU1_NFER ((volatile u32*)(IFX_MPS + 0x0064)) ++/* CPU to CPU interrup request register */ ++#define IFX_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(IFX_MPS + 0x0070)) ++#define IFX_MPS_CPU0_2_CPU1_IER ((volatile u32*)(IFX_MPS + 0x0074)) ++/* Global interrupt request and request enable register */ ++#define IFX_MPS_GIRR ((volatile u32*)(IFX_MPS + 0x0078)) ++#define IFX_MPS_GIER ((volatile u32*)(IFX_MPS + 0x007C)) ++ ++#define IFX_MPS_SRAM ((volatile u32*)(KSEG1 | 0x1F200000)) ++ ++#define IFX_MPS_VCPU_FW_AD ((volatile u32*)(KSEG1 | 0x1F2001E0)) ++ ++#define IFX_FUSE_BASE_ADDR (KSEG1 | 0x1F107354) ++ ++ ++ ++/************************************************************************/ ++/* Module : DEU register address and bits */ ++/************************************************************************/ ++ ++#define IFX_DEU_BASE_ADDR (KSEG1 | 0x1E103100) ++ ++/* DEU Control Register */ ++#define IFX_DEU_CLK ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0000)) ++#define IFX_DEU_ID ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0008)) ++ ++/* DEU control register */ ++#define IFX_DES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0010)) ++#define IFX_DES_IHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0014)) ++#define IFX_DES_ILR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0018)) ++#define IFX_DES_K1HR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x001C)) ++#define IFX_DES_K1LR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0020)) ++#define IFX_DES_K3HR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0024)) ++#define IFX_DES_K3LR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0028)) ++#define IFX_DES_IVHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x002C)) ++#define IFX_DES_IVLR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0030)) ++#define IFX_DES_OHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0040)) ++#define IFX_DES_OLR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050)) ++ ++/* AES DEU register */ ++#define IFX_AES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050)) ++#define IFX_AES_ID3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0054)) ++#define IFX_AES_ID2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0058)) ++#define IFX_AES_ID1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x005C)) ++#define IFX_AES_ID0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0060)) ++ ++/* AES Key register */ ++#define IFX_AES_K7R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0064)) ++#define IFX_AES_K6R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0068)) ++#define IFX_AES_K5R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x006C)) ++#define IFX_AES_K4R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0070)) ++#define IFX_AES_K3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0074)) ++#define IFX_AES_K2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0078)) ++#define IFX_AES_K1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x007C)) ++#define IFX_AES_K0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0080)) ++ ++/* AES vector register */ ++#define IFX_AES_IV3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0084)) ++#define IFX_AES_IV2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0088)) ++#define IFX_AES_IV1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x008C)) ++#define IFX_AES_IV0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0090)) ++#define IFX_AES_0D3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0094)) ++#define IFX_AES_0D2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0098)) ++#define IFX_AES_OD1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x009C)) ++#define IFX_AES_OD0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00A0)) ++ ++/* ARC4 DEU register */ ++#define IFX_ARC4_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0100)) ++#define IFX_ARC4_IDLEN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0114)) ++#define IFX_ARC4_ID3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0118)) ++#define IFX_ARC4_ID2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x011C)) ++#define IFX_ARC4_ID1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0120)) ++#define IFX_ARC4_ID0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0124)) ++ ++/* ARC4 Key register */ ++#define IFX_ARC4_K3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0104)) ++#define IFX_ARC4_K2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0108)) ++#define IFX_ARC4_K1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x010C)) ++#define IFX_ARC4_K0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0110)) ++ ++/* ARC4 vector register */ ++#define IFX_ARC4_OD3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0128)) ++#define IFX_ARC4_OD2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x012C)) ++#define IFX_ARC4_OD1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0130)) ++#define IFX_ARC4_OD0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0134)) ++ ++/* hash control register */ ++#define IFX_HASH_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B0)) ++#define IFX_HASH_MR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B4)) ++#define IFX_HASH_D1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B8)) ++#define IFX_HASH_D2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00BC)) ++#define IFX_HASH_D3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C0)) ++#define IFX_HASH_D4R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C4)) ++#define IFX_HASH_D5R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C8)) ++ ++#define IFX_HMAC_KIDX ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00D0)) ++#define IFX_HMAC_KEY ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00D4)) ++#define IFX_HMAC_DBN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00D8)) ++ ++#define IFX_DEU_DMA_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00EC)) ++ ++#define IFX_DEU_IRNEN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00F4)) ++#define IFX_DEU_IRNCR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00F8)) ++#define IFX_DEU_IRNICR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00FC)) ++ ++ ++ ++/************************************************************************/ ++/* Module : PPE register address and bits */ ++/************************************************************************/ ++ ++#define IFX_PPE32_BASE (KSEG1 | 0x1E180000) ++#define IFX_PPE32_DEBUG_BREAK_TRACE_REG (IFX_PPE32_BASE + (0x0000 * 4)) ++#define IFX_PPE32_INT_MASK_STATUS_REG (IFX_PPE32_BASE + (0x0030 * 4)) ++#define IFX_PPE32_INT_RESOURCE_REG (IFX_PPE32_BASE + (0x0040 * 4)) ++#define IFX_PPE32_CDM_CODE_MEM_B0 (IFX_PPE32_BASE + (0x1000 * 4)) ++#define IFX_PPE32_CDM_CODE_MEM_B1 (IFX_PPE32_BASE + (0x2000 * 4)) ++#define IFX_PPE32_DATA_MEM_MAP_REG_BASE (IFX_PPE32_BASE + (0x4000 * 4)) ++ ++#define IFX_PPE32_SRST (IFX_PPE32_BASE + 0x10080) ++ ++/* ++ * ETOP MDIO Registers ++ */ ++#define IFX_PP32_ETOP_MDIO_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4))) ++#define IFX_PP32_ETOP_MDIO_ACC ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4))) ++#define IFX_PP32_ETOP_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4))) ++#define IFX_PP32_ETOP_IG_VLAN_COS ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4))) ++#define IFX_PP32_ETOP_IG_DSCP_COS3 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4))) ++#define IFX_PP32_ETOP_IG_DSCP_COS2 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4))) ++#define IFX_PP32_ETOP_IG_DSCP_COS1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4))) ++#define IFX_PP32_ETOP_IG_DSCP_COS0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4))) ++#define IFX_PP32_ETOP_IG_PLEN_CTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4))) ++#define IFX_PP32_ETOP_ISR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4))) ++#define IFX_PP32_ETOP_IER ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4))) ++#define IFX_PP32_ETOP_VPID ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4))) ++#define IFX_PP32_ENET_MAC_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4))) ++#define IFX_PP32_ENETS_DBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4))) ++#define IFX_PP32_ENETS_CBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4))) ++#define IFX_PP32_ENETS_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4))) ++#define IFX_PP32_ENETS_PGCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4))) ++#define IFX_PP32_ENETS_PKTCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4))) ++#define IFX_PP32_ENETS_BUF_CTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4))) ++#define IFX_PP32_ENETS_COS_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4))) ++#define IFX_PP32_ENETS_IGDROP ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4))) ++#define IFX_PP32_ENETS_IGERR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4))) ++#define IFX_PP32_ENET_MAC_DA0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4))) ++#define IFX_PP32_ENET_MAC_DA1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4))) ++ ++#define IFX_PP32_ENETF_DBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0630 * 4))) ++#define IFX_PP32_ENETF_CBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0631 * 4))) ++#define IFX_PP32_ENETF_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0632 * 4))) ++#define IFX_PP32_ENETF_PGCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0633 * 4))) ++#define IFX_PP32_ENETF_PKTCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0634 * 4))) ++#define IFX_PP32_ENETF_HFCTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0635 * 4))) ++#define IFX_PP32_ENETF_TXCTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0636 * 4))) ++ ++#define IFX_PP32_ENETF_VLCOS0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0638 * 4))) ++#define IFX_PP32_ENETF_VLCOS1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0639 * 4))) ++#define IFX_PP32_ENETF_VLCOS2 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063A * 4))) ++#define IFX_PP32_ENETF_VLCOS3 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063B * 4))) ++#define IFX_PP32_ENETF_EGERR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063C * 4))) ++#define IFX_PP32_ENETF_EGDROP ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063D * 4))) ++ ++ ++/* Sharebuff SB RAM2 control data */ ++#define IFX_PP32_SB2_DATABASE ((IFX_PPE32_BASE + (0x8C00 * 4))) ++#define IFX_PP32_SB2_CTRLBASE ((IFX_PPE32_BASE + (0x92E0 * 4))) ++ ++ ++ ++/************************************************************************/ ++/* Module : 3-port Switch register address and bits */ ++/************************************************************************/ ++ ++#define IFX_SW (KSEG1 | 0x1E108000) ++ ++#define IFX_SW_PS (IFX_SW + 0x000) ++#define IFX_SW_P0_CTL (IFX_SW + 0x004) ++#define IFX_SW_P1_CTL (IFX_SW + 0x008) ++#define IFX_SW_P2_CTL (IFX_SW + 0x00C) ++#define IFX_SW_P0_VLAN (IFX_SW + 0x010) ++#define IFX_SW_P1_VLAN (IFX_SW + 0x014) ++#define IFX_SW_P2_VLAN (IFX_SW + 0x018) ++#define IFX_SW_P0_INCTL (IFX_SW + 0x020) ++#define IFX_SW_P1_INCTL (IFX_SW + 0x024) ++#define IFX_SW_P2_INCTL (IFX_SW + 0x028) ++#define IFX_SW_DF_PORTMAP (IFX_SW + 0x02C) ++#define IFX_SW_P0_ECS_Q32 (IFX_SW + 0x030) ++#define IFX_SW_P0_ECS_Q10 (IFX_SW + 0x034) ++#define IFX_SW_P0_ECW_Q32 (IFX_SW + 0x038) ++#define IFX_SW_P0_ECW_Q10 (IFX_SW + 0x03C) ++#define IFX_SW_P1_ECS_Q32 (IFX_SW + 0x040) ++#define IFX_SW_P1_ECS_Q10 (IFX_SW + 0x044) ++#define IFX_SW_P1_ECW_Q32 (IFX_SW + 0x048) ++#define IFX_SW_P1_ECW_Q10 (IFX_SW + 0x04C) ++#define IFX_SW_P2_ECS_Q32 (IFX_SW + 0x050) ++#define IFX_SW_P2_ECS_Q10 (IFX_SW + 0x054) ++#define IFX_SW_P2_ECW_Q32 (IFX_SW + 0x058) ++#define IFX_SW_P2_ECW_Q10 (IFX_SW + 0x05C) ++#define IFX_SW_INT_ENA (IFX_SW + 0x060) ++#define IFX_SW_INT_ST (IFX_SW + 0x064) ++#define IFX_SW_GCTL0 (IFX_SW + 0x068) ++#define IFX_SW_GCTL1 (IFX_SW + 0x06C) ++#define IFX_SW_ARP (IFX_SW + 0x070) ++#define IFX_SW_STRM_CTL (IFX_SW + 0x074) ++#define IFX_SW_RGMII_CTL (IFX_SW + 0x078) ++#define IFX_SW_1P_PRT (IFX_SW + 0x07C) ++#define IFX_SW_GBKT_SZBS (IFX_SW + 0x080) ++#define IFX_SW_GBKT_SZEBS (IFX_SW + 0x084) ++#define IFX_SW_BF_TH (IFX_SW + 0x088) ++#define IFX_SW_PMAC_HD_CTL (IFX_SW + 0x08C) ++#define IFX_SW_PMAC_SA1 (IFX_SW + 0x090) ++#define IFX_SW_PMAC_SA2 (IFX_SW + 0x094) ++#define IFX_SW_PMAC_DA1 (IFX_SW + 0x098) ++#define IFX_SW_PMAC_DA2 (IFX_SW + 0x09C) ++#define IFX_SW_PMAC_VLAN (IFX_SW + 0x0A0) ++#define IFX_SW_PMAC_TX_IPG (IFX_SW + 0x0A4) ++#define IFX_SW_PMAC_RX_IPG (IFX_SW + 0x0A8) ++#define IFX_SW_ADR_TB_CTL0 (IFX_SW + 0x0AC) ++#define IFX_SW_ADR_TB_CTL1 (IFX_SW + 0x0B0) ++#define IFX_SW_ADR_TB_CTL2 (IFX_SW + 0x0B4) ++#define IFX_SW_ADR_TB_ST0 (IFX_SW + 0x0B8) ++#define IFX_SW_ADR_TB_ST1 (IFX_SW + 0x0BC) ++#define IFX_SW_ADR_TB_ST2 (IFX_SW + 0x0C0) ++#define IFX_SW_RMON_CTL (IFX_SW + 0x0C4) ++#define IFX_SW_RMON_ST (IFX_SW + 0x0C8) ++#define IFX_SW_MDIO_CTL (IFX_SW + 0x0CC) ++#define IFX_SW_MDIO_DATA (IFX_SW + 0x0D0) ++#define IFX_SW_TP_FLT_ACT (IFX_SW + 0x0D4) ++#define IFX_SW_PRTCL_FLT_ACT (IFX_SW + 0x0D8) ++#define IFX_SW_VLAN_FLT0 (IFX_SW + 0x100) ++#define IFX_SW_VLAN_FLT1 (IFX_SW + 0x104) ++#define IFX_SW_VLAN_FLT2 (IFX_SW + 0x108) ++#define IFX_SW_VLAN_FLT3 (IFX_SW + 0x10C) ++#define IFX_SW_VLAN_FLT4 (IFX_SW + 0x110) ++#define IFX_SW_VLAN_FLT5 (IFX_SW + 0x114) ++#define IFX_SW_VLAN_FLT6 (IFX_SW + 0x118) ++#define IFX_SW_VLAN_FLT7 (IFX_SW + 0x11C) ++#define IFX_SW_VLAN_FLT8 (IFX_SW + 0x120) ++#define IFX_SW_VLAN_FLT9 (IFX_SW + 0x124) ++#define IFX_SW_VLAN_FLT10 (IFX_SW + 0x128) ++#define IFX_SW_VLAN_FLT11 (IFX_SW + 0x12C) ++#define IFX_SW_VLAN_FLT12 (IFX_SW + 0x130) ++#define IFX_SW_VLAN_FLT13 (IFX_SW + 0x134) ++#define IFX_SW_VLAN_FLT14 (IFX_SW + 0x138) ++#define IFX_SW_VLAN_FLT15 (IFX_SW + 0x13C) ++#define IFX_SW_TP_FLT10 (IFX_SW + 0x140) ++#define IFX_SW_TP_FLT32 (IFX_SW + 0x144) ++#define IFX_SW_TP_FLT54 (IFX_SW + 0x148) ++#define IFX_SW_TP_FLT76 (IFX_SW + 0x14C) ++#define IFX_SW_DFSRV_MAP0 (IFX_SW + 0x150) ++#define IFX_SW_DFSRV_MAP1 (IFX_SW + 0x154) ++#define IFX_SW_DFSRV_MAP2 (IFX_SW + 0x158) ++#define IFX_SW_DFSRV_MAP3 (IFX_SW + 0x15C) ++#define IFX_SW_TCP_PF0 (IFX_SW + 0x160) ++#define IFX_SW_TCP_PF1 (IFX_SW + 0x164) ++#define IFX_SW_TCP_PF2 (IFX_SW + 0x168) ++#define IFX_SW_TCP_PF3 (IFX_SW + 0x16C) ++#define IFX_SW_TCP_PF4 (IFX_SW + 0x170) ++#define IFX_SW_TCP_PF5 (IFX_SW + 0x174) ++#define IFX_SW_TCP_PF6 (IFX_SW + 0x178) ++#define IFX_SW_TCP_PF7 (IFX_SW + 0x17C) ++#define IFX_SW_RA_03_00 (IFX_SW + 0x180) ++#define IFX_SW_RA_07_04 (IFX_SW + 0x184) ++#define IFX_SW_RA_0B_08 (IFX_SW + 0x188) ++#define IFX_SW_RA_0F_0C (IFX_SW + 0x18C) ++#define IFX_SW_RA_13_10 (IFX_SW + 0x190) ++#define IFX_SW_RA_17_14 (IFX_SW + 0x194) ++#define IFX_SW_RA_1B_18 (IFX_SW + 0x198) ++#define IFX_SW_RA_1F_1C (IFX_SW + 0x19C) ++#define IFX_SW_RA_23_20 (IFX_SW + 0x1A0) ++#define IFX_SW_RA_27_24 (IFX_SW + 0x1A4) ++#define IFX_SW_RA_2B_28 (IFX_SW + 0x1A8) ++#define IFX_SW_RA_2F_2C (IFX_SW + 0x1AC) ++#define IFX_SW_F0 (IFX_SW + 0x1B0) ++#define IFX_SW_F1 (IFX_SW + 0x1B4) ++ ++/* ++ * Routine for Voice ++ */ ++extern const void (*ifx_bsp_basic_mps_decrypt)(unsigned int addr, int n); ++ ++ ++#endif /* AR9_H */ ++ +diff --git a/arch/mips/include/asm/ifx/ar9/ar9_ref_board.h b/arch/mips/include/asm/ifx/ar9/ar9_ref_board.h +new file mode 100644 +index 0000000..b37710d +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ar9/ar9_ref_board.h +@@ -0,0 +1,48 @@ ++/****************************************************************************** ++** ++** FILE NAME : ar9_ref_board.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : header file for AR9 ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef AR9_REF_BOARD_H ++#define AR9_REF_BOARD_H ++ ++#if defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) ++#define IFX_MTD_SPI_PART_NB 3 ++#define IFX_SPI_FLASH_MAX 8 ++#endif /* defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) */ ++ ++#if defined(CONFIG_USB_HOST_IFX) || defined(CONFIG_USB_HOST_IFX_MODULE) ++ #if defined(CONFIG_IFX_GW188) ++// #define IFX_GPIO_USB_VBUS1 IFX_GPIO_PIN_ID(2, 5) ++ #else ++// #define IFX_GPIO_USB_VBUS1 IFX_GPIO_PIN_ID(1, 13) ++ #endif ++// #define IFX_GPIO_USB_VBUS2 IFX_GPIO_PIN_ID(3, 4) ++#endif ++ ++#if (defined(CONFIG_USB_GADGET_IFX) || defined(CONFIG_USB_GADGET_IFX_MODULE)) && defined(CONFIG_USB_GADGET_IFX_LED) ++ #define IFX_LEDLED_USB_LED 10 ++#endif ++ ++#endif /* AR9_REF_BOARD_H */ ++ +diff --git a/arch/mips/include/asm/ifx/ar9/irq.h b/arch/mips/include/asm/ifx/ar9/irq.h +new file mode 100644 +index 0000000..3c8cd28 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ar9/irq.h +@@ -0,0 +1,176 @@ ++/****************************************************************************** ++** ++** FILE NAME : irq.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : header file for AR9 ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef AR9_IRQ_H ++#define AR9_IRQ_H ++ ++ ++ ++/****** Interrupt Assigments ***********/ ++ ++#define IFX_ASC0_TIR INT_NUM_IM3_IRL0 /* TX interrupt */ ++#define IFX_ASC0_TBIR INT_NUM_IM3_IRL1 /* TX buffer interrupt */ ++#define IFX_ASC0_RIR INT_NUM_IM3_IRL2 /* RX interrupt */ ++#define IFX_ASC0_EIR INT_NUM_IM3_IRL3 /* ERROR interrupt */ ++#define IFX_ASC0_ABSTIR INT_NUM_IM3_IRL4 ++#define IFX_ASC0_ABDETIR INT_NUM_IM3_IRL5 ++#define IFX_ASC0_SFCIR INT_NUM_IM3_IRL6 ++#define IFX_ASC0_MIR INT_NUM_IM3_IRL21 ++#define IFX_ASC1_TIR INT_NUM_IM3_IRL7 /* TX interrupt */ ++#define IFX_ASC1_TBIR INT_NUM_IM3_IRL8 /* TX buffer interrupt */ ++#define IFX_ASC1_RIR INT_NUM_IM3_IRL9 /* RX interrupt */ ++#define IFX_ASC1_EIR INT_NUM_IM3_IRL10 /* ERROR interrupt */ ++#define IFX_ASC1_ABSTIR INT_NUM_IM3_IRL11 ++#define IFX_ASC1_ABDETIR INT_NUM_IM3_IRL12 ++#define IFX_ASC1_SFCIR INT_NUM_IM3_IRL13 ++ ++#define IFX_FPI_SLAVE_BCU0_IR INT_NUM_IM1_IRL25 ++#define IFX_FPI_MASTER_COSBCU_IR INT_NUM_IM0_IRL25 ++#define IFX_FPI_SLAVE_BCU_IRQ IFX_FPI_SLAVE_BCU0_IR ++#define IFX_FPI_MASTER_BCU_IRQ IFX_FPI_MASTER_COSBCU_IR ++ ++#define IFX_DSL_DFE_IR INT_NUM_IM1_IRL23 ++#define IFX_DSL_AFEOVL_IR INT_NUM_IM1_IRL24 ++#define IFX_DSL_DYING_GASP_INT INT_NUM_IM1_IRL21 ++#define IFX_DSL_DFE_INT0IR INT_NUM_IM2_IRL12 ++#define IFX_DSL_DFE_INT1IR INT_NUM_IM2_IRL13 ++#define IFX_DSL_DFE_INT2IR INT_NUM_IM2_IRL14 ++#define IFX_DSL_DFE_INT3IR INT_NUM_IM2_IRL15 ++#define IFX_MEI_INT IFX_DSL_DFE_IR ++#define IFX_MEI_DYING_GASP_INT IFX_DSL_DYING_GASP_INT ++#define IFX_DSL_DFE_TXIR IFX_DSL_DFE_INT0IR ++#define IFX_DSL_DFE_RXIR IFX_DSL_DFE_INT1IR ++ ++#define IFX_VOICE_DFE0_CH0_RX INT_NUM_IM4_IRL12 ++#define IFX_VOICE_DFE0_CH0_TX INT_NUM_IM4_IRL13 ++#define IFX_VOICE_DFE0_CH0_GP INT_NUM_IM0_IRL31 ++#define IFX_VOICE_DFE0_CH1_RX INT_NUM_IM3_IRL19 ++#define IFX_VOICE_DFE0_CH1_TX INT_NUM_IM3_IRL20 ++#define IFX_VOICE_DFE0_CH1_GP INT_NUM_IM3_IRL14 ++#define IFX_VOICE_DFE1_CH0_RX INT_NUM_IM1_IRL3 ++#define IFX_VOICE_DFE1_CH0_TX INT_NUM_IM1_IRL4 ++#define IFX_VOICE_DFE1_CH0_GP INT_NUM_IM1_IRL5 ++#define IFX_VOICE_DFE1_CH1_RX INT_NUM_IM1_IRL6 ++#define IFX_VOICE_DFE1_CH1_TX INT_NUM_IM1_IRL7 ++#define IFX_VOICE_DFE1_CH1_GP INT_NUM_IM1_IRL8 ++ ++#define IFX_DEU_DESIR INT_NUM_IM0_IRL27 ++#define IFX_DEU_AESIR INT_NUM_IM0_IRL28 ++#define IFX_DEU_HASHIR INT_NUM_IM0_IRL29 ++#define IFX_DEU_ARCIR INT_NUM_IM0_IRL26 ++ ++#define IFX_DMA_CH0_INT INT_NUM_IM2_IRL0 ++#define IFX_DMA_CH1_INT INT_NUM_IM2_IRL1 ++#define IFX_DMA_CH2_INT INT_NUM_IM2_IRL2 ++#define IFX_DMA_CH3_INT INT_NUM_IM2_IRL3 ++#define IFX_DMA_CH4_INT INT_NUM_IM2_IRL4 ++#define IFX_DMA_CH5_INT INT_NUM_IM2_IRL5 ++#define IFX_DMA_CH6_INT INT_NUM_IM2_IRL6 ++#define IFX_DMA_CH7_INT INT_NUM_IM2_IRL7 ++#define IFX_DMA_CH8_INT INT_NUM_IM2_IRL8 ++#define IFX_DMA_CH9_INT INT_NUM_IM2_IRL9 ++#define IFX_DMA_CH10_INT INT_NUM_IM2_IRL10 ++#define IFX_DMA_CH11_INT INT_NUM_IM2_IRL11 ++#define IFX_DMA_CH12_INT INT_NUM_IM2_IRL25 ++#define IFX_DMA_CH13_INT INT_NUM_IM2_IRL26 ++#define IFX_DMA_CH14_INT INT_NUM_IM2_IRL27 ++#define IFX_DMA_CH15_INT INT_NUM_IM2_IRL28 ++#define IFX_DMA_CH16_INT INT_NUM_IM2_IRL29 ++#define IFX_DMA_CH17_INT INT_NUM_IM1_IRL30 ++#define IFX_DMA_CH18_INT INT_NUM_IM2_IRL16 ++#define IFX_DMA_CH19_INT INT_NUM_IM2_IRL21 ++ ++#define IFX_PPE_MBOX_INT0 INT_NUM_IM2_IRL23 ++#define IFX_PPE_MBOX_INT1 INT_NUM_IM2_IRL24 ++#define IFX_PPE_MBOX_INT2 INT_NUM_IM1_IRL29 ++#define IFX_PPE_QSB_INT INT_NUM_IM1_IRL31 ++ ++#define IFX_GE_SW_INT INT_NUM_IM1_IRL16 ++ ++#define IFX_EIU_IR0 INT_NUM_IM4_IRL30 /* 158 */ ++#define IFX_EIU_IR1 INT_NUM_IM3_IRL31 /* 127 */ ++#define IFX_EIU_IR2 INT_NUM_IM1_IRL26 /* 58 */ ++#define IFX_EIU_IR3 INT_NUM_IM1_IRL0 /* 32 */ ++#define IFX_EIU_IR4 INT_NUM_IM1_IRL1 /* 33 */ ++#define IFX_EIU_IR5 INT_NUM_IM1_IRL2 /* 34 */ ++ ++#define IFX_EIU_IR6 INT_NUM_IM2_IRL30 /* 94 */ ++#define IFX_SI_EIU_IR IFX_EIU_IR6 ++ ++#define IFX_MPS_IR0 INT_NUM_IM4_IRL14 ++#define IFX_MPS_IR1 INT_NUM_IM4_IRL15 ++#define IFX_MPS_IR2 INT_NUM_IM4_IRL16 ++#define IFX_MPS_IR3 INT_NUM_IM4_IRL17 ++#define IFX_MPS_IR4 INT_NUM_IM4_IRL18 ++#define IFX_MPS_IR5 INT_NUM_IM4_IRL19 ++#define IFX_MPS_IR6 INT_NUM_IM4_IRL20 ++#define IFX_MPS_IR7 INT_NUM_IM4_IRL21 ++#define IFX_MPS_IR8 INT_NUM_IM4_IRL22 ++#define IFX_MPS_SEMAPHORE_IR IFX_MPS_IR7 ++#define IFX_MPS_GLOBAL_IR IFX_MPS_IR8 ++ ++#define IFX_RTI_8KHZ_IR INT_NUM_IM2_IRL31 ++ ++#define IFX_GPTU_TC1A INT_NUM_IM3_IRL22 ++#define IFX_GPTU_TC1B INT_NUM_IM3_IRL23 ++#define IFX_GPTU_TC2A INT_NUM_IM3_IRL24 ++#define IFX_GPTU_TC2B INT_NUM_IM3_IRL25 ++#define IFX_GPTU_TC3A INT_NUM_IM3_IRL26 ++#define IFX_GPTU_TC3B INT_NUM_IM3_IRL27 ++ ++#define IFX_MC_IR INT_NUM_IM3_IRL28 ++ ++#define IFX_EBU_IR INT_NUM_IM0_IRL22 ++ ++#define IFX_PCI_IR INT_NUM_IM1_IRL17 ++#define IFX_PCI_WRIR INT_NUM_IM1_IRL18 ++ ++#define IFX_PCM_TXIR INT_NUM_IM1_IRL19 ++#define IFX_PCM_RXIR INT_NUM_IM1_IRL20 ++ ++#define IFX_PMCIR INT_NUM_IM4_IRL31 ++ ++#define IFX_SBIU_ERRIR INT_NUM_IM1_IRL27 ++ ++#define IFX_SSC_RIR INT_NUM_IM0_IRL14 ++#define IFX_SSC_TIR INT_NUM_IM0_IRL15 ++#define IFX_SSC_EIR INT_NUM_IM0_IRL16 ++#define IFX_SSC_FIR INT_NUM_IM0_IRL17 ++ ++#define IFX_MMC_CONTROLLER_INTR0_IRQ INT_NUM_IM0_IRL18 ++#define IFX_MMC_CONTROLLER_INTR1_IRQ INT_NUM_IM0_IRL19 ++#define IFX_MMC_CONTROLLER_SDIO_I_IRQ INT_NUM_IM0_IRL20 ++ ++#define IFX_VLYNQ_IR INT_NUM_IM2_IRL20 ++ ++#define IFX_USB0_IR INT_NUM_IM1_IRL22 ++#define IFX_USB1_IR INT_NUM_IM2_IRL19 ++#define IFX_USB0_OCIR INT_NUM_IM1_IRL28 ++#define IFX_USB_INT IFX_USB0_IR ++#define IFX_USB_OC_INT IFX_USB0_OCIR ++ ++ ++ ++#endif // AR9_IRQ_H +diff --git a/arch/mips/include/asm/ifx/ar9/model.h b/arch/mips/include/asm/ifx/ar9/model.h +new file mode 100644 +index 0000000..2717929 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ar9/model.h +@@ -0,0 +1,54 @@ ++/****************************************************************************** ++** ++** FILE NAME : model.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : header file for AR9 ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef AR9_MODEL_H ++#define AR9_MODEL_H ++/****************************************************************************** ++ Copyright (c) 2002, Infineon Technologies. All rights reserved. ++ ++ No Warranty ++ Because the program is licensed free of charge, there is no warranty for ++ the program, to the extent permitted by applicable law. Except when ++ otherwise stated in writing the copyright holders and/or other parties ++ provide the program "as is" without warranty of any kind, either ++ expressed or implied, including, but not limited to, the implied ++ warranties of merchantability and fitness for a particular purpose. The ++ entire risk as to the quality and performance of the program is with ++ you. should the program prove defective, you assume the cost of all ++ necessary servicing, repair or correction. ++ ++ In no event unless required by applicable law or agreed to in writing ++ will any copyright holder, or any other party who may modify and/or ++ redistribute the program as permitted above, be liable to you for ++ damages, including any general, special, incidental or consequential ++ damages arising out of the use or inability to use the program ++ (including but not limited to loss of data or data being rendered ++ inaccurate or losses sustained by you or third parties or a failure of ++ the program to operate with any other programs), even if such holder or ++ other party has been advised of the possibility of such damages. ++******************************************************************************/ ++#define BOARD_SYSTEM_TYPE "AR9" ++#define SYSTEM_MODEL_NAME "AR9 First Version" ++#endif +diff --git a/arch/mips/include/asm/ifx/common_routines.h b/arch/mips/include/asm/ifx/common_routines.h +new file mode 100644 +index 0000000..85733e2 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/common_routines.h +@@ -0,0 +1,221 @@ ++/****************************************************************************** ++** ++** FILE NAME : common_routines.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : common header file ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef COMMON_ROUTINES_H ++#define COMMON_ROUTINES_H ++ ++ ++ ++#include ++ ++ ++ ++/* ++ * Array Help Macro ++ */ ++#define NUM_ENTITY(x) (sizeof(x) / sizeof(*(x))) ++ ++/* Always report fatal error */ ++#define IFX_KASSERT(exp, msg) do { \ ++ if (unlikely(!(exp))) { \ ++ printk msg; \ ++ BUG(); \ ++ } \ ++} while (0) ++ ++ ++/* ++ * find first 1 from MSB in a 32-bit word ++ * if all ZERO, return -1 ++ * e.g. 0x10000000 => 28 ++ */ ++static inline IFX_int32_t clz(IFX_uint32_t x) ++{ ++ __asm__ ( ++ " .set push \n" ++ " .set mips32 \n" ++ " clz %0, %1 \n" ++ " .set pop \n" ++ : "=r" (x) ++ : "r" (x)); ++ ++ return 31 - (IFX_int32_t)x; ++} ++ ++/* ++ * find first 0 from MSB in a 32-bit word ++ * if all ONE, return -1 ++ * e.g. 0xF0000000 => 27 ++ */ ++static inline IFX_int32_t clo(IFX_uint32_t x) ++{ ++ __asm__ ( ++ " .set push \n" ++ " .set mips32 \n" ++ " clo %0, %1 \n" ++ " .set pop \n" ++ : "=r" (x) ++ : "r" (x)); ++ ++ return 31 - (IFX_int32_t)x; ++} ++ ++/* Tail queue declarations */ ++#define TAILQ_HEAD(name, type) \ ++struct name { \ ++ struct type *tqh_first; /* first element */ \ ++ struct type **tqh_last; /* addr of last next element */ \ ++} ++ ++#define TAILQ_HEAD_INITIALIZER(head) \ ++ { NULL, &(head).tqh_first } ++ ++#define TAILQ_ENTRY(type) \ ++struct { \ ++ struct type *tqe_next; /* next element */ \ ++ struct type **tqe_prev; /* address of previous next element */ \ ++} ++/* ++ * Tail queue functions. ++ */ ++#define TAILQ_CONCAT(head1, head2, field) do { \ ++ if (!TAILQ_EMPTY(head2)) { \ ++ *(head1)->tqh_last = (head2)->tqh_first; \ ++ (head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \ ++ (head1)->tqh_last = (head2)->tqh_last; \ ++ TAILQ_INIT((head2)); \ ++ } \ ++} while (0) ++ ++#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) ++ ++#define TAILQ_FIRST(head) ((head)->tqh_first) ++ ++#define TAILQ_FOREACH(var, head, field) \ ++ for ((var) = TAILQ_FIRST((head)); \ ++ (var); \ ++ (var) = TAILQ_NEXT((var), field)) ++ ++#define TAILQ_FOREACH_SAFE(var, head, field, tvar) \ ++ for ((var) = TAILQ_FIRST((head)); \ ++ (var) && ((tvar) = TAILQ_NEXT((var), field), 1); \ ++ (var) = (tvar)) ++ ++#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \ ++ for ((var) = TAILQ_LAST((head), headname); \ ++ (var); \ ++ (var) = TAILQ_PREV((var), headname, field)) ++ ++#define TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, tvar) \ ++ for ((var) = TAILQ_LAST((head), headname); \ ++ (var) && ((tvar) = TAILQ_PREV((var), headname, field), 1); \ ++ (var) = (tvar)) ++ ++#define TAILQ_INIT(head) do { \ ++ TAILQ_FIRST((head)) = NULL; \ ++ (head)->tqh_last = &TAILQ_FIRST((head)); \ ++} while (0) ++ ++#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ ++ if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\ ++ TAILQ_NEXT((elm), field)->field.tqe_prev = \ ++ &TAILQ_NEXT((elm), field); \ ++ else { \ ++ (head)->tqh_last = &TAILQ_NEXT((elm), field); \ ++ } \ ++ TAILQ_NEXT((listelm), field) = (elm); \ ++ (elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field); \ ++} while (0) ++ ++#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ ++ (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ ++ TAILQ_NEXT((elm), field) = (listelm); \ ++ *(listelm)->field.tqe_prev = (elm); \ ++ (listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field); \ ++} while (0) ++ ++#define TAILQ_INSERT_HEAD(head, elm, field) do { \ ++ if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL) \ ++ TAILQ_FIRST((head))->field.tqe_prev = \ ++ &TAILQ_NEXT((elm), field); \ ++ else \ ++ (head)->tqh_last = &TAILQ_NEXT((elm), field); \ ++ TAILQ_FIRST((head)) = (elm); \ ++ (elm)->field.tqe_prev = &TAILQ_FIRST((head)); \ ++} while (0) ++ ++#define TAILQ_INSERT_TAIL(head, elm, field) do { \ ++ TAILQ_NEXT((elm), field) = NULL; \ ++ (elm)->field.tqe_prev = (head)->tqh_last; \ ++ *(head)->tqh_last = (elm); \ ++ (head)->tqh_last = &TAILQ_NEXT((elm), field); \ ++} while (0) ++ ++#define TAILQ_LAST(head, headname) \ ++ (*(((struct headname *)((head)->tqh_last))->tqh_last)) ++ ++#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) ++ ++#define TAILQ_PREV(elm, headname, field) \ ++ (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) ++ ++#define TAILQ_REMOVE(head, elm, field) do { \ ++ if ((TAILQ_NEXT((elm), field)) != NULL) \ ++ TAILQ_NEXT((elm), field)->field.tqe_prev = \ ++ (elm)->field.tqe_prev; \ ++ else { \ ++ (head)->tqh_last = (elm)->field.tqe_prev; \ ++ } \ ++ *(elm)->field.tqe_prev = TAILQ_NEXT((elm), field); \ ++} while (0) ++ ++ ++static inline int ++ifx_drv_ver(char *buf, char *module, int major, int mid, int minor) ++{ ++ return sprintf(buf, "Lantiq %s driver, version %d.%d.%d, (c) 2001-2011 Lantiq Deutschland GmbH\n", ++ module, major, mid, minor); ++} ++ ++/* ++ * Basic Clock Functions (not for 100% precise usage) ++ */ ++extern unsigned int ifx_get_cpu_hz(void); ++extern unsigned int ifx_get_fpi_hz(void); ++ ++/* ++ * Output on ASC (before ASC/Console driver is ready) ++ */ ++extern void prom_printf(const char *, ...); ++ ++/* ++ * Get Reserved Memory for Voice ++ */ ++extern unsigned int* ifx_get_cp1_base(void); ++extern unsigned int ifx_get_cp1_size(void); ++ ++ ++ ++#endif // COMMON_ROUTINES_H +diff --git a/arch/mips/include/asm/ifx/danube/danube.h b/arch/mips/include/asm/ifx/danube/danube.h +new file mode 100644 +index 0000000..c07661e +--- /dev/null ++++ b/arch/mips/include/asm/ifx/danube/danube.h +@@ -0,0 +1,1442 @@ ++/****************************************************************************** ++** ++** FILE NAME : danube.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : header file for Danube ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef DANUBE_H ++#define DANUBE_H ++#include ++/****************************************************************************** ++ Copyright (c) 2002, Infineon Technologies. All rights reserved. ++ ++ No Warranty ++ Because the program is licensed free of charge, there is no warranty for ++ the program, to the extent permitted by applicable law. Except when ++ otherwise stated in writing the copyright holders and/or other parties ++ provide the program "as is" without warranty of any kind, either ++ expressed or implied, including, but not limited to, the implied ++ warranties of merchantability and fitness for a particular purpose. The ++ entire risk as to the quality and performance of the program is with ++ you. should the program prove defective, you assume the cost of all ++ necessary servicing, repair or correction. ++ ++ In no event unless required by applicable law or agreed to in writing ++ will any copyright holder, or any other party who may modify and/or ++ redistribute the program as permitted above, be liable to you for ++ damages, including any general, special, incidental or consequential ++ damages arising out of the use or inability to use the program ++ (including but not limited to loss of data or data being rendered ++ inaccurate or losses sustained by you or third parties or a failure of ++ the program to operate with any other programs), even if such holder or ++ other party has been advised of the possibility of such damages. ++******************************************************************************/ ++#define MACH_GROUP_IFX MACH_GROUP_DANUBE ++#define MACH_TYPE_IFX MACH_DANUBE ++ ++ ++/***********************************************************************/ ++/* Module : WDT register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_WDT (KSEG1 | 0x1F880000) ++ ++/***Watchdog Timer Control Register ***/ ++#define IFX_WDT_CR ((volatile u32*)(IFX_WDT + 0x03F0)) ++#define IFX_WDT_CR_GEN (1 << 31) ++#define IFX_WDT_CR_DSEN (1 << 30) ++#define IFX_WDT_CR_LPEN (1 << 29) ++#define IFX_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1)) ++#define IFX_WDT_CR_PWL_SET(value) (((( 1 << 2) - 1) & (value)) << 26) ++#define IFX_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1)) ++#define IFX_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24) ++#define IFX_WDT_CR_PW_GET(value) (((value) >> 16) & ((1 << 8) - 1)) ++#define IFX_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16) ++#define IFX_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1)) ++#define IFX_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0) ++ ++/***Watchdog Timer Status Register***/ ++#define IFX_WDT_SR ((volatile u32*)(IFX_WDT + 0x03F8)) ++#define IFX_WDT_SR_EN (1 << 31) ++#define IFX_WDT_SR_AE (1 << 30) ++#define IFX_WDT_SR_PRW (1 << 29) ++#define IFX_WDT_SR_EXP (1 << 28) ++#define IFX_WDT_SR_PWD (1 << 27) ++#define IFX_WDT_SR_DS (1 << 26) ++#define IFX_WDT_SR_VALUE_GET(value) (((value) >> 0) & ((1 << 16) - 1)) ++#define IFX_WDT_SR_VALUE_SET(value) (((( 1 << 16) - 1) & (value)) << 0) ++ ++ ++/***********************************************************************/ ++/* Module : RCU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_RCU (KSEG1 | 0x1F203000) ++ ++#define IFX_RCU_UBSCFG ((volatile u32*)(IFX_RCU + 0x18)) ++ ++#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) ++#define IFX_RCU_RST_STAT ((volatile u32*)(IFX_RCU + 0x0014)) ++#define IFX_USB_CFG ((volatile u32*)(IFX_RCU + 0x0018)) ++#define IFX_USBCFG_HDSEL_BIT 11 // 0:host, 1:device ++#define IFX_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end ++#define IFX_USBCFG_AHB_END_BIT 9 // 0:little_end, 1:big_end ++ ++#define IFX_RST_ALL (1 << 30) ++ ++/***Reset Request Register***/ ++#define IFX_RCU_RST_REQ_CPU0 (1 << 31) ++#define IFX_RCU_RST_REQ_CPU1 (1 << 3) ++#define IFX_RCU_RST_REQ_CPUSUB (1 << 29) ++#define IFX_RCU_RST_REQ_HRST (1 << 28) ++#define IFX_RCU_RST_REQ_WDT0 (1 << 27) ++#define IFX_RCU_RST_REQ_WDT1 (1 << 26) ++#define IFX_RCU_RST_REQ_CFG_GET(value) (((value) >> 23) & ((1 << 3) - 1)) ++#define IFX_RCU_RST_REQ_CFG_SET(value) (((( 1 << 3) - 1) & (value)) << 23) ++#define IFX_RCU_RST_REQ_SWTBOOT (1 << 22) ++#define IFX_RCU_RST_REQ_DMA (1 << 21) ++#define IFX_RCU_RST_REQ_ARC_JTAG (1 << 20) ++#define IFX_RCU_RST_REQ_ETHPHY0 (1 << 19) ++#define IFX_RCU_RST_REQ_CPU0_BR (1 << 18) ++ ++#define IFX_RCU_RST_REQ_AFE (1 << 11) ++#define IFX_RCU_RST_REQ_PPE (1 << 8) ++#define IFX_RCU_RST_REQ_DFE (1 << 7) ++ ++/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */ ++#define IFX_RCU_RST_REQ_ALL IFX_RST_ALL ++ ++ ++ ++/***********************************************************************/ ++/* Module : BCU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_BCU_BASE_ADDR (KSEG1 | 0x1E100000) ++#define IFX_SLAVE_BCU_BASE_ADDR (KSEG1 | 0x1C200400) ++ ++/***BCU Control Register (0010H)***/ ++#define IFX_BCU_CON ((volatile u32*)(0x0010 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_CON ((volatile u32*)(0x0010 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_STARVATION_MASK (0xFF << 24) ++#define IFX_BCU_STARVATION_SHIFT 24 ++#define IFX_BCU_TOUT_MASK 0xFFFF ++#define IFX_BCU_CON_SPC(value) (((( 1 << 8) - 1) & (value)) << 24) ++#define IFX_BCU_CON_SPE (1 << 19) ++#define IFX_BCU_CON_PSE (1 << 18) ++#define IFX_BCU_CON_DBG (1 << 16) ++#define IFX_BCU_CON_TOUT(value) (((( 1 << 16) - 1) & (value)) << 0) ++ ++/***BCU Error Control Capture Register (0020H)***/ ++#define IFX_BCU_ECON ((volatile u32*)(0x0020 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_ECON ((volatile u32*)(0x0020 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_ECON_TAG(value) (((( 1 << 4) - 1) & (value)) << 24) ++#define IFX_BCU_ECON_RDN (1 << 23) ++#define IFX_BCU_ECON_WRN (1 << 22) ++#define IFX_BCU_ECON_SVM (1 << 21) ++#define IFX_BCU_ECON_ACK(value) (((( 1 << 2) - 1) & (value)) << 19) ++#define IFX_BCU_ECON_ABT (1 << 18) ++#define IFX_BCU_ECON_RDY (1 << 17) ++#define IFX_BCU_ECON_TOUT (1 << 16) ++#define IFX_BCU_ECON_ERRCNT(value) (((( 1 << 16) - 1) & (value)) << 0) ++#define IFX_BCU_ECON_OPC(value) (((( 1 << 4) - 1) & (value)) << 28) ++ ++/***BCU Error Address Capture Register (0024 H)***/ ++#define IFX_BCU_EADD ((volatile u32*)(0x0024 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_EADD ((volatile u32*)(0x0024 + IFX_SLAVE_BCU_BASE_ADDR)) ++ ++/***BCU Error Data Capture Register (0028H)***/ ++#define IFX_BCU_EDAT ((volatile u32*)(0x0028 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_EDAT ((volatile u32*)(0x0028 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_IRNICR ((volatile u32*)(0x00F8 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_IRNICR ((volatile u32*)(0x00F8 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_IRNCR ((volatile u32*)(0x00FC + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_IRNCR ((volatile u32*)(0x00FC + IFX_SLAVE_BCU_BASE_ADDR)) ++ ++ ++ ++/***********************************************************************/ ++/* Module : LED register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_LED (KSEG1 | 0x1E100BB0) ++ ++#define IFX_LED_CON0 ((volatile u32*)(IFX_LED + 0x0000)) ++#define IFX_LED_CON1 ((volatile u32*)(IFX_LED + 0x0004)) ++#define IFX_LED_CPU0 ((volatile u32*)(IFX_LED + 0x0008)) ++#define IFX_LED_CPU1 ((volatile u32*)(IFX_LED + 0x000C)) ++#define IFX_LED_AR ((volatile u32*)(IFX_LED + 0x0010)) ++ ++/* ++ * LED Control 0 Register ++ */ ++#define IFX_LED_SWU_SHIFT 31 ++#define IFX_LED_RZFL_SHIFT 26 ++#define IFX_LED_AD1_SHIFT 25 ++#define IFX_LED_AD0_SHIFT 24 ++ ++#define IFX_LED_ADSL_MASK (3 << LED_AD0_SHIFT) ++#define IFX_LED_CON0_SWU (*IFX_LED_CON0 & (1 << 31)) ++#define IFX_LED_CON0_FALLING_EDGE (*IFX_LED_CON0 & (1 << 26)) ++#define IFX_LED_CON0_AD1 (*IFX_LED_CON0 & (1 << 25)) ++#define IFX_LED_CON0_AD0 (*IFX_LED_CON0 & (1 << 24)) ++#define IFX_LED_CON0_LBn(n) (*IFX_LED_CON0 & (1 << n)) ++#define IFX_LED_CON0_DEFAULT_VALUE (0x80000000 | (DATA_CLOCKING_EDGE << 26)) ++ ++/* ++ * LED Control 1 Register ++ */ ++#define IFX_LED_CON1_US (*IFX_LED_CON1 >> 30) ++#define IFX_LED_CON1_SCS (*IFX_LED_CON1 & (1 << 28)) ++#define IFX_LED_CON1_FPID GET_BITS(*IFX_LED_CON1, 27, 23) ++#define IFX_LED_CON1_FPIS GET_BITS(*IFX_LED_CON1, 21, 20) ++#define IFX_LED_CON1_DO GET_BITS(*IFX_LED_CON1, 19, 18) ++#define IFX_LED_CON1_G2 (*IFX_LED_CON1 & (1 << 2)) ++#define IFX_LED_CON1_G1 (*IFX_LED_CON1 & (1 << 1)) ++#define IFX_LED_CON1_G0 (*IFX_LED_CON1 & 0x01) ++#define IFX_LED_CON1_G (*IFX_LED_CON1 & 0x07) ++#define IFX_LED_CON1_DEFAULT_VALUE 0x00000000 ++ ++/* ++ * LED Data Output CPU 0 Register ++ */ ++#define IFX_LED_CPU0_Ln(n) (*IFX_LED_CPU0 & (1 << n)) ++#define IFX_LED_LED_CPU0_DEFAULT_VALUE 0x00000000 ++ ++/* ++ * LED Data Output CPU 1 Register ++ */ ++#define IFX_LED_CPU1_Ln(n) (*IFX_LED_CPU1 & (1 << n)) ++#define IFX_LED_LED_CPU1_DEFAULT_VALUE 0x00000000 ++ ++/* ++ * LED Data Output Access Rights Register ++ */ ++#define IFX_LED_AR_Ln(n) (*IFX_LED_AR & (1 << n)) ++#define IFX_LED_AR_DEFAULT_VALUE 0x00000000 ++ ++ ++ ++/***********************************************************************/ ++/* Module : MEI register address and bits */ ++/***********************************************************************/ ++#define IFX_MEI_SPACE_ACCESS (KSEG1 | 0x1E116000) ++ ++/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/ ++#define IFX_MEI_DATA_XFR ((volatile u32*)(0x0000 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_VERSION ((volatile u32*)(0x0004 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_ARC_GP_STAT ((volatile u32*)(0x0008 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_DATA_XFR_STAT ((volatile u32*)(0x000C + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XFR_ADDR ((volatile u32*)(0x0010 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_MAX_WAIT ((volatile u32*)(0x0014 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_TO_ARC_INT ((volatile u32*)(0x0018 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_ARC_TO_MEI_INT ((volatile u32*)(0x001C + IFX_MEI_SPACE_ACCESS)) ++#define IFX_ARC_TO_MEI_INT_MASK ((volatile u32*)(0x0020 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_DEBUG_WAD ((volatile u32*)(0x0024 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_DEBUG_RAD ((volatile u32*)(0x0028 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_DEBUG_DATA ((volatile u32*)(0x002C + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_DEBUG_DEC ((volatile u32*)(0x0030 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_CONFIG ((volatile u32*)(0x0034 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_RST_CONTROL ((volatile u32*)(0x0038 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_DBG_MASTER ((volatile u32*)(0x003C + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_CLK_CONTROL ((volatile u32*)(0x0040 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_BIST_CONTROL ((volatile u32*)(0x0044 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_BIST_STAT ((volatile u32*)(0x0048 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XDATA_BASE_SH ((volatile u32*)(0x004c + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XDATA_BASE ((volatile u32*)(0x0050 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR_BASE ((volatile u32*)(0x0054 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR0 ((volatile u32*)(0x0054 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR1 ((volatile u32*)(0x0058 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR2 ((volatile u32*)(0x005C + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR3 ((volatile u32*)(0x0060 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR4 ((volatile u32*)(0x0064 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR5 ((volatile u32*)(0x0068 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR6 ((volatile u32*)(0x006C + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR7 ((volatile u32*)(0x0070 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR8 ((volatile u32*)(0x0074 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR9 ((volatile u32*)(0x0078 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR10 ((volatile u32*)(0x007C + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR11 ((volatile u32*)(0x0080 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR12 ((volatile u32*)(0x0084 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR13 ((volatile u32*)(0x0088 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR14 ((volatile u32*)(0x008C + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR15 ((volatile u32*)(0x0090 + IFX_MEI_SPACE_ACCESS)) ++#define IFX_MEI_XMEM_BAR16 ((volatile u32*)(0x0094 + IFX_MEI_SPACE_ACCESS)) ++ ++ ++ ++/***********************************************************************/ ++/* Module : SSC1 register address and bits */ ++/***********************************************************************/ ++ ++ ++/***********************************************************************/ ++/* Module : GPIO register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_GPIO (KSEG1 | 0x1E100B00) ++ ++#define IFX_GPIO_Pn_BASE(n) (IFX_GPIO + 0x0010 + 0x0030 * (n)) ++ ++/***Port 0 Data Output Register (0010H)***/ ++#define IFX_GPIO_P0_OUT ((volatile u32 *)(IFX_GPIO + 0x0010)) ++/***Port 1 Data Output Register (0040H)***/ ++#define IFX_GPIO_P1_OUT ((volatile u32 *)(IFX_GPIO + 0x0040)) ++/***Port 0 Data Input Register (0014H)***/ ++#define IFX_GPIO_P0_IN ((volatile u32 *)(IFX_GPIO + 0x0014)) ++/***Port 1 Data Input Register (0044H)***/ ++#define IFX_GPIO_P1_IN ((volatile u32 *)(IFX_GPIO + 0x0044)) ++/***Port 0 Direction Register (0018H)***/ ++#define IFX_GPIO_P0_DIR ((volatile u32 *)(IFX_GPIO + 0x0018)) ++/***Port 1 Direction Register (0048H)***/ ++#define IFX_GPIO_P1_DIR ((volatile u32 *)(IFX_GPIO + 0x0048)) ++/***Port 0 Alternate Function Select Register 0 (001C H) ***/ ++#define IFX_GPIO_P0_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x001C)) ++/***Port 1 Alternate Function Select Register 0 (004C H) ***/ ++#define IFX_GPIO_P1_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x004C)) ++/***Port 0 Alternate Function Select Register 1 (0020 H) ***/ ++#define IFX_GPIO_P0_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0020)) ++/***Port 1 Alternate Function Select Register 0 (0050 H) ***/ ++#define IFX_GPIO_P1_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0050)) ++/***Port 0 Open Drain Control Register (0024H)***/ ++#define IFX_GPIO_P0_OD ((volatile u32 *)(IFX_GPIO + 0x0024)) ++/***Port 1 Open Drain Control Register (0054H)***/ ++#define IFX_GPIO_P1_OD ((volatile u32 *)(IFX_GPIO + 0x0054)) ++/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/ ++#define IFX_GPIO_P0_STOFF ((volatile u32 *)(IFX_GPIO + 0x0028)) ++/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/ ++#define IFX_GPIO_P1_STOFF ((volatile u32 *)(IFX_GPIO + 0x0058)) ++/***Port 0 Pull Up/Pull Down Select Register (002C H)***/ ++#define IFX_GPIO_P0_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x002C)) ++/***Port 1 Pull Up/Pull Down Select Register (005C H)***/ ++#define IFX_GPIO_P1_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x005C)) ++/***Port 0 Pull Up Device Enable Register (0030 H)***/ ++#define IFX_GPIO_P0_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0030)) ++/***Port 1 Pull Up Device Enable Register (0060 H)***/ ++#define IFX_GPIO_P1_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0060)) ++ ++ ++ ++/***********************************************************************/ ++/* Module : CGU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_CGU (KSEG1 | 0x1F103000) ++ ++/***CGU Clock PLL0 ***/ ++#define IFX_CGU_PLL0_CFG ((volatile u32*)(IFX_CGU + 0x0004)) ++/***CGU Clock PLL1 ***/ ++#define IFX_CGU_PLL1_CFG ((volatile u32*)(IFX_CGU + 0x0008)) ++/***CGU Clock PLL2 ***/ ++#define IFX_CGU_PLL2_CFG ((volatile u32*)(IFX_CGU + 0x000C)) ++/***CGU Clock SYS Mux Register***/ ++#define IFX_CGU_SYS ((volatile u32*)(IFX_CGU + 0x0010)) ++#define IFX_CGU_UPDATE ((volatile u32*)(IFX_CGU + 0x0014)) ++#define IFX_CGU_IF_CLK ((volatile u32*)(IFX_CGU + 0x0018)) ++#define IFX_CGU_OSC_CON ((volatile u32*)(IFX_CGU + 0x001C)) ++#define IFX_CGU_SMD ((volatile u32*)(IFX_CGU + 0x0020)) ++#define IFX_CGU_CT1SR ((volatile u32*)(IFX_CGU + 0x0028)) ++#define IFX_CGU_CT2SR ((volatile u32*)(IFX_CGU + 0x002C)) ++#define IFX_CGU_PCMCR ((volatile u32*)(IFX_CGU + 0x0030)) ++#define IFX_CGU_PCI_CR ((volatile u32*)(IFX_CGU + 0x0034)) ++#define IFX_CGU_PD_PC ((volatile u32*)(IFX_CGU + 0x0038)) ++#define IFX_CGU_FMR ((volatile u32*)(IFX_CGU + 0x003C)) ++ ++/* ++ * CGU PLL0 Configure Register ++ */ ++#define CGU_PLL0_PHASE_DIVIDER_ENABLE (*IFX_CGU_PLL0_CFG & (1 << 31)) ++#define CGU_PLL0_BYPASS (*IFX_CGU_PLL0_CFG & (1 << 30)) ++#define CGU_PLL0_SRC (*IFX_CGU_PLL0_CFG & (1 << 29)) ++#define CGU_PLL0_CFG_DSMSEL (*IFX_CGU_PLL0_CFG & (1 << 28)) ++#define CGU_PLL0_CFG_FRAC_EN (*IFX_CGU_PLL0_CFG & (1 << 27)) ++#define CGU_PLL0_CFG_PLLK GET_BITS(*IFX_CGU_PLL0_CFG, 26, 17) ++//#define CGU_PLL0_CFG_PLLD GET_BITS(*IFX_CGU_PLL0_CFG, 16, 13) ++#define CGU_PLL0_CFG_PLLN GET_BITS(*IFX_CGU_PLL0_CFG, 12, 6) ++#define CGU_PLL0_CFG_PLLM GET_BITS(*IFX_CGU_PLL0_CFG, 5, 2) ++#define CGU_PLL0_CFG_PLLL (*IFX_CGU_PLL0_CFG & (1 << 1)) ++#define CGU_PLL0_CFG_PLLEN (*IFX_CGU_PLL0_CFG & (1 << 0)) ++ ++/* ++ * CGU PLL1 Configure Register ++ */ ++#define CGU_PLL1_SRC (*IFX_CGU_PLL1_CFG & (1 << 31)) ++#define CGU_PLL1_BYPASS (*IFX_CGU_PLL1_CFG & (1 << 30)) ++#define CGU_PLL1_CFG_CTEN (*IFX_CGU_PLL1_CFG & (1 << 29)) ++#define CGU_PLL1_CFG_DSMSEL (*IFX_CGU_PLL1_CFG & (1 << 28)) ++#define CGU_PLL1_CFG_FRAC_EN (*IFX_CGU_PLL1_CFG & (1 << 27)) ++#define CGU_PLL1_CFG_PLLK GET_BITS(*IFX_CGU_PLL1_CFG, 26, 17) ++//#define CGU_PLL1_CFG_PLLD GET_BITS(*IFX_CGU_PLL1_CFG, 16, 13) ++#define CGU_PLL1_CFG_PLLN GET_BITS(*IFX_CGU_PLL1_CFG, 12, 6) ++#define CGU_PLL1_CFG_PLLM GET_BITS(*IFX_CGU_PLL1_CFG, 5, 2) ++#define CGU_PLL1_CFG_PLLL (*IFX_CGU_PLL1_CFG & (1 << 1)) ++#define CGU_PLL1_CFG_PLLEN (*IFX_CGU_PLL1_CFG & (1 << 0)) ++ ++/* ++ * CGU PLL2 Configure/Status Register ++ */ ++//#define CGU_PLL2_PHASE_DIVIDER_ENABLE (*IFX_CGU_PLL2_CFG & (1 << 31)) // Write bit 31, Read from bit 20 ++#define CGU_PLL2_PHASE_DIVIDER_ENABLE (*IFX_CGU_PLL2_CFG & (1 << 20)) ++#define CGU_PLL2_BYPASS (*IFX_CGU_PLL2_CFG & (1 << 19)) ++#define CGU_PLL2_SRC GET_BITS(*IFX_CGU_PLL2_CFG, 18, 17) ++#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(*IFX_CGU_PLL2_CFG, 16, 13) ++#define CGU_PLL2_CFG_PLLN GET_BITS(*IFX_CGU_PLL2_CFG, 12, 6) ++#define CGU_PLL2_CFG_PLLM GET_BITS(*IFX_CGU_PLL2_CFG, 5, 2) ++#define CGU_PLL2_CFG_PLLL (*IFX_CGU_PLL2_CFG & (1 << 1)) ++#define CGU_PLL2_CFG_PLLEN (*IFX_CGU_PLL2_CFG & (1 << 0)) ++ ++/* ++ * CGU Clock Sys Mux Register ++ */ ++#define CGU_SYS_PPESEL GET_BITS(*IFX_CGU_SYS, 8, 7) ++#define CGU_SYS_FPI_SEL (*IFX_CGU_SYS & (1 << 6)) ++#define CGU_SYS_CPU1SEL GET_BITS(*IFX_CGU_SYS, 5, 4) ++#define CGU_SYS_CPU0SEL GET_BITS(*IFX_CGU_SYS, 3, 2) ++#define CGU_SYS_DDR_SEL GET_BITS(*IFX_CGU_SYS, 1, 0) ++ ++/* ++ * CGU Update Register ++ */ ++#define CGU_UPDATE_UPDATE (*IFX_CGU_UPDATE & (1 << 0)) ++ ++/* ++ * CGU Interface Clock Register ++ */ ++#define CGU_IF_CLK_O_RMII1 (*IFX_CGU_IF_CLK & (1 << 25)) ++#define CGU_IF_CLK_O_RMII0 (*IFX_CGU_IF_CLK & (1 << 24)) ++#define CGU_IF_CLK_PCI_CLK GET_BITS(*IFX_CGU_IF_CLK, 23, 20) ++#define CGU_IF_CLK_PDA (*IFX_CGU_IF_CLK & (1 << 19)) ++#define CGU_IF_CLK_PCI_B (*IFX_CGU_IF_CLK & (1 << 18)) ++#define CGU_IF_CLK_PCIBM (*IFX_CGU_IF_CLK & (1 << 17)) ++#define CGU_IF_CLK_PCIS (*IFX_CGU_IF_CLK & (1 << 16)) ++#define CGU_IF_CLK_CLKOD0 GET_BITS(*IFX_CGU_IF_CLK, 15, 14) ++#define CGU_IF_CLK_CLKOD1 GET_BITS(*IFX_CGU_IF_CLK, 13, 12) ++#define CGU_IF_CLK_CLKOD2 GET_BITS(*IFX_CGU_IF_CLK, 11, 10) ++#define CGU_IF_CLK_CLKOD3 GET_BITS(*IFX_CGU_IF_CLK, 9, 8) ++//#define CGU_IF_CLK_PPESEL GET_BITS(*IFX_CGU_IF_CLK, 7, 6) ++#define CGU_IF_CLK_USBSEL GET_BITS(*IFX_CGU_IF_CLK, 5, 4) ++#define CGU_IF_CLK_MDCSEL GET_BITS(*IFX_CGU_IF_CLK, 3, 2) ++#define CGU_IF_CLK_MIISEL GET_BITS(*IFX_CGU_IF_CLK, 1, 0) ++ ++/* ++ * CGU SDRAM Memory Delay Register ++ */ ++//#define CGU_SMD_CLKI (*IFX_CGU_SMD & (1 << 31)) ++#define CGU_SMD_CLK_IN_S (*IFX_CGU_SMD & (1 << 22)) ++#define CGU_SMD_DDR_PRG (*IFX_CGU_SMD & (1 << 21)) ++#define CGU_SMD_DDR_CQ (*IFX_CGU_SMD & (1 << 20)) ++#define CGU_SMD_DDR_EQ (*IFX_CGU_SMD & (1 << 19)) ++#define CGU_SMD_SDR_CLKS (*IFX_CGU_SMD & (1 << 18)) ++#define CGU_SMD_MIDS GET_BITS(*IFX_CGU_SMD, 17, 12) ++#define CGU_SMD_MODS GET_BITS(*IFX_CGU_SMD, 11, 6) ++#define CGU_SMD_MDSEL GET_BITS(*IFX_CGU_SMD, 5, 0) ++ ++/* ++ * CGU CT Status Register 1 ++ */ ++#define CGU_CT1SR_PDOUT GET_BITS(*IFX_CGU_CT1SR, 14, 0) ++ ++/* ++ * CGU CT Status Register 2 ++ */ ++#define CGU_CT1SR_PLL1K GET_BITS(*IFX_CGU_CT2SR, 9, 0) ++ ++/* ++ * CGU PCM Control Register ++ */ ++#define CGU_PCMCR_DCL1 GET_BITS(*IFX_CGU_PCMCR, 27, 25) ++#define CGU_PCMCR_MUXDCL (*IFX_CGU_MUXDCL & (1 << 22)) ++#define CGU_PCMCR_MUXFSC (*IFX_CGU_MUXDCL & (1 << 18)) ++#define CGU_PCMCR_PCM_SL (*IFX_CGU_MUXDCL & (1 << 13)) ++#define CGU_PCMCR_DNTR GET_BITS(*IFX_CGU_PCMCR, 12, 11) ++#define CGU_PCMCR_NTRS (*IFX_CGU_MUXDCL & (1 << 10)) ++#define CGU_PCMCR_AC97_EN (*IFX_CGU_MUXDCL & (1 << 9)) ++#define CGU_PCMCR_CTTMUX (*IFX_CGU_MUXDCL & (1 << 8)) ++ ++/* ++ * PCI Clock Control Register ++ */ ++#define CGU_PCI_CR_PADSEL (*IFX_CGU_PCI_CR & (1 << 31)) ++#define CGU_PCI_CR_RESSEL (*IFX_CGU_PCI_CR & (1 << 30)) ++#define CGU_PCI_CR_PCID_H GET_BITS(*IFX_CGU_PCI_CR, 23, 21) ++#define CGU_PCI_CR_PCID_L GET_BITS(*IFX_CGU_PCI_CR, 20, 18) ++ ++#define IFX_PCI_CLK_SHIFT 20 ++#define IFX_PCI_CLK_MASK (0xF << IFX_PCI_CLK_SHIFT) ++#define IFX_PCI_33MHZ (8 << IFX_PCI_CLK_SHIFT) ++#define IFX_PCI_60MHZ (4 << IFX_PCI_CLK_SHIFT) ++#define IFX_PCI_INTERNAL_CLK_SRC 0x00010000 /* Internal means output */ ++ ++#define IFX_PCI_CLK_FROM_CGU 0x80000000 ++#define IFX_PCI_CLK_RESET_FROM_CGU 0x40000000 ++#define IFX_PCI_DELAY_SHIFT 21 ++#define IFX_PCI_DELAY_MASK (0x7 << IFX_PCI_DELAY_SHIFT) ++ ++/***********************************************************************/ ++/* Module : MCD register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_MCD (KSEG1 | 0x1F106000) ++ ++/***Manufacturer Identification Register***/ ++#define IFX_MCD_MANID ((volatile u32*)(IFX_MCD + 0x0024)) ++#define IFX_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5) ++ ++/***Chip Identification Register***/ ++#define IFX_MCD_CHIPID ((volatile u32*)(IFX_MCD + 0x0028)) ++#define IFX_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & 0xF) ++#define IFX_MCD_CHIPID_VERSION_SET(value) (((value) & 0xF) << 28) ++#define IFX_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & 0xFFFF) ++#define IFX_MCD_CHIPID_PART_NUMBER_SET(value) (((value) & 0xFFFF) << 12) ++#define IFX_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & 0x7FF) ++#define IFX_MCD_CHIPID_MANID_SET(value) (((value) & 0x7FF) << 1) ++ ++#define IFX_CHIPID_STANDARD 0x00EB ++#define IFX_CHIPID_YANGTSE 0x00ED ++ ++/***Redesign Tracing Identification Register***/ ++#define IFX_MCD_RTID ((volatile u32*)(IFX_MCD + 0x002C)) ++#define IFX_MCD_RTID_LC (1 << 15) ++#define IFX_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0) ++ ++ ++ ++/***********************************************************************/ ++/* Module : EBU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_EBU (KSEG1 | 0x1E105300) ++ ++/***EBU Clock Control Register***/ ++#define IFX_EBU_CLC ((volatile u32*)(IFX_EBU + 0x0000)) ++#define IFX_EBU_CLC_DISS (1 << 1) ++#define IFX_EBU_CLC_DISR (1 << 0) ++ ++/***EBU Global Control Register***/ ++#define IFX_EBU_CON ((volatile u32*)(IFX_EBU + 0x0010)) ++#define IFX_EBU_CON_DTACS(value) (((( 1 << 3) - 1) & (value)) << 20) ++#define IFX_EBU_CON_DTARW(value) (((( 1 << 3) - 1) & (value)) << 16) ++#define IFX_EBU_CON_TOUTC(value) (((( 1 << 8) - 1) & (value)) << 8) ++#define IFX_EBU_CON_ARBMODE(value) (((( 1 << 2) - 1) & (value)) << 6) ++#define IFX_EBU_CON_ARBSYNC (1 << 5) ++#define IFX_EBU_CON_1 (1 << 3) ++ ++#define IFX_EBU_ADDR_SEL_EN 1 ++ ++/***EBU Address Select Register 0***/ ++#define IFX_EBU_ADDSEL0 ((volatile u32*)(IFX_EBU + 0x0020)) ++#define IFX_EBU_ADDSEL0_BASE (KSEG1 + 0x10000000) ++#define IFX_EBU_ADDR_SEL0 IFX_EBU_ADDSEL0 ++ ++/***EBU Address Select Register 1***/ ++#define IFX_EBU_ADDSEL1 ((volatile u32*)(IFX_EBU + 0x0024)) ++#define IFX_EBU_ADDSEL1_BASE (KSEG1 + 0x14000000) ++#define IFX_EBU_ADDSEL1_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_EBU_ADDSEL1_MIRRORE (1 << 1) ++#define IFX_EBU_ADDSEL1_REGEN (1 << 0) ++ ++ ++/***EBU Address Select Register 2***/ ++#define IFX_EBU_ADDSEL2 ((volatile u32*)(IFX_EBU + 0x0028)) ++ ++/***EBU Address Select Register 3***/ ++#define IFX_EBU_ADDSEL3 ((volatile u32*)(IFX_EBU + 0x0028)) ++ ++/***EBU Bus Configuration Register 0***/ ++#define IFX_EBU_BUSCON0 ((volatile u32*)(IFX_EBU + 0x0060)) ++#define IFX_EBU_BUSCON0_CMULT 0x00000003 ++#define IFX_EBU_BUSCON0_CMULT_S 0 ++enum { ++ IFX_EBU_BUSCON0_CMULT1 = 0, ++ IFX_EBU_BUSCON0_CMULT4, ++ IFX_EBU_BUSCON0_CMULT8, ++ IFX_EBU_BUSCON0_CMULT16, /* Default after reset */ ++}; ++ ++#define IFX_EBU_BUSCON0_RECOVC 0x00000000c ++#define IFX_EBU_BUSCON0_RECOVC_S 2 ++enum { ++ IFX_EBU_BUSCON0_RECOVC0 = 0, ++ IFX_EBU_BUSCON0_RECOVC1, ++ IFX_EBU_BUSCON0_RECOVC2, ++ IFX_EBU_BUSCON0_RECOVC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON0_HOLDC 0x00000030 ++#define IFX_EBU_BUSCON0_HOLDC_S 4 ++enum { ++ IFX_EBU_BUSCON0_HOLDC0 = 0, ++ IFX_EBU_BUSCON0_HOLDC1, ++ IFX_EBU_BUSCON0_HOLDC2, ++ IFX_EBU_BUSCON0_HOLDC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON0_WAITRDC 0x000000c0 ++#define IFX_EBU_BUSCON0_WAITRDC_S 6 ++enum { ++ IFX_EBU_BUSCON0_WAITRDC0 = 0, ++ IFX_EBU_BUSCON0_WAITRDC1, ++ IFX_EBU_BUSCON0_WAITRDC2, ++ IFX_EBU_BUSCON0_WAITRDC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON0_WAITWRC 0x00000700 ++#define IFX_EBU_BUSCON0_WAITWRC_S 8 ++enum { ++ IFX_EBU_BUSCON0_WAITWRC0 = 0, ++ IFX_EBU_BUSCON0_WAITWRC1, ++ IFX_EBU_BUSCON0_WAITWRC2, ++ IFX_EBU_BUSCON0_WAITWRC3, ++ IFX_EBU_BUSCON0_WAITWRC4, ++ IFX_EBU_BUSCON0_WAITWRC5, ++ IFX_EBU_BUSCON0_WAITWRC6, ++ IFX_EBU_BUSCON0_WAITWRC7, /* Default */ ++}; ++ ++#define IFX_EBU_BUSCON0_BCGEN 0x00003000 ++#define IFX_EBU_BUSCON0_BCGEN_S 12 ++enum { ++ IFX_EBU_BUSCON0_BCGEN_CS = 0, ++ IFX_EBU_BUSCON0_BCGEN_INTEL, /* Default */ ++ IFX_EBU_BUSCON0_BCGEN_MOTOROLA, ++ IFX_EBU_BUSCON0_BCGEN_RES, ++}; ++ ++#define IFX_EBU_BUSCON0_ALEC 0x0000c000 ++#define IFX_EBU_BUSCON0_ALEC_S 14 ++enum { ++ IFX_EBU_BUSCON0_ALEC0 = 0, ++ IFX_EBU_BUSCON0_ALEC1, ++ IFX_EBU_BUSCON0_ALEC2, ++ IFX_EBU_BUSCON0_ALEC3, /* Default */ ++}; ++ ++#define IFX_EBU_BUSCON0_XDM 0x00030000 ++#define IFX_EBU_BUSCON0_XDM_S 16 ++enum { ++ IFX_EBU_BUSCON0_XDM8 = 0, ++ IFX_EBU_BUSCON0_XDM16, /* Default */ ++}; ++ ++#define IFX_EBU_BUSCON0_VN_EN 0x00040000 ++ ++#define IFX_EBU_BUSCON0_WAITINV_HI 0x00080000 /* low by default */ ++ ++#define IFX_EBU_BUSCON0_WAIT 0x00300000 ++#define IFX_EBU_BUSCON0_WAIT_S 20 ++enum { ++ IFX_EBU_BUSCON0_WAIT_DISABLE = 0, ++ IFX_EBU_BUSCON0_WAIT_ASYNC, ++ IFX_EBU_BUSCON0_WAIT_SYNC, ++}; ++#define IFX_EBU_BUSCON0_SETUP_EN 0x00400000 /* Disable by default */ ++ ++#define IFX_EBU_BUSCON0_AGEN 0x07000000 ++#define IFX_EBU_BUSCON0_AGEN_S 24 ++enum { ++ IFX_EBU_BUSCON0_AGEN_DEMUX = 0, /* Default */ ++ IFX_EBU_BUSCON0_AGEN_RES, ++ IFX_EBU_BUSCON0_AGEN_MUX, ++}; ++ ++#define IFX_EBU_BUSCON0_ADSWP 0x40000000 /* Disable by default */ ++#define IFX_EBU_BUSCON0_WRDIS 0x80000000 /* Disable by default */ ++ ++/***EBU Bus Configuration Register 1***/ ++#define IFX_EBU_BUSCON1 ((volatile u32*)(IFX_EBU + 0x0064)) ++#define IFX_EBU_BUSCON1_CMULT 0x00000003 ++#define IFX_EBU_BUSCON1_CMULT_S 0 ++enum { ++ IFX_EBU_BUSCON1_CMULT1 = 0, ++ IFX_EBU_BUSCON1_CMULT4, ++ IFX_EBU_BUSCON1_CMULT8, ++ IFX_EBU_BUSCON1_CMULT16, /* Default after reset */ ++}; ++ ++#define IFX_EBU_BUSCON1_RECOVC 0x00000000c ++#define IFX_EBU_BUSCON1_RECOVC_S 2 ++enum { ++ IFX_EBU_BUSCON1_RECOVC0 = 0, ++ IFX_EBU_BUSCON1_RECOVC1, ++ IFX_EBU_BUSCON1_RECOVC2, ++ IFX_EBU_BUSCON1_RECOVC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON1_HOLDC 0x00000030 ++#define IFX_EBU_BUSCON1_HOLDC_S 4 ++enum { ++ IFX_EBU_BUSCON1_HOLDC0 = 0, ++ IFX_EBU_BUSCON1_HOLDC1, ++ IFX_EBU_BUSCON1_HOLDC2, ++ IFX_EBU_BUSCON1_HOLDC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON1_WAITRDC 0x000000c0 ++#define IFX_EBU_BUSCON1_WAITRDC_S 6 ++enum { ++ IFX_EBU_BUSCON1_WAITRDC0 = 0, ++ IFX_EBU_BUSCON1_WAITRDC1, ++ IFX_EBU_BUSCON1_WAITRDC2, ++ IFX_EBU_BUSCON1_WAITRDC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON1_WAITWRC 0x00000700 ++#define IFX_EBU_BUSCON1_WAITWRC_S 8 ++enum { ++ IFX_EBU_BUSCON1_WAITWRC0 = 0, ++ IFX_EBU_BUSCON1_WAITWRC1, ++ IFX_EBU_BUSCON1_WAITWRC2, ++ IFX_EBU_BUSCON1_WAITWRC3, ++ IFX_EBU_BUSCON1_WAITWRC4, ++ IFX_EBU_BUSCON1_WAITWRC5, ++ IFX_EBU_BUSCON1_WAITWRC6, ++ IFX_EBU_BUSCON1_WAITWRC7, /* Default */ ++}; ++#define IFX_EBU_BUSCON1_BCGEN 0x00003000 ++#define IFX_EBU_BUSCON1_BCGEN_S 12 ++enum { ++ IFX_EBU_BUSCON1_BCGEN_CS = 0, ++ IFX_EBU_BUSCON1_BCGEN_INTEL, /* Default */ ++ IFX_EBU_BUSCON1_BCGEN_MOTOROLA, ++ IFX_EBU_BUSCON1_BCGEN_RES, ++}; ++ ++#define IFX_EBU_BUSCON1_ALEC 0x0000c000 ++#define IFX_EBU_BUSCON1_ALEC_S 14 ++enum { ++ IFX_EBU_BUSCON1_ALEC0 = 0, ++ IFX_EBU_BUSCON1_ALEC1, ++ IFX_EBU_BUSCON1_ALEC2, ++ IFX_EBU_BUSCON1_ALEC3, /* Default */ ++}; ++ ++#define IFX_EBU_BUSCON1_SETUP (1 << 22) ++/***EBU Bus Configuration Register 2***/ ++#define IFX_EBU_BUSCON2 ((volatile u32*)(IFX_EBU + 0x0068)) ++ ++#define IFX_EBU_ADDRSEL_SHIFT 4 ++#define IFX_EBU_ADDRSEL_MASK 0xF ++#define IFX_EBU_ADDRSEL_MASK_SET(value) ((value & BSP_EBU_ADDRSEL_MASK) << BSP_EBU_ADDRSEL_SHIFT) ++ ++#define IFX_EBU_BUSCON_WRDIS (1 << 31) ++#define IFX_EBU_BUSCON_ADSWP (1 << 30) ++#define IFX_EBU_BUSCON_AGEN_SHIFT 24 ++#define IFX_EBU_BUSCON_AGEN_MASK 7 ++#define IFX_EBU_BUSCON_SETUP (1 << 22) ++#define IFX_EBU_BUSCON_WAIT_SHIFT 20 ++#define IFX_EBU_BUSCON_WAIT_MASK 3 ++#define IFX_EBU_BUSCON_ACTIVE_WAIT_LEVEL (1 << 19) ++#define IFX_EBU_BUSCON_DATA_WIDTH_SHIFT 16 ++#define IFX_EBU_BUSCON_DATA_WIDTH_MASK 3 ++#define IFX_EBU_BUSCON_ALE_DUR_SHIFT 14 ++#define IFX_EBU_BUSCON_ALE_DUR_MASK 3 ++#define IFX_EBU_BUSCON_BCGEN_SHIFT 12 ++#define IFX_EBU_BUSCON_BCGEN_MASK 3 ++#define IFX_EBU_BUSCON_WAITWRC_SHIFT 8 ++#define IFX_EBU_BUSCON_WAITWRC_MASK 7 ++#define IFX_EBU_BUSCON_WAITRDC_SHIFT 6 ++#define IFX_EBU_BUSCON_WAITRDC_MASK 3 ++#define IFX_EBU_BUSCON_HOLDC_SHIFT 4 ++#define IFX_EBU_BUSCON_HOLDC_MASK 3 ++#define IFX_EBU_BUSCON_RECOVC_SHIFT 2 ++#define IFX_EBU_BUSCON_RECOVC_MASK 3 ++#define IFX_EBU_BUSCON_CMULT_SHIFT 0 ++#define IFX_EBU_BUSCON_CMULT_MASK 3 ++ ++#define IFX_EBU_BUSCON_AGEN(value) ((value & IFX_EBU_BUSCON_AGEN_MASK) << IFX_EBU_BUSCON_AGEN_SHIFT) ++#define IFX_EBU_BUSCON_WAIT(value) ((value & IFX_EBU_BUSCON_WAIT_MASK) << IFX_EBU_BUSCON_WAIT_SHIFT) ++#define IFX_EBU_BUSCON_DATA_WIDTH(value) ((value & IFX_EBU_BUSCON_DATA_WIDTH_MASK) << IFX_EBU_BUSCON_DATA_WIDTH_SHIFT) ++#define IFX_EBU_BUSCON_ALEC(value) ((value & IFX_EBU_BUSCON_ALE_DUR_MASK) << IFX_EBU_BUSCON_ALE_DUR_SHIFT) ++#define IFX_EBU_BUSCON_BCGEN(value) ((value & IFX_EBU_BUSCON_BCGEN_MASK) << IFX_EBU_BUSCON_BCGEN_SHIFT) ++#define IFX_EBU_BUSCON_WR_WAIT(value) ((value & IFX_EBU_BUSCON_WAITWRC_MASK) << IFX_EBU_BUSCON_WAITWRC_SHIFT) ++#define IFX_EBU_BUSCON_RD_WAIT(value) ((value & IFX_EBU_BUSCON_WAITRDC_MASK) << IFX_EBU_BUSCON_WAITRDC_SHIFT) ++#define IFX_EBU_BUSCON_HOLD(value) ((value & IFX_EBU_BUSCON_HOLDC_MASK) << IFX_EBU_BUSCON_HOLDC_SHIFT) ++#define IFX_EBU_BUSCON_RECOV(value) ((value & IFX_EBU_BUSCON_RECOVC_MASK) << IFX_EBU_BUSCON_RECOVC_SHIFT) ++#define IFX_EBU_BUSCON_CMULT(value) ((value & IFX_EBU_BUSCON_CMULT_MASK) << IFX_EBU_BUSCON_CMULT_SHIFT) ++ ++#define IFX_EBU_PCC_CON ((volatile u32*)(IFX_EBU + 0x0090)) ++#define IFX_EBU_PCC_CON_PCCARD_ON 0x00000001 ++#define IFX_EBU_PCC_CON_IREQ_RISING_EDGE 0x00000002 ++#define IFX_EBU_PCC_CON_IREQ_FALLING_EDGE 0x00000004 ++#define IFX_EBU_PCC_CON_IREQ_BOTH_EDGE 0x00000006 ++#define IFX_EBU_PCC_CON_IREQ_DIS 0x00000008 ++#define IFX_EBU_PCC_CON_IREQ_HIGH_LEVEL_DETECT 0x0000000A ++#define IFX_EBU_PCC_CON_IREQ_LOW_LEVEL_DETECT 0x0000000C ++ ++#define IFX_EBU_PCC_STAT ((volatile u32*)(IFX_EBU + 0x0094)) ++#define IFX_EBU_PCC_ISTAT ((volatile u32*)(IFX_EBU + 0x00A0)) ++#define IFX_EBU_PCC_IEN ((volatile u32*)(IFX_EBU + 0x00A4)) ++#define IFX_EBU_PCC_IEN_PCI_EN 0x00000010 ++ ++#define IFX_EBU_NAND_CON ((volatile u32*)(IFX_EBU + 0xB0)) ++#define IFX_EBU_NAND_CON_NANDM (1<<0) ++#define IFX_EBU_NAND_CON_NANDM_S 0 ++enum { ++ IFX_EBU_NAND_CON_NANDM_DISABLE = 0,/* Default after reset */ ++ IFX_EBU_NAND_CON_NANDM_ENABLE, ++ }; ++ ++#define IFX_EBU_NAND_CON_CSMUX_E (1<<1) ++#define IFX_EBU_NAND_CON_CSMUX_E_S 1 ++enum { ++ IFX_EBU_NAND_CON_CSMUX_E_DISABLE = 0,/* Default after reset */ ++ IFX_EBU_NAND_CON_CSMUX_E_ENABLE, ++ }; ++ ++#define IFX_EBU_NAND_CON_CS_P (1<<4) ++#define IFX_EBU_NAND_CON_CS_P_S 4 ++enum { ++ IFX_EBU_NAND_CON_CS_P_HIGH = 0, ++ IFX_EBU_NAND_CON_CS_P_LOW, /* Default after reset */ ++ }; ++ ++#define IFX_EBU_NAND_CON_SE_P (1<<5) ++#define IFX_EBU_NAND_CON_SE_P_S 5 ++enum { ++ IFX_EBU_NAND_CON_SE_P_HIGH = 0, ++ IFX_EBU_NAND_CON_SE_P_LOW, /* Default after reset */ ++ }; ++ ++#define IFX_EBU_NAND_CON_WP_P (1<<6) ++#define IFX_EBU_NAND_CON_WP_P_S 6 ++enum { ++ IFX_EBU_NAND_CON_WP_P_HIGH = 0, ++ IFX_EBU_NAND_CON_WP_P_LOW, /* Default after reset */ ++ }; ++ ++#define IFX_EBU_NAND_CON_PRE_P (1<<7) ++#define IFX_EBU_NAND_CON_PRE_P_S 7 ++enum { ++ IFX_EBU_NAND_CON_PRE_P_HIGH = 0, ++ IFX_EBU_NAND_CON_PRE_P_LOW, /* Default after reset */ ++ }; ++ ++#define IFX_EBU_NAND_CON_IN_CS (3<<8) ++#define IFX_EBU_NAND_CON_IN_CS_S 8 ++enum { ++ IFX_EBU_NAND_CON_IN_CS0 = 0, /* Default after reset */ ++ IFX_EBU_NAND_CON_IN_CS1, ++ }; ++ ++#define IFX_EBU_NAND_CON_OUT_CS (3<<10) ++#define IFX_EBU_NAND_CON_OUT_CS_S 10 ++enum { ++ IFX_EBU_NAND_CON_OUT_CS0 = 0, /* Default after reset */ ++ IFX_EBU_NAND_CON_OUT_CS1, ++ }; ++ ++ ++#define IFX_EBU_NAND_WAIT ((volatile u32*)(IFX_EBU + 0xB4)) ++#define IFX_EBU_NAND_WAIT_RD (1<<0) ++#define IFX_EBU_NAND_WAIT_BY_E (1<<1) ++#define IFX_EBU_NAND_WAIT_RD_E (1<<2) ++#define IFX_EBU_NAND_WAIT_WR_C (1<<3) ++ ++#define IFX_EBU_NAND_ECC0 ((volatile u32*)(IFX_EBU + 0xB8)) ++#define IFX_EBU_NAND_ECC_AC ((volatile u32*)(IFX_EBU + 0xBC)) ++ ++#define IFX_EBU_NAND_ECC_ON (1 << 31) ++#define IFX_EBU_NAND_LATCH_EN_SHIFT 18 ++#define IFX_EBU_NAND_LATCH_EN_MASK 0x3F ++#define IFX_EBU_NAND_OUT_CS_SHIFT 10 ++#define IFX_EBU_NAND_OUT_CS_MASK 3 ++#define IFX_EBU_NAND_IN_CS_SHIFT 8 ++#define IFX_EBU_NAND_IN_CS_MASK 3 ++#define IFX_EBU_NAND_PRE_P (1 << 7) ++#define IFX_EBU_NAND_WP_P (1 << 6) ++#define IFX_EBU_NAND_SE_P (1 << 5) ++#define IFX_EBU_NAND_CS_P (1 << 4) ++#define IFX_EBU_NAND_CLE_P (1 << 3) ++#define IFX_EBU_NAND_ALE_P (1 << 2) ++#define IFX_EBU_NAND_CSMUX_E (1 << 1) ++#define IFX_EBU_NAND_NANDM 1 ++ ++#define IFX_EBU_NAND_LATCH_EN(value) ((value & IFX_EBU_NAND_LATCH_EN_MASK) << IFX_EBU_NAND_LATCH_EN_SHIFT) ++#define IFX_EBU_NAND_OUT_CS(value) ((value & IFX_EBU_NAND_OUT_CS_MASK) << IFX_EBU_NAND_OUT_CS_SHIFT) ++#define IFX_EBU_NAND_IN_CS(value) ((value & IFX_EBU_NAND_IN_CS_MASK) << IFX_EBU_NAND_IN_CS_SHIFT) ++#define IFX_EBU_NAND_LATCH_PRE_P (1 << 23) ++#define IFX_EBU_NAND_LATCH_WP_P (1 << 22) ++#define IFX_EBU_NAND_LATCH_SE_P (1 << 21) ++#define IFX_EBU_NAND_LATCH_CS_P (1 << 20) ++#define IFX_EBU_NAND_LATCH_CLE_P (1 << 19) ++#define IFX_EBU_NAND_LATCH_ALE_P (1 << 18) ++ ++ ++ ++/***********************************************************************/ ++/* Module : SDRAM register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_SDRAM (KSEG1 | 0x1F800000) ++ ++/***MC Access Error Cause Register***/ ++#define IFX_SDRAM_MC_ERRCAUSE ((volatile u32*)(IFX_SDRAM + 0x0100)) ++#define IFX_SDRAM_MC_ERRCAUSE_ERR (1 << 31) ++#define IFX_SDRAM_MC_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16) ++#define IFX_SDRAM_MC_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_ERRCAUSE_Res(value) (((( 1 << NaN) - 1) & (value)) << NaN) ++ ++/***MC Access Error Address Register***/ ++#define IFX_SDRAM_MC_ERRADDR ((volatile u32*)(IFX_SDRAM + 0x0108)) ++ ++/***MC I/O General Purpose Register***/ ++#define IFX_SDRAM_MC_IOGP ((volatile u32*)(IFX_SDRAM + 0x0800)) ++#define IFX_SDRAM_MC_IOGP_GPR6(value) (((( 1 << 4) - 1) & (value)) << 28) ++#define IFX_SDRAM_MC_IOGP_GPR5(value) (((( 1 << 4) - 1) & (value)) << 24) ++#define IFX_SDRAM_MC_IOGP_GPR4(value) (((( 1 << 4) - 1) & (value)) << 20) ++#define IFX_SDRAM_MC_IOGP_GPR3(value) (((( 1 << 4) - 1) & (value)) << 16) ++#define IFX_SDRAM_MC_IOGP_GPR2(value) (((( 1 << 4) - 1) & (value)) << 12) ++#define IFX_SDRAM_MC_IOGP_CPS (1 << 11) ++#define IFX_SDRAM_MC_IOGP_CLKDELAY(value) (((( 1 << 3) - 1) & (value)) << 8) ++#define IFX_SDRAM_MC_IOGP_CLKRAT(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_IOGP_RDDEL(value) (((( 1 << 4) - 1) & (value)) << 0) ++ ++/***MC Self Refresh Register***/ ++#define IFX_SDRAM_MC_SELFRFSH ((volatile u32*)(IFX_SDRAM + 0x0A00)) ++#define IFX_SDRAM_MC_SELFRFSH_PWDS (1 << 1) ++#define IFX_SDRAM_MC_SELFRFSH_PWD (1 << 0) ++#define IFX_SDRAM_MC_SELFRFSH_Res(value) (((( 1 << 30) - 1) & (value)) << 2) ++ ++/***MC Enable Register***/ ++#define IFX_SDRAM_MC_CTRLENA ((volatile u32*)(IFX_SDRAM + 0x1000)) ++#define IFX_SDRAM_MC_CTRLENA_ENA (1 << 0) ++#define IFX_SDRAM_MC_CTRLENA_Res(value) (((( 1 << 31) - 1) & (value)) << 1) ++ ++/***MC Mode Register Setup Code***/ ++#define IFX_SDRAM_MC_MRSCODE ((volatile u32*)(IFX_SDRAM + 0x1008)) ++#define IFX_SDRAM_MC_MRSCODE_UMC(value) (((( 1 << 5) - 1) & (value)) << 7) ++#define IFX_SDRAM_MC_MRSCODE_CL(value) (((( 1 << 3) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_MRSCODE_WT (1 << 3) ++#define IFX_SDRAM_MC_MRSCODE_BL(value) (((( 1 << 3) - 1) & (value)) << 0) ++ ++/***MC Configuration Data-word Width Register***/ ++#define IFX_SDRAM_MC_CFGDW ((volatile u32*)(IFX_SDRAM + 0x1010)) ++#define IFX_SDRAM_MC_CFGDW_DW(value) (((( 1 << 4) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_CFGDW_Res(value) (((( 1 << 28) - 1) & (value)) << 4) ++ ++/***MC Configuration Physical Bank 0 Register***/ ++#define IFX_SDRAM_MC_CFGPB0 ((volatile u32*)(IFX_SDRAM + 0x1018)) ++#define IFX_SDRAM_MC_CFGPB0_MCSEN0(value) (((( 1 << 4) - 1) & (value)) << 12) ++#define IFX_SDRAM_MC_CFGPB0_BANKN0(value) (((( 1 << 4) - 1) & (value)) << 8) ++#define IFX_SDRAM_MC_CFGPB0_ROWW0(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_CFGPB0_COLW0(value) (((( 1 << 4) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_CFGPB0_Res(value) (((( 1 << 16) - 1) & (value)) << 16) ++ ++/***MC Latency Register***/ ++#define IFX_SDRAM_MC_LATENCY ((volatile u32*)(IFX_SDRAM + 0x1038)) ++#define IFX_SDRAM_MC_LATENCY_TRP(value) (((( 1 << 4) - 1) & (value)) << 16) ++#define IFX_SDRAM_MC_LATENCY_TRAS(value) (((( 1 << 4) - 1) & (value)) << 12) ++#define IFX_SDRAM_MC_LATENCY_TRCD(value) (((( 1 << 4) - 1) & (value)) << 8) ++#define IFX_SDRAM_MC_LATENCY_TDPL(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_LATENCY_TDAL(value) (((( 1 << 4) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_LATENCY_Res(value) (((( 1 << 12) - 1) & (value)) << 20) ++ ++/***MC Refresh Cycle Time Register***/ ++#define IFX_SDRAM_MC_TREFRESH ((volatile u32*)(IFX_SDRAM + 0x1040)) ++#define IFX_SDRAM_MC_TREFRESH_TREF(value) (((( 1 << 13) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_TREFRESH_Res(value) (((( 1 << 19) - 1) & (value)) << 13) ++ ++ ++ ++/***********************************************************************/ ++/* Module : GPTC register address and bits */ ++/***********************************************************************/ ++ ++/***********************************************************************/ ++/* Module : ASC0 register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_ASC0 (KSEG1 | 0x1E100400) ++ ++#define IFX_ASC0_TBUF ((volatile u32*)(IFX_ASC0 + 0x0020)) ++#define IFX_ASC0_RBUF ((volatile u32*)(IFX_ASC0 + 0x0024)) ++#define IFX_ASC0_FSTAT ((volatile u32*)(IFX_ASC0 + 0x0048)) ++#define IFX_ASC0_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) ++#define IFX_ASC0_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) ++#define IFX_ASC0_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) ++#define IFX_ASC0_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) ++#define IFX_ASC0_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) ++#define IFX_ASC0_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) ++#define IFX_ASC0_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) ++#define IFX_ASC0_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) ++ ++ ++ ++/***********************************************************************/ ++/* Module : ASC1 register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_ASC1 (KSEG1 | 0x1E100C00) ++ ++/***ASC Clock Control Register***/ ++#define IFX_ASC1_CLC ((volatile u32*)(IFX_ASC1+ 0x0000)) ++#define IFX_ASC1_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) ++#define IFX_ASC1_CLC_DISS (1 << 1) ++#define IFX_ASC1_CLC_DISR (1 << 0) ++ ++/***ASC Port Input Select Register***/ ++#define IFX_ASC1_PISEL ((volatile u32*)(IFX_ASC1+ 0x0004)) ++#define IFX_ASC1_PISEL ((volatile u32*)(IFX_ASC1+ 0x0004)) ++#define IFX_ASC1_PISEL_RIS (1 << 0) ++ ++/***ASC Control Register***/ ++#define IFX_ASC1_CON ((volatile u32*)(IFX_ASC1+ 0x0010)) ++#define IFX_ASC1_CON_BEN (1 << 20) ++#define IFX_ASC1_CON_TOEN (1 << 20) ++#define IFX_ASC1_CON_ROEN (1 << 19) ++#define IFX_ASC1_CON_RUEN (1 << 18) ++#define IFX_ASC1_CON_FEN (1 << 17) ++#define IFX_ASC1_CON_PAL (1 << 16) ++#define IFX_ASC1_CON_R (1 << 15) ++#define IFX_ASC1_CON_ACO (1 << 14) ++#define IFX_ASC1_CON_LB (1 << 13) ++#define IFX_ASC1_CON_ERCLK (1 << 10) ++#define IFX_ASC1_CON_FDE (1 << 9) ++#define IFX_ASC1_CON_BRS (1 << 8) ++#define IFX_ASC1_CON_STP (1 << 7) ++#define IFX_ASC1_CON_SP (1 << 6) ++#define IFX_ASC1_CON_ODD (1 << 5) ++#define IFX_ASC1_CON_PEN (1 << 4) ++#define IFX_ASC1_CON_M(value) (((( 1 << 3) - 1) & (value)) << 0) ++ ++/***ASC Staus Register***/ ++#define IFX_ASC1_STATE ((volatile u32*)(IFX_ASC1 + 0x0014)) ++/***ASC Write Hardware Modified Control Register***/ ++#define IFX_ASC1_WHBSTATE ((volatile u32*)(IFX_ASC1 + 0x0018)) ++#define IFX_ASC1_WHBSTATE_SETBE (1 << 113) ++#define IFX_ASC1_WHBSTATE_SETTOE (1 << 12) ++#define IFX_ASC1_WHBSTATE_SETROE (1 << 11) ++#define IFX_ASC1_WHBSTATE_SETRUE (1 << 10) ++#define IFX_ASC1_WHBSTATE_SETFE (1 << 19) ++#define IFX_ASC1_WHBSTATE_SETPE (1 << 18) ++#define IFX_ASC1_WHBSTATE_CLRBE (1 << 17) ++#define IFX_ASC1_WHBSTATE_CLRTOE (1 << 6) ++#define IFX_ASC1_WHBSTATE_CLRROE (1 << 5) ++#define IFX_ASC1_WHBSTATE_CLRRUE (1 << 4) ++#define IFX_ASC1_WHBSTATE_CLRFE (1 << 3) ++#define IFX_ASC1_WHBSTATE_CLRPE (1 << 2) ++#define IFX_ASC1_WHBSTATE_SETREN (1 << 1) ++#define IFX_ASC1_WHBSTATE_CLRREN (1 << 0) ++ ++/***ASC Baudrate Timer/Reload Register***/ ++#define IFX_ASC1_BG ((volatile u32*)(IFX_ASC1 + 0x0050)) ++#define IFX_ASC1_BG_BR_VALUE(value) (((( 1 << 13) - 1) & (value)) << 0) ++ ++/***ASC Fractional Divider Register***/ ++#define IFX_ASC1_FDV ((volatile u32*)(IFX_ASC1 + 0x0018)) ++#define IFX_ASC1_FDV_FD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) ++ ++/***ASC Transmit Buffer Register***/ ++#define IFX_ASC1_TBUF ((volatile u32*)(IFX_ASC1 + 0x0020)) ++#define IFX_ASC1_TBUF_TD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) ++ ++/***ASC Receive Buffer Register***/ ++#define IFX_ASC1_RBUF ((volatile u32*)(IFX_ASC1 + 0x0024)) ++#define IFX_ASC1_RBUF_RD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) ++ ++/***ASC Autobaud Control Register***/ ++#define IFX_ASC1_ABCON ((volatile u32*)(IFX_ASC1 + 0x0030)) ++#define IFX_ASC1_ABCON_RXINV (1 << 11) ++#define IFX_ASC1_ABCON_TXINV (1 << 10) ++#define IFX_ASC1_ABCON_ABEM(value) (((( 1 << 2) - 1) & (value)) << 8) ++#define IFX_ASC1_ABCON_FCDETEN (1 << 4) ++#define IFX_ASC1_ABCON_ABDETEN (1 << 3) ++#define IFX_ASC1_ABCON_ABSTEN (1 << 2) ++#define IFX_ASC1_ABCON_AUREN (1 << 1) ++#define IFX_ASC1_ABCON_ABEN (1 << 0) ++ ++/***Receive FIFO Control Register***/ ++#define IFX_ASC1_RXFCON ((volatile u32*)(IFX_ASC1 + 0x0040)) ++#define IFX_ASC1_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) ++#define IFX_ASC1_RXFCON_RXFFLU (1 << 1) ++#define IFX_ASC1_RXFCON_RXFEN (1 << 0) ++ ++/***Transmit FIFO Control Register***/ ++#define IFX_ASC1_TXFCON ((volatile u32*)(IFX_ASC1 + 0x0044)) ++#define IFX_ASC1_TXFCON_TXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) ++#define IFX_ASC1_TXFCON_TXFFLU (1 << 1) ++#define IFX_ASC1_TXFCON_TXFEN (1 << 0) ++ ++/***FIFO Status Register***/ ++#define IFX_ASC1_FSTAT ((volatile u32*)(IFX_ASC1 + 0x0048)) ++#define IFX_ASC1_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8) ++#define IFX_ASC1_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0) ++#define IFX_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) ++#define IFX_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) ++#define IFX_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) ++#define IFX_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) ++#define IFX_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) ++#define IFX_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) ++#define IFX_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) ++#define IFX_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) ++ ++ ++/***ASC Autobaud Status Register***/ ++#define IFX_ASC1_ABSTAT ((volatile u32*)(IFX_ASC1 + 0x0034)) ++#define IFX_ASC1_ABSTAT_DETWAIT (1 << 4) ++#define IFX_ASC1_ABSTAT_SCCDET (1 << 3) ++#define IFX_ASC1_ABSTAT_SCSDET (1 << 2) ++#define IFX_ASC1_ABSTAT_FCCDET (1 << 1) ++#define IFX_ASC1_ABSTAT_FCSDET (1 << 0) ++ ++/***ASC Write HW Modified Autobaud Status Register***/ ++#define IFX_ASC1_WHBABSTAT ((volatile u32*)(IFX_ASC1 + 0x003C)) ++#define IFX_ASC1_WHBABSTAT_SETDETWAIT (1 << 9) ++#define IFX_ASC1_WHBABSTAT_CLRDETWAIT (1 << 8) ++#define IFX_ASC1_WHBABSTAT_SETSCCDET (1 << 7) ++#define IFX_ASC1_WHBABSTAT_CLRSCCDET (1 << 6) ++#define IFX_ASC1_WHBABSTAT_SETSCSDET (1 << 5) ++#define IFX_ASC1_WHBABSTAT_CLRSCSDET (1 << 4) ++#define IFX_ASC1_WHBABSTAT_SETFCCDET (1 << 3) ++#define IFX_ASC1_WHBABSTAT_CLRFCCDET (1 << 2) ++#define IFX_ASC1_WHBABSTAT_SETFCSDET (1 << 1) ++#define IFX_ASC1_WHBABSTAT_CLRFCSDET (1 << 0) ++ ++/***ASC IRNCR0 **/ ++#define IFX_ASC1_IRNREN ((volatile u32*)(IFX_ASC1 + 0x00F4)) ++#define IFX_ASC1_IRNICR ((volatile u32*)(IFX_ASC1 + 0x00FC)) ++/***ASC IRNCR1 **/ ++#define IFX_ASC1_IRNCR ((volatile u32*)(IFX_ASC1 + 0x00F8)) ++#define IFX_ASC_IRNCR_TIR 0x1 ++#define IFX_ASC_IRNCR_RIR 0x2 ++#define IFX_ASC_IRNCR_EIR 0x4 ++ ++ ++ ++/***********************************************************************/ ++/* Module : DMA register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_DMA (KSEG1 | 0x1E104100) ++ ++#define IFX_DMA_BASE IFX_DMA ++#define IFX_DMA_CLC (volatile u32*)IFX_DMA_BASE ++#define IFX_DMA_ID (volatile u32*)(IFX_DMA_BASE+0x08) ++#define IFX_DMA_CTRL (volatile u32*)(IFX_DMA_BASE+0x10) ++#define IFX_DMA_CPOLL (volatile u32*)(IFX_DMA_BASE+0x14) ++#define IFX_DMA_CS (volatile u32*)(IFX_DMA_BASE+0x18) ++#define IFX_DMA_CCTRL (volatile u32*)(IFX_DMA_BASE+0x1C) ++#define IFX_DMA_CDBA (volatile u32*)(IFX_DMA_BASE+0x20) ++#define IFX_DMA_CDLEN (volatile u32*)(IFX_DMA_BASE+0x24) ++#define IFX_DMA_CIS (volatile u32*)(IFX_DMA_BASE+0x28) ++#define IFX_DMA_CIE (volatile u32*)(IFX_DMA_BASE+0x2C) ++ ++#define IFX_DMA_PS (volatile u32*)(IFX_DMA_BASE+0x40) ++#define IFX_DMA_PCTRL (volatile u32*)(IFX_DMA_BASE+0x44) ++ ++#define IFX_DMA_IRNEN (volatile u32*)(IFX_DMA_BASE+0xf4) ++#define IFX_DMA_IRNCR (volatile u32*)(IFX_DMA_BASE+0xf8) ++#define IFX_DMA_IRNICR (volatile u32*)(IFX_DMA_BASE+0xfc) ++ ++ ++ ++/***********************************************************************/ ++/* Module : Debug register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_Debug (KSEG1 | 0x1F106000) ++ ++/***MCD Break Bus Switch Register***/ ++#define IFX_Debug_MCD_BBS ((volatile u32*)(IFX_Debug + 0x0000)) ++#define IFX_Debug_MCD_BBS_BTP1 (1 << 19) ++#define IFX_Debug_MCD_BBS_BTP0 (1 << 18) ++#define IFX_Debug_MCD_BBS_BSP1 (1 << 17) ++#define IFX_Debug_MCD_BBS_BSP0 (1 << 16) ++#define IFX_Debug_MCD_BBS_BT5EN (1 << 15) ++#define IFX_Debug_MCD_BBS_BT4EN (1 << 14) ++#define IFX_Debug_MCD_BBS_BT5 (1 << 13) ++#define IFX_Debug_MCD_BBS_BT4 (1 << 12) ++#define IFX_Debug_MCD_BBS_BS5EN (1 << 7) ++#define IFX_Debug_MCD_BBS_BS4EN (1 << 6) ++#define IFX_Debug_MCD_BBS_BS5 (1 << 5) ++#define IFX_Debug_MCD_BBS_BS4 (1 << 4) ++ ++/***MCD Multiplexer Control Register***/ ++#define IFX_Debug_MCD_MCR ((volatile u32*)(IFX_Debug+ 0x0008)) ++#define IFX_Debug_MCD_MCR_MUX5 (1 << 4) ++#define IFX_Debug_MCD_MCR_MUX4 (1 << 3) ++#define IFX_Debug_MCD_MCR_MUX1 (1 << 0) ++ ++ ++ ++/***********************************************************************/ ++/* Module : ICU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_ICU (KSEG1 | 0x1F880200) ++ ++#define IFX_ICU_IM0_ISR ((volatile u32*)(IFX_ICU + 0x0000)) ++#define IFX_ICU_IM0_IER ((volatile u32*)(IFX_ICU + 0x0008)) ++#define IFX_ICU_IM0_IOSR ((volatile u32*)(IFX_ICU + 0x0010)) ++#define IFX_ICU_IM0_IRSR ((volatile u32*)(IFX_ICU + 0x0018)) ++#define IFX_ICU_IM0_IMR ((volatile u32*)(IFX_ICU + 0x0020)) ++#define IFX_ICU_IM0_IMR_IID (1 << 31) ++#define IFX_ICU_IM0_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) ++#define IFX_ICU_IM0_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) ++#define IFX_ICU_IM0_IR(value) (1 << (value)) ++#define IFX_ICU_IM1_ISR ((volatile u32*)(IFX_ICU + 0x0028)) ++#define IFX_ICU_IM1_IER ((volatile u32*)(IFX_ICU + 0x0030)) ++#define IFX_ICU_IM1_IOSR ((volatile u32*)(IFX_ICU + 0x0038)) ++#define IFX_ICU_IM1_IRSR ((volatile u32*)(IFX_ICU + 0x0040)) ++#define IFX_ICU_IM1_IMR ((volatile u32*)(IFX_ICU + 0x0048)) ++#define IFX_ICU_IM1_IMR_IID (1 << 31) ++#define IFX_ICU_IM1_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) ++#define IFX_ICU_IM1_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) ++#define IFX_ICU_IM1_IR(value) (1 << (value)) ++#define IFX_ICU_IM2_ISR ((volatile u32*)(IFX_ICU + 0x0050)) ++#define IFX_ICU_IM2_IER ((volatile u32*)(IFX_ICU + 0x0058)) ++#define IFX_ICU_IM2_IOSR ((volatile u32*)(IFX_ICU + 0x0060)) ++#define IFX_ICU_IM2_IRSR ((volatile u32*)(IFX_ICU + 0x0068)) ++#define IFX_ICU_IM2_IMR ((volatile u32*)(IFX_ICU + 0x0070)) ++#define IFX_ICU_IM2_IMR_IID (1 << 31) ++#define IFX_ICU_IM2_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) ++#define IFX_ICU_IM2_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) ++#define IFX_ICU_IM2_IR(value) (1 << (value)) ++#define IFX_ICU_IM3_ISR ((volatile u32*)(IFX_ICU + 0x0078)) ++#define IFX_ICU_IM3_IER ((volatile u32*)(IFX_ICU + 0x0080)) ++#define IFX_ICU_IM3_IOSR ((volatile u32*)(IFX_ICU + 0x0088)) ++#define IFX_ICU_IM3_IRSR ((volatile u32*)(IFX_ICU + 0x0090)) ++#define IFX_ICU_IM3_IMR ((volatile u32*)(IFX_ICU + 0x0098)) ++#define IFX_ICU_IM3_IMR_IID (1 << 31) ++#define IFX_ICU_IM3_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) ++#define IFX_ICU_IM3_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) ++#define IFX_ICU_IM3_IR(value) (1 << (value)) ++#define IFX_ICU_IM4_ISR ((volatile u32*)(IFX_ICU + 0x00A0)) ++#define IFX_ICU_IM4_IER ((volatile u32*)(IFX_ICU + 0x00A8)) ++#define IFX_ICU_IM4_IOSR ((volatile u32*)(IFX_ICU + 0x00B0)) ++#define IFX_ICU_IM4_IRSR ((volatile u32*)(IFX_ICU + 0x00B8)) ++#define IFX_ICU_IM4_IMR ((volatile u32*)(IFX_ICU + 0x00C0)) ++#define IFX_ICU_IM4_IMR_IID (1 << 31) ++#define IFX_ICU_IM4_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) ++#define IFX_ICU_IM4_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) ++#define IFX_ICU_IM4_IR(value) (1 << (value)) ++ ++/***Interrupt Vector Value Register***/ ++#define IFX_ICU_IM_VEC ((volatile u32*)(IFX_ICU + 0x00F8)) ++ ++/***Interrupt Vector Value Mask***/ ++#define IFX_ICU_IM0_VEC_MASK 0x3F ++#define IFX_ICU_IM1_VEC_MASK (0x3F << 6) ++#define IFX_ICU_IM2_VEC_MASK (0x3F << 12) ++#define IFX_ICU_IM3_VEC_MASK (0x3F << 18) ++#define IFX_ICU_IM4_VEC_MASK (0x3F << 24) ++ ++/***External Interrupt Control Register***/ ++#define IFX_ICU_EIU (KSEG1 | 0x1f101000) ++#define IFX_ICU_EIU_EXIN_C ((volatile u32*)(IFX_ICU_EIU + 0x0000)) ++#define IFX_ICU_EIU_INIC ((volatile u32*)(IFX_ICU_EIU + 0x0004)) ++#define IFX_ICU_EIU_INC ((volatile u32*)(IFX_ICU_EIU + 0x0008)) ++#define IFX_ICU_EIU_INEN ((volatile u32*)(IFX_ICU_EIU + 0x000c)) ++ ++ ++ ++/***********************************************************************/ ++/* Module : MPS register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_MPS (KSEG1 | 0x1F107000) ++ ++#define IFX_MPS_CHIPID ((volatile u32*)(IFX_MPS + 0x0344)) ++#define IFX_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & 0xF) ++#define IFX_MPS_CHIPID_VERSION_SET(value) (((value) & 0xF) << 28) ++#define IFX_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & 0xFFFF) ++#define IFX_MPS_CHIPID_PARTNUM_SET(value) (((value) & 0xFFFF) << 12) ++#define IFX_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & 0x7FF) ++#define IFX_MPS_CHIPID_MANID_SET(value) (((value) & 0x7FF) << 1) ++ ++/* voice channel 0 ... 3 interrupt enable register */ ++#define IFX_MPS_VC0ENR ((volatile u32*)(IFX_MPS + 0x0000)) ++#define IFX_MPS_VC1ENR ((volatile u32*)(IFX_MPS + 0x0004)) ++#define IFX_MPS_VC2ENR ((volatile u32*)(IFX_MPS + 0x0008)) ++#define IFX_MPS_VC3ENR ((volatile u32*)(IFX_MPS + 0x000C)) ++/* voice channel 0 ... 3 interrupt status read register */ ++#define IFX_MPS_RVC0SR ((volatile u32*)(IFX_MPS + 0x0010)) ++#define IFX_MPS_RVC1SR ((volatile u32*)(IFX_MPS + 0x0014)) ++#define IFX_MPS_RVC2SR ((volatile u32*)(IFX_MPS + 0x0018)) ++#define IFX_MPS_RVC3SR ((volatile u32*)(IFX_MPS + 0x001C)) ++/* voice channel 0 ... 3 interrupt status set register */ ++#define IFX_MPS_SVC0SR ((volatile u32*)(IFX_MPS + 0x0020)) ++#define IFX_MPS_SVC1SR ((volatile u32*)(IFX_MPS + 0x0024)) ++#define IFX_MPS_SVC2SR ((volatile u32*)(IFX_MPS + 0x0028)) ++#define IFX_MPS_SVC3SR ((volatile u32*)(IFX_MPS + 0x002C)) ++/* voice channel 0 ... 3 interrupt status clear register */ ++#define IFX_MPS_CVC0SR ((volatile u32*)(IFX_MPS + 0x0030)) ++#define IFX_MPS_CVC1SR ((volatile u32*)(IFX_MPS + 0x0034)) ++#define IFX_MPS_CVC2SR ((volatile u32*)(IFX_MPS + 0x0038)) ++#define IFX_MPS_CVC3SR ((volatile u32*)(IFX_MPS + 0x003C)) ++/* common status 0 and 1 read register */ ++#define IFX_MPS_RAD0SR ((volatile u32*)(IFX_MPS + 0x0040)) ++#define IFX_MPS_RAD1SR ((volatile u32*)(IFX_MPS + 0x0044)) ++/* common status 0 and 1 set register */ ++#define IFX_MPS_SAD0SR ((volatile u32*)(IFX_MPS + 0x0048)) ++#define IFX_MPS_SAD1SR ((volatile u32*)(IFX_MPS + 0x004C)) ++/* common status 0 and 1 clear register */ ++#define IFX_MPS_CAD0SR ((volatile u32*)(IFX_MPS + 0x0050)) ++#define IFX_MPS_CAD1SR ((volatile u32*)(IFX_MPS + 0x0054)) ++/* common status 0 and 1 enable register */ ++#define IFX_MPS_AD0ENR ((volatile u32*)(IFX_MPS + 0x0058)) ++#define IFX_MPS_AD1ENR ((volatile u32*)(IFX_MPS + 0x005C)) ++/* notification enable register */ ++#define IFX_MPS_CPU0_NFER ((volatile u32*)(IFX_MPS + 0x0060)) ++#define IFX_MPS_CPU1_NFER ((volatile u32*)(IFX_MPS + 0x0064)) ++/* CPU to CPU interrup request register */ ++#define IFX_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(IFX_MPS + 0x0070)) ++#define IFX_MPS_CPU0_2_CPU1_IER ((volatile u32*)(IFX_MPS + 0x0074)) ++/* Global interrupt request and request enable register */ ++#define IFX_MPS_GIRR ((volatile u32*)(IFX_MPS + 0x0078)) ++#define IFX_MPS_GIER ((volatile u32*)(IFX_MPS + 0x007C)) ++ ++#define IFX_MPS_SRAM ((volatile u32*)(KSEG1 + 0x1F200000)) ++ ++#define IFX_MPS_VCPU_FW_AD ((volatile u32*)(KSEG1 + 0x1F2001E0)) ++ ++#define IFX_FUSE_BASE_ADDR (KSEG1 | 0x1F107354) ++ ++ ++ ++/************************************************************************/ ++/* Module : DEU register address and bits */ ++/************************************************************************/ ++ ++#define IFX_DEU_BASE_ADDR (KSEG1 | 0x1E103100) ++ ++/* DEU Control Register */ ++#define IFX_DEU_CLK ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0000)) ++#define IFX_DEU_ID ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0008)) ++ ++/* DEU control register */ ++#define IFX_DES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0010)) ++#define IFX_DES_IHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0014)) ++#define IFX_DES_ILR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0018)) ++#define IFX_DES_K1HR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x001C)) ++#define IFX_DES_K1LR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0020)) ++#define IFX_DES_K3HR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0024)) ++#define IFX_DES_K3LR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0028)) ++#define IFX_DES_IVHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x002C)) ++#define IFX_DES_IVLR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0030)) ++#define IFX_DES_OHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0040)) ++#define IFX_DES_OLR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050)) ++ ++/* AES DEU register */ ++#define IFX_AES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050)) ++#define IFX_AES_ID3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0054)) ++#define IFX_AES_ID2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0058)) ++#define IFX_AES_ID1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x005C)) ++#define IFX_AES_ID0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0060)) ++ ++/* AES Key register */ ++#define IFX_AES_K7R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0064)) ++#define IFX_AES_K6R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0068)) ++#define IFX_AES_K5R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x006C)) ++#define IFX_AES_K4R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0070)) ++#define IFX_AES_K3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0074)) ++#define IFX_AES_K2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0078)) ++#define IFX_AES_K1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x007C)) ++#define IFX_AES_K0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0080)) ++ ++/* AES vector register */ ++#define IFX_AES_IV3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0084)) ++#define IFX_AES_IV2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0088)) ++#define IFX_AES_IV1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x008C)) ++#define IFX_AES_IV0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0090)) ++#define IFX_AES_0D3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0094)) ++#define IFX_AES_0D2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0098)) ++#define IFX_AES_OD1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x009C)) ++#define IFX_AES_OD0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00A0)) ++ ++/* hash control registe */ ++#define IFX_HASH_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B0)) ++#define IFX_HASH_MR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B4)) ++#define IFX_HASH_D1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B8)) ++#define IFX_HASH_D2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00BC)) ++#define IFX_HASH_D3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C0)) ++#define IFX_HASH_D4R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C4)) ++#define IFX_HASH_D5R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C8)) ++ ++#define IFX_DEU_DMA_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00EC)) ++ ++#define IFX_DEU_IRNEN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00F4)) ++#define IFX_DEU_IRNCR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00F8)) ++#define IFX_DEU_IRNICR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00FC)) ++ ++ ++ ++/************************************************************************/ ++/* Module : PPE register address and bits */ ++/************************************************************************/ ++ ++#define IFX_PPE32_BASE (KSEG1 | 0x1E180000) ++#define IFX_PPE32_DEBUG_BREAK_TRACE_REG (IFX_PPE32_BASE + (0x0000 * 4)) ++#define IFX_PPE32_INT_MASK_STATUS_REG (IFX_PPE32_BASE + (0x0030 * 4)) ++#define IFX_PPE32_INT_RESOURCE_REG (IFX_PPE32_BASE + (0x0040 * 4)) ++#define IFX_PPE32_CDM_CODE_MEM_B0 (IFX_PPE32_BASE + (0x1000 * 4)) ++#define IFX_PPE32_CDM_CODE_MEM_B1 (IFX_PPE32_BASE + (0x2000 * 4)) ++#define IFX_PPE32_DATA_MEM_MAP_REG_BASE (IFX_PPE32_BASE + (0x4000 * 4)) ++ ++#define IFX_PPE32_SRST (IFX_PPE32_BASE + 0x10080) ++ ++/* ++ * ETOP MDIO Registers ++ */ ++#define IFX_PP32_ETOP_MDIO_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4))) ++#define IFX_PP32_ETOP_MDIO_ACC ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4))) ++#define IFX_PP32_ETOP_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4))) ++#define IFX_PP32_ETOP_IG_VLAN_COS ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4))) ++#define IFX_PP32_ETOP_IG_DSCP_COS3 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4))) ++#define IFX_PP32_ETOP_IG_DSCP_COS2 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4))) ++#define IFX_PP32_ETOP_IG_DSCP_COS1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4))) ++#define IFX_PP32_ETOP_IG_DSCP_COS0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4))) ++#define IFX_PP32_ETOP_IG_PLEN_CTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4))) ++#define IFX_PP32_ETOP_ISR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4))) ++#define IFX_PP32_ETOP_IER ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4))) ++#define IFX_PP32_ETOP_VPID ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4))) ++#define IFX_PP32_ENET_MAC_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4))) ++#define IFX_PP32_ENETS_DBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4))) ++#define IFX_PP32_ENETS_CBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4))) ++#define IFX_PP32_ENETS_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4))) ++#define IFX_PP32_ENETS_PGCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4))) ++#define IFX_PP32_ENETS_PKTCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4))) ++#define IFX_PP32_ENETS_BUF_CTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4))) ++#define IFX_PP32_ENETS_COS_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4))) ++#define IFX_PP32_ENETS_IGDROP ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4))) ++#define IFX_PP32_ENETS_IGERR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4))) ++#define IFX_PP32_ENET_MAC_DA0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4))) ++#define IFX_PP32_ENET_MAC_DA1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4))) ++ ++#define IFX_PP32_ENETF_DBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0630 * 4))) ++#define IFX_PP32_ENETF_CBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0631 * 4))) ++#define IFX_PP32_ENETF_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0632 * 4))) ++#define IFX_PP32_ENETF_PGCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0633 * 4))) ++#define IFX_PP32_ENETF_PKTCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0634 * 4))) ++#define IFX_PP32_ENETF_HFCTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0635 * 4))) ++#define IFX_PP32_ENETF_TXCTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0636 * 4))) ++ ++#define IFX_PP32_ENETF_VLCOS0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0638 * 4))) ++#define IFX_PP32_ENETF_VLCOS1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0639 * 4))) ++#define IFX_PP32_ENETF_VLCOS2 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063A * 4))) ++#define IFX_PP32_ENETF_VLCOS3 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063B * 4))) ++#define IFX_PP32_ENETF_EGERR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063C * 4))) ++#define IFX_PP32_ENETF_EGDROP ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063D * 4))) ++ ++ ++/* Sharebuff SB RAM2 control data */ ++#define IFX_PP32_SB2_DATABASE ((IFX_PPE32_BASE + (0x8C00 * 4))) ++#define IFX_PP32_SB2_CTRLBASE ((IFX_PPE32_BASE + (0x92E0 * 4))) ++ ++#endif /* DANUBE_H */ ++ +diff --git a/arch/mips/include/asm/ifx/danube/danube_ref_board.h b/arch/mips/include/asm/ifx/danube/danube_ref_board.h +new file mode 100644 +index 0000000..18d2c58 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/danube/danube_ref_board.h +@@ -0,0 +1,37 @@ ++/****************************************************************************** ++** ++** FILE NAME : danube_ref_board.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : header file for Danube ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef DANUBE_REF_BOARD_H ++#define DANUBE_REF_BOARD_H ++ ++#if defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) ++#define IFX_MTD_SPI_PART_NB 3 ++#define IFX_SPI_FLASH_MAX 7 ++#endif /* defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) */ ++ ++#define IFX_LEDLED_USB_VBUS ++ ++#endif /* DANUBE_REF_BOARD_H */ ++ +diff --git a/arch/mips/include/asm/ifx/danube/irq.h b/arch/mips/include/asm/ifx/danube/irq.h +new file mode 100644 +index 0000000..1c5f57b +--- /dev/null ++++ b/arch/mips/include/asm/ifx/danube/irq.h +@@ -0,0 +1,152 @@ ++/****************************************************************************** ++** ++** file name : irq.h ++** project : ifx ueip ++** modules : bsp basic ++** ++** date : 27 may 2009 ++** author : xu liang ++** description : header file for danube ++** copyright : copyright (c) 2009 ++** infineon technologies ag ++** am campeon 1-12, 85579 neubiberg, germany ++** ++** this program is free software; you can redistribute it and/or modify ++** it under the terms of the gnu general public license as published by ++** the free software foundation; either version 2 of the license, or ++** (at your option) any later version. ++** ++** history ++** $date $author $comment ++** 27 may 2009 xu liang the first ueip release ++*******************************************************************************/ ++ ++ ++ ++#ifndef DANUBE_IRQ ++#define DANUBE_IRQ ++ ++ ++ ++/****** Interrupt Assigments ***********/ ++ ++#define IFX_ASC0_TIR INT_NUM_IM3_IRL0 // INT_NUM_IM0_IRL0 ++#define IFX_ASC0_TBIR INT_NUM_IM3_IRL1 // INT_NUM_IM0_IRL1 ++#define IFX_ASC0_RIR INT_NUM_IM3_IRL2 // INT_NUM_IM0_IRL2 ++#define IFX_ASC0_EIR INT_NUM_IM3_IRL3 // INT_NUM_IM0_IRL3 ++#define IFX_ASC0_ABSTIR INT_NUM_IM3_IRL4 // INT_NUM_IM0_IRL4 ++#define IFX_ASC0_ABDETIR INT_NUM_IM3_IRL5 // INT_NUM_IM0_IRL5 ++#define IFX_ASC0_SFCIR INT_NUM_IM3_IRL6 // INT_NUM_IM0_IRL6 ++#define IFX_ASC0_MIR INT_NUM_IM3_IRL21 // INT_NUM_IM0_IRL21 ++#define IFX_ASC1_TIR INT_NUM_IM3_IRL7 // INT_NUM_IM0_IRL7 ++#define IFX_ASC1_TBIR INT_NUM_IM3_IRL8 // INT_NUM_IM0_IRL8 ++#define IFX_ASC1_RIR INT_NUM_IM3_IRL9 // INT_NUM_IM0_IRL9 ++#define IFX_ASC1_EIR INT_NUM_IM3_IRL10 // INT_NUM_IM0_IRL10 ++#define IFX_ASC1_ABSTIR INT_NUM_IM3_IRL11 // INT_NUM_IM0_IRL11 ++#define IFX_ASC1_ABDETIR INT_NUM_IM3_IRL12 // INT_NUM_IM0_IRL12 ++#define IFX_ASC1_SFCIR INT_NUM_IM3_IRL13 // INT_NUM_IM0_IRL13 ++ ++#define IFX_FPI_SLAVE_BCU0_IR INT_NUM_IM1_IRL25 ++#define IFX_FPI_MASTER_COSBCU_IR INT_NUM_IM0_IRL25 ++#define IFX_FPI_SLAVE_BCU_IRQ IFX_FPI_SLAVE_BCU0_IR ++#define IFX_FPI_MASTER_BCU_IRQ IFX_FPI_MASTER_COSBCU_IR ++ ++#define IFX_DSL_DFE_IR INT_NUM_IM2_IRL14 // INT_NUM_IM1_IRL23 ++#define IFX_DSL_AFEOVL_IR INT_NUM_IM2_IRL15 // INT_NUM_IM1_IRL24 ++#define IFX_DSL_DYING_GASP_INT INT_NUM_IM1_IRL21 ++#define IFX_DSL_DFE_INT0IR INT_NUM_IM4_IRL12 // INT_NUM_IM2_IRL12 ++#define IFX_DSL_DFE_INT1IR INT_NUM_IM4_IRL13 // INT_NUM_IM2_IRL13 ++#define IFX_FCSI_IR INT_NUM_IM1_IRL16 // INT_NUM_IM0_IRL31 ++#define IFX_MEI_INT IFX_DSL_DFE_IR ++#define IFX_MEI_DYING_GASP_INT IFX_DSL_DYING_GASP_INT ++#define IFX_DSL_DFE_TXIR IFX_DSL_DFE_INT0IR ++#define IFX_DSL_DFE_RXIR IFX_DSL_DFE_INT1IR ++ ++#define IFX_DEU_DESIR INT_NUM_IM1_IRL6 // INT_NUM_IM0_IRL27 ++#define IFX_DEU_AESIR INT_NUM_IM1_IRL7 // INT_NUM_IM0_IRL28 ++#define IFX_DEU_HASHIR INT_NUM_IM1_IRL8 // INT_NUM_IM0_IRL29 ++ ++#define IFX_DMA_CH0_INT INT_NUM_IM4_IRL0 // INT_NUM_IM2_IRL0 ++#define IFX_DMA_CH1_INT INT_NUM_IM4_IRL1 // INT_NUM_IM2_IRL1 ++#define IFX_DMA_CH2_INT INT_NUM_IM4_IRL2 // INT_NUM_IM2_IRL2 ++#define IFX_DMA_CH3_INT INT_NUM_IM4_IRL3 // INT_NUM_IM2_IRL3 ++#define IFX_DMA_CH4_INT INT_NUM_IM4_IRL4 // INT_NUM_IM2_IRL4 ++#define IFX_DMA_CH5_INT INT_NUM_IM4_IRL5 // INT_NUM_IM2_IRL5 ++#define IFX_DMA_CH6_INT INT_NUM_IM4_IRL6 // INT_NUM_IM2_IRL6 ++#define IFX_DMA_CH7_INT INT_NUM_IM4_IRL7 // INT_NUM_IM2_IRL7 ++#define IFX_DMA_CH8_INT INT_NUM_IM4_IRL8 // INT_NUM_IM2_IRL8 ++#define IFX_DMA_CH9_INT INT_NUM_IM4_IRL9 // INT_NUM_IM2_IRL9 ++#define IFX_DMA_CH10_INT INT_NUM_IM4_IRL10 // INT_NUM_IM2_IRL10 ++#define IFX_DMA_CH11_INT INT_NUM_IM4_IRL11 // INT_NUM_IM2_IRL11 ++#define IFX_DMA_CH12_INT INT_NUM_IM4_IRL25 // INT_NUM_IM2_IRL25 ++#define IFX_DMA_CH13_INT INT_NUM_IM4_IRL26 // INT_NUM_IM2_IRL26 ++#define IFX_DMA_CH14_INT INT_NUM_IM4_IRL27 // INT_NUM_IM2_IRL27 ++#define IFX_DMA_CH15_INT INT_NUM_IM4_IRL28 // INT_NUM_IM2_IRL28 ++#define IFX_DMA_CH16_INT INT_NUM_IM4_IRL29 // INT_NUM_IM2_IRL29 ++#define IFX_DMA_CH17_INT INT_NUM_IM1_IRL30 // INT_NUM_IM0_IRL30 ++#define IFX_DMA_CH18_INT INT_NUM_IM2_IRL16 ++#define IFX_DMA_CH19_INT INT_NUM_IM2_IRL21 ++ ++#define IFX_PPE_MBOX_INT0 INT_NUM_IM2_IRL23 // INT_NUM_IM0_IRL23 ++#define IFX_PPE_MBOX_INT1 INT_NUM_IM2_IRL24 // INT_NUM_IM0_IRL24 ++#define IFX_PPE_MBOX_INT2 INT_NUM_IM1_IRL29 ++#define IFX_PPE_QSB_INT INT_NUM_IM1_IRL31 ++ ++#define IFX_EIU_IR0 INT_NUM_IM4_IRL30 ++#define IFX_EIU_IR1 INT_NUM_IM3_IRL31 // INT_NUM_IM2_IRL31 ++#define IFX_EIU_IR2 INT_NUM_IM1_IRL26 // INT_NUM_IM0_IRL26 ++ ++#define IFX_MPS_IR0 INT_NUM_IM4_IRL14 // INT_NUM_IM1_IRL9 ++#define IFX_MPS_IR1 INT_NUM_IM4_IRL15 // INT_NUM_IM1_IRL10 ++#define IFX_MPS_IR2 INT_NUM_IM4_IRL16 // INT_NUM_IM1_IRL11 ++#define IFX_MPS_IR3 INT_NUM_IM4_IRL17 // INT_NUM_IM1_IRL12 ++#define IFX_MPS_IR4 INT_NUM_IM4_IRL18 // INT_NUM_IM1_IRL13 ++#define IFX_MPS_IR5 INT_NUM_IM4_IRL19 // INT_NUM_IM1_IRL14 ++#define IFX_MPS_IR6 INT_NUM_IM4_IRL20 // INT_NUM_IM1_IRL15 ++#define IFX_MPS_IR7 INT_NUM_IM3_IRL29 // INT_NUM_IM0_IRL7 ! MIPS1 ++#define IFX_MPS_IR8 INT_NUM_IM4_IRL21 // INT_NUM_IM3_IRL29 ++#define IFX_MPS_SEMAPHORE_IR IFX_MPS_IR7 ++#define IFX_MPS_GLOBAL_IR IFX_MPS_IR8 ++ ++#define IFX_GPTU_TC1A INT_NUM_IM3_IRL22 // INT_NUM_IM1_IRL0 ++#define IFX_GPTU_TC1B INT_NUM_IM3_IRL23 // INT_NUM_IM1_IRL1 ++#define IFX_GPTU_TC2A INT_NUM_IM3_IRL24 // INT_NUM_IM1_IRL2 ++#define IFX_GPTU_TC2B INT_NUM_IM3_IRL25 // INT_NUM_IM1_IRL3 ++#define IFX_GPTU_TC3A INT_NUM_IM3_IRL26 // INT_NUM_IM1_IRL4 ++#define IFX_GPTU_TC3B INT_NUM_IM3_IRL27 // INT_NUM_IM1_IRL5 ++ ++#define IFX_MC_IR INT_NUM_IM3_IRL28 ++ ++#define IFX_EBU_IR INT_NUM_IM0_IRL22 ++ ++#define IFX_PCI_IR INT_NUM_IM2_IRL17 // INT_NUM_IM1_IRL17 ++#define IFX_PCI_WRIR INT_NUM_IM2_IRL18 // INT_NUM_IM1_IRL18 ++ ++#define IFX_PCM_TXIR INT_NUM_IM2_IRL19 // INT_NUM_IM1_IRL19 ++#define IFX_PCM_RXIR INT_NUM_IM2_IRL20 // INT_NUM_IM1_IRL20 ++ ++#define IFX_PMCIR INT_NUM_IM4_IRL31 // INT_NUM_IM2_IRL30 ++ ++#define IFX_SBIU0_ERRIR INT_NUM_IM1_IRL27 ++#define IFX_SBIU1_ERRIR INT_NUM_IM1_IRL28 ++#define IFX_SBIU_ERRIR IFX_SBIU0_ERRIR ++ ++#define IFX_SSC_RIR INT_NUM_IM3_IRL14 // INT_NUM_IM0_IRL14 ++#define IFX_SSC_TIR INT_NUM_IM3_IRL15 // INT_NUM_IM0_IRL15 ++#define IFX_SSC_EIR INT_NUM_IM3_IRL16 // INT_NUM_IM0_IRL16 ++#define IFX_SSC_FIR INT_NUM_IM3_IRL17 // INT_NUM_IM0_IRL17 ++ ++#define IFX_MMC_CONTROLLER_INTR0_IRQ INT_NUM_IM3_IRL18 // INT_NUM_IM0_IRL18 ++#define IFX_MMC_CONTROLLER_INTR1_IRQ INT_NUM_IM3_IRL19 // INT_NUM_IM0_IRL19 ++#define IFX_MMC_CONTROLLER_SDIO_I_IRQ INT_NUM_IM3_IRL20 // INT_NUM_IM0_IRL20 ++ ++#define IFX_USB0_IR INT_NUM_IM2_IRL22 // INT_NUM_IM1_IRL22 ++#define IFX_USB0_OCIR INT_NUM_IM4_IRL23 ++#define IFX_USB_INT IFX_USB0_IR ++#define IFX_USB_OC_INT IFX_USB0_OCIR ++ ++#define IFX_WDT_AEIR INT_NUM_IM4_IRL24 ++ ++ ++ ++#endif // DANUBE_IRQ +diff --git a/arch/mips/include/asm/ifx/danube/model.h b/arch/mips/include/asm/ifx/danube/model.h +new file mode 100644 +index 0000000..befff4c +--- /dev/null ++++ b/arch/mips/include/asm/ifx/danube/model.h +@@ -0,0 +1,54 @@ ++/****************************************************************************** ++** ++** FILE NAME : model.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : header file for Danube ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef DANUBE_MODEL_H ++#define DANUBE_MODEL_H ++/****************************************************************************** ++ Copyright (c) 2002, Infineon Technologies. All rights reserved. ++ ++ No Warranty ++ Because the program is licensed free of charge, there is no warranty for ++ the program, to the extent permitted by applicable law. Except when ++ otherwise stated in writing the copyright holders and/or other parties ++ provide the program "as is" without warranty of any kind, either ++ expressed or implied, including, but not limited to, the implied ++ warranties of merchantability and fitness for a particular purpose. The ++ entire risk as to the quality and performance of the program is with ++ you. should the program prove defective, you assume the cost of all ++ necessary servicing, repair or correction. ++ ++ In no event unless required by applicable law or agreed to in writing ++ will any copyright holder, or any other party who may modify and/or ++ redistribute the program as permitted above, be liable to you for ++ damages, including any general, special, incidental or consequential ++ damages arising out of the use or inability to use the program ++ (including but not limited to loss of data or data being rendered ++ inaccurate or losses sustained by you or third parties or a failure of ++ the program to operate with any other programs), even if such holder or ++ other party has been advised of the possibility of such damages. ++******************************************************************************/ ++#define BOARD_SYSTEM_TYPE "Danube" ++#define SYSTEM_MODEL_NAME "Danube Reference Board BSP26" ++#endif +diff --git a/arch/mips/include/asm/ifx/hn1/emulation.h b/arch/mips/include/asm/ifx/hn1/emulation.h +new file mode 100644 +index 0000000..68a7093 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/hn1/emulation.h +@@ -0,0 +1,40 @@ ++/****************************************************************************** ++** ++** FILE NAME : emulation.h ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Lei Chuan Hua ++** DESCRIPTION : header file for HN1 ++** COPYRIGHT : Copyright (c) 2011 ++** Lantiq Deutschland GmbH ++** Am Campeon 3, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++*******************************************************************************/ ++ ++ ++ ++#ifndef EMULATION_H ++#define EMULATION_H ++ ++#ifdef CONFIG_USE_EMULATOR ++ ++//For Palladium using db.rel_106.c database the EMULATOR_CPU_SPEED is 271KHz ++ #define EMULATOR_CPU_SPEED 271000 ++ #define PLL0_CLK_SPEED 271000 ++ ++#else /* Real chip */ ++ #define PLL0_CLK_SPEED 1000000000 ++#endif /* CONFIG_USE_EMULATOR */ ++ ++ ++#endif /* */ ++ /* EMULATION_H */ ++ +diff --git a/arch/mips/include/asm/ifx/hn1/hn1.h b/arch/mips/include/asm/ifx/hn1/hn1.h +new file mode 100644 +index 0000000..8c0037d +--- /dev/null ++++ b/arch/mips/include/asm/ifx/hn1/hn1.h +@@ -0,0 +1,1293 @@ ++/****************************************************************************** ++** ++** FILE NAME : hn1.h ++** MODULES : BSP Basic ++** ++** DATE : 11 Jan 2011 ++** AUTHOR : Kishore Kankipati ++** DESCRIPTION : header file for HN1 ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 11 Jan 2011 Kishore First version for HN1 derived from VR9 ++** 11 Feb 2011 Yinglei Modified for HN1 ++*******************************************************************************/ ++ ++ ++ ++#ifndef HN1_H ++#define HN1_H ++ ++#include ++ ++#define MACH_GROUP_IFX MACH_GROUP_HN1 ++#define MACH_TYPE_IFX MACH_HN1 ++ ++ ++/***********************************************************************/ ++/* Module : WDT register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_WDT (KSEG1 | 0x1F880000) ++ ++/***Watchdog Timer Control Register ***/ ++#define IFX_WDT_CR ((volatile u32*)(IFX_WDT + 0x03F0)) ++#define IFX_WDT_CR_GEN (1 << 31) ++#define IFX_WDT_CR_DSEN (1 << 30) ++#define IFX_WDT_CR_LPEN (1 << 29) ++#define IFX_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1)) ++#define IFX_WDT_CR_PWL_SET(value) (((( 1 << 2) - 1) & (value)) << 26) ++#define IFX_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1)) ++#define IFX_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24) ++#define IFX_WDT_CR_PW_GET(value) (((value) >> 16) & ((1 << 8) - 1)) ++#define IFX_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16) ++#define IFX_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1)) ++#define IFX_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0) ++ ++/***Watchdog Timer Status Register***/ ++#define IFX_WDT_SR ((volatile u32*)(IFX_WDT + 0x03F8)) ++#define IFX_WDT_SR_EN (1 << 31) ++#define IFX_WDT_SR_AE (1 << 30) ++#define IFX_WDT_SR_PRW (1 << 29) ++#define IFX_WDT_SR_EXP (1 << 28) ++#define IFX_WDT_SR_PWD (1 << 27) ++#define IFX_WDT_SR_DS (1 << 26) ++#define IFX_WDT_SR_VALUE_GET(value) (((value) >> 0) & ((1 << 16) - 1)) ++#define IFX_WDT_SR_VALUE_SET(value) (((( 1 << 16) - 1) & (value)) << 0) ++ ++ ++/***********************************************************************/ ++/* Module : RCU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_RCU (KSEG1 | 0x1F203000) ++ ++/* Reset Request Register */ ++#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) ++#define IFX_RCU_RST_REQ_HOT_RST 0x00000001 /* Hot reset, domain 0*/ ++ ++#define IFX_RCU_RST_STAT ((volatile u32*)(IFX_RCU + 0x0014)) ++#define IFX_RCU_GPIO_STRAP ((volatile u32*)(IFX_RCU + 0x001C)) ++#define IFX_RCU_GPHY0_FW_ADDR ((volatile u32*)(IFX_RCU + 0x0020)) ++#define IFX_RCU_SLIC_USB_RST_STAT ((volatile u32*)(IFX_RCU + 0x0024)) ++#define IFX_RCU_PCIE_PHY_CON_STAT ((volatile u32*)(IFX_RCU + 0x0030)) ++#define IFX_RCU_GPHY01_MDIO_ADD ((volatile u32*)(IFX_RCU + 0x0044)) ++#define IFX_RCU_GPHY0_RST_REQ ((volatile u32*)(IFX_RCU + 0x0048)) ++ ++/* AHB Endian Register */ ++#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) ++ ++#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ ++#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ ++#define IFX_RCU_AHB_BE_USIF 0x00000004 /* Configure AHB slave port that connects to USIF in big endian */ ++#define IFX_RCU_AHB_BE_XBAR_S 0x00000008 /* Configure AHB slave port that connects to XBAR in big endian */ ++#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ ++#define IFX_RCU_AHB_BE_PCIE_DBI 0x00000020 /* Configure DBI module in big endian*/ ++#define IFX_RCU_AHB_BE_DC_PDI 0x00000040 /* Configure DC PDI module in big endian*/ ++#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ ++ ++#define IFX_RCU_CPU_CFG ((volatile u32*)(IFX_RCU + 0x0060)) ++ ++/* Reset Request Register */ ++#define IFX_RCU_RST_REQ_GPHY0 (1 << 31) ++#define IFX_RCU_RST_REQ_SRST (1 << 30) ++#define IFX_RCU_RST_REQ_GPHY1 (1 << 29) ++#define IFX_RCU_RST_REQ_MIPS0 (1 << 1) ++ ++/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */ ++#define IFX_RCU_RST_REQ_ALL (IFX_RCU_RST_REQ_SRST | IFX_RCU_RST_REQ_GPHY0 | IFX_RCU_RST_REQ_GPHY1 | IFX_RCU_RST_REQ_MIPS0) ++ ++#define IFX_RCU_RST_REQ_DFE (1 << 7) ++#define IFX_RCU_RST_REQ_AFE (1 << 11) ++#define IFX_RCU_RST_REQ_ARC_JTAG (1 << 20) ++ ++ ++/***********************************************************************/ ++/* Module : BCU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_BCU_BASE_ADDR (KSEG1 | 0x1E100000) ++#define IFX_SLAVE_BCU_BASE_ADDR (KSEG1 | 0x1E000000) ++ ++/***BCU Control Register (0010H)***/ ++#define IFX_BCU_CON ((volatile u32*)(0x0010 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_CON ((volatile u32*)(0x0010 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_STARVATION_MASK (0xFF << 24) ++#define IFX_BCU_STARVATION_SHIFT 24 ++#define IFX_BCU_TOUT_MASK 0xFFFF ++#define IFX_BCU_CON_SPC(value) (((( 1 << 8) - 1) & (value)) << 24) ++#define IFX_BCU_CON_SPE (1 << 19) ++#define IFX_BCU_CON_PSE (1 << 18) ++#define IFX_BCU_CON_DBG (1 << 16) ++#define IFX_BCU_CON_TOUT(value) (((( 1 << 16) - 1) & (value)) << 0) ++ ++/***BCU Error Control Capture Register (0020H)***/ ++#define IFX_BCU_ECON ((volatile u32*)(0x0020 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_ECON ((volatile u32*)(0x0020 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_ECON_TAG(value) (((( 1 << 4) - 1) & (value)) << 24) ++#define IFX_BCU_ECON_RDN (1 << 23) ++#define IFX_BCU_ECON_WRN (1 << 22) ++#define IFX_BCU_ECON_SVM (1 << 21) ++#define IFX_BCU_ECON_ACK(value) (((( 1 << 2) - 1) & (value)) << 19) ++#define IFX_BCU_ECON_ABT (1 << 18) ++#define IFX_BCU_ECON_RDY (1 << 17) ++#define IFX_BCU_ECON_TOUT (1 << 16) ++#define IFX_BCU_ECON_ERRCNT(value) (((( 1 << 16) - 1) & (value)) << 0) ++#define IFX_BCU_ECON_OPC(value) (((( 1 << 4) - 1) & (value)) << 28) ++ ++/***BCU Error Address Capture Register (0024 H)***/ ++#define IFX_BCU_EADD ((volatile u32*)(0x0024 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_EADD ((volatile u32*)(0x0024 + IFX_SLAVE_BCU_BASE_ADDR)) ++ ++/***BCU Error Data Capture Register (0028H)***/ ++#define IFX_BCU_EDAT ((volatile u32*)(0x0028 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_EDAT ((volatile u32*)(0x0028 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_IRNICR ((volatile u32*)(0x00F8 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_IRNICR ((volatile u32*)(0x00F8 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_IRNCR ((volatile u32*)(0x00FC + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_IRNCR ((volatile u32*)(0x00FC + IFX_SLAVE_BCU_BASE_ADDR)) ++ ++ ++/***********************************************************************/ ++/* Module : HSNAND register address and bits */ ++/***********************************************************************/ ++#define IFX_HSNAND_BASE (KSEG1 | 0x1E100400) ++ ++/****** HSNAND REGISTERS *******/ ++#define IFX_NDAC_CTL1 ((volatile u32*)(0x0010 + IFX_HSNAND_BASE)) ++#define IFX_NDAC_CTL2 ((volatile u32*)(0x0014 + IFX_HSNAND_BASE)) ++#define IFX_BASE_A ((volatile u32*)(0x0018 + IFX_HSNAND_BASE)) ++#define IFX_RX_CNT ((volatile u32*)(0x001C + IFX_HSNAND_BASE)) ++#define IFX_DPLUS_CTRL ((volatile u32*)(0x0020 + IFX_HSNAND_BASE)) ++#define IFX_HSNAND_INTR_MASK_CTRL ((volatile u32*)(0x0024 + IFX_HSNAND_BASE)) ++#define IFX_HSNAND_INTR_STAT ((volatile u32*)(0x0028 + IFX_HSNAND_BASE)) ++#define IFX_HSMD_CTRL ((volatile u32*)(0x0030 + IFX_HSNAND_BASE)) ++#define IFX_CS_BASE_A ((volatile u32*)(0x0034 + IFX_HSNAND_BASE)) ++#define IFX_NAND_INFO ((volatile u32*)(0X0038 + IFX_HSNAND_BASE)) ++ ++#define IFX_HSNAND_CE_SEL (0xF<<3) ++#define IFX_HSNAND_CE_SEL_S 3 ++#define IFX_HSNAND_CE_SEL_NONE 0 ++#define IFX_HSNAND_CE_SEL_CS0 1 ++#define IFX_HSNAND_CE_SEL_CS1 2 ++#define IFX_HSNAND_CE_SEL_CS2 4 ++#define IFX_HSNAND_CE_SEL_CS3 8 ++ ++#define IFX_HSNAND_FSM (1<<2) ++#define IFX_HSNAND_FSM_S 2 ++enum { ++ IFX_HSNAND_FSM_DISABLED = 0, ++ IFX_HSNAND_FSM_ENABLED, ++}; ++ ++#define IFX_HSNAND_ENR (3<<0) ++#define IFX_HSNAND_ENR_S 0 ++enum { ++ IFX_HSNAND_ENR_XIP = 0, ++ IFX_HSNAND_ENR_HSDMA, ++ IFX_HSNAND_ENR_IO, ++ IFX_HSNAND_ENR_NONE ++}; ++ ++#define IFX_HSNAND_XFER_SEL (7<<0) ++#define IFX_HSNAND_XFER_SEL_S 7 ++enum { ++ IFX_HSNAND_NO_XFER = 0, ++ IFX_HSNAND_START_XFER ++}; ++ ++/***********************************************************************/ ++/* Module : GPIO register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_GPIO (KSEG1 | 0x1E100B00) ++ ++/***Port 0 Data Output Register (0010H)***/ ++#define IFX_GPIO_P0_OUT ((volatile u32 *)(IFX_GPIO + 0x0010)) ++/***Port 1 Data Output Register (0040H)***/ ++#define IFX_GPIO_P1_OUT ((volatile u32 *)(IFX_GPIO + 0x0040)) ++/***Port 2 Data Output Register (0070H)***/ ++#define IFX_GPIO_P2_OUT ((volatile u32 *)(IFX_GPIO + 0x0070)) ++/***Port 3 Data Output Register (00A0H)***/ ++#define IFX_GPIO_P3_OUT ((volatile u32 *)(IFX_GPIO + 0x00A0)) ++/***Port 0 Data Input Register (0014H)***/ ++#define IFX_GPIO_P0_IN ((volatile u32 *)(IFX_GPIO + 0x0014)) ++/***Port 1 Data Input Register (0044H)***/ ++#define IFX_GPIO_P1_IN ((volatile u32 *)(IFX_GPIO + 0x0044)) ++/***Port 2 Data Input Register (0074H)***/ ++#define IFX_GPIO_P2_IN ((volatile u32 *)(IFX_GPIO + 0x0074)) ++/***Port 3 Data Input Register (00A4H)***/ ++#define IFX_GPIO_P3_IN ((volatile u32 *)(IFX_GPIO + 0x00A4)) ++/***Port 0 Direction Register (0018H)***/ ++#define IFX_GPIO_P0_DIR ((volatile u32 *)(IFX_GPIO + 0x0018)) ++/***Port 1 Direction Register (0048H)***/ ++#define IFX_GPIO_P1_DIR ((volatile u32 *)(IFX_GPIO + 0x0048)) ++/***Port 2 Direction Register (0078H)***/ ++#define IFX_GPIO_P2_DIR ((volatile u32 *)(IFX_GPIO + 0x0078)) ++/***Port 3 Direction Register (0048H)***/ ++#define IFX_GPIO_P3_DIR ((volatile u32 *)(IFX_GPIO + 0x00A8)) ++/***Port 0 Alternate Function Select Register 0 (001C H) ***/ ++#define IFX_GPIO_P0_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x001C)) ++/***Port 1 Alternate Function Select Register 0 (004C H) ***/ ++#define IFX_GPIO_P1_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x004C)) ++/***Port 2 Alternate Function Select Register 0 (007C H) ***/ ++#define IFX_GPIO_P2_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x007C)) ++/***Port 3 Alternate Function Select Register 0 (00AC H) ***/ ++#define IFX_GPIO_P3_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x00AC)) ++/***Port 0 Alternate Function Select Register 1 (0020 H) ***/ ++#define IFX_GPIO_P0_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0020)) ++/***Port 1 Alternate Function Select Register 0 (0050 H) ***/ ++#define IFX_GPIO_P1_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0050)) ++/***Port 2 Alternate Function Select Register 0 (0080 H) ***/ ++#define IFX_GPIO_P2_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0080)) ++/***Port 3 Alternate Function Select Register 0 (0064 H) ***/ ++#define IFX_GPIO_P3_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0064)) ++/***Port 0 Open Drain Control Register (0024H)***/ ++#define IFX_GPIO_P0_OD ((volatile u32 *)(IFX_GPIO + 0x0024)) ++/***Port 1 Open Drain Control Register (0054H)***/ ++#define IFX_GPIO_P1_OD ((volatile u32 *)(IFX_GPIO + 0x0054)) ++/***Port 2 Open Drain Control Register (0084H)***/ ++#define IFX_GPIO_P2_OD ((volatile u32 *)(IFX_GPIO + 0x0084)) ++/***Port 3 Open Drain Control Register (0034H)***/ ++#define IFX_GPIO_P3_OD ((volatile u32 *)(IFX_GPIO + 0x0034)) ++/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/ ++#define IFX_GPIO_P0_STOFF ((volatile u32 *)(IFX_GPIO + 0x0028)) ++/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/ ++#define IFX_GPIO_P1_STOFF ((volatile u32 *)(IFX_GPIO + 0x0058)) ++/***Port 2 Input Schmitt-Trigger Off Register (0088 H) ***/ ++#define IFX_GPIO_P2_STOFF ((volatile u32 *)(IFX_GPIO + 0x0088)) ++/***Port 3 Input Schmitt-Trigger Off Register (0094 H) ***/ ++ ++/***Port 0 Pull Up/Pull Down Select Register (002C H)***/ ++#define IFX_GPIO_P0_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x002C)) ++/***Port 1 Pull Up/Pull Down Select Register (005C H)***/ ++#define IFX_GPIO_P1_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x005C)) ++/***Port 2 Pull Up/Pull Down Select Register (008C H)***/ ++#define IFX_GPIO_P2_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x008C)) ++/***Port 3 Pull Up/Pull Down Select Register (0038 H)***/ ++#define IFX_GPIO_P3_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x0038)) ++/***Port 0 Pull Up Device Enable Register (0030 H)***/ ++#define IFX_GPIO_P0_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0030)) ++/***Port 1 Pull Up Device Enable Register (0060 H)***/ ++#define IFX_GPIO_P1_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0060)) ++/***Port 2 Pull Up Device Enable Register (0090 H)***/ ++#define IFX_GPIO_P2_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0090)) ++/***Port 3 Pull Up Device Enable Register (003c H)***/ ++#define IFX_GPIO_P3_PUDEN ((volatile u32 *)(IFX_GPIO + 0x003C)) ++ ++ ++ ++/***********************************************************************/ ++/* Module : CGU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_CGU (KSEG1 | 0x1F103000) ++ ++/***CGU Clock PLL0 ***/ ++#define IFX_CGU_PLL0_CFG ((volatile u32*)(IFX_CGU + 0x0004)) ++/***CGU Clock PLL1 ***/ ++#define IFX_CGU_PLL1_CFG ((volatile u32*)(IFX_CGU + 0x0008)) ++/***CGU Clock PLL2 ***/ ++#define IFX_CGU_PLL2_CFG ((volatile u32*)(IFX_CGU + 0x0060)) ++/***CGU Clock SYS Mux Register***/ ++#define IFX_CGU_SYS ((volatile u32*)(IFX_CGU + 0x000C)) ++/***CGU CGU Clock Frequency Select Register***/ ++#define IFX_CGU_CLKFSR ((volatile u32*)(IFX_CGU + 0x0010)) ++/**Update CGU Register***/ ++#define IFX_CGU_UPDATE ((volatile u32*)(IFX_CGU + 0x0020)) ++/***CGU Interface Clock Control Register***/ ++#define IFX_CGU_IF_CLK ((volatile u32*)(IFX_CGU + 0x0024)) ++ ++/***********************************************************************/ ++/* Module : MCD register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_MCD (KSEG1 | 0x1F106000) ++ ++/***Manufacturer Identification Register***/ ++#define IFX_MCD_MANID ((volatile u32*)(IFX_MCD + 0x0024)) ++#define IFX_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5) ++ ++/***Chip Identification Register***/ ++#define IFX_MCD_CHIPID ((volatile u32*)(IFX_MCD + 0x0028)) ++#define IFX_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) ++#define IFX_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) ++#define IFX_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1)) ++#define IFX_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12) ++#define IFX_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1)) ++#define IFX_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1) ++ ++#define IFX_CHIPID_STANDARD 0x00EB ++#define IFX_CHIPID_YANGTSE 0x00ED ++ ++/***Redesign Tracing Identification Register***/ ++#define IFX_MCD_RTID ((volatile u32*)(IFX_MCD + 0x002C)) ++#define IFX_MCD_RTID_LC (1 << 15) ++#define IFX_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0) ++ ++ ++ ++/***********************************************************************/ ++/* Module : EBU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_EBU (KSEG1 | 0x1E105300) ++ ++/***EBU Clock Control Register***/ ++#define IFX_EBU_CLC ((volatile u32*)(IFX_EBU + 0x0000)) ++#define IFX_EBU_CLC_DISS (1 << 1) ++#define IFX_EBU_CLC_DISR (1 << 0) ++ ++#define IFX_EBU_ID ((volatile u32*)(IFX_EBU + 0x0008)) ++ ++/***EBU Global Control Register***/ ++#define IFX_EBU_CON ((volatile u32*)(IFX_EBU + 0x0010)) ++#define IFX_EBU_CON_DTACS(value) (((( 1 << 3) - 1) & (value)) << 20) ++#define IFX_EBU_CON_DTARW(value) (((( 1 << 3) - 1) & (value)) << 16) ++#define IFX_EBU_CON_TOUTC(value) (((( 1 << 8) - 1) & (value)) << 8) ++#define IFX_EBU_CON_ARBMODE(value) (((( 1 << 2) - 1) & (value)) << 6) ++#define IFX_EBU_CON_ARBSYNC (1 << 5) ++ ++/***EBU Address Select Register 0***/ ++#define IFX_EBU_ADDSEL0 ((volatile u32*)(IFX_EBU + 0x0020)) ++#define IFX_EBU_ADDSEL0_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) ++#define IFX_EBU_ADDSEL0_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_EBU_ADDSEL0_MIRRORE (1 << 1) ++#define IFX_EBU_ADDSEL0_REGEN (1 << 0) ++ ++/***EBU Address Select Register 1***/ ++#define IFX_EBU_ADDSEL1 ((volatile u32*)(IFX_EBU + 0x0024)) ++#define IFX_EBU_ADDSEL1_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) ++#define IFX_EBU_ADDSEL1_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_EBU_ADDSEL1_MIRRORE (1 << 1) ++#define IFX_EBU_ADDSEL1_REGEN (1 << 0) ++ ++/***EBU Address Select Register 2***/ ++#define IFX_EBU_ADDSEL2 ((volatile u32*)(IFX_EBU + 0x0028)) ++#define IFX_EBU_ADDSEL2_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) ++#define IFX_EBU_ADDSEL2_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_EBU_ADDSEL2_MIRRORE (1 << 1) ++#define IFX_EBU_ADDSEL2_REGEN (1 << 0) ++ ++/***EBU Address Select Register 3***/ ++#define IFX_EBU_ADDSEL3 ((volatile u32*)(IFX_EBU + 0x002C)) ++#define IFX_EBU_ADDSEL3_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) ++#define IFX_EBU_ADDSEL3_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_EBU_ADDSEL3_MIRRORE (1 << 1) ++#define IFX_EBU_ADDSEL3_REGEN (1 << 0) ++ ++/***EBU Bus Configuration Register 0***/ ++#define IFX_EBU_BUSCON0 ((volatile u32*)(IFX_EBU+ 0x0060)) ++ ++#define IFX_EBU_BUSCON0_CMULT 0x00000003 ++#define IFX_EBU_BUSCON0_CMULT_S 0 ++enum { ++ IFX_EBU_BUSCON0_CMULT1 = 0, ++ IFX_EBU_BUSCON0_CMULT4, ++ IFX_EBU_BUSCON0_CMULT8, ++ IFX_EBU_BUSCON0_CMULT16, /* Default after reset */ ++}; ++ ++#define IFX_EBU_BUSCON0_RECOVC 0x00000000c ++#define IFX_EBU_BUSCON0_RECOVC_S 2 ++enum { ++ IFX_EBU_BUSCON0_RECOVC0 = 0, ++ IFX_EBU_BUSCON0_RECOVC1, ++ IFX_EBU_BUSCON0_RECOVC2, ++ IFX_EBU_BUSCON0_RECOVC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON0_HOLDC 0x00000030 ++#define IFX_EBU_BUSCON0_HOLDC_S 4 ++enum { ++ IFX_EBU_BUSCON0_HOLDC0 = 0, ++ IFX_EBU_BUSCON0_HOLDC1, ++ IFX_EBU_BUSCON0_HOLDC2, ++ IFX_EBU_BUSCON0_HOLDC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON0_WAITRDC 0x000000c0 ++#define IFX_EBU_BUSCON0_WAITRDC_S 6 ++enum { ++ IFX_EBU_BUSCON0_WAITRDC0 = 0, ++ IFX_EBU_BUSCON0_WAITRDC1, ++ IFX_EBU_BUSCON0_WAITRDC2, ++ IFX_EBU_BUSCON0_WAITRDC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON0_WAITWRC 0x00000700 ++#define IFX_EBU_BUSCON0_WAITWRC_S 8 ++enum { ++ IFX_EBU_BUSCON0_WAITWRC0 = 0, ++ IFX_EBU_BUSCON0_WAITWRC1, ++ IFX_EBU_BUSCON0_WAITWRC2, ++ IFX_EBU_BUSCON0_WAITWRC3, ++ IFX_EBU_BUSCON0_WAITWRC4, ++ IFX_EBU_BUSCON0_WAITWRC5, ++ IFX_EBU_BUSCON0_WAITWRC6, ++ IFX_EBU_BUSCON0_WAITWRC7, /* Default */ ++}; ++ ++#define IFX_EBU_BUSCON0_BCGEN 0x00003000 ++#define IFX_EBU_BUSCON0_BCGEN_S 12 ++enum { ++ IFX_EBU_BUSCON0_BCGEN_CS = 0, ++ IFX_EBU_BUSCON0_BCGEN_INTEL, /* Default */ ++ IFX_EBU_BUSCON0_BCGEN_MOTOROLA, ++ IFX_EBU_BUSCON0_BCGEN_RES, ++}; ++ ++#define IFX_EBU_BUSCON0_ALEC 0x0000c000 ++#define IFX_EBU_BUSCON0_ALEC_S 14 ++enum { ++ IFX_EBU_BUSCON0_ALEC0 = 0, ++ IFX_EBU_BUSCON0_ALEC1, ++ IFX_EBU_BUSCON0_ALEC2, ++ IFX_EBU_BUSCON0_ALEC3, /* Default */ ++}; ++ ++#define IFX_EBU_BUSCON0_XDM 0x00030000 ++#define IFX_EBU_BUSCON0_XDM_S 16 ++enum { ++ IFX_EBU_BUSCON0_XDM8 = 0, ++ IFX_EBU_BUSCON0_XDM16, /* Default */ ++}; ++ ++#define IFX_EBU_BUSCON0_VN_EN 0x00040000 ++ ++#define IFX_EBU_BUSCON0_WAITINV_HI 0x00080000 /* low by default */ ++ ++#define IFX_EBU_BUSCON0_WAIT 0x00300000 ++#define IFX_EBU_BUSCON0_WAIT_S 20 ++enum { ++ IFX_EBU_BUSCON0_WAIT_DISABLE = 0, ++ IFX_EBU_BUSCON0_WAIT_ASYNC, ++ IFX_EBU_BUSCON0_WAIT_SYNC, ++}; ++#define IFX_EBU_BUSCON0_SETUP_EN 0x00400000 /* Disable by default */ ++ ++#define IFX_EBU_BUSCON0_AGEN 0x07000000 ++#define IFX_EBU_BUSCON0_AGEN_S 24 ++enum { ++ IFX_EBU_BUSCON0_AGEN_DEMUX = 0, /* Default */ ++ IFX_EBU_BUSCON0_AGEN_RES, ++ IFX_EBU_BUSCON0_AGEN_MUX, ++}; ++ ++#define IFX_EBU_BUSCON0_PG_EN 0x20000000 ++#define IFX_EBU_BUSCON0_ADSWP 0x40000000 /* Disable by default */ ++#define IFX_EBU_BUSCON0_WRDIS 0x80000000 /* Disable by default */ ++ ++/***EBU Bus Configuration Register 1***/ ++#define IFX_EBU_BUSCON1 ((volatile u32*)(IFX_EBU + 0x0064)) ++#define IFX_EBU_BUSCON1_CMULT 0x00000003 ++#define IFX_EBU_BUSCON1_CMULT_S 0 ++enum { ++ IFX_EBU_BUSCON1_CMULT1 = 0, ++ IFX_EBU_BUSCON1_CMULT4, ++ IFX_EBU_BUSCON1_CMULT8, ++ IFX_EBU_BUSCON1_CMULT16, /* Default after reset */ ++ }; ++ ++#define IFX_EBU_BUSCON1_RECOVC 0x00000000c ++#define IFX_EBU_BUSCON1_RECOVC_S 2 ++enum { ++ IFX_EBU_BUSCON1_RECOVC0 = 0, ++ IFX_EBU_BUSCON1_RECOVC1, ++ IFX_EBU_BUSCON1_RECOVC2, ++ IFX_EBU_BUSCON1_RECOVC3, /* Default */ ++ }; ++#define IFX_EBU_BUSCON1_HOLDC 0x00000030 ++#define IFX_EBU_BUSCON1_HOLDC_S 4 ++enum { ++ IFX_EBU_BUSCON1_HOLDC0 = 0, ++ IFX_EBU_BUSCON1_HOLDC1, ++ IFX_EBU_BUSCON1_HOLDC2, ++ IFX_EBU_BUSCON1_HOLDC3, /* Default */ ++ }; ++#define IFX_EBU_BUSCON1_WAITRDC 0x000000c0 ++#define IFX_EBU_BUSCON1_WAITRDC_S 6 ++enum { ++ IFX_EBU_BUSCON1_WAITRDC0 = 0, ++ IFX_EBU_BUSCON1_WAITRDC1, ++ IFX_EBU_BUSCON1_WAITRDC2, ++ IFX_EBU_BUSCON1_WAITRDC3, /* Default */ ++ }; ++#define IFX_EBU_BUSCON1_WAITWRC 0x00000700 ++#define IFX_EBU_BUSCON1_WAITWRC_S 8 ++enum { ++ IFX_EBU_BUSCON1_WAITWRC0 = 0, ++ IFX_EBU_BUSCON1_WAITWRC1, ++ IFX_EBU_BUSCON1_WAITWRC2, ++ IFX_EBU_BUSCON1_WAITWRC3, ++ IFX_EBU_BUSCON1_WAITWRC4, ++ IFX_EBU_BUSCON1_WAITWRC5, ++ IFX_EBU_BUSCON1_WAITWRC6, ++ IFX_EBU_BUSCON1_WAITWRC7, /* Default */ ++ }; ++#define IFX_EBU_BUSCON1_BCGEN 0x00003000 ++#define IFX_EBU_BUSCON1_BCGEN_S 12 ++enum { ++ IFX_EBU_BUSCON1_BCGEN_CS = 0, ++ IFX_EBU_BUSCON1_BCGEN_INTEL, /* Default */ ++ IFX_EBU_BUSCON1_BCGEN_MOTOROLA, ++ IFX_EBU_BUSCON1_BCGEN_RES, ++ }; ++#define IFX_EBU_BUSCON1_ALEC 0x0000c000 ++#define IFX_EBU_BUSCON1_ALEC_S 14 ++enum { ++ IFX_EBU_BUSCON1_ALEC0 = 0, ++ IFX_EBU_BUSCON1_ALEC1, ++ IFX_EBU_BUSCON1_ALEC2, ++ IFX_EBU_BUSCON1_ALEC3, /* Default */ ++ }; ++ ++#define IFX_EBU_BUSCON1_SETUP (1 << 22) ++ ++#define IFX_EBU_BUSCON1_WRDIS (1 << 31) ++//#define IFX_EBU_BUSCON1_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) ++//#define IFX_EBU_BUSCON1_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) ++//#define IFX_EBU_BUSCON1_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) ++//#define IFX_EBU_BUSCON1_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) ++//#define IFX_EBU_BUSCON1_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) ++//#define IFX_EBU_BUSCON1_WAITINV (1 << 19) ++//#define IFX_EBU_BUSCON1_SETUP (1 << 18) ++//#define IFX_EBU_BUSCON1_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) ++//#define IFX_EBU_BUSCON1_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) ++//#define IFX_EBU_BUSCON1_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) ++//#define IFX_EBU_BUSCON1_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) ++//#define IFX_EBU_BUSCON1_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) ++//#define IFX_EBU_BUSCON1_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) ++ ++/***EBU Bus Configuration Register 2***/ ++#define IFX_EBU_BUSCON2 ((volatile u32*)(IFX_EBU + 0x0068)) ++#define IFX_EBU_BUSCON2_WRDIS (1 << 31) ++#define IFX_EBU_BUSCON2_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) ++#define IFX_EBU_BUSCON2_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) ++#define IFX_EBU_BUSCON2_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) ++#define IFX_EBU_BUSCON2_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) ++#define IFX_EBU_BUSCON2_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) ++#define IFX_EBU_BUSCON2_WAITINV (1 << 19) ++#define IFX_EBU_BUSCON2_SETUP (1 << 18) ++#define IFX_EBU_BUSCON2_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) ++#define IFX_EBU_BUSCON2_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) ++#define IFX_EBU_BUSCON2_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) ++#define IFX_EBU_BUSCON2_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) ++#define IFX_EBU_BUSCON2_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) ++#define IFX_EBU_BUSCON2_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) ++ ++/***EBU Bus Configuration Register 2***/ ++#define IFX_EBU_BUSCON3 ((volatile u32*)(IFX_EBU + 0x006C)) ++#define IFX_EBU_BUSCON3_WRDIS (1 << 31) ++#define IFX_EBU_BUSCON3_ADSWP(value) (1 << 30) ++#define IFX_EBU_BUSCON3_PG_EN(value) (1 << 29) ++#define IFX_EBU_BUSCON3_AGEN(value) (((( 1 << 3) - 1) & (value)) << 24) ++#define IFX_EBU_BUSCON3_SETUP (1 << 22) ++#define IFX_EBU_BUSCON3_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) ++#define IFX_EBU_BUSCON3_WAITINV (1 << 19) ++#define IFX_EBU_BUSCON3_VN_EN (1 << 18) ++#define IFX_EBU_BUSCON3_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) ++#define IFX_EBU_BUSCON3_ALEC(value) (((( 1 << 2) - 1) & (value)) << 14) ++#define IFX_EBU_BUSCON3_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 12) ++#define IFX_EBU_BUSCON3_WAITWDC(value) (((( 1 << 4) - 1) & (value)) << 8) ++#define IFX_EBU_BUSCON3_WAITRRC(value) (((( 1 << 2) - 1) & (value)) << 6) ++#define IFX_EBU_BUSCON3_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) ++#define IFX_EBU_BUSCON3_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) ++#define IFX_EBU_BUSCON3_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) ++ ++#define IFX_EBU_PCC_ISTAT IFX_EBU_ECC_ISTAT ++#define IFX_EBU_ECC_ISTAT ((volatile u32*)(IFX_EBU+ 0x00A0)) ++#define IFX_EBU_ECC_IEN ((volatile u32*)(IFX_EBU+ 0x00A4)) ++#define IFX_EBU_ECC_IEN_PCI_EN 0x00000010 ++ ++#define IFX_EBU_ECC_INT_OUT ((volatile u32*)(IFX_EBU+ 0x00A8)) ++ ++#define IFX_EBU_NAND_CON (volatile u32*)(IFX_EBU + 0xB0) ++#define IFX_EBU_NAND_WAIT (volatile u32*)(IFX_EBU + 0xB4) ++#define IFX_EBU_NAND_ECC0 (volatile u32*)(IFX_EBU + 0xB8) ++#define IFX_EBU_NAND_ECC_AC (volatile u32*)(IFX_EBU + 0xBC) ++#define IFX_EBU_NAND_ECC_CR (volatile u32*)(IFX_EBU + 0xC0) ++#define IFX_EBU_SYN_CON1 (volatile u32*)(IFX_EBU + 0xC4) ++ ++#define IFX_EBU_NAND_CON_NANDM (1<<0) ++#define IFX_EBU_NAND_CON_NANDM_S 0 ++enum { ++ IFX_EBU_NAND_CON_NANDM_DISABLE = 0,/* Default after reset */ ++ IFX_EBU_NAND_CON_NANDM_ENABLE, ++ }; ++ ++#define IFX_EBU_NAND_CON_CSMUX_E (1<<1) ++#define IFX_EBU_NAND_CON_CSMUX_E_S 1 ++enum { ++ IFX_EBU_NAND_CON_CSMUX_E_DISABLE = 0,/* Default after reset */ ++ IFX_EBU_NAND_CON_CSMUX_E_ENABLE, ++ }; ++ ++#define IFX_EBU_NAND_CON_ALE_P (1<<2) ++#define IFX_EBU_NAND_CON_ALE_P_S 2 ++enum { ++ IFX_EBU_NAND_CON_ALE_P_HIGH = 0, ++ IFX_EBU_NAND_CON_ALE_P_LOW, ++}; ++ ++#define IFX_EBU_NAND_CON_CLE_P (1<<3) ++#define IFX_EBU_NAND_CON_CLE_P_S 3 ++enum { ++ IFX_EBU_NAND_CON_CLE_P_HIGH = 0, ++ IFX_EBU_NAND_CON_CLE_P_LOW, ++}; ++ ++#define IFX_EBU_NAND_CON_CS_P (1<<4) ++#define IFX_EBU_NAND_CON_CS_P_S 4 ++enum { ++ IFX_EBU_NAND_CON_CS_P_HIGH = 0, ++ IFX_EBU_NAND_CON_CS_P_LOW, /* Default after reset */ ++ }; ++ ++#define IFX_EBU_NAND_CON_SE_P (1<<5) ++#define IFX_EBU_NAND_CON_SE_P_S 5 ++enum { ++ IFX_EBU_NAND_CON_SE_P_HIGH = 0, ++ IFX_EBU_NAND_CON_SE_P_LOW, /* Default after reset */ ++ }; ++#define IFX_EBU_NAND_CON_WP_P (1<<6) ++#define IFX_EBU_NAND_CON_WP_P_S 6 ++enum { ++ IFX_EBU_NAND_CON_WP_P_HIGH = 0, ++ IFX_EBU_NAND_CON_WP_P_LOW, /* Default after reset */ ++ }; ++ ++#define IFX_EBU_NAND_CON_PRE_P (1<<7) ++#define IFX_EBU_NAND_CON_PRE_P_S 7 ++enum { ++ IFX_EBU_NAND_CON_PRE_P_HIGH = 0, ++ IFX_EBU_NAND_CON_PRE_P_LOW, /* Default after reset */ ++ }; ++ ++#define IFX_EBU_NAND_CON_IN_CS (3<<8) ++#define IFX_EBU_NAND_CON_IN_CS_S 8 ++enum { ++ IFX_EBU_NAND_CON_IN_CS0 = 0, /* Default after reset */ ++ IFX_EBU_NAND_CON_IN_CS1, ++ }; ++ ++#define IFX_EBU_NAND_CON_OUT_CS (3<<10) ++#define IFX_EBU_NAND_CON_OUT_CS_S 10 ++enum { ++ IFX_EBU_NAND_CON_OUT_CS0 = 0, /* Default after reset */ ++ IFX_EBU_NAND_CON_OUT_CS1, ++ }; ++ ++#define IFX_EBU_NAND_CON_ECC (1<<31) ++#define IFX_EBU_NAND_CON_ECC_S 31 ++enum { ++ IFX_EBU_NAND_CON_ECC_OFF = 0, ++ IFX_EBU_NAND_CON_ECC_ON, ++}; ++ ++#define IFX_EBU_NAND_CON_LAT_EN (0x3F << 18) ++#define IFX_EBU_NAND_CON_LAT_EN_S 18 ++enum { ++ IFX_EBU_NAND_CON_LAT_EN_DEF = 0x3D, ++}; ++ ++#define IFX_EBU_NAND_ECC_CRM (1<<31) ++#define IFX_EBU_NAND_ECC_CRM_S 31 ++enum { ++ IFX_EBU_NAND_ECC_CRM_DISABLE = 0, ++ IFX_EBU_NAND_ECC_CRM_ENABLE, ++}; ++ ++#define IFX_EBU_NAND_ECC_PAGE (3<<14) ++#define IFX_EBU_NAND_ECC_PAGE_S 14 ++enum { ++ IFX_EBU_NAND_ECC_PAGE_256 = 0, ++ IFX_EBU_NAND_ECC_PAGE_512, ++ IFX_EBU_NAND_ECC_PAGE_RES, ++}; ++ ++#define IFX_EBU_ECC_IEN_IR (1<<5) ++#define IFX_EBU_ECC_IEN_IR_S 5 ++enum { ++ IFX_EBU_ECC_IEN_DISABLE = 0, ++ IFX_EBU_ECC_IEN_ENABLE, ++}; ++ ++#define IFX_EBU_NAND_ECC_STATE (3<<0) ++#define IFX_EBU_NAND_ECC_STATE_S 0 ++ ++#define IFX_EBU_NAND_ECC_ROW_VAL (0x1FF<<5) ++#define IFX_EBU_NAND_ECC_ROW_VAL_S 5 ++ ++#define IFX_EBU_NAND_ECC_BIT_POS (7<<2) ++#define IFX_EBU_NAND_ECC_BIT_POS_S 2 ++ ++#define IFX_EBU_NAND_WAIT_RD (0x1) ++#define IFX_EBU_NAND_WAIT_BY_E (1<<1) ++#define IFX_EBU_NAND_WAIT_RD_E (1<<2) ++#define IFX_EBU_NAND_WAIT_WR_C (1<<3) ++ ++#if 0 //YLH: Not exist anymore ++/***********************************************************************/ ++/* Module : SDRAM register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_SDRAM (KSEG1 | 0x1F800000) ++ ++/***MC Access Error Cause Register***/ ++#define IFX_SDRAM_MC_ERRCAUSE ((volatile u32*)(IFX_SDRAM + 0x0100)) ++#define IFX_SDRAM_MC_ERRCAUSE_ERR (1 << 31) ++#define IFX_SDRAM_MC_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16) ++#define IFX_SDRAM_MC_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_ERRCAUSE_Res(value) (((( 1 << NaN) - 1) & (value)) << NaN) ++ ++/***MC Access Error Address Register***/ ++#define IFX_SDRAM_MC_ERRADDR ((volatile u32*)(IFX_SDRAM + 0x0108)) ++ ++/***MC I/O General Purpose Register***/ ++#define IFX_SDRAM_MC_IOGP ((volatile u32*)(IFX_SDRAM + 0x0800)) ++#define IFX_SDRAM_MC_IOGP_GPR6(value) (((( 1 << 4) - 1) & (value)) << 28) ++#define IFX_SDRAM_MC_IOGP_GPR5(value) (((( 1 << 4) - 1) & (value)) << 24) ++#define IFX_SDRAM_MC_IOGP_GPR4(value) (((( 1 << 4) - 1) & (value)) << 20) ++#define IFX_SDRAM_MC_IOGP_GPR3(value) (((( 1 << 4) - 1) & (value)) << 16) ++#define IFX_SDRAM_MC_IOGP_GPR2(value) (((( 1 << 4) - 1) & (value)) << 12) ++#define IFX_SDRAM_MC_IOGP_CPS (1 << 11) ++#define IFX_SDRAM_MC_IOGP_CLKDELAY(value) (((( 1 << 3) - 1) & (value)) << 8) ++#define IFX_SDRAM_MC_IOGP_CLKRAT(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_IOGP_RDDEL(value) (((( 1 << 4) - 1) & (value)) << 0) ++ ++/***MC Self Refresh Register***/ ++#define IFX_SDRAM_MC_SELFRFSH ((volatile u32*)(IFX_SDRAM + 0x0A00)) ++#define IFX_SDRAM_MC_SELFRFSH_PWDS (1 << 1) ++#define IFX_SDRAM_MC_SELFRFSH_PWD (1 << 0) ++#define IFX_SDRAM_MC_SELFRFSH_Res(value) (((( 1 << 30) - 1) & (value)) << 2) ++ ++/***MC Enable Register***/ ++#define IFX_SDRAM_MC_CTRLENA ((volatile u32*)(IFX_SDRAM + 0x1000)) ++#define IFX_SDRAM_MC_CTRLENA_ENA (1 << 0) ++#define IFX_SDRAM_MC_CTRLENA_Res(value) (((( 1 << 31) - 1) & (value)) << 1) ++ ++/***MC Mode Register Setup Code***/ ++#define IFX_SDRAM_MC_MRSCODE ((volatile u32*)(IFX_SDRAM + 0x1008)) ++#define IFX_SDRAM_MC_MRSCODE_UMC(value) (((( 1 << 5) - 1) & (value)) << 7) ++#define IFX_SDRAM_MC_MRSCODE_CL(value) (((( 1 << 3) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_MRSCODE_WT (1 << 3) ++#define IFX_SDRAM_MC_MRSCODE_BL(value) (((( 1 << 3) - 1) & (value)) << 0) ++ ++/***MC Configuration Data-word Width Register***/ ++#define IFX_SDRAM_MC_CFGDW ((volatile u32*)(IFX_SDRAM + 0x1010)) ++#define IFX_SDRAM_MC_CFGDW_DW(value) (((( 1 << 4) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_CFGDW_Res(value) (((( 1 << 28) - 1) & (value)) << 4) ++ ++/***MC Configuration Physical Bank 0 Register***/ ++#define IFX_SDRAM_MC_CFGPB0 ((volatile u32*)(IFX_SDRAM + 0x1018)) ++#define IFX_SDRAM_MC_CFGPB0_MCSEN0(value) (((( 1 << 4) - 1) & (value)) << 12) ++#define IFX_SDRAM_MC_CFGPB0_BANKN0(value) (((( 1 << 4) - 1) & (value)) << 8) ++#define IFX_SDRAM_MC_CFGPB0_ROWW0(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_CFGPB0_COLW0(value) (((( 1 << 4) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_CFGPB0_Res(value) (((( 1 << 16) - 1) & (value)) << 16) ++ ++/***MC Latency Register***/ ++#define IFX_SDRAM_MC_LATENCY ((volatile u32*)(IFX_SDRAM + 0x1038)) ++#define IFX_SDRAM_MC_LATENCY_TRP(value) (((( 1 << 4) - 1) & (value)) << 16) ++#define IFX_SDRAM_MC_LATENCY_TRAS(value) (((( 1 << 4) - 1) & (value)) << 12) ++#define IFX_SDRAM_MC_LATENCY_TRCD(value) (((( 1 << 4) - 1) & (value)) << 8) ++#define IFX_SDRAM_MC_LATENCY_TDPL(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_LATENCY_TDAL(value) (((( 1 << 4) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_LATENCY_Res(value) (((( 1 << 12) - 1) & (value)) << 20) ++ ++/***MC Refresh Cycle Time Register***/ ++#define IFX_SDRAM_MC_TREFRESH ((volatile u32*)(IFX_SDRAM + 0x1040)) ++#define IFX_SDRAM_MC_TREFRESH_TREF(value) (((( 1 << 13) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_TREFRESH_Res(value) (((( 1 << 19) - 1) & (value)) << 13) ++ ++/***MC Status Register***/ ++#define IFX_SDRAM_MC_STAT ((volatile u32*)(IFX_SDRAM + 0x0070)) ++ ++/***MC DDR Control Register 00***/ ++#define IFX_DDR_MC_DC00 ((volatile u32*)(IFX_SDRAM + 0x1000)) ++/***MC DDR Control Register 03***/ ++#define IFX_DDR_MC_DC03 ((volatile u32*)(IFX_SDRAM + 0x1030)) ++/***MC DDR Control Register 17***/ ++#define IFX_DDR_MC_DC17 ((volatile u32*)(IFX_SDRAM + 0x1110)) ++#endif ++ ++/***********************************************************************/ ++/* Module : ASC1 register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_ASC1 (KSEG1 | 0x1E100C00) ++ ++/***ASC Clock Control Register***/ ++#define IFX_ASC1_CLC ((volatile u32*)(IFX_ASC1 + 0x0000)) ++#define IFX_ASC1_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) ++#define IFX_ASC1_CLC_DISS (1 << 1) ++#define IFX_ASC1_CLC_DISR (1 << 0) ++ ++/***ASC Port Input Select Register***/ ++#define IFX_ASC1_PISEL ((volatile u32*)(IFX_ASC1 + 0x0004)) ++#define IFX_ASC1_ID ((volatile u32*)(IFX_ASC1 + 0x0008)) ++#define IFX_ASC1_PISEL_RIS (1 << 0) ++ ++/***ASC Control Register***/ ++#define IFX_ASC1_CON ((volatile u32*)(IFX_ASC1 + 0x0010)) ++#define IFX_ASC1_CON_BEN (1 << 20) ++#define IFX_ASC1_CON_TOEN (1 << 20) ++#define IFX_ASC1_CON_ROEN (1 << 19) ++#define IFX_ASC1_CON_RUEN (1 << 18) ++#define IFX_ASC1_CON_FEN (1 << 17) ++#define IFX_ASC1_CON_PAL (1 << 16) ++#define IFX_ASC1_CON_R (1 << 15) ++#define IFX_ASC1_CON_ACO (1 << 14) ++#define IFX_ASC1_CON_LB (1 << 13) ++#define IFX_ASC1_CON_ERCLK (1 << 10) ++#define IFX_ASC1_CON_FDE (1 << 9) ++#define IFX_ASC1_CON_BRS (1 << 8) ++#define IFX_ASC1_CON_STP (1 << 7) ++#define IFX_ASC1_CON_SP (1 << 6) ++#define IFX_ASC1_CON_ODD (1 << 5) ++#define IFX_ASC1_CON_PEN (1 << 4) ++#define IFX_ASC1_CON_M(value) (((( 1 << 3) - 1) & (value)) << 0) ++ ++/***ASC Staus Register***/ ++#define IFX_ASC1_STATE ((volatile u32*)(IFX_ASC1 + 0x0014)) ++/***ASC Write Hardware Modified Control Register***/ ++#define IFX_ASC1_WHBSTATE ((volatile u32*)(IFX_ASC1 + 0x0018)) ++#define IFX_ASC1_WHBSTATE_SETBE (1 << 113) ++#define IFX_ASC1_WHBSTATE_SETTOE (1 << 12) ++#define IFX_ASC1_WHBSTATE_SETROE (1 << 11) ++#define IFX_ASC1_WHBSTATE_SETRUE (1 << 10) ++#define IFX_ASC1_WHBSTATE_SETFE (1 << 19) ++#define IFX_ASC1_WHBSTATE_SETPE (1 << 18) ++#define IFX_ASC1_WHBSTATE_CLRBE (1 << 17) ++#define IFX_ASC1_WHBSTATE_CLRTOE (1 << 6) ++#define IFX_ASC1_WHBSTATE_CLRROE (1 << 5) ++#define IFX_ASC1_WHBSTATE_CLRRUE (1 << 4) ++#define IFX_ASC1_WHBSTATE_CLRFE (1 << 3) ++#define IFX_ASC1_WHBSTATE_CLRPE (1 << 2) ++#define IFX_ASC1_WHBSTATE_SETREN (1 << 1) ++#define IFX_ASC1_WHBSTATE_CLRREN (1 << 0) ++ ++/***ASC Baudrate Timer/Reload Register***/ ++#define IFX_ASC1_BG ((volatile u32*)(IFX_ASC1 + 0x0050)) ++#define IFX_ASC1_BG_BR_VALUE(value) (((( 1 << 13) - 1) & (value)) << 0) ++ ++/***ASC Fractional Divider Register***/ ++#define IFX_ASC1_FDV ((volatile u32*)(IFX_ASC1 + 0x0058)) ++#define IFX_ASC1_FDV_FD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) ++ ++/***ASC Transmit Buffer Register***/ ++#define IFX_ASC1_TBUF ((volatile u32*)(IFX_ASC1 + 0x0020)) ++#define IFX_ASC1_TBUF_TD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) ++ ++/***ASC Receive Buffer Register***/ ++#define IFX_ASC1_RBUF ((volatile u32*)(IFX_ASC1 + 0x0024)) ++#define IFX_ASC1_RBUF_RD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) ++ ++/***ASC Autobaud Control Register***/ ++#define IFX_ASC1_ABCON ((volatile u32*)(IFX_ASC1 + 0x0030)) ++#define IFX_ASC1_ABCON_RXINV (1 << 11) ++#define IFX_ASC1_ABCON_TXINV (1 << 10) ++#define IFX_ASC1_ABCON_ABEM(value) (((( 1 << 2) - 1) & (value)) << 8) ++#define IFX_ASC1_ABCON_FCDETEN (1 << 4) ++#define IFX_ASC1_ABCON_ABDETEN (1 << 3) ++#define IFX_ASC1_ABCON_ABSTEN (1 << 2) ++#define IFX_ASC1_ABCON_AUREN (1 << 1) ++#define IFX_ASC1_ABCON_ABEN (1 << 0) ++ ++/***Receive FIFO Control Register***/ ++#define IFX_ASC1_RXFCON ((volatile u32*)(IFX_ASC1 + 0x0040)) ++#define IFX_ASC1_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) ++#define IFX_ASC1_RXFCON_RXFFLU (1 << 1) ++#define IFX_ASC1_RXFCON_RXFEN (1 << 0) ++ ++/***Transmit FIFO Control Register***/ ++#define IFX_ASC1_TXFCON ((volatile u32*)(IFX_ASC1 + 0x0044)) ++#define IFX_ASC1_TXFCON_TXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) ++#define IFX_ASC1_TXFCON_TXFFLU (1 << 1) ++#define IFX_ASC1_TXFCON_TXFEN (1 << 0) ++ ++/***FIFO Status Register***/ ++#define IFX_ASC1_FSTAT ((volatile u32*)(IFX_ASC1 + 0x0048)) ++#define IFX_ASC1_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8) ++#define IFX_ASC1_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0) ++#define IFX_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) ++#define IFX_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) ++#define IFX_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) ++#define IFX_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) ++#define IFX_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) ++#define IFX_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) ++#define IFX_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) ++#define IFX_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) ++ ++ ++/***ASC Autobaud Status Register***/ ++#define IFX_ASC1_ABSTAT ((volatile u32*)(IFX_ASC1 + 0x0034)) ++#define IFX_ASC1_ABSTAT_DETWAIT (1 << 4) ++#define IFX_ASC1_ABSTAT_SCCDET (1 << 3) ++#define IFX_ASC1_ABSTAT_SCSDET (1 << 2) ++#define IFX_ASC1_ABSTAT_FCCDET (1 << 1) ++#define IFX_ASC1_ABSTAT_FCSDET (1 << 0) ++ ++/***ASC Write HW Modified Autobaud Status Register***/ ++#define IFX_ASC1_WHBABSTAT ((volatile u32*)(IFX_ASC1 + 0x003C)) ++#define IFX_ASC1_WHBABSTAT_SETDETWAIT (1 << 9) ++#define IFX_ASC1_WHBABSTAT_CLRDETWAIT (1 << 8) ++#define IFX_ASC1_WHBABSTAT_SETSCCDET (1 << 7) ++#define IFX_ASC1_WHBABSTAT_CLRSCCDET (1 << 6) ++#define IFX_ASC1_WHBABSTAT_SETSCSDET (1 << 5) ++#define IFX_ASC1_WHBABSTAT_CLRSCSDET (1 << 4) ++#define IFX_ASC1_WHBABSTAT_SETFCCDET (1 << 3) ++#define IFX_ASC1_WHBABSTAT_CLRFCCDET (1 << 2) ++#define IFX_ASC1_WHBABSTAT_SETFCSDET (1 << 1) ++#define IFX_ASC1_WHBABSTAT_CLRFCSDET (1 << 0) ++ ++/***ASC IRNCR0 **/ ++#define IFX_ASC1_IRNREN ((volatile u32*)(IFX_ASC1 + 0x00F4)) ++#define IFX_ASC1_IRNICR ((volatile u32*)(IFX_ASC1 + 0x00FC)) ++/***ASC IRNCR1 **/ ++#define IFX_ASC1_IRNCR ((volatile u32*)(IFX_ASC1 + 0x00F8)) ++#define IFX_ASC_IRNCR_TIR 0x1 ++#define IFX_ASC_IRNCR_RIR 0x2 ++#define IFX_ASC_IRNCR_EIR 0x4 ++ ++ ++ ++/***********************************************************************/ ++/* Module : DMA register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_DMA (KSEG1 | 0x1E104100) ++ ++#define IFX_DMA_BASE IFX_DMA ++#define IFX_DMA_CLC (volatile u32*)(IFX_DMA_BASE + 0x00) ++#define IFX_DMA_ID (volatile u32*)(IFX_DMA_BASE + 0x08) ++#define IFX_DMA_CTRL (volatile u32*)(IFX_DMA_BASE + 0x10) ++#define IFX_DMA_CPOLL (volatile u32*)(IFX_DMA_BASE + 0x14) ++ ++#define IFX_DMA_CS(i) (volatile u32*)(IFX_DMA_BASE + 0x18 + 0x38 * (i)) ++#define IFX_DMA_CCTRL(i) (volatile u32*)(IFX_DMA_BASE + 0x1C + 0x38 * (i)) ++#define IFX_DMA_CDBA(i) (volatile u32*)(IFX_DMA_BASE + 0x20 + 0x38 * (i)) ++#define IFX_DMA_CDLEN(i) (volatile u32*)(IFX_DMA_BASE + 0x24 + 0x38 * (i)) ++#define IFX_DMA_CIS(i) (volatile u32*)(IFX_DMA_BASE + 0x28 + 0x38 * (i)) ++#define IFX_DMA_CIE(i) (volatile u32*)(IFX_DMA_BASE + 0x2C + 0x38 * (i)) ++ ++#define IFX_DMA_CGBL (volatile u32*)(IFX_DMA_BASE + 0x30) ++#define IFX_DMA_CDPTNRD (volatile u32*)(IFX_DMA_BASE + 0x34) ++ ++#define IFX_DMA_PS(i) (volatile u32*)(IFX_DMA_BASE + 0x40 + 0x30 * (i)) ++#define IFX_DMA_PCTRL(i) (volatile u32*)(IFX_DMA_BASE + 0x44 + 0x30 * (i)) ++ ++#define IFX_DMA_IRNEN (volatile u32*)(IFX_DMA_BASE + 0xf4) ++#define IFX_DMA_IRNCR (volatile u32*)(IFX_DMA_BASE + 0xf8) ++#define IFX_DMA_IRNICR (volatile u32*)(IFX_DMA_BASE + 0xfc) ++/* Global Software Reset (0) */ ++#define IFX_DMA_CTRL_RST (0x1) ++ ++/* Channel Polling Register */ ++ ++/* Enable (31) */ ++#define IFX_DMA_CPOLL_EN (0x1 << 31) ++#define IFX_DMA_CPOLL_EN_VAL(val) (((val) & 0x1) << 31) ++ ++/* Counter (15:4) */ ++#define IFX_DMA_CPOLL_CNT (0xfff << 4) ++#define IFX_DMA_CPOLL_CNT_VAL(val) (((val) & 0xfff) << 4) ++ ++/* Channel Control Register */ ++ ++/* Peripheral to Peripheral Copy (24) */ ++#define IFX_DMA_CCTRL_P2PCPY (0x1 << 24) ++#define IFX_DMA_CCTRL_P2PCPY_VAL(val) (((val) & 0x1) << 24) ++#define IFX_DMA_CCTRL_P2PCPY_GET(val) ((((val) & IFX_DMA_CCTRL_P2PCPY) >> 24) & 0x1) ++ ++/* Channel Weight for Transmit Direction (17:16) */ ++#define IFX_DMA_CCTRL_TXWGT (0x3 << 16) ++#define IFX_DMA_CCTRL_TXWGT_VAL(val) (((val) & 0x3) << 16) ++#define IFX_DMA_CCTRL_TXWGT_GET(val) ((((val) & IFX_DMA_CCTRL_TXWGT) >> 16) & 0x3) ++ ++/* Port Assignment (13:11) */ ++#define IFX_DMA_CCTRL_PRTNR (0x7 << 11) ++#define IFX_DMA_CCTRL_PRTNR_GET(val) ((((val) & IFX_DMA_CCTRL_PRTNR) >> 11) & 0x7) ++ ++/* Class (10:9) */ ++#define IFX_DMA_CCTRL_CLASS (0x3 << 9) ++#define IFX_DMA_CCTRL_CLASS_VAL(val) (((val) & 0x3) << 9) ++#define IFX_DMA_CCTRL_CLASS_GET(val) ((((val) & IFX_DMA_CCTRL_CLASS) >> 9) & 0x3) ++ ++/* Direction (8) */ ++#define IFX_DMA_CCTRL_DIR (0x1 << 8) ++/* Reset (1) */ ++#define IFX_DMA_CCTRL_RST (0x1 << 1) ++/* Channel On or Off (0) */ ++#define IFX_DMA_CCTRL_ON (0x1) ++ ++/* Channel Interrupt Status Register */ ++ ++/* SAI Read Error Interrupt (5) */ ++#define IFX_DMA_CIS_RDERR (0x1 << 5) ++/* Channel Off Interrupt (4) */ ++#define IFX_DMA_CIS_CHOFF (0x1 << 4) ++/* Descriptor Complete Interrupt (3) */ ++#define IFX_DMA_CIS_DESCPT (0x1 << 3) ++/* Descriptor Under-Run Interrupt (2) */ ++#define IFX_DMA_CIS_DUR (0x1 << 2) ++/* End of Packet Interrupt (1) */ ++#define IFX_DMA_CIS_EOP (0x1 << 1) ++ ++#define IFX_DMA_CIS_ALL (IFX_DMA_CIS_RDERR | IFX_DMA_CIS_CHOFF| \ ++ IFX_DMA_CIS_DESCPT | IFX_DMA_CIS_DUR | \ ++ IFX_DMA_CIS_EOP) ++ ++/* Channel Interrupt Enable Register */ ++ ++/* SAI Read Error Interrupt (5) */ ++#define IFX_DMA_CIE_RDERR (0x1 << 5) ++/* Channel Off Interrupt (4) */ ++#define IFX_DMA_CIE_CHOFF (0x1 << 4) ++/* Descriptor Complete Interrupt Enable (3) */ ++#define IFX_DMA_CIE_DESCPT (0x1 << 3) ++/* Descriptor Under Run Interrupt Enable (2) */ ++#define IFX_DMA_CIE_DUR (0x1 << 2) ++/* End of Packet Interrupt Enable (1) */ ++#define IFX_DMA_CIE_EOP (0x1 << 1) ++ ++#define IFX_DMA_CIE_DEFAULT (IFX_DMA_CIE_DESCPT | IFX_DMA_CIE_EOP) ++ ++/* Port Select Register */ ++ ++/* Port Selection (2:0) */ ++#define IFX_DMA_PS_PS (0x7) ++#define IFX_DMA_PS_PS_VAL(val) (((val) & 0x7) << 0) ++ ++/* Port Control Register */ ++ ++/* General Purpose Control (16) */ ++#define IFX_DMA_PCTRL_GPC (0x1 << 16) ++#define IFX_DMA_PCTRL_GPC_VAL(val) (((val) & 0x1) << 16) ++ ++/* Port Weight for Transmit Direction (14:12) */ ++#define IFX_DMA_PCTRL_TXWGT (0x7 << 12) ++#define IFX_DMA_PCTRL_TXWGT_VAL(val) (((val) & 0x7) << 12) ++/* Endianness for Transmit Direction (11:10) */ ++#define IFX_DMA_PCTRL_TXENDI (0x3 << 10) ++#define IFX_DMA_PCTRL_TXENDI_VAL(val) (((val) & 0x3) << 10) ++/* Endianness for Receive Direction (9:8) */ ++#define IFX_DMA_PCTRL_RXENDI (0x3 << 8) ++#define IFX_DMA_PCTRL_RXENDI_VAL(val) (((val) & 0x3) << 8) ++/* Packet Drop Enable (6) */ ++#define IFX_DMA_PCTRL_PDEN (0x1 << 6) ++#define IFX_DMA_PCTRL_PDEN_VAL(val) (((val) & 0x1) << 6) ++/* Burst Length for Transmit Direction (5:4) */ ++#define IFX_DMA_PCTRL_TXBL (0x3 << 4) ++#define IFX_DMA_PCTRL_TXBL_VAL(val) (((val) & 0x3) << 4) ++/* Burst Length for Receive Direction (3:2) */ ++#define IFX_DMA_PCTRL_RXBL (0x3 << 2) ++#define IFX_DMA_PCTRL_RXBL_VAL(val) (((val) & 0x3) << 2) ++ ++ ++ ++/***********************************************************************/ ++/* Module : Debug register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_Debug (KSEG1 | 0x1F106000) ++ ++/***MCD Break Bus Switch Register***/ ++#define IFX_Debug_MCD_BBS ((volatile u32*)(IFX_Debug + 0x0000)) ++#define IFX_Debug_MCD_BBS_BTP1 (1 << 19) ++#define IFX_Debug_MCD_BBS_BTP0 (1 << 18) ++#define IFX_Debug_MCD_BBS_BSP1 (1 << 17) ++#define IFX_Debug_MCD_BBS_BSP0 (1 << 16) ++#define IFX_Debug_MCD_BBS_BT5EN (1 << 15) ++#define IFX_Debug_MCD_BBS_BT4EN (1 << 14) ++#define IFX_Debug_MCD_BBS_BT5 (1 << 13) ++#define IFX_Debug_MCD_BBS_BT4 (1 << 12) ++#define IFX_Debug_MCD_BBS_BS5EN (1 << 7) ++#define IFX_Debug_MCD_BBS_BS4EN (1 << 6) ++#define IFX_Debug_MCD_BBS_BS5 (1 << 5) ++#define IFX_Debug_MCD_BBS_BS4 (1 << 4) ++ ++/***MCD Multiplexer Control Register***/ ++#define IFX_Debug_MCD_MCR ((volatile u32*)(IFX_Debug+ 0x0008)) ++#define IFX_Debug_MCD_MCR_MUX5 (1 << 4) ++#define IFX_Debug_MCD_MCR_MUX4 (1 << 3) ++#define IFX_Debug_MCD_MCR_MUX1 (1 << 0) ++ ++ ++ ++/***********************************************************************/ ++/* Module : ICU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_ICU (KSEG1 | 0x1F880200) ++ ++#define IFX_ICU_IM0_ISR ((volatile u32*)(IFX_ICU + 0x0000)) ++#define IFX_ICU_IM0_IER ((volatile u32*)(IFX_ICU + 0x0008)) ++#define IFX_ICU_IM0_IOSR ((volatile u32*)(IFX_ICU + 0x0010)) ++#define IFX_ICU_IM0_IRSR ((volatile u32*)(IFX_ICU + 0x0018)) ++#define IFX_ICU_IM0_IMR ((volatile u32*)(IFX_ICU + 0x0020)) ++ ++#define IFX_ICU_IM1_ISR ((volatile u32*)(IFX_ICU + 0x0028)) ++#define IFX_ICU_IM1_IER ((volatile u32*)(IFX_ICU + 0x0030)) ++#define IFX_ICU_IM1_IOSR ((volatile u32*)(IFX_ICU + 0x0038)) ++#define IFX_ICU_IM1_IRSR ((volatile u32*)(IFX_ICU + 0x0040)) ++#define IFX_ICU_IM1_IMR ((volatile u32*)(IFX_ICU + 0x0048)) ++ ++#define IFX_ICU_IM2_ISR ((volatile u32*)(IFX_ICU + 0x0050)) ++#define IFX_ICU_IM2_IER ((volatile u32*)(IFX_ICU + 0x0058)) ++#define IFX_ICU_IM2_IOSR ((volatile u32*)(IFX_ICU + 0x0060)) ++#define IFX_ICU_IM2_IRSR ((volatile u32*)(IFX_ICU + 0x0068)) ++#define IFX_ICU_IM2_IMR ((volatile u32*)(IFX_ICU + 0x0070)) ++ ++#define IFX_ICU_IM3_ISR ((volatile u32*)(IFX_ICU + 0x0078)) ++#define IFX_ICU_IM3_IER ((volatile u32*)(IFX_ICU + 0x0080)) ++#define IFX_ICU_IM3_IOSR ((volatile u32*)(IFX_ICU + 0x0088)) ++#define IFX_ICU_IM3_IRSR ((volatile u32*)(IFX_ICU + 0x0090)) ++#define IFX_ICU_IM3_IMR ((volatile u32*)(IFX_ICU + 0x0098)) ++ ++#define IFX_ICU_IM4_ISR ((volatile u32*)(IFX_ICU + 0x00A0)) ++#define IFX_ICU_IM4_IER ((volatile u32*)(IFX_ICU + 0x00A8)) ++#define IFX_ICU_IM4_IOSR ((volatile u32*)(IFX_ICU + 0x00B0)) ++#define IFX_ICU_IM4_IRSR ((volatile u32*)(IFX_ICU + 0x00B8)) ++#define IFX_ICU_IM4_IMR ((volatile u32*)(IFX_ICU + 0x00C0)) ++ ++/***Interrupt Vector Value Register***/ ++#define IFX_ICU_IM_VEC ((volatile u32*)(IFX_ICU + 0x00C8)) ++ ++/***********************************************************************/ ++ ++#define IFX_ICU_VPE1 (KSEG1 | 0x1F880300) ++#define IFX_ICU1 IFX_ICU_VPE1 ++ ++#define IFX_ICU_VPE1_IM0_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0000)) ++#define IFX_ICU_VPE1_IM0_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0008)) ++#define IFX_ICU_VPE1_IM0_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0010)) ++#define IFX_ICU_VPE1_IM0_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0018)) ++#define IFX_ICU_VPE1_IM0_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0020)) ++ ++#define IFX_ICU_VPE1_IM1_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0028)) ++#define IFX_ICU_VPE1_IM1_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0030)) ++#define IFX_ICU_VPE1_IM1_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0038)) ++#define IFX_ICU_VPE1_IM1_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0040)) ++#define IFX_ICU_VPE1_IM1_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0048)) ++ ++#define IFX_ICU_VPE1_IM2_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0050)) ++#define IFX_ICU_VPE1_IM2_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0058)) ++#define IFX_ICU_VPE1_IM2_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0060)) ++#define IFX_ICU_VPE1_IM2_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0068)) ++#define IFX_ICU_VPE1_IM2_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0070)) ++ ++#define IFX_ICU_VPE1_IM3_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0078)) ++#define IFX_ICU_VPE1_IM3_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0080)) ++#define IFX_ICU_VPE1_IM3_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0088)) ++#define IFX_ICU_VPE1_IM3_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0090)) ++#define IFX_ICU_VPE1_IM3_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0098)) ++ ++#define IFX_ICU_VPE1_IM4_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x00A0)) ++#define IFX_ICU_VPE1_IM4_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x00A8)) ++#define IFX_ICU_VPE1_IM4_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x00B0)) ++#define IFX_ICU_VPE1_IM4_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x00B8)) ++#define IFX_ICU_VPE1_IM4_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x00C0)) ++ ++/***Interrupt Vector Value Register***/ ++#define IFX_ICU_VPE1_IM_VEC ((volatile u32*)(IFX_ICU_VPE1 + 0x00C8)) ++#define IFX_ICU_IM_VEC1 IFX_ICU_VPE1_IM_VEC ++ ++/* MSI PIC */ ++#define IFX_MSI_PIC_REG_BASE (KSEG1 | 0x1F700000) ++ ++#define IFX_MSI_PIC_BIG_ENDIAN 1 ++#define IFX_MSI_PIC_LITTLE_ENDIAN 0 ++ ++#define IFX_MSI_PCI_INT_DISABLE 0x80000000 ++#define IFX_MSI_PIC_INT_LINE 0x30000000 ++#define IFX_MSI_PIC_INT_LINE_S 28 ++#define IFX_MSI_PIC_MSG_ADDR 0x0FFF0000 ++#define IFX_MSI_PIC_MSG_ADDR_S 16 ++#define IFX_MSI_PIC_MSG_DATA 0x0000FFFF ++#define IFX_MSI_PIC_MSG_DATA_S 0x0 ++ ++/***Interrupt Vector Value Mask***/ ++#define IFX_ICU_IM0_VEC_MASK (0x3F << 0) ++#define IFX_ICU_IM1_VEC_MASK (0x3F << 6) ++#define IFX_ICU_IM2_VEC_MASK (0x3F << 12) ++#define IFX_ICU_IM3_VEC_MASK (0x3F << 18) ++#define IFX_ICU_IM4_VEC_MASK (0x3F << 24) ++ ++/***External Interrupt Control Register***/ ++#define IFX_ICU_EIU (KSEG1 | 0x1F101000) ++#define IFX_ICU_EIU_EXIN_C ((volatile u32 *)(IFX_ICU_EIU + 0x0000)) ++#define IFX_ICU_EIU_INIC ((volatile u32 *)(IFX_ICU_EIU + 0x0004)) ++#define IFX_ICU_EIU_INC ((volatile u32 *)(IFX_ICU_EIU + 0x0008)) ++#define IFX_ICU_EIU_INEN ((volatile u32 *)(IFX_ICU_EIU + 0x000C)) ++#define IFX_YIELDEN(n) ((volatile u32 *)(IFX_ICU_EIU + 0x0010 + (n) * 4) ++#define IFX_NMI_CR ((volatile u32 *)(IFX_ICU_EIU + 0x00F0)) ++#define IFX_NMI_SR ((volatile u32 *)(IFX_ICU_EIU + 0x00F4)) ++ ++ ++ ++/***********************************************************************/ ++/* Module : MPS register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_MPS (KSEG1 | 0x1F107000) ++ ++#define IFX_MPS_CHIPID ((volatile u32*)(IFX_MPS + 0x0344)) ++#define IFX_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) ++#define IFX_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) ++#define IFX_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) ++#define IFX_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12) ++#define IFX_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) ++#define IFX_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1) ++ ++ ++/* notification enable register */ ++#define IFX_MPS_CPU0_NFER ((volatile u32*)(IFX_MPS + 0x0060)) ++#define IFX_MPS_CPU1_NFER ((volatile u32*)(IFX_MPS + 0x0064)) ++/* CPU to CPU interrup request register */ ++#define IFX_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(IFX_MPS + 0x0070)) ++#define IFX_MPS_CPU0_2_CPU1_IER ((volatile u32*)(IFX_MPS + 0x0074)) ++/* Global interrupt request and request enable register */ ++#define IFX_MPS_GIRR ((volatile u32*)(IFX_MPS + 0x0078)) ++#define IFX_MPS_GIER ((volatile u32*)(IFX_MPS + 0x007C)) ++#define IFX_MPS_VPE0_2_VPE1_ICR ((volatile u32*)(IFX_MPS + 0x0080)) ++#define IFX_MPS_VPE0_2_VPE1_IRDR ((volatile u32*)(IFX_MPS + 0x0084)) ++#define IFX_MPS_GIRDR ((volatile u32*)(IFX_MPS + 0x0088)) ++#define IFX_MPS_GICR ((volatile u32*)(IFX_MPS + 0x008C)) ++#define IFX_MPS_VPE0_NFICR ((volatile u32*)(IFX_MPS + 0x0090)) ++#define IFX_MPS_VPE1_NFICR ((volatile u32*)(IFX_MPS + 0x0094)) ++#define IFX_MPS_VPE0_BINSEM0 ((volatile u32*)(IFX_MPS + 0x0100)) ++#define IFX_MPS_VPE1_BINSEM0 ((volatile u32*)(IFX_MPS + 0x0200)) ++ ++#define IFX_MPS_SRAM ((volatile u32*)(KSEG1 | 0x1F200000)) ++ ++#define IFX_MPS_VCPU_FW_AD ((volatile u32*)(KSEG1 | 0x1F2001E0)) ++ ++//YLH: 0x354 is FAB_LOT_ID0, 0x35C is chip configuration fuse register ++// ++#define IFX_FUSE_BASE_ADDR (KSEG1 | 0x1F107354) ++ ++/************************************************************************/ ++/* Module : XBAR Register definition */ ++/************************************************************************/ ++#define IFX_XBAR_REG_BASE (KSEG1 | 0x1F400000) ++ ++#define IFX_XBAR_ALWAYS_LAST (volatile u32*)(IFX_XBAR_REG_BASE + 0x430) ++#define IFX_XBAR_FPI_BURST_EN 0x00000002 ++#define IFX_XBAR_AHB_BURST_EN 0x00000004 ++#define IFX_XBAR_DDR_SEL_EN 0x00000001 ++ ++/* ++ * Routine for Voice ++ */ ++extern const void (*ifx_bsp_basic_mps_decrypt)(unsigned int addr, int n); ++ ++#endif /* HN1_H */ +diff --git a/arch/mips/include/asm/ifx/hn1/hn1_eval_board.h b/arch/mips/include/asm/ifx/hn1/hn1_eval_board.h +new file mode 100644 +index 0000000..e017045 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/hn1/hn1_eval_board.h +@@ -0,0 +1,36 @@ ++/****************************************************************************** ++** ++** FILE NAME : hn1_eval_board.h ++** MODULES : BSP Basic ++** ++** DATE : 11 Jan 2011 ++** AUTHOR : Kishore Kankipati ++** DESCRIPTION : header file for HN1 ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 11 Jan 2011 Kishore First version for HN1 derived from VR9 ++*******************************************************************************/ ++ ++#ifndef HN1_EVAL_BOARD_H ++#define HN1_EVAL_BOARD_H ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++ ++#if defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) \ ++ || defined(CONFIG_IFX_USIF_SPI_FLASH) || defined (CONFIG_IFX_USIF_SPI_FLASH_MODULE) ++#define IFX_MTD_SPI_PART_NB 3 ++#define IFX_SPI_FLASH_MAX 8 ++#endif /* defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) */ ++ ++#endif /* HN1_EVAL_BOARD_H */ ++ +diff --git a/arch/mips/include/asm/ifx/hn1/hn1_ref_board.h b/arch/mips/include/asm/ifx/hn1/hn1_ref_board.h +new file mode 100644 +index 0000000..330f65d +--- /dev/null ++++ b/arch/mips/include/asm/ifx/hn1/hn1_ref_board.h +@@ -0,0 +1,36 @@ ++/****************************************************************************** ++** ++** FILE NAME : hn1_ref_board.h ++** MODULES : BSP Basic ++** ++** DATE : 11 Jan 2011 ++** AUTHOR : Kishore Kankipati ++** DESCRIPTION : header file for HN1 ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 11 Jan 2011 Kishore First version for HN1 derived from VR9 ++*******************************************************************************/ ++ ++#ifndef HN1_REF_BOARD_H ++#define HN1_REF_BOARD_H ++#ifndef AUTOCONF_INCLUDED ++#include ++#endif /* AUTOCONF_INCLUDED */ ++ ++#if defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) \ ++ || defined(CONFIG_IFX_USIF_SPI_FLASH) || defined (CONFIG_IFX_USIF_SPI_FLASH_MODULE) ++#define IFX_MTD_SPI_PART_NB 3 ++#define IFX_SPI_FLASH_MAX 8 ++#endif /* defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) */ ++ ++#endif /* HN1_REF_BOARD_H */ ++ +diff --git a/arch/mips/include/asm/ifx/hn1/irq.h b/arch/mips/include/asm/ifx/hn1/irq.h +new file mode 100644 +index 0000000..4700d5e +--- /dev/null ++++ b/arch/mips/include/asm/ifx/hn1/irq.h +@@ -0,0 +1,183 @@ ++/****************************************************************************** ++** ++** FILE NAME : irq.h ++** PROJECT : HN1 ++** MODULES : BSP Basic ++** ++** DATE : 11 January 2011 ++** AUTHOR : Kishore Kankipati ++** DESCRIPTION : header file for HN1 ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 11 Jan 2011 Kishore Kankipati The first HN1 release (file derived from VR9) ++** 11 Feb 2011 Yinglei Modified for HN1 ++** 13 May 2011 Kishore Kankipati Added defintion of missing interrupts. ++*******************************************************************************/ ++ ++ ++#ifndef HN1_IRQ_H ++#define HN1_IRQ_H ++ ++ ++ ++/****** Interrupt Assigments based on HN1_SOC_SAS_V1.0.4_Spec.pdf, P. 701-707***********/ ++ ++#define IFX_ASC1_TIR INT_NUM_IM3_IRL7 /* TX interrupt */ ++#define IFX_ASC1_TBIR INT_NUM_IM3_IRL8 /* TX buffer interrupt */ ++#define IFX_ASC1_RIR INT_NUM_IM3_IRL9 /* RX interrupt */ ++#define IFX_ASC1_EIR INT_NUM_IM3_IRL10 /* ERROR interrupt */ ++#define IFX_ASC1_ABSTIR INT_NUM_IM3_IRL11 ++#define IFX_ASC1_ABDETIR INT_NUM_IM3_IRL12 ++#define IFX_ASC1_SFCIR INT_NUM_IM3_IRL13 ++ ++#define IFX_FPI_SLAVE_BCU0_IR INT_NUM_IM1_IRL25 ++#define IFX_FPI_MASTER_COSBCU_IR INT_NUM_IM0_IRL25 ++#define IFX_CROSSBAR_ERR_IR INT_NUM_IM4_IRL23 ++#define IFX_FPI_SLAVE_BCU_IRQ IFX_FPI_SLAVE_BCU0_IR ++#define IFX_FPI_MASTER_BCU_IRQ IFX_FPI_MASTER_COSBCU_IR ++ ++#define IFX_HN1_ZERO_CROSS_INT INT_NUM_IM1_IRL21 ++#define IFX_HN1_DFE_INT0IR INT_NUM_IM2_IRL12 ++#define IFX_HN1_DFE_INT1IR INT_NUM_IM2_IRL13 ++#define IFX_HN1_DFE_INT2IR INT_NUM_IM2_IRL14 ++#define IFX_HN1_DFE_INT3IR INT_NUM_IM2_IRL15 ++#define IFX_HN1_DFE_TXIR IFX_HN1_DFE_INT0IR ++#define IFX_HN1_DFE_RXIR IFX_HN1_DFE_INT1IR ++ ++#define IFX_PCIE_INTA INT_NUM_IM4_IRL8 ++#define IFX_PCIE_INTB INT_NUM_IM4_IRL9 ++#define IFX_PCIE_INTC INT_NUM_IM4_IRL10 ++#define IFX_PCIE_INTD INT_NUM_IM4_IRL11 ++#define IFX_PCIE_IR INT_NUM_IM4_IRL25 ++#define IFX_PCIE_WAKE INT_NUM_IM4_IRL26 ++#define IFX_PCIE_MSI_IR0 INT_NUM_IM4_IRL27 ++#define IFX_PCIE_MSI_IR1 INT_NUM_IM4_IRL28 ++#define IFX_PCIE_MSI_IR2 INT_NUM_IM4_IRL29 ++#define IFX_PCIE_MSI_IR3 INT_NUM_IM0_IRL30 ++#define IFX_PCIE_L3_INT INT_NUM_IM3_IRL16 ++ ++#define IFX_HN1_I2C_IR0 INT_NUM_IM1_IRL3 ++#define IFX_HN1_I2C_IR1 INT_NUM_IM1_IRL4 ++#define IFX_HN1_I2C_IR2 INT_NUM_IM1_IRL5 ++#define IFX_HN1_I2C_IR3 INT_NUM_IM1_IRL6 ++#define IFX_HN1_I2C_IR4 INT_NUM_IM1_IRL7 ++#define IFX_HN1_I2C_IR5 INT_NUM_IM1_IRL8 ++ ++#define IFX_HN1_I2S_IR0 INT_NUM_IM0_IRL11 ++#define IFX_HN1_I2S_IR1 INT_NUM_IM0_IRL12 ++#define IFX_HN1_I2S_IR2 INT_NUM_IM0_IRL23 ++#define IFX_HN1_I2S_IR3 INT_NUM_IM0_IRL24 ++#define IFX_HN1_I2S_IR4 INT_NUM_IM0_IRL26 ++#define IFX_HN1_I2S_IR5 INT_NUM_IM0_IRL27 ++#define IFX_HN1_I2S_IR6 INT_NUM_IM0_IRL28 ++#define IFX_HN1_I2S_IR7 INT_NUM_IM0_IRL29 ++#define IFX_HN1_I2S_IR8 INT_NUM_IM0_IRL31 ++ ++#define IFX_DMA_CH0_INT INT_NUM_IM2_IRL0 ++#define IFX_DMA_CH1_INT INT_NUM_IM2_IRL1 ++#define IFX_DMA_CH2_INT INT_NUM_IM2_IRL2 ++#define IFX_DMA_CH3_INT INT_NUM_IM2_IRL3 ++#define IFX_DMA_CH4_INT INT_NUM_IM2_IRL4 ++#define IFX_DMA_CH5_INT INT_NUM_IM2_IRL5 ++#define IFX_DMA_CH6_INT INT_NUM_IM2_IRL6 ++#define IFX_DMA_CH7_INT INT_NUM_IM2_IRL7 ++#define IFX_DMA_CH8_INT INT_NUM_IM2_IRL8 ++#define IFX_DMA_CH9_INT INT_NUM_IM2_IRL9 ++#define IFX_DMA_CH10_INT INT_NUM_IM2_IRL10 ++#define IFX_DMA_CH11_INT INT_NUM_IM2_IRL11 ++#define IFX_DMA_CH12_INT INT_NUM_IM2_IRL25 ++#define IFX_DMA_CH13_INT INT_NUM_IM2_IRL26 ++#define IFX_DMA_CH14_INT INT_NUM_IM2_IRL27 ++#define IFX_DMA_CH15_INT INT_NUM_IM2_IRL28 ++#define IFX_DMA_CH16_INT INT_NUM_IM2_IRL29 ++#define IFX_DMA_CH17_INT INT_NUM_IM1_IRL30 ++#define IFX_DMA_CH18_INT INT_NUM_IM2_IRL16 ++#define IFX_DMA_CH19_INT INT_NUM_IM2_IRL21 ++#define IFX_DMA_CH20_INT INT_NUM_IM4_IRL0 ++#define IFX_DMA_CH21_INT INT_NUM_IM4_IRL1 ++#define IFX_DMA_CH22_INT INT_NUM_IM4_IRL2 ++#define IFX_DMA_CH23_INT INT_NUM_IM4_IRL3 ++#define IFX_DMA_CH24_INT INT_NUM_IM4_IRL4 ++#define IFX_DMA_CH25_INT INT_NUM_IM4_IRL5 ++#define IFX_DMA_CH26_INT INT_NUM_IM4_IRL6 ++#define IFX_DMA_CH27_INT INT_NUM_IM4_IRL7 ++#define IFX_DMA_FCC_INT INT_NUM_IM0_IRL13 ++ ++#define IFX_GE_SW_INT INT_NUM_IM1_IRL16 ++ ++#define IFX_GPHY_INT INT_NUM_IM3_IRL18 ++ ++#define IFX_EIU_IR0 INT_NUM_IM4_IRL30 /* 158 */ ++#define IFX_EIU_IR1 INT_NUM_IM3_IRL31 /* 127 */ ++#define IFX_EIU_IR2 INT_NUM_IM1_IRL26 /* 58 */ ++#define IFX_EIU_IR3 INT_NUM_IM1_IRL0 /* 32 */ ++#define IFX_EIU_IR4 INT_NUM_IM1_IRL1 /* 33 */ ++#define IFX_EIU_IR5 INT_NUM_IM1_IRL2 /* 34 */ ++#define IFX_EIU_IR6 INT_NUM_IM2_IRL30 /* 94 */ ++ ++#define IFX_MPS_IR0 INT_NUM_IM4_IRL14 ++#define IFX_MPS_IR1 INT_NUM_IM4_IRL15 ++#define IFX_MPS_IR2 INT_NUM_IM4_IRL16 ++#define IFX_MPS_IR3 INT_NUM_IM4_IRL17 ++#define IFX_MPS_IR4 INT_NUM_IM4_IRL18 ++#define IFX_MPS_IR5 INT_NUM_IM4_IRL19 ++#define IFX_MPS_IR6 INT_NUM_IM4_IRL20 ++#define IFX_MPS_IR7 INT_NUM_IM4_IRL21 ++#define IFX_MPS_IR8 INT_NUM_IM4_IRL22 ++#define IFX_MPS_SEMAPHORE_IR IFX_MPS_IR7 ++#define IFX_MPS_GLOBAL_IR IFX_MPS_IR8 ++ ++#define IFX_RTI_8KHZ_IR INT_NUM_IM2_IRL31 ++ ++#define IFX_GPTU_TC1A INT_NUM_IM3_IRL22 ++#define IFX_GPTU_TC1B INT_NUM_IM3_IRL23 ++#define IFX_GPTU_TC2A INT_NUM_IM3_IRL24 ++#define IFX_GPTU_TC2B INT_NUM_IM3_IRL25 ++#define IFX_GPTU_TC3A INT_NUM_IM3_IRL26 ++#define IFX_GPTU_TC3B INT_NUM_IM3_IRL27 ++ ++#define IFX_MC_IR INT_NUM_IM3_IRL28 ++ ++#define IFX_EBU_IR INT_NUM_IM0_IRL22 ++ ++#define IFX_PCI_IR INT_NUM_IM1_IRL17 ++#define IFX_PCI_WRIR INT_NUM_IM1_IRL18 ++ ++#define IFX_PCM_TXIR INT_NUM_IM1_IRL19 ++#define IFX_PCM_RXIR INT_NUM_IM1_IRL20 ++ ++#define IFX_PMCIR INT_NUM_IM4_IRL31 ++ ++#define IFX_SBIU_ERRIR INT_NUM_IM1_IRL27 ++ ++#define IFX_SSC_RIR INT_NUM_IM0_IRL14 ++#define IFX_SSC_TIR INT_NUM_IM0_IRL15 ++#define IFX_SSC_EIR INT_NUM_IM0_IRL16 ++#define IFX_SSC_FIR INT_NUM_IM0_IRL17 ++ ++#define IFX_MMC_CONTROLLER_INTR0_IRQ INT_NUM_IM0_IRL18 ++#define IFX_MMC_CONTROLLER_INTR1_IRQ INT_NUM_IM0_IRL19 ++#define IFX_MMC_CONTROLLER_SDIO_I_IRQ INT_NUM_IM0_IRL20 ++ ++#define IFX_WDT_AEIR INT_NUM_IM4_IRL24 ++ ++#define IFX_USIF_EIR_INT INT_NUM_IM3_IRL3 ++#define IFX_USIF_STA_INT INT_NUM_IM3_IRL4 ++#define IFX_USIF_AB_INT INT_NUM_IM3_IRL5 ++#define IFX_USIF_WKP_INT INT_NUM_IM3_IRL6 ++#define IFX_USIF_TX_INT INT_NUM_IM0_IRL21 ++#define IFX_USIF_RX_INT INT_NUM_IM3_IRL21 ++ ++#define IFX_AHB1S_BUS_ERROR INT_NUM_IM3_IRL1 ++ ++#endif // HN1_IRQ_H ++ +diff --git a/arch/mips/include/asm/ifx/hn1/model.h b/arch/mips/include/asm/ifx/hn1/model.h +new file mode 100644 +index 0000000..b7ac967 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/hn1/model.h +@@ -0,0 +1,28 @@ ++/****************************************************************************** ++** ++** FILE NAME : model.h ++** MODULES : BSP Basic ++** ++** DATE : 11 Jan 2011 ++** AUTHOR : Kishore ++** DESCRIPTION : header file for HN1 ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 11 Jan 2011 Kishore ++*******************************************************************************/ ++ ++ ++#ifndef HN1_MODEL_H ++#define HN1_MODEL_H ++#define BOARD_SYSTEM_TYPE "HNX100" ++#define SYSTEM_MODEL_NAME "HNX Eval Version" ++#endif +diff --git a/arch/mips/include/asm/ifx/ifx_atm.h b/arch/mips/include/asm/ifx/ifx_atm.h +new file mode 100644 +index 0000000..bf045a9 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_atm.h +@@ -0,0 +1,196 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_atm.h ++** PROJECT : UEIP ++** MODULES : ATM ++** ++** DATE : 17 Jun 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : Global ATM driver header file ++** COPYRIGHT : Copyright (c) 2006 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 07 JUL 2009 Xu Liang Init Version ++*******************************************************************************/ ++ ++#ifndef IFX_ATM_H ++#define IFX_ATM_H ++ ++ ++ ++/*! ++ \defgroup IFX_ATM UEIP Project - ATM driver module ++ \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9. ++ */ ++ ++/*! ++ \defgroup IFX_ATM_IOCTL IOCTL Commands ++ \ingroup IFX_ATM ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_ATM_STRUCT Structures ++ \ingroup IFX_ATM ++ \brief Structures used by user application. ++ */ ++ ++/*! ++ \file ifx_atm.h ++ \ingroup IFX_ATM ++ \brief ATM driver header file ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_ATM_STRUCT ++ */ ++/*@{*/ ++ ++/* ++ * ATM MIB ++ */ ++ ++/*! ++ \struct atm_cell_ifEntry_t ++ \brief Structure used for Cell Level MIB Counters. ++ ++ User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL". ++ */ ++typedef struct { ++ __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */ ++ __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */ ++ __u32 ifInErrors; /*!< counter of error ingress cells */ ++ __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */ ++ __u32 ifOutErrors; /*!< counter of error egress cells */ ++} atm_cell_ifEntry_t; ++ ++/*! ++ \struct atm_aal5_ifEntry_t ++ \brief Structure used for AAL5 Frame Level MIB Counters. ++ ++ User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5". ++ */ ++typedef struct { ++ __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */ ++ __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */ ++ __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */ ++ __u32 ifInUcastPkts; /*!< counter of ingress packets */ ++ __u32 ifOutUcastPkts; /*!< counter of egress packets */ ++ __u32 ifInErrors; /*!< counter of error ingress packets */ ++ __u32 ifInDiscards; /*!< counter of dropped ingress packets */ ++ __u32 ifOutErros; /*!< counter of error egress packets */ ++ __u32 ifOutDiscards; /*!< counter of dropped egress packets */ ++} atm_aal5_ifEntry_t; ++ ++/*! ++ \struct atm_aal5_vcc_t ++ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. ++ ++ This structure is a part of structure "atm_aal5_vcc_x_t". ++ */ ++typedef struct { ++ __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */ ++ __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet ++ __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */ ++} atm_aal5_vcc_t; ++ ++/*! ++ \struct atm_aal5_vcc_x_t ++ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. ++ ++ User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC". ++ */ ++typedef struct { ++ int vpi; /*!< VPI of the VCC to get MIB counters */ ++ int vci; /*!< VCI of the VCC to get MIB counters */ ++ atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */ ++} atm_aal5_vcc_x_t; ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * IOCTL ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_ATM_IOCTL ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Command ++ */ ++/*! ++ \brief ATM IOCTL Magic Number ++ */ ++#define PPE_ATM_IOC_MAGIC 'o' ++/*! ++ \brief ATM IOCTL Command - Get Cell Level MIB Counters ++ ++ This command is obsolete. User can get cell level MIB from DSL API. ++ This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters. ++ */ ++#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t) ++/*! ++ \brief ATM IOCTL Command - Get AAL5 Level MIB Counters ++ ++ Get AAL5 packet counters. ++ This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters. ++ */ ++#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t) ++/*! ++ \brief ATM IOCTL Command - Get Per PVC MIB Counters ++ ++ Get AAL5 packet counters for each PVC. ++ This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters. ++ */ ++#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t) ++/*! ++ \brief Total Number of ATM IOCTL Commands ++ */ ++#define PPE_ATM_IOC_MAXNR 3 ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * API ++ * #################################### ++ */ ++ ++#ifdef __KERNEL__ ++struct port_cell_info { ++ unsigned int port_num; ++ unsigned int tx_link_rate[2]; ++}; ++#endif ++ ++ ++ ++#endif // IFX_ATM_H ++ +diff --git a/arch/mips/include/asm/ifx/ifx_board.h b/arch/mips/include/asm/ifx/ifx_board.h +new file mode 100644 +index 0000000..e5706e5 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_board.h +@@ -0,0 +1,52 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_board.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : common header file ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef IFX_BOARD_H ++#define IFX_BOARD_H ++ ++ ++ ++#if defined(CONFIG_DANUBE) ++# include "danube/danube_ref_board.h" ++#elif defined(CONFIG_AMAZON_SE) ++# include "amazon_se/boards/boards.h" ++#elif defined(CONFIG_AR9) || defined(CONFIG_AR9_CUSTOM_BOARD) ++# include "ar9/ar9_ref_board.h" ++#elif defined(CONFIG_VR9) ++# include "vr9/vr9_ref_board.h" ++#elif defined(CONFIG_AR10) ++# include "ar10/ar10_ref_board.h" ++#elif defined(CONFIG_HN1_EVAL_BOARD) ++# include "hn1/hn1_eval_board.h" ++#elif defined(CONFIG_HN1) ++# include "hn1/hn1_ref_board.h" ++#else ++# error unknown board ++#endif ++ ++ ++ ++#endif // IFX_BOARD_H ++ +diff --git a/arch/mips/include/asm/ifx/ifx_clk.h b/arch/mips/include/asm/ifx/ifx_clk.h +new file mode 100644 +index 0000000..ad45bdf +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_clk.h +@@ -0,0 +1,140 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_clk.h ++** PROJECT : IFX UEIP ++** MODULES : CGU ++** ++** DATE : 28 May 2009 ++** AUTHOR : Huang Xiaogang ++** DESCRIPTION : IFX Cross-Platform Clock Generation Unit driver header file ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 28 May 2009 Huang Xiaogang The first UEIP release ++*******************************************************************************/ ++ ++#ifndef IFX_CLK_H ++#define IFX_CLK_H ++ ++/*! ++ \defgroup IFX_CGU UEIP Project - CGU driver module ++ \brief UEIP Project - CGU driver module, support Danube, Amazon-SE, AR9, VR9. ++ */ ++ ++/*! ++ \defgroup IFX_CGU_API APIs ++ \ingroup IFX_CGU ++ \brief APIs used by other drivers/modules. ++ */ ++ ++/*! ++ \defgroup IFX_CGU_IOCTL IOCTL Commands ++ \ingroup IFX_CGU ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_CGU_STRUCT Structures ++ \ingroup IFX_CGU ++ \brief Structures used by user application. ++ */ ++ ++/*! \file ifx_clk.h ++ \brief This file contains the interface of clock(cgu) driver. ++*/ ++ ++#define IFX_CGU_MAJOR 246 ++ ++#define IFX_CGU_VER_MAJOR 1 ++#define IFX_CGU_VER_MID 1 ++#define IFX_CGU_VER_MINOR 32 ++ ++/*! ++ \addtogroup IFX_CGU_STRUCT ++ */ ++/*@{*/ ++ ++/*! ++ \struct ifx_cgu_ioctl_version ++ \brief Structure used for query of driver version. ++ */ ++struct ifx_cgu_ioctl_version { ++ unsigned int major; /*!< output, major number of driver */ ++ unsigned int mid; /*!< output, mid number of driver */ ++ unsigned int minor; /*!< output, minor number of driver */ ++}; ++/*@}*/ ++ ++/*! ++ \addtogroup IFX_CGU_IOCTL ++ */ ++/*@{*/ ++#define IFX_CGU_IOC_MAGIC 'u' ++/*! ++ \def IFX_CGU_GET_CLOCK_RATES ++ \brief Get Clock rates ++ */ ++#define IFX_CGU_GET_CLOCK_RATES _IOR(IFX_CGU_IOC_MAGIC, 0, struct cgu_clock_rates) ++/*! ++ \def IFX_CGU_IOC_VERSION ++ \brief Get CGU driver version ++ */ ++#define IFX_CGU_IOC_VERSION _IOR(IFX_CGU_IOC_MAGIC, 1, struct ifx_cgu_ioctl_version) ++#define CGU_IOC_MAXNR 1 ++/*@}*/ ++ ++#ifndef CONFIG_USE_EMULATOR ++ #define PLL0_CLK_SPEED 1000000000 ++#endif ++ ++/* ++ * Data Type Used to Call ioctl(GET_CLOCK_RATES) ++ */ ++struct cgu_clock_rates { ++ u32 mips0; ++ u32 mips1; ++ u32 cpu; ++ u32 io_region; ++ u32 fpi_bus1; ++ u32 fpi_bus2; ++ u32 pp32; ++ u32 pci; ++ u32 mii0; ++ u32 mii1; ++ u32 usb; ++ u32 clockout0; ++ u32 clockout1; ++ u32 clockout2; ++ u32 clockout3; ++}; ++ ++#if defined(__KERNEL__) ++ extern u32 cgu_get_cpu_clock(void); ++ extern u32 cgu_get_io_region_clock(void); ++#if defined(CONFIG_VR9) || defined(CONFIG_HN1) ++ extern u32 ifx_get_ddr_hz(void); ++#endif ++#if defined(CONFIG_DANUBE) || defined(CONFIG_VR9) || defined(CONFIG_AR10) || defined(CONFIG_HN1) ++ extern u32 cgu_get_mips_clock(int); ++ extern u32 cgu_get_fpi_bus_clock (int); ++#else ++ extern u32 cgu_get_mips_clock(void); ++ extern u32 cgu_get_fpi_bus_clock(void); ++#endif ++ extern u32 cgu_get_pp32_clock(void); ++ extern u32 cgu_get_qsb_clock(void); ++ extern u32 cgu_get_pci_clock(void); ++ extern u32 cgu_get_ethernet_clock(void); ++ extern u32 cgu_get_usb_clock(void); ++ extern u32 cgu_get_clockout(int); ++#endif // defined(__KERNEL__) ++ ++#endif // IFX_CLK_H +diff --git a/arch/mips/include/asm/ifx/ifx_dcdc.h b/arch/mips/include/asm/ifx/ifx_dcdc.h +new file mode 100644 +index 0000000..75bb9c1 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_dcdc.h +@@ -0,0 +1,255 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_dcdc.h ++** PROJECT : IFX UEIP ++** MODULES : IFX DCDC converter driver ++** DATE : 07 Dec 2010 ++** AUTHOR : Sameer Ahmad ++** DESCRIPTION : IFX Cross platform DCDC converter driver ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 07 Dec 2010 Sameer Ahmad ++*******************************************************************************/ ++#ifndef _IFX_DCDC_H_ ++#define _IFX_DCDC_H_ ++#include "linux/spinlock.h" ++ ++//#define IFX_DEBUG ++#ifdef IFX_DEBUG ++#define IFX_DCDC_PRINT(format, arg...) \ ++ printk(format, ##arg) ++#else ++#define IFX_DCDC_PRINT(format, arg...) \ ++ do {} while(0) ++#endif ++ ++/*DCDC drive ioctl control*/ ++ ++/*DCDC driver IOCTL magic number*/ ++#define IFX_DCDC_IOCTL_MAGIC 0xd0 ++/*IOCTL command to read the DCDC driver version*/ ++#define IFX_DCDC_VERSION _IOR(IFX_DCDC_IOCTL_MAGIC, 0, char*) ++/*IOCTL comand to read the power state*/ ++#define IFX_DCDC_PWSTATE_QUERY _IOR(IFX_DCDC_IOCTL_MAGIC, 1, int) ++/*IOCTL command to query the voltage*/ ++#define IFX_DCDC_VOLTAGE_QUERY _IOR(IFX_DCDC_IOCTL_MAGIC, 2, int) ++/*IOCTL command to query the voltage level*/ ++#define IFX_DCDC_VOLTAGE_LEVEL_QUERY _IOR(IFX_DCDC_IOCTL_MAGIC, 3, int) ++ ++/* Name of the DCDC device*/ ++#define IFX_DCDC_DEV_NAME "ifx_dcdc" ++#define IFX_DCDC_DEV_NAMSIZ 16 ++#define IFX_DCDC_DRV_VERSION "1.0.3" ++#define IFX_SUCCESS 0 ++#define IFX_ERROR -1 ++/* DCDC Converter Core Voltage Level: Table to Map the Power state to voltage ++* is maintained by the CPU driver and we define the core voltage level params ++* as integers and following is the mapping ++* 930 ----> .93 V ++* 1000 ----> 1.0 V ++* 1175 ----> 1.175 V ++*/ ++#define IFX_DCDC_CORE_VOLTAGE_930 930 ++#define IFX_DCDC_CORE_VOLTAGE_1000 1000 ++#define IFX_DCDC_CORE_VOLTAGE_1050 1050 ++#define IFX_DCDC_CORE_VOLTAGE_1175 1175 ++#define IFX_DCDC_MAX_VOLTAGE_LEVELS 3 ++#define IFX_DIGREF_DEFAULT_VALUE 1000 ++#define IFX_DIGREF_DEFAULT_BITMASK 0x7f ++ ++/*Define Bit mask corrosponding to the core voltage*/ ++#define IFX_DCDC_CORE_VOLTAGE_930_BITMASK 0x0 ++#define IFX_DCDC_CORE_VOLTAGE_1000_BITMASK 0x1 ++#define IFX_DCDC_CORE_VOLTAGE_1050_BITMASK 0x2 ++#define IFX_DCDC_CORE_VOLTAGE_1175_BITMASK 0x3 ++/*DCDC ABSOLUTE REGISTER BASE ADDRESS*/ ++#define IFX_DCDC_MODULE_BASE_ADDRESS 0x1F106A00 ++#define IFX_DCDC_ABSOLUTE_REGISTER_ADDR KSEG1ADDR(IFX_DCDC_MODULE_BASE_ADDRESS) ++/* ++* DCDC Device struct ++*/ ++typedef struct _dcdc_dev { ++ char name[16]; ++ int major_num; ++ int minor_num; ++ unsigned int Current_voltage; ++ unsigned int Power_state; ++ spinlock_t ifx_dcdc_lock; ++}DcDcDevt; ++ ++/* ++* DCDC Converter Registers definition ++*/ ++ ++/*Clock setup register 0*/ ++typedef union _Clock_setup0_t { ++ unsigned char byte; ++ struct _Clock_setup0_reg { ++ unsigned char mdll_byp : 1; ++ unsigned char clk_sel_p : 1; ++ unsigned char mdll_m : 6; ++ }Clock_setup0_reg; ++} __attribute__((packed)) Clock_setup0_t; ++ ++/*Clock setup register 1*/ ++typedef union _Clock_setup1_t { ++ unsigned char byte; ++ struct _Clock_setup1_reg { ++ unsigned char res0 : 2; ++ unsigned char sel_div25 : 1; ++ unsigned char clk_sel_adc : 1; ++ unsigned char mdll_ix2 : 1; ++ unsigned char mdll_res : 2; ++ unsigned char res1 : 1; ++ }Clock_setup1_reg; ++} __attribute__((packed)) Clock_setup1_t; ++ ++/*BIAS setting register*/ ++typedef union _Bias_Vreg0_t { ++ unsigned char byte; ++ struct _Bias_reg { ++ unsigned char res0 : 1; ++ unsigned char ii_loadinc : 1; ++ unsigned char ii_red : 1; ++ unsigned char vreg_sel : 2; ++ unsigned char vref_sel : 3; ++ }Bias_reg; ++} __attribute__((packed)) Bias_Vreg0_t; ++ ++/*ADC setting register*/ ++typedef union _Adc_Gen0_t { ++ unsigned char byte; ++ struct _Adc_reg0 { ++ unsigned char iset_lsb_dr : 1; ++ unsigned char del_inc_p : 1; ++ unsigned char del_inc_n : 1; ++ unsigned char out_inv : 1; ++ unsigned char os_en8 : 1; ++ unsigned char os_en : 1; ++ unsigned char pfm_mode : 1; ++ unsigned char forc_sta_dc : 1; ++ }Adc_reg0; ++} __attribute__((packed)) Adc_Gen0_t; ++ ++/*ADC setting register*/ ++typedef union _Adc_Gen1_t { ++ unsigned char byte; ++ struct _Adc_reg1 { ++ unsigned char set_ROM_sel : 2; ++ unsigned char set_coma : 3; ++ unsigned char set_compr : 3; ++ }Adc_reg1; ++} __attribute__((packed)) Adc_Gen1_t; ++ ++/*ADC Configure setting register*/ ++typedef union _Adc_CON0_t { ++ unsigned char byte; ++ struct _Adc_Con0 { ++ unsigned char res0 : 1; ++ unsigned char set_scr : 2; ++ unsigned char set_compc : 3; ++ unsigned char set_off_cal : 1; ++ unsigned char set_rsta : 1; ++ }Adc_Con0; ++} __attribute__((packed)) Adc_CON0_t; ++ ++/*ADC Configure setting register*/ ++typedef union _Adc_CON1_t { ++ unsigned char byte; ++ struct _Adc_Con1 { ++ unsigned char set_start : 4; ++ unsigned char set_Rstart : 4; ++ }Adc_Con1; ++} __attribute__((packed)) Adc_CON1_t; ++ ++/*OSC Configure setting register*/ ++typedef union _Osc_Conf_t { ++ unsigned char byte; ++ struct _Osc_Conf { ++ unsigned char pd_osc : 1; ++ unsigned char res0 : 4; ++ unsigned char SHP_By : 1; ++ unsigned char CAPUP : 1; ++ unsigned char res1 : 1; ++ }Osc_Conf; ++} __attribute__((packed)) Osc_Conf_t; ++ ++/*OSC Status register*/ ++typedef union _Osc_Status_t { ++ unsigned char byte; ++ struct _Osc_Status { ++ unsigned char res0 : 7; ++ unsigned char Clk_Det : 1; ++ }Osc_Status; ++} __attribute__((packed)) Osc_Status_t; ++ ++/*NON OV delay register*/ ++typedef union _NonOv_Delay_t { ++ unsigned char byte; ++ struct _NonOv_Delay { ++ unsigned char Delay_P :4; ++ unsigned char Delay_N :4; ++ }NonOv_Delay; ++}__attribute__((packed))NonOv_Delay_t; ++ ++/* Register MAP of DCDC converter*/ ++ ++typedef struct _Dcdc_register_map { ++ unsigned char B0_Coeh; ++ unsigned char B0_Coel; ++ unsigned char B1_Coeh; ++ unsigned char B1_Coel; ++ unsigned char B2_Coeh; ++ unsigned char B2_Coel; ++ Clock_setup0_t Clk_Set0; ++ Clock_setup1_t Clk_Set1; ++ unsigned char PWM_Confh; ++ unsigned char PWM_Confl; ++ Bias_Vreg0_t Bias_Vreg0; ++ unsigned char Bias_Vreg1; ++ Adc_Gen0_t Adc_Gen0; ++ Adc_Gen1_t Adc_Gen1; ++ Adc_CON0_t Adc_Con0; ++ Adc_CON1_t Adc_Con1; ++ unsigned char res0[5]; ++ NonOv_Delay_t Non_OV_Delay; ++ unsigned char res1; ++ unsigned char Duty_Cycle_max_sat; ++ unsigned char Duty_Cycle_min_sat; ++ unsigned char res2[6]; ++ Osc_Conf_t Osc_Conf; ++ Osc_Status_t Osc_Sta; ++} __attribute__((packed)) Dcdc_register_map; ++ ++/*Define a pointer to the platform dependent set function*/ ++typedef int (*IfxDcdcPlatformSetCallback_t)(int arg); ++/*Define a pointer to the platform dependent get function*/ ++typedef int (*IfxDcdcPlatformGetCallback_t)(void); ++/*Define a pointer to the platform dependent Enable/Disable function*/ ++typedef int (*IfxDcdcPlatformEnableDisableCallback_t)(void); ++/*CB type to set the Non-OV Delay*/ ++typedef int (*IfxDcdcPlatformSetCallbackType2_t)(unsigned int arg1, ++ unsigned int arg2); ++ ++/*Table which contains the pointers to the platform dependent callbacks ++* These callbacks would be used to access platform dependent DCDC converter ++* Registers, Each platform should provide these callbacks*/ ++typedef struct _Ifx_dcdc_platform_callbacks_table { ++ IfxDcdcPlatformSetCallback_t Ifx_dcdc_voltage_set_cb; ++ IfxDcdcPlatformGetCallback_t Ifx_dcdc_voltage_get_cb; ++ IfxDcdcPlatformSetCallback_t Ifx_dcdc_DutyCycleMax_set_cb; ++ IfxDcdcPlatformSetCallback_t Ifx_dcdc_PwmSwitchingFreq_set_cb; ++ IfxDcdcPlatformSetCallbackType2_t Ifx_dcdc_NonOvDelay_set_cb; ++ IfxDcdcPlatformEnableDisableCallback_t Ifx_dcdc_PfmModeEnable_cb; ++ IfxDcdcPlatformEnableDisableCallback_t Ifx_dcdc_PfmModeDisable_cb; ++} Ifx_dcdc_platform_callbacks_table; ++#endif +diff --git a/arch/mips/include/asm/ifx/ifx_dma_core.h b/arch/mips/include/asm/ifx/ifx_dma_core.h +new file mode 100644 +index 0000000..20c2d57 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_dma_core.h +@@ -0,0 +1,316 @@ ++/** ++** FILE NAME : ifx_dma_core.h ++** PROJECT : IFX UEIP ++** MODULES : Central DMA ++** DATE : 03 June 2009 ++** AUTHOR : Reddy Mallikarjuna ++** DESCRIPTION : IFX Cross-Platform Central DMA driver header file ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 03 June 2009 Reddy Mallikarjuna Initial release ++*******************************************************************************/ ++#ifndef _IFX_DMA_CORE_H_ ++#define _IFX_DMA_CORE_H_ ++ ++/*! ++ \defgroup IFX_DMA_CORE UEIP Project - Central DMA core driver ++ \brief UEIP Project - Central DMA core Module, supports IFX CPE platforms(Danube/ASE/ARx/VRx). ++ */ ++ ++/*! ++ \defgroup IFX_DMA_DRV_API External APIs ++ \ingroup IFX_DMA_CORE ++ \brief External APIs definitions for other modules. ++ */ ++ ++/*! ++ \defgroup IFX_DMA_DRV_STRUCTURE Driver Structures ++ \ingroup IFX_DMA_CORE ++ \brief Definitions/Structures of IFX dma core module. ++ */ ++ ++/*! ++ \file ifx_dma_core.h ++ \ingroup IFX_DMA_CORE ++ \brief Header file for IFX Central DMA core driver ++ */ ++ ++/** =============================*/ ++/* Includes */ ++/** =============================*/ ++#include ++ ++#define CONFIG_IFX_DMA_DESCRIPTOR_NUMBER 32 ++ ++/* ============================= */ ++/* Local Macros & Definitions */ ++/* ============================= */ ++/** Platform specific supported DMA channel & Devices */ ++#if defined(CONFIG_DANUBE) ++#define ENABLE_RX_DPLUS_PATH 0 ++/** Max num of ports */ ++#if !defined(ENABLE_RX_DPLUS_PATH) || !ENABLE_RX_DPLUS_PATH ++#define MAX_DMA_DEVICE_NUM 6 ++#else ++#define MAX_DMA_DEVICE_NUM 7 ++#endif ++/** Max num of dma channels */ ++#define MAX_DMA_CHANNEL_NUM 20 ++#elif defined(CONFIG_AMAZON_SE) ++/** Max num of ports */ ++#define MAX_DMA_DEVICE_NUM 3 ++/** Max num of dma channels */ ++#define MAX_DMA_CHANNEL_NUM 10 ++#elif defined(CONFIG_AR9) ++/** Max num of ports */ ++#define MAX_DMA_DEVICE_NUM 6 ++/** Max num of dma channels */ ++#define MAX_DMA_CHANNEL_NUM 20 ++#elif defined(CONFIG_VR9) ++/** Max num of ports */ ++#define MAX_DMA_DEVICE_NUM 7 ++/** Max num of dma channels */ ++#define MAX_DMA_CHANNEL_NUM 28 ++#elif defined(CONFIG_AR10) ++/** Max num of ports */ ++#define MAX_DMA_DEVICE_NUM 5 ++/** Max num of dma channels */ ++#define MAX_DMA_CHANNEL_NUM 24 ++#elif defined(CONFIG_HN1) ++/** Max num of ports */ ++#define MAX_DMA_DEVICE_NUM 6 ++/** Max num of dma channels */ ++#define MAX_DMA_CHANNEL_NUM 28 ++#else ++#error "Platform is not specified(ifx_dma_core.h)!!!\n" ++#endif ++ ++/** Config the Num of descriptors from Kernel configurations ++* or else if will take default number of descriptors per channel ++*/ ++//#ifdef CONFIG_IFX_EXTRA_CFG ++#define IFX_DMA_DESCRIPTOR_OFFSET CONFIG_IFX_DMA_DESCRIPTOR_NUMBER ++//#else ++//#define IFX_DMA_DESCRIPTOR_OFFSET 32 ++//#endif ++ ++/*! ++ \addtogroup IFX_DMA_DRV_STRUCTURE ++ */ ++/*@{*/ ++ ++/*! \enum dma_psuedeo_interrupts_t ++* \brief DMA pseudo interrupts. ++ These interrupts are generated by dma core driver to sync with client drivers to handle the data between the clinet and core driver. ++*/ ++typedef enum { ++ RCV_INT = 1, /*!< Receive psuedo interrupt */ ++ TX_BUF_FULL_INT = 2, /*!< Tx channel descriptors full interrupt */ ++ TRANSMIT_CPT_INT = 4, /*!< Tx channel descriptors available interrupt */ ++}dma_psuedeo_interrupts_t; ++ ++/*! \enum ifx_dma_channel_onOff_t ++ \brief dma channel is on/ off. ++*/ ++typedef enum { ++ IFX_DMA_CH_OFF = 0, /*!< DMA channel is OFF */ ++ IFX_DMA_CH_ON = 1, /*!< DMA channel is ON */ ++} ifx_dma_channel_onOff_t; ++ ++/*! \enum ifx_dma_class_t ++ \brief dma channel class value. ++*/ ++typedef enum { ++ IFX_DMA_CLASS_0 = 0, ++ IFX_DMA_CLASS_1, ++ IFX_DMA_CLASS_2, ++ IFX_DMA_CLASS_3, ++ IFX_DMA_CLASS_4, ++ IFX_DMA_CLASS_5, ++ IFX_DMA_CLASS_6, ++ IFX_DMA_CLASS_7, ++} ifx_dma_class_t; ++ ++/*! \enum ifx_dma_endian_t ++ \brief DMA endiannes type. ++*/ ++typedef enum { ++ IFX_DMA_ENDIAN_TYPE0 = 0, /*!< No byte Swapping */ ++ IFX_DMA_ENDIAN_TYPE1, /*!< Byte Swap(B0B1B2B3 => B1B0B3B2)*/ ++ IFX_DMA_ENDIAN_TYPE2, /*!< Word Swap (B0B1B2B3 => B2B3B0B1)*/ ++ IFX_DMA_ENDIAN_TYPE3, /*!< DWord Swap (B0B1B2B3 => B3B2B1B0) */ ++}ifx_dma_endian_t; ++ ++enum { ++ /** 2 DWORDS */ ++ IFX_DMA_BURSTL_2 = 1, ++ /** 4 DWORDS */ ++ IFX_DMA_BURSTL_4 = 2, ++ /** 8 DWORDS */ ++ IFX_DMA_BURSTL_8 = 3, ++}; ++ ++/*! \enum ifx_dma_burst_len_t ++ \brief DMA Burst length. ++*/ ++typedef enum { ++ DMA_BURSTL_2DW = 2, /*!< 2 DWORD DMA burst length */ ++ DMA_BURSTL_4DW = 4, /*!< 4 DWORD DMA burst length */ ++ DMA_BURSTL_8DW = 8, /*!< 8 DWORD DMA burst length (not supported all peripherals) */ ++}ifx_dma_burst_len_t; ++ ++/*! \typedef _dma_arbitration_info ++ \brief Parameter Structure to used to configure DMA arbitration ++ based on packet or burst also Descriptor read back enabled/disabled (Supported only VR9) ++ Used by reference dma_device_info ++*/ ++typedef struct dma_arbitration_info { ++ IFX_enDis_t packet_arbitration; /*!< enabled/disabled packet arbitration*/ ++ IFX_enDis_t multiple_burst_arbitration;/*!< Enabled/Disabled Multi burst arbitration */ ++ unsigned int multiple_burst_counter; /*!< Counter of the Multi burst arbitration(Num of bursts that served before the arbitration of another peri port)*/ ++ IFX_enDis_t desc_read_back; /*!< enabled/disabled Descriptor read back */ ++}_dma_arbitration_info; ++ ++/*! \typedef _dma_channel_info ++ \brief The parameter structure is used to configure the DMA channel info ++ when the peripheral driver need to register with DMA core device driver. ++*/ ++typedef struct dma_channel_info { ++ int rel_chan_no; /*!< Relative channel number(if more than one DMA channel for device) */ ++ int dir; /*!< Direction of channel */ ++ int irq; /*!< DMA channel IRQ number */ ++ unsigned int desc_base; /*!< Channel descriptor base address*/ ++ int desc_len; /*!< Num of descriptors per channel */ ++ int curr_desc; /*!< Current Descriptor number*/ ++ int prev_desc; /*!< Previous Descriptor number */ ++ int byte_offset; /*!< Byte offset */ ++ int desc_handle; /*!< Descriptor handled flag ( to handle Rx Descriptor by client driver)*/ ++ int weight; /*!< WFQ present weight value for DMA channel */ ++ int default_weight; /*!< WFQ default weight value to handle in driver for DMA channel */ ++ int tx_channel_weight; /*!< Config the Tx DMA channel weight value */ ++ ifx_dma_class_t class_value; /*!< Config the DMA class value */ ++ int packet_size; /*!< Size of the packet length */ ++ int channel_packet_drop_enable; /*!< Config channel based packet drop(supported only VR9)*/ ++ int channel_packet_drop_counter;/*!< Channel based packet drop counter */ ++ int peri_to_peri; /*!< Config Peripheral to Peripheral(not supported Danube) */ ++ int global_buffer_len; /*!< Config global buffer length, valid only when enabled peri_to_peri) */ ++ int loopback_enable; /*!< Config Loop back between the DMA channels (Supported only VRx)*/ ++ int loopback_channel_number; /*!< Config the loopback Channel number (supported only VRx) */ ++ int req_irq_to_free; /*!< Release the DMA channel IRQ, which was already requested */ ++ int dur; /*!< Flag for Descriptor underrun interrupt */ ++ spinlock_t irq_lock; /*!< spin lock */ ++ ifx_dma_channel_onOff_t control; /*!< Channel on/off flag */ ++ void* opt[IFX_DMA_DESCRIPTOR_OFFSET]; /*!< Optional info*/ ++ void* dma_dev; /*!< Pointing to the devices */ ++ void (*open)(struct dma_channel_info* pCh); /*!< DMA channel ON */ ++ void (*close)(struct dma_channel_info* pCh);/*!< DMA channel OFF */ ++ void (*reset)(struct dma_channel_info* pCh);/*!< Reset DMA channel */ ++ void (*enable_irq)(struct dma_channel_info* pCh);/*!< Enable DMA channel interrupt */ ++ void (*disable_irq)(struct dma_channel_info* pCh);/*!< Disable DMA channel interrupt */ ++} _dma_channel_info; ++ ++/*! \typedef _dma_device_info ++ \brief The parameter structure is used to configure the DMA Peripheral ports info ++ when the peripheral driver need to register with DMA core device driver. ++*/ ++typedef struct dma_device_info { ++ char device_name[16]; /*!< Peripheral Device name */ ++ int port_reserved; /*!< Reserve the device by client driver */ ++ int port_num; /*!< Port number */ ++ ifx_dma_burst_len_t tx_burst_len; /*!< Configure the Tx burst length */ ++ ifx_dma_burst_len_t rx_burst_len; /*!< Conigure the Rx burst length */ ++ int port_tx_weight; /*!< Configure the Port based weight value */ ++ int port_packet_drop_enable; /*!< Packet drop Enabled/Disabled*/ ++ int port_packet_drop_counter; /*!< Packet drop counter */ ++ int mem_port_control; /*!< Configure the mem port control, only used Memory Ports */ ++ ifx_dma_endian_t tx_endianness_mode; /*!< Configure the Endiannes in Tx direction */ ++ ifx_dma_endian_t rx_endianness_mode; /*!< Configure the Endiannes in Rx direction */ ++ int current_tx_chan; /*!< Current Tx channel of the device*/ ++ int current_rx_chan; /*!< Current Rx channel of the device */ ++ int num_tx_chan; /*!< Config the num of Tx channels for device */ ++ int num_rx_chan; /*!< Config the num of Rx channels for device */ ++ int max_rx_chan_num; /*!< Max number of Rx channels supported */ ++ int max_tx_chan_num; /*!< Max number of Tx channels supported */ ++ spinlock_t irq_lock; /*!< spin lock */ ++ _dma_arbitration_info arbitration_info; /*!< Structure of the arbitration config*/ ++ _dma_channel_info* tx_chan[MAX_DMA_CHANNEL_NUM]; /*!< Max number of Channesl */ ++ _dma_channel_info* rx_chan[MAX_DMA_CHANNEL_NUM]; /*!< Max number of Channesl */ ++ u8* (*buffer_alloc)(int len, int* offset, void** opt); /*!< Buffer allocation */ ++ int (*buffer_free)(u8* dataptr, void* opt); /*!< Buffer free */ ++ int (*intr_handler)(struct dma_device_info* info, int status); /*!< DMA pseudo interrupt handler */ ++ void (*activate_poll)(struct dma_device_info* dma_dev); /*!< activate the polling (Used when NAPI enables)*/ ++ void (*inactivate_poll)(struct dma_device_info* dma_dev); /*!< Deactivate the polling (used when NAPI enabled) */ ++ void * priv; /*!< Pointer to the device private structure */ ++}_dma_device_info; ++ ++/* @} */ ++ ++/** Reserve the dma device port ++* This function should call before the dma_device_register */ ++extern _dma_device_info* dma_device_reserve(char* dev_name); ++ ++/** Unreseve the dma device port ++* This function will called after the dma_device_unregister */ ++extern int dma_device_release(_dma_device_info* dev); ++ ++/** Register with DMA device driver. ++This function should call after dma_device_reserve function. ++* This function register with dma device driver to handle dma functionality. ++* Should provide the required configuration info during the register with dma device. ++* if not provide config info, then take default values. */ ++extern int dma_device_register(_dma_device_info* info); ++ ++/** Unregister with DMA core driver ++* This function unregister with dma core driver. Once it unregister there is no ++* DMA handling with client driver.*/ ++extern int dma_device_unregister(_dma_device_info* info); ++ ++/** Read data packet from DMA Rx channel. ++* This function gets the data from the current rx descriptor of the DMA channel and send ++* to the client driver. ++* This functions is called when the client driver gets a pseudo DMA interrupt(RCV_INT). ++* Handle with care when call this function as well as dma_device_desc_setup function.*/ ++extern int dma_device_read(struct dma_device_info* info, u8** dataptr, void** opt); ++ ++/** Write data Packet to DMA Tx channel. ++* This function gets the data packet from the client driver and send over on DMA channel.*/ ++extern int dma_device_write(struct dma_device_info* info, u8* dataptr, int len, void* opt); ++ ++/** Setup the DMA channel descriptor. ++* This function setup the descriptor of the DMA channel used by client driver. ++* The client driver will take care the buffer allocation and do proper checking of ++* buffer for DMA burst alignment. ++* Handle with care when call this function as well as dma_device_read function */ ++extern int dma_device_desc_setup(_dma_device_info *dma_dev, char *buf, size_t len); ++ ++/** Clear the interrupt status flag ++* This function used to exit from DMA tasklet(tasklet don't need to run again and again ) ++* This is also used to avoid multiple psuedo interrupt (RCV_INT) per packet.*/ ++extern int dma_device_clear_int(_dma_device_info *dma_dev, int dir); ++ ++/**Clear the descriptor status word from the client driver once receive ++ a pseudo interrupt(RCV_INT) from the DMA module to avoid duplicate interrupts from tasklet. ++*/ ++extern int dma_device_clear_desc_status_word(_dma_device_info *dma_dev, int dir); ++ ++/** Poll the DMA device channel descriptors ++* This function polls the interrupts status in polling mode. */ ++extern int dma_device_poll(struct dma_device_info* info, int work_to_do, int *work_done); ++ ++/** setup the dma channel class value ++* This function setup the class of service value for DMA channel.*/ ++extern void dma_device_setup_class_val(_dma_channel_info* pCh, int cls); ++ ++/** poll DMA ownership bit to ensure that rx transactions are complete ++* to prevent descriptor errors */ ++extern void poll_dma_ownership_bit(_dma_device_info *dma_dev); ++#endif /* _IFX_DMA_CORE_H_ */ +diff --git a/arch/mips/include/asm/ifx/ifx_ebu_led.h b/arch/mips/include/asm/ifx/ifx_ebu_led.h +new file mode 100644 +index 0000000..c14b621 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_ebu_led.h +@@ -0,0 +1,76 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_ebu_led.h ++** PROJECT : UEIP ++** MODULES : EBU to Control LEDs ++** ++** DATE : 16 Jul 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : Global EBU LED Controller driver header file ++** COPYRIGHT : Copyright (c) 2006 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 16 JUL 2009 Xu Liang Init Version ++*******************************************************************************/ ++ ++#ifndef IFX_EBU_LED_H ++#define IFX_EBU_LED_H ++ ++ ++ ++/*! ++ \defgroup IFX_LEDEBU UEIP Project - LED EBU sub-driver module ++ \brief UEIP Project - LED EBU sub-driver module, support Danube, Amazon-SE, AR9, VR9. ++ */ ++ ++/*! ++ \defgroup IFX_LEDEBU_API APIs ++ \ingroup IFX_LEDEBU ++ \brief APIs used by other drivers/modules. ++ */ ++ ++/*! ++ \file ifx_ebu_led.h ++ \ingroup IFX_LEDEBU ++ \brief LED EBU sub-driver header file ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * IOCTL ++ * #################################### ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * API ++ * #################################### ++ */ ++ ++#ifdef __KERNEL__ ++ #ifdef CONFIG_IFX_EBU_LED ++ int ifx_ebu_led_set_data(unsigned int led, unsigned int data); ++ void ifx_ebu_led_enable(void); ++ void ifx_ebu_led_disable(void); ++ #else ++ #define ifx_ebu_led_set_data(led, data) ++ #define ifx_ebu_led_enable() ++ #define ifx_ebu_led_disable() ++ #endif ++#endif ++ ++ ++ ++#endif // IFX_EBU_LED_H +diff --git a/arch/mips/include/asm/ifx/ifx_eth_framework.h b/arch/mips/include/asm/ifx/ifx_eth_framework.h +new file mode 100644 +index 0000000..b55d735 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_eth_framework.h +@@ -0,0 +1,90 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_eth_framework.h ++** PROJECT : UEIP ++** MODULES : ETH ++** ++** DATE : 2 Nov 2010 ++** AUTHOR : Xu Liang ++** DESCRIPTION : Global ETH driver framework header file ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3; 85579 Neubiberg, Germany ++** ++** For licensing information, see the file 'LICENSE' in the root folder of ++** this software module. ++** ++** HISTORY ++** $Date $Author $Comment ++** 02 NOV 2010 Xu Liang Init Version ++*******************************************************************************/ ++ ++ ++ ++#ifndef IFX_ETH_FRAMEWORK_H ++#define IFX_ETH_FRAMEWORK_H ++ ++ ++ ++/* ++ * #################################### ++ * Data Type ++ * #################################### ++ */ ++ ++typedef enum { ++ IFX_ETH_FW_POLL_COMPLETE = 0, ++ IFX_ETH_FW_POLL_CONTINUE = 1, ++} ifx_eth_fw_poll_ret_t; ++ ++struct ifx_eth_fw_netdev_ops { ++ // routines usually implemented by IFX ETH/PPE drivers ++ // not all routines defined in net_device/net_device_ops are covered ++ int (*init)(struct net_device *dev); ++ void (*uninit)(struct net_device *dev); ++ ++ int (*open)(struct net_device *dev); ++ int (*stop)(struct net_device *dev); ++ ++ int (*start_xmit)(struct sk_buff *skb, struct net_device *dev); ++ ++ void (*set_multicast_list)(struct net_device *dev); ++ int (*set_mac_address)(struct net_device *dev, void *addr); ++ int (*do_ioctl)(struct net_device *dev, struct ifreq *ifr, int cmd); ++ int (*set_config)(struct net_device *dev, struct ifmap *map); ++ int (*change_mtu)(struct net_device *dev, int new_mtu); ++ int (*neigh_setup)(struct net_device *dev, struct neigh_parms *); ++ ++ struct net_device_stats* ++ (*get_stats)(struct net_device *dev); ++ ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ void (*poll_controller)(struct net_device *dev); ++#endif ++ ifx_eth_fw_poll_ret_t ++ (*poll)(struct net_device *dev, int work_to_do, int *work_done); ++ int weight; ++ ++ void (*tx_timeout)(struct net_device *dev); ++ int watchdog_timeo; ++}; ++ ++ ++ ++/* ++ * #################################### ++ * Declaration ++ * #################################### ++ */ ++ ++extern void *ifx_eth_fw_netdev_priv(struct net_device *dev); ++extern struct net_device *ifx_eth_fw_alloc_netdev(int sizeof_priv, const char *name, struct ifx_eth_fw_netdev_ops *ops); ++extern void ifx_eth_fw_free_netdev(struct net_device *dev, int force); ++extern int ifx_eth_fw_register_netdev(struct net_device *dev); ++void ifx_eth_fw_unregister_netdev(struct net_device *dev, int force); ++extern int ifx_eth_fw_poll_schedule(struct net_device *dev); ++extern int ifx_eth_fw_poll_complete(struct net_device *dev); ++ ++ ++ ++#endif // IFX_ETH_FRAMEWORK_H +diff --git a/arch/mips/include/asm/ifx/ifx_gpio.h b/arch/mips/include/asm/ifx/ifx_gpio.h +new file mode 100644 +index 0000000..429029e +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_gpio.h +@@ -0,0 +1,428 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_gpio.h ++** PROJECT : UEIP ++** MODULES : GPIO ++** ++** DATE : 3 Jul 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : Global GPIO driver header file ++** COPYRIGHT : Copyright (c) 2006 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 03 JUL 2009 Xu Liang Init Version ++*******************************************************************************/ ++ ++#ifndef IFX_GPIO_H ++#define IFX_GPIO_H ++ ++ ++ ++/*! ++ \defgroup IFX_GPIO UEIP Project - GPIO driver module ++ \brief UEIP Project - GPIO driver module, support Danube, Amazon-SE, AR9, VR9. ++ */ ++ ++/*! ++ \defgroup IFX_GPIO_API APIs ++ \ingroup IFX_GPIO ++ \brief APIs used by other drivers/modules. ++ */ ++ ++/*! ++ \defgroup IFX_GPIO_IOCTL IOCTL Commands ++ \ingroup IFX_GPIO ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_GPIO_STRUCT Structures ++ \ingroup IFX_GPIO ++ \brief Structures used by user application. ++ */ ++ ++/*! ++ \file ifx_gpio.h ++ \ingroup IFX_GPIO ++ \brief GPIO driver header file ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++#define IFX_GPIO_PIN_NUMBER_PER_PORT 16 ++#define IFX_GPIO_PIN_ID(port, pin) ((port) * IFX_GPIO_PIN_NUMBER_PER_PORT + (pin)) ++#define IFX_GPIO_PIN_ID_TO_PORT(pin_id) (pin_id >> 4) ++#define IFX_GPIO_PIN_ID_TO_PIN(pin_id) (pin_id & 0x0F) ++ ++enum { ++ IFX_GPIO_PIN_AVAILABLE = 0, ++ IFX_GPIO_MODULE_MIN = IFX_GPIO_PIN_AVAILABLE, ++ // following are module_id used by component while registering ++ IFX_GPIO_MODULE_TEST, ++ IFX_GPIO_MODULE_MEI, ++ IFX_GPIO_MODULE_DSL_NTR, ++ IFX_GPIO_MODULE_SSC, ++ IFX_GPIO_MODULE_ASC0, ++ IFX_GPIO_MODULE_SDIO, ++ IFX_GPIO_MODULE_LEDC, ++ IFX_GPIO_MODULE_USB, ++ IFX_GPIO_MODULE_INTERNAL_SWITCH, ++ IFX_GPIO_MODULE_PCI, ++ IFX_GPIO_MODULE_PCIE, ++ IFX_GPIO_MODULE_NAND, ++ IFX_GPIO_MODULE_PPA, ++ IFX_GPIO_MODULE_TAPI_VMMC, ++ IFX_GPIO_MODULE_TAPI_DEMO, ++ IFX_GPIO_MODULE_TAPI_FXO, ++ IFX_GPIO_MODULE_TAPI_DXT, ++ IFX_GPIO_MODULE_TAPI_VCPE, ++ IFX_GPIO_MODULE_VINAX, ++ IFX_GPIO_MODULE_USIF_UART, ++ IFX_GPIO_MODULE_USIF_SPI, ++ IFX_GPIO_MODULE_SPI_FLASH, ++ IFX_GPIO_MODULE_SPI_EEPROM, ++ IFX_GPIO_MODULE_USIF_SPI_SFLASH, ++ IFX_GPIO_MODULE_LED, ++ IFX_GPIO_MODULE_EBU_LED, ++ IFX_GPIO_MODULE_EXIN, // external interrupt detection unit ++ IFX_GPIO_MODULE_PAGE, // page button gpio ++ IFX_GPIO_MODULE_DECT, // DECT ++ IFX_GPIO_MODULE_SI, ++ IFX_GPIO_MODULE_SWRESET,// sw reset button ++ // add more component in the future ++ IFX_GPIO_MODULE_MAX, ++ // flag to init module during system bootup no matter whether this module is loaded or not ++ IFX_GPIO_MODULE_EARLY_REGISTER = 0x08000000, // this bit flag trigger pin init during system bootup ++}; ++ ++#define IFX_GPIO_DECLARE_MODULE_NAME(var) \ ++ char *var[] = { \ ++ "Available", \ ++ "TEST", \ ++ "MEI", \ ++ "DSL-NTR", \ ++ "SSC", \ ++ "ASC0", \ ++ "SDIO", \ ++ "LEDC", \ ++ "USB", \ ++ "INT_SW", \ ++ "PCI", \ ++ "PCIE", \ ++ "NAND", \ ++ "PPA", \ ++ "TAPI-VMMC", \ ++ "TAPI-DEMO", \ ++ "TAPI-FXO", \ ++ "TAPI-DXT", \ ++ "TAPI-VCPE", \ ++ "VINAX", \ ++ "USIF-UART", \ ++ "USIF-SPI", \ ++ "SFLASH", \ ++ "EEPROM", \ ++ "USIF-SFLASH", \ ++ "LED", \ ++ "EBU_LED", \ ++ "EXIN", \ ++ "PAGE_BUTTON", \ ++ "DECT", \ ++ "SERIAL_IN", \ ++ "SWRESET", \ ++ } ++ ++ ++ ++/* ++ * #################################### ++ * IOCTL ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_GPIO_STRUCT ++ */ ++/*@{*/ ++ ++/*! ++ \struct ifx_gpio_ioctl_parm ++ \brief Structure used for single pin configuration. ++ ++ User application use this structure to call single pin configuration IOCTL commands: ++ IFX_GPIO_IOC_OD, IFX_GPIO_IOC_PUDSEL, IFX_GPIO_IOC_PUDEN, IFX_GPIO_IOC_STOFF, ++ IFX_GPIO_IOC_DIR, IFX_GPIO_IOC_OUTPUT, IFX_GPIO_IOC_INPUT, IFX_GPIO_IOC_ALTSEL0, ++ IFX_GPIO_IOC_ALTSEL1. "port", "pin" and "module" are input. Driver takes input ++ "port" and "pin" to identify which pin to configure. "module" is module ID so that ++ driver can do sanity check to avoid improper pin usage (e.g. two module share one pin). ++ "value" could be either input or output. ++ */ ++struct ifx_gpio_ioctl_parm { ++ int port; /*!< input, GPIO port number 0 ~ 3 */ ++ int pin; /*!< input, GPIO pin number 0 ~ 15 */ ++ int value; /*!< input/output, value to be set (or get) */ ++ int module; /*!< input, module id of this operation */ ++}; ++ ++/*! ++ \struct ifx_gpio_ioctl_version ++ \brief Structure used for query of driver version. ++ */ ++struct ifx_gpio_ioctl_version { ++ unsigned int major; /*!< output, major number of driver */ ++ unsigned int mid; /*!< output, mid number of driver */ ++ unsigned int minor; /*!< output, minor number of driver */ ++}; ++ ++/*! ++ \struct ifx_gpio_ioctl_pin_reserve ++ \brief Structure used to reserve pin. ++ */ ++struct ifx_gpio_ioctl_pin_reserve { ++ int pin; /*!< input, pin ID */ ++ int module_id; /*!< input, module ID */ ++}; ++ ++/*! ++ \struct ifx_gpio_ioctl_pin_config ++ \brief Structure used for single pin configuration (IFX_GPIO_IOC_PIN_CONFIG). ++ ++ User application use this structure to call pin configuration IOCTL command - IFX_GPIO_IOC_PIN_CONFIG. ++ */ ++struct ifx_gpio_ioctl_pin_config { ++ int module_id; /*!< input, module ID */ ++ int pin; /*!< input, pin ID */ ++#define IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET (1 << 0) /*!< config flag, enable Open Drain */ ++#define IFX_GPIO_IOCTL_PIN_CONFIG_OD_CLEAR (1 << 1) /*!< config flag, disable Open Drain */ ++#define IFX_GPIO_IOCTL_PIN_CONFIG_PUDSEL_SET (1 << 2) /*!< config flag, set Pull-Up */ ++#define IFX_GPIO_IOCTL_PIN_CONFIG_PUDSEL_CLEAR (1 << 3) /*!< config flag, set Pull-Down */ ++#define IFX_GPIO_IOCTL_PIN_CONFIG_PUDEN_SET (1 << 4) /*!< config flag, enable Pull-Up/Down */ ++#define IFX_GPIO_IOCTL_PIN_CONFIG_PUDEN_CLEAR (1 << 5) /*!< config flag, disable Pull-Up/Down */ ++#define IFX_GPIO_IOCTL_PIN_CONFIG_STOFF_SET (1 << 6) /*!< config flag, enable Schmitt Trigger */ ++#define IFX_GPIO_IOCTL_PIN_CONFIG_STOFF_CLEAR (1 << 7) /*!< config flag, disable Schmitt Trigger */ ++#define IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT (1 << 8) /*!< config flag, configure GPIO pin as output */ ++#define IFX_GPIO_IOCTL_PIN_CONFIG_DIR_IN (1 << 9) /*!< config flag, configure GPIO pin as input */ ++#define IFX_GPIO_IOCTL_PIN_CONFIG_OUTPUT_SET (1 << 10) /*!< config flag, output 1 */ ++#define IFX_GPIO_IOCTL_PIN_CONFIG_OUTPUT_CLEAR (1 << 11) /*!< config flag, output 0 */ ++#define IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET (1 << 12) /*!< config flag, set Alternative Select 0 with value 1 */ ++#define IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR (1 << 13) /*!< config flag, set Alternative Select 0 with value 0 */ ++#define IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_SET (1 << 14) /*!< config flag, set Alternative Select 1 with value 1 */ ++#define IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR (1 << 15) /*!< config flag, set Alternative Select 1 with value 0 */ ++ unsigned int config; /*!< input, config flags */ ++}; ++ ++/*! ++ \struct ifx_gpio_ioctl_module_query ++ \brief Structure used for query of port. ++ ++ User application use this structure to call IOCTL command - IFX_GPIO_IOC_MODULE_QUERY. ++ Driver will check the GPIO port and return all pins' status of this port. ++ */ ++struct ifx_gpio_ioctl_module_query { ++ int module_id; /*!< input, ID of port (0 ~ 3) */ ++ unsigned int pin_num; /*!< input, number of pins in this port */ ++ unsigned int pin[IFX_GPIO_PIN_NUMBER_PER_PORT]; /*!< input, status of each pin (module using this pin) */ ++}; ++ ++/*! ++ \struct ifx_gpio_ioctl_pin_query ++ \brief Structure used for query of pin. ++ ++ User application use this structure to call IOCTL command - IFX_GPIO_IOC_PIN_CONFIG. ++ Driver will check the module ID using this pin. If this pin is configured as input, ++ the input value will be stored in member "input". ++ */ ++struct ifx_gpio_ioctl_pin_query { ++ int pin; /*!< input, pin ID to query */ ++ int module_id; /*!< output, module ID using this pin, ZERO if the pin is not reserved */ ++ int input; /*!< output, input value if this pin is configured as input */ ++}; ++ ++/*@}*/ ++ ++ ++/*! ++ \addtogroup IFX_GPIO_IOCTL ++ */ ++/*@{*/ ++#define IFX_GPIO_IOC_MAGIC 0xbf ++// backward compatible ++/*! ++ \def IFX_GPIO_IOC_OD ++ \brief GPIO IOCTL Command - Configure Open Drain for given pin. ++ ++ This command uses structure "ifx_gpio_ioctl_parm" as parameter to configure Open Drain for given pin. ++ */ ++#define IFX_GPIO_IOC_OD _IOW( IFX_GPIO_IOC_MAGIC, 0, struct ifx_gpio_ioctl_parm) ++/*! ++ \def IFX_GPIO_IOC_PUDSEL ++ \brief GPIO IOCTL Command - Configure Pull-Up/Down resistor for given pin. ++ ++ This command uses structure "ifx_gpio_ioctl_parm" as parameter to configure Pull-Up/Down resistor for given pin. ++ */ ++#define IFX_GPIO_IOC_PUDSEL _IOW( IFX_GPIO_IOC_MAGIC, 1, struct ifx_gpio_ioctl_parm) ++/*! ++ \def IFX_GPIO_IOC_PUDEN ++ \brief GPIO IOCTL Command - Enable/Disable Pull-Up/Down feature for given pin. ++ ++ This command uses structure "ifx_gpio_ioctl_parm" as parameter to enable/disable Pull-Up/Down feature for given pin. ++ */ ++#define IFX_GPIO_IOC_PUDEN _IOW( IFX_GPIO_IOC_MAGIC, 2, struct ifx_gpio_ioctl_parm) ++/*! ++ \def IFX_GPIO_IOC_STOFF ++ \brief GPIO IOCTL Command - Enable/Disable Pull-Up/Down feature for given pin. ++ ++ This command uses structure "ifx_gpio_ioctl_parm" as parameter to enable/disable Pull-Up/Down feature for given pin. ++ */ ++#define IFX_GPIO_IOC_STOFF _IOW( IFX_GPIO_IOC_MAGIC, 3, struct ifx_gpio_ioctl_parm) ++/*! ++ \def IFX_GPIO_IOC_DIR ++ \brief GPIO IOCTL Command - Configure given pin to be input or output. ++ ++ This command uses structure "ifx_gpio_ioctl_parm" as parameter to configure given pin to be input or output. ++ */ ++#define IFX_GPIO_IOC_DIR _IOW( IFX_GPIO_IOC_MAGIC, 4, struct ifx_gpio_ioctl_parm) ++/*! ++ \def IFX_GPIO_IOC_OUTPUT ++ \brief GPIO IOCTL Command - Configure given pin to output 0 or 1. ++ ++ This command uses structure "ifx_gpio_ioctl_parm" as parameter to configure given pin to output 0 or 1. ++ */ ++#define IFX_GPIO_IOC_OUTPUT _IOW( IFX_GPIO_IOC_MAGIC, 5, struct ifx_gpio_ioctl_parm) ++/*! ++ \def IFX_GPIO_IOC_INPUT ++ \brief GPIO IOCTL Command - Collect input from given pin. ++ ++ This command uses structure "ifx_gpio_ioctl_parm" as parameter to collect input from given pin. ++ */ ++#define IFX_GPIO_IOC_INPUT _IOWR(IFX_GPIO_IOC_MAGIC, 6, struct ifx_gpio_ioctl_parm) ++/*! ++ \def IFX_GPIO_IOC_ALTSEL0 ++ \brief GPIO IOCTL Command - Configure Alternative Select 0 for given pin. ++ ++ This command uses structure "ifx_gpio_ioctl_parm" as parameter to configure Alternative Select 0 for given pin. ++ */ ++#define IFX_GPIO_IOC_ALTSEL0 _IOW( IFX_GPIO_IOC_MAGIC, 7, struct ifx_gpio_ioctl_parm) ++/*! ++ \def IFX_GPIO_IOC_ALTSEL1 ++ \brief GPIO IOCTL Command - Configure Alternative Select 1 for given pin. ++ ++ This command uses structure "ifx_gpio_ioctl_parm" as parameter to configure Alternative Select 1 for given pin. ++ */ ++#define IFX_GPIO_IOC_ALTSEL1 _IOW( IFX_GPIO_IOC_MAGIC, 8, struct ifx_gpio_ioctl_parm) ++// UEIP IOCTL commands ++/*! ++ \def IFX_GPIO_IOC_VERSION ++ \brief GPIO IOCTL Command - Get version number of driver. ++ ++ This command uses structure "ifx_gpio_ioctl_version" as parameter to get version number of driver. ++ */ ++#define IFX_GPIO_IOC_VERSION _IOR( IFX_GPIO_IOC_MAGIC, 10, struct ifx_gpio_ioctl_version) ++/*! ++ \def IFX_GPIO_IOC_REGISTER ++ \brief GPIO IOCTL Command - Register module. ++ ++ This command uses "arg" as parameter (module_id) to register module. ++ */ ++#define IFX_GPIO_IOC_REGISTER _IO( IFX_GPIO_IOC_MAGIC, 11) ++/*! ++ \def IFX_GPIO_IOC_DEREGISTER ++ \brief GPIO IOCTL Command - Deregister module. ++ ++ This command uses "arg" as parameter (module_id) to deregister module. ++ */ ++#define IFX_GPIO_IOC_DEREGISTER _IO( IFX_GPIO_IOC_MAGIC, 12) ++/*! ++ \def IFX_GPIO_IOC_PIN_RESERVE ++ \brief GPIO IOCTL Command - Reserve pin. ++ ++ This command uses struct "ifx_gpio_ioctl_pin_reserve" as parameter to reserve pin. ++ */ ++#define IFX_GPIO_IOC_PIN_RESERVE _IOW( IFX_GPIO_IOC_MAGIC, 13, struct ifx_gpio_ioctl_pin_reserve) ++/*! ++ \def IFX_GPIO_IOC_PIN_FREE ++ \brief GPIO IOCTL Command - Free pin. ++ ++ This command uses struct "ifx_gpio_ioctl_pin_reserve" as parameter to free pin. ++ */ ++#define IFX_GPIO_IOC_PIN_FREE _IOW( IFX_GPIO_IOC_MAGIC, 14, struct ifx_gpio_ioctl_pin_reserve) ++/*! ++ \def IFX_GPIO_IOC_PIN_CONFIG ++ \brief GPIO IOCTL Command - Configure pin. ++ ++ This command uses struct "ifx_gpio_ioctl_pin_config" as parameter to configure pin. ++ */ ++#define IFX_GPIO_IOC_PIN_CONFIG _IOR( IFX_GPIO_IOC_MAGIC, 15, struct ifx_gpio_ioctl_pin_config) ++/*! ++ \def IFX_GPIO_IOC_MODULE_QUERY ++ \brief GPIO IOCTL Command - Get pin information of given module ID. ++ ++ This command uses struct "ifx_gpio_ioctl_module_query" as parameter to get pin information of given module ID. ++ */ ++#define IFX_GPIO_IOC_MODULE_QUERY _IOWR(IFX_GPIO_IOC_MAGIC, 16, struct ifx_gpio_ioctl_module_query) ++/*! ++ \def IFX_GPIO_IOC_PIN_QUERY ++ \brief GPIO IOCTL Command - Get pin information of given pin ID. ++ ++ This command uses struct "ifx_gpio_ioctl_module_query" as parameter to get pin information of given pin ID. ++ */ ++#define IFX_GPIO_IOC_PIN_QUERY _IOWR(IFX_GPIO_IOC_MAGIC, 17, struct ifx_gpio_ioctl_pin_query) ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * API ++ * #################################### ++ */ ++ ++#ifdef __KERNEL__ ++ /* ++ * Module Level Functions ++ */ ++ int ifx_gpio_register(int module_id); ++ int ifx_gpio_deregister(int module_id); ++ /* ++ * Pin Operation Functions ++ */ ++ int ifx_gpio_output_set(int pin, int module_id); ++ int ifx_gpio_output_clear(int pin, int module_id); ++ int ifx_gpio_input_get(int pin, int module_id, int *input); ++ /* ++ * Pin Operation Functions (Backward Compatible) ++ */ ++ int ifx_gpio_pin_reserve(int pin, int module_id); ++ int ifx_gpio_pin_free(int pin, int module_id); ++ int ifx_gpio_open_drain_set(int pin, int module_id); ++ int ifx_gpio_open_drain_clear(int pin, int module_id); ++ int ifx_gpio_pudsel_set(int pin, int module_id); ++ int ifx_gpio_pudsel_clear(int pin, int module_id); ++ int ifx_gpio_puden_set(int pin, int module_id); ++ int ifx_gpio_puden_clear(int pin, int module_id); ++ int ifx_gpio_stoff_set(int pin, int module_id); ++ int ifx_gpio_stoff_clear(int pin, int module_id); ++ int ifx_gpio_dir_out_set(int pin, int module_id); ++ int ifx_gpio_dir_in_set(int pin, int module_id); ++ int ifx_gpio_altsel0_set(int pin, int module_id); ++ int ifx_gpio_altsel0_clear(int pin, int module_id); ++ int ifx_gpio_altsel1_set(int pin, int module_id); ++ int ifx_gpio_altsel1_clear(int pin, int module_id); ++#endif // __KERNEL__ ++ ++ ++ ++#endif // IFX_GPIO_H +diff --git a/arch/mips/include/asm/ifx/ifx_gptu.h b/arch/mips/include/asm/ifx/ifx_gptu.h +new file mode 100644 +index 0000000..1acb9da +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_gptu.h +@@ -0,0 +1,239 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_gptu.h ++** PROJECT : IFX UEIP ++** MODULES : GPTU ++** ++** DATE : 28 May 2009 ++** AUTHOR : Huang Xiaogang ++** DESCRIPTION : IFX General Purpose Timer Counter driver header file ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 28 May 2009 Huang Xiaogang The first UEIP release ++*******************************************************************************/ ++#ifndef IFX_GPTU_H ++#define IFX_GPTU_H ++ ++/*! ++ \defgroup IFX_GPTU UEIP Project - GPTU driver module ++ \brief UEIP Project - GPTU driver module, support Danube, Amazon-SE, AR9, VR9. ++ */ ++ ++/*! ++ \defgroup IFX_GPTU_API APIs ++ \ingroup IFX_GPTU ++ \brief APIs used by other drivers/modules. ++ */ ++ ++/*! ++ \defgroup IFX_GPTU_IOCTL IOCTL Commands ++ \ingroup IFX_GPTU ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_GPTU_STRUCT Structures ++ \ingroup IFX_GPTU ++ \brief Structures used by user application. ++ */ ++ ++/*! \file ifx_gptu.h ++ \ingroup IFX_GPTU ++ \brief This file contains the interface to GPTU driver. ++*/ ++ ++/* ++ * Available Timer/Counter Index ++ */ ++#define TIMER(n, X) (n * 2 + (X ? 1 : 0)) ++#define TIMER_ANY 0x00 ++#define TIMER1A TIMER(1, 0) ++#define TIMER1B TIMER(1, 1) ++#define TIMER2A TIMER(2, 0) ++#define TIMER2B TIMER(2, 1) ++#define TIMER3A TIMER(3, 0) ++#define TIMER3B TIMER(3, 1) ++ ++/* ++ * Flag of Timer/Counter ++ * These flags specify the way in which timer is configured. ++ */ ++/* Bit size of timer/counter. */ ++#define TIMER_FLAG_16BIT 0x0000 ++#define TIMER_FLAG_32BIT 0x0001 ++/* Switch between timer and counter. */ ++#define TIMER_FLAG_TIMER 0x0000 ++#define TIMER_FLAG_COUNTER 0x0002 ++/* Stop or continue when overflowing/underflowing. */ ++#define TIMER_FLAG_ONCE 0x0000 ++#define TIMER_FLAG_CYCLIC 0x0004 ++/* Count up or counter down. */ ++#define TIMER_FLAG_UP 0x0000 ++#define TIMER_FLAG_DOWN 0x0008 ++/* Count on specific level or edge. */ ++#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000 ++#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040 ++#define TIMER_FLAG_RISE_EDGE 0x0010 ++#define TIMER_FLAG_FALL_EDGE 0x0020 ++#define TIMER_FLAG_ANY_EDGE 0x0030 ++/* Signal is syncronous to module clock or not. */ ++#define TIMER_FLAG_UNSYNC 0x0000 ++#define TIMER_FLAG_SYNC 0x0080 ++/* Different interrupt handle type. */ ++#define TIMER_FLAG_NO_HANDLE 0x0000 ++#if defined(__KERNEL__) ++ #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100 ++#endif // defined(__KERNEL__) ++#define TIMER_FLAG_SIGNAL 0x0300 ++/* Internal clock source or external clock source */ ++#define TIMER_FLAG_INT_SRC 0x0000 ++#define TIMER_FLAG_EXT_SRC 0x1000 ++ ++#define IFX_GPTU_VER_MAJOR 2 ++#define IFX_GPTU_VER_MID 0 ++#define IFX_GPTU_VER_MINOR 1 ++ ++/*! ++ \addtogroup IFX_GPTU_STRUCT ++ */ ++/*@{*/ ++ ++/*! ++ \struct ifx_gptu_ioctl_version ++ \brief Structure used for query of driver version. ++ */ ++struct ifx_gptu_ioctl_version { ++ unsigned int major; /*!< output, major number of driver */ ++ unsigned int mid; /*!< output, mid number of driver */ ++ unsigned int minor; /*!< output, minor number of driver */ ++}; ++ ++/*! ++ \struct gptu_ioctl_param ++ \brief data type used to call ioctl ++ */ ++struct gptu_ioctl_param { ++ unsigned int timer; /*!< In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and ++ GPTU_SET_COUNTER, this field is ID of expected ++ timer/counter. If it's zero, a timer/counter would ++ be dynamically allocated and ID would be stored in ++ this field. ++ In command GPTU_GET_COUNT_VALUE, this field is ++ ignored. ++ In other command, this field is ID of timer/counter ++ allocated.*/ ++ unsigned int flag; /*!< In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and ++ GPTU_SET_COUNTER, this field contains flags to ++ specify how to configure timer/counter. ++ In command GPTU_START_TIMER, zero indicate start ++ and non-zero indicate resume timer/counter. ++ In other command, this field is ignored.*/ ++ unsigned long value; /*!< In command GPTU_REQUEST_TIMER, this field contains ++ init/reload value. ++ In command GPTU_SET_TIMER, this field contains ++ frequency (0.001Hz) of timer. ++ In command GPTU_GET_COUNT_VALUE, current count ++ value would be stored in this field. ++ In command GPTU_CALCULATE_DIVIDER, this field ++ contains frequency wanted, and after calculation, ++ divider would be stored in this field to overwrite ++ the frequency.*/ ++ int pid; /*!< In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, ++ if signal is required, this field contains process ++ ID to which signal would be sent. ++ In other command, this field is ignored.*/ ++ int sig; /*!< In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, ++ if signal is required, this field contains signal ++ number which would be sent. ++ In other command, this field is ignored.*/ ++}; ++/*@}*/ ++ ++/*! ++ \addtogroup IFX_GPTU_IOCTL ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Command ++ */ ++#define IFX_GPTU_IOC_MAGIC 'g' ++ ++/*! ++ \def IFX_GPTU_REQUEST_TIMER ++ \brief General method to setup timer/counter. ++ */ ++#define IFX_GPTU_REQUEST_TIMER _IOWR(IFX_GPTU_IOC_MAGIC, 1, struct gptu_ioctl_param) ++ ++/*! ++ \def IFX_GPTU_FREE_TIMER ++ \brief Free timer/counter ++ */ ++#define IFX_GPTU_FREE_TIMER _IOW(IFX_GPTU_IOC_MAGIC, 2, struct gptu_ioctl_param) ++ ++/*! ++ \def IFX_GPTU_START_TIMER ++ \brief Start or resume timer/counter ++ */ ++#define IFX_GPTU_START_TIMER _IOW(IFX_GPTU_IOC_MAGIC, 3, struct gptu_ioctl_param) ++ ++/*! ++ \def IFX_GPTU_STOP_TIMER ++ \brief Suspend timer/counter ++ */ ++#define IFX_GPTU_STOP_TIMER _IOW(IFX_GPTU_IOC_MAGIC, 4, struct gptu_ioctl_param) ++ ++/*! ++ \def IFX_GPTU_GET_COUNT_VALUE ++ \brief Get current count value ++ */ ++#define IFX_GPTU_GET_COUNT_VALUE _IOWR(IFX_GPTU_IOC_MAGIC, 5, struct gptu_ioctl_param) ++ ++/*! ++ \def IFX_GPTU_CALCULATE_DIVIDER ++ \brief Calculate timer divider from given freq ++ */ ++#define IFX_GPTU_CALCULATE_DIVIDER _IOWR(IFX_GPTU_IOC_MAGIC, 6, struct gptu_ioctl_param) ++ ++/*! ++ \def IFX_GPTU_SET_TIMER ++ \brief Simplified method to setup timer ++ */ ++#define IFX_GPTU_SET_TIMER _IOWR(IFX_GPTU_IOC_MAGIC, 7, struct gptu_ioctl_param) ++ ++/*! ++ \def IFX_GPTU_SET_COUNTER ++ \brief Simplified method to setup counter ++ */ ++#define IFX_GPTU_SET_COUNTER _IOWR(IFX_GPTU_IOC_MAGIC, 8, struct gptu_ioctl_param) ++ ++/*! ++ \def IFX_GPTU_VERSION ++ \brief Get GPTU driver version number ++ */ ++#define IFX_GPTU_VERSION _IOR(IFX_GPTU_IOC_MAGIC, 9, struct ifx_gptu_ioctl_version) ++/*@}*/ ++ ++typedef void (*timer_callback)(unsigned long arg); ++ ++extern int ifx_gptu_timer_request(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long); ++extern int ifx_gptu_timer_free(unsigned int); ++extern int ifx_gptu_timer_start(unsigned int, int); ++extern int ifx_gptu_timer_stop(unsigned int); ++extern int ifx_gptu_counter_flags_reset(u32 timer, u32 flags); ++extern int ifx_gptu_countvalue_get(unsigned int, unsigned long *); ++extern u32 ifx_gptu_divider_cal(unsigned long); ++extern int ifx_gptu_timer_set(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long); ++extern int ifx_gptu_counter_set(unsigned int timer, unsigned int flag, ++ u32 reload, unsigned long arg1, unsigned long arg2); ++ ++#endif /* IFX_GPTU_H */ +diff --git a/arch/mips/include/asm/ifx/ifx_led.h b/arch/mips/include/asm/ifx/ifx_led.h +new file mode 100644 +index 0000000..2d1e956 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_led.h +@@ -0,0 +1,331 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_led.h ++** PROJECT : UEIP ++** MODULES : LED Driver ++** ++** DATE : 16 Jul 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : Global LED driver header file ++** COPYRIGHT : Copyright (c) 2006 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 16 JUL 2009 Xu Liang Init Version ++*******************************************************************************/ ++ ++#ifndef IFX_LED_H ++#define IFX_LED_H ++ ++ ++ ++/*! ++ \defgroup IFX_LED UEIP Project - LED driver module ++ \brief UEIP Project - LED driver module, support Danube, Amazon-SE, AR9, VR9. ++ */ ++ ++/*! ++ \defgroup IFX_LED_API APIs ++ \ingroup IFX_LED ++ \brief APIs used by other drivers/modules. ++ */ ++ ++/*! ++ \defgroup IFX_LED_IOCTL IOCTL Commands ++ \ingroup IFX_LED ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_LED_STRUCT Structures ++ \ingroup IFX_LED ++ \brief Structures used by user application. ++ */ ++ ++/*! ++ \file ifx_led.h ++ \ingroup IFX_LED ++ \brief LED driver header file ++ */ ++ ++ ++ ++#include ++#include "asm/ifx/ifx_types.h" ++ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++/* ++ * LED Events ++ */ ++#define IFX_LED_TRIGGER_POWER_ON "power_on" ++#define IFX_LED_TRIGGER_WARNING "warning" ++#define IFX_LED_TRIGGER_DSL_LINK "dsl_link" ++#define IFX_LED_TRIGGER_DSL_DATA "dsl_data" ++#define IFX_LED_TRIGGER_USB_LINK "usb_link" ++#define IFX_LED_TRIGGER_WAN_STATUS "wan_status" ++#define IFX_LED_TRIGGER_EPHY_LINK "ephy_link" ++#define IFX_LED_TRIGGER_EPHY_SPEED "ephy_speed" ++#define IFX_LED_TRIGGER_FXS1_LINK "fxs1_link" ++#define IFX_LED_TRIGGER_FXS2_LINK "fxs2_link" ++#define IFX_LED_TRIGGER_FXO_ACT "fxo_act" ++#define IFX_LED_TRIGGER_WLAN_READY1 "wlan_ready1" ++#define IFX_LED_TRIGGER_WLAN_READY2 "wlan_ready2" ++#define IFX_LED_TRIGGER_SD_LINK "sd_link" ++ ++/* ++ * Macros for dual color LED ++ */ ++#define IFX_LED_DUAL_MAKE_PHYS_ID(phys_id_led1, phys_id_led2) (((phys_id_led2) << 16) | (phys_id_led1)) ++#define IFX_LED_DUAL_GET_PHYS_ID_LED1(phys_id) ((phys_id) & 0xffff) ++#define IFX_LED_DUAL_GET_PHYS_ID_LED2(phys_id) (((phys_id) >> 16) & 0xffff) ++ ++/* ++ * #################################### ++ * Data Type ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_LED_STRUCT ++ */ ++/*@{*/ ++ ++/* ++ * LED Device Definition ++ */ ++/*! ++ \struct ifx_led_device ++ \brief Structure used for LED device. ++ */ ++struct ifx_led_device { ++ struct led_classdev device; /*!< LED device */ ++ char name[32]; /*!< LED device name */ ++ ++ char *default_trigger; /*!< default event/trigger of LED device */ ++ unsigned int phys_id; /*!< physical ID of LED device, driver use this ID to communicate with physical LED driver */ ++ unsigned int value_on; /*!< value to turn on LED */ ++ unsigned int value_off; /*!< value to turn off LED */ ++ unsigned int color; /*!< color of the LED */ ++/*! ++ \def IFX_LED_DEVICE_FLAG_PHYS_GPIO ++ \brief field "flags" of struct "ifx_led_device" - LED drived by GPIO. ++ */ ++#define IFX_LED_DEVICE_FLAG_PHYS_GPIO 0 ++/*! ++ \def IFX_LED_DEVICE_FLAG_PHYS_LEDC ++ \brief field "flags" of struct "ifx_led_device" - LED drived by LED Controller (Serial Out). ++ */ ++#define IFX_LED_DEVICE_FLAG_PHYS_LEDC 1 ++/*! ++ \def IFX_LED_DEVICE_FLAG_PHYS_EBU ++ \brief field "flags" of struct "ifx_led_device" - LED drived by EBU. ++ */ ++#define IFX_LED_DEVICE_FLAG_PHYS_EBU 2 ++#define IFX_LED_DEVICE_FLAG_PHYS_MASK 3 ++#define IFX_LED_DEVICE_FLAG_DUAL_LED (1 << 29) ++#define IFX_LED_DEVICE_FLAG_CREATED (1 << 30) ++/*! ++ \def IFX_LED_DEVICE_FLAG_INVALID ++ \brief field "flags" of struct "ifx_led_device" - LED is not in use. ++ */ ++#define IFX_LED_DEVICE_FLAG_INVALID (1 << 31) ++ unsigned int flags; /*!< additional flags */ ++}; ++ ++/* ++ * LED Trigger Atrribute ++ */ ++/*! ++ \struct ifx_led_trigger_attrib ++ \brief Structure used for LED default behavior (attibutes). ++ */ ++struct ifx_led_trigger_attrib { ++ unsigned int delay_on; /*!< delay of LED on (in millisecond) */ ++ unsigned int delay_off; /*!< delay of LED off (in millisecond) */ ++ unsigned int timeout; /*!< stop blinking/on after timeout (in millisecond) */ ++ unsigned int def_value; /*!< default state of LED (on/off) */ ++/*! ++ \def IFX_LED_TRIGGER_ATTRIB_DELAY_ON ++ \brief field "flags" of struct "ifx_led_trigger_attrib" - delay_on is valid. ++ */ ++#define IFX_LED_TRIGGER_ATTRIB_DELAY_ON (1 << 0) ++/*! ++ \def IFX_LED_TRIGGER_ATTRIB_DELAY_OFF ++ \brief field "flags" of struct "ifx_led_trigger_attrib" - delay_off is valid. ++ */ ++#define IFX_LED_TRIGGER_ATTRIB_DELAY_OFF (1 << 1) ++/*! ++ \def IFX_LED_TRIGGER_ATTRIB_TIMEOUT ++ \brief field "flags" of struct "ifx_led_trigger_attrib" - timeout is valid. ++ */ ++#define IFX_LED_TRIGGER_ATTRIB_TIMEOUT (1 << 2) ++/*! ++ \def IFX_LED_TRIGGER_ATTRIB_DEF_VALUE ++ \brief field "flags" of struct "ifx_led_trigger_attrib" - def_value is valid. ++ */ ++#define IFX_LED_TRIGGER_ATTRIB_DEF_VALUE (1 << 3) ++ unsigned int flags; /*!< additional flags */ ++}; ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * IOCTL ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_LED_STRUCT ++ */ ++/*@{*/ ++ ++/*! ++ \struct ifx_led_ioctl_version ++ \brief Structure used for query of driver version. ++ */ ++struct ifx_led_ioctl_version { ++ unsigned int major; /*!< output, major number of driver */ ++ unsigned int mid; /*!< output, mid number of driver */ ++ unsigned int minor; /*!< output, minor number of driver */ ++}; ++ ++/*! ++ \struct ifx_led_ioctl_trigger ++ \brief Structure used for trigger operations. ++ */ ++struct ifx_led_ioctl_trigger { ++ char name[32]; /*!< input, name of trigger */ ++ void *handler; /*!< input/output, handler of trigger */ ++ struct ifx_led_trigger_attrib attrib; /*!< input, behavior of LED */ ++}; ++ ++/*@}*/ ++ ++ ++/*! ++ \addtogroup IFX_LED_IOCTL ++ */ ++/*@{*/ ++#define IFX_LED_IOC_MAGIC 0xed ++/*! ++ \def IFX_LED_IOC_VERSION ++ \brief LED IOCTL Command - Get version number of driver. ++ ++ This command uses structure "ifx_led_ioctl_version" as parameter to get version number of driver. ++ */ ++#define IFX_LED_IOC_VERSION _IOR( IFX_LED_IOC_MAGIC, 0, struct ifx_led_ioctl_version) ++/*! ++ \def IFX_LED_IOC_TRIGGER_REGISTER ++ \brief LED IOCTL Command - Register a LED trigger (source of event). ++ ++ This command uses structure "ifx_led_ioctl_trigger" as parameter to register a LED trigger (source of event). ++ User need provide valid "name" before call this IOCTL. ++ The return value is hold in "handler", and it should be used for other IOCTL commands. ++ */ ++#define IFX_LED_IOC_TRIGGER_REGISTER _IOWR(IFX_LED_IOC_MAGIC, 1, struct ifx_led_ioctl_trigger) ++/*! ++ \def IFX_LED_IOC_TRIGGER_DEREGISTER ++ \brief LED IOCTL Command - Deregister a LED trigger (source of event). ++ ++ This command uses structure "ifx_led_ioctl_trigger" as parameter to deregister a LED trigger (source of event). ++ User need provide valid "handler" which is got from "IFX_LED_IOC_TRIGGER_REGISTER". ++ After this command, the "handler" is destroyed and can not be used anymore. ++ */ ++#define IFX_LED_IOC_TRIGGER_DEREGISTER _IOW( IFX_LED_IOC_MAGIC, 2, struct ifx_led_ioctl_trigger) ++/*! ++ \def IFX_LED_IOC_TRIGGER_ACTIVATE ++ \brief LED IOCTL Command - send LED trigger (event). ++ ++ This command uses structure "ifx_led_ioctl_trigger" as parameter to send a LED trigger (event). ++ User uses this command to give a notice on LED event, and LED driver will drive LED according to attributes. ++ User need provide valid "handler" which is got from "IFX_LED_IOC_TRIGGER_REGISTER". ++ */ ++#define IFX_LED_IOC_TRIGGER_ACTIVATE _IOW( IFX_LED_IOC_MAGIC, 3, struct ifx_led_ioctl_trigger) ++/*! ++ \def IFX_LED_IOC_TRIGGER_DEACTIVATE ++ \brief LED IOCTL Command - reset LED to default status. ++ ++ This command uses structure "ifx_led_ioctl_trigger" as parameter to reset LED to default status. ++ User uses this command to reset LED to default status (e.g. LED off). ++ User need provide valid "handler" which is got from "IFX_LED_IOC_TRIGGER_REGISTER". ++ */ ++#define IFX_LED_IOC_TRIGGER_DEACTIVATE _IOW( IFX_LED_IOC_MAGIC, 4, struct ifx_led_ioctl_trigger) ++/*! ++ \def IFX_LED_IOC_TRIGGER_SET_ATTRIB ++ \brief LED IOCTL Command - define LED behavior. ++ ++ This command uses structure "ifx_led_ioctl_trigger" as parameter to define LED behavior. ++ User need provide valid "handler" which is got from "IFX_LED_IOC_TRIGGER_REGISTER". ++ */ ++#define IFX_LED_IOC_TRIGGER_SET_ATTRIB _IOW( IFX_LED_IOC_MAGIC, 5, struct ifx_led_ioctl_trigger) ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * API ++ * #################################### ++ */ ++ ++#ifdef __KERNEL__ ++ int ifx_led_trigger_register(const char *trigger, void **pphandler); ++ void ifx_led_trigger_deregister(void *phandler); ++ void ifx_led_trigger_activate(void *phandler); ++ void ifx_led_trigger_deactivate(void *phandler); ++ void ifx_led_trigger_set_attrib(void *phandler, struct ifx_led_trigger_attrib *attrib); ++ ++ // Use LED for GPIO Output operation. ++ // Register LED trigger. ++ static inline int ifx_led_gpio_output_register(const char *trigger, void **pphandler) ++ { ++ int ret; ++ struct ifx_led_trigger_attrib attrib = {0}; ++ ++ attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE; ++ ++ ret = ifx_led_trigger_register(trigger, pphandler); ++ if ( ret == IFX_SUCCESS && *pphandler != NULL ) ++ ifx_led_trigger_set_attrib(*pphandler, &attrib); ++ ++ return ret; ++ } ++ ++ // Use LED for GPIO Output operation. ++ // Deregister LED trigger. ++ static inline void ifx_led_gpio_output_deregister(void *phandler) ++ { ++ ifx_led_trigger_deregister(phandler); ++ } ++ ++ // Use LED for GPIO Output operation. ++ // Output value. ++ static inline void ifx_led_gpio_output_value(void *phandler, unsigned int value) ++ { ++ if ( value != 0 ) ++ ifx_led_trigger_activate(phandler); ++ else ++ ifx_led_trigger_deactivate(phandler); ++ } ++#endif ++ ++ ++ ++#endif // IFX_LED_H +diff --git a/arch/mips/include/asm/ifx/ifx_ledc.h b/arch/mips/include/asm/ifx/ifx_ledc.h +new file mode 100644 +index 0000000..d1a89c1 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_ledc.h +@@ -0,0 +1,351 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_ledc.h ++** PROJECT : UEIP ++** MODULES : LED Controller (Serial Out) ++** ++** DATE : 16 Jul 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : Global LED Controller driver header file ++** COPYRIGHT : Copyright (c) 2006 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 16 JUL 2009 Xu Liang Init Version ++*******************************************************************************/ ++ ++#ifndef IFX_LEDC_H ++#define IFX_LEDC_H ++ ++ ++ ++/*! ++ \defgroup IFX_LEDC UEIP Project - LED Controller sub-driver module ++ \brief UEIP Project - LED Controller (Serial Out) sub-driver module, support Danube, Amazon-SE, AR9, VR9. ++ */ ++ ++/*! ++ \defgroup IFX_LEDC_API APIs ++ \ingroup IFX_LEDC ++ \brief APIs used by other drivers/modules. ++ */ ++ ++/*! ++ \defgroup IFX_LEDC_IOCTL IOCTL Commands ++ \ingroup IFX_LEDC ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_LEDC_STRUCT Structures ++ \ingroup IFX_LEDC ++ \brief Structures used by user application. ++ */ ++ ++/*! ++ \file ifx_ledc.h ++ \ingroup IFX_LEDC ++ \brief LED Controller (Serial Out) sub-driver header file ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_LEDC_STRUCT ++ */ ++/*@{*/ ++ ++/* ++ * Definition of Operation MASK ++ */ ++/*! ++ \def IFX_LEDC_CFG_OP_UPDATE_SOURCE ++ \brief field "operation_mask" of struct "ifx_ledc_config_param" - select LED data source. ++ */ ++#define IFX_LEDC_CFG_OP_UPDATE_SOURCE 0x0001 ++/*! ++ \def IFX_LEDC_CFG_OP_BLINK ++ \brief field "operation_mask" of struct "ifx_ledc_config_param" - enable/disable blink. ++ */ ++#define IFX_LEDC_CFG_OP_BLINK 0x0002 ++/*! ++ \def IFX_LEDC_CFG_OP_UPDATE_CLOCK ++ \brief field "operation_mask" of struct "ifx_ledc_config_param" - select update clock source. ++ */ ++#define IFX_LEDC_CFG_OP_UPDATE_CLOCK 0x0004 ++/*! ++ \def IFX_LEDC_CFG_OP_STORE_MODE ++ \brief field "operation_mask" of struct "ifx_ledc_config_param" - select clock store mode or single pulse store mode. ++ */ ++#define IFX_LEDC_CFG_OP_STORE_MODE 0x0008 ++/*! ++ \def IFX_LEDC_CFG_OP_SHIFT_CLOCK ++ \brief field "operation_mask" of struct "ifx_ledc_config_param" - select shift clock source. ++ */ ++#define IFX_LEDC_CFG_OP_SHIFT_CLOCK 0x0010 ++/*! ++ \def IFX_LEDC_CFG_OP_DATA_OFFSET ++ \brief field "operation_mask" of struct "ifx_ledc_config_param" - select cycles (0 ~ 3) to be inserted before data transmition. ++ */ ++#define IFX_LEDC_CFG_OP_DATA_OFFSET 0x0020 ++/*! ++ \def IFX_LEDC_CFG_OP_NUMBER_OF_LED ++ \brief field "operation_mask" of struct "ifx_ledc_config_param" - select number of LEDs (8, 16, 24). ++ */ ++#define IFX_LEDC_CFG_OP_NUMBER_OF_LED 0x0040 ++/*! ++ \def IFX_LEDC_CFG_OP_DATA ++ \brief field "operation_mask" of struct "ifx_ledc_config_param" - LED on/off. ++ */ ++#define IFX_LEDC_CFG_OP_DATA 0x0080 ++/*! ++ \def IFX_LEDC_CFG_OP_MIPS0_ACCESS ++ \brief field "operation_mask" of struct "ifx_ledc_config_param" - select owner of LED (mips0/mips1). ++ */ ++#define IFX_LEDC_CFG_OP_MIPS0_ACCESS 0x0100 ++/*! ++ \def IFX_LEDC_CFG_OP_DATA_CLOCK_EDGE ++ \brief field "operation_mask" of struct "ifx_ledc_config_param" - select data clock effective edge (rising/falling). ++ */ ++#define IFX_LEDC_CFG_OP_DATA_CLOCK_EDGE 0x0200 ++ ++/* ++ * Constant for Some Operations ++ */ ++/*! ++ \def IFX_LED_CON1_UPDATE_SRC_SOFTWARE ++ \brief field "update_clock" of struct "ifx_ledc_config_param" - update LED by software trigger. ++ */ ++#define IFX_LED_CON1_UPDATE_SRC_SOFTWARE 0 ++#define LED_CON1_UPDATE_SRC_SOFTWARE IFX_LED_CON1_UPDATE_SRC_SOFTWARE ++/*! ++ \def IFX_LED_CON1_UPDATE_SRC_GPT ++ \brief field "update_clock" of struct "ifx_ledc_config_param" - update LED by GPT timer. ++ */ ++#define IFX_LED_CON1_UPDATE_SRC_GPT 1 ++#define LED_CON1_UPDATE_SRC_GPT IFX_LED_CON1_UPDATE_SRC_GPT ++/*! ++ \def IFX_LED_CON1_UPDATE_SRC_FPI ++ \brief field "update_clock" of struct "ifx_ledc_config_param" - update LED by FPI clock. ++ */ ++#define IFX_LED_CON1_UPDATE_SRC_FPI 2 ++#define LED_CON1_UPDATE_SRC_FPI IFX_LED_CON1_UPDATE_SRC_FPI ++ ++ ++#define IFX_LED_CON1_GROUP2 (1 << 2) ++#define IFX_LED_CON1_GROUP1 (1 << 1) ++#define IFX_LED_CON1_GROUP0 (1 << 0) ++#define LED_CON1_GROUP2 IFX_LED_CON1_GROUP2 ++#define LED_CON1_GROUP1 IFX_LED_CON1_GROUP1 ++#define LED_CON1_GROUP0 IFX_LED_CON1_GROUP0 ++ ++/*! ++ \def IFX_LED_EXT_SRC_DSL_LED0 ++ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of DSL LED0 ++ */ ++#define IFX_LED_EXT_SRC_DSL_LED0 0 ++/*! ++ \def IFX_LED_EXT_SRC_DSL_LED1 ++ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of DSL LED1 ++ */ ++#define IFX_LED_EXT_SRC_DSL_LED1 1 ++/*! ++ \def IFX_LED_EXT_SRC_GPHY1_LED0 ++ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of GPHY1 LED0 ++ */ ++#define IFX_LED_EXT_SRC_GPHY1_LED0 2 ++/*! ++ \def IFX_LED_EXT_SRC_GPHY1_LED1 ++ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of GPHY1 LED1 ++ */ ++#define IFX_LED_EXT_SRC_GPHY1_LED1 3 ++/*! ++ \def IFX_LED_EXT_SRC_GPHY1_LED2 ++ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of GPHY1 LED2 ++ */ ++#define IFX_LED_EXT_SRC_GPHY1_LED2 4 ++/*! ++ \def IFX_LED_EXT_SRC_GPHY0_LED0 ++ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of GPHY0 LED0 ++ */ ++#define IFX_LED_EXT_SRC_GPHY0_LED0 5 ++/*! ++ \def IFX_LED_EXT_SRC_GPHY0_LED1 ++ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of GPHY0 LED1 ++ */ ++#define IFX_LED_EXT_SRC_GPHY0_LED1 6 ++/*! ++ \def IFX_LED_EXT_SRC_GPHY0_LED2 ++ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of GPHY0 LED2 ++ */ ++#define IFX_LED_EXT_SRC_GPHY0_LED2 7 ++/*! ++ \def IFX_LED_EXT_SRC_EPHY_LINK_LED ++ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of Ephy Link LED ++ */ ++#define IFX_LED_EXT_SRC_EPHY_LINK_LED IFX_LED_EXT_SRC_GPHY1_LED0 ++/*! ++ \def IFX_LED_EXT_SRC_EPHY_SPEED_LED ++ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of Ephy Speed LED ++ */ ++#define IFX_LED_EXT_SRC_EPHY_SPEED_LED IFX_LED_EXT_SRC_GPHY1_LED1 ++/*! ++ \def IFX_LED_EXT_SRC_EPHY_COLLISION_LED ++ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of Ephy Collision LED ++ */ ++#define IFX_LED_EXT_SRC_EPHY_COLLISION_LED IFX_LED_EXT_SRC_GPHY1_LED2 ++/*! ++ \def IFX_LED_EXT_SRC_EPHY_DUPLEX_LED ++ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of Ephy Duplex LED ++ */ ++#define IFX_LED_EXT_SRC_EPHY_DUPLEX_LED IFX_LED_EXT_SRC_GPHY0_LED0 ++/*! ++ \def IFX_LED_EXT_SRC_GPHY2_LED0 ++ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of GPHY2 LED0 ++ */ ++#define IFX_LED_EXT_SRC_GPHY2_LED0 8 ++/*! ++ \def IFX_LED_EXT_SRC_GPHY2_LED1 ++ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of GPHY2 LED1 ++ */ ++#define IFX_LED_EXT_SRC_GPHY2_LED1 9 ++/*! ++ \def IFX_LED_EXT_SRC_GPHY2_LED2 ++ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of GPHY2 LED2 ++ */ ++#define IFX_LED_EXT_SRC_GPHY2_LED2 10 ++/*! ++ \def IFX_LED_EXT_SRC_WLAN_SB_LQ ++ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of WLAN Link Quality Single Band LED ++ */ ++#define IFX_LED_EXT_SRC_WLAN_SB_LQ 11 ++/*! ++ \def IFX_LED_EXT_SRC_WLAN_DB_LQ ++ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of WLAN Link Quality Dual Band LED ++ */ ++#define IFX_LED_EXT_SRC_WLAN_DB_LQ 12 ++/*! ++ \def IFX_LED_EXT_SRC_WLAN_SB_LA ++ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of WLAN Link/Activity Single Band LED ++ */ ++#define IFX_LED_EXT_SRC_WLAN_SB_LA 13 ++/*! ++ \def IFX_LED_EXT_SRC_WLAN_DB_LA ++ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of WLAN Link/Activity Dual Band LED ++ */ ++#define IFX_LED_EXT_SRC_WLAN_DB_LA 14 ++/*! ++ \def IFX_LED_EXT_SRC_WLAN_SECU0 ++ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of WLAN Security LED0 (Dual Color) ++ */ ++#define IFX_LED_EXT_SRC_WLAN_SECU0 15 ++/*! ++ \def IFX_LED_EXT_SRC_WLAN_SECU1 ++ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of WLAN Security LED1 (Dual Color) ++ */ ++#define IFX_LED_EXT_SRC_WLAN_SECU1 16 ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * IOCTL ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_LEDC_STRUCT ++ */ ++/*@{*/ ++ ++/*! ++ \struct ifx_ledc_ioctl_version ++ \brief Structure used for query of driver version. ++ */ ++struct ifx_ledc_ioctl_version { ++ unsigned int major; /*!< output, major number of driver */ ++ unsigned int mid; /*!< output, mid number of driver */ ++ unsigned int minor; /*!< output, minor number of driver */ ++}; ++ ++/*! ++ \struct ifx_ledc_config_param ++ \brief Structure used for configure LED Controller (Serial Out). ++ */ ++struct ifx_ledc_config_param { ++ unsigned long operation_mask; /*!< input, Select operations to be performed */ ++ unsigned long source_mask; /*!< input, LED to change update source (LEDC or Ext - ADSL, PHY) */ ++ unsigned long source; /*!< input, Corresponding update source (LEDC or Ext - ADSL, PHY), 0 - LEDC, 1 - EXT */ ++ unsigned long blink_mask; /*!< input, LEDs to set blink mode */ ++ unsigned long blink; /*!< input, Set to blink mode or normal mode, 0 - blinking, 1 - non-blinking */ ++ unsigned long update_clock; /*!< input, Select the source of update clock, 0 - Software, 1 - GPT, 2 - FPI */ ++ unsigned long fpid; /*!< input, If FPI is the source of update clock, set the divider */ ++ /*!< input, else if GPT is the source, set the frequency (unit 1/10Hz) */ ++ /*!< input, else if SOFTWARE is the source, set the frequency (unit 1/10Hz), or 0 stands for update on request */ ++ unsigned long store_mode; /*!< input, Set clock mode or single pulse mode for store signal, 0 - single store, 1 - shift clock store */ ++ unsigned long fpis; /*!< input, FPI is the source of shift clock, set the divider */ ++ unsigned long data_offset; /*!< input, Set cycles to be inserted before data is transmitted (0 - 3) */ ++ unsigned long number_of_enabled_led; /*!< input, Total number of LED to be enabled (0, 8, 16, 24) */ ++ unsigned long data_mask; /*!< input, LEDs to set value */ ++ unsigned long data; /*!< input, Corresponding value, 0 - low output (off), 1 - high output (on) */ ++ unsigned long mips0_access_mask; /*!< input, LEDs to set access right (not valid for Amazon-SE) */ ++ unsigned long mips0_access; /*!< input, 1: the corresponding data is output from MIPS0, 0: MIPS1 */ ++ unsigned long f_data_clock_on_rising; /*!< input, 1: data clock on rising edge, 0: data clock on falling edge */ ++}; ++ ++/*@}*/ ++ ++/*! ++ \addtogroup IFX_LEDC_IOCTL ++ */ ++/*@{*/ ++#define IFX_LEDC_IOC_MAGIC 'k' ++/*! ++ \def IFX_LEDC_IOC_VERSION ++ \brief LED Controller IOCTL Command - Get driver version number. ++ ++ This command uses struct "ifx_ledc_ioctl_version" as parameter to LED Controller driver version number. ++ */ ++#define IFX_LEDC_IOC_VERSION _IOR(IFX_LEDC_IOC_MAGIC, 0, struct ifx_ledc_ioctl_version) ++/*! ++ \def IFX_LEDC_IOC_SET_CONFIG ++ \brief LED Controller IOCTL Command - Config LED Controller (Serial Out). ++ ++ This command uses struct "ifx_ledc_config_param" as parameter to configure LED Controller (Serial Out). ++ */ ++#define IFX_LEDC_IOC_SET_CONFIG _IOW(IFX_LEDC_IOC_MAGIC, 1, struct ifx_ledc_config_param) ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * API ++ * #################################### ++ */ ++ ++#ifdef __KERNEL__ ++ int ifx_ledc_set_blink(unsigned int led, unsigned int blink); ++ int ifx_ledc_set_data(unsigned int led, unsigned int data); ++int ifx_ledc_set_data2(unsigned int led1, unsigned int data1, unsigned int led2, unsigned int data2); ++ int ifx_ledc_config(struct ifx_ledc_config_param *param); ++#endif ++ ++ ++ ++#endif // IFX_LEDC_H +diff --git a/arch/mips/include/asm/ifx/ifx_mmc_wlan.h b/arch/mips/include/asm/ifx/ifx_mmc_wlan.h +new file mode 100644 +index 0000000..6f770f6 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_mmc_wlan.h +@@ -0,0 +1,311 @@ ++/** ++** FILE NAME : ifx_mmc_wlan.h ++** PROJECT : IFX UEIP ++** MODULES : MMC module for WLAN ++** DATE : ++** AUTHOR : Ralf Janssen ++** DESCRIPTION : IFX Cross-Platform MMC for WLAN device driver header file ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 12 May 2010 Ralf Janssen Initial release ++*******************************************************************************/ ++/*! ++ \file ifx_mmc_wlan.h ++ \ingroup IFX_MMC_DRV ++ \brief MMC host driver for WLAN SDIO Card ++*/ ++ ++#ifndef __IFX_SDIO_WLAN_H__ ++#define __IFX_SDIO_WLAN_H__ ++ ++/*! ++ @brief Handle, that is returned by \ref ifx_sdio_open and is passed to all SDIO functions. ++ */ ++typedef uint32_t ifx_sdio_handle_t; ++ ++/*! ++ @brief Function pointer to callback handler. ++ ++ The WLAN driver (or any other driver using this SDIO driver) can use this callback handler ++ to get informed, when an asynchronous transaction has been completed. ++ */ ++typedef void (*ifx_sdio_callback_handler_t)(void *context, int status); ++ ++/*! ++ @brief Structure containing the required configuration and default parameters for the SDIO driver. ++ ++ This structure is passed to \ref ifx_sdio_open to configure the SDIO interface with respect to ++ clock, function select, block/byte mode, bus width, CRC handling, interrupt path (in-band/out-of-band) ++ and which GPIO is used for reset. ++ */ ++typedef struct ifx_sdio_config { ++ ifx_sdio_callback_handler_t callback_handler; /*!< Callback handler, used for async operations */ ++ void *context; /*!< Context of SDIO device driver, ++ will be passed to async callback handlers. */ ++ uint32_t clock; /*!< SDIO clock freuqency in Hz */ ++ ++ /* The following parameters are used to pre-define some parameters */ ++ /* used with almost all SDIO commands (CMD52/CMD53). */ ++ uint8_t function; /*!< Default function number in CMD52/53 */ ++ uint8_t raw; /*!< Default RAW flag in CMD52 */ ++ uint8_t block_mode; /*!< Default block-/byte-mode flag in CMD53 */ ++ uint8_t opcode; /*!< Default opcode flag in CMD53 */ ++ ++ uint16_t block_len; /*!< @brief Default block length for CMD53 block transfers */ ++ uint8_t bus_width; /*!< 1-/4-Bit bus */ ++ ++ /* The SDIO controller does not generate a CRC in byte mode */ ++ /* Therefore the driver allows to calculate and append the CRC in SW */ ++ uint8_t crc; /*!< If set, calculate and append CRC for CMD53 byte mode */ ++ uint8_t irq_oob; /*!< If set, use Out-Of-Band interrupt via GPIO29 */ ++ uint8_t rst_gpio; /*!< GPIO-Number for external reset (255 for none) */ ++} ifx_sdio_config_t; ++ ++ ++/*! ++ @brief Structure containing definition for SDIO commands. ++ ++ This structure contains information about the command (0..63), the argument of the command ++ and the response type (\ref MMC_RSP_TYPES). ++ */ ++typedef struct ifx_sdio_cmd { ++ uint32_t op_code; /*!< SDIO command (0..63) */ ++ uint32_t args; /*!< argument to SDIO command */ ++ uint32_t response_type; /*!< Response type (\ref MMC_RSP_TYPES) */ ++ uint32_t response[4]; /*!< Short/Long response from SDIO device */ ++ int error; /*!< return code of \ref ifx_sdio_cmd */ ++} ifx_sdio_cmd_t; ++ ++/*! ++ @internal ++ */ ++/*@{*/ ++/* response types, copied from linux-2.6.26.1/include/linux/mmc/core.h */ ++#define MMC_RSP_PRESENT (1 << 0) ++#define MMC_RSP_136 (1 << 1) /* 136 bit response */ ++#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ ++#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ ++#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ ++ ++/*! ++ @defgroup MMC_RSP_TYPES SDIO Response types ++ @{ ++ */ ++#define MMC_RSP_NONE (0) /*!< No response expected */ ++#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) /*!< Response R1 expected */ ++#define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY) /*!< Response R1B expected */ ++#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) /*!< Response R2 expected */ ++#define MMC_RSP_R3 (MMC_RSP_PRESENT) /*!< Response R3 expected */ ++#define MMC_RSP_R4 (MMC_RSP_PRESENT) /*!< Response R4 expected */ ++#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) /*!< Response R5 expected */ ++#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) /*!< Response R6 expected */ ++#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) /*!< Response R7 expected */ ++/* @} */ ++ ++ ++/* ++ * Exported functions ++ */ ++ ++/* open SDIO interface and set configuration */ ++/*! ++ * @brief ++ * This function opens the SDIO interface. ++ * ++ * It initializes all registers and activates the module clock.\n ++ * The second parameter allows to configure the operational mode. ++ * @param[in] ++ * dev_index Device index starting with 0 for the first SDIO device. ++ * @param[in] ++ * cfg Requested configuration of the SDIO interface. ++ * @return ++ * < 0 In case of errors (see errno.h for error codes).\n ++ * >=0 Device handle that is used to call SDIO functions. ++ */ ++ifx_sdio_handle_t ifx_sdio_open(int dev_index, ifx_sdio_config_t *cfg); ++ ++ ++/* close SDIO interface and release resources */ ++/*! ++ * @brief ++ * This function closes the SDIO interface. ++ * ++ * It clears all registers and deactivates the module clock. ++ * @param[in] ++ * sh Device handle returned by ifx_sdio_open ++ * @return ++ * < 0 In case of errors (see errno.h for error codes).\n ++ * 0 If no error ocurred. ++ */ ++int ifx_sdio_close(ifx_sdio_handle_t sh); ++ ++ ++/* configure various settings of the driver */ ++/*! ++ * @brief ++ * Provide ioctl style function for configuration purposes. ++ * ++ * ++ * @param[in] ++ * sh Device handle returned by \ref ifx_sdio_open ++ * @param[in] ++ * command Command that should be executed (\ref IFX_SDIO_IOCTL_COMMANDS).\n ++ * @param[in, out] ++ * param Parameter to command. The meaning is command specific ++ * ++ * @return ++ * < 0 In case of errors (see errno.h for error codes).\n ++ * 0 If no error ocurred. ++ */ ++int ifx_sdio_ioctl(ifx_sdio_handle_t sh, uint32_t command, uint32_t param); ++ ++/* Request SDIO device interrupt line from kernel and enable interrupt in SDIO core */ ++int ifx_sdio_request_irq(ifx_sdio_handle_t sh, irq_handler_t handler, ++ unsigned long flags, const char *dev_name, ++ void *dev_id); ++ ++/* Disable interrupt in SDIO core and free interrupt line. */ ++int ifx_sdio_free_irq (ifx_sdio_handle_t sh, void *dev_id); ++ ++/* This functions enables the SDIO device interrupt. */ ++int ifx_sdio_enable_irq (ifx_sdio_handle_t sh); ++ ++/* This function disables the SDIO device interrupt. */ ++int ifx_sdio_disable_irq (ifx_sdio_handle_t sh); ++ ++/* send a command to the SDIO device and wait for response */ ++int ifx_sdio_cmd(ifx_sdio_handle_t sh, ifx_sdio_cmd_t *cmd); ++ ++/* send a command to the SDIO device and wait for response, ++ provide all parameters directly */ ++int ifx_sdio_cmd_ext(ifx_sdio_handle_t sh, uint8_t op_code, uint32_t args, ++ uint32_t response_type, uint32_t *response); ++ ++/* write one byte via CMD52 to SDIO device */ ++int ifx_sdio_write_byte(ifx_sdio_handle_t sh, uint32_t address, ++ uint8_t in, uint8_t *out); ++ ++/* write one byte via CMD52 to SDIO device, but provide all parameter */ ++int ifx_sdio_write_byte_ext(ifx_sdio_handle_t sh, uint32_t address, ++ uint8_t function, uint8_t raw, ++ uint8_t in, uint8_t *out); ++ ++/* Write arbitrary number of bytes to device. ++ Return, when all data has been transferred. */ ++int ifx_sdio_write_sync(ifx_sdio_handle_t sh, uint32_t address, ++ void *data, uint32_t count); ++ ++/* Write arbitrary number of bytes to device, but provide all parameter. ++ Return, when all data has been transferred. */ ++int ifx_sdio_write_sync_ext(ifx_sdio_handle_t sh, uint32_t address, ++ void *data, uint32_t count, ++ uint8_t function, uint8_t block_len_pow, uint8_t opcode); ++ ++/* Write arbitrary number of bytes to device. ++ Return immediately after starting the transfer. */ ++int ifx_sdio_write_async(ifx_sdio_handle_t sh, uint32_t address, ++ void *data, uint32_t count); ++ ++/* Write arbitrary number of bytes to device, but provide all parameter ++ Return immediately after starting the transfer. */ ++int ifx_sdio_write_async_ext(ifx_sdio_handle_t sh, uint32_t address, ++ void *data, uint32_t count, ++ uint8_t function, uint8_t block_len_pow, uint8_t opcode); ++ ++/* Read a single byte via CMD52. */ ++int ifx_sdio_read_byte(ifx_sdio_handle_t sh, uint32_t address, uint8_t *pdata); ++ ++/* Read a single byte via CMD52, but provide all paramter. */ ++int ifx_sdio_read_byte_ext(ifx_sdio_handle_t sh, uint32_t address, ++ uint8_t function, uint8_t *pdata); ++ ++/* Read arbitrary number of bytes from device. ++ Return, when all data has been transferred. */ ++int ifx_sdio_read_sync (ifx_sdio_handle_t sh, uint32_t address, ++ void *data, uint32_t count); ++ ++/* Read arbitrary number of bytes from device, but provide all parameter. ++ Return, when all data has been transferred. */ ++int ifx_sdio_read_sync_ext (ifx_sdio_handle_t sh, uint32_t address, ++ void *data, uint32_t count, ++ uint8_t function, uint8_t block_len_pow, uint8_t opcode); ++ ++/* Read arbitrary number of bytes from device. ++ Return immediately after starting the transfer. */ ++int ifx_sdio_read_async (ifx_sdio_handle_t sh, uint32_t address, ++ void *data, uint32_t count); ++ ++/* Read arbitrary number of bytes from device, but provide all parameter. ++ Return immediately after starting the transfer. */ ++int ifx_sdio_read_async_ext(ifx_sdio_handle_t sh, uint32_t address, ++ void *data, uint32_t count, ++ uint8_t function, uint8_t block_len_pow, uint8_t opcode); ++ ++ ++ ++int ifx_sdio_enumerate(ifx_sdio_handle_t sh); ++ ++int ifx_sdio_poll_async_state(ifx_sdio_handle_t sh); ++ ++ ++/* ++ * IOCTL commands ++ */ ++/*! ++ @defgroup IFX_SDIO_IOCTL_COMMANDS IFX SDIO ioctl commands ++ @{ ++ ++ This section lists the available ioctl commands of the SDIO driver. ++ Also the meaning of the \ref ifx_sdio_ioctl parameter ++ is described per command. ++*/ ++ ++/*! ++ IFX_SDIO_IOCTL_SET_CLK sets the clock frequency of SDIO interface in Hz. ++ ++ @param The requested SDIO clock in HZ is specified as parameter in \ref ifx_sdio_ioctl. ++ The actual frequency is rounded to the next valid value less or equal to the requested one. ++*/ ++#define IFX_SDIO_IOCTL_SET_CLK 1 ++ ++/*! ++ IFX_SDIO_IOCTL_SET_BUS_WIDTH select the bus width of the SDIO interface, when using CMD53. ++ ++ @param Bus width selection as defined by \ref IFX_SDIO_IOCTL_PARAM_BUS_WIDTH. ++ */ ++#define IFX_SDIO_IOCTL_SET_BUS_WIDTH 2 ++ ++/*! ++ IFX_SDIO_IOCTL_SET_BLOCK_LENGTH sets the block length for CMD53 block-transactions. ++ ++ @param Block length in bytes. The block length must be a power of 2. ++ */ ++#define IFX_SDIO_IOCTL_SET_BLOCK_LENGTH 3 ++ ++/*! ++ IFX_SDIO_IOCTL_SET_FUNCTION modifies the by default selected function withtin the SDIO device. ++ This feature has not been implemented, yet. ++ ++ @param Function number (0..7) of SDIO device. ++ */ ++#define IFX_SDIO_IOCTL_SET_FUNCTION 4 ++/* @} */ ++ ++/*! ++ @defgroup IFX_SDIO_IOCTL_PARAM_BUS_WIDTH ioctl parameter for command \ref IFX_SDIO_IOCTL_SET_BUS_WIDTH ++ @{ ++ */ ++#define IFX_SDIO_IOCTL_BUS_WIDTH_1 0 /*!< Set Bus width to 1-Bit */ ++#define IFX_SDIO_IOCTL_BUS_WIDTH_4 1 /*!< Set Bus width to 4-Bit */ ++/* @} */ ++ ++#endif /* __IFX_SDIO_WLAN_H__ */ +diff --git a/arch/mips/include/asm/ifx/ifx_pmcu.h b/arch/mips/include/asm/ifx/ifx_pmcu.h +new file mode 100644 +index 0000000..128431d +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_pmcu.h +@@ -0,0 +1,417 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++#ifndef _IFX_PMCU_H_ ++#define _IFX_PMCU_H_ ++ ++#include "ifx_types.h" ++ ++/** ++ \file ifx_pmcu.h ++ PMCU (Power Management Control Unit) , userinterface controls and kernel API ++ ++ Header file contains defines, structures, constants and prototypes for I/O ++*/ ++ ++ ++/** ++ \defgroup LQ_PMCU_IOCTL IOCTL's ++ \ingroup LQ_PMCU ++*/ ++/* @{ */ ++/*=============================================================================*/ ++/* PMCU IOCTL DEFINES */ ++/*=============================================================================*/ ++/** Set a given module into a specific power state ++ ++ \param IFX_PMCU_MODULE_STATE_t* Pointer to a ++ \ref IFX_PMCU_MODULE_STATE_t structure. ++ ++ \return Returns value as follows: ++ - IFX_SUCCESS: if successful ++ - IFX_ERROR: in case of an error ++ ++ \code ++ IFX_PMCU_MODULE_STATE_t param; ++ param.pmcuModule=IFX_PMCU_MODULE_CPU; ++ param.pmcuModuleNr=0; ++ param.pmcuState=IFX_PMCU_STATE_D0; ++ ioctl(fd, IFX_PMCU_STATE_REQ, ¶m); ++ \endcode ++*/ ++#define IFX_PMCU_STATE_REQ 0 ++ ++ ++/** Get the current power state from a given module ++ \param IFX_PMCU_MODULE_STATE_t* Pointer to a ++ \ref IFX_PMCU_MODULE_STATE_t structure. ++ ++ \return Returns value as follows: ++ - IFX_SUCCESS: if successful ++ - IFX_ERROR: in case of an error ++ ++ \code ++ IFX_PMCU_MODULE_STATE_t param; ++ param.pmcuModule=IFX_PMCU_MODULE_CPU; ++ param.pmcuModuleNr=0; ++ param.pmcuState=IFX_PMCU_STATE_INVALID; ++ ioctl(fd, IFX_PMCU_STATE_GET, ¶m); ++ \endcode ++*/ ++#define IFX_PMCU_STATE_GET 1 ++ ++ ++/** Change the log level for the PMCU module ++ \param integer value which specifies the log level ++ - <0 = quiet ++ - 0 = only ERRORS,WARNINGS (default) ++ - 1 = + INFO ++ - 2 = all ++ ++ \return Returns value as follows: ++ - IFX_SUCCESS: if successful ++ - IFX_ERROR: in case of an error ++ ++ \code ++ int loglevel = 2; ++ ioctl(fd, IFX_PMCU_LOG_LEVEL, &loglevel); ++ \endcode ++*/ ++#define IFX_PMCU_LOG_LEVEL 2 ++ ++ ++/** Control the acceptance of the powerstate request for the ++ PMCU module. To have a central possibility for a global ++ enable/disable of the powerstate requests coming from other ++ modules, this IOCTL is introduced. ++ \param integer value to enable/disable the powerstate ++ request inside the PMCU driver. ++ - 0 = All powerstate requests received by the PMCU ++ will be rejected. Default ++ - 1 = Powerstate requests are accepted by the PMCU ++ ++ \return Returns value as follows: ++ - IFX_SUCCESS: if successful ++ - IFX_ERROR: in case of an error ++ ++ \code ++ enable the powerstate request acceptance ++ int reqCtrl = 1; ++ ioctl(fd, IFX_PMCU_REQ_CTRL, &reqCtrl); ++ \endcode ++*/ ++#define IFX_PMCU_REQ_CTRL 3 ++ ++//########################################## ++/** Switch the available power management features of the system ++ on and off. ++ ++ \param IFX_PMCU_MODULE_PWR_FEATURE_STATE_t* Pointer to struct ++ \ref IFX_PMCU_MODULE_PWR_FEATURE_STATE_t structure. ++ ++ \return Returns value as follows: ++ - IFX_SUCCESS: if successful ++ - IFX_ERROR: in case of an error ++ ++ \code ++ IFX_PMCU_MODULE_PWR_FEATURE_STATE_t param; ++ param.pmcuModule=IFX_PMCU_MODULE_CPU; ++ param.pmcuModuleNr=0; ++ param.pmcuPwrFeatureState=IFX_PMCU_PWR_STATE_OFF; ++ ioctl(fd, IFX_PMCU_PWR_FEATURE_SWITCH, ¶m); ++ \endcode ++*/ ++#define IFX_PMCU_PWR_FEATURE_SWITCH 4 ++ ++//########################################## ++ ++ ++ ++/* @} */ /* LQ_PMCU_IOCTL */ ++ ++/** ++ \defgroup LQ_PMCU Power Management Control Unit ++ \ingroup LQ_COC ++ Ifx pmcu driver module ++*/ ++/* @{ */ ++/*=============================================================================*/ ++/* PMCU ENUMERATION */ ++/*=============================================================================*/ ++/** IFX_PMCU_MODULE_t ++ Definition of the modules identifier ++ */ ++typedef enum { ++ IFX_PMCU_MODULE_PMCU = 0, /** all modules registered within PMCU */ ++ IFX_PMCU_MODULE_CPU = 1, ++ IFX_PMCU_MODULE_ETH = 2, ++ IFX_PMCU_MODULE_USB = 3, ++ IFX_PMCU_MODULE_DSL = 4, ++ IFX_PMCU_MODULE_WLAN = 5, ++ IFX_PMCU_MODULE_DECT = 6, ++ IFX_PMCU_MODULE_FXS = 7, ++ IFX_PMCU_MODULE_FXO = 8, ++ IFX_PMCU_MODULE_VE = 9, ++ IFX_PMCU_MODULE_PPE = 10, ++ IFX_PMCU_MODULE_SWITCH = 11, ++ IFX_PMCU_MODULE_UART = 12, ++ IFX_PMCU_MODULE_SPI = 13, ++ IFX_PMCU_MODULE_SDIO = 14, ++ IFX_PMCU_MODULE_PCI = 15, ++ IFX_PMCU_MODULE_VLYNQ = 16, ++ IFX_PMCU_MODULE_DEU = 17, ++ IFX_PMCU_MODULE_CPU_PS = 18, ++ IFX_PMCU_MODULE_GPTC = 19, ++ IFX_PMCU_MODULE_USIF_UART = 20, /* VR9 usage */ ++ IFX_PMCU_MODULE_USIF_SPI = 21, /* VR9 usage */ ++ IFX_PMCU_MODULE_PCIE = 22, /* VR9 usage */ ++ IFX_PMCU_MODULE_ID_MAX = 23, ++} IFX_PMCU_MODULE_t; ++ ++ ++/** IFX_PMCU_STATE_t ++ Definition of power management state ++*/ ++typedef enum { ++ /* ATTENTION: Keep in mind that this list correspond to the ifx_pmcu_stateMap[][] array. ++ If you have to change this list for any reason, ifx_pmcu_stateMap[][] must be adapted too. */ ++ ++ /** State Invalid. */ ++ IFX_PMCU_STATE_INVALID = 0, ++ /** State D0. Fully on */ ++ IFX_PMCU_STATE_D0 = 1, ++ /** State D1. Device dependent */ ++ IFX_PMCU_STATE_D1 = 2, ++ /** State D2. Device dependent */ ++ IFX_PMCU_STATE_D2 = 3, ++ /** State D3. Off */ ++ IFX_PMCU_STATE_D3 = 4, ++ /** don't care state */ ++ IFX_PMCU_STATE_D0D3 = 5, ++} IFX_PMCU_STATE_t; ++ ++ ++//################################################# ++typedef enum { ++ /** State Invalid. */ ++ IFX_PMCU_PWR_STATE_INVALID = 0, ++ /** Features State on */ ++ IFX_PMCU_PWR_STATE_ON = 1, ++ /** Features State off */ ++ IFX_PMCU_PWR_STATE_OFF = 2, ++} IFX_PMCU_PWR_STATE_ENA_t; ++//################################################# ++ ++ ++ ++/** IFX_PMCU_TRANSITION_t ++ Event passed to the PMCU ++ \remarks Reserved for future use. ++*/ ++typedef enum { ++ /** No event to be reported */ ++ IFX_PMCU_EVENT_NONE = 0, ++ /** State change */ ++ IFX_PMCU_EVENT_STATE = 1, ++ /** Module activated */ ++ IFX_PMCU_EVENT_ACTIVATED = 2, ++ /** Module deactivated */ ++ IFX_PMCU_EVENT_DEACTIVATED = 3, ++ /** Device dependent event EXT1 */ ++ IFX_PMCU_EVENT_EXT1 = 4, ++ /** Device dependent event EXT2 */ ++ IFX_PMCU_EVENT_EXT2 = 5, ++} IFX_PMCU_TRANSITION_t; ++ ++ ++/** IFX_PMCU_RETURN_t ++ Return value for PMCU functions and callbacks ++*/ ++typedef enum { ++ /** Operation success */ ++ IFX_PMCU_RETURN_SUCCESS = 0, ++ /** Operation denied */ ++ IFX_PMCU_RETURN_DENIED = 1, ++ /** Error condition */ ++ IFX_PMCU_RETURN_ERROR = 2, ++ /** called function just return without doing anything; used only in callback functions */ ++ IFX_PMCU_RETURN_NOACTIVITY = 3, ++ /** is used if callback function is not defined */ ++ IFX_PMCU_RETURN_NOTDEFINED = 4, ++} IFX_PMCU_RETURN_t; ++ ++ ++/*=============================================================================*/ ++/* PMCU STRUCTURES */ ++/*=============================================================================*/ ++/** IFX_PMCU_MODULE_STATE_t ++ Structure hold the module-ID, the moduleSub-ID and the PowerState of one module. ++*/ ++typedef struct { ++ /** Module identifier */ ++ IFX_PMCU_MODULE_t pmcuModule; ++ /** instance identification of a Module; values 0,1,2,..... (0=first instance) */ ++ IFX_uint8_t pmcuModuleNr; ++ /** Module PowerState */ ++ IFX_PMCU_STATE_t pmcuState; ++} IFX_PMCU_MODULE_STATE_t; ++ ++//################################### ++/** IFX_PMCU_MODULE_PWR_FEATURE_STATE_t ++ Structure hold the module-ID and the PowerFeature_State to be set for a dedicated module. ++*/ ++typedef struct { ++ /** Module identifier */ ++ IFX_PMCU_MODULE_t pmcuModule; ++ /** instance identification of a Module; values 0,1,2,..... (0=first instance) */ ++ IFX_uint8_t pmcuModuleNr; ++ /** Module PowerFeatureState */ ++ IFX_PMCU_PWR_STATE_ENA_t pmcuPwrFeatureState; ++} IFX_PMCU_MODULE_PWR_FEATURE_STATE_t; ++//################################### ++ ++ ++/** IFX_PMCU_STATES_DEP_t ++ Structure that describes dependencies on the given power-states of the ++ given module. ++*/ ++typedef struct { ++ /** Module identifier */ ++ IFX_PMCU_MODULE_t pmcuModule; ++ /** instance identification of a Module; values 0,1,2,..... (0=first instance) */ ++ IFX_uint8_t pmcuModuleNr; ++ /** possible values: D0, D1, D2, D3 */ ++ IFX_PMCU_STATE_t onState; ++ /** possible values: D0, D1, D2, D3 */ ++ IFX_PMCU_STATE_t standBy; ++ /** possible values: D0, D1, D2, D3 */ ++ IFX_PMCU_STATE_t lpStandBy; ++ /** possible values: D0, D1, D2, D3 */ ++ IFX_PMCU_STATE_t offState; ++} IFX_PMCU_STATES_DEP_t; ++ ++ ++/** IFX_PMCU_MODULE_DEP_t ++ Structure to list dependencies on multiple modules. ++*/ ++typedef struct { ++ /** number of entries in the dependency list moduleStates[] */ ++ IFX_uint32_t nDepth; ++ /** power state dependency list(s) of one module */ ++ IFX_PMCU_STATES_DEP_t moduleStates[]; ++} IFX_PMCU_MODULE_DEP_t; ++ ++ ++/**IFX_PMCU_EVENT_t ++ Structure used to report an information to the PMCU ++ \remarks Reserved for future use. ++ */ ++typedef struct { ++ /** Module identifier */ ++ IFX_PMCU_MODULE_t pmcuModule; ++ /** instance identification of a Module; values 0,1,2,..... (0=first instance) */ ++ IFX_uint8_t pmcuModuleNr; ++ /** Current module state */ ++ IFX_PMCU_STATE_t pmcuState; ++ /** Transition passed to the PMCU */ ++ IFX_PMCU_TRANSITION_t pmcuTransition; ++} IFX_PMCU_EVENT_t; ++ ++ ++/** IFX_PMCU_REGISTER_t ++ Structure used to register/unregister a driver to the PMCU ++*/ ++typedef struct { ++ /** Module identifier */ ++ IFX_PMCU_MODULE_t pmcuModule; ++ /** instance identification of a Module; values 0,1,2,..... (0=first instance) */ ++ IFX_uint8_t pmcuModuleNr; ++ /** pointer to the module dependency list. ++ The dependency list will be copied into a static structure inside the PMCU. */ ++ IFX_PMCU_MODULE_DEP_t *pmcuModuleDep; ++ /** Callback to be called before module changes it's state to new */ ++ IFX_PMCU_RETURN_t (*pre) ( IFX_PMCU_MODULE_t pmcuModule, ++ IFX_PMCU_STATE_t newState, ++ IFX_PMCU_STATE_t oldState); ++ /** Callback used to change module's power state */ ++ IFX_PMCU_RETURN_t (*ifx_pmcu_state_change) ( IFX_PMCU_STATE_t pmcuState ); ++ /** Callback to be called after module changes it's state to new state */ ++ IFX_PMCU_RETURN_t (*post) ( IFX_PMCU_MODULE_t pmcuModule, ++ IFX_PMCU_STATE_t newState, ++ IFX_PMCU_STATE_t oldState); ++ /** Optional: Callback used to get module's power state. Set to NULL if unused */ ++ IFX_PMCU_RETURN_t (*ifx_pmcu_state_get) ( IFX_PMCU_STATE_t *pmcuState ); ++//################################### ++ /** Callback used to enable/disable the power features of the module */ ++ IFX_PMCU_RETURN_t (*ifx_pmcu_pwr_feature_switch) ( IFX_PMCU_PWR_STATE_ENA_t pmcuPwrStateEna ); ++//################################### ++ ++} IFX_PMCU_REGISTER_t; ++/* @} */ /* LQ_PMCU */ ++ ++/** ++ \defgroup LQ_PMCU_KERNEL_API Kernel API ++ \ingroup LQ_PMCU ++*/ ++/* @{ */ ++/*=============================================================================*/ ++/* PMCU FUNCTION PROTOTYPES */ ++/*=============================================================================*/ ++#ifdef __KERNEL__ ++/** ++ PMCU kernel API prototypes ++*/ ++ ++/** ++ Request module state change to PMCU ++ ++ \param [in] pmcuModule define module for state change ++ \param [in] pmcuModuleNr instance identification of a Module; values 0,1,2,..... (0=first instance) ++ \param [in] newState requested power state ++ ++ \return Returns value as follows: ++ - IFX_PMCU_RETURN_SUCCESS: if successful ++ - IFX_PMCU_RETURN_ERROR: in case of an error ++ ++*/ ++IFX_PMCU_RETURN_t ifx_pmcu_state_req (IFX_PMCU_MODULE_t pmcuModule, IFX_uint8_t pmcuModuleNr, IFX_PMCU_STATE_t newState); ++ ++ ++/** ++ Register a module, which is affected by a powerState change or initiate a powerState change, to the PMCU ++ ++ \param [in] pmcuRegister Registration Information ++ ++ \return Returns value as follows: ++ - IFX_PMCU_RETURN_SUCCESS: if successful ++ - IFX_PMCU_RETURN_ERROR: in case of an error ++ ++*/ ++IFX_PMCU_RETURN_t ifx_pmcu_register (IFX_PMCU_REGISTER_t* pmcuRegister); ++ ++ ++/** ++ Unregister a module from the PMCU. ++ ++ \param [in] pmcuUnregister Unregistration Information. Only module name is required. ++ ++ \return Returns value as follows: ++ - IFX_PMCU_RETURN_SUCCESS: if successful ++ - IFX_PMCU_RETURN_ERROR: in case of an error ++ ++*/ ++IFX_PMCU_RETURN_t ifx_pmcu_unregister (IFX_PMCU_REGISTER_t* pmcuUnregister); ++ ++#endif /* __KERNEL__ */ ++ ++/* @} */ /* LQ_PMCU_KERNEL_API */ ++ ++#endif /* _IFX_PMCU_H_ */ ++ +diff --git a/arch/mips/include/asm/ifx/ifx_pmon.h b/arch/mips/include/asm/ifx/ifx_pmon.h +new file mode 100644 +index 0000000..acccc08 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_pmon.h +@@ -0,0 +1,204 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_pmon.h ++** PROJECT : IFX UEIP ++** MODULES : PMON ++** ++** DATE : 21 July 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : IFX Performance Monitor ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 21 July 2009 Lei Chuanhua The first UEIP release ++*******************************************************************************/ ++ ++/** ++ \defgroup IFX_PMON Performance Monitor Interface Module ++ \brief ifx pmon driver module ++*/ ++ ++/*! ++ \defgroup IFX_PMON_DEFINITIONS Defintions and structures ++ \ingroup IFX_PMON ++ \brief definitions for ifx pmon driver ++*/ ++ ++/*! ++ \defgroup IFX_PMON_IOCTL User API IOCTL ++ \ingroup IFX_PMON ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \file ifx_pmon.h ++ \ingroup IFX_PMON ++ \brief ifx pmon driver header file for APIs ++*/ ++#ifndef IFX_PMON_H ++#define IFX_PMON_H ++/*! ++ \addtogroup IFX_PMON_DEFINITIONS ++ */ ++/* @{ */ ++#ifdef CONFIG_VR9 ++/*! \enum IFX_PMON_EVENT ++ \brief External PMON Event defintion ++ */ ++enum IFX_PMON_EVENT { ++ IFX_PMON_EVENT_NONE = 0, /*!< No input (default) */ ++#define IFX_PMON_EVENT_MIN IFX_PMON_EVENT_NONE ++ IFX_PMON_EVENT_DDR_READ, /*!< DDR read commands, independent of length */ ++ IFX_PMON_EVENT_DDR_WRITE, /*!< DDR write commands, independent of length */ ++ IFX_PMON_EVENT_DDR_MASK_WRITE, /*!< DDR masked write commands */ ++ IFX_PMON_EVENT_DDR_ONE_WORD_64BIT_READ,/*!< Single-word 64-bit read commands */ ++ IFX_PMON_EVENT_DDR_TWO_WORD_64BIT_READ,/*!< 2-beat burst 64-bit read commands */ ++ IFX_PMON_EVENT_DDR_FOUR_WORD_64BIT_READ,/*!< 4-word 64-bit read commands */ ++ IFX_PMON_EVENT_DDR_EIGHT_WORD_64BIT_READ,/*!< 8-word 64-bit read commands */ ++ IFX_PMON_EVENT_DDR_ONE_WORD_64BIT_WRITE,/*!< Single 64-bit write commands */ ++ IFX_PMON_EVENT_DDR_TWO_WORD_64BIT_WRITE, /*!< 2-word 64-bit write commands */ ++ IFX_PMON_EVENT_DDR_FOUR_WORD_64BIT_WRITE,/*!< 4-word 64-bit write commands */ ++ IFX_PMON_EVENT_DDR_EIGHT_WORD_64BIT_WIRTE,/*!< 8-word 64-bit write commands */ ++ IFX_PMON_EVENT_AHB_READ_CYCLES, /*!< DMA 32-bit receive block counter */ ++ IFX_PMON_EVENT_AHB_READ_CPT, /*!< DMA 32-bit transmit block counter */ ++ IFX_PMON_EVENT_AHB_WRITE_CYCLES,/*!< AHB read completed */ ++ IFX_PMON_EVENT_AHB_WRITE_CPT, /*!< AHB write completed */ ++ IFX_PMON_EVENT_DMA_RX_BLOCK_CNT,/*!< AHB total read cycles */ ++ IFX_PMON_EVENT_DMA_TX_BLOCK_CNT,/*!< AHB total write cycles */ ++#define IFX_PMON_EVENT_MAX IFX_PMON_EVENT_DMA_TX_BLOCK_CNT ++}; ++#elif defined (CONFIG_AR10) ++#define IFX_PMON_EVENT_NONE 0 ++#define IFX_PMON_BIU0_READ_EVENT 0x04 /*!< Bus interface Unit0 read */ ++#define IFX_PMON_BIU0_WRITE_EVENT 0x05 /*!< Bus interface Unit0 write */ ++#define IFX_PMON_BIU1_READ_EVENT 0x06 /*!< Bus interface Unit1 read */ ++#define IFX_PMON_BIU1_WRITE_EVENT 0x07 /*!< Bus interface Unit1 write */ ++ ++#define IFX_PMON_EVENT_MIN IFX_PMON_EVENT_NONE ++ ++/* DMA */ ++#define IFX_PMON_DMA_READ_EVENT 0x0C /*!< DMA read */ ++#define IFX_PMON_DMA_WRITE_EVENT 0x0D /*!< DMA write */ ++#define IFX_PMON_DMA_RX_EVENT 0x0E /*!< DMA payload rx */ ++#define IFX_PMON_DMA_TX_EVENT 0x0F /*!< DMA payload tx */ ++ ++/* PPE, GPHY, ethernet */ ++#define IFX_PMON_FPI1S_READ_EVENT 0x14 /*!< FPI1 Slave bus read */ ++#define IFX_PMON_FPI1S_WRITE_EVENT 0x15 /*!< FPI1 Slave bus write */ ++ ++/* WLAN BB/MAC, CPU DMA */ ++#define IFX_PMON_AHB1S_READ_EVENT 0x18 /*!< AHB1 Slave bus read */ ++#define IFX_PMON_AHB1S_WRITE_EVENT 0x19 /*!< AHB1 Slave bus write */ ++ ++/* USB, DSL */ ++#define IFX_PMON_AHB2S_READ_EVENT 0x1C /*!< AHB2 Slave bus read */ ++#define IFX_PMON_AHB2S_WRITE_EVENT 0x1D /*!< AHB2 Slave bus write */ ++ ++/* PCIe */ ++#define IFX_PMON_AHB4S_READ_EVENT 0x20 /*!< AHB4 Slave bus read */ ++#define IFX_PMON_AHB4S_WRITE_EVENT 0x21 /*!< AHB4 Slave bus Write */ ++ ++/* DDR */ ++#define IFX_PMON_DDR_READ_EVENT 0x40 /*!< DDR single read */ ++#define IFX_PMON_DDR_WRITE_EVENT 0x41 /*!< DDR single write */ ++#define IFX_PMON_DDR_CMD_QUEUE_ALMOST_FULL 0x43 /*!< DDR Command Queue Almost Full */ ++#define IFX_PMON_DDR_CKE_STAT 0x44 /*!< DDR CKE status */ ++#define IFX_PMON_DDR_REFRESH_IN_PROGRESS 0x45 /*!< DDR Refresh in progress */ ++#define IFX_PMON_DDR_CONTROLLER_BUSY 0x46 /*!< DDR Controller Busy */ ++#define IFX_PMON_DDR_CMD_QUEUE_FULL 0x47 /*!< DDR Command Queue Full */ ++ ++/* SRAM */ ++#define IFX_PMON_SRAM_READ_EVENT 0x50 /*!< SRAM read */ ++#define IFX_PMON_SRAM_WRITE_EVENT 0x51 /*!< SRAM write */ ++ ++/* FPI2M */ ++#define IFX_PMON_FPI2M_READ_EVENT 0x58 /*!< FPI2 master read */ ++#define IFX_PMON_FPI2M_WRITE_EVENT 0x59 /*!< FPI2 master write */ ++ ++/* FPI3M */ ++#define IFX_PMON_FPI3M_READ_EVENT 0x5C /*!< FPI3 master read */ ++#define IFX_PMON_FPI3M_WRITE_EVENT 0x5D /*!< FPI3 master write */ ++ ++/* AHB3M */ ++#define IFX_PMON_AHB3M_READ_EVENT 0x60 /*!< AHB3 master read */ ++#define IFX_PMON_AHB3M_WRITE_EVENT 0x61 /*!< AHB3 master write */ ++ ++#define IFX_PMON_EVENT_MAX IFX_PMON_AHB3M_WRITE_EVENT ++#else ++#error "platform not supported" ++#endif ++ ++ ++#define IFX_PMON_XTC_COUNTER0 0 ++ ++#define IFX_PMON_XTC_COUNTER1 1 ++ ++#define IFX_PMON_MAX_PERF_CNT_PER_TC 2 ++ ++/* @} */ ++ ++/*! \enum IFX_MIPS_TC ++ \brief Multithread Index ++ */ ++enum IFX_MIPS_TC{ ++ IFX_MIPS_TC0 = 0, /*!< MT TC 0 */ ++ IFX_MIPS_TC1, /*!< MT TC 1 */ ++ IFX_MIPS_TC2, /*!< MT TC 2 */ ++ IFX_MIPS_TC3, /*!< MT TC 3 */ ++}; ++ ++/*! ++ \addtogroup IFX_PMON_IOCTL ++ */ ++/* @{ */ ++/*! ++ \brief Structure describing pmon version ++ */ ++struct ifx_pmon_ioctl_version { ++ unsigned int major; /*!< Version Major number */ ++ unsigned int mid; /*!< Version Mid number */ ++ unsigned int minor; /*!< Version Minor number */ ++}; ++ ++/*! ++ \brief Structure describing pmon event ++ */ ++struct ifx_pmon_ioctl_event { ++ unsigned int pmon_event; /*!< PMON external even id */ ++ unsigned int counter; /*!< CPU performance counter 0 or 1 */ ++ unsigned int tc; /*!< MT TC index 0~3*/ ++}; ++ ++/*! ++ * \def IFX_PMON_IOC_MAGIC ++ * \brief PMON IOCTL Magic number ++ */ ++#define IFX_PMON_IOC_MAGIC 0xef ++/*! ++ * \def IFX_PMON_IOC_VERSION ++ * \brief PMON IOCTL to get version number ++ */ ++#define IFX_PMON_IOC_VERSION _IOR( IFX_PMON_IOC_MAGIC, 0, struct ifx_pmon_ioctl_version) ++/*! ++ * \def IFX_PMON_IOC_EVENT ++ * \brief PMON IOCTL to configure external event and CPU performance counter 0/1 ++ */ ++#define IFX_PMON_IOC_EVENT _IOWR(IFX_PMON_IOC_MAGIC, 1, struct ifx_pmon_ioctl_event) ++/*! ++ * \def IFX_PMON_IOC_DISABLE ++ * \brief PMON IOCTL to disable PMON module ++ */ ++ ++#define IFX_PMON_IOC_DISABLE _IOWR(IFX_PMON_IOC_MAGIC, 2, int) ++/* @} */ ++ ++#endif /* IFX_PMON_H */ ++ +diff --git a/arch/mips/include/asm/ifx/ifx_pmu.h b/arch/mips/include/asm/ifx/ifx_pmu.h +new file mode 100644 +index 0000000..9f00195 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_pmu.h +@@ -0,0 +1,776 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_pmu.h ++** PROJECT : IFX UEIP ++** MODULES : PMU ++** ++** DATE : 28 May 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : IFX Cross-Platform Power Management Unit driver header file ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 28 May 2009 Lei Chuanhua The first UEIP release ++*******************************************************************************/ ++#ifndef IFX_PMU_H ++#define IFX_PMU_H ++ ++/*! ++ \defgroup IFX_PMU PMU driver module ++ \brief UEIP Project - PMU module. ++*/ ++ ++/*! ++ \defgroup IFX_PMU_DEFINITIONS Definition and structions ++ \ingroup IFX_PMU ++ \brief definitions for ifx pmu driver ++*/ ++ ++/*! ++ \file ifx_pmu.h ++ \ingroup IFX_PMU ++ \brief header file for PMU external interface ++*/ ++/*! ++ \addtogroup IFX_PMU_DEFINITIONS ++*/ ++/* @{ */ ++ ++/*! \def IFX_PMU_MODULE_USB0_PHY ++ \brief USB0 PHY Module ++ */ ++#define IFX_PMU_MODULE_USB0_PHY (0) ++ ++/*! \def IFX_PMU_MODULE_USB_PHY ++ \brief USB PHY Module ++ */ ++#define IFX_PMU_MODULE_USB_PHY IFX_PMU_MODULE_USB0_PHY ++ ++/*! \def IFX_PMU_MODULE_FPIS ++ \brief FPI Slave Module ++ */ ++#define IFX_PMU_MODULE_FPIS (1) ++ ++/*! \def IFX_PMU_MODULE_FPI1 ++ \brief FPI bus 1 Module ++ */ ++#define IFX_PMU_MODULE_FPI1 IFX_PMU_MODULE_FPIS ++ ++/*! \def IFX_PMU_MODULE_FPI2 ++ \brief FPI bus 2 Module ++ */ ++#define IFX_PMU_MODULE_FPI2 IFX_PMU_MODULE_FPI1 ++ ++/*! \def IFX_PMU_MODULE_DFEV0 ++ \brief DFEV 0 Module ++ */ ++#define IFX_PMU_MODULE_DFEV0 (2) ++#ifdef CONFIG_AMAZON_SE ++/*! \def IFX_PMU_MODULE_SDIO ++ \brief SDIO Module, ASE only ++ */ ++#define IFX_PMU_MODULE_SDIO IFX_PMU_MODULE_DFEV0 ++#endif ++/*! \def IFX_PMU_MODULE_DFEV1 ++ \brief DFEV 1 Module ++ */ ++#define IFX_PMU_MODULE_DFEV1 (3) ++ ++/*! \def IFX_PMU_MODULE_VO_MIPS ++ \brief Voice MIPS Module ++ */ ++#define IFX_PMU_MODULE_VO_MIPS IFX_PMU_MODULE_DFEV0 ++ ++/*! \def IFX_PMU_MODULE_VODEC ++ \brief Voice Decoder Module ++ */ ++#define IFX_PMU_MODULE_VODEC IFX_PMU_MODULE_DFEV1 ++ ++/*! \def IFX_PMU_MODULE_PCI ++ \brief PCI Module ++ */ ++#define IFX_PMU_MODULE_PCI (4) ++ ++/*! \def IFX_PMU_MODULE_DMA ++ \brief DMA Module ++ */ ++#define IFX_PMU_MODULE_DMA (5) ++ ++/*! \def IFX_PMU_MODULE_USB0_CTRL ++ \brief USB0 Controller Module ++ */ ++#define IFX_PMU_MODULE_USB0_CTRL (6) ++ ++/*! \def IFX_PMU_MODULE_USB_CTRL ++ \brief USB Controller Module ++ */ ++#define IFX_PMU_MODULE_USB_CTRL IFX_PMU_MODULE_USB0_CTRL ++ ++/*! \def IFX_PMU_MODULE_USIF ++ \brief USIF Module ++ */ ++#define IFX_PMU_MODULE_USIF (7) ++ ++/*! \def IFX_PMU_MODULE_UART0 ++ \brief UART0/ASC0 Module ++ */ ++#define IFX_PMU_MODULE_UART0 IFX_PMU_MODULE_USIF ++ ++/*! \def IFX_PMU_MODULE_EPHY ++ \brief EPHY Module ++ */ ++#define IFX_PMU_MODULE_EPHY IFX_PMU_MODULE_UART0 ++ ++/*! \def IFX_PMU_MODULE_SPI ++ \brief SSC/SPI Module ++ */ ++#define IFX_PMU_MODULE_SPI (8) ++ ++/*! \def IFX_PMU_MODULE_DSL_DFE ++ \brief DSL /DFE Module ++ */ ++#define IFX_PMU_MODULE_DSL_DFE (9) ++ ++/*! \def IFX_PMU_MODULE_EBU ++ \brief EBU Module ++ */ ++#define IFX_PMU_MODULE_EBU (10) ++ ++/*! \def IFX_PMU_MODULE_LEDC ++ \brief LEDc Controller Module ++ */ ++#define IFX_PMU_MODULE_LEDC (11) ++ ++/*! \def IFX_PMU_MODULE_GPTC ++ \brief GPTU Module ++ */ ++#define IFX_PMU_MODULE_GPTC (12) ++ ++/*! \def IFX_PMU_MODULE_AHBS ++ \brief AHB Slave Module ++ */ ++#define IFX_PMU_MODULE_AHBS (13) ++ ++/*! \def IFX_PMU_MODULE_PCIE1_PHY ++ \brief PCIe 1 PHY module ++ */ ++#define IFX_PMU_MODULE_PCIE1_PHY IFX_PMU_MODULE_AHBS ++ ++/*! \def IFX_PMU_MODULE_PPE_TPE ++ \brief PPE/TPE Module ++ */ ++#define IFX_PMU_MODULE_PPE_TPE IFX_PMU_MODULE_AHBS ++ ++/*! \def IFX_PMU_MODULE_VLYNQ ++ \brief VLYNQ Module ++ */ ++#define IFX_PMU_MODULE_VLYNQ IFX_PMU_MODULE_AHBS ++ ++/*! \def IFX_PMU_MODULE_FPIM ++ \brief FPI Master Module ++ */ ++#define IFX_PMU_MODULE_FPIM (14) ++ ++/*! \def IFX_PMU_MODULE_ADSL_AFE ++ \brief AR10 ADSL AFE Module ++ */ ++#define IFX_PMU_MODULE_ADSL_AFE IFX_PMU_MODULE_FPIM ++ ++/*! \def IFX_PMU_MODULE_FPI0 ++ \brief FPI bus 0 Module ++ */ ++#define IFX_PMU_MODULE_FPI0 IFX_PMU_MODULE_FPIM ++ ++/*! \def IFX_PMU_MODULE_AHBM ++ \brief AHB Master Module ++ */ ++#define IFX_PMU_MODULE_AHBM (15) ++ ++/*! \def IFX_PMU_MODULE_DCDC_2V5 ++ \brief AR10 DCDC 2.5V Module ++ */ ++#define IFX_PMU_MODULE_DCDC_2V5 IFX_PMU_MODULE_AHBM ++ ++/*! \def IFX_PMU_MODULE_AHB ++ \brief AHB Module ++ */ ++#define IFX_PMU_MODULE_AHB IFX_PMU_MODULE_AHBM ++#ifndef CONFIG_AMAZON_SE ++/*! \def IFX_PMU_MODULE_SDIO ++ \brief SDIO Module, ARX,Danube, VRX ++ */ ++#define IFX_PMU_MODULE_SDIO (16) ++#endif ++/*! \def IFX_PMU_MODULE_UART1 ++ \brief UART1/ASC1 module ++ */ ++#define IFX_PMU_MODULE_UART1 (17) ++ ++/*! \def IFX_PMU_MODULE_PPE_QSB ++ \brief PPE QSB module ++ */ ++#define IFX_PMU_MODULE_PPE_QSB (18) ++ ++/*! \def IFX_PMU_MODULE_DCDC_1VX ++ \brief AR10 DCDC 1.5V and 1.8V Module ++ */ ++#define IFX_PMU_MODULE_DCDC_1VX IFX_PMU_MODULE_PPE_QSB ++ ++/*! \def IFX_PMU_MODULE_PPE_SLL01 ++ \brief PPE SLL01 module ++ */ ++#define IFX_PMU_MODULE_PPE_SLL01 (19) ++ ++/*! \def IFX_PMU_MODULE_DCDC_1V0 ++ \brief AR10 DCDC 1.0V Module ++ */ ++#define IFX_PMU_MODULE_DCDC_1V0 IFX_PMU_MODULE_PPE_SLL01 ++ ++/*! \def IFX_PMU_MODULE_WDT0 ++ \brief WDT0 module ++ */ ++#define IFX_PMU_MODULE_WDT0 IFX_PMU_MODULE_PPE_QSB ++ ++/*! \def IFX_PMU_MODULE_WDT1 ++ \brief WDT1 module ++ */ ++#define IFX_PMU_MODULE_WDT1 IFX_PMU_MODULE_PPE_SLL01 ++ ++/*! \def IFX_PMU_MODULE_DEU ++ \brief DEU module ++ */ ++#define IFX_PMU_MODULE_DEU (20) ++ ++/*! \def IFX_PMU_MODULE_PPE_TC ++ \brief PPE TC module ++ */ ++#define IFX_PMU_MODULE_PPE_TC (21) ++ ++/*! \def IFX_PMU_MODULE_PPE_EMA ++ \brief PPE EMA module ++ */ ++#define IFX_PMU_MODULE_PPE_EMA (22) ++ ++/*! \def IFX_PMU_MODULE_PPE_ENET1 ++ \brief PPE ENET1 module ++ */ ++#define IFX_PMU_MODULE_PPE_ENET1 IFX_PMU_MODULE_PPE_EMA ++ ++/*! \def IFX_PMU_MODULE_PPE_DPLUSM ++ \brief Dplus Master module ++ */ ++#define IFX_PMU_MODULE_PPE_DPLUSM (23) ++ ++/*! \def IFX_PMU_MODULE_PPE_DPLUS ++ \brief Dplus module ++ */ ++#define IFX_PMU_MODULE_PPE_DPLUS IFX_PMU_MODULE_PPE_DPLUSM ++ ++/*! \def IFX_PMU_MODULE_PPE_ENET0 ++ \brief PPE ENET0 module ++ */ ++#define IFX_PMU_MODULE_PPE_ENET0 IFX_PMU_MODULE_PPE_DPLUSM ++ ++/*! \def IFX_PMU_MODULE_PPE_DPLUSS ++ \brief Dplus Slave module ++ */ ++#define IFX_PMU_MODULE_PPE_DPLUSS (24) ++ ++/*! \def IFX_PMU_MODULE_DDR_MEM ++ \brief DDR MC module ++ */ ++#define IFX_PMU_MODULE_DDR_MEM IFX_PMU_MODULE_PPE_DPLUSS ++ ++/*! \def IFX_PMU_MODULE_TDM ++ \brief TDM module ++ */ ++#define IFX_PMU_MODULE_TDM (25) ++ ++/*! \def IFX_PMU_MODULE_USB1_PHY ++ \brief USB 1 PHY module ++ */ ++#define IFX_PMU_MODULE_USB1_PHY (26) ++ ++/*! \def IFX_PMU_MODULE_USB1_CTRL ++ \brief USB1 Controller module ++ */ ++#define IFX_PMU_MODULE_USB1_CTRL (27) ++ ++/*! \def IFX_PMU_MODULE_SWITCH ++ \brief Switch module ++ */ ++#define IFX_PMU_MODULE_SWITCH (28) ++ ++/*! \def IFX_PMU_MODULE_PPE_TOP ++ \brief PPE Top module ++ */ ++#define IFX_PMU_MODULE_PPE_TOP (29) ++ ++/*! \def IFX_PMU_MODULE_DDR_DPD ++ \brief DDR DPD module ++ */ ++#define IFX_PMU_MODULE_DDR_DPD IFX_PMU_MODULE_PPE_TOP ++ ++/*! \def IFX_PMU_MODULE_GPHY0 ++ \brief GPHY0 module ++ */ ++#define IFX_PMU_MODULE_GPHY0 IFX_PMU_MODULE_PPE_TOP ++ ++ ++/*! \def IFX_PMU_MODULE_GPHY ++ \brief Internal GPHY module ++ */ ++#define IFX_PMU_MODULE_GPHY (30) ++ ++/*! \def IFX_PMU_MODULE_GPHY1 ++ \brief Internal GPHY1 module ++ */ ++#define IFX_PMU_MODULE_GPHY1 IFX_PMU_MODULE_GPHY ++ ++/*! \def IFX_PMU_MODULE_PCIE_L0_CLK ++ \brief PCIe L0 Clock module ++ */ ++#define IFX_PMU_MODULE_PCIE_L0_CLK (31) ++ ++/*! \def IFX_PMU_MODULE_GPHY2 ++ \brief Internal GPHY2 module ++ */ ++#define IFX_PMU_MODULE_GPHY2 IFX_PMU_MODULE_PCIE_L0_CLK ++ ++/*! \def IFX_PMU_MODULE_PCIE_PHY ++ \brief PCIe PHY module ++ */ ++#define IFX_PMU_MODULE_PCIE_PHY (32) ++ ++/*! \def IFX_PMU_MODULE_PCIE0_PHY ++ \brief PCIe 0 PHY module ++ */ ++#define IFX_PMU_MODULE_PCIE0_PHY IFX_PMU_MODULE_PCIE_PHY ++ ++/*! \def IFX_PMU_MODULE_PCIE_CTRL ++ \brief PCIe Controller module ++ */ ++#define IFX_PMU_MODULE_PCIE_CTRL (33) ++ ++/*! \def IFX_PMU_MODULE_PCIE0_CTRL ++ \brief PCIe Controller 0 module ++ */ ++#define IFX_PMU_MODULE_PCIE0_CTRL IFX_PMU_MODULE_PCIE_CTRL ++ ++/*! \def IFX_PMU_MODULE_AHB_ARC ++ \brief AHB ARC module ++ */ ++#define IFX_PMU_MODULE_AHB_ARC (34) /* XXX */ ++ ++/*! \def IFX_PMU_MODULE_PCIE1_CTRL ++ \brief PCIe Controller 1 module ++ */ ++#define IFX_PMU_MODULE_PCIE1_CTRL IFX_PMU_MODULE_AHB_ARC ++ ++/*! \def IFX_PMU_MODULE_HSNAND ++ \brief High Speed NAND module ++ */ ++#define IFX_PMU_MODULE_HSNAND (35) /* XXX */ ++ ++/*! \def IFX_PMU_MODULE_PDI1 ++ \brief PCIe PDI 1 module ++ */ ++#define IFX_PMU_MODULE_PDI1 IFX_PMU_MODULE_HSNAND ++ ++ ++/*! \def IFX_PMU_MODULE_PDI ++ \brief PDI module ++ */ ++#define IFX_PMU_MODULE_PDI (36) ++ ++/*! \def IFX_PMU_MODULE_PDI0 ++ \brief PCIe PDI module ++ */ ++#define IFX_PMU_MODULE_PDI0 IFX_PMU_MODULE_PDI ++ ++/*! \def IFX_PMU_MODULE_MSI ++ \brief PCIe MSI module ++ */ ++#define IFX_PMU_MODULE_MSI (37) ++ ++/*! \def IFX_PMU_MODULE_MSI0 ++ \brief PCIe MSI 0 module ++ */ ++#define IFX_PMU_MODULE_MSI0 IFX_PMU_MODULE_MSI ++ ++/*! \def IFX_PMU_MODULE_DDR_CKE ++ \brief DDR CKE module ++ */ ++#define IFX_PMU_MODULE_DDR_CKE (38) ++ ++ ++/*! \def IFX_PMU_MODULE_MSI1 ++ \brief PCIe MSI 1 module ++ */ ++#define IFX_PMU_MODULE_MSI1 (39) ++ ++/* Will be exported to user space, __ prefix is used, see linux/types.h */ ++typedef struct ifx_pmu_clk { ++ __u32 module; /* Clok module index */ ++ __u32 enable; /* enable or disable */ ++} ifx_pmu_clk_t; ++ ++/* Used by ioctl */ ++#define IFX_PMU_IOC_MAGIC 0xe0 ++ ++#define IFX_PMU_IOC_CLK_ENABLE (1) ++#define IFX_PMU_IOC_CLK_DISABLE (2) ++#define IFX_PMU_IOC_CLK_GET (3) ++ ++#define IFX_PMU_IOC_CLK_GATING_ENABLE _IOW(IFX_PMU_IOC_MAGIC, IFX_PMU_IOC_CLK_ENABLE ,ifx_pmu_clk_t) ++#define IFX_PMU_IOC_CLK_GATING_DISABLE _IOW(IFX_PMU_IOC_MAGIC, IFX_PMU_IOC_CLK_DISABLE ,ifx_pmu_clk_t) ++#define IFX_PMU_IOC_GET_CLK_GATING _IOR(IFX_PMU_IOC_MAGIC, IFX_PMU_IOC_CLK_GET ,ifx_pmu_clk_t) ++ ++ ++#ifdef CONFIG_IFX_PMU_POWER_GATING ++ ++/* ++ * Power Gating Power domain Index definition ++ * The underlying power domain continues to evolve and change. To maintain the ++ * forward compatibiblity with future hardware platforms. Index is better. ++ * However, every new platform has to maintain one index-to-power domain table. ++ */ ++ ++/*! \def IFX_PMU_PG_DOMAIN_USB ++ \brief USB power domain ++ */ ++#define IFX_PMU_PG_DOMAIN_USB 0 ++ ++/*! \def IFX_PMU_PG_DOMAIN_PCIE ++ \brief PCI express power domain ++ */ ++#define IFX_PMU_PG_DOMAIN_PCIE 1 ++ ++/*! \def IFX_PMU_PG_DOMAIN_PCIE ++ \brief SLIC plus TDM power domain ++ */ ++#define IFX_PMU_PG_DOMAIN_SLIC_TDM 2 ++ ++/*! \def IFX_PMU_PG_DOMAIN_DEU ++ \brief DEU power domain ++ */ ++#define IFX_PMU_PG_DOMAIN_DEU 3 ++ ++/*! \def IFX_PMU_PG_DOMAIN_FPI_TOP ++ \brief FPI Top power domain ++ */ ++#define IFX_PMU_PG_DOMAIN_FPI_TOP 4 ++ ++/*! \def IFX_PMU_PG_DOMAIN_PPE ++ \brief PPE power domain ++ */ ++#define IFX_PMU_PG_DOMAIN_PPE 5 ++ ++/*! \def IFX_PMU_PG_DOMAIN_SWITCH ++ \brief Switch power domain ++ */ ++#define IFX_PMU_PG_DOMAIN_SWITCH 6 ++ ++/*! \def IFX_PMU_PG_DOMAIN_MIPS ++ \brief MIPS Core power domain ++ */ ++#define IFX_PMU_PG_DOMAIN_MIPS 7 ++ ++/*! \def IFX_PMU_PG_DOMAIN_DSL_DFE ++ \brief DSL DFE power domain ++ */ ++#define IFX_PMU_PG_DOMAIN_DSL_DFE 8 ++ ++/*! \def IFX_PMU_PG_DOMAIN_WLAN ++ \brief Built-in WiFi power domain ++ */ ++#define IFX_PMU_PG_DOMAIN_WLAN 9 ++ ++/*! \def IFX_PMU_PG_DOMAIN_GPHY0 ++ \brief Giga bit PHY0 power domain ++ */ ++#define IFX_PMU_PG_DOMAIN_GPHY0 10 ++ ++/*! \def IFX_PMU_PG_DOMAIN_GPHY1 ++ \brief Giga bit PHY1 power domain ++ */ ++#define IFX_PMU_PG_DOMAIN_GPHY1 11 ++ ++/*! \def IFX_PMU_PG_DOMAIN_GPHY2 ++ \brief Giga bit PHY2 power domain ++ */ ++#define IFX_PMU_PG_DOMAIN_GPHY2 12 ++ ++#define IFX_PMU_PG_DOMAIN_RES0 13 ++#define IFX_PMU_PG_DOMAIN_RES1 14 ++#define IFX_PMU_PG_DOMAIN_RES2 15 ++ ++/* XXX, more definition */ ++ ++#define IFX_POWER_DOMAIN(X) IFX_PMU_PG_DOMAIN_##X ++ ++/* Will be exported to user space, __ prefix is used, see linux/types.h */ ++typedef struct ifx_pmu_pg { ++ __u32 power_domain; /* Power Domain index */ ++ __u32 flags; /* Future use */ ++} ifx_pmu_pg_t; ++ ++ ++/* XXX, don't overlap with Clock Gating */ ++#define IFX_PMU_IOC_PG_ENABLE (60) ++#define IFX_PMU_IOC_PG_DISABLE (61) ++#define IFX_PMU_IOC_PG_GET (62) ++ ++#define IFX_PMU_IOC_POWER_GATING_ENABLE _IOW(IFX_PMU_IOC_MAGIC, IFX_PMU_IOC_PG_ENABLE ,ifx_pmu_pg_t) ++#define IFX_PMU_IOC_POWER_GATING_DISABLE _IOW(IFX_PMU_IOC_MAGIC, IFX_PMU_IOC_PG_DISABLE ,ifx_pmu_pg_t) ++#define IFX_PMU_IOC_GET_POWER_GATING _IOR(IFX_PMU_IOC_MAGIC, IFX_PMU_IOC_PG_GET ,ifx_pmu_pg_t) ++ ++#endif /* CONFIG_IFX_PMU_POWER_GATING */ ++/* @} */ ++ ++#ifdef __KERNEL__ ++ ++#define IFX_PMU_ENABLE 1 ++#define IFX_PMU_DISABLE 0 ++ ++#define USB0_PHY_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_USB0_PHY, (__x)) ++#define USB_PHY_PMU_SETUP(__x) USB0_PHY_PMU_SETUP((__x)) ++#define FPIS_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_FPIS, (__x)) ++#define FPI1_PMU_SETUP(__x) FPIS_PMU_SETUP((__x)) ++#define FPI2_PMU_SETUP(__x) FPIS_PMU_SETUP((__x)) ++#define DFEV0_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_DFEV0, (__x)) ++#ifdef CONFIG_AMAZON_SE ++#define SDIO_PMU_SETUP(__x) DFEV0_PMU_SETUP((__x)) ++#endif ++#define DFEV1_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_DFEV1, (__x)) ++#define VO_MIPS_PMU_SETUP(__x) DFEV0_PMU_SETUP((__x)) ++#define VODEC_PMU_SETUP(__x) DFEV1_PMU_SETUP((__x)) ++#define PCI_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PCI, (__x)) ++#define DMA_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_DMA, (__x)) ++#define USB0_CTRL_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_USB0_CTRL, (__x)) ++#define USIF_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_USIF, (__x)) ++#define UART0_PMU_SETUP(__x) USIF_PMU_SETUP((__x)) ++#define EPHY_PMU_SETUP(__x) USIF_PMU_SETUP((__x)) ++#define SPI_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_SPI, (__x)) ++#define DSL_DFE_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_DSL_DFE, (__x)) ++#define EBU_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_EBU, (__x)) ++#define LEDC_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_LEDC, (__x)) ++#define GPTC_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_GPTC, (__x)) ++ ++#define AHBS_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_AHBS, (__x)) ++#define VLYNQ_PMU_SETUP(__x) AHBS_PMU_SETUP((__x)) ++#define PPE_TPE_PMU_SETUP(__x) AHBS_PMU_SETUP((__x)) ++#define PCIE1_PHY_PMU_SETUP(__x) AHBS_PMU_SETUP((__x)) ++ ++#define FPIM_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_FPIM, (__x)) ++#define FPI0_PMU_SETUP(__x) FPIM_PMU_SETUP((__x)) ++#define ADSL_AFE_PMU_SETUP(__x) FPIM_PMU_SETUP((__x)) ++ ++#define AHBM_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_AHBM, (__x)) ++#define AHB_PMU_SETUP(__x) AHBM_PMU_SETUP((__x)) ++#define DCDC_2V5_PMU_SETUP(__x) AHBM_PMU_SETUP((__x)) ++ ++#ifndef CONFIG_AMAZON_SE ++#define SDIO_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_SDIO, (__x)) ++#endif ++#define UART1_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_UART1, (__x)) ++#define PPE_QSB_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_QSB, (__x)) ++#define WDT0_PMU_SETUP(__x) PPE_QSB_PMU_SETUP((__x)) ++#define DCDC_1VX_PMU_SETUP(__x) PPE_QSB_PMU_SETUP((__x)) ++ ++#define PPE_SLL01_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_SLL01, (__x)) ++#define DCDC_1V0_PMU_SETUP(__x) PPE_SLL01_PMU_SETUP((__x)) ++ ++#define WDT1_PMU_SETUP(__x) PPE_SLL01_PMU_SETUP((__x)) ++#define DEU_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_DEU, (__x)) ++#define PPE_TC_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_TC, (__x)) ++#define PPE_EMA_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_EMA, (__x)) ++#define PPE_ENET1_PMU_SETUP(__x) PPE_EMA_PMU_SETUP((__x)) ++#define PPE_DPLUSM_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_DPLUSM, (__x)) ++#define PPE_DPLUS_PMU_SETUP(__x) PPE_DPLUSM_PMU_SETUP((__x)) ++#define PPE_ENET0_PMU_SETUP(__x) PPE_DPLUS_PMU_SETUP((__x)) ++#define PPE_DPLUSS_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_DPLUSS, (__x)) ++#define DDR_MEM_PMU_SETUP(__x) PPE_DPLUSS_PMU_SETUP((__x)) ++#define TDM_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_TDM, (__x)) ++#define USB1_PHY_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_USB1_PHY, (__x)) ++#define USB1_CTRL_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_USB1_CTRL, (__x)) ++#define SWITCH_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_SWITCH, (__x)) ++ ++#define PPE_TOP_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_TOP, (__x)) ++#define GPHY0_PMU_SETUP(__x) PPE_TOP_PMU_SETUP((__x)) ++#define DDR_DPD_PMU_SETUP(__x) PPE_TOP_PMU_SETUP((__x)) ++ ++#define GPHY_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_GPHY, (__x)) ++#define GPHY1_PMU_SETUP(__x) GPHY_PMU_SETUP((__x)) ++ ++#define PCIE_L0_CLK_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PCIE_L0_CLK, (__x)) ++#define GPHY2_PMU_SETUP(__x) PCIE_L0_CLK_PMU_SETUP((__x)) ++ ++#define PCIE_PHY_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PCIE_PHY, (__x)) ++#define PCIE0_PHY_PMU_SETUP(__x) PCIE_PHY_PMU_SETUP((__x)) ++ ++#define PCIE_CTRL_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PCIE_CTRL, (__x)) ++#define PCIE0_CTRL_PMU_SETUP(__x) PCIE_CTRL_PMU_SETUP((__x)) ++ ++#define AHB_ARC_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_AHB_ARC, (__x)) ++#define PCIE1_CTRL_PMU_SETUP(__x) AHB_ARC_PMU_SETUP((__x)) ++ ++#define HSNAND_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_HSNAND, (__x)) ++#define PDI1_PMU_SETUP(__x) HSNAND_PMU_SETUP((__x)) ++ ++#define PDI_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PDI, (__x)) ++#define PDI0_PMU_SETUP(__x) PDI_PMU_SETUP((__x)) ++ ++#define MSI_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_MSI, (__x)) ++#define MSI0_PMU_SETUP(__x) MSI_PMU_SETUP((__x)) ++ ++#define DDR_CKE_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_DDR_CKE, (__x)) ++ ++#define MSI1_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_MSI1, (__x)) ++ ++#ifndef ifx_pmu_set ++extern int ifx_pmu_set(int module, int value); ++#endif ++extern void ifx_pmu_enable_all_modules(void); ++extern void ifx_pmu_disable_all_modules(void); ++#ifdef CONFIG_IFX_PMU_POWER_GATING ++extern int ifx_pmu_pg_enable(ifx_pmu_pg_t *pg); ++extern void ifx_pmu_pg_enable_all_domains(void); ++extern void ifx_pmu_pg_disable_all_domains(void); ++extern int ifx_pmu_pg_disable(ifx_pmu_pg_t *pg); ++extern int ifx_pmu_pg_mips_enable(void); ++extern int ifx_pmu_pg_mips_disable(void); ++extern int ifx_pmu_pg_usb_enable(void); ++extern int ifx_pmu_pg_usb_disable(void); ++extern int ifx_pmu_pg_pcie_enable(void); ++extern int ifx_pmu_pg_pcie_disable(void); ++extern int ifx_pmu_pg_switch_enable(void); ++extern int ifx_pmu_pg_switch_disable(void); ++extern int ifx_pmu_pg_deu_enable(void); ++extern int ifx_pmu_pg_deu_disable(void); ++extern int ifx_pmu_pg_ppe_enable(void); ++extern int ifx_pmu_pg_ppe_disable(void); ++extern int ifx_pmu_pg_dsl_dfe_enable(void); ++extern int ifx_pmu_pg_dsl_dfe_disable(void); ++extern int ifx_pmu_pg_fpi_top_enable(void); ++extern int ifx_pmu_pg_fpi_top_disable(void); ++extern int ifx_pmu_pg_slic_tdm_enable(void); ++extern int ifx_pmu_pg_slic_tdm_disable(void); ++extern int ifx_pmu_pg_wkup_loc_setup(void *loc); ++#else ++static inline void ifx_pmu_pg_enable_all_domains(void) ++{ ++} ++ ++static inline void ifx_pmu_pg_disable_all_domains(void) ++{ ++} ++ ++static inline int ifx_pmu_pg_mips_enable(void) ++{ ++ return 0; ++} ++ ++static inline int ifx_pmu_pg_mips_disable(void) ++{ ++ return 0; ++} ++ ++static inline int ifx_pmu_pg_usb_enable(void) ++{ ++ return 0; ++} ++ ++static inline int ifx_pmu_pg_usb_disable(void) ++{ ++ return 0; ++} ++ ++static inline int ifx_pmu_pg_pcie_enable(void) ++{ ++ return 0; ++ ++} ++ ++static inline int ifx_pmu_pg_pcie_disable(void) ++{ ++ return 0; ++} ++ ++static inline int ifx_pmu_pg_switch_enable(void) ++{ ++ return 0; ++} ++ ++static inline int ifx_pmu_pg_switch_disable(void) ++{ ++ return 0; ++} ++ ++static inline int ifx_pmu_pg_deu_enable(void) ++{ ++ return 0; ++} ++ ++static inline int ifx_pmu_pg_deu_disable(void) ++{ ++ return 0; ++} ++ ++static inline int ifx_pmu_pg_ppe_enable(void) ++{ ++ return 0; ++} ++ ++static inline int ifx_pmu_pg_ppe_disable(void) ++{ ++ return 0; ++} ++ ++static inline int ifx_pmu_pg_dsl_dfe_enable(void) ++{ ++ return 0; ++} ++ ++static inline int ifx_pmu_pg_dsl_dfe_disable(void) ++{ ++ return 0; ++} ++ ++static inline int ifx_pmu_pg_fpi_top_enable(void) ++{ ++ return 0; ++} ++ ++static inline int ifx_pmu_pg_fpi_top_disable(void) ++{ ++ return 0; ++} ++ ++static inline int ifx_pmu_pg_slic_tdm_enable(void) ++{ ++ return 0; ++} ++ ++static inline int ifx_pmu_pg_slic_tdm_disable(void) ++{ ++ return 0; ++} ++ ++static inline int ifx_pmu_pg_wkup_loc_setup(void *loc) ++{ ++ return 0; ++} ++#endif /* CONFIG_IFX_PMU_POWER_GATING */ ++ ++#endif /* __KERNEL__ */ ++#endif /* IFX_PMU_H */ ++ +diff --git a/arch/mips/include/asm/ifx/ifx_ptm.h b/arch/mips/include/asm/ifx/ifx_ptm.h +new file mode 100644 +index 0000000..698e5c3 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_ptm.h +@@ -0,0 +1,203 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_ptm.h ++** PROJECT : UEIP ++** MODULES : PTM ++** ++** DATE : 17 Jun 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : Global PTM driver header file ++** COPYRIGHT : Copyright (c) 2006 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 07 JUL 2009 Xu Liang Init Version ++*******************************************************************************/ ++ ++#ifndef IFX_PTM_H ++#define IFX_PTM_H ++ ++ ++ ++/*! ++ \defgroup IFX_PTM UEIP Project - PTM driver module ++ \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9. ++ */ ++ ++/*! ++ \defgroup IFX_PTM_IOCTL IOCTL Commands ++ \ingroup IFX_PTM ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_PTM_STRUCT Structures ++ \ingroup IFX_PTM ++ \brief Structures used by user application. ++ */ ++ ++/*! ++ \file ifx_ptm.h ++ \ingroup IFX_PTM ++ \brief PTM driver header file ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * IOCTL ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_PTM_IOCTL ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Command ++ */ ++/*! ++ \brief PTM IOCTL Command - Get codeword MIB counters. ++ ++ This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters. ++ */ ++#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1 ++/*! ++ \brief PTM IOCTL Command - Get packet MIB counters. ++ ++ This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters. ++ */ ++#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2 ++/*! ++ \brief PTM IOCTL Command - Get firmware configuration (CRC). ++ ++ This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC). ++ */ ++#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3 ++/*! ++ \brief PTM IOCTL Command - Set firmware configuration (CRC). ++ ++ This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC). ++ */ ++#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4 ++/*! ++ \brief PTM IOCTL Command - Program priority value to TX queue mapping. ++ ++ This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping. ++ */ ++#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14 ++ ++/*@}*/ ++ ++ ++/*! ++ \addtogroup IFX_PTM_STRUCT ++ */ ++/*@{*/ ++ ++/* ++ * ioctl Data Type ++ */ ++ ++/*! ++ \typedef PTM_CW_IF_ENTRY_T ++ \brief Wrapping of structure "ptm_cw_ifEntry_t". ++ */ ++/*! ++ \struct ptm_cw_ifEntry_t ++ \brief Structure used for CodeWord level MIB counters. ++ */ ++typedef struct ptm_cw_ifEntry_t { ++ uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */ ++ uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */ ++ uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */ ++ uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */ ++ uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */ ++} PTM_CW_IF_ENTRY_T; ++ ++/*! ++ \typedef PTM_FRAME_MIB_T ++ \brief Wrapping of structure "ptm_frame_mib_t". ++ */ ++/*! ++ \struct ptm_frame_mib_t ++ \brief Structure used for packet level MIB counters. ++ */ ++typedef struct ptm_frame_mib_t { ++ uint32_t RxCorrect; /*!< output, number of ingress packet */ ++ uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */ ++ uint32_t RxDropped; /*!< output, number of dropped ingress packet */ ++ uint32_t TxSend; /*!< output, number of egress packet */ ++} PTM_FRAME_MIB_T; ++ ++/*! ++ \typedef IFX_PTM_CFG_T ++ \brief Wrapping of structure "ptm_cfg_t". ++ */ ++/*! ++ \struct ptm_cfg_t ++ \brief Structure used for ETH/TC CRC configuration. ++ */ ++typedef struct ptm_cfg_t { ++ uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */ ++ uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */ ++ uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */ ++ uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */ ++ uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */ ++ uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */ ++ uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */ ++} IFX_PTM_CFG_T; ++ ++/*! ++ \typedef IFX_PTM_PRIO_Q_MAP_T ++ \brief Wrapping of structure "ppe_prio_q_map". ++ */ ++/*! ++ \struct ppe_prio_q_map ++ \brief Structure used for Priority Value to TX Queue mapping. ++ */ ++typedef struct ppe_prio_q_map { ++ int pkt_prio; ++ int qid; ++ int vpi; // ignored in eth interface ++ int vci; // ignored in eth interface ++} IFX_PTM_PRIO_Q_MAP_T; ++ ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * API ++ * #################################### ++ */ ++ ++#ifdef __KERNEL__ ++struct port_cell_info { ++ unsigned int port_num; ++ unsigned int tx_link_rate[2]; ++}; ++#endif ++ ++ ++ ++#endif // IFX_PTM_H ++ +diff --git a/arch/mips/include/asm/ifx/ifx_rcu.h b/arch/mips/include/asm/ifx/ifx_rcu.h +new file mode 100644 +index 0000000..d2dbafd +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_rcu.h +@@ -0,0 +1,298 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_rcu.h ++** PROJECT : UEIP ++** MODULES : RCU (Reset Control Unit) ++** ++** DATE : 17 Jun 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : Global RCU driver header file ++** COPYRIGHT : Copyright (c) 2006 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 17 JUN 2009 Xu Liang Init Version ++*******************************************************************************/ ++ ++#ifndef IFX_RCU_H ++#define IFX_RCU_H ++ ++ ++ ++/*! ++ \defgroup IFX_RCU UEIP Project - RCU (Reset) driver module ++ \brief UEIP Project - RCU (Reset) driver module, support Danube, Amazon-SE, AR9, VR9. ++ */ ++ ++/*! ++ \defgroup IFX_RCU_API APIs ++ \ingroup IFX_RCU ++ \brief APIs used by other drivers/modules. ++ */ ++ ++/*! ++ \defgroup IFX_RCU_IOCTL IOCTL Commands ++ \ingroup IFX_RCU ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_RCU_STRUCT Structures ++ \ingroup IFX_RCU ++ \brief Structures used by user application. ++ */ ++ ++/*! ++ \file ifx_rcu.h ++ \ingroup IFX_RCU ++ \brief RCU driver header file ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++#if defined(CONFIG_HN1) ++ ++enum { ++ IFX_RCU_DOMAIN_HRST = 0, // HRST output (0: RD0) ++ IFX_RCU_DOMAIN_CPU0, // Main CPU (1: RD1) ++ IFX_RCU_DOMAIN_FPI, // FPI bus (2: RD2) ++ IFX_RCU_DOMAIN_DLLCORE, // HN DLL Core (3: RD3) ++ IFX_RCU_DOMAIN_I2C, // I2C (4: RD4) ++ IFX_RCU_DOMAIN_AHB, // AHB bus (5: RD6) ++ IFX_RCU_DOMAIN_BULKSRAM, // BULK SRAM (6: RD7) ++ IFX_RCU_DOMAIN_I2S, // I2S module (7: RD8) ++ IFX_RCU_DOMAIN_DMA, // DMA module (8: RD9) ++ IFX_RCU_DOMAIN_SDIO, // SDIO module (9: RD10) ++ IFX_RCU_DOMAIN_PHYCORE, // PHY CORE (10:RD11) ++ IFX_RCU_DOMAIN_PCIEPHY, // PCIE PHY (12:RD12) ++ IFX_RCU_DOMAIN_MC, // Memory Controller module (13:RD14) ++ IFX_RCU_DOMAIN_HSNAND, // HSNAND (14:RD16) ++ IFX_RCU_DOMAIN_TDM, // TDM interface (Voice) (15:RD19) ++ IFX_RCU_DOMAIN_SW, // ETHERNET SWITCH (16:RD21) ++ IFX_RCU_DOMAIN_PCIE, // PCIE PART (17:RD22) ++ IFX_RCU_DOMAIN_AHBDLL, // AHB DLL (18:RD23) ++ IFX_RCU_DOMAIN_GPHY0, // GPHY0 (19: RD31) ++ // add more component in the future ++ IFX_RCU_DOMAIN_MAX, ++}; ++ ++#define IFX_RCU_DECLARE_DOMAIN_NAME(var) \ ++ char *var[] = { \ ++ "HRST", \ ++ "Main CPU", \ ++ "FPI bus", \ ++ "DLL Core", \ ++ "I2C", \ ++ "AHB bus", \ ++ "BULK SRAM", \ ++ "I2S", \ ++ "DMA", \ ++ "SDIO", \ ++ "PHY CORE", \ ++ "PCIE PHY", \ ++ "Memory Controller", \ ++ "High Speed NAND", \ ++ "TDM interface", \ ++ "Internal Switch", \ ++ "PCIE", \ ++ "AHB DLL", \ ++ "GPHY0", \ ++ } ++ ++#else ++ ++enum { ++ IFX_RCU_DOMAIN_HRST = 0, ++ IFX_RCU_DOMAIN_CPU0, // Main CPU ++ IFX_RCU_DOMAIN_FPI, // FPI bus ++ IFX_RCU_DOMAIN_DSLDSP, // DSL DSP ++ IFX_RCU_DOMAIN_USB1, // USB1 & PHY ++ IFX_RCU_DOMAIN_USB0, // USB0 & PHY ++ IFX_RCU_DOMAIN_ETHMAC1, // 2nd Ethernet MAC (Danube Only) ++ IFX_RCU_DOMAIN_AHB, // AHB bus ++ IFX_RCU_DOMAIN_DSLDFE, // DSL DFE ++ IFX_RCU_DOMAIN_PPE, // PPE module ++ IFX_RCU_DOMAIN_DMA, // DMA module ++ IFX_RCU_DOMAIN_SDIO, // SDIO module ++ IFX_RCU_DOMAIN_DSLAFE, // DSL AFE ++ IFX_RCU_DOMAIN_VOICE, // Voice DFE/AFE ++ IFX_RCU_DOMAIN_PCI, // PCI bus ++ IFX_RCU_DOMAIN_MC, // Memory Controller module ++ IFX_RCU_DOMAIN_SW, // Internal Switch ++ IFX_RCU_DOMAIN_TDM, // TDM interface (Voice) ++ IFX_RCU_DOMAIN_DSLTC, // (ATM) TC module in PPE ++ IFX_RCU_DOMAIN_CPU1, // 2nd CPU (Danube only) ++ IFX_RCU_DOMAIN_EPHY, // EPHY (Amazon-SE only) ++ IFX_RCU_DOMAIN_GPHY0, // GPHY0 (VR9 only) ++ IFX_RCU_DOMAIN_GPHY1, // GPHY1 (VR9 only) ++ IFX_RCU_DOMAIN_ARC, // ARC (DSL DSP) ++ IFX_RCU_DOMAIN_PCIE_PHY, // PCIexpress PHY (VR9 only) ++ IFX_RCU_DOMAIN_PCIE, // PCIexpress core (VR9 only) ++ IFX_RCU_DOMAIN_HSNAND, // High Speed NAND Flash Interface (VR9 only) ++ // add more component in the future ++ IFX_RCU_DOMAIN_MAX, ++}; ++ ++#define IFX_RCU_DECLARE_DOMAIN_NAME(var) \ ++ char *var[] = { \ ++ "HRST", \ ++ "Main CPU", \ ++ "FPI bus", \ ++ "DSL DSP", \ ++ "USB1 & PHY", \ ++ "USB0 & PHY", \ ++ "2nd MAC", \ ++ "AHB bus", \ ++ "DSL DFE", \ ++ "PPE", \ ++ "DMA", \ ++ "SDIO", \ ++ "DSL AFE", \ ++ "Voice DFE/AFE", \ ++ "PCI bus", \ ++ "Memory Controller", \ ++ "Internal Switch", \ ++ "TDM interface", \ ++ "DSL TC", \ ++ "2nd CPU", \ ++ "EPHY", \ ++ "GPHY0", \ ++ "GPHY1", \ ++ "ARC", \ ++ "PCIe PHY", \ ++ "PCIe core", \ ++ "High Speed NAND", \ ++ } ++ ++#endif ++ ++enum { ++ IFX_RCU_MODULE_USB, ++ IFX_RCU_MODULE_ETH, ++ IFX_RCU_MODULE_ATM, ++ IFX_RCU_MODULE_PTM, ++ IFX_RCU_MODULE_PPA, ++ IFX_RCU_MODULE_DMA, ++ IFX_RCU_MODULE_SDIO, ++ IFX_RCU_MODULE_MEI, ++ IFX_RCU_MODULE_TAPI, ++ IFX_RCU_MODULE_PCI, ++ IFX_RCU_MODULE_NAND, ++ // add more component in the future ++ IFX_RCU_MODULE_MAX, ++}; ++ ++#define IFX_RCU_DECLARE_MODULE_NAME(var) \ ++ char *var[] = { \ ++ "USB", \ ++ "ETH", \ ++ "ATM", \ ++ "PTM", \ ++ "PPA", \ ++ "DMA", \ ++ "SDIO", \ ++ "MEI", \ ++ "TAPI", \ ++ "PCI", \ ++ "NAND", \ ++ } ++ ++typedef int (*ifx_rcu_callbackfn)(unsigned int reset_domain_id, unsigned int module_id, int f_after_reset, unsigned long arg); ++ ++ ++ ++/* ++ * #################################### ++ * IOCTL ++ * #################################### ++ */ ++ ++/*! ++ \addtogroup IFX_RCU_STRUCT ++ */ ++/*@{*/ ++ ++/*! ++ \struct ifx_rcu_ioctl_version ++ \brief Structure used for query of driver version. ++ */ ++struct ifx_rcu_ioctl_version { ++ unsigned int major; /*!< output, major number of driver */ ++ unsigned int mid; /*!< output, mid number of driver */ ++ unsigned int minor; /*!< output, minor number of driver */ ++}; ++ ++/*! ++ \struct ifx_rcu_ioctl_query_rst_domain ++ \brief Structure used to get reset status of given hardware module. ++ */ ++struct ifx_rcu_ioctl_query_rst_domain { ++ unsigned int domain_id; /*!< input, hardware module ID */ ++ int f_reset; /*!< output, reset status */ ++}; ++ ++/*@}*/ ++ ++ ++/*! ++ \addtogroup IFX_RCU_IOCTL ++ */ ++/*@{*/ ++#define IFX_RCU_IOC_MAGIC 0xe0 ++/*! ++ \def IFX_RCU_IOC_VERSION ++ \brief RCU IOCTL Command - Get driver version number. ++ ++ This command uses struct "ifx_rcu_ioctl_version" as parameter to RCU driver version number. ++ */ ++#define IFX_RCU_IOC_VERSION _IOR( IFX_RCU_IOC_MAGIC, 0, struct ifx_rcu_ioctl_version) ++/*! ++ \def IFX_RCU_IOC_QUERY_RST_DOMAIN ++ \brief RCU IOCTL Command - Get reset status of given hardware module. ++ ++ This command uses struct "ifx_rcu_ioctl_query_rst_domain" as parameter to get reset status of given hardware module. ++ */ ++#define IFX_RCU_IOC_QUERY_RST_DOMAIN _IOWR(IFX_RCU_IOC_MAGIC, 1, struct ifx_rcu_ioctl_query_rst_domain) ++/*@}*/ ++ ++ ++ ++/* ++ * #################################### ++ * API ++ * #################################### ++ */ ++ ++#ifdef __KERNEL__ ++ /* ++ * RST_REQ/RST_STAT Register Access ++ * For accessing to special bits in these two registers, such as fusing, endianess ++ */ ++ unsigned int ifx_rcu_rst_req_read(void); ++ void ifx_rcu_rst_req_write(unsigned int value, unsigned int mask); ++ unsigned int ifx_rcu_rst_stat_read(void); ++ /* ++ * Reset Operation ++ */ ++ int ifx_rcu_request(unsigned int reset_domain_id, unsigned int module_id, ifx_rcu_callbackfn callbackfn, unsigned long arg); ++ int ifx_rcu_free(unsigned int reset_domain_id, unsigned int module_id); ++ int ifx_rcu_stat_get(unsigned int reset_domain_id); ++ int ifx_rcu_rst(unsigned int reset_domain_id, unsigned int module_id); ++#endif ++ ++ ++ ++#endif // IFX_RCU_H +diff --git a/arch/mips/include/asm/ifx/ifx_regs.h b/arch/mips/include/asm/ifx/ifx_regs.h +new file mode 100644 +index 0000000..678bfc3 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_regs.h +@@ -0,0 +1,262 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_regs.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : common header file ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef IFX_CHIP_REGS_H ++#define IFX_CHIP_REGS_H ++ ++#include ++ ++/* ++ * Register Operation ++ */ ++#define IFX_REG_R32(_r) __raw_readl((volatile unsigned int *)(_r)) ++#define IFX_REG_W32(_v, _r) __raw_writel((_v), (volatile unsigned int *)(_r)) ++#define IFX_REG_W32_MASK(_clr, _set, _r) IFX_REG_W32((IFX_REG_R32((_r)) & ~(_clr)) | (_set), (_r)) ++#define IFX_REG_R16(_r) __raw_readw((_r)) ++#define IFX_REG_W16(_v, _r) __raw_writew((_v), (_r)) ++#define IFX_REG_W16_MASK(_clr, _set, _r) IFX_REG_W16((IFX_REG_R16((_r)) & ~(_clr)) | (_set), (_r)) ++#define IFX_REG_R8(_r) __raw_readb((_r)) ++#define IFX_REG_W8(_v, _r) __raw_writeb((_v), (_r)) ++#define IFX_REG_W8_MASK(_clr, _set, _r) IFX_REG_W8((IFX_REG_R8((_r)) & ~(_clr)) | (_set), (_r)) ++ ++/* ++ * Register manipulation macros that expect bit field defines ++ * to follow the convention that an _S suffix is appended for ++ * a shift count, while the field mask has no suffix. Or can use ++ * _M as suffix ++ */ ++ ++/* Shift first, then mask, usually for write operation */ ++#define SM(_v, _f) (((_v) << _f##_S) & (_f)) ++ ++/* Mask first , then shift, usually for read operation */ ++#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) ++ ++#define IFX_REG_RMW32(_set, _clr, _r) \ ++ IFX_REG_W32((IFX_REG_R32((_r)) & ~(_clr)) | (_set), (_r)) ++ ++#define IFX_REG_RMW32_FILED(_f, _v, _r) \ ++ IFX_REG_W32(\ ++ (IFX_REG_R32((_r)) &~ (_f)) | (((_v) << (_f##_S)) & (_f)), (_r)) ++ ++#define IFX_REG_SET_BIT(_f, _r) \ ++ IFX_REG_W32((IFX_REG_R32((_r)) &~ (_f)) | (_f), (_r)) ++ ++#define IFX_REG_CLR_BIT(_f, _r) \ ++ IFX_REG_W32(IFX_REG_R32((_r)) &~ (_f), (_r)) ++ ++#define IFX_REG_IS_BIT_SET(_f, _r) \ ++ ((IFX_REG_R32((_r)) & (_f)) != 0) ++ ++/* ++ * Bits Operation ++ */ ++#define GET_BITS(x, msb, lsb) \ ++ (((x) >> (lsb)) & ((1 << ((msb) + 1 - (lsb))) - 1)) ++#define SET_BITS(x, msb, lsb, value) \ ++ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) ++ ++#if defined(CONFIG_DANUBE) ++#include "danube/danube.h" ++#elif defined(CONFIG_AMAZON_SE) ++#include "amazon_se/amazon_se.h" ++#elif defined(CONFIG_AR9) ++#include "ar9/ar9.h" ++#elif defined(CONFIG_VR9) ++#include "vr9/vr9.h" ++#elif defined(CONFIG_AR10) ++#include "ar10/ar10.h" ++#elif defined(CONFIG_HN1) ++#include "hn1/hn1.h" ++#else ++#error unknown chip ++#endif ++#include "ifx_board.h" ++ ++/* ++ * Chip ID ++ */ ++typedef struct { ++#define IFX_FAMILY_UNKNOWN 0 ++#define IFX_FAMILY_DANUBE 1 ++#define IFX_FAMILY_TWINPASS IFX_FAMILY_DANUBE ++#define IFX_FAMILY_AMAZON_SE 2 ++#define IFX_FAMILY_ASE IFX_FAMILY_AMAZON_SE ++#define IFX_FAMILY_AR9 3 ++#define IFX_FAMILY_xRX100 IFX_FAMILY_AR9 ++#define IFX_FAMILY_VR9 4 ++#define IFX_FAMILY_xRX200 IFX_FAMILY_VR9 ++#define IFX_FAMILY_AR10 5 ++#define IFX_FAMILY_xRX300 IFX_FAMILY_AR10 ++ unsigned int family_id; ++#define IFX_FAMILY_DANUBE_A1x 1 ++#define IFX_FAMILY_TWINPASS_A1x IFX_FAMILY_DANUBE_A1x ++#define IFX_FAMILY_AMAZON_SE_A1x 1 ++#define IFX_FAMILY_ASE_A1x IFX_FAMILY_AMAZON_SE_A1x ++#define IFX_FAMILY_AR9_A1x 1 ++#define IFX_FAMILY_xRX100_A1x IFX_FAMILY_AR9_A1x ++#define IFX_FAMILY_VR9_A1x 1 ++#define IFX_FAMILY_xRX200_A1x IFX_FAMILY_VR9_A1x ++#define IFX_FAMILY_VR9_A2x 2 ++#define IFX_FAMILY_xRX200_A2x IFX_FAMILY_VR9_A2x ++#define IFX_FAMILY_AR10_A1x 1 ++#define IFX_FAMILY_xRX300_A1x IFX_FAMILY_AR10_A1x ++ unsigned int family_ver; ++#define IFX_PARTNUM_DANUBE 0x00EB ++#define IFX_PARTNUM_DANUBE_S 0x00ED ++#define IFX_PARTNUM_AMAZON_S 0x00EF ++#define IFX_PARTNUM_VINAX_VE 0x013C ++#define IFX_PARTNUM_VINAX_E 0x0151 ++#define IFX_PARTNUM_AMAZON_SE_50601 0x0152 ++#define IFX_PARTNUM_AMAZON_SE_50600 0x0153 ++#define IFX_PARTNUM_ARX188 0x016C ++#define IFX_PARTNUM_ARX168 0x016D ++#define IFX_PARTNUM_GRX188 0x0170 ++#define IFX_PARTNUM_GRX168 0x0171 ++#define IFX_PARTNUM_VRX288_A1x 0x01C0 ++#define IFX_PARTNUM_VRX282_A1x 0x01C1 ++#define IFX_PARTNUM_VRX268_A1x 0x01C2 ++#define IFX_PARTNUM_GRX288_A1x 0x01C9 ++#define IFX_PARTNUM_GRX268_A1x 0x01C8 ++#define IFX_PARTNUM_VRX288_A2x 0x000B ++#define IFX_PARTNUM_VRX282_A2x 0x000E ++#define IFX_PARTNUM_VRX268_A2x 0x000C ++#define IFX_PARTNUM_GRX288_A2x 0x000D ++#define IFX_PARTNUM_ARX361 0x0003 // 1x1 Router ++#define IFX_PARTNUM_ARX362 0x0004 // 2x2 Router ++#define IFX_PARTNUM_ARX363 0x0005 // 3x3 Router ++#define IFX_PARTNUM_ARX381 0x0006 // 1x1 Gateway ++#define IFX_PARTNUM_ARX382 0x0007 // 2x2 Gateway ++#define IFX_PARTNUM_ARX383 0x0008 // 3x3 Gateway ++#define IFX_PARTNUM_GRX388 0x0009 // 3x3 Ethernet Router/Gateway ++#define IFX_PARTNUM_ARX368 0x000A // 3x3 High-end Router ++#define IFX_PARTNUM_ARX388 0x000B // 3x3 High-end Gateway ++ unsigned int part_number; ++ unsigned int chip_version; ++ unsigned int manufacturer_id; ++} ifx_chipid_t; ++static inline unsigned int ifx_get_chipid(ifx_chipid_t *p_chipid) ++{ ++ unsigned int chipid; ++ ++ chipid = IFX_REG_R32(IFX_MPS_CHIPID); ++ ++ if ( p_chipid == NULL ) ++ return chipid; ++ ++ p_chipid->part_number = GET_BITS(chipid, 27, 12); ++ p_chipid->chip_version = GET_BITS(chipid, 30, 28); ++ p_chipid->manufacturer_id = GET_BITS(chipid, 11, 1); ++ ++ switch ( p_chipid->part_number ) { ++ case IFX_PARTNUM_DANUBE: ++ case IFX_PARTNUM_DANUBE_S: ++ case IFX_PARTNUM_AMAZON_S: ++ p_chipid->family_id = IFX_FAMILY_DANUBE; ++ p_chipid->family_ver = IFX_FAMILY_DANUBE_A1x; ++ break; ++ case IFX_PARTNUM_VINAX_VE: ++ case IFX_PARTNUM_VINAX_E: ++ p_chipid->family_id = IFX_FAMILY_TWINPASS; ++ p_chipid->family_ver = IFX_FAMILY_DANUBE_A1x; ++ break; ++ case IFX_PARTNUM_AMAZON_SE_50601: ++ case IFX_PARTNUM_AMAZON_SE_50600: ++ p_chipid->family_id = IFX_FAMILY_AMAZON_SE; ++ p_chipid->family_ver = IFX_FAMILY_AMAZON_SE_A1x; ++ break; ++ case IFX_PARTNUM_ARX188: ++ case IFX_PARTNUM_ARX168: ++ case IFX_PARTNUM_GRX188: ++ case IFX_PARTNUM_GRX168: ++ p_chipid->family_id = IFX_FAMILY_xRX100; ++ p_chipid->family_ver = IFX_FAMILY_xRX100_A1x; ++ break; ++ case IFX_PARTNUM_VRX288_A1x: ++ case IFX_PARTNUM_VRX282_A1x: ++ case IFX_PARTNUM_VRX268_A1x: ++ case IFX_PARTNUM_GRX288_A1x: ++ case IFX_PARTNUM_GRX268_A1x: ++ p_chipid->family_id = IFX_FAMILY_xRX200; ++ p_chipid->family_ver = IFX_FAMILY_xRX200_A1x; ++ break; ++ case IFX_PARTNUM_VRX288_A2x: ++ case IFX_PARTNUM_VRX282_A2x: ++ case IFX_PARTNUM_VRX268_A2x: ++ case IFX_PARTNUM_GRX288_A2x: ++ p_chipid->family_id = IFX_FAMILY_xRX200; ++ p_chipid->family_ver = IFX_FAMILY_xRX200_A2x; ++ break; ++ case IFX_PARTNUM_ARX361: ++ case IFX_PARTNUM_ARX362: ++ case IFX_PARTNUM_ARX363: ++ case IFX_PARTNUM_ARX381: ++ case IFX_PARTNUM_ARX382: ++ case IFX_PARTNUM_ARX383: ++ case IFX_PARTNUM_GRX388: ++ case IFX_PARTNUM_ARX368: ++// case IFX_PARTNUM_ARX388: // conflict with VR9 ++ p_chipid->family_id = IFX_FAMILY_xRX300; ++ p_chipid->family_ver = IFX_FAMILY_xRX300_A1x; ++ break; ++ default: ++ p_chipid->family_id = IFX_FAMILY_UNKNOWN; ++ } ++ ++ return chipid; ++} ++ ++/* ++ * Clock ++ */ ++#define CLOCK_25M 25000000 ++#define CLOCK_48M 48000000 ++#define CLOCK_60M 60000000 ++#define CLOCK_62_5M 62500000 ++#define CLOCK_83M 83333333 ++#define CLOCK_83_5M 83500000 ++#define CLOCK_98_304M 98304000 ++#define CLOCK_100M 100000000 ++#define CLOCK_111M 111111111 ++#define CLOCK_125M 125000000 ++#define CLOCK_133M 133333333 ++#define CLOCK_150M 150000000 ++#define CLOCK_166M 166666666 ++#define CLOCK_167M 166666667 ++#define CLOCK_200M 200000000 ++#define CLOCK_196_608M 196608000 ++#define CLOCK_222M 222222222 ++#define CLOCK_250M 250000000 ++#define CLOCK_266M 266666666 ++#define CLOCK_300M 300000000 ++#define CLOCK_333M 333333333 ++#define CLOCK_393M 393215332 ++#define CLOCK_400M 400000000 ++#define CLOCK_500M 500000000 ++#define CLOCK_600M 600000000 ++#define CLOCK_1000M 1000000000 ++ ++#endif /* IFX_CHIP_REGS_H */ ++ +diff --git a/arch/mips/include/asm/ifx/ifx_si.h b/arch/mips/include/asm/ifx/ifx_si.h +new file mode 100644 +index 0000000..0afb8f6 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_si.h +@@ -0,0 +1,246 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_si.h ++** PROJECT : UEIP ++** MODULES : Serial In Controller ++** ++** DATE : 26 Apr 2010 ++** AUTHOR : Xu Liang ++** DESCRIPTION : Global Serial In Controller driver header file ++** COPYRIGHT : Copyright (c) 2006 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** Apr 26, 2010 Xu Liang Init Version ++*******************************************************************************/ ++ ++ ++ ++#ifndef IFX_SI_H ++#define IFX_SI_H ++ ++/*! ++ \defgroup IFX_SI UEIP Project - SI Controller driver module ++ \brief UEIP Project - Serial In Controller driver module, support AR9, VR9, AR10. ++ */ ++ ++/*! ++ \defgroup IFX_SI_API APIs ++ \ingroup IFX_SI ++ \brief APIs used by other drivers/modules. ++ */ ++ ++/*! ++ \defgroup IFX_SI_IOCTL IOCTL Commands ++ \ingroup IFX_SI ++ \brief IOCTL Commands used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_SI_STRUCT Structures ++ \ingroup IFX_SI ++ \brief Structures used by user application. ++ */ ++ ++/*! ++ \defgroup IFX_SI_ENUM Enumerated Types ++ \ingroup IFX_SI ++ \brief Enumerated types used by user application. ++ */ ++ ++/*! ++ \file ifx_si.h ++ \ingroup IFX_SI ++ \brief SI Controller (Serial In) driver header file ++ */ ++ ++ ++ ++/*! ++ \addtogroup IFX_SI_ENUM ++ */ ++/*@{*/ ++ ++/*! ++ \enum IFX_SI_UPD_SRC_t ++ \brief enum used to configure update source. ++ */ ++typedef enum { ++ IFX_SI_UPD_SRC_SW = 0, ++ IFX_SI_UPD_SRC_GPT3 = 1, ++ IFX_SI_UPD_SRC_FPID = 2, ++ IFX_SI_UPD_SRC_ERR = 3, // no such thing. HW Error. ++} IFX_SI_UPD_SRC_t; ++ ++/*! ++ \enum IFX_SI_SYNC_MODE_t ++ \brief enum used to select either sync mode or async mode. ++ */ ++typedef enum { ++ IFX_SI_ASYNC_MODE = 0, ++ IFX_SI_SYNC_MODE = 1, ++} IFX_SI_SYNC_MODE_t; ++ ++/*! ++ \enum IFX_SI_FPI_SAMPLECLK_DIV_t ++ \brief enum used to select between FPI CLK Division for setting read interval, ++ applicable only when update source = FPID. ++ */ ++typedef enum { ++ // FPID2[26:25] For Sampling Interval Clk ++ IFX_SI_FPI_SAMPLECLK_DIV_010 = 1, ++ IFX_SI_FPI_SAMPLECLK_DIV_040 = 2, ++ IFX_SI_FPI_SAMPLECLK_DIV_080 = 3, ++ IFX_SI_FPI_SAMPLECLK_DIV_160 = 0, ++} IFX_SI_FPI_SAMPLECLK_DIV_t; ++ ++/*! ++ \enum IFX_SI_GROUP_t ++ \brief enum used to select how many input signals are supported. ++ */ ++typedef enum { ++ IFX_SI_GROUP_00 = 0, ++ IFX_SI_GROUP_08 = 1, ++ IFX_SI_GROUP_16 = 3, ++} IFX_SI_GROUP_t; ++ ++/*! ++ \enum IFX_SI_FPI_SHIFTCLK_DIV_t ++ \brief enum used to configure shift-in clock. ++ */ ++typedef enum { ++ // FPID[1:0] For Serial Input Clk ++ IFX_SI_FPI_SHIFTCLK_DIV_002 = 0, ++ IFX_SI_FPI_SHIFTCLK_DIV_004 = 1, ++ IFX_SI_FPI_SHIFTCLK_DIV_008 = 2, ++ IFX_SI_FPI_SHIFTCLK_DIV_016 = 3, ++} IFX_SI_FPI_SHIFTCLK_DIV_t; ++ ++/*! ++ \enum IFX_SI_CONFIG_OP_MASK_t ++ \brief enumerated key for field "operation_mask" of struct "ifx_si_config_param_t". ++ */ ++typedef enum { ++ IFX_SI_CFG_OP_UPDATE_SOURCE = 1 << 0, /* for setting update source. */ ++ IFX_SI_CFG_OP_UPDATE_MODE = 1 << 1, /* for setting sync/async mode. */ ++ IFX_SI_CFG_OP_UPDATE_GROUP = 1 << 2, /* for setting number of input signals. */ ++ IFX_SI_CFG_OP_UPDATE_SHIFTCLKDIV = 1 << 3, /* for setting Shift-in clock through FPI CLK DIV. */ ++} IFX_SI_CONFIG_OP_MASK_t; ++ ++/*@}*/ ++ ++ ++ ++/*! ++ \addtogroup IFX_SI_STRUCT ++ */ ++/*@{*/ ++ ++/*! ++ \struct ifx_si_ioctl_version_t ++ \brief Structure used for query of driver version. ++ */ ++typedef struct { ++ unsigned int major; /*!< output, major number of driver */ ++ unsigned int mid; /*!< output, mid number of driver */ ++ unsigned int minor; /*!< output, minor number of driver */ ++} ifx_si_ioctl_version_t; ++ ++/*! ++ \struct ifx_si_config_param_t ++ \brief Structure used for configure SI Controller (Serial In). ++ */ ++typedef struct { ++ unsigned int operation_mask; /*!< input, Select operations to be performed */ ++ IFX_SI_UPD_SRC_t update_source_type; /*!< input, Corresponding update source (SW, GPT3 or FPID) */ ++ IFX_SI_FPI_SAMPLECLK_DIV_t sampling_clk_div; /*!< input, If FPID is chosen as update source type, set the divider; */ ++ /*!< input, if GPT is chosen as update source type, set the frequency;*/ ++ /*!< input, otherwise, it is ignored. */ ++ IFX_SI_SYNC_MODE_t sync_mode; /*!< input, 0: async mode (74x165), 1: sync mode (74x166) */ ++ IFX_SI_GROUP_t input_group_type; /*!< input, 0: only one is connected and hence only inputs [7:0] are enabled; */ ++ /*!< input, 1: two is connected and both inputs [15:8] and [7:0] are enabled. */ ++ IFX_SI_FPI_SHIFTCLK_DIV_t shift_in_clk_div; /*!< input, Shift-in Clock Div setting */ ++} ifx_si_config_param_t; ++ ++/*! ++ \struct ifx_si_eiu_config ++ \brief Structure used for interrupt extension with SI Controller (Serial In). ++ */ ++struct ifx_si_eiu_config { ++ int irq; // irq triggered by serial input, negative value means no SI EIU support ++ unsigned int intsync; // 1: sync mode (74x166), 0: async mode (74x165) ++ unsigned int sampling_clk; // maximum frequency of sampling clock ++ unsigned int shift_clk; // maximum frequency of shift in clock ++ unsigned int group; // 0: disabled, 1: 8 inputs, 2: 16 inputs ++ unsigned int active_high; // bit0-15: 0 - active low, 1 - active high ++}; ++ ++/*@}*/ ++ ++ ++ ++/*! ++ \addtogroup IFX_SI_IOCTL ++ */ ++/*@{*/ ++ ++#define IFX_SI_IOC_MAGIC 0xfd ++/*! ++ \def IFX_SI_IOC_VERSION ++ \brief SI Controller IOCTL Command - Get driver version number. ++ ++ This command uses struct "ifx_si_ioctl_version" as parameter to SI Controller driver version number. ++ */ ++#define IFX_SI_IOC_VERSION _IOR(IFX_SI_IOC_MAGIC, 1, ifx_si_ioctl_version_t) ++ ++/*! ++ \def IFX_SI_IOC_SET_CONFIG ++ \brief SI Controller IOCTL Command - Config SI Controller (Serial In). ++ ++ This command uses struct "ifx_si_config_param_t" as parameter to configure SI Controller (Serial In). ++ */ ++#define IFX_SI_IOC_SET_CONFIG _IOW(IFX_SI_IOC_MAGIC, 2, ifx_si_config_param_t) ++ ++/*! ++ \def IFX_SI_IOC_GET_SHIFTIN_DATA ++ \brief SI Controller IOCTL Command - Read back shift-in data value (32-bit). ++ ++ This command uses "uint32_t" as parameter to store read-back shift-in data value. ++ */ ++#define IFX_SI_IOC_GET_SHIFTIN_DATA _IOR(IFX_SI_IOC_MAGIC, 3, uint32_t) ++ ++/*! ++ \def IFX_SI_IOC_TEST ++ \brief SI Controller IOCTL Command - Run basic driver sanity check (debug). ++ ++ No parameter is needed for this command. Only for internal sanity check purpose. ++ */ ++#define IFX_SI_IOC_TEST _IO(IFX_SI_IOC_MAGIC, 0) ++ ++/* For checking endpoint */ ++#define IFX_SI_IOC_MAXNR 4 ++ ++/*@}*/ ++ ++ ++ ++#ifdef __KERNEL__ ++ extern unsigned int ifx_si_get_data(void); ++ extern unsigned int ifx_si_get_bit(unsigned int bit); ++ extern int ifx_si_config(ifx_si_config_param_t *param); ++ extern int ifx_si_irq_active_high(unsigned int bit, int active_high); ++ extern int ifx_si_irq_enable(unsigned int bit, int enable); ++ extern unsigned int ifx_si_irq_ier(void); ++ extern unsigned int ifx_si_irq_isr(void); ++#endif ++ ++ ++ ++#endif // IFX_SI_H +diff --git a/arch/mips/include/asm/ifx/ifx_ssc.h b/arch/mips/include/asm/ifx/ifx_ssc.h +new file mode 100644 +index 0000000..ea61e72 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_ssc.h +@@ -0,0 +1,242 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_ssc.h ++** PROJECT : IFX UEIP ++** MODULES : SSC ++** ++** DATE : 03 July 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : USIF for SPI Master/Slave ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Date $Author $Comment ++** 03 July,2009 Lei Chuanhua Initial UEIP version ++*******************************************************************************/ ++#ifndef IFX_SSC_H ++#define IFX_SSC_H ++ ++/*! ++ \defgroup IFX_SSC SSC bus driver module ++ \brief UEIP Project - SSC bus driver module, support all CPEs. ++*/ ++ ++/*! ++ \defgroup IFX_SSC_DEFINITIONS Definition and structions ++ \ingroup IFX_SSC ++ \brief definitions for ifx ssc driver ++*/ ++ ++/*! ++ \defgroup IFX_SSC_FUNCTIONS external APIs ++ \ingroup IFX_SSC ++ \brief IFX ssc external driver functions ++*/ ++ ++/*! ++ \defgroup IFX_SSC_INTERNAL Internal functions ++ \ingroup IFX_SSC ++ \brief IFX ssc internal driver functions ++*/ ++ ++/*! ++ \file ifx_ssc.h ++ \ingroup IFX_SSC ++ \brief header file for SSC bus driver external interface ++*/ ++ ++/*! ++ \addtogroup IFX_SSC_DEFINITIONS ++*/ ++/* @{ */ ++/*! \enum IFX_SSC_PRIO_t ++ \brief Set communication priority of SSC connection ++ ++ Three priority levels are defined. Low-level priority queue used for applications like FLASH driver ++ (ifx_ssc_prio_low). normal priority queue used for applications like display (ifx_ssc_prio_mid). ++ High priority queue used for applications like RTP packet transfer (ifx_ssc_prio_high). ++ */ ++typedef enum{ ++ IFX_SSC_PRIO_LOW = 0, /*!< Low Priority queue. For FLASH driver, etc. */ ++ IFX_SSC_PRIO_MID, /*!< Normal Priority queue. For LCD, display data, etc. */ ++ IFX_SSC_PRIO_HIGH, /*!< High priority queue. Ror RTP voice, etc. */ ++ IFX_SSC_PRIO_ASYNC, /*!< Tasklet priority (This is the highest supported priority). ++ For this priority level only the asynchronous API set ++ of the SSC driver can be called. These funtions stay unblocked and a ++ callback function is called when the request is processed. This allows ++ that the APIs are called from tasklet level. The callback function is ++ always called on tasklet level */ ++}IFX_SSC_PRIO_t; ++ ++#define IFX_SSC_PRIO_MAX IFX_SSC_PRIO_ASYNC ++ ++/*! \enum IFX_SSC_MODE_t ++ \brief Defines the Ssc hardware mode settings supported ++ ++ Because there is no official specification, what exactly SPI is and what not, it is necessary ++ to consult the data sheets of the components one wants to use. Important are the permitted clock ++ frequencies and the type of valid transitions. There are no general rules for transitions where ++ data should be latched. Although not specified by Motorola, in practice four modes are used. ++ These four modes are the combinations of CPOL and CPHA. In table 1, the four modes are listed.If ++ the phase of the clock is zero, i.e. CPHA = 0, data is latched at the rising edge of the clock with ++ CPOL = 0, and at the falling edge of the clock with CPOL = 1. If CPHA = 1, the polarities are reversed. ++ CPOL = 0 means falling edge, CPOL = 1 rising edge.The micro controllers from Motorola allow the polarity ++ and the phase of the clock to be adjusted. A positive polarity results in latching data at the rising ++ edge of the clock. However data is put on the data line already at the falling edge in order to stabilize. ++ Most peripherals which can only be slaves, work with this configuration. If it should become necessary ++ to use the other polarity, transitions are reversed. ++ */ ++typedef enum { ++ IFX_SSC_MODE_0 = 0, /*!< CPOL=0,CPHA=0 */ ++ IFX_SSC_MODE_1, /*!< CPOL=0,CPHA=1 */ ++ IFX_SSC_MODE_2, /*!< CPOL=1,CPHA=0 */ ++ IFX_SSC_MODE_3, /*!< CPOL=1,CPHA=1 */ ++ IFX_SSC_MODE_UNKNOWN,/*!< Unknown SPI mode */ ++} IFX_SSC_MODE_t; ++ ++/*! \enum IFX_SSC_HANDL_TYPE_t ++ \brief Defines the SPI handler type supported ++ */ ++typedef enum { ++ IFX_SSC_HANDL_TYPE_SYNC = 0, /*!< Only SYNC handler which be used by sync application */ ++ IFX_SSC_HANDL_TYPE_ASYNC, /*!< Only ASYNC handler which be used by async application */ ++}IFX_SSC_HANDL_TYPE_t; ++ ++/*! \enum IFX_SSC_DLX_t ++ \brief Set communication duplex mode of SSC connection ++ ++ The duplex mode is used to notify SSC bus driver by SSC device driver about what kind of ++ communication mode should be used. Which duplex mode will be used depends on the SSC device ++ driver instead of SSC bus driver. ++ */ ++typedef enum{ ++ IFX_SSC_HALF_DUPLEX = 0, /*!< Half Duplex. Interface is used in half duplex when ++ calling \ref ifx_sscTxRx or \ref ifx_sscAsyncTxRx. ++ The TX path is servered before the RX path. */ ++ IFX_SSC_FULL_DUPLEX, /*!< Full Duplex. Interface is used in full duplex when ++ calling \ref ifx_sscTxRx or \ref ifx_sscAsyncTxRx. ++ The TX-and RX- path is servered simultaneously. */ ++}IFX_SSC_DLX_t; ++ ++ ++/*!< \typedef IFX_CS_DATA ++ \brief Definition of device specific data for chip select ++ */ ++typedef int IFX_CS_DATA; ++ ++enum { ++ IFX_SSC_CS_ON = 0, ++ IFX_SSC_CS_OFF, ++}; ++ ++#define IFX_SSC_WHBGPOSTAT_OUT0_POS 0 ++#define IFX_SSC_WHBGPOSTAT_OUT1_POS 1 ++#define IFX_SSC_WHBGPOSTAT_OUT2_POS 2 ++#define IFX_SSC_WHBGPOSTAT_OUT3_POS 3 ++#define IFX_SSC_WHBGPOSTAT_OUT4_POS 4 ++#define IFX_SSC_WHBGPOSTAT_OUT5_POS 5 ++#define IFX_SSC_WHBGPOSTAT_OUT6_POS 6 ++#define IFX_SSC_WHBGPOSTAT_OUT7_POS 7 ++ ++ ++/*! \typedef IFX_SSC_CS_CB_t ++ \brief Chip Select Callback function type declaration ++ ++ csq csq=0, i.e. CS low (active). csq=1, i.e.CS high (idle). ++ cs_data This is the device number in case if more than one device is using the same registered driver. ++ E.g. two VINETICs, each with it´s own CS. ++ */ ++typedef int (*IFX_SSC_CS_CB_t)(u32 csq, IFX_CS_DATA cs_data); ++ ++/*! typedef ifx_ssc_async_fkt_cb_t ++ \brief Callback definition for asynchronous SSC API calls. This callback is called ++ by the SSC driver on tasklet level after the request is completed or exit with ++ an error. ++ ++ \param handle Funktion handle that provided for callback registration ++ during the SSC asynchronous API call. ++ \param retvalue This return value describe if the asynchronous request ++ identified an error and worked successfully. ++*/ ++typedef void (*ifx_ssc_async_fkt_cb_t) (int handle, int retvalue); ++ ++/*! typedef IFX_SSC_ASYNC_CALLBACK_t ++ \brief Parameter to specify the asynchronous callback. It is called by the SSC ++ tasklet after the requested transmission or locking is done. ++*/ ++typedef struct{ ++ ifx_ssc_async_fkt_cb_t pFunction; /*!< Callback function pointer, called in the SSC tasklet ++ when the requested command is executed*/ ++ int functionHandle; /*!< Callback function handle. This parameter is ++ transparently given to the callback function without ++ any modification by the SSC driver*/ ++}IFX_SSC_ASYNC_CALLBACK_t; ++ ++/*! \brief Parameter structure used to configure an SSC connection "ConnId". ++ */ ++typedef struct { ++ IFX_SSC_MODE_t ssc_mode; /*!< Defines the hardware setup mode of the SSC */ ++ IFX_SSC_PRIO_t ssc_prio; /*!< The communication priority of SSC connection. ++ Three priority levels are defined. Low-level priority queue used for applications ++ like FLASH driver (ifx_ssc_prio_low). Normal priority queue used for applications ++ like display (ifx_ssc_prio_mid). High priority queue used for applications like RTP ++ packet transfer (ifx_ssc_prio_high). The here defined SSC priority corresponds to ++ the priority the SSC driver application and should be set just for information when ++ the driver is registered by the application. ++ */ ++ int baudrate; /*!< Baudrate used for the ConnId. ++ This parameter can be later be modified by a call of ifx_sscSetBaud ++ */ ++ int fragSize; /*!< All transmitted and received packets should be fragmented in this fragment ++ size. Size given in Bytes. A maximum of 1024 Bytes is allowed. If the client ++ uses a bigger values here, SSC returns with error. The client has to take ++ care of the fragmentation ++ */ ++ int maxFIFOSize; /*!< Maximum packet size in FIFO mode. ++ All transmitted and received packets are transmitted in DMA mode if the packet ++ size is greater than this value. A value of 148 is recommended at first. ++ Size given in Bytes ++ */ ++ IFX_SSC_CS_CB_t csset_cb; /*!< Function Callback called by SSC driver when it starts/stops to receive or transmit */ ++ IFX_CS_DATA cs_data; /*!< Parameter used for the function call of "csSet_cb". */ ++ IFX_SSC_DLX_t duplex_mode; /*!< Duplex Mode Selector. Connection used the SSC interface either in half- or full- duplex mode. */ ++} IFX_SSC_CONFIGURE_t; ++ ++/*! \typedef IFX_SSC_HANDLE ++ \brief Definition of the connection handle ++ ++ as it is used by the client kernel module that use the SSC driver ++ Inside of the SSC driver, this handle is mapped to an internal structure that contains the connection specific ++ parameter (e.g. Baudrate, Chipselect Callbacks, etc.). ++ */ ++typedef void * IFX_SSC_HANDLE; ++/* @} */ ++ ++ ++extern int ifx_ssc_cs_low(u32 pin); ++extern int ifx_ssc_cs_high(u32 pin); ++extern int ifx_sscLock(IFX_SSC_HANDLE handler); ++extern int ifx_sscUnlock(IFX_SSC_HANDLE handler); ++extern int ifx_sscSetBaud(IFX_SSC_HANDLE handler, unsigned int baud); ++extern int ifx_sscTxRx(IFX_SSC_HANDLE handler, char* tx_buf, u32 tx_len, char* rx_buf, u32 rx_len); ++extern int ifx_sscRx(IFX_SSC_HANDLE handler, char *rx_buf, u32 rx_len); ++extern int ifx_sscTx(IFX_SSC_HANDLE handler, char *tx_buf, u32 tx_len); ++extern IFX_SSC_HANDLE ifx_sscAllocConnection(char *dev_name, IFX_SSC_CONFIGURE_t *connid); ++extern int ifx_sscFreeConnection(IFX_SSC_HANDLE handler); ++extern int ifx_sscAsyncTxRx(IFX_SSC_HANDLE handler, IFX_SSC_ASYNC_CALLBACK_t *pCallback, ++ char *txbuf, int txsize, char *rxbuf, int rxsize); ++extern int ifx_sscAsyncTx(IFX_SSC_HANDLE handler, IFX_SSC_ASYNC_CALLBACK_t *pCallback, ++ char *txbuf, int txsize); ++extern int ifx_sscAsyncRx(IFX_SSC_HANDLE handler, IFX_SSC_ASYNC_CALLBACK_t *pCallback, ++ char *rxbuf, int rxsize); ++extern int ifx_sscAsyncLock(IFX_SSC_HANDLE handler, IFX_SSC_ASYNC_CALLBACK_t *pCallback); ++extern int ifx_sscAsyncUnLock(IFX_SSC_HANDLE handler); ++ ++#endif /* IFX_SSC_H */ ++ +diff --git a/arch/mips/include/asm/ifx/ifx_types.h b/arch/mips/include/asm/ifx/ifx_types.h +new file mode 100644 +index 0000000..777bc75 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_types.h +@@ -0,0 +1,217 @@ ++#ifndef _IFX_TYPES_H ++#define _IFX_TYPES_H ++/******************************************************************************* ++ ++ Copyright (c) 2007-2009 ++ Infineon Technologies AG ++ Am Campeon 1-12; 81726 Munich, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++ ++/* Determine the target type */ ++#if defined(WIN64) || defined (_WIN64) \ ++ || defined(__x86_64__) \ ++ || defined(__LP64__) || defined(_LP64) \ ++ || defined (__amd64) \ ++ || defined (powerpc64) || defined (__powerpc64__) || defined (__ppc64__) \ ++ || defined (__64BIT__) ++/* X86_64 */ ++# ifndef IFX_64 ++# define IFX_64 1 ++# endif /* IFX_64 */ ++#elif defined (__ia64__) || defined (__ia64) ++/* IA64 */ ++# ifndef IFX_64 ++# define IFX_64 1 ++# endif /* IFX_64 */ ++#else ++/* not 64 bit system */ ++#endif /* 64 bit determination */ ++ ++/** \defgroup IFX_BASIC_TYPES Basic IFX Data Types ++ This section describes the Infineon basic data type definitions */ ++/*@{*/ ++ ++/** This is the character datatype. */ ++typedef char IFX_char_t; ++/** This is the integer datatype. */ ++typedef signed int IFX_int_t; ++/** This is the unsigned integer datatype. */ ++typedef unsigned int IFX_uint_t; ++/** This is the unsigned 8-bit datatype. */ ++typedef unsigned char IFX_uint8_t; ++/** This is the signed 8-bit datatype. */ ++typedef signed char IFX_int8_t; ++/** This is the unsigned 16-bit datatype. */ ++typedef unsigned short IFX_uint16_t; ++/** This is the signed 16-bit datatype. */ ++typedef signed short IFX_int16_t; ++/** This is the unsigned 32-bit datatype. */ ++typedef unsigned int IFX_uint32_t; ++/** This is the signed 32-bit datatype. */ ++typedef signed int IFX_int32_t; ++/** This is the float datatype. */ ++typedef float IFX_float_t; ++/** This is the void datatype. */ ++typedef void IFX_void_t; ++ ++ ++#if defined(IFX_64) && (IFX_64 == 1) ++ /* NOTE: Most Unix systems use the I32LP64 standard ++ which defines a long as 64 bits and Win64 uses ++ the IL32LLP64 standard which defines a long as 32 bits. ++ */ ++ #if defined(WIN64) ++ /** This is the unsigned 64-bit datatype. */ ++ typedef unsigned long long int IFX_uint64_t; ++ /** This is the signed 64-bit datatype. */ ++ typedef signed long long int IFX_int64_t; ++ #else /* WIN64 */ ++ /** This is the unsigned 64-bit datatype. */ ++ typedef unsigned long int IFX_uint64_t; ++ /** This is the signed 64-bit datatype. */ ++ typedef signed long int IFX_int64_t; ++ #endif /* WIN64 */ ++ ++ /** This is the unsigned long datatype. ++ On 64 bit systems it is 8 byte wide. ++ */ ++ typedef IFX_uint64_t IFX_ulong_t; ++ #define HAVE_IFX_ULONG_T ++ ++ /** This is the signed long datatype. ++ On 64 bit systems it is 8 byte wide. ++ */ ++ typedef IFX_int64_t IFX_long_t; ++ #define HAVE_IFX_LONG_T ++#else ++ /** This is the unsigned 64-bit datatype. */ ++ typedef unsigned long long int IFX_uint64_t; ++ /** This is the signed 64-bit datatype. */ ++ typedef signed long long int IFX_int64_t; ++ ++ /** This is the unsigned long datatype. ++ On 32bit systems it is 4 byte wide. ++ */ ++ typedef unsigned long IFX_ulong_t; ++ #define HAVE_IFX_ULONG_T ++ ++ /** This is the signed long datatype. ++ On 32bit systems it is 4 byte wide. ++ */ ++ typedef signed long IFX_long_t; ++ #define HAVE_IFX_LONG_T ++#endif /* 32/64 bit specific types */ ++ ++ ++/** This is the size data type (32 or 64 bit) */ ++typedef IFX_ulong_t IFX_size_t; ++#define HAVE_IFX_SIZE_T ++ ++/** This is the signed size data type (32 or 64 bit) */ ++typedef IFX_long_t IFX_ssize_t; ++#define HAVE_IFX_SSIZE_T ++ ++/** This is the time data type (32 or 64 bit) */ ++typedef IFX_ulong_t IFX_time_t; ++ ++/* NOTE: (ANSI X3.159-1989) ++ While some of these architectures feature uniform pointers ++ which are the size of some integer type, maximally portable ++ code may not assume any necessary correspondence between ++ different pointer types and the integral types. ++ ++ Since pointers and integers are now considered incommensurate, ++ the only integer that can be safely converted to a pointer ++ is the constant 0. ++*/ ++/** Conversion pointer to unsigned values (32 or 64 bit) */ ++typedef IFX_ulong_t IFX_uintptr_t; ++#define HAVE_IFX_UINTPTR_T ++/** Conversion pointer to signed values (32 or 64 bit) */ ++typedef IFX_long_t IFX_intptr_t; ++#define HAVE_IFX_INTPTR_T ++ ++/** This is the volatile unsigned 8-bit datatype. */ ++typedef volatile IFX_uint8_t IFX_vuint8_t; ++/** This is the volatile signed 8-bit datatype. */ ++typedef volatile IFX_int8_t IFX_vint8_t; ++/** This is the volatile unsigned 16-bit datatype. */ ++typedef volatile IFX_uint16_t IFX_vuint16_t; ++/** This is the volatile signed 16-bit datatype. */ ++typedef volatile IFX_int16_t IFX_vint16_t; ++/** This is the volatile unsigned 32-bit datatype. */ ++typedef volatile IFX_uint32_t IFX_vuint32_t; ++/** This is the volatile signed 32-bit datatype. */ ++typedef volatile IFX_int32_t IFX_vint32_t; ++/** This is the volatile unsigned 64-bit datatype. */ ++typedef volatile IFX_uint64_t IFX_vuint64_t; ++/** This is the volatile signed 64-bit datatype. */ ++typedef volatile IFX_int64_t IFX_vint64_t; ++/** This is the volatile float datatype. */ ++typedef volatile IFX_float_t IFX_vfloat_t; ++ ++ ++/** A type for handling boolean issues. */ ++typedef enum { ++ /** false */ ++ IFX_FALSE = 0, ++ /** true */ ++ IFX_TRUE = 1 ++} IFX_boolean_t; ++ ++ ++/** ++ This type is used for parameters that should enable ++ and disable a dedicated feature. */ ++typedef enum { ++ /** disable */ ++ IFX_DISABLE = 0, ++ /** enable */ ++ IFX_ENABLE = 1 ++} IFX_enDis_t; ++ ++/** ++ This type is used for parameters that should enable ++ and disable a dedicated feature. */ ++typedef IFX_enDis_t IFX_operation_t; ++ ++/** ++ This type has two states, even and odd. ++*/ ++typedef enum { ++ /** even */ ++ IFX_EVEN = 0, ++ /** odd */ ++ IFX_ODD = 1 ++} IFX_evenOdd_t; ++ ++ ++/** ++ This type has two states, high and low. ++*/ ++typedef enum { ++ /** low */ ++ IFX_LOW = 0, ++ /** high */ ++ IFX_HIGH = 1 ++} IFX_highLow_t; ++ ++/** ++ This type has two states, success and error ++*/ ++typedef enum { ++ /** operation failed */ ++ IFX_ERROR = -1, ++ /** operation succeeded */ ++ IFX_SUCCESS = 0 ++} IFX_return_t; ++ ++/** NULL pointer */ ++#define IFX_NULL ((IFX_void_t *)0) ++/*@}*/ /* IFX_BASIC_TYPES */ ++ ++#endif /* _IFX_TYPES_H */ +diff --git a/arch/mips/include/asm/ifx/ifx_usif_spi.h b/arch/mips/include/asm/ifx/ifx_usif_spi.h +new file mode 100644 +index 0000000..a3caa8a +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_usif_spi.h +@@ -0,0 +1,247 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_usif_spi.h ++** PROJECT : IFX UEIP for VRX200 ++** MODULES : USIF for SPI Mode ++** ++** DATE : 03 Jun 2009 ++** AUTHOR : Lei Chuanhua ++** DESCRIPTION : USIF SPI mode for counterpart API ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Date $Author $Comment ++** 03 Jun,2009 Lei Chuanhua Initial version ++*******************************************************************************/ ++ ++#ifndef IFX_USIF_SPI_H ++#define IFX_USIF_SPI_H ++ ++/*! ++ \defgroup IFX_USIF_SPI IFX USIF SPI mode module ++ \brief ifx usif spi mode driver module ++*/ ++ ++/*! ++ \defgroup IFX_USIF_SPI_DEFINITIONS Defintion and structures ++ \ingroup IFX_USIF_SPI ++ \brief definitions for ifx usif spi mode driver ++*/ ++ ++/*! ++ \defgroup IFX_USIF_SPI_FUNCTIONS External APIs ++ \ingroup IFX_USIF_SPI ++ \brief usif spi external driver functions ++*/ ++ ++/*! ++ \defgroup IFX_USIF_SPI_INTERNAL Internal functions ++ \ingroup IFX_USIF_SPI ++ \brief usif spi internal driver functions ++*/ ++ ++/*! ++ \file ifx_usif_spi.h ++ \brief header file for usif spi driver ++*/ ++ ++/* @{ */ ++/*! ++ \addtogroup IFX_USIF_SPI_DEFINITIONS ++*/ ++/*! \enum IFX_USIF_SPI_PRIO_t ++ \brief Set communication priority of USIF_SPI connection ++ ++ Three priority levels are defined. Low-level priority queue used for applications like FLASH driver ++ (ifx_usif_spi_prio_low). normal priority queue used for applications like display (ifx_usif_spi_prio_mid). ++ High priority queue used for applications like RTP packet transfer (ifx_usif_spi_prio_high). ++ */ ++typedef enum{ ++ IFX_USIF_SPI_PRIO_LOW = 0, /*!< Low Priority queue. For FLASH driver, etc. */ ++ IFX_USIF_SPI_PRIO_MID, /*!< Normal Priority queue. For LCD, display data, etc. */ ++ IFX_USIF_SPI_PRIO_HIGH, /*!< High priority queue. Ror RTP voice, etc. */ ++ IFX_USIF_SPI_PRIO_ASYNC, /*!< Tasklet priority (This is the highest supported priority). ++ For this priority level only the asynchronous API set ++ of the SSC driver can be called. These funtions stay unblocked and a ++ callback function is called when the request is processed. This allows ++ that the APIs are called from tasklet level. The callback function is ++ always called on tasklet level */ ++}IFX_USIF_SPI_PRIO_t; ++ ++#define IFX_USIF_SPI_PRIO_MAX IFX_USIF_SPI_PRIO_ASYNC ++ ++ ++/*! \enum IFX_USIF_SPI_MODE_t ++ \brief Defines the Ssc hardware mode settings supported ++ ++ Because there is no official specification, what exactly SPI is and what not, it is necessary ++ to consult the data sheets of the components one wants to use. Important are the permitted clock ++ frequencies and the type of valid transitions. There are no general rules for transitions where ++ data should be latched. Although not specified by Motorola, in practice four modes are used. ++ These four modes are the combinations of CPOL and CPHA. In table 1, the four modes are listed.If ++ the phase of the clock is zero, i.e. CPHA = 0, data is latched at the rising edge of the clock with ++ CPOL = 0, and at the falling edge of the clock with CPOL = 1. If CPHA = 1, the polarities are reversed. ++ CPOL = 0 means falling edge, CPOL = 1 rising edge.The micro controllers from Motorola allow the polarity ++ and the phase of the clock to be adjusted. A positive polarity results in latching data at the rising ++ edge of the clock. However data is put on the data line already at the falling edge in order to stabilize. ++ Most peripherals which can only be slaves, work with this configuration. If it should become necessary ++ to use the other polarity, transitions are reversed. ++ */ ++typedef enum { ++ IFX_USIF_SPI_MODE_0 = 0, /*!< CPOL=0,CPHA=0 */ ++ IFX_USIF_SPI_MODE_1, /*!< CPOL=0,CPHA=1 */ ++ IFX_USIF_SPI_MODE_2, /*!< CPOL=1,CPHA=0 */ ++ IFX_USIF_SPI_MODE_3, /*!< CPOL=1,CPHA=1 */ ++ IFX_USIF_SPI_MODE_UNKNOWN,/*!< Unknown SPI mode */ ++} IFX_USIF_SPI_MODE_t; ++ ++/*! \enum IFX_USIF_SPI_HANDL_TYPE_t ++ \brief Defines the USIF SPI handler type supported ++ */ ++typedef enum { ++ IFX_USIF_SPI_HANDL_TYPE_SYNC = 0, /*!< Only SYNC handler which be used by sync application */ ++ IFX_USIF_SPI_HANDL_TYPE_ASYNC, /*!< Only ASYNC handler which be used by async application */ ++}IFX_USIF_SPI_HANDL_TYPE_t; ++ ++/*! \enum IFX_USIF_SPI_DLX_t ++ \brief Set communication duplex mode of USIF SPI connection ++ ++ The duplex mode is used to notify USIF SPI bus driver by USIF SPI device driver about what kind of ++ communication mode should be used. Which duplex mode will be used depends on the USIF SPI device ++ driver instead of USIF SPI bus driver. ++ */ ++typedef enum{ ++ IFX_USIF_SPI_HALF_DUPLEX = 0, /*!< Half Duplex. Interface is used in half duplex when ++ calling \ref ifx_usif_spiTxRx or \ref ifx_usif_spiAsyncTxRx ++ The TX path is servered before the RX path. */ ++ IFX_USIF_SPI_FULL_DUPLEX, /*!< Full Duplex. Interface is used in full duplex when ++ calling \ref ifx_usif_spiTxRx or \ref ifx_usif_spiAsyncTxRx. ++ The TX-and RX- path is servered simultaneously. */ ++}IFX_USIF_SPI_DLX_t; ++ ++ ++ ++/*!< \typedef IFX_USIF_SPI_CS_DATA_t ++ \brief Definition of device specific data for chip select ++ */ ++typedef int IFX_USIF_SPI_CS_DATA_t; ++ ++/* chip select number */ ++#define IFX_USIF_SPI_CS0 0 ++#define IFX_USIF_SPI_CS1 1 ++#define IFX_USIF_SPI_CS2 2 ++#define IFX_USIF_SPI_CS3 3 ++#define IFX_USIF_SPI_CS4 4 ++#define IFX_USIF_SPI_CS5 5 ++#define IFX_USIF_SPI_CS6 6 ++#define IFX_USIF_SPI_CS7 7 ++ ++enum { ++ IFX_USIF_SPI_CS_ON = 0, ++ IFX_USIF_SPI_CS_OFF, ++}; ++ ++/*! \typedef IFX_USIF_SPI_CS_CB_t ++ \brief Chip Select Callback function type declaration ++ ++ csq csq=0, i.e. CS low (active). csq=1, i.e.CS high (idle). ++ cs_data This is the device number in case if more than one device is using the same registered driver. ++ E.g. two VINETICs, each with it´s own CS. ++ */ ++typedef int (*IFX_USIF_SPI_CS_CB_t)(u32 csq, IFX_USIF_SPI_CS_DATA_t cs_data); ++ ++/*! typedef ifx_usif_spi_async_fkt_cb_t ++ \brief Callback definition for asynchronous SSC API calls. This callback is called ++ by the SSC driver on tasklet level after the request is completed or exit with ++ an error. ++ ++ \param handle Funktion handle that provided for callback registration ++ during the SSC asynchronous API call. ++ \param retvalue This return value describe if the asynchronous request ++ identified an error and worked successfully. ++*/ ++typedef void (*ifx_usif_spi_async_fkt_cb_t)(int handle, int retvalue); ++ ++/*! typedef IFX_SSC_ASYNC_CALLBACK_t ++ \brief Parameter to specify the asynchronous callback. It is called by the SSC ++ tasklet after the requested transmission or locking is done. ++*/ ++typedef struct{ ++ ifx_usif_spi_async_fkt_cb_t pFunction; /*!< Callback function pointer, called in the SSC tasklet ++ when the requested command is executed*/ ++ int functionHandle; /*!< Callback function handle. This parameter is ++ transparently given to the callback function without ++ any modification by the SSC driver*/ ++}IFX_USIF_SPI_ASYNC_CALLBACK_t; ++ ++ ++/*! \brief Parameter structure used to configure an USIF_SPI connection "ConnId". ++ */ ++typedef struct{ ++ IFX_USIF_SPI_MODE_t spi_mode; /*!< Defines the hardware setup mode of the USIF_SPI */ ++ IFX_USIF_SPI_PRIO_t spi_prio; /*!< The communication priority of USIF_SPI connection. ++ Three priority levels are defined. Low-level priority queue used for applications ++ like FLASH driver (ifx_usif_spi_prio_low). Normal priority queue used for applications ++ like display (ifx_usif_spi_prio_mid). High priority queue used for applications like RTP ++ packet transfer (ifx_usif_spi_prio_high). The here defined USIF_SPI priority corresponds to ++ the priority the USIF_SPI driver application and should be set just for information when ++ the driver is registered by the application. ++ */ ++ int baudrate; /*!< Baudrate used for the ConnId. ++ This parameter can be later be modified by a call of ifx_usif_spiSetBaud ++ */ ++ int fragSize; /*!< All transmitted and received packets should be fragmented in this fragment ++ size. Size given in Bytes. A maximum of 1024 Bytes is allowed. If the client ++ uses a bigger values here, USIF_SPI returns with error. The client has to take ++ care of the fragmentation ++ */ ++ int maxFIFOSize; /*!< Maximum packet size in FIFO mode. ++ All transmitted and received packets are transmitted in DMA mode if the packet ++ size is greater than this value. A value of 148 is recommended at first. ++ Size given in Bytes ++ */ ++ IFX_USIF_SPI_CS_CB_t csset_cb; /*!< Function Callback called by USIF_SPI driver when it starts/stops to receive or transmit */ ++ IFX_USIF_SPI_CS_DATA_t cs_data; /*!< Parameter used for the function call of "csSet_cb". */ ++ IFX_USIF_SPI_DLX_t duplex_mode; /*!< Duplex Mode Selector. Connection used the USIF SPI interface either in half- or full- duplex mode. */ ++ ++} IFX_USIF_SPI_CONFIGURE_t; ++ ++/*! \typedef IFX_USIF_SPI_HANDLE_t ++ \brief Definition of the connection handle ++ ++ as it is used by the client kernel module that use the USIF_SPI driver ++ Inside of the USIF_SPI driver, this handle is mapped to an internal structure that contains the connection specific ++ parameter (e.g. Baudrate, Chipselect Callbacks, etc.). ++ */ ++typedef void * IFX_USIF_SPI_HANDLE_t; ++/* @} */ ++ ++extern int ifx_usif_spi_cs_low(u32 pin); ++extern int ifx_usif_spi_cs_high(u32 pin); ++extern int ifx_usif_spiLock(IFX_USIF_SPI_HANDLE_t handler); ++extern int ifx_usif_spiUnlock(IFX_USIF_SPI_HANDLE_t handler); ++extern int ifx_usif_spiSetBaud(IFX_USIF_SPI_HANDLE_t handler, unsigned int baud); ++extern int ifx_usif_spiTxRx(IFX_USIF_SPI_HANDLE_t handler, char* txbuf, ++ u32 txlen,char* rxbuf, u32 rxlen); ++extern int ifx_usif_spiRx(IFX_USIF_SPI_HANDLE_t handler, char *rxbuf, u32 rxlen); ++extern int ifx_usif_spiTx(IFX_USIF_SPI_HANDLE_t handler, char *txbuf, u32 txlen); ++extern IFX_USIF_SPI_HANDLE_t ifx_usif_spiAllocConnection (char *dev_name, IFX_USIF_SPI_CONFIGURE_t *connid); ++extern int ifx_usif_spiFreeConnection (IFX_USIF_SPI_HANDLE_t handler); ++extern int ifx_usif_spiAsyncTxRx(IFX_USIF_SPI_HANDLE_t handler, IFX_USIF_SPI_ASYNC_CALLBACK_t *pCallback, ++ char *txbuf, int txsize, char *rxbuf, int rxsize); ++extern int ifx_usif_spiAsyncTx(IFX_USIF_SPI_HANDLE_t handler, IFX_USIF_SPI_ASYNC_CALLBACK_t *pCallback, ++ char *txbuf, int txsize); ++extern int ifx_usif_spiAsyncRx(IFX_USIF_SPI_HANDLE_t handler, IFX_USIF_SPI_ASYNC_CALLBACK_t *pCallback, ++ char *rxbuf, int rxsize); ++ ++extern int ifx_usif_spiAsyncLock(IFX_USIF_SPI_HANDLE_t handler, IFX_USIF_SPI_ASYNC_CALLBACK_t *pCallback); ++extern int ifx_usif_spiAsyncUnLock(IFX_USIF_SPI_HANDLE_t handler); ++ ++#endif /* IFX_USIF_SPI_H */ ++ +diff --git a/arch/mips/include/asm/ifx/ifx_wdt.h b/arch/mips/include/asm/ifx/ifx_wdt.h +new file mode 100644 +index 0000000..8424507 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/ifx_wdt.h +@@ -0,0 +1,118 @@ ++/****************************************************************************** ++** ++** FILE NAME : ifx_wdt.h ++** PROJECT : IFX UEIP ++** MODULES : WDT ++** ++** DATE : 12 Aug 2009 ++** AUTHOR : Lee Yao Chye ++** DESCRIPTION : Watchdog Timer ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** HISTORY ++** $Date $Author $Comment ++** 12 Aug 2009 Lee Yao Chye Initial UEIP version ++** 19 Oct 2009 Lee Yao Chye Add Linux style ioctls ++*******************************************************************************/ ++#ifndef IFX_WDT_H ++#define IFX_WDT_H ++ ++/*! ++ \defgroup IFX_WDT_IOCTL IOCTL Commands ++ \ingroup IFX_WDT ++ \brief IOCTL Commands used by user application. ++ */ ++ ++ ++#include ++ ++/*! ++ \addtogroup IFX_WDT_IOCTL ++ */ ++/*@{*/ ++ ++/* wdt ioctl control */ ++#define IFX_WDT_IOC_MAGIC 0xc0 ++ ++/*! ++ \def IFX_WDT_IOC_START ++ \brief wdt IOCTL Command - similar to WDIOC_SETTIMEOUT ++ ++ This command is used to configure the watchdog timeout and start the watchdog. ++ */ ++#define IFX_WDT_IOC_START _IOW(IFX_WDT_IOC_MAGIC, 0, int) ++ ++/*! ++ \def IFX_WDT_IOC_STOP ++ \brief wdt IOCTL Command - stop the watchdog ++ ++ This command is used to stop the watchdog. ++ */ ++#define IFX_WDT_IOC_STOP _IO(IFX_WDT_IOC_MAGIC, 1) ++ ++/*! ++ \def IFX_WDT_IOC_PING ++ \brief wdt IOCTL Command - similar to WDIOC_KEEPALIVE ++ ++ This command is used to keep the watchdog alive. ++ */ ++#define IFX_WDT_IOC_PING _IO(IFX_WDT_IOC_MAGIC, 2) ++ ++/*! ++ \def IFX_WDT_IOC_SET_PWL ++ \brief wdt IOCTL Command - set prewarning level ++ ++ This command is used to configure the prewarning level. ++ 0 for 1/2 of the max WDT period ++ 1 for 1/4 of the max WDT period ++ 2 for 1/8 of the max WDT period ++ 3 for 1/16 of the max WDT period ++ */ ++#define IFX_WDT_IOC_SET_PWL _IOW(IFX_WDT_IOC_MAGIC, 3, int) ++ ++/*! ++ \def IFX_WDT_IOC_SET_DSEN ++ \brief wdt IOCTL Command - configure debug suspend ++ ++ This command is used to configure debug suspend. ++ */ ++#define IFX_WDT_IOC_SET_DSEN _IOW(IFX_WDT_IOC_MAGIC, 4, int) ++ ++/*! ++ \def IFX_WDT_IOC_SET_LPEN ++ \brief wdt IOCTL Command - configure low power clock freeze mode ++ ++ This command is used to configure low power clock freeze mode. ++ */ ++#define IFX_WDT_IOC_SET_LPEN _IOW(IFX_WDT_IOC_MAGIC, 5, int) ++ ++/*! ++ \def IFX_WDT_IOC_GET_STATUS ++ \brief wdt IOCTL Command - reads the watchdog status register ++ ++ This command is used to read the watchdog status register. ++ */ ++#define IFX_WDT_IOC_GET_STATUS _IOR(IFX_WDT_IOC_MAGIC, 6, int) ++ ++/*! ++ \def IFX_WDT_IOC_SET_CLKDIV ++ \brief wdt IOCTL Command - configures the watchdog clock divider ++ ++ This command is used to configure the watchdog clock divider. ++ 0 for CLK_WDT = 1 x CLK_TIMER ++ 1 for CLK_WDT = 64 x CLK_TIMER ++ 2 for CLK_WDT = 4096 x CLK_TIMER ++ 3 for CLK_WDT = 262144 x CLK_TIMER ++ */ ++#define IFX_WDT_IOC_SET_CLKDIV _IOW(IFX_WDT_IOC_MAGIC, 7, int) ++ ++/*@}*/ ++ ++ ++#endif /* IFX_WDT_H */ +diff --git a/arch/mips/include/asm/ifx/irq.h b/arch/mips/include/asm/ifx/irq.h +new file mode 100644 +index 0000000..6a66f96 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/irq.h +@@ -0,0 +1,256 @@ ++/****************************************************************************** ++** ++** FILE NAME : irq.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : common header file ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef IFX_IRQ_H ++#define IFX_IRQ_H ++ ++ ++#include ++#include ++ ++unsigned int ltq_irq_create_mapping(unsigned int irq); ++ ++/* these vectors are to handle the interrupts from the internal DANUBE ++ * interrupt controller. THe INT_NUM values are really just indices into ++ * an array and are set up so that we can use the INT_NUM as a shift ++ * to calculate a mask value. ++ */ ++//#define INT_NUM_IRQ0 0x00 ++#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) ++#define INT_NUM_IM0_IRL1 (INT_NUM_IRQ0 + 1) ++#define INT_NUM_IM0_IRL2 (INT_NUM_IRQ0 + 2) ++#define INT_NUM_IM0_IRL3 (INT_NUM_IRQ0 + 3) ++#define INT_NUM_IM0_IRL4 (INT_NUM_IRQ0 + 4) ++#define INT_NUM_IM0_IRL5 (INT_NUM_IRQ0 + 5) ++#define INT_NUM_IM0_IRL6 (INT_NUM_IRQ0 + 6) ++#define INT_NUM_IM0_IRL7 (INT_NUM_IRQ0 + 7) ++#define INT_NUM_IM0_IRL8 (INT_NUM_IRQ0 + 8) ++#define INT_NUM_IM0_IRL9 (INT_NUM_IRQ0 + 9) ++#define INT_NUM_IM0_IRL10 (INT_NUM_IRQ0 + 10) ++#define INT_NUM_IM0_IRL11 (INT_NUM_IRQ0 + 11) ++#define INT_NUM_IM0_IRL12 (INT_NUM_IRQ0 + 12) ++#define INT_NUM_IM0_IRL13 (INT_NUM_IRQ0 + 13) ++#define INT_NUM_IM0_IRL14 (INT_NUM_IRQ0 + 14) ++#define INT_NUM_IM0_IRL15 (INT_NUM_IRQ0 + 15) ++#define INT_NUM_IM0_IRL16 (INT_NUM_IRQ0 + 16) ++#define INT_NUM_IM0_IRL17 (INT_NUM_IRQ0 + 17) ++#define INT_NUM_IM0_IRL18 (INT_NUM_IRQ0 + 18) ++#define INT_NUM_IM0_IRL19 (INT_NUM_IRQ0 + 19) ++#define INT_NUM_IM0_IRL20 (INT_NUM_IRQ0 + 20) ++#define INT_NUM_IM0_IRL21 (INT_NUM_IRQ0 + 21) ++#define INT_NUM_IM0_IRL22 (INT_NUM_IRQ0 + 22) ++#define INT_NUM_IM0_IRL23 (INT_NUM_IRQ0 + 23) ++#define INT_NUM_IM0_IRL24 (INT_NUM_IRQ0 + 24) ++#define INT_NUM_IM0_IRL25 (INT_NUM_IRQ0 + 25) ++#define INT_NUM_IM0_IRL26 (INT_NUM_IRQ0 + 26) ++#define INT_NUM_IM0_IRL27 (INT_NUM_IRQ0 + 27) ++#define INT_NUM_IM0_IRL28 (INT_NUM_IRQ0 + 28) ++#define INT_NUM_IM0_IRL29 (INT_NUM_IRQ0 + 29) ++#define INT_NUM_IM0_IRL30 (INT_NUM_IRQ0 + 30) ++#define INT_NUM_IM0_IRL31 (INT_NUM_IRQ0 + 31) ++ ++#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32) ++#define INT_NUM_IM1_IRL1 (INT_NUM_IM1_IRL0 + 1) ++#define INT_NUM_IM1_IRL2 (INT_NUM_IM1_IRL0 + 2) ++#define INT_NUM_IM1_IRL3 (INT_NUM_IM1_IRL0 + 3) ++#define INT_NUM_IM1_IRL4 (INT_NUM_IM1_IRL0 + 4) ++#define INT_NUM_IM1_IRL5 (INT_NUM_IM1_IRL0 + 5) ++#define INT_NUM_IM1_IRL6 (INT_NUM_IM1_IRL0 + 6) ++#define INT_NUM_IM1_IRL7 (INT_NUM_IM1_IRL0 + 7) ++#define INT_NUM_IM1_IRL8 (INT_NUM_IM1_IRL0 + 8) ++#define INT_NUM_IM1_IRL9 (INT_NUM_IM1_IRL0 + 9) ++#define INT_NUM_IM1_IRL10 (INT_NUM_IM1_IRL0 + 10) ++#define INT_NUM_IM1_IRL11 (INT_NUM_IM1_IRL0 + 11) ++#define INT_NUM_IM1_IRL12 (INT_NUM_IM1_IRL0 + 12) ++#define INT_NUM_IM1_IRL13 (INT_NUM_IM1_IRL0 + 13) ++#define INT_NUM_IM1_IRL14 (INT_NUM_IM1_IRL0 + 14) ++#define INT_NUM_IM1_IRL15 (INT_NUM_IM1_IRL0 + 15) ++#define INT_NUM_IM1_IRL16 (INT_NUM_IM1_IRL0 + 16) ++#define INT_NUM_IM1_IRL17 (INT_NUM_IM1_IRL0 + 17) ++#define INT_NUM_IM1_IRL18 (INT_NUM_IM1_IRL0 + 18) ++#define INT_NUM_IM1_IRL19 (INT_NUM_IM1_IRL0 + 19) ++#define INT_NUM_IM1_IRL20 (INT_NUM_IM1_IRL0 + 20) ++#define INT_NUM_IM1_IRL21 (INT_NUM_IM1_IRL0 + 21) ++#define INT_NUM_IM1_IRL22 (INT_NUM_IM1_IRL0 + 22) ++#define INT_NUM_IM1_IRL23 (INT_NUM_IM1_IRL0 + 23) ++#define INT_NUM_IM1_IRL24 (INT_NUM_IM1_IRL0 + 24) ++#define INT_NUM_IM1_IRL25 (INT_NUM_IM1_IRL0 + 25) ++#define INT_NUM_IM1_IRL26 (INT_NUM_IM1_IRL0 + 26) ++#define INT_NUM_IM1_IRL27 (INT_NUM_IM1_IRL0 + 27) ++#define INT_NUM_IM1_IRL28 (INT_NUM_IM1_IRL0 + 28) ++#define INT_NUM_IM1_IRL29 (INT_NUM_IM1_IRL0 + 29) ++#define INT_NUM_IM1_IRL30 (INT_NUM_IM1_IRL0 + 30) ++#define INT_NUM_IM1_IRL31 (INT_NUM_IM1_IRL0 + 31) ++ ++#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64) ++#define INT_NUM_IM2_IRL1 (INT_NUM_IM2_IRL0 + 1) ++#define INT_NUM_IM2_IRL2 (INT_NUM_IM2_IRL0 + 2) ++#define INT_NUM_IM2_IRL3 (INT_NUM_IM2_IRL0 + 3) ++#define INT_NUM_IM2_IRL4 (INT_NUM_IM2_IRL0 + 4) ++#define INT_NUM_IM2_IRL5 (INT_NUM_IM2_IRL0 + 5) ++#define INT_NUM_IM2_IRL6 (INT_NUM_IM2_IRL0 + 6) ++#define INT_NUM_IM2_IRL7 (INT_NUM_IM2_IRL0 + 7) ++#define INT_NUM_IM2_IRL8 (INT_NUM_IM2_IRL0 + 8) ++#define INT_NUM_IM2_IRL9 (INT_NUM_IM2_IRL0 + 9) ++#define INT_NUM_IM2_IRL10 (INT_NUM_IM2_IRL0 + 10) ++#define INT_NUM_IM2_IRL11 (INT_NUM_IM2_IRL0 + 11) ++#define INT_NUM_IM2_IRL12 (INT_NUM_IM2_IRL0 + 12) ++#define INT_NUM_IM2_IRL13 (INT_NUM_IM2_IRL0 + 13) ++#define INT_NUM_IM2_IRL14 (INT_NUM_IM2_IRL0 + 14) ++#define INT_NUM_IM2_IRL15 (INT_NUM_IM2_IRL0 + 15) ++#define INT_NUM_IM2_IRL16 (INT_NUM_IM2_IRL0 + 16) ++#define INT_NUM_IM2_IRL17 (INT_NUM_IM2_IRL0 + 17) ++#define INT_NUM_IM2_IRL18 (INT_NUM_IM2_IRL0 + 18) ++#define INT_NUM_IM2_IRL19 (INT_NUM_IM2_IRL0 + 19) ++#define INT_NUM_IM2_IRL20 (INT_NUM_IM2_IRL0 + 20) ++#define INT_NUM_IM2_IRL21 (INT_NUM_IM2_IRL0 + 21) ++#define INT_NUM_IM2_IRL22 (INT_NUM_IM2_IRL0 + 22) ++#define INT_NUM_IM2_IRL23 (INT_NUM_IM2_IRL0 + 23) ++#define INT_NUM_IM2_IRL24 (INT_NUM_IM2_IRL0 + 24) ++#define INT_NUM_IM2_IRL25 (INT_NUM_IM2_IRL0 + 25) ++#define INT_NUM_IM2_IRL26 (INT_NUM_IM2_IRL0 + 26) ++#define INT_NUM_IM2_IRL27 (INT_NUM_IM2_IRL0 + 27) ++#define INT_NUM_IM2_IRL28 (INT_NUM_IM2_IRL0 + 28) ++#define INT_NUM_IM2_IRL29 (INT_NUM_IM2_IRL0 + 29) ++#define INT_NUM_IM2_IRL30 (INT_NUM_IM2_IRL0 + 30) ++#define INT_NUM_IM2_IRL31 (INT_NUM_IM2_IRL0 + 31) ++ ++#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96) ++#define INT_NUM_IM3_IRL1 (INT_NUM_IM3_IRL0 + 1) ++#define INT_NUM_IM3_IRL2 (INT_NUM_IM3_IRL0 + 2) ++#define INT_NUM_IM3_IRL3 (INT_NUM_IM3_IRL0 + 3) ++#define INT_NUM_IM3_IRL4 (INT_NUM_IM3_IRL0 + 4) ++#define INT_NUM_IM3_IRL5 (INT_NUM_IM3_IRL0 + 5) ++#define INT_NUM_IM3_IRL6 (INT_NUM_IM3_IRL0 + 6) ++#define INT_NUM_IM3_IRL7 (INT_NUM_IM3_IRL0 + 7) ++#define INT_NUM_IM3_IRL8 (INT_NUM_IM3_IRL0 + 8) ++#define INT_NUM_IM3_IRL9 (INT_NUM_IM3_IRL0 + 9) ++#define INT_NUM_IM3_IRL10 (INT_NUM_IM3_IRL0 + 10) ++#define INT_NUM_IM3_IRL11 (INT_NUM_IM3_IRL0 + 11) ++#define INT_NUM_IM3_IRL12 (INT_NUM_IM3_IRL0 + 12) ++#define INT_NUM_IM3_IRL13 (INT_NUM_IM3_IRL0 + 13) ++#define INT_NUM_IM3_IRL14 (INT_NUM_IM3_IRL0 + 14) ++#define INT_NUM_IM3_IRL15 (INT_NUM_IM3_IRL0 + 15) ++#define INT_NUM_IM3_IRL16 (INT_NUM_IM3_IRL0 + 16) ++#define INT_NUM_IM3_IRL17 (INT_NUM_IM3_IRL0 + 17) ++#define INT_NUM_IM3_IRL18 (INT_NUM_IM3_IRL0 + 18) ++#define INT_NUM_IM3_IRL19 (INT_NUM_IM3_IRL0 + 19) ++#define INT_NUM_IM3_IRL20 (INT_NUM_IM3_IRL0 + 20) ++#define INT_NUM_IM3_IRL21 (INT_NUM_IM3_IRL0 + 21) ++#define INT_NUM_IM3_IRL22 (INT_NUM_IM3_IRL0 + 22) ++#define INT_NUM_IM3_IRL23 (INT_NUM_IM3_IRL0 + 23) ++#define INT_NUM_IM3_IRL24 (INT_NUM_IM3_IRL0 + 24) ++#define INT_NUM_IM3_IRL25 (INT_NUM_IM3_IRL0 + 25) ++#define INT_NUM_IM3_IRL26 (INT_NUM_IM3_IRL0 + 26) ++#define INT_NUM_IM3_IRL27 (INT_NUM_IM3_IRL0 + 27) ++#define INT_NUM_IM3_IRL28 (INT_NUM_IM3_IRL0 + 28) ++#define INT_NUM_IM3_IRL29 (INT_NUM_IM3_IRL0 + 29) ++#define INT_NUM_IM3_IRL30 (INT_NUM_IM3_IRL0 + 30) ++#define INT_NUM_IM3_IRL31 (INT_NUM_IM3_IRL0 + 31) ++ ++#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128) ++#define INT_NUM_IM4_IRL1 (INT_NUM_IM4_IRL0 + 1) ++#define INT_NUM_IM4_IRL2 (INT_NUM_IM4_IRL0 + 2) ++#define INT_NUM_IM4_IRL3 (INT_NUM_IM4_IRL0 + 3) ++#define INT_NUM_IM4_IRL4 (INT_NUM_IM4_IRL0 + 4) ++#define INT_NUM_IM4_IRL5 (INT_NUM_IM4_IRL0 + 5) ++#define INT_NUM_IM4_IRL6 (INT_NUM_IM4_IRL0 + 6) ++#define INT_NUM_IM4_IRL7 (INT_NUM_IM4_IRL0 + 7) ++#define INT_NUM_IM4_IRL8 (INT_NUM_IM4_IRL0 + 8) ++#define INT_NUM_IM4_IRL9 (INT_NUM_IM4_IRL0 + 9) ++#define INT_NUM_IM4_IRL10 (INT_NUM_IM4_IRL0 + 10) ++#define INT_NUM_IM4_IRL11 (INT_NUM_IM4_IRL0 + 11) ++#define INT_NUM_IM4_IRL12 (INT_NUM_IM4_IRL0 + 12) ++#define INT_NUM_IM4_IRL13 (INT_NUM_IM4_IRL0 + 13) ++#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14) ++#define INT_NUM_IM4_IRL15 (INT_NUM_IM4_IRL0 + 15) ++#define INT_NUM_IM4_IRL16 (INT_NUM_IM4_IRL0 + 16) ++#define INT_NUM_IM4_IRL17 (INT_NUM_IM4_IRL0 + 17) ++#define INT_NUM_IM4_IRL18 (INT_NUM_IM4_IRL0 + 18) ++#define INT_NUM_IM4_IRL19 (INT_NUM_IM4_IRL0 + 19) ++#define INT_NUM_IM4_IRL20 (INT_NUM_IM4_IRL0 + 20) ++#define INT_NUM_IM4_IRL21 (INT_NUM_IM4_IRL0 + 21) ++#define INT_NUM_IM4_IRL22 (INT_NUM_IM4_IRL0 + 22) ++#define INT_NUM_IM4_IRL23 (INT_NUM_IM4_IRL0 + 23) ++#define INT_NUM_IM4_IRL24 (INT_NUM_IM4_IRL0 + 24) ++#define INT_NUM_IM4_IRL25 (INT_NUM_IM4_IRL0 + 25) ++#define INT_NUM_IM4_IRL26 (INT_NUM_IM4_IRL0 + 26) ++#define INT_NUM_IM4_IRL27 (INT_NUM_IM4_IRL0 + 27) ++#define INT_NUM_IM4_IRL28 (INT_NUM_IM4_IRL0 + 28) ++#define INT_NUM_IM4_IRL29 (INT_NUM_IM4_IRL0 + 29) ++#define INT_NUM_IM4_IRL30 (INT_NUM_IM4_IRL0 + 30) ++#define INT_NUM_IM4_IRL31 (INT_NUM_IM4_IRL0 + 31) ++ ++#define INT_NUM_SI_EIU_IR0 (INT_NUM_IRQ0 + 160) ++#define INT_NUM_SI_EIU_IR1 (INT_NUM_SI_EIU_IR0 + 1) ++#define INT_NUM_SI_EIU_IR2 (INT_NUM_SI_EIU_IR0 + 2) ++#define INT_NUM_SI_EIU_IR3 (INT_NUM_SI_EIU_IR0 + 3) ++#define INT_NUM_SI_EIU_IR4 (INT_NUM_SI_EIU_IR0 + 4) ++#define INT_NUM_SI_EIU_IR5 (INT_NUM_SI_EIU_IR0 + 5) ++#define INT_NUM_SI_EIU_IR6 (INT_NUM_SI_EIU_IR0 + 6) ++#define INT_NUM_SI_EIU_IR7 (INT_NUM_SI_EIU_IR0 + 7) ++#define INT_NUM_SI_EIU_IR8 (INT_NUM_SI_EIU_IR0 + 8) ++#define INT_NUM_SI_EIU_IR9 (INT_NUM_SI_EIU_IR0 + 9) ++#define INT_NUM_SI_EIU_IR10 (INT_NUM_SI_EIU_IR0 + 10) ++#define INT_NUM_SI_EIU_IR11 (INT_NUM_SI_EIU_IR0 + 11) ++#define INT_NUM_SI_EIU_IR12 (INT_NUM_SI_EIU_IR0 + 12) ++#define INT_NUM_SI_EIU_IR13 (INT_NUM_SI_EIU_IR0 + 13) ++#define INT_NUM_SI_EIU_IR14 (INT_NUM_SI_EIU_IR0 + 14) ++#define INT_NUM_SI_EIU_IR15 (INT_NUM_SI_EIU_IR0 + 15) ++ ++#define MIPS_CPU_CPUCTR_IRQ INT_NUM_IM4_IRL31 ++//#define MIPS_CPU_TIMER_IRQ (INT_NUM_SI_EIU_IR15 + 1) ++#define MIPSCPU_INT_BASE (MIPS_CPU_TIMER_IRQ + 1) ++ ++#ifdef CONFIG_MIPS_MT_SMTC ++#define MIPSCPU_INT_CPUCTR 7 ++#endif ++ ++ ++#if defined(CONFIG_DANUBE) ++#include "danube/irq.h" ++#elif defined(CONFIG_AMAZON_SE) ++#include "amazon_se/irq.h" ++#elif defined(CONFIG_AR9) ++#include "ar9/irq.h" ++#elif defined(CONFIG_VR9) ++#include "vr9/irq.h" ++#elif defined(CONFIG_AR10) ++#include "ar10/irq.h" ++#elif defined(CONFIG_HN1) ++#include "hn1/irq.h" ++#else ++#error unknown chip ++#endif ++ ++ ++extern void bsp_mask_and_ack_irq(u32 irq_nr); ++extern void bsp_enable_irq(u32 irq_nr); ++extern void bsp_disable_irq(u32 irq_nr); ++extern void ifx_icu_irsr_set(u32 irq); ++extern void ifx_icu_irsr_clr(u32 irq); ++ ++ ++#endif /* IFX_IRQ_H */ +diff --git a/arch/mips/include/asm/ifx/model.h b/arch/mips/include/asm/ifx/model.h +new file mode 100644 +index 0000000..d3b9fab +--- /dev/null ++++ b/arch/mips/include/asm/ifx/model.h +@@ -0,0 +1,50 @@ ++/****************************************************************************** ++** ++** FILE NAME : model.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : common header file ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef IFX_MODEL_H ++#define IFX_MODEL_H ++ ++ ++ ++#if defined(CONFIG_DANUBE) ++# include "danube/model.h" ++#elif defined(CONFIG_AMAZON_SE) ++# include "amazon_se/model.h" ++#elif defined(CONFIG_AR9) ++# include "ar9/model.h" ++#elif defined(CONFIG_VR9) ++# include "vr9/model.h" ++#elif defined(CONFIG_AR10) ++# include "ar10/model.h" ++#elif defined(CONFIG_HN1) ++# include "hn1/model.h" ++#else ++# error unknown chip ++#endif ++ ++ ++ ++#endif // IFX_MODEL_H ++ +diff --git a/arch/mips/include/asm/ifx/vr9/emulation.h b/arch/mips/include/asm/ifx/vr9/emulation.h +new file mode 100644 +index 0000000..819523a +--- /dev/null ++++ b/arch/mips/include/asm/ifx/vr9/emulation.h +@@ -0,0 +1,46 @@ ++/****************************************************************************** ++** ++** FILE NAME : emulation.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Lei Chuan Hua ++** DESCRIPTION : header file for VR9 ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Lei Chuan Hua The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef EMULATION_H ++#define EMULATION_H ++ ++#ifdef CONFIG_USE_EMULATOR ++ ++#ifdef CONFIG_USE_VENUS ++ #define EMULATOR_CPU_SPEED 3000000 ++ #define PLL0_CLK_SPEED 2500000 ++#elif defined(CONFIG_USE_PALLADIUM) ++ #define EMULATOR_CPU_SPEED 214000 ++ #define PLL0_CLK_SPEED 214000 ++#else ++ #define EMULATOR_CPU_SPEED 25000 ++ #define PLL0_CLK_SPEED 25000 ++#endif /* CONFIG_USE_VENUS */ ++#else /* Real chip */ ++ #define PLL0_CLK_SPEED 1000000000 ++#endif /* CONFIG_USE_EMULATOR */ ++#endif /* */ ++ /* EMULATION_H */ ++ +diff --git a/arch/mips/include/asm/ifx/vr9/irq.h b/arch/mips/include/asm/ifx/vr9/irq.h +new file mode 100644 +index 0000000..35b3d4b +--- /dev/null ++++ b/arch/mips/include/asm/ifx/vr9/irq.h +@@ -0,0 +1,196 @@ ++/****************************************************************************** ++** ++** FILE NAME : irq.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : header file for VR9 ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef VR9_IRQ_H ++#define VR9_IRQ_H ++ ++ ++ ++/****** Interrupt Assigments ***********/ ++ ++#define IFX_ASC1_TIR INT_NUM_IM3_IRL7 /* TX interrupt */ ++#define IFX_ASC1_TBIR INT_NUM_IM3_IRL8 /* TX buffer interrupt */ ++#define IFX_ASC1_RIR INT_NUM_IM3_IRL9 /* RX interrupt */ ++#define IFX_ASC1_EIR INT_NUM_IM3_IRL10 /* ERROR interrupt */ ++#define IFX_ASC1_ABSTIR INT_NUM_IM3_IRL11 ++#define IFX_ASC1_ABDETIR INT_NUM_IM3_IRL12 ++#define IFX_ASC1_SFCIR INT_NUM_IM3_IRL13 ++ ++#define IFX_FPI_SLAVE_BCU0_IR INT_NUM_IM1_IRL25 ++#define IFX_FPI_MASTER_COSBCU_IR INT_NUM_IM0_IRL25 ++#define IFX_CROSSBAR_ERR_IR INT_NUM_IM4_IRL23 ++#define IFX_FPI_SLAVE_BCU_IRQ IFX_FPI_SLAVE_BCU0_IR ++#define IFX_FPI_MASTER_BCU_IRQ IFX_FPI_MASTER_COSBCU_IR ++ ++#define IFX_DSL_DFE_IR INT_NUM_IM1_IRL23 ++#define IFX_DSL_AFEOVL_IR INT_NUM_IM1_IRL24 ++#define IFX_DSL_DYING_GASP_INT INT_NUM_IM1_IRL21 ++#define IFX_DSL_DFE_INT0IR INT_NUM_IM2_IRL12 ++#define IFX_DSL_DFE_INT1IR INT_NUM_IM2_IRL13 ++#define IFX_DSL_DFE_INT2IR INT_NUM_IM2_IRL14 ++#define IFX_DSL_DFE_INT3IR INT_NUM_IM2_IRL15 ++#define IFX_DSL_SI INT_NUM_IM2_IRL20 ++#define IFX_DSL_WAKEUP INT_NUM_IM2_IRL22 ++#define IFX_MEI_INT IFX_DSL_DFE_IR ++#define IFX_MEI_DYING_GASP_INT IFX_DSL_DYING_GASP_INT ++#define IFX_DSL_DFE_TXIR IFX_DSL_DFE_INT0IR ++#define IFX_DSL_DFE_RXIR IFX_DSL_DFE_INT1IR ++ ++#define IFX_PCIE_INTA INT_NUM_IM4_IRL8 ++#define IFX_PCIE_INTB INT_NUM_IM4_IRL9 ++#define IFX_PCIE_INTC INT_NUM_IM4_IRL10 ++#define IFX_PCIE_INTD INT_NUM_IM4_IRL11 ++#define IFX_PCIE_IR INT_NUM_IM4_IRL25 ++#define IFX_PCIE_WAKE INT_NUM_IM4_IRL26 ++#define IFX_PCIE_MSI_IR0 INT_NUM_IM4_IRL27 ++#define IFX_PCIE_MSI_IR1 INT_NUM_IM4_IRL28 ++#define IFX_PCIE_MSI_IR2 INT_NUM_IM4_IRL29 ++#define IFX_PCIE_MSI_IR3 INT_NUM_IM0_IRL30 ++#define IFX_PCIE_L3_INT INT_NUM_IM3_IRL16 ++ ++#define IFX_DEU_DESIR INT_NUM_IM0_IRL27 ++#define IFX_DEU_AESIR INT_NUM_IM0_IRL28 ++#define IFX_DEU_HASHIR INT_NUM_IM0_IRL29 ++#define IFX_DEU_ARCIR INT_NUM_IM0_IRL26 ++ ++#define IFX_DMA_CH0_INT INT_NUM_IM2_IRL0 ++#define IFX_DMA_CH1_INT INT_NUM_IM2_IRL1 ++#define IFX_DMA_CH2_INT INT_NUM_IM2_IRL2 ++#define IFX_DMA_CH3_INT INT_NUM_IM2_IRL3 ++#define IFX_DMA_CH4_INT INT_NUM_IM2_IRL4 ++#define IFX_DMA_CH5_INT INT_NUM_IM2_IRL5 ++#define IFX_DMA_CH6_INT INT_NUM_IM2_IRL6 ++#define IFX_DMA_CH7_INT INT_NUM_IM2_IRL7 ++#define IFX_DMA_CH8_INT INT_NUM_IM2_IRL8 ++#define IFX_DMA_CH9_INT INT_NUM_IM2_IRL9 ++#define IFX_DMA_CH10_INT INT_NUM_IM2_IRL10 ++#define IFX_DMA_CH11_INT INT_NUM_IM2_IRL11 ++#define IFX_DMA_CH12_INT INT_NUM_IM2_IRL25 ++#define IFX_DMA_CH13_INT INT_NUM_IM2_IRL26 ++#define IFX_DMA_CH14_INT INT_NUM_IM2_IRL27 ++#define IFX_DMA_CH15_INT INT_NUM_IM2_IRL28 ++#define IFX_DMA_CH16_INT INT_NUM_IM2_IRL29 ++#define IFX_DMA_CH17_INT INT_NUM_IM1_IRL30 ++#define IFX_DMA_CH18_INT INT_NUM_IM2_IRL16 ++#define IFX_DMA_CH19_INT INT_NUM_IM2_IRL21 ++#define IFX_DMA_CH20_INT INT_NUM_IM4_IRL0 ++#define IFX_DMA_CH21_INT INT_NUM_IM4_IRL1 ++#define IFX_DMA_CH22_INT INT_NUM_IM4_IRL2 ++#define IFX_DMA_CH23_INT INT_NUM_IM4_IRL3 ++#define IFX_DMA_CH24_INT INT_NUM_IM4_IRL4 ++#define IFX_DMA_CH25_INT INT_NUM_IM4_IRL5 ++#define IFX_DMA_CH26_INT INT_NUM_IM4_IRL6 ++#define IFX_DMA_CH27_INT INT_NUM_IM4_IRL7 ++#define IFX_DMA_FCC_INT INT_NUM_IM0_IRL13 ++ ++#define IFX_PPE_MBOX_INT0 INT_NUM_IM2_IRL23 ++#define IFX_PPE_MBOX_INT1 INT_NUM_IM2_IRL24 ++#define IFX_PPE_MBOX_INT2 INT_NUM_IM1_IRL29 ++#define IFX_PPE_QSB_INT INT_NUM_IM1_IRL31 ++ ++#define IFX_GE_SW_INT INT_NUM_IM1_IRL16 ++ ++#define IFX_GPHY_CD_INT INT_NUM_IM3_IRL17 ++#define IFX_GPHY_INT INT_NUM_IM3_IRL18 ++ ++#define IFX_EIU_IR0 INT_NUM_IM4_IRL30 /* 158 */ ++#define IFX_EIU_IR1 INT_NUM_IM3_IRL31 /* 127 */ ++#define IFX_EIU_IR2 INT_NUM_IM1_IRL26 /* 58 */ ++#define IFX_EIU_IR3 INT_NUM_IM1_IRL0 /* 32 */ ++#define IFX_EIU_IR4 INT_NUM_IM1_IRL1 /* 33 */ ++#define IFX_EIU_IR5 INT_NUM_IM1_IRL2 /* 34 */ ++ ++#define IFX_EIU_IR6 INT_NUM_IM2_IRL30 /* 94 */ ++#define IFX_SI_EIU_IR IFX_EIU_IR6 ++ ++#define IFX_MPS_IR0 INT_NUM_IM4_IRL14 ++#define IFX_MPS_IR1 INT_NUM_IM4_IRL15 ++#define IFX_MPS_IR2 INT_NUM_IM4_IRL16 ++#define IFX_MPS_IR3 INT_NUM_IM4_IRL17 ++#define IFX_MPS_IR4 INT_NUM_IM4_IRL18 ++#define IFX_MPS_IR5 INT_NUM_IM4_IRL19 ++#define IFX_MPS_IR6 INT_NUM_IM4_IRL20 ++#define IFX_MPS_IR7 INT_NUM_IM4_IRL21 ++#define IFX_MPS_IR8 INT_NUM_IM4_IRL22 ++#define IFX_MPS_SEMAPHORE_IR IFX_MPS_IR7 ++#define IFX_MPS_GLOBAL_IR IFX_MPS_IR8 ++ ++#define IFX_RTI_8KHZ_IR INT_NUM_IM2_IRL31 ++ ++#define IFX_GPTU_TC1A INT_NUM_IM3_IRL22 ++#define IFX_GPTU_TC1B INT_NUM_IM3_IRL23 ++#define IFX_GPTU_TC2A INT_NUM_IM3_IRL24 ++#define IFX_GPTU_TC2B INT_NUM_IM3_IRL25 ++#define IFX_GPTU_TC3A INT_NUM_IM3_IRL26 ++#define IFX_GPTU_TC3B INT_NUM_IM3_IRL27 ++ ++#define IFX_MC_IR INT_NUM_IM3_IRL28 ++ ++#define IFX_EBU_IR INT_NUM_IM0_IRL22 ++ ++#define IFX_PCI_IR INT_NUM_IM1_IRL17 ++#define IFX_PCI_WRIR INT_NUM_IM1_IRL18 ++ ++#define IFX_PCM_TXIR INT_NUM_IM1_IRL19 ++#define IFX_PCM_RXIR INT_NUM_IM1_IRL20 ++ ++#define IFX_PMCIR INT_NUM_IM4_IRL31 ++ ++#define IFX_SBIU_ERRIR INT_NUM_IM1_IRL27 ++ ++#define IFX_SSC_RIR INT_NUM_IM0_IRL14 ++#define IFX_SSC_TIR INT_NUM_IM0_IRL15 ++#define IFX_SSC_EIR INT_NUM_IM0_IRL16 ++#define IFX_SSC_FIR INT_NUM_IM0_IRL17 ++ ++#define IFX_MMC_CONTROLLER_INTR0_IRQ INT_NUM_IM0_IRL18 ++#define IFX_MMC_CONTROLLER_INTR1_IRQ INT_NUM_IM0_IRL19 ++#define IFX_MMC_CONTROLLER_SDIO_I_IRQ INT_NUM_IM0_IRL20 ++ ++#define IFX_USB0_IR INT_NUM_IM1_IRL22 ++#define IFX_USB1_IR INT_NUM_IM1_IRL16 ++#define IFX_USB0_OCIR INT_NUM_IM1_IRL28 ++#define IFX_USB1_OCIR INT_NUM_IM1_IRL24 // same as IFX_DSL_AFEOVL_IR ++#define IFX_USB_INT IFX_USB0_IR ++#define IFX_USB_OC_INT IFX_USB0_OCIR ++ ++#define IFX_WDT_AEIR INT_NUM_IM4_IRL24 ++ ++#define IFX_OVD_INT INT_NUM_IM3_IRL15 ++#define IFX_PSU_INT INT_NUM_IM3_IRL30 ++ ++#define IFX_USIF_EIR_INT INT_NUM_IM3_IRL3 ++#define IFX_USIF_STA_INT INT_NUM_IM3_IRL4 ++#define IFX_USIF_AB_INT INT_NUM_IM3_IRL5 ++#define IFX_USIF_WKP_INT INT_NUM_IM3_IRL6 ++#define IFX_USIF_TX_INT INT_NUM_IM0_IRL21 ++#define IFX_USIF_RX_INT INT_NUM_IM3_IRL21 ++ ++#define IFX_AHB1S_BUS_ERROR INT_NUM_IM3_IRL1 ++ ++ ++ ++#endif // VR9_IRQ_H ++ +diff --git a/arch/mips/include/asm/ifx/vr9/model.h b/arch/mips/include/asm/ifx/vr9/model.h +new file mode 100644 +index 0000000..ba11b36 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/vr9/model.h +@@ -0,0 +1,54 @@ ++/****************************************************************************** ++** ++** FILE NAME : model.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : header file for VR9 ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef VR9_MODEL_H ++#define VR9_MODEL_H ++/****************************************************************************** ++ Copyright (c) 2002, Infineon Technologies. All rights reserved. ++ ++ No Warranty ++ Because the program is licensed free of charge, there is no warranty for ++ the program, to the extent permitted by applicable law. Except when ++ otherwise stated in writing the copyright holders and/or other parties ++ provide the program "as is" without warranty of any kind, either ++ expressed or implied, including, but not limited to, the implied ++ warranties of merchantability and fitness for a particular purpose. The ++ entire risk as to the quality and performance of the program is with ++ you. should the program prove defective, you assume the cost of all ++ necessary servicing, repair or correction. ++ ++ In no event unless required by applicable law or agreed to in writing ++ will any copyright holder, or any other party who may modify and/or ++ redistribute the program as permitted above, be liable to you for ++ damages, including any general, special, incidental or consequential ++ damages arising out of the use or inability to use the program ++ (including but not limited to loss of data or data being rendered ++ inaccurate or losses sustained by you or third parties or a failure of ++ the program to operate with any other programs), even if such holder or ++ other party has been advised of the possibility of such damages. ++******************************************************************************/ ++#define BOARD_SYSTEM_TYPE "VR9" ++#define SYSTEM_MODEL_NAME "VR9 First Version" ++#endif +diff --git a/arch/mips/include/asm/ifx/vr9/vr9.h b/arch/mips/include/asm/ifx/vr9/vr9.h +new file mode 100644 +index 0000000..bca6f00 +--- /dev/null ++++ b/arch/mips/include/asm/ifx/vr9/vr9.h +@@ -0,0 +1,1785 @@ ++/****************************************************************************** ++** ++** FILE NAME : vr9.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : header file for VR9 ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef VR9_H ++#define VR9_H ++ ++#include ++ ++/****************************************************************************** ++ Copyright (c) 2002, Infineon Technologies. All rights reserved. ++ ++ No Warranty ++ Because the program is licensed free of charge, there is no warranty for ++ the program, to the extent permitted by applicable law. Except when ++ otherwise stated in writing the copyright holders and/or other parties ++ provide the program "as is" without warranty of any kind, either ++ expressed or implied, including, but not limited to, the implied ++ warranties of merchantability and fitness for a particular purpose. The ++ entire risk as to the quality and performance of the program is with ++ you. should the program prove defective, you assume the cost of all ++ necessary servicing, repair or correction. ++ ++ In no event unless required by applicable law or agreed to in writing ++ will any copyright holder, or any other party who may modify and/or ++ redistribute the program as permitted above, be liable to you for ++ damages, including any general, special, incidental or consequential ++ damages arising out of the use or inability to use the program ++ (including but not limited to loss of data or data being rendered ++ inaccurate or losses sustained by you or third parties or a failure of ++ the program to operate with any other programs), even if such holder or ++ other party has been advised of the possibility of such damages. ++******************************************************************************/ ++#define MACH_GROUP_IFX MACH_GROUP_VR9 ++#define MACH_TYPE_IFX MACH_VR9 ++ ++ ++/***********************************************************************/ ++/* Module : WDT register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_WDT (KSEG1 | 0x1F880000) ++ ++/***Watchdog Timer Control Register ***/ ++#define IFX_WDT_CR ((volatile u32*)(IFX_WDT + 0x03F0)) ++#define IFX_WDT_CR_GEN (1 << 31) ++#define IFX_WDT_CR_DSEN (1 << 30) ++#define IFX_WDT_CR_LPEN (1 << 29) ++#define IFX_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1)) ++#define IFX_WDT_CR_PWL_SET(value) (((( 1 << 2) - 1) & (value)) << 26) ++#define IFX_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1)) ++#define IFX_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24) ++#define IFX_WDT_CR_PW_GET(value) (((value) >> 16) & ((1 << 8) - 1)) ++#define IFX_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16) ++#define IFX_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1)) ++#define IFX_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0) ++ ++/***Watchdog Timer Status Register***/ ++#define IFX_WDT_SR ((volatile u32*)(IFX_WDT + 0x03F8)) ++#define IFX_WDT_SR_EN (1 << 31) ++#define IFX_WDT_SR_AE (1 << 30) ++#define IFX_WDT_SR_PRW (1 << 29) ++#define IFX_WDT_SR_EXP (1 << 28) ++#define IFX_WDT_SR_PWD (1 << 27) ++#define IFX_WDT_SR_DS (1 << 26) ++#define IFX_WDT_SR_VALUE_GET(value) (((value) >> 0) & ((1 << 16) - 1)) ++#define IFX_WDT_SR_VALUE_SET(value) (((( 1 << 16) - 1) & (value)) << 0) ++ ++ ++/***********************************************************************/ ++/* Module : RCU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_RCU (KSEG1 | 0x1F203000) ++ ++/* Reset Request Register */ ++#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) ++#define IFX_RCU_RST_REQ_HOT_RST 0x00000001 /* Hot reset, domain 0*/ ++ ++#define IFX_RCU_RST_STAT ((volatile u32*)(IFX_RCU + 0x0014)) ++#define IFX_RCU_USB0_CFG ((volatile u32*)(IFX_RCU + 0x0018)) ++#define IFX_RCU_GPIO_STRAP ((volatile u32*)(IFX_RCU + 0x001C)) ++#define IFX_RCU_GPHY0_FW_ADDR ((volatile u32*)(IFX_RCU + 0x0020)) ++#define IFX_RCU_SLIC_USB_RST_STAT ((volatile u32*)(IFX_RCU + 0x0024)) ++#define IFX_RCU_PCI_BOOT_READY ((volatile u32*)(IFX_RCU + 0x0028)) ++#define IFX_RCU_PPE_CONF ((volatile u32*)(IFX_RCU + 0x002C)) ++#define IFX_RCU_PCIE_PHY_CON_STAT ((volatile u32*)(IFX_RCU + 0x0030)) ++#define IFX_RCU_USB1_CFG ((volatile u32*)(IFX_RCU + 0x0034)) ++#define IFX_RCU_USB_AFE_CFG_1A ((volatile u32*)(IFX_RCU + 0x0038)) ++#define IFX_RCU_USB_AFE_CFG_1B ((volatile u32*)(IFX_RCU + 0x003C)) ++#define IFX_RCU_USB_AFE_CFG_2A ((volatile u32*)(IFX_RCU + 0x0040)) ++#define IFX_RCU_USB_AFE_CFG_2B ((volatile u32*)(IFX_RCU + 0x0044)) ++#define IFX_RCU_SLIC_USB_RST_REQ ((volatile u32*)(IFX_RCU + 0x0048)) ++ ++/* AHB Endian Register */ ++#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) ++ ++#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ ++#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ ++#define IFX_RCU_AHB_BE_USIF 0x00000004 /* Configure AHB slave port that connects to USIF in big endian */ ++#define IFX_RCU_AHB_BE_XBAR_S 0x00000008 /* Configure AHB slave port that connects to XBAR in big endian */ ++#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ ++#define IFX_RCU_AHB_BE_PCIE_DBI 0x00000020 /* Configure DBI module in big endian*/ ++#define IFX_RCU_AHB_BE_DC_PDI 0x00000040 /* Configure DC PDI module in big endian*/ ++#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ ++ ++#define IFX_RCU_CPU_CFG ((volatile u32*)(IFX_RCU + 0x0060)) ++#define IFX_RCU_GPHY1_FW_ADDR ((volatile u32*)(IFX_RCU + 0x0068)) ++ ++/* Reset Request Register */ ++#define IFX_RCU_RST_REQ_GPHY0 (1 << 31) ++#define IFX_RCU_RST_REQ_SRST (1 << 30) ++#define IFX_RCU_RST_REQ_GPHY1 (1 << 29) ++#define IFX_RCU_RST_REQ_SWITCH (1 << 21) ++#define IFX_RCU_RST_REQ_MIPS0 (1 << 1) ++ ++/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */ ++#define IFX_RCU_RST_REQ_ALL (IFX_RCU_RST_REQ_SRST | IFX_RCU_RST_REQ_GPHY0 | IFX_RCU_RST_REQ_GPHY1 | IFX_RCU_RST_REQ_MIPS0) ++ ++#define IFX_RCU_RST_REQ_DFE (1 << 7) ++#define IFX_RCU_RST_REQ_AFE (1 << 11) ++#define IFX_RCU_RST_REQ_ARC_JTAG (1 << 20) ++ ++ ++/***********************************************************************/ ++/* Module : BCU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_BCU_BASE_ADDR (KSEG1 | 0x1E100000) ++#define IFX_SLAVE_BCU_BASE_ADDR (KSEG1 | 0x1C200400) ++ ++/***BCU Control Register (0010H)***/ ++#define IFX_BCU_CON ((volatile u32*)(0x0010 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_CON ((volatile u32*)(0x0010 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_STARVATION_MASK (0xFF << 24) ++#define IFX_BCU_STARVATION_SHIFT 24 ++#define IFX_BCU_TOUT_MASK 0xFFFF ++#define IFX_BCU_CON_SPC(value) (((( 1 << 8) - 1) & (value)) << 24) ++#define IFX_BCU_CON_SPE (1 << 19) ++#define IFX_BCU_CON_PSE (1 << 18) ++#define IFX_BCU_CON_DBG (1 << 16) ++#define IFX_BCU_CON_TOUT(value) (((( 1 << 16) - 1) & (value)) << 0) ++ ++/***BCU Error Control Capture Register (0020H)***/ ++#define IFX_BCU_ECON ((volatile u32*)(0x0020 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_ECON ((volatile u32*)(0x0020 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_ECON_TAG(value) (((( 1 << 4) - 1) & (value)) << 24) ++#define IFX_BCU_ECON_RDN (1 << 23) ++#define IFX_BCU_ECON_WRN (1 << 22) ++#define IFX_BCU_ECON_SVM (1 << 21) ++#define IFX_BCU_ECON_ACK(value) (((( 1 << 2) - 1) & (value)) << 19) ++#define IFX_BCU_ECON_ABT (1 << 18) ++#define IFX_BCU_ECON_RDY (1 << 17) ++#define IFX_BCU_ECON_TOUT (1 << 16) ++#define IFX_BCU_ECON_ERRCNT(value) (((( 1 << 16) - 1) & (value)) << 0) ++#define IFX_BCU_ECON_OPC(value) (((( 1 << 4) - 1) & (value)) << 28) ++ ++/***BCU Error Address Capture Register (0024 H)***/ ++#define IFX_BCU_EADD ((volatile u32*)(0x0024 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_EADD ((volatile u32*)(0x0024 + IFX_SLAVE_BCU_BASE_ADDR)) ++ ++/***BCU Error Data Capture Register (0028H)***/ ++#define IFX_BCU_EDAT ((volatile u32*)(0x0028 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_EDAT ((volatile u32*)(0x0028 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_IRNICR ((volatile u32*)(0x00FC + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_IRNICR ((volatile u32*)(0x00FC + IFX_SLAVE_BCU_BASE_ADDR)) ++#define IFX_BCU_IRNCR ((volatile u32*)(0x00F8 + IFX_BCU_BASE_ADDR)) ++#define IFX_SLAVE_BCU_IRNCR ((volatile u32*)(0x00F8 + IFX_SLAVE_BCU_BASE_ADDR)) ++ ++ ++/***********************************************************************/ ++/* Module : HSNAND register address and bits */ ++/***********************************************************************/ ++#define IFX_HSNAND_BASE (KSEG1 | 0x1E100400) ++ ++/****** HSNAND REGISTERS *******/ ++#define IFX_NDAC_CTL1 ((volatile u32*)(0x0010 + IFX_HSNAND_BASE)) ++#define IFX_NDAC_CTL2 ((volatile u32*)(0x0014 + IFX_HSNAND_BASE)) ++#define IFX_BASE_A ((volatile u32*)(0x0018 + IFX_HSNAND_BASE)) ++#define IFX_RX_CNT ((volatile u32*)(0x001C + IFX_HSNAND_BASE)) ++#define IFX_DPLUS_CTRL ((volatile u32*)(0x0020 + IFX_HSNAND_BASE)) ++#define IFX_HSNAND_INTR_MASK_CTRL ((volatile u32*)(0x0024 + IFX_HSNAND_BASE)) ++#define IFX_HSNAND_INTR_STAT ((volatile u32*)(0x0028 + IFX_HSNAND_BASE)) ++#define IFX_HSMD_CTRL ((volatile u32*)(0x0030 + IFX_HSNAND_BASE)) ++#define IFX_CS_BASE_A ((volatile u32*)(0x0034 + IFX_HSNAND_BASE)) ++#define IFX_NAND_INFO ((volatile u32*)(0X0038 + IFX_HSNAND_BASE)) ++ ++#define IFX_HSNAND_CE_SEL (0xF<<3) ++#define IFX_HSNAND_CE_SEL_S 3 ++#define IFX_HSNAND_CE_SEL_NONE 0 ++#define IFX_HSNAND_CE_SEL_CS0 1 ++#define IFX_HSNAND_CE_SEL_CS1 2 ++#define IFX_HSNAND_CE_SEL_CS2 4 ++#define IFX_HSNAND_CE_SEL_CS3 8 ++ ++#define IFX_HSNAND_FSM (1<<2) ++#define IFX_HSNAND_FSM_S 2 ++enum { ++ IFX_HSNAND_FSM_DISABLED = 0, ++ IFX_HSNAND_FSM_ENABLED, ++}; ++ ++#define IFX_HSNAND_ENR (3<<0) ++#define IFX_HSNAND_ENR_S 0 ++enum { ++ IFX_HSNAND_ENR_XIP = 0, ++ IFX_HSNAND_ENR_HSDMA, ++ IFX_HSNAND_ENR_IO, ++ IFX_HSNAND_ENR_NONE ++}; ++ ++#define IFX_HSNAND_XFER_SEL (7<<0) ++#define IFX_HSNAND_XFER_SEL_S 7 ++enum { ++ IFX_HSNAND_NO_XFER = 0, ++ IFX_HSNAND_START_XFER ++}; ++ ++/***********************************************************************/ ++/* Module : MEI register address and bits */ ++/***********************************************************************/ ++ ++#define IFXMIPS_MEI_BASE_ADDR (KSEG1 | 0x1E116000) ++#define IFX_DFE_LDST_BASE_ADDR (KSEG1 | 0x1EF00000) ++ ++/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/ ++#if 0 ++#define MEI_DATA_XFR ((volatile u32*)(0x0000 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_VERSION ((volatile u32*)(0x0004 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_ARC_GP_STAT ((volatile u32*)(0x0008 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_DATA_XFR_STAT ((volatile u32*)(0x000C + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XFR_ADDR ((volatile u32*)(0x0010 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_MAX_WAIT ((volatile u32*)(0x0014 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_TO_ARC_INT ((volatile u32*)(0x0018 + IFXMIPS_MEI_BASE_ADDR)) ++#define ARC_TO_MEI_INT ((volatile u32*)(0x0004 + IFXMIPS_MEI_BASE_ADDR)) ++#define ARC_TO_MEI_INT_MASK ((volatile u32*)(0x0020 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_DEBUG_WAD ((volatile u32*)(0x0024 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_DEBUG_RAD ((volatile u32*)(0x0028 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_DEBUG_DATA ((volatile u32*)(0x002C + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_DEBUG_DEC ((volatile u32*)(0x0030 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_CONFIG ((volatile u32*)(0x0034 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_RST_CONTROL ((volatile u32*)(0x0038 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_DBG_MASTER ((volatile u32*)(0x003C + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_CLK_CONTROL ((volatile u32*)(0x0040 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_BIST_CONTROL ((volatile u32*)(0x0044 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_BIST_STAT ((volatile u32*)(0x0048 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XDATA_BASE_SH ((volatile u32*)(0x004c + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XDATA_BASE ((volatile u32*)(0x0050 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR_BASE ((volatile u32*)(0x0054 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR0 ((volatile u32*)(0x0054 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR1 ((volatile u32*)(0x0058 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR2 ((volatile u32*)(0x005C + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR3 ((volatile u32*)(0x0060 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR4 ((volatile u32*)(0x0064 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR5 ((volatile u32*)(0x0068 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR6 ((volatile u32*)(0x006C + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR7 ((volatile u32*)(0x0070 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR8 ((volatile u32*)(0x0074 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR9 ((volatile u32*)(0x0078 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR10 ((volatile u32*)(0x007C + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR11 ((volatile u32*)(0x0080 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR12 ((volatile u32*)(0x0084 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR13 ((volatile u32*)(0x0088 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR14 ((volatile u32*)(0x008C + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR15 ((volatile u32*)(0x0090 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR16 ((volatile u32*)(0x0094 + IFXMIPS_MEI_BASE_ADDR)) ++ ++ ++#define MEI_VERSION ((volatile u32*)(0x0000 + IFXMIPS_MEI_BASE_ADDR)) ++#define ARC_TO_MEI_INT ((volatile u32*)(0x0004 + IFXMIPS_MEI_BASE_ADDR)) ++#define ARC_TO_MEI_INT_MASK ((volatile u32*)(0x0008 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_TO_ARC_INT ((volatile u32*)(0x000C + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_ME2ARC_STAT ((volatile u32*)(0x0010 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_CLK_CONTROL ((volatile u32*)(0x0014 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_RST_CONTROL ((volatile u32*)(0x0018 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_CHIP_CONFIG ((volatile u32*)(0x001C + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_DBG_MASTER ((volatile u32*)(0x0020 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_DEBUG_DEC ((volatile u32*)(0x0024 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_DBG_PORT_SEL ((volatile u32*)(0x0028 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_DEBUG_RAD ((volatile u32*)(0x002C + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_DEBUG_WAD ((volatile u32*)(0x0030 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_DEBUG_DATA ((volatile u32*)(0x0034 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_DX_PORT_SEL ((volatile u32*)(0x0038 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XFR_ADDR ((volatile u32*)(0x003C + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_DATA_XFR ((volatile u32*)(0x0040 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_DATA_XFR_STAT ((volatile u32*)(0x0044 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_MAX_WAIT ((volatile u32*)(0x0048 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_ARC_GP_STAT ((volatile u32*)(0x004C + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XDATA_BASE_SH ((volatile u32*)(0x0050 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XDATA_BASE ((volatile u32*)(0x0054 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR_BASE ((volatile u32*)(0x0058 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR0 ((volatile u32*)(0x0058 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR1 ((volatile u32*)(0x005C + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR2 ((volatile u32*)(0x0060 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR3 ((volatile u32*)(0x0064 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR4 ((volatile u32*)(0x0068 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR5 ((volatile u32*)(0x006C + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR6 ((volatile u32*)(0x0070 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR7 ((volatile u32*)(0x0074 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR8 ((volatile u32*)(0x0078 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR9 ((volatile u32*)(0x007C + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR10 ((volatile u32*)(0x0080 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR11 ((volatile u32*)(0x0084 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR12 ((volatile u32*)(0x0088 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR13 ((volatile u32*)(0x008C + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR14 ((volatile u32*)(0x0090 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR15 ((volatile u32*)(0x0094 + IFXMIPS_MEI_BASE_ADDR)) ++#define MEI_XMEM_BAR16 ((volatile u32*)(0x0098 + IFXMIPS_MEI_BASE_ADDR)) ++//#else ++#define ME_VERSION ((volatile u32*)(0x0000 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_ARC2ME_STAT ((volatile u32*)(0x0004 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_ARC2ME_MASK ((volatile u32*)(0x0008 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_ME2ARC_INT ((volatile u32*)(0x000C + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_ME2ARC_STAT ((volatile u32*)(0x0010 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_CLK_CTRL ((volatile u32*)(0x0014 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_RST_CTRL ((volatile u32*)(0x0018 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_CHIP_CONFIG ((volatile u32*)(0x001C + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_DBG_MASTER ((volatile u32*)(0x0020 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_DBG_DECODE ((volatile u32*)(0x0024 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_DBG_PORT_SEL ((volatile u32*)(0x0028 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_DBG_RD_AD ((volatile u32*)(0x002C + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_DBG_WR_AD ((volatile u32*)(0x0030 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_DBG_DATA ((volatile u32*)(0x0034 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_DX_PORT_SEL ((volatile u32*)(0x0038 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_DX_AD ((volatile u32*)(0x003C + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_DX_DATA ((volatile u32*)(0x0040 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_DX_STAT ((volatile u32*)(0x0044 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_DX_MWS ((volatile u32*)(0x0048 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_ARC_GP_STAT ((volatile u32*)(0x004C + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_XDATA_BASE_SH ((volatile u32*)(0x0050 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_XDATA_BASE ((volatile u32*)(0x0054 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_XMEM_BAR_BASE ((volatile u32*)(0x0058 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_XMEM_BAR0 ((volatile u32*)(0x0058 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_XMEM_BAR1 ((volatile u32*)(0x005C + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_XMEM_BAR2 ((volatile u32*)(0x0060 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_XMEM_BAR3 ((volatile u32*)(0x0064 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_XMEM_BAR4 ((volatile u32*)(0x0068 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_XMEM_BAR5 ((volatile u32*)(0x006C + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_XMEM_BAR6 ((volatile u32*)(0x0070 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_XMEM_BAR7 ((volatile u32*)(0x0074 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_XMEM_BAR8 ((volatile u32*)(0x0078 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_XMEM_BAR9 ((volatile u32*)(0x007C + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_XMEM_BAR10 ((volatile u32*)(0x0080 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_XMEM_BAR11 ((volatile u32*)(0x0084 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_XMEM_BAR12 ((volatile u32*)(0x0088 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_XMEM_BAR13 ((volatile u32*)(0x008C + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_XMEM_BAR14 ((volatile u32*)(0x0090 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_XMEM_BAR15 ((volatile u32*)(0x0094 + IFXMIPS_MEI_BASE_ADDR)) ++#define ME_XMEM_BAR16 ((volatile u32*)(0x0098 + IFXMIPS_MEI_BASE_ADDR)) ++#endif ++ ++ ++/***********************************************************************/ ++/* Module : GPIO register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_GPIO (KSEG1 | 0x1E100B00) ++ ++/***Port 0 Data Output Register (0010H)***/ ++#define IFX_GPIO_P0_OUT ((volatile u32 *)(IFX_GPIO + 0x0010)) ++/***Port 1 Data Output Register (0040H)***/ ++#define IFX_GPIO_P1_OUT ((volatile u32 *)(IFX_GPIO + 0x0040)) ++/***Port 2 Data Output Register (0070H)***/ ++#define IFX_GPIO_P2_OUT ((volatile u32 *)(IFX_GPIO + 0x0070)) ++/***Port 3 Data Output Register (00A0H)***/ ++#define IFX_GPIO_P3_OUT ((volatile u32 *)(IFX_GPIO + 0x00A0)) ++/***Port 0 Data Input Register (0014H)***/ ++#define IFX_GPIO_P0_IN ((volatile u32 *)(IFX_GPIO + 0x0014)) ++/***Port 1 Data Input Register (0044H)***/ ++#define IFX_GPIO_P1_IN ((volatile u32 *)(IFX_GPIO + 0x0044)) ++/***Port 2 Data Input Register (0074H)***/ ++#define IFX_GPIO_P2_IN ((volatile u32 *)(IFX_GPIO + 0x0074)) ++/***Port 3 Data Input Register (00A4H)***/ ++#define IFX_GPIO_P3_IN ((volatile u32 *)(IFX_GPIO + 0x00A4)) ++/***Port 0 Direction Register (0018H)***/ ++#define IFX_GPIO_P0_DIR ((volatile u32 *)(IFX_GPIO + 0x0018)) ++/***Port 1 Direction Register (0048H)***/ ++#define IFX_GPIO_P1_DIR ((volatile u32 *)(IFX_GPIO + 0x0048)) ++/***Port 2 Direction Register (0078H)***/ ++#define IFX_GPIO_P2_DIR ((volatile u32 *)(IFX_GPIO + 0x0078)) ++/***Port 3 Direction Register (0048H)***/ ++#define IFX_GPIO_P3_DIR ((volatile u32 *)(IFX_GPIO + 0x00A8)) ++/***Port 0 Alternate Function Select Register 0 (001C H) ***/ ++#define IFX_GPIO_P0_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x001C)) ++/***Port 1 Alternate Function Select Register 0 (004C H) ***/ ++#define IFX_GPIO_P1_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x004C)) ++/***Port 2 Alternate Function Select Register 0 (007C H) ***/ ++#define IFX_GPIO_P2_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x007C)) ++/***Port 3 Alternate Function Select Register 0 (00AC H) ***/ ++#define IFX_GPIO_P3_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x00AC)) ++/***Port 0 Alternate Function Select Register 1 (0020 H) ***/ ++#define IFX_GPIO_P0_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0020)) ++/***Port 1 Alternate Function Select Register 0 (0050 H) ***/ ++#define IFX_GPIO_P1_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0050)) ++/***Port 2 Alternate Function Select Register 0 (0080 H) ***/ ++#define IFX_GPIO_P2_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0080)) ++/***Port 3 Alternate Function Select Register 0 (0064 H) ***/ ++#define IFX_GPIO_P3_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0064)) ++/***Port 0 Open Drain Control Register (0024H)***/ ++#define IFX_GPIO_P0_OD ((volatile u32 *)(IFX_GPIO + 0x0024)) ++/***Port 1 Open Drain Control Register (0054H)***/ ++#define IFX_GPIO_P1_OD ((volatile u32 *)(IFX_GPIO + 0x0054)) ++/***Port 2 Open Drain Control Register (0084H)***/ ++#define IFX_GPIO_P2_OD ((volatile u32 *)(IFX_GPIO + 0x0084)) ++/***Port 3 Open Drain Control Register (0034H)***/ ++#define IFX_GPIO_P3_OD ((volatile u32 *)(IFX_GPIO + 0x0034)) ++/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/ ++#define IFX_GPIO_P0_STOFF ((volatile u32 *)(IFX_GPIO + 0x0028)) ++/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/ ++#define IFX_GPIO_P1_STOFF ((volatile u32 *)(IFX_GPIO + 0x0058)) ++/***Port 2 Input Schmitt-Trigger Off Register (0088 H) ***/ ++#define IFX_GPIO_P2_STOFF ((volatile u32 *)(IFX_GPIO + 0x0088)) ++/***Port 3 Input Schmitt-Trigger Off Register (0094 H) ***/ ++ ++/***Port 0 Pull Up/Pull Down Select Register (002C H)***/ ++#define IFX_GPIO_P0_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x002C)) ++/***Port 1 Pull Up/Pull Down Select Register (005C H)***/ ++#define IFX_GPIO_P1_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x005C)) ++/***Port 2 Pull Up/Pull Down Select Register (008C H)***/ ++#define IFX_GPIO_P2_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x008C)) ++/***Port 3 Pull Up/Pull Down Select Register (0038 H)***/ ++#define IFX_GPIO_P3_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x0038)) ++/***Port 0 Pull Up Device Enable Register (0030 H)***/ ++#define IFX_GPIO_P0_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0030)) ++/***Port 1 Pull Up Device Enable Register (0060 H)***/ ++#define IFX_GPIO_P1_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0060)) ++/***Port 2 Pull Up Device Enable Register (0090 H)***/ ++#define IFX_GPIO_P2_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0090)) ++/***Port 3 Pull Up Device Enable Register (003c H)***/ ++#define IFX_GPIO_P3_PUDEN ((volatile u32 *)(IFX_GPIO + 0x003C)) ++ ++ ++ ++/***********************************************************************/ ++/* Module : CGU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_CGU (KSEG1 | 0x1F103000) ++ ++/***CGU Clock PLL0 ***/ ++#define IFX_CGU_PLL0_CFG ((volatile u32*)(IFX_CGU + 0x0004)) ++/***CGU Clock PLL1 ***/ ++#define IFX_CGU_PLL1_CFG ((volatile u32*)(IFX_CGU + 0x0008)) ++/***CGU Clock PLL2 ***/ ++#define IFX_CGU_PLL2_CFG ((volatile u32*)(IFX_CGU + 0x0060)) ++/***CGU Clock SYS Mux Register***/ ++#define IFX_CGU_SYS ((volatile u32*)(IFX_CGU + 0x000C)) ++/***CGU CGU Clock Frequency Select Register***/ ++#define IFX_CGU_CLKFSR ((volatile u32*)(IFX_CGU + 0x0010)) ++/**Update CGU Register***/ ++#define IFX_CGU_UPDATE ((volatile u32*)(IFX_CGU + 0x0020)) ++/***CGU Interface Clock Control Register***/ ++#define IFX_CGU_IF_CLK ((volatile u32*)(IFX_CGU + 0x0024)) ++/***CGU PCI Clock Control Register**/ ++#define IFX_CGU_PCI_CR ((volatile u32*)(IFX_CGU + 0x0038)) ++ ++#define IFX_PCI_CLK_SHIFT 20 ++#define IFX_PCI_CLK_MASK (0x1F << IFX_PCI_CLK_SHIFT) ++#define IFX_PCI_33MHZ (0xe << IFX_PCI_CLK_SHIFT) ++#define IFX_PCI_60MHZ (0x7 << IFX_PCI_CLK_SHIFT) ++#define IFX_PCI_INTERNAL_CLK_SRC 0x00010000 /* Internal means output */ ++ ++#define IFX_PCI_CLK_FROM_CGU 0x80000000 ++#define IFX_PCI_CLK_RESET_FROM_CGU 0x40000000 ++#define IFX_PCI_DELAY_SHIFT 21 ++#define IFX_PCI_DELAY_MASK (0x7 << IFX_PCI_DELAY_SHIFT) ++ ++/***GPHY1 Configuration Register**/ ++#define IFX_GPHY1_CFG ((volatile u32*)(IFX_CGU + 0x0040)) ++#define IFX_SSC_HIGH_BAUD_DELAY_MASK 0x00000060 ++#define IFX_SSC_HIGH_BAUD_DELAY_TWO_HALF_CLOCK 0x00000020 ++#define IFX_SSC_HIGH_BAUD_DELAY_THREE_CLOCK 0x00000040 ++#define IFX_SSC_HIGH_BAUD_DELAY_THREE_HALF_CLOCK 0x00000060 ++ ++ ++/***********************************************************************/ ++/* Module : MCD register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_MCD (KSEG1 | 0x1F106000) ++ ++/***Manufacturer Identification Register***/ ++#define IFX_MCD_MANID ((volatile u32*)(IFX_MCD + 0x0024)) ++#define IFX_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5) ++ ++/***Chip Identification Register***/ ++#define IFX_MCD_CHIPID ((volatile u32*)(IFX_MCD + 0x0028)) ++#define IFX_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) ++#define IFX_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) ++#define IFX_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1)) ++#define IFX_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12) ++#define IFX_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1)) ++#define IFX_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1) ++ ++#define IFX_CHIPID_STANDARD 0x00EB ++#define IFX_CHIPID_YANGTSE 0x00ED ++ ++/***Redesign Tracing Identification Register***/ ++#define IFX_MCD_RTID ((volatile u32*)(IFX_MCD + 0x002C)) ++#define IFX_MCD_RTID_LC (1 << 15) ++#define IFX_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0) ++ ++ ++ ++/***********************************************************************/ ++/* Module : EBU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_EBU (KSEG1 | 0x1E105300) ++ ++/***EBU Clock Control Register***/ ++#define IFX_EBU_CLC ((volatile u32*)(IFX_EBU + 0x0000)) ++#define IFX_EBU_CLC_DISS (1 << 1) ++#define IFX_EBU_CLC_DISR (1 << 0) ++ ++#define IFX_EBU_ID ((volatile u32*)(IFX_EBU + 0x0008)) ++ ++/***EBU Global Control Register***/ ++#define IFX_EBU_CON ((volatile u32*)(IFX_EBU + 0x0010)) ++#define IFX_EBU_CON_DTACS(value) (((( 1 << 3) - 1) & (value)) << 20) ++#define IFX_EBU_CON_DTARW(value) (((( 1 << 3) - 1) & (value)) << 16) ++#define IFX_EBU_CON_TOUTC(value) (((( 1 << 8) - 1) & (value)) << 8) ++#define IFX_EBU_CON_ARBMODE(value) (((( 1 << 2) - 1) & (value)) << 6) ++#define IFX_EBU_CON_ARBSYNC (1 << 5) ++ ++/***EBU Address Select Register 0***/ ++#define IFX_EBU_ADDSEL0 ((volatile u32*)(IFX_EBU + 0x0020)) ++#define IFX_EBU_ADDSEL0_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) ++#define IFX_EBU_ADDSEL0_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_EBU_ADDSEL0_MIRRORE (1 << 1) ++#define IFX_EBU_ADDSEL0_REGEN (1 << 0) ++ ++/***EBU Address Select Register 1***/ ++#define IFX_EBU_ADDSEL1 ((volatile u32*)(IFX_EBU + 0x0024)) ++#define IFX_EBU_ADDSEL1_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) ++#define IFX_EBU_ADDSEL1_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_EBU_ADDSEL1_MIRRORE (1 << 1) ++#define IFX_EBU_ADDSEL1_REGEN (1 << 0) ++ ++/***EBU Address Select Register 2***/ ++#define IFX_EBU_ADDSEL2 ((volatile u32*)(IFX_EBU + 0x0028)) ++#define IFX_EBU_ADDSEL2_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) ++#define IFX_EBU_ADDSEL2_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_EBU_ADDSEL2_MIRRORE (1 << 1) ++#define IFX_EBU_ADDSEL2_REGEN (1 << 0) ++ ++/***EBU Address Select Register 3***/ ++#define IFX_EBU_ADDSEL3 ((volatile u32*)(IFX_EBU + 0x002C)) ++#define IFX_EBU_ADDSEL3_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) ++#define IFX_EBU_ADDSEL3_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_EBU_ADDSEL3_MIRRORE (1 << 1) ++#define IFX_EBU_ADDSEL3_REGEN (1 << 0) ++ ++/***EBU Bus Configuration Register 0***/ ++#define IFX_EBU_BUSCON0 ((volatile u32*)(IFX_EBU+ 0x0060)) ++ ++#define IFX_EBU_BUSCON0_CMULT 0x00000003 ++#define IFX_EBU_BUSCON0_CMULT_S 0 ++enum { ++ IFX_EBU_BUSCON0_CMULT1 = 0, ++ IFX_EBU_BUSCON0_CMULT4, ++ IFX_EBU_BUSCON0_CMULT8, ++ IFX_EBU_BUSCON0_CMULT16, /* Default after reset */ ++}; ++ ++#define IFX_EBU_BUSCON0_RECOVC 0x00000000c ++#define IFX_EBU_BUSCON0_RECOVC_S 2 ++enum { ++ IFX_EBU_BUSCON0_RECOVC0 = 0, ++ IFX_EBU_BUSCON0_RECOVC1, ++ IFX_EBU_BUSCON0_RECOVC2, ++ IFX_EBU_BUSCON0_RECOVC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON0_HOLDC 0x00000030 ++#define IFX_EBU_BUSCON0_HOLDC_S 4 ++enum { ++ IFX_EBU_BUSCON0_HOLDC0 = 0, ++ IFX_EBU_BUSCON0_HOLDC1, ++ IFX_EBU_BUSCON0_HOLDC2, ++ IFX_EBU_BUSCON0_HOLDC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON0_WAITRDC 0x000000c0 ++#define IFX_EBU_BUSCON0_WAITRDC_S 6 ++enum { ++ IFX_EBU_BUSCON0_WAITRDC0 = 0, ++ IFX_EBU_BUSCON0_WAITRDC1, ++ IFX_EBU_BUSCON0_WAITRDC2, ++ IFX_EBU_BUSCON0_WAITRDC3, /* Default */ ++}; ++#define IFX_EBU_BUSCON0_WAITWRC 0x00000700 ++#define IFX_EBU_BUSCON0_WAITWRC_S 8 ++enum { ++ IFX_EBU_BUSCON0_WAITWRC0 = 0, ++ IFX_EBU_BUSCON0_WAITWRC1, ++ IFX_EBU_BUSCON0_WAITWRC2, ++ IFX_EBU_BUSCON0_WAITWRC3, ++ IFX_EBU_BUSCON0_WAITWRC4, ++ IFX_EBU_BUSCON0_WAITWRC5, ++ IFX_EBU_BUSCON0_WAITWRC6, ++ IFX_EBU_BUSCON0_WAITWRC7, /* Default */ ++}; ++ ++#define IFX_EBU_BUSCON0_BCGEN 0x00003000 ++#define IFX_EBU_BUSCON0_BCGEN_S 12 ++enum { ++ IFX_EBU_BUSCON0_BCGEN_CS = 0, ++ IFX_EBU_BUSCON0_BCGEN_INTEL, /* Default */ ++ IFX_EBU_BUSCON0_BCGEN_MOTOROLA, ++ IFX_EBU_BUSCON0_BCGEN_RES, ++}; ++ ++#define IFX_EBU_BUSCON0_ALEC 0x0000c000 ++#define IFX_EBU_BUSCON0_ALEC_S 14 ++enum { ++ IFX_EBU_BUSCON0_ALEC0 = 0, ++ IFX_EBU_BUSCON0_ALEC1, ++ IFX_EBU_BUSCON0_ALEC2, ++ IFX_EBU_BUSCON0_ALEC3, /* Default */ ++}; ++ ++#define IFX_EBU_BUSCON0_XDM 0x00030000 ++#define IFX_EBU_BUSCON0_XDM_S 16 ++enum { ++ IFX_EBU_BUSCON0_XDM8 = 0, ++ IFX_EBU_BUSCON0_XDM16, /* Default */ ++}; ++ ++#define IFX_EBU_BUSCON0_VN_EN 0x00040000 ++ ++#define IFX_EBU_BUSCON0_WAITINV_HI 0x00080000 /* low by default */ ++ ++#define IFX_EBU_BUSCON0_WAIT 0x00300000 ++#define IFX_EBU_BUSCON0_WAIT_S 20 ++enum { ++ IFX_EBU_BUSCON0_WAIT_DISABLE = 0, ++ IFX_EBU_BUSCON0_WAIT_ASYNC, ++ IFX_EBU_BUSCON0_WAIT_SYNC, ++}; ++#define IFX_EBU_BUSCON0_SETUP_EN 0x00400000 /* Disable by default */ ++ ++#define IFX_EBU_BUSCON0_AGEN 0x07000000 ++#define IFX_EBU_BUSCON0_AGEN_S 24 ++enum { ++ IFX_EBU_BUSCON0_AGEN_DEMUX = 0, /* Default */ ++ IFX_EBU_BUSCON0_AGEN_RES, ++ IFX_EBU_BUSCON0_AGEN_MUX, ++}; ++ ++#define IFX_EBU_BUSCON0_PG_EN 0x20000000 ++#define IFX_EBU_BUSCON0_ADSWP 0x40000000 /* Disable by default */ ++#define IFX_EBU_BUSCON0_WRDIS 0x80000000 /* Disable by default */ ++ ++/***EBU Bus Configuration Register 1***/ ++#define IFX_EBU_BUSCON1 ((volatile u32*)(IFX_EBU + 0x0064)) ++#define IFX_EBU_BUSCON1_CMULT 0x00000003 ++#define IFX_EBU_BUSCON1_CMULT_S 0 ++enum { ++ IFX_EBU_BUSCON1_CMULT1 = 0, ++ IFX_EBU_BUSCON1_CMULT4, ++ IFX_EBU_BUSCON1_CMULT8, ++ IFX_EBU_BUSCON1_CMULT16, /* Default after reset */ ++ }; ++ ++#define IFX_EBU_BUSCON1_RECOVC 0x00000000c ++#define IFX_EBU_BUSCON1_RECOVC_S 2 ++enum { ++ IFX_EBU_BUSCON1_RECOVC0 = 0, ++ IFX_EBU_BUSCON1_RECOVC1, ++ IFX_EBU_BUSCON1_RECOVC2, ++ IFX_EBU_BUSCON1_RECOVC3, /* Default */ ++ }; ++#define IFX_EBU_BUSCON1_HOLDC 0x00000030 ++#define IFX_EBU_BUSCON1_HOLDC_S 4 ++enum { ++ IFX_EBU_BUSCON1_HOLDC0 = 0, ++ IFX_EBU_BUSCON1_HOLDC1, ++ IFX_EBU_BUSCON1_HOLDC2, ++ IFX_EBU_BUSCON1_HOLDC3, /* Default */ ++ }; ++#define IFX_EBU_BUSCON1_WAITRDC 0x000000c0 ++#define IFX_EBU_BUSCON1_WAITRDC_S 6 ++enum { ++ IFX_EBU_BUSCON1_WAITRDC0 = 0, ++ IFX_EBU_BUSCON1_WAITRDC1, ++ IFX_EBU_BUSCON1_WAITRDC2, ++ IFX_EBU_BUSCON1_WAITRDC3, /* Default */ ++ }; ++#define IFX_EBU_BUSCON1_WAITWRC 0x00000700 ++#define IFX_EBU_BUSCON1_WAITWRC_S 8 ++enum { ++ IFX_EBU_BUSCON1_WAITWRC0 = 0, ++ IFX_EBU_BUSCON1_WAITWRC1, ++ IFX_EBU_BUSCON1_WAITWRC2, ++ IFX_EBU_BUSCON1_WAITWRC3, ++ IFX_EBU_BUSCON1_WAITWRC4, ++ IFX_EBU_BUSCON1_WAITWRC5, ++ IFX_EBU_BUSCON1_WAITWRC6, ++ IFX_EBU_BUSCON1_WAITWRC7, /* Default */ ++ }; ++#define IFX_EBU_BUSCON1_BCGEN 0x00003000 ++#define IFX_EBU_BUSCON1_BCGEN_S 12 ++enum { ++ IFX_EBU_BUSCON1_BCGEN_CS = 0, ++ IFX_EBU_BUSCON1_BCGEN_INTEL, /* Default */ ++ IFX_EBU_BUSCON1_BCGEN_MOTOROLA, ++ IFX_EBU_BUSCON1_BCGEN_RES, ++ }; ++#define IFX_EBU_BUSCON1_ALEC 0x0000c000 ++#define IFX_EBU_BUSCON1_ALEC_S 14 ++enum { ++ IFX_EBU_BUSCON1_ALEC0 = 0, ++ IFX_EBU_BUSCON1_ALEC1, ++ IFX_EBU_BUSCON1_ALEC2, ++ IFX_EBU_BUSCON1_ALEC3, /* Default */ ++ }; ++ ++#define IFX_EBU_BUSCON1_SETUP (1 << 22) ++ ++#define IFX_EBU_BUSCON1_WRDIS (1 << 31) ++//#define IFX_EBU_BUSCON1_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) ++//#define IFX_EBU_BUSCON1_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) ++//#define IFX_EBU_BUSCON1_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) ++//#define IFX_EBU_BUSCON1_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) ++//#define IFX_EBU_BUSCON1_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) ++//#define IFX_EBU_BUSCON1_WAITINV (1 << 19) ++//#define IFX_EBU_BUSCON1_SETUP (1 << 18) ++//#define IFX_EBU_BUSCON1_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) ++//#define IFX_EBU_BUSCON1_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) ++//#define IFX_EBU_BUSCON1_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) ++//#define IFX_EBU_BUSCON1_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) ++//#define IFX_EBU_BUSCON1_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) ++//#define IFX_EBU_BUSCON1_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) ++ ++/***EBU Bus Configuration Register 2***/ ++#define IFX_EBU_BUSCON2 ((volatile u32*)(IFX_EBU + 0x0068)) ++#define IFX_EBU_BUSCON2_WRDIS (1 << 31) ++#define IFX_EBU_BUSCON2_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) ++#define IFX_EBU_BUSCON2_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) ++#define IFX_EBU_BUSCON2_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) ++#define IFX_EBU_BUSCON2_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) ++#define IFX_EBU_BUSCON2_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) ++#define IFX_EBU_BUSCON2_WAITINV (1 << 19) ++#define IFX_EBU_BUSCON2_SETUP (1 << 18) ++#define IFX_EBU_BUSCON2_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) ++#define IFX_EBU_BUSCON2_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) ++#define IFX_EBU_BUSCON2_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) ++#define IFX_EBU_BUSCON2_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) ++#define IFX_EBU_BUSCON2_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) ++#define IFX_EBU_BUSCON2_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) ++ ++/***EBU Bus Configuration Register 2***/ ++#define IFX_EBU_BUSCON3 ((volatile u32*)(IFX_EBU + 0x006C)) ++#define IFX_EBU_BUSCON3_WRDIS (1 << 31) ++#define IFX_EBU_BUSCON3_ADSWP(value) (1 << 30) ++#define IFX_EBU_BUSCON3_PG_EN(value) (1 << 29) ++#define IFX_EBU_BUSCON3_AGEN(value) (((( 1 << 3) - 1) & (value)) << 24) ++#define IFX_EBU_BUSCON3_SETUP (1 << 22) ++#define IFX_EBU_BUSCON3_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) ++#define IFX_EBU_BUSCON3_WAITINV (1 << 19) ++#define IFX_EBU_BUSCON3_VN_EN (1 << 18) ++#define IFX_EBU_BUSCON3_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) ++#define IFX_EBU_BUSCON3_ALEC(value) (((( 1 << 2) - 1) & (value)) << 14) ++#define IFX_EBU_BUSCON3_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 12) ++#define IFX_EBU_BUSCON3_WAITWDC(value) (((( 1 << 4) - 1) & (value)) << 8) ++#define IFX_EBU_BUSCON3_WAITRRC(value) (((( 1 << 2) - 1) & (value)) << 6) ++#define IFX_EBU_BUSCON3_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) ++#define IFX_EBU_BUSCON3_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) ++#define IFX_EBU_BUSCON3_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) ++ ++/* PC-Card Configuration */ ++#define IFX_EBU_PCC_CON ((volatile u32*)(IFX_EBU+ 0x0090)) ++#define IFX_EBU_PCC_CON_PCCARD_ON 0x00000001 ++#define IFX_EBU_PCC_CON_IREQ_RISING_EDGE 0x00000002 ++#define IFX_EBU_PCC_CON_IREQ_FALLING_EDGE 0x00000004 ++#define IFX_EBU_PCC_CON_IREQ_BOTH_EDGE 0x00000006 ++#define IFX_EBU_PCC_CON_IREQ_DIS 0x00000008 ++#define IFX_EBU_PCC_CON_IREQ_HIGH_LEVEL_DETECT 0x0000000A ++#define IFX_EBU_PCC_CON_IREQ_LOW_LEVEL_DETECT 0x0000000C ++ ++#define IFX_EBU_PCC_STAT ((volatile u32*)(IFX_EBU+ 0x0094)) ++#define IFX_EBU_PCC_ISTAT ((volatile u32*)(IFX_EBU+ 0x00A0)) ++#define IFX_EBU_PCC_IEN ((volatile u32*)(IFX_EBU+ 0x00A4)) ++#define IFX_EBU_PCC_IEN_PCI_EN 0x00000010 ++ ++#define IFX_EBU_PCC_INT_OUT ((volatile u32*)(IFX_EBU+ 0x00A8)) ++#define IFX_EBU_PCC_IRS ((volatile u32*)(IFX_EBU+ 0x00AC)) ++ ++#define IFX_EBU_ECC_IEN ((volatile u32*)(IFX_EBU+ 0x00A4)) ++#define IFX_EBU_NAND_CON (volatile u32*)(IFX_EBU + 0xB0) ++#define IFX_EBU_NAND_WAIT (volatile u32*)(IFX_EBU + 0xB4) ++#define IFX_EBU_NAND_ECC0 (volatile u32*)(IFX_EBU + 0xB8) ++#define IFX_EBU_NAND_ECC_AC (volatile u32*)(IFX_EBU + 0xBC) ++#define IFX_EBU_NAND_ECC_CR (volatile u32*)(IFX_EBU + 0xC0) ++#define IFX_EBU_NAND_CON_NANDM (1<<0) ++#define IFX_EBU_NAND_CON_NANDM_S 0 ++enum { ++ IFX_EBU_NAND_CON_NANDM_DISABLE = 0,/* Default after reset */ ++ IFX_EBU_NAND_CON_NANDM_ENABLE, ++ }; ++ ++#define IFX_EBU_NAND_CON_CSMUX_E (1<<1) ++#define IFX_EBU_NAND_CON_CSMUX_E_S 1 ++enum { ++ IFX_EBU_NAND_CON_CSMUX_E_DISABLE = 0,/* Default after reset */ ++ IFX_EBU_NAND_CON_CSMUX_E_ENABLE, ++ }; ++ ++#define IFX_EBU_NAND_CON_ALE_P (1<<2) ++#define IFX_EBU_NAND_CON_ALE_P_S 2 ++enum { ++ IFX_EBU_NAND_CON_ALE_P_HIGH = 0, ++ IFX_EBU_NAND_CON_ALE_P_LOW, ++}; ++ ++#define IFX_EBU_NAND_CON_CLE_P (1<<3) ++#define IFX_EBU_NAND_CON_CLE_P_S 3 ++enum { ++ IFX_EBU_NAND_CON_CLE_P_HIGH = 0, ++ IFX_EBU_NAND_CON_CLE_P_LOW, ++}; ++ ++#define IFX_EBU_NAND_CON_CS_P (1<<4) ++#define IFX_EBU_NAND_CON_CS_P_S 4 ++enum { ++ IFX_EBU_NAND_CON_CS_P_HIGH = 0, ++ IFX_EBU_NAND_CON_CS_P_LOW, /* Default after reset */ ++ }; ++ ++#define IFX_EBU_NAND_CON_SE_P (1<<5) ++#define IFX_EBU_NAND_CON_SE_P_S 5 ++enum { ++ IFX_EBU_NAND_CON_SE_P_HIGH = 0, ++ IFX_EBU_NAND_CON_SE_P_LOW, /* Default after reset */ ++ }; ++#define IFX_EBU_NAND_CON_WP_P (1<<6) ++#define IFX_EBU_NAND_CON_WP_P_S 6 ++enum { ++ IFX_EBU_NAND_CON_WP_P_HIGH = 0, ++ IFX_EBU_NAND_CON_WP_P_LOW, /* Default after reset */ ++ }; ++ ++#define IFX_EBU_NAND_CON_PRE_P (1<<7) ++#define IFX_EBU_NAND_CON_PRE_P_S 7 ++enum { ++ IFX_EBU_NAND_CON_PRE_P_HIGH = 0, ++ IFX_EBU_NAND_CON_PRE_P_LOW, /* Default after reset */ ++ }; ++ ++#define IFX_EBU_NAND_CON_IN_CS (3<<8) ++#define IFX_EBU_NAND_CON_IN_CS_S 8 ++enum { ++ IFX_EBU_NAND_CON_IN_CS0 = 0, /* Default after reset */ ++ IFX_EBU_NAND_CON_IN_CS1, ++ }; ++ ++#define IFX_EBU_NAND_CON_OUT_CS (3<<10) ++#define IFX_EBU_NAND_CON_OUT_CS_S 10 ++enum { ++ IFX_EBU_NAND_CON_OUT_CS0 = 0, /* Default after reset */ ++ IFX_EBU_NAND_CON_OUT_CS1, ++ }; ++ ++#define IFX_EBU_NAND_CON_ECC (1<<31) ++#define IFX_EBU_NAND_CON_ECC_S 31 ++enum { ++ IFX_EBU_NAND_CON_ECC_OFF = 0, ++ IFX_EBU_NAND_CON_ECC_ON, ++}; ++ ++#define IFX_EBU_NAND_CON_LAT_EN (0x3F << 18) ++#define IFX_EBU_NAND_CON_LAT_EN_S 18 ++enum { ++ IFX_EBU_NAND_CON_LAT_EN_DEF = 0x3D, ++}; ++ ++#define IFX_EBU_NAND_ECC_CRM (1<<31) ++#define IFX_EBU_NAND_ECC_CRM_S 31 ++enum { ++ IFX_EBU_NAND_ECC_CRM_DISABLE = 0, ++ IFX_EBU_NAND_ECC_CRM_ENABLE, ++}; ++ ++#define IFX_EBU_NAND_ECC_PAGE (3<<14) ++#define IFX_EBU_NAND_ECC_PAGE_S 14 ++enum { ++ IFX_EBU_NAND_ECC_PAGE_256 = 0, ++ IFX_EBU_NAND_ECC_PAGE_512, ++ IFX_EBU_NAND_ECC_PAGE_RES, ++}; ++ ++#define IFX_EBU_ECC_IEN_IR (1<<5) ++#define IFX_EBU_ECC_IEN_IR_S 5 ++enum { ++ IFX_EBU_ECC_IEN_DISABLE = 0, ++ IFX_EBU_ECC_IEN_ENABLE, ++}; ++ ++#define IFX_EBU_NAND_ECC_STATE (3<<0) ++#define IFX_EBU_NAND_ECC_STATE_S 0 ++ ++#define IFX_EBU_NAND_ECC_ROW_VAL (0x1FF<<5) ++#define IFX_EBU_NAND_ECC_ROW_VAL_S 5 ++ ++#define IFX_EBU_NAND_ECC_BIT_POS (7<<2) ++#define IFX_EBU_NAND_ECC_BIT_POS_S 2 ++ ++#define IFX_EBU_NAND_WAIT_RD (0x1) ++#define IFX_EBU_NAND_WAIT_BY_E (1<<1) ++#define IFX_EBU_NAND_WAIT_RD_E (1<<2) ++#define IFX_EBU_NAND_WAIT_WR_C (1<<3) ++ ++#define IFX_EBU_NAND_ECC0 (volatile u32*)(IFX_EBU + 0xB8) ++#define IFX_EBU_NAND_ECC_AC (volatile u32*)(IFX_EBU + 0xBC) ++ ++ ++ ++/***********************************************************************/ ++/* Module : SDRAM register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_SDRAM (KSEG1 | 0x1F800000) ++ ++/***MC Access Error Cause Register***/ ++#define IFX_SDRAM_MC_ERRCAUSE ((volatile u32*)(IFX_SDRAM + 0x0100)) ++#define IFX_SDRAM_MC_ERRCAUSE_ERR (1 << 31) ++#define IFX_SDRAM_MC_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16) ++#define IFX_SDRAM_MC_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_ERRCAUSE_Res(value) (((( 1 << NaN) - 1) & (value)) << NaN) ++ ++/***MC Access Error Address Register***/ ++#define IFX_SDRAM_MC_ERRADDR ((volatile u32*)(IFX_SDRAM + 0x0108)) ++ ++/***MC I/O General Purpose Register***/ ++#define IFX_SDRAM_MC_IOGP ((volatile u32*)(IFX_SDRAM + 0x0800)) ++#define IFX_SDRAM_MC_IOGP_GPR6(value) (((( 1 << 4) - 1) & (value)) << 28) ++#define IFX_SDRAM_MC_IOGP_GPR5(value) (((( 1 << 4) - 1) & (value)) << 24) ++#define IFX_SDRAM_MC_IOGP_GPR4(value) (((( 1 << 4) - 1) & (value)) << 20) ++#define IFX_SDRAM_MC_IOGP_GPR3(value) (((( 1 << 4) - 1) & (value)) << 16) ++#define IFX_SDRAM_MC_IOGP_GPR2(value) (((( 1 << 4) - 1) & (value)) << 12) ++#define IFX_SDRAM_MC_IOGP_CPS (1 << 11) ++#define IFX_SDRAM_MC_IOGP_CLKDELAY(value) (((( 1 << 3) - 1) & (value)) << 8) ++#define IFX_SDRAM_MC_IOGP_CLKRAT(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_IOGP_RDDEL(value) (((( 1 << 4) - 1) & (value)) << 0) ++ ++/***MC Self Refresh Register***/ ++#define IFX_SDRAM_MC_SELFRFSH ((volatile u32*)(IFX_SDRAM + 0x0A00)) ++#define IFX_SDRAM_MC_SELFRFSH_PWDS (1 << 1) ++#define IFX_SDRAM_MC_SELFRFSH_PWD (1 << 0) ++#define IFX_SDRAM_MC_SELFRFSH_Res(value) (((( 1 << 30) - 1) & (value)) << 2) ++ ++/***MC Enable Register***/ ++#define IFX_SDRAM_MC_CTRLENA ((volatile u32*)(IFX_SDRAM + 0x1000)) ++#define IFX_SDRAM_MC_CTRLENA_ENA (1 << 0) ++#define IFX_SDRAM_MC_CTRLENA_Res(value) (((( 1 << 31) - 1) & (value)) << 1) ++ ++/***MC Mode Register Setup Code***/ ++#define IFX_SDRAM_MC_MRSCODE ((volatile u32*)(IFX_SDRAM + 0x1008)) ++#define IFX_SDRAM_MC_MRSCODE_UMC(value) (((( 1 << 5) - 1) & (value)) << 7) ++#define IFX_SDRAM_MC_MRSCODE_CL(value) (((( 1 << 3) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_MRSCODE_WT (1 << 3) ++#define IFX_SDRAM_MC_MRSCODE_BL(value) (((( 1 << 3) - 1) & (value)) << 0) ++ ++/***MC Configuration Data-word Width Register***/ ++#define IFX_SDRAM_MC_CFGDW ((volatile u32*)(IFX_SDRAM + 0x1010)) ++#define IFX_SDRAM_MC_CFGDW_DW(value) (((( 1 << 4) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_CFGDW_Res(value) (((( 1 << 28) - 1) & (value)) << 4) ++ ++/***MC Configuration Physical Bank 0 Register***/ ++#define IFX_SDRAM_MC_CFGPB0 ((volatile u32*)(IFX_SDRAM + 0x1018)) ++#define IFX_SDRAM_MC_CFGPB0_MCSEN0(value) (((( 1 << 4) - 1) & (value)) << 12) ++#define IFX_SDRAM_MC_CFGPB0_BANKN0(value) (((( 1 << 4) - 1) & (value)) << 8) ++#define IFX_SDRAM_MC_CFGPB0_ROWW0(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_CFGPB0_COLW0(value) (((( 1 << 4) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_CFGPB0_Res(value) (((( 1 << 16) - 1) & (value)) << 16) ++ ++/***MC Latency Register***/ ++#define IFX_SDRAM_MC_LATENCY ((volatile u32*)(IFX_SDRAM + 0x1038)) ++#define IFX_SDRAM_MC_LATENCY_TRP(value) (((( 1 << 4) - 1) & (value)) << 16) ++#define IFX_SDRAM_MC_LATENCY_TRAS(value) (((( 1 << 4) - 1) & (value)) << 12) ++#define IFX_SDRAM_MC_LATENCY_TRCD(value) (((( 1 << 4) - 1) & (value)) << 8) ++#define IFX_SDRAM_MC_LATENCY_TDPL(value) (((( 1 << 4) - 1) & (value)) << 4) ++#define IFX_SDRAM_MC_LATENCY_TDAL(value) (((( 1 << 4) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_LATENCY_Res(value) (((( 1 << 12) - 1) & (value)) << 20) ++ ++/***MC Refresh Cycle Time Register***/ ++#define IFX_SDRAM_MC_TREFRESH ((volatile u32*)(IFX_SDRAM + 0x1040)) ++#define IFX_SDRAM_MC_TREFRESH_TREF(value) (((( 1 << 13) - 1) & (value)) << 0) ++#define IFX_SDRAM_MC_TREFRESH_Res(value) (((( 1 << 19) - 1) & (value)) << 13) ++ ++/***MC Status Register***/ ++#define IFX_SDRAM_MC_STAT ((volatile u32*)(IFX_SDRAM + 0x0070)) ++ ++/***MC DDR Control Register 00***/ ++#define IFX_DDR_MC_DC00 ((volatile u32*)(IFX_SDRAM + 0x1000)) ++/***MC DDR Control Register 03***/ ++#define IFX_DDR_MC_DC03 ((volatile u32*)(IFX_SDRAM + 0x1030)) ++/***MC DDR Control Register 17***/ ++#define IFX_DDR_MC_DC17 ((volatile u32*)(IFX_SDRAM + 0x1110)) ++ ++/***********************************************************************/ ++/* Module : ASC1 register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_ASC1 (KSEG1 | 0x1E100C00) ++ ++/***ASC Clock Control Register***/ ++#define IFX_ASC1_CLC ((volatile u32*)(IFX_ASC1 + 0x0000)) ++#define IFX_ASC1_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) ++#define IFX_ASC1_CLC_DISS (1 << 1) ++#define IFX_ASC1_CLC_DISR (1 << 0) ++ ++/***ASC Port Input Select Register***/ ++#define IFX_ASC1_PISEL ((volatile u32*)(IFX_ASC1 + 0x0004)) ++#define IFX_ASC1_PISEL ((volatile u32*)(IFX_ASC1 + 0x0004)) ++#define IFX_ASC1_PISEL_RIS (1 << 0) ++ ++/***ASC Control Register***/ ++#define IFX_ASC1_CON ((volatile u32*)(IFX_ASC1 + 0x0010)) ++#define IFX_ASC1_CON_BEN (1 << 20) ++#define IFX_ASC1_CON_TOEN (1 << 20) ++#define IFX_ASC1_CON_ROEN (1 << 19) ++#define IFX_ASC1_CON_RUEN (1 << 18) ++#define IFX_ASC1_CON_FEN (1 << 17) ++#define IFX_ASC1_CON_PAL (1 << 16) ++#define IFX_ASC1_CON_R (1 << 15) ++#define IFX_ASC1_CON_ACO (1 << 14) ++#define IFX_ASC1_CON_LB (1 << 13) ++#define IFX_ASC1_CON_ERCLK (1 << 10) ++#define IFX_ASC1_CON_FDE (1 << 9) ++#define IFX_ASC1_CON_BRS (1 << 8) ++#define IFX_ASC1_CON_STP (1 << 7) ++#define IFX_ASC1_CON_SP (1 << 6) ++#define IFX_ASC1_CON_ODD (1 << 5) ++#define IFX_ASC1_CON_PEN (1 << 4) ++#define IFX_ASC1_CON_M(value) (((( 1 << 3) - 1) & (value)) << 0) ++ ++/***ASC Staus Register***/ ++#define IFX_ASC1_STATE ((volatile u32*)(IFX_ASC1 + 0x0014)) ++/***ASC Write Hardware Modified Control Register***/ ++#define IFX_ASC1_WHBSTATE ((volatile u32*)(IFX_ASC1 + 0x0018)) ++#define IFX_ASC1_WHBSTATE_SETBE (1 << 113) ++#define IFX_ASC1_WHBSTATE_SETTOE (1 << 12) ++#define IFX_ASC1_WHBSTATE_SETROE (1 << 11) ++#define IFX_ASC1_WHBSTATE_SETRUE (1 << 10) ++#define IFX_ASC1_WHBSTATE_SETFE (1 << 19) ++#define IFX_ASC1_WHBSTATE_SETPE (1 << 18) ++#define IFX_ASC1_WHBSTATE_CLRBE (1 << 17) ++#define IFX_ASC1_WHBSTATE_CLRTOE (1 << 6) ++#define IFX_ASC1_WHBSTATE_CLRROE (1 << 5) ++#define IFX_ASC1_WHBSTATE_CLRRUE (1 << 4) ++#define IFX_ASC1_WHBSTATE_CLRFE (1 << 3) ++#define IFX_ASC1_WHBSTATE_CLRPE (1 << 2) ++#define IFX_ASC1_WHBSTATE_SETREN (1 << 1) ++#define IFX_ASC1_WHBSTATE_CLRREN (1 << 0) ++ ++/***ASC Baudrate Timer/Reload Register***/ ++#define IFX_ASC1_BG ((volatile u32*)(IFX_ASC1 + 0x0050)) ++#define IFX_ASC1_BG_BR_VALUE(value) (((( 1 << 13) - 1) & (value)) << 0) ++ ++/***ASC Fractional Divider Register***/ ++#define IFX_ASC1_FDV ((volatile u32*)(IFX_ASC1 + 0x0018)) ++#define IFX_ASC1_FDV_FD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) ++ ++/***ASC Transmit Buffer Register***/ ++#define IFX_ASC1_TBUF ((volatile u32*)(IFX_ASC1 + 0x0020)) ++#define IFX_ASC1_TBUF_TD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) ++ ++/***ASC Receive Buffer Register***/ ++#define IFX_ASC1_RBUF ((volatile u32*)(IFX_ASC1 + 0x0024)) ++#define IFX_ASC1_RBUF_RD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) ++ ++/***ASC Autobaud Control Register***/ ++#define IFX_ASC1_ABCON ((volatile u32*)(IFX_ASC1 + 0x0030)) ++#define IFX_ASC1_ABCON_RXINV (1 << 11) ++#define IFX_ASC1_ABCON_TXINV (1 << 10) ++#define IFX_ASC1_ABCON_ABEM(value) (((( 1 << 2) - 1) & (value)) << 8) ++#define IFX_ASC1_ABCON_FCDETEN (1 << 4) ++#define IFX_ASC1_ABCON_ABDETEN (1 << 3) ++#define IFX_ASC1_ABCON_ABSTEN (1 << 2) ++#define IFX_ASC1_ABCON_AUREN (1 << 1) ++#define IFX_ASC1_ABCON_ABEN (1 << 0) ++ ++/***Receive FIFO Control Register***/ ++#define IFX_ASC1_RXFCON ((volatile u32*)(IFX_ASC1 + 0x0040)) ++#define IFX_ASC1_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) ++#define IFX_ASC1_RXFCON_RXFFLU (1 << 1) ++#define IFX_ASC1_RXFCON_RXFEN (1 << 0) ++ ++/***Transmit FIFO Control Register***/ ++#define IFX_ASC1_TXFCON ((volatile u32*)(IFX_ASC1 + 0x0044)) ++#define IFX_ASC1_TXFCON_TXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) ++#define IFX_ASC1_TXFCON_TXFFLU (1 << 1) ++#define IFX_ASC1_TXFCON_TXFEN (1 << 0) ++ ++/***FIFO Status Register***/ ++#define IFX_ASC1_FSTAT ((volatile u32*)(IFX_ASC1 + 0x0048)) ++#define IFX_ASC1_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8) ++#define IFX_ASC1_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0) ++#define IFX_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) ++#define IFX_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) ++#define IFX_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) ++#define IFX_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) ++#define IFX_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) ++#define IFX_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) ++#define IFX_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) ++#define IFX_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) ++ ++ ++/***ASC Autobaud Status Register***/ ++#define IFX_ASC1_ABSTAT ((volatile u32*)(IFX_ASC1 + 0x0034)) ++#define IFX_ASC1_ABSTAT_DETWAIT (1 << 4) ++#define IFX_ASC1_ABSTAT_SCCDET (1 << 3) ++#define IFX_ASC1_ABSTAT_SCSDET (1 << 2) ++#define IFX_ASC1_ABSTAT_FCCDET (1 << 1) ++#define IFX_ASC1_ABSTAT_FCSDET (1 << 0) ++ ++/***ASC Write HW Modified Autobaud Status Register***/ ++#define IFX_ASC1_WHBABSTAT ((volatile u32*)(IFX_ASC1 + 0x003C)) ++#define IFX_ASC1_WHBABSTAT_SETDETWAIT (1 << 9) ++#define IFX_ASC1_WHBABSTAT_CLRDETWAIT (1 << 8) ++#define IFX_ASC1_WHBABSTAT_SETSCCDET (1 << 7) ++#define IFX_ASC1_WHBABSTAT_CLRSCCDET (1 << 6) ++#define IFX_ASC1_WHBABSTAT_SETSCSDET (1 << 5) ++#define IFX_ASC1_WHBABSTAT_CLRSCSDET (1 << 4) ++#define IFX_ASC1_WHBABSTAT_SETFCCDET (1 << 3) ++#define IFX_ASC1_WHBABSTAT_CLRFCCDET (1 << 2) ++#define IFX_ASC1_WHBABSTAT_SETFCSDET (1 << 1) ++#define IFX_ASC1_WHBABSTAT_CLRFCSDET (1 << 0) ++ ++/***ASC IRNCR0 **/ ++#define IFX_ASC1_IRNREN ((volatile u32*)(IFX_ASC1 + 0x00F4)) ++#define IFX_ASC1_IRNICR ((volatile u32*)(IFX_ASC1 + 0x00FC)) ++/***ASC IRNCR1 **/ ++#define IFX_ASC1_IRNCR ((volatile u32*)(IFX_ASC1 + 0x00F8)) ++#define IFX_ASC_IRNCR_TIR 0x1 ++#define IFX_ASC_IRNCR_RIR 0x2 ++#define IFX_ASC_IRNCR_EIR 0x4 ++ ++ ++ ++/***********************************************************************/ ++/* Module : DMA register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_DMA (KSEG1 | 0x1E104100) ++ ++#define IFX_DMA_BASE IFX_DMA ++#define IFX_DMA_CLC (volatile u32*)(IFX_DMA_BASE + 0x00) ++#define IFX_DMA_ID (volatile u32*)(IFX_DMA_BASE + 0x08) ++#define IFX_DMA_CTRL (volatile u32*)(IFX_DMA_BASE + 0x10) ++#define IFX_DMA_CPOLL (volatile u32*)(IFX_DMA_BASE + 0x14) ++ ++#define IFX_DMA_CS(i) (volatile u32*)(IFX_DMA_BASE + 0x18 + 0x38 * (i)) ++#define IFX_DMA_CCTRL(i) (volatile u32*)(IFX_DMA_BASE + 0x1C + 0x38 * (i)) ++#define IFX_DMA_CDBA(i) (volatile u32*)(IFX_DMA_BASE + 0x20 + 0x38 * (i)) ++#define IFX_DMA_CDLEN(i) (volatile u32*)(IFX_DMA_BASE + 0x24 + 0x38 * (i)) ++#define IFX_DMA_CIS(i) (volatile u32*)(IFX_DMA_BASE + 0x28 + 0x38 * (i)) ++#define IFX_DMA_CIE(i) (volatile u32*)(IFX_DMA_BASE + 0x2C + 0x38 * (i)) ++ ++#define IFX_DMA_CGBL (volatile u32*)(IFX_DMA_BASE + 0x30) ++ ++#define IFX_DMA_CDPTNRD(i) (volatile u32*)(IFX_DMA_BASE + 0x34 + 0x04 * (i)) ++ ++#define IFX_DMA_PS(i) (volatile u32*)(IFX_DMA_BASE + 0x40 + 0x30 * (i)) ++#define IFX_DMA_PCTRL(i) (volatile u32*)(IFX_DMA_BASE + 0x44 + 0x30 * (i)) ++ ++#define IFX_DMA_IRNEN (volatile u32*)(IFX_DMA_BASE + 0xf4) ++#define IFX_DMA_IRNCR (volatile u32*)(IFX_DMA_BASE + 0xf8) ++#define IFX_DMA_IRNICR (volatile u32*)(IFX_DMA_BASE + 0xfc) ++/* Global Software Reset (0) */ ++#define IFX_DMA_CTRL_RST (0x1) ++ ++/* Channel Polling Register */ ++ ++/* Enable (31) */ ++#define IFX_DMA_CPOLL_EN (0x1 << 31) ++#define IFX_DMA_CPOLL_EN_VAL(val) (((val) & 0x1) << 31) ++ ++/* Counter (15:4) */ ++#define IFX_DMA_CPOLL_CNT (0xfff << 4) ++#define IFX_DMA_CPOLL_CNT_VAL(val) (((val) & 0xfff) << 4) ++ ++/* Channel Control Register */ ++ ++/* Peripheral to Peripheral Copy (24) */ ++#define IFX_DMA_CCTRL_P2PCPY (0x1 << 24) ++#define IFX_DMA_CCTRL_P2PCPY_VAL(val) (((val) & 0x1) << 24) ++#define IFX_DMA_CCTRL_P2PCPY_GET(val) ((((val) & IFX_DMA_CCTRL_P2PCPY) >> 24) & 0x1) ++ ++/* Channel Weight for Transmit Direction (17:16) */ ++#define IFX_DMA_CCTRL_TXWGT (0x3 << 16) ++#define IFX_DMA_CCTRL_TXWGT_VAL(val) (((val) & 0x3) << 16) ++#define IFX_DMA_CCTRL_TXWGT_GET(val) ((((val) & IFX_DMA_CCTRL_TXWGT) >> 16) & 0x3) ++ ++/* Port Assignment (13:11) */ ++#define IFX_DMA_CCTRL_PRTNR (0x7 << 11) ++#define IFX_DMA_CCTRL_PRTNR_GET(val) ((((val) & IFX_DMA_CCTRL_PRTNR) >> 11) & 0x7) ++ ++/* Class (10:9) */ ++#define IFX_DMA_CCTRL_CLASS (0x3 << 9) ++#define IFX_DMA_CCTRL_CLASS_VAL(val) (((val) & 0x3) << 9) ++#define IFX_DMA_CCTRL_CLASS_GET(val) ((((val) & IFX_DMA_CCTRL_CLASS) >> 9) & 0x3) ++ ++/* Direction (8) */ ++#define IFX_DMA_CCTRL_DIR (0x1 << 8) ++/* Reset (1) */ ++#define IFX_DMA_CCTRL_RST (0x1 << 1) ++/* Channel On or Off (0) */ ++#define IFX_DMA_CCTRL_ON (0x1) ++ ++/* Channel Interrupt Status Register */ ++ ++/* SAI Read Error Interrupt (5) */ ++#define IFX_DMA_CIS_RDERR (0x1 << 5) ++/* Channel Off Interrupt (4) */ ++#define IFX_DMA_CIS_CHOFF (0x1 << 4) ++/* Descriptor Complete Interrupt (3) */ ++#define IFX_DMA_CIS_DESCPT (0x1 << 3) ++/* Descriptor Under-Run Interrupt (2) */ ++#define IFX_DMA_CIS_DUR (0x1 << 2) ++/* End of Packet Interrupt (1) */ ++#define IFX_DMA_CIS_EOP (0x1 << 1) ++ ++#define IFX_DMA_CIS_ALL (IFX_DMA_CIS_RDERR | IFX_DMA_CIS_CHOFF| \ ++ IFX_DMA_CIS_DESCPT | IFX_DMA_CIS_DUR | \ ++ IFX_DMA_CIS_EOP) ++ ++/* Channel Interrupt Enable Register */ ++ ++/* SAI Read Error Interrupt (5) */ ++#define IFX_DMA_CIE_RDERR (0x1 << 5) ++/* Channel Off Interrupt (4) */ ++#define IFX_DMA_CIE_CHOFF (0x1 << 4) ++/* Descriptor Complete Interrupt Enable (3) */ ++#define IFX_DMA_CIE_DESCPT (0x1 << 3) ++/* Descriptor Under Run Interrupt Enable (2) */ ++#define IFX_DMA_CIE_DUR (0x1 << 2) ++/* End of Packet Interrupt Enable (1) */ ++#define IFX_DMA_CIE_EOP (0x1 << 1) ++ ++#define IFX_DMA_CIE_DEFAULT (IFX_DMA_CIE_DESCPT | IFX_DMA_CIE_EOP) ++ ++/* Port Select Register */ ++ ++/* Port Selection (2:0) */ ++#define IFX_DMA_PS_PS (0x7) ++#define IFX_DMA_PS_PS_VAL(val) (((val) & 0x7) << 0) ++ ++/* Port Control Register */ ++ ++/* General Purpose Control (16) */ ++#define IFX_DMA_PCTRL_GPC (0x1 << 16) ++#define IFX_DMA_PCTRL_GPC_VAL(val) (((val) & 0x1) << 16) ++ ++/* Port Weight for Transmit Direction (14:12) */ ++#define IFX_DMA_PCTRL_TXWGT (0x7 << 12) ++#define IFX_DMA_PCTRL_TXWGT_VAL(val) (((val) & 0x7) << 12) ++/* Endianness for Transmit Direction (11:10) */ ++#define IFX_DMA_PCTRL_TXENDI (0x3 << 10) ++#define IFX_DMA_PCTRL_TXENDI_VAL(val) (((val) & 0x3) << 10) ++/* Endianness for Receive Direction (9:8) */ ++#define IFX_DMA_PCTRL_RXENDI (0x3 << 8) ++#define IFX_DMA_PCTRL_RXENDI_VAL(val) (((val) & 0x3) << 8) ++/* Packet Drop Enable (6) */ ++#define IFX_DMA_PCTRL_PDEN (0x1 << 6) ++#define IFX_DMA_PCTRL_PDEN_VAL(val) (((val) & 0x1) << 6) ++/* Burst Length for Transmit Direction (5:4) */ ++#define IFX_DMA_PCTRL_TXBL (0x3 << 4) ++#define IFX_DMA_PCTRL_TXBL_VAL(val) (((val) & 0x3) << 4) ++/* Burst Length for Receive Direction (3:2) */ ++#define IFX_DMA_PCTRL_RXBL (0x3 << 2) ++#define IFX_DMA_PCTRL_RXBL_VAL(val) (((val) & 0x3) << 2) ++ ++ ++ ++/***********************************************************************/ ++/* Module : Debug register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_Debug (KSEG1 | 0x1F106000) ++ ++/***MCD Break Bus Switch Register***/ ++#define IFX_Debug_MCD_BBS ((volatile u32*)(IFX_Debug + 0x0000)) ++#define IFX_Debug_MCD_BBS_BTP1 (1 << 19) ++#define IFX_Debug_MCD_BBS_BTP0 (1 << 18) ++#define IFX_Debug_MCD_BBS_BSP1 (1 << 17) ++#define IFX_Debug_MCD_BBS_BSP0 (1 << 16) ++#define IFX_Debug_MCD_BBS_BT5EN (1 << 15) ++#define IFX_Debug_MCD_BBS_BT4EN (1 << 14) ++#define IFX_Debug_MCD_BBS_BT5 (1 << 13) ++#define IFX_Debug_MCD_BBS_BT4 (1 << 12) ++#define IFX_Debug_MCD_BBS_BS5EN (1 << 7) ++#define IFX_Debug_MCD_BBS_BS4EN (1 << 6) ++#define IFX_Debug_MCD_BBS_BS5 (1 << 5) ++#define IFX_Debug_MCD_BBS_BS4 (1 << 4) ++ ++/***MCD Multiplexer Control Register***/ ++#define IFX_Debug_MCD_MCR ((volatile u32*)(IFX_Debug+ 0x0008)) ++#define IFX_Debug_MCD_MCR_MUX5 (1 << 4) ++#define IFX_Debug_MCD_MCR_MUX4 (1 << 3) ++#define IFX_Debug_MCD_MCR_MUX1 (1 << 0) ++ ++ ++ ++/***********************************************************************/ ++/* Module : ICU register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_ICU (KSEG1 | 0x1F880200) ++ ++#define IFX_ICU_IM0_ISR ((volatile u32*)(IFX_ICU + 0x0000)) ++#define IFX_ICU_IM0_IER ((volatile u32*)(IFX_ICU + 0x0008)) ++#define IFX_ICU_IM0_IOSR ((volatile u32*)(IFX_ICU + 0x0010)) ++#define IFX_ICU_IM0_IRSR ((volatile u32*)(IFX_ICU + 0x0018)) ++#define IFX_ICU_IM0_IMR ((volatile u32*)(IFX_ICU + 0x0020)) ++ ++#define IFX_ICU_IM1_ISR ((volatile u32*)(IFX_ICU + 0x0028)) ++#define IFX_ICU_IM1_IER ((volatile u32*)(IFX_ICU + 0x0030)) ++#define IFX_ICU_IM1_IOSR ((volatile u32*)(IFX_ICU + 0x0038)) ++#define IFX_ICU_IM1_IRSR ((volatile u32*)(IFX_ICU + 0x0040)) ++#define IFX_ICU_IM1_IMR ((volatile u32*)(IFX_ICU + 0x0048)) ++ ++#define IFX_ICU_IM2_ISR ((volatile u32*)(IFX_ICU + 0x0050)) ++#define IFX_ICU_IM2_IER ((volatile u32*)(IFX_ICU + 0x0058)) ++#define IFX_ICU_IM2_IOSR ((volatile u32*)(IFX_ICU + 0x0060)) ++#define IFX_ICU_IM2_IRSR ((volatile u32*)(IFX_ICU + 0x0068)) ++#define IFX_ICU_IM2_IMR ((volatile u32*)(IFX_ICU + 0x0070)) ++ ++#define IFX_ICU_IM3_ISR ((volatile u32*)(IFX_ICU + 0x0078)) ++#define IFX_ICU_IM3_IER ((volatile u32*)(IFX_ICU + 0x0080)) ++#define IFX_ICU_IM3_IOSR ((volatile u32*)(IFX_ICU + 0x0088)) ++#define IFX_ICU_IM3_IRSR ((volatile u32*)(IFX_ICU + 0x0090)) ++#define IFX_ICU_IM3_IMR ((volatile u32*)(IFX_ICU + 0x0098)) ++ ++#define IFX_ICU_IM4_ISR ((volatile u32*)(IFX_ICU + 0x00A0)) ++#define IFX_ICU_IM4_IER ((volatile u32*)(IFX_ICU + 0x00A8)) ++#define IFX_ICU_IM4_IOSR ((volatile u32*)(IFX_ICU + 0x00B0)) ++#define IFX_ICU_IM4_IRSR ((volatile u32*)(IFX_ICU + 0x00B8)) ++#define IFX_ICU_IM4_IMR ((volatile u32*)(IFX_ICU + 0x00C0)) ++ ++/***Interrupt Vector Value Register***/ ++#define IFX_ICU_IM_VEC_5 ((volatile u32*)(IFX_ICU + 0x00C8)) ++#define IFX_ICU_IM_VEC ((volatile u32*)(IFX_ICU + 0x00D0)) ++ ++/***********************************************************************/ ++ ++#define IFX_ICU_VPE1 (KSEG1 | 0x1F880300) ++#define IFX_ICU1 IFX_ICU_VPE1 ++ ++#define IFX_ICU_VPE1_IM0_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0000)) ++#define IFX_ICU_VPE1_IM0_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0008)) ++#define IFX_ICU_VPE1_IM0_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0010)) ++#define IFX_ICU_VPE1_IM0_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0018)) ++#define IFX_ICU_VPE1_IM0_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0020)) ++ ++#define IFX_ICU_VPE1_IM1_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0028)) ++#define IFX_ICU_VPE1_IM1_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0030)) ++#define IFX_ICU_VPE1_IM1_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0038)) ++#define IFX_ICU_VPE1_IM1_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0040)) ++#define IFX_ICU_VPE1_IM1_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0048)) ++ ++#define IFX_ICU_VPE1_IM2_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0050)) ++#define IFX_ICU_VPE1_IM2_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0058)) ++#define IFX_ICU_VPE1_IM2_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0060)) ++#define IFX_ICU_VPE1_IM2_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0068)) ++#define IFX_ICU_VPE1_IM2_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0070)) ++ ++#define IFX_ICU_VPE1_IM3_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0078)) ++#define IFX_ICU_VPE1_IM3_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0080)) ++#define IFX_ICU_VPE1_IM3_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0088)) ++#define IFX_ICU_VPE1_IM3_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0090)) ++#define IFX_ICU_VPE1_IM3_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0098)) ++ ++#define IFX_ICU_VPE1_IM4_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x00A0)) ++#define IFX_ICU_VPE1_IM4_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x00A8)) ++#define IFX_ICU_VPE1_IM4_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x00B0)) ++#define IFX_ICU_VPE1_IM4_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x00B8)) ++#define IFX_ICU_VPE1_IM4_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x00C0)) ++ ++/***Interrupt Vector Value Register***/ ++#define IFX_ICU_VPE1_IM_VEC_5 ((volatile u32*)(IFX_ICU_VPE1 + 0x00C8)) ++#define IFX_ICU_VPE1_IM_VEC ((volatile u32*)(IFX_ICU_VPE1 + 0x00D0)) ++#define IFX_ICU_IM_VEC1 IFX_ICU_VPE1_IM_VEC ++ ++/* MSI PIC */ ++#define IFX_MSI_PIC_REG_BASE (KSEG1 | 0x1F700000) ++ ++#define IFX_MSI_PIC_BIG_ENDIAN 1 ++#define IFX_MSI_PIC_LITTLE_ENDIAN 0 ++ ++#define IFX_MSI_PCI_INT_DISABLE 0x80000000 ++#define IFX_MSI_PIC_INT_LINE 0x30000000 ++#define IFX_MSI_PIC_INT_LINE_S 28 ++#define IFX_MSI_PIC_MSG_ADDR 0x0FFF0000 ++#define IFX_MSI_PIC_MSG_ADDR_S 16 ++#define IFX_MSI_PIC_MSG_DATA 0x0000FFFF ++#define IFX_MSI_PIC_MSG_DATA_S 0x0 ++ ++/***Interrupt Vector Value Mask***/ ++#define IFX_ICU_IM0_VEC_MASK (0x3F << 0) ++#define IFX_ICU_IM1_VEC_MASK (0x3F << 6) ++#define IFX_ICU_IM2_VEC_MASK (0x3F << 12) ++#define IFX_ICU_IM3_VEC_MASK (0x3F << 18) ++#define IFX_ICU_IM4_VEC_MASK (0x3F << 24) ++ ++/***External Interrupt Control Register***/ ++#define IFX_ICU_EIU (KSEG1 | 0x1F101000) ++#define IFX_ICU_EIU_EXIN_C ((volatile u32 *)(IFX_ICU_EIU + 0x0000)) ++#define IFX_ICU_EIU_INIC ((volatile u32 *)(IFX_ICU_EIU + 0x0004)) ++#define IFX_ICU_EIU_INC ((volatile u32 *)(IFX_ICU_EIU + 0x0008)) ++#define IFX_ICU_EIU_INEN ((volatile u32 *)(IFX_ICU_EIU + 0x000C)) ++#define IFX_YIELDEN(n) ((volatile u32 *)(IFX_ICU_EIU + 0x0010 + (n) * 4) ++#define IFX_NMI_CR ((volatile u32 *)(IFX_ICU_EIU + 0x00F0)) ++#define IFX_NMI_SR ((volatile u32 *)(IFX_ICU_EIU + 0x00F4)) ++ ++ ++ ++/***********************************************************************/ ++/* Module : MPS register address and bits */ ++/***********************************************************************/ ++ ++#define IFX_MPS (KSEG1 | 0x1F107000) ++ ++#define IFX_MPS_CHIPID ((volatile u32*)(IFX_MPS + 0x0344)) ++#define IFX_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) ++#define IFX_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) ++#define IFX_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) ++#define IFX_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12) ++#define IFX_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) ++#define IFX_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1) ++ ++ ++/* voice channel 0 ... 3 interrupt enable register */ ++#define IFX_MPS_VC0ENR ((volatile u32*)(IFX_MPS + 0x0000)) ++#define IFX_MPS_VC1ENR ((volatile u32*)(IFX_MPS + 0x0004)) ++#define IFX_MPS_VC2ENR ((volatile u32*)(IFX_MPS + 0x0008)) ++#define IFX_MPS_VC3ENR ((volatile u32*)(IFX_MPS + 0x000C)) ++/* voice channel 0 ... 3 interrupt status read register */ ++#define IFX_MPS_RVC0SR ((volatile u32*)(IFX_MPS + 0x0010)) ++#define IFX_MPS_RVC1SR ((volatile u32*)(IFX_MPS + 0x0014)) ++#define IFX_MPS_RVC2SR ((volatile u32*)(IFX_MPS + 0x0018)) ++#define IFX_MPS_RVC3SR ((volatile u32*)(IFX_MPS + 0x001C)) ++/* voice channel 0 ... 3 interrupt status set register */ ++#define IFX_MPS_SVC0SR ((volatile u32*)(IFX_MPS + 0x0020)) ++#define IFX_MPS_SVC1SR ((volatile u32*)(IFX_MPS + 0x0024)) ++#define IFX_MPS_SVC2SR ((volatile u32*)(IFX_MPS + 0x0028)) ++#define IFX_MPS_SVC3SR ((volatile u32*)(IFX_MPS + 0x002C)) ++/* voice channel 0 ... 3 interrupt status clear register */ ++#define IFX_MPS_CVC0SR ((volatile u32*)(IFX_MPS + 0x0030)) ++#define IFX_MPS_CVC1SR ((volatile u32*)(IFX_MPS + 0x0034)) ++#define IFX_MPS_CVC2SR ((volatile u32*)(IFX_MPS + 0x0038)) ++#define IFX_MPS_CVC3SR ((volatile u32*)(IFX_MPS + 0x003C)) ++/* common status 0 and 1 read register */ ++#define IFX_MPS_RAD0SR ((volatile u32*)(IFX_MPS + 0x0040)) ++#define IFX_MPS_RAD1SR ((volatile u32*)(IFX_MPS + 0x0044)) ++/* common status 0 and 1 set register */ ++#define IFX_MPS_SAD0SR ((volatile u32*)(IFX_MPS + 0x0048)) ++#define IFX_MPS_SAD1SR ((volatile u32*)(IFX_MPS + 0x004C)) ++/* common status 0 and 1 clear register */ ++#define IFX_MPS_CAD0SR ((volatile u32*)(IFX_MPS + 0x0050)) ++#define IFX_MPS_CAD1SR ((volatile u32*)(IFX_MPS + 0x0054)) ++/* common status 0 and 1 enable register */ ++#define IFX_MPS_AD0ENR ((volatile u32*)(IFX_MPS + 0x0058)) ++#define IFX_MPS_AD1ENR ((volatile u32*)(IFX_MPS + 0x005C)) ++/* notification enable register */ ++#define IFX_MPS_CPU0_NFER ((volatile u32*)(IFX_MPS + 0x0060)) ++#define IFX_MPS_CPU1_NFER ((volatile u32*)(IFX_MPS + 0x0064)) ++/* CPU to CPU interrup request register */ ++#define IFX_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(IFX_MPS + 0x0070)) ++#define IFX_MPS_CPU0_2_CPU1_IER ((volatile u32*)(IFX_MPS + 0x0074)) ++/* Global interrupt request and request enable register */ ++#define IFX_MPS_GIRR ((volatile u32*)(IFX_MPS + 0x0078)) ++#define IFX_MPS_GIER ((volatile u32*)(IFX_MPS + 0x007C)) ++ ++#define IFX_MPS_SRAM ((volatile u32*)(KSEG1 | 0x1F200000)) ++ ++#define IFX_MPS_VCPU_FW_AD ((volatile u32*)(KSEG1 | 0x1F2001E0)) ++ ++#define IFX_FUSE_ID_CFG ((volatile u32*)(KSEG1 | 0x1F107350)) ++#define IFX_FUSE_BASE_ADDR (KSEG1 | 0x1F107354) ++ ++ ++ ++/************************************************************************/ ++/* Module : DEU register address and bits */ ++/************************************************************************/ ++ ++#define IFX_DEU_BASE_ADDR (KSEG1 | 0x1E103100) ++ ++/* DEU Control Register */ ++#define IFX_DEU_CLK ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0000)) ++#define IFX_DEU_ID ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0008)) ++ ++/* DEU control register */ ++#define IFX_DES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0010)) ++#define IFX_DES_IHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0014)) ++#define IFX_DES_ILR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0018)) ++#define IFX_DES_K1HR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x001C)) ++#define IFX_DES_K1LR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0020)) ++#define IFX_DES_K3HR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0024)) ++#define IFX_DES_K3LR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0028)) ++#define IFX_DES_IVHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x002C)) ++#define IFX_DES_IVLR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0030)) ++#define IFX_DES_OHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0040)) ++#define IFX_DES_OLR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050)) ++ ++/* AES DEU register */ ++#define IFX_AES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050)) ++#define IFX_AES_ID3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0054)) ++#define IFX_AES_ID2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0058)) ++#define IFX_AES_ID1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x005C)) ++#define IFX_AES_ID0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0060)) ++ ++/* AES Key register */ ++#define IFX_AES_K7R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0064)) ++#define IFX_AES_K6R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0068)) ++#define IFX_AES_K5R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x006C)) ++#define IFX_AES_K4R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0070)) ++#define IFX_AES_K3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0074)) ++#define IFX_AES_K2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0078)) ++#define IFX_AES_K1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x007C)) ++#define IFX_AES_K0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0080)) ++ ++/* AES vector register */ ++#define IFX_AES_IV3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0084)) ++#define IFX_AES_IV2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0088)) ++#define IFX_AES_IV1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x008C)) ++#define IFX_AES_IV0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0090)) ++#define IFX_AES_0D3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0094)) ++#define IFX_AES_0D2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0098)) ++#define IFX_AES_OD1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x009C)) ++#define IFX_AES_OD0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00A0)) ++ ++/* ARC4 DEU register */ ++#define IFX_ARC4_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0100)) ++#define IFX_ARC4_IDLEN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0114)) ++#define IFX_ARC4_ID3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0118)) ++#define IFX_ARC4_ID2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x011C)) ++#define IFX_ARC4_ID1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0120)) ++#define IFX_ARC4_ID0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0124)) ++ ++/* ARC4 Key register */ ++#define IFX_ARC4_K3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0104)) ++#define IFX_ARC4_K2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0108)) ++#define IFX_ARC4_K1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x010C)) ++#define IFX_ARC4_K0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0110)) ++ ++/* ARC4 vector register */ ++#define IFX_ARC4_OD3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0128)) ++#define IFX_ARC4_OD2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x012C)) ++#define IFX_ARC4_OD1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0130)) ++#define IFX_ARC4_OD0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0134)) ++ ++/* hash control register */ ++#define IFX_HASH_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B0)) ++#define IFX_HASH_MR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B4)) ++#define IFX_HASH_D1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B8)) ++#define IFX_HASH_D2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00BC)) ++#define IFX_HASH_D3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C0)) ++#define IFX_HASH_D4R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C4)) ++#define IFX_HASH_D5R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C8)) ++ ++#define IFX_HMAC_KIDX ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00D0)) ++#define IFX_HMAC_KEY ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00D4)) ++#define IFX_HMAC_DBN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00D8)) ++ ++#define IFX_DEU_DMA_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00EC)) ++ ++#define IFX_DEU_IRNEN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00F4)) ++#define IFX_DEU_IRNCR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00F8)) ++#define IFX_DEU_IRNICR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00FC)) ++ ++ ++ ++/************************************************************************/ ++/* Module : PPE register address and bits */ ++/************************************************************************/ ++ ++#define IFX_PPE32_BASE (KSEG1 | 0x1E200000) ++#define IFX_PPE32_DEBUG_BREAK_TRACE_REG (IFX_PPE32_BASE + (0x0000 * 4)) ++#define IFX_PPE32_INT_MASK_STATUS_REG (IFX_PPE32_BASE + (0x0030 * 4)) ++#define IFX_PPE32_INT_RESOURCE_REG (IFX_PPE32_BASE + (0x0040 * 4)) ++#define IFX_PPE32_CDM_CODE_MEM_B0 (IFX_PPE32_BASE + (0x1000 * 4)) ++#define IFX_PPE32_CDM_CODE_MEM_B1 (IFX_PPE32_BASE + (0x2000 * 4)) ++#define IFX_PPE32_DATA_MEM_MAP_REG_BASE (IFX_PPE32_BASE + (0x4000 * 4)) ++ ++#define IFX_PPE32_SRST (IFX_PPE32_BASE + 0x10080) ++ ++/* ++ * ETOP MDIO Registers ++ */ ++#define IFX_PP32_ETOP_MDIO_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4))) ++#define IFX_PP32_ETOP_MDIO_ACC ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4))) ++#define IFX_PP32_ETOP_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4))) ++#define IFX_PP32_ETOP_IG_VLAN_COS ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4))) ++#define IFX_PP32_ETOP_IG_DSCP_COS3 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4))) ++#define IFX_PP32_ETOP_IG_DSCP_COS2 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4))) ++#define IFX_PP32_ETOP_IG_DSCP_COS1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4))) ++#define IFX_PP32_ETOP_IG_DSCP_COS0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4))) ++#define IFX_PP32_ETOP_IG_PLEN_CTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4))) ++#define IFX_PP32_ETOP_ISR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4))) ++#define IFX_PP32_ETOP_IER ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4))) ++#define IFX_PP32_ETOP_VPID ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4))) ++#define IFX_PP32_ENET_MAC_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4))) ++#define IFX_PP32_ENETS_DBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4))) ++#define IFX_PP32_ENETS_CBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4))) ++#define IFX_PP32_ENETS_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4))) ++#define IFX_PP32_ENETS_PGCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4))) ++#define IFX_PP32_ENETS_PKTCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4))) ++#define IFX_PP32_ENETS_BUF_CTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4))) ++#define IFX_PP32_ENETS_COS_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4))) ++#define IFX_PP32_ENETS_IGDROP ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4))) ++#define IFX_PP32_ENETS_IGERR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4))) ++#define IFX_PP32_ENET_MAC_DA0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4))) ++#define IFX_PP32_ENET_MAC_DA1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4))) ++ ++#define IFX_PP32_ENETF_DBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0630 * 4))) ++#define IFX_PP32_ENETF_CBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0631 * 4))) ++#define IFX_PP32_ENETF_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0632 * 4))) ++#define IFX_PP32_ENETF_PGCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0633 * 4))) ++#define IFX_PP32_ENETF_PKTCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0634 * 4))) ++#define IFX_PP32_ENETF_HFCTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0635 * 4))) ++#define IFX_PP32_ENETF_TXCTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0636 * 4))) ++ ++#define IFX_PP32_ENETF_VLCOS0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0638 * 4))) ++#define IFX_PP32_ENETF_VLCOS1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0639 * 4))) ++#define IFX_PP32_ENETF_VLCOS2 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063A * 4))) ++#define IFX_PP32_ENETF_VLCOS3 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063B * 4))) ++#define IFX_PP32_ENETF_EGERR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063C * 4))) ++#define IFX_PP32_ENETF_EGDROP ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063D * 4))) ++ ++ ++/* Sharebuff SB RAM2 control data */ ++#define IFX_PP32_SB2_DATABASE ((IFX_PPE32_BASE + (0x8C00 * 4))) ++#define IFX_PP32_SB2_CTRLBASE ((IFX_PPE32_BASE + (0x92E0 * 4))) ++ ++ ++ ++/************************************************************************/ ++/* Module : 3-port Switch register address and bits */ ++/************************************************************************/ ++ ++#define IFX_SW (KSEG1 | 0x1E108000) ++ ++#define IFX_SW_PS (IFX_SW + 0x000) ++#define IFX_SW_P0_CTL (IFX_SW + 0x004) ++#define IFX_SW_P1_CTL (IFX_SW + 0x008) ++#define IFX_SW_P2_CTL (IFX_SW + 0x00C) ++#define IFX_SW_P0_VLAN (IFX_SW + 0x010) ++#define IFX_SW_P1_VLAN (IFX_SW + 0x014) ++#define IFX_SW_P2_VLAN (IFX_SW + 0x018) ++#define IFX_SW_P0_INCTL (IFX_SW + 0x020) ++#define IFX_SW_P1_INCTL (IFX_SW + 0x024) ++#define IFX_SW_P2_INCTL (IFX_SW + 0x028) ++#define IFX_SW_DF_PORTMAP (IFX_SW + 0x02C) ++#define IFX_SW_P0_ECS_Q32 (IFX_SW + 0x030) ++#define IFX_SW_P0_ECS_Q10 (IFX_SW + 0x034) ++#define IFX_SW_P0_ECW_Q32 (IFX_SW + 0x038) ++#define IFX_SW_P0_ECW_Q10 (IFX_SW + 0x03C) ++#define IFX_SW_P1_ECS_Q32 (IFX_SW + 0x040) ++#define IFX_SW_P1_ECS_Q10 (IFX_SW + 0x044) ++#define IFX_SW_P1_ECW_Q32 (IFX_SW + 0x048) ++#define IFX_SW_P1_ECW_Q10 (IFX_SW + 0x04C) ++#define IFX_SW_P2_ECS_Q32 (IFX_SW + 0x050) ++#define IFX_SW_P2_ECS_Q10 (IFX_SW + 0x054) ++#define IFX_SW_P2_ECW_Q32 (IFX_SW + 0x058) ++#define IFX_SW_P2_ECW_Q10 (IFX_SW + 0x05C) ++#define IFX_SW_INT_ENA (IFX_SW + 0x060) ++#define IFX_SW_INT_ST (IFX_SW + 0x064) ++#define IFX_SW_GCTL0 (IFX_SW + 0x068) ++#define IFX_SW_GCTL1 (IFX_SW + 0x06C) ++#define IFX_SW_ARP (IFX_SW + 0x070) ++#define IFX_SW_STRM_CTL (IFX_SW + 0x074) ++#define IFX_SW_RGMII_CTL (IFX_SW + 0x078) ++#define IFX_SW_1P_PRT (IFX_SW + 0x07C) ++#define IFX_SW_GBKT_SZBS (IFX_SW + 0x080) ++#define IFX_SW_GBKT_SZEBS (IFX_SW + 0x084) ++#define IFX_SW_BF_TH (IFX_SW + 0x088) ++#define IFX_SW_PMAC_HD_CTL (IFX_SW + 0x08C) ++#define IFX_SW_PMAC_SA1 (IFX_SW + 0x090) ++#define IFX_SW_PMAC_SA2 (IFX_SW + 0x094) ++#define IFX_SW_PMAC_DA1 (IFX_SW + 0x098) ++#define IFX_SW_PMAC_DA2 (IFX_SW + 0x09C) ++#define IFX_SW_PMAC_VLAN (IFX_SW + 0x0A0) ++#define IFX_SW_PMAC_TX_IPG (IFX_SW + 0x0A4) ++#define IFX_SW_PMAC_RX_IPG (IFX_SW + 0x0A8) ++#define IFX_SW_ADR_TB_CTL0 (IFX_SW + 0x0AC) ++#define IFX_SW_ADR_TB_CTL1 (IFX_SW + 0x0B0) ++#define IFX_SW_ADR_TB_CTL2 (IFX_SW + 0x0B4) ++#define IFX_SW_ADR_TB_ST0 (IFX_SW + 0x0B8) ++#define IFX_SW_ADR_TB_ST1 (IFX_SW + 0x0BC) ++#define IFX_SW_ADR_TB_ST2 (IFX_SW + 0x0C0) ++#define IFX_SW_RMON_CTL (IFX_SW + 0x0C4) ++#define IFX_SW_RMON_ST (IFX_SW + 0x0C8) ++#define IFX_SW_MDIO_CTL (IFX_SW + 0x0CC) ++#define IFX_SW_MDIO_DATA (IFX_SW + 0x0D0) ++#define IFX_SW_TP_FLT_ACT (IFX_SW + 0x0D4) ++#define IFX_SW_PRTCL_FLT_ACT (IFX_SW + 0x0D8) ++#define IFX_SW_VLAN_FLT0 (IFX_SW + 0x100) ++#define IFX_SW_VLAN_FLT1 (IFX_SW + 0x104) ++#define IFX_SW_VLAN_FLT2 (IFX_SW + 0x108) ++#define IFX_SW_VLAN_FLT3 (IFX_SW + 0x10C) ++#define IFX_SW_VLAN_FLT4 (IFX_SW + 0x110) ++#define IFX_SW_VLAN_FLT5 (IFX_SW + 0x114) ++#define IFX_SW_VLAN_FLT6 (IFX_SW + 0x118) ++#define IFX_SW_VLAN_FLT7 (IFX_SW + 0x11C) ++#define IFX_SW_VLAN_FLT8 (IFX_SW + 0x120) ++#define IFX_SW_VLAN_FLT9 (IFX_SW + 0x124) ++#define IFX_SW_VLAN_FLT10 (IFX_SW + 0x128) ++#define IFX_SW_VLAN_FLT11 (IFX_SW + 0x12C) ++#define IFX_SW_VLAN_FLT12 (IFX_SW + 0x130) ++#define IFX_SW_VLAN_FLT13 (IFX_SW + 0x134) ++#define IFX_SW_VLAN_FLT14 (IFX_SW + 0x138) ++#define IFX_SW_VLAN_FLT15 (IFX_SW + 0x13C) ++#define IFX_SW_TP_FLT10 (IFX_SW + 0x140) ++#define IFX_SW_TP_FLT32 (IFX_SW + 0x144) ++#define IFX_SW_TP_FLT54 (IFX_SW + 0x148) ++#define IFX_SW_TP_FLT76 (IFX_SW + 0x14C) ++#define IFX_SW_DFSRV_MAP0 (IFX_SW + 0x150) ++#define IFX_SW_DFSRV_MAP1 (IFX_SW + 0x154) ++#define IFX_SW_DFSRV_MAP2 (IFX_SW + 0x158) ++#define IFX_SW_DFSRV_MAP3 (IFX_SW + 0x15C) ++#define IFX_SW_TCP_PF0 (IFX_SW + 0x160) ++#define IFX_SW_TCP_PF1 (IFX_SW + 0x164) ++#define IFX_SW_TCP_PF2 (IFX_SW + 0x168) ++#define IFX_SW_TCP_PF3 (IFX_SW + 0x16C) ++#define IFX_SW_TCP_PF4 (IFX_SW + 0x170) ++#define IFX_SW_TCP_PF5 (IFX_SW + 0x174) ++#define IFX_SW_TCP_PF6 (IFX_SW + 0x178) ++#define IFX_SW_TCP_PF7 (IFX_SW + 0x17C) ++#define IFX_SW_RA_03_00 (IFX_SW + 0x180) ++#define IFX_SW_RA_07_04 (IFX_SW + 0x184) ++#define IFX_SW_RA_0B_08 (IFX_SW + 0x188) ++#define IFX_SW_RA_0F_0C (IFX_SW + 0x18C) ++#define IFX_SW_RA_13_10 (IFX_SW + 0x190) ++#define IFX_SW_RA_17_14 (IFX_SW + 0x194) ++#define IFX_SW_RA_1B_18 (IFX_SW + 0x198) ++#define IFX_SW_RA_1F_1C (IFX_SW + 0x19C) ++#define IFX_SW_RA_23_20 (IFX_SW + 0x1A0) ++#define IFX_SW_RA_27_24 (IFX_SW + 0x1A4) ++#define IFX_SW_RA_2B_28 (IFX_SW + 0x1A8) ++#define IFX_SW_RA_2F_2C (IFX_SW + 0x1AC) ++#define IFX_SW_F0 (IFX_SW + 0x1B0) ++#define IFX_SW_F1 (IFX_SW + 0x1B4) ++ ++/************************************************************************/ ++/* Module : XBAR Register definition */ ++/************************************************************************/ ++#define IFX_XBAR_REG_BASE (KSEG1 | 0x1F400000) ++ ++#define IFX_XBAR_ALWAYS_LAST (volatile u32*)(IFX_XBAR_REG_BASE + 0x430) ++#define IFX_XBAR_FPI_BURST_EN 0x00000002 ++#define IFX_XBAR_AHB_BURST_EN 0x00000004 ++#define IFX_XBAR_DDR_SEL_EN 0x00000001 ++ ++/* ++ * Routine for Voice ++ */ ++extern const void (*ifx_bsp_basic_mps_decrypt)(unsigned int addr, int n); ++extern int ifx_is_vr9_a21_chip(void); ++ ++#endif /* VR9_H */ +diff --git a/arch/mips/include/asm/ifx/vr9/vr9_ref_board.h b/arch/mips/include/asm/ifx/vr9/vr9_ref_board.h +new file mode 100644 +index 0000000..4dfe3dc +--- /dev/null ++++ b/arch/mips/include/asm/ifx/vr9/vr9_ref_board.h +@@ -0,0 +1,46 @@ ++/****************************************************************************** ++** ++** FILE NAME : vr9_ref_board.h ++** PROJECT : IFX UEIP ++** MODULES : BSP Basic ++** ++** DATE : 27 May 2009 ++** AUTHOR : Xu Liang ++** DESCRIPTION : header file for VR9 ++** COPYRIGHT : Copyright (c) 2009 ++** Infineon Technologies AG ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 27 May 2009 Xu Liang The first UEIP release ++*******************************************************************************/ ++ ++ ++ ++#ifndef VR9_REF_BOARD_H ++#define VR9_REF_BOARD_H ++ ++#if defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) \ ++ || defined(CONFIG_IFX_USIF_SPI_FLASH) || defined (CONFIG_IFX_USIF_SPI_FLASH_MODULE) ++#define IFX_MTD_SPI_PART_NB 3 ++#define IFX_SPI_FLASH_MAX 8 ++#endif /* defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) */ ++ ++#if defined(CONFIG_USB_HOST_IFX) || defined(CONFIG_USB_HOST_IFX_MODULE) ++ #if 1 ++// #define IFX_GPIO_USB_VBUS IFX_GPIO_PIN_ID(2, 1) ++ #else ++ #define IFX_GPIO_USB_VBUS1 IFX_GPIO_PIN_ID(1, 13) ++ #define IFX_GPIO_USB_VBUS2 IFX_GPIO_PIN_ID(3, 0) ++ #endif ++#endif ++ ++ ++#endif /* VR9_REF_BOARD_H */ ++ +diff --git a/arch/mips/include/asm/ifx/war.h b/arch/mips/include/asm/ifx/war.h +new file mode 100644 +index 0000000..958d04d +--- /dev/null ++++ b/arch/mips/include/asm/ifx/war.h +@@ -0,0 +1,25 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle ++ */ ++#ifndef __ASM_MIPS_IFX_WAR_H ++#define __ASM_MIPS_IFX_WAR_H ++ ++#define R4600_V1_INDEX_ICACHEOP_WAR 0 ++#define R4600_V1_HIT_CACHEOP_WAR 0 ++#define R4600_V2_HIT_CACHEOP_WAR 0 ++#define R5432_CP0_INTERRUPT_WAR 0 ++#define BCM1250_M3_WAR 0 ++#define SIBYTE_1956_WAR 0 ++#define MIPS4K_ICACHE_REFILL_WAR 0 ++#define MIPS_CACHE_SYNC_WAR 0 ++#define TX49XX_ICACHE_INDEX_INV_WAR 0 ++#define RM9000_CDEX_SMP_WAR 0 ++#define ICACHE_REFILLS_WORKAROUND_WAR 0 ++#define R10000_LLSC_WAR 0 ++#define MIPS34K_MISSED_ITLB_WAR 0 ++ ++#endif /* __ASM_MIPS_IFX_WAR_H */ +diff --git a/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h +new file mode 100644 +index 0000000..c094e5d +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h +@@ -0,0 +1,58 @@ ++/* ++ * Lantiq FALCON specific CPU feature overrides ++ * ++ * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland ++ * ++ * This file was derived from: include/asm-mips/cpu-features.h ++ * Copyright (C) 2003, 2004 Ralf Baechle ++ * Copyright (C) 2004 Maciej W. Rozycki ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ */ ++#ifndef __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H ++#define __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H ++ ++#define cpu_has_tlb 1 ++#define cpu_has_4kex 1 ++#define cpu_has_3k_cache 0 ++#define cpu_has_4k_cache 1 ++#define cpu_has_tx39_cache 0 ++#define cpu_has_sb1_cache 0 ++#define cpu_has_fpu 0 ++#define cpu_has_32fpr 0 ++#define cpu_has_counter 1 ++#define cpu_has_watch 1 ++#define cpu_has_divec 1 ++ ++#define cpu_has_prefetch 1 ++#define cpu_has_ejtag 1 ++#define cpu_has_llsc 1 ++ ++#define cpu_has_mips16 1 ++#define cpu_has_mdmx 0 ++#define cpu_has_mips3d 0 ++#define cpu_has_smartmips 0 ++ ++#define cpu_has_mips32r1 1 ++#define cpu_has_mips32r2 1 ++#define cpu_has_mips64r1 0 ++#define cpu_has_mips64r2 0 ++ ++#define cpu_has_dsp 1 ++#define cpu_has_mipsmt 1 ++ ++#define cpu_has_vint 1 ++#define cpu_has_veic 1 ++ ++#define cpu_has_64bits 0 ++#define cpu_has_64bit_zero_reg 0 ++#define cpu_has_64bit_gp_regs 0 ++#define cpu_has_64bit_addresses 0 ++ ++#define cpu_dcache_line_size() 32 ++#define cpu_icache_line_size() 32 ++ ++#endif /* __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H */ +diff --git a/arch/mips/include/asm/mach-lantiq/falcon/ebu_reg.h b/arch/mips/include/asm/mach-lantiq/falcon/ebu_reg.h +new file mode 100644 +index 0000000..c47f5e1 +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/ebu_reg.h +@@ -0,0 +1,1520 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++ ++#ifndef _ebu_reg_h ++#define _ebu_reg_h ++ ++/** \addtogroup EBU_REGISTER ++ @{ ++*/ ++/* access macros */ ++#define ebu_r32(reg) reg_r32(&ebu->reg) ++#define ebu_w32(val, reg) reg_w32(val, &ebu->reg) ++#define ebu_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &ebu->reg) ++#define ebu_r32_table(reg, idx) reg_r32_table(ebu->reg, idx) ++#define ebu_w32_table(val, reg, idx) reg_w32_table(val, ebu->reg, idx) ++#define ebu_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, ebu->reg, idx) ++#define ebu_adr_table(reg, idx) adr_table(ebu->reg, idx) ++ ++ ++/** EBU register structure */ ++struct gpon_reg_ebu ++{ ++ /** Reserved */ ++ unsigned int res_0[2]; /* 0x00000000 */ ++ /** Module ID Register ++ Module type and version identifier */ ++ unsigned int modid; /* 0x00000008 */ ++ /** Module Control Register ++ This register contains general configuration information observed for all CS regions or dealing with EBU functionality that is not directly related to external memory access. */ ++ unsigned int modcon; /* 0x0000000C */ ++ /** Bus Read Configuration Register0 ++ Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */ ++ unsigned int busrcon0; /* 0x00000010 */ ++ /** Bus Read Parameters Register0 */ ++ unsigned int busrp0; /* 0x00000014 */ ++ /** Bus Write Configuration Register0 ++ Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */ ++ unsigned int buswcon0; /* 0x00000018 */ ++ /** Bus Write Parameters Register0 */ ++ unsigned int buswp0; /* 0x0000001C */ ++ /** Bus Read Configuration Register1 ++ Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */ ++ unsigned int busrcon1; /* 0x00000020 */ ++ /** Bus Read Parameters Register1 */ ++ unsigned int busrp1; /* 0x00000024 */ ++ /** Bus Write Configuration Register1 ++ Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */ ++ unsigned int buswcon1; /* 0x00000028 */ ++ /** Bus Write Parameters Register1 */ ++ unsigned int buswp1; /* 0x0000002C */ ++ /** Reserved */ ++ unsigned int res_1[8]; /* 0x00000030 */ ++ /** Bus Protocol Configuration Extension Register 0 */ ++ unsigned int busconext0; /* 0x00000050 */ ++ /** Bus Protocol Configuration Extension Register 1 */ ++ unsigned int busconext1; /* 0x00000054 */ ++ /** Reserved */ ++ unsigned int res_2[10]; /* 0x00000058 */ ++ /** Serial Flash Configuration Register ++ The content of this register configures the EBU's Serial Flash protocol engine. */ ++ unsigned int sfcon; /* 0x00000080 */ ++ /** Serial Flash Timing Register ++ This register defines the signal timing for the Serial Flash Access. See Section 3.18.3 on page 112 for details. */ ++ unsigned int sftime; /* 0x00000084 */ ++ /** Serial Flash Status Register ++ This register holds status information on the Serial Flash device(s) attached and the EBU's Serial Flash protocol engine. */ ++ unsigned int sfstat; /* 0x00000088 */ ++ /** Serial Flash Command Register ++ When writing to this register's opcode field, a command is started in the EBU's Serial Flash controller. */ ++ unsigned int sfcmd; /* 0x0000008C */ ++ /** Serial Flash Address Register ++ This register holds the address to be sent (if any) with accesses to/from a Serial Flash started by writing to EBU_SFCMD (Indirect Access Mode, see Section 3.18.2.4.1 on page 103). */ ++ unsigned int sfaddr; /* 0x00000090 */ ++ /** Serial Flash Data Register ++ This register holds the data being transferred (if any) with accesses to/from a Serial Flash started by writing to EBU_SFCMD (Indirect Access Mode, see Section 4.18.2.4.1 on page 116). */ ++ unsigned int sfdata; /* 0x00000094 */ ++ /** Serial Flash I/O Control Register ++ This register provides additional configuration for controlling the IO pads of the Serial Flash interface. */ ++ unsigned int sfio; /* 0x00000098 */ ++ /** Reserved */ ++ unsigned int res_3[25]; /* 0x0000009C */ ++}; ++ ++ ++/* Fields of "Module ID Register" */ ++/** Feature Select ++ This field indicates the types of external devices/protocols supported by the GPON version of the EBU. */ ++#define MODID_FSEL_MASK 0xE0000000 ++/** field offset */ ++#define MODID_FSEL_OFFSET 29 ++/** Support for SRAM, NAND/NOR/OneNand Flash and Cellular RAM is implemented. */ ++#define MODID_FSEL_SRAM_FLASH_CRAM 0x00000000 ++/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM and SDR SDRAM is implemented. */ ++#define MODID_FSEL_SRAM_FLASH_CRAM_SDR 0x20000000 ++/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM and SDR/DDR SDRAM is implemented. */ ++#define MODID_FSEL_SRAM_FLASH_CRAM_DDR 0x40000000 ++/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM, SDR/DDR SDRAM 0nd LPDDR-Flash is implemented. */ ++#define MODID_FSEL_SRAM_FLASH_CRAM_DDR_LPNVM 0x60000000 ++/** Serial Flash Support ++ Indicates whether or not the support of Serial Flash devices is available. */ ++#define MODID_SF 0x10000000 ++/* Not Available ++#define MODID_SF_NAV 0x00000000 */ ++/** Available */ ++#define MODID_SF_AV 0x10000000 ++/** AAD-mux Support ++ Indicates whether or not the GPON EBU supports AAD-mux protocol for Burst Flash and Cellular RAM. */ ++#define MODID_AAD 0x08000000 ++/* Not Available ++#define MODID_AAD_NAV 0x00000000 */ ++/** Available */ ++#define MODID_AAD_AV 0x08000000 ++/** Indicates whether or not the GPON EBU implements a DLL which is e.g. used for 50% duty cycle external clock generation. Note that a DLL is always implemented if DDR-SDRAM support is selected. */ ++#define MODID_DLL 0x04000000 ++/* Not Available ++#define MODID_DLL_NAV 0x00000000 */ ++/** Available */ ++#define MODID_DLL_AV 0x04000000 ++/** Pad Multiplexing Scheme */ ++#define MODID_PMS_MASK 0x03000000 ++/** field offset */ ++#define MODID_PMS_OFFSET 24 ++/** The EBU comprises of dedicated address pins A[EXTAW-1=:16]. */ ++#define MODID_PMS_PMS_CLASSIC 0x00000000 ++/** Revision ++ Revision Number */ ++#define MODID_REV_MASK 0x000F0000 ++/** field offset */ ++#define MODID_REV_OFFSET 16 ++/** Module ID ++ This field contains the EBU's unique peripheral ID. */ ++#define MODID_ID_MASK 0x0000FF00 ++/** field offset */ ++#define MODID_ID_OFFSET 8 ++/** Version ++ This field gives the EBU version number. */ ++#define MODID_VERSION_MASK 0x000000FF ++/** field offset */ ++#define MODID_VERSION_OFFSET 0 ++ ++/* Fields of "Module Control Register" */ ++/** Reserved */ ++#define MODCON_DLLUPDINT_MASK 0xC0000000 ++/** field offset */ ++#define MODCON_DLLUPDINT_OFFSET 30 ++/** Access Inhibit Acknowledge ++ After suspension of all accesses to the External Bus has been requested by setting bit acc_inh, acc_inh_ack acknowledges the request and inidcates that access suspension is now in effect. The bit is cleared when acc_inh gets deasserted. */ ++#define MODCON_AIA 0x02000000 ++/* no access restriction are active in the EBU subsystem ++#define MODCON_AIA_NO_INHIBIT 0x00000000 */ ++/** accesses are restricted to selected (configuration) system bus port(s) */ ++#define MODCON_AIA_INHIBIT 0x02000000 ++/** Access Inhibit request ++ Setting this bit will suspend all non-CPU system bus ports and the EBU itself from accessing the External Bus. This feature is usually used when the CPU needs to reconfigure protocol parameters in the EBU in order to avoid external accesses with invalid settings. The EBU acknowledges that the access suspension is in effect by asserting acc_inh_ack. */ ++#define MODCON_AI 0x01000000 ++/* no access restriction are active in the EBU subsystem ++#define MODCON_AI_NO_INHIBIT 0x00000000 */ ++/** accesses are restricted to selected (configuration) system bus port(s) */ ++#define MODCON_AI_INHIBIT 0x01000000 ++/** Lock Timeout */ ++#define MODCON_LTO_MASK 0x00FF0000 ++/** field offset */ ++#define MODCON_LTO_OFFSET 16 ++/** Reserved */ ++#define MODCON_DDREN 0x00008000 ++/** Pad Drive Control ++ Intended to be used to control the EBU pad''s drive strength. Refer to the GPON chip specification to see which drive strnegth options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */ ++#define MODCON_PEXT 0x00004000 ++/* Normal drive ++#define MODCON_PEXT_NORMAL 0x00000000 */ ++/** Strong drive */ ++#define MODCON_PEXT_STRONG 0x00004000 ++/** Pad Slew Falling Edge Control ++ Intended to be used to trim the External Bus pad's falling edge slew rate. Refer to the GPON chip specification to see which slew rate options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */ ++#define MODCON_SLF 0x00002000 ++/* Slow slew rate ++#define MODCON_SLF_SLOW 0x00000000 */ ++/** Fast slew rate */ ++#define MODCON_SLF_FAST 0x00002000 ++/** Pad Slew Rising Edge Control ++ Intended to be used to trim the External Bus pad's rising edge slew rate. Refer to the GPON chip specification to see which slew rate options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */ ++#define MODCON_SLR 0x00001000 ++/* Slow slew rate ++#define MODCON_SLR_SLOW 0x00000000 */ ++/** Fast slew rate */ ++#define MODCON_SLR_FAST 0x00001000 ++/** Write Buffering Mode ++ This bit controls when the EBU starts a new write burst transaction from the Memport interface. */ ++#define MODCON_WBM 0x00000040 ++/* The EBU starts a write transaction on the External Bus as early as possible, expecting that the n beats of the write burst will be transferred within n or n+1 clock cycles over the EBU's Memport interface. Use this mode if the EBU is clocked at the same or a slower frequency than the system bus interconnect. ++#define MODCON_WBM_START_WRITE_EARLY 0x00000000 */ ++/** The EBU start a write transaction only after all data of a write burst have been received over the EBU's Memport interface. Use this mode if the EBU is clocked at a higher frequency than the system bus interrconnect. */ ++#define MODCON_WBM_START_WRITE_LATE 0x00000040 ++/** Reserved */ ++#define MODCON_SDCLKEN 0x00000020 ++/** Standby Mode Enable ++ When set allows the EBU subsystem to enter standby mode in response to a rising edge on input signal standby_req_i. See Section 3.9.3 for details. */ ++#define MODCON_STBYEN 0x00000010 ++/* Disable ++#define MODCON_STBYEN_DIS 0x00000000 */ ++/** Enable */ ++#define MODCON_STBYEN_EN 0x00000010 ++/** Enable BFCLK1 ++ This field will enables or disables mirroring the clock that is output on BFCLKO_0 also on pad BFCLKO_1 to double the drive strength. See also Section 3.17.3) */ ++#define MODCON_BFCLK1EN 0x00000008 ++/* Disable ++#define MODCON_BFCLK1EN_DIS 0x00000000 */ ++/** Enable */ ++#define MODCON_BFCLK1EN_EN 0x00000008 ++/** Ready/Busy Status Edge ++ This is a read-only bit which shows a change of the logic level shown in the sts field since last read. It is reset by a read access. */ ++#define MODCON_STSEDGE 0x00000004 ++/** Ready/Busy Status ++ This is a read-only bit which reflects the current logic level present on the RDY/BSY or STS input pin which is (optionally) fed-in from a General Purpose I/O pad which is not part of the EBU via the EBU's input pin signal gpio_nand_rdy_ */ ++#define MODCON_STS 0x00000002 ++/** External Bus Arbitration Mode ++ This bit allows to disconnect the EBU from the External Bus. While EBU_MODCON.acc_inh_ack is 0, the value of arb_mode is forced to OWN_BUS. */ ++#define MODCON_AM 0x00000001 ++/* The EBU does not own the bus (multi-master) ++#define MODCON_AM_SHAREDBUS 0x00000000 */ ++/** The EBU owns the external bus. */ ++#define MODCON_AM_OWNBUS 0x00000001 ++ ++/* Fields of "Bus Read Configuration Register0" */ ++/** Device Type For Region ++ After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */ ++#define BUSRCON0_AGEN_MASK 0xF0000000 ++/** field offset */ ++#define BUSRCON0_AGEN_OFFSET 28 ++/** Muxed Asynchronous Type External Memory */ ++#define BUSRCON0_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000 ++/** Muxed Burst Type External Memory */ ++#define BUSRCON0_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000 ++/** NAND Flash (page optimised) */ ++#define BUSRCON0_AGEN_NAND_FLASH 0x20000000 ++/** Muxed Cellular RAM External Memory */ ++#define BUSRCON0_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000 ++/** Demuxed Asynchronous Type External Memory */ ++#define BUSRCON0_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000 ++/** Demuxed Burst Type External Memory */ ++#define BUSRCON0_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000 ++/** Demuxed Page Mode External Memory */ ++#define BUSRCON0_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000 ++/** Demuxed Cellular RAM External Memory */ ++#define BUSRCON0_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000 ++/** Serial Flash */ ++#define BUSRCON0_AGEN_SERIAL_FLASH 0xF0000000 ++/** Device Addressing Mode ++ t.b.d. */ ++#define BUSRCON0_PORTW_MASK 0x0C000000 ++/** field offset */ ++#define BUSRCON0_PORTW_OFFSET 26 ++/** 8-bit multiplexed */ ++#define BUSRCON0_PORTW_8_BIT_MUX 0x00000000 ++/** 16-bit multiplexed */ ++#define BUSRCON0_PORTW_16_BIT_MUX 0x04000000 ++/** Twin, 16-bit multiplexed */ ++#define BUSRCON0_PORTW_TWIN_16_BIT_MUX 0x08000000 ++/** 32-bit multiplexed */ ++#define BUSRCON0_PORTW_32_BIT_MUX 0x0C000000 ++/** External Wait Control ++ Function of the WAIT input. This is specific to the device type (i.e. the agen field). */ ++#define BUSRCON0_WAIT_MASK 0x03000000 ++/** field offset */ ++#define BUSRCON0_WAIT_OFFSET 24 ++/** WAIT is ignored (default after reset). */ ++#define BUSRCON0_WAIT_OFF 0x00000000 ++/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */ ++#define BUSRCON0_WAIT_EARLY_WAIT 0x01000000 ++/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */ ++#define BUSRCON0_WAIT_TWO_STAGE_SYNC 0x01000000 ++/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */ ++#define BUSRCON0_WAIT_WAIT_WITH_DATA 0x02000000 ++/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */ ++#define BUSRCON0_WAIT_SINGLE_STAGE_SYNC 0x02000000 ++/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */ ++#define BUSRCON0_WAIT_ABORT_AND_RETRY 0x03000000 ++/** Disable Burst Address Wrapping */ ++#define BUSRCON0_DBA 0x00800000 ++/** Reversed polarity at wait */ ++#define BUSRCON0_WAITINV 0x00400000 ++/* Low active. ++#define BUSRCON0_WAITINV_ACTLOW 0x00000000 */ ++/** High active */ ++#define BUSRCON0_WAITINV_ACTHI 0x00400000 ++/** Early ADV Enable for Synchronous Bursts */ ++#define BUSRCON0_EBSE 0x00200000 ++/* Low active. ++#define BUSRCON0_EBSE_DELAYED 0x00000000 */ ++/** High active */ ++#define BUSRCON0_EBSE_NOT_DELAYED 0x00200000 ++/** Early Control Signals for Synchronous Bursts */ ++#define BUSRCON0_ECSE 0x00100000 ++/* Low active. ++#define BUSRCON0_ECSE_DELAYED 0x00000000 */ ++/** High active */ ++#define BUSRCON0_ECSE_NOT_DELAYED 0x00100000 ++/** Synchronous Burst Buffer Mode Select */ ++#define BUSRCON0_FBBMSEL 0x00080000 ++/* FIXED_LENGTH ++#define BUSRCON0_FBBMSEL_FIXED_LENGTH 0x00000000 */ ++/** CONTINUOUS */ ++#define BUSRCON0_FBBMSEL_CONTINUOUS 0x00080000 ++/** Burst Length for Synchronous Burst */ ++#define BUSRCON0_FETBLEN_MASK 0x00070000 ++/** field offset */ ++#define BUSRCON0_FETBLEN_OFFSET 16 ++/** Up to 1 data cycle (default after reset). */ ++#define BUSRCON0_FETBLEN_SINGLE 0x00000000 ++/** Up to 2 data cycles. */ ++#define BUSRCON0_FETBLEN_BURST2 0x00010000 ++/** Up to 4 data cycles. */ ++#define BUSRCON0_FETBLEN_BURST4 0x00020000 ++/** Up to 8 data cycles. */ ++#define BUSRCON0_FETBLEN_BURST8 0x00030000 ++/** Up to 16 data cycles. */ ++#define BUSRCON0_FETBLEN_BURST16 0x00040000 ++/** Reserved ++ This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */ ++#define BUSRCON0_NANDAMAP_MASK 0x0000C000 ++/** field offset */ ++#define BUSRCON0_NANDAMAP_OFFSET 14 ++/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ ++#define BUSRCON0_NANDAMAP_NAND_A17_16 0x00000000 ++/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ ++#define BUSRCON0_NANDAMAP_NAND_WAIT_ADV 0x00004000 ++/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */ ++#define BUSRCON0_NANDAMAP_NAND_AD9_8 0x00008000 ++/** Reserved for future use. Do not use or unpredictable results may occur. */ ++#define BUSRCON0_NANDAMAP_NAND_RFU 0x0000C000 ++/** AAD-mux Protocol ++ If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */ ++#define BUSRCON0_AADMUX 0x00002000 ++/* Muxed device is write accessed in AD-mux mode. ++#define BUSRCON0_AADMUX_AD_MUX 0x00000000 */ ++/** Muxed device is write accessed in AAD-mux mode. */ ++#define BUSRCON0_AADMUX_AAD_MUX 0x00002000 ++/** Asynchronous Address Phase */ ++#define BUSRCON0_AAP 0x00001000 ++/* Clock is enabled at beginning of access. ++#define BUSRCON0_AAP_EARLY 0x00000000 */ ++/** Clock is enabled after address phase. */ ++#define BUSRCON0_AAP_LATE 0x00001000 ++/** Burst Flash Read Single Stage Synchronisation */ ++#define BUSRCON0_BFSSS 0x00000800 ++/* Two stages of synchronisation used. ++#define BUSRCON0_BFSSS_TWO_STAGE 0x00000000 */ ++/** Single stage of synchronisation used. */ ++#define BUSRCON0_BFSSS_SINGLE_STAGE 0x00000800 ++/** Burst Flash Clock Feedback Enable */ ++#define BUSRCON0_FDBKEN 0x00000400 ++/* Disable ++#define BUSRCON0_FDBKEN_DIS 0x00000000 */ ++/** Enable */ ++#define BUSRCON0_FDBKEN_EN 0x00000400 ++/** Auxiliary Chip Select Enable ++ Not supported in GPON-EBU, field must be set to 0. */ ++#define BUSRCON0_CSA 0x00000200 ++/* Disable ++#define BUSRCON0_CSA_DIS 0x00000000 */ ++/** Enable */ ++#define BUSRCON0_CSA_EN 0x00000200 ++/** Flash Non-Array Access Enable ++ Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */ ++#define BUSRCON0_NAA 0x00000100 ++/* Disable ++#define BUSRCON0_NAA_DIS 0x00000000 */ ++/** Enable */ ++#define BUSRCON0_NAA_EN 0x00000100 ++/** Module Enable */ ++#define BUSRCON0_ENABLE 0x00000001 ++/* Disable ++#define BUSRCON0_ENABLE_DIS 0x00000000 */ ++/** Enable */ ++#define BUSRCON0_ENABLE_EN 0x00000001 ++ ++/* Fields of "Bus Read Parameters Register0" */ ++/** Address Cycles ++ Number of cycles for address phase. */ ++#define BUSRP0_ADDRC_MASK 0xF0000000 ++/** field offset */ ++#define BUSRP0_ADDRC_OFFSET 28 ++/** Address Hold Cycles For Multiplexed Address ++ Number of address hold cycles during multiplexed accesses. */ ++#define BUSRP0_ADHOLC_MASK 0x0F000000 ++/** field offset */ ++#define BUSRP0_ADHOLC_OFFSET 24 ++/** Programmed Command Delay Cycles ++ Number of delay cycles during command delay phase. */ ++#define BUSRP0_CMDDELAY_MASK 0x00F00000 ++/** field offset */ ++#define BUSRP0_CMDDELAY_OFFSET 20 ++/** Extended Data */ ++#define BUSRP0_EXTDATA_MASK 0x000C0000 ++/** field offset */ ++#define BUSRP0_EXTDATA_OFFSET 18 ++/** External device outputs data every BFCLK cycle */ ++#define BUSRP0_EXTDATA_ONE 0x00000000 ++/** External device outputs data every 2nd BFCLK cycles */ ++#define BUSRP0_EXTDATA_TWO 0x00040000 ++/** External device outputs data every 4th BFCLK cycles */ ++#define BUSRP0_EXTDATA_FOUR 0x00080000 ++/** External device outputs data every 8th BFCLK cycles */ ++#define BUSRP0_EXTDATA_EIGHT 0x000C0000 ++/** Frequency of external clock at pin BFCLKO */ ++#define BUSRP0_EXTCLOCK_MASK 0x00030000 ++/** field offset */ ++#define BUSRP0_EXTCLOCK_OFFSET 16 ++/** Equal to ebu_clk frequency. */ ++#define BUSRP0_EXTCLOCK_ONE_TO_ONE 0x00000000 ++/** 1/2 of ebu_clk frequency. */ ++#define BUSRP0_EXTCLOCK_ONE_TO_TWO 0x00010000 ++/** 1/3 of ebu_clk frequency. */ ++#define BUSRP0_EXTCLOCK_ONE_TO_THREE 0x00020000 ++/** 1/4 of ebu_clk frequency (default after reset). */ ++#define BUSRP0_EXTCLOCK_ONE_TO_FOUR 0x00030000 ++/** Data Hold Cycles For read Accesses ++ Number of data hold cycles during read accesses. Applies to spinner support only where the address is guaranteed stable for datac clocks after RD high */ ++#define BUSRP0_DATAC_MASK 0x0000F000 ++/** field offset */ ++#define BUSRP0_DATAC_OFFSET 12 ++/** Programmed Wait States for read accesses ++ Number of programmed wait states for read accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */ ++#define BUSRP0_WAITRDC_MASK 0x00000F80 ++/** field offset */ ++#define BUSRP0_WAITRDC_OFFSET 7 ++/** Recovery Cycles After read Accesses, same CS ++ Number of idle cycles after read accesses when the next access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */ ++#define BUSRP0_RECOVC_MASK 0x00000070 ++/** field offset */ ++#define BUSRP0_RECOVC_OFFSET 4 ++/** Recovery Cycles After read Accesses, other CS ++ Number of idle cycles after read accesses when the next access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */ ++#define BUSRP0_DTACS_MASK 0x0000000F ++/** field offset */ ++#define BUSRP0_DTACS_OFFSET 0 ++ ++/* Fields of "Bus Write Configuration Register0" */ ++/** Device Type For Region ++ After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */ ++#define BUSWCON0_AGEN_MASK 0xF0000000 ++/** field offset */ ++#define BUSWCON0_AGEN_OFFSET 28 ++/** Muxed Asynchronous Type External Memory */ ++#define BUSWCON0_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000 ++/** Muxed Burst Type External Memory */ ++#define BUSWCON0_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000 ++/** NAND Flash (page optimised) */ ++#define BUSWCON0_AGEN_NAND_FLASH 0x20000000 ++/** Muxed Cellular RAM External Memory */ ++#define BUSWCON0_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000 ++/** Demuxed Asynchronous Type External Memory */ ++#define BUSWCON0_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000 ++/** Demuxed Burst Type External Memory */ ++#define BUSWCON0_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000 ++/** Demuxed Page Mode External Memory */ ++#define BUSWCON0_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000 ++/** Demuxed Cellular RAM External Memory */ ++#define BUSWCON0_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000 ++/** Serial Flash */ ++#define BUSWCON0_AGEN_SERIAL_FLASH 0xF0000000 ++/** Device Addressing Mode ++ t.b.d. */ ++#define BUSWCON0_PORTW_MASK 0x0C000000 ++/** field offset */ ++#define BUSWCON0_PORTW_OFFSET 26 ++/** External Wait Control ++ Function of the WAIT input. This is specific to the device type (i.e. the agen field). */ ++#define BUSWCON0_WAIT_MASK 0x03000000 ++/** field offset */ ++#define BUSWCON0_WAIT_OFFSET 24 ++/** WAIT is ignored (default after reset). */ ++#define BUSWCON0_WAIT_OFF 0x00000000 ++/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */ ++#define BUSWCON0_WAIT_EARLY_WAIT 0x01000000 ++/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */ ++#define BUSWCON0_WAIT_TWO_STAGE_SYNC 0x01000000 ++/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */ ++#define BUSWCON0_WAIT_WAIT_WITH_DATA 0x02000000 ++/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */ ++#define BUSWCON0_WAIT_SINGLE_STAGE_SYNC 0x02000000 ++/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */ ++#define BUSWCON0_WAIT_ABORT_AND_RETRY 0x03000000 ++/** Reserved */ ++#define BUSWCON0_LOCKCS 0x00800000 ++/** Reversed polarity at wait */ ++#define BUSWCON0_WAITINV 0x00400000 ++/* Low active. ++#define BUSWCON0_WAITINV_ACTLOW 0x00000000 */ ++/** High active */ ++#define BUSWCON0_WAITINV_ACTHI 0x00400000 ++/** Early ADV Enable for Synchronous Bursts */ ++#define BUSWCON0_EBSE 0x00200000 ++/* Low active. ++#define BUSWCON0_EBSE_DELAYED 0x00000000 */ ++/** High active */ ++#define BUSWCON0_EBSE_NOT_DELAYED 0x00200000 ++/** Early Control Signals for Synchronous Bursts */ ++#define BUSWCON0_ECSE 0x00100000 ++/* Low active. ++#define BUSWCON0_ECSE_DELAYED 0x00000000 */ ++/** High active */ ++#define BUSWCON0_ECSE_NOT_DELAYED 0x00100000 ++/** Synchronous Burst Buffer Mode Select */ ++#define BUSWCON0_FBBMSEL 0x00080000 ++/* FIXED_LENGTH ++#define BUSWCON0_FBBMSEL_FIXED_LENGTH 0x00000000 */ ++/** CONTINUOUS */ ++#define BUSWCON0_FBBMSEL_CONTINUOUS 0x00080000 ++/** Burst Length for Synchronous Burst */ ++#define BUSWCON0_FETBLEN_MASK 0x00070000 ++/** field offset */ ++#define BUSWCON0_FETBLEN_OFFSET 16 ++/** Up to 1 data cycle (default after reset). */ ++#define BUSWCON0_FETBLEN_SINGLE 0x00000000 ++/** Up to 2 data cycles. */ ++#define BUSWCON0_FETBLEN_BURST2 0x00010000 ++/** Up to 4 data cycles. */ ++#define BUSWCON0_FETBLEN_BURST4 0x00020000 ++/** Up to 8 data cycles. */ ++#define BUSWCON0_FETBLEN_BURST8 0x00030000 ++/** Up to 16 data cycles. */ ++#define BUSWCON0_FETBLEN_BURST16 0x00040000 ++/** Reserved ++ This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */ ++#define BUSWCON0_NANDAMAP_MASK 0x0000C000 ++/** field offset */ ++#define BUSWCON0_NANDAMAP_OFFSET 14 ++/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ ++#define BUSWCON0_NANDAMAP_NAND_A17_16 0x00000000 ++/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ ++#define BUSWCON0_NANDAMAP_NAND_WAIT_ADV 0x00004000 ++/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */ ++#define BUSWCON0_NANDAMAP_NAND_AD9_8 0x00008000 ++/** Reserved for future use. Do not use or unpredictable results may occur. */ ++#define BUSWCON0_NANDAMAP_NAND_RFU 0x0000C000 ++/** AAD-mux Protocol ++ If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */ ++#define BUSWCON0_AADMUX 0x00002000 ++/* Muxed device is write accessed in AD-mux mode. ++#define BUSWCON0_AADMUX_AD_MUX 0x00000000 */ ++/** Muxed device is write accessed in AAD-mux mode. */ ++#define BUSWCON0_AADMUX_AAD_MUX 0x00002000 ++/** Asynchronous Address Phase */ ++#define BUSWCON0_AAP 0x00001000 ++/* Clock is enabled at beginning of access. ++#define BUSWCON0_AAP_EARLY 0x00000000 */ ++/** Clock is enabled after address phase. */ ++#define BUSWCON0_AAP_LATE 0x00001000 ++/** Auxiliary Chip Select Enable ++ Not supported in GPON-EBU, field must be set to 0. */ ++#define BUSWCON0_CSA 0x00000200 ++/* Disable ++#define BUSWCON0_CSA_DIS 0x00000000 */ ++/** Enable */ ++#define BUSWCON0_CSA_EN 0x00000200 ++/** Flash Non-Array Access Enable ++ Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */ ++#define BUSWCON0_NAA 0x00000100 ++/* Disable ++#define BUSWCON0_NAA_DIS 0x00000000 */ ++/** Enable */ ++#define BUSWCON0_NAA_EN 0x00000100 ++/** Module Enable */ ++#define BUSWCON0_ENABLE 0x00000001 ++/* Disable ++#define BUSWCON0_ENABLE_DIS 0x00000000 */ ++/** Enable */ ++#define BUSWCON0_ENABLE_EN 0x00000001 ++ ++/* Fields of "Bus Write Parameters Register0" */ ++/** Address Cycles ++ Number of cycles for address phase. */ ++#define BUSWP0_ADDRC_MASK 0xF0000000 ++/** field offset */ ++#define BUSWP0_ADDRC_OFFSET 28 ++/** Address Hold Cycles For Multiplexed Address ++ Number of address hold cycles during multiplexed accesses. */ ++#define BUSWP0_ADHOLC_MASK 0x0F000000 ++/** field offset */ ++#define BUSWP0_ADHOLC_OFFSET 24 ++/** Programmed Command Delay Cycles ++ Number of delay cycles during command delay phase. */ ++#define BUSWP0_CMDDELAY_MASK 0x00F00000 ++/** field offset */ ++#define BUSWP0_CMDDELAY_OFFSET 20 ++/** Extended Data */ ++#define BUSWP0_EXTDATA_MASK 0x000C0000 ++/** field offset */ ++#define BUSWP0_EXTDATA_OFFSET 18 ++/** External device outputs data every BFCLK cycle */ ++#define BUSWP0_EXTDATA_ONE 0x00000000 ++/** External device outputs data every 2nd BFCLK cycles */ ++#define BUSWP0_EXTDATA_TWO 0x00040000 ++/** External device outputs data every 4th BFCLK cycles */ ++#define BUSWP0_EXTDATA_FOUR 0x00080000 ++/** External device outputs data every 8th BFCLK cycles */ ++#define BUSWP0_EXTDATA_EIGHT 0x000C0000 ++/** Frequency of external clock at pin BFCLKO */ ++#define BUSWP0_EXTCLOCK_MASK 0x00030000 ++/** field offset */ ++#define BUSWP0_EXTCLOCK_OFFSET 16 ++/** Equal to ebu_clk frequency. */ ++#define BUSWP0_EXTCLOCK_ONE_TO_ONE 0x00000000 ++/** 1/2 of ebu_clk frequency. */ ++#define BUSWP0_EXTCLOCK_ONE_TO_TWO 0x00010000 ++/** 1/3 of ebu_clk frequency. */ ++#define BUSWP0_EXTCLOCK_ONE_TO_THREE 0x00020000 ++/** 1/4 of ebu_clk frequency (default after reset). */ ++#define BUSWP0_EXTCLOCK_ONE_TO_FOUR 0x00030000 ++/** Data Hold Cycles For write Accesses ++ Number of data hold cycles during write accesses. */ ++#define BUSWP0_DATAC_MASK 0x0000F000 ++/** field offset */ ++#define BUSWP0_DATAC_OFFSET 12 ++/** Programmed Wait States For write Accesses ++ Number of programmed wait states for write accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */ ++#define BUSWP0_WAITWDC_MASK 0x00000F80 ++/** field offset */ ++#define BUSWP0_WAITWDC_OFFSET 7 ++/** Recovery Cycles After write Accesses, same CS ++ Number of idle cycles after write accesses when following access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */ ++#define BUSWP0_RECOVC_MASK 0x00000070 ++/** field offset */ ++#define BUSWP0_RECOVC_OFFSET 4 ++/** Recovery Cycles After write Accesses, other CS ++ Number of idle cycles after write accesses when the following access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */ ++#define BUSWP0_DTACS_MASK 0x0000000F ++/** field offset */ ++#define BUSWP0_DTACS_OFFSET 0 ++ ++/* Fields of "Bus Read Configuration Register1" */ ++/** Device Type For Region ++ After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */ ++#define BUSRCON1_AGEN_MASK 0xF0000000 ++/** field offset */ ++#define BUSRCON1_AGEN_OFFSET 28 ++/** Muxed Asynchronous Type External Memory */ ++#define BUSRCON1_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000 ++/** Muxed Burst Type External Memory */ ++#define BUSRCON1_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000 ++/** NAND Flash (page optimised) */ ++#define BUSRCON1_AGEN_NAND_FLASH 0x20000000 ++/** Muxed Cellular RAM External Memory */ ++#define BUSRCON1_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000 ++/** Demuxed Asynchronous Type External Memory */ ++#define BUSRCON1_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000 ++/** Demuxed Burst Type External Memory */ ++#define BUSRCON1_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000 ++/** Demuxed Page Mode External Memory */ ++#define BUSRCON1_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000 ++/** Demuxed Cellular RAM External Memory */ ++#define BUSRCON1_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000 ++/** Serial Flash */ ++#define BUSRCON1_AGEN_SERIAL_FLASH 0xF0000000 ++/** Device Addressing Mode ++ t.b.d. */ ++#define BUSRCON1_PORTW_MASK 0x0C000000 ++/** field offset */ ++#define BUSRCON1_PORTW_OFFSET 26 ++/** 8-bit multiplexed */ ++#define BUSRCON1_PORTW_8_BIT_MUX 0x00000000 ++/** 16-bit multiplexed */ ++#define BUSRCON1_PORTW_16_BIT_MUX 0x04000000 ++/** Twin, 16-bit multiplexed */ ++#define BUSRCON1_PORTW_TWIN_16_BIT_MUX 0x08000000 ++/** 32-bit multiplexed */ ++#define BUSRCON1_PORTW_32_BIT_MUX 0x0C000000 ++/** External Wait Control ++ Function of the WAIT input. This is specific to the device type (i.e. the agen field). */ ++#define BUSRCON1_WAIT_MASK 0x03000000 ++/** field offset */ ++#define BUSRCON1_WAIT_OFFSET 24 ++/** WAIT is ignored (default after reset). */ ++#define BUSRCON1_WAIT_OFF 0x00000000 ++/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */ ++#define BUSRCON1_WAIT_EARLY_WAIT 0x01000000 ++/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */ ++#define BUSRCON1_WAIT_TWO_STAGE_SYNC 0x01000000 ++/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */ ++#define BUSRCON1_WAIT_WAIT_WITH_DATA 0x02000000 ++/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */ ++#define BUSRCON1_WAIT_SINGLE_STAGE_SYNC 0x02000000 ++/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */ ++#define BUSRCON1_WAIT_ABORT_AND_RETRY 0x03000000 ++/** Disable Burst Address Wrapping */ ++#define BUSRCON1_DBA 0x00800000 ++/** Reversed polarity at wait */ ++#define BUSRCON1_WAITINV 0x00400000 ++/* Low active. ++#define BUSRCON1_WAITINV_ACTLOW 0x00000000 */ ++/** High active */ ++#define BUSRCON1_WAITINV_ACTHI 0x00400000 ++/** Early ADV Enable for Synchronous Bursts */ ++#define BUSRCON1_EBSE 0x00200000 ++/* Low active. ++#define BUSRCON1_EBSE_DELAYED 0x00000000 */ ++/** High active */ ++#define BUSRCON1_EBSE_NOT_DELAYED 0x00200000 ++/** Early Control Signals for Synchronous Bursts */ ++#define BUSRCON1_ECSE 0x00100000 ++/* Low active. ++#define BUSRCON1_ECSE_DELAYED 0x00000000 */ ++/** High active */ ++#define BUSRCON1_ECSE_NOT_DELAYED 0x00100000 ++/** Synchronous Burst Buffer Mode Select */ ++#define BUSRCON1_FBBMSEL 0x00080000 ++/* FIXED_LENGTH ++#define BUSRCON1_FBBMSEL_FIXED_LENGTH 0x00000000 */ ++/** CONTINUOUS */ ++#define BUSRCON1_FBBMSEL_CONTINUOUS 0x00080000 ++/** Burst Length for Synchronous Burst */ ++#define BUSRCON1_FETBLEN_MASK 0x00070000 ++/** field offset */ ++#define BUSRCON1_FETBLEN_OFFSET 16 ++/** Up to 1 data cycle (default after reset). */ ++#define BUSRCON1_FETBLEN_SINGLE 0x00000000 ++/** Up to 2 data cycles. */ ++#define BUSRCON1_FETBLEN_BURST2 0x00010000 ++/** Up to 4 data cycles. */ ++#define BUSRCON1_FETBLEN_BURST4 0x00020000 ++/** Up to 8 data cycles. */ ++#define BUSRCON1_FETBLEN_BURST8 0x00030000 ++/** Up to 16 data cycles. */ ++#define BUSRCON1_FETBLEN_BURST16 0x00040000 ++/** Reserved ++ This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */ ++#define BUSRCON1_NANDAMAP_MASK 0x0000C000 ++/** field offset */ ++#define BUSRCON1_NANDAMAP_OFFSET 14 ++/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ ++#define BUSRCON1_NANDAMAP_NAND_A17_16 0x00000000 ++/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ ++#define BUSRCON1_NANDAMAP_NAND_WAIT_ADV 0x00004000 ++/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */ ++#define BUSRCON1_NANDAMAP_NAND_AD9_8 0x00008000 ++/** Reserved for future use. Do not use or unpredictable results may occur. */ ++#define BUSRCON1_NANDAMAP_NAND_RFU 0x0000C000 ++/** AAD-mux Protocol ++ If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */ ++#define BUSRCON1_AADMUX 0x00002000 ++/* Muxed device is write accessed in AD-mux mode. ++#define BUSRCON1_AADMUX_AD_MUX 0x00000000 */ ++/** Muxed device is write accessed in AAD-mux mode. */ ++#define BUSRCON1_AADMUX_AAD_MUX 0x00002000 ++/** Asynchronous Address Phase */ ++#define BUSRCON1_AAP 0x00001000 ++/* Clock is enabled at beginning of access. ++#define BUSRCON1_AAP_EARLY 0x00000000 */ ++/** Clock is enabled after address phase. */ ++#define BUSRCON1_AAP_LATE 0x00001000 ++/** Burst Flash Read Single Stage Synchronisation */ ++#define BUSRCON1_BFSSS 0x00000800 ++/* Two stages of synchronisation used. ++#define BUSRCON1_BFSSS_TWO_STAGE 0x00000000 */ ++/** Single stage of synchronisation used. */ ++#define BUSRCON1_BFSSS_SINGLE_STAGE 0x00000800 ++/** Burst Flash Clock Feedback Enable */ ++#define BUSRCON1_FDBKEN 0x00000400 ++/* Disable ++#define BUSRCON1_FDBKEN_DIS 0x00000000 */ ++/** Enable */ ++#define BUSRCON1_FDBKEN_EN 0x00000400 ++/** Auxiliary Chip Select Enable ++ Not supported in GPON-EBU, field must be set to 0. */ ++#define BUSRCON1_CSA 0x00000200 ++/* Disable ++#define BUSRCON1_CSA_DIS 0x00000000 */ ++/** Enable */ ++#define BUSRCON1_CSA_EN 0x00000200 ++/** Flash Non-Array Access Enable ++ Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */ ++#define BUSRCON1_NAA 0x00000100 ++/* Disable ++#define BUSRCON1_NAA_DIS 0x00000000 */ ++/** Enable */ ++#define BUSRCON1_NAA_EN 0x00000100 ++/** Module Enable */ ++#define BUSRCON1_ENABLE 0x00000001 ++/* Disable ++#define BUSRCON1_ENABLE_DIS 0x00000000 */ ++/** Enable */ ++#define BUSRCON1_ENABLE_EN 0x00000001 ++ ++/* Fields of "Bus Read Parameters Register1" */ ++/** Address Cycles ++ Number of cycles for address phase. */ ++#define BUSRP1_ADDRC_MASK 0xF0000000 ++/** field offset */ ++#define BUSRP1_ADDRC_OFFSET 28 ++/** Address Hold Cycles For Multiplexed Address ++ Number of address hold cycles during multiplexed accesses. */ ++#define BUSRP1_ADHOLC_MASK 0x0F000000 ++/** field offset */ ++#define BUSRP1_ADHOLC_OFFSET 24 ++/** Programmed Command Delay Cycles ++ Number of delay cycles during command delay phase. */ ++#define BUSRP1_CMDDELAY_MASK 0x00F00000 ++/** field offset */ ++#define BUSRP1_CMDDELAY_OFFSET 20 ++/** Extended Data */ ++#define BUSRP1_EXTDATA_MASK 0x000C0000 ++/** field offset */ ++#define BUSRP1_EXTDATA_OFFSET 18 ++/** External device outputs data every BFCLK cycle */ ++#define BUSRP1_EXTDATA_ONE 0x00000000 ++/** External device outputs data every 2nd BFCLK cycles */ ++#define BUSRP1_EXTDATA_TWO 0x00040000 ++/** External device outputs data every 4th BFCLK cycles */ ++#define BUSRP1_EXTDATA_FOUR 0x00080000 ++/** External device outputs data every 8th BFCLK cycles */ ++#define BUSRP1_EXTDATA_EIGHT 0x000C0000 ++/** Frequency of external clock at pin BFCLKO */ ++#define BUSRP1_EXTCLOCK_MASK 0x00030000 ++/** field offset */ ++#define BUSRP1_EXTCLOCK_OFFSET 16 ++/** Equal to ebu_clk frequency. */ ++#define BUSRP1_EXTCLOCK_ONE_TO_ONE 0x00000000 ++/** 1/2 of ebu_clk frequency. */ ++#define BUSRP1_EXTCLOCK_ONE_TO_TWO 0x00010000 ++/** 1/3 of ebu_clk frequency. */ ++#define BUSRP1_EXTCLOCK_ONE_TO_THREE 0x00020000 ++/** 1/4 of ebu_clk frequency (default after reset). */ ++#define BUSRP1_EXTCLOCK_ONE_TO_FOUR 0x00030000 ++/** Data Hold Cycles For read Accesses ++ Number of data hold cycles during read accesses. Applies to spinner support only where the address is guaranteed stable for datac clocks after RD high */ ++#define BUSRP1_DATAC_MASK 0x0000F000 ++/** field offset */ ++#define BUSRP1_DATAC_OFFSET 12 ++/** Programmed Wait States for read accesses ++ Number of programmed wait states for read accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */ ++#define BUSRP1_WAITRDC_MASK 0x00000F80 ++/** field offset */ ++#define BUSRP1_WAITRDC_OFFSET 7 ++/** Recovery Cycles After read Accesses, same CS ++ Number of idle cycles after read accesses when the next access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */ ++#define BUSRP1_RECOVC_MASK 0x00000070 ++/** field offset */ ++#define BUSRP1_RECOVC_OFFSET 4 ++/** Recovery Cycles After read Accesses, other CS ++ Number of idle cycles after read accesses when the next access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */ ++#define BUSRP1_DTACS_MASK 0x0000000F ++/** field offset */ ++#define BUSRP1_DTACS_OFFSET 0 ++ ++/* Fields of "Bus Write Configuration Register1" */ ++/** Device Type For Region ++ After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */ ++#define BUSWCON1_AGEN_MASK 0xF0000000 ++/** field offset */ ++#define BUSWCON1_AGEN_OFFSET 28 ++/** Muxed Asynchronous Type External Memory */ ++#define BUSWCON1_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000 ++/** Muxed Burst Type External Memory */ ++#define BUSWCON1_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000 ++/** NAND Flash (page optimised) */ ++#define BUSWCON1_AGEN_NAND_FLASH 0x20000000 ++/** Muxed Cellular RAM External Memory */ ++#define BUSWCON1_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000 ++/** Demuxed Asynchronous Type External Memory */ ++#define BUSWCON1_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000 ++/** Demuxed Burst Type External Memory */ ++#define BUSWCON1_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000 ++/** Demuxed Page Mode External Memory */ ++#define BUSWCON1_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000 ++/** Demuxed Cellular RAM External Memory */ ++#define BUSWCON1_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000 ++/** Serial Flash */ ++#define BUSWCON1_AGEN_SERIAL_FLASH 0xF0000000 ++/** Device Addressing Mode ++ t.b.d. */ ++#define BUSWCON1_PORTW_MASK 0x0C000000 ++/** field offset */ ++#define BUSWCON1_PORTW_OFFSET 26 ++/** External Wait Control ++ Function of the WAIT input. This is specific to the device type (i.e. the agen field). */ ++#define BUSWCON1_WAIT_MASK 0x03000000 ++/** field offset */ ++#define BUSWCON1_WAIT_OFFSET 24 ++/** WAIT is ignored (default after reset). */ ++#define BUSWCON1_WAIT_OFF 0x00000000 ++/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */ ++#define BUSWCON1_WAIT_EARLY_WAIT 0x01000000 ++/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */ ++#define BUSWCON1_WAIT_TWO_STAGE_SYNC 0x01000000 ++/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */ ++#define BUSWCON1_WAIT_WAIT_WITH_DATA 0x02000000 ++/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */ ++#define BUSWCON1_WAIT_SINGLE_STAGE_SYNC 0x02000000 ++/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */ ++#define BUSWCON1_WAIT_ABORT_AND_RETRY 0x03000000 ++/** Reserved */ ++#define BUSWCON1_LOCKCS 0x00800000 ++/** Reversed polarity at wait */ ++#define BUSWCON1_WAITINV 0x00400000 ++/* Low active. ++#define BUSWCON1_WAITINV_ACTLOW 0x00000000 */ ++/** High active */ ++#define BUSWCON1_WAITINV_ACTHI 0x00400000 ++/** Early ADV Enable for Synchronous Bursts */ ++#define BUSWCON1_EBSE 0x00200000 ++/* Low active. ++#define BUSWCON1_EBSE_DELAYED 0x00000000 */ ++/** High active */ ++#define BUSWCON1_EBSE_NOT_DELAYED 0x00200000 ++/** Early Control Signals for Synchronous Bursts */ ++#define BUSWCON1_ECSE 0x00100000 ++/* Low active. ++#define BUSWCON1_ECSE_DELAYED 0x00000000 */ ++/** High active */ ++#define BUSWCON1_ECSE_NOT_DELAYED 0x00100000 ++/** Synchronous Burst Buffer Mode Select */ ++#define BUSWCON1_FBBMSEL 0x00080000 ++/* FIXED_LENGTH ++#define BUSWCON1_FBBMSEL_FIXED_LENGTH 0x00000000 */ ++/** CONTINUOUS */ ++#define BUSWCON1_FBBMSEL_CONTINUOUS 0x00080000 ++/** Burst Length for Synchronous Burst */ ++#define BUSWCON1_FETBLEN_MASK 0x00070000 ++/** field offset */ ++#define BUSWCON1_FETBLEN_OFFSET 16 ++/** Up to 1 data cycle (default after reset). */ ++#define BUSWCON1_FETBLEN_SINGLE 0x00000000 ++/** Up to 2 data cycles. */ ++#define BUSWCON1_FETBLEN_BURST2 0x00010000 ++/** Up to 4 data cycles. */ ++#define BUSWCON1_FETBLEN_BURST4 0x00020000 ++/** Up to 8 data cycles. */ ++#define BUSWCON1_FETBLEN_BURST8 0x00030000 ++/** Up to 16 data cycles. */ ++#define BUSWCON1_FETBLEN_BURST16 0x00040000 ++/** Reserved ++ This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */ ++#define BUSWCON1_NANDAMAP_MASK 0x0000C000 ++/** field offset */ ++#define BUSWCON1_NANDAMAP_OFFSET 14 ++/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ ++#define BUSWCON1_NANDAMAP_NAND_A17_16 0x00000000 ++/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ ++#define BUSWCON1_NANDAMAP_NAND_WAIT_ADV 0x00004000 ++/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */ ++#define BUSWCON1_NANDAMAP_NAND_AD9_8 0x00008000 ++/** Reserved for future use. Do not use or unpredictable results may occur. */ ++#define BUSWCON1_NANDAMAP_NAND_RFU 0x0000C000 ++/** AAD-mux Protocol ++ If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */ ++#define BUSWCON1_AADMUX 0x00002000 ++/* Muxed device is write accessed in AD-mux mode. ++#define BUSWCON1_AADMUX_AD_MUX 0x00000000 */ ++/** Muxed device is write accessed in AAD-mux mode. */ ++#define BUSWCON1_AADMUX_AAD_MUX 0x00002000 ++/** Asynchronous Address Phase */ ++#define BUSWCON1_AAP 0x00001000 ++/* Clock is enabled at beginning of access. ++#define BUSWCON1_AAP_EARLY 0x00000000 */ ++/** Clock is enabled after address phase. */ ++#define BUSWCON1_AAP_LATE 0x00001000 ++/** Auxiliary Chip Select Enable ++ Not supported in GPON-EBU, field must be set to 0. */ ++#define BUSWCON1_CSA 0x00000200 ++/* Disable ++#define BUSWCON1_CSA_DIS 0x00000000 */ ++/** Enable */ ++#define BUSWCON1_CSA_EN 0x00000200 ++/** Flash Non-Array Access Enable ++ Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */ ++#define BUSWCON1_NAA 0x00000100 ++/* Disable ++#define BUSWCON1_NAA_DIS 0x00000000 */ ++/** Enable */ ++#define BUSWCON1_NAA_EN 0x00000100 ++/** Module Enable */ ++#define BUSWCON1_ENABLE 0x00000001 ++/* Disable ++#define BUSWCON1_ENABLE_DIS 0x00000000 */ ++/** Enable */ ++#define BUSWCON1_ENABLE_EN 0x00000001 ++ ++/* Fields of "Bus Write Parameters Register1" */ ++/** Address Cycles ++ Number of cycles for address phase. */ ++#define BUSWP1_ADDRC_MASK 0xF0000000 ++/** field offset */ ++#define BUSWP1_ADDRC_OFFSET 28 ++/** Address Hold Cycles For Multiplexed Address ++ Number of address hold cycles during multiplexed accesses. */ ++#define BUSWP1_ADHOLC_MASK 0x0F000000 ++/** field offset */ ++#define BUSWP1_ADHOLC_OFFSET 24 ++/** Programmed Command Delay Cycles ++ Number of delay cycles during command delay phase. */ ++#define BUSWP1_CMDDELAY_MASK 0x00F00000 ++/** field offset */ ++#define BUSWP1_CMDDELAY_OFFSET 20 ++/** Extended Data */ ++#define BUSWP1_EXTDATA_MASK 0x000C0000 ++/** field offset */ ++#define BUSWP1_EXTDATA_OFFSET 18 ++/** External device outputs data every BFCLK cycle */ ++#define BUSWP1_EXTDATA_ONE 0x00000000 ++/** External device outputs data every 2nd BFCLK cycles */ ++#define BUSWP1_EXTDATA_TWO 0x00040000 ++/** External device outputs data every 4th BFCLK cycles */ ++#define BUSWP1_EXTDATA_FOUR 0x00080000 ++/** External device outputs data every 8th BFCLK cycles */ ++#define BUSWP1_EXTDATA_EIGHT 0x000C0000 ++/** Frequency of external clock at pin BFCLKO */ ++#define BUSWP1_EXTCLOCK_MASK 0x00030000 ++/** field offset */ ++#define BUSWP1_EXTCLOCK_OFFSET 16 ++/** Equal to ebu_clk frequency. */ ++#define BUSWP1_EXTCLOCK_ONE_TO_ONE 0x00000000 ++/** 1/2 of ebu_clk frequency. */ ++#define BUSWP1_EXTCLOCK_ONE_TO_TWO 0x00010000 ++/** 1/3 of ebu_clk frequency. */ ++#define BUSWP1_EXTCLOCK_ONE_TO_THREE 0x00020000 ++/** 1/4 of ebu_clk frequency (default after reset). */ ++#define BUSWP1_EXTCLOCK_ONE_TO_FOUR 0x00030000 ++/** Data Hold Cycles For write Accesses ++ Number of data hold cycles during write accesses. */ ++#define BUSWP1_DATAC_MASK 0x0000F000 ++/** field offset */ ++#define BUSWP1_DATAC_OFFSET 12 ++/** Programmed Wait States For write Accesses ++ Number of programmed wait states for write accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */ ++#define BUSWP1_WAITWDC_MASK 0x00000F80 ++/** field offset */ ++#define BUSWP1_WAITWDC_OFFSET 7 ++/** Recovery Cycles After write Accesses, same CS ++ Number of idle cycles after write accesses when following access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */ ++#define BUSWP1_RECOVC_MASK 0x00000070 ++/** field offset */ ++#define BUSWP1_RECOVC_OFFSET 4 ++/** Recovery Cycles After write Accesses, other CS ++ Number of idle cycles after write accesses when the following access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */ ++#define BUSWP1_DTACS_MASK 0x0000000F ++/** field offset */ ++#define BUSWP1_DTACS_OFFSET 0 ++ ++/* Fields of "Bus Protocol Configuration Extension Register 0" */ ++/** Byte Control Mapping ++ Remapping of byte enable signals on address lines is not supported in the GPON-EBU. */ ++#define BUSCONEXT0_BCMAP_MASK 0x00030000 ++/** field offset */ ++#define BUSCONEXT0_BCMAP_OFFSET 16 ++/** No mirroring of byte enables. */ ++#define BUSCONEXT0_BCMAP_NOBCMAP 0x00000000 ++/** Asynchronous Early Write ++ This bit is obsolete and must be set to 0 or unpredictable results may result. */ ++#define BUSCONEXT0_AEW 0x00008000 ++/** AAD-mux Consecutive Address Cycles ++ This bit selects whether ADV gets deasserted between the high and the low address phase of a synchronous AAD-mux access or the two address cycles are consecutive. See Figure 32 for a waveform example that results when acac is set. acac only takes effect if the CS region is configured for synchronous AADmux access (agen = 1 or 3, aadmux = 1) and is ignored otherwise. */ ++#define BUSCONEXT0_ACAC 0x00004000 ++/* ADV is deasserted between high and low address phase. ++#define BUSCONEXT0_ACAC_SEPERATED 0x00000000 */ ++/** ADV is not deasserted between high and low address phase. */ ++#define BUSCONEXT0_ACAC_CONSECUTIVE 0x00004000 ++/** AAD-mux Write Address-to-Address Delay ++ Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when writing to the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSWCON, fields agen and aadmux. */ ++#define BUSCONEXT0_WAAC_MASK 0x00003800 ++/** field offset */ ++#define BUSCONEXT0_WAAC_OFFSET 11 ++/** AAD-mux Read Address-to-Address Delay ++ Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when reading from the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSRCON, fields agen and aadmux. */ ++#define BUSCONEXT0_RAAC_MASK 0x00000700 ++/** field offset */ ++#define BUSCONEXT0_RAAC_OFFSET 8 ++/** AAD-mux Paging Enable for CS0 ++ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field selects whether or not to use paging. If paging is enabled, the EBU skips the high address cycle in case the upper address that would be sent are the same as in the most recent access to the device.configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */ ++#define BUSCONEXT0_PAGE_EN 0x00000080 ++/* Disable ++#define BUSCONEXT0_PAGE_EN_DIS 0x00000000 */ ++/** Enable */ ++#define BUSCONEXT0_PAGE_EN_EN 0x00000080 ++/** AAD-mux Address Extension Bit Generation Mode ++ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */ ++#define BUSCONEXT0_AEBM_MASK 0x00000070 ++/** field offset */ ++#define BUSCONEXT0_AEBM_OFFSET 4 ++/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 0 */ ++#define BUSCONEXT0_AEBM_AMAP_CRE_RFU0 0x00000000 ++/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 1 */ ++#define BUSCONEXT0_AEBM_AMAP_CRE_RFU1 0x00000010 ++/** A[15] in the high address cycle is set to AMemport[amsb+18], A[14] is set to AMemport[amsb+17] */ ++#define BUSCONEXT0_AEBM_AMAP_CRE_AND_RFU 0x00000020 ++/** Do not use */ ++#define BUSCONEXT0_AEBM_reserved 0x00000030 ++/** A[15:14] in the high address cycle is set to 00B. */ ++#define BUSCONEXT0_AEBM_DIRECT_00 0x00000040 ++/** A[15:14] in the high address cycle is set to 01B */ ++#define BUSCONEXT0_AEBM_DIRECT_01 0x00000050 ++/** A[15:14] in the high address cycle is set to 10B */ ++#define BUSCONEXT0_AEBM_DIRECT_10 0x00000060 ++/** A[15:14] in the high address cycle is set to 11B. */ ++#define BUSCONEXT0_AEBM_DIRECT_11 0x00000070 ++/** Most Significant Address Bit of External Device ++ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then for amsb < 14 the EBU always sets A[13:amsb] = 0 in the high address cycle of an access. The value of A[15:14] is defined in field aebm. A value of amsb > 13 therefore has no effect. It is recommended to set amsb that it matches the addressable range of the external device according to the following formula: amsb = n - 16 for a device with 2n addressable words. */ ++#define BUSCONEXT0_AMSB_MASK 0x0000000F ++/** field offset */ ++#define BUSCONEXT0_AMSB_OFFSET 0 ++ ++/* Fields of "Bus Protocol Configuration Extension Register 1" */ ++/** Byte Control Mapping ++ Remapping of byte enable signals on address lines is not supported in the GPON-EBU. */ ++#define BUSCONEXT1_BCMAP_MASK 0x00030000 ++/** field offset */ ++#define BUSCONEXT1_BCMAP_OFFSET 16 ++/** No mirroring of byte enables. */ ++#define BUSCONEXT1_BCMAP_NOBCMAP 0x00000000 ++/** Asynchronous Early Write ++ This bit is obsolete and must be set to 0 or unpredictable results may result. */ ++#define BUSCONEXT1_AEW 0x00008000 ++/** AAD-mux Consecutive Address Cycles ++ This bit selects whether ADV gets deasserted between the high and the low address phase of a synchronous AAD-mux access or the two address cycles are consecutive. See Figure 32 for a waveform example that results when acac is set. acac only takes effect if the CS region is configured for synchronous AADmux access (agen = 1 or 3, aadmux = 1) and is ignored otherwise. */ ++#define BUSCONEXT1_ACAC 0x00004000 ++/* ADV is deasserted between high and low address phase. ++#define BUSCONEXT1_ACAC_SEPERATED 0x00000000 */ ++/** ADV is not deasserted between high and low address phase. */ ++#define BUSCONEXT1_ACAC_CONSECUTIVE 0x00004000 ++/** AAD-mux Write Address-to-Address Delay ++ Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when writing to the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSWCON, fields agen and aadmux. */ ++#define BUSCONEXT1_WAAC_MASK 0x00003800 ++/** field offset */ ++#define BUSCONEXT1_WAAC_OFFSET 11 ++/** AAD-mux Read Address-to-Address Delay ++ Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when reading from the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSRCON, fields agen and aadmux. */ ++#define BUSCONEXT1_RAAC_MASK 0x00000700 ++/** field offset */ ++#define BUSCONEXT1_RAAC_OFFSET 8 ++/** AAD-mux Paging Enable for CS0 ++ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field selects whether or not to use paging. If paging is enabled, the EBU skips the high address cycle in case the upper address that would be sent are the same as in the most recent access to the device.configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */ ++#define BUSCONEXT1_PAGE_EN 0x00000080 ++/* Disable ++#define BUSCONEXT1_PAGE_EN_DIS 0x00000000 */ ++/** Enable */ ++#define BUSCONEXT1_PAGE_EN_EN 0x00000080 ++/** AAD-mux Address Extension Bit Generation Mode ++ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */ ++#define BUSCONEXT1_AEBM_MASK 0x00000070 ++/** field offset */ ++#define BUSCONEXT1_AEBM_OFFSET 4 ++/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 0 */ ++#define BUSCONEXT1_AEBM_AMAP_CRE_RFU0 0x00000000 ++/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 1 */ ++#define BUSCONEXT1_AEBM_AMAP_CRE_RFU1 0x00000010 ++/** A[15] in the high address cycle is set to AMemport[amsb+18], A[14] is set to AMemport[amsb+17] */ ++#define BUSCONEXT1_AEBM_AMAP_CRE_AND_RFU 0x00000020 ++/** Do not use */ ++#define BUSCONEXT1_AEBM_reserved 0x00000030 ++/** A[15:14] in the high address cycle is set to 00B. */ ++#define BUSCONEXT1_AEBM_DIRECT_00 0x00000040 ++/** A[15:14] in the high address cycle is set to 01B */ ++#define BUSCONEXT1_AEBM_DIRECT_01 0x00000050 ++/** A[15:14] in the high address cycle is set to 10B */ ++#define BUSCONEXT1_AEBM_DIRECT_10 0x00000060 ++/** A[15:14] in the high address cycle is set to 11B. */ ++#define BUSCONEXT1_AEBM_DIRECT_11 0x00000070 ++/** Most Significant Address Bit of External Device ++ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then for amsb < 14 the EBU always sets A[13:amsb] = 0 in the high address cycle of an access. The value of A[15:14] is defined in field aebm. A value of amsb > 13 therefore has no effect. It is recommended to set amsb that it matches the addressable range of the external device according to the following formula: amsb = n - 16 for a device with 2n addressable words. */ ++#define BUSCONEXT1_AMSB_MASK 0x0000000F ++/** field offset */ ++#define BUSCONEXT1_AMSB_OFFSET 0 ++ ++/* Fields of "Serial Flash Configuration Register" */ ++/** Direct Access Device Port Width ++ DA_PORTW Defines the number of signal lines to be used with direct read access from a Serial Flash as defined for the command with opcode rd_opc. Depending on thedevice type and/or command, the number of used signal lines might differbetween command, address, and data phase of the transaction. */ ++#define SFCON_DA_PORTW_MASK 0xE0000000 ++/** field offset */ ++#define SFCON_DA_PORTW_OFFSET 29 ++/** One signal line used in all phases of the transaction. */ ++#define SFCON_DA_PORTW_WIDTH_1_1_1 0x00000000 ++/** One signal line used in the COMMAND and ADDRESS phase of the transaction and two signal lines used in the DATA phase. */ ++#define SFCON_DA_PORTW_WIDTH_1_1_2 0x20000000 ++/** One signal used in the COMMAND phase of the transaction and two signal lines used in the ADDRESS/DUMMY phase and the DATA phase. */ ++#define SFCON_DA_PORTW_WIDTH_1_2_2 0x40000000 ++/** Two signal lines used in all phases of the transaction. */ ++#define SFCON_DA_PORTW_WIDTH_2_2_2 0x60000000 ++/** One signal line used in the COMMAND and ADDRESS phase of the transaction and four signal lines used in the DATA phase. */ ++#define SFCON_DA_PORTW_WIDTH_1_1_4 0x80000000 ++/** One signal used in the COMMAND phase of the transaction and four signal lines used in the ADDRESS/DUMMY phase and the DATA phase. */ ++#define SFCON_DA_PORTW_WIDTH_1_4_4 0xA0000000 ++/** Four signal lines used in all phases of the transaction. */ ++#define SFCON_DA_PORTW_WIDTH_4_4_4 0xC0000000 ++/** for future use. */ ++#define SFCON_DA_PORTW_WIDTH_reserved 0xE0000000 ++/** Read Abort Enable ++ If set, a read access from the external device can be aborted via signal sf_rd_abort_i. See Section 3.18.2.9 for details. */ ++#define SFCON_RD_ABORT_EN 0x10000000 ++/** Device Size ++ Defines the number of significant address bits for the Serial Flash device(s). All address bits above the MSB are forced to 0. The configuration in this field also defines for the address auto-increment feature when to wrap around from the upper most address to 0. */ ++#define SFCON_DEV_SIZE_MASK 0x0F000000 ++/** field offset */ ++#define SFCON_DEV_SIZE_OFFSET 24 ++/** 16 MBit device */ ++#define SFCON_DEV_SIZE_A20_0 0x00000000 ++/** 32 MBit device */ ++#define SFCON_DEV_SIZE_A21_0 0x01000000 ++/** 64 MBit device */ ++#define SFCON_DEV_SIZE_A22_0 0x02000000 ++/** 128 MBit device */ ++#define SFCON_DEV_SIZE_A23_0 0x03000000 ++/** 256 MBit device */ ++#define SFCON_DEV_SIZE_A24_0 0x04000000 ++/** 512 MBit device */ ++#define SFCON_DEV_SIZE_A25_0 0x05000000 ++/** 1 GBit device */ ++#define SFCON_DEV_SIZE_A26_0 0x06000000 ++/** 2 GBit device */ ++#define SFCON_DEV_SIZE_A27_0 0x07000000 ++/** 4 GBit device */ ++#define SFCON_DEV_SIZE_A28_0 0x08000000 ++/** 8 GBit device */ ++#define SFCON_DEV_SIZE_A29_0 0x09000000 ++/** 16 GBit device */ ++#define SFCON_DEV_SIZE_A30_0 0x0A000000 ++/** 32 GBit device */ ++#define SFCON_DEV_SIZE_A31_0 0x0B000000 ++/** Device Page Size ++ Defines the page size employed by all connected Serial Flash devices. The device page size is used to determine the address wrap-around for the write address auto-increment feature. */ ++#define SFCON_DPS_MASK 0x00C00000 ++/** field offset */ ++#define SFCON_DPS_OFFSET 22 ++/** Device page size is 256 Bytes */ ++#define SFCON_DPS_DPS_256 0x00000000 ++/** Device page size is 512 Bytes */ ++#define SFCON_DPS_DPS_512 0x00400000 ++/** Page Buffer Size ++ Defines the size of the EBU's page buffer used in Buffered Access. Page buffer size configured here must be less than or equal to the maximum page buffer size which is a built option of the EBU (256 Bytes for GPON). */ ++#define SFCON_PB_SIZE_MASK 0x00300000 ++/** field offset */ ++#define SFCON_PB_SIZE_OFFSET 20 ++/** No read buffer is available/used. */ ++#define SFCON_PB_SIZE_NONE 0x00000000 ++/** 128 Bytes */ ++#define SFCON_PB_SIZE_SIZE_128 0x00100000 ++/** 256 Bytes */ ++#define SFCON_PB_SIZE_SIZE_256 0x00200000 ++/** Bidirectional Data Bus ++ Defines whether the Serial Flash uses a unidirectional or a bidirectional data bus. */ ++#define SFCON_BIDIR 0x00080000 ++/* The Serial Flash interface uses a pair of two unidirectional busses (one for write, one for read) ++#define SFCON_BIDIR_UNIDIRECTIONAL 0x00000000 */ ++/** The Serial Flash interface uses a bidirectional data bus. */ ++#define SFCON_BIDIR_BIDIRECTIONAL 0x00080000 ++/** No Busy Error termination ++ By default, the EBU error-terminates all direct access to a Serial Flash while EBU_SFSTAT.busy is set. By setting NO_BUSY_ERR, the EBU can be configured to permit direct accesses to proceed to the Serial Flash, e.g. for devices that support a read-while-write functionality. */ ++#define SFCON_NO_BUSY_ERR 0x00040000 ++/** End-of-Busy Detection Mode ++ Defines how the EBU detects the end of a busy phase in the Serial Flash device. The current version of the EBU requires the software to explicitly poll the device's status register and then inform the EBU on the end of the busy status by clearing the corresponding bit in register EBU_SF_STAT. */ ++#define SFCON_EOBDM_MASK 0x00030000 ++/** field offset */ ++#define SFCON_EOBDM_OFFSET 16 ++/** No read buffer is available/used. */ ++#define SFCON_EOBDM_SOFTWARE 0x00000000 ++/** Poll device status register (not supported yet) */ ++#define SFCON_EOBDM_POLL_SR 0x00010000 ++/** Poll devices busy/ready pin fed into EBU via WAIT pin (not supported yet). */ ++#define SFCON_EOBDM_POLL_RDY 0x00020000 ++/** Same as POLL_RDY, but CS must be asserted to have the device output its busy/ready status (not supported yet). */ ++#define SFCON_EOBDM_POLL_RDY_WITH_CS 0x00030000 ++/** Direct Access Keep Chip Select ++ Defines whether the Serial Flash remains selected after a direct access transaction has been finished. */ ++#define SFCON_DA_KEEP_CS 0x00008000 ++/* After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address. ++#define SFCON_DA_KEEP_CS_DESELECT 0x00000000 */ ++/** Chip Select of device is kept active after direct read access so that device is ready for follow-up read of next sequential byte without the need to send command and address. If the next command is to another Chip Select, is a different command or accesses a different address, the EBU first deactivates the kept Chip Select before it starts the new transaction with sending the command opcode and address. */ ++#define SFCON_DA_KEEP_CS_KEEP_SELECTED 0x00008000 ++/** Early Read Abort Enable ++ When aborting a Serial Flash Read is enabled in bit EBU_SFCON.rd_abort_en, bit early_abort selects at what point in the protocol an external access might be aborted. Datasheets of many Serial Flash devices are not explicit on what happens (and whether it is allowed) when a read access is cut-short by deselecting the device during the CMD, ADDR or DUMMY phase of the protocol. */ ++#define SFCON_EARLY_ABORT 0x00004000 ++/* DISABLE Early abortion is disabled (default after reset). Once the EBU has started the access on the External Bus (first bit time slot), the EBU continues the external transfer until the first data byte has been received. After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address. ++#define SFCON_EARLY_ABORT_DISABLE 0x00000000 */ ++/** Early abortion is not yet supported in the current version of the EBU. Do not use. The feature is a late improvement to the EBU and could not be verified completely before the final release. After proven to work, it should be made officially available to reduce access latency after aborted Serial Flash reads. Setting early_abort to ENABLE alters the read abort handling in the following way: Once the EBU has started the access on the External Bus, the transfer is cut-short after transferring the CMD byte, the three address bytes, any DUMMY bits or at the end of the next data byte - whatever comes first. */ ++#define SFCON_EARLY_ABORT_ENABLE 0x00004000 ++/** Direct Access Address Length ++ Defines the number of address bytes to be sent (MSB first) to the device with a direct read access transaction. Other values than listed below are not supported and have unpredictable results. */ ++#define SFCON_DA_ALEN_MASK 0x00003000 ++/** field offset */ ++#define SFCON_DA_ALEN_OFFSET 12 ++/** 3 address bytes (bits 23:0 of the internal address) */ ++#define SFCON_DA_ALEN_THREE 0x00000000 ++/** Read Access Dummy Bytes ++ This field defines the number of dummy bytes to send between the last address byte before the EBU starts capturing read data from the bus for a direct read access. The number of dummy bytes depends on the data access command being used (see field), the clock frequency and the type of device being used. */ ++#define SFCON_RD_DUMLEN_MASK 0x00000F00 ++/** field offset */ ++#define SFCON_RD_DUMLEN_OFFSET 8 ++/** Direct Read Access Command Opcode ++ This byte defines the command opcode to send when performing a data read from the Serial Flash in Direct Access Mode. Any value can be set (the EBU does not interpret the value, but directly uses the contents of this register field in the command phase of the transaction). Common opcodes to be used and understood by most devices are READ (03H) and FAST_READ (0BH), but some devices might provide additional opcodes, e.g. to support higher clock frequencies requiring additional dummy bytes or to define a wider interface bus. */ ++#define SFCON_RD_OPC_MASK 0x000000FF ++/** field offset */ ++#define SFCON_RD_OPC_OFFSET 0 ++/** READ */ ++#define SFCON_RD_OPC_READ 0x00000003 ++/** FAST_READ */ ++#define SFCON_RD_OPC_FAST_READ 0x0000000B ++ ++/* Fields of "Serial Flash Timing Register" */ ++/** CS Idle time ++ This field defines the minimum time the device's Chip Select has to be deasserted in between accesses. Most devices require a minimum deselect time between 50 and 100 ns. See Table 43 for the encoding used in this field. */ ++#define SFTIME_CS_IDLE_MASK 0xF0000000 ++/** field offset */ ++#define SFTIME_CS_IDLE_OFFSET 28 ++/** 1 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_0 0x00000000 ++/** 2 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_1 0x10000000 ++/** 3 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_2 0x20000000 ++/** 4 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_3 0x30000000 ++/** 6 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_4 0x40000000 ++/** 8 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_5 0x50000000 ++/** 10 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_6 0x60000000 ++/** 12 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_7 0x70000000 ++/** 14 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_8 0x80000000 ++/** 16 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_9 0x90000000 ++/** 20 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_10 0xA0000000 ++/** 24 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_11 0xB0000000 ++/** 32 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_12 0xC0000000 ++/** 40 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_13 0xD0000000 ++/** 48 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_14 0xE0000000 ++/** 64 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_15 0xF0000000 ++/** CS Hold time ++ This field defines (in multiples of the EBU internal clock's period) the minimum time the device's Chip Select must remain asserted after transfer of the last bit of a write transaction. This CS hold time does not apply to read accesses */ ++#define SFTIME_CS_HOLD_MASK 0x0C000000 ++/** field offset */ ++#define SFTIME_CS_HOLD_OFFSET 26 ++/** CS Setup time ++ This field defines (in multiples of the EBU internal clock's period) when to assert the device's Chip Select before the first SCK clock period for transferring the command is started on the External Bus */ ++#define SFTIME_CS_SETUP_MASK 0x03000000 ++/** field offset */ ++#define SFTIME_CS_SETUP_OFFSET 24 ++/** Write-to-Read Pause ++ This field defines the length of the optional pause when switching from write to read direction in the transaction. During this pause, SCK is held stable. */ ++#define SFTIME_WR2RD_PAUSE_MASK 0x00300000 ++/** field offset */ ++#define SFTIME_WR2RD_PAUSE_OFFSET 20 ++/** Read Data Position ++ This field defines when to capture valid read data bit(s) (in multiples of half of the EBU internal clock's period) relative to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. RD_POS must be less than or equal to EBU_SFTIME.sck_per (not checked in hardware) or unpredictable results may occur. */ ++#define SFTIME_RD_POS_MASK 0x000F0000 ++/** field offset */ ++#define SFTIME_RD_POS_OFFSET 16 ++/** SCK Fall-edge Position ++ This field defines the positioning of the SCK fall edge (in multiples of half of the EBU internal clock's period) with respect to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. SCKF_POS must be less than or equal to SCK_PER (not checked in hardware) or unpredictable results may occur. If EBU_SFTIME.sck_inv is set, SCKF_POS defines the positioning of the falling instead of the rising edge of SCK. In the current version of the EBU, SCKF_POS must be set 0 or unpredictable results may occur. */ ++#define SFTIME_SCKF_POS_MASK 0x0000F000 ++/** field offset */ ++#define SFTIME_SCKF_POS_OFFSET 12 ++/** SCK Rise-edge Position ++ This field defines the positioning of the SCK rise edge (in multiples of half of the EBU internal clock's period) with respect to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. SCKR_POS must be less than EBU_SFTIME.sck_per (not checked in hardware) or unpredictable results may occur. If EBU_SFTIME.sck_inv is set, SCKR_POS defines the positioning of the falling instead of the rising edge of SCK. */ ++#define SFTIME_SCKR_POS_MASK 0x00000F00 ++/** field offset */ ++#define SFTIME_SCKR_POS_OFFSET 8 ++/** SCK Feedback Clock Inversion ++ If set, read data gets captured with the falling instead of the rising edge of SCK if clock feedback is enabled in EBU_SFTIME.sck_fdbk_en. */ ++#define SFTIME_SCK_FDBK_INV 0x00000040 ++/** SCK Clock Feedback ++ If set, read data is captured using the external SCK clock feedback into the chip instead of the EBU's internal clock. Using the feedback clock compensate for the high delay over the pads and its use is required at higher frequencies. A penalty for synchronizing the read data from the SCK into the ebu_clk domain applies to the read access latency. */ ++#define SFTIME_SCK_FDBK_EN 0x00000020 ++/** Inverted SCK ++ If set, the clock to the Serial Flash devices is inverted. This also results in SCK high while a Serial Flash remains selected between transactions (keep_cs feature). In the current version of the EBU, clock inversion is not supported. SCK_INV must be set to 0 or unpredictable results may occur. */ ++#define SFTIME_SCK_INV 0x00000010 ++/** SCK Period ++ This field defines the period of the SCK clock in multiples of half of the EBU clock period. The EBU supports values between 2 and 14, corresponding to a frequency ratio range from 1:1. to 1:7 between SCK and the internal clock. Other values are prohibited and result in unpredictable behaviour. In the current version of the EBU, odd values for SCK_PER are not supported. */ ++#define SFTIME_SCK_PER_MASK 0x0000000F ++/** field offset */ ++#define SFTIME_SCK_PER_OFFSET 0 ++ ++/* Fields of "Serial Flash Status Register" */ ++/** Command Overwrite Error ++ This bit is set on an attempt to start an indirect access while a previous indirect access has not finished. The bit remains unaltered when the software writes a '0' and is toggled when a '1' is written. This toggle-by-write-1 behavior allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit to clear after it has been set by the Serial Flash protocol engine. */ ++#define SFSTAT_CMD_OVWRT_ERR 0x40000000 ++/** Command Error ++ This bit is set when the EBU discards an indirect or direct access to/from a Serial Flash. The bit remains unaltered when the software writes a '0' and is toggled when a '1' is written. This toggle-by-write-1 behavior allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit to clear after it has been set by the Serial Flash protocol engine. */ ++#define SFSTAT_CMD_ERR 0x20000000 ++/** Access Command Pending ++ If set, indicates that access from/to a Serial Flash device has not finished yet. */ ++#define SFSTAT_CMD_PEND 0x00400000 ++/** External Device Selected ++ If set, indicates that the Chip Select of a Serial Flash device is currently active on the External Bus. */ ++#define SFSTAT_SELECTED 0x00200000 ++/** Protocol Engine Active ++ If set, indicates that the EBU's Serial Flash protocol engine is active. */ ++#define SFSTAT_ACTIVE 0x00100000 ++/** Page Buffer Invalidate ++ When writing a one to this bit, bits PB_VALID and PB_UPDATE are both cleared, thereby invalidating the page buffer for access to/from the Serial Flash device. After invalidating the buffer, PB_INVALID is automatically cleared so that it always reads as 0. */ ++#define SFSTAT_PB_INVALID 0x00010000 ++/** Page Buffer Update ++ This bit is set when data in the page buffer gets modified. It is cleared when new data gets loaded to the page buffer, when it is written back to the device (WRITE_PAGE command) or when PB_VALID gets cleared. */ ++#define SFSTAT_PB_UPDATE 0x00002000 ++/** Page Buffer Valid ++ This bit is set after the last data byte of a LOAD_PAGE command has been stored in the page buffer or when the page buffer is explicitely validated via a VALIDATE_PAGE special command. It remains set until the page buffer gets invalidated by writing a 1 to PB_INVALID or any of the LOAD_PAGE special commands. While PB_VALID is set, all accesses to the buffered address range are diverted to the page buffer with no access being performed on the External Bus. */ ++#define SFSTAT_PB_VALID 0x00001000 ++/** Page Buffer Busy ++ The bit is set when the EBU starts executing a LOAD_PAGE or a WRITE_PAGE command and cleared when the last byte of the requested page has been transferred from/to the external device. The inverted value of PB_BUSY is output on the EBU interface and may trigger a system interrupt. */ ++#define SFSTAT_PB_BUSY 0x00000100 ++/** Device Busy ++ This bit is set by the Serial Flash protocol engine when an indirect access is performed via register EBU_SFCMD with SET_BUSY being set. While busy is set, access to the Serial Flash is very limited and all transactions are error-terminated except when explicitly marked to ignore the busy status. If the EBU is configured in EBU_SFCON.EOBDM to automatically poll the busy status of the device, busy is cleared as soon as the device is found to be idle again. On a software write, busy remains unaltered when written with a '0' and is toggled when written with a '1', respectively.This toggle-by-write-1 behaviour allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit after it got set by the Serial Flash protocol engine and no automatic busy detection is configured in EBU_SFCON.EOBDM Then the software has to clear busy when it finds the device to be no longer busy by either polling the device's status register via the EBU or by waiting for the maximum busy time of the operation started in the device. */ ++#define SFSTAT_BUSY 0x00000001 ++ ++/* Fields of "Serial Flash Command Register" */ ++/** Command Type ++ This field is a qualifier of the command opcode in EBU_SFCMD.opc. Two types */ ++#define SFCMD_CMDTYPE 0x80000000 ++/* The opcode in EBU_SFCMD.opc is directly used in the command phase of a single transaction to the Serial Flash device. ++#define SFCMD_CMDTYPE_ACCESS_CMD 0x00000000 */ ++/** The opcode in EBU_SFCMD.opc is used to start a special command in the Serial Flash Controller which might include any number of external transactions to/from the Serial Flash device. */ ++#define SFCMD_CMDTYPE_SPECIAL_CMD 0x80000000 ++/** Device Port Width ++ Defines the number of signal lines to be used with direct read access from a Serial Flash as defined for the command with opcode opc. The encoding of this field is the same as forDA_PORTW. */ ++#define SFCMD_PORTW_MASK 0x70000000 ++/** field offset */ ++#define SFCMD_PORTW_OFFSET 28 ++/** Bidirectional Signal Lines ++ If set selects bidirectional signal lines to be used for the data transfer. */ ++#define SFCMD_BIDIR 0x08000000 ++/** Chip Select ++ This field selects which of the EBU's Chip Selects to activated for the command that is written to EBU_SFCMD.opc. A value between 0 and 3 selects one of the EBU's main CSs while 4 to 7 chooses one of the Auxiliary Chip Selects CSA[3:0], respectively. */ ++#define SFCMD_CS_MASK 0x07000000 ++/** field offset */ ++#define SFCMD_CS_OFFSET 24 ++/** Disable Auto Address Increment ++ By default, the address in register EBU_SFADDR is automatically incremented with each data byte being transferred. By setting this bit, the auto-increment can be disabled. */ ++#define SFCMD_DIS_AAI 0x00800000 ++/** Address Length ++ Defines the number of address bytes from register EBU_SFADDR to sent in the address phase of the transaction to/from the Serial Flash. Note: Address bytes are also sent when the command has no data. */ ++#define SFCMD_ALEN_MASK 0x00700000 ++/** field offset */ ++#define SFCMD_ALEN_OFFSET 20 ++/** Dummy Phase Length ++ Defines the number of dummy bytes to send to the device between the command/address phase and the data phase of a transaction. Note:Dummy bytes are also sent when the command has no address and/or no data. */ ++#define SFCMD_DUMLEN_MASK 0x000F0000 ++/** field offset */ ++#define SFCMD_DUMLEN_OFFSET 16 ++/** Keep Chip Select ++ Defines whether the Serial Flash remains selected after the indirect access transaction has been finished. */ ++#define SFCMD_KEEP_CS 0x00008000 ++/* After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address. ++#define SFCMD_KEEP_CS_DESELECT 0x00000000 */ ++/** Chip Select of device is kept active after direct read access so that device is ready for follow-up read of next sequential byte without the need to send command and address. If the next command is to another Chip Select, is a different command or accesses a different address, the EBU first deactivates the kept Chip Select before it starts the new transaction with sending the command opcode and address. */ ++#define SFCMD_KEEP_CS_KEEP_SELECTED 0x00008000 ++/** Set Busy Flag ++ If set, starting the command sets EBU_SFSTAT.busy. */ ++#define SFCMD_SET_BUSY 0x00004000 ++/** Ignore Busy ++ By default, the EBU error terminates all attempts to access a Serial Flash while EBU_SFSTAT.busy is set. Setting this bit overrules this error termination and permits the command written to EBU_SFCMD.opc to proceed to the External Bus. Normally, this bit is only set to execute a Read Status Register command to the Serial Flash, but may also be used for any other type of access the device is able to handle while it is busy. */ ++#define SFCMD_IGNORE_BUSY 0x00002000 ++/** Skip Opcode ++ If this bit is set, the opcode in field OPC is not sent to the External Bus, but the external transaction starts with sending the first address byte (if ALEN 0), the first dummy byte (if alen = 0 and DUMLEN 0), or directly with transferring the data bytes (if ALEN = DUMLEN = 0 and DLEN 0). Limiting the external transfer to just the data phase - together with the keep_cs feature - allow to transfer any number of data bytes for a device command sent via EBU_SFCMD by keeping the device selected between accesses and chaining multiple indirect access commands each transferring up to 4 data bytes from/to register EBU_SFDATA. */ ++#define SFCMD_SKIP_OPC 0x00001000 ++/** Data Length ++ This field defines the number of data bytes to transfer in the data phase of the command. For a read command, the data bytes are stored in register EBU_SFDATA, for a write transfer they are taken from that register. As the data register can hold at most 4 bytes, DLEN is restricted to the range [0..4]. */ ++#define SFCMD_DLEN_MASK 0x00000E00 ++/** field offset */ ++#define SFCMD_DLEN_OFFSET 9 ++/** Direction ++ Defines the direction of the data transfer (if any) in the data phase of the transaction to/from the serial bus. */ ++#define SFCMD_DIR 0x00000100 ++/* dlen bytes of data are read from the Serial Flash during the data phase of the transaction and stored in register EBU_SFDATA. ++#define SFCMD_DIR_READ 0x00000000 */ ++/** dlen bytes of data are read from register EBU_SFDATA and written to the Serial Flash during the data phase of the transactione */ ++#define SFCMD_DIR_WRITE 0x00000100 ++/** Command Opcode ++ A write access to this field starts an Indirect Access command in the EBU's Serial Flash controller. Two types of commands are supported (selected in EBU_SFCMD.cmdtype) and determine how the EBU interprets the opcode:- - For a ACCESS_CMD, a single transaction is executed to/from the Serial Flash device and the OPC is sent to the device in the command phase of the protocol. The number of address, dummy and data bytes to transfer with the command are given in fields ALEN, DUMLEN, and DLEN of register EBU_SFCMD, respectively. - For a SPECIAL_CMD, the EBU starts a complex operation that usually involves multiple transactions to/from the Serial Flash device. See Section 3.18.2.5 for an overview of the complex commands currently supported. */ ++#define SFCMD_OPC_MASK 0x000000FF ++/** field offset */ ++#define SFCMD_OPC_OFFSET 0 ++ ++/* Fields of "Serial Flash Address Register" */ ++/** Address ++ Before writing to register EBU_SFCMD to start a command that requires the transfer of an address, the address to use must be stored in this register. If not disabled in EBU_SFCMD.dis_aai, ADDR is incremented automatically with each data byte transferred between the EBU and the Serial Flash for an indirect access. Note:Register EBU_SFADDR is only used for access in Indirect Access Mode and is ignored/remains unaltered for all accesses in Direct Access Mode. */ ++#define SFADDR_ADDR_MASK 0xFFFFFFFF ++/** field offset */ ++#define SFADDR_ADDR_OFFSET 0 ++ ++/* Fields of "Serial Flash Data Register" */ ++/** Data Bytes ++ Before writing to register EBU_SFCMD to start a command that requires the transfer of data from the EBU to the Serial Flash device (write access), the data to send must be stored in this register. The data bytes have to be right-aligned in this register, that is, the last byte to send must be placed in bits DATA[7:0], the second-to-last byte in bits DATA[15:8], etc.. Similarly, for a read access with data being transferred from the Serial Flash to the EBU, this register collects the read data received from the device. The read data is right-aligned, that is, the last byte received gets placed in bits DATA[7:0], the second-to-last byte in bits DATA[15:8], etc... The number of data bytes to be transferred between EBU and the Serial Flash is defined in EBU_SFCMD.DLEN. Note:Register EBU_SFDATA is only used for accesses in Indirect Access Mode and is ignored/remains unaltered for all accesses in Direct Access Mode. */ ++#define SFDATA_DATA_MASK 0xFFFFFFFF ++/** field offset */ ++#define SFDATA_DATA_OFFSET 0 ++ ++/* Fields of "Serial Flash I/O Control Register" */ ++/** Start of Write Delay ++ By default, the EBU starts driving to AD[3:0] two EBU clock cycles before asserting the CS for an external Serial Flash access. For write accesses, this delay can be increased via field SOWD. */ ++#define SFIO_SOWD_MASK 0x0000F000 ++/** field offset */ ++#define SFIO_SOWD_OFFSET 12 ++/** End of Write Delay ++ This field defines the time (in number of EBU clock cycles) for which the EBU keeps driving the External Bus AD[3:0] after deassertion of the device's CS. */ ++#define SFIO_EOWD_MASK 0x00000F00 ++/** field offset */ ++#define SFIO_EOWD_OFFSET 8 ++/** Data Output ++ The EBU always controls the AD[3:0] pins while a CS for a Serial Flash device is asserted. Field UNUSED_WD defines the values being driven to these pins while the Serial Flash controller is not writing data to or is reading data from the device via the respective line. See Section 3.18.6 for details. */ ++#define SFIO_UNUSED_WD_MASK 0x0000000F ++/** field offset */ ++#define SFIO_UNUSED_WD_OFFSET 0 ++ ++/*! @} */ /* EBU_REGISTER */ ++ ++#endif /* _ebu_reg_h */ +diff --git a/arch/mips/include/asm/mach-lantiq/falcon/gpon_reg_base.h b/arch/mips/include/asm/mach-lantiq/falcon/gpon_reg_base.h +new file mode 100644 +index 0000000..d575082 +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/gpon_reg_base.h +@@ -0,0 +1,376 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++ ++#ifndef _gpon_reg_base_h ++#define _gpon_reg_base_h ++ ++/** \addtogroup GPON_BASE ++ @{ ++*/ ++ ++#ifndef KSEG1 ++#define KSEG1 0xA0000000 ++#endif ++ ++/** address range for ebu ++ 0x18000000--0x180000FF */ ++#define GPON_EBU_BASE (KSEG1 | 0x18000000) ++#define GPON_EBU_END (KSEG1 | 0x180000FF) ++#define GPON_EBU_SIZE 0x00000100 ++/** address range for gpearb ++ 0x1D400100--0x1D4001FF */ ++#define GPON_GPEARB_BASE (KSEG1 | 0x1D400100) ++#define GPON_GPEARB_END (KSEG1 | 0x1D4001FF) ++#define GPON_GPEARB_SIZE 0x00000100 ++/** address range for tmu ++ 0x1D404000--0x1D404FFF */ ++#define GPON_TMU_BASE (KSEG1 | 0x1D404000) ++#define GPON_TMU_END (KSEG1 | 0x1D404FFF) ++#define GPON_TMU_SIZE 0x00001000 ++/** address range for iqm ++ 0x1D410000--0x1D41FFFF */ ++#define GPON_IQM_BASE (KSEG1 | 0x1D410000) ++#define GPON_IQM_END (KSEG1 | 0x1D41FFFF) ++#define GPON_IQM_SIZE 0x00010000 ++/** address range for octrlg ++ 0x1D420000--0x1D42FFFF */ ++#define GPON_OCTRLG_BASE (KSEG1 | 0x1D420000) ++#define GPON_OCTRLG_END (KSEG1 | 0x1D42FFFF) ++#define GPON_OCTRLG_SIZE 0x00010000 ++/** address range for octrll0 ++ 0x1D440000--0x1D4400FF */ ++#define GPON_OCTRLL0_BASE (KSEG1 | 0x1D440000) ++#define GPON_OCTRLL0_END (KSEG1 | 0x1D4400FF) ++#define GPON_OCTRLL0_SIZE 0x00000100 ++/** address range for octrll1 ++ 0x1D440100--0x1D4401FF */ ++#define GPON_OCTRLL1_BASE (KSEG1 | 0x1D440100) ++#define GPON_OCTRLL1_END (KSEG1 | 0x1D4401FF) ++#define GPON_OCTRLL1_SIZE 0x00000100 ++/** address range for octrll2 ++ 0x1D440200--0x1D4402FF */ ++#define GPON_OCTRLL2_BASE (KSEG1 | 0x1D440200) ++#define GPON_OCTRLL2_END (KSEG1 | 0x1D4402FF) ++#define GPON_OCTRLL2_SIZE 0x00000100 ++/** address range for octrll3 ++ 0x1D440300--0x1D4403FF */ ++#define GPON_OCTRLL3_BASE (KSEG1 | 0x1D440300) ++#define GPON_OCTRLL3_END (KSEG1 | 0x1D4403FF) ++#define GPON_OCTRLL3_SIZE 0x00000100 ++/** address range for octrlc ++ 0x1D441000--0x1D4410FF */ ++#define GPON_OCTRLC_BASE (KSEG1 | 0x1D441000) ++#define GPON_OCTRLC_END (KSEG1 | 0x1D4410FF) ++#define GPON_OCTRLC_SIZE 0x00000100 ++/** address range for ictrlg ++ 0x1D450000--0x1D45FFFF */ ++#define GPON_ICTRLG_BASE (KSEG1 | 0x1D450000) ++#define GPON_ICTRLG_END (KSEG1 | 0x1D45FFFF) ++#define GPON_ICTRLG_SIZE 0x00010000 ++/** address range for ictrll0 ++ 0x1D460000--0x1D4601FF */ ++#define GPON_ICTRLL0_BASE (KSEG1 | 0x1D460000) ++#define GPON_ICTRLL0_END (KSEG1 | 0x1D4601FF) ++#define GPON_ICTRLL0_SIZE 0x00000200 ++/** address range for ictrll1 ++ 0x1D460200--0x1D4603FF */ ++#define GPON_ICTRLL1_BASE (KSEG1 | 0x1D460200) ++#define GPON_ICTRLL1_END (KSEG1 | 0x1D4603FF) ++#define GPON_ICTRLL1_SIZE 0x00000200 ++/** address range for ictrll2 ++ 0x1D460400--0x1D4605FF */ ++#define GPON_ICTRLL2_BASE (KSEG1 | 0x1D460400) ++#define GPON_ICTRLL2_END (KSEG1 | 0x1D4605FF) ++#define GPON_ICTRLL2_SIZE 0x00000200 ++/** address range for ictrll3 ++ 0x1D460600--0x1D4607FF */ ++#define GPON_ICTRLL3_BASE (KSEG1 | 0x1D460600) ++#define GPON_ICTRLL3_END (KSEG1 | 0x1D4607FF) ++#define GPON_ICTRLL3_SIZE 0x00000200 ++/** address range for ictrlc0 ++ 0x1D461000--0x1D4610FF */ ++#define GPON_ICTRLC0_BASE (KSEG1 | 0x1D461000) ++#define GPON_ICTRLC0_END (KSEG1 | 0x1D4610FF) ++#define GPON_ICTRLC0_SIZE 0x00000100 ++/** address range for ictrlc1 ++ 0x1D461100--0x1D4611FF */ ++#define GPON_ICTRLC1_BASE (KSEG1 | 0x1D461100) ++#define GPON_ICTRLC1_END (KSEG1 | 0x1D4611FF) ++#define GPON_ICTRLC1_SIZE 0x00000100 ++/** address range for fsqm ++ 0x1D500000--0x1D5FFFFF */ ++#define GPON_FSQM_BASE (KSEG1 | 0x1D500000) ++#define GPON_FSQM_END (KSEG1 | 0x1D5FFFFF) ++#define GPON_FSQM_SIZE 0x00100000 ++/** address range for pctrl ++ 0x1D600000--0x1D6001FF */ ++#define GPON_PCTRL_BASE (KSEG1 | 0x1D600000) ++#define GPON_PCTRL_END (KSEG1 | 0x1D6001FF) ++#define GPON_PCTRL_SIZE 0x00000200 ++/** address range for link0 ++ 0x1D600200--0x1D6002FF */ ++#define GPON_LINK0_BASE (KSEG1 | 0x1D600200) ++#define GPON_LINK0_END (KSEG1 | 0x1D6002FF) ++#define GPON_LINK0_SIZE 0x00000100 ++/** address range for link1 ++ 0x1D600300--0x1D6003FF */ ++#define GPON_LINK1_BASE (KSEG1 | 0x1D600300) ++#define GPON_LINK1_END (KSEG1 | 0x1D6003FF) ++#define GPON_LINK1_SIZE 0x00000100 ++/** address range for link2 ++ 0x1D600400--0x1D6004FF */ ++#define GPON_LINK2_BASE (KSEG1 | 0x1D600400) ++#define GPON_LINK2_END (KSEG1 | 0x1D6004FF) ++#define GPON_LINK2_SIZE 0x00000100 ++/** address range for disp ++ 0x1D600500--0x1D6005FF */ ++#define GPON_DISP_BASE (KSEG1 | 0x1D600500) ++#define GPON_DISP_END (KSEG1 | 0x1D6005FF) ++#define GPON_DISP_SIZE 0x00000100 ++/** address range for merge ++ 0x1D600600--0x1D6006FF */ ++#define GPON_MERGE_BASE (KSEG1 | 0x1D600600) ++#define GPON_MERGE_END (KSEG1 | 0x1D6006FF) ++#define GPON_MERGE_SIZE 0x00000100 ++/** address range for tbm ++ 0x1D600700--0x1D6007FF */ ++#define GPON_TBM_BASE (KSEG1 | 0x1D600700) ++#define GPON_TBM_END (KSEG1 | 0x1D6007FF) ++#define GPON_TBM_SIZE 0x00000100 ++/** address range for pe0 ++ 0x1D610000--0x1D61FFFF */ ++#define GPON_PE0_BASE (KSEG1 | 0x1D610000) ++#define GPON_PE0_END (KSEG1 | 0x1D61FFFF) ++#define GPON_PE0_SIZE 0x00010000 ++/** address range for pe1 ++ 0x1D620000--0x1D62FFFF */ ++#define GPON_PE1_BASE (KSEG1 | 0x1D620000) ++#define GPON_PE1_END (KSEG1 | 0x1D62FFFF) ++#define GPON_PE1_SIZE 0x00010000 ++/** address range for pe2 ++ 0x1D630000--0x1D63FFFF */ ++#define GPON_PE2_BASE (KSEG1 | 0x1D630000) ++#define GPON_PE2_END (KSEG1 | 0x1D63FFFF) ++#define GPON_PE2_SIZE 0x00010000 ++/** address range for pe3 ++ 0x1D640000--0x1D64FFFF */ ++#define GPON_PE3_BASE (KSEG1 | 0x1D640000) ++#define GPON_PE3_END (KSEG1 | 0x1D64FFFF) ++#define GPON_PE3_SIZE 0x00010000 ++/** address range for pe4 ++ 0x1D650000--0x1D65FFFF */ ++#define GPON_PE4_BASE (KSEG1 | 0x1D650000) ++#define GPON_PE4_END (KSEG1 | 0x1D65FFFF) ++#define GPON_PE4_SIZE 0x00010000 ++/** address range for pe5 ++ 0x1D660000--0x1D66FFFF */ ++#define GPON_PE5_BASE (KSEG1 | 0x1D660000) ++#define GPON_PE5_END (KSEG1 | 0x1D66FFFF) ++#define GPON_PE5_SIZE 0x00010000 ++/** address range for sys_gpe ++ 0x1D700000--0x1D7000FF */ ++#define GPON_SYS_GPE_BASE (KSEG1 | 0x1D700000) ++#define GPON_SYS_GPE_END (KSEG1 | 0x1D7000FF) ++#define GPON_SYS_GPE_SIZE 0x00000100 ++/** address range for eim ++ 0x1D800000--0x1D800FFF */ ++#define GPON_EIM_BASE (KSEG1 | 0x1D800000) ++#define GPON_EIM_END (KSEG1 | 0x1D800FFF) ++#define GPON_EIM_SIZE 0x00001000 ++/** address range for sxgmii ++ 0x1D808800--0x1D8088FF */ ++#define GPON_SXGMII_BASE (KSEG1 | 0x1D808800) ++#define GPON_SXGMII_END (KSEG1 | 0x1D8088FF) ++#define GPON_SXGMII_SIZE 0x00000100 ++/** address range for sgmii ++ 0x1D808C00--0x1D808CFF */ ++#define GPON_SGMII_BASE (KSEG1 | 0x1D808C00) ++#define GPON_SGMII_END (KSEG1 | 0x1D808CFF) ++#define GPON_SGMII_SIZE 0x00000100 ++/** address range for gpio0 ++ 0x1D810000--0x1D81007F */ ++#define GPON_GPIO0_BASE (KSEG1 | 0x1D810000) ++#define GPON_GPIO0_END (KSEG1 | 0x1D81007F) ++#define GPON_GPIO0_SIZE 0x00000080 ++/** address range for gpio2 ++ 0x1D810100--0x1D81017F */ ++#define GPON_GPIO2_BASE (KSEG1 | 0x1D810100) ++#define GPON_GPIO2_END (KSEG1 | 0x1D81017F) ++#define GPON_GPIO2_SIZE 0x00000080 ++/** address range for sys_eth ++ 0x1DB00000--0x1DB000FF */ ++#define GPON_SYS_ETH_BASE (KSEG1 | 0x1DB00000) ++#define GPON_SYS_ETH_END (KSEG1 | 0x1DB000FF) ++#define GPON_SYS_ETH_SIZE 0x00000100 ++/** address range for padctrl0 ++ 0x1DB01000--0x1DB010FF */ ++#define GPON_PADCTRL0_BASE (KSEG1 | 0x1DB01000) ++#define GPON_PADCTRL0_END (KSEG1 | 0x1DB010FF) ++#define GPON_PADCTRL0_SIZE 0x00000100 ++/** address range for padctrl2 ++ 0x1DB02000--0x1DB020FF */ ++#define GPON_PADCTRL2_BASE (KSEG1 | 0x1DB02000) ++#define GPON_PADCTRL2_END (KSEG1 | 0x1DB020FF) ++#define GPON_PADCTRL2_SIZE 0x00000100 ++/** address range for gtc ++ 0x1DC05000--0x1DC052D4 */ ++#define GPON_GTC_BASE (KSEG1 | 0x1DC05000) ++#define GPON_GTC_END (KSEG1 | 0x1DC052D4) ++#define GPON_GTC_SIZE 0x000002D5 ++/** address range for pma ++ 0x1DD00000--0x1DD003FF */ ++#define GPON_PMA_BASE (KSEG1 | 0x1DD00000) ++#define GPON_PMA_END (KSEG1 | 0x1DD003FF) ++#define GPON_PMA_SIZE 0x00000400 ++/** address range for fcsic ++ 0x1DD00600--0x1DD0061F */ ++#define GPON_FCSIC_BASE (KSEG1 | 0x1DD00600) ++#define GPON_FCSIC_END (KSEG1 | 0x1DD0061F) ++#define GPON_FCSIC_SIZE 0x00000020 ++/** address range for pma_int200 ++ 0x1DD00700--0x1DD0070F */ ++#define GPON_PMA_INT200_BASE (KSEG1 | 0x1DD00700) ++#define GPON_PMA_INT200_END (KSEG1 | 0x1DD0070F) ++#define GPON_PMA_INT200_SIZE 0x00000010 ++/** address range for pma_inttx ++ 0x1DD00720--0x1DD0072F */ ++#define GPON_PMA_INTTX_BASE (KSEG1 | 0x1DD00720) ++#define GPON_PMA_INTTX_END (KSEG1 | 0x1DD0072F) ++#define GPON_PMA_INTTX_SIZE 0x00000010 ++/** address range for pma_intrx ++ 0x1DD00740--0x1DD0074F */ ++#define GPON_PMA_INTRX_BASE (KSEG1 | 0x1DD00740) ++#define GPON_PMA_INTRX_END (KSEG1 | 0x1DD0074F) ++#define GPON_PMA_INTRX_SIZE 0x00000010 ++/** address range for gtc_pma ++ 0x1DEFFF00--0x1DEFFFFF */ ++#define GPON_GTC_PMA_BASE (KSEG1 | 0x1DEFFF00) ++#define GPON_GTC_PMA_END (KSEG1 | 0x1DEFFFFF) ++#define GPON_GTC_PMA_SIZE 0x00000100 ++/** address range for sys ++ 0x1DF00000--0x1DF000FF */ ++#define GPON_SYS_BASE (KSEG1 | 0x1DF00000) ++#define GPON_SYS_END (KSEG1 | 0x1DF000FF) ++#define GPON_SYS_SIZE 0x00000100 ++/** address range for asc1 ++ 0x1E100B00--0x1E100BFF */ ++#define GPON_ASC1_BASE (KSEG1 | 0x1E100B00) ++#define GPON_ASC1_END (KSEG1 | 0x1E100BFF) ++#define GPON_ASC1_SIZE 0x00000100 ++/** address range for asc0 ++ 0x1E100C00--0x1E100CFF */ ++#define GPON_ASC0_BASE (KSEG1 | 0x1E100C00) ++#define GPON_ASC0_END (KSEG1 | 0x1E100CFF) ++#define GPON_ASC0_SIZE 0x00000100 ++/** address range for i2c ++ 0x1E200000--0x1E20FFFF */ ++#define GPON_I2C_BASE (KSEG1 | 0x1E200000) ++#define GPON_I2C_END (KSEG1 | 0x1E20FFFF) ++#define GPON_I2C_SIZE 0x00010000 ++/** address range for gpio1 ++ 0x1E800100--0x1E80017F */ ++#define GPON_GPIO1_BASE (KSEG1 | 0x1E800100) ++#define GPON_GPIO1_END (KSEG1 | 0x1E80017F) ++#define GPON_GPIO1_SIZE 0x00000080 ++/** address range for gpio3 ++ 0x1E800200--0x1E80027F */ ++#define GPON_GPIO3_BASE (KSEG1 | 0x1E800200) ++#define GPON_GPIO3_END (KSEG1 | 0x1E80027F) ++#define GPON_GPIO3_SIZE 0x00000080 ++/** address range for gpio4 ++ 0x1E800300--0x1E80037F */ ++#define GPON_GPIO4_BASE (KSEG1 | 0x1E800300) ++#define GPON_GPIO4_END (KSEG1 | 0x1E80037F) ++#define GPON_GPIO4_SIZE 0x00000080 ++/** address range for padctrl1 ++ 0x1E800400--0x1E8004FF */ ++#define GPON_PADCTRL1_BASE (KSEG1 | 0x1E800400) ++#define GPON_PADCTRL1_END (KSEG1 | 0x1E8004FF) ++#define GPON_PADCTRL1_SIZE 0x00000100 ++/** address range for padctrl3 ++ 0x1E800500--0x1E8005FF */ ++#define GPON_PADCTRL3_BASE (KSEG1 | 0x1E800500) ++#define GPON_PADCTRL3_END (KSEG1 | 0x1E8005FF) ++#define GPON_PADCTRL3_SIZE 0x00000100 ++/** address range for padctrl4 ++ 0x1E800600--0x1E8006FF */ ++#define GPON_PADCTRL4_BASE (KSEG1 | 0x1E800600) ++#define GPON_PADCTRL4_END (KSEG1 | 0x1E8006FF) ++#define GPON_PADCTRL4_SIZE 0x00000100 ++/** address range for status ++ 0x1E802000--0x1E80207F */ ++#define GPON_STATUS_BASE (KSEG1 | 0x1E802000) ++#define GPON_STATUS_END (KSEG1 | 0x1E80207F) ++#define GPON_STATUS_SIZE 0x00000080 ++/** address range for dcdc_1v0 ++ 0x1E803000--0x1E8033FF */ ++#define GPON_DCDC_1V0_BASE (KSEG1 | 0x1E803000) ++#define GPON_DCDC_1V0_END (KSEG1 | 0x1E8033FF) ++#define GPON_DCDC_1V0_SIZE 0x00000400 ++/** address range for dcdc_ddr ++ 0x1E804000--0x1E8043FF */ ++#define GPON_DCDC_DDR_BASE (KSEG1 | 0x1E804000) ++#define GPON_DCDC_DDR_END (KSEG1 | 0x1E8043FF) ++#define GPON_DCDC_DDR_SIZE 0x00000400 ++/** address range for dcdc_apd ++ 0x1E805000--0x1E8053FF */ ++#define GPON_DCDC_APD_BASE (KSEG1 | 0x1E805000) ++#define GPON_DCDC_APD_END (KSEG1 | 0x1E8053FF) ++#define GPON_DCDC_APD_SIZE 0x00000400 ++/** address range for sys1 ++ 0x1EF00000--0x1EF000FF */ ++#define GPON_SYS1_BASE (KSEG1 | 0x1EF00000) ++#define GPON_SYS1_END (KSEG1 | 0x1EF000FF) ++#define GPON_SYS1_SIZE 0x00000100 ++/** address range for sbs0ctrl ++ 0x1F080000--0x1F0801FF */ ++#define GPON_SBS0CTRL_BASE (KSEG1 | 0x1F080000) ++#define GPON_SBS0CTRL_END (KSEG1 | 0x1F0801FF) ++#define GPON_SBS0CTRL_SIZE 0x00000200 ++/** address range for sbs0red ++ 0x1F080200--0x1F08027F */ ++#define GPON_SBS0RED_BASE (KSEG1 | 0x1F080200) ++#define GPON_SBS0RED_END (KSEG1 | 0x1F08027F) ++#define GPON_SBS0RED_SIZE 0x00000080 ++/** address range for sbs0ram ++ 0x1F200000--0x1F32FFFF */ ++#define GPON_SBS0RAM_BASE (KSEG1 | 0x1F200000) ++#define GPON_SBS0RAM_END (KSEG1 | 0x1F32FFFF) ++#define GPON_SBS0RAM_SIZE 0x00130000 ++/** address range for ddrdb ++ 0x1F701000--0x1F701FFF */ ++#define GPON_DDRDB_BASE (KSEG1 | 0x1F701000) ++#define GPON_DDRDB_END (KSEG1 | 0x1F701FFF) ++#define GPON_DDRDB_SIZE 0x00001000 ++/** address range for sbiu ++ 0x1F880000--0x1F8800FF */ ++#define GPON_SBIU_BASE (KSEG1 | 0x1F880000) ++#define GPON_SBIU_END (KSEG1 | 0x1F8800FF) ++#define GPON_SBIU_SIZE 0x00000100 ++/** address range for icu0 ++ 0x1F880200--0x1F8802DF */ ++#define GPON_ICU0_BASE (KSEG1 | 0x1F880200) ++#define GPON_ICU0_END (KSEG1 | 0x1F8802DF) ++#define GPON_ICU0_SIZE 0x000000E0 ++/** address range for icu1 ++ 0x1F880300--0x1F8803DF */ ++#define GPON_ICU1_BASE (KSEG1 | 0x1F880300) ++#define GPON_ICU1_END (KSEG1 | 0x1F8803DF) ++#define GPON_ICU1_SIZE 0x000000E0 ++/** address range for wdt ++ 0x1F8803F0--0x1F8803FF */ ++#define GPON_WDT_BASE (KSEG1 | 0x1F8803F0) ++#define GPON_WDT_END (KSEG1 | 0x1F8803FF) ++#define GPON_WDT_SIZE 0x00000010 ++ ++/*! @} */ /* GPON_BASE */ ++ ++#endif /* _gpon_reg_base_h */ ++ +diff --git a/arch/mips/include/asm/mach-lantiq/falcon/i2c_reg.h b/arch/mips/include/asm/mach-lantiq/falcon/i2c_reg.h +new file mode 100644 +index 0000000..5c94618 +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/i2c_reg.h +@@ -0,0 +1,830 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++ ++#ifndef _i2c_reg_h ++#define _i2c_reg_h ++ ++/** \addtogroup I2C_REGISTER ++ @{ ++*/ ++/* access macros */ ++#define i2c_r32(reg) reg_r32(&i2c->reg) ++#define i2c_w32(val, reg) reg_w32(val, &i2c->reg) ++#define i2c_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &i2c->reg) ++#define i2c_r32_table(reg, idx) reg_r32_table(i2c->reg, idx) ++#define i2c_w32_table(val, reg, idx) reg_w32_table(val, i2c->reg, idx) ++#define i2c_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, i2c->reg, idx) ++#define i2c_adr_table(reg, idx) adr_table(i2c->reg, idx) ++ ++ ++/** I2C register structure */ ++struct gpon_reg_i2c ++{ ++ /** I2C Kernel Clock Control Register */ ++ unsigned int clc; /* 0x00000000 */ ++ /** Reserved */ ++ unsigned int res_0; /* 0x00000004 */ ++ /** I2C Identification Register */ ++ unsigned int id; /* 0x00000008 */ ++ /** Reserved */ ++ unsigned int res_1; /* 0x0000000C */ ++ /** I2C RUN Control Register ++ This register enables and disables the I2C peripheral. Before enabling, the I2C has to be configured properly. After enabling no configuration is possible */ ++ unsigned int run_ctrl; /* 0x00000010 */ ++ /** I2C End Data Control Register ++ This register is used to either turn around the data transmission direction or to address another slave without sending a stop condition. Also the software can stop the slave-transmitter by sending a not-accolade when working as master-receiver or even stop data transmission immediately when operating as master-transmitter. The writing to the bits of this control register is only effective when in MASTER RECEIVES BYTES, MASTER TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state */ ++ unsigned int endd_ctrl; /* 0x00000014 */ ++ /** I2C Fractional Divider Configuration Register ++ These register is used to program the fractional divider of the I2C bus. Before the peripheral is switched on by setting the RUN-bit the two (fixed) values for the two operating frequencies are programmed into these (configuration) registers. The Register FDIV_HIGH_CFG has the same layout as I2C_FDIV_CFG. */ ++ unsigned int fdiv_cfg; /* 0x00000018 */ ++ /** I2C Fractional Divider (highspeed mode) Configuration Register ++ These register is used to program the fractional divider of the I2C bus. Before the peripheral is switched on by setting the RUN-bit the two (fixed) values for the two operating frequencies are programmed into these (configuration) registers. The Register FDIV_CFG has the same layout as I2C_FDIV_CFG. */ ++ unsigned int fdiv_high_cfg; /* 0x0000001C */ ++ /** I2C Address Configuration Register */ ++ unsigned int addr_cfg; /* 0x00000020 */ ++ /** I2C Bus Status Register ++ This register gives a status information of the I2C. This additional information can be used by the software to start proper actions. */ ++ unsigned int bus_stat; /* 0x00000024 */ ++ /** I2C FIFO Configuration Register */ ++ unsigned int fifo_cfg; /* 0x00000028 */ ++ /** I2C Maximum Received Packet Size Register */ ++ unsigned int mrps_ctrl; /* 0x0000002C */ ++ /** I2C Received Packet Size Status Register */ ++ unsigned int rps_stat; /* 0x00000030 */ ++ /** I2C Transmit Packet Size Register */ ++ unsigned int tps_ctrl; /* 0x00000034 */ ++ /** I2C Filled FIFO Stages Status Register */ ++ unsigned int ffs_stat; /* 0x00000038 */ ++ /** Reserved */ ++ unsigned int res_2; /* 0x0000003C */ ++ /** I2C Timing Configuration Register */ ++ unsigned int tim_cfg; /* 0x00000040 */ ++ /** Reserved */ ++ unsigned int res_3[7]; /* 0x00000044 */ ++ /** I2C Error Interrupt Request Source Mask Register */ ++ unsigned int err_irqsm; /* 0x00000060 */ ++ /** I2C Error Interrupt Request Source Status Register */ ++ unsigned int err_irqss; /* 0x00000064 */ ++ /** I2C Error Interrupt Request Source Clear Register */ ++ unsigned int err_irqsc; /* 0x00000068 */ ++ /** Reserved */ ++ unsigned int res_4; /* 0x0000006C */ ++ /** I2C Protocol Interrupt Request Source Mask Register */ ++ unsigned int p_irqsm; /* 0x00000070 */ ++ /** I2C Protocol Interrupt Request Source Status Register */ ++ unsigned int p_irqss; /* 0x00000074 */ ++ /** I2C Protocol Interrupt Request Source Clear Register */ ++ unsigned int p_irqsc; /* 0x00000078 */ ++ /** Reserved */ ++ unsigned int res_5; /* 0x0000007C */ ++ /** I2C Raw Interrupt Status Register */ ++ unsigned int ris; /* 0x00000080 */ ++ /** I2C Interrupt Mask Control Register */ ++ unsigned int imsc; /* 0x00000084 */ ++ /** I2C Masked Interrupt Status Register */ ++ unsigned int mis; /* 0x00000088 */ ++ /** I2C Interrupt Clear Register */ ++ unsigned int icr; /* 0x0000008C */ ++ /** I2C Interrupt Set Register */ ++ unsigned int isr; /* 0x00000090 */ ++ /** I2C DMA Enable Register */ ++ unsigned int dmae; /* 0x00000094 */ ++ /** Reserved */ ++ unsigned int res_6[8154]; /* 0x00000098 */ ++ /** I2C Transmit Data Register */ ++ unsigned int txd; /* 0x00008000 */ ++ /** Reserved */ ++ unsigned int res_7[4095]; /* 0x00008004 */ ++ /** I2C Receive Data Register */ ++ unsigned int rxd; /* 0x0000C000 */ ++ /** Reserved */ ++ unsigned int res_8[4095]; /* 0x0000C004 */ ++}; ++ ++ ++/* Fields of "I2C Kernel Clock Control Register" */ ++/** Clock Divider for Optional Run Mode (AHB peripherals) ++ Max 8-bit divider value. Note: As long as the new divider value ORMC is not valid, the register returns 0x0000 00xx on reading. */ ++#define I2C_CLC_ORMC_MASK 0x00FF0000 ++/** field offset */ ++#define I2C_CLC_ORMC_OFFSET 16 ++/** Clock Divider for Normal Run Mode ++ Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long as the new divider value RMC is not valid, the register returns 0x0000 00xx on reading. */ ++#define I2C_CLC_RMC_MASK 0x0000FF00 ++/** field offset */ ++#define I2C_CLC_RMC_OFFSET 8 ++/** Fast Shut-Off Enable Bit */ ++#define I2C_CLC_FSOE 0x00000020 ++/* Disable ++#define I2C_CLC_FSOE_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_CLC_FSOE_EN 0x00000020 ++/** Suspend Bit Write Enable for OCDS */ ++#define I2C_CLC_SBWE 0x00000010 ++/* Disable ++#define I2C_CLC_SBWE_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_CLC_SBWE_EN 0x00000010 ++/** Disable External Request Disable */ ++#define I2C_CLC_EDIS 0x00000008 ++/* Enable ++#define I2C_CLC_EDIS_EN 0x00000000 */ ++/** Disable */ ++#define I2C_CLC_EDIS_DIS 0x00000008 ++/** Suspend Enable Bit for OCDS */ ++#define I2C_CLC_SPEN 0x00000004 ++/* Disable ++#define I2C_CLC_SPEN_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_CLC_SPEN_EN 0x00000004 ++/** Disable Status Bit ++ Bit DISS can be modified only by writing to bit DISR */ ++#define I2C_CLC_DISS 0x00000002 ++/* Enable ++#define I2C_CLC_DISS_EN 0x00000000 */ ++/** Disable */ ++#define I2C_CLC_DISS_DIS 0x00000002 ++/** Disable Request Bit */ ++#define I2C_CLC_DISR 0x00000001 ++/* Module disable not requested ++#define I2C_CLC_DISR_OFF 0x00000000 */ ++/** Module disable requested */ ++#define I2C_CLC_DISR_ON 0x00000001 ++ ++/* Fields of "I2C Identification Register" */ ++/** Module ID */ ++#define I2C_ID_ID_MASK 0x0000FF00 ++/** field offset */ ++#define I2C_ID_ID_OFFSET 8 ++/** Revision */ ++#define I2C_ID_REV_MASK 0x000000FF ++/** field offset */ ++#define I2C_ID_REV_OFFSET 0 ++ ++/* Fields of "I2C RUN Control Register" */ ++/** Enabling I2C Interface ++ Only when this bit is set to zero, the configuration registers of the I2C peripheral are writable by SW. */ ++#define I2C_RUN_CTRL_RUN 0x00000001 ++/* Disable ++#define I2C_RUN_CTRL_RUN_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_RUN_CTRL_RUN_EN 0x00000001 ++ ++/* Fields of "I2C End Data Control Register" */ ++/** Set End of Transmission ++ Note:Do not write '1' to this bit when bus is free. This will cause an abort after the first byte when a new transfer is started. */ ++#define I2C_ENDD_CTRL_SETEND 0x00000002 ++/* No-Operation ++#define I2C_ENDD_CTRL_SETEND_NOP 0x00000000 */ ++/** Master Receives Bytes */ ++#define I2C_ENDD_CTRL_SETEND_MRB 0x00000002 ++/** Set Restart Condition */ ++#define I2C_ENDD_CTRL_SETRSC 0x00000001 ++/* No-Operation ++#define I2C_ENDD_CTRL_SETRSC_NOP 0x00000000 */ ++/** Master Restart */ ++#define I2C_ENDD_CTRL_SETRSC_RESTART 0x00000001 ++ ++/* Fields of "I2C Fractional Divider Configuration Register" */ ++/** Decrement Value of fractional divider */ ++#define I2C_FDIV_CFG_INC_MASK 0x00FF0000 ++/** field offset */ ++#define I2C_FDIV_CFG_INC_OFFSET 16 ++/** Increment Value of fractional divider */ ++#define I2C_FDIV_CFG_DEC_MASK 0x000007FF ++/** field offset */ ++#define I2C_FDIV_CFG_DEC_OFFSET 0 ++ ++/* Fields of "I2C Fractional Divider (highspeed mode) Configuration Register" */ ++/** Decrement Value of fractional divider */ ++#define I2C_FDIV_HIGH_CFG_INC_MASK 0x00FF0000 ++/** field offset */ ++#define I2C_FDIV_HIGH_CFG_INC_OFFSET 16 ++/** Increment Value of fractional divider */ ++#define I2C_FDIV_HIGH_CFG_DEC_MASK 0x000007FF ++/** field offset */ ++#define I2C_FDIV_HIGH_CFG_DEC_OFFSET 0 ++ ++/* Fields of "I2C Address Configuration Register" */ ++/** Stop on Packet End ++ If device works as receiver a not acknowledge is generated in both cases. After successful transmission of a master code (during high speed mode) SOPE is not considered till a stop condition is manually generated by SETEND. */ ++#define I2C_ADDR_CFG_SOPE 0x00200000 ++/* Disable ++#define I2C_ADDR_CFG_SOPE_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_ADDR_CFG_SOPE_EN 0x00200000 ++/** Stop on Not Acknowledge ++ After successful transmission of a master code (during high speed mode) SONA is not considered till a stop condition is manually generated by SETEND. */ ++#define I2C_ADDR_CFG_SONA 0x00100000 ++/* Disable ++#define I2C_ADDR_CFG_SONA_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_ADDR_CFG_SONA_EN 0x00100000 ++/** Master Enable */ ++#define I2C_ADDR_CFG_MnS 0x00080000 ++/* Disable ++#define I2C_ADDR_CFG_MnS_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_ADDR_CFG_MnS_EN 0x00080000 ++/** Master Code Enable */ ++#define I2C_ADDR_CFG_MCE 0x00040000 ++/* Disable ++#define I2C_ADDR_CFG_MCE_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_ADDR_CFG_MCE_EN 0x00040000 ++/** General Call Enable */ ++#define I2C_ADDR_CFG_GCE 0x00020000 ++/* Disable ++#define I2C_ADDR_CFG_GCE_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_ADDR_CFG_GCE_EN 0x00020000 ++/** Ten Bit Address Mode */ ++#define I2C_ADDR_CFG_TBAM 0x00010000 ++/* 7-bit address mode enabled. ++#define I2C_ADDR_CFG_TBAM_7bit 0x00000000 */ ++/** 10-bit address mode enabled. */ ++#define I2C_ADDR_CFG_TBAM_10bit 0x00010000 ++/** I2C Bus device address ++ This is the address of this device. (Watch out for reserved addresses by referring to Phillips Spec V2.1) This could either be a 7bit- address (bits [7:1]) or a 10bit- address (bits [9:0]). Note:The validity of the bits are in accordance with the TBAM bit. Bit-1 (Bit-0) is the LSB of the device address. */ ++#define I2C_ADDR_CFG_ADR_MASK 0x000003FF ++/** field offset */ ++#define I2C_ADDR_CFG_ADR_OFFSET 0 ++ ++/* Fields of "I2C Bus Status Register" */ ++/** Read / not Write */ ++#define I2C_BUS_STAT_RNW 0x00000004 ++/* Write to I2C Bus. ++#define I2C_BUS_STAT_RNW_WRITE 0x00000000 */ ++/** Read from I2C Bus. */ ++#define I2C_BUS_STAT_RNW_READ 0x00000004 ++/** Bus Status */ ++#define I2C_BUS_STAT_BS_MASK 0x00000003 ++/** field offset */ ++#define I2C_BUS_STAT_BS_OFFSET 0 ++/** I2C Bus is free. */ ++#define I2C_BUS_STAT_BS_FREE 0x00000000 ++/** A start condition has been detected on the bus (bus busy). */ ++#define I2C_BUS_STAT_BS_SC 0x00000001 ++/** The device is working as master and has claimed the control on the I2C-bus (busy master). */ ++#define I2C_BUS_STAT_BS_BM 0x00000002 ++/** A remote master has accessed this device as slave. */ ++#define I2C_BUS_STAT_BS_RM 0x00000003 ++ ++/* Fields of "I2C FIFO Configuration Register" */ ++/** TX FIFO Flow Control */ ++#define I2C_FIFO_CFG_TXFC 0x00020000 ++/* TX FIFO not as Flow Controller ++#define I2C_FIFO_CFG_TXFC_TXNFC 0x00000000 */ ++/** RX FIFO Flow Control */ ++#define I2C_FIFO_CFG_RXFC 0x00010000 ++/* RX FIFO not as Flow Controller ++#define I2C_FIFO_CFG_RXFC_RXNFC 0x00000000 */ ++/** The reset value depends on the used character sizes of the peripheral. The maximum selectable alignment depends on the maximum number of characters per stage. */ ++#define I2C_FIFO_CFG_TXFA_MASK 0x00003000 ++/** field offset */ ++#define I2C_FIFO_CFG_TXFA_OFFSET 12 ++/** Byte aligned (character alignment) */ ++#define I2C_FIFO_CFG_TXFA_TXFA0 0x00000000 ++/** Half word aligned (character alignment of two characters) */ ++#define I2C_FIFO_CFG_TXFA_TXFA1 0x00001000 ++/** Word aligned (character alignment of four characters) */ ++#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000 ++/** Double word aligned (character alignment of eight */ ++#define I2C_FIFO_CFG_TXFA_TXFA3 0x00003000 ++/** The reset value depends on the used character sizes of the peripheral. The maximum selectable alignment depends on the maximum number of characters per stage. */ ++#define I2C_FIFO_CFG_RXFA_MASK 0x00000300 ++/** field offset */ ++#define I2C_FIFO_CFG_RXFA_OFFSET 8 ++/** Byte aligned (character alignment) */ ++#define I2C_FIFO_CFG_RXFA_RXFA0 0x00000000 ++/** Half word aligned (character alignment of two characters) */ ++#define I2C_FIFO_CFG_RXFA_RXFA1 0x00000100 ++/** Word aligned (character alignment of four characters) */ ++#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200 ++/** Double word aligned (character alignment of eight */ ++#define I2C_FIFO_CFG_RXFA_RXFA3 0x00000300 ++/** DMA controller does not support a burst size of 2 words. The reset value is the half of the FIFO size. The maximum selectable burst size is smaller than the FIFO size. */ ++#define I2C_FIFO_CFG_TXBS_MASK 0x00000030 ++/** field offset */ ++#define I2C_FIFO_CFG_TXBS_OFFSET 4 ++/** 1 word */ ++#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000 ++/** 2 words */ ++#define I2C_FIFO_CFG_TXBS_TXBS1 0x00000010 ++/** 4 words */ ++#define I2C_FIFO_CFG_TXBS_TXBS2 0x00000020 ++/** 8 words */ ++#define I2C_FIFO_CFG_TXBS_TXBS3 0x00000030 ++/** DMA controller does not support a burst size of 2 words. The reset value is the half of the FIFO size. The maximum selectable burst size is smaller than the FIFO size. */ ++#define I2C_FIFO_CFG_RXBS_MASK 0x00000003 ++/** field offset */ ++#define I2C_FIFO_CFG_RXBS_OFFSET 0 ++/** 1 word */ ++#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000 ++/** 2 words */ ++#define I2C_FIFO_CFG_RXBS_RXBS1 0x00000001 ++/** 4 words */ ++#define I2C_FIFO_CFG_RXBS_RXBS2 0x00000002 ++/** 8 words */ ++#define I2C_FIFO_CFG_RXBS_RXBS3 0x00000003 ++ ++/* Fields of "I2C Maximum Received Packet Size Register" */ ++/** MRPS */ ++#define I2C_MRPS_CTRL_MRPS_MASK 0x00003FFF ++/** field offset */ ++#define I2C_MRPS_CTRL_MRPS_OFFSET 0 ++ ++/* Fields of "I2C Received Packet Size Status Register" */ ++/** RPS */ ++#define I2C_RPS_STAT_RPS_MASK 0x00003FFF ++/** field offset */ ++#define I2C_RPS_STAT_RPS_OFFSET 0 ++ ++/* Fields of "I2C Transmit Packet Size Register" */ ++/** TPS */ ++#define I2C_TPS_CTRL_TPS_MASK 0x00003FFF ++/** field offset */ ++#define I2C_TPS_CTRL_TPS_OFFSET 0 ++ ++/* Fields of "I2C Filled FIFO Stages Status Register" */ ++/** FFS */ ++#define I2C_FFS_STAT_FFS_MASK 0x0000000F ++/** field offset */ ++#define I2C_FFS_STAT_FFS_OFFSET 0 ++ ++/* Fields of "I2C Timing Configuration Register" */ ++/** SDA Delay Stages for Start/Stop bit in High Speed Mode ++ The actual delay is calculated as the value of this field + 3 */ ++#define I2C_TIM_CFG_HS_SDA_DEL_MASK 0x00070000 ++/** field offset */ ++#define I2C_TIM_CFG_HS_SDA_DEL_OFFSET 16 ++/** Enable Fast Mode SCL Low period timing */ ++#define I2C_TIM_CFG_FS_SCL_LOW 0x00008000 ++/* Disable ++#define I2C_TIM_CFG_FS_SCL_LOW_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_TIM_CFG_FS_SCL_LOW_EN 0x00008000 ++/** SCL Delay Stages for Hold Time Start (Restart) Bit. ++ The actual delay is calculated as the value of this field + 2 */ ++#define I2C_TIM_CFG_SCL_DEL_HD_STA_MASK 0x00000E00 ++/** field offset */ ++#define I2C_TIM_CFG_SCL_DEL_HD_STA_OFFSET 9 ++/** SDA Delay Stages for Start/Stop bit in High Speed Mode ++ The actual delay is calculated as the value of this field + 3 */ ++#define I2C_TIM_CFG_HS_SDA_DEL_HD_DAT_MASK 0x000001C0 ++/** field offset */ ++#define I2C_TIM_CFG_HS_SDA_DEL_HD_DAT_OFFSET 6 ++/** SDA Delay Stages for Start/Stop bit in High Speed Mode ++ The actual delay is calculated as the value of this field + 3 */ ++#define I2C_TIM_CFG_SDA_DEL_HD_DAT_MASK 0x0000003F ++/** field offset */ ++#define I2C_TIM_CFG_SDA_DEL_HD_DAT_OFFSET 0 ++ ++/* Fields of "I2C Error Interrupt Request Source Mask Register" */ ++/** Enables the corresponding error interrupt. */ ++#define I2C_ERR_IRQSM_TXF_OFL 0x00000008 ++/* Disable ++#define I2C_ERR_IRQSM_TXF_OFL_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_ERR_IRQSM_TXF_OFL_EN 0x00000008 ++/** Enables the corresponding error interrupt. */ ++#define I2C_ERR_IRQSM_TXF_UFL 0x00000004 ++/* Disable ++#define I2C_ERR_IRQSM_TXF_UFL_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_ERR_IRQSM_TXF_UFL_EN 0x00000004 ++/** Enables the corresponding error interrupt. */ ++#define I2C_ERR_IRQSM_RXF_OFL 0x00000002 ++/* Disable ++#define I2C_ERR_IRQSM_RXF_OFL_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_ERR_IRQSM_RXF_OFL_EN 0x00000002 ++/** Enables the corresponding error interrupt. */ ++#define I2C_ERR_IRQSM_RXF_UFL 0x00000001 ++/* Disable ++#define I2C_ERR_IRQSM_RXF_UFL_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_ERR_IRQSM_RXF_UFL_EN 0x00000001 ++ ++/* Fields of "I2C Error Interrupt Request Source Status Register" */ ++/** TXF_OFL */ ++#define I2C_ERR_IRQSS_TXF_OFL 0x00000008 ++/* Nothing ++#define I2C_ERR_IRQSS_TXF_OFL_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_ERR_IRQSS_TXF_OFL_INTOCC 0x00000008 ++/** TXF_UFL */ ++#define I2C_ERR_IRQSS_TXF_UFL 0x00000004 ++/* Nothing ++#define I2C_ERR_IRQSS_TXF_UFL_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_ERR_IRQSS_TXF_UFL_INTOCC 0x00000004 ++/** RXF_OFL */ ++#define I2C_ERR_IRQSS_RXF_OFL 0x00000002 ++/* Nothing ++#define I2C_ERR_IRQSS_RXF_OFL_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_ERR_IRQSS_RXF_OFL_INTOCC 0x00000002 ++/** RXF_UFL */ ++#define I2C_ERR_IRQSS_RXF_UFL 0x00000001 ++/* Nothing ++#define I2C_ERR_IRQSS_RXF_UFL_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_ERR_IRQSS_RXF_UFL_INTOCC 0x00000001 ++ ++/* Fields of "I2C Error Interrupt Request Source Clear Register" */ ++/** TXF_OFL */ ++#define I2C_ERR_IRQSC_TXF_OFL 0x00000008 ++/* No-Operation ++#define I2C_ERR_IRQSC_TXF_OFL_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_ERR_IRQSC_TXF_OFL_CLR 0x00000008 ++/** TXF_UFL */ ++#define I2C_ERR_IRQSC_TXF_UFL 0x00000004 ++/* No-Operation ++#define I2C_ERR_IRQSC_TXF_UFL_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_ERR_IRQSC_TXF_UFL_CLR 0x00000004 ++/** RXF_OFL */ ++#define I2C_ERR_IRQSC_RXF_OFL 0x00000002 ++/* No-Operation ++#define I2C_ERR_IRQSC_RXF_OFL_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_ERR_IRQSC_RXF_OFL_CLR 0x00000002 ++/** RXF_UFL */ ++#define I2C_ERR_IRQSC_RXF_UFL 0x00000001 ++/* No-Operation ++#define I2C_ERR_IRQSC_RXF_UFL_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_ERR_IRQSC_RXF_UFL_CLR 0x00000001 ++ ++/* Fields of "I2C Protocol Interrupt Request Source Mask Register" */ ++/** Enables the corresponding interrupt. */ ++#define I2C_P_IRQSM_RX 0x00000040 ++/* Disable ++#define I2C_P_IRQSM_RX_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_P_IRQSM_RX_EN 0x00000040 ++/** Enables the corresponding interrupt. */ ++#define I2C_P_IRQSM_TX_END 0x00000020 ++/* Disable ++#define I2C_P_IRQSM_TX_END_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_P_IRQSM_TX_END_EN 0x00000020 ++/** Enables the corresponding interrupt. */ ++#define I2C_P_IRQSM_NACK 0x00000010 ++/* Disable ++#define I2C_P_IRQSM_NACK_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_P_IRQSM_NACK_EN 0x00000010 ++/** Enables the corresponding interrupt. */ ++#define I2C_P_IRQSM_AL 0x00000008 ++/* Disable ++#define I2C_P_IRQSM_AL_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_P_IRQSM_AL_EN 0x00000008 ++/** Enables the corresponding interrupt. */ ++#define I2C_P_IRQSM_MC 0x00000004 ++/* Disable ++#define I2C_P_IRQSM_MC_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_P_IRQSM_MC_EN 0x00000004 ++/** Enables the corresponding interrupt. */ ++#define I2C_P_IRQSM_GC 0x00000002 ++/* Disable ++#define I2C_P_IRQSM_GC_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_P_IRQSM_GC_EN 0x00000002 ++/** Enables the corresponding interrupt. */ ++#define I2C_P_IRQSM_AM 0x00000001 ++/* Disable ++#define I2C_P_IRQSM_AM_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_P_IRQSM_AM_EN 0x00000001 ++ ++/* Fields of "I2C Protocol Interrupt Request Source Status Register" */ ++/** RX */ ++#define I2C_P_IRQSS_RX 0x00000040 ++/* Nothing ++#define I2C_P_IRQSS_RX_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_P_IRQSS_RX_INTOCC 0x00000040 ++/** TX_END */ ++#define I2C_P_IRQSS_TX_END 0x00000020 ++/* Nothing ++#define I2C_P_IRQSS_TX_END_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_P_IRQSS_TX_END_INTOCC 0x00000020 ++/** NACK */ ++#define I2C_P_IRQSS_NACK 0x00000010 ++/* Nothing ++#define I2C_P_IRQSS_NACK_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_P_IRQSS_NACK_INTOCC 0x00000010 ++/** AL */ ++#define I2C_P_IRQSS_AL 0x00000008 ++/* Nothing ++#define I2C_P_IRQSS_AL_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_P_IRQSS_AL_INTOCC 0x00000008 ++/** MC */ ++#define I2C_P_IRQSS_MC 0x00000004 ++/* Nothing ++#define I2C_P_IRQSS_MC_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_P_IRQSS_MC_INTOCC 0x00000004 ++/** GC */ ++#define I2C_P_IRQSS_GC 0x00000002 ++/* Nothing ++#define I2C_P_IRQSS_GC_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_P_IRQSS_GC_INTOCC 0x00000002 ++/** AM */ ++#define I2C_P_IRQSS_AM 0x00000001 ++/* Nothing ++#define I2C_P_IRQSS_AM_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_P_IRQSS_AM_INTOCC 0x00000001 ++ ++/* Fields of "I2C Protocol Interrupt Request Source Clear Register" */ ++/** RX */ ++#define I2C_P_IRQSC_RX 0x00000040 ++/* No-Operation ++#define I2C_P_IRQSC_RX_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_P_IRQSC_RX_CLR 0x00000040 ++/** TX_END */ ++#define I2C_P_IRQSC_TX_END 0x00000020 ++/* No-Operation ++#define I2C_P_IRQSC_TX_END_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_P_IRQSC_TX_END_CLR 0x00000020 ++/** NACK */ ++#define I2C_P_IRQSC_NACK 0x00000010 ++/* No-Operation ++#define I2C_P_IRQSC_NACK_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_P_IRQSC_NACK_CLR 0x00000010 ++/** AL */ ++#define I2C_P_IRQSC_AL 0x00000008 ++/* No-Operation ++#define I2C_P_IRQSC_AL_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_P_IRQSC_AL_CLR 0x00000008 ++/** MC */ ++#define I2C_P_IRQSC_MC 0x00000004 ++/* No-Operation ++#define I2C_P_IRQSC_MC_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_P_IRQSC_MC_CLR 0x00000004 ++/** GC */ ++#define I2C_P_IRQSC_GC 0x00000002 ++/* No-Operation ++#define I2C_P_IRQSC_GC_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_P_IRQSC_GC_CLR 0x00000002 ++/** AM */ ++#define I2C_P_IRQSC_AM 0x00000001 ++/* No-Operation ++#define I2C_P_IRQSC_AM_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_P_IRQSC_AM_CLR 0x00000001 ++ ++/* Fields of "I2C Raw Interrupt Status Register" */ ++/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */ ++#define I2C_RIS_I2C_P_INT 0x00000020 ++/* Nothing ++#define I2C_RIS_I2C_P_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020 ++/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */ ++#define I2C_RIS_I2C_ERR_INT 0x00000010 ++/* Nothing ++#define I2C_RIS_I2C_ERR_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010 ++/** BREQ_INT */ ++#define I2C_RIS_BREQ_INT 0x00000008 ++/* Nothing ++#define I2C_RIS_BREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_RIS_BREQ_INT_INTOCC 0x00000008 ++/** LBREQ_INT */ ++#define I2C_RIS_LBREQ_INT 0x00000004 ++/* Nothing ++#define I2C_RIS_LBREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_RIS_LBREQ_INT_INTOCC 0x00000004 ++/** SREQ_INT */ ++#define I2C_RIS_SREQ_INT 0x00000002 ++/* Nothing ++#define I2C_RIS_SREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_RIS_SREQ_INT_INTOCC 0x00000002 ++/** LSREQ_INT */ ++#define I2C_RIS_LSREQ_INT 0x00000001 ++/* Nothing ++#define I2C_RIS_LSREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_RIS_LSREQ_INT_INTOCC 0x00000001 ++ ++/* Fields of "I2C Interrupt Mask Control Register" */ ++/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */ ++#define I2C_IMSC_I2C_P_INT 0x00000020 ++/* Disable ++#define I2C_IMSC_I2C_P_INT_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_IMSC_I2C_P_INT_EN 0x00000020 ++/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */ ++#define I2C_IMSC_I2C_ERR_INT 0x00000010 ++/* Disable ++#define I2C_IMSC_I2C_ERR_INT_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010 ++/** BREQ_INT */ ++#define I2C_IMSC_BREQ_INT 0x00000008 ++/* Disable ++#define I2C_IMSC_BREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_IMSC_BREQ_INT_EN 0x00000008 ++/** LBREQ_INT */ ++#define I2C_IMSC_LBREQ_INT 0x00000004 ++/* Disable ++#define I2C_IMSC_LBREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_IMSC_LBREQ_INT_EN 0x00000004 ++/** SREQ_INT */ ++#define I2C_IMSC_SREQ_INT 0x00000002 ++/* Disable ++#define I2C_IMSC_SREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_IMSC_SREQ_INT_EN 0x00000002 ++/** LSREQ_INT */ ++#define I2C_IMSC_LSREQ_INT 0x00000001 ++/* Disable ++#define I2C_IMSC_LSREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_IMSC_LSREQ_INT_EN 0x00000001 ++ ++/* Fields of "I2C Masked Interrupt Status Register" */ ++/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */ ++#define I2C_MIS_I2C_P_INT 0x00000020 ++/* Nothing ++#define I2C_MIS_I2C_P_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_MIS_I2C_P_INT_INTOCC 0x00000020 ++/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */ ++#define I2C_MIS_I2C_ERR_INT 0x00000010 ++/* Nothing ++#define I2C_MIS_I2C_ERR_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_MIS_I2C_ERR_INT_INTOCC 0x00000010 ++/** BREQ_INT */ ++#define I2C_MIS_BREQ_INT 0x00000008 ++/* Nothing ++#define I2C_MIS_BREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_MIS_BREQ_INT_INTOCC 0x00000008 ++/** LBREQ_INT */ ++#define I2C_MIS_LBREQ_INT 0x00000004 ++/* Nothing ++#define I2C_MIS_LBREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_MIS_LBREQ_INT_INTOCC 0x00000004 ++/** SREQ_INT */ ++#define I2C_MIS_SREQ_INT 0x00000002 ++/* Nothing ++#define I2C_MIS_SREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_MIS_SREQ_INT_INTOCC 0x00000002 ++/** LSREQ_INT */ ++#define I2C_MIS_LSREQ_INT 0x00000001 ++/* Nothing ++#define I2C_MIS_LSREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_MIS_LSREQ_INT_INTOCC 0x00000001 ++ ++/* Fields of "I2C Interrupt Clear Register" */ ++/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */ ++#define I2C_ICR_I2C_P_INT 0x00000020 ++/* No-Operation ++#define I2C_ICR_I2C_P_INT_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_ICR_I2C_P_INT_CLR 0x00000020 ++/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */ ++#define I2C_ICR_I2C_ERR_INT 0x00000010 ++/* No-Operation ++#define I2C_ICR_I2C_ERR_INT_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_ICR_I2C_ERR_INT_CLR 0x00000010 ++/** BREQ_INT */ ++#define I2C_ICR_BREQ_INT 0x00000008 ++/* No-Operation ++#define I2C_ICR_BREQ_INT_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_ICR_BREQ_INT_CLR 0x00000008 ++/** LBREQ_INT */ ++#define I2C_ICR_LBREQ_INT 0x00000004 ++/* No-Operation ++#define I2C_ICR_LBREQ_INT_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_ICR_LBREQ_INT_CLR 0x00000004 ++/** SREQ_INT */ ++#define I2C_ICR_SREQ_INT 0x00000002 ++/* No-Operation ++#define I2C_ICR_SREQ_INT_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_ICR_SREQ_INT_CLR 0x00000002 ++/** LSREQ_INT */ ++#define I2C_ICR_LSREQ_INT 0x00000001 ++/* No-Operation ++#define I2C_ICR_LSREQ_INT_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_ICR_LSREQ_INT_CLR 0x00000001 ++ ++/* Fields of "I2C Interrupt Set Register" */ ++/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */ ++#define I2C_ISR_I2C_P_INT 0x00000020 ++/* No-Operation ++#define I2C_ISR_I2C_P_INT_NOP 0x00000000 */ ++/** Set */ ++#define I2C_ISR_I2C_P_INT_SET 0x00000020 ++/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */ ++#define I2C_ISR_I2C_ERR_INT 0x00000010 ++/* No-Operation ++#define I2C_ISR_I2C_ERR_INT_NOP 0x00000000 */ ++/** Set */ ++#define I2C_ISR_I2C_ERR_INT_SET 0x00000010 ++/** BREQ_INT */ ++#define I2C_ISR_BREQ_INT 0x00000008 ++/* No-Operation ++#define I2C_ISR_BREQ_INT_NOP 0x00000000 */ ++/** Set */ ++#define I2C_ISR_BREQ_INT_SET 0x00000008 ++/** LBREQ_INT */ ++#define I2C_ISR_LBREQ_INT 0x00000004 ++/* No-Operation ++#define I2C_ISR_LBREQ_INT_NOP 0x00000000 */ ++/** Set */ ++#define I2C_ISR_LBREQ_INT_SET 0x00000004 ++/** SREQ_INT */ ++#define I2C_ISR_SREQ_INT 0x00000002 ++/* No-Operation ++#define I2C_ISR_SREQ_INT_NOP 0x00000000 */ ++/** Set */ ++#define I2C_ISR_SREQ_INT_SET 0x00000002 ++/** LSREQ_INT */ ++#define I2C_ISR_LSREQ_INT 0x00000001 ++/* No-Operation ++#define I2C_ISR_LSREQ_INT_NOP 0x00000000 */ ++/** Set */ ++#define I2C_ISR_LSREQ_INT_SET 0x00000001 ++ ++/* Fields of "I2C DMA Enable Register" */ ++/** BREQ_INT */ ++#define I2C_DMAE_BREQ_INT 0x00000008 ++/* Disable ++#define I2C_DMAE_BREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_DMAE_BREQ_INT_EN 0x00000008 ++/** LBREQ_INT */ ++#define I2C_DMAE_LBREQ_INT 0x00000004 ++/* Disable ++#define I2C_DMAE_LBREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_DMAE_LBREQ_INT_EN 0x00000004 ++/** SREQ_INT */ ++#define I2C_DMAE_SREQ_INT 0x00000002 ++/* Disable ++#define I2C_DMAE_SREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_DMAE_SREQ_INT_EN 0x00000002 ++/** LSREQ_INT */ ++#define I2C_DMAE_LSREQ_INT 0x00000001 ++/* Disable ++#define I2C_DMAE_LSREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_DMAE_LSREQ_INT_EN 0x00000001 ++ ++/* Fields of "I2C Transmit Data Register" */ ++/** Characters to be transmitted */ ++#define I2C_TXD_TXD_MASK 0xFFFFFFFF ++/** field offset */ ++#define I2C_TXD_TXD_OFFSET 0 ++ ++/* Fields of "I2C Receive Data Register" */ ++/** Received characters */ ++#define I2C_RXD_RXD_MASK 0xFFFFFFFF ++/** field offset */ ++#define I2C_RXD_RXD_OFFSET 0 ++ ++/*! @} */ /* I2C_REGISTER */ ++ ++#endif /* _i2c_reg_h */ +diff --git a/arch/mips/include/asm/mach-lantiq/falcon/icu0_reg.h b/arch/mips/include/asm/mach-lantiq/falcon/icu0_reg.h +new file mode 100644 +index 0000000..d68c22e +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/icu0_reg.h +@@ -0,0 +1,4324 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++ ++#ifndef _icu0_reg_h ++#define _icu0_reg_h ++ ++/** \addtogroup ICU0_REGISTER ++ @{ ++*/ ++/* access macros */ ++#define icu0_r32(reg) reg_r32(&icu0->reg) ++#define icu0_w32(val, reg) reg_w32(val, &icu0->reg) ++#define icu0_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &icu0->reg) ++#define icu0_r32_table(reg, idx) reg_r32_table(icu0->reg, idx) ++#define icu0_w32_table(val, reg, idx) reg_w32_table(val, icu0->reg, idx) ++#define icu0_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, icu0->reg, idx) ++#define icu0_adr_table(reg, idx) adr_table(icu0->reg, idx) ++ ++ ++/** ICU0 register structure */ ++struct gpon_reg_icu0 ++{ ++ /** IM0 Interrupt Status Register ++ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */ ++ unsigned int im0_isr; /* 0x00000000 */ ++ /** Reserved */ ++ unsigned int res_0; /* 0x00000004 */ ++ /** IM0 Interrupt Enable Register ++ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM0_IOSR register and are not signalled via the interrupt line towards the controller. */ ++ unsigned int im0_ier; /* 0x00000008 */ ++ /** Reserved */ ++ unsigned int res_1; /* 0x0000000C */ ++ /** IM0 Interrupt Output Status Register ++ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM0_IER register. */ ++ unsigned int im0_iosr; /* 0x00000010 */ ++ /** Reserved */ ++ unsigned int res_2; /* 0x00000014 */ ++ /** IM0 Interrupt Request Set Register ++ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ ++ unsigned int im0_irsr; /* 0x00000018 */ ++ /** Reserved */ ++ unsigned int res_3; /* 0x0000001C */ ++ /** IM0 Interrupt Mode Register ++ This register shows the type of interrupt for each bit. */ ++ unsigned int im0_imr; /* 0x00000020 */ ++ /** Reserved */ ++ unsigned int res_4; /* 0x00000024 */ ++ /** IM1 Interrupt Status Register ++ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */ ++ unsigned int im1_isr; /* 0x00000028 */ ++ /** Reserved */ ++ unsigned int res_5; /* 0x0000002C */ ++ /** IM1 Interrupt Enable Register ++ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM1_IOSR register and are not signalled via the interrupt line towards the controller. */ ++ unsigned int im1_ier; /* 0x00000030 */ ++ /** Reserved */ ++ unsigned int res_6; /* 0x00000034 */ ++ /** IM1 Interrupt Output Status Register ++ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM1_IER register. */ ++ unsigned int im1_iosr; /* 0x00000038 */ ++ /** Reserved */ ++ unsigned int res_7; /* 0x0000003C */ ++ /** IM1 Interrupt Request Set Register ++ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ ++ unsigned int im1_irsr; /* 0x00000040 */ ++ /** Reserved */ ++ unsigned int res_8; /* 0x00000044 */ ++ /** IM1 Interrupt Mode Register ++ This register shows the type of interrupt for each bit. */ ++ unsigned int im1_imr; /* 0x00000048 */ ++ /** Reserved */ ++ unsigned int res_9; /* 0x0000004C */ ++ /** IM2 Interrupt Status Register ++ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */ ++ unsigned int im2_isr; /* 0x00000050 */ ++ /** Reserved */ ++ unsigned int res_10; /* 0x00000054 */ ++ /** IM2 Interrupt Enable Register ++ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM2_IOSR register and are not signalled via the interrupt line towards the controller. */ ++ unsigned int im2_ier; /* 0x00000058 */ ++ /** Reserved */ ++ unsigned int res_11; /* 0x0000005C */ ++ /** IM2 Interrupt Output Status Register ++ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM2_IER register. */ ++ unsigned int im2_iosr; /* 0x00000060 */ ++ /** Reserved */ ++ unsigned int res_12; /* 0x00000064 */ ++ /** IM2 Interrupt Request Set Register ++ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ ++ unsigned int im2_irsr; /* 0x00000068 */ ++ /** Reserved */ ++ unsigned int res_13; /* 0x0000006C */ ++ /** IM2 Interrupt Mode Register ++ This register shows the type of interrupt for each bit. */ ++ unsigned int im2_imr; /* 0x00000070 */ ++ /** Reserved */ ++ unsigned int res_14; /* 0x00000074 */ ++ /** IM3 Interrupt Status Register ++ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */ ++ unsigned int im3_isr; /* 0x00000078 */ ++ /** Reserved */ ++ unsigned int res_15; /* 0x0000007C */ ++ /** IM3 Interrupt Enable Register ++ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM3_IOSR register and are not signalled via the interrupt line towards the controller. */ ++ unsigned int im3_ier; /* 0x00000080 */ ++ /** Reserved */ ++ unsigned int res_16; /* 0x00000084 */ ++ /** IM3 Interrupt Output Status Register ++ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM3_IER register. */ ++ unsigned int im3_iosr; /* 0x00000088 */ ++ /** Reserved */ ++ unsigned int res_17; /* 0x0000008C */ ++ /** IM3 Interrupt Request Set Register ++ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ ++ unsigned int im3_irsr; /* 0x00000090 */ ++ /** Reserved */ ++ unsigned int res_18; /* 0x00000094 */ ++ /** IM3 Interrupt Mode Register ++ This register shows the type of interrupt for each bit. */ ++ unsigned int im3_imr; /* 0x00000098 */ ++ /** Reserved */ ++ unsigned int res_19; /* 0x0000009C */ ++ /** IM4 Interrupt Status Register ++ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */ ++ unsigned int im4_isr; /* 0x000000A0 */ ++ /** Reserved */ ++ unsigned int res_20; /* 0x000000A4 */ ++ /** IM4 Interrupt Enable Register ++ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM4_IOSR register and are not signalled via the interrupt line towards the controller. */ ++ unsigned int im4_ier; /* 0x000000A8 */ ++ /** Reserved */ ++ unsigned int res_21; /* 0x000000AC */ ++ /** IM4 Interrupt Output Status Register ++ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM4_IER register. */ ++ unsigned int im4_iosr; /* 0x000000B0 */ ++ /** Reserved */ ++ unsigned int res_22; /* 0x000000B4 */ ++ /** IM4 Interrupt Request Set Register ++ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ ++ unsigned int im4_irsr; /* 0x000000B8 */ ++ /** Reserved */ ++ unsigned int res_23; /* 0x000000BC */ ++ /** IM4 Interrupt Mode Register ++ This register shows the type of interrupt for each bit. */ ++ unsigned int im4_imr; /* 0x000000C0 */ ++ /** Reserved */ ++ unsigned int res_24; /* 0x000000C4 */ ++ /** ICU Interrupt Vector Register (5 bit variant) ++ Shows the leftmost pending interrupt request. If e.g. bit 14 of the IOSR register is set, 15 is reported, because the 15th interrupt request is active. */ ++ unsigned int icu_ivec; /* 0x000000C8 */ ++ /** Reserved */ ++ unsigned int res_25; /* 0x000000CC */ ++ /** ICU Interrupt Vector Register (6 bit variant) ++ Shows the leftmost pending interrupt request. If e.g. bit 14 of the IOSR register is set, 15 is reported, because the 15th interrupt request is active. */ ++ unsigned int icu_ivec_6; /* 0x000000D0 */ ++ /** Reserved */ ++ unsigned int res_26[3]; /* 0x000000D4 */ ++}; ++ ++ ++/* Fields of "IM0 Interrupt Status Register" */ ++/** PCM Transmit Crash Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_PCM_HW2_CRASH 0x80000000 ++/* Nothing ++#define ICU0_IM0_ISR_PCM_HW2_CRASH_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_PCM_HW2_CRASH_INTACK 0x80000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_PCM_HW2_CRASH_INTOCC 0x80000000 ++/** PCM Transmit Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_PCM_TX 0x40000000 ++/* Nothing ++#define ICU0_IM0_ISR_PCM_TX_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_PCM_TX_INTACK 0x40000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_PCM_TX_INTOCC 0x40000000 ++/** PCM Receive Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_PCM_RX 0x20000000 ++/* Nothing ++#define ICU0_IM0_ISR_PCM_RX_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_PCM_RX_INTACK 0x20000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_PCM_RX_INTOCC 0x20000000 ++/** Secure Hash Algorithm Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM0_ISR_SHA1_HASH 0x10000000 ++/* Nothing ++#define ICU0_IM0_ISR_SHA1_HASH_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_SHA1_HASH_INTACK 0x10000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_SHA1_HASH_INTOCC 0x10000000 ++/** Advanced Encryption Standard Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM0_ISR_AES_AES 0x08000000 ++/* Nothing ++#define ICU0_IM0_ISR_AES_AES_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_AES_AES_INTACK 0x08000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_AES_AES_INTOCC 0x08000000 ++/** SSC Frame Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM0_ISR_SSC0_F 0x00020000 ++/* Nothing ++#define ICU0_IM0_ISR_SSC0_F_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_SSC0_F_INTACK 0x00020000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_SSC0_F_INTOCC 0x00020000 ++/** SSC Error Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM0_ISR_SSC0_E 0x00010000 ++/* Nothing ++#define ICU0_IM0_ISR_SSC0_E_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_SSC0_E_INTACK 0x00010000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_SSC0_E_INTOCC 0x00010000 ++/** SSC Receive Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM0_ISR_SSC0_R 0x00008000 ++/* Nothing ++#define ICU0_IM0_ISR_SSC0_R_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_SSC0_R_INTACK 0x00008000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_SSC0_R_INTOCC 0x00008000 ++/** SSC Transmit Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM0_ISR_SSC0_T 0x00004000 ++/* Nothing ++#define ICU0_IM0_ISR_SSC0_T_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_SSC0_T_INTACK 0x00004000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_SSC0_T_INTOCC 0x00004000 ++/** I2C Peripheral Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_I2C_I2C_P_INT 0x00002000 ++/* Nothing ++#define ICU0_IM0_ISR_I2C_I2C_P_INT_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_I2C_I2C_P_INT_INTACK 0x00002000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_I2C_I2C_P_INT_INTOCC 0x00002000 ++/** I2C Error Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_I2C_I2C_ERR_INT 0x00001000 ++/* Nothing ++#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_INTACK 0x00001000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_INTOCC 0x00001000 ++/** I2C Burst Data Transfer Request ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_I2C_BREQ_INT 0x00000800 ++/* Nothing ++#define ICU0_IM0_ISR_I2C_BREQ_INT_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_I2C_BREQ_INT_INTACK 0x00000800 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_I2C_BREQ_INT_INTOCC 0x00000800 ++/** I2C Last Burst Data Transfer Request ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_I2C_LBREQ_INT 0x00000400 ++/* Nothing ++#define ICU0_IM0_ISR_I2C_LBREQ_INT_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_I2C_LBREQ_INT_INTACK 0x00000400 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_I2C_LBREQ_INT_INTOCC 0x00000400 ++/** I2C Single Data Transfer Request ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_I2C_SREQ_INT 0x00000200 ++/* Nothing ++#define ICU0_IM0_ISR_I2C_SREQ_INT_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_I2C_SREQ_INT_INTACK 0x00000200 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_I2C_SREQ_INT_INTOCC 0x00000200 ++/** I2C Last Single Data Transfer Request ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_I2C_LSREQ_INT 0x00000100 ++/* Nothing ++#define ICU0_IM0_ISR_I2C_LSREQ_INT_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_I2C_LSREQ_INT_INTACK 0x00000100 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_I2C_LSREQ_INT_INTOCC 0x00000100 ++/** HOST IF Mailbox1 Transmit Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_HOST_MB1_TIR 0x00000010 ++/* Nothing ++#define ICU0_IM0_ISR_HOST_MB1_TIR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_HOST_MB1_TIR_INTACK 0x00000010 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_HOST_MB1_TIR_INTOCC 0x00000010 ++/** HOST IF Mailbox1 Receive Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_HOST_MB1_RIR 0x00000008 ++/* Nothing ++#define ICU0_IM0_ISR_HOST_MB1_RIR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_HOST_MB1_RIR_INTACK 0x00000008 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_HOST_MB1_RIR_INTOCC 0x00000008 ++/** HOST IF Mailbox0 Transmit Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_HOST_MB0_TIR 0x00000004 ++/* Nothing ++#define ICU0_IM0_ISR_HOST_MB0_TIR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_HOST_MB0_TIR_INTACK 0x00000004 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_HOST_MB0_TIR_INTOCC 0x00000004 ++/** HOST IF Mailbox0 Receive Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_HOST_MB0_RIR 0x00000002 ++/* Nothing ++#define ICU0_IM0_ISR_HOST_MB0_RIR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_HOST_MB0_RIR_INTACK 0x00000002 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_HOST_MB0_RIR_INTOCC 0x00000002 ++/** HOST IF Event Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_HOST_EIR 0x00000001 ++/* Nothing ++#define ICU0_IM0_ISR_HOST_EIR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_HOST_EIR_INTACK 0x00000001 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_HOST_EIR_INTOCC 0x00000001 ++ ++/* Fields of "IM0 Interrupt Enable Register" */ ++/** PCM Transmit Crash Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_PCM_HW2_CRASH 0x80000000 ++/* Disable ++#define ICU0_IM0_IER_PCM_HW2_CRASH_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_PCM_HW2_CRASH_EN 0x80000000 ++/** PCM Transmit Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_PCM_TX 0x40000000 ++/* Disable ++#define ICU0_IM0_IER_PCM_TX_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_PCM_TX_EN 0x40000000 ++/** PCM Receive Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_PCM_RX 0x20000000 ++/* Disable ++#define ICU0_IM0_IER_PCM_RX_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_PCM_RX_EN 0x20000000 ++/** Secure Hash Algorithm Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_SHA1_HASH 0x10000000 ++/* Disable ++#define ICU0_IM0_IER_SHA1_HASH_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_SHA1_HASH_EN 0x10000000 ++/** Advanced Encryption Standard Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_AES_AES 0x08000000 ++/* Disable ++#define ICU0_IM0_IER_AES_AES_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_AES_AES_EN 0x08000000 ++/** SSC Frame Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_SSC0_F 0x00020000 ++/* Disable ++#define ICU0_IM0_IER_SSC0_F_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_SSC0_F_EN 0x00020000 ++/** SSC Error Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_SSC0_E 0x00010000 ++/* Disable ++#define ICU0_IM0_IER_SSC0_E_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_SSC0_E_EN 0x00010000 ++/** SSC Receive Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_SSC0_R 0x00008000 ++/* Disable ++#define ICU0_IM0_IER_SSC0_R_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_SSC0_R_EN 0x00008000 ++/** SSC Transmit Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_SSC0_T 0x00004000 ++/* Disable ++#define ICU0_IM0_IER_SSC0_T_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_SSC0_T_EN 0x00004000 ++/** I2C Peripheral Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_I2C_I2C_P_INT 0x00002000 ++/* Disable ++#define ICU0_IM0_IER_I2C_I2C_P_INT_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_I2C_I2C_P_INT_EN 0x00002000 ++/** I2C Error Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_I2C_I2C_ERR_INT 0x00001000 ++/* Disable ++#define ICU0_IM0_IER_I2C_I2C_ERR_INT_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_I2C_I2C_ERR_INT_EN 0x00001000 ++/** I2C Burst Data Transfer Request ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_I2C_BREQ_INT 0x00000800 ++/* Disable ++#define ICU0_IM0_IER_I2C_BREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_I2C_BREQ_INT_EN 0x00000800 ++/** I2C Last Burst Data Transfer Request ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_I2C_LBREQ_INT 0x00000400 ++/* Disable ++#define ICU0_IM0_IER_I2C_LBREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_I2C_LBREQ_INT_EN 0x00000400 ++/** I2C Single Data Transfer Request ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_I2C_SREQ_INT 0x00000200 ++/* Disable ++#define ICU0_IM0_IER_I2C_SREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_I2C_SREQ_INT_EN 0x00000200 ++/** I2C Last Single Data Transfer Request ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_I2C_LSREQ_INT 0x00000100 ++/* Disable ++#define ICU0_IM0_IER_I2C_LSREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_I2C_LSREQ_INT_EN 0x00000100 ++/** HOST IF Mailbox1 Transmit Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_HOST_MB1_TIR 0x00000010 ++/* Disable ++#define ICU0_IM0_IER_HOST_MB1_TIR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_HOST_MB1_TIR_EN 0x00000010 ++/** HOST IF Mailbox1 Receive Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_HOST_MB1_RIR 0x00000008 ++/* Disable ++#define ICU0_IM0_IER_HOST_MB1_RIR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_HOST_MB1_RIR_EN 0x00000008 ++/** HOST IF Mailbox0 Transmit Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_HOST_MB0_TIR 0x00000004 ++/* Disable ++#define ICU0_IM0_IER_HOST_MB0_TIR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_HOST_MB0_TIR_EN 0x00000004 ++/** HOST IF Mailbox0 Receive Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_HOST_MB0_RIR 0x00000002 ++/* Disable ++#define ICU0_IM0_IER_HOST_MB0_RIR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_HOST_MB0_RIR_EN 0x00000002 ++/** HOST IF Event Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_HOST_EIR 0x00000001 ++/* Disable ++#define ICU0_IM0_IER_HOST_EIR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_HOST_EIR_EN 0x00000001 ++ ++/* Fields of "IM0 Interrupt Output Status Register" */ ++/** PCM Transmit Crash Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_PCM_HW2_CRASH 0x80000000 ++/* Nothing ++#define ICU0_IM0_IOSR_PCM_HW2_CRASH_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_PCM_HW2_CRASH_INTOCC 0x80000000 ++/** PCM Transmit Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_PCM_TX 0x40000000 ++/* Nothing ++#define ICU0_IM0_IOSR_PCM_TX_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_PCM_TX_INTOCC 0x40000000 ++/** PCM Receive Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_PCM_RX 0x20000000 ++/* Nothing ++#define ICU0_IM0_IOSR_PCM_RX_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_PCM_RX_INTOCC 0x20000000 ++/** Secure Hash Algorithm Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_SHA1_HASH 0x10000000 ++/* Nothing ++#define ICU0_IM0_IOSR_SHA1_HASH_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_SHA1_HASH_INTOCC 0x10000000 ++/** Advanced Encryption Standard Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_AES_AES 0x08000000 ++/* Nothing ++#define ICU0_IM0_IOSR_AES_AES_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_AES_AES_INTOCC 0x08000000 ++/** SSC Frame Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_SSC0_F 0x00020000 ++/* Nothing ++#define ICU0_IM0_IOSR_SSC0_F_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_SSC0_F_INTOCC 0x00020000 ++/** SSC Error Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_SSC0_E 0x00010000 ++/* Nothing ++#define ICU0_IM0_IOSR_SSC0_E_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_SSC0_E_INTOCC 0x00010000 ++/** SSC Receive Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_SSC0_R 0x00008000 ++/* Nothing ++#define ICU0_IM0_IOSR_SSC0_R_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_SSC0_R_INTOCC 0x00008000 ++/** SSC Transmit Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_SSC0_T 0x00004000 ++/* Nothing ++#define ICU0_IM0_IOSR_SSC0_T_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_SSC0_T_INTOCC 0x00004000 ++/** I2C Peripheral Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_I2C_I2C_P_INT 0x00002000 ++/* Nothing ++#define ICU0_IM0_IOSR_I2C_I2C_P_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_I2C_I2C_P_INT_INTOCC 0x00002000 ++/** I2C Error Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT 0x00001000 ++/* Nothing ++#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT_INTOCC 0x00001000 ++/** I2C Burst Data Transfer Request ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_I2C_BREQ_INT 0x00000800 ++/* Nothing ++#define ICU0_IM0_IOSR_I2C_BREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_I2C_BREQ_INT_INTOCC 0x00000800 ++/** I2C Last Burst Data Transfer Request ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_I2C_LBREQ_INT 0x00000400 ++/* Nothing ++#define ICU0_IM0_IOSR_I2C_LBREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_I2C_LBREQ_INT_INTOCC 0x00000400 ++/** I2C Single Data Transfer Request ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_I2C_SREQ_INT 0x00000200 ++/* Nothing ++#define ICU0_IM0_IOSR_I2C_SREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_I2C_SREQ_INT_INTOCC 0x00000200 ++/** I2C Last Single Data Transfer Request ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_I2C_LSREQ_INT 0x00000100 ++/* Nothing ++#define ICU0_IM0_IOSR_I2C_LSREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_I2C_LSREQ_INT_INTOCC 0x00000100 ++/** HOST IF Mailbox1 Transmit Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_HOST_MB1_TIR 0x00000010 ++/* Nothing ++#define ICU0_IM0_IOSR_HOST_MB1_TIR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_HOST_MB1_TIR_INTOCC 0x00000010 ++/** HOST IF Mailbox1 Receive Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_HOST_MB1_RIR 0x00000008 ++/* Nothing ++#define ICU0_IM0_IOSR_HOST_MB1_RIR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_HOST_MB1_RIR_INTOCC 0x00000008 ++/** HOST IF Mailbox0 Transmit Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_HOST_MB0_TIR 0x00000004 ++/* Nothing ++#define ICU0_IM0_IOSR_HOST_MB0_TIR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_HOST_MB0_TIR_INTOCC 0x00000004 ++/** HOST IF Mailbox0 Receive Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_HOST_MB0_RIR 0x00000002 ++/* Nothing ++#define ICU0_IM0_IOSR_HOST_MB0_RIR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_HOST_MB0_RIR_INTOCC 0x00000002 ++/** HOST IF Event Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_HOST_EIR 0x00000001 ++/* Nothing ++#define ICU0_IM0_IOSR_HOST_EIR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_HOST_EIR_INTOCC 0x00000001 ++ ++/* Fields of "IM0 Interrupt Request Set Register" */ ++/** PCM Transmit Crash Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_PCM_HW2_CRASH 0x80000000 ++/** PCM Transmit Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_PCM_TX 0x40000000 ++/** PCM Receive Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_PCM_RX 0x20000000 ++/** Secure Hash Algorithm Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_SHA1_HASH 0x10000000 ++/** Advanced Encryption Standard Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_AES_AES 0x08000000 ++/** SSC Frame Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_SSC0_F 0x00020000 ++/** SSC Error Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_SSC0_E 0x00010000 ++/** SSC Receive Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_SSC0_R 0x00008000 ++/** SSC Transmit Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_SSC0_T 0x00004000 ++/** I2C Peripheral Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_I2C_I2C_P_INT 0x00002000 ++/** I2C Error Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_I2C_I2C_ERR_INT 0x00001000 ++/** I2C Burst Data Transfer Request ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_I2C_BREQ_INT 0x00000800 ++/** I2C Last Burst Data Transfer Request ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_I2C_LBREQ_INT 0x00000400 ++/** I2C Single Data Transfer Request ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_I2C_SREQ_INT 0x00000200 ++/** I2C Last Single Data Transfer Request ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_I2C_LSREQ_INT 0x00000100 ++/** HOST IF Mailbox1 Transmit Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_HOST_MB1_TIR 0x00000010 ++/** HOST IF Mailbox1 Receive Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_HOST_MB1_RIR 0x00000008 ++/** HOST IF Mailbox0 Transmit Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_HOST_MB0_TIR 0x00000004 ++/** HOST IF Mailbox0 Receive Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_HOST_MB0_RIR 0x00000002 ++/** HOST IF Event Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_HOST_EIR 0x00000001 ++ ++/* Fields of "IM0 Interrupt Mode Register" */ ++/** PCM Transmit Crash Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_PCM_HW2_CRASH 0x80000000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_PCM_HW2_CRASH_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_PCM_HW2_CRASH_DIR 0x80000000 ++/** PCM Transmit Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_PCM_TX 0x40000000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_PCM_TX_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_PCM_TX_DIR 0x40000000 ++/** PCM Receive Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_PCM_RX 0x20000000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_PCM_RX_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_PCM_RX_DIR 0x20000000 ++/** Secure Hash Algorithm Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_SHA1_HASH 0x10000000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_SHA1_HASH_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_SHA1_HASH_DIR 0x10000000 ++/** Advanced Encryption Standard Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_AES_AES 0x08000000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_AES_AES_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_AES_AES_DIR 0x08000000 ++/** SSC Frame Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_SSC0_F 0x00020000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_SSC0_F_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_SSC0_F_DIR 0x00020000 ++/** SSC Error Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_SSC0_E 0x00010000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_SSC0_E_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_SSC0_E_DIR 0x00010000 ++/** SSC Receive Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_SSC0_R 0x00008000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_SSC0_R_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_SSC0_R_DIR 0x00008000 ++/** SSC Transmit Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_SSC0_T 0x00004000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_SSC0_T_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_SSC0_T_DIR 0x00004000 ++/** I2C Peripheral Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_I2C_I2C_P_INT 0x00002000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_I2C_I2C_P_INT_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_I2C_I2C_P_INT_DIR 0x00002000 ++/** I2C Error Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_I2C_I2C_ERR_INT 0x00001000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_I2C_I2C_ERR_INT_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_I2C_I2C_ERR_INT_DIR 0x00001000 ++/** I2C Burst Data Transfer Request ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_I2C_BREQ_INT 0x00000800 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_I2C_BREQ_INT_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_I2C_BREQ_INT_DIR 0x00000800 ++/** I2C Last Burst Data Transfer Request ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_I2C_LBREQ_INT 0x00000400 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_I2C_LBREQ_INT_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_I2C_LBREQ_INT_DIR 0x00000400 ++/** I2C Single Data Transfer Request ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_I2C_SREQ_INT 0x00000200 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_I2C_SREQ_INT_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_I2C_SREQ_INT_DIR 0x00000200 ++/** I2C Last Single Data Transfer Request ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_I2C_LSREQ_INT 0x00000100 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_I2C_LSREQ_INT_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_I2C_LSREQ_INT_DIR 0x00000100 ++/** HOST IF Mailbox1 Transmit Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_HOST_MB1_TIR 0x00000010 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_HOST_MB1_TIR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_HOST_MB1_TIR_DIR 0x00000010 ++/** HOST IF Mailbox1 Receive Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_HOST_MB1_RIR 0x00000008 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_HOST_MB1_RIR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_HOST_MB1_RIR_DIR 0x00000008 ++/** HOST IF Mailbox0 Transmit Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_HOST_MB0_TIR 0x00000004 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_HOST_MB0_TIR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_HOST_MB0_TIR_DIR 0x00000004 ++/** HOST IF Mailbox0 Receive Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_HOST_MB0_RIR 0x00000002 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_HOST_MB0_RIR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_HOST_MB0_RIR_DIR 0x00000002 ++/** HOST IF Event Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_HOST_EIR 0x00000001 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_HOST_EIR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_HOST_EIR_DIR 0x00000001 ++ ++/* Fields of "IM1 Interrupt Status Register" */ ++/** Crossbar Error Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_XBAR_ERROR 0x80000000 ++/* Nothing ++#define ICU0_IM1_ISR_XBAR_ERROR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_XBAR_ERROR_INTACK 0x80000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_XBAR_ERROR_INTOCC 0x80000000 ++/** DDR Controller Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_DDR 0x40000000 ++/* Nothing ++#define ICU0_IM1_ISR_DDR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_DDR_INTACK 0x40000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_DDR_INTOCC 0x40000000 ++/** FPI Bus Control Unit Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM1_ISR_BCU0 0x20000000 ++/* Nothing ++#define ICU0_IM1_ISR_BCU0_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_BCU0_INTACK 0x20000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_BCU0_INTOCC 0x20000000 ++/** SBIU interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_SBIU0 0x08000000 ++/* Nothing ++#define ICU0_IM1_ISR_SBIU0_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_SBIU0_INTACK 0x08000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_SBIU0_INTOCC 0x08000000 ++/** Watchdog Prewarning Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_WDT_PIR 0x02000000 ++/* Nothing ++#define ICU0_IM1_ISR_WDT_PIR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_WDT_PIR_INTACK 0x02000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_WDT_PIR_INTOCC 0x02000000 ++/** Watchdog Access Error Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_WDT_AEIR 0x01000000 ++/* Nothing ++#define ICU0_IM1_ISR_WDT_AEIR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_WDT_AEIR_INTACK 0x01000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_WDT_AEIR_INTOCC 0x01000000 ++/** SYS GPE Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_SYS_GPE 0x00200000 ++/* Nothing ++#define ICU0_IM1_ISR_SYS_GPE_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_SYS_GPE_INTACK 0x00200000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_SYS_GPE_INTOCC 0x00200000 ++/** SYS1 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_SYS1 0x00100000 ++/* Nothing ++#define ICU0_IM1_ISR_SYS1_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_SYS1_INTACK 0x00100000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_SYS1_INTOCC 0x00100000 ++/** PMA Interrupt from IntNode of the RX Clk Domain ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_PMA_RX 0x00020000 ++/* Nothing ++#define ICU0_IM1_ISR_PMA_RX_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_PMA_RX_INTACK 0x00020000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_PMA_RX_INTOCC 0x00020000 ++/** PMA Interrupt from IntNode of the TX Clk Domain ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_PMA_TX 0x00010000 ++/* Nothing ++#define ICU0_IM1_ISR_PMA_TX_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_PMA_TX_INTACK 0x00010000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_PMA_TX_INTOCC 0x00010000 ++/** PMA Interrupt from IntNode of the 200MHz Domain ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_PMA_200M 0x00008000 ++/* Nothing ++#define ICU0_IM1_ISR_PMA_200M_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_PMA_200M_INTACK 0x00008000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_PMA_200M_INTOCC 0x00008000 ++/** Time of Day ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_TOD 0x00004000 ++/* Nothing ++#define ICU0_IM1_ISR_TOD_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_TOD_INTACK 0x00004000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_TOD_INTOCC 0x00004000 ++/** 8kHz root interrupt derived from GPON interface ++ This bit is a direct interrupt. */ ++#define ICU0_IM1_ISR_FSC_ROOT 0x00002000 ++/* Nothing ++#define ICU0_IM1_ISR_FSC_ROOT_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_FSC_ROOT_INTACK 0x00002000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_FSC_ROOT_INTOCC 0x00002000 ++/** FSC Timer Interrupt 1 ++ Delayed version of FSCROOT. This bit is a direct interrupt. */ ++#define ICU0_IM1_ISR_FSCT_CMP1 0x00001000 ++/* Nothing ++#define ICU0_IM1_ISR_FSCT_CMP1_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_FSCT_CMP1_INTACK 0x00001000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_FSCT_CMP1_INTOCC 0x00001000 ++/** FSC Timer Interrupt 0 ++ Delayed version of FSCROOT. This bit is a direct interrupt. */ ++#define ICU0_IM1_ISR_FSCT_CMP0 0x00000800 ++/* Nothing ++#define ICU0_IM1_ISR_FSCT_CMP0_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_FSCT_CMP0_INTACK 0x00000800 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_FSCT_CMP0_INTOCC 0x00000800 ++/** 8kHz backup interrupt derived from core-PLL ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_FSC_BKP 0x00000400 ++/* Nothing ++#define ICU0_IM1_ISR_FSC_BKP_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_FSC_BKP_INTACK 0x00000400 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_FSC_BKP_INTOCC 0x00000400 ++/** External Interrupt from GPIO P4 ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_P4 0x00000100 ++/* Nothing ++#define ICU0_IM1_ISR_P4_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_P4_INTACK 0x00000100 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_P4_INTOCC 0x00000100 ++/** External Interrupt from GPIO P3 ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_P3 0x00000080 ++/* Nothing ++#define ICU0_IM1_ISR_P3_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_P3_INTACK 0x00000080 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_P3_INTOCC 0x00000080 ++/** External Interrupt from GPIO P2 ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_P2 0x00000040 ++/* Nothing ++#define ICU0_IM1_ISR_P2_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_P2_INTACK 0x00000040 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_P2_INTOCC 0x00000040 ++/** External Interrupt from GPIO P1 ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_P1 0x00000020 ++/* Nothing ++#define ICU0_IM1_ISR_P1_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_P1_INTACK 0x00000020 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_P1_INTOCC 0x00000020 ++/** External Interrupt from GPIO P0 ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_P0 0x00000010 ++/* Nothing ++#define ICU0_IM1_ISR_P0_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_P0_INTACK 0x00000010 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_P0_INTOCC 0x00000010 ++/** EBU Serial Flash Busy ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_EBU_SF_BUSY 0x00000004 ++/* Nothing ++#define ICU0_IM1_ISR_EBU_SF_BUSY_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_EBU_SF_BUSY_INTACK 0x00000004 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_EBU_SF_BUSY_INTOCC 0x00000004 ++/** EBU Serial Flash Command Overwrite Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_EBU_SF_COVERR 0x00000002 ++/* Nothing ++#define ICU0_IM1_ISR_EBU_SF_COVERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_EBU_SF_COVERR_INTACK 0x00000002 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_EBU_SF_COVERR_INTOCC 0x00000002 ++/** EBU Serial Flash Command Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_EBU_SF_CMDERR 0x00000001 ++/* Nothing ++#define ICU0_IM1_ISR_EBU_SF_CMDERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_EBU_SF_CMDERR_INTACK 0x00000001 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_EBU_SF_CMDERR_INTOCC 0x00000001 ++ ++/* Fields of "IM1 Interrupt Enable Register" */ ++/** Crossbar Error Interrupt ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_XBAR_ERROR 0x80000000 ++/* Disable ++#define ICU0_IM1_IER_XBAR_ERROR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_XBAR_ERROR_EN 0x80000000 ++/** DDR Controller Interrupt ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_DDR 0x40000000 ++/* Disable ++#define ICU0_IM1_IER_DDR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_DDR_EN 0x40000000 ++/** FPI Bus Control Unit Interrupt ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_BCU0 0x20000000 ++/* Disable ++#define ICU0_IM1_IER_BCU0_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_BCU0_EN 0x20000000 ++/** SBIU interrupt ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_SBIU0 0x08000000 ++/* Disable ++#define ICU0_IM1_IER_SBIU0_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_SBIU0_EN 0x08000000 ++/** Watchdog Prewarning Interrupt ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_WDT_PIR 0x02000000 ++/* Disable ++#define ICU0_IM1_IER_WDT_PIR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_WDT_PIR_EN 0x02000000 ++/** Watchdog Access Error Interrupt ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_WDT_AEIR 0x01000000 ++/* Disable ++#define ICU0_IM1_IER_WDT_AEIR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_WDT_AEIR_EN 0x01000000 ++/** SYS GPE Interrupt ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_SYS_GPE 0x00200000 ++/* Disable ++#define ICU0_IM1_IER_SYS_GPE_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_SYS_GPE_EN 0x00200000 ++/** SYS1 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_SYS1 0x00100000 ++/* Disable ++#define ICU0_IM1_IER_SYS1_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_SYS1_EN 0x00100000 ++/** PMA Interrupt from IntNode of the RX Clk Domain ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_PMA_RX 0x00020000 ++/* Disable ++#define ICU0_IM1_IER_PMA_RX_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_PMA_RX_EN 0x00020000 ++/** PMA Interrupt from IntNode of the TX Clk Domain ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_PMA_TX 0x00010000 ++/* Disable ++#define ICU0_IM1_IER_PMA_TX_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_PMA_TX_EN 0x00010000 ++/** PMA Interrupt from IntNode of the 200MHz Domain ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_PMA_200M 0x00008000 ++/* Disable ++#define ICU0_IM1_IER_PMA_200M_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_PMA_200M_EN 0x00008000 ++/** Time of Day ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_TOD 0x00004000 ++/* Disable ++#define ICU0_IM1_IER_TOD_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_TOD_EN 0x00004000 ++/** 8kHz root interrupt derived from GPON interface ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_FSC_ROOT 0x00002000 ++/* Disable ++#define ICU0_IM1_IER_FSC_ROOT_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_FSC_ROOT_EN 0x00002000 ++/** FSC Timer Interrupt 1 ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_FSCT_CMP1 0x00001000 ++/* Disable ++#define ICU0_IM1_IER_FSCT_CMP1_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_FSCT_CMP1_EN 0x00001000 ++/** FSC Timer Interrupt 0 ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_FSCT_CMP0 0x00000800 ++/* Disable ++#define ICU0_IM1_IER_FSCT_CMP0_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_FSCT_CMP0_EN 0x00000800 ++/** 8kHz backup interrupt derived from core-PLL ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_FSC_BKP 0x00000400 ++/* Disable ++#define ICU0_IM1_IER_FSC_BKP_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_FSC_BKP_EN 0x00000400 ++/** External Interrupt from GPIO P4 ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_P4 0x00000100 ++/* Disable ++#define ICU0_IM1_IER_P4_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_P4_EN 0x00000100 ++/** External Interrupt from GPIO P3 ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_P3 0x00000080 ++/* Disable ++#define ICU0_IM1_IER_P3_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_P3_EN 0x00000080 ++/** External Interrupt from GPIO P2 ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_P2 0x00000040 ++/* Disable ++#define ICU0_IM1_IER_P2_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_P2_EN 0x00000040 ++/** External Interrupt from GPIO P1 ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_P1 0x00000020 ++/* Disable ++#define ICU0_IM1_IER_P1_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_P1_EN 0x00000020 ++/** External Interrupt from GPIO P0 ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_P0 0x00000010 ++/* Disable ++#define ICU0_IM1_IER_P0_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_P0_EN 0x00000010 ++/** EBU Serial Flash Busy ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_EBU_SF_BUSY 0x00000004 ++/* Disable ++#define ICU0_IM1_IER_EBU_SF_BUSY_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_EBU_SF_BUSY_EN 0x00000004 ++/** EBU Serial Flash Command Overwrite Error ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_EBU_SF_COVERR 0x00000002 ++/* Disable ++#define ICU0_IM1_IER_EBU_SF_COVERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_EBU_SF_COVERR_EN 0x00000002 ++/** EBU Serial Flash Command Error ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_EBU_SF_CMDERR 0x00000001 ++/* Disable ++#define ICU0_IM1_IER_EBU_SF_CMDERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_EBU_SF_CMDERR_EN 0x00000001 ++ ++/* Fields of "IM1 Interrupt Output Status Register" */ ++/** Crossbar Error Interrupt ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_XBAR_ERROR 0x80000000 ++/* Nothing ++#define ICU0_IM1_IOSR_XBAR_ERROR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_XBAR_ERROR_INTOCC 0x80000000 ++/** DDR Controller Interrupt ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_DDR 0x40000000 ++/* Nothing ++#define ICU0_IM1_IOSR_DDR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_DDR_INTOCC 0x40000000 ++/** FPI Bus Control Unit Interrupt ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_BCU0 0x20000000 ++/* Nothing ++#define ICU0_IM1_IOSR_BCU0_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_BCU0_INTOCC 0x20000000 ++/** SBIU interrupt ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_SBIU0 0x08000000 ++/* Nothing ++#define ICU0_IM1_IOSR_SBIU0_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_SBIU0_INTOCC 0x08000000 ++/** Watchdog Prewarning Interrupt ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_WDT_PIR 0x02000000 ++/* Nothing ++#define ICU0_IM1_IOSR_WDT_PIR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_WDT_PIR_INTOCC 0x02000000 ++/** Watchdog Access Error Interrupt ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_WDT_AEIR 0x01000000 ++/* Nothing ++#define ICU0_IM1_IOSR_WDT_AEIR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_WDT_AEIR_INTOCC 0x01000000 ++/** SYS GPE Interrupt ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_SYS_GPE 0x00200000 ++/* Nothing ++#define ICU0_IM1_IOSR_SYS_GPE_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_SYS_GPE_INTOCC 0x00200000 ++/** SYS1 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_SYS1 0x00100000 ++/* Nothing ++#define ICU0_IM1_IOSR_SYS1_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_SYS1_INTOCC 0x00100000 ++/** PMA Interrupt from IntNode of the RX Clk Domain ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_PMA_RX 0x00020000 ++/* Nothing ++#define ICU0_IM1_IOSR_PMA_RX_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_PMA_RX_INTOCC 0x00020000 ++/** PMA Interrupt from IntNode of the TX Clk Domain ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_PMA_TX 0x00010000 ++/* Nothing ++#define ICU0_IM1_IOSR_PMA_TX_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_PMA_TX_INTOCC 0x00010000 ++/** PMA Interrupt from IntNode of the 200MHz Domain ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_PMA_200M 0x00008000 ++/* Nothing ++#define ICU0_IM1_IOSR_PMA_200M_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_PMA_200M_INTOCC 0x00008000 ++/** Time of Day ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_TOD 0x00004000 ++/* Nothing ++#define ICU0_IM1_IOSR_TOD_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_TOD_INTOCC 0x00004000 ++/** 8kHz root interrupt derived from GPON interface ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_FSC_ROOT 0x00002000 ++/* Nothing ++#define ICU0_IM1_IOSR_FSC_ROOT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_FSC_ROOT_INTOCC 0x00002000 ++/** FSC Timer Interrupt 1 ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_FSCT_CMP1 0x00001000 ++/* Nothing ++#define ICU0_IM1_IOSR_FSCT_CMP1_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_FSCT_CMP1_INTOCC 0x00001000 ++/** FSC Timer Interrupt 0 ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_FSCT_CMP0 0x00000800 ++/* Nothing ++#define ICU0_IM1_IOSR_FSCT_CMP0_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_FSCT_CMP0_INTOCC 0x00000800 ++/** 8kHz backup interrupt derived from core-PLL ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_FSC_BKP 0x00000400 ++/* Nothing ++#define ICU0_IM1_IOSR_FSC_BKP_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_FSC_BKP_INTOCC 0x00000400 ++/** External Interrupt from GPIO P4 ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_P4 0x00000100 ++/* Nothing ++#define ICU0_IM1_IOSR_P4_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_P4_INTOCC 0x00000100 ++/** External Interrupt from GPIO P3 ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_P3 0x00000080 ++/* Nothing ++#define ICU0_IM1_IOSR_P3_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_P3_INTOCC 0x00000080 ++/** External Interrupt from GPIO P2 ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_P2 0x00000040 ++/* Nothing ++#define ICU0_IM1_IOSR_P2_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_P2_INTOCC 0x00000040 ++/** External Interrupt from GPIO P1 ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_P1 0x00000020 ++/* Nothing ++#define ICU0_IM1_IOSR_P1_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_P1_INTOCC 0x00000020 ++/** External Interrupt from GPIO P0 ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_P0 0x00000010 ++/* Nothing ++#define ICU0_IM1_IOSR_P0_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_P0_INTOCC 0x00000010 ++/** EBU Serial Flash Busy ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_EBU_SF_BUSY 0x00000004 ++/* Nothing ++#define ICU0_IM1_IOSR_EBU_SF_BUSY_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_EBU_SF_BUSY_INTOCC 0x00000004 ++/** EBU Serial Flash Command Overwrite Error ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_EBU_SF_COVERR 0x00000002 ++/* Nothing ++#define ICU0_IM1_IOSR_EBU_SF_COVERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_EBU_SF_COVERR_INTOCC 0x00000002 ++/** EBU Serial Flash Command Error ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_EBU_SF_CMDERR 0x00000001 ++/* Nothing ++#define ICU0_IM1_IOSR_EBU_SF_CMDERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_EBU_SF_CMDERR_INTOCC 0x00000001 ++ ++/* Fields of "IM1 Interrupt Request Set Register" */ ++/** Crossbar Error Interrupt ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_XBAR_ERROR 0x80000000 ++/** DDR Controller Interrupt ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_DDR 0x40000000 ++/** FPI Bus Control Unit Interrupt ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_BCU0 0x20000000 ++/** SBIU interrupt ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_SBIU0 0x08000000 ++/** Watchdog Prewarning Interrupt ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_WDT_PIR 0x02000000 ++/** Watchdog Access Error Interrupt ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_WDT_AEIR 0x01000000 ++/** SYS GPE Interrupt ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_SYS_GPE 0x00200000 ++/** SYS1 Interrupt ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_SYS1 0x00100000 ++/** PMA Interrupt from IntNode of the RX Clk Domain ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_PMA_RX 0x00020000 ++/** PMA Interrupt from IntNode of the TX Clk Domain ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_PMA_TX 0x00010000 ++/** PMA Interrupt from IntNode of the 200MHz Domain ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_PMA_200M 0x00008000 ++/** Time of Day ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_TOD 0x00004000 ++/** 8kHz root interrupt derived from GPON interface ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_FSC_ROOT 0x00002000 ++/** FSC Timer Interrupt 1 ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_FSCT_CMP1 0x00001000 ++/** FSC Timer Interrupt 0 ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_FSCT_CMP0 0x00000800 ++/** 8kHz backup interrupt derived from core-PLL ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_FSC_BKP 0x00000400 ++/** External Interrupt from GPIO P4 ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_P4 0x00000100 ++/** External Interrupt from GPIO P3 ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_P3 0x00000080 ++/** External Interrupt from GPIO P2 ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_P2 0x00000040 ++/** External Interrupt from GPIO P1 ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_P1 0x00000020 ++/** External Interrupt from GPIO P0 ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_P0 0x00000010 ++/** EBU Serial Flash Busy ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_EBU_SF_BUSY 0x00000004 ++/** EBU Serial Flash Command Overwrite Error ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_EBU_SF_COVERR 0x00000002 ++/** EBU Serial Flash Command Error ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_EBU_SF_CMDERR 0x00000001 ++ ++/* Fields of "IM1 Interrupt Mode Register" */ ++/** Crossbar Error Interrupt ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_XBAR_ERROR 0x80000000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_XBAR_ERROR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_XBAR_ERROR_DIR 0x80000000 ++/** DDR Controller Interrupt ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_DDR 0x40000000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_DDR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_DDR_DIR 0x40000000 ++/** FPI Bus Control Unit Interrupt ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_BCU0 0x20000000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_BCU0_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_BCU0_DIR 0x20000000 ++/** SBIU interrupt ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_SBIU0 0x08000000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_SBIU0_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_SBIU0_DIR 0x08000000 ++/** Watchdog Prewarning Interrupt ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_WDT_PIR 0x02000000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_WDT_PIR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_WDT_PIR_DIR 0x02000000 ++/** Watchdog Access Error Interrupt ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_WDT_AEIR 0x01000000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_WDT_AEIR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_WDT_AEIR_DIR 0x01000000 ++/** SYS GPE Interrupt ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_SYS_GPE 0x00200000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_SYS_GPE_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_SYS_GPE_DIR 0x00200000 ++/** SYS1 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_SYS1 0x00100000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_SYS1_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_SYS1_DIR 0x00100000 ++/** PMA Interrupt from IntNode of the RX Clk Domain ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_PMA_RX 0x00020000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_PMA_RX_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_PMA_RX_DIR 0x00020000 ++/** PMA Interrupt from IntNode of the TX Clk Domain ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_PMA_TX 0x00010000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_PMA_TX_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_PMA_TX_DIR 0x00010000 ++/** PMA Interrupt from IntNode of the 200MHz Domain ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_PMA_200M 0x00008000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_PMA_200M_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_PMA_200M_DIR 0x00008000 ++/** Time of Day ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_TOD 0x00004000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_TOD_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_TOD_DIR 0x00004000 ++/** 8kHz root interrupt derived from GPON interface ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_FSC_ROOT 0x00002000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_FSC_ROOT_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_FSC_ROOT_DIR 0x00002000 ++/** FSC Timer Interrupt 1 ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_FSCT_CMP1 0x00001000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_FSCT_CMP1_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_FSCT_CMP1_DIR 0x00001000 ++/** FSC Timer Interrupt 0 ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_FSCT_CMP0 0x00000800 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_FSCT_CMP0_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_FSCT_CMP0_DIR 0x00000800 ++/** 8kHz backup interrupt derived from core-PLL ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_FSC_BKP 0x00000400 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_FSC_BKP_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_FSC_BKP_DIR 0x00000400 ++/** External Interrupt from GPIO P4 ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_P4 0x00000100 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_P4_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_P4_DIR 0x00000100 ++/** External Interrupt from GPIO P3 ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_P3 0x00000080 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_P3_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_P3_DIR 0x00000080 ++/** External Interrupt from GPIO P2 ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_P2 0x00000040 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_P2_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_P2_DIR 0x00000040 ++/** External Interrupt from GPIO P1 ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_P1 0x00000020 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_P1_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_P1_DIR 0x00000020 ++/** External Interrupt from GPIO P0 ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_P0 0x00000010 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_P0_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_P0_DIR 0x00000010 ++/** EBU Serial Flash Busy ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_EBU_SF_BUSY 0x00000004 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_EBU_SF_BUSY_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_EBU_SF_BUSY_DIR 0x00000004 ++/** EBU Serial Flash Command Overwrite Error ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_EBU_SF_COVERR 0x00000002 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_EBU_SF_COVERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_EBU_SF_COVERR_DIR 0x00000002 ++/** EBU Serial Flash Command Error ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_EBU_SF_CMDERR 0x00000001 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_EBU_SF_CMDERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_EBU_SF_CMDERR_DIR 0x00000001 ++ ++/* Fields of "IM2 Interrupt Status Register" */ ++/** EIM Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_EIM 0x80000000 ++/* Nothing ++#define ICU0_IM2_ISR_EIM_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_EIM_INTACK 0x80000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_EIM_INTOCC 0x80000000 ++/** GTC Upstream Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_GTC_US 0x40000000 ++/* Nothing ++#define ICU0_IM2_ISR_GTC_US_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_GTC_US_INTACK 0x40000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_GTC_US_INTOCC 0x40000000 ++/** GTC Downstream Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_GTC_DS 0x20000000 ++/* Nothing ++#define ICU0_IM2_ISR_GTC_DS_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_GTC_DS_INTACK 0x20000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_GTC_DS_INTOCC 0x20000000 ++/** TBM Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_TBM 0x00400000 ++/* Nothing ++#define ICU0_IM2_ISR_TBM_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_TBM_INTACK 0x00400000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_TBM_INTOCC 0x00400000 ++/** Dispatcher Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_DISP 0x00200000 ++/* Nothing ++#define ICU0_IM2_ISR_DISP_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_DISP_INTACK 0x00200000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_DISP_INTOCC 0x00200000 ++/** CONFIG Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_CONFIG 0x00100000 ++/* Nothing ++#define ICU0_IM2_ISR_CONFIG_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_CONFIG_INTACK 0x00100000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_CONFIG_INTOCC 0x00100000 ++/** CONFIG Break Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_CONFIG_BREAK 0x00080000 ++/* Nothing ++#define ICU0_IM2_ISR_CONFIG_BREAK_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_CONFIG_BREAK_INTACK 0x00080000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_CONFIG_BREAK_INTOCC 0x00080000 ++/** OCTRLC Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_OCTRLC 0x00040000 ++/* Nothing ++#define ICU0_IM2_ISR_OCTRLC_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_OCTRLC_INTACK 0x00040000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_OCTRLC_INTOCC 0x00040000 ++/** ICTRLC 1 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_ICTRLC1 0x00020000 ++/* Nothing ++#define ICU0_IM2_ISR_ICTRLC1_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_ICTRLC1_INTACK 0x00020000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_ICTRLC1_INTOCC 0x00020000 ++/** ICTRLC 0 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_ICTRLC0 0x00010000 ++/* Nothing ++#define ICU0_IM2_ISR_ICTRLC0_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_ICTRLC0_INTACK 0x00010000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_ICTRLC0_INTOCC 0x00010000 ++/** LINK 1 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_LINK1 0x00004000 ++/* Nothing ++#define ICU0_IM2_ISR_LINK1_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_LINK1_INTACK 0x00004000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_LINK1_INTOCC 0x00004000 ++/** TMU Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_TMU 0x00001000 ++/* Nothing ++#define ICU0_IM2_ISR_TMU_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_TMU_INTACK 0x00001000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_TMU_INTOCC 0x00001000 ++/** FSQM Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_FSQM 0x00000800 ++/* Nothing ++#define ICU0_IM2_ISR_FSQM_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_FSQM_INTACK 0x00000800 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_FSQM_INTOCC 0x00000800 ++/** IQM Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_IQM 0x00000400 ++/* Nothing ++#define ICU0_IM2_ISR_IQM_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_IQM_INTACK 0x00000400 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_IQM_INTOCC 0x00000400 ++/** OCTRLG Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_OCTRLG 0x00000200 ++/* Nothing ++#define ICU0_IM2_ISR_OCTRLG_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_OCTRLG_INTACK 0x00000200 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_OCTRLG_INTOCC 0x00000200 ++/** OCTRLL 3 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_OCTRLL3 0x00000080 ++/* Nothing ++#define ICU0_IM2_ISR_OCTRLL3_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_OCTRLL3_INTACK 0x00000080 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_OCTRLL3_INTOCC 0x00000080 ++/** OCTRLL 2 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_OCTRLL2 0x00000040 ++/* Nothing ++#define ICU0_IM2_ISR_OCTRLL2_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_OCTRLL2_INTACK 0x00000040 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_OCTRLL2_INTOCC 0x00000040 ++/** OCTRLL 1 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_OCTRLL1 0x00000020 ++/* Nothing ++#define ICU0_IM2_ISR_OCTRLL1_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_OCTRLL1_INTACK 0x00000020 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_OCTRLL1_INTOCC 0x00000020 ++/** OCTRLL 0 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_OCTRLL0 0x00000010 ++/* Nothing ++#define ICU0_IM2_ISR_OCTRLL0_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_OCTRLL0_INTACK 0x00000010 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_OCTRLL0_INTOCC 0x00000010 ++/** ICTRLL 3 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_ICTRLL3 0x00000008 ++/* Nothing ++#define ICU0_IM2_ISR_ICTRLL3_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_ICTRLL3_INTACK 0x00000008 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_ICTRLL3_INTOCC 0x00000008 ++/** ICTRLL 2 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_ICTRLL2 0x00000004 ++/* Nothing ++#define ICU0_IM2_ISR_ICTRLL2_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_ICTRLL2_INTACK 0x00000004 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_ICTRLL2_INTOCC 0x00000004 ++/** ICTRLL 1 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_ICTRLL1 0x00000002 ++/* Nothing ++#define ICU0_IM2_ISR_ICTRLL1_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_ICTRLL1_INTACK 0x00000002 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_ICTRLL1_INTOCC 0x00000002 ++/** ICTRLL 0 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_ICTRLL0 0x00000001 ++/* Nothing ++#define ICU0_IM2_ISR_ICTRLL0_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_ICTRLL0_INTACK 0x00000001 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_ICTRLL0_INTOCC 0x00000001 ++ ++/* Fields of "IM2 Interrupt Enable Register" */ ++/** EIM Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_EIM 0x80000000 ++/* Disable ++#define ICU0_IM2_IER_EIM_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_EIM_EN 0x80000000 ++/** GTC Upstream Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_GTC_US 0x40000000 ++/* Disable ++#define ICU0_IM2_IER_GTC_US_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_GTC_US_EN 0x40000000 ++/** GTC Downstream Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_GTC_DS 0x20000000 ++/* Disable ++#define ICU0_IM2_IER_GTC_DS_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_GTC_DS_EN 0x20000000 ++/** TBM Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_TBM 0x00400000 ++/* Disable ++#define ICU0_IM2_IER_TBM_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_TBM_EN 0x00400000 ++/** Dispatcher Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_DISP 0x00200000 ++/* Disable ++#define ICU0_IM2_IER_DISP_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_DISP_EN 0x00200000 ++/** CONFIG Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_CONFIG 0x00100000 ++/* Disable ++#define ICU0_IM2_IER_CONFIG_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_CONFIG_EN 0x00100000 ++/** CONFIG Break Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_CONFIG_BREAK 0x00080000 ++/* Disable ++#define ICU0_IM2_IER_CONFIG_BREAK_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_CONFIG_BREAK_EN 0x00080000 ++/** OCTRLC Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_OCTRLC 0x00040000 ++/* Disable ++#define ICU0_IM2_IER_OCTRLC_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_OCTRLC_EN 0x00040000 ++/** ICTRLC 1 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_ICTRLC1 0x00020000 ++/* Disable ++#define ICU0_IM2_IER_ICTRLC1_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_ICTRLC1_EN 0x00020000 ++/** ICTRLC 0 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_ICTRLC0 0x00010000 ++/* Disable ++#define ICU0_IM2_IER_ICTRLC0_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_ICTRLC0_EN 0x00010000 ++/** LINK 1 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_LINK1 0x00004000 ++/* Disable ++#define ICU0_IM2_IER_LINK1_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_LINK1_EN 0x00004000 ++/** TMU Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_TMU 0x00001000 ++/* Disable ++#define ICU0_IM2_IER_TMU_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_TMU_EN 0x00001000 ++/** FSQM Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_FSQM 0x00000800 ++/* Disable ++#define ICU0_IM2_IER_FSQM_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_FSQM_EN 0x00000800 ++/** IQM Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_IQM 0x00000400 ++/* Disable ++#define ICU0_IM2_IER_IQM_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_IQM_EN 0x00000400 ++/** OCTRLG Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_OCTRLG 0x00000200 ++/* Disable ++#define ICU0_IM2_IER_OCTRLG_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_OCTRLG_EN 0x00000200 ++/** OCTRLL 3 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_OCTRLL3 0x00000080 ++/* Disable ++#define ICU0_IM2_IER_OCTRLL3_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_OCTRLL3_EN 0x00000080 ++/** OCTRLL 2 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_OCTRLL2 0x00000040 ++/* Disable ++#define ICU0_IM2_IER_OCTRLL2_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_OCTRLL2_EN 0x00000040 ++/** OCTRLL 1 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_OCTRLL1 0x00000020 ++/* Disable ++#define ICU0_IM2_IER_OCTRLL1_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_OCTRLL1_EN 0x00000020 ++/** OCTRLL 0 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_OCTRLL0 0x00000010 ++/* Disable ++#define ICU0_IM2_IER_OCTRLL0_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_OCTRLL0_EN 0x00000010 ++/** ICTRLL 3 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_ICTRLL3 0x00000008 ++/* Disable ++#define ICU0_IM2_IER_ICTRLL3_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_ICTRLL3_EN 0x00000008 ++/** ICTRLL 2 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_ICTRLL2 0x00000004 ++/* Disable ++#define ICU0_IM2_IER_ICTRLL2_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_ICTRLL2_EN 0x00000004 ++/** ICTRLL 1 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_ICTRLL1 0x00000002 ++/* Disable ++#define ICU0_IM2_IER_ICTRLL1_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_ICTRLL1_EN 0x00000002 ++/** ICTRLL 0 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_ICTRLL0 0x00000001 ++/* Disable ++#define ICU0_IM2_IER_ICTRLL0_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_ICTRLL0_EN 0x00000001 ++ ++/* Fields of "IM2 Interrupt Output Status Register" */ ++/** EIM Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_EIM 0x80000000 ++/* Nothing ++#define ICU0_IM2_IOSR_EIM_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_EIM_INTOCC 0x80000000 ++/** GTC Upstream Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_GTC_US 0x40000000 ++/* Nothing ++#define ICU0_IM2_IOSR_GTC_US_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_GTC_US_INTOCC 0x40000000 ++/** GTC Downstream Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_GTC_DS 0x20000000 ++/* Nothing ++#define ICU0_IM2_IOSR_GTC_DS_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_GTC_DS_INTOCC 0x20000000 ++/** TBM Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_TBM 0x00400000 ++/* Nothing ++#define ICU0_IM2_IOSR_TBM_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_TBM_INTOCC 0x00400000 ++/** Dispatcher Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_DISP 0x00200000 ++/* Nothing ++#define ICU0_IM2_IOSR_DISP_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_DISP_INTOCC 0x00200000 ++/** CONFIG Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_CONFIG 0x00100000 ++/* Nothing ++#define ICU0_IM2_IOSR_CONFIG_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_CONFIG_INTOCC 0x00100000 ++/** CONFIG Break Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_CONFIG_BREAK 0x00080000 ++/* Nothing ++#define ICU0_IM2_IOSR_CONFIG_BREAK_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_CONFIG_BREAK_INTOCC 0x00080000 ++/** OCTRLC Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_OCTRLC 0x00040000 ++/* Nothing ++#define ICU0_IM2_IOSR_OCTRLC_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_OCTRLC_INTOCC 0x00040000 ++/** ICTRLC 1 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_ICTRLC1 0x00020000 ++/* Nothing ++#define ICU0_IM2_IOSR_ICTRLC1_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_ICTRLC1_INTOCC 0x00020000 ++/** ICTRLC 0 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_ICTRLC0 0x00010000 ++/* Nothing ++#define ICU0_IM2_IOSR_ICTRLC0_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_ICTRLC0_INTOCC 0x00010000 ++/** LINK 1 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_LINK1 0x00004000 ++/* Nothing ++#define ICU0_IM2_IOSR_LINK1_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_LINK1_INTOCC 0x00004000 ++/** TMU Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_TMU 0x00001000 ++/* Nothing ++#define ICU0_IM2_IOSR_TMU_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_TMU_INTOCC 0x00001000 ++/** FSQM Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_FSQM 0x00000800 ++/* Nothing ++#define ICU0_IM2_IOSR_FSQM_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_FSQM_INTOCC 0x00000800 ++/** IQM Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_IQM 0x00000400 ++/* Nothing ++#define ICU0_IM2_IOSR_IQM_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_IQM_INTOCC 0x00000400 ++/** OCTRLG Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_OCTRLG 0x00000200 ++/* Nothing ++#define ICU0_IM2_IOSR_OCTRLG_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_OCTRLG_INTOCC 0x00000200 ++/** OCTRLL 3 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_OCTRLL3 0x00000080 ++/* Nothing ++#define ICU0_IM2_IOSR_OCTRLL3_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_OCTRLL3_INTOCC 0x00000080 ++/** OCTRLL 2 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_OCTRLL2 0x00000040 ++/* Nothing ++#define ICU0_IM2_IOSR_OCTRLL2_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_OCTRLL2_INTOCC 0x00000040 ++/** OCTRLL 1 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_OCTRLL1 0x00000020 ++/* Nothing ++#define ICU0_IM2_IOSR_OCTRLL1_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_OCTRLL1_INTOCC 0x00000020 ++/** OCTRLL 0 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_OCTRLL0 0x00000010 ++/* Nothing ++#define ICU0_IM2_IOSR_OCTRLL0_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_OCTRLL0_INTOCC 0x00000010 ++/** ICTRLL 3 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_ICTRLL3 0x00000008 ++/* Nothing ++#define ICU0_IM2_IOSR_ICTRLL3_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_ICTRLL3_INTOCC 0x00000008 ++/** ICTRLL 2 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_ICTRLL2 0x00000004 ++/* Nothing ++#define ICU0_IM2_IOSR_ICTRLL2_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_ICTRLL2_INTOCC 0x00000004 ++/** ICTRLL 1 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_ICTRLL1 0x00000002 ++/* Nothing ++#define ICU0_IM2_IOSR_ICTRLL1_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_ICTRLL1_INTOCC 0x00000002 ++/** ICTRLL 0 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_ICTRLL0 0x00000001 ++/* Nothing ++#define ICU0_IM2_IOSR_ICTRLL0_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_ICTRLL0_INTOCC 0x00000001 ++ ++/* Fields of "IM2 Interrupt Request Set Register" */ ++/** EIM Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_EIM 0x80000000 ++/** GTC Upstream Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_GTC_US 0x40000000 ++/** GTC Downstream Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_GTC_DS 0x20000000 ++/** TBM Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_TBM 0x00400000 ++/** Dispatcher Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_DISP 0x00200000 ++/** CONFIG Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_CONFIG 0x00100000 ++/** CONFIG Break Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_CONFIG_BREAK 0x00080000 ++/** OCTRLC Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_OCTRLC 0x00040000 ++/** ICTRLC 1 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_ICTRLC1 0x00020000 ++/** ICTRLC 0 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_ICTRLC0 0x00010000 ++/** LINK 1 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_LINK1 0x00004000 ++/** TMU Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_TMU 0x00001000 ++/** FSQM Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_FSQM 0x00000800 ++/** IQM Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_IQM 0x00000400 ++/** OCTRLG Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_OCTRLG 0x00000200 ++/** OCTRLL 3 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_OCTRLL3 0x00000080 ++/** OCTRLL 2 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_OCTRLL2 0x00000040 ++/** OCTRLL 1 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_OCTRLL1 0x00000020 ++/** OCTRLL 0 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_OCTRLL0 0x00000010 ++/** ICTRLL 3 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_ICTRLL3 0x00000008 ++/** ICTRLL 2 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_ICTRLL2 0x00000004 ++/** ICTRLL 1 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_ICTRLL1 0x00000002 ++/** ICTRLL 0 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_ICTRLL0 0x00000001 ++ ++/* Fields of "IM2 Interrupt Mode Register" */ ++/** EIM Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_EIM 0x80000000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_EIM_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_EIM_DIR 0x80000000 ++/** GTC Upstream Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_GTC_US 0x40000000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_GTC_US_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_GTC_US_DIR 0x40000000 ++/** GTC Downstream Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_GTC_DS 0x20000000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_GTC_DS_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_GTC_DS_DIR 0x20000000 ++/** TBM Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_TBM 0x00400000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_TBM_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_TBM_DIR 0x00400000 ++/** Dispatcher Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_DISP 0x00200000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_DISP_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_DISP_DIR 0x00200000 ++/** CONFIG Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_CONFIG 0x00100000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_CONFIG_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_CONFIG_DIR 0x00100000 ++/** CONFIG Break Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_CONFIG_BREAK 0x00080000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_CONFIG_BREAK_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_CONFIG_BREAK_DIR 0x00080000 ++/** OCTRLC Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_OCTRLC 0x00040000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_OCTRLC_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_OCTRLC_DIR 0x00040000 ++/** ICTRLC 1 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_ICTRLC1 0x00020000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_ICTRLC1_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_ICTRLC1_DIR 0x00020000 ++/** ICTRLC 0 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_ICTRLC0 0x00010000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_ICTRLC0_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_ICTRLC0_DIR 0x00010000 ++/** LINK 1 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_LINK1 0x00004000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_LINK1_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_LINK1_DIR 0x00004000 ++/** TMU Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_TMU 0x00001000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_TMU_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_TMU_DIR 0x00001000 ++/** FSQM Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_FSQM 0x00000800 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_FSQM_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_FSQM_DIR 0x00000800 ++/** IQM Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_IQM 0x00000400 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_IQM_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_IQM_DIR 0x00000400 ++/** OCTRLG Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_OCTRLG 0x00000200 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_OCTRLG_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_OCTRLG_DIR 0x00000200 ++/** OCTRLL 3 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_OCTRLL3 0x00000080 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_OCTRLL3_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_OCTRLL3_DIR 0x00000080 ++/** OCTRLL 2 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_OCTRLL2 0x00000040 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_OCTRLL2_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_OCTRLL2_DIR 0x00000040 ++/** OCTRLL 1 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_OCTRLL1 0x00000020 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_OCTRLL1_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_OCTRLL1_DIR 0x00000020 ++/** OCTRLL 0 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_OCTRLL0 0x00000010 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_OCTRLL0_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_OCTRLL0_DIR 0x00000010 ++/** ICTRLL 3 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_ICTRLL3 0x00000008 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_ICTRLL3_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_ICTRLL3_DIR 0x00000008 ++/** ICTRLL 2 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_ICTRLL2 0x00000004 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_ICTRLL2_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_ICTRLL2_DIR 0x00000004 ++/** ICTRLL 1 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_ICTRLL1 0x00000002 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_ICTRLL1_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_ICTRLL1_DIR 0x00000002 ++/** ICTRLL 0 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_ICTRLL0 0x00000001 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_ICTRLL0_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_ICTRLL0_DIR 0x00000001 ++ ++/* Fields of "IM3 Interrupt Status Register" */ ++/** DFEV0, Channel 0 General Purpose Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_1GP 0x80000000 ++/* Nothing ++#define ICU0_IM3_ISR_DFEV0_1GP_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_1GP_INTACK 0x80000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_DFEV0_1GP_INTOCC 0x80000000 ++/** DFEV0, Channel 0 Receive Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_1RX 0x40000000 ++/* Nothing ++#define ICU0_IM3_ISR_DFEV0_1RX_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_1RX_INTACK 0x40000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_DFEV0_1RX_INTOCC 0x40000000 ++/** DFEV0, Channel 0 Transmit Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_1TX 0x20000000 ++/* Nothing ++#define ICU0_IM3_ISR_DFEV0_1TX_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_1TX_INTACK 0x20000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_DFEV0_1TX_INTOCC 0x20000000 ++/** DFEV0, Channel 1 General Purpose Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_2GP 0x10000000 ++/* Nothing ++#define ICU0_IM3_ISR_DFEV0_2GP_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_2GP_INTACK 0x10000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_DFEV0_2GP_INTOCC 0x10000000 ++/** DFEV0, Channel 1 Receive Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_2RX 0x08000000 ++/* Nothing ++#define ICU0_IM3_ISR_DFEV0_2RX_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_2RX_INTACK 0x08000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_DFEV0_2RX_INTOCC 0x08000000 ++/** DFEV0, Channel 1 Transmit Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_2TX 0x04000000 ++/* Nothing ++#define ICU0_IM3_ISR_DFEV0_2TX_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_2TX_INTACK 0x04000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_DFEV0_2TX_INTOCC 0x04000000 ++/** GPTC Timer/Counter 3B Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC3B 0x00200000 ++/* Nothing ++#define ICU0_IM3_ISR_GPTC_TC3B_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC3B_INTACK 0x00200000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_GPTC_TC3B_INTOCC 0x00200000 ++/** GPTC Timer/Counter 3A Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC3A 0x00100000 ++/* Nothing ++#define ICU0_IM3_ISR_GPTC_TC3A_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC3A_INTACK 0x00100000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_GPTC_TC3A_INTOCC 0x00100000 ++/** GPTC Timer/Counter 2B Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC2B 0x00080000 ++/* Nothing ++#define ICU0_IM3_ISR_GPTC_TC2B_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC2B_INTACK 0x00080000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_GPTC_TC2B_INTOCC 0x00080000 ++/** GPTC Timer/Counter 2A Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC2A 0x00040000 ++/* Nothing ++#define ICU0_IM3_ISR_GPTC_TC2A_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC2A_INTACK 0x00040000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_GPTC_TC2A_INTOCC 0x00040000 ++/** GPTC Timer/Counter 1B Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC1B 0x00020000 ++/* Nothing ++#define ICU0_IM3_ISR_GPTC_TC1B_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC1B_INTACK 0x00020000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_GPTC_TC1B_INTOCC 0x00020000 ++/** GPTC Timer/Counter 1A Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC1A 0x00010000 ++/* Nothing ++#define ICU0_IM3_ISR_GPTC_TC1A_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC1A_INTACK 0x00010000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_GPTC_TC1A_INTOCC 0x00010000 ++/** ASC1 Soft Flow Control Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC1_SFC 0x00008000 ++/* Nothing ++#define ICU0_IM3_ISR_ASC1_SFC_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC1_SFC_INTACK 0x00008000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC1_SFC_INTOCC 0x00008000 ++/** ASC1 Modem Status Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC1_MS 0x00004000 ++/* Nothing ++#define ICU0_IM3_ISR_ASC1_MS_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC1_MS_INTACK 0x00004000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC1_MS_INTOCC 0x00004000 ++/** ASC1 Autobaud Detection Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC1_ABDET 0x00002000 ++/* Nothing ++#define ICU0_IM3_ISR_ASC1_ABDET_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC1_ABDET_INTACK 0x00002000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC1_ABDET_INTOCC 0x00002000 ++/** ASC1 Autobaud Start Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC1_ABST 0x00001000 ++/* Nothing ++#define ICU0_IM3_ISR_ASC1_ABST_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC1_ABST_INTACK 0x00001000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC1_ABST_INTOCC 0x00001000 ++/** ASC1 Transmit Buffer Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC1_TB 0x00000800 ++/* Nothing ++#define ICU0_IM3_ISR_ASC1_TB_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC1_TB_INTACK 0x00000800 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC1_TB_INTOCC 0x00000800 ++/** ASC1 Error Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC1_E 0x00000400 ++/* Nothing ++#define ICU0_IM3_ISR_ASC1_E_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC1_E_INTACK 0x00000400 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC1_E_INTOCC 0x00000400 ++/** ASC1 Receive Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC1_R 0x00000200 ++/* Nothing ++#define ICU0_IM3_ISR_ASC1_R_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC1_R_INTACK 0x00000200 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC1_R_INTOCC 0x00000200 ++/** ASC1 Transmit Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC1_T 0x00000100 ++/* Nothing ++#define ICU0_IM3_ISR_ASC1_T_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC1_T_INTACK 0x00000100 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC1_T_INTOCC 0x00000100 ++/** ASC0 Soft Flow Control Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC0_SFC 0x00000080 ++/* Nothing ++#define ICU0_IM3_ISR_ASC0_SFC_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC0_SFC_INTACK 0x00000080 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC0_SFC_INTOCC 0x00000080 ++/** ASC1 Modem Status Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC0_MS 0x00000040 ++/* Nothing ++#define ICU0_IM3_ISR_ASC0_MS_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC0_MS_INTACK 0x00000040 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC0_MS_INTOCC 0x00000040 ++/** ASC0 Autobaud Detection Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC0_ABDET 0x00000020 ++/* Nothing ++#define ICU0_IM3_ISR_ASC0_ABDET_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC0_ABDET_INTACK 0x00000020 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC0_ABDET_INTOCC 0x00000020 ++/** ASC0 Autobaud Start Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC0_ABST 0x00000010 ++/* Nothing ++#define ICU0_IM3_ISR_ASC0_ABST_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC0_ABST_INTACK 0x00000010 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC0_ABST_INTOCC 0x00000010 ++/** ASC0 Transmit Buffer Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC0_TB 0x00000008 ++/* Nothing ++#define ICU0_IM3_ISR_ASC0_TB_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC0_TB_INTACK 0x00000008 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC0_TB_INTOCC 0x00000008 ++/** ASC0 Error Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC0_E 0x00000004 ++/* Nothing ++#define ICU0_IM3_ISR_ASC0_E_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC0_E_INTACK 0x00000004 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC0_E_INTOCC 0x00000004 ++/** ASC0 Receive Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC0_R 0x00000002 ++/* Nothing ++#define ICU0_IM3_ISR_ASC0_R_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC0_R_INTACK 0x00000002 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC0_R_INTOCC 0x00000002 ++/** ASC0 Transmit Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC0_T 0x00000001 ++/* Nothing ++#define ICU0_IM3_ISR_ASC0_T_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC0_T_INTACK 0x00000001 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC0_T_INTOCC 0x00000001 ++ ++/* Fields of "IM3 Interrupt Enable Register" */ ++/** DFEV0, Channel 0 General Purpose Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_DFEV0_1GP 0x80000000 ++/* Disable ++#define ICU0_IM3_IER_DFEV0_1GP_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_DFEV0_1GP_EN 0x80000000 ++/** DFEV0, Channel 0 Receive Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_DFEV0_1RX 0x40000000 ++/* Disable ++#define ICU0_IM3_IER_DFEV0_1RX_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_DFEV0_1RX_EN 0x40000000 ++/** DFEV0, Channel 0 Transmit Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_DFEV0_1TX 0x20000000 ++/* Disable ++#define ICU0_IM3_IER_DFEV0_1TX_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_DFEV0_1TX_EN 0x20000000 ++/** DFEV0, Channel 1 General Purpose Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_DFEV0_2GP 0x10000000 ++/* Disable ++#define ICU0_IM3_IER_DFEV0_2GP_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_DFEV0_2GP_EN 0x10000000 ++/** DFEV0, Channel 1 Receive Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_DFEV0_2RX 0x08000000 ++/* Disable ++#define ICU0_IM3_IER_DFEV0_2RX_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_DFEV0_2RX_EN 0x08000000 ++/** DFEV0, Channel 1 Transmit Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_DFEV0_2TX 0x04000000 ++/* Disable ++#define ICU0_IM3_IER_DFEV0_2TX_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_DFEV0_2TX_EN 0x04000000 ++/** GPTC Timer/Counter 3B Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_GPTC_TC3B 0x00200000 ++/* Disable ++#define ICU0_IM3_IER_GPTC_TC3B_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_GPTC_TC3B_EN 0x00200000 ++/** GPTC Timer/Counter 3A Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_GPTC_TC3A 0x00100000 ++/* Disable ++#define ICU0_IM3_IER_GPTC_TC3A_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_GPTC_TC3A_EN 0x00100000 ++/** GPTC Timer/Counter 2B Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_GPTC_TC2B 0x00080000 ++/* Disable ++#define ICU0_IM3_IER_GPTC_TC2B_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_GPTC_TC2B_EN 0x00080000 ++/** GPTC Timer/Counter 2A Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_GPTC_TC2A 0x00040000 ++/* Disable ++#define ICU0_IM3_IER_GPTC_TC2A_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_GPTC_TC2A_EN 0x00040000 ++/** GPTC Timer/Counter 1B Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_GPTC_TC1B 0x00020000 ++/* Disable ++#define ICU0_IM3_IER_GPTC_TC1B_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_GPTC_TC1B_EN 0x00020000 ++/** GPTC Timer/Counter 1A Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_GPTC_TC1A 0x00010000 ++/* Disable ++#define ICU0_IM3_IER_GPTC_TC1A_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_GPTC_TC1A_EN 0x00010000 ++/** ASC1 Soft Flow Control Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC1_SFC 0x00008000 ++/* Disable ++#define ICU0_IM3_IER_ASC1_SFC_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC1_SFC_EN 0x00008000 ++/** ASC1 Modem Status Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC1_MS 0x00004000 ++/* Disable ++#define ICU0_IM3_IER_ASC1_MS_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC1_MS_EN 0x00004000 ++/** ASC1 Autobaud Detection Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC1_ABDET 0x00002000 ++/* Disable ++#define ICU0_IM3_IER_ASC1_ABDET_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC1_ABDET_EN 0x00002000 ++/** ASC1 Autobaud Start Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC1_ABST 0x00001000 ++/* Disable ++#define ICU0_IM3_IER_ASC1_ABST_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC1_ABST_EN 0x00001000 ++/** ASC1 Transmit Buffer Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC1_TB 0x00000800 ++/* Disable ++#define ICU0_IM3_IER_ASC1_TB_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC1_TB_EN 0x00000800 ++/** ASC1 Error Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC1_E 0x00000400 ++/* Disable ++#define ICU0_IM3_IER_ASC1_E_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC1_E_EN 0x00000400 ++/** ASC1 Receive Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC1_R 0x00000200 ++/* Disable ++#define ICU0_IM3_IER_ASC1_R_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC1_R_EN 0x00000200 ++/** ASC1 Transmit Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC1_T 0x00000100 ++/* Disable ++#define ICU0_IM3_IER_ASC1_T_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC1_T_EN 0x00000100 ++/** ASC0 Soft Flow Control Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC0_SFC 0x00000080 ++/* Disable ++#define ICU0_IM3_IER_ASC0_SFC_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC0_SFC_EN 0x00000080 ++/** ASC1 Modem Status Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC0_MS 0x00000040 ++/* Disable ++#define ICU0_IM3_IER_ASC0_MS_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC0_MS_EN 0x00000040 ++/** ASC0 Autobaud Detection Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC0_ABDET 0x00000020 ++/* Disable ++#define ICU0_IM3_IER_ASC0_ABDET_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC0_ABDET_EN 0x00000020 ++/** ASC0 Autobaud Start Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC0_ABST 0x00000010 ++/* Disable ++#define ICU0_IM3_IER_ASC0_ABST_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC0_ABST_EN 0x00000010 ++/** ASC0 Transmit Buffer Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC0_TB 0x00000008 ++/* Disable ++#define ICU0_IM3_IER_ASC0_TB_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC0_TB_EN 0x00000008 ++/** ASC0 Error Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC0_E 0x00000004 ++/* Disable ++#define ICU0_IM3_IER_ASC0_E_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC0_E_EN 0x00000004 ++/** ASC0 Receive Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC0_R 0x00000002 ++/* Disable ++#define ICU0_IM3_IER_ASC0_R_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC0_R_EN 0x00000002 ++/** ASC0 Transmit Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC0_T 0x00000001 ++/* Disable ++#define ICU0_IM3_IER_ASC0_T_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC0_T_EN 0x00000001 ++ ++/* Fields of "IM3 Interrupt Output Status Register" */ ++/** DFEV0, Channel 0 General Purpose Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_DFEV0_1GP 0x80000000 ++/* Nothing ++#define ICU0_IM3_IOSR_DFEV0_1GP_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_DFEV0_1GP_INTOCC 0x80000000 ++/** DFEV0, Channel 0 Receive Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_DFEV0_1RX 0x40000000 ++/* Nothing ++#define ICU0_IM3_IOSR_DFEV0_1RX_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_DFEV0_1RX_INTOCC 0x40000000 ++/** DFEV0, Channel 0 Transmit Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_DFEV0_1TX 0x20000000 ++/* Nothing ++#define ICU0_IM3_IOSR_DFEV0_1TX_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_DFEV0_1TX_INTOCC 0x20000000 ++/** DFEV0, Channel 1 General Purpose Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_DFEV0_2GP 0x10000000 ++/* Nothing ++#define ICU0_IM3_IOSR_DFEV0_2GP_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_DFEV0_2GP_INTOCC 0x10000000 ++/** DFEV0, Channel 1 Receive Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_DFEV0_2RX 0x08000000 ++/* Nothing ++#define ICU0_IM3_IOSR_DFEV0_2RX_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_DFEV0_2RX_INTOCC 0x08000000 ++/** DFEV0, Channel 1 Transmit Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_DFEV0_2TX 0x04000000 ++/* Nothing ++#define ICU0_IM3_IOSR_DFEV0_2TX_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_DFEV0_2TX_INTOCC 0x04000000 ++/** GPTC Timer/Counter 3B Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_GPTC_TC3B 0x00200000 ++/* Nothing ++#define ICU0_IM3_IOSR_GPTC_TC3B_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_GPTC_TC3B_INTOCC 0x00200000 ++/** GPTC Timer/Counter 3A Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_GPTC_TC3A 0x00100000 ++/* Nothing ++#define ICU0_IM3_IOSR_GPTC_TC3A_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_GPTC_TC3A_INTOCC 0x00100000 ++/** GPTC Timer/Counter 2B Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_GPTC_TC2B 0x00080000 ++/* Nothing ++#define ICU0_IM3_IOSR_GPTC_TC2B_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_GPTC_TC2B_INTOCC 0x00080000 ++/** GPTC Timer/Counter 2A Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_GPTC_TC2A 0x00040000 ++/* Nothing ++#define ICU0_IM3_IOSR_GPTC_TC2A_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_GPTC_TC2A_INTOCC 0x00040000 ++/** GPTC Timer/Counter 1B Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_GPTC_TC1B 0x00020000 ++/* Nothing ++#define ICU0_IM3_IOSR_GPTC_TC1B_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_GPTC_TC1B_INTOCC 0x00020000 ++/** GPTC Timer/Counter 1A Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_GPTC_TC1A 0x00010000 ++/* Nothing ++#define ICU0_IM3_IOSR_GPTC_TC1A_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_GPTC_TC1A_INTOCC 0x00010000 ++/** ASC1 Soft Flow Control Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC1_SFC 0x00008000 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC1_SFC_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC1_SFC_INTOCC 0x00008000 ++/** ASC1 Modem Status Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC1_MS 0x00004000 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC1_MS_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC1_MS_INTOCC 0x00004000 ++/** ASC1 Autobaud Detection Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC1_ABDET 0x00002000 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC1_ABDET_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC1_ABDET_INTOCC 0x00002000 ++/** ASC1 Autobaud Start Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC1_ABST 0x00001000 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC1_ABST_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC1_ABST_INTOCC 0x00001000 ++/** ASC1 Transmit Buffer Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC1_TB 0x00000800 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC1_TB_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC1_TB_INTOCC 0x00000800 ++/** ASC1 Error Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC1_E 0x00000400 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC1_E_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC1_E_INTOCC 0x00000400 ++/** ASC1 Receive Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC1_R 0x00000200 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC1_R_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC1_R_INTOCC 0x00000200 ++/** ASC1 Transmit Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC1_T 0x00000100 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC1_T_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC1_T_INTOCC 0x00000100 ++/** ASC0 Soft Flow Control Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC0_SFC 0x00000080 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC0_SFC_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC0_SFC_INTOCC 0x00000080 ++/** ASC1 Modem Status Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC0_MS 0x00000040 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC0_MS_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC0_MS_INTOCC 0x00000040 ++/** ASC0 Autobaud Detection Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC0_ABDET 0x00000020 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC0_ABDET_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC0_ABDET_INTOCC 0x00000020 ++/** ASC0 Autobaud Start Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC0_ABST 0x00000010 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC0_ABST_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC0_ABST_INTOCC 0x00000010 ++/** ASC0 Transmit Buffer Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC0_TB 0x00000008 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC0_TB_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC0_TB_INTOCC 0x00000008 ++/** ASC0 Error Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC0_E 0x00000004 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC0_E_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC0_E_INTOCC 0x00000004 ++/** ASC0 Receive Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC0_R 0x00000002 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC0_R_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC0_R_INTOCC 0x00000002 ++/** ASC0 Transmit Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC0_T 0x00000001 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC0_T_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC0_T_INTOCC 0x00000001 ++ ++/* Fields of "IM3 Interrupt Request Set Register" */ ++/** DFEV0, Channel 0 General Purpose Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_DFEV0_1GP 0x80000000 ++/** DFEV0, Channel 0 Receive Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_DFEV0_1RX 0x40000000 ++/** DFEV0, Channel 0 Transmit Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_DFEV0_1TX 0x20000000 ++/** DFEV0, Channel 1 General Purpose Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_DFEV0_2GP 0x10000000 ++/** DFEV0, Channel 1 Receive Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_DFEV0_2RX 0x08000000 ++/** DFEV0, Channel 1 Transmit Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_DFEV0_2TX 0x04000000 ++/** GPTC Timer/Counter 3B Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_GPTC_TC3B 0x00200000 ++/** GPTC Timer/Counter 3A Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_GPTC_TC3A 0x00100000 ++/** GPTC Timer/Counter 2B Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_GPTC_TC2B 0x00080000 ++/** GPTC Timer/Counter 2A Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_GPTC_TC2A 0x00040000 ++/** GPTC Timer/Counter 1B Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_GPTC_TC1B 0x00020000 ++/** GPTC Timer/Counter 1A Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_GPTC_TC1A 0x00010000 ++/** ASC1 Soft Flow Control Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC1_SFC 0x00008000 ++/** ASC1 Modem Status Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC1_MS 0x00004000 ++/** ASC1 Autobaud Detection Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC1_ABDET 0x00002000 ++/** ASC1 Autobaud Start Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC1_ABST 0x00001000 ++/** ASC1 Transmit Buffer Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC1_TB 0x00000800 ++/** ASC1 Error Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC1_E 0x00000400 ++/** ASC1 Receive Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC1_R 0x00000200 ++/** ASC1 Transmit Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC1_T 0x00000100 ++/** ASC0 Soft Flow Control Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC0_SFC 0x00000080 ++/** ASC1 Modem Status Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC0_MS 0x00000040 ++/** ASC0 Autobaud Detection Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC0_ABDET 0x00000020 ++/** ASC0 Autobaud Start Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC0_ABST 0x00000010 ++/** ASC0 Transmit Buffer Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC0_TB 0x00000008 ++/** ASC0 Error Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC0_E 0x00000004 ++/** ASC0 Receive Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC0_R 0x00000002 ++/** ASC0 Transmit Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC0_T 0x00000001 ++ ++/* Fields of "IM3 Interrupt Mode Register" */ ++/** DFEV0, Channel 0 General Purpose Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_1GP 0x80000000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_DFEV0_1GP_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_1GP_DIR 0x80000000 ++/** DFEV0, Channel 0 Receive Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_1RX 0x40000000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_DFEV0_1RX_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_1RX_DIR 0x40000000 ++/** DFEV0, Channel 0 Transmit Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_1TX 0x20000000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_DFEV0_1TX_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_1TX_DIR 0x20000000 ++/** DFEV0, Channel 1 General Purpose Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_2GP 0x10000000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_DFEV0_2GP_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_2GP_DIR 0x10000000 ++/** DFEV0, Channel 1 Receive Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_2RX 0x08000000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_DFEV0_2RX_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_2RX_DIR 0x08000000 ++/** DFEV0, Channel 1 Transmit Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_2TX 0x04000000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_DFEV0_2TX_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_2TX_DIR 0x04000000 ++/** GPTC Timer/Counter 3B Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC3B 0x00200000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_GPTC_TC3B_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC3B_DIR 0x00200000 ++/** GPTC Timer/Counter 3A Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC3A 0x00100000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_GPTC_TC3A_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC3A_DIR 0x00100000 ++/** GPTC Timer/Counter 2B Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC2B 0x00080000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_GPTC_TC2B_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC2B_DIR 0x00080000 ++/** GPTC Timer/Counter 2A Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC2A 0x00040000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_GPTC_TC2A_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC2A_DIR 0x00040000 ++/** GPTC Timer/Counter 1B Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC1B 0x00020000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_GPTC_TC1B_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC1B_DIR 0x00020000 ++/** GPTC Timer/Counter 1A Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC1A 0x00010000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_GPTC_TC1A_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC1A_DIR 0x00010000 ++/** ASC1 Soft Flow Control Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC1_SFC 0x00008000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC1_SFC_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC1_SFC_DIR 0x00008000 ++/** ASC1 Modem Status Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC1_MS 0x00004000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC1_MS_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC1_MS_DIR 0x00004000 ++/** ASC1 Autobaud Detection Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC1_ABDET 0x00002000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC1_ABDET_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC1_ABDET_DIR 0x00002000 ++/** ASC1 Autobaud Start Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC1_ABST 0x00001000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC1_ABST_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC1_ABST_DIR 0x00001000 ++/** ASC1 Transmit Buffer Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC1_TB 0x00000800 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC1_TB_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC1_TB_DIR 0x00000800 ++/** ASC1 Error Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC1_E 0x00000400 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC1_E_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC1_E_DIR 0x00000400 ++/** ASC1 Receive Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC1_R 0x00000200 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC1_R_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC1_R_DIR 0x00000200 ++/** ASC1 Transmit Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC1_T 0x00000100 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC1_T_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC1_T_DIR 0x00000100 ++/** ASC0 Soft Flow Control Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC0_SFC 0x00000080 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC0_SFC_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC0_SFC_DIR 0x00000080 ++/** ASC1 Modem Status Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC0_MS 0x00000040 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC0_MS_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC0_MS_DIR 0x00000040 ++/** ASC0 Autobaud Detection Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC0_ABDET 0x00000020 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC0_ABDET_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC0_ABDET_DIR 0x00000020 ++/** ASC0 Autobaud Start Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC0_ABST 0x00000010 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC0_ABST_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC0_ABST_DIR 0x00000010 ++/** ASC0 Transmit Buffer Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC0_TB 0x00000008 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC0_TB_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC0_TB_DIR 0x00000008 ++/** ASC0 Error Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC0_E 0x00000004 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC0_E_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC0_E_DIR 0x00000004 ++/** ASC0 Receive Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC0_R 0x00000002 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC0_R_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC0_R_DIR 0x00000002 ++/** ASC0 Transmit Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC0_T 0x00000001 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC0_T_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC0_T_DIR 0x00000001 ++ ++/* Fields of "IM4 Interrupt Status Register" */ ++/** VPE0 Performance Monitoring Counter Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_VPE0_PMCIR 0x80000000 ++/* Nothing ++#define ICU0_IM4_ISR_VPE0_PMCIR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_VPE0_PMCIR_INTACK 0x80000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_VPE0_PMCIR_INTOCC 0x80000000 ++/** VPE0 Error Level Flag Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_VPE0_ERL 0x40000000 ++/* Nothing ++#define ICU0_IM4_ISR_VPE0_ERL_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_VPE0_ERL_INTACK 0x40000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_VPE0_ERL_INTOCC 0x40000000 ++/** VPE0 Exception Level Flag Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_VPE0_EXL 0x20000000 ++/* Nothing ++#define ICU0_IM4_ISR_VPE0_EXL_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_VPE0_EXL_INTACK 0x20000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_VPE0_EXL_INTOCC 0x20000000 ++/** MPS Bin. Sem Interrupt to VPE0 ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR8 0x00400000 ++/* Nothing ++#define ICU0_IM4_ISR_MPS_IR8_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR8_INTACK 0x00400000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_MPS_IR8_INTOCC 0x00400000 ++/** MPS Global Interrupt to VPE0 ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR7 0x00200000 ++/* Nothing ++#define ICU0_IM4_ISR_MPS_IR7_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR7_INTACK 0x00200000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_MPS_IR7_INTOCC 0x00200000 ++/** MPS Status Interrupt #6 (VPE1 to VPE0) ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR6 0x00100000 ++/* Nothing ++#define ICU0_IM4_ISR_MPS_IR6_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR6_INTACK 0x00100000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_MPS_IR6_INTOCC 0x00100000 ++/** MPS Status Interrupt #5 (VPE1 to VPE0) ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR5 0x00080000 ++/* Nothing ++#define ICU0_IM4_ISR_MPS_IR5_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR5_INTACK 0x00080000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_MPS_IR5_INTOCC 0x00080000 ++/** MPS Status Interrupt #4 (VPE1 to VPE0) ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR4 0x00040000 ++/* Nothing ++#define ICU0_IM4_ISR_MPS_IR4_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR4_INTACK 0x00040000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_MPS_IR4_INTOCC 0x00040000 ++/** MPS Status Interrupt #3 (VPE1 to VPE0) ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR3 0x00020000 ++/* Nothing ++#define ICU0_IM4_ISR_MPS_IR3_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR3_INTACK 0x00020000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_MPS_IR3_INTOCC 0x00020000 ++/** MPS Status Interrupt #2 (VPE1 to VPE0) ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR2 0x00010000 ++/* Nothing ++#define ICU0_IM4_ISR_MPS_IR2_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR2_INTACK 0x00010000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_MPS_IR2_INTOCC 0x00010000 ++/** MPS Status Interrupt #1 (VPE1 to VPE0) ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR1 0x00008000 ++/* Nothing ++#define ICU0_IM4_ISR_MPS_IR1_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR1_INTACK 0x00008000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_MPS_IR1_INTOCC 0x00008000 ++/** MPS Status Interrupt #0 (VPE1 to VPE0) ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR0 0x00004000 ++/* Nothing ++#define ICU0_IM4_ISR_MPS_IR0_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR0_INTACK 0x00004000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_MPS_IR0_INTOCC 0x00004000 ++/** TMU Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_TMU_ERR 0x00001000 ++/* Nothing ++#define ICU0_IM4_ISR_TMU_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_TMU_ERR_INTACK 0x00001000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_TMU_ERR_INTOCC 0x00001000 ++/** FSQM Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_FSQM_ERR 0x00000800 ++/* Nothing ++#define ICU0_IM4_ISR_FSQM_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_FSQM_ERR_INTACK 0x00000800 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_FSQM_ERR_INTOCC 0x00000800 ++/** IQM Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_IQM_ERR 0x00000400 ++/* Nothing ++#define ICU0_IM4_ISR_IQM_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_IQM_ERR_INTACK 0x00000400 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_IQM_ERR_INTOCC 0x00000400 ++/** OCTRLG Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_OCTRLG_ERR 0x00000200 ++/* Nothing ++#define ICU0_IM4_ISR_OCTRLG_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_OCTRLG_ERR_INTACK 0x00000200 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_OCTRLG_ERR_INTOCC 0x00000200 ++/** ICTRLG Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_ICTRLG_ERR 0x00000100 ++/* Nothing ++#define ICU0_IM4_ISR_ICTRLG_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_ICTRLG_ERR_INTACK 0x00000100 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_ICTRLG_ERR_INTOCC 0x00000100 ++/** OCTRLL 3 Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_OCTRLL3_ERR 0x00000080 ++/* Nothing ++#define ICU0_IM4_ISR_OCTRLL3_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_OCTRLL3_ERR_INTACK 0x00000080 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_OCTRLL3_ERR_INTOCC 0x00000080 ++/** OCTRLL 2 Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_OCTRLL2_ERR 0x00000040 ++/* Nothing ++#define ICU0_IM4_ISR_OCTRLL2_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_OCTRLL2_ERR_INTACK 0x00000040 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_OCTRLL2_ERR_INTOCC 0x00000040 ++/** OCTRLL 1 Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_OCTRLL1_ERR 0x00000020 ++/* Nothing ++#define ICU0_IM4_ISR_OCTRLL1_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_OCTRLL1_ERR_INTACK 0x00000020 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_OCTRLL1_ERR_INTOCC 0x00000020 ++/** OCTRLL 0 Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_OCTRLL0_ERR 0x00000010 ++/* Nothing ++#define ICU0_IM4_ISR_OCTRLL0_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_OCTRLL0_ERR_INTACK 0x00000010 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_OCTRLL0_ERR_INTOCC 0x00000010 ++/** ICTRLL 3 Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_ICTRLL3_ERR 0x00000008 ++/* Nothing ++#define ICU0_IM4_ISR_ICTRLL3_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_ICTRLL3_ERR_INTACK 0x00000008 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_ICTRLL3_ERR_INTOCC 0x00000008 ++/** ICTRLL 2 Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_ICTRLL2_ERR 0x00000004 ++/* Nothing ++#define ICU0_IM4_ISR_ICTRLL2_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_ICTRLL2_ERR_INTACK 0x00000004 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_ICTRLL2_ERR_INTOCC 0x00000004 ++/** ICTRLL 1 Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_ICTRLL1_ERR 0x00000002 ++/* Nothing ++#define ICU0_IM4_ISR_ICTRLL1_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_ICTRLL1_ERR_INTACK 0x00000002 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_ICTRLL1_ERR_INTOCC 0x00000002 ++/** ICTRLL 0 Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_ICTRLL0_ERR 0x00000001 ++/* Nothing ++#define ICU0_IM4_ISR_ICTRLL0_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_ICTRLL0_ERR_INTACK 0x00000001 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_ICTRLL0_ERR_INTOCC 0x00000001 ++ ++/* Fields of "IM4 Interrupt Enable Register" */ ++/** VPE0 Performance Monitoring Counter Interrupt ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_VPE0_PMCIR 0x80000000 ++/* Disable ++#define ICU0_IM4_IER_VPE0_PMCIR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_VPE0_PMCIR_EN 0x80000000 ++/** VPE0 Error Level Flag Interrupt ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_VPE0_ERL 0x40000000 ++/* Disable ++#define ICU0_IM4_IER_VPE0_ERL_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_VPE0_ERL_EN 0x40000000 ++/** VPE0 Exception Level Flag Interrupt ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_VPE0_EXL 0x20000000 ++/* Disable ++#define ICU0_IM4_IER_VPE0_EXL_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_VPE0_EXL_EN 0x20000000 ++/** MPS Bin. Sem Interrupt to VPE0 ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_MPS_IR8 0x00400000 ++/* Disable ++#define ICU0_IM4_IER_MPS_IR8_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_MPS_IR8_EN 0x00400000 ++/** MPS Global Interrupt to VPE0 ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_MPS_IR7 0x00200000 ++/* Disable ++#define ICU0_IM4_IER_MPS_IR7_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_MPS_IR7_EN 0x00200000 ++/** MPS Status Interrupt #6 (VPE1 to VPE0) ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_MPS_IR6 0x00100000 ++/* Disable ++#define ICU0_IM4_IER_MPS_IR6_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_MPS_IR6_EN 0x00100000 ++/** MPS Status Interrupt #5 (VPE1 to VPE0) ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_MPS_IR5 0x00080000 ++/* Disable ++#define ICU0_IM4_IER_MPS_IR5_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_MPS_IR5_EN 0x00080000 ++/** MPS Status Interrupt #4 (VPE1 to VPE0) ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_MPS_IR4 0x00040000 ++/* Disable ++#define ICU0_IM4_IER_MPS_IR4_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_MPS_IR4_EN 0x00040000 ++/** MPS Status Interrupt #3 (VPE1 to VPE0) ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_MPS_IR3 0x00020000 ++/* Disable ++#define ICU0_IM4_IER_MPS_IR3_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_MPS_IR3_EN 0x00020000 ++/** MPS Status Interrupt #2 (VPE1 to VPE0) ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_MPS_IR2 0x00010000 ++/* Disable ++#define ICU0_IM4_IER_MPS_IR2_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_MPS_IR2_EN 0x00010000 ++/** MPS Status Interrupt #1 (VPE1 to VPE0) ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_MPS_IR1 0x00008000 ++/* Disable ++#define ICU0_IM4_IER_MPS_IR1_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_MPS_IR1_EN 0x00008000 ++/** MPS Status Interrupt #0 (VPE1 to VPE0) ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_MPS_IR0 0x00004000 ++/* Disable ++#define ICU0_IM4_IER_MPS_IR0_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_MPS_IR0_EN 0x00004000 ++/** TMU Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_TMU_ERR 0x00001000 ++/* Disable ++#define ICU0_IM4_IER_TMU_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_TMU_ERR_EN 0x00001000 ++/** FSQM Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_FSQM_ERR 0x00000800 ++/* Disable ++#define ICU0_IM4_IER_FSQM_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_FSQM_ERR_EN 0x00000800 ++/** IQM Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_IQM_ERR 0x00000400 ++/* Disable ++#define ICU0_IM4_IER_IQM_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_IQM_ERR_EN 0x00000400 ++/** OCTRLG Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_OCTRLG_ERR 0x00000200 ++/* Disable ++#define ICU0_IM4_IER_OCTRLG_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_OCTRLG_ERR_EN 0x00000200 ++/** ICTRLG Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_ICTRLG_ERR 0x00000100 ++/* Disable ++#define ICU0_IM4_IER_ICTRLG_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_ICTRLG_ERR_EN 0x00000100 ++/** OCTRLL 3 Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_OCTRLL3_ERR 0x00000080 ++/* Disable ++#define ICU0_IM4_IER_OCTRLL3_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_OCTRLL3_ERR_EN 0x00000080 ++/** OCTRLL 2 Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_OCTRLL2_ERR 0x00000040 ++/* Disable ++#define ICU0_IM4_IER_OCTRLL2_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_OCTRLL2_ERR_EN 0x00000040 ++/** OCTRLL 1 Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_OCTRLL1_ERR 0x00000020 ++/* Disable ++#define ICU0_IM4_IER_OCTRLL1_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_OCTRLL1_ERR_EN 0x00000020 ++/** OCTRLL 0 Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_OCTRLL0_ERR 0x00000010 ++/* Disable ++#define ICU0_IM4_IER_OCTRLL0_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_OCTRLL0_ERR_EN 0x00000010 ++/** ICTRLL 3 Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_ICTRLL3_ERR 0x00000008 ++/* Disable ++#define ICU0_IM4_IER_ICTRLL3_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_ICTRLL3_ERR_EN 0x00000008 ++/** ICTRLL 2 Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_ICTRLL2_ERR 0x00000004 ++/* Disable ++#define ICU0_IM4_IER_ICTRLL2_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_ICTRLL2_ERR_EN 0x00000004 ++/** ICTRLL 1 Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_ICTRLL1_ERR 0x00000002 ++/* Disable ++#define ICU0_IM4_IER_ICTRLL1_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_ICTRLL1_ERR_EN 0x00000002 ++/** ICTRLL 0 Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_ICTRLL0_ERR 0x00000001 ++/* Disable ++#define ICU0_IM4_IER_ICTRLL0_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_ICTRLL0_ERR_EN 0x00000001 ++ ++/* Fields of "IM4 Interrupt Output Status Register" */ ++/** VPE0 Performance Monitoring Counter Interrupt ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_VPE0_PMCIR 0x80000000 ++/* Nothing ++#define ICU0_IM4_IOSR_VPE0_PMCIR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_VPE0_PMCIR_INTOCC 0x80000000 ++/** VPE0 Error Level Flag Interrupt ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_VPE0_ERL 0x40000000 ++/* Nothing ++#define ICU0_IM4_IOSR_VPE0_ERL_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_VPE0_ERL_INTOCC 0x40000000 ++/** VPE0 Exception Level Flag Interrupt ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_VPE0_EXL 0x20000000 ++/* Nothing ++#define ICU0_IM4_IOSR_VPE0_EXL_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_VPE0_EXL_INTOCC 0x20000000 ++/** MPS Bin. Sem Interrupt to VPE0 ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_MPS_IR8 0x00400000 ++/* Nothing ++#define ICU0_IM4_IOSR_MPS_IR8_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_MPS_IR8_INTOCC 0x00400000 ++/** MPS Global Interrupt to VPE0 ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_MPS_IR7 0x00200000 ++/* Nothing ++#define ICU0_IM4_IOSR_MPS_IR7_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_MPS_IR7_INTOCC 0x00200000 ++/** MPS Status Interrupt #6 (VPE1 to VPE0) ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_MPS_IR6 0x00100000 ++/* Nothing ++#define ICU0_IM4_IOSR_MPS_IR6_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_MPS_IR6_INTOCC 0x00100000 ++/** MPS Status Interrupt #5 (VPE1 to VPE0) ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_MPS_IR5 0x00080000 ++/* Nothing ++#define ICU0_IM4_IOSR_MPS_IR5_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_MPS_IR5_INTOCC 0x00080000 ++/** MPS Status Interrupt #4 (VPE1 to VPE0) ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_MPS_IR4 0x00040000 ++/* Nothing ++#define ICU0_IM4_IOSR_MPS_IR4_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_MPS_IR4_INTOCC 0x00040000 ++/** MPS Status Interrupt #3 (VPE1 to VPE0) ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_MPS_IR3 0x00020000 ++/* Nothing ++#define ICU0_IM4_IOSR_MPS_IR3_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_MPS_IR3_INTOCC 0x00020000 ++/** MPS Status Interrupt #2 (VPE1 to VPE0) ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_MPS_IR2 0x00010000 ++/* Nothing ++#define ICU0_IM4_IOSR_MPS_IR2_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_MPS_IR2_INTOCC 0x00010000 ++/** MPS Status Interrupt #1 (VPE1 to VPE0) ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_MPS_IR1 0x00008000 ++/* Nothing ++#define ICU0_IM4_IOSR_MPS_IR1_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_MPS_IR1_INTOCC 0x00008000 ++/** MPS Status Interrupt #0 (VPE1 to VPE0) ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_MPS_IR0 0x00004000 ++/* Nothing ++#define ICU0_IM4_IOSR_MPS_IR0_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_MPS_IR0_INTOCC 0x00004000 ++/** TMU Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_TMU_ERR 0x00001000 ++/* Nothing ++#define ICU0_IM4_IOSR_TMU_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_TMU_ERR_INTOCC 0x00001000 ++/** FSQM Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_FSQM_ERR 0x00000800 ++/* Nothing ++#define ICU0_IM4_IOSR_FSQM_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_FSQM_ERR_INTOCC 0x00000800 ++/** IQM Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_IQM_ERR 0x00000400 ++/* Nothing ++#define ICU0_IM4_IOSR_IQM_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_IQM_ERR_INTOCC 0x00000400 ++/** OCTRLG Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_OCTRLG_ERR 0x00000200 ++/* Nothing ++#define ICU0_IM4_IOSR_OCTRLG_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_OCTRLG_ERR_INTOCC 0x00000200 ++/** ICTRLG Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_ICTRLG_ERR 0x00000100 ++/* Nothing ++#define ICU0_IM4_IOSR_ICTRLG_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_ICTRLG_ERR_INTOCC 0x00000100 ++/** OCTRLL 3 Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_OCTRLL3_ERR 0x00000080 ++/* Nothing ++#define ICU0_IM4_IOSR_OCTRLL3_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_OCTRLL3_ERR_INTOCC 0x00000080 ++/** OCTRLL 2 Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_OCTRLL2_ERR 0x00000040 ++/* Nothing ++#define ICU0_IM4_IOSR_OCTRLL2_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_OCTRLL2_ERR_INTOCC 0x00000040 ++/** OCTRLL 1 Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_OCTRLL1_ERR 0x00000020 ++/* Nothing ++#define ICU0_IM4_IOSR_OCTRLL1_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_OCTRLL1_ERR_INTOCC 0x00000020 ++/** OCTRLL 0 Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_OCTRLL0_ERR 0x00000010 ++/* Nothing ++#define ICU0_IM4_IOSR_OCTRLL0_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_OCTRLL0_ERR_INTOCC 0x00000010 ++/** ICTRLL 3 Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_ICTRLL3_ERR 0x00000008 ++/* Nothing ++#define ICU0_IM4_IOSR_ICTRLL3_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_ICTRLL3_ERR_INTOCC 0x00000008 ++/** ICTRLL 2 Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_ICTRLL2_ERR 0x00000004 ++/* Nothing ++#define ICU0_IM4_IOSR_ICTRLL2_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_ICTRLL2_ERR_INTOCC 0x00000004 ++/** ICTRLL 1 Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_ICTRLL1_ERR 0x00000002 ++/* Nothing ++#define ICU0_IM4_IOSR_ICTRLL1_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_ICTRLL1_ERR_INTOCC 0x00000002 ++/** ICTRLL 0 Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_ICTRLL0_ERR 0x00000001 ++/* Nothing ++#define ICU0_IM4_IOSR_ICTRLL0_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_ICTRLL0_ERR_INTOCC 0x00000001 ++ ++/* Fields of "IM4 Interrupt Request Set Register" */ ++/** VPE0 Performance Monitoring Counter Interrupt ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_VPE0_PMCIR 0x80000000 ++/** VPE0 Error Level Flag Interrupt ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_VPE0_ERL 0x40000000 ++/** VPE0 Exception Level Flag Interrupt ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_VPE0_EXL 0x20000000 ++/** MPS Bin. Sem Interrupt to VPE0 ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_MPS_IR8 0x00400000 ++/** MPS Global Interrupt to VPE0 ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_MPS_IR7 0x00200000 ++/** MPS Status Interrupt #6 (VPE1 to VPE0) ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_MPS_IR6 0x00100000 ++/** MPS Status Interrupt #5 (VPE1 to VPE0) ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_MPS_IR5 0x00080000 ++/** MPS Status Interrupt #4 (VPE1 to VPE0) ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_MPS_IR4 0x00040000 ++/** MPS Status Interrupt #3 (VPE1 to VPE0) ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_MPS_IR3 0x00020000 ++/** MPS Status Interrupt #2 (VPE1 to VPE0) ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_MPS_IR2 0x00010000 ++/** MPS Status Interrupt #1 (VPE1 to VPE0) ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_MPS_IR1 0x00008000 ++/** MPS Status Interrupt #0 (VPE1 to VPE0) ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_MPS_IR0 0x00004000 ++/** TMU Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_TMU_ERR 0x00001000 ++/** FSQM Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_FSQM_ERR 0x00000800 ++/** IQM Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_IQM_ERR 0x00000400 ++/** OCTRLG Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_OCTRLG_ERR 0x00000200 ++/** ICTRLG Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_ICTRLG_ERR 0x00000100 ++/** OCTRLL 3 Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_OCTRLL3_ERR 0x00000080 ++/** OCTRLL 2 Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_OCTRLL2_ERR 0x00000040 ++/** OCTRLL 1 Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_OCTRLL1_ERR 0x00000020 ++/** OCTRLL 0 Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_OCTRLL0_ERR 0x00000010 ++/** ICTRLL 3 Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_ICTRLL3_ERR 0x00000008 ++/** ICTRLL 2 Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_ICTRLL2_ERR 0x00000004 ++/** ICTRLL 1 Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_ICTRLL1_ERR 0x00000002 ++/** ICTRLL 0 Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_ICTRLL0_ERR 0x00000001 ++ ++/* Fields of "IM4 Interrupt Mode Register" */ ++/** VPE0 Performance Monitoring Counter Interrupt ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_VPE0_PMCIR 0x80000000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_VPE0_PMCIR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_VPE0_PMCIR_DIR 0x80000000 ++/** VPE0 Error Level Flag Interrupt ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_VPE0_ERL 0x40000000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_VPE0_ERL_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_VPE0_ERL_DIR 0x40000000 ++/** VPE0 Exception Level Flag Interrupt ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_VPE0_EXL 0x20000000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_VPE0_EXL_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_VPE0_EXL_DIR 0x20000000 ++/** MPS Bin. Sem Interrupt to VPE0 ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR8 0x00400000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_MPS_IR8_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR8_DIR 0x00400000 ++/** MPS Global Interrupt to VPE0 ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR7 0x00200000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_MPS_IR7_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR7_DIR 0x00200000 ++/** MPS Status Interrupt #6 (VPE1 to VPE0) ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR6 0x00100000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_MPS_IR6_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR6_DIR 0x00100000 ++/** MPS Status Interrupt #5 (VPE1 to VPE0) ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR5 0x00080000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_MPS_IR5_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR5_DIR 0x00080000 ++/** MPS Status Interrupt #4 (VPE1 to VPE0) ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR4 0x00040000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_MPS_IR4_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR4_DIR 0x00040000 ++/** MPS Status Interrupt #3 (VPE1 to VPE0) ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR3 0x00020000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_MPS_IR3_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR3_DIR 0x00020000 ++/** MPS Status Interrupt #2 (VPE1 to VPE0) ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR2 0x00010000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_MPS_IR2_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR2_DIR 0x00010000 ++/** MPS Status Interrupt #1 (VPE1 to VPE0) ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR1 0x00008000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_MPS_IR1_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR1_DIR 0x00008000 ++/** MPS Status Interrupt #0 (VPE1 to VPE0) ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR0 0x00004000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_MPS_IR0_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR0_DIR 0x00004000 ++/** TMU Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_TMU_ERR 0x00001000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_TMU_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_TMU_ERR_DIR 0x00001000 ++/** FSQM Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_FSQM_ERR 0x00000800 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_FSQM_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_FSQM_ERR_DIR 0x00000800 ++/** IQM Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_IQM_ERR 0x00000400 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_IQM_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_IQM_ERR_DIR 0x00000400 ++/** OCTRLG Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_OCTRLG_ERR 0x00000200 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_OCTRLG_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_OCTRLG_ERR_DIR 0x00000200 ++/** ICTRLG Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_ICTRLG_ERR 0x00000100 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_ICTRLG_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_ICTRLG_ERR_DIR 0x00000100 ++/** OCTRLL 3 Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_OCTRLL3_ERR 0x00000080 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_OCTRLL3_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_OCTRLL3_ERR_DIR 0x00000080 ++/** OCTRLL 2 Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_OCTRLL2_ERR 0x00000040 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_OCTRLL2_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_OCTRLL2_ERR_DIR 0x00000040 ++/** OCTRLL 1 Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_OCTRLL1_ERR 0x00000020 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_OCTRLL1_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_OCTRLL1_ERR_DIR 0x00000020 ++/** OCTRLL 0 Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_OCTRLL0_ERR 0x00000010 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_OCTRLL0_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_OCTRLL0_ERR_DIR 0x00000010 ++/** ICTRLL 3 Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_ICTRLL3_ERR 0x00000008 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_ICTRLL3_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_ICTRLL3_ERR_DIR 0x00000008 ++/** ICTRLL 2 Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_ICTRLL2_ERR 0x00000004 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_ICTRLL2_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_ICTRLL2_ERR_DIR 0x00000004 ++/** ICTRLL 1 Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_ICTRLL1_ERR 0x00000002 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_ICTRLL1_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_ICTRLL1_ERR_DIR 0x00000002 ++/** ICTRLL 0 Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_ICTRLL0_ERR 0x00000001 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_ICTRLL0_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_ICTRLL0_ERR_DIR 0x00000001 ++ ++/* Fields of "ICU Interrupt Vector Register (5 bit variant)" */ ++/** IM4 Interrupt Vector Value ++ Returns the highest priority pending interrupt vector. */ ++#define ICU0_ICU_IVEC_IM4_vec_MASK 0x01F00000 ++/** field offset */ ++#define ICU0_ICU_IVEC_IM4_vec_OFFSET 20 ++/** Interrupt pending at bit 31 or no pending interrupt */ ++#define ICU0_ICU_IVEC_IM4_vec_NOINTorBit31 0x00000000 ++/** Interrupt pending at bit 0. */ ++#define ICU0_ICU_IVEC_IM4_vec_BIT0 0x00100000 ++/** Interrupt pending at bit 1. */ ++#define ICU0_ICU_IVEC_IM4_vec_BIT1 0x00200000 ++/** Interrupt pending at bit 30. */ ++#define ICU0_ICU_IVEC_IM4_vec_BIT30 0x01F00000 ++/** IM3 Interrupt Vector Value ++ Returns the highest priority pending interrupt vector. */ ++#define ICU0_ICU_IVEC_IM3_vec_MASK 0x000F8000 ++/** field offset */ ++#define ICU0_ICU_IVEC_IM3_vec_OFFSET 15 ++/** Interrupt pending at bit 31 or no pending interrupt */ ++#define ICU0_ICU_IVEC_IM3_vec_NOINTorBit31 0x00000000 ++/** Interrupt pending at bit 0. */ ++#define ICU0_ICU_IVEC_IM3_vec_BIT0 0x00008000 ++/** Interrupt pending at bit 1. */ ++#define ICU0_ICU_IVEC_IM3_vec_BIT1 0x00010000 ++/** Interrupt pending at bit 30. */ ++#define ICU0_ICU_IVEC_IM3_vec_BIT30 0x000F8000 ++/** IM2 Interrupt Vector Value ++ Returns the highest priority pending interrupt vector. */ ++#define ICU0_ICU_IVEC_IM2_vec_MASK 0x00007C00 ++/** field offset */ ++#define ICU0_ICU_IVEC_IM2_vec_OFFSET 10 ++/** Interrupt pending at bit 31 or no pending interrupt */ ++#define ICU0_ICU_IVEC_IM2_vec_NOINTorBit31 0x00000000 ++/** Interrupt pending at bit 0. */ ++#define ICU0_ICU_IVEC_IM2_vec_BIT0 0x00000400 ++/** Interrupt pending at bit 1. */ ++#define ICU0_ICU_IVEC_IM2_vec_BIT1 0x00000800 ++/** Interrupt pending at bit 30. */ ++#define ICU0_ICU_IVEC_IM2_vec_BIT30 0x00007C00 ++/** IM1 Interrupt Vector Value ++ Returns the highest priority pending interrupt vector. */ ++#define ICU0_ICU_IVEC_IM1_vec_MASK 0x000003E0 ++/** field offset */ ++#define ICU0_ICU_IVEC_IM1_vec_OFFSET 5 ++/** Interrupt pending at bit 31 or no pending interrupt */ ++#define ICU0_ICU_IVEC_IM1_vec_NOINTorBit31 0x00000000 ++/** Interrupt pending at bit 0. */ ++#define ICU0_ICU_IVEC_IM1_vec_BIT0 0x00000020 ++/** Interrupt pending at bit 1. */ ++#define ICU0_ICU_IVEC_IM1_vec_BIT1 0x00000040 ++/** Interrupt pending at bit 30. */ ++#define ICU0_ICU_IVEC_IM1_vec_BIT30 0x000003E0 ++/** IM0 Interrupt Vector Value ++ Returns the highest priority pending interrupt vector. */ ++#define ICU0_ICU_IVEC_IM0_vec_MASK 0x0000001F ++/** field offset */ ++#define ICU0_ICU_IVEC_IM0_vec_OFFSET 0 ++/** Interrupt pending at bit 31 or no pending interrupt */ ++#define ICU0_ICU_IVEC_IM0_vec_NOINTorBit31 0x00000000 ++/** Interrupt pending at bit 0. */ ++#define ICU0_ICU_IVEC_IM0_vec_BIT0 0x00000001 ++/** Interrupt pending at bit 1. */ ++#define ICU0_ICU_IVEC_IM0_vec_BIT1 0x00000002 ++/** Interrupt pending at bit 30. */ ++#define ICU0_ICU_IVEC_IM0_vec_BIT30 0x0000001F ++ ++/* Fields of "ICU Interrupt Vector Register (6 bit variant)" */ ++/** IM4 Interrupt Vector Value ++ Returns the highest priority pending interrupt vector. */ ++#define ICU0_ICU_IVEC_6_IM4_vec_MASK 0x3F000000 ++/** field offset */ ++#define ICU0_ICU_IVEC_6_IM4_vec_OFFSET 24 ++/** No pending interrupt */ ++#define ICU0_ICU_IVEC_6_IM4_vec_NOINT 0x00000000 ++/** Interrupt pending at bit 0. */ ++#define ICU0_ICU_IVEC_6_IM4_vec_BIT0 0x01000000 ++/** Interrupt pending at bit 1. */ ++#define ICU0_ICU_IVEC_6_IM4_vec_BIT1 0x02000000 ++/** Interrupt pending at bit 30. */ ++#define ICU0_ICU_IVEC_6_IM4_vec_BIT30 0x1F000000 ++/** Interrupt pending at bit 31. */ ++#define ICU0_ICU_IVEC_6_IM4_vec_BIT31 0x20000000 ++/** IM3 Interrupt Vector Value ++ Returns the highest priority pending interrupt vector. */ ++#define ICU0_ICU_IVEC_6_IM3_vec_MASK 0x00FC0000 ++/** field offset */ ++#define ICU0_ICU_IVEC_6_IM3_vec_OFFSET 18 ++/** No pending interrupt */ ++#define ICU0_ICU_IVEC_6_IM3_vec_NOINT 0x00000000 ++/** Interrupt pending at bit 0. */ ++#define ICU0_ICU_IVEC_6_IM3_vec_BIT0 0x00040000 ++/** Interrupt pending at bit 1. */ ++#define ICU0_ICU_IVEC_6_IM3_vec_BIT1 0x00080000 ++/** Interrupt pending at bit 30. */ ++#define ICU0_ICU_IVEC_6_IM3_vec_BIT30 0x007C0000 ++/** Interrupt pending at bit 31. */ ++#define ICU0_ICU_IVEC_6_IM3_vec_BIT31 0x00800000 ++/** IM2 Interrupt Vector Value ++ Returns the highest priority pending interrupt vector. */ ++#define ICU0_ICU_IVEC_6_IM2_vec_MASK 0x0003F000 ++/** field offset */ ++#define ICU0_ICU_IVEC_6_IM2_vec_OFFSET 12 ++/** No pending interrupt */ ++#define ICU0_ICU_IVEC_6_IM2_vec_NOINT 0x00000000 ++/** Interrupt pending at bit 0. */ ++#define ICU0_ICU_IVEC_6_IM2_vec_BIT0 0x00001000 ++/** Interrupt pending at bit 1. */ ++#define ICU0_ICU_IVEC_6_IM2_vec_BIT1 0x00002000 ++/** Interrupt pending at bit 30. */ ++#define ICU0_ICU_IVEC_6_IM2_vec_BIT30 0x0001F000 ++/** Interrupt pending at bit 31. */ ++#define ICU0_ICU_IVEC_6_IM2_vec_BIT31 0x00020000 ++/** IM1 Interrupt Vector Value ++ Returns the highest priority pending interrupt vector. */ ++#define ICU0_ICU_IVEC_6_IM1_vec_MASK 0x00000FC0 ++/** field offset */ ++#define ICU0_ICU_IVEC_6_IM1_vec_OFFSET 6 ++/** No pending interrupt */ ++#define ICU0_ICU_IVEC_6_IM1_vec_NOINT 0x00000000 ++/** Interrupt pending at bit 0. */ ++#define ICU0_ICU_IVEC_6_IM1_vec_BIT0 0x00000040 ++/** Interrupt pending at bit 1. */ ++#define ICU0_ICU_IVEC_6_IM1_vec_BIT1 0x00000080 ++/** Interrupt pending at bit 30. */ ++#define ICU0_ICU_IVEC_6_IM1_vec_BIT30 0x000007C0 ++/** Interrupt pending at bit 31. */ ++#define ICU0_ICU_IVEC_6_IM1_vec_BIT31 0x00000800 ++/** IM0 Interrupt Vector Value ++ Returns the highest priority pending interrupt vector. */ ++#define ICU0_ICU_IVEC_6_IM0_vec_MASK 0x0000003F ++/** field offset */ ++#define ICU0_ICU_IVEC_6_IM0_vec_OFFSET 0 ++/** No pending interrupt */ ++#define ICU0_ICU_IVEC_6_IM0_vec_NOINT 0x00000000 ++/** Interrupt pending at bit 0. */ ++#define ICU0_ICU_IVEC_6_IM0_vec_BIT0 0x00000001 ++/** Interrupt pending at bit 1. */ ++#define ICU0_ICU_IVEC_6_IM0_vec_BIT1 0x00000002 ++/** Interrupt pending at bit 30. */ ++#define ICU0_ICU_IVEC_6_IM0_vec_BIT30 0x0000001F ++/** Interrupt pending at bit 31. */ ++#define ICU0_ICU_IVEC_6_IM0_vec_BIT31 0x00000020 ++ ++/*! @} */ /* ICU0_REGISTER */ ++ ++#endif /* _icu0_reg_h */ +diff --git a/arch/mips/include/asm/mach-lantiq/falcon/status_reg.h b/arch/mips/include/asm/mach-lantiq/falcon/status_reg.h +new file mode 100644 +index 0000000..dfab030 +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/status_reg.h +@@ -0,0 +1,529 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++ ++#ifndef _status_reg_h ++#define _status_reg_h ++ ++/** \addtogroup STATUS_REGISTER ++ @{ ++*/ ++/* access macros */ ++#define status_r32(reg) reg_r32(&status->reg) ++#define status_w32(val, reg) reg_w32(val, &status->reg) ++#define status_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &status->reg) ++#define status_r32_table(reg, idx) reg_r32_table(status->reg, idx) ++#define status_w32_table(val, reg, idx) reg_w32_table(val, status->reg, idx) ++#define status_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, status->reg, idx) ++#define status_adr_table(reg, idx) adr_table(status->reg, idx) ++ ++ ++/** STATUS register structure */ ++struct gpon_reg_status ++{ ++ /** Reserved */ ++ unsigned int res_0[3]; /* 0x00000000 */ ++ /** Chip Identification Register */ ++ unsigned int chipid; /* 0x0000000C */ ++ /** Chip Location Register ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int chiploc; /* 0x00000010 */ ++ /** Redundancy register ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int red0; /* 0x00000014 */ ++ /** Redundancy register ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int red1; /* 0x00000018 */ ++ /** Redundancy register ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int red2; /* 0x0000001C */ ++ /** Redundancy register ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int red3; /* 0x00000020 */ ++ /** Redundancy register ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int red4; /* 0x00000024 */ ++ /** Redundancy register ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int red5; /* 0x00000028 */ ++ /** Redundancy register ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int red6; /* 0x0000002C */ ++ /** Redundancy register ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int red7; /* 0x00000030 */ ++ /** Redundancy register ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int red8; /* 0x00000034 */ ++ /** SPARE fuse register 0 ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int fuse0; /* 0x00000038 */ ++ /** Fuses for Analog modules ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int analog; /* 0x0000003C */ ++ /** Configuration fuses for drivers and pll ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int config; /* 0x00000040 */ ++ /** SPARE fuse register 1 ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int fuse1; /* 0x00000044 */ ++ /** Configuration for sbs0 rambist */ ++ unsigned int mbcfg; /* 0x00000048 */ ++ /** sbs0 bist result and debug data */ ++ unsigned int mbdata; /* 0x0000004C */ ++ /** Reserved */ ++ unsigned int res_1[12]; /* 0x00000050 */ ++}; ++ ++ ++/* Fields of "Chip Identification Register" */ ++/** Chip Version Number ++ Version number */ ++#define STATUS_CHIPID_VERSION_MASK 0xF0000000 ++/** field offset */ ++#define STATUS_CHIPID_VERSION_OFFSET 28 ++/** Part Number, Constant Part ++ The Part Number is fixed to 016Bhex. */ ++#define STATUS_CHIPID_PARTNR_MASK 0x0FFFF000 ++/** field offset */ ++#define STATUS_CHIPID_PARTNR_OFFSET 12 ++/** Manufacturer ID ++ The value of bit field MANID is fixed to 41hex as configured in the JTAG ID register. The JEDEC normalized manufacturer code for Infineon Technologies is C1hex */ ++#define STATUS_CHIPID_MANID_MASK 0x00000FFE ++/** field offset */ ++#define STATUS_CHIPID_MANID_OFFSET 1 ++/** Constant bit ++ The value of bit field CONST1 is fixed to 1hex */ ++#define STATUS_CHIPID_CONST1 0x00000001 ++ ++/* Fields of "Chip Location Register" */ ++/** Chip Lot ID */ ++#define STATUS_CHIPLOC_CHIPLOT_MASK 0xFFFF0000 ++/** field offset */ ++#define STATUS_CHIPLOC_CHIPLOT_OFFSET 16 ++/** Chip X Coordinate */ ++#define STATUS_CHIPLOC_CHIPX_MASK 0x0000FF00 ++/** field offset */ ++#define STATUS_CHIPLOC_CHIPX_OFFSET 8 ++/** Chip Y Coordinate */ ++#define STATUS_CHIPLOC_CHIPY_MASK 0x000000FF ++/** field offset */ ++#define STATUS_CHIPLOC_CHIPY_OFFSET 0 ++ ++/* Fields of "Redundancy register" */ ++/** Redundancy ++ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ ++#define STATUS_RED0_REDUNDANCY_MASK 0x0003FFFF ++/** field offset */ ++#define STATUS_RED0_REDUNDANCY_OFFSET 0 ++ ++/* Fields of "Redundancy register" */ ++/** Redundancy ++ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ ++#define STATUS_RED1_REDUNDANCY_MASK 0x0003FFFF ++/** field offset */ ++#define STATUS_RED1_REDUNDANCY_OFFSET 0 ++ ++/* Fields of "Redundancy register" */ ++/** Redundancy ++ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ ++#define STATUS_RED2_REDUNDANCY_MASK 0x0003FFFF ++/** field offset */ ++#define STATUS_RED2_REDUNDANCY_OFFSET 0 ++ ++/* Fields of "Redundancy register" */ ++/** Redundancy ++ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ ++#define STATUS_RED3_REDUNDANCY_MASK 0x0003FFFF ++/** field offset */ ++#define STATUS_RED3_REDUNDANCY_OFFSET 0 ++ ++/* Fields of "Redundancy register" */ ++/** Redundancy ++ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ ++#define STATUS_RED4_REDUNDANCY_MASK 0x0003FFFF ++/** field offset */ ++#define STATUS_RED4_REDUNDANCY_OFFSET 0 ++ ++/* Fields of "Redundancy register" */ ++/** Redundancy ++ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ ++#define STATUS_RED5_REDUNDANCY_MASK 0x0003FFFF ++/** field offset */ ++#define STATUS_RED5_REDUNDANCY_OFFSET 0 ++ ++/* Fields of "Redundancy register" */ ++/** Redundancy ++ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ ++#define STATUS_RED6_REDUNDANCY_MASK 0x0003FFFF ++/** field offset */ ++#define STATUS_RED6_REDUNDANCY_OFFSET 0 ++ ++/* Fields of "Redundancy register" */ ++/** Redundancy ++ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ ++#define STATUS_RED7_REDUNDANCY_MASK 0x0003FFFF ++/** field offset */ ++#define STATUS_RED7_REDUNDANCY_OFFSET 0 ++ ++/* Fields of "Redundancy register" */ ++/** Redundancy ++ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ ++#define STATUS_RED8_REDUNDANCY_MASK 0x0003FFFF ++/** field offset */ ++#define STATUS_RED8_REDUNDANCY_OFFSET 0 ++ ++/* Fields of "SPARE fuse register 0" */ ++/** Soft fuse control ++ Controls whether the status block is in its softfused state or not. In the softfused state the values written via software are active effective. */ ++#define STATUS_FUSE0_SFC 0x80000000 ++/* Not selected ++#define STATUS_FUSE0_SFC_NSEL 0x00000000 */ ++/** Selected */ ++#define STATUS_FUSE0_SFC_SEL 0x80000000 ++/** Soft control MBCFG ++ Controls whether mbist configuration can be overwritten or not from subsystem. If not selected jtag mbcfg register is source for software mbist configuration */ ++#define STATUS_FUSE0_SC_MBCFG 0x40000000 ++/* Not selected ++#define STATUS_FUSE0_SC_MBCFG_NSEL 0x00000000 */ ++/** Selected */ ++#define STATUS_FUSE0_SC_MBCFG_SEL 0x40000000 ++/** spare fuse0 ++ eFuses not assigned to hw/sw, can be used for future applications */ ++#define STATUS_FUSE0_F0_MASK 0x3C000000 ++/** field offset */ ++#define STATUS_FUSE0_F0_OFFSET 26 ++/** VCALMM20 Voltage Reference ++ Voltage Reference for calibration via R and constant current (20 uA) */ ++#define STATUS_FUSE0_VCALMM20_MASK 0x03F00000 ++/** field offset */ ++#define STATUS_FUSE0_VCALMM20_OFFSET 20 ++/** VCALMM100 Voltage Reference ++ Voltage Reference for calibration via R and constant current (100 uA) */ ++#define STATUS_FUSE0_VCALMM100_MASK 0x000FC000 ++/** field offset */ ++#define STATUS_FUSE0_VCALMM100_OFFSET 14 ++/** VCALMM400 Voltage Reference ++ Voltage Reference for calibration via R and constant current (400 uA) */ ++#define STATUS_FUSE0_VCALMM400_MASK 0x00003F00 ++/** field offset */ ++#define STATUS_FUSE0_VCALMM400_OFFSET 8 ++/** RCALMM R error correction ++ The resistance deviation from ideal R (1000 Ohm) */ ++#define STATUS_FUSE0_RCALMM_MASK 0x000000FF ++/** field offset */ ++#define STATUS_FUSE0_RCALMM_OFFSET 0 ++ ++/* Fields of "Fuses for Analog modules" */ ++/** reserved Analog eFuses ++ Reserved Register contains information stored in eFuses needed for the analog modules */ ++#define STATUS_ANALOG_A0_MASK 0xFF000000 ++/** field offset */ ++#define STATUS_ANALOG_A0_OFFSET 24 ++/** Absolut Temperature ++ Temperature ERROR */ ++#define STATUS_ANALOG_TEMPMM_MASK 0x00FC0000 ++/** field offset */ ++#define STATUS_ANALOG_TEMPMM_OFFSET 18 ++/** Bias Voltage Generation ++ temperature dependency */ ++#define STATUS_ANALOG_TBGP_MASK 0x00038000 ++/** field offset */ ++#define STATUS_ANALOG_TBGP_OFFSET 15 ++/** Bias Voltage Generation ++ voltage dependency */ ++#define STATUS_ANALOG_VBGP_MASK 0x00007000 ++/** field offset */ ++#define STATUS_ANALOG_VBGP_OFFSET 12 ++/** Bias Current Generation */ ++#define STATUS_ANALOG_IREFBGP_MASK 0x00000F00 ++/** field offset */ ++#define STATUS_ANALOG_IREFBGP_OFFSET 8 ++/** Drive DAC Gain */ ++#define STATUS_ANALOG_GAINDRIVEDAC_MASK 0x000000F0 ++/** field offset */ ++#define STATUS_ANALOG_GAINDRIVEDAC_OFFSET 4 ++/** BIAS DAC Gain */ ++#define STATUS_ANALOG_GAINBIASDAC_MASK 0x0000000F ++/** field offset */ ++#define STATUS_ANALOG_GAINBIASDAC_OFFSET 0 ++ ++/* Fields of "Configuration fuses for drivers and pll" */ ++/** ddr PU driver ++ ddr pullup driver strength adjustment */ ++#define STATUS_CONFIG_DDRPU_MASK 0xC0000000 ++/** field offset */ ++#define STATUS_CONFIG_DDRPU_OFFSET 30 ++/** ddr PD driver ++ ddr pulldown driver strength adjustment */ ++#define STATUS_CONFIG_DDRPD_MASK 0x30000000 ++/** field offset */ ++#define STATUS_CONFIG_DDRPD_OFFSET 28 ++/** Authentification Unit enable ++ This bit can only be set via eFuse and enables the authentification unit. */ ++#define STATUS_CONFIG_SHA1EN 0x08000000 ++/* Not selected ++#define STATUS_CONFIG_SHA1EN_NSEL 0x00000000 */ ++/** Selected */ ++#define STATUS_CONFIG_SHA1EN_SEL 0x08000000 ++/** Encryption Unit enable ++ This bit can only be set via eFuse and enables the encryption unit. */ ++#define STATUS_CONFIG_AESEN 0x04000000 ++/* Not selected ++#define STATUS_CONFIG_AESEN_NSEL 0x00000000 */ ++/** Selected */ ++#define STATUS_CONFIG_AESEN_SEL 0x04000000 ++/** Subversion Number ++ The subversion number has no direct effect on hardware functions. It is used to provide another chip version number that is fixed in hardware and can be read out by software. In this way different product packages consisting of GPON_MODEM and software can be defined for example */ ++#define STATUS_CONFIG_SUBVERS_MASK 0x03C00000 ++/** field offset */ ++#define STATUS_CONFIG_SUBVERS_OFFSET 22 ++/** PLL settings ++ PLL settings for infrastructure block */ ++#define STATUS_CONFIG_PLLINFRA_MASK 0x003FF000 ++/** field offset */ ++#define STATUS_CONFIG_PLLINFRA_OFFSET 12 ++/** GPE frequency selection ++ Scaling down the GPE frequency for debugging purpose */ ++#define STATUS_CONFIG_GPEFREQ_MASK 0x00000C00 ++/** field offset */ ++#define STATUS_CONFIG_GPEFREQ_OFFSET 10 ++/** RM enable ++ Activates the Read Margin Settings defined in the RM Field, for all VIRAGE Memories except GPE */ ++#define STATUS_CONFIG_RME 0x00000200 ++/* Not selected ++#define STATUS_CONFIG_RME_NSEL 0x00000000 */ ++/** Selected */ ++#define STATUS_CONFIG_RME_SEL 0x00000200 ++/** RM settings ++ Read Marging Settings for all VIRAGE Memories except GPE */ ++#define STATUS_CONFIG_RM_MASK 0x000001E0 ++/** field offset */ ++#define STATUS_CONFIG_RM_OFFSET 5 ++/** RM enable for GPE Memories ++ Activates the Read Margin Settings defined in the RM Field */ ++#define STATUS_CONFIG_RMEGPE 0x00000010 ++/* Not selected ++#define STATUS_CONFIG_RMEGPE_NSEL 0x00000000 */ ++/** Selected */ ++#define STATUS_CONFIG_RMEGPE_SEL 0x00000010 ++/** RM settings for GPE Memories ++ Read Marging Settings for VIRAGE Memories in GPE module */ ++#define STATUS_CONFIG_RMGPE_MASK 0x0000000F ++/** field offset */ ++#define STATUS_CONFIG_RMGPE_OFFSET 0 ++ ++/* Fields of "SPARE fuse register 1" */ ++/** spare fuse1 ++ eFuses not assigned to hw/sw, can be used for future applications */ ++#define STATUS_FUSE1_F1_MASK 0xFFF00000 ++/** field offset */ ++#define STATUS_FUSE1_F1_OFFSET 20 ++/** DCDC DDR OFFSET ++ offset error sense path */ ++#define STATUS_FUSE1_OFFSETDDRDCDC_MASK 0x000F0000 ++/** field offset */ ++#define STATUS_FUSE1_OFFSETDDRDCDC_OFFSET 16 ++/** DCDC DDR GAIN ++ gain error sense path */ ++#define STATUS_FUSE1_GAINDDRDCDC_MASK 0x0000FC00 ++/** field offset */ ++#define STATUS_FUSE1_GAINDDRDCDC_OFFSET 10 ++/** DCDC APD OFFSET ++ offset error sense path */ ++#define STATUS_FUSE1_OFFSETAPDDCDC_MASK 0x000003C0 ++/** field offset */ ++#define STATUS_FUSE1_OFFSETAPDDCDC_OFFSET 6 ++/** DCDC APD GAIN ++ gain error sense path */ ++#define STATUS_FUSE1_GAINAPDDCDC_MASK 0x0000003F ++/** field offset */ ++#define STATUS_FUSE1_GAINAPDDCDC_OFFSET 0 ++ ++/* Fields of "Configuration for sbs0 rambist" */ ++/** Disable asc monitoring during boot-up ++ Bit is used to avoid asc output for reducing pattern count on testsystem */ ++#define STATUS_MBCFG_ASC_DBGDIS 0x01000000 ++/* Disable ++#define STATUS_MBCFG_ASC_DBGDIS_DIS 0x00000000 */ ++/** Enable */ ++#define STATUS_MBCFG_ASC_DBGDIS_EN 0x01000000 ++/** Descrambling Enable/Disable ++ Enables Address and Data Descrambling for internal Memory Test */ ++#define STATUS_MBCFG_DSC 0x00800000 ++/* Disable ++#define STATUS_MBCFG_DSC_DIS 0x00000000 */ ++/** Enable */ ++#define STATUS_MBCFG_DSC_EN 0x00800000 ++/** Enable repair mode ++ When bit is set redundancy repair mode is activated */ ++#define STATUS_MBCFG_REPAIR 0x00400000 ++/* Disable ++#define STATUS_MBCFG_REPAIR_DIS 0x00000000 */ ++/** Enable */ ++#define STATUS_MBCFG_REPAIR_EN 0x00400000 ++/** DEBUG Mode */ ++#define STATUS_MBCFG_DBG 0x00200000 ++/* Disable ++#define STATUS_MBCFG_DBG_DIS 0x00000000 */ ++/** Enable */ ++#define STATUS_MBCFG_DBG_EN 0x00200000 ++/** Retention Time ++ Length oft the Retention Time */ ++#define STATUS_MBCFG_RTIME_MASK 0x001C0000 ++/** field offset */ ++#define STATUS_MBCFG_RTIME_OFFSET 18 ++/** retention mode is switched off */ ++#define STATUS_MBCFG_RTIME_RET0 0x00000000 ++/** Retention time 50 ms */ ++#define STATUS_MBCFG_RTIME_RET50 0x00040000 ++/** Retention time 60 ms */ ++#define STATUS_MBCFG_RTIME_RET60 0x00080000 ++/** Retention time 70 ms */ ++#define STATUS_MBCFG_RTIME_RET70 0x000C0000 ++/** Retention time 80 ms */ ++#define STATUS_MBCFG_RTIME_RET80 0x00100000 ++/** Retention time 90 ms */ ++#define STATUS_MBCFG_RTIME_RET90 0x00140000 ++/** Retention time 1000 ms */ ++#define STATUS_MBCFG_RTIME_RET1000 0x00180000 ++/** Test ID ++ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ ++#define STATUS_MBCFG_TID_5_MASK 0x00038000 ++/** field offset */ ++#define STATUS_MBCFG_TID_5_OFFSET 15 ++/** No test is performed */ ++#define STATUS_MBCFG_TID_5_NONE 0x00000000 ++/** March test */ ++#define STATUS_MBCFG_TID_5_MARCH 0x00008000 ++/** Checkerboard test */ ++#define STATUS_MBCFG_TID_5_CHCK 0x00010000 ++/** Hammer test */ ++#define STATUS_MBCFG_TID_5_HAM 0x00018000 ++/** Address decoder test */ ++#define STATUS_MBCFG_TID_5_ADEC 0x00020000 ++/** Write mask byte test */ ++#define STATUS_MBCFG_TID_5_WMBYTE 0x00028000 ++/** Reserved */ ++#define STATUS_MBCFG_TID_5_RES 0x00030000 ++/** Test ID ++ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ ++#define STATUS_MBCFG_TID_4_MASK 0x00007000 ++/** field offset */ ++#define STATUS_MBCFG_TID_4_OFFSET 12 ++/** No test is performed */ ++#define STATUS_MBCFG_TID_4_NONE 0x00000000 ++/** March test */ ++#define STATUS_MBCFG_TID_4_MARCH 0x00001000 ++/** Checkerboard test */ ++#define STATUS_MBCFG_TID_4_CHCK 0x00002000 ++/** Hammer test */ ++#define STATUS_MBCFG_TID_4_HAM 0x00003000 ++/** Address decoder test */ ++#define STATUS_MBCFG_TID_4_ADEC 0x00004000 ++/** Write mask byte test */ ++#define STATUS_MBCFG_TID_4_WMBYTE 0x00005000 ++/** Reserved */ ++#define STATUS_MBCFG_TID_4_RES 0x00006000 ++/** Test ID ++ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ ++#define STATUS_MBCFG_TID_3_MASK 0x00000E00 ++/** field offset */ ++#define STATUS_MBCFG_TID_3_OFFSET 9 ++/** No test is performed */ ++#define STATUS_MBCFG_TID_3_NONE 0x00000000 ++/** March test */ ++#define STATUS_MBCFG_TID_3_MARCH 0x00000200 ++/** Checkerboard test */ ++#define STATUS_MBCFG_TID_3_CHCK 0x00000400 ++/** Hammer test */ ++#define STATUS_MBCFG_TID_3_HAM 0x00000600 ++/** Address decoder test */ ++#define STATUS_MBCFG_TID_3_ADEC 0x00000800 ++/** Write mask byte test */ ++#define STATUS_MBCFG_TID_3_WMBYTE 0x00000A00 ++/** Reserved */ ++#define STATUS_MBCFG_TID_3_RES 0x00000C00 ++/** Test ID ++ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ ++#define STATUS_MBCFG_TID_2_MASK 0x000001C0 ++/** field offset */ ++#define STATUS_MBCFG_TID_2_OFFSET 6 ++/** No test is performed */ ++#define STATUS_MBCFG_TID_2_NONE 0x00000000 ++/** March test */ ++#define STATUS_MBCFG_TID_2_MARCH 0x00000040 ++/** Checkerboard test */ ++#define STATUS_MBCFG_TID_2_CHCK 0x00000080 ++/** Hammer test */ ++#define STATUS_MBCFG_TID_2_HAM 0x000000C0 ++/** Address decoder test */ ++#define STATUS_MBCFG_TID_2_ADEC 0x00000100 ++/** Write mask byte test */ ++#define STATUS_MBCFG_TID_2_WMBYTE 0x00000140 ++/** Reserved */ ++#define STATUS_MBCFG_TID_2_RES 0x00000180 ++/** Test ID ++ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ ++#define STATUS_MBCFG_TID_1_MASK 0x00000038 ++/** field offset */ ++#define STATUS_MBCFG_TID_1_OFFSET 3 ++/** No test is performed */ ++#define STATUS_MBCFG_TID_1_NONE 0x00000000 ++/** March test */ ++#define STATUS_MBCFG_TID_1_MARCH 0x00000008 ++/** Checkerboard test */ ++#define STATUS_MBCFG_TID_1_CHCK 0x00000010 ++/** Hammer test */ ++#define STATUS_MBCFG_TID_1_HAM 0x00000018 ++/** Address decoder test */ ++#define STATUS_MBCFG_TID_1_ADEC 0x00000020 ++/** Write mask byte test */ ++#define STATUS_MBCFG_TID_1_WMBYTE 0x00000028 ++/** Reserved */ ++#define STATUS_MBCFG_TID_1_RES 0x00000030 ++/** Test ID ++ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ ++#define STATUS_MBCFG_TID_0_MASK 0x00000007 ++/** field offset */ ++#define STATUS_MBCFG_TID_0_OFFSET 0 ++/** No test is performed */ ++#define STATUS_MBCFG_TID_0_NONE 0x00000000 ++/** March test */ ++#define STATUS_MBCFG_TID_0_MARCH 0x00000001 ++/** Checkerboard test */ ++#define STATUS_MBCFG_TID_0_CHCK 0x00000002 ++/** Hammer test */ ++#define STATUS_MBCFG_TID_0_HAM 0x00000003 ++/** Address decoder test */ ++#define STATUS_MBCFG_TID_0_ADEC 0x00000004 ++/** Write mask byte test */ ++#define STATUS_MBCFG_TID_0_WMBYTE 0x00000005 ++/** Reserved */ ++#define STATUS_MBCFG_TID_0_RES 0x00000006 ++ ++/* Fields of "sbs0 bist result and debug data" */ ++/** BIST result and debug data ++ Stores additional debug information */ ++#define STATUS_MBDATA_DATA_MASK 0xFFFFFFF8 ++/** field offset */ ++#define STATUS_MBDATA_DATA_OFFSET 3 ++/** MBIST NOGO ++ The BIST failed and cannot be repaired due to many failure locations */ ++#define STATUS_MBDATA_MBNOGO 0x00000004 ++/** MBIST FAILED ++ The BIST failed but can be repaired */ ++#define STATUS_MBDATA_MBFAIL 0x00000002 ++/** MBIST PASSED ++ The BIST passed without any Failures */ ++#define STATUS_MBDATA_MBPASS 0x00000001 ++ ++/*! @} */ /* STATUS_REGISTER */ ++ ++#endif /* _status_reg_h */ +diff --git a/arch/mips/include/asm/mach-lantiq/falcon/sys1_reg.h b/arch/mips/include/asm/mach-lantiq/falcon/sys1_reg.h +new file mode 100644 +index 0000000..d29007f +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/sys1_reg.h +@@ -0,0 +1,2008 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++ ++#ifndef _sys1_reg_h ++#define _sys1_reg_h ++ ++/** \addtogroup SYS1_REGISTER ++ @{ ++*/ ++/* access macros */ ++#define sys1_r32(reg) reg_r32(&sys1->reg) ++#define sys1_w32(val, reg) reg_w32(val, &sys1->reg) ++#define sys1_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys1->reg) ++#define sys1_r32_table(reg, idx) reg_r32_table(sys1->reg, idx) ++#define sys1_w32_table(val, reg, idx) reg_w32_table(val, sys1->reg, idx) ++#define sys1_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys1->reg, idx) ++#define sys1_adr_table(reg, idx) adr_table(sys1->reg, idx) ++ ++ ++/** SYS1 register structure */ ++struct gpon_reg_sys1 ++{ ++ /** Clock Status Register */ ++ unsigned int clks; /* 0x00000000 */ ++ /** Clock Enable Register ++ Via this register the clocks for the domains can be enabled. */ ++ unsigned int clken; /* 0x00000004 */ ++ /** Clock Clear Register ++ Via this register the clocks for the domains can be disabled. */ ++ unsigned int clkclr; /* 0x00000008 */ ++ /** Reserved */ ++ unsigned int res_0[5]; /* 0x0000000C */ ++ /** Activation Status Register */ ++ unsigned int acts; /* 0x00000020 */ ++ /** Activation Register ++ Via this register the domains can be activated. */ ++ unsigned int act; /* 0x00000024 */ ++ /** Deactivation Register ++ Via this register the domains can be deactivated. */ ++ unsigned int deact; /* 0x00000028 */ ++ /** Reboot Trigger Register ++ Via this register the domains can be rebooted (sent through reset). */ ++ unsigned int rbt; /* 0x0000002C */ ++ /** Reserved */ ++ unsigned int res_1[4]; /* 0x00000030 */ ++ /** CPU0 Clock Control Register ++ Clock control register for CPU0 */ ++ unsigned int cpu0cc; /* 0x00000040 */ ++ /** Reserved */ ++ unsigned int res_2[7]; /* 0x00000044 */ ++ /** CPU0 Reset Source Register ++ Via this register the CPU can find the the root cause for the boot it currently goes through, and take the appropriate measures. */ ++ unsigned int cpu0rs; /* 0x00000060 */ ++ /** Reserved */ ++ unsigned int res_3[7]; /* 0x00000064 */ ++ /** CPU0 Wakeup Configuration Register ++ Controls the wakeup condition for CPU0. Note: The upper 16 bit of this register have to be set to the same value as the mask bits within the yield-resume interface block. If the yield-resume interface is not used at all, set the upper 16 bit to 0. */ ++ unsigned int cpu0wcfg; /* 0x00000080 */ ++ /** Reserved */ ++ unsigned int res_4[7]; /* 0x00000084 */ ++ /** Bootmode Control Register ++ Reflects the bootmode for the CPU and provides means to manipulate it. */ ++ unsigned int bmc; /* 0x000000A0 */ ++ /** Reserved */ ++ unsigned int res_5[3]; /* 0x000000A4 */ ++ /** Sleep Configuration Register */ ++ unsigned int scfg; /* 0x000000B0 */ ++ /** Power Down Configuration Register ++ Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be switched off. */ ++ unsigned int pdcfg; /* 0x000000B4 */ ++ /** CLKO Pad Control Register ++ Controls the behaviour of the CLKO pad/ball. */ ++ unsigned int clkoc; /* 0x000000B8 */ ++ /** Infrastructure Control Register ++ Controls the behaviour of the components of the infrastructure block. */ ++ unsigned int infrac; /* 0x000000BC */ ++ /** HRST_OUT_N Control Register ++ Controls the behaviour of the HRST_OUT_N pin. */ ++ unsigned int hrstoutc; /* 0x000000C0 */ ++ /** EBU Clock Control Register ++ Clock control register for the EBU. */ ++ unsigned int ebucc; /* 0x000000C4 */ ++ /** Reserved */ ++ unsigned int res_6[2]; /* 0x000000C8 */ ++ /** NMI Status Register ++ The Test NMI source is the GPTC counter 1A overflow bit. */ ++ unsigned int nmis; /* 0x000000D0 */ ++ /** NMI Set Register */ ++ unsigned int nmiset; /* 0x000000D4 */ ++ /** NMI Clear Register */ ++ unsigned int nmiclr; /* 0x000000D8 */ ++ /** NMI Test Configuration Register */ ++ unsigned int nmitcfg; /* 0x000000DC */ ++ /** NMI VPE1 Control Register */ ++ unsigned int nmivpe1c; /* 0x000000E0 */ ++ /** Reserved */ ++ unsigned int res_7[3]; /* 0x000000E4 */ ++ /** IRN Capture Register ++ This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNEN register. The interrupts can be acknowledged by a write operation. */ ++ unsigned int irncr; /* 0x000000F0 */ ++ /** IRN Interrupt Control Register ++ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ ++ unsigned int irnicr; /* 0x000000F4 */ ++ /** IRN Interrupt Enable Register ++ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCR register and are not signalled via the interrupt line towards the controller. */ ++ unsigned int irnen; /* 0x000000F8 */ ++ /** Reserved */ ++ unsigned int res_8; /* 0x000000FC */ ++}; ++ ++ ++/* Fields of "Clock Status Register" */ ++/** STATUS Clock Enable ++ Shows the clock enable bit for the STATUS domain. This domain contains the STATUS block. */ ++#define CLKS_STATUS 0x80000000 ++/* Disable ++#define CLKS_STATUS_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_STATUS_EN 0x80000000 ++/** SHA1 Clock Enable ++ Shows the clock enable bit for the SHA1 domain. This domain contains the SHA1 block. */ ++#define CLKS_SHA1 0x40000000 ++/* Disable ++#define CLKS_SHA1_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_SHA1_EN 0x40000000 ++/** AES Clock Enable ++ Shows the clock enable bit for the AES domain. This domain contains the AES block. */ ++#define CLKS_AES 0x20000000 ++/* Disable ++#define CLKS_AES_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_AES_EN 0x20000000 ++/** PCM Clock Enable ++ Shows the clock enable bit for the PCM domain. This domain contains the PCM interface block. */ ++#define CLKS_PCM 0x10000000 ++/* Disable ++#define CLKS_PCM_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_PCM_EN 0x10000000 ++/** FSCT Clock Enable ++ Shows the clock enable bit for the FSCT domain. This domain contains the FSCT block. */ ++#define CLKS_FSCT 0x08000000 ++/* Disable ++#define CLKS_FSCT_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_FSCT_EN 0x08000000 ++/** GPTC Clock Enable ++ Shows the clock enable bit for the GPTC domain. This domain contains the GPTC block. */ ++#define CLKS_GPTC 0x04000000 ++/* Disable ++#define CLKS_GPTC_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_GPTC_EN 0x04000000 ++/** MPS Clock Enable ++ Shows the clock enable bit for the MPS domain. This domain contains the MPS block. */ ++#define CLKS_MPS 0x02000000 ++/* Disable ++#define CLKS_MPS_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_MPS_EN 0x02000000 ++/** DFEV0 Clock Enable ++ Shows the clock enable bit for the DFEV0 domain. This domain contains the DFEV0 block. */ ++#define CLKS_DFEV0 0x01000000 ++/* Disable ++#define CLKS_DFEV0_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_DFEV0_EN 0x01000000 ++/** PADCTRL4 Clock Enable ++ Shows the clock enable bit for the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ ++#define CLKS_PADCTRL4 0x00400000 ++/* Disable ++#define CLKS_PADCTRL4_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_PADCTRL4_EN 0x00400000 ++/** PADCTRL3 Clock Enable ++ Shows the clock enable bit for the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ ++#define CLKS_PADCTRL3 0x00200000 ++/* Disable ++#define CLKS_PADCTRL3_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_PADCTRL3_EN 0x00200000 ++/** PADCTRL1 Clock Enable ++ Shows the clock enable bit for the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ ++#define CLKS_PADCTRL1 0x00100000 ++/* Disable ++#define CLKS_PADCTRL1_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_PADCTRL1_EN 0x00100000 ++/** P4 Clock Enable ++ Shows the clock enable bit for the P4 domain. This domain contains the P4 instance of the GPIO block. */ ++#define CLKS_P4 0x00040000 ++/* Disable ++#define CLKS_P4_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_P4_EN 0x00040000 ++/** P3 Clock Enable ++ Shows the clock enable bit for the P3 domain. This domain contains the P3 instance of the GPIO block. */ ++#define CLKS_P3 0x00020000 ++/* Disable ++#define CLKS_P3_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_P3_EN 0x00020000 ++/** P1 Clock Enable ++ Shows the clock enable bit for the P1 domain. This domain contains the P1 instance of the GPIO block. */ ++#define CLKS_P1 0x00010000 ++/* Disable ++#define CLKS_P1_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_P1_EN 0x00010000 ++/** HOST Clock Enable ++ Shows the clock enable bit for the HOST domain. This domain contains the HOST interface block. */ ++#define CLKS_HOST 0x00008000 ++/* Disable ++#define CLKS_HOST_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_HOST_EN 0x00008000 ++/** I2C Clock Enable ++ Shows the clock enable bit for the I2C domain. This domain contains the I2C interface block. */ ++#define CLKS_I2C 0x00004000 ++/* Disable ++#define CLKS_I2C_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_I2C_EN 0x00004000 ++/** SSC0 Clock Enable ++ Shows the clock enable bit for the SSC0 domain. This domain contains the SSC0 interface block. */ ++#define CLKS_SSC0 0x00002000 ++/* Disable ++#define CLKS_SSC0_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_SSC0_EN 0x00002000 ++/** ASC0 Clock Enable ++ Shows the clock enable bit for the ASC0 domain. This domain contains the ASC0 interface block. */ ++#define CLKS_ASC0 0x00001000 ++/* Disable ++#define CLKS_ASC0_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_ASC0_EN 0x00001000 ++/** ASC1 Clock Enable ++ Shows the clock enable bit for the ASC1 domain. This domain contains the ASC1 block. */ ++#define CLKS_ASC1 0x00000800 ++/* Disable ++#define CLKS_ASC1_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_ASC1_EN 0x00000800 ++/** DCDCAPD Clock Enable ++ Shows the clock enable bit for the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ ++#define CLKS_DCDCAPD 0x00000400 ++/* Disable ++#define CLKS_DCDCAPD_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_DCDCAPD_EN 0x00000400 ++/** DCDCDDR Clock Enable ++ Shows the clock enable bit for the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ ++#define CLKS_DCDCDDR 0x00000200 ++/* Disable ++#define CLKS_DCDCDDR_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_DCDCDDR_EN 0x00000200 ++/** DCDC1V0 Clock Enable ++ Shows the clock enable bit for the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ ++#define CLKS_DCDC1V0 0x00000100 ++/* Disable ++#define CLKS_DCDC1V0_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_DCDC1V0_EN 0x00000100 ++/** TRC2MEM Clock Enable ++ Shows the clock enable bit for the TRC2MEM domain. This domain contains the TRC2MEM block. */ ++#define CLKS_TRC2MEM 0x00000040 ++/* Disable ++#define CLKS_TRC2MEM_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_TRC2MEM_EN 0x00000040 ++/** DDR Clock Enable ++ Shows the clock enable bit for the DDR domain. This domain contains the DDR interface block. */ ++#define CLKS_DDR 0x00000020 ++/* Disable ++#define CLKS_DDR_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_DDR_EN 0x00000020 ++/** EBU Clock Enable ++ Shows the clock enable bit for the EBU domain. This domain contains the EBU interface block. */ ++#define CLKS_EBU 0x00000010 ++/* Disable ++#define CLKS_EBU_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_EBU_EN 0x00000010 ++ ++/* Fields of "Clock Enable Register" */ ++/** Set Clock Enable STATUS ++ Sets the clock enable bit of the STATUS domain. This domain contains the STATUS block. */ ++#define CLKEN_STATUS 0x80000000 ++/* No-Operation ++#define CLKEN_STATUS_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_STATUS_SET 0x80000000 ++/** Set Clock Enable SHA1 ++ Sets the clock enable bit of the SHA1 domain. This domain contains the SHA1 block. */ ++#define CLKEN_SHA1 0x40000000 ++/* No-Operation ++#define CLKEN_SHA1_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_SHA1_SET 0x40000000 ++/** Set Clock Enable AES ++ Sets the clock enable bit of the AES domain. This domain contains the AES block. */ ++#define CLKEN_AES 0x20000000 ++/* No-Operation ++#define CLKEN_AES_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_AES_SET 0x20000000 ++/** Set Clock Enable PCM ++ Sets the clock enable bit of the PCM domain. This domain contains the PCM interface block. */ ++#define CLKEN_PCM 0x10000000 ++/* No-Operation ++#define CLKEN_PCM_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_PCM_SET 0x10000000 ++/** Set Clock Enable FSCT ++ Sets the clock enable bit of the FSCT domain. This domain contains the FSCT block. */ ++#define CLKEN_FSCT 0x08000000 ++/* No-Operation ++#define CLKEN_FSCT_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_FSCT_SET 0x08000000 ++/** Set Clock Enable GPTC ++ Sets the clock enable bit of the GPTC domain. This domain contains the GPTC block. */ ++#define CLKEN_GPTC 0x04000000 ++/* No-Operation ++#define CLKEN_GPTC_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_GPTC_SET 0x04000000 ++/** Set Clock Enable MPS ++ Sets the clock enable bit of the MPS domain. This domain contains the MPS block. */ ++#define CLKEN_MPS 0x02000000 ++/* No-Operation ++#define CLKEN_MPS_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_MPS_SET 0x02000000 ++/** Set Clock Enable DFEV0 ++ Sets the clock enable bit of the DFEV0 domain. This domain contains the DFEV0 block. */ ++#define CLKEN_DFEV0 0x01000000 ++/* No-Operation ++#define CLKEN_DFEV0_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_DFEV0_SET 0x01000000 ++/** Set Clock Enable PADCTRL4 ++ Sets the clock enable bit of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ ++#define CLKEN_PADCTRL4 0x00400000 ++/* No-Operation ++#define CLKEN_PADCTRL4_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_PADCTRL4_SET 0x00400000 ++/** Set Clock Enable PADCTRL3 ++ Sets the clock enable bit of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ ++#define CLKEN_PADCTRL3 0x00200000 ++/* No-Operation ++#define CLKEN_PADCTRL3_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_PADCTRL3_SET 0x00200000 ++/** Set Clock Enable PADCTRL1 ++ Sets the clock enable bit of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ ++#define CLKEN_PADCTRL1 0x00100000 ++/* No-Operation ++#define CLKEN_PADCTRL1_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_PADCTRL1_SET 0x00100000 ++/** Set Clock Enable P4 ++ Sets the clock enable bit of the P4 domain. This domain contains the P4 instance of the GPIO block. */ ++#define CLKEN_P4 0x00040000 ++/* No-Operation ++#define CLKEN_P4_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_P4_SET 0x00040000 ++/** Set Clock Enable P3 ++ Sets the clock enable bit of the P3 domain. This domain contains the P3 instance of the GPIO block. */ ++#define CLKEN_P3 0x00020000 ++/* No-Operation ++#define CLKEN_P3_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_P3_SET 0x00020000 ++/** Set Clock Enable P1 ++ Sets the clock enable bit of the P1 domain. This domain contains the P1 instance of the GPIO block. */ ++#define CLKEN_P1 0x00010000 ++/* No-Operation ++#define CLKEN_P1_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_P1_SET 0x00010000 ++/** Set Clock Enable HOST ++ Sets the clock enable bit of the HOST domain. This domain contains the HOST interface block. */ ++#define CLKEN_HOST 0x00008000 ++/* No-Operation ++#define CLKEN_HOST_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_HOST_SET 0x00008000 ++/** Set Clock Enable I2C ++ Sets the clock enable bit of the I2C domain. This domain contains the I2C interface block. */ ++#define CLKEN_I2C 0x00004000 ++/* No-Operation ++#define CLKEN_I2C_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_I2C_SET 0x00004000 ++/** Set Clock Enable SSC0 ++ Sets the clock enable bit of the SSC0 domain. This domain contains the SSC0 interface block. */ ++#define CLKEN_SSC0 0x00002000 ++/* No-Operation ++#define CLKEN_SSC0_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_SSC0_SET 0x00002000 ++/** Set Clock Enable ASC0 ++ Sets the clock enable bit of the ASC0 domain. This domain contains the ASC0 interface block. */ ++#define CLKEN_ASC0 0x00001000 ++/* No-Operation ++#define CLKEN_ASC0_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_ASC0_SET 0x00001000 ++/** Set Clock Enable ASC1 ++ Sets the clock enable bit of the ASC1 domain. This domain contains the ASC1 block. */ ++#define CLKEN_ASC1 0x00000800 ++/* No-Operation ++#define CLKEN_ASC1_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_ASC1_SET 0x00000800 ++/** Set Clock Enable DCDCAPD ++ Sets the clock enable bit of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ ++#define CLKEN_DCDCAPD 0x00000400 ++/* No-Operation ++#define CLKEN_DCDCAPD_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_DCDCAPD_SET 0x00000400 ++/** Set Clock Enable DCDCDDR ++ Sets the clock enable bit of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ ++#define CLKEN_DCDCDDR 0x00000200 ++/* No-Operation ++#define CLKEN_DCDCDDR_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_DCDCDDR_SET 0x00000200 ++/** Set Clock Enable DCDC1V0 ++ Sets the clock enable bit of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ ++#define CLKEN_DCDC1V0 0x00000100 ++/* No-Operation ++#define CLKEN_DCDC1V0_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_DCDC1V0_SET 0x00000100 ++/** Set Clock Enable TRC2MEM ++ Sets the clock enable bit of the TRC2MEM domain. This domain contains the TRC2MEM block. */ ++#define CLKEN_TRC2MEM 0x00000040 ++/* No-Operation ++#define CLKEN_TRC2MEM_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_TRC2MEM_SET 0x00000040 ++/** Set Clock Enable DDR ++ Sets the clock enable bit of the DDR domain. This domain contains the DDR interface block. */ ++#define CLKEN_DDR 0x00000020 ++/* No-Operation ++#define CLKEN_DDR_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_DDR_SET 0x00000020 ++/** Set Clock Enable EBU ++ Sets the clock enable bit of the EBU domain. This domain contains the EBU interface block. */ ++#define CLKEN_EBU 0x00000010 ++/* No-Operation ++#define CLKEN_EBU_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_EBU_SET 0x00000010 ++ ++/* Fields of "Clock Clear Register" */ ++/** Clear Clock Enable STATUS ++ Clears the clock enable bit of the STATUS domain. This domain contains the STATUS block. */ ++#define CLKCLR_STATUS 0x80000000 ++/* No-Operation ++#define CLKCLR_STATUS_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_STATUS_CLR 0x80000000 ++/** Clear Clock Enable SHA1 ++ Clears the clock enable bit of the SHA1 domain. This domain contains the SHA1 block. */ ++#define CLKCLR_SHA1 0x40000000 ++/* No-Operation ++#define CLKCLR_SHA1_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_SHA1_CLR 0x40000000 ++/** Clear Clock Enable AES ++ Clears the clock enable bit of the AES domain. This domain contains the AES block. */ ++#define CLKCLR_AES 0x20000000 ++/* No-Operation ++#define CLKCLR_AES_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_AES_CLR 0x20000000 ++/** Clear Clock Enable PCM ++ Clears the clock enable bit of the PCM domain. This domain contains the PCM interface block. */ ++#define CLKCLR_PCM 0x10000000 ++/* No-Operation ++#define CLKCLR_PCM_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_PCM_CLR 0x10000000 ++/** Clear Clock Enable FSCT ++ Clears the clock enable bit of the FSCT domain. This domain contains the FSCT block. */ ++#define CLKCLR_FSCT 0x08000000 ++/* No-Operation ++#define CLKCLR_FSCT_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_FSCT_CLR 0x08000000 ++/** Clear Clock Enable GPTC ++ Clears the clock enable bit of the GPTC domain. This domain contains the GPTC block. */ ++#define CLKCLR_GPTC 0x04000000 ++/* No-Operation ++#define CLKCLR_GPTC_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_GPTC_CLR 0x04000000 ++/** Clear Clock Enable MPS ++ Clears the clock enable bit of the MPS domain. This domain contains the MPS block. */ ++#define CLKCLR_MPS 0x02000000 ++/* No-Operation ++#define CLKCLR_MPS_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_MPS_CLR 0x02000000 ++/** Clear Clock Enable DFEV0 ++ Clears the clock enable bit of the DFEV0 domain. This domain contains the DFEV0 block. */ ++#define CLKCLR_DFEV0 0x01000000 ++/* No-Operation ++#define CLKCLR_DFEV0_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_DFEV0_CLR 0x01000000 ++/** Clear Clock Enable PADCTRL4 ++ Clears the clock enable bit of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ ++#define CLKCLR_PADCTRL4 0x00400000 ++/* No-Operation ++#define CLKCLR_PADCTRL4_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_PADCTRL4_CLR 0x00400000 ++/** Clear Clock Enable PADCTRL3 ++ Clears the clock enable bit of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ ++#define CLKCLR_PADCTRL3 0x00200000 ++/* No-Operation ++#define CLKCLR_PADCTRL3_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_PADCTRL3_CLR 0x00200000 ++/** Clear Clock Enable PADCTRL1 ++ Clears the clock enable bit of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ ++#define CLKCLR_PADCTRL1 0x00100000 ++/* No-Operation ++#define CLKCLR_PADCTRL1_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_PADCTRL1_CLR 0x00100000 ++/** Clear Clock Enable P4 ++ Clears the clock enable bit of the P4 domain. This domain contains the P4 instance of the GPIO block. */ ++#define CLKCLR_P4 0x00040000 ++/* No-Operation ++#define CLKCLR_P4_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_P4_CLR 0x00040000 ++/** Clear Clock Enable P3 ++ Clears the clock enable bit of the P3 domain. This domain contains the P3 instance of the GPIO block. */ ++#define CLKCLR_P3 0x00020000 ++/* No-Operation ++#define CLKCLR_P3_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_P3_CLR 0x00020000 ++/** Clear Clock Enable P1 ++ Clears the clock enable bit of the P1 domain. This domain contains the P1 instance of the GPIO block. */ ++#define CLKCLR_P1 0x00010000 ++/* No-Operation ++#define CLKCLR_P1_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_P1_CLR 0x00010000 ++/** Clear Clock Enable HOST ++ Clears the clock enable bit of the HOST domain. This domain contains the HOST interface block. */ ++#define CLKCLR_HOST 0x00008000 ++/* No-Operation ++#define CLKCLR_HOST_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_HOST_CLR 0x00008000 ++/** Clear Clock Enable I2C ++ Clears the clock enable bit of the I2C domain. This domain contains the I2C interface block. */ ++#define CLKCLR_I2C 0x00004000 ++/* No-Operation ++#define CLKCLR_I2C_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_I2C_CLR 0x00004000 ++/** Clear Clock Enable SSC0 ++ Clears the clock enable bit of the SSC0 domain. This domain contains the SSC0 interface block. */ ++#define CLKCLR_SSC0 0x00002000 ++/* No-Operation ++#define CLKCLR_SSC0_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_SSC0_CLR 0x00002000 ++/** Clear Clock Enable ASC0 ++ Clears the clock enable bit of the ASC0 domain. This domain contains the ASC0 interface block. */ ++#define CLKCLR_ASC0 0x00001000 ++/* No-Operation ++#define CLKCLR_ASC0_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_ASC0_CLR 0x00001000 ++/** Clear Clock Enable ASC1 ++ Clears the clock enable bit of the ASC1 domain. This domain contains the ASC1 block. */ ++#define CLKCLR_ASC1 0x00000800 ++/* No-Operation ++#define CLKCLR_ASC1_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_ASC1_CLR 0x00000800 ++/** Clear Clock Enable DCDCAPD ++ Clears the clock enable bit of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ ++#define CLKCLR_DCDCAPD 0x00000400 ++/* No-Operation ++#define CLKCLR_DCDCAPD_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_DCDCAPD_CLR 0x00000400 ++/** Clear Clock Enable DCDCDDR ++ Clears the clock enable bit of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ ++#define CLKCLR_DCDCDDR 0x00000200 ++/* No-Operation ++#define CLKCLR_DCDCDDR_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_DCDCDDR_CLR 0x00000200 ++/** Clear Clock Enable DCDC1V0 ++ Clears the clock enable bit of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ ++#define CLKCLR_DCDC1V0 0x00000100 ++/* No-Operation ++#define CLKCLR_DCDC1V0_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_DCDC1V0_CLR 0x00000100 ++/** Clear Clock Enable TRC2MEM ++ Clears the clock enable bit of the TRC2MEM domain. This domain contains the TRC2MEM block. */ ++#define CLKCLR_TRC2MEM 0x00000040 ++/* No-Operation ++#define CLKCLR_TRC2MEM_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_TRC2MEM_CLR 0x00000040 ++/** Clear Clock Enable DDR ++ Clears the clock enable bit of the DDR domain. This domain contains the DDR interface block. */ ++#define CLKCLR_DDR 0x00000020 ++/* No-Operation ++#define CLKCLR_DDR_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_DDR_CLR 0x00000020 ++/** Clear Clock Enable EBU ++ Clears the clock enable bit of the EBU domain. This domain contains the EBU interface block. */ ++#define CLKCLR_EBU 0x00000010 ++/* No-Operation ++#define CLKCLR_EBU_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_EBU_CLR 0x00000010 ++ ++/* Fields of "Activation Status Register" */ ++/** STATUS Status ++ Shows the activation status of the STATUS domain. This domain contains the STATUS block. */ ++#define ACTS_STATUS 0x80000000 ++/* The block is inactive. ++#define ACTS_STATUS_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_STATUS_ACT 0x80000000 ++/** SHA1 Status ++ Shows the activation status of the SHA1 domain. This domain contains the SHA1 block. */ ++#define ACTS_SHA1 0x40000000 ++/* The block is inactive. ++#define ACTS_SHA1_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_SHA1_ACT 0x40000000 ++/** AES Status ++ Shows the activation status of the AES domain. This domain contains the AES block. */ ++#define ACTS_AES 0x20000000 ++/* The block is inactive. ++#define ACTS_AES_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_AES_ACT 0x20000000 ++/** PCM Status ++ Shows the activation status of the PCM domain. This domain contains the PCM interface block. */ ++#define ACTS_PCM 0x10000000 ++/* The block is inactive. ++#define ACTS_PCM_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_PCM_ACT 0x10000000 ++/** FSCT Status ++ Shows the activation status of the FSCT domain. This domain contains the FSCT block. */ ++#define ACTS_FSCT 0x08000000 ++/* The block is inactive. ++#define ACTS_FSCT_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_FSCT_ACT 0x08000000 ++/** GPTC Status ++ Shows the activation status of the GPTC domain. This domain contains the GPTC block. */ ++#define ACTS_GPTC 0x04000000 ++/* The block is inactive. ++#define ACTS_GPTC_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_GPTC_ACT 0x04000000 ++/** MPS Status ++ Shows the activation status of the MPS domain. This domain contains the MPS block. */ ++#define ACTS_MPS 0x02000000 ++/* The block is inactive. ++#define ACTS_MPS_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_MPS_ACT 0x02000000 ++/** DFEV0 Status ++ Shows the activation status of the DFEV0 domain. This domain contains the DFEV0 block. */ ++#define ACTS_DFEV0 0x01000000 ++/* The block is inactive. ++#define ACTS_DFEV0_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_DFEV0_ACT 0x01000000 ++/** PADCTRL4 Status ++ Shows the activation status of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ ++#define ACTS_PADCTRL4 0x00400000 ++/* The block is inactive. ++#define ACTS_PADCTRL4_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_PADCTRL4_ACT 0x00400000 ++/** PADCTRL3 Status ++ Shows the activation status of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ ++#define ACTS_PADCTRL3 0x00200000 ++/* The block is inactive. ++#define ACTS_PADCTRL3_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_PADCTRL3_ACT 0x00200000 ++/** PADCTRL1 Status ++ Shows the activation status of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ ++#define ACTS_PADCTRL1 0x00100000 ++/* The block is inactive. ++#define ACTS_PADCTRL1_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_PADCTRL1_ACT 0x00100000 ++/** P4 Status ++ Shows the activation status of the P4 domain. This domain contains the P4 instance of the GPIO block. */ ++#define ACTS_P4 0x00040000 ++/* The block is inactive. ++#define ACTS_P4_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_P4_ACT 0x00040000 ++/** P3 Status ++ Shows the activation status of the P3 domain. This domain contains the P3 instance of the GPIO block. */ ++#define ACTS_P3 0x00020000 ++/* The block is inactive. ++#define ACTS_P3_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_P3_ACT 0x00020000 ++/** P1 Status ++ Shows the activation status of the P1 domain. This domain contains the P1 instance of the GPIO block. */ ++#define ACTS_P1 0x00010000 ++/* The block is inactive. ++#define ACTS_P1_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_P1_ACT 0x00010000 ++/** HOST Status ++ Shows the activation status of the HOST domain. This domain contains the HOST interface block. */ ++#define ACTS_HOST 0x00008000 ++/* The block is inactive. ++#define ACTS_HOST_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_HOST_ACT 0x00008000 ++/** I2C Status ++ Shows the activation status of the I2C domain. This domain contains the I2C interface block. */ ++#define ACTS_I2C 0x00004000 ++/* The block is inactive. ++#define ACTS_I2C_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_I2C_ACT 0x00004000 ++/** SSC0 Status ++ Shows the activation status of the SSC0 domain. This domain contains the SSC0 interface block. */ ++#define ACTS_SSC0 0x00002000 ++/* The block is inactive. ++#define ACTS_SSC0_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_SSC0_ACT 0x00002000 ++/** ASC0 Status ++ Shows the activation status of the ASC0 domain. This domain contains the ASC0 interface block. */ ++#define ACTS_ASC0 0x00001000 ++/* The block is inactive. ++#define ACTS_ASC0_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_ASC0_ACT 0x00001000 ++/** ASC1 Status ++ Shows the activation status of the ASC1 domain. This domain contains the ASC1 block. */ ++#define ACTS_ASC1 0x00000800 ++/* The block is inactive. ++#define ACTS_ASC1_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_ASC1_ACT 0x00000800 ++/** DCDCAPD Status ++ Shows the activation status of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ ++#define ACTS_DCDCAPD 0x00000400 ++/* The block is inactive. ++#define ACTS_DCDCAPD_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_DCDCAPD_ACT 0x00000400 ++/** DCDCDDR Status ++ Shows the activation status of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ ++#define ACTS_DCDCDDR 0x00000200 ++/* The block is inactive. ++#define ACTS_DCDCDDR_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_DCDCDDR_ACT 0x00000200 ++/** DCDC1V0 Status ++ Shows the activation status of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ ++#define ACTS_DCDC1V0 0x00000100 ++/* The block is inactive. ++#define ACTS_DCDC1V0_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_DCDC1V0_ACT 0x00000100 ++/** TRC2MEM Status ++ Shows the activation status of the TRC2MEM domain. This domain contains the TRC2MEM block. */ ++#define ACTS_TRC2MEM 0x00000040 ++/* The block is inactive. ++#define ACTS_TRC2MEM_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_TRC2MEM_ACT 0x00000040 ++/** DDR Status ++ Shows the activation status of the DDR domain. This domain contains the DDR interface block. */ ++#define ACTS_DDR 0x00000020 ++/* The block is inactive. ++#define ACTS_DDR_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_DDR_ACT 0x00000020 ++/** EBU Status ++ Shows the activation status of the EBU domain. This domain contains the EBU interface block. */ ++#define ACTS_EBU 0x00000010 ++/* The block is inactive. ++#define ACTS_EBU_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_EBU_ACT 0x00000010 ++ ++/* Fields of "Activation Register" */ ++/** Activate STATUS ++ Sets the activation flag of the STATUS domain. This domain contains the STATUS block. */ ++#define ACT_STATUS 0x80000000 ++/* No-Operation ++#define ACT_STATUS_NOP 0x00000000 */ ++/** Set */ ++#define ACT_STATUS_SET 0x80000000 ++/** Activate SHA1 ++ Sets the activation flag of the SHA1 domain. This domain contains the SHA1 block. */ ++#define ACT_SHA1 0x40000000 ++/* No-Operation ++#define ACT_SHA1_NOP 0x00000000 */ ++/** Set */ ++#define ACT_SHA1_SET 0x40000000 ++/** Activate AES ++ Sets the activation flag of the AES domain. This domain contains the AES block. */ ++#define ACT_AES 0x20000000 ++/* No-Operation ++#define ACT_AES_NOP 0x00000000 */ ++/** Set */ ++#define ACT_AES_SET 0x20000000 ++/** Activate PCM ++ Sets the activation flag of the PCM domain. This domain contains the PCM interface block. */ ++#define ACT_PCM 0x10000000 ++/* No-Operation ++#define ACT_PCM_NOP 0x00000000 */ ++/** Set */ ++#define ACT_PCM_SET 0x10000000 ++/** Activate FSCT ++ Sets the activation flag of the FSCT domain. This domain contains the FSCT block. */ ++#define ACT_FSCT 0x08000000 ++/* No-Operation ++#define ACT_FSCT_NOP 0x00000000 */ ++/** Set */ ++#define ACT_FSCT_SET 0x08000000 ++/** Activate GPTC ++ Sets the activation flag of the GPTC domain. This domain contains the GPTC block. */ ++#define ACT_GPTC 0x04000000 ++/* No-Operation ++#define ACT_GPTC_NOP 0x00000000 */ ++/** Set */ ++#define ACT_GPTC_SET 0x04000000 ++/** Activate MPS ++ Sets the activation flag of the MPS domain. This domain contains the MPS block. */ ++#define ACT_MPS 0x02000000 ++/* No-Operation ++#define ACT_MPS_NOP 0x00000000 */ ++/** Set */ ++#define ACT_MPS_SET 0x02000000 ++/** Activate DFEV0 ++ Sets the activation flag of the DFEV0 domain. This domain contains the DFEV0 block. */ ++#define ACT_DFEV0 0x01000000 ++/* No-Operation ++#define ACT_DFEV0_NOP 0x00000000 */ ++/** Set */ ++#define ACT_DFEV0_SET 0x01000000 ++/** Activate PADCTRL4 ++ Sets the activation flag of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ ++#define ACT_PADCTRL4 0x00400000 ++/* No-Operation ++#define ACT_PADCTRL4_NOP 0x00000000 */ ++/** Set */ ++#define ACT_PADCTRL4_SET 0x00400000 ++/** Activate PADCTRL3 ++ Sets the activation flag of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ ++#define ACT_PADCTRL3 0x00200000 ++/* No-Operation ++#define ACT_PADCTRL3_NOP 0x00000000 */ ++/** Set */ ++#define ACT_PADCTRL3_SET 0x00200000 ++/** Activate PADCTRL1 ++ Sets the activation flag of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ ++#define ACT_PADCTRL1 0x00100000 ++/* No-Operation ++#define ACT_PADCTRL1_NOP 0x00000000 */ ++/** Set */ ++#define ACT_PADCTRL1_SET 0x00100000 ++/** Activate P4 ++ Sets the activation flag of the P4 domain. This domain contains the P4 instance of the GPIO block. */ ++#define ACT_P4 0x00040000 ++/* No-Operation ++#define ACT_P4_NOP 0x00000000 */ ++/** Set */ ++#define ACT_P4_SET 0x00040000 ++/** Activate P3 ++ Sets the activation flag of the P3 domain. This domain contains the P3 instance of the GPIO block. */ ++#define ACT_P3 0x00020000 ++/* No-Operation ++#define ACT_P3_NOP 0x00000000 */ ++/** Set */ ++#define ACT_P3_SET 0x00020000 ++/** Activate P1 ++ Sets the activation flag of the P1 domain. This domain contains the P1 instance of the GPIO block. */ ++#define ACT_P1 0x00010000 ++/* No-Operation ++#define ACT_P1_NOP 0x00000000 */ ++/** Set */ ++#define ACT_P1_SET 0x00010000 ++/** Activate HOST ++ Sets the activation flag of the HOST domain. This domain contains the HOST interface block. */ ++#define ACT_HOST 0x00008000 ++/* No-Operation ++#define ACT_HOST_NOP 0x00000000 */ ++/** Set */ ++#define ACT_HOST_SET 0x00008000 ++/** Activate I2C ++ Sets the activation flag of the I2C domain. This domain contains the I2C interface block. */ ++#define ACT_I2C 0x00004000 ++/* No-Operation ++#define ACT_I2C_NOP 0x00000000 */ ++/** Set */ ++#define ACT_I2C_SET 0x00004000 ++/** Activate SSC0 ++ Sets the activation flag of the SSC0 domain. This domain contains the SSC0 interface block. */ ++#define ACT_SSC0 0x00002000 ++/* No-Operation ++#define ACT_SSC0_NOP 0x00000000 */ ++/** Set */ ++#define ACT_SSC0_SET 0x00002000 ++/** Activate ASC0 ++ Sets the activation flag of the ASC0 domain. This domain contains the ASC0 interface block. */ ++#define ACT_ASC0 0x00001000 ++/* No-Operation ++#define ACT_ASC0_NOP 0x00000000 */ ++/** Set */ ++#define ACT_ASC0_SET 0x00001000 ++/** Activate ASC1 ++ Sets the activation flag of the ASC1 domain. This domain contains the ASC1 block. */ ++#define ACT_ASC1 0x00000800 ++/* No-Operation ++#define ACT_ASC1_NOP 0x00000000 */ ++/** Set */ ++#define ACT_ASC1_SET 0x00000800 ++/** Activate DCDCAPD ++ Sets the activation flag of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ ++#define ACT_DCDCAPD 0x00000400 ++/* No-Operation ++#define ACT_DCDCAPD_NOP 0x00000000 */ ++/** Set */ ++#define ACT_DCDCAPD_SET 0x00000400 ++/** Activate DCDCDDR ++ Sets the activation flag of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ ++#define ACT_DCDCDDR 0x00000200 ++/* No-Operation ++#define ACT_DCDCDDR_NOP 0x00000000 */ ++/** Set */ ++#define ACT_DCDCDDR_SET 0x00000200 ++/** Activate DCDC1V0 ++ Sets the activation flag of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ ++#define ACT_DCDC1V0 0x00000100 ++/* No-Operation ++#define ACT_DCDC1V0_NOP 0x00000000 */ ++/** Set */ ++#define ACT_DCDC1V0_SET 0x00000100 ++/** Activate TRC2MEM ++ Sets the activation flag of the TRC2MEM domain. This domain contains the TRC2MEM block. */ ++#define ACT_TRC2MEM 0x00000040 ++/* No-Operation ++#define ACT_TRC2MEM_NOP 0x00000000 */ ++/** Set */ ++#define ACT_TRC2MEM_SET 0x00000040 ++/** Activate DDR ++ Sets the activation flag of the DDR domain. This domain contains the DDR interface block. */ ++#define ACT_DDR 0x00000020 ++/* No-Operation ++#define ACT_DDR_NOP 0x00000000 */ ++/** Set */ ++#define ACT_DDR_SET 0x00000020 ++/** Activate EBU ++ Sets the activation flag of the EBU domain. This domain contains the EBU interface block. */ ++#define ACT_EBU 0x00000010 ++/* No-Operation ++#define ACT_EBU_NOP 0x00000000 */ ++/** Set */ ++#define ACT_EBU_SET 0x00000010 ++ ++/* Fields of "Deactivation Register" */ ++/** Deactivate STATUS ++ Clears the activation flag of the STATUS domain. This domain contains the STATUS block. */ ++#define DEACT_STATUS 0x80000000 ++/* No-Operation ++#define DEACT_STATUS_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_STATUS_CLR 0x80000000 ++/** Deactivate SHA1 ++ Clears the activation flag of the SHA1 domain. This domain contains the SHA1 block. */ ++#define DEACT_SHA1 0x40000000 ++/* No-Operation ++#define DEACT_SHA1_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_SHA1_CLR 0x40000000 ++/** Deactivate AES ++ Clears the activation flag of the AES domain. This domain contains the AES block. */ ++#define DEACT_AES 0x20000000 ++/* No-Operation ++#define DEACT_AES_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_AES_CLR 0x20000000 ++/** Deactivate PCM ++ Clears the activation flag of the PCM domain. This domain contains the PCM interface block. */ ++#define DEACT_PCM 0x10000000 ++/* No-Operation ++#define DEACT_PCM_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_PCM_CLR 0x10000000 ++/** Deactivate FSCT ++ Clears the activation flag of the FSCT domain. This domain contains the FSCT block. */ ++#define DEACT_FSCT 0x08000000 ++/* No-Operation ++#define DEACT_FSCT_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_FSCT_CLR 0x08000000 ++/** Deactivate GPTC ++ Clears the activation flag of the GPTC domain. This domain contains the GPTC block. */ ++#define DEACT_GPTC 0x04000000 ++/* No-Operation ++#define DEACT_GPTC_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_GPTC_CLR 0x04000000 ++/** Deactivate MPS ++ Clears the activation flag of the MPS domain. This domain contains the MPS block. */ ++#define DEACT_MPS 0x02000000 ++/* No-Operation ++#define DEACT_MPS_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_MPS_CLR 0x02000000 ++/** Deactivate DFEV0 ++ Clears the activation flag of the DFEV0 domain. This domain contains the DFEV0 block. */ ++#define DEACT_DFEV0 0x01000000 ++/* No-Operation ++#define DEACT_DFEV0_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_DFEV0_CLR 0x01000000 ++/** Deactivate PADCTRL4 ++ Clears the activation flag of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ ++#define DEACT_PADCTRL4 0x00400000 ++/* No-Operation ++#define DEACT_PADCTRL4_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_PADCTRL4_CLR 0x00400000 ++/** Deactivate PADCTRL3 ++ Clears the activation flag of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ ++#define DEACT_PADCTRL3 0x00200000 ++/* No-Operation ++#define DEACT_PADCTRL3_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_PADCTRL3_CLR 0x00200000 ++/** Deactivate PADCTRL1 ++ Clears the activation flag of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ ++#define DEACT_PADCTRL1 0x00100000 ++/* No-Operation ++#define DEACT_PADCTRL1_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_PADCTRL1_CLR 0x00100000 ++/** Deactivate P4 ++ Clears the activation flag of the P4 domain. This domain contains the P4 instance of the GPIO block. */ ++#define DEACT_P4 0x00040000 ++/* No-Operation ++#define DEACT_P4_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_P4_CLR 0x00040000 ++/** Deactivate P3 ++ Clears the activation flag of the P3 domain. This domain contains the P3 instance of the GPIO block. */ ++#define DEACT_P3 0x00020000 ++/* No-Operation ++#define DEACT_P3_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_P3_CLR 0x00020000 ++/** Deactivate P1 ++ Clears the activation flag of the P1 domain. This domain contains the P1 instance of the GPIO block. */ ++#define DEACT_P1 0x00010000 ++/* No-Operation ++#define DEACT_P1_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_P1_CLR 0x00010000 ++/** Deactivate HOST ++ Clears the activation flag of the HOST domain. This domain contains the HOST interface block. */ ++#define DEACT_HOST 0x00008000 ++/* No-Operation ++#define DEACT_HOST_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_HOST_CLR 0x00008000 ++/** Deactivate I2C ++ Clears the activation flag of the I2C domain. This domain contains the I2C interface block. */ ++#define DEACT_I2C 0x00004000 ++/* No-Operation ++#define DEACT_I2C_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_I2C_CLR 0x00004000 ++/** Deactivate SSC0 ++ Clears the activation flag of the SSC0 domain. This domain contains the SSC0 interface block. */ ++#define DEACT_SSC0 0x00002000 ++/* No-Operation ++#define DEACT_SSC0_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_SSC0_CLR 0x00002000 ++/** Deactivate ASC0 ++ Clears the activation flag of the ASC0 domain. This domain contains the ASC0 interface block. */ ++#define DEACT_ASC0 0x00001000 ++/* No-Operation ++#define DEACT_ASC0_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_ASC0_CLR 0x00001000 ++/** Deactivate ASC1 ++ Clears the activation flag of the ASC1 domain. This domain contains the ASC1 block. */ ++#define DEACT_ASC1 0x00000800 ++/* No-Operation ++#define DEACT_ASC1_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_ASC1_CLR 0x00000800 ++/** Deactivate DCDCAPD ++ Clears the activation flag of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ ++#define DEACT_DCDCAPD 0x00000400 ++/* No-Operation ++#define DEACT_DCDCAPD_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_DCDCAPD_CLR 0x00000400 ++/** Deactivate DCDCDDR ++ Clears the activation flag of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ ++#define DEACT_DCDCDDR 0x00000200 ++/* No-Operation ++#define DEACT_DCDCDDR_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_DCDCDDR_CLR 0x00000200 ++/** Deactivate DCDC1V0 ++ Clears the activation flag of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ ++#define DEACT_DCDC1V0 0x00000100 ++/* No-Operation ++#define DEACT_DCDC1V0_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_DCDC1V0_CLR 0x00000100 ++/** Deactivate TRC2MEM ++ Clears the activation flag of the TRC2MEM domain. This domain contains the TRC2MEM block. */ ++#define DEACT_TRC2MEM 0x00000040 ++/* No-Operation ++#define DEACT_TRC2MEM_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_TRC2MEM_CLR 0x00000040 ++/** Deactivate DDR ++ Clears the activation flag of the DDR domain. This domain contains the DDR interface block. */ ++#define DEACT_DDR 0x00000020 ++/* No-Operation ++#define DEACT_DDR_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_DDR_CLR 0x00000020 ++/** Deactivate EBU ++ Clears the activation flag of the EBU domain. This domain contains the EBU interface block. */ ++#define DEACT_EBU 0x00000010 ++/* No-Operation ++#define DEACT_EBU_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_EBU_CLR 0x00000010 ++ ++/* Fields of "Reboot Trigger Register" */ ++/** Reboot STATUS ++ Triggers a reboot of the STATUS domain. This domain contains the STATUS block. */ ++#define RBT_STATUS 0x80000000 ++/* No-Operation ++#define RBT_STATUS_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_STATUS_TRIG 0x80000000 ++/** Reboot SHA1 ++ Triggers a reboot of the SHA1 domain. This domain contains the SHA1 block. */ ++#define RBT_SHA1 0x40000000 ++/* No-Operation ++#define RBT_SHA1_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_SHA1_TRIG 0x40000000 ++/** Reboot AES ++ Triggers a reboot of the AES domain. This domain contains the AES block. */ ++#define RBT_AES 0x20000000 ++/* No-Operation ++#define RBT_AES_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_AES_TRIG 0x20000000 ++/** Reboot PCM ++ Triggers a reboot of the PCM domain. This domain contains the PCM interface block. */ ++#define RBT_PCM 0x10000000 ++/* No-Operation ++#define RBT_PCM_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_PCM_TRIG 0x10000000 ++/** Reboot FSCT ++ Triggers a reboot of the FSCT domain. This domain contains the FSCT block. */ ++#define RBT_FSCT 0x08000000 ++/* No-Operation ++#define RBT_FSCT_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_FSCT_TRIG 0x08000000 ++/** Reboot GPTC ++ Triggers a reboot of the GPTC domain. This domain contains the GPTC block. */ ++#define RBT_GPTC 0x04000000 ++/* No-Operation ++#define RBT_GPTC_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_GPTC_TRIG 0x04000000 ++/** Reboot MPS ++ Triggers a reboot of the MPS domain. This domain contains the MPS block. */ ++#define RBT_MPS 0x02000000 ++/* No-Operation ++#define RBT_MPS_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_MPS_TRIG 0x02000000 ++/** Reboot DFEV0 ++ Triggers a reboot of the DFEV0 domain. This domain contains the DFEV0 block. */ ++#define RBT_DFEV0 0x01000000 ++/* No-Operation ++#define RBT_DFEV0_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_DFEV0_TRIG 0x01000000 ++/** Reboot PADCTRL4 ++ Triggers a reboot of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ ++#define RBT_PADCTRL4 0x00400000 ++/* No-Operation ++#define RBT_PADCTRL4_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_PADCTRL4_TRIG 0x00400000 ++/** Reboot PADCTRL3 ++ Triggers a reboot of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ ++#define RBT_PADCTRL3 0x00200000 ++/* No-Operation ++#define RBT_PADCTRL3_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_PADCTRL3_TRIG 0x00200000 ++/** Reboot PADCTRL1 ++ Triggers a reboot of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ ++#define RBT_PADCTRL1 0x00100000 ++/* No-Operation ++#define RBT_PADCTRL1_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_PADCTRL1_TRIG 0x00100000 ++/** Reboot P4 ++ Triggers a reboot of the P4 domain. This domain contains the P4 instance of the GPIO block. */ ++#define RBT_P4 0x00040000 ++/* No-Operation ++#define RBT_P4_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_P4_TRIG 0x00040000 ++/** Reboot P3 ++ Triggers a reboot of the P3 domain. This domain contains the P3 instance of the GPIO block. */ ++#define RBT_P3 0x00020000 ++/* No-Operation ++#define RBT_P3_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_P3_TRIG 0x00020000 ++/** Reboot P1 ++ Triggers a reboot of the P1 domain. This domain contains the P1 instance of the GPIO block. */ ++#define RBT_P1 0x00010000 ++/* No-Operation ++#define RBT_P1_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_P1_TRIG 0x00010000 ++/** Reboot HOST ++ Triggers a reboot of the HOST domain. This domain contains the HOST interface block. */ ++#define RBT_HOST 0x00008000 ++/* No-Operation ++#define RBT_HOST_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_HOST_TRIG 0x00008000 ++/** Reboot I2C ++ Triggers a reboot of the I2C domain. This domain contains the I2C interface block. */ ++#define RBT_I2C 0x00004000 ++/* No-Operation ++#define RBT_I2C_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_I2C_TRIG 0x00004000 ++/** Reboot SSC0 ++ Triggers a reboot of the SSC0 domain. This domain contains the SSC0 interface block. */ ++#define RBT_SSC0 0x00002000 ++/* No-Operation ++#define RBT_SSC0_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_SSC0_TRIG 0x00002000 ++/** Reboot ASC0 ++ Triggers a reboot of the ASC0 domain. This domain contains the ASC0 interface block. */ ++#define RBT_ASC0 0x00001000 ++/* No-Operation ++#define RBT_ASC0_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_ASC0_TRIG 0x00001000 ++/** Reboot ASC1 ++ Triggers a reboot of the ASC1 domain. This domain contains the ASC1 block. */ ++#define RBT_ASC1 0x00000800 ++/* No-Operation ++#define RBT_ASC1_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_ASC1_TRIG 0x00000800 ++/** Reboot DCDCAPD ++ Triggers a reboot of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ ++#define RBT_DCDCAPD 0x00000400 ++/* No-Operation ++#define RBT_DCDCAPD_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_DCDCAPD_TRIG 0x00000400 ++/** Reboot DCDCDDR ++ Triggers a reboot of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ ++#define RBT_DCDCDDR 0x00000200 ++/* No-Operation ++#define RBT_DCDCDDR_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_DCDCDDR_TRIG 0x00000200 ++/** Reboot DCDC1V0 ++ Triggers a reboot of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ ++#define RBT_DCDC1V0 0x00000100 ++/* No-Operation ++#define RBT_DCDC1V0_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_DCDC1V0_TRIG 0x00000100 ++/** Reboot TRC2MEM ++ Triggers a reboot of the TRC2MEM domain. This domain contains the TRC2MEM block. */ ++#define RBT_TRC2MEM 0x00000040 ++/* No-Operation ++#define RBT_TRC2MEM_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_TRC2MEM_TRIG 0x00000040 ++/** Reboot DDR ++ Triggers a reboot of the DDR domain. This domain contains the DDR interface block. */ ++#define RBT_DDR 0x00000020 ++/* No-Operation ++#define RBT_DDR_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_DDR_TRIG 0x00000020 ++/** Reboot EBU ++ Triggers a reboot of the EBU domain. This domain contains the EBU interface block. */ ++#define RBT_EBU 0x00000010 ++/* No-Operation ++#define RBT_EBU_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_EBU_TRIG 0x00000010 ++/** Reboot XBAR ++ Triggers a reboot of the XBAR. */ ++#define RBT_XBAR 0x00000002 ++/* No-Operation ++#define RBT_XBAR_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_XBAR_TRIG 0x00000002 ++/** Reboot CPU ++ Triggers a reboot of the CPU. */ ++#define RBT_CPU 0x00000001 ++/* No-Operation ++#define RBT_CPU_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_CPU_TRIG 0x00000001 ++ ++/* Fields of "CPU0 Clock Control Register" */ ++/** CPU Clock Divider ++ Via this bit the divider and therefore the frequency of the clock of CPU0 can be selected. */ ++#define CPU0CC_CPUDIV 0x00000001 ++/* Frequency set to the nominal value. ++#define CPU0CC_CPUDIV_SELFNOM 0x00000000 */ ++/** Frequency set to half of its nominal value. */ ++#define CPU0CC_CPUDIV_SELFHALF 0x00000001 ++ ++/* Fields of "CPU0 Reset Source Register" */ ++/** Software Reboot Request Occurred ++ This bit can be acknowledged by a write operation. */ ++#define CPU0RS_SWRRO 0x00000004 ++/* Nothing ++#define CPU0RS_SWRRO_NULL 0x00000000 */ ++/** Write: Acknowledge the event. */ ++#define CPU0RS_SWRRO_EVACK 0x00000004 ++/** Read: Event occurred. */ ++#define CPU0RS_SWRRO_EVOCC 0x00000004 ++/** Hardware Reset Source ++ Reflects the root cause for the last hardware reset. The infrastructure-block is only reset in case of POR. For all other blocks there is no difference between the three HW-reset sources. */ ++#define CPU0RS_HWRS_MASK 0x00000003 ++/** field offset */ ++#define CPU0RS_HWRS_OFFSET 0 ++/** Power-on reset. */ ++#define CPU0RS_HWRS_POR 0x00000000 ++/** RST pin. */ ++#define CPU0RS_HWRS_RST 0x00000001 ++/** Watchdog reset request. */ ++#define CPU0RS_HWRS_WDT 0x00000002 ++ ++/* Fields of "CPU0 Wakeup Configuration Register" */ ++/** Wakeup Request Source Yield Resume 15 ++ Select the signal connected to the yield/resume interface pin 15 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR15 0x80000000 ++/* Not selected ++#define CPU0WCFG_WRSYR15_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR15_SEL 0x80000000 ++/** Wakeup Request Source Yield Resume 14 ++ Select the signal connected to the yield/resume interface pin 14 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR14 0x40000000 ++/* Not selected ++#define CPU0WCFG_WRSYR14_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR14_SEL 0x40000000 ++/** Wakeup Request Source Yield Resume 13 ++ Select the signal connected to the yield/resume interface pin 13 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR13 0x20000000 ++/* Not selected ++#define CPU0WCFG_WRSYR13_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR13_SEL 0x20000000 ++/** Wakeup Request Source Yield Resume 12 ++ Select the signal connected to the yield/resume interface pin 12 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR12 0x10000000 ++/* Not selected ++#define CPU0WCFG_WRSYR12_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR12_SEL 0x10000000 ++/** Wakeup Request Source Yield Resume 11 ++ Select the signal connected to the yield/resume interface pin 11 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR11 0x08000000 ++/* Not selected ++#define CPU0WCFG_WRSYR11_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR11_SEL 0x08000000 ++/** Wakeup Request Source Yield Resume 10 ++ Select the signal connected to the yield/resume interface pin 10 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR10 0x04000000 ++/* Not selected ++#define CPU0WCFG_WRSYR10_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR10_SEL 0x04000000 ++/** Wakeup Request Source Yield Resume 9 ++ Select the signal connected to the yield/resume interface pin 9 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR9 0x02000000 ++/* Not selected ++#define CPU0WCFG_WRSYR9_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR9_SEL 0x02000000 ++/** Wakeup Request Source Yield Resume 8 ++ Select the signal connected to the yield/resume interface pin 8 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR8 0x01000000 ++/* Not selected ++#define CPU0WCFG_WRSYR8_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR8_SEL 0x01000000 ++/** Wakeup Request Source Yield Resume 7 ++ Select the signal connected to the yield/resume interface pin 7 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR7 0x00800000 ++/* Not selected ++#define CPU0WCFG_WRSYR7_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR7_SEL 0x00800000 ++/** Wakeup Request Source Yield Resume 6 ++ Select the signal connected to the yield/resume interface pin 6 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR6 0x00400000 ++/* Not selected ++#define CPU0WCFG_WRSYR6_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR6_SEL 0x00400000 ++/** Wakeup Request Source Yield Resume 5 ++ Select the signal connected to the yield/resume interface pin 5 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR5 0x00200000 ++/* Not selected ++#define CPU0WCFG_WRSYR5_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR5_SEL 0x00200000 ++/** Wakeup Request Source Yield Resume 4 ++ Select the signal connected to the yield/resume interface pin 4 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR4 0x00100000 ++/* Not selected ++#define CPU0WCFG_WRSYR4_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR4_SEL 0x00100000 ++/** Wakeup Request Source Yield Resume 3 ++ Select the signal connected to the yield/resume interface pin 3 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR3 0x00080000 ++/* Not selected ++#define CPU0WCFG_WRSYR3_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR3_SEL 0x00080000 ++/** Wakeup Request Source Yield Resume 2 ++ Select the signal connected to the yield/resume interface pin 2 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR2 0x00040000 ++/* Not selected ++#define CPU0WCFG_WRSYR2_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR2_SEL 0x00040000 ++/** Wakeup Request Source Yield Resume 1 ++ Select the signal connected to the yield/resume interface pin 1 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR1 0x00020000 ++/* Not selected ++#define CPU0WCFG_WRSYR1_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR1_SEL 0x00020000 ++/** Wakeup Request Source Yield Resume 0 ++ Select the signal connected to the yield/resume interface pin 0 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR0 0x00010000 ++/* Not selected ++#define CPU0WCFG_WRSYR0_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR0_SEL 0x00010000 ++/** Wakeup Request Source Debug ++ Select signal EJ_DINT as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSDBG 0x00000100 ++/* Not selected ++#define CPU0WCFG_WRSDBG_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSDBG_SEL 0x00000100 ++/** Wakeup Request Source ICU of VPE1 ++ Select signal ICU_IRQ of VPE1 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSICUVPE1 0x00000002 ++/* Not selected ++#define CPU0WCFG_WRSICUVPE1_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSICUVPE1_SEL 0x00000002 ++/** Wakeup Request Source ICU of VPE0 ++ Select signal ICU_IRQ of VPE0 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSICUVPE0 0x00000001 ++/* Not selected ++#define CPU0WCFG_WRSICUVPE0_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSICUVPE0_SEL 0x00000001 ++ ++/* Fields of "Bootmode Control Register" */ ++/** Software Bootmode Select ++ Enables SW writing of Bootmode and shows whether or not the SW-programmed bootmode is reflected in field Bootmode instead of the hardware given value. */ ++#define BMC_BMSW 0x80000000 ++/* Disable ++#define BMC_BMSW_DIS 0x00000000 */ ++/** Enable */ ++#define BMC_BMSW_EN 0x80000000 ++/** Bootmode ++ Initially this field holds the value of the pinstraps LED_BMODEx on positions 5:0, and the value of the corresponding JTAG register bit on position 6. Writing is enabled by setting Software Bootmode Select to 1 during the write cycle. */ ++#define BMC_BM_MASK 0x0000007F ++/** field offset */ ++#define BMC_BM_OFFSET 0 ++ ++/* Fields of "Sleep Configuration Register" */ ++/** Enable XBAR Clockoff When All XBAR masters Clockoff ++ Enable XBAR clock shutdown in case all XBAR masters are in clockoff mode. This bit has no effect if bit CPU0 is not enabled. */ ++#define SCFG_XBAR 0x00010000 ++/* Disable ++#define SCFG_XBAR_DIS 0x00000000 */ ++/** Enable */ ++#define SCFG_XBAR_EN 0x00010000 ++/** CPU0 Clockoff On Sleep ++ Enable CPU0 clock shutdown in case its SI_SLEEP signal becomes active. */ ++#define SCFG_CPU0 0x00000001 ++/* Disable ++#define SCFG_CPU0_DIS 0x00000000 */ ++/** Enable */ ++#define SCFG_CPU0_EN 0x00000001 ++ ++/* Fields of "Power Down Configuration Register" */ ++/** Enable Power Down STATUS ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_STATUS 0x80000000 ++/* Disable ++#define PDCFG_STATUS_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_STATUS_EN 0x80000000 ++/** Enable Power Down SHA1 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_SHA1 0x40000000 ++/* Disable ++#define PDCFG_SHA1_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_SHA1_EN 0x40000000 ++/** Enable Power Down AES ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_AES 0x20000000 ++/* Disable ++#define PDCFG_AES_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_AES_EN 0x20000000 ++/** Enable Power Down PCM ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_PCM 0x10000000 ++/* Disable ++#define PDCFG_PCM_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_PCM_EN 0x10000000 ++/** Enable Power Down FSCT ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_FSCT 0x08000000 ++/* Disable ++#define PDCFG_FSCT_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_FSCT_EN 0x08000000 ++/** Enable Power Down GPTC ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_GPTC 0x04000000 ++/* Disable ++#define PDCFG_GPTC_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_GPTC_EN 0x04000000 ++/** Enable Power Down MPS ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_MPS 0x02000000 ++/* Disable ++#define PDCFG_MPS_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_MPS_EN 0x02000000 ++/** Enable Power Down DFEV0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_DFEV0 0x01000000 ++/* Disable ++#define PDCFG_DFEV0_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_DFEV0_EN 0x01000000 ++/** Enable Power Down PADCTRL4 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_PADCTRL4 0x00400000 ++/* Disable ++#define PDCFG_PADCTRL4_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_PADCTRL4_EN 0x00400000 ++/** Enable Power Down PADCTRL3 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_PADCTRL3 0x00200000 ++/* Disable ++#define PDCFG_PADCTRL3_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_PADCTRL3_EN 0x00200000 ++/** Enable Power Down PADCTRL1 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_PADCTRL1 0x00100000 ++/* Disable ++#define PDCFG_PADCTRL1_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_PADCTRL1_EN 0x00100000 ++/** Enable Power Down P4 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_P4 0x00040000 ++/* Disable ++#define PDCFG_P4_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_P4_EN 0x00040000 ++/** Enable Power Down P3 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_P3 0x00020000 ++/* Disable ++#define PDCFG_P3_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_P3_EN 0x00020000 ++/** Enable Power Down P1 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_P1 0x00010000 ++/* Disable ++#define PDCFG_P1_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_P1_EN 0x00010000 ++/** Enable Power Down HOST ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_HOST 0x00008000 ++/* Disable ++#define PDCFG_HOST_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_HOST_EN 0x00008000 ++/** Enable Power Down I2C ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_I2C 0x00004000 ++/* Disable ++#define PDCFG_I2C_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_I2C_EN 0x00004000 ++/** Enable Power Down SSC0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_SSC0 0x00002000 ++/* Disable ++#define PDCFG_SSC0_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_SSC0_EN 0x00002000 ++/** Enable Power Down ASC0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_ASC0 0x00001000 ++/* Disable ++#define PDCFG_ASC0_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_ASC0_EN 0x00001000 ++/** Enable Power Down ASC1 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_ASC1 0x00000800 ++/* Disable ++#define PDCFG_ASC1_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_ASC1_EN 0x00000800 ++/** Enable Power Down DCDCAPD ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_DCDCAPD 0x00000400 ++/* Disable ++#define PDCFG_DCDCAPD_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_DCDCAPD_EN 0x00000400 ++/** Enable Power Down DCDCDDR ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_DCDCDDR 0x00000200 ++/* Disable ++#define PDCFG_DCDCDDR_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_DCDCDDR_EN 0x00000200 ++/** Enable Power Down DCDC1V0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_DCDC1V0 0x00000100 ++/* Disable ++#define PDCFG_DCDC1V0_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_DCDC1V0_EN 0x00000100 ++/** Enable Power Down TRC2MEM ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_TRC2MEM 0x00000040 ++/* Disable ++#define PDCFG_TRC2MEM_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_TRC2MEM_EN 0x00000040 ++/** Enable Power Down DDR ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_DDR 0x00000020 ++/* Disable ++#define PDCFG_DDR_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_DDR_EN 0x00000020 ++/** Enable Power Down EBU ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_EBU 0x00000010 ++/* Disable ++#define PDCFG_EBU_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_EBU_EN 0x00000010 ++ ++/* Fields of "CLKO Pad Control Register" */ ++/** Ethernet Reference Clock CLKO Select ++ Selects the CLKO pad's input as source for the GPHY, SGMII PLLs. */ ++#define CLKOC_ETHREF 0x00000002 ++/* Not selected ++#define CLKOC_ETHREF_NSEL 0x00000000 */ ++/** Selected */ ++#define CLKOC_ETHREF_SEL 0x00000002 ++/** Output Enable ++ Enables the output driver of the CLKO pad. */ ++#define CLKOC_OEN 0x00000001 ++/* Disable ++#define CLKOC_OEN_DIS 0x00000000 */ ++/** Enable */ ++#define CLKOC_OEN_EN 0x00000001 ++ ++/* Fields of "Infrastructure Control Register" */ ++/** General Purpose Control ++ Backup bits. Currently they are connected as: bit 0 : connected to the configmode_on pin of the pinstrapping block. bit 1 : clock enable of the GPE primary clock. bits 3:2 : frequency select of the GPE primary clock. 00 = 769.2MHz, 01 = 625MHz, 10 = 555.6MHz, 11 = 500MHz All other bits are unconnected. */ ++#define INFRAC_GP_MASK 0x1F000000 ++/** field offset */ ++#define INFRAC_GP_OFFSET 24 ++/** CMOS2CML Ethernet Control ++ CMOS2CML Ethernet Control. */ ++#define INFRAC_CMOS2CML_GPON_MASK 0x0000F000 ++/** field offset */ ++#define INFRAC_CMOS2CML_GPON_OFFSET 12 ++/** CMOS2CML Ethernet Control ++ CMOS2CML Ethernet Control. */ ++#define INFRAC_CMOS2CML_ETH_MASK 0x00000F00 ++/** field offset */ ++#define INFRAC_CMOS2CML_ETH_OFFSET 8 ++/** Dying Gasp Enable ++ Enables the dying gasp detector. */ ++#define INFRAC_DGASPEN 0x00000040 ++/* Disable ++#define INFRAC_DGASPEN_DIS 0x00000000 */ ++/** Enable */ ++#define INFRAC_DGASPEN_EN 0x00000040 ++/** Dying Gasp Hysteresis Control ++ Dying Gasp Hysteresis Control. */ ++#define INFRAC_DGASPHYS_MASK 0x00000030 ++/** field offset */ ++#define INFRAC_DGASPHYS_OFFSET 4 ++/** Linear Regulator 1.5V Enable ++ Enables 1.5V linear regulator. */ ++#define INFRAC_LIN1V5EN 0x00000008 ++/* Disable ++#define INFRAC_LIN1V5EN_DIS 0x00000000 */ ++/** Enable */ ++#define INFRAC_LIN1V5EN_EN 0x00000008 ++/** Linear Regulator 1.5V Control ++ Linear regulator 1.5V control. */ ++#define INFRAC_LIN1V5C_MASK 0x00000007 ++/** field offset */ ++#define INFRAC_LIN1V5C_OFFSET 0 ++ ++/* Fields of "HRST_OUT_N Control Register" */ ++/** HRST_OUT_N Pin Value ++ Controls the value of the HRST_OUT_N pin. */ ++#define HRSTOUTC_VALUE 0x00000001 ++ ++/* Fields of "EBU Clock Control Register" */ ++/** EBU Clock Divider ++ Via this bit the frequency of the clock of the EBU can be selected. */ ++#define EBUCC_EBUDIV 0x00000001 ++/* Frequency set to 50MHz. ++#define EBUCC_EBUDIV_SELF50 0x00000000 */ ++/** Frequency set to 100MHz. */ ++#define EBUCC_EBUDIV_SELF100 0x00000001 ++ ++/* Fields of "NMI Status Register" */ ++/** NMI Status Flag TEST ++ Shows whether the event NMI TEST occurred. */ ++#define NMIS_TEST 0x00000100 ++/* Nothing ++#define NMIS_TEST_NULL 0x00000000 */ ++/** Read: Event occurred. */ ++#define NMIS_TEST_EVOCC 0x00000100 ++/** NMI Status Flag DGASP ++ Shows whether the event NMI DGASP occurred. */ ++#define NMIS_DGASP 0x00000004 ++/* Nothing ++#define NMIS_DGASP_NULL 0x00000000 */ ++/** Read: Event occurred. */ ++#define NMIS_DGASP_EVOCC 0x00000004 ++/** NMI Status Flag HOST ++ Shows whether the event NMI HOST occurred. */ ++#define NMIS_HOST 0x00000002 ++/* Nothing ++#define NMIS_HOST_NULL 0x00000000 */ ++/** Read: Event occurred. */ ++#define NMIS_HOST_EVOCC 0x00000002 ++/** NMI Status Flag PIN ++ Shows whether the event NMI PIN occurred. */ ++#define NMIS_PIN 0x00000001 ++/* Nothing ++#define NMIS_PIN_NULL 0x00000000 */ ++/** Read: Event occurred. */ ++#define NMIS_PIN_EVOCC 0x00000001 ++ ++/* Fields of "NMI Set Register" */ ++/** Set NMI Status Flag TEST ++ Sets the corresponding NMI status flag. */ ++#define NMISET_TEST 0x00000100 ++/* Nothing ++#define NMISET_TEST_NULL 0x00000000 */ ++/** Set */ ++#define NMISET_TEST_SET 0x00000100 ++/** Set NMI Status Flag DGASP ++ Sets the corresponding NMI status flag. */ ++#define NMISET_DGASP 0x00000004 ++/* Nothing ++#define NMISET_DGASP_NULL 0x00000000 */ ++/** Set */ ++#define NMISET_DGASP_SET 0x00000004 ++/** Set NMI Status Flag HOST ++ Sets the corresponding NMI status flag. */ ++#define NMISET_HOST 0x00000002 ++/* Nothing ++#define NMISET_HOST_NULL 0x00000000 */ ++/** Set */ ++#define NMISET_HOST_SET 0x00000002 ++/** Set NMI Status Flag PIN ++ Sets the corresponding NMI status flag. */ ++#define NMISET_PIN 0x00000001 ++/* Nothing ++#define NMISET_PIN_NULL 0x00000000 */ ++/** Set */ ++#define NMISET_PIN_SET 0x00000001 ++ ++/* Fields of "NMI Clear Register" */ ++/** Clear NMI Status Flag TEST ++ Clears the corresponding NMI status flag. */ ++#define NMICLR_TEST 0x00000100 ++/* Nothing ++#define NMICLR_TEST_NULL 0x00000000 */ ++/** Clear */ ++#define NMICLR_TEST_CLR 0x00000100 ++/** Clear NMI Status Flag DGASP ++ Clears the corresponding NMI status flag. */ ++#define NMICLR_DGASP 0x00000004 ++/* Nothing ++#define NMICLR_DGASP_NULL 0x00000000 */ ++/** Clear */ ++#define NMICLR_DGASP_CLR 0x00000004 ++/** Clear NMI Status Flag HOST ++ Clears the corresponding NMI status flag. */ ++#define NMICLR_HOST 0x00000002 ++/* Nothing ++#define NMICLR_HOST_NULL 0x00000000 */ ++/** Clear */ ++#define NMICLR_HOST_CLR 0x00000002 ++/** Clear NMI Status Flag PIN ++ Clears the corresponding NMI status flag. */ ++#define NMICLR_PIN 0x00000001 ++/* Nothing ++#define NMICLR_PIN_NULL 0x00000000 */ ++/** Clear */ ++#define NMICLR_PIN_CLR 0x00000001 ++ ++/* Fields of "NMI Test Configuration Register" */ ++/** Enable NMI Test Feature ++ Enables the operation of the NMI TEST flag. This is the mask for the Non-Maskable-Interrupt dedicated to SW tests. All others cannot be masked. */ ++#define NMITCFG_TEN 0x00000100 ++/* Disable ++#define NMITCFG_TEN_DIS 0x00000000 */ ++/** Enable */ ++#define NMITCFG_TEN_EN 0x00000100 ++ ++/* Fields of "NMI VPE1 Control Register" */ ++/** NMI VPE1 State ++ Reflects the state of the NMI signal towards VPE1. This bit is controlled by software only, there is no hardware NMI source dedicated to VPE1. So VPE0 could trigger an NMI at VPE1 using this bit in its own NMI-routine. */ ++#define NMIVPE1C_NMI 0x00000001 ++/* False ++#define NMIVPE1C_NMI_FALSE 0x00000000 */ ++/** True */ ++#define NMIVPE1C_NMI_TRUE 0x00000001 ++ ++/* Fields of "IRN Capture Register" */ ++/** DCDCAPD Alarm ++ The DCDC Converter for the APD Supply submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define IRNCR_DCDCAPD 0x00400000 ++/* Nothing ++#define IRNCR_DCDCAPD_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define IRNCR_DCDCAPD_INTACK 0x00400000 ++/** Read: Interrupt occurred. */ ++#define IRNCR_DCDCAPD_INTOCC 0x00400000 ++/** DCDCDDR Alarm ++ The DCDC Converter for the DDR Supply submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define IRNCR_DCDCDDR 0x00200000 ++/* Nothing ++#define IRNCR_DCDCDDR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define IRNCR_DCDCDDR_INTACK 0x00200000 ++/** Read: Interrupt occurred. */ ++#define IRNCR_DCDCDDR_INTOCC 0x00200000 ++/** DCDC1V0 Alarm ++ The DCDC Converter for the 1.0 Volts submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define IRNCR_DCDC1V0 0x00100000 ++/* Nothing ++#define IRNCR_DCDC1V0_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define IRNCR_DCDC1V0_INTACK 0x00100000 ++/** Read: Interrupt occurred. */ ++#define IRNCR_DCDC1V0_INTOCC 0x00100000 ++/** SIF0 wakeup request ++ SmartSlic Interface 0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define IRNCR_SIF0 0x00010000 ++/* Nothing ++#define IRNCR_SIF0_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define IRNCR_SIF0_INTACK 0x00010000 ++/** Read: Interrupt occurred. */ ++#define IRNCR_SIF0_INTOCC 0x00010000 ++ ++/* Fields of "IRN Interrupt Control Register" */ ++/** DCDCAPD Alarm ++ Interrupt control bit for the corresponding bit in the IRNCR register. */ ++#define IRNICR_DCDCAPD 0x00400000 ++/** DCDCDDR Alarm ++ Interrupt control bit for the corresponding bit in the IRNCR register. */ ++#define IRNICR_DCDCDDR 0x00200000 ++/** DCDC1V0 Alarm ++ Interrupt control bit for the corresponding bit in the IRNCR register. */ ++#define IRNICR_DCDC1V0 0x00100000 ++/** SIF0 wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCR register. */ ++#define IRNICR_SIF0 0x00010000 ++ ++/* Fields of "IRN Interrupt Enable Register" */ ++/** DCDCAPD Alarm ++ Interrupt enable bit for the corresponding bit in the IRNCR register. */ ++#define IRNEN_DCDCAPD 0x00400000 ++/* Disable ++#define IRNEN_DCDCAPD_DIS 0x00000000 */ ++/** Enable */ ++#define IRNEN_DCDCAPD_EN 0x00400000 ++/** DCDCDDR Alarm ++ Interrupt enable bit for the corresponding bit in the IRNCR register. */ ++#define IRNEN_DCDCDDR 0x00200000 ++/* Disable ++#define IRNEN_DCDCDDR_DIS 0x00000000 */ ++/** Enable */ ++#define IRNEN_DCDCDDR_EN 0x00200000 ++/** DCDC1V0 Alarm ++ Interrupt enable bit for the corresponding bit in the IRNCR register. */ ++#define IRNEN_DCDC1V0 0x00100000 ++/* Disable ++#define IRNEN_DCDC1V0_DIS 0x00000000 */ ++/** Enable */ ++#define IRNEN_DCDC1V0_EN 0x00100000 ++/** SIF0 wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCR register. */ ++#define IRNEN_SIF0 0x00010000 ++/* Disable ++#define IRNEN_SIF0_DIS 0x00000000 */ ++/** Enable */ ++#define IRNEN_SIF0_EN 0x00010000 ++ ++/*! @} */ /* SYS1_REGISTER */ ++ ++#endif /* _sys1_reg_h */ +diff --git a/arch/mips/include/asm/mach-lantiq/falcon/sys_eth_reg.h b/arch/mips/include/asm/mach-lantiq/falcon/sys_eth_reg.h +new file mode 100644 +index 0000000..e1777e5 +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/sys_eth_reg.h +@@ -0,0 +1,1132 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++ ++#ifndef _sys_eth_reg_h ++#define _sys_eth_reg_h ++ ++/** \addtogroup SYS_ETH_REGISTER ++ @{ ++*/ ++/* access macros */ ++#define sys_eth_r32(reg) reg_r32(&sys_eth->reg) ++#define sys_eth_w32(val, reg) reg_w32(val, &sys_eth->reg) ++#define sys_eth_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys_eth->reg) ++#define sys_eth_r32_table(reg, idx) reg_r32_table(sys_eth->reg, idx) ++#define sys_eth_w32_table(val, reg, idx) reg_w32_table(val, sys_eth->reg, idx) ++#define sys_eth_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys_eth->reg, idx) ++#define sys_eth_adr_table(reg, idx) adr_table(sys_eth->reg, idx) ++ ++ ++/** SYS_ETH register structure */ ++struct gpon_reg_sys_eth ++{ ++ /** Clock Status Register */ ++ unsigned int clks; /* 0x00000000 */ ++ /** Clock Enable Register ++ Via this register the clocks for the domains can be enabled. */ ++ unsigned int clken; /* 0x00000004 */ ++ /** Clock Clear Register ++ Via this register the clocks for the domains can be disabled. */ ++ unsigned int clkclr; /* 0x00000008 */ ++ /** Reserved */ ++ unsigned int res_0[5]; /* 0x0000000C */ ++ /** Activation Status Register */ ++ unsigned int acts; /* 0x00000020 */ ++ /** Activation Register ++ Via this register the domains can be activated. */ ++ unsigned int act; /* 0x00000024 */ ++ /** Deactivation Register ++ Via this register the domains can be deactivated. */ ++ unsigned int deact; /* 0x00000028 */ ++ /** Reboot Trigger Register ++ Via this register the domains can be rebooted (sent through reset). */ ++ unsigned int rbt; /* 0x0000002C */ ++ /** Reserved */ ++ unsigned int res_1[32]; /* 0x00000030 */ ++ /** External PHY Control Register */ ++ unsigned int extphyc; /* 0x000000B0 */ ++ /** Power Down Configuration Register ++ Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be removed. */ ++ unsigned int pdcfg; /* 0x000000B4 */ ++ /** Datarate Control Register ++ Controls the datarate of the various physical layers. The contents of the writeable fields of this register shall not be changed during operation. */ ++ unsigned int drc; /* 0x000000B8 */ ++ /** GMAC Multiplexer Control Register ++ Controls the interconnect between GMACs and the various physical layers. All fields need to have a different content. If two GMACs are muxed to the same PHY unpredictable results may occur. The contents of this register shall not be changed during operation. */ ++ unsigned int gmuxc; /* 0x000000BC */ ++ /** Datarate Status Register ++ Shows the datarate of the GMACs. The datarate of a GMAC is derived from the datarate of the physical layer it is multiplexed to. This register is for debugging only. */ ++ unsigned int drs; /* 0x000000C0 */ ++ /** SGMII Control Register */ ++ unsigned int sgmiic; /* 0x000000C4 */ ++ /** Reserved */ ++ unsigned int res_2[14]; /* 0x000000C8 */ ++}; ++ ++ ++/* Fields of "Clock Status Register" */ ++/** GPHY1MII2 Clock Enable ++ Shows the clock enable bit for GPHY1MII2. */ ++#define SYS_ETH_CLKS_GPHY1MII2 0x02000000 ++/* Disable ++#define SYS_ETH_CLKS_GPHY1MII2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_GPHY1MII2_EN 0x02000000 ++/** GPHY0MII2 Clock Enable ++ Shows the clock enable bit for GPHY0MII2. */ ++#define SYS_ETH_CLKS_GPHY0MII2 0x01000000 ++/* Disable ++#define SYS_ETH_CLKS_GPHY0MII2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_GPHY0MII2_EN 0x01000000 ++/** PADCTRL2 Clock Enable ++ Shows the clock enable bit for the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ ++#define SYS_ETH_CLKS_PADCTRL2 0x00200000 ++/* Disable ++#define SYS_ETH_CLKS_PADCTRL2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_PADCTRL2_EN 0x00200000 ++/** PADCTRL0 Clock Enable ++ Shows the clock enable bit for the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ ++#define SYS_ETH_CLKS_PADCTRL0 0x00100000 ++/* Disable ++#define SYS_ETH_CLKS_PADCTRL0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_PADCTRL0_EN 0x00100000 ++/** P2 Clock Enable ++ Shows the clock enable bit for the P2 domain. This domain contains the P2 instance of the GPIO block. */ ++#define SYS_ETH_CLKS_P2 0x00020000 ++/* Disable ++#define SYS_ETH_CLKS_P2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_P2_EN 0x00020000 ++/** P0 Clock Enable ++ Shows the clock enable bit for the P0 domain. This domain contains the P0 instance of the GPIO block. */ ++#define SYS_ETH_CLKS_P0 0x00010000 ++/* Disable ++#define SYS_ETH_CLKS_P0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_P0_EN 0x00010000 ++/** xMII Clock Enable ++ Shows the clock enable bit for the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ ++#define SYS_ETH_CLKS_xMII 0x00000800 ++/* Disable ++#define SYS_ETH_CLKS_xMII_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_xMII_EN 0x00000800 ++/** SGMII Clock Enable ++ Shows the clock enable bit for the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_CLKS_SGMII 0x00000400 ++/* Disable ++#define SYS_ETH_CLKS_SGMII_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_SGMII_EN 0x00000400 ++/** GPHY1 Clock Enable ++ Shows the clock enable bit for the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_CLKS_GPHY1 0x00000200 ++/* Disable ++#define SYS_ETH_CLKS_GPHY1_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_GPHY1_EN 0x00000200 ++/** GPHY0 Clock Enable ++ Shows the clock enable bit for the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_CLKS_GPHY0 0x00000100 ++/* Disable ++#define SYS_ETH_CLKS_GPHY0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_GPHY0_EN 0x00000100 ++/** MDIO Clock Enable ++ Shows the clock enable bit for the MDIO domain. This domain contains the MDIO block. */ ++#define SYS_ETH_CLKS_MDIO 0x00000080 ++/* Disable ++#define SYS_ETH_CLKS_MDIO_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_MDIO_EN 0x00000080 ++/** GMAC3 Clock Enable ++ Shows the clock enable bit for the GMAC3 domain. This domain contains the GMAC3 block. */ ++#define SYS_ETH_CLKS_GMAC3 0x00000008 ++/* Disable ++#define SYS_ETH_CLKS_GMAC3_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_GMAC3_EN 0x00000008 ++/** GMAC2 Clock Enable ++ Shows the clock enable bit for the GMAC2 domain. This domain contains the GMAC2 block. */ ++#define SYS_ETH_CLKS_GMAC2 0x00000004 ++/* Disable ++#define SYS_ETH_CLKS_GMAC2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_GMAC2_EN 0x00000004 ++/** GMAC1 Clock Enable ++ Shows the clock enable bit for the GMAC1 domain. This domain contains the GMAC1 block. */ ++#define SYS_ETH_CLKS_GMAC1 0x00000002 ++/* Disable ++#define SYS_ETH_CLKS_GMAC1_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_GMAC1_EN 0x00000002 ++/** GMAC0 Clock Enable ++ Shows the clock enable bit for the GMAC0 domain. This domain contains the GMAC0 block. */ ++#define SYS_ETH_CLKS_GMAC0 0x00000001 ++/* Disable ++#define SYS_ETH_CLKS_GMAC0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_GMAC0_EN 0x00000001 ++ ++/* Fields of "Clock Enable Register" */ ++/** Set Clock Enable GPHY1MII2 ++ Sets the clock enable bit of the GPHY1MII2. */ ++#define SYS_ETH_CLKEN_GPHY1MII2 0x02000000 ++/* No-Operation ++#define SYS_ETH_CLKEN_GPHY1MII2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_GPHY1MII2_SET 0x02000000 ++/** Set Clock Enable GPHY0MII2 ++ Sets the clock enable bit of the GPHY0MII2. */ ++#define SYS_ETH_CLKEN_GPHY0MII2 0x01000000 ++/* No-Operation ++#define SYS_ETH_CLKEN_GPHY0MII2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_GPHY0MII2_SET 0x01000000 ++/** Set Clock Enable PADCTRL2 ++ Sets the clock enable bit of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ ++#define SYS_ETH_CLKEN_PADCTRL2 0x00200000 ++/* No-Operation ++#define SYS_ETH_CLKEN_PADCTRL2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_PADCTRL2_SET 0x00200000 ++/** Set Clock Enable PADCTRL0 ++ Sets the clock enable bit of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ ++#define SYS_ETH_CLKEN_PADCTRL0 0x00100000 ++/* No-Operation ++#define SYS_ETH_CLKEN_PADCTRL0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_PADCTRL0_SET 0x00100000 ++/** Set Clock Enable P2 ++ Sets the clock enable bit of the P2 domain. This domain contains the P2 instance of the GPIO block. */ ++#define SYS_ETH_CLKEN_P2 0x00020000 ++/* No-Operation ++#define SYS_ETH_CLKEN_P2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_P2_SET 0x00020000 ++/** Set Clock Enable P0 ++ Sets the clock enable bit of the P0 domain. This domain contains the P0 instance of the GPIO block. */ ++#define SYS_ETH_CLKEN_P0 0x00010000 ++/* No-Operation ++#define SYS_ETH_CLKEN_P0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_P0_SET 0x00010000 ++/** Set Clock Enable xMII ++ Sets the clock enable bit of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ ++#define SYS_ETH_CLKEN_xMII 0x00000800 ++/* No-Operation ++#define SYS_ETH_CLKEN_xMII_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_xMII_SET 0x00000800 ++/** Set Clock Enable SGMII ++ Sets the clock enable bit of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_CLKEN_SGMII 0x00000400 ++/* No-Operation ++#define SYS_ETH_CLKEN_SGMII_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_SGMII_SET 0x00000400 ++/** Set Clock Enable GPHY1 ++ Sets the clock enable bit of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_CLKEN_GPHY1 0x00000200 ++/* No-Operation ++#define SYS_ETH_CLKEN_GPHY1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_GPHY1_SET 0x00000200 ++/** Set Clock Enable GPHY0 ++ Sets the clock enable bit of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_CLKEN_GPHY0 0x00000100 ++/* No-Operation ++#define SYS_ETH_CLKEN_GPHY0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_GPHY0_SET 0x00000100 ++/** Set Clock Enable MDIO ++ Sets the clock enable bit of the MDIO domain. This domain contains the MDIO block. */ ++#define SYS_ETH_CLKEN_MDIO 0x00000080 ++/* No-Operation ++#define SYS_ETH_CLKEN_MDIO_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_MDIO_SET 0x00000080 ++/** Set Clock Enable GMAC3 ++ Sets the clock enable bit of the GMAC3 domain. This domain contains the GMAC3 block. */ ++#define SYS_ETH_CLKEN_GMAC3 0x00000008 ++/* No-Operation ++#define SYS_ETH_CLKEN_GMAC3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_GMAC3_SET 0x00000008 ++/** Set Clock Enable GMAC2 ++ Sets the clock enable bit of the GMAC2 domain. This domain contains the GMAC2 block. */ ++#define SYS_ETH_CLKEN_GMAC2 0x00000004 ++/* No-Operation ++#define SYS_ETH_CLKEN_GMAC2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_GMAC2_SET 0x00000004 ++/** Set Clock Enable GMAC1 ++ Sets the clock enable bit of the GMAC1 domain. This domain contains the GMAC1 block. */ ++#define SYS_ETH_CLKEN_GMAC1 0x00000002 ++/* No-Operation ++#define SYS_ETH_CLKEN_GMAC1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_GMAC1_SET 0x00000002 ++/** Set Clock Enable GMAC0 ++ Sets the clock enable bit of the GMAC0 domain. This domain contains the GMAC0 block. */ ++#define SYS_ETH_CLKEN_GMAC0 0x00000001 ++/* No-Operation ++#define SYS_ETH_CLKEN_GMAC0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_GMAC0_SET 0x00000001 ++ ++/* Fields of "Clock Clear Register" */ ++/** Clear Clock Enable GPHY1MII2 ++ Clears the clock enable bit of the GPHY1MII2. */ ++#define SYS_ETH_CLKCLR_GPHY1MII2 0x02000000 ++/* No-Operation ++#define SYS_ETH_CLKCLR_GPHY1MII2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_GPHY1MII2_CLR 0x02000000 ++/** Clear Clock Enable GPHY0MII2 ++ Clears the clock enable bit of the GPHY0MII2. */ ++#define SYS_ETH_CLKCLR_GPHY0MII2 0x01000000 ++/* No-Operation ++#define SYS_ETH_CLKCLR_GPHY0MII2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_GPHY0MII2_CLR 0x01000000 ++/** Clear Clock Enable PADCTRL2 ++ Clears the clock enable bit of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ ++#define SYS_ETH_CLKCLR_PADCTRL2 0x00200000 ++/* No-Operation ++#define SYS_ETH_CLKCLR_PADCTRL2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_PADCTRL2_CLR 0x00200000 ++/** Clear Clock Enable PADCTRL0 ++ Clears the clock enable bit of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ ++#define SYS_ETH_CLKCLR_PADCTRL0 0x00100000 ++/* No-Operation ++#define SYS_ETH_CLKCLR_PADCTRL0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_PADCTRL0_CLR 0x00100000 ++/** Clear Clock Enable P2 ++ Clears the clock enable bit of the P2 domain. This domain contains the P2 instance of the GPIO block. */ ++#define SYS_ETH_CLKCLR_P2 0x00020000 ++/* No-Operation ++#define SYS_ETH_CLKCLR_P2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_P2_CLR 0x00020000 ++/** Clear Clock Enable P0 ++ Clears the clock enable bit of the P0 domain. This domain contains the P0 instance of the GPIO block. */ ++#define SYS_ETH_CLKCLR_P0 0x00010000 ++/* No-Operation ++#define SYS_ETH_CLKCLR_P0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_P0_CLR 0x00010000 ++/** Clear Clock Enable xMII ++ Clears the clock enable bit of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ ++#define SYS_ETH_CLKCLR_xMII 0x00000800 ++/* No-Operation ++#define SYS_ETH_CLKCLR_xMII_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_xMII_CLR 0x00000800 ++/** Clear Clock Enable SGMII ++ Clears the clock enable bit of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_CLKCLR_SGMII 0x00000400 ++/* No-Operation ++#define SYS_ETH_CLKCLR_SGMII_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_SGMII_CLR 0x00000400 ++/** Clear Clock Enable GPHY1 ++ Clears the clock enable bit of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_CLKCLR_GPHY1 0x00000200 ++/* No-Operation ++#define SYS_ETH_CLKCLR_GPHY1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_GPHY1_CLR 0x00000200 ++/** Clear Clock Enable GPHY0 ++ Clears the clock enable bit of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_CLKCLR_GPHY0 0x00000100 ++/* No-Operation ++#define SYS_ETH_CLKCLR_GPHY0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_GPHY0_CLR 0x00000100 ++/** Clear Clock Enable MDIO ++ Clears the clock enable bit of the MDIO domain. This domain contains the MDIO block. */ ++#define SYS_ETH_CLKCLR_MDIO 0x00000080 ++/* No-Operation ++#define SYS_ETH_CLKCLR_MDIO_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_MDIO_CLR 0x00000080 ++/** Clear Clock Enable GMAC3 ++ Clears the clock enable bit of the GMAC3 domain. This domain contains the GMAC3 block. */ ++#define SYS_ETH_CLKCLR_GMAC3 0x00000008 ++/* No-Operation ++#define SYS_ETH_CLKCLR_GMAC3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_GMAC3_CLR 0x00000008 ++/** Clear Clock Enable GMAC2 ++ Clears the clock enable bit of the GMAC2 domain. This domain contains the GMAC2 block. */ ++#define SYS_ETH_CLKCLR_GMAC2 0x00000004 ++/* No-Operation ++#define SYS_ETH_CLKCLR_GMAC2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_GMAC2_CLR 0x00000004 ++/** Clear Clock Enable GMAC1 ++ Clears the clock enable bit of the GMAC1 domain. This domain contains the GMAC1 block. */ ++#define SYS_ETH_CLKCLR_GMAC1 0x00000002 ++/* No-Operation ++#define SYS_ETH_CLKCLR_GMAC1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_GMAC1_CLR 0x00000002 ++/** Clear Clock Enable GMAC0 ++ Clears the clock enable bit of the GMAC0 domain. This domain contains the GMAC0 block. */ ++#define SYS_ETH_CLKCLR_GMAC0 0x00000001 ++/* No-Operation ++#define SYS_ETH_CLKCLR_GMAC0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_GMAC0_CLR 0x00000001 ++ ++/* Fields of "Activation Status Register" */ ++/** PADCTRL2 Status ++ Shows the activation status of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ ++#define SYS_ETH_ACTS_PADCTRL2 0x00200000 ++/* The block is inactive. ++#define SYS_ETH_ACTS_PADCTRL2_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_PADCTRL2_ACT 0x00200000 ++/** PADCTRL0 Status ++ Shows the activation status of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ ++#define SYS_ETH_ACTS_PADCTRL0 0x00100000 ++/* The block is inactive. ++#define SYS_ETH_ACTS_PADCTRL0_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_PADCTRL0_ACT 0x00100000 ++/** P2 Status ++ Shows the activation status of the P2 domain. This domain contains the P2 instance of the GPIO block. */ ++#define SYS_ETH_ACTS_P2 0x00020000 ++/* The block is inactive. ++#define SYS_ETH_ACTS_P2_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_P2_ACT 0x00020000 ++/** P0 Status ++ Shows the activation status of the P0 domain. This domain contains the P0 instance of the GPIO block. */ ++#define SYS_ETH_ACTS_P0 0x00010000 ++/* The block is inactive. ++#define SYS_ETH_ACTS_P0_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_P0_ACT 0x00010000 ++/** xMII Status ++ Shows the activation status of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ ++#define SYS_ETH_ACTS_xMII 0x00000800 ++/* The block is inactive. ++#define SYS_ETH_ACTS_xMII_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_xMII_ACT 0x00000800 ++/** SGMII Status ++ Shows the activation status of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_ACTS_SGMII 0x00000400 ++/* The block is inactive. ++#define SYS_ETH_ACTS_SGMII_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_SGMII_ACT 0x00000400 ++/** GPHY1 Status ++ Shows the activation status of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_ACTS_GPHY1 0x00000200 ++/* The block is inactive. ++#define SYS_ETH_ACTS_GPHY1_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_GPHY1_ACT 0x00000200 ++/** GPHY0 Status ++ Shows the activation status of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_ACTS_GPHY0 0x00000100 ++/* The block is inactive. ++#define SYS_ETH_ACTS_GPHY0_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_GPHY0_ACT 0x00000100 ++/** MDIO Status ++ Shows the activation status of the MDIO domain. This domain contains the MDIO block. */ ++#define SYS_ETH_ACTS_MDIO 0x00000080 ++/* The block is inactive. ++#define SYS_ETH_ACTS_MDIO_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_MDIO_ACT 0x00000080 ++/** GMAC3 Status ++ Shows the activation status of the GMAC3 domain. This domain contains the GMAC3 block. */ ++#define SYS_ETH_ACTS_GMAC3 0x00000008 ++/* The block is inactive. ++#define SYS_ETH_ACTS_GMAC3_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_GMAC3_ACT 0x00000008 ++/** GMAC2 Status ++ Shows the activation status of the GMAC2 domain. This domain contains the GMAC2 block. */ ++#define SYS_ETH_ACTS_GMAC2 0x00000004 ++/* The block is inactive. ++#define SYS_ETH_ACTS_GMAC2_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_GMAC2_ACT 0x00000004 ++/** GMAC1 Status ++ Shows the activation status of the GMAC1 domain. This domain contains the GMAC1 block. */ ++#define SYS_ETH_ACTS_GMAC1 0x00000002 ++/* The block is inactive. ++#define SYS_ETH_ACTS_GMAC1_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_GMAC1_ACT 0x00000002 ++/** GMAC0 Status ++ Shows the activation status of the GMAC0 domain. This domain contains the GMAC0 block. */ ++#define SYS_ETH_ACTS_GMAC0 0x00000001 ++/* The block is inactive. ++#define SYS_ETH_ACTS_GMAC0_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_GMAC0_ACT 0x00000001 ++ ++/* Fields of "Activation Register" */ ++/** Activate PADCTRL2 ++ Sets the activation flag of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ ++#define SYS_ETH_ACT_PADCTRL2 0x00200000 ++/* No-Operation ++#define SYS_ETH_ACT_PADCTRL2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_PADCTRL2_SET 0x00200000 ++/** Activate PADCTRL0 ++ Sets the activation flag of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ ++#define SYS_ETH_ACT_PADCTRL0 0x00100000 ++/* No-Operation ++#define SYS_ETH_ACT_PADCTRL0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_PADCTRL0_SET 0x00100000 ++/** Activate P2 ++ Sets the activation flag of the P2 domain. This domain contains the P2 instance of the GPIO block. */ ++#define SYS_ETH_ACT_P2 0x00020000 ++/* No-Operation ++#define SYS_ETH_ACT_P2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_P2_SET 0x00020000 ++/** Activate P0 ++ Sets the activation flag of the P0 domain. This domain contains the P0 instance of the GPIO block. */ ++#define SYS_ETH_ACT_P0 0x00010000 ++/* No-Operation ++#define SYS_ETH_ACT_P0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_P0_SET 0x00010000 ++/** Activate xMII ++ Sets the activation flag of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ ++#define SYS_ETH_ACT_xMII 0x00000800 ++/* No-Operation ++#define SYS_ETH_ACT_xMII_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_xMII_SET 0x00000800 ++/** Activate SGMII ++ Sets the activation flag of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_ACT_SGMII 0x00000400 ++/* No-Operation ++#define SYS_ETH_ACT_SGMII_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_SGMII_SET 0x00000400 ++/** Activate GPHY1 ++ Sets the activation flag of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_ACT_GPHY1 0x00000200 ++/* No-Operation ++#define SYS_ETH_ACT_GPHY1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_GPHY1_SET 0x00000200 ++/** Activate GPHY0 ++ Sets the activation flag of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_ACT_GPHY0 0x00000100 ++/* No-Operation ++#define SYS_ETH_ACT_GPHY0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_GPHY0_SET 0x00000100 ++/** Activate MDIO ++ Sets the activation flag of the MDIO domain. This domain contains the MDIO block. */ ++#define SYS_ETH_ACT_MDIO 0x00000080 ++/* No-Operation ++#define SYS_ETH_ACT_MDIO_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_MDIO_SET 0x00000080 ++/** Activate GMAC3 ++ Sets the activation flag of the GMAC3 domain. This domain contains the GMAC3 block. */ ++#define SYS_ETH_ACT_GMAC3 0x00000008 ++/* No-Operation ++#define SYS_ETH_ACT_GMAC3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_GMAC3_SET 0x00000008 ++/** Activate GMAC2 ++ Sets the activation flag of the GMAC2 domain. This domain contains the GMAC2 block. */ ++#define SYS_ETH_ACT_GMAC2 0x00000004 ++/* No-Operation ++#define SYS_ETH_ACT_GMAC2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_GMAC2_SET 0x00000004 ++/** Activate GMAC1 ++ Sets the activation flag of the GMAC1 domain. This domain contains the GMAC1 block. */ ++#define SYS_ETH_ACT_GMAC1 0x00000002 ++/* No-Operation ++#define SYS_ETH_ACT_GMAC1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_GMAC1_SET 0x00000002 ++/** Activate GMAC0 ++ Sets the activation flag of the GMAC0 domain. This domain contains the GMAC0 block. */ ++#define SYS_ETH_ACT_GMAC0 0x00000001 ++/* No-Operation ++#define SYS_ETH_ACT_GMAC0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_GMAC0_SET 0x00000001 ++ ++/* Fields of "Deactivation Register" */ ++/** Deactivate PADCTRL2 ++ Clears the activation flag of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ ++#define SYS_ETH_DEACT_PADCTRL2 0x00200000 ++/* No-Operation ++#define SYS_ETH_DEACT_PADCTRL2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_PADCTRL2_CLR 0x00200000 ++/** Deactivate PADCTRL0 ++ Clears the activation flag of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ ++#define SYS_ETH_DEACT_PADCTRL0 0x00100000 ++/* No-Operation ++#define SYS_ETH_DEACT_PADCTRL0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_PADCTRL0_CLR 0x00100000 ++/** Deactivate P2 ++ Clears the activation flag of the P2 domain. This domain contains the P2 instance of the GPIO block. */ ++#define SYS_ETH_DEACT_P2 0x00020000 ++/* No-Operation ++#define SYS_ETH_DEACT_P2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_P2_CLR 0x00020000 ++/** Deactivate P0 ++ Clears the activation flag of the P0 domain. This domain contains the P0 instance of the GPIO block. */ ++#define SYS_ETH_DEACT_P0 0x00010000 ++/* No-Operation ++#define SYS_ETH_DEACT_P0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_P0_CLR 0x00010000 ++/** Deactivate xMII ++ Clears the activation flag of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ ++#define SYS_ETH_DEACT_xMII 0x00000800 ++/* No-Operation ++#define SYS_ETH_DEACT_xMII_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_xMII_CLR 0x00000800 ++/** Deactivate SGMII ++ Clears the activation flag of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_DEACT_SGMII 0x00000400 ++/* No-Operation ++#define SYS_ETH_DEACT_SGMII_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_SGMII_CLR 0x00000400 ++/** Deactivate GPHY1 ++ Clears the activation flag of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_DEACT_GPHY1 0x00000200 ++/* No-Operation ++#define SYS_ETH_DEACT_GPHY1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_GPHY1_CLR 0x00000200 ++/** Deactivate GPHY0 ++ Clears the activation flag of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_DEACT_GPHY0 0x00000100 ++/* No-Operation ++#define SYS_ETH_DEACT_GPHY0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_GPHY0_CLR 0x00000100 ++/** Deactivate MDIO ++ Clears the activation flag of the MDIO domain. This domain contains the MDIO block. */ ++#define SYS_ETH_DEACT_MDIO 0x00000080 ++/* No-Operation ++#define SYS_ETH_DEACT_MDIO_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_MDIO_CLR 0x00000080 ++/** Deactivate GMAC3 ++ Clears the activation flag of the GMAC3 domain. This domain contains the GMAC3 block. */ ++#define SYS_ETH_DEACT_GMAC3 0x00000008 ++/* No-Operation ++#define SYS_ETH_DEACT_GMAC3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_GMAC3_CLR 0x00000008 ++/** Deactivate GMAC2 ++ Clears the activation flag of the GMAC2 domain. This domain contains the GMAC2 block. */ ++#define SYS_ETH_DEACT_GMAC2 0x00000004 ++/* No-Operation ++#define SYS_ETH_DEACT_GMAC2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_GMAC2_CLR 0x00000004 ++/** Deactivate GMAC1 ++ Clears the activation flag of the GMAC1 domain. This domain contains the GMAC1 block. */ ++#define SYS_ETH_DEACT_GMAC1 0x00000002 ++/* No-Operation ++#define SYS_ETH_DEACT_GMAC1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_GMAC1_CLR 0x00000002 ++/** Deactivate GMAC0 ++ Clears the activation flag of the GMAC0 domain. This domain contains the GMAC0 block. */ ++#define SYS_ETH_DEACT_GMAC0 0x00000001 ++/* No-Operation ++#define SYS_ETH_DEACT_GMAC0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_GMAC0_CLR 0x00000001 ++ ++/* Fields of "Reboot Trigger Register" */ ++/** Reboot PADCTRL2 ++ Triggers a reboot of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ ++#define SYS_ETH_RBT_PADCTRL2 0x00200000 ++/* No-Operation ++#define SYS_ETH_RBT_PADCTRL2_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_PADCTRL2_TRIG 0x00200000 ++/** Reboot PADCTRL0 ++ Triggers a reboot of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ ++#define SYS_ETH_RBT_PADCTRL0 0x00100000 ++/* No-Operation ++#define SYS_ETH_RBT_PADCTRL0_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_PADCTRL0_TRIG 0x00100000 ++/** Reboot P2 ++ Triggers a reboot of the P2 domain. This domain contains the P2 instance of the GPIO block. */ ++#define SYS_ETH_RBT_P2 0x00020000 ++/* No-Operation ++#define SYS_ETH_RBT_P2_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_P2_TRIG 0x00020000 ++/** Reboot P0 ++ Triggers a reboot of the P0 domain. This domain contains the P0 instance of the GPIO block. */ ++#define SYS_ETH_RBT_P0 0x00010000 ++/* No-Operation ++#define SYS_ETH_RBT_P0_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_P0_TRIG 0x00010000 ++/** Reboot xMII ++ Triggers a reboot of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ ++#define SYS_ETH_RBT_xMII 0x00000800 ++/* No-Operation ++#define SYS_ETH_RBT_xMII_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_xMII_TRIG 0x00000800 ++/** Reboot SGMII ++ Triggers a reboot of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_RBT_SGMII 0x00000400 ++/* No-Operation ++#define SYS_ETH_RBT_SGMII_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_SGMII_TRIG 0x00000400 ++/** Reboot GPHY1 ++ Triggers a reboot of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_RBT_GPHY1 0x00000200 ++/* No-Operation ++#define SYS_ETH_RBT_GPHY1_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_GPHY1_TRIG 0x00000200 ++/** Reboot GPHY0 ++ Triggers a reboot of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_RBT_GPHY0 0x00000100 ++/* No-Operation ++#define SYS_ETH_RBT_GPHY0_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_GPHY0_TRIG 0x00000100 ++/** Reboot MDIO ++ Triggers a reboot of the MDIO domain. This domain contains the MDIO block. */ ++#define SYS_ETH_RBT_MDIO 0x00000080 ++/* No-Operation ++#define SYS_ETH_RBT_MDIO_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_MDIO_TRIG 0x00000080 ++/** Reboot GMAC3 ++ Triggers a reboot of the GMAC3 domain. This domain contains the GMAC3 block. */ ++#define SYS_ETH_RBT_GMAC3 0x00000008 ++/* No-Operation ++#define SYS_ETH_RBT_GMAC3_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_GMAC3_TRIG 0x00000008 ++/** Reboot GMAC2 ++ Triggers a reboot of the GMAC2 domain. This domain contains the GMAC2 block. */ ++#define SYS_ETH_RBT_GMAC2 0x00000004 ++/* No-Operation ++#define SYS_ETH_RBT_GMAC2_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_GMAC2_TRIG 0x00000004 ++/** Reboot GMAC1 ++ Triggers a reboot of the GMAC1 domain. This domain contains the GMAC1 block. */ ++#define SYS_ETH_RBT_GMAC1 0x00000002 ++/* No-Operation ++#define SYS_ETH_RBT_GMAC1_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_GMAC1_TRIG 0x00000002 ++/** Reboot GMAC0 ++ Triggers a reboot of the GMAC0 domain. This domain contains the GMAC0 block. */ ++#define SYS_ETH_RBT_GMAC0 0x00000001 ++/* No-Operation ++#define SYS_ETH_RBT_GMAC0_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_GMAC0_TRIG 0x00000001 ++ ++/* Fields of "External PHY Control Register" */ ++/** PHY_CLKO Output Enable ++ Enables the output driver of the PHY_CLKO pin. */ ++#define SYS_ETH_EXTPHYC_CLKEN 0x80000000 ++/* Disable ++#define SYS_ETH_EXTPHYC_CLKEN_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_EXTPHYC_CLKEN_EN 0x80000000 ++/** PHY_CLKO Frequency Select ++ Selects the frequency of the PHY_CLKO pin. */ ++#define SYS_ETH_EXTPHYC_CLKSEL_MASK 0x00000007 ++/** field offset */ ++#define SYS_ETH_EXTPHYC_CLKSEL_OFFSET 0 ++/** 25 MHz. */ ++#define SYS_ETH_EXTPHYC_CLKSEL_F25 0x00000001 ++/** 125 MHz. */ ++#define SYS_ETH_EXTPHYC_CLKSEL_F125 0x00000002 ++/** 50 MHz. */ ++#define SYS_ETH_EXTPHYC_CLKSEL_F50 0x00000005 ++ ++/* Fields of "Power Down Configuration Register" */ ++/** Enable Power Down PADCTRL2 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_PADCTRL2 0x00200000 ++/* Disable ++#define SYS_ETH_PDCFG_PADCTRL2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_PADCTRL2_EN 0x00200000 ++/** Enable Power Down PADCTRL0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_PADCTRL0 0x00100000 ++/* Disable ++#define SYS_ETH_PDCFG_PADCTRL0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_PADCTRL0_EN 0x00100000 ++/** Enable Power Down P2 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_P2 0x00020000 ++/* Disable ++#define SYS_ETH_PDCFG_P2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_P2_EN 0x00020000 ++/** Enable Power Down P0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_P0 0x00010000 ++/* Disable ++#define SYS_ETH_PDCFG_P0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_P0_EN 0x00010000 ++/** Enable Power Down xMII ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_xMII 0x00000800 ++/* Disable ++#define SYS_ETH_PDCFG_xMII_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_xMII_EN 0x00000800 ++/** Enable Power Down SGMII ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_SGMII 0x00000400 ++/* Disable ++#define SYS_ETH_PDCFG_SGMII_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_SGMII_EN 0x00000400 ++/** Enable Power Down GPHY1 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_GPHY1 0x00000200 ++/* Disable ++#define SYS_ETH_PDCFG_GPHY1_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_GPHY1_EN 0x00000200 ++/** Enable Power Down GPHY0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_GPHY0 0x00000100 ++/* Disable ++#define SYS_ETH_PDCFG_GPHY0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_GPHY0_EN 0x00000100 ++/** Enable Power Down MDIO ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_MDIO 0x00000080 ++/* Disable ++#define SYS_ETH_PDCFG_MDIO_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_MDIO_EN 0x00000080 ++/** Enable Power Down GMAC3 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_GMAC3 0x00000008 ++/* Disable ++#define SYS_ETH_PDCFG_GMAC3_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_GMAC3_EN 0x00000008 ++/** Enable Power Down GMAC2 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_GMAC2 0x00000004 ++/* Disable ++#define SYS_ETH_PDCFG_GMAC2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_GMAC2_EN 0x00000004 ++/** Enable Power Down GMAC1 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_GMAC1 0x00000002 ++/* Disable ++#define SYS_ETH_PDCFG_GMAC1_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_GMAC1_EN 0x00000002 ++/** Enable Power Down GMAC0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_GMAC0 0x00000001 ++/* Disable ++#define SYS_ETH_PDCFG_GMAC0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_GMAC0_EN 0x00000001 ++ ++/* Fields of "Datarate Control Register" */ ++/** MDC Clockrate ++ Selects the clockrate of the MDIO interface. */ ++#define SYS_ETH_DRC_MDC_MASK 0x30000000 ++/** field offset */ ++#define SYS_ETH_DRC_MDC_OFFSET 28 ++/** 312.5/128 = appr. 2.44 MHz. */ ++#define SYS_ETH_DRC_MDC_F2M44 0x00000000 ++/** 312.5/64 = appr. 4.88 MHz. */ ++#define SYS_ETH_DRC_MDC_F4M88 0x10000000 ++/** 312.5/32 = appr. 9.77 MHz. */ ++#define SYS_ETH_DRC_MDC_F9M77 0x20000000 ++/** 312.5/16 = appr. 19.5 MHz. */ ++#define SYS_ETH_DRC_MDC_F19M5 0x30000000 ++/** xMII1 Datarate ++ Selects the datarate of the xMII1 interface. */ ++#define SYS_ETH_DRC_xMII1_MASK 0x07000000 ++/** field offset */ ++#define SYS_ETH_DRC_xMII1_OFFSET 24 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRC_xMII1_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRC_xMII1_DR100 0x01000000 ++/** 1000 MBit/s. */ ++#define SYS_ETH_DRC_xMII1_DR1000 0x02000000 ++/** 200 MBit/s. */ ++#define SYS_ETH_DRC_xMII1_DR200 0x05000000 ++/** xMII0 Datarate ++ Selects the datarate of the xMII0 interface. */ ++#define SYS_ETH_DRC_xMII0_MASK 0x00700000 ++/** field offset */ ++#define SYS_ETH_DRC_xMII0_OFFSET 20 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRC_xMII0_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRC_xMII0_DR100 0x00100000 ++/** 1000 MBit/s. */ ++#define SYS_ETH_DRC_xMII0_DR1000 0x00200000 ++/** 200 MBit/s. */ ++#define SYS_ETH_DRC_xMII0_DR200 0x00500000 ++/** SGMII Datarate ++ Selects the datarate of the SGMII interface. */ ++#define SYS_ETH_DRC_SGMII_MASK 0x00070000 ++/** field offset */ ++#define SYS_ETH_DRC_SGMII_OFFSET 16 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRC_SGMII_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRC_SGMII_DR100 0x00010000 ++/** 1000 MBit/s. */ ++#define SYS_ETH_DRC_SGMII_DR1000 0x00020000 ++/** 2500 MBit/s. */ ++#define SYS_ETH_DRC_SGMII_DR2500 0x00040000 ++/** GPHY1_MII2 Datarate ++ Shows the datarate of the GPHY1_MII2 interface. */ ++#define SYS_ETH_DRC_GPHY1_MII2_MASK 0x00007000 ++/** field offset */ ++#define SYS_ETH_DRC_GPHY1_MII2_OFFSET 12 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRC_GPHY1_MII2_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRC_GPHY1_MII2_DR100 0x00001000 ++/** GPHY1_GMII Datarate ++ Shows the datarate of the GPHY1_GMII interface. */ ++#define SYS_ETH_DRC_GPHY1_GMII_MASK 0x00000700 ++/** field offset */ ++#define SYS_ETH_DRC_GPHY1_GMII_OFFSET 8 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRC_GPHY1_GMII_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRC_GPHY1_GMII_DR100 0x00000100 ++/** 1000 MBit/s. */ ++#define SYS_ETH_DRC_GPHY1_GMII_DR1000 0x00000200 ++/** GPHY0_MII2 Datarate ++ Shows the datarate of the GPHY0_MII2 interface. */ ++#define SYS_ETH_DRC_GPHY0_MII2_MASK 0x00000070 ++/** field offset */ ++#define SYS_ETH_DRC_GPHY0_MII2_OFFSET 4 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRC_GPHY0_MII2_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRC_GPHY0_MII2_DR100 0x00000010 ++/** GPHY0_GMII Datarate ++ Shows the datarate of the GPHY0_GMII interface. */ ++#define SYS_ETH_DRC_GPHY0_GMII_MASK 0x00000007 ++/** field offset */ ++#define SYS_ETH_DRC_GPHY0_GMII_OFFSET 0 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRC_GPHY0_GMII_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRC_GPHY0_GMII_DR100 0x00000001 ++/** 1000 MBit/s. */ ++#define SYS_ETH_DRC_GPHY0_GMII_DR1000 0x00000002 ++ ++/* Fields of "GMAC Multiplexer Control Register" */ ++/** GMAC 3 MUX setting ++ Selects the physical layer to be connected to GMAC3 */ ++#define SYS_ETH_GMUXC_GMAC3_MASK 0x00007000 ++/** field offset */ ++#define SYS_ETH_GMUXC_GMAC3_OFFSET 12 ++/** GMAC connects to GPHY0_GMII interface */ ++#define SYS_ETH_GMUXC_GMAC3_GPHY0_GMII 0x00000000 ++/** GMAC connects to GPHY0_MII2 interface */ ++#define SYS_ETH_GMUXC_GMAC3_GPHY0_MII2 0x00001000 ++/** GMAC connects to GPHY1_GMII interface */ ++#define SYS_ETH_GMUXC_GMAC3_GPHY1_GMII 0x00002000 ++/** GMAC connects to GPHY1_MII2 interface */ ++#define SYS_ETH_GMUXC_GMAC3_GPHY1_MII2 0x00003000 ++/** GMAC connects to SGMII interface */ ++#define SYS_ETH_GMUXC_GMAC3_SGMII 0x00004000 ++/** GMAC connects to xMII0 interface */ ++#define SYS_ETH_GMUXC_GMAC3_xMII0 0x00005000 ++/** GMAC connects to xMII1 interface */ ++#define SYS_ETH_GMUXC_GMAC3_xMII1 0x00006000 ++/** GMAC 2 MUX setting ++ Selects the physical layer to be connected to GMAC2 */ ++#define SYS_ETH_GMUXC_GMAC2_MASK 0x00000700 ++/** field offset */ ++#define SYS_ETH_GMUXC_GMAC2_OFFSET 8 ++/** GMAC connects to GPHY0_GMII interface */ ++#define SYS_ETH_GMUXC_GMAC2_GPHY0_GMII 0x00000000 ++/** GMAC connects to GPHY0_MII2 interface */ ++#define SYS_ETH_GMUXC_GMAC2_GPHY0_MII2 0x00000100 ++/** GMAC connects to GPHY1_GMII interface */ ++#define SYS_ETH_GMUXC_GMAC2_GPHY1_GMII 0x00000200 ++/** GMAC connects to GPHY1_MII2 interface */ ++#define SYS_ETH_GMUXC_GMAC2_GPHY1_MII2 0x00000300 ++/** GMAC connects to SGMII interface */ ++#define SYS_ETH_GMUXC_GMAC2_SGMII 0x00000400 ++/** GMAC connects to xMII0 interface */ ++#define SYS_ETH_GMUXC_GMAC2_xMII0 0x00000500 ++/** GMAC connects to xMII1 interface */ ++#define SYS_ETH_GMUXC_GMAC2_xMII1 0x00000600 ++/** GMAC 1 MUX setting ++ Selects the physical layer to be connected to GMAC1 */ ++#define SYS_ETH_GMUXC_GMAC1_MASK 0x00000070 ++/** field offset */ ++#define SYS_ETH_GMUXC_GMAC1_OFFSET 4 ++/** GMAC connects to GPHY0_GMII interface */ ++#define SYS_ETH_GMUXC_GMAC1_GPHY0_GMII 0x00000000 ++/** GMAC connects to GPHY0_MII2 interface */ ++#define SYS_ETH_GMUXC_GMAC1_GPHY0_MII2 0x00000010 ++/** GMAC connects to GPHY1_GMII interface */ ++#define SYS_ETH_GMUXC_GMAC1_GPHY1_GMII 0x00000020 ++/** GMAC connects to GPHY1_MII2 interface */ ++#define SYS_ETH_GMUXC_GMAC1_GPHY1_MII2 0x00000030 ++/** GMAC connects to SGMII interface */ ++#define SYS_ETH_GMUXC_GMAC1_SGMII 0x00000040 ++/** GMAC connects to xMII0 interface */ ++#define SYS_ETH_GMUXC_GMAC1_xMII0 0x00000050 ++/** GMAC connects to xMII1 interface */ ++#define SYS_ETH_GMUXC_GMAC1_xMII1 0x00000060 ++/** GMAC 0 MUX setting ++ Selects the physical layer to be connected to GMAC0 */ ++#define SYS_ETH_GMUXC_GMAC0_MASK 0x00000007 ++/** field offset */ ++#define SYS_ETH_GMUXC_GMAC0_OFFSET 0 ++/** GMAC connects to GPHY0_GMII interface */ ++#define SYS_ETH_GMUXC_GMAC0_GPHY0_GMII 0x00000000 ++/** GMAC connects to GPHY0_MII2 interface */ ++#define SYS_ETH_GMUXC_GMAC0_GPHY0_MII2 0x00000001 ++/** GMAC connects to GPHY1_GMII interface */ ++#define SYS_ETH_GMUXC_GMAC0_GPHY1_GMII 0x00000002 ++/** GMAC connects to GPHY1_MII2 interface */ ++#define SYS_ETH_GMUXC_GMAC0_GPHY1_MII2 0x00000003 ++/** GMAC connects to SGMII interface */ ++#define SYS_ETH_GMUXC_GMAC0_SGMII 0x00000004 ++/** GMAC connects to xMII0 interface */ ++#define SYS_ETH_GMUXC_GMAC0_xMII0 0x00000005 ++/** GMAC connects to xMII1 interface */ ++#define SYS_ETH_GMUXC_GMAC0_xMII1 0x00000006 ++ ++/* Fields of "Datarate Status Register" */ ++/** GMAC 3 datarate ++ Shows the datarate of GMAC3 */ ++#define SYS_ETH_DRS_GMAC3_MASK 0x00007000 ++/** field offset */ ++#define SYS_ETH_DRS_GMAC3_OFFSET 12 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRS_GMAC3_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRS_GMAC3_DR100 0x00001000 ++/** 1000 MBit/s. */ ++#define SYS_ETH_DRS_GMAC3_DR1000 0x00002000 ++/** 2500 MBit/s. */ ++#define SYS_ETH_DRS_GMAC3_DR2500 0x00004000 ++/** 200 MBit/s. */ ++#define SYS_ETH_DRS_GMAC3_DR200 0x00005000 ++/** GMAC 2 datarate ++ Shows the datarate of GMAC2 */ ++#define SYS_ETH_DRS_GMAC2_MASK 0x00000700 ++/** field offset */ ++#define SYS_ETH_DRS_GMAC2_OFFSET 8 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRS_GMAC2_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRS_GMAC2_DR100 0x00000100 ++/** 1000 MBit/s. */ ++#define SYS_ETH_DRS_GMAC2_DR1000 0x00000200 ++/** 2500 MBit/s. */ ++#define SYS_ETH_DRS_GMAC2_DR2500 0x00000400 ++/** 200 MBit/s. */ ++#define SYS_ETH_DRS_GMAC2_DR200 0x00000500 ++/** GMAC 1 datarate ++ Shows the datarate of GMAC1 */ ++#define SYS_ETH_DRS_GMAC1_MASK 0x00000070 ++/** field offset */ ++#define SYS_ETH_DRS_GMAC1_OFFSET 4 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRS_GMAC1_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRS_GMAC1_DR100 0x00000010 ++/** 1000 MBit/s. */ ++#define SYS_ETH_DRS_GMAC1_DR1000 0x00000020 ++/** 2500 MBit/s. */ ++#define SYS_ETH_DRS_GMAC1_DR2500 0x00000040 ++/** 200 MBit/s. */ ++#define SYS_ETH_DRS_GMAC1_DR200 0x00000050 ++/** GMAC 0 datarate ++ Shows the datarate of GMAC0 */ ++#define SYS_ETH_DRS_GMAC0_MASK 0x00000007 ++/** field offset */ ++#define SYS_ETH_DRS_GMAC0_OFFSET 0 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRS_GMAC0_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRS_GMAC0_DR100 0x00000001 ++/** 1000 MBit/s. */ ++#define SYS_ETH_DRS_GMAC0_DR1000 0x00000002 ++/** 2500 MBit/s. */ ++#define SYS_ETH_DRS_GMAC0_DR2500 0x00000004 ++/** 200 MBit/s. */ ++#define SYS_ETH_DRS_GMAC0_DR200 0x00000005 ++ ++/* Fields of "SGMII Control Register" */ ++/** Auto Negotiation Protocol ++ Selects the TBX/SGMII mode for the autonegotiation of the SGMII interface. */ ++#define SYS_ETH_SGMIIC_ANP 0x00000002 ++/* TBX Mode (IEEE 802.3 Clause 37 ANEG) ++#define SYS_ETH_SGMIIC_ANP_TBXM 0x00000000 */ ++/** SGMII Mode (Cisco Aneg) */ ++#define SYS_ETH_SGMIIC_ANP_SGMIIM 0x00000002 ++/** Auto Negotiation MAC/PHY ++ Selects the MAC/PHY mode for the autonegotiation of the SGMII interface. */ ++#define SYS_ETH_SGMIIC_ANMP 0x00000001 ++/* MAC Mode ++#define SYS_ETH_SGMIIC_ANMP_MAC 0x00000000 */ ++/** PHY Mode */ ++#define SYS_ETH_SGMIIC_ANMP_PHY 0x00000001 ++ ++/*! @} */ /* SYS_ETH_REGISTER */ ++ ++#endif /* _sys_eth_reg_h */ +diff --git a/arch/mips/include/asm/mach-lantiq/falcon/sys_gpe_reg.h b/arch/mips/include/asm/mach-lantiq/falcon/sys_gpe_reg.h +new file mode 100644 +index 0000000..a9a1b1b +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/sys_gpe_reg.h +@@ -0,0 +1,2829 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++ ++#ifndef _sys_gpe_reg_h ++#define _sys_gpe_reg_h ++ ++/** \addtogroup SYS_GPE_REGISTER ++ @{ ++*/ ++/* access macros */ ++#define sys_gpe_r32(reg) reg_r32(&sys_gpe->reg) ++#define sys_gpe_w32(val, reg) reg_w32(val, &sys_gpe->reg) ++#define sys_gpe_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys_gpe->reg) ++#define sys_gpe_r32_table(reg, idx) reg_r32_table(sys_gpe->reg, idx) ++#define sys_gpe_w32_table(val, reg, idx) reg_w32_table(val, sys_gpe->reg, idx) ++#define sys_gpe_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys_gpe->reg, idx) ++#define sys_gpe_adr_table(reg, idx) adr_table(sys_gpe->reg, idx) ++ ++ ++/** SYS_GPE register structure */ ++struct gpon_reg_sys_gpe ++{ ++ /** Clock Status Register ++ The clock status reflects the actual clocking mode as a function of the SW settings and the hardware sleep mode. */ ++ unsigned int clks; /* 0x00000000 */ ++ /** Clock Enable Register ++ Via this register the clocks for the domains can be enabled. */ ++ unsigned int clken; /* 0x00000004 */ ++ /** Clock Clear Register ++ Via this register the clocks for the domains can be disabled. */ ++ unsigned int clkclr; /* 0x00000008 */ ++ /** Reserved */ ++ unsigned int res_0[5]; /* 0x0000000C */ ++ /** Activation Status Register */ ++ unsigned int acts; /* 0x00000020 */ ++ /** Activation Register ++ Via this register the domains can be activated. */ ++ unsigned int act; /* 0x00000024 */ ++ /** Deactivation Register ++ Via this register the domains can be deactivated. */ ++ unsigned int deact; /* 0x00000028 */ ++ /** Reboot Trigger Register ++ Via this register the domains can be rebooted (sent through reset). */ ++ unsigned int rbt; /* 0x0000002C */ ++ /** Reserved */ ++ unsigned int res_1[33]; /* 0x00000030 */ ++ /** Power Down Configuration Register ++ Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be removed. */ ++ unsigned int pdcfg; /* 0x000000B4 */ ++ /** Sleep Source Configuration Register ++ All sleep/wakeup conditions selected in this register contribute to the generation of the hardware sleep/wakeup request. Unselected conditions are ignored for sleep and wakeup. If no bit is selected, HW sleep is disabled. */ ++ unsigned int sscfg; /* 0x000000B8 */ ++ /** Sleep Source Timer Register */ ++ unsigned int sst; /* 0x000000BC */ ++ /** Sleep Destination Status Register ++ Shows the status of the sleep destination vector. All clock domains selected in this register will be shutoff in case of a hardware sleep request. These clocks will be automatically reenabled in case of a hardware wakeup request. */ ++ unsigned int sds; /* 0x000000C0 */ ++ /** Sleep Destination Set Register ++ Via this register the the domains to be shutoff in case of a hardware sleep request can be selected. */ ++ unsigned int sdset; /* 0x000000C4 */ ++ /** Sleep Destination Clear Register ++ Via this register the the domains to be shutoff in case of a hardware sleep request can be deselected. */ ++ unsigned int sdclr; /* 0x000000C8 */ ++ /** Reserved */ ++ unsigned int res_2[9]; /* 0x000000CC */ ++ /** IRNCS Capture Register ++ This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNCSEN register. The interrupts can be acknowledged by a write operation. */ ++ unsigned int irncscr; /* 0x000000F0 */ ++ /** IRNCS Interrupt Control Register ++ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ ++ unsigned int irncsicr; /* 0x000000F4 */ ++ /** IRNCS Interrupt Enable Register ++ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCSCR register and are not signalled via the interrupt line towards the controller. */ ++ unsigned int irncsen; /* 0x000000F8 */ ++ /** Reserved */ ++ unsigned int res_3; /* 0x000000FC */ ++}; ++ ++ ++/* Fields of "Clock Status Register" */ ++/** COP7 Clock Enable ++ Shows the clock enable bit for the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ ++#define SYS_GPE_CLKS_COP7 0x80000000 ++/* Disable ++#define SYS_GPE_CLKS_COP7_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_COP7_EN 0x80000000 ++/** COP6 Clock Enable ++ Shows the clock enable bit for the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ ++#define SYS_GPE_CLKS_COP6 0x40000000 ++/* Disable ++#define SYS_GPE_CLKS_COP6_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_COP6_EN 0x40000000 ++/** COP5 Clock Enable ++ Shows the clock enable bit for the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ ++#define SYS_GPE_CLKS_COP5 0x20000000 ++/* Disable ++#define SYS_GPE_CLKS_COP5_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_COP5_EN 0x20000000 ++/** COP4 Clock Enable ++ Shows the clock enable bit for the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ ++#define SYS_GPE_CLKS_COP4 0x10000000 ++/* Disable ++#define SYS_GPE_CLKS_COP4_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_COP4_EN 0x10000000 ++/** COP3 Clock Enable ++ Shows the clock enable bit for the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ ++#define SYS_GPE_CLKS_COP3 0x08000000 ++/* Disable ++#define SYS_GPE_CLKS_COP3_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_COP3_EN 0x08000000 ++/** COP2 Clock Enable ++ Shows the clock enable bit for the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ ++#define SYS_GPE_CLKS_COP2 0x04000000 ++/* Disable ++#define SYS_GPE_CLKS_COP2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_COP2_EN 0x04000000 ++/** COP1 Clock Enable ++ Shows the clock enable bit for the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ ++#define SYS_GPE_CLKS_COP1 0x02000000 ++/* Disable ++#define SYS_GPE_CLKS_COP1_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_COP1_EN 0x02000000 ++/** COP0 Clock Enable ++ Shows the clock enable bit for the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ ++#define SYS_GPE_CLKS_COP0 0x01000000 ++/* Disable ++#define SYS_GPE_CLKS_COP0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_COP0_EN 0x01000000 ++/** PE5 Clock Enable ++ Shows the clock enable bit for the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ ++#define SYS_GPE_CLKS_PE5 0x00200000 ++/* Disable ++#define SYS_GPE_CLKS_PE5_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_PE5_EN 0x00200000 ++/** PE4 Clock Enable ++ Shows the clock enable bit for the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ ++#define SYS_GPE_CLKS_PE4 0x00100000 ++/* Disable ++#define SYS_GPE_CLKS_PE4_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_PE4_EN 0x00100000 ++/** PE3 Clock Enable ++ Shows the clock enable bit for the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ ++#define SYS_GPE_CLKS_PE3 0x00080000 ++/* Disable ++#define SYS_GPE_CLKS_PE3_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_PE3_EN 0x00080000 ++/** PE2 Clock Enable ++ Shows the clock enable bit for the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ ++#define SYS_GPE_CLKS_PE2 0x00040000 ++/* Disable ++#define SYS_GPE_CLKS_PE2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_PE2_EN 0x00040000 ++/** PE1 Clock Enable ++ Shows the clock enable bit for the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ ++#define SYS_GPE_CLKS_PE1 0x00020000 ++/* Disable ++#define SYS_GPE_CLKS_PE1_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_PE1_EN 0x00020000 ++/** PE0 Clock Enable ++ Shows the clock enable bit for the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ ++#define SYS_GPE_CLKS_PE0 0x00010000 ++/* Disable ++#define SYS_GPE_CLKS_PE0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_PE0_EN 0x00010000 ++/** ARB Clock Enable ++ Shows the clock enable bit for the ARB domain. This domain contains the Arbiter. */ ++#define SYS_GPE_CLKS_ARB 0x00002000 ++/* Disable ++#define SYS_GPE_CLKS_ARB_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_ARB_EN 0x00002000 ++/** FSQM Clock Enable ++ Shows the clock enable bit for the FSQM domain. This domain contains the FSQM. */ ++#define SYS_GPE_CLKS_FSQM 0x00001000 ++/* Disable ++#define SYS_GPE_CLKS_FSQM_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_FSQM_EN 0x00001000 ++/** TMU Clock Enable ++ Shows the clock enable bit for the TMU domain. This domain contains the TMU. */ ++#define SYS_GPE_CLKS_TMU 0x00000800 ++/* Disable ++#define SYS_GPE_CLKS_TMU_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_TMU_EN 0x00000800 ++/** MRG Clock Enable ++ Shows the clock enable bit for the MRG domain. This domain contains the Merger. */ ++#define SYS_GPE_CLKS_MRG 0x00000400 ++/* Disable ++#define SYS_GPE_CLKS_MRG_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_MRG_EN 0x00000400 ++/** DISP Clock Enable ++ Shows the clock enable bit for the DISP domain. This domain contains the Dispatcher. */ ++#define SYS_GPE_CLKS_DISP 0x00000200 ++/* Disable ++#define SYS_GPE_CLKS_DISP_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_DISP_EN 0x00000200 ++/** IQM Clock Enable ++ Shows the clock enable bit for the IQM domain. This domain contains the IQM. */ ++#define SYS_GPE_CLKS_IQM 0x00000100 ++/* Disable ++#define SYS_GPE_CLKS_IQM_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_IQM_EN 0x00000100 ++/** CPUE Clock Enable ++ Shows the clock enable bit for the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ ++#define SYS_GPE_CLKS_CPUE 0x00000080 ++/* Disable ++#define SYS_GPE_CLKS_CPUE_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_CPUE_EN 0x00000080 ++/** CPUI Clock Enable ++ Shows the clock enable bit for the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ ++#define SYS_GPE_CLKS_CPUI 0x00000040 ++/* Disable ++#define SYS_GPE_CLKS_CPUI_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_CPUI_EN 0x00000040 ++/** GPONE Clock Enable ++ Shows the clock enable bit for the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ ++#define SYS_GPE_CLKS_GPONE 0x00000020 ++/* Disable ++#define SYS_GPE_CLKS_GPONE_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_GPONE_EN 0x00000020 ++/** GPONI Clock Enable ++ Shows the clock enable bit for the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ ++#define SYS_GPE_CLKS_GPONI 0x00000010 ++/* Disable ++#define SYS_GPE_CLKS_GPONI_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_GPONI_EN 0x00000010 ++/** LAN3 Clock Enable ++ Shows the clock enable bit for the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ ++#define SYS_GPE_CLKS_LAN3 0x00000008 ++/* Disable ++#define SYS_GPE_CLKS_LAN3_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_LAN3_EN 0x00000008 ++/** LAN2 Clock Enable ++ Shows the clock enable bit for the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ ++#define SYS_GPE_CLKS_LAN2 0x00000004 ++/* Disable ++#define SYS_GPE_CLKS_LAN2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_LAN2_EN 0x00000004 ++/** LAN1 Clock Enable ++ Shows the clock enable bit for the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ ++#define SYS_GPE_CLKS_LAN1 0x00000002 ++/* Disable ++#define SYS_GPE_CLKS_LAN1_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_LAN1_EN 0x00000002 ++/** LAN0 Clock Enable ++ Shows the clock enable bit for the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ ++#define SYS_GPE_CLKS_LAN0 0x00000001 ++/* Disable ++#define SYS_GPE_CLKS_LAN0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_LAN0_EN 0x00000001 ++ ++/* Fields of "Clock Enable Register" */ ++/** Set Clock Enable COP7 ++ Sets the clock enable bit of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ ++#define SYS_GPE_CLKEN_COP7 0x80000000 ++/* No-Operation ++#define SYS_GPE_CLKEN_COP7_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_COP7_SET 0x80000000 ++/** Set Clock Enable COP6 ++ Sets the clock enable bit of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ ++#define SYS_GPE_CLKEN_COP6 0x40000000 ++/* No-Operation ++#define SYS_GPE_CLKEN_COP6_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_COP6_SET 0x40000000 ++/** Set Clock Enable COP5 ++ Sets the clock enable bit of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ ++#define SYS_GPE_CLKEN_COP5 0x20000000 ++/* No-Operation ++#define SYS_GPE_CLKEN_COP5_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_COP5_SET 0x20000000 ++/** Set Clock Enable COP4 ++ Sets the clock enable bit of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ ++#define SYS_GPE_CLKEN_COP4 0x10000000 ++/* No-Operation ++#define SYS_GPE_CLKEN_COP4_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_COP4_SET 0x10000000 ++/** Set Clock Enable COP3 ++ Sets the clock enable bit of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ ++#define SYS_GPE_CLKEN_COP3 0x08000000 ++/* No-Operation ++#define SYS_GPE_CLKEN_COP3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_COP3_SET 0x08000000 ++/** Set Clock Enable COP2 ++ Sets the clock enable bit of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ ++#define SYS_GPE_CLKEN_COP2 0x04000000 ++/* No-Operation ++#define SYS_GPE_CLKEN_COP2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_COP2_SET 0x04000000 ++/** Set Clock Enable COP1 ++ Sets the clock enable bit of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ ++#define SYS_GPE_CLKEN_COP1 0x02000000 ++/* No-Operation ++#define SYS_GPE_CLKEN_COP1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_COP1_SET 0x02000000 ++/** Set Clock Enable COP0 ++ Sets the clock enable bit of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ ++#define SYS_GPE_CLKEN_COP0 0x01000000 ++/* No-Operation ++#define SYS_GPE_CLKEN_COP0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_COP0_SET 0x01000000 ++/** Set Clock Enable PE5 ++ Sets the clock enable bit of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ ++#define SYS_GPE_CLKEN_PE5 0x00200000 ++/* No-Operation ++#define SYS_GPE_CLKEN_PE5_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_PE5_SET 0x00200000 ++/** Set Clock Enable PE4 ++ Sets the clock enable bit of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ ++#define SYS_GPE_CLKEN_PE4 0x00100000 ++/* No-Operation ++#define SYS_GPE_CLKEN_PE4_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_PE4_SET 0x00100000 ++/** Set Clock Enable PE3 ++ Sets the clock enable bit of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ ++#define SYS_GPE_CLKEN_PE3 0x00080000 ++/* No-Operation ++#define SYS_GPE_CLKEN_PE3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_PE3_SET 0x00080000 ++/** Set Clock Enable PE2 ++ Sets the clock enable bit of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ ++#define SYS_GPE_CLKEN_PE2 0x00040000 ++/* No-Operation ++#define SYS_GPE_CLKEN_PE2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_PE2_SET 0x00040000 ++/** Set Clock Enable PE1 ++ Sets the clock enable bit of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ ++#define SYS_GPE_CLKEN_PE1 0x00020000 ++/* No-Operation ++#define SYS_GPE_CLKEN_PE1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_PE1_SET 0x00020000 ++/** Set Clock Enable PE0 ++ Sets the clock enable bit of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ ++#define SYS_GPE_CLKEN_PE0 0x00010000 ++/* No-Operation ++#define SYS_GPE_CLKEN_PE0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_PE0_SET 0x00010000 ++/** Set Clock Enable ARB ++ Sets the clock enable bit of the ARB domain. This domain contains the Arbiter. */ ++#define SYS_GPE_CLKEN_ARB 0x00002000 ++/* No-Operation ++#define SYS_GPE_CLKEN_ARB_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_ARB_SET 0x00002000 ++/** Set Clock Enable FSQM ++ Sets the clock enable bit of the FSQM domain. This domain contains the FSQM. */ ++#define SYS_GPE_CLKEN_FSQM 0x00001000 ++/* No-Operation ++#define SYS_GPE_CLKEN_FSQM_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_FSQM_SET 0x00001000 ++/** Set Clock Enable TMU ++ Sets the clock enable bit of the TMU domain. This domain contains the TMU. */ ++#define SYS_GPE_CLKEN_TMU 0x00000800 ++/* No-Operation ++#define SYS_GPE_CLKEN_TMU_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_TMU_SET 0x00000800 ++/** Set Clock Enable MRG ++ Sets the clock enable bit of the MRG domain. This domain contains the Merger. */ ++#define SYS_GPE_CLKEN_MRG 0x00000400 ++/* No-Operation ++#define SYS_GPE_CLKEN_MRG_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_MRG_SET 0x00000400 ++/** Set Clock Enable DISP ++ Sets the clock enable bit of the DISP domain. This domain contains the Dispatcher. */ ++#define SYS_GPE_CLKEN_DISP 0x00000200 ++/* No-Operation ++#define SYS_GPE_CLKEN_DISP_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_DISP_SET 0x00000200 ++/** Set Clock Enable IQM ++ Sets the clock enable bit of the IQM domain. This domain contains the IQM. */ ++#define SYS_GPE_CLKEN_IQM 0x00000100 ++/* No-Operation ++#define SYS_GPE_CLKEN_IQM_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_IQM_SET 0x00000100 ++/** Set Clock Enable CPUE ++ Sets the clock enable bit of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ ++#define SYS_GPE_CLKEN_CPUE 0x00000080 ++/* No-Operation ++#define SYS_GPE_CLKEN_CPUE_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_CPUE_SET 0x00000080 ++/** Set Clock Enable CPUI ++ Sets the clock enable bit of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ ++#define SYS_GPE_CLKEN_CPUI 0x00000040 ++/* No-Operation ++#define SYS_GPE_CLKEN_CPUI_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_CPUI_SET 0x00000040 ++/** Set Clock Enable GPONE ++ Sets the clock enable bit of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ ++#define SYS_GPE_CLKEN_GPONE 0x00000020 ++/* No-Operation ++#define SYS_GPE_CLKEN_GPONE_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_GPONE_SET 0x00000020 ++/** Set Clock Enable GPONI ++ Sets the clock enable bit of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ ++#define SYS_GPE_CLKEN_GPONI 0x00000010 ++/* No-Operation ++#define SYS_GPE_CLKEN_GPONI_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_GPONI_SET 0x00000010 ++/** Set Clock Enable LAN3 ++ Sets the clock enable bit of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ ++#define SYS_GPE_CLKEN_LAN3 0x00000008 ++/* No-Operation ++#define SYS_GPE_CLKEN_LAN3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_LAN3_SET 0x00000008 ++/** Set Clock Enable LAN2 ++ Sets the clock enable bit of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ ++#define SYS_GPE_CLKEN_LAN2 0x00000004 ++/* No-Operation ++#define SYS_GPE_CLKEN_LAN2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_LAN2_SET 0x00000004 ++/** Set Clock Enable LAN1 ++ Sets the clock enable bit of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ ++#define SYS_GPE_CLKEN_LAN1 0x00000002 ++/* No-Operation ++#define SYS_GPE_CLKEN_LAN1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_LAN1_SET 0x00000002 ++/** Set Clock Enable LAN0 ++ Sets the clock enable bit of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ ++#define SYS_GPE_CLKEN_LAN0 0x00000001 ++/* No-Operation ++#define SYS_GPE_CLKEN_LAN0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_LAN0_SET 0x00000001 ++ ++/* Fields of "Clock Clear Register" */ ++/** Clear Clock Enable COP7 ++ Clears the clock enable bit of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ ++#define SYS_GPE_CLKCLR_COP7 0x80000000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_COP7_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_COP7_CLR 0x80000000 ++/** Clear Clock Enable COP6 ++ Clears the clock enable bit of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ ++#define SYS_GPE_CLKCLR_COP6 0x40000000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_COP6_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_COP6_CLR 0x40000000 ++/** Clear Clock Enable COP5 ++ Clears the clock enable bit of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ ++#define SYS_GPE_CLKCLR_COP5 0x20000000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_COP5_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_COP5_CLR 0x20000000 ++/** Clear Clock Enable COP4 ++ Clears the clock enable bit of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ ++#define SYS_GPE_CLKCLR_COP4 0x10000000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_COP4_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_COP4_CLR 0x10000000 ++/** Clear Clock Enable COP3 ++ Clears the clock enable bit of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ ++#define SYS_GPE_CLKCLR_COP3 0x08000000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_COP3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_COP3_CLR 0x08000000 ++/** Clear Clock Enable COP2 ++ Clears the clock enable bit of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ ++#define SYS_GPE_CLKCLR_COP2 0x04000000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_COP2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_COP2_CLR 0x04000000 ++/** Clear Clock Enable COP1 ++ Clears the clock enable bit of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ ++#define SYS_GPE_CLKCLR_COP1 0x02000000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_COP1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_COP1_CLR 0x02000000 ++/** Clear Clock Enable COP0 ++ Clears the clock enable bit of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ ++#define SYS_GPE_CLKCLR_COP0 0x01000000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_COP0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_COP0_CLR 0x01000000 ++/** Clear Clock Enable PE5 ++ Clears the clock enable bit of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ ++#define SYS_GPE_CLKCLR_PE5 0x00200000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_PE5_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_PE5_CLR 0x00200000 ++/** Clear Clock Enable PE4 ++ Clears the clock enable bit of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ ++#define SYS_GPE_CLKCLR_PE4 0x00100000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_PE4_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_PE4_CLR 0x00100000 ++/** Clear Clock Enable PE3 ++ Clears the clock enable bit of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ ++#define SYS_GPE_CLKCLR_PE3 0x00080000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_PE3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_PE3_CLR 0x00080000 ++/** Clear Clock Enable PE2 ++ Clears the clock enable bit of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ ++#define SYS_GPE_CLKCLR_PE2 0x00040000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_PE2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_PE2_CLR 0x00040000 ++/** Clear Clock Enable PE1 ++ Clears the clock enable bit of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ ++#define SYS_GPE_CLKCLR_PE1 0x00020000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_PE1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_PE1_CLR 0x00020000 ++/** Clear Clock Enable PE0 ++ Clears the clock enable bit of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ ++#define SYS_GPE_CLKCLR_PE0 0x00010000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_PE0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_PE0_CLR 0x00010000 ++/** Clear Clock Enable ARB ++ Clears the clock enable bit of the ARB domain. This domain contains the Arbiter. */ ++#define SYS_GPE_CLKCLR_ARB 0x00002000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_ARB_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_ARB_CLR 0x00002000 ++/** Clear Clock Enable FSQM ++ Clears the clock enable bit of the FSQM domain. This domain contains the FSQM. */ ++#define SYS_GPE_CLKCLR_FSQM 0x00001000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_FSQM_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_FSQM_CLR 0x00001000 ++/** Clear Clock Enable TMU ++ Clears the clock enable bit of the TMU domain. This domain contains the TMU. */ ++#define SYS_GPE_CLKCLR_TMU 0x00000800 ++/* No-Operation ++#define SYS_GPE_CLKCLR_TMU_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_TMU_CLR 0x00000800 ++/** Clear Clock Enable MRG ++ Clears the clock enable bit of the MRG domain. This domain contains the Merger. */ ++#define SYS_GPE_CLKCLR_MRG 0x00000400 ++/* No-Operation ++#define SYS_GPE_CLKCLR_MRG_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_MRG_CLR 0x00000400 ++/** Clear Clock Enable DISP ++ Clears the clock enable bit of the DISP domain. This domain contains the Dispatcher. */ ++#define SYS_GPE_CLKCLR_DISP 0x00000200 ++/* No-Operation ++#define SYS_GPE_CLKCLR_DISP_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_DISP_CLR 0x00000200 ++/** Clear Clock Enable IQM ++ Clears the clock enable bit of the IQM domain. This domain contains the IQM. */ ++#define SYS_GPE_CLKCLR_IQM 0x00000100 ++/* No-Operation ++#define SYS_GPE_CLKCLR_IQM_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_IQM_CLR 0x00000100 ++/** Clear Clock Enable CPUE ++ Clears the clock enable bit of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ ++#define SYS_GPE_CLKCLR_CPUE 0x00000080 ++/* No-Operation ++#define SYS_GPE_CLKCLR_CPUE_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_CPUE_CLR 0x00000080 ++/** Clear Clock Enable CPUI ++ Clears the clock enable bit of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ ++#define SYS_GPE_CLKCLR_CPUI 0x00000040 ++/* No-Operation ++#define SYS_GPE_CLKCLR_CPUI_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_CPUI_CLR 0x00000040 ++/** Clear Clock Enable GPONE ++ Clears the clock enable bit of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ ++#define SYS_GPE_CLKCLR_GPONE 0x00000020 ++/* No-Operation ++#define SYS_GPE_CLKCLR_GPONE_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_GPONE_CLR 0x00000020 ++/** Clear Clock Enable GPONI ++ Clears the clock enable bit of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ ++#define SYS_GPE_CLKCLR_GPONI 0x00000010 ++/* No-Operation ++#define SYS_GPE_CLKCLR_GPONI_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_GPONI_CLR 0x00000010 ++/** Clear Clock Enable LAN3 ++ Clears the clock enable bit of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ ++#define SYS_GPE_CLKCLR_LAN3 0x00000008 ++/* No-Operation ++#define SYS_GPE_CLKCLR_LAN3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_LAN3_CLR 0x00000008 ++/** Clear Clock Enable LAN2 ++ Clears the clock enable bit of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ ++#define SYS_GPE_CLKCLR_LAN2 0x00000004 ++/* No-Operation ++#define SYS_GPE_CLKCLR_LAN2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_LAN2_CLR 0x00000004 ++/** Clear Clock Enable LAN1 ++ Clears the clock enable bit of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ ++#define SYS_GPE_CLKCLR_LAN1 0x00000002 ++/* No-Operation ++#define SYS_GPE_CLKCLR_LAN1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_LAN1_CLR 0x00000002 ++/** Clear Clock Enable LAN0 ++ Clears the clock enable bit of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ ++#define SYS_GPE_CLKCLR_LAN0 0x00000001 ++/* No-Operation ++#define SYS_GPE_CLKCLR_LAN0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_LAN0_CLR 0x00000001 ++ ++/* Fields of "Activation Status Register" */ ++/** COP7 Status ++ Shows the activation status of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ ++#define SYS_GPE_ACTS_COP7 0x80000000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_COP7_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_COP7_ACT 0x80000000 ++/** COP6 Status ++ Shows the activation status of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ ++#define SYS_GPE_ACTS_COP6 0x40000000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_COP6_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_COP6_ACT 0x40000000 ++/** COP5 Status ++ Shows the activation status of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ ++#define SYS_GPE_ACTS_COP5 0x20000000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_COP5_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_COP5_ACT 0x20000000 ++/** COP4 Status ++ Shows the activation status of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ ++#define SYS_GPE_ACTS_COP4 0x10000000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_COP4_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_COP4_ACT 0x10000000 ++/** COP3 Status ++ Shows the activation status of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ ++#define SYS_GPE_ACTS_COP3 0x08000000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_COP3_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_COP3_ACT 0x08000000 ++/** COP2 Status ++ Shows the activation status of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ ++#define SYS_GPE_ACTS_COP2 0x04000000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_COP2_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_COP2_ACT 0x04000000 ++/** COP1 Status ++ Shows the activation status of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ ++#define SYS_GPE_ACTS_COP1 0x02000000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_COP1_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_COP1_ACT 0x02000000 ++/** COP0 Status ++ Shows the activation status of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ ++#define SYS_GPE_ACTS_COP0 0x01000000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_COP0_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_COP0_ACT 0x01000000 ++/** PE5 Status ++ Shows the activation status of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ ++#define SYS_GPE_ACTS_PE5 0x00200000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_PE5_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_PE5_ACT 0x00200000 ++/** PE4 Status ++ Shows the activation status of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ ++#define SYS_GPE_ACTS_PE4 0x00100000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_PE4_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_PE4_ACT 0x00100000 ++/** PE3 Status ++ Shows the activation status of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ ++#define SYS_GPE_ACTS_PE3 0x00080000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_PE3_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_PE3_ACT 0x00080000 ++/** PE2 Status ++ Shows the activation status of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ ++#define SYS_GPE_ACTS_PE2 0x00040000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_PE2_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_PE2_ACT 0x00040000 ++/** PE1 Status ++ Shows the activation status of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ ++#define SYS_GPE_ACTS_PE1 0x00020000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_PE1_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_PE1_ACT 0x00020000 ++/** PE0 Status ++ Shows the activation status of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ ++#define SYS_GPE_ACTS_PE0 0x00010000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_PE0_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_PE0_ACT 0x00010000 ++/** ARB Status ++ Shows the activation status of the ARB domain. This domain contains the Arbiter. */ ++#define SYS_GPE_ACTS_ARB 0x00002000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_ARB_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_ARB_ACT 0x00002000 ++/** FSQM Status ++ Shows the activation status of the FSQM domain. This domain contains the FSQM. */ ++#define SYS_GPE_ACTS_FSQM 0x00001000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_FSQM_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_FSQM_ACT 0x00001000 ++/** TMU Status ++ Shows the activation status of the TMU domain. This domain contains the TMU. */ ++#define SYS_GPE_ACTS_TMU 0x00000800 ++/* The block is inactive. ++#define SYS_GPE_ACTS_TMU_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_TMU_ACT 0x00000800 ++/** MRG Status ++ Shows the activation status of the MRG domain. This domain contains the Merger. */ ++#define SYS_GPE_ACTS_MRG 0x00000400 ++/* The block is inactive. ++#define SYS_GPE_ACTS_MRG_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_MRG_ACT 0x00000400 ++/** DISP Status ++ Shows the activation status of the DISP domain. This domain contains the Dispatcher. */ ++#define SYS_GPE_ACTS_DISP 0x00000200 ++/* The block is inactive. ++#define SYS_GPE_ACTS_DISP_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_DISP_ACT 0x00000200 ++/** IQM Status ++ Shows the activation status of the IQM domain. This domain contains the IQM. */ ++#define SYS_GPE_ACTS_IQM 0x00000100 ++/* The block is inactive. ++#define SYS_GPE_ACTS_IQM_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_IQM_ACT 0x00000100 ++/** CPUE Status ++ Shows the activation status of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ ++#define SYS_GPE_ACTS_CPUE 0x00000080 ++/* The block is inactive. ++#define SYS_GPE_ACTS_CPUE_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_CPUE_ACT 0x00000080 ++/** CPUI Status ++ Shows the activation status of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ ++#define SYS_GPE_ACTS_CPUI 0x00000040 ++/* The block is inactive. ++#define SYS_GPE_ACTS_CPUI_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_CPUI_ACT 0x00000040 ++/** GPONE Status ++ Shows the activation status of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ ++#define SYS_GPE_ACTS_GPONE 0x00000020 ++/* The block is inactive. ++#define SYS_GPE_ACTS_GPONE_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_GPONE_ACT 0x00000020 ++/** GPONI Status ++ Shows the activation status of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ ++#define SYS_GPE_ACTS_GPONI 0x00000010 ++/* The block is inactive. ++#define SYS_GPE_ACTS_GPONI_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_GPONI_ACT 0x00000010 ++/** LAN3 Status ++ Shows the activation status of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ ++#define SYS_GPE_ACTS_LAN3 0x00000008 ++/* The block is inactive. ++#define SYS_GPE_ACTS_LAN3_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_LAN3_ACT 0x00000008 ++/** LAN2 Status ++ Shows the activation status of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ ++#define SYS_GPE_ACTS_LAN2 0x00000004 ++/* The block is inactive. ++#define SYS_GPE_ACTS_LAN2_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_LAN2_ACT 0x00000004 ++/** LAN1 Status ++ Shows the activation status of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ ++#define SYS_GPE_ACTS_LAN1 0x00000002 ++/* The block is inactive. ++#define SYS_GPE_ACTS_LAN1_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_LAN1_ACT 0x00000002 ++/** LAN0 Status ++ Shows the activation status of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ ++#define SYS_GPE_ACTS_LAN0 0x00000001 ++/* The block is inactive. ++#define SYS_GPE_ACTS_LAN0_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_LAN0_ACT 0x00000001 ++ ++/* Fields of "Activation Register" */ ++/** Activate COP7 ++ Sets the activation flag of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ ++#define SYS_GPE_ACT_COP7 0x80000000 ++/* No-Operation ++#define SYS_GPE_ACT_COP7_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_COP7_SET 0x80000000 ++/** Activate COP6 ++ Sets the activation flag of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ ++#define SYS_GPE_ACT_COP6 0x40000000 ++/* No-Operation ++#define SYS_GPE_ACT_COP6_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_COP6_SET 0x40000000 ++/** Activate COP5 ++ Sets the activation flag of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ ++#define SYS_GPE_ACT_COP5 0x20000000 ++/* No-Operation ++#define SYS_GPE_ACT_COP5_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_COP5_SET 0x20000000 ++/** Activate COP4 ++ Sets the activation flag of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ ++#define SYS_GPE_ACT_COP4 0x10000000 ++/* No-Operation ++#define SYS_GPE_ACT_COP4_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_COP4_SET 0x10000000 ++/** Activate COP3 ++ Sets the activation flag of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ ++#define SYS_GPE_ACT_COP3 0x08000000 ++/* No-Operation ++#define SYS_GPE_ACT_COP3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_COP3_SET 0x08000000 ++/** Activate COP2 ++ Sets the activation flag of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ ++#define SYS_GPE_ACT_COP2 0x04000000 ++/* No-Operation ++#define SYS_GPE_ACT_COP2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_COP2_SET 0x04000000 ++/** Activate COP1 ++ Sets the activation flag of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ ++#define SYS_GPE_ACT_COP1 0x02000000 ++/* No-Operation ++#define SYS_GPE_ACT_COP1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_COP1_SET 0x02000000 ++/** Activate COP0 ++ Sets the activation flag of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ ++#define SYS_GPE_ACT_COP0 0x01000000 ++/* No-Operation ++#define SYS_GPE_ACT_COP0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_COP0_SET 0x01000000 ++/** Activate PE5 ++ Sets the activation flag of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ ++#define SYS_GPE_ACT_PE5 0x00200000 ++/* No-Operation ++#define SYS_GPE_ACT_PE5_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_PE5_SET 0x00200000 ++/** Activate PE4 ++ Sets the activation flag of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ ++#define SYS_GPE_ACT_PE4 0x00100000 ++/* No-Operation ++#define SYS_GPE_ACT_PE4_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_PE4_SET 0x00100000 ++/** Activate PE3 ++ Sets the activation flag of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ ++#define SYS_GPE_ACT_PE3 0x00080000 ++/* No-Operation ++#define SYS_GPE_ACT_PE3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_PE3_SET 0x00080000 ++/** Activate PE2 ++ Sets the activation flag of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ ++#define SYS_GPE_ACT_PE2 0x00040000 ++/* No-Operation ++#define SYS_GPE_ACT_PE2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_PE2_SET 0x00040000 ++/** Activate PE1 ++ Sets the activation flag of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ ++#define SYS_GPE_ACT_PE1 0x00020000 ++/* No-Operation ++#define SYS_GPE_ACT_PE1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_PE1_SET 0x00020000 ++/** Activate PE0 ++ Sets the activation flag of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ ++#define SYS_GPE_ACT_PE0 0x00010000 ++/* No-Operation ++#define SYS_GPE_ACT_PE0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_PE0_SET 0x00010000 ++/** Activate ARB ++ Sets the activation flag of the ARB domain. This domain contains the Arbiter. */ ++#define SYS_GPE_ACT_ARB 0x00002000 ++/* No-Operation ++#define SYS_GPE_ACT_ARB_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_ARB_SET 0x00002000 ++/** Activate FSQM ++ Sets the activation flag of the FSQM domain. This domain contains the FSQM. */ ++#define SYS_GPE_ACT_FSQM 0x00001000 ++/* No-Operation ++#define SYS_GPE_ACT_FSQM_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_FSQM_SET 0x00001000 ++/** Activate TMU ++ Sets the activation flag of the TMU domain. This domain contains the TMU. */ ++#define SYS_GPE_ACT_TMU 0x00000800 ++/* No-Operation ++#define SYS_GPE_ACT_TMU_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_TMU_SET 0x00000800 ++/** Activate MRG ++ Sets the activation flag of the MRG domain. This domain contains the Merger. */ ++#define SYS_GPE_ACT_MRG 0x00000400 ++/* No-Operation ++#define SYS_GPE_ACT_MRG_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_MRG_SET 0x00000400 ++/** Activate DISP ++ Sets the activation flag of the DISP domain. This domain contains the Dispatcher. */ ++#define SYS_GPE_ACT_DISP 0x00000200 ++/* No-Operation ++#define SYS_GPE_ACT_DISP_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_DISP_SET 0x00000200 ++/** Activate IQM ++ Sets the activation flag of the IQM domain. This domain contains the IQM. */ ++#define SYS_GPE_ACT_IQM 0x00000100 ++/* No-Operation ++#define SYS_GPE_ACT_IQM_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_IQM_SET 0x00000100 ++/** Activate CPUE ++ Sets the activation flag of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ ++#define SYS_GPE_ACT_CPUE 0x00000080 ++/* No-Operation ++#define SYS_GPE_ACT_CPUE_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_CPUE_SET 0x00000080 ++/** Activate CPUI ++ Sets the activation flag of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ ++#define SYS_GPE_ACT_CPUI 0x00000040 ++/* No-Operation ++#define SYS_GPE_ACT_CPUI_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_CPUI_SET 0x00000040 ++/** Activate GPONE ++ Sets the activation flag of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ ++#define SYS_GPE_ACT_GPONE 0x00000020 ++/* No-Operation ++#define SYS_GPE_ACT_GPONE_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_GPONE_SET 0x00000020 ++/** Activate GPONI ++ Sets the activation flag of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ ++#define SYS_GPE_ACT_GPONI 0x00000010 ++/* No-Operation ++#define SYS_GPE_ACT_GPONI_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_GPONI_SET 0x00000010 ++/** Activate LAN3 ++ Sets the activation flag of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ ++#define SYS_GPE_ACT_LAN3 0x00000008 ++/* No-Operation ++#define SYS_GPE_ACT_LAN3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_LAN3_SET 0x00000008 ++/** Activate LAN2 ++ Sets the activation flag of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ ++#define SYS_GPE_ACT_LAN2 0x00000004 ++/* No-Operation ++#define SYS_GPE_ACT_LAN2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_LAN2_SET 0x00000004 ++/** Activate LAN1 ++ Sets the activation flag of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ ++#define SYS_GPE_ACT_LAN1 0x00000002 ++/* No-Operation ++#define SYS_GPE_ACT_LAN1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_LAN1_SET 0x00000002 ++/** Activate LAN0 ++ Sets the activation flag of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ ++#define SYS_GPE_ACT_LAN0 0x00000001 ++/* No-Operation ++#define SYS_GPE_ACT_LAN0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_LAN0_SET 0x00000001 ++ ++/* Fields of "Deactivation Register" */ ++/** Deactivate COP7 ++ Clears the activation flag of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ ++#define SYS_GPE_DEACT_COP7 0x80000000 ++/* No-Operation ++#define SYS_GPE_DEACT_COP7_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_COP7_CLR 0x80000000 ++/** Deactivate COP6 ++ Clears the activation flag of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ ++#define SYS_GPE_DEACT_COP6 0x40000000 ++/* No-Operation ++#define SYS_GPE_DEACT_COP6_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_COP6_CLR 0x40000000 ++/** Deactivate COP5 ++ Clears the activation flag of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ ++#define SYS_GPE_DEACT_COP5 0x20000000 ++/* No-Operation ++#define SYS_GPE_DEACT_COP5_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_COP5_CLR 0x20000000 ++/** Deactivate COP4 ++ Clears the activation flag of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ ++#define SYS_GPE_DEACT_COP4 0x10000000 ++/* No-Operation ++#define SYS_GPE_DEACT_COP4_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_COP4_CLR 0x10000000 ++/** Deactivate COP3 ++ Clears the activation flag of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ ++#define SYS_GPE_DEACT_COP3 0x08000000 ++/* No-Operation ++#define SYS_GPE_DEACT_COP3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_COP3_CLR 0x08000000 ++/** Deactivate COP2 ++ Clears the activation flag of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ ++#define SYS_GPE_DEACT_COP2 0x04000000 ++/* No-Operation ++#define SYS_GPE_DEACT_COP2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_COP2_CLR 0x04000000 ++/** Deactivate COP1 ++ Clears the activation flag of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ ++#define SYS_GPE_DEACT_COP1 0x02000000 ++/* No-Operation ++#define SYS_GPE_DEACT_COP1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_COP1_CLR 0x02000000 ++/** Deactivate COP0 ++ Clears the activation flag of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ ++#define SYS_GPE_DEACT_COP0 0x01000000 ++/* No-Operation ++#define SYS_GPE_DEACT_COP0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_COP0_CLR 0x01000000 ++/** Deactivate PE5 ++ Clears the activation flag of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ ++#define SYS_GPE_DEACT_PE5 0x00200000 ++/* No-Operation ++#define SYS_GPE_DEACT_PE5_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_PE5_CLR 0x00200000 ++/** Deactivate PE4 ++ Clears the activation flag of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ ++#define SYS_GPE_DEACT_PE4 0x00100000 ++/* No-Operation ++#define SYS_GPE_DEACT_PE4_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_PE4_CLR 0x00100000 ++/** Deactivate PE3 ++ Clears the activation flag of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ ++#define SYS_GPE_DEACT_PE3 0x00080000 ++/* No-Operation ++#define SYS_GPE_DEACT_PE3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_PE3_CLR 0x00080000 ++/** Deactivate PE2 ++ Clears the activation flag of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ ++#define SYS_GPE_DEACT_PE2 0x00040000 ++/* No-Operation ++#define SYS_GPE_DEACT_PE2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_PE2_CLR 0x00040000 ++/** Deactivate PE1 ++ Clears the activation flag of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ ++#define SYS_GPE_DEACT_PE1 0x00020000 ++/* No-Operation ++#define SYS_GPE_DEACT_PE1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_PE1_CLR 0x00020000 ++/** Deactivate PE0 ++ Clears the activation flag of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ ++#define SYS_GPE_DEACT_PE0 0x00010000 ++/* No-Operation ++#define SYS_GPE_DEACT_PE0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_PE0_CLR 0x00010000 ++/** Deactivate ARB ++ Clears the activation flag of the ARB domain. This domain contains the Arbiter. */ ++#define SYS_GPE_DEACT_ARB 0x00002000 ++/* No-Operation ++#define SYS_GPE_DEACT_ARB_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_ARB_CLR 0x00002000 ++/** Deactivate FSQM ++ Clears the activation flag of the FSQM domain. This domain contains the FSQM. */ ++#define SYS_GPE_DEACT_FSQM 0x00001000 ++/* No-Operation ++#define SYS_GPE_DEACT_FSQM_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_FSQM_CLR 0x00001000 ++/** Deactivate TMU ++ Clears the activation flag of the TMU domain. This domain contains the TMU. */ ++#define SYS_GPE_DEACT_TMU 0x00000800 ++/* No-Operation ++#define SYS_GPE_DEACT_TMU_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_TMU_CLR 0x00000800 ++/** Deactivate MRG ++ Clears the activation flag of the MRG domain. This domain contains the Merger. */ ++#define SYS_GPE_DEACT_MRG 0x00000400 ++/* No-Operation ++#define SYS_GPE_DEACT_MRG_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_MRG_CLR 0x00000400 ++/** Deactivate DISP ++ Clears the activation flag of the DISP domain. This domain contains the Dispatcher. */ ++#define SYS_GPE_DEACT_DISP 0x00000200 ++/* No-Operation ++#define SYS_GPE_DEACT_DISP_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_DISP_CLR 0x00000200 ++/** Deactivate IQM ++ Clears the activation flag of the IQM domain. This domain contains the IQM. */ ++#define SYS_GPE_DEACT_IQM 0x00000100 ++/* No-Operation ++#define SYS_GPE_DEACT_IQM_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_IQM_CLR 0x00000100 ++/** Deactivate CPUE ++ Clears the activation flag of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ ++#define SYS_GPE_DEACT_CPUE 0x00000080 ++/* No-Operation ++#define SYS_GPE_DEACT_CPUE_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_CPUE_CLR 0x00000080 ++/** Deactivate CPUI ++ Clears the activation flag of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ ++#define SYS_GPE_DEACT_CPUI 0x00000040 ++/* No-Operation ++#define SYS_GPE_DEACT_CPUI_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_CPUI_CLR 0x00000040 ++/** Deactivate GPONE ++ Clears the activation flag of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ ++#define SYS_GPE_DEACT_GPONE 0x00000020 ++/* No-Operation ++#define SYS_GPE_DEACT_GPONE_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_GPONE_CLR 0x00000020 ++/** Deactivate GPONI ++ Clears the activation flag of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ ++#define SYS_GPE_DEACT_GPONI 0x00000010 ++/* No-Operation ++#define SYS_GPE_DEACT_GPONI_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_GPONI_CLR 0x00000010 ++/** Deactivate LAN3 ++ Clears the activation flag of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ ++#define SYS_GPE_DEACT_LAN3 0x00000008 ++/* No-Operation ++#define SYS_GPE_DEACT_LAN3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_LAN3_CLR 0x00000008 ++/** Deactivate LAN2 ++ Clears the activation flag of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ ++#define SYS_GPE_DEACT_LAN2 0x00000004 ++/* No-Operation ++#define SYS_GPE_DEACT_LAN2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_LAN2_CLR 0x00000004 ++/** Deactivate LAN1 ++ Clears the activation flag of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ ++#define SYS_GPE_DEACT_LAN1 0x00000002 ++/* No-Operation ++#define SYS_GPE_DEACT_LAN1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_LAN1_CLR 0x00000002 ++/** Deactivate LAN0 ++ Clears the activation flag of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ ++#define SYS_GPE_DEACT_LAN0 0x00000001 ++/* No-Operation ++#define SYS_GPE_DEACT_LAN0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_LAN0_CLR 0x00000001 ++ ++/* Fields of "Reboot Trigger Register" */ ++/** Reboot COP7 ++ Triggers a reboot of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ ++#define SYS_GPE_RBT_COP7 0x80000000 ++/* No-Operation ++#define SYS_GPE_RBT_COP7_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_COP7_TRIG 0x80000000 ++/** Reboot COP6 ++ Triggers a reboot of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ ++#define SYS_GPE_RBT_COP6 0x40000000 ++/* No-Operation ++#define SYS_GPE_RBT_COP6_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_COP6_TRIG 0x40000000 ++/** Reboot COP5 ++ Triggers a reboot of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ ++#define SYS_GPE_RBT_COP5 0x20000000 ++/* No-Operation ++#define SYS_GPE_RBT_COP5_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_COP5_TRIG 0x20000000 ++/** Reboot COP4 ++ Triggers a reboot of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ ++#define SYS_GPE_RBT_COP4 0x10000000 ++/* No-Operation ++#define SYS_GPE_RBT_COP4_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_COP4_TRIG 0x10000000 ++/** Reboot COP3 ++ Triggers a reboot of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ ++#define SYS_GPE_RBT_COP3 0x08000000 ++/* No-Operation ++#define SYS_GPE_RBT_COP3_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_COP3_TRIG 0x08000000 ++/** Reboot COP2 ++ Triggers a reboot of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ ++#define SYS_GPE_RBT_COP2 0x04000000 ++/* No-Operation ++#define SYS_GPE_RBT_COP2_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_COP2_TRIG 0x04000000 ++/** Reboot COP1 ++ Triggers a reboot of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ ++#define SYS_GPE_RBT_COP1 0x02000000 ++/* No-Operation ++#define SYS_GPE_RBT_COP1_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_COP1_TRIG 0x02000000 ++/** Reboot COP0 ++ Triggers a reboot of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ ++#define SYS_GPE_RBT_COP0 0x01000000 ++/* No-Operation ++#define SYS_GPE_RBT_COP0_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_COP0_TRIG 0x01000000 ++/** Reboot PE5 ++ Triggers a reboot of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ ++#define SYS_GPE_RBT_PE5 0x00200000 ++/* No-Operation ++#define SYS_GPE_RBT_PE5_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_PE5_TRIG 0x00200000 ++/** Reboot PE4 ++ Triggers a reboot of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ ++#define SYS_GPE_RBT_PE4 0x00100000 ++/* No-Operation ++#define SYS_GPE_RBT_PE4_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_PE4_TRIG 0x00100000 ++/** Reboot PE3 ++ Triggers a reboot of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ ++#define SYS_GPE_RBT_PE3 0x00080000 ++/* No-Operation ++#define SYS_GPE_RBT_PE3_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_PE3_TRIG 0x00080000 ++/** Reboot PE2 ++ Triggers a reboot of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ ++#define SYS_GPE_RBT_PE2 0x00040000 ++/* No-Operation ++#define SYS_GPE_RBT_PE2_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_PE2_TRIG 0x00040000 ++/** Reboot PE1 ++ Triggers a reboot of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ ++#define SYS_GPE_RBT_PE1 0x00020000 ++/* No-Operation ++#define SYS_GPE_RBT_PE1_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_PE1_TRIG 0x00020000 ++/** Reboot PE0 ++ Triggers a reboot of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ ++#define SYS_GPE_RBT_PE0 0x00010000 ++/* No-Operation ++#define SYS_GPE_RBT_PE0_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_PE0_TRIG 0x00010000 ++/** Reboot ARB ++ Triggers a reboot of the ARB domain. This domain contains the Arbiter. */ ++#define SYS_GPE_RBT_ARB 0x00002000 ++/* No-Operation ++#define SYS_GPE_RBT_ARB_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_ARB_TRIG 0x00002000 ++/** Reboot FSQM ++ Triggers a reboot of the FSQM domain. This domain contains the FSQM. */ ++#define SYS_GPE_RBT_FSQM 0x00001000 ++/* No-Operation ++#define SYS_GPE_RBT_FSQM_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_FSQM_TRIG 0x00001000 ++/** Reboot TMU ++ Triggers a reboot of the TMU domain. This domain contains the TMU. */ ++#define SYS_GPE_RBT_TMU 0x00000800 ++/* No-Operation ++#define SYS_GPE_RBT_TMU_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_TMU_TRIG 0x00000800 ++/** Reboot MRG ++ Triggers a reboot of the MRG domain. This domain contains the Merger. */ ++#define SYS_GPE_RBT_MRG 0x00000400 ++/* No-Operation ++#define SYS_GPE_RBT_MRG_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_MRG_TRIG 0x00000400 ++/** Reboot DISP ++ Triggers a reboot of the DISP domain. This domain contains the Dispatcher. */ ++#define SYS_GPE_RBT_DISP 0x00000200 ++/* No-Operation ++#define SYS_GPE_RBT_DISP_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_DISP_TRIG 0x00000200 ++/** Reboot IQM ++ Triggers a reboot of the IQM domain. This domain contains the IQM. */ ++#define SYS_GPE_RBT_IQM 0x00000100 ++/* No-Operation ++#define SYS_GPE_RBT_IQM_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_IQM_TRIG 0x00000100 ++/** Reboot CPUE ++ Triggers a reboot of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ ++#define SYS_GPE_RBT_CPUE 0x00000080 ++/* No-Operation ++#define SYS_GPE_RBT_CPUE_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_CPUE_TRIG 0x00000080 ++/** Reboot CPUI ++ Triggers a reboot of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ ++#define SYS_GPE_RBT_CPUI 0x00000040 ++/* No-Operation ++#define SYS_GPE_RBT_CPUI_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_CPUI_TRIG 0x00000040 ++/** Reboot GPONE ++ Triggers a reboot of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ ++#define SYS_GPE_RBT_GPONE 0x00000020 ++/* No-Operation ++#define SYS_GPE_RBT_GPONE_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_GPONE_TRIG 0x00000020 ++/** Reboot GPONI ++ Triggers a reboot of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ ++#define SYS_GPE_RBT_GPONI 0x00000010 ++/* No-Operation ++#define SYS_GPE_RBT_GPONI_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_GPONI_TRIG 0x00000010 ++/** Reboot LAN3 ++ Triggers a reboot of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ ++#define SYS_GPE_RBT_LAN3 0x00000008 ++/* No-Operation ++#define SYS_GPE_RBT_LAN3_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_LAN3_TRIG 0x00000008 ++/** Reboot LAN2 ++ Triggers a reboot of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ ++#define SYS_GPE_RBT_LAN2 0x00000004 ++/* No-Operation ++#define SYS_GPE_RBT_LAN2_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_LAN2_TRIG 0x00000004 ++/** Reboot LAN1 ++ Triggers a reboot of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ ++#define SYS_GPE_RBT_LAN1 0x00000002 ++/* No-Operation ++#define SYS_GPE_RBT_LAN1_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_LAN1_TRIG 0x00000002 ++/** Reboot LAN0 ++ Triggers a reboot of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ ++#define SYS_GPE_RBT_LAN0 0x00000001 ++/* No-Operation ++#define SYS_GPE_RBT_LAN0_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_LAN0_TRIG 0x00000001 ++ ++/* Fields of "Power Down Configuration Register" */ ++/** Enable Power Down COP7 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_COP7 0x80000000 ++/* Disable ++#define SYS_GPE_PDCFG_COP7_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_COP7_EN 0x80000000 ++/** Enable Power Down COP6 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_COP6 0x40000000 ++/* Disable ++#define SYS_GPE_PDCFG_COP6_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_COP6_EN 0x40000000 ++/** Enable Power Down COP5 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_COP5 0x20000000 ++/* Disable ++#define SYS_GPE_PDCFG_COP5_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_COP5_EN 0x20000000 ++/** Enable Power Down COP4 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_COP4 0x10000000 ++/* Disable ++#define SYS_GPE_PDCFG_COP4_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_COP4_EN 0x10000000 ++/** Enable Power Down COP3 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_COP3 0x08000000 ++/* Disable ++#define SYS_GPE_PDCFG_COP3_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_COP3_EN 0x08000000 ++/** Enable Power Down COP2 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_COP2 0x04000000 ++/* Disable ++#define SYS_GPE_PDCFG_COP2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_COP2_EN 0x04000000 ++/** Enable Power Down COP1 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_COP1 0x02000000 ++/* Disable ++#define SYS_GPE_PDCFG_COP1_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_COP1_EN 0x02000000 ++/** Enable Power Down COP0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_COP0 0x01000000 ++/* Disable ++#define SYS_GPE_PDCFG_COP0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_COP0_EN 0x01000000 ++/** Enable Power Down PE5 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_PE5 0x00200000 ++/* Disable ++#define SYS_GPE_PDCFG_PE5_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_PE5_EN 0x00200000 ++/** Enable Power Down PE4 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_PE4 0x00100000 ++/* Disable ++#define SYS_GPE_PDCFG_PE4_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_PE4_EN 0x00100000 ++/** Enable Power Down PE3 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_PE3 0x00080000 ++/* Disable ++#define SYS_GPE_PDCFG_PE3_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_PE3_EN 0x00080000 ++/** Enable Power Down PE2 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_PE2 0x00040000 ++/* Disable ++#define SYS_GPE_PDCFG_PE2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_PE2_EN 0x00040000 ++/** Enable Power Down PE1 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_PE1 0x00020000 ++/* Disable ++#define SYS_GPE_PDCFG_PE1_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_PE1_EN 0x00020000 ++/** Enable Power Down PE0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_PE0 0x00010000 ++/* Disable ++#define SYS_GPE_PDCFG_PE0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_PE0_EN 0x00010000 ++/** Enable Power Down ARB ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_ARB 0x00002000 ++/* Disable ++#define SYS_GPE_PDCFG_ARB_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_ARB_EN 0x00002000 ++/** Enable Power Down FSQM ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_FSQM 0x00001000 ++/* Disable ++#define SYS_GPE_PDCFG_FSQM_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_FSQM_EN 0x00001000 ++/** Enable Power Down TMU ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_TMU 0x00000800 ++/* Disable ++#define SYS_GPE_PDCFG_TMU_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_TMU_EN 0x00000800 ++/** Enable Power Down MRG ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_MRG 0x00000400 ++/* Disable ++#define SYS_GPE_PDCFG_MRG_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_MRG_EN 0x00000400 ++/** Enable Power Down DISP ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_DISP 0x00000200 ++/* Disable ++#define SYS_GPE_PDCFG_DISP_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_DISP_EN 0x00000200 ++/** Enable Power Down IQM ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_IQM 0x00000100 ++/* Disable ++#define SYS_GPE_PDCFG_IQM_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_IQM_EN 0x00000100 ++/** Enable Power Down CPUE ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_CPUE 0x00000080 ++/* Disable ++#define SYS_GPE_PDCFG_CPUE_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_CPUE_EN 0x00000080 ++/** Enable Power Down CPUI ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_CPUI 0x00000040 ++/* Disable ++#define SYS_GPE_PDCFG_CPUI_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_CPUI_EN 0x00000040 ++/** Enable Power Down GPONE ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_GPONE 0x00000020 ++/* Disable ++#define SYS_GPE_PDCFG_GPONE_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_GPONE_EN 0x00000020 ++/** Enable Power Down GPONI ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_GPONI 0x00000010 ++/* Disable ++#define SYS_GPE_PDCFG_GPONI_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_GPONI_EN 0x00000010 ++/** Enable Power Down LAN3 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_LAN3 0x00000008 ++/* Disable ++#define SYS_GPE_PDCFG_LAN3_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_LAN3_EN 0x00000008 ++/** Enable Power Down LAN2 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_LAN2 0x00000004 ++/* Disable ++#define SYS_GPE_PDCFG_LAN2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_LAN2_EN 0x00000004 ++/** Enable Power Down LAN1 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_LAN1 0x00000002 ++/* Disable ++#define SYS_GPE_PDCFG_LAN1_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_LAN1_EN 0x00000002 ++/** Enable Power Down LAN0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_LAN0 0x00000001 ++/* Disable ++#define SYS_GPE_PDCFG_LAN0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_LAN0_EN 0x00000001 ++ ++/* Fields of "Sleep Source Configuration Register" */ ++/** Sleep/Wakeup Source CPU ++ Selects the CPU access signal as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_CPU 0x00020000 ++/* Not selected ++#define SYS_GPE_SSCFG_CPU_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_CPU_SEL 0x00020000 ++/** Sleep/Wakeup Source FSQM ++ Selects the FSQM signal as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_FSQM 0x00008000 ++/* Not selected ++#define SYS_GPE_SSCFG_FSQM_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_FSQM_SEL 0x00008000 ++/** Sleep/Wakeup Source GPONT ++ Selects the FIFO empty signal of the TCONT Request FIFO of port GPON as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_GPONT 0x00002000 ++/* Not selected ++#define SYS_GPE_SSCFG_GPONT_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_GPONT_SEL 0x00002000 ++/** Sleep/Wakeup Source GPONE ++ Selects the FIFO empty signal of the EGRESS FIFO of port GPON as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_GPONE 0x00001000 ++/* Not selected ++#define SYS_GPE_SSCFG_GPONE_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_GPONE_SEL 0x00001000 ++/** Sleep/Wakeup Source LAN3E ++ Selects the FIFO empty signal of the EGRESS FIFO of port LAN3 as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_LAN3E 0x00000800 ++/* Not selected ++#define SYS_GPE_SSCFG_LAN3E_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_LAN3E_SEL 0x00000800 ++/** Sleep/Wakeup Source LAN2E ++ Selects the FIFO empty signal of the EGRESS FIFO of port LAN2 as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_LAN2E 0x00000400 ++/* Not selected ++#define SYS_GPE_SSCFG_LAN2E_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_LAN2E_SEL 0x00000400 ++/** Sleep/Wakeup Source LAN1E ++ Selects the FIFO empty signal of the EGRESS FIFO of port LAN1 as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_LAN1E 0x00000200 ++/* Not selected ++#define SYS_GPE_SSCFG_LAN1E_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_LAN1E_SEL 0x00000200 ++/** Sleep/Wakeup Source LAN0E ++ Selects the FIFO empty signal of the EGRESS FIFO of port LAN0 as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_LAN0E 0x00000100 ++/* Not selected ++#define SYS_GPE_SSCFG_LAN0E_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_LAN0E_SEL 0x00000100 ++/** Sleep/Wakeup Source GPONI ++ Selects the FIFO empty signal of the INGRESS FIFO of port GPON as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_GPONI 0x00000010 ++/* Not selected ++#define SYS_GPE_SSCFG_GPONI_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_GPONI_SEL 0x00000010 ++/** Sleep/Wakeup Source LAN3I ++ Selects the FIFO empty signal of the INGRESS FIFO of port LAN3 as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_LAN3I 0x00000008 ++/* Not selected ++#define SYS_GPE_SSCFG_LAN3I_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_LAN3I_SEL 0x00000008 ++/** Sleep/Wakeup Source LAN2I ++ Selects the FIFO empty signal of the INGRESS FIFO of port LAN2 as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_LAN2I 0x00000004 ++/* Not selected ++#define SYS_GPE_SSCFG_LAN2I_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_LAN2I_SEL 0x00000004 ++/** Sleep/Wakeup Source LAN1I ++ Selects the FIFO empty signal of the INGRESS FIFO of port LAN1 as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_LAN1I 0x00000002 ++/* Not selected ++#define SYS_GPE_SSCFG_LAN1I_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_LAN1I_SEL 0x00000002 ++/** Sleep/Wakeup Source LAN0I ++ Selects the FIFO empty signal of the INGRESS FIFO of port LAN0 as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_LAN0I 0x00000001 ++/* Not selected ++#define SYS_GPE_SSCFG_LAN0I_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_LAN0I_SEL 0x00000001 ++ ++/* Fields of "Sleep Source Timer Register" */ ++/** Sleep Delay Value ++ A HW sleep request is delayed by this value multiplied by 3.2ns before it takes effect. A wakeup request is not delayed but takes effect immediately. Values lower than 256 are limited to 256. */ ++#define SYS_GPE_SST_SDV_MASK 0x7FFFFFFF ++/** field offset */ ++#define SYS_GPE_SST_SDV_OFFSET 0 ++ ++/* Fields of "Sleep Destination Status Register" */ ++/** Shutoff COP7 on HW Sleep ++ If selected the domain COP7 is shutoff on a hardware sleep request. This domain contains the Coprocessor 7 of the SCE. */ ++#define SYS_GPE_SDS_COP7 0x80000000 ++/* Not selected ++#define SYS_GPE_SDS_COP7_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_COP7_SEL 0x80000000 ++/** Shutoff COP6 on HW Sleep ++ If selected the domain COP6 is shutoff on a hardware sleep request. This domain contains the Coprocessor 6 of the SCE. */ ++#define SYS_GPE_SDS_COP6 0x40000000 ++/* Not selected ++#define SYS_GPE_SDS_COP6_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_COP6_SEL 0x40000000 ++/** Shutoff COP5 on HW Sleep ++ If selected the domain COP5 is shutoff on a hardware sleep request. This domain contains the Coprocessor 5 of the SCE. */ ++#define SYS_GPE_SDS_COP5 0x20000000 ++/* Not selected ++#define SYS_GPE_SDS_COP5_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_COP5_SEL 0x20000000 ++/** Shutoff COP4 on HW Sleep ++ If selected the domain COP4 is shutoff on a hardware sleep request. This domain contains the Coprocessor 4 of the SCE. */ ++#define SYS_GPE_SDS_COP4 0x10000000 ++/* Not selected ++#define SYS_GPE_SDS_COP4_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_COP4_SEL 0x10000000 ++/** Shutoff COP3 on HW Sleep ++ If selected the domain COP3 is shutoff on a hardware sleep request. This domain contains the Coprocessor 3 of the SCE. */ ++#define SYS_GPE_SDS_COP3 0x08000000 ++/* Not selected ++#define SYS_GPE_SDS_COP3_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_COP3_SEL 0x08000000 ++/** Shutoff COP2 on HW Sleep ++ If selected the domain COP2 is shutoff on a hardware sleep request. This domain contains the Coprocessor 2 of the SCE. */ ++#define SYS_GPE_SDS_COP2 0x04000000 ++/* Not selected ++#define SYS_GPE_SDS_COP2_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_COP2_SEL 0x04000000 ++/** Shutoff COP1 on HW Sleep ++ If selected the domain COP1 is shutoff on a hardware sleep request. This domain contains the Coprocessor 1 of the SCE. */ ++#define SYS_GPE_SDS_COP1 0x02000000 ++/* Not selected ++#define SYS_GPE_SDS_COP1_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_COP1_SEL 0x02000000 ++/** Shutoff COP0 on HW Sleep ++ If selected the domain COP0 is shutoff on a hardware sleep request. This domain contains the Coprocessor 0 of the SCE. */ ++#define SYS_GPE_SDS_COP0 0x01000000 ++/* Not selected ++#define SYS_GPE_SDS_COP0_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_COP0_SEL 0x01000000 ++/** Shutoff PE5 on HW Sleep ++ If selected the domain PE5 is shutoff on a hardware sleep request. This domain contains the Processing Element 5 of the SCE. */ ++#define SYS_GPE_SDS_PE5 0x00200000 ++/* Not selected ++#define SYS_GPE_SDS_PE5_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_PE5_SEL 0x00200000 ++/** Shutoff PE4 on HW Sleep ++ If selected the domain PE4 is shutoff on a hardware sleep request. This domain contains the Processing Element 4 of the SCE. */ ++#define SYS_GPE_SDS_PE4 0x00100000 ++/* Not selected ++#define SYS_GPE_SDS_PE4_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_PE4_SEL 0x00100000 ++/** Shutoff PE3 on HW Sleep ++ If selected the domain PE3 is shutoff on a hardware sleep request. This domain contains the Processing Element 3 of the SCE. */ ++#define SYS_GPE_SDS_PE3 0x00080000 ++/* Not selected ++#define SYS_GPE_SDS_PE3_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_PE3_SEL 0x00080000 ++/** Shutoff PE2 on HW Sleep ++ If selected the domain PE2 is shutoff on a hardware sleep request. This domain contains the Processing Element 2 of the SCE. */ ++#define SYS_GPE_SDS_PE2 0x00040000 ++/* Not selected ++#define SYS_GPE_SDS_PE2_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_PE2_SEL 0x00040000 ++/** Shutoff PE1 on HW Sleep ++ If selected the domain PE1 is shutoff on a hardware sleep request. This domain contains the Processing Element 1 of the SCE. */ ++#define SYS_GPE_SDS_PE1 0x00020000 ++/* Not selected ++#define SYS_GPE_SDS_PE1_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_PE1_SEL 0x00020000 ++/** Shutoff PE0 on HW Sleep ++ If selected the domain PE0 is shutoff on a hardware sleep request. This domain contains the Processing Element 0 of the SCE. */ ++#define SYS_GPE_SDS_PE0 0x00010000 ++/* Not selected ++#define SYS_GPE_SDS_PE0_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_PE0_SEL 0x00010000 ++/** Shutoff ARB on HW Sleep ++ If selected the domain ARB is shutoff on a hardware sleep request. This domain contains the Arbiter. */ ++#define SYS_GPE_SDS_ARB 0x00002000 ++/* Not selected ++#define SYS_GPE_SDS_ARB_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_ARB_SEL 0x00002000 ++/** Shutoff FSQM on HW Sleep ++ If selected the domain FSQM is shutoff on a hardware sleep request. This domain contains the FSQM. */ ++#define SYS_GPE_SDS_FSQM 0x00001000 ++/* Not selected ++#define SYS_GPE_SDS_FSQM_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_FSQM_SEL 0x00001000 ++/** Shutoff TMU on HW Sleep ++ If selected the domain TMU is shutoff on a hardware sleep request. This domain contains the TMU. */ ++#define SYS_GPE_SDS_TMU 0x00000800 ++/* Not selected ++#define SYS_GPE_SDS_TMU_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_TMU_SEL 0x00000800 ++/** Shutoff MRG on HW Sleep ++ If selected the domain MRG is shutoff on a hardware sleep request. This domain contains the Merger. */ ++#define SYS_GPE_SDS_MRG 0x00000400 ++/* Not selected ++#define SYS_GPE_SDS_MRG_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_MRG_SEL 0x00000400 ++/** Shutoff DISP on HW Sleep ++ If selected the domain DISP is shutoff on a hardware sleep request. This domain contains the Dispatcher. */ ++#define SYS_GPE_SDS_DISP 0x00000200 ++/* Not selected ++#define SYS_GPE_SDS_DISP_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_DISP_SEL 0x00000200 ++/** Shutoff IQM on HW Sleep ++ If selected the domain IQM is shutoff on a hardware sleep request. This domain contains the IQM. */ ++#define SYS_GPE_SDS_IQM 0x00000100 ++/* Not selected ++#define SYS_GPE_SDS_IQM_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_IQM_SEL 0x00000100 ++/** Shutoff CPUE on HW Sleep ++ If selected the domain CPUE is shutoff on a hardware sleep request. This domain contains all parts related to the CPU EGRESS interface. */ ++#define SYS_GPE_SDS_CPUE 0x00000080 ++/* Not selected ++#define SYS_GPE_SDS_CPUE_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_CPUE_SEL 0x00000080 ++/** Shutoff CPUI on HW Sleep ++ If selected the domain CPUI is shutoff on a hardware sleep request. This domain contains all parts related to the CPU INGRESS interface. */ ++#define SYS_GPE_SDS_CPUI 0x00000040 ++/* Not selected ++#define SYS_GPE_SDS_CPUI_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_CPUI_SEL 0x00000040 ++/** Shutoff GPONE on HW Sleep ++ If selected the domain GPONE is shutoff on a hardware sleep request. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ ++#define SYS_GPE_SDS_GPONE 0x00000020 ++/* Not selected ++#define SYS_GPE_SDS_GPONE_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_GPONE_SEL 0x00000020 ++/** Shutoff GPONI on HW Sleep ++ If selected the domain GPONI is shutoff on a hardware sleep request. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ ++#define SYS_GPE_SDS_GPONI 0x00000010 ++/* Not selected ++#define SYS_GPE_SDS_GPONI_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_GPONI_SEL 0x00000010 ++/** Shutoff LAN3 on HW Sleep ++ If selected the domain LAN3 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN3 interface. */ ++#define SYS_GPE_SDS_LAN3 0x00000008 ++/* Not selected ++#define SYS_GPE_SDS_LAN3_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_LAN3_SEL 0x00000008 ++/** Shutoff LAN2 on HW Sleep ++ If selected the domain LAN2 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN2 interface. */ ++#define SYS_GPE_SDS_LAN2 0x00000004 ++/* Not selected ++#define SYS_GPE_SDS_LAN2_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_LAN2_SEL 0x00000004 ++/** Shutoff LAN1 on HW Sleep ++ If selected the domain LAN1 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN1 interface. */ ++#define SYS_GPE_SDS_LAN1 0x00000002 ++/* Not selected ++#define SYS_GPE_SDS_LAN1_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_LAN1_SEL 0x00000002 ++/** Shutoff LAN0 on HW Sleep ++ If selected the domain LAN0 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN0 interface. */ ++#define SYS_GPE_SDS_LAN0 0x00000001 ++/* Not selected ++#define SYS_GPE_SDS_LAN0_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_LAN0_SEL 0x00000001 ++ ++/* Fields of "Sleep Destination Set Register" */ ++/** Set Sleep Selection COP7 ++ Sets the selection bit for domain COP7This domain contains the Coprocessor 7 of the SCE. */ ++#define SYS_GPE_SDSET_COP7 0x80000000 ++/* No-Operation ++#define SYS_GPE_SDSET_COP7_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_COP7_SET 0x80000000 ++/** Set Sleep Selection COP6 ++ Sets the selection bit for domain COP6This domain contains the Coprocessor 6 of the SCE. */ ++#define SYS_GPE_SDSET_COP6 0x40000000 ++/* No-Operation ++#define SYS_GPE_SDSET_COP6_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_COP6_SET 0x40000000 ++/** Set Sleep Selection COP5 ++ Sets the selection bit for domain COP5This domain contains the Coprocessor 5 of the SCE. */ ++#define SYS_GPE_SDSET_COP5 0x20000000 ++/* No-Operation ++#define SYS_GPE_SDSET_COP5_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_COP5_SET 0x20000000 ++/** Set Sleep Selection COP4 ++ Sets the selection bit for domain COP4This domain contains the Coprocessor 4 of the SCE. */ ++#define SYS_GPE_SDSET_COP4 0x10000000 ++/* No-Operation ++#define SYS_GPE_SDSET_COP4_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_COP4_SET 0x10000000 ++/** Set Sleep Selection COP3 ++ Sets the selection bit for domain COP3This domain contains the Coprocessor 3 of the SCE. */ ++#define SYS_GPE_SDSET_COP3 0x08000000 ++/* No-Operation ++#define SYS_GPE_SDSET_COP3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_COP3_SET 0x08000000 ++/** Set Sleep Selection COP2 ++ Sets the selection bit for domain COP2This domain contains the Coprocessor 2 of the SCE. */ ++#define SYS_GPE_SDSET_COP2 0x04000000 ++/* No-Operation ++#define SYS_GPE_SDSET_COP2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_COP2_SET 0x04000000 ++/** Set Sleep Selection COP1 ++ Sets the selection bit for domain COP1This domain contains the Coprocessor 1 of the SCE. */ ++#define SYS_GPE_SDSET_COP1 0x02000000 ++/* No-Operation ++#define SYS_GPE_SDSET_COP1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_COP1_SET 0x02000000 ++/** Set Sleep Selection COP0 ++ Sets the selection bit for domain COP0This domain contains the Coprocessor 0 of the SCE. */ ++#define SYS_GPE_SDSET_COP0 0x01000000 ++/* No-Operation ++#define SYS_GPE_SDSET_COP0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_COP0_SET 0x01000000 ++/** Set Sleep Selection PE5 ++ Sets the selection bit for domain PE5This domain contains the Processing Element 5 of the SCE. */ ++#define SYS_GPE_SDSET_PE5 0x00200000 ++/* No-Operation ++#define SYS_GPE_SDSET_PE5_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_PE5_SET 0x00200000 ++/** Set Sleep Selection PE4 ++ Sets the selection bit for domain PE4This domain contains the Processing Element 4 of the SCE. */ ++#define SYS_GPE_SDSET_PE4 0x00100000 ++/* No-Operation ++#define SYS_GPE_SDSET_PE4_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_PE4_SET 0x00100000 ++/** Set Sleep Selection PE3 ++ Sets the selection bit for domain PE3This domain contains the Processing Element 3 of the SCE. */ ++#define SYS_GPE_SDSET_PE3 0x00080000 ++/* No-Operation ++#define SYS_GPE_SDSET_PE3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_PE3_SET 0x00080000 ++/** Set Sleep Selection PE2 ++ Sets the selection bit for domain PE2This domain contains the Processing Element 2 of the SCE. */ ++#define SYS_GPE_SDSET_PE2 0x00040000 ++/* No-Operation ++#define SYS_GPE_SDSET_PE2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_PE2_SET 0x00040000 ++/** Set Sleep Selection PE1 ++ Sets the selection bit for domain PE1This domain contains the Processing Element 1 of the SCE. */ ++#define SYS_GPE_SDSET_PE1 0x00020000 ++/* No-Operation ++#define SYS_GPE_SDSET_PE1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_PE1_SET 0x00020000 ++/** Set Sleep Selection PE0 ++ Sets the selection bit for domain PE0This domain contains the Processing Element 0 of the SCE. */ ++#define SYS_GPE_SDSET_PE0 0x00010000 ++/* No-Operation ++#define SYS_GPE_SDSET_PE0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_PE0_SET 0x00010000 ++/** Set Sleep Selection ARB ++ Sets the selection bit for domain ARBThis domain contains the Arbiter. */ ++#define SYS_GPE_SDSET_ARB 0x00002000 ++/* No-Operation ++#define SYS_GPE_SDSET_ARB_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_ARB_SET 0x00002000 ++/** Set Sleep Selection FSQM ++ Sets the selection bit for domain FSQMThis domain contains the FSQM. */ ++#define SYS_GPE_SDSET_FSQM 0x00001000 ++/* No-Operation ++#define SYS_GPE_SDSET_FSQM_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_FSQM_SET 0x00001000 ++/** Set Sleep Selection TMU ++ Sets the selection bit for domain TMUThis domain contains the TMU. */ ++#define SYS_GPE_SDSET_TMU 0x00000800 ++/* No-Operation ++#define SYS_GPE_SDSET_TMU_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_TMU_SET 0x00000800 ++/** Set Sleep Selection MRG ++ Sets the selection bit for domain MRGThis domain contains the Merger. */ ++#define SYS_GPE_SDSET_MRG 0x00000400 ++/* No-Operation ++#define SYS_GPE_SDSET_MRG_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_MRG_SET 0x00000400 ++/** Set Sleep Selection DISP ++ Sets the selection bit for domain DISPThis domain contains the Dispatcher. */ ++#define SYS_GPE_SDSET_DISP 0x00000200 ++/* No-Operation ++#define SYS_GPE_SDSET_DISP_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_DISP_SET 0x00000200 ++/** Set Sleep Selection IQM ++ Sets the selection bit for domain IQMThis domain contains the IQM. */ ++#define SYS_GPE_SDSET_IQM 0x00000100 ++/* No-Operation ++#define SYS_GPE_SDSET_IQM_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_IQM_SET 0x00000100 ++/** Set Sleep Selection CPUE ++ Sets the selection bit for domain CPUEThis domain contains all parts related to the CPU EGRESS interface. */ ++#define SYS_GPE_SDSET_CPUE 0x00000080 ++/* No-Operation ++#define SYS_GPE_SDSET_CPUE_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_CPUE_SET 0x00000080 ++/** Set Sleep Selection CPUI ++ Sets the selection bit for domain CPUIThis domain contains all parts related to the CPU INGRESS interface. */ ++#define SYS_GPE_SDSET_CPUI 0x00000040 ++/* No-Operation ++#define SYS_GPE_SDSET_CPUI_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_CPUI_SET 0x00000040 ++/** Set Sleep Selection GPONE ++ Sets the selection bit for domain GPONEThis domain contains all parts related to the GPON (GTC) EGRESS interface. */ ++#define SYS_GPE_SDSET_GPONE 0x00000020 ++/* No-Operation ++#define SYS_GPE_SDSET_GPONE_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_GPONE_SET 0x00000020 ++/** Set Sleep Selection GPONI ++ Sets the selection bit for domain GPONIThis domain contains all parts related to the GPON (GTC) INGRESS interface. */ ++#define SYS_GPE_SDSET_GPONI 0x00000010 ++/* No-Operation ++#define SYS_GPE_SDSET_GPONI_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_GPONI_SET 0x00000010 ++/** Set Sleep Selection LAN3 ++ Sets the selection bit for domain LAN3This domain contains all parts related to the LAN3 interface. */ ++#define SYS_GPE_SDSET_LAN3 0x00000008 ++/* No-Operation ++#define SYS_GPE_SDSET_LAN3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_LAN3_SET 0x00000008 ++/** Set Sleep Selection LAN2 ++ Sets the selection bit for domain LAN2This domain contains all parts related to the LAN2 interface. */ ++#define SYS_GPE_SDSET_LAN2 0x00000004 ++/* No-Operation ++#define SYS_GPE_SDSET_LAN2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_LAN2_SET 0x00000004 ++/** Set Sleep Selection LAN1 ++ Sets the selection bit for domain LAN1This domain contains all parts related to the LAN1 interface. */ ++#define SYS_GPE_SDSET_LAN1 0x00000002 ++/* No-Operation ++#define SYS_GPE_SDSET_LAN1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_LAN1_SET 0x00000002 ++/** Set Sleep Selection LAN0 ++ Sets the selection bit for domain LAN0This domain contains all parts related to the LAN0 interface. */ ++#define SYS_GPE_SDSET_LAN0 0x00000001 ++/* No-Operation ++#define SYS_GPE_SDSET_LAN0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_LAN0_SET 0x00000001 ++ ++/* Fields of "Sleep Destination Clear Register" */ ++/** Clear Sleep Selection COP7 ++ Clears the selection bit for domain COP7This domain contains the Coprocessor 7 of the SCE. */ ++#define SYS_GPE_SDCLR_COP7 0x80000000 ++/* No-Operation ++#define SYS_GPE_SDCLR_COP7_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_COP7_CLR 0x80000000 ++/** Clear Sleep Selection COP6 ++ Clears the selection bit for domain COP6This domain contains the Coprocessor 6 of the SCE. */ ++#define SYS_GPE_SDCLR_COP6 0x40000000 ++/* No-Operation ++#define SYS_GPE_SDCLR_COP6_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_COP6_CLR 0x40000000 ++/** Clear Sleep Selection COP5 ++ Clears the selection bit for domain COP5This domain contains the Coprocessor 5 of the SCE. */ ++#define SYS_GPE_SDCLR_COP5 0x20000000 ++/* No-Operation ++#define SYS_GPE_SDCLR_COP5_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_COP5_CLR 0x20000000 ++/** Clear Sleep Selection COP4 ++ Clears the selection bit for domain COP4This domain contains the Coprocessor 4 of the SCE. */ ++#define SYS_GPE_SDCLR_COP4 0x10000000 ++/* No-Operation ++#define SYS_GPE_SDCLR_COP4_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_COP4_CLR 0x10000000 ++/** Clear Sleep Selection COP3 ++ Clears the selection bit for domain COP3This domain contains the Coprocessor 3 of the SCE. */ ++#define SYS_GPE_SDCLR_COP3 0x08000000 ++/* No-Operation ++#define SYS_GPE_SDCLR_COP3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_COP3_CLR 0x08000000 ++/** Clear Sleep Selection COP2 ++ Clears the selection bit for domain COP2This domain contains the Coprocessor 2 of the SCE. */ ++#define SYS_GPE_SDCLR_COP2 0x04000000 ++/* No-Operation ++#define SYS_GPE_SDCLR_COP2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_COP2_CLR 0x04000000 ++/** Clear Sleep Selection COP1 ++ Clears the selection bit for domain COP1This domain contains the Coprocessor 1 of the SCE. */ ++#define SYS_GPE_SDCLR_COP1 0x02000000 ++/* No-Operation ++#define SYS_GPE_SDCLR_COP1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_COP1_CLR 0x02000000 ++/** Clear Sleep Selection COP0 ++ Clears the selection bit for domain COP0This domain contains the Coprocessor 0 of the SCE. */ ++#define SYS_GPE_SDCLR_COP0 0x01000000 ++/* No-Operation ++#define SYS_GPE_SDCLR_COP0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_COP0_CLR 0x01000000 ++/** Clear Sleep Selection PE5 ++ Clears the selection bit for domain PE5This domain contains the Processing Element 5 of the SCE. */ ++#define SYS_GPE_SDCLR_PE5 0x00200000 ++/* No-Operation ++#define SYS_GPE_SDCLR_PE5_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_PE5_CLR 0x00200000 ++/** Clear Sleep Selection PE4 ++ Clears the selection bit for domain PE4This domain contains the Processing Element 4 of the SCE. */ ++#define SYS_GPE_SDCLR_PE4 0x00100000 ++/* No-Operation ++#define SYS_GPE_SDCLR_PE4_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_PE4_CLR 0x00100000 ++/** Clear Sleep Selection PE3 ++ Clears the selection bit for domain PE3This domain contains the Processing Element 3 of the SCE. */ ++#define SYS_GPE_SDCLR_PE3 0x00080000 ++/* No-Operation ++#define SYS_GPE_SDCLR_PE3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_PE3_CLR 0x00080000 ++/** Clear Sleep Selection PE2 ++ Clears the selection bit for domain PE2This domain contains the Processing Element 2 of the SCE. */ ++#define SYS_GPE_SDCLR_PE2 0x00040000 ++/* No-Operation ++#define SYS_GPE_SDCLR_PE2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_PE2_CLR 0x00040000 ++/** Clear Sleep Selection PE1 ++ Clears the selection bit for domain PE1This domain contains the Processing Element 1 of the SCE. */ ++#define SYS_GPE_SDCLR_PE1 0x00020000 ++/* No-Operation ++#define SYS_GPE_SDCLR_PE1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_PE1_CLR 0x00020000 ++/** Clear Sleep Selection PE0 ++ Clears the selection bit for domain PE0This domain contains the Processing Element 0 of the SCE. */ ++#define SYS_GPE_SDCLR_PE0 0x00010000 ++/* No-Operation ++#define SYS_GPE_SDCLR_PE0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_PE0_CLR 0x00010000 ++/** Clear Sleep Selection ARB ++ Clears the selection bit for domain ARBThis domain contains the Arbiter. */ ++#define SYS_GPE_SDCLR_ARB 0x00002000 ++/* No-Operation ++#define SYS_GPE_SDCLR_ARB_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_ARB_CLR 0x00002000 ++/** Clear Sleep Selection FSQM ++ Clears the selection bit for domain FSQMThis domain contains the FSQM. */ ++#define SYS_GPE_SDCLR_FSQM 0x00001000 ++/* No-Operation ++#define SYS_GPE_SDCLR_FSQM_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_FSQM_CLR 0x00001000 ++/** Clear Sleep Selection TMU ++ Clears the selection bit for domain TMUThis domain contains the TMU. */ ++#define SYS_GPE_SDCLR_TMU 0x00000800 ++/* No-Operation ++#define SYS_GPE_SDCLR_TMU_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_TMU_CLR 0x00000800 ++/** Clear Sleep Selection MRG ++ Clears the selection bit for domain MRGThis domain contains the Merger. */ ++#define SYS_GPE_SDCLR_MRG 0x00000400 ++/* No-Operation ++#define SYS_GPE_SDCLR_MRG_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_MRG_CLR 0x00000400 ++/** Clear Sleep Selection DISP ++ Clears the selection bit for domain DISPThis domain contains the Dispatcher. */ ++#define SYS_GPE_SDCLR_DISP 0x00000200 ++/* No-Operation ++#define SYS_GPE_SDCLR_DISP_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_DISP_CLR 0x00000200 ++/** Clear Sleep Selection IQM ++ Clears the selection bit for domain IQMThis domain contains the IQM. */ ++#define SYS_GPE_SDCLR_IQM 0x00000100 ++/* No-Operation ++#define SYS_GPE_SDCLR_IQM_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_IQM_CLR 0x00000100 ++/** Clear Sleep Selection CPUE ++ Clears the selection bit for domain CPUEThis domain contains all parts related to the CPU EGRESS interface. */ ++#define SYS_GPE_SDCLR_CPUE 0x00000080 ++/* No-Operation ++#define SYS_GPE_SDCLR_CPUE_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_CPUE_CLR 0x00000080 ++/** Clear Sleep Selection CPUI ++ Clears the selection bit for domain CPUIThis domain contains all parts related to the CPU INGRESS interface. */ ++#define SYS_GPE_SDCLR_CPUI 0x00000040 ++/* No-Operation ++#define SYS_GPE_SDCLR_CPUI_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_CPUI_CLR 0x00000040 ++/** Clear Sleep Selection GPONE ++ Clears the selection bit for domain GPONEThis domain contains all parts related to the GPON (GTC) EGRESS interface. */ ++#define SYS_GPE_SDCLR_GPONE 0x00000020 ++/* No-Operation ++#define SYS_GPE_SDCLR_GPONE_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_GPONE_CLR 0x00000020 ++/** Clear Sleep Selection GPONI ++ Clears the selection bit for domain GPONIThis domain contains all parts related to the GPON (GTC) INGRESS interface. */ ++#define SYS_GPE_SDCLR_GPONI 0x00000010 ++/* No-Operation ++#define SYS_GPE_SDCLR_GPONI_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_GPONI_CLR 0x00000010 ++/** Clear Sleep Selection LAN3 ++ Clears the selection bit for domain LAN3This domain contains all parts related to the LAN3 interface. */ ++#define SYS_GPE_SDCLR_LAN3 0x00000008 ++/* No-Operation ++#define SYS_GPE_SDCLR_LAN3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_LAN3_CLR 0x00000008 ++/** Clear Sleep Selection LAN2 ++ Clears the selection bit for domain LAN2This domain contains all parts related to the LAN2 interface. */ ++#define SYS_GPE_SDCLR_LAN2 0x00000004 ++/* No-Operation ++#define SYS_GPE_SDCLR_LAN2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_LAN2_CLR 0x00000004 ++/** Clear Sleep Selection LAN1 ++ Clears the selection bit for domain LAN1This domain contains all parts related to the LAN1 interface. */ ++#define SYS_GPE_SDCLR_LAN1 0x00000002 ++/* No-Operation ++#define SYS_GPE_SDCLR_LAN1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_LAN1_CLR 0x00000002 ++/** Clear Sleep Selection LAN0 ++ Clears the selection bit for domain LAN0This domain contains all parts related to the LAN0 interface. */ ++#define SYS_GPE_SDCLR_LAN0 0x00000001 ++/* No-Operation ++#define SYS_GPE_SDCLR_LAN0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_LAN0_CLR 0x00000001 ++ ++/* Fields of "IRNCS Capture Register" */ ++/** FSQM wakeup request ++ The FSQM submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_FSQMWR 0x80000000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_FSQMWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_FSQMWR_INTACK 0x80000000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_FSQMWR_INTOCC 0x80000000 ++/** GPONT wakeup request ++ The TCONT Request FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONTWR 0x20000000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_GPONTWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONTWR_INTACK 0x20000000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_GPONTWR_INTOCC 0x20000000 ++/** GPONE wakeup request ++ The EGRESS FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONEWR 0x10000000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_GPONEWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONEWR_INTACK 0x10000000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_GPONEWR_INTOCC 0x10000000 ++/** LAN3E wakeup request ++ The EGRESS FIFO of port LAN3 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN3EWR 0x08000000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN3EWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN3EWR_INTACK 0x08000000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN3EWR_INTOCC 0x08000000 ++/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request. ++ This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN2EWR 0x04000000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN2EWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN2EWR_INTACK 0x04000000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN2EWR_INTOCC 0x04000000 ++/** LAN1E wakeup request ++ The EGRESS FIFO of port LAN1 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN1EWR 0x02000000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN1EWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN1EWR_INTACK 0x02000000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN1EWR_INTOCC 0x02000000 ++/** LAN0E wakeup request ++ The EGRESS FIFO of port LAN0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN0EWR 0x01000000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN0EWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN0EWR_INTACK 0x01000000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN0EWR_INTOCC 0x01000000 ++/** GPONI wakeup request ++ The INGRESS FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONIWR 0x00100000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_GPONIWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONIWR_INTACK 0x00100000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_GPONIWR_INTOCC 0x00100000 ++/** LAN3I wakeup request ++ The INGRESS FIFO of port LAN3 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN3IWR 0x00080000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN3IWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN3IWR_INTACK 0x00080000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN3IWR_INTOCC 0x00080000 ++/** LAN2I wakeup request ++ The INGRESS FIFO of port LAN2 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN2IWR 0x00040000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN2IWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN2IWR_INTACK 0x00040000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN2IWR_INTOCC 0x00040000 ++/** LAN1I wakeup request ++ The INGRESS FIFO of port LAN1 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN1IWR 0x00020000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN1IWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN1IWR_INTACK 0x00020000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN1IWR_INTOCC 0x00020000 ++/** LAN0I wakeup request ++ The INGRESS FIFO of port LAN0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN0IWR 0x00010000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN0IWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN0IWR_INTACK 0x00010000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN0IWR_INTOCC 0x00010000 ++/** FSQM sleep request ++ The FSQM submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_FSQMSR 0x00008000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_FSQMSR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_FSQMSR_INTACK 0x00008000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_FSQMSR_INTOCC 0x00008000 ++/** GPONT sleep request ++ The TCONT Request FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONTSR 0x00002000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_GPONTSR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONTSR_INTACK 0x00002000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_GPONTSR_INTOCC 0x00002000 ++/** GPONE sleep request ++ The EGRESS FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONESR 0x00001000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_GPONESR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONESR_INTACK 0x00001000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_GPONESR_INTOCC 0x00001000 ++/** LAN3E sleep request ++ The EGRESS FIFO of port LAN3 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN3ESR 0x00000800 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN3ESR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN3ESR_INTACK 0x00000800 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN3ESR_INTOCC 0x00000800 ++/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request. ++ This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN2ESR 0x00000400 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN2ESR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN2ESR_INTACK 0x00000400 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN2ESR_INTOCC 0x00000400 ++/** LAN1E sleep request ++ The EGRESS FIFO of port LAN1 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN1ESR 0x00000200 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN1ESR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN1ESR_INTACK 0x00000200 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN1ESR_INTOCC 0x00000200 ++/** LAN0E sleep request ++ The EGRESS FIFO of port LAN0 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN0ESR 0x00000100 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN0ESR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN0ESR_INTACK 0x00000100 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN0ESR_INTOCC 0x00000100 ++/** GPONI sleep request ++ The INGRESS FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONISR 0x00000010 ++/* Nothing ++#define SYS_GPE_IRNCSCR_GPONISR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONISR_INTACK 0x00000010 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_GPONISR_INTOCC 0x00000010 ++/** LAN3I sleep request ++ The INGRESS FIFO of port LAN3 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN3ISR 0x00000008 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN3ISR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN3ISR_INTACK 0x00000008 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN3ISR_INTOCC 0x00000008 ++/** LAN2I sleep request ++ The INGRESS FIFO of port LAN2 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN2ISR 0x00000004 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN2ISR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN2ISR_INTACK 0x00000004 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN2ISR_INTOCC 0x00000004 ++/** LAN1I sleep request ++ The INGRESS FIFO of port LAN1 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN1ISR 0x00000002 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN1ISR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN1ISR_INTACK 0x00000002 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN1ISR_INTOCC 0x00000002 ++/** LAN0I sleep request ++ The INGRESS FIFO of port LAN0 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN0ISR 0x00000001 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN0ISR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN0ISR_INTACK 0x00000001 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN0ISR_INTOCC 0x00000001 ++ ++/* Fields of "IRNCS Interrupt Control Register" */ ++/** FSQM wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_FSQMWR 0x80000000 ++/** GPONT wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_GPONTWR 0x20000000 ++/** GPONE wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_GPONEWR 0x10000000 ++/** LAN3E wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN3EWR 0x08000000 ++/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request. ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN2EWR 0x04000000 ++/** LAN1E wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN1EWR 0x02000000 ++/** LAN0E wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN0EWR 0x01000000 ++/** GPONI wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_GPONIWR 0x00100000 ++/** LAN3I wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN3IWR 0x00080000 ++/** LAN2I wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN2IWR 0x00040000 ++/** LAN1I wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN1IWR 0x00020000 ++/** LAN0I wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN0IWR 0x00010000 ++/** FSQM sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_FSQMSR 0x00008000 ++/** GPONT sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_GPONTSR 0x00002000 ++/** GPONE sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_GPONESR 0x00001000 ++/** LAN3E sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN3ESR 0x00000800 ++/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request. ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN2ESR 0x00000400 ++/** LAN1E sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN1ESR 0x00000200 ++/** LAN0E sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN0ESR 0x00000100 ++/** GPONI sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_GPONISR 0x00000010 ++/** LAN3I sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN3ISR 0x00000008 ++/** LAN2I sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN2ISR 0x00000004 ++/** LAN1I sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN1ISR 0x00000002 ++/** LAN0I sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN0ISR 0x00000001 ++ ++/* Fields of "IRNCS Interrupt Enable Register" */ ++/** FSQM wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_FSQMWR 0x80000000 ++/* Disable ++#define SYS_GPE_IRNCSEN_FSQMWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_FSQMWR_EN 0x80000000 ++/** GPONT wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_GPONTWR 0x20000000 ++/* Disable ++#define SYS_GPE_IRNCSEN_GPONTWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_GPONTWR_EN 0x20000000 ++/** GPONE wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_GPONEWR 0x10000000 ++/* Disable ++#define SYS_GPE_IRNCSEN_GPONEWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_GPONEWR_EN 0x10000000 ++/** LAN3E wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN3EWR 0x08000000 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN3EWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN3EWR_EN 0x08000000 ++/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request. ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN2EWR 0x04000000 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN2EWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN2EWR_EN 0x04000000 ++/** LAN1E wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN1EWR 0x02000000 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN1EWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN1EWR_EN 0x02000000 ++/** LAN0E wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN0EWR 0x01000000 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN0EWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN0EWR_EN 0x01000000 ++/** GPONI wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_GPONIWR 0x00100000 ++/* Disable ++#define SYS_GPE_IRNCSEN_GPONIWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_GPONIWR_EN 0x00100000 ++/** LAN3I wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN3IWR 0x00080000 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN3IWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN3IWR_EN 0x00080000 ++/** LAN2I wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN2IWR 0x00040000 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN2IWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN2IWR_EN 0x00040000 ++/** LAN1I wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN1IWR 0x00020000 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN1IWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN1IWR_EN 0x00020000 ++/** LAN0I wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN0IWR 0x00010000 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN0IWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN0IWR_EN 0x00010000 ++/** FSQM sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_FSQMSR 0x00008000 ++/* Disable ++#define SYS_GPE_IRNCSEN_FSQMSR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_FSQMSR_EN 0x00008000 ++/** GPONT sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_GPONTSR 0x00002000 ++/* Disable ++#define SYS_GPE_IRNCSEN_GPONTSR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_GPONTSR_EN 0x00002000 ++/** GPONE sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_GPONESR 0x00001000 ++/* Disable ++#define SYS_GPE_IRNCSEN_GPONESR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_GPONESR_EN 0x00001000 ++/** LAN3E sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN3ESR 0x00000800 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN3ESR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN3ESR_EN 0x00000800 ++/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request. ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN2ESR 0x00000400 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN2ESR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN2ESR_EN 0x00000400 ++/** LAN1E sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN1ESR 0x00000200 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN1ESR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN1ESR_EN 0x00000200 ++/** LAN0E sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN0ESR 0x00000100 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN0ESR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN0ESR_EN 0x00000100 ++/** GPONI sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_GPONISR 0x00000010 ++/* Disable ++#define SYS_GPE_IRNCSEN_GPONISR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_GPONISR_EN 0x00000010 ++/** LAN3I sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN3ISR 0x00000008 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN3ISR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN3ISR_EN 0x00000008 ++/** LAN2I sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN2ISR 0x00000004 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN2ISR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN2ISR_EN 0x00000004 ++/** LAN1I sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN1ISR 0x00000002 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN1ISR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN1ISR_EN 0x00000002 ++/** LAN0I sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN0ISR 0x00000001 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN0ISR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN0ISR_EN 0x00000001 ++ ++/*! @} */ /* SYS_GPE_REGISTER */ ++ ++#endif /* _sys_gpe_reg_h */ +diff --git a/arch/mips/include/asm/mach-lantiq/falcon/sysctrl.h b/arch/mips/include/asm/mach-lantiq/falcon/sysctrl.h +new file mode 100644 +index 0000000..8fa3ea0 +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/sysctrl.h +@@ -0,0 +1,60 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland ++ */ ++ ++#ifndef __FALCON_SYSCTRL_H ++#define __FALCON_SYSCTRL_H ++ ++#include ++ ++static inline void sys1_hw_activate(u32 mask) ++{ ltq_sysctl_activate(SYSCTL_SYS1, mask); } ++static inline void sys1_hw_deactivate(u32 mask) ++{ ltq_sysctl_deactivate(SYSCTL_SYS1, mask); } ++static inline void sys1_hw_clk_enable(u32 mask) ++{ ltq_sysctl_clken(SYSCTL_SYS1, mask); } ++static inline void sys1_hw_clk_disable(u32 mask) ++{ ltq_sysctl_clkdis(SYSCTL_SYS1, mask); } ++static inline void sys1_hw_activate_or_reboot(u32 mask) ++{ ltq_sysctl_reboot(SYSCTL_SYS1, mask); } ++ ++static inline void sys_eth_hw_activate(u32 mask) ++{ ltq_sysctl_activate(SYSCTL_SYSETH, mask); } ++static inline void sys_eth_hw_deactivate(u32 mask) ++{ ltq_sysctl_deactivate(SYSCTL_SYSETH, mask); } ++static inline void sys_eth_hw_clk_enable(u32 mask) ++{ ltq_sysctl_clken(SYSCTL_SYSETH, mask); } ++static inline void sys_eth_hw_clk_disable(u32 mask) ++{ ltq_sysctl_clkdis(SYSCTL_SYSETH, mask); } ++static inline void sys_eth_hw_activate_or_reboot(u32 mask) ++{ ltq_sysctl_reboot(SYSCTL_SYSETH, mask); } ++ ++static inline void sys_gpe_hw_activate(u32 mask) ++{ ltq_sysctl_activate(SYSCTL_SYSGPE, mask); } ++static inline void sys_gpe_hw_deactivate(u32 mask) ++{ ltq_sysctl_deactivate(SYSCTL_SYSGPE, mask); } ++static inline void sys_gpe_hw_clk_enable(u32 mask) ++{ ltq_sysctl_clken(SYSCTL_SYSGPE, mask); } ++static inline void sys_gpe_hw_clk_disable(u32 mask) ++{ ltq_sysctl_clkdis(SYSCTL_SYSGPE, mask); } ++static inline void sys_gpe_hw_activate_or_reboot(u32 mask) ++{ ltq_sysctl_reboot(SYSCTL_SYSGPE, mask); } ++static inline int sys_gpe_hw_is_activated(u32 mask) ++{ return 1; } ++ ++#endif /* __FALCON_SYSCTRL_H */ +diff --git a/include/linux/atm.h b/include/linux/atm.h +index 2c63d27..47396c4 100644 +--- a/include/linux/atm.h ++++ b/include/linux/atm.h +@@ -130,6 +130,11 @@ + #define ATM_ABR 4 + #define ATM_ANYCLASS 5 /* compatible with everything */ + ++#define ATM_VBR_NRT ATM_VBR ++#define ATM_VBR_RT 6 ++#define ATM_UBR_PLUS 7 ++#define ATM_GFR 8 ++ + #define ATM_MAX_PCR -1 /* maximum available PCR */ + + struct atm_trafprm { +diff --git a/include/linux/pci.h b/include/linux/pci.h +index a16b1df..135fd2d 100644 +--- a/include/linux/pci.h ++++ b/include/linux/pci.h +@@ -964,6 +964,7 @@ int pci_cfg_space_size_ext(struct pci_dev *dev); + int pci_cfg_space_size(struct pci_dev *dev); + unsigned char pci_bus_max_busnr(struct pci_bus *bus); + void pci_setup_bridge(struct pci_bus *bus); ++int pci_find_preexist_bus_nr(const struct pci_bus *from); + + #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) + #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) +diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h +index 31d77af..146694b 100644 +--- a/include/linux/pci_ids.h ++++ b/include/linux/pci_ids.h +@@ -2904,3 +2904,11 @@ + #define PCI_DEVICE_ID_XEN_PLATFORM 0x0001 + + #define PCI_VENDOR_ID_OCZ 0x1b85 ++ ++#define PCI_VENDOR_ID_INFINEON 0x15D1 ++#define PCI_DEVICE_ID_INFINEON_DANUBE 0x000F ++#define PCI_DEVICE_ID_INFINEON_PCIE 0x0011 ++ ++#define PCI_VENDOR_ID_LANTIQ 0x1BEF ++#define PCI_DEVICE_ID_LANTIQ_PCIE 0x0011 ++ +diff --git a/include/net/ifx_ppa_api.h b/include/net/ifx_ppa_api.h +new file mode 100644 +index 0000000..ee22832 +--- /dev/null ++++ b/include/net/ifx_ppa_api.h +@@ -0,0 +1,2606 @@ ++#ifndef __IFX_PPA_API_H__20081031_1913__ ++#define __IFX_PPA_API_H__20081031_1913__ ++ ++ ++/******************************************************************************* ++** ++** FILE NAME : ifx_ppa_api.h ++** PROJECT : PPA ++** MODULES : PPA API (Routing/Bridging Acceleration APIs) ++** ++** DATE : 31 OCT 2008 ++** AUTHOR : Xu Liang ++** DESCRIPTION : PPA Protocol Stack Hook API Header File ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3; 85579 Neubiberg, Germany ++** ++** For licensing information, see the file 'LICENSE' in the root folder of ++** this software module. ++** ++** HISTORY ++** $Date $Author $Comment ++** 31 OCT 2008 Xu Liang Initiate Version ++*******************************************************************************/ ++/*! \file ifx_ppa_api.h ++ \brief This file contains es. ++ provide PPA API. ++*/ ++ ++/** \defgroup PPA_API PPA Kernel Hook and Userspace Function API ++ \brief PPA is a loadable network module. Hence, it exports its API though function pointer hooks. Callers need to check that hooks are non-NULL before invoking them. The hooks are initialized when the PPA is initialized. Certain API which are control / configuration related are also exposed to user space applications through the ioctl API. The PPA Kernel and Userspace API are discussed in the following sections: ++*/ ++/* @{*/ ++/** \defgroup PPA_IOCTL PPA Userspace API ++ \brief The subset of PPA API which is exposed to userspace for control and configuration of the PPA is invoked through ++ an ioctls()/system call interface as described in this section. ++ The API is defined in the following two source files: ++ - ifx_ppa_api.h: Header file for PPA API ++ - ifx_ppa_api.c: C Implementation file for PPA API ++*/ ++ ++/** \defgroup PPA_HOOK_API PPA Hook API ++ \brief PPA is a loadable network module. Hence, it exports its API though function pointer hooks. Callers need to check that hooks are non-NULL before invoking them. The hooks are initialized when the PPA is initialized. ++ - ifx_ppa_hook.h: Header file for PPA API ++ - ifx_ppa_hook.c: C Implementation file for PPA API ++*/ ++ ++/** \defgroup PPA_PWM_API PPA Power Management API ++ \brief PPA Power Management API provide PPA Power Management and IOCTL API ++ The API is defined in the following two source files ++ - ifx_ppa_api_pwm.h: Header file for PPA API ++ - ifx_ppa_api_pwm.c: C Implementation file for PPA Power management API ++ - ifx_ppa_api_pwm_logic.c: C impelementation file for Powr management Logic and interface with PPE driver ++*/ ++ /** \defgroup PPA_API_DIRECTPATH PPA Direct Path API ++ \brief This section describes the PPA DirectPath API that allows a driver on a CPU to bypass the protocol stack and send and receive packets directly from the PPA acceleration function. For a 2-CPU system, this API is used to communicate with devices whose drivers are running on the 2nd CPU (or Core 1) - usually Core 1 is not running any protocol stack, and all protocol stack intelligence is on Core 0. This API is not yet implemented for PPE D4 or A4 firmware. It is provided as advance information on the DirectPath interfaces.The PPA DirectPath aims to accelerate packet processing by reducing CPU load when the protocol stack processes the packet. It allows a CPU-bound driver to directly talk to the PPA and to the PPE engine bypassing the stack path and providing a short-cut. ++ - ifx_ppa_api_directpath.h: Header file for PPA API ++ - ifx_ppa_api_directpath.c: C Implementation file for PPA API ++*/ ++ ++/** \defgroup PPA_ADAPTATION_LAYER PPA Stack Adaptation API ++ \brief PPA module aims for OS and Protocol stack independence, and the ++ core PPA logic does not access any OS or Protocol stack implementation ++ specific structures directly. The PPA Protocol Stack Adaptation layer ++ provides API that allows for straight-forward and structured OS / protocol ++ stack porting of the PPA just by porting the Adaptation Layer (AL) API. ++ The AL API is defined in the following two source files ++ - ifx_ppa_stack_al.h: Header file for AL layer ++ - ifx_ppa_stack_al.c: C Implementation file for AL API ++*/ ++/* @}*/ ++ ++ ++ ++#include ++#include ++#ifdef __KERNEL__ ++ #include ++#endif ++ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++/*! ++ \brief PPA_MAX_IFS_NUM ++*/ ++#define PPA_MAX_IFS_NUM 10 /*!< Maximum interface number supported */ ++ ++ ++ ++/*! ++ \brief PPA_MAX_MC_IFS_NUM ++*/ ++#define PPA_MAX_MC_IFS_NUM 8 /*!< Maximum number of Multicast supporting interfaces */ ++ ++/*! ++ \brief PPA_MAX_VLAN_FILTER ++*/ ++#define PPA_MAX_VLAN_FILTER 32 /*!< Maximum number of VLAN fitler */ ++ ++ ++/*! ++ \brief PPA_IOC_MAGIC ++*/ ++#define PPA_IOC_MAGIC ((uint32_t)'p') /*!< Magic number to differentiate PPA ioctl commands */ ++ ++/*! ++ \brief IFX_SUCCESS ++*/ ++#define IFX_SUCCESS 0 /*!< Operation was successful. */ ++ ++/*! ++ \brief IFX_FAILURE ++*/ ++#define IFX_FAILURE -1 /*!< Operation failed */ ++ ++/*! ++ \brief IFX_EPERM ++*/ ++#define IFX_EPERM -2 /*!< not permitted */ ++ ++/*! ++ \brief IFX_EIO ++*/ ++#define IFX_EIO -5 /*!< I/O/Hardware/Firmware error */ ++ ++/*! ++ \brief IFX_EAGAIN ++*/ ++#define IFX_EAGAIN -11 /*!< try again later */ ++ ++/*! ++ \brief IFX_ENOMEM ++*/ ++#define IFX_ENOMEM -12 /*!< out of memory */ ++ ++/*! ++ \brief IFX_EACCESS ++*/ ++#define IFX_EACCESS IFX_EPERM ++ ++/*! ++ \brief IFX_EFAULT ++*/ ++#define IFX_EFAULT -14 /*!< bad address */ ++ ++/*! ++ \brief IFX_EBUSY ++*/ ++#define IFX_EBUSY -16 /*!< busy */ ++ ++/*! ++ \brief IFX_EINVAL ++*/ ++#define IFX_EINVAL -22 /*!< invalid argument */ ++ ++/*! ++ \brief IFX_ENOTAVAIL ++*/ ++#define IFX_ENOTAVAIL -97 ++ ++/*! ++ \brief IFX_ENOTPOSSIBLE ++*/ ++#define IFX_ENOTPOSSIBLE -98 ++ ++/*! ++ \brief IFX_ENOTIMPL ++*/ ++#define IFX_ENOTIMPL -99 /*!< not implemented */ ++ ++/*! ++ \brief IFX_ENABLED ++*/ ++#define IFX_ENABLED 1 /*!< Status enabled / Device was enabled */ ++ ++/*! ++ \brief IFX_DISABLED ++*/ ++#define IFX_DISABLED 0 /*!< Status disabled / Device was disabled. */ ++ ++/* ++ * flags ++ */ ++ ++/*! ++ \brief PPA_F_BEFORE_NAT_TRANSFORM ++ \note PPA Routing Session add hook is called before NAT transform has taken place. \n ++ In Linux OS, this NSFORM corresponds to the netfilter PREROUTING hook ++*/ ++#define PPA_F_BEFORE_NAT_TRANSFORM 0x00000001 ++ ++/*! ++ \brief PPA_F_ACCEL_MODE ++ \note notify PPA to enable or disable acceleration for one routing session. It is only for Hook/ioctl, not for PPE FW usage ++*/ ++#define PPA_F_ACCEL_MODE 0x00000002 ++ ++/*! ++ \brief PPA_F_SESSION_ORG_DIR ++ \note Packet in original direction of session i.e. the direction in which the session was established ++*/ ++#define PPA_F_SESSION_ORG_DIR 0x00000010 ++ ++/*! ++ \brief PPA_F_SESSION_REPLY_DIR ++ \note Packet in reply direction of session i.e. opposite to the direction in which session was initiated. ++*/ ++#define PPA_F_SESSION_REPLY_DIR 0x00000020 ++ ++/*! ++ \brief PPA_F_SESSION_BIDIRECTIONAL ++ \note For PPA Session add, add a bidirectional session, else unidirection session is assumed. ++*/ ++#define PPA_F_SESSION_BIDIRECTIONAL (PPA_F_SESSION_ORG_DIR | PPA_F_SESSION_REPLY_DIR) ++ ++/*! ++ \brief PPA_F_BRIDGED_SESSION ++ \note Denotes that the PPA session is bridged ++*/ ++#define PPA_F_BRIDGED_SESSION 0x00000100 ++ ++/*! ++ \brief PPA_F_SESSION_NEW_DSCP ++ \note Denotes that the PPA session has DSCP remarking enabled ++*/ ++#define PPA_F_SESSION_NEW_DSCP 0x00001000 ++ ++/*! ++ \brief PPA_F_SESSION_VLAN ++ \note Denotes that the PPA session has VLAN tagging enabled. ++*/ ++#define PPA_F_SESSION_VLAN 0x00002000 ++ ++/*! ++ \brief PPA_F_MTU ++ \note Denotes that the PPA session has a MTU limit specified ++*/ ++#define PPA_F_MTU 0x00004000 ++ ++/*! ++ \brief PPA_F_SESSION_OUT_VLAN ++ \note Denotes that the PPA session has Outer VLAN tagging enable ++*/ ++#define PPA_F_SESSION_OUT_VLAN 0x00008000 ++ ++/*! ++ \brief PPA_F_BRIDGE_LOCAL ++ \note Denotes that the PPA bridge session is for a flow terminated at the CPE (i.e. not bridged out). Such an entry will not be accelerated ++*/ ++#define PPA_F_BRIDGE_LOCAL 0x00010000 ++ ++/*! ++ \brief PPA_F_LAN_IF ++ \note Indicates that the interface is a LAN interface ++*/ ++#define PPA_F_LAN_IF 0x01000000 ++ ++/*! ++ \brief PPA_F_STATIC_ENTRY ++ \note Indicates that it is a static entry ++*/ ++#define PPA_F_STATIC_ENTRY 0x20000000 ++ ++/*! ++ \brief PPA_F_DROP_PACKET ++ \note Denotes that the PPA session has a drop action specified. In other words, this acts as a fast path \n ++ packet filter drop action ++*/ ++#define PPA_F_DROP_PACKET 0x40000000 ++ ++/*! ++ \brief PPA_F_BRIDGE_ACCEL_MODE ++ \note Flag denoting that the PPA should accelerate bridging sessions. Reserved currently ++*/ ++#define PPA_F_BRIDGE_ACCEL_MODE 0x80000000 ++ ++/* ++ * interface flags ++ */ ++ ++/*! ++ \brief IFX_PPA_SESSION_NOT_ADDED ++*/ ++#define IFX_PPA_SESSION_NOT_ADDED -1 /*!< PPA Session Add failed. This can happen either because the Session is not yet ready for addition or \n ++ that PPA cannot accelerate the session because the packet is looped back */ ++ ++/*! ++ \brief IFX_PPA_SESSION_ADDED ++*/ ++#define IFX_PPA_SESSION_ADDED 0 /*!< Indicates PPA was able to successfully add the session */ ++ ++/*! ++ \brief IFX_PPA_SESSION_EXISTS ++*/ ++#define IFX_PPA_SESSION_EXISTS 1 /*!< Indicates PPA already has the session added. This is also a success indication */ ++ ++ ++/* ++ * ifx_ppa_inactivity_status return value ++ */ ++/*! ++ \brief IFX_PPA_HIT ++ \note PPA Session is active i.e. was hit with packets within the configured inactivity time inter ++*/ ++ #define IFX_PPA_HIT 0 ++ ++/*! ++ \brief IFX_PPA_TIMEOUT ++ \note PPA Session is inactive and hence has timed out ++*/ ++#define IFX_PPA_TIMEOUT 1 ++ ++/*! ++ \brief PPA_F_VLAN_FILTER_IFNAME ++*/ ++#define PPA_F_VLAN_FILTER_IFNAME 0 /*!< Port based VLAN */ ++ ++/*! ++ \brief PPA_F_VLAN_FILTER_IP_SRC ++*/ ++#define PPA_F_VLAN_FILTER_IP_SRC 1 /*!< SRC IP based VLAN */ ++ ++/*! ++ \brief PPA_F_VLAN_FILTER_ETH_PROTO ++*/ ++#define PPA_F_VLAN_FILTER_ETH_PROTO 2 /*!< Ethernet Type based VLAN */ ++ ++/*! ++ \brief PPA_F_VLAN_FILTER_VLAN_TAG ++*/ ++#define PPA_F_VLAN_FILTER_VLAN_TAG 3 /*!< Vlan tag based VLAN */ ++ ++/*! ++ \brief PPA_INVALID_QID ++*/ ++#define PPA_INVALID_QID 0xFFFF /*!< Invalid VLAN ID. Note, it is used only in IOCTL */ ++ ++/*! ++ \brief PPA_VLAN_TAG_MASK ++*/ ++#define PPA_VLAN_TAG_MASK 0xFFFF1FFF /*!< VLAN MASK to remove VLAN priority*/ ++ ++/*! ++ \brief MAX_HOOK_NAME_LEN ++*/ ++#define MAX_HOOK_NAME_LEN 71 /*!< maximum hook name length */ ++ ++ ++/*! ++ \brief PPA_PORT_MODE_ETH ++*/ ++#define PPA_PORT_MODE_ETH 1 /*!< Ethernet Port */ ++/*! ++ \brief PPA_PORT_MODE_DSL ++*/ ++#define PPA_PORT_MODE_DSL 2 /*!< DSL Port */ ++ ++/*! ++ \brief PPA_PORT_MODE_EXT ++*/ ++#define PPA_PORT_MODE_EXT 3 /*!< Extension Port, like USB/WLAN */ ++ ++/*! ++ \brief PPA_PORT_MODE_CPU ++*/ ++#define PPA_PORT_MODE_CPU 4 /*!< CPU */ ++ ++ ++ ++#ifdef NO_DOXY ++#define VLAN_ID_SPLIT(full_id, pri, cfi, vid) pri=( (full_id) >> 13 ) & 7; cfi=( (full_id) >>12) & 1; vid= (full_id) & 0xFFF ++#define VLAN_ID_CONBINE(full_id, pri, cfi, vid) full_id =( ( (uint16_t)(pri) & 7) << 13 ) | ( ( (uint16_t)( cfi) & 1) << 12 ) | ((uint16_t) (vid) & 0xFFF ) ++ ++ ++/* ++ * internal flag ++ */ ++ ++#define SESSION_INTERNAL_FLAG_BASE 0 ++#define SESSION_IS_REPLY 0x00000001 ++#define SESSION_BRIDGING_VCI_CHECK 0x00000002 ++#define SESSION_IS_TCP 0x00000004 ++#define SESSION_BYTE_STAMPING 0x00000008 //for PPA session management purse ++#define SESSION_ADDED_IN_HW 0x00000010 ++#define SESSION_NON_ACCE_MASK ~SESSION_ADDED_IN_HW //for ioctl only ++#define SESSION_CAN_NOT_ACCEL 0x00000020 // later may need to change the naming, so far it also used for sesson management ++#define SESSION_STATIC 0x00000040 ++#define SESSION_DROP 0x00000080 ++#define SESSION_VALID_NAT_IP 0x00000100 ++#define SESSION_VALID_NAT_PORT 0x00000200 ++#define SESSION_VALID_NAT_SNAT 0x00000400 // src IP is replaced, otherwise dest IP is replaced ++#define SESSION_NOT_ACCELABLE 0x00000800 //Session cannot be accelerated at all ++#define SESSION_VALID_VLAN_INS 0x00001000 ++#define SESSION_VALID_VLAN_RM 0x00002000 ++#define SESSION_VALID_OUT_VLAN_INS 0x00004000 ++#define SESSION_VALID_OUT_VLAN_RM 0x00008000 ++#define SESSION_VALID_PPPOE 0x00010000 ++#define SESSION_VALID_NEW_SRC_MAC 0x00020000 ++#define SESSION_VALID_SRC_MAC SESSION_VALID_NEW_SRC_MAC ++#define SESSION_VALID_MTU 0x00040000 ++#define SESSION_VALID_NEW_DSCP 0x00080000 ++#define SESSION_VALID_DSLWAN_QID 0x00100000 ++#define SESSION_TX_ITF_IPOA 0x00200000 ++#define SESSION_TX_ITF_PPPOA 0x00400000 ++#define SESSION_TX_ITF_IPOA_PPPOA_MASK (SESSION_TX_ITF_IPOA | SESSION_TX_ITF_PPPOA) ++#define SESSION_SRC_MAC_DROP_EN 0x01000000 ++#define SESSION_TUNNEL_6RD 0x02000000 ++#define SESSION_TUNNEL_DSLITE 0x04000000 ++#define SESSION_LAN_ENTRY 0x10000000 ++#define SESSION_WAN_ENTRY 0x20000000 ++#define SESSION_IS_IPV6 0x40000000 ++#endif ++ ++/* ++ * #################################### ++ * Data Type ++ * #################################### ++ */ ++ ++/* -------------------------------------------------------------------------- */ ++/* Structure and Enumeration Type Defintions */ ++/* -------------------------------------------------------------------------- */ ++ ++/** \addtogroup PPA_HOOK_API */ ++/*@{*/ ++ ++/*! ++ \brief This is the data structure for PPA Interface Info specification. ++*/ ++typedef struct { ++ PPA_IFNAME *ifname; /*!< Name of the stack interface */ ++ uint32_t if_flags; /*!< Flags for Interface. Valid values are below: PPA_F_LAN_IF and PPA_F_WAN_IF */ ++ uint32_t port; /*!< physical port id for this Interface. Valid values are below: 0 ~ */ ++} PPA_IFINFO; ++ ++/*! ++ \brief This is the data structure for PPA Packet header verification checks. ++*/ ++typedef struct ppa_verify_checks { ++ uint32_t f_ip_verify :1; /*!< Enable/Disable IP verification checks. Valid values are IFX_ENABLED or IFX_DISABLED */ ++ uint32_t f_tcp_udp_verify :1; /*!< Enable/Disable TCP/UDP verification checks. Valid values are IFX_ENABLED or IFX_DISABLED */ ++ uint32_t f_tcp_udp_err_drop :1; /*!< Enable/Disable drop packet if TCP/UDP checksum is wrong. \n ++ If packet is not dropped, then it is forwarded to the control CPU. \n ++ Valid values are IFX_ENABLED or IFX_DISABLED */ ++ uint32_t f_drop_on_no_hit :1; /*!< Drop unicast packets on no hit, forward to MIPS/Control CPU otherwise (default). Valid values are IFX_ENABLED or IFX_DISABLED */ ++ uint32_t f_mc_drop_on_no_hit :1; /*!< Drop multicast on no hit, forward to MIPS/Control CPU otherwise (default). Valid values are IFX_ENABLED or IFX_DISABLED */ ++} PPA_VERIFY_CHECKS; ++ ++/*! ++ \brief This is the data structure for PPA Initialization kernel hook function ++*/ ++typedef struct { ++ PPA_VERIFY_CHECKS lan_rx_checks; /*!< LAN Ingress packet checks */ ++ PPA_VERIFY_CHECKS wan_rx_checks; /*!< WAN Ingress packet checks */ ++ uint32_t num_lanifs; /*!< Number of LAN side interfaces */ ++ PPA_IFINFO *p_lanifs; /*!< Pointer to array of LAN Interfaces. */ ++ uint32_t num_wanifs; /*!< Number of WAN side interfaces */ ++ PPA_IFINFO *p_wanifs; /*!< Pointer to array of WAN Interfaces. */ ++ uint32_t max_lan_source_entries; /*!< Maximum Number of session entries with LAN source */ ++ uint32_t max_wan_source_entries; /*!< Maximum Number of session entries with WAN source */ ++ uint32_t max_mc_entries; /*!< Maximum Number of multicast sessions */ ++ uint32_t max_bridging_entries; /*!< Maximum Number of bridging entries */ ++ uint32_t add_requires_min_hits; /*!< Minimum number of calls to ppa_add_session() before session would be added in h/w - calls from the same hook position in stack. Currently, set to 1 */ ++} PPA_INIT_INFO; ++ ++/*! ++ \brief This is the data structure for additional session related information for the PPA. It specifies on a per session basis ++ attributes like VLAN tagging, DSCP remarking etc. This structure depends on the PPE acceleration firmware ++ capabilities. New versions of PPA will only support the capabilities as in PPE A4/D4 firmware, ++ The current PPA driver (for PPE A4/D4 firmware) supports 2-level of VLANs (or stacked VLANs). The outer VLAN is ++ the one used for separating LAN and WAN traffic on a switch (for Ethernet WAN). Inner VLAN tag is application ++ specific VLAN. In case, there is no outer VLAN tag required (for LAN/WAN separation on the switch), then this ++ field is not specified. ++*/ ++typedef struct { ++ uint32_t new_dscp :6; /*!< New DSCP code point value for the session.Valid values are 0-63. */ ++ uint32_t dscp_remark :1; /*!< DSCP remarking needs to be carried out for the session.Valid values are:IFX_ENABLED and IFX_DISABLED */ ++ uint32_t vlan_insert :1; /*!< If inner VLAN tag should be inserted into the frame at egress. Valid values are: IFX_ENABLED and IFX_DISABLED */ ++ uint32_t vlan_remove :1; /*!< If inner VLAN untagging should be performed on the received frame. Untagging, if enabled, is \n ++ carried out before any VLAN tag insert. Valid values are:IFX_ENABLED and IFX_DISABLED */ ++ uint32_t out_vlan_insert :1; /*!< If outer VLAN tag should be inserted into the frame at egress. Valid values are: IFX_ENABLED and IFX_DISABLED */ ++ uint32_t out_vlan_remove :1; /*!< If outer VLAN untagging should be performed on the received frame. Untagging, if enabled, is \n ++ carried out before any VLAN tag insert. Valid values are:IFX_ENABLED and IFX_DISABLED */ ++ uint16_t dslwan_qid_remark :1; /*!< if dslwan qid should be set. Valid values are: IFX_ENABLED and IFX_DISABLED */ ++ uint32_t reserved1 :4; /*!< reserved */ ++ uint32_t vlan_prio :3; /*!< 802.1p VLAN priority configuration. Valid values are 0-7. */ ++ uint32_t vlan_cfi :1; /*!< lways set to 1 for Ethernet frames */ ++ uint32_t vlan_id :12;/*!< VLAN Id to be used to tag the frame. Valid values are 0-4095. */ ++ uint16_t mtu; /*!< MTU of frames classified to this session */ ++ uint16_t dslwan_qid; /*!< dslwan_qid. Valid values are 0 ~ 16 */ ++ uint32_t session_flags; /*!< Session flags used to identify which fields in the PPA_SESSION_EXTRA structure are valid in \n ++ a call to the PPA Session Modify API. \n ++ Valid values are one or more of: \n ++ PPA_F_SESSION_NEW_DSCP \n ++ PPA_F_SESSION_VLAN \n ++ PPA_F_SESSION_OUT_VLAN \n ++ PPA_F_MTU \n ++ */ ++ uint32_t out_vlan_tag; /*!< VLAN tag value including VLAN Id */ ++ ++ ++ ++ uint16_t accel_enable:1; /*!< to enable/disable acceleartion for one specified routing session. It will be used only in PPA API level, not HAL and PPE FW level */ ++} PPA_SESSION_EXTRA; ++ ++/*! ++ \brief This is the data structure which specifies an interface and its TTL value as applicable for multicast routing. ++*/ ++typedef struct { ++ PPA_IFNAME *ifname; /*!< Pointer to interface name. */ ++ uint8_t ttl; /*!< Time to Live (TTL) value of interface which is used for multicast routing to decide if a packet can be routed onto that interface ++ Note, it is not used at present. ++ */ ++} IF_TTL_ENTRY; ++ ++/*! ++ \brief This is the data structure for basic IPV4/IPV6 address ++*/ ++typedef union { ++ uint32_t ip; /*!< ipv4 address */ ++ uint32_t ip6[4]; /*!< ipv6 address */ ++}IP_ADDR; ++ ++/*! ++ \brief This is the data structure for complex IPV4/IPV6 address ++*/ ++typedef struct { ++ uint32_t f_ipv6; /*!< flag to specify the ipv4 version: 0---IPV4, 1 -- IPV6 */ ++ IP_ADDR ip; /*!< multiple ip address format support */ ++} IP_ADDR_C; ++ ++ ++/*! ++ \brief This is the data structure for PPA Multicast Group membership. It specifies the interfaces which are members of ++ the specified IP Multicast Group address. Please see the discussion on outer and inner VLAN tags in the ++ section on PPA_SESSION_EXTRA data structure. ++*/ ++typedef struct { ++ IP_ADDR_C ip_mc_group; /*!< Multicast IP address group */ ++ int8_t num_ifs; /*!< Number of Interfaces which are member of this Multicast IP group address */ ++ IF_TTL_ENTRY array_mem_ifs[PPA_MAX_MC_IFS_NUM]; /*!< Array of interface elements of maximum PPA_MAX_MC_IFS_NUM elements. ++ Actual number of entries is specified by num_ifs */ ++ uint8_t if_mask; /*!< Mask of Interfaces corresponding to num_ifs interfaces specified in array_mem_ifs. For internaly use only. */ ++ PPA_IFNAME *src_ifname; /*!< the source interface of specified multicast IP address group */ ++ uint32_t vlan_insert :1; /*!< If inner VLAN tag should be inserted into the frame at egress. Valid values are: IFX_ENABLED and IFX_DISABLED */ ++ uint32_t vlan_remove :1; /*!< If inner VLAN untagging should be performed on the received frame. Untagging, if enabled, is ++ carried out before any VLAN tag insert. Valid values are:IFX_ENABLED and IFX_DISABLED */ ++ uint32_t out_vlan_insert :1; /*!< If outer VLAN tag should be inserted into the frame at egress. Valid values are: IFX_ENABLED and IFX_DISABLED */ ++ uint32_t out_vlan_remove :1; /*!< If outer VLAN untagging should be performed on the received frame. Untagging, if enabled, is ++ carried out before any VLAN tag insert. Valid values are:IFX_ENABLED and IFX_DISABLED */ ++ uint32_t dslwan_qid_remark:1; /*!< not use at present */ ++ uint32_t reserved1 :3; /*!< valid in A4/A5 */ ++ uint32_t vlan_prio :3; /*!< 802.1p VLAN priority configuration. Valid values are 0-7. */ ++ uint32_t vlan_cfi :1; /*!< Always set to 1 for Ethernet frames */ ++ uint32_t vlan_id :12; /*!< VLAN Id to be used to tag the frame. Valid values are 0-4095 */ ++ uint32_t out_vlan_tag; /*!< Outer VLAN tag value including VLAN Id. */ ++ uint32_t new_dscp_en :1; /*!< If new dscp value should be set. Valid values are:IFX_ENABLED and IFX_DISABLED */ ++ uint32_t res :15; /*!< reserved */ ++ uint32_t new_dscp :16; /*!< New DSCP code point value for the session.Valid values are 0-63. */ ++ uint16_t dslwan_qid; /*!< not use at present */ ++ ++ uint32_t bridging_flag; /*!< 0 - routing mode/igmp proxy, 1 - bridge mode/igmp snooping. */ ++ uint8_t mac[PPA_ETH_ALEN]; /*!< reserved for future */ ++ uint8_t SSM_flag; /*!< Set the flag if source specific forwarding is required default 0*/ ++ PPA_IPADDR source_ip; /*!< source ip address */ ++} PPA_MC_GROUP; ++ ++/*! ++ \brief This data structure is an abstraction for unicast and multicast routing sessions. ++ Pointer to any kind of PPA session ++*/ ++typedef void PPA_U_SESSION; ++ ++/*! ++ \brief This is the data structure for standard packet and byte statistics for an interface. ++*/ ++typedef struct { ++ uint32_t tx_pkts; /*!< Number of transmitted packets through the interface */ ++ uint32_t rx_pkts; /*!< Number of received packets through the interface */ ++ uint32_t tx_discard_pkts; /*!< Number of packets discarded while transmitting through the interface. */ ++ uint32_t tx_error_pkts; /*!< Number of transmit errors through the interface. */ ++ uint32_t rx_discard_pkts; /*!< Number of received packets through the interface that were discarded */ ++ uint32_t rx_error_pkts; /*!< Number of received errors through the interface. */ ++ uint32_t tx_bytes; /*!< Number of transmit bytes through the interface */ ++ uint32_t rx_bytes; /*!< Number of received bytes through the interface */ ++} PPA_IF_STATS; ++ ++/*! ++ \brief This is the data structure for PPA accelerated statistics for an interface. Depending on the platform and ++ acceleration capabilities, some of the statistics may not be available. ++*/ ++typedef struct { ++ uint32_t fast_routed_tcp_pkts; /*!< Fastpath routed TCP unicast packets Tx */ ++ uint32_t fast_routed_udp_pkts; /*!< Fastpath routed UDP unicast packets Tx */ ++ uint32_t fast_routed_udp_mcast_pkts; /*!< Fastpath routed UDP multicast packets Tx */ ++ uint32_t fast_drop_pkts; /*!< Fastpath ingress pkts dropped */ ++ uint32_t fast_drop_bytes; /*!< Fastpath ingress bytes dropped */ ++ uint32_t fast_ingress_cpu_pkts; /*!< Fastpath ingress CPU pkts */ ++ uint32_t fast_ingress_cpu_bytes; /*!< Fastpath ingress CPU bytes */ ++ uint32_t rx_pkt_errors; /*!< Fastpath packet error */ ++ uint32_t fast_bridged_ucast_pkts; /*!< Fastpath bridged unicast pkts */ ++ uint32_t fast_bridged_mcast_pkts; /*!< Fastpath bridged multicast pkts */ ++ uint32_t fast_bridged_bcast_pkts; /*!< Fastpath bridged broadcast pkts */ ++ uint32_t fast_bridged_bytes; /*!< Fastpath bridged bytes */ ++} PPA_ACCEL_STATS; ++ ++/*! ++ \brief This is the data structure for VLAN tag control on a per interface basis. It is currently supported only for bridging ++ paths. For PPE A4 firmware, 2 levels of VLAN is configurable, while for older PPE D4 firmware, only inner VLAN ++ tag is configurable. Please see discussion in section PPA_SESSION_EXTRA. Briefly, couter VLAN tag ++ configuration is used for LAN and WAN isolation on the same external switch, while the other set of VLAN tag ++ configuration is driven from application needs (i.e. not stripped off when the packet hits the wire). ++*/ ++typedef struct { ++ uint32_t unmodified :1; /*!< Indicates if there is no VLAN tag modification. Valid values are IFX_ENABLED and IFX_DISABLED */ ++ uint32_t insertion :1; /*!< Indicates if there is a VLAN tag inserted. Valid values are IFX_ENABLED and IFX_DISABLED */ ++ uint32_t remove :1; /*!< Indicates if there is a VLAN tag removed. Valid values are IFX_ENABLED and IFX_DISABLED */ ++ uint32_t replace :1; /*!< Indicates if there is a VLAN tag replaced. Valid values are IFX_ENABLED and IFX_DISABLED */ ++ uint32_t out_unmodified :1; /*!< Indicates if there is no outer VLAN tag modification. Valid values are IFX_ENABLED and IFX_DISABLED */ ++ uint32_t out_insertion :1; /*!< Indicates if there is a outer VLAN tag inserted. Valid values are IFX_ENABLED and IFX_DISABLED */ ++ uint32_t out_remove :1; /*!< Indicates if there is a outer VLAN tag removed. Valid values are IFX_ENABLED and IFX_DISABLED */ ++ uint32_t out_replace :1; /*!< Indicates if there is a outerVLAN tag replaced. Valid values are IFX_ENABLED and IFX_DISABLED */ ++} PPA_VLAN_TAG_CTRL; ++ ++/*! ++ \brief This is the data structure for VLAN configuration control on a per interface basis. It is currently supported only for ++ bridging paths. ++*/ ++typedef struct { ++ uint32_t src_ip_based_vlan :1; /*!< Indicates if Source IP address filter based VLAN tagging is enabled for this interface. Valid values are IFX_ENABLED and IFX_DISABLED */ ++ uint32_t eth_type_based_vlan :1; /*!< Indicates if Ethernet header type based VLAN tagging is enabled for this interface. Valid values are IFX_ENABLED and IFX_DISABLED */ ++ uint32_t vlanid_based_vlan :1; /*!< Indicates if VLAN re-tagging is enabled based on existing VLAN Id of received frame. Valid values are IFX_ENABLED and IFX_DISABLED */ ++ uint32_t port_based_vlan :1; /*!< Indicates if port based VLAN tagging is enabled for this interface. Valid values are IFX_ENABLED and IFX_DISABLED */ ++ uint32_t vlan_aware :1; /*!< Indicates if bridge is VLAN aware and enforces VLAN based forwarding for this interface. Valid values are IFX_ENABLED and IFX_DISABLED */ ++ uint32_t out_vlan_aware :1; /*!< Indicates if bridge is outer VLAN aware and enforces VLAN based forwarding for this ++ interface. If this field is not enabled, then outer VLAN processing is don't care. ++ interface. If this field is not enabled, then outer VLAN processing is don't care. ++ Valid values are IFX_ENABLED and IFX_DISABLED */ ++} PPA_VLAN_CFG; ++ ++/*! ++ \brief Union of PPA VLAN filter criteria. ++*/ ++typedef union ++{ ++ PPA_IFNAME *ifname; /*!< Pointer to interface name on which VLAN filter match is to be performed. */ ++ IPADDR ip_src; /*!< IP source address of ingress frame for VLAN filter matching. */ ++ uint32_t eth_protocol; /*!< Ethernet protocol as a match filter for VLAN filter matching */ ++ uint32_t ingress_vlan_tag; /*!< Ingress frame VLAN tag as match criteria for VLAN filter matching */ ++} match_criteria_vlan; ++ ++/*! ++ \brief This data structure specifies the filter or match criteria for applying VLAN transforms based on rules. It is currently supported only for bridging paths. ++*/ ++typedef struct { ++ match_criteria_vlan match_field; /*!< Union of VLAN filter criteria */ ++ uint32_t match_flags; /*!< Indicates which VLAN filter criteria is specified in this VLAN match entry. ++ Valid values are one of the following: \n ++ PPA_F_VLAN_FILTER_IFNAME \n ++ PPA_F_VLAN_FILTER_IP_SRC \n ++ PPA_F_VLAN_FILTER_ETH_PROTO \n ++ PPA_F_VLAN_FILTER_VLAN_TAG \n ++ */ ++} PPA_VLAN_MATCH_FIELD; ++ ++/*! ++ \brief This is the data structure for PPA VLAN configuration ioctl() on a per interface basis from userspace. It is currently ++supported only for bridging paths. ++*/ ++typedef struct { ++ uint16_t vlan_vci; /*!< VLAN Information including VLAN Id, 802.1p and CFI bits. */ ++ uint16_t qid; /*!< queue index */ ++ uint32_t out_vlan_id; /*!< out vlan id */ ++ uint32_t inner_vlan_tag_ctrl;/*!< none(0)/remove(1)/insert(2)/replac(3), for vlan tag based only. */ ++ uint32_t out_vlan_tag_ctrl; /*!< none(0)/remove(1)/insert(2)/replac(3), for vlan tag based only. */ ++ uint16_t num_ifs; /*!< Number of interfaces in the array of PPA_IFINFO structures. */ ++ PPA_IFINFO *vlan_if_membership; /*!< Pointer to array of interface info structures for each interface which is a member of this VLAN group. The number of entries is given by num_ifs. */ ++} PPA_VLAN_INFO; ++ ++/*! ++ \brief This is the data structure for PPA VLAN filter configuration. It is currently supported only for bridging paths ++*/ ++typedef struct { ++ PPA_VLAN_MATCH_FIELD match_field; /*!< VLAN Match field information */ ++ PPA_VLAN_INFO vlan_info; /*!< VLAN Group and Membership Info */ ++} PPA_VLAN_FILTER_CONFIG; ++ ++/*! ++ \brief This is the data structure for cout information, like lan interface count, LAN acceleration count and so on ++*/ ++typedef struct { ++ uint32_t count; /*!< the number */ ++ uint32_t flag; /*!< the flag */ ++} PPA_CMD_COUNT_INFO; ++ ++/*! ++ \brief This is the data structure for get some structure size ++*/ ++typedef struct { ++ uint32_t rout_session_size; /*!< the structure size of one routing session */ ++ uint32_t mc_session_size; /*!< the structure size of one multicast session */ ++ uint32_t br_session_size; /*!< the structure size of one bridge session */ ++ uint32_t netif_size; /*!< the structure size of one network interface information*/ ++} PPA_CMD_SIZE_INFO; ++/*@}*/ /* PPA_HOOK_API */ ++ ++/* ++ * ioctl command structures ++ */ ++ ++/** \addtogroup PPA_IOCTL */ ++/*@{*/ ++ ++/*! ++ \brief This is the data structure for PPA Interface information used from the userspacef ++*/ ++typedef struct { ++ PPA_IFNAME ifname[PPA_IF_NAME_SIZE]; /*!< Name of the stack interface ( provide storage buffer ) */ ++ uint32_t if_flags; /*!< Flags for Interface. Valid values are below: PPA_F_LAN_IF and PPA_F_WAN_IF */ ++} PPA_CMD_IFINFO; ++ ++/*! ++ \brief This is the data structure for PPA Init used from the userspace ++*/ ++typedef struct { ++ PPA_VERIFY_CHECKS lan_rx_checks; /*!< LAN Ingress checks */ ++ PPA_VERIFY_CHECKS wan_rx_checks; /*!< WAN Ingress checks */ ++ uint32_t num_lanifs; /*!< Number of LAN side interfaces */ ++ PPA_CMD_IFINFO p_lanifs[PPA_MAX_IFS_NUM]; /*!< Array of LAN Interface Info structures (provides storage buffer). */ ++ uint32_t num_wanifs; /*!< Number of WAN side interfaces */ ++ PPA_CMD_IFINFO p_wanifs[PPA_MAX_IFS_NUM]; /*!< Array of WAN Interface Info structures (provides storage buffer). */ ++ uint32_t max_lan_source_entries; /*!< Number of session entries with LAN source */ ++ uint32_t max_wan_source_entries; /*!< Number of session entries with WAN source */ ++ uint32_t max_mc_entries; /*!< Number of multicast sessions */ ++ uint32_t max_bridging_entries; /*!< Number of bridging entries */ ++ uint32_t add_requires_min_hits; /*!< Minimum number of calls to ppa_add before session would be added in h/w */ ++ uint32_t mtu; /*!< specify PPA network internface's MTU size, default is 1500 */ ++ uint32_t flags; /*!< Flags for PPA Initialization. Currently this field is reserved. */ ++ ++} PPA_CMD_INIT_INFO; ++ ++/*! ++ \brief This is the data structure for PPA Acceleration Enable / Disable configuration ++*/ ++typedef struct { ++ uint32_t lan_rx_ppa_enable; /*!< lan Interface specific flags. Current Valid values are IFX_ENABLED and IFX_DISABLED */ ++ uint32_t wan_rx_ppa_enable; /*!< wan Interface specific flags. Current Valid values are IFX_ENABLED and IFX_DISABLED */ ++ uint32_t flags; /*!< Reserved currently */ ++} PPA_CMD_ENABLE_INFO; ++ ++/*! ++ \brief This is the data structure for MAC table entry used in PPA ioctl interface ++*/ ++typedef struct { ++ IP_ADDR_C mcast_addr; /*!< MC address of the entry */ ++ IP_ADDR source_ip; /*!< source ip */ ++ uint8_t SSM_flag; /*!< ssm flag */ ++ PPA_SESSION_EXTRA mc_extra; /*!< Pointer to PPA Multicast session parameters like VLAN configuration, DSCP remarking */ ++ uint32_t flags; /*!< Flags for the PPA Multicast entry info structure. Reserved currently. */ ++ ++} PPA_CMD_MC_ENTRY; ++ ++/*! ++ \brief This is the data structure for learned MAC address used in PPA ioctl interface ++*/ ++typedef struct { ++ uint8_t mac_addr[PPA_ETH_ALEN]; /*!< MAC address learned */ ++ PPA_IFNAME ifname[PPA_IF_NAME_SIZE]; /*!< The interface which learned the MAC address */ ++ uint32_t flags; /*!< for future */ ++} PPA_CMD_MAC_ENTRY; ++ ++/*! ++ \brief This is the data structure for PPA VLAN configuration ioctl() on a per interface basis from userspace. It is currently ++ supported only for bridging paths. ++*/ ++typedef struct ++{ ++ PPA_IFNAME if_name[PPA_IF_NAME_SIZE]; /*!< Pointer to interface name for which VLAN related configuration is specified. */ ++ PPA_VLAN_TAG_CTRL vlan_tag_ctrl; /*!< VLAN Tag Control structure for the interface */ ++ PPA_VLAN_CFG vlan_cfg; /*!< VLAN Configuration control structure for the interface */ ++ uint32_t flags; /*!< Flags field. Reserved currently and omitted in implementation. */ ++} PPA_CMD_BR_IF_VLAN_CONFIG; ++ ++ ++/*! ++ \brief Union for VLAN filter matching criteria. ++*/ ++typedef union { ++ PPA_IFNAME ifname[PPA_IF_NAME_SIZE]; /*!< Pointer to interface name on which VLAN filter match is to be performed. */ ++ IPADDR ip_src; /*!< IP source address of ingress frame for VLAN filter matching. */ ++ uint32_t eth_protocol; /*!< Ethernet protocol as a match filter for VLAN filter matching. */ ++ uint32_t ingress_vlan_tag; /*!< Ingress frame VLAN tag as match criteria for VLAN filter matching. */ ++} filter_criteria; ++ ++ ++/*! ++ \brief This data structure specifies the filter or match criteria for applying VLAN transforms based on rules. It is currently supported only for bridging paths. ++*/ ++typedef struct { ++ filter_criteria match_field; /*!< Union for VLAN filter criteria. */ ++ uint32_t match_flags; /*!< Indicates which VLAN filter criteria is specified in this VLAN match entry. \n ++ Valid values are one of the following: \n ++ - PPA_F_VLAN_FILTER_IFNAME \n ++ - PPA_F_VLAN_FILTER_IP_SRC \n ++ - PPA_F_VLAN_FILTER_ETH_PROTO \n ++ - PPA_F_VLAN_FILTER_VLAN_TAG ++ */ ++} PPA_CMD_VLAN_MATCH_FIELD; ++ ++/*! ++ \brief This is the data structure for PPA VLAN configuration ioctl() on a per interface basis from userspace. It is currently supported only for bridging paths. ++*/ ++typedef struct { ++ uint16_t vlan_vci; /*!< VLAN Information including VLAN Id, 802.1p and CFI bits */ ++ uint16_t qid; /*!< dest_qos */ ++ uint32_t out_vlan_id; /*!< new out vlan id */ ++ uint32_t out_vlan_tag_ctrl; /*!< unmodify(0)/remove(1)/insert(2)/replac(3), for vlan tag based only. */ ++ uint32_t inner_vlan_tag_ctrl;/*!< unmodify(0)/remove(1)/insert(2)/replac(3), for vlan tag based only. */ ++ uint16_t num_ifs; /*!< Number of interfaces in the array of PPA_IFINFO structures. */ ++ PPA_CMD_IFINFO vlan_if_membership[PPA_MAX_IFS_NUM]; /*!< Pointer to array of interface info structures for each interface which is a member of this VLAN group. The number of entries is given by num_ifs. */ ++} PPA_CMD_VLAN_INFO; ++ ++/*! ++ \brief This is the data structure for basic VLAN filter setting in PPA ioctl interface ++*/ ++typedef struct { ++ PPA_CMD_VLAN_MATCH_FIELD match_field; /*!< vlan filter match field */ ++ PPA_CMD_VLAN_INFO vlan_info; /*!< vlan information */ ++} _PPA_CMD_VLAN_FILTER_CONFIG; ++ ++/*! ++ \brief This is the data structure for VLAN filter configure in PPA ioctl interface ++*/ ++typedef struct { ++ _PPA_CMD_VLAN_FILTER_CONFIG vlan_filter_cfg; /*!< vlan filter basc information */ ++ uint32_t flags; /*!< flag */ ++} PPA_CMD_VLAN_FILTER_CONFIG; ++ ++/*! ++ \brief This is the data structure for PPA VLAN configuration as passed to the PPA ioctl() API from userspace. It is ++currently supported only for bridging paths. ++*/ ++typedef struct { ++ PPA_CMD_COUNT_INFO count_info; /*!< Number of filters returned in pointer to array of filters. */ ++ PPA_CMD_VLAN_FILTER_CONFIG filters[1]; /*!< it is a dummy array. Userspace should apply storage buffer for it */ ++} PPA_CMD_VLAN_ALL_FILTER_CONFIG; ++/*! ++ \brief This is the data structure for PPA accelerated statistics for an interface. Depending on the platform and ++ acceleration capabilities, some of the statistics may not be available. ++*/ ++typedef struct { ++ PPA_IFNAME ifname[PPA_IF_NAME_SIZE]; /*!< interface name ( provides storage buffer) */ ++ uint8_t mac[PPA_ETH_ALEN]; /*!< MAC address of the Ethernet Interface ( provides storage buffer) */ ++ uint32_t flags; /*!< reserved for future */ ++} PPA_CMD_IF_MAC_INFO; ++ ++/*! ++ \brief This is the data structure for LAN/WAN interface setting ++*/ ++typedef struct { ++ uint32_t num_ifinfos; /*!< number of interface in the list */ ++ PPA_CMD_IFINFO ifinfo[PPA_MAX_IFS_NUM]; /*!< buffer for storing network interface list */ ++} PPA_CMD_IFINFOS; ++ ++/*! ++ \brief This is the data structure for Multicast group related ioctl ++*/ ++typedef struct { ++ uint8_t mac[PPA_ETH_ALEN]; /*!< mac address of the multicast group, reserved for future */ ++ PPA_IFNAME lan_ifname[PPA_MAX_MC_IFS_NUM][PPA_IF_NAME_SIZE]; /*!< downstream interface list buffer */ ++ PPA_IFNAME src_ifname[PPA_IF_NAME_SIZE]; /*!< source interface which receive multicast streaming packet */ ++ uint32_t num_ifs; /*!< downstream interface number */ ++ uint32_t bridging_flag; /*!< IGMP Proxy/snooping flag: 0 - routing mode/igmp proxy, 1 - bring mode/igmp snooping. */ ++ ++ uint32_t new_dscp_en; /*!< dscp editing flag: 1 -- need to edit, 0 --unmodify */ ++ PPA_CMD_MC_ENTRY mc; /*!< multicast group information */ ++} PPA_CMD_MC_GROUP_INFO; ++/*! ++ \brief This is the data structure for get all Multicast group via ioctl ++*/ ++typedef struct { ++ PPA_CMD_COUNT_INFO count_info; /*!< the multicast counter */ ++ PPA_CMD_MC_GROUP_INFO mc_group_list[1]; /*!< Note, here is a dummy array, user need to malloc memory accordingly to the session number */ ++} PPA_CMD_MC_GROUPS_INFO; ++ ++/*! ++ \brief This is the data structure contains PPA session information. ++*/ ++typedef struct { ++ uint16_t ip_proto; /*!< IP portocol TCP,UDP. */ ++ uint16_t ip_tos; /*!< IP ToS value */ ++ PPA_IPADDR src_ip; /*!< source IP address */ ++ uint16_t src_port; /*!< source port */ ++ PPA_IPADDR dst_ip; /*!< destination IP address */ ++ uint16_t dst_port; /*!< destination port */ ++ PPA_IPADDR nat_ip; /*!< IP address to be replaced by NAT if NAT applies */ ++ uint16_t nat_port; /*!< Port to be replaced by NAT if NAT applies */ ++ uint32_t new_dscp; /*!< If DSCP remarking required */ ++ uint16_t new_vci; /*!< new vci ( in fact, it is new inner vlan id )*/ ++ uint32_t out_vlan_tag; /*!< Out VLAN tag */ ++ uint16_t dslwan_qid; /*!< WAN qid */ ++ uint16_t dest_ifid; /*!< Destination interface */ ++ ++ uint32_t flags; /*!< Internal flag : SESSION_IS_REPLY, SESSION_IS_TCP, \n ++ SESSION_ADDED_IN_HW, SESSION_CAN_NOT_ACCEL \n ++ SESSION_VALID_NAT_IP, SESSION_VALID_NAT_PORT, \n ++ SESSION_VALID_VLAN_INS, SESSION_VALID_VLAN_RM, \n ++ SESSION_VALID_OUT_VLAN_INS, SESSION_VALID_OUT_VLAN_RM, \n ++ SESSION_VALID_PPPOE, SESSION_VALID_NEW_SRC_MAC, \n ++ SESSION_VALID_MTU, SESSION_VALID_NEW_DSCP, \n ++ SESSION_VALID_DSLWAN_QID, \n ++ SESSION_TX_ITF_IPOA, SESSION_TX_ITF_PPPOA \n ++ SESSION_LAN_ENTRY, SESSION_WAN_ENTRY, */ ++ PPA_IFNAME rx_if_name[PPA_IF_NAME_SIZE]; /*!< receive interface name. Note, in struct session_list_item, rx_if and tx_if is a pointer, so here we have to make a workaround for it. */ ++ PPA_IFNAME tx_if_name[PPA_IF_NAME_SIZE]; /*!< txansmit interface name. */ ++ uint64_t mips_bytes; /*!< bytes processed by the mips */ ++ uint64_t hw_bytes; /*!< bytes proccesed by hareware acceleration unit*/ ++ uint64_t prev_sess_bytes; /*!< last bytes proccesed by hareware acceleration unit or */ ++ uint32_t session; /*!< PPA SESSION pointer. Note, here we just use its address to delete a session for ioctl*/ ++ uint32_t collision_flag; /*!< 1 mean the entry is in collsion table or none-hashed, like ASE/Danubel*/ ++ uint32_t priority; /*!< skb->priority*/ ++} PPA_CMD_SESSION_ENTRY; ++ ++/*! ++ \brief This is the data structure contains PPA session extra information. ++*/ ++typedef struct { ++ uint32_t session; /*!< PPA SESSION pointer. Note, here we just use its address to modify a session for ioctl*/ ++ PPA_SESSION_EXTRA session_extra; /*!< PPA SESSION extra pointer. */ ++ uint32_t flags; /*!< Internal flag : PPA_F_SESSION_NEW_DSCP \n ++ PPA_F_MTU, PPA_F_SESSION_OUT_VLAN, PPA_F_ACCEL_MODE ....\n ++ */ ++ uint32_t lan_wan_flags; /*!< Internal flag : the flag to matcn LAN only, or WAN only or both \n ++ The possible value is SESSION_WAN_ENTRY, SESSION_LAN_ENTRY ++ */ ++}PPA_CMD_SESSION_EXTRA_ENTRY; ++ ++ ++typedef struct { ++ uint32_t session; /*!< PPA SESSION pointer. Note, here we just use its address to modify a session for ioctl*/ ++ int32_t timer_in_sec; /*!< PPA SESSION polling timer in seconds. */ ++ uint32_t flags; /*!< Reserved for future */ ++}PPA_CMD_SESSION_TIMER; ++ ++ ++/*! ++ \brief This is the data structure for routing session information ++*/ ++typedef struct { ++ PPA_CMD_COUNT_INFO count_info; /*!< session count */ ++ PPA_CMD_SESSION_ENTRY session_list[1]; /*!< Note, here is a dummy array, user need to malloc memory accordingly to the session number */ ++} PPA_CMD_SESSIONS_INFO; ++ ++/*! ++ \brief This is the data structure for routing detail session information ++*/ ++typedef struct { ++ uint16_t ip_proto; /*!< IP portocol TCP,UDP. */ ++ PPA_IPADDR src_ip; /*!< source IP address */ ++ uint16_t src_port; /*!< source port */ ++ PPA_IPADDR dst_ip; /*!< destination IP address */ ++ uint16_t dst_port; /*!< destination port */ ++ PPA_IPADDR nat_ip; /*!< IP address to be replaced by NAT if NAT applies */ ++ uint16_t nat_port; /*!< Port to be replaced by NAT if NAT applies */ ++ uint32_t new_dscp; /*!< If DSCP remarking required */ ++ uint16_t in_vci_vlanid; /*!< new vci ( in fact, it is new inner vlan id )*/ ++ uint32_t out_vlan_tag; /*!< Out VLAN tag */ ++ uint16_t qid; /*!< WAN qid */ ++ uint32_t flags; /*!< Internal flag : SESSION_IS_REPLY, SESSION_IS_TCP, \n ++ SESSION_ADDED_IN_HW, SESSION_CAN_NOT_ACCEL \n ++ SESSION_VALID_NAT_IP, SESSION_VALID_NAT_PORT, \n ++ SESSION_VALID_VLAN_INS, SESSION_VALID_VLAN_RM, \n ++ SESSION_VALID_OUT_VLAN_INS, SESSION_VALID_OUT_VLAN_RM, \n ++ SESSION_VALID_PPPOE, SESSION_VALID_NEW_SRC_MAC, \n ++ SESSION_VALID_MTU, SESSION_VALID_NEW_DSCP, \n ++ SESSION_VALID_DSLWAN_QID, \n ++ SESSION_TX_ITF_IPOA, SESSION_TX_ITF_PPPOA \n ++ SESSION_LAN_ENTRY, SESSION_WAN_ENTRY, */ ++ uint32_t dest_ifid; /*!< txansmit interface name. */ ++ uint8_t src_mac[PPA_ETH_ALEN]; /*!< src mac addres */ ++ uint8_t dst_mac[PPA_ETH_ALEN]; /*!< dst mac address */ ++ uint16_t pppoe_session_id; /*!< pppoe session id */ ++ ++ uint32_t mtu; /*!< mtu */ ++}PPA_CMD_SESSIONS_DETAIL_INFO; ++ ++/*! ++ \brief This is the data structure for basic ppa Versions ++*/ ++typedef struct { ++ uint32_t index; /*!< index for PP32 */ ++ uint32_t family; /*!< ppa version hardware family */ ++ uint32_t type; /*!< ppa version hardware type */ ++ uint32_t itf;/*!< ppa version itf */ ++ uint32_t mode; /*!< ppa version mode */ ++ uint32_t major; /*!< ppa version major version number */ ++ uint32_t mid; /*!< ppa version mid version number */ ++ uint32_t minor; /*!< ppa version minor version number */ ++} PPA_VERSION; ++ ++/*! ++ \brief This is the data structure for ppa wan mode information ++*/ ++typedef struct{ ++ uint32_t wan_port_map; /*!< wan port map information*/ ++ uint32_t mixed; /*!< mixed flag */ ++} PPA_WAN_INFO; ++ ++/*! ++ \brief This is the data structure for ppa supported feature list information ++*/ ++typedef struct{ ++ uint8_t ipv6_en; /*!< ipv6 enable/disable status */ ++ uint8_t qos_en; /*!< qos enable/disable status */ ++} PPA_FEATURE_INFO; ++ ++/*! ++ \brief This is the data structure for PPA subsystem Versions, like ppa subsystem, ppe fw, ppe driver and so on ++*/ ++typedef struct { ++ PPA_VERSION ppa_api_ver; /*!< PPA API verion */ ++ PPA_VERSION ppa_stack_al_ver; /*!< PPA stack verion */ ++ PPA_VERSION ppe_hal_ver; /*!< PPA HAL verion */ ++ PPA_VERSION ppe_fw_ver[2]; /*!< PPA FW verion */ ++ PPA_VERSION ppa_subsys_ver; /*!< PPA Subsystem verion */ ++ PPA_WAN_INFO ppa_wan_info; /*!< PPA WAN INFO */ ++ PPA_FEATURE_INFO ppe_fw_feature; /*!< PPE FW feature lists */ ++ PPA_FEATURE_INFO ppa_feature; /*!< PPA Level feature lists */ ++ ++} PPA_CMD_VERSION_INFO; ++ ++/*! ++ \brief This is the data structure for basic vlan range ++*/ ++typedef struct { ++ uint32_t start_vlan_range; /*!< WAN interface start vlan id */ ++ uint32_t end_vlan_range; /*!< WAN interface end vlan id */ ++}PPA_VLAN_RANGE; ++ ++/*! ++ \brief This is the data structure VLAN range in mixed mode ++*/ ++typedef struct { ++ PPA_CMD_COUNT_INFO count_info; /*!< PPA Count info */ ++ PPA_VLAN_RANGE ranges[1]; /*!< it is dummy array, need to malloc in userspace */ ++} PPA_CMD_VLAN_RANGES; ++ ++/*! ++ \brief This is the data structure for MAC INFO ++*/ ++typedef struct { ++ PPA_CMD_COUNT_INFO count_info; /*!< PPA Count info */ ++ PPA_CMD_MAC_ENTRY session_list[1]; /*!< it is a dummy array, need to malloc bedore use it in userspace */ ++} PPA_CMD_ALL_MAC_INFO; ++ ++/*! ++ \brief This is the data structure for BRIGE MAC LEARNING ENABLE/DISABLE INFO ++*/ ++typedef struct { ++ uint32_t bridge_enable; /*!< enable/disable bridging mac address learning flag */ ++ uint32_t flags; /*!< reserved for future */ ++} PPA_CMD_BRIDGE_ENABLE_INFO; ++ ++typedef struct { ++ uint32_t t; /*!< Time Tick */ ++ uint32_t w; /*!< weight */ ++ uint32_t s; /*!< burst */ ++ uint32_t r; /*!< Replenish */ ++ uint32_t d; /*!< ppe internal variable */ ++ uint32_t tick_cnt; /*!< ppe internal variable */ ++ uint32_t b; /*!< ppe internal variable */ ++ ++ /*For PPA Level only */ ++ uint32_t reg_addr; /*!< register address */ ++ uint32_t bit_rate_kbps; /*!< rate shaping in kbps */ ++ uint32_t weight_level; /*!< internal wfq weight */ ++ ++}PPA_QOS_INTERVAL; ++ ++typedef struct { ++ //struct wtx_qos_q_desc_cfg ++ uint32_t threshold; /*!< qos wtx threshold */ ++ uint32_t length; /*!< qos wtx length */ ++ uint32_t addr; /*!< qos wtx address */ ++ uint32_t rd_ptr; /*!< qos wtx read pointer */ ++ uint32_t wr_ptr; /*!< qos wtx write pointer */ ++ ++ /*For PPA Level only */ ++ uint32_t reg_addr; /*!< register address */ ++}PPA_QOS_DESC_CFG_INTERNAL; ++ ++ ++/*! ++ \brief This is the data structure for PPA QOS to get the maximum queue number supported for one physical port ++*/ ++typedef struct { ++ uint32_t portid; /*!< the phisical port id which support qos queue */ ++ uint32_t queue_num; /*!< the maximum queue number is supported */ ++ uint32_t flags; /*!< Reserved currently */ ++} PPA_CMD_QUEUE_NUM_INFO; ++ ++/*! ++ \brief This is the data structure for PPA QOS MIB Counter ++*/ ++typedef struct { ++ uint32_t total_rx_pkt; /*!< all packets received by this queue */ ++ uint32_t total_rx_bytes; /*!< all bytes received by thi queue */ ++ uint32_t total_tx_pkt; /*!< all packets trasmitted by this queue */ ++ uint32_t total_tx_bytes; /*!< all bytes trasmitted by thi queue */ ++ ++ uint32_t cpu_path_small_pkt_drop_cnt; /*!< all small packets dropped in CPU path for lack of TX DMA descriptor in the queue*/ ++ uint32_t cpu_path_total_pkt_drop_cnt; /*!< all packets dropped in CPU path for lack of TX DMA descriptor in the queue*/ ++ uint32_t fast_path_small_pkt_drop_cnt; /*!< all small packets dropped in fast path for lack of TX DMA descriptor */ ++ uint32_t fast_path_total_pkt_drop_cnt; /*!< all packets dropped in fast path for lack of TX DMA descriptor */ ++} PPA_QOS_MIB; ++ ++/*! ++ \brief This is the data structure for PPA QOS to get the maximum queue number supported for one physical port ++*/ ++typedef struct { ++ uint32_t portid; /*!< the phisical port id which support qos queue */ ++ uint32_t queueid; /*!< the queue id for the mib */ ++ PPA_QOS_MIB mib; /*!< the mib information for the current specified queue */ ++ uint32_t flags; /*!< Reserved currently */ ++} PPA_CMD_QOS_MIB_INFO; ++ ++ ++ ++/*! ++ \brief This is the data structure for PPA QOS to be enabled/disabled ++*/ ++typedef struct { ++ uint32_t portid; /*!< which support qos queue. */ ++ uint32_t enable; /*!< enable/disable flag */ ++ uint32_t flags; /*!< Reserved currently */ ++} PPA_CMD_QOS_CTRL_INFO; ++ ++/*! ++ \brief This is the data structure for PPA Rate Shapping Set/Get/Reset one queue's rate limit ++*/ ++typedef struct { ++ uint32_t portid; /*!< the phisical port id which support qos queue */ ++ uint32_t queueid; /*!< the queu id. Now it only support 0 ~ 7 */ ++ uint32_t rate; /*!< rate limit in kbps */ ++ uint32_t burst; /*!< rate limit in bytes. Note: it is PPE FW QOS internal value. Normally there is no need to set this value or just set to default value zero */ ++ uint32_t flags; /*!< Reserved currently */ ++} PPA_CMD_RATE_INFO; ++ ++ ++ ++/*! ++ \brief This is the data structure for PPA WFQ Set/Get/Reset one queue's weight ++*/ ++typedef struct { ++ uint32_t portid; /*!< the phisical port id which support qos queue */ ++ uint32_t queueid; /*!< the queu id. Now it only support 0 ~ 7 */ ++ uint32_t weight; /*!< WFQ weight. The value is from 0 ~ 100 */ ++ uint32_t flags; /*!< Reserved currently */ ++} PPA_CMD_WFQ_INFO; ++ ++#if defined(CONFIG_IFX_PMCU) || defined(CONFIG_IFX_PMCU_MODULE) ++/*! ++ \brief Union of ppa power transitin watermark. ++*/ ++union watermark { ++ uint32_t ppa_pwm_wm1; /*!< Watermark value for PPE transition between D0 and D1 */ ++ uint32_t ppa_pwm_wm2; /*!< Watermark value for PPE transition between D1 and D2 */ ++ uint32_t ppa_pwm_wm3; /*!< Watermark value for PPE transition between D2 and D3 */ ++}; ++ ++/*! ++ \brief This is the data structure definition for PPA PWM states water mark ++*/ ++typedef struct { ++ int16_t flag; /*!< flag indicating if watermark type. flag=1: watermark is packet count; flag=2: watermark is byte count */ ++ int32_t time_interval; /*!< time interval of watermarks in milliseconds. */ ++ union watermark WM; /*!< Watermark value for PPE transition */ ++}WM_t; ++ ++/*! ++ \brief This is the data structure for PPA Power management basic watermark configuration ++*/ ++typedef struct { ++ WM_t ppa_pwm_wm1; /*!< Watermark value for PPE transition between D0 and D1 */ ++ WM_t ppa_pwm_wm2; /*!< Watermark value for PPE transition between D1 and D2*/ ++ WM_t ppa_pwm_wm3; /*!< Watermark value for PPE transition between D2 and D3*/ ++}PPA_PWM_WM_t; ++ ++/*! ++ \brief This is the data structure for PPA Power management configuration ++*/ ++typedef struct { ++ uint8_t ppa_pwm; /*!< PPA power management mode: 0/1-OFF/ON */ ++ PPA_PWM_WM_t ppa_pwm_wm_up; /*!< Watermark value for PPE transition for various states. */ ++ PPA_PWM_WM_t ppa_pwm_wm_down; /*!< Watermark value for PPE transition for various states. */ ++ PPA_PWM_STATE_t e_ppa_pwm_init_state; /*!< Initial power/performance state for PPE */ ++ uint32_t flag; /*!< reserved.*/ ++}PPA_PWM_CONFIG_t; ++#endif //end of CONFIG_IFX_PMCU ++ ++/*! ++ \brief This is the data structure for Mutiple Field Based Classification And VLAN Assigment feature's basic auto-learning VLAN related information. ++*/ ++typedef struct ++{ ++ PPA_IFNAME tx_ifname[PPA_IF_NAME_SIZE]; /*!< destination interface name, like eth0.3. If blank, then match all interface */ ++ PPA_IFNAME rx_ifname[PPA_IF_NAME_SIZE]; /*!< receiving interface name, like eth1.2, If blank, then match all interface */ ++}PPA_MULTIFIELD_VLAN_INFO_AUTO; ++ ++/*! ++ \brief This is the data structure for Mutiple Field Based Classification And VLAN Assigment's manual-learning VLAN information based on default key selection. ++*/ ++typedef struct ++{ ++ uint8_t tx_if_id; /*!< physical destination interface id match, like 0 for eth0, 1 for eth1. It is part of key 14 */ ++ uint8_t rx_if_id; /*!< physical destination interface id match, like 0 for eth0, 1 for eth1. It is part of key 15 */ ++ uint8_t is_vlan; /*!< VLAN Flag match. 1: only match single vlan, 2: match double vlan, 0: match no vlan packet. It is part of key14 */ ++ uint8_t is_vlan_mask; /*!< VLAN Flag mask*/ ++ ++ uint8_t out_vlan_pri; /*!< outer vlan priority ( 3 bits only) match. Based on PPA default Key Selection, it is part of key 8/l2_off14 */ ++ uint8_t out_vlan_pri_mask; /*!< match mask to specify the bits to match. Note, 0 means need to match and 1 means not to match*/ ++ uint8_t out_vlan_cfi; /*!< outer vlan cfi ( 1 bits only) match. Based on PPA default Key Selection, it is part of key 8/l2_off14 */ ++ uint8_t out_vlan_cfi_mask; /*!< match mask to specify the bits to match. Note, 0 means need to match and 1 means not to match*/ ++ ++ uint16_t out_vlan_vid; /*!< outer vlan id ( 1 bits only) match. Based on PPA default Key Selection, it is part of key 8 and 9/l2_off14-15 */ ++ uint16_t out_vlan_vid_mask; /*!< match mask to specify the bits to match. Note, 0 means need to match and 1 means not to match*/ ++ ++ uint8_t in_vlan_pri; /*!< inner vlan priority ( 3 bits only) match. Based on PPA default Key Selection, it is part of key 12/l2_off18 */ ++ uint8_t in_vlan_pri_mask; /*!< match mask to specify the bits to match. Note, 0 means need to match and 1 means not to match*/ ++ uint8_t in_vlan_cfi; /*!< inner vlan cfi ( 1 bits only) match. Based on PPA default Key Selection, it is part of key 12/l2_off18 */ ++ uint8_t in_vlan_cfi_mask; /*!< match mask to specify the bits to match. Note, 0 means need to match and 1 means not to match*/ ++ ++ uint16_t in_vlan_vid; /*!< inner vlan id ( 1 bits only) match. Based on PPA default Key Selection, it is part of key 12 and 13/l2_off18-19 */ ++ uint16_t in_vlan_vid_mask; /*!< match mask to specify the bits to match. Note, 0 means need to match and 1 means not to match*/ ++ ++ uint8_t action_out_vlan_insert; /*!< out vlan insert action */ ++ uint8_t action_in_vlan_insert; /*!< inner vlan insert action */ ++ uint8_t action_out_vlan_remove; /*!< out vlan remove action */ ++ uint8_t action_in_vlan_remove; /*!< inner vlan remove action */ ++ ++ uint8_t new_out_vlan_pri; /*!< action: new out vlan priority */ ++ uint8_t new_out_vlan_cfi; /*!< action:new out vlan cfi */ ++ uint8_t new_in_vlan_pri; /*!< action:new inner vlan priority */ ++ uint8_t new_in_vlan_cfi; /*!< action:new inner vlan cfi */ ++ ++ uint16_t new_out_vlan_vid; /*!< action:new out vlan id */ ++ uint16_t new_in_vlan_vid; /*!< action:new inner vlan id */ ++ ++ uint16_t new_out_vlan_tpid; /*!< action:new out vlan tpid */ ++}PPA_MULTIFIELD_VLAN_INFO_MANUAL; ++ ++/*! ++ \brief This is the data structure for Mutiple Field Based Classification And VLAN Assigment's VLAN KEY/MASK/ACTION based on default key selection. ++*/ ++typedef struct ++{ ++ uint8_t bfauto; /*!< flag to use simple autoway to add a multiple field editing flow. It is used by PPA API level and hook/ppacmd only*/ ++ PPA_MULTIFIELD_VLAN_INFO_AUTO vlan_info_auto; /*!< auto-learn vlan key/mask/action. Note, it is only for add/delete a rule, not for get commands */ ++ PPA_MULTIFIELD_VLAN_INFO_MANUAL vlan_info_manual; /*!< munually provide vlan key/mask/action. Even vlan_info_auto is used, ppa will set vlan_info_manual structure for PPE driver */ ++ ++}PPA_MULTIFIELD_VLAN_INFO; ++ ++/*! ++ \brief This is the data structure for Mutiple Field Based Classification And VLAN Assigment's configuration based on default key selection. ++*/ ++typedef struct ++{ ++ uint16_t ether_type; /*!< ethernet type match, like 0x0800. Based on PPA default Key Selection, it is key0_1*/ ++ uint16_t ether_type_mask; /*!< match mask to specify the bits to match. Note, 0 means need to match and 1 means not to match*/ ++ ++ uint8_t dscp; /*!< dscp(tos) match. 1: key of dscp in ip header, like 0x08. Based on PPA default Key Selection, it is key2*/ ++ uint8_t dscp_mask; /*!< match mask to specify the bits to match. Note, 0 means need to match and 1 means not to match*/ ++ uint8_t pkt_length; /*!< packet length ( less than) match. Its value is got from ethernet packet length /64. Based on PPA default Key Selection, it is key3*/ ++ uint8_t pkt_length_mask; /*!< packet length mask.*/ ++ ++ uint32_t s_ip; /*!< source ip match, like 0x0a000009 ( 10.0.0.9) . Based on PPA default Key Selection, it is key4 ~ Key7*/ ++ uint32_t s_ip_mask; /*!< match mask to specify the bits to match. Note, 0 means need to match and 1 means not to match*/ ++ ++ uint8_t l3_off0; /*!< L3 Offset 0 match. Baed on PPA default key selection, it is key10 */ ++ uint8_t l3_off0_mask; /*!< L3 Offset 0 mask */ ++ uint8_t l3_off1; /*!< L3 Offset 1 match. Baed on PPA default key selection, it is key11 */ ++ uint8_t l3_off1_mask; /*!< L3 Offset 1 mask */ ++ ++ uint8_t ipv4; /*!< ipv4 match ( 1 bit). 1: match only ipv4. 0: match none ipv4 packet. It is part of key15. */ ++ uint8_t ipv4_mask; /*!< ipv4 mask. 0 -need to match, 1-no need to match */ ++ uint8_t ipv6; /*!< < ipv6 match ( 1 bit). 1: match only ipv6. 0: match none ipv6 packet. 1: match only ipv6, 0: match none ipv6 packet. It is part of key15 */ ++ uint8_t ipv6_mask; /*!< ipv6 mask. 0 -need to match, 1-no need to match */ ++ ++ uint8_t pppoe_session; /*!< pppoe session flag match: 1: match pppoe session only. 0-- match none pppoe session packet. It is part of key14 */ ++ uint8_t pppoe_session_mask; /*!< pppoe session flag mask. 0 -need to match, 1-no need to match */ ++ uint8_t fwd_cpu; /*!< action: forward packet to CPU or not. \n ++ 1: forward to CPU. ++ 0: forward to its original destination port\n */ ++ ++ uint8_t queue_id; /*!< action: which queue assign for the current flow. */ ++ ++ PPA_MULTIFIELD_VLAN_INFO vlan_info; /*!< specify vlan key/mask/action. Based on PPA default Key Selection. It relates to key8/key9, key 12/key13 and key14/key15 and part of vlan action*/ ++} PPA_MULTIFIELD_DEFAULT_INFO; ++ ++/*! ++ \brief This is the data structure for Mutiple Field Based Classification And VLAN Assigment's configuration based on second default key selection. ++ \note, for future only now ++*/ ++ ++typedef struct ++{ ++ ++}PPA_MULTIFIELD_DEFAULT2_INFO; ++ ++/*! ++ \brief This is the data structure for Mutiple Field Based Classification And VLAN Assigment's configuration based on different key selection. ++ \note More key selection based configuration will be implemented. Note, different key selectoin may have different configuration. \n ++ PPA should parse the cfg according to current key selection mode ++ ++*/ ++typedef union ++{ ++ PPA_MULTIFIELD_DEFAULT_INFO cfg0; /*!< multiple field configuration based on default key selection. */ ++ PPA_MULTIFIELD_DEFAULT2_INFO cfg2; /*!< multiple field configuration based on second default key selection. */ ++}PPA_MULTIFIELD_FLOW_INFO; ++ ++/*! ++ \brief This is the data structure for IOCTL of Mutiple Field Based Classification And VLAN Assigment's configuration. ++ ++*/ ++typedef struct ++{ ++ int32_t index; /*!< for get command, it is input, for add command, it is input. for del, it is input ( index must be valid in this case, -1 means delete all flow ) */ ++ int32_t last_index; /*!< for get command. It will be used in ppacmd.c only */ ++ uint32_t flag; /*!< Most time, it is input only. But for PPA_CMD_GET_MULTIFIELD_STATUS, it is input/ouput */ ++ PPA_MULTIFIELD_FLOW_INFO flow; /*!< the Mutiple Field Based Classification And VLAN Assigment configuration/information */ ++} PPA_CMD_MULTIFIELD_FLOW_INFO ; ++ ++/*! ++ \brief This is the data structure for IOCTL to enable/disable Mutiple Field Based Classification And VLAN Assigment. ++ ++*/ ++typedef struct PPA_CMD_ENABLE_MULTIFIELD_INFO ++{ ++ uint32_t enable_multifield; /*!< flag of enable/disable the Mutiple Field Based Classification And VLAN Assigment feature */ ++ uint32_t flag; /*!< reserved for future */ ++} PPA_CMD_ENABLE_MULTIFIELD_INFO; ++ ++/*! ++ \brief This is the data structure for getting all exported PPA hooks. ++*/ ++typedef struct ++{ ++ uint8_t hookname[MAX_HOOK_NAME_LEN]; /*!< hook name */ ++ uint32_t hook_addr; /*!< hook address */ ++ uint32_t real_func; /*!< hook pointer to real function*/ ++ uint8_t hook_flag; /*!< hooked flag: 0-disabled, 1-enabled */ ++}PPA_HOOK_INFO; ++ ++/*! ++ \brief This is the data structure for PPA hooks list ++*/ ++typedef struct PPA_HOOK_INFO_LIST { ++ PPA_HOOK_INFO info; /*!< ppa hook info */ ++ ++ struct PPA_HOOK_INFO_LIST *next; /*!< point to next ppa hook info */ ++} PPA_HOOK_INFO_LIST; ++ ++/*! ++ \brief This is the data structure for getting all exported PPA hooks. ++*/ ++typedef struct ++{ ++ uint32_t hook_count; /*!< hook counter */ ++ uint32_t flag; /*!< reserved for future */ ++ PPA_HOOK_INFO list[1]; /*!< it is a dummy array. Userspace should apply storage buffer for it. */ ++}PPA_CMD_HOOK_LIST_INFO; ++ ++/*! ++ \brief This is the data structure for enable/disable ppa hook ++*/ ++typedef struct ++{ ++ uint8_t hookname[MAX_HOOK_NAME_LEN]; /*!< hook name */ ++ uint32_t enable; /*!< enable/disable ppa hook */ ++ uint32_t flag; /*!< reserved for future */ ++}PPA_HOOK_ENABLE_INFO; ++ ++/*! ++ \brief This is the data structure for IOCTL to enable/disable ppa hook ++*/ ++typedef PPA_HOOK_ENABLE_INFO PPA_CMD_HOOK_ENABLE_INFO; ++ ++/*! ++ \brief This is the data structure to get the memory value. ++*/ ++typedef struct ++{ ++ uint32_t addr; /*!< The memory adddress to read */ ++ uint32_t addr_mapped; /*!< The mapped memory adddress to read */ ++ uint32_t shift; /*!< the bits to shitf */ ++ uint32_t size; /*!< size of bits to read*/ ++ uint32_t repeat; /*!< read repeat times */ ++ uint32_t flag; /*!< reserved for future */ ++ uint32_t buffer[1]; /*!< the buffer to store the value. it is a dummy array. Userspace should apply storage buffer for it. Its size should be at least size * sizeof (uint32_t) */ ++}PPA_READ_MEM_INFO; ++ ++#ifdef NO_DOXY ++typedef PPA_READ_MEM_INFO PPA_CMD_READ_MEM_INFO; ++ ++/*! ++ \brief This is the data structure to set the memory value. ++*/ ++typedef struct ++{ ++ uint32_t addr; /*!< The memory adddress to set */ ++ uint32_t addr_mapped; /*!< The mapped memory adddress to read */ ++ uint32_t shift; /*!< the bits to shitf */ ++ uint32_t size; /*!< size of bits */ ++ uint32_t value; /*!< value of the data*/ ++ uint32_t repeat; /*!< set repeat times*/ ++ uint32_t flag; /*!< reserved for future */ ++}PPA_SET_MEM_INFO; ++ ++/*! ++ \brief This is the data structure to set the memory value for IOCTL. ++*/ ++typedef PPA_SET_MEM_INFO PPA_CMD_SET_MEM_INFO; ++#endif ++ ++/*! ++ \brief This is the data structure to get the maximum entries, like lan/wan/mc/bridging ++*/ ++typedef struct ++{ ++ uint32_t max_lan_entries; /*!< Maximum LAN session entries */ ++ uint32_t max_wan_entries; /*!< Maximum WAN session entries */ ++ uint32_t max_lan_collision_entries; /*!< Maximum LAN session entries */ ++ uint32_t max_wan_collision_entries; /*!< Maximum WAN session entries */ ++ uint32_t max_mc_entries; /*!< Maximum Multicast session entries */ ++ uint32_t max_bridging_entries;/*!< Maximum Bridge session entries */ ++ uint32_t max_ipv6_addr_entries; /*!< Maximum IPV6 address entries */ ++ uint32_t max_fw_queue; /*!< Maximum PPE FW queue number */ ++ uint32_t max_6rd_entries; /*! ++#endif ++ ++ ++#endif // __IFX_PPA_API_H__20081031_1913__ ++ +diff --git a/include/net/ifx_ppa_api_common.h b/include/net/ifx_ppa_api_common.h +new file mode 100644 +index 0000000..5ede8b4 +--- /dev/null ++++ b/include/net/ifx_ppa_api_common.h +@@ -0,0 +1,47 @@ ++#ifndef __IFX_PPA_API_COMMON_H__20100203__1740__ ++#define __IFX_PPA_API_COMMON_H__20100203__1740__ ++ ++/******************************************************************************* ++** ++** FILE NAME : ifx_ppa_api_common.h ++** PROJECT : PPA ++** MODULES : PPA Common header file ++** ++** DATE : 3 NOV 2008 ++** AUTHOR : Xu Liang ++** DESCRIPTION : PPA Common Header File ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3; 85579 Neubiberg, Germany ++** ++** For licensing information, see the file 'LICENSE' in the root folder of ++** this software module. ++** ++** HISTORY ++** $Date $Author $Comment ++** 03 NOV 2008 Xu Liang Initiate Version ++*******************************************************************************/ ++ ++#define NO_DOXY 1 ++ ++#ifndef CONFIG_IFX_PPA_DSLITE //if not defined in kernel's .configure file, then use local's definition ++#define CONFIG_IFX_PPA_DSLITE 1 ++#endif ++ ++#ifndef CONFIG_IFX_PPA_MFE //if not defined in kernel's .configure file, then use local's definition ++#define CONFIG_IFX_PPA_MFE 0 ++#endif ++ ++ /*force dynamic ppe driver's module parameter */ ++#define IFX_PPA_DP_DBG_PARAM_ENABLE 1 //for PPA automation purpose. for non-linux os porting, just disable it ++ ++#if IFX_PPA_DP_DBG_PARAM_ENABLE ++ extern int ifx_ppa_drv_dp_dbg_param_enable; ++ extern int ifx_ppa_drv_dp_dbg_param_ethwan; ++ extern int ifx_ppa_drv_dp_dbg_param_wanitf; ++ extern int ifx_ppa_drv_dp_dbg_param_ipv6_acc_en; ++ extern int ifx_ppa_drv_dp_dbg_param_wanqos_en; ++#endif // end of IFX_PPA_DP_DBG_PARAM_ENABLE ++ ++#endif ++ +diff --git a/include/net/ifx_ppa_api_directpath.h b/include/net/ifx_ppa_api_directpath.h +new file mode 100644 +index 0000000..919342d +--- /dev/null ++++ b/include/net/ifx_ppa_api_directpath.h +@@ -0,0 +1,301 @@ ++#ifndef __IFX_PPA_API_DIRECTPATH_H__20081119_1144__ ++#define __IFX_PPA_API_DIRECTPATH_H__20081119_1144__ ++ ++ ++ ++/******************************************************************************* ++** ++** FILE NAME : ifx_ppa_api_directpath.h ++** PROJECT : PPA ++** MODULES : PPA API (Routing/Bridging Acceleration APIs) ++** ++** DATE : 19 NOV 2008 ++** AUTHOR : Xu Liang ++** DESCRIPTION : PPA Protocol Stack Hook API Directpath Functions Header ++** File ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3; 85579 Neubiberg, Germany ++** ++** For licensing information, see the file 'LICENSE' in the root folder of ++** this software module. ++** ++** HISTORY ++** $Date $Author $Comment ++** 19 NOV 2008 Xu Liang Initiate Version ++*******************************************************************************/ ++/*! \file ifx_ppa_api_directpath.h ++ \brief This file contains: PPA direct path api. ++*/ ++ ++ ++ ++#include ++ ++ ++ ++/* ++ * #################################### ++ * Data Type ++ * #################################### ++ */ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++/* ++ * Directpath API Flags ++ */ ++/*! ++ \brief PPA_F_DIRECTPATH_REGISTER ++*/ ++#define PPA_F_DIRECTPATH_REGISTER 0x00100000 /*!< Directpath register flag*/ ++ ++/*! ++ \brief PPA_F_DIRECTPATH_CORE1 ++*/ ++#define PPA_F_DIRECTPATH_CORE1 0x00200000 /*!< Directpath flag: run in CPU Core 1*/ ++/*! ++ \brief PPA_F_DIRECTPATH_ETH_IF ++*/ ++#define PPA_F_DIRECTPATH_ETH_IF 0x00400000 /*!< Directpath flag: Ethernet type*/ ++ ++/* ++ * Directpath Internal Flags ++ */ ++ /*! ++ \brief PPE_DIRECTPATH_DATA_ENTRY_VALID ++*/ ++#define PPE_DIRECTPATH_DATA_ENTRY_VALID (1 << 31) /*!< define flag */ ++ /*! ++ \brief PPE_DIRECTPATH_DATA_RX_ENABLE ++*/ ++#define PPE_DIRECTPATH_DATA_RX_ENABLE (1 << 0) /*!< define flag */ ++ /*! ++ \brief PPE_DIRECTPATH_ETH ++*/ ++#define PPE_DIRECTPATH_ETH (1 << 4) /*!< define flag */ ++ /*! ++ \brief PPE_DIRECTPATH_CORE0 ++*/ ++#define PPE_DIRECTPATH_CORE0 (1 << 8) /*!< define flag */ ++ /*! ++ \brief PPE_DIRECTPATH_CORE1 ++*/ ++#define PPE_DIRECTPATH_CORE1 (1 << 9) /*!< define flag */ ++ /*! ++ \brief PPE_DIRECTPATH_ITF_TYPE_MASK ++*/ ++#define PPE_DIRECTPATH_ITF_TYPE_MASK (PPE_DIRECTPATH_ETH) /*!< define flag */ ++ /*! ++ \brief PPE_DIRECTPATH_CORE_MASK ++*/ ++#define PPE_DIRECTPATH_CORE_MASK (PPE_DIRECTPATH_CORE0 | PPE_DIRECTPATH_CORE1) /*!< define flag */ ++ /*! ++ \brief PPE_DIRECTPATH_MASK ++*/ ++#define PPE_DIRECTPATH_MASK (PPE_DIRECTPATH_ITF_TYPE_MASK | PPE_DIRECTPATH_CORE_MASK) /*!< define flag */ ++ ++ ++/** \addtogroup PPA_API_DIRECTPATH */ ++/*@{*/ ++/*! \fn PPA_FP_STOP_TX_FN ++ \brief This is the definition for the PPA DirectPath Stop Transmit function callback used for flow control when transmitting ++ packets through the PPA DirectPath. The PPA DirectPath calls this hook to indicate to the device driver that it ++ cannot receive any more packets for transmission. ++ \param[in] dev The protocol stack network interface structure on which to signal Stop Tx for flow control ++ \return The return value can be any one of the following: \n ++ IFX_SUCCESS on sucess \n ++ IFX_FAILURE on error if the driver cannot handle flow control ++ \note This function must be provided by the CPU-bound interface driver and will be called by the PPA Directpath to pass ++ on frames directly to the driver for transmitting out of its interface. ++*/ ++typedef int32_t (*PPA_FP_STOP_TX_FN)(PPA_NETIF *dev); ++ ++/*! \fn PPA_FP_RESTART_TX_FN ++ \brief This is the definition for the PPA DirectPath Restart Transmit function callback used for flow control when ++ transmitting packets through the PPA DirectPath. The PPA DirectPath calls this hook to indicate to the device ++ driver that it is ready to receive packets for transmission after having asserted stop flow control using ++ PPA_FP_STOP_TX_FN. ++ \param[in] dev The protocol stack network interface structure on which to signal restart Tx for flow control. ++ \return The return value can be any one of the following: \n ++ IFX_SUCCESS on sucess \n ++ IFX_FAILURE on error if the driver cannot handle flow control ++ \note It is recommended for a device driver to use the PPA DirectPath flow control functions for efficient packet ++ processing. This callback must always be used in conjunction with the PPA_FP_STOP_TX_FN callback, i.e., ++ either both callbacks or none must be configure ++*/ ++typedef int32_t (*PPA_FP_RESTART_TX_FN)(PPA_NETIF *dev); ++/*! \fn PPA_FP_RX_FN ++ \brief This is the definition for the PPA DirectPath receive function callback that passes packet from PPA DirectPath to ++ the CPU bound driver. This callback is registered for the device with the PPA module by the device driver. This is required to allow the PPA acceleration layer to directly pass packets to the relevant device driver bypassing the protocol stack. It is also the only way for the PPA to deliver packets to drivers running on Core 1. ++ The packet buffer passed to the rx_fn callback will have the data pointer point to the start of Link layer header (i.e. Ethernet header). For eg., on Linux, skb->data will point to the Ethernet header. ++ \param[in] rxif PPA Receive interface pointer on which the packet is received. ++ \param[in] txif PPA Tx interface pointer to which the packet is transmitted. ++ \param[in] skb Pointer to SKB buffer received. ++ \param[in] len Length of packet frame. ++ \return The return value can be any one of the following: \n ++ IFX_SUCCESS on sucess. \n ++ IFX_FAILURE on error if the driver process the packet for some reason. ++ \note This function must be provided by the CPU-bound interface driver and will be called by the PPA Directpath to pass on frames directly to the driver for transmitting out of its interface. ++*/ ++typedef int32_t (*PPA_FP_RX_FN)(PPA_NETIF *rxif, PPA_NETIF *txif, PPA_BUF *skb, int32_t len); ++ ++/*@}*/ /*PPA_API_DIRECTPATH */ ++ ++ ++/** \addtogroup PPA_API_DIRECTPATH */ ++/*@{*/ ++ ++/*! ++ \brief This is the data structure for the PPA DirectPath device registration which provides the necessary callback ++ registration for receiving packets from PPA DirectPath to the driver for transmit, and for flow control to be asserted ++ by the PPA DirectPath for packets from the driver to the PPA DirectPath. ++*/ ++typedef struct { ++ PPA_FP_STOP_TX_FN stop_tx_fn; /*!< Pointer to the Driver Stop Tx function callback. Providing a NULL pointer disables the callback functionality. */ ++ PPA_FP_RESTART_TX_FN start_tx_fn; /*!< Pointer to the Driver Restart Tx function callback. Providing a NULL pointer disables the callback functionality.*/ ++ PPA_FP_RX_FN rx_fn; /*!< Device Receive Function callback for packets. Setting a value of NULL pointer disables Receive callback for the device */ ++} PPA_DIRECTPATH_CB; ++ ++/* ++ * Internal Structure of directpath ++ */ ++/*! ++ \brief This is the data structure for the PPA DirectPath device status ++*/ ++struct ppe_directpath_data { ++ PPA_DIRECTPATH_CB callback; /*!< Callback Pointer to PPA_DIRECTPATH_CB */ ++ PPA_NETIF *netif; /*!< pointer to PPA_NETIF*/ ++ uint32_t ifid; /*!< directpath interface id */ ++ uint8_t mac[(PPA_ETH_ALEN + sizeof(uint32_t) - 1) / sizeof(uint32_t) * sizeof(uint32_t)]; /*!< interface mac address */ ++ PPA_BUF *skb_list; /*!< the directpath interface's skb list */ ++ uint32_t skb_list_len; /*!< the skb list length */ ++ uint32_t skb_list_size; /*!< the skb list size */ ++ uint32_t rx_fn_rxif_pkt; /*!< received packet counter */ ++ uint32_t rx_fn_txif_pkt; /*!< transmitted packet coutner */ ++ uint32_t tx_pkt; /*!< transmitted packet counter */ ++ uint32_t tx_pkt_dropped; /*!< dropped packet counter */ ++ uint32_t tx_pkt_queued; /*!< queued packet counter */ ++ uint32_t flags; /*!< bit 0 - directpath send valid, 31 - entry valid */ ++}; ++ ++ ++/*@}*/ /* PPA_API_DIRECTPATH */ ++ ++ ++/* ++ * #################################### ++ * Declaration ++ * #################################### ++ */ ++#ifdef NO_DOXY ++extern struct ppe_directpath_data g_ppe_directpath_data[]; ++#endif ++ ++/** \addtogroup PPA_API_DIRECTPATH */ ++/*@{*/ ++#ifdef CONFIG_IFX_PPA_API_DIRECTPATH ++/*! ++ \brief This function allows a device driver to register or deregister a network device to the PPA. ++ \param[out] if_id PPA specific Interface Identifier. It is currently a number between 0 to 7. This Id is returned by the PPA module. ++ \param[in] dev Pointer to the network device structure in the protocol stack. For e.g. pointer to a struct netdevice. ++ \param[in] pDirectpathCb Pointer to the DirectPath callback structure which provides the driver callbacks for rx_fn, stop_tx_fn and restart_tx_fn. This parameter is only available on new PPA API. ++ \param[in] flags Flag to indicate if device is being registered or deregistered. Valid values are:\n ++ - PPA_F_DIRECTPATH_DEREGISTER, if de-registering, zero otherwise \n ++ - PPA_F_DIRECTPATH_CORE1 if the driver for the network interface is running on Core 1 (i.e. 2nd CPU) \n ++ - PPA_F_DIRECTPATH_ETH_IF if the network interface is an Ethernet-like interface ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess \n ++ - IFX_FAILURE ++ \note ++*/ ++int32_t ifx_ppa_directpath_register_dev(uint32_t *if_id, PPA_NETIF *dev, PPA_DIRECTPATH_CB *pDirectpathCb, uint32_t flags); ++ ++/*! \brief This function allows the device driver to transmit a packet using the PPA DirectPath interface. The packet buffer passed to the function must have its "packet data" pointer set to the IP header with the Ethernet header/Link layer header etc. preceding the IP header (For e.g., on Linux skb->data points to IP header, and doing the appropriate skb_push() will allow skb->data to move backwards and point to Ethernet header). In other words, PPA Directpath must be able to access the full frame even though the packet buffer "points" to the IP header as required by the Linux netif_rx() function. ++ \param[in] rx_if_id Receive interface Id in the protocol stack. ++ \param[in] buf Pointer to the packet buffer structure of the stack for the packet which is to be transmitted. ++ \param[in] len Size of packet in bytes. ++ \param[in] flags Currently Reserved ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess \n ++ - IFX_FAILURE ++ \note The DirectPath Tx API can have internal "shortcut" path to the destination or fallback to passing the packet to the protocol stack. The aim is to insulate the device driver calling the API from such details. For Linux, the driver must call this function through the hook pointer where it passes packets to the network stack by calling the "netif_rx()" or "netif_receive_skb()" functions. \n ++ Note: The CPU-bound device driver is strongly recommended to call this API from tasklet mode (or equivalent non-interrupt context on non-Linux OS) and not from IRQ context for better system dynamics. ++*/ ++ int32_t ifx_ppa_directpath_send(uint32_t rx_if_id, PPA_BUF *buf, int32_t len, uint32_t flags); ++ ++/*! \brief This function allows the device driver to indicate to the PPA that it cannot receive any further packets from the latter. The device driver can call this function for flow control. ++ \param[in] if_id Interface Id for which to apply flow control. ++ \param[in] flags Currently Reserved ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess \n ++ - IFX_FAILURE ++ \note \n ++*/ ++ int32_t ifx_ppa_directpath_rx_stop(uint32_t if_id, uint32_t flags); ++ ++/*! \brief This function allows the device driver to indicate to the PPA that it can again receive packets from the latter. The device driver can call this function for flow control after it has called the "Rx Stop" function to halt supply of packets from the PPA. ++ \param[in] if_id Interface Id for which the driver requests the flow control action to restart transmission. ++ \param[in] flags Currently Reserved ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess \n ++ - IFX_FAILURE ++ \note It is recommended for a device driver to use the PPA DirectPath flow control functions for efficient packet processing. This function must be used in conjunction with the PPA_FP_STOP_TX_FN. \n ++*/ ++ int32_t ifx_ppa_directpath_rx_restart(uint32_t if_id, uint32_t flags); ++ ++/*! \brief This function maps the PPA Interface Id to Protocol stack interface structure. ++ \param[in] if_id PPA Interface Identifier. ++ \return The return value can be any one of the following: \n ++ - Pointer to the interface structure in the protocol stack \n ++ - NULL ++ \note This API may not implemented on older PPA version. \n ++*/ ++ PPA_NETIF *ifx_ppa_get_netif_for_ppa_ifid(uint32_t if_id); ++ ++/*! \brief This function maps the Protocol stack interface structure to the PPA Interface Id. ++ \param[in] dev Pointer to the protocol stack network interface structure for the device. ++ \return The return value can be any one of the following: \n ++ - PPA Interface Identifier, if_id \n ++ - IFX_FAILUREPPA_NETIF. \n ++ \note This API may not implemented on older PPA version. \n ++*/ ++ int32_t ifx_ppa_get_ifid_for_netif(PPA_NETIF *dev); ++ ++/*! \brief This function is used to initialize the interation of ppe_directpath_data information ++ \param[in,out] ppos offset of current ppe_directpath_data, after call, its value will be changed to next offset ++ \param[out] info Buffer to store the ppe_directpath_data. ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS, if succeed \n ++ - IFX_FAILURE, if fail to get \n ++*/ ++ int32_t ppa_directpath_data_start_iteration(uint32_t *ppos, struct ppe_directpath_data **info); ++ ++/*! \brief This function is used to ge the next ppe_directpath_data information during its iteration ++ \param[in,out] ppos offset of ppe_directpath_data, after call, its value will be changed to next offset ++ \param[out] info Buffer to store the ppe_directpath_data. ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS, if succeed \n ++ - IFX_FAILURE, if fail to get \n ++*/ ++ int32_t ppa_directpath_data_iterate_next(uint32_t *ppos, struct ppe_directpath_data **info); ++ ++/*! \brief This function is used to stop ppe_directpath_data iteration ++ \return NULL ++*/ ++ void ppa_directpath_data_stop_iteration(void); ++ ++ /*! \brief This function is used to get directpath's ifid range ++ \param[out] p_start_ifid Buffer to store the directpath's start ifid ++ \param[out] p_end_ifid Buffer to store the directpath's end ifid ++ \return NULL\n ++*/ ++ void ppa_directpath_get_ifid_range(uint32_t *p_start_ifid, uint32_t *p_end_ifid); ++#endif ++ ++/* @}*/ /* PPA_API_DIRECTPATH */ ++ ++#endif // __IFX_PPA_API_DIRECTPATH_H__20081119_1144__ +diff --git a/include/net/ifx_ppa_hook.h b/include/net/ifx_ppa_hook.h +new file mode 100644 +index 0000000..41a9278 +--- /dev/null ++++ b/include/net/ifx_ppa_hook.h +@@ -0,0 +1,1150 @@ ++#ifndef __IFX_PPA_HOOK_H__20081103_1736__ ++#define __IFX_PPA_HOOK_H__20081103_1736__ ++ ++ ++ ++/****************************************************************************** ++** ++** FILE NAME : ifx_ppa_hook.h ++** PROJECT : PPA ++** MODULES : PPA Protocol Stack Hooks ++** ++** DATE : 3 NOV 2008 ++** AUTHOR : Xu Liang ++** DESCRIPTION : PPA Protocol Stack Hook Pointers Header File ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3; 85579 Neubiberg, Germany ++** ++** For licensing information, see the file 'LICENSE' in the root folder of ++** this software module. ++** ++** HISTORY ++** $Date $Author $Comment ++** 03 NOV 2008 Xu Liang Initiate Version ++*******************************************************************************/ ++/*! \file ifx_ppa_hook.h ++ \brief This file contains all exported HOOK API to linux Kernel and user space via ioctl API. ++*/ ++ ++ ++ ++#include ++ ++/** \addtogroup PPA_HOOK_API */ ++/*@{*/ ++ ++/* ++ * #################################### ++ * Declaration ++ * #################################### ++ */ ++ ++#ifdef __KERNEL__ ++ ++ ++/*! ++ \brief This command Initialize the PPA module and the embedded acceleration functions. ++ \param[in] info Pointer to the initialization info structure passed to the API. ++ \param[in] flag Reserved currently. ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS \n ++ - IFX_FAILURE ++ \note p_info can be passed NULL to the init function wherein default handling will be applied by the PPA. This includes the following behavior. \n ++ - Identifying one LAN interface (eth0) and one WAN interface (eth1) \n ++ - Disabling acceleration in both LAN to WAN and WAN to LAN directions \n ++ - IP header verification enabled \n ++ - TCP/UDP header verification enabled \n ++ - Drop on no hit disabled - pass packets on matching any accelerated session entry to Control CPU \n ++ - Drop Multicast packet on no hit disable \n ++ Please refer to the PPA_INIT_INFO data structure and its members for all the information that is passed to the PPA module on initialization. ++ Specifically, the LAN and WAN interface list can be populated with all possible interfaces of either type expected in the system even if these interfaces don't exist at the time of initialization. ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_init_fn)(PPA_INIT_INFO *info, uint32_t flag); ++#else ++extern int32_t ppa_hook_init_fn(PPA_INIT_INFO *info, uint32_t flag); ++#endif ++/*! ++ \brief This command un-Initialize the PPA module ++ \return void ++*/ ++#ifdef NO_DOXY ++extern void (*ppa_hook_exit_fn)(void); ++#else ++extern void ppa_hook_exit_fn(void); ++#endif ++ ++/*! ++ \brief This API exposes the PPA Enable / Disable API to userspace. ++ \param[in] lan_rx_ppa_enable Enable / Disable accelerated LAN to WAN path through PPA. \n ++ Valid values are:\n ++ IFX_ENABLED \n ++ IFX_DISABLED \n ++ \param[in] wan_rx_ppa_enable Enable / Disable accelerated WAN to LAN path through PPA. \n ++ Valid values are:\n ++ - IFX_ENABLED \n ++ - IFX_DISABLED \n ++ \param[in] flag Reserved currently. ++ ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS \n ++ - IFX_FAILURE ++ \note The LAN to WAN and WAN to LAN separate acceleration disable feature is a function of the acceleration module in the system. In some cases, it maybe only possible to complete disable / enable acceleration. ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_enable_fn)(uint32_t lan_rx_ppa_enable, uint32_t wan_rx_ppa_enable, uint32_t flag); ++#else ++extern int32_t ppa_hook_enable_fn(uint32_t lan_rx_ppa_enable, uint32_t wan_rx_ppa_enable, uint32_t flag); ++#endif ++/*! ++ \brief This API returns the current Enable / Disable status of the PPA to the caller. ++ \param[out] lan_rx_ppa_enable Enable / Disable accelerated LAN to WAN path through PPA. \n ++ Valid values are ++ IFX_ENABLED \n ++ IFX_DISABLED \n ++ \param[out] wan_rx_ppa_enable Enable / Disable accelerated WAN to LAN path through PPA. \n ++ Valid values are ++ - IFX_ENABLED \n ++ - IFX_DISABLED \n ++ \param[in] flag Reserved currently. ++ ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS \n ++ - IFX_FAILURE ++ \note This parameter is not available on older PPA version. ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_get_status_fn)(uint32_t *lan_rx_ppa_enable, uint32_t *wan_rx_ppa_enable, uint32_t flag); ++#else ++extern int32_t ppa_hook_get_status_fn(uint32_t *lan_rx_ppa_enable, uint32_t *wan_rx_ppa_enable, uint32_t flag); ++#endif ++/*! ++ \brief Add a PPA routing session entry ++ \param[in] skb Pointer to the packet buffer for which PPA session addition is to be done. ++ \param[in] p_session Points to the connection tracking session to which this packet belongs. It maybe passed as NULL in which case PPA will try to determine it using the PPA stack adaptation layer. ++ \param[in] flags Flags as valid for the PPA session Valid \n ++ values are one or more of: \n ++ - PPA_F_SESSION_BIDIRECTIONAL \n ++ - PPA_F_BRIDGED_SESSION \n ++ - PPA_F_STATIC_ENTRY \n ++ - PPA_F_DROP_PACKET \n ++ - PPA_F_SESSION_ORG_DIR \n ++ - PPA_F_SESSION_REPLY_DIR \n ++ - PPA_F_BEFORE_NAT_TRANSFORM \n ++ \return The return value can be any one of the following: \n ++ - IFX_PPA_SESSION_NOT_ADDED \n ++ - IFX_PPA_SESSION_ADDED \n ++ - IFX_PPA_SESSION_EXISTS \n ++ ++ \note Linux 2.4 Hook-up recommendation \n ++ Must be hooked into the stack before the PREROUTING and after the POSTROUTING hooks In ip_conntrack_in() function in file ip_conntrack_core.c, with the flag PPA_F_BEFORE_NAT_TRANSFORM specified. \n ++ 1) In ip_finish_output2(), the hook should be invoked after NAT transforms are applied and at the very beginning of function call. \n ++ Linux 2.6 Hook-up recommendation \n ++ Must be in netfilter IPV4 or IPV6 hook PREROUTRING and POSTROUTING hooks. In nf_conntrack_in for function which is common for both IPV4 and V6 connection tracking, PPA_F_BEFORE_NAT_TRANSFORM. In ip_finish_output2(), the hook should be invoked after NAT transforms are applied at netfilter POSTROUTING hooks and at the very beginning of function call. ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_session_add_fn)(PPA_BUF *skb, PPA_SESSION *p_session, uint32_t flags); ++#else ++extern int32_t ppa_hook_session_add_fn(PPA_BUF *skb, PPA_SESSION *p_session, uint32_t flags); ++#endif ++ ++/*! ++ \brief Del a PPA routing session entry ++ \param[in] p_session Points to the connection tracking session to which this packet belongs. It maybe passed as NULL in which case PPA will try to determine it using the PPA stack adaptation layer. ++ \param[in] flags Reserved currently. ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS \n ++ - IFX_FAILURE ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_session_del_fn)(PPA_SESSION *p_session, uint32_t flags); ++#else ++extern int32_t ppa_hook_session_del_fn(PPA_SESSION *p_session, uint32_t flags); ++#endif ++ ++/*! ++ \brief Modify an existing PPA session to allow handling for additional features like VLAN, DSCP and others. ++ \param[in] p_session PPA session id ++ \param[in] p_extra Extra parameters of PPA session ++ \param[in] flags Flags passed to modify session API to indicate which processing parameters are specified. Valid values are one or more of: ++ - PPA_F_SESSION_NEW_DSCP \n ++ - PPA_F_SESSION_VLAN \n ++ - PPA_F_MTU \n ++ ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS \n ++ - IFX_FAILURE \n ++ \note Linux 2.4 Hook-up recommendation \n ++ - Called in the stack on a per session basis to set additional handling like VLAN, DSCP and MTU parameters. \n ++ - One place to hook the call is after the function ppa_hook_session_add_fn() returns IFX_PPA_SESSION_ADDED. \n ++ - Needs to evaluate the settings for VLAN, DSCP, MTU etc which are required to be used for this session. These steps need to be written for the stack and supported functionality. \n ++ - Another place for hookup is in the Configuration routines of the individual features \n ++ - For example, for a VLAN configuration, go through the list of conntrack sessions, and call ppa_hook_session_modify_fn() for each session that is impacted by the change in configuration. \n ++ - If this step is not supported, then only sessions created after the configuration change will be affected. ++ \note Linux 2.6 Hook-up recommendation \n ++ Same as 2.4. ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_session_modify_fn)(PPA_SESSION *p_session, PPA_SESSION_EXTRA *p_extra, uint32_t flags); ++#else ++extern int32_t ppa_hook_session_modify_fn(PPA_SESSION *p_session, PPA_SESSION_EXTRA *p_extra, uint32_t flags); ++#endif ++ ++/*! ++ \brief Returns all the configured unicast PPA sessions ++ \param[out] pp_sessions Allocates and returns a pointer to an array of session data structures for all unicast sessions in PPA. \n Caller needs to free the memory after use. ++ \param[out] p_extra Allocates and returns a pointer to an array of session attributes structures for all unicast sessions in PPA.\n Caller needs to free the memory after use. ++ \param[out] p_num_entries Returns the number of session entries filled in the pp_sessions and pp_extra arrays. ++ \param[in] flags Reserved. ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS \n ++ - IFX_FAILURE ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_session_get_fn)(PPA_SESSION ***pp_sessions, PPA_SESSION_EXTRA **p_extra, int32_t *p_num_entries, uint32_t flags); ++#else ++extern int32_t ppa_hook_session_get_fn(PPA_SESSION ***pp_sessions, PPA_SESSION_EXTRA **p_extra, int32_t *p_num_entries, uint32_t flags); ++#endif ++ ++/*! ++ \brief Add, Modify and Delete PPA multicast group information like membership of interfaces to a multicast group address. ++ \param[in] ppa_mc_entry Pointer to multicast group entry. I ++ \param[in] flags Flags for the multicast group update operation. Valid values are:\n ++ PPA_F_DROP_PACKET: Drop packets with this multicast group address as destination. ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS \n ++ - IFX_FAILURE \n ++ ++ \note add or delete one or more interface(s) to a multicast group entry, the function ppa_hook_mc_group_update_fn() needs to be called, the PPA_MC_GROUP structure modified appropriately and passed to this function. \n ++ -> Linux 2.4 Hook-up recommendation \n ++ The function needs to be hooked up in the Linux kernel functions ipmr_mfc_add() and ipmr_mfc_del() in the IP stack multicast routing path. \n ++ For bridging path, hookup is required in the bridge forwarding path if IGMP snooping is implemented. It is also possible to make configuration entries from management interface path. ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_mc_group_update_fn)(PPA_MC_GROUP *ppa_mc_entry, uint32_t flags); ++#else ++extern int32_t ppa_hook_mc_group_update_fn(PPA_MC_GROUP *ppa_mc_entry, uint32_t flags); ++#endif ++ ++/*! ++ \brief This function gets the multicast group entry for the specified multicast group address. ++ \param[in] ip_mc_group IP multicast group address for which Multicast group information has to be returned. ++ \param[out] ppa_mc_entry Pointer to multicast group entry. Valid memory space to be passed by caller. ++ \param[in] flags Reserved for future ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS \n ++ - IFX_FAILURE \n ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_mc_group_get_fn)(IP_ADDR_C ip_mc_group, PPA_MC_GROUP *ppa_mc_entry, uint32_t flags); ++#else ++extern int32_t ppa_hook_mc_group_get_fn(IP_ADDR_C ip_mc_group, PPA_MC_GROUP *ppa_mc_entry, uint32_t flags); ++#endif ++ ++/*! ++ \brief This function modifies an existing multicast group entry for additional functionality like VLAN support ++ \param[in] ip_mc_group Pointer to IP multicast group address for which additional functionality needs to be configured. ++ \param[in] ppa_mc_entry Pointer to PPA MC group entry. ++ \param[in] p_extra Pointer to additional MC entry functional configuration. Currently, only VLAN configuration is supported ++ \param[in] flags Reserved for future ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS if entry exists for multicast group address \n ++ - IFX_FAILURE otherwise \n ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_mc_entry_modify_fn)(IP_ADDR_C ip_mc_group, PPA_MC_GROUP *ppa_mc_entry, PPA_SESSION_EXTRA *p_extra, uint32_t flags); ++#else ++extern int32_t ppa_hook_mc_entry_modify_fn(IP_ADDR_C ip_mc_group, PPA_MC_GROUP *ppa_mc_entry, PPA_SESSION_EXTRA *p_extra, uint32_t flags); ++#endif ++ ++/*! ++ \brief This function returns an existing multicast group entry with its additional functionality configuration like VLAN support. ++ \param[in] ip_mc_group Pointer to IP multicast group address for which additional functionality needs to be configured. ++ \param[in] p_extra Pointer to additional MC entry functional configuration. Currently, only VLAN configuration is supported ++ \param[in] flags Reserved for future ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS if entry exists for multicast group address \n ++ - IFX_FAILURE otherwise \n ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_mc_entry_get_fn)(IP_ADDR_C ip_mc_group, PPA_SESSION_EXTRA *p_extra, uint32_t flags); ++#else ++extern int32_t ppa_hook_mc_entry_get_fn(IP_ADDR_C ip_mc_group, PPA_SESSION_EXTRA *p_extra, uint32_t flags); ++#endif ++ ++/*! ++ \brief This function is used to get a multicast source interface ++ \param[in] buf A skb buffer ++ \param[in] netif The interface pointer which received the ip packet. If NULL, it can be got from PPA_BUF *. ++ ++ \return The return value can be any one of the following: \n ++ - IFX_PPA_SESSION_ADDED if if entry exists for multicast group address \n ++ - IFX_PPA_SESSION_EXISTS if already added ++ - IFX_PPA_SESSION_NOT_ADDED otherwise \n ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_multicast_pkt_srcif_add_fn)(PPA_BUF *buf, PPA_NETIF *netif); ++#else ++extern int32_t ppa_hook_multicast_pkt_srcif_add_fn(PPA_BUF *buf, PPA_NETIF *netif); ++#endif ++ ++/*! ++ \brief Checks if the "accelerated" PPA session should be timed out due to inactivity. ++ \param[in] p_session Pointer to PPA unicast or multicast session. ++ \return The return value can be any one of the following: \n ++ - IFX_TIMEOUT if the PPA session inactivity timer has expired \n ++ - IFX_HIT if the PPA session has been active ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_inactivity_status_fn)(PPA_U_SESSION *p_session); ++#else ++extern int32_t ppa_hook_inactivity_status_fn(PPA_U_SESSION *p_session); ++#endif ++ ++/*! ++ \brief Update the session inactivity timeout for a PPA session as per the session inactivity configuration in the protocol stack. ++ \param[in] p_session Pointer to PPA unicast or multicast session. ++ \param[in] timeout Timeout value for session inactivity in seconds. ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS \n ++ - IFX_FAILURE \n ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_set_inactivity_fn)(PPA_U_SESSION *p_session, int32_t timeout); ++#else ++extern int32_t ppa_hook_set_inactivity_fn(PPA_U_SESSION *p_session, int32_t timeout); ++#endif ++ ++/*! ++ \brief Add or update a MAC entry and its source ethernet port information in the PPA bridge table. ++ \param[in] mac_addr Pointer to MAC address to add to PPA bridge table. ++ \param[in] netif Pointer to PPA net interface which is the source of the MAC address. ++ \param[in] flags Valid values are: ++ - PPA_F_BRIDGE_LOCAL - traffic is destined for local termination. ++ - PPA_F_STATIC_ENTRY - static MAC address entry in the PPA bridge table. It will not be aged out. ++ - PPA_F_DROP_PACKET - firewall action. Always drop packets with this MAC destination. ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS \n ++ - IFX_FAILURE \n ++ \note Static MAC entry updates and MAC address drop filters can be configured from userspace. For dynamic entries, the function must be hooked from bridging code where new entries are inserted into bridge mac table (or forwarding database, fdb). ++ Linux 2.4 Hook-up recommendation \n ++ Hook in kernel function br_fdb_insert() in net/bridge/br_fdb.c. For Linux bridging code, the netif is given by fdb->dst->dev field where fdb points to a MAC entry. ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_bridge_entry_add_fn)(uint8_t *mac_addr, PPA_NETIF *netif, uint32_t flags); ++#else ++extern int32_t ppa_hook_bridge_entry_add_fn(uint8_t *mac_addr, PPA_NETIF *netif, uint32_t flags); ++#endif ++ ++/*! ++ \brief Delete a MAC entry from PPA Bridge table since the MAC entry is aged out or administratively triggered. ++ \param[in] mac_addr Pointer to MAC address to delete from PPA bridge table. ++ \param[in] flags Reserved ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS \n ++ - IFX_FAILURE ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_bridge_entry_delete_fn)(uint8_t *mac_addr, uint32_t flags); ++#else ++extern int32_t ppa_hook_bridge_entry_delete_fn(uint8_t *mac_addr, uint32_t flags); ++#endif ++ ++/*! ++ \brief Get latest packet arriving time for the specified MAC address entry. This is used for aging out decisions for the MAC entry. ++ \param[in] mac_addr Pointer to MAC address whose entry hit time is being queried ++ \param[out] p_hit_time Provides the latest packet arriving time in seconds from system bootup. ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS \n ++ - IFX_FAILURE ++ \note Linux 2.4 Hook-up recommendation \n ++ This API can be hooked in function br_fdb_cleanup(). In Linux, there is a kernel thread (br_fdb_cleanup) polling each entry in the MAC table and removes entries without traffic for a long time. ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_bridge_entry_hit_time_fn)(uint8_t *mac_addr, uint32_t *p_hit_time); ++#else ++extern int32_t ppa_hook_bridge_entry_hit_time_fn(uint8_t *mac_addr, uint32_t *p_hit_time); ++#endif ++ ++/*! ++ \brief Check if a PPA Bridge entry should be aged out due to inactivity as per the aging time configured by function \ref ppa_hook_set_bridge_entry_timeout_fn. ++ \param[in] mac_addr Pointer to MAC address whose entry hit time is being queried ++ \return The return value can be any one of the following: \n ++ - IFX_PPA_TIMEOUT if entry should be aged out \n ++ - IFX_PPA_HIT if entry should not be aged out ++ \note Linux 2.4 Hook-up recommendation \n ++ This API can be hooked in function has_expired() in br_fdb.c. \n ++ Note that the function pair of ppa_hook_bridge_entry_inactivity_status_fn and ppa_hook_set_bridge_entry_timeout_fn is an alternate aging mechanism to the use of function ppa_hook_bridge_entry_hit_time_fn. ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_bridge_entry_inactivity_status_fn)(uint8_t *mac_addr); ++#else ++extern int32_t ppa_hook_bridge_entry_inactivity_status_fn(uint8_t *mac_addr); ++#endif ++ ++/*! ++ \brief Set the PPA bridge entry inactivity timeout in seconds. ++ \param[in] mac_addr Pointer to MAC address whose entry hit time is being set ++ \param[in] timeout Timeout in seconds for inactivity timeout. ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess \n ++ - IFX_FAILURE on error ++ \note This function should be called immediately after ppa_hook_bridge_entry_add_fn() and whenever timeout needs to be changed by bridge stack. \n ++ Linux 2.4 Hook-up recommendation \n For Linux, the timeout is equal to the bridge aging time and can be called from the function br_fdb_insert(). ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_set_bridge_entry_timeout_fn)(uint8_t *mac_addr, uint32_t timeout); ++#else ++extern int32_t ppa_hook_set_bridge_entry_timeout_fn(uint8_t *mac_addr, uint32_t timeout); ++#endif ++ ++/*! \brief This fucntion will enable bridging hook ?? ++ \param[in] f_enable 0--disable, 1--enable ++ \param[in] flags for future usage. ++ \return The following value: \n ++ - IFX_SUCCESS if sucessfully \n ++ - IFX_FAILURE otherwise. ++ \note It it used to enable/disable PPA bridging mac address learning. Normally it is called by network stack which want to enable/disable mac address learning. ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_bridge_enable_fn)(uint32_t f_enable, uint32_t flags); ++#else ++extern int32_t ppa_hook_bridge_enable_fn(uint32_t f_enable, uint32_t flags); ++#endif ++ ++/*! ++ \brief This function configures PPA Bridge Interface VLAN configuration behaviour. This includes functionality like whether the bridge is VLAN aware. ++ \param[in] netif Pointer to network interface structure. ++ \param[in] vlan_tag_control Pointer to VLAN Tagging control structure. This specifies whether VLAN tag, untag, replace should be carried out for the interface. ++ \param[in] vlan_cfg Pointer to network interface structure. ++ \param[in] flags Reserved. ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess \n ++ - IFX_FAILURE on error ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_set_bridge_if_vlan_config_fn)(PPA_NETIF *netif, PPA_VLAN_TAG_CTRL *vlan_tag_control, PPA_VLAN_CFG *vlan_cfg, uint32_t flags); ++#else ++extern int32_t ppa_hook_set_bridge_if_vlan_config_fn(PPA_NETIF *netif, PPA_VLAN_TAG_CTRL *vlan_tag_control, PPA_VLAN_CFG *vlan_cfg, uint32_t flags); ++#endif ++ ++/*! ++ \brief This function gets the PPA Bridge Interface VLAN configuration. This includes functionality like whether the bridge is VLAN aware. ++ \param[in] netif Pointer to network interface structure ++ \param[out] vlan_tag_control Pointer to VLAN Tagging control structure. This specifies whether VLAN tag, untag, replace should be carried out for the interface. ++ \param[out] vlan_cfg Pointer to network interface structure. ++ \param[in] flags Reserved. ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess \n ++ - IFX_FAILURE on error ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_get_bridge_if_vlan_config_fn)(PPA_NETIF *netif, PPA_VLAN_TAG_CTRL *vlan_tag_control, PPA_VLAN_CFG *vlan_cfg, uint32_t flags); ++#else ++extern int32_t ppa_hook_get_bridge_if_vlan_config_fn(PPA_NETIF *netif, PPA_VLAN_TAG_CTRL *vlan_tag_control, PPA_VLAN_CFG *vlan_cfg, uint32_t flags); ++#endif ++ ++/*! ++ \brief This function configures filters for VLAN tag/untag/retag actions in the PPA Bridge functionality. ++ \param[in] vlan_match_field Pointer to VLAN match filter that specifies the match criteria. ++ \param[in] vlan_info Pointer to VLAN Info structure that specifies what VLAN tag action needs to be taken for traffic matching the filter ++ \param[in] flags Reserved. ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess \n ++ - IFX_FAILURE on error ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_vlan_filter_add_fn)(PPA_VLAN_MATCH_FIELD *vlan_match_field, PPA_VLAN_INFO *vlan_info, uint32_t flags); ++#else ++extern int32_t ppa_hook_vlan_filter_add_fn(PPA_VLAN_MATCH_FIELD *vlan_match_field, PPA_VLAN_INFO *vlan_info, uint32_t flags); ++#endif ++ ++/*! ++ \brief This function removes filters for VLAN tag/untag/retag actions in the PPA Bridge functionality. ++ \param[in] vlan_match_field Pointer to VLAN match filter that specifies the match criteria. ++ \param[in] vlan_info Pointer to VLAN Info structure that specifies what VLAN tag action needs to be taken for traffic matching the filter ++ \param[in] flags Reserved. ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess \n ++ - IFX_FAILURE on error ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_vlan_filter_del_fn)(PPA_VLAN_MATCH_FIELD *vlan_match_field, PPA_VLAN_INFO *vlan_info, uint32_t flags); ++#else ++extern int32_t ppa_hook_vlan_filter_del_fn(PPA_VLAN_MATCH_FIELD *vlan_match_field, PPA_VLAN_INFO *vlan_info, uint32_t flags); ++#endif ++ ++/*! ++ \brief This function returns all configured filters for VLAN tag/untag/retag actions in the PPA Bridge functionality. ++ \param[out] num_filters Pointer to number of VLAN filters returned by the PPA. ++ \param[out] vlan_filters Pointer to allocated array of VLAN filters.Caller needs to free the allocated memory ++ \param[in] flags Reserved. ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess \n ++ - IFX_FAILURE on error ++ \note This function is not implemented currently. ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_vlan_filter_get_all_fn)(int32_t *num_filters, PPA_VLAN_FILTER_CONFIG *vlan_filters, uint32_t flags); ++#else ++extern int32_t ppa_hook_vlan_filter_get_all_fn(int32_t *num_filters, PPA_VLAN_FILTER_CONFIG *vlan_filters, uint32_t flags); ++#endif ++ ++/*! ++ \brief This function removes all filters for VLAN tag/untag/retag actions in the PPA Bridge functionality. ++ \param[in] flags Reserved. ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess \n ++ - IFX_FAILURE on error ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_vlan_filter_del_all_fn)(uint32_t flags); ++#else ++extern int32_t ppa_hook_vlan_filter_del_all_fn(uint32_t flags); ++#endif ++ ++/*! ++ \brief Returns interface statistics from the PPA which is a subset of IfTable in SNMP MIB-II standard. ++ \param[in] ifname Pointer to the interface name ++ \param[out] p_stats Pointer to the Statistics data structure of the interface. ++ \param[in] flags Reserved. ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess \n ++ - IFX_FAILURE on error ++ \note This function is provided to allow the fastpath packet and byte counters to be accounted in stack interface statistics. This function is only implemented for D4 firmware. ++ ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_get_if_stats_fn)(PPA_IFNAME *ifname, PPA_IF_STATS *p_stats, uint32_t flags); ++#else ++extern int32_t ppa_hook_get_if_stats_fn(PPA_IFNAME *ifname, PPA_IF_STATS *p_stats, uint32_t flags); ++#endif ++ ++ ++/*! ++ \brief Returns per interface statistics kept by the PPA which is a superset of the per Interface statistics above. This provides, for example, fastpath routed and bridged statistics. ++ \param[in] ifname Pointer to the interface name ++ \param[out] p_stats Pointer to the Statistics data structure of the interface. ++ \param[in] flags Reserved. ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess \n ++ - IFX_FAILURE on error ++ \note This function is only implemented for D4 firmware. ++ ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_get_accel_stats_fn)(PPA_IFNAME *ifname, PPA_ACCEL_STATS *p_stats, uint32_t flags); ++#else ++extern int32_t ppa_hook_get_accel_stats_fn(PPA_IFNAME *ifname, PPA_ACCEL_STATS *p_stats, uint32_t flags); ++#endif ++ ++/*! ++ \brief Configures MAC address of the Interface (if it is an Ethernet-like interface). ++ \param[in] ifname Pointer to the interface name ++ \param[in] mac_addr Pointer to the MAC address of the interface which is to be set. ++ \param[in] flags Reserved. ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess \n ++ - IFX_FAILURE on error ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_set_if_mac_address_fn)(PPA_IFNAME *ifname, uint8_t *mac_addr, uint32_t flags); ++#else ++extern int32_t ppa_hook_set_if_mac_address_fn(PPA_IFNAME *ifname, uint8_t *mac_addr, uint32_t flags); ++#endif ++ ++/*! ++ \brief Returns MAC address of the Interface (if it is an Ethernet-like interface). ++ \param[in] ifname Pointer to the interface name ++ \param[out] mac_addr Pointer to the MAC address of the interface. ++ \param[in] flags Reserved. ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess \n ++ - IFX_FAILURE on error ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_get_if_mac_address_fn)(PPA_IFNAME *ifname, uint8_t *mac_addr, uint32_t flags); ++#else ++extern int32_t ppa_hook_get_if_mac_address_fn(PPA_IFNAME *ifname, uint8_t *mac_addr, uint32_t flags); ++#endif ++ ++/*! ++ \brief Adds a new interface to the PPA interface list. The new interface maybe a LAN interface or a WAN interface ++ \param[in] ifinfo Pointer to the interface info structure ++ \param[in] flags Flag indicating whether interface is LAN flags or WAN. Valid value is: \n ++ PPA_F_LAN_IF if LAN interface ++ ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess \n ++ - IFX_FAILURE on error ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_add_if_fn)(PPA_IFINFO *ifinfo, uint32_t flags); ++#else ++extern int32_t ppa_hook_add_if_fn(PPA_IFINFO *ifinfo, uint32_t flags); ++#endif ++ ++/*! ++ \brief Deletes an interface from the PPA interface list. The new interface maybe a LAN interface or a WAN interface ++ \param[in] ifinfo Pointer to the interface info structure ++ \param[in] flags Flag indicating whether interface is LAN flags or WAN. Valid value is: \n ++ PPA_F_LAN_IF if LAN interface ++ ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess \n ++ - IFX_FAILURE on error ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_del_if_fn)(PPA_IFINFO *ifinfo, uint32_t flags); ++#else ++extern int32_t ppa_hook_del_if_fn(PPA_IFINFO *ifinfo, uint32_t flags); ++#endif ++ ++/*! ++ \brief Gets the list of LAN or WAN interfaces from the PPA interface list ++ \param[in] num_ifs Pointer to number of interface elements returned by the API ++ \param[out] ifinfo ointer to the allocated array of interface info structures. Caller has to free the pointer returned ++ \param[in] flags Flag indicating whether interface is LAN flags or WAN. Valid value is: \n ++ PPA_F_LAN_IF if LAN interface ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess \n ++ - IFX_FAILURE on error ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_get_if_fn)(int32_t *num_ifs, PPA_IFINFO **ifinfo, uint32_t flags); ++#else ++extern int32_t ppa_hook_get_if_fn(int32_t *num_ifs, PPA_IFINFO **ifinfo, uint32_t flags); ++#endif ++ ++/*! ++ \brief This function allows a device driver to register or deregister a network device to the PPA ++ \param[out] if_id PPA specific Interface Identifier. It is currently a number between 0 to 7. This Id is returned by the PPA module ++ \param[in] dev Pointer to the network device structure in the protocol stack. For eg. pointer to a struct netdevice ++ \param[in] pDirectpathCb Pointer to the DirectPath callback structure which provides the driver callbacks for rx_fn, stop_tx_fn and restart_tx_fn. ++ ++ \param[in] flags Flag to indicate if device is being registered or deregisterd. Valid values are: \n ++ PPA_F_DIRECTPATH_DEREGISTER, if de-registering, zero otherwise ++ PPA_F_DIRECTPATH_CORE1 if the driver for the network interface is running on Core 1 (i.e. 2nd CPU) ++ PPA_F_DIRECTPATH_ETH_IF if the network interface is an Ethernet-like interface ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess \n ++ - IFX_FAILURE on error ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_directpath_register_dev_fn)(uint32_t *if_id, PPA_NETIF *dev, PPA_DIRECTPATH_CB *pDirectpathCb, uint32_t flags); ++#else ++extern int32_t ppa_hook_directpath_register_dev_fn(uint32_t *if_id, PPA_NETIF *dev, PPA_DIRECTPATH_CB *pDirectpathCb, uint32_t flags); ++#endif ++ ++/*! ++ \brief This function allows the device driver to transmit a packet using the PPA DirectPath interface. The packet buffer ++ passed to the function must have its packet data pointer set to the IP header with the Ethernet ++ header/Link layer header etc preceding the IP header (For eg., on Linux skb->data points to IP header, and ++ doing the appropriate skb_push() will allow skb->data to move backwards and point to Ethernet header). ++ In other words, PPA Directpath must be able to access the full frame even though the packet buffer points to the ++ IP header as required by the Linux netif_rx() function. ++ \param[in] rx_if_id Receive interface Id in the protocol stack ++ \param[in] buf Pointer to the packet buffer structure of the stack for the packet which is to be transmitted ++ \param[in] len Size of packet in bytes ++ \param[in] flags reserved ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess \n ++ - IFX_FAILURE on error ++ \note The DirectPath Tx API can have internal shortcut path to the destination or fallback to passing the packet to the ++ protocol stack. The aim is to insulate the device driver calling the API from such details. \n ++ For Linux, the driver must call this function through the hook pointer where it passes packets to the network stack by calling the netif_rx() or netif_receive_skb() functions. \n ++ Note : The CPU-bound device driver is strongly recommended to call this API from tasklet mode (or equivalent non-interrupt context on non-Linux OS) and not from IRQ context for better system dynamics. ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_directpath_send_fn)(uint32_t rx_if_id, PPA_BUF *buf, int32_t len, uint32_t flags); ++#else ++extern int32_t ppa_hook_directpath_send_fn(uint32_t rx_if_id, PPA_BUF *buf, int32_t len, uint32_t flags); ++#endif ++ ++/*! ++ \brief This function allows the device driver to indicate to the PPA that it cannot receive any further packets from the ++ latter. The device driver can call this function for flow control. ++ \param[in] if_id interface Id for which to apply flow control ++ \param[in] flags reserved ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess\n ++ - IFX_FAILURE on fail\n ++ - IFX_EINVAL if the interface not exist ++ \note It is recommended for a device driver to use the PPA DirectPath flow control functions for efficient packet processing. ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_directpath_rx_stop_fn)(uint32_t if_id, uint32_t flags); ++#else ++extern int32_t ppa_hook_directpath_rx_stop_fn(uint32_t if_id, uint32_t flags); ++#endif ++ ++/*! ++ \brief This function allows the device driver to indicate to the PPA that it can again receive packets from the latter. The ++ device driver can call this function for flow control after it has called the Rx Stop function to halt supply of packets ++ from the PPA. ++ \param[in] if_id interface Id for which the driver requests the flow control action to restart transmission. ++ \param[in] flags reserved ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on sucess\n ++ - IFX_FAILURE on fail\n ++ - IFX_EINVAL if the interface not exist ++ \note It is recommended for a device driver to use the PPA DirectPath flow control functions for efficient packet processing. This function must be used in conjunction with the PPA_FP_STOP_TX_FN. ++ ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_directpath_rx_restart_fn)(uint32_t if_id, uint32_t flags); ++#else ++extern int32_t ppa_hook_directpath_rx_restart_fn(uint32_t if_id, uint32_t flags); ++#endif ++ ++/*! ++ \brief This function maps the PPA Interface Id to Protocol stack interface structure. ++ \param[in] if_id PPA Interface Identifier, if_id ++ \return The return value can be any one of the following: \n ++ - Pointer to the interface structure in the protocol stack \n ++ - NULL ++*/ ++#ifdef NO_DOXY ++extern PPA_NETIF *(*ppa_hook_get_netif_for_ppa_ifid_fn)(uint32_t if_id); ++#else ++extern PPA_NETIF *ppa_hook_get_netif_for_ppa_ifid_fn(uint32_t if_id); ++#endif ++ ++/*! ++ \brief This function maps the Protocol stack interface structure to the PPA Interface Id. ++ \param[in] netif Pointer to the protocol stack network interface structure for the device ++ \return The return value can be any one of the following: \n ++ - PPA Interface Identifier, if_id \n ++ - IFX_FAILURE ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_get_ifid_for_netif_fn)(PPA_NETIF *netif); ++#else ++extern int32_t ppa_hook_get_ifid_for_netif_fn(PPA_NETIF *netif); ++#endif ++ ++/*! ++ \brief This function add a vlan range for wan interface in mixed mode ++ \param[in] vlan_range Pointer to vlan id range ++ \param[in] flags reserved ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on success\n ++ - IFX_FAILURE on fail\n ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_wan_mii0_vlan_range_add_fn)(PPA_VLAN_RANGE *vlan_range, uint32_t flags) ; ++#else ++extern int32_t ppa_hook_wan_mii0_vlan_range_add_fn(PPA_VLAN_RANGE *vlan_range, uint32_t flags) ; ++#endif ++ ++/*! ++ \brief This function remove a vlan range from wan interface in mixed mode/RAN ++ ++ \param[in] vlan_range Pointer to vlan id range ++ \param[in] flags reserved ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on success\n ++ - IFX_FAILURE on fail\n ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_wan_mii0_vlan_range_del_fn)(PPA_VLAN_RANGE *vlan_range, int32_t flags); ++#else ++extern int32_t ppa_hook_wan_mii0_vlan_range_del_fn(PPA_VLAN_RANGE *vlan_range, int32_t flags); ++#endif ++ ++/*! ++ \brief This function get a vlan range list from wan interface in mixed mode ++ \param[out] vlan The vlan id range number ++ \param[out] vlan_range Pointer to vlan id range list ++ \param[in] flags reserved ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on success\n ++ - IFX_FAILURE on fail\n ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_hook_wan_mii0_vlan_ranges_get_fn)(int32_t *vlan, PPA_VLAN_RANGE *vlan_range, uint32_t flags); ++#else ++extern int32_t ppa_hook_wan_mii0_vlan_ranges_get_fn(int32_t *vlan, PPA_VLAN_RANGE *vlan_range, uint32_t flags); ++#endif ++ ++#ifdef CONFIG_IFX_PPA_QOS ++/*! ++ \brief This is to get the maximum queue number supported on specified port ++ \param[in] portid the physical port id which support qos queue ++ \param[in] flag reserved for future ++ \return returns the queue number supported on this port. ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ifx_ppa_hook_get_qos_qnum)( uint32_t portid, uint32_t flag); ++#else ++extern int32_t ifx_ppa_hook_get_qos_qnum( uint32_t portid, uint32_t flag); ++#endif ++ ++/*! ++ \brief This is to get the mib counter on specified port and queueid ++ \param[in] portid the physical port id which support qos queue ++ \param[in] queueid the queue id for the mib ++ \param[out] mib the buffer to store qos mib ++ \param[in] flag reserved for future ++ \return returns the queue number supported on this port. ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ifx_ppa_hook_get_qos_mib)( uint32_t portid, uint32_t queueid, PPA_QOS_MIB *mib, uint32_t flag); ++#else ++extern int32_t ifx_ppa_hook_get_qos_mib( uint32_t portid, uint32_t queueid, PPA_QOS_MIB *mib, uint32_t flag); ++#endif ++ ++ ++#ifdef CONFIG_IFX_PPA_QOS_RATE_SHAPING ++/*! ++ \brief This is to eanble/disable Rate Shaping feature ++ \param[in] portid the phisical port id which support qos queue ++ \param[in] enable 1:enable 0: disable ++ \param[in] flag reserved for future ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on success \n ++ - IFX_FAILURE on error \n ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ifx_ppa_hook_set_ctrl_qos_rate)( uint32_t portid, uint32_t enable, uint32_t flag); ++#else ++extern int32_t ifx_ppa_hook_set_ctrl_qos_rate( uint32_t portid, uint32_t enable, uint32_t flag); ++#endif ++ ++/*! ++ \brief This is to get Rate Shaping feature status: enabled or disabled ++ \param[in] portid the phisical port id which support qos queue ++ \param[out] enable buffer to store status: 1:enable 0: disable ++ \param[in] flag reserved for future ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on success \n ++ - IFX_FAILURE on error \n ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ifx_ppa_hook_get_ctrl_qos_rate)( uint32_t portid, uint32_t *enable, uint32_t flag); ++#else ++extern int32_t ifx_ppa_hook_get_ctrl_qos_rate( uint32_t portid, uint32_t *enable, uint32_t flag); ++#endif ++ ++/*! ++ \brief This is to set Rate Shaping for one specified port and queue ++ \param[in] portid the phisical port id which support qos queue ++ \param[in] queueid the queue id need to set rate shaping ++ \param[in] rate the maximum rate limit in kbps ++ \param[in] burst the maximun burst in bytes ++ \param[in] flag reserved for future ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on success \n ++ - IFX_FAILURE on error \n ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ifx_ppa_hook_set_qos_rate)( uint32_t portid, uint32_t queueid, uint32_t rate, uint32_t burst, uint32_t flag); ++#else ++extern int32_t ifx_ppa_hook_set_qos_rate( uint32_t portid, uint32_t queueid, uint32_t rate, uint32_t burst, uint32_t flag); ++#endif ++ ++/*! ++ \brief This is to get Rate Shaping settings for one specified port and queue ++ \param[in] portid the phisical port id which support qos queue ++ \param[in] queueid the queue id need to set rate shaping ++ \param[out] rate the maximum rate limit in kbps ++ \param[out] burst the maximun burst in bytes ++ \param[in] flag reserved for future ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on success \n ++ - IFX_FAILURE on error \n ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ifx_ppa_hook_get_qos_rate)( uint32_t portid, uint32_t queueid, uint32_t *rate, uint32_t *burst, uint32_t flag); ++#else ++extern int32_t ifx_ppa_hook_get_qos_rate( uint32_t portid, uint32_t queueid, uint32_t *rate, uint32_t *burst, uint32_t flag); ++#endif ++ ++/*! ++ \brief This is to reset Rate Shaping for one specified port and queue ( ++ \param[in] portid the phisical port id which support qos queue ++ \param[in] queueid the queue id need to set rate shaping ++ \param[in] flag reserved for future ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on success \n ++ - IFX_FAILURE on error \n ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ifx_ppa_hook_reset_qos_rate)( uint32_t portid, uint32_t queueid, uint32_t flag ); ++#else ++extern int32_t ifx_ppa_hook_reset_qos_rate( uint32_t portid, uint32_t queueid, uint32_t flag ); ++#endif ++ ++#endif /*end of CONFIG_IFX_PPA_QOS_RATE_SHAPING*/ ++ ++ ++#ifdef CONFIG_IFX_PPA_QOS_WFQ ++/*! ++ \brief This is to eanble/disable WFQ feature ++ \param[in] portid the phisical port id which support qos queue ++ \param[in] enable 1:enable 0: disable ++ \param[in] flag reserved for future ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on success \n ++ - IFX_FAILURE on error \n ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ifx_ppa_hook_set_ctrl_qos_wfq)( uint32_t portid, uint32_t enable, uint32_t flag); ++#else ++extern int32_t ifx_ppa_hook_set_ctrl_qos_wfq( uint32_t portid, uint32_t enable, uint32_t flag); ++#endif ++ ++/*! ++ \brief This is to get WFQ feature status: enabled or disabled ++ \param[in] portid the phisical port id which support qos queue ++ \param[out] enable 1:enable 0: disable ++ \param[in] flag reserved for future ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on success \n ++ - IFX_FAILURE on error \n ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ifx_ppa_hook_get_ctrl_qos_wfq)( uint32_t portid, uint32_t *enable, uint32_t flag); ++#else ++extern int32_t ifx_ppa_hook_get_ctrl_qos_wfq( uint32_t portid, uint32_t *enable, uint32_t flag); ++#endif ++ ++/*! ++ \brief This is to set WFQ weight level for one specified port and queue ++ \param[in] portid the phisical port id which support qos queue ++ \param[in] queueid the queue id need to set WFQ ++ \param[out] weight_level the value should be 0 ~ 100. ++ \param[in] flag reserved for future ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on success \n ++ - IFX_FAILURE on error \n ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ifx_ppa_hook_set_qos_wfq)( uint32_t portid, uint32_t queueid, uint32_t weight_level, uint32_t flag); ++#else ++extern int32_t ifx_ppa_hook_set_qos_wfq( uint32_t portid, uint32_t queueid, uint32_t weight_level, uint32_t flag); ++#endif ++ ++/*! ++ \brief This is to get WFQ settings for one specified port and queue ( default value should be 0xFFFF) ++ \param[in] portid the phisical port id which support qos queue ++ \param[in] queueid the queue id need to set WFQ ++ \param[out] weight_level the value should be 0 ~ 100. ++ \param[in] flag reserved for future ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on success \n ++ - IFX_FAILURE on error \n ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ifx_ppa_hook_get_qos_wfq)( uint32_t portid, uint32_t queueid, uint32_t *weight_level, uint32_t flag); ++#else ++extern int32_t ifx_ppa_hook_get_qos_wfq( uint32_t portid, uint32_t queueid, uint32_t *weight_level, uint32_t flag); ++#endif ++ ++/*! ++ \brief This is to reset WFQ for one specified port and queue ( default value should be 0xFFFF) ++ \param[in] portid the phisical port id which support qos queue ++ \param[in] queueid the queue id need to set WFQ ++ \param[in] flag reserved for future ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS on success \n ++ - IFX_FAILURE on error \n ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ifx_ppa_hook_reset_qos_wfq)( uint32_t portid, uint32_t queueid, uint32_t flag ); ++#else ++extern int32_t ifx_ppa_hook_reset_qos_wfq( uint32_t portid, uint32_t queueid, uint32_t flag ); ++#endif ++ ++#endif /*end of CONFIG_IFX_PPA_QOS_WFQ*/ ++#endif /*end of CONFIG_IFX_PPA_QOS*/ ++ ++#if defined(CONFIG_IFX_PPA_MFE) && CONFIG_IFX_PPA_MFE ++/*! ++ \brief This is to enable/disable multiple field function ++ \param[in] enable, 1--enable/0--disable multiple field ++ \return uint8_t, The return value can be any one of the following: \n ++ IFX_SUCCESS on sucess \n ++ IFX_FAILURE on error ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ifx_ppa_hook_multifield_control)(uint8_t enable, uint32_t flag); ++#else ++extern int32_t ifx_ppa_hook_multifield_control(uint8_t enable, uint32_t flag); ++#endif //end of NO_DOXY ++ ++/*! ++ \brief This is to get multiple field status: enable or disable ++ \param[out] enable, buffer for store the multiple filed feature stauts: 1 enabled, 0 disabled. ++ \param[in] flag, reserved for future ++ \return uint8_t The return value can be any one of the following: \n ++ IFX_SUCCESS on sucess \n ++ IFX_FAILURE on error ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ifx_ppa_hook_get_multifield_status)(uint8_t *enable, uint32_t flag); ++#else ++extern int32_t ifx_ppa_hook_get_multifield_status(uint8_t *enable, uint32_t flag); ++#endif //end of NO_DOXY ++ ++/*! ++ \brief This is to get the maximum multiple field entry/flow number ++ \return int32_t, return the maximum multiple field entry number. For PPA 2.3 it is 32 once multiple filed feature is enabled. ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ifx_ppa_hook_get_multifield_max_flow)(uint32_t flag); ++#else ++extern int32_t ifx_ppa_hook_get_multifield_max_flow(uint32_t flag); ++#endif //end of NO_DOXY ++ ++/*! ++ \brief This is to add one multiple field flow ++ \param[in] p_multifield_info, the pointer which store the classficication set. ++ \param[out]: index return the flow index if successfully added into. \n ++ \param[in] flag, reserved for future ++ \return int32_t, The return value can be any one of the following: \n ++ IFX_SUCCESS on sucess \n ++ IFX_FAILURE on error \n ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ifx_ppa_hook_add_multifield_flow)( PPA_MULTIFIELD_FLOW_INFO *p_multifield_info, int32_t *index, uint32_t flag); ++#else ++extern int32_t ifx_ppa_hook_add_multifield_flow( PPA_MULTIFIELD_FLOW_INFO *p_multifield_info, int32_t *index, uint32_t flag); ++#endif //end of NO_DOXY ++ ++/*! ++ \brief This is to get one multiple field flow as specified via index ++ \param[in] p_multifield_info, the pointer which stores the classficication set configuration ++ \param[in] flag, reserved for future ++ \return int32_t, return the bytes in the compare table. It can be any one of the following now: \n ++ IFX_SUCCESS on sucess \n ++ IFX_FAILURE on error ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ifx_ppa_hook_get_multifield_flow)( int32_t index, PPA_MULTIFIELD_FLOW_INFO *p_multifield_info, uint32_t flag ); ++#else ++extern int32_t ifx_ppa_hook_get_multifield_flow( int32_t index, PPA_MULTIFIELD_FLOW_INFO *p_multifield_info, uint32_t flag ); ++#endif ++/*! ++ \brief This is to delete multiple field entry if compare/mask/key completely match ++ \param[in] p_multifield_info, the pointer to store the classficication set configuration ++ \param[in] flag, reserved for future ++ \return int32_t, The return value can be any one of the following: \n ++ IFX_SUCCESS on sucess \n ++ IFX_FAILURE on error, like entry full already ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ifx_ppa_hook_del_multifield_flow)( PPA_MULTIFIELD_FLOW_INFO *p_multifield_info, uint32_t flag ); ++#else ++extern int32_t ifx_ppa_hook_del_multifield_flow( PPA_MULTIFIELD_FLOW_INFO *p_multifield_info, uint32_t flag ); ++#endif //end of NO_DOXY ++ ++/*! ++ \brief This is to delete multiple field entry as specified via index ++ \param[out] index, the index of compare table to delete ++ \return int32_t, return the bytes in the compare table. It can be any one of the following now: \n ++ \return int32_t, The return value can be any one of the following: \n ++ IFX_SUCCESS on sucess \n ++ IFX_FAILURE on error ++ \note if index is _1, it will delete all multiple field entries ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ifx_ppa_hook_quick_del_multifield_flow)( int32_t index, uint32_t flag); ++#else ++extern int32_t ifx_ppa_hook_quick_del_multifield_flow( int32_t index, uint32_t flag); ++#endif //end of NO_DOXY ++#endif //end of CONFIG_IFX_PPA_API_MFE ++ ++/*! ++ \brief This is to get dsl mib counter ++ \param[out] mib the buffer to store dsl mib ++ \param[in/out] flag reserved for future ++ \return int32_t, The return value can be any one of the following: \n ++ IFX_SUCCESS on sucess \n ++ IFX_FAILURE on error ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ifx_ppa_hook_get_dsl_mib)( PPA_DSL_QUEUE_MIB *mib, uint32_t flag); ++#else ++extern int32_t ifx_ppa_hook_get_dsl_mib(PPA_DSL_QUEUE_MIB *mib, uint32_t flag); ++#endif //end of NO_DOXY ++ ++/*! ++ \brief This is to get port mib counter ++ \param[out] mib the buffer to store dsl mib ++ \param[in/out] flag reserved for future ++ \return int32_t, The return value can be any one of the following: \n ++ IFX_SUCCESS on sucess \n ++ IFX_FAILURE on error ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ifx_ppa_hook_get_port_mib)( PPA_PORT_MIB *mib); ++#else ++extern int32_t ifx_ppa_hook_get_port_mib(PPA_PORT_MIB *mib); ++#endif //end of NO_DOXY ++ ++ ++/*! ++ \brief This is to get 6rd tunnel's destination mac address ++ \param[in] network device pointer ++ \param[out] buffer to store ethernet mac address ++ \return int32_t, The return value can be any one of the following: \n ++ IFX_SUCCESS on sucess \n ++ IFX_FAILURE on error ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_get_6rd_dmac_fn)(PPA_NETIF *netif, uint8_t *mac); ++#else ++extern int32_t ppa_get_6rd_dmac_fn(PPA_NETIF *netif, uint8_t *mac); ++#endif ++ ++/*! ++ \brief This is to get ipv6 tunnel's destination mac address ++ \param[in] network device pointer ++ \param[out] buffer to store ethernet mac address ++ \return int32_t, The return value can be any one of the following: \n ++ IFX_SUCCESS on sucess \n ++ IFX_FAILURE on error ++*/ ++#ifdef NO_DOXY ++extern int32_t (*ppa_get_ip4ip6_dmac_fn)(PPA_NETIF *netif, uint8_t *mac); ++#else ++extern int32_t ppa_get_ip4ip6_dmac_fn(PPA_NETIF *netif, uint8_t *mac); ++#endif ++ ++ ++/*! ++ \brief This is to get 6rd tunnel's underlayer device ++ \param[in] network device pointer ++ \return int32_t, The return value can be any one of the following: \n ++ pointer to the 6rd's underlayer device \n ++ NULL on error ++*/ ++#ifdef NO_DOXY ++extern PPA_NETIF* (*ppa_get_6rd_phyif_fn)(PPA_NETIF *netif); ++#else ++extern PPA_NETIF* ppa_get_6rd_phyif_fn(PPA_NETIF *netif); ++ ++#endif ++ ++/*! ++ \brief This is to get ipv6 tunnel's underlayer device ++ \param[in] network device pointer ++ \return int32_t, The return value can be any one of the following: \n ++ pointer to the ipv6 tunnel's underlayer device \n ++ NULL on error ++*/ ++#ifdef NO_DOXY ++extern PPA_NETIF* (*ppa_get_ip4ip6_phyif_fn)(PPA_NETIF *netif); ++#else ++extern PPA_NETIF* ppa_get_ip4ip6_phyif_fn(PPA_NETIF *netif); ++ ++#endif ++ ++ ++#endif //end of __KERNEL__ ++ ++ ++/* @} */ ++#endif // __IFX_PPA_HOOK_H__20081103_1736__ +diff --git a/include/net/ifx_ppa_ppe_hal.h b/include/net/ifx_ppa_ppe_hal.h +new file mode 100644 +index 0000000..b5d3e0f +--- /dev/null ++++ b/include/net/ifx_ppa_ppe_hal.h +@@ -0,0 +1,317 @@ ++#ifndef __IFX_PPA_PPE_HAL_H__20081104_1318__ ++#define __IFX_PPA_PPE_HAL_H__20081104_1318__ ++ ++ ++ ++/******************************************************************************* ++** ++** FILE NAME : ifx_ppa_ppe_hal.h ++** PROJECT : PPA ++** MODULES : PPA API (Routing/Bridging Acceleration APIs) ++** ++** DATE : 4 NOV 2008 ++** AUTHOR : Xu Liang ++** DESCRIPTION : PPA PPE Firmware Hardware/Firmware Adaption Layer Header File ++*** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3; 85579 Neubiberg, Germany ++** ++** For licensing information, see the file 'LICENSE' in the root folder of ++** this software module. ++** ++** HISTORY ++** $Date $Author $Comment ++** 04 NOV 2008 Xu Liang Initiate Version ++*******************************************************************************/ ++ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++#define IFX_PPA_IF_NOT_FOUND 0 ++#define IFX_PPA_IF_TYPE_LAN 1 ++#define IFX_PPA_IF_TYPE_WAN 2 ++#define IFX_PPA_IF_TYPE_MIX 3 ++ ++#define IFX_PPA_ACC_MODE_NONE 0 ++#define IFX_PPA_ACC_MODE_BRIDGING 1 ++#define IFX_PPA_ACC_MODE_ROUTING 2 ++#define IFX_PPA_ACC_MODE_HYBRID 3 ++ ++#define IFX_PPA_SET_ROUTE_CFG_ENTRY_NUM 0x01 ++#define IFX_PPA_SET_ROUTE_CFG_MC_ENTRY_NUM 0x02 ++#define IFX_PPA_SET_ROUTE_CFG_IP_VERIFY 0x04 ++#define IFX_PPA_SET_ROUTE_CFG_TCPUDP_VERIFY 0x08 ++#define IFX_PPA_SET_ROUTE_CFG_TCPUDP_ERR_DROP 0x10 ++#define IFX_PPA_SET_ROUTE_CFG_DROP_ON_NOT_HIT 0x20 ++#define IFX_PPA_SET_ROUTE_CFG_MC_DROP_ON_NOT_HIT 0x40 ++ ++#define IFX_PPA_SET_BRIDGING_CFG_ENTRY_NUM 0x01 ++#define IFX_PPA_SET_BRIDGING_CFG_BR_TO_SRC_PORT_EN 0x02 ++#define IFX_PPA_SET_BRIDGING_CFG_DEST_VLAN_EN 0x04 ++#define IFX_PPA_SET_BRIDGING_CFG_SRC_VLAN_EN 0x08 ++#define IFX_PPA_SET_BRIDGING_CFG_MAC_CHANGE_DROP 0x10 ++ ++#define IFX_PPA_ROUTE_TYPE_NULL 0 ++#define IFX_PPA_ROUTE_TYPE_IPV4 1 ++#define IFX_PPA_ROUTE_TYPE_NAT 2 ++#define IFX_PPA_ROUTE_TYPE_NAPT 3 ++ ++//#define IFX_PPA_DEST_LIST_ETH0 0x01 ++//#define IFX_PPA_DEST_LIST_ETH1 0x02 ++//#define IFX_PPA_DEST_LIST_CPU0 0x04 ++//#define IFX_PPA_DEST_LIST_EXT_INT1 0x08 ++//#define IFX_PPA_DEST_LIST_EXT_INT2 0x10 ++//#define IFX_PPA_DEST_LIST_EXT_INT3 0x20 ++//#define IFX_PPA_DEST_LIST_EXT_INT4 0x40 ++//#define IFX_PPA_DEST_LIST_EXT_INT5 0x80 ++//#define IFX_PPA_DEST_LIST_ATM IFX_PPA_DEST_LIST_EXT_INT5 // EoA ++ ++//#define IFX_PPA_DEST_LIST_ETH0 0x0001 ++//#define IFX_PPA_DEST_LIST_ETH1 0x0002 ++//#define IFX_PPA_DEST_LIST_CPU0 0x0004 ++//#define IFX_PPA_DEST_LIST_EXT_INT1 0x0008 ++//#define IFX_PPA_DEST_LIST_EXT_INT2 0x0010 ++//#define IFX_PPA_DEST_LIST_EXT_INT3 0x0020 ++//#define IFX_PPA_DEST_LIST_EXT_INT4 0x0040 ++//#define IFX_PPA_DEST_LIST_EXT_INT5 0x0080 ++//#define IFX_PPA_DEST_LIST_ATM 0x0100 ++//#define IFX_PPA_DEST_LIST_NO_REMAP (1 << 31) ++ ++#define IFX_PPA_PHYS_PORT_FLAGS_VALID 0x0001 ++#define IFX_PPA_PHYS_PORT_FLAGS_TYPE_CPU 0x0000 ++#define IFX_PPA_PHYS_PORT_FLAGS_TYPE_ATM 0x0010 ++#define IFX_PPA_PHYS_PORT_FLAGS_TYPE_ETH 0x0020 ++#define IFX_PPA_PHYS_PORT_FLAGS_TYPE_EXT 0x0030 ++#define IFX_PPA_PHYS_PORT_FLAGS_TYPE_MASK 0x0030 ++#define IFX_PPA_PHYS_PORT_FLAGS_MODE_LAN 0x0100 ++#define IFX_PPA_PHYS_PORT_FLAGS_MODE_WAN 0x0200 ++#define IFX_PPA_PHYS_PORT_FLAGS_MODE_MIX (IFX_PPA_PHYS_PORT_FLAGS_MODE_LAN | IFX_PPA_PHYS_PORT_FLAGS_MODE_WAN) ++#define IFX_PPA_PHYS_PORT_FLAGS_MODE_MASK 0x0300 ++#define IFX_PPA_PHYS_PORT_FLAGS_OUTER_VLAN 0x1000 ++#define IFX_PPA_PHYS_PORT_FLAGS_EXT_CPU0 0x4000 ++#define IFX_PPA_PHYS_PORT_FLAGS_EXT_CPU1 0x8000 ++ ++#define IFX_PPA_PHYS_PORT_FLAGS_MODE_ETH_LAN_VALID (IFX_PPA_PHYS_PORT_FLAGS_TYPE_ETH | IFX_PPA_PHYS_PORT_FLAGS_MODE_LAN | IFX_PPA_PHYS_PORT_FLAGS_VALID) ++#define IFX_PPA_PHYS_PORT_FLAGS_MODE_ETH_WAN_VALID (IFX_PPA_PHYS_PORT_FLAGS_TYPE_ETH | IFX_PPA_PHYS_PORT_FLAGS_MODE_WAN | IFX_PPA_PHYS_PORT_FLAGS_VALID) ++#define IFX_PPA_PHYS_PORT_FLAGS_MODE_ETH_MIX_VALID (IFX_PPA_PHYS_PORT_FLAGS_TYPE_ETH | IFX_PPA_PHYS_PORT_FLAGS_MODE_MIX | IFX_PPA_PHYS_PORT_FLAGS_VALID) ++#define IFX_PPA_PHYS_PORT_FLAGS_MODE_CPU_VALID (IFX_PPA_PHYS_PORT_FLAGS_TYPE_CPU | IFX_PPA_PHYS_PORT_FLAGS_VALID) ++#define IFX_PPA_PHYS_PORT_FLAGS_MODE_ATM_WAN_VALID (IFX_PPA_PHYS_PORT_FLAGS_TYPE_ATM | IFX_PPA_PHYS_PORT_FLAGS_MODE_WAN | IFX_PPA_PHYS_PORT_FLAGS_VALID) ++#define IFX_PPA_PHYS_PORT_FLAGS_MODE_EXT_LAN_VALID (IFX_PPA_PHYS_PORT_FLAGS_TYPE_EXT | IFX_PPA_PHYS_PORT_FLAGS_MODE_LAN | IFX_PPA_PHYS_PORT_FLAGS_VALID) ++#define IFX_PPA_PHYS_PORT_FLAGS_MODE_EXT_WAN_VALID (IFX_PPA_PHYS_PORT_FLAGS_TYPE_EXT | IFX_PPA_PHYS_PORT_FLAGS_MODE_WAN | IFX_PPA_PHYS_PORT_FLAGS_VALID) ++ ++#define IFX_PPA_PPPOE_MODE_TRANSPARENT 0 ++#define IFX_PPA_PPPOE_MODE_TERMINATION 1 ++ ++#define IFX_PPA_UPDATE_ROUTING_ENTRY_ROUTE_TYPE 0x0001 ++#define IFX_PPA_UPDATE_ROUTING_ENTRY_NEW_IP 0x0002 ++#define IFX_PPA_UPDATE_ROUTING_ENTRY_NEW_PORT 0x0004 ++#define IFX_PPA_UPDATE_ROUTING_ENTRY_NEW_MAC 0x0008 ++#define IFX_PPA_UPDATE_ROUTING_ENTRY_NEW_SRC_MAC_IX 0x0010 ++#define IFX_PPA_UPDATE_ROUTING_ENTRY_MTU_IX 0x0020 ++#define IFX_PPA_UPDATE_ROUTING_ENTRY_NEW_DSCP_EN 0x0040 ++#define IFX_PPA_UPDATE_ROUTING_ENTRY_NEW_DSCP 0x0080 ++#define IFX_PPA_UPDATE_ROUTING_ENTRY_VLAN_INS_EN 0x0100 ++#define IFX_PPA_UPDATE_ROUTING_ENTRY_NEW_VCI 0x0200 ++#define IFX_PPA_UPDATE_ROUTING_ENTRY_VLAN_RM_EN 0x0400 ++#define IFX_PPA_UPDATE_ROUTING_ENTRY_PPPOE_MODE 0x0800 ++#define IFX_PPA_UPDATE_ROUTING_ENTRY_PPPOE_IX 0x1000 ++#define IFX_PPA_UPDATE_ROUTING_ENTRY_OUT_VLAN_INS_EN 0x0100 ++#define IFX_PPA_UPDATE_ROUTING_ENTRY_OUT_VLAN_IX 0x0200 ++#define IFX_PPA_UPDATE_ROUTING_ENTRY_OUT_VLAN_RM_EN 0x0400 ++#define IFX_PPA_UPDATE_ROUTING_ENTRY_DEST_LIST 0x2000 ++#define IFX_PPA_UPDATE_ROUTING_ENTRY_DEST_QID 0x4000 ++ ++#define IFX_PPA_UPDATE_WAN_MC_ENTRY_VLAN_INS_EN 0x0001 ++#define IFX_PPA_UPDATE_WAN_MC_ENTRY_NEW_VCI 0x0002 ++#define IFX_PPA_UPDATE_WAN_MC_ENTRY_VLAN_RM_EN 0x0004 ++#define IFX_PPA_UPDATE_WAN_MC_ENTRY_SRC_MAC_EN 0x0008 ++#define IFX_PPA_UPDATE_WAN_MC_ENTRY_SRC_MAC_IX 0x0010 ++#define IFX_PPA_UPDATE_WAN_MC_ENTRY_DEST_LIST 0x0020 ++#define IFX_PPA_UPDATE_WAN_MC_ENTRY_DEST_CHID 0x0040 ++#define IFX_PPA_UPDATE_WAN_MC_ENTRY_PPPOE_MODE 0x0080 ++#define IFX_PPA_UPDATE_WAN_MC_ENTRY_OUT_VLAN_INS_EN 0x0100 ++#define IFX_PPA_UPDATE_WAN_MC_ENTRY_OUT_VLAN_IX 0x0200 ++#define IFX_PPA_UPDATE_WAN_MC_ENTRY_OUT_VLAN_RM_EN 0x0400 ++#define IFX_PPA_UPDATE_WAN_MC_ENTRY_NEW_DSCP_EN 0x0800 ++#define IFX_PPA_UPDATE_WAN_MC_ENTRY_NEW_DSCP 0x1000 ++#define IFX_PPA_UPDATE_WAN_MC_ENTRY_DEST_QID IFX_PPA_UPDATE_WAN_MC_ENTRY_DEST_CHID ++ ++#define IFX_PPA_ADD_MAC_ENTRY_PPPOE 0x01 ++#define IFX_PPA_ADD_MAC_ENTRY_LAN 0x02 ++#define IFX_PPA_ADD_MAC_ENTRY_WAN 0x00 ++ ++#define IFX_PPA_SET_FAST_MODE_CPU1 0x01 ++#define IFX_PPA_SET_FAST_MODE_APP2 IFX_PPA_SET_FAST_MODE_CPU1 ++#define IFX_PPA_SET_FAST_MODE_ETH1 0x02 ++#define IFX_PPA_SET_FAST_MODE_ATM IFX_PPA_SET_FAST_MODE_ETH1 ++ ++#define IFX_PPA_SET_FAST_MODE_CPU1_DIRECT IFX_PPA_SET_FAST_MODE_CPU1 ++#define IFX_PPA_SET_FAST_MODE_CPU1_INDIRECT 0 ++#define IFX_PPA_SET_FAST_MODE_APP2_DIRECT IFX_PPA_SET_FAST_MODE_CPU1_DIRECT ++#define IFX_PPA_SET_FAST_MODE_APP2_INDIRECT IFX_PPA_SET_FAST_MODE_CPU1_INDIRECT ++#define IFX_PPA_SET_FAST_MODE_ETH1_DIRECT IFX_PPA_SET_FAST_MODE_ETH1 ++#define IFX_PPA_SET_FAST_MODE_ETH1_INDIRECT 0 ++#define IFX_PPA_SET_FAST_MODE_ATM_DIRECT IFX_PPA_SET_FAST_MODE_ETH1_DIRECT ++#define IFX_PPA_SET_FAST_MODE_ATM_INDIRECT IFX_PPA_SET_FAST_MODE_ETH1_INDIRECT ++ ++//#define IFX_PPA_PORT_ETH0 0x00 ++//#define IFX_PPA_PORT_ETH1 0x01 ++//#define IFX_PPA_PORT_CPU0 0x02 ++//#define IFX_PPA_PORT_CPU1_EXT_IF0 0x05 ++//#define IFX_PPA_PORT_ATM 0x07 ++//#define IFX_PPA_PORT_ANY IFX_PPA_PORT_CPU0 ++//#define IFX_PPA_PORT_NUM 0x08 ++ ++// Obsolete, for bridging only ++//#define IFX_PPA_PORT_ETH0 0x00 ++//#define IFX_PPA_PORT_ETH1 0x01 ++//#define IFX_PPA_PORT_CPU0 0x02 ++//#define IFX_PPA_PORT_CPU1_EXT_IF0 0x05 ++//#define IFX_PPA_PORT_ATM 0x08 ++//#define IFX_PPA_PORT_ANY IFX_PPA_PORT_CPU0 ++//#define IFX_PPA_PORT_NUM 0x09 ++ ++#define IFX_PPA_BRG_VLAN_IG_COND_TYPE_DEF 0 ++#define IFX_PPA_BRG_VLAN_IG_COND_TYPE_SRC_IP 1 ++#define IFX_PPA_BRG_VLAN_IG_COND_TYPE_ETH_TYPE 2 ++#define IFX_PPA_BRG_VLAN_IG_COND_TYPE_VLAN 3 ++ ++typedef enum { ++ PPA_GENERIC_HAL_GET_DSL_MIB= 0, //Get dsl mib ++ PPA_GENERIC_HAL_CLEAR_DSL_MIB, //clear dsl mib ++ PPA_GENERIC_WAN_INFO, //get wan information ++ PPA_GENERIC_HAL_GET_PORT_MIB, //get alls ports mib ++ PPA_GENERIC_HAL_CLEAR_PORT_MIB, //clear all ports mib ++ PPA_GENERIC_HAL_SET_DEBUG, // turn on/off hal debug information ++ PPA_GENERIC_HAL_GET_FEATURE_LIST, //get featuer list ++ ++//Fix warning message when exports API from different PPE FW Driver--begin ++ PPA_GENERIC_HAL_GET_MAX_ENTRIES, //get maximum ipv4 routing entry number ++ PPA_GENERIC_HAL_GET_HAL_VERSION, //get hal version number ++ PPA_GENERIC_HAL_GET_PPE_FW_VERSION, //get ppe fw version number ++ PPA_GENERIC_HAL_GET_PHYS_PORT_NUM, //get maixum physical port number ++ PPA_GENERIC_HAL_GET_PHYS_PORT_INFO, //get physical port information ++ PPA_GENERIC_HAL_SET_MIX_WAN_VLAN_ID, //set WAN interface's vlan range for mixed mode ++ PPA_GENERIC_HAL_GET_MIX_WAN_VLAN_ID, //get WAN interface's vlan range for mixed mode ++ PPA_GENERIC_HAL_SET_ROUT_CFG, //set routing configuration ++ PPA_GENERIC_HAL_SET_BRDG_CFG, //set bridge confgiration ++ PPA_GENERIC_HAL_SET_FAST_MODE_CFG, //set fact mode configuration ++ PPA_GENERIC_HAL_SET_DEST_LIST, // set destion list ++ PPA_GENERIC_HAL_SET_ACC_ENABLE, // eanble/disable Lan/wan routing acceleration respectively ++ PPA_GENERIC_HAL_GET_ACC_ENABLE, //get lan/wan routing eanble flag ++ PPA_GENERIC_HAL_SET_BRDG_VLAN_CFG, //set vlan briding configuration for a4/d4/e4 only ++ PPA_GENERIC_HAL_GET_BRDG_VLAN_CFG, //get vlan briding configuration for a4/d4/e4 only ++ PPA_GENERIC_HAL_ADD_BRDG_VLAN_FITLER, //set vlan briding flow for a4/d4/e4 only ++ PPA_GENERIC_HAL_DEL_BRDG_VLAN_FITLER, //del vlan briding flow for a4/d4/e4 only ++ PPA_GENERIC_HAL_GET_BRDG_VLAN_FITLER, //get vlan briding flow for a4/d4/e4 only ++ PPA_GENERIC_HAL_DEL_BRDG_VLAN_ALL_FITLER_MAP, //delete all vlan briding filter's mapping ++ PPA_GENERIC_HAL_GET_MAX_VFILTER_ENTRY_NUM, //get the maxumum entry for vlan filter ++ PPA_GENERIC_HAL_GET_IPV6_FLAG, //get ipv6 status : enabled or disabled ++ PPA_GENERIC_HAL_ADD_ROUTE_ENTRY, //add an ipv4 routing entry ++ PPA_GENERIC_HAL_DEL_ROUTE_ENTRY, //del an ipv4 routing entry ++ PPA_GENERIC_HAL_UPDATE_ROUTE_ENTRY, //modify an ipv4 routing entry ++ PPA_GENERIC_HAL_ADD_MC_ENTRY, //add a multicast entry ++ PPA_GENERIC_HAL_DEL_MC_ENTRY, //del a multicast entry ++ PPA_GENERIC_HAL_UPDATE_MC_ENTRY, //modify a multicast entry ++ PPA_GENERIC_HAL_ADD_BR_MAC_BRIDGING_ENTRY, //add an mac address from brdging learning ++ PPA_GENERIC_HAL_DEL_BR_MAC_BRIDGING_ENTRY, //del an mac address from brdging learning ++ PPA_GENERIC_HAL_ADD_PPPOE_ENTRY, //add a pppoe entry ++ PPA_GENERIC_HAL_DEL_PPPOE_ENTRY, //del a pppoe entry ++ PPA_GENERIC_HAL_GET_PPPOE_ENTRY, //get a ppoe entry ++ PPA_GENERIC_HAL_ADD_6RD_TUNNEL_ENTRY, //add a 6rd tunnel entry ++ PPA_GENERIC_HAL_DEL_6RD_TUNNEL_ENTRY, //del a 6rd tunnel entry ++ PPA_GENERIC_HAL_GET_6RD_TUNNEL_ENTRY, //get a 6rd tunnel entry ++ PPA_GENERIC_HAL_ADD_DSLITE_TUNNEL_ENTRY, //add a dslite tunnel entry ++ PPA_GENERIC_HAL_DEL_DSLITE_TUNNEL_ENTRY, //del a dslite tunnel entry ++ PPA_GENERIC_HAL_GET_DSLITE_TUNNEL_ENTRY, //get a dslite tunnel entry ++ PPA_GENERIC_HAL_ADD_MTU_ENTRY, //and a MTU entry ++ PPA_GENERIC_HAL_DEL_MTU_ENTRY, //del a MTU entry ++ PPA_GENERIC_HAL_GET_MTU_ENTRY, //get a MUT entry ++ PPA_GENERIC_HAL_GET_ROUTE_ACC_BYTES, //get the acclerated bytes counter for a specified acceleration routing entry ++ PPA_GENERIC_HAL_ADD_MAC_ENTRY, //add a routing mac address ++ PPA_GENERIC_HAL_DEL_MAC_ENTRY, //del a routing mac address ++ PPA_GENERIC_HAL_GET_MAC_ENTRY, //get a routing mac address ++ PPA_GENERIC_HAL_ADD_OUT_VLAN_ENTRY, //add a out vlan entry ++ PPA_GENERIC_HAL_DEL_OUT_VLAN_ENTRY, //del a out vlan entry ++ PPA_GENERIC_HAL_GET_OUT_VLAN_ENTRY, //get a out vlan entry info ++ PPA_GENERIC_HAL_GET_ITF_MIB, /*get one port's mib counter. I think it should be merged with PPA_GENERIC_HAL_GET_PORT_MIB */ ++ PPA_GENERIC_HAL_MFE_CONTROL, //enable/disable multiple field vlan editing feature ++ PPA_GENERIC_HAL_MFE_STATUS, // get a multiple field vlan editing feature status: enabled/disabled ++ PPA_GENERIC_HAL_MFE_GET_FLOW_MAX_ENTRY, // get muaximum entry number for multiple field vlan editing ++ PPA_GENERIC_HAL_MFE_ADD_FLOW, //add a multiple field vlan editing entry ++ PPA_GENERIC_HAL_MFE_DEL_FLOW, //del a multiple field vlan editing entry ++ PPA_GENERIC_HAL_MFE_DEL_FLOW_VIA_ENTRY, //del a multiple field vlan editing entry ++ PPA_GENERIC_HAL_MFE_GET_FLOW, //get a multiple field vlan editing entry ++ PPA_GENERIC_HAL_TEST_CLEAR_ROUTE_HIT_STAT, //check whether a routing session is hit or not ++ PPA_GENERIC_HAL_TEST_CLEAR_BR_HIT_STAT, //check whether a routing session is hit or not ++ PPA_GENERIC_HAL_INIT, //init HAL ++ PPA_GENERIC_HAL_EXIT, //exit HAL ++ PPA_GENERIC_HAL_GET_QOS_QUEUE_NUM, //get maximum QOS queue number ++ PPA_GENERIC_HAL_GET_QOS_MIB, //get maximum QOS queue number ++ PPA_GENERIC_HAL_SET_QOS_WFQ_CTRL, //enable/disable WFQ ++ PPA_GENERIC_HAL_GET_QOS_WFQ_CTRL, //get WFQ status: enabeld/disabled ++ PPA_GENERIC_HAL_SET_QOS_WFQ_CFG, //set WFQ cfg ++ PPA_GENERIC_HAL_RESET_QOS_WFQ_CFG, //reset WFQ cfg ++ PPA_GENERIC_HAL_GET_QOS_WFQ_CFG, //get WFQ cfg ++ PPA_GENERIC_HAL_INIT_QOS_WFQ, // init QOS Rateshapping ++ PPA_GENERIC_HAL_SET_QOS_RATE_SHAPING_CTRL, //enable/disable Rate shaping ++ PPA_GENERIC_HAL_GET_QOS_RATE_SHAPING_CTRL, //get Rateshaping status: enabeld/disabled ++ PPA_GENERIC_HAL_SET_QOS_RATE_SHAPING_CFG, //set rate shaping ++ PPA_GENERIC_HAL_GET_QOS_RATE_SHAPING_CFG, //get rate shaping cfg ++ PPA_GENERIC_HAL_RESET_QOS_RATE_SHAPING_CFG, //reset rate shaping cfg ++ PPA_GENERIC_HAL_INIT_QOS_RATE_SHAPING, // init QOS Rateshapping ++ ++//Fix warning message when exports API from different PPE FW Driver--End ++ ++ PPA_GENERIC_HAL_GET_QOS_STATUS, // get QOS tatus ++ ++ ++ ++ /*make sure it is the last one */ ++ PPA_GENERIC_HAL_MAX_FLAG ++}PPA_GENERIC_HOOK_CMD; ++ ++#define IFX_PPA_PWM_LEVEL_D0 0 ++#define IFX_PPA_PWM_LEVEL_D1 1 ++#define IFX_PPA_PWM_LEVEL_D2 2 ++#define IFX_PPA_PWM_LEVEL_D3 3 ++ ++ ++ ++/* ++ * #################################### ++ * Data Type ++ * #################################### ++ */ ++ ++ ++ ++ ++ ++ ++/* ++ * #################################### ++ * Declaration ++ * #################################### ++ */ ++ ++#ifdef __KERNEL__ ++ ++ ++ ++ /* ++ * implemented in datapath driver ++ */ ++ ++extern int32_t (*ifx_ppa_drv_hal_generic_hook)(PPA_GENERIC_HOOK_CMD cmd, void *buffer, uint32_t flag); ++ ++#endif // __KERNEL__ ++ ++ ++ ++#endif // __IFX_PPA_PPE_HAL_H__20081104_1318__ +diff --git a/include/net/ifx_ppa_stack_al.h b/include/net/ifx_ppa_stack_al.h +new file mode 100644 +index 0000000..7d28b7b +--- /dev/null ++++ b/include/net/ifx_ppa_stack_al.h +@@ -0,0 +1,1559 @@ ++#ifndef __IFX_PPA_STACK_AL_H__20081103_1153__ ++#define __IFX_PPA_STACK_AL_H__20081103_1153__ ++ ++ ++ ++/****************************************************************************** ++** ++** FILE NAME : ifx_ppa_stack_al.h ++** PROJECT : PPA ++** MODULES : PPA Protocol Stack Adaption Layer (Linux) ++** ++** DATE : 3 NOV 2008 ++** AUTHOR : Xu Liang ++** DESCRIPTION : PPA Protocol Stack Adaption Layer (Linux) Header File ++** COPYRIGHT : Copyright (c) 2009 ++** Lantiq Deutschland GmbH ++** Am Campeon 3; 85579 Neubiberg, Germany ++** ++** For licensing information, see the file 'LICENSE' in the root folder of ++** this software module. ++** ++** HISTORY ++** $Date $Author $Comment ++** 03 NOV 2008 Xu Liang Initiate Version ++*******************************************************************************/ ++ ++/*! \file ifx_ppa_stack_al.h ++ \brief This file contains es. ++ provide linux os depenent api for PPA to use ++*/ ++ ++ ++#include ++ ++#ifdef __KERNEL__ ++ #include ++ #include ++ #include ++ #if defined(CONFIG_NF_CONNTRACK_SUPPORT) || defined(CONFIG_NF_CONNTRACK) ++ #include /* protocol independent conntrack */ ++ #else ++ #include ++ #endif ++#endif //end of __KERNEL__ ++ ++#if defined(CONFIG_IFX_PMCU) || defined(CONFIG_IFX_PMCU_MODULE) ++ //PMCU specific Head File ++ #include ++ #include ++#endif //end of CONFIG_IFX_PMCU ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++/*! \def PPA_ETH_ALEN ++ \brief Macro that specifies the maximum length of an Ethernet MAC address. ++ */ ++#define PPA_ETH_ALEN ETH_ALEN ++ ++/*! \def PPA_ETH_HLEN ++ \brief Macro that specifies the maximum length of an Ethernet MAC header. ++ */ ++#define PPA_ETH_HLEN ETH_HLEN ++ ++/*! \def PPA_ETH_CRCLEN ++ \brief Macro that specifies the maximum length of an Ethernet CRC. ++ */ ++#define PPA_ETH_CRCLEN 4 ++ ++/*! \def PPA_IF_NAME_SIZE ++ \brief Macro that specifies the maximum size of one interface name ++ */ ++#define PPA_IF_NAME_SIZE IFNAMSIZ ++ ++/*! \def IFX_IPPROTO_TCP ++ \brief Macro that specifies TCP flag ++ */ ++#define IFX_IPPROTO_TCP 6 ++ ++/*! \def IFX_IPPROTO_UDP ++ \brief Macro that specifies UDP flag ++ */ ++#define IFX_IPPROTO_UDP 17 ++ ++/*! \def PPA_USER ++ \brief Macro that specifies the flag for the buffer type from User Space via ioctl ++ */ ++#define PPA_USER __user ++ ++/* ++ * definition for application layer ++ */ ++#ifndef __KERNEL__ ++/*! \def ETH_ALEN ++ \brief Macro that specifies the maximum length of an Ethernet MAC address. ++ */ ++ #define ETH_ALEN 6 ++ ++/*! \def IFNAMSIZ ++ \brief Macro that specifies the maximum size of an interface NAME ++ */ ++ #define IFNAMSIZ 16 ++#endif ++ ++#define NIPQUAD(addr) \ ++ ((unsigned char *)&addr)[0], \ ++ ((unsigned char *)&addr)[1], \ ++ ((unsigned char *)&addr)[2], \ ++ ((unsigned char *)&addr)[3] ++ ++#undef NIP6 ++#define NIP6(addr) \ ++ ntohs(((unsigned short *)addr)[0]), \ ++ ntohs(((unsigned short *)addr)[1]), \ ++ ntohs(((unsigned short *)addr)[2]), \ ++ ntohs(((unsigned short *)addr)[3]), \ ++ ntohs(((unsigned short *)addr)[4]), \ ++ ntohs(((unsigned short *)addr)[5]), \ ++ ntohs(((unsigned short *)addr)[6]), \ ++ ntohs(((unsigned short *)addr)[7]) ++ ++/* ++ * #################################### ++ * Data Type ++ * #################################### ++ */ ++ ++/* ++ * data type for application layer ++ */ ++#ifndef __KERNEL__ ++/*! ++ \brief This is the unsigned char 32-bit data type. ++*/ ++ typedef unsigned long uint32_t; ++ ++/*! \def uint16_t ++ \brief This is the unsigned char 16-bit data type. ++*/ ++ typedef unsigned short uint16_t; ++ ++/*! ++ \brief This is the unsigned char 8-bit data type. ++*/ ++ typedef unsigned char uint8_t; ++ ++/*! ++ \brief This is the unsigned char 64-bit data type. ++*/ ++ typedef unsigned long long uint64_t; ++ ++#endif ++ ++/* ++ * data type for API ++ */ ++/*! ++ \brief Pointer to interface name ++*/ ++typedef char PPA_IFNAME; ++/*! ++ \brief This is the data structure holding the IP address. It helps to provide future compatibility for IPv6 support. ++ Currently it only supports IPv4. ++ ++*/ ++typedef uint32_t IPADDR; ++ ++/*! ++ \brief Union of PPA network address ++ */ ++ typedef union { ++ uint32_t ip; /*!< the storage buffer for ipv4 */ ++#ifdef CONFIG_IFX_PPA_IPv6_ENABLE ++ uint32_t ip6[4]; /*!< the storage buffer for ipv6 */ ++#endif ++ }PPA_IPADDR; ++ ++#ifdef __KERNEL__ ++ ++/*! ++ \brief Packet buffer structure. For Linux OS, this is the sk_buff structure. ++*/ ++ typedef struct sk_buff PPA_BUF; ++ ++/*! ++ \brief Stateful Packet inspection / connection tracking session data structure. ++ A packet is classified to such a session by SPI/NAT infrastructure. ++ In Linux, this is defined to the Linux ip_conntrack/nf_conntrack structure. ++*/ ++ #if defined(CONFIG_NF_CONNTRACK_SUPPORT) || defined(CONFIG_NF_CONNTRACK) ++ typedef struct nf_conn PPA_SESSION; ++ #else ++ typedef struct ip_conntrack PPA_SESSION; ++ #endif ++ ++ ++/*! ++ \brief Macro that specifies PPA network interface data structure ++ */ ++ typedef struct net_device PPA_NETIF; ++ ++ /*! ++ \brief Macro that specifies PPA network interface status structure ++ */ ++ typedef struct net_device_stats PPA_NETIF_STATS; ++ ++ ++/*! ++ \brief This is the data structure for the PPA ATM VC structure. In Linux, this is defined to the Linux atm_vcc structure ++ */ ++ typedef struct atm_vcc PPA_VCC; ++ ++/*! ++ \brief PPA synchronization primitive for exclusion and/or synchronization ++*/ ++ typedef struct mutex PPA_LOCK; ++ ++/*! ++ \brief PPA memory pool cache for efficient allocation of PPA data structures. Can be mapped to ++ suitable OS allocation logic ++*/ ++ typedef struct kmem_cache PPA_MEM_CACHE; ++ ++/*! ++ \brief PPA Timer data structure. Should allow one shot timers to be configured with a passed ++ timer callback function ++*/ ++ typedef struct timer_list PPA_TIMER; ++ ++/*! ++ \brief PPA atomic timer structure. In linux, it is atomic_t structure. ++*/ ++ typedef atomic_t PPA_ATOMIC; ++ /*! ++ \brief PPA SIZE_T. For Linux OS, the size_t is unsigned int. ++*/ ++ typedef size_t PPA_SIZE_T; ++/*! ++ \brief PPA FILE PPA_FILE_OPERATIONS. For Linux OS, it is file_operations ++*/ ++ typedef struct file_operations PPA_FILE_OPERATIONS; ++ ++/*! ++ \brief PPA sync. For Linux OS, it is __sync ++ \note, someties GCC will wrongly optimize the code, so __sync is used to avoid it. \n ++ otherwise, just define PPA_SYNC to do { } while(0) ++*/ ++ ++ #define PPA_SYNC __sync ++ ++#if defined(CONFIG_IFX_PMCU) || defined(CONFIG_IFX_PMCU_MODULE) ++/*! ++ \brief PPA POWER MANAGEMENT RETURN VALUE. ++*/ ++ typedef IFX_PMCU_STATE_t PPA_PWM_STATE_t; ++ ++/*! ++ \brief PPA POWER MANAGEMENT RETURN VALUE. ++*/ ++ typedef IFX_PMCU_RETURN_t PPA_PWM_RETURN_t; ++ ++/*! ++ \brief PPA POWER MANAGEMENT MODUE STATE VALUE. ++*/ ++ typedef IFX_PMCU_MODULE_STATE_t PPA_PWM_MODULE_STATE_t; ++#endif //end of CONFIG_IFX_PMCU ++ ++#endif ++ ++ ++ ++/* ++ * #################################### ++ * Inline Functions ++ * #################################### ++ */ ++ ++ ++ ++/* ++ * #################################### ++ * Declaration ++ * #################################### ++ */ ++/** \addtogroup PPA_ADAPTATION_LAYER */ ++/*@{*/ ++ ++#ifdef __KERNEL__ ++/*! \brief Get the ppa adaption layer version ++ \param[in] p_family Pointer to the hardware family ++ \param[in] p_type Pointer to hardware type ++ \param[in] p_if Pointer interface ++ \param[in] p_mode Pointer mode ++ \param[in] p_major Pointer major version number ++ \param[in] p_mid Pointer to min version number ++ \param[in] p_minor Pointer to minor version number ++ \note Provide anything required to put in remark section. ++*/ ++ void ppa_get_stack_al_id(uint32_t *p_family, ++ uint32_t *p_type, ++ uint32_t *p_if, ++ uint32_t *p_mode, ++ uint32_t *p_major, ++ uint32_t *p_mid, ++ uint32_t *p_minor); ++ ++/*! \brief Get the PPA session according to PPA_BUF ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return returns the PPA session pointer if found, otherwise return NULL ++*/ ++ PPA_SESSION *ppa_get_session(PPA_BUF *ppa_buf); ++ ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32) ++ ++/*! \brief Get the PPA buffer network protocol header. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return point to the network header. ++ \note Provide anything required to put in remark section. ++*/ ++ uint8_t *skb_network_header(const PPA_BUF *ppa_buf); ++ ++ ++/*! \brief Get the PPA buffer transport protocol header. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return point to the transport protocol header. ++ \note Provide anything required to put in remark section. ++*/ ++// uint8_t *skb_transport_header(const PPA_BUF *ppa_buf); ++ ++ ++/*! \brief Get the PPA buffer MAC header. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return point to the MAC header. ++ \note Provide anything required to put in remark section. ++*/ ++ uint8_t *skb_mac_header(const PPA_BUF *ppa_buf); ++ ++ ++/*! \brief Get the PPA buffer IPv6 packet's header. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return point to the IPv6 header structure. ++ \note Provide anything required to put in remark section. ++*/ ++ struct ipv6hdr *ipv6_hdr(const PPA_BUF *ppa_buf); ++ ++ ++/*! \brief Get the PPA buffer IPv4 packet's header. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return point to the IPv4 header structure. ++ \note Provide anything required to put in remark section. ++*/ ++ struct iphdr *ip_hdr(const PPA_BUF *ppa_buf); ++ ++/*! \brief Returns if the IPv4 address is an IPv4 multicast packet. ++ \param[in] addr IPv4 address value. ++ \return This function returns the one of the following values: \n ++ - IFX_TRUE if the packet is a IPv4 multicast packet. \n ++ - IFX_FALSE otherwise. \n ++ \note Provide anything required to put in remark section. ++*/ ++ uint32_t ipv4_is_multicast(uint32_t addr); ++ ++ ++#endif /*LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22)*/ ++ ++ ++#if defined(CONFIG_IFX_PPA_IPv6_ENABLE) && (defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)) ++ ++ ++/*! \brief Get the PPA buffer IPv6 transport protocol. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return transport protocol value. ++ \note Provide anything required to put in remark section. ++*/ ++ uint8_t ppa_get_ipv6_l4_proto(PPA_BUF *ppa_buf); ++ ++ ++/*! \brief Get the PPA buffer IPv6 packet's Type of Service value. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return Type of Service value. ++ \note Provide anything required to put in remark section. ++*/ ++ uint8_t ppa_get_ipv6_tos(PPA_BUF *ppa_buf); ++ ++ ++/*! \brief Get the PPA buffer IPv6 packet's source IP address. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return source IP address value. ++ \note Provide anything required to put in remark section. ++*/ ++ PPA_IPADDR ppa_get_ipv6_saddr(PPA_BUF *ppa_buf); ++ ++ ++/*! \brief Get the PPA buffer IPv6 packet's destination IP address. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return destination IP address value. ++ \note Provide anything required to put in remark section. ++*/ ++ PPA_IPADDR ppa_get_ipv6_daddr(PPA_BUF *ppa_buf); ++ ++ ++/*! \brief Returns if the packet pointed to by ppa_buf is an IPv6 multicast packet. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return This function returns the one of the following values: \n ++ - IFX_TRUE if the packet is an IPv6 multicast packet. \n ++ - IFX_FALSE otherwise. \n ++ \note Provide anything required to put in remark section. ++*/ ++ int32_t ppa_is_ipv6_multicast(PPA_BUF *ppa_buf); ++ ++ ++/*! \brief Returns if the packet pointed to by ppa_buf is an IPv6 fragment packet. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return This function returns the one of the following values: \n ++ - IFX_TRUE if the packet is an IPv6 fragment packet. \n ++ - IFX_FALSE otherwise. \n ++ \note Provide anything required to put in remark section. ++*/ ++ uint32_t ppa_is_ipv6_fragment(PPA_BUF *ppa_buf); ++ ++#endif /*CONFIG_IFX_PPA_IPv6_ENABLE*/ ++ ++ ++/*! \brief return the judgement of IPv6 packet type check. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return The function returns one of the following. \n ++ - IFX_TRUE, if the packet is an IPv6 packet. \n ++ - IFX_FALSE, if the packet is not an IPv6 packet. ++ \note Provide anything required to put in remark section. ++*/ ++ uint8_t ppa_is_pkt_ipv6(const PPA_BUF *ppa_buf); ++ ++ ++/*! \brief Get the PPA buffer IPv4 packet's transport protocol value. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return transport protocol value. ++ \note Provide anything required to put in remark section. ++*/ ++ uint8_t ppa_get_ip_l4_proto(PPA_BUF *ppa_buf); ++ ++ ++/*! \brief Get the PPA buffer IPv4 packet's Type of Service value. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return Type of Service value. ++ \note Provide anything required to put in remark section. ++*/ ++ uint8_t ppa_get_ip_tos(PPA_BUF *ppa_buf); ++ ++ ++/*! \brief Get the PPA buffer IPv4 packet's source IP address. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return source IP address value. ++ \note Provide anything required to put in remark section. ++*/ ++ PPA_IPADDR ppa_get_ip_saddr(PPA_BUF *ppa_buf); ++ ++ ++/*! \brief Get the PPA buffer IPv4 packet's destination IP address. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return destination IP address value. ++ \note Provide anything required to put in remark section. ++*/ ++ PPA_IPADDR ppa_get_ip_daddr(PPA_BUF *ppa_buf); ++ ++ ++/*! \brief Returns if the packet pointed to by ppa_buf is an IPv4 multicast packet. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return This function returns the one of the following values: \n ++ - IFX_TRUE if the packet is an IPv4 multicast packet. \n ++ - IFX_FALSE otherwise. \n ++ \note Provide anything required to put in remark section. ++*/ ++ int32_t ppa_is_ip_multicast(PPA_BUF *ppa_buf); ++ ++ ++/*! \brief Returns if the packet pointed to by ppa_buf is an IPv4 fragment packet. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return This function returns the one of the following values: \n ++ - IFX_TRUE if the packet is an IPv4 fragment packet. \n ++ - IFX_FALSE otherwise. \n ++ \note Provide anything required to put in remark section. ++*/ ++ uint32_t ppa_is_ip_fragment(PPA_BUF *ppa_buf); ++ ++ ++/*! \brief Turn the given IP to string and put it to the given buffer. ++ \param[in] ppa_ip the source ip address ++ \param[in] flag the flag of ipv6 or ipv4: 1--ipv6, 0-ipv4 ++ \param[out] strbuf contains the string format of IP ( the storage buffer should be allocated before calling the api). ++ \return return the point to the given buffer. ++ \note Provide anything required to put in remark section. ++*/ ++ int8_t *ppa_get_pkt_ip_string(PPA_IPADDR ppa_ip, uint32_t flag, int8_t *strbuf); ++ ++ ++/*! \brief Turn the given MAC address to string and put it to the given buffer. ++ \param[in] *mac point to MAC address buffer. ++ \param[out] *strbuf contains the string format of MAC. ++ \return return the point to the given buffer. ++ \note Provide anything required to put in remark section. ++*/ ++ int8_t *ppa_get_pkt_mac_string(uint8_t *mac, int8_t *strbuf); ++ ++ ++/*! \brief return the length of IP address. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return return the number of bytes of the length of IP address. ++ \note Provide anything required to put in remark section. ++*/ ++ uint32_t ppa_get_pkt_ip_len(PPA_BUF *ppa_buf); ++ ++ ++ ++/*! \brief Get the PPA buffer IP protocol ++ \param[in] buf Pointer to the packet buffer. ++ \return The return value can be IP protocol value between 0-255. A value of 0 ++ \note Provide anything required to put in remark section. ++*/ ++ uint8_t ppa_get_pkt_ip_proto(PPA_BUF *buf); ++ ++ ++ ++/*! \brief Get the PPA buffer IP Type of Service field. ++ \param[in] buf Pointer to the packet buffer. ++ \return The return value is IP header ToS value. ++ \note ++*/ ++ uint8_t ppa_get_pkt_ip_tos(PPA_BUF *buf); ++ ++ ++ ++/*! \brief Returns source IP address of the packet. ++ \param[in] buf Pointer to the Packet buffer. ++ \return The Source IP address of the packet. ++ \note ++*/ ++ PPA_IPADDR ppa_get_pkt_src_ip(PPA_BUF *buf); ++ ++ ++ ++/*! \brief Will return source IP address of a packet, it is enhancement of ppa_get_pkt_src_ip in the sense that it can be. nvoked from both Layer 2 and Layer 3. If the source IP address it multicast one it will return 0. ++ \param[in] buf Pointer to the packet buffer. ++ \return The Source IP address of the packet. ++ \note ++*/ ++ IPADDR ppa_get_pkt_src_ip2(PPA_BUF *buf); ++ ++ ++ ++/*! \brief Returns destination IP address of the packet. ++ \param[in] buf Pointer to the packet buffer. ++ \return The Destination IP address of the packet.. ++ \note ++*/ ++ PPA_IPADDR ppa_get_pkt_dst_ip(PPA_BUF *buf); ++ ++ ++/*! \brief Returns source TCP/UDP port of the IP packet. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return TCP/UDP Source Port of the packet. ++ \note ++*/ ++ uint16_t ppa_get_pkt_src_port(PPA_BUF *ppa_buf); ++ ++ ++/*! \brief Returns destination TCP/UDP port of the packet. ++ \param[in] ppa_buf Pointer to the PPA packet buffer. ++ \return TCP/UDP Destination Port of the packet. ++ \note ++*/ ++ uint16_t ppa_get_pkt_dst_port(PPA_BUF *ppa_buf); ++ ++ ++/*! \brief Get the Source MAC address of the packet as received by the router. ++ \param[in] ppa_buf Pointer to the PPA packet buffer. ++ \param[out] mac MAC address buffer in which the source MAC address is copied by the function. ++ \return This function does not return anything. ++ \note This API may not implemented on older PPA version. ++*/ ++ void ppa_get_pkt_rx_src_mac_addr(PPA_BUF *ppa_buf, uint8_t mac[PPA_ETH_ALEN]); ++ ++ ++/*! \brief Get the Destination MAC address of the packet as received by the router. ++ \param[in] ppa_buf Pointer to the PPA packet buffer. ++ \param[out] mac MAC address buffer in which the Destination MAC address is copied by the function. ++ \return This function does not return anything. ++ \note This API may not implemented on older PPA version. ++*/ ++ void ppa_get_pkt_rx_dst_mac_addr(PPA_BUF *ppa_buf, uint8_t mac[PPA_ETH_ALEN]); ++ ++ ++/*! \brief Returns source (i.e. Received) interface of the packet at the router. ++ \param[in] ppa_buf Pointer to the PPA packet buffer. ++ \return Pointer to the Source /Rx Interface of the packet. The following values can be returned.\n ++ - NULL on error ++ - Pointer to Rx interface of the packet ++ \note This API may not implemented on older PPA version. ++*/ ++ PPA_NETIF *ppa_get_pkt_src_if(PPA_BUF *ppa_buf); ++ ++ ++/*! \brief Returns Destination (i.e. Tx) interface of the packet at the router (for packets forwarded at IP or bridge level). ++ \param[in] ppa_buf Pointer to the PPA packet buffer. ++ \return Pointer to the Destination /Tx Interface of the packet. The following values can be returned.\n ++ - NULL on error ++ - Pointer to Rx interface of the packet ++ \note This API may not implemented on older PPA version. ++*/ ++ PPA_NETIF *ppa_get_pkt_dst_if(PPA_BUF *ppa_buf); ++ ++/*! \brief Returns skb priority of the packet at the router (for packets forwarded at IP or bridge level). ++ \param[in] ppa_buf Pointer to the PPA packet buffer. ++ \return Pointer to the Destination /Tx Interface of the packet. The following values can be returned.\n ++ - NULL on error ++ - Pointer to Rx interface of the packet ++*/ ++uint32_t ppa_get_pkt_priority(PPA_BUF *ppa_buf); ++ ++/*! \brief set new skb priority of the packet: for test purpose only ++ \param[in] ppa_buf Pointer to the PPA packet buffer. ++ \param[in] new_pri new skb priority value ++ \return new priority if sucessful. otherwise return -1; ++*/ ++uint32_t ppa_set_pkt_priority(PPA_BUF *ppa_buf, uint32_t new_pri); ++ ++ ++/*! ++ \brief get ppoe mac address and session id ++ \param[in] netif Pointer to pppoe network interface. ++ \param[out] *pa Pointer to pppoe addres. ++ \return Pointer to the Destination /Tx Interface of the packet. The following values can be returned.\n ++ - NULL on error ++ - Pointer to Rx interface of the packet ++ \note This API may not implemented on older PPA version. ++*/ ++ int32_t ppa_pppoe_get_pppoe_addr(PPA_NETIF *netif, struct pppoe_addr *pa); ++ ++ ++ ++/*! \brief Returns the PPPoE session Id of the net interface structure. ++ \param[in] netif Pointer network interface structure. ++ \return The return value can be any one of the following:\n ++ - Non-zero value is PPPoE Session Id ++ - Zero indicates no valid PPPoE session. ++ \note ++*/ ++__u16 ppa_pppoe_get_pppoe_session_id(PPA_NETIF *netif); ++ ++ ++/*! \brief Returns the PPPoE session Id of the packet. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \return The return value can be any one of the following:\n ++ - Non-zero value is PPPoE Session Id. \n ++ - Zero indicates no valid PPPoE session i.e. not a PPPoE session packet. ++ \note ++*/ ++ __u16 ppa_get_pkt_pppoe_session_id(PPA_BUF *ppa_buf); ++ ++ ++/*! \brief get the pppoe's sub ethernet interface name ++ \param[in] netif Pointer to ppp network interface ++ \param[out] pppoe_eth_ifname Provide buffer to store its sub ethernet interface name ++ \return The return value can be any one of the following:\n ++ - Non-zero fail to get its sub ethernet interface name \n ++ - Zero indicates succeed ++ \note ++*/ ++ int32_t ppa_pppoe_get_eth_netif(PPA_NETIF *netif, PPA_IFNAME pppoe_eth_ifname[PPA_IF_NAME_SIZE]); ++ ++ ++ ++/*! \brief This function returns the physical or underlying interface (Ethernet-like) for a PPPoE interface specified by netif.. ++ \param[in] netif Pointer to the network interface structure in the stack. ++ \param[in] ifname Pointer to the network interface name. ++ \param[out] phy_ifname Interface name buffer in which the Physical interface name is copied by the function. ++ \return The return value can be any one of the following:\n ++ - IFX_SUCCESS, if PPPoE physical address retrieved ok ++ - IFX_FAILURE, on error ++ \note ++*/ ++ int32_t ppa_pppoe_get_physical_if(PPA_NETIF *netif, PPA_IFNAME *ifname, PPA_IFNAME phy_ifname[PPA_IF_NAME_SIZE]); ++ ++ ++/*! \brief check whether it is a ppp interface ++ \param[in] netif Pointer to the network interface structure in the stack. ++ \return The return value can be any one of the following:\n ++ - IFX_SUCCESS, on success. \n ++ - IFX_FAILURE, on error. ++ \note This API may not implemented on older PPA version. ++*/ ++ uint32_t ppa_check_is_ppp_netif(PPA_NETIF *netif); ++ ++/*! \brief check whether it is a pppoe interface ++ \param[in] netif Pointer to the network interface structure in the stack. ++ \return The return value can be any one of the following:\n ++ - IFX_SUCCESS, on success. \n ++ - IFX_FAILURE, on error. ++ \note This API may not implemented on older PPA version. ++*/ ++ uint32_t ppa_check_is_pppoe_netif(PPA_NETIF *netif); ++ ++/*! \brief get pppoe's destination mac address, ie, remote peer's mac address ++ \param[in] netif Pointer to the network interface structure in the stack. ++ \param[out] mac provide buffer to store desnation mac address ++ \return The return value can be any one of the following:\n ++ - IFX_SUCCESS, on success. \n ++ - IFX_FAILURE, on error. ++ \note This API may not implemented on older PPA version. ++*/ ++ int32_t ppa_pppoe_get_dst_mac(PPA_NETIF *netif , uint8_t mac[PPA_ETH_ALEN]); ++ ++ ++/*! \brief This function returns the destination MAC address to be used in the Ethernet frame when transmitted out of the router. ++ \param[in] ppa_buf Pointer to the packet buffer. ++ \param[in] p_session Pointer to the NAT connection tracking session to which the packet belongs. This parameter may not be required in the function implementation, for eg. on Linux 2.4 adaptation. ++ \param[out] mac The destination MAC address for the specific packet is copied into this field. ++ \return The return value can be any one of the following: \n ++ - IFX_SUCCESS, if destination MAC address is retrieved ok \n ++ - IFX_FAILURE, on error ++ \note ++*/ ++ int32_t ppa_get_dst_mac(PPA_BUF *ppa_buf, PPA_SESSION *p_session, uint8_t mac[PPA_ETH_ALEN]); ++ ++ ++ ++/*! \brief Returns the pointer to network interface data structure in the stack for the specified interface name. For Linux, this is the netdevice structure pointer. ++ \param[in] ifname Pointer to the interface name. ++ \return The return value can be any one of the following: \n ++ - Pointer to network interface structure, on success. \n ++ - NULL on error. ++ \note This function needs to ensure that it has a handle / reference count to the network interface structure, so that the interface structure cannot be deleted while the PPA has a reference to it. Please see the section Release Reference to network interface structure for the function to release the PPA's reference to the PPA_NETIF structure when done. ++*/ ++ PPA_NETIF *ppa_get_netif(PPA_IFNAME *ifname); ++ ++ ++/*! \brief This function releases the reference to a PPA_NETIF structure obtained through the function ppa_get_netif. ++ \param[in] netif Pointer to the netif structure. ++ \return No return value. ++ \note ++*/ ++ void ppa_put_netif(PPA_NETIF *netif); ++ ++ ++ ++/*! \brief Get the MAC address of the specified interface of the router. It is valid for an Ethernet-like interface or a PPPoE interface bound to the former. ++ \param[in] netif Pointer to the network interface structure. ++ \param[out] mac MAC address buffer in which the MAC address of the interface is copied by the function if its an Ethernet like interface. ++ \return No return value. ++ \note This API may not implemented on older PPA version. ++*/ ++ int32_t ppa_get_netif_hwaddr(PPA_NETIF *netif, uint8_t mac[PPA_ETH_ALEN]); ++ ++ ++ ++ /*! \brief Returns the pointer to the interface name for the specified netif structure. ++ \param[in] netif Pointer to the network interface structure. ++ \return The return value can be any one of the following: \n ++ - Pointer to interface name, on success. \n ++ - NULL on error. ++ \note ++*/ ++ PPA_IFNAME *ppa_get_netif_name(PPA_NETIF *netif); ++ ++ ++ ++ ++ /*! \brief Returns true if both the netif structure points to same physical interface. ++ \param[in] netif1 Pointer to the first network interface structure. ++ \param[in] netif2 Pointer to the second network interface structure. ++ \return Valid values are below. \n ++ - IFX_TRUE, if netif1 is same as netif2 interface \n ++ - IFX_FALSE, if interface are not equal \n ++ \note ++*/ ++uint32_t ppa_is_netif_equal(PPA_NETIF *netif1, PPA_NETIF *netif2); ++ ++ ++ ++ ++ /*! \brief This function returns if the Network interface structure pointer corresponds to the interface name specified. ++ \param[in] netif Pointer to the network interface structure. ++ \param[in] ifname Pointer to the network interface name. ++ \return The function returns one of the following. \n ++ - IFX_TRUE, if the netif corresponds to the ifname. \n ++ - IFX_FALSE, if the netif is not for the ifname. ++ \note This API may not implemented on older PPA version. ++*/ ++ uint32_t ppa_is_netif_name(PPA_NETIF *netif, PPA_IFNAME *ifname); ++ ++ ++/*! \brief This function checks if the interface name prefix specified applies for the interface name of the specified PPA_NETIF structure. For eg., eth0 and eth1 both have network prefix of eth (n=3). ++ \param[in] netif Pointer to the network interface structure. ++ \param[in] ifname_prefix Pointer to the network interface name prefix. ++ \param[in] n Number of bytes of the prefix to compare with the interface name of the netif. ++ \return The function returns one of the following. \n ++ - IFX_TRUE, if the netif corresponds to the ifname prefix. \n ++ - IFX_FALSE, if the netif is not matching the ifname prefix. ++ \note This API may not implemented on older PPA version. ++*/ ++ ++ uint32_t ppa_is_netif_name_prefix(PPA_NETIF *netif, PPA_IFNAME *ifname_prefix, int32_t n); ++ ++ ++ ++/*! \brief Get the Physical or underlying Interface for the interface specified by netif or ifname pointers. If netif is specified, it is used for the lookup, else ifname is used. ++ \param[in] netif Pointer to the network interface structure for which physical interface needs to be determined. ++ \param[in] ifname Pointer to the network interface name for which physical interface needs to be determined. ++ \param[in] phy_ifname Interface name buffer in which the Physical interface name is copied by the function. ++ \return This function returns the following values. \n ++ - IFX_SUCCESS, on success. \n ++ - IFX_FAILURE, on error. \n ++ \note This API may not implemented on older PPA version. ++*/ ++ int32_t ppa_get_physical_if(PPA_NETIF *netif, PPA_IFNAME *ifname, PPA_IFNAME phy_ifname[PPA_IF_NAME_SIZE]); ++ ++ ++ ++/*! \brief This function gives the vlan interface name specified by netif strucutre or ifname pointers. One of the two arguments needs to be specified in the function. ++ \param[in] netif Pointer to the network interface structure for VLAN interface check is to be done. ++ \param[in] ifname Pointer to the network interface name for which VLAN check is to be done. ++ \param[in] vlan_ifname Buffer where the vlan interface name is copied by the function. ++ \return The function returns one of the following. \n ++ - IFX_TRUE, if the interface exist. \n ++ - IFX_FALSE, if the interface doesn't exist. ++ \note ++*/ ++ int32_t ppa_get_underlying_vlan_if(PPA_NETIF *netif, PPA_IFNAME *ifname, PPA_IFNAME vlan_ifname[PPA_IF_NAME_SIZE]); ++ ++ ++ ++/*! \brief This function checks whether the interface specified by netif or ifname pointers is a VLAN interface. One of the two arguments needs to be specified in the function. ++ \param[in] netif Pointer to the network interface structure for VLAN interface check is to be done. ++ \param[in] ifname Pointer to the network interface name for which VLAN check is to be done. ++ \return This function returns the following values. \n ++ - IFX_SUCCESS, if the VLAN interface exist. \n ++ - IFX_FALSE, if the interface is does not exist. ++ \note ++*/ ++ int32_t ppa_if_is_vlan_if(PPA_NETIF *netif, PPA_IFNAME *ifname); ++ ++ ++ ++/*! \brief This function returns the physical or underlying interface (Ethernet-like) for a pseudo VLAN interface specified by netif structure or interface name. ++ \param[in] netif Pointer to the VLAN net interface structure. ++ \param[in] ifname Pointer to the VLAN interface name for which underlying interface is to be determined ++ \param[out] phy_ifname Buffer where the physical/underlying interface is copied by the function for the VLAN interface ifname. ++ \return This function returns the following values. \n ++ - IFX_TRUE, if the interface is a VLAN interface \n ++ - IFX_FAILURE, if the interface is not a VLAN interface ++ \note ++*/ ++ int32_t ppa_vlan_get_underlying_if(PPA_NETIF *netif, PPA_IFNAME *ifname, PPA_IFNAME phy_ifname[PPA_IF_NAME_SIZE]); ++ ++ ++ ++ ++/*! \brief This function returns the physical or underlying interface (Ethernet-like) for a pseudo VLAN interface specified by netif structure or interface name. ++ \param[in] netif Pointer to the VLAN network interface structure. ++ \param[in] ifname Pointer to the VLAN interface name for which underlying interface is to be determined. ++ \param[out] phy_ifname Buffer where the physical/underlying interface is copied by the function for the VLAN interface. ++ \return This function returns the following values. \n ++ - IFX_SUCCESS, if the VLAN interface exist \n ++ - IFX_FAILURE, if the interface is does not exist\n ++ \note ++*/ ++ int32_t ppa_vlan_get_physical_if(PPA_NETIF *netif, PPA_IFNAME *ifname, PPA_IFNAME phy_ifname[PPA_IF_NAME_SIZE]); ++ ++ ++ ++/*! \brief This function returns the VLAN Id and tag info for a VLAN interface specified by netif. This includes the VLAN tag, 802.1P bits and the CFI bit. The caller will first determine if the network interface is a VLAN interface before invoking this function. ++ \param[in] netif Pointer to the network interface structure for which VLANId is to be returned. ++ \return This function returns the VLAN TCI (Tag control information). ++ \note ++*/ ++ uint32_t ppa_get_vlan_id(PPA_NETIF *netif); ++ ++ ++ ++ ++/*! \brief This function returns the TCI including priority and VLAN Id for a PPA buffer pointer by buf. ++ \param[in] buf Pointer to PPA buffer. ++ \return This function returns the VLAN TCI (Tag control information). ++ \note ++*/ ++ uint32_t ppa_get_vlan_tag(PPA_BUF *buf); ++ ++ ++ ++/*! \brief This function returns whether the interface specified by ifname or netif pointer is enslaved to a bridge, i.e. member of a bridge. ++ \param[in] ifname Pointer to the network interface name for which bridge membership has to be determined. ++ \param[in] netif Pointer to the network interface structure for which bridge membership is to be determined. ++ \return This function returns the one of the following values: \n ++ - IFX_TRUE, if the network interface is enslaved to a bridge. \n ++ - IFX_FALSE, if the network interface is not enslaved to a bridge. ++ \note ++*/ ++ int32_t ppa_is_netif_bridged(PPA_IFNAME *ifname, PPA_NETIF *netif); ++ ++ ++ #ifdef NO_DOXY ++ int32_t ppa_get_bridge_member_ifs(PPA_IFNAME *ifname, int *, PPA_IFNAME **); ++ #endif ++ ++/*! \brief This function returns whether the interface specified by ifname or netif pointer is a bridge interface, i.e. other interfaces are enslaved to this bridge interface. For eg., br0 is a bridge interface in Linux which may have bridge members like eth0, nas0 etc. ++ \param[in] netif Pointer to the network interface structure for which bridge interface check is to be done. ++ \param[in] ifname Pointer to the network interface name for which bridge interface check is to be done. ++ \return This function returns the one of the following values: \n ++ - IFX_TRUE, if the network interface is a bridge interface/port. \n ++ - IFX_FALSE, if the network interface is not a bridge interface/port. ++ \note ++*/ ++ int32_t ppa_if_is_br_if(PPA_NETIF *netif, PPA_IFNAME *ifname); ++ ++ ++/*! \brief This function performs a bridge forwarding database lookup for the bridge specified by netif and returns the member interface on which the packet needs to be forwarded. ++ \param[in] netif Pointer to the network interface structure for the bridge interface where destination lookup is to be performed. ++ \param[in] buf Pointer to the packet buffer for the frame which has to be bridged (forwarded at Layer-2). ++ \param[out] p_netif Pointer to the bridge member network interface structure to which the packet needs to be forwarded. ++ \return This function returns the one of the following values: \n ++ - IFX_SUCCESS, if the lookup is successful in the bridge forwarding database. \n ++ - IFX_FAILURE, if the lookup is not successful.\n ++ \note ++*/ ++ int32_t ppa_get_br_dst_port(PPA_NETIF *netif, PPA_BUF *buf, PPA_NETIF **p_netif); ++ ++ ++ ++/*! \brief This function performs a bridge forwarding database lookup for the bridge specified by netif and returns the member interface on which the packet needs to be forwarded. ++ \param[in] netif Pointer to the network interface structure for the bridge interface where destination lookup is to be performed. ++ \param[in] mac Pointer to destination mac address. ++ \param[out] p_netif Pointer to the bridge member network interface structure to which the packet needs to be forwarded. ++ \return This function returns the one of the following values: \n ++ - IFX_SUCCESS, if the lookup is successful in the bridge forwarding database. \n ++ - IFX_FAILURE, if the lookup is not successful. ++\note ++*/ ++ int32_t ppa_get_br_dst_port_with_mac(PPA_NETIF *netif, uint8_t mac[PPA_ETH_ALEN], PPA_NETIF **p_netif); ++ ++ ++/*! \brief This function returns the PPA ATM VC structure for the EoATM (RFC 2684 Ethernet over ATM) interface specified by netif. ++ \param[in] netif Pointer to the network interface structure for the bridge interface where destination lookup is to be performed. ++ \param[in] pvcc Pointer to the pointer to PPA_VCC structure which is set to the VC associated with the EoATM interface specified by netif. ++ \return This function returns the one of the following values: \n ++ - IFX_SUCCESS, if the VCC structure is found for the EoATM interface \n ++ - IFX_FAILURE, on error ++\note ++*/ ++ int32_t ppa_br2684_get_vcc(PPA_NETIF *netif, PPA_VCC **pvcc); ++ ++ ++ ++ ++ /*! \brief This function checks if the interface specified by netif or ifname pointers is an EoATM interface as per RFC2684. The interface will be specified by passing one of netif and ifname in the call. ++ \param[in] netif Pointer to the network interface structure for the EoATM check is to be performed. ++ \param[in] ifname Pointer to the interface name for which the EoATM check is to be performed. ++ \return This function returns the one of the following values: \n ++ - IFX_TRUE, if the interface is an EoATM interface. \n ++ - IFX_FALSE, if the interface is not an EoATM interface. \n ++\note ++*/ ++int32_t ppa_if_is_br2684(PPA_NETIF *netif, PPA_IFNAME *ifname); ++ ++/*! \brief This function checks if the interface specified by netif or ifname pointers is bridged or routed encapsulaton. ++ \param[in] netif Pointer to the network interface structure for the check is to be performed. ++ \param[in] ifname Pointer to the interface name for which the check is to be performed. ++ \return This function returns the one of the following values: \n ++ - IFX_SUCCESS, Interface is enabled with IP encapsulation. \n ++ - IFX_FAILURE, Error. ++\note ++*/ ++int32_t ppa_if_is_ipoa(PPA_NETIF *netif, PPA_IFNAME *ifname); ++ ++ ++ ++/*! \brief This function returns the PPA ATM VC structure for the PPPoA (RFC 2364 PPP over AAL5) interface specified by netif. ++ \param[in] netif Pointer to the network interface structure for the bridge interface where destination lookup is to be performed. ++ \param[out] patmvcc Pointer to the pointer to PPA_VCC structure which is set to the VC associated with the PPPoATM interface specified by netif. ++ \return This function returns the one of the following values: \n ++ - IFX_SUCCESS, if the VCC structure is found for the PPPoATM interface. \n ++ - IFX_FAILURE, on error. ++\note ++*/ ++int32_t ppa_pppoa_get_vcc(PPA_NETIF *netif, PPA_VCC **patmvcc); ++ ++ ++/*! \brief check whether it is a pppoa session. ++ \param[in] netif Pointer to the interface's netif ++ \param[in] ifname Pointer to interface name ++ \return This function returns the one of the following values: \n ++ - IFX_TRUE if the two session pointers are the same. \n ++ - IFX_FALSE if the two session pointers point to different sessions. \n ++ \note, one of netif and ifname should be not NULL. ++*/ ++ int32_t ppa_if_is_pppoa(PPA_NETIF *netif, PPA_IFNAME *ifname); ++ ++ ++/*! \brief Returns true if the two sessions are the same. ++ \param[in] p_session1 Pointer to the PPA session 1. ++ \param[in] p_session2 Pointer to the PPA session 2. ++ \return This function returns the one of the following values: \n ++ - IFX_TRUE if the two session pointers are the same. \n ++ - IFX_FALSE if the two session pointers point to different sessions. \n ++\note ++*/ ++ uint32_t ppa_is_session_equal(PPA_SESSION *p_session1, PPA_SESSION *p_session2); ++ ++ ++ ++/*! \brief Get the Stack session Helper function for connection tracking. Such helper functions exist when a Connection tracking / SPI logic for the application protocol of that session. Examples are FTP control session, SIP signalling session etc. ++ \param[in] p_session Pointer to the PPA Session. ++ \return This function returns the one of the following values: \n ++ - Pointer to the session helper function as an uint32_t if helper exists. \n ++ - NULL otherwise. \n ++ \note The exact pointer of the session helper function is not of interest to PPA. Adaptations may just return IFX_TRUE if session has helper function, and return IFX_FALSE otherwise. ++*/ ++ uint32_t ppa_get_session_helper(PPA_SESSION *p_session); ++ ++ ++ ++/*! \brief Is the PPA session pointing to a special session which needs "slow path" handling due to protocol processing requirements of connection tracking, NAT or by any other criteria. Examples are FTP control session, SIP signalling session etc.The API can check the session based on either a PPA buffer pointer or a PPA session pointer. ++ \param[in] ppa_buf Pointer to the PPA Buffer. ++ \param[in] p_session Pointer to the PPA Session. ++ \return This function returns the one of the following values: \n ++ - IFX_TRUE if the session is a special session. \n ++ - IFX_FALSE otherwise\note. \n ++ \note ++*/ ++ uint32_t ppa_check_is_special_session(PPA_BUF *ppa_buf, PPA_SESSION *p_session); ++ ++ ++ ++/*! \brief Returns if the packet pointed to by ppa_buf is a fragmented IP datagram. ++ \param[in] ppa_buf Pointer to the PPA Buffer. ++ \return This function returns the one of the following values: \n ++ - IFX_TRUE if packet is fragment of an IP datagram. \n ++ - IFX_FALSE if the packet is a non-fragmented IP datagram. \n ++ \note ++*/ ++ uint32_t ppa_is_pkt_fragment(PPA_BUF *ppa_buf); ++ ++ ++ ++/*! \brief Returns if the packet pointed to by ppa_buf is addressed to the host (i.e. terminated inside the router). ++ \param[in] ppa_buf Pointer to the PPA Buffer. ++ \return This function returns the one of the following values: \n ++ - IFX_TRUE if packet is addressed to host, i.e. for host output. \n ++ - IFX_FALSE if the packet is to be forwarded out of the router. \n ++ \note ++*/ ++ int32_t ppa_is_pkt_host_output(PPA_BUF *ppa_buf); ++ ++ ++ ++/*! \brief Returns if the packet pointed to by ppa_buf is a broadcast packet. ++ \param[in] ppa_buf Pointer to the PPA Buffer. ++ \return This function returns the one of the following values: \n ++ - IFX_TRUE if packet is a broadcast packet. \n ++ - IFX_FALSE if the packet is not a broadcast packet. \n ++ \note ++*/ ++ int32_t ppa_is_pkt_broadcast(PPA_BUF *ppa_buf); ++ ++ ++ ++/*! \brief Returns if the packet pointed to by ppa_buf is a multicast packet. ++ \param[in] ppa_buf Pointer to the PPA Buffer. ++ \return This function returns the one of the following values: \n ++ - IFX_TRUE if the packet is a multicast packet. \n ++ - IFX_FALSE otherwise. \n ++ \note ++*/ ++ int32_t ppa_is_pkt_multicast(PPA_BUF *ppa_buf); ++ ++ ++ ++/*! \brief Returns if the packet pointed to by ppa_buf is a loopback packet, i.e. output to a loopback interface in the router (and not transmitted out of the router external interfaces). ++ \param[in] ppa_buf Pointer to the PPA Buffer. ++ \return This function returns the one of the following values: \n ++ - IFX_TRUE if packet is a loopback packet. \n ++ - IFX_FALSE if the packet is not a loopback packet \n ++ \note ++*/ ++ int32_t ppa_is_pkt_loopback(PPA_BUF *ppa_buf); ++ ++ ++ ++/*! \brief Returns if the packet pointed to by ppa_buf is for local delivery, i.e. ingress packet delivered to Layer-4 and above).. ++ \param[in] ppa_buf Pointer to the PPA Buffer. ++ \return This function returns the one of the following values: \n ++ - IFX_TRUE if packet is for local delivery to Layer-4 and above. \n ++ - IFX_FALSE if the packet is not a local delivery packet. \n ++ \note ++*/ ++ int32_t ppa_is_pkt_local(PPA_BUF *ppa_buf); ++ ++ ++ ++ /*! \brief Returns if the packet pointed to by ppa_buf is routed, i.e. forwarded at IP layer. ++ \param[in] ppa_buf Pointer to the PPA Buffer. ++ \return This function returns the one of the following values: \n ++ - IFX_TRUE if packet is forwarded at IP layer. \n ++ - IFX_FALSE if the packet is not forwarded at IP layer \n ++ \note ++*/ ++ int32_t ppa_is_pkt_routing(PPA_BUF *ppa_buf); ++ ++ ++ ++/*! \brief Returns if the packet pointed to by ppa_buf is multicast routed. ++ \param[in] ppa_buf Pointer to the PPA Buffer. ++ \return This function returns the one of the following values: \n ++ - IFX_TRUE if packet is multicast forwarded at IP layer. \n ++ - IFX_FALSE if the packet is not multicast forwarded at IP layer. \n ++ \note ++*/ ++ int32_t ppa_is_pkt_mc_routing(PPA_BUF *ppa_buf); ++ ++ ++ ++ /*! \brief Returns true if tcp connection state is established for a PPA session. ++ \param[in] p_session Pointer to ppa connection tracking session data structure. ++ \return This function returns the one of the following values: \n ++ - IFX_TRUE if TCP connection state is established after SYN from server. \n ++ - IFX_FALSE if TCP connection is not established completely. \n ++ \note ++*/ ++ int32_t ppa_is_tcp_established(PPA_SESSION *p_session); ++ ++ ++ /*! \brief check whether the TCP session is open or not. ++ \param[in] p_session Pointer to ppa connection tracking session data structure. ++ \return This function returns the one of the following values: \n ++ - 1 if the tcp state is not TIME_WAIT or error ++ - otherwise, return 0 ++ \note ++*/ ++ int32_t ppa_is_tcp_open(PPA_SESSION *p_session); ++ ++ ++ ++/*! \brief Initialize a lock for synchronization. ++ \param[in] p_lock Pointer to the PPA lock variable which is allocated by the caller. ++ \return This function returns the one of the following values: \n ++ - IFX_SUCCESS, if PPA Lock initialization is success. \n ++ - IFX_FAILURE, if the PPA Lock initialization fails. \n ++ \note ++*/ ++ int32_t ppa_lock_init(PPA_LOCK *p_lock); ++ ++/*! \brief Get or Acquire a PPA lock for synchronization. ++ \param[in] p_lock Pointer to the PPA lock variable which has been already initialized by the caller. ++ \return No value returned. ++ \note ++*/ ++ void ppa_lock_get(PPA_LOCK *p_lock); ++ ++ ++/*! \brief Release a PPA Lock acquired for synchronization. ++ \param[in] p_lock Pointer to the PPA lock variable which is to be released by the caller.. ++ \return No valure returned. ++ \note ++*/ ++ void ppa_lock_release(PPA_LOCK *p_lock); ++ ++ ++/*! \brief Destroy a PPA lock created with the ppa_lock_init API ++ \param[in] p_lock Pointer to the PPA lock variable which is allocated by the caller. ++ \return No valure returned. ++ \note ++*/ ++ void ppa_lock_destroy(PPA_LOCK *p_lock); ++ ++ ++/*! \brief Disable interrupt processing to protect certain PPA critical regions and save current interrupt state to a global variable in the AL. ++ \return No valure returned. ++ \note ++*/ ++uint32_t ppa_disable_int(void); ++ ++ ++/*! \brief Enable interrupt processing to protect certain PPA critical regions. This must actually restore interrupt status from the last ppa_disable_int call. ++ \param[in] flag Interrupt status flag. ++ \return No valure returned. ++ \note ++*/ ++void ppa_enable_int(uint32_t flag); ++ ++ ++/*! \brief This function dynamically allocates memory for PPA use. ++ \param[in] size Specifies the number of bytes to be allocated. ++ \return The return value is one of the following: \n ++ - Non-NULL value, if memory allocation is successful. \n ++ - NULL, if the PPA Lock initialization fails. \n ++ \note ++*/ ++ void *ppa_malloc(uint32_t size); ++ ++/*! \brief This function frees dynamically allocated memory. ++ \param[in] buff Pointer to buffer allocated by ppa_malloc routine, which needs to be freed. ++ \return The return value is one of the following: \n ++ - IFX_SUCCESS, if memory free is successful. \n ++ - IFX_FAILURE, if the memory free operation fails. \n ++ \note ++*/ ++ int32_t ppa_free(void *buff); ++ ++ ++ ++ /*! \brief This function dynamically allocates memory for a cache of objects of a fixed size for PPA use. ++ \param[in] name Specifies the name of the memory cache as a string. ++ \param[in] size Specifies the object size in bytes for the memory cache to be created. ++ \param[out] pp_cache Pointer to pointer to the memory cache to be created. *pp_cache is set by the function. ++ \return The return value is one of the following: \n ++ - IFX_SUCCESS value, if memory cache creation is successful. \n ++ - IFX_FAILURE, if the memory cache creation fails. \n ++ \note ++*/int32_t ppa_mem_cache_create(const char *name, uint32_t size, PPA_MEM_CACHE **pp_cache); ++ ++ ++ /*! \brief This function frees (or destroys) dynamically created memory cache using ppa_mem_cache_create API. ++ \param[in] p_cache Pointer to memory cache created by ppa_mem_cache_create routine, which needs to be destroyed. ++ \return The return value is one of the following: \n ++ - IFX_SUCCESS, if memory cache is destroyed. \n ++ - IFX_FAILURE, if the memory cache free operation fails \n ++ \note ++*/ ++int32_t ppa_mem_cache_destroy(PPA_MEM_CACHE *p_cache); ++ ++ ++/*! \brief This function allocates a memory cache object from the specified memory cache created using ppa_mem_cache_create API. ++ \param[in] p_cache Pointer to memory cache created by ppa_mem_cache_create routine, to which an object needs to be freed. ++ \return No return value. ++ \note ++*/ ++ void *ppa_mem_cache_alloc(PPA_MEM_CACHE *p_cache); ++ ++ ++/*! \brief This function frees (or returns) allocated memory cache object using ppa_mem_cache_alloc API back to the memory cache pool. ++ \param[in] buf Pointer to memory cache object allocated from memory cache pointed to by p_cache pointer. ++ \param[in] p_cache Pointer to memory cache created by ppa_mem_cache_create routine, which needs to be destroyed. ++ \return The return value is one of the following: \n ++ - IFX_SUCCESS, if memory cache is destroyed. \n ++ - IFX_FAILURE, if the memory cache free operation fails. \n ++ \note ++*/ ++void ppa_mem_cache_free(void *buf, PPA_MEM_CACHE *p_cache); ++ ++ ++/*! \brief This function does a byte copy from source buffer to destination buffer for the specified number of bytes. ++ \param[in] dst Pointer to destination buffer to copy to. ++ \param[in] src Pointer to source buffer to copy from. ++ \param[in] count Specifies the number of bytes to copy. ++ \return No return value. ++ \note ++*/ ++ void ppa_memcpy(void *dst, const void *src, uint32_t count); ++ ++ ++ /*! \brief This function does a byte set to destination buffer with the specified fill byte for the specified number of bytes.. ++ \param[in] dst Pointer to destination buffer to set bytes. ++ \param[in] fillbyte Byte value to fill in the destination buffer. ++ \param[in] count Specifies the number of bytes to set to fillbyte. ++ \return No return value. ++ \note ++*/ ++ void ppa_memset(void *dst, uint32_t fillbyte, uint32_t count); ++ ++ /*! \brief This function compares the memory areas buff1 and buff2 for specified number of bytes. ++ \param[in] buff1 Pointer to destination first buffer. ++ \param[in] buff2 Pointer to source second buffer. ++ \param[in] count Specifies the number of bytes to compare. ++ \return Returns an integer less than, equal to, or greater than zero if the first n bytes of buff1 is found, respectively, to be less than, to match, or be greater than the first n bytes of buff2. ++ \note ++*/ ++ int ppa_memcmp(const void *buff1, const void *buff2, size_t count); ++ ++/*! \brief This function initializes the PPA_TIMER structure and fills in the callback function which is to be invoked by the timer facility when the timer expires. The PPA timer facility is a "one-shot" timer and not a periodic one. ++ \param[in] p_timer Pointer to the PPA_TIMER structure allocated by caller. ++ \param[in] callback Timer callback function that is invoked when the timer expires. ++ \return The function returns one of the following values: \n ++ - IFX_SUCCESS, on success. \n ++ - IFX_FAILURE, on error. \n ++ \note ++*/ ++int32_t ppa_timer_init(PPA_TIMER *p_timer, void (*callback)(unsigned long)); ++ ++/*! \brief This function adds or installs a timer with the specified timer interval. ++ \param[in] p_timer Pointer to the initialized PPA_TIMER structure to be installed. ++ \param[in] timeout_in_sec Timer expiry interval in seconds after which the one-shot timer will fire. ++ \return The function returns one of the following values: \n ++ - IFX_SUCCESS, on success. \n ++ - IFX_FAILURE, on error. \n ++ \note ++*/ ++int32_t ppa_timer_add(PPA_TIMER *p_timer, uint32_t timeout_in_sec); ++ ++ ++/*! \brief This function deletes an install timer which has not yet expired. ++ \param[in] p_timer Pointer to the installed PPA_TIMER structure to be deleted. ++ \return The function returns one of the following values: \n ++ - IFX_SUCCESS, on successful deletion of the timer. \n ++ - IFX_FAILURE, on error (for eg., timer already expired, or invalid timer pointer). \n ++ \note ++*/ ++void ppa_timer_del(PPA_TIMER *p_timer); ++ ++ ++/*! \brief This function adds or installs a timer with the specified timer interval. ++ \return The function returns the following value: \n ++ - Current time in 10 milliseconds resolution. ++ \note ++*/ ++ uint32_t ppa_get_time_in_10msec(void); ++ ++/*! \brief This function returns the current time of the system in seconds. It can be the time since reboot of the system, or an absolute time wrt NTP synced world time. PPA uses this function for timing intervals or periods. ++ \return The function returns the following values: \n ++ - Current time in seconds \n ++ \note ++*/ ++ uint32_t ppa_get_time_in_sec(void); ++ ++ ++/*! \brief Read atomic variable. ++ \param[in] v Pointer to the PPA atomic variable which is to be read. ++ \return No return value. ++ \note ++*/ ++ int32_t ppa_atomic_read(PPA_ATOMIC *v); ++ ++/*! \brief Initialize the PPA atomic variable to specified value. ++ \param[in] v Pointer to the PPA atomic variable which is to be initalized. ++ \param[in] i Intended value to be set for atomic variable p_atomic. ++ \return No return value. ++ \note ++*/ ++ void ppa_atomic_set(PPA_ATOMIC *v, int32_t i); ++ ++/*! \brief Atomic Increment of variable. ++ \param[in] v Pointer to the PPA atomic variable which is to be incremented. ++ \return No return value. ++ \note ++*/ ++ int32_t ppa_atomic_inc(PPA_ATOMIC *v); ++ ++/*! \brief Atomic decrement of variable. ++ \param[in] v Pointer to the PPA atomic variable which is to be decremented. ++ \return No return value. ++ \note ++*/ ++int32_t ppa_atomic_dec(PPA_ATOMIC *v); ++ ++/*! \brief Used to perform buffer cloning. ++ \param[in] ppa_buf Pointer to ppa buffer. ++ \param[in] flags Reserved for future use. ++ \return The return value is the pointer to cloned PPA buffer structure. ++ \note ++*/ ++ PPA_BUF *ppa_buf_clone(PPA_BUF *ppa_buf, uint32_t flags); ++ ++ ++ ++/*! \brief Used to check if the buffer is cloned. ++ \param[in] ppa_buf Pointer to ppa buffer. ++ \return The return value is IFX_TRUE if the buffer is cloned and IFX_FLASE otherwise. ++ \note ++*/ ++int32_t ppa_buf_cloned(PPA_BUF *ppa_buf); ++ ++ ++/*! \brief get ppa prevous buffer ++ \param[in] ppa_buf Pointer to ppa buffer. ++ \return return the prevois buffer ++ \note ++*/ ++ PPA_BUF *ppa_buf_get_prev(PPA_BUF *ppa_buf); ++ ++/*! \brief get ppa next buffer ++ \param[in] ppa_buf Pointer to ppa buffer. ++ \return return the next buffer ++ \note ++*/ ++ PPA_BUF *ppa_buf_get_next(PPA_BUF *ppa_buf); ++ ++/*! \brief free ppa buffer ++ \param[in] ppa_buf Pointer to ppa buffer . ++ \note ++*/ ++ void ppa_buf_free(PPA_BUF *ppa_buf); ++ ++/*! \brief copy data from username to kernel ++ \param[out] to destination buffer ++ \param[in] from source buffer ++ \param[in] n bytes to copy ++ \note ++*/ ++ uint32_t ppa_copy_from_user(void *to, const void PPA_USER *from, uint32_t n); ++ ++/*! \brief copy data from kernel to username ++ \param[out] to destination buffer ++ \param[in] from source buffer ++ \param[in] n bytes to copy ++ \note ++*/ ++ uint32_t ppa_copy_to_user(void PPA_USER *to, const void *from, uint32_t n); ++ ++/*! \brief copy string, like strcpy ++ \param[out] dest destination buffer ++ \param[in] src source buffer ++ \note ++*/ ++ uint8_t *ppa_strcpy(uint8_t *dest, const uint8_t *src); ++ ++/*! \brief copy string, like strncpy ++ \param[out] dest destination buffer ++ \param[in] src source buffer ++ \param[in] n maximum bytes to copy ++ \note ++*/ ++ uint8_t *ppa_strncpy(uint8_t *dest, const uint8_t *src, PPA_SIZE_T n); ++ ++/*! \brief get string length, like strlen ++ \param[in] s string buffer ++ \return return the string length ++ \note ++*/ ++ PPA_SIZE_T ppa_strlen(const uint8_t *s); ++ ++/*! \brief shrink cache buffer. in linux, it is kmem_cache_shrink ++ \param[in] p_cache Pointer to cache buffer ++ \return return the string length ++ \note ++*/ ++ int32_t ppa_kmem_cache_shrink(PPA_MEM_CACHE *p_cache); ++ ++/*! \brief lookup symble. In linux, it is kallsyms_lookup ++ \note ++*/ ++ const uint8_t *ppa_kallsyms_lookup(uint32_t addr, uint32_t *symbolsize, uint32_t *offset, uint8_t **modname, uint8_t *namebuf); ++ ++/*! \brief register network device, in linux, it is register_netdev ++ \param[in] dev pointer to network device ++ \return ++ \note ++*/ ++ int32_t ppa_register_netdev(PPA_NETIF *dev); ++ ++/*! \brief unregister network device, in linux, it is unregister_netdev ++ \param[in] dev pointer to network device ++ \return ++ \note ++*/ ++ void ppa_unregister_netdev(PPA_NETIF *dev); ++ ++/*! \brief register char devide, in linux, it is register_chrdev ++ \param[in] major Character device major version ++ \param[in] name Character device name ++ \param[in] fops Character device operation pointer ++ \return ++ \note ++*/ ++ int32_t ppa_register_chrdev(int32_t major, const uint8_t *name, PPA_FILE_OPERATIONS *fops); ++ ++/*! \brief unregister char devide, in linux, it is unregister_chrdev ++ \param[in] major char device major version ++ \param[in] name char device name ++ \return ++ \note ++*/ ++ void ppa_unregister_chrdev(int32_t major, const uint8_t *name); ++ ++/*! \brief format a string to buffer, in linux, it is snprintf ++ \return ++ \note ++*/ ++ int ppa_snprintf(uint8_t* buf, size_t size, const uint8_t *fmt, ...); ++ ++/*! \brief format a string to buffer, in linux, it is sprintf ++ \return ++ \note ++*/ ++ int ppa_sprintf(uint8_t * buf, const uint8_t *fmt, ...); ++ ++/*! \brief get ioctl type, in linux, it is _IOC_TYPE ++ \return ++ \note ++*/ ++ uint32_t ppa_ioc_type(uint32_t); ++ ++/*! \brief get ioctl nr, in linux, it is _IOC_NR ++ \return ++ \note ++*/ ++ uint32_t ppa_ioc_nr(uint32_t); ++ ++/*! \brief get ioctl dir, in linux, it is _IOC_DIR ++ \return ++ \note ++*/ ++ uint32_t ppa_ioc_dir(uint32_t); ++ ++/*! \brief get ioctl read flag, in linux, it is _IOC_READ ++ \return ++ \note ++*/ ++ uint32_t ppa_ioc_read(void); ++ ++/*! \brief get ioctl write flag, in linux, it is _IOC_WRITE ++ \return ++ \note ++*/ ++ uint32_t ppa_ioc_write(void); ++ ++/*! \brief get ioctl size, in linux, it is _IOC_SIZE ++ \return ++ \note ++*/ ++ uint32_t ppa_ioc_size(uint32_t); ++ ++/*! \brief check ioctl access right, in linux, it is access_ok ++ \return ++ \note ++*/ ++ uint32_t ppa_ioc_access_ok(uint32_t type, uint32_t addr, uint32_t size); ++ ++/*! \brief get ioctl verify write flag, in linux it is VERIFY_WRITE ++ \return ++ \note ++*/ ++ uint32_t ppa_ioc_verify_write(void); ++ ++/*! \brief get ioctl verify read flag, in linux it is VERIFY_READ ++ \return ++ \note ++*/ ++ uint32_t ppa_ioc_verify_read(void); ++ ++/*! \brief print format string, in linux it is printk ++ \return ++ \note ++*/ ++ int32_t ppa_printk(const char *fmt, ...); ++ ++/*! \brief get egress qos mask ++ \param dev pointer to net device structure. ++ \param buf pointer to buffer. ++ \return ++ \note ++*/ ++ uint16_t ppa_vlan_dev_get_egress_qos_mask(PPA_NETIF *dev, PPA_BUF *buf); ++ ++#endif // __KERNEL__ ++/* @} */ ++ ++ ++#endif // __IFX_PPA_STACK_AL_H__20081103_1153__ +diff --git a/include/net/ipv6.h b/include/net/ipv6.h +index e4170a2..503c16f 100644 +--- a/include/net/ipv6.h ++++ b/include/net/ipv6.h +@@ -299,6 +299,11 @@ static inline int ipv6_addr_cmp(const struct in6_addr *a1, const struct in6_addr + return memcmp(a1, a2, sizeof(struct in6_addr)); + } + ++static inline void ipv6_addr_copy(struct in6_addr *a1, const struct in6_addr *a2) ++{ ++ memcpy(a1, a2, sizeof(struct in6_addr)); ++} ++ + static inline int + ipv6_masked_addr_cmp(const struct in6_addr *a1, const struct in6_addr *m, + const struct in6_addr *a2) +diff --git a/include/switch_api/AR9.h b/include/switch_api/AR9.h +new file mode 100644 +index 0000000..7cf8d3e +--- /dev/null ++++ b/include/switch_api/AR9.h +@@ -0,0 +1,4342 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ *****************************************************************************/ ++ ++#ifndef _AR9_H ++#define _AR9_H ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port Status Register' */ ++/* Bit: 'P1FCS' */ ++/* Description: 'Port 1 Flow Control Status' */ ++#define AR9_PS_REG_P1FCS_OFFSET 0x0000 ++#define AR9_PS_REG_P1FCS_SHIFT 12 ++#define AR9_PS_REG_P1FCS_SIZE 1 ++/* Bit: 'P1DS' */ ++/* Description: 'Port 1 Duplex Status' */ ++#define AR9_PS_REG_P1DS_OFFSET 0x0000 ++#define AR9_PS_REG_P1DS_SHIFT 11 ++#define AR9_PS_REG_P1DS_SIZE 1 ++/* Bit: 'P1SHS' */ ++/* Description: 'Port 1 Speed High Status' */ ++#define AR9_PS_REG_P1SHS_OFFSET 0x0000 ++#define AR9_PS_REG_P1SHS_SHIFT 10 ++#define AR9_PS_REG_P1SHS_SIZE 1 ++/* Bit: 'P1SS' */ ++/* Description: 'Port 1 Speed Status' */ ++#define AR9_PS_REG_P1SS_OFFSET 0x0000 ++#define AR9_PS_REG_P1SS_SHIFT 9 ++#define AR9_PS_REG_P1SS_SIZE 1 ++/* Bit: 'P1LS' */ ++/* Description: 'Port 1 Link Status' */ ++#define AR9_PS_REG_P1LS_OFFSET 0x0000 ++#define AR9_PS_REG_P1LS_SHIFT 8 ++#define AR9_PS_REG_P1LS_SIZE 1 ++/* Bit: 'P0FCS' */ ++/* Description: 'Port 0 Flow Control Status' */ ++#define AR9_PS_REG_P0FCS_OFFSET 0x0000 ++#define AR9_PS_REG_P0FCS_SHIFT 4 ++#define AR9_PS_REG_P0FCS_SIZE 1 ++/* Bit: 'P0DS' */ ++/* Description: 'Port 0 Duplex Status' */ ++#define AR9_PS_REG_P0DS_OFFSET 0x0000 ++#define AR9_PS_REG_P0DS_SHIFT 3 ++#define AR9_PS_REG_P0DS_SIZE 1 ++/* Bit: 'P0SHS' */ ++/* Description: 'Port 0 Speed High Status' */ ++#define AR9_PS_REG_P0SHS_OFFSET 0x0000 ++#define AR9_PS_REG_P0SHS_SHIFT 2 ++#define AR9_PS_REG_P0SHS_SIZE 1 ++/* Bit: 'P0SS' */ ++/* Description: 'Port 0 Speed Status' */ ++#define AR9_PS_REG_P0SS_OFFSET 0x0000 ++#define AR9_PS_REG_P0SS_SHIFT 1 ++#define AR9_PS_REG_P0SS_SIZE 1 ++/* Bit: 'P0LS' */ ++/* Description: 'Port 0 Link Status' */ ++#define AR9_PS_REG_P0LS_OFFSET 0x0000 ++#define AR9_PS_REG_P0LS_SHIFT 0 ++#define AR9_PS_REG_P0LS_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'P0 Control Register' */ ++/* Bit: 'SPS' */ ++/* Description: 'STP/RSTP port state' */ ++#define AR9_P0_CTL_REG_SPS_OFFSET 0x0004 ++#define AR9_P0_CTL_REG_SPS_SHIFT 30 ++#define AR9_P0_CTL_REG_SPS_SIZE 2 ++/* Bit: 'TCPE' */ ++/* Description: 'TCP/UDP PRIEN' */ ++#define AR9_P0_CTL_REG_TCPE_OFFSET 0x0004 ++#define AR9_P0_CTL_REG_TCPE_SHIFT 29 ++#define AR9_P0_CTL_REG_TCPE_SIZE 1 ++/* Bit: 'IPOVTU' */ ++/* Description: ' IP over TCP/UDP' */ ++#define AR9_P0_CTL_REG_IPOVTU_OFFSET 0x0004 ++#define AR9_P0_CTL_REG_IPOVTU_SHIFT 28 ++#define AR9_P0_CTL_REG_IPOVTU_SIZE 1 ++/* Bit: 'VPE' */ ++/* Description: 'VLAN Priority Enable' */ ++#define AR9_P0_CTL_REG_VPE_OFFSET 0x0004 ++#define AR9_P0_CTL_REG_VPE_SHIFT 27 ++#define AR9_P0_CTL_REG_VPE_SIZE 1 ++/* Bit: 'SPE' */ ++/* Description: 'Service Priority Enable' */ ++#define AR9_P0_CTL_REG_SPE_OFFSET 0x0004 ++#define AR9_P0_CTL_REG_SPE_SHIFT 26 ++#define AR9_P0_CTL_REG_SPE_SIZE 1 ++/* Bit: 'IPVLAN' */ ++/* Description: 'IP over VLAN PRI' */ ++#define AR9_P0_CTL_REG_IPVLAN_OFFSET 0x0004 ++#define AR9_P0_CTL_REG_IPVLAN_SHIFT 25 ++#define AR9_P0_CTL_REG_IPVLAN_SIZE 1 ++/* Bit: 'TPE' */ ++/* Description: 'Ether Type Priority Enable' */ ++#define AR9_P0_CTL_REG_TPE_OFFSET 0x0004 ++#define AR9_P0_CTL_REG_TPE_SHIFT 24 ++#define AR9_P0_CTL_REG_TPE_SIZE 1 ++/* Bit: 'DFWD' */ ++/* Description: 'Port Ingress Direct Forwarding' */ ++#define AR9_P0_CTL_REG_DFWD_OFFSET 0x0004 ++#define AR9_P0_CTL_REG_DFWD_SHIFT 19 ++#define AR9_P0_CTL_REG_DFWD_SIZE 1 ++/* Bit: 'FLP' */ ++/* Description: 'Force Link Up' */ ++#define AR9_P0_CTL_REG_FLP_OFFSET 0x0004 ++#define AR9_P0_CTL_REG_FLP_SHIFT 18 ++#define AR9_P0_CTL_REG_FLP_SIZE 1 ++/* Bit: 'FLD' */ ++/* Description: 'Force Link Down' */ ++#define AR9_P0_CTL_REG_FLD_OFFSET 0x0004 ++#define AR9_P0_CTL_REG_FLD_SHIFT 17 ++#define AR9_P0_CTL_REG_FLD_SIZE 1 ++/* Bit: 'RMWFQ' */ ++/* Description: 'Ratio Mode for WFQ' */ ++#define AR9_P0_CTL_REG_RMWFQ_OFFSET 0x0004 ++#define AR9_P0_CTL_REG_RMWFQ_SHIFT 16 ++#define AR9_P0_CTL_REG_RMWFQ_SIZE 1 ++/* Bit: 'AD' */ ++/* Description: 'Aging Disable' */ ++#define AR9_P0_CTL_REG_AD_OFFSET 0x0004 ++#define AR9_P0_CTL_REG_AD_SHIFT 15 ++#define AR9_P0_CTL_REG_AD_SIZE 1 ++/* Bit: 'LD' */ ++/* Description: 'Learning Disable' */ ++#define AR9_P0_CTL_REG_LD_OFFSET 0x0004 ++#define AR9_P0_CTL_REG_LD_SHIFT 14 ++#define AR9_P0_CTL_REG_LD_SIZE 1 ++/* Bit: 'REDIR' */ ++/* Description: 'Port Redirect Option' */ ++#define AR9_P0_CTL_REG_REDIR_OFFSET 0x0004 ++#define AR9_P0_CTL_REG_REDIR_SHIFT 13 ++#define AR9_P0_CTL_REG_REDIR_SIZE 1 ++/* Bit: 'MNA024' */ ++/* Description: 'Maximum Number of Addresses' */ ++#define AR9_P0_CTL_REG_MNA024_OFFSET 0x0004 ++#define AR9_P0_CTL_REG_MNA024_SHIFT 8 ++#define AR9_P0_CTL_REG_MNA024_SIZE 5 ++/* Bit: 'PPPOEP' */ ++/* Description: 'PPPOE Port Only' */ ++#define AR9_P0_CTL_REG_PPPOEP_OFFSET 0x0004 ++#define AR9_P0_CTL_REG_PPPOEP_SHIFT 7 ++#define AR9_P0_CTL_REG_PPPOEP_SIZE 1 ++/* Bit: 'PM' */ ++/* Description: 'PPPOE Manage' */ ++#define AR9_P0_CTL_REG_PM_OFFSET 0x0004 ++#define AR9_P0_CTL_REG_PM_SHIFT 6 ++#define AR9_P0_CTL_REG_PM_SIZE 1 ++/* Bit: 'IPMO' */ ++/* Description: 'Port Mirror Option' */ ++#define AR9_P0_CTL_REG_IPMO_OFFSET 0x0004 ++#define AR9_P0_CTL_REG_IPMO_SHIFT 4 ++#define AR9_P0_CTL_REG_IPMO_SIZE 2 ++/* Bit: 'PAS' */ ++/* Description: '802.1x Port Authorized state' */ ++#define AR9_P0_CTL_REG_PAS_OFFSET 0x0004 ++#define AR9_P0_CTL_REG_PAS_SHIFT 2 ++#define AR9_P0_CTL_REG_PAS_SIZE 2 ++/* Bit: 'DSV8021x' */ ++/* Description: 'Drop Scheme for violation 802.1x' */ ++#define AR9_P0_CTL_REG_DSV8021X_OFFSET 0x0004 ++#define AR9_P0_CTL_REG_DSV8021X_SHIFT 1 ++#define AR9_P0_CTL_REG_DSV8021X_SIZE 1 ++/* Bit: 'BYPASS' */ ++/* Description: 'ByPass Mode for Output' */ ++#define AR9_P0_CTL_REG_BYPASS_OFFSET 0x0004 ++#define AR9_P0_CTL_REG_BYPASS_SHIFT 0 ++#define AR9_P0_CTL_REG_BYPASS_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'P1 Control Register' */ ++/* Bit: 'SPS' */ ++/* Description: 'STP/RSTP port state' */ ++#define AR9_P1_CTL_REG_SPS_OFFSET 0x0008 ++#define AR9_P1_CTL_REG_SPS_SHIFT 30 ++#define AR9_P1_CTL_REG_SPS_SIZE 2 ++/* Bit: 'TCPE' */ ++/* Description: 'TCP/UDP PRIEN' */ ++#define AR9_P1_CTL_REG_TCPE_OFFSET 0x0008 ++#define AR9_P1_CTL_REG_TCPE_SHIFT 29 ++#define AR9_P1_CTL_REG_TCPE_SIZE 1 ++/* Bit: 'IPOVTU' */ ++/* Description: ' IP over TCP/UDP' */ ++#define AR9_P1_CTL_REG_IPOVTU_OFFSET 0x0008 ++#define AR9_P1_CTL_REG_IPOVTU_SHIFT 28 ++#define AR9_P1_CTL_REG_IPOVTU_SIZE 1 ++/* Bit: 'VPE' */ ++/* Description: 'VLAN Priority Enable' */ ++#define AR9_P1_CTL_REG_VPE_OFFSET 0x0008 ++#define AR9_P1_CTL_REG_VPE_SHIFT 27 ++#define AR9_P1_CTL_REG_VPE_SIZE 1 ++/* Bit: 'SPE' */ ++/* Description: 'Service Priority Enable' */ ++#define AR9_P1_CTL_REG_SPE_OFFSET 0x0008 ++#define AR9_P1_CTL_REG_SPE_SHIFT 26 ++#define AR9_P1_CTL_REG_SPE_SIZE 1 ++/* Bit: 'IPVLAN' */ ++/* Description: 'IP over VLAN PRI' */ ++#define AR9_P1_CTL_REG_IPVLAN_OFFSET 0x0008 ++#define AR9_P1_CTL_REG_IPVLAN_SHIFT 25 ++#define AR9_P1_CTL_REG_IPVLAN_SIZE 1 ++/* Bit: 'TPE' */ ++/* Description: 'Ether Type Priority Enable' */ ++#define AR9_P1_CTL_REG_TPE_OFFSET 0x0008 ++#define AR9_P1_CTL_REG_TPE_SHIFT 24 ++#define AR9_P1_CTL_REG_TPE_SIZE 1 ++/* Bit: 'DFWD' */ ++/* Description: 'Port Ingress Direct Forwarding' */ ++#define AR9_P1_CTL_REG_DFWD_OFFSET 0x0008 ++#define AR9_P1_CTL_REG_DFWD_SHIFT 19 ++#define AR9_P1_CTL_REG_DFWD_SIZE 1 ++/* Bit: 'FLP' */ ++/* Description: 'Force Link Up' */ ++#define AR9_P1_CTL_REG_FLP_OFFSET 0x0008 ++#define AR9_P1_CTL_REG_FLP_SHIFT 18 ++#define AR9_P1_CTL_REG_FLP_SIZE 1 ++/* Bit: 'FLD' */ ++/* Description: 'Force Link Down' */ ++#define AR9_P1_CTL_REG_FLD_OFFSET 0x0008 ++#define AR9_P1_CTL_REG_FLD_SHIFT 17 ++#define AR9_P1_CTL_REG_FLD_SIZE 1 ++/* Bit: 'RMWFQ' */ ++/* Description: 'Ratio Mode for WFQ' */ ++#define AR9_P1_CTL_REG_RMWFQ_OFFSET 0x0008 ++#define AR9_P1_CTL_REG_RMWFQ_SHIFT 16 ++#define AR9_P1_CTL_REG_RMWFQ_SIZE 1 ++/* Bit: 'AD' */ ++/* Description: 'Aging Disable' */ ++#define AR9_P1_CTL_REG_AD_OFFSET 0x0008 ++#define AR9_P1_CTL_REG_AD_SHIFT 15 ++#define AR9_P1_CTL_REG_AD_SIZE 1 ++/* Bit: 'LD' */ ++/* Description: 'Learning Disable' */ ++#define AR9_P1_CTL_REG_LD_OFFSET 0x0008 ++#define AR9_P1_CTL_REG_LD_SHIFT 14 ++#define AR9_P1_CTL_REG_LD_SIZE 1 ++/* Bit: 'REDIR' */ ++/* Description: 'Port Redirect Option' */ ++#define AR9_P1_CTL_REG_REDIR_OFFSET 0x0008 ++#define AR9_P1_CTL_REG_REDIR_SHIFT 13 ++#define AR9_P1_CTL_REG_REDIR_SIZE 1 ++/* Bit: 'MNA024' */ ++/* Description: 'Maximum Number of Addresses' */ ++#define AR9_P1_CTL_REG_MNA024_OFFSET 0x0008 ++#define AR9_P1_CTL_REG_MNA024_SHIFT 8 ++#define AR9_P1_CTL_REG_MNA024_SIZE 5 ++/* Bit: 'PPPOEP' */ ++/* Description: 'PPPOE Port Only' */ ++#define AR9_P1_CTL_REG_PPPOEP_OFFSET 0x0008 ++#define AR9_P1_CTL_REG_PPPOEP_SHIFT 7 ++#define AR9_P1_CTL_REG_PPPOEP_SIZE 1 ++/* Bit: 'PM' */ ++/* Description: 'PPPOE Manage' */ ++#define AR9_P1_CTL_REG_PM_OFFSET 0x0008 ++#define AR9_P1_CTL_REG_PM_SHIFT 6 ++#define AR9_P1_CTL_REG_PM_SIZE 1 ++/* Bit: 'IPMO' */ ++/* Description: 'Port Mirror Option' */ ++#define AR9_P1_CTL_REG_IPMO_OFFSET 0x0008 ++#define AR9_P1_CTL_REG_IPMO_SHIFT 4 ++#define AR9_P1_CTL_REG_IPMO_SIZE 2 ++/* Bit: 'PAS' */ ++/* Description: '802.1x Port Authorized state' */ ++#define AR9_P1_CTL_REG_PAS_OFFSET 0x0008 ++#define AR9_P1_CTL_REG_PAS_SHIFT 2 ++#define AR9_P1_CTL_REG_PAS_SIZE 2 ++/* Bit: 'DSV8021x' */ ++/* Description: 'Drop Scheme for violation 802.1x' */ ++#define AR9_P1_CTL_REG_DSV8021X_OFFSET 0x0008 ++#define AR9_P1_CTL_REG_DSV8021X_SHIFT 1 ++#define AR9_P1_CTL_REG_DSV8021X_SIZE 1 ++/* Bit: 'BYPASS' */ ++/* Description: 'ByPass Mode for Output' */ ++#define AR9_P1_CTL_REG_BYPASS_OFFSET 0x0008 ++#define AR9_P1_CTL_REG_BYPASS_SHIFT 0 ++#define AR9_P1_CTL_REG_BYPASS_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'P2 Control Register' */ ++/* Bit: 'SPS' */ ++/* Description: 'STP/RSTP port state' */ ++#define AR9_P2_CTL_REG_SPS_OFFSET 0x000C ++#define AR9_P2_CTL_REG_SPS_SHIFT 30 ++#define AR9_P2_CTL_REG_SPS_SIZE 2 ++/* Bit: 'TCPE' */ ++/* Description: 'TCP/UDP PRIEN' */ ++#define AR9_P2_CTL_REG_TCPE_OFFSET 0x000C ++#define AR9_P2_CTL_REG_TCPE_SHIFT 29 ++#define AR9_P2_CTL_REG_TCPE_SIZE 1 ++/* Bit: 'IPOVTU' */ ++/* Description: ' IP over TCP/UDP' */ ++#define AR9_P2_CTL_REG_IPOVTU_OFFSET 0x000C ++#define AR9_P2_CTL_REG_IPOVTU_SHIFT 28 ++#define AR9_P2_CTL_REG_IPOVTU_SIZE 1 ++/* Bit: 'VPE' */ ++/* Description: 'VLAN Priority Enable' */ ++#define AR9_P2_CTL_REG_VPE_OFFSET 0x000C ++#define AR9_P2_CTL_REG_VPE_SHIFT 27 ++#define AR9_P2_CTL_REG_VPE_SIZE 1 ++/* Bit: 'SPE' */ ++/* Description: 'Service Priority Enable' */ ++#define AR9_P2_CTL_REG_SPE_OFFSET 0x000C ++#define AR9_P2_CTL_REG_SPE_SHIFT 26 ++#define AR9_P2_CTL_REG_SPE_SIZE 1 ++/* Bit: 'IPVLAN' */ ++/* Description: 'IP over VLAN PRI' */ ++#define AR9_P2_CTL_REG_IPVLAN_OFFSET 0x000C ++#define AR9_P2_CTL_REG_IPVLAN_SHIFT 25 ++#define AR9_P2_CTL_REG_IPVLAN_SIZE 1 ++/* Bit: 'TPE' */ ++/* Description: 'Ether Type Priority Enable' */ ++#define AR9_P2_CTL_REG_TPE_OFFSET 0x000C ++#define AR9_P2_CTL_REG_TPE_SHIFT 24 ++#define AR9_P2_CTL_REG_TPE_SIZE 1 ++/* Bit: 'DFWD' */ ++/* Description: 'Port Ingress Direct Forwarding' */ ++#define AR9_P2_CTL_REG_DFWD_OFFSET 0x000C ++#define AR9_P2_CTL_REG_DFWD_SHIFT 19 ++#define AR9_P2_CTL_REG_DFWD_SIZE 1 ++/* Bit: 'FLP' */ ++/* Description: 'Force Link Up' */ ++#define AR9_P2_CTL_REG_FLP_OFFSET 0x000C ++#define AR9_P2_CTL_REG_FLP_SHIFT 18 ++#define AR9_P2_CTL_REG_FLP_SIZE 1 ++/* Bit: 'FLD' */ ++/* Description: 'Force Link Down' */ ++#define AR9_P2_CTL_REG_FLD_OFFSET 0x000C ++#define AR9_P2_CTL_REG_FLD_SHIFT 17 ++#define AR9_P2_CTL_REG_FLD_SIZE 1 ++/* Bit: 'RMWFQ' */ ++/* Description: 'Ratio Mode for WFQ' */ ++#define AR9_P2_CTL_REG_RMWFQ_OFFSET 0x000C ++#define AR9_P2_CTL_REG_RMWFQ_SHIFT 16 ++#define AR9_P2_CTL_REG_RMWFQ_SIZE 1 ++/* Bit: 'AD' */ ++/* Description: 'Aging Disable' */ ++#define AR9_P2_CTL_REG_AD_OFFSET 0x000C ++#define AR9_P2_CTL_REG_AD_SHIFT 15 ++#define AR9_P2_CTL_REG_AD_SIZE 1 ++/* Bit: 'LD' */ ++/* Description: 'Learning Disable' */ ++#define AR9_P2_CTL_REG_LD_OFFSET 0x000C ++#define AR9_P2_CTL_REG_LD_SHIFT 14 ++#define AR9_P2_CTL_REG_LD_SIZE 1 ++/* Bit: 'REDIR' */ ++/* Description: 'Port Redirect Option' */ ++#define AR9_P2_CTL_REG_REDIR_OFFSET 0x000C ++#define AR9_P2_CTL_REG_REDIR_SHIFT 13 ++#define AR9_P2_CTL_REG_REDIR_SIZE 1 ++/* Bit: 'MNA024' */ ++/* Description: 'Maximum Number of Addresses' */ ++#define AR9_P2_CTL_REG_MNA024_OFFSET 0x000C ++#define AR9_P2_CTL_REG_MNA024_SHIFT 8 ++#define AR9_P2_CTL_REG_MNA024_SIZE 5 ++/* Bit: 'PPPOEP' */ ++/* Description: 'PPPOE Port Only' */ ++#define AR9_P2_CTL_REG_PPPOEP_OFFSET 0x000C ++#define AR9_P2_CTL_REG_PPPOEP_SHIFT 7 ++#define AR9_P2_CTL_REG_PPPOEP_SIZE 1 ++/* Bit: 'PM' */ ++/* Description: 'PPPOE Manage' */ ++#define AR9_P2_CTL_REG_PM_OFFSET 0x000C ++#define AR9_P2_CTL_REG_PM_SHIFT 6 ++#define AR9_P2_CTL_REG_PM_SIZE 1 ++/* Bit: 'IPMO' */ ++/* Description: 'Port Mirror Option' */ ++#define AR9_P2_CTL_REG_IPMO_OFFSET 0x000C ++#define AR9_P2_CTL_REG_IPMO_SHIFT 4 ++#define AR9_P2_CTL_REG_IPMO_SIZE 2 ++/* Bit: 'PAS' */ ++/* Description: '802.1x Port Authorized state' */ ++#define AR9_P2_CTL_REG_PAS_OFFSET 0x000C ++#define AR9_P2_CTL_REG_PAS_SHIFT 2 ++#define AR9_P2_CTL_REG_PAS_SIZE 2 ++/* Bit: 'DSV8021x' */ ++/* Description: 'Drop Scheme for violation 802.1x' */ ++#define AR9_P2_CTL_REG_DSV8021X_OFFSET 0x000C ++#define AR9_P2_CTL_REG_DSV8021X_SHIFT 1 ++#define AR9_P2_CTL_REG_DSV8021X_SIZE 1 ++/* Bit: 'BYPASS' */ ++/* Description: 'ByPass Mode for Output' */ ++#define AR9_P2_CTL_REG_BYPASS_OFFSET 0x000C ++#define AR9_P2_CTL_REG_BYPASS_SHIFT 0 ++#define AR9_P2_CTL_REG_BYPASS_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 0 VLAN Control Register' */ ++/* Bit: 'DFID' */ ++/* Description: 'Default FID' */ ++#define AR9_P0_VLAN_REG_DFID_OFFSET 0x0010 ++#define AR9_P0_VLAN_REG_DFID_SHIFT 30 ++#define AR9_P0_VLAN_REG_DFID_SIZE 2 ++/* Bit: 'TBVE' */ ++/* Description: 'Tagged Base VLAN Enable' */ ++#define AR9_P0_VLAN_REG_TBVE_OFFSET 0x0010 ++#define AR9_P0_VLAN_REG_TBVE_SHIFT 29 ++#define AR9_P0_VLAN_REG_TBVE_SIZE 1 ++/* Bit: 'IFNTE' */ ++/* Description: 'Input Force No TAG Enable' */ ++#define AR9_P0_VLAN_REG_IFNTE_OFFSET 0x0010 ++#define AR9_P0_VLAN_REG_IFNTE_SHIFT 28 ++#define AR9_P0_VLAN_REG_IFNTE_SIZE 1 ++/* Bit: 'VC' */ ++/* Description: 'VID Check with the VID table' */ ++#define AR9_P0_VLAN_REG_VC_OFFSET 0x0010 ++#define AR9_P0_VLAN_REG_VC_SHIFT 27 ++#define AR9_P0_VLAN_REG_VC_SIZE 1 ++/* Bit: 'VSD' */ ++/* Description: 'VLAN Security Disable' */ ++#define AR9_P0_VLAN_REG_VSD_OFFSET 0x0010 ++#define AR9_P0_VLAN_REG_VSD_SHIFT 26 ++#define AR9_P0_VLAN_REG_VSD_SIZE 1 ++/* Bit: 'AOVTP' */ ++/* Description: 'Admit Only VLAN_Tagged Packet' */ ++#define AR9_P0_VLAN_REG_AOVTP_OFFSET 0x0010 ++#define AR9_P0_VLAN_REG_AOVTP_SHIFT 25 ++#define AR9_P0_VLAN_REG_AOVTP_SIZE 1 ++/* Bit: 'VMCE' */ ++/* Description: 'VLAN Member Check Enable' */ ++#define AR9_P0_VLAN_REG_VMCE_OFFSET 0x0010 ++#define AR9_P0_VLAN_REG_VMCE_SHIFT 24 ++#define AR9_P0_VLAN_REG_VMCE_SIZE 1 ++/* Bit: 'DVPM' */ ++/* Description: 'Default VLAN Port Map' */ ++#define AR9_P0_VLAN_REG_DVPM_OFFSET 0x0010 ++#define AR9_P0_VLAN_REG_DVPM_SHIFT 16 ++#define AR9_P0_VLAN_REG_DVPM_SIZE 8 ++/* Bit: 'PP' */ ++/* Description: 'Port Priority' */ ++#define AR9_P0_VLAN_REG_PP_OFFSET 0x0010 ++#define AR9_P0_VLAN_REG_PP_SHIFT 14 ++#define AR9_P0_VLAN_REG_PP_SIZE 2 ++/* Bit: 'PPE' */ ++/* Description: 'Port Priority Enable' */ ++#define AR9_P0_VLAN_REG_PPE_OFFSET 0x0010 ++#define AR9_P0_VLAN_REG_PPE_SHIFT 13 ++#define AR9_P0_VLAN_REG_PPE_SIZE 1 ++/* Bit: 'PVTAGMP' */ ++/* Description: 'Port base VLAN tag member for Port 0' */ ++#define AR9_P0_VLAN_REG_PVTAGMP_OFFSET 0x0010 ++#define AR9_P0_VLAN_REG_PVTAGMP_SHIFT 12 ++#define AR9_P0_VLAN_REG_PVTAGMP_SIZE 1 ++/* Bit: 'PVID' */ ++/* Description: 'PVID' */ ++#define AR9_P0_VLAN_REG_PVID_OFFSET 0x0010 ++#define AR9_P0_VLAN_REG_PVID_SHIFT 0 ++#define AR9_P0_VLAN_REG_PVID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 1 VLAN Control Register' */ ++/* Bit: 'DFID' */ ++/* Description: 'Default FID' */ ++#define AR9_P1_VLAN_REG_DFID_OFFSET 0x0014 ++#define AR9_P1_VLAN_REG_DFID_SHIFT 30 ++#define AR9_P1_VLAN_REG_DFID_SIZE 2 ++/* Bit: 'TBVE' */ ++/* Description: 'Tagged Base VLAN Enable' */ ++#define AR9_P1_VLAN_REG_TBVE_OFFSET 0x0014 ++#define AR9_P1_VLAN_REG_TBVE_SHIFT 29 ++#define AR9_P1_VLAN_REG_TBVE_SIZE 1 ++/* Bit: 'IFNTE' */ ++/* Description: 'Input Force No TAG Enable' */ ++#define AR9_P1_VLAN_REG_IFNTE_OFFSET 0x0014 ++#define AR9_P1_VLAN_REG_IFNTE_SHIFT 28 ++#define AR9_P1_VLAN_REG_IFNTE_SIZE 1 ++/* Bit: 'VC' */ ++/* Description: 'VID Check with the VID table' */ ++#define AR9_P1_VLAN_REG_VC_OFFSET 0x0014 ++#define AR9_P1_VLAN_REG_VC_SHIFT 27 ++#define AR9_P1_VLAN_REG_VC_SIZE 1 ++/* Bit: 'VSD' */ ++/* Description: 'VLAN Security Disable' */ ++#define AR9_P1_VLAN_REG_VSD_OFFSET 0x0014 ++#define AR9_P1_VLAN_REG_VSD_SHIFT 26 ++#define AR9_P1_VLAN_REG_VSD_SIZE 1 ++/* Bit: 'AOVTP' */ ++/* Description: 'Admit Only VLAN_Tagged Packet' */ ++#define AR9_P1_VLAN_REG_AOVTP_OFFSET 0x0014 ++#define AR9_P1_VLAN_REG_AOVTP_SHIFT 25 ++#define AR9_P1_VLAN_REG_AOVTP_SIZE 1 ++/* Bit: 'VMCE' */ ++/* Description: 'VLAN Member Check Enable' */ ++#define AR9_P1_VLAN_REG_VMCE_OFFSET 0x0014 ++#define AR9_P1_VLAN_REG_VMCE_SHIFT 24 ++#define AR9_P1_VLAN_REG_VMCE_SIZE 1 ++/* Bit: 'DVPM' */ ++/* Description: 'Default VLAN Port Map' */ ++#define AR9_P1_VLAN_REG_DVPM_OFFSET 0x0014 ++#define AR9_P1_VLAN_REG_DVPM_SHIFT 16 ++#define AR9_P1_VLAN_REG_DVPM_SIZE 8 ++/* Bit: 'PP' */ ++/* Description: 'Port Priority' */ ++#define AR9_P1_VLAN_REG_PP_OFFSET 0x0014 ++#define AR9_P1_VLAN_REG_PP_SHIFT 14 ++#define AR9_P1_VLAN_REG_PP_SIZE 2 ++/* Bit: 'PPE' */ ++/* Description: 'Port Priority Enable' */ ++#define AR9_P1_VLAN_REG_PPE_OFFSET 0x0014 ++#define AR9_P1_VLAN_REG_PPE_SHIFT 13 ++#define AR9_P1_VLAN_REG_PPE_SIZE 1 ++/* Bit: 'PVTAGMP' */ ++/* Description: 'Port base VLAN tag member for Port 0' */ ++#define AR9_P1_VLAN_REG_PVTAGMP_OFFSET 0x0014 ++#define AR9_P1_VLAN_REG_PVTAGMP_SHIFT 12 ++#define AR9_P1_VLAN_REG_PVTAGMP_SIZE 1 ++/* Bit: 'PVID' */ ++/* Description: 'PVID' */ ++#define AR9_P1_VLAN_REG_PVID_OFFSET 0x0014 ++#define AR9_P1_VLAN_REG_PVID_SHIFT 0 ++#define AR9_P1_VLAN_REG_PVID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 2 VLAN Control Register' */ ++/* Bit: 'DFID' */ ++/* Description: 'Default FID' */ ++#define AR9_P2_VLAN_REG_DFID_OFFSET 0x0018 ++#define AR9_P2_VLAN_REG_DFID_SHIFT 30 ++#define AR9_P2_VLAN_REG_DFID_SIZE 2 ++/* Bit: 'TBVE' */ ++/* Description: 'Tagged Base VLAN Enable' */ ++#define AR9_P2_VLAN_REG_TBVE_OFFSET 0x0018 ++#define AR9_P2_VLAN_REG_TBVE_SHIFT 29 ++#define AR9_P2_VLAN_REG_TBVE_SIZE 1 ++/* Bit: 'IFNTE' */ ++/* Description: 'Input Force No TAG Enable' */ ++#define AR9_P2_VLAN_REG_IFNTE_OFFSET 0x0018 ++#define AR9_P2_VLAN_REG_IFNTE_SHIFT 28 ++#define AR9_P2_VLAN_REG_IFNTE_SIZE 1 ++/* Bit: 'VC' */ ++/* Description: 'VID Check with the VID table' */ ++#define AR9_P2_VLAN_REG_VC_OFFSET 0x0018 ++#define AR9_P2_VLAN_REG_VC_SHIFT 27 ++#define AR9_P2_VLAN_REG_VC_SIZE 1 ++/* Bit: 'VSD' */ ++/* Description: 'VLAN Security Disable' */ ++#define AR9_P2_VLAN_REG_VSD_OFFSET 0x0018 ++#define AR9_P2_VLAN_REG_VSD_SHIFT 26 ++#define AR9_P2_VLAN_REG_VSD_SIZE 1 ++/* Bit: 'AOVTP' */ ++/* Description: 'Admit Only VLAN_Tagged Packet' */ ++#define AR9_P2_VLAN_REG_AOVTP_OFFSET 0x0018 ++#define AR9_P2_VLAN_REG_AOVTP_SHIFT 25 ++#define AR9_P2_VLAN_REG_AOVTP_SIZE 1 ++/* Bit: 'VMCE' */ ++/* Description: 'VLAN Member Check Enable' */ ++#define AR9_P2_VLAN_REG_VMCE_OFFSET 0x0018 ++#define AR9_P2_VLAN_REG_VMCE_SHIFT 24 ++#define AR9_P2_VLAN_REG_VMCE_SIZE 1 ++/* Bit: 'DVPM' */ ++/* Description: 'Default VLAN Port Map' */ ++#define AR9_P2_VLAN_REG_DVPM_OFFSET 0x0018 ++#define AR9_P2_VLAN_REG_DVPM_SHIFT 16 ++#define AR9_P2_VLAN_REG_DVPM_SIZE 8 ++/* Bit: 'PP' */ ++/* Description: 'Port Priority' */ ++#define AR9_P2_VLAN_REG_PP_OFFSET 0x0018 ++#define AR9_P2_VLAN_REG_PP_SHIFT 14 ++#define AR9_P2_VLAN_REG_PP_SIZE 2 ++/* Bit: 'PPE' */ ++/* Description: 'Port Priority Enable' */ ++#define AR9_P2_VLAN_REG_PPE_OFFSET 0x0018 ++#define AR9_P2_VLAN_REG_PPE_SHIFT 13 ++#define AR9_P2_VLAN_REG_PPE_SIZE 1 ++/* Bit: 'PVTAGMP' */ ++/* Description: 'Port base VLAN tag member for Port 0' */ ++#define AR9_P2_VLAN_REG_PVTAGMP_OFFSET 0x0018 ++#define AR9_P2_VLAN_REG_PVTAGMP_SHIFT 12 ++#define AR9_P2_VLAN_REG_PVTAGMP_SIZE 1 ++/* Bit: 'PVID' */ ++/* Description: 'PVID' */ ++#define AR9_P2_VLAN_REG_PVID_OFFSET 0x0018 ++#define AR9_P2_VLAN_REG_PVID_SHIFT 0 ++#define AR9_P2_VLAN_REG_PVID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 0 Ingress Control Register' */ ++/* Bit: 'P0ITT' */ ++/* Description: 'Port 0 Ingress/Egress Timer Tick T selection' */ ++#define AR9_P0_INCTL_REG_P0ITT_OFFSET 0x0020 ++#define AR9_P0_INCTL_REG_P0ITT_SHIFT 11 ++#define AR9_P0_INCTL_REG_P0ITT_SIZE 2 ++/* Bit: 'P0ITR' */ ++/* Description: 'Port 0 Ingress Token R' */ ++#define AR9_P0_INCTL_REG_P0ITR_OFFSET 0x0020 ++#define AR9_P0_INCTL_REG_P0ITR_SHIFT 0 ++#define AR9_P0_INCTL_REG_P0ITR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 1 Ingress Control Register' */ ++/* Bit: 'P1ITT' */ ++/* Description: 'Port 1 Ingress/Egress Timer Tick T selection' */ ++#define AR9_P1_INCTL_REG_P1ITT_OFFSET 0x0024 ++#define AR9_P1_INCTL_REG_P1ITT_SHIFT 11 ++#define AR9_P1_INCTL_REG_P1ITT_SIZE 2 ++/* Bit: 'P1ITR' */ ++/* Description: 'Port 1 Ingress Token R' */ ++#define AR9_P1_INCTL_REG_P1ITR_OFFSET 0x0024 ++#define AR9_P1_INCTL_REG_P1ITR_SHIFT 0 ++#define AR9_P1_INCTL_REG_P1ITR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 2 Ingress Control Register' */ ++/* Bit: 'P2ITT' */ ++/* Description: 'Port 2 Ingress/Egress Timer Tick T selection' */ ++#define AR9_P2_INCTL_REG_P2ITT_OFFSET 0x0028 ++#define AR9_P2_INCTL_REG_P2ITT_SHIFT 11 ++#define AR9_P2_INCTL_REG_P2ITT_SIZE 2 ++/* Bit: 'P2ITR' */ ++/* Description: 'Port 2 Ingress Token R' */ ++#define AR9_P2_INCTL_REG_P2ITR_OFFSET 0x0028 ++#define AR9_P2_INCTL_REG_P2ITR_SHIFT 0 ++#define AR9_P2_INCTL_REG_P2ITR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 0 Egress Control for Strict Q32 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define AR9_P0_ECS_Q32_REG_P0SPQ3TR_OFFSET 0x0030 ++#define AR9_P0_ECS_Q32_REG_P0SPQ3TR_SHIFT 16 ++#define AR9_P0_ECS_Q32_REG_P0SPQ3TR_SIZE 11 ++/* Bit: 'P0SPQ2TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q2' */ ++#define AR9_P0_ECS_Q32_REG_P0SPQ2TR_OFFSET 0x0030 ++#define AR9_P0_ECS_Q32_REG_P0SPQ2TR_SHIFT 0 ++#define AR9_P0_ECS_Q32_REG_P0SPQ2TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 1 Egress Control for Strict Q32 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define AR9_P1_ECS_Q32_REG_P0SPQ3TR_OFFSET 0x0040 ++#define AR9_P1_ECS_Q32_REG_P0SPQ3TR_SHIFT 16 ++#define AR9_P1_ECS_Q32_REG_P0SPQ3TR_SIZE 11 ++/* Bit: 'P0SPQ2TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q2' */ ++#define AR9_P1_ECS_Q32_REG_P0SPQ2TR_OFFSET 0x0040 ++#define AR9_P1_ECS_Q32_REG_P0SPQ2TR_SHIFT 0 ++#define AR9_P1_ECS_Q32_REG_P0SPQ2TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 2 Egress Control for Strict Q32 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define AR9_P2_ECS_Q32_REG_P0SPQ3TR_OFFSET 0x0050 ++#define AR9_P2_ECS_Q32_REG_P0SPQ3TR_SHIFT 16 ++#define AR9_P2_ECS_Q32_REG_P0SPQ3TR_SIZE 11 ++/* Bit: 'P0SPQ2TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q2' */ ++#define AR9_P2_ECS_Q32_REG_P0SPQ2TR_OFFSET 0x0050 ++#define AR9_P2_ECS_Q32_REG_P0SPQ2TR_SHIFT 0 ++#define AR9_P2_ECS_Q32_REG_P0SPQ2TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 0 Egress Control for Strict Q10 Register' */ ++/* Bit: 'P0SPQ1TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q1' */ ++#define AR9_P0_ECS_Q10_REG_P0SPQ1TR_OFFSET 0x0034 ++#define AR9_P0_ECS_Q10_REG_P0SPQ1TR_SHIFT 16 ++#define AR9_P0_ECS_Q10_REG_P0SPQ1TR_SIZE 11 ++/* Bit: 'P0SPQ0TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q0' */ ++#define AR9_P0_ECS_Q10_REG_P0SPQ0TR_OFFSET 0x0034 ++#define AR9_P0_ECS_Q10_REG_P0SPQ0TR_SHIFT 0 ++#define AR9_P0_ECS_Q10_REG_P0SPQ0TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 1 Egress Control for Strict Q10 Register' */ ++/* Bit: 'P0SPQ1TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q1' */ ++#define AR9_P1_ECS_Q10_REG_P0SPQ1TR_OFFSET 0x0044 ++#define AR9_P1_ECS_Q10_REG_P0SPQ1TR_SHIFT 16 ++#define AR9_P1_ECS_Q10_REG_P0SPQ1TR_SIZE 11 ++/* Bit: 'P0SPQ0TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q0' */ ++#define AR9_P1_ECS_Q10_REG_P0SPQ0TR_OFFSET 0x0044 ++#define AR9_P1_ECS_Q10_REG_P0SPQ0TR_SHIFT 0 ++#define AR9_P1_ECS_Q10_REG_P0SPQ0TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 2 Egress Control for Strict Q10 Register' */ ++/* Bit: 'P0SPQ1TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q1' */ ++#define AR9_P2_ECS_Q10_REG_P0SPQ1TR_OFFSET 0x0054 ++#define AR9_P2_ECS_Q10_REG_P0SPQ1TR_SHIFT 16 ++#define AR9_P2_ECS_Q10_REG_P0SPQ1TR_SIZE 11 ++/* Bit: 'P0SPQ0TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q0' */ ++#define AR9_P2_ECS_Q10_REG_P0SPQ0TR_OFFSET 0x0054 ++#define AR9_P2_ECS_Q10_REG_P0SPQ0TR_SHIFT 0 ++#define AR9_P2_ECS_Q10_REG_P0SPQ0TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 0 Egress Control for WFQ Q32 Register' */ ++/* Bit: 'P0WQ3TR' */ ++/* Description: 'Port 0 Egress Token R for WFQ Q3' */ ++#define AR9_P0_ECW_Q32_REG_P0WQ3TR_OFFSET 0x0038 ++#define AR9_P0_ECW_Q32_REG_P0WQ3TR_SHIFT 16 ++#define AR9_P0_ECW_Q32_REG_P0WQ3TR_SIZE 11 ++/* Bit: 'P0WQ2TR' */ ++/* Description: 'Port 0 Egress Token R for WFQ Q2' */ ++#define AR9_P0_ECW_Q32_REG_P0WQ2TR_OFFSET 0x0038 ++#define AR9_P0_ECW_Q32_REG_P0WQ2TR_SHIFT 0 ++#define AR9_P0_ECW_Q32_REG_P0WQ2TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 1 Egress Control for WFQ Q32 Register' */ ++/* Bit: 'P1WQ3TR' */ ++/* Description: 'Port 1 Egress Token R for WFQ Q3' */ ++#define AR9_P1_ECW_Q32_REG_P1WQ3TR_OFFSET 0x0048 ++#define AR9_P1_ECW_Q32_REG_P1WQ3TR_SHIFT 16 ++#define AR9_P1_ECW_Q32_REG_P1WQ3TR_SIZE 11 ++/* Bit: 'P1WQ2TR' */ ++/* Description: 'Port 1 Egress Token R for WFQ Q2' */ ++#define AR9_P1_ECW_Q32_REG_P1WQ2TR_OFFSET 0x0048 ++#define AR9_P1_ECW_Q32_REG_P1WQ2TR_SHIFT 0 ++#define AR9_P1_ECW_Q32_REG_P1WQ2TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 2 Egress Control for WFQ Q32 Register' */ ++/* Bit: 'P2WQ3TR' */ ++/* Description: 'Port 2 Egress Token R for WFQ Q3' */ ++#define AR9_P2_ECW_Q32_REG_P2WQ3TR_OFFSET 0x0058 ++#define AR9_P2_ECW_Q32_REG_P2WQ3TR_SHIFT 16 ++#define AR9_P2_ECW_Q32_REG_P2WQ3TR_SIZE 11 ++/* Bit: 'P2WQ2TR' */ ++/* Description: 'Port 2 Egress Token R for WFQ Q2' */ ++#define AR9_P2_ECW_Q32_REG_P2WQ2TR_OFFSET 0x0058 ++#define AR9_P2_ECW_Q32_REG_P2WQ2TR_SHIFT 0 ++#define AR9_P2_ECW_Q32_REG_P2WQ2TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 0 Egress Control for WFQ Q10 Register' */ ++/* Bit: 'P0WQ1TR' */ ++/* Description: 'Port 0 Egress Token R for WFQ Q1' */ ++#define AR9_P0_ECW_Q10_REG_P0WQ1TR_OFFSET 0x003C ++#define AR9_P0_ECW_Q10_REG_P0WQ1TR_SHIFT 16 ++#define AR9_P0_ECW_Q10_REG_P0WQ1TR_SIZE 11 ++/* Bit: 'P0WQ0TR' */ ++/* Description: 'Port 0 Egress Token R for WFQ Q0' */ ++#define AR9_P0_ECW_Q10_REG_P0WQ0TR_OFFSET 0x003C ++#define AR9_P0_ECW_Q10_REG_P0WQ0TR_SHIFT 0 ++#define AR9_P0_ECW_Q10_REG_P0WQ0TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 1 Egress Control for WFQ Q10 Register' */ ++/* Bit: 'P1WQ1TR' */ ++/* Description: 'Port 1 Egress Token R for WFQ Q1' */ ++#define AR9_P1_ECW_Q10_REG_P1WQ1TR_OFFSET 0x004C ++#define AR9_P1_ECW_Q10_REG_P1WQ1TR_SHIFT 16 ++#define AR9_P1_ECW_Q10_REG_P1WQ1TR_SIZE 11 ++/* Bit: 'P1WQ0TR' */ ++/* Description: 'Port 1 Egress Token R for WFQ Q0' */ ++#define AR9_P1_ECW_Q10_REG_P1WQ0TR_OFFSET 0x004C ++#define AR9_P1_ECW_Q10_REG_P1WQ0TR_SHIFT 0 ++#define AR9_P1_ECW_Q10_REG_P1WQ0TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 2 Egress Control for WFQ Q10 Register' */ ++/* Bit: 'P2WQ1TR' */ ++/* Description: 'Port 2 Egress Token R for WFQ Q1' */ ++#define AR9_P2_ECW_Q10_REG_P2WQ1TR_OFFSET 0x005C ++#define AR9_P2_ECW_Q10_REG_P2WQ1TR_SHIFT 16 ++#define AR9_P2_ECW_Q10_REG_P2WQ1TR_SIZE 11 ++/* Bit: 'P2WQ0TR' */ ++/* Description: 'Port 2 Egress Token R for WFQ Q0' */ ++#define AR9_P2_ECW_Q10_REG_P2WQ0TR_OFFSET 0x005C ++#define AR9_P2_ECW_Q10_REG_P2WQ0TR_SHIFT 0 ++#define AR9_P2_ECW_Q10_REG_P2WQ0TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Interrupt Enable Register' */ ++/* Bit: 'DBFIE' */ ++/* Description: 'Data Buffer is Full Interrupt Enable' */ ++#define AR9_INT_ENA_REG_DBFIE_OFFSET 0x0060 ++#define AR9_INT_ENA_REG_DBFIE_SHIFT 7 ++#define AR9_INT_ENA_REG_DBFIE_SIZE 1 ++/* Bit: 'DBNFIE' */ ++/* Description: 'Data Buffer is nearly Full Interrupt Enable' */ ++#define AR9_INT_ENA_REG_DBNFIE_OFFSET 0x0060 ++#define AR9_INT_ENA_REG_DBNFIE_SHIFT 6 ++#define AR9_INT_ENA_REG_DBNFIE_SIZE 1 ++/* Bit: 'LTFIE' */ ++/* Description: 'Learning Table Full Interrupt Enable' */ ++#define AR9_INT_ENA_REG_LTFIE_OFFSET 0x0060 ++#define AR9_INT_ENA_REG_LTFIE_SHIFT 5 ++#define AR9_INT_ENA_REG_LTFIE_SIZE 1 ++/* Bit: 'LTADIE' */ ++/* Description: 'Leaning Table Access Done Interrupt Enable' */ ++#define AR9_INT_ENA_REG_LTADIE_OFFSET 0x0060 ++#define AR9_INT_ENA_REG_LTADIE_SHIFT 4 ++#define AR9_INT_ENA_REG_LTADIE_SIZE 1 ++/* Bit: 'PSVIE' */ ++/* Description: 'Port Security Violation Interrupt Enable' */ ++#define AR9_INT_ENA_REG_PSVIE_OFFSET 0x0060 ++#define AR9_INT_ENA_REG_PSVIE_SHIFT 1 ++#define AR9_INT_ENA_REG_PSVIE_SIZE 3 ++/* Bit: 'PSCIE' */ ++/* Description: 'Port Status Change Interrupt Enable' */ ++#define AR9_INT_ENA_REG_PSCIE_OFFSET 0x0060 ++#define AR9_INT_ENA_REG_PSCIE_SHIFT 0 ++#define AR9_INT_ENA_REG_PSCIE_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Interrupt Status Register' */ ++/* Bit: 'DBF' */ ++/* Description: 'Data Buffer is Full' */ ++#define AR9_INT_ST_REG_DBF_OFFSET 0x0064 ++#define AR9_INT_ST_REG_DBF_SHIFT 7 ++#define AR9_INT_ST_REG_DBF_SIZE 1 ++/* Bit: 'DBNF' */ ++/* Description: 'Data Buffer is nearly Full' */ ++#define AR9_INT_ST_REG_DBNF_OFFSET 0x0064 ++#define AR9_INT_ST_REG_DBNF_SHIFT 6 ++#define AR9_INT_ST_REG_DBNF_SIZE 1 ++/* Bit: 'LTF' */ ++/* Description: 'Learning Table Full' */ ++#define AR9_INT_ST_REG_LTF_OFFSET 0x0064 ++#define AR9_INT_ST_REG_LTF_SHIFT 5 ++#define AR9_INT_ST_REG_LTF_SIZE 1 ++/* Bit: 'LTAD' */ ++/* Description: 'Leaning Table Access Done' */ ++#define AR9_INT_ST_REG_LTAD_OFFSET 0x0064 ++#define AR9_INT_ST_REG_LTAD_SHIFT 4 ++#define AR9_INT_ST_REG_LTAD_SIZE 1 ++/* Bit: 'PSV' */ ++/* Description: 'Port Security Violation' */ ++#define AR9_INT_ST_REG_PSV_OFFSET 0x0064 ++#define AR9_INT_ST_REG_PSV_SHIFT 1 ++#define AR9_INT_ST_REG_PSV_SIZE 3 ++/* Bit: 'PSC' */ ++/* Description: 'Port Status Change' */ ++#define AR9_INT_ST_REG_PSC_OFFSET 0x0064 ++#define AR9_INT_ST_REG_PSC_SHIFT 0 ++#define AR9_INT_ST_REG_PSC_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Switch Global Control Register 0' */ ++/* Bit: 'SE' */ ++/* Description: 'Switch Enable' */ ++#define AR9_SW_GCTL0_REG_SE_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_SE_SHIFT 31 ++#define AR9_SW_GCTL0_REG_SE_SIZE 1 ++/* Bit: 'ICRCCD' */ ++/* Description: 'CRC Check Disable' */ ++#define AR9_SW_GCTL0_REG_ICRCCD_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_ICRCCD_SHIFT 30 ++#define AR9_SW_GCTL0_REG_ICRCCD_SIZE 1 ++/* Bit: 'LPE' */ ++/* Description: 'Virtual Ports Over CPU Physical Port Enable' */ ++#define AR9_SW_GCTL0_REG_LPE_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_LPE_SHIFT 29 ++#define AR9_SW_GCTL0_REG_LPE_SIZE 1 ++/* Bit: 'RVID0' */ ++/* Description: 'Replace VID0' */ ++#define AR9_SW_GCTL0_REG_RVID0_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_RVID0_SHIFT 28 ++#define AR9_SW_GCTL0_REG_RVID0_SIZE 1 ++/* Bit: 'RVID1' */ ++/* Description: 'Replace VID1' */ ++#define AR9_SW_GCTL0_REG_RVID1_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_RVID1_SHIFT 27 ++#define AR9_SW_GCTL0_REG_RVID1_SIZE 1 ++/* Bit: 'RVIDFFF' */ ++/* Description: 'Replace VIDFFF' */ ++#define AR9_SW_GCTL0_REG_RVIDFFF_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_RVIDFFF_SHIFT 26 ++#define AR9_SW_GCTL0_REG_RVIDFFF_SIZE 1 ++/* Bit: 'PCR' */ ++/* Description: 'Priority Change Rule' */ ++#define AR9_SW_GCTL0_REG_PCR_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_PCR_SHIFT 25 ++#define AR9_SW_GCTL0_REG_PCR_SIZE 1 ++/* Bit: 'PCE' */ ++/* Description: 'Priority Change Enable' */ ++#define AR9_SW_GCTL0_REG_PCE_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_PCE_SHIFT 24 ++#define AR9_SW_GCTL0_REG_PCE_SIZE 1 ++/* Bit: 'TSIPGE' */ ++/* Description: 'Transmit Short IPG Enable' */ ++#define AR9_SW_GCTL0_REG_TSIPGE_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_TSIPGE_SHIFT 23 ++#define AR9_SW_GCTL0_REG_TSIPGE_SIZE 1 ++/* Bit: 'PHYBA' */ ++/* Description: 'PHY Base Address' */ ++#define AR9_SW_GCTL0_REG_PHYBA_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_PHYBA_SHIFT 22 ++#define AR9_SW_GCTL0_REG_PHYBA_SIZE 1 ++/* Bit: 'DPWECH' */ ++/* Description: 'Drop Packet When Excessive Collision Happen' */ ++#define AR9_SW_GCTL0_REG_DPWECH_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_DPWECH_SHIFT 21 ++#define AR9_SW_GCTL0_REG_DPWECH_SIZE 1 ++/* Bit: 'ATS' */ ++/* Description: 'Aging Timer Select' */ ++#define AR9_SW_GCTL0_REG_ATS_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_ATS_SHIFT 18 ++#define AR9_SW_GCTL0_REG_ATS_SIZE 3 ++/* Bit: 'MCA' */ ++/* Description: 'Mirror CRC Also' */ ++#define AR9_SW_GCTL0_REG_MCA_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_MCA_SHIFT 17 ++#define AR9_SW_GCTL0_REG_MCA_SIZE 1 ++/* Bit: 'MRA' */ ++/* Description: 'Mirror RXER Also' */ ++#define AR9_SW_GCTL0_REG_MRA_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_MRA_SHIFT 16 ++#define AR9_SW_GCTL0_REG_MRA_SIZE 1 ++/* Bit: 'MPA' */ ++/* Description: 'Mirror PAUSE Also' */ ++#define AR9_SW_GCTL0_REG_MPA_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_MPA_SHIFT 15 ++#define AR9_SW_GCTL0_REG_MPA_SIZE 1 ++/* Bit: 'MLA' */ ++/* Description: 'Mirror Long Also' */ ++#define AR9_SW_GCTL0_REG_MLA_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_MLA_SHIFT 14 ++#define AR9_SW_GCTL0_REG_MLA_SIZE 1 ++/* Bit: 'MSA' */ ++/* Description: 'Mirror Short Also' */ ++#define AR9_SW_GCTL0_REG_MSA_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_MSA_SHIFT 13 ++#define AR9_SW_GCTL0_REG_MSA_SIZE 1 ++/* Bit: 'SNIFFPN' */ ++/* Description: 'Sniffer port number' */ ++#define AR9_SW_GCTL0_REG_SNIFFPN_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_SNIFFPN_SHIFT 10 ++#define AR9_SW_GCTL0_REG_SNIFFPN_SIZE 3 ++/* Bit: 'MPL' */ ++/* Description: 'Max Packet Length (MAXPKTLEN)' */ ++#define AR9_SW_GCTL0_REG_MPL_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_MPL_SHIFT 8 ++#define AR9_SW_GCTL0_REG_MPL_SIZE 2 ++/* Bit: 'DMQ3' */ ++/* Description: 'Discard Mode (Drop scheme for Packets Classified ++as Q3)' */ ++#define AR9_SW_GCTL0_REG_DMQ3_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_DMQ3_SHIFT 6 ++#define AR9_SW_GCTL0_REG_DMQ3_SIZE 2 ++/* Bit: 'DMQ2' */ ++/* Description: 'Discard Mode (Drop scheme for Packets Classified ++as Q2)' */ ++#define AR9_SW_GCTL0_REG_DMQ2_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_DMQ2_SHIFT 4 ++#define AR9_SW_GCTL0_REG_DMQ2_SIZE 2 ++/* Bit: 'DMQ1' */ ++/* Description: 'Discard Mode (Drop scheme for Packets Classified ++as Q1)' */ ++#define AR9_SW_GCTL0_REG_DMQ1_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_DMQ1_SHIFT 2 ++#define AR9_SW_GCTL0_REG_DMQ1_SIZE 2 ++/* Bit: 'DMQ0' */ ++/* Description: 'Discard Mode (Drop scheme for Packets Classified ++as Q0)' */ ++#define AR9_SW_GCTL0_REG_DMQ0_OFFSET 0x0068 ++#define AR9_SW_GCTL0_REG_DMQ0_SHIFT 0 ++#define AR9_SW_GCTL0_REG_DMQ0_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Switch Global Control Register 1' */ ++/* Bit: 'BISTDN' */ ++/* Description: 'BIST Done' */ ++#define AR9_SW_GCTL1_REG_BISTDN_OFFSET 0x006C ++#define AR9_SW_GCTL1_REG_BISTDN_SHIFT 27 ++#define AR9_SW_GCTL1_REG_BISTDN_SIZE 1 ++/* Bit: 'EDSTX' */ ++/* Description: 'Enable drop scheme of TX and RX' */ ++#define AR9_SW_GCTL1_REG_EDSTX_OFFSET 0x006C ++#define AR9_SW_GCTL1_REG_EDSTX_SHIFT 26 ++#define AR9_SW_GCTL1_REG_EDSTX_SIZE 1 ++/* Bit: 'CTTX' */ ++/* Description: 'Congestion threshold for TX queue' */ ++#define AR9_SW_GCTL1_REG_CTTX_OFFSET 0x006C ++#define AR9_SW_GCTL1_REG_CTTX_SHIFT 24 ++#define AR9_SW_GCTL1_REG_CTTX_SIZE 2 ++/* Bit: 'IJT' */ ++/* Description: 'Input Jam Threshold' */ ++#define AR9_SW_GCTL1_REG_IJT_OFFSET 0x006C ++#define AR9_SW_GCTL1_REG_IJT_SHIFT 21 ++#define AR9_SW_GCTL1_REG_IJT_SIZE 3 ++/* Bit: 'DIVS' */ ++/* Description: 'Do not Identify VLAN after SNAP' */ ++#define AR9_SW_GCTL1_REG_DIVS_OFFSET 0x006C ++#define AR9_SW_GCTL1_REG_DIVS_SHIFT 20 ++#define AR9_SW_GCTL1_REG_DIVS_SIZE 1 ++/* Bit: 'DII6P' */ ++/* Description: 'Do not Identify IPV6 in PPPOE' */ ++#define AR9_SW_GCTL1_REG_DII6P_OFFSET 0x006C ++#define AR9_SW_GCTL1_REG_DII6P_SHIFT 19 ++#define AR9_SW_GCTL1_REG_DII6P_SIZE 1 ++/* Bit: 'DIIPS' */ ++/* Description: 'Do not Identify IP in PPPOE after SNAP' */ ++#define AR9_SW_GCTL1_REG_DIIPS_OFFSET 0x006C ++#define AR9_SW_GCTL1_REG_DIIPS_SHIFT 18 ++#define AR9_SW_GCTL1_REG_DIIPS_SIZE 1 ++/* Bit: 'DIE' */ ++/* Description: 'Do not Identify IPV6' */ ++#define AR9_SW_GCTL1_REG_DIE_OFFSET 0x006C ++#define AR9_SW_GCTL1_REG_DIE_SHIFT 17 ++#define AR9_SW_GCTL1_REG_DIE_SIZE 1 ++/* Bit: 'DIIP' */ ++/* Description: 'Do not Identify IPv4 in PPPOE' */ ++#define AR9_SW_GCTL1_REG_DIIP_OFFSET 0x006C ++#define AR9_SW_GCTL1_REG_DIIP_SHIFT 16 ++#define AR9_SW_GCTL1_REG_DIIP_SIZE 1 ++/* Bit: 'DIS' */ ++/* Description: 'Do not Identify SNAP' */ ++#define AR9_SW_GCTL1_REG_DIS_OFFSET 0x006C ++#define AR9_SW_GCTL1_REG_DIS_SHIFT 15 ++#define AR9_SW_GCTL1_REG_DIS_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Default Portmap Register' */ ++/* Bit: 'UP' */ ++/* Description: 'Unknown Unicast Portmap' */ ++#define AR9_DF_PORTMAP_REG_UP_OFFSET 0x002C ++#define AR9_DF_PORTMAP_REG_UP_SHIFT 24 ++#define AR9_DF_PORTMAP_REG_UP_SIZE 8 ++/* Bit: 'BP' */ ++/* Description: 'Broadcast Portmap' */ ++#define AR9_DF_PORTMAP_REG_BP_OFFSET 0x002C ++#define AR9_DF_PORTMAP_REG_BP_SHIFT 16 ++#define AR9_DF_PORTMAP_REG_BP_SIZE 8 ++/* Bit: 'MP' */ ++/* Description: 'Unknown Multicast Portmap' */ ++#define AR9_DF_PORTMAP_REG_MP_OFFSET 0x002C ++#define AR9_DF_PORTMAP_REG_MP_SHIFT 8 ++#define AR9_DF_PORTMAP_REG_MP_SIZE 8 ++/* Bit: 'RP' */ ++/* Description: 'Reserve Portmap' */ ++#define AR9_DF_PORTMAP_REG_RP_OFFSET 0x002C ++#define AR9_DF_PORTMAP_REG_RP_SHIFT 0 ++#define AR9_DF_PORTMAP_REG_RP_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'ARP/RARP Register' */ ++/* Bit: 'MACA' */ ++/* Description: 'MAC Control Action' */ ++#define AR9_ARP_REG_MACA_OFFSET 0x0070 ++#define AR9_ARP_REG_MACA_SHIFT 14 ++#define AR9_ARP_REG_MACA_SIZE 2 ++/* Bit: 'UPT' */ ++/* Description: 'Unicast packet Treated as Cross_VLAN packet' */ ++#define AR9_ARP_REG_UPT_OFFSET 0x0070 ++#define AR9_ARP_REG_UPT_SHIFT 13 ++#define AR9_ARP_REG_UPT_SIZE 1 ++/* Bit: 'RPT' */ ++/* Description: 'RARP Packet Treated as Cross_VLAN Packet' */ ++#define AR9_ARP_REG_RPT_OFFSET 0x0070 ++#define AR9_ARP_REG_RPT_SHIFT 12 ++#define AR9_ARP_REG_RPT_SIZE 1 ++/* Bit: 'RAPA' */ ++/* Description: 'RARP/ARP Packet Action' */ ++#define AR9_ARP_REG_RAPA_OFFSET 0x0070 ++#define AR9_ARP_REG_RAPA_SHIFT 10 ++#define AR9_ARP_REG_RAPA_SIZE 2 ++/* Bit: 'RAPPE' */ ++/* Description: 'RARP/ARP Packet Priority Enable' */ ++#define AR9_ARP_REG_RAPPE_OFFSET 0x0070 ++#define AR9_ARP_REG_RAPPE_SHIFT 9 ++#define AR9_ARP_REG_RAPPE_SIZE 1 ++/* Bit: 'RAPP' */ ++/* Description: 'RARP/ARP Packet Priority' */ ++#define AR9_ARP_REG_RAPP_OFFSET 0x0070 ++#define AR9_ARP_REG_RAPP_SHIFT 7 ++#define AR9_ARP_REG_RAPP_SIZE 2 ++/* Bit: 'RAPOTH' */ ++/* Description: 'RARP/ARP Packet Output Tag Handle' */ ++#define AR9_ARP_REG_RAPOTH_OFFSET 0x0070 ++#define AR9_ARP_REG_RAPOTH_SHIFT 5 ++#define AR9_ARP_REG_RAPOTH_SIZE 2 ++/* Bit: 'APT' */ ++/* Description: 'ARP Packet Treated as Cross _ VLAN Packet' */ ++#define AR9_ARP_REG_APT_OFFSET 0x0070 ++#define AR9_ARP_REG_APT_SHIFT 4 ++#define AR9_ARP_REG_APT_SIZE 1 ++/* Bit: 'RAPTM' */ ++/* Description: 'RARP/ARP Packet Treated as Management Packet' */ ++#define AR9_ARP_REG_RAPTM_OFFSET 0x0070 ++#define AR9_ARP_REG_RAPTM_SHIFT 3 ++#define AR9_ARP_REG_RAPTM_SIZE 1 ++/* Bit: 'TAPTS' */ ++/* Description: 'RARP/ARP Packet Treated as Span Packet' */ ++#define AR9_ARP_REG_TAPTS_OFFSET 0x0070 ++#define AR9_ARP_REG_TAPTS_SHIFT 2 ++#define AR9_ARP_REG_TAPTS_SIZE 1 ++/* Bit: 'TAP' */ ++/* Description: 'Trap ARP Packet' */ ++#define AR9_ARP_REG_TAP_OFFSET 0x0070 ++#define AR9_ARP_REG_TAP_SHIFT 1 ++#define AR9_ARP_REG_TAP_SIZE 1 ++/* Bit: 'TRP' */ ++/* Description: 'Trap RARP Packet' */ ++#define AR9_ARP_REG_TRP_OFFSET 0x0070 ++#define AR9_ARP_REG_TRP_SHIFT 0 ++#define AR9_ARP_REG_TRP_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Storm control Register' */ ++/* Bit: 'STORM_10_TH' */ ++/* Description: '10M Threshold' */ ++#define AR9_STRM_CTL_REG_STORM_10_TH_OFFSET 0x0074 ++#define AR9_STRM_CTL_REG_STORM_10_TH_SHIFT 16 ++#define AR9_STRM_CTL_REG_STORM_10_TH_SIZE 13 ++/* Bit: 'STORM_B' */ ++/* Description: 'Storm Enable for Broadcast Packets' */ ++#define AR9_STRM_CTL_REG_STORM_B_OFFSET 0x0074 ++#define AR9_STRM_CTL_REG_STORM_B_SHIFT 15 ++#define AR9_STRM_CTL_REG_STORM_B_SIZE 1 ++/* Bit: 'STORM_M' */ ++/* Description: 'Storm Enable for Multicast Packets' */ ++#define AR9_STRM_CTL_REG_STORM_M_OFFSET 0x0074 ++#define AR9_STRM_CTL_REG_STORM_M_SHIFT 14 ++#define AR9_STRM_CTL_REG_STORM_M_SIZE 1 ++/* Bit: 'STORM_U' */ ++/* Description: 'Storm Enable for Un-learned Unicast Packets' */ ++#define AR9_STRM_CTL_REG_STORM_U_OFFSET 0x0074 ++#define AR9_STRM_CTL_REG_STORM_U_SHIFT 13 ++#define AR9_STRM_CTL_REG_STORM_U_SIZE 1 ++/* Bit: 'STORM_100_TH' */ ++/* Description: '100M Threshold' */ ++#define AR9_STRM_CTL_REG_STORM_100_TH_OFFSET 0x0074 ++#define AR9_STRM_CTL_REG_STORM_100_TH_SHIFT 0 ++#define AR9_STRM_CTL_REG_STORM_100_TH_SIZE 13 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'RGMII/GMII Port Control Register' */ ++/* Bit: 'MCS' */ ++/* Description: 'Management Clock Select' */ ++#define AR9_RGMII_CTL_REG_MCS_OFFSET 0x0078 ++#define AR9_RGMII_CTL_REG_MCS_SHIFT 24 ++#define AR9_RGMII_CTL_REG_MCS_SIZE 8 ++/* Bit: 'P1CKIO' */ ++/* Description: 'Interface Clk PAD I/O Select' */ ++#define AR9_RGMII_CTL_REG_P1CKIO_OFFSET 0x0078 ++#define AR9_RGMII_CTL_REG_P1CKIO_SHIFT 23 ++#define AR9_RGMII_CTL_REG_P1CKIO_SIZE 1 ++/* Bit: 'P1Feq' */ ++/* Description: 'Interface Reverse MII Clk Frequency' */ ++#define AR9_RGMII_CTL_REG_P1FEQ_OFFSET 0x0078 ++#define AR9_RGMII_CTL_REG_P1FEQ_SHIFT 22 ++#define AR9_RGMII_CTL_REG_P1FEQ_SIZE 1 ++/* Bit: 'P0CKIO' */ ++/* Description: 'Interface Clk PAD I/O Select' */ ++#define AR9_RGMII_CTL_REG_P0CKIO_OFFSET 0x0078 ++#define AR9_RGMII_CTL_REG_P0CKIO_SHIFT 21 ++#define AR9_RGMII_CTL_REG_P0CKIO_SIZE 1 ++/* Bit: 'P0Feq' */ ++/* Description: 'Interface Reverse MII Clk Frequency' */ ++#define AR9_RGMII_CTL_REG_P0FEQ_OFFSET 0x0078 ++#define AR9_RGMII_CTL_REG_P0FEQ_SHIFT 20 ++#define AR9_RGMII_CTL_REG_P0FEQ_SIZE 1 ++/* Bit: 'P1IS' */ ++/* Description: 'Interface Selection' */ ++#define AR9_RGMII_CTL_REG_P1IS_OFFSET 0x0078 ++#define AR9_RGMII_CTL_REG_P1IS_SHIFT 18 ++#define AR9_RGMII_CTL_REG_P1IS_SIZE 2 ++/* Bit: 'P1RDLY' */ ++/* Description: 'Port 1 RGMII Rx Clock Delay' */ ++#define AR9_RGMII_CTL_REG_P1RDLY_OFFSET 0x0078 ++#define AR9_RGMII_CTL_REG_P1RDLY_SHIFT 16 ++#define AR9_RGMII_CTL_REG_P1RDLY_SIZE 2 ++/* Bit: 'P1TDLY' */ ++/* Description: 'Port 1 RGMII Tx Clock Delay' */ ++#define AR9_RGMII_CTL_REG_P1TDLY_OFFSET 0x0078 ++#define AR9_RGMII_CTL_REG_P1TDLY_SHIFT 14 ++#define AR9_RGMII_CTL_REG_P1TDLY_SIZE 2 ++/* Bit: 'P1SPD' */ ++/* Description: 'Port 1 Speed' */ ++#define AR9_RGMII_CTL_REG_P1SPD_OFFSET 0x0078 ++#define AR9_RGMII_CTL_REG_P1SPD_SHIFT 12 ++#define AR9_RGMII_CTL_REG_P1SPD_SIZE 2 ++/* Bit: 'P1DUP' */ ++/* Description: 'Port 1 Duplex mode' */ ++#define AR9_RGMII_CTL_REG_P1DUP_OFFSET 0x0078 ++#define AR9_RGMII_CTL_REG_P1DUP_SHIFT 11 ++#define AR9_RGMII_CTL_REG_P1DUP_SIZE 1 ++/* Bit: 'P1FCE' */ ++/* Description: 'Port 1 Flow Control Enable' */ ++#define AR9_RGMII_CTL_REG_P1FCE_OFFSET 0x0078 ++#define AR9_RGMII_CTL_REG_P1FCE_SHIFT 10 ++#define AR9_RGMII_CTL_REG_P1FCE_SIZE 1 ++/* Bit: 'P0IS' */ ++/* Description: 'Interface Selection' */ ++#define AR9_RGMII_CTL_REG_P0IS_OFFSET 0x0078 ++#define AR9_RGMII_CTL_REG_P0IS_SHIFT 8 ++#define AR9_RGMII_CTL_REG_P0IS_SIZE 2 ++/* Bit: 'P0RDLY' */ ++/* Description: 'Port 0 RGMII Rx Clock Delay' */ ++#define AR9_RGMII_CTL_REG_P0RDLY_OFFSET 0x0078 ++#define AR9_RGMII_CTL_REG_P0RDLY_SHIFT 6 ++#define AR9_RGMII_CTL_REG_P0RDLY_SIZE 2 ++/* Bit: 'P0TDLY' */ ++/* Description: 'Port 0 RGMII Tx Clock Delay' */ ++#define AR9_RGMII_CTL_REG_P0TDLY_OFFSET 0x0078 ++#define AR9_RGMII_CTL_REG_P0TDLY_SHIFT 4 ++#define AR9_RGMII_CTL_REG_P0TDLY_SIZE 2 ++/* Bit: 'P0SPD' */ ++/* Description: 'Port 0 Speed' */ ++#define AR9_RGMII_CTL_REG_P0SPD_OFFSET 0x0078 ++#define AR9_RGMII_CTL_REG_P0SPD_SHIFT 2 ++#define AR9_RGMII_CTL_REG_P0SPD_SIZE 2 ++/* Bit: 'P0DUP' */ ++/* Description: 'Port 0 Duplex mode' */ ++#define AR9_RGMII_CTL_REG_P0DUP_OFFSET 0x0078 ++#define AR9_RGMII_CTL_REG_P0DUP_SHIFT 1 ++#define AR9_RGMII_CTL_REG_P0DUP_SIZE 1 ++/* Bit: 'P0FCE' */ ++/* Description: 'Port 0 Flow Control Enable' */ ++#define AR9_RGMII_CTL_REG_P0FCE_OFFSET 0x0078 ++#define AR9_RGMII_CTL_REG_P0FCE_SHIFT 0 ++#define AR9_RGMII_CTL_REG_P0FCE_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: '802.1p Priority Map Register' */ ++/* Bit: '1PPQ7' */ ++/* Description: 'Priority Queue 7' */ ++#define AR9_1P_PRT_REG_1PPQ7_OFFSET 0x007C ++#define AR9_1P_PRT_REG_1PPQ7_SHIFT 14 ++#define AR9_1P_PRT_REG_1PPQ7_SIZE 2 ++/* Bit: '1PPQ6' */ ++/* Description: 'Priority Queue 6' */ ++#define AR9_1P_PRT_REG_1PPQ6_OFFSET 0x007C ++#define AR9_1P_PRT_REG_1PPQ6_SHIFT 12 ++#define AR9_1P_PRT_REG_1PPQ6_SIZE 2 ++/* Bit: '1PPQ5' */ ++/* Description: 'Priority Queue 5' */ ++#define AR9_1P_PRT_REG_1PPQ5_OFFSET 0x007C ++#define AR9_1P_PRT_REG_1PPQ5_SHIFT 10 ++#define AR9_1P_PRT_REG_1PPQ5_SIZE 2 ++/* Bit: '1PPQ4' */ ++/* Description: 'Priority Queue 4' */ ++#define AR9_1P_PRT_REG_1PPQ4_OFFSET 0x007C ++#define AR9_1P_PRT_REG_1PPQ4_SHIFT 8 ++#define AR9_1P_PRT_REG_1PPQ4_SIZE 2 ++/* Bit: '1PPQ3' */ ++/* Description: 'Priority Queue 3' */ ++#define AR9_1P_PRT_REG_1PPQ3_OFFSET 0x007C ++#define AR9_1P_PRT_REG_1PPQ3_SHIFT 6 ++#define AR9_1P_PRT_REG_1PPQ3_SIZE 2 ++/* Bit: '1PPQ2' */ ++/* Description: 'Priority Queue 2' */ ++#define AR9_1P_PRT_REG_1PPQ2_OFFSET 0x007C ++#define AR9_1P_PRT_REG_1PPQ2_SHIFT 4 ++#define AR9_1P_PRT_REG_1PPQ2_SIZE 2 ++/* Bit: '1PPQ1' */ ++/* Description: 'Priority Queue 1' */ ++#define AR9_1P_PRT_REG_1PPQ1_OFFSET 0x007C ++#define AR9_1P_PRT_REG_1PPQ1_SHIFT 2 ++#define AR9_1P_PRT_REG_1PPQ1_SIZE 2 ++/* Bit: '1PPQ0' */ ++/* Description: 'Priority Queue 0' */ ++#define AR9_1P_PRT_REG_1PPQ0_OFFSET 0x007C ++#define AR9_1P_PRT_REG_1PPQ0_SHIFT 0 ++#define AR9_1P_PRT_REG_1PPQ0_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ingress Policing Flow Control On Watermark' */ ++/* Bit: 'F' */ ++/* Description: 'Ingress Policing Flow Control On Watermark' */ ++#define AR9_PAUSE_ON_WM_F_OFFSET 0x0080 ++#define AR9_PAUSE_ON_WM_F_SHIFT 0 ++#define AR9_PAUSE_ON_WM_F_SIZE 18 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ingress Policing Flow Control Off Watermark' */ ++/* Bit: 'B' */ ++/* Description: 'Ingress Policing Flow Control Off Watermark' */ ++#define AR9_PAUSE_OFF_WM_B_OFFSET 0x0084 ++#define AR9_PAUSE_OFF_WM_B_SHIFT 0 ++#define AR9_PAUSE_OFF_WM_B_SIZE 18 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Buffer Threshold Register' */ ++/* Bit: 'PUO2' */ ++/* Description: 'Port 2 Based Flow Control Off Watermark Offset' */ ++#define AR9_BF_TH_REG_PUO2_OFFSET 0x0088 ++#define AR9_BF_TH_REG_PUO2_SHIFT 30 ++#define AR9_BF_TH_REG_PUO2_SIZE 2 ++/* Bit: 'PUO1' */ ++/* Description: 'Port 1 Based Flow Control Off Watermark Offset' */ ++#define AR9_BF_TH_REG_PUO1_OFFSET 0x0088 ++#define AR9_BF_TH_REG_PUO1_SHIFT 28 ++#define AR9_BF_TH_REG_PUO1_SIZE 2 ++/* Bit: 'PUO0' */ ++/* Description: 'Port 0 Based Flow Control Off Watermark Offset' */ ++#define AR9_BF_TH_REG_PUO0_OFFSET 0x0088 ++#define AR9_BF_TH_REG_PUO0_SHIFT 26 ++#define AR9_BF_TH_REG_PUO0_SIZE 2 ++/* Bit: 'PFO2' */ ++/* Description: 'Port 2 Based Flow Control On Watermark Offset' */ ++#define AR9_BF_TH_REG_PFO2_OFFSET 0x0088 ++#define AR9_BF_TH_REG_PFO2_SHIFT 22 ++#define AR9_BF_TH_REG_PFO2_SIZE 2 ++/* Bit: 'PFO1' */ ++/* Description: 'Port 1 Based Flow Control On Watermark Offset' */ ++#define AR9_BF_TH_REG_PFO1_OFFSET 0x0088 ++#define AR9_BF_TH_REG_PFO1_SHIFT 20 ++#define AR9_BF_TH_REG_PFO1_SIZE 2 ++/* Bit: 'PFO0' */ ++/* Description: 'Port 0 Based Flow Control On Watermark Offset' */ ++#define AR9_BF_TH_REG_PFO0_OFFSET 0x0088 ++#define AR9_BF_TH_REG_PFO0_SHIFT 18 ++#define AR9_BF_TH_REG_PFO0_SIZE 2 ++/* Bit: 'TLA' */ ++/* Description: 'Global Flow Control Stop Watermark Selection' */ ++#define AR9_BF_TH_REG_TLA_OFFSET 0x0088 ++#define AR9_BF_TH_REG_TLA_SHIFT 13 ++#define AR9_BF_TH_REG_TLA_SIZE 1 ++/* Bit: 'THA' */ ++/* Description: 'Global Flow Control On Watermark Selection' */ ++#define AR9_BF_TH_REG_THA_OFFSET 0x0088 ++#define AR9_BF_TH_REG_THA_SHIFT 12 ++#define AR9_BF_TH_REG_THA_SIZE 1 ++/* Bit: 'TLO' */ ++/* Description: 'Global Flow Control Off Watermark Offset' */ ++#define AR9_BF_TH_REG_TLO_OFFSET 0x0088 ++#define AR9_BF_TH_REG_TLO_SHIFT 10 ++#define AR9_BF_TH_REG_TLO_SIZE 2 ++/* Bit: 'THO' */ ++/* Description: 'Global Flow Control On Watermark Offset' */ ++#define AR9_BF_TH_REG_THO_OFFSET 0x0088 ++#define AR9_BF_TH_REG_THO_SHIFT 8 ++#define AR9_BF_TH_REG_THO_SIZE 2 ++/* Bit: 'PUA' */ ++/* Description: 'Port Based Flow Control Off Watermark Selection ' */ ++#define AR9_BF_TH_REG_PUA_OFFSET 0x0088 ++#define AR9_BF_TH_REG_PUA_SHIFT 5 ++#define AR9_BF_TH_REG_PUA_SIZE 3 ++/* Bit: 'PFA' */ ++/* Description: 'Port Based Flow Control on Watermark Selection' */ ++#define AR9_BF_TH_REG_PFA_OFFSET 0x0088 ++#define AR9_BF_TH_REG_PFA_SHIFT 1 ++#define AR9_BF_TH_REG_PFA_SIZE 3 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PMAC Header Control Register' */ ++/* Bit: 'RES' */ ++/* Description: 'Reserved' */ ++#define AR9_PMAC_HD_CTL_RES_OFFSET 0x008C ++#define AR9_PMAC_HD_CTL_RES_SHIFT 23 ++#define AR9_PMAC_HD_CTL_RES_SIZE 9 ++/* Bit: 'RXSH' */ ++/* Description: 'Status Header for Packets from DMA to PMAC' */ ++#define AR9_PMAC_HD_CTL_RXSH_OFFSET 0x008C ++#define AR9_PMAC_HD_CTL_RXSH_SHIFT 22 ++#define AR9_PMAC_HD_CTL_RXSH_SIZE 1 ++/* Bit: 'RL2' */ ++/* Description: 'Remove Layer-2 Header from Packets Going from PMAC ++to DMA' */ ++#define AR9_PMAC_HD_CTL_RL2_OFFSET 0x008C ++#define AR9_PMAC_HD_CTL_RL2_SHIFT 21 ++#define AR9_PMAC_HD_CTL_RL2_SIZE 1 ++/* Bit: 'RC' */ ++/* Description: 'Remove CRC from Packets Going from PMAC to DMA' */ ++#define AR9_PMAC_HD_CTL_RC_OFFSET 0x008C ++#define AR9_PMAC_HD_CTL_RC_SHIFT 20 ++#define AR9_PMAC_HD_CTL_RC_SIZE 1 ++/* Bit: 'AS' */ ++/* Description: 'Status Header for Packets from PMAC to DMA' */ ++#define AR9_PMAC_HD_CTL_AS_OFFSET 0x008C ++#define AR9_PMAC_HD_CTL_AS_SHIFT 19 ++#define AR9_PMAC_HD_CTL_AS_SIZE 1 ++/* Bit: 'AC' */ ++/* Description: 'Add CRC for packets from DMA to PMAC' */ ++#define AR9_PMAC_HD_CTL_AC_OFFSET 0x008C ++#define AR9_PMAC_HD_CTL_AC_SHIFT 18 ++#define AR9_PMAC_HD_CTL_AC_SIZE 1 ++/* Bit: 'TYPE_LEN' */ ++/* Description: 'Contains the length/type value to the added to packets ++from DMA to PMAC' */ ++#define AR9_PMAC_HD_CTL_TYPE_LEN_OFFSET 0x008C ++#define AR9_PMAC_HD_CTL_TYPE_LEN_SHIFT 2 ++#define AR9_PMAC_HD_CTL_TYPE_LEN_SIZE 16 ++/* Bit: 'TAG' */ ++/* Description: 'Add TAG to Packets from DMA to PMAC' */ ++#define AR9_PMAC_HD_CTL_TAG_OFFSET 0x008C ++#define AR9_PMAC_HD_CTL_TAG_SHIFT 1 ++#define AR9_PMAC_HD_CTL_TAG_SIZE 1 ++/* Bit: 'ADD' */ ++/* Description: 'ADD Header to Packets from DMA to PMAC' */ ++#define AR9_PMAC_HD_CTL_ADD_OFFSET 0x008C ++#define AR9_PMAC_HD_CTL_ADD_SHIFT 0 ++#define AR9_PMAC_HD_CTL_ADD_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PMAC Source Address Register 1' */ ++/* Bit: 'SA_47_32' */ ++/* Description: 'Source Address to be inserted as a part of the Ethernet ++header.' */ ++#define AR9_PMAC_SA1_SA_47_32_OFFSET 0x0090 ++#define AR9_PMAC_SA1_SA_47_32_SHIFT 0 ++#define AR9_PMAC_SA1_SA_47_32_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PMAC Source Address Register 2' */ ++/* Bit: 'SA_31_0' */ ++/* Description: 'Source Address' */ ++#define AR9_PMAC_SA2_SA_31_0_OFFSET 0x0094 ++#define AR9_PMAC_SA2_SA_31_0_SHIFT 0 ++#define AR9_PMAC_SA2_SA_31_0_SIZE 32 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PMAC Destination Address Register 1' */ ++/* Bit: 'DA_47_32' */ ++/* Description: 'Destination Address' */ ++#define AR9_PMAC_DA1_DA_47_32_OFFSET 0x0098 ++#define AR9_PMAC_DA1_DA_47_32_SHIFT 0 ++#define AR9_PMAC_DA1_DA_47_32_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PMAC Destination Address Register 2' */ ++/* Bit: 'DA_31_0' */ ++/* Description: 'Destination Address to be inserted as a part of ++the Ethernet header.' */ ++#define AR9_PMAC_DA2_DA_31_0_OFFSET 0x009C ++#define AR9_PMAC_DA2_DA_31_0_SHIFT 0 ++#define AR9_PMAC_DA2_DA_31_0_SIZE 32 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PMAC VLAN Register' */ ++/* Bit: 'PRI' */ ++/* Description: 'Priority to be inserted as a part of VLAN tag' */ ++#define AR9_PMAC_VLAN_PRI_OFFSET 0x00A0 ++#define AR9_PMAC_VLAN_PRI_SHIFT 13 ++#define AR9_PMAC_VLAN_PRI_SIZE 3 ++/* Bit: 'CFI' */ ++/* Description: 'CFI bit to be inserted as a part of VLAN tag' */ ++#define AR9_PMAC_VLAN_CFI_OFFSET 0x00A0 ++#define AR9_PMAC_VLAN_CFI_SHIFT 12 ++#define AR9_PMAC_VLAN_CFI_SIZE 1 ++/* Bit: 'VLAN ID' */ ++/* Description: 'VLAN ID to be inserted as a part of VLAN tag' */ ++#define AR9_PMAC_VLAN_VLAN_ID_OFFSET 0x00A0 ++#define AR9_PMAC_VLAN_VLAN_ID_SHIFT 0 ++#define AR9_PMAC_VLAN_VLAN_ID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PMAC TX IPG Counter Register' */ ++/* Bit: 'IPG_CNT' */ ++/* Description: 'IPG Counter' */ ++#define AR9_PMAC_TX_IPG_IPG_CNT_OFFSET 0x00A4 ++#define AR9_PMAC_TX_IPG_IPG_CNT_SHIFT 0 ++#define AR9_PMAC_TX_IPG_IPG_CNT_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PMAC RX IPG Counter Register' */ ++/* Bit: 'IDIS_REQ_WM' */ ++/* Description: 'Disable RX FIFO Request Watermark' */ ++#define AR9_PMAC_RX_IPG_IDIS_REQ_WM_OFFSET 0x00A8 ++#define AR9_PMAC_RX_IPG_IDIS_REQ_WM_SHIFT 8 ++#define AR9_PMAC_RX_IPG_IDIS_REQ_WM_SIZE 1 ++/* Bit: 'IREQ_WM' */ ++/* Description: 'RX FIFO Request Watermark' */ ++#define AR9_PMAC_RX_IPG_IREQ_WM_OFFSET 0x00A8 ++#define AR9_PMAC_RX_IPG_IREQ_WM_SHIFT 4 ++#define AR9_PMAC_RX_IPG_IREQ_WM_SIZE 4 ++/* Bit: 'IPG_CNT' */ ++/* Description: 'IPG Counter' */ ++#define AR9_PMAC_RX_IPG_IPG_CNT_OFFSET 0x00A8 ++#define AR9_PMAC_RX_IPG_IPG_CNT_SHIFT 0 ++#define AR9_PMAC_RX_IPG_IPG_CNT_SIZE 4 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Address Table Control 0 Register' */ ++/* Bit: 'ADDR31_0' */ ++/* Description: 'Address [31:0]' */ ++#define AR9_ADR_TB_CTL0_REG_ADDR31_0_OFFSET 0x00AC ++#define AR9_ADR_TB_CTL0_REG_ADDR31_0_SHIFT 0 ++#define AR9_ADR_TB_CTL0_REG_ADDR31_0_SIZE 32 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Address Table Control 1 Register' */ ++/* Bit: 'PMAP' */ ++/* Description: 'Port Map' */ ++#define AR9_ADR_TB_CTL1_REG_PMAP_OFFSET 0x00B0 ++#define AR9_ADR_TB_CTL1_REG_PMAP_SHIFT 20 ++#define AR9_ADR_TB_CTL1_REG_PMAP_SIZE 8 ++/* Bit: 'FID' */ ++/* Description: 'FID group' */ ++#define AR9_ADR_TB_CTL1_REG_FID_OFFSET 0x00B0 ++#define AR9_ADR_TB_CTL1_REG_FID_SHIFT 16 ++#define AR9_ADR_TB_CTL1_REG_FID_SIZE 2 ++/* Bit: 'ADDR47_32' */ ++/* Description: 'Address [47:32]' */ ++#define AR9_ADR_TB_CTL1_REG_ADDR47_32_OFFSET 0x00B0 ++#define AR9_ADR_TB_CTL1_REG_ADDR47_32_SHIFT 0 ++#define AR9_ADR_TB_CTL1_REG_ADDR47_32_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Address Table Control 2 Register' */ ++/* Bit: 'IFCE' */ ++/* Description: 'Find Within Current HASH' */ ++#define AR9_ADR_TB_CTL2_REG_IFCE_OFFSET 0x00B4 ++#define AR9_ADR_TB_CTL2_REG_IFCE_SHIFT 23 ++#define AR9_ADR_TB_CTL2_REG_IFCE_SIZE 1 ++/* Bit: 'CMD' */ ++/* Description: 'Command' */ ++#define AR9_ADR_TB_CTL2_REG_CMD_OFFSET 0x00B4 ++#define AR9_ADR_TB_CTL2_REG_CMD_SHIFT 20 ++#define AR9_ADR_TB_CTL2_REG_CMD_SIZE 3 ++/* Bit: 'AC' */ ++/* Description: 'Access Control' */ ++#define AR9_ADR_TB_CTL2_REG_AC_OFFSET 0x00B4 ++#define AR9_ADR_TB_CTL2_REG_AC_SHIFT 16 ++#define AR9_ADR_TB_CTL2_REG_AC_SIZE 4 ++/* Bit: 'INFOT' */ ++/* Description: 'Info Type: Static address' */ ++#define AR9_ADR_TB_CTL2_REG_INFOT_OFFSET 0x00B4 ++#define AR9_ADR_TB_CTL2_REG_INFOT_SHIFT 12 ++#define AR9_ADR_TB_CTL2_REG_INFOT_SIZE 1 ++/* Bit: 'ITAT' */ ++/* Description: 'Info_Ctrl/Age Timer' */ ++#define AR9_ADR_TB_CTL2_REG_ITAT_OFFSET 0x00B4 ++#define AR9_ADR_TB_CTL2_REG_ITAT_SHIFT 0 ++#define AR9_ADR_TB_CTL2_REG_ITAT_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Address Table Status 0 Register' */ ++/* Bit: 'ADDRS31_0' */ ++/* Description: 'Address [31:0]' */ ++#define AR9_ADR_TB_ST0_REG_ADDRS31_0_OFFSET 0x00B8 ++#define AR9_ADR_TB_ST0_REG_ADDRS31_0_SHIFT 0 ++#define AR9_ADR_TB_ST0_REG_ADDRS31_0_SIZE 32 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Address Table Status 1 Register' */ ++/* Bit: 'PMAPS' */ ++/* Description: 'Port Map' */ ++#define AR9_ADR_TB_ST1_REG_PMAPS_OFFSET 0x00BC ++#define AR9_ADR_TB_ST1_REG_PMAPS_SHIFT 20 ++#define AR9_ADR_TB_ST1_REG_PMAPS_SIZE 8 ++/* Bit: 'FIDS' */ ++/* Description: 'FID group' */ ++#define AR9_ADR_TB_ST1_REG_FIDS_OFFSET 0x00BC ++#define AR9_ADR_TB_ST1_REG_FIDS_SHIFT 16 ++#define AR9_ADR_TB_ST1_REG_FIDS_SIZE 2 ++/* Bit: 'ADDRS47_32' */ ++/* Description: 'Address [47:32]' */ ++#define AR9_ADR_TB_ST1_REG_ADDRS47_32_OFFSET 0x00BC ++#define AR9_ADR_TB_ST1_REG_ADDRS47_32_SHIFT 0 ++#define AR9_ADR_TB_ST1_REG_ADDRS47_32_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Address Table Status 2 Register' */ ++/* Bit: 'BUSY' */ ++/* Description: 'Busy: Access Logic is Busy' */ ++#define AR9_ADR_TB_ST2_REG_BUSY_OFFSET 0x00C0 ++#define AR9_ADR_TB_ST2_REG_BUSY_SHIFT 31 ++#define AR9_ADR_TB_ST2_REG_BUSY_SIZE 1 ++/* Bit: 'RSLT' */ ++/* Description: 'Result' */ ++#define AR9_ADR_TB_ST2_REG_RSLT_OFFSET 0x00C0 ++#define AR9_ADR_TB_ST2_REG_RSLT_SHIFT 28 ++#define AR9_ADR_TB_ST2_REG_RSLT_SIZE 3 ++/* Bit: 'CMD' */ ++/* Description: 'Command' */ ++#define AR9_ADR_TB_ST2_REG_CMD_OFFSET 0x00C0 ++#define AR9_ADR_TB_ST2_REG_CMD_SHIFT 20 ++#define AR9_ADR_TB_ST2_REG_CMD_SIZE 3 ++/* Bit: 'AC' */ ++/* Description: 'Access Control' */ ++#define AR9_ADR_TB_ST2_REG_AC_OFFSET 0x00C0 ++#define AR9_ADR_TB_ST2_REG_AC_SHIFT 16 ++#define AR9_ADR_TB_ST2_REG_AC_SIZE 4 ++/* Bit: 'BAD' */ ++/* Description: 'Bad Status' */ ++#define AR9_ADR_TB_ST2_REG_BAD_OFFSET 0x00C0 ++#define AR9_ADR_TB_ST2_REG_BAD_SHIFT 14 ++#define AR9_ADR_TB_ST2_REG_BAD_SIZE 1 ++/* Bit: 'OCP' */ ++/* Description: 'Occupy Status' */ ++#define AR9_ADR_TB_ST2_REG_OCP_OFFSET 0x00C0 ++#define AR9_ADR_TB_ST2_REG_OCP_SHIFT 13 ++#define AR9_ADR_TB_ST2_REG_OCP_SIZE 1 ++/* Bit: 'INFOTS' */ ++/* Description: 'Info Type: Static address' */ ++#define AR9_ADR_TB_ST2_REG_INFOTS_OFFSET 0x00C0 ++#define AR9_ADR_TB_ST2_REG_INFOTS_SHIFT 12 ++#define AR9_ADR_TB_ST2_REG_INFOTS_SIZE 1 ++/* Bit: 'ITATS' */ ++/* Description: 'Info_Ctrl/Age Timer Status' */ ++#define AR9_ADR_TB_ST2_REG_ITATS_OFFSET 0x00C0 ++#define AR9_ADR_TB_ST2_REG_ITATS_SHIFT 0 ++#define AR9_ADR_TB_ST2_REG_ITATS_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'RMON Counter Control Register' */ ++/* Bit: 'BAS' */ ++/* Description: 'Busy/Access Start' */ ++#define AR9_RMON_CTL_REG_BAS_OFFSET 0x00C4 ++#define AR9_RMON_CTL_REG_BAS_SHIFT 11 ++#define AR9_RMON_CTL_REG_BAS_SIZE 1 ++/* Bit: 'CAC' */ ++/* Description: 'Command for access counter' */ ++#define AR9_RMON_CTL_REG_CAC_OFFSET 0x00C4 ++#define AR9_RMON_CTL_REG_CAC_SHIFT 9 ++#define AR9_RMON_CTL_REG_CAC_SIZE 2 ++/* Bit: 'PORTC' */ ++/* Description: 'Port' */ ++#define AR9_RMON_CTL_REG_PORTC_OFFSET 0x00C4 ++#define AR9_RMON_CTL_REG_PORTC_SHIFT 6 ++#define AR9_RMON_CTL_REG_PORTC_SIZE 3 ++/* Bit: 'OFFSET' */ ++/* Description: 'Counter Offset' */ ++#define AR9_RMON_CTL_REG_OFFSET_OFFSET 0x00C4 ++#define AR9_RMON_CTL_REG_OFFSET_SHIFT 0 ++#define AR9_RMON_CTL_REG_OFFSET_SIZE 6 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'RMON Counter Status Register' */ ++/* Bit: 'COUNTER' */ ++/* Description: 'RMON Counter field 31:0 or counter field 63:32' */ ++#define AR9_RMON_ST_REG_COUNTER_OFFSET 0x00C8 ++#define AR9_RMON_ST_REG_COUNTER_SHIFT 0 ++#define AR9_RMON_ST_REG_COUNTER_SIZE 32 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MDIO Indirect Access Control' */ ++/* Bit: 'WD' */ ++/* Description: 'The Write Data to the MDIO register' */ ++#define AR9_MDIO_CTL_REG_WD_OFFSET 0x00CC ++#define AR9_MDIO_CTL_REG_WD_SHIFT 16 ++#define AR9_MDIO_CTL_REG_WD_SIZE 16 ++/* Bit: 'MBUSY' */ ++/* Description: 'Busy state' */ ++#define AR9_MDIO_CTL_REG_MBUSY_OFFSET 0x00CC ++#define AR9_MDIO_CTL_REG_MBUSY_SHIFT 15 ++#define AR9_MDIO_CTL_REG_MBUSY_SIZE 1 ++/* Bit: 'OP' */ ++/* Description: 'Operation Code' */ ++#define AR9_MDIO_CTL_REG_OP_OFFSET 0x00CC ++#define AR9_MDIO_CTL_REG_OP_SHIFT 10 ++#define AR9_MDIO_CTL_REG_OP_SIZE 2 ++/* Bit: 'PHYAD' */ ++/* Description: 'PHY Address' */ ++#define AR9_MDIO_CTL_REG_PHYAD_OFFSET 0x00CC ++#define AR9_MDIO_CTL_REG_PHYAD_SHIFT 5 ++#define AR9_MDIO_CTL_REG_PHYAD_SIZE 5 ++/* Bit: 'REGAD' */ ++/* Description: 'Register Address' */ ++#define AR9_MDIO_CTL_REG_REGAD_OFFSET 0x00CC ++#define AR9_MDIO_CTL_REG_REGAD_SHIFT 0 ++#define AR9_MDIO_CTL_REG_REGAD_SIZE 5 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MDIO Indirect Read Data' */ ++/* Bit: 'RD' */ ++/* Description: 'The Read Data' */ ++#define AR9_MDIO_DATA_REG_RD_OFFSET 0x00D0 ++#define AR9_MDIO_DATA_REG_RD_SHIFT 0 ++#define AR9_MDIO_DATA_REG_RD_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Type Filter Action' */ ++/* Bit: 'QATF7' */ ++/* Description: 'Destination Queue for Type Filter 7' */ ++#define AR9_TP_FLT_ACT_REG_QATF7_OFFSET 0x00D4 ++#define AR9_TP_FLT_ACT_REG_QATF7_SHIFT 30 ++#define AR9_TP_FLT_ACT_REG_QATF7_SIZE 2 ++/* Bit: 'QATF6' */ ++/* Description: 'Destination Queue for Type Filter 6' */ ++#define AR9_TP_FLT_ACT_REG_QATF6_OFFSET 0x00D4 ++#define AR9_TP_FLT_ACT_REG_QATF6_SHIFT 28 ++#define AR9_TP_FLT_ACT_REG_QATF6_SIZE 2 ++/* Bit: 'QTF5' */ ++/* Description: 'Destination Queue for Type Filter 5' */ ++#define AR9_TP_FLT_ACT_REG_QTF5_OFFSET 0x00D4 ++#define AR9_TP_FLT_ACT_REG_QTF5_SHIFT 26 ++#define AR9_TP_FLT_ACT_REG_QTF5_SIZE 2 ++/* Bit: 'QTF4' */ ++/* Description: 'Destination Queue for Type Filter 4' */ ++#define AR9_TP_FLT_ACT_REG_QTF4_OFFSET 0x00D4 ++#define AR9_TP_FLT_ACT_REG_QTF4_SHIFT 24 ++#define AR9_TP_FLT_ACT_REG_QTF4_SIZE 2 ++/* Bit: 'QTF3' */ ++/* Description: 'Destination Queue for Type Filter 3' */ ++#define AR9_TP_FLT_ACT_REG_QTF3_OFFSET 0x00D4 ++#define AR9_TP_FLT_ACT_REG_QTF3_SHIFT 22 ++#define AR9_TP_FLT_ACT_REG_QTF3_SIZE 2 ++/* Bit: 'QTF2' */ ++/* Description: 'Destination Queue for Type Filter 2' */ ++#define AR9_TP_FLT_ACT_REG_QTF2_OFFSET 0x00D4 ++#define AR9_TP_FLT_ACT_REG_QTF2_SHIFT 20 ++#define AR9_TP_FLT_ACT_REG_QTF2_SIZE 2 ++/* Bit: 'QTF1' */ ++/* Description: 'Destination Queue for Type Filter 1' */ ++#define AR9_TP_FLT_ACT_REG_QTF1_OFFSET 0x00D4 ++#define AR9_TP_FLT_ACT_REG_QTF1_SHIFT 18 ++#define AR9_TP_FLT_ACT_REG_QTF1_SIZE 2 ++/* Bit: 'QTF0' */ ++/* Description: 'Destination Queue for Type Filter 0' */ ++#define AR9_TP_FLT_ACT_REG_QTF0_OFFSET 0x00D4 ++#define AR9_TP_FLT_ACT_REG_QTF0_SHIFT 16 ++#define AR9_TP_FLT_ACT_REG_QTF0_SIZE 2 ++/* Bit: 'ATF7' */ ++/* Description: 'Action for Type Filter 7' */ ++#define AR9_TP_FLT_ACT_REG_ATF7_OFFSET 0x00D4 ++#define AR9_TP_FLT_ACT_REG_ATF7_SHIFT 14 ++#define AR9_TP_FLT_ACT_REG_ATF7_SIZE 2 ++/* Bit: 'ATF6' */ ++/* Description: 'Action for Type Filter 6' */ ++#define AR9_TP_FLT_ACT_REG_ATF6_OFFSET 0x00D4 ++#define AR9_TP_FLT_ACT_REG_ATF6_SHIFT 12 ++#define AR9_TP_FLT_ACT_REG_ATF6_SIZE 2 ++/* Bit: 'ATF5' */ ++/* Description: 'Action for Type Filter 5' */ ++#define AR9_TP_FLT_ACT_REG_ATF5_OFFSET 0x00D4 ++#define AR9_TP_FLT_ACT_REG_ATF5_SHIFT 10 ++#define AR9_TP_FLT_ACT_REG_ATF5_SIZE 2 ++/* Bit: 'ATF4' */ ++/* Description: 'Action for Type Filter 4' */ ++#define AR9_TP_FLT_ACT_REG_ATF4_OFFSET 0x00D4 ++#define AR9_TP_FLT_ACT_REG_ATF4_SHIFT 8 ++#define AR9_TP_FLT_ACT_REG_ATF4_SIZE 2 ++/* Bit: 'ATF3' */ ++/* Description: 'Action for Type Filter 3' */ ++#define AR9_TP_FLT_ACT_REG_ATF3_OFFSET 0x00D4 ++#define AR9_TP_FLT_ACT_REG_ATF3_SHIFT 6 ++#define AR9_TP_FLT_ACT_REG_ATF3_SIZE 2 ++/* Bit: 'ATF2' */ ++/* Description: 'Action for Type Filter 2' */ ++#define AR9_TP_FLT_ACT_REG_ATF2_OFFSET 0x00D4 ++#define AR9_TP_FLT_ACT_REG_ATF2_SHIFT 4 ++#define AR9_TP_FLT_ACT_REG_ATF2_SIZE 2 ++/* Bit: 'ATF1' */ ++/* Description: 'Action for Type Filter 1' */ ++#define AR9_TP_FLT_ACT_REG_ATF1_OFFSET 0x00D4 ++#define AR9_TP_FLT_ACT_REG_ATF1_SHIFT 2 ++#define AR9_TP_FLT_ACT_REG_ATF1_SIZE 2 ++/* Bit: 'ATF0' */ ++/* Description: 'Action for Type Filter 0' */ ++#define AR9_TP_FLT_ACT_REG_ATF0_OFFSET 0x00D4 ++#define AR9_TP_FLT_ACT_REG_ATF0_SHIFT 0 ++#define AR9_TP_FLT_ACT_REG_ATF0_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Protocol Filter Action' */ ++/* Bit: 'APF7' */ ++/* Description: 'Action for Protocol Filter 7' */ ++#define AR9_PRTCL_FLT_ACT_REG_APF7_OFFSET 0x00D8 ++#define AR9_PRTCL_FLT_ACT_REG_APF7_SHIFT 14 ++#define AR9_PRTCL_FLT_ACT_REG_APF7_SIZE 2 ++/* Bit: 'APF6' */ ++/* Description: 'Action for Protocol Filter 6' */ ++#define AR9_PRTCL_FLT_ACT_REG_APF6_OFFSET 0x00D8 ++#define AR9_PRTCL_FLT_ACT_REG_APF6_SHIFT 12 ++#define AR9_PRTCL_FLT_ACT_REG_APF6_SIZE 2 ++/* Bit: 'APF5' */ ++/* Description: 'Action for Protocol Filter 5' */ ++#define AR9_PRTCL_FLT_ACT_REG_APF5_OFFSET 0x00D8 ++#define AR9_PRTCL_FLT_ACT_REG_APF5_SHIFT 10 ++#define AR9_PRTCL_FLT_ACT_REG_APF5_SIZE 2 ++/* Bit: 'APF4' */ ++/* Description: 'Action for Protocol Filter 4' */ ++#define AR9_PRTCL_FLT_ACT_REG_APF4_OFFSET 0x00D8 ++#define AR9_PRTCL_FLT_ACT_REG_APF4_SHIFT 8 ++#define AR9_PRTCL_FLT_ACT_REG_APF4_SIZE 2 ++/* Bit: 'APF3' */ ++/* Description: 'Action for Protocol Filter 3' */ ++#define AR9_PRTCL_FLT_ACT_REG_APF3_OFFSET 0x00D8 ++#define AR9_PRTCL_FLT_ACT_REG_APF3_SHIFT 6 ++#define AR9_PRTCL_FLT_ACT_REG_APF3_SIZE 2 ++/* Bit: 'APF2' */ ++/* Description: 'Action for Protocol Filter 2' */ ++#define AR9_PRTCL_FLT_ACT_REG_APF2_OFFSET 0x00D8 ++#define AR9_PRTCL_FLT_ACT_REG_APF2_SHIFT 4 ++#define AR9_PRTCL_FLT_ACT_REG_APF2_SIZE 2 ++/* Bit: 'APF1' */ ++/* Description: 'Action for Protocol Filter 1' */ ++#define AR9_PRTCL_FLT_ACT_REG_APF1_OFFSET 0x00D8 ++#define AR9_PRTCL_FLT_ACT_REG_APF1_SHIFT 2 ++#define AR9_PRTCL_FLT_ACT_REG_APF1_SIZE 2 ++/* Bit: 'APF0' */ ++/* Description: 'Action for Protocol Filter 0' */ ++#define AR9_PRTCL_FLT_ACT_REG_APF0_OFFSET 0x00D8 ++#define AR9_PRTCL_FLT_ACT_REG_APF0_SHIFT 0 ++#define AR9_PRTCL_FLT_ACT_REG_APF0_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 0' */ ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define AR9_VLAN_FLT0_REG_M_OFFSET 0x0100 ++#define AR9_VLAN_FLT0_REG_M_SHIFT 24 ++#define AR9_VLAN_FLT0_REG_M_SIZE 8 ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define AR9_VLAN_FLT0_REG_FID_OFFSET 0x0100 ++#define AR9_VLAN_FLT0_REG_FID_SHIFT 22 ++#define AR9_VLAN_FLT0_REG_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define AR9_VLAN_FLT0_REG_TM_OFFSET 0x0100 ++#define AR9_VLAN_FLT0_REG_TM_SHIFT 19 ++#define AR9_VLAN_FLT0_REG_TM_SIZE 3 ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define AR9_VLAN_FLT0_REG_VV_OFFSET 0x0100 ++#define AR9_VLAN_FLT0_REG_VV_SHIFT 15 ++#define AR9_VLAN_FLT0_REG_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define AR9_VLAN_FLT0_REG_VP_OFFSET 0x0100 ++#define AR9_VLAN_FLT0_REG_VP_SHIFT 12 ++#define AR9_VLAN_FLT0_REG_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define AR9_VLAN_FLT0_REG_VID_OFFSET 0x0100 ++#define AR9_VLAN_FLT0_REG_VID_SHIFT 0 ++#define AR9_VLAN_FLT0_REG_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 1' */ ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define AR9_VLAN_FLT1_REG_M_OFFSET 0x0104 ++#define AR9_VLAN_FLT1_REG_M_SHIFT 24 ++#define AR9_VLAN_FLT1_REG_M_SIZE 8 ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define AR9_VLAN_FLT1_REG_FID_OFFSET 0x0104 ++#define AR9_VLAN_FLT1_REG_FID_SHIFT 22 ++#define AR9_VLAN_FLT1_REG_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define AR9_VLAN_FLT1_REG_TM_OFFSET 0x0104 ++#define AR9_VLAN_FLT1_REG_TM_SHIFT 19 ++#define AR9_VLAN_FLT1_REG_TM_SIZE 3 ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define AR9_VLAN_FLT1_REG_VV_OFFSET 0x0104 ++#define AR9_VLAN_FLT1_REG_VV_SHIFT 15 ++#define AR9_VLAN_FLT1_REG_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define AR9_VLAN_FLT1_REG_VP_OFFSET 0x0104 ++#define AR9_VLAN_FLT1_REG_VP_SHIFT 12 ++#define AR9_VLAN_FLT1_REG_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define AR9_VLAN_FLT1_REG_VID_OFFSET 0x0104 ++#define AR9_VLAN_FLT1_REG_VID_SHIFT 0 ++#define AR9_VLAN_FLT1_REG_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 2' */ ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define AR9_VLAN_FLT2_REG_M_OFFSET 0x0108 ++#define AR9_VLAN_FLT2_REG_M_SHIFT 24 ++#define AR9_VLAN_FLT2_REG_M_SIZE 8 ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define AR9_VLAN_FLT2_REG_FID_OFFSET 0x0108 ++#define AR9_VLAN_FLT2_REG_FID_SHIFT 22 ++#define AR9_VLAN_FLT2_REG_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define AR9_VLAN_FLT2_REG_TM_OFFSET 0x0108 ++#define AR9_VLAN_FLT2_REG_TM_SHIFT 19 ++#define AR9_VLAN_FLT2_REG_TM_SIZE 3 ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define AR9_VLAN_FLT2_REG_VV_OFFSET 0x0108 ++#define AR9_VLAN_FLT2_REG_VV_SHIFT 15 ++#define AR9_VLAN_FLT2_REG_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define AR9_VLAN_FLT2_REG_VP_OFFSET 0x0108 ++#define AR9_VLAN_FLT2_REG_VP_SHIFT 12 ++#define AR9_VLAN_FLT2_REG_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define AR9_VLAN_FLT2_REG_VID_OFFSET 0x0108 ++#define AR9_VLAN_FLT2_REG_VID_SHIFT 0 ++#define AR9_VLAN_FLT2_REG_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 3' */ ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define AR9_VLAN_FLT3_REG_M_OFFSET 0x010C ++#define AR9_VLAN_FLT3_REG_M_SHIFT 24 ++#define AR9_VLAN_FLT3_REG_M_SIZE 8 ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define AR9_VLAN_FLT3_REG_FID_OFFSET 0x010C ++#define AR9_VLAN_FLT3_REG_FID_SHIFT 22 ++#define AR9_VLAN_FLT3_REG_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define AR9_VLAN_FLT3_REG_TM_OFFSET 0x010C ++#define AR9_VLAN_FLT3_REG_TM_SHIFT 19 ++#define AR9_VLAN_FLT3_REG_TM_SIZE 3 ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define AR9_VLAN_FLT3_REG_VV_OFFSET 0x010C ++#define AR9_VLAN_FLT3_REG_VV_SHIFT 15 ++#define AR9_VLAN_FLT3_REG_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define AR9_VLAN_FLT3_REG_VP_OFFSET 0x010C ++#define AR9_VLAN_FLT3_REG_VP_SHIFT 12 ++#define AR9_VLAN_FLT3_REG_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define AR9_VLAN_FLT3_REG_VID_OFFSET 0x010C ++#define AR9_VLAN_FLT3_REG_VID_SHIFT 0 ++#define AR9_VLAN_FLT3_REG_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 4' */ ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define AR9_VLAN_FLT4_REG_M_OFFSET 0x0110 ++#define AR9_VLAN_FLT4_REG_M_SHIFT 24 ++#define AR9_VLAN_FLT4_REG_M_SIZE 8 ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define AR9_VLAN_FLT4_REG_FID_OFFSET 0x0110 ++#define AR9_VLAN_FLT4_REG_FID_SHIFT 22 ++#define AR9_VLAN_FLT4_REG_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define AR9_VLAN_FLT4_REG_TM_OFFSET 0x0110 ++#define AR9_VLAN_FLT4_REG_TM_SHIFT 19 ++#define AR9_VLAN_FLT4_REG_TM_SIZE 3 ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define AR9_VLAN_FLT4_REG_VV_OFFSET 0x0110 ++#define AR9_VLAN_FLT4_REG_VV_SHIFT 15 ++#define AR9_VLAN_FLT4_REG_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define AR9_VLAN_FLT4_REG_VP_OFFSET 0x0110 ++#define AR9_VLAN_FLT4_REG_VP_SHIFT 12 ++#define AR9_VLAN_FLT4_REG_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define AR9_VLAN_FLT4_REG_VID_OFFSET 0x0110 ++#define AR9_VLAN_FLT4_REG_VID_SHIFT 0 ++#define AR9_VLAN_FLT4_REG_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 5' */ ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define AR9_VLAN_FLT5_REG_M_OFFSET 0x0114 ++#define AR9_VLAN_FLT5_REG_M_SHIFT 24 ++#define AR9_VLAN_FLT5_REG_M_SIZE 8 ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define AR9_VLAN_FLT5_REG_FID_OFFSET 0x0114 ++#define AR9_VLAN_FLT5_REG_FID_SHIFT 22 ++#define AR9_VLAN_FLT5_REG_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define AR9_VLAN_FLT5_REG_TM_OFFSET 0x0114 ++#define AR9_VLAN_FLT5_REG_TM_SHIFT 19 ++#define AR9_VLAN_FLT5_REG_TM_SIZE 3 ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define AR9_VLAN_FLT5_REG_VV_OFFSET 0x0114 ++#define AR9_VLAN_FLT5_REG_VV_SHIFT 15 ++#define AR9_VLAN_FLT5_REG_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define AR9_VLAN_FLT5_REG_VP_OFFSET 0x0114 ++#define AR9_VLAN_FLT5_REG_VP_SHIFT 12 ++#define AR9_VLAN_FLT5_REG_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define AR9_VLAN_FLT5_REG_VID_OFFSET 0x0114 ++#define AR9_VLAN_FLT5_REG_VID_SHIFT 0 ++#define AR9_VLAN_FLT5_REG_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 6' */ ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define AR9_VLAN_FLT6_REG_M_OFFSET 0x0118 ++#define AR9_VLAN_FLT6_REG_M_SHIFT 24 ++#define AR9_VLAN_FLT6_REG_M_SIZE 8 ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define AR9_VLAN_FLT6_REG_FID_OFFSET 0x0118 ++#define AR9_VLAN_FLT6_REG_FID_SHIFT 22 ++#define AR9_VLAN_FLT6_REG_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define AR9_VLAN_FLT6_REG_TM_OFFSET 0x0118 ++#define AR9_VLAN_FLT6_REG_TM_SHIFT 19 ++#define AR9_VLAN_FLT6_REG_TM_SIZE 3 ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define AR9_VLAN_FLT6_REG_VV_OFFSET 0x0118 ++#define AR9_VLAN_FLT6_REG_VV_SHIFT 15 ++#define AR9_VLAN_FLT6_REG_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define AR9_VLAN_FLT6_REG_VP_OFFSET 0x0118 ++#define AR9_VLAN_FLT6_REG_VP_SHIFT 12 ++#define AR9_VLAN_FLT6_REG_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define AR9_VLAN_FLT6_REG_VID_OFFSET 0x0118 ++#define AR9_VLAN_FLT6_REG_VID_SHIFT 0 ++#define AR9_VLAN_FLT6_REG_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 7' */ ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define AR9_VLAN_FLT7_REG_M_OFFSET 0x011C ++#define AR9_VLAN_FLT7_REG_M_SHIFT 24 ++#define AR9_VLAN_FLT7_REG_M_SIZE 8 ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define AR9_VLAN_FLT7_REG_FID_OFFSET 0x011C ++#define AR9_VLAN_FLT7_REG_FID_SHIFT 22 ++#define AR9_VLAN_FLT7_REG_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define AR9_VLAN_FLT7_REG_TM_OFFSET 0x011C ++#define AR9_VLAN_FLT7_REG_TM_SHIFT 19 ++#define AR9_VLAN_FLT7_REG_TM_SIZE 3 ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define AR9_VLAN_FLT7_REG_VV_OFFSET 0x011C ++#define AR9_VLAN_FLT7_REG_VV_SHIFT 15 ++#define AR9_VLAN_FLT7_REG_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define AR9_VLAN_FLT7_REG_VP_OFFSET 0x011C ++#define AR9_VLAN_FLT7_REG_VP_SHIFT 12 ++#define AR9_VLAN_FLT7_REG_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define AR9_VLAN_FLT7_REG_VID_OFFSET 0x011C ++#define AR9_VLAN_FLT7_REG_VID_SHIFT 0 ++#define AR9_VLAN_FLT7_REG_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 8' */ ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define AR9_VLAN_FLT8_REG_M_OFFSET 0x0120 ++#define AR9_VLAN_FLT8_REG_M_SHIFT 24 ++#define AR9_VLAN_FLT8_REG_M_SIZE 8 ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define AR9_VLAN_FLT8_REG_FID_OFFSET 0x0120 ++#define AR9_VLAN_FLT8_REG_FID_SHIFT 22 ++#define AR9_VLAN_FLT8_REG_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define AR9_VLAN_FLT8_REG_TM_OFFSET 0x0120 ++#define AR9_VLAN_FLT8_REG_TM_SHIFT 19 ++#define AR9_VLAN_FLT8_REG_TM_SIZE 3 ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define AR9_VLAN_FLT8_REG_VV_OFFSET 0x0120 ++#define AR9_VLAN_FLT8_REG_VV_SHIFT 15 ++#define AR9_VLAN_FLT8_REG_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define AR9_VLAN_FLT8_REG_VP_OFFSET 0x0120 ++#define AR9_VLAN_FLT8_REG_VP_SHIFT 12 ++#define AR9_VLAN_FLT8_REG_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define AR9_VLAN_FLT8_REG_VID_OFFSET 0x0120 ++#define AR9_VLAN_FLT8_REG_VID_SHIFT 0 ++#define AR9_VLAN_FLT8_REG_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 9' */ ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define AR9_VLAN_FLT9_REG_M_OFFSET 0x0124 ++#define AR9_VLAN_FLT9_REG_M_SHIFT 24 ++#define AR9_VLAN_FLT9_REG_M_SIZE 8 ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define AR9_VLAN_FLT9_REG_FID_OFFSET 0x0124 ++#define AR9_VLAN_FLT9_REG_FID_SHIFT 22 ++#define AR9_VLAN_FLT9_REG_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define AR9_VLAN_FLT9_REG_TM_OFFSET 0x0124 ++#define AR9_VLAN_FLT9_REG_TM_SHIFT 19 ++#define AR9_VLAN_FLT9_REG_TM_SIZE 3 ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define AR9_VLAN_FLT9_REG_VV_OFFSET 0x0124 ++#define AR9_VLAN_FLT9_REG_VV_SHIFT 15 ++#define AR9_VLAN_FLT9_REG_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define AR9_VLAN_FLT9_REG_VP_OFFSET 0x0124 ++#define AR9_VLAN_FLT9_REG_VP_SHIFT 12 ++#define AR9_VLAN_FLT9_REG_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define AR9_VLAN_FLT9_REG_VID_OFFSET 0x0124 ++#define AR9_VLAN_FLT9_REG_VID_SHIFT 0 ++#define AR9_VLAN_FLT9_REG_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 10' */ ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define AR9_VLAN_FLT10_REG_M_OFFSET 0x0128 ++#define AR9_VLAN_FLT10_REG_M_SHIFT 24 ++#define AR9_VLAN_FLT10_REG_M_SIZE 8 ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define AR9_VLAN_FLT10_REG_FID_OFFSET 0x0128 ++#define AR9_VLAN_FLT10_REG_FID_SHIFT 22 ++#define AR9_VLAN_FLT10_REG_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define AR9_VLAN_FLT10_REG_TM_OFFSET 0x0128 ++#define AR9_VLAN_FLT10_REG_TM_SHIFT 19 ++#define AR9_VLAN_FLT10_REG_TM_SIZE 3 ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define AR9_VLAN_FLT10_REG_VV_OFFSET 0x0128 ++#define AR9_VLAN_FLT10_REG_VV_SHIFT 15 ++#define AR9_VLAN_FLT10_REG_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define AR9_VLAN_FLT10_REG_VP_OFFSET 0x0128 ++#define AR9_VLAN_FLT10_REG_VP_SHIFT 12 ++#define AR9_VLAN_FLT10_REG_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define AR9_VLAN_FLT10_REG_VID_OFFSET 0x0128 ++#define AR9_VLAN_FLT10_REG_VID_SHIFT 0 ++#define AR9_VLAN_FLT10_REG_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 11' */ ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define AR9_VLAN_FLT11_REG_M_OFFSET 0x012C ++#define AR9_VLAN_FLT11_REG_M_SHIFT 24 ++#define AR9_VLAN_FLT11_REG_M_SIZE 8 ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define AR9_VLAN_FLT11_REG_FID_OFFSET 0x012C ++#define AR9_VLAN_FLT11_REG_FID_SHIFT 22 ++#define AR9_VLAN_FLT11_REG_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define AR9_VLAN_FLT11_REG_TM_OFFSET 0x012C ++#define AR9_VLAN_FLT11_REG_TM_SHIFT 19 ++#define AR9_VLAN_FLT11_REG_TM_SIZE 3 ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define AR9_VLAN_FLT11_REG_VV_OFFSET 0x012C ++#define AR9_VLAN_FLT11_REG_VV_SHIFT 15 ++#define AR9_VLAN_FLT11_REG_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define AR9_VLAN_FLT11_REG_VP_OFFSET 0x012C ++#define AR9_VLAN_FLT11_REG_VP_SHIFT 12 ++#define AR9_VLAN_FLT11_REG_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define AR9_VLAN_FLT11_REG_VID_OFFSET 0x012C ++#define AR9_VLAN_FLT11_REG_VID_SHIFT 0 ++#define AR9_VLAN_FLT11_REG_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 12' */ ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define AR9_VLAN_FLT12_REG_M_OFFSET 0x0130 ++#define AR9_VLAN_FLT12_REG_M_SHIFT 24 ++#define AR9_VLAN_FLT12_REG_M_SIZE 8 ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define AR9_VLAN_FLT12_REG_FID_OFFSET 0x0130 ++#define AR9_VLAN_FLT12_REG_FID_SHIFT 22 ++#define AR9_VLAN_FLT12_REG_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define AR9_VLAN_FLT12_REG_TM_OFFSET 0x0130 ++#define AR9_VLAN_FLT12_REG_TM_SHIFT 19 ++#define AR9_VLAN_FLT12_REG_TM_SIZE 3 ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define AR9_VLAN_FLT12_REG_VV_OFFSET 0x0130 ++#define AR9_VLAN_FLT12_REG_VV_SHIFT 15 ++#define AR9_VLAN_FLT12_REG_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define AR9_VLAN_FLT12_REG_VP_OFFSET 0x0130 ++#define AR9_VLAN_FLT12_REG_VP_SHIFT 12 ++#define AR9_VLAN_FLT12_REG_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define AR9_VLAN_FLT12_REG_VID_OFFSET 0x0130 ++#define AR9_VLAN_FLT12_REG_VID_SHIFT 0 ++#define AR9_VLAN_FLT12_REG_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 13' */ ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define AR9_VLAN_FLT13_REG_M_OFFSET 0x0134 ++#define AR9_VLAN_FLT13_REG_M_SHIFT 24 ++#define AR9_VLAN_FLT13_REG_M_SIZE 8 ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define AR9_VLAN_FLT13_REG_FID_OFFSET 0x0134 ++#define AR9_VLAN_FLT13_REG_FID_SHIFT 22 ++#define AR9_VLAN_FLT13_REG_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define AR9_VLAN_FLT13_REG_TM_OFFSET 0x0134 ++#define AR9_VLAN_FLT13_REG_TM_SHIFT 19 ++#define AR9_VLAN_FLT13_REG_TM_SIZE 3 ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define AR9_VLAN_FLT13_REG_VV_OFFSET 0x0134 ++#define AR9_VLAN_FLT13_REG_VV_SHIFT 15 ++#define AR9_VLAN_FLT13_REG_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define AR9_VLAN_FLT13_REG_VP_OFFSET 0x0134 ++#define AR9_VLAN_FLT13_REG_VP_SHIFT 12 ++#define AR9_VLAN_FLT13_REG_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define AR9_VLAN_FLT13_REG_VID_OFFSET 0x0134 ++#define AR9_VLAN_FLT13_REG_VID_SHIFT 0 ++#define AR9_VLAN_FLT13_REG_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 14' */ ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define AR9_VLAN_FLT14_REG_M_OFFSET 0x0138 ++#define AR9_VLAN_FLT14_REG_M_SHIFT 24 ++#define AR9_VLAN_FLT14_REG_M_SIZE 8 ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define AR9_VLAN_FLT14_REG_FID_OFFSET 0x0138 ++#define AR9_VLAN_FLT14_REG_FID_SHIFT 22 ++#define AR9_VLAN_FLT14_REG_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define AR9_VLAN_FLT14_REG_TM_OFFSET 0x0138 ++#define AR9_VLAN_FLT14_REG_TM_SHIFT 19 ++#define AR9_VLAN_FLT14_REG_TM_SIZE 3 ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define AR9_VLAN_FLT14_REG_VV_OFFSET 0x0138 ++#define AR9_VLAN_FLT14_REG_VV_SHIFT 15 ++#define AR9_VLAN_FLT14_REG_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define AR9_VLAN_FLT14_REG_VP_OFFSET 0x0138 ++#define AR9_VLAN_FLT14_REG_VP_SHIFT 12 ++#define AR9_VLAN_FLT14_REG_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define AR9_VLAN_FLT14_REG_VID_OFFSET 0x0138 ++#define AR9_VLAN_FLT14_REG_VID_SHIFT 0 ++#define AR9_VLAN_FLT14_REG_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 15' */ ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define AR9_VLAN_FLT15_REG_M_OFFSET 0x013C ++#define AR9_VLAN_FLT15_REG_M_SHIFT 24 ++#define AR9_VLAN_FLT15_REG_M_SIZE 8 ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define AR9_VLAN_FLT15_REG_FID_OFFSET 0x013C ++#define AR9_VLAN_FLT15_REG_FID_SHIFT 22 ++#define AR9_VLAN_FLT15_REG_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define AR9_VLAN_FLT15_REG_TM_OFFSET 0x013C ++#define AR9_VLAN_FLT15_REG_TM_SHIFT 19 ++#define AR9_VLAN_FLT15_REG_TM_SIZE 3 ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define AR9_VLAN_FLT15_REG_VV_OFFSET 0x013C ++#define AR9_VLAN_FLT15_REG_VV_SHIFT 15 ++#define AR9_VLAN_FLT15_REG_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define AR9_VLAN_FLT15_REG_VP_OFFSET 0x013C ++#define AR9_VLAN_FLT15_REG_VP_SHIFT 12 ++#define AR9_VLAN_FLT15_REG_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define AR9_VLAN_FLT15_REG_VID_OFFSET 0x013C ++#define AR9_VLAN_FLT15_REG_VID_SHIFT 0 ++#define AR9_VLAN_FLT15_REG_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Type Filter 10' */ ++/* Bit: 'VCET1' */ ++/* Description: 'Value 1 Compared with Ether-Type' */ ++#define AR9_TP_FLT10_REG_VCET1_OFFSET 0x0140 ++#define AR9_TP_FLT10_REG_VCET1_SHIFT 16 ++#define AR9_TP_FLT10_REG_VCET1_SIZE 16 ++/* Bit: 'VCET0' */ ++/* Description: 'Value 0 Compared with Ether-Type' */ ++#define AR9_TP_FLT10_REG_VCET0_OFFSET 0x0140 ++#define AR9_TP_FLT10_REG_VCET0_SHIFT 0 ++#define AR9_TP_FLT10_REG_VCET0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Type Filter 32' */ ++/* Bit: 'VCET1' */ ++/* Description: 'Value 1 Compared with Ether-Type' */ ++#define AR9_TP_FLT32_REG_VCET1_OFFSET 0x0144 ++#define AR9_TP_FLT32_REG_VCET1_SHIFT 16 ++#define AR9_TP_FLT32_REG_VCET1_SIZE 16 ++/* Bit: 'VCET0' */ ++/* Description: 'Value 0 Compared with Ether-Type' */ ++#define AR9_TP_FLT32_REG_VCET0_OFFSET 0x0144 ++#define AR9_TP_FLT32_REG_VCET0_SHIFT 0 ++#define AR9_TP_FLT32_REG_VCET0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Type Filter 54' */ ++/* Bit: 'VCET1' */ ++/* Description: 'Value 1 Compared with Ether-Type' */ ++#define AR9_TP_FLT54_REG_VCET1_OFFSET 0x0148 ++#define AR9_TP_FLT54_REG_VCET1_SHIFT 16 ++#define AR9_TP_FLT54_REG_VCET1_SIZE 16 ++/* Bit: 'VCET0' */ ++/* Description: 'Value 0 Compared with Ether-Type' */ ++#define AR9_TP_FLT54_REG_VCET0_OFFSET 0x0148 ++#define AR9_TP_FLT54_REG_VCET0_SHIFT 0 ++#define AR9_TP_FLT54_REG_VCET0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Type Filter 76' */ ++/* Bit: 'VCET1' */ ++/* Description: 'Value 1 Compared with Ether-Type' */ ++#define AR9_TP_FLT76_REG_VCET1_OFFSET 0x014C ++#define AR9_TP_FLT76_REG_VCET1_SHIFT 16 ++#define AR9_TP_FLT76_REG_VCET1_SIZE 16 ++/* Bit: 'VCET0' */ ++/* Description: 'Value 0 Compared with Ether-Type' */ ++#define AR9_TP_FLT76_REG_VCET0_OFFSET 0x014C ++#define AR9_TP_FLT76_REG_VCET0_SHIFT 0 ++#define AR9_TP_FLT76_REG_VCET0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'DiffServMapping 0' */ ++/* Bit: 'PQF' */ ++/* Description: 'Priority Queue F' */ ++#define AR9_DFSRV_MAP0_REG_PQF_OFFSET 0x0150 ++#define AR9_DFSRV_MAP0_REG_PQF_SHIFT 30 ++#define AR9_DFSRV_MAP0_REG_PQF_SIZE 2 ++/* Bit: 'PQE' */ ++/* Description: 'Priority Queue E' */ ++#define AR9_DFSRV_MAP0_REG_PQE_OFFSET 0x0150 ++#define AR9_DFSRV_MAP0_REG_PQE_SHIFT 28 ++#define AR9_DFSRV_MAP0_REG_PQE_SIZE 2 ++/* Bit: 'PQD' */ ++/* Description: 'Priority Queue D' */ ++#define AR9_DFSRV_MAP0_REG_PQD_OFFSET 0x0150 ++#define AR9_DFSRV_MAP0_REG_PQD_SHIFT 26 ++#define AR9_DFSRV_MAP0_REG_PQD_SIZE 2 ++/* Bit: 'PQC' */ ++/* Description: 'Priority Queue C' */ ++#define AR9_DFSRV_MAP0_REG_PQC_OFFSET 0x0150 ++#define AR9_DFSRV_MAP0_REG_PQC_SHIFT 24 ++#define AR9_DFSRV_MAP0_REG_PQC_SIZE 2 ++/* Bit: 'PQB' */ ++/* Description: 'Priority Queue B' */ ++#define AR9_DFSRV_MAP0_REG_PQB_OFFSET 0x0150 ++#define AR9_DFSRV_MAP0_REG_PQB_SHIFT 22 ++#define AR9_DFSRV_MAP0_REG_PQB_SIZE 2 ++/* Bit: 'PQA' */ ++/* Description: 'Priority Queue A' */ ++#define AR9_DFSRV_MAP0_REG_PQA_OFFSET 0x0150 ++#define AR9_DFSRV_MAP0_REG_PQA_SHIFT 20 ++#define AR9_DFSRV_MAP0_REG_PQA_SIZE 2 ++/* Bit: 'PQ9' */ ++/* Description: 'Priority Queue 9' */ ++#define AR9_DFSRV_MAP0_REG_PQ9_OFFSET 0x0150 ++#define AR9_DFSRV_MAP0_REG_PQ9_SHIFT 18 ++#define AR9_DFSRV_MAP0_REG_PQ9_SIZE 2 ++/* Bit: 'PQ8' */ ++/* Description: 'Priority Queue 8' */ ++#define AR9_DFSRV_MAP0_REG_PQ8_OFFSET 0x0150 ++#define AR9_DFSRV_MAP0_REG_PQ8_SHIFT 16 ++#define AR9_DFSRV_MAP0_REG_PQ8_SIZE 2 ++/* Bit: 'PQ7' */ ++/* Description: 'Priority Queue 7' */ ++#define AR9_DFSRV_MAP0_REG_PQ7_OFFSET 0x0150 ++#define AR9_DFSRV_MAP0_REG_PQ7_SHIFT 14 ++#define AR9_DFSRV_MAP0_REG_PQ7_SIZE 2 ++/* Bit: 'PQ6' */ ++/* Description: 'Priority Queue 6' */ ++#define AR9_DFSRV_MAP0_REG_PQ6_OFFSET 0x0150 ++#define AR9_DFSRV_MAP0_REG_PQ6_SHIFT 12 ++#define AR9_DFSRV_MAP0_REG_PQ6_SIZE 2 ++/* Bit: 'PQ5' */ ++/* Description: 'Priority Queue 5' */ ++#define AR9_DFSRV_MAP0_REG_PQ5_OFFSET 0x0150 ++#define AR9_DFSRV_MAP0_REG_PQ5_SHIFT 10 ++#define AR9_DFSRV_MAP0_REG_PQ5_SIZE 2 ++/* Bit: 'PQ4' */ ++/* Description: 'Priority Queue 4' */ ++#define AR9_DFSRV_MAP0_REG_PQ4_OFFSET 0x0150 ++#define AR9_DFSRV_MAP0_REG_PQ4_SHIFT 8 ++#define AR9_DFSRV_MAP0_REG_PQ4_SIZE 2 ++/* Bit: 'PQ3' */ ++/* Description: 'Priority Queue 3' */ ++#define AR9_DFSRV_MAP0_REG_PQ3_OFFSET 0x0150 ++#define AR9_DFSRV_MAP0_REG_PQ3_SHIFT 6 ++#define AR9_DFSRV_MAP0_REG_PQ3_SIZE 2 ++/* Bit: 'PQ2' */ ++/* Description: 'Priority Queue 2' */ ++#define AR9_DFSRV_MAP0_REG_PQ2_OFFSET 0x0150 ++#define AR9_DFSRV_MAP0_REG_PQ2_SHIFT 4 ++#define AR9_DFSRV_MAP0_REG_PQ2_SIZE 2 ++/* Bit: 'PQ1' */ ++/* Description: 'Priority Queue 1' */ ++#define AR9_DFSRV_MAP0_REG_PQ1_OFFSET 0x0150 ++#define AR9_DFSRV_MAP0_REG_PQ1_SHIFT 2 ++#define AR9_DFSRV_MAP0_REG_PQ1_SIZE 2 ++/* Bit: 'PQ0' */ ++/* Description: 'Priority Queue 0' */ ++#define AR9_DFSRV_MAP0_REG_PQ0_OFFSET 0x0150 ++#define AR9_DFSRV_MAP0_REG_PQ0_SHIFT 0 ++#define AR9_DFSRV_MAP0_REG_PQ0_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'DiffServMapping 1' */ ++/* Bit: 'PQ1F' */ ++/* Description: 'Priority Queue 1F' */ ++#define AR9_DFSRV_MAP1_REG_PQ1F_OFFSET 0x0154 ++#define AR9_DFSRV_MAP1_REG_PQ1F_SHIFT 30 ++#define AR9_DFSRV_MAP1_REG_PQ1F_SIZE 2 ++/* Bit: 'PQ1E' */ ++/* Description: 'Priority Queue 1E' */ ++#define AR9_DFSRV_MAP1_REG_PQ1E_OFFSET 0x0154 ++#define AR9_DFSRV_MAP1_REG_PQ1E_SHIFT 28 ++#define AR9_DFSRV_MAP1_REG_PQ1E_SIZE 2 ++/* Bit: 'PQ1D' */ ++/* Description: 'Priority Queue 1D' */ ++#define AR9_DFSRV_MAP1_REG_PQ1D_OFFSET 0x0154 ++#define AR9_DFSRV_MAP1_REG_PQ1D_SHIFT 26 ++#define AR9_DFSRV_MAP1_REG_PQ1D_SIZE 2 ++/* Bit: 'PQ1C' */ ++/* Description: 'Priority Queue 1C' */ ++#define AR9_DFSRV_MAP1_REG_PQ1C_OFFSET 0x0154 ++#define AR9_DFSRV_MAP1_REG_PQ1C_SHIFT 24 ++#define AR9_DFSRV_MAP1_REG_PQ1C_SIZE 2 ++/* Bit: 'PQ1B' */ ++/* Description: 'Priority Queue 1B' */ ++#define AR9_DFSRV_MAP1_REG_PQ1B_OFFSET 0x0154 ++#define AR9_DFSRV_MAP1_REG_PQ1B_SHIFT 22 ++#define AR9_DFSRV_MAP1_REG_PQ1B_SIZE 2 ++/* Bit: 'PQ1A' */ ++/* Description: 'Priority Queue 1A' */ ++#define AR9_DFSRV_MAP1_REG_PQ1A_OFFSET 0x0154 ++#define AR9_DFSRV_MAP1_REG_PQ1A_SHIFT 20 ++#define AR9_DFSRV_MAP1_REG_PQ1A_SIZE 2 ++/* Bit: 'PQ19' */ ++/* Description: 'Priority Queue 19' */ ++#define AR9_DFSRV_MAP1_REG_PQ19_OFFSET 0x0154 ++#define AR9_DFSRV_MAP1_REG_PQ19_SHIFT 18 ++#define AR9_DFSRV_MAP1_REG_PQ19_SIZE 2 ++/* Bit: 'PQ18' */ ++/* Description: 'Priority Queue 18' */ ++#define AR9_DFSRV_MAP1_REG_PQ18_OFFSET 0x0154 ++#define AR9_DFSRV_MAP1_REG_PQ18_SHIFT 16 ++#define AR9_DFSRV_MAP1_REG_PQ18_SIZE 2 ++/* Bit: 'PQ17' */ ++/* Description: 'Priority Queue 17' */ ++#define AR9_DFSRV_MAP1_REG_PQ17_OFFSET 0x0154 ++#define AR9_DFSRV_MAP1_REG_PQ17_SHIFT 14 ++#define AR9_DFSRV_MAP1_REG_PQ17_SIZE 2 ++/* Bit: 'PQ16' */ ++/* Description: 'Priority Queue 16' */ ++#define AR9_DFSRV_MAP1_REG_PQ16_OFFSET 0x0154 ++#define AR9_DFSRV_MAP1_REG_PQ16_SHIFT 12 ++#define AR9_DFSRV_MAP1_REG_PQ16_SIZE 2 ++/* Bit: 'PQ15' */ ++/* Description: 'Priority Queue 15' */ ++#define AR9_DFSRV_MAP1_REG_PQ15_OFFSET 0x0154 ++#define AR9_DFSRV_MAP1_REG_PQ15_SHIFT 10 ++#define AR9_DFSRV_MAP1_REG_PQ15_SIZE 2 ++/* Bit: 'PQ14' */ ++/* Description: 'Priority Queue 14' */ ++#define AR9_DFSRV_MAP1_REG_PQ14_OFFSET 0x0154 ++#define AR9_DFSRV_MAP1_REG_PQ14_SHIFT 8 ++#define AR9_DFSRV_MAP1_REG_PQ14_SIZE 2 ++/* Bit: 'PQ13' */ ++/* Description: 'Priority Queue 13' */ ++#define AR9_DFSRV_MAP1_REG_PQ13_OFFSET 0x0154 ++#define AR9_DFSRV_MAP1_REG_PQ13_SHIFT 6 ++#define AR9_DFSRV_MAP1_REG_PQ13_SIZE 2 ++/* Bit: 'PQ12' */ ++/* Description: 'Priority Queue 12' */ ++#define AR9_DFSRV_MAP1_REG_PQ12_OFFSET 0x0154 ++#define AR9_DFSRV_MAP1_REG_PQ12_SHIFT 4 ++#define AR9_DFSRV_MAP1_REG_PQ12_SIZE 2 ++/* Bit: 'PQ11' */ ++/* Description: 'Priority Queue 11' */ ++#define AR9_DFSRV_MAP1_REG_PQ11_OFFSET 0x0154 ++#define AR9_DFSRV_MAP1_REG_PQ11_SHIFT 2 ++#define AR9_DFSRV_MAP1_REG_PQ11_SIZE 2 ++/* Bit: 'PQ10' */ ++/* Description: 'Priority Queue 10' */ ++#define AR9_DFSRV_MAP1_REG_PQ10_OFFSET 0x0154 ++#define AR9_DFSRV_MAP1_REG_PQ10_SHIFT 0 ++#define AR9_DFSRV_MAP1_REG_PQ10_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'DiffServMapping 2' */ ++/* Bit: 'PQ2F' */ ++/* Description: 'Priority Queue 2F' */ ++#define AR9_DFSRV_MAP2_REG_PQ2F_OFFSET 0x0158 ++#define AR9_DFSRV_MAP2_REG_PQ2F_SHIFT 30 ++#define AR9_DFSRV_MAP2_REG_PQ2F_SIZE 2 ++/* Bit: 'PQ2E' */ ++/* Description: 'Priority Queue 2E' */ ++#define AR9_DFSRV_MAP2_REG_PQ2E_OFFSET 0x0158 ++#define AR9_DFSRV_MAP2_REG_PQ2E_SHIFT 28 ++#define AR9_DFSRV_MAP2_REG_PQ2E_SIZE 2 ++/* Bit: 'PQ2D' */ ++/* Description: 'Priority Queue 2D' */ ++#define AR9_DFSRV_MAP2_REG_PQ2D_OFFSET 0x0158 ++#define AR9_DFSRV_MAP2_REG_PQ2D_SHIFT 26 ++#define AR9_DFSRV_MAP2_REG_PQ2D_SIZE 2 ++/* Bit: 'PQ2C' */ ++/* Description: 'Priority Queue 2C' */ ++#define AR9_DFSRV_MAP2_REG_PQ2C_OFFSET 0x0158 ++#define AR9_DFSRV_MAP2_REG_PQ2C_SHIFT 24 ++#define AR9_DFSRV_MAP2_REG_PQ2C_SIZE 2 ++/* Bit: 'PQ2B' */ ++/* Description: 'Priority Queue 2B' */ ++#define AR9_DFSRV_MAP2_REG_PQ2B_OFFSET 0x0158 ++#define AR9_DFSRV_MAP2_REG_PQ2B_SHIFT 22 ++#define AR9_DFSRV_MAP2_REG_PQ2B_SIZE 2 ++/* Bit: 'PQ2A' */ ++/* Description: 'Priority Queue 2A' */ ++#define AR9_DFSRV_MAP2_REG_PQ2A_OFFSET 0x0158 ++#define AR9_DFSRV_MAP2_REG_PQ2A_SHIFT 20 ++#define AR9_DFSRV_MAP2_REG_PQ2A_SIZE 2 ++/* Bit: 'PQ29' */ ++/* Description: 'Priority Queue 29' */ ++#define AR9_DFSRV_MAP2_REG_PQ29_OFFSET 0x0158 ++#define AR9_DFSRV_MAP2_REG_PQ29_SHIFT 18 ++#define AR9_DFSRV_MAP2_REG_PQ29_SIZE 2 ++/* Bit: 'PQ28' */ ++/* Description: 'Priority Queue 28' */ ++#define AR9_DFSRV_MAP2_REG_PQ28_OFFSET 0x0158 ++#define AR9_DFSRV_MAP2_REG_PQ28_SHIFT 16 ++#define AR9_DFSRV_MAP2_REG_PQ28_SIZE 2 ++/* Bit: 'PQ27' */ ++/* Description: 'Priority Queue 27' */ ++#define AR9_DFSRV_MAP2_REG_PQ27_OFFSET 0x0158 ++#define AR9_DFSRV_MAP2_REG_PQ27_SHIFT 14 ++#define AR9_DFSRV_MAP2_REG_PQ27_SIZE 2 ++/* Bit: 'PQ26' */ ++/* Description: 'Priority Queue 26' */ ++#define AR9_DFSRV_MAP2_REG_PQ26_OFFSET 0x0158 ++#define AR9_DFSRV_MAP2_REG_PQ26_SHIFT 12 ++#define AR9_DFSRV_MAP2_REG_PQ26_SIZE 2 ++/* Bit: 'PQ25' */ ++/* Description: 'Priority Queue 25' */ ++#define AR9_DFSRV_MAP2_REG_PQ25_OFFSET 0x0158 ++#define AR9_DFSRV_MAP2_REG_PQ25_SHIFT 10 ++#define AR9_DFSRV_MAP2_REG_PQ25_SIZE 2 ++/* Bit: 'PQ24' */ ++/* Description: 'Priority Queue 24' */ ++#define AR9_DFSRV_MAP2_REG_PQ24_OFFSET 0x0158 ++#define AR9_DFSRV_MAP2_REG_PQ24_SHIFT 8 ++#define AR9_DFSRV_MAP2_REG_PQ24_SIZE 2 ++/* Bit: 'PQ23' */ ++/* Description: 'Priority Queue 23' */ ++#define AR9_DFSRV_MAP2_REG_PQ23_OFFSET 0x0158 ++#define AR9_DFSRV_MAP2_REG_PQ23_SHIFT 6 ++#define AR9_DFSRV_MAP2_REG_PQ23_SIZE 2 ++/* Bit: 'PQ22' */ ++/* Description: 'Priority Queue 22' */ ++#define AR9_DFSRV_MAP2_REG_PQ22_OFFSET 0x0158 ++#define AR9_DFSRV_MAP2_REG_PQ22_SHIFT 4 ++#define AR9_DFSRV_MAP2_REG_PQ22_SIZE 2 ++/* Bit: 'PQ21' */ ++/* Description: 'Priority Queue 21' */ ++#define AR9_DFSRV_MAP2_REG_PQ21_OFFSET 0x0158 ++#define AR9_DFSRV_MAP2_REG_PQ21_SHIFT 2 ++#define AR9_DFSRV_MAP2_REG_PQ21_SIZE 2 ++/* Bit: 'PQ20' */ ++/* Description: 'Priority Queue 20' */ ++#define AR9_DFSRV_MAP2_REG_PQ20_OFFSET 0x0158 ++#define AR9_DFSRV_MAP2_REG_PQ20_SHIFT 0 ++#define AR9_DFSRV_MAP2_REG_PQ20_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'DiffServMapping 3' */ ++/* Bit: 'PQ3F' */ ++/* Description: 'Priority Queue 3F' */ ++#define AR9_DFSRV_MAP3_REG_PQ3F_OFFSET 0x015C ++#define AR9_DFSRV_MAP3_REG_PQ3F_SHIFT 30 ++#define AR9_DFSRV_MAP3_REG_PQ3F_SIZE 2 ++/* Bit: 'PQ3E' */ ++/* Description: 'Priority Queue 3E' */ ++#define AR9_DFSRV_MAP3_REG_PQ3E_OFFSET 0x015C ++#define AR9_DFSRV_MAP3_REG_PQ3E_SHIFT 28 ++#define AR9_DFSRV_MAP3_REG_PQ3E_SIZE 2 ++/* Bit: 'PQ3D' */ ++/* Description: 'Priority Queue 3D' */ ++#define AR9_DFSRV_MAP3_REG_PQ3D_OFFSET 0x015C ++#define AR9_DFSRV_MAP3_REG_PQ3D_SHIFT 26 ++#define AR9_DFSRV_MAP3_REG_PQ3D_SIZE 2 ++/* Bit: 'PQ3C' */ ++/* Description: 'Priority Queue 3C' */ ++#define AR9_DFSRV_MAP3_REG_PQ3C_OFFSET 0x015C ++#define AR9_DFSRV_MAP3_REG_PQ3C_SHIFT 24 ++#define AR9_DFSRV_MAP3_REG_PQ3C_SIZE 2 ++/* Bit: 'PQ3B' */ ++/* Description: 'Priority Queue 3B' */ ++#define AR9_DFSRV_MAP3_REG_PQ3B_OFFSET 0x015C ++#define AR9_DFSRV_MAP3_REG_PQ3B_SHIFT 22 ++#define AR9_DFSRV_MAP3_REG_PQ3B_SIZE 2 ++/* Bit: 'PQ3A' */ ++/* Description: 'Priority Queue 3A' */ ++#define AR9_DFSRV_MAP3_REG_PQ3A_OFFSET 0x015C ++#define AR9_DFSRV_MAP3_REG_PQ3A_SHIFT 20 ++#define AR9_DFSRV_MAP3_REG_PQ3A_SIZE 2 ++/* Bit: 'PQ39' */ ++/* Description: 'Priority Queue 39' */ ++#define AR9_DFSRV_MAP3_REG_PQ39_OFFSET 0x015C ++#define AR9_DFSRV_MAP3_REG_PQ39_SHIFT 18 ++#define AR9_DFSRV_MAP3_REG_PQ39_SIZE 2 ++/* Bit: 'PQ38' */ ++/* Description: 'Priority Queue 38' */ ++#define AR9_DFSRV_MAP3_REG_PQ38_OFFSET 0x015C ++#define AR9_DFSRV_MAP3_REG_PQ38_SHIFT 16 ++#define AR9_DFSRV_MAP3_REG_PQ38_SIZE 2 ++/* Bit: 'PQ37' */ ++/* Description: 'Priority Queue 37' */ ++#define AR9_DFSRV_MAP3_REG_PQ37_OFFSET 0x015C ++#define AR9_DFSRV_MAP3_REG_PQ37_SHIFT 14 ++#define AR9_DFSRV_MAP3_REG_PQ37_SIZE 2 ++/* Bit: 'PQ36' */ ++/* Description: 'Priority Queue 36' */ ++#define AR9_DFSRV_MAP3_REG_PQ36_OFFSET 0x015C ++#define AR9_DFSRV_MAP3_REG_PQ36_SHIFT 12 ++#define AR9_DFSRV_MAP3_REG_PQ36_SIZE 2 ++/* Bit: 'PQ35' */ ++/* Description: 'Priority Queue 35' */ ++#define AR9_DFSRV_MAP3_REG_PQ35_OFFSET 0x015C ++#define AR9_DFSRV_MAP3_REG_PQ35_SHIFT 10 ++#define AR9_DFSRV_MAP3_REG_PQ35_SIZE 2 ++/* Bit: 'PQ34' */ ++/* Description: 'Priority Queue 34' */ ++#define AR9_DFSRV_MAP3_REG_PQ34_OFFSET 0x015C ++#define AR9_DFSRV_MAP3_REG_PQ34_SHIFT 8 ++#define AR9_DFSRV_MAP3_REG_PQ34_SIZE 2 ++/* Bit: 'PQ33' */ ++/* Description: 'Priority Queue 33' */ ++#define AR9_DFSRV_MAP3_REG_PQ33_OFFSET 0x015C ++#define AR9_DFSRV_MAP3_REG_PQ33_SHIFT 6 ++#define AR9_DFSRV_MAP3_REG_PQ33_SIZE 2 ++/* Bit: 'PQ32' */ ++/* Description: 'Priority Queue 32' */ ++#define AR9_DFSRV_MAP3_REG_PQ32_OFFSET 0x015C ++#define AR9_DFSRV_MAP3_REG_PQ32_SHIFT 4 ++#define AR9_DFSRV_MAP3_REG_PQ32_SIZE 2 ++/* Bit: 'PQ31' */ ++/* Description: 'Priority Queue 31' */ ++#define AR9_DFSRV_MAP3_REG_PQ31_OFFSET 0x015C ++#define AR9_DFSRV_MAP3_REG_PQ31_SHIFT 2 ++#define AR9_DFSRV_MAP3_REG_PQ31_SIZE 2 ++/* Bit: 'PQ30' */ ++/* Description: 'Priority Queue 30' */ ++#define AR9_DFSRV_MAP3_REG_PQ30_OFFSET 0x015C ++#define AR9_DFSRV_MAP3_REG_PQ30_SHIFT 0 ++#define AR9_DFSRV_MAP3_REG_PQ30_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Filter 0' */ ++/* Bit: 'ATUF0' */ ++/* Description: 'Action for TCP/UDP Port Filter 0' */ ++#define AR9_TCP_PF0_REG_ATUF0_OFFSET 0x0160 ++#define AR9_TCP_PF0_REG_ATUF0_SHIFT 28 ++#define AR9_TCP_PF0_REG_ATUF0_SIZE 2 ++/* Bit: 'TUPF0' */ ++/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 0' */ ++#define AR9_TCP_PF0_REG_TUPF0_OFFSET 0x0160 ++#define AR9_TCP_PF0_REG_TUPF0_SHIFT 26 ++#define AR9_TCP_PF0_REG_TUPF0_SIZE 2 ++/* Bit: 'COMP0' */ ++/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ ++#define AR9_TCP_PF0_REG_COMP0_OFFSET 0x0160 ++#define AR9_TCP_PF0_REG_COMP0_SHIFT 24 ++#define AR9_TCP_PF0_REG_COMP0_SIZE 2 ++/* Bit: 'PRANGE0' */ ++/* Description: 'Port Range in TCP/UDP' */ ++#define AR9_TCP_PF0_REG_PRANGE0_OFFSET 0x0160 ++#define AR9_TCP_PF0_REG_PRANGE0_SHIFT 16 ++#define AR9_TCP_PF0_REG_PRANGE0_SIZE 8 ++/* Bit: 'BASEPT0' */ ++/* Description: 'Base Port number 0' */ ++#define AR9_TCP_PF0_REG_BASEPT0_OFFSET 0x0160 ++#define AR9_TCP_PF0_REG_BASEPT0_SHIFT 0 ++#define AR9_TCP_PF0_REG_BASEPT0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Filter 1' */ ++/* Bit: 'ATUF1' */ ++/* Description: 'Action for TCP/UDP Port Filter 1' */ ++#define AR9_TCP_PF1_REG_ATUF1_OFFSET 0x0164 ++#define AR9_TCP_PF1_REG_ATUF1_SHIFT 28 ++#define AR9_TCP_PF1_REG_ATUF1_SIZE 2 ++/* Bit: 'TUPF1' */ ++/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 1' */ ++#define AR9_TCP_PF1_REG_TUPF1_OFFSET 0x0164 ++#define AR9_TCP_PF1_REG_TUPF1_SHIFT 26 ++#define AR9_TCP_PF1_REG_TUPF1_SIZE 2 ++/* Bit: 'COMP1' */ ++/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ ++#define AR9_TCP_PF1_REG_COMP1_OFFSET 0x0164 ++#define AR9_TCP_PF1_REG_COMP1_SHIFT 24 ++#define AR9_TCP_PF1_REG_COMP1_SIZE 2 ++/* Bit: 'PRANGE1' */ ++/* Description: 'Port Range in TCP/UDP' */ ++#define AR9_TCP_PF1_REG_PRANGE1_OFFSET 0x0164 ++#define AR9_TCP_PF1_REG_PRANGE1_SHIFT 16 ++#define AR9_TCP_PF1_REG_PRANGE1_SIZE 8 ++/* Bit: 'BASEPT1' */ ++/* Description: 'Base Port number 1' */ ++#define AR9_TCP_PF1_REG_BASEPT1_OFFSET 0x0164 ++#define AR9_TCP_PF1_REG_BASEPT1_SHIFT 0 ++#define AR9_TCP_PF1_REG_BASEPT1_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Filter 2' */ ++/* Bit: 'ATUF2' */ ++/* Description: 'Action for TCP/UDP Port Filter 2' */ ++#define AR9_TCP_PF2_REG_ATUF2_OFFSET 0x0168 ++#define AR9_TCP_PF2_REG_ATUF2_SHIFT 28 ++#define AR9_TCP_PF2_REG_ATUF2_SIZE 2 ++/* Bit: 'TUPF2' */ ++/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 2' */ ++#define AR9_TCP_PF2_REG_TUPF2_OFFSET 0x0168 ++#define AR9_TCP_PF2_REG_TUPF2_SHIFT 26 ++#define AR9_TCP_PF2_REG_TUPF2_SIZE 2 ++/* Bit: 'COMP2' */ ++/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ ++#define AR9_TCP_PF2_REG_COMP2_OFFSET 0x0168 ++#define AR9_TCP_PF2_REG_COMP2_SHIFT 24 ++#define AR9_TCP_PF2_REG_COMP2_SIZE 2 ++/* Bit: 'PRANGE2' */ ++/* Description: 'Port Range in TCP/UDP' */ ++#define AR9_TCP_PF2_REG_PRANGE2_OFFSET 0x0168 ++#define AR9_TCP_PF2_REG_PRANGE2_SHIFT 16 ++#define AR9_TCP_PF2_REG_PRANGE2_SIZE 8 ++/* Bit: 'BASEPT2' */ ++/* Description: 'Base Port number 2' */ ++#define AR9_TCP_PF2_REG_BASEPT2_OFFSET 0x0168 ++#define AR9_TCP_PF2_REG_BASEPT2_SHIFT 0 ++#define AR9_TCP_PF2_REG_BASEPT2_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Filter 3' */ ++/* Bit: 'ATUF3' */ ++/* Description: 'Action for TCP/UDP Port Filter 3' */ ++#define AR9_TCP_PF3_REG_ATUF3_OFFSET 0x016C ++#define AR9_TCP_PF3_REG_ATUF3_SHIFT 28 ++#define AR9_TCP_PF3_REG_ATUF3_SIZE 2 ++/* Bit: 'TUPF3' */ ++/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 3' */ ++#define AR9_TCP_PF3_REG_TUPF3_OFFSET 0x016C ++#define AR9_TCP_PF3_REG_TUPF3_SHIFT 26 ++#define AR9_TCP_PF3_REG_TUPF3_SIZE 2 ++/* Bit: 'COMP3' */ ++/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ ++#define AR9_TCP_PF3_REG_COMP3_OFFSET 0x016C ++#define AR9_TCP_PF3_REG_COMP3_SHIFT 24 ++#define AR9_TCP_PF3_REG_COMP3_SIZE 2 ++/* Bit: 'PRANGE3' */ ++/* Description: 'Port Range in TCP/UDP' */ ++#define AR9_TCP_PF3_REG_PRANGE3_OFFSET 0x016C ++#define AR9_TCP_PF3_REG_PRANGE3_SHIFT 16 ++#define AR9_TCP_PF3_REG_PRANGE3_SIZE 8 ++/* Bit: 'BASEPT3' */ ++/* Description: 'Base Port number 3' */ ++#define AR9_TCP_PF3_REG_BASEPT3_OFFSET 0x016C ++#define AR9_TCP_PF3_REG_BASEPT3_SHIFT 0 ++#define AR9_TCP_PF3_REG_BASEPT3_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Filter 4' */ ++/* Bit: 'ATUF4' */ ++/* Description: 'Action for TCP/UDP Port Filter 4' */ ++#define AR9_TCP_PF4_REG_ATUF4_OFFSET 0x0170 ++#define AR9_TCP_PF4_REG_ATUF4_SHIFT 28 ++#define AR9_TCP_PF4_REG_ATUF4_SIZE 2 ++/* Bit: 'TUPF4' */ ++/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 4' */ ++#define AR9_TCP_PF4_REG_TUPF4_OFFSET 0x0170 ++#define AR9_TCP_PF4_REG_TUPF4_SHIFT 26 ++#define AR9_TCP_PF4_REG_TUPF4_SIZE 2 ++/* Bit: 'COMP4' */ ++/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ ++#define AR9_TCP_PF4_REG_COMP4_OFFSET 0x0170 ++#define AR9_TCP_PF4_REG_COMP4_SHIFT 24 ++#define AR9_TCP_PF4_REG_COMP4_SIZE 2 ++/* Bit: 'PRANGE4' */ ++/* Description: 'Port Range in TCP/UDP' */ ++#define AR9_TCP_PF4_REG_PRANGE4_OFFSET 0x0170 ++#define AR9_TCP_PF4_REG_PRANGE4_SHIFT 16 ++#define AR9_TCP_PF4_REG_PRANGE4_SIZE 8 ++/* Bit: 'BASEPT4' */ ++/* Description: 'Base Port number 4' */ ++#define AR9_TCP_PF4_REG_BASEPT4_OFFSET 0x0170 ++#define AR9_TCP_PF4_REG_BASEPT4_SHIFT 0 ++#define AR9_TCP_PF4_REG_BASEPT4_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Filter 5' */ ++/* Bit: 'ATUF5' */ ++/* Description: 'Action for TCP/UDP Port Filter 5' */ ++#define AR9_TCP_PF5_REG_ATUF5_OFFSET 0x0174 ++#define AR9_TCP_PF5_REG_ATUF5_SHIFT 28 ++#define AR9_TCP_PF5_REG_ATUF5_SIZE 2 ++/* Bit: 'TUPF5' */ ++/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 5' */ ++#define AR9_TCP_PF5_REG_TUPF5_OFFSET 0x0174 ++#define AR9_TCP_PF5_REG_TUPF5_SHIFT 26 ++#define AR9_TCP_PF5_REG_TUPF5_SIZE 2 ++/* Bit: 'COMP5' */ ++/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ ++#define AR9_TCP_PF5_REG_COMP5_OFFSET 0x0174 ++#define AR9_TCP_PF5_REG_COMP5_SHIFT 24 ++#define AR9_TCP_PF5_REG_COMP5_SIZE 2 ++/* Bit: 'PRANGE5' */ ++/* Description: 'Port Range in TCP/UDP' */ ++#define AR9_TCP_PF5_REG_PRANGE5_OFFSET 0x0174 ++#define AR9_TCP_PF5_REG_PRANGE5_SHIFT 16 ++#define AR9_TCP_PF5_REG_PRANGE5_SIZE 8 ++/* Bit: 'BASEPT5' */ ++/* Description: 'Base Port number 5' */ ++#define AR9_TCP_PF5_REG_BASEPT5_OFFSET 0x0174 ++#define AR9_TCP_PF5_REG_BASEPT5_SHIFT 0 ++#define AR9_TCP_PF5_REG_BASEPT5_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Filter 6' */ ++/* Bit: 'ATUF6' */ ++/* Description: 'Action for TCP/UDP Port Filter 6' */ ++#define AR9_TCP_PF6_REG_ATUF6_OFFSET 0x0178 ++#define AR9_TCP_PF6_REG_ATUF6_SHIFT 28 ++#define AR9_TCP_PF6_REG_ATUF6_SIZE 2 ++/* Bit: 'TUPF6' */ ++/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 6' */ ++#define AR9_TCP_PF6_REG_TUPF6_OFFSET 0x0178 ++#define AR9_TCP_PF6_REG_TUPF6_SHIFT 26 ++#define AR9_TCP_PF6_REG_TUPF6_SIZE 2 ++/* Bit: 'COMP6' */ ++/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ ++#define AR9_TCP_PF6_REG_COMP6_OFFSET 0x0178 ++#define AR9_TCP_PF6_REG_COMP6_SHIFT 24 ++#define AR9_TCP_PF6_REG_COMP6_SIZE 2 ++/* Bit: 'PRANGE6' */ ++/* Description: 'Port Range in TCP/UDP' */ ++#define AR9_TCP_PF6_REG_PRANGE6_OFFSET 0x0178 ++#define AR9_TCP_PF6_REG_PRANGE6_SHIFT 16 ++#define AR9_TCP_PF6_REG_PRANGE6_SIZE 8 ++/* Bit: 'BASEPT6' */ ++/* Description: 'Base Port number 6' */ ++#define AR9_TCP_PF6_REG_BASEPT6_OFFSET 0x0178 ++#define AR9_TCP_PF6_REG_BASEPT6_SHIFT 0 ++#define AR9_TCP_PF6_REG_BASEPT6_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Filter 7' */ ++/* Bit: 'ATUF7' */ ++/* Description: 'Action for TCP/UDP Port Filter 7' */ ++#define AR9_TCP_PF7_REG_ATUF7_OFFSET 0x017C ++#define AR9_TCP_PF7_REG_ATUF7_SHIFT 28 ++#define AR9_TCP_PF7_REG_ATUF7_SIZE 2 ++/* Bit: 'TUPF7' */ ++/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 7' */ ++#define AR9_TCP_PF7_REG_TUPF7_OFFSET 0x017C ++#define AR9_TCP_PF7_REG_TUPF7_SHIFT 26 ++#define AR9_TCP_PF7_REG_TUPF7_SIZE 2 ++/* Bit: 'COMP7' */ ++/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ ++#define AR9_TCP_PF7_REG_COMP7_OFFSET 0x017C ++#define AR9_TCP_PF7_REG_COMP7_SHIFT 24 ++#define AR9_TCP_PF7_REG_COMP7_SIZE 2 ++/* Bit: 'PRANGE7' */ ++/* Description: 'Port Range in TCP/UDP' */ ++#define AR9_TCP_PF7_REG_PRANGE7_OFFSET 0x017C ++#define AR9_TCP_PF7_REG_PRANGE7_SHIFT 16 ++#define AR9_TCP_PF7_REG_PRANGE7_SIZE 8 ++/* Bit: 'BASEPT7' */ ++/* Description: 'Base Port number 7' */ ++#define AR9_TCP_PF7_REG_BASEPT7_OFFSET 0x017C ++#define AR9_TCP_PF7_REG_BASEPT7_SHIFT 0 ++#define AR9_TCP_PF7_REG_BASEPT7_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserved DA(0180C2000003~0180C2000000) control register' */ ++/* Bit: 'RA03_VALID' */ ++/* Description: 'Valid bit for 0180C2000003' */ ++#define AR9_RA_03_00_REG_RA03_VALID_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA03_VALID_SHIFT 31 ++#define AR9_RA_03_00_REG_RA03_VALID_SIZE 1 ++/* Bit: 'RA03_SPAN' */ ++/* Description: 'Span bit for 0180C2000003' */ ++#define AR9_RA_03_00_REG_RA03_SPAN_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA03_SPAN_SHIFT 30 ++#define AR9_RA_03_00_REG_RA03_SPAN_SIZE 1 ++/* Bit: 'RA03_MG' */ ++/* Description: 'Management bit for 0180C2000003' */ ++#define AR9_RA_03_00_REG_RA03_MG_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA03_MG_SHIFT 29 ++#define AR9_RA_03_00_REG_RA03_MG_SIZE 1 ++/* Bit: 'RA03_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000003' */ ++#define AR9_RA_03_00_REG_RA03_CV_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA03_CV_SHIFT 28 ++#define AR9_RA_03_00_REG_RA03_CV_SIZE 1 ++/* Bit: 'RA03_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000003' */ ++#define AR9_RA_03_00_REG_RA03_TXTAG_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA03_TXTAG_SHIFT 26 ++#define AR9_RA_03_00_REG_RA03_TXTAG_SIZE 2 ++/* Bit: 'RA03_ACT' */ ++/* Description: 'Action bit for 0180C2000003' */ ++#define AR9_RA_03_00_REG_RA03_ACT_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA03_ACT_SHIFT 24 ++#define AR9_RA_03_00_REG_RA03_ACT_SIZE 2 ++/* Bit: 'RA02_VALID' */ ++/* Description: 'Valid bit for 0180C2000002' */ ++#define AR9_RA_03_00_REG_RA02_VALID_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA02_VALID_SHIFT 23 ++#define AR9_RA_03_00_REG_RA02_VALID_SIZE 1 ++/* Bit: 'RA02_SPAN' */ ++/* Description: 'Span bit for 0180C2000002' */ ++#define AR9_RA_03_00_REG_RA02_SPAN_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA02_SPAN_SHIFT 22 ++#define AR9_RA_03_00_REG_RA02_SPAN_SIZE 1 ++/* Bit: 'RA02_MG' */ ++/* Description: 'Management bit for 0180C2000002' */ ++#define AR9_RA_03_00_REG_RA02_MG_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA02_MG_SHIFT 21 ++#define AR9_RA_03_00_REG_RA02_MG_SIZE 1 ++/* Bit: 'RA02_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000002' */ ++#define AR9_RA_03_00_REG_RA02_CV_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA02_CV_SHIFT 20 ++#define AR9_RA_03_00_REG_RA02_CV_SIZE 1 ++/* Bit: 'RA02_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000002' */ ++#define AR9_RA_03_00_REG_RA02_TXTAG_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA02_TXTAG_SHIFT 18 ++#define AR9_RA_03_00_REG_RA02_TXTAG_SIZE 2 ++/* Bit: 'RA02_ACT' */ ++/* Description: 'Action bit for 0180C2000002' */ ++#define AR9_RA_03_00_REG_RA02_ACT_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA02_ACT_SHIFT 16 ++#define AR9_RA_03_00_REG_RA02_ACT_SIZE 2 ++/* Bit: 'RA01_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define AR9_RA_03_00_REG_RA01_VALID_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA01_VALID_SHIFT 15 ++#define AR9_RA_03_00_REG_RA01_VALID_SIZE 1 ++/* Bit: 'RA01_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define AR9_RA_03_00_REG_RA01_SPAN_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA01_SPAN_SHIFT 14 ++#define AR9_RA_03_00_REG_RA01_SPAN_SIZE 1 ++/* Bit: 'RA01_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define AR9_RA_03_00_REG_RA01_MG_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA01_MG_SHIFT 13 ++#define AR9_RA_03_00_REG_RA01_MG_SIZE 1 ++/* Bit: 'RA01_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define AR9_RA_03_00_REG_RA01_CV_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA01_CV_SHIFT 12 ++#define AR9_RA_03_00_REG_RA01_CV_SIZE 1 ++/* Bit: 'RA01_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define AR9_RA_03_00_REG_RA01_TXTAG_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA01_TXTAG_SHIFT 10 ++#define AR9_RA_03_00_REG_RA01_TXTAG_SIZE 2 ++/* Bit: 'RA01_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define AR9_RA_03_00_REG_RA01_ACT_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA01_ACT_SHIFT 8 ++#define AR9_RA_03_00_REG_RA01_ACT_SIZE 2 ++/* Bit: 'RA00_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define AR9_RA_03_00_REG_RA00_VALID_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA00_VALID_SHIFT 7 ++#define AR9_RA_03_00_REG_RA00_VALID_SIZE 1 ++/* Bit: 'RA00_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define AR9_RA_03_00_REG_RA00_SPAN_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA00_SPAN_SHIFT 6 ++#define AR9_RA_03_00_REG_RA00_SPAN_SIZE 1 ++/* Bit: 'RA00_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define AR9_RA_03_00_REG_RA00_MG_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA00_MG_SHIFT 5 ++#define AR9_RA_03_00_REG_RA00_MG_SIZE 1 ++/* Bit: 'RA00_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define AR9_RA_03_00_REG_RA00_CV_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA00_CV_SHIFT 4 ++#define AR9_RA_03_00_REG_RA00_CV_SIZE 1 ++/* Bit: 'RA00_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define AR9_RA_03_00_REG_RA00_TXTAG_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA00_TXTAG_SHIFT 2 ++#define AR9_RA_03_00_REG_RA00_TXTAG_SIZE 2 ++/* Bit: 'RA00_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define AR9_RA_03_00_REG_RA00_ACT_OFFSET 0x0180 ++#define AR9_RA_03_00_REG_RA00_ACT_SHIFT 0 ++#define AR9_RA_03_00_REG_RA00_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C2000007~0180C2000004' */ ++/* Bit: 'RA13_VALID' */ ++/* Description: 'Valid bit for 0180C2000003' */ ++#define AR9_RA_07_04_REG_RA13_VALID_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA13_VALID_SHIFT 31 ++#define AR9_RA_07_04_REG_RA13_VALID_SIZE 1 ++/* Bit: 'RA13_SPAN' */ ++/* Description: 'Span bit for 0180C2000003' */ ++#define AR9_RA_07_04_REG_RA13_SPAN_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA13_SPAN_SHIFT 30 ++#define AR9_RA_07_04_REG_RA13_SPAN_SIZE 1 ++/* Bit: 'RA13_MG' */ ++/* Description: 'Management bit for 0180C2000003' */ ++#define AR9_RA_07_04_REG_RA13_MG_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA13_MG_SHIFT 29 ++#define AR9_RA_07_04_REG_RA13_MG_SIZE 1 ++/* Bit: 'RA13_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000003' */ ++#define AR9_RA_07_04_REG_RA13_CV_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA13_CV_SHIFT 28 ++#define AR9_RA_07_04_REG_RA13_CV_SIZE 1 ++/* Bit: 'RA13_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000003' */ ++#define AR9_RA_07_04_REG_RA13_TXTAG_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA13_TXTAG_SHIFT 26 ++#define AR9_RA_07_04_REG_RA13_TXTAG_SIZE 2 ++/* Bit: 'RA13_ACT' */ ++/* Description: 'Action bit for 0180C2000003' */ ++#define AR9_RA_07_04_REG_RA13_ACT_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA13_ACT_SHIFT 24 ++#define AR9_RA_07_04_REG_RA13_ACT_SIZE 2 ++/* Bit: 'RA12_VALID' */ ++/* Description: 'Valid bit for 0180C2000002' */ ++#define AR9_RA_07_04_REG_RA12_VALID_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA12_VALID_SHIFT 23 ++#define AR9_RA_07_04_REG_RA12_VALID_SIZE 1 ++/* Bit: 'RA12_SPAN' */ ++/* Description: 'Span bit for 0180C2000002' */ ++#define AR9_RA_07_04_REG_RA12_SPAN_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA12_SPAN_SHIFT 22 ++#define AR9_RA_07_04_REG_RA12_SPAN_SIZE 1 ++/* Bit: 'RA12_MG' */ ++/* Description: 'Management bit for 0180C2000002' */ ++#define AR9_RA_07_04_REG_RA12_MG_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA12_MG_SHIFT 21 ++#define AR9_RA_07_04_REG_RA12_MG_SIZE 1 ++/* Bit: 'RA12_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000002' */ ++#define AR9_RA_07_04_REG_RA12_CV_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA12_CV_SHIFT 20 ++#define AR9_RA_07_04_REG_RA12_CV_SIZE 1 ++/* Bit: 'RA12_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000002' */ ++#define AR9_RA_07_04_REG_RA12_TXTAG_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA12_TXTAG_SHIFT 18 ++#define AR9_RA_07_04_REG_RA12_TXTAG_SIZE 2 ++/* Bit: 'RA12_ACT' */ ++/* Description: 'Action bit for 0180C2000002' */ ++#define AR9_RA_07_04_REG_RA12_ACT_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA12_ACT_SHIFT 16 ++#define AR9_RA_07_04_REG_RA12_ACT_SIZE 2 ++/* Bit: 'RA11_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define AR9_RA_07_04_REG_RA11_VALID_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA11_VALID_SHIFT 15 ++#define AR9_RA_07_04_REG_RA11_VALID_SIZE 1 ++/* Bit: 'RA11_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define AR9_RA_07_04_REG_RA11_SPAN_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA11_SPAN_SHIFT 14 ++#define AR9_RA_07_04_REG_RA11_SPAN_SIZE 1 ++/* Bit: 'RA11_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define AR9_RA_07_04_REG_RA11_MG_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA11_MG_SHIFT 13 ++#define AR9_RA_07_04_REG_RA11_MG_SIZE 1 ++/* Bit: 'RA11_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define AR9_RA_07_04_REG_RA11_CV_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA11_CV_SHIFT 12 ++#define AR9_RA_07_04_REG_RA11_CV_SIZE 1 ++/* Bit: 'RA11_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define AR9_RA_07_04_REG_RA11_TXTAG_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA11_TXTAG_SHIFT 10 ++#define AR9_RA_07_04_REG_RA11_TXTAG_SIZE 2 ++/* Bit: 'RA11_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define AR9_RA_07_04_REG_RA11_ACT_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA11_ACT_SHIFT 8 ++#define AR9_RA_07_04_REG_RA11_ACT_SIZE 2 ++/* Bit: 'RA10_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define AR9_RA_07_04_REG_RA10_VALID_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA10_VALID_SHIFT 7 ++#define AR9_RA_07_04_REG_RA10_VALID_SIZE 1 ++/* Bit: 'RA10_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define AR9_RA_07_04_REG_RA10_SPAN_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA10_SPAN_SHIFT 6 ++#define AR9_RA_07_04_REG_RA10_SPAN_SIZE 1 ++/* Bit: 'RA10_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define AR9_RA_07_04_REG_RA10_MG_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA10_MG_SHIFT 5 ++#define AR9_RA_07_04_REG_RA10_MG_SIZE 1 ++/* Bit: 'RA10_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define AR9_RA_07_04_REG_RA10_CV_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA10_CV_SHIFT 4 ++#define AR9_RA_07_04_REG_RA10_CV_SIZE 1 ++/* Bit: 'RA10_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define AR9_RA_07_04_REG_RA10_TXTAG_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA10_TXTAG_SHIFT 2 ++#define AR9_RA_07_04_REG_RA10_TXTAG_SIZE 2 ++/* Bit: 'RA10_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define AR9_RA_07_04_REG_RA10_ACT_OFFSET 0x0184 ++#define AR9_RA_07_04_REG_RA10_ACT_SHIFT 0 ++#define AR9_RA_07_04_REG_RA10_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C200000B~0180C2000008' */ ++/* Bit: 'RA23_VALID' */ ++/* Description: 'Valid bit for 0180C2000003' */ ++#define AR9_RA_0B_08_REG_RA23_VALID_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA23_VALID_SHIFT 31 ++#define AR9_RA_0B_08_REG_RA23_VALID_SIZE 1 ++/* Bit: 'RA23_SPAN' */ ++/* Description: 'Span bit for 0180C2000003' */ ++#define AR9_RA_0B_08_REG_RA23_SPAN_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA23_SPAN_SHIFT 30 ++#define AR9_RA_0B_08_REG_RA23_SPAN_SIZE 1 ++/* Bit: 'RA23_MG' */ ++/* Description: 'Management bit for 0180C2000003' */ ++#define AR9_RA_0B_08_REG_RA23_MG_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA23_MG_SHIFT 29 ++#define AR9_RA_0B_08_REG_RA23_MG_SIZE 1 ++/* Bit: 'RA23_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000003' */ ++#define AR9_RA_0B_08_REG_RA23_CV_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA23_CV_SHIFT 28 ++#define AR9_RA_0B_08_REG_RA23_CV_SIZE 1 ++/* Bit: 'RA23_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000003' */ ++#define AR9_RA_0B_08_REG_RA23_TXTAG_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA23_TXTAG_SHIFT 26 ++#define AR9_RA_0B_08_REG_RA23_TXTAG_SIZE 2 ++/* Bit: 'RA23_ACT' */ ++/* Description: 'Action bit for 0180C2000003' */ ++#define AR9_RA_0B_08_REG_RA23_ACT_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA23_ACT_SHIFT 24 ++#define AR9_RA_0B_08_REG_RA23_ACT_SIZE 2 ++/* Bit: 'RA22_VALID' */ ++/* Description: 'Valid bit for 0180C2000002' */ ++#define AR9_RA_0B_08_REG_RA22_VALID_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA22_VALID_SHIFT 23 ++#define AR9_RA_0B_08_REG_RA22_VALID_SIZE 1 ++/* Bit: 'RA22_SPAN' */ ++/* Description: 'Span bit for 0180C2000002' */ ++#define AR9_RA_0B_08_REG_RA22_SPAN_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA22_SPAN_SHIFT 22 ++#define AR9_RA_0B_08_REG_RA22_SPAN_SIZE 1 ++/* Bit: 'RA22_MG' */ ++/* Description: 'Management bit for 0180C2000002' */ ++#define AR9_RA_0B_08_REG_RA22_MG_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA22_MG_SHIFT 21 ++#define AR9_RA_0B_08_REG_RA22_MG_SIZE 1 ++/* Bit: 'RA22_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000002' */ ++#define AR9_RA_0B_08_REG_RA22_CV_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA22_CV_SHIFT 20 ++#define AR9_RA_0B_08_REG_RA22_CV_SIZE 1 ++/* Bit: 'RA22_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000002' */ ++#define AR9_RA_0B_08_REG_RA22_TXTAG_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA22_TXTAG_SHIFT 18 ++#define AR9_RA_0B_08_REG_RA22_TXTAG_SIZE 2 ++/* Bit: 'RA22_ACT' */ ++/* Description: 'Action bit for 0180C2000002' */ ++#define AR9_RA_0B_08_REG_RA22_ACT_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA22_ACT_SHIFT 16 ++#define AR9_RA_0B_08_REG_RA22_ACT_SIZE 2 ++/* Bit: 'RA21_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define AR9_RA_0B_08_REG_RA21_VALID_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA21_VALID_SHIFT 15 ++#define AR9_RA_0B_08_REG_RA21_VALID_SIZE 1 ++/* Bit: 'RA21_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define AR9_RA_0B_08_REG_RA21_SPAN_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA21_SPAN_SHIFT 14 ++#define AR9_RA_0B_08_REG_RA21_SPAN_SIZE 1 ++/* Bit: 'RA21_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define AR9_RA_0B_08_REG_RA21_MG_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA21_MG_SHIFT 13 ++#define AR9_RA_0B_08_REG_RA21_MG_SIZE 1 ++/* Bit: 'RA21_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define AR9_RA_0B_08_REG_RA21_CV_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA21_CV_SHIFT 12 ++#define AR9_RA_0B_08_REG_RA21_CV_SIZE 1 ++/* Bit: 'RA21_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define AR9_RA_0B_08_REG_RA21_TXTAG_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA21_TXTAG_SHIFT 10 ++#define AR9_RA_0B_08_REG_RA21_TXTAG_SIZE 2 ++/* Bit: 'RA21_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define AR9_RA_0B_08_REG_RA21_ACT_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA21_ACT_SHIFT 8 ++#define AR9_RA_0B_08_REG_RA21_ACT_SIZE 2 ++/* Bit: 'RA20_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define AR9_RA_0B_08_REG_RA20_VALID_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA20_VALID_SHIFT 7 ++#define AR9_RA_0B_08_REG_RA20_VALID_SIZE 1 ++/* Bit: 'RA20_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define AR9_RA_0B_08_REG_RA20_SPAN_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA20_SPAN_SHIFT 6 ++#define AR9_RA_0B_08_REG_RA20_SPAN_SIZE 1 ++/* Bit: 'RA20_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define AR9_RA_0B_08_REG_RA20_MG_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA20_MG_SHIFT 5 ++#define AR9_RA_0B_08_REG_RA20_MG_SIZE 1 ++/* Bit: 'RA20_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define AR9_RA_0B_08_REG_RA20_CV_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA20_CV_SHIFT 4 ++#define AR9_RA_0B_08_REG_RA20_CV_SIZE 1 ++/* Bit: 'RA20_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define AR9_RA_0B_08_REG_RA20_TXTAG_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA20_TXTAG_SHIFT 2 ++#define AR9_RA_0B_08_REG_RA20_TXTAG_SIZE 2 ++/* Bit: 'RA20_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define AR9_RA_0B_08_REG_RA20_ACT_OFFSET 0x0188 ++#define AR9_RA_0B_08_REG_RA20_ACT_SHIFT 0 ++#define AR9_RA_0B_08_REG_RA20_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C200000F~0180C200000C' */ ++/* Bit: 'RA33_VALID' */ ++/* Description: 'Valid bit for 0180C2000003' */ ++#define AR9_RA_0F_0C_REG_RA33_VALID_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA33_VALID_SHIFT 31 ++#define AR9_RA_0F_0C_REG_RA33_VALID_SIZE 1 ++/* Bit: 'RA33_SPAN' */ ++/* Description: 'Span bit for 0180C2000003' */ ++#define AR9_RA_0F_0C_REG_RA33_SPAN_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA33_SPAN_SHIFT 30 ++#define AR9_RA_0F_0C_REG_RA33_SPAN_SIZE 1 ++/* Bit: 'RA33_MG' */ ++/* Description: 'Management bit for 0180C2000003' */ ++#define AR9_RA_0F_0C_REG_RA33_MG_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA33_MG_SHIFT 29 ++#define AR9_RA_0F_0C_REG_RA33_MG_SIZE 1 ++/* Bit: 'RA33_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000003' */ ++#define AR9_RA_0F_0C_REG_RA33_CV_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA33_CV_SHIFT 28 ++#define AR9_RA_0F_0C_REG_RA33_CV_SIZE 1 ++/* Bit: 'RA33_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000003' */ ++#define AR9_RA_0F_0C_REG_RA33_TXTAG_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA33_TXTAG_SHIFT 26 ++#define AR9_RA_0F_0C_REG_RA33_TXTAG_SIZE 2 ++/* Bit: 'RA33_ACT' */ ++/* Description: 'Action bit for 0180C2000003' */ ++#define AR9_RA_0F_0C_REG_RA33_ACT_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA33_ACT_SHIFT 24 ++#define AR9_RA_0F_0C_REG_RA33_ACT_SIZE 2 ++/* Bit: 'RA32_VALID' */ ++/* Description: 'Valid bit for 0180C2000002' */ ++#define AR9_RA_0F_0C_REG_RA32_VALID_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA32_VALID_SHIFT 23 ++#define AR9_RA_0F_0C_REG_RA32_VALID_SIZE 1 ++/* Bit: 'RA32_SPAN' */ ++/* Description: 'Span bit for 0180C2000002' */ ++#define AR9_RA_0F_0C_REG_RA32_SPAN_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA32_SPAN_SHIFT 22 ++#define AR9_RA_0F_0C_REG_RA32_SPAN_SIZE 1 ++/* Bit: 'RA32_MG' */ ++/* Description: 'Management bit for 0180C2000002' */ ++#define AR9_RA_0F_0C_REG_RA32_MG_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA32_MG_SHIFT 21 ++#define AR9_RA_0F_0C_REG_RA32_MG_SIZE 1 ++/* Bit: 'RA32_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000002' */ ++#define AR9_RA_0F_0C_REG_RA32_CV_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA32_CV_SHIFT 20 ++#define AR9_RA_0F_0C_REG_RA32_CV_SIZE 1 ++/* Bit: 'RA32_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000002' */ ++#define AR9_RA_0F_0C_REG_RA32_TXTAG_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA32_TXTAG_SHIFT 18 ++#define AR9_RA_0F_0C_REG_RA32_TXTAG_SIZE 2 ++/* Bit: 'RA32_ACT' */ ++/* Description: 'Action bit for 0180C2000002' */ ++#define AR9_RA_0F_0C_REG_RA32_ACT_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA32_ACT_SHIFT 16 ++#define AR9_RA_0F_0C_REG_RA32_ACT_SIZE 2 ++/* Bit: 'RA31_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define AR9_RA_0F_0C_REG_RA31_VALID_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA31_VALID_SHIFT 15 ++#define AR9_RA_0F_0C_REG_RA31_VALID_SIZE 1 ++/* Bit: 'RA31_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define AR9_RA_0F_0C_REG_RA31_SPAN_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA31_SPAN_SHIFT 14 ++#define AR9_RA_0F_0C_REG_RA31_SPAN_SIZE 1 ++/* Bit: 'RA31_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define AR9_RA_0F_0C_REG_RA31_MG_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA31_MG_SHIFT 13 ++#define AR9_RA_0F_0C_REG_RA31_MG_SIZE 1 ++/* Bit: 'RA31_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define AR9_RA_0F_0C_REG_RA31_CV_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA31_CV_SHIFT 12 ++#define AR9_RA_0F_0C_REG_RA31_CV_SIZE 1 ++/* Bit: 'RA31_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define AR9_RA_0F_0C_REG_RA31_TXTAG_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA31_TXTAG_SHIFT 10 ++#define AR9_RA_0F_0C_REG_RA31_TXTAG_SIZE 2 ++/* Bit: 'RA31_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define AR9_RA_0F_0C_REG_RA31_ACT_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA31_ACT_SHIFT 8 ++#define AR9_RA_0F_0C_REG_RA31_ACT_SIZE 2 ++/* Bit: 'RA30_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define AR9_RA_0F_0C_REG_RA30_VALID_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA30_VALID_SHIFT 7 ++#define AR9_RA_0F_0C_REG_RA30_VALID_SIZE 1 ++/* Bit: 'RA30_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define AR9_RA_0F_0C_REG_RA30_SPAN_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA30_SPAN_SHIFT 6 ++#define AR9_RA_0F_0C_REG_RA30_SPAN_SIZE 1 ++/* Bit: 'RA30_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define AR9_RA_0F_0C_REG_RA30_MG_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA30_MG_SHIFT 5 ++#define AR9_RA_0F_0C_REG_RA30_MG_SIZE 1 ++/* Bit: 'RA30_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define AR9_RA_0F_0C_REG_RA30_CV_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA30_CV_SHIFT 4 ++#define AR9_RA_0F_0C_REG_RA30_CV_SIZE 1 ++/* Bit: 'RA30_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define AR9_RA_0F_0C_REG_RA30_TXTAG_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA30_TXTAG_SHIFT 2 ++#define AR9_RA_0F_0C_REG_RA30_TXTAG_SIZE 2 ++/* Bit: 'RA30_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define AR9_RA_0F_0C_REG_RA30_ACT_OFFSET 0x018C ++#define AR9_RA_0F_0C_REG_RA30_ACT_SHIFT 0 ++#define AR9_RA_0F_0C_REG_RA30_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C2000013~0180C2000010' */ ++/* Bit: 'RA43_VALID' */ ++/* Description: 'Valid bit for 0180C2000003' */ ++#define AR9_RA_13_10_REG_RA43_VALID_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA43_VALID_SHIFT 31 ++#define AR9_RA_13_10_REG_RA43_VALID_SIZE 1 ++/* Bit: 'RA43_SPAN' */ ++/* Description: 'Span bit for 0180C2000003' */ ++#define AR9_RA_13_10_REG_RA43_SPAN_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA43_SPAN_SHIFT 30 ++#define AR9_RA_13_10_REG_RA43_SPAN_SIZE 1 ++/* Bit: 'RA43_MG' */ ++/* Description: 'Management bit for 0180C2000003' */ ++#define AR9_RA_13_10_REG_RA43_MG_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA43_MG_SHIFT 29 ++#define AR9_RA_13_10_REG_RA43_MG_SIZE 1 ++/* Bit: 'RA43_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000003' */ ++#define AR9_RA_13_10_REG_RA43_CV_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA43_CV_SHIFT 28 ++#define AR9_RA_13_10_REG_RA43_CV_SIZE 1 ++/* Bit: 'RA43_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000003' */ ++#define AR9_RA_13_10_REG_RA43_TXTAG_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA43_TXTAG_SHIFT 26 ++#define AR9_RA_13_10_REG_RA43_TXTAG_SIZE 2 ++/* Bit: 'RA43_ACT' */ ++/* Description: 'Action bit for 0180C2000003' */ ++#define AR9_RA_13_10_REG_RA43_ACT_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA43_ACT_SHIFT 24 ++#define AR9_RA_13_10_REG_RA43_ACT_SIZE 2 ++/* Bit: 'RA42_VALID' */ ++/* Description: 'Valid bit for 0180C2000002' */ ++#define AR9_RA_13_10_REG_RA42_VALID_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA42_VALID_SHIFT 23 ++#define AR9_RA_13_10_REG_RA42_VALID_SIZE 1 ++/* Bit: 'RA42_SPAN' */ ++/* Description: 'Span bit for 0180C2000002' */ ++#define AR9_RA_13_10_REG_RA42_SPAN_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA42_SPAN_SHIFT 22 ++#define AR9_RA_13_10_REG_RA42_SPAN_SIZE 1 ++/* Bit: 'RA42_MG' */ ++/* Description: 'Management bit for 0180C2000002' */ ++#define AR9_RA_13_10_REG_RA42_MG_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA42_MG_SHIFT 21 ++#define AR9_RA_13_10_REG_RA42_MG_SIZE 1 ++/* Bit: 'RA42_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000002' */ ++#define AR9_RA_13_10_REG_RA42_CV_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA42_CV_SHIFT 20 ++#define AR9_RA_13_10_REG_RA42_CV_SIZE 1 ++/* Bit: 'RA42_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000002' */ ++#define AR9_RA_13_10_REG_RA42_TXTAG_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA42_TXTAG_SHIFT 18 ++#define AR9_RA_13_10_REG_RA42_TXTAG_SIZE 2 ++/* Bit: 'RA42_ACT' */ ++/* Description: 'Action bit for 0180C2000002' */ ++#define AR9_RA_13_10_REG_RA42_ACT_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA42_ACT_SHIFT 16 ++#define AR9_RA_13_10_REG_RA42_ACT_SIZE 2 ++/* Bit: 'RA41_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define AR9_RA_13_10_REG_RA41_VALID_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA41_VALID_SHIFT 15 ++#define AR9_RA_13_10_REG_RA41_VALID_SIZE 1 ++/* Bit: 'RA41_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define AR9_RA_13_10_REG_RA41_SPAN_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA41_SPAN_SHIFT 14 ++#define AR9_RA_13_10_REG_RA41_SPAN_SIZE 1 ++/* Bit: 'RA41_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define AR9_RA_13_10_REG_RA41_MG_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA41_MG_SHIFT 13 ++#define AR9_RA_13_10_REG_RA41_MG_SIZE 1 ++/* Bit: 'RA41_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define AR9_RA_13_10_REG_RA41_CV_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA41_CV_SHIFT 12 ++#define AR9_RA_13_10_REG_RA41_CV_SIZE 1 ++/* Bit: 'RA41_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define AR9_RA_13_10_REG_RA41_TXTAG_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA41_TXTAG_SHIFT 10 ++#define AR9_RA_13_10_REG_RA41_TXTAG_SIZE 2 ++/* Bit: 'RA41_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define AR9_RA_13_10_REG_RA41_ACT_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA41_ACT_SHIFT 8 ++#define AR9_RA_13_10_REG_RA41_ACT_SIZE 2 ++/* Bit: 'RA40_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define AR9_RA_13_10_REG_RA40_VALID_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA40_VALID_SHIFT 7 ++#define AR9_RA_13_10_REG_RA40_VALID_SIZE 1 ++/* Bit: 'RA40_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define AR9_RA_13_10_REG_RA40_SPAN_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA40_SPAN_SHIFT 6 ++#define AR9_RA_13_10_REG_RA40_SPAN_SIZE 1 ++/* Bit: 'RA40_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define AR9_RA_13_10_REG_RA40_MG_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA40_MG_SHIFT 5 ++#define AR9_RA_13_10_REG_RA40_MG_SIZE 1 ++/* Bit: 'RA40_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define AR9_RA_13_10_REG_RA40_CV_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA40_CV_SHIFT 4 ++#define AR9_RA_13_10_REG_RA40_CV_SIZE 1 ++/* Bit: 'RA40_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define AR9_RA_13_10_REG_RA40_TXTAG_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA40_TXTAG_SHIFT 2 ++#define AR9_RA_13_10_REG_RA40_TXTAG_SIZE 2 ++/* Bit: 'RA40_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define AR9_RA_13_10_REG_RA40_ACT_OFFSET 0x0190 ++#define AR9_RA_13_10_REG_RA40_ACT_SHIFT 0 ++#define AR9_RA_13_10_REG_RA40_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C2000017~0180C2000014' */ ++/* Bit: 'RA53_VALID' */ ++/* Description: 'Valid bit for 0180C2000003' */ ++#define AR9_RA_17_14_REG_RA53_VALID_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA53_VALID_SHIFT 31 ++#define AR9_RA_17_14_REG_RA53_VALID_SIZE 1 ++/* Bit: 'RA53_SPAN' */ ++/* Description: 'Span bit for 0180C2000003' */ ++#define AR9_RA_17_14_REG_RA53_SPAN_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA53_SPAN_SHIFT 30 ++#define AR9_RA_17_14_REG_RA53_SPAN_SIZE 1 ++/* Bit: 'RA53_MG' */ ++/* Description: 'Management bit for 0180C2000003' */ ++#define AR9_RA_17_14_REG_RA53_MG_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA53_MG_SHIFT 29 ++#define AR9_RA_17_14_REG_RA53_MG_SIZE 1 ++/* Bit: 'RA53_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000003' */ ++#define AR9_RA_17_14_REG_RA53_CV_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA53_CV_SHIFT 28 ++#define AR9_RA_17_14_REG_RA53_CV_SIZE 1 ++/* Bit: 'RA53_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000003' */ ++#define AR9_RA_17_14_REG_RA53_TXTAG_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA53_TXTAG_SHIFT 26 ++#define AR9_RA_17_14_REG_RA53_TXTAG_SIZE 2 ++/* Bit: 'RA53_ACT' */ ++/* Description: 'Action bit for 0180C2000003' */ ++#define AR9_RA_17_14_REG_RA53_ACT_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA53_ACT_SHIFT 24 ++#define AR9_RA_17_14_REG_RA53_ACT_SIZE 2 ++/* Bit: 'RA52_VALID' */ ++/* Description: 'Valid bit for 0180C2000002' */ ++#define AR9_RA_17_14_REG_RA52_VALID_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA52_VALID_SHIFT 23 ++#define AR9_RA_17_14_REG_RA52_VALID_SIZE 1 ++/* Bit: 'RA52_SPAN' */ ++/* Description: 'Span bit for 0180C2000002' */ ++#define AR9_RA_17_14_REG_RA52_SPAN_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA52_SPAN_SHIFT 22 ++#define AR9_RA_17_14_REG_RA52_SPAN_SIZE 1 ++/* Bit: 'RA52_MG' */ ++/* Description: 'Management bit for 0180C2000002' */ ++#define AR9_RA_17_14_REG_RA52_MG_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA52_MG_SHIFT 21 ++#define AR9_RA_17_14_REG_RA52_MG_SIZE 1 ++/* Bit: 'RA52_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000002' */ ++#define AR9_RA_17_14_REG_RA52_CV_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA52_CV_SHIFT 20 ++#define AR9_RA_17_14_REG_RA52_CV_SIZE 1 ++/* Bit: 'RA52_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000002' */ ++#define AR9_RA_17_14_REG_RA52_TXTAG_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA52_TXTAG_SHIFT 18 ++#define AR9_RA_17_14_REG_RA52_TXTAG_SIZE 2 ++/* Bit: 'RA52_ACT' */ ++/* Description: 'Action bit for 0180C2000002' */ ++#define AR9_RA_17_14_REG_RA52_ACT_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA52_ACT_SHIFT 16 ++#define AR9_RA_17_14_REG_RA52_ACT_SIZE 2 ++/* Bit: 'RA51_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define AR9_RA_17_14_REG_RA51_VALID_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA51_VALID_SHIFT 15 ++#define AR9_RA_17_14_REG_RA51_VALID_SIZE 1 ++/* Bit: 'RA51_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define AR9_RA_17_14_REG_RA51_SPAN_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA51_SPAN_SHIFT 14 ++#define AR9_RA_17_14_REG_RA51_SPAN_SIZE 1 ++/* Bit: 'RA51_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define AR9_RA_17_14_REG_RA51_MG_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA51_MG_SHIFT 13 ++#define AR9_RA_17_14_REG_RA51_MG_SIZE 1 ++/* Bit: 'RA51_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define AR9_RA_17_14_REG_RA51_CV_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA51_CV_SHIFT 12 ++#define AR9_RA_17_14_REG_RA51_CV_SIZE 1 ++/* Bit: 'RA51_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define AR9_RA_17_14_REG_RA51_TXTAG_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA51_TXTAG_SHIFT 10 ++#define AR9_RA_17_14_REG_RA51_TXTAG_SIZE 2 ++/* Bit: 'RA51_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define AR9_RA_17_14_REG_RA51_ACT_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA51_ACT_SHIFT 8 ++#define AR9_RA_17_14_REG_RA51_ACT_SIZE 2 ++/* Bit: 'RA50_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define AR9_RA_17_14_REG_RA50_VALID_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA50_VALID_SHIFT 7 ++#define AR9_RA_17_14_REG_RA50_VALID_SIZE 1 ++/* Bit: 'RA50_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define AR9_RA_17_14_REG_RA50_SPAN_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA50_SPAN_SHIFT 6 ++#define AR9_RA_17_14_REG_RA50_SPAN_SIZE 1 ++/* Bit: 'RA50_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define AR9_RA_17_14_REG_RA50_MG_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA50_MG_SHIFT 5 ++#define AR9_RA_17_14_REG_RA50_MG_SIZE 1 ++/* Bit: 'RA50_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define AR9_RA_17_14_REG_RA50_CV_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA50_CV_SHIFT 4 ++#define AR9_RA_17_14_REG_RA50_CV_SIZE 1 ++/* Bit: 'RA50_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define AR9_RA_17_14_REG_RA50_TXTAG_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA50_TXTAG_SHIFT 2 ++#define AR9_RA_17_14_REG_RA50_TXTAG_SIZE 2 ++/* Bit: 'RA50_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define AR9_RA_17_14_REG_RA50_ACT_OFFSET 0x0194 ++#define AR9_RA_17_14_REG_RA50_ACT_SHIFT 0 ++#define AR9_RA_17_14_REG_RA50_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C200001B~0180C2000018' */ ++/* Bit: 'RA63_VALID' */ ++/* Description: 'Valid bit for 0180C2000003' */ ++#define AR9_RA_1B_18_REG_RA63_VALID_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA63_VALID_SHIFT 31 ++#define AR9_RA_1B_18_REG_RA63_VALID_SIZE 1 ++/* Bit: 'RA63_SPAN' */ ++/* Description: 'Span bit for 0180C2000003' */ ++#define AR9_RA_1B_18_REG_RA63_SPAN_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA63_SPAN_SHIFT 30 ++#define AR9_RA_1B_18_REG_RA63_SPAN_SIZE 1 ++/* Bit: 'RA63_MG' */ ++/* Description: 'Management bit for 0180C2000003' */ ++#define AR9_RA_1B_18_REG_RA63_MG_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA63_MG_SHIFT 29 ++#define AR9_RA_1B_18_REG_RA63_MG_SIZE 1 ++/* Bit: 'RA63_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000003' */ ++#define AR9_RA_1B_18_REG_RA63_CV_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA63_CV_SHIFT 28 ++#define AR9_RA_1B_18_REG_RA63_CV_SIZE 1 ++/* Bit: 'RA63_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000003' */ ++#define AR9_RA_1B_18_REG_RA63_TXTAG_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA63_TXTAG_SHIFT 26 ++#define AR9_RA_1B_18_REG_RA63_TXTAG_SIZE 2 ++/* Bit: 'RA63_ACT' */ ++/* Description: 'Action bit for 0180C2000003' */ ++#define AR9_RA_1B_18_REG_RA63_ACT_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA63_ACT_SHIFT 24 ++#define AR9_RA_1B_18_REG_RA63_ACT_SIZE 2 ++/* Bit: 'RA62_VALID' */ ++/* Description: 'Valid bit for 0180C2000002' */ ++#define AR9_RA_1B_18_REG_RA62_VALID_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA62_VALID_SHIFT 23 ++#define AR9_RA_1B_18_REG_RA62_VALID_SIZE 1 ++/* Bit: 'RA62_SPAN' */ ++/* Description: 'Span bit for 0180C2000002' */ ++#define AR9_RA_1B_18_REG_RA62_SPAN_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA62_SPAN_SHIFT 22 ++#define AR9_RA_1B_18_REG_RA62_SPAN_SIZE 1 ++/* Bit: 'RA62_MG' */ ++/* Description: 'Management bit for 0180C2000002' */ ++#define AR9_RA_1B_18_REG_RA62_MG_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA62_MG_SHIFT 21 ++#define AR9_RA_1B_18_REG_RA62_MG_SIZE 1 ++/* Bit: 'RA62_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000002' */ ++#define AR9_RA_1B_18_REG_RA62_CV_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA62_CV_SHIFT 20 ++#define AR9_RA_1B_18_REG_RA62_CV_SIZE 1 ++/* Bit: 'RA62_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000002' */ ++#define AR9_RA_1B_18_REG_RA62_TXTAG_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA62_TXTAG_SHIFT 18 ++#define AR9_RA_1B_18_REG_RA62_TXTAG_SIZE 2 ++/* Bit: 'RA62_ACT' */ ++/* Description: 'Action bit for 0180C2000002' */ ++#define AR9_RA_1B_18_REG_RA62_ACT_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA62_ACT_SHIFT 16 ++#define AR9_RA_1B_18_REG_RA62_ACT_SIZE 2 ++/* Bit: 'RA61_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define AR9_RA_1B_18_REG_RA61_VALID_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA61_VALID_SHIFT 15 ++#define AR9_RA_1B_18_REG_RA61_VALID_SIZE 1 ++/* Bit: 'RA61_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define AR9_RA_1B_18_REG_RA61_SPAN_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA61_SPAN_SHIFT 14 ++#define AR9_RA_1B_18_REG_RA61_SPAN_SIZE 1 ++/* Bit: 'RA61_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define AR9_RA_1B_18_REG_RA61_MG_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA61_MG_SHIFT 13 ++#define AR9_RA_1B_18_REG_RA61_MG_SIZE 1 ++/* Bit: 'RA61_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define AR9_RA_1B_18_REG_RA61_CV_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA61_CV_SHIFT 12 ++#define AR9_RA_1B_18_REG_RA61_CV_SIZE 1 ++/* Bit: 'RA61_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define AR9_RA_1B_18_REG_RA61_TXTAG_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA61_TXTAG_SHIFT 10 ++#define AR9_RA_1B_18_REG_RA61_TXTAG_SIZE 2 ++/* Bit: 'RA61_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define AR9_RA_1B_18_REG_RA61_ACT_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA61_ACT_SHIFT 8 ++#define AR9_RA_1B_18_REG_RA61_ACT_SIZE 2 ++/* Bit: 'RA60_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define AR9_RA_1B_18_REG_RA60_VALID_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA60_VALID_SHIFT 7 ++#define AR9_RA_1B_18_REG_RA60_VALID_SIZE 1 ++/* Bit: 'RA60_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define AR9_RA_1B_18_REG_RA60_SPAN_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA60_SPAN_SHIFT 6 ++#define AR9_RA_1B_18_REG_RA60_SPAN_SIZE 1 ++/* Bit: 'RA60_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define AR9_RA_1B_18_REG_RA60_MG_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA60_MG_SHIFT 5 ++#define AR9_RA_1B_18_REG_RA60_MG_SIZE 1 ++/* Bit: 'RA60_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define AR9_RA_1B_18_REG_RA60_CV_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA60_CV_SHIFT 4 ++#define AR9_RA_1B_18_REG_RA60_CV_SIZE 1 ++/* Bit: 'RA60_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define AR9_RA_1B_18_REG_RA60_TXTAG_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA60_TXTAG_SHIFT 2 ++#define AR9_RA_1B_18_REG_RA60_TXTAG_SIZE 2 ++/* Bit: 'RA60_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define AR9_RA_1B_18_REG_RA60_ACT_OFFSET 0x0198 ++#define AR9_RA_1B_18_REG_RA60_ACT_SHIFT 0 ++#define AR9_RA_1B_18_REG_RA60_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C200001F~0180C200001C' */ ++/* Bit: 'RA73_VALID' */ ++/* Description: 'Valid bit for 0180C2000003' */ ++#define AR9_RA_1F_1C_REG_RA73_VALID_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA73_VALID_SHIFT 31 ++#define AR9_RA_1F_1C_REG_RA73_VALID_SIZE 1 ++/* Bit: 'RA73_SPAN' */ ++/* Description: 'Span bit for 0180C2000003' */ ++#define AR9_RA_1F_1C_REG_RA73_SPAN_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA73_SPAN_SHIFT 30 ++#define AR9_RA_1F_1C_REG_RA73_SPAN_SIZE 1 ++/* Bit: 'RA73_MG' */ ++/* Description: 'Management bit for 0180C2000003' */ ++#define AR9_RA_1F_1C_REG_RA73_MG_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA73_MG_SHIFT 29 ++#define AR9_RA_1F_1C_REG_RA73_MG_SIZE 1 ++/* Bit: 'RA73_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000003' */ ++#define AR9_RA_1F_1C_REG_RA73_CV_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA73_CV_SHIFT 28 ++#define AR9_RA_1F_1C_REG_RA73_CV_SIZE 1 ++/* Bit: 'RA73_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000003' */ ++#define AR9_RA_1F_1C_REG_RA73_TXTAG_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA73_TXTAG_SHIFT 26 ++#define AR9_RA_1F_1C_REG_RA73_TXTAG_SIZE 2 ++/* Bit: 'RA73_ACT' */ ++/* Description: 'Action bit for 0180C2000003' */ ++#define AR9_RA_1F_1C_REG_RA73_ACT_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA73_ACT_SHIFT 24 ++#define AR9_RA_1F_1C_REG_RA73_ACT_SIZE 2 ++/* Bit: 'RA72_VALID' */ ++/* Description: 'Valid bit for 0180C2000002' */ ++#define AR9_RA_1F_1C_REG_RA72_VALID_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA72_VALID_SHIFT 23 ++#define AR9_RA_1F_1C_REG_RA72_VALID_SIZE 1 ++/* Bit: 'RA72_SPAN' */ ++/* Description: 'Span bit for 0180C2000002' */ ++#define AR9_RA_1F_1C_REG_RA72_SPAN_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA72_SPAN_SHIFT 22 ++#define AR9_RA_1F_1C_REG_RA72_SPAN_SIZE 1 ++/* Bit: 'RA72_MG' */ ++/* Description: 'Management bit for 0180C2000002' */ ++#define AR9_RA_1F_1C_REG_RA72_MG_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA72_MG_SHIFT 21 ++#define AR9_RA_1F_1C_REG_RA72_MG_SIZE 1 ++/* Bit: 'RA72_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000002' */ ++#define AR9_RA_1F_1C_REG_RA72_CV_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA72_CV_SHIFT 20 ++#define AR9_RA_1F_1C_REG_RA72_CV_SIZE 1 ++/* Bit: 'RA72_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000002' */ ++#define AR9_RA_1F_1C_REG_RA72_TXTAG_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA72_TXTAG_SHIFT 18 ++#define AR9_RA_1F_1C_REG_RA72_TXTAG_SIZE 2 ++/* Bit: 'RA72_ACT' */ ++/* Description: 'Action bit for 0180C2000002' */ ++#define AR9_RA_1F_1C_REG_RA72_ACT_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA72_ACT_SHIFT 16 ++#define AR9_RA_1F_1C_REG_RA72_ACT_SIZE 2 ++/* Bit: 'RA71_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define AR9_RA_1F_1C_REG_RA71_VALID_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA71_VALID_SHIFT 15 ++#define AR9_RA_1F_1C_REG_RA71_VALID_SIZE 1 ++/* Bit: 'RA71_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define AR9_RA_1F_1C_REG_RA71_SPAN_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA71_SPAN_SHIFT 14 ++#define AR9_RA_1F_1C_REG_RA71_SPAN_SIZE 1 ++/* Bit: 'RA71_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define AR9_RA_1F_1C_REG_RA71_MG_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA71_MG_SHIFT 13 ++#define AR9_RA_1F_1C_REG_RA71_MG_SIZE 1 ++/* Bit: 'RA71_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define AR9_RA_1F_1C_REG_RA71_CV_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA71_CV_SHIFT 12 ++#define AR9_RA_1F_1C_REG_RA71_CV_SIZE 1 ++/* Bit: 'RA71_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define AR9_RA_1F_1C_REG_RA71_TXTAG_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA71_TXTAG_SHIFT 10 ++#define AR9_RA_1F_1C_REG_RA71_TXTAG_SIZE 2 ++/* Bit: 'RA71_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define AR9_RA_1F_1C_REG_RA71_ACT_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA71_ACT_SHIFT 8 ++#define AR9_RA_1F_1C_REG_RA71_ACT_SIZE 2 ++/* Bit: 'RA70_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define AR9_RA_1F_1C_REG_RA70_VALID_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA70_VALID_SHIFT 7 ++#define AR9_RA_1F_1C_REG_RA70_VALID_SIZE 1 ++/* Bit: 'RA70_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define AR9_RA_1F_1C_REG_RA70_SPAN_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA70_SPAN_SHIFT 6 ++#define AR9_RA_1F_1C_REG_RA70_SPAN_SIZE 1 ++/* Bit: 'RA70_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define AR9_RA_1F_1C_REG_RA70_MG_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA70_MG_SHIFT 5 ++#define AR9_RA_1F_1C_REG_RA70_MG_SIZE 1 ++/* Bit: 'RA70_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define AR9_RA_1F_1C_REG_RA70_CV_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA70_CV_SHIFT 4 ++#define AR9_RA_1F_1C_REG_RA70_CV_SIZE 1 ++/* Bit: 'RA70_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define AR9_RA_1F_1C_REG_RA70_TXTAG_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA70_TXTAG_SHIFT 2 ++#define AR9_RA_1F_1C_REG_RA70_TXTAG_SIZE 2 ++/* Bit: 'RA70_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define AR9_RA_1F_1C_REG_RA70_ACT_OFFSET 0x019C ++#define AR9_RA_1F_1C_REG_RA70_ACT_SHIFT 0 ++#define AR9_RA_1F_1C_REG_RA70_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C2000023~0180C2000020' */ ++/* Bit: 'RA83_VALID' */ ++/* Description: 'Valid bit for 0180C2000003' */ ++#define AR9_RA_23_20_REG_RA83_VALID_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA83_VALID_SHIFT 31 ++#define AR9_RA_23_20_REG_RA83_VALID_SIZE 1 ++/* Bit: 'RA83_SPAN' */ ++/* Description: 'Span bit for 0180C2000003' */ ++#define AR9_RA_23_20_REG_RA83_SPAN_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA83_SPAN_SHIFT 30 ++#define AR9_RA_23_20_REG_RA83_SPAN_SIZE 1 ++/* Bit: 'RA83_MG' */ ++/* Description: 'Management bit for 0180C2000003' */ ++#define AR9_RA_23_20_REG_RA83_MG_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA83_MG_SHIFT 29 ++#define AR9_RA_23_20_REG_RA83_MG_SIZE 1 ++/* Bit: 'RA83_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000003' */ ++#define AR9_RA_23_20_REG_RA83_CV_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA83_CV_SHIFT 28 ++#define AR9_RA_23_20_REG_RA83_CV_SIZE 1 ++/* Bit: 'RA83_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000003' */ ++#define AR9_RA_23_20_REG_RA83_TXTAG_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA83_TXTAG_SHIFT 26 ++#define AR9_RA_23_20_REG_RA83_TXTAG_SIZE 2 ++/* Bit: 'RA83_ACT' */ ++/* Description: 'Action bit for 0180C2000003' */ ++#define AR9_RA_23_20_REG_RA83_ACT_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA83_ACT_SHIFT 24 ++#define AR9_RA_23_20_REG_RA83_ACT_SIZE 2 ++/* Bit: 'RA82_VALID' */ ++/* Description: 'Valid bit for 0180C2000002' */ ++#define AR9_RA_23_20_REG_RA82_VALID_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA82_VALID_SHIFT 23 ++#define AR9_RA_23_20_REG_RA82_VALID_SIZE 1 ++/* Bit: 'RA82_SPAN' */ ++/* Description: 'Span bit for 0180C2000002' */ ++#define AR9_RA_23_20_REG_RA82_SPAN_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA82_SPAN_SHIFT 22 ++#define AR9_RA_23_20_REG_RA82_SPAN_SIZE 1 ++/* Bit: 'RA82_MG' */ ++/* Description: 'Management bit for 0180C2000002' */ ++#define AR9_RA_23_20_REG_RA82_MG_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA82_MG_SHIFT 21 ++#define AR9_RA_23_20_REG_RA82_MG_SIZE 1 ++/* Bit: 'RA82_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000002' */ ++#define AR9_RA_23_20_REG_RA82_CV_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA82_CV_SHIFT 20 ++#define AR9_RA_23_20_REG_RA82_CV_SIZE 1 ++/* Bit: 'RA82_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000002' */ ++#define AR9_RA_23_20_REG_RA82_TXTAG_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA82_TXTAG_SHIFT 18 ++#define AR9_RA_23_20_REG_RA82_TXTAG_SIZE 2 ++/* Bit: 'RA82_ACT' */ ++/* Description: 'Action bit for 0180C2000002' */ ++#define AR9_RA_23_20_REG_RA82_ACT_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA82_ACT_SHIFT 16 ++#define AR9_RA_23_20_REG_RA82_ACT_SIZE 2 ++/* Bit: 'RA81_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define AR9_RA_23_20_REG_RA81_VALID_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA81_VALID_SHIFT 15 ++#define AR9_RA_23_20_REG_RA81_VALID_SIZE 1 ++/* Bit: 'RA81_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define AR9_RA_23_20_REG_RA81_SPAN_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA81_SPAN_SHIFT 14 ++#define AR9_RA_23_20_REG_RA81_SPAN_SIZE 1 ++/* Bit: 'RA81_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define AR9_RA_23_20_REG_RA81_MG_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA81_MG_SHIFT 13 ++#define AR9_RA_23_20_REG_RA81_MG_SIZE 1 ++/* Bit: 'RA81_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define AR9_RA_23_20_REG_RA81_CV_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA81_CV_SHIFT 12 ++#define AR9_RA_23_20_REG_RA81_CV_SIZE 1 ++/* Bit: 'RA81_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define AR9_RA_23_20_REG_RA81_TXTAG_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA81_TXTAG_SHIFT 10 ++#define AR9_RA_23_20_REG_RA81_TXTAG_SIZE 2 ++/* Bit: 'RA81_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define AR9_RA_23_20_REG_RA81_ACT_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA81_ACT_SHIFT 8 ++#define AR9_RA_23_20_REG_RA81_ACT_SIZE 2 ++/* Bit: 'RA80_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define AR9_RA_23_20_REG_RA80_VALID_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA80_VALID_SHIFT 7 ++#define AR9_RA_23_20_REG_RA80_VALID_SIZE 1 ++/* Bit: 'RA80_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define AR9_RA_23_20_REG_RA80_SPAN_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA80_SPAN_SHIFT 6 ++#define AR9_RA_23_20_REG_RA80_SPAN_SIZE 1 ++/* Bit: 'RA80_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define AR9_RA_23_20_REG_RA80_MG_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA80_MG_SHIFT 5 ++#define AR9_RA_23_20_REG_RA80_MG_SIZE 1 ++/* Bit: 'RA80_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define AR9_RA_23_20_REG_RA80_CV_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA80_CV_SHIFT 4 ++#define AR9_RA_23_20_REG_RA80_CV_SIZE 1 ++/* Bit: 'RA80_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define AR9_RA_23_20_REG_RA80_TXTAG_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA80_TXTAG_SHIFT 2 ++#define AR9_RA_23_20_REG_RA80_TXTAG_SIZE 2 ++/* Bit: 'RA80_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define AR9_RA_23_20_REG_RA80_ACT_OFFSET 0x01A0 ++#define AR9_RA_23_20_REG_RA80_ACT_SHIFT 0 ++#define AR9_RA_23_20_REG_RA80_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C2000027~0180C2000024' */ ++/* Bit: 'RA93_VALID' */ ++/* Description: 'Valid bit for 0180C2000003' */ ++#define AR9_RA_27_24_REG_RA93_VALID_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA93_VALID_SHIFT 31 ++#define AR9_RA_27_24_REG_RA93_VALID_SIZE 1 ++/* Bit: 'RA93_SPAN' */ ++/* Description: 'Span bit for 0180C2000003' */ ++#define AR9_RA_27_24_REG_RA93_SPAN_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA93_SPAN_SHIFT 30 ++#define AR9_RA_27_24_REG_RA93_SPAN_SIZE 1 ++/* Bit: 'RA93_MG' */ ++/* Description: 'Management bit for 0180C2000003' */ ++#define AR9_RA_27_24_REG_RA93_MG_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA93_MG_SHIFT 29 ++#define AR9_RA_27_24_REG_RA93_MG_SIZE 1 ++/* Bit: 'RA93_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000003' */ ++#define AR9_RA_27_24_REG_RA93_CV_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA93_CV_SHIFT 28 ++#define AR9_RA_27_24_REG_RA93_CV_SIZE 1 ++/* Bit: 'RA93_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000003' */ ++#define AR9_RA_27_24_REG_RA93_TXTAG_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA93_TXTAG_SHIFT 26 ++#define AR9_RA_27_24_REG_RA93_TXTAG_SIZE 2 ++/* Bit: 'RA93_ACT' */ ++/* Description: 'Action bit for 0180C2000003' */ ++#define AR9_RA_27_24_REG_RA93_ACT_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA93_ACT_SHIFT 24 ++#define AR9_RA_27_24_REG_RA93_ACT_SIZE 2 ++/* Bit: 'RA92_VALID' */ ++/* Description: 'Valid bit for 0180C2000002' */ ++#define AR9_RA_27_24_REG_RA92_VALID_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA92_VALID_SHIFT 23 ++#define AR9_RA_27_24_REG_RA92_VALID_SIZE 1 ++/* Bit: 'RA92_SPAN' */ ++/* Description: 'Span bit for 0180C2000002' */ ++#define AR9_RA_27_24_REG_RA92_SPAN_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA92_SPAN_SHIFT 22 ++#define AR9_RA_27_24_REG_RA92_SPAN_SIZE 1 ++/* Bit: 'RA92_MG' */ ++/* Description: 'Management bit for 0180C2000002' */ ++#define AR9_RA_27_24_REG_RA92_MG_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA92_MG_SHIFT 21 ++#define AR9_RA_27_24_REG_RA92_MG_SIZE 1 ++/* Bit: 'RA92_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000002' */ ++#define AR9_RA_27_24_REG_RA92_CV_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA92_CV_SHIFT 20 ++#define AR9_RA_27_24_REG_RA92_CV_SIZE 1 ++/* Bit: 'RA92_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000002' */ ++#define AR9_RA_27_24_REG_RA92_TXTAG_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA92_TXTAG_SHIFT 18 ++#define AR9_RA_27_24_REG_RA92_TXTAG_SIZE 2 ++/* Bit: 'RA92_ACT' */ ++/* Description: 'Action bit for 0180C2000002' */ ++#define AR9_RA_27_24_REG_RA92_ACT_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA92_ACT_SHIFT 16 ++#define AR9_RA_27_24_REG_RA92_ACT_SIZE 2 ++/* Bit: 'RA91_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define AR9_RA_27_24_REG_RA91_VALID_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA91_VALID_SHIFT 15 ++#define AR9_RA_27_24_REG_RA91_VALID_SIZE 1 ++/* Bit: 'RA91_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define AR9_RA_27_24_REG_RA91_SPAN_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA91_SPAN_SHIFT 14 ++#define AR9_RA_27_24_REG_RA91_SPAN_SIZE 1 ++/* Bit: 'RA91_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define AR9_RA_27_24_REG_RA91_MG_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA91_MG_SHIFT 13 ++#define AR9_RA_27_24_REG_RA91_MG_SIZE 1 ++/* Bit: 'RA91_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define AR9_RA_27_24_REG_RA91_CV_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA91_CV_SHIFT 12 ++#define AR9_RA_27_24_REG_RA91_CV_SIZE 1 ++/* Bit: 'RA91_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define AR9_RA_27_24_REG_RA91_TXTAG_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA91_TXTAG_SHIFT 10 ++#define AR9_RA_27_24_REG_RA91_TXTAG_SIZE 2 ++/* Bit: 'RA91_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define AR9_RA_27_24_REG_RA91_ACT_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA91_ACT_SHIFT 8 ++#define AR9_RA_27_24_REG_RA91_ACT_SIZE 2 ++/* Bit: 'RA90_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define AR9_RA_27_24_REG_RA90_VALID_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA90_VALID_SHIFT 7 ++#define AR9_RA_27_24_REG_RA90_VALID_SIZE 1 ++/* Bit: 'RA90_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define AR9_RA_27_24_REG_RA90_SPAN_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA90_SPAN_SHIFT 6 ++#define AR9_RA_27_24_REG_RA90_SPAN_SIZE 1 ++/* Bit: 'RA90_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define AR9_RA_27_24_REG_RA90_MG_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA90_MG_SHIFT 5 ++#define AR9_RA_27_24_REG_RA90_MG_SIZE 1 ++/* Bit: 'RA90_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define AR9_RA_27_24_REG_RA90_CV_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA90_CV_SHIFT 4 ++#define AR9_RA_27_24_REG_RA90_CV_SIZE 1 ++/* Bit: 'RA90_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define AR9_RA_27_24_REG_RA90_TXTAG_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA90_TXTAG_SHIFT 2 ++#define AR9_RA_27_24_REG_RA90_TXTAG_SIZE 2 ++/* Bit: 'RA90_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define AR9_RA_27_24_REG_RA90_ACT_OFFSET 0x01A4 ++#define AR9_RA_27_24_REG_RA90_ACT_SHIFT 0 ++#define AR9_RA_27_24_REG_RA90_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C200002B~0180C2000028' */ ++/* Bit: 'RA103_VALID' */ ++/* Description: 'Valid bit for 0180C2000003' */ ++#define AR9_RA_2B_28_REG_RA103_VALID_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA103_VALID_SHIFT 31 ++#define AR9_RA_2B_28_REG_RA103_VALID_SIZE 1 ++/* Bit: 'RA103_SPAN' */ ++/* Description: 'Span bit for 0180C2000003' */ ++#define AR9_RA_2B_28_REG_RA103_SPAN_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA103_SPAN_SHIFT 30 ++#define AR9_RA_2B_28_REG_RA103_SPAN_SIZE 1 ++/* Bit: 'RA103_MG' */ ++/* Description: 'Management bit for 0180C2000003' */ ++#define AR9_RA_2B_28_REG_RA103_MG_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA103_MG_SHIFT 29 ++#define AR9_RA_2B_28_REG_RA103_MG_SIZE 1 ++/* Bit: 'RA103_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000003' */ ++#define AR9_RA_2B_28_REG_RA103_CV_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA103_CV_SHIFT 28 ++#define AR9_RA_2B_28_REG_RA103_CV_SIZE 1 ++/* Bit: 'RA103_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000003' */ ++#define AR9_RA_2B_28_REG_RA103_TXTAG_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA103_TXTAG_SHIFT 26 ++#define AR9_RA_2B_28_REG_RA103_TXTAG_SIZE 2 ++/* Bit: 'RA103_ACT' */ ++/* Description: 'Action bit for 0180C2000003' */ ++#define AR9_RA_2B_28_REG_RA103_ACT_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA103_ACT_SHIFT 24 ++#define AR9_RA_2B_28_REG_RA103_ACT_SIZE 2 ++/* Bit: 'RA102_VALID' */ ++/* Description: 'Valid bit for 0180C2000002' */ ++#define AR9_RA_2B_28_REG_RA102_VALID_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA102_VALID_SHIFT 23 ++#define AR9_RA_2B_28_REG_RA102_VALID_SIZE 1 ++/* Bit: 'RA102_SPAN' */ ++/* Description: 'Span bit for 0180C2000002' */ ++#define AR9_RA_2B_28_REG_RA102_SPAN_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA102_SPAN_SHIFT 22 ++#define AR9_RA_2B_28_REG_RA102_SPAN_SIZE 1 ++/* Bit: 'RA102_MG' */ ++/* Description: 'Management bit for 0180C2000002' */ ++#define AR9_RA_2B_28_REG_RA102_MG_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA102_MG_SHIFT 21 ++#define AR9_RA_2B_28_REG_RA102_MG_SIZE 1 ++/* Bit: 'RA102_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000002' */ ++#define AR9_RA_2B_28_REG_RA102_CV_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA102_CV_SHIFT 20 ++#define AR9_RA_2B_28_REG_RA102_CV_SIZE 1 ++/* Bit: 'RA102_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000002' */ ++#define AR9_RA_2B_28_REG_RA102_TXTAG_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA102_TXTAG_SHIFT 18 ++#define AR9_RA_2B_28_REG_RA102_TXTAG_SIZE 2 ++/* Bit: 'RA102_ACT' */ ++/* Description: 'Action bit for 0180C2000002' */ ++#define AR9_RA_2B_28_REG_RA102_ACT_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA102_ACT_SHIFT 16 ++#define AR9_RA_2B_28_REG_RA102_ACT_SIZE 2 ++/* Bit: 'RA101_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define AR9_RA_2B_28_REG_RA101_VALID_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA101_VALID_SHIFT 15 ++#define AR9_RA_2B_28_REG_RA101_VALID_SIZE 1 ++/* Bit: 'RA101_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define AR9_RA_2B_28_REG_RA101_SPAN_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA101_SPAN_SHIFT 14 ++#define AR9_RA_2B_28_REG_RA101_SPAN_SIZE 1 ++/* Bit: 'RA101_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define AR9_RA_2B_28_REG_RA101_MG_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA101_MG_SHIFT 13 ++#define AR9_RA_2B_28_REG_RA101_MG_SIZE 1 ++/* Bit: 'RA101_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define AR9_RA_2B_28_REG_RA101_CV_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA101_CV_SHIFT 12 ++#define AR9_RA_2B_28_REG_RA101_CV_SIZE 1 ++/* Bit: 'RA101_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define AR9_RA_2B_28_REG_RA101_TXTAG_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA101_TXTAG_SHIFT 10 ++#define AR9_RA_2B_28_REG_RA101_TXTAG_SIZE 2 ++/* Bit: 'RA101_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define AR9_RA_2B_28_REG_RA101_ACT_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA101_ACT_SHIFT 8 ++#define AR9_RA_2B_28_REG_RA101_ACT_SIZE 2 ++/* Bit: 'RA100_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define AR9_RA_2B_28_REG_RA100_VALID_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA100_VALID_SHIFT 7 ++#define AR9_RA_2B_28_REG_RA100_VALID_SIZE 1 ++/* Bit: 'RA100_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define AR9_RA_2B_28_REG_RA100_SPAN_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA100_SPAN_SHIFT 6 ++#define AR9_RA_2B_28_REG_RA100_SPAN_SIZE 1 ++/* Bit: 'RA100_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define AR9_RA_2B_28_REG_RA100_MG_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA100_MG_SHIFT 5 ++#define AR9_RA_2B_28_REG_RA100_MG_SIZE 1 ++/* Bit: 'RA100_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define AR9_RA_2B_28_REG_RA100_CV_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA100_CV_SHIFT 4 ++#define AR9_RA_2B_28_REG_RA100_CV_SIZE 1 ++/* Bit: 'RA100_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define AR9_RA_2B_28_REG_RA100_TXTAG_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA100_TXTAG_SHIFT 2 ++#define AR9_RA_2B_28_REG_RA100_TXTAG_SIZE 2 ++/* Bit: 'RA100_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define AR9_RA_2B_28_REG_RA100_ACT_OFFSET 0x01A8 ++#define AR9_RA_2B_28_REG_RA100_ACT_SHIFT 0 ++#define AR9_RA_2B_28_REG_RA100_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C200002F~0180C200002C' */ ++/* Bit: 'RA113_VALID' */ ++/* Description: 'Valid bit for 0180C2000003' */ ++#define AR9_RA_2F_2C_REG_RA113_VALID_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA113_VALID_SHIFT 31 ++#define AR9_RA_2F_2C_REG_RA113_VALID_SIZE 1 ++/* Bit: 'RA113_SPAN' */ ++/* Description: 'Span bit for 0180C2000003' */ ++#define AR9_RA_2F_2C_REG_RA113_SPAN_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA113_SPAN_SHIFT 30 ++#define AR9_RA_2F_2C_REG_RA113_SPAN_SIZE 1 ++/* Bit: 'RA113_MG' */ ++/* Description: 'Management bit for 0180C2000003' */ ++#define AR9_RA_2F_2C_REG_RA113_MG_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA113_MG_SHIFT 29 ++#define AR9_RA_2F_2C_REG_RA113_MG_SIZE 1 ++/* Bit: 'RA113_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000003' */ ++#define AR9_RA_2F_2C_REG_RA113_CV_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA113_CV_SHIFT 28 ++#define AR9_RA_2F_2C_REG_RA113_CV_SIZE 1 ++/* Bit: 'RA113_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000003' */ ++#define AR9_RA_2F_2C_REG_RA113_TXTAG_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA113_TXTAG_SHIFT 26 ++#define AR9_RA_2F_2C_REG_RA113_TXTAG_SIZE 2 ++/* Bit: 'RA113_ACT' */ ++/* Description: 'Action bit for 0180C2000003' */ ++#define AR9_RA_2F_2C_REG_RA113_ACT_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA113_ACT_SHIFT 24 ++#define AR9_RA_2F_2C_REG_RA113_ACT_SIZE 2 ++/* Bit: 'RA112_VALID' */ ++/* Description: 'Valid bit for 0180C2000002' */ ++#define AR9_RA_2F_2C_REG_RA112_VALID_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA112_VALID_SHIFT 23 ++#define AR9_RA_2F_2C_REG_RA112_VALID_SIZE 1 ++/* Bit: 'RA112_SPAN' */ ++/* Description: 'Span bit for 0180C2000002' */ ++#define AR9_RA_2F_2C_REG_RA112_SPAN_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA112_SPAN_SHIFT 22 ++#define AR9_RA_2F_2C_REG_RA112_SPAN_SIZE 1 ++/* Bit: 'RA112_MG' */ ++/* Description: 'Management bit for 0180C2000002' */ ++#define AR9_RA_2F_2C_REG_RA112_MG_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA112_MG_SHIFT 21 ++#define AR9_RA_2F_2C_REG_RA112_MG_SIZE 1 ++/* Bit: 'RA112_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000002' */ ++#define AR9_RA_2F_2C_REG_RA112_CV_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA112_CV_SHIFT 20 ++#define AR9_RA_2F_2C_REG_RA112_CV_SIZE 1 ++/* Bit: 'RA112_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000002' */ ++#define AR9_RA_2F_2C_REG_RA112_TXTAG_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA112_TXTAG_SHIFT 18 ++#define AR9_RA_2F_2C_REG_RA112_TXTAG_SIZE 2 ++/* Bit: 'RA112_ACT' */ ++/* Description: 'Action bit for 0180C2000002' */ ++#define AR9_RA_2F_2C_REG_RA112_ACT_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA112_ACT_SHIFT 16 ++#define AR9_RA_2F_2C_REG_RA112_ACT_SIZE 2 ++/* Bit: 'RA111_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define AR9_RA_2F_2C_REG_RA111_VALID_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA111_VALID_SHIFT 15 ++#define AR9_RA_2F_2C_REG_RA111_VALID_SIZE 1 ++/* Bit: 'RA111_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define AR9_RA_2F_2C_REG_RA111_SPAN_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA111_SPAN_SHIFT 14 ++#define AR9_RA_2F_2C_REG_RA111_SPAN_SIZE 1 ++/* Bit: 'RA111_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define AR9_RA_2F_2C_REG_RA111_MG_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA111_MG_SHIFT 13 ++#define AR9_RA_2F_2C_REG_RA111_MG_SIZE 1 ++/* Bit: 'RA111_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define AR9_RA_2F_2C_REG_RA111_CV_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA111_CV_SHIFT 12 ++#define AR9_RA_2F_2C_REG_RA111_CV_SIZE 1 ++/* Bit: 'RA111_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define AR9_RA_2F_2C_REG_RA111_TXTAG_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA111_TXTAG_SHIFT 10 ++#define AR9_RA_2F_2C_REG_RA111_TXTAG_SIZE 2 ++/* Bit: 'RA111_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define AR9_RA_2F_2C_REG_RA111_ACT_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA111_ACT_SHIFT 8 ++#define AR9_RA_2F_2C_REG_RA111_ACT_SIZE 2 ++/* Bit: 'RA110_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define AR9_RA_2F_2C_REG_RA110_VALID_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA110_VALID_SHIFT 7 ++#define AR9_RA_2F_2C_REG_RA110_VALID_SIZE 1 ++/* Bit: 'RA110_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define AR9_RA_2F_2C_REG_RA110_SPAN_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA110_SPAN_SHIFT 6 ++#define AR9_RA_2F_2C_REG_RA110_SPAN_SIZE 1 ++/* Bit: 'RA110_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define AR9_RA_2F_2C_REG_RA110_MG_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA110_MG_SHIFT 5 ++#define AR9_RA_2F_2C_REG_RA110_MG_SIZE 1 ++/* Bit: 'RA110_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define AR9_RA_2F_2C_REG_RA110_CV_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA110_CV_SHIFT 4 ++#define AR9_RA_2F_2C_REG_RA110_CV_SIZE 1 ++/* Bit: 'RA110_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define AR9_RA_2F_2C_REG_RA110_TXTAG_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA110_TXTAG_SHIFT 2 ++#define AR9_RA_2F_2C_REG_RA110_TXTAG_SIZE 2 ++/* Bit: 'RA110_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define AR9_RA_2F_2C_REG_RA110_ACT_OFFSET 0x01AC ++#define AR9_RA_2F_2C_REG_RA110_ACT_SHIFT 0 ++#define AR9_RA_2F_2C_REG_RA110_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Protocol Filter 0' */ ++/* Bit: 'PFR3' */ ++/* Description: 'Value Compared with Protocol in IP Header' */ ++#define AR9_PRTCL_F0_REG_PFR3_OFFSET 0x01B0 ++#define AR9_PRTCL_F0_REG_PFR3_SHIFT 24 ++#define AR9_PRTCL_F0_REG_PFR3_SIZE 8 ++/* Bit: 'PFR2' */ ++/* Description: 'Value Compared with Protocol in IP Header' */ ++#define AR9_PRTCL_F0_REG_PFR2_OFFSET 0x01B0 ++#define AR9_PRTCL_F0_REG_PFR2_SHIFT 16 ++#define AR9_PRTCL_F0_REG_PFR2_SIZE 8 ++/* Bit: 'PFR1' */ ++/* Description: 'Value Compared with Protocol in IP Header' */ ++#define AR9_PRTCL_F0_REG_PFR1_OFFSET 0x01B0 ++#define AR9_PRTCL_F0_REG_PFR1_SHIFT 8 ++#define AR9_PRTCL_F0_REG_PFR1_SIZE 8 ++/* Bit: 'PFR0' */ ++/* Description: 'Value Compared with Protocol in IP Header' */ ++#define AR9_PRTCL_F0_REG_PFR0_OFFSET 0x01B0 ++#define AR9_PRTCL_F0_REG_PFR0_SHIFT 0 ++#define AR9_PRTCL_F0_REG_PFR0_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Protocol Filter 1' */ ++/* Bit: 'PFR3' */ ++/* Description: 'Value Compared with Protocol in IP Header' */ ++#define AR9_PRTCL_F1_REG_PFR3_OFFSET 0x01B4 ++#define AR9_PRTCL_F1_REG_PFR3_SHIFT 24 ++#define AR9_PRTCL_F1_REG_PFR3_SIZE 8 ++/* Bit: 'PFR2' */ ++/* Description: 'Value Compared with Protocol in IP Header' */ ++#define AR9_PRTCL_F1_REG_PFR2_OFFSET 0x01B4 ++#define AR9_PRTCL_F1_REG_PFR2_SHIFT 16 ++#define AR9_PRTCL_F1_REG_PFR2_SIZE 8 ++/* Bit: 'PFR1' */ ++/* Description: 'Value Compared with Protocol in IP Header' */ ++#define AR9_PRTCL_F1_REG_PFR1_OFFSET 0x01B4 ++#define AR9_PRTCL_F1_REG_PFR1_SHIFT 8 ++#define AR9_PRTCL_F1_REG_PFR1_SIZE 8 ++/* Bit: 'PFR0' */ ++/* Description: 'Value Compared with Protocol in IP Header' */ ++#define AR9_PRTCL_F1_REG_PFR0_OFFSET 0x01B4 ++#define AR9_PRTCL_F1_REG_PFR0_SHIFT 0 ++#define AR9_PRTCL_F1_REG_PFR0_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++#endif /* #ifndef _AR9_H */ +diff --git a/include/switch_api/Tantos3G.h b/include/switch_api/Tantos3G.h +new file mode 100644 +index 0000000..04cb62f +--- /dev/null ++++ b/include/switch_api/Tantos3G.h +@@ -0,0 +1,5882 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++ ++#ifndef _TANTOS3G_H ++#define _TANTOS3G_H ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 0 Status Register' */ ++/* Bit: 'P0FCS' */ ++/* Description: 'Port 0 Flow Control Status' */ ++#define TANTOS_3G_P0S_P0FCS_OFFSET 0x00 ++#define TANTOS_3G_P0S_P0FCS_SHIFT 4 ++#define TANTOS_3G_P0S_P0FCS_SIZE 1 ++/* Bit: 'P0DS' */ ++/* Description: 'Port 0 Duplex Status' */ ++#define TANTOS_3G_P0S_P0DS_OFFSET 0x00 ++#define TANTOS_3G_P0S_P0DS_SHIFT 3 ++#define TANTOS_3G_P0S_P0DS_SIZE 1 ++/* Bit: 'P0SHS' */ ++/* Description: 'Port 0 Speed High Status' */ ++#define TANTOS_3G_P0S_P0SHS_OFFSET 0x00 ++#define TANTOS_3G_P0S_P0SHS_SHIFT 2 ++#define TANTOS_3G_P0S_P0SHS_SIZE 1 ++/* Bit: 'P0SS' */ ++/* Description: 'Port 0 Speed Status' */ ++#define TANTOS_3G_P0S_P0SS_OFFSET 0x00 ++#define TANTOS_3G_P0S_P0SS_SHIFT 1 ++#define TANTOS_3G_P0S_P0SS_SIZE 1 ++/* Bit: 'P0LS' */ ++/* Description: 'Port 0 Link Status' */ ++#define TANTOS_3G_P0S_P0LS_OFFSET 0x00 ++#define TANTOS_3G_P0S_P0LS_SHIFT 0 ++#define TANTOS_3G_P0S_P0LS_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 1 Status Register' */ ++/* Bit: 'P1FCS' */ ++/* Description: 'Port 1 Flow Control Status' */ ++#define TANTOS_3G_P1S_P1FCS_OFFSET 0x20 ++#define TANTOS_3G_P1S_P1FCS_SHIFT 4 ++#define TANTOS_3G_P1S_P1FCS_SIZE 1 ++/* Bit: 'P1DS' */ ++/* Description: 'Port 1 Duplex Status' */ ++#define TANTOS_3G_P1S_P1DS_OFFSET 0x20 ++#define TANTOS_3G_P1S_P1DS_SHIFT 3 ++#define TANTOS_3G_P1S_P1DS_SIZE 1 ++/* Bit: 'P1SHS' */ ++/* Description: 'Port 1 Speed High Status' */ ++#define TANTOS_3G_P1S_P1SHS_OFFSET 0x20 ++#define TANTOS_3G_P1S_P1SHS_SHIFT 2 ++#define TANTOS_3G_P1S_P1SHS_SIZE 1 ++/* Bit: 'P1SS' */ ++/* Description: 'Port 1 Speed Status' */ ++#define TANTOS_3G_P1S_P1SS_OFFSET 0x20 ++#define TANTOS_3G_P1S_P1SS_SHIFT 1 ++#define TANTOS_3G_P1S_P1SS_SIZE 1 ++/* Bit: 'P1LS' */ ++/* Description: 'Port 1 Link Status' */ ++#define TANTOS_3G_P1S_P1LS_OFFSET 0x20 ++#define TANTOS_3G_P1S_P1LS_SHIFT 0 ++#define TANTOS_3G_P1S_P1LS_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 2 Status Register' */ ++/* Bit: 'P2FCS' */ ++/* Description: 'Port 2 Flow Control Status' */ ++#define TANTOS_3G_P2S_P2FCS_OFFSET 0x40 ++#define TANTOS_3G_P2S_P2FCS_SHIFT 4 ++#define TANTOS_3G_P2S_P2FCS_SIZE 1 ++/* Bit: 'P2DS' */ ++/* Description: 'Port 2 Duplex Status' */ ++#define TANTOS_3G_P2S_P2DS_OFFSET 0x40 ++#define TANTOS_3G_P2S_P2DS_SHIFT 3 ++#define TANTOS_3G_P2S_P2DS_SIZE 1 ++/* Bit: 'P2SHS' */ ++/* Description: 'Port 2 Speed High Status' */ ++#define TANTOS_3G_P2S_P2SHS_OFFSET 0x40 ++#define TANTOS_3G_P2S_P2SHS_SHIFT 2 ++#define TANTOS_3G_P2S_P2SHS_SIZE 1 ++/* Bit: 'P2SS' */ ++/* Description: 'Port 2 Speed Status' */ ++#define TANTOS_3G_P2S_P2SS_OFFSET 0x40 ++#define TANTOS_3G_P2S_P2SS_SHIFT 1 ++#define TANTOS_3G_P2S_P2SS_SIZE 1 ++/* Bit: 'P2LS' */ ++/* Description: 'Port 2 Link Status' */ ++#define TANTOS_3G_P2S_P2LS_OFFSET 0x40 ++#define TANTOS_3G_P2S_P2LS_SHIFT 0 ++#define TANTOS_3G_P2S_P2LS_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 3 Status Register' */ ++/* Bit: 'P3FCS' */ ++/* Description: 'Port 3 Flow Control Status' */ ++#define TANTOS_3G_P3S_P3FCS_OFFSET 0x60 ++#define TANTOS_3G_P3S_P3FCS_SHIFT 4 ++#define TANTOS_3G_P3S_P3FCS_SIZE 1 ++/* Bit: 'P3DS' */ ++/* Description: 'Port 3 Duplex Status' */ ++#define TANTOS_3G_P3S_P3DS_OFFSET 0x60 ++#define TANTOS_3G_P3S_P3DS_SHIFT 3 ++#define TANTOS_3G_P3S_P3DS_SIZE 1 ++/* Bit: 'P3SHS' */ ++/* Description: 'Port 3 Speed High Status' */ ++#define TANTOS_3G_P3S_P3SHS_OFFSET 0x60 ++#define TANTOS_3G_P3S_P3SHS_SHIFT 2 ++#define TANTOS_3G_P3S_P3SHS_SIZE 1 ++/* Bit: 'P3SS' */ ++/* Description: 'Port 3 Speed Status' */ ++#define TANTOS_3G_P3S_P3SS_OFFSET 0x60 ++#define TANTOS_3G_P3S_P3SS_SHIFT 1 ++#define TANTOS_3G_P3S_P3SS_SIZE 1 ++/* Bit: 'P3LS' */ ++/* Description: 'Port 3 Link Status' */ ++#define TANTOS_3G_P3S_P3LS_OFFSET 0x60 ++#define TANTOS_3G_P3S_P3LS_SHIFT 0 ++#define TANTOS_3G_P3S_P3LS_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 4 Status Register' */ ++/* Bit: 'P4FCS' */ ++/* Description: 'Port 4 Flow Control Status' */ ++#define TANTOS_3G_P4S_P4FCS_OFFSET 0x80 ++#define TANTOS_3G_P4S_P4FCS_SHIFT 4 ++#define TANTOS_3G_P4S_P4FCS_SIZE 1 ++/* Bit: 'P4DS' */ ++/* Description: 'Port 4 Duplex Status' */ ++#define TANTOS_3G_P4S_P4DS_OFFSET 0x80 ++#define TANTOS_3G_P4S_P4DS_SHIFT 3 ++#define TANTOS_3G_P4S_P4DS_SIZE 1 ++/* Bit: 'P4SHS' */ ++/* Description: 'Port 4 Speed High Status' */ ++#define TANTOS_3G_P4S_P4SHS_OFFSET 0x80 ++#define TANTOS_3G_P4S_P4SHS_SHIFT 2 ++#define TANTOS_3G_P4S_P4SHS_SIZE 1 ++/* Bit: 'P4SS' */ ++/* Description: 'Port 4 Speed Status' */ ++#define TANTOS_3G_P4S_P4SS_OFFSET 0x80 ++#define TANTOS_3G_P4S_P4SS_SHIFT 1 ++#define TANTOS_3G_P4S_P4SS_SIZE 1 ++/* Bit: 'P4LS' */ ++/* Description: 'Port 4 Link Status' */ ++#define TANTOS_3G_P4S_P4LS_OFFSET 0x80 ++#define TANTOS_3G_P4S_P4LS_SHIFT 0 ++#define TANTOS_3G_P4S_P4LS_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 5 Status Register' */ ++/* Bit: 'P5FCS' */ ++/* Description: 'Port 5 Flow Control Status' */ ++#define TANTOS_3G_P5S_P5FCS_OFFSET 0xA0 ++#define TANTOS_3G_P5S_P5FCS_SHIFT 4 ++#define TANTOS_3G_P5S_P5FCS_SIZE 1 ++/* Bit: 'P5DS' */ ++/* Description: 'Port 5 Duplex Status' */ ++#define TANTOS_3G_P5S_P5DS_OFFSET 0xA0 ++#define TANTOS_3G_P5S_P5DS_SHIFT 3 ++#define TANTOS_3G_P5S_P5DS_SIZE 1 ++/* Bit: 'P5SHS' */ ++/* Description: 'Port 5 Speed High Status' */ ++#define TANTOS_3G_P5S_P5SHS_OFFSET 0xA0 ++#define TANTOS_3G_P5S_P5SHS_SHIFT 2 ++#define TANTOS_3G_P5S_P5SHS_SIZE 1 ++/* Bit: 'P5SS' */ ++/* Description: 'Port 5 Speed Status' */ ++#define TANTOS_3G_P5S_P5SS_OFFSET 0xA0 ++#define TANTOS_3G_P5S_P5SS_SHIFT 1 ++#define TANTOS_3G_P5S_P5SS_SIZE 1 ++/* Bit: 'P5LS' */ ++/* Description: 'Port 5 Link Status' */ ++#define TANTOS_3G_P5S_P5LS_OFFSET 0xA0 ++#define TANTOS_3G_P5S_P5LS_SHIFT 0 ++#define TANTOS_3G_P5S_P5LS_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 6 Status Register' */ ++/* Bit: 'P6FCS' */ ++/* Description: 'Port 6 Flow Control Status' */ ++#define TANTOS_3G_P6S_P6FCS_OFFSET 0xC0 ++#define TANTOS_3G_P6S_P6FCS_SHIFT 4 ++#define TANTOS_3G_P6S_P6FCS_SIZE 1 ++/* Bit: 'P6DS' */ ++/* Description: 'Port 6 Duplex Status' */ ++#define TANTOS_3G_P6S_P6DS_OFFSET 0xC0 ++#define TANTOS_3G_P6S_P6DS_SHIFT 3 ++#define TANTOS_3G_P6S_P6DS_SIZE 1 ++/* Bit: 'P6SHS' */ ++/* Description: 'Port 6 Speed High Status' */ ++#define TANTOS_3G_P6S_P6SHS_OFFSET 0xC0 ++#define TANTOS_3G_P6S_P6SHS_SHIFT 2 ++#define TANTOS_3G_P6S_P6SHS_SIZE 1 ++/* Bit: 'P6SS' */ ++/* Description: 'Port 6 Speed Status' */ ++#define TANTOS_3G_P6S_P6SS_OFFSET 0xC0 ++#define TANTOS_3G_P6S_P6SS_SHIFT 1 ++#define TANTOS_3G_P6S_P6SS_SIZE 1 ++/* Bit: 'P6LS' */ ++/* Description: 'Port 6 Link Status' */ ++#define TANTOS_3G_P6S_P6LS_OFFSET 0xC0 ++#define TANTOS_3G_P6S_P6LS_SHIFT 0 ++#define TANTOS_3G_P6S_P6LS_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'P0 Basic Control Register' */ ++/* Bit: 'SPS' */ ++/* Description: 'STP/RSTP port state' */ ++#define TANTOS_3G_P0BC_SPS_OFFSET 0x01 ++#define TANTOS_3G_P0BC_SPS_SHIFT 14 ++#define TANTOS_3G_P0BC_SPS_SIZE 2 ++/* Bit: 'TCPE' */ ++/* Description: 'TCP/UDP PRIEN' */ ++#define TANTOS_3G_P0BC_TCPE_OFFSET 0x01 ++#define TANTOS_3G_P0BC_TCPE_SHIFT 13 ++#define TANTOS_3G_P0BC_TCPE_SIZE 1 ++/* Bit: 'IPOVTU' */ ++/* Description: ' IP over TCP/UDP' */ ++#define TANTOS_3G_P0BC_IPOVTU_OFFSET 0x01 ++#define TANTOS_3G_P0BC_IPOVTU_SHIFT 12 ++#define TANTOS_3G_P0BC_IPOVTU_SIZE 1 ++/* Bit: 'VPE' */ ++/* Description: 'VLAN Priority Enable' */ ++#define TANTOS_3G_P0BC_VPE_OFFSET 0x01 ++#define TANTOS_3G_P0BC_VPE_SHIFT 11 ++#define TANTOS_3G_P0BC_VPE_SIZE 1 ++/* Bit: 'SPE' */ ++/* Description: 'Service Priority Enable' */ ++#define TANTOS_3G_P0BC_SPE_OFFSET 0x01 ++#define TANTOS_3G_P0BC_SPE_SHIFT 10 ++#define TANTOS_3G_P0BC_SPE_SIZE 1 ++/* Bit: 'IPVLAN' */ ++/* Description: 'IP over VLAN PRI' */ ++#define TANTOS_3G_P0BC_IPVLAN_OFFSET 0x01 ++#define TANTOS_3G_P0BC_IPVLAN_SHIFT 9 ++#define TANTOS_3G_P0BC_IPVLAN_SIZE 1 ++/* Bit: 'TPE' */ ++/* Description: 'Ether Type Priority Enable' */ ++#define TANTOS_3G_P0BC_TPE_OFFSET 0x01 ++#define TANTOS_3G_P0BC_TPE_SHIFT 8 ++#define TANTOS_3G_P0BC_TPE_SIZE 1 ++/* Bit: 'FLP' */ ++/* Description: 'Force Link Up' */ ++#define TANTOS_3G_P0BC_FLP_OFFSET 0x01 ++#define TANTOS_3G_P0BC_FLP_SHIFT 2 ++#define TANTOS_3G_P0BC_FLP_SIZE 1 ++/* Bit: 'FLD' */ ++/* Description: 'Force Link Down' */ ++#define TANTOS_3G_P0BC_FLD_OFFSET 0x01 ++#define TANTOS_3G_P0BC_FLD_SHIFT 1 ++#define TANTOS_3G_P0BC_FLD_SIZE 1 ++/* Bit: 'RMWFQ' */ ++/* Description: 'Ratio Mode for WFQ' */ ++#define TANTOS_3G_P0BC_RMWFQ_OFFSET 0x01 ++#define TANTOS_3G_P0BC_RMWFQ_SHIFT 0 ++#define TANTOS_3G_P0BC_RMWFQ_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'P1 Basic Control Register' */ ++/* Bit: 'SPS' */ ++/* Description: 'STP/RSTP port state' */ ++#define TANTOS_3G_P1BC_SPS_OFFSET 0x21 ++#define TANTOS_3G_P1BC_SPS_SHIFT 14 ++#define TANTOS_3G_P1BC_SPS_SIZE 2 ++/* Bit: 'TCPE' */ ++/* Description: 'TCP/UDP PRIEN' */ ++#define TANTOS_3G_P1BC_TCPE_OFFSET 0x21 ++#define TANTOS_3G_P1BC_TCPE_SHIFT 13 ++#define TANTOS_3G_P1BC_TCPE_SIZE 1 ++/* Bit: 'IPOVTU' */ ++/* Description: ' IP over TCP/UDP' */ ++#define TANTOS_3G_P1BC_IPOVTU_OFFSET 0x21 ++#define TANTOS_3G_P1BC_IPOVTU_SHIFT 12 ++#define TANTOS_3G_P1BC_IPOVTU_SIZE 1 ++/* Bit: 'VPE' */ ++/* Description: 'VLAN Priority Enable' */ ++#define TANTOS_3G_P1BC_VPE_OFFSET 0x21 ++#define TANTOS_3G_P1BC_VPE_SHIFT 11 ++#define TANTOS_3G_P1BC_VPE_SIZE 1 ++/* Bit: 'SPE' */ ++/* Description: 'Service Priority Enable' */ ++#define TANTOS_3G_P1BC_SPE_OFFSET 0x21 ++#define TANTOS_3G_P1BC_SPE_SHIFT 10 ++#define TANTOS_3G_P1BC_SPE_SIZE 1 ++/* Bit: 'IPVLAN' */ ++/* Description: 'IP over VLAN PRI' */ ++#define TANTOS_3G_P1BC_IPVLAN_OFFSET 0x21 ++#define TANTOS_3G_P1BC_IPVLAN_SHIFT 9 ++#define TANTOS_3G_P1BC_IPVLAN_SIZE 1 ++/* Bit: 'TPE' */ ++/* Description: 'Ether Type Priority Enable' */ ++#define TANTOS_3G_P1BC_TPE_OFFSET 0x21 ++#define TANTOS_3G_P1BC_TPE_SHIFT 8 ++#define TANTOS_3G_P1BC_TPE_SIZE 1 ++/* Bit: 'FLP' */ ++/* Description: 'Force Link Up' */ ++#define TANTOS_3G_P1BC_FLP_OFFSET 0x21 ++#define TANTOS_3G_P1BC_FLP_SHIFT 2 ++#define TANTOS_3G_P1BC_FLP_SIZE 1 ++/* Bit: 'FLD' */ ++/* Description: 'Force Link Down' */ ++#define TANTOS_3G_P1BC_FLD_OFFSET 0x21 ++#define TANTOS_3G_P1BC_FLD_SHIFT 1 ++#define TANTOS_3G_P1BC_FLD_SIZE 1 ++/* Bit: 'RMWFQ' */ ++/* Description: 'Ratio Mode for WFQ' */ ++#define TANTOS_3G_P1BC_RMWFQ_OFFSET 0x21 ++#define TANTOS_3G_P1BC_RMWFQ_SHIFT 0 ++#define TANTOS_3G_P1BC_RMWFQ_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'P2 Basic Control Register' */ ++/* Bit: 'SPS' */ ++/* Description: 'STP/RSTP port state' */ ++#define TANTOS_3G_P2BC_SPS_OFFSET 0x41 ++#define TANTOS_3G_P2BC_SPS_SHIFT 14 ++#define TANTOS_3G_P2BC_SPS_SIZE 2 ++/* Bit: 'TCPE' */ ++/* Description: 'TCP/UDP PRIEN' */ ++#define TANTOS_3G_P2BC_TCPE_OFFSET 0x41 ++#define TANTOS_3G_P2BC_TCPE_SHIFT 13 ++#define TANTOS_3G_P2BC_TCPE_SIZE 1 ++/* Bit: 'IPOVTU' */ ++/* Description: ' IP over TCP/UDP' */ ++#define TANTOS_3G_P2BC_IPOVTU_OFFSET 0x41 ++#define TANTOS_3G_P2BC_IPOVTU_SHIFT 12 ++#define TANTOS_3G_P2BC_IPOVTU_SIZE 1 ++/* Bit: 'VPE' */ ++/* Description: 'VLAN Priority Enable' */ ++#define TANTOS_3G_P2BC_VPE_OFFSET 0x41 ++#define TANTOS_3G_P2BC_VPE_SHIFT 11 ++#define TANTOS_3G_P2BC_VPE_SIZE 1 ++/* Bit: 'SPE' */ ++/* Description: 'Service Priority Enable' */ ++#define TANTOS_3G_P2BC_SPE_OFFSET 0x41 ++#define TANTOS_3G_P2BC_SPE_SHIFT 10 ++#define TANTOS_3G_P2BC_SPE_SIZE 1 ++/* Bit: 'IPVLAN' */ ++/* Description: 'IP over VLAN PRI' */ ++#define TANTOS_3G_P2BC_IPVLAN_OFFSET 0x41 ++#define TANTOS_3G_P2BC_IPVLAN_SHIFT 9 ++#define TANTOS_3G_P2BC_IPVLAN_SIZE 1 ++/* Bit: 'TPE' */ ++/* Description: 'Ether Type Priority Enable' */ ++#define TANTOS_3G_P2BC_TPE_OFFSET 0x41 ++#define TANTOS_3G_P2BC_TPE_SHIFT 8 ++#define TANTOS_3G_P2BC_TPE_SIZE 1 ++/* Bit: 'FLP' */ ++/* Description: 'Force Link Up' */ ++#define TANTOS_3G_P2BC_FLP_OFFSET 0x41 ++#define TANTOS_3G_P2BC_FLP_SHIFT 2 ++#define TANTOS_3G_P2BC_FLP_SIZE 1 ++/* Bit: 'FLD' */ ++/* Description: 'Force Link Down' */ ++#define TANTOS_3G_P2BC_FLD_OFFSET 0x41 ++#define TANTOS_3G_P2BC_FLD_SHIFT 1 ++#define TANTOS_3G_P2BC_FLD_SIZE 1 ++/* Bit: 'RMWFQ' */ ++/* Description: 'Ratio Mode for WFQ' */ ++#define TANTOS_3G_P2BC_RMWFQ_OFFSET 0x41 ++#define TANTOS_3G_P2BC_RMWFQ_SHIFT 0 ++#define TANTOS_3G_P2BC_RMWFQ_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'P3 Basic Control Register' */ ++/* Bit: 'SPS' */ ++/* Description: 'STP/RSTP port state' */ ++#define TANTOS_3G_P3BC_SPS_OFFSET 0x61 ++#define TANTOS_3G_P3BC_SPS_SHIFT 14 ++#define TANTOS_3G_P3BC_SPS_SIZE 2 ++/* Bit: 'TCPE' */ ++/* Description: 'TCP/UDP PRIEN' */ ++#define TANTOS_3G_P3BC_TCPE_OFFSET 0x61 ++#define TANTOS_3G_P3BC_TCPE_SHIFT 13 ++#define TANTOS_3G_P3BC_TCPE_SIZE 1 ++/* Bit: 'IPOVTU' */ ++/* Description: ' IP over TCP/UDP' */ ++#define TANTOS_3G_P3BC_IPOVTU_OFFSET 0x61 ++#define TANTOS_3G_P3BC_IPOVTU_SHIFT 12 ++#define TANTOS_3G_P3BC_IPOVTU_SIZE 1 ++/* Bit: 'VPE' */ ++/* Description: 'VLAN Priority Enable' */ ++#define TANTOS_3G_P3BC_VPE_OFFSET 0x61 ++#define TANTOS_3G_P3BC_VPE_SHIFT 11 ++#define TANTOS_3G_P3BC_VPE_SIZE 1 ++/* Bit: 'SPE' */ ++/* Description: 'Service Priority Enable' */ ++#define TANTOS_3G_P3BC_SPE_OFFSET 0x61 ++#define TANTOS_3G_P3BC_SPE_SHIFT 10 ++#define TANTOS_3G_P3BC_SPE_SIZE 1 ++/* Bit: 'IPVLAN' */ ++/* Description: 'IP over VLAN PRI' */ ++#define TANTOS_3G_P3BC_IPVLAN_OFFSET 0x61 ++#define TANTOS_3G_P3BC_IPVLAN_SHIFT 9 ++#define TANTOS_3G_P3BC_IPVLAN_SIZE 1 ++/* Bit: 'TPE' */ ++/* Description: 'Ether Type Priority Enable' */ ++#define TANTOS_3G_P3BC_TPE_OFFSET 0x61 ++#define TANTOS_3G_P3BC_TPE_SHIFT 8 ++#define TANTOS_3G_P3BC_TPE_SIZE 1 ++/* Bit: 'FLP' */ ++/* Description: 'Force Link Up' */ ++#define TANTOS_3G_P3BC_FLP_OFFSET 0x61 ++#define TANTOS_3G_P3BC_FLP_SHIFT 2 ++#define TANTOS_3G_P3BC_FLP_SIZE 1 ++/* Bit: 'FLD' */ ++/* Description: 'Force Link Down' */ ++#define TANTOS_3G_P3BC_FLD_OFFSET 0x61 ++#define TANTOS_3G_P3BC_FLD_SHIFT 1 ++#define TANTOS_3G_P3BC_FLD_SIZE 1 ++/* Bit: 'RMWFQ' */ ++/* Description: 'Ratio Mode for WFQ' */ ++#define TANTOS_3G_P3BC_RMWFQ_OFFSET 0x61 ++#define TANTOS_3G_P3BC_RMWFQ_SHIFT 0 ++#define TANTOS_3G_P3BC_RMWFQ_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'P4 Basic Control Register' */ ++/* Bit: 'SPS' */ ++/* Description: 'STP/RSTP port state' */ ++#define TANTOS_3G_P4BC_SPS_OFFSET 0x81 ++#define TANTOS_3G_P4BC_SPS_SHIFT 14 ++#define TANTOS_3G_P4BC_SPS_SIZE 2 ++/* Bit: 'TCPE' */ ++/* Description: 'TCP/UDP PRIEN' */ ++#define TANTOS_3G_P4BC_TCPE_OFFSET 0x81 ++#define TANTOS_3G_P4BC_TCPE_SHIFT 13 ++#define TANTOS_3G_P4BC_TCPE_SIZE 1 ++/* Bit: 'IPOVTU' */ ++/* Description: ' IP over TCP/UDP' */ ++#define TANTOS_3G_P4BC_IPOVTU_OFFSET 0x81 ++#define TANTOS_3G_P4BC_IPOVTU_SHIFT 12 ++#define TANTOS_3G_P4BC_IPOVTU_SIZE 1 ++/* Bit: 'VPE' */ ++/* Description: 'VLAN Priority Enable' */ ++#define TANTOS_3G_P4BC_VPE_OFFSET 0x81 ++#define TANTOS_3G_P4BC_VPE_SHIFT 11 ++#define TANTOS_3G_P4BC_VPE_SIZE 1 ++/* Bit: 'SPE' */ ++/* Description: 'Service Priority Enable' */ ++#define TANTOS_3G_P4BC_SPE_OFFSET 0x81 ++#define TANTOS_3G_P4BC_SPE_SHIFT 10 ++#define TANTOS_3G_P4BC_SPE_SIZE 1 ++/* Bit: 'IPVLAN' */ ++/* Description: 'IP over VLAN PRI' */ ++#define TANTOS_3G_P4BC_IPVLAN_OFFSET 0x81 ++#define TANTOS_3G_P4BC_IPVLAN_SHIFT 9 ++#define TANTOS_3G_P4BC_IPVLAN_SIZE 1 ++/* Bit: 'TPE' */ ++/* Description: 'Ether Type Priority Enable' */ ++#define TANTOS_3G_P4BC_TPE_OFFSET 0x81 ++#define TANTOS_3G_P4BC_TPE_SHIFT 8 ++#define TANTOS_3G_P4BC_TPE_SIZE 1 ++/* Bit: 'FLP' */ ++/* Description: 'Force Link Up' */ ++#define TANTOS_3G_P4BC_FLP_OFFSET 0x81 ++#define TANTOS_3G_P4BC_FLP_SHIFT 2 ++#define TANTOS_3G_P4BC_FLP_SIZE 1 ++/* Bit: 'FLD' */ ++/* Description: 'Force Link Down' */ ++#define TANTOS_3G_P4BC_FLD_OFFSET 0x81 ++#define TANTOS_3G_P4BC_FLD_SHIFT 1 ++#define TANTOS_3G_P4BC_FLD_SIZE 1 ++/* Bit: 'RMWFQ' */ ++/* Description: 'Ratio Mode for WFQ' */ ++#define TANTOS_3G_P4BC_RMWFQ_OFFSET 0x81 ++#define TANTOS_3G_P4BC_RMWFQ_SHIFT 0 ++#define TANTOS_3G_P4BC_RMWFQ_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'P5 Basic Control Register' */ ++/* Bit: 'SPS' */ ++/* Description: 'STP/RSTP port state' */ ++#define TANTOS_3G_P5BC_SPS_OFFSET 0xA1 ++#define TANTOS_3G_P5BC_SPS_SHIFT 14 ++#define TANTOS_3G_P5BC_SPS_SIZE 2 ++/* Bit: 'TCPE' */ ++/* Description: 'TCP/UDP PRIEN' */ ++#define TANTOS_3G_P5BC_TCPE_OFFSET 0xA1 ++#define TANTOS_3G_P5BC_TCPE_SHIFT 13 ++#define TANTOS_3G_P5BC_TCPE_SIZE 1 ++/* Bit: 'IPOVTU' */ ++/* Description: ' IP over TCP/UDP' */ ++#define TANTOS_3G_P5BC_IPOVTU_OFFSET 0xA1 ++#define TANTOS_3G_P5BC_IPOVTU_SHIFT 12 ++#define TANTOS_3G_P5BC_IPOVTU_SIZE 1 ++/* Bit: 'VPE' */ ++/* Description: 'VLAN Priority Enable' */ ++#define TANTOS_3G_P5BC_VPE_OFFSET 0xA1 ++#define TANTOS_3G_P5BC_VPE_SHIFT 11 ++#define TANTOS_3G_P5BC_VPE_SIZE 1 ++/* Bit: 'SPE' */ ++/* Description: 'Service Priority Enable' */ ++#define TANTOS_3G_P5BC_SPE_OFFSET 0xA1 ++#define TANTOS_3G_P5BC_SPE_SHIFT 10 ++#define TANTOS_3G_P5BC_SPE_SIZE 1 ++/* Bit: 'IPVLAN' */ ++/* Description: 'IP over VLAN PRI' */ ++#define TANTOS_3G_P5BC_IPVLAN_OFFSET 0xA1 ++#define TANTOS_3G_P5BC_IPVLAN_SHIFT 9 ++#define TANTOS_3G_P5BC_IPVLAN_SIZE 1 ++/* Bit: 'TPE' */ ++/* Description: 'Ether Type Priority Enable' */ ++#define TANTOS_3G_P5BC_TPE_OFFSET 0xA1 ++#define TANTOS_3G_P5BC_TPE_SHIFT 8 ++#define TANTOS_3G_P5BC_TPE_SIZE 1 ++/* Bit: 'FLP' */ ++/* Description: 'Force Link Up' */ ++#define TANTOS_3G_P5BC_FLP_OFFSET 0xA1 ++#define TANTOS_3G_P5BC_FLP_SHIFT 2 ++#define TANTOS_3G_P5BC_FLP_SIZE 1 ++/* Bit: 'FLD' */ ++/* Description: 'Force Link Down' */ ++#define TANTOS_3G_P5BC_FLD_OFFSET 0xA1 ++#define TANTOS_3G_P5BC_FLD_SHIFT 1 ++#define TANTOS_3G_P5BC_FLD_SIZE 1 ++/* Bit: 'RMWFQ' */ ++/* Description: 'Ratio Mode for WFQ' */ ++#define TANTOS_3G_P5BC_RMWFQ_OFFSET 0xA1 ++#define TANTOS_3G_P5BC_RMWFQ_SHIFT 0 ++#define TANTOS_3G_P5BC_RMWFQ_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'P6 Basic Control Register' */ ++/* Bit: 'SPS' */ ++/* Description: 'STP/RSTP port state' */ ++#define TANTOS_3G_P6BC_SPS_OFFSET 0xC1 ++#define TANTOS_3G_P6BC_SPS_SHIFT 14 ++#define TANTOS_3G_P6BC_SPS_SIZE 2 ++/* Bit: 'TCPE' */ ++/* Description: 'TCP/UDP PRIEN' */ ++#define TANTOS_3G_P6BC_TCPE_OFFSET 0xC1 ++#define TANTOS_3G_P6BC_TCPE_SHIFT 13 ++#define TANTOS_3G_P6BC_TCPE_SIZE 1 ++/* Bit: 'IPOVTU' */ ++/* Description: ' IP over TCP/UDP' */ ++#define TANTOS_3G_P6BC_IPOVTU_OFFSET 0xC1 ++#define TANTOS_3G_P6BC_IPOVTU_SHIFT 12 ++#define TANTOS_3G_P6BC_IPOVTU_SIZE 1 ++/* Bit: 'VPE' */ ++/* Description: 'VLAN Priority Enable' */ ++#define TANTOS_3G_P6BC_VPE_OFFSET 0xC1 ++#define TANTOS_3G_P6BC_VPE_SHIFT 11 ++#define TANTOS_3G_P6BC_VPE_SIZE 1 ++/* Bit: 'SPE' */ ++/* Description: 'Service Priority Enable' */ ++#define TANTOS_3G_P6BC_SPE_OFFSET 0xC1 ++#define TANTOS_3G_P6BC_SPE_SHIFT 10 ++#define TANTOS_3G_P6BC_SPE_SIZE 1 ++/* Bit: 'IPVLAN' */ ++/* Description: 'IP over VLAN PRI' */ ++#define TANTOS_3G_P6BC_IPVLAN_OFFSET 0xC1 ++#define TANTOS_3G_P6BC_IPVLAN_SHIFT 9 ++#define TANTOS_3G_P6BC_IPVLAN_SIZE 1 ++/* Bit: 'TPE' */ ++/* Description: 'Ether Type Priority Enable' */ ++#define TANTOS_3G_P6BC_TPE_OFFSET 0xC1 ++#define TANTOS_3G_P6BC_TPE_SHIFT 8 ++#define TANTOS_3G_P6BC_TPE_SIZE 1 ++/* Bit: 'FLP' */ ++/* Description: 'Force Link Up' */ ++#define TANTOS_3G_P6BC_FLP_OFFSET 0xC1 ++#define TANTOS_3G_P6BC_FLP_SHIFT 2 ++#define TANTOS_3G_P6BC_FLP_SIZE 1 ++/* Bit: 'FLD' */ ++/* Description: 'Force Link Down' */ ++#define TANTOS_3G_P6BC_FLD_OFFSET 0xC1 ++#define TANTOS_3G_P6BC_FLD_SHIFT 1 ++#define TANTOS_3G_P6BC_FLD_SIZE 1 ++/* Bit: 'RMWFQ' */ ++/* Description: 'Ratio Mode for WFQ' */ ++#define TANTOS_3G_P6BC_RMWFQ_OFFSET 0xC1 ++#define TANTOS_3G_P6BC_RMWFQ_SHIFT 0 ++#define TANTOS_3G_P6BC_RMWFQ_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'P0 Extended Control Register' */ ++/* Bit: 'AD' */ ++/* Description: 'Aging Disable' */ ++#define TANTOS_3G_P0EC_AD_OFFSET 0x02 ++#define TANTOS_3G_P0EC_AD_SHIFT 15 ++#define TANTOS_3G_P0EC_AD_SIZE 1 ++/* Bit: 'LD' */ ++/* Description: 'Learning Disable' */ ++#define TANTOS_3G_P0EC_LD_OFFSET 0x02 ++#define TANTOS_3G_P0EC_LD_SHIFT 14 ++#define TANTOS_3G_P0EC_LD_SIZE 1 ++/* Bit: 'IMTE' */ ++/* Description: 'IGMP/MLD Trap Enable' */ ++#define TANTOS_3G_P0EC_IMTE_OFFSET 0x02 ++#define TANTOS_3G_P0EC_IMTE_SHIFT 13 ++#define TANTOS_3G_P0EC_IMTE_SIZE 1 ++/* Bit: 'MNA024' */ ++/* Description: 'Maximum Number of Addresses' */ ++#define TANTOS_3G_P0EC_MNA024_OFFSET 0x02 ++#define TANTOS_3G_P0EC_MNA024_SHIFT 8 ++#define TANTOS_3G_P0EC_MNA024_SIZE 5 ++/* Bit: 'PPPOEP' */ ++/* Description: 'PPPOE Port Only' */ ++#define TANTOS_3G_P0EC_PPPOEP_OFFSET 0x02 ++#define TANTOS_3G_P0EC_PPPOEP_SHIFT 7 ++#define TANTOS_3G_P0EC_PPPOEP_SIZE 1 ++/* Bit: 'PM' */ ++/* Description: 'PPPOE Manage' */ ++#define TANTOS_3G_P0EC_PM_OFFSET 0x02 ++#define TANTOS_3G_P0EC_PM_SHIFT 6 ++#define TANTOS_3G_P0EC_PM_SIZE 1 ++/* Bit: 'IPMO' */ ++/* Description: 'Port Mirror Option' */ ++#define TANTOS_3G_P0EC_IPMO_OFFSET 0x02 ++#define TANTOS_3G_P0EC_IPMO_SHIFT 4 ++#define TANTOS_3G_P0EC_IPMO_SIZE 2 ++/* Bit: 'PAS' */ ++/* Description: '802.1x Port Authorized state' */ ++#define TANTOS_3G_P0EC_PAS_OFFSET 0x02 ++#define TANTOS_3G_P0EC_PAS_SHIFT 2 ++#define TANTOS_3G_P0EC_PAS_SIZE 2 ++/* Bit: 'IFNTE' */ ++/* Description: 'Input Force No TAG Enable' */ ++#define TANTOS_3G_P0EC_IFNTE_OFFSET 0x02 ++#define TANTOS_3G_P0EC_IFNTE_SHIFT 1 ++#define TANTOS_3G_P0EC_IFNTE_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'P1 Extended Control Register' */ ++/* Bit: 'AD' */ ++/* Description: 'Aging Disable' */ ++#define TANTOS_3G_P1EC_AD_OFFSET 0x22 ++#define TANTOS_3G_P1EC_AD_SHIFT 15 ++#define TANTOS_3G_P1EC_AD_SIZE 1 ++/* Bit: 'LD' */ ++/* Description: 'Learning Disable' */ ++#define TANTOS_3G_P1EC_LD_OFFSET 0x22 ++#define TANTOS_3G_P1EC_LD_SHIFT 14 ++#define TANTOS_3G_P1EC_LD_SIZE 1 ++/* Bit: 'IMTE' */ ++/* Description: 'IGMP/MLD Trap Enable' */ ++#define TANTOS_3G_P1EC_IMTE_OFFSET 0x22 ++#define TANTOS_3G_P1EC_IMTE_SHIFT 13 ++#define TANTOS_3G_P1EC_IMTE_SIZE 1 ++/* Bit: 'MNA024' */ ++/* Description: 'Maximum Number of Addresses' */ ++#define TANTOS_3G_P1EC_MNA024_OFFSET 0x22 ++#define TANTOS_3G_P1EC_MNA024_SHIFT 8 ++#define TANTOS_3G_P1EC_MNA024_SIZE 5 ++/* Bit: 'PPPOEP' */ ++/* Description: 'PPPOE Port Only' */ ++#define TANTOS_3G_P1EC_PPPOEP_OFFSET 0x22 ++#define TANTOS_3G_P1EC_PPPOEP_SHIFT 7 ++#define TANTOS_3G_P1EC_PPPOEP_SIZE 1 ++/* Bit: 'PM' */ ++/* Description: 'PPPOE Manage' */ ++#define TANTOS_3G_P1EC_PM_OFFSET 0x22 ++#define TANTOS_3G_P1EC_PM_SHIFT 6 ++#define TANTOS_3G_P1EC_PM_SIZE 1 ++/* Bit: 'IPMO' */ ++/* Description: 'Port Mirror Option' */ ++#define TANTOS_3G_P1EC_IPMO_OFFSET 0x22 ++#define TANTOS_3G_P1EC_IPMO_SHIFT 4 ++#define TANTOS_3G_P1EC_IPMO_SIZE 2 ++/* Bit: 'PAS' */ ++/* Description: '802.1x Port Authorized state' */ ++#define TANTOS_3G_P1EC_PAS_OFFSET 0x22 ++#define TANTOS_3G_P1EC_PAS_SHIFT 2 ++#define TANTOS_3G_P1EC_PAS_SIZE 2 ++/* Bit: 'IFNTE' */ ++/* Description: 'Input Force No TAG Enable' */ ++#define TANTOS_3G_P1EC_IFNTE_OFFSET 0x22 ++#define TANTOS_3G_P1EC_IFNTE_SHIFT 1 ++#define TANTOS_3G_P1EC_IFNTE_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'P2 Extended Control Register' */ ++/* Bit: 'AD' */ ++/* Description: 'Aging Disable' */ ++#define TANTOS_3G_P2EC_AD_OFFSET 0x42 ++#define TANTOS_3G_P2EC_AD_SHIFT 15 ++#define TANTOS_3G_P2EC_AD_SIZE 1 ++/* Bit: 'LD' */ ++/* Description: 'Learning Disable' */ ++#define TANTOS_3G_P2EC_LD_OFFSET 0x42 ++#define TANTOS_3G_P2EC_LD_SHIFT 14 ++#define TANTOS_3G_P2EC_LD_SIZE 1 ++/* Bit: 'IMTE' */ ++/* Description: 'IGMP/MLD Trap Enable' */ ++#define TANTOS_3G_P2EC_IMTE_OFFSET 0x42 ++#define TANTOS_3G_P2EC_IMTE_SHIFT 13 ++#define TANTOS_3G_P2EC_IMTE_SIZE 1 ++/* Bit: 'MNA024' */ ++/* Description: 'Maximum Number of Addresses' */ ++#define TANTOS_3G_P2EC_MNA024_OFFSET 0x42 ++#define TANTOS_3G_P2EC_MNA024_SHIFT 8 ++#define TANTOS_3G_P2EC_MNA024_SIZE 5 ++/* Bit: 'PPPOEP' */ ++/* Description: 'PPPOE Port Only' */ ++#define TANTOS_3G_P2EC_PPPOEP_OFFSET 0x42 ++#define TANTOS_3G_P2EC_PPPOEP_SHIFT 7 ++#define TANTOS_3G_P2EC_PPPOEP_SIZE 1 ++/* Bit: 'PM' */ ++/* Description: 'PPPOE Manage' */ ++#define TANTOS_3G_P2EC_PM_OFFSET 0x42 ++#define TANTOS_3G_P2EC_PM_SHIFT 6 ++#define TANTOS_3G_P2EC_PM_SIZE 1 ++/* Bit: 'IPMO' */ ++/* Description: 'Port Mirror Option' */ ++#define TANTOS_3G_P2EC_IPMO_OFFSET 0x42 ++#define TANTOS_3G_P2EC_IPMO_SHIFT 4 ++#define TANTOS_3G_P2EC_IPMO_SIZE 2 ++/* Bit: 'PAS' */ ++/* Description: '802.1x Port Authorized state' */ ++#define TANTOS_3G_P2EC_PAS_OFFSET 0x42 ++#define TANTOS_3G_P2EC_PAS_SHIFT 2 ++#define TANTOS_3G_P2EC_PAS_SIZE 2 ++/* Bit: 'IFNTE' */ ++/* Description: 'Input Force No TAG Enable' */ ++#define TANTOS_3G_P2EC_IFNTE_OFFSET 0x42 ++#define TANTOS_3G_P2EC_IFNTE_SHIFT 1 ++#define TANTOS_3G_P2EC_IFNTE_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'P3 Extended Control Register' */ ++/* Bit: 'AD' */ ++/* Description: 'Aging Disable' */ ++#define TANTOS_3G_P3EC_AD_OFFSET 0x62 ++#define TANTOS_3G_P3EC_AD_SHIFT 15 ++#define TANTOS_3G_P3EC_AD_SIZE 1 ++/* Bit: 'LD' */ ++/* Description: 'Learning Disable' */ ++#define TANTOS_3G_P3EC_LD_OFFSET 0x62 ++#define TANTOS_3G_P3EC_LD_SHIFT 14 ++#define TANTOS_3G_P3EC_LD_SIZE 1 ++/* Bit: 'IMTE' */ ++/* Description: 'IGMP/MLD Trap Enable' */ ++#define TANTOS_3G_P3EC_IMTE_OFFSET 0x62 ++#define TANTOS_3G_P3EC_IMTE_SHIFT 13 ++#define TANTOS_3G_P3EC_IMTE_SIZE 1 ++/* Bit: 'MNA024' */ ++/* Description: 'Maximum Number of Addresses' */ ++#define TANTOS_3G_P3EC_MNA024_OFFSET 0x62 ++#define TANTOS_3G_P3EC_MNA024_SHIFT 8 ++#define TANTOS_3G_P3EC_MNA024_SIZE 5 ++/* Bit: 'PPPOEP' */ ++/* Description: 'PPPOE Port Only' */ ++#define TANTOS_3G_P3EC_PPPOEP_OFFSET 0x62 ++#define TANTOS_3G_P3EC_PPPOEP_SHIFT 7 ++#define TANTOS_3G_P3EC_PPPOEP_SIZE 1 ++/* Bit: 'PM' */ ++/* Description: 'PPPOE Manage' */ ++#define TANTOS_3G_P3EC_PM_OFFSET 0x62 ++#define TANTOS_3G_P3EC_PM_SHIFT 6 ++#define TANTOS_3G_P3EC_PM_SIZE 1 ++/* Bit: 'IPMO' */ ++/* Description: 'Port Mirror Option' */ ++#define TANTOS_3G_P3EC_IPMO_OFFSET 0x62 ++#define TANTOS_3G_P3EC_IPMO_SHIFT 4 ++#define TANTOS_3G_P3EC_IPMO_SIZE 2 ++/* Bit: 'PAS' */ ++/* Description: '802.1x Port Authorized state' */ ++#define TANTOS_3G_P3EC_PAS_OFFSET 0x62 ++#define TANTOS_3G_P3EC_PAS_SHIFT 2 ++#define TANTOS_3G_P3EC_PAS_SIZE 2 ++/* Bit: 'IFNTE' */ ++/* Description: 'Input Force No TAG Enable' */ ++#define TANTOS_3G_P3EC_IFNTE_OFFSET 0x62 ++#define TANTOS_3G_P3EC_IFNTE_SHIFT 1 ++#define TANTOS_3G_P3EC_IFNTE_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'P4 Extended Control Register' */ ++/* Bit: 'AD' */ ++/* Description: 'Aging Disable' */ ++#define TANTOS_3G_P4EC_AD_OFFSET 0x82 ++#define TANTOS_3G_P4EC_AD_SHIFT 15 ++#define TANTOS_3G_P4EC_AD_SIZE 1 ++/* Bit: 'LD' */ ++/* Description: 'Learning Disable' */ ++#define TANTOS_3G_P4EC_LD_OFFSET 0x82 ++#define TANTOS_3G_P4EC_LD_SHIFT 14 ++#define TANTOS_3G_P4EC_LD_SIZE 1 ++/* Bit: 'IMTE' */ ++/* Description: 'IGMP/MLD Trap Enable' */ ++#define TANTOS_3G_P4EC_IMTE_OFFSET 0x82 ++#define TANTOS_3G_P4EC_IMTE_SHIFT 13 ++#define TANTOS_3G_P4EC_IMTE_SIZE 1 ++/* Bit: 'MNA024' */ ++/* Description: 'Maximum Number of Addresses' */ ++#define TANTOS_3G_P4EC_MNA024_OFFSET 0x82 ++#define TANTOS_3G_P4EC_MNA024_SHIFT 8 ++#define TANTOS_3G_P4EC_MNA024_SIZE 5 ++/* Bit: 'PPPOEP' */ ++/* Description: 'PPPOE Port Only' */ ++#define TANTOS_3G_P4EC_PPPOEP_OFFSET 0x82 ++#define TANTOS_3G_P4EC_PPPOEP_SHIFT 7 ++#define TANTOS_3G_P4EC_PPPOEP_SIZE 1 ++/* Bit: 'PM' */ ++/* Description: 'PPPOE Manage' */ ++#define TANTOS_3G_P4EC_PM_OFFSET 0x82 ++#define TANTOS_3G_P4EC_PM_SHIFT 6 ++#define TANTOS_3G_P4EC_PM_SIZE 1 ++/* Bit: 'IPMO' */ ++/* Description: 'Port Mirror Option' */ ++#define TANTOS_3G_P4EC_IPMO_OFFSET 0x82 ++#define TANTOS_3G_P4EC_IPMO_SHIFT 4 ++#define TANTOS_3G_P4EC_IPMO_SIZE 2 ++/* Bit: 'PAS' */ ++/* Description: '802.1x Port Authorized state' */ ++#define TANTOS_3G_P4EC_PAS_OFFSET 0x82 ++#define TANTOS_3G_P4EC_PAS_SHIFT 2 ++#define TANTOS_3G_P4EC_PAS_SIZE 2 ++/* Bit: 'IFNTE' */ ++/* Description: 'Input Force No TAG Enable' */ ++#define TANTOS_3G_P4EC_IFNTE_OFFSET 0x82 ++#define TANTOS_3G_P4EC_IFNTE_SHIFT 1 ++#define TANTOS_3G_P4EC_IFNTE_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'P5 Extended Control Register' */ ++/* Bit: 'AD' */ ++/* Description: 'Aging Disable' */ ++#define TANTOS_3G_P5EC_AD_OFFSET 0xA2 ++#define TANTOS_3G_P5EC_AD_SHIFT 15 ++#define TANTOS_3G_P5EC_AD_SIZE 1 ++/* Bit: 'LD' */ ++/* Description: 'Learning Disable' */ ++#define TANTOS_3G_P5EC_LD_OFFSET 0xA2 ++#define TANTOS_3G_P5EC_LD_SHIFT 14 ++#define TANTOS_3G_P5EC_LD_SIZE 1 ++/* Bit: 'IMTE' */ ++/* Description: 'IGMP/MLD Trap Enable' */ ++#define TANTOS_3G_P5EC_IMTE_OFFSET 0xA2 ++#define TANTOS_3G_P5EC_IMTE_SHIFT 13 ++#define TANTOS_3G_P5EC_IMTE_SIZE 1 ++/* Bit: 'MNA024' */ ++/* Description: 'Maximum Number of Addresses' */ ++#define TANTOS_3G_P5EC_MNA024_OFFSET 0xA2 ++#define TANTOS_3G_P5EC_MNA024_SHIFT 8 ++#define TANTOS_3G_P5EC_MNA024_SIZE 5 ++/* Bit: 'PPPOEP' */ ++/* Description: 'PPPOE Port Only' */ ++#define TANTOS_3G_P5EC_PPPOEP_OFFSET 0xA2 ++#define TANTOS_3G_P5EC_PPPOEP_SHIFT 7 ++#define TANTOS_3G_P5EC_PPPOEP_SIZE 1 ++/* Bit: 'PM' */ ++/* Description: 'PPPOE Manage' */ ++#define TANTOS_3G_P5EC_PM_OFFSET 0xA2 ++#define TANTOS_3G_P5EC_PM_SHIFT 6 ++#define TANTOS_3G_P5EC_PM_SIZE 1 ++/* Bit: 'IPMO' */ ++/* Description: 'Port Mirror Option' */ ++#define TANTOS_3G_P5EC_IPMO_OFFSET 0xA2 ++#define TANTOS_3G_P5EC_IPMO_SHIFT 4 ++#define TANTOS_3G_P5EC_IPMO_SIZE 2 ++/* Bit: 'PAS' */ ++/* Description: '802.1x Port Authorized state' */ ++#define TANTOS_3G_P5EC_PAS_OFFSET 0xA2 ++#define TANTOS_3G_P5EC_PAS_SHIFT 2 ++#define TANTOS_3G_P5EC_PAS_SIZE 2 ++/* Bit: 'IFNTE' */ ++/* Description: 'Input Force No TAG Enable' */ ++#define TANTOS_3G_P5EC_IFNTE_OFFSET 0xA2 ++#define TANTOS_3G_P5EC_IFNTE_SHIFT 1 ++#define TANTOS_3G_P5EC_IFNTE_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'P6 Extended Control Register' */ ++/* Bit: 'AD' */ ++/* Description: 'Aging Disable' */ ++#define TANTOS_3G_P6EC_AD_OFFSET 0xC2 ++#define TANTOS_3G_P6EC_AD_SHIFT 15 ++#define TANTOS_3G_P6EC_AD_SIZE 1 ++/* Bit: 'LD' */ ++/* Description: 'Learning Disable' */ ++#define TANTOS_3G_P6EC_LD_OFFSET 0xC2 ++#define TANTOS_3G_P6EC_LD_SHIFT 14 ++#define TANTOS_3G_P6EC_LD_SIZE 1 ++/* Bit: 'IMTE' */ ++/* Description: 'IGMP/MLD Trap Enable' */ ++#define TANTOS_3G_P6EC_IMTE_OFFSET 0xC2 ++#define TANTOS_3G_P6EC_IMTE_SHIFT 13 ++#define TANTOS_3G_P6EC_IMTE_SIZE 1 ++/* Bit: 'MNA024' */ ++/* Description: 'Maximum Number of Addresses' */ ++#define TANTOS_3G_P6EC_MNA024_OFFSET 0xC2 ++#define TANTOS_3G_P6EC_MNA024_SHIFT 8 ++#define TANTOS_3G_P6EC_MNA024_SIZE 5 ++/* Bit: 'PPPOEP' */ ++/* Description: 'PPPOE Port Only' */ ++#define TANTOS_3G_P6EC_PPPOEP_OFFSET 0xC2 ++#define TANTOS_3G_P6EC_PPPOEP_SHIFT 7 ++#define TANTOS_3G_P6EC_PPPOEP_SIZE 1 ++/* Bit: 'PM' */ ++/* Description: 'PPPOE Manage' */ ++#define TANTOS_3G_P6EC_PM_OFFSET 0xC2 ++#define TANTOS_3G_P6EC_PM_SHIFT 6 ++#define TANTOS_3G_P6EC_PM_SIZE 1 ++/* Bit: 'IPMO' */ ++/* Description: 'Port Mirror Option' */ ++#define TANTOS_3G_P6EC_IPMO_OFFSET 0xC2 ++#define TANTOS_3G_P6EC_IPMO_SHIFT 4 ++#define TANTOS_3G_P6EC_IPMO_SIZE 2 ++/* Bit: 'PAS' */ ++/* Description: '802.1x Port Authorized state' */ ++#define TANTOS_3G_P6EC_PAS_OFFSET 0xC2 ++#define TANTOS_3G_P6EC_PAS_SHIFT 2 ++#define TANTOS_3G_P6EC_PAS_SIZE 2 ++/* Bit: 'IFNTE' */ ++/* Description: 'Input Force No TAG Enable' */ ++#define TANTOS_3G_P6EC_IFNTE_OFFSET 0xC2 ++#define TANTOS_3G_P6EC_IFNTE_SHIFT 1 ++#define TANTOS_3G_P6EC_IFNTE_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 0 Port Base VLAN Map Register' */ ++/* Bit: 'DFID' */ ++/* Description: 'Default FID' */ ++#define TANTOS_3G_P0PBVM_DFID_OFFSET 0x03 ++#define TANTOS_3G_P0PBVM_DFID_SHIFT 14 ++#define TANTOS_3G_P0PBVM_DFID_SIZE 2 ++/* Bit: 'TBVE' */ ++/* Description: 'Tagged Base VLAN Enable' */ ++#define TANTOS_3G_P0PBVM_TBVE_OFFSET 0x03 ++#define TANTOS_3G_P0PBVM_TBVE_SHIFT 13 ++#define TANTOS_3G_P0PBVM_TBVE_SIZE 1 ++/* Bit: 'VC' */ ++/* Description: 'VID Check with the VID table' */ ++#define TANTOS_3G_P0PBVM_VC_OFFSET 0x03 ++#define TANTOS_3G_P0PBVM_VC_SHIFT 11 ++#define TANTOS_3G_P0PBVM_VC_SIZE 1 ++/* Bit: 'VSD' */ ++/* Description: 'VLAN Security Disable' */ ++#define TANTOS_3G_P0PBVM_VSD_OFFSET 0x03 ++#define TANTOS_3G_P0PBVM_VSD_SHIFT 10 ++#define TANTOS_3G_P0PBVM_VSD_SIZE 1 ++/* Bit: 'AOVTP' */ ++/* Description: 'Admit Only VLAN_Tagged Packet' */ ++#define TANTOS_3G_P0PBVM_AOVTP_OFFSET 0x03 ++#define TANTOS_3G_P0PBVM_AOVTP_SHIFT 9 ++#define TANTOS_3G_P0PBVM_AOVTP_SIZE 1 ++/* Bit: 'VMCE' */ ++/* Description: 'VLAN Member Check Enable' */ ++#define TANTOS_3G_P0PBVM_VMCE_OFFSET 0x03 ++#define TANTOS_3G_P0PBVM_VMCE_SHIFT 8 ++#define TANTOS_3G_P0PBVM_VMCE_SIZE 1 ++/* Bit: 'BYPASS' */ ++/* Description: 'ByPass Mode for Output' */ ++#define TANTOS_3G_P0PBVM_BYPASS_OFFSET 0x03 ++#define TANTOS_3G_P0PBVM_BYPASS_SHIFT 7 ++#define TANTOS_3G_P0PBVM_BYPASS_SIZE 1 ++/* Bit: 'DVPM' */ ++/* Description: 'Port Based VLAN Port Map' */ ++#define TANTOS_3G_P0PBVM_DVPM_OFFSET 0x03 ++#define TANTOS_3G_P0PBVM_DVPM_SHIFT 0 ++#define TANTOS_3G_P0PBVM_DVPM_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 1 Port Base VLAN Map Register' */ ++/* Bit: 'DFID' */ ++/* Description: 'Default FID' */ ++#define TANTOS_3G_P1PBVM_DFID_OFFSET 0x23 ++#define TANTOS_3G_P1PBVM_DFID_SHIFT 14 ++#define TANTOS_3G_P1PBVM_DFID_SIZE 2 ++/* Bit: 'TBVE' */ ++/* Description: 'Tagged Base VLAN Enable' */ ++#define TANTOS_3G_P1PBVM_TBVE_OFFSET 0x23 ++#define TANTOS_3G_P1PBVM_TBVE_SHIFT 13 ++#define TANTOS_3G_P1PBVM_TBVE_SIZE 1 ++/* Bit: 'VC' */ ++/* Description: 'VID Check with the VID table' */ ++#define TANTOS_3G_P1PBVM_VC_OFFSET 0x23 ++#define TANTOS_3G_P1PBVM_VC_SHIFT 11 ++#define TANTOS_3G_P1PBVM_VC_SIZE 1 ++/* Bit: 'VSD' */ ++/* Description: 'VLAN Security Disable' */ ++#define TANTOS_3G_P1PBVM_VSD_OFFSET 0x23 ++#define TANTOS_3G_P1PBVM_VSD_SHIFT 10 ++#define TANTOS_3G_P1PBVM_VSD_SIZE 1 ++/* Bit: 'AOVTP' */ ++/* Description: 'Admit Only VLAN_Tagged Packet' */ ++#define TANTOS_3G_P1PBVM_AOVTP_OFFSET 0x23 ++#define TANTOS_3G_P1PBVM_AOVTP_SHIFT 9 ++#define TANTOS_3G_P1PBVM_AOVTP_SIZE 1 ++/* Bit: 'VMCE' */ ++/* Description: 'VLAN Member Check Enable' */ ++#define TANTOS_3G_P1PBVM_VMCE_OFFSET 0x23 ++#define TANTOS_3G_P1PBVM_VMCE_SHIFT 8 ++#define TANTOS_3G_P1PBVM_VMCE_SIZE 1 ++/* Bit: 'BYPASS' */ ++/* Description: 'ByPass Mode for Output' */ ++#define TANTOS_3G_P1PBVM_BYPASS_OFFSET 0x23 ++#define TANTOS_3G_P1PBVM_BYPASS_SHIFT 7 ++#define TANTOS_3G_P1PBVM_BYPASS_SIZE 1 ++/* Bit: 'DVPM' */ ++/* Description: 'Port Based VLAN Port Map' */ ++#define TANTOS_3G_P1PBVM_DVPM_OFFSET 0x23 ++#define TANTOS_3G_P1PBVM_DVPM_SHIFT 0 ++#define TANTOS_3G_P1PBVM_DVPM_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 2 Port Base VLAN Map Register' */ ++/* Bit: 'DFID' */ ++/* Description: 'Default FID' */ ++#define TANTOS_3G_P2PBVM_DFID_OFFSET 0x43 ++#define TANTOS_3G_P2PBVM_DFID_SHIFT 14 ++#define TANTOS_3G_P2PBVM_DFID_SIZE 2 ++/* Bit: 'TBVE' */ ++/* Description: 'Tagged Base VLAN Enable' */ ++#define TANTOS_3G_P2PBVM_TBVE_OFFSET 0x43 ++#define TANTOS_3G_P2PBVM_TBVE_SHIFT 13 ++#define TANTOS_3G_P2PBVM_TBVE_SIZE 1 ++/* Bit: 'VC' */ ++/* Description: 'VID Check with the VID table' */ ++#define TANTOS_3G_P2PBVM_VC_OFFSET 0x43 ++#define TANTOS_3G_P2PBVM_VC_SHIFT 11 ++#define TANTOS_3G_P2PBVM_VC_SIZE 1 ++/* Bit: 'VSD' */ ++/* Description: 'VLAN Security Disable' */ ++#define TANTOS_3G_P2PBVM_VSD_OFFSET 0x43 ++#define TANTOS_3G_P2PBVM_VSD_SHIFT 10 ++#define TANTOS_3G_P2PBVM_VSD_SIZE 1 ++/* Bit: 'AOVTP' */ ++/* Description: 'Admit Only VLAN_Tagged Packet' */ ++#define TANTOS_3G_P2PBVM_AOVTP_OFFSET 0x43 ++#define TANTOS_3G_P2PBVM_AOVTP_SHIFT 9 ++#define TANTOS_3G_P2PBVM_AOVTP_SIZE 1 ++/* Bit: 'VMCE' */ ++/* Description: 'VLAN Member Check Enable' */ ++#define TANTOS_3G_P2PBVM_VMCE_OFFSET 0x43 ++#define TANTOS_3G_P2PBVM_VMCE_SHIFT 8 ++#define TANTOS_3G_P2PBVM_VMCE_SIZE 1 ++/* Bit: 'BYPASS' */ ++/* Description: 'ByPass Mode for Output' */ ++#define TANTOS_3G_P2PBVM_BYPASS_OFFSET 0x43 ++#define TANTOS_3G_P2PBVM_BYPASS_SHIFT 7 ++#define TANTOS_3G_P2PBVM_BYPASS_SIZE 1 ++/* Bit: 'DVPM' */ ++/* Description: 'Port Based VLAN Port Map' */ ++#define TANTOS_3G_P2PBVM_DVPM_OFFSET 0x43 ++#define TANTOS_3G_P2PBVM_DVPM_SHIFT 0 ++#define TANTOS_3G_P2PBVM_DVPM_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 3 Port Base VLAN Map Register' */ ++/* Bit: 'DFID' */ ++/* Description: 'Default FID' */ ++#define TANTOS_3G_P3PBVM_DFID_OFFSET 0x63 ++#define TANTOS_3G_P3PBVM_DFID_SHIFT 14 ++#define TANTOS_3G_P3PBVM_DFID_SIZE 2 ++/* Bit: 'TBVE' */ ++/* Description: 'Tagged Base VLAN Enable' */ ++#define TANTOS_3G_P3PBVM_TBVE_OFFSET 0x63 ++#define TANTOS_3G_P3PBVM_TBVE_SHIFT 13 ++#define TANTOS_3G_P3PBVM_TBVE_SIZE 1 ++/* Bit: 'VC' */ ++/* Description: 'VID Check with the VID table' */ ++#define TANTOS_3G_P3PBVM_VC_OFFSET 0x63 ++#define TANTOS_3G_P3PBVM_VC_SHIFT 11 ++#define TANTOS_3G_P3PBVM_VC_SIZE 1 ++/* Bit: 'VSD' */ ++/* Description: 'VLAN Security Disable' */ ++#define TANTOS_3G_P3PBVM_VSD_OFFSET 0x63 ++#define TANTOS_3G_P3PBVM_VSD_SHIFT 10 ++#define TANTOS_3G_P3PBVM_VSD_SIZE 1 ++/* Bit: 'AOVTP' */ ++/* Description: 'Admit Only VLAN_Tagged Packet' */ ++#define TANTOS_3G_P3PBVM_AOVTP_OFFSET 0x63 ++#define TANTOS_3G_P3PBVM_AOVTP_SHIFT 9 ++#define TANTOS_3G_P3PBVM_AOVTP_SIZE 1 ++/* Bit: 'VMCE' */ ++/* Description: 'VLAN Member Check Enable' */ ++#define TANTOS_3G_P3PBVM_VMCE_OFFSET 0x63 ++#define TANTOS_3G_P3PBVM_VMCE_SHIFT 8 ++#define TANTOS_3G_P3PBVM_VMCE_SIZE 1 ++/* Bit: 'BYPASS' */ ++/* Description: 'ByPass Mode for Output' */ ++#define TANTOS_3G_P3PBVM_BYPASS_OFFSET 0x63 ++#define TANTOS_3G_P3PBVM_BYPASS_SHIFT 7 ++#define TANTOS_3G_P3PBVM_BYPASS_SIZE 1 ++/* Bit: 'DVPM' */ ++/* Description: 'Port Based VLAN Port Map' */ ++#define TANTOS_3G_P3PBVM_DVPM_OFFSET 0x63 ++#define TANTOS_3G_P3PBVM_DVPM_SHIFT 0 ++#define TANTOS_3G_P3PBVM_DVPM_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 4 Port Base VLAN Map Register' */ ++/* Bit: 'DFID' */ ++/* Description: 'Default FID' */ ++#define TANTOS_3G_P4PBVM_DFID_OFFSET 0x83 ++#define TANTOS_3G_P4PBVM_DFID_SHIFT 14 ++#define TANTOS_3G_P4PBVM_DFID_SIZE 2 ++/* Bit: 'TBVE' */ ++/* Description: 'Tagged Base VLAN Enable' */ ++#define TANTOS_3G_P4PBVM_TBVE_OFFSET 0x83 ++#define TANTOS_3G_P4PBVM_TBVE_SHIFT 13 ++#define TANTOS_3G_P4PBVM_TBVE_SIZE 1 ++/* Bit: 'VC' */ ++/* Description: 'VID Check with the VID table' */ ++#define TANTOS_3G_P4PBVM_VC_OFFSET 0x83 ++#define TANTOS_3G_P4PBVM_VC_SHIFT 11 ++#define TANTOS_3G_P4PBVM_VC_SIZE 1 ++/* Bit: 'VSD' */ ++/* Description: 'VLAN Security Disable' */ ++#define TANTOS_3G_P4PBVM_VSD_OFFSET 0x83 ++#define TANTOS_3G_P4PBVM_VSD_SHIFT 10 ++#define TANTOS_3G_P4PBVM_VSD_SIZE 1 ++/* Bit: 'AOVTP' */ ++/* Description: 'Admit Only VLAN_Tagged Packet' */ ++#define TANTOS_3G_P4PBVM_AOVTP_OFFSET 0x83 ++#define TANTOS_3G_P4PBVM_AOVTP_SHIFT 9 ++#define TANTOS_3G_P4PBVM_AOVTP_SIZE 1 ++/* Bit: 'VMCE' */ ++/* Description: 'VLAN Member Check Enable' */ ++#define TANTOS_3G_P4PBVM_VMCE_OFFSET 0x83 ++#define TANTOS_3G_P4PBVM_VMCE_SHIFT 8 ++#define TANTOS_3G_P4PBVM_VMCE_SIZE 1 ++/* Bit: 'BYPASS' */ ++/* Description: 'ByPass Mode for Output' */ ++#define TANTOS_3G_P4PBVM_BYPASS_OFFSET 0x83 ++#define TANTOS_3G_P4PBVM_BYPASS_SHIFT 7 ++#define TANTOS_3G_P4PBVM_BYPASS_SIZE 1 ++/* Bit: 'DVPM' */ ++/* Description: 'Port Based VLAN Port Map' */ ++#define TANTOS_3G_P4PBVM_DVPM_OFFSET 0x83 ++#define TANTOS_3G_P4PBVM_DVPM_SHIFT 0 ++#define TANTOS_3G_P4PBVM_DVPM_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 5 Port Base VLAN Map Register' */ ++/* Bit: 'DFID' */ ++/* Description: 'Default FID' */ ++#define TANTOS_3G_P5PBVM_DFID_OFFSET 0xA3 ++#define TANTOS_3G_P5PBVM_DFID_SHIFT 14 ++#define TANTOS_3G_P5PBVM_DFID_SIZE 2 ++/* Bit: 'TBVE' */ ++/* Description: 'Tagged Base VLAN Enable' */ ++#define TANTOS_3G_P5PBVM_TBVE_OFFSET 0xA3 ++#define TANTOS_3G_P5PBVM_TBVE_SHIFT 13 ++#define TANTOS_3G_P5PBVM_TBVE_SIZE 1 ++/* Bit: 'VC' */ ++/* Description: 'VID Check with the VID table' */ ++#define TANTOS_3G_P5PBVM_VC_OFFSET 0xA3 ++#define TANTOS_3G_P5PBVM_VC_SHIFT 11 ++#define TANTOS_3G_P5PBVM_VC_SIZE 1 ++/* Bit: 'VSD' */ ++/* Description: 'VLAN Security Disable' */ ++#define TANTOS_3G_P5PBVM_VSD_OFFSET 0xA3 ++#define TANTOS_3G_P5PBVM_VSD_SHIFT 10 ++#define TANTOS_3G_P5PBVM_VSD_SIZE 1 ++/* Bit: 'AOVTP' */ ++/* Description: 'Admit Only VLAN_Tagged Packet' */ ++#define TANTOS_3G_P5PBVM_AOVTP_OFFSET 0xA3 ++#define TANTOS_3G_P5PBVM_AOVTP_SHIFT 9 ++#define TANTOS_3G_P5PBVM_AOVTP_SIZE 1 ++/* Bit: 'VMCE' */ ++/* Description: 'VLAN Member Check Enable' */ ++#define TANTOS_3G_P5PBVM_VMCE_OFFSET 0xA3 ++#define TANTOS_3G_P5PBVM_VMCE_SHIFT 8 ++#define TANTOS_3G_P5PBVM_VMCE_SIZE 1 ++/* Bit: 'BYPASS' */ ++/* Description: 'ByPass Mode for Output' */ ++#define TANTOS_3G_P5PBVM_BYPASS_OFFSET 0xA3 ++#define TANTOS_3G_P5PBVM_BYPASS_SHIFT 7 ++#define TANTOS_3G_P5PBVM_BYPASS_SIZE 1 ++/* Bit: 'DVPM' */ ++/* Description: 'Port Based VLAN Port Map' */ ++#define TANTOS_3G_P5PBVM_DVPM_OFFSET 0xA3 ++#define TANTOS_3G_P5PBVM_DVPM_SHIFT 0 ++#define TANTOS_3G_P5PBVM_DVPM_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 6 Port Base VLAN Map Register' */ ++/* Bit: 'DFID' */ ++/* Description: 'Default FID' */ ++#define TANTOS_3G_P6PBVM_DFID_OFFSET 0xC3 ++#define TANTOS_3G_P6PBVM_DFID_SHIFT 14 ++#define TANTOS_3G_P6PBVM_DFID_SIZE 2 ++/* Bit: 'TBVE' */ ++/* Description: 'Tagged Base VLAN Enable' */ ++#define TANTOS_3G_P6PBVM_TBVE_OFFSET 0xC3 ++#define TANTOS_3G_P6PBVM_TBVE_SHIFT 13 ++#define TANTOS_3G_P6PBVM_TBVE_SIZE 1 ++/* Bit: 'VC' */ ++/* Description: 'VID Check with the VID table' */ ++#define TANTOS_3G_P6PBVM_VC_OFFSET 0xC3 ++#define TANTOS_3G_P6PBVM_VC_SHIFT 11 ++#define TANTOS_3G_P6PBVM_VC_SIZE 1 ++/* Bit: 'VSD' */ ++/* Description: 'VLAN Security Disable' */ ++#define TANTOS_3G_P6PBVM_VSD_OFFSET 0xC3 ++#define TANTOS_3G_P6PBVM_VSD_SHIFT 10 ++#define TANTOS_3G_P6PBVM_VSD_SIZE 1 ++/* Bit: 'AOVTP' */ ++/* Description: 'Admit Only VLAN_Tagged Packet' */ ++#define TANTOS_3G_P6PBVM_AOVTP_OFFSET 0xC3 ++#define TANTOS_3G_P6PBVM_AOVTP_SHIFT 9 ++#define TANTOS_3G_P6PBVM_AOVTP_SIZE 1 ++/* Bit: 'VMCE' */ ++/* Description: 'VLAN Member Check Enable' */ ++#define TANTOS_3G_P6PBVM_VMCE_OFFSET 0xC3 ++#define TANTOS_3G_P6PBVM_VMCE_SHIFT 8 ++#define TANTOS_3G_P6PBVM_VMCE_SIZE 1 ++/* Bit: 'BYPASS' */ ++/* Description: 'ByPass Mode for Output' */ ++#define TANTOS_3G_P6PBVM_BYPASS_OFFSET 0xC3 ++#define TANTOS_3G_P6PBVM_BYPASS_SHIFT 7 ++#define TANTOS_3G_P6PBVM_BYPASS_SIZE 1 ++/* Bit: 'DVPM' */ ++/* Description: 'Port Based VLAN Port Map' */ ++#define TANTOS_3G_P6PBVM_DVPM_OFFSET 0xC3 ++#define TANTOS_3G_P6PBVM_DVPM_SHIFT 0 ++#define TANTOS_3G_P6PBVM_DVPM_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 0 Default VLAN ID & Priority Register' */ ++/* Bit: 'PP' */ ++/* Description: 'Port Priority' */ ++#define TANTOS_3G_P0DVID_PP_OFFSET 0x04 ++#define TANTOS_3G_P0DVID_PP_SHIFT 14 ++#define TANTOS_3G_P0DVID_PP_SIZE 2 ++/* Bit: 'PPE' */ ++/* Description: 'Port Priority Enable' */ ++#define TANTOS_3G_P0DVID_PPE_OFFSET 0x04 ++#define TANTOS_3G_P0DVID_PPE_SHIFT 13 ++#define TANTOS_3G_P0DVID_PPE_SIZE 1 ++/* Bit: 'PVTAGMP' */ ++/* Description: 'Portbase VLAN tag member for Port 0' */ ++#define TANTOS_3G_P0DVID_PVTAGMP_OFFSET 0x04 ++#define TANTOS_3G_P0DVID_PVTAGMP_SHIFT 12 ++#define TANTOS_3G_P0DVID_PVTAGMP_SIZE 1 ++/* Bit: 'PVID' */ ++/* Description: 'PVID' */ ++#define TANTOS_3G_P0DVID_PVID_OFFSET 0x04 ++#define TANTOS_3G_P0DVID_PVID_SHIFT 0 ++#define TANTOS_3G_P0DVID_PVID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 1 Default VLAN ID & Priority Register' */ ++/* Bit: 'PP' */ ++/* Description: 'Port Priority' */ ++#define TANTOS_3G_P1DVID_PP_OFFSET 0x24 ++#define TANTOS_3G_P1DVID_PP_SHIFT 14 ++#define TANTOS_3G_P1DVID_PP_SIZE 2 ++/* Bit: 'PPE' */ ++/* Description: 'Port Priority Enable' */ ++#define TANTOS_3G_P1DVID_PPE_OFFSET 0x24 ++#define TANTOS_3G_P1DVID_PPE_SHIFT 13 ++#define TANTOS_3G_P1DVID_PPE_SIZE 1 ++/* Bit: 'PVTAGMP' */ ++/* Description: 'Portbase VLAN tag member for Port 0' */ ++#define TANTOS_3G_P1DVID_PVTAGMP_OFFSET 0x24 ++#define TANTOS_3G_P1DVID_PVTAGMP_SHIFT 12 ++#define TANTOS_3G_P1DVID_PVTAGMP_SIZE 1 ++/* Bit: 'PVID' */ ++/* Description: 'PVID' */ ++#define TANTOS_3G_P1DVID_PVID_OFFSET 0x24 ++#define TANTOS_3G_P1DVID_PVID_SHIFT 0 ++#define TANTOS_3G_P1DVID_PVID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 2 Default VLAN ID & Priority Register' */ ++/* Bit: 'PP' */ ++/* Description: 'Port Priority' */ ++#define TANTOS_3G_P2DVID_PP_OFFSET 0x44 ++#define TANTOS_3G_P2DVID_PP_SHIFT 14 ++#define TANTOS_3G_P2DVID_PP_SIZE 2 ++/* Bit: 'PPE' */ ++/* Description: 'Port Priority Enable' */ ++#define TANTOS_3G_P2DVID_PPE_OFFSET 0x44 ++#define TANTOS_3G_P2DVID_PPE_SHIFT 13 ++#define TANTOS_3G_P2DVID_PPE_SIZE 1 ++/* Bit: 'PVTAGMP' */ ++/* Description: 'Portbase VLAN tag member for Port 0' */ ++#define TANTOS_3G_P2DVID_PVTAGMP_OFFSET 0x44 ++#define TANTOS_3G_P2DVID_PVTAGMP_SHIFT 12 ++#define TANTOS_3G_P2DVID_PVTAGMP_SIZE 1 ++/* Bit: 'PVID' */ ++/* Description: 'PVID' */ ++#define TANTOS_3G_P2DVID_PVID_OFFSET 0x44 ++#define TANTOS_3G_P2DVID_PVID_SHIFT 0 ++#define TANTOS_3G_P2DVID_PVID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 3 Default VLAN ID & Priority Register' */ ++/* Bit: 'PP' */ ++/* Description: 'Port Priority' */ ++#define TANTOS_3G_P3DVID_PP_OFFSET 0x64 ++#define TANTOS_3G_P3DVID_PP_SHIFT 14 ++#define TANTOS_3G_P3DVID_PP_SIZE 2 ++/* Bit: 'PPE' */ ++/* Description: 'Port Priority Enable' */ ++#define TANTOS_3G_P3DVID_PPE_OFFSET 0x64 ++#define TANTOS_3G_P3DVID_PPE_SHIFT 13 ++#define TANTOS_3G_P3DVID_PPE_SIZE 1 ++/* Bit: 'PVTAGMP' */ ++/* Description: 'Portbase VLAN tag member for Port 0' */ ++#define TANTOS_3G_P3DVID_PVTAGMP_OFFSET 0x64 ++#define TANTOS_3G_P3DVID_PVTAGMP_SHIFT 12 ++#define TANTOS_3G_P3DVID_PVTAGMP_SIZE 1 ++/* Bit: 'PVID' */ ++/* Description: 'PVID' */ ++#define TANTOS_3G_P3DVID_PVID_OFFSET 0x64 ++#define TANTOS_3G_P3DVID_PVID_SHIFT 0 ++#define TANTOS_3G_P3DVID_PVID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 4 Default VLAN ID & Priority Register' */ ++/* Bit: 'PP' */ ++/* Description: 'Port Priority' */ ++#define TANTOS_3G_P4DVID_PP_OFFSET 0x84 ++#define TANTOS_3G_P4DVID_PP_SHIFT 14 ++#define TANTOS_3G_P4DVID_PP_SIZE 2 ++/* Bit: 'PPE' */ ++/* Description: 'Port Priority Enable' */ ++#define TANTOS_3G_P4DVID_PPE_OFFSET 0x84 ++#define TANTOS_3G_P4DVID_PPE_SHIFT 13 ++#define TANTOS_3G_P4DVID_PPE_SIZE 1 ++/* Bit: 'PVTAGMP' */ ++/* Description: 'Portbase VLAN tag member for Port 0' */ ++#define TANTOS_3G_P4DVID_PVTAGMP_OFFSET 0x84 ++#define TANTOS_3G_P4DVID_PVTAGMP_SHIFT 12 ++#define TANTOS_3G_P4DVID_PVTAGMP_SIZE 1 ++/* Bit: 'PVID' */ ++/* Description: 'PVID' */ ++#define TANTOS_3G_P4DVID_PVID_OFFSET 0x84 ++#define TANTOS_3G_P4DVID_PVID_SHIFT 0 ++#define TANTOS_3G_P4DVID_PVID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 5 Default VLAN ID & Priority Register' */ ++/* Bit: 'PP' */ ++/* Description: 'Port Priority' */ ++#define TANTOS_3G_P5DVID_PP_OFFSET 0xA4 ++#define TANTOS_3G_P5DVID_PP_SHIFT 14 ++#define TANTOS_3G_P5DVID_PP_SIZE 2 ++/* Bit: 'PPE' */ ++/* Description: 'Port Priority Enable' */ ++#define TANTOS_3G_P5DVID_PPE_OFFSET 0xA4 ++#define TANTOS_3G_P5DVID_PPE_SHIFT 13 ++#define TANTOS_3G_P5DVID_PPE_SIZE 1 ++/* Bit: 'PVTAGMP' */ ++/* Description: 'Portbase VLAN tag member for Port 0' */ ++#define TANTOS_3G_P5DVID_PVTAGMP_OFFSET 0xA4 ++#define TANTOS_3G_P5DVID_PVTAGMP_SHIFT 12 ++#define TANTOS_3G_P5DVID_PVTAGMP_SIZE 1 ++/* Bit: 'PVID' */ ++/* Description: 'PVID' */ ++#define TANTOS_3G_P5DVID_PVID_OFFSET 0xA4 ++#define TANTOS_3G_P5DVID_PVID_SHIFT 0 ++#define TANTOS_3G_P5DVID_PVID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 6 Default VLAN ID & Priority Register' */ ++/* Bit: 'PP' */ ++/* Description: 'Port Priority' */ ++#define TANTOS_3G_P6DVID_PP_OFFSET 0xC4 ++#define TANTOS_3G_P6DVID_PP_SHIFT 14 ++#define TANTOS_3G_P6DVID_PP_SIZE 2 ++/* Bit: 'PPE' */ ++/* Description: 'Port Priority Enable' */ ++#define TANTOS_3G_P6DVID_PPE_OFFSET 0xC4 ++#define TANTOS_3G_P6DVID_PPE_SHIFT 13 ++#define TANTOS_3G_P6DVID_PPE_SIZE 1 ++/* Bit: 'PVTAGMP' */ ++/* Description: 'Portbase VLAN tag member for Port 0' */ ++#define TANTOS_3G_P6DVID_PVTAGMP_OFFSET 0xC4 ++#define TANTOS_3G_P6DVID_PVTAGMP_SHIFT 12 ++#define TANTOS_3G_P6DVID_PVTAGMP_SIZE 1 ++/* Bit: 'PVID' */ ++/* Description: 'PVID' */ ++#define TANTOS_3G_P6DVID_PVID_OFFSET 0xC4 ++#define TANTOS_3G_P6DVID_PVID_SHIFT 0 ++#define TANTOS_3G_P6DVID_PVID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 0 Egress Control for Strict Q3 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P0ECSQ3_P0SPQ3TR_OFFSET 0x05 ++#define TANTOS_3G_P0ECSQ3_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P0ECSQ3_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 1 Egress Control for Strict Q3 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P1ECSQ3_P0SPQ3TR_OFFSET 0x25 ++#define TANTOS_3G_P1ECSQ3_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P1ECSQ3_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 2 Egress Control for Strict Q3 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P2ECSQ3_P0SPQ3TR_OFFSET 0x45 ++#define TANTOS_3G_P2ECSQ3_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P2ECSQ3_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 3 Egress Control for Strict Q3 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P3ECSQ3_P0SPQ3TR_OFFSET 0x65 ++#define TANTOS_3G_P3ECSQ3_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P3ECSQ3_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 4 Egress Control for Strict Q3 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P4ECSQ3_P0SPQ3TR_OFFSET 0x85 ++#define TANTOS_3G_P4ECSQ3_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P4ECSQ3_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 5 Egress Control for Strict Q3 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P5ECSQ3_P0SPQ3TR_OFFSET 0xA5 ++#define TANTOS_3G_P5ECSQ3_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P5ECSQ3_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 6 Egress Control for Strict Q3 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P6ECSQ3_P0SPQ3TR_OFFSET 0xC5 ++#define TANTOS_3G_P6ECSQ3_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P6ECSQ3_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 0 Egress Control for Strict Q2 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P0ECSQ2_P0SPQ3TR_OFFSET 0x06 ++#define TANTOS_3G_P0ECSQ2_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P0ECSQ2_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 1 Egress Control for Strict Q2 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P1ECSQ2_P0SPQ3TR_OFFSET 0x26 ++#define TANTOS_3G_P1ECSQ2_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P1ECSQ2_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 2 Egress Control for Strict Q2 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P2ECSQ2_P0SPQ3TR_OFFSET 0x46 ++#define TANTOS_3G_P2ECSQ2_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P2ECSQ2_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 3 Egress Control for Strict Q2 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P3ECSQ2_P0SPQ3TR_OFFSET 0x66 ++#define TANTOS_3G_P3ECSQ2_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P3ECSQ2_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 4 Egress Control for Strict Q2 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P4ECSQ2_P0SPQ3TR_OFFSET 0x86 ++#define TANTOS_3G_P4ECSQ2_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P4ECSQ2_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 5 Egress Control for Strict Q2 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P5ECSQ2_P0SPQ3TR_OFFSET 0xA6 ++#define TANTOS_3G_P5ECSQ2_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P5ECSQ2_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 6 Egress Control for Strict Q2 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P6ECSQ2_P0SPQ3TR_OFFSET 0xC6 ++#define TANTOS_3G_P6ECSQ2_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P6ECSQ2_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 0 Egress Control for Strict Q1 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P0ECSQ1_P0SPQ3TR_OFFSET 0x07 ++#define TANTOS_3G_P0ECSQ1_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P0ECSQ1_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 1 Egress Control for Strict Q1 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P1ECSQ1_P0SPQ3TR_OFFSET 0x27 ++#define TANTOS_3G_P1ECSQ1_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P1ECSQ1_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 2 Egress Control for Strict Q1 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P2ECSQ1_P0SPQ3TR_OFFSET 0x47 ++#define TANTOS_3G_P2ECSQ1_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P2ECSQ1_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 3 Egress Control for Strict Q1 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P3ECSQ1_P0SPQ3TR_OFFSET 0x67 ++#define TANTOS_3G_P3ECSQ1_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P3ECSQ1_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 4 Egress Control for Strict Q1 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P4ECSQ1_P0SPQ3TR_OFFSET 0x87 ++#define TANTOS_3G_P4ECSQ1_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P4ECSQ1_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 5 Egress Control for Strict Q1 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P5ECSQ1_P0SPQ3TR_OFFSET 0xA7 ++#define TANTOS_3G_P5ECSQ1_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P5ECSQ1_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 6 Egress Control for Strict Q1 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P6ECSQ1_P0SPQ3TR_OFFSET 0xC7 ++#define TANTOS_3G_P6ECSQ1_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P6ECSQ1_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 0 Egress Control for Strict Q0 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P0ECSQ0_P0SPQ3TR_OFFSET 0x08 ++#define TANTOS_3G_P0ECSQ0_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P0ECSQ0_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 1 Egress Control for Strict Q0 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P1ECSQ0_P0SPQ3TR_OFFSET 0x28 ++#define TANTOS_3G_P1ECSQ0_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P1ECSQ0_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 2 Egress Control for Strict Q0 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P2ECSQ0_P0SPQ3TR_OFFSET 0x48 ++#define TANTOS_3G_P2ECSQ0_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P2ECSQ0_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 3 Egress Control for Strict Q0 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P3ECSQ0_P0SPQ3TR_OFFSET 0x68 ++#define TANTOS_3G_P3ECSQ0_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P3ECSQ0_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 4 Egress Control for Strict Q0 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P4ECSQ0_P0SPQ3TR_OFFSET 0x88 ++#define TANTOS_3G_P4ECSQ0_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P4ECSQ0_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 5 Egress Control for Strict Q0 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P5ECSQ0_P0SPQ3TR_OFFSET 0xA8 ++#define TANTOS_3G_P5ECSQ0_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P5ECSQ0_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 6 Egress Control for Strict Q0 Register' */ ++/* Bit: 'P0SPQ3TR' */ ++/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ ++#define TANTOS_3G_P6ECSQ0_P0SPQ3TR_OFFSET 0xC8 ++#define TANTOS_3G_P6ECSQ0_P0SPQ3TR_SHIFT 0 ++#define TANTOS_3G_P6ECSQ0_P0SPQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 0 Egress Control for WFQ Q3 Register' */ ++/* Bit: 'P0WQ3TR' */ ++/* Description: 'Port 0 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P0ECWQ3_P0WQ3TR_OFFSET 0x09 ++#define TANTOS_3G_P0ECWQ3_P0WQ3TR_SHIFT 0 ++#define TANTOS_3G_P0ECWQ3_P0WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 1 Egress Control for WFQ Q3 Register' */ ++/* Bit: 'P1WQ3TR' */ ++/* Description: 'Port 1 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P1ECWQ3_P1WQ3TR_OFFSET 0x29 ++#define TANTOS_3G_P1ECWQ3_P1WQ3TR_SHIFT 0 ++#define TANTOS_3G_P1ECWQ3_P1WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 2 Egress Control for WFQ Q3 Register' */ ++/* Bit: 'P2WQ3TR' */ ++/* Description: 'Port 2 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P2ECWQ3_P2WQ3TR_OFFSET 0x49 ++#define TANTOS_3G_P2ECWQ3_P2WQ3TR_SHIFT 0 ++#define TANTOS_3G_P2ECWQ3_P2WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 3 Egress Control for WFQ Q3 Register' */ ++/* Bit: 'P3WQ3TR' */ ++/* Description: 'Port 3 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P3ECWQ3_P3WQ3TR_OFFSET 0x69 ++#define TANTOS_3G_P3ECWQ3_P3WQ3TR_SHIFT 0 ++#define TANTOS_3G_P3ECWQ3_P3WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 4 Egress Control for WFQ Q3 Register' */ ++/* Bit: 'P4WQ3TR' */ ++/* Description: 'Port 4 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P4ECWQ3_P4WQ3TR_OFFSET 0x89 ++#define TANTOS_3G_P4ECWQ3_P4WQ3TR_SHIFT 0 ++#define TANTOS_3G_P4ECWQ3_P4WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 5 Egress Control for WFQ Q3 Register' */ ++/* Bit: 'P5WQ3TR' */ ++/* Description: 'Port 5 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P5ECWQ3_P5WQ3TR_OFFSET 0xA9 ++#define TANTOS_3G_P5ECWQ3_P5WQ3TR_SHIFT 0 ++#define TANTOS_3G_P5ECWQ3_P5WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 6 Egress Control for WFQ Q3 Register' */ ++/* Bit: 'P6WQ3TR' */ ++/* Description: 'Port 6 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P6ECWQ3_P6WQ3TR_OFFSET 0xC9 ++#define TANTOS_3G_P6ECWQ3_P6WQ3TR_SHIFT 0 ++#define TANTOS_3G_P6ECWQ3_P6WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 0 Egress Control for WFQ Q2 Register' */ ++/* Bit: 'P0WQ3TR' */ ++/* Description: 'Port 0 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P0ECWQ2_P0WQ3TR_OFFSET 0x0A ++#define TANTOS_3G_P0ECWQ2_P0WQ3TR_SHIFT 0 ++#define TANTOS_3G_P0ECWQ2_P0WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 1 Egress Control for WFQ Q2 Register' */ ++/* Bit: 'P8WQ3TR' */ ++/* Description: 'Port 8 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P1ECWQ2_P8WQ3TR_OFFSET 0x2A ++#define TANTOS_3G_P1ECWQ2_P8WQ3TR_SHIFT 0 ++#define TANTOS_3G_P1ECWQ2_P8WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 2 Egress Control for WFQ Q2 Register' */ ++/* Bit: 'P9WQ3TR' */ ++/* Description: 'Port 9 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P2ECWQ2_P9WQ3TR_OFFSET 0x4A ++#define TANTOS_3G_P2ECWQ2_P9WQ3TR_SHIFT 0 ++#define TANTOS_3G_P2ECWQ2_P9WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 3 Egress Control for WFQ Q2 Register' */ ++/* Bit: 'P10WQ3TR' */ ++/* Description: 'Port 10 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P3ECWQ2_P10WQ3TR_OFFSET 0x6A ++#define TANTOS_3G_P3ECWQ2_P10WQ3TR_SHIFT 0 ++#define TANTOS_3G_P3ECWQ2_P10WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 4 Egress Control for WFQ Q2 Register' */ ++/* Bit: 'P11WQ3TR' */ ++/* Description: 'Port 11 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P4ECWQ2_P11WQ3TR_OFFSET 0x8A ++#define TANTOS_3G_P4ECWQ2_P11WQ3TR_SHIFT 0 ++#define TANTOS_3G_P4ECWQ2_P11WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 5 Egress Control for WFQ Q2 Register' */ ++/* Bit: 'P12WQ3TR' */ ++/* Description: 'Port 12 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P5ECWQ2_P12WQ3TR_OFFSET 0xAA ++#define TANTOS_3G_P5ECWQ2_P12WQ3TR_SHIFT 0 ++#define TANTOS_3G_P5ECWQ2_P12WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 6 Egress Control for WFQ Q2 Register' */ ++/* Bit: 'P13WQ3TR' */ ++/* Description: 'Port 13 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P6ECWQ2_P13WQ3TR_OFFSET 0xCA ++#define TANTOS_3G_P6ECWQ2_P13WQ3TR_SHIFT 0 ++#define TANTOS_3G_P6ECWQ2_P13WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 0 Egress Control for WFQ Q1 Register' */ ++/* Bit: 'P0WQ3TR' */ ++/* Description: 'Port 0 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P0ECWQ1_P0WQ3TR_OFFSET 0x0B ++#define TANTOS_3G_P0ECWQ1_P0WQ3TR_SHIFT 0 ++#define TANTOS_3G_P0ECWQ1_P0WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 1 Egress Control for WFQ Q1 Register' */ ++/* Bit: 'P15WQ3TR' */ ++/* Description: 'Port 15 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P1ECWQ1_P15WQ3TR_OFFSET 0x2B ++#define TANTOS_3G_P1ECWQ1_P15WQ3TR_SHIFT 0 ++#define TANTOS_3G_P1ECWQ1_P15WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 2 Egress Control for WFQ Q1 Register' */ ++/* Bit: 'P16WQ3TR' */ ++/* Description: 'Port 16 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P2ECWQ1_P16WQ3TR_OFFSET 0x4B ++#define TANTOS_3G_P2ECWQ1_P16WQ3TR_SHIFT 0 ++#define TANTOS_3G_P2ECWQ1_P16WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 3 Egress Control for WFQ Q1 Register' */ ++/* Bit: 'P17WQ3TR' */ ++/* Description: 'Port 17 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P3ECWQ1_P17WQ3TR_OFFSET 0x6B ++#define TANTOS_3G_P3ECWQ1_P17WQ3TR_SHIFT 0 ++#define TANTOS_3G_P3ECWQ1_P17WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 4 Egress Control for WFQ Q1 Register' */ ++/* Bit: 'P18WQ3TR' */ ++/* Description: 'Port 18 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P4ECWQ1_P18WQ3TR_OFFSET 0x8B ++#define TANTOS_3G_P4ECWQ1_P18WQ3TR_SHIFT 0 ++#define TANTOS_3G_P4ECWQ1_P18WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 5 Egress Control for WFQ Q1 Register' */ ++/* Bit: 'P19WQ3TR' */ ++/* Description: 'Port 19 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P5ECWQ1_P19WQ3TR_OFFSET 0xAB ++#define TANTOS_3G_P5ECWQ1_P19WQ3TR_SHIFT 0 ++#define TANTOS_3G_P5ECWQ1_P19WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 6 Egress Control for WFQ Q1 Register' */ ++/* Bit: 'P20WQ3TR' */ ++/* Description: 'Port 20 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P6ECWQ1_P20WQ3TR_OFFSET 0xCB ++#define TANTOS_3G_P6ECWQ1_P20WQ3TR_SHIFT 0 ++#define TANTOS_3G_P6ECWQ1_P20WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 0 Egress Control for WFQ Q0 Register' */ ++/* Bit: 'P0WQ3TR' */ ++/* Description: 'Port 0 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P0ECWQ0_P0WQ3TR_OFFSET 0x0C ++#define TANTOS_3G_P0ECWQ0_P0WQ3TR_SHIFT 0 ++#define TANTOS_3G_P0ECWQ0_P0WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 1 Egress Control for WFQ Q0 Register' */ ++/* Bit: 'P22WQ3TR' */ ++/* Description: 'Port 22 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P1ECWQ0_P22WQ3TR_OFFSET 0x2C ++#define TANTOS_3G_P1ECWQ0_P22WQ3TR_SHIFT 0 ++#define TANTOS_3G_P1ECWQ0_P22WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 2 Egress Control for WFQ Q0 Register' */ ++/* Bit: 'P23WQ3TR' */ ++/* Description: 'Port 23 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P2ECWQ0_P23WQ3TR_OFFSET 0x4C ++#define TANTOS_3G_P2ECWQ0_P23WQ3TR_SHIFT 0 ++#define TANTOS_3G_P2ECWQ0_P23WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 3 Egress Control for WFQ Q0 Register' */ ++/* Bit: 'P24WQ3TR' */ ++/* Description: 'Port 24 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P3ECWQ0_P24WQ3TR_OFFSET 0x6C ++#define TANTOS_3G_P3ECWQ0_P24WQ3TR_SHIFT 0 ++#define TANTOS_3G_P3ECWQ0_P24WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 4 Egress Control for WFQ Q0 Register' */ ++/* Bit: 'P25WQ3TR' */ ++/* Description: 'Port 25 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P4ECWQ0_P25WQ3TR_OFFSET 0x8C ++#define TANTOS_3G_P4ECWQ0_P25WQ3TR_SHIFT 0 ++#define TANTOS_3G_P4ECWQ0_P25WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 5 Egress Control for WFQ Q0 Register' */ ++/* Bit: 'P26WQ3TR' */ ++/* Description: 'Port 26 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P5ECWQ0_P26WQ3TR_OFFSET 0xAC ++#define TANTOS_3G_P5ECWQ0_P26WQ3TR_SHIFT 0 ++#define TANTOS_3G_P5ECWQ0_P26WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 6 Egress Control for WFQ Q0 Register' */ ++/* Bit: 'P27WQ3TR' */ ++/* Description: 'Port 27 Egress Token R for WFQ Q3' */ ++#define TANTOS_3G_P6ECWQ0_P27WQ3TR_OFFSET 0xCC ++#define TANTOS_3G_P6ECWQ0_P27WQ3TR_SHIFT 0 ++#define TANTOS_3G_P6ECWQ0_P27WQ3TR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 0 Ingress Control Register' */ ++/* Bit: 'P0ITT' */ ++/* Description: 'Port 0 Ingress/Egress Timer Tick T selection' */ ++#define TANTOS_3G_P0ICR_P0ITT_OFFSET 0x0D ++#define TANTOS_3G_P0ICR_P0ITT_SHIFT 11 ++#define TANTOS_3G_P0ICR_P0ITT_SIZE 2 ++/* Bit: 'P0ITR' */ ++/* Description: 'Port 0 Ingress Token R' */ ++#define TANTOS_3G_P0ICR_P0ITR_OFFSET 0x0D ++#define TANTOS_3G_P0ICR_P0ITR_SHIFT 0 ++#define TANTOS_3G_P0ICR_P0ITR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 1 Ingress Control Register' */ ++/* Bit: 'P1ITT' */ ++/* Description: 'Port 1 Ingress/Egress Timer Tick T selection' */ ++#define TANTOS_3G_P1ICR_P1ITT_OFFSET 0x2D ++#define TANTOS_3G_P1ICR_P1ITT_SHIFT 11 ++#define TANTOS_3G_P1ICR_P1ITT_SIZE 2 ++/* Bit: 'P1ITR' */ ++/* Description: 'Port 1 Ingress Token R' */ ++#define TANTOS_3G_P1ICR_P1ITR_OFFSET 0x2D ++#define TANTOS_3G_P1ICR_P1ITR_SHIFT 0 ++#define TANTOS_3G_P1ICR_P1ITR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 2 Ingress Control Register' */ ++/* Bit: 'P2ITT' */ ++/* Description: 'Port 2 Ingress/Egress Timer Tick T selection' */ ++#define TANTOS_3G_P2ICR_P2ITT_OFFSET 0x4D ++#define TANTOS_3G_P2ICR_P2ITT_SHIFT 11 ++#define TANTOS_3G_P2ICR_P2ITT_SIZE 2 ++/* Bit: 'P2ITR' */ ++/* Description: 'Port 2 Ingress Token R' */ ++#define TANTOS_3G_P2ICR_P2ITR_OFFSET 0x4D ++#define TANTOS_3G_P2ICR_P2ITR_SHIFT 0 ++#define TANTOS_3G_P2ICR_P2ITR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 3 Ingress Control Register' */ ++/* Bit: 'P3ITT' */ ++/* Description: 'Port 3 Ingress/Egress Timer Tick T selection' */ ++#define TANTOS_3G_P3ICR_P3ITT_OFFSET 0x6D ++#define TANTOS_3G_P3ICR_P3ITT_SHIFT 11 ++#define TANTOS_3G_P3ICR_P3ITT_SIZE 2 ++/* Bit: 'P3ITR' */ ++/* Description: 'Port 3 Ingress Token R' */ ++#define TANTOS_3G_P3ICR_P3ITR_OFFSET 0x6D ++#define TANTOS_3G_P3ICR_P3ITR_SHIFT 0 ++#define TANTOS_3G_P3ICR_P3ITR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 4 Ingress Control Register' */ ++/* Bit: 'P4ITT' */ ++/* Description: 'Port 4 Ingress/Egress Timer Tick T selection' */ ++#define TANTOS_3G_P4ICR_P4ITT_OFFSET 0x8D ++#define TANTOS_3G_P4ICR_P4ITT_SHIFT 11 ++#define TANTOS_3G_P4ICR_P4ITT_SIZE 2 ++/* Bit: 'P4ITR' */ ++/* Description: 'Port 4 Ingress Token R' */ ++#define TANTOS_3G_P4ICR_P4ITR_OFFSET 0x8D ++#define TANTOS_3G_P4ICR_P4ITR_SHIFT 0 ++#define TANTOS_3G_P4ICR_P4ITR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 5 Ingress Control Register' */ ++/* Bit: 'P5ITT' */ ++/* Description: 'Port 5 Ingress/Egress Timer Tick T selection' */ ++#define TANTOS_3G_P5ICR_P5ITT_OFFSET 0xAD ++#define TANTOS_3G_P5ICR_P5ITT_SHIFT 11 ++#define TANTOS_3G_P5ICR_P5ITT_SIZE 2 ++/* Bit: 'P5ITR' */ ++/* Description: 'Port 5 Ingress Token R' */ ++#define TANTOS_3G_P5ICR_P5ITR_OFFSET 0xAD ++#define TANTOS_3G_P5ICR_P5ITR_SHIFT 0 ++#define TANTOS_3G_P5ICR_P5ITR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port 6 Ingress Control Register' */ ++/* Bit: 'P6ITT' */ ++/* Description: 'Port 6 Ingress/Egress Timer Tick T selection' */ ++#define TANTOS_3G_P6ICR_P6ITT_OFFSET 0xCD ++#define TANTOS_3G_P6ICR_P6ITT_SHIFT 11 ++#define TANTOS_3G_P6ICR_P6ITT_SIZE 2 ++/* Bit: 'P6ITR' */ ++/* Description: 'Port 6 Ingress Token R' */ ++#define TANTOS_3G_P6ICR_P6ITR_OFFSET 0xCD ++#define TANTOS_3G_P6ICR_P6ITR_SHIFT 0 ++#define TANTOS_3G_P6ICR_P6ITR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 0 Low' */ ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define TANTOS_3G_VF0L_VV_OFFSET 0x10 ++#define TANTOS_3G_VF0L_VV_SHIFT 15 ++#define TANTOS_3G_VF0L_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define TANTOS_3G_VF0L_VP_OFFSET 0x10 ++#define TANTOS_3G_VF0L_VP_SHIFT 12 ++#define TANTOS_3G_VF0L_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define TANTOS_3G_VF0L_VID_OFFSET 0x10 ++#define TANTOS_3G_VF0L_VID_SHIFT 0 ++#define TANTOS_3G_VF0L_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 1 Low' */ ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define TANTOS_3G_VF1L_VV_OFFSET 0x12 ++#define TANTOS_3G_VF1L_VV_SHIFT 15 ++#define TANTOS_3G_VF1L_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define TANTOS_3G_VF1L_VP_OFFSET 0x12 ++#define TANTOS_3G_VF1L_VP_SHIFT 12 ++#define TANTOS_3G_VF1L_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define TANTOS_3G_VF1L_VID_OFFSET 0x12 ++#define TANTOS_3G_VF1L_VID_SHIFT 0 ++#define TANTOS_3G_VF1L_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 2 Low' */ ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define TANTOS_3G_VF2L_VV_OFFSET 0x14 ++#define TANTOS_3G_VF2L_VV_SHIFT 15 ++#define TANTOS_3G_VF2L_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define TANTOS_3G_VF2L_VP_OFFSET 0x14 ++#define TANTOS_3G_VF2L_VP_SHIFT 12 ++#define TANTOS_3G_VF2L_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define TANTOS_3G_VF2L_VID_OFFSET 0x14 ++#define TANTOS_3G_VF2L_VID_SHIFT 0 ++#define TANTOS_3G_VF2L_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 3Low' */ ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define TANTOS_3G_VF3L_VV_OFFSET 0x16 ++#define TANTOS_3G_VF3L_VV_SHIFT 15 ++#define TANTOS_3G_VF3L_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define TANTOS_3G_VF3L_VP_OFFSET 0x16 ++#define TANTOS_3G_VF3L_VP_SHIFT 12 ++#define TANTOS_3G_VF3L_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define TANTOS_3G_VF3L_VID_OFFSET 0x16 ++#define TANTOS_3G_VF3L_VID_SHIFT 0 ++#define TANTOS_3G_VF3L_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 4 Low' */ ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define TANTOS_3G_VF4L_VV_OFFSET 0x18 ++#define TANTOS_3G_VF4L_VV_SHIFT 15 ++#define TANTOS_3G_VF4L_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define TANTOS_3G_VF4L_VP_OFFSET 0x18 ++#define TANTOS_3G_VF4L_VP_SHIFT 12 ++#define TANTOS_3G_VF4L_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define TANTOS_3G_VF4L_VID_OFFSET 0x18 ++#define TANTOS_3G_VF4L_VID_SHIFT 0 ++#define TANTOS_3G_VF4L_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 5 Low' */ ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define TANTOS_3G_VF5L_VV_OFFSET 0x1A ++#define TANTOS_3G_VF5L_VV_SHIFT 15 ++#define TANTOS_3G_VF5L_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define TANTOS_3G_VF5L_VP_OFFSET 0x1A ++#define TANTOS_3G_VF5L_VP_SHIFT 12 ++#define TANTOS_3G_VF5L_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define TANTOS_3G_VF5L_VID_OFFSET 0x1A ++#define TANTOS_3G_VF5L_VID_SHIFT 0 ++#define TANTOS_3G_VF5L_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 6 Low' */ ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define TANTOS_3G_VF6L_VV_OFFSET 0x1C ++#define TANTOS_3G_VF6L_VV_SHIFT 15 ++#define TANTOS_3G_VF6L_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define TANTOS_3G_VF6L_VP_OFFSET 0x1C ++#define TANTOS_3G_VF6L_VP_SHIFT 12 ++#define TANTOS_3G_VF6L_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define TANTOS_3G_VF6L_VID_OFFSET 0x1C ++#define TANTOS_3G_VF6L_VID_SHIFT 0 ++#define TANTOS_3G_VF6L_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 7 Low' */ ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define TANTOS_3G_VF7L_VV_OFFSET 0x1E ++#define TANTOS_3G_VF7L_VV_SHIFT 15 ++#define TANTOS_3G_VF7L_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define TANTOS_3G_VF7L_VP_OFFSET 0x1E ++#define TANTOS_3G_VF7L_VP_SHIFT 12 ++#define TANTOS_3G_VF7L_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define TANTOS_3G_VF7L_VID_OFFSET 0x1E ++#define TANTOS_3G_VF7L_VID_SHIFT 0 ++#define TANTOS_3G_VF7L_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 8 Low' */ ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define TANTOS_3G_VF8L_VV_OFFSET 0x30 ++#define TANTOS_3G_VF8L_VV_SHIFT 15 ++#define TANTOS_3G_VF8L_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define TANTOS_3G_VF8L_VP_OFFSET 0x30 ++#define TANTOS_3G_VF8L_VP_SHIFT 12 ++#define TANTOS_3G_VF8L_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define TANTOS_3G_VF8L_VID_OFFSET 0x30 ++#define TANTOS_3G_VF8L_VID_SHIFT 0 ++#define TANTOS_3G_VF8L_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 9 Low' */ ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define TANTOS_3G_VF9L_VV_OFFSET 0x32 ++#define TANTOS_3G_VF9L_VV_SHIFT 15 ++#define TANTOS_3G_VF9L_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define TANTOS_3G_VF9L_VP_OFFSET 0x32 ++#define TANTOS_3G_VF9L_VP_SHIFT 12 ++#define TANTOS_3G_VF9L_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define TANTOS_3G_VF9L_VID_OFFSET 0x32 ++#define TANTOS_3G_VF9L_VID_SHIFT 0 ++#define TANTOS_3G_VF9L_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 10 Low' */ ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define TANTOS_3G_VF10L_VV_OFFSET 0x34 ++#define TANTOS_3G_VF10L_VV_SHIFT 15 ++#define TANTOS_3G_VF10L_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define TANTOS_3G_VF10L_VP_OFFSET 0x34 ++#define TANTOS_3G_VF10L_VP_SHIFT 12 ++#define TANTOS_3G_VF10L_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define TANTOS_3G_VF10L_VID_OFFSET 0x34 ++#define TANTOS_3G_VF10L_VID_SHIFT 0 ++#define TANTOS_3G_VF10L_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 11 Low' */ ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define TANTOS_3G_VF11L_VV_OFFSET 0x36 ++#define TANTOS_3G_VF11L_VV_SHIFT 15 ++#define TANTOS_3G_VF11L_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define TANTOS_3G_VF11L_VP_OFFSET 0x36 ++#define TANTOS_3G_VF11L_VP_SHIFT 12 ++#define TANTOS_3G_VF11L_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define TANTOS_3G_VF11L_VID_OFFSET 0x36 ++#define TANTOS_3G_VF11L_VID_SHIFT 0 ++#define TANTOS_3G_VF11L_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 12 Low' */ ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define TANTOS_3G_VF12L_VV_OFFSET 0x38 ++#define TANTOS_3G_VF12L_VV_SHIFT 15 ++#define TANTOS_3G_VF12L_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define TANTOS_3G_VF12L_VP_OFFSET 0x38 ++#define TANTOS_3G_VF12L_VP_SHIFT 12 ++#define TANTOS_3G_VF12L_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define TANTOS_3G_VF12L_VID_OFFSET 0x38 ++#define TANTOS_3G_VF12L_VID_SHIFT 0 ++#define TANTOS_3G_VF12L_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 13 Low' */ ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define TANTOS_3G_VF13L_VV_OFFSET 0x3A ++#define TANTOS_3G_VF13L_VV_SHIFT 15 ++#define TANTOS_3G_VF13L_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define TANTOS_3G_VF13L_VP_OFFSET 0x3A ++#define TANTOS_3G_VF13L_VP_SHIFT 12 ++#define TANTOS_3G_VF13L_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define TANTOS_3G_VF13L_VID_OFFSET 0x3A ++#define TANTOS_3G_VF13L_VID_SHIFT 0 ++#define TANTOS_3G_VF13L_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 14 Low' */ ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define TANTOS_3G_VF14L_VV_OFFSET 0x3C ++#define TANTOS_3G_VF14L_VV_SHIFT 15 ++#define TANTOS_3G_VF14L_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define TANTOS_3G_VF14L_VP_OFFSET 0x3C ++#define TANTOS_3G_VF14L_VP_SHIFT 12 ++#define TANTOS_3G_VF14L_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define TANTOS_3G_VF14L_VID_OFFSET 0x3C ++#define TANTOS_3G_VF14L_VID_SHIFT 0 ++#define TANTOS_3G_VF14L_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 15 Low' */ ++/* Bit: 'VV' */ ++/* Description: 'VLAN_Valid' */ ++#define TANTOS_3G_VF15L_VV_OFFSET 0x3E ++#define TANTOS_3G_VF15L_VV_SHIFT 15 ++#define TANTOS_3G_VF15L_VV_SIZE 1 ++/* Bit: 'VP' */ ++/* Description: 'VLAN PRI' */ ++#define TANTOS_3G_VF15L_VP_OFFSET 0x3E ++#define TANTOS_3G_VF15L_VP_SHIFT 12 ++#define TANTOS_3G_VF15L_VP_SIZE 3 ++/* Bit: 'VID' */ ++/* Description: 'VID' */ ++#define TANTOS_3G_VF15L_VID_OFFSET 0x3E ++#define TANTOS_3G_VF15L_VID_SHIFT 0 ++#define TANTOS_3G_VF15L_VID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 0 High' */ ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define TANTOS_3G_VF0H_FID_OFFSET 0x11 ++#define TANTOS_3G_VF0H_FID_SHIFT 14 ++#define TANTOS_3G_VF0H_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define TANTOS_3G_VF0H_TM_OFFSET 0x11 ++#define TANTOS_3G_VF0H_TM_SHIFT 7 ++#define TANTOS_3G_VF0H_TM_SIZE 7 ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define TANTOS_3G_VF0H_M_OFFSET 0x11 ++#define TANTOS_3G_VF0H_M_SHIFT 0 ++#define TANTOS_3G_VF0H_M_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 1 High' */ ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define TANTOS_3G_VF1H_FID_OFFSET 0x13 ++#define TANTOS_3G_VF1H_FID_SHIFT 14 ++#define TANTOS_3G_VF1H_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define TANTOS_3G_VF1H_TM_OFFSET 0x13 ++#define TANTOS_3G_VF1H_TM_SHIFT 7 ++#define TANTOS_3G_VF1H_TM_SIZE 7 ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define TANTOS_3G_VF1H_M_OFFSET 0x13 ++#define TANTOS_3G_VF1H_M_SHIFT 0 ++#define TANTOS_3G_VF1H_M_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 2 High' */ ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define TANTOS_3G_VF2H_FID_OFFSET 0x15 ++#define TANTOS_3G_VF2H_FID_SHIFT 14 ++#define TANTOS_3G_VF2H_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define TANTOS_3G_VF2H_TM_OFFSET 0x15 ++#define TANTOS_3G_VF2H_TM_SHIFT 7 ++#define TANTOS_3G_VF2H_TM_SIZE 7 ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define TANTOS_3G_VF2H_M_OFFSET 0x15 ++#define TANTOS_3G_VF2H_M_SHIFT 0 ++#define TANTOS_3G_VF2H_M_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 3 High' */ ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define TANTOS_3G_VF3H_FID_OFFSET 0x17 ++#define TANTOS_3G_VF3H_FID_SHIFT 14 ++#define TANTOS_3G_VF3H_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define TANTOS_3G_VF3H_TM_OFFSET 0x17 ++#define TANTOS_3G_VF3H_TM_SHIFT 7 ++#define TANTOS_3G_VF3H_TM_SIZE 7 ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define TANTOS_3G_VF3H_M_OFFSET 0x17 ++#define TANTOS_3G_VF3H_M_SHIFT 0 ++#define TANTOS_3G_VF3H_M_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 4 High' */ ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define TANTOS_3G_VF4H_FID_OFFSET 0x19 ++#define TANTOS_3G_VF4H_FID_SHIFT 14 ++#define TANTOS_3G_VF4H_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define TANTOS_3G_VF4H_TM_OFFSET 0x19 ++#define TANTOS_3G_VF4H_TM_SHIFT 7 ++#define TANTOS_3G_VF4H_TM_SIZE 7 ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define TANTOS_3G_VF4H_M_OFFSET 0x19 ++#define TANTOS_3G_VF4H_M_SHIFT 0 ++#define TANTOS_3G_VF4H_M_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 5 High' */ ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define TANTOS_3G_VF5H_FID_OFFSET 0x1B ++#define TANTOS_3G_VF5H_FID_SHIFT 14 ++#define TANTOS_3G_VF5H_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define TANTOS_3G_VF5H_TM_OFFSET 0x1B ++#define TANTOS_3G_VF5H_TM_SHIFT 7 ++#define TANTOS_3G_VF5H_TM_SIZE 7 ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define TANTOS_3G_VF5H_M_OFFSET 0x1B ++#define TANTOS_3G_VF5H_M_SHIFT 0 ++#define TANTOS_3G_VF5H_M_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 6 High' */ ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define TANTOS_3G_VF6H_FID_OFFSET 0x1D ++#define TANTOS_3G_VF6H_FID_SHIFT 14 ++#define TANTOS_3G_VF6H_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define TANTOS_3G_VF6H_TM_OFFSET 0x1D ++#define TANTOS_3G_VF6H_TM_SHIFT 7 ++#define TANTOS_3G_VF6H_TM_SIZE 7 ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define TANTOS_3G_VF6H_M_OFFSET 0x1D ++#define TANTOS_3G_VF6H_M_SHIFT 0 ++#define TANTOS_3G_VF6H_M_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 7 High' */ ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define TANTOS_3G_VF7H_FID_OFFSET 0x1F ++#define TANTOS_3G_VF7H_FID_SHIFT 14 ++#define TANTOS_3G_VF7H_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define TANTOS_3G_VF7H_TM_OFFSET 0x1F ++#define TANTOS_3G_VF7H_TM_SHIFT 7 ++#define TANTOS_3G_VF7H_TM_SIZE 7 ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define TANTOS_3G_VF7H_M_OFFSET 0x1F ++#define TANTOS_3G_VF7H_M_SHIFT 0 ++#define TANTOS_3G_VF7H_M_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 8 High' */ ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define TANTOS_3G_VF8H_FID_OFFSET 0x31 ++#define TANTOS_3G_VF8H_FID_SHIFT 14 ++#define TANTOS_3G_VF8H_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define TANTOS_3G_VF8H_TM_OFFSET 0x31 ++#define TANTOS_3G_VF8H_TM_SHIFT 7 ++#define TANTOS_3G_VF8H_TM_SIZE 7 ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define TANTOS_3G_VF8H_M_OFFSET 0x31 ++#define TANTOS_3G_VF8H_M_SHIFT 0 ++#define TANTOS_3G_VF8H_M_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 9 High' */ ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define TANTOS_3G_VF9H_FID_OFFSET 0x33 ++#define TANTOS_3G_VF9H_FID_SHIFT 14 ++#define TANTOS_3G_VF9H_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define TANTOS_3G_VF9H_TM_OFFSET 0x33 ++#define TANTOS_3G_VF9H_TM_SHIFT 7 ++#define TANTOS_3G_VF9H_TM_SIZE 7 ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define TANTOS_3G_VF9H_M_OFFSET 0x33 ++#define TANTOS_3G_VF9H_M_SHIFT 0 ++#define TANTOS_3G_VF9H_M_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 10 High' */ ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define TANTOS_3G_VF10H_FID_OFFSET 0x35 ++#define TANTOS_3G_VF10H_FID_SHIFT 14 ++#define TANTOS_3G_VF10H_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define TANTOS_3G_VF10H_TM_OFFSET 0x35 ++#define TANTOS_3G_VF10H_TM_SHIFT 7 ++#define TANTOS_3G_VF10H_TM_SIZE 7 ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define TANTOS_3G_VF10H_M_OFFSET 0x35 ++#define TANTOS_3G_VF10H_M_SHIFT 0 ++#define TANTOS_3G_VF10H_M_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 11 High' */ ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define TANTOS_3G_VF11H_FID_OFFSET 0x37 ++#define TANTOS_3G_VF11H_FID_SHIFT 14 ++#define TANTOS_3G_VF11H_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define TANTOS_3G_VF11H_TM_OFFSET 0x37 ++#define TANTOS_3G_VF11H_TM_SHIFT 7 ++#define TANTOS_3G_VF11H_TM_SIZE 7 ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define TANTOS_3G_VF11H_M_OFFSET 0x37 ++#define TANTOS_3G_VF11H_M_SHIFT 0 ++#define TANTOS_3G_VF11H_M_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 12 High' */ ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define TANTOS_3G_VF12H_FID_OFFSET 0x39 ++#define TANTOS_3G_VF12H_FID_SHIFT 14 ++#define TANTOS_3G_VF12H_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define TANTOS_3G_VF12H_TM_OFFSET 0x39 ++#define TANTOS_3G_VF12H_TM_SHIFT 7 ++#define TANTOS_3G_VF12H_TM_SIZE 7 ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define TANTOS_3G_VF12H_M_OFFSET 0x39 ++#define TANTOS_3G_VF12H_M_SHIFT 0 ++#define TANTOS_3G_VF12H_M_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 13 High' */ ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define TANTOS_3G_VF13H_FID_OFFSET 0x3B ++#define TANTOS_3G_VF13H_FID_SHIFT 14 ++#define TANTOS_3G_VF13H_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define TANTOS_3G_VF13H_TM_OFFSET 0x3B ++#define TANTOS_3G_VF13H_TM_SHIFT 7 ++#define TANTOS_3G_VF13H_TM_SIZE 7 ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define TANTOS_3G_VF13H_M_OFFSET 0x3B ++#define TANTOS_3G_VF13H_M_SHIFT 0 ++#define TANTOS_3G_VF13H_M_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 14 High' */ ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define TANTOS_3G_VF14H_FID_OFFSET 0x3D ++#define TANTOS_3G_VF14H_FID_SHIFT 14 ++#define TANTOS_3G_VF14H_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define TANTOS_3G_VF14H_TM_OFFSET 0x3D ++#define TANTOS_3G_VF14H_TM_SHIFT 7 ++#define TANTOS_3G_VF14H_TM_SIZE 7 ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define TANTOS_3G_VF14H_M_OFFSET 0x3D ++#define TANTOS_3G_VF14H_M_SHIFT 0 ++#define TANTOS_3G_VF14H_M_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Filter 15 High' */ ++/* Bit: 'FID' */ ++/* Description: 'FID' */ ++#define TANTOS_3G_VF15H_FID_OFFSET 0x3F ++#define TANTOS_3G_VF15H_FID_SHIFT 14 ++#define TANTOS_3G_VF15H_FID_SIZE 2 ++/* Bit: 'TM' */ ++/* Description: 'Tagged Member' */ ++#define TANTOS_3G_VF15H_TM_OFFSET 0x3F ++#define TANTOS_3G_VF15H_TM_SHIFT 7 ++#define TANTOS_3G_VF15H_TM_SIZE 7 ++/* Bit: 'M' */ ++/* Description: 'Member' */ ++#define TANTOS_3G_VF15H_M_OFFSET 0x3F ++#define TANTOS_3G_VF15H_M_SHIFT 0 ++#define TANTOS_3G_VF15H_M_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Type Filter 0' */ ++/* Bit: 'VCET' */ ++/* Description: 'Value Compared with Ether-Type' */ ++#define TANTOS_3G_TF0_VCET_OFFSET 0x50 ++#define TANTOS_3G_TF0_VCET_SHIFT 0 ++#define TANTOS_3G_TF0_VCET_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Type Filter 1' */ ++/* Bit: 'VCET' */ ++/* Description: 'Value Compared with Ether-Type' */ ++#define TANTOS_3G_TF1_VCET_OFFSET 0x51 ++#define TANTOS_3G_TF1_VCET_SHIFT 0 ++#define TANTOS_3G_TF1_VCET_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Type Filter 2' */ ++/* Bit: 'VCET' */ ++/* Description: 'Value Compared with Ether-Type' */ ++#define TANTOS_3G_TF2_VCET_OFFSET 0x52 ++#define TANTOS_3G_TF2_VCET_SHIFT 0 ++#define TANTOS_3G_TF2_VCET_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Type Filter 3' */ ++/* Bit: 'VCET' */ ++/* Description: 'Value Compared with Ether-Type' */ ++#define TANTOS_3G_TF3_VCET_OFFSET 0x53 ++#define TANTOS_3G_TF3_VCET_SHIFT 0 ++#define TANTOS_3G_TF3_VCET_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Type Filter 4' */ ++/* Bit: 'VCET' */ ++/* Description: 'Value Compared with Ether-Type' */ ++#define TANTOS_3G_TF4_VCET_OFFSET 0x54 ++#define TANTOS_3G_TF4_VCET_SHIFT 0 ++#define TANTOS_3G_TF4_VCET_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Type Filter 5' */ ++/* Bit: 'VCET' */ ++/* Description: 'Value Compared with Ether-Type' */ ++#define TANTOS_3G_TF5_VCET_OFFSET 0x55 ++#define TANTOS_3G_TF5_VCET_SHIFT 0 ++#define TANTOS_3G_TF5_VCET_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Type Filter 6' */ ++/* Bit: 'VCET' */ ++/* Description: 'Value Compared with Ether-Type' */ ++#define TANTOS_3G_TF6_VCET_OFFSET 0x56 ++#define TANTOS_3G_TF6_VCET_SHIFT 0 ++#define TANTOS_3G_TF6_VCET_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Type Filter 7' */ ++/* Bit: 'VCET' */ ++/* Description: 'Value Compared with Ether-Type' */ ++#define TANTOS_3G_TF7_VCET_OFFSET 0x57 ++#define TANTOS_3G_TF7_VCET_SHIFT 0 ++#define TANTOS_3G_TF7_VCET_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'DiffServ Mapping 0' */ ++/* Bit: 'PQ7' */ ++/* Description: 'Priority Queue 7' */ ++#define TANTOS_3G_DM0_PQ7_OFFSET 0x58 ++#define TANTOS_3G_DM0_PQ7_SHIFT 14 ++#define TANTOS_3G_DM0_PQ7_SIZE 2 ++/* Bit: 'PQ6' */ ++/* Description: 'Priority Queue 6' */ ++#define TANTOS_3G_DM0_PQ6_OFFSET 0x58 ++#define TANTOS_3G_DM0_PQ6_SHIFT 12 ++#define TANTOS_3G_DM0_PQ6_SIZE 2 ++/* Bit: 'PQ5' */ ++/* Description: 'Priority Queue 5' */ ++#define TANTOS_3G_DM0_PQ5_OFFSET 0x58 ++#define TANTOS_3G_DM0_PQ5_SHIFT 10 ++#define TANTOS_3G_DM0_PQ5_SIZE 2 ++/* Bit: 'PQ4' */ ++/* Description: 'Priority Queue 4' */ ++#define TANTOS_3G_DM0_PQ4_OFFSET 0x58 ++#define TANTOS_3G_DM0_PQ4_SHIFT 8 ++#define TANTOS_3G_DM0_PQ4_SIZE 2 ++/* Bit: 'PQ3' */ ++/* Description: 'Priority Queue 3' */ ++#define TANTOS_3G_DM0_PQ3_OFFSET 0x58 ++#define TANTOS_3G_DM0_PQ3_SHIFT 6 ++#define TANTOS_3G_DM0_PQ3_SIZE 2 ++/* Bit: 'PQ2' */ ++/* Description: 'Priority Queue 2' */ ++#define TANTOS_3G_DM0_PQ2_OFFSET 0x58 ++#define TANTOS_3G_DM0_PQ2_SHIFT 4 ++#define TANTOS_3G_DM0_PQ2_SIZE 2 ++/* Bit: 'PQ1' */ ++/* Description: 'Priority Queue 1' */ ++#define TANTOS_3G_DM0_PQ1_OFFSET 0x58 ++#define TANTOS_3G_DM0_PQ1_SHIFT 2 ++#define TANTOS_3G_DM0_PQ1_SIZE 2 ++/* Bit: 'PQ0' */ ++/* Description: 'Priority Queue 0' */ ++#define TANTOS_3G_DM0_PQ0_OFFSET 0x58 ++#define TANTOS_3G_DM0_PQ0_SHIFT 0 ++#define TANTOS_3G_DM0_PQ0_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'DiffServMapping 1' */ ++/* Bit: 'PQF' */ ++/* Description: 'Priority Queue F' */ ++#define TANTOS_3G_DM1_PQF_OFFSET 0x59 ++#define TANTOS_3G_DM1_PQF_SHIFT 14 ++#define TANTOS_3G_DM1_PQF_SIZE 2 ++/* Bit: 'PQE' */ ++/* Description: 'Priority Queue E' */ ++#define TANTOS_3G_DM1_PQE_OFFSET 0x59 ++#define TANTOS_3G_DM1_PQE_SHIFT 12 ++#define TANTOS_3G_DM1_PQE_SIZE 2 ++/* Bit: 'PQD' */ ++/* Description: 'Priority Queue D' */ ++#define TANTOS_3G_DM1_PQD_OFFSET 0x59 ++#define TANTOS_3G_DM1_PQD_SHIFT 10 ++#define TANTOS_3G_DM1_PQD_SIZE 2 ++/* Bit: 'PQC' */ ++/* Description: 'Priority Queue C' */ ++#define TANTOS_3G_DM1_PQC_OFFSET 0x59 ++#define TANTOS_3G_DM1_PQC_SHIFT 8 ++#define TANTOS_3G_DM1_PQC_SIZE 2 ++/* Bit: 'PQB' */ ++/* Description: 'Priority Queue B' */ ++#define TANTOS_3G_DM1_PQB_OFFSET 0x59 ++#define TANTOS_3G_DM1_PQB_SHIFT 6 ++#define TANTOS_3G_DM1_PQB_SIZE 2 ++/* Bit: 'PQA' */ ++/* Description: 'Priority Queue A' */ ++#define TANTOS_3G_DM1_PQA_OFFSET 0x59 ++#define TANTOS_3G_DM1_PQA_SHIFT 4 ++#define TANTOS_3G_DM1_PQA_SIZE 2 ++/* Bit: 'PQ9' */ ++/* Description: 'Priority Queue 9' */ ++#define TANTOS_3G_DM1_PQ9_OFFSET 0x59 ++#define TANTOS_3G_DM1_PQ9_SHIFT 2 ++#define TANTOS_3G_DM1_PQ9_SIZE 2 ++/* Bit: 'PQ8' */ ++/* Description: 'Priority Queue 8' */ ++#define TANTOS_3G_DM1_PQ8_OFFSET 0x59 ++#define TANTOS_3G_DM1_PQ8_SHIFT 0 ++#define TANTOS_3G_DM1_PQ8_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'DiffServMapping 2' */ ++/* Bit: 'PQ17' */ ++/* Description: 'Priority Queue 17' */ ++#define TANTOS_3G_DM2_PQ17_OFFSET 0x5A ++#define TANTOS_3G_DM2_PQ17_SHIFT 14 ++#define TANTOS_3G_DM2_PQ17_SIZE 2 ++/* Bit: 'PQ16' */ ++/* Description: 'Priority Queue 16' */ ++#define TANTOS_3G_DM2_PQ16_OFFSET 0x5A ++#define TANTOS_3G_DM2_PQ16_SHIFT 12 ++#define TANTOS_3G_DM2_PQ16_SIZE 2 ++/* Bit: 'PQ15' */ ++/* Description: 'Priority Queue 15' */ ++#define TANTOS_3G_DM2_PQ15_OFFSET 0x5A ++#define TANTOS_3G_DM2_PQ15_SHIFT 10 ++#define TANTOS_3G_DM2_PQ15_SIZE 2 ++/* Bit: 'PQ14' */ ++/* Description: 'Priority Queue 14' */ ++#define TANTOS_3G_DM2_PQ14_OFFSET 0x5A ++#define TANTOS_3G_DM2_PQ14_SHIFT 8 ++#define TANTOS_3G_DM2_PQ14_SIZE 2 ++/* Bit: 'PQ13' */ ++/* Description: 'Priority Queue 13' */ ++#define TANTOS_3G_DM2_PQ13_OFFSET 0x5A ++#define TANTOS_3G_DM2_PQ13_SHIFT 6 ++#define TANTOS_3G_DM2_PQ13_SIZE 2 ++/* Bit: 'PQ12' */ ++/* Description: 'Priority Queue 12' */ ++#define TANTOS_3G_DM2_PQ12_OFFSET 0x5A ++#define TANTOS_3G_DM2_PQ12_SHIFT 4 ++#define TANTOS_3G_DM2_PQ12_SIZE 2 ++/* Bit: 'PQ11' */ ++/* Description: 'Priority Queue 11' */ ++#define TANTOS_3G_DM2_PQ11_OFFSET 0x5A ++#define TANTOS_3G_DM2_PQ11_SHIFT 2 ++#define TANTOS_3G_DM2_PQ11_SIZE 2 ++/* Bit: 'PQ10' */ ++/* Description: 'Priority Queue 10' */ ++#define TANTOS_3G_DM2_PQ10_OFFSET 0x5A ++#define TANTOS_3G_DM2_PQ10_SHIFT 0 ++#define TANTOS_3G_DM2_PQ10_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'DiffServMapping 3' */ ++/* Bit: 'PQ1F' */ ++/* Description: 'Priority Queue 1F' */ ++#define TANTOS_3G_DM3_PQ1F_OFFSET 0x5B ++#define TANTOS_3G_DM3_PQ1F_SHIFT 14 ++#define TANTOS_3G_DM3_PQ1F_SIZE 2 ++/* Bit: 'PQ1E' */ ++/* Description: 'Priority Queue 1E' */ ++#define TANTOS_3G_DM3_PQ1E_OFFSET 0x5B ++#define TANTOS_3G_DM3_PQ1E_SHIFT 12 ++#define TANTOS_3G_DM3_PQ1E_SIZE 2 ++/* Bit: 'PQ1D' */ ++/* Description: 'Priority Queue 1D' */ ++#define TANTOS_3G_DM3_PQ1D_OFFSET 0x5B ++#define TANTOS_3G_DM3_PQ1D_SHIFT 10 ++#define TANTOS_3G_DM3_PQ1D_SIZE 2 ++/* Bit: 'PQ1C' */ ++/* Description: 'Priority Queue 1C' */ ++#define TANTOS_3G_DM3_PQ1C_OFFSET 0x5B ++#define TANTOS_3G_DM3_PQ1C_SHIFT 8 ++#define TANTOS_3G_DM3_PQ1C_SIZE 2 ++/* Bit: 'PQ1B' */ ++/* Description: 'Priority Queue 1B' */ ++#define TANTOS_3G_DM3_PQ1B_OFFSET 0x5B ++#define TANTOS_3G_DM3_PQ1B_SHIFT 6 ++#define TANTOS_3G_DM3_PQ1B_SIZE 2 ++/* Bit: 'PQ1A' */ ++/* Description: 'Priority Queue 1A' */ ++#define TANTOS_3G_DM3_PQ1A_OFFSET 0x5B ++#define TANTOS_3G_DM3_PQ1A_SHIFT 4 ++#define TANTOS_3G_DM3_PQ1A_SIZE 2 ++/* Bit: 'PQ19' */ ++/* Description: 'Priority Queue 19' */ ++#define TANTOS_3G_DM3_PQ19_OFFSET 0x5B ++#define TANTOS_3G_DM3_PQ19_SHIFT 2 ++#define TANTOS_3G_DM3_PQ19_SIZE 2 ++/* Bit: 'PQ18' */ ++/* Description: 'Priority Queue 18' */ ++#define TANTOS_3G_DM3_PQ18_OFFSET 0x5B ++#define TANTOS_3G_DM3_PQ18_SHIFT 0 ++#define TANTOS_3G_DM3_PQ18_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'DiffServMapping 4' */ ++/* Bit: 'PQ27' */ ++/* Description: 'Priority Queue 27' */ ++#define TANTOS_3G_DM4_PQ27_OFFSET 0x5C ++#define TANTOS_3G_DM4_PQ27_SHIFT 14 ++#define TANTOS_3G_DM4_PQ27_SIZE 2 ++/* Bit: 'PQ26' */ ++/* Description: 'Priority Queue 26' */ ++#define TANTOS_3G_DM4_PQ26_OFFSET 0x5C ++#define TANTOS_3G_DM4_PQ26_SHIFT 12 ++#define TANTOS_3G_DM4_PQ26_SIZE 2 ++/* Bit: 'PQ25' */ ++/* Description: 'Priority Queue 25' */ ++#define TANTOS_3G_DM4_PQ25_OFFSET 0x5C ++#define TANTOS_3G_DM4_PQ25_SHIFT 10 ++#define TANTOS_3G_DM4_PQ25_SIZE 2 ++/* Bit: 'PQ24' */ ++/* Description: 'Priority Queue 24' */ ++#define TANTOS_3G_DM4_PQ24_OFFSET 0x5C ++#define TANTOS_3G_DM4_PQ24_SHIFT 8 ++#define TANTOS_3G_DM4_PQ24_SIZE 2 ++/* Bit: 'PQ23' */ ++/* Description: 'Priority Queue 23' */ ++#define TANTOS_3G_DM4_PQ23_OFFSET 0x5C ++#define TANTOS_3G_DM4_PQ23_SHIFT 6 ++#define TANTOS_3G_DM4_PQ23_SIZE 2 ++/* Bit: 'PQ22' */ ++/* Description: 'Priority Queue 22' */ ++#define TANTOS_3G_DM4_PQ22_OFFSET 0x5C ++#define TANTOS_3G_DM4_PQ22_SHIFT 4 ++#define TANTOS_3G_DM4_PQ22_SIZE 2 ++/* Bit: 'PQ21' */ ++/* Description: 'Priority Queue 21' */ ++#define TANTOS_3G_DM4_PQ21_OFFSET 0x5C ++#define TANTOS_3G_DM4_PQ21_SHIFT 2 ++#define TANTOS_3G_DM4_PQ21_SIZE 2 ++/* Bit: 'PQ20' */ ++/* Description: 'Priority Queue 20' */ ++#define TANTOS_3G_DM4_PQ20_OFFSET 0x5C ++#define TANTOS_3G_DM4_PQ20_SHIFT 0 ++#define TANTOS_3G_DM4_PQ20_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'DiffServMapping 5' */ ++/* Bit: 'PQ2F' */ ++/* Description: 'Priority Queue 2F' */ ++#define TANTOS_3G_DM5_PQ2F_OFFSET 0x5D ++#define TANTOS_3G_DM5_PQ2F_SHIFT 14 ++#define TANTOS_3G_DM5_PQ2F_SIZE 2 ++/* Bit: 'PQ2E' */ ++/* Description: 'Priority Queue 2E' */ ++#define TANTOS_3G_DM5_PQ2E_OFFSET 0x5D ++#define TANTOS_3G_DM5_PQ2E_SHIFT 12 ++#define TANTOS_3G_DM5_PQ2E_SIZE 2 ++/* Bit: 'PQ2D' */ ++/* Description: 'Priority Queue 2D' */ ++#define TANTOS_3G_DM5_PQ2D_OFFSET 0x5D ++#define TANTOS_3G_DM5_PQ2D_SHIFT 10 ++#define TANTOS_3G_DM5_PQ2D_SIZE 2 ++/* Bit: 'PQ2C' */ ++/* Description: 'Priority Queue 2C' */ ++#define TANTOS_3G_DM5_PQ2C_OFFSET 0x5D ++#define TANTOS_3G_DM5_PQ2C_SHIFT 8 ++#define TANTOS_3G_DM5_PQ2C_SIZE 2 ++/* Bit: 'PQ2B' */ ++/* Description: 'Priority Queue 2B' */ ++#define TANTOS_3G_DM5_PQ2B_OFFSET 0x5D ++#define TANTOS_3G_DM5_PQ2B_SHIFT 6 ++#define TANTOS_3G_DM5_PQ2B_SIZE 2 ++/* Bit: 'PQ2A' */ ++/* Description: 'Priority Queue 2A' */ ++#define TANTOS_3G_DM5_PQ2A_OFFSET 0x5D ++#define TANTOS_3G_DM5_PQ2A_SHIFT 4 ++#define TANTOS_3G_DM5_PQ2A_SIZE 2 ++/* Bit: 'PQ29' */ ++/* Description: 'Priority Queue 29' */ ++#define TANTOS_3G_DM5_PQ29_OFFSET 0x5D ++#define TANTOS_3G_DM5_PQ29_SHIFT 2 ++#define TANTOS_3G_DM5_PQ29_SIZE 2 ++/* Bit: 'PQ28' */ ++/* Description: 'Priority Queue 28' */ ++#define TANTOS_3G_DM5_PQ28_OFFSET 0x5D ++#define TANTOS_3G_DM5_PQ28_SHIFT 0 ++#define TANTOS_3G_DM5_PQ28_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'DiffServMapping 6' */ ++/* Bit: 'PQ37' */ ++/* Description: 'Priority Queue 37' */ ++#define TANTOS_3G_DM6_PQ37_OFFSET 0x5E ++#define TANTOS_3G_DM6_PQ37_SHIFT 14 ++#define TANTOS_3G_DM6_PQ37_SIZE 2 ++/* Bit: 'PQ36' */ ++/* Description: 'Priority Queue 36' */ ++#define TANTOS_3G_DM6_PQ36_OFFSET 0x5E ++#define TANTOS_3G_DM6_PQ36_SHIFT 12 ++#define TANTOS_3G_DM6_PQ36_SIZE 2 ++/* Bit: 'PQ35' */ ++/* Description: 'Priority Queue 35' */ ++#define TANTOS_3G_DM6_PQ35_OFFSET 0x5E ++#define TANTOS_3G_DM6_PQ35_SHIFT 10 ++#define TANTOS_3G_DM6_PQ35_SIZE 2 ++/* Bit: 'PQ34' */ ++/* Description: 'Priority Queue 34' */ ++#define TANTOS_3G_DM6_PQ34_OFFSET 0x5E ++#define TANTOS_3G_DM6_PQ34_SHIFT 8 ++#define TANTOS_3G_DM6_PQ34_SIZE 2 ++/* Bit: 'PQ33' */ ++/* Description: 'Priority Queue 33' */ ++#define TANTOS_3G_DM6_PQ33_OFFSET 0x5E ++#define TANTOS_3G_DM6_PQ33_SHIFT 6 ++#define TANTOS_3G_DM6_PQ33_SIZE 2 ++/* Bit: 'PQ32' */ ++/* Description: 'Priority Queue 32' */ ++#define TANTOS_3G_DM6_PQ32_OFFSET 0x5E ++#define TANTOS_3G_DM6_PQ32_SHIFT 4 ++#define TANTOS_3G_DM6_PQ32_SIZE 2 ++/* Bit: 'PQ31' */ ++/* Description: 'Priority Queue 31' */ ++#define TANTOS_3G_DM6_PQ31_OFFSET 0x5E ++#define TANTOS_3G_DM6_PQ31_SHIFT 2 ++#define TANTOS_3G_DM6_PQ31_SIZE 2 ++/* Bit: 'PQ30' */ ++/* Description: 'Priority Queue 30' */ ++#define TANTOS_3G_DM6_PQ30_OFFSET 0x5E ++#define TANTOS_3G_DM6_PQ30_SHIFT 0 ++#define TANTOS_3G_DM6_PQ30_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'DiffServMapping 7' */ ++/* Bit: 'PQ3F' */ ++/* Description: 'Priority Queue 3F' */ ++#define TANTOS_3G_DM7_PQ3F_OFFSET 0x5F ++#define TANTOS_3G_DM7_PQ3F_SHIFT 14 ++#define TANTOS_3G_DM7_PQ3F_SIZE 2 ++/* Bit: 'PQ3E' */ ++/* Description: 'Priority Queue 3E' */ ++#define TANTOS_3G_DM7_PQ3E_OFFSET 0x5F ++#define TANTOS_3G_DM7_PQ3E_SHIFT 12 ++#define TANTOS_3G_DM7_PQ3E_SIZE 2 ++/* Bit: 'PQ3D' */ ++/* Description: 'Priority Queue 3D' */ ++#define TANTOS_3G_DM7_PQ3D_OFFSET 0x5F ++#define TANTOS_3G_DM7_PQ3D_SHIFT 10 ++#define TANTOS_3G_DM7_PQ3D_SIZE 2 ++/* Bit: 'PQ3C' */ ++/* Description: 'Priority Queue 3C' */ ++#define TANTOS_3G_DM7_PQ3C_OFFSET 0x5F ++#define TANTOS_3G_DM7_PQ3C_SHIFT 8 ++#define TANTOS_3G_DM7_PQ3C_SIZE 2 ++/* Bit: 'PQ3B' */ ++/* Description: 'Priority Queue 3B' */ ++#define TANTOS_3G_DM7_PQ3B_OFFSET 0x5F ++#define TANTOS_3G_DM7_PQ3B_SHIFT 6 ++#define TANTOS_3G_DM7_PQ3B_SIZE 2 ++/* Bit: 'PQ3A' */ ++/* Description: 'Priority Queue 3A' */ ++#define TANTOS_3G_DM7_PQ3A_OFFSET 0x5F ++#define TANTOS_3G_DM7_PQ3A_SHIFT 4 ++#define TANTOS_3G_DM7_PQ3A_SIZE 2 ++/* Bit: 'PQ39' */ ++/* Description: 'Priority Queue 39' */ ++#define TANTOS_3G_DM7_PQ39_OFFSET 0x5F ++#define TANTOS_3G_DM7_PQ39_SHIFT 2 ++#define TANTOS_3G_DM7_PQ39_SIZE 2 ++/* Bit: 'PQ38' */ ++/* Description: 'Priority Queue 38' */ ++#define TANTOS_3G_DM7_PQ38_OFFSET 0x5F ++#define TANTOS_3G_DM7_PQ38_SHIFT 0 ++#define TANTOS_3G_DM7_PQ38_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Filter 0' */ ++/* Bit: 'BASEPT0' */ ++/* Description: 'Base Port number 0' */ ++#define TANTOS_3G_TUPF0_BASEPT0_OFFSET 0x70 ++#define TANTOS_3G_TUPF0_BASEPT0_SHIFT 0 ++#define TANTOS_3G_TUPF0_BASEPT0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Filter 1' */ ++/* Bit: 'BASEPT1' */ ++/* Description: 'Base Port number 1' */ ++#define TANTOS_3G_TUPF1_BASEPT1_OFFSET 0x72 ++#define TANTOS_3G_TUPF1_BASEPT1_SHIFT 0 ++#define TANTOS_3G_TUPF1_BASEPT1_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Filter 2' */ ++/* Bit: 'BASEPT2' */ ++/* Description: 'Base Port number 2' */ ++#define TANTOS_3G_TUPF2_BASEPT2_OFFSET 0x74 ++#define TANTOS_3G_TUPF2_BASEPT2_SHIFT 0 ++#define TANTOS_3G_TUPF2_BASEPT2_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Filter 3' */ ++/* Bit: 'BASEPT3' */ ++/* Description: 'Base Port number 3' */ ++#define TANTOS_3G_TUPF3_BASEPT3_OFFSET 0x76 ++#define TANTOS_3G_TUPF3_BASEPT3_SHIFT 0 ++#define TANTOS_3G_TUPF3_BASEPT3_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Filter 4' */ ++/* Bit: 'BASEPT4' */ ++/* Description: 'Base Port number 4' */ ++#define TANTOS_3G_TUPF4_BASEPT4_OFFSET 0x78 ++#define TANTOS_3G_TUPF4_BASEPT4_SHIFT 0 ++#define TANTOS_3G_TUPF4_BASEPT4_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Filter 5' */ ++/* Bit: 'BASEPT5' */ ++/* Description: 'Base Port number 5' */ ++#define TANTOS_3G_TUPF5_BASEPT5_OFFSET 0x7A ++#define TANTOS_3G_TUPF5_BASEPT5_SHIFT 0 ++#define TANTOS_3G_TUPF5_BASEPT5_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Filter 6' */ ++/* Bit: 'BASEPT6' */ ++/* Description: 'Base Port number 6' */ ++#define TANTOS_3G_TUPF6_BASEPT6_OFFSET 0x7C ++#define TANTOS_3G_TUPF6_BASEPT6_SHIFT 0 ++#define TANTOS_3G_TUPF6_BASEPT6_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Filter 7' */ ++/* Bit: 'BASEPT7' */ ++/* Description: 'Base Port number 7' */ ++#define TANTOS_3G_TUPF7_BASEPT7_OFFSET 0x7E ++#define TANTOS_3G_TUPF7_BASEPT7_SHIFT 0 ++#define TANTOS_3G_TUPF7_BASEPT7_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Range 0' */ ++/* Bit: 'ATUF0' */ ++/* Description: 'Action for TCP/UDP Port Filter 0' */ ++#define TANTOS_3G_TUPR0_ATUF0_OFFSET 0x71 ++#define TANTOS_3G_TUPR0_ATUF0_SHIFT 12 ++#define TANTOS_3G_TUPR0_ATUF0_SIZE 2 ++/* Bit: 'TUPF0' */ ++/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 0' */ ++#define TANTOS_3G_TUPR0_TUPF0_OFFSET 0x71 ++#define TANTOS_3G_TUPR0_TUPF0_SHIFT 10 ++#define TANTOS_3G_TUPR0_TUPF0_SIZE 2 ++/* Bit: 'COMP0' */ ++/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ ++#define TANTOS_3G_TUPR0_COMP0_OFFSET 0x71 ++#define TANTOS_3G_TUPR0_COMP0_SHIFT 8 ++#define TANTOS_3G_TUPR0_COMP0_SIZE 2 ++/* Bit: 'PRANGE0' */ ++/* Description: 'Port Range in TCP/UDP' */ ++#define TANTOS_3G_TUPR0_PRANGE0_OFFSET 0x71 ++#define TANTOS_3G_TUPR0_PRANGE0_SHIFT 0 ++#define TANTOS_3G_TUPR0_PRANGE0_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Range 1' */ ++/* Bit: 'ATUF1' */ ++/* Description: 'Action for TCP/UDP Port Filter 1' */ ++#define TANTOS_3G_TUPR1_ATUF1_OFFSET 0x73 ++#define TANTOS_3G_TUPR1_ATUF1_SHIFT 12 ++#define TANTOS_3G_TUPR1_ATUF1_SIZE 2 ++/* Bit: 'TUPF1' */ ++/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 1' */ ++#define TANTOS_3G_TUPR1_TUPF1_OFFSET 0x73 ++#define TANTOS_3G_TUPR1_TUPF1_SHIFT 10 ++#define TANTOS_3G_TUPR1_TUPF1_SIZE 2 ++/* Bit: 'COMP1' */ ++/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ ++#define TANTOS_3G_TUPR1_COMP1_OFFSET 0x73 ++#define TANTOS_3G_TUPR1_COMP1_SHIFT 8 ++#define TANTOS_3G_TUPR1_COMP1_SIZE 2 ++/* Bit: 'PRANGE1' */ ++/* Description: 'Port Range in TCP/UDP' */ ++#define TANTOS_3G_TUPR1_PRANGE1_OFFSET 0x73 ++#define TANTOS_3G_TUPR1_PRANGE1_SHIFT 0 ++#define TANTOS_3G_TUPR1_PRANGE1_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Range 2' */ ++/* Bit: 'ATUF2' */ ++/* Description: 'Action for TCP/UDP Port Filter 2' */ ++#define TANTOS_3G_TUPR2_ATUF2_OFFSET 0x75 ++#define TANTOS_3G_TUPR2_ATUF2_SHIFT 12 ++#define TANTOS_3G_TUPR2_ATUF2_SIZE 2 ++/* Bit: 'TUPF2' */ ++/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 2' */ ++#define TANTOS_3G_TUPR2_TUPF2_OFFSET 0x75 ++#define TANTOS_3G_TUPR2_TUPF2_SHIFT 10 ++#define TANTOS_3G_TUPR2_TUPF2_SIZE 2 ++/* Bit: 'COMP2' */ ++/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ ++#define TANTOS_3G_TUPR2_COMP2_OFFSET 0x75 ++#define TANTOS_3G_TUPR2_COMP2_SHIFT 8 ++#define TANTOS_3G_TUPR2_COMP2_SIZE 2 ++/* Bit: 'PRANGE2' */ ++/* Description: 'Port Range in TCP/UDP' */ ++#define TANTOS_3G_TUPR2_PRANGE2_OFFSET 0x75 ++#define TANTOS_3G_TUPR2_PRANGE2_SHIFT 0 ++#define TANTOS_3G_TUPR2_PRANGE2_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Range 3' */ ++/* Bit: 'ATUF3' */ ++/* Description: 'Action for TCP/UDP Port Filter 3' */ ++#define TANTOS_3G_TUPR3_ATUF3_OFFSET 0x77 ++#define TANTOS_3G_TUPR3_ATUF3_SHIFT 12 ++#define TANTOS_3G_TUPR3_ATUF3_SIZE 2 ++/* Bit: 'TUPF3' */ ++/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 3' */ ++#define TANTOS_3G_TUPR3_TUPF3_OFFSET 0x77 ++#define TANTOS_3G_TUPR3_TUPF3_SHIFT 10 ++#define TANTOS_3G_TUPR3_TUPF3_SIZE 2 ++/* Bit: 'COMP3' */ ++/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ ++#define TANTOS_3G_TUPR3_COMP3_OFFSET 0x77 ++#define TANTOS_3G_TUPR3_COMP3_SHIFT 8 ++#define TANTOS_3G_TUPR3_COMP3_SIZE 2 ++/* Bit: 'PRANGE3' */ ++/* Description: 'Port Range in TCP/UDP' */ ++#define TANTOS_3G_TUPR3_PRANGE3_OFFSET 0x77 ++#define TANTOS_3G_TUPR3_PRANGE3_SHIFT 0 ++#define TANTOS_3G_TUPR3_PRANGE3_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Range 4' */ ++/* Bit: 'ATUF4' */ ++/* Description: 'Action for TCP/UDP Port Filter 4' */ ++#define TANTOS_3G_TUPR4_ATUF4_OFFSET 0x79 ++#define TANTOS_3G_TUPR4_ATUF4_SHIFT 12 ++#define TANTOS_3G_TUPR4_ATUF4_SIZE 2 ++/* Bit: 'TUPF4' */ ++/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 4' */ ++#define TANTOS_3G_TUPR4_TUPF4_OFFSET 0x79 ++#define TANTOS_3G_TUPR4_TUPF4_SHIFT 10 ++#define TANTOS_3G_TUPR4_TUPF4_SIZE 2 ++/* Bit: 'COMP4' */ ++/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ ++#define TANTOS_3G_TUPR4_COMP4_OFFSET 0x79 ++#define TANTOS_3G_TUPR4_COMP4_SHIFT 8 ++#define TANTOS_3G_TUPR4_COMP4_SIZE 2 ++/* Bit: 'PRANGE4' */ ++/* Description: 'Port Range in TCP/UDP' */ ++#define TANTOS_3G_TUPR4_PRANGE4_OFFSET 0x79 ++#define TANTOS_3G_TUPR4_PRANGE4_SHIFT 0 ++#define TANTOS_3G_TUPR4_PRANGE4_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Range 5' */ ++/* Bit: 'ATUF5' */ ++/* Description: 'Action for TCP/UDP Port Filter 5' */ ++#define TANTOS_3G_TUPR5_ATUF5_OFFSET 0x7B ++#define TANTOS_3G_TUPR5_ATUF5_SHIFT 12 ++#define TANTOS_3G_TUPR5_ATUF5_SIZE 2 ++/* Bit: 'TUPF5' */ ++/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 5' */ ++#define TANTOS_3G_TUPR5_TUPF5_OFFSET 0x7B ++#define TANTOS_3G_TUPR5_TUPF5_SHIFT 10 ++#define TANTOS_3G_TUPR5_TUPF5_SIZE 2 ++/* Bit: 'COMP5' */ ++/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ ++#define TANTOS_3G_TUPR5_COMP5_OFFSET 0x7B ++#define TANTOS_3G_TUPR5_COMP5_SHIFT 8 ++#define TANTOS_3G_TUPR5_COMP5_SIZE 2 ++/* Bit: 'PRANGE5' */ ++/* Description: 'Port Range in TCP/UDP' */ ++#define TANTOS_3G_TUPR5_PRANGE5_OFFSET 0x7B ++#define TANTOS_3G_TUPR5_PRANGE5_SHIFT 0 ++#define TANTOS_3G_TUPR5_PRANGE5_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Range 6' */ ++/* Bit: 'ATUF6' */ ++/* Description: 'Action for TCP/UDP Port Filter 6' */ ++#define TANTOS_3G_TUPR6_ATUF6_OFFSET 0x7D ++#define TANTOS_3G_TUPR6_ATUF6_SHIFT 12 ++#define TANTOS_3G_TUPR6_ATUF6_SIZE 2 ++/* Bit: 'TUPF6' */ ++/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 6' */ ++#define TANTOS_3G_TUPR6_TUPF6_OFFSET 0x7D ++#define TANTOS_3G_TUPR6_TUPF6_SHIFT 10 ++#define TANTOS_3G_TUPR6_TUPF6_SIZE 2 ++/* Bit: 'COMP6' */ ++/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ ++#define TANTOS_3G_TUPR6_COMP6_OFFSET 0x7D ++#define TANTOS_3G_TUPR6_COMP6_SHIFT 8 ++#define TANTOS_3G_TUPR6_COMP6_SIZE 2 ++/* Bit: 'PRANGE6' */ ++/* Description: 'Port Range in TCP/UDP' */ ++#define TANTOS_3G_TUPR6_PRANGE6_OFFSET 0x7D ++#define TANTOS_3G_TUPR6_PRANGE6_SHIFT 0 ++#define TANTOS_3G_TUPR6_PRANGE6_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'TCP/UDP Port Range 7' */ ++/* Bit: 'ATUF7' */ ++/* Description: 'Action for TCP/UDP Port Filter 7' */ ++#define TANTOS_3G_TUPR7_ATUF7_OFFSET 0x7F ++#define TANTOS_3G_TUPR7_ATUF7_SHIFT 12 ++#define TANTOS_3G_TUPR7_ATUF7_SIZE 2 ++/* Bit: 'TUPF7' */ ++/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 7' */ ++#define TANTOS_3G_TUPR7_TUPF7_OFFSET 0x7F ++#define TANTOS_3G_TUPR7_TUPF7_SHIFT 10 ++#define TANTOS_3G_TUPR7_TUPF7_SIZE 2 ++/* Bit: 'COMP7' */ ++/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ ++#define TANTOS_3G_TUPR7_COMP7_OFFSET 0x7F ++#define TANTOS_3G_TUPR7_COMP7_SHIFT 8 ++#define TANTOS_3G_TUPR7_COMP7_SIZE 2 ++/* Bit: 'PRANGE7' */ ++/* Description: 'Port Range in TCP/UDP' */ ++#define TANTOS_3G_TUPR7_PRANGE7_OFFSET 0x7F ++#define TANTOS_3G_TUPR7_PRANGE7_SHIFT 0 ++#define TANTOS_3G_TUPR7_PRANGE7_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserved DA(0180C2000001~0180C2000000) control register' */ ++/* Bit: 'RA01_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_01_00_RA01_VALID_OFFSET 0x90 ++#define TANTOS_3G_RA_01_00_RA01_VALID_SHIFT 15 ++#define TANTOS_3G_RA_01_00_RA01_VALID_SIZE 1 ++/* Bit: 'RA01_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_01_00_RA01_SPAN_OFFSET 0x90 ++#define TANTOS_3G_RA_01_00_RA01_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_01_00_RA01_SPAN_SIZE 1 ++/* Bit: 'RA01_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_01_00_RA01_MG_OFFSET 0x90 ++#define TANTOS_3G_RA_01_00_RA01_MG_SHIFT 13 ++#define TANTOS_3G_RA_01_00_RA01_MG_SIZE 1 ++/* Bit: 'RA01_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_01_00_RA01_CV_OFFSET 0x90 ++#define TANTOS_3G_RA_01_00_RA01_CV_SHIFT 12 ++#define TANTOS_3G_RA_01_00_RA01_CV_SIZE 1 ++/* Bit: 'RA01_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_01_00_RA01_TXTAG_OFFSET 0x90 ++#define TANTOS_3G_RA_01_00_RA01_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_01_00_RA01_TXTAG_SIZE 2 ++/* Bit: 'RA01_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_01_00_RA01_ACT_OFFSET 0x90 ++#define TANTOS_3G_RA_01_00_RA01_ACT_SHIFT 8 ++#define TANTOS_3G_RA_01_00_RA01_ACT_SIZE 2 ++/* Bit: 'RA00_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_01_00_RA00_VALID_OFFSET 0x90 ++#define TANTOS_3G_RA_01_00_RA00_VALID_SHIFT 7 ++#define TANTOS_3G_RA_01_00_RA00_VALID_SIZE 1 ++/* Bit: 'RA00_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_01_00_RA00_SPAN_OFFSET 0x90 ++#define TANTOS_3G_RA_01_00_RA00_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_01_00_RA00_SPAN_SIZE 1 ++/* Bit: 'RA00_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_01_00_RA00_MG_OFFSET 0x90 ++#define TANTOS_3G_RA_01_00_RA00_MG_SHIFT 5 ++#define TANTOS_3G_RA_01_00_RA00_MG_SIZE 1 ++/* Bit: 'RA00_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_01_00_RA00_CV_OFFSET 0x90 ++#define TANTOS_3G_RA_01_00_RA00_CV_SHIFT 4 ++#define TANTOS_3G_RA_01_00_RA00_CV_SIZE 1 ++/* Bit: 'RA00_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_01_00_RA00_TXTAG_OFFSET 0x90 ++#define TANTOS_3G_RA_01_00_RA00_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_01_00_RA00_TXTAG_SIZE 2 ++/* Bit: 'RA00_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_01_00_RA00_ACT_OFFSET 0x90 ++#define TANTOS_3G_RA_01_00_RA00_ACT_SHIFT 0 ++#define TANTOS_3G_RA_01_00_RA00_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C2000003~0180C2000002' */ ++/* Bit: 'RA23_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_03_02_RA23_VALID_OFFSET 0x91 ++#define TANTOS_3G_RA_03_02_RA23_VALID_SHIFT 15 ++#define TANTOS_3G_RA_03_02_RA23_VALID_SIZE 1 ++/* Bit: 'RA23_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_03_02_RA23_SPAN_OFFSET 0x91 ++#define TANTOS_3G_RA_03_02_RA23_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_03_02_RA23_SPAN_SIZE 1 ++/* Bit: 'RA23_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_03_02_RA23_MG_OFFSET 0x91 ++#define TANTOS_3G_RA_03_02_RA23_MG_SHIFT 13 ++#define TANTOS_3G_RA_03_02_RA23_MG_SIZE 1 ++/* Bit: 'RA23_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_03_02_RA23_CV_OFFSET 0x91 ++#define TANTOS_3G_RA_03_02_RA23_CV_SHIFT 12 ++#define TANTOS_3G_RA_03_02_RA23_CV_SIZE 1 ++/* Bit: 'RA23_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_03_02_RA23_TXTAG_OFFSET 0x91 ++#define TANTOS_3G_RA_03_02_RA23_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_03_02_RA23_TXTAG_SIZE 2 ++/* Bit: 'RA23_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_03_02_RA23_ACT_OFFSET 0x91 ++#define TANTOS_3G_RA_03_02_RA23_ACT_SHIFT 8 ++#define TANTOS_3G_RA_03_02_RA23_ACT_SIZE 2 ++/* Bit: 'RA20_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_03_02_RA20_VALID_OFFSET 0x91 ++#define TANTOS_3G_RA_03_02_RA20_VALID_SHIFT 7 ++#define TANTOS_3G_RA_03_02_RA20_VALID_SIZE 1 ++/* Bit: 'RA20_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_03_02_RA20_SPAN_OFFSET 0x91 ++#define TANTOS_3G_RA_03_02_RA20_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_03_02_RA20_SPAN_SIZE 1 ++/* Bit: 'RA20_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_03_02_RA20_MG_OFFSET 0x91 ++#define TANTOS_3G_RA_03_02_RA20_MG_SHIFT 5 ++#define TANTOS_3G_RA_03_02_RA20_MG_SIZE 1 ++/* Bit: 'RA20_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_03_02_RA20_CV_OFFSET 0x91 ++#define TANTOS_3G_RA_03_02_RA20_CV_SHIFT 4 ++#define TANTOS_3G_RA_03_02_RA20_CV_SIZE 1 ++/* Bit: 'RA20_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_03_02_RA20_TXTAG_OFFSET 0x91 ++#define TANTOS_3G_RA_03_02_RA20_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_03_02_RA20_TXTAG_SIZE 2 ++/* Bit: 'RA20_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_03_02_RA20_ACT_OFFSET 0x91 ++#define TANTOS_3G_RA_03_02_RA20_ACT_SHIFT 0 ++#define TANTOS_3G_RA_03_02_RA20_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C2000005~0180C2000004' */ ++/* Bit: 'RA45_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_05_04_RA45_VALID_OFFSET 0x92 ++#define TANTOS_3G_RA_05_04_RA45_VALID_SHIFT 15 ++#define TANTOS_3G_RA_05_04_RA45_VALID_SIZE 1 ++/* Bit: 'RA45_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_05_04_RA45_SPAN_OFFSET 0x92 ++#define TANTOS_3G_RA_05_04_RA45_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_05_04_RA45_SPAN_SIZE 1 ++/* Bit: 'RA45_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_05_04_RA45_MG_OFFSET 0x92 ++#define TANTOS_3G_RA_05_04_RA45_MG_SHIFT 13 ++#define TANTOS_3G_RA_05_04_RA45_MG_SIZE 1 ++/* Bit: 'RA45_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_05_04_RA45_CV_OFFSET 0x92 ++#define TANTOS_3G_RA_05_04_RA45_CV_SHIFT 12 ++#define TANTOS_3G_RA_05_04_RA45_CV_SIZE 1 ++/* Bit: 'RA45_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_05_04_RA45_TXTAG_OFFSET 0x92 ++#define TANTOS_3G_RA_05_04_RA45_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_05_04_RA45_TXTAG_SIZE 2 ++/* Bit: 'RA45_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_05_04_RA45_ACT_OFFSET 0x92 ++#define TANTOS_3G_RA_05_04_RA45_ACT_SHIFT 8 ++#define TANTOS_3G_RA_05_04_RA45_ACT_SIZE 2 ++/* Bit: 'RA40_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_05_04_RA40_VALID_OFFSET 0x92 ++#define TANTOS_3G_RA_05_04_RA40_VALID_SHIFT 7 ++#define TANTOS_3G_RA_05_04_RA40_VALID_SIZE 1 ++/* Bit: 'RA40_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_05_04_RA40_SPAN_OFFSET 0x92 ++#define TANTOS_3G_RA_05_04_RA40_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_05_04_RA40_SPAN_SIZE 1 ++/* Bit: 'RA40_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_05_04_RA40_MG_OFFSET 0x92 ++#define TANTOS_3G_RA_05_04_RA40_MG_SHIFT 5 ++#define TANTOS_3G_RA_05_04_RA40_MG_SIZE 1 ++/* Bit: 'RA40_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_05_04_RA40_CV_OFFSET 0x92 ++#define TANTOS_3G_RA_05_04_RA40_CV_SHIFT 4 ++#define TANTOS_3G_RA_05_04_RA40_CV_SIZE 1 ++/* Bit: 'RA40_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_05_04_RA40_TXTAG_OFFSET 0x92 ++#define TANTOS_3G_RA_05_04_RA40_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_05_04_RA40_TXTAG_SIZE 2 ++/* Bit: 'RA40_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_05_04_RA40_ACT_OFFSET 0x92 ++#define TANTOS_3G_RA_05_04_RA40_ACT_SHIFT 0 ++#define TANTOS_3G_RA_05_04_RA40_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C2000007~0180C2000006' */ ++/* Bit: 'RA67_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_07_06_RA67_VALID_OFFSET 0x93 ++#define TANTOS_3G_RA_07_06_RA67_VALID_SHIFT 15 ++#define TANTOS_3G_RA_07_06_RA67_VALID_SIZE 1 ++/* Bit: 'RA67_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_07_06_RA67_SPAN_OFFSET 0x93 ++#define TANTOS_3G_RA_07_06_RA67_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_07_06_RA67_SPAN_SIZE 1 ++/* Bit: 'RA67_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_07_06_RA67_MG_OFFSET 0x93 ++#define TANTOS_3G_RA_07_06_RA67_MG_SHIFT 13 ++#define TANTOS_3G_RA_07_06_RA67_MG_SIZE 1 ++/* Bit: 'RA67_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_07_06_RA67_CV_OFFSET 0x93 ++#define TANTOS_3G_RA_07_06_RA67_CV_SHIFT 12 ++#define TANTOS_3G_RA_07_06_RA67_CV_SIZE 1 ++/* Bit: 'RA67_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_07_06_RA67_TXTAG_OFFSET 0x93 ++#define TANTOS_3G_RA_07_06_RA67_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_07_06_RA67_TXTAG_SIZE 2 ++/* Bit: 'RA67_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_07_06_RA67_ACT_OFFSET 0x93 ++#define TANTOS_3G_RA_07_06_RA67_ACT_SHIFT 8 ++#define TANTOS_3G_RA_07_06_RA67_ACT_SIZE 2 ++/* Bit: 'RA60_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_07_06_RA60_VALID_OFFSET 0x93 ++#define TANTOS_3G_RA_07_06_RA60_VALID_SHIFT 7 ++#define TANTOS_3G_RA_07_06_RA60_VALID_SIZE 1 ++/* Bit: 'RA60_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_07_06_RA60_SPAN_OFFSET 0x93 ++#define TANTOS_3G_RA_07_06_RA60_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_07_06_RA60_SPAN_SIZE 1 ++/* Bit: 'RA60_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_07_06_RA60_MG_OFFSET 0x93 ++#define TANTOS_3G_RA_07_06_RA60_MG_SHIFT 5 ++#define TANTOS_3G_RA_07_06_RA60_MG_SIZE 1 ++/* Bit: 'RA60_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_07_06_RA60_CV_OFFSET 0x93 ++#define TANTOS_3G_RA_07_06_RA60_CV_SHIFT 4 ++#define TANTOS_3G_RA_07_06_RA60_CV_SIZE 1 ++/* Bit: 'RA60_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_07_06_RA60_TXTAG_OFFSET 0x93 ++#define TANTOS_3G_RA_07_06_RA60_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_07_06_RA60_TXTAG_SIZE 2 ++/* Bit: 'RA60_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_07_06_RA60_ACT_OFFSET 0x93 ++#define TANTOS_3G_RA_07_06_RA60_ACT_SHIFT 0 ++#define TANTOS_3G_RA_07_06_RA60_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C2000009~0180C2000008' */ ++/* Bit: 'RA89_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_09_08_RA89_VALID_OFFSET 0x94 ++#define TANTOS_3G_RA_09_08_RA89_VALID_SHIFT 15 ++#define TANTOS_3G_RA_09_08_RA89_VALID_SIZE 1 ++/* Bit: 'RA89_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_09_08_RA89_SPAN_OFFSET 0x94 ++#define TANTOS_3G_RA_09_08_RA89_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_09_08_RA89_SPAN_SIZE 1 ++/* Bit: 'RA89_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_09_08_RA89_MG_OFFSET 0x94 ++#define TANTOS_3G_RA_09_08_RA89_MG_SHIFT 13 ++#define TANTOS_3G_RA_09_08_RA89_MG_SIZE 1 ++/* Bit: 'RA89_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_09_08_RA89_CV_OFFSET 0x94 ++#define TANTOS_3G_RA_09_08_RA89_CV_SHIFT 12 ++#define TANTOS_3G_RA_09_08_RA89_CV_SIZE 1 ++/* Bit: 'RA89_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_09_08_RA89_TXTAG_OFFSET 0x94 ++#define TANTOS_3G_RA_09_08_RA89_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_09_08_RA89_TXTAG_SIZE 2 ++/* Bit: 'RA89_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_09_08_RA89_ACT_OFFSET 0x94 ++#define TANTOS_3G_RA_09_08_RA89_ACT_SHIFT 8 ++#define TANTOS_3G_RA_09_08_RA89_ACT_SIZE 2 ++/* Bit: 'RA80_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_09_08_RA80_VALID_OFFSET 0x94 ++#define TANTOS_3G_RA_09_08_RA80_VALID_SHIFT 7 ++#define TANTOS_3G_RA_09_08_RA80_VALID_SIZE 1 ++/* Bit: 'RA80_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_09_08_RA80_SPAN_OFFSET 0x94 ++#define TANTOS_3G_RA_09_08_RA80_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_09_08_RA80_SPAN_SIZE 1 ++/* Bit: 'RA80_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_09_08_RA80_MG_OFFSET 0x94 ++#define TANTOS_3G_RA_09_08_RA80_MG_SHIFT 5 ++#define TANTOS_3G_RA_09_08_RA80_MG_SIZE 1 ++/* Bit: 'RA80_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_09_08_RA80_CV_OFFSET 0x94 ++#define TANTOS_3G_RA_09_08_RA80_CV_SHIFT 4 ++#define TANTOS_3G_RA_09_08_RA80_CV_SIZE 1 ++/* Bit: 'RA80_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_09_08_RA80_TXTAG_OFFSET 0x94 ++#define TANTOS_3G_RA_09_08_RA80_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_09_08_RA80_TXTAG_SIZE 2 ++/* Bit: 'RA80_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_09_08_RA80_ACT_OFFSET 0x94 ++#define TANTOS_3G_RA_09_08_RA80_ACT_SHIFT 0 ++#define TANTOS_3G_RA_09_08_RA80_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C200000B~0180C200000A' */ ++/* Bit: 'RA1101_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_0B_0A_RA1101_VALID_OFFSET 0x95 ++#define TANTOS_3G_RA_0B_0A_RA1101_VALID_SHIFT 15 ++#define TANTOS_3G_RA_0B_0A_RA1101_VALID_SIZE 1 ++/* Bit: 'RA1101_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_0B_0A_RA1101_SPAN_OFFSET 0x95 ++#define TANTOS_3G_RA_0B_0A_RA1101_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_0B_0A_RA1101_SPAN_SIZE 1 ++/* Bit: 'RA1101_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_0B_0A_RA1101_MG_OFFSET 0x95 ++#define TANTOS_3G_RA_0B_0A_RA1101_MG_SHIFT 13 ++#define TANTOS_3G_RA_0B_0A_RA1101_MG_SIZE 1 ++/* Bit: 'RA1101_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_0B_0A_RA1101_CV_OFFSET 0x95 ++#define TANTOS_3G_RA_0B_0A_RA1101_CV_SHIFT 12 ++#define TANTOS_3G_RA_0B_0A_RA1101_CV_SIZE 1 ++/* Bit: 'RA1101_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_0B_0A_RA1101_TXTAG_OFFSET 0x95 ++#define TANTOS_3G_RA_0B_0A_RA1101_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_0B_0A_RA1101_TXTAG_SIZE 2 ++/* Bit: 'RA1101_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_0B_0A_RA1101_ACT_OFFSET 0x95 ++#define TANTOS_3G_RA_0B_0A_RA1101_ACT_SHIFT 8 ++#define TANTOS_3G_RA_0B_0A_RA1101_ACT_SIZE 2 ++/* Bit: 'RA1100_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_0B_0A_RA1100_VALID_OFFSET 0x95 ++#define TANTOS_3G_RA_0B_0A_RA1100_VALID_SHIFT 7 ++#define TANTOS_3G_RA_0B_0A_RA1100_VALID_SIZE 1 ++/* Bit: 'RA1100_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_0B_0A_RA1100_SPAN_OFFSET 0x95 ++#define TANTOS_3G_RA_0B_0A_RA1100_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_0B_0A_RA1100_SPAN_SIZE 1 ++/* Bit: 'RA1100_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_0B_0A_RA1100_MG_OFFSET 0x95 ++#define TANTOS_3G_RA_0B_0A_RA1100_MG_SHIFT 5 ++#define TANTOS_3G_RA_0B_0A_RA1100_MG_SIZE 1 ++/* Bit: 'RA1100_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_0B_0A_RA1100_CV_OFFSET 0x95 ++#define TANTOS_3G_RA_0B_0A_RA1100_CV_SHIFT 4 ++#define TANTOS_3G_RA_0B_0A_RA1100_CV_SIZE 1 ++/* Bit: 'RA1100_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_0B_0A_RA1100_TXTAG_OFFSET 0x95 ++#define TANTOS_3G_RA_0B_0A_RA1100_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_0B_0A_RA1100_TXTAG_SIZE 2 ++/* Bit: 'RA1100_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_0B_0A_RA1100_ACT_OFFSET 0x95 ++#define TANTOS_3G_RA_0B_0A_RA1100_ACT_SHIFT 0 ++#define TANTOS_3G_RA_0B_0A_RA1100_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C200000D~0180C200000C' */ ++/* Bit: 'RA1321_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_0D_0C_RA1321_VALID_OFFSET 0x96 ++#define TANTOS_3G_RA_0D_0C_RA1321_VALID_SHIFT 15 ++#define TANTOS_3G_RA_0D_0C_RA1321_VALID_SIZE 1 ++/* Bit: 'RA1321_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_0D_0C_RA1321_SPAN_OFFSET 0x96 ++#define TANTOS_3G_RA_0D_0C_RA1321_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_0D_0C_RA1321_SPAN_SIZE 1 ++/* Bit: 'RA1321_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_0D_0C_RA1321_MG_OFFSET 0x96 ++#define TANTOS_3G_RA_0D_0C_RA1321_MG_SHIFT 13 ++#define TANTOS_3G_RA_0D_0C_RA1321_MG_SIZE 1 ++/* Bit: 'RA1321_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_0D_0C_RA1321_CV_OFFSET 0x96 ++#define TANTOS_3G_RA_0D_0C_RA1321_CV_SHIFT 12 ++#define TANTOS_3G_RA_0D_0C_RA1321_CV_SIZE 1 ++/* Bit: 'RA1321_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_0D_0C_RA1321_TXTAG_OFFSET 0x96 ++#define TANTOS_3G_RA_0D_0C_RA1321_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_0D_0C_RA1321_TXTAG_SIZE 2 ++/* Bit: 'RA1321_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_0D_0C_RA1321_ACT_OFFSET 0x96 ++#define TANTOS_3G_RA_0D_0C_RA1321_ACT_SHIFT 8 ++#define TANTOS_3G_RA_0D_0C_RA1321_ACT_SIZE 2 ++/* Bit: 'RA1320_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_0D_0C_RA1320_VALID_OFFSET 0x96 ++#define TANTOS_3G_RA_0D_0C_RA1320_VALID_SHIFT 7 ++#define TANTOS_3G_RA_0D_0C_RA1320_VALID_SIZE 1 ++/* Bit: 'RA1320_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_0D_0C_RA1320_SPAN_OFFSET 0x96 ++#define TANTOS_3G_RA_0D_0C_RA1320_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_0D_0C_RA1320_SPAN_SIZE 1 ++/* Bit: 'RA1320_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_0D_0C_RA1320_MG_OFFSET 0x96 ++#define TANTOS_3G_RA_0D_0C_RA1320_MG_SHIFT 5 ++#define TANTOS_3G_RA_0D_0C_RA1320_MG_SIZE 1 ++/* Bit: 'RA1320_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_0D_0C_RA1320_CV_OFFSET 0x96 ++#define TANTOS_3G_RA_0D_0C_RA1320_CV_SHIFT 4 ++#define TANTOS_3G_RA_0D_0C_RA1320_CV_SIZE 1 ++/* Bit: 'RA1320_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_0D_0C_RA1320_TXTAG_OFFSET 0x96 ++#define TANTOS_3G_RA_0D_0C_RA1320_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_0D_0C_RA1320_TXTAG_SIZE 2 ++/* Bit: 'RA1320_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_0D_0C_RA1320_ACT_OFFSET 0x96 ++#define TANTOS_3G_RA_0D_0C_RA1320_ACT_SHIFT 0 ++#define TANTOS_3G_RA_0D_0C_RA1320_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C200000F~0180C200000E' */ ++/* Bit: 'RA1541_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_0F_0E_RA1541_VALID_OFFSET 0x97 ++#define TANTOS_3G_RA_0F_0E_RA1541_VALID_SHIFT 15 ++#define TANTOS_3G_RA_0F_0E_RA1541_VALID_SIZE 1 ++/* Bit: 'RA1541_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_0F_0E_RA1541_SPAN_OFFSET 0x97 ++#define TANTOS_3G_RA_0F_0E_RA1541_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_0F_0E_RA1541_SPAN_SIZE 1 ++/* Bit: 'RA1541_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_0F_0E_RA1541_MG_OFFSET 0x97 ++#define TANTOS_3G_RA_0F_0E_RA1541_MG_SHIFT 13 ++#define TANTOS_3G_RA_0F_0E_RA1541_MG_SIZE 1 ++/* Bit: 'RA1541_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_0F_0E_RA1541_CV_OFFSET 0x97 ++#define TANTOS_3G_RA_0F_0E_RA1541_CV_SHIFT 12 ++#define TANTOS_3G_RA_0F_0E_RA1541_CV_SIZE 1 ++/* Bit: 'RA1541_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_0F_0E_RA1541_TXTAG_OFFSET 0x97 ++#define TANTOS_3G_RA_0F_0E_RA1541_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_0F_0E_RA1541_TXTAG_SIZE 2 ++/* Bit: 'RA1541_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_0F_0E_RA1541_ACT_OFFSET 0x97 ++#define TANTOS_3G_RA_0F_0E_RA1541_ACT_SHIFT 8 ++#define TANTOS_3G_RA_0F_0E_RA1541_ACT_SIZE 2 ++/* Bit: 'RA1540_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_0F_0E_RA1540_VALID_OFFSET 0x97 ++#define TANTOS_3G_RA_0F_0E_RA1540_VALID_SHIFT 7 ++#define TANTOS_3G_RA_0F_0E_RA1540_VALID_SIZE 1 ++/* Bit: 'RA1540_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_0F_0E_RA1540_SPAN_OFFSET 0x97 ++#define TANTOS_3G_RA_0F_0E_RA1540_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_0F_0E_RA1540_SPAN_SIZE 1 ++/* Bit: 'RA1540_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_0F_0E_RA1540_MG_OFFSET 0x97 ++#define TANTOS_3G_RA_0F_0E_RA1540_MG_SHIFT 5 ++#define TANTOS_3G_RA_0F_0E_RA1540_MG_SIZE 1 ++/* Bit: 'RA1540_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_0F_0E_RA1540_CV_OFFSET 0x97 ++#define TANTOS_3G_RA_0F_0E_RA1540_CV_SHIFT 4 ++#define TANTOS_3G_RA_0F_0E_RA1540_CV_SIZE 1 ++/* Bit: 'RA1540_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_0F_0E_RA1540_TXTAG_OFFSET 0x97 ++#define TANTOS_3G_RA_0F_0E_RA1540_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_0F_0E_RA1540_TXTAG_SIZE 2 ++/* Bit: 'RA1540_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_0F_0E_RA1540_ACT_OFFSET 0x97 ++#define TANTOS_3G_RA_0F_0E_RA1540_ACT_SHIFT 0 ++#define TANTOS_3G_RA_0F_0E_RA1540_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C2000011~0180C2000010' */ ++/* Bit: 'RA1761_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_11_10_RA1761_VALID_OFFSET 0x98 ++#define TANTOS_3G_RA_11_10_RA1761_VALID_SHIFT 15 ++#define TANTOS_3G_RA_11_10_RA1761_VALID_SIZE 1 ++/* Bit: 'RA1761_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_11_10_RA1761_SPAN_OFFSET 0x98 ++#define TANTOS_3G_RA_11_10_RA1761_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_11_10_RA1761_SPAN_SIZE 1 ++/* Bit: 'RA1761_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_11_10_RA1761_MG_OFFSET 0x98 ++#define TANTOS_3G_RA_11_10_RA1761_MG_SHIFT 13 ++#define TANTOS_3G_RA_11_10_RA1761_MG_SIZE 1 ++/* Bit: 'RA1761_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_11_10_RA1761_CV_OFFSET 0x98 ++#define TANTOS_3G_RA_11_10_RA1761_CV_SHIFT 12 ++#define TANTOS_3G_RA_11_10_RA1761_CV_SIZE 1 ++/* Bit: 'RA1761_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_11_10_RA1761_TXTAG_OFFSET 0x98 ++#define TANTOS_3G_RA_11_10_RA1761_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_11_10_RA1761_TXTAG_SIZE 2 ++/* Bit: 'RA1761_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_11_10_RA1761_ACT_OFFSET 0x98 ++#define TANTOS_3G_RA_11_10_RA1761_ACT_SHIFT 8 ++#define TANTOS_3G_RA_11_10_RA1761_ACT_SIZE 2 ++/* Bit: 'RA1760_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_11_10_RA1760_VALID_OFFSET 0x98 ++#define TANTOS_3G_RA_11_10_RA1760_VALID_SHIFT 7 ++#define TANTOS_3G_RA_11_10_RA1760_VALID_SIZE 1 ++/* Bit: 'RA1760_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_11_10_RA1760_SPAN_OFFSET 0x98 ++#define TANTOS_3G_RA_11_10_RA1760_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_11_10_RA1760_SPAN_SIZE 1 ++/* Bit: 'RA1760_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_11_10_RA1760_MG_OFFSET 0x98 ++#define TANTOS_3G_RA_11_10_RA1760_MG_SHIFT 5 ++#define TANTOS_3G_RA_11_10_RA1760_MG_SIZE 1 ++/* Bit: 'RA1760_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_11_10_RA1760_CV_OFFSET 0x98 ++#define TANTOS_3G_RA_11_10_RA1760_CV_SHIFT 4 ++#define TANTOS_3G_RA_11_10_RA1760_CV_SIZE 1 ++/* Bit: 'RA1760_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_11_10_RA1760_TXTAG_OFFSET 0x98 ++#define TANTOS_3G_RA_11_10_RA1760_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_11_10_RA1760_TXTAG_SIZE 2 ++/* Bit: 'RA1760_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_11_10_RA1760_ACT_OFFSET 0x98 ++#define TANTOS_3G_RA_11_10_RA1760_ACT_SHIFT 0 ++#define TANTOS_3G_RA_11_10_RA1760_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C2000013~0180C2000012' */ ++/* Bit: 'RA1981_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_13_12_RA1981_VALID_OFFSET 0x99 ++#define TANTOS_3G_RA_13_12_RA1981_VALID_SHIFT 15 ++#define TANTOS_3G_RA_13_12_RA1981_VALID_SIZE 1 ++/* Bit: 'RA1981_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_13_12_RA1981_SPAN_OFFSET 0x99 ++#define TANTOS_3G_RA_13_12_RA1981_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_13_12_RA1981_SPAN_SIZE 1 ++/* Bit: 'RA1981_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_13_12_RA1981_MG_OFFSET 0x99 ++#define TANTOS_3G_RA_13_12_RA1981_MG_SHIFT 13 ++#define TANTOS_3G_RA_13_12_RA1981_MG_SIZE 1 ++/* Bit: 'RA1981_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_13_12_RA1981_CV_OFFSET 0x99 ++#define TANTOS_3G_RA_13_12_RA1981_CV_SHIFT 12 ++#define TANTOS_3G_RA_13_12_RA1981_CV_SIZE 1 ++/* Bit: 'RA1981_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_13_12_RA1981_TXTAG_OFFSET 0x99 ++#define TANTOS_3G_RA_13_12_RA1981_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_13_12_RA1981_TXTAG_SIZE 2 ++/* Bit: 'RA1981_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_13_12_RA1981_ACT_OFFSET 0x99 ++#define TANTOS_3G_RA_13_12_RA1981_ACT_SHIFT 8 ++#define TANTOS_3G_RA_13_12_RA1981_ACT_SIZE 2 ++/* Bit: 'RA1980_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_13_12_RA1980_VALID_OFFSET 0x99 ++#define TANTOS_3G_RA_13_12_RA1980_VALID_SHIFT 7 ++#define TANTOS_3G_RA_13_12_RA1980_VALID_SIZE 1 ++/* Bit: 'RA1980_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_13_12_RA1980_SPAN_OFFSET 0x99 ++#define TANTOS_3G_RA_13_12_RA1980_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_13_12_RA1980_SPAN_SIZE 1 ++/* Bit: 'RA1980_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_13_12_RA1980_MG_OFFSET 0x99 ++#define TANTOS_3G_RA_13_12_RA1980_MG_SHIFT 5 ++#define TANTOS_3G_RA_13_12_RA1980_MG_SIZE 1 ++/* Bit: 'RA1980_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_13_12_RA1980_CV_OFFSET 0x99 ++#define TANTOS_3G_RA_13_12_RA1980_CV_SHIFT 4 ++#define TANTOS_3G_RA_13_12_RA1980_CV_SIZE 1 ++/* Bit: 'RA1980_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_13_12_RA1980_TXTAG_OFFSET 0x99 ++#define TANTOS_3G_RA_13_12_RA1980_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_13_12_RA1980_TXTAG_SIZE 2 ++/* Bit: 'RA1980_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_13_12_RA1980_ACT_OFFSET 0x99 ++#define TANTOS_3G_RA_13_12_RA1980_ACT_SHIFT 0 ++#define TANTOS_3G_RA_13_12_RA1980_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C2000015~0180C2000014' */ ++/* Bit: 'RA2021_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_15_14_RA2021_VALID_OFFSET 0x9A ++#define TANTOS_3G_RA_15_14_RA2021_VALID_SHIFT 15 ++#define TANTOS_3G_RA_15_14_RA2021_VALID_SIZE 1 ++/* Bit: 'RA2021_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_15_14_RA2021_SPAN_OFFSET 0x9A ++#define TANTOS_3G_RA_15_14_RA2021_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_15_14_RA2021_SPAN_SIZE 1 ++/* Bit: 'RA2021_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_15_14_RA2021_MG_OFFSET 0x9A ++#define TANTOS_3G_RA_15_14_RA2021_MG_SHIFT 13 ++#define TANTOS_3G_RA_15_14_RA2021_MG_SIZE 1 ++/* Bit: 'RA2021_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_15_14_RA2021_CV_OFFSET 0x9A ++#define TANTOS_3G_RA_15_14_RA2021_CV_SHIFT 12 ++#define TANTOS_3G_RA_15_14_RA2021_CV_SIZE 1 ++/* Bit: 'RA2021_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_15_14_RA2021_TXTAG_OFFSET 0x9A ++#define TANTOS_3G_RA_15_14_RA2021_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_15_14_RA2021_TXTAG_SIZE 2 ++/* Bit: 'RA2021_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_15_14_RA2021_ACT_OFFSET 0x9A ++#define TANTOS_3G_RA_15_14_RA2021_ACT_SHIFT 8 ++#define TANTOS_3G_RA_15_14_RA2021_ACT_SIZE 2 ++/* Bit: 'RA200_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_15_14_RA200_VALID_OFFSET 0x9A ++#define TANTOS_3G_RA_15_14_RA200_VALID_SHIFT 7 ++#define TANTOS_3G_RA_15_14_RA200_VALID_SIZE 1 ++/* Bit: 'RA200_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_15_14_RA200_SPAN_OFFSET 0x9A ++#define TANTOS_3G_RA_15_14_RA200_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_15_14_RA200_SPAN_SIZE 1 ++/* Bit: 'RA200_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_15_14_RA200_MG_OFFSET 0x9A ++#define TANTOS_3G_RA_15_14_RA200_MG_SHIFT 5 ++#define TANTOS_3G_RA_15_14_RA200_MG_SIZE 1 ++/* Bit: 'RA200_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_15_14_RA200_CV_OFFSET 0x9A ++#define TANTOS_3G_RA_15_14_RA200_CV_SHIFT 4 ++#define TANTOS_3G_RA_15_14_RA200_CV_SIZE 1 ++/* Bit: 'RA200_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_15_14_RA200_TXTAG_OFFSET 0x9A ++#define TANTOS_3G_RA_15_14_RA200_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_15_14_RA200_TXTAG_SIZE 2 ++/* Bit: 'RA200_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_15_14_RA200_ACT_OFFSET 0x9A ++#define TANTOS_3G_RA_15_14_RA200_ACT_SHIFT 0 ++#define TANTOS_3G_RA_15_14_RA200_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C2000017~0180C2000016' */ ++/* Bit: 'RA2223_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_17_16_RA2223_VALID_OFFSET 0x9B ++#define TANTOS_3G_RA_17_16_RA2223_VALID_SHIFT 15 ++#define TANTOS_3G_RA_17_16_RA2223_VALID_SIZE 1 ++/* Bit: 'RA2223_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_17_16_RA2223_SPAN_OFFSET 0x9B ++#define TANTOS_3G_RA_17_16_RA2223_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_17_16_RA2223_SPAN_SIZE 1 ++/* Bit: 'RA2223_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_17_16_RA2223_MG_OFFSET 0x9B ++#define TANTOS_3G_RA_17_16_RA2223_MG_SHIFT 13 ++#define TANTOS_3G_RA_17_16_RA2223_MG_SIZE 1 ++/* Bit: 'RA2223_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_17_16_RA2223_CV_OFFSET 0x9B ++#define TANTOS_3G_RA_17_16_RA2223_CV_SHIFT 12 ++#define TANTOS_3G_RA_17_16_RA2223_CV_SIZE 1 ++/* Bit: 'RA2223_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_17_16_RA2223_TXTAG_OFFSET 0x9B ++#define TANTOS_3G_RA_17_16_RA2223_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_17_16_RA2223_TXTAG_SIZE 2 ++/* Bit: 'RA2223_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_17_16_RA2223_ACT_OFFSET 0x9B ++#define TANTOS_3G_RA_17_16_RA2223_ACT_SHIFT 8 ++#define TANTOS_3G_RA_17_16_RA2223_ACT_SIZE 2 ++/* Bit: 'RA220_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_17_16_RA220_VALID_OFFSET 0x9B ++#define TANTOS_3G_RA_17_16_RA220_VALID_SHIFT 7 ++#define TANTOS_3G_RA_17_16_RA220_VALID_SIZE 1 ++/* Bit: 'RA220_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_17_16_RA220_SPAN_OFFSET 0x9B ++#define TANTOS_3G_RA_17_16_RA220_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_17_16_RA220_SPAN_SIZE 1 ++/* Bit: 'RA220_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_17_16_RA220_MG_OFFSET 0x9B ++#define TANTOS_3G_RA_17_16_RA220_MG_SHIFT 5 ++#define TANTOS_3G_RA_17_16_RA220_MG_SIZE 1 ++/* Bit: 'RA220_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_17_16_RA220_CV_OFFSET 0x9B ++#define TANTOS_3G_RA_17_16_RA220_CV_SHIFT 4 ++#define TANTOS_3G_RA_17_16_RA220_CV_SIZE 1 ++/* Bit: 'RA220_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_17_16_RA220_TXTAG_OFFSET 0x9B ++#define TANTOS_3G_RA_17_16_RA220_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_17_16_RA220_TXTAG_SIZE 2 ++/* Bit: 'RA220_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_17_16_RA220_ACT_OFFSET 0x9B ++#define TANTOS_3G_RA_17_16_RA220_ACT_SHIFT 0 ++#define TANTOS_3G_RA_17_16_RA220_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C2000019~0180C2000018' */ ++/* Bit: 'RA2425_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_19_18_RA2425_VALID_OFFSET 0x9C ++#define TANTOS_3G_RA_19_18_RA2425_VALID_SHIFT 15 ++#define TANTOS_3G_RA_19_18_RA2425_VALID_SIZE 1 ++/* Bit: 'RA2425_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_19_18_RA2425_SPAN_OFFSET 0x9C ++#define TANTOS_3G_RA_19_18_RA2425_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_19_18_RA2425_SPAN_SIZE 1 ++/* Bit: 'RA2425_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_19_18_RA2425_MG_OFFSET 0x9C ++#define TANTOS_3G_RA_19_18_RA2425_MG_SHIFT 13 ++#define TANTOS_3G_RA_19_18_RA2425_MG_SIZE 1 ++/* Bit: 'RA2425_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_19_18_RA2425_CV_OFFSET 0x9C ++#define TANTOS_3G_RA_19_18_RA2425_CV_SHIFT 12 ++#define TANTOS_3G_RA_19_18_RA2425_CV_SIZE 1 ++/* Bit: 'RA2425_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_19_18_RA2425_TXTAG_OFFSET 0x9C ++#define TANTOS_3G_RA_19_18_RA2425_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_19_18_RA2425_TXTAG_SIZE 2 ++/* Bit: 'RA2425_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_19_18_RA2425_ACT_OFFSET 0x9C ++#define TANTOS_3G_RA_19_18_RA2425_ACT_SHIFT 8 ++#define TANTOS_3G_RA_19_18_RA2425_ACT_SIZE 2 ++/* Bit: 'RA240_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_19_18_RA240_VALID_OFFSET 0x9C ++#define TANTOS_3G_RA_19_18_RA240_VALID_SHIFT 7 ++#define TANTOS_3G_RA_19_18_RA240_VALID_SIZE 1 ++/* Bit: 'RA240_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_19_18_RA240_SPAN_OFFSET 0x9C ++#define TANTOS_3G_RA_19_18_RA240_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_19_18_RA240_SPAN_SIZE 1 ++/* Bit: 'RA240_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_19_18_RA240_MG_OFFSET 0x9C ++#define TANTOS_3G_RA_19_18_RA240_MG_SHIFT 5 ++#define TANTOS_3G_RA_19_18_RA240_MG_SIZE 1 ++/* Bit: 'RA240_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_19_18_RA240_CV_OFFSET 0x9C ++#define TANTOS_3G_RA_19_18_RA240_CV_SHIFT 4 ++#define TANTOS_3G_RA_19_18_RA240_CV_SIZE 1 ++/* Bit: 'RA240_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_19_18_RA240_TXTAG_OFFSET 0x9C ++#define TANTOS_3G_RA_19_18_RA240_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_19_18_RA240_TXTAG_SIZE 2 ++/* Bit: 'RA240_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_19_18_RA240_ACT_OFFSET 0x9C ++#define TANTOS_3G_RA_19_18_RA240_ACT_SHIFT 0 ++#define TANTOS_3G_RA_19_18_RA240_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C200001B~0180C200001A' */ ++/* Bit: 'RA2627_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_1B_1A_RA2627_VALID_OFFSET 0x9D ++#define TANTOS_3G_RA_1B_1A_RA2627_VALID_SHIFT 15 ++#define TANTOS_3G_RA_1B_1A_RA2627_VALID_SIZE 1 ++/* Bit: 'RA2627_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_1B_1A_RA2627_SPAN_OFFSET 0x9D ++#define TANTOS_3G_RA_1B_1A_RA2627_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_1B_1A_RA2627_SPAN_SIZE 1 ++/* Bit: 'RA2627_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_1B_1A_RA2627_MG_OFFSET 0x9D ++#define TANTOS_3G_RA_1B_1A_RA2627_MG_SHIFT 13 ++#define TANTOS_3G_RA_1B_1A_RA2627_MG_SIZE 1 ++/* Bit: 'RA2627_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_1B_1A_RA2627_CV_OFFSET 0x9D ++#define TANTOS_3G_RA_1B_1A_RA2627_CV_SHIFT 12 ++#define TANTOS_3G_RA_1B_1A_RA2627_CV_SIZE 1 ++/* Bit: 'RA2627_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_1B_1A_RA2627_TXTAG_OFFSET 0x9D ++#define TANTOS_3G_RA_1B_1A_RA2627_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_1B_1A_RA2627_TXTAG_SIZE 2 ++/* Bit: 'RA2627_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_1B_1A_RA2627_ACT_OFFSET 0x9D ++#define TANTOS_3G_RA_1B_1A_RA2627_ACT_SHIFT 8 ++#define TANTOS_3G_RA_1B_1A_RA2627_ACT_SIZE 2 ++/* Bit: 'RA260_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_1B_1A_RA260_VALID_OFFSET 0x9D ++#define TANTOS_3G_RA_1B_1A_RA260_VALID_SHIFT 7 ++#define TANTOS_3G_RA_1B_1A_RA260_VALID_SIZE 1 ++/* Bit: 'RA260_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_1B_1A_RA260_SPAN_OFFSET 0x9D ++#define TANTOS_3G_RA_1B_1A_RA260_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_1B_1A_RA260_SPAN_SIZE 1 ++/* Bit: 'RA260_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_1B_1A_RA260_MG_OFFSET 0x9D ++#define TANTOS_3G_RA_1B_1A_RA260_MG_SHIFT 5 ++#define TANTOS_3G_RA_1B_1A_RA260_MG_SIZE 1 ++/* Bit: 'RA260_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_1B_1A_RA260_CV_OFFSET 0x9D ++#define TANTOS_3G_RA_1B_1A_RA260_CV_SHIFT 4 ++#define TANTOS_3G_RA_1B_1A_RA260_CV_SIZE 1 ++/* Bit: 'RA260_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_1B_1A_RA260_TXTAG_OFFSET 0x9D ++#define TANTOS_3G_RA_1B_1A_RA260_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_1B_1A_RA260_TXTAG_SIZE 2 ++/* Bit: 'RA260_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_1B_1A_RA260_ACT_OFFSET 0x9D ++#define TANTOS_3G_RA_1B_1A_RA260_ACT_SHIFT 0 ++#define TANTOS_3G_RA_1B_1A_RA260_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C200001D~0180C200001C' */ ++/* Bit: 'RA2829_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_1D_1C_RA2829_VALID_OFFSET 0x9E ++#define TANTOS_3G_RA_1D_1C_RA2829_VALID_SHIFT 15 ++#define TANTOS_3G_RA_1D_1C_RA2829_VALID_SIZE 1 ++/* Bit: 'RA2829_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_1D_1C_RA2829_SPAN_OFFSET 0x9E ++#define TANTOS_3G_RA_1D_1C_RA2829_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_1D_1C_RA2829_SPAN_SIZE 1 ++/* Bit: 'RA2829_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_1D_1C_RA2829_MG_OFFSET 0x9E ++#define TANTOS_3G_RA_1D_1C_RA2829_MG_SHIFT 13 ++#define TANTOS_3G_RA_1D_1C_RA2829_MG_SIZE 1 ++/* Bit: 'RA2829_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_1D_1C_RA2829_CV_OFFSET 0x9E ++#define TANTOS_3G_RA_1D_1C_RA2829_CV_SHIFT 12 ++#define TANTOS_3G_RA_1D_1C_RA2829_CV_SIZE 1 ++/* Bit: 'RA2829_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_1D_1C_RA2829_TXTAG_OFFSET 0x9E ++#define TANTOS_3G_RA_1D_1C_RA2829_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_1D_1C_RA2829_TXTAG_SIZE 2 ++/* Bit: 'RA2829_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_1D_1C_RA2829_ACT_OFFSET 0x9E ++#define TANTOS_3G_RA_1D_1C_RA2829_ACT_SHIFT 8 ++#define TANTOS_3G_RA_1D_1C_RA2829_ACT_SIZE 2 ++/* Bit: 'RA280_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_1D_1C_RA280_VALID_OFFSET 0x9E ++#define TANTOS_3G_RA_1D_1C_RA280_VALID_SHIFT 7 ++#define TANTOS_3G_RA_1D_1C_RA280_VALID_SIZE 1 ++/* Bit: 'RA280_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_1D_1C_RA280_SPAN_OFFSET 0x9E ++#define TANTOS_3G_RA_1D_1C_RA280_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_1D_1C_RA280_SPAN_SIZE 1 ++/* Bit: 'RA280_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_1D_1C_RA280_MG_OFFSET 0x9E ++#define TANTOS_3G_RA_1D_1C_RA280_MG_SHIFT 5 ++#define TANTOS_3G_RA_1D_1C_RA280_MG_SIZE 1 ++/* Bit: 'RA280_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_1D_1C_RA280_CV_OFFSET 0x9E ++#define TANTOS_3G_RA_1D_1C_RA280_CV_SHIFT 4 ++#define TANTOS_3G_RA_1D_1C_RA280_CV_SIZE 1 ++/* Bit: 'RA280_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_1D_1C_RA280_TXTAG_OFFSET 0x9E ++#define TANTOS_3G_RA_1D_1C_RA280_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_1D_1C_RA280_TXTAG_SIZE 2 ++/* Bit: 'RA280_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_1D_1C_RA280_ACT_OFFSET 0x9E ++#define TANTOS_3G_RA_1D_1C_RA280_ACT_SHIFT 0 ++#define TANTOS_3G_RA_1D_1C_RA280_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C200001F~0180C200001E' */ ++/* Bit: 'RA3031_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_1F_1E_RA3031_VALID_OFFSET 0x9F ++#define TANTOS_3G_RA_1F_1E_RA3031_VALID_SHIFT 15 ++#define TANTOS_3G_RA_1F_1E_RA3031_VALID_SIZE 1 ++/* Bit: 'RA3031_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_1F_1E_RA3031_SPAN_OFFSET 0x9F ++#define TANTOS_3G_RA_1F_1E_RA3031_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_1F_1E_RA3031_SPAN_SIZE 1 ++/* Bit: 'RA3031_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_1F_1E_RA3031_MG_OFFSET 0x9F ++#define TANTOS_3G_RA_1F_1E_RA3031_MG_SHIFT 13 ++#define TANTOS_3G_RA_1F_1E_RA3031_MG_SIZE 1 ++/* Bit: 'RA3031_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_1F_1E_RA3031_CV_OFFSET 0x9F ++#define TANTOS_3G_RA_1F_1E_RA3031_CV_SHIFT 12 ++#define TANTOS_3G_RA_1F_1E_RA3031_CV_SIZE 1 ++/* Bit: 'RA3031_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_1F_1E_RA3031_TXTAG_OFFSET 0x9F ++#define TANTOS_3G_RA_1F_1E_RA3031_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_1F_1E_RA3031_TXTAG_SIZE 2 ++/* Bit: 'RA3031_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_1F_1E_RA3031_ACT_OFFSET 0x9F ++#define TANTOS_3G_RA_1F_1E_RA3031_ACT_SHIFT 8 ++#define TANTOS_3G_RA_1F_1E_RA3031_ACT_SIZE 2 ++/* Bit: 'RA300_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_1F_1E_RA300_VALID_OFFSET 0x9F ++#define TANTOS_3G_RA_1F_1E_RA300_VALID_SHIFT 7 ++#define TANTOS_3G_RA_1F_1E_RA300_VALID_SIZE 1 ++/* Bit: 'RA300_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_1F_1E_RA300_SPAN_OFFSET 0x9F ++#define TANTOS_3G_RA_1F_1E_RA300_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_1F_1E_RA300_SPAN_SIZE 1 ++/* Bit: 'RA300_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_1F_1E_RA300_MG_OFFSET 0x9F ++#define TANTOS_3G_RA_1F_1E_RA300_MG_SHIFT 5 ++#define TANTOS_3G_RA_1F_1E_RA300_MG_SIZE 1 ++/* Bit: 'RA300_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_1F_1E_RA300_CV_OFFSET 0x9F ++#define TANTOS_3G_RA_1F_1E_RA300_CV_SHIFT 4 ++#define TANTOS_3G_RA_1F_1E_RA300_CV_SIZE 1 ++/* Bit: 'RA300_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_1F_1E_RA300_TXTAG_OFFSET 0x9F ++#define TANTOS_3G_RA_1F_1E_RA300_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_1F_1E_RA300_TXTAG_SIZE 2 ++/* Bit: 'RA300_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_1F_1E_RA300_ACT_OFFSET 0x9F ++#define TANTOS_3G_RA_1F_1E_RA300_ACT_SHIFT 0 ++#define TANTOS_3G_RA_1F_1E_RA300_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C2000021~0180C2000020' */ ++/* Bit: 'RA3233_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_21_20_RA3233_VALID_OFFSET 0xB0 ++#define TANTOS_3G_RA_21_20_RA3233_VALID_SHIFT 15 ++#define TANTOS_3G_RA_21_20_RA3233_VALID_SIZE 1 ++/* Bit: 'RA3233_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_21_20_RA3233_SPAN_OFFSET 0xB0 ++#define TANTOS_3G_RA_21_20_RA3233_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_21_20_RA3233_SPAN_SIZE 1 ++/* Bit: 'RA3233_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_21_20_RA3233_MG_OFFSET 0xB0 ++#define TANTOS_3G_RA_21_20_RA3233_MG_SHIFT 13 ++#define TANTOS_3G_RA_21_20_RA3233_MG_SIZE 1 ++/* Bit: 'RA3233_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_21_20_RA3233_CV_OFFSET 0xB0 ++#define TANTOS_3G_RA_21_20_RA3233_CV_SHIFT 12 ++#define TANTOS_3G_RA_21_20_RA3233_CV_SIZE 1 ++/* Bit: 'RA3233_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_21_20_RA3233_TXTAG_OFFSET 0xB0 ++#define TANTOS_3G_RA_21_20_RA3233_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_21_20_RA3233_TXTAG_SIZE 2 ++/* Bit: 'RA3233_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_21_20_RA3233_ACT_OFFSET 0xB0 ++#define TANTOS_3G_RA_21_20_RA3233_ACT_SHIFT 8 ++#define TANTOS_3G_RA_21_20_RA3233_ACT_SIZE 2 ++/* Bit: 'RA320_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_21_20_RA320_VALID_OFFSET 0xB0 ++#define TANTOS_3G_RA_21_20_RA320_VALID_SHIFT 7 ++#define TANTOS_3G_RA_21_20_RA320_VALID_SIZE 1 ++/* Bit: 'RA320_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_21_20_RA320_SPAN_OFFSET 0xB0 ++#define TANTOS_3G_RA_21_20_RA320_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_21_20_RA320_SPAN_SIZE 1 ++/* Bit: 'RA320_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_21_20_RA320_MG_OFFSET 0xB0 ++#define TANTOS_3G_RA_21_20_RA320_MG_SHIFT 5 ++#define TANTOS_3G_RA_21_20_RA320_MG_SIZE 1 ++/* Bit: 'RA320_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_21_20_RA320_CV_OFFSET 0xB0 ++#define TANTOS_3G_RA_21_20_RA320_CV_SHIFT 4 ++#define TANTOS_3G_RA_21_20_RA320_CV_SIZE 1 ++/* Bit: 'RA320_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_21_20_RA320_TXTAG_OFFSET 0xB0 ++#define TANTOS_3G_RA_21_20_RA320_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_21_20_RA320_TXTAG_SIZE 2 ++/* Bit: 'RA320_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_21_20_RA320_ACT_OFFSET 0xB0 ++#define TANTOS_3G_RA_21_20_RA320_ACT_SHIFT 0 ++#define TANTOS_3G_RA_21_20_RA320_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C2000023~0180C2000022' */ ++/* Bit: 'RA3435_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_23_22_RA3435_VALID_OFFSET 0xB1 ++#define TANTOS_3G_RA_23_22_RA3435_VALID_SHIFT 15 ++#define TANTOS_3G_RA_23_22_RA3435_VALID_SIZE 1 ++/* Bit: 'RA3435_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_23_22_RA3435_SPAN_OFFSET 0xB1 ++#define TANTOS_3G_RA_23_22_RA3435_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_23_22_RA3435_SPAN_SIZE 1 ++/* Bit: 'RA3435_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_23_22_RA3435_MG_OFFSET 0xB1 ++#define TANTOS_3G_RA_23_22_RA3435_MG_SHIFT 13 ++#define TANTOS_3G_RA_23_22_RA3435_MG_SIZE 1 ++/* Bit: 'RA3435_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_23_22_RA3435_CV_OFFSET 0xB1 ++#define TANTOS_3G_RA_23_22_RA3435_CV_SHIFT 12 ++#define TANTOS_3G_RA_23_22_RA3435_CV_SIZE 1 ++/* Bit: 'RA3435_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_23_22_RA3435_TXTAG_OFFSET 0xB1 ++#define TANTOS_3G_RA_23_22_RA3435_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_23_22_RA3435_TXTAG_SIZE 2 ++/* Bit: 'RA3435_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_23_22_RA3435_ACT_OFFSET 0xB1 ++#define TANTOS_3G_RA_23_22_RA3435_ACT_SHIFT 8 ++#define TANTOS_3G_RA_23_22_RA3435_ACT_SIZE 2 ++/* Bit: 'RA340_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_23_22_RA340_VALID_OFFSET 0xB1 ++#define TANTOS_3G_RA_23_22_RA340_VALID_SHIFT 7 ++#define TANTOS_3G_RA_23_22_RA340_VALID_SIZE 1 ++/* Bit: 'RA340_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_23_22_RA340_SPAN_OFFSET 0xB1 ++#define TANTOS_3G_RA_23_22_RA340_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_23_22_RA340_SPAN_SIZE 1 ++/* Bit: 'RA340_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_23_22_RA340_MG_OFFSET 0xB1 ++#define TANTOS_3G_RA_23_22_RA340_MG_SHIFT 5 ++#define TANTOS_3G_RA_23_22_RA340_MG_SIZE 1 ++/* Bit: 'RA340_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_23_22_RA340_CV_OFFSET 0xB1 ++#define TANTOS_3G_RA_23_22_RA340_CV_SHIFT 4 ++#define TANTOS_3G_RA_23_22_RA340_CV_SIZE 1 ++/* Bit: 'RA340_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_23_22_RA340_TXTAG_OFFSET 0xB1 ++#define TANTOS_3G_RA_23_22_RA340_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_23_22_RA340_TXTAG_SIZE 2 ++/* Bit: 'RA340_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_23_22_RA340_ACT_OFFSET 0xB1 ++#define TANTOS_3G_RA_23_22_RA340_ACT_SHIFT 0 ++#define TANTOS_3G_RA_23_22_RA340_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C2000025~0180C2000024' */ ++/* Bit: 'RA3637_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_25_24_RA3637_VALID_OFFSET 0xB2 ++#define TANTOS_3G_RA_25_24_RA3637_VALID_SHIFT 15 ++#define TANTOS_3G_RA_25_24_RA3637_VALID_SIZE 1 ++/* Bit: 'RA3637_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_25_24_RA3637_SPAN_OFFSET 0xB2 ++#define TANTOS_3G_RA_25_24_RA3637_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_25_24_RA3637_SPAN_SIZE 1 ++/* Bit: 'RA3637_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_25_24_RA3637_MG_OFFSET 0xB2 ++#define TANTOS_3G_RA_25_24_RA3637_MG_SHIFT 13 ++#define TANTOS_3G_RA_25_24_RA3637_MG_SIZE 1 ++/* Bit: 'RA3637_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_25_24_RA3637_CV_OFFSET 0xB2 ++#define TANTOS_3G_RA_25_24_RA3637_CV_SHIFT 12 ++#define TANTOS_3G_RA_25_24_RA3637_CV_SIZE 1 ++/* Bit: 'RA3637_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_25_24_RA3637_TXTAG_OFFSET 0xB2 ++#define TANTOS_3G_RA_25_24_RA3637_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_25_24_RA3637_TXTAG_SIZE 2 ++/* Bit: 'RA3637_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_25_24_RA3637_ACT_OFFSET 0xB2 ++#define TANTOS_3G_RA_25_24_RA3637_ACT_SHIFT 8 ++#define TANTOS_3G_RA_25_24_RA3637_ACT_SIZE 2 ++/* Bit: 'RA360_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_25_24_RA360_VALID_OFFSET 0xB2 ++#define TANTOS_3G_RA_25_24_RA360_VALID_SHIFT 7 ++#define TANTOS_3G_RA_25_24_RA360_VALID_SIZE 1 ++/* Bit: 'RA360_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_25_24_RA360_SPAN_OFFSET 0xB2 ++#define TANTOS_3G_RA_25_24_RA360_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_25_24_RA360_SPAN_SIZE 1 ++/* Bit: 'RA360_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_25_24_RA360_MG_OFFSET 0xB2 ++#define TANTOS_3G_RA_25_24_RA360_MG_SHIFT 5 ++#define TANTOS_3G_RA_25_24_RA360_MG_SIZE 1 ++/* Bit: 'RA360_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_25_24_RA360_CV_OFFSET 0xB2 ++#define TANTOS_3G_RA_25_24_RA360_CV_SHIFT 4 ++#define TANTOS_3G_RA_25_24_RA360_CV_SIZE 1 ++/* Bit: 'RA360_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_25_24_RA360_TXTAG_OFFSET 0xB2 ++#define TANTOS_3G_RA_25_24_RA360_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_25_24_RA360_TXTAG_SIZE 2 ++/* Bit: 'RA360_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_25_24_RA360_ACT_OFFSET 0xB2 ++#define TANTOS_3G_RA_25_24_RA360_ACT_SHIFT 0 ++#define TANTOS_3G_RA_25_24_RA360_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C2000027~0180C2000026' */ ++/* Bit: 'RA3839_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_27_26_RA3839_VALID_OFFSET 0xB3 ++#define TANTOS_3G_RA_27_26_RA3839_VALID_SHIFT 15 ++#define TANTOS_3G_RA_27_26_RA3839_VALID_SIZE 1 ++/* Bit: 'RA3839_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_27_26_RA3839_SPAN_OFFSET 0xB3 ++#define TANTOS_3G_RA_27_26_RA3839_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_27_26_RA3839_SPAN_SIZE 1 ++/* Bit: 'RA3839_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_27_26_RA3839_MG_OFFSET 0xB3 ++#define TANTOS_3G_RA_27_26_RA3839_MG_SHIFT 13 ++#define TANTOS_3G_RA_27_26_RA3839_MG_SIZE 1 ++/* Bit: 'RA3839_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_27_26_RA3839_CV_OFFSET 0xB3 ++#define TANTOS_3G_RA_27_26_RA3839_CV_SHIFT 12 ++#define TANTOS_3G_RA_27_26_RA3839_CV_SIZE 1 ++/* Bit: 'RA3839_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_27_26_RA3839_TXTAG_OFFSET 0xB3 ++#define TANTOS_3G_RA_27_26_RA3839_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_27_26_RA3839_TXTAG_SIZE 2 ++/* Bit: 'RA3839_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_27_26_RA3839_ACT_OFFSET 0xB3 ++#define TANTOS_3G_RA_27_26_RA3839_ACT_SHIFT 8 ++#define TANTOS_3G_RA_27_26_RA3839_ACT_SIZE 2 ++/* Bit: 'RA380_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_27_26_RA380_VALID_OFFSET 0xB3 ++#define TANTOS_3G_RA_27_26_RA380_VALID_SHIFT 7 ++#define TANTOS_3G_RA_27_26_RA380_VALID_SIZE 1 ++/* Bit: 'RA380_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_27_26_RA380_SPAN_OFFSET 0xB3 ++#define TANTOS_3G_RA_27_26_RA380_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_27_26_RA380_SPAN_SIZE 1 ++/* Bit: 'RA380_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_27_26_RA380_MG_OFFSET 0xB3 ++#define TANTOS_3G_RA_27_26_RA380_MG_SHIFT 5 ++#define TANTOS_3G_RA_27_26_RA380_MG_SIZE 1 ++/* Bit: 'RA380_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_27_26_RA380_CV_OFFSET 0xB3 ++#define TANTOS_3G_RA_27_26_RA380_CV_SHIFT 4 ++#define TANTOS_3G_RA_27_26_RA380_CV_SIZE 1 ++/* Bit: 'RA380_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_27_26_RA380_TXTAG_OFFSET 0xB3 ++#define TANTOS_3G_RA_27_26_RA380_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_27_26_RA380_TXTAG_SIZE 2 ++/* Bit: 'RA380_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_27_26_RA380_ACT_OFFSET 0xB3 ++#define TANTOS_3G_RA_27_26_RA380_ACT_SHIFT 0 ++#define TANTOS_3G_RA_27_26_RA380_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C2000029~0180C2000028' */ ++/* Bit: 'RA4041_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_29_28_RA4041_VALID_OFFSET 0xB4 ++#define TANTOS_3G_RA_29_28_RA4041_VALID_SHIFT 15 ++#define TANTOS_3G_RA_29_28_RA4041_VALID_SIZE 1 ++/* Bit: 'RA4041_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_29_28_RA4041_SPAN_OFFSET 0xB4 ++#define TANTOS_3G_RA_29_28_RA4041_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_29_28_RA4041_SPAN_SIZE 1 ++/* Bit: 'RA4041_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_29_28_RA4041_MG_OFFSET 0xB4 ++#define TANTOS_3G_RA_29_28_RA4041_MG_SHIFT 13 ++#define TANTOS_3G_RA_29_28_RA4041_MG_SIZE 1 ++/* Bit: 'RA4041_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_29_28_RA4041_CV_OFFSET 0xB4 ++#define TANTOS_3G_RA_29_28_RA4041_CV_SHIFT 12 ++#define TANTOS_3G_RA_29_28_RA4041_CV_SIZE 1 ++/* Bit: 'RA4041_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_29_28_RA4041_TXTAG_OFFSET 0xB4 ++#define TANTOS_3G_RA_29_28_RA4041_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_29_28_RA4041_TXTAG_SIZE 2 ++/* Bit: 'RA4041_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_29_28_RA4041_ACT_OFFSET 0xB4 ++#define TANTOS_3G_RA_29_28_RA4041_ACT_SHIFT 8 ++#define TANTOS_3G_RA_29_28_RA4041_ACT_SIZE 2 ++/* Bit: 'RA400_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_29_28_RA400_VALID_OFFSET 0xB4 ++#define TANTOS_3G_RA_29_28_RA400_VALID_SHIFT 7 ++#define TANTOS_3G_RA_29_28_RA400_VALID_SIZE 1 ++/* Bit: 'RA400_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_29_28_RA400_SPAN_OFFSET 0xB4 ++#define TANTOS_3G_RA_29_28_RA400_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_29_28_RA400_SPAN_SIZE 1 ++/* Bit: 'RA400_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_29_28_RA400_MG_OFFSET 0xB4 ++#define TANTOS_3G_RA_29_28_RA400_MG_SHIFT 5 ++#define TANTOS_3G_RA_29_28_RA400_MG_SIZE 1 ++/* Bit: 'RA400_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_29_28_RA400_CV_OFFSET 0xB4 ++#define TANTOS_3G_RA_29_28_RA400_CV_SHIFT 4 ++#define TANTOS_3G_RA_29_28_RA400_CV_SIZE 1 ++/* Bit: 'RA400_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_29_28_RA400_TXTAG_OFFSET 0xB4 ++#define TANTOS_3G_RA_29_28_RA400_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_29_28_RA400_TXTAG_SIZE 2 ++/* Bit: 'RA400_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_29_28_RA400_ACT_OFFSET 0xB4 ++#define TANTOS_3G_RA_29_28_RA400_ACT_SHIFT 0 ++#define TANTOS_3G_RA_29_28_RA400_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C200002B~0180C200002A' */ ++/* Bit: 'RA4243_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_2B_2A_RA4243_VALID_OFFSET 0xB5 ++#define TANTOS_3G_RA_2B_2A_RA4243_VALID_SHIFT 15 ++#define TANTOS_3G_RA_2B_2A_RA4243_VALID_SIZE 1 ++/* Bit: 'RA4243_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_2B_2A_RA4243_SPAN_OFFSET 0xB5 ++#define TANTOS_3G_RA_2B_2A_RA4243_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_2B_2A_RA4243_SPAN_SIZE 1 ++/* Bit: 'RA4243_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_2B_2A_RA4243_MG_OFFSET 0xB5 ++#define TANTOS_3G_RA_2B_2A_RA4243_MG_SHIFT 13 ++#define TANTOS_3G_RA_2B_2A_RA4243_MG_SIZE 1 ++/* Bit: 'RA4243_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_2B_2A_RA4243_CV_OFFSET 0xB5 ++#define TANTOS_3G_RA_2B_2A_RA4243_CV_SHIFT 12 ++#define TANTOS_3G_RA_2B_2A_RA4243_CV_SIZE 1 ++/* Bit: 'RA4243_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_2B_2A_RA4243_TXTAG_OFFSET 0xB5 ++#define TANTOS_3G_RA_2B_2A_RA4243_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_2B_2A_RA4243_TXTAG_SIZE 2 ++/* Bit: 'RA4243_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_2B_2A_RA4243_ACT_OFFSET 0xB5 ++#define TANTOS_3G_RA_2B_2A_RA4243_ACT_SHIFT 8 ++#define TANTOS_3G_RA_2B_2A_RA4243_ACT_SIZE 2 ++/* Bit: 'RA420_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_2B_2A_RA420_VALID_OFFSET 0xB5 ++#define TANTOS_3G_RA_2B_2A_RA420_VALID_SHIFT 7 ++#define TANTOS_3G_RA_2B_2A_RA420_VALID_SIZE 1 ++/* Bit: 'RA420_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_2B_2A_RA420_SPAN_OFFSET 0xB5 ++#define TANTOS_3G_RA_2B_2A_RA420_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_2B_2A_RA420_SPAN_SIZE 1 ++/* Bit: 'RA420_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_2B_2A_RA420_MG_OFFSET 0xB5 ++#define TANTOS_3G_RA_2B_2A_RA420_MG_SHIFT 5 ++#define TANTOS_3G_RA_2B_2A_RA420_MG_SIZE 1 ++/* Bit: 'RA420_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_2B_2A_RA420_CV_OFFSET 0xB5 ++#define TANTOS_3G_RA_2B_2A_RA420_CV_SHIFT 4 ++#define TANTOS_3G_RA_2B_2A_RA420_CV_SIZE 1 ++/* Bit: 'RA420_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_2B_2A_RA420_TXTAG_OFFSET 0xB5 ++#define TANTOS_3G_RA_2B_2A_RA420_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_2B_2A_RA420_TXTAG_SIZE 2 ++/* Bit: 'RA420_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_2B_2A_RA420_ACT_OFFSET 0xB5 ++#define TANTOS_3G_RA_2B_2A_RA420_ACT_SHIFT 0 ++#define TANTOS_3G_RA_2B_2A_RA420_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C200002D~0180C200002C' */ ++/* Bit: 'RA4445_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_2D_2C_RA4445_VALID_OFFSET 0xB6 ++#define TANTOS_3G_RA_2D_2C_RA4445_VALID_SHIFT 15 ++#define TANTOS_3G_RA_2D_2C_RA4445_VALID_SIZE 1 ++/* Bit: 'RA4445_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_2D_2C_RA4445_SPAN_OFFSET 0xB6 ++#define TANTOS_3G_RA_2D_2C_RA4445_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_2D_2C_RA4445_SPAN_SIZE 1 ++/* Bit: 'RA4445_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_2D_2C_RA4445_MG_OFFSET 0xB6 ++#define TANTOS_3G_RA_2D_2C_RA4445_MG_SHIFT 13 ++#define TANTOS_3G_RA_2D_2C_RA4445_MG_SIZE 1 ++/* Bit: 'RA4445_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_2D_2C_RA4445_CV_OFFSET 0xB6 ++#define TANTOS_3G_RA_2D_2C_RA4445_CV_SHIFT 12 ++#define TANTOS_3G_RA_2D_2C_RA4445_CV_SIZE 1 ++/* Bit: 'RA4445_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_2D_2C_RA4445_TXTAG_OFFSET 0xB6 ++#define TANTOS_3G_RA_2D_2C_RA4445_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_2D_2C_RA4445_TXTAG_SIZE 2 ++/* Bit: 'RA4445_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_2D_2C_RA4445_ACT_OFFSET 0xB6 ++#define TANTOS_3G_RA_2D_2C_RA4445_ACT_SHIFT 8 ++#define TANTOS_3G_RA_2D_2C_RA4445_ACT_SIZE 2 ++/* Bit: 'RA440_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_2D_2C_RA440_VALID_OFFSET 0xB6 ++#define TANTOS_3G_RA_2D_2C_RA440_VALID_SHIFT 7 ++#define TANTOS_3G_RA_2D_2C_RA440_VALID_SIZE 1 ++/* Bit: 'RA440_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_2D_2C_RA440_SPAN_OFFSET 0xB6 ++#define TANTOS_3G_RA_2D_2C_RA440_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_2D_2C_RA440_SPAN_SIZE 1 ++/* Bit: 'RA440_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_2D_2C_RA440_MG_OFFSET 0xB6 ++#define TANTOS_3G_RA_2D_2C_RA440_MG_SHIFT 5 ++#define TANTOS_3G_RA_2D_2C_RA440_MG_SIZE 1 ++/* Bit: 'RA440_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_2D_2C_RA440_CV_OFFSET 0xB6 ++#define TANTOS_3G_RA_2D_2C_RA440_CV_SHIFT 4 ++#define TANTOS_3G_RA_2D_2C_RA440_CV_SIZE 1 ++/* Bit: 'RA440_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_2D_2C_RA440_TXTAG_OFFSET 0xB6 ++#define TANTOS_3G_RA_2D_2C_RA440_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_2D_2C_RA440_TXTAG_SIZE 2 ++/* Bit: 'RA440_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_2D_2C_RA440_ACT_OFFSET 0xB6 ++#define TANTOS_3G_RA_2D_2C_RA440_ACT_SHIFT 0 ++#define TANTOS_3G_RA_2D_2C_RA440_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Reserve Action for 0180C200002F~0180C200002E' */ ++/* Bit: 'RA4647_VALID' */ ++/* Description: 'Valid bit for 0180C2000001' */ ++#define TANTOS_3G_RA_2F_2E_RA4647_VALID_OFFSET 0xB7 ++#define TANTOS_3G_RA_2F_2E_RA4647_VALID_SHIFT 15 ++#define TANTOS_3G_RA_2F_2E_RA4647_VALID_SIZE 1 ++/* Bit: 'RA4647_SPAN' */ ++/* Description: 'Span bit for 0180C2000001' */ ++#define TANTOS_3G_RA_2F_2E_RA4647_SPAN_OFFSET 0xB7 ++#define TANTOS_3G_RA_2F_2E_RA4647_SPAN_SHIFT 14 ++#define TANTOS_3G_RA_2F_2E_RA4647_SPAN_SIZE 1 ++/* Bit: 'RA4647_MG' */ ++/* Description: 'Management bit for 0180C2000001' */ ++#define TANTOS_3G_RA_2F_2E_RA4647_MG_OFFSET 0xB7 ++#define TANTOS_3G_RA_2F_2E_RA4647_MG_SHIFT 13 ++#define TANTOS_3G_RA_2F_2E_RA4647_MG_SIZE 1 ++/* Bit: 'RA4647_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000001' */ ++#define TANTOS_3G_RA_2F_2E_RA4647_CV_OFFSET 0xB7 ++#define TANTOS_3G_RA_2F_2E_RA4647_CV_SHIFT 12 ++#define TANTOS_3G_RA_2F_2E_RA4647_CV_SIZE 1 ++/* Bit: 'RA4647_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000001' */ ++#define TANTOS_3G_RA_2F_2E_RA4647_TXTAG_OFFSET 0xB7 ++#define TANTOS_3G_RA_2F_2E_RA4647_TXTAG_SHIFT 10 ++#define TANTOS_3G_RA_2F_2E_RA4647_TXTAG_SIZE 2 ++/* Bit: 'RA4647_ACT' */ ++/* Description: 'Action bit for 0180C2000001' */ ++#define TANTOS_3G_RA_2F_2E_RA4647_ACT_OFFSET 0xB7 ++#define TANTOS_3G_RA_2F_2E_RA4647_ACT_SHIFT 8 ++#define TANTOS_3G_RA_2F_2E_RA4647_ACT_SIZE 2 ++/* Bit: 'RA460_VALID' */ ++/* Description: 'Valid bit for 0180C2000000' */ ++#define TANTOS_3G_RA_2F_2E_RA460_VALID_OFFSET 0xB7 ++#define TANTOS_3G_RA_2F_2E_RA460_VALID_SHIFT 7 ++#define TANTOS_3G_RA_2F_2E_RA460_VALID_SIZE 1 ++/* Bit: 'RA460_SPAN' */ ++/* Description: 'Span bit for 0180C2000000' */ ++#define TANTOS_3G_RA_2F_2E_RA460_SPAN_OFFSET 0xB7 ++#define TANTOS_3G_RA_2F_2E_RA460_SPAN_SHIFT 6 ++#define TANTOS_3G_RA_2F_2E_RA460_SPAN_SIZE 1 ++/* Bit: 'RA460_MG' */ ++/* Description: 'Management bit for 0180C2000000' */ ++#define TANTOS_3G_RA_2F_2E_RA460_MG_OFFSET 0xB7 ++#define TANTOS_3G_RA_2F_2E_RA460_MG_SHIFT 5 ++#define TANTOS_3G_RA_2F_2E_RA460_MG_SIZE 1 ++/* Bit: 'RA460_CV' */ ++/* Description: 'Cross_VLAN bit for 0180C2000000' */ ++#define TANTOS_3G_RA_2F_2E_RA460_CV_OFFSET 0xB7 ++#define TANTOS_3G_RA_2F_2E_RA460_CV_SHIFT 4 ++#define TANTOS_3G_RA_2F_2E_RA460_CV_SIZE 1 ++/* Bit: 'RA460_TXTAG' */ ++/* Description: 'TXTAG bit for 0180C2000000' */ ++#define TANTOS_3G_RA_2F_2E_RA460_TXTAG_OFFSET 0xB7 ++#define TANTOS_3G_RA_2F_2E_RA460_TXTAG_SHIFT 2 ++#define TANTOS_3G_RA_2F_2E_RA460_TXTAG_SIZE 2 ++/* Bit: 'RA460_ACT' */ ++/* Description: 'Action bit for 0180C2000000' */ ++#define TANTOS_3G_RA_2F_2E_RA460_ACT_OFFSET 0xB7 ++#define TANTOS_3G_RA_2F_2E_RA460_ACT_SHIFT 0 ++#define TANTOS_3G_RA_2F_2E_RA460_ACT_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Protocol Filter 0' */ ++/* Bit: 'PFR1' */ ++/* Description: 'Value Compared with Protocol in IP Header' */ ++#define TANTOS_3G_PF_0_PFR1_OFFSET 0xB8 ++#define TANTOS_3G_PF_0_PFR1_SHIFT 8 ++#define TANTOS_3G_PF_0_PFR1_SIZE 8 ++/* Bit: 'PFR0' */ ++/* Description: 'Value Compared with Protocol in IP Header' */ ++#define TANTOS_3G_PF_0_PFR0_OFFSET 0xB8 ++#define TANTOS_3G_PF_0_PFR0_SHIFT 0 ++#define TANTOS_3G_PF_0_PFR0_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Protocol Filter 3 and 2' */ ++/* Bit: 'PFR1' */ ++/* Description: 'Value Compared with Protocol in IP Header' */ ++#define TANTOS_3G_PF_1_PFR1_OFFSET 0xB9 ++#define TANTOS_3G_PF_1_PFR1_SHIFT 8 ++#define TANTOS_3G_PF_1_PFR1_SIZE 8 ++/* Bit: 'PFR0' */ ++/* Description: 'Value Compared with Protocol in IP Header' */ ++#define TANTOS_3G_PF_1_PFR0_OFFSET 0xB9 ++#define TANTOS_3G_PF_1_PFR0_SHIFT 0 ++#define TANTOS_3G_PF_1_PFR0_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Protocol Filter 5 and 4' */ ++/* Bit: 'PFR1' */ ++/* Description: 'Value Compared with Protocol in IP Header' */ ++#define TANTOS_3G_PF_2_PFR1_OFFSET 0xBA ++#define TANTOS_3G_PF_2_PFR1_SHIFT 8 ++#define TANTOS_3G_PF_2_PFR1_SIZE 8 ++/* Bit: 'PFR0' */ ++/* Description: 'Value Compared with Protocol in IP Header' */ ++#define TANTOS_3G_PF_2_PFR0_OFFSET 0xBA ++#define TANTOS_3G_PF_2_PFR0_SHIFT 0 ++#define TANTOS_3G_PF_2_PFR0_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Protocol Filter 7 and 6' */ ++/* Bit: 'PFR1' */ ++/* Description: 'Value Compared with Protocol in IP Header' */ ++#define TANTOS_3G_PF_3_PFR1_OFFSET 0xBB ++#define TANTOS_3G_PF_3_PFR1_SHIFT 8 ++#define TANTOS_3G_PF_3_PFR1_SIZE 8 ++/* Bit: 'PFR0' */ ++/* Description: 'Value Compared with Protocol in IP Header' */ ++#define TANTOS_3G_PF_3_PFR0_OFFSET 0xBB ++#define TANTOS_3G_PF_3_PFR0_SHIFT 0 ++#define TANTOS_3G_PF_3_PFR0_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PHY Initial Control 0 Register' */ ++/* Bit: 'PHYIE6' */ ++/* Description: 'PHY Initial Enable for port 6' */ ++#define TANTOS_3G_PHYIC0_PHYIE6_OFFSET 0xD0 ++#define TANTOS_3G_PHYIC0_PHYIE6_SHIFT 14 ++#define TANTOS_3G_PHYIC0_PHYIE6_SIZE 1 ++/* Bit: 'PHYIE5' */ ++/* Description: 'PHY Initial Enable for port 5' */ ++#define TANTOS_3G_PHYIC0_PHYIE5_OFFSET 0xD0 ++#define TANTOS_3G_PHYIC0_PHYIE5_SHIFT 13 ++#define TANTOS_3G_PHYIC0_PHYIE5_SIZE 1 ++/* Bit: 'PHYIE4' */ ++/* Description: 'PHY Initial Enable for port 4' */ ++#define TANTOS_3G_PHYIC0_PHYIE4_OFFSET 0xD0 ++#define TANTOS_3G_PHYIC0_PHYIE4_SHIFT 12 ++#define TANTOS_3G_PHYIC0_PHYIE4_SIZE 1 ++/* Bit: 'PHYIE3' */ ++/* Description: 'PHY Initial Enable for port 3' */ ++#define TANTOS_3G_PHYIC0_PHYIE3_OFFSET 0xD0 ++#define TANTOS_3G_PHYIC0_PHYIE3_SHIFT 11 ++#define TANTOS_3G_PHYIC0_PHYIE3_SIZE 1 ++/* Bit: 'PHYIE2' */ ++/* Description: 'PHY Initial Enable for port 2' */ ++#define TANTOS_3G_PHYIC0_PHYIE2_OFFSET 0xD0 ++#define TANTOS_3G_PHYIC0_PHYIE2_SHIFT 10 ++#define TANTOS_3G_PHYIC0_PHYIE2_SIZE 1 ++/* Bit: 'PHYIE1' */ ++/* Description: 'PHY Initial Enable for port 1' */ ++#define TANTOS_3G_PHYIC0_PHYIE1_OFFSET 0xD0 ++#define TANTOS_3G_PHYIC0_PHYIE1_SHIFT 9 ++#define TANTOS_3G_PHYIC0_PHYIE1_SIZE 1 ++/* Bit: 'PHYIE0' */ ++/* Description: 'PHY Initial Enable for port 0' */ ++#define TANTOS_3G_PHYIC0_PHYIE0_OFFSET 0xD0 ++#define TANTOS_3G_PHYIC0_PHYIE0_SHIFT 8 ++#define TANTOS_3G_PHYIC0_PHYIE0_SIZE 1 ++/* Bit: 'REGA0' */ ++/* Description: 'Register Address 0' */ ++#define TANTOS_3G_PHYIC0_REGA0_OFFSET 0xD0 ++#define TANTOS_3G_PHYIC0_REGA0_SHIFT 0 ++#define TANTOS_3G_PHYIC0_REGA0_SIZE 5 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PHY Initial Control 1 Register' */ ++/* Bit: 'PHYIE6' */ ++/* Description: 'PHY Initial Enable for port 6' */ ++#define TANTOS_3G_PHYIC1_PHYIE6_OFFSET 0xD2 ++#define TANTOS_3G_PHYIC1_PHYIE6_SHIFT 14 ++#define TANTOS_3G_PHYIC1_PHYIE6_SIZE 1 ++/* Bit: 'PHYIE5' */ ++/* Description: 'PHY Initial Enable for port 5' */ ++#define TANTOS_3G_PHYIC1_PHYIE5_OFFSET 0xD2 ++#define TANTOS_3G_PHYIC1_PHYIE5_SHIFT 13 ++#define TANTOS_3G_PHYIC1_PHYIE5_SIZE 1 ++/* Bit: 'PHYIE4' */ ++/* Description: 'PHY Initial Enable for port 4' */ ++#define TANTOS_3G_PHYIC1_PHYIE4_OFFSET 0xD2 ++#define TANTOS_3G_PHYIC1_PHYIE4_SHIFT 12 ++#define TANTOS_3G_PHYIC1_PHYIE4_SIZE 1 ++/* Bit: 'PHYIE3' */ ++/* Description: 'PHY Initial Enable for port 3' */ ++#define TANTOS_3G_PHYIC1_PHYIE3_OFFSET 0xD2 ++#define TANTOS_3G_PHYIC1_PHYIE3_SHIFT 11 ++#define TANTOS_3G_PHYIC1_PHYIE3_SIZE 1 ++/* Bit: 'PHYIE2' */ ++/* Description: 'PHY Initial Enable for port 2' */ ++#define TANTOS_3G_PHYIC1_PHYIE2_OFFSET 0xD2 ++#define TANTOS_3G_PHYIC1_PHYIE2_SHIFT 10 ++#define TANTOS_3G_PHYIC1_PHYIE2_SIZE 1 ++/* Bit: 'PHYIE1' */ ++/* Description: 'PHY Initial Enable for port 1' */ ++#define TANTOS_3G_PHYIC1_PHYIE1_OFFSET 0xD2 ++#define TANTOS_3G_PHYIC1_PHYIE1_SHIFT 9 ++#define TANTOS_3G_PHYIC1_PHYIE1_SIZE 1 ++/* Bit: 'PHYIE0' */ ++/* Description: 'PHY Initial Enable for port 0' */ ++#define TANTOS_3G_PHYIC1_PHYIE0_OFFSET 0xD2 ++#define TANTOS_3G_PHYIC1_PHYIE0_SHIFT 8 ++#define TANTOS_3G_PHYIC1_PHYIE0_SIZE 1 ++/* Bit: 'REGA0' */ ++/* Description: 'Register Address 0' */ ++#define TANTOS_3G_PHYIC1_REGA0_OFFSET 0xD2 ++#define TANTOS_3G_PHYIC1_REGA0_SHIFT 0 ++#define TANTOS_3G_PHYIC1_REGA0_SIZE 5 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PHY Initial Control 2 Register' */ ++/* Bit: 'PHYIE6' */ ++/* Description: 'PHY Initial Enable for port 6' */ ++#define TANTOS_3G_PHYIC2_PHYIE6_OFFSET 0xD4 ++#define TANTOS_3G_PHYIC2_PHYIE6_SHIFT 14 ++#define TANTOS_3G_PHYIC2_PHYIE6_SIZE 1 ++/* Bit: 'PHYIE5' */ ++/* Description: 'PHY Initial Enable for port 5' */ ++#define TANTOS_3G_PHYIC2_PHYIE5_OFFSET 0xD4 ++#define TANTOS_3G_PHYIC2_PHYIE5_SHIFT 13 ++#define TANTOS_3G_PHYIC2_PHYIE5_SIZE 1 ++/* Bit: 'PHYIE4' */ ++/* Description: 'PHY Initial Enable for port 4' */ ++#define TANTOS_3G_PHYIC2_PHYIE4_OFFSET 0xD4 ++#define TANTOS_3G_PHYIC2_PHYIE4_SHIFT 12 ++#define TANTOS_3G_PHYIC2_PHYIE4_SIZE 1 ++/* Bit: 'PHYIE3' */ ++/* Description: 'PHY Initial Enable for port 3' */ ++#define TANTOS_3G_PHYIC2_PHYIE3_OFFSET 0xD4 ++#define TANTOS_3G_PHYIC2_PHYIE3_SHIFT 11 ++#define TANTOS_3G_PHYIC2_PHYIE3_SIZE 1 ++/* Bit: 'PHYIE2' */ ++/* Description: 'PHY Initial Enable for port 2' */ ++#define TANTOS_3G_PHYIC2_PHYIE2_OFFSET 0xD4 ++#define TANTOS_3G_PHYIC2_PHYIE2_SHIFT 10 ++#define TANTOS_3G_PHYIC2_PHYIE2_SIZE 1 ++/* Bit: 'PHYIE1' */ ++/* Description: 'PHY Initial Enable for port 1' */ ++#define TANTOS_3G_PHYIC2_PHYIE1_OFFSET 0xD4 ++#define TANTOS_3G_PHYIC2_PHYIE1_SHIFT 9 ++#define TANTOS_3G_PHYIC2_PHYIE1_SIZE 1 ++/* Bit: 'PHYIE0' */ ++/* Description: 'PHY Initial Enable for port 0' */ ++#define TANTOS_3G_PHYIC2_PHYIE0_OFFSET 0xD4 ++#define TANTOS_3G_PHYIC2_PHYIE0_SHIFT 8 ++#define TANTOS_3G_PHYIC2_PHYIE0_SIZE 1 ++/* Bit: 'REGA0' */ ++/* Description: 'Register Address 0' */ ++#define TANTOS_3G_PHYIC2_REGA0_OFFSET 0xD4 ++#define TANTOS_3G_PHYIC2_REGA0_SHIFT 0 ++#define TANTOS_3G_PHYIC2_REGA0_SIZE 5 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PHY Initial Control 3 Register' */ ++/* Bit: 'PHYIE6' */ ++/* Description: 'PHY Initial Enable for port 6' */ ++#define TANTOS_3G_PHYIC3_PHYIE6_OFFSET 0xD6 ++#define TANTOS_3G_PHYIC3_PHYIE6_SHIFT 14 ++#define TANTOS_3G_PHYIC3_PHYIE6_SIZE 1 ++/* Bit: 'PHYIE5' */ ++/* Description: 'PHY Initial Enable for port 5' */ ++#define TANTOS_3G_PHYIC3_PHYIE5_OFFSET 0xD6 ++#define TANTOS_3G_PHYIC3_PHYIE5_SHIFT 13 ++#define TANTOS_3G_PHYIC3_PHYIE5_SIZE 1 ++/* Bit: 'PHYIE4' */ ++/* Description: 'PHY Initial Enable for port 4' */ ++#define TANTOS_3G_PHYIC3_PHYIE4_OFFSET 0xD6 ++#define TANTOS_3G_PHYIC3_PHYIE4_SHIFT 12 ++#define TANTOS_3G_PHYIC3_PHYIE4_SIZE 1 ++/* Bit: 'PHYIE3' */ ++/* Description: 'PHY Initial Enable for port 3' */ ++#define TANTOS_3G_PHYIC3_PHYIE3_OFFSET 0xD6 ++#define TANTOS_3G_PHYIC3_PHYIE3_SHIFT 11 ++#define TANTOS_3G_PHYIC3_PHYIE3_SIZE 1 ++/* Bit: 'PHYIE2' */ ++/* Description: 'PHY Initial Enable for port 2' */ ++#define TANTOS_3G_PHYIC3_PHYIE2_OFFSET 0xD6 ++#define TANTOS_3G_PHYIC3_PHYIE2_SHIFT 10 ++#define TANTOS_3G_PHYIC3_PHYIE2_SIZE 1 ++/* Bit: 'PHYIE1' */ ++/* Description: 'PHY Initial Enable for port 1' */ ++#define TANTOS_3G_PHYIC3_PHYIE1_OFFSET 0xD6 ++#define TANTOS_3G_PHYIC3_PHYIE1_SHIFT 9 ++#define TANTOS_3G_PHYIC3_PHYIE1_SIZE 1 ++/* Bit: 'PHYIE0' */ ++/* Description: 'PHY Initial Enable for port 0' */ ++#define TANTOS_3G_PHYIC3_PHYIE0_OFFSET 0xD6 ++#define TANTOS_3G_PHYIC3_PHYIE0_SHIFT 8 ++#define TANTOS_3G_PHYIC3_PHYIE0_SIZE 1 ++/* Bit: 'REGA0' */ ++/* Description: 'Register Address 0' */ ++#define TANTOS_3G_PHYIC3_REGA0_OFFSET 0xD6 ++#define TANTOS_3G_PHYIC3_REGA0_SHIFT 0 ++#define TANTOS_3G_PHYIC3_REGA0_SIZE 5 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PHY Initial Data 0 Register' */ ++/* Bit: 'REGD0' */ ++/* Description: 'Register Data 0' */ ++#define TANTOS_3G_PHYID0_REGD0_OFFSET 0xD1 ++#define TANTOS_3G_PHYID0_REGD0_SHIFT 0 ++#define TANTOS_3G_PHYID0_REGD0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PHY Initial Data 1 Register' */ ++/* Bit: 'REGD1' */ ++/* Description: 'Register Data 0' */ ++#define TANTOS_3G_PHYID1_REGD1_OFFSET 0xD3 ++#define TANTOS_3G_PHYID1_REGD1_SHIFT 0 ++#define TANTOS_3G_PHYID1_REGD1_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PHY Initial Data 2 Register' */ ++/* Bit: 'REGD2' */ ++/* Description: 'Register Data 0' */ ++#define TANTOS_3G_PHYID2_REGD2_OFFSET 0xD5 ++#define TANTOS_3G_PHYID2_REGD2_SHIFT 0 ++#define TANTOS_3G_PHYID2_REGD2_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PHY Initial Data 3 Register' */ ++/* Bit: 'REGD3' */ ++/* Description: 'Register Data 0' */ ++#define TANTOS_3G_PHYID3_REGD3_OFFSET 0xD7 ++#define TANTOS_3G_PHYID3_REGD3_SHIFT 0 ++#define TANTOS_3G_PHYID3_REGD3_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Interrupt Enable Register' */ ++/* Bit: 'LTADIE' */ ++/* Description: 'Leaning Table Access Done Interrupt Enable' */ ++#define TANTOS_3G_IE_LTADIE_OFFSET 0xD8 ++#define TANTOS_3G_IE_LTADIE_SHIFT 8 ++#define TANTOS_3G_IE_LTADIE_SIZE 1 ++/* Bit: 'PSVIE' */ ++/* Description: 'Port Security Violation Interrupt Enable' */ ++#define TANTOS_3G_IE_PSVIE_OFFSET 0xD8 ++#define TANTOS_3G_IE_PSVIE_SHIFT 1 ++#define TANTOS_3G_IE_PSVIE_SIZE 7 ++/* Bit: 'PSCIE' */ ++/* Description: 'Port Status Change Interrupt Enable' */ ++#define TANTOS_3G_IE_PSCIE_OFFSET 0xD8 ++#define TANTOS_3G_IE_PSCIE_SHIFT 0 ++#define TANTOS_3G_IE_PSCIE_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Interrupt Status Register' */ ++/* Bit: 'LTAD' */ ++/* Description: 'Leaning Table Access Done' */ ++#define TANTOS_3G_IS_LTAD_OFFSET 0xD9 ++#define TANTOS_3G_IS_LTAD_SHIFT 8 ++#define TANTOS_3G_IS_LTAD_SIZE 1 ++/* Bit: 'PSV' */ ++/* Description: 'Port Security Violation' */ ++#define TANTOS_3G_IS_PSV_OFFSET 0xD9 ++#define TANTOS_3G_IS_PSV_SHIFT 1 ++#define TANTOS_3G_IS_PSV_SIZE 7 ++/* Bit: 'PSC' */ ++/* Description: 'Port Status Change' */ ++#define TANTOS_3G_IS_PSC_OFFSET 0xD9 ++#define TANTOS_3G_IS_PSC_SHIFT 0 ++#define TANTOS_3G_IS_PSC_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Type Filter Action 0' */ ++/* Bit: 'ATF7' */ ++/* Description: 'Action for Type Filter 7' */ ++#define TANTOS_3G_TFA0_ATF7_OFFSET 0xDA ++#define TANTOS_3G_TFA0_ATF7_SHIFT 14 ++#define TANTOS_3G_TFA0_ATF7_SIZE 2 ++/* Bit: 'ATF6' */ ++/* Description: 'Action for Type Filter 6' */ ++#define TANTOS_3G_TFA0_ATF6_OFFSET 0xDA ++#define TANTOS_3G_TFA0_ATF6_SHIFT 12 ++#define TANTOS_3G_TFA0_ATF6_SIZE 2 ++/* Bit: 'ATF5' */ ++/* Description: 'Action for Type Filter 5' */ ++#define TANTOS_3G_TFA0_ATF5_OFFSET 0xDA ++#define TANTOS_3G_TFA0_ATF5_SHIFT 10 ++#define TANTOS_3G_TFA0_ATF5_SIZE 2 ++/* Bit: 'ATF4' */ ++/* Description: 'Action for Type Filter 4' */ ++#define TANTOS_3G_TFA0_ATF4_OFFSET 0xDA ++#define TANTOS_3G_TFA0_ATF4_SHIFT 8 ++#define TANTOS_3G_TFA0_ATF4_SIZE 2 ++/* Bit: 'ATF3' */ ++/* Description: 'Action for Type Filter 3' */ ++#define TANTOS_3G_TFA0_ATF3_OFFSET 0xDA ++#define TANTOS_3G_TFA0_ATF3_SHIFT 6 ++#define TANTOS_3G_TFA0_ATF3_SIZE 2 ++/* Bit: 'ATF2' */ ++/* Description: 'Action for Type Filter 2' */ ++#define TANTOS_3G_TFA0_ATF2_OFFSET 0xDA ++#define TANTOS_3G_TFA0_ATF2_SHIFT 4 ++#define TANTOS_3G_TFA0_ATF2_SIZE 2 ++/* Bit: 'ATF1' */ ++/* Description: 'Action for Type Filter 1' */ ++#define TANTOS_3G_TFA0_ATF1_OFFSET 0xDA ++#define TANTOS_3G_TFA0_ATF1_SHIFT 2 ++#define TANTOS_3G_TFA0_ATF1_SIZE 2 ++/* Bit: 'ATF0' */ ++/* Description: 'Action for Type Filter 0' */ ++#define TANTOS_3G_TFA0_ATF0_OFFSET 0xDA ++#define TANTOS_3G_TFA0_ATF0_SHIFT 0 ++#define TANTOS_3G_TFA0_ATF0_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Type Filter Action 1' */ ++/* Bit: 'QATF7' */ ++/* Description: 'Destination Queue for Type Filter 7' */ ++#define TANTOS_3G_TFA1_QATF7_OFFSET 0xDB ++#define TANTOS_3G_TFA1_QATF7_SHIFT 14 ++#define TANTOS_3G_TFA1_QATF7_SIZE 2 ++/* Bit: 'QATF6' */ ++/* Description: 'Destination Queue for Type Filter 6' */ ++#define TANTOS_3G_TFA1_QATF6_OFFSET 0xDB ++#define TANTOS_3G_TFA1_QATF6_SHIFT 12 ++#define TANTOS_3G_TFA1_QATF6_SIZE 2 ++/* Bit: 'QTF5' */ ++/* Description: 'Destination Queue for Type Filter 5' */ ++#define TANTOS_3G_TFA1_QTF5_OFFSET 0xDB ++#define TANTOS_3G_TFA1_QTF5_SHIFT 10 ++#define TANTOS_3G_TFA1_QTF5_SIZE 2 ++/* Bit: 'QTF4' */ ++/* Description: 'Destination Queue for Type Filter 4' */ ++#define TANTOS_3G_TFA1_QTF4_OFFSET 0xDB ++#define TANTOS_3G_TFA1_QTF4_SHIFT 8 ++#define TANTOS_3G_TFA1_QTF4_SIZE 2 ++/* Bit: 'QTF3' */ ++/* Description: 'Destination Queue for Type Filter 3' */ ++#define TANTOS_3G_TFA1_QTF3_OFFSET 0xDB ++#define TANTOS_3G_TFA1_QTF3_SHIFT 6 ++#define TANTOS_3G_TFA1_QTF3_SIZE 2 ++/* Bit: 'QTF2' */ ++/* Description: 'Destination Queue for Type Filter 2' */ ++#define TANTOS_3G_TFA1_QTF2_OFFSET 0xDB ++#define TANTOS_3G_TFA1_QTF2_SHIFT 4 ++#define TANTOS_3G_TFA1_QTF2_SIZE 2 ++/* Bit: 'QTF1' */ ++/* Description: 'Destination Queue for Type Filter 1' */ ++#define TANTOS_3G_TFA1_QTF1_OFFSET 0xDB ++#define TANTOS_3G_TFA1_QTF1_SHIFT 2 ++#define TANTOS_3G_TFA1_QTF1_SIZE 2 ++/* Bit: 'QTF0' */ ++/* Description: 'Destination Queue for Type Filter 0' */ ++#define TANTOS_3G_TFA1_QTF0_OFFSET 0xDB ++#define TANTOS_3G_TFA1_QTF0_SHIFT 0 ++#define TANTOS_3G_TFA1_QTF0_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'ARP/RARP Register' */ ++/* Bit: 'MACA' */ ++/* Description: 'MAC Control Action' */ ++#define TANTOS_3G_AR_MACA_OFFSET 0xDC ++#define TANTOS_3G_AR_MACA_SHIFT 14 ++#define TANTOS_3G_AR_MACA_SIZE 2 ++/* Bit: 'UPT' */ ++/* Description: 'Unicast packet Treated as Cross_VLAN packet' */ ++#define TANTOS_3G_AR_UPT_OFFSET 0xDC ++#define TANTOS_3G_AR_UPT_SHIFT 13 ++#define TANTOS_3G_AR_UPT_SIZE 1 ++/* Bit: 'RPT' */ ++/* Description: 'RARP Packet Treated as Cross_VLAN Packet' */ ++#define TANTOS_3G_AR_RPT_OFFSET 0xDC ++#define TANTOS_3G_AR_RPT_SHIFT 12 ++#define TANTOS_3G_AR_RPT_SIZE 1 ++/* Bit: 'RAPA' */ ++/* Description: 'RARP/ARP Packet Action' */ ++#define TANTOS_3G_AR_RAPA_OFFSET 0xDC ++#define TANTOS_3G_AR_RAPA_SHIFT 10 ++#define TANTOS_3G_AR_RAPA_SIZE 2 ++/* Bit: 'RAPPE' */ ++/* Description: 'RARP/ARP Packet Priority Enable' */ ++#define TANTOS_3G_AR_RAPPE_OFFSET 0xDC ++#define TANTOS_3G_AR_RAPPE_SHIFT 9 ++#define TANTOS_3G_AR_RAPPE_SIZE 1 ++/* Bit: 'RAPP' */ ++/* Description: 'RARP/ARP Packet Priority' */ ++#define TANTOS_3G_AR_RAPP_OFFSET 0xDC ++#define TANTOS_3G_AR_RAPP_SHIFT 7 ++#define TANTOS_3G_AR_RAPP_SIZE 2 ++/* Bit: 'RAPOTH' */ ++/* Description: 'RARP/ARP Packet Output Tag Handle' */ ++#define TANTOS_3G_AR_RAPOTH_OFFSET 0xDC ++#define TANTOS_3G_AR_RAPOTH_SHIFT 5 ++#define TANTOS_3G_AR_RAPOTH_SIZE 2 ++/* Bit: 'APT' */ ++/* Description: 'ARP Packet Treated as Cross _ VLAN Packet' */ ++#define TANTOS_3G_AR_APT_OFFSET 0xDC ++#define TANTOS_3G_AR_APT_SHIFT 4 ++#define TANTOS_3G_AR_APT_SIZE 1 ++/* Bit: 'RAPTM' */ ++/* Description: 'RARP/ARP Packet Treated as Management Packet' */ ++#define TANTOS_3G_AR_RAPTM_OFFSET 0xDC ++#define TANTOS_3G_AR_RAPTM_SHIFT 3 ++#define TANTOS_3G_AR_RAPTM_SIZE 1 ++/* Bit: 'TAPTS' */ ++/* Description: 'RARP/ARP Packet Treated as Span Packet' */ ++#define TANTOS_3G_AR_TAPTS_OFFSET 0xDC ++#define TANTOS_3G_AR_TAPTS_SHIFT 2 ++#define TANTOS_3G_AR_TAPTS_SIZE 1 ++/* Bit: 'TAP' */ ++/* Description: 'Trap ARP Packet' */ ++#define TANTOS_3G_AR_TAP_OFFSET 0xDC ++#define TANTOS_3G_AR_TAP_SHIFT 1 ++#define TANTOS_3G_AR_TAP_SIZE 1 ++/* Bit: 'TRP' */ ++/* Description: 'Trap RARP Packet' */ ++#define TANTOS_3G_AR_TRP_OFFSET 0xDC ++#define TANTOS_3G_AR_TRP_SHIFT 0 ++#define TANTOS_3G_AR_TRP_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Packet Identification Option' */ ++/* Bit: 'DIVS' */ ++/* Description: 'Do not Identify VLAN after SNAP' */ ++#define TANTOS_3G_PIOFGPM_DIVS_OFFSET 0xDD ++#define TANTOS_3G_PIOFGPM_DIVS_SHIFT 14 ++#define TANTOS_3G_PIOFGPM_DIVS_SIZE 1 ++/* Bit: 'DII6P' */ ++/* Description: 'Do not Identify IPV6 in PPPOE' */ ++#define TANTOS_3G_PIOFGPM_DII6P_OFFSET 0xDD ++#define TANTOS_3G_PIOFGPM_DII6P_SHIFT 13 ++#define TANTOS_3G_PIOFGPM_DII6P_SIZE 1 ++/* Bit: 'DIIPS' */ ++/* Description: 'Do not Identify IP in PPPOE after SNAP' */ ++#define TANTOS_3G_PIOFGPM_DIIPS_OFFSET 0xDD ++#define TANTOS_3G_PIOFGPM_DIIPS_SHIFT 12 ++#define TANTOS_3G_PIOFGPM_DIIPS_SIZE 1 ++/* Bit: 'DIE' */ ++/* Description: 'Do not Identify Ether-Type = 0x0800, IP VER = 6 ++as IPV6 packets' */ ++#define TANTOS_3G_PIOFGPM_DIE_OFFSET 0xDD ++#define TANTOS_3G_PIOFGPM_DIE_SHIFT 11 ++#define TANTOS_3G_PIOFGPM_DIE_SIZE 1 ++/* Bit: 'DIIP' */ ++/* Description: 'Do not Identify IP in PPPOE' */ ++#define TANTOS_3G_PIOFGPM_DIIP_OFFSET 0xDD ++#define TANTOS_3G_PIOFGPM_DIIP_SHIFT 10 ++#define TANTOS_3G_PIOFGPM_DIIP_SIZE 1 ++/* Bit: 'DIS' */ ++/* Description: 'Do not Identify SNAP' */ ++#define TANTOS_3G_PIOFGPM_DIS_OFFSET 0xDD ++#define TANTOS_3G_PIOFGPM_DIS_SHIFT 9 ++#define TANTOS_3G_PIOFGPM_DIS_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Switch Global Control Register 1' */ ++/* Bit: 'TSIPGE' */ ++/* Description: 'Transmit Short IPG Enable' */ ++#define TANTOS_3G_SGC1_TSIPGE_OFFSET 0xE0 ++#define TANTOS_3G_SGC1_TSIPGE_SHIFT 15 ++#define TANTOS_3G_SGC1_TSIPGE_SIZE 1 ++/* Bit: 'PHYBA' */ ++/* Description: 'PHY Base Address' */ ++#define TANTOS_3G_SGC1_PHYBA_OFFSET 0xE0 ++#define TANTOS_3G_SGC1_PHYBA_SHIFT 14 ++#define TANTOS_3G_SGC1_PHYBA_SIZE 1 ++/* Bit: 'DPWECH' */ ++/* Description: 'Drop Packet When Excessive Collision Happen' */ ++#define TANTOS_3G_SGC1_DPWECH_OFFSET 0xE0 ++#define TANTOS_3G_SGC1_DPWECH_SHIFT 13 ++#define TANTOS_3G_SGC1_DPWECH_SIZE 1 ++/* Bit: 'ATS' */ ++/* Description: 'Aging Timer Select' */ ++#define TANTOS_3G_SGC1_ATS_OFFSET 0xE0 ++#define TANTOS_3G_SGC1_ATS_SHIFT 10 ++#define TANTOS_3G_SGC1_ATS_SIZE 3 ++/* Bit: 'MPL' */ ++/* Description: 'Max Packet Length (MAXPKTLEN)' */ ++#define TANTOS_3G_SGC1_MPL_OFFSET 0xE0 ++#define TANTOS_3G_SGC1_MPL_SHIFT 8 ++#define TANTOS_3G_SGC1_MPL_SIZE 2 ++/* Bit: 'DMQ3' */ ++/* Description: 'Discard Mode (Drop scheme for Packets Classified ++as Q3)' */ ++#define TANTOS_3G_SGC1_DMQ3_OFFSET 0xE0 ++#define TANTOS_3G_SGC1_DMQ3_SHIFT 6 ++#define TANTOS_3G_SGC1_DMQ3_SIZE 2 ++/* Bit: 'DMQ2' */ ++/* Description: 'Discard Mode (Drop scheme for Packets Classified ++as Q2)' */ ++#define TANTOS_3G_SGC1_DMQ2_OFFSET 0xE0 ++#define TANTOS_3G_SGC1_DMQ2_SHIFT 4 ++#define TANTOS_3G_SGC1_DMQ2_SIZE 2 ++/* Bit: 'DMQ1' */ ++/* Description: 'Discard Mode (Drop scheme for Packets Classified ++as Q1)' */ ++#define TANTOS_3G_SGC1_DMQ1_OFFSET 0xE0 ++#define TANTOS_3G_SGC1_DMQ1_SHIFT 2 ++#define TANTOS_3G_SGC1_DMQ1_SIZE 2 ++/* Bit: 'DMQ0' */ ++/* Description: 'Discard Mode (Drop scheme for Packets Classified ++as Q0)' */ ++#define TANTOS_3G_SGC1_DMQ0_OFFSET 0xE0 ++#define TANTOS_3G_SGC1_DMQ0_SHIFT 0 ++#define TANTOS_3G_SGC1_DMQ0_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Switch Global Control Register 2' */ ++/* Bit: 'SE' */ ++/* Description: 'Switch Enable. (when WAIT_INIT=1)' */ ++#define TANTOS_3G_SGC2_SE_OFFSET 0xE1 ++#define TANTOS_3G_SGC2_SE_SHIFT 15 ++#define TANTOS_3G_SGC2_SE_SIZE 1 ++/* Bit: 'ICRCCD' */ ++/* Description: 'CRC Check Disable' */ ++#define TANTOS_3G_SGC2_ICRCCD_OFFSET 0xE1 ++#define TANTOS_3G_SGC2_ICRCCD_SHIFT 14 ++#define TANTOS_3G_SGC2_ICRCCD_SIZE 1 ++/* Bit: 'ITRUNK' */ ++/* Description: 'Port 2 and Port 3 Trunk Enable' */ ++#define TANTOS_3G_SGC2_ITRUNK_OFFSET 0xE1 ++#define TANTOS_3G_SGC2_ITRUNK_SHIFT 12 ++#define TANTOS_3G_SGC2_ITRUNK_SIZE 1 ++/* Bit: 'ITENLMT' */ ++/* Description: '10Mbit/s Drop Packet before 100Mbit/s Enable' */ ++#define TANTOS_3G_SGC2_ITENLMT_OFFSET 0xE1 ++#define TANTOS_3G_SGC2_ITENLMT_SHIFT 11 ++#define TANTOS_3G_SGC2_ITENLMT_SIZE 1 ++/* Bit: 'RVID0' */ ++/* Description: 'Replace VID0' */ ++#define TANTOS_3G_SGC2_RVID0_OFFSET 0xE1 ++#define TANTOS_3G_SGC2_RVID0_SHIFT 9 ++#define TANTOS_3G_SGC2_RVID0_SIZE 1 ++/* Bit: 'RVID1' */ ++/* Description: 'Replace VID1' */ ++#define TANTOS_3G_SGC2_RVID1_OFFSET 0xE1 ++#define TANTOS_3G_SGC2_RVID1_SHIFT 8 ++#define TANTOS_3G_SGC2_RVID1_SIZE 1 ++/* Bit: 'RVIDFFF' */ ++/* Description: 'Replace VIDFFF' */ ++#define TANTOS_3G_SGC2_RVIDFFF_OFFSET 0xE1 ++#define TANTOS_3G_SGC2_RVIDFFF_SHIFT 7 ++#define TANTOS_3G_SGC2_RVIDFFF_SIZE 1 ++/* Bit: 'DUPCOLSP' */ ++/* Description: 'Dupcol LED Separate' */ ++#define TANTOS_3G_SGC2_DUPCOLSP_OFFSET 0xE1 ++#define TANTOS_3G_SGC2_DUPCOLSP_SHIFT 6 ++#define TANTOS_3G_SGC2_DUPCOLSP_SIZE 1 ++/* Bit: 'PCR' */ ++/* Description: 'Priority Change Rule' */ ++#define TANTOS_3G_SGC2_PCR_OFFSET 0xE1 ++#define TANTOS_3G_SGC2_PCR_SHIFT 4 ++#define TANTOS_3G_SGC2_PCR_SIZE 1 ++/* Bit: 'PCE' */ ++/* Description: 'Priority Change Enable' */ ++#define TANTOS_3G_SGC2_PCE_OFFSET 0xE1 ++#define TANTOS_3G_SGC2_PCE_SHIFT 3 ++#define TANTOS_3G_SGC2_PCE_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'CPU Port & Mirror Control Register' */ ++/* Bit: 'SPN' */ ++/* Description: 'Sniffer Port Number' */ ++#define TANTOS_3G_CMH_SPN_OFFSET 0xE2 ++#define TANTOS_3G_CMH_SPN_SHIFT 13 ++#define TANTOS_3G_CMH_SPN_SIZE 3 ++/* Bit: 'MCA' */ ++/* Description: 'Mirror CRC Also' */ ++#define TANTOS_3G_CMH_MCA_OFFSET 0xE2 ++#define TANTOS_3G_CMH_MCA_SHIFT 12 ++#define TANTOS_3G_CMH_MCA_SIZE 1 ++/* Bit: 'MRA' */ ++/* Description: 'Mirror RXER Also' */ ++#define TANTOS_3G_CMH_MRA_OFFSET 0xE2 ++#define TANTOS_3G_CMH_MRA_SHIFT 11 ++#define TANTOS_3G_CMH_MRA_SIZE 1 ++/* Bit: 'MPA' */ ++/* Description: 'Mirror PAUSE Also' */ ++#define TANTOS_3G_CMH_MPA_OFFSET 0xE2 ++#define TANTOS_3G_CMH_MPA_SHIFT 10 ++#define TANTOS_3G_CMH_MPA_SIZE 1 ++/* Bit: 'MLA' */ ++/* Description: 'Mirror Long Also' */ ++#define TANTOS_3G_CMH_MLA_OFFSET 0xE2 ++#define TANTOS_3G_CMH_MLA_SHIFT 9 ++#define TANTOS_3G_CMH_MLA_SIZE 1 ++/* Bit: 'MSA' */ ++/* Description: 'Mirror Short Also' */ ++#define TANTOS_3G_CMH_MSA_OFFSET 0xE2 ++#define TANTOS_3G_CMH_MSA_SHIFT 8 ++#define TANTOS_3G_CMH_MSA_SIZE 1 ++/* Bit: 'CPN' */ ++/* Description: 'CPU Port Number' */ ++#define TANTOS_3G_CMH_CPN_OFFSET 0xE2 ++#define TANTOS_3G_CMH_CPN_SHIFT 5 ++#define TANTOS_3G_CMH_CPN_SIZE 3 ++/* Bit: 'STRE' */ ++/* Description: 'Special TAG Receive Enable' */ ++#define TANTOS_3G_CMH_STRE_OFFSET 0xE2 ++#define TANTOS_3G_CMH_STRE_SHIFT 4 ++#define TANTOS_3G_CMH_STRE_SIZE 1 ++/* Bit: 'STTE' */ ++/* Description: 'Special TAG Transmit Enable' */ ++#define TANTOS_3G_CMH_STTE_OFFSET 0xE2 ++#define TANTOS_3G_CMH_STTE_SHIFT 3 ++#define TANTOS_3G_CMH_STTE_SIZE 1 ++/* Bit: 'PAST' */ ++/* Description: 'Pause also adds Special Tag when Special TAG Transmit ++is enabled' */ ++#define TANTOS_3G_CMH_PAST_OFFSET 0xE2 ++#define TANTOS_3G_CMH_PAST_SHIFT 2 ++#define TANTOS_3G_CMH_PAST_SIZE 1 ++/* Bit: 'CCCRC' */ ++/* Description: 'CPU Port doesn't check CRC for packets with Special ++Tag' */ ++#define TANTOS_3G_CMH_CCCRC_OFFSET 0xE2 ++#define TANTOS_3G_CMH_CCCRC_SHIFT 1 ++#define TANTOS_3G_CMH_CCCRC_SIZE 1 ++/* Bit: 'IGSTA' */ ++/* Description: 'Interframe gap for Special Tag application' */ ++#define TANTOS_3G_CMH_IGSTA_OFFSET 0xE2 ++#define TANTOS_3G_CMH_IGSTA_SHIFT 0 ++#define TANTOS_3G_CMH_IGSTA_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Multicast Snooping Register' */ ++/* Bit: 'SCPA' */ ++/* Description: 'Snooping Control Packet Action' */ ++#define TANTOS_3G_MS_SCPA_OFFSET 0xE3 ++#define TANTOS_3G_MS_SCPA_SHIFT 14 ++#define TANTOS_3G_MS_SCPA_SIZE 2 ++/* Bit: 'SCPPE' */ ++/* Description: 'Snooping Control Packet Priority Enable' */ ++#define TANTOS_3G_MS_SCPPE_OFFSET 0xE3 ++#define TANTOS_3G_MS_SCPPE_SHIFT 13 ++#define TANTOS_3G_MS_SCPPE_SIZE 1 ++/* Bit: 'SCPP' */ ++/* Description: 'Snooping Control Packet Priority' */ ++#define TANTOS_3G_MS_SCPP_OFFSET 0xE3 ++#define TANTOS_3G_MS_SCPP_SHIFT 11 ++#define TANTOS_3G_MS_SCPP_SIZE 2 ++/* Bit: 'SCPTTH' */ ++/* Description: 'Snooping Control Packet Transmission Tag Handle' */ ++#define TANTOS_3G_MS_SCPTTH_OFFSET 0xE3 ++#define TANTOS_3G_MS_SCPTTH_SHIFT 9 ++#define TANTOS_3G_MS_SCPTTH_SIZE 2 ++/* Bit: 'SCPTCP' */ ++/* Description: 'Snooping Control Packet Treated as Cross_VLAN Packet' */ ++#define TANTOS_3G_MS_SCPTCP_OFFSET 0xE3 ++#define TANTOS_3G_MS_SCPTCP_SHIFT 8 ++#define TANTOS_3G_MS_SCPTCP_SIZE 1 ++/* Bit: 'SCPTMP' */ ++/* Description: 'Snooping Control Packet Treated as Management Packet' */ ++#define TANTOS_3G_MS_SCPTMP_OFFSET 0xE3 ++#define TANTOS_3G_MS_SCPTMP_SHIFT 7 ++#define TANTOS_3G_MS_SCPTMP_SIZE 1 ++/* Bit: 'SCPTSP' */ ++/* Description: 'Snooping Control Packet Treated as Span Packet' */ ++#define TANTOS_3G_MS_SCPTSP_OFFSET 0xE3 ++#define TANTOS_3G_MS_SCPTSP_SHIFT 6 ++#define TANTOS_3G_MS_SCPTSP_SIZE 1 ++/* Bit: 'ASC' */ ++/* Description: 'Additional Snooping Control. These bits are used ++when the packets on the incoming port with the Ethernet destination ++address = 01-00-5E-XX-XX-XX/33-33-XX-XX-XX-XX are not IGMP_IP/MLD_IPV/ MLD_IPV6 ++packets and not found in the learning table or the hardware IGMP ++table' */ ++#define TANTOS_3G_MS_ASC_OFFSET 0xE3 ++#define TANTOS_3G_MS_ASC_SHIFT 4 ++#define TANTOS_3G_MS_ASC_SIZE 2 ++/* Bit: 'IPMPT' */ ++/* Description: 'IP Multicast Packet Treated as Cross_VLAN packet' */ ++#define TANTOS_3G_MS_IPMPT_OFFSET 0xE3 ++#define TANTOS_3G_MS_IPMPT_SHIFT 2 ++#define TANTOS_3G_MS_IPMPT_SIZE 1 ++/* Bit: 'RV' */ ++/* Description: 'Robust Variable' */ ++#define TANTOS_3G_MS_RV_OFFSET 0xE3 ++#define TANTOS_3G_MS_RV_SHIFT 0 ++#define TANTOS_3G_MS_RV_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Hardware IGMP Control Register' */ ++/* Bit: 'QI' */ ++/* Description: 'Query Interval' */ ++#define TANTOS_3G_HIC_QI_OFFSET 0xE4 ++#define TANTOS_3G_HIC_QI_SHIFT 8 ++#define TANTOS_3G_HIC_QI_SIZE 8 ++/* Bit: 'HIPI' */ ++/* Description: 'Hardware IGMP Packet Ignore CPU Port' */ ++#define TANTOS_3G_HIC_HIPI_OFFSET 0xE4 ++#define TANTOS_3G_HIC_HIPI_SHIFT 7 ++#define TANTOS_3G_HIC_HIPI_SIZE 1 ++/* Bit: 'DRP' */ ++/* Description: 'Default Router Portmap' */ ++#define TANTOS_3G_HIC_DRP_OFFSET 0xE4 ++#define TANTOS_3G_HIC_DRP_SHIFT 0 ++#define TANTOS_3G_HIC_DRP_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Unicast Port Map and Broadcast Port Map' */ ++/* Bit: 'UP' */ ++/* Description: 'Unicast Portmap' */ ++#define TANTOS_3G_UPMBPM_UP_OFFSET 0xE5 ++#define TANTOS_3G_UPMBPM_UP_SHIFT 8 ++#define TANTOS_3G_UPMBPM_UP_SIZE 7 ++/* Bit: 'BP' */ ++/* Description: 'Broadcast Portmap' */ ++#define TANTOS_3G_UPMBPM_BP_OFFSET 0xE5 ++#define TANTOS_3G_UPMBPM_BP_SHIFT 0 ++#define TANTOS_3G_UPMBPM_BP_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Multicast Port Map and Reserve Port Map' */ ++/* Bit: 'MP' */ ++/* Description: 'Multicast Portmap' */ ++#define TANTOS_3G_MPMRPM_MP_OFFSET 0xE6 ++#define TANTOS_3G_MPMRPM_MP_SHIFT 8 ++#define TANTOS_3G_MPMRPM_MP_SIZE 7 ++/* Bit: 'RP' */ ++/* Description: 'Reserve Portmap' */ ++#define TANTOS_3G_MPMRPM_RP_OFFSET 0xE6 ++#define TANTOS_3G_MPMRPM_RP_SHIFT 0 ++#define TANTOS_3G_MPMRPM_RP_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Protocol Filter Action' */ ++/* Bit: 'APF7' */ ++/* Description: 'Action for Protocol Filter 7' */ ++#define TANTOS_3G_PFA_APF7_OFFSET 0xE7 ++#define TANTOS_3G_PFA_APF7_SHIFT 14 ++#define TANTOS_3G_PFA_APF7_SIZE 2 ++/* Bit: 'APF6' */ ++/* Description: 'Action for Protocol Filter 6' */ ++#define TANTOS_3G_PFA_APF6_OFFSET 0xE7 ++#define TANTOS_3G_PFA_APF6_SHIFT 12 ++#define TANTOS_3G_PFA_APF6_SIZE 2 ++/* Bit: 'APF5' */ ++/* Description: 'Action for Protocol Filter 5' */ ++#define TANTOS_3G_PFA_APF5_OFFSET 0xE7 ++#define TANTOS_3G_PFA_APF5_SHIFT 10 ++#define TANTOS_3G_PFA_APF5_SIZE 2 ++/* Bit: 'APF4' */ ++/* Description: 'Action for Protocol Filter 4' */ ++#define TANTOS_3G_PFA_APF4_OFFSET 0xE7 ++#define TANTOS_3G_PFA_APF4_SHIFT 8 ++#define TANTOS_3G_PFA_APF4_SIZE 2 ++/* Bit: 'APF3' */ ++/* Description: 'Action for Protocol Filter 3' */ ++#define TANTOS_3G_PFA_APF3_OFFSET 0xE7 ++#define TANTOS_3G_PFA_APF3_SHIFT 6 ++#define TANTOS_3G_PFA_APF3_SIZE 2 ++/* Bit: 'APF2' */ ++/* Description: 'Action for Protocol Filter 2' */ ++#define TANTOS_3G_PFA_APF2_OFFSET 0xE7 ++#define TANTOS_3G_PFA_APF2_SHIFT 4 ++#define TANTOS_3G_PFA_APF2_SIZE 2 ++/* Bit: 'APF1' */ ++/* Description: 'Action for Protocol Filter 1' */ ++#define TANTOS_3G_PFA_APF1_OFFSET 0xE7 ++#define TANTOS_3G_PFA_APF1_SHIFT 2 ++#define TANTOS_3G_PFA_APF1_SIZE 2 ++/* Bit: 'APF0' */ ++/* Description: 'Action for Protocol Filter 0' */ ++#define TANTOS_3G_PFA_APF0_OFFSET 0xE7 ++#define TANTOS_3G_PFA_APF0_SHIFT 0 ++#define TANTOS_3G_PFA_APF0_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: '802.1p Priority Map Register' */ ++/* Bit: '1PPQ7' */ ++/* Description: 'Priority Queue 7' */ ++#define TANTOS_3G_1PPM_1PPQ7_OFFSET 0xE8 ++#define TANTOS_3G_1PPM_1PPQ7_SHIFT 14 ++#define TANTOS_3G_1PPM_1PPQ7_SIZE 2 ++/* Bit: '1PPQ6' */ ++/* Description: 'Priority Queue 6' */ ++#define TANTOS_3G_1PPM_1PPQ6_OFFSET 0xE8 ++#define TANTOS_3G_1PPM_1PPQ6_SHIFT 12 ++#define TANTOS_3G_1PPM_1PPQ6_SIZE 2 ++/* Bit: '1PPQ5' */ ++/* Description: 'Priority Queue 5' */ ++#define TANTOS_3G_1PPM_1PPQ5_OFFSET 0xE8 ++#define TANTOS_3G_1PPM_1PPQ5_SHIFT 10 ++#define TANTOS_3G_1PPM_1PPQ5_SIZE 2 ++/* Bit: '1PPQ4' */ ++/* Description: 'Priority Queue 4' */ ++#define TANTOS_3G_1PPM_1PPQ4_OFFSET 0xE8 ++#define TANTOS_3G_1PPM_1PPQ4_SHIFT 8 ++#define TANTOS_3G_1PPM_1PPQ4_SIZE 2 ++/* Bit: '1PPQ3' */ ++/* Description: 'Priority Queue 3' */ ++#define TANTOS_3G_1PPM_1PPQ3_OFFSET 0xE8 ++#define TANTOS_3G_1PPM_1PPQ3_SHIFT 6 ++#define TANTOS_3G_1PPM_1PPQ3_SIZE 2 ++/* Bit: '1PPQ2' */ ++/* Description: 'Priority Queue 2' */ ++#define TANTOS_3G_1PPM_1PPQ2_OFFSET 0xE8 ++#define TANTOS_3G_1PPM_1PPQ2_SHIFT 4 ++#define TANTOS_3G_1PPM_1PPQ2_SIZE 2 ++/* Bit: '1PPQ1' */ ++/* Description: 'Priority Queue 1' */ ++#define TANTOS_3G_1PPM_1PPQ1_OFFSET 0xE8 ++#define TANTOS_3G_1PPM_1PPQ1_SHIFT 2 ++#define TANTOS_3G_1PPM_1PPQ1_SIZE 2 ++/* Bit: '1PPQ0' */ ++/* Description: 'Priority Queue 0' */ ++#define TANTOS_3G_1PPM_1PPQ0_OFFSET 0xE8 ++#define TANTOS_3G_1PPM_1PPQ0_SHIFT 0 ++#define TANTOS_3G_1PPM_1PPQ0_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Switch MAC Address Register 1' */ ++/* Bit: 'ADDR47_41' */ ++/* Description: 'Address [47:41]' */ ++#define TANTOS_3G_SMA1_ADDR47_41_OFFSET 0xE9 ++#define TANTOS_3G_SMA1_ADDR47_41_SHIFT 9 ++#define TANTOS_3G_SMA1_ADDR47_41_SIZE 7 ++/* Bit: 'PAC' */ ++/* Description: 'Pause Address Change' */ ++#define TANTOS_3G_SMA1_PAC_OFFSET 0xE9 ++#define TANTOS_3G_SMA1_PAC_SHIFT 8 ++#define TANTOS_3G_SMA1_PAC_SIZE 1 ++/* Bit: 'ADDR39_32' */ ++/* Description: 'Address [39:32]' */ ++#define TANTOS_3G_SMA1_ADDR39_32_OFFSET 0xE9 ++#define TANTOS_3G_SMA1_ADDR39_32_SHIFT 0 ++#define TANTOS_3G_SMA1_ADDR39_32_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Switch MAC Address Register 2' */ ++/* Bit: 'ADDR31_16' */ ++/* Description: 'Address [31:16]' */ ++#define TANTOS_3G_SMA2_ADDR31_16_OFFSET 0xEA ++#define TANTOS_3G_SMA2_ADDR31_16_SHIFT 0 ++#define TANTOS_3G_SMA2_ADDR31_16_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Switch MAC Address Register 3' */ ++/* Bit: 'ADDR15_0' */ ++/* Description: 'Address [15:0]' */ ++#define TANTOS_3G_SMA3_ADDR15_0_OFFSET 0xEB ++#define TANTOS_3G_SMA3_ADDR15_0_SHIFT 0 ++#define TANTOS_3G_SMA3_ADDR15_0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Global Bucket Size Base counter' */ ++/* Bit: 'Base15_0' */ ++/* Description: 'Base[15:0]' */ ++#define TANTOS_3G_GBSBC_BASE15_0_OFFSET 0xEC ++#define TANTOS_3G_GBSBC_BASE15_0_SHIFT 0 ++#define TANTOS_3G_GBSBC_BASE15_0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Global Bucket Size Extend Base Counter' */ ++/* Bit: 'EBase15_0' */ ++/* Description: 'Extend Base[15:0]' */ ++#define TANTOS_3G_GBSEBC_EBASE15_0_OFFSET 0xED ++#define TANTOS_3G_GBSEBC_EBASE15_0_SHIFT 0 ++#define TANTOS_3G_GBSEBC_EBASE15_0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Global Bucket Size Counter High Bits' */ ++/* Bit: 'EBase17_16' */ ++/* Description: 'EBase[17:16]' */ ++#define TANTOS_3G_GBSCHB_EBASE17_16_OFFSET 0xEE ++#define TANTOS_3G_GBSCHB_EBASE17_16_SHIFT 8 ++#define TANTOS_3G_GBSCHB_EBASE17_16_SIZE 2 ++/* Bit: 'Base17_16' */ ++/* Description: 'Base[17:16]' */ ++#define TANTOS_3G_GBSCHB_BASE17_16_OFFSET 0xEE ++#define TANTOS_3G_GBSCHB_BASE17_16_SHIFT 0 ++#define TANTOS_3G_GBSCHB_BASE17_16_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Congestion Control register' */ ++/* Bit: 'EDSTX' */ ++/* Description: 'Drop scheme selection' */ ++#define TANTOS_3G_CCR_EDSTX_OFFSET 0xEF ++#define TANTOS_3G_CCR_EDSTX_SHIFT 15 ++#define TANTOS_3G_CCR_EDSTX_SIZE 1 ++/* Bit: 'IRSJA' */ ++/* Description: 'IGMP Report Supression and Join Aggregation control' */ ++#define TANTOS_3G_CCR_IRSJA_OFFSET 0xEF ++#define TANTOS_3G_CCR_IRSJA_SHIFT 8 ++#define TANTOS_3G_CCR_IRSJA_SIZE 2 ++/* Bit: 'IJT' */ ++/* Description: 'Input Jam Threshold' */ ++#define TANTOS_3G_CCR_IJT_OFFSET 0xEF ++#define TANTOS_3G_CCR_IJT_SHIFT 0 ++#define TANTOS_3G_CCR_IJT_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Storm control Register 0' */ ++/* Bit: 'STORM_B' */ ++/* Description: 'Storm Enable for Broadcast Packets' */ ++#define TANTOS_3G_SCR0_STORM_B_OFFSET 0xF0 ++#define TANTOS_3G_SCR0_STORM_B_SHIFT 15 ++#define TANTOS_3G_SCR0_STORM_B_SIZE 1 ++/* Bit: 'STORM_M' */ ++/* Description: 'Storm Enable for Multicast Packets' */ ++#define TANTOS_3G_SCR0_STORM_M_OFFSET 0xF0 ++#define TANTOS_3G_SCR0_STORM_M_SHIFT 14 ++#define TANTOS_3G_SCR0_STORM_M_SIZE 1 ++/* Bit: 'STORM_U' */ ++/* Description: 'Storm Enable for Un-learned Unicast Packets' */ ++#define TANTOS_3G_SCR0_STORM_U_OFFSET 0xF0 ++#define TANTOS_3G_SCR0_STORM_U_SHIFT 13 ++#define TANTOS_3G_SCR0_STORM_U_SIZE 1 ++/* Bit: 'STORM_100_TH' */ ++/* Description: '100M Threshold' */ ++#define TANTOS_3G_SCR0_STORM_100_TH_OFFSET 0xF0 ++#define TANTOS_3G_SCR0_STORM_100_TH_SHIFT 0 ++#define TANTOS_3G_SCR0_STORM_100_TH_SIZE 13 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Storm Control Register 1' */ ++/* Bit: 'STORM_10_TH' */ ++/* Description: '10M Threshold' */ ++#define TANTOS_3G_SCR1_STORM_10_TH_OFFSET 0xF1 ++#define TANTOS_3G_SCR1_STORM_10_TH_SHIFT 0 ++#define TANTOS_3G_SCR1_STORM_10_TH_SIZE 13 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Management Clock Select Register' */ ++/* Bit: 'MCS' */ ++/* Description: 'Management Clock Select' */ ++#define TANTOS_3G_MCSR_MCS_OFFSET 0xF2 ++#define TANTOS_3G_MCSR_MCS_SHIFT 0 ++#define TANTOS_3G_MCSR_MCS_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'RGMII/GMII Port Control Register' */ ++/* Bit: 'P6SPD' */ ++/* Description: 'Port 6 Speed' */ ++#define TANTOS_3G_RGMIICR_P6SPD_OFFSET 0xF5 ++#define TANTOS_3G_RGMIICR_P6SPD_SHIFT 10 ++#define TANTOS_3G_RGMIICR_P6SPD_SIZE 2 ++/* Bit: 'P6DUP' */ ++/* Description: 'Port 6 Duplex mode' */ ++#define TANTOS_3G_RGMIICR_P6DUP_OFFSET 0xF5 ++#define TANTOS_3G_RGMIICR_P6DUP_SHIFT 9 ++#define TANTOS_3G_RGMIICR_P6DUP_SIZE 1 ++/* Bit: 'P6FCE' */ ++/* Description: 'Port 6 Flow Control Enable' */ ++#define TANTOS_3G_RGMIICR_P6FCE_OFFSET 0xF5 ++#define TANTOS_3G_RGMIICR_P6FCE_SHIFT 8 ++#define TANTOS_3G_RGMIICR_P6FCE_SIZE 1 ++/* Bit: 'P5SPD' */ ++/* Description: 'Port 5 Speed' */ ++#define TANTOS_3G_RGMIICR_P5SPD_OFFSET 0xF5 ++#define TANTOS_3G_RGMIICR_P5SPD_SHIFT 6 ++#define TANTOS_3G_RGMIICR_P5SPD_SIZE 2 ++/* Bit: 'P5DUP' */ ++/* Description: 'Port 5 Duplex mode' */ ++#define TANTOS_3G_RGMIICR_P5DUP_OFFSET 0xF5 ++#define TANTOS_3G_RGMIICR_P5DUP_SHIFT 5 ++#define TANTOS_3G_RGMIICR_P5DUP_SIZE 1 ++/* Bit: 'P5FCE' */ ++/* Description: 'Port 5 Flow Control Enable' */ ++#define TANTOS_3G_RGMIICR_P5FCE_OFFSET 0xF5 ++#define TANTOS_3G_RGMIICR_P5FCE_SHIFT 4 ++#define TANTOS_3G_RGMIICR_P5FCE_SIZE 1 ++/* Bit: 'P4SPD' */ ++/* Description: 'Port 4 Speed' */ ++#define TANTOS_3G_RGMIICR_P4SPD_OFFSET 0xF5 ++#define TANTOS_3G_RGMIICR_P4SPD_SHIFT 2 ++#define TANTOS_3G_RGMIICR_P4SPD_SIZE 2 ++/* Bit: 'P4DUP' */ ++/* Description: 'Port 4 Duplex mode' */ ++#define TANTOS_3G_RGMIICR_P4DUP_OFFSET 0xF5 ++#define TANTOS_3G_RGMIICR_P4DUP_SHIFT 1 ++#define TANTOS_3G_RGMIICR_P4DUP_SIZE 1 ++/* Bit: 'P4FCE' */ ++/* Description: 'Port 4 Flow Control Enable' */ ++#define TANTOS_3G_RGMIICR_P4FCE_OFFSET 0xF5 ++#define TANTOS_3G_RGMIICR_P4FCE_SHIFT 0 ++#define TANTOS_3G_RGMIICR_P4FCE_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Hardware IGMP Option Register' */ ++/* Bit: 'TIMERC' */ ++/* Description: 'Timer configuration for IGMP' */ ++#define TANTOS_3G_HIOR_TIMERC_OFFSET 0xF6 ++#define TANTOS_3G_HIOR_TIMERC_SHIFT 9 ++#define TANTOS_3G_HIOR_TIMERC_SIZE 1 ++/* Bit: 'HISE' */ ++/* Description: 'Hardware IGMP Snooping Enable' */ ++#define TANTOS_3G_HIOR_HISE_OFFSET 0xF6 ++#define TANTOS_3G_HIOR_HISE_SHIFT 8 ++#define TANTOS_3G_HIOR_HISE_SIZE 1 ++/* Bit: 'HISFL' */ ++/* Description: 'Hardware IGMP Snooping fast Leave option' */ ++#define TANTOS_3G_HIOR_HISFL_OFFSET 0xF6 ++#define TANTOS_3G_HIOR_HISFL_SHIFT 7 ++#define TANTOS_3G_HIOR_HISFL_SIZE 1 ++/* Bit: 'IGMPV3E' */ ++/* Description: 'IGMPv3 enable' */ ++#define TANTOS_3G_HIOR_IGMPV3E_OFFSET 0xF6 ++#define TANTOS_3G_HIOR_IGMPV3E_SHIFT 6 ++#define TANTOS_3G_HIOR_IGMPV3E_SIZE 1 ++/* Bit: 'SARE' */ ++/* Description: 'SA Replacement Enable' */ ++#define TANTOS_3G_HIOR_SARE_OFFSET 0xF6 ++#define TANTOS_3G_HIOR_SARE_SHIFT 5 ++#define TANTOS_3G_HIOR_SARE_SIZE 1 ++/* Bit: 'PPPoEHR' */ ++/* Description: 'PPPoE header remove for IGMP data stream enable' */ ++#define TANTOS_3G_HIOR_PPPOEHR_OFFSET 0xF6 ++#define TANTOS_3G_HIOR_PPPOEHR_SHIFT 4 ++#define TANTOS_3G_HIOR_PPPOEHR_SIZE 1 ++/* Bit: 'B33' */ ++/* Description: 'Broadcast 33.33.0.0.0.x disable' */ ++#define TANTOS_3G_HIOR_B33_OFFSET 0xF6 ++#define TANTOS_3G_HIOR_B33_SHIFT 3 ++#define TANTOS_3G_HIOR_B33_SIZE 1 ++/* Bit: 'B01' */ ++/* Description: 'Broadcast 01.0.5E.0.0.x disable' */ ++#define TANTOS_3G_HIOR_B01_OFFSET 0xF6 ++#define TANTOS_3G_HIOR_B01_SHIFT 2 ++#define TANTOS_3G_HIOR_B01_SIZE 1 ++/* Bit: 'B224' */ ++/* Description: 'Broadcast 224.0.0.x disable' */ ++#define TANTOS_3G_HIOR_B224_OFFSET 0xF6 ++#define TANTOS_3G_HIOR_B224_SHIFT 1 ++#define TANTOS_3G_HIOR_B224_SIZE 1 ++/* Bit: 'DAIPS' */ ++/* Description: 'DA or IP for Search group ID' */ ++#define TANTOS_3G_HIOR_DAIPS_OFFSET 0xF6 ++#define TANTOS_3G_HIOR_DAIPS_SHIFT 0 ++#define TANTOS_3G_HIOR_DAIPS_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PPPoE Session ID Register' */ ++/* Bit: 'PPPoESID' */ ++/* Description: 'PPPoE Session ID' */ ++#define TANTOS_3G_PSIDR_PPPOESID_OFFSET 0xF7 ++#define TANTOS_3G_PSIDR_PPPOESID_SHIFT 0 ++#define TANTOS_3G_PSIDR_PPPOESID_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Chip Identifier 0' */ ++/* Bit: 'BOND' */ ++/* Description: 'Bonding Option' */ ++#define TANTOS_3G_CI0_BOND_OFFSET 0x100 ++#define TANTOS_3G_CI0_BOND_SHIFT 4 ++#define TANTOS_3G_CI0_BOND_SIZE 1 ++/* Bit: 'VN' */ ++/* Description: 'Version Number' */ ++#define TANTOS_3G_CI0_VN_OFFSET 0x100 ++#define TANTOS_3G_CI0_VN_SHIFT 0 ++#define TANTOS_3G_CI0_VN_SIZE 4 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Chip Identifier 1' */ ++/* Bit: 'PC' */ ++/* Description: 'Product Code' */ ++#define TANTOS_3G_CI1_PC_OFFSET 0x101 ++#define TANTOS_3G_CI1_PC_SHIFT 0 ++#define TANTOS_3G_CI1_PC_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Global Status and Hardware Setting Register' */ ++/* Bit: 'LTBR' */ ++/* Description: 'Learning Table Bist Result' */ ++#define TANTOS_3G_GSHS_LTBR_OFFSET 0x102 ++#define TANTOS_3G_GSHS_LTBR_SHIFT 11 ++#define TANTOS_3G_GSHS_LTBR_SIZE 1 ++/* Bit: 'LLTBR' */ ++/* Description: 'Linklist Table Bist Result' */ ++#define TANTOS_3G_GSHS_LLTBR_OFFSET 0x102 ++#define TANTOS_3G_GSHS_LLTBR_SHIFT 10 ++#define TANTOS_3G_GSHS_LLTBR_SIZE 1 ++/* Bit: 'CTBR' */ ++/* Description: 'Control Table Bist Result' */ ++#define TANTOS_3G_GSHS_CTBR_OFFSET 0x102 ++#define TANTOS_3G_GSHS_CTBR_SHIFT 9 ++#define TANTOS_3G_GSHS_CTBR_SIZE 1 ++/* Bit: 'HISTBR' */ ++/* Description: 'Hardware IGMP Source List Table Bist Result' */ ++#define TANTOS_3G_GSHS_HISTBR_OFFSET 0x102 ++#define TANTOS_3G_GSHS_HISTBR_SHIFT 8 ++#define TANTOS_3G_GSHS_HISTBR_SIZE 1 ++/* Bit: 'HIGTBR' */ ++/* Description: 'Hardware IGMP Group Table Bist Result' */ ++#define TANTOS_3G_GSHS_HIGTBR_OFFSET 0x102 ++#define TANTOS_3G_GSHS_HIGTBR_SHIFT 7 ++#define TANTOS_3G_GSHS_HIGTBR_SIZE 1 ++/* Bit: 'DBBR' */ ++/* Description: 'Data Buffer Bist Result' */ ++#define TANTOS_3G_GSHS_DBBR_OFFSET 0x102 ++#define TANTOS_3G_GSHS_DBBR_SHIFT 6 ++#define TANTOS_3G_GSHS_DBBR_SIZE 1 ++/* Bit: 'P6M' */ ++/* Description: 'P6 Mode' */ ++#define TANTOS_3G_GSHS_P6M_OFFSET 0x102 ++#define TANTOS_3G_GSHS_P6M_SHIFT 4 ++#define TANTOS_3G_GSHS_P6M_SIZE 2 ++/* Bit: 'P5M' */ ++/* Description: 'P5 Mode' */ ++#define TANTOS_3G_GSHS_P5M_OFFSET 0x102 ++#define TANTOS_3G_GSHS_P5M_SHIFT 2 ++#define TANTOS_3G_GSHS_P5M_SIZE 2 ++/* Bit: 'P4M' */ ++/* Description: 'P4 Mode' */ ++#define TANTOS_3G_GSHS_P4M_OFFSET 0x102 ++#define TANTOS_3G_GSHS_P4M_SHIFT 0 ++#define TANTOS_3G_GSHS_P4M_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Address Table Control 0 Register' */ ++/* Bit: 'ADDR15_0' */ ++/* Description: 'Address [15:0]' */ ++#define TANTOS_3G_ATC0_ADDR15_0_OFFSET 0x104 ++#define TANTOS_3G_ATC0_ADDR15_0_SHIFT 0 ++#define TANTOS_3G_ATC0_ADDR15_0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Address Table Control 1 Register' */ ++/* Bit: 'ADDR31_16' */ ++/* Description: 'Address [31:16]' */ ++#define TANTOS_3G_ATC1_ADDR31_16_OFFSET 0x105 ++#define TANTOS_3G_ATC1_ADDR31_16_SHIFT 0 ++#define TANTOS_3G_ATC1_ADDR31_16_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Address Table Control 2 Register' */ ++/* Bit: 'ADDR47_32' */ ++/* Description: 'Address [47:32]' */ ++#define TANTOS_3G_ATC2_ADDR47_32_OFFSET 0x106 ++#define TANTOS_3G_ATC2_ADDR47_32_SHIFT 0 ++#define TANTOS_3G_ATC2_ADDR47_32_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Address Table Control 3 Register' */ ++/* Bit: 'PMAP' */ ++/* Description: 'Port Map' */ ++#define TANTOS_3G_ATC3_PMAP_OFFSET 0x107 ++#define TANTOS_3G_ATC3_PMAP_SHIFT 4 ++#define TANTOS_3G_ATC3_PMAP_SIZE 7 ++/* Bit: 'FID' */ ++/* Description: 'FID group' */ ++#define TANTOS_3G_ATC3_FID_OFFSET 0x107 ++#define TANTOS_3G_ATC3_FID_SHIFT 0 ++#define TANTOS_3G_ATC3_FID_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Address Table Control 4 Register' */ ++/* Bit: 'INFOT' */ ++/* Description: 'Info Type: Static address' */ ++#define TANTOS_3G_ATC4_INFOT_OFFSET 0x108 ++#define TANTOS_3G_ATC4_INFOT_SHIFT 12 ++#define TANTOS_3G_ATC4_INFOT_SIZE 1 ++/* Bit: 'ITAT' */ ++/* Description: 'Info_Ctrl/Age Timer' */ ++#define TANTOS_3G_ATC4_ITAT_OFFSET 0x108 ++#define TANTOS_3G_ATC4_ITAT_SHIFT 0 ++#define TANTOS_3G_ATC4_ITAT_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Address Table Control 5 Register' */ ++/* Bit: 'FCE' */ ++/* Description: 'Find within the current entry' */ ++#define TANTOS_3G_ATC5_FCE_OFFSET 0x109 ++#define TANTOS_3G_ATC5_FCE_SHIFT 7 ++#define TANTOS_3G_ATC5_FCE_SIZE 1 ++/* Bit: 'CMD' */ ++/* Description: 'Command' */ ++#define TANTOS_3G_ATC5_CMD_OFFSET 0x109 ++#define TANTOS_3G_ATC5_CMD_SHIFT 4 ++#define TANTOS_3G_ATC5_CMD_SIZE 3 ++/* Bit: 'AC' */ ++/* Description: 'Access Control' */ ++#define TANTOS_3G_ATC5_AC_OFFSET 0x109 ++#define TANTOS_3G_ATC5_AC_SHIFT 0 ++#define TANTOS_3G_ATC5_AC_SIZE 4 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Address Table Status 0 Register' */ ++/* Bit: 'ADDRS15_0' */ ++/* Description: 'Address [15:0]' */ ++#define TANTOS_3G_ATS0_ADDRS15_0_OFFSET 0x10A ++#define TANTOS_3G_ATS0_ADDRS15_0_SHIFT 0 ++#define TANTOS_3G_ATS0_ADDRS15_0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Address Table Status 1 Register' */ ++/* Bit: 'ADDRS31_16' */ ++/* Description: 'Address [31:16]' */ ++#define TANTOS_3G_ATS1_ADDRS31_16_OFFSET 0x10B ++#define TANTOS_3G_ATS1_ADDRS31_16_SHIFT 0 ++#define TANTOS_3G_ATS1_ADDRS31_16_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Address Table Status 2 Register' */ ++/* Bit: 'ADDRS47_32' */ ++/* Description: 'Address [47:32]' */ ++#define TANTOS_3G_ATS2_ADDRS47_32_OFFSET 0x10C ++#define TANTOS_3G_ATS2_ADDRS47_32_SHIFT 0 ++#define TANTOS_3G_ATS2_ADDRS47_32_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Address Table Status 3 Register' */ ++/* Bit: 'PMAPS' */ ++/* Description: 'Port Map' */ ++#define TANTOS_3G_ATS3_PMAPS_OFFSET 0x10D ++#define TANTOS_3G_ATS3_PMAPS_SHIFT 4 ++#define TANTOS_3G_ATS3_PMAPS_SIZE 7 ++/* Bit: 'FIDS' */ ++/* Description: 'FID group' */ ++#define TANTOS_3G_ATS3_FIDS_OFFSET 0x10D ++#define TANTOS_3G_ATS3_FIDS_SHIFT 0 ++#define TANTOS_3G_ATS3_FIDS_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Address Table Status 4 Register' */ ++/* Bit: 'BAD' */ ++/* Description: 'Bad Status' */ ++#define TANTOS_3G_ATS4_BAD_OFFSET 0x10E ++#define TANTOS_3G_ATS4_BAD_SHIFT 14 ++#define TANTOS_3G_ATS4_BAD_SIZE 1 ++/* Bit: 'OCP' */ ++/* Description: 'Occupy' */ ++#define TANTOS_3G_ATS4_OCP_OFFSET 0x10E ++#define TANTOS_3G_ATS4_OCP_SHIFT 13 ++#define TANTOS_3G_ATS4_OCP_SIZE 1 ++/* Bit: 'INFOTS' */ ++/* Description: 'Info Type: Static address' */ ++#define TANTOS_3G_ATS4_INFOTS_OFFSET 0x10E ++#define TANTOS_3G_ATS4_INFOTS_SHIFT 12 ++#define TANTOS_3G_ATS4_INFOTS_SIZE 1 ++/* Bit: 'ITATS' */ ++/* Description: 'Info_Ctrl/Age Timer Status' */ ++#define TANTOS_3G_ATS4_ITATS_OFFSET 0x10E ++#define TANTOS_3G_ATS4_ITATS_SHIFT 0 ++#define TANTOS_3G_ATS4_ITATS_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Address Table Status 5 Register' */ ++/* Bit: 'BUSY' */ ++/* Description: 'Busy' */ ++#define TANTOS_3G_ATS5_BUSY_OFFSET 0x10F ++#define TANTOS_3G_ATS5_BUSY_SHIFT 15 ++#define TANTOS_3G_ATS5_BUSY_SIZE 1 ++/* Bit: 'RSLT' */ ++/* Description: 'Result' */ ++#define TANTOS_3G_ATS5_RSLT_OFFSET 0x10F ++#define TANTOS_3G_ATS5_RSLT_SHIFT 12 ++#define TANTOS_3G_ATS5_RSLT_SIZE 3 ++/* Bit: 'FCE' */ ++/* Description: 'Find within the current entry' */ ++#define TANTOS_3G_ATS5_FCE_OFFSET 0x10F ++#define TANTOS_3G_ATS5_FCE_SHIFT 7 ++#define TANTOS_3G_ATS5_FCE_SIZE 1 ++/* Bit: 'CMD' */ ++/* Description: 'Command' */ ++#define TANTOS_3G_ATS5_CMD_OFFSET 0x10F ++#define TANTOS_3G_ATS5_CMD_SHIFT 4 ++#define TANTOS_3G_ATS5_CMD_SIZE 3 ++/* Bit: 'AC' */ ++/* Description: 'Access Control' */ ++#define TANTOS_3G_ATS5_AC_OFFSET 0x10F ++#define TANTOS_3G_ATS5_AC_SHIFT 0 ++#define TANTOS_3G_ATS5_AC_SIZE 4 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'IGMP Table Control 0 Register' */ ++/* Bit: 'SIP15_0' */ ++/* Description: 'Source IP[15:0]' */ ++#define TANTOS_3G_IGMPTC0_SIP15_0_OFFSET 0x110 ++#define TANTOS_3G_IGMPTC0_SIP15_0_SHIFT 0 ++#define TANTOS_3G_IGMPTC0_SIP15_0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'IGMP Table Control 1 Register' */ ++/* Bit: 'SIP31_16' */ ++/* Description: 'Source IP[31:16]' */ ++#define TANTOS_3G_IGMPTC1_SIP31_16_OFFSET 0x111 ++#define TANTOS_3G_IGMPTC1_SIP31_16_SHIFT 0 ++#define TANTOS_3G_IGMPTC1_SIP31_16_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'IGMP Table Control 2 Register' */ ++/* Bit: 'SIP47_32' */ ++/* Description: 'Source IP[47:32] for IPv6 MLD' */ ++#define TANTOS_3G_IGMPTC2_SIP47_32_OFFSET 0x112 ++#define TANTOS_3G_IGMPTC2_SIP47_32_SHIFT 0 ++#define TANTOS_3G_IGMPTC2_SIP47_32_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'IGMP Table Control 3 Register' */ ++/* Bit: 'GID15_0' */ ++/* Description: 'Group ID [15:0]' */ ++#define TANTOS_3G_IGMPTC3_GID15_0_OFFSET 0x113 ++#define TANTOS_3G_IGMPTC3_GID15_0_SHIFT 0 ++#define TANTOS_3G_IGMPTC3_GID15_0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'IGMP Table Control 4 Register' */ ++/* Bit: 'GID31_16' */ ++/* Description: 'Group ID [31:16]. For IPv4 only [23:16] are used.' */ ++#define TANTOS_3G_IGMPTC4_GID31_16_OFFSET 0x114 ++#define TANTOS_3G_IGMPTC4_GID31_16_SHIFT 0 ++#define TANTOS_3G_IGMPTC4_GID31_16_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'IGMP Table Control 5 Register' */ ++/* Bit: 'ICMD' */ ++/* Description: 'IGMP Command' */ ++#define TANTOS_3G_IGMPTC5_ICMD_OFFSET 0x115 ++#define TANTOS_3G_IGMPTC5_ICMD_SHIFT 8 ++#define TANTOS_3G_IGMPTC5_ICMD_SIZE 3 ++/* Bit: 'INVC' */ ++/* Description: 'Invalid control' */ ++#define TANTOS_3G_IGMPTC5_INVC_OFFSET 0x115 ++#define TANTOS_3G_IGMPTC5_INVC_SHIFT 5 ++#define TANTOS_3G_IGMPTC5_INVC_SIZE 1 ++/* Bit: 'FMODE' */ ++/* Description: 'Filter Mode' */ ++#define TANTOS_3G_IGMPTC5_FMODE_OFFSET 0x115 ++#define TANTOS_3G_IGMPTC5_FMODE_SHIFT 4 ++#define TANTOS_3G_IGMPTC5_FMODE_SIZE 1 ++/* Bit: 'PORT' */ ++/* Description: 'Port number associated with this command' */ ++#define TANTOS_3G_IGMPTC5_PORT_OFFSET 0x115 ++#define TANTOS_3G_IGMPTC5_PORT_SHIFT 0 ++#define TANTOS_3G_IGMPTC5_PORT_SIZE 3 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'IGMP Table Status 0 Register' */ ++/* Bit: 'SIPGID0' */ ++/* Description: 'Source IP or Group ID bit [15:0]' */ ++#define TANTOS_3G_IGMPTS0_SIPGID0_OFFSET 0x116 ++#define TANTOS_3G_IGMPTS0_SIPGID0_SHIFT 0 ++#define TANTOS_3G_IGMPTS0_SIPGID0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'IGMP Table Status 1 Register' */ ++/* Bit: 'SIPGID1' */ ++/* Description: 'Source IP or Group ID bit [31:16]' */ ++#define TANTOS_3G_IGMPTS1_SIPGID1_OFFSET 0x117 ++#define TANTOS_3G_IGMPTS1_SIPGID1_SHIFT 0 ++#define TANTOS_3G_IGMPTS1_SIPGID1_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'IGMP Table Status 2 Register' */ ++/* Bit: 'SIPGID2' */ ++/* Description: 'Source IP or Group ID bit [47:32]' */ ++#define TANTOS_3G_IGMPTS2_SIPGID2_OFFSET 0x118 ++#define TANTOS_3G_IGMPTS2_SIPGID2_SHIFT 0 ++#define TANTOS_3G_IGMPTS2_SIPGID2_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'IGMP Table Status 3 Register' */ ++/* Bit: 'S3PMI' */ ++/* Description: 'Port Map Include/exclude Status' */ ++#define TANTOS_3G_IGMPTS3_S3PMI_OFFSET 0x119 ++#define TANTOS_3G_IGMPTS3_S3PMI_SHIFT 7 ++#define TANTOS_3G_IGMPTS3_S3PMI_SIZE 7 ++/* Bit: 'S3PMV' */ ++/* Description: 'Port Map Valid Status' */ ++#define TANTOS_3G_IGMPTS3_S3PMV_OFFSET 0x119 ++#define TANTOS_3G_IGMPTS3_S3PMV_SHIFT 0 ++#define TANTOS_3G_IGMPTS3_S3PMV_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'IGMP Table Status 4 Register' */ ++/* Bit: 'S4BUSY' */ ++/* Description: 'Busy' */ ++#define TANTOS_3G_IGMPTS4_S4BUSY_OFFSET 0x11A ++#define TANTOS_3G_IGMPTS4_S4BUSY_SHIFT 3 ++#define TANTOS_3G_IGMPTS4_S4BUSY_SIZE 1 ++/* Bit: 'S4R' */ ++/* Description: 'Result' */ ++#define TANTOS_3G_IGMPTS4_S4R_OFFSET 0x11A ++#define TANTOS_3G_IGMPTS4_S4R_SHIFT 0 ++#define TANTOS_3G_IGMPTS4_S4R_SIZE 3 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'RMON Counter Control Register' */ ++/* Bit: 'BAS' */ ++/* Description: 'Busy/Access Start' */ ++#define TANTOS_3G_RCC_BAS_OFFSET 0x11B ++#define TANTOS_3G_RCC_BAS_SHIFT 11 ++#define TANTOS_3G_RCC_BAS_SIZE 1 ++/* Bit: 'CAC' */ ++/* Description: 'Command for access counter' */ ++#define TANTOS_3G_RCC_CAC_OFFSET 0x11B ++#define TANTOS_3G_RCC_CAC_SHIFT 9 ++#define TANTOS_3G_RCC_CAC_SIZE 2 ++/* Bit: 'PORTC' */ ++/* Description: 'Port' */ ++#define TANTOS_3G_RCC_PORTC_OFFSET 0x11B ++#define TANTOS_3G_RCC_PORTC_SHIFT 6 ++#define TANTOS_3G_RCC_PORTC_SIZE 3 ++/* Bit: 'OFFSET' */ ++/* Description: 'Counter Offset' */ ++#define TANTOS_3G_RCC_OFFSET_OFFSET 0x11B ++#define TANTOS_3G_RCC_OFFSET_SHIFT 0 ++#define TANTOS_3G_RCC_OFFSET_SIZE 6 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'RMON Counter Status Low Register' */ ++/* Bit: 'COUNTER' */ ++/* Description: 'Counter [15:0] or Counter[47:32] for byte count' */ ++#define TANTOS_3G_RCSL_COUNTER_OFFSET 0x11C ++#define TANTOS_3G_RCSL_COUNTER_SHIFT 0 ++#define TANTOS_3G_RCSL_COUNTER_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'RMON Counter Status High Register' */ ++/* Bit: 'COUNTER' */ ++/* Description: 'Counter [31:16] or Counter[63:48] for byte count' */ ++#define TANTOS_3G_RCSH_COUNTER_OFFSET 0x11D ++#define TANTOS_3G_RCSH_COUNTER_SHIFT 0 ++#define TANTOS_3G_RCSH_COUNTER_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MII Indirect Access Control' */ ++/* Bit: 'MBUSY' */ ++/* Description: 'Busy state' */ ++#define TANTOS_3G_MIIAC_MBUSY_OFFSET 0x120 ++#define TANTOS_3G_MIIAC_MBUSY_SHIFT 15 ++#define TANTOS_3G_MIIAC_MBUSY_SIZE 1 ++/* Bit: 'OP' */ ++/* Description: 'Operation Code' */ ++#define TANTOS_3G_MIIAC_OP_OFFSET 0x120 ++#define TANTOS_3G_MIIAC_OP_SHIFT 10 ++#define TANTOS_3G_MIIAC_OP_SIZE 2 ++/* Bit: 'PHYAD' */ ++/* Description: 'PHY Address' */ ++#define TANTOS_3G_MIIAC_PHYAD_OFFSET 0x120 ++#define TANTOS_3G_MIIAC_PHYAD_SHIFT 5 ++#define TANTOS_3G_MIIAC_PHYAD_SIZE 5 ++/* Bit: 'REGAD' */ ++/* Description: 'Register Address' */ ++#define TANTOS_3G_MIIAC_REGAD_OFFSET 0x120 ++#define TANTOS_3G_MIIAC_REGAD_SHIFT 0 ++#define TANTOS_3G_MIIAC_REGAD_SIZE 5 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MII Indirect Write Data' */ ++/* Bit: 'WD' */ ++/* Description: 'The Write Data to the MII register' */ ++#define TANTOS_3G_MIIWD_WD_OFFSET 0x121 ++#define TANTOS_3G_MIIWD_WD_SHIFT 0 ++#define TANTOS_3G_MIIWD_WD_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MII Indirect Read Data' */ ++/* Bit: 'RD' */ ++/* Description: 'The Read Data' */ ++#define TANTOS_3G_MIIRD_RD_OFFSET 0x122 ++#define TANTOS_3G_MIIRD_RD_SHIFT 0 ++#define TANTOS_3G_MIIRD_RD_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++#endif /* #ifndef _TANTOS3G_H */ +diff --git a/include/switch_api/VR9_switch.h b/include/switch_api/VR9_switch.h +new file mode 100644 +index 0000000..f0dd37a +--- /dev/null ++++ b/include/switch_api/VR9_switch.h +@@ -0,0 +1,2637 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2011 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++#ifndef _VR9_SWITCH_H ++#define _VR9_SWITCH_H ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet Switch ResetControl Register' */ ++/* Bit: 'R1' */ ++/* Description: 'GSWIP Software Reset' */ ++#define VR9_ETHSW_SWRES_R1_OFFSET 0x000 ++#define VR9_ETHSW_SWRES_R1_SHIFT 1 ++#define VR9_ETHSW_SWRES_R1_SIZE 1 ++/* Bit: 'R0' */ ++/* Description: 'GSWIP Hardware Reset' */ ++#define VR9_ETHSW_SWRES_R0_OFFSET 0x000 ++#define VR9_ETHSW_SWRES_R0_SHIFT 0 ++#define VR9_ETHSW_SWRES_R0_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet Switch Clock ControlRegister ' */ ++/* Bit: 'CORACT_OVR' */ ++/* Description: 'Core Active Override' */ ++#define VR9_ETHSW_CLK_CORACT_OVR_OFFSET 0x001 ++#define VR9_ETHSW_CLK_CORACT_OVR_SHIFT 1 ++#define VR9_ETHSW_CLK_CORACT_OVR_SIZE 1 ++/* Bit: 'LNKDWN_OVR' */ ++/* Description: 'Link Down Override' */ ++#define VR9_ETHSW_CLK_LNKDWN_OVR_OFFSET 0x001 ++#define VR9_ETHSW_CLK_LNKDWN_OVR_SHIFT 0 ++#define VR9_ETHSW_CLK_LNKDWN_OVR_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet Switch SharedSegment Buffer Mode Register' */ ++/* Bit: 'ADDE' */ ++/* Description: 'Memory Address' */ ++#define VR9_ETHSW_SSB_MODE_ADDE_OFFSET 0x003 ++#define VR9_ETHSW_SSB_MODE_ADDE_SHIFT 2 ++#define VR9_ETHSW_SSB_MODE_ADDE_SIZE 4 ++/* Bit: 'MODE' */ ++/* Description: 'Memory Access Mode' */ ++#define VR9_ETHSW_SSB_MODE_MODE_OFFSET 0x003 ++#define VR9_ETHSW_SSB_MODE_MODE_SHIFT 0 ++#define VR9_ETHSW_SSB_MODE_MODE_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet Switch SharedSegment Buffer Address Register' */ ++/* Bit: 'ADDE' */ ++/* Description: 'Memory Address' */ ++#define VR9_ETHSW_SSB_ADDR_ADDE_OFFSET 0x004 ++#define VR9_ETHSW_SSB_ADDR_ADDE_SHIFT 0 ++#define VR9_ETHSW_SSB_ADDR_ADDE_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet Switch SharedSegment Buffer Data Register' */ ++/* Bit: 'DATA' */ ++/* Description: 'Data Value' */ ++#define VR9_ETHSW_SSB_DATA_DATA_OFFSET 0x005 ++#define VR9_ETHSW_SSB_DATA_DATA_SHIFT 0 ++#define VR9_ETHSW_SSB_DATA_DATA_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet Switch CapabilityRegister 0' */ ++/* Bit: 'SPEED' */ ++/* Description: 'Clock frequency' */ ++#define VR9_ETHSW_CAP_0_SPEED_OFFSET 0x006 ++#define VR9_ETHSW_CAP_0_SPEED_SHIFT 0 ++#define VR9_ETHSW_CAP_0_SPEED_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet Switch CapabilityRegister 1' */ ++/* Bit: 'GMAC' */ ++/* Description: 'MAC operation mode' */ ++#define VR9_ETHSW_CAP_1_GMAC_OFFSET 0x007 ++#define VR9_ETHSW_CAP_1_GMAC_SHIFT 15 ++#define VR9_ETHSW_CAP_1_GMAC_SIZE 1 ++/* Bit: 'QUEUE' */ ++/* Description: 'Number of queues' */ ++#define VR9_ETHSW_CAP_1_QUEUE_OFFSET 0x007 ++#define VR9_ETHSW_CAP_1_QUEUE_SHIFT 8 ++#define VR9_ETHSW_CAP_1_QUEUE_SIZE 7 ++/* Bit: 'VPORTS' */ ++/* Description: 'Number of virtual ports' */ ++#define VR9_ETHSW_CAP_1_VPORTS_OFFSET 0x007 ++#define VR9_ETHSW_CAP_1_VPORTS_SHIFT 4 ++#define VR9_ETHSW_CAP_1_VPORTS_SIZE 4 ++/* Bit: 'PPORTS' */ ++/* Description: 'Number of physical ports' */ ++#define VR9_ETHSW_CAP_1_PPORTS_OFFSET 0x007 ++#define VR9_ETHSW_CAP_1_PPORTS_SHIFT 0 ++#define VR9_ETHSW_CAP_1_PPORTS_SIZE 4 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet Switch CapabilityRegister 2' */ ++/* Bit: 'PACKETS' */ ++/* Description: 'Number of packets' */ ++#define VR9_ETHSW_CAP_2_PACKETS_OFFSET 0x008 ++#define VR9_ETHSW_CAP_2_PACKETS_SHIFT 0 ++#define VR9_ETHSW_CAP_2_PACKETS_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet Switch CapabilityRegister 3' */ ++/* Bit: 'METERS' */ ++/* Description: 'Number of traffic meters' */ ++#define VR9_ETHSW_CAP_3_METERS_OFFSET 0x009 ++#define VR9_ETHSW_CAP_3_METERS_SHIFT 8 ++#define VR9_ETHSW_CAP_3_METERS_SIZE 8 ++/* Bit: 'SHAPERS' */ ++/* Description: 'Number of traffic shapers' */ ++#define VR9_ETHSW_CAP_3_SHAPERS_OFFSET 0x009 ++#define VR9_ETHSW_CAP_3_SHAPERS_SHIFT 0 ++#define VR9_ETHSW_CAP_3_SHAPERS_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet Switch CapabilityRegister 4' */ ++/* Bit: 'PPPOE' */ ++/* Description: 'PPPoE table size' */ ++#define VR9_ETHSW_CAP_4_PPPOE_OFFSET 0x00A ++#define VR9_ETHSW_CAP_4_PPPOE_SHIFT 8 ++#define VR9_ETHSW_CAP_4_PPPOE_SIZE 8 ++/* Bit: 'VLAN' */ ++/* Description: 'Active VLAN table size' */ ++#define VR9_ETHSW_CAP_4_VLAN_OFFSET 0x00A ++#define VR9_ETHSW_CAP_4_VLAN_SHIFT 0 ++#define VR9_ETHSW_CAP_4_VLAN_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet Switch CapabilityRegister 5' */ ++/* Bit: 'IPPLEN' */ ++/* Description: 'IP packet length table size' */ ++#define VR9_ETHSW_CAP_5_IPPLEN_OFFSET 0x00B ++#define VR9_ETHSW_CAP_5_IPPLEN_SHIFT 8 ++#define VR9_ETHSW_CAP_5_IPPLEN_SIZE 8 ++/* Bit: 'PROT' */ ++/* Description: 'Protocol table size' */ ++#define VR9_ETHSW_CAP_5_PROT_OFFSET 0x00B ++#define VR9_ETHSW_CAP_5_PROT_SHIFT 0 ++#define VR9_ETHSW_CAP_5_PROT_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet Switch CapabilityRegister 6' */ ++/* Bit: 'MACDASA' */ ++/* Description: 'MAC DA/SA table size' */ ++#define VR9_ETHSW_CAP_6_MACDASA_OFFSET 0x00C ++#define VR9_ETHSW_CAP_6_MACDASA_SHIFT 8 ++#define VR9_ETHSW_CAP_6_MACDASA_SIZE 8 ++/* Bit: 'APPL' */ ++/* Description: 'Application table size' */ ++#define VR9_ETHSW_CAP_6_APPL_OFFSET 0x00C ++#define VR9_ETHSW_CAP_6_APPL_SHIFT 0 ++#define VR9_ETHSW_CAP_6_APPL_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet Switch CapabilityRegister 7' */ ++/* Bit: 'IPDASAM' */ ++/* Description: 'IP DA/SA MSB table size' */ ++#define VR9_ETHSW_CAP_7_IPDASAM_OFFSET 0x00D ++#define VR9_ETHSW_CAP_7_IPDASAM_SHIFT 8 ++#define VR9_ETHSW_CAP_7_IPDASAM_SIZE 8 ++/* Bit: 'IPDASAL' */ ++/* Description: 'IP DA/SA LSB table size' */ ++#define VR9_ETHSW_CAP_7_IPDASAL_OFFSET 0x00D ++#define VR9_ETHSW_CAP_7_IPDASAL_SHIFT 0 ++#define VR9_ETHSW_CAP_7_IPDASAL_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet Switch CapabilityRegister 8' */ ++/* Bit: 'MCAST' */ ++/* Description: 'Multicast table size' */ ++#define VR9_ETHSW_CAP_8_MCAST_OFFSET 0x00E ++#define VR9_ETHSW_CAP_8_MCAST_SHIFT 0 ++#define VR9_ETHSW_CAP_8_MCAST_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet Switch CapabilityRegister 9' */ ++/* Bit: 'FLAGG' */ ++/* Description: 'Flow Aggregation table size' */ ++#define VR9_ETHSW_CAP_9_FLAGG_OFFSET 0x00F ++#define VR9_ETHSW_CAP_9_FLAGG_SHIFT 0 ++#define VR9_ETHSW_CAP_9_FLAGG_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet Switch CapabilityRegister 10' */ ++/* Bit: 'MACBT' */ ++/* Description: 'MAC bridging table size' */ ++#define VR9_ETHSW_CAP_10_MACBT_OFFSET 0x010 ++#define VR9_ETHSW_CAP_10_MACBT_SHIFT 0 ++#define VR9_ETHSW_CAP_10_MACBT_SIZE 13 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet Switch CapabilityRegister 11' */ ++/* Bit: 'BSIZEL' */ ++/* Description: 'Packet buffer size (lower part, in byte)' */ ++#define VR9_ETHSW_CAP_11_BSIZEL_OFFSET 0x011 ++#define VR9_ETHSW_CAP_11_BSIZEL_SHIFT 0 ++#define VR9_ETHSW_CAP_11_BSIZEL_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet Switch CapabilityRegister 12' */ ++/* Bit: 'BSIZEH' */ ++/* Description: 'Packet buffer size (higher part, in byte)' */ ++#define VR9_ETHSW_CAP_12_BSIZEH_OFFSET 0x012 ++#define VR9_ETHSW_CAP_12_BSIZEH_SHIFT 0 ++#define VR9_ETHSW_CAP_12_BSIZEH_SIZE 3 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet Switch VersionRegister' */ ++/* Bit: 'MOD_ID' */ ++/* Description: 'Module Identification' */ ++#define VR9_ETHSW_VERSION_MOD_ID_OFFSET 0x013 ++#define VR9_ETHSW_VERSION_MOD_ID_SHIFT 8 ++#define VR9_ETHSW_VERSION_MOD_ID_SIZE 8 ++/* Bit: 'REV_ID' */ ++/* Description: 'Hardware Revision Identification' */ ++#define VR9_ETHSW_VERSION_REV_ID_OFFSET 0x013 ++#define VR9_ETHSW_VERSION_REV_ID_SHIFT 0 ++#define VR9_ETHSW_VERSION_REV_ID_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Interrupt Enable Register' */ ++/* Bit: 'FDMAIE' */ ++/* Description: 'Fetch DMA Interrupt Enable' */ ++#define VR9_ETHSW_IER_FDMAIE_OFFSET 0x014 ++#define VR9_ETHSW_IER_FDMAIE_SHIFT 4 ++#define VR9_ETHSW_IER_FDMAIE_SIZE 1 ++/* Bit: 'SDMAIE' */ ++/* Description: 'Store DMA Interrupt Enable' */ ++#define VR9_ETHSW_IER_SDMAIE_OFFSET 0x014 ++#define VR9_ETHSW_IER_SDMAIE_SHIFT 3 ++#define VR9_ETHSW_IER_SDMAIE_SIZE 1 ++/* Bit: 'MACIE' */ ++/* Description: 'Ethernet MAC Interrupt Enable' */ ++#define VR9_ETHSW_IER_MACIE_OFFSET 0x014 ++#define VR9_ETHSW_IER_MACIE_SHIFT 2 ++#define VR9_ETHSW_IER_MACIE_SIZE 1 ++/* Bit: 'PCEIE' */ ++/* Description: 'Parser and Classification Engine Interrupt Enable' */ ++#define VR9_ETHSW_IER_PCEIE_OFFSET 0x014 ++#define VR9_ETHSW_IER_PCEIE_SHIFT 1 ++#define VR9_ETHSW_IER_PCEIE_SIZE 1 ++/* Bit: 'BMIE' */ ++/* Description: 'Buffer Manager Interrupt Enable' */ ++#define VR9_ETHSW_IER_BMIE_OFFSET 0x014 ++#define VR9_ETHSW_IER_BMIE_SHIFT 0 ++#define VR9_ETHSW_IER_BMIE_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Interrupt Status Register' */ ++/* Bit: 'FDMAINT' */ ++/* Description: 'Fetch DMA Interrupt' */ ++#define VR9_ETHSW_ISR_FDMAINT_OFFSET 0x015 ++#define VR9_ETHSW_ISR_FDMAINT_SHIFT 4 ++#define VR9_ETHSW_ISR_FDMAINT_SIZE 1 ++/* Bit: 'SDMAINT' */ ++/* Description: 'Store DMA Interrupt' */ ++#define VR9_ETHSW_ISR_SDMAINT_OFFSET 0x015 ++#define VR9_ETHSW_ISR_SDMAINT_SHIFT 3 ++#define VR9_ETHSW_ISR_SDMAINT_SIZE 1 ++/* Bit: 'MACINT' */ ++/* Description: 'Ethernet MAC Interrupt' */ ++#define VR9_ETHSW_ISR_MACINT_OFFSET 0x015 ++#define VR9_ETHSW_ISR_MACINT_SHIFT 2 ++#define VR9_ETHSW_ISR_MACINT_SIZE 1 ++/* Bit: 'PCEINT' */ ++/* Description: 'Parser and Classification Engine Interrupt' */ ++#define VR9_ETHSW_ISR_PCEINT_OFFSET 0x015 ++#define VR9_ETHSW_ISR_PCEINT_SHIFT 1 ++#define VR9_ETHSW_ISR_PCEINT_SIZE 1 ++/* Bit: 'BMINT' */ ++/* Description: 'Buffer Manager Interrupt' */ ++#define VR9_ETHSW_ISR_BMINT_OFFSET 0x015 ++#define VR9_ETHSW_ISR_BMINT_SHIFT 0 ++#define VR9_ETHSW_ISR_BMINT_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'RAM Value Register 3' */ ++/* Bit: 'VAL3' */ ++/* Description: 'Data value [15:0]' */ ++#define VR9_BM_RAM_VAL_3_VAL3_OFFSET 0x040 ++#define VR9_BM_RAM_VAL_3_VAL3_SHIFT 0 ++#define VR9_BM_RAM_VAL_3_VAL3_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'RAM Value Register 2' */ ++/* Bit: 'VAL2' */ ++/* Description: 'Data value [15:0]' */ ++#define VR9_BM_RAM_VAL_2_VAL2_OFFSET 0x041 ++#define VR9_BM_RAM_VAL_2_VAL2_SHIFT 0 ++#define VR9_BM_RAM_VAL_2_VAL2_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'RAM Value Register 1' */ ++/* Bit: 'VAL1' */ ++/* Description: 'Data value [15:0]' */ ++#define VR9_BM_RAM_VAL_1_VAL1_OFFSET 0x042 ++#define VR9_BM_RAM_VAL_1_VAL1_SHIFT 0 ++#define VR9_BM_RAM_VAL_1_VAL1_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'RAM Value Register 0' */ ++/* Bit: 'VAL0' */ ++/* Description: 'Data value [15:0]' */ ++#define VR9_BM_RAM_VAL_0_VAL0_OFFSET 0x043 ++#define VR9_BM_RAM_VAL_0_VAL0_SHIFT 0 ++#define VR9_BM_RAM_VAL_0_VAL0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'RAM Address Register' */ ++/* Bit: 'ADDR' */ ++/* Description: 'RAM Address' */ ++#define VR9_BM_RAM_ADDR_ADDR_OFFSET 0x044 ++#define VR9_BM_RAM_ADDR_ADDR_SHIFT 0 ++#define VR9_BM_RAM_ADDR_ADDR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'RAM Access Control Register' */ ++/* Bit: 'BAS' */ ++/* Description: 'Access Busy/Access Start' */ ++#define VR9_BM_RAM_CTRL_BAS_OFFSET 0x045 ++#define VR9_BM_RAM_CTRL_BAS_SHIFT 15 ++#define VR9_BM_RAM_CTRL_BAS_SIZE 1 ++/* Bit: 'OPMOD' */ ++/* Description: 'Lookup Table Access Operation Mode' */ ++#define VR9_BM_RAM_CTRL_OPMOD_OFFSET 0x045 ++#define VR9_BM_RAM_CTRL_OPMOD_SHIFT 5 ++#define VR9_BM_RAM_CTRL_OPMOD_SIZE 1 ++/* Bit: 'ADDR' */ ++/* Description: 'Address for RAM selection' */ ++#define VR9_BM_RAM_CTRL_ADDR_OFFSET 0x045 ++#define VR9_BM_RAM_CTRL_ADDR_SHIFT 0 ++#define VR9_BM_RAM_CTRL_ADDR_SIZE 5 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Free Segment Queue ManagerGlobal Control Register' */ ++/* Bit: 'SEGNUM' */ ++/* Description: 'Maximum Segment Number' */ ++#define VR9_BM_FSQM_GCTRL_SEGNUM_OFFSET 0x046 ++#define VR9_BM_FSQM_GCTRL_SEGNUM_SHIFT 0 ++#define VR9_BM_FSQM_GCTRL_SEGNUM_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Number of Consumed SegmentsRegister' */ ++/* Bit: 'FSEG' */ ++/* Description: 'Number of Consumed Segments' */ ++#define VR9_BM_CONS_SEG_FSEG_OFFSET 0x047 ++#define VR9_BM_CONS_SEG_FSEG_SHIFT 0 ++#define VR9_BM_CONS_SEG_FSEG_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Number of Consumed PacketPointers Register' */ ++/* Bit: 'FQP' */ ++/* Description: 'Number of Consumed Packet Pointers' */ ++#define VR9_BM_CONS_PKT_FQP_OFFSET 0x048 ++#define VR9_BM_CONS_PKT_FQP_SHIFT 0 ++#define VR9_BM_CONS_PKT_FQP_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Buffer Manager Global ControlRegister 0' */ ++/* Bit: 'BM_STA' */ ++/* Description: 'Buffer Manager Initialization Status Bit' */ ++#define VR9_BM_GCTRL_BM_STA_OFFSET 0x049 ++#define VR9_BM_GCTRL_BM_STA_SHIFT 13 ++#define VR9_BM_GCTRL_BM_STA_SIZE 1 ++/* Bit: 'SAT' */ ++/* Description: 'RMON Counter Update Mode' */ ++#define VR9_BM_GCTRL_SAT_OFFSET 0x049 ++#define VR9_BM_GCTRL_SAT_SHIFT 12 ++#define VR9_BM_GCTRL_SAT_SIZE 1 ++/* Bit: 'FR_RBC' */ ++/* Description: 'Freeze RMON RX Bad Byte 64 Bit Counter' */ ++#define VR9_BM_GCTRL_FR_RBC_OFFSET 0x049 ++#define VR9_BM_GCTRL_FR_RBC_SHIFT 11 ++#define VR9_BM_GCTRL_FR_RBC_SIZE 1 ++/* Bit: 'FR_RGC' */ ++/* Description: 'Freeze RMON RX Good Byte 64 Bit Counter' */ ++#define VR9_BM_GCTRL_FR_RGC_OFFSET 0x049 ++#define VR9_BM_GCTRL_FR_RGC_SHIFT 10 ++#define VR9_BM_GCTRL_FR_RGC_SIZE 1 ++/* Bit: 'FR_TGC' */ ++/* Description: 'Freeze RMON TX Good Byte 64 Bit Counter' */ ++#define VR9_BM_GCTRL_FR_TGC_OFFSET 0x049 ++#define VR9_BM_GCTRL_FR_TGC_SHIFT 9 ++#define VR9_BM_GCTRL_FR_TGC_SIZE 1 ++/* Bit: 'I_FIN' */ ++/* Description: 'RAM initialization finished' */ ++#define VR9_BM_GCTRL_I_FIN_OFFSET 0x049 ++#define VR9_BM_GCTRL_I_FIN_SHIFT 8 ++#define VR9_BM_GCTRL_I_FIN_SIZE 1 ++/* Bit: 'CX_INI' */ ++/* Description: 'PQM Context RAM initialization' */ ++#define VR9_BM_GCTRL_CX_INI_OFFSET 0x049 ++#define VR9_BM_GCTRL_CX_INI_SHIFT 7 ++#define VR9_BM_GCTRL_CX_INI_SIZE 1 ++/* Bit: 'FP_INI' */ ++/* Description: 'FPQM RAM initialization' */ ++#define VR9_BM_GCTRL_FP_INI_OFFSET 0x049 ++#define VR9_BM_GCTRL_FP_INI_SHIFT 6 ++#define VR9_BM_GCTRL_FP_INI_SIZE 1 ++/* Bit: 'FS_INI' */ ++/* Description: 'FSQM RAM initialization' */ ++#define VR9_BM_GCTRL_FS_INI_OFFSET 0x049 ++#define VR9_BM_GCTRL_FS_INI_SHIFT 5 ++#define VR9_BM_GCTRL_FS_INI_SIZE 1 ++/* Bit: 'R_SRES' */ ++/* Description: 'Software Reset for RMON' */ ++#define VR9_BM_GCTRL_R_SRES_OFFSET 0x049 ++#define VR9_BM_GCTRL_R_SRES_SHIFT 4 ++#define VR9_BM_GCTRL_R_SRES_SIZE 1 ++/* Bit: 'S_SRES' */ ++/* Description: 'Software Reset for Scheduler' */ ++#define VR9_BM_GCTRL_S_SRES_OFFSET 0x049 ++#define VR9_BM_GCTRL_S_SRES_SHIFT 3 ++#define VR9_BM_GCTRL_S_SRES_SIZE 1 ++/* Bit: 'A_SRES' */ ++/* Description: 'Software Reset for AVG' */ ++#define VR9_BM_GCTRL_A_SRES_OFFSET 0x049 ++#define VR9_BM_GCTRL_A_SRES_SHIFT 2 ++#define VR9_BM_GCTRL_A_SRES_SIZE 1 ++/* Bit: 'P_SRES' */ ++/* Description: 'Software Reset for PQM' */ ++#define VR9_BM_GCTRL_P_SRES_OFFSET 0x049 ++#define VR9_BM_GCTRL_P_SRES_SHIFT 1 ++#define VR9_BM_GCTRL_P_SRES_SIZE 1 ++/* Bit: 'F_SRES' */ ++/* Description: 'Software Reset for FSQM' */ ++#define VR9_BM_GCTRL_F_SRES_OFFSET 0x049 ++#define VR9_BM_GCTRL_F_SRES_SHIFT 0 ++#define VR9_BM_GCTRL_F_SRES_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Queue Manager GlobalControl Register 0' */ ++/* Bit: 'GL_MOD' */ ++/* Description: 'WRED Mode Signal' */ ++#define VR9_BM_QUEUE_GCTRL_GL_MOD_OFFSET 0x04A ++#define VR9_BM_QUEUE_GCTRL_GL_MOD_SHIFT 10 ++#define VR9_BM_QUEUE_GCTRL_GL_MOD_SIZE 1 ++/* Bit: 'AQUI' */ ++/* Description: 'Average Queue Update Interval' */ ++#define VR9_BM_QUEUE_GCTRL_AQUI_OFFSET 0x04A ++#define VR9_BM_QUEUE_GCTRL_AQUI_SHIFT 7 ++#define VR9_BM_QUEUE_GCTRL_AQUI_SIZE 3 ++/* Bit: 'AQWF' */ ++/* Description: 'Average Queue Weight Factor' */ ++#define VR9_BM_QUEUE_GCTRL_AQWF_OFFSET 0x04A ++#define VR9_BM_QUEUE_GCTRL_AQWF_SHIFT 3 ++#define VR9_BM_QUEUE_GCTRL_AQWF_SIZE 4 ++/* Bit: 'QAVGEN' */ ++/* Description: 'Queue Average Calculation Enable' */ ++#define VR9_BM_QUEUE_GCTRL_QAVGEN_OFFSET 0x04A ++#define VR9_BM_QUEUE_GCTRL_QAVGEN_SHIFT 2 ++#define VR9_BM_QUEUE_GCTRL_QAVGEN_SIZE 1 ++/* Bit: 'DPROB' */ ++/* Description: 'Drop Probability Profile' */ ++#define VR9_BM_QUEUE_GCTRL_DPROB_OFFSET 0x04A ++#define VR9_BM_QUEUE_GCTRL_DPROB_SHIFT 0 ++#define VR9_BM_QUEUE_GCTRL_DPROB_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'WRED Red Threshold Register0' */ ++/* Bit: 'MINTH' */ ++/* Description: 'Minimum Threshold' */ ++#define VR9_BM_WRED_RTH_0_MINTH_OFFSET 0x04B ++#define VR9_BM_WRED_RTH_0_MINTH_SHIFT 0 ++#define VR9_BM_WRED_RTH_0_MINTH_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'WRED Red Threshold Register1' */ ++/* Bit: 'MAXTH' */ ++/* Description: 'Maximum Threshold' */ ++#define VR9_BM_WRED_RTH_1_MAXTH_OFFSET 0x04C ++#define VR9_BM_WRED_RTH_1_MAXTH_SHIFT 0 ++#define VR9_BM_WRED_RTH_1_MAXTH_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'WRED Yellow ThresholdRegister 0' */ ++/* Bit: 'MINTH' */ ++/* Description: 'Minimum Threshold' */ ++#define VR9_BM_WRED_YTH_0_MINTH_OFFSET 0x04D ++#define VR9_BM_WRED_YTH_0_MINTH_SHIFT 0 ++#define VR9_BM_WRED_YTH_0_MINTH_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'WRED Yellow ThresholdRegister 1' */ ++/* Bit: 'MAXTH' */ ++/* Description: 'Maximum Threshold' */ ++#define VR9_BM_WRED_YTH_1_MAXTH_OFFSET 0x04E ++#define VR9_BM_WRED_YTH_1_MAXTH_SHIFT 0 ++#define VR9_BM_WRED_YTH_1_MAXTH_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'WRED Green ThresholdRegister 0' */ ++/* Bit: 'MINTH' */ ++/* Description: 'Minimum Threshold' */ ++#define VR9_BM_WRED_GTH_0_MINTH_OFFSET 0x04F ++#define VR9_BM_WRED_GTH_0_MINTH_SHIFT 0 ++#define VR9_BM_WRED_GTH_0_MINTH_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'WRED Green ThresholdRegister 1' */ ++/* Bit: 'MAXTH' */ ++/* Description: 'Maximum Threshold' */ ++#define VR9_BM_WRED_GTH_1_MAXTH_OFFSET 0x050 ++#define VR9_BM_WRED_GTH_1_MAXTH_SHIFT 0 ++#define VR9_BM_WRED_GTH_1_MAXTH_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Drop Threshold ConfigurationRegister 0' */ ++/* Bit: 'THR_FQ' */ ++/* Description: 'Threshold for frames marked red' */ ++#define VR9_BM_DROP_GTH_0_THR_FQ_OFFSET 0x051 ++#define VR9_BM_DROP_GTH_0_THR_FQ_SHIFT 0 ++#define VR9_BM_DROP_GTH_0_THR_FQ_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Drop Threshold ConfigurationRegister 1' */ ++/* Bit: 'THY_FQ' */ ++/* Description: 'Threshold for frames marked yellow' */ ++#define VR9_BM_DROP_GTH_1_THY_FQ_OFFSET 0x052 ++#define VR9_BM_DROP_GTH_1_THY_FQ_SHIFT 0 ++#define VR9_BM_DROP_GTH_1_THY_FQ_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Drop Threshold ConfigurationRegister 2' */ ++/* Bit: 'THG_FQ' */ ++/* Description: 'Threshold for frames marked green' */ ++#define VR9_BM_DROP_GTH_2_THG_FQ_OFFSET 0x053 ++#define VR9_BM_DROP_GTH_2_THG_FQ_SHIFT 0 ++#define VR9_BM_DROP_GTH_2_THG_FQ_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Buffer Manager Global InterruptEnable Register' */ ++/* Bit: 'CNT4' */ ++/* Description: 'Counter Group 4 (RMON-CLASSIFICATION) Interrupt ++Enable' */ ++#define VR9_BM_IER_CNT4_OFFSET 0x054 ++#define VR9_BM_IER_CNT4_SHIFT 7 ++#define VR9_BM_IER_CNT4_SIZE 1 ++/* Bit: 'CNT3' */ ++/* Description: 'Counter Group 3 (RMON-PQM) Interrupt Enable' */ ++#define VR9_BM_IER_CNT3_OFFSET 0x054 ++#define VR9_BM_IER_CNT3_SHIFT 6 ++#define VR9_BM_IER_CNT3_SIZE 1 ++/* Bit: 'CNT2' */ ++/* Description: 'Counter Group 2 (RMON-SCHEDULER) Interrupt Enable' */ ++#define VR9_BM_IER_CNT2_OFFSET 0x054 ++#define VR9_BM_IER_CNT2_SHIFT 5 ++#define VR9_BM_IER_CNT2_SIZE 1 ++/* Bit: 'CNT1' */ ++/* Description: 'Counter Group 1 (RMON-QFETCH) Interrupt Enable' */ ++#define VR9_BM_IER_CNT1_OFFSET 0x054 ++#define VR9_BM_IER_CNT1_SHIFT 4 ++#define VR9_BM_IER_CNT1_SIZE 1 ++/* Bit: 'CNT0' */ ++/* Description: 'Counter Group 0 (RMON-QSTOR) Interrupt Enable' */ ++#define VR9_BM_IER_CNT0_OFFSET 0x054 ++#define VR9_BM_IER_CNT0_SHIFT 3 ++#define VR9_BM_IER_CNT0_SIZE 1 ++/* Bit: 'DEQ' */ ++/* Description: 'PQM dequeue Interrupt Enable' */ ++#define VR9_BM_IER_DEQ_OFFSET 0x054 ++#define VR9_BM_IER_DEQ_SHIFT 2 ++#define VR9_BM_IER_DEQ_SIZE 1 ++/* Bit: 'ENQ' */ ++/* Description: 'PQM Enqueue Interrupt Enable' */ ++#define VR9_BM_IER_ENQ_OFFSET 0x054 ++#define VR9_BM_IER_ENQ_SHIFT 1 ++#define VR9_BM_IER_ENQ_SIZE 1 ++/* Bit: 'FSQM' */ ++/* Description: 'Buffer Empty Interrupt Enable' */ ++#define VR9_BM_IER_FSQM_OFFSET 0x054 ++#define VR9_BM_IER_FSQM_SHIFT 0 ++#define VR9_BM_IER_FSQM_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Buffer Manager Global InterruptStatus Register' */ ++/* Bit: 'CNT4' */ ++/* Description: 'Counter Group 4 Interrupt' */ ++#define VR9_BM_ISR_CNT4_OFFSET 0x055 ++#define VR9_BM_ISR_CNT4_SHIFT 7 ++#define VR9_BM_ISR_CNT4_SIZE 1 ++/* Bit: 'CNT3' */ ++/* Description: 'Counter Group 3 Interrupt' */ ++#define VR9_BM_ISR_CNT3_OFFSET 0x055 ++#define VR9_BM_ISR_CNT3_SHIFT 6 ++#define VR9_BM_ISR_CNT3_SIZE 1 ++/* Bit: 'CNT2' */ ++/* Description: 'Counter Group 2 Interrupt' */ ++#define VR9_BM_ISR_CNT2_OFFSET 0x055 ++#define VR9_BM_ISR_CNT2_SHIFT 5 ++#define VR9_BM_ISR_CNT2_SIZE 1 ++/* Bit: 'CNT1' */ ++/* Description: 'Counter Group 1 Interrupt' */ ++#define VR9_BM_ISR_CNT1_OFFSET 0x055 ++#define VR9_BM_ISR_CNT1_SHIFT 4 ++#define VR9_BM_ISR_CNT1_SIZE 1 ++/* Bit: 'CNT0' */ ++/* Description: 'Counter Group 0 Interrupt' */ ++#define VR9_BM_ISR_CNT0_OFFSET 0x055 ++#define VR9_BM_ISR_CNT0_SHIFT 3 ++#define VR9_BM_ISR_CNT0_SIZE 1 ++/* Bit: 'DEQ' */ ++/* Description: 'PQM dequeue Interrupt Enable' */ ++#define VR9_BM_ISR_DEQ_OFFSET 0x055 ++#define VR9_BM_ISR_DEQ_SHIFT 2 ++#define VR9_BM_ISR_DEQ_SIZE 1 ++/* Bit: 'ENQ' */ ++/* Description: 'PQM Enqueue Interrupt' */ ++#define VR9_BM_ISR_ENQ_OFFSET 0x055 ++#define VR9_BM_ISR_ENQ_SHIFT 1 ++#define VR9_BM_ISR_ENQ_SIZE 1 ++/* Bit: 'FSQM' */ ++/* Description: 'Buffer Empty Interrupt' */ ++#define VR9_BM_ISR_FSQM_OFFSET 0x055 ++#define VR9_BM_ISR_FSQM_SHIFT 0 ++#define VR9_BM_ISR_FSQM_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Buffer Manager RMON CounterInterrupt Select Register' */ ++/* Bit: 'PORT' */ ++/* Description: 'Port Number' */ ++#define VR9_BM_CISEL_PORT_OFFSET 0x056 ++#define VR9_BM_CISEL_PORT_SHIFT 0 ++#define VR9_BM_CISEL_PORT_SIZE 4 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Debug Control Register' */ ++/* Bit: 'DBG_SEL' */ ++/* Description: 'Select Signal for Debug Multiplexer' */ ++#define VR9_BM_DEBUG_CTRL_DBG_SEL_OFFSET 0x057 ++#define VR9_BM_DEBUG_CTRL_DBG_SEL_SHIFT 0 ++#define VR9_BM_DEBUG_CTRL_DBG_SEL_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Debug Value Register' */ ++/* Bit: 'DBG_DAT' */ ++/* Description: 'Debug Data Value' */ ++#define VR9_BM_DEBUG_VAL_DBG_DAT_OFFSET 0x058 ++#define VR9_BM_DEBUG_VAL_DBG_DAT_SHIFT 0 ++#define VR9_BM_DEBUG_VAL_DBG_DAT_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Buffer Manager PortConfiguration Register' */ ++/* Bit: 'IGCNT' */ ++/* Description: 'Ingress Special Tag RMON count' */ ++#define VR9_BM_PCFG_IGCNT_OFFSET 0x080 ++#define VR9_BM_PCFG_IGCNT_SHIFT 1 ++#define VR9_BM_PCFG_IGCNT_SIZE 1 ++/* Bit: 'CNTEN' */ ++/* Description: 'RMON Counter Enable' */ ++#define VR9_BM_PCFG_CNTEN_OFFSET 0x080 ++#define VR9_BM_PCFG_CNTEN_SHIFT 0 ++#define VR9_BM_PCFG_CNTEN_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Buffer ManagerRMON Control Register' */ ++/* Bit: 'RAM2_RES' */ ++/* Description: 'Software Reset for RMON RAM2' */ ++#define VR9_BM_RMON_CTRL_RAM2_RES_OFFSET 0x081 ++#define VR9_BM_RMON_CTRL_RAM2_RES_SHIFT 1 ++#define VR9_BM_RMON_CTRL_RAM2_RES_SIZE 1 ++/* Bit: 'RAM1_RES' */ ++/* Description: 'Software Reset for RMON RAM1' */ ++#define VR9_BM_RMON_CTRL_RAM1_RES_OFFSET 0x081 ++#define VR9_BM_RMON_CTRL_RAM1_RES_SHIFT 0 ++#define VR9_BM_RMON_CTRL_RAM1_RES_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Packet Queue ManagerRate Shaper Assignment Register' */ ++/* Bit: 'EN2' */ ++/* Description: 'Rate Shaper 2 Enable' */ ++#define VR9_PQM_RS_EN2_OFFSET 0x101 ++#define VR9_PQM_RS_EN2_SHIFT 15 ++#define VR9_PQM_RS_EN2_SIZE 1 ++/* Bit: 'RS2' */ ++/* Description: 'Rate Shaper 2' */ ++#define VR9_PQM_RS_RS2_OFFSET 0x101 ++#define VR9_PQM_RS_RS2_SHIFT 8 ++#define VR9_PQM_RS_RS2_SIZE 4 ++/* Bit: 'EN1' */ ++/* Description: 'Rate Shaper 1 Enable' */ ++#define VR9_PQM_RS_EN1_OFFSET 0x101 ++#define VR9_PQM_RS_EN1_SHIFT 7 ++#define VR9_PQM_RS_EN1_SIZE 1 ++/* Bit: 'RS1' */ ++/* Description: 'Rate Shaper 1' */ ++#define VR9_PQM_RS_RS1_OFFSET 0x101 ++#define VR9_PQM_RS_RS1_SHIFT 0 ++#define VR9_PQM_RS_RS1_SIZE 4 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Rate Shaper ControlRegister' */ ++/* Bit: 'RSEN' */ ++/* Description: 'Rate Shaper Enable' */ ++#define VR9_RS_CTRL_RSEN_OFFSET 0x140 ++#define VR9_RS_CTRL_RSEN_SHIFT 0 ++#define VR9_RS_CTRL_RSEN_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Rate Shaper CommittedBurst Size Register' */ ++/* Bit: 'CBS' */ ++/* Description: 'Committed Burst Size' */ ++#define VR9_RS_CBS_CBS_OFFSET 0x141 ++#define VR9_RS_CBS_CBS_SHIFT 0 ++#define VR9_RS_CBS_CBS_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Rate Shaper InstantaneousBurst Size Register' */ ++/* Bit: 'IBS' */ ++/* Description: 'Instantaneous Burst Size' */ ++#define VR9_RS_IBS_IBS_OFFSET 0x142 ++#define VR9_RS_IBS_IBS_SHIFT 0 ++#define VR9_RS_IBS_IBS_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Rate Shaper RateExponent Register' */ ++/* Bit: 'EXP' */ ++/* Description: 'Exponent' */ ++#define VR9_RS_CIR_EXP_EXP_OFFSET 0x143 ++#define VR9_RS_CIR_EXP_EXP_SHIFT 0 ++#define VR9_RS_CIR_EXP_EXP_SIZE 4 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Rate Shaper RateMantissa Register' */ ++/* Bit: 'MANT' */ ++/* Description: 'Mantissa' */ ++#define VR9_RS_CIR_MANT_MANT_OFFSET 0x144 ++#define VR9_RS_CIR_MANT_MANT_SHIFT 0 ++#define VR9_RS_CIR_MANT_MANT_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Key Data 15' */ ++/* Bit: 'KEY15' */ ++/* Description: 'Key Value[15:0]' */ ++#define VR9_PCE_TBL_KEY_15_KEY15_OFFSET 0x438 ++#define VR9_PCE_TBL_KEY_15_KEY15_SHIFT 0 ++#define VR9_PCE_TBL_KEY_15_KEY15_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Key Data 14' */ ++/* Bit: 'KEY14' */ ++/* Description: 'Key Value[15:0]' */ ++#define VR9_PCE_TBL_KEY_14_KEY14_OFFSET 0x439 ++#define VR9_PCE_TBL_KEY_14_KEY14_SHIFT 0 ++#define VR9_PCE_TBL_KEY_14_KEY14_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Key Data 13' */ ++/* Bit: 'KEY13' */ ++/* Description: 'Key Value[15:0]' */ ++#define VR9_PCE_TBL_KEY_13_KEY13_OFFSET 0x43A ++#define VR9_PCE_TBL_KEY_13_KEY13_SHIFT 0 ++#define VR9_PCE_TBL_KEY_13_KEY13_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Key Data 12' */ ++/* Bit: 'KEY12' */ ++/* Description: 'Key Value[15:0]' */ ++#define VR9_PCE_TBL_KEY_12_KEY12_OFFSET 0x43B ++#define VR9_PCE_TBL_KEY_12_KEY12_SHIFT 0 ++#define VR9_PCE_TBL_KEY_12_KEY12_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Key Data 11' */ ++/* Bit: 'KEY11' */ ++/* Description: 'Key Value[15:0]' */ ++#define VR9_PCE_TBL_KEY_11_KEY11_OFFSET 0x43C ++#define VR9_PCE_TBL_KEY_11_KEY11_SHIFT 0 ++#define VR9_PCE_TBL_KEY_11_KEY11_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Key Data 10' */ ++/* Bit: 'KEY10' */ ++/* Description: 'Key Value[15:0]' */ ++#define VR9_PCE_TBL_KEY_10_KEY10_OFFSET 0x43D ++#define VR9_PCE_TBL_KEY_10_KEY10_SHIFT 0 ++#define VR9_PCE_TBL_KEY_10_KEY10_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Key Data 9' */ ++/* Bit: 'KEY9' */ ++/* Description: 'Key Value[15:0]' */ ++#define VR9_PCE_TBL_KEY_9_KEY9_OFFSET 0x43E ++#define VR9_PCE_TBL_KEY_9_KEY9_SHIFT 0 ++#define VR9_PCE_TBL_KEY_9_KEY9_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Key Data 8' */ ++/* Bit: 'KEY8' */ ++/* Description: 'Key Value[15:0]' */ ++#define VR9_PCE_TBL_KEY_8_KEY8_OFFSET 0x43F ++#define VR9_PCE_TBL_KEY_8_KEY8_SHIFT 0 ++#define VR9_PCE_TBL_KEY_8_KEY8_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Key Data 7' */ ++/* Bit: 'KEY7' */ ++/* Description: 'Key Value[15:0]' */ ++#define VR9_PCE_TBL_KEY_7_KEY7_OFFSET 0x440 ++#define VR9_PCE_TBL_KEY_7_KEY7_SHIFT 0 ++#define VR9_PCE_TBL_KEY_7_KEY7_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Key Data 6' */ ++/* Bit: 'KEY6' */ ++/* Description: 'Key Value[15:0]' */ ++#define VR9_PCE_TBL_KEY_6_KEY6_OFFSET 0x441 ++#define VR9_PCE_TBL_KEY_6_KEY6_SHIFT 0 ++#define VR9_PCE_TBL_KEY_6_KEY6_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Key Data 5' */ ++/* Bit: 'KEY5' */ ++/* Description: 'Key Value[15:0]' */ ++#define VR9_PCE_TBL_KEY_5_KEY5_OFFSET 0x442 ++#define VR9_PCE_TBL_KEY_5_KEY5_SHIFT 0 ++#define VR9_PCE_TBL_KEY_5_KEY5_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Key Data 4' */ ++/* Bit: 'KEY4' */ ++/* Description: 'Key Value[15:0]' */ ++#define VR9_PCE_TBL_KEY_4_KEY4_OFFSET 0x443 ++#define VR9_PCE_TBL_KEY_4_KEY4_SHIFT 0 ++#define VR9_PCE_TBL_KEY_4_KEY4_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Key Data 3' */ ++/* Bit: 'KEY3' */ ++/* Description: 'Key Value[15:0]' */ ++#define VR9_PCE_TBL_KEY_3_KEY3_OFFSET 0x444 ++#define VR9_PCE_TBL_KEY_3_KEY3_SHIFT 0 ++#define VR9_PCE_TBL_KEY_3_KEY3_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Key Data 2' */ ++/* Bit: 'KEY2' */ ++/* Description: 'Key Value[15:0]' */ ++#define VR9_PCE_TBL_KEY_2_KEY2_OFFSET 0x445 ++#define VR9_PCE_TBL_KEY_2_KEY2_SHIFT 0 ++#define VR9_PCE_TBL_KEY_2_KEY2_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Key Data 1' */ ++/* Bit: 'KEY1' */ ++/* Description: 'Key Value[15:0]' */ ++#define VR9_PCE_TBL_KEY_1_KEY1_OFFSET 0x446 ++#define VR9_PCE_TBL_KEY_1_KEY1_SHIFT 0 ++#define VR9_PCE_TBL_KEY_1_KEY1_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Key Data 0' */ ++/* Bit: 'KEY0' */ ++/* Description: 'Key Value[15:0]' */ ++#define VR9_PCE_TBL_KEY_0_KEY0_OFFSET 0x447 ++#define VR9_PCE_TBL_KEY_0_KEY0_SHIFT 0 ++#define VR9_PCE_TBL_KEY_0_KEY0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Mask Write Register0' */ ++/* Bit: 'MASK0' */ ++/* Description: 'Mask Pattern [15:0]' */ ++#define VR9_PCE_TBL_MASK_0_MASK0_OFFSET 0x448 ++#define VR9_PCE_TBL_MASK_0_MASK0_SHIFT 0 ++#define VR9_PCE_TBL_MASK_0_MASK0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Value Register4' */ ++/* Bit: 'VAL4' */ ++/* Description: 'Data value [15:0]' */ ++#define VR9_PCE_TBL_VAL_4_VAL4_OFFSET 0x449 ++#define VR9_PCE_TBL_VAL_4_VAL4_SHIFT 0 ++#define VR9_PCE_TBL_VAL_4_VAL4_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Value Register3' */ ++/* Bit: 'VAL3' */ ++/* Description: 'Data value [15:0]' */ ++#define VR9_PCE_TBL_VAL_3_VAL3_OFFSET 0x44A ++#define VR9_PCE_TBL_VAL_3_VAL3_SHIFT 0 ++#define VR9_PCE_TBL_VAL_3_VAL3_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Value Register2' */ ++/* Bit: 'VAL2' */ ++/* Description: 'Data value [15:0]' */ ++#define VR9_PCE_TBL_VAL_2_VAL2_OFFSET 0x44B ++#define VR9_PCE_TBL_VAL_2_VAL2_SHIFT 0 ++#define VR9_PCE_TBL_VAL_2_VAL2_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Value Register1' */ ++/* Bit: 'VAL1' */ ++/* Description: 'Data value [15:0]' */ ++#define VR9_PCE_TBL_VAL_1_VAL1_OFFSET 0x44C ++#define VR9_PCE_TBL_VAL_1_VAL1_SHIFT 0 ++#define VR9_PCE_TBL_VAL_1_VAL1_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Value Register0' */ ++/* Bit: 'VAL0' */ ++/* Description: 'Data value [15:0]' */ ++#define VR9_PCE_TBL_VAL_0_VAL0_OFFSET 0x44D ++#define VR9_PCE_TBL_VAL_0_VAL0_SHIFT 0 ++#define VR9_PCE_TBL_VAL_0_VAL0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Entry AddressRegister' */ ++/* Bit: 'ADDR' */ ++/* Description: 'Table Address' */ ++#define VR9_PCE_TBL_ADDR_ADDR_OFFSET 0x44E ++#define VR9_PCE_TBL_ADDR_ADDR_SHIFT 0 ++#define VR9_PCE_TBL_ADDR_ADDR_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table Access ControlRegister' */ ++/* Bit: 'BAS' */ ++/* Description: 'Access Busy/Access Start' */ ++#define VR9_PCE_TBL_CTRL_BAS_OFFSET 0x44F ++#define VR9_PCE_TBL_CTRL_BAS_SHIFT 15 ++#define VR9_PCE_TBL_CTRL_BAS_SIZE 1 ++/* Bit: 'TYPE' */ ++/* Description: 'Lookup Entry Type' */ ++#define VR9_PCE_TBL_CTRL_TYPE_OFFSET 0x44F ++#define VR9_PCE_TBL_CTRL_TYPE_SHIFT 13 ++#define VR9_PCE_TBL_CTRL_TYPE_SIZE 1 ++/* Bit: 'VLD' */ ++/* Description: 'Lookup Entry Valid' */ ++#define VR9_PCE_TBL_CTRL_VLD_OFFSET 0x44F ++#define VR9_PCE_TBL_CTRL_VLD_SHIFT 12 ++#define VR9_PCE_TBL_CTRL_VLD_SIZE 1 ++/* Bit: 'KEYFORM' */ ++/* Description: 'Key Format' */ ++#define VR9_PCE_TBL_CTRL_KEYFORM_OFFSET 0x44F ++#define VR9_PCE_TBL_CTRL_KEYFORM_SHIFT 11 ++#define VR9_PCE_TBL_CTRL_KEYFORM_SIZE 1 ++/* Bit: 'GMAP' */ ++/* Description: 'Group Map' */ ++#define VR9_PCE_TBL_CTRL_GMAP_OFFSET 0x44F ++#define VR9_PCE_TBL_CTRL_GMAP_SHIFT 7 ++#define VR9_PCE_TBL_CTRL_GMAP_SIZE 4 ++/* Bit: 'OPMOD' */ ++/* Description: 'Lookup Table Access Operation Mode' */ ++#define VR9_PCE_TBL_CTRL_OPMOD_OFFSET 0x44F ++#define VR9_PCE_TBL_CTRL_OPMOD_SHIFT 5 ++#define VR9_PCE_TBL_CTRL_OPMOD_SIZE 2 ++/* Bit: 'ADDR' */ ++/* Description: 'Lookup Table Address' */ ++#define VR9_PCE_TBL_CTRL_ADDR_OFFSET 0x44F ++#define VR9_PCE_TBL_CTRL_ADDR_SHIFT 0 ++#define VR9_PCE_TBL_CTRL_ADDR_SIZE 5 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Table General StatusRegister' */ ++/* Bit: 'TBUSY' */ ++/* Description: 'Table Access Busy' */ ++#define VR9_PCE_TBL_STAT_TBUSY_OFFSET 0x450 ++#define VR9_PCE_TBL_STAT_TBUSY_SHIFT 2 ++#define VR9_PCE_TBL_STAT_TBUSY_SIZE 1 ++/* Bit: 'TEMPT' */ ++/* Description: 'Table Empty' */ ++#define VR9_PCE_TBL_STAT_TEMPT_OFFSET 0x450 ++#define VR9_PCE_TBL_STAT_TEMPT_SHIFT 1 ++#define VR9_PCE_TBL_STAT_TEMPT_SIZE 1 ++/* Bit: 'TFUL' */ ++/* Description: 'Table Full' */ ++#define VR9_PCE_TBL_STAT_TFUL_OFFSET 0x450 ++#define VR9_PCE_TBL_STAT_TFUL_SHIFT 0 ++#define VR9_PCE_TBL_STAT_TFUL_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Aging Counter ConfigurationRegister 0' */ ++/* Bit: 'EXP' */ ++/* Description: 'Aging Counter Exponent Value ' */ ++#define VR9_PCE_AGE_0_EXP_OFFSET 0x451 ++#define VR9_PCE_AGE_0_EXP_SHIFT 0 ++#define VR9_PCE_AGE_0_EXP_SIZE 4 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Aging Counter ConfigurationRegister 1' */ ++/* Bit: 'MANT' */ ++/* Description: 'Aging Counter Mantissa Value ' */ ++#define VR9_PCE_AGE_1_MANT_OFFSET 0x452 ++#define VR9_PCE_AGE_1_MANT_SHIFT 0 ++#define VR9_PCE_AGE_1_MANT_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port Map Register 1' */ ++/* Bit: 'MPMAP' */ ++/* Description: 'Monitoring Port Map' */ ++#define VR9_PCE_PMAP_1_MPMAP_OFFSET 0x453 ++#define VR9_PCE_PMAP_1_MPMAP_SHIFT 0 ++#define VR9_PCE_PMAP_1_MPMAP_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port Map Register 2' */ ++/* Bit: 'DMCPMAP' */ ++/* Description: 'Default Multicast Port Map' */ ++#define VR9_PCE_PMAP_2_DMCPMAP_OFFSET 0x454 ++#define VR9_PCE_PMAP_2_DMCPMAP_SHIFT 0 ++#define VR9_PCE_PMAP_2_DMCPMAP_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Port Map Register 3' */ ++/* Bit: 'UUCMAP' */ ++/* Description: 'Default Unknown Unicast Port Map' */ ++#define VR9_PCE_PMAP_3_UUCMAP_OFFSET 0x455 ++#define VR9_PCE_PMAP_3_UUCMAP_SHIFT 0 ++#define VR9_PCE_PMAP_3_UUCMAP_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PCE Global Control Register0' */ ++/* Bit: 'IGMP' */ ++/* Description: 'IGMP Mode Selection' */ ++#define VR9_PCE_GCTRL_0_IGMP_OFFSET 0x456 ++#define VR9_PCE_GCTRL_0_IGMP_SHIFT 15 ++#define VR9_PCE_GCTRL_0_IGMP_SIZE 1 ++/* Bit: 'VLAN' */ ++/* Description: 'VLAN-aware Switching' */ ++#define VR9_PCE_GCTRL_0_VLAN_OFFSET 0x456 ++#define VR9_PCE_GCTRL_0_VLAN_SHIFT 14 ++#define VR9_PCE_GCTRL_0_VLAN_SIZE 1 ++/* Bit: 'NOPM' */ ++/* Description: 'No Port Map Forwarding' */ ++#define VR9_PCE_GCTRL_0_NOPM_OFFSET 0x456 ++#define VR9_PCE_GCTRL_0_NOPM_SHIFT 13 ++#define VR9_PCE_GCTRL_0_NOPM_SIZE 1 ++/* Bit: 'SCONUC' */ ++/* Description: 'Unknown Unicast Storm Control' */ ++#define VR9_PCE_GCTRL_0_SCONUC_OFFSET 0x456 ++#define VR9_PCE_GCTRL_0_SCONUC_SHIFT 12 ++#define VR9_PCE_GCTRL_0_SCONUC_SIZE 1 ++/* Bit: 'SCONMC' */ ++/* Description: 'Multicast Storm Control' */ ++#define VR9_PCE_GCTRL_0_SCONMC_OFFSET 0x456 ++#define VR9_PCE_GCTRL_0_SCONMC_SHIFT 11 ++#define VR9_PCE_GCTRL_0_SCONMC_SIZE 1 ++/* Bit: 'SCONBC' */ ++/* Description: 'Broadcast Storm Control' */ ++#define VR9_PCE_GCTRL_0_SCONBC_OFFSET 0x456 ++#define VR9_PCE_GCTRL_0_SCONBC_SHIFT 10 ++#define VR9_PCE_GCTRL_0_SCONBC_SIZE 1 ++/* Bit: 'SCONMOD' */ ++/* Description: 'Storm Control Mode' */ ++#define VR9_PCE_GCTRL_0_SCONMOD_OFFSET 0x456 ++#define VR9_PCE_GCTRL_0_SCONMOD_SHIFT 8 ++#define VR9_PCE_GCTRL_0_SCONMOD_SIZE 2 ++/* Bit: 'SCONMET' */ ++/* Description: 'Storm Control Metering Instance' */ ++#define VR9_PCE_GCTRL_0_SCONMET_OFFSET 0x456 ++#define VR9_PCE_GCTRL_0_SCONMET_SHIFT 4 ++#define VR9_PCE_GCTRL_0_SCONMET_SIZE 4 ++/* Bit: 'MC_VALID' */ ++/* Description: 'Access Request' */ ++#define VR9_PCE_GCTRL_0_MC_VALID_OFFSET 0x456 ++#define VR9_PCE_GCTRL_0_MC_VALID_SHIFT 3 ++#define VR9_PCE_GCTRL_0_MC_VALID_SIZE 1 ++/* Bit: 'PLCKMOD' */ ++/* Description: 'Port Lock Mode' */ ++#define VR9_PCE_GCTRL_0_PLCKMOD_OFFSET 0x456 ++#define VR9_PCE_GCTRL_0_PLCKMOD_SHIFT 2 ++#define VR9_PCE_GCTRL_0_PLCKMOD_SIZE 1 ++/* Bit: 'PLIMMOD' */ ++/* Description: 'MAC Address Learning Limitation Mode' */ ++#define VR9_PCE_GCTRL_0_PLIMMOD_OFFSET 0x456 ++#define VR9_PCE_GCTRL_0_PLIMMOD_SHIFT 1 ++#define VR9_PCE_GCTRL_0_PLIMMOD_SIZE 1 ++/* Bit: 'MTFL' */ ++/* Description: 'MAC Table Flushing' */ ++#define VR9_PCE_GCTRL_0_MTFL_OFFSET 0x456 ++#define VR9_PCE_GCTRL_0_MTFL_SHIFT 0 ++#define VR9_PCE_GCTRL_0_MTFL_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PCE Global Control Register1' */ ++/* Bit: 'PARSER_DBG' */ ++/* Description: 'Parser Debug Selection' */ ++#define VR9_PCE_GCTRL_1_PARSER_DBG_OFFSET 0x457 ++#define VR9_PCE_GCTRL_1_PARSER_DBG_SHIFT 14 ++#define VR9_PCE_GCTRL_1_PARSER_DBG_SIZE 2 ++/* Bit: 'FLOWPTR_LIST_EN' */ ++/* Description: 'Flow Pointer List enable' */ ++#define VR9_PCE_GCTRL_1_FLOWPTR_LIST_EN_OFFSET 0x457 ++#define VR9_PCE_GCTRL_1_FLOWPTR_LIST_EN_SHIFT 4 ++#define VR9_PCE_GCTRL_1_FLOWPTR_LIST_EN_SIZE 1 ++/* Bit: 'MAC_GLOCKMOD' */ ++/* Description: 'MAC Address Table Lock forwarding mode' */ ++#define VR9_PCE_GCTRL_1_MAC_GLOCKMOD_OFFSET 0x457 ++#define VR9_PCE_GCTRL_1_MAC_GLOCKMOD_SHIFT 3 ++#define VR9_PCE_GCTRL_1_MAC_GLOCKMOD_SIZE 1 ++/* Bit: 'MAC_GLOCK' */ ++/* Description: 'MAC Address Table Lock' */ ++#define VR9_PCE_GCTRL_1_MAC_GLOCK_OFFSET 0x457 ++#define VR9_PCE_GCTRL_1_MAC_GLOCK_SHIFT 2 ++#define VR9_PCE_GCTRL_1_MAC_GLOCK_SIZE 1 ++/* Bit: 'PCE_DIS' */ ++/* Description: 'PCE Disable after currently processed packet' */ ++#define VR9_PCE_GCTRL_1_PCE_DIS_OFFSET 0x457 ++#define VR9_PCE_GCTRL_1_PCE_DIS_SHIFT 1 ++#define VR9_PCE_GCTRL_1_PCE_DIS_SIZE 1 ++/* Bit: 'LRNMOD' */ ++/* Description: 'MAC Address Learning Mode' */ ++#define VR9_PCE_GCTRL_1_LRNMOD_OFFSET 0x457 ++#define VR9_PCE_GCTRL_1_LRNMOD_SHIFT 0 ++#define VR9_PCE_GCTRL_1_LRNMOD_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Three-color MarkerGlobal Control Register' */ ++/* Bit: 'DPRED' */ ++/* Description: 'Re-marking Drop Precedence Red Encoding' */ ++#define VR9_PCE_TCM_GLOB_CTRL_DPRED_OFFSET 0x458 ++#define VR9_PCE_TCM_GLOB_CTRL_DPRED_SHIFT 6 ++#define VR9_PCE_TCM_GLOB_CTRL_DPRED_SIZE 3 ++/* Bit: 'DPYEL' */ ++/* Description: 'Re-marking Drop Precedence Yellow Encoding' */ ++#define VR9_PCE_TCM_GLOB_CTRL_DPYEL_OFFSET 0x458 ++#define VR9_PCE_TCM_GLOB_CTRL_DPYEL_SHIFT 3 ++#define VR9_PCE_TCM_GLOB_CTRL_DPYEL_SIZE 3 ++/* Bit: 'DPGRN' */ ++/* Description: 'Re-marking Drop Precedence Green Encoding' */ ++#define VR9_PCE_TCM_GLOB_CTRL_DPGRN_OFFSET 0x458 ++#define VR9_PCE_TCM_GLOB_CTRL_DPGRN_SHIFT 0 ++#define VR9_PCE_TCM_GLOB_CTRL_DPGRN_SIZE 3 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'IGMP Control Register' */ ++/* Bit: 'FAGEEN' */ ++/* Description: 'Force Aging of Table Entries Enable' */ ++#define VR9_PCE_IGMP_CTRL_FAGEEN_OFFSET 0x459 ++#define VR9_PCE_IGMP_CTRL_FAGEEN_SHIFT 15 ++#define VR9_PCE_IGMP_CTRL_FAGEEN_SIZE 1 ++/* Bit: 'FLEAVE' */ ++/* Description: 'Fast Leave Enable' */ ++#define VR9_PCE_IGMP_CTRL_FLEAVE_OFFSET 0x459 ++#define VR9_PCE_IGMP_CTRL_FLEAVE_SHIFT 14 ++#define VR9_PCE_IGMP_CTRL_FLEAVE_SIZE 1 ++/* Bit: 'DMRTEN' */ ++/* Description: 'Default Maximum Response Time Enable' */ ++#define VR9_PCE_IGMP_CTRL_DMRTEN_OFFSET 0x459 ++#define VR9_PCE_IGMP_CTRL_DMRTEN_SHIFT 13 ++#define VR9_PCE_IGMP_CTRL_DMRTEN_SIZE 1 ++/* Bit: 'JASUP' */ ++/* Description: 'Join Aggregation Suppression Enable' */ ++#define VR9_PCE_IGMP_CTRL_JASUP_OFFSET 0x459 ++#define VR9_PCE_IGMP_CTRL_JASUP_SHIFT 12 ++#define VR9_PCE_IGMP_CTRL_JASUP_SIZE 1 ++/* Bit: 'REPSUP' */ ++/* Description: 'Report Suppression Enable' */ ++#define VR9_PCE_IGMP_CTRL_REPSUP_OFFSET 0x459 ++#define VR9_PCE_IGMP_CTRL_REPSUP_SHIFT 11 ++#define VR9_PCE_IGMP_CTRL_REPSUP_SIZE 1 ++/* Bit: 'SRPEN' */ ++/* Description: 'Snooping of Router Port Enable' */ ++#define VR9_PCE_IGMP_CTRL_SRPEN_OFFSET 0x459 ++#define VR9_PCE_IGMP_CTRL_SRPEN_SHIFT 10 ++#define VR9_PCE_IGMP_CTRL_SRPEN_SIZE 1 ++/* Bit: 'ROB' */ ++/* Description: 'Robustness Variable' */ ++#define VR9_PCE_IGMP_CTRL_ROB_OFFSET 0x459 ++#define VR9_PCE_IGMP_CTRL_ROB_SHIFT 8 ++#define VR9_PCE_IGMP_CTRL_ROB_SIZE 2 ++/* Bit: 'DMRT' */ ++/* Description: 'IGMP Default Maximum Response Time' */ ++#define VR9_PCE_IGMP_CTRL_DMRT_OFFSET 0x459 ++#define VR9_PCE_IGMP_CTRL_DMRT_SHIFT 0 ++#define VR9_PCE_IGMP_CTRL_DMRT_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'IGMP Default RouterPort Map Register' */ ++/* Bit: 'DRPM' */ ++/* Description: 'IGMP Default Router Port Map' */ ++#define VR9_PCE_IGMP_DRPM_DRPM_OFFSET 0x45A ++#define VR9_PCE_IGMP_DRPM_DRPM_SHIFT 0 ++#define VR9_PCE_IGMP_DRPM_DRPM_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'IGMP Aging Register0' */ ++/* Bit: 'MANT' */ ++/* Description: 'IGMP Group Aging Time Mantissa' */ ++#define VR9_PCE_IGMP_AGE_0_MANT_OFFSET 0x45B ++#define VR9_PCE_IGMP_AGE_0_MANT_SHIFT 3 ++#define VR9_PCE_IGMP_AGE_0_MANT_SIZE 8 ++/* Bit: 'EXP' */ ++/* Description: 'IGMP Group Aging Time Exponent' */ ++#define VR9_PCE_IGMP_AGE_0_EXP_OFFSET 0x45B ++#define VR9_PCE_IGMP_AGE_0_EXP_SHIFT 0 ++#define VR9_PCE_IGMP_AGE_0_EXP_SIZE 3 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'IGMP Aging Register1' */ ++/* Bit: 'MANT' */ ++/* Description: 'IGMP Router Port Aging Time Mantissa' */ ++#define VR9_PCE_IGMP_AGE_1_MANT_OFFSET 0x45C ++#define VR9_PCE_IGMP_AGE_1_MANT_SHIFT 0 ++#define VR9_PCE_IGMP_AGE_1_MANT_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'IGMP Status Register' */ ++/* Bit: 'IGPM' */ ++/* Description: 'IGMP Port Map' */ ++#define VR9_PCE_IGMP_STAT_IGPM_OFFSET 0x45D ++#define VR9_PCE_IGMP_STAT_IGPM_SHIFT 0 ++#define VR9_PCE_IGMP_STAT_IGPM_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Wake-on-LAN ControlRegister' */ ++/* Bit: 'PASSEN' */ ++/* Description: 'WoL Password Enable' */ ++#define VR9_WOL_GLB_CTRL_PASSEN_OFFSET 0x45E ++#define VR9_WOL_GLB_CTRL_PASSEN_SHIFT 0 ++#define VR9_WOL_GLB_CTRL_PASSEN_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Wake-on-LAN DestinationAddress Register 0' */ ++/* Bit: 'DA0' */ ++/* Description: 'WoL Destination Address [15:0]' */ ++#define VR9_WOL_DA_0_DA0_OFFSET 0x45F ++#define VR9_WOL_DA_0_DA0_SHIFT 0 ++#define VR9_WOL_DA_0_DA0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Wake-on-LAN DestinationAddress Register 1' */ ++/* Bit: 'DA1' */ ++/* Description: 'WoL Destination Address [31:16]' */ ++#define VR9_WOL_DA_1_DA1_OFFSET 0x460 ++#define VR9_WOL_DA_1_DA1_SHIFT 0 ++#define VR9_WOL_DA_1_DA1_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Wake-on-LAN DestinationAddress Register 2' */ ++/* Bit: 'DA2' */ ++/* Description: 'WoL Destination Address [47:32]' */ ++#define VR9_WOL_DA_2_DA2_OFFSET 0x461 ++#define VR9_WOL_DA_2_DA2_SHIFT 0 ++#define VR9_WOL_DA_2_DA2_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Wake-on-LAN Password Register0' */ ++/* Bit: 'PW0' */ ++/* Description: 'WoL Password [15:0]' */ ++#define VR9_WOL_PW_0_PW0_OFFSET 0x462 ++#define VR9_WOL_PW_0_PW0_SHIFT 0 ++#define VR9_WOL_PW_0_PW0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Wake-on-LAN Password Register1' */ ++/* Bit: 'PW1' */ ++/* Description: 'WoL Password [31:16]' */ ++#define VR9_WOL_PW_1_PW1_OFFSET 0x463 ++#define VR9_WOL_PW_1_PW1_SHIFT 0 ++#define VR9_WOL_PW_1_PW1_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Wake-on-LAN Password Register2' */ ++/* Bit: 'PW2' */ ++/* Description: 'WoL Password [47:32]' */ ++#define VR9_WOL_PW_2_PW2_OFFSET 0x464 ++#define VR9_WOL_PW_2_PW2_SHIFT 0 ++#define VR9_WOL_PW_2_PW2_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Parser and ClassificationEngine Global Interrupt Enable Register 0' */ ++/* Bit: 'PINT_15' */ ++/* Description: 'Port Interrupt Enable' */ ++#define VR9_PCE_IER_0_PINT_15_OFFSET 0x465 ++#define VR9_PCE_IER_0_PINT_15_SHIFT 15 ++#define VR9_PCE_IER_0_PINT_15_SIZE 1 ++/* Bit: 'PINT_14' */ ++/* Description: 'Port Interrupt Enable' */ ++#define VR9_PCE_IER_0_PINT_14_OFFSET 0x465 ++#define VR9_PCE_IER_0_PINT_14_SHIFT 14 ++#define VR9_PCE_IER_0_PINT_14_SIZE 1 ++/* Bit: 'PINT_13' */ ++/* Description: 'Port Interrupt Enable' */ ++#define VR9_PCE_IER_0_PINT_13_OFFSET 0x465 ++#define VR9_PCE_IER_0_PINT_13_SHIFT 13 ++#define VR9_PCE_IER_0_PINT_13_SIZE 1 ++/* Bit: 'PINT_12' */ ++/* Description: 'Port Interrupt Enable' */ ++#define VR9_PCE_IER_0_PINT_12_OFFSET 0x465 ++#define VR9_PCE_IER_0_PINT_12_SHIFT 12 ++#define VR9_PCE_IER_0_PINT_12_SIZE 1 ++/* Bit: 'PINT_11' */ ++/* Description: 'Port Interrupt Enable' */ ++#define VR9_PCE_IER_0_PINT_11_OFFSET 0x465 ++#define VR9_PCE_IER_0_PINT_11_SHIFT 11 ++#define VR9_PCE_IER_0_PINT_11_SIZE 1 ++/* Bit: 'PINT_10' */ ++/* Description: 'Port Interrupt Enable' */ ++#define VR9_PCE_IER_0_PINT_10_OFFSET 0x465 ++#define VR9_PCE_IER_0_PINT_10_SHIFT 10 ++#define VR9_PCE_IER_0_PINT_10_SIZE 1 ++/* Bit: 'PINT_9' */ ++/* Description: 'Port Interrupt Enable' */ ++#define VR9_PCE_IER_0_PINT_9_OFFSET 0x465 ++#define VR9_PCE_IER_0_PINT_9_SHIFT 9 ++#define VR9_PCE_IER_0_PINT_9_SIZE 1 ++/* Bit: 'PINT_8' */ ++/* Description: 'Port Interrupt Enable' */ ++#define VR9_PCE_IER_0_PINT_8_OFFSET 0x465 ++#define VR9_PCE_IER_0_PINT_8_SHIFT 8 ++#define VR9_PCE_IER_0_PINT_8_SIZE 1 ++/* Bit: 'PINT_7' */ ++/* Description: 'Port Interrupt Enable' */ ++#define VR9_PCE_IER_0_PINT_7_OFFSET 0x465 ++#define VR9_PCE_IER_0_PINT_7_SHIFT 7 ++#define VR9_PCE_IER_0_PINT_7_SIZE 1 ++/* Bit: 'PINT_6' */ ++/* Description: 'Port Interrupt Enable' */ ++#define VR9_PCE_IER_0_PINT_6_OFFSET 0x465 ++#define VR9_PCE_IER_0_PINT_6_SHIFT 6 ++#define VR9_PCE_IER_0_PINT_6_SIZE 1 ++/* Bit: 'PINT_5' */ ++/* Description: 'Port Interrupt Enable' */ ++#define VR9_PCE_IER_0_PINT_5_OFFSET 0x465 ++#define VR9_PCE_IER_0_PINT_5_SHIFT 5 ++#define VR9_PCE_IER_0_PINT_5_SIZE 1 ++/* Bit: 'PINT_4' */ ++/* Description: 'Port Interrupt Enable' */ ++#define VR9_PCE_IER_0_PINT_4_OFFSET 0x465 ++#define VR9_PCE_IER_0_PINT_4_SHIFT 4 ++#define VR9_PCE_IER_0_PINT_4_SIZE 1 ++/* Bit: 'PINT_3' */ ++/* Description: 'Port Interrupt Enable' */ ++#define VR9_PCE_IER_0_PINT_3_OFFSET 0x465 ++#define VR9_PCE_IER_0_PINT_3_SHIFT 3 ++#define VR9_PCE_IER_0_PINT_3_SIZE 1 ++/* Bit: 'PINT_2' */ ++/* Description: 'Port Interrupt Enable' */ ++#define VR9_PCE_IER_0_PINT_2_OFFSET 0x465 ++#define VR9_PCE_IER_0_PINT_2_SHIFT 2 ++#define VR9_PCE_IER_0_PINT_2_SIZE 1 ++/* Bit: 'PINT_1' */ ++/* Description: 'Port Interrupt Enable' */ ++#define VR9_PCE_IER_0_PINT_1_OFFSET 0x465 ++#define VR9_PCE_IER_0_PINT_1_SHIFT 1 ++#define VR9_PCE_IER_0_PINT_1_SIZE 1 ++/* Bit: 'PINT_0' */ ++/* Description: 'Port Interrupt Enable' */ ++#define VR9_PCE_IER_0_PINT_0_OFFSET 0x465 ++#define VR9_PCE_IER_0_PINT_0_SHIFT 0 ++#define VR9_PCE_IER_0_PINT_0_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Parser and ClassificationEngine Global Interrupt Enable Register 1' */ ++/* Bit: 'FLOWINT' */ ++/* Description: 'Traffic Flow Table Interrupt Rule matched Interrupt ++Enable' */ ++#define VR9_PCE_IER_1_FLOWINT_OFFSET 0x466 ++#define VR9_PCE_IER_1_FLOWINT_SHIFT 6 ++#define VR9_PCE_IER_1_FLOWINT_SIZE 1 ++/* Bit: 'CPH2' */ ++/* Description: 'Classification Phase 2 Ready Interrupt Enable' */ ++#define VR9_PCE_IER_1_CPH2_OFFSET 0x466 ++#define VR9_PCE_IER_1_CPH2_SHIFT 5 ++#define VR9_PCE_IER_1_CPH2_SIZE 1 ++/* Bit: 'CPH1' */ ++/* Description: 'Classification Phase 1 Ready Interrupt Enable' */ ++#define VR9_PCE_IER_1_CPH1_OFFSET 0x466 ++#define VR9_PCE_IER_1_CPH1_SHIFT 4 ++#define VR9_PCE_IER_1_CPH1_SIZE 1 ++/* Bit: 'CPH0' */ ++/* Description: 'Classification Phase 0 Ready Interrupt Enable' */ ++#define VR9_PCE_IER_1_CPH0_OFFSET 0x466 ++#define VR9_PCE_IER_1_CPH0_SHIFT 3 ++#define VR9_PCE_IER_1_CPH0_SIZE 1 ++/* Bit: 'PRDY' */ ++/* Description: 'Parser Ready Interrupt Enable' */ ++#define VR9_PCE_IER_1_PRDY_OFFSET 0x466 ++#define VR9_PCE_IER_1_PRDY_SHIFT 2 ++#define VR9_PCE_IER_1_PRDY_SIZE 1 ++/* Bit: 'IGTF' */ ++/* Description: 'IGMP Table Full Interrupt Enable' */ ++#define VR9_PCE_IER_1_IGTF_OFFSET 0x466 ++#define VR9_PCE_IER_1_IGTF_SHIFT 1 ++#define VR9_PCE_IER_1_IGTF_SIZE 1 ++/* Bit: 'MTF' */ ++/* Description: 'MAC Table Full Interrupt Enable' */ ++#define VR9_PCE_IER_1_MTF_OFFSET 0x466 ++#define VR9_PCE_IER_1_MTF_SHIFT 0 ++#define VR9_PCE_IER_1_MTF_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Parser and ClassificationEngine Global Interrupt Status Register 0' */ ++/* Bit: 'PINT_15' */ ++/* Description: 'Port Interrupt' */ ++#define VR9_PCE_ISR_0_PINT_15_OFFSET 0x467 ++#define VR9_PCE_ISR_0_PINT_15_SHIFT 15 ++#define VR9_PCE_ISR_0_PINT_15_SIZE 1 ++/* Bit: 'PINT_14' */ ++/* Description: 'Port Interrupt' */ ++#define VR9_PCE_ISR_0_PINT_14_OFFSET 0x467 ++#define VR9_PCE_ISR_0_PINT_14_SHIFT 14 ++#define VR9_PCE_ISR_0_PINT_14_SIZE 1 ++/* Bit: 'PINT_13' */ ++/* Description: 'Port Interrupt' */ ++#define VR9_PCE_ISR_0_PINT_13_OFFSET 0x467 ++#define VR9_PCE_ISR_0_PINT_13_SHIFT 13 ++#define VR9_PCE_ISR_0_PINT_13_SIZE 1 ++/* Bit: 'PINT_12' */ ++/* Description: 'Port Interrupt' */ ++#define VR9_PCE_ISR_0_PINT_12_OFFSET 0x467 ++#define VR9_PCE_ISR_0_PINT_12_SHIFT 12 ++#define VR9_PCE_ISR_0_PINT_12_SIZE 1 ++/* Bit: 'PINT_11' */ ++/* Description: 'Port Interrupt' */ ++#define VR9_PCE_ISR_0_PINT_11_OFFSET 0x467 ++#define VR9_PCE_ISR_0_PINT_11_SHIFT 11 ++#define VR9_PCE_ISR_0_PINT_11_SIZE 1 ++/* Bit: 'PINT_10' */ ++/* Description: 'Port Interrupt' */ ++#define VR9_PCE_ISR_0_PINT_10_OFFSET 0x467 ++#define VR9_PCE_ISR_0_PINT_10_SHIFT 10 ++#define VR9_PCE_ISR_0_PINT_10_SIZE 1 ++/* Bit: 'PINT_9' */ ++/* Description: 'Port Interrupt' */ ++#define VR9_PCE_ISR_0_PINT_9_OFFSET 0x467 ++#define VR9_PCE_ISR_0_PINT_9_SHIFT 9 ++#define VR9_PCE_ISR_0_PINT_9_SIZE 1 ++/* Bit: 'PINT_8' */ ++/* Description: 'Port Interrupt' */ ++#define VR9_PCE_ISR_0_PINT_8_OFFSET 0x467 ++#define VR9_PCE_ISR_0_PINT_8_SHIFT 8 ++#define VR9_PCE_ISR_0_PINT_8_SIZE 1 ++/* Bit: 'PINT_7' */ ++/* Description: 'Port Interrupt' */ ++#define VR9_PCE_ISR_0_PINT_7_OFFSET 0x467 ++#define VR9_PCE_ISR_0_PINT_7_SHIFT 7 ++#define VR9_PCE_ISR_0_PINT_7_SIZE 1 ++/* Bit: 'PINT_6' */ ++/* Description: 'Port Interrupt' */ ++#define VR9_PCE_ISR_0_PINT_6_OFFSET 0x467 ++#define VR9_PCE_ISR_0_PINT_6_SHIFT 6 ++#define VR9_PCE_ISR_0_PINT_6_SIZE 1 ++/* Bit: 'PINT_5' */ ++/* Description: 'Port Interrupt' */ ++#define VR9_PCE_ISR_0_PINT_5_OFFSET 0x467 ++#define VR9_PCE_ISR_0_PINT_5_SHIFT 5 ++#define VR9_PCE_ISR_0_PINT_5_SIZE 1 ++/* Bit: 'PINT_4' */ ++/* Description: 'Port Interrupt' */ ++#define VR9_PCE_ISR_0_PINT_4_OFFSET 0x467 ++#define VR9_PCE_ISR_0_PINT_4_SHIFT 4 ++#define VR9_PCE_ISR_0_PINT_4_SIZE 1 ++/* Bit: 'PINT_3' */ ++/* Description: 'Port Interrupt' */ ++#define VR9_PCE_ISR_0_PINT_3_OFFSET 0x467 ++#define VR9_PCE_ISR_0_PINT_3_SHIFT 3 ++#define VR9_PCE_ISR_0_PINT_3_SIZE 1 ++/* Bit: 'PINT_2' */ ++/* Description: 'Port Interrupt' */ ++#define VR9_PCE_ISR_0_PINT_2_OFFSET 0x467 ++#define VR9_PCE_ISR_0_PINT_2_SHIFT 2 ++#define VR9_PCE_ISR_0_PINT_2_SIZE 1 ++/* Bit: 'PINT_1' */ ++/* Description: 'Port Interrupt' */ ++#define VR9_PCE_ISR_0_PINT_1_OFFSET 0x467 ++#define VR9_PCE_ISR_0_PINT_1_SHIFT 1 ++#define VR9_PCE_ISR_0_PINT_1_SIZE 1 ++/* Bit: 'PINT_0' */ ++/* Description: 'Port Interrupt' */ ++#define VR9_PCE_ISR_0_PINT_0_OFFSET 0x467 ++#define VR9_PCE_ISR_0_PINT_0_SHIFT 0 ++#define VR9_PCE_ISR_0_PINT_0_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Parser and ClassificationEngine Global Interrupt Status Register 1' */ ++/* Bit: 'FLOWINT' */ ++/* Description: 'Traffic Flow Table Interrupt Rule matched' */ ++#define VR9_PCE_ISR_1_FLOWINT_OFFSET 0x468 ++#define VR9_PCE_ISR_1_FLOWINT_SHIFT 6 ++#define VR9_PCE_ISR_1_FLOWINT_SIZE 1 ++/* Bit: 'CPH2' */ ++/* Description: 'Classification Phase 2 Ready Interrupt' */ ++#define VR9_PCE_ISR_1_CPH2_OFFSET 0x468 ++#define VR9_PCE_ISR_1_CPH2_SHIFT 5 ++#define VR9_PCE_ISR_1_CPH2_SIZE 1 ++/* Bit: 'CPH1' */ ++/* Description: 'Classification Phase 1 Ready Interrupt' */ ++#define VR9_PCE_ISR_1_CPH1_OFFSET 0x468 ++#define VR9_PCE_ISR_1_CPH1_SHIFT 4 ++#define VR9_PCE_ISR_1_CPH1_SIZE 1 ++/* Bit: 'CPH0' */ ++/* Description: 'Classification Phase 0 Ready Interrupt' */ ++#define VR9_PCE_ISR_1_CPH0_OFFSET 0x468 ++#define VR9_PCE_ISR_1_CPH0_SHIFT 3 ++#define VR9_PCE_ISR_1_CPH0_SIZE 1 ++/* Bit: 'PRDY' */ ++/* Description: 'Parser Ready Interrupt' */ ++#define VR9_PCE_ISR_1_PRDY_OFFSET 0x468 ++#define VR9_PCE_ISR_1_PRDY_SHIFT 2 ++#define VR9_PCE_ISR_1_PRDY_SIZE 1 ++/* Bit: 'IGTF' */ ++/* Description: 'IGMP Table Full Interrupt' */ ++#define VR9_PCE_ISR_1_IGTF_OFFSET 0x468 ++#define VR9_PCE_ISR_1_IGTF_SHIFT 1 ++#define VR9_PCE_ISR_1_IGTF_SIZE 1 ++/* Bit: 'MTF' */ ++/* Description: 'MAC Table Full Interrupt' */ ++#define VR9_PCE_ISR_1_MTF_OFFSET 0x468 ++#define VR9_PCE_ISR_1_MTF_SHIFT 0 ++#define VR9_PCE_ISR_1_MTF_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Parser Status Register' */ ++/* Bit: 'FSM_DAT_CNT' */ ++/* Description: 'Parser FSM Data Counter' */ ++#define VR9_PARSER_STAT_FSM_DAT_CNT_OFFSET 0x469 ++#define VR9_PARSER_STAT_FSM_DAT_CNT_SHIFT 8 ++#define VR9_PARSER_STAT_FSM_DAT_CNT_SIZE 8 ++/* Bit: 'FSM_STATE' */ ++/* Description: 'Parser FSM State' */ ++#define VR9_PARSER_STAT_FSM_STATE_OFFSET 0x469 ++#define VR9_PARSER_STAT_FSM_STATE_SHIFT 5 ++#define VR9_PARSER_STAT_FSM_STATE_SIZE 3 ++/* Bit: 'PKT_ERR' */ ++/* Description: 'Packet error detected' */ ++#define VR9_PARSER_STAT_PKT_ERR_OFFSET 0x469 ++#define VR9_PARSER_STAT_PKT_ERR_SHIFT 4 ++#define VR9_PARSER_STAT_PKT_ERR_SIZE 1 ++/* Bit: 'FSM_FIN' */ ++/* Description: 'Parser FSM finished' */ ++#define VR9_PARSER_STAT_FSM_FIN_OFFSET 0x469 ++#define VR9_PARSER_STAT_FSM_FIN_SHIFT 3 ++#define VR9_PARSER_STAT_FSM_FIN_SIZE 1 ++/* Bit: 'FSM_START' */ ++/* Description: 'Parser FSM start' */ ++#define VR9_PARSER_STAT_FSM_START_OFFSET 0x469 ++#define VR9_PARSER_STAT_FSM_START_SHIFT 2 ++#define VR9_PARSER_STAT_FSM_START_SIZE 1 ++/* Bit: 'FIFO_RDY' */ ++/* Description: 'Parser FIFO ready for read.' */ ++#define VR9_PARSER_STAT_FIFO_RDY_OFFSET 0x469 ++#define VR9_PARSER_STAT_FIFO_RDY_SHIFT 1 ++#define VR9_PARSER_STAT_FIFO_RDY_SIZE 1 ++/* Bit: 'FIFO_FULL' */ ++/* Description: 'Parser's FIFO full' */ ++#define VR9_PARSER_STAT_FIFO_FULL_OFFSET 0x469 ++#define VR9_PARSER_STAT_FIFO_FULL_SHIFT 0 ++#define VR9_PARSER_STAT_FIFO_FULL_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PCE Port ControlRegister 0' */ ++/* Bit: 'MCST' */ ++/* Description: 'Multicast Forwarding Mode Selection' */ ++#define VR9_PCE_PCTRL_0_MCST_OFFSET 0x480 ++#define VR9_PCE_PCTRL_0_MCST_SHIFT 13 ++#define VR9_PCE_PCTRL_0_MCST_SIZE 1 ++/* Bit: 'EGSTEN' */ ++/* Description: 'Table-based Egress Special Tag Enable' */ ++#define VR9_PCE_PCTRL_0_EGSTEN_OFFSET 0x480 ++#define VR9_PCE_PCTRL_0_EGSTEN_SHIFT 12 ++#define VR9_PCE_PCTRL_0_EGSTEN_SIZE 1 ++/* Bit: 'IGSTEN' */ ++/* Description: 'Ingress Special Tag Enable' */ ++#define VR9_PCE_PCTRL_0_IGSTEN_OFFSET 0x480 ++#define VR9_PCE_PCTRL_0_IGSTEN_SHIFT 11 ++#define VR9_PCE_PCTRL_0_IGSTEN_SIZE 1 ++/* Bit: 'PCPEN' */ ++/* Description: 'PCP Remarking Mode' */ ++#define VR9_PCE_PCTRL_0_PCPEN_OFFSET 0x480 ++#define VR9_PCE_PCTRL_0_PCPEN_SHIFT 10 ++#define VR9_PCE_PCTRL_0_PCPEN_SIZE 1 ++/* Bit: 'CLPEN' */ ++/* Description: 'Class Remarking Mode' */ ++#define VR9_PCE_PCTRL_0_CLPEN_OFFSET 0x480 ++#define VR9_PCE_PCTRL_0_CLPEN_SHIFT 9 ++#define VR9_PCE_PCTRL_0_CLPEN_SIZE 1 ++/* Bit: 'DPEN' */ ++/* Description: 'Drop Precedence Remarking Mode' */ ++#define VR9_PCE_PCTRL_0_DPEN_OFFSET 0x480 ++#define VR9_PCE_PCTRL_0_DPEN_SHIFT 8 ++#define VR9_PCE_PCTRL_0_DPEN_SIZE 1 ++/* Bit: 'CMOD' */ ++/* Description: 'Three-color Marker Color Mode' */ ++#define VR9_PCE_PCTRL_0_CMOD_OFFSET 0x480 ++#define VR9_PCE_PCTRL_0_CMOD_SHIFT 7 ++#define VR9_PCE_PCTRL_0_CMOD_SIZE 1 ++/* Bit: 'VREP' */ ++/* Description: 'VLAN Replacement Mode' */ ++#define VR9_PCE_PCTRL_0_VREP_OFFSET 0x480 ++#define VR9_PCE_PCTRL_0_VREP_SHIFT 6 ++#define VR9_PCE_PCTRL_0_VREP_SIZE 1 ++/* Bit: 'TVM' */ ++/* Description: 'Transparent VLAN Mode' */ ++#define VR9_PCE_PCTRL_0_TVM_OFFSET 0x480 ++#define VR9_PCE_PCTRL_0_TVM_SHIFT 5 ++#define VR9_PCE_PCTRL_0_TVM_SIZE 1 ++/* Bit: 'PLOCK' */ ++/* Description: 'Port Locking Enable' */ ++#define VR9_PCE_PCTRL_0_PLOCK_OFFSET 0x480 ++#define VR9_PCE_PCTRL_0_PLOCK_SHIFT 4 ++#define VR9_PCE_PCTRL_0_PLOCK_SIZE 1 ++/* Bit: 'AGEDIS' */ ++/* Description: 'Aging Disable' */ ++#define VR9_PCE_PCTRL_0_AGEDIS_OFFSET 0x480 ++#define VR9_PCE_PCTRL_0_AGEDIS_SHIFT 3 ++#define VR9_PCE_PCTRL_0_AGEDIS_SIZE 1 ++/* Bit: 'PSTATE' */ ++/* Description: 'Port State' */ ++#define VR9_PCE_PCTRL_0_PSTATE_OFFSET 0x480 ++#define VR9_PCE_PCTRL_0_PSTATE_SHIFT 0 ++#define VR9_PCE_PCTRL_0_PSTATE_SIZE 3 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PCE Port ControlRegister 1' */ ++/* Bit: 'LRNLIM' */ ++/* Description: 'MAC Address Learning Limit' */ ++#define VR9_PCE_PCTRL_1_LRNLIM_OFFSET 0x481 ++#define VR9_PCE_PCTRL_1_LRNLIM_SHIFT 0 ++#define VR9_PCE_PCTRL_1_LRNLIM_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PCE Port ControlRegister 2' */ ++/* Bit: 'DSCPMOD' */ ++/* Description: 'DSCP Mode Selection' */ ++#define VR9_PCE_PCTRL_2_DSCPMOD_OFFSET 0x482 ++#define VR9_PCE_PCTRL_2_DSCPMOD_SHIFT 7 ++#define VR9_PCE_PCTRL_2_DSCPMOD_SIZE 1 ++/* Bit: 'DSCP' */ ++/* Description: 'Enable DSCP to select the Class of Service' */ ++#define VR9_PCE_PCTRL_2_DSCP_OFFSET 0x482 ++#define VR9_PCE_PCTRL_2_DSCP_SHIFT 5 ++#define VR9_PCE_PCTRL_2_DSCP_SIZE 2 ++/* Bit: 'PCP' */ ++/* Description: 'Enable VLAN PCP to select the Class of Service' */ ++#define VR9_PCE_PCTRL_2_PCP_OFFSET 0x482 ++#define VR9_PCE_PCTRL_2_PCP_SHIFT 4 ++#define VR9_PCE_PCTRL_2_PCP_SIZE 1 ++/* Bit: 'PCLASS' */ ++/* Description: 'Port-based Traffic Class' */ ++#define VR9_PCE_PCTRL_2_PCLASS_OFFSET 0x482 ++#define VR9_PCE_PCTRL_2_PCLASS_SHIFT 0 ++#define VR9_PCE_PCTRL_2_PCLASS_SIZE 4 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PCE Port ControlRegister 3' */ ++/* Bit: 'VIO_8' */ ++/* Description: 'Violation Type 8 Mirroring Enable' */ ++#define VR9_PCE_PCTRL_3_VIO_8_OFFSET 0x483 ++#define VR9_PCE_PCTRL_3_VIO_8_SHIFT 12 ++#define VR9_PCE_PCTRL_3_VIO_8_SIZE 1 ++/* Bit: 'EDIR' */ ++/* Description: 'Egress Redirection Mode' */ ++#define VR9_PCE_PCTRL_3_EDIR_OFFSET 0x483 ++#define VR9_PCE_PCTRL_3_EDIR_SHIFT 11 ++#define VR9_PCE_PCTRL_3_EDIR_SIZE 1 ++/* Bit: 'RXDMIR' */ ++/* Description: 'Receive Mirroring Enable for dropped frames' */ ++#define VR9_PCE_PCTRL_3_RXDMIR_OFFSET 0x483 ++#define VR9_PCE_PCTRL_3_RXDMIR_SHIFT 10 ++#define VR9_PCE_PCTRL_3_RXDMIR_SIZE 1 ++/* Bit: 'RXVMIR' */ ++/* Description: 'Receive Mirroring Enable for valid frames' */ ++#define VR9_PCE_PCTRL_3_RXVMIR_OFFSET 0x483 ++#define VR9_PCE_PCTRL_3_RXVMIR_SHIFT 9 ++#define VR9_PCE_PCTRL_3_RXVMIR_SIZE 1 ++/* Bit: 'TXMIR' */ ++/* Description: 'Transmit Mirroring Enable' */ ++#define VR9_PCE_PCTRL_3_TXMIR_OFFSET 0x483 ++#define VR9_PCE_PCTRL_3_TXMIR_SHIFT 8 ++#define VR9_PCE_PCTRL_3_TXMIR_SIZE 1 ++/* Bit: 'VIO_7' */ ++/* Description: 'Violation Type 7 Mirroring Enable' */ ++#define VR9_PCE_PCTRL_3_VIO_7_OFFSET 0x483 ++#define VR9_PCE_PCTRL_3_VIO_7_SHIFT 7 ++#define VR9_PCE_PCTRL_3_VIO_7_SIZE 1 ++/* Bit: 'VIO_6' */ ++/* Description: 'Violation Type 6 Mirroring Enable' */ ++#define VR9_PCE_PCTRL_3_VIO_6_OFFSET 0x483 ++#define VR9_PCE_PCTRL_3_VIO_6_SHIFT 6 ++#define VR9_PCE_PCTRL_3_VIO_6_SIZE 1 ++/* Bit: 'VIO_5' */ ++/* Description: 'Violation Type 5 Mirroring Enable' */ ++#define VR9_PCE_PCTRL_3_VIO_5_OFFSET 0x483 ++#define VR9_PCE_PCTRL_3_VIO_5_SHIFT 5 ++#define VR9_PCE_PCTRL_3_VIO_5_SIZE 1 ++/* Bit: 'VIO_4' */ ++/* Description: 'Violation Type 4 Mirroring Enable' */ ++#define VR9_PCE_PCTRL_3_VIO_4_OFFSET 0x483 ++#define VR9_PCE_PCTRL_3_VIO_4_SHIFT 4 ++#define VR9_PCE_PCTRL_3_VIO_4_SIZE 1 ++/* Bit: 'VIO_3' */ ++/* Description: 'Violation Type 3 Mirroring Enable' */ ++#define VR9_PCE_PCTRL_3_VIO_3_OFFSET 0x483 ++#define VR9_PCE_PCTRL_3_VIO_3_SHIFT 3 ++#define VR9_PCE_PCTRL_3_VIO_3_SIZE 1 ++/* Bit: 'VIO_2' */ ++/* Description: 'Violation Type 2 Mirroring Enable' */ ++#define VR9_PCE_PCTRL_3_VIO_2_OFFSET 0x483 ++#define VR9_PCE_PCTRL_3_VIO_2_SHIFT 2 ++#define VR9_PCE_PCTRL_3_VIO_2_SIZE 1 ++/* Bit: 'VIO_1' */ ++/* Description: 'Violation Type 1 Mirroring Enable' */ ++#define VR9_PCE_PCTRL_3_VIO_1_OFFSET 0x483 ++#define VR9_PCE_PCTRL_3_VIO_1_SHIFT 1 ++#define VR9_PCE_PCTRL_3_VIO_1_SIZE 1 ++/* Bit: 'VIO_0' */ ++/* Description: 'Violation Type 0 Mirroring Enable' */ ++#define VR9_PCE_PCTRL_3_VIO_0_OFFSET 0x483 ++#define VR9_PCE_PCTRL_3_VIO_0_SHIFT 0 ++#define VR9_PCE_PCTRL_3_VIO_0_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Wake-on-LAN ControlRegister' */ ++/* Bit: 'PORT' */ ++/* Description: 'WoL Enable' */ ++#define VR9_WOL_CTRL_PORT_OFFSET 0x484 ++#define VR9_WOL_CTRL_PORT_SHIFT 0 ++#define VR9_WOL_CTRL_PORT_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PCE VLAN ControlRegister' */ ++/* Bit: 'VID0' */ ++/* Description: 'Priority Tagged Rule' */ ++#define VR9_PCE_VCTRL_VID0_OFFSET 0x485 ++#define VR9_PCE_VCTRL_VID0_SHIFT 6 ++#define VR9_PCE_VCTRL_VID0_SIZE 1 ++/* Bit: 'VSR' */ ++/* Description: 'VLAN Security Rule' */ ++#define VR9_PCE_VCTRL_VSR_OFFSET 0x485 ++#define VR9_PCE_VCTRL_VSR_SHIFT 5 ++#define VR9_PCE_VCTRL_VSR_SIZE 1 ++/* Bit: 'VEMR' */ ++/* Description: 'VLAN Egress Member Violation Rule' */ ++#define VR9_PCE_VCTRL_VEMR_OFFSET 0x485 ++#define VR9_PCE_VCTRL_VEMR_SHIFT 4 ++#define VR9_PCE_VCTRL_VEMR_SIZE 1 ++/* Bit: 'VIMR' */ ++/* Description: 'VLAN Ingress Member Violation Rule' */ ++#define VR9_PCE_VCTRL_VIMR_OFFSET 0x485 ++#define VR9_PCE_VCTRL_VIMR_SHIFT 3 ++#define VR9_PCE_VCTRL_VIMR_SIZE 1 ++/* Bit: 'VINR' */ ++/* Description: 'VLAN Ingress Tag Rule' */ ++#define VR9_PCE_VCTRL_VINR_OFFSET 0x485 ++#define VR9_PCE_VCTRL_VINR_SHIFT 1 ++#define VR9_PCE_VCTRL_VINR_SIZE 2 ++/* Bit: 'UVR' */ ++/* Description: 'Unknown VLAN Rule' */ ++#define VR9_PCE_VCTRL_UVR_OFFSET 0x485 ++#define VR9_PCE_VCTRL_UVR_SHIFT 0 ++#define VR9_PCE_VCTRL_UVR_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PCE Default PortVID Register' */ ++/* Bit: 'PVID' */ ++/* Description: 'Default Port VID Index' */ ++#define VR9_PCE_DEFPVID_PVID_OFFSET 0x486 ++#define VR9_PCE_DEFPVID_PVID_SHIFT 0 ++#define VR9_PCE_DEFPVID_PVID_SIZE 6 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PCE Port StatusRegister' */ ++/* Bit: 'LRNCNT' */ ++/* Description: 'Learning Count' */ ++#define VR9_PCE_PSTAT_LRNCNT_OFFSET 0x487 ++#define VR9_PCE_PSTAT_LRNCNT_SHIFT 0 ++#define VR9_PCE_PSTAT_LRNCNT_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Parser and ClassificationEngine Port Interrupt Enable Register' */ ++/* Bit: 'FRZDRP' */ ++/* Description: 'MAC Table Freeze Drop Interrupt Enable' */ ++#define VR9_PCE_PIER_FRZDRP_OFFSET 0x488 ++#define VR9_PCE_PIER_FRZDRP_SHIFT 6 ++#define VR9_PCE_PIER_FRZDRP_SIZE 1 ++/* Bit: 'CLDRP' */ ++/* Description: 'Classification Drop Interrupt Enable' */ ++#define VR9_PCE_PIER_CLDRP_OFFSET 0x488 ++#define VR9_PCE_PIER_CLDRP_SHIFT 5 ++#define VR9_PCE_PIER_CLDRP_SIZE 1 ++/* Bit: 'PTDRP' */ ++/* Description: 'Port Drop Interrupt Enable' */ ++#define VR9_PCE_PIER_PTDRP_OFFSET 0x488 ++#define VR9_PCE_PIER_PTDRP_SHIFT 4 ++#define VR9_PCE_PIER_PTDRP_SIZE 1 ++/* Bit: 'VLAN' */ ++/* Description: 'VLAN Violation Interrupt Enable' */ ++#define VR9_PCE_PIER_VLAN_OFFSET 0x488 ++#define VR9_PCE_PIER_VLAN_SHIFT 3 ++#define VR9_PCE_PIER_VLAN_SIZE 1 ++/* Bit: 'WOL' */ ++/* Description: 'Wake-on-LAN Interrupt Enable' */ ++#define VR9_PCE_PIER_WOL_OFFSET 0x488 ++#define VR9_PCE_PIER_WOL_SHIFT 2 ++#define VR9_PCE_PIER_WOL_SIZE 1 ++/* Bit: 'LOCK' */ ++/* Description: 'Port Lock Alert Interrupt Enable' */ ++#define VR9_PCE_PIER_LOCK_OFFSET 0x488 ++#define VR9_PCE_PIER_LOCK_SHIFT 1 ++#define VR9_PCE_PIER_LOCK_SIZE 1 ++/* Bit: 'LIM' */ ++/* Description: 'Port Limit Alert Interrupt Enable' */ ++#define VR9_PCE_PIER_LIM_OFFSET 0x488 ++#define VR9_PCE_PIER_LIM_SHIFT 0 ++#define VR9_PCE_PIER_LIM_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Parser and ClassificationEngine Port Interrupt Status Register' */ ++/* Bit: 'FRZDRP' */ ++/* Description: 'MAC Table Freeze Drop Interrupt' */ ++#define VR9_PCE_PISR_FRZDRP_OFFSET 0x489 ++#define VR9_PCE_PISR_FRZDRP_SHIFT 6 ++#define VR9_PCE_PISR_FRZDRP_SIZE 1 ++/* Bit: 'CLDRP' */ ++/* Description: 'Classification Drop Interrupt' */ ++#define VR9_PCE_PISR_CLDRP_OFFSET 0x489 ++#define VR9_PCE_PISR_CLDRP_SHIFT 5 ++#define VR9_PCE_PISR_CLDRP_SIZE 1 ++/* Bit: 'PTDRP' */ ++/* Description: 'Port Drop Interrupt' */ ++#define VR9_PCE_PISR_PTDRP_OFFSET 0x489 ++#define VR9_PCE_PISR_PTDRP_SHIFT 4 ++#define VR9_PCE_PISR_PTDRP_SIZE 1 ++/* Bit: 'VLAN' */ ++/* Description: 'VLAN Violation Interrupt' */ ++#define VR9_PCE_PISR_VLAN_OFFSET 0x489 ++#define VR9_PCE_PISR_VLAN_SHIFT 3 ++#define VR9_PCE_PISR_VLAN_SIZE 1 ++/* Bit: 'WOL' */ ++/* Description: 'Wake-on-LAN Interrupt' */ ++#define VR9_PCE_PISR_WOL_OFFSET 0x489 ++#define VR9_PCE_PISR_WOL_SHIFT 2 ++#define VR9_PCE_PISR_WOL_SIZE 1 ++/* Bit: 'LOCK' */ ++/* Description: 'Port Lock Alert Interrupt' */ ++#define VR9_PCE_PISR_LOCK_OFFSET 0x489 ++#define VR9_PCE_PISR_LOCK_SHIFT 1 ++#define VR9_PCE_PISR_LOCK_SIZE 1 ++/* Bit: 'LIMIT' */ ++/* Description: 'Port Limitation Alert Interrupt' */ ++#define VR9_PCE_PISR_LIMIT_OFFSET 0x489 ++#define VR9_PCE_PISR_LIMIT_SHIFT 0 ++#define VR9_PCE_PISR_LIMIT_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Three-colorMarker Control Register' */ ++/* Bit: 'TCMEN' */ ++/* Description: 'Three-color Marker metering instance enable' */ ++#define VR9_PCE_TCM_CTRL_TCMEN_OFFSET 0x580 ++#define VR9_PCE_TCM_CTRL_TCMEN_SHIFT 0 ++#define VR9_PCE_TCM_CTRL_TCMEN_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Three-colorMarker Status Register' */ ++/* Bit: 'AL1' */ ++/* Description: 'Three-color Marker Alert 1 Status' */ ++#define VR9_PCE_TCM_STAT_AL1_OFFSET 0x581 ++#define VR9_PCE_TCM_STAT_AL1_SHIFT 1 ++#define VR9_PCE_TCM_STAT_AL1_SIZE 1 ++/* Bit: 'AL0' */ ++/* Description: 'Three-color Marker Alert 0 Status' */ ++#define VR9_PCE_TCM_STAT_AL0_OFFSET 0x581 ++#define VR9_PCE_TCM_STAT_AL0_SHIFT 0 ++#define VR9_PCE_TCM_STAT_AL0_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Three-color MarkerCommitted Burst Size Register' */ ++/* Bit: 'CBS' */ ++/* Description: 'Committed Burst Size' */ ++#define VR9_PCE_TCM_CBS_CBS_OFFSET 0x582 ++#define VR9_PCE_TCM_CBS_CBS_SHIFT 0 ++#define VR9_PCE_TCM_CBS_CBS_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Three-color MarkerExcess Burst Size Register' */ ++/* Bit: 'EBS' */ ++/* Description: 'Excess Burst Size' */ ++#define VR9_PCE_TCM_EBS_EBS_OFFSET 0x583 ++#define VR9_PCE_TCM_EBS_EBS_SHIFT 0 ++#define VR9_PCE_TCM_EBS_EBS_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Three-color MarkerInstantaneous Burst Size Register' */ ++/* Bit: 'IBS' */ ++/* Description: 'Instantaneous Burst Size' */ ++#define VR9_PCE_TCM_IBS_IBS_OFFSET 0x584 ++#define VR9_PCE_TCM_IBS_IBS_SHIFT 0 ++#define VR9_PCE_TCM_IBS_IBS_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Three-colorMarker Constant Information Rate Mantissa Register' */ ++/* Bit: 'MANT' */ ++/* Description: 'Rate Counter Mantissa' */ ++#define VR9_PCE_TCM_CIR_MANT_MANT_OFFSET 0x585 ++#define VR9_PCE_TCM_CIR_MANT_MANT_SHIFT 0 ++#define VR9_PCE_TCM_CIR_MANT_MANT_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Three-colorMarker Constant Information Rate Exponent Register' */ ++/* Bit: 'EXP' */ ++/* Description: 'Rate Counter Exponent' */ ++#define VR9_PCE_TCM_CIR_EXP_EXP_OFFSET 0x586 ++#define VR9_PCE_TCM_CIR_EXP_EXP_SHIFT 0 ++#define VR9_PCE_TCM_CIR_EXP_EXP_SIZE 4 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MAC Test Register' */ ++/* Bit: 'JTP' */ ++/* Description: 'Jitter Test Pattern' */ ++#define VR9_MAC_TEST_JTP_OFFSET 0x8C0 ++#define VR9_MAC_TEST_JTP_SHIFT 0 ++#define VR9_MAC_TEST_JTP_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MAC Pause FrameSource Address Configuration Register' */ ++/* Bit: 'SAMOD' */ ++/* Description: 'Source Address Mode' */ ++#define VR9_MAC_PFAD_CFG_SAMOD_OFFSET 0x8C1 ++#define VR9_MAC_PFAD_CFG_SAMOD_SHIFT 0 ++#define VR9_MAC_PFAD_CFG_SAMOD_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Pause Frame SourceAddress Part 0 ' */ ++/* Bit: 'PFAD' */ ++/* Description: 'Pause Frame Source Address Part 0' */ ++#define VR9_MAC_PFSA_0_PFAD_OFFSET 0x8C2 ++#define VR9_MAC_PFSA_0_PFAD_SHIFT 0 ++#define VR9_MAC_PFSA_0_PFAD_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Pause Frame SourceAddress Part 1 ' */ ++/* Bit: 'PFAD' */ ++/* Description: 'Pause Frame Source Address Part 1' */ ++#define VR9_MAC_PFSA_1_PFAD_OFFSET 0x8C3 ++#define VR9_MAC_PFSA_1_PFAD_SHIFT 0 ++#define VR9_MAC_PFSA_1_PFAD_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Pause Frame SourceAddress Part 2 ' */ ++/* Bit: 'PFAD' */ ++/* Description: 'Pause Frame Source Address Part 2' */ ++#define VR9_MAC_PFSA_2_PFAD_OFFSET 0x8C4 ++#define VR9_MAC_PFSA_2_PFAD_SHIFT 0 ++#define VR9_MAC_PFSA_2_PFAD_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MAC Frame Length Register' */ ++/* Bit: 'LEN' */ ++/* Description: 'Maximum Frame Length' */ ++#define VR9_MAC_FLEN_LEN_OFFSET 0x8C5 ++#define VR9_MAC_FLEN_LEN_SHIFT 0 ++#define VR9_MAC_FLEN_LEN_SIZE 14 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MAC VLAN EthertypeRegister 0' */ ++/* Bit: 'OUTER' */ ++/* Description: 'Ethertype' */ ++#define VR9_MAC_VLAN_ETYPE_0_OUTER_OFFSET 0x8C6 ++#define VR9_MAC_VLAN_ETYPE_0_OUTER_SHIFT 0 ++#define VR9_MAC_VLAN_ETYPE_0_OUTER_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MAC VLAN EthertypeRegister 1' */ ++/* Bit: 'INNER' */ ++/* Description: 'Ethertype' */ ++#define VR9_MAC_VLAN_ETYPE_1_INNER_OFFSET 0x8C7 ++#define VR9_MAC_VLAN_ETYPE_1_INNER_SHIFT 0 ++#define VR9_MAC_VLAN_ETYPE_1_INNER_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MAC Interrupt EnableRegister' */ ++/* Bit: 'MACIEN' */ ++/* Description: 'MAC Interrupt Enable' */ ++#define VR9_MAC_IER_MACIEN_OFFSET 0x8C8 ++#define VR9_MAC_IER_MACIEN_SHIFT 0 ++#define VR9_MAC_IER_MACIEN_SIZE 13 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MAC Interrupt StatusRegister' */ ++/* Bit: 'MACINT' */ ++/* Description: 'MAC Interrupt' */ ++#define VR9_MAC_ISR_MACINT_OFFSET 0x8C9 ++#define VR9_MAC_ISR_MACINT_SHIFT 0 ++#define VR9_MAC_ISR_MACINT_SIZE 13 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MAC Port Status Register' */ ++/* Bit: 'PACT' */ ++/* Description: 'PHY Active Status' */ ++#define VR9_MAC_PSTAT_PACT_OFFSET 0x900 ++#define VR9_MAC_PSTAT_PACT_SHIFT 11 ++#define VR9_MAC_PSTAT_PACT_SIZE 1 ++/* Bit: 'GBIT' */ ++/* Description: 'Gigabit Speed Status' */ ++#define VR9_MAC_PSTAT_GBIT_OFFSET 0x900 ++#define VR9_MAC_PSTAT_GBIT_SHIFT 10 ++#define VR9_MAC_PSTAT_GBIT_SIZE 1 ++/* Bit: 'MBIT' */ ++/* Description: 'Megabit Speed Status' */ ++#define VR9_MAC_PSTAT_MBIT_OFFSET 0x900 ++#define VR9_MAC_PSTAT_MBIT_SHIFT 9 ++#define VR9_MAC_PSTAT_MBIT_SIZE 1 ++/* Bit: 'FDUP' */ ++/* Description: 'Full Duplex Status' */ ++#define VR9_MAC_PSTAT_FDUP_OFFSET 0x900 ++#define VR9_MAC_PSTAT_FDUP_SHIFT 8 ++#define VR9_MAC_PSTAT_FDUP_SIZE 1 ++/* Bit: 'RXPAU' */ ++/* Description: 'Receive Pause Status' */ ++#define VR9_MAC_PSTAT_RXPAU_OFFSET 0x900 ++#define VR9_MAC_PSTAT_RXPAU_SHIFT 7 ++#define VR9_MAC_PSTAT_RXPAU_SIZE 1 ++/* Bit: 'TXPAU' */ ++/* Description: 'Transmit Pause Status' */ ++#define VR9_MAC_PSTAT_TXPAU_OFFSET 0x900 ++#define VR9_MAC_PSTAT_TXPAU_SHIFT 6 ++#define VR9_MAC_PSTAT_TXPAU_SIZE 1 ++/* Bit: 'RXPAUEN' */ ++/* Description: 'Receive Pause Enable Status' */ ++#define VR9_MAC_PSTAT_RXPAUEN_OFFSET 0x900 ++#define VR9_MAC_PSTAT_RXPAUEN_SHIFT 5 ++#define VR9_MAC_PSTAT_RXPAUEN_SIZE 1 ++/* Bit: 'TXPAUEN' */ ++/* Description: 'Transmit Pause Enable Status' */ ++#define VR9_MAC_PSTAT_TXPAUEN_OFFSET 0x900 ++#define VR9_MAC_PSTAT_TXPAUEN_SHIFT 4 ++#define VR9_MAC_PSTAT_TXPAUEN_SIZE 1 ++/* Bit: 'LSTAT' */ ++/* Description: 'Link Status' */ ++#define VR9_MAC_PSTAT_LSTAT_OFFSET 0x900 ++#define VR9_MAC_PSTAT_LSTAT_SHIFT 3 ++#define VR9_MAC_PSTAT_LSTAT_SIZE 1 ++/* Bit: 'CRS' */ ++/* Description: 'Carrier Sense Status' */ ++#define VR9_MAC_PSTAT_CRS_OFFSET 0x900 ++#define VR9_MAC_PSTAT_CRS_SHIFT 2 ++#define VR9_MAC_PSTAT_CRS_SIZE 1 ++/* Bit: 'TXLPI' */ ++/* Description: 'Transmit Low-power Idle Status' */ ++#define VR9_MAC_PSTAT_TXLPI_OFFSET 0x900 ++#define VR9_MAC_PSTAT_TXLPI_SHIFT 1 ++#define VR9_MAC_PSTAT_TXLPI_SIZE 1 ++/* Bit: 'RXLPI' */ ++/* Description: 'Receive Low-power Idle Status' */ ++#define VR9_MAC_PSTAT_RXLPI_OFFSET 0x900 ++#define VR9_MAC_PSTAT_RXLPI_SHIFT 0 ++#define VR9_MAC_PSTAT_RXLPI_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MAC Interrupt Status Register' */ ++/* Bit: 'PHYERR' */ ++/* Description: 'PHY Error Interrupt' */ ++#define VR9_MAC_PISR_PHYERR_OFFSET 0x901 ++#define VR9_MAC_PISR_PHYERR_SHIFT 15 ++#define VR9_MAC_PISR_PHYERR_SIZE 1 ++/* Bit: 'ALIGN' */ ++/* Description: 'Allignment Error Interrupt' */ ++#define VR9_MAC_PISR_ALIGN_OFFSET 0x901 ++#define VR9_MAC_PISR_ALIGN_SHIFT 14 ++#define VR9_MAC_PISR_ALIGN_SIZE 1 ++/* Bit: 'PACT' */ ++/* Description: 'PHY Active Status' */ ++#define VR9_MAC_PISR_PACT_OFFSET 0x901 ++#define VR9_MAC_PISR_PACT_SHIFT 13 ++#define VR9_MAC_PISR_PACT_SIZE 1 ++/* Bit: 'SPEED' */ ++/* Description: 'Megabit Speed Status' */ ++#define VR9_MAC_PISR_SPEED_OFFSET 0x901 ++#define VR9_MAC_PISR_SPEED_SHIFT 12 ++#define VR9_MAC_PISR_SPEED_SIZE 1 ++/* Bit: 'FDUP' */ ++/* Description: 'Full Duplex Status' */ ++#define VR9_MAC_PISR_FDUP_OFFSET 0x901 ++#define VR9_MAC_PISR_FDUP_SHIFT 11 ++#define VR9_MAC_PISR_FDUP_SIZE 1 ++/* Bit: 'RXPAUEN' */ ++/* Description: 'Receive Pause Enable Status' */ ++#define VR9_MAC_PISR_RXPAUEN_OFFSET 0x901 ++#define VR9_MAC_PISR_RXPAUEN_SHIFT 10 ++#define VR9_MAC_PISR_RXPAUEN_SIZE 1 ++/* Bit: 'TXPAUEN' */ ++/* Description: 'Transmit Pause Enable Status' */ ++#define VR9_MAC_PISR_TXPAUEN_OFFSET 0x901 ++#define VR9_MAC_PISR_TXPAUEN_SHIFT 9 ++#define VR9_MAC_PISR_TXPAUEN_SIZE 1 ++/* Bit: 'LPIOFF' */ ++/* Description: 'Receive Low-power Idle Mode is left' */ ++#define VR9_MAC_PISR_LPIOFF_OFFSET 0x901 ++#define VR9_MAC_PISR_LPIOFF_SHIFT 8 ++#define VR9_MAC_PISR_LPIOFF_SIZE 1 ++/* Bit: 'LPION' */ ++/* Description: 'Receive Low-power Idle Mode is entered' */ ++#define VR9_MAC_PISR_LPION_OFFSET 0x901 ++#define VR9_MAC_PISR_LPION_SHIFT 7 ++#define VR9_MAC_PISR_LPION_SIZE 1 ++/* Bit: 'JAM' */ ++/* Description: 'Jam Status Detected' */ ++#define VR9_MAC_PISR_JAM_OFFSET 0x901 ++#define VR9_MAC_PISR_JAM_SHIFT 6 ++#define VR9_MAC_PISR_JAM_SIZE 1 ++/* Bit: 'TOOSHORT' */ ++/* Description: 'Too Short Frame Error Detected' */ ++#define VR9_MAC_PISR_TOOSHORT_OFFSET 0x901 ++#define VR9_MAC_PISR_TOOSHORT_SHIFT 5 ++#define VR9_MAC_PISR_TOOSHORT_SIZE 1 ++/* Bit: 'TOOLONG' */ ++/* Description: 'Too Long Frame Error Detected' */ ++#define VR9_MAC_PISR_TOOLONG_OFFSET 0x901 ++#define VR9_MAC_PISR_TOOLONG_SHIFT 4 ++#define VR9_MAC_PISR_TOOLONG_SIZE 1 ++/* Bit: 'LENERR' */ ++/* Description: 'Length Mismatch Error Detected' */ ++#define VR9_MAC_PISR_LENERR_OFFSET 0x901 ++#define VR9_MAC_PISR_LENERR_SHIFT 3 ++#define VR9_MAC_PISR_LENERR_SIZE 1 ++/* Bit: 'FCSERR' */ ++/* Description: 'Frame Checksum Error Detected' */ ++#define VR9_MAC_PISR_FCSERR_OFFSET 0x901 ++#define VR9_MAC_PISR_FCSERR_SHIFT 2 ++#define VR9_MAC_PISR_FCSERR_SIZE 1 ++/* Bit: 'TXPAUSE' */ ++/* Description: 'Pause Frame Transmitted' */ ++#define VR9_MAC_PISR_TXPAUSE_OFFSET 0x901 ++#define VR9_MAC_PISR_TXPAUSE_SHIFT 1 ++#define VR9_MAC_PISR_TXPAUSE_SIZE 1 ++/* Bit: 'RXPAUSE' */ ++/* Description: 'Pause Frame Received' */ ++#define VR9_MAC_PISR_RXPAUSE_OFFSET 0x901 ++#define VR9_MAC_PISR_RXPAUSE_SHIFT 0 ++#define VR9_MAC_PISR_RXPAUSE_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MAC Interrupt Enable Register' */ ++/* Bit: 'PHYERR' */ ++/* Description: 'PHY Error Interrupt' */ ++#define VR9_MAC_PIER_PHYERR_OFFSET 0x902 ++#define VR9_MAC_PIER_PHYERR_SHIFT 15 ++#define VR9_MAC_PIER_PHYERR_SIZE 1 ++/* Bit: 'ALIGN' */ ++/* Description: 'Allignment Error Interrupt' */ ++#define VR9_MAC_PIER_ALIGN_OFFSET 0x902 ++#define VR9_MAC_PIER_ALIGN_SHIFT 14 ++#define VR9_MAC_PIER_ALIGN_SIZE 1 ++/* Bit: 'PACT' */ ++/* Description: 'PHY Active Status' */ ++#define VR9_MAC_PIER_PACT_OFFSET 0x902 ++#define VR9_MAC_PIER_PACT_SHIFT 13 ++#define VR9_MAC_PIER_PACT_SIZE 1 ++/* Bit: 'SPEED' */ ++/* Description: 'Megabit Speed Status' */ ++#define VR9_MAC_PIER_SPEED_OFFSET 0x902 ++#define VR9_MAC_PIER_SPEED_SHIFT 12 ++#define VR9_MAC_PIER_SPEED_SIZE 1 ++/* Bit: 'FDUP' */ ++/* Description: 'Full Duplex Status' */ ++#define VR9_MAC_PIER_FDUP_OFFSET 0x902 ++#define VR9_MAC_PIER_FDUP_SHIFT 11 ++#define VR9_MAC_PIER_FDUP_SIZE 1 ++/* Bit: 'RXPAUEN' */ ++/* Description: 'Receive Pause Enable Status' */ ++#define VR9_MAC_PIER_RXPAUEN_OFFSET 0x902 ++#define VR9_MAC_PIER_RXPAUEN_SHIFT 10 ++#define VR9_MAC_PIER_RXPAUEN_SIZE 1 ++/* Bit: 'TXPAUEN' */ ++/* Description: 'Transmit Pause Enable Status' */ ++#define VR9_MAC_PIER_TXPAUEN_OFFSET 0x902 ++#define VR9_MAC_PIER_TXPAUEN_SHIFT 9 ++#define VR9_MAC_PIER_TXPAUEN_SIZE 1 ++/* Bit: 'LPIOFF' */ ++/* Description: 'Low-power Idle Off Interrupt Mask' */ ++#define VR9_MAC_PIER_LPIOFF_OFFSET 0x902 ++#define VR9_MAC_PIER_LPIOFF_SHIFT 8 ++#define VR9_MAC_PIER_LPIOFF_SIZE 1 ++/* Bit: 'LPION' */ ++/* Description: 'Low-power Idle On Interrupt Mask' */ ++#define VR9_MAC_PIER_LPION_OFFSET 0x902 ++#define VR9_MAC_PIER_LPION_SHIFT 7 ++#define VR9_MAC_PIER_LPION_SIZE 1 ++/* Bit: 'JAM' */ ++/* Description: 'Jam Status Interrupt Mask' */ ++#define VR9_MAC_PIER_JAM_OFFSET 0x902 ++#define VR9_MAC_PIER_JAM_SHIFT 6 ++#define VR9_MAC_PIER_JAM_SIZE 1 ++/* Bit: 'TOOSHORT' */ ++/* Description: 'Too Short Frame Error Interrupt Mask' */ ++#define VR9_MAC_PIER_TOOSHORT_OFFSET 0x902 ++#define VR9_MAC_PIER_TOOSHORT_SHIFT 5 ++#define VR9_MAC_PIER_TOOSHORT_SIZE 1 ++/* Bit: 'TOOLONG' */ ++/* Description: 'Too Long Frame Error Interrupt Mask' */ ++#define VR9_MAC_PIER_TOOLONG_OFFSET 0x902 ++#define VR9_MAC_PIER_TOOLONG_SHIFT 4 ++#define VR9_MAC_PIER_TOOLONG_SIZE 1 ++/* Bit: 'LENERR' */ ++/* Description: 'Length Mismatch Error Interrupt Mask' */ ++#define VR9_MAC_PIER_LENERR_OFFSET 0x902 ++#define VR9_MAC_PIER_LENERR_SHIFT 3 ++#define VR9_MAC_PIER_LENERR_SIZE 1 ++/* Bit: 'FCSERR' */ ++/* Description: 'Frame Checksum Error Interrupt Mask' */ ++#define VR9_MAC_PIER_FCSERR_OFFSET 0x902 ++#define VR9_MAC_PIER_FCSERR_SHIFT 2 ++#define VR9_MAC_PIER_FCSERR_SIZE 1 ++/* Bit: 'TXPAUSE' */ ++/* Description: 'Transmit Pause Frame Interrupt Mask' */ ++#define VR9_MAC_PIER_TXPAUSE_OFFSET 0x902 ++#define VR9_MAC_PIER_TXPAUSE_SHIFT 1 ++#define VR9_MAC_PIER_TXPAUSE_SIZE 1 ++/* Bit: 'RXPAUSE' */ ++/* Description: 'Receive Pause Frame Interrupt Mask' */ ++#define VR9_MAC_PIER_RXPAUSE_OFFSET 0x902 ++#define VR9_MAC_PIER_RXPAUSE_SHIFT 0 ++#define VR9_MAC_PIER_RXPAUSE_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MAC Control Register0' */ ++/* Bit: 'BM' */ ++/* Description: 'Burst Mode Control' */ ++#define VR9_MAC_CTRL_0_BM_OFFSET 0x903 ++#define VR9_MAC_CTRL_0_BM_SHIFT 12 ++#define VR9_MAC_CTRL_0_BM_SIZE 1 ++/* Bit: 'APADEN' */ ++/* Description: 'Automatic VLAN Padding Enable' */ ++#define VR9_MAC_CTRL_0_APADEN_OFFSET 0x903 ++#define VR9_MAC_CTRL_0_APADEN_SHIFT 11 ++#define VR9_MAC_CTRL_0_APADEN_SIZE 1 ++/* Bit: 'VPAD2EN' */ ++/* Description: 'Stacked VLAN Padding Enable' */ ++#define VR9_MAC_CTRL_0_VPAD2EN_OFFSET 0x903 ++#define VR9_MAC_CTRL_0_VPAD2EN_SHIFT 10 ++#define VR9_MAC_CTRL_0_VPAD2EN_SIZE 1 ++/* Bit: 'VPADEN' */ ++/* Description: 'VLAN Padding Enable' */ ++#define VR9_MAC_CTRL_0_VPADEN_OFFSET 0x903 ++#define VR9_MAC_CTRL_0_VPADEN_SHIFT 9 ++#define VR9_MAC_CTRL_0_VPADEN_SIZE 1 ++/* Bit: 'PADEN' */ ++/* Description: 'Padding Enable' */ ++#define VR9_MAC_CTRL_0_PADEN_OFFSET 0x903 ++#define VR9_MAC_CTRL_0_PADEN_SHIFT 8 ++#define VR9_MAC_CTRL_0_PADEN_SIZE 1 ++/* Bit: 'FCS' */ ++/* Description: 'Transmit FCS Control' */ ++#define VR9_MAC_CTRL_0_FCS_OFFSET 0x903 ++#define VR9_MAC_CTRL_0_FCS_SHIFT 7 ++#define VR9_MAC_CTRL_0_FCS_SIZE 1 ++/* Bit: 'FCON' */ ++/* Description: 'Flow Control Mode' */ ++#define VR9_MAC_CTRL_0_FCON_OFFSET 0x903 ++#define VR9_MAC_CTRL_0_FCON_SHIFT 4 ++#define VR9_MAC_CTRL_0_FCON_SIZE 3 ++/* Bit: 'FDUP' */ ++/* Description: 'Full Duplex Control' */ ++#define VR9_MAC_CTRL_0_FDUP_OFFSET 0x903 ++#define VR9_MAC_CTRL_0_FDUP_SHIFT 2 ++#define VR9_MAC_CTRL_0_FDUP_SIZE 2 ++/* Bit: 'GMII' */ ++/* Description: 'GMII/MII interface mode selection' */ ++#define VR9_MAC_CTRL_0_GMII_OFFSET 0x903 ++#define VR9_MAC_CTRL_0_GMII_SHIFT 0 ++#define VR9_MAC_CTRL_0_GMII_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MAC Control Register1' */ ++/* Bit: 'DEFERMODE' */ ++/* Description: 'Defer Model' */ ++#define VR9_MAC_CTRL_1_DEFERMODE_OFFSET 0x904 ++#define VR9_MAC_CTRL_1_DEFERMODE_SHIFT 15 ++#define VR9_MAC_CTRL_1_DEFERMODE_SIZE 1 ++/* Bit: 'SHORTPRE' */ ++/* Description: 'Short Preamble Control' */ ++#define VR9_MAC_CTRL_1_SHORTPRE_OFFSET 0x904 ++#define VR9_MAC_CTRL_1_SHORTPRE_SHIFT 8 ++#define VR9_MAC_CTRL_1_SHORTPRE_SIZE 1 ++/* Bit: 'IPG' */ ++/* Description: 'Minimum Inter Packet Gap Size' */ ++#define VR9_MAC_CTRL_1_IPG_OFFSET 0x904 ++#define VR9_MAC_CTRL_1_IPG_SHIFT 0 ++#define VR9_MAC_CTRL_1_IPG_SIZE 4 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MAC Control Register2' */ ++/* Bit: 'MLEN' */ ++/* Description: 'Maximum Untagged Frame Length' */ ++#define VR9_MAC_CTRL_2_MLEN_OFFSET 0x905 ++#define VR9_MAC_CTRL_2_MLEN_SHIFT 3 ++#define VR9_MAC_CTRL_2_MLEN_SIZE 1 ++/* Bit: 'LCHKL' */ ++/* Description: 'Frame Length Check Long Enable' */ ++#define VR9_MAC_CTRL_2_LCHKL_OFFSET 0x905 ++#define VR9_MAC_CTRL_2_LCHKL_SHIFT 2 ++#define VR9_MAC_CTRL_2_LCHKL_SIZE 1 ++/* Bit: 'LCHKS' */ ++/* Description: 'Frame Length Check Short Enable' */ ++#define VR9_MAC_CTRL_2_LCHKS_OFFSET 0x905 ++#define VR9_MAC_CTRL_2_LCHKS_SHIFT 0 ++#define VR9_MAC_CTRL_2_LCHKS_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MAC Control Register3' */ ++/* Bit: 'RCNT' */ ++/* Description: 'Retry Count' */ ++#define VR9_MAC_CTRL_3_RCNT_OFFSET 0x906 ++#define VR9_MAC_CTRL_3_RCNT_SHIFT 0 ++#define VR9_MAC_CTRL_3_RCNT_SIZE 4 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MAC Control Register4' */ ++/* Bit: 'GWAIT' */ ++/* Description: 'LPI Wait Time for 1G' */ ++#define VR9_MAC_CTRL_4_GWAIT_OFFSET 0x907 ++#define VR9_MAC_CTRL_4_GWAIT_SHIFT 8 ++#define VR9_MAC_CTRL_4_GWAIT_SIZE 7 ++/* Bit: 'LPIEN' */ ++/* Description: 'LPI Mode Enable' */ ++#define VR9_MAC_CTRL_4_LPIEN_OFFSET 0x907 ++#define VR9_MAC_CTRL_4_LPIEN_SHIFT 7 ++#define VR9_MAC_CTRL_4_LPIEN_SIZE 1 ++/* Bit: 'WAIT' */ ++/* Description: 'LPI Wait Time for 100M' */ ++#define VR9_MAC_CTRL_4_WAIT_OFFSET 0x907 ++#define VR9_MAC_CTRL_4_WAIT_SHIFT 0 ++#define VR9_MAC_CTRL_4_WAIT_SIZE 7 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MAC Control Register5' */ ++/* Bit: 'PJPS_NOBP' */ ++/* Description: 'Prolonged Jam pattern size during no-backpressure ++state' */ ++#define VR9_MAC_CTRL_5_PJPS_NOBP_OFFSET 0x908 ++#define VR9_MAC_CTRL_5_PJPS_NOBP_SHIFT 1 ++#define VR9_MAC_CTRL_5_PJPS_NOBP_SIZE 1 ++/* Bit: 'PJPS_BP' */ ++/* Description: 'Prolonged Jam pattern size during backpressure state' */ ++#define VR9_MAC_CTRL_5_PJPS_BP_OFFSET 0x908 ++#define VR9_MAC_CTRL_5_PJPS_BP_SHIFT 0 ++#define VR9_MAC_CTRL_5_PJPS_BP_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MAC Test Enable Register' */ ++/* Bit: 'JTEN' */ ++/* Description: 'Jitter Test Enable' */ ++#define VR9_MAC_TESTEN_JTEN_OFFSET 0x90B ++#define VR9_MAC_TESTEN_JTEN_SHIFT 2 ++#define VR9_MAC_TESTEN_JTEN_SIZE 1 ++/* Bit: 'TXER' */ ++/* Description: 'Transmit Error Insertion' */ ++#define VR9_MAC_TESTEN_TXER_OFFSET 0x90B ++#define VR9_MAC_TESTEN_TXER_SHIFT 1 ++#define VR9_MAC_TESTEN_TXER_SIZE 1 ++/* Bit: 'LOOP' */ ++/* Description: 'MAC Loopback Enable' */ ++#define VR9_MAC_TESTEN_LOOP_OFFSET 0x90B ++#define VR9_MAC_TESTEN_LOOP_SHIFT 0 ++#define VR9_MAC_TESTEN_LOOP_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet Switch FetchDMA Control Register' */ ++/* Bit: 'EGCNT' */ ++/* Description: 'Egress Special Tag RMON count' */ ++#define VR9_FDMA_CTRL_EGCNT_OFFSET 0xA40 ++#define VR9_FDMA_CTRL_EGCNT_SHIFT 7 ++#define VR9_FDMA_CTRL_EGCNT_SIZE 1 ++/* Bit: 'LPI_MODE' */ ++/* Description: 'Low Power Idle Mode' */ ++#define VR9_FDMA_CTRL_LPI_MODE_OFFSET 0xA40 ++#define VR9_FDMA_CTRL_LPI_MODE_SHIFT 4 ++#define VR9_FDMA_CTRL_LPI_MODE_SIZE 3 ++/* Bit: 'EGSTAG' */ ++/* Description: 'Egress Special Tag Size' */ ++#define VR9_FDMA_CTRL_EGSTAG_OFFSET 0xA40 ++#define VR9_FDMA_CTRL_EGSTAG_SHIFT 2 ++#define VR9_FDMA_CTRL_EGSTAG_SIZE 2 ++/* Bit: 'IGSTAG' */ ++/* Description: 'Ingress Special Tag Size' */ ++#define VR9_FDMA_CTRL_IGSTAG_OFFSET 0xA40 ++#define VR9_FDMA_CTRL_IGSTAG_SHIFT 1 ++#define VR9_FDMA_CTRL_IGSTAG_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Special Tag EthertypeControl Register' */ ++/* Bit: 'ETYPE' */ ++/* Description: 'Special Tag Ethertype' */ ++#define VR9_FDMA_STETYPE_ETYPE_OFFSET 0xA41 ++#define VR9_FDMA_STETYPE_ETYPE_SHIFT 0 ++#define VR9_FDMA_STETYPE_ETYPE_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'VLAN Tag EthertypeControl Register' */ ++/* Bit: 'ETYPE' */ ++/* Description: 'VLAN Tag Ethertype' */ ++#define VR9_FDMA_VTETYPE_ETYPE_OFFSET 0xA42 ++#define VR9_FDMA_VTETYPE_ETYPE_SHIFT 0 ++#define VR9_FDMA_VTETYPE_ETYPE_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'FDMA Status Register0' */ ++/* Bit: 'FSMS' */ ++/* Description: 'FSM states status' */ ++#define VR9_FDMA_STAT_0_FSMS_OFFSET 0xA43 ++#define VR9_FDMA_STAT_0_FSMS_SHIFT 0 ++#define VR9_FDMA_STAT_0_FSMS_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Fetch DMA Global InterruptEnable Register' */ ++/* Bit: 'PCKD' */ ++/* Description: 'Packet Drop Interrupt Enable' */ ++#define VR9_FDMA_IER_PCKD_OFFSET 0xA44 ++#define VR9_FDMA_IER_PCKD_SHIFT 14 ++#define VR9_FDMA_IER_PCKD_SIZE 1 ++/* Bit: 'PCKR' */ ++/* Description: 'Packet Ready Interrupt Enable' */ ++#define VR9_FDMA_IER_PCKR_OFFSET 0xA44 ++#define VR9_FDMA_IER_PCKR_SHIFT 13 ++#define VR9_FDMA_IER_PCKR_SIZE 1 ++/* Bit: 'PCKT' */ ++/* Description: 'Packet Sent Interrupt Enable' */ ++#define VR9_FDMA_IER_PCKT_OFFSET 0xA44 ++#define VR9_FDMA_IER_PCKT_SHIFT 0 ++#define VR9_FDMA_IER_PCKT_SIZE 13 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Fetch DMA Global InterruptStatus Register' */ ++/* Bit: 'PCKTD' */ ++/* Description: 'Packet Drop' */ ++#define VR9_FDMA_ISR_PCKTD_OFFSET 0xA45 ++#define VR9_FDMA_ISR_PCKTD_SHIFT 14 ++#define VR9_FDMA_ISR_PCKTD_SIZE 1 ++/* Bit: 'PCKR' */ ++/* Description: 'Packet is Ready for Transmission' */ ++#define VR9_FDMA_ISR_PCKR_OFFSET 0xA45 ++#define VR9_FDMA_ISR_PCKR_SHIFT 13 ++#define VR9_FDMA_ISR_PCKR_SIZE 1 ++/* Bit: 'PCKT' */ ++/* Description: 'Packet Sent Event' */ ++#define VR9_FDMA_ISR_PCKT_OFFSET 0xA45 ++#define VR9_FDMA_ISR_PCKT_SHIFT 0 ++#define VR9_FDMA_ISR_PCKT_SIZE 13 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet SwitchFetch DMA Port Control Register' */ ++/* Bit: 'ST_TYPE' */ ++/* Description: 'Special Tag Ethertype Mode' */ ++#define VR9_FDMA_PCTRL_ST_TYPE_OFFSET 0xA80 ++#define VR9_FDMA_PCTRL_ST_TYPE_SHIFT 5 ++#define VR9_FDMA_PCTRL_ST_TYPE_SIZE 1 ++/* Bit: 'VLANMOD' */ ++/* Description: 'VLAN Modification Control' */ ++#define VR9_FDMA_PCTRL_VLANMOD_OFFSET 0xA80 ++#define VR9_FDMA_PCTRL_VLANMOD_SHIFT 3 ++#define VR9_FDMA_PCTRL_VLANMOD_SIZE 2 ++/* Bit: 'DSCPRM' */ ++/* Description: 'DSCP Re-marking Enable' */ ++#define VR9_FDMA_PCTRL_DSCPRM_OFFSET 0xA80 ++#define VR9_FDMA_PCTRL_DSCPRM_SHIFT 2 ++#define VR9_FDMA_PCTRL_DSCPRM_SIZE 1 ++/* Bit: 'STEN' */ ++/* Description: 'Special Tag Insertion Enable' */ ++#define VR9_FDMA_PCTRL_STEN_OFFSET 0xA80 ++#define VR9_FDMA_PCTRL_STEN_SHIFT 1 ++#define VR9_FDMA_PCTRL_STEN_SIZE 1 ++/* Bit: 'EN' */ ++/* Description: 'FDMA Port Enable' */ ++#define VR9_FDMA_PCTRL_EN_OFFSET 0xA80 ++#define VR9_FDMA_PCTRL_EN_SHIFT 0 ++#define VR9_FDMA_PCTRL_EN_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet SwitchFetch DMA Port Priority Register' */ ++/* Bit: 'PRIO' */ ++/* Description: 'FDMA PRIO' */ ++#define VR9_FDMA_PRIO_PRIO_OFFSET 0xA81 ++#define VR9_FDMA_PRIO_PRIO_SHIFT 0 ++#define VR9_FDMA_PRIO_PRIO_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet SwitchFetch DMA Port Status Register 0' */ ++/* Bit: 'PKT_AVAIL' */ ++/* Description: 'Port Egress Packet Available' */ ++#define VR9_FDMA_PSTAT0_PKT_AVAIL_OFFSET 0xA82 ++#define VR9_FDMA_PSTAT0_PKT_AVAIL_SHIFT 15 ++#define VR9_FDMA_PSTAT0_PKT_AVAIL_SIZE 1 ++/* Bit: 'POK' */ ++/* Description: 'Port Status OK' */ ++#define VR9_FDMA_PSTAT0_POK_OFFSET 0xA82 ++#define VR9_FDMA_PSTAT0_POK_SHIFT 14 ++#define VR9_FDMA_PSTAT0_POK_SIZE 1 ++/* Bit: 'PSEG' */ ++/* Description: 'Port Egress Segment Count' */ ++#define VR9_FDMA_PSTAT0_PSEG_OFFSET 0xA82 ++#define VR9_FDMA_PSTAT0_PSEG_SHIFT 0 ++#define VR9_FDMA_PSTAT0_PSEG_SIZE 6 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet SwitchFetch DMA Port Status Register 1' */ ++/* Bit: 'HDR_PTR' */ ++/* Description: 'Header Pointer' */ ++#define VR9_FDMA_PSTAT1_HDR_PTR_OFFSET 0xA83 ++#define VR9_FDMA_PSTAT1_HDR_PTR_SHIFT 0 ++#define VR9_FDMA_PSTAT1_HDR_PTR_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Egress TimeStamp Register 0' */ ++/* Bit: 'TSTL' */ ++/* Description: 'Time Stamp [15:0]' */ ++#define VR9_FDMA_TSTAMP0_TSTL_OFFSET 0xA84 ++#define VR9_FDMA_TSTAMP0_TSTL_SHIFT 0 ++#define VR9_FDMA_TSTAMP0_TSTL_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Egress TimeStamp Register 1' */ ++/* Bit: 'TSTH' */ ++/* Description: 'Time Stamp [31:16]' */ ++#define VR9_FDMA_TSTAMP1_TSTH_OFFSET 0xA85 ++#define VR9_FDMA_TSTAMP1_TSTH_SHIFT 0 ++#define VR9_FDMA_TSTAMP1_TSTH_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet Switch StoreDMA Control Register' */ ++/* Bit: 'RMON_ALIGN' */ ++/* Description: 'MUX to select what to count on align error rmon ++counter' */ ++#define VR9_SDMA_CTRL_RMON_ALIGN_OFFSET 0xB40 ++#define VR9_SDMA_CTRL_RMON_ALIGN_SHIFT 2 ++#define VR9_SDMA_CTRL_RMON_ALIGN_SIZE 2 ++/* Bit: 'ARBIT' */ ++/* Description: 'SIMPLE ARBITER FOR PARSER FILLING' */ ++#define VR9_SDMA_CTRL_ARBIT_OFFSET 0xB40 ++#define VR9_SDMA_CTRL_ARBIT_SHIFT 1 ++#define VR9_SDMA_CTRL_ARBIT_SIZE 1 ++/* Bit: 'TSTEN' */ ++/* Description: 'Time Stamp Enable' */ ++#define VR9_SDMA_CTRL_TSTEN_OFFSET 0xB40 ++#define VR9_SDMA_CTRL_TSTEN_SHIFT 0 ++#define VR9_SDMA_CTRL_TSTEN_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'SDMA Flow Control Threshold1 Register' */ ++/* Bit: 'THR1' */ ++/* Description: 'Threshold 1' */ ++#define VR9_SDMA_FCTHR1_THR1_OFFSET 0xB41 ++#define VR9_SDMA_FCTHR1_THR1_SHIFT 0 ++#define VR9_SDMA_FCTHR1_THR1_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'SDMA Flow Control Threshold2 Register' */ ++/* Bit: 'THR2' */ ++/* Description: 'Threshold 2' */ ++#define VR9_SDMA_FCTHR2_THR2_OFFSET 0xB42 ++#define VR9_SDMA_FCTHR2_THR2_SHIFT 0 ++#define VR9_SDMA_FCTHR2_THR2_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'SDMA Flow Control Threshold3 Register' */ ++/* Bit: 'THR3' */ ++/* Description: 'Threshold 3' */ ++#define VR9_SDMA_FCTHR3_THR3_OFFSET 0xB43 ++#define VR9_SDMA_FCTHR3_THR3_SHIFT 0 ++#define VR9_SDMA_FCTHR3_THR3_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'SDMA Flow Control Threshold4 Register' */ ++/* Bit: 'THR4' */ ++/* Description: 'Threshold 4' */ ++#define VR9_SDMA_FCTHR4_THR4_OFFSET 0xB44 ++#define VR9_SDMA_FCTHR4_THR4_SHIFT 0 ++#define VR9_SDMA_FCTHR4_THR4_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'SDMA Flow Control Threshold5 Register' */ ++/* Bit: 'THR5' */ ++/* Description: 'Threshold 5' */ ++#define VR9_SDMA_FCTHR5_THR5_OFFSET 0xB45 ++#define VR9_SDMA_FCTHR5_THR5_SHIFT 0 ++#define VR9_SDMA_FCTHR5_THR5_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'SDMA Flow Control Threshold6 Register' */ ++/* Bit: 'THR6' */ ++/* Description: 'Threshold 6' */ ++#define VR9_SDMA_FCTHR6_THR6_OFFSET 0xB46 ++#define VR9_SDMA_FCTHR6_THR6_SHIFT 0 ++#define VR9_SDMA_FCTHR6_THR6_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'SDMA Flow Control Threshold7 Register' */ ++/* Bit: 'THR7' */ ++/* Description: 'Threshold 7' */ ++#define VR9_SDMA_FCTHR7_THR7_OFFSET 0xB47 ++#define VR9_SDMA_FCTHR7_THR7_SHIFT 0 ++#define VR9_SDMA_FCTHR7_THR7_SIZE 11 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'SDMA Status Register0' */ ++/* Bit: 'BPS_FILL' */ ++/* Description: 'Back Pressure Status' */ ++#define VR9_SDMA_STAT_0_BPS_FILL_OFFSET 0xB48 ++#define VR9_SDMA_STAT_0_BPS_FILL_SHIFT 4 ++#define VR9_SDMA_STAT_0_BPS_FILL_SIZE 3 ++/* Bit: 'BPS_PNT' */ ++/* Description: 'Back Pressure Status' */ ++#define VR9_SDMA_STAT_0_BPS_PNT_OFFSET 0xB48 ++#define VR9_SDMA_STAT_0_BPS_PNT_SHIFT 2 ++#define VR9_SDMA_STAT_0_BPS_PNT_SIZE 2 ++/* Bit: 'DROP' */ ++/* Description: 'Back Pressure Status' */ ++#define VR9_SDMA_STAT_0_DROP_OFFSET 0xB48 ++#define VR9_SDMA_STAT_0_DROP_SHIFT 0 ++#define VR9_SDMA_STAT_0_DROP_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'SDMA Status Register1' */ ++/* Bit: 'FILL' */ ++/* Description: 'Buffer Filling Level' */ ++#define VR9_SDMA_STAT_1_FILL_OFFSET 0xB49 ++#define VR9_SDMA_STAT_1_FILL_SHIFT 0 ++#define VR9_SDMA_STAT_1_FILL_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'SDMA Status Register2' */ ++/* Bit: 'FSMS' */ ++/* Description: 'FSM states status' */ ++#define VR9_SDMA_STAT_2_FSMS_OFFSET 0xB4A ++#define VR9_SDMA_STAT_2_FSMS_SHIFT 0 ++#define VR9_SDMA_STAT_2_FSMS_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'SDMA Interrupt Enable Register' */ ++/* Bit: 'BPEX' */ ++/* Description: 'Buffer Pointers Exceeded' */ ++#define VR9_SDMA_IER_BPEX_OFFSET 0xB4B ++#define VR9_SDMA_IER_BPEX_SHIFT 15 ++#define VR9_SDMA_IER_BPEX_SIZE 1 ++/* Bit: 'BFULL' */ ++/* Description: 'Buffer Full' */ ++#define VR9_SDMA_IER_BFULL_OFFSET 0xB4B ++#define VR9_SDMA_IER_BFULL_SHIFT 14 ++#define VR9_SDMA_IER_BFULL_SIZE 1 ++/* Bit: 'FERR' */ ++/* Description: 'Frame Error' */ ++#define VR9_SDMA_IER_FERR_OFFSET 0xB4B ++#define VR9_SDMA_IER_FERR_SHIFT 13 ++#define VR9_SDMA_IER_FERR_SIZE 1 ++/* Bit: 'FRX' */ ++/* Description: 'Frame Received Successfully' */ ++#define VR9_SDMA_IER_FRX_OFFSET 0xB4B ++#define VR9_SDMA_IER_FRX_SHIFT 0 ++#define VR9_SDMA_IER_FRX_SIZE 13 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'SDMA Interrupt Status Register' */ ++/* Bit: 'BPEX' */ ++/* Description: 'Packet Descriptors Exceeded' */ ++#define VR9_SDMA_ISR_BPEX_OFFSET 0xB4C ++#define VR9_SDMA_ISR_BPEX_SHIFT 15 ++#define VR9_SDMA_ISR_BPEX_SIZE 1 ++/* Bit: 'BFULL' */ ++/* Description: 'Buffer Full' */ ++#define VR9_SDMA_ISR_BFULL_OFFSET 0xB4C ++#define VR9_SDMA_ISR_BFULL_SHIFT 14 ++#define VR9_SDMA_ISR_BFULL_SIZE 1 ++/* Bit: 'FERR' */ ++/* Description: 'Frame Error' */ ++#define VR9_SDMA_ISR_FERR_OFFSET 0xB4C ++#define VR9_SDMA_ISR_FERR_SHIFT 13 ++#define VR9_SDMA_ISR_FERR_SIZE 1 ++/* Bit: 'FRX' */ ++/* Description: 'Frame Received Successfully' */ ++#define VR9_SDMA_ISR_FRX_OFFSET 0xB4C ++#define VR9_SDMA_ISR_FRX_SHIFT 0 ++#define VR9_SDMA_ISR_FRX_SIZE 13 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet SwitchStore DMA Port Control Register' */ ++/* Bit: 'DTHR' */ ++/* Description: 'Drop Threshold Selection' */ ++#define VR9_SDMA_PCTRL_DTHR_OFFSET 0xBC0 ++#define VR9_SDMA_PCTRL_DTHR_SHIFT 13 ++#define VR9_SDMA_PCTRL_DTHR_SIZE 2 ++/* Bit: 'PTHR' */ ++/* Description: 'Pause Threshold Selection' */ ++#define VR9_SDMA_PCTRL_PTHR_OFFSET 0xBC0 ++#define VR9_SDMA_PCTRL_PTHR_SHIFT 11 ++#define VR9_SDMA_PCTRL_PTHR_SIZE 2 ++/* Bit: 'PHYEFWD' */ ++/* Description: 'Forward PHY Error Frames' */ ++#define VR9_SDMA_PCTRL_PHYEFWD_OFFSET 0xBC0 ++#define VR9_SDMA_PCTRL_PHYEFWD_SHIFT 10 ++#define VR9_SDMA_PCTRL_PHYEFWD_SIZE 1 ++/* Bit: 'ALGFWD' */ ++/* Description: 'Forward Alignment Error Frames' */ ++#define VR9_SDMA_PCTRL_ALGFWD_OFFSET 0xBC0 ++#define VR9_SDMA_PCTRL_ALGFWD_SHIFT 9 ++#define VR9_SDMA_PCTRL_ALGFWD_SIZE 1 ++/* Bit: 'LENFWD' */ ++/* Description: 'Forward Length Errored Frames' */ ++#define VR9_SDMA_PCTRL_LENFWD_OFFSET 0xBC0 ++#define VR9_SDMA_PCTRL_LENFWD_SHIFT 8 ++#define VR9_SDMA_PCTRL_LENFWD_SIZE 1 ++/* Bit: 'OSFWD' */ ++/* Description: 'Forward Oversized Frames' */ ++#define VR9_SDMA_PCTRL_OSFWD_OFFSET 0xBC0 ++#define VR9_SDMA_PCTRL_OSFWD_SHIFT 7 ++#define VR9_SDMA_PCTRL_OSFWD_SIZE 1 ++/* Bit: 'USFWD' */ ++/* Description: 'Forward Undersized Frames' */ ++#define VR9_SDMA_PCTRL_USFWD_OFFSET 0xBC0 ++#define VR9_SDMA_PCTRL_USFWD_SHIFT 6 ++#define VR9_SDMA_PCTRL_USFWD_SIZE 1 ++/* Bit: 'FCSIGN' */ ++/* Description: 'Ignore FCS Errors' */ ++#define VR9_SDMA_PCTRL_FCSIGN_OFFSET 0xBC0 ++#define VR9_SDMA_PCTRL_FCSIGN_SHIFT 5 ++#define VR9_SDMA_PCTRL_FCSIGN_SIZE 1 ++/* Bit: 'FCSFWD' */ ++/* Description: 'Forward FCS Errored Frames' */ ++#define VR9_SDMA_PCTRL_FCSFWD_OFFSET 0xBC0 ++#define VR9_SDMA_PCTRL_FCSFWD_SHIFT 4 ++#define VR9_SDMA_PCTRL_FCSFWD_SIZE 1 ++/* Bit: 'PAUFWD' */ ++/* Description: 'Pause Frame Forwarding' */ ++#define VR9_SDMA_PCTRL_PAUFWD_OFFSET 0xBC0 ++#define VR9_SDMA_PCTRL_PAUFWD_SHIFT 3 ++#define VR9_SDMA_PCTRL_PAUFWD_SIZE 1 ++/* Bit: 'MFCEN' */ ++/* Description: 'Metering Flow Control Enable' */ ++#define VR9_SDMA_PCTRL_MFCEN_OFFSET 0xBC0 ++#define VR9_SDMA_PCTRL_MFCEN_SHIFT 2 ++#define VR9_SDMA_PCTRL_MFCEN_SIZE 1 ++/* Bit: 'FCEN' */ ++/* Description: 'Flow Control Enable' */ ++#define VR9_SDMA_PCTRL_FCEN_OFFSET 0xBC0 ++#define VR9_SDMA_PCTRL_FCEN_SHIFT 1 ++#define VR9_SDMA_PCTRL_FCEN_SIZE 1 ++/* Bit: 'PEN' */ ++/* Description: 'Port Enable' */ ++#define VR9_SDMA_PCTRL_PEN_OFFSET 0xBC0 ++#define VR9_SDMA_PCTRL_PEN_SHIFT 0 ++#define VR9_SDMA_PCTRL_PEN_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet SwitchStore DMA Port Priority Register' */ ++/* Bit: 'MIN_IFG' */ ++/* Description: 'Minimum IFG,SFD and preamble' */ ++#define VR9_SDMA_PRIO_MIN_IFG_OFFSET 0xBC1 ++#define VR9_SDMA_PRIO_MIN_IFG_SHIFT 7 ++#define VR9_SDMA_PRIO_MIN_IFG_SIZE 5 ++/* Bit: 'PHYEIGN' */ ++/* Description: 'Ignore PHY Error Frames' */ ++#define VR9_SDMA_PRIO_PHYEIGN_OFFSET 0xBC1 ++#define VR9_SDMA_PRIO_PHYEIGN_SHIFT 6 ++#define VR9_SDMA_PRIO_PHYEIGN_SIZE 1 ++/* Bit: 'ALGIGN' */ ++/* Description: 'Ignore Alignment Error Frames' */ ++#define VR9_SDMA_PRIO_ALGIGN_OFFSET 0xBC1 ++#define VR9_SDMA_PRIO_ALGIGN_SHIFT 5 ++#define VR9_SDMA_PRIO_ALGIGN_SIZE 1 ++/* Bit: 'LENIGN' */ ++/* Description: 'Ignore Length Errored Frames' */ ++#define VR9_SDMA_PRIO_LENIGN_OFFSET 0xBC1 ++#define VR9_SDMA_PRIO_LENIGN_SHIFT 4 ++#define VR9_SDMA_PRIO_LENIGN_SIZE 1 ++/* Bit: 'OSIGN' */ ++/* Description: 'Ignore Oversized Frames' */ ++#define VR9_SDMA_PRIO_OSIGN_OFFSET 0xBC1 ++#define VR9_SDMA_PRIO_OSIGN_SHIFT 3 ++#define VR9_SDMA_PRIO_OSIGN_SIZE 1 ++/* Bit: 'USIGN' */ ++/* Description: 'Ignore Undersized Frames' */ ++#define VR9_SDMA_PRIO_USIGN_OFFSET 0xBC1 ++#define VR9_SDMA_PRIO_USIGN_SHIFT 2 ++#define VR9_SDMA_PRIO_USIGN_SIZE 1 ++/* Bit: 'PRIO' */ ++/* Description: 'SDMA PRIO' */ ++#define VR9_SDMA_PRIO_PRIO_OFFSET 0xBC1 ++#define VR9_SDMA_PRIO_PRIO_SHIFT 0 ++#define VR9_SDMA_PRIO_PRIO_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet SwitchStore DMA Port Status Register 0' */ ++/* Bit: 'HDR_PTR' */ ++/* Description: 'Port Ingress Queue Header Pointer' */ ++#define VR9_SDMA_PSTAT0_HDR_PTR_OFFSET 0xBC2 ++#define VR9_SDMA_PSTAT0_HDR_PTR_SHIFT 0 ++#define VR9_SDMA_PSTAT0_HDR_PTR_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ethernet SwitchStore DMA Port Status Register 1' */ ++/* Bit: 'PPKT' */ ++/* Description: 'Port Ingress Packet Count' */ ++#define VR9_SDMA_PSTAT1_PPKT_OFFSET 0xBC3 ++#define VR9_SDMA_PSTAT1_PPKT_SHIFT 0 ++#define VR9_SDMA_PSTAT1_PPKT_SIZE 10 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ingress TimeStamp Register 0' */ ++/* Bit: 'TSTL' */ ++/* Description: 'Time Stamp [15:0]' */ ++#define VR9_SDMA_TSTAMP0_TSTL_OFFSET 0xBC4 ++#define VR9_SDMA_TSTAMP0_TSTL_SHIFT 0 ++#define VR9_SDMA_TSTAMP0_TSTL_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Ingress TimeStamp Register 1' */ ++/* Bit: 'TSTH' */ ++/* Description: 'Time Stamp [31:16]' */ ++#define VR9_SDMA_TSTAMP1_TSTH_OFFSET 0xBC5 ++#define VR9_SDMA_TSTAMP1_TSTH_SHIFT 0 ++#define VR9_SDMA_TSTAMP1_TSTH_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++#endif /* #ifndef _VR9_SWITCH_H */ +diff --git a/include/switch_api/VR9_top.h b/include/switch_api/VR9_top.h +new file mode 100644 +index 0000000..626a4bf +--- /dev/null ++++ b/include/switch_api/VR9_top.h +@@ -0,0 +1,798 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2011 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++#ifndef _VR9_TOP_H ++#define _VR9_TOP_H ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Global Control Register0' */ ++/* Bit: 'SE' */ ++/* Description: 'Global Switch Macro Enable' */ ++#define VR9_GLOB_CTRL_SE_OFFSET 0x000 ++#define VR9_GLOB_CTRL_SE_SHIFT 15 ++#define VR9_GLOB_CTRL_SE_SIZE 1 ++/* Bit: 'HWRES' */ ++/* Description: 'Global Hardware Reset' */ ++#define VR9_GLOB_CTRL_HWRES_OFFSET 0x000 ++#define VR9_GLOB_CTRL_HWRES_SHIFT 1 ++#define VR9_GLOB_CTRL_HWRES_SIZE 1 ++/* Bit: 'SWRES' */ ++/* Description: 'Global Software Reset' */ ++#define VR9_GLOB_CTRL_SWRES_OFFSET 0x000 ++#define VR9_GLOB_CTRL_SWRES_SHIFT 0 ++#define VR9_GLOB_CTRL_SWRES_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MDIO Control Register' */ ++/* Bit: 'MBUSY' */ ++/* Description: 'MDIO Busy' */ ++#define VR9_MDIO_CTRL_MBUSY_OFFSET 0x008 ++#define VR9_MDIO_CTRL_MBUSY_SHIFT 12 ++#define VR9_MDIO_CTRL_MBUSY_SIZE 1 ++/* Bit: 'OP' */ ++/* Description: 'Operation Code' */ ++#define VR9_MDIO_CTRL_OP_OFFSET 0x008 ++#define VR9_MDIO_CTRL_OP_SHIFT 10 ++#define VR9_MDIO_CTRL_OP_SIZE 2 ++/* Bit: 'PHYAD' */ ++/* Description: 'PHY Address' */ ++#define VR9_MDIO_CTRL_PHYAD_OFFSET 0x008 ++#define VR9_MDIO_CTRL_PHYAD_SHIFT 5 ++#define VR9_MDIO_CTRL_PHYAD_SIZE 5 ++/* Bit: 'REGAD' */ ++/* Description: 'Register Address' */ ++#define VR9_MDIO_CTRL_REGAD_OFFSET 0x008 ++#define VR9_MDIO_CTRL_REGAD_SHIFT 0 ++#define VR9_MDIO_CTRL_REGAD_SIZE 5 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MDIO Read Data Register' */ ++/* Bit: 'RDATA' */ ++/* Description: 'Read Data' */ ++#define VR9_MDIO_READ_RDATA_OFFSET 0x009 ++#define VR9_MDIO_READ_RDATA_SHIFT 0 ++#define VR9_MDIO_READ_RDATA_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MDIO Write Data Register' */ ++/* Bit: 'WDATA' */ ++/* Description: 'Write Data' */ ++#define VR9_MDIO_WRITE_WDATA_OFFSET 0x00A ++#define VR9_MDIO_WRITE_WDATA_SHIFT 0 ++#define VR9_MDIO_WRITE_WDATA_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MDC Clock ConfigurationRegister 0' */ ++/* Bit: 'PEN_5' */ ++/* Description: 'Polling State Machine Enable' */ ++#define VR9_MDC_CFG_0_PEN_5_OFFSET 0x00B ++#define VR9_MDC_CFG_0_PEN_5_SHIFT 5 ++#define VR9_MDC_CFG_0_PEN_5_SIZE 1 ++/* Bit: 'PEN_4' */ ++/* Description: 'Polling State Machine Enable' */ ++#define VR9_MDC_CFG_0_PEN_4_OFFSET 0x00B ++#define VR9_MDC_CFG_0_PEN_4_SHIFT 4 ++#define VR9_MDC_CFG_0_PEN_4_SIZE 1 ++/* Bit: 'PEN_3' */ ++/* Description: 'Polling State Machine Enable' */ ++#define VR9_MDC_CFG_0_PEN_3_OFFSET 0x00B ++#define VR9_MDC_CFG_0_PEN_3_SHIFT 3 ++#define VR9_MDC_CFG_0_PEN_3_SIZE 1 ++/* Bit: 'PEN_2' */ ++/* Description: 'Polling State Machine Enable' */ ++#define VR9_MDC_CFG_0_PEN_2_OFFSET 0x00B ++#define VR9_MDC_CFG_0_PEN_2_SHIFT 2 ++#define VR9_MDC_CFG_0_PEN_2_SIZE 1 ++/* Bit: 'PEN_1' */ ++/* Description: 'Polling State Machine Enable' */ ++#define VR9_MDC_CFG_0_PEN_1_OFFSET 0x00B ++#define VR9_MDC_CFG_0_PEN_1_SHIFT 1 ++#define VR9_MDC_CFG_0_PEN_1_SIZE 1 ++/* Bit: 'PEN_0' */ ++/* Description: 'Polling State Machine Enable' */ ++#define VR9_MDC_CFG_0_PEN_0_OFFSET 0x00B ++#define VR9_MDC_CFG_0_PEN_0_SHIFT 0 ++#define VR9_MDC_CFG_0_PEN_0_SIZE 1 ++/* Bit: 'PEN_0~PEN_5' */ ++/* Description: 'Polling State Machine Enable' */ ++#define VR9_MDC_CFG_0_PEN_ALL_OFFSET 0x00B ++#define VR9_MDC_CFG_0_PEN_ALL_SHIFT 0 ++#define VR9_MDC_CFG_0_PEN_ALL_SIZE 6 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'MDC Clock ConfigurationRegister 1' */ ++/* Bit: 'RES' */ ++/* Description: 'MDIO Hardware Reset' */ ++#define VR9_MDC_CFG_1_RES_OFFSET 0x00C ++#define VR9_MDC_CFG_1_RES_SHIFT 15 ++#define VR9_MDC_CFG_1_RES_SIZE 1 ++/* Bit: 'MCEN' */ ++/* Description: 'Management Clock Enable' */ ++#define VR9_MDC_CFG_1_MCEN_OFFSET 0x00C ++#define VR9_MDC_CFG_1_MCEN_SHIFT 8 ++#define VR9_MDC_CFG_1_MCEN_SIZE 1 ++/* Bit: 'FREQ' */ ++/* Description: 'MDIO Interface Clock Rate' */ ++#define VR9_MDC_CFG_1_FREQ_OFFSET 0x00C ++#define VR9_MDC_CFG_1_FREQ_SHIFT 0 ++#define VR9_MDC_CFG_1_FREQ_SIZE 8 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PHY Address RegisterPORT 5' */ ++/* Bit: 'LNKST' */ ++/* Description: 'Link Status Control' */ ++#define VR9_PHY_ADDR_5_LNKST_OFFSET 0x010 ++#define VR9_PHY_ADDR_5_LNKST_SHIFT 13 ++#define VR9_PHY_ADDR_5_LNKST_SIZE 2 ++/* Bit: 'SPEED' */ ++/* Description: 'Speed Control' */ ++#define VR9_PHY_ADDR_5_SPEED_OFFSET 0x010 ++#define VR9_PHY_ADDR_5_SPEED_SHIFT 11 ++#define VR9_PHY_ADDR_5_SPEED_SIZE 2 ++/* Bit: 'FDUP' */ ++/* Description: 'Full Duplex Control' */ ++#define VR9_PHY_ADDR_5_FDUP_OFFSET 0x010 ++#define VR9_PHY_ADDR_5_FDUP_SHIFT 9 ++#define VR9_PHY_ADDR_5_FDUP_SIZE 2 ++/* Bit: 'FCONTX' */ ++/* Description: 'Flow Control Mode TX' */ ++#define VR9_PHY_ADDR_5_FCONTX_OFFSET 0x010 ++#define VR9_PHY_ADDR_5_FCONTX_SHIFT 7 ++#define VR9_PHY_ADDR_5_FCONTX_SIZE 2 ++/* Bit: 'FCONRX' */ ++/* Description: 'Flow Control Mode RX' */ ++#define VR9_PHY_ADDR_5_FCONRX_OFFSET 0x010 ++#define VR9_PHY_ADDR_5_FCONRX_SHIFT 5 ++#define VR9_PHY_ADDR_5_FCONRX_SIZE 2 ++/* Bit: 'ADDR' */ ++/* Description: 'PHY Address' */ ++#define VR9_PHY_ADDR_5_ADDR_OFFSET 0x010 ++#define VR9_PHY_ADDR_5_ADDR_SHIFT 0 ++#define VR9_PHY_ADDR_5_ADDR_SIZE 5 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PHY Address RegisterPORT 4' */ ++/* Bit: 'LNKST' */ ++/* Description: 'Link Status Control' */ ++#define VR9_PHY_ADDR_4_LNKST_OFFSET 0x011 ++#define VR9_PHY_ADDR_4_LNKST_SHIFT 13 ++#define VR9_PHY_ADDR_4_LNKST_SIZE 2 ++/* Bit: 'SPEED' */ ++/* Description: 'Speed Control' */ ++#define VR9_PHY_ADDR_4_SPEED_OFFSET 0x011 ++#define VR9_PHY_ADDR_4_SPEED_SHIFT 11 ++#define VR9_PHY_ADDR_4_SPEED_SIZE 2 ++/* Bit: 'FDUP' */ ++/* Description: 'Full Duplex Control' */ ++#define VR9_PHY_ADDR_4_FDUP_OFFSET 0x011 ++#define VR9_PHY_ADDR_4_FDUP_SHIFT 9 ++#define VR9_PHY_ADDR_4_FDUP_SIZE 2 ++/* Bit: 'FCONTX' */ ++/* Description: 'Flow Control Mode TX' */ ++#define VR9_PHY_ADDR_4_FCONTX_OFFSET 0x011 ++#define VR9_PHY_ADDR_4_FCONTX_SHIFT 7 ++#define VR9_PHY_ADDR_4_FCONTX_SIZE 2 ++/* Bit: 'FCONRX' */ ++/* Description: 'Flow Control Mode RX' */ ++#define VR9_PHY_ADDR_4_FCONRX_OFFSET 0x011 ++#define VR9_PHY_ADDR_4_FCONRX_SHIFT 5 ++#define VR9_PHY_ADDR_4_FCONRX_SIZE 2 ++/* Bit: 'ADDR' */ ++/* Description: 'PHY Address' */ ++#define VR9_PHY_ADDR_4_ADDR_OFFSET 0x011 ++#define VR9_PHY_ADDR_4_ADDR_SHIFT 0 ++#define VR9_PHY_ADDR_4_ADDR_SIZE 5 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PHY Address RegisterPORT 3' */ ++/* Bit: 'LNKST' */ ++/* Description: 'Link Status Control' */ ++#define VR9_PHY_ADDR_3_LNKST_OFFSET 0x012 ++#define VR9_PHY_ADDR_3_LNKST_SHIFT 13 ++#define VR9_PHY_ADDR_3_LNKST_SIZE 2 ++/* Bit: 'SPEED' */ ++/* Description: 'Speed Control' */ ++#define VR9_PHY_ADDR_3_SPEED_OFFSET 0x012 ++#define VR9_PHY_ADDR_3_SPEED_SHIFT 11 ++#define VR9_PHY_ADDR_3_SPEED_SIZE 2 ++/* Bit: 'FDUP' */ ++/* Description: 'Full Duplex Control' */ ++#define VR9_PHY_ADDR_3_FDUP_OFFSET 0x012 ++#define VR9_PHY_ADDR_3_FDUP_SHIFT 9 ++#define VR9_PHY_ADDR_3_FDUP_SIZE 2 ++/* Bit: 'FCONTX' */ ++/* Description: 'Flow Control Mode TX' */ ++#define VR9_PHY_ADDR_3_FCONTX_OFFSET 0x012 ++#define VR9_PHY_ADDR_3_FCONTX_SHIFT 7 ++#define VR9_PHY_ADDR_3_FCONTX_SIZE 2 ++/* Bit: 'FCONRX' */ ++/* Description: 'Flow Control Mode RX' */ ++#define VR9_PHY_ADDR_3_FCONRX_OFFSET 0x012 ++#define VR9_PHY_ADDR_3_FCONRX_SHIFT 5 ++#define VR9_PHY_ADDR_3_FCONRX_SIZE 2 ++/* Bit: 'ADDR' */ ++/* Description: 'PHY Address' */ ++#define VR9_PHY_ADDR_3_ADDR_OFFSET 0x012 ++#define VR9_PHY_ADDR_3_ADDR_SHIFT 0 ++#define VR9_PHY_ADDR_3_ADDR_SIZE 5 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PHY Address RegisterPORT 2' */ ++/* Bit: 'LNKST' */ ++/* Description: 'Link Status Control' */ ++#define VR9_PHY_ADDR_2_LNKST_OFFSET 0x013 ++#define VR9_PHY_ADDR_2_LNKST_SHIFT 13 ++#define VR9_PHY_ADDR_2_LNKST_SIZE 2 ++/* Bit: 'SPEED' */ ++/* Description: 'Speed Control' */ ++#define VR9_PHY_ADDR_2_SPEED_OFFSET 0x013 ++#define VR9_PHY_ADDR_2_SPEED_SHIFT 11 ++#define VR9_PHY_ADDR_2_SPEED_SIZE 2 ++/* Bit: 'FDUP' */ ++/* Description: 'Full Duplex Control' */ ++#define VR9_PHY_ADDR_2_FDUP_OFFSET 0x013 ++#define VR9_PHY_ADDR_2_FDUP_SHIFT 9 ++#define VR9_PHY_ADDR_2_FDUP_SIZE 2 ++/* Bit: 'FCONTX' */ ++/* Description: 'Flow Control Mode TX' */ ++#define VR9_PHY_ADDR_2_FCONTX_OFFSET 0x013 ++#define VR9_PHY_ADDR_2_FCONTX_SHIFT 7 ++#define VR9_PHY_ADDR_2_FCONTX_SIZE 2 ++/* Bit: 'FCONRX' */ ++/* Description: 'Flow Control Mode RX' */ ++#define VR9_PHY_ADDR_2_FCONRX_OFFSET 0x013 ++#define VR9_PHY_ADDR_2_FCONRX_SHIFT 5 ++#define VR9_PHY_ADDR_2_FCONRX_SIZE 2 ++/* Bit: 'ADDR' */ ++/* Description: 'PHY Address' */ ++#define VR9_PHY_ADDR_2_ADDR_OFFSET 0x013 ++#define VR9_PHY_ADDR_2_ADDR_SHIFT 0 ++#define VR9_PHY_ADDR_2_ADDR_SIZE 5 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PHY Address RegisterPORT 1' */ ++/* Bit: 'LNKST' */ ++/* Description: 'Link Status Control' */ ++#define VR9_PHY_ADDR_1_LNKST_OFFSET 0x014 ++#define VR9_PHY_ADDR_1_LNKST_SHIFT 13 ++#define VR9_PHY_ADDR_1_LNKST_SIZE 2 ++/* Bit: 'SPEED' */ ++/* Description: 'Speed Control' */ ++#define VR9_PHY_ADDR_1_SPEED_OFFSET 0x014 ++#define VR9_PHY_ADDR_1_SPEED_SHIFT 11 ++#define VR9_PHY_ADDR_1_SPEED_SIZE 2 ++/* Bit: 'FDUP' */ ++/* Description: 'Full Duplex Control' */ ++#define VR9_PHY_ADDR_1_FDUP_OFFSET 0x014 ++#define VR9_PHY_ADDR_1_FDUP_SHIFT 9 ++#define VR9_PHY_ADDR_1_FDUP_SIZE 2 ++/* Bit: 'FCONTX' */ ++/* Description: 'Flow Control Mode TX' */ ++#define VR9_PHY_ADDR_1_FCONTX_OFFSET 0x014 ++#define VR9_PHY_ADDR_1_FCONTX_SHIFT 7 ++#define VR9_PHY_ADDR_1_FCONTX_SIZE 2 ++/* Bit: 'FCONRX' */ ++/* Description: 'Flow Control Mode RX' */ ++#define VR9_PHY_ADDR_1_FCONRX_OFFSET 0x014 ++#define VR9_PHY_ADDR_1_FCONRX_SHIFT 5 ++#define VR9_PHY_ADDR_1_FCONRX_SIZE 2 ++/* Bit: 'ADDR' */ ++/* Description: 'PHY Address' */ ++#define VR9_PHY_ADDR_1_ADDR_OFFSET 0x014 ++#define VR9_PHY_ADDR_1_ADDR_SHIFT 0 ++#define VR9_PHY_ADDR_1_ADDR_SIZE 5 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PHY Address RegisterPORT 0' */ ++/* Bit: 'LNKST' */ ++/* Description: 'Link Status Control' */ ++#define VR9_PHY_ADDR_0_LNKST_OFFSET 0x015 ++#define VR9_PHY_ADDR_0_LNKST_SHIFT 13 ++#define VR9_PHY_ADDR_0_LNKST_SIZE 2 ++/* Bit: 'SPEED' */ ++/* Description: 'Speed Control' */ ++#define VR9_PHY_ADDR_0_SPEED_OFFSET 0x015 ++#define VR9_PHY_ADDR_0_SPEED_SHIFT 11 ++#define VR9_PHY_ADDR_0_SPEED_SIZE 2 ++/* Bit: 'FDUP' */ ++/* Description: 'Full Duplex Control' */ ++#define VR9_PHY_ADDR_0_FDUP_OFFSET 0x015 ++#define VR9_PHY_ADDR_0_FDUP_SHIFT 9 ++#define VR9_PHY_ADDR_0_FDUP_SIZE 2 ++/* Bit: 'FCONTX' */ ++/* Description: 'Flow Control Mode TX' */ ++#define VR9_PHY_ADDR_0_FCONTX_OFFSET 0x015 ++#define VR9_PHY_ADDR_0_FCONTX_SHIFT 7 ++#define VR9_PHY_ADDR_0_FCONTX_SIZE 2 ++/* Bit: 'FCONRX' */ ++/* Description: 'Flow Control Mode RX' */ ++#define VR9_PHY_ADDR_0_FCONRX_OFFSET 0x015 ++#define VR9_PHY_ADDR_0_FCONRX_SHIFT 5 ++#define VR9_PHY_ADDR_0_FCONRX_SIZE 2 ++/* Bit: 'ADDR' */ ++/* Description: 'PHY Address' */ ++#define VR9_PHY_ADDR_0_ADDR_OFFSET 0x015 ++#define VR9_PHY_ADDR_0_ADDR_SHIFT 0 ++#define VR9_PHY_ADDR_0_ADDR_SIZE 5 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PHY MDIO PollingStatus per PORT' */ ++/* Bit: 'CLK_STOP_CAPABLE' */ ++/* Description: 'PHY supports MAC turning of TX clk' */ ++#define VR9_MDIO_STAT_0_CLK_STOP_CAPABLE_OFFSET 0x016 ++#define VR9_MDIO_STAT_0_CLK_STOP_CAPABLE_SHIFT 8 ++#define VR9_MDIO_STAT_0_CLK_STOP_CAPABLE_SIZE 1 ++/* Bit: 'EEE_CAPABLE' */ ++/* Description: 'PHY and link partner support EEE for current speed' */ ++#define VR9_MDIO_STAT_0_EEE_CAPABLE_OFFSET 0x016 ++#define VR9_MDIO_STAT_0_EEE_CAPABLE_SHIFT 7 ++#define VR9_MDIO_STAT_0_EEE_CAPABLE_SIZE 1 ++/* Bit: 'PACT' */ ++/* Description: 'PHY Active Status' */ ++#define VR9_MDIO_STAT_0_PACT_OFFSET 0x016 ++#define VR9_MDIO_STAT_0_PACT_SHIFT 6 ++#define VR9_MDIO_STAT_0_PACT_SIZE 1 ++/* Bit: 'LSTAT' */ ++/* Description: 'Link Status' */ ++#define VR9_MDIO_STAT_0_LSTAT_OFFSET 0x016 ++#define VR9_MDIO_STAT_0_LSTAT_SHIFT 5 ++#define VR9_MDIO_STAT_0_LSTAT_SIZE 1 ++/* Bit: 'SPEED' */ ++/* Description: 'Speed Control' */ ++#define VR9_MDIO_STAT_0_SPEED_OFFSET 0x016 ++#define VR9_MDIO_STAT_0_SPEED_SHIFT 3 ++#define VR9_MDIO_STAT_0_SPEED_SIZE 2 ++/* Bit: 'FDUP' */ ++/* Description: 'Full Duplex Status' */ ++#define VR9_MDIO_STAT_0_FDUP_OFFSET 0x016 ++#define VR9_MDIO_STAT_0_FDUP_SHIFT 2 ++#define VR9_MDIO_STAT_0_FDUP_SIZE 1 ++/* Bit: 'RXPAUEN' */ ++/* Description: 'Receive Pause Enable Status' */ ++#define VR9_MDIO_STAT_0_RXPAUEN_OFFSET 0x016 ++#define VR9_MDIO_STAT_0_RXPAUEN_SHIFT 1 ++#define VR9_MDIO_STAT_0_RXPAUEN_SIZE 1 ++/* Bit: 'TXPAUEN' */ ++/* Description: 'Transmit Pause Enable Status' */ ++#define VR9_MDIO_STAT_0_TXPAUEN_OFFSET 0x016 ++#define VR9_MDIO_STAT_0_TXPAUEN_SHIFT 0 ++#define VR9_MDIO_STAT_0_TXPAUEN_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'EEE auto negotiationoverides' */ ++/* Bit: 'CLK_STOP_CAPABLE' */ ++/* Description: 'clk stop capable' */ ++#define VR9_ANEG_EEE_0_CLK_STOP_CAPABLE_OFFSET 0x01C ++#define VR9_ANEG_EEE_0_CLK_STOP_CAPABLE_SHIFT 2 ++#define VR9_ANEG_EEE_0_CLK_STOP_CAPABLE_SIZE 2 ++/* Bit: 'EEE_CAPABLE' */ ++/* Description: 'EEE capable' */ ++#define VR9_ANEG_EEE_0_EEE_CAPABLE_OFFSET 0x01C ++#define VR9_ANEG_EEE_0_EEE_CAPABLE_SHIFT 0 ++#define VR9_ANEG_EEE_0_EEE_CAPABLE_SIZE 2 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'xMII Port 0 ConfigurationRegister' */ ++/* Bit: 'RES' */ ++/* Description: 'Hardware Reset' */ ++#define VR9_MII_CFG_0_RES_OFFSET 0x036 ++#define VR9_MII_CFG_0_RES_SHIFT 15 ++#define VR9_MII_CFG_0_RES_SIZE 1 ++/* Bit: 'EN' */ ++/* Description: 'xMII Interface Enable' */ ++#define VR9_MII_CFG_0_EN_OFFSET 0x036 ++#define VR9_MII_CFG_0_EN_SHIFT 14 ++#define VR9_MII_CFG_0_EN_SIZE 1 ++/* Bit: 'ISOL' */ ++/* Description: 'ISOLATE xMII Interface' */ ++#define VR9_MII_CFG_0_ISOL_OFFSET 0x036 ++#define VR9_MII_CFG_0_ISOL_SHIFT 13 ++#define VR9_MII_CFG_0_ISOL_SIZE 1 ++/* Bit: 'LDCLKDIS' */ ++/* Description: 'Link Down Clock Disable' */ ++#define VR9_MII_CFG_0_LDCLKDIS_OFFSET 0x036 ++#define VR9_MII_CFG_0_LDCLKDIS_SHIFT 12 ++#define VR9_MII_CFG_0_LDCLKDIS_SIZE 1 ++/* Bit: 'CRS' */ ++/* Description: 'CRS Sensitivity Configuration' */ ++#define VR9_MII_CFG_0_CRS_OFFSET 0x036 ++#define VR9_MII_CFG_0_CRS_SHIFT 9 ++#define VR9_MII_CFG_0_CRS_SIZE 2 ++/* Bit: 'RGMII_IBS' */ ++/* Description: 'RGMII In Band Status' */ ++#define VR9_MII_CFG_0_RGMII_IBS_OFFSET 0x036 ++#define VR9_MII_CFG_0_RGMII_IBS_SHIFT 8 ++#define VR9_MII_CFG_0_RGMII_IBS_SIZE 1 ++/* Bit: 'RMII' */ ++/* Description: 'RMII Reference Clock Direction of the Port' */ ++#define VR9_MII_CFG_0_RMII_OFFSET 0x036 ++#define VR9_MII_CFG_0_RMII_SHIFT 7 ++#define VR9_MII_CFG_0_RMII_SIZE 1 ++/* Bit: 'MIIRATE' */ ++/* Description: 'xMII Port Interface Clock Rate' */ ++#define VR9_MII_CFG_0_MIIRATE_OFFSET 0x036 ++#define VR9_MII_CFG_0_MIIRATE_SHIFT 4 ++#define VR9_MII_CFG_0_MIIRATE_SIZE 3 ++/* Bit: 'MIIMODE' */ ++/* Description: 'xMII Interface Mode' */ ++#define VR9_MII_CFG_0_MIIMODE_OFFSET 0x036 ++#define VR9_MII_CFG_0_MIIMODE_SHIFT 0 ++#define VR9_MII_CFG_0_MIIMODE_SIZE 4 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Configuration of ClockDelay for Port 0' */ ++/* Bit: 'RXLOCK' */ ++/* Description: 'Lock Status MDL of Receive PCDU' */ ++#define VR9_PCDU_0_RXLOCK_OFFSET 0x037 ++#define VR9_PCDU_0_RXLOCK_SHIFT 15 ++#define VR9_PCDU_0_RXLOCK_SIZE 1 ++/* Bit: 'TXLOCK' */ ++/* Description: 'Lock Status of MDL of Transmit PCDU' */ ++#define VR9_PCDU_0_TXLOCK_OFFSET 0x037 ++#define VR9_PCDU_0_TXLOCK_SHIFT 14 ++#define VR9_PCDU_0_TXLOCK_SIZE 1 ++/* Bit: 'RXDLY' */ ++/* Description: 'Configure Receive Clock Delay' */ ++#define VR9_PCDU_0_RXDLY_OFFSET 0x037 ++#define VR9_PCDU_0_RXDLY_SHIFT 7 ++#define VR9_PCDU_0_RXDLY_SIZE 3 ++/* Bit: 'TXDLY' */ ++/* Description: 'Configure Transmit PCDU' */ ++#define VR9_PCDU_0_TXDLY_OFFSET 0x037 ++#define VR9_PCDU_0_TXDLY_SHIFT 0 ++#define VR9_PCDU_0_TXDLY_SIZE 3 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'xMII Port 1 ConfigurationRegister' */ ++/* Bit: 'RES' */ ++/* Description: 'Hardware Reset' */ ++#define VR9_MII_CFG_1_RES_OFFSET 0x038 ++#define VR9_MII_CFG_1_RES_SHIFT 15 ++#define VR9_MII_CFG_1_RES_SIZE 1 ++/* Bit: 'EN' */ ++/* Description: 'xMII Interface Enable' */ ++#define VR9_MII_CFG_1_EN_OFFSET 0x038 ++#define VR9_MII_CFG_1_EN_SHIFT 14 ++#define VR9_MII_CFG_1_EN_SIZE 1 ++/* Bit: 'ISOL' */ ++/* Description: 'ISOLATE xMII Interface' */ ++#define VR9_MII_CFG_1_ISOL_OFFSET 0x038 ++#define VR9_MII_CFG_1_ISOL_SHIFT 13 ++#define VR9_MII_CFG_1_ISOL_SIZE 1 ++/* Bit: 'LDCLKDIS' */ ++/* Description: 'Link Down Clock Disable' */ ++#define VR9_MII_CFG_1_LDCLKDIS_OFFSET 0x038 ++#define VR9_MII_CFG_1_LDCLKDIS_SHIFT 12 ++#define VR9_MII_CFG_1_LDCLKDIS_SIZE 1 ++/* Bit: 'CRS' */ ++/* Description: 'CRS Sensitivity Configuration' */ ++#define VR9_MII_CFG_1_CRS_OFFSET 0x038 ++#define VR9_MII_CFG_1_CRS_SHIFT 9 ++#define VR9_MII_CFG_1_CRS_SIZE 2 ++/* Bit: 'RGMII_IBS' */ ++/* Description: 'RGMII In Band Status' */ ++#define VR9_MII_CFG_1_RGMII_IBS_OFFSET 0x038 ++#define VR9_MII_CFG_1_RGMII_IBS_SHIFT 8 ++#define VR9_MII_CFG_1_RGMII_IBS_SIZE 1 ++/* Bit: 'RMII' */ ++/* Description: 'RMII Reference Clock Direction of the Port' */ ++#define VR9_MII_CFG_1_RMII_OFFSET 0x038 ++#define VR9_MII_CFG_1_RMII_SHIFT 7 ++#define VR9_MII_CFG_1_RMII_SIZE 1 ++/* Bit: 'MIIRATE' */ ++/* Description: 'xMII Port Interface Clock Rate' */ ++#define VR9_MII_CFG_1_MIIRATE_OFFSET 0x038 ++#define VR9_MII_CFG_1_MIIRATE_SHIFT 4 ++#define VR9_MII_CFG_1_MIIRATE_SIZE 3 ++/* Bit: 'MIIMODE' */ ++/* Description: 'xMII Interface Mode' */ ++#define VR9_MII_CFG_1_MIIMODE_OFFSET 0x038 ++#define VR9_MII_CFG_1_MIIMODE_SHIFT 0 ++#define VR9_MII_CFG_1_MIIMODE_SIZE 4 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Configuration of ClockDelay for Port 1' */ ++/* Bit: 'RXLOCK' */ ++/* Description: 'Lock Status MDL of Receive PCDU' */ ++#define VR9_PCDU_1_RXLOCK_OFFSET 0x039 ++#define VR9_PCDU_1_RXLOCK_SHIFT 15 ++#define VR9_PCDU_1_RXLOCK_SIZE 1 ++/* Bit: 'TXLOCK' */ ++/* Description: 'Lock Status of MDL of Transmit PCDU' */ ++#define VR9_PCDU_1_TXLOCK_OFFSET 0x039 ++#define VR9_PCDU_1_TXLOCK_SHIFT 14 ++#define VR9_PCDU_1_TXLOCK_SIZE 1 ++/* Bit: 'RXDLY' */ ++/* Description: 'Configure Receive Clock Delay' */ ++#define VR9_PCDU_1_RXDLY_OFFSET 0x039 ++#define VR9_PCDU_1_RXDLY_SHIFT 7 ++#define VR9_PCDU_1_RXDLY_SIZE 3 ++/* Bit: 'TXDLY' */ ++/* Description: 'Configure Transmit PCDU' */ ++#define VR9_PCDU_1_TXDLY_OFFSET 0x039 ++#define VR9_PCDU_1_TXDLY_SHIFT 0 ++#define VR9_PCDU_1_TXDLY_SIZE 3 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'xMII Port 5 ConfigurationRegister' */ ++/* Bit: 'RES' */ ++/* Description: 'Hardware Reset' */ ++#define VR9_MII_CFG_5_RES_OFFSET 0x040 ++#define VR9_MII_CFG_5_RES_SHIFT 15 ++#define VR9_MII_CFG_5_RES_SIZE 1 ++/* Bit: 'EN' */ ++/* Description: 'xMII Interface Enable' */ ++#define VR9_MII_CFG_5_EN_OFFSET 0x040 ++#define VR9_MII_CFG_5_EN_SHIFT 14 ++#define VR9_MII_CFG_5_EN_SIZE 1 ++/* Bit: 'ISOL' */ ++/* Description: 'ISOLATE xMII Interface' */ ++#define VR9_MII_CFG_5_ISOL_OFFSET 0x040 ++#define VR9_MII_CFG_5_ISOL_SHIFT 13 ++#define VR9_MII_CFG_5_ISOL_SIZE 1 ++/* Bit: 'LDCLKDIS' */ ++/* Description: 'Link Down Clock Disable' */ ++#define VR9_MII_CFG_5_LDCLKDIS_OFFSET 0x040 ++#define VR9_MII_CFG_5_LDCLKDIS_SHIFT 12 ++#define VR9_MII_CFG_5_LDCLKDIS_SIZE 1 ++/* Bit: 'CRS' */ ++/* Description: 'CRS Sensitivity Configuration' */ ++#define VR9_MII_CFG_5_CRS_OFFSET 0x040 ++#define VR9_MII_CFG_5_CRS_SHIFT 9 ++#define VR9_MII_CFG_5_CRS_SIZE 2 ++/* Bit: 'RGMII_IBS' */ ++/* Description: 'RGMII In Band Status' */ ++#define VR9_MII_CFG_5_RGMII_IBS_OFFSET 0x040 ++#define VR9_MII_CFG_5_RGMII_IBS_SHIFT 8 ++#define VR9_MII_CFG_5_RGMII_IBS_SIZE 1 ++/* Bit: 'MIIRATE' */ ++/* Description: 'xMII Port Interface Clock Rate' */ ++#define VR9_MII_CFG_5_MIIRATE_OFFSET 0x040 ++#define VR9_MII_CFG_5_MIIRATE_SHIFT 4 ++#define VR9_MII_CFG_5_MIIRATE_SIZE 3 ++/* Bit: 'MIIMODE' */ ++/* Description: 'xMII Interface Mode' */ ++#define VR9_MII_CFG_5_MIIMODE_OFFSET 0x040 ++#define VR9_MII_CFG_5_MIIMODE_SHIFT 0 ++#define VR9_MII_CFG_5_MIIMODE_SIZE 4 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Configuration of ClockDelay for External Port 5' */ ++/* Bit: 'RXLOCK' */ ++/* Description: 'Lock Status MDL of Receive PCDU' */ ++#define VR9_PCDU_5_RXLOCK_OFFSET 0x041 ++#define VR9_PCDU_5_RXLOCK_SHIFT 15 ++#define VR9_PCDU_5_RXLOCK_SIZE 1 ++/* Bit: 'TXLOCK' */ ++/* Description: 'Lock Status of MDL of Transmit PCDU' */ ++#define VR9_PCDU_5_TXLOCK_OFFSET 0x041 ++#define VR9_PCDU_5_TXLOCK_SHIFT 14 ++#define VR9_PCDU_5_TXLOCK_SIZE 1 ++/* Bit: 'RXDLY' */ ++/* Description: 'Configure Receive Clock Delay' */ ++#define VR9_PCDU_5_RXDLY_OFFSET 0x041 ++#define VR9_PCDU_5_RXDLY_SHIFT 7 ++#define VR9_PCDU_5_RXDLY_SIZE 3 ++/* Bit: 'TXDLY' */ ++/* Description: 'Configure Transmit PCDU' */ ++#define VR9_PCDU_5_TXDLY_OFFSET 0x041 ++#define VR9_PCDU_5_TXDLY_SHIFT 0 ++#define VR9_PCDU_5_TXDLY_SIZE 3 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Receive Buffer ControlRegister for Port 0' */ ++/* Bit: 'RBUF_UFL' */ ++/* Description: 'Receive Buffer Underflow Indicator' */ ++#define VR9_RXB_CTL_0_RBUF_UFL_OFFSET 0x056 ++#define VR9_RXB_CTL_0_RBUF_UFL_SHIFT 15 ++#define VR9_RXB_CTL_0_RBUF_UFL_SIZE 1 ++/* Bit: 'RBUF_OFL' */ ++/* Description: 'Receive Buffer Overflow Indicator' */ ++#define VR9_RXB_CTL_0_RBUF_OFL_OFFSET 0x056 ++#define VR9_RXB_CTL_0_RBUF_OFL_SHIFT 14 ++#define VR9_RXB_CTL_0_RBUF_OFL_SIZE 1 ++/* Bit: 'RBUF_DLY_WP' */ ++/* Description: 'Delay' */ ++#define VR9_RXB_CTL_0_RBUF_DLY_WP_OFFSET 0x056 ++#define VR9_RXB_CTL_0_RBUF_DLY_WP_SHIFT 0 ++#define VR9_RXB_CTL_0_RBUF_DLY_WP_SIZE 3 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Receive Buffer ControlRegister External Port 1' */ ++/* Bit: 'RBUF_UFL' */ ++/* Description: 'Receive Buffer Underflow Indicator' */ ++#define VR9_RXB_CTL_1_RBUF_UFL_OFFSET 0x057 ++#define VR9_RXB_CTL_1_RBUF_UFL_SHIFT 15 ++#define VR9_RXB_CTL_1_RBUF_UFL_SIZE 1 ++/* Bit: 'RBUF_OFL' */ ++/* Description: 'Receive Buffer Overflow Indicator' */ ++#define VR9_RXB_CTL_1_RBUF_OFL_OFFSET 0x057 ++#define VR9_RXB_CTL_1_RBUF_OFL_SHIFT 14 ++#define VR9_RXB_CTL_1_RBUF_OFL_SIZE 1 ++/* Bit: 'RBUF_DLY_WP' */ ++/* Description: 'Delay' */ ++#define VR9_RXB_CTL_1_RBUF_DLY_WP_OFFSET 0x057 ++#define VR9_RXB_CTL_1_RBUF_DLY_WP_SHIFT 0 ++#define VR9_RXB_CTL_1_RBUF_DLY_WP_SIZE 3 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Receive Buffer ControlRegister External Port 5' */ ++/* Bit: 'RBUF_UFL' */ ++/* Description: 'Receive Buffer Underflow Indicator' */ ++#define VR9_RXB_CTL_5_RBUF_UFL_OFFSET 0x05B ++#define VR9_RXB_CTL_5_RBUF_UFL_SHIFT 15 ++#define VR9_RXB_CTL_5_RBUF_UFL_SIZE 1 ++/* Bit: 'RBUF_OFL' */ ++/* Description: 'Receive Buffer Overflow Indicator' */ ++#define VR9_RXB_CTL_5_RBUF_OFL_OFFSET 0x05B ++#define VR9_RXB_CTL_5_RBUF_OFL_SHIFT 14 ++#define VR9_RXB_CTL_5_RBUF_OFL_SIZE 1 ++/* Bit: 'RBUF_DLY_WP' */ ++/* Description: 'Delay' */ ++#define VR9_RXB_CTL_5_RBUF_DLY_WP_OFFSET 0x05B ++#define VR9_RXB_CTL_5_RBUF_DLY_WP_SHIFT 0 ++#define VR9_RXB_CTL_5_RBUF_DLY_WP_SIZE 3 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'Debug Control Register' */ ++/* Bit: 'DBG_EN' */ ++/* Description: 'Debug enable' */ ++#define VR9_DBG_CTL_DBG_EN_OFFSET 0x081 ++#define VR9_DBG_CTL_DBG_EN_SHIFT 14 ++#define VR9_DBG_CTL_DBG_EN_SIZE 1 ++/* Bit: 'DBG_SEL' */ ++/* Description: 'Debug select' */ ++#define VR9_DBG_CTL_DBG_SEL_OFFSET 0x081 ++#define VR9_DBG_CTL_DBG_SEL_SHIFT 0 ++#define VR9_DBG_CTL_DBG_SEL_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PMAC Header ControlRegister' */ ++/* Bit: 'FC' */ ++/* Description: 'Enable Flow Control' */ ++#define VR9_PMAC_HD_CTL_FC_OFFSET 0x082 ++#define VR9_PMAC_HD_CTL_FC_SHIFT 10 ++#define VR9_PMAC_HD_CTL_FC_SIZE 1 ++/* Bit: 'CCRC' */ ++/* Description: 'Check CRC' */ ++#define VR9_PMAC_HD_CTL_CCRC_OFFSET 0x082 ++#define VR9_PMAC_HD_CTL_CCRC_SHIFT 9 ++#define VR9_PMAC_HD_CTL_CCRC_SIZE 1 ++/* Bit: 'RST' */ ++/* Description: 'Remove Special Tag' */ ++#define VR9_PMAC_HD_CTL_RST_OFFSET 0x082 ++#define VR9_PMAC_HD_CTL_RST_SHIFT 8 ++#define VR9_PMAC_HD_CTL_RST_SIZE 1 ++/* Bit: 'AST' */ ++/* Description: 'Add Special Tag' */ ++#define VR9_PMAC_HD_CTL_AST_OFFSET 0x082 ++#define VR9_PMAC_HD_CTL_AST_SHIFT 7 ++#define VR9_PMAC_HD_CTL_AST_SIZE 1 ++/* Bit: 'RXSH' */ ++/* Description: 'Status Header' */ ++#define VR9_PMAC_HD_CTL_RXSH_OFFSET 0x082 ++#define VR9_PMAC_HD_CTL_RXSH_SHIFT 6 ++#define VR9_PMAC_HD_CTL_RXSH_SIZE 1 ++/* Bit: 'RL2' */ ++/* Description: 'Remove Layer-2 Header' */ ++#define VR9_PMAC_HD_CTL_RL2_OFFSET 0x082 ++#define VR9_PMAC_HD_CTL_RL2_SHIFT 5 ++#define VR9_PMAC_HD_CTL_RL2_SIZE 1 ++/* Bit: 'RC' */ ++/* Description: 'Remove CRC' */ ++#define VR9_PMAC_HD_CTL_RC_OFFSET 0x082 ++#define VR9_PMAC_HD_CTL_RC_SHIFT 4 ++#define VR9_PMAC_HD_CTL_RC_SIZE 1 ++/* Bit: 'AS' */ ++/* Description: 'Add Status Header' */ ++#define VR9_PMAC_HD_CTL_AS_OFFSET 0x082 ++#define VR9_PMAC_HD_CTL_AS_SHIFT 3 ++#define VR9_PMAC_HD_CTL_AS_SIZE 1 ++/* Bit: 'AC' */ ++/* Description: 'Add CRC' */ ++#define VR9_PMAC_HD_CTL_AC_OFFSET 0x082 ++#define VR9_PMAC_HD_CTL_AC_SHIFT 2 ++#define VR9_PMAC_HD_CTL_AC_SIZE 1 ++/* Bit: 'TAG' */ ++/* Description: 'Add TAG' */ ++#define VR9_PMAC_HD_CTL_TAG_OFFSET 0x082 ++#define VR9_PMAC_HD_CTL_TAG_SHIFT 1 ++#define VR9_PMAC_HD_CTL_TAG_SIZE 1 ++/* Bit: 'ADD' */ ++/* Description: 'ADD Header' */ ++#define VR9_PMAC_HD_CTL_ADD_OFFSET 0x082 ++#define VR9_PMAC_HD_CTL_ADD_SHIFT 0 ++#define VR9_PMAC_HD_CTL_ADD_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PMAC Type/Length Register' */ ++/* Bit: 'TYPE_LEN' */ ++/* Description: 'TYPE or Lenght Value' */ ++#define VR9_PMAC_TL_TYPE_LEN_OFFSET 0x083 ++#define VR9_PMAC_TL_TYPE_LEN_SHIFT 0 ++#define VR9_PMAC_TL_TYPE_LEN_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PMAC Source Address Register1' */ ++/* Bit: 'SA_47_32' */ ++/* Description: 'Source Address 47..32' */ ++#define VR9_PMAC_SA1_SA_47_32_OFFSET 0x084 ++#define VR9_PMAC_SA1_SA_47_32_SHIFT 0 ++#define VR9_PMAC_SA1_SA_47_32_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PMAC Source Address Register2' */ ++/* Bit: 'SA_31_16' */ ++/* Description: 'Source Address 31..16' */ ++#define VR9_PMAC_SA2_SA_31_16_OFFSET 0x085 ++#define VR9_PMAC_SA2_SA_31_16_SHIFT 0 ++#define VR9_PMAC_SA2_SA_31_16_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PMAC Source Address Register3' */ ++/* Bit: 'SA_15_0' */ ++/* Description: 'Source Address 15..0' */ ++#define VR9_PMAC_SA3_SA_15_0_OFFSET 0x086 ++#define VR9_PMAC_SA3_SA_15_0_SHIFT 0 ++#define VR9_PMAC_SA3_SA_15_0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PMAC Destination AddressRegister 1' */ ++/* Bit: 'SA_47_32' */ ++/* Description: 'Destination Address 47..32' */ ++#define VR9_PMAC_DA1_SA_47_32_OFFSET 0x087 ++#define VR9_PMAC_DA1_SA_47_32_SHIFT 0 ++#define VR9_PMAC_DA1_SA_47_32_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PMAC Destination AddressRegister 2' */ ++/* Bit: 'DA_31_16' */ ++/* Description: 'Destination Address 31..16' */ ++#define VR9_PMAC_DA2_DA_31_16_OFFSET 0x088 ++#define VR9_PMAC_DA2_DA_31_16_SHIFT 0 ++#define VR9_PMAC_DA2_DA_31_16_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PMAC Destination AddressRegister 3' */ ++/* Bit: 'DA_15_0' */ ++/* Description: 'Destination Address 15..0' */ ++#define VR9_PMAC_DA3_DA_15_0_OFFSET 0x089 ++#define VR9_PMAC_DA3_DA_15_0_SHIFT 0 ++#define VR9_PMAC_DA3_DA_15_0_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PMAC VLAN Register' */ ++/* Bit: 'PRI' */ ++/* Description: 'VLAN Priority' */ ++#define VR9_PMAC_VLAN_PRI_OFFSET 0x08A ++#define VR9_PMAC_VLAN_PRI_SHIFT 13 ++#define VR9_PMAC_VLAN_PRI_SIZE 3 ++/* Bit: 'CFI' */ ++/* Description: 'Canonical Format Identifier' */ ++#define VR9_PMAC_VLAN_CFI_OFFSET 0x08A ++#define VR9_PMAC_VLAN_CFI_SHIFT 12 ++#define VR9_PMAC_VLAN_CFI_SIZE 1 ++/* Bit: 'VLAN_ID' */ ++/* Description: 'VLAN ID' */ ++#define VR9_PMAC_VLAN_VLAN_ID_OFFSET 0x08A ++#define VR9_PMAC_VLAN_VLAN_ID_SHIFT 0 ++#define VR9_PMAC_VLAN_VLAN_ID_SIZE 12 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PMAC Inter Packet Gapin RX Direction' */ ++/* Bit: 'REQ_DS_THRES' */ ++/* Description: 'Request Deassertion Threshold' */ ++#define VR9_PMAC_RX_IPG_REQ_DS_THRES_OFFSET 0x08B ++#define VR9_PMAC_RX_IPG_REQ_DS_THRES_SHIFT 8 ++#define VR9_PMAC_RX_IPG_REQ_DS_THRES_SIZE 1 ++/* Bit: 'REQ_AS_THRES' */ ++/* Description: 'Request Assertion Threshold' */ ++#define VR9_PMAC_RX_IPG_REQ_AS_THRES_OFFSET 0x08B ++#define VR9_PMAC_RX_IPG_REQ_AS_THRES_SHIFT 4 ++#define VR9_PMAC_RX_IPG_REQ_AS_THRES_SIZE 4 ++/* Bit: 'IPG_CNT' */ ++/* Description: 'IPG Counter' */ ++#define VR9_PMAC_RX_IPG_IPG_CNT_OFFSET 0x08B ++#define VR9_PMAC_RX_IPG_IPG_CNT_SHIFT 0 ++#define VR9_PMAC_RX_IPG_IPG_CNT_SIZE 4 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PMAC Special Tag Ethertype' */ ++/* Bit: 'ST_ETYPE' */ ++/* Description: 'Special Tag Ethertype' */ ++#define VR9_PMAC_ST_ETYPE_ST_ETYPE_OFFSET 0x08C ++#define VR9_PMAC_ST_ETYPE_ST_ETYPE_SHIFT 0 ++#define VR9_PMAC_ST_ETYPE_ST_ETYPE_SIZE 16 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PMAC Ethernet WAN Group' */ ++/* Bit: 'EWAN' */ ++/* Description: 'Ethernet WAN Group' */ ++#define VR9_PMAC_EWAN_EWAN_OFFSET 0x08D ++#define VR9_PMAC_EWAN_EWAN_SHIFT 0 ++#define VR9_PMAC_EWAN_EWAN_SIZE 6 ++/* -------------------------------------------------------------------------- */ ++/* Register: 'PMAC Control Register' */ ++/* Bit: 'SPEED' */ ++/* Description: 'Speed Control' */ ++#define VR9_PMAC_CTL_SPEED_OFFSET 0x08E ++#define VR9_PMAC_CTL_SPEED_SHIFT 1 ++#define VR9_PMAC_CTL_SPEED_SIZE 1 ++/* Bit: 'EN' */ ++/* Description: 'PMAC Enable' */ ++#define VR9_PMAC_CTL_EN_OFFSET 0x08E ++#define VR9_PMAC_CTL_EN_SHIFT 0 ++#define VR9_PMAC_CTL_EN_SIZE 1 ++/* -------------------------------------------------------------------------- */ ++#endif /* #ifndef _VR9_TOP_H */ +diff --git a/include/switch_api/commonReg.h b/include/switch_api/commonReg.h +new file mode 100644 +index 0000000..373defc +--- /dev/null ++++ b/include/switch_api/commonReg.h +@@ -0,0 +1,1312 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++#ifndef _IFX_ETHSW_REGMAPPERSELECTOR_H ++#define _IFX_ETHSW_REGMAPPERSELECTOR_H ++ ++typedef enum { ++ ARP_APT, /* (# 0) */ ++ ARP_MACA, /* (# 1) */ ++ ARP_RAPA, /* (# 2) */ ++ ARP_RAPOTH, /* (# 3) */ ++ ARP_RAPP, /* (# 4) */ ++ ARP_RAPPE, /* (# 5) */ ++ ARP_RAPTM, /* (# 6) */ ++ ARP_RPT, /* (# 7) */ ++ ARP_TAP, /* (# 8) */ ++ ARP_TAPTS, /* (# 9) */ ++ ARP_TRP, /* (# 10) */ ++ ARP_UPT, /* (# 11) */ ++ BIST_CTBR, /* (# 12) */ ++ BIST_DBBR, /* (# 13) */ ++ BIST_DONE, /* (# 14) */ ++ BIST_HIGTBR, /* (# 15) */ ++ BIST_HISTBR, /* (# 16) */ ++ BIST_LLTBR, /* (# 17) */ ++ BIST_LTBR, /* (# 18) */ ++ BUFFER_PFA, /* (# 19) */ ++ BUFFER_PFO0, /* (# 20) */ ++ BUFFER_PFO1, /* (# 21) */ ++ BUFFER_PFO2, /* (# 22) */ ++ BUFFER_PUA, /* (# 23) */ ++ BUFFER_PUO0, /* (# 24) */ ++ BUFFER_PUO1, /* (# 25) */ ++ BUFFER_PUO2, /* (# 26) */ ++ BUFFER_THA, /* (# 27) */ ++ BUFFER_THO, /* (# 28) */ ++ BUFFER_TLA, /* (# 29) */ ++ BUFFER_TLO, /* (# 30) */ ++ CHIPID_BOND, /* (# 31) */ ++ CHIPID_PC, /* (# 32) */ ++ CHIPID_VN, /* (# 33) */ ++ CONGESTION_EDSTX, /* (# 34) */ ++ CONGESTION_IJT, /* (# 35) */ ++ CONGESTION_IRSJA, /* (# 36) */ ++ CONGESTION_STORM_100_TH, /* (# 37) */ ++ CONGESTION_STORM_10_TH, /* (# 38) */ ++ CONGESTION_STORM_B, /* (# 39) */ ++ CONGESTION_STORM_M, /* (# 40) */ ++ CONGESTION_STORM_U, /* (# 41) */ ++ DIFFSERV_PQA, /* (# 42) */ ++ DIFFSERV_PQA01, /* (# 43) */ ++ DIFFSERV_PQA02, /* (# 44) */ ++ DIFFSERV_PQA03, /* (# 45) */ ++ DIFFSERV_PQA04, /* (# 46) */ ++ DIFFSERV_PQA05, /* (# 47) */ ++ DIFFSERV_PQA06, /* (# 48) */ ++ DIFFSERV_PQA07, /* (# 49) */ ++ DIFFSERV_PQA08, /* (# 50) */ ++ DIFFSERV_PQA09, /* (# 51) */ ++ DIFFSERV_PQA10, /* (# 52) */ ++ DIFFSERV_PQA11, /* (# 53) */ ++ DIFFSERV_PQA12, /* (# 54) */ ++ DIFFSERV_PQA13, /* (# 55) */ ++ DIFFSERV_PQA14, /* (# 56) */ ++ DIFFSERV_PQA15, /* (# 57) */ ++ DIFFSERV_PQB, /* (# 58) */ ++ DIFFSERV_PQB01, /* (# 59) */ ++ DIFFSERV_PQB02, /* (# 60) */ ++ DIFFSERV_PQB03, /* (# 61) */ ++ DIFFSERV_PQB04, /* (# 62) */ ++ DIFFSERV_PQB05, /* (# 63) */ ++ DIFFSERV_PQB06, /* (# 64) */ ++ DIFFSERV_PQB07, /* (# 65) */ ++ DIFFSERV_PQB08, /* (# 66) */ ++ DIFFSERV_PQB09, /* (# 67) */ ++ DIFFSERV_PQB10, /* (# 68) */ ++ DIFFSERV_PQB11, /* (# 69) */ ++ DIFFSERV_PQB12, /* (# 70) */ ++ DIFFSERV_PQB13, /* (# 71) */ ++ DIFFSERV_PQB14, /* (# 72) */ ++ DIFFSERV_PQB15, /* (# 73) */ ++ DIFFSERV_PQC, /* (# 74) */ ++ DIFFSERV_PQC01, /* (# 75) */ ++ DIFFSERV_PQC02, /* (# 76) */ ++ DIFFSERV_PQC03, /* (# 77) */ ++ DIFFSERV_PQC04, /* (# 78) */ ++ DIFFSERV_PQC05, /* (# 79) */ ++ DIFFSERV_PQC06, /* (# 80) */ ++ DIFFSERV_PQC07, /* (# 81) */ ++ DIFFSERV_PQC08, /* (# 82) */ ++ DIFFSERV_PQC09, /* (# 83) */ ++ DIFFSERV_PQC10, /* (# 84) */ ++ DIFFSERV_PQC11, /* (# 85) */ ++ DIFFSERV_PQC12, /* (# 86) */ ++ DIFFSERV_PQC13, /* (# 87) */ ++ DIFFSERV_PQC14, /* (# 88) */ ++ DIFFSERV_PQC15, /* (# 89) */ ++ DIFFSERV_PQD, /* (# 90) */ ++ DIFFSERV_PQD01, /* (# 91) */ ++ DIFFSERV_PQD02, /* (# 92) */ ++ DIFFSERV_PQD03, /* (# 93) */ ++ DIFFSERV_PQD04, /* (# 94) */ ++ DIFFSERV_PQD05, /* (# 95) */ ++ DIFFSERV_PQD06, /* (# 96) */ ++ DIFFSERV_PQD07, /* (# 97) */ ++ DIFFSERV_PQD08, /* (# 98) */ ++ DIFFSERV_PQD09, /* (# 99) */ ++ DIFFSERV_PQD10, /* (# 100) */ ++ DIFFSERV_PQD11, /* (# 101) */ ++ DIFFSERV_PQD12, /* (# 102) */ ++ DIFFSERV_PQD13, /* (# 103) */ ++ DIFFSERV_PQD14, /* (# 104) */ ++ DIFFSERV_PQD15, /* (# 105) */ ++ DOT1X_PRIORITY_1PPQ, /* (# 106) */ ++ DOT1X_PRIORITY_1PPQ1, /* (# 107) */ ++ DOT1X_PRIORITY_1PPQ2, /* (# 108) */ ++ DOT1X_PRIORITY_1PPQ3, /* (# 109) */ ++ DOT1X_PRIORITY_1PPQ4, /* (# 110) */ ++ DOT1X_PRIORITY_1PPQ5, /* (# 111) */ ++ DOT1X_PRIORITY_1PPQ6, /* (# 112) */ ++ DOT1X_PRIORITY_1PPQ7, /* (# 113) */ ++ GLOBAL_ATS, /* (# 114) */ ++ GLOBAL_CTTX, /* (# 115) */ ++ GLOBAL_DIE, /* (# 116) */ ++ GLOBAL_DII6P, /* (# 117) */ ++ GLOBAL_DIIP, /* (# 118) */ ++ GLOBAL_DIIPS, /* (# 119) */ ++ GLOBAL_DIS, /* (# 120) */ ++ GLOBAL_DIVS, /* (# 121) */ ++ GLOBAL_DMQ0, /* (# 122) */ ++ GLOBAL_DMQ1, /* (# 123) */ ++ GLOBAL_DMQ2, /* (# 124) */ ++ GLOBAL_DMQ3, /* (# 125) */ ++ GLOBAL_DPWECH, /* (# 126) */ ++ GLOBAL_DUPCOLSP, /* (# 127) */ ++ GLOBAL_ICRCCD, /* (# 128) */ ++ GLOBAL_ITENLMT, /* (# 129) */ ++ GLOBAL_ITRUNK, /* (# 130) */ ++ GLOBAL_LPE, /* (# 131) */ ++ GLOBAL_MPL, /* (# 132) */ ++ GLOBAL_P4M, /* (# 133) */ ++ GLOBAL_P5M, /* (# 134) */ ++ GLOBAL_P6M, /* (# 135) */ ++ GLOBAL_PCE, /* (# 136) */ ++ GLOBAL_PCR, /* (# 137) */ ++ GLOBAL_PHYBA, /* (# 138) */ ++ GLOBAL_RVID0, /* (# 139) */ ++ GLOBAL_RVID1, /* (# 140) */ ++ GLOBAL_RVIDFFF, /* (# 141) */ ++ GLOBAL_SE, /* (# 142) */ ++ GLOBAL_TSIPGE, /* (# 143) */ ++ INGRESS_FLOW_CTRL_B, /* (# 144) */ ++ INGRESS_FLOW_CTRL_BASE15_0, /* (# 145) */ ++ INGRESS_FLOW_CTRL_BASE17_16, /* (# 146) */ ++ INGRESS_FLOW_CTRL_EBASE15_0, /* (# 147) */ ++ INGRESS_FLOW_CTRL_EBASE17_16, /* (# 148) */ ++ INGRESS_FLOW_CTRL_F, /* (# 149) */ ++ IRQ_DBF, /* (# 150) */ ++ IRQ_DBFIE, /* (# 151) */ ++ IRQ_DBNF, /* (# 152) */ ++ IRQ_DBNFIE, /* (# 153) */ ++ IRQ_LTAD, /* (# 154) */ ++ IRQ_LTADIE, /* (# 155) */ ++ IRQ_LTF, /* (# 156) */ ++ IRQ_LTFIE, /* (# 157) */ ++ IRQ_PSC, /* (# 158) */ ++ IRQ_PSCIE, /* (# 159) */ ++ IRQ_PSV, /* (# 160) */ ++ IRQ_PSVIE, /* (# 161) */ ++ MAC_TABLE_ADDR15_0, /* (# 162) */ ++ MAC_TABLE_ADDR31_0, /* (# 163) */ ++ MAC_TABLE_ADDR31_16, /* (# 164) */ ++ MAC_TABLE_ADDR47_32, /* (# 165) */ ++ MAC_TABLE_ADDRS15_0, /* (# 166) */ ++ MAC_TABLE_ADDRS31_0, /* (# 167) */ ++ MAC_TABLE_ADDRS31_16, /* (# 168) */ ++ MAC_TABLE_ADDRS47_32, /* (# 169) */ ++ MAC_TABLE_BAD, /* (# 170) */ ++ MAC_TABLE_BUSY, /* (# 171) */ ++ MAC_TABLE_C_AC, /* (# 172) */ ++ MAC_TABLE_C_CMD, /* (# 173) */ ++ MAC_TABLE_C_FCE, /* (# 174) */ ++ MAC_TABLE_FID, /* (# 175) */ ++ MAC_TABLE_FIDS, /* (# 176) */ ++ MAC_TABLE_INFOT, /* (# 177) */ ++ MAC_TABLE_INFOTS, /* (# 178) */ ++ MAC_TABLE_ITAT, /* (# 179) */ ++ MAC_TABLE_ITATS, /* (# 180) */ ++ MAC_TABLE_OCP, /* (# 181) */ ++ MAC_TABLE_PMAP, /* (# 182) */ ++ MAC_TABLE_PMAPS, /* (# 183) */ ++ MAC_TABLE_RSLT, /* (# 184) */ ++ MAC_TABLE_S_AC, /* (# 185) */ ++ MAC_TABLE_S_CMD, /* (# 186) */ ++ MAC_TABLE_S_FCE, /* (# 187) */ ++ MCS, /* (# 188) */ ++ MDIO_MBUSY, /* (# 189) */ ++ MDIO_OP, /* (# 190) */ ++ MDIO_PHYAD, /* (# 191) */ ++ MDIO_RD, /* (# 192) */ ++ MDIO_REGAD, /* (# 193) */ ++ MDIO_WD, /* (# 194) */ ++ MIRROR_CCCRC, /* (# 195) */ ++ MIRROR_CPN, /* (# 196) */ ++ MIRROR_IGSTA, /* (# 197) */ ++ MIRROR_MCA, /* (# 198) */ ++ MIRROR_MLA, /* (# 199) */ ++ MIRROR_MPA, /* (# 200) */ ++ MIRROR_MRA, /* (# 201) */ ++ MIRROR_MSA, /* (# 202) */ ++ MIRROR_PAST, /* (# 203) */ ++ MIRROR_SNIFFPN, /* (# 204) */ ++ MIRROR_STRE, /* (# 205) */ ++ MIRROR_STTE, /* (# 206) */ ++ MULTICAST_ASC, /* (# 207) */ ++ MULTICAST_B01, /* (# 208) */ ++ MULTICAST_B224, /* (# 209) */ ++ MULTICAST_B33, /* (# 210) */ ++ MULTICAST_DAIPS, /* (# 211) */ ++ MULTICAST_DRP, /* (# 212) */ ++ MULTICAST_FMODE, /* (# 213) */ ++ MULTICAST_GID15_0, /* (# 214) */ ++ MULTICAST_GID31_16, /* (# 215) */ ++ MULTICAST_HIPI, /* (# 216) */ ++ MULTICAST_HISE, /* (# 217) */ ++ MULTICAST_HISFL, /* (# 218) */ ++ MULTICAST_ICMD, /* (# 219) */ ++ MULTICAST_IGMPV3E, /* (# 220) */ ++ MULTICAST_INVC, /* (# 221) */ ++ MULTICAST_IPMPT, /* (# 222) */ ++ MULTICAST_PORT, /* (# 223) */ ++ MULTICAST_PPPOEHR, /* (# 224) */ ++ MULTICAST_QI, /* (# 225) */ ++ MULTICAST_RV, /* (# 226) */ ++ MULTICAST_S3PMI, /* (# 227) */ ++ MULTICAST_S3PMV, /* (# 228) */ ++ MULTICAST_S4BUSY, /* (# 229) */ ++ MULTICAST_S4R, /* (# 230) */ ++ MULTICAST_SARE, /* (# 231) */ ++ MULTICAST_SCPA, /* (# 232) */ ++ MULTICAST_SCPP, /* (# 233) */ ++ MULTICAST_SCPPE, /* (# 234) */ ++ MULTICAST_SCPTCP, /* (# 235) */ ++ MULTICAST_SCPTMP, /* (# 236) */ ++ MULTICAST_SCPTSP, /* (# 237) */ ++ MULTICAST_SCPTTH, /* (# 238) */ ++ MULTICAST_SIP15_0, /* (# 239) */ ++ MULTICAST_SIP31_16, /* (# 240) */ ++ MULTICAST_SIP47_32, /* (# 241) */ ++ MULTICAST_SIPGID0, /* (# 242) */ ++ MULTICAST_SIPGID1, /* (# 243) */ ++ MULTICAST_SIPGID2, /* (# 244) */ ++ MULTICAST_TIMERC, /* (# 245) */ ++ PAUSE_ADDR15_0, /* (# 246) */ ++ PAUSE_ADDR31_16, /* (# 247) */ ++ PAUSE_ADDR39_32, /* (# 248) */ ++ PAUSE_ADDR47_41, /* (# 249) */ ++ PAUSE_PAC, /* (# 250) */ ++ PHY_INIT_PHYIE0, /* (# 251) */ ++ PHY_INIT_PHYIE01, /* (# 252) */ ++ PHY_INIT_PHYIE02, /* (# 253) */ ++ PHY_INIT_PHYIE03, /* (# 254) */ ++ PHY_INIT_PHYIE1, /* (# 255) */ ++ PHY_INIT_PHYIE11, /* (# 256) */ ++ PHY_INIT_PHYIE12, /* (# 257) */ ++ PHY_INIT_PHYIE13, /* (# 258) */ ++ PHY_INIT_PHYIE2, /* (# 259) */ ++ PHY_INIT_PHYIE21, /* (# 260) */ ++ PHY_INIT_PHYIE22, /* (# 261) */ ++ PHY_INIT_PHYIE23, /* (# 262) */ ++ PHY_INIT_PHYIE3, /* (# 263) */ ++ PHY_INIT_PHYIE31, /* (# 264) */ ++ PHY_INIT_PHYIE32, /* (# 265) */ ++ PHY_INIT_PHYIE33, /* (# 266) */ ++ PHY_INIT_PHYIE4, /* (# 267) */ ++ PHY_INIT_PHYIE41, /* (# 268) */ ++ PHY_INIT_PHYIE42, /* (# 269) */ ++ PHY_INIT_PHYIE43, /* (# 270) */ ++ PHY_INIT_PHYIE5, /* (# 271) */ ++ PHY_INIT_PHYIE51, /* (# 272) */ ++ PHY_INIT_PHYIE52, /* (# 273) */ ++ PHY_INIT_PHYIE53, /* (# 274) */ ++ PHY_INIT_PHYIE6, /* (# 275) */ ++ PHY_INIT_PHYIE61, /* (# 276) */ ++ PHY_INIT_PHYIE62, /* (# 277) */ ++ PHY_INIT_PHYIE63, /* (# 278) */ ++ PHY_INIT_REGA, /* (# 279) */ ++ PHY_INIT_REGA1, /* (# 280) */ ++ PHY_INIT_REGA2, /* (# 281) */ ++ PHY_INIT_REGA3, /* (# 282) */ ++ PHY_INIT_REGD, /* (# 283) */ ++ PHY_INIT_REGD1, /* (# 284) */ ++ PHY_INIT_REGD2, /* (# 285) */ ++ PHY_INIT_REGD3, /* (# 286) */ ++ PMAC_ADD, /* (# 287) */ ++ PMAC_ADD_CRC, /* (# 288) */ ++ PMAC_AS, /* (# 289) */ ++ PMAC_CFI, /* (# 290) */ ++ PMAC_DA_31_0, /* (# 291) */ ++ PMAC_DA_47_32, /* (# 292) */ ++ PMAC_IDIS_REQ_WM, /* (# 293) */ ++ PMAC_IPG_RX_CNT, /* (# 294) */ ++ PMAC_IPG_TX_CNT, /* (# 295) */ ++ PMAC_IREQ_WM, /* (# 296) */ ++ PMAC_PRI, /* (# 297) */ ++ PMAC_RC, /* (# 298) */ ++ PMAC_RL2, /* (# 299) */ ++ PMAC_RXSH, /* (# 300) */ ++ PMAC_SA_31_0, /* (# 301) */ ++ PMAC_SA_47_32, /* (# 302) */ ++ PMAC_TAG, /* (# 303) */ ++ PMAC_TYPE_LEN, /* (# 304) */ ++ PMAC_VLAN_ID, /* (# 305) */ ++ PORT_AD, /* (# 306) */ ++ PORT_AD1, /* (# 307) */ ++ PORT_AD2, /* (# 308) */ ++ PORT_AD3, /* (# 309) */ ++ PORT_AD4, /* (# 310) */ ++ PORT_AD5, /* (# 311) */ ++ PORT_AD6, /* (# 312) */ ++ PORT_BP, /* (# 313) */ ++ PORT_DFWD, /* (# 314) */ ++ PORT_DFWD1, /* (# 315) */ ++ PORT_DFWD2, /* (# 316) */ ++ PORT_DSV821X, /* (# 317) */ ++ PORT_DSV821X1, /* (# 318) */ ++ PORT_DSV821X2, /* (# 319) */ ++ PORT_EGRESS_PSPQ0TR, /* (# 320) */ ++ PORT_EGRESS_PSPQ0TR1, /* (# 321) */ ++ PORT_EGRESS_PSPQ0TR2, /* (# 322) */ ++ PORT_EGRESS_PSPQ0TR3, /* (# 323) */ ++ PORT_EGRESS_PSPQ0TR4, /* (# 324) */ ++ PORT_EGRESS_PSPQ0TR5, /* (# 325) */ ++ PORT_EGRESS_PSPQ0TR6, /* (# 326) */ ++ PORT_EGRESS_PSPQ1TR, /* (# 327) */ ++ PORT_EGRESS_PSPQ1TR1, /* (# 328) */ ++ PORT_EGRESS_PSPQ1TR2, /* (# 329) */ ++ PORT_EGRESS_PSPQ1TR3, /* (# 330) */ ++ PORT_EGRESS_PSPQ1TR4, /* (# 331) */ ++ PORT_EGRESS_PSPQ1TR5, /* (# 332) */ ++ PORT_EGRESS_PSPQ1TR6, /* (# 333) */ ++ PORT_EGRESS_PSPQ2TR, /* (# 334) */ ++ PORT_EGRESS_PSPQ2TR1, /* (# 335) */ ++ PORT_EGRESS_PSPQ2TR2, /* (# 336) */ ++ PORT_EGRESS_PSPQ2TR3, /* (# 337) */ ++ PORT_EGRESS_PSPQ2TR4, /* (# 338) */ ++ PORT_EGRESS_PSPQ2TR5, /* (# 339) */ ++ PORT_EGRESS_PSPQ2TR6, /* (# 340) */ ++ PORT_EGRESS_PSPQ3TR, /* (# 341) */ ++ PORT_EGRESS_PSPQ3TR1, /* (# 342) */ ++ PORT_EGRESS_PSPQ3TR2, /* (# 343) */ ++ PORT_EGRESS_PSPQ3TR3, /* (# 344) */ ++ PORT_EGRESS_PSPQ3TR4, /* (# 345) */ ++ PORT_EGRESS_PSPQ3TR5, /* (# 346) */ ++ PORT_EGRESS_PSPQ3TR6, /* (# 347) */ ++ PORT_EGRESS_PWQ0TR, /* (# 348) */ ++ PORT_EGRESS_PWQ0TR1, /* (# 349) */ ++ PORT_EGRESS_PWQ0TR2, /* (# 350) */ ++ PORT_EGRESS_PWQ0TR3, /* (# 351) */ ++ PORT_EGRESS_PWQ0TR4, /* (# 352) */ ++ PORT_EGRESS_PWQ0TR5, /* (# 353) */ ++ PORT_EGRESS_PWQ0TR6, /* (# 354) */ ++ PORT_EGRESS_PWQ1TR, /* (# 355) */ ++ PORT_EGRESS_PWQ1TR1, /* (# 356) */ ++ PORT_EGRESS_PWQ1TR2, /* (# 357) */ ++ PORT_EGRESS_PWQ1TR3, /* (# 358) */ ++ PORT_EGRESS_PWQ1TR4, /* (# 359) */ ++ PORT_EGRESS_PWQ1TR5, /* (# 360) */ ++ PORT_EGRESS_PWQ1TR6, /* (# 361) */ ++ PORT_EGRESS_PWQ2TR, /* (# 362) */ ++ PORT_EGRESS_PWQ2TR1, /* (# 363) */ ++ PORT_EGRESS_PWQ2TR2, /* (# 364) */ ++ PORT_EGRESS_PWQ2TR3, /* (# 365) */ ++ PORT_EGRESS_PWQ2TR4, /* (# 366) */ ++ PORT_EGRESS_PWQ2TR5, /* (# 367) */ ++ PORT_EGRESS_PWQ2TR6, /* (# 368) */ ++ PORT_EGRESS_PWQ3TR, /* (# 369) */ ++ PORT_EGRESS_PWQ3TR1, /* (# 370) */ ++ PORT_EGRESS_PWQ3TR2, /* (# 371) */ ++ PORT_EGRESS_PWQ3TR3, /* (# 372) */ ++ PORT_EGRESS_PWQ3TR4, /* (# 373) */ ++ PORT_EGRESS_PWQ3TR5, /* (# 374) */ ++ PORT_EGRESS_PWQ3TR6, /* (# 375) */ ++ PORT_FILTER_ATUF, /* (# 376) */ ++ PORT_FILTER_ATUF1, /* (# 377) */ ++ PORT_FILTER_ATUF2, /* (# 378) */ ++ PORT_FILTER_ATUF3, /* (# 379) */ ++ PORT_FILTER_ATUF4, /* (# 380) */ ++ PORT_FILTER_ATUF5, /* (# 381) */ ++ PORT_FILTER_ATUF6, /* (# 382) */ ++ PORT_FILTER_ATUF7, /* (# 383) */ ++ PORT_FILTER_BASEPT, /* (# 384) */ ++ PORT_FILTER_BASEPT1, /* (# 385) */ ++ PORT_FILTER_BASEPT2, /* (# 386) */ ++ PORT_FILTER_BASEPT3, /* (# 387) */ ++ PORT_FILTER_BASEPT4, /* (# 388) */ ++ PORT_FILTER_BASEPT5, /* (# 389) */ ++ PORT_FILTER_BASEPT6, /* (# 390) */ ++ PORT_FILTER_BASEPT7, /* (# 391) */ ++ PORT_FILTER_COMP, /* (# 392) */ ++ PORT_FILTER_COMP1, /* (# 393) */ ++ PORT_FILTER_COMP2, /* (# 394) */ ++ PORT_FILTER_COMP3, /* (# 395) */ ++ PORT_FILTER_COMP4, /* (# 396) */ ++ PORT_FILTER_COMP5, /* (# 397) */ ++ PORT_FILTER_COMP6, /* (# 398) */ ++ PORT_FILTER_COMP7, /* (# 399) */ ++ PORT_FILTER_PRANGE, /* (# 400) */ ++ PORT_FILTER_PRANGE1, /* (# 401) */ ++ PORT_FILTER_PRANGE2, /* (# 402) */ ++ PORT_FILTER_PRANGE3, /* (# 403) */ ++ PORT_FILTER_PRANGE4, /* (# 404) */ ++ PORT_FILTER_PRANGE5, /* (# 405) */ ++ PORT_FILTER_PRANGE6, /* (# 406) */ ++ PORT_FILTER_PRANGE7, /* (# 407) */ ++ PORT_FILTER_TUPF, /* (# 408) */ ++ PORT_FILTER_TUPF1, /* (# 409) */ ++ PORT_FILTER_TUPF2, /* (# 410) */ ++ PORT_FILTER_TUPF3, /* (# 411) */ ++ PORT_FILTER_TUPF4, /* (# 412) */ ++ PORT_FILTER_TUPF5, /* (# 413) */ ++ PORT_FILTER_TUPF6, /* (# 414) */ ++ PORT_FILTER_TUPF7, /* (# 415) */ ++ PORT_FLD, /* (# 416) */ ++ PORT_FLD1, /* (# 417) */ ++ PORT_FLD2, /* (# 418) */ ++ PORT_FLD3, /* (# 419) */ ++ PORT_FLD4, /* (# 420) */ ++ PORT_FLD5, /* (# 421) */ ++ PORT_FLD6, /* (# 422) */ ++ PORT_FLP, /* (# 423) */ ++ PORT_FLP1, /* (# 424) */ ++ PORT_FLP2, /* (# 425) */ ++ PORT_FLP3, /* (# 426) */ ++ PORT_FLP4, /* (# 427) */ ++ PORT_FLP5, /* (# 428) */ ++ PORT_FLP6, /* (# 429) */ ++ PORT_IFNTE, /* (# 430) */ ++ PORT_IFNTE1, /* (# 431) */ ++ PORT_IFNTE2, /* (# 432) */ ++ PORT_IFNTE3, /* (# 433) */ ++ PORT_IFNTE4, /* (# 434) */ ++ PORT_IFNTE5, /* (# 435) */ ++ PORT_IFNTE6, /* (# 436) */ ++ PORT_IMTE, /* (# 437) */ ++ PORT_IMTE1, /* (# 438) */ ++ PORT_IMTE2, /* (# 439) */ ++ PORT_IMTE3, /* (# 440) */ ++ PORT_IMTE4, /* (# 441) */ ++ PORT_IMTE5, /* (# 442) */ ++ PORT_IMTE6, /* (# 443) */ ++ PORT_INGRESS_PITR, /* (# 444) */ ++ PORT_INGRESS_PITR1, /* (# 445) */ ++ PORT_INGRESS_PITR2, /* (# 446) */ ++ PORT_INGRESS_PITR3, /* (# 447) */ ++ PORT_INGRESS_PITR4, /* (# 448) */ ++ PORT_INGRESS_PITR5, /* (# 449) */ ++ PORT_INGRESS_PITR6, /* (# 450) */ ++ PORT_INGRESS_PITT, /* (# 451) */ ++ PORT_INGRESS_PITT1, /* (# 452) */ ++ PORT_INGRESS_PITT2, /* (# 453) */ ++ PORT_INGRESS_PITT3, /* (# 454) */ ++ PORT_INGRESS_PITT4, /* (# 455) */ ++ PORT_INGRESS_PITT5, /* (# 456) */ ++ PORT_INGRESS_PITT6, /* (# 457) */ ++ PORT_IPMO, /* (# 458) */ ++ PORT_IPMO1, /* (# 459) */ ++ PORT_IPMO2, /* (# 460) */ ++ PORT_IPMO3, /* (# 461) */ ++ PORT_IPMO4, /* (# 462) */ ++ PORT_IPMO5, /* (# 463) */ ++ PORT_IPMO6, /* (# 464) */ ++ PORT_IPOVTU, /* (# 465) */ ++ PORT_IPOVTU1, /* (# 466) */ ++ PORT_IPOVTU2, /* (# 467) */ ++ PORT_IPOVTU3, /* (# 468) */ ++ PORT_IPOVTU4, /* (# 469) */ ++ PORT_IPOVTU5, /* (# 470) */ ++ PORT_IPOVTU6, /* (# 471) */ ++ PORT_IPVLAN, /* (# 472) */ ++ PORT_IPVLAN1, /* (# 473) */ ++ PORT_IPVLAN2, /* (# 474) */ ++ PORT_IPVLAN3, /* (# 475) */ ++ PORT_IPVLAN4, /* (# 476) */ ++ PORT_IPVLAN5, /* (# 477) */ ++ PORT_IPVLAN6, /* (# 478) */ ++ PORT_LD, /* (# 479) */ ++ PORT_LD1, /* (# 480) */ ++ PORT_LD2, /* (# 481) */ ++ PORT_LD3, /* (# 482) */ ++ PORT_LD4, /* (# 483) */ ++ PORT_LD5, /* (# 484) */ ++ PORT_LD6, /* (# 485) */ ++ PORT_MNA24, /* (# 486) */ ++ PORT_MNA241, /* (# 487) */ ++ PORT_MNA242, /* (# 488) */ ++ PORT_MNA243, /* (# 489) */ ++ PORT_MNA244, /* (# 490) */ ++ PORT_MNA245, /* (# 491) */ ++ PORT_MNA246, /* (# 492) */ ++ PORT_MP, /* (# 493) */ ++ PORT_PAS, /* (# 494) */ ++ PORT_PAS1, /* (# 495) */ ++ PORT_PAS2, /* (# 496) */ ++ PORT_PAS3, /* (# 497) */ ++ PORT_PAS4, /* (# 498) */ ++ PORT_PAS5, /* (# 499) */ ++ PORT_PAS6, /* (# 500) */ ++ PORT_PDS, /* (# 501) */ ++ PORT_PDS1, /* (# 502) */ ++ PORT_PDS2, /* (# 503) */ ++ PORT_PDS3, /* (# 504) */ ++ PORT_PDS4, /* (# 505) */ ++ PORT_PDS5, /* (# 506) */ ++ PORT_PDS6, /* (# 507) */ ++ PORT_PFCS, /* (# 508) */ ++ PORT_PFCS1, /* (# 509) */ ++ PORT_PFCS2, /* (# 510) */ ++ PORT_PFCS3, /* (# 511) */ ++ PORT_PFCS4, /* (# 512) */ ++ PORT_PFCS5, /* (# 513) */ ++ PORT_PFCS6, /* (# 514) */ ++ PORT_PLS, /* (# 515) */ ++ PORT_PLS1, /* (# 516) */ ++ PORT_PLS2, /* (# 517) */ ++ PORT_PLS3, /* (# 518) */ ++ PORT_PLS4, /* (# 519) */ ++ PORT_PLS5, /* (# 520) */ ++ PORT_PLS6, /* (# 521) */ ++ PORT_PM, /* (# 522) */ ++ PORT_PM1, /* (# 523) */ ++ PORT_PM2, /* (# 524) */ ++ PORT_PM3, /* (# 525) */ ++ PORT_PM4, /* (# 526) */ ++ PORT_PM5, /* (# 527) */ ++ PORT_PM6, /* (# 528) */ ++ PORT_PPPOEP, /* (# 529) */ ++ PORT_PPPOEP1, /* (# 530) */ ++ PORT_PPPOEP2, /* (# 531) */ ++ PORT_PPPOEP3, /* (# 532) */ ++ PORT_PPPOEP4, /* (# 533) */ ++ PORT_PPPOEP5, /* (# 534) */ ++ PORT_PPPOEP6, /* (# 535) */ ++ PORT_PSHS, /* (# 536) */ ++ PORT_PSHS1, /* (# 537) */ ++ PORT_PSHS2, /* (# 538) */ ++ PORT_PSHS3, /* (# 539) */ ++ PORT_PSHS4, /* (# 540) */ ++ PORT_PSHS5, /* (# 541) */ ++ PORT_PSHS6, /* (# 542) */ ++ PORT_PSS, /* (# 543) */ ++ PORT_PSS1, /* (# 544) */ ++ PORT_PSS2, /* (# 545) */ ++ PORT_PSS3, /* (# 546) */ ++ PORT_PSS4, /* (# 547) */ ++ PORT_PSS5, /* (# 548) */ ++ PORT_PSS6, /* (# 549) */ ++ PORT_REDIR, /* (# 550) */ ++ PORT_REDIR1, /* (# 551) */ ++ PORT_REDIR2, /* (# 552) */ ++ PORT_RGMII_GMII_P0CKIO, /* (# 553) */ ++ PORT_RGMII_GMII_P0DUP, /* (# 554) */ ++ PORT_RGMII_GMII_P0FCE, /* (# 555) */ ++ PORT_RGMII_GMII_P0FEQ, /* (# 556) */ ++ PORT_RGMII_GMII_P0IS, /* (# 557) */ ++ PORT_RGMII_GMII_P0RDLY, /* (# 558) */ ++ PORT_RGMII_GMII_P0SPD, /* (# 559) */ ++ PORT_RGMII_GMII_P0TDLY, /* (# 560) */ ++ PORT_RGMII_GMII_P1CKIO, /* (# 561) */ ++ PORT_RGMII_GMII_P1DUP, /* (# 562) */ ++ PORT_RGMII_GMII_P1FCE, /* (# 563) */ ++ PORT_RGMII_GMII_P1FEQ, /* (# 564) */ ++ PORT_RGMII_GMII_P1IS, /* (# 565) */ ++ PORT_RGMII_GMII_P1RDLY, /* (# 566) */ ++ PORT_RGMII_GMII_P1SPD, /* (# 567) */ ++ PORT_RGMII_GMII_P1TDLY, /* (# 568) */ ++ PORT_RGMII_GMII_P4DUP, /* (# 569) */ ++ PORT_RGMII_GMII_P4FCE, /* (# 570) */ ++ PORT_RGMII_GMII_P4SPD, /* (# 571) */ ++ PORT_RGMII_GMII_P5DUP, /* (# 572) */ ++ PORT_RGMII_GMII_P5FCE, /* (# 573) */ ++ PORT_RGMII_GMII_P5SPD, /* (# 574) */ ++ PORT_RGMII_GMII_P6DUP, /* (# 575) */ ++ PORT_RGMII_GMII_P6FCE, /* (# 576) */ ++ PORT_RGMII_GMII_P6SPD, /* (# 577) */ ++ PORT_RMWFQ, /* (# 578) */ ++ PORT_RMWFQ1, /* (# 579) */ ++ PORT_RMWFQ2, /* (# 580) */ ++ PORT_RMWFQ3, /* (# 581) */ ++ PORT_RMWFQ4, /* (# 582) */ ++ PORT_RMWFQ5, /* (# 583) */ ++ PORT_RMWFQ6, /* (# 584) */ ++ PORT_RP, /* (# 585) */ ++ PORT_SPE, /* (# 586) */ ++ PORT_SPE1, /* (# 587) */ ++ PORT_SPE2, /* (# 588) */ ++ PORT_SPE3, /* (# 589) */ ++ PORT_SPE4, /* (# 590) */ ++ PORT_SPE5, /* (# 591) */ ++ PORT_SPE6, /* (# 592) */ ++ PORT_SPS, /* (# 593) */ ++ PORT_SPS1, /* (# 594) */ ++ PORT_SPS2, /* (# 595) */ ++ PORT_SPS3, /* (# 596) */ ++ PORT_SPS4, /* (# 597) */ ++ PORT_SPS5, /* (# 598) */ ++ PORT_SPS6, /* (# 599) */ ++ PORT_TCPE, /* (# 600) */ ++ PORT_TCPE1, /* (# 601) */ ++ PORT_TCPE2, /* (# 602) */ ++ PORT_TCPE3, /* (# 603) */ ++ PORT_TCPE4, /* (# 604) */ ++ PORT_TCPE5, /* (# 605) */ ++ PORT_TCPE6, /* (# 606) */ ++ PORT_TPE, /* (# 607) */ ++ PORT_TPE1, /* (# 608) */ ++ PORT_TPE2, /* (# 609) */ ++ PORT_TPE3, /* (# 610) */ ++ PORT_TPE4, /* (# 611) */ ++ PORT_TPE5, /* (# 612) */ ++ PORT_TPE6, /* (# 613) */ ++ PORT_UP, /* (# 614) */ ++ PORT_VLAN_AOVTP, /* (# 615) */ ++ PORT_VLAN_AOVTP1, /* (# 616) */ ++ PORT_VLAN_AOVTP2, /* (# 617) */ ++ PORT_VLAN_AOVTP3, /* (# 618) */ ++ PORT_VLAN_AOVTP4, /* (# 619) */ ++ PORT_VLAN_AOVTP5, /* (# 620) */ ++ PORT_VLAN_AOVTP6, /* (# 621) */ ++ PORT_VLAN_BYPASS, /* (# 622) */ ++ PORT_VLAN_BYPASS1, /* (# 623) */ ++ PORT_VLAN_BYPASS2, /* (# 624) */ ++ PORT_VLAN_BYPASS3, /* (# 625) */ ++ PORT_VLAN_BYPASS4, /* (# 626) */ ++ PORT_VLAN_BYPASS5, /* (# 627) */ ++ PORT_VLAN_BYPASS6, /* (# 628) */ ++ PORT_VLAN_DFID, /* (# 629) */ ++ PORT_VLAN_DFID1, /* (# 630) */ ++ PORT_VLAN_DFID2, /* (# 631) */ ++ PORT_VLAN_DFID3, /* (# 632) */ ++ PORT_VLAN_DFID4, /* (# 633) */ ++ PORT_VLAN_DFID5, /* (# 634) */ ++ PORT_VLAN_DFID6, /* (# 635) */ ++ PORT_VLAN_DVPM, /* (# 636) */ ++ PORT_VLAN_DVPM1, /* (# 637) */ ++ PORT_VLAN_DVPM2, /* (# 638) */ ++ PORT_VLAN_DVPM3, /* (# 639) */ ++ PORT_VLAN_DVPM4, /* (# 640) */ ++ PORT_VLAN_DVPM5, /* (# 641) */ ++ PORT_VLAN_DVPM6, /* (# 642) */ ++ PORT_VLAN_PP, /* (# 643) */ ++ PORT_VLAN_PP1, /* (# 644) */ ++ PORT_VLAN_PP2, /* (# 645) */ ++ PORT_VLAN_PP3, /* (# 646) */ ++ PORT_VLAN_PP4, /* (# 647) */ ++ PORT_VLAN_PP5, /* (# 648) */ ++ PORT_VLAN_PP6, /* (# 649) */ ++ PORT_VLAN_PPE, /* (# 650) */ ++ PORT_VLAN_PPE1, /* (# 651) */ ++ PORT_VLAN_PPE2, /* (# 652) */ ++ PORT_VLAN_PPE3, /* (# 653) */ ++ PORT_VLAN_PPE4, /* (# 654) */ ++ PORT_VLAN_PPE5, /* (# 655) */ ++ PORT_VLAN_PPE6, /* (# 656) */ ++ PORT_VLAN_PVID, /* (# 657) */ ++ PORT_VLAN_PVID1, /* (# 658) */ ++ PORT_VLAN_PVID2, /* (# 659) */ ++ PORT_VLAN_PVID3, /* (# 660) */ ++ PORT_VLAN_PVID4, /* (# 661) */ ++ PORT_VLAN_PVID5, /* (# 662) */ ++ PORT_VLAN_PVID6, /* (# 663) */ ++ PORT_VLAN_PVTAGMP, /* (# 664) */ ++ PORT_VLAN_PVTAGMP1, /* (# 665) */ ++ PORT_VLAN_PVTAGMP2, /* (# 666) */ ++ PORT_VLAN_PVTAGMP3, /* (# 667) */ ++ PORT_VLAN_PVTAGMP4, /* (# 668) */ ++ PORT_VLAN_PVTAGMP5, /* (# 669) */ ++ PORT_VLAN_PVTAGMP6, /* (# 670) */ ++ PORT_VLAN_TBVE, /* (# 671) */ ++ PORT_VLAN_TBVE1, /* (# 672) */ ++ PORT_VLAN_TBVE2, /* (# 673) */ ++ PORT_VLAN_TBVE3, /* (# 674) */ ++ PORT_VLAN_TBVE4, /* (# 675) */ ++ PORT_VLAN_TBVE5, /* (# 676) */ ++ PORT_VLAN_TBVE6, /* (# 677) */ ++ PORT_VLAN_VC, /* (# 678) */ ++ PORT_VLAN_VC1, /* (# 679) */ ++ PORT_VLAN_VC2, /* (# 680) */ ++ PORT_VLAN_VC3, /* (# 681) */ ++ PORT_VLAN_VC4, /* (# 682) */ ++ PORT_VLAN_VC5, /* (# 683) */ ++ PORT_VLAN_VC6, /* (# 684) */ ++ PORT_VLAN_VMCE, /* (# 685) */ ++ PORT_VLAN_VMCE1, /* (# 686) */ ++ PORT_VLAN_VMCE2, /* (# 687) */ ++ PORT_VLAN_VMCE3, /* (# 688) */ ++ PORT_VLAN_VMCE4, /* (# 689) */ ++ PORT_VLAN_VMCE5, /* (# 690) */ ++ PORT_VLAN_VMCE6, /* (# 691) */ ++ PORT_VLAN_VSD, /* (# 692) */ ++ PORT_VLAN_VSD1, /* (# 693) */ ++ PORT_VLAN_VSD2, /* (# 694) */ ++ PORT_VLAN_VSD3, /* (# 695) */ ++ PORT_VLAN_VSD4, /* (# 696) */ ++ PORT_VLAN_VSD5, /* (# 697) */ ++ PORT_VLAN_VSD6, /* (# 698) */ ++ PORT_VPE, /* (# 699) */ ++ PORT_VPE1, /* (# 700) */ ++ PORT_VPE2, /* (# 701) */ ++ PORT_VPE3, /* (# 702) */ ++ PORT_VPE4, /* (# 703) */ ++ PORT_VPE5, /* (# 704) */ ++ PORT_VPE6, /* (# 705) */ ++ PPPOE_SID, /* (# 706) */ ++ PROTOCOL_FILTER_APF, /* (# 707) */ ++ PROTOCOL_FILTER_APF1, /* (# 708) */ ++ PROTOCOL_FILTER_APF2, /* (# 709) */ ++ PROTOCOL_FILTER_APF3, /* (# 710) */ ++ PROTOCOL_FILTER_APF4, /* (# 711) */ ++ PROTOCOL_FILTER_APF5, /* (# 712) */ ++ PROTOCOL_FILTER_APF6, /* (# 713) */ ++ PROTOCOL_FILTER_APF7, /* (# 714) */ ++ PROTOCOL_FILTER_PFR0, /* (# 715) */ ++ PROTOCOL_FILTER_PFR01, /* (# 716) */ ++ PROTOCOL_FILTER_PFR02, /* (# 717) */ ++ PROTOCOL_FILTER_PFR03, /* (# 718) */ ++ PROTOCOL_FILTER_PFR1, /* (# 719) */ ++ PROTOCOL_FILTER_PFR11, /* (# 720) */ ++ PROTOCOL_FILTER_PFR12, /* (# 721) */ ++ PROTOCOL_FILTER_PFR13, /* (# 722) */ ++ PROTOCOL_FILTER_PFR2, /* (# 723) */ ++ PROTOCOL_FILTER_PFR21, /* (# 724) */ ++ PROTOCOL_FILTER_PFR3, /* (# 725) */ ++ PROTOCOL_FILTER_PFR31, /* (# 726) */ ++ RA00_ACT, /* (# 727) */ ++ RA00_ACT1, /* (# 728) */ ++ RA00_ACT2, /* (# 729) */ ++ RA00_ACT3, /* (# 730) */ ++ RA00_ACT4, /* (# 731) */ ++ RA00_ACT5, /* (# 732) */ ++ RA00_ACT6, /* (# 733) */ ++ RA00_ACT7, /* (# 734) */ ++ RA00_ACT8, /* (# 735) */ ++ RA00_ACT9, /* (# 736) */ ++ RA00_ACT10, /* (# 737) */ ++ RA00_ACT11, /* (# 738) */ ++ RA00_ACT12, /* (# 739) */ ++ RA00_ACT13, /* (# 740) */ ++ RA00_ACT14, /* (# 741) */ ++ RA00_ACT15, /* (# 742) */ ++ RA00_ACT16, /* (# 743) */ ++ RA00_ACT17, /* (# 744) */ ++ RA00_ACT18, /* (# 745) */ ++ RA00_ACT19, /* (# 746) */ ++ RA00_ACT20, /* (# 747) */ ++ RA00_ACT21, /* (# 748) */ ++ RA00_ACT22, /* (# 749) */ ++ RA00_ACT23, /* (# 750) */ ++ RA00_CV, /* (# 751) */ ++ RA00_CV1, /* (# 752) */ ++ RA00_CV2, /* (# 753) */ ++ RA00_CV3, /* (# 754) */ ++ RA00_CV4, /* (# 755) */ ++ RA00_CV5, /* (# 756) */ ++ RA00_CV6, /* (# 757) */ ++ RA00_CV7, /* (# 758) */ ++ RA00_CV8, /* (# 759) */ ++ RA00_CV9, /* (# 760) */ ++ RA00_CV10, /* (# 761) */ ++ RA00_CV11, /* (# 762) */ ++ RA00_CV12, /* (# 763) */ ++ RA00_CV13, /* (# 764) */ ++ RA00_CV14, /* (# 765) */ ++ RA00_CV15, /* (# 766) */ ++ RA00_CV16, /* (# 767) */ ++ RA00_CV17, /* (# 768) */ ++ RA00_CV18, /* (# 769) */ ++ RA00_CV19, /* (# 770) */ ++ RA00_CV20, /* (# 771) */ ++ RA00_CV21, /* (# 772) */ ++ RA00_CV22, /* (# 773) */ ++ RA00_CV23, /* (# 774) */ ++ RA00_MG, /* (# 775) */ ++ RA00_MG1, /* (# 776) */ ++ RA00_MG2, /* (# 777) */ ++ RA00_MG3, /* (# 778) */ ++ RA00_MG4, /* (# 779) */ ++ RA00_MG5, /* (# 780) */ ++ RA00_MG6, /* (# 781) */ ++ RA00_MG7, /* (# 782) */ ++ RA00_MG8, /* (# 783) */ ++ RA00_MG9, /* (# 784) */ ++ RA00_MG10, /* (# 785) */ ++ RA00_MG11, /* (# 786) */ ++ RA00_MG12, /* (# 787) */ ++ RA00_MG13, /* (# 788) */ ++ RA00_MG14, /* (# 789) */ ++ RA00_MG15, /* (# 790) */ ++ RA00_MG16, /* (# 791) */ ++ RA00_MG17, /* (# 792) */ ++ RA00_MG18, /* (# 793) */ ++ RA00_MG19, /* (# 794) */ ++ RA00_MG20, /* (# 795) */ ++ RA00_MG21, /* (# 796) */ ++ RA00_MG22, /* (# 797) */ ++ RA00_MG23, /* (# 798) */ ++ RA00_SPAN, /* (# 799) */ ++ RA00_SPAN1, /* (# 800) */ ++ RA00_SPAN2, /* (# 801) */ ++ RA00_SPAN3, /* (# 802) */ ++ RA00_SPAN4, /* (# 803) */ ++ RA00_SPAN5, /* (# 804) */ ++ RA00_SPAN6, /* (# 805) */ ++ RA00_SPAN7, /* (# 806) */ ++ RA00_SPAN8, /* (# 807) */ ++ RA00_SPAN9, /* (# 808) */ ++ RA00_SPAN10, /* (# 809) */ ++ RA00_SPAN11, /* (# 810) */ ++ RA00_SPAN12, /* (# 811) */ ++ RA00_SPAN13, /* (# 812) */ ++ RA00_SPAN14, /* (# 813) */ ++ RA00_SPAN15, /* (# 814) */ ++ RA00_SPAN16, /* (# 815) */ ++ RA00_SPAN17, /* (# 816) */ ++ RA00_SPAN18, /* (# 817) */ ++ RA00_SPAN19, /* (# 818) */ ++ RA00_SPAN20, /* (# 819) */ ++ RA00_SPAN21, /* (# 820) */ ++ RA00_SPAN22, /* (# 821) */ ++ RA00_SPAN23, /* (# 822) */ ++ RA00_TXTAG, /* (# 823) */ ++ RA00_TXTAG1, /* (# 824) */ ++ RA00_TXTAG2, /* (# 825) */ ++ RA00_TXTAG3, /* (# 826) */ ++ RA00_TXTAG4, /* (# 827) */ ++ RA00_TXTAG5, /* (# 828) */ ++ RA00_TXTAG6, /* (# 829) */ ++ RA00_TXTAG7, /* (# 830) */ ++ RA00_TXTAG8, /* (# 831) */ ++ RA00_TXTAG9, /* (# 832) */ ++ RA00_TXTAG10, /* (# 833) */ ++ RA00_TXTAG11, /* (# 834) */ ++ RA00_TXTAG12, /* (# 835) */ ++ RA00_TXTAG13, /* (# 836) */ ++ RA00_TXTAG14, /* (# 837) */ ++ RA00_TXTAG15, /* (# 838) */ ++ RA00_TXTAG16, /* (# 839) */ ++ RA00_TXTAG17, /* (# 840) */ ++ RA00_TXTAG18, /* (# 841) */ ++ RA00_TXTAG19, /* (# 842) */ ++ RA00_TXTAG20, /* (# 843) */ ++ RA00_TXTAG21, /* (# 844) */ ++ RA00_TXTAG22, /* (# 845) */ ++ RA00_TXTAG23, /* (# 846) */ ++ RA00_VALID, /* (# 847) */ ++ RA00_VALID1, /* (# 848) */ ++ RA00_VALID2, /* (# 849) */ ++ RA00_VALID3, /* (# 850) */ ++ RA00_VALID4, /* (# 851) */ ++ RA00_VALID5, /* (# 852) */ ++ RA00_VALID6, /* (# 853) */ ++ RA00_VALID7, /* (# 854) */ ++ RA00_VALID8, /* (# 855) */ ++ RA00_VALID9, /* (# 856) */ ++ RA00_VALID10, /* (# 857) */ ++ RA00_VALID11, /* (# 858) */ ++ RA00_VALID12, /* (# 859) */ ++ RA00_VALID13, /* (# 860) */ ++ RA00_VALID14, /* (# 861) */ ++ RA00_VALID15, /* (# 862) */ ++ RA00_VALID16, /* (# 863) */ ++ RA00_VALID17, /* (# 864) */ ++ RA00_VALID18, /* (# 865) */ ++ RA00_VALID19, /* (# 866) */ ++ RA00_VALID20, /* (# 867) */ ++ RA00_VALID21, /* (# 868) */ ++ RA00_VALID22, /* (# 869) */ ++ RA00_VALID23, /* (# 870) */ ++ RA01_ACT, /* (# 871) */ ++ RA01_ACT1, /* (# 872) */ ++ RA01_ACT2, /* (# 873) */ ++ RA01_ACT3, /* (# 874) */ ++ RA01_ACT4, /* (# 875) */ ++ RA01_ACT5, /* (# 876) */ ++ RA01_ACT6, /* (# 877) */ ++ RA01_ACT7, /* (# 878) */ ++ RA01_ACT8, /* (# 879) */ ++ RA01_ACT9, /* (# 880) */ ++ RA01_ACT10, /* (# 881) */ ++ RA01_ACT11, /* (# 882) */ ++ RA01_ACT12, /* (# 883) */ ++ RA01_ACT13, /* (# 884) */ ++ RA01_ACT14, /* (# 885) */ ++ RA01_ACT15, /* (# 886) */ ++ RA01_ACT16, /* (# 887) */ ++ RA01_ACT17, /* (# 888) */ ++ RA01_ACT18, /* (# 889) */ ++ RA01_ACT19, /* (# 890) */ ++ RA01_ACT20, /* (# 891) */ ++ RA01_ACT21, /* (# 892) */ ++ RA01_ACT22, /* (# 893) */ ++ RA01_ACT23, /* (# 894) */ ++ RA01_CV, /* (# 895) */ ++ RA01_CV1, /* (# 896) */ ++ RA01_CV2, /* (# 897) */ ++ RA01_CV3, /* (# 898) */ ++ RA01_CV4, /* (# 899) */ ++ RA01_CV5, /* (# 900) */ ++ RA01_CV6, /* (# 901) */ ++ RA01_CV7, /* (# 902) */ ++ RA01_CV8, /* (# 903) */ ++ RA01_CV9, /* (# 904) */ ++ RA01_CV10, /* (# 905) */ ++ RA01_CV11, /* (# 906) */ ++ RA01_CV12, /* (# 907) */ ++ RA01_CV13, /* (# 908) */ ++ RA01_CV14, /* (# 909) */ ++ RA01_CV15, /* (# 910) */ ++ RA01_CV16, /* (# 911) */ ++ RA01_CV17, /* (# 912) */ ++ RA01_CV18, /* (# 913) */ ++ RA01_CV19, /* (# 914) */ ++ RA01_CV20, /* (# 915) */ ++ RA01_CV21, /* (# 916) */ ++ RA01_CV22, /* (# 917) */ ++ RA01_CV23, /* (# 918) */ ++ RA01_MG, /* (# 919) */ ++ RA01_MG1, /* (# 920) */ ++ RA01_MG2, /* (# 921) */ ++ RA01_MG3, /* (# 922) */ ++ RA01_MG4, /* (# 923) */ ++ RA01_MG5, /* (# 924) */ ++ RA01_MG6, /* (# 925) */ ++ RA01_MG7, /* (# 926) */ ++ RA01_MG8, /* (# 927) */ ++ RA01_MG9, /* (# 928) */ ++ RA01_MG10, /* (# 929) */ ++ RA01_MG11, /* (# 930) */ ++ RA01_MG12, /* (# 931) */ ++ RA01_MG13, /* (# 932) */ ++ RA01_MG14, /* (# 933) */ ++ RA01_MG15, /* (# 934) */ ++ RA01_MG16, /* (# 935) */ ++ RA01_MG17, /* (# 936) */ ++ RA01_MG18, /* (# 937) */ ++ RA01_MG19, /* (# 938) */ ++ RA01_MG20, /* (# 939) */ ++ RA01_MG21, /* (# 940) */ ++ RA01_MG22, /* (# 941) */ ++ RA01_MG23, /* (# 942) */ ++ RA01_SPAN, /* (# 943) */ ++ RA01_SPAN1, /* (# 944) */ ++ RA01_SPAN2, /* (# 945) */ ++ RA01_SPAN3, /* (# 946) */ ++ RA01_SPAN4, /* (# 947) */ ++ RA01_SPAN5, /* (# 948) */ ++ RA01_SPAN6, /* (# 949) */ ++ RA01_SPAN7, /* (# 950) */ ++ RA01_SPAN8, /* (# 951) */ ++ RA01_SPAN9, /* (# 952) */ ++ RA01_SPAN10, /* (# 953) */ ++ RA01_SPAN11, /* (# 954) */ ++ RA01_SPAN12, /* (# 955) */ ++ RA01_SPAN13, /* (# 956) */ ++ RA01_SPAN14, /* (# 957) */ ++ RA01_SPAN15, /* (# 958) */ ++ RA01_SPAN16, /* (# 959) */ ++ RA01_SPAN17, /* (# 960) */ ++ RA01_SPAN18, /* (# 961) */ ++ RA01_SPAN19, /* (# 962) */ ++ RA01_SPAN20, /* (# 963) */ ++ RA01_SPAN21, /* (# 964) */ ++ RA01_SPAN22, /* (# 965) */ ++ RA01_SPAN23, /* (# 966) */ ++ RA01_TXTAG, /* (# 967) */ ++ RA01_TXTAG1, /* (# 968) */ ++ RA01_TXTAG2, /* (# 969) */ ++ RA01_TXTAG3, /* (# 970) */ ++ RA01_TXTAG4, /* (# 971) */ ++ RA01_TXTAG5, /* (# 972) */ ++ RA01_TXTAG6, /* (# 973) */ ++ RA01_TXTAG7, /* (# 974) */ ++ RA01_TXTAG8, /* (# 975) */ ++ RA01_TXTAG9, /* (# 976) */ ++ RA01_TXTAG10, /* (# 977) */ ++ RA01_TXTAG11, /* (# 978) */ ++ RA01_TXTAG12, /* (# 979) */ ++ RA01_TXTAG13, /* (# 980) */ ++ RA01_TXTAG14, /* (# 981) */ ++ RA01_TXTAG15, /* (# 982) */ ++ RA01_TXTAG16, /* (# 983) */ ++ RA01_TXTAG17, /* (# 984) */ ++ RA01_TXTAG18, /* (# 985) */ ++ RA01_TXTAG19, /* (# 986) */ ++ RA01_TXTAG20, /* (# 987) */ ++ RA01_TXTAG21, /* (# 988) */ ++ RA01_TXTAG22, /* (# 989) */ ++ RA01_TXTAG23, /* (# 990) */ ++ RA01_VALID, /* (# 991) */ ++ RA01_VALID1, /* (# 992) */ ++ RA01_VALID2, /* (# 993) */ ++ RA01_VALID3, /* (# 994) */ ++ RA01_VALID4, /* (# 995) */ ++ RA01_VALID5, /* (# 996) */ ++ RA01_VALID6, /* (# 997) */ ++ RA01_VALID7, /* (# 998) */ ++ RA01_VALID8, /* (# 999) */ ++ RA01_VALID9, /* (# 1000) */ ++ RA01_VALID10, /* (# 1001) */ ++ RA01_VALID11, /* (# 1002) */ ++ RA01_VALID12, /* (# 1003) */ ++ RA01_VALID13, /* (# 1004) */ ++ RA01_VALID14, /* (# 1005) */ ++ RA01_VALID15, /* (# 1006) */ ++ RA01_VALID16, /* (# 1007) */ ++ RA01_VALID17, /* (# 1008) */ ++ RA01_VALID18, /* (# 1009) */ ++ RA01_VALID19, /* (# 1010) */ ++ RA01_VALID20, /* (# 1011) */ ++ RA01_VALID21, /* (# 1012) */ ++ RA01_VALID22, /* (# 1013) */ ++ RA01_VALID23, /* (# 1014) */ ++ RA02_ACT, /* (# 1015) */ ++ RA02_ACT1, /* (# 1016) */ ++ RA02_ACT2, /* (# 1017) */ ++ RA02_ACT3, /* (# 1018) */ ++ RA02_ACT4, /* (# 1019) */ ++ RA02_ACT5, /* (# 1020) */ ++ RA02_ACT6, /* (# 1021) */ ++ RA02_ACT7, /* (# 1022) */ ++ RA02_ACT8, /* (# 1023) */ ++ RA02_ACT9, /* (# 1024) */ ++ RA02_ACT10, /* (# 1025) */ ++ RA02_ACT11, /* (# 1026) */ ++ RA02_CV, /* (# 1027) */ ++ RA02_CV1, /* (# 1028) */ ++ RA02_CV2, /* (# 1029) */ ++ RA02_CV3, /* (# 1030) */ ++ RA02_CV4, /* (# 1031) */ ++ RA02_CV5, /* (# 1032) */ ++ RA02_CV6, /* (# 1033) */ ++ RA02_CV7, /* (# 1034) */ ++ RA02_CV8, /* (# 1035) */ ++ RA02_CV9, /* (# 1036) */ ++ RA02_CV10, /* (# 1037) */ ++ RA02_CV11, /* (# 1038) */ ++ RA02_MG, /* (# 1039) */ ++ RA02_MG1, /* (# 1040) */ ++ RA02_MG2, /* (# 1041) */ ++ RA02_MG3, /* (# 1042) */ ++ RA02_MG4, /* (# 1043) */ ++ RA02_MG5, /* (# 1044) */ ++ RA02_MG6, /* (# 1045) */ ++ RA02_MG7, /* (# 1046) */ ++ RA02_MG8, /* (# 1047) */ ++ RA02_MG9, /* (# 1048) */ ++ RA02_MG10, /* (# 1049) */ ++ RA02_MG11, /* (# 1050) */ ++ RA02_SPAN, /* (# 1051) */ ++ RA02_SPAN1, /* (# 1052) */ ++ RA02_SPAN2, /* (# 1053) */ ++ RA02_SPAN3, /* (# 1054) */ ++ RA02_SPAN4, /* (# 1055) */ ++ RA02_SPAN5, /* (# 1056) */ ++ RA02_SPAN6, /* (# 1057) */ ++ RA02_SPAN7, /* (# 1058) */ ++ RA02_SPAN8, /* (# 1059) */ ++ RA02_SPAN9, /* (# 1060) */ ++ RA02_SPAN10, /* (# 1061) */ ++ RA02_SPAN11, /* (# 1062) */ ++ RA02_TXTAG, /* (# 1063) */ ++ RA02_TXTAG1, /* (# 1064) */ ++ RA02_TXTAG2, /* (# 1065) */ ++ RA02_TXTAG3, /* (# 1066) */ ++ RA02_TXTAG4, /* (# 1067) */ ++ RA02_TXTAG5, /* (# 1068) */ ++ RA02_TXTAG6, /* (# 1069) */ ++ RA02_TXTAG7, /* (# 1070) */ ++ RA02_TXTAG8, /* (# 1071) */ ++ RA02_TXTAG9, /* (# 1072) */ ++ RA02_TXTAG10, /* (# 1073) */ ++ RA02_TXTAG11, /* (# 1074) */ ++ RA02_VALID, /* (# 1075) */ ++ RA02_VALID1, /* (# 1076) */ ++ RA02_VALID2, /* (# 1077) */ ++ RA02_VALID3, /* (# 1078) */ ++ RA02_VALID4, /* (# 1079) */ ++ RA02_VALID5, /* (# 1080) */ ++ RA02_VALID6, /* (# 1081) */ ++ RA02_VALID7, /* (# 1082) */ ++ RA02_VALID8, /* (# 1083) */ ++ RA02_VALID9, /* (# 1084) */ ++ RA02_VALID10, /* (# 1085) */ ++ RA02_VALID11, /* (# 1086) */ ++ RA03_ACT, /* (# 1087) */ ++ RA03_ACT1, /* (# 1088) */ ++ RA03_ACT2, /* (# 1089) */ ++ RA03_ACT3, /* (# 1090) */ ++ RA03_ACT4, /* (# 1091) */ ++ RA03_ACT5, /* (# 1092) */ ++ RA03_ACT6, /* (# 1093) */ ++ RA03_ACT7, /* (# 1094) */ ++ RA03_ACT8, /* (# 1095) */ ++ RA03_ACT9, /* (# 1096) */ ++ RA03_ACT10, /* (# 1097) */ ++ RA03_ACT11, /* (# 1098) */ ++ RA03_CV, /* (# 1099) */ ++ RA03_CV1, /* (# 1100) */ ++ RA03_CV2, /* (# 1101) */ ++ RA03_CV3, /* (# 1102) */ ++ RA03_CV4, /* (# 1103) */ ++ RA03_CV5, /* (# 1104) */ ++ RA03_CV6, /* (# 1105) */ ++ RA03_CV7, /* (# 1106) */ ++ RA03_CV8, /* (# 1107) */ ++ RA03_CV9, /* (# 1108) */ ++ RA03_CV10, /* (# 1109) */ ++ RA03_CV11, /* (# 1110) */ ++ RA03_MG, /* (# 1111) */ ++ RA03_MG1, /* (# 1112) */ ++ RA03_MG2, /* (# 1113) */ ++ RA03_MG3, /* (# 1114) */ ++ RA03_MG4, /* (# 1115) */ ++ RA03_MG5, /* (# 1116) */ ++ RA03_MG6, /* (# 1117) */ ++ RA03_MG7, /* (# 1118) */ ++ RA03_MG8, /* (# 1119) */ ++ RA03_MG9, /* (# 1120) */ ++ RA03_MG10, /* (# 1121) */ ++ RA03_MG11, /* (# 1122) */ ++ RA03_SPAN, /* (# 1123) */ ++ RA03_SPAN1, /* (# 1124) */ ++ RA03_SPAN2, /* (# 1125) */ ++ RA03_SPAN3, /* (# 1126) */ ++ RA03_SPAN4, /* (# 1127) */ ++ RA03_SPAN5, /* (# 1128) */ ++ RA03_SPAN6, /* (# 1129) */ ++ RA03_SPAN7, /* (# 1130) */ ++ RA03_SPAN8, /* (# 1131) */ ++ RA03_SPAN9, /* (# 1132) */ ++ RA03_SPAN10, /* (# 1133) */ ++ RA03_SPAN11, /* (# 1134) */ ++ RA03_TXTAG, /* (# 1135) */ ++ RA03_TXTAG1, /* (# 1136) */ ++ RA03_TXTAG2, /* (# 1137) */ ++ RA03_TXTAG3, /* (# 1138) */ ++ RA03_TXTAG4, /* (# 1139) */ ++ RA03_TXTAG5, /* (# 1140) */ ++ RA03_TXTAG6, /* (# 1141) */ ++ RA03_TXTAG7, /* (# 1142) */ ++ RA03_TXTAG8, /* (# 1143) */ ++ RA03_TXTAG9, /* (# 1144) */ ++ RA03_TXTAG10, /* (# 1145) */ ++ RA03_TXTAG11, /* (# 1146) */ ++ RA03_VALID, /* (# 1147) */ ++ RA03_VALID1, /* (# 1148) */ ++ RA03_VALID2, /* (# 1149) */ ++ RA03_VALID3, /* (# 1150) */ ++ RA03_VALID4, /* (# 1151) */ ++ RA03_VALID5, /* (# 1152) */ ++ RA03_VALID6, /* (# 1153) */ ++ RA03_VALID7, /* (# 1154) */ ++ RA03_VALID8, /* (# 1155) */ ++ RA03_VALID9, /* (# 1156) */ ++ RA03_VALID10, /* (# 1157) */ ++ RA03_VALID11, /* (# 1158) */ ++ RMON_BAS, /* (# 1159) */ ++ RMON_CAC, /* (# 1160) */ ++ RMON_COUNTER, /* (# 1161) */ ++ RMON_HIGH_COUNTER, /* (# 1162) */ ++ RMON_LOW_COUNTER, /* (# 1163) */ ++ RMON_OFFSET, /* (# 1164) */ ++ RMON_PORTC, /* (# 1165) */ ++ TYPE_FILTER_ATF, /* (# 1166) */ ++ TYPE_FILTER_ATF1, /* (# 1167) */ ++ TYPE_FILTER_ATF2, /* (# 1168) */ ++ TYPE_FILTER_ATF3, /* (# 1169) */ ++ TYPE_FILTER_ATF4, /* (# 1170) */ ++ TYPE_FILTER_ATF5, /* (# 1171) */ ++ TYPE_FILTER_ATF6, /* (# 1172) */ ++ TYPE_FILTER_ATF7, /* (# 1173) */ ++ TYPE_FILTER_QTF, /* (# 1174) */ ++ TYPE_FILTER_QTF1, /* (# 1175) */ ++ TYPE_FILTER_QTF2, /* (# 1176) */ ++ TYPE_FILTER_QTF3, /* (# 1177) */ ++ TYPE_FILTER_QTF4, /* (# 1178) */ ++ TYPE_FILTER_QTF5, /* (# 1179) */ ++ TYPE_FILTER_QTF6, /* (# 1180) */ ++ TYPE_FILTER_QTF7, /* (# 1181) */ ++ TYPE_FILTER_VCET0, /* (# 1182) */ ++ TYPE_FILTER_VCET01, /* (# 1183) */ ++ TYPE_FILTER_VCET02, /* (# 1184) */ ++ TYPE_FILTER_VCET03, /* (# 1185) */ ++ TYPE_FILTER_VCET1, /* (# 1186) */ ++ TYPE_FILTER_VCET11, /* (# 1187) */ ++ TYPE_FILTER_VCET12, /* (# 1188) */ ++ TYPE_FILTER_VCET13, /* (# 1189) */ ++ TYPE_FILTER_VCET_ALL, /* (# 1190) */ ++ TYPE_FILTER_VCET_ALL1, /* (# 1191) */ ++ TYPE_FILTER_VCET_ALL2, /* (# 1192) */ ++ TYPE_FILTER_VCET_ALL3, /* (# 1193) */ ++ TYPE_FILTER_VCET_ALL4, /* (# 1194) */ ++ TYPE_FILTER_VCET_ALL5, /* (# 1195) */ ++ TYPE_FILTER_VCET_ALL6, /* (# 1196) */ ++ TYPE_FILTER_VCET_ALL7, /* (# 1197) */ ++ VLAN_FILTER_M, /* (# 1198) */ ++ VLAN_FILTER_M1, /* (# 1199) */ ++ VLAN_FILTER_M2, /* (# 1200) */ ++ VLAN_FILTER_M3, /* (# 1201) */ ++ VLAN_FILTER_M4, /* (# 1202) */ ++ VLAN_FILTER_M5, /* (# 1203) */ ++ VLAN_FILTER_M6, /* (# 1204) */ ++ VLAN_FILTER_M7, /* (# 1205) */ ++ VLAN_FILTER_M8, /* (# 1206) */ ++ VLAN_FILTER_M9, /* (# 1207) */ ++ VLAN_FILTER_M10, /* (# 1208) */ ++ VLAN_FILTER_M11, /* (# 1209) */ ++ VLAN_FILTER_M12, /* (# 1210) */ ++ VLAN_FILTER_M13, /* (# 1211) */ ++ VLAN_FILTER_M14, /* (# 1212) */ ++ VLAN_FILTER_M15, /* (# 1213) */ ++ VLAN_FILTER_TM, /* (# 1214) */ ++ VLAN_FILTER_TM1, /* (# 1215) */ ++ VLAN_FILTER_TM2, /* (# 1216) */ ++ VLAN_FILTER_TM3, /* (# 1217) */ ++ VLAN_FILTER_TM4, /* (# 1218) */ ++ VLAN_FILTER_TM5, /* (# 1219) */ ++ VLAN_FILTER_TM6, /* (# 1220) */ ++ VLAN_FILTER_TM7, /* (# 1221) */ ++ VLAN_FILTER_TM8, /* (# 1222) */ ++ VLAN_FILTER_TM9, /* (# 1223) */ ++ VLAN_FILTER_TM10, /* (# 1224) */ ++ VLAN_FILTER_TM11, /* (# 1225) */ ++ VLAN_FILTER_TM12, /* (# 1226) */ ++ VLAN_FILTER_TM13, /* (# 1227) */ ++ VLAN_FILTER_TM14, /* (# 1228) */ ++ VLAN_FILTER_TM15, /* (# 1229) */ ++ VLAN_FILTER_VFID, /* (# 1230) */ ++ VLAN_FILTER_VFID1, /* (# 1231) */ ++ VLAN_FILTER_VFID2, /* (# 1232) */ ++ VLAN_FILTER_VFID3, /* (# 1233) */ ++ VLAN_FILTER_VFID4, /* (# 1234) */ ++ VLAN_FILTER_VFID5, /* (# 1235) */ ++ VLAN_FILTER_VFID6, /* (# 1236) */ ++ VLAN_FILTER_VFID7, /* (# 1237) */ ++ VLAN_FILTER_VFID8, /* (# 1238) */ ++ VLAN_FILTER_VFID9, /* (# 1239) */ ++ VLAN_FILTER_VFID10, /* (# 1240) */ ++ VLAN_FILTER_VFID11, /* (# 1241) */ ++ VLAN_FILTER_VFID12, /* (# 1242) */ ++ VLAN_FILTER_VFID13, /* (# 1243) */ ++ VLAN_FILTER_VFID14, /* (# 1244) */ ++ VLAN_FILTER_VFID15, /* (# 1245) */ ++ VLAN_FILTER_VID, /* (# 1246) */ ++ VLAN_FILTER_VID1, /* (# 1247) */ ++ VLAN_FILTER_VID2, /* (# 1248) */ ++ VLAN_FILTER_VID3, /* (# 1249) */ ++ VLAN_FILTER_VID4, /* (# 1250) */ ++ VLAN_FILTER_VID5, /* (# 1251) */ ++ VLAN_FILTER_VID6, /* (# 1252) */ ++ VLAN_FILTER_VID7, /* (# 1253) */ ++ VLAN_FILTER_VID8, /* (# 1254) */ ++ VLAN_FILTER_VID9, /* (# 1255) */ ++ VLAN_FILTER_VID10, /* (# 1256) */ ++ VLAN_FILTER_VID11, /* (# 1257) */ ++ VLAN_FILTER_VID12, /* (# 1258) */ ++ VLAN_FILTER_VID13, /* (# 1259) */ ++ VLAN_FILTER_VID14, /* (# 1260) */ ++ VLAN_FILTER_VID15, /* (# 1261) */ ++ VLAN_FILTER_VP, /* (# 1262) */ ++ VLAN_FILTER_VP1, /* (# 1263) */ ++ VLAN_FILTER_VP2, /* (# 1264) */ ++ VLAN_FILTER_VP3, /* (# 1265) */ ++ VLAN_FILTER_VP4, /* (# 1266) */ ++ VLAN_FILTER_VP5, /* (# 1267) */ ++ VLAN_FILTER_VP6, /* (# 1268) */ ++ VLAN_FILTER_VP7, /* (# 1269) */ ++ VLAN_FILTER_VP8, /* (# 1270) */ ++ VLAN_FILTER_VP9, /* (# 1271) */ ++ VLAN_FILTER_VP10, /* (# 1272) */ ++ VLAN_FILTER_VP11, /* (# 1273) */ ++ VLAN_FILTER_VP12, /* (# 1274) */ ++ VLAN_FILTER_VP13, /* (# 1275) */ ++ VLAN_FILTER_VP14, /* (# 1276) */ ++ VLAN_FILTER_VP15, /* (# 1277) */ ++ VLAN_FILTER_VV, /* (# 1278) */ ++ VLAN_FILTER_VV1, /* (# 1279) */ ++ VLAN_FILTER_VV2, /* (# 1280) */ ++ VLAN_FILTER_VV3, /* (# 1281) */ ++ VLAN_FILTER_VV4, /* (# 1282) */ ++ VLAN_FILTER_VV5, /* (# 1283) */ ++ VLAN_FILTER_VV6, /* (# 1284) */ ++ VLAN_FILTER_VV7, /* (# 1285) */ ++ VLAN_FILTER_VV8, /* (# 1286) */ ++ VLAN_FILTER_VV9, /* (# 1287) */ ++ VLAN_FILTER_VV10, /* (# 1288) */ ++ VLAN_FILTER_VV11, /* (# 1289) */ ++ VLAN_FILTER_VV12, /* (# 1290) */ ++ VLAN_FILTER_VV13, /* (# 1291) */ ++ VLAN_FILTER_VV14, /* (# 1292) */ ++ VLAN_FILTER_VV15, /* (# 1293) */ ++ COMMON_BIT_LATEST /* (# 1294) */ ++}IFX_ETHSW_regMapperSelector_t; ++ ++#endif /* #ifndef _IFX_ETHSW_REGMAPPERSELECTOR_H */ +diff --git a/include/switch_api/gphy_fw.h b/include/switch_api/gphy_fw.h +new file mode 100644 +index 0000000..9a9ee30 +--- /dev/null ++++ b/include/switch_api/gphy_fw.h +@@ -0,0 +1,20 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ \file gphy_fw.h ++ \remarks implement GPHY driver firmware on VR9 platform ++ *****************************************************************************/ ++ ++#ifndef _GPHY_FW_H_ ++#define _GPHY_FW_H_ ++ ++#define GPHY_FW_LEN (64 * 1024) ++#define GPHY_FW_LEN_D (128 * 1024) ++ ++#endif /* _GPHY_FW_H_ */ +diff --git a/include/switch_api/gphy_fw_fe.h b/include/switch_api/gphy_fw_fe.h +new file mode 100644 +index 0000000..323858c +--- /dev/null ++++ b/include/switch_api/gphy_fw_fe.h +@@ -0,0 +1,8217 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ \file gphy_fw_fe.h ++ \remarks implement GPHY driver firmware in VR9 platform ++ \Track bin : gphy_fw_fe.bin [ 0915-2010 ] ++ *****************************************************************************/ ++#ifndef __GPHY_IP_22F_FW__ ++#define __GPHY_IP_22F_FW__ ++ ++static const unsigned char gphy_fe_fw_data[] = { ++ 0x80, 0x4E, 0x00, 0x02, 0x32, 0x32, 0x32, 0x00, 0x80, 0x32, 0x32, 0x32, 0x7F, 0x54, 0xEF, 0xF9, ++ 0x80, 0x22, 0x99, 0xF5, 0x00, 0x00, 0x22, 0xF2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEB, ++ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDC, ++ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEF, 0xE1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF2, ++ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17, 0x09, 0x02, 0x00, 0x00, 0x00, 0x81, 0x75, 0x2A, 0x0B, ++ 0x2D, 0x03, 0x02, 0xB1, 0x75, 0x07, 0x10, 0x75, 0x0E, 0x7E, 0x12, 0x11, 0x73, 0x71, 0x6C, 0x7F, ++ 0x56, 0x7F, 0x22, 0x7E, 0xF7, 0x21, 0x73, 0x71, 0xEF, 0xD1, 0x01, 0x90, 0x01, 0x90, 0xE4, 0xF0, ++ 0x80, 0x22, 0xF0, 0xCE, 0x54, 0x90, 0xE5, 0x95, 0xC0, 0x03, 0xC4, 0x0F, 0xC0, 0x04, 0x74, 0xE0, ++ 0xC0, 0x82, 0xC0, 0xE0, 0x00, 0x04, 0x02, 0x83, 0x0F, 0x54, 0x90, 0xE5, 0xE0, 0xC0, 0x03, 0xC4, ++ 0xE0, 0xC0, 0x04, 0x74, 0x83, 0xC0, 0x82, 0xC0, 0xE5, 0x08, 0x04, 0x02, 0xC4, 0x0F, 0x54, 0x90, ++ 0x74, 0xE0, 0xC0, 0x03, 0xC0, 0xE0, 0xC0, 0x04, 0x02, 0x83, 0xC0, 0x82, 0x90, 0xE5, 0x10, 0x04, ++ 0x03, 0xC4, 0x0F, 0x54, 0x04, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, 0xC0, 0x04, 0x02, 0x83, 0xC0, ++ 0x54, 0x90, 0xE5, 0x18, 0xC0, 0x03, 0xC4, 0x0F, 0xC0, 0x04, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, ++ 0x20, 0x04, 0x02, 0x83, 0x0F, 0x54, 0x90, 0xE5, 0xE0, 0xC0, 0x03, 0xC4, 0xE0, 0xC0, 0x04, 0x74, ++ 0x83, 0xC0, 0x82, 0xC0, 0xE5, 0x28, 0x04, 0x02, 0xC4, 0x0F, 0x54, 0x90, 0x74, 0xE0, 0xC0, 0x03, ++ 0xC0, 0xE0, 0xC0, 0x04, 0x02, 0x83, 0xC0, 0x82, 0x90, 0xE5, 0x30, 0x04, 0x03, 0xC4, 0x0F, 0x54, ++ 0x04, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, 0xC0, 0x04, 0x02, 0x83, 0xC0, 0x54, 0x90, 0xE5, 0x38, ++ 0xC0, 0x03, 0xC4, 0x0F, 0xC0, 0x04, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, 0x40, 0x04, 0x02, 0x83, ++ 0x0F, 0x54, 0x90, 0xE5, 0xE0, 0xC0, 0x03, 0xC4, 0xE0, 0xC0, 0x04, 0x74, 0x83, 0xC0, 0x82, 0xC0, ++ 0xE5, 0x48, 0x04, 0x02, 0xC4, 0x0F, 0x54, 0x90, 0x74, 0xE0, 0xC0, 0x03, 0xC0, 0xE0, 0xC0, 0x04, ++ 0x02, 0x83, 0xC0, 0x82, 0x90, 0xE5, 0x50, 0x04, 0x03, 0xC4, 0x0F, 0x54, 0x04, 0x74, 0xE0, 0xC0, ++ 0x82, 0xC0, 0xE0, 0xC0, 0x04, 0x02, 0x83, 0xC0, 0x54, 0x90, 0xE5, 0x58, 0xC0, 0x03, 0xC4, 0x0F, ++ 0xC0, 0x04, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, 0x60, 0x04, 0x02, 0x83, 0x0F, 0x54, 0x90, 0xE5, ++ 0xE0, 0xC0, 0x03, 0xC4, 0xE0, 0xC0, 0x04, 0x74, 0x83, 0xC0, 0x82, 0xC0, 0xE5, 0x68, 0x04, 0x02, ++ 0xC4, 0x0F, 0x54, 0x90, 0x74, 0xE0, 0xC0, 0x03, 0xC0, 0xE0, 0xC0, 0x04, 0x02, 0x83, 0xC0, 0x82, ++ 0x90, 0xE5, 0x70, 0x04, 0x03, 0xC4, 0x0F, 0x54, 0x04, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, 0xC0, ++ 0x04, 0x02, 0x83, 0xC0, 0x03, 0xC4, 0xEF, 0x78, 0x73, 0x00, 0x04, 0x90, 0x01, 0x56, 0x22, 0x90, ++ 0xF5, 0x22, 0x90, 0x88, 0x26, 0x90, 0x9B, 0x01, 0x90, 0xAE, 0x01, 0x51, 0xC1, 0x01, 0x19, 0x26, ++ 0x01, 0xC1, 0x26, 0x90, 0xC1, 0x26, 0x90, 0xD4, 0x28, 0x90, 0xE7, 0x01, 0x90, 0xFA, 0x01, 0x07, ++ 0x0D, 0x21, 0x09, 0x28, 0x21, 0x2D, 0x28, 0x90, 0x68, 0x24, 0x90, 0x20, 0x28, 0x90, 0x33, 0x21, ++ 0x90, 0x46, 0x21, 0x21, 0x59, 0x21, 0x68, 0x24, 0x21, 0xE7, 0x27, 0x90, 0xE7, 0x27, 0x90, 0x6C, ++ 0x2E, 0x90, 0x7F, 0x21, 0x90, 0x92, 0x21, 0x81, 0x88, 0x01, 0x28, 0x20, 0x01, 0x53, 0x21, 0x90, ++ 0xEC, 0x22, 0x90, 0x88, 0x20, 0x90, 0x9B, 0x01, 0x90, 0x9B, 0x01, 0x88, 0xAE, 0x01, 0xAC, 0x20, ++ 0x01, 0x60, 0x22, 0x90, 0xEE, 0x23, 0x90, 0xAE, 0x24, 0x90, 0xAE, 0x01, 0x90, 0xAE, 0x01, 0xEB, ++ 0xAE, 0x01, 0xA6, 0x25, 0x01, 0x82, 0x20, 0x90, 0x28, 0x22, 0x90, 0xC1, 0x23, 0x90, 0xC1, 0x01, ++ 0x90, 0xC1, 0x01, 0xB6, 0xC1, 0x01, 0xB3, 0x24, 0x01, 0x6E, 0x25, 0x90, 0xC9, 0x21, 0x90, 0xC1, ++ 0x20, 0x90, 0xD4, 0x01, 0x90, 0xD4, 0x01, 0x58, 0xD4, 0x01, 0xD6, 0x21, 0x01, 0xEB, 0x22, 0x90, ++ 0xF8, 0x24, 0x90, 0xD4, 0x21, 0x90, 0xD4, 0x01, 0x90, 0xE7, 0x01, 0xC9, 0xE7, 0x01, 0x58, 0x20, ++ 0x01, 0xD6, 0x21, 0x90, 0xEB, 0x22, 0x90, 0xE7, 0x24, 0x90, 0xE7, 0x01, 0x90, 0xE7, 0x01, 0xF8, ++ 0xFA, 0x01, 0x43, 0x20, 0x01, 0xDA, 0x26, 0x90, 0x43, 0x20, 0x90, 0xFA, 0x26, 0x90, 0x0D, 0x21, ++ 0x90, 0x0D, 0x21, 0xDA, 0x20, 0x21, 0xF4, 0x25, 0x21, 0x79, 0x20, 0x90, 0xEE, 0x25, 0x90, 0x33, ++ 0x20, 0x90, 0x46, 0x21, 0x90, 0x59, 0x21, 0x79, 0x6C, 0x21, 0x22, 0x27, 0x21, 0x22, 0x27, 0x90, ++ 0xB1, 0x28, 0x90, 0x7F, 0xBB, 0x00, 0x92, 0x21, 0x82, 0x89, 0x06, 0x01, 0x22, 0xE0, 0x83, 0x8A, ++ 0x22, 0xE7, 0x02, 0x50, 0xE3, 0x02, 0xFE, 0xBB, 0x8A, 0x82, 0x89, 0x22, 0x22, 0x93, 0xE4, 0x83, ++ 0xA4, 0xF0, 0x8D, 0xEF, 0x8C, 0xCF, 0xF0, 0xA8, 0xCE, 0x28, 0xA4, 0xF0, 0x2E, 0xA4, 0xF0, 0x8D, ++ 0x00, 0xBC, 0x22, 0xFE, 0x29, 0x00, 0xBE, 0x0B, 0x84, 0xF0, 0x8D, 0xEF, 0x22, 0xF0, 0xAD, 0xFF, ++ 0x75, 0xF8, 0xCC, 0xE4, 0x2F, 0xEF, 0x08, 0xF0, 0xFE, 0x33, 0xEE, 0xFF, 0xEE, 0xFC, 0x33, 0xEC, ++ 0x40, 0x98, 0xEC, 0x9D, 0x9D, 0xEE, 0xFC, 0x05, 0xF0, 0xD5, 0x0F, 0xFE, 0xFD, 0xCE, 0xE4, 0xE9, ++ 0xF5, 0xF8, 0xED, 0x22, 0x20, 0x84, 0xEE, 0xF0, 0xAD, 0xFE, 0x1C, 0xD2, 0x08, 0xF0, 0x75, 0xF0, ++ 0xED, 0xFF, 0x2F, 0xEF, 0x07, 0x40, 0xFD, 0x33, 0xD5, 0x06, 0x50, 0x98, 0xC3, 0x22, 0xF2, 0xF0, ++ 0xD5, 0x0F, 0xFD, 0x98, 0x8A, 0x22, 0xEA, 0xF0, 0xE4, 0x82, 0x89, 0x83, 0x03, 0x60, 0xE4, 0x73, ++ 0x75, 0x6C, 0x0E, 0x12, 0x54, 0x11, 0xFF, 0xB0, 0x3D, 0x51, 0xFC, 0x31, 0x07, 0x90, 0x56, 0x51, ++ 0xF0, 0x54, 0xE0, 0x34, 0x90, 0xF0, 0x04, 0x44, 0xFF, 0xE0, 0x44, 0x07, 0x07, 0x54, 0x13, 0xC4, ++ 0x00, 0x03, 0xE0, 0x20, 0x9D, 0x71, 0xF1, 0x80, 0xE0, 0x07, 0x07, 0x90, 0xE0, 0xF0, 0x10, 0x44, ++ 0x43, 0xF0, 0xEF, 0x54, 0xFB, 0x80, 0x01, 0x87, 0xEF, 0xD0, 0x01, 0x90, 0x01, 0x90, 0xE4, 0xF0, ++ 0xEF, 0x22, 0xF0, 0xCD, 0xEE, 0xFF, 0x10, 0x24, 0xEF, 0xFE, 0xE0, 0x34, 0xFF, 0x24, 0xF0, 0x54, ++ 0xFF, 0x34, 0xEE, 0xFF, 0xFD, 0x11, 0xE5, 0xFE, 0x11, 0xF5, 0x02, 0x24, 0x34, 0xFC, 0x10, 0xE5, ++ 0x8D, 0x10, 0xF5, 0x00, 0xEE, 0x83, 0x8C, 0x82, 0xF0, 0xEF, 0xA3, 0xF0, 0xA8, 0xF5, 0xE4, 0x22, ++ 0xAC, 0xD2, 0xE8, 0xF5, 0xE9, 0xD2, 0xEA, 0xD2, 0xF9, 0x75, 0xE8, 0xD2, 0xF0, 0xF8, 0x75, 0xF0, ++ 0xB8, 0x75, 0xB9, 0xF5, 0x22, 0xAF, 0xD2, 0x10, 0xCF, 0x01, 0x90, 0xE4, 0x06, 0x90, 0x22, 0xF0, ++ 0xA3, 0xFE, 0xE0, 0x34, 0x06, 0x90, 0xFF, 0xE0, 0xFE, 0x5E, 0xE0, 0x32, 0x4E, 0x5F, 0xE0, 0xA3, ++ 0x06, 0x90, 0x14, 0x70, 0xA3, 0xFE, 0xE0, 0x74, 0x06, 0x90, 0xFF, 0xE0, 0xFE, 0x5E, 0xE0, 0x72, ++ 0x4E, 0x5F, 0xE0, 0xA3, 0x07, 0x90, 0x07, 0x60, 0x10, 0x44, 0xE0, 0x07, 0xFF, 0x7B, 0x22, 0xF0, ++ 0x21, 0x79, 0x20, 0x7A, 0x02, 0xFC, 0xFD, 0xE4, 0x00, 0x00, 0x40, 0x0D, 0x00, 0x00, 0x00, 0x00, ++ 0x22, 0xF0, 0x90, 0x53, 0x00, 0x00, 0x00, 0x00, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF1, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF2, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF3, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF4, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF5, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF6, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF7, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF8, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF9, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xFA, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xFB, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xFC, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xFD, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xFE, 0x90, 0x22, 0x0F, 0x90, 0x43, 0xF0, 0xC0, 0xE0, 0xC0, ++ 0x82, 0xC0, 0x83, 0xC0, 0xD0, 0x75, 0xD0, 0xC0, 0x01, 0xA2, 0x63, 0x00, 0x82, 0xC0, 0x83, 0xC0, ++ 0xC0, 0x01, 0xA2, 0x63, 0xC0, 0x01, 0xC0, 0x00, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x05, 0xC0, 0x04, ++ 0x30, 0x07, 0xC0, 0x06, 0x99, 0xC2, 0x24, 0x99, 0x0F, 0x65, 0x0E, 0xE5, 0x0E, 0xAF, 0x1A, 0x60, ++ 0x00, 0x7E, 0x0E, 0x05, 0x24, 0x7F, 0x54, 0xEF, 0xEE, 0x82, 0xF5, 0x00, 0x83, 0xF5, 0x02, 0x34, ++ 0x0D, 0x11, 0xFF, 0xE0, 0x02, 0x80, 0x16, 0xC2, 0x07, 0xD0, 0x17, 0xC2, 0x05, 0xD0, 0x06, 0xD0, ++ 0x03, 0xD0, 0x04, 0xD0, 0x01, 0xD0, 0x02, 0xD0, 0xA2, 0x63, 0x00, 0xD0, 0xD0, 0x82, 0xD0, 0x01, ++ 0x01, 0xA2, 0x63, 0x83, 0x82, 0xD0, 0xD0, 0xD0, 0xF0, 0xD0, 0x83, 0xD0, 0xC0, 0x32, 0xE0, 0xD0, ++ 0xC0, 0xF0, 0xC0, 0xE0, 0xC0, 0x82, 0xC0, 0x83, 0x00, 0xD0, 0x75, 0xD0, 0xC0, 0x01, 0xA2, 0x63, ++ 0x63, 0x82, 0xC0, 0x83, 0x00, 0xC0, 0x01, 0xA2, 0x02, 0xC0, 0x01, 0xC0, 0x04, 0xC0, 0x03, 0xC0, ++ 0x06, 0xC0, 0x05, 0xC0, 0x07, 0x90, 0x07, 0xC0, 0x56, 0xF5, 0xE0, 0x02, 0x54, 0xEF, 0x56, 0xAF, ++ 0x13, 0x13, 0xC4, 0x40, 0x57, 0xF5, 0x03, 0x54, 0xA4, 0x40, 0xF0, 0x75, 0x82, 0xF5, 0x00, 0x24, ++ 0xAF, 0x06, 0x34, 0xE4, 0x8F, 0x0C, 0xF5, 0x82, 0x25, 0x20, 0x74, 0x0D, 0x57, 0xE5, 0xFF, 0x57, ++ 0x01, 0x90, 0x05, 0x70, 0x90, 0x03, 0x80, 0xD2, 0xFC, 0xE0, 0xD4, 0x01, 0x0A, 0x8C, 0xE0, 0xA3, ++ 0x56, 0xAE, 0x0B, 0xF5, 0x13, 0x13, 0xC4, 0xEE, 0x30, 0x01, 0x54, 0x13, 0x31, 0xE1, 0x02, 0xE0, ++ 0x54, 0xEE, 0x56, 0xAE, 0x70, 0xFC, 0x24, 0x1F, 0x24, 0x42, 0xC1, 0x02, 0xC1, 0x02, 0x70, 0xFD, ++ 0x70, 0xFE, 0x24, 0x6C, 0x24, 0x74, 0xC1, 0x02, 0xC1, 0x02, 0x70, 0xFC, 0x02, 0x70, 0x14, 0x9A, ++ 0xF7, 0x24, 0xB6, 0xC1, 0xF2, 0xC1, 0x02, 0x70, 0x02, 0x60, 0x17, 0x24, 0x0D, 0x85, 0xBA, 0xE1, ++ 0x83, 0x0C, 0x85, 0x82, 0x13, 0xC4, 0xFE, 0xE0, 0x01, 0x54, 0x13, 0x13, 0xC2, 0x0C, 0xE0, 0x30, ++ 0xE6, 0x07, 0xA8, 0xE8, 0xD2, 0xF6, 0x01, 0x44, 0xEE, 0xBA, 0xE1, 0xE8, 0x30, 0x0F, 0x54, 0xC4, ++ 0x0D, 0x85, 0x39, 0xE0, 0x83, 0x0C, 0x85, 0x82, 0x25, 0x02, 0x54, 0xE0, 0x07, 0xA8, 0xFE, 0xE0, ++ 0x4E, 0xFB, 0x54, 0xE6, 0x82, 0x0D, 0x85, 0xF6, 0xA3, 0x83, 0x0C, 0x85, 0xC4, 0xE0, 0xA3, 0xA3, ++ 0x7E, 0x07, 0x54, 0x13, 0x02, 0xE0, 0x20, 0x00, 0x54, 0xEE, 0x01, 0x7E, 0x54, 0x33, 0xC4, 0x01, ++ 0x07, 0xA8, 0xFE, 0xE0, 0x4E, 0xDF, 0x54, 0xE6, 0x85, 0x17, 0x80, 0xF6, 0x0C, 0x85, 0x82, 0x0D, ++ 0xFD, 0x54, 0xE0, 0x83, 0xA3, 0xA3, 0xA3, 0xF0, 0xF0, 0xDF, 0x54, 0xE0, 0x44, 0xE6, 0x07, 0xA8, ++ 0x0D, 0x85, 0xF6, 0x20, 0x83, 0x0C, 0x85, 0x82, 0x13, 0x13, 0xFE, 0xE0, 0xEE, 0xFD, 0x01, 0x54, ++ 0x54, 0x13, 0x13, 0xC4, 0xA3, 0xFE, 0x4D, 0x01, 0x13, 0x13, 0xC4, 0xE0, 0x4E, 0x01, 0x54, 0x13, ++ 0x54, 0xC4, 0x01, 0x54, 0x07, 0xA8, 0xFE, 0xF0, 0x4E, 0xEF, 0x54, 0xE6, 0x82, 0x0D, 0x85, 0xF6, ++ 0xE0, 0x83, 0x0C, 0x85, 0x13, 0x13, 0x08, 0x54, 0xE6, 0xFE, 0x3F, 0x54, 0xF6, 0x4E, 0xFD, 0x54, ++ 0x0D, 0x85, 0xBA, 0xE1, 0x83, 0x0C, 0x85, 0x82, 0xE0, 0xA3, 0xA3, 0xA3, 0x07, 0x54, 0x13, 0xC4, ++ 0xE1, 0x02, 0xE0, 0x30, 0x82, 0x0D, 0x85, 0xBA, 0xE0, 0x83, 0x0C, 0x85, 0x20, 0x0F, 0x54, 0xC4, ++ 0xBA, 0xE1, 0x02, 0xE0, 0x44, 0xE6, 0x07, 0xA8, 0xBA, 0xE1, 0xF6, 0x04, 0x44, 0xE6, 0x07, 0xA8, ++ 0xBA, 0xE1, 0xF6, 0x08, 0x12, 0x24, 0x0D, 0xE5, 0x35, 0xE4, 0x82, 0xF5, 0xE0, 0x83, 0xF5, 0x0C, ++ 0x07, 0x54, 0x13, 0xC4, 0x02, 0x60, 0x00, 0x7E, 0x54, 0xEE, 0x01, 0x7E, 0xF0, 0x54, 0xC4, 0x01, ++ 0xE6, 0x07, 0xA8, 0xFE, 0xF6, 0x4E, 0xEF, 0x54, 0x0C, 0x12, 0xBA, 0xE1, 0x02, 0x60, 0xEF, 0xE3, ++ 0x0D, 0xE5, 0x99, 0xE1, 0x82, 0xF5, 0x1C, 0x24, 0xF5, 0x0C, 0x35, 0xE4, 0xF0, 0x0A, 0xE5, 0x83, ++ 0xF0, 0x0B, 0xE5, 0xA3, 0x0C, 0x12, 0xBA, 0xE1, 0x15, 0x70, 0xEF, 0xE3, 0x1C, 0x24, 0x0D, 0xE5, ++ 0x35, 0xE4, 0x82, 0xF5, 0xE0, 0x83, 0xF5, 0x0C, 0x8E, 0xE0, 0xA3, 0xFE, 0xE1, 0x0B, 0xF5, 0x0A, ++ 0x24, 0x57, 0xE5, 0xBA, 0x12, 0x13, 0x92, 0xFF, 0x0C, 0x12, 0xD7, 0x0B, 0x02, 0x64, 0xEF, 0xE3, ++ 0x0C, 0x12, 0x06, 0x60, 0x08, 0x03, 0xBF, 0xE3, 0x0B, 0xE5, 0x0B, 0x05, 0x0A, 0x05, 0x02, 0x70, ++ 0x57, 0xE5, 0x99, 0xE1, 0x06, 0x90, 0x1B, 0x70, 0x03, 0x54, 0xE0, 0x2F, 0x6F, 0x06, 0x90, 0xFF, ++ 0x4F, 0xFC, 0x54, 0xE0, 0x2E, 0x06, 0x90, 0xF0, 0xFF, 0x08, 0x54, 0xE0, 0x80, 0x6E, 0x06, 0x90, ++ 0x6F, 0x06, 0x90, 0x19, 0xFF, 0x03, 0x54, 0xE0, 0xE0, 0x2F, 0x06, 0x90, 0xF0, 0x4F, 0xFC, 0x54, ++ 0xE0, 0x6E, 0x06, 0x90, 0x90, 0xFF, 0x08, 0x54, 0x54, 0xE0, 0x2E, 0x06, 0xE1, 0xF0, 0x4F, 0xF7, ++ 0xEF, 0x56, 0xAF, 0xBA, 0xFA, 0x24, 0x1F, 0x54, 0xF8, 0x24, 0x24, 0x60, 0xF4, 0x24, 0x47, 0x60, ++ 0x19, 0x24, 0x62, 0x60, 0x0D, 0x85, 0x74, 0x70, 0x83, 0x0C, 0x85, 0x82, 0xE0, 0xA3, 0xA3, 0xA3, ++ 0x85, 0xF0, 0xEF, 0x54, 0x0C, 0x85, 0x82, 0x0D, 0xA3, 0xA3, 0xA3, 0x83, 0x0D, 0xE5, 0x21, 0x80, ++ 0x82, 0xF5, 0x0D, 0x24, 0xF5, 0x0C, 0x35, 0xE4, 0xEF, 0x54, 0xE0, 0x83, 0xFF, 0x01, 0x90, 0xF0, ++ 0x46, 0xE0, 0x20, 0xE0, 0x0D, 0x24, 0x0D, 0xE5, 0x35, 0xE4, 0x82, 0xF5, 0xE0, 0x83, 0xF5, 0x0C, ++ 0x80, 0xF0, 0xFD, 0x54, 0xE3, 0x0C, 0x12, 0x35, 0x05, 0x08, 0x02, 0xBF, 0x70, 0x0B, 0xE5, 0x0B, ++ 0x12, 0x0A, 0x05, 0x02, 0x60, 0xEF, 0xE3, 0x0C, 0x24, 0x57, 0xE5, 0x21, 0x12, 0x13, 0x92, 0xFF, ++ 0x16, 0x80, 0x58, 0x0C, 0x34, 0x24, 0x0D, 0xE5, 0x35, 0xE4, 0x82, 0xF5, 0xE4, 0x83, 0xF5, 0x0C, ++ 0x90, 0xF0, 0xA3, 0xF0, 0x54, 0xE0, 0x07, 0x07, 0x57, 0xE5, 0xF0, 0xEF, 0x01, 0x90, 0x05, 0x70, ++ 0x90, 0x03, 0x80, 0xD2, 0x0A, 0xE5, 0xD4, 0x01, 0x0B, 0xE5, 0xA3, 0xF0, 0xD0, 0x07, 0xD0, 0xF0, ++ 0xD0, 0x05, 0xD0, 0x06, 0xD0, 0x03, 0xD0, 0x04, 0xD0, 0x01, 0xD0, 0x02, 0x01, 0xA2, 0x63, 0x00, ++ 0x83, 0xD0, 0x82, 0xD0, 0xD0, 0x01, 0xA2, 0x63, 0xD0, 0x82, 0xD0, 0xD0, 0xD0, 0xF0, 0xD0, 0x83, ++ 0xE0, 0xC0, 0x32, 0xE0, 0x83, 0xC0, 0xF0, 0xC0, 0xD0, 0xC0, 0x82, 0xC0, 0x63, 0x00, 0xD0, 0x75, ++ 0x83, 0xC0, 0x01, 0xA2, 0xA2, 0x63, 0x82, 0xC0, 0xC0, 0x00, 0xC0, 0x01, 0xC0, 0x02, 0xC0, 0x01, ++ 0xC0, 0x04, 0xC0, 0x03, 0xC0, 0x06, 0xC0, 0x05, 0x20, 0x58, 0x75, 0x07, 0x90, 0x00, 0x59, 0x75, ++ 0x04, 0x74, 0x65, 0x07, 0xCD, 0x01, 0x90, 0xF0, 0x90, 0xF0, 0x04, 0xE0, 0xFF, 0xE0, 0xD0, 0x01, ++ 0xE0, 0xCD, 0x01, 0x90, 0x40, 0x40, 0x9F, 0xD3, 0xE9, 0xC2, 0xF0, 0xE4, 0x5F, 0x65, 0x61, 0xE5, ++ 0x60, 0xE5, 0x04, 0x70, 0x00, 0x7F, 0x5E, 0x65, 0x01, 0x7F, 0x02, 0x60, 0x66, 0xE5, 0x66, 0x8F, ++ 0x60, 0x85, 0x06, 0x60, 0x5F, 0x61, 0x85, 0x5E, 0xE0, 0x43, 0x07, 0x90, 0x30, 0x0F, 0x54, 0xC4, ++ 0x54, 0xE0, 0x0F, 0xE0, 0x85, 0x90, 0xF5, 0x0F, 0x58, 0x85, 0x82, 0x59, 0xF5, 0x93, 0xE4, 0x83, ++ 0xA9, 0x5E, 0xAA, 0x5A, 0x27, 0x03, 0x12, 0x5F, 0xE0, 0xCE, 0x01, 0x90, 0x01, 0x90, 0xF0, 0x04, ++ 0x90, 0xFF, 0xE0, 0xD1, 0xD3, 0xE0, 0xCE, 0x01, 0xE4, 0x40, 0x40, 0x9F, 0xE5, 0xE9, 0xC2, 0xF0, ++ 0x70, 0x69, 0x65, 0x6B, 0x65, 0x6A, 0xE5, 0x04, 0x60, 0x00, 0x7F, 0x68, 0x8F, 0x01, 0x7F, 0x02, ++ 0x60, 0x70, 0xE5, 0x70, 0x68, 0x6A, 0x85, 0x06, 0x90, 0x69, 0x6B, 0x85, 0xC4, 0xE0, 0x44, 0x07, ++ 0xE0, 0x30, 0x0F, 0x54, 0x0F, 0x54, 0xE0, 0x0F, 0x59, 0x85, 0x90, 0xF5, 0x83, 0x58, 0x85, 0x82, ++ 0x5A, 0xF5, 0x93, 0xE4, 0x69, 0xA9, 0x68, 0xAA, 0x90, 0x27, 0x03, 0x12, 0x30, 0xE0, 0x7C, 0x07, ++ 0x01, 0x74, 0x0A, 0xE0, 0x34, 0x06, 0x90, 0xF0, 0xF0, 0x80, 0x44, 0xE0, 0xE0, 0xC5, 0x07, 0x90, ++ 0x74, 0x0A, 0xE0, 0x30, 0x06, 0x90, 0xF0, 0x01, 0x80, 0x44, 0xE0, 0x74, 0xBE, 0x03, 0x12, 0xF0, ++ 0x07, 0xD0, 0xE9, 0xD2, 0x05, 0xD0, 0x06, 0xD0, 0x03, 0xD0, 0x04, 0xD0, 0x01, 0xD0, 0x02, 0xD0, ++ 0xA2, 0x63, 0x00, 0xD0, 0xD0, 0x82, 0xD0, 0x01, 0x01, 0xA2, 0x63, 0x83, 0x82, 0xD0, 0xD0, 0xD0, ++ 0xF0, 0xD0, 0x83, 0xD0, 0xC0, 0x32, 0xE0, 0xD0, 0xC0, 0xF0, 0xC0, 0xE0, 0xC0, 0x82, 0xC0, 0x83, ++ 0x00, 0xD0, 0x75, 0xD0, 0xC0, 0x01, 0xA2, 0x63, 0x63, 0x82, 0xC0, 0x83, 0x00, 0xC0, 0x01, 0xA2, ++ 0x02, 0xC0, 0x01, 0xC0, 0x04, 0xC0, 0x03, 0xC0, 0x06, 0xC0, 0x05, 0xC0, 0x07, 0x90, 0x07, 0xC0, ++ 0xF0, 0x08, 0x74, 0x65, 0x01, 0x90, 0xEA, 0xC2, 0xF0, 0x04, 0xE0, 0xCF, 0x32, 0x94, 0xC3, 0xE0, ++ 0x80, 0x31, 0x07, 0x40, 0xE4, 0xCF, 0x01, 0x90, 0xD0, 0xEA, 0xD2, 0xF0, 0xD0, 0x06, 0xD0, 0x07, ++ 0xD0, 0x04, 0xD0, 0x05, 0xD0, 0x02, 0xD0, 0x03, 0x63, 0x00, 0xD0, 0x01, 0x82, 0xD0, 0x01, 0xA2, ++ 0xA2, 0x63, 0x83, 0xD0, 0xD0, 0xD0, 0xD0, 0x01, 0xD0, 0x83, 0xD0, 0x82, 0x32, 0xE0, 0xD0, 0xF0, ++ 0x74, 0xD8, 0x01, 0x90, 0x74, 0xA3, 0xF0, 0x01, 0x01, 0x90, 0xF0, 0xE2, 0x54, 0xC4, 0xE0, 0xE0, ++ 0x03, 0x54, 0xFF, 0x0F, 0xA8, 0x64, 0x74, 0xFE, 0x02, 0x80, 0x08, 0x06, 0xFC, 0xD8, 0x13, 0xC3, ++ 0x13, 0xEF, 0x5B, 0xF5, 0x54, 0x3F, 0x54, 0x13, 0x64, 0x74, 0xFF, 0x03, 0x80, 0x08, 0x07, 0xA8, ++ 0xD8, 0x13, 0xC3, 0x02, 0x17, 0x78, 0xF9, 0xFC, 0x95, 0xC3, 0x06, 0xE6, 0xE4, 0x02, 0x40, 0x5B, ++ 0xE6, 0x12, 0x78, 0xF6, 0x40, 0x99, 0xC3, 0x06, 0xE4, 0xF6, 0xE4, 0x02, 0x01, 0x90, 0xFA, 0xFB, ++ 0xA3, 0xFE, 0xE0, 0xD8, 0x8E, 0x82, 0xF5, 0xE0, 0x5C, 0xF5, 0xE0, 0x83, 0x5D, 0xF5, 0xE0, 0xA3, ++ 0xE0, 0xD9, 0x01, 0x90, 0x90, 0xF0, 0x02, 0x24, 0x34, 0xE0, 0xD8, 0x01, 0x13, 0x74, 0xF0, 0x00, ++ 0xD3, 0xE6, 0xF8, 0x2A, 0x1E, 0x40, 0x00, 0x94, 0x74, 0xFF, 0x13, 0xE9, 0xE6, 0xF8, 0x2A, 0x13, ++ 0x50, 0x9F, 0xD3, 0x16, 0x74, 0xA6, 0x41, 0x02, 0x08, 0x02, 0xA8, 0x01, 0x33, 0xC3, 0x02, 0x80, ++ 0x03, 0x42, 0xFC, 0xD8, 0x54, 0xEA, 0xA6, 0x41, 0x24, 0xE0, 0x25, 0x01, 0xE4, 0x82, 0xF5, 0xC9, ++ 0x83, 0xF5, 0x01, 0x34, 0x13, 0x13, 0x13, 0xE0, 0xAE, 0xFF, 0x1F, 0x54, 0x07, 0x54, 0xEE, 0x5D, ++ 0x74, 0x08, 0x60, 0x5F, 0xA6, 0xF8, 0x2A, 0x13, 0xE5, 0x6B, 0x80, 0x01, 0x0F, 0x54, 0xC4, 0x5D, ++ 0x92, 0x13, 0xEA, 0xFF, 0xEF, 0xD8, 0x51, 0x15, 0x5B, 0xE5, 0x1B, 0x60, 0x78, 0xFF, 0x13, 0xC3, ++ 0x9F, 0xD3, 0xE6, 0x17, 0x01, 0x74, 0x50, 0x40, 0x80, 0x08, 0x02, 0xA8, 0xD8, 0x33, 0xC3, 0x02, ++ 0x80, 0x03, 0x42, 0xFC, 0x92, 0x13, 0xEA, 0x41, 0x51, 0x5C, 0xAF, 0x15, 0x1A, 0x60, 0xEF, 0xD8, ++ 0xFF, 0x13, 0xC3, 0xE9, 0xD3, 0xE6, 0x12, 0x78, 0x74, 0x2B, 0x40, 0x9F, 0x08, 0x02, 0xA8, 0x01, ++ 0x33, 0xC3, 0x02, 0x80, 0x03, 0x42, 0xFC, 0xD8, 0x5C, 0xE5, 0x1C, 0x80, 0xFF, 0x0F, 0x54, 0xC4, ++ 0x15, 0x92, 0x13, 0xEA, 0x60, 0xEF, 0xD8, 0x51, 0xA8, 0x01, 0x74, 0x0D, 0x02, 0x80, 0x08, 0x02, ++ 0xFC, 0xD8, 0x33, 0xC3, 0xEA, 0x0A, 0x03, 0x42, 0x02, 0x60, 0x04, 0x64, 0x01, 0x90, 0xCE, 0x21, ++ 0xC7, 0x54, 0xE0, 0xC9, 0xCB, 0x01, 0x90, 0xF0, 0xF0, 0xC7, 0x54, 0xE0, 0xE0, 0x36, 0x06, 0x90, ++ 0x52, 0xFA, 0x0F, 0x54, 0xFF, 0x02, 0x63, 0x03, 0x54, 0xE0, 0xA3, 0xE0, 0x03, 0x42, 0x5A, 0x0F, ++ 0x90, 0x80, 0x44, 0xEB, 0x22, 0xF0, 0x08, 0x07, 0x04, 0x53, 0x07, 0xAC, 0xE3, 0x30, 0xEC, 0x0F, ++ 0xE4, 0x15, 0xA2, 0x29, 0xFF, 0xE0, 0x25, 0x33, 0x74, 0xFE, 0x33, 0xE4, 0x82, 0xF5, 0x2F, 0xC8, ++ 0xF5, 0x3E, 0x01, 0x74, 0xEC, 0xFF, 0xE0, 0x83, 0x74, 0xFE, 0x07, 0x54, 0x08, 0x06, 0xA8, 0x01, ++ 0x33, 0xC3, 0x02, 0x80, 0xFD, 0x5F, 0xFC, 0xD8, 0x15, 0xA2, 0x1D, 0x80, 0xE0, 0x25, 0x33, 0xE4, ++ 0xFE, 0x33, 0xE4, 0xFF, 0xF5, 0x2F, 0xC9, 0x74, 0x3E, 0x01, 0x74, 0x82, 0xFF, 0xE0, 0x83, 0xF5, ++ 0xFE, 0x07, 0x54, 0xEC, 0xAF, 0xFD, 0x5E, 0xEF, 0xE0, 0xC0, 0x22, 0x05, 0x82, 0xC0, 0x83, 0xC0, ++ 0xD0, 0x75, 0xD0, 0xC0, 0x01, 0xA2, 0x63, 0x00, 0x82, 0xC0, 0x83, 0xC0, 0xC0, 0x01, 0xA2, 0x63, ++ 0x65, 0x07, 0x90, 0x07, 0x0F, 0x54, 0xC4, 0xE0, 0x90, 0x22, 0xE0, 0x30, 0x44, 0xE0, 0x00, 0x06, ++ 0x06, 0x90, 0xF0, 0x80, 0x80, 0x44, 0xE0, 0x40, 0xE5, 0xE8, 0xC2, 0xF0, 0xF5, 0x01, 0x44, 0x20, ++ 0x44, 0x21, 0xE5, 0x20, 0x90, 0x21, 0xF5, 0x01, 0x10, 0x74, 0x65, 0x07, 0x63, 0x07, 0xD0, 0xF0, ++ 0x82, 0xD0, 0x01, 0xA2, 0xA2, 0x63, 0x83, 0xD0, 0xD0, 0xD0, 0xD0, 0x01, 0xD0, 0x83, 0xD0, 0x82, ++ 0x13, 0xA2, 0x32, 0xE0, 0x14, 0xA2, 0x14, 0x92, 0xF8, 0xC4, 0x33, 0xE4, 0x68, 0xC8, 0x0F, 0x54, ++ 0x54, 0xC4, 0xE4, 0xFF, 0x74, 0xFE, 0x48, 0xF0, 0x74, 0xF9, 0x2F, 0x9C, 0x01, 0xAF, 0x3E, 0x01, ++ 0x09, 0x8F, 0x08, 0xF5, 0xC3, 0xEF, 0x0B, 0xAF, 0x0B, 0xE5, 0xFD, 0x13, 0xFD, 0x01, 0x54, 0x4D, ++ 0x13, 0x13, 0x13, 0xEF, 0xEF, 0xFF, 0x06, 0x54, 0x01, 0x90, 0xFF, 0x4D, 0xA3, 0xF0, 0xE4, 0xD6, ++ 0x25, 0xE0, 0xF0, 0xEF, 0x01, 0x90, 0xFF, 0xE0, 0xFE, 0x33, 0xE0, 0xD6, 0xF5, 0x09, 0x25, 0xEF, ++ 0x08, 0x35, 0xEE, 0x09, 0x71, 0x22, 0x08, 0xF5, 0x24, 0x0D, 0xE5, 0x82, 0xE4, 0x82, 0xF5, 0x1B, ++ 0x83, 0xF5, 0x0C, 0x35, 0x24, 0x1F, 0x54, 0xE0, 0x24, 0x28, 0x60, 0xF9, 0x14, 0x46, 0x60, 0xE9, ++ 0x1C, 0x24, 0x52, 0x60, 0x0B, 0xE5, 0x61, 0x70, 0x0D, 0xE5, 0x5D, 0x70, 0x82, 0xF5, 0x1C, 0x24, ++ 0xF5, 0x0C, 0x35, 0xE4, 0x04, 0x54, 0xE0, 0x83, 0x85, 0x82, 0x09, 0x85, 0xA3, 0xF0, 0x83, 0x08, ++ 0xE5, 0x22, 0xF0, 0xE4, 0x70, 0x3C, 0x64, 0x0B, 0x24, 0x0D, 0xE5, 0x3E, 0xE4, 0x82, 0xF5, 0x1C, ++ 0x83, 0xF5, 0x0C, 0x35, 0x02, 0x54, 0xE0, 0xA3, 0x82, 0x09, 0x85, 0xFF, 0xE4, 0x83, 0x08, 0x85, ++ 0xF0, 0xEF, 0xA3, 0xF0, 0x2C, 0x06, 0x90, 0x22, 0xF0, 0x40, 0x44, 0xE0, 0xE0, 0x6C, 0x06, 0x90, ++ 0x22, 0xF0, 0x40, 0x44, 0x1D, 0x24, 0x0D, 0xE5, 0x35, 0xE4, 0x82, 0xF5, 0xE0, 0x83, 0xF5, 0x0C, ++ 0x85, 0x82, 0x0B, 0x85, 0x22, 0xF0, 0x83, 0x0A, 0x1C, 0x24, 0x0D, 0xE5, 0x35, 0xE4, 0x82, 0xF5, ++ 0xE4, 0x83, 0xF5, 0x0C, 0x71, 0xF0, 0xA3, 0xF0, 0x24, 0x0D, 0xE5, 0x82, 0xE4, 0x82, 0xF5, 0x1B, ++ 0x83, 0xF5, 0x0C, 0x35, 0x24, 0x1F, 0x54, 0xE0, 0x24, 0x1E, 0x60, 0xF9, 0x14, 0x3F, 0x60, 0xE9, ++ 0x1C, 0x24, 0x4B, 0x60, 0x0B, 0xE5, 0x5C, 0x70, 0x24, 0x0C, 0x60, 0x14, 0x24, 0x08, 0x60, 0xED, ++ 0x24, 0x04, 0x60, 0xFE, 0x80, 0x4B, 0x70, 0x16, 0x24, 0x0B, 0xE5, 0x09, 0x04, 0x03, 0x60, 0xC3, ++ 0x09, 0x85, 0x40, 0x70, 0x83, 0x08, 0x85, 0x82, 0xE0, 0xA3, 0xFE, 0xE0, 0x24, 0x0D, 0xE5, 0xFF, ++ 0xE4, 0x82, 0xF5, 0x1C, 0x83, 0xF5, 0x0C, 0x35, 0xEF, 0xA3, 0xF0, 0xEE, 0x06, 0x90, 0x22, 0xF0, ++ 0x40, 0x44, 0xE0, 0x2C, 0x6C, 0x06, 0x90, 0xF0, 0xF0, 0x40, 0x44, 0xE0, 0x82, 0x0B, 0x85, 0x22, ++ 0xE0, 0x83, 0x0A, 0x85, 0x24, 0x0D, 0xE5, 0xFF, 0xE4, 0x82, 0xF5, 0x1D, 0x83, 0xF5, 0x0C, 0x35, ++ 0xE5, 0x22, 0xF0, 0xEF, 0xF5, 0x1A, 0x24, 0x0D, 0x0C, 0x35, 0xE4, 0x82, 0xC4, 0xE0, 0x83, 0xF5, ++ 0x03, 0x54, 0x13, 0x13, 0x07, 0x90, 0x22, 0xFF, 0x13, 0xFE, 0xE0, 0x42, 0x1F, 0x54, 0x13, 0x13, ++ 0x74, 0x04, 0xE0, 0x30, 0x20, 0xFF, 0x2F, 0x80, 0x17, 0x20, 0x2A, 0x16, 0x02, 0x17, 0xD2, 0x05, ++ 0xAC, 0xC2, 0x0D, 0x00, 0x0F, 0x05, 0x0F, 0xAE, 0x54, 0x00, 0x7C, 0xEE, 0xF5, 0x00, 0x24, 0x7F, ++ 0x02, 0x34, 0xEC, 0x82, 0xF0, 0xEF, 0x83, 0xF5, 0x0E, 0x65, 0x0F, 0xE5, 0x02, 0x70, 0x7F, 0x54, ++ 0xAC, 0xD2, 0x16, 0xD2, 0xC4, 0xFF, 0xE0, 0x22, 0x54, 0x13, 0x13, 0x13, 0x00, 0x7C, 0xFD, 0x01, ++ 0x2A, 0x8A, 0x29, 0x8B, 0x2C, 0x8C, 0x2B, 0x89, 0x11, 0xC2, 0x2D, 0x8D, 0x2A, 0xAA, 0x29, 0xAB, ++ 0x02, 0x12, 0x2B, 0xA9, 0x02, 0x70, 0xFF, 0xA7, 0x11, 0x20, 0x47, 0xC1, 0x04, 0x25, 0xB4, 0x19, ++ 0x3A, 0xC1, 0x11, 0xD2, 0x08, 0x0A, 0xB4, 0xEF, 0xF6, 0x91, 0x0D, 0x7F, 0x38, 0xC1, 0x0A, 0x7F, ++ 0xFF, 0xA7, 0x02, 0x12, 0x11, 0xC2, 0x38, 0xC1, 0xFB, 0xA7, 0x02, 0x12, 0x4E, 0x60, 0xBC, 0x24, ++ 0x62, 0x60, 0xE0, 0x24, 0x02, 0x60, 0xEC, 0x24, 0x2E, 0x75, 0x35, 0xC1, 0x2E, 0xE5, 0xC3, 0x0C, ++ 0x80, 0x94, 0x80, 0x64, 0x3A, 0xC1, 0x02, 0x50, 0x2C, 0xAE, 0x2D, 0xE5, 0x80, 0x08, 0x2E, 0xA8, ++ 0xE7, 0xA2, 0xCE, 0x06, 0xD8, 0x13, 0xCE, 0x13, 0xF5, 0x0F, 0x54, 0xF8, 0x80, 0x64, 0xD3, 0x34, ++ 0x08, 0x40, 0x89, 0x94, 0x37, 0x24, 0x34, 0xE5, 0x06, 0x80, 0x34, 0xF5, 0x34, 0x25, 0x30, 0x74, ++ 0x34, 0xAF, 0x34, 0xF5, 0xFC, 0x74, 0xF6, 0x91, 0x2E, 0xF5, 0x2E, 0x25, 0xE5, 0xC3, 0xBF, 0x80, ++ 0x94, 0x80, 0x64, 0x2C, 0xC3, 0x0F, 0x50, 0x80, 0xF5, 0x2D, 0x95, 0xE4, 0x2C, 0x95, 0xE4, 0x2D, ++ 0x2D, 0x7F, 0x2C, 0xF5, 0x2D, 0xE5, 0xF6, 0x91, 0x04, 0x70, 0x2C, 0x45, 0xF6, 0x91, 0x30, 0x7F, ++ 0xE5, 0x2E, 0xF5, 0xE4, 0x60, 0x2C, 0x45, 0x2D, 0xAF, 0x2C, 0xAE, 0x2B, 0x7D, 0x00, 0x7C, 0x2D, ++ 0xD2, 0x02, 0x12, 0x0A, 0xFF, 0x30, 0x24, 0xED, 0x2E, 0x05, 0x2E, 0xAE, 0xF8, 0x2E, 0x2F, 0x74, ++ 0xAE, 0xC6, 0xEF, 0xC6, 0x7C, 0x2D, 0xAF, 0x2C, 0x12, 0x0A, 0x7D, 0x00, 0x2C, 0x8E, 0xD2, 0x02, ++ 0xCF, 0x80, 0x2D, 0x8F, 0x12, 0x60, 0x2E, 0xE5, 0x2F, 0x74, 0x2E, 0x15, 0xE6, 0xF8, 0x2E, 0x25, ++ 0x80, 0xF6, 0x91, 0xFF, 0xCF, 0xEB, 0xCF, 0xEF, 0x01, 0x74, 0xF6, 0x91, 0x2B, 0xF5, 0x2B, 0x25, ++ 0xF5, 0x2A, 0x35, 0xE4, 0x22, 0x4C, 0xA1, 0x2A, 0x00, 0xA9, 0x07, 0xA8, 0x47, 0x19, 0xE7, 0x09, ++ 0xE6, 0x08, 0x09, 0x60, 0x01, 0x70, 0x18, 0x16, 0xD3, 0x22, 0xC3, 0x16, 0xE4, 0x10, 0xA2, 0x22, ++ 0xF8, 0x20, 0x24, 0x33, 0xC3, 0x37, 0x54, 0xE6, 0x22, 0xD3, 0x01, 0x60, 0x12, 0xAC, 0x01, 0x12, ++ 0x32, 0x59, 0x48, 0x50, 0x56, 0x5F, 0x46, 0x32, 0x00, 0x0A, 0x39, 0x52, 0x4C, 0x4F, 0x54, 0x50, ++ 0x44, 0x25, 0x20, 0x3A, 0x93, 0xAA, 0x00, 0x0A, 0x39, 0x4F, 0x66, 0x7D, 0xF5, 0xE4, 0x0B, 0x22, ++ 0xC2, 0x0F, 0xF5, 0x0E, 0x22, 0x16, 0xC2, 0x17, 0xF5, 0x7F, 0x22, 0x7E, 0x7E, 0x73, 0x03, 0x12, ++ 0x12, 0x51, 0x7F, 0x26, 0x26, 0x7E, 0x73, 0x03, 0x03, 0x12, 0x19, 0x7F, 0x7F, 0x26, 0x7E, 0x73, ++ 0x73, 0x03, 0x12, 0xC1, 0xC1, 0x7F, 0x26, 0x7E, 0x7E, 0x73, 0x03, 0x12, 0x12, 0x07, 0x7F, 0x28, ++ 0x28, 0x7E, 0x73, 0x03, 0x03, 0x12, 0x09, 0x7F, 0x7F, 0x28, 0x7E, 0x73, 0x73, 0x03, 0x12, 0x2D, ++ 0x68, 0x7F, 0x24, 0x7E, 0x7E, 0x73, 0x03, 0x12, 0x12, 0x21, 0x7F, 0x28, 0x24, 0x7E, 0x73, 0x03, ++ 0x03, 0x12, 0x68, 0x7F, 0x7F, 0x27, 0x7E, 0x73, 0x73, 0x03, 0x12, 0xE7, 0xE7, 0x7F, 0x27, 0x7E, ++ 0x7E, 0x73, 0x03, 0x12, 0x02, 0x81, 0x7F, 0x2E, 0xF5, 0xE4, 0x73, 0x03, 0xF5, 0x5F, 0xF5, 0x5E, ++ 0xF5, 0x69, 0xF5, 0x68, 0xF5, 0x63, 0xF5, 0x62, 0xF5, 0x6D, 0xF5, 0x6C, 0xF5, 0x65, 0xF5, 0x64, ++ 0x75, 0x6F, 0xF5, 0x6E, 0x70, 0x75, 0x01, 0x66, 0x01, 0x67, 0x75, 0x01, 0x75, 0x01, 0x71, 0x75, ++ 0x61, 0x75, 0x02, 0x60, 0x02, 0x6A, 0x75, 0x0B, 0x31, 0x24, 0x6B, 0x75, 0x7B, 0x1E, 0x11, 0x9D, ++ 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x00, 0x03, 0x12, 0x55, 0x31, 0x7D, 0x90, 0x31, 0xB8, ++ 0xE4, 0x13, 0x7C, 0x88, 0x7D, 0xAB, 0x31, 0xFF, 0xE4, 0x61, 0x7C, 0xA8, 0xE4, 0xD2, 0x31, 0xFF, ++ 0x7F, 0xFA, 0x11, 0xFF, 0x31, 0xFA, 0x11, 0x01, 0x12, 0xFB, 0x31, 0x11, 0x02, 0x12, 0x42, 0x02, ++ 0x00, 0x07, 0x90, 0x5B, 0xD2, 0xF0, 0x01, 0x74, 0x07, 0xAD, 0x22, 0xE8, 0x90, 0x07, 0x70, 0xED, ++ 0x44, 0xE0, 0x47, 0x07, 0x01, 0xBD, 0xF0, 0x01, 0x47, 0x07, 0x90, 0x07, 0xF0, 0x02, 0x44, 0xE0, ++ 0x07, 0x07, 0x90, 0x22, 0x90, 0xF0, 0x01, 0x74, 0x04, 0x74, 0x00, 0x07, 0x90, 0xF0, 0xE4, 0xF0, ++ 0x90, 0xF0, 0x03, 0x07, 0x90, 0xF0, 0x04, 0x07, 0xF0, 0x04, 0x05, 0x07, 0x74, 0x06, 0x07, 0x90, ++ 0x07, 0x90, 0xF0, 0xFF, 0xF0, 0x04, 0x74, 0x01, 0xF0, 0x08, 0x44, 0xE0, 0x24, 0x75, 0x10, 0xC2, ++ 0x06, 0x02, 0x12, 0x02, 0x24, 0x75, 0x10, 0xD2, 0x06, 0x02, 0x12, 0x02, 0x74, 0x00, 0x07, 0x90, ++ 0x01, 0x22, 0xF0, 0x01, 0x8B, 0x0D, 0x90, 0x8A, 0x0F, 0x54, 0xC4, 0xE0, 0x30, 0x10, 0xC2, 0xFF, ++ 0x10, 0xD2, 0x05, 0xE3, 0xEF, 0x0F, 0x07, 0x63, 0x93, 0x16, 0x20, 0x90, 0x30, 0x00, 0x7C, 0xFD, ++ 0xE4, 0xC3, 0x07, 0x10, 0x9C, 0xE4, 0xFD, 0x9D, 0x8B, 0x0D, 0x90, 0xFC, 0x13, 0xC3, 0xFF, 0xE0, ++ 0x7C, 0x04, 0xE0, 0x20, 0x7B, 0xFF, 0x7D, 0x7F, 0x79, 0x20, 0x7A, 0xFF, 0x40, 0x0D, 0x02, 0x0C, ++ 0x89, 0x43, 0x8C, 0xC2, 0x8A, 0xF5, 0xE4, 0x01, 0x8C, 0xD2, 0x8C, 0xF5, 0x75, 0x8E, 0xC2, 0x22, ++ 0x89, 0x43, 0xC2, 0x98, 0xEF, 0x8D, 0x75, 0x20, 0x90, 0x22, 0x8E, 0xD2, 0x54, 0xE0, 0x47, 0x07, ++ 0x54, 0xEF, 0xF0, 0xFE, 0x07, 0x90, 0xFF, 0x01, 0xFE, 0x54, 0xE0, 0x48, 0x90, 0xE4, 0xF0, 0x4F, ++ 0x90, 0xF0, 0x4A, 0x07, 0xED, 0xF0, 0x49, 0x07, 0xF0, 0x4C, 0x07, 0x90, 0x4B, 0x07, 0x90, 0xEC, ++ 0x07, 0x90, 0x22, 0xF0, 0xFD, 0x54, 0xE0, 0x47, 0x01, 0x54, 0xEF, 0xF0, 0x90, 0xFF, 0xE0, 0x25, ++ 0x54, 0xE0, 0x48, 0x07, 0xE4, 0xF0, 0x4F, 0xFD, 0xF0, 0x4E, 0x07, 0x90, 0xF0, 0x4D, 0x07, 0x90, ++ 0x50, 0x07, 0x90, 0xED, 0x07, 0x90, 0xEC, 0xF0, 0xE4, 0x22, 0xF0, 0x4F, 0xF0, 0xC8, 0x01, 0x90, ++ 0xF0, 0xA3, 0xF0, 0xA3, 0x17, 0x78, 0xF0, 0xA3, 0xF6, 0x12, 0x78, 0xF6, 0x08, 0xF6, 0x13, 0x78, ++ 0x08, 0xF6, 0x08, 0xF6, 0xE0, 0x01, 0x90, 0xF6, 0xA3, 0xF0, 0xD0, 0x74, 0x01, 0x90, 0xF0, 0xE4, ++ 0xF0, 0x30, 0x74, 0xE2, 0xF0, 0x03, 0x74, 0xA3, 0x74, 0xE4, 0x01, 0x90, 0x74, 0xA3, 0xF0, 0x30, ++ 0x01, 0x90, 0xF0, 0x03, 0xF0, 0x20, 0x74, 0xE6, 0x90, 0xF0, 0xE4, 0xA3, 0x20, 0x74, 0xE8, 0x01, ++ 0xF0, 0xE4, 0xA3, 0xF0, 0x74, 0x36, 0x06, 0x90, 0xE4, 0xA3, 0xF0, 0x0F, 0x08, 0x07, 0x90, 0xF0, ++ 0x80, 0x44, 0xE0, 0xF0, 0x00, 0x22, 0x22, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xC0, 0x00, 0xEE, 0x00, 0x1E, 0x00, 0xDE, 0x00, 0x49, 0x78, 0x00, 0x90, 0x18, 0xA4, 0x65, 0xD5, ++ 0x00, 0x00, 0xE1, 0x01, 0x01, 0x20, 0x04, 0x00, 0x00, 0x00, 0x01, 0x20, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x80, 0x01, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x06, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, ++ 0xAA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x01, 0xFF, 0xFF, 0x3F, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, ++ 0xFF, 0xFF, 0x00, 0x40, 0x00, 0x48, 0xFF, 0xFF, 0x00, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, ++ 0xE0, 0x3F, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xF8, 0x00, 0xFF, 0xFF, ++ 0xFF, 0xF0, 0xF8, 0x3E, 0x3C, 0x66, 0xFF, 0x7F, 0xC0, 0x43, 0xFF, 0xFF, 0xF0, 0xF0, 0xFF, 0xFF, ++ 0x00, 0x00, 0x8C, 0xD0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xE4, 0x10, 0xA2, 0xC3, 0x06, 0x78, 0x33, ++ 0xCE, 0x33, 0xCE, 0x33, 0x00, 0x24, 0xF9, 0xD8, 0x06, 0x74, 0x82, 0xF5, 0xF5, 0x82, 0xAF, 0x3E, ++ 0xFE, 0x26, 0x8F, 0x25, 0x08, 0x7D, 0x20, 0x7C, 0xC5, 0x31, 0x24, 0xAB, 0x02, 0xB4, 0x24, 0xE5, ++ 0x24, 0x26, 0xE5, 0x11, 0x35, 0xE4, 0xFF, 0x80, 0x20, 0x7C, 0xFE, 0x25, 0x02, 0x7B, 0x48, 0x7D, ++ 0x24, 0xE5, 0xC5, 0x31, 0x17, 0x60, 0x02, 0x64, 0x03, 0x64, 0x24, 0xE5, 0x57, 0x21, 0x02, 0x60, ++ 0x28, 0x24, 0x26, 0xE5, 0x35, 0xE4, 0x82, 0xF5, 0xE0, 0x83, 0xF5, 0x25, 0xA2, 0x78, 0xE0, 0x20, ++ 0xC4, 0x33, 0xE4, 0x10, 0xC8, 0x0F, 0x54, 0xF8, 0xC4, 0xE4, 0xFF, 0x68, 0xFE, 0x48, 0xF0, 0x54, ++ 0xF5, 0x2F, 0x9C, 0x74, 0x3E, 0x01, 0x74, 0x82, 0xF0, 0xE4, 0x83, 0xF5, 0x9E, 0x74, 0xF0, 0xA3, ++ 0x74, 0x82, 0xF5, 0x2F, 0x83, 0xF5, 0x3E, 0x01, 0xF0, 0xA3, 0xF0, 0xE4, 0xF5, 0x2F, 0xA0, 0x74, ++ 0x3E, 0x01, 0x74, 0x82, 0xF0, 0xE4, 0x83, 0xF5, 0xA2, 0x74, 0xF0, 0xA3, 0x74, 0x82, 0xF5, 0x2F, ++ 0x83, 0xF5, 0x3E, 0x01, 0xF0, 0xA3, 0xF0, 0xE4, 0xF5, 0x2F, 0xA8, 0x74, 0x3E, 0x01, 0x74, 0x82, ++ 0xF0, 0xE4, 0x83, 0xF5, 0xAA, 0x74, 0xF0, 0xA3, 0x74, 0x82, 0xF5, 0x2F, 0x83, 0xF5, 0x3E, 0x01, ++ 0xF0, 0xA3, 0xF0, 0xE4, 0xF0, 0xFF, 0x01, 0x90, 0x90, 0x05, 0x10, 0x30, 0x04, 0x80, 0xD4, 0x01, ++ 0xD2, 0x01, 0x90, 0xE4, 0xE4, 0xF0, 0xA3, 0xF0, 0x0D, 0x07, 0x90, 0xFF, 0x54, 0x13, 0x13, 0xE0, ++ 0x02, 0xE0, 0x30, 0x3F, 0x07, 0x90, 0x02, 0x7F, 0x13, 0x13, 0xE0, 0x0D, 0x30, 0x1F, 0x54, 0x13, ++ 0x07, 0x43, 0x03, 0xE0, 0x0D, 0x07, 0x90, 0x01, 0x0F, 0x54, 0xC4, 0xE0, 0x43, 0x03, 0xE0, 0x30, ++ 0x07, 0x90, 0x08, 0x07, 0x13, 0xC4, 0xE0, 0x0D, 0xE0, 0x30, 0x07, 0x54, 0x04, 0x07, 0x43, 0x03, ++ 0x78, 0xEF, 0x00, 0x7E, 0xCE, 0x33, 0xC3, 0x05, 0xF9, 0xD8, 0xCE, 0x33, 0x24, 0x26, 0xE5, 0xFF, ++ 0xE4, 0x82, 0xF5, 0x08, 0x83, 0xF5, 0x25, 0x35, 0x82, 0xC0, 0x83, 0xC0, 0xFC, 0xE0, 0x54, 0xE0, ++ 0x1F, 0x54, 0xE0, 0xA3, 0xFE, 0x4E, 0xEC, 0xFD, 0xD0, 0xFF, 0x4F, 0xED, 0xEE, 0x83, 0xD0, 0x82, ++ 0xF0, 0xEF, 0xA3, 0xF0, 0x8F, 0x27, 0x8E, 0x22, 0x8D, 0x29, 0x8C, 0x28, 0x8F, 0x31, 0x8E, 0x2A, ++ 0x24, 0x32, 0xE5, 0x32, 0xE4, 0x82, 0xF5, 0x28, 0x83, 0xF5, 0x31, 0x35, 0x11, 0x92, 0x13, 0xE0, ++ 0x2C, 0x24, 0x32, 0xE5, 0x35, 0xE4, 0x82, 0xF5, 0xE0, 0x83, 0xF5, 0x31, 0x13, 0x13, 0x13, 0xC4, ++ 0x92, 0x13, 0x01, 0x54, 0xEB, 0xFF, 0xE4, 0x12, 0x0B, 0x60, 0xFD, 0x24, 0x65, 0x70, 0x03, 0x24, ++ 0xF5, 0x2B, 0xF5, 0xE4, 0x30, 0x79, 0x80, 0x2C, 0xD3, 0xEF, 0x5B, 0x11, 0x55, 0x40, 0x0F, 0x94, ++ 0x24, 0xE0, 0x25, 0xEF, 0xE4, 0x82, 0xF5, 0x48, 0x83, 0xF5, 0x20, 0x34, 0x2F, 0xF5, 0x93, 0xE4, ++ 0xF5, 0x93, 0x01, 0x74, 0xFD, 0x2A, 0xE5, 0x30, 0x2A, 0xF5, 0x02, 0x24, 0x34, 0xFC, 0x29, 0xE5, ++ 0x8D, 0x29, 0xF5, 0x00, 0xE4, 0x83, 0x8C, 0x82, 0xF5, 0x2F, 0x55, 0x93, 0x93, 0x01, 0x74, 0x2D, ++ 0x2E, 0xF5, 0x30, 0x55, 0x85, 0x82, 0x28, 0x85, 0x30, 0xE5, 0x83, 0x27, 0x2F, 0xE5, 0xFD, 0xF4, ++ 0x5C, 0xE0, 0xFC, 0xF4, 0x5D, 0xE0, 0xA3, 0xFC, 0x4C, 0x2D, 0xE5, 0xFD, 0x2E, 0xE5, 0x2B, 0xF5, ++ 0x80, 0x2C, 0xF5, 0x4D, 0xFD, 0x2A, 0xE5, 0x1B, 0x2A, 0xF5, 0x02, 0x24, 0x34, 0xFC, 0x29, 0xE5, ++ 0x8D, 0x29, 0xF5, 0x00, 0xE4, 0x83, 0x8C, 0x82, 0x74, 0x2B, 0xF5, 0x93, 0x2C, 0xF5, 0x93, 0x01, ++ 0x24, 0xFD, 0x28, 0xE5, 0xE5, 0x28, 0xF5, 0x02, 0x00, 0x34, 0xFC, 0x27, 0x82, 0x8D, 0x27, 0xF5, ++ 0x2B, 0xE5, 0x83, 0x8C, 0x2C, 0xE5, 0xA3, 0xF0, 0x64, 0xEF, 0x0F, 0xF0, 0x21, 0x02, 0x60, 0x20, ++ 0x0F, 0x11, 0x30, 0xF7, 0x38, 0x24, 0x32, 0xE5, 0x35, 0xE4, 0x82, 0xF5, 0xE4, 0x83, 0xF5, 0x31, ++ 0xEB, 0xF0, 0xA3, 0xF0, 0x33, 0x70, 0x03, 0x64, 0x54, 0x33, 0x11, 0xA2, 0x32, 0xE5, 0xFF, 0x01, ++ 0x82, 0xF5, 0x28, 0x24, 0xF5, 0x31, 0x35, 0xE4, 0xFE, 0x54, 0xE0, 0x83, 0x12, 0xA2, 0xF0, 0x4F, ++ 0x01, 0x54, 0x33, 0xE4, 0x33, 0x33, 0x33, 0xC4, 0xE5, 0xFF, 0x80, 0x54, 0xF5, 0x2C, 0x24, 0x32, ++ 0x31, 0x35, 0xE4, 0x82, 0x54, 0xE0, 0x83, 0xF5, 0x22, 0xF0, 0x4F, 0x7F, 0x74, 0x00, 0x20, 0x90, ++ 0x24, 0xF5, 0x93, 0x01, 0x00, 0x00, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x6E, 0x69, 0x61, 0x4D, 0x6E, 0x49, 0x00, 0x0A, 0x00, 0x0A, 0x74, 0x69, 0x69, 0x74, 0x63, 0x41, ++ 0x00, 0x0A, 0x65, 0x76, 0x65, 0x52, 0x41, 0x09, 0x09, 0x00, 0x0A, 0x73, 0x20, 0x3E, 0x2D, 0x09, ++ 0x30, 0x00, 0x30, 0x31, 0x44, 0x46, 0x2D, 0x00, 0x44, 0x48, 0x2D, 0x00, 0x45, 0x45, 0x2F, 0x00, ++ 0x50, 0x2D, 0x00, 0x45, 0x64, 0x25, 0x3A, 0x53, 0x43, 0x09, 0x00, 0x0A, 0x4B, 0x43, 0x41, 0x2D, ++ 0x09, 0x09, 0x00, 0x0A, 0x53, 0x46, 0x58, 0x52, 0x64, 0x25, 0x3D, 0x4D, 0x4E, 0x09, 0x00, 0x0A, ++ 0x61, 0x57, 0x2D, 0x50, 0x00, 0x0A, 0x74, 0x69, 0x58, 0x54, 0x09, 0x09, 0x3D, 0x4D, 0x53, 0x46, ++ 0x00, 0x0A, 0x64, 0x25, 0x69, 0x62, 0x41, 0x09, 0x0A, 0x44, 0x2D, 0x6C, 0x7B, 0x00, 0x0A, 0x00, ++ 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x06, 0x69, 0x65, 0x15, 0x74, 0x00, 0x74, 0x04, 0x70, ++ 0x1E, 0x70, 0x68, 0x65, 0x75, 0x02, 0x6A, 0x75, 0x07, 0x90, 0x24, 0x6B, 0xF0, 0x54, 0xE0, 0x34, ++ 0x90, 0xF0, 0x04, 0x44, 0xFF, 0xE0, 0x44, 0x07, 0x07, 0x54, 0x13, 0xC4, 0x00, 0x03, 0xE0, 0x20, ++ 0x02, 0x12, 0xF1, 0x80, 0x20, 0x64, 0x75, 0x42, 0x22, 0xE2, 0x65, 0x75, 0x12, 0x60, 0x66, 0xE5, ++ 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x00, 0x79, 0x20, 0x64, 0x75, 0xF4, 0x75, 0x6F, 0x65, 0x75, ++ 0x63, 0xE5, 0x01, 0x67, 0x04, 0x70, 0x65, 0x65, 0x64, 0x65, 0x62, 0xE5, 0x64, 0x85, 0x09, 0x60, ++ 0x63, 0x65, 0x85, 0x62, 0xAA, 0x01, 0x67, 0x75, 0x12, 0x63, 0xA9, 0x62, 0xF5, 0xE4, 0x27, 0x03, ++ 0x67, 0xE5, 0x22, 0x67, 0xFF, 0x7B, 0x0F, 0x60, 0x0C, 0x79, 0x20, 0x7A, 0xE5, 0xF4, 0x03, 0x12, ++ 0xF5, 0xDF, 0x54, 0x20, 0x30, 0x20, 0xE5, 0x20, 0x39, 0x41, 0x02, 0xE0, 0xC3, 0xEF, 0x20, 0xAF, ++ 0x04, 0xE0, 0x30, 0x13, 0x32, 0x80, 0xFF, 0xE4, 0xC4, 0xEF, 0x20, 0xAF, 0xE0, 0x30, 0x0F, 0x54, ++ 0x12, 0x06, 0x90, 0x32, 0x54, 0x13, 0xC4, 0xE0, 0x07, 0xBF, 0xFF, 0x07, 0x44, 0x21, 0xE5, 0x1B, ++ 0x74, 0x21, 0xF5, 0x10, 0x70, 0x69, 0x65, 0x15, 0x65, 0x00, 0x74, 0x04, 0x41, 0x02, 0x60, 0x68, ++ 0x02, 0x60, 0x75, 0x54, 0x22, 0xA1, 0x61, 0x75, 0x55, 0x51, 0x01, 0x7F, 0x75, 0x02, 0x60, 0x75, ++ 0x90, 0x22, 0x51, 0x61, 0xFE, 0xE0, 0x02, 0x06, 0x05, 0x78, 0xE0, 0xA3, 0xCE, 0x13, 0xC3, 0xCE, ++ 0x30, 0xF9, 0xD8, 0x13, 0x06, 0x90, 0x0A, 0xE0, 0x54, 0xC4, 0xE0, 0x00, 0x0C, 0xE0, 0x20, 0x0F, ++ 0xE0, 0x00, 0x06, 0x90, 0x30, 0x0F, 0x54, 0xC4, 0x40, 0x41, 0x02, 0xE0, 0xE0, 0x00, 0x06, 0x90, ++ 0x30, 0x0F, 0x54, 0xC4, 0x18, 0x41, 0x02, 0xE0, 0xE0, 0xA3, 0xFE, 0xE0, 0xC3, 0xCE, 0x06, 0x78, ++ 0xD8, 0x13, 0xCE, 0x13, 0x25, 0x01, 0x54, 0xF9, 0x06, 0x90, 0xFD, 0xE0, 0x13, 0xC4, 0xE0, 0x00, ++ 0xF9, 0x4D, 0x01, 0x54, 0x31, 0x06, 0x90, 0xFD, 0x6D, 0x03, 0x54, 0xE0, 0x60, 0xE4, 0x01, 0x70, ++ 0x35, 0x06, 0x90, 0x07, 0xF0, 0x02, 0x44, 0xE0, 0x54, 0xE9, 0x01, 0xAF, 0x06, 0x90, 0xFF, 0x03, ++ 0xA3, 0xFC, 0xE0, 0x30, 0xFD, 0xFC, 0x54, 0xE0, 0x4F, 0xED, 0xFE, 0xEC, 0x30, 0x06, 0x90, 0xFF, ++ 0xEF, 0xA3, 0xF0, 0xEE, 0x00, 0x06, 0x90, 0xF0, 0x54, 0x00, 0x7C, 0xE0, 0x06, 0x90, 0xFD, 0x01, ++ 0xA3, 0xFE, 0xE0, 0x30, 0xCE, 0x03, 0x78, 0xE0, 0x13, 0xCE, 0x13, 0xC3, 0x01, 0x54, 0xF9, 0xD8, ++ 0xEC, 0x01, 0x70, 0x6D, 0x06, 0x90, 0x07, 0x60, 0x04, 0x44, 0xE0, 0x35, 0x00, 0x06, 0x90, 0xF0, ++ 0xFE, 0x01, 0x54, 0xE0, 0x05, 0x78, 0xE4, 0xA3, 0xCE, 0x13, 0xC3, 0xCE, 0xFF, 0xF9, 0xD8, 0x13, ++ 0xE0, 0x30, 0x06, 0x90, 0x54, 0xE0, 0xA3, 0xFC, 0x4E, 0xEC, 0xFD, 0xF7, 0xFF, 0x4F, 0xED, 0xFE, ++ 0xEE, 0x30, 0x06, 0x90, 0xF0, 0xEF, 0xA3, 0xF0, 0xE0, 0x31, 0x06, 0x90, 0x0E, 0x60, 0x03, 0x54, ++ 0x7F, 0x16, 0x70, 0x14, 0x75, 0x55, 0x51, 0x01, 0x61, 0x75, 0x02, 0x60, 0x01, 0x7F, 0x22, 0x83, ++ 0x60, 0x75, 0x55, 0x51, 0x6F, 0x61, 0x75, 0x02, 0x20, 0x64, 0x75, 0x22, 0x22, 0x6F, 0x65, 0x75, ++ 0xE0, 0x00, 0x06, 0x90, 0x30, 0x0F, 0x54, 0xC4, 0xFF, 0xE4, 0x0A, 0xE0, 0x60, 0x75, 0x55, 0x51, ++ 0x97, 0x61, 0x75, 0x02, 0x7B, 0x24, 0x8F, 0x22, 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x02, 0x6D, ++ 0x54, 0xEF, 0x72, 0xAF, 0x7B, 0x72, 0xF5, 0xFE, 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x14, ++ 0x30, 0x06, 0x90, 0xE4, 0x90, 0xF0, 0xA3, 0xF0, 0x54, 0xE0, 0x09, 0x06, 0x60, 0x01, 0x64, 0x1F, ++ 0x90, 0xE6, 0x61, 0x02, 0x54, 0xE0, 0x0B, 0x06, 0x60, 0x01, 0x64, 0x1F, 0x90, 0xE6, 0x61, 0x02, ++ 0xFE, 0xE0, 0x0A, 0x06, 0x90, 0xFF, 0xE0, 0xA3, 0x5E, 0xE0, 0x08, 0x06, 0xA3, 0xF6, 0x90, 0x78, ++ 0xF6, 0x08, 0x5F, 0xE0, 0xE0, 0x30, 0xE6, 0x18, 0x31, 0x06, 0x90, 0x0A, 0x44, 0xFC, 0x54, 0xE0, ++ 0x78, 0x27, 0x80, 0x01, 0x13, 0xC4, 0xE6, 0x91, 0x01, 0x54, 0x13, 0x13, 0x90, 0x0A, 0xE0, 0x30, ++ 0x54, 0xE0, 0x31, 0x06, 0x80, 0x01, 0x44, 0xFC, 0xE6, 0x91, 0x78, 0x28, 0x54, 0x13, 0x13, 0xC4, ++ 0x0D, 0xE0, 0x30, 0x03, 0xE0, 0x31, 0x06, 0x90, 0xE0, 0xF0, 0xFC, 0x54, 0x80, 0xF0, 0x08, 0x44, ++ 0xE6, 0x91, 0x78, 0x1E, 0x07, 0x54, 0x13, 0xC4, 0x90, 0x0D, 0xE0, 0x30, 0x54, 0xE0, 0x31, 0x06, ++ 0x54, 0xE0, 0xF0, 0xFC, 0x07, 0x80, 0xF0, 0xF7, 0x44, 0xEF, 0x72, 0xAF, 0x90, 0x72, 0xF5, 0x01, ++ 0xC3, 0xE0, 0xA9, 0x01, 0x17, 0xE0, 0x30, 0x13, 0xE0, 0xAB, 0x01, 0x90, 0xE0, 0x30, 0x13, 0xC3, ++ 0x31, 0x06, 0x90, 0x0E, 0xFF, 0x03, 0x54, 0xE0, 0xE0, 0x04, 0x01, 0xBF, 0x78, 0xF0, 0x04, 0x44, ++ 0x13, 0xFF, 0xE6, 0x90, 0x30, 0x3F, 0x54, 0x13, 0x06, 0x90, 0x09, 0xE0, 0x30, 0x44, 0xE0, 0x31, ++ 0x78, 0x37, 0x80, 0xF0, 0x13, 0xFF, 0xE6, 0x90, 0x1F, 0x54, 0x13, 0x13, 0x90, 0x24, 0xE0, 0x30, ++ 0x30, 0xE0, 0x08, 0x06, 0x06, 0x90, 0x0B, 0xE2, 0xCF, 0x54, 0xE0, 0x31, 0x80, 0xF0, 0x20, 0x44, ++ 0x0A, 0x06, 0x90, 0x19, 0x31, 0x06, 0x90, 0xE0, 0xE0, 0x0B, 0xE2, 0x30, 0x10, 0x44, 0xCF, 0x54, ++ 0x90, 0x07, 0x80, 0xF0, 0x54, 0xE0, 0x31, 0x06, 0x06, 0x90, 0xF0, 0xCF, 0x20, 0x44, 0xE0, 0x03, ++ 0x34, 0x06, 0x90, 0xF0, 0xF0, 0x04, 0x44, 0xE0, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x1B, 0x79, ++ 0x8A, 0x78, 0xE4, 0xF4, 0x31, 0x06, 0x90, 0xF6, 0xFF, 0x03, 0x54, 0xE0, 0xC3, 0xE6, 0x8A, 0x78, ++ 0x7B, 0x0E, 0x50, 0x9F, 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x23, 0x80, 0x06, 0x8A, 0x78, ++ 0x31, 0x06, 0x90, 0xE4, 0x13, 0x13, 0xFF, 0xE0, 0x7B, 0x1F, 0x54, 0x13, 0x06, 0xE0, 0x30, 0xFF, ++ 0x25, 0x79, 0x20, 0x7A, 0x20, 0x7A, 0x04, 0x80, 0x03, 0x12, 0x29, 0x79, 0x31, 0x06, 0x90, 0xF4, ++ 0x13, 0x13, 0xFF, 0xE0, 0xE0, 0x30, 0x3F, 0x54, 0x7A, 0xFF, 0x7B, 0x09, 0x12, 0x2D, 0x79, 0x20, ++ 0xFF, 0x7B, 0xF4, 0x03, 0x32, 0x79, 0x20, 0x7A, 0xE0, 0x31, 0x06, 0x90, 0x03, 0x54, 0xC4, 0xFF, ++ 0x02, 0x00, 0x7C, 0xFD, 0x72, 0xAF, 0x40, 0x0D, 0xF5, 0x01, 0x44, 0xEF, 0xFF, 0x7B, 0x22, 0x72, ++ 0x3A, 0x79, 0x20, 0x7A, 0x78, 0xF4, 0x03, 0x12, 0x78, 0x07, 0x76, 0x8B, 0xFA, 0x24, 0xE6, 0x94, ++ 0x60, 0x14, 0x07, 0x60, 0x70, 0x06, 0x24, 0x08, 0x76, 0x94, 0x78, 0x20, 0xE6, 0x8D, 0x78, 0x07, ++ 0x54, 0x13, 0xC4, 0xFF, 0x14, 0xE0, 0x30, 0x07, 0xFE, 0x07, 0x54, 0xE6, 0x0A, 0x64, 0xE6, 0x08, ++ 0x78, 0x09, 0x70, 0x4E, 0x80, 0x05, 0x76, 0x94, 0x06, 0x94, 0x78, 0x03, 0x24, 0xE6, 0x94, 0x78, ++ 0x24, 0x35, 0x60, 0xFA, 0x78, 0x3F, 0x70, 0x05, 0x08, 0xFF, 0xE6, 0x8D, 0x0A, 0x06, 0x90, 0xE6, ++ 0xEF, 0xA3, 0xF0, 0xCF, 0x54, 0xE6, 0x18, 0xF0, 0xFF, 0x13, 0xC3, 0x20, 0xE0, 0x03, 0x06, 0x90, ++ 0xF0, 0x4F, 0xEF, 0x54, 0xE0, 0x0A, 0x06, 0x90, 0x54, 0xC4, 0x80, 0x54, 0x06, 0x90, 0xFF, 0x0F, ++ 0xF7, 0x54, 0xE0, 0x0D, 0x0E, 0x80, 0xF0, 0x4F, 0xFF, 0xE6, 0x8D, 0x78, 0x01, 0x90, 0xE6, 0x08, ++ 0xA3, 0xF0, 0xCF, 0xAA, 0x94, 0x78, 0xF0, 0xEF, 0x60, 0x01, 0x64, 0xE6, 0xE6, 0x8D, 0x78, 0x0E, ++ 0x90, 0xE6, 0x08, 0xFF, 0xF0, 0xCF, 0x10, 0x06, 0x90, 0xF0, 0xEF, 0xA3, 0x44, 0xE0, 0x34, 0x06, ++ 0xFF, 0x7B, 0xF0, 0x20, 0x42, 0x79, 0x20, 0x7A, 0xFD, 0xE6, 0x94, 0x78, 0x0D, 0x12, 0x00, 0x7C, ++ 0x0D, 0x06, 0x90, 0x40, 0xF0, 0x02, 0x44, 0xE0, 0x54, 0xE6, 0x8D, 0x78, 0x33, 0x33, 0x33, 0x08, ++ 0xAE, 0xFF, 0xF8, 0x54, 0xBF, 0x54, 0xEE, 0x72, 0xAF, 0x72, 0xF5, 0x4F, 0x13, 0xC4, 0xEF, 0x72, ++ 0x01, 0x54, 0x13, 0x13, 0xE0, 0x20, 0x00, 0x7F, 0xEF, 0x01, 0x7F, 0x02, 0x33, 0xC4, 0x01, 0x54, ++ 0x80, 0x54, 0x33, 0x33, 0xEE, 0x72, 0xAE, 0xFF, 0xF5, 0x4F, 0x7F, 0x54, 0xE6, 0x93, 0x78, 0x72, ++ 0x90, 0x07, 0x01, 0xB4, 0x54, 0xE0, 0x08, 0x06, 0x7B, 0x22, 0xF0, 0xDF, 0x79, 0x20, 0x7A, 0xFF, ++ 0xF4, 0x03, 0x12, 0x4E, 0xF6, 0x8A, 0x78, 0xE4, 0x08, 0xF6, 0x8D, 0x78, 0xE6, 0x93, 0x78, 0xF6, ++ 0x32, 0x60, 0xFA, 0x24, 0x14, 0x4A, 0x60, 0x14, 0x07, 0x24, 0x47, 0x60, 0x01, 0x90, 0x40, 0x70, ++ 0xC3, 0xFF, 0xE0, 0xA9, 0x06, 0xE0, 0x30, 0x13, 0x05, 0x76, 0x93, 0x78, 0x06, 0x90, 0x33, 0x80, ++ 0xC4, 0xFF, 0xE0, 0x08, 0x54, 0x13, 0x13, 0x13, 0x20, 0x93, 0x78, 0x01, 0x08, 0x76, 0x04, 0xE0, ++ 0x07, 0x76, 0x1F, 0x80, 0x06, 0x90, 0x1B, 0x80, 0xC4, 0xFF, 0xE0, 0x08, 0x54, 0x13, 0x13, 0x13, ++ 0x20, 0x93, 0x78, 0x01, 0x08, 0x76, 0x04, 0xE0, 0x07, 0x76, 0x07, 0x80, 0x93, 0x78, 0x03, 0x80, ++ 0xE6, 0x93, 0x78, 0x06, 0x25, 0x60, 0xFA, 0x24, 0x10, 0x60, 0xFE, 0x24, 0x37, 0x70, 0x03, 0x24, ++ 0x0A, 0x76, 0x91, 0x78, 0xE6, 0xF6, 0x18, 0xE4, 0x0A, 0x80, 0x80, 0x44, 0x01, 0x76, 0x91, 0x78, ++ 0xE6, 0xF6, 0x18, 0xE4, 0xE6, 0xF6, 0x7F, 0x54, 0x80, 0xF6, 0x20, 0x44, 0xA8, 0x01, 0x90, 0x1A, ++ 0xE0, 0xA3, 0xFE, 0xE0, 0x06, 0xA6, 0x90, 0x78, 0x06, 0x90, 0xF6, 0x08, 0x80, 0x54, 0xE0, 0x08, ++ 0x54, 0xE6, 0x18, 0xFF, 0x7B, 0xF6, 0x4F, 0x7F, 0x79, 0x20, 0x7A, 0xFF, 0xE6, 0x93, 0x78, 0x58, ++ 0x02, 0x00, 0x7C, 0xFD, 0xFF, 0x7B, 0x40, 0x0D, 0x64, 0x79, 0x20, 0x7A, 0xE4, 0xF4, 0x03, 0x12, ++ 0x78, 0xF6, 0x8A, 0x78, 0x76, 0x08, 0xF6, 0x80, 0x2A, 0x76, 0x08, 0x9B, 0x78, 0xC8, 0x76, 0x08, ++ 0xF6, 0x08, 0xF6, 0x8D, 0x02, 0x76, 0x84, 0x78, 0x78, 0x6C, 0x76, 0x08, 0x08, 0x01, 0x76, 0x93, ++ 0x08, 0x06, 0x90, 0xF6, 0xE0, 0xA3, 0xFF, 0xE0, 0x76, 0xAD, 0x75, 0xAC, 0x83, 0x8C, 0x82, 0x8D, ++ 0xEF, 0xA3, 0xF0, 0xCF, 0xAF, 0x75, 0xAE, 0xF0, 0x8E, 0x82, 0x8F, 0x76, 0xC0, 0x83, 0xC0, 0x83, ++ 0x90, 0xFF, 0xE0, 0x82, 0xC3, 0xE0, 0xA9, 0x01, 0xFE, 0x01, 0x54, 0x13, 0x13, 0x13, 0xC4, 0xEF, ++ 0xFD, 0x01, 0x54, 0x13, 0xFF, 0x7F, 0x54, 0xEF, 0x01, 0x54, 0x4E, 0xED, 0x33, 0x33, 0x33, 0xC4, ++ 0xD0, 0x4F, 0x80, 0x54, 0xF0, 0x83, 0xD0, 0x82, 0x76, 0xAF, 0x75, 0xAE, 0x83, 0x8E, 0x82, 0x8F, ++ 0xC4, 0x08, 0x54, 0xE0, 0xAE, 0xFF, 0xF0, 0x54, 0x7F, 0x54, 0xEE, 0x72, 0xE4, 0x72, 0xF5, 0x4F, ++ 0xF0, 0x0A, 0x06, 0x90, 0x06, 0x90, 0xF0, 0xA3, 0xFE, 0x54, 0xE0, 0x0D, 0xF7, 0x54, 0xE0, 0xF0, ++ 0xFD, 0x54, 0xE0, 0xF0, 0x01, 0x90, 0xE4, 0xF0, 0xF0, 0xA3, 0xF0, 0xAA, 0xF0, 0x97, 0x07, 0x90, ++ 0x00, 0x00, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x6E, 0x69, 0x61, 0x4D, 0x6E, 0x49, 0x00, 0x0A, 0x00, 0x0A, 0x74, 0x69, 0x69, 0x74, 0x63, 0x41, ++ 0x00, 0x0A, 0x65, 0x76, 0x65, 0x52, 0x41, 0x09, 0x09, 0x00, 0x0A, 0x73, 0x20, 0x3E, 0x2D, 0x09, ++ 0x30, 0x00, 0x30, 0x31, 0x44, 0x46, 0x2D, 0x00, 0x44, 0x48, 0x2D, 0x00, 0x45, 0x45, 0x2F, 0x00, ++ 0x50, 0x2D, 0x00, 0x45, 0x64, 0x25, 0x3A, 0x53, 0x43, 0x09, 0x00, 0x0A, 0x4B, 0x43, 0x41, 0x2D, ++ 0x09, 0x09, 0x00, 0x0A, 0x53, 0x46, 0x58, 0x52, 0x64, 0x25, 0x3D, 0x4D, 0x4E, 0x09, 0x00, 0x0A, ++ 0x61, 0x57, 0x2D, 0x50, 0x00, 0x0A, 0x74, 0x69, 0x58, 0x54, 0x09, 0x09, 0x3D, 0x4D, 0x53, 0x46, ++ 0x00, 0x0A, 0x64, 0x25, 0x69, 0x62, 0x41, 0x09, 0x0A, 0x44, 0x2D, 0x6C, 0x7B, 0x00, 0x0A, 0x00, ++ 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x06, 0x75, 0x5B, 0x02, 0x12, 0x6F, 0x75, 0x20, 0x6E, ++ 0x70, 0xE5, 0x22, 0xB8, 0xFF, 0x7B, 0x12, 0x60, 0x00, 0x79, 0x20, 0x7A, 0x75, 0xF4, 0x03, 0x12, ++ 0x6F, 0x75, 0x20, 0x6E, 0x01, 0x71, 0x75, 0x6F, 0x6F, 0x65, 0x6D, 0xE5, 0x6C, 0xE5, 0x04, 0x70, ++ 0x09, 0x60, 0x6E, 0x65, 0x85, 0x6C, 0x6E, 0x85, 0x71, 0x75, 0x6D, 0x6F, 0xA9, 0x6C, 0xAA, 0x01, ++ 0x27, 0x03, 0x12, 0x6D, 0x22, 0x71, 0xF5, 0xE4, 0x0F, 0x60, 0x71, 0xE5, 0x20, 0x7A, 0xFF, 0x7B, ++ 0x03, 0x12, 0x0C, 0x79, 0x54, 0x21, 0xE5, 0xF4, 0xE5, 0x21, 0xF5, 0xDF, 0x02, 0xE0, 0x30, 0x21, ++ 0x21, 0xAF, 0x01, 0x41, 0x30, 0x13, 0xC3, 0xEF, 0xFF, 0xE4, 0x04, 0xE0, 0x21, 0xAF, 0x24, 0x80, ++ 0x0F, 0x54, 0xC4, 0xEF, 0x90, 0x24, 0xE0, 0x30, 0xC4, 0xE0, 0x12, 0x06, 0xFF, 0x07, 0x54, 0x13, ++ 0xE5, 0x0D, 0x07, 0xBF, 0xF5, 0xEF, 0x54, 0x21, 0x00, 0x6A, 0x75, 0x21, 0x22, 0x15, 0x6B, 0x75, ++ 0x1D, 0x51, 0x01, 0x7F, 0x75, 0x02, 0x6A, 0x75, 0x90, 0x22, 0x6A, 0x6B, 0xFE, 0xE0, 0x42, 0x06, ++ 0x05, 0x78, 0xE0, 0xA3, 0xCE, 0x13, 0xC3, 0xCE, 0x30, 0xF9, 0xD8, 0x13, 0x06, 0x90, 0x0A, 0xE0, ++ 0x54, 0xC4, 0xE0, 0x40, 0x0C, 0xE0, 0x20, 0x0F, 0xE0, 0x40, 0x06, 0x90, 0x30, 0x0F, 0x54, 0xC4, ++ 0x08, 0x41, 0x02, 0xE0, 0xE0, 0x40, 0x06, 0x90, 0x30, 0x0F, 0x54, 0xC4, 0xE0, 0x21, 0x02, 0xE0, ++ 0xE0, 0xA3, 0xFE, 0xE0, 0xC3, 0xCE, 0x06, 0x78, 0xD8, 0x13, 0xCE, 0x13, 0x25, 0x01, 0x54, 0xF9, ++ 0x06, 0x90, 0xFD, 0xE0, 0x13, 0xC4, 0xE0, 0x40, 0xF9, 0x4D, 0x01, 0x54, 0x71, 0x06, 0x90, 0xFD, ++ 0x6D, 0x03, 0x54, 0xE0, 0x60, 0xE4, 0x01, 0x70, 0x75, 0x06, 0x90, 0x07, 0xF0, 0x02, 0x44, 0xE0, ++ 0x54, 0xE9, 0x01, 0xAF, 0x06, 0x90, 0xFF, 0x03, 0xA3, 0xFC, 0xE0, 0x70, 0xFD, 0xFC, 0x54, 0xE0, ++ 0x4F, 0xED, 0xFE, 0xEC, 0x70, 0x06, 0x90, 0xFF, 0xEF, 0xA3, 0xF0, 0xEE, 0x40, 0x06, 0x90, 0xF0, ++ 0x54, 0x00, 0x7C, 0xE0, 0x06, 0x90, 0xFD, 0x01, 0xA3, 0xFE, 0xE0, 0x70, 0xCE, 0x03, 0x78, 0xE0, ++ 0x13, 0xCE, 0x13, 0xC3, 0x01, 0x54, 0xF9, 0xD8, 0xEC, 0x01, 0x70, 0x6D, 0x06, 0x90, 0x07, 0x60, ++ 0x04, 0x44, 0xE0, 0x75, 0x40, 0x06, 0x90, 0xF0, 0xFE, 0x01, 0x54, 0xE0, 0x05, 0x78, 0xE4, 0xA3, ++ 0xCE, 0x13, 0xC3, 0xCE, 0xFF, 0xF9, 0xD8, 0x13, 0xE0, 0x70, 0x06, 0x90, 0x54, 0xE0, 0xA3, 0xFC, ++ 0x4E, 0xEC, 0xFD, 0xF7, 0xFF, 0x4F, 0xED, 0xFE, 0xEE, 0x70, 0x06, 0x90, 0xF0, 0xEF, 0xA3, 0xF0, ++ 0xE0, 0x71, 0x06, 0x90, 0x0E, 0x60, 0x03, 0x54, 0x7F, 0x16, 0x70, 0x14, 0x75, 0x1D, 0x51, 0x01, ++ 0x6B, 0x75, 0x02, 0x6A, 0x01, 0x7F, 0x22, 0x8D, 0x6A, 0x75, 0x1D, 0x51, 0x79, 0x6B, 0x75, 0x02, ++ 0x20, 0x6E, 0x75, 0x22, 0x22, 0x6F, 0x6F, 0x75, 0xE0, 0x40, 0x06, 0x90, 0x30, 0x0F, 0x54, 0xC4, ++ 0xFF, 0xE4, 0x0A, 0xE0, 0x6A, 0x75, 0x1D, 0x51, 0x9C, 0x6B, 0x75, 0x02, 0x7B, 0x24, 0x8F, 0x22, ++ 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x02, 0x6D, 0x54, 0xEF, 0x79, 0xAF, 0x7B, 0x79, 0xF5, 0xFE, ++ 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x14, 0x70, 0x06, 0x90, 0xE4, 0x90, 0xF0, 0xA3, 0xF0, ++ 0x54, 0xE0, 0x49, 0x06, 0x60, 0x01, 0x64, 0x1F, 0x90, 0xAE, 0x61, 0x02, 0x54, 0xE0, 0x4B, 0x06, ++ 0x60, 0x01, 0x64, 0x1F, 0x90, 0xAE, 0x61, 0x02, 0xFE, 0xE0, 0x4A, 0x06, 0x90, 0xFF, 0xE0, 0xA3, ++ 0x5E, 0xE0, 0x48, 0x06, 0xA3, 0xF6, 0xA9, 0x78, 0xF6, 0x08, 0x5F, 0xE0, 0xE0, 0x30, 0xE6, 0x18, ++ 0x71, 0x06, 0x90, 0x0A, 0x44, 0xFC, 0x54, 0xE0, 0x78, 0x27, 0x80, 0x01, 0x13, 0xC4, 0xE6, 0xAA, ++ 0x01, 0x54, 0x13, 0x13, 0x90, 0x0A, 0xE0, 0x30, 0x54, 0xE0, 0x71, 0x06, 0x80, 0x01, 0x44, 0xFC, ++ 0xE6, 0xAA, 0x78, 0x28, 0x54, 0x13, 0x13, 0xC4, 0x0D, 0xE0, 0x30, 0x03, 0xE0, 0x71, 0x06, 0x90, ++ 0xE0, 0xF0, 0xFC, 0x54, 0x80, 0xF0, 0x08, 0x44, 0xE6, 0xAA, 0x78, 0x1E, 0x07, 0x54, 0x13, 0xC4, ++ 0x90, 0x0D, 0xE0, 0x30, 0x54, 0xE0, 0x71, 0x06, 0x54, 0xE0, 0xF0, 0xFC, 0x07, 0x80, 0xF0, 0xF7, ++ 0x44, 0xEF, 0x79, 0xAF, 0x90, 0x79, 0xF5, 0x01, 0xC3, 0xE0, 0xB9, 0x01, 0x17, 0xE0, 0x30, 0x13, ++ 0xE0, 0xBB, 0x01, 0x90, 0xE0, 0x30, 0x13, 0xC3, 0x71, 0x06, 0x90, 0x0E, 0xFF, 0x03, 0x54, 0xE0, ++ 0xE0, 0x04, 0x01, 0xBF, 0x78, 0xF0, 0x04, 0x44, 0x13, 0xFF, 0xE6, 0xA9, 0x30, 0x3F, 0x54, 0x13, ++ 0x06, 0x90, 0x09, 0xE0, 0x30, 0x44, 0xE0, 0x71, 0x78, 0x37, 0x80, 0xF0, 0x13, 0xFF, 0xE6, 0xA9, ++ 0x1F, 0x54, 0x13, 0x13, 0x90, 0x24, 0xE0, 0x30, 0x30, 0xE0, 0x48, 0x06, 0x06, 0x90, 0x0B, 0xE2, ++ 0xCF, 0x54, 0xE0, 0x71, 0x80, 0xF0, 0x20, 0x44, 0x4A, 0x06, 0x90, 0x19, 0x71, 0x06, 0x90, 0xE0, ++ 0xE0, 0x0B, 0xE2, 0x30, 0x10, 0x44, 0xCF, 0x54, 0x90, 0x07, 0x80, 0xF0, 0x54, 0xE0, 0x71, 0x06, ++ 0x06, 0x90, 0xF0, 0xCF, 0x20, 0x44, 0xE0, 0x43, 0x74, 0x06, 0x90, 0xF0, 0xF0, 0x04, 0x44, 0xE0, ++ 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x1B, 0x79, 0xA3, 0x78, 0xE4, 0xF4, 0x71, 0x06, 0x90, 0xF6, ++ 0xFF, 0x03, 0x54, 0xE0, 0xC3, 0xE6, 0xA3, 0x78, 0x7B, 0x0E, 0x50, 0x9F, 0x79, 0x20, 0x7A, 0xFF, ++ 0xF4, 0x03, 0x12, 0x23, 0x80, 0x06, 0xA3, 0x78, 0x71, 0x06, 0x90, 0xE4, 0x13, 0x13, 0xFF, 0xE0, ++ 0x7B, 0x1F, 0x54, 0x13, 0x06, 0xE0, 0x30, 0xFF, 0x25, 0x79, 0x20, 0x7A, 0x20, 0x7A, 0x04, 0x80, ++ 0x03, 0x12, 0x29, 0x79, 0x71, 0x06, 0x90, 0xF4, 0x13, 0x13, 0xFF, 0xE0, 0xE0, 0x30, 0x3F, 0x54, ++ 0x7A, 0xFF, 0x7B, 0x09, 0x12, 0x2D, 0x79, 0x20, 0xFF, 0x7B, 0xF4, 0x03, 0x32, 0x79, 0x20, 0x7A, ++ 0xE0, 0x71, 0x06, 0x90, 0x03, 0x54, 0xC4, 0xFF, 0x02, 0x00, 0x7C, 0xFD, 0x79, 0xAF, 0x40, 0x0D, ++ 0xF5, 0x01, 0x44, 0xEF, 0xFF, 0x7B, 0x22, 0x79, 0x3A, 0x79, 0x20, 0x7A, 0x78, 0xF4, 0x03, 0x12, ++ 0x78, 0x07, 0x76, 0xA4, 0xFA, 0x24, 0xE6, 0xAD, 0x60, 0x14, 0x07, 0x60, 0x70, 0x06, 0x24, 0x08, ++ 0x76, 0xAD, 0x78, 0x20, 0xE6, 0xA6, 0x78, 0x07, 0x54, 0x13, 0xC4, 0xFF, 0x14, 0xE0, 0x30, 0x07, ++ 0xFE, 0x07, 0x54, 0xE6, 0x0A, 0x64, 0xE6, 0x08, 0x78, 0x09, 0x70, 0x4E, 0x80, 0x05, 0x76, 0xAD, ++ 0x06, 0xAD, 0x78, 0x03, 0x24, 0xE6, 0xAD, 0x78, 0x24, 0x35, 0x60, 0xFA, 0x78, 0x3F, 0x70, 0x05, ++ 0x08, 0xFF, 0xE6, 0xA6, 0x4A, 0x06, 0x90, 0xE6, 0xEF, 0xA3, 0xF0, 0xCF, 0x54, 0xE6, 0x18, 0xF0, ++ 0xFF, 0x13, 0xC3, 0x20, 0xE0, 0x43, 0x06, 0x90, 0xF0, 0x4F, 0xEF, 0x54, 0xE0, 0x4A, 0x06, 0x90, ++ 0x54, 0xC4, 0x80, 0x54, 0x06, 0x90, 0xFF, 0x0F, 0xF7, 0x54, 0xE0, 0x4D, 0x0E, 0x80, 0xF0, 0x4F, ++ 0xFF, 0xE6, 0xA6, 0x78, 0x01, 0x90, 0xE6, 0x08, 0xA3, 0xF0, 0xCF, 0xBA, 0xAD, 0x78, 0xF0, 0xEF, ++ 0x60, 0x01, 0x64, 0xE6, 0xE6, 0xA6, 0x78, 0x0E, 0x90, 0xE6, 0x08, 0xFF, 0xF0, 0xCF, 0x50, 0x06, ++ 0x90, 0xF0, 0xEF, 0xA3, 0x44, 0xE0, 0x74, 0x06, 0xFF, 0x7B, 0xF0, 0x20, 0x42, 0x79, 0x20, 0x7A, ++ 0xFD, 0xE6, 0xAD, 0x78, 0x0D, 0x12, 0x00, 0x7C, 0x4D, 0x06, 0x90, 0x40, 0xF0, 0x02, 0x44, 0xE0, ++ 0x54, 0xE6, 0xA6, 0x78, 0x33, 0x33, 0x33, 0x08, 0xAE, 0xFF, 0xF8, 0x54, 0xBF, 0x54, 0xEE, 0x79, ++ 0xAF, 0x79, 0xF5, 0x4F, 0x13, 0xC4, 0xEF, 0x79, 0x01, 0x54, 0x13, 0x13, 0xE0, 0x20, 0x00, 0x7F, ++ 0xEF, 0x01, 0x7F, 0x02, 0x33, 0xC4, 0x01, 0x54, 0x80, 0x54, 0x33, 0x33, 0xEE, 0x79, 0xAE, 0xFF, ++ 0xF5, 0x4F, 0x7F, 0x54, 0xE6, 0xAC, 0x78, 0x79, 0x90, 0x07, 0x01, 0xB4, 0x54, 0xE0, 0x48, 0x06, ++ 0x7B, 0x22, 0xF0, 0xDF, 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x4E, 0xF6, 0xA3, 0x78, 0xE4, ++ 0x08, 0xF6, 0xA6, 0x78, 0xE6, 0xAC, 0x78, 0xF6, 0x32, 0x60, 0xFA, 0x24, 0x14, 0x4A, 0x60, 0x14, ++ 0x07, 0x24, 0x47, 0x60, 0x01, 0x90, 0x40, 0x70, 0xC3, 0xFF, 0xE0, 0xB9, 0x06, 0xE0, 0x30, 0x13, ++ 0x05, 0x76, 0xAC, 0x78, 0x06, 0x90, 0x33, 0x80, 0xC4, 0xFF, 0xE0, 0x48, 0x54, 0x13, 0x13, 0x13, ++ 0x20, 0xAC, 0x78, 0x01, 0x08, 0x76, 0x04, 0xE0, 0x07, 0x76, 0x1F, 0x80, 0x06, 0x90, 0x1B, 0x80, ++ 0xC4, 0xFF, 0xE0, 0x48, 0x54, 0x13, 0x13, 0x13, 0x20, 0xAC, 0x78, 0x01, 0x08, 0x76, 0x04, 0xE0, ++ 0x07, 0x76, 0x07, 0x80, 0xAC, 0x78, 0x03, 0x80, 0xE6, 0xAC, 0x78, 0x06, 0x25, 0x60, 0xFA, 0x24, ++ 0x10, 0x60, 0xFE, 0x24, 0x37, 0x70, 0x03, 0x24, 0x0A, 0x76, 0xAA, 0x78, 0xE6, 0xF6, 0x18, 0xE4, ++ 0x0A, 0x80, 0x80, 0x44, 0x01, 0x76, 0xAA, 0x78, 0xE6, 0xF6, 0x18, 0xE4, 0xE6, 0xF6, 0x7F, 0x54, ++ 0x80, 0xF6, 0x20, 0x44, 0xB8, 0x01, 0x90, 0x1A, 0xE0, 0xA3, 0xFE, 0xE0, 0x06, 0xA6, 0xA9, 0x78, ++ 0x06, 0x90, 0xF6, 0x08, 0x80, 0x54, 0xE0, 0x48, 0x54, 0xE6, 0x18, 0xFF, 0x7B, 0xF6, 0x4F, 0x7F, ++ 0x79, 0x20, 0x7A, 0xFF, 0xE6, 0xAC, 0x78, 0x58, 0x02, 0x00, 0x7C, 0xFD, 0xFF, 0x7B, 0x40, 0x0D, ++ 0x64, 0x79, 0x20, 0x7A, 0xE4, 0xF4, 0x03, 0x12, 0x78, 0xF6, 0xA3, 0x78, 0x76, 0x08, 0xF6, 0x99, ++ 0x2A, 0x76, 0x08, 0x9B, 0x78, 0xC8, 0x76, 0x08, 0xF6, 0x08, 0xF6, 0xA6, 0x02, 0x76, 0x9D, 0x78, ++ 0x78, 0x6C, 0x76, 0x08, 0x08, 0x01, 0x76, 0xAC, 0x48, 0x06, 0x90, 0xF6, 0xE0, 0xA3, 0xFF, 0xE0, ++ 0x7D, 0xAD, 0x7C, 0xAC, 0x83, 0x8C, 0x82, 0x8D, 0xEF, 0xA3, 0xF0, 0xCF, 0xAF, 0x7C, 0xAE, 0xF0, ++ 0x8E, 0x82, 0x8F, 0x7D, 0xC0, 0x83, 0xC0, 0x83, 0x90, 0xFF, 0xE0, 0x82, 0xC3, 0xE0, 0xB9, 0x01, ++ 0xFE, 0x01, 0x54, 0x13, 0x13, 0x13, 0xC4, 0xEF, 0xFD, 0x01, 0x54, 0x13, 0xFF, 0x7F, 0x54, 0xEF, ++ 0x01, 0x54, 0x4E, 0xED, 0x33, 0x33, 0x33, 0xC4, 0xD0, 0x4F, 0x80, 0x54, 0xF0, 0x83, 0xD0, 0x82, ++ 0x7D, 0xAF, 0x7C, 0xAE, 0x83, 0x8E, 0x82, 0x8F, 0xC4, 0x08, 0x54, 0xE0, 0xAE, 0xFF, 0xF0, 0x54, ++ 0x7F, 0x54, 0xEE, 0x79, 0xE4, 0x79, 0xF5, 0x4F, 0xF0, 0x4A, 0x06, 0x90, 0x06, 0x90, 0xF0, 0xA3, ++ 0xFE, 0x54, 0xE0, 0x4D, 0xF7, 0x54, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xF0, 0x01, 0x90, 0xE4, 0xF0, ++ 0xF0, 0xA3, 0xF0, 0xBA, 0xF0, 0xE0, 0x07, 0x90, 0x00, 0x00, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, ++ 0x69, 0x6E, 0x49, 0x09, 0x00, 0x0A, 0x30, 0x74, 0x00, 0xFF, 0x00, 0x01, 0xAC, 0x00, 0x00, 0x00, ++ 0x99, 0x01, 0xA2, 0x00, 0x00, 0x00, 0x55, 0x4C, 0x54, 0x09, 0x00, 0x00, 0x50, 0x74, 0x73, 0x65, ++ 0x09, 0x00, 0x0A, 0x44, 0x74, 0x65, 0x53, 0x09, 0x00, 0x0A, 0x70, 0x75, 0x44, 0x50, 0x09, 0x09, ++ 0x0A, 0x6E, 0x77, 0x6F, 0x4C, 0x09, 0x09, 0x00, 0x09, 0x00, 0x0A, 0x42, 0x4F, 0x43, 0x09, 0x09, ++ 0x64, 0x25, 0x3D, 0x4C, 0x45, 0x09, 0x00, 0x0A, 0x0A, 0x74, 0x69, 0x78, 0x4D, 0x09, 0x09, 0x00, ++ 0x3D, 0x4C, 0x4C, 0x44, 0x00, 0x0A, 0x64, 0x25, 0x03, 0x12, 0x32, 0x7F, 0x00, 0x06, 0x90, 0x68, ++ 0x13, 0xC4, 0xFF, 0xE0, 0x01, 0x54, 0x13, 0x13, 0xC2, 0x20, 0xE0, 0x30, 0x75, 0x10, 0xC2, 0xE8, ++ 0x02, 0x12, 0x03, 0x24, 0x20, 0xF5, 0xE4, 0x06, 0xF0, 0xC8, 0x01, 0x90, 0x02, 0x12, 0xF0, 0xA3, ++ 0x00, 0x06, 0x90, 0x01, 0xF0, 0x7F, 0x54, 0xE0, 0xD2, 0xF0, 0xE0, 0xA3, 0x90, 0xE3, 0x11, 0xE8, ++ 0x44, 0xE0, 0x62, 0x07, 0x44, 0xE0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x04, 0x54, 0xE0, 0xF0, 0x08, ++ 0x54, 0xE0, 0xF0, 0xFE, 0x54, 0xE0, 0xF0, 0xFB, 0x0D, 0x7E, 0xF0, 0xF7, 0xAE, 0x31, 0x00, 0x7F, ++ 0x20, 0x7F, 0x0D, 0x7E, 0x0D, 0x90, 0xAE, 0x31, 0xF0, 0x2B, 0x74, 0x08, 0x28, 0x0D, 0x90, 0xE0, ++ 0x40, 0x08, 0x90, 0xF0, 0xF0, 0x80, 0x44, 0xE0, 0xF0, 0xBF, 0x54, 0xE0, 0xA5, 0x08, 0x90, 0xE0, ++ 0x45, 0x08, 0x90, 0xF0, 0xE0, 0xF0, 0x7F, 0x74, 0xF0, 0xAA, 0x08, 0x90, 0x74, 0xFC, 0x07, 0x90, ++ 0x90, 0x22, 0xF0, 0x6A, 0x13, 0xE0, 0x8B, 0x0D, 0x30, 0x3F, 0x54, 0x13, 0x06, 0x90, 0x2B, 0xE0, ++ 0x13, 0xC3, 0xE0, 0x27, 0xD2, 0x11, 0xE0, 0x30, 0x31, 0x58, 0x7F, 0x10, 0xBE, 0x01, 0x90, 0x85, ++ 0x10, 0xC2, 0xF0, 0xEF, 0x3A, 0x80, 0x58, 0x7F, 0x78, 0x7F, 0x10, 0xD2, 0x01, 0x90, 0x85, 0x31, ++ 0xC2, 0xF0, 0xEF, 0xBE, 0x80, 0x78, 0x7F, 0x10, 0x27, 0x06, 0x90, 0x29, 0x30, 0x13, 0xC3, 0xE0, ++ 0x10, 0xD2, 0x11, 0xE0, 0x85, 0x31, 0x51, 0x7F, 0xEF, 0xBE, 0x01, 0x90, 0x7F, 0x10, 0xC2, 0xF0, ++ 0xD2, 0x0F, 0x80, 0x51, 0x31, 0x61, 0x7F, 0x10, 0xBE, 0x01, 0x90, 0x85, 0x10, 0xC2, 0xF0, 0xEF, ++ 0x85, 0x31, 0x61, 0x7F, 0xEF, 0xBF, 0x01, 0x90, 0xBE, 0x01, 0x90, 0xF0, 0xBC, 0x01, 0x90, 0xE0, ++ 0xBF, 0x01, 0x90, 0xF0, 0xBD, 0x01, 0x90, 0xE0, 0x7F, 0x10, 0xD2, 0xF0, 0x90, 0x85, 0x31, 0x70, ++ 0xF0, 0xEF, 0xC0, 0x01, 0x70, 0x7F, 0x10, 0xC2, 0x01, 0x90, 0x85, 0x31, 0x90, 0xF0, 0xEF, 0xC1, ++ 0xF4, 0xE0, 0xBF, 0x01, 0x01, 0x90, 0xF0, 0x04, 0x04, 0xF4, 0xE0, 0xBD, 0xC1, 0x01, 0x90, 0xF0, ++ 0xF0, 0x04, 0xF4, 0xE0, 0x26, 0x06, 0x90, 0x22, 0xFE, 0x0F, 0x54, 0xE0, 0x94, 0x80, 0x64, 0xD3, ++ 0x74, 0x04, 0x40, 0x87, 0xEE, 0xFE, 0x2E, 0xF0, 0x10, 0x30, 0xFF, 0x2F, 0xFF, 0x04, 0xF4, 0x03, ++ 0xE0, 0x26, 0x06, 0x90, 0x30, 0x0F, 0x54, 0xC4, 0x00, 0x7F, 0x03, 0xE0, 0xFD, 0xE4, 0x22, 0x22, ++ 0x09, 0x20, 0x90, 0xED, 0xEF, 0x0F, 0xFC, 0x93, 0x01, 0x70, 0x06, 0xAA, 0x82, 0xF5, 0x14, 0x0E, ++ 0xF0, 0xEC, 0x83, 0x8A, 0xE8, 0x11, 0xBD, 0x0D, 0x7A, 0xFF, 0x7B, 0x22, 0x12, 0x00, 0x79, 0x20, ++ 0xF5, 0xE4, 0xF4, 0x03, 0x82, 0x78, 0x22, 0x20, 0x08, 0x90, 0x05, 0x76, 0xF0, 0x03, 0x74, 0x1F, ++ 0xF0, 0x21, 0x08, 0x90, 0x74, 0x22, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x01, 0xF0, 0x0F, 0x74, 0x21, ++ 0x74, 0x23, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x04, 0x74, 0xF0, 0x14, 0x27, 0x08, 0x90, 0xF0, 0x07, ++ 0xF0, 0x04, 0x74, 0x28, 0x14, 0x29, 0x08, 0x90, 0x2A, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x05, 0x74, ++ 0x01, 0x74, 0x29, 0x08, 0x24, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x17, 0x74, 0x15, 0x74, 0x25, 0x08, ++ 0x2B, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x04, 0x74, 0x40, 0x74, 0x2D, 0x08, 0x26, 0x08, 0x90, 0xF0, ++ 0x90, 0xF0, 0x03, 0x74, 0x01, 0x74, 0x1F, 0x08, 0x21, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x0D, 0x74, ++ 0x05, 0x74, 0x27, 0x08, 0x08, 0x90, 0xE4, 0xF0, 0xFF, 0x7B, 0xF0, 0x2B, 0x7F, 0xFD, 0x7F, 0x7A, ++ 0x7B, 0xC9, 0x51, 0x01, 0xE4, 0xEC, 0x7A, 0x00, 0xC9, 0x51, 0xFF, 0xFD, 0x75, 0xE6, 0x90, 0x78, ++ 0xFF, 0xA4, 0x08, 0xF0, 0x9F, 0xE0, 0x74, 0xC3, 0x95, 0xFF, 0x74, 0xFD, 0x75, 0xE6, 0xFC, 0xF0, ++ 0xFF, 0xA4, 0x04, 0xF0, 0xFB, 0x9F, 0xED, 0xC3, 0xFA, 0xF0, 0x95, 0xEC, 0x02, 0x7F, 0xFD, 0xE4, ++ 0x00, 0x7B, 0xC9, 0x51, 0x02, 0x7D, 0x40, 0x7A, 0xC9, 0x51, 0xFF, 0xE4, 0xE0, 0x24, 0x08, 0x90, ++ 0x90, 0xF0, 0xFE, 0x54, 0x44, 0xE0, 0x40, 0x08, 0x44, 0xE0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x04, ++ 0x08, 0x90, 0xF0, 0x10, 0xF0, 0x54, 0xE0, 0x44, 0x90, 0xF0, 0x04, 0x44, 0x54, 0xE0, 0x43, 0x08, ++ 0xF0, 0x06, 0x44, 0xF8, 0xF0, 0x08, 0x44, 0xE0, 0xE0, 0x42, 0x08, 0x90, 0x01, 0x44, 0xFC, 0x54, ++ 0x40, 0x08, 0x90, 0xF0, 0xF0, 0xFB, 0x54, 0xE0, 0x0F, 0x54, 0xEF, 0x22, 0xED, 0xFF, 0x10, 0x44, ++ 0x60, 0x54, 0x33, 0xC4, 0x2E, 0x08, 0x90, 0x4F, 0x90, 0xFF, 0xEA, 0xF0, 0xF0, 0xEF, 0x2F, 0x08, ++ 0xEB, 0x30, 0x08, 0x90, 0x08, 0x90, 0xE4, 0xF0, 0xE4, 0x22, 0xF0, 0x2E, 0xF0, 0x01, 0x0D, 0x90, ++ 0x74, 0x00, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x78, 0x0D, 0x90, 0xF0, 0x20, 0xF0, 0xAA, 0x74, 0x82, ++ 0x74, 0x02, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x30, 0x0D, 0x90, 0xF0, 0x22, 0xF0, 0x20, 0x74, 0x05, ++ 0xF0, 0x25, 0x0D, 0x90, 0x74, 0x06, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x9C, 0x0D, 0x90, 0xF0, 0x26, ++ 0xF0, 0x89, 0x74, 0x0A, 0xF0, 0x2A, 0x0D, 0x90, 0x21, 0x0D, 0x90, 0xE4, 0xF0, 0x07, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0x74, 0xF5, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x01, ++ 0xF8, 0x54, 0xE0, 0xF9, 0xE4, 0xF0, 0x01, 0x44, 0xF0, 0xC4, 0x08, 0x90, 0xF0, 0xC3, 0x08, 0x90, ++ 0xF0, 0xC2, 0x08, 0x90, 0x04, 0xC5, 0x08, 0x90, 0xBA, 0x08, 0x90, 0xF0, 0x14, 0xF0, 0x03, 0x74, ++ 0xC1, 0x08, 0x90, 0xF0, 0x01, 0x74, 0xF0, 0x04, 0x55, 0x08, 0x90, 0xF0, 0x74, 0xF0, 0x03, 0x74, ++ 0x08, 0x90, 0xF0, 0x01, 0xF0, 0x03, 0x74, 0x56, 0xF0, 0x57, 0x08, 0x90, 0x74, 0x58, 0x08, 0x90, ++ 0x08, 0x90, 0xF0, 0xC8, 0xF0, 0x03, 0x74, 0x5C, 0xE4, 0xF0, 0x01, 0x74, 0xF0, 0x5F, 0x08, 0x90, ++ 0xF0, 0x5E, 0x08, 0x90, 0xF0, 0x5D, 0x08, 0x90, 0x04, 0x60, 0x08, 0x90, 0xFF, 0x07, 0x90, 0xF0, ++ 0xF0, 0xFD, 0x54, 0xE0, 0x74, 0xFE, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x03, 0x00, 0x00, 0xF0, 0xFD, ++ 0x90, 0x00, 0x00, 0x00, 0xF0, 0x14, 0xFE, 0x07, 0xF0, 0xFD, 0x07, 0x90, 0xF0, 0x33, 0x08, 0x90, ++ 0x04, 0x3A, 0x08, 0x90, 0x3B, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x05, 0x74, 0x90, 0xF0, 0x3C, 0x08, ++ 0x0B, 0x74, 0x3D, 0x08, 0xF0, 0x09, 0x74, 0xF0, 0x74, 0x38, 0x08, 0x90, 0x01, 0x74, 0xF0, 0x03, ++ 0x37, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x05, 0x74, 0x03, 0x74, 0x36, 0x08, 0xF0, 0x01, 0x74, 0xF0, ++ 0xF0, 0x75, 0x07, 0x90, 0xE0, 0x30, 0x06, 0x90, 0x78, 0xE0, 0xA3, 0xFE, 0x13, 0xC3, 0xCE, 0x03, ++ 0xF9, 0xD8, 0x13, 0xCE, 0x33, 0x33, 0x01, 0x54, 0x44, 0x08, 0x54, 0x33, 0x76, 0x07, 0x90, 0x01, ++ 0xA1, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x15, 0x74, 0xE4, 0xF0, 0xA2, 0x07, 0xA6, 0x07, 0x90, 0xF0, ++ 0x90, 0xF0, 0x30, 0x74, 0x01, 0x74, 0x8F, 0x07, 0x8E, 0x07, 0x90, 0xF0, 0x90, 0x07, 0x90, 0xF0, ++ 0x90, 0xF0, 0x03, 0x74, 0xE4, 0xF0, 0x91, 0x07, 0xF0, 0x8F, 0x07, 0x90, 0x04, 0x93, 0x07, 0x90, ++ 0x92, 0x07, 0x90, 0xF0, 0x94, 0x07, 0x90, 0xF0, 0x95, 0x07, 0x90, 0xF0, 0xE4, 0xF0, 0x03, 0x74, ++ 0xF0, 0x93, 0x07, 0x90, 0x74, 0x0F, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x03, 0xFE, 0x54, 0xE0, 0x0E, ++ 0xFD, 0x54, 0xE0, 0xF0, 0x90, 0xFF, 0xE4, 0xF0, 0x64, 0xE0, 0x0F, 0x08, 0xEF, 0x0A, 0x60, 0x03, ++ 0x50, 0xFF, 0x94, 0xC3, 0x80, 0x0F, 0x00, 0x04, 0x7A, 0xFF, 0x7B, 0xEE, 0xEF, 0x4D, 0x79, 0x20, ++ 0x12, 0x00, 0x7C, 0xFD, 0x08, 0x90, 0x40, 0x0D, 0xF0, 0x43, 0x74, 0x16, 0xF0, 0x18, 0x08, 0x90, ++ 0xF0, 0x1A, 0x08, 0x90, 0xF0, 0x1C, 0x08, 0x90, 0x74, 0x01, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x03, ++ 0x08, 0x90, 0xF0, 0x02, 0x08, 0x90, 0xF0, 0x03, 0xFF, 0xE4, 0xF0, 0x04, 0x80, 0xBF, 0x0F, 0x00, ++ 0x16, 0x08, 0x90, 0xFB, 0x90, 0xF0, 0x42, 0x74, 0x90, 0xF0, 0x18, 0x08, 0x90, 0xF0, 0x1A, 0x08, ++ 0x90, 0xF0, 0x1C, 0x08, 0x04, 0x74, 0x01, 0x08, 0x02, 0x08, 0x90, 0xF0, 0x03, 0x08, 0x90, 0xF0, ++ 0x04, 0x08, 0x90, 0xF0, 0x0E, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, ++ 0x74, 0x1E, 0x08, 0x90, 0x07, 0x90, 0xF0, 0x12, 0xF0, 0x0D, 0x74, 0xF3, 0xE0, 0x07, 0x07, 0x90, ++ 0xE0, 0xF0, 0x10, 0x44, 0x22, 0xF0, 0xEF, 0x54, 0x12, 0x60, 0x66, 0xE5, 0x20, 0x7A, 0xFF, 0x7B, ++ 0x03, 0x12, 0x1A, 0x79, 0x25, 0x64, 0x75, 0xF4, 0x75, 0x39, 0x65, 0x75, 0x20, 0xE5, 0x01, 0x67, ++ 0x75, 0x06, 0xE0, 0x30, 0x65, 0x75, 0x26, 0x64, 0x65, 0x63, 0xE5, 0xAA, 0xE5, 0x04, 0x70, 0x65, ++ 0x60, 0x64, 0x65, 0x62, 0x62, 0x64, 0x85, 0x09, 0x75, 0x63, 0x65, 0x85, 0x62, 0xAA, 0x01, 0x67, ++ 0x03, 0x12, 0x63, 0xA9, 0x67, 0xF5, 0xE4, 0x27, 0x60, 0x67, 0xE5, 0x22, 0x7A, 0xFF, 0x7B, 0x09, ++ 0x12, 0x23, 0x79, 0x20, 0x06, 0x90, 0xF4, 0x03, 0x13, 0xC4, 0xE0, 0x00, 0x20, 0x03, 0x54, 0x13, ++ 0x13, 0xE0, 0x13, 0xE0, 0x20, 0x3F, 0x54, 0x13, 0xE0, 0xA3, 0x0B, 0xE0, 0x13, 0x13, 0x13, 0xC4, ++ 0xE0, 0x30, 0x01, 0x54, 0xC8, 0x01, 0x90, 0x0E, 0xF0, 0x20, 0x44, 0xE0, 0x75, 0x25, 0x64, 0x75, ++ 0x75, 0x22, 0xAD, 0x65, 0x65, 0x75, 0x25, 0x64, 0x67, 0xE5, 0x22, 0x7A, 0xFF, 0x7B, 0x20, 0x60, ++ 0x2C, 0x79, 0x20, 0x7A, 0x90, 0xF4, 0x03, 0x12, 0x44, 0xE0, 0xC8, 0x01, 0x0C, 0x7F, 0xF0, 0x01, ++ 0x90, 0x68, 0x03, 0x12, 0x54, 0xE0, 0xF0, 0x07, 0x54, 0xE0, 0xF0, 0xFE, 0x20, 0xAF, 0xF0, 0xFD, ++ 0x20, 0x13, 0xC3, 0xEF, 0x64, 0x75, 0x06, 0xE0, 0xAA, 0x65, 0x75, 0x26, 0x70, 0x67, 0xE5, 0x22, ++ 0x7B, 0x43, 0xC1, 0x02, 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x35, 0xE0, 0x00, 0x06, 0x90, ++ 0x78, 0xE0, 0xA3, 0xFE, 0x13, 0xC3, 0xCE, 0x06, 0xF9, 0xD8, 0x13, 0xCE, 0xE0, 0x25, 0x01, 0x54, ++ 0x90, 0x33, 0xE4, 0xFD, 0xC4, 0xE0, 0x00, 0x06, 0xFF, 0x01, 0x54, 0x13, 0x03, 0x54, 0x4F, 0xED, ++ 0x30, 0x06, 0x90, 0xFF, 0xE0, 0xA3, 0xFC, 0xE0, 0xEC, 0xFD, 0xFC, 0x54, 0xFF, 0x4F, 0xED, 0xFE, ++ 0xEE, 0x30, 0x06, 0x90, 0xF0, 0xEF, 0xA3, 0xF0, 0xE0, 0x75, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, ++ 0x54, 0xE0, 0x31, 0x06, 0x07, 0x90, 0xFF, 0x03, 0xF8, 0x54, 0xE0, 0x76, 0x07, 0x90, 0xF0, 0x4F, ++ 0xF0, 0x01, 0x74, 0x8E, 0xF0, 0x8F, 0x07, 0x90, 0x04, 0x90, 0x07, 0x90, 0x07, 0x90, 0xE4, 0xF0, ++ 0x07, 0x90, 0xF0, 0x8F, 0x90, 0xF0, 0x04, 0x92, 0x90, 0xF0, 0x93, 0x07, 0xF0, 0x04, 0x94, 0x07, ++ 0x93, 0x07, 0x90, 0xE4, 0x79, 0x07, 0x90, 0xF0, 0xF0, 0x03, 0x44, 0xE0, 0xE0, 0x03, 0x06, 0x90, ++ 0x90, 0xF0, 0x04, 0x44, 0x54, 0xE0, 0x7A, 0x07, 0x06, 0x90, 0xFF, 0x01, 0xC4, 0xFE, 0xE0, 0x01, ++ 0x54, 0x13, 0x13, 0x13, 0x1E, 0x60, 0x6F, 0x01, 0x20, 0x7A, 0xFF, 0x7B, 0x0D, 0x12, 0x3B, 0x79, ++ 0x01, 0x06, 0x90, 0x35, 0xC4, 0x80, 0x54, 0xE0, 0x54, 0x13, 0x13, 0x13, 0x07, 0x90, 0xFF, 0x01, ++ 0xFE, 0x54, 0xE0, 0x7A, 0x06, 0x90, 0xF0, 0x4F, 0x13, 0xC4, 0xE0, 0x00, 0x20, 0x03, 0x54, 0x13, ++ 0x13, 0xE0, 0x27, 0xE0, 0x20, 0x3F, 0x54, 0x13, 0xE0, 0xA3, 0x1F, 0xE0, 0x13, 0x13, 0x13, 0xC4, ++ 0xE0, 0x20, 0x01, 0x54, 0x79, 0x07, 0x90, 0x14, 0xF0, 0xFC, 0x54, 0xE0, 0xE0, 0x03, 0x06, 0x90, ++ 0x75, 0xF0, 0xFB, 0x54, 0x65, 0x75, 0x26, 0x64, 0xFF, 0x7B, 0x22, 0xAA, 0x46, 0x79, 0x20, 0x7A, ++ 0xE4, 0xF4, 0x03, 0x12, 0xF0, 0xC8, 0x01, 0x90, 0x60, 0x75, 0xF0, 0xA3, 0x0B, 0x61, 0x75, 0x02, ++ 0x00, 0x00, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x69, 0x6E, 0x49, 0x09, 0x00, 0x0A, 0x31, 0x74, 0x00, 0xFF, 0x00, 0x01, 0xAC, 0x00, 0x00, 0x00, ++ 0x99, 0x01, 0xA2, 0x00, 0x00, 0x00, 0x55, 0x4C, 0x54, 0x09, 0x00, 0x00, 0x50, 0x74, 0x73, 0x65, ++ 0x09, 0x00, 0x0A, 0x44, 0x74, 0x65, 0x53, 0x09, 0x00, 0x0A, 0x70, 0x75, 0x44, 0x50, 0x09, 0x09, ++ 0x0A, 0x6E, 0x77, 0x6F, 0x4C, 0x09, 0x09, 0x00, 0x09, 0x00, 0x0A, 0x42, 0x4F, 0x43, 0x09, 0x09, ++ 0x64, 0x25, 0x3D, 0x4C, 0x45, 0x09, 0x00, 0x0A, 0x0A, 0x74, 0x69, 0x78, 0x4D, 0x09, 0x09, 0x00, ++ 0x3D, 0x4C, 0x4C, 0x44, 0x00, 0x0A, 0x64, 0x25, 0x00, 0x12, 0x32, 0x7F, 0x40, 0x06, 0x90, 0x68, ++ 0x13, 0xC4, 0xFF, 0xE0, 0x01, 0x54, 0x13, 0x13, 0xC2, 0x20, 0xE0, 0x30, 0x75, 0x10, 0xD2, 0xE8, ++ 0x02, 0x12, 0x03, 0x24, 0x21, 0xF5, 0xE4, 0x06, 0xF0, 0xCA, 0x01, 0x90, 0x02, 0x12, 0xF0, 0xA3, ++ 0x40, 0x06, 0x90, 0x01, 0xF0, 0x7F, 0x54, 0xE0, 0xD2, 0xF0, 0xE0, 0xA3, 0x90, 0xE3, 0x11, 0xE8, ++ 0x44, 0xE0, 0x62, 0x07, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0x10, 0x54, 0xE0, 0xF0, 0x20, ++ 0x54, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xF0, 0xEF, 0x0D, 0x7E, 0xF0, 0xDF, 0xAE, 0x31, 0x40, 0x7F, ++ 0x60, 0x7F, 0x0D, 0x7E, 0x0D, 0x90, 0xAE, 0x31, 0xF0, 0x2B, 0x74, 0x48, 0x68, 0x0D, 0x90, 0xE0, ++ 0x6F, 0x09, 0x90, 0xF0, 0xF0, 0x80, 0x44, 0xE0, 0xF0, 0xBF, 0x54, 0xE0, 0x0A, 0x09, 0x90, 0xE0, ++ 0x74, 0x09, 0x90, 0xF0, 0xE0, 0xF0, 0x7F, 0x74, 0xF0, 0x0F, 0x09, 0x90, 0x74, 0xFC, 0x07, 0x90, ++ 0x90, 0x22, 0xF0, 0x6A, 0x13, 0xE0, 0x8B, 0x0D, 0x30, 0x3F, 0x54, 0x13, 0x06, 0x90, 0x2B, 0xE0, ++ 0x13, 0xC3, 0xE0, 0x67, 0xD2, 0x11, 0xE0, 0x30, 0x31, 0x58, 0x7F, 0x10, 0xC4, 0x01, 0x90, 0x85, ++ 0x10, 0xC2, 0xF0, 0xEF, 0x3A, 0x80, 0x58, 0x7F, 0x78, 0x7F, 0x10, 0xD2, 0x01, 0x90, 0x85, 0x31, ++ 0xC2, 0xF0, 0xEF, 0xC4, 0x80, 0x78, 0x7F, 0x10, 0x67, 0x06, 0x90, 0x29, 0x30, 0x13, 0xC3, 0xE0, ++ 0x10, 0xD2, 0x11, 0xE0, 0x85, 0x31, 0x51, 0x7F, 0xEF, 0xC4, 0x01, 0x90, 0x7F, 0x10, 0xC2, 0xF0, ++ 0xD2, 0x0F, 0x80, 0x51, 0x31, 0x61, 0x7F, 0x10, 0xC4, 0x01, 0x90, 0x85, 0x10, 0xC2, 0xF0, 0xEF, ++ 0x85, 0x31, 0x61, 0x7F, 0xEF, 0xC5, 0x01, 0x90, 0xC4, 0x01, 0x90, 0xF0, 0xC2, 0x01, 0x90, 0xE0, ++ 0xC5, 0x01, 0x90, 0xF0, 0xC3, 0x01, 0x90, 0xE0, 0x7F, 0x10, 0xD2, 0xF0, 0x90, 0x85, 0x31, 0x70, ++ 0xF0, 0xEF, 0xC6, 0x01, 0x70, 0x7F, 0x10, 0xC2, 0x01, 0x90, 0x85, 0x31, 0x90, 0xF0, 0xEF, 0xC7, ++ 0xF4, 0xE0, 0xC5, 0x01, 0x01, 0x90, 0xF0, 0x04, 0x04, 0xF4, 0xE0, 0xC3, 0xC7, 0x01, 0x90, 0xF0, ++ 0xF0, 0x04, 0xF4, 0xE0, 0x66, 0x06, 0x90, 0x22, 0xFE, 0x0F, 0x54, 0xE0, 0x94, 0x80, 0x64, 0xD3, ++ 0x74, 0x04, 0x40, 0x87, 0xEE, 0xFE, 0x2E, 0xF0, 0x10, 0x30, 0xFF, 0x2F, 0xFF, 0x04, 0xF4, 0x03, ++ 0xE0, 0x66, 0x06, 0x90, 0x30, 0x0F, 0x54, 0xC4, 0x00, 0x7F, 0x03, 0xE0, 0xFD, 0xE4, 0x22, 0x22, ++ 0x09, 0x20, 0x90, 0xED, 0xEF, 0x0F, 0xFC, 0x93, 0x01, 0x70, 0x06, 0xAA, 0x82, 0xF5, 0x14, 0x0E, ++ 0xF0, 0xEC, 0x83, 0x8A, 0xE8, 0x11, 0xBD, 0x0D, 0x7A, 0xFF, 0x7B, 0x22, 0x12, 0x00, 0x79, 0x20, ++ 0xF5, 0xE4, 0xF4, 0x03, 0x9B, 0x78, 0x22, 0x21, 0x09, 0x90, 0x05, 0x76, 0xF0, 0x03, 0x74, 0x4E, ++ 0xF0, 0x50, 0x09, 0x90, 0x74, 0x51, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x01, 0xF0, 0x0F, 0x74, 0x50, ++ 0x74, 0x52, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x04, 0x74, 0xF0, 0x14, 0x56, 0x09, 0x90, 0xF0, 0x07, ++ 0xF0, 0x04, 0x74, 0x57, 0x14, 0x58, 0x09, 0x90, 0x59, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x05, 0x74, ++ 0x01, 0x74, 0x58, 0x09, 0x53, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x17, 0x74, 0x15, 0x74, 0x54, 0x09, ++ 0x5A, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x04, 0x74, 0x40, 0x74, 0x5C, 0x09, 0x55, 0x09, 0x90, 0xF0, ++ 0x90, 0xF0, 0x03, 0x74, 0x01, 0x74, 0x4E, 0x09, 0x50, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x0D, 0x74, ++ 0x05, 0x74, 0x56, 0x09, 0x09, 0x90, 0xE4, 0xF0, 0xFF, 0x7B, 0xF0, 0x5A, 0x7F, 0xFD, 0x7F, 0x7A, ++ 0x7B, 0xC9, 0x51, 0x01, 0xE4, 0xEC, 0x7A, 0x00, 0xC9, 0x51, 0xFF, 0xFD, 0x75, 0xE6, 0xA9, 0x78, ++ 0xFF, 0xA4, 0x08, 0xF0, 0x9F, 0xE0, 0x74, 0xC3, 0x95, 0xFF, 0x74, 0xFD, 0x75, 0xE6, 0xFC, 0xF0, ++ 0xFF, 0xA4, 0x04, 0xF0, 0xFB, 0x9F, 0xED, 0xC3, 0xFA, 0xF0, 0x95, 0xEC, 0x02, 0x7F, 0xFD, 0xE4, ++ 0x00, 0x7B, 0xC9, 0x51, 0x02, 0x7D, 0x40, 0x7A, 0xC9, 0x51, 0xFF, 0xE4, 0xE0, 0x53, 0x09, 0x90, ++ 0x90, 0xF0, 0xFE, 0x54, 0x44, 0xE0, 0x6F, 0x09, 0x44, 0xE0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x04, ++ 0x09, 0x90, 0xF0, 0x10, 0xF0, 0x54, 0xE0, 0x73, 0x90, 0xF0, 0x04, 0x44, 0x54, 0xE0, 0x72, 0x09, ++ 0xF0, 0x06, 0x44, 0xF8, 0xF0, 0x08, 0x44, 0xE0, 0xE0, 0x71, 0x09, 0x90, 0x01, 0x44, 0xFC, 0x54, ++ 0x6F, 0x09, 0x90, 0xF0, 0xF0, 0xFB, 0x54, 0xE0, 0x0F, 0x54, 0xEF, 0x22, 0xED, 0xFF, 0x10, 0x44, ++ 0x60, 0x54, 0x33, 0xC4, 0x5D, 0x09, 0x90, 0x4F, 0x90, 0xFF, 0xEA, 0xF0, 0xF0, 0xEF, 0x5E, 0x09, ++ 0xEB, 0x5F, 0x09, 0x90, 0x09, 0x90, 0xE4, 0xF0, 0xE4, 0x22, 0xF0, 0x5D, 0xF0, 0x41, 0x0D, 0x90, ++ 0x74, 0x40, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x78, 0x0D, 0x90, 0xF0, 0x60, 0xF0, 0xAA, 0x74, 0x82, ++ 0x74, 0x42, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x30, 0x0D, 0x90, 0xF0, 0x62, 0xF0, 0x20, 0x74, 0x45, ++ 0xF0, 0x65, 0x0D, 0x90, 0x74, 0x46, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x9C, 0x0D, 0x90, 0xF0, 0x66, ++ 0xF0, 0x89, 0x74, 0x4A, 0xF0, 0x6A, 0x0D, 0x90, 0x61, 0x0D, 0x90, 0xE4, 0xF0, 0x07, 0x90, 0xF0, ++ 0xF0, 0xFB, 0x54, 0xE0, 0xF0, 0x08, 0x44, 0xE0, 0x74, 0xF5, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x01, ++ 0x8F, 0x54, 0xE0, 0xFA, 0xE4, 0xF0, 0x20, 0x44, 0xF0, 0x29, 0x09, 0x90, 0xF0, 0x28, 0x09, 0x90, ++ 0xF0, 0x27, 0x09, 0x90, 0x04, 0x2A, 0x09, 0x90, 0x1F, 0x09, 0x90, 0xF0, 0x14, 0xF0, 0x03, 0x74, ++ 0x26, 0x09, 0x90, 0xF0, 0x01, 0x74, 0xF0, 0x04, 0x84, 0x09, 0x90, 0xF0, 0x74, 0xF0, 0x03, 0x74, ++ 0x09, 0x90, 0xF0, 0x01, 0xF0, 0x03, 0x74, 0x85, 0xF0, 0x86, 0x09, 0x90, 0x74, 0x87, 0x09, 0x90, ++ 0x09, 0x90, 0xF0, 0xC8, 0xF0, 0x03, 0x74, 0x8B, 0xE4, 0xF0, 0x01, 0x74, 0xF0, 0x8E, 0x09, 0x90, ++ 0xF0, 0x8D, 0x09, 0x90, 0xF0, 0x8C, 0x09, 0x90, 0x04, 0x8F, 0x09, 0x90, 0x2E, 0x09, 0x90, 0xF0, ++ 0xF0, 0xFD, 0x54, 0xE0, 0x74, 0x2D, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x03, 0x00, 0x00, 0xF0, 0x2C, ++ 0x90, 0x00, 0x00, 0x00, 0xF0, 0x14, 0x2D, 0x09, 0xF0, 0x2C, 0x09, 0x90, 0xF0, 0x62, 0x09, 0x90, ++ 0x04, 0x69, 0x09, 0x90, 0x6A, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x05, 0x74, 0x90, 0xF0, 0x6B, 0x09, ++ 0x0B, 0x74, 0x6C, 0x09, 0xF0, 0x09, 0x74, 0xF0, 0x74, 0x67, 0x09, 0x90, 0x01, 0x74, 0xF0, 0x03, ++ 0x66, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x05, 0x74, 0x03, 0x74, 0x65, 0x09, 0xF0, 0x01, 0x74, 0xF0, ++ 0xF0, 0xBE, 0x07, 0x90, 0xE0, 0x70, 0x06, 0x90, 0x78, 0xE0, 0xA3, 0xFE, 0x13, 0xC3, 0xCE, 0x03, ++ 0xF9, 0xD8, 0x13, 0xCE, 0x33, 0x33, 0x01, 0x54, 0x44, 0x08, 0x54, 0x33, 0xBF, 0x07, 0x90, 0x01, ++ 0xEA, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x15, 0x74, 0xE4, 0xF0, 0xEB, 0x07, 0xEF, 0x07, 0x90, 0xF0, ++ 0x90, 0xF0, 0x30, 0x74, 0x01, 0x74, 0xD8, 0x07, 0xD7, 0x07, 0x90, 0xF0, 0xD9, 0x07, 0x90, 0xF0, ++ 0x90, 0xF0, 0x03, 0x74, 0xE4, 0xF0, 0xDA, 0x07, 0xF0, 0xD8, 0x07, 0x90, 0x04, 0xDC, 0x07, 0x90, ++ 0xDB, 0x07, 0x90, 0xF0, 0xDD, 0x07, 0x90, 0xF0, 0xDE, 0x07, 0x90, 0xF0, 0xE4, 0xF0, 0x03, 0x74, ++ 0xF0, 0xDC, 0x07, 0x90, 0x74, 0x3E, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x03, 0xFE, 0x54, 0xE0, 0x3D, ++ 0xFD, 0x54, 0xE0, 0xF0, 0x90, 0xFF, 0xE4, 0xF0, 0x64, 0xE0, 0x3E, 0x09, 0xEF, 0x0A, 0x60, 0x03, ++ 0x50, 0xFF, 0x94, 0xC3, 0x80, 0x0F, 0x00, 0x04, 0x7A, 0xFF, 0x7B, 0xEE, 0xEF, 0x4D, 0x79, 0x20, ++ 0x12, 0x00, 0x7C, 0xFD, 0x09, 0x90, 0x40, 0x0D, 0xF0, 0x43, 0x74, 0x45, 0xF0, 0x47, 0x09, 0x90, ++ 0xF0, 0x49, 0x09, 0x90, 0xF0, 0x4B, 0x09, 0x90, 0x74, 0x30, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x03, ++ 0x09, 0x90, 0xF0, 0x31, 0x09, 0x90, 0xF0, 0x32, 0xFF, 0xE4, 0xF0, 0x33, 0x80, 0xBF, 0x0F, 0x00, ++ 0x45, 0x09, 0x90, 0xFB, 0x90, 0xF0, 0x42, 0x74, 0x90, 0xF0, 0x47, 0x09, 0x90, 0xF0, 0x49, 0x09, ++ 0x90, 0xF0, 0x4B, 0x09, 0x04, 0x74, 0x30, 0x09, 0x31, 0x09, 0x90, 0xF0, 0x32, 0x09, 0x90, 0xF0, ++ 0x33, 0x09, 0x90, 0xF0, 0x3D, 0x09, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, ++ 0x74, 0x4D, 0x09, 0x90, 0x07, 0x90, 0xF0, 0x12, 0xF0, 0x0D, 0x74, 0xF3, 0xE0, 0x07, 0x07, 0x90, ++ 0xE0, 0xF0, 0x10, 0x44, 0x22, 0xF0, 0xEF, 0x54, 0x12, 0x60, 0x70, 0xE5, 0x20, 0x7A, 0xFF, 0x7B, ++ 0x03, 0x12, 0x1A, 0x79, 0x25, 0x6E, 0x75, 0xF4, 0x75, 0x39, 0x6F, 0x75, 0x21, 0xE5, 0x01, 0x71, ++ 0x75, 0x06, 0xE0, 0x30, 0x6F, 0x75, 0x26, 0x6E, 0x65, 0x6D, 0xE5, 0xAA, 0xE5, 0x04, 0x70, 0x6F, ++ 0x60, 0x6E, 0x65, 0x6C, 0x6C, 0x6E, 0x85, 0x09, 0x75, 0x6D, 0x6F, 0x85, 0x6C, 0xAA, 0x01, 0x71, ++ 0x03, 0x12, 0x6D, 0xA9, 0x71, 0xF5, 0xE4, 0x27, 0x60, 0x71, 0xE5, 0x22, 0x7A, 0xFF, 0x7B, 0x09, ++ 0x12, 0x23, 0x79, 0x20, 0x06, 0x90, 0xF4, 0x03, 0x13, 0xC4, 0xE0, 0x40, 0x20, 0x03, 0x54, 0x13, ++ 0x13, 0xE0, 0x13, 0xE0, 0x20, 0x3F, 0x54, 0x13, 0xE0, 0xA3, 0x0B, 0xE0, 0x13, 0x13, 0x13, 0xC4, ++ 0xE0, 0x30, 0x01, 0x54, 0xCA, 0x01, 0x90, 0x0E, 0xF0, 0x20, 0x44, 0xE0, 0x75, 0x25, 0x6E, 0x75, ++ 0x75, 0x22, 0xAD, 0x6F, 0x6F, 0x75, 0x25, 0x6E, 0x71, 0xE5, 0x22, 0x7A, 0xFF, 0x7B, 0x20, 0x60, ++ 0x2C, 0x79, 0x20, 0x7A, 0x90, 0xF4, 0x03, 0x12, 0x44, 0xE0, 0xCA, 0x01, 0x0C, 0x7F, 0xF0, 0x01, ++ 0x90, 0x68, 0x00, 0x12, 0x54, 0xE0, 0xF0, 0x07, 0x54, 0xE0, 0xF0, 0xFB, 0x21, 0xAF, 0xF0, 0xF7, ++ 0x20, 0x13, 0xC3, 0xEF, 0x6E, 0x75, 0x06, 0xE0, 0xAA, 0x6F, 0x75, 0x26, 0x70, 0x71, 0xE5, 0x22, ++ 0x7B, 0x43, 0xC1, 0x02, 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x35, 0xE0, 0x40, 0x06, 0x90, ++ 0x78, 0xE0, 0xA3, 0xFE, 0x13, 0xC3, 0xCE, 0x06, 0xF9, 0xD8, 0x13, 0xCE, 0xE0, 0x25, 0x01, 0x54, ++ 0x90, 0x33, 0xE4, 0xFD, 0xC4, 0xE0, 0x40, 0x06, 0xFF, 0x01, 0x54, 0x13, 0x03, 0x54, 0x4F, 0xED, ++ 0x70, 0x06, 0x90, 0xFF, 0xE0, 0xA3, 0xFC, 0xE0, 0xEC, 0xFD, 0xFC, 0x54, 0xFF, 0x4F, 0xED, 0xFE, ++ 0xEE, 0x70, 0x06, 0x90, 0xF0, 0xEF, 0xA3, 0xF0, 0xE0, 0xBE, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, ++ 0x54, 0xE0, 0x71, 0x06, 0x07, 0x90, 0xFF, 0x03, 0xF8, 0x54, 0xE0, 0xBF, 0x07, 0x90, 0xF0, 0x4F, ++ 0xF0, 0x01, 0x74, 0xD7, 0xF0, 0xD8, 0x07, 0x90, 0x04, 0xD9, 0x07, 0x90, 0x07, 0x90, 0xE4, 0xF0, ++ 0x07, 0x90, 0xF0, 0xD8, 0x90, 0xF0, 0x04, 0xDB, 0x90, 0xF0, 0xDC, 0x07, 0xF0, 0x04, 0xDD, 0x07, ++ 0xDC, 0x07, 0x90, 0xE4, 0xC2, 0x07, 0x90, 0xF0, 0xF0, 0x03, 0x44, 0xE0, 0xE0, 0x43, 0x06, 0x90, ++ 0x90, 0xF0, 0x04, 0x44, 0x54, 0xE0, 0xC3, 0x07, 0x06, 0x90, 0xFF, 0x01, 0xC4, 0xFE, 0xE0, 0x41, ++ 0x54, 0x13, 0x13, 0x13, 0x1E, 0x60, 0x6F, 0x01, 0x20, 0x7A, 0xFF, 0x7B, 0x0D, 0x12, 0x3B, 0x79, ++ 0x41, 0x06, 0x90, 0x35, 0xC4, 0x80, 0x54, 0xE0, 0x54, 0x13, 0x13, 0x13, 0x07, 0x90, 0xFF, 0x01, ++ 0xFE, 0x54, 0xE0, 0xC3, 0x06, 0x90, 0xF0, 0x4F, 0x13, 0xC4, 0xE0, 0x40, 0x20, 0x03, 0x54, 0x13, ++ 0x13, 0xE0, 0x27, 0xE0, 0x20, 0x3F, 0x54, 0x13, 0xE0, 0xA3, 0x1F, 0xE0, 0x13, 0x13, 0x13, 0xC4, ++ 0xE0, 0x20, 0x01, 0x54, 0xC2, 0x07, 0x90, 0x14, 0xF0, 0xFC, 0x54, 0xE0, 0xE0, 0x43, 0x06, 0x90, ++ 0x75, 0xF0, 0xFB, 0x54, 0x6F, 0x75, 0x26, 0x6E, 0xFF, 0x7B, 0x22, 0xAA, 0x46, 0x79, 0x20, 0x7A, ++ 0xE4, 0xF4, 0x03, 0x12, 0xF0, 0xCA, 0x01, 0x90, 0x6A, 0x75, 0xF0, 0xA3, 0x24, 0x6B, 0x75, 0x02, ++ 0x00, 0x00, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x42, 0x30, 0x31, 0x09, 0x09, 0x00, 0x0A, 0x54, 0x75, 0x74, 0x65, 0x53, 0x09, 0x00, 0x0A, 0x70, ++ 0x6B, 0x6E, 0x69, 0x4C, 0x0A, 0x70, 0x55, 0x2D, 0x4C, 0x09, 0x09, 0x00, 0x2D, 0x6B, 0x6E, 0x69, ++ 0x73, 0x73, 0x6F, 0x4C, 0x4C, 0x09, 0x00, 0x0A, 0x2D, 0x6B, 0x6E, 0x69, 0x6E, 0x77, 0x6F, 0x44, ++ 0x09, 0x09, 0x00, 0x0A, 0x00, 0x49, 0x44, 0x4D, 0x00, 0x0A, 0x00, 0x58, 0x69, 0x78, 0x45, 0x09, ++ 0xE5, 0x00, 0x0A, 0x74, 0x7B, 0x12, 0x60, 0x66, 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x00, ++ 0x75, 0x20, 0x64, 0x75, 0x67, 0x75, 0xBE, 0x65, 0x12, 0x10, 0xC2, 0x01, 0x1E, 0x50, 0x5D, 0x0E, ++ 0x8F, 0x7F, 0x26, 0x7E, 0x70, 0x63, 0x65, 0xEF, 0x62, 0x65, 0xEE, 0x03, 0xA4, 0x74, 0x10, 0x60, ++ 0x04, 0x70, 0x63, 0x65, 0x62, 0x65, 0x26, 0x74, 0x64, 0x8E, 0x04, 0x60, 0x63, 0xE5, 0x65, 0x8F, ++ 0x04, 0x70, 0x65, 0x65, 0x64, 0x65, 0x62, 0xE5, 0x64, 0x85, 0x09, 0x60, 0x63, 0x65, 0x85, 0x62, ++ 0xAA, 0x01, 0x67, 0x75, 0x12, 0x63, 0xA9, 0x62, 0xF5, 0xE4, 0x27, 0x03, 0xE6, 0x87, 0x78, 0x67, ++ 0xC3, 0xFF, 0x01, 0x54, 0x08, 0x74, 0x9F, 0xE4, 0x05, 0x54, 0x00, 0x94, 0xC3, 0xE6, 0x18, 0xFC, ++ 0xE6, 0x08, 0xFE, 0x13, 0x6C, 0xEE, 0xFF, 0x13, 0x08, 0xEF, 0xF6, 0x18, 0xFF, 0x7B, 0x22, 0xF6, ++ 0x07, 0x79, 0x20, 0x7A, 0x51, 0xF4, 0x03, 0x12, 0x12, 0x05, 0x7F, 0xDE, 0x06, 0x90, 0x68, 0x03, ++ 0x90, 0x04, 0x31, 0x23, 0xFF, 0xE0, 0x8A, 0x0D, 0xE0, 0x8B, 0x0D, 0x90, 0x07, 0x90, 0xFF, 0x6F, ++ 0xE4, 0xFD, 0xE0, 0x0B, 0xEF, 0xF6, 0x86, 0x78, 0xE4, 0xF6, 0x08, 0x6D, 0x08, 0xF6, 0x80, 0x78, ++ 0x22, 0x76, 0x08, 0xF6, 0x90, 0x2E, 0x76, 0x08, 0x0D, 0x74, 0xF3, 0x07, 0x21, 0x64, 0x75, 0xF0, ++ 0x22, 0xE8, 0x65, 0x75, 0x13, 0x13, 0xFF, 0xE0, 0x92, 0x13, 0x3F, 0x54, 0x27, 0x06, 0x90, 0x10, ++ 0x03, 0xE0, 0x30, 0xE0, 0x90, 0x1A, 0x10, 0x30, 0x20, 0xE0, 0x27, 0x06, 0x06, 0x90, 0x63, 0xE0, ++ 0xA3, 0xFE, 0xE0, 0x26, 0xCE, 0x02, 0x78, 0xE0, 0x13, 0xCE, 0x13, 0xC3, 0xE0, 0x20, 0xF9, 0xD8, ++ 0x90, 0x10, 0xC2, 0x50, 0x0F, 0x74, 0x01, 0x0D, 0x21, 0x0D, 0x90, 0xF0, 0x0D, 0x90, 0xF0, 0x04, ++ 0x9F, 0x54, 0xE0, 0x00, 0x20, 0x0D, 0x90, 0xF0, 0x44, 0x9F, 0x54, 0xE0, 0x0D, 0x90, 0xF0, 0x20, ++ 0x13, 0x13, 0xE0, 0x8B, 0x22, 0x24, 0x01, 0x54, 0xF0, 0x0C, 0x0D, 0x90, 0x74, 0x2C, 0x0D, 0x90, ++ 0x07, 0x90, 0xF0, 0x12, 0xFC, 0x54, 0xE0, 0xF1, 0xF3, 0x54, 0xE0, 0xF0, 0x90, 0xF0, 0x04, 0x44, ++ 0x54, 0xE0, 0xF2, 0x07, 0xF0, 0x01, 0x44, 0xFC, 0xF0, 0xF3, 0x54, 0xE0, 0x80, 0xBE, 0x01, 0x90, ++ 0x90, 0x10, 0xD2, 0x4E, 0x0F, 0x74, 0x21, 0x0D, 0x01, 0x0D, 0x90, 0xF0, 0x0D, 0x90, 0xF0, 0x04, ++ 0x9F, 0x54, 0xE0, 0x00, 0x90, 0xF0, 0x20, 0x44, 0x54, 0xE0, 0x20, 0x0D, 0x0D, 0x90, 0xF0, 0x9F, ++ 0xF0, 0x12, 0x74, 0x0C, 0xE0, 0x8B, 0x0D, 0x90, 0x01, 0x54, 0x13, 0x13, 0x0D, 0x90, 0x22, 0x24, ++ 0x07, 0x90, 0xF0, 0x2C, 0xFC, 0x54, 0xE0, 0xF1, 0xE0, 0xF0, 0x01, 0x44, 0x90, 0xF0, 0xF3, 0x54, ++ 0x54, 0xE0, 0xF2, 0x07, 0x54, 0xE0, 0xF0, 0xFC, 0xF0, 0x04, 0x44, 0xF3, 0xE0, 0xBF, 0x01, 0x90, ++ 0xF0, 0x3E, 0x08, 0x90, 0x33, 0xE4, 0x10, 0xA2, 0xE0, 0x25, 0x01, 0x54, 0x90, 0xFF, 0xE0, 0x25, ++ 0x54, 0xE0, 0x23, 0x06, 0x22, 0xF0, 0x4F, 0xFB, 0x25, 0x60, 0x67, 0xE5, 0x20, 0x7A, 0xFF, 0x7B, ++ 0x03, 0x12, 0x26, 0x79, 0x76, 0x84, 0x78, 0xF4, 0xD4, 0x76, 0x08, 0x30, 0xE0, 0x8F, 0x07, 0x90, ++ 0x90, 0xF0, 0x01, 0x44, 0x44, 0xE0, 0x93, 0x07, 0x07, 0x90, 0xF0, 0x01, 0x02, 0x44, 0xE0, 0x8B, ++ 0x00, 0x06, 0x90, 0xF0, 0x0F, 0x54, 0xC4, 0xE0, 0xD3, 0x1B, 0xE0, 0x30, 0x94, 0xE6, 0x83, 0x78, ++ 0x94, 0xE6, 0x18, 0x00, 0x08, 0x09, 0x40, 0x00, 0x70, 0x18, 0x16, 0xE6, 0x06, 0x80, 0x16, 0x01, ++ 0x75, 0x26, 0x64, 0x75, 0x07, 0x90, 0x8F, 0x65, 0x07, 0x54, 0xE0, 0xA0, 0x09, 0x60, 0x01, 0x64, ++ 0xE0, 0x8B, 0x07, 0x90, 0xE0, 0x30, 0x13, 0xC3, 0x25, 0x64, 0x75, 0x06, 0x90, 0x5D, 0x65, 0x75, ++ 0xC4, 0xE0, 0x00, 0x06, 0xE0, 0x30, 0x0F, 0x54, 0x23, 0x06, 0x90, 0x05, 0x06, 0x90, 0x07, 0x80, ++ 0xE0, 0x20, 0xE0, 0x27, 0x78, 0x04, 0x31, 0x0A, 0x08, 0x30, 0x76, 0x84, 0xD3, 0x22, 0xD4, 0x76, ++ 0x94, 0xE6, 0x85, 0x78, 0x94, 0xE6, 0x18, 0x00, 0x08, 0x08, 0x40, 0x00, 0x70, 0x18, 0x16, 0xE6, ++ 0x78, 0x22, 0x16, 0x01, 0x08, 0x30, 0x76, 0x84, 0x07, 0x90, 0xD4, 0x76, 0x07, 0x54, 0xE0, 0xA0, ++ 0x87, 0x78, 0x4B, 0x70, 0xFF, 0x01, 0x54, 0xE6, 0xE0, 0x23, 0x06, 0x90, 0x54, 0x13, 0x13, 0xFD, ++ 0x01, 0x70, 0x6F, 0x01, 0x90, 0x07, 0x60, 0xE4, 0x44, 0xE0, 0x35, 0x06, 0x87, 0x78, 0xF0, 0x08, ++ 0x10, 0x92, 0x13, 0xE6, 0xFF, 0x7B, 0x0D, 0x31, 0x32, 0x79, 0x20, 0x7A, 0x90, 0xF4, 0x03, 0x12, ++ 0xFF, 0xE0, 0x23, 0x06, 0x3F, 0x54, 0x13, 0x13, 0x7B, 0x09, 0xE0, 0x30, 0x79, 0x20, 0x7A, 0xFF, ++ 0xF4, 0x03, 0x12, 0x38, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x3A, 0x79, 0x90, 0xE4, 0x22, 0xF4, ++ 0x90, 0xF0, 0x01, 0x0D, 0x54, 0xE0, 0x00, 0x0D, 0x44, 0xE0, 0xF0, 0xF8, 0x90, 0xE0, 0xF0, 0x18, ++ 0x90, 0xF0, 0x20, 0x0D, 0x49, 0x74, 0x0A, 0x0D, 0x2A, 0x0D, 0x90, 0xF0, 0x06, 0x0D, 0x90, 0xF0, ++ 0x90, 0xF0, 0x5C, 0x74, 0x90, 0xF0, 0x26, 0x0D, 0xAA, 0x74, 0x82, 0x0D, 0x0C, 0x0D, 0x90, 0xF0, ++ 0x90, 0xF0, 0x11, 0x74, 0x90, 0xF0, 0x2C, 0x0D, 0x30, 0x74, 0x02, 0x0D, 0x22, 0x0D, 0x90, 0xF0, ++ 0x05, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x20, 0x74, 0xE4, 0xF0, 0x25, 0x0D, 0xF0, 0x21, 0x0D, 0x90, ++ 0xE0, 0xF0, 0x07, 0x90, 0xE0, 0xF0, 0x01, 0x44, 0x90, 0xF0, 0xFD, 0x54, 0x44, 0xE0, 0xF5, 0x07, ++ 0x07, 0x90, 0xF0, 0x01, 0xF8, 0x54, 0xE0, 0xF9, 0x90, 0xF0, 0x01, 0x44, 0x44, 0xE0, 0xC1, 0x08, ++ 0x44, 0xE0, 0xF0, 0x01, 0x54, 0xE0, 0xF0, 0x02, 0x08, 0x90, 0xF0, 0xFD, 0xF0, 0xAB, 0x74, 0xC4, ++ 0x14, 0xC3, 0x08, 0x90, 0xC2, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x0A, 0x74, 0x01, 0x74, 0xC5, 0x08, ++ 0x55, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, ++ 0xE0, 0x56, 0x08, 0x90, 0xE0, 0xF0, 0xF0, 0x54, 0x90, 0xF0, 0x30, 0x44, 0x54, 0xE0, 0x57, 0x08, ++ 0xF0, 0x06, 0x44, 0xF8, 0xE0, 0x58, 0x08, 0x90, 0x90, 0xF0, 0x78, 0x74, 0x44, 0xE0, 0x5C, 0x08, ++ 0x08, 0x90, 0xF0, 0x01, 0xF0, 0xAB, 0x74, 0x5F, 0x14, 0x5E, 0x08, 0x90, 0x5D, 0x08, 0x90, 0xF0, ++ 0x90, 0xF0, 0x0A, 0x74, 0x01, 0x74, 0x60, 0x08, 0xFF, 0x07, 0x90, 0xF0, 0xF0, 0xFD, 0x54, 0xE0, ++ 0xE0, 0xFE, 0x07, 0x90, 0xE0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xF7, 0x54, ++ 0x90, 0xF0, 0xFB, 0x54, 0x44, 0xE0, 0xFD, 0x07, 0x44, 0xE0, 0xF0, 0x01, 0x54, 0xE0, 0xF0, 0x02, ++ 0x00, 0x00, 0xF0, 0xF7, 0x90, 0x00, 0x00, 0x00, 0x54, 0xE0, 0xFE, 0x07, 0x07, 0x90, 0xF0, 0xFE, ++ 0xFE, 0x54, 0xE0, 0xFD, 0x33, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x54, 0xE0, 0x34, 0x08, ++ 0x08, 0x90, 0xF0, 0xFE, 0xF0, 0x01, 0x74, 0x3A, 0x74, 0x3B, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x09, ++ 0xF0, 0x01, 0x74, 0x3C, 0xE0, 0x3D, 0x08, 0x90, 0xE0, 0xF0, 0x01, 0x44, 0x90, 0xF0, 0x08, 0x44, ++ 0x44, 0xE0, 0x38, 0x08, 0x07, 0x90, 0xF0, 0x01, 0x01, 0x44, 0xE0, 0x75, 0x8E, 0x07, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x8F, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, 0x54, 0xE0, 0x90, 0x07, ++ 0xF0, 0x03, 0x44, 0xF0, 0x74, 0x91, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x03, 0xFE, 0x54, 0xE0, 0x8F, ++ 0x92, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x93, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, ++ 0x54, 0xE0, 0x94, 0x07, 0xF0, 0x01, 0x44, 0xF0, 0x74, 0x95, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x03, ++ 0xFE, 0x54, 0xE0, 0x93, 0x26, 0x06, 0x90, 0xF0, 0x13, 0xC4, 0xFF, 0xE0, 0xFE, 0x24, 0x07, 0x54, ++ 0x70, 0x04, 0x1D, 0x60, 0x79, 0x07, 0x90, 0x22, 0x90, 0xF0, 0x03, 0x74, 0x54, 0xE0, 0x94, 0x07, ++ 0xF0, 0x02, 0x44, 0xF0, 0xE0, 0x90, 0x07, 0x90, 0x02, 0x44, 0xF0, 0x54, 0x90, 0x0D, 0x80, 0xF0, ++ 0x01, 0x74, 0x79, 0x07, 0xE4, 0x05, 0x80, 0xF0, 0xF0, 0x79, 0x07, 0x90, 0xE0, 0x76, 0x07, 0x90, ++ 0x90, 0xF0, 0xF8, 0x54, 0xFE, 0xE0, 0x30, 0x06, 0x03, 0x78, 0xE0, 0xA3, 0xCE, 0x13, 0xC3, 0xCE, ++ 0x54, 0xF9, 0xD8, 0x13, 0x33, 0x33, 0x33, 0x01, 0x90, 0xFF, 0xF8, 0x54, 0x54, 0xE0, 0x76, 0x07, ++ 0x90, 0xF0, 0x4F, 0xF7, 0x44, 0xE0, 0x96, 0x07, 0x44, 0xE0, 0xF0, 0x02, 0x07, 0x90, 0xF0, 0x01, ++ 0x01, 0x44, 0xE0, 0x97, 0xFE, 0x54, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xF0, ++ 0x49, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xFB, 0x54, 0xE0, ++ 0xF0, 0xF7, 0x54, 0xE0, 0x74, 0x4A, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x0F, 0x08, 0x90, 0xF0, 0x4B, ++ 0xE0, 0x54, 0xE0, 0x4C, 0x90, 0xF0, 0x04, 0x44, 0x54, 0xE0, 0x4D, 0x08, 0xF0, 0x12, 0x44, 0xE0, ++ 0xE0, 0x4E, 0x08, 0x90, 0x17, 0x44, 0xE0, 0x54, 0x4F, 0x08, 0x90, 0xF0, 0x44, 0xC0, 0x54, 0xE0, ++ 0x08, 0x90, 0xF0, 0x26, 0xFC, 0x54, 0xE0, 0x50, 0xE0, 0xF0, 0x01, 0x44, 0x90, 0xF0, 0x3C, 0x44, ++ 0x44, 0xE0, 0x52, 0x08, 0x54, 0xE0, 0xF0, 0x03, 0x08, 0x90, 0xF0, 0xF3, 0xFD, 0x54, 0xE0, 0x49, ++ 0x07, 0x07, 0x90, 0xF0, 0xF0, 0x10, 0x44, 0xE0, 0xF0, 0xEF, 0x54, 0xE0, 0x60, 0x67, 0xE5, 0x22, ++ 0x7A, 0xFF, 0x7B, 0x38, 0x12, 0x0F, 0x79, 0x20, 0x80, 0x78, 0xF4, 0x03, 0x76, 0x08, 0x01, 0x76, ++ 0xC9, 0x01, 0x90, 0xF4, 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x03, 0x06, 0x90, 0x90, 0xF0, 0x04, 0x44, ++ 0x44, 0xE0, 0x35, 0x06, 0x07, 0x90, 0xF0, 0x01, 0xFE, 0x54, 0xE0, 0x8F, 0x93, 0x07, 0x90, 0xF0, ++ 0xF0, 0xFE, 0x54, 0xE0, 0x08, 0xF6, 0x08, 0xE4, 0xA0, 0x07, 0x90, 0xF6, 0x13, 0x13, 0x13, 0xE0, ++ 0xE0, 0x30, 0x1F, 0x54, 0x03, 0x06, 0x90, 0x0D, 0xF0, 0x02, 0x44, 0xE0, 0x74, 0xA0, 0x07, 0x90, ++ 0x07, 0x90, 0xF0, 0x08, 0x14, 0x60, 0xE0, 0x91, 0xE0, 0x8F, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, ++ 0x03, 0x74, 0x91, 0x07, 0x8F, 0x07, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0xC9, 0x01, 0x90, ++ 0x8B, 0x07, 0x90, 0xFF, 0x13, 0x13, 0xC4, 0xE0, 0xEF, 0xFE, 0x01, 0x54, 0x01, 0x54, 0x13, 0xC4, ++ 0xDF, 0x54, 0xEF, 0xFD, 0x54, 0x4E, 0xED, 0xFF, 0x54, 0x33, 0xC4, 0x01, 0x01, 0x90, 0x4F, 0xE0, ++ 0xFF, 0xE0, 0xF0, 0xC9, 0xE0, 0x8B, 0x07, 0x90, 0x01, 0x54, 0x13, 0xC4, 0x13, 0x13, 0xEF, 0xFE, ++ 0xFD, 0x01, 0x54, 0x13, 0xFF, 0xF7, 0x54, 0xEF, 0x01, 0x54, 0x4E, 0xED, 0x54, 0x33, 0x33, 0x33, ++ 0x01, 0x90, 0x4F, 0xF8, 0xFF, 0xE0, 0xF0, 0xC9, 0xE0, 0x8B, 0x07, 0x90, 0x01, 0x54, 0x13, 0xC3, ++ 0x54, 0xC4, 0xEF, 0xFE, 0x54, 0xEF, 0xFD, 0x01, 0x4E, 0xED, 0xFF, 0xEF, 0xC4, 0xFE, 0x01, 0x54, ++ 0x90, 0x4F, 0xF0, 0x54, 0x90, 0xF0, 0xC9, 0x01, 0x62, 0x74, 0x8B, 0x07, 0xA0, 0x07, 0x90, 0xF0, ++ 0x64, 0x07, 0x54, 0xE0, 0xE0, 0x40, 0x60, 0x01, 0x03, 0x64, 0x07, 0x54, 0x78, 0xD3, 0x39, 0x60, ++ 0x00, 0x94, 0xE6, 0x81, 0x00, 0x94, 0xE6, 0x18, 0xE6, 0x08, 0x08, 0x40, 0x01, 0x70, 0x18, 0x16, ++ 0x64, 0x75, 0x22, 0x16, 0xE8, 0x65, 0x75, 0x21, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x19, 0x79, ++ 0xC9, 0x01, 0x90, 0xF4, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0x03, 0x06, 0x90, 0x90, 0xF0, 0xFB, 0x54, ++ 0x44, 0xE0, 0x35, 0x06, 0x78, 0x22, 0xF0, 0x01, 0x08, 0x01, 0x76, 0x80, 0x90, 0x22, 0xF4, 0x76, ++ 0x44, 0xE0, 0x93, 0x07, 0x07, 0x90, 0xF0, 0x01, 0x04, 0x44, 0xE0, 0x9E, 0x26, 0x64, 0x75, 0xF0, ++ 0x22, 0xA4, 0x65, 0x75, 0x09, 0x60, 0x67, 0xE5, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x3C, 0x79, ++ 0x97, 0x07, 0x90, 0xF4, 0x90, 0xF0, 0x03, 0x74, 0x54, 0xE0, 0x96, 0x07, 0x01, 0x90, 0xF0, 0xFE, ++ 0xFE, 0x54, 0xE0, 0xC9, 0x02, 0x06, 0x90, 0xF0, 0xE0, 0xA3, 0xF0, 0xE0, 0xE0, 0xF0, 0xFB, 0x54, ++ 0x75, 0xF0, 0xDF, 0x54, 0x61, 0x75, 0x02, 0x60, 0x90, 0xE4, 0x22, 0x0B, 0x90, 0xF0, 0x01, 0x0D, ++ 0x18, 0x74, 0x00, 0x0D, 0x0D, 0x90, 0xE0, 0xF0, 0x0D, 0x90, 0xF0, 0x20, 0xF0, 0x49, 0x74, 0x0A, ++ 0xF0, 0x2A, 0x0D, 0x90, 0x74, 0x06, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x5C, 0x0D, 0x90, 0xF0, 0x26, ++ 0xF0, 0x4A, 0x74, 0x0B, 0xF0, 0x2B, 0x0D, 0x90, 0x74, 0x82, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0xAA, ++ 0xF0, 0x11, 0x74, 0x0C, 0xF0, 0x2C, 0x0D, 0x90, 0x74, 0x02, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x30, ++ 0x0D, 0x90, 0xF0, 0x22, 0xF0, 0x20, 0x74, 0x05, 0xF0, 0x25, 0x0D, 0x90, 0x21, 0x0D, 0x90, 0xE4, ++ 0xF0, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xE0, 0xF5, 0x07, 0x90, ++ 0x90, 0xF0, 0x01, 0x44, 0x54, 0xE0, 0xF9, 0x07, 0x08, 0x90, 0xF0, 0xF8, 0xF0, 0x03, 0x74, 0x5C, ++ 0x90, 0xF0, 0x01, 0x74, 0xAB, 0x74, 0x5F, 0x08, 0x5E, 0x08, 0x90, 0xF0, 0x08, 0x90, 0xF0, 0x14, ++ 0xF0, 0x0A, 0x74, 0x5D, 0x74, 0x60, 0x08, 0x90, 0x07, 0x90, 0xF0, 0x01, 0xF0, 0x08, 0x74, 0xFF, ++ 0x74, 0xFE, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x03, 0x00, 0x00, 0xF0, 0xFD, 0x90, 0x00, 0x00, 0x00, ++ 0xF0, 0x14, 0xFE, 0x07, 0xF0, 0xFD, 0x07, 0x90, 0x14, 0x33, 0x08, 0x90, 0x3A, 0x08, 0x90, 0xF0, ++ 0x3B, 0x08, 0x90, 0xF0, 0x74, 0xF0, 0x0B, 0x74, 0x08, 0x90, 0xF0, 0x09, 0xF0, 0x03, 0x74, 0x3C, ++ 0x90, 0xF0, 0x01, 0x74, 0x0B, 0x74, 0x3D, 0x08, 0xF0, 0x09, 0x74, 0xF0, 0x74, 0x38, 0x08, 0x90, ++ 0x01, 0x74, 0xF0, 0x03, 0x49, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x03, 0x74, 0x0F, 0x74, 0x4A, 0x08, ++ 0x4B, 0x08, 0x90, 0xF0, 0x50, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x11, 0x74, 0x03, 0x74, 0x52, 0x08, ++ 0x49, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x90, 0xF0, 0x75, 0x07, 0x54, 0xE0, 0x76, 0x07, ++ 0xF0, 0x03, 0x44, 0xF8, 0x74, 0x8E, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x01, 0x07, 0x90, 0xF0, 0x8F, ++ 0x07, 0x90, 0xF0, 0x92, 0x07, 0x90, 0xF0, 0x93, 0xF0, 0x03, 0x74, 0x96, 0xF0, 0x97, 0x07, 0x90, ++ 0x74, 0x9E, 0x07, 0x90, 0x22, 0x22, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x42, 0x30, 0x31, 0x09, 0x09, 0x00, 0x0A, 0x54, 0x75, 0x74, 0x65, 0x53, 0x09, 0x00, 0x0A, 0x70, ++ 0x6B, 0x6E, 0x69, 0x4C, 0x0A, 0x70, 0x55, 0x2D, 0x4C, 0x09, 0x09, 0x00, 0x2D, 0x6B, 0x6E, 0x69, ++ 0x73, 0x73, 0x6F, 0x4C, 0x4C, 0x09, 0x00, 0x0A, 0x2D, 0x6B, 0x6E, 0x69, 0x6E, 0x77, 0x6F, 0x44, ++ 0x09, 0x09, 0x00, 0x0A, 0x00, 0x49, 0x44, 0x4D, 0x00, 0x0A, 0x00, 0x58, 0x69, 0x78, 0x45, 0x09, ++ 0xE5, 0x00, 0x0A, 0x74, 0x7B, 0x12, 0x60, 0x70, 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x00, ++ 0x75, 0x20, 0x6E, 0x75, 0x71, 0x75, 0xBE, 0x6F, 0x12, 0x10, 0xD2, 0x01, 0x1E, 0x50, 0x5D, 0x0E, ++ 0x8F, 0x7F, 0x26, 0x7E, 0x70, 0x6D, 0x65, 0xEF, 0x6C, 0x65, 0xEE, 0x03, 0xA4, 0x74, 0x10, 0x60, ++ 0x04, 0x70, 0x6D, 0x65, 0x6C, 0x65, 0x26, 0x74, 0x6E, 0x8E, 0x04, 0x60, 0x6D, 0xE5, 0x6F, 0x8F, ++ 0x04, 0x70, 0x6F, 0x65, 0x6E, 0x65, 0x6C, 0xE5, 0x6E, 0x85, 0x09, 0x60, 0x6D, 0x6F, 0x85, 0x6C, ++ 0xAA, 0x01, 0x71, 0x75, 0x12, 0x6D, 0xA9, 0x6C, 0xF5, 0xE4, 0x27, 0x03, 0xE6, 0xA0, 0x78, 0x71, ++ 0xC3, 0xFF, 0x01, 0x54, 0x08, 0x74, 0x9F, 0xE4, 0x05, 0x54, 0x00, 0x94, 0xC3, 0xE6, 0x18, 0xFC, ++ 0xE6, 0x08, 0xFE, 0x13, 0x6C, 0xEE, 0xFF, 0x13, 0x08, 0xEF, 0xF6, 0x18, 0xFF, 0x7B, 0x22, 0xF6, ++ 0x07, 0x79, 0x20, 0x7A, 0x51, 0xF4, 0x03, 0x12, 0x12, 0x05, 0x7F, 0xDE, 0x06, 0x90, 0x68, 0x00, ++ 0x90, 0x04, 0x31, 0x63, 0xFF, 0xE0, 0x8A, 0x0D, 0xE0, 0x8B, 0x0D, 0x90, 0x07, 0x90, 0xFF, 0x6F, ++ 0xE4, 0xFD, 0xE0, 0x0C, 0xEF, 0xF6, 0x9F, 0x78, 0xE4, 0xF6, 0x08, 0x6D, 0x08, 0xF6, 0x99, 0x78, ++ 0x22, 0x76, 0x08, 0xF6, 0x90, 0x2E, 0x76, 0x08, 0x0D, 0x74, 0xF3, 0x07, 0x21, 0x6E, 0x75, 0xF0, ++ 0x22, 0xE8, 0x6F, 0x75, 0x13, 0x13, 0xFF, 0xE0, 0x92, 0x13, 0x3F, 0x54, 0x67, 0x06, 0x90, 0x10, ++ 0x03, 0xE0, 0x30, 0xE0, 0x90, 0x1A, 0x10, 0x30, 0x20, 0xE0, 0x67, 0x06, 0x06, 0x90, 0x63, 0xE0, ++ 0xA3, 0xFE, 0xE0, 0x66, 0xCE, 0x02, 0x78, 0xE0, 0x13, 0xCE, 0x13, 0xC3, 0xE0, 0x20, 0xF9, 0xD8, ++ 0x90, 0x10, 0xC2, 0x50, 0x0F, 0x74, 0x41, 0x0D, 0x61, 0x0D, 0x90, 0xF0, 0x0D, 0x90, 0xF0, 0x04, ++ 0x9F, 0x54, 0xE0, 0x40, 0x60, 0x0D, 0x90, 0xF0, 0x44, 0x9F, 0x54, 0xE0, 0x0D, 0x90, 0xF0, 0x20, ++ 0x13, 0x13, 0xE0, 0x8B, 0x22, 0x24, 0x01, 0x54, 0xF0, 0x4C, 0x0D, 0x90, 0x74, 0x6C, 0x0D, 0x90, ++ 0x07, 0x90, 0xF0, 0x12, 0x30, 0x44, 0xE0, 0xF1, 0x3F, 0x54, 0xE0, 0xF0, 0x90, 0xF0, 0x80, 0x44, ++ 0x54, 0xE0, 0xF2, 0x07, 0xF0, 0x20, 0x44, 0xCF, 0xF0, 0xC0, 0x44, 0xE0, 0x80, 0xC4, 0x01, 0x90, ++ 0x90, 0x10, 0xD2, 0x4E, 0x0F, 0x74, 0x61, 0x0D, 0x41, 0x0D, 0x90, 0xF0, 0x0D, 0x90, 0xF0, 0x04, ++ 0x9F, 0x54, 0xE0, 0x40, 0x90, 0xF0, 0x20, 0x44, 0x54, 0xE0, 0x60, 0x0D, 0x0D, 0x90, 0xF0, 0x9F, ++ 0xF0, 0x12, 0x74, 0x4C, 0xE0, 0x8B, 0x0D, 0x90, 0x01, 0x54, 0x13, 0x13, 0x0D, 0x90, 0x22, 0x24, ++ 0x07, 0x90, 0xF0, 0x6C, 0xCF, 0x54, 0xE0, 0xF1, 0xE0, 0xF0, 0x20, 0x44, 0x90, 0xF0, 0xC0, 0x44, ++ 0x44, 0xE0, 0xF2, 0x07, 0x54, 0xE0, 0xF0, 0x30, 0xF0, 0x80, 0x44, 0x3F, 0xE0, 0xC5, 0x01, 0x90, ++ 0xF0, 0x6D, 0x09, 0x90, 0x33, 0xE4, 0x10, 0xA2, 0xE0, 0x25, 0x01, 0x54, 0x90, 0xFF, 0xE0, 0x25, ++ 0x54, 0xE0, 0x63, 0x06, 0x22, 0xF0, 0x4F, 0xFB, 0x25, 0x60, 0x71, 0xE5, 0x20, 0x7A, 0xFF, 0x7B, ++ 0x03, 0x12, 0x26, 0x79, 0x76, 0x9D, 0x78, 0xF4, 0xD4, 0x76, 0x08, 0x30, 0xE0, 0xD8, 0x07, 0x90, ++ 0x90, 0xF0, 0x01, 0x44, 0x44, 0xE0, 0xDC, 0x07, 0x07, 0x90, 0xF0, 0x01, 0x02, 0x44, 0xE0, 0xD4, ++ 0x40, 0x06, 0x90, 0xF0, 0x0F, 0x54, 0xC4, 0xE0, 0xD3, 0x1B, 0xE0, 0x30, 0x94, 0xE6, 0x9C, 0x78, ++ 0x94, 0xE6, 0x18, 0x00, 0x08, 0x09, 0x40, 0x00, 0x70, 0x18, 0x16, 0xE6, 0x06, 0x80, 0x16, 0x01, ++ 0x75, 0x26, 0x6E, 0x75, 0x07, 0x90, 0x8F, 0x6F, 0x07, 0x54, 0xE0, 0xE9, 0x09, 0x60, 0x01, 0x64, ++ 0xE0, 0xD4, 0x07, 0x90, 0xE0, 0x30, 0x13, 0xC3, 0x25, 0x6E, 0x75, 0x06, 0x90, 0x5D, 0x6F, 0x75, ++ 0xC4, 0xE0, 0x40, 0x06, 0xE0, 0x30, 0x0F, 0x54, 0x63, 0x06, 0x90, 0x05, 0x06, 0x90, 0x07, 0x80, ++ 0xE0, 0x20, 0xE0, 0x67, 0x78, 0x04, 0x31, 0x0A, 0x08, 0x30, 0x76, 0x9D, 0xD3, 0x22, 0xD4, 0x76, ++ 0x94, 0xE6, 0x9E, 0x78, 0x94, 0xE6, 0x18, 0x00, 0x08, 0x08, 0x40, 0x00, 0x70, 0x18, 0x16, 0xE6, ++ 0x78, 0x22, 0x16, 0x01, 0x08, 0x30, 0x76, 0x9D, 0x07, 0x90, 0xD4, 0x76, 0x07, 0x54, 0xE0, 0xE9, ++ 0xA0, 0x78, 0x4B, 0x70, 0xFF, 0x01, 0x54, 0xE6, 0xE0, 0x63, 0x06, 0x90, 0x54, 0x13, 0x13, 0xFD, ++ 0x01, 0x70, 0x6F, 0x01, 0x90, 0x07, 0x60, 0xE4, 0x44, 0xE0, 0x75, 0x06, 0xA0, 0x78, 0xF0, 0x08, ++ 0x10, 0x92, 0x13, 0xE6, 0xFF, 0x7B, 0x0D, 0x31, 0x32, 0x79, 0x20, 0x7A, 0x90, 0xF4, 0x03, 0x12, ++ 0xFF, 0xE0, 0x63, 0x06, 0x3F, 0x54, 0x13, 0x13, 0x7B, 0x09, 0xE0, 0x30, 0x79, 0x20, 0x7A, 0xFF, ++ 0xF4, 0x03, 0x12, 0x38, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x3A, 0x79, 0x90, 0xE4, 0x22, 0xF4, ++ 0x90, 0xF0, 0x41, 0x0D, 0x54, 0xE0, 0x40, 0x0D, 0x44, 0xE0, 0xF0, 0xF8, 0x90, 0xE0, 0xF0, 0x18, ++ 0x90, 0xF0, 0x60, 0x0D, 0x49, 0x74, 0x4A, 0x0D, 0x6A, 0x0D, 0x90, 0xF0, 0x46, 0x0D, 0x90, 0xF0, ++ 0x90, 0xF0, 0x5C, 0x74, 0x90, 0xF0, 0x66, 0x0D, 0xAA, 0x74, 0x82, 0x0D, 0x4C, 0x0D, 0x90, 0xF0, ++ 0x90, 0xF0, 0x11, 0x74, 0x90, 0xF0, 0x6C, 0x0D, 0x30, 0x74, 0x42, 0x0D, 0x62, 0x0D, 0x90, 0xF0, ++ 0x45, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x20, 0x74, 0xE4, 0xF0, 0x65, 0x0D, 0xF0, 0x61, 0x0D, 0x90, ++ 0xE0, 0xF0, 0x07, 0x90, 0xE0, 0xF0, 0x08, 0x44, 0x90, 0xF0, 0xFB, 0x54, 0x44, 0xE0, 0xF5, 0x07, ++ 0x07, 0x90, 0xF0, 0x01, 0x8F, 0x54, 0xE0, 0xFA, 0x90, 0xF0, 0x20, 0x44, 0x44, 0xE0, 0x26, 0x09, ++ 0x44, 0xE0, 0xF0, 0x01, 0x54, 0xE0, 0xF0, 0x02, 0x09, 0x90, 0xF0, 0xFD, 0xF0, 0xAB, 0x74, 0x29, ++ 0x14, 0x28, 0x09, 0x90, 0x27, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x0A, 0x74, 0x01, 0x74, 0x2A, 0x09, ++ 0x84, 0x09, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, ++ 0xE0, 0x85, 0x09, 0x90, 0xE0, 0xF0, 0xF0, 0x54, 0x90, 0xF0, 0x30, 0x44, 0x54, 0xE0, 0x86, 0x09, ++ 0xF0, 0x06, 0x44, 0xF8, 0xE0, 0x87, 0x09, 0x90, 0x90, 0xF0, 0x78, 0x74, 0x44, 0xE0, 0x8B, 0x09, ++ 0x09, 0x90, 0xF0, 0x01, 0xF0, 0xAB, 0x74, 0x8E, 0x14, 0x8D, 0x09, 0x90, 0x8C, 0x09, 0x90, 0xF0, ++ 0x90, 0xF0, 0x0A, 0x74, 0x01, 0x74, 0x8F, 0x09, 0x2E, 0x09, 0x90, 0xF0, 0xF0, 0xFD, 0x54, 0xE0, ++ 0xE0, 0x2D, 0x09, 0x90, 0xE0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xF7, 0x54, ++ 0x90, 0xF0, 0xFB, 0x54, 0x44, 0xE0, 0x2C, 0x09, 0x44, 0xE0, 0xF0, 0x01, 0x54, 0xE0, 0xF0, 0x02, ++ 0x00, 0x00, 0xF0, 0xF7, 0x90, 0x00, 0x00, 0x00, 0x54, 0xE0, 0x2D, 0x09, 0x09, 0x90, 0xF0, 0xFE, ++ 0xFE, 0x54, 0xE0, 0x2C, 0x62, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x54, 0xE0, 0x63, 0x09, ++ 0x09, 0x90, 0xF0, 0xFE, 0xF0, 0x01, 0x74, 0x69, 0x74, 0x6A, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x09, ++ 0xF0, 0x01, 0x74, 0x6B, 0xE0, 0x6C, 0x09, 0x90, 0xE0, 0xF0, 0x01, 0x44, 0x90, 0xF0, 0x08, 0x44, ++ 0x44, 0xE0, 0x67, 0x09, 0x07, 0x90, 0xF0, 0x01, 0x01, 0x44, 0xE0, 0xBE, 0xD7, 0x07, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0xD8, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, 0x54, 0xE0, 0xD9, 0x07, ++ 0xF0, 0x03, 0x44, 0xF0, 0x74, 0xDA, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x03, 0xFE, 0x54, 0xE0, 0xD8, ++ 0xDB, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0xDC, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, ++ 0x54, 0xE0, 0xDD, 0x07, 0xF0, 0x01, 0x44, 0xF0, 0x74, 0xDE, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x03, ++ 0xFE, 0x54, 0xE0, 0xDC, 0x66, 0x06, 0x90, 0xF0, 0x13, 0xC4, 0xFF, 0xE0, 0xFE, 0x24, 0x07, 0x54, ++ 0x70, 0x04, 0x1D, 0x60, 0xC2, 0x07, 0x90, 0x22, 0x90, 0xF0, 0x03, 0x74, 0x54, 0xE0, 0xDD, 0x07, ++ 0xF0, 0x02, 0x44, 0xF0, 0xE0, 0xD9, 0x07, 0x90, 0x02, 0x44, 0xF0, 0x54, 0x90, 0x0D, 0x80, 0xF0, ++ 0x01, 0x74, 0xC2, 0x07, 0xE4, 0x05, 0x80, 0xF0, 0xF0, 0xC2, 0x07, 0x90, 0xE0, 0xBF, 0x07, 0x90, ++ 0x90, 0xF0, 0xF8, 0x54, 0xFE, 0xE0, 0x70, 0x06, 0x03, 0x78, 0xE0, 0xA3, 0xCE, 0x13, 0xC3, 0xCE, ++ 0x54, 0xF9, 0xD8, 0x13, 0x33, 0x33, 0x33, 0x01, 0x90, 0xFF, 0xF8, 0x54, 0x54, 0xE0, 0xBF, 0x07, ++ 0x90, 0xF0, 0x4F, 0xF7, 0x44, 0xE0, 0xDF, 0x07, 0x44, 0xE0, 0xF0, 0x02, 0x07, 0x90, 0xF0, 0x01, ++ 0x01, 0x44, 0xE0, 0xE0, 0xFE, 0x54, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xF0, ++ 0x78, 0x09, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xFB, 0x54, 0xE0, ++ 0xF0, 0xF7, 0x54, 0xE0, 0x74, 0x79, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x0F, 0x09, 0x90, 0xF0, 0x7A, ++ 0xE0, 0x54, 0xE0, 0x7B, 0x90, 0xF0, 0x04, 0x44, 0x54, 0xE0, 0x7C, 0x09, 0xF0, 0x12, 0x44, 0xE0, ++ 0xE0, 0x7D, 0x09, 0x90, 0x17, 0x44, 0xE0, 0x54, 0x7E, 0x09, 0x90, 0xF0, 0x44, 0xC0, 0x54, 0xE0, ++ 0x09, 0x90, 0xF0, 0x26, 0xFC, 0x54, 0xE0, 0x7F, 0xE0, 0xF0, 0x01, 0x44, 0x90, 0xF0, 0x3C, 0x44, ++ 0x44, 0xE0, 0x81, 0x09, 0x54, 0xE0, 0xF0, 0x03, 0x09, 0x90, 0xF0, 0xF3, 0xFD, 0x54, 0xE0, 0x78, ++ 0x07, 0x07, 0x90, 0xF0, 0xF0, 0x10, 0x44, 0xE0, 0xF0, 0xEF, 0x54, 0xE0, 0x60, 0x71, 0xE5, 0x22, ++ 0x7A, 0xFF, 0x7B, 0x38, 0x12, 0x0F, 0x79, 0x20, 0x99, 0x78, 0xF4, 0x03, 0x76, 0x08, 0x01, 0x76, ++ 0xCB, 0x01, 0x90, 0xF4, 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x43, 0x06, 0x90, 0x90, 0xF0, 0x04, 0x44, ++ 0x44, 0xE0, 0x75, 0x06, 0x07, 0x90, 0xF0, 0x01, 0xFE, 0x54, 0xE0, 0xD8, 0xDC, 0x07, 0x90, 0xF0, ++ 0xF0, 0xFE, 0x54, 0xE0, 0x08, 0xF6, 0x08, 0xE4, 0xE9, 0x07, 0x90, 0xF6, 0x13, 0x13, 0x13, 0xE0, ++ 0xE0, 0x30, 0x1F, 0x54, 0x43, 0x06, 0x90, 0x0D, 0xF0, 0x02, 0x44, 0xE0, 0x74, 0xE9, 0x07, 0x90, ++ 0x07, 0x90, 0xF0, 0x08, 0x14, 0x60, 0xE0, 0xDA, 0xE0, 0xD8, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, ++ 0x03, 0x74, 0xDA, 0x07, 0xD8, 0x07, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0xCB, 0x01, 0x90, ++ 0xD4, 0x07, 0x90, 0xFF, 0x13, 0x13, 0xC4, 0xE0, 0xEF, 0xFE, 0x01, 0x54, 0x01, 0x54, 0x13, 0xC4, ++ 0xDF, 0x54, 0xEF, 0xFD, 0x54, 0x4E, 0xED, 0xFF, 0x54, 0x33, 0xC4, 0x01, 0x01, 0x90, 0x4F, 0xE0, ++ 0xFF, 0xE0, 0xF0, 0xCB, 0xE0, 0xD4, 0x07, 0x90, 0x01, 0x54, 0x13, 0xC4, 0x13, 0x13, 0xEF, 0xFE, ++ 0xFD, 0x01, 0x54, 0x13, 0xFF, 0xF7, 0x54, 0xEF, 0x01, 0x54, 0x4E, 0xED, 0x54, 0x33, 0x33, 0x33, ++ 0x01, 0x90, 0x4F, 0xF8, 0xFF, 0xE0, 0xF0, 0xCB, 0xE0, 0xD4, 0x07, 0x90, 0x01, 0x54, 0x13, 0xC3, ++ 0x54, 0xC4, 0xEF, 0xFE, 0x54, 0xEF, 0xFD, 0x01, 0x4E, 0xED, 0xFF, 0xEF, 0xC4, 0xFE, 0x01, 0x54, ++ 0x90, 0x4F, 0xF0, 0x54, 0x90, 0xF0, 0xCB, 0x01, 0x62, 0x74, 0xD4, 0x07, 0xE9, 0x07, 0x90, 0xF0, ++ 0x64, 0x07, 0x54, 0xE0, 0xE0, 0x40, 0x60, 0x01, 0x03, 0x64, 0x07, 0x54, 0x78, 0xD3, 0x39, 0x60, ++ 0x00, 0x94, 0xE6, 0x9A, 0x00, 0x94, 0xE6, 0x18, 0xE6, 0x08, 0x08, 0x40, 0x01, 0x70, 0x18, 0x16, ++ 0x6E, 0x75, 0x22, 0x16, 0xE8, 0x6F, 0x75, 0x21, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x19, 0x79, ++ 0xCB, 0x01, 0x90, 0xF4, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0x43, 0x06, 0x90, 0x90, 0xF0, 0xFB, 0x54, ++ 0x44, 0xE0, 0x75, 0x06, 0x78, 0x22, 0xF0, 0x01, 0x08, 0x01, 0x76, 0x99, 0x90, 0x22, 0xF4, 0x76, ++ 0x44, 0xE0, 0xDC, 0x07, 0x07, 0x90, 0xF0, 0x01, 0x04, 0x44, 0xE0, 0xE7, 0x26, 0x6E, 0x75, 0xF0, ++ 0x22, 0xA4, 0x6F, 0x75, 0x09, 0x60, 0x71, 0xE5, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x3C, 0x79, ++ 0xE0, 0x07, 0x90, 0xF4, 0x90, 0xF0, 0x03, 0x74, 0x54, 0xE0, 0xDF, 0x07, 0x01, 0x90, 0xF0, 0xFE, ++ 0xFE, 0x54, 0xE0, 0xCB, 0x42, 0x06, 0x90, 0xF0, 0xE0, 0xA3, 0xF0, 0xE0, 0xE0, 0xF0, 0xFB, 0x54, ++ 0x75, 0xF0, 0xDF, 0x54, 0x6B, 0x75, 0x02, 0x6A, 0x90, 0xE4, 0x22, 0x24, 0x90, 0xF0, 0x41, 0x0D, ++ 0x18, 0x74, 0x40, 0x0D, 0x0D, 0x90, 0xE0, 0xF0, 0x0D, 0x90, 0xF0, 0x60, 0xF0, 0x49, 0x74, 0x4A, ++ 0xF0, 0x6A, 0x0D, 0x90, 0x74, 0x46, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x5C, 0x0D, 0x90, 0xF0, 0x66, ++ 0xF0, 0x4A, 0x74, 0x4B, 0xF0, 0x6B, 0x0D, 0x90, 0x74, 0x82, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0xAA, ++ 0xF0, 0x11, 0x74, 0x4C, 0xF0, 0x6C, 0x0D, 0x90, 0x74, 0x42, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x30, ++ 0x0D, 0x90, 0xF0, 0x62, 0xF0, 0x20, 0x74, 0x45, 0xF0, 0x65, 0x0D, 0x90, 0x61, 0x0D, 0x90, 0xE4, ++ 0xF0, 0x07, 0x90, 0xF0, 0xF0, 0xFB, 0x54, 0xE0, 0xF0, 0x08, 0x44, 0xE0, 0xE0, 0xF5, 0x07, 0x90, ++ 0x90, 0xF0, 0x01, 0x44, 0x54, 0xE0, 0xFA, 0x07, 0xF0, 0x30, 0x44, 0x8F, 0x74, 0x8B, 0x09, 0x90, ++ 0x01, 0x74, 0xF0, 0x03, 0x8E, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0xAB, 0x74, 0xF0, 0x14, 0x8D, 0x09, ++ 0x74, 0x8C, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x0A, 0xF0, 0x01, 0x74, 0x8F, 0x74, 0x2E, 0x09, 0x90, ++ 0x09, 0x90, 0xF0, 0x08, 0xF0, 0x03, 0x74, 0x2D, 0xF0, 0x2C, 0x09, 0x90, 0x00, 0x00, 0x00, 0x00, ++ 0x2D, 0x09, 0x90, 0x00, 0x09, 0x90, 0xF0, 0x14, 0x09, 0x90, 0xF0, 0x2C, 0x90, 0xF0, 0x14, 0x62, ++ 0x90, 0xF0, 0x69, 0x09, 0x0B, 0x74, 0x6A, 0x09, 0xF0, 0x09, 0x74, 0xF0, 0x74, 0x6B, 0x09, 0x90, ++ 0x01, 0x74, 0xF0, 0x03, 0x6C, 0x09, 0x90, 0xF0, 0x74, 0xF0, 0x0B, 0x74, 0x09, 0x90, 0xF0, 0x09, ++ 0xF0, 0x03, 0x74, 0x67, 0x90, 0xF0, 0x01, 0x74, 0x03, 0x74, 0x78, 0x09, 0x79, 0x09, 0x90, 0xF0, ++ 0x90, 0xF0, 0x0F, 0x74, 0x90, 0xF0, 0x7A, 0x09, 0x11, 0x74, 0x7F, 0x09, 0x81, 0x09, 0x90, 0xF0, ++ 0x90, 0xF0, 0x03, 0x74, 0x01, 0x74, 0x78, 0x09, 0xBE, 0x07, 0x90, 0xF0, 0xBF, 0x07, 0x90, 0xF0, ++ 0x44, 0xF8, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x03, 0xF0, 0x01, 0x74, 0xD7, 0xF0, 0xD8, 0x07, 0x90, ++ 0xF0, 0xDB, 0x07, 0x90, 0xF0, 0xDC, 0x07, 0x90, 0x74, 0xDF, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x03, ++ 0x07, 0x90, 0xF0, 0xE0, 0xF0, 0xFF, 0x74, 0xE7, 0x00, 0x00, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, ++ 0x30, 0x30, 0x31, 0x09, 0x0A, 0x58, 0x54, 0x62, 0x65, 0x53, 0x09, 0x00, 0x0A, 0x70, 0x75, 0x74, ++ 0x61, 0x57, 0x09, 0x00, 0x0A, 0x50, 0x74, 0x69, 0x4D, 0x09, 0x09, 0x00, 0x58, 0x00, 0x49, 0x44, ++ 0x09, 0x00, 0x0A, 0x00, 0x0A, 0x43, 0x47, 0x41, 0x41, 0x09, 0x09, 0x00, 0x25, 0x3D, 0x43, 0x47, ++ 0x50, 0x00, 0x20, 0x64, 0x25, 0x3D, 0x52, 0x57, 0x09, 0x00, 0x0A, 0x64, 0x0A, 0x30, 0x4B, 0x4F, ++ 0x4C, 0x09, 0x09, 0x00, 0x25, 0x20, 0x3A, 0x43, 0x09, 0x00, 0x0A, 0x64, 0x0A, 0x31, 0x4B, 0x4F, ++ 0x4B, 0x4F, 0x09, 0x00, 0x09, 0x00, 0x0A, 0x32, 0x0A, 0x33, 0x4B, 0x4F, 0x4B, 0x4F, 0x09, 0x00, ++ 0x09, 0x09, 0x0A, 0x34, 0x00, 0x64, 0x25, 0x00, 0x61, 0x72, 0x54, 0x09, 0x00, 0x0A, 0x6B, 0x63, ++ 0x6E, 0x79, 0x53, 0x09, 0x09, 0x00, 0x0A, 0x63, 0x6E, 0x77, 0x6F, 0x44, 0x45, 0x09, 0x00, 0x0A, ++ 0x0A, 0x74, 0x69, 0x78, 0x60, 0x67, 0xE5, 0x00, 0x7A, 0xFF, 0x7B, 0x10, 0x12, 0x3B, 0x79, 0x20, ++ 0x82, 0x78, 0xF4, 0x03, 0x02, 0x12, 0x05, 0x76, 0x50, 0xD7, 0x11, 0x47, 0x22, 0x64, 0x75, 0x07, ++ 0x22, 0xC3, 0x65, 0x75, 0x70, 0xE6, 0x82, 0x78, 0x2E, 0x08, 0x90, 0x2D, 0x9F, 0x54, 0xE0, 0xF0, ++ 0x7B, 0xF0, 0x40, 0x44, 0x79, 0x20, 0x7A, 0xFF, 0x31, 0x08, 0x90, 0x41, 0x08, 0x90, 0xFE, 0xE0, ++ 0xEE, 0xFD, 0xE0, 0x32, 0x0D, 0x12, 0xED, 0xFC, 0x24, 0x64, 0x75, 0x40, 0x78, 0xC2, 0x65, 0x75, ++ 0x08, 0x01, 0x76, 0x85, 0x90, 0x22, 0xF4, 0x76, 0xFF, 0xE0, 0x47, 0x08, 0x94, 0x80, 0x64, 0xD3, ++ 0x78, 0x0C, 0x40, 0x85, 0x0A, 0x94, 0xE6, 0x88, 0x80, 0x06, 0x03, 0x50, 0xC3, 0x22, 0xC3, 0x0E, ++ 0x94, 0x80, 0x64, 0xEF, 0xE4, 0x04, 0x50, 0x83, 0xD3, 0xF6, 0x88, 0x78, 0x60, 0x67, 0xE5, 0x22, ++ 0x7A, 0xFF, 0x7B, 0x69, 0x12, 0x11, 0x79, 0x20, 0x0D, 0x90, 0xF4, 0x03, 0xF8, 0x54, 0xE0, 0x00, ++ 0x20, 0x0D, 0x90, 0xF0, 0xF0, 0xF8, 0x54, 0xE0, 0x0C, 0x76, 0x8C, 0x78, 0x90, 0x1C, 0x76, 0x08, ++ 0xFF, 0xE0, 0x8A, 0x0D, 0xE0, 0x8B, 0x0D, 0x90, 0x07, 0x90, 0xFF, 0x6F, 0xE4, 0xFD, 0xE0, 0x0B, ++ 0x6D, 0xEF, 0xF6, 0x08, 0x78, 0xE4, 0xF6, 0x08, 0x0D, 0x90, 0xF6, 0x88, 0xF0, 0x30, 0x74, 0x89, ++ 0xE0, 0x40, 0x08, 0x90, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0x08, 0x44, 0x90, 0xF0, 0x20, 0x44, ++ 0x54, 0xE0, 0x44, 0x08, 0xF0, 0x20, 0x44, 0x0F, 0xE0, 0x43, 0x08, 0x90, 0xE0, 0xF0, 0x70, 0x44, ++ 0x90, 0xF0, 0x80, 0x44, 0x54, 0xE0, 0x40, 0x08, 0x06, 0x90, 0xF0, 0xF7, 0x54, 0xC4, 0xE0, 0x00, ++ 0x04, 0xE0, 0x30, 0x0F, 0x1E, 0x80, 0x0C, 0x51, 0xE0, 0x27, 0x06, 0x90, 0xE0, 0x20, 0xE0, 0x20, ++ 0x01, 0x54, 0x13, 0x13, 0x23, 0x06, 0x90, 0xFF, 0x13, 0x13, 0xFE, 0xE0, 0x60, 0x6F, 0x01, 0x54, ++ 0x27, 0x06, 0x90, 0x05, 0x8C, 0x78, 0x0F, 0x51, 0x76, 0x08, 0x0C, 0x76, 0x7F, 0x62, 0x80, 0x1C, ++ 0x48, 0x0E, 0x12, 0x8C, 0x8C, 0x78, 0x5B, 0x50, 0x76, 0x08, 0x0C, 0x76, 0x47, 0x08, 0x90, 0x1C, ++ 0x05, 0x94, 0xC3, 0xE0, 0x8F, 0x78, 0x24, 0x50, 0xFF, 0x01, 0x54, 0xE6, 0xE0, 0x23, 0x06, 0x90, ++ 0x54, 0x13, 0x13, 0xFD, 0x01, 0x70, 0x6F, 0x01, 0x90, 0x07, 0x60, 0xE4, 0x44, 0xE0, 0x35, 0x06, ++ 0x8F, 0x78, 0xF0, 0x08, 0x10, 0x92, 0x13, 0xE6, 0xFF, 0x7B, 0x18, 0x51, 0x19, 0x79, 0x20, 0x7A, ++ 0x90, 0xF4, 0x03, 0x12, 0xFF, 0xE0, 0x23, 0x06, 0x3F, 0x54, 0x13, 0x13, 0x7B, 0x09, 0xE0, 0x30, ++ 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x1F, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x21, 0x79, ++ 0x40, 0xD7, 0x11, 0xF4, 0x26, 0x64, 0x75, 0x06, 0x22, 0x7D, 0x65, 0x75, 0xE0, 0x23, 0x06, 0x90, ++ 0x54, 0x13, 0x13, 0xFF, 0x10, 0x92, 0x13, 0x3F, 0xE0, 0x27, 0x06, 0x90, 0x30, 0x03, 0xE0, 0x30, ++ 0x06, 0x90, 0x1A, 0x10, 0xE0, 0x20, 0xE0, 0x27, 0x26, 0x06, 0x90, 0x4B, 0xE0, 0xA3, 0xFE, 0xE0, ++ 0xC3, 0xCE, 0x02, 0x78, 0xD8, 0x13, 0xCE, 0x13, 0x38, 0xE0, 0x20, 0xF9, 0x0D, 0x90, 0x10, 0xC2, ++ 0xF0, 0x0F, 0x74, 0x01, 0x04, 0x21, 0x0D, 0x90, 0xF1, 0x07, 0x90, 0xF0, 0xF0, 0xFC, 0x54, 0xE0, ++ 0x44, 0xF3, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x04, 0xFC, 0x54, 0xE0, 0xF2, 0xE0, 0xF0, 0x01, 0x44, ++ 0x90, 0xF0, 0xF3, 0x54, 0x36, 0x74, 0x0C, 0x0D, 0x2C, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x15, 0x74, ++ 0x36, 0x80, 0xC0, 0x01, 0x0D, 0x90, 0x10, 0xD2, 0xF0, 0x0F, 0x74, 0x21, 0x04, 0x01, 0x0D, 0x90, ++ 0xF1, 0x07, 0x90, 0xF0, 0x44, 0xFC, 0x54, 0xE0, 0x54, 0xE0, 0xF0, 0x01, 0x07, 0x90, 0xF0, 0xF3, ++ 0xFC, 0x54, 0xE0, 0xF2, 0xF3, 0x54, 0xE0, 0xF0, 0x90, 0xF0, 0x04, 0x44, 0x36, 0x74, 0x2C, 0x0D, ++ 0x0C, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x15, 0x74, 0x90, 0xE0, 0xC1, 0x01, 0xA2, 0xF0, 0x3E, 0x08, ++ 0x54, 0x33, 0xE4, 0x10, 0x25, 0xE0, 0x25, 0x01, 0x06, 0x90, 0xFF, 0xE0, 0xFB, 0x54, 0xE0, 0x23, ++ 0x7B, 0x22, 0xF0, 0x4F, 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x77, 0xC9, 0x01, 0x90, 0xE4, ++ 0x02, 0x06, 0x90, 0xF0, 0xE0, 0xA3, 0xF0, 0xE0, 0xE4, 0xF0, 0xFB, 0x54, 0x08, 0xF6, 0x83, 0x78, ++ 0x93, 0x07, 0x90, 0xF6, 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x00, 0x06, 0x90, 0x20, 0x0F, 0x54, 0xC4, ++ 0xC4, 0xE0, 0x23, 0xE0, 0x30, 0x07, 0x54, 0x13, 0xFE, 0xE0, 0x1B, 0xE0, 0x06, 0x78, 0xE0, 0xA3, ++ 0xCE, 0x13, 0xC3, 0xCE, 0x20, 0xF9, 0xD8, 0x13, 0xD7, 0x11, 0x0B, 0xE0, 0x64, 0x75, 0x11, 0x50, ++ 0xFD, 0x65, 0x75, 0x20, 0xE6, 0x87, 0x78, 0x22, 0x11, 0x0B, 0x60, 0x16, 0x75, 0x07, 0x40, 0xD7, ++ 0x65, 0x75, 0x20, 0x64, 0x64, 0x75, 0x22, 0x85, 0xEA, 0x65, 0x75, 0x27, 0x7A, 0xFF, 0x7B, 0x22, ++ 0x12, 0x09, 0x79, 0x20, 0x02, 0x12, 0xF4, 0x03, 0x75, 0x0C, 0x51, 0x4C, 0x65, 0x75, 0x20, 0x64, ++ 0xFF, 0x7B, 0x22, 0xFD, 0x68, 0x79, 0x20, 0x7A, 0x90, 0xF4, 0x03, 0x12, 0x78, 0xE0, 0x47, 0x08, ++ 0x90, 0xE4, 0xF6, 0x89, 0x90, 0xF0, 0x23, 0x08, 0x54, 0xE0, 0x24, 0x08, 0xF0, 0x08, 0x44, 0xE3, ++ 0x74, 0x28, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x02, 0xFB, 0x54, 0xE0, 0x27, 0x56, 0x08, 0x90, 0xF0, ++ 0x90, 0xF0, 0x37, 0x74, 0x05, 0x74, 0x57, 0x08, 0x58, 0x08, 0x90, 0xF0, 0xC8, 0x74, 0xE4, 0xE0, ++ 0x50, 0xD7, 0x11, 0xF0, 0x22, 0x64, 0x75, 0x07, 0x22, 0xC3, 0x65, 0x75, 0x75, 0x25, 0x64, 0x75, ++ 0xE5, 0x22, 0x51, 0x65, 0x7B, 0x4A, 0x60, 0x67, 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x57, ++ 0x64, 0x76, 0x82, 0x78, 0x74, 0x21, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x0D, 0x07, 0x44, 0xE0, 0x43, ++ 0x42, 0x08, 0x90, 0xF0, 0xF0, 0x03, 0x44, 0xE0, 0x74, 0x23, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x02, ++ 0xE3, 0x54, 0xE0, 0x24, 0x90, 0xF0, 0x14, 0x44, 0x02, 0x74, 0x28, 0x08, 0x56, 0x08, 0x90, 0xF0, ++ 0x90, 0xF0, 0x37, 0x74, 0x03, 0x74, 0x57, 0x08, 0x58, 0x08, 0x90, 0xF0, 0xC8, 0x74, 0xE4, 0xE0, ++ 0x50, 0xD7, 0x11, 0xF0, 0x22, 0x64, 0x75, 0x07, 0x22, 0xC3, 0x65, 0x75, 0x70, 0xE6, 0x82, 0x78, ++ 0x27, 0x64, 0x75, 0x06, 0x22, 0x19, 0x65, 0x75, 0x2E, 0x60, 0x67, 0xE5, 0x20, 0x7A, 0xFF, 0x7B, ++ 0x03, 0x12, 0x51, 0x79, 0x76, 0x82, 0x78, 0xF4, 0x24, 0x08, 0x90, 0x14, 0xF0, 0xFD, 0x54, 0xE0, ++ 0xE0, 0x27, 0x08, 0x90, 0x90, 0xF0, 0xFB, 0x54, 0x54, 0xE0, 0x2B, 0x08, 0x08, 0x90, 0xF0, 0xFD, ++ 0xF0, 0x37, 0x74, 0x56, 0x74, 0x57, 0x08, 0x90, 0x72, 0x91, 0xF0, 0x03, 0x07, 0x40, 0xD7, 0x11, ++ 0x0E, 0x12, 0x85, 0x7F, 0x75, 0x07, 0x50, 0x48, 0x65, 0x75, 0x22, 0x64, 0x82, 0x78, 0x22, 0xC3, ++ 0x90, 0x2E, 0x70, 0xE6, 0xC3, 0xE0, 0x46, 0x08, 0x08, 0x50, 0x0D, 0x94, 0x75, 0x23, 0x64, 0x75, ++ 0x06, 0x80, 0x93, 0x65, 0x75, 0x24, 0x64, 0x75, 0x90, 0xE4, 0xC2, 0x65, 0xE0, 0xF0, 0x2E, 0x08, ++ 0x40, 0x44, 0x9F, 0x54, 0x31, 0x08, 0x90, 0xF0, 0x75, 0x06, 0x70, 0xE0, 0x65, 0x75, 0x20, 0x64, ++ 0x08, 0x90, 0x22, 0x85, 0xF0, 0x0D, 0x74, 0x21, 0x54, 0xED, 0x02, 0x7D, 0x2E, 0x08, 0x90, 0x0F, ++ 0x31, 0x08, 0x90, 0xF0, 0x90, 0x24, 0xF5, 0xE0, 0xF5, 0xE0, 0x32, 0x08, 0xFF, 0x24, 0xE5, 0x25, ++ 0xFE, 0xE0, 0x95, 0x33, 0x9F, 0x25, 0xE5, 0xC3, 0x24, 0xE5, 0x25, 0xF5, 0x90, 0x24, 0xF5, 0x9E, ++ 0x44, 0xE0, 0x2E, 0x08, 0x08, 0x90, 0xF0, 0x10, 0xF0, 0x24, 0xE5, 0x2F, 0xE5, 0x30, 0x08, 0x90, ++ 0x90, 0xE4, 0xF0, 0x25, 0x0D, 0xF0, 0x2E, 0x08, 0x90, 0xBF, 0x0A, 0xBD, 0x05, 0x74, 0x21, 0x08, ++ 0x67, 0xE5, 0x22, 0xF0, 0xFF, 0x7B, 0x64, 0x60, 0x4B, 0x79, 0x20, 0x7A, 0x78, 0xF4, 0x03, 0x12, ++ 0x90, 0x0A, 0x76, 0x82, 0x0D, 0x74, 0x21, 0x08, 0x23, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x04, 0x74, ++ 0x54, 0xE0, 0x24, 0x08, 0xF0, 0x10, 0x44, 0xE3, 0xF0, 0x02, 0x44, 0xE0, 0xE0, 0x27, 0x08, 0x90, ++ 0x90, 0xF0, 0xFB, 0x54, 0x03, 0x74, 0x28, 0x08, 0x29, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, ++ 0xE0, 0x2B, 0x08, 0x90, 0xE0, 0xF0, 0xE7, 0x54, 0xE0, 0xF0, 0x01, 0x44, 0x90, 0xF0, 0xFD, 0x54, ++ 0x74, 0xE0, 0x2C, 0x08, 0x08, 0x90, 0xF0, 0xCD, 0xF0, 0x34, 0x74, 0x56, 0x74, 0x57, 0x08, 0x90, ++ 0x08, 0x90, 0xF0, 0x03, 0x74, 0xE4, 0xE0, 0x58, 0xD7, 0x11, 0xF0, 0xC8, 0x85, 0x7F, 0x07, 0x40, ++ 0x50, 0x48, 0x0E, 0x12, 0x22, 0x64, 0x75, 0x07, 0x22, 0xC3, 0x65, 0x75, 0x70, 0xE6, 0x82, 0x78, ++ 0x46, 0x08, 0x90, 0x0F, 0x17, 0x94, 0xC3, 0xE0, 0x64, 0x75, 0x06, 0x50, 0xF8, 0x65, 0x75, 0x23, ++ 0x70, 0x67, 0xE5, 0x22, 0x7B, 0xD9, 0xA1, 0x02, 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x70, ++ 0xF6, 0x87, 0x78, 0xE4, 0xE0, 0x02, 0x06, 0x90, 0x44, 0xE0, 0xA3, 0xF0, 0x06, 0x90, 0xF0, 0x04, ++ 0x13, 0xC4, 0xE0, 0x26, 0xFE, 0x24, 0x07, 0x54, 0x70, 0x04, 0x1D, 0x60, 0x79, 0x07, 0x90, 0x22, ++ 0x90, 0xF0, 0x03, 0x74, 0x54, 0xE0, 0x94, 0x07, 0xF0, 0x02, 0x44, 0xF0, 0xE0, 0x90, 0x07, 0x90, ++ 0x02, 0x44, 0xF0, 0x54, 0x90, 0x0D, 0x80, 0xF0, 0x01, 0x74, 0x79, 0x07, 0xE4, 0x05, 0x80, 0xF0, ++ 0xF0, 0x79, 0x07, 0x90, 0xE0, 0xA1, 0x07, 0x90, 0xE0, 0xF0, 0x08, 0x44, 0xE0, 0xF0, 0x20, 0x44, ++ 0x90, 0xF0, 0x02, 0x44, 0x44, 0xE0, 0xA2, 0x07, 0x44, 0xE0, 0xF0, 0x08, 0x44, 0xE0, 0xF0, 0x20, ++ 0x07, 0x90, 0xF0, 0x02, 0xFE, 0x54, 0xE0, 0x93, 0xA2, 0x07, 0x90, 0xF0, 0xF0, 0xF7, 0x54, 0xE0, ++ 0xF0, 0xDF, 0x54, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0x50, 0xD7, 0x11, 0x22, 0x22, 0x64, 0x75, 0x07, ++ 0x22, 0xC3, 0x65, 0x75, 0x75, 0x02, 0x60, 0x75, 0x64, 0x75, 0x88, 0x61, 0xC3, 0x65, 0x75, 0x22, ++ 0x22, 0x01, 0x66, 0x75, 0x2C, 0x60, 0x66, 0xE5, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x00, 0x79, ++ 0x23, 0x64, 0x75, 0xF4, 0x75, 0x2D, 0x65, 0x75, 0x78, 0xE4, 0x01, 0x67, 0xF6, 0x08, 0xF6, 0x82, ++ 0x89, 0x78, 0xF6, 0x08, 0x76, 0x87, 0x78, 0xF6, 0x03, 0x12, 0xFF, 0x03, 0x76, 0x80, 0x78, 0x68, ++ 0xE6, 0x76, 0x08, 0xAA, 0x60, 0xE6, 0x82, 0x78, 0xF8, 0xD1, 0x16, 0x01, 0xE0, 0x00, 0x06, 0x90, ++ 0x0F, 0x54, 0xC4, 0xFF, 0x90, 0x19, 0xE0, 0x30, 0xFF, 0xE0, 0x03, 0x06, 0x3F, 0x54, 0x13, 0x13, ++ 0x7F, 0x0D, 0xE0, 0x20, 0x48, 0x0E, 0x12, 0x80, 0x64, 0x75, 0x06, 0x50, 0xEA, 0x65, 0x75, 0x27, ++ 0x0E, 0x12, 0x10, 0xC2, 0x75, 0x06, 0x50, 0x5D, 0x65, 0x75, 0x27, 0x64, 0x65, 0x63, 0xE5, 0xEA, ++ 0xE5, 0x04, 0x70, 0x65, 0x60, 0x64, 0x65, 0x62, 0x62, 0x64, 0x85, 0x09, 0x75, 0x63, 0x65, 0x85, ++ 0x62, 0xAA, 0x01, 0x67, 0x03, 0x12, 0x63, 0xA9, 0x67, 0xF5, 0xE4, 0x27, 0x60, 0x67, 0xE5, 0x22, ++ 0x7A, 0xFF, 0x7B, 0x1F, 0x12, 0x23, 0x79, 0x20, 0x82, 0x78, 0xF4, 0x03, 0x90, 0x78, 0x0A, 0x76, ++ 0x0D, 0x90, 0x07, 0x76, 0x07, 0x44, 0xE0, 0x00, 0x20, 0x0D, 0x90, 0xF0, 0xF0, 0x07, 0x44, 0xE0, ++ 0x70, 0xE6, 0x82, 0x78, 0x78, 0x0A, 0x76, 0x52, 0x94, 0xD3, 0xE6, 0x90, 0x90, 0x23, 0x40, 0x00, ++ 0xD3, 0xE0, 0x47, 0x08, 0x1A, 0x40, 0x0A, 0x94, 0x07, 0x54, 0xE6, 0x16, 0x00, 0x0D, 0x90, 0xFF, ++ 0x4F, 0xF8, 0x54, 0xE0, 0x07, 0x54, 0xE6, 0xF0, 0x20, 0x0D, 0x90, 0xFF, 0x4F, 0xF8, 0x54, 0xE0, ++ 0xFF, 0x7B, 0x22, 0xF0, 0x29, 0x79, 0x20, 0x7A, 0xFD, 0xE6, 0x90, 0x78, 0x0D, 0x12, 0x00, 0x7C, ++ 0x7A, 0xFF, 0x7B, 0x40, 0x90, 0x33, 0x79, 0x20, 0xFD, 0xE0, 0x47, 0x08, 0x0D, 0x12, 0x00, 0x7C, ++ 0x20, 0x64, 0x75, 0x40, 0x22, 0x85, 0x65, 0x75, 0x54, 0xE6, 0x8F, 0x78, 0xE4, 0xC3, 0xFF, 0x01, ++ 0x94, 0x08, 0x74, 0x9F, 0xFC, 0x05, 0x54, 0x00, 0x13, 0xC3, 0xE6, 0x18, 0x13, 0xE6, 0x08, 0xFE, ++ 0x18, 0x6C, 0xEE, 0xFF, 0xF6, 0x08, 0xEF, 0xF6, 0x60, 0x67, 0xE5, 0x22, 0x7A, 0xFF, 0x7B, 0x3D, ++ 0x12, 0x5D, 0x79, 0x20, 0x82, 0x78, 0xF4, 0x03, 0x06, 0x90, 0x05, 0x76, 0x13, 0x13, 0xE0, 0x29, ++ 0xE0, 0x30, 0x3F, 0x54, 0x02, 0x0D, 0x90, 0x54, 0x44, 0x8F, 0x54, 0xE0, 0x0D, 0x90, 0xF0, 0x30, ++ 0x8F, 0x54, 0xE0, 0x22, 0x90, 0xF0, 0x30, 0x44, 0x54, 0xE0, 0x05, 0x0D, 0xF0, 0x20, 0x44, 0x8F, ++ 0xE0, 0x25, 0x0D, 0x90, 0x20, 0x44, 0x8F, 0x54, 0x06, 0x90, 0x22, 0xF0, 0x13, 0xFF, 0xE0, 0x29, ++ 0x30, 0x3F, 0x54, 0x13, 0x8A, 0xF1, 0x0F, 0xE0, 0xFD, 0x33, 0xFC, 0xE4, 0x20, 0x7A, 0xFF, 0x7B, ++ 0x0D, 0x12, 0x65, 0x79, 0xE6, 0x82, 0x78, 0x40, 0xFF, 0x7B, 0x0F, 0x70, 0x21, 0x79, 0x20, 0x7A, ++ 0x75, 0xF4, 0x03, 0x12, 0x65, 0x75, 0x23, 0x64, 0x0A, 0x7F, 0x22, 0x42, 0x06, 0x7D, 0x0D, 0x7E, ++ 0x10, 0xD2, 0x0D, 0x7C, 0x83, 0x8E, 0x82, 0x8F, 0x0F, 0x54, 0xC4, 0xE0, 0x40, 0x04, 0x94, 0xD3, ++ 0x46, 0x08, 0x90, 0x36, 0x50, 0x19, 0x94, 0xE0, 0x8C, 0x82, 0x8D, 0x2E, 0xC4, 0xFD, 0xE0, 0x83, ++ 0xED, 0xFC, 0x0F, 0x54, 0xEC, 0xFD, 0x0F, 0x54, 0xC4, 0x0F, 0x54, 0x14, 0xF0, 0x4D, 0xF0, 0x54, ++ 0xFF, 0xE0, 0x82, 0x8F, 0xFE, 0x0F, 0x54, 0xC4, 0xFF, 0x0F, 0x54, 0xEF, 0x0F, 0x54, 0x14, 0xEE, ++ 0x4F, 0xF0, 0x54, 0xC4, 0x90, 0x10, 0xC2, 0xF0, 0x90, 0xE0, 0x06, 0x0D, 0x90, 0xF0, 0x26, 0x0D, ++ 0x90, 0xE0, 0x0A, 0x0D, 0xA2, 0xF0, 0x2A, 0x0D, 0xFF, 0x7B, 0x22, 0x10, 0x7E, 0x79, 0x20, 0x7A, ++ 0x90, 0xF4, 0x03, 0x12, 0x01, 0x74, 0xF3, 0x07, 0xA2, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x3F, 0x74, ++ 0x44, 0xE0, 0x93, 0x07, 0x90, 0xE4, 0xF0, 0x01, 0x90, 0xF0, 0xC9, 0x01, 0x54, 0xE0, 0x03, 0x06, ++ 0x54, 0xE0, 0xF0, 0xFB, 0x06, 0x90, 0xF0, 0xDF, 0xF0, 0x80, 0x74, 0x20, 0xF0, 0xFF, 0x74, 0xA3, ++ 0xE0, 0x3E, 0x08, 0x90, 0x60, 0x75, 0xF0, 0xE4, 0x0B, 0x61, 0x75, 0x02, 0x00, 0x00, 0x22, 0x22, ++ 0x74, 0x61, 0x44, 0x09, 0x0A, 0x00, 0x0A, 0x61, 0x4F, 0x4C, 0x09, 0x09, 0x25, 0x20, 0x3A, 0x4B, ++ 0x09, 0x00, 0x0A, 0x64, 0x4C, 0x56, 0x4C, 0x09, 0x64, 0x25, 0x20, 0x3A, 0x09, 0x09, 0x00, 0x0A, ++ 0x3A, 0x52, 0x57, 0x50, 0x20, 0x44, 0x25, 0x20, 0x09, 0x09, 0x00, 0x0A, 0x3A, 0x52, 0x4E, 0x53, ++ 0x20, 0x64, 0x25, 0x20, 0x00, 0x0A, 0x42, 0x64, 0x52, 0x46, 0x09, 0x09, 0x25, 0x20, 0x3A, 0x4F, ++ 0x70, 0x70, 0x20, 0x44, 0x09, 0x00, 0x0A, 0x6D, 0x51, 0x45, 0x4C, 0x09, 0x25, 0x20, 0x00, 0x3A, ++ 0x00, 0x0A, 0x00, 0x44, 0x46, 0x44, 0x09, 0x09, 0x09, 0x00, 0x3A, 0x45, 0x44, 0x41, 0x42, 0x09, ++ 0x47, 0x49, 0x53, 0x5F, 0x09, 0x09, 0x00, 0x0A, 0x43, 0x53, 0x6F, 0x4C, 0x09, 0x00, 0x0A, 0x52, ++ 0x53, 0x6F, 0x4C, 0x09, 0x22, 0x22, 0x00, 0x0A, 0x60, 0x66, 0xE5, 0x22, 0x7A, 0xFF, 0x7B, 0x25, ++ 0x12, 0x00, 0x79, 0x20, 0x06, 0x90, 0xF4, 0x03, 0x01, 0x44, 0xE0, 0x35, 0x8A, 0x78, 0xE4, 0xF0, ++ 0x78, 0xF6, 0x08, 0xF6, 0x72, 0x75, 0xF6, 0x88, 0x76, 0x73, 0x75, 0x20, 0x75, 0x20, 0x74, 0x75, ++ 0x07, 0x90, 0x77, 0x75, 0x14, 0x60, 0xE0, 0x91, 0xE0, 0x8F, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, ++ 0x03, 0x74, 0x91, 0x07, 0x8F, 0x07, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0xC9, 0x01, 0x90, ++ 0xF0, 0xFF, 0x02, 0x44, 0x07, 0x90, 0xFE, 0xE0, 0x13, 0xC4, 0xE0, 0x8B, 0xFD, 0x01, 0x54, 0x13, ++ 0x54, 0x13, 0xC4, 0xEE, 0x54, 0xEF, 0xFE, 0x01, 0x4D, 0xEE, 0xFF, 0xDF, 0x33, 0xC4, 0x01, 0x54, ++ 0x90, 0x4F, 0xE0, 0x54, 0xE0, 0xF0, 0xC9, 0x01, 0x8B, 0x07, 0x90, 0xFF, 0x54, 0x13, 0xC4, 0xE0, ++ 0x13, 0xEF, 0xFE, 0x01, 0x01, 0x54, 0x13, 0x13, 0xF7, 0x54, 0xEF, 0xFD, 0x54, 0x4E, 0xED, 0xFF, ++ 0x33, 0x33, 0x33, 0x01, 0x90, 0x4F, 0xF8, 0x54, 0xE0, 0xF0, 0xC9, 0x01, 0x8B, 0x07, 0x90, 0xFF, ++ 0x54, 0x13, 0xC3, 0xE0, 0xC4, 0xEF, 0xFE, 0x01, 0xEF, 0xFD, 0x01, 0x54, 0xED, 0xFF, 0xEF, 0x54, ++ 0xFE, 0x01, 0x54, 0x4E, 0x4F, 0xF0, 0x54, 0xC4, 0xF0, 0xC9, 0x01, 0x90, 0x74, 0x8B, 0x07, 0x90, ++ 0x10, 0xC2, 0xF0, 0x62, 0x40, 0x5D, 0x0E, 0x12, 0x65, 0x78, 0x74, 0x20, 0x74, 0x04, 0x70, 0x75, ++ 0x60, 0x74, 0x65, 0x20, 0x65, 0x77, 0x74, 0x14, 0x74, 0x04, 0x70, 0x75, 0x70, 0x74, 0x65, 0x20, ++ 0x40, 0xCA, 0x31, 0x78, 0x50, 0x73, 0x71, 0x04, 0xC2, 0xEC, 0xC2, 0x70, 0x47, 0x07, 0x90, 0xEE, ++ 0xF0, 0xFB, 0x54, 0xE0, 0xF0, 0xEF, 0x54, 0xE0, 0x74, 0x66, 0x07, 0x90, 0x07, 0x90, 0xF0, 0xFF, ++ 0x0D, 0x90, 0xF0, 0x68, 0xDF, 0x54, 0xE0, 0x01, 0x21, 0x0D, 0x90, 0xF0, 0xF0, 0xDF, 0x54, 0xE0, ++ 0xE0, 0x01, 0x0D, 0x90, 0x90, 0xF0, 0xEF, 0x54, 0x54, 0xE0, 0x21, 0x0D, 0x07, 0x90, 0xF0, 0xEF, ++ 0x02, 0x44, 0xE0, 0xFE, 0xF7, 0x54, 0xE0, 0xF0, 0xFD, 0x07, 0x90, 0xF0, 0xF0, 0x02, 0x44, 0xE0, ++ 0xF0, 0xF7, 0x54, 0xE0, 0xE0, 0xA6, 0x07, 0x90, 0x90, 0xF0, 0xFE, 0x54, 0x44, 0xE0, 0xFB, 0x07, ++ 0x44, 0xE0, 0xF0, 0x01, 0x06, 0x90, 0xF0, 0x10, 0x01, 0x44, 0xE0, 0x35, 0x7F, 0x02, 0x7E, 0xF0, ++ 0x8F, 0x60, 0x8E, 0x83, 0x8F, 0x5E, 0x8E, 0x61, 0x17, 0x30, 0x22, 0x5F, 0x78, 0x5D, 0x61, 0x02, ++ 0x18, 0xE6, 0x06, 0x8B, 0x78, 0x06, 0x01, 0x70, 0x01, 0x64, 0xE6, 0x8B, 0x02, 0x60, 0x46, 0x18, ++ 0x08, 0x90, 0xBA, 0x41, 0x25, 0xF5, 0xE0, 0x59, 0xE0, 0x5A, 0x08, 0x90, 0x26, 0xE5, 0x26, 0xF5, ++ 0x06, 0x78, 0x25, 0xAE, 0x13, 0xE7, 0xA2, 0xCE, 0xF8, 0xD8, 0x13, 0xCE, 0xE5, 0x06, 0xAC, 0xFD, ++ 0x78, 0x25, 0xAE, 0x26, 0xE7, 0xA2, 0xCE, 0x05, 0xD8, 0x13, 0xCE, 0x13, 0xEE, 0xFF, 0x2D, 0xF8, ++ 0x25, 0xEF, 0xFE, 0x3C, 0xEE, 0x26, 0xF5, 0x26, 0x25, 0xF5, 0x25, 0x35, 0xE0, 0x46, 0x08, 0x90, ++ 0x7C, 0xED, 0x7D, 0xFF, 0x8F, 0xA6, 0x71, 0x21, 0x90, 0x26, 0xAF, 0x27, 0xF0, 0xEF, 0x20, 0x06, ++ 0x94, 0xD3, 0x27, 0xE5, 0x40, 0x27, 0xAF, 0x0E, 0xEF, 0x0E, 0x7F, 0x02, 0x54, 0xC4, 0x0F, 0x54, ++ 0x06, 0x90, 0xFF, 0xF0, 0x0F, 0x54, 0xE0, 0x21, 0x90, 0xE4, 0xF0, 0x4F, 0xE0, 0xF0, 0x2E, 0x08, ++ 0x40, 0x44, 0x9F, 0x54, 0x31, 0x08, 0x90, 0xF0, 0x7B, 0x28, 0xF5, 0xE0, 0x79, 0x20, 0x7A, 0xFF, ++ 0x08, 0x83, 0x78, 0x07, 0x86, 0x18, 0xE6, 0x06, 0x06, 0x01, 0x70, 0x04, 0x0D, 0x12, 0xFD, 0x14, ++ 0x7A, 0xFF, 0x7B, 0x40, 0xE5, 0x13, 0x79, 0x20, 0x08, 0x90, 0xFE, 0x28, 0xEE, 0xFD, 0xE0, 0x32, ++ 0x0D, 0x12, 0xED, 0xFC, 0x7A, 0xFF, 0x7B, 0x40, 0x90, 0x1E, 0x79, 0x20, 0xFD, 0xE0, 0x47, 0x08, ++ 0x0D, 0x12, 0x00, 0x7C, 0x7A, 0xFF, 0x7B, 0x40, 0xE5, 0x2A, 0x79, 0x20, 0x00, 0x7C, 0xFD, 0x27, ++ 0x7B, 0x40, 0x0D, 0x12, 0x79, 0x20, 0x7A, 0xFF, 0xAC, 0x26, 0xAD, 0x38, 0x40, 0x0D, 0x12, 0x25, ++ 0x94, 0xD3, 0x28, 0xE5, 0x61, 0x02, 0x40, 0x01, 0x8B, 0x78, 0x22, 0x5D, 0x18, 0x02, 0x64, 0xE6, ++ 0x7B, 0x44, 0x70, 0x46, 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x47, 0x2E, 0x08, 0x90, 0xE4, ++ 0x9F, 0x54, 0xE0, 0xF0, 0x24, 0xF5, 0xE4, 0xF0, 0x0F, 0x54, 0x24, 0xE5, 0x2E, 0x08, 0x90, 0xFF, ++ 0x4F, 0xF0, 0x54, 0xE0, 0x7A, 0xFF, 0x7B, 0xF0, 0x90, 0x4E, 0x79, 0x20, 0xFE, 0xE0, 0x31, 0x08, ++ 0xE0, 0x32, 0x08, 0x90, 0xAC, 0xFF, 0xED, 0xFD, 0x40, 0x0D, 0x12, 0x06, 0x24, 0xE5, 0x24, 0x05, ++ 0x40, 0x0A, 0x94, 0xC3, 0x78, 0x4D, 0x80, 0xD3, 0x03, 0x64, 0xE6, 0x8B, 0x4D, 0x70, 0x46, 0x18, ++ 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x54, 0x79, 0x08, 0x90, 0xE4, 0xF4, 0x54, 0xE0, 0xF0, 0x2E, ++ 0xF0, 0x20, 0x44, 0x9F, 0xE5, 0x24, 0xF5, 0xE4, 0xFF, 0x0F, 0x54, 0x24, 0xE0, 0x2E, 0x08, 0x90, ++ 0xF0, 0x4F, 0xF0, 0x54, 0x20, 0x7A, 0xFF, 0x7B, 0x08, 0x90, 0x4E, 0x79, 0x90, 0xFE, 0xE0, 0x31, ++ 0xFD, 0xE0, 0x32, 0x08, 0x06, 0xAC, 0xFF, 0xED, 0x05, 0x40, 0x0D, 0x12, 0xC3, 0x24, 0xE5, 0x24, ++ 0xD3, 0x40, 0x08, 0x94, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x52, 0x79, 0x46, 0x08, 0x90, 0xF4, ++ 0x3C, 0x94, 0xD3, 0xE0, 0xFF, 0x7B, 0x0B, 0x40, 0x5B, 0x79, 0x20, 0x7A, 0xD3, 0xF4, 0x03, 0x12, ++ 0x90, 0x22, 0xC3, 0x22, 0xD3, 0xE0, 0xA4, 0x07, 0x08, 0x40, 0xA0, 0x94, 0x20, 0x7A, 0xFF, 0x7B, ++ 0x17, 0x80, 0x66, 0x79, 0xE0, 0x47, 0x08, 0x90, 0x50, 0x03, 0x94, 0xC3, 0xE6, 0x88, 0x78, 0x13, ++ 0x40, 0x0A, 0x94, 0x06, 0x7A, 0xFF, 0x7B, 0x0F, 0x12, 0x6F, 0x79, 0x20, 0x22, 0xD3, 0xF4, 0x03, ++ 0xF6, 0x88, 0x78, 0xE4, 0x29, 0x8C, 0x22, 0xC3, 0xFB, 0xE4, 0x2A, 0x8D, 0x83, 0xF5, 0x82, 0xF5, ++ 0x80, 0x64, 0xEF, 0xC3, 0x02, 0x50, 0x81, 0x94, 0xEF, 0xD3, 0x01, 0x7F, 0xBF, 0x94, 0x80, 0x64, ++ 0x3F, 0x7F, 0x02, 0x40, 0x04, 0xF0, 0x75, 0xEF, 0xF0, 0xAC, 0xFD, 0xA4, 0x09, 0xE7, 0x20, 0xED, ++ 0xFD, 0xE0, 0x25, 0x0B, 0x80, 0xFC, 0x33, 0xEC, 0xAF, 0xFA, 0xE4, 0xF3, 0x12, 0x04, 0xAE, 0x05, ++ 0x06, 0xAC, 0xC0, 0x02, 0x78, 0xED, 0x07, 0xAD, 0x13, 0xC3, 0xCE, 0x07, 0xF9, 0xD8, 0x13, 0xCE, ++ 0xC3, 0x06, 0xAC, 0xFD, 0x40, 0x01, 0x94, 0xEC, 0x9A, 0x07, 0x74, 0x24, 0x7E, 0x01, 0x74, 0xFF, ++ 0x08, 0x07, 0xA8, 0x00, 0x33, 0xC3, 0x05, 0x80, 0xD8, 0xCE, 0x33, 0xCE, 0xF5, 0x82, 0x25, 0xF9, ++ 0x83, 0x35, 0xEE, 0x82, 0xC3, 0xEC, 0x83, 0xF5, 0x13, 0xED, 0xFC, 0x13, 0x08, 0xBA, 0x0A, 0xFD, ++ 0x05, 0x74, 0xC3, 0xBA, 0xFE, 0xEF, 0xFF, 0x9B, 0xF5, 0x82, 0x25, 0xE4, 0x83, 0x35, 0xEE, 0x82, ++ 0x00, 0x7C, 0x83, 0xF5, 0x82, 0xAF, 0x06, 0x7D, 0xC0, 0x02, 0x12, 0xFE, 0x82, 0x8F, 0x83, 0x8E, ++ 0x95, 0x82, 0xE5, 0xD3, 0x95, 0x83, 0xE5, 0x2A, 0xE4, 0x07, 0x40, 0x29, 0x82, 0xF5, 0x83, 0xF5, ++ 0xE5, 0xC3, 0x0D, 0x80, 0xF5, 0x82, 0x95, 0x2A, 0x95, 0x29, 0xE5, 0x82, 0xE5, 0x83, 0xF5, 0x83, ++ 0x75, 0x82, 0xF5, 0x83, 0x22, 0xFF, 0x00, 0x83, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, ++ 0x30, 0x30, 0x31, 0x09, 0x0A, 0x58, 0x54, 0x62, 0x65, 0x53, 0x09, 0x00, 0x0A, 0x70, 0x75, 0x74, ++ 0x61, 0x57, 0x09, 0x00, 0x0A, 0x50, 0x74, 0x69, 0x4D, 0x09, 0x09, 0x00, 0x58, 0x00, 0x49, 0x44, ++ 0x09, 0x00, 0x0A, 0x00, 0x0A, 0x43, 0x47, 0x41, 0x41, 0x09, 0x09, 0x00, 0x25, 0x3D, 0x43, 0x47, ++ 0x50, 0x00, 0x20, 0x64, 0x25, 0x3D, 0x52, 0x57, 0x09, 0x00, 0x0A, 0x64, 0x0A, 0x30, 0x4B, 0x4F, ++ 0x4C, 0x09, 0x09, 0x00, 0x25, 0x20, 0x3A, 0x43, 0x09, 0x00, 0x0A, 0x64, 0x0A, 0x31, 0x4B, 0x4F, ++ 0x4B, 0x4F, 0x09, 0x00, 0x09, 0x00, 0x0A, 0x32, 0x0A, 0x33, 0x4B, 0x4F, 0x4B, 0x4F, 0x09, 0x00, ++ 0x09, 0x09, 0x0A, 0x34, 0x00, 0x64, 0x25, 0x00, 0x61, 0x72, 0x54, 0x09, 0x00, 0x0A, 0x6B, 0x63, ++ 0x6E, 0x79, 0x53, 0x09, 0x09, 0x00, 0x0A, 0x63, 0x6E, 0x77, 0x6F, 0x44, 0x45, 0x09, 0x00, 0x0A, ++ 0x0A, 0x74, 0x69, 0x78, 0x60, 0x71, 0xE5, 0x00, 0x7A, 0xFF, 0x7B, 0x10, 0x12, 0x3B, 0x79, 0x20, ++ 0x9B, 0x78, 0xF4, 0x03, 0x02, 0x12, 0x05, 0x76, 0x50, 0xD7, 0x11, 0x60, 0x22, 0x6E, 0x75, 0x07, ++ 0x22, 0xBD, 0x6F, 0x75, 0x70, 0xE6, 0x9B, 0x78, 0x5D, 0x09, 0x90, 0x2D, 0x9F, 0x54, 0xE0, 0xF0, ++ 0x7B, 0xF0, 0x40, 0x44, 0x79, 0x20, 0x7A, 0xFF, 0x60, 0x09, 0x90, 0x41, 0x09, 0x90, 0xFE, 0xE0, ++ 0xEE, 0xFD, 0xE0, 0x61, 0x0D, 0x12, 0xED, 0xFC, 0x24, 0x6E, 0x75, 0x40, 0x78, 0xBC, 0x6F, 0x75, ++ 0x08, 0x01, 0x76, 0x9E, 0x90, 0x22, 0xF4, 0x76, 0xFF, 0xE0, 0x76, 0x09, 0x94, 0x80, 0x64, 0xD3, ++ 0x78, 0x0C, 0x40, 0x85, 0x0A, 0x94, 0xE6, 0xA1, 0x80, 0x06, 0x03, 0x50, 0xC3, 0x22, 0xC3, 0x0E, ++ 0x94, 0x80, 0x64, 0xEF, 0xE4, 0x04, 0x50, 0x83, 0xD3, 0xF6, 0xA1, 0x78, 0x60, 0x71, 0xE5, 0x22, ++ 0x7A, 0xFF, 0x7B, 0x69, 0x12, 0x11, 0x79, 0x20, 0x0D, 0x90, 0xF4, 0x03, 0xF8, 0x54, 0xE0, 0x40, ++ 0x60, 0x0D, 0x90, 0xF0, 0xF0, 0xF8, 0x54, 0xE0, 0x0C, 0x76, 0xA5, 0x78, 0x90, 0x1C, 0x76, 0x08, ++ 0xFF, 0xE0, 0x8A, 0x0D, 0xE0, 0x8B, 0x0D, 0x90, 0x07, 0x90, 0xFF, 0x6F, 0xE4, 0xFD, 0xE0, 0x0C, ++ 0x6D, 0xEF, 0xF6, 0x08, 0x78, 0xE4, 0xF6, 0x08, 0x0D, 0x90, 0xF6, 0xA1, 0xF0, 0xC0, 0x74, 0x89, ++ 0xE0, 0x6F, 0x09, 0x90, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0x08, 0x44, 0x90, 0xF0, 0x20, 0x44, ++ 0x54, 0xE0, 0x73, 0x09, 0xF0, 0x20, 0x44, 0x0F, 0xE0, 0x72, 0x09, 0x90, 0xE0, 0xF0, 0x70, 0x44, ++ 0x90, 0xF0, 0x80, 0x44, 0x54, 0xE0, 0x6F, 0x09, 0x06, 0x90, 0xF0, 0xF7, 0x54, 0xC4, 0xE0, 0x40, ++ 0x04, 0xE0, 0x30, 0x0F, 0x1E, 0x80, 0x06, 0x51, 0xE0, 0x67, 0x06, 0x90, 0xE0, 0x20, 0xE0, 0x20, ++ 0x01, 0x54, 0x13, 0x13, 0x63, 0x06, 0x90, 0xFF, 0x13, 0x13, 0xFE, 0xE0, 0x60, 0x6F, 0x01, 0x54, ++ 0x67, 0x06, 0x90, 0x05, 0xA5, 0x78, 0x09, 0x51, 0x76, 0x08, 0x0C, 0x76, 0x7F, 0x5C, 0x80, 0x1C, ++ 0x48, 0x0E, 0x12, 0xA5, 0xA5, 0x78, 0x55, 0x50, 0x76, 0x08, 0x0C, 0x76, 0x76, 0x09, 0x90, 0x1C, ++ 0x05, 0x94, 0xC3, 0xE0, 0xA8, 0x78, 0x24, 0x50, 0xFF, 0x01, 0x54, 0xE6, 0xE0, 0x63, 0x06, 0x90, ++ 0x54, 0x13, 0x13, 0xFD, 0x01, 0x70, 0x6F, 0x01, 0x90, 0x07, 0x60, 0xE4, 0x44, 0xE0, 0x75, 0x06, ++ 0xA8, 0x78, 0xF0, 0x08, 0x10, 0x92, 0x13, 0xE6, 0xFF, 0x7B, 0x12, 0x51, 0x19, 0x79, 0x20, 0x7A, ++ 0x90, 0xF4, 0x03, 0x12, 0xFF, 0xE0, 0x63, 0x06, 0x3F, 0x54, 0x13, 0x13, 0x7B, 0x09, 0xE0, 0x30, ++ 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x1F, 0x11, 0xEE, 0x03, 0x12, 0x75, 0x06, 0x40, 0xD7, ++ 0x6F, 0x75, 0x26, 0x6E, 0x06, 0x90, 0x22, 0x98, 0x13, 0xFF, 0xE0, 0x63, 0x13, 0x3F, 0x54, 0x13, ++ 0x06, 0x90, 0x10, 0x92, 0xE0, 0x30, 0xE0, 0x67, 0x1A, 0x10, 0x30, 0x03, 0xE0, 0x67, 0x06, 0x90, ++ 0x90, 0x4B, 0xE0, 0x20, 0xFE, 0xE0, 0x66, 0x06, 0x02, 0x78, 0xE0, 0xA3, 0xCE, 0x13, 0xC3, 0xCE, ++ 0x20, 0xF9, 0xD8, 0x13, 0x10, 0xC2, 0x38, 0xE0, 0x74, 0x41, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x0F, ++ 0x90, 0xF0, 0x04, 0x61, 0x54, 0xE0, 0xF1, 0x07, 0xF0, 0x80, 0x44, 0x3F, 0xF0, 0x30, 0x44, 0xE0, ++ 0xE0, 0xF2, 0x07, 0x90, 0xE0, 0xF0, 0xC0, 0x44, 0x20, 0x44, 0xCF, 0x54, 0x4C, 0x0D, 0x90, 0xF0, ++ 0x90, 0xF0, 0x36, 0x74, 0x15, 0x74, 0x6C, 0x0D, 0xC6, 0x01, 0x90, 0xF0, 0x10, 0xD2, 0x36, 0x80, ++ 0x74, 0x61, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x0F, 0x90, 0xF0, 0x04, 0x41, 0x44, 0xE0, 0xF1, 0x07, ++ 0x54, 0xE0, 0xF0, 0xC0, 0xF0, 0x20, 0x44, 0xCF, 0xE0, 0xF2, 0x07, 0x90, 0x80, 0x44, 0x3F, 0x54, ++ 0x30, 0x44, 0xE0, 0xF0, 0x6C, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x36, 0x74, 0x15, 0x74, 0x4C, 0x0D, ++ 0xC7, 0x01, 0x90, 0xF0, 0x6D, 0x09, 0x90, 0xE0, 0xE4, 0x10, 0xA2, 0xF0, 0x25, 0x01, 0x54, 0x33, ++ 0xFF, 0xE0, 0x25, 0xE0, 0xE0, 0x63, 0x06, 0x90, 0xF0, 0x4F, 0xFB, 0x54, 0x7A, 0xFF, 0x7B, 0x22, ++ 0x12, 0x77, 0x79, 0x20, 0x90, 0xE4, 0xF4, 0x03, 0x90, 0xF0, 0xCB, 0x01, 0xF0, 0xE0, 0x42, 0x06, ++ 0xFB, 0x54, 0xE0, 0xA3, 0x9C, 0x78, 0xE4, 0xF0, 0x90, 0xF6, 0x08, 0xF6, 0x44, 0xE0, 0xDC, 0x07, ++ 0x06, 0x90, 0xF0, 0x01, 0x54, 0xC4, 0xE0, 0x40, 0x23, 0xE0, 0x20, 0x0F, 0x54, 0x13, 0xC4, 0xE0, ++ 0x1B, 0xE0, 0x30, 0x07, 0xE0, 0xA3, 0xFE, 0xE0, 0xC3, 0xCE, 0x06, 0x78, 0xD8, 0x13, 0xCE, 0x13, ++ 0x0B, 0xE0, 0x20, 0xF9, 0x11, 0x50, 0xD7, 0x11, 0x75, 0x20, 0x6E, 0x75, 0x78, 0x22, 0xFD, 0x6F, ++ 0x60, 0x16, 0xE6, 0xA0, 0x40, 0xD7, 0x11, 0x0B, 0x20, 0x6E, 0x75, 0x07, 0x22, 0x85, 0x6F, 0x75, ++ 0x75, 0x27, 0x6E, 0x75, 0x7B, 0x22, 0xDE, 0x6F, 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x09, ++ 0x51, 0x65, 0x02, 0x12, 0x20, 0x6E, 0x75, 0x06, 0x22, 0xFD, 0x6F, 0x75, 0x20, 0x7A, 0xFF, 0x7B, ++ 0x03, 0x12, 0x68, 0x79, 0x76, 0x09, 0x90, 0xF4, 0xF6, 0xA2, 0x78, 0xE0, 0x52, 0x09, 0x90, 0xE4, ++ 0x53, 0x09, 0x90, 0xF0, 0x44, 0xE3, 0x54, 0xE0, 0x09, 0x90, 0xF0, 0x08, 0xF0, 0x02, 0x74, 0x57, ++ 0xE0, 0x56, 0x09, 0x90, 0x90, 0xF0, 0xFB, 0x54, 0x37, 0x74, 0x85, 0x09, 0x86, 0x09, 0x90, 0xF0, ++ 0x90, 0xF0, 0x05, 0x74, 0xE4, 0xE0, 0x87, 0x09, 0x11, 0xF0, 0xC8, 0x74, 0x75, 0x07, 0x50, 0xD7, ++ 0x6F, 0x75, 0x22, 0x6E, 0x6E, 0x75, 0x22, 0xBD, 0x4B, 0x6F, 0x75, 0x25, 0x60, 0x71, 0xE5, 0x22, ++ 0x7A, 0xFF, 0x7B, 0x4A, 0x12, 0x57, 0x79, 0x20, 0x9B, 0x78, 0xF4, 0x03, 0x09, 0x90, 0x64, 0x76, ++ 0xF0, 0x0D, 0x74, 0x50, 0xE0, 0x72, 0x09, 0x90, 0x90, 0xF0, 0x07, 0x44, 0x44, 0xE0, 0x71, 0x09, ++ 0x09, 0x90, 0xF0, 0x03, 0xF0, 0x02, 0x74, 0x52, 0xE0, 0x53, 0x09, 0x90, 0x14, 0x44, 0xE3, 0x54, ++ 0x57, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x02, 0x74, 0x37, 0x74, 0x85, 0x09, 0x86, 0x09, 0x90, 0xF0, ++ 0x90, 0xF0, 0x03, 0x74, 0xE4, 0xE0, 0x87, 0x09, 0x11, 0xF0, 0xC8, 0x74, 0x75, 0x07, 0x50, 0xD7, ++ 0x6F, 0x75, 0x22, 0x6E, 0x9B, 0x78, 0x22, 0xBD, 0x75, 0x06, 0x70, 0xE6, 0x6F, 0x75, 0x27, 0x6E, ++ 0x71, 0xE5, 0x22, 0x13, 0xFF, 0x7B, 0x2E, 0x60, 0x51, 0x79, 0x20, 0x7A, 0x78, 0xF4, 0x03, 0x12, ++ 0x90, 0x14, 0x76, 0x9B, 0x54, 0xE0, 0x53, 0x09, 0x09, 0x90, 0xF0, 0xFD, 0xFB, 0x54, 0xE0, 0x56, ++ 0x5A, 0x09, 0x90, 0xF0, 0xF0, 0xFD, 0x54, 0xE0, 0x74, 0x85, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x37, ++ 0xF0, 0x03, 0x74, 0x86, 0xD7, 0x11, 0x6C, 0x91, 0x9E, 0x7F, 0x07, 0x40, 0x50, 0x48, 0x0E, 0x12, ++ 0x22, 0x6E, 0x75, 0x07, 0x22, 0xBD, 0x6F, 0x75, 0x70, 0xE6, 0x9B, 0x78, 0x75, 0x09, 0x90, 0x2E, ++ 0x0D, 0x94, 0xC3, 0xE0, 0x6E, 0x75, 0x08, 0x50, 0x8D, 0x6F, 0x75, 0x23, 0x6E, 0x75, 0x06, 0x80, ++ 0xBC, 0x6F, 0x75, 0x24, 0x5D, 0x09, 0x90, 0xE4, 0x9F, 0x54, 0xE0, 0xF0, 0x90, 0xF0, 0x40, 0x44, ++ 0x70, 0xE0, 0x60, 0x09, 0x20, 0x6E, 0x75, 0x06, 0x22, 0x85, 0x6F, 0x75, 0x74, 0x50, 0x09, 0x90, ++ 0x02, 0x7D, 0xF0, 0x0D, 0x90, 0x0F, 0x54, 0xED, 0x90, 0xF0, 0x5D, 0x09, 0xF5, 0xE0, 0x60, 0x09, ++ 0x61, 0x09, 0x90, 0x24, 0xE5, 0x25, 0xF5, 0xE0, 0x95, 0x33, 0xFF, 0x24, 0xE5, 0xC3, 0xFE, 0xE0, ++ 0x25, 0xF5, 0x9F, 0x25, 0xF5, 0x9E, 0x24, 0xE5, 0x5D, 0x09, 0x90, 0x24, 0xF0, 0x10, 0x44, 0xE0, ++ 0xE5, 0x5E, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x24, 0xF0, 0x25, 0xE5, 0x5F, 0x5D, 0x09, 0x90, 0xE4, ++ 0x0A, 0xBD, 0x0D, 0xF0, 0x50, 0x09, 0x90, 0xBF, 0x22, 0xF0, 0x05, 0x74, 0x64, 0x60, 0x71, 0xE5, ++ 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x4B, 0x79, 0x76, 0x9B, 0x78, 0xF4, 0x50, 0x09, 0x90, 0x0A, ++ 0x90, 0xF0, 0x0D, 0x74, 0x04, 0x74, 0x52, 0x09, 0x53, 0x09, 0x90, 0xF0, 0x44, 0xE3, 0x54, 0xE0, ++ 0x44, 0xE0, 0xF0, 0x10, 0x09, 0x90, 0xF0, 0x02, 0xFB, 0x54, 0xE0, 0x56, 0x57, 0x09, 0x90, 0xF0, ++ 0x90, 0xF0, 0x03, 0x74, 0x44, 0xE0, 0x58, 0x09, 0x09, 0x90, 0xF0, 0x01, 0xE7, 0x54, 0xE0, 0x5A, ++ 0x01, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xF0, 0x5B, 0x09, 0x90, 0xF0, 0xF0, 0xCD, 0x74, 0xE0, ++ 0x74, 0x85, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x34, 0xF0, 0x03, 0x74, 0x86, 0xE0, 0x87, 0x09, 0x90, ++ 0xF0, 0xC8, 0x74, 0xE4, 0x07, 0x40, 0xD7, 0x11, 0x0E, 0x12, 0x9E, 0x7F, 0x75, 0x07, 0x50, 0x48, ++ 0x6F, 0x75, 0x22, 0x6E, 0x9B, 0x78, 0x22, 0xBD, 0x90, 0x0F, 0x70, 0xE6, 0xC3, 0xE0, 0x75, 0x09, ++ 0x06, 0x50, 0x17, 0x94, 0x75, 0x23, 0x6E, 0x75, 0xE5, 0x22, 0xF2, 0x6F, 0xA1, 0x02, 0x70, 0x71, ++ 0x7A, 0xFF, 0x7B, 0xD3, 0x12, 0x70, 0x79, 0x20, 0x78, 0xE4, 0xF4, 0x03, 0x06, 0x90, 0xF6, 0xA0, ++ 0xA3, 0xF0, 0xE0, 0x42, 0xF0, 0x04, 0x44, 0xE0, 0xE0, 0x66, 0x06, 0x90, 0x07, 0x54, 0x13, 0xC4, ++ 0x1D, 0x60, 0xFE, 0x24, 0x90, 0x22, 0x70, 0x04, 0x03, 0x74, 0xC2, 0x07, 0xDD, 0x07, 0x90, 0xF0, ++ 0x44, 0xF0, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x02, 0xF0, 0x54, 0xE0, 0xD9, 0x80, 0xF0, 0x02, 0x44, ++ 0xC2, 0x07, 0x90, 0x0D, 0x80, 0xF0, 0x01, 0x74, 0x07, 0x90, 0xE4, 0x05, 0x07, 0x90, 0xF0, 0xC2, ++ 0x08, 0x44, 0xE0, 0xEA, 0x20, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xEB, 0x07, 0x90, 0xF0, ++ 0xF0, 0x08, 0x44, 0xE0, 0xF0, 0x20, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xE0, 0xDC, 0x07, 0x90, ++ 0x90, 0xF0, 0xFE, 0x54, 0x54, 0xE0, 0xEB, 0x07, 0x54, 0xE0, 0xF0, 0xF7, 0x54, 0xE0, 0xF0, 0xDF, ++ 0x11, 0x22, 0xF0, 0xFD, 0x75, 0x07, 0x50, 0xD7, 0x6F, 0x75, 0x22, 0x6E, 0x6A, 0x75, 0x22, 0xBD, ++ 0x92, 0x6B, 0x75, 0x02, 0x75, 0x22, 0x6E, 0x75, 0x70, 0x75, 0xBD, 0x6F, 0x70, 0xE5, 0x22, 0x01, ++ 0xFF, 0x7B, 0x2C, 0x60, 0x00, 0x79, 0x20, 0x7A, 0x75, 0xF4, 0x03, 0x12, 0x6F, 0x75, 0x23, 0x6E, ++ 0x01, 0x71, 0x75, 0x27, 0xF6, 0x9B, 0x78, 0xE4, 0xF6, 0x08, 0xF6, 0x08, 0x78, 0xF6, 0xA2, 0x78, ++ 0xFF, 0x03, 0x76, 0xA0, 0x78, 0x68, 0x00, 0x12, 0x08, 0xAA, 0x76, 0x99, 0x9B, 0x78, 0xE6, 0x76, ++ 0x16, 0x01, 0x60, 0xE6, 0x06, 0x90, 0x77, 0xD1, 0xC4, 0xFF, 0xE0, 0x40, 0xE0, 0x30, 0x0F, 0x54, ++ 0x43, 0x06, 0x90, 0x19, 0x13, 0x13, 0xFF, 0xE0, 0xE0, 0x20, 0x3F, 0x54, 0x12, 0x99, 0x7F, 0x0D, ++ 0x06, 0x50, 0x48, 0x0E, 0x75, 0x27, 0x6E, 0x75, 0x10, 0xD2, 0xDE, 0x6F, 0x50, 0x5D, 0x0E, 0x12, ++ 0x27, 0x6E, 0x75, 0x06, 0xE5, 0xDE, 0x6F, 0x75, 0x70, 0x6F, 0x65, 0x6D, 0x65, 0x6C, 0xE5, 0x04, ++ 0x85, 0x09, 0x60, 0x6E, 0x6F, 0x85, 0x6C, 0x6E, 0x01, 0x71, 0x75, 0x6D, 0x6D, 0xA9, 0x6C, 0xAA, ++ 0xE4, 0x27, 0x03, 0x12, 0x78, 0x22, 0x71, 0xF5, 0x01, 0x54, 0xE6, 0xA8, 0x9F, 0xE4, 0xC3, 0xFF, ++ 0x00, 0x94, 0x08, 0x74, 0x18, 0xFC, 0x05, 0x54, 0xFE, 0x13, 0xC3, 0xE6, 0xFF, 0x13, 0xE6, 0x08, ++ 0xF6, 0x18, 0x6C, 0xEE, 0x22, 0xF6, 0x08, 0xEF, 0x1F, 0x60, 0x71, 0xE5, 0x20, 0x7A, 0xFF, 0x7B, ++ 0x03, 0x12, 0x23, 0x79, 0x76, 0x9B, 0x78, 0xF4, 0x76, 0xA9, 0x78, 0x0A, 0x40, 0x0D, 0x90, 0x07, ++ 0xF0, 0x07, 0x44, 0xE0, 0xE0, 0x60, 0x0D, 0x90, 0x78, 0xF0, 0x07, 0x44, 0x52, 0x70, 0xE6, 0x9B, ++ 0xA9, 0x78, 0x0A, 0x76, 0x00, 0x94, 0xD3, 0xE6, 0x09, 0x90, 0x23, 0x40, 0x94, 0xD3, 0xE0, 0x76, ++ 0x16, 0x1A, 0x40, 0x0A, 0xFF, 0x07, 0x54, 0xE6, 0xE0, 0x40, 0x0D, 0x90, 0xF0, 0x4F, 0xF8, 0x54, ++ 0xFF, 0x07, 0x54, 0xE6, 0xE0, 0x60, 0x0D, 0x90, 0xF0, 0x4F, 0xF8, 0x54, 0x7A, 0xFF, 0x7B, 0x22, ++ 0x78, 0x29, 0x79, 0x20, 0x7C, 0xFD, 0xE6, 0xA9, 0x40, 0x0D, 0x12, 0x00, 0x20, 0x7A, 0xFF, 0x7B, ++ 0x09, 0x90, 0x33, 0x79, 0x7C, 0xFD, 0xE0, 0x76, 0x40, 0x0D, 0x12, 0x00, 0x75, 0x20, 0x6E, 0x75, ++ 0xE5, 0x22, 0x85, 0x6F, 0x7B, 0x3D, 0x60, 0x71, 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x5D, ++ 0x05, 0x76, 0x9B, 0x78, 0xE0, 0x69, 0x06, 0x90, 0x3F, 0x54, 0x13, 0x13, 0x90, 0x4E, 0xE0, 0x30, ++ 0x54, 0xE0, 0x42, 0x0D, 0xF0, 0x30, 0x44, 0x8F, 0xE0, 0x62, 0x0D, 0x90, 0x30, 0x44, 0x8F, 0x54, ++ 0x45, 0x0D, 0x90, 0xF0, 0x44, 0x8F, 0x54, 0xE0, 0x0D, 0x90, 0xF0, 0x20, 0x8F, 0x54, 0xE0, 0x65, ++ 0x22, 0xF0, 0x20, 0x44, 0xE0, 0x69, 0x06, 0x90, 0x54, 0x13, 0x13, 0xFF, 0x0F, 0xE0, 0x30, 0x3F, ++ 0xFC, 0xE4, 0x7E, 0xF1, 0xFF, 0x7B, 0xFD, 0x33, 0x65, 0x79, 0x20, 0x7A, 0x78, 0x40, 0x0D, 0x12, ++ 0x09, 0x70, 0xE6, 0x9B, 0x75, 0xEE, 0x03, 0x12, 0x6F, 0x75, 0x23, 0x6E, 0x4A, 0x7F, 0x22, 0x3C, ++ 0x46, 0x7D, 0x0D, 0x7E, 0x10, 0xD2, 0x0D, 0x7C, 0x83, 0x8E, 0x82, 0x8F, 0x0F, 0x54, 0xC4, 0xE0, ++ 0x40, 0x04, 0x94, 0xD3, 0x75, 0x09, 0x90, 0x36, 0x50, 0x19, 0x94, 0xE0, 0x8C, 0x82, 0x8D, 0x2E, ++ 0xC4, 0xFD, 0xE0, 0x83, 0xED, 0xFC, 0x0F, 0x54, 0xEC, 0xFD, 0x0F, 0x54, 0xC4, 0x0F, 0x54, 0x14, ++ 0xF0, 0x4D, 0xF0, 0x54, 0xFF, 0xE0, 0x82, 0x8F, 0xFE, 0x0F, 0x54, 0xC4, 0xFF, 0x0F, 0x54, 0xEF, ++ 0x0F, 0x54, 0x14, 0xEE, 0x4F, 0xF0, 0x54, 0xC4, 0x90, 0x10, 0xC2, 0xF0, 0x90, 0xE0, 0x46, 0x0D, ++ 0x90, 0xF0, 0x66, 0x0D, 0x90, 0xE0, 0x4A, 0x0D, 0xA2, 0xF0, 0x6A, 0x0D, 0xFF, 0x7B, 0x22, 0x10, ++ 0x7E, 0x79, 0x20, 0x7A, 0x90, 0xF4, 0x03, 0x12, 0x01, 0x74, 0xF3, 0x07, 0xEB, 0x07, 0x90, 0xF0, ++ 0x90, 0xF0, 0x3F, 0x74, 0x44, 0xE0, 0xDC, 0x07, 0x90, 0xE4, 0xF0, 0x01, 0x90, 0xF0, 0xCB, 0x01, ++ 0x54, 0xE0, 0x43, 0x06, 0x54, 0xE0, 0xF0, 0xFB, 0x06, 0x90, 0xF0, 0xDF, 0xF0, 0x80, 0x74, 0x60, ++ 0xF0, 0xFF, 0x74, 0xA3, 0xE0, 0x6D, 0x09, 0x90, 0x6A, 0x75, 0xF0, 0xE4, 0x24, 0x6B, 0x75, 0x02, ++ 0x00, 0x00, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x74, 0x61, 0x44, 0x09, 0x0A, 0x00, 0x0A, 0x61, 0x4F, 0x4C, 0x09, 0x09, 0x25, 0x20, 0x3A, 0x4B, ++ 0x09, 0x00, 0x0A, 0x64, 0x4C, 0x56, 0x4C, 0x09, 0x64, 0x25, 0x20, 0x3A, 0x09, 0x09, 0x00, 0x0A, ++ 0x3A, 0x52, 0x57, 0x50, 0x20, 0x44, 0x25, 0x20, 0x09, 0x09, 0x00, 0x0A, 0x3A, 0x52, 0x4E, 0x53, ++ 0x20, 0x64, 0x25, 0x20, 0x00, 0x0A, 0x42, 0x64, 0x52, 0x46, 0x09, 0x09, 0x25, 0x20, 0x3A, 0x4F, ++ 0x70, 0x70, 0x20, 0x44, 0x09, 0x00, 0x0A, 0x6D, 0x51, 0x45, 0x4C, 0x09, 0x25, 0x20, 0x00, 0x3A, ++ 0x00, 0x0A, 0x00, 0x44, 0x46, 0x44, 0x09, 0x09, 0x09, 0x00, 0x3A, 0x45, 0x44, 0x41, 0x42, 0x09, ++ 0x47, 0x49, 0x53, 0x5F, 0x09, 0x09, 0x00, 0x0A, 0x43, 0x53, 0x6F, 0x4C, 0x09, 0x00, 0x0A, 0x52, ++ 0x53, 0x6F, 0x4C, 0x09, 0x22, 0x22, 0x00, 0x0A, 0x60, 0x70, 0xE5, 0x22, 0x7A, 0xFF, 0x7B, 0x25, ++ 0x12, 0x00, 0x79, 0x20, 0x06, 0x90, 0xF4, 0x03, 0x01, 0x44, 0xE0, 0x75, 0xA3, 0x78, 0xE4, 0xF0, ++ 0x78, 0xF6, 0x08, 0xF6, 0x79, 0x75, 0xF6, 0xA1, 0x76, 0x7A, 0x75, 0x20, 0x75, 0x20, 0x7B, 0x75, ++ 0x07, 0x90, 0x77, 0x7C, 0x14, 0x60, 0xE0, 0xDA, 0xE0, 0xD8, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, ++ 0x03, 0x74, 0xDA, 0x07, 0xD8, 0x07, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0xCB, 0x01, 0x90, ++ 0xF0, 0xFF, 0x02, 0x44, 0x07, 0x90, 0xFE, 0xE0, 0x13, 0xC4, 0xE0, 0xD4, 0xFD, 0x01, 0x54, 0x13, ++ 0x54, 0x13, 0xC4, 0xEE, 0x54, 0xEF, 0xFE, 0x01, 0x4D, 0xEE, 0xFF, 0xDF, 0x33, 0xC4, 0x01, 0x54, ++ 0x90, 0x4F, 0xE0, 0x54, 0xE0, 0xF0, 0xCB, 0x01, 0xD4, 0x07, 0x90, 0xFF, 0x54, 0x13, 0xC4, 0xE0, ++ 0x13, 0xEF, 0xFE, 0x01, 0x01, 0x54, 0x13, 0x13, 0xF7, 0x54, 0xEF, 0xFD, 0x54, 0x4E, 0xED, 0xFF, ++ 0x33, 0x33, 0x33, 0x01, 0x90, 0x4F, 0xF8, 0x54, 0xE0, 0xF0, 0xCB, 0x01, 0xD4, 0x07, 0x90, 0xFF, ++ 0x54, 0x13, 0xC3, 0xE0, 0xC4, 0xEF, 0xFE, 0x01, 0xEF, 0xFD, 0x01, 0x54, 0xED, 0xFF, 0xEF, 0x54, ++ 0xFE, 0x01, 0x54, 0x4E, 0x4F, 0xF0, 0x54, 0xC4, 0xF0, 0xCB, 0x01, 0x90, 0x74, 0xD4, 0x07, 0x90, ++ 0x10, 0xD2, 0xF0, 0x62, 0x40, 0x5D, 0x0E, 0x12, 0x65, 0x78, 0x74, 0x20, 0x74, 0x04, 0x70, 0x7C, ++ 0x60, 0x7B, 0x65, 0x20, 0x65, 0x77, 0x74, 0x14, 0x74, 0x04, 0x70, 0x7C, 0x70, 0x7B, 0x65, 0x20, ++ 0x40, 0xCA, 0x31, 0x78, 0x50, 0x73, 0x71, 0x04, 0xC2, 0xEC, 0xC2, 0x70, 0x47, 0x07, 0x90, 0xEE, ++ 0xF0, 0xF7, 0x54, 0xE0, 0xF0, 0xDF, 0x54, 0xE0, 0x74, 0x67, 0x07, 0x90, 0x07, 0x90, 0xF0, 0xFF, ++ 0x0D, 0x90, 0xF0, 0x69, 0xDF, 0x54, 0xE0, 0x41, 0x61, 0x0D, 0x90, 0xF0, 0xF0, 0xDF, 0x54, 0xE0, ++ 0xE0, 0x41, 0x0D, 0x90, 0x90, 0xF0, 0xEF, 0x54, 0x54, 0xE0, 0x61, 0x0D, 0x09, 0x90, 0xF0, 0xEF, ++ 0x02, 0x44, 0xE0, 0x2D, 0xF7, 0x54, 0xE0, 0xF0, 0x2C, 0x09, 0x90, 0xF0, 0xF0, 0x02, 0x44, 0xE0, ++ 0xF0, 0xF7, 0x54, 0xE0, 0xE0, 0xEF, 0x07, 0x90, 0x90, 0xF0, 0xFE, 0x54, 0x44, 0xE0, 0xFB, 0x07, ++ 0x44, 0xE0, 0xF0, 0x08, 0x06, 0x90, 0xF0, 0x80, 0x01, 0x44, 0xE0, 0x75, 0x7F, 0x02, 0x7E, 0xF0, ++ 0x8F, 0x6A, 0x8E, 0x8D, 0x8F, 0x68, 0x8E, 0x6B, 0x17, 0x30, 0x22, 0x69, 0x78, 0x5D, 0x61, 0x02, ++ 0x18, 0xE6, 0x06, 0xA4, 0x78, 0x06, 0x01, 0x70, 0x01, 0x64, 0xE6, 0xA4, 0x02, 0x60, 0x46, 0x18, ++ 0x08, 0x90, 0xBA, 0x41, 0x25, 0xF5, 0xE0, 0x59, 0xE0, 0x5A, 0x08, 0x90, 0x26, 0xE5, 0x26, 0xF5, ++ 0x06, 0x78, 0x25, 0xAE, 0x13, 0xE7, 0xA2, 0xCE, 0xF8, 0xD8, 0x13, 0xCE, 0xE5, 0x06, 0xAC, 0xFD, ++ 0x78, 0x25, 0xAE, 0x26, 0xE7, 0xA2, 0xCE, 0x05, 0xD8, 0x13, 0xCE, 0x13, 0xEE, 0xFF, 0x2D, 0xF8, ++ 0x25, 0xEF, 0xFE, 0x3C, 0xEE, 0x26, 0xF5, 0x26, 0x25, 0xF5, 0x25, 0x35, 0xE0, 0x75, 0x09, 0x90, ++ 0x7C, 0xED, 0x7D, 0xFF, 0x8F, 0xA6, 0x71, 0x21, 0x90, 0x26, 0xAF, 0x27, 0xF0, 0xEF, 0x60, 0x06, ++ 0x94, 0xD3, 0x27, 0xE5, 0x40, 0x27, 0xAF, 0x0E, 0xEF, 0x0E, 0x7F, 0x02, 0x54, 0xC4, 0x0F, 0x54, ++ 0x06, 0x90, 0xFF, 0xF0, 0x0F, 0x54, 0xE0, 0x61, 0x90, 0xE4, 0xF0, 0x4F, 0xE0, 0xF0, 0x5D, 0x09, ++ 0x40, 0x44, 0x9F, 0x54, 0x60, 0x09, 0x90, 0xF0, 0x7B, 0x28, 0xF5, 0xE0, 0x79, 0x20, 0x7A, 0xFF, ++ 0x08, 0x9C, 0x78, 0x07, 0x86, 0x18, 0xE6, 0x06, 0x06, 0x01, 0x70, 0x04, 0x0D, 0x12, 0xFD, 0x14, ++ 0x7A, 0xFF, 0x7B, 0x40, 0xE5, 0x13, 0x79, 0x20, 0x09, 0x90, 0xFE, 0x28, 0xEE, 0xFD, 0xE0, 0x61, ++ 0x0D, 0x12, 0xED, 0xFC, 0x7A, 0xFF, 0x7B, 0x40, 0x90, 0x1E, 0x79, 0x20, 0xFD, 0xE0, 0x76, 0x09, ++ 0x0D, 0x12, 0x00, 0x7C, 0x7A, 0xFF, 0x7B, 0x40, 0xE5, 0x2A, 0x79, 0x20, 0x00, 0x7C, 0xFD, 0x27, ++ 0x7B, 0x40, 0x0D, 0x12, 0x79, 0x20, 0x7A, 0xFF, 0xAC, 0x26, 0xAD, 0x38, 0x40, 0x0D, 0x12, 0x25, ++ 0x94, 0xD3, 0x28, 0xE5, 0x61, 0x02, 0x40, 0x01, 0xA4, 0x78, 0x22, 0x5D, 0x18, 0x02, 0x64, 0xE6, ++ 0x7B, 0x44, 0x70, 0x46, 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x47, 0x5D, 0x09, 0x90, 0xE4, ++ 0x9F, 0x54, 0xE0, 0xF0, 0x24, 0xF5, 0xE4, 0xF0, 0x0F, 0x54, 0x24, 0xE5, 0x5D, 0x09, 0x90, 0xFF, ++ 0x4F, 0xF0, 0x54, 0xE0, 0x7A, 0xFF, 0x7B, 0xF0, 0x90, 0x4E, 0x79, 0x20, 0xFE, 0xE0, 0x60, 0x09, ++ 0xE0, 0x61, 0x09, 0x90, 0xAC, 0xFF, 0xED, 0xFD, 0x40, 0x0D, 0x12, 0x06, 0x24, 0xE5, 0x24, 0x05, ++ 0x40, 0x0A, 0x94, 0xC3, 0x78, 0x4D, 0x80, 0xD3, 0x03, 0x64, 0xE6, 0xA4, 0x4D, 0x70, 0x46, 0x18, ++ 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x54, 0x79, 0x09, 0x90, 0xE4, 0xF4, 0x54, 0xE0, 0xF0, 0x5D, ++ 0xF0, 0x20, 0x44, 0x9F, 0xE5, 0x24, 0xF5, 0xE4, 0xFF, 0x0F, 0x54, 0x24, 0xE0, 0x5D, 0x09, 0x90, ++ 0xF0, 0x4F, 0xF0, 0x54, 0x20, 0x7A, 0xFF, 0x7B, 0x09, 0x90, 0x4E, 0x79, 0x90, 0xFE, 0xE0, 0x60, ++ 0xFD, 0xE0, 0x61, 0x09, 0x06, 0xAC, 0xFF, 0xED, 0x05, 0x40, 0x0D, 0x12, 0xC3, 0x24, 0xE5, 0x24, ++ 0xD3, 0x40, 0x08, 0x94, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x52, 0x79, 0x75, 0x09, 0x90, 0xF4, ++ 0x3C, 0x94, 0xD3, 0xE0, 0xFF, 0x7B, 0x0B, 0x40, 0x5B, 0x79, 0x20, 0x7A, 0xD3, 0xF4, 0x03, 0x12, ++ 0x90, 0x22, 0xC3, 0x22, 0xD3, 0xE0, 0xED, 0x07, 0x08, 0x40, 0xA0, 0x94, 0x20, 0x7A, 0xFF, 0x7B, ++ 0x17, 0x80, 0x66, 0x79, 0xE0, 0x76, 0x09, 0x90, 0x50, 0x03, 0x94, 0xC3, 0xE6, 0xA1, 0x78, 0x13, ++ 0x40, 0x0A, 0x94, 0x06, 0x7A, 0xFF, 0x7B, 0x0F, 0x12, 0x6F, 0x79, 0x20, 0x22, 0xD3, 0xF4, 0x03, ++ 0xF6, 0xA1, 0x78, 0xE4, 0x29, 0x8C, 0x22, 0xC3, 0xFB, 0xE4, 0x2A, 0x8D, 0x83, 0xF5, 0x82, 0xF5, ++ 0x80, 0x64, 0xEF, 0xC3, 0x02, 0x50, 0x81, 0x94, 0xEF, 0xD3, 0x01, 0x7F, 0xBF, 0x94, 0x80, 0x64, ++ 0x3F, 0x7F, 0x02, 0x40, 0x04, 0xF0, 0x75, 0xEF, 0xF0, 0xAC, 0xFD, 0xA4, 0x09, 0xE7, 0x20, 0xED, ++ 0xFD, 0xE0, 0x25, 0x0B, 0x80, 0xFC, 0x33, 0xEC, 0xAF, 0xFA, 0xE4, 0xF3, 0x12, 0x04, 0xAE, 0x05, ++ 0x06, 0xAC, 0xC0, 0x02, 0x78, 0xED, 0x07, 0xAD, 0x13, 0xC3, 0xCE, 0x07, 0xF9, 0xD8, 0x13, 0xCE, ++ 0xC3, 0x06, 0xAC, 0xFD, 0x40, 0x01, 0x94, 0xEC, 0x9A, 0x07, 0x74, 0x24, 0x7E, 0x01, 0x74, 0xFF, ++ 0x08, 0x07, 0xA8, 0x00, 0x33, 0xC3, 0x05, 0x80, 0xD8, 0xCE, 0x33, 0xCE, 0xF5, 0x82, 0x25, 0xF9, ++ 0x83, 0x35, 0xEE, 0x82, 0xC3, 0xEC, 0x83, 0xF5, 0x13, 0xED, 0xFC, 0x13, 0x08, 0xBA, 0x0A, 0xFD, ++ 0x05, 0x74, 0xC3, 0xBA, 0xFE, 0xEF, 0xFF, 0x9B, 0xF5, 0x82, 0x25, 0xE4, 0x83, 0x35, 0xEE, 0x82, ++ 0x00, 0x7C, 0x83, 0xF5, 0x82, 0xAF, 0x06, 0x7D, 0xC0, 0x02, 0x12, 0xFE, 0x82, 0x8F, 0x83, 0x8E, ++ 0x95, 0x82, 0xE5, 0xD3, 0x95, 0x83, 0xE5, 0x2A, 0xE4, 0x07, 0x40, 0x29, 0x82, 0xF5, 0x83, 0xF5, ++ 0xE5, 0xC3, 0x0D, 0x80, 0xF5, 0x82, 0x95, 0x2A, 0x95, 0x29, 0xE5, 0x82, 0xE5, 0x83, 0xF5, 0x83, ++ 0x75, 0x82, 0xF5, 0x83, 0x22, 0xFF, 0x00, 0x83, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, ++ 0x09, 0x09, 0x09, 0x09, 0x25, 0x3A, 0x58, 0x52, 0x09, 0x00, 0x0A, 0x78, 0x58, 0x54, 0x09, 0x09, ++ 0x00, 0x3A, 0x64, 0x25, 0x00, 0x0A, 0x78, 0x25, 0x44, 0x78, 0x54, 0x09, 0x00, 0x0A, 0x73, 0x69, ++ 0x2D, 0x53, 0x4C, 0x09, 0x0A, 0x6B, 0x68, 0x43, 0x50, 0x09, 0x09, 0x00, 0x61, 0x46, 0x2D, 0x44, ++ 0x0A, 0x74, 0x6C, 0x75, 0x43, 0x41, 0x09, 0x00, 0x0A, 0x44, 0x2D, 0x4B, 0x4E, 0x09, 0x09, 0x00, ++ 0x41, 0x4D, 0x2D, 0x4F, 0x0A, 0x48, 0x43, 0x54, 0x10, 0x02, 0x12, 0x00, 0x30, 0xEF, 0x72, 0xAF, ++ 0x06, 0x90, 0x17, 0xE0, 0x08, 0x44, 0xE0, 0x34, 0x7A, 0xFF, 0x7B, 0xF0, 0x12, 0x3D, 0x79, 0x20, ++ 0x64, 0x75, 0xF4, 0x03, 0xBD, 0x65, 0x75, 0x24, 0x27, 0x64, 0x75, 0x22, 0x22, 0xD9, 0x65, 0x75, ++ 0x03, 0x60, 0x67, 0xE5, 0xAF, 0x15, 0x02, 0x12, 0xE0, 0x30, 0xEF, 0x73, 0xE6, 0x8B, 0x78, 0x09, ++ 0x40, 0x00, 0x94, 0xD3, 0x8B, 0x78, 0x16, 0x01, 0x90, 0x40, 0x70, 0xE6, 0x13, 0xE0, 0x0D, 0x06, ++ 0x30, 0x3F, 0x54, 0x13, 0x13, 0xE0, 0x2F, 0xE0, 0x1F, 0x54, 0x13, 0x13, 0xAE, 0x26, 0xE0, 0x30, ++ 0x8F, 0x76, 0xAF, 0x75, 0xE0, 0x83, 0x8E, 0x82, 0x13, 0x13, 0x13, 0xC4, 0xE0, 0x20, 0x01, 0x54, ++ 0x10, 0x06, 0x90, 0x0D, 0x13, 0x13, 0xC4, 0xE0, 0x30, 0x01, 0x54, 0x13, 0x64, 0x75, 0x07, 0xE0, ++ 0xCC, 0x65, 0x75, 0x20, 0x20, 0x64, 0x75, 0x22, 0x22, 0x49, 0x65, 0x75, 0xE0, 0xA0, 0x07, 0x90, ++ 0x02, 0x64, 0x07, 0x54, 0x64, 0x75, 0x06, 0x60, 0xBD, 0x65, 0x75, 0x24, 0x03, 0x60, 0x67, 0xE5, ++ 0x78, 0x1A, 0x02, 0x12, 0x07, 0x64, 0xE6, 0x93, 0x20, 0xAF, 0x4B, 0x70, 0x13, 0x13, 0x13, 0xEF, ++ 0xE0, 0x30, 0x1F, 0x54, 0x0E, 0x06, 0x90, 0x65, 0xE0, 0xA3, 0xFE, 0xE0, 0x06, 0xA6, 0x90, 0x78, ++ 0x72, 0xAF, 0xF6, 0x08, 0xC4, 0x80, 0x54, 0xEF, 0x18, 0xFF, 0x0F, 0x54, 0x4F, 0xF7, 0x54, 0xE6, ++ 0x08, 0xFF, 0xE6, 0xF6, 0xAD, 0x75, 0xAC, 0xE6, 0x8C, 0x82, 0x8D, 0x76, 0xA3, 0xF0, 0xCF, 0x83, ++ 0x06, 0x90, 0xF0, 0xEF, 0x13, 0xC4, 0xE0, 0x0E, 0x01, 0x54, 0x13, 0x13, 0x78, 0x2B, 0xE0, 0x20, ++ 0x80, 0x08, 0x76, 0x93, 0x60, 0x67, 0xE5, 0x25, 0xEF, 0x72, 0xAF, 0x21, 0x54, 0xC4, 0x80, 0x54, ++ 0x90, 0x78, 0xFF, 0x0F, 0x4F, 0xF7, 0x54, 0xE6, 0x08, 0xFF, 0xE6, 0xF6, 0xAD, 0x75, 0xAC, 0xE6, ++ 0x8C, 0x82, 0x8D, 0x76, 0xA3, 0xF0, 0xCF, 0x83, 0x73, 0xAF, 0xF0, 0xEF, 0x20, 0x13, 0xC3, 0xEF, ++ 0xF7, 0x21, 0x02, 0xE0, 0x78, 0xAF, 0x77, 0xAE, 0x83, 0x8E, 0x82, 0x8F, 0xF0, 0xBF, 0x54, 0xE0, ++ 0x78, 0xAF, 0x77, 0xAE, 0x83, 0x8E, 0x82, 0x8F, 0xE0, 0xA3, 0xFE, 0xE0, 0x70, 0x66, 0x8E, 0x78, ++ 0x66, 0x18, 0xEE, 0x03, 0x8A, 0x78, 0x5B, 0x70, 0x94, 0xC3, 0xE6, 0x06, 0x76, 0x68, 0x40, 0x02, ++ 0xAF, 0x77, 0xAE, 0x02, 0x8E, 0x82, 0x8F, 0x78, 0x13, 0x13, 0xE0, 0x83, 0xFF, 0x01, 0x54, 0x13, ++ 0xC4, 0xEE, 0x72, 0xAE, 0x01, 0x54, 0x13, 0x13, 0x78, 0x4C, 0x60, 0x6F, 0x07, 0xB4, 0xE6, 0x93, ++ 0xEF, 0x20, 0xAF, 0x0B, 0x54, 0x13, 0x13, 0x13, 0x3B, 0xE0, 0x30, 0x1F, 0x75, 0x27, 0x64, 0x75, ++ 0x93, 0x78, 0x45, 0x65, 0x70, 0x07, 0x64, 0xE6, 0x54, 0x20, 0xE5, 0x2E, 0xE6, 0x20, 0xF5, 0xF7, ++ 0x23, 0x60, 0x01, 0x64, 0x60, 0x08, 0x64, 0xE6, 0x34, 0x06, 0x90, 0x1E, 0xF0, 0x10, 0x44, 0xE0, ++ 0xAF, 0x77, 0xAE, 0x22, 0x8E, 0x82, 0x8F, 0x78, 0xA3, 0xFE, 0xE0, 0x83, 0xA6, 0x8D, 0x78, 0xE0, ++ 0xE4, 0xF6, 0x08, 0x06, 0x22, 0xF6, 0x8A, 0x78, 0x08, 0x60, 0x67, 0xE5, 0x90, 0x1F, 0x02, 0x12, ++ 0x4D, 0x71, 0x23, 0x06, 0xC3, 0xEF, 0x72, 0xAF, 0x0A, 0xE0, 0x20, 0x13, 0x13, 0xEF, 0x72, 0xAF, ++ 0x30, 0x3F, 0x54, 0x13, 0x80, 0x7F, 0x27, 0xE0, 0x50, 0x48, 0x0E, 0x12, 0x76, 0x84, 0x78, 0x27, ++ 0x6C, 0x76, 0x08, 0x02, 0x54, 0xEF, 0x72, 0xAF, 0xF0, 0x54, 0xC4, 0x02, 0xEE, 0x72, 0xAE, 0xFF, ++ 0xF5, 0x4F, 0xDF, 0x54, 0x24, 0x64, 0x75, 0x72, 0x80, 0x2B, 0x65, 0x75, 0x76, 0x80, 0x78, 0x07, ++ 0x36, 0x76, 0x08, 0x01, 0xE0, 0xA0, 0x07, 0x90, 0x02, 0x64, 0x07, 0x54, 0x78, 0xE4, 0x0B, 0x60, ++ 0x8D, 0x78, 0xF6, 0x8A, 0x80, 0xF6, 0x08, 0xF6, 0xEF, 0x73, 0xAF, 0x57, 0xE0, 0x30, 0x13, 0xC3, ++ 0xAF, 0x77, 0xAE, 0x4F, 0x8E, 0x82, 0x8F, 0x78, 0x40, 0x54, 0xE0, 0x83, 0xE6, 0x8D, 0x78, 0xFF, ++ 0xF6, 0x4F, 0xBF, 0x54, 0x78, 0xAF, 0x77, 0xAE, 0x83, 0x8E, 0x82, 0x8F, 0xE0, 0xA3, 0xFE, 0xE0, ++ 0x03, 0x70, 0x66, 0x08, 0x70, 0x66, 0x18, 0xEE, 0x06, 0x8A, 0x78, 0x11, 0x02, 0x94, 0xC3, 0xE6, ++ 0x64, 0x75, 0x1E, 0x40, 0x45, 0x65, 0x75, 0x27, 0x77, 0xAE, 0x16, 0x80, 0x82, 0x8F, 0x78, 0xAF, ++ 0xFE, 0xE0, 0x83, 0x8E, 0x8D, 0x78, 0xE0, 0xA3, 0xF6, 0x08, 0x06, 0xA6, 0xF6, 0x8A, 0x78, 0xE4, ++ 0xE0, 0x27, 0x06, 0x90, 0x61, 0x02, 0xE0, 0x20, 0x12, 0x82, 0x7F, 0x39, 0x09, 0x40, 0x48, 0x0E, ++ 0x0E, 0x12, 0x84, 0x7F, 0x61, 0x02, 0x40, 0x48, 0xEF, 0x73, 0xAF, 0x4C, 0xAF, 0x7D, 0xE0, 0x30, ++ 0xE0, 0x20, 0xEF, 0x72, 0xE6, 0x83, 0x78, 0x77, 0x34, 0x70, 0x46, 0x18, 0xE0, 0x23, 0x06, 0x90, ++ 0x54, 0x13, 0x13, 0xFF, 0x07, 0xE0, 0x30, 0x3F, 0xE0, 0x35, 0x06, 0x90, 0xC2, 0xF0, 0x08, 0x44, ++ 0x71, 0x11, 0xC2, 0x10, 0xE6, 0x88, 0x78, 0x58, 0x08, 0xFE, 0x07, 0x54, 0xFF, 0xE0, 0x25, 0xE6, ++ 0xEF, 0xFE, 0x33, 0xEE, 0x83, 0x78, 0xC8, 0x24, 0x2A, 0x34, 0xEE, 0xF6, 0x21, 0x80, 0xF6, 0x18, ++ 0x54, 0xE6, 0x89, 0x78, 0x06, 0x90, 0xFF, 0x01, 0x13, 0xFD, 0xE0, 0x23, 0x6F, 0x01, 0x54, 0x13, ++ 0x60, 0xE4, 0x01, 0x70, 0x35, 0x06, 0x90, 0x07, 0xF0, 0x08, 0x44, 0xE0, 0x71, 0xE6, 0x89, 0x78, ++ 0x76, 0x84, 0x78, 0x53, 0x6C, 0x76, 0x08, 0x02, 0x76, 0x84, 0x78, 0x22, 0x6C, 0x76, 0x08, 0x02, ++ 0x2A, 0x76, 0x82, 0x78, 0x90, 0xC8, 0x76, 0x08, 0x4D, 0x71, 0x27, 0x06, 0x13, 0xFF, 0xE0, 0x22, ++ 0x13, 0x3F, 0x54, 0x13, 0x11, 0xC2, 0x10, 0x92, 0xE0, 0x27, 0x06, 0x90, 0x30, 0x03, 0xE0, 0x30, ++ 0x06, 0x90, 0x1A, 0x10, 0xE0, 0x20, 0xE0, 0x27, 0x26, 0x06, 0x90, 0x5F, 0xE0, 0xA3, 0xFE, 0xE0, ++ 0xC3, 0xCE, 0x02, 0x78, 0xD8, 0x13, 0xCE, 0x13, 0x4C, 0xE0, 0x20, 0xF9, 0x11, 0xA2, 0x10, 0xC2, ++ 0x54, 0xC4, 0x33, 0xE4, 0x90, 0x0F, 0x44, 0x10, 0x90, 0xF0, 0x01, 0x0D, 0x10, 0x74, 0x21, 0x0D, ++ 0x00, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x18, 0x74, 0x38, 0x74, 0x20, 0x0D, 0x0C, 0x0D, 0x90, 0xF0, ++ 0x90, 0xF0, 0x15, 0x74, 0x12, 0x74, 0x2C, 0x0D, 0xF1, 0x07, 0x90, 0xF0, 0xF0, 0xFC, 0x54, 0xE0, ++ 0x44, 0xF3, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x04, 0xFC, 0x54, 0xE0, 0xF2, 0xE0, 0xF0, 0x01, 0x44, ++ 0x90, 0xF0, 0xF3, 0x54, 0x4A, 0x80, 0xBC, 0x01, 0x11, 0xA2, 0x10, 0xD2, 0x54, 0xC4, 0x33, 0xE4, ++ 0x90, 0x0F, 0x44, 0xF0, 0x90, 0xF0, 0x21, 0x0D, 0x10, 0x74, 0x01, 0x0D, 0x00, 0x0D, 0x90, 0xF0, ++ 0x90, 0xF0, 0x38, 0x74, 0x18, 0x74, 0x20, 0x0D, 0x0C, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x12, 0x74, ++ 0x15, 0x74, 0x2C, 0x0D, 0xF1, 0x07, 0x90, 0xF0, 0x44, 0xFC, 0x54, 0xE0, 0x54, 0xE0, 0xF0, 0x01, ++ 0x07, 0x90, 0xF0, 0xF3, 0xFC, 0x54, 0xE0, 0xF2, 0xF3, 0x54, 0xE0, 0xF0, 0x90, 0xF0, 0x04, 0x44, ++ 0x90, 0xE0, 0xBD, 0x01, 0xA2, 0xF0, 0x3E, 0x08, 0x54, 0x33, 0xE4, 0x10, 0x25, 0xE0, 0x25, 0x01, ++ 0x06, 0x90, 0xFF, 0xE0, 0xFB, 0x54, 0xE0, 0x23, 0xE5, 0x22, 0xF0, 0x4F, 0x7B, 0x26, 0x60, 0x67, ++ 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x20, 0x74, 0x97, 0x07, 0x90, 0x06, 0x90, 0xF0, 0x01, ++ 0x13, 0xFF, 0xE0, 0x23, 0x13, 0x3F, 0x54, 0x13, 0x11, 0xD2, 0x10, 0x92, 0x80, 0x78, 0x58, 0x71, ++ 0x76, 0x08, 0x1D, 0x76, 0xEF, 0x72, 0xAF, 0x4C, 0x07, 0x54, 0x13, 0xC4, 0xE0, 0x30, 0x72, 0xAF, ++ 0x02, 0x54, 0xEF, 0x0A, 0x54, 0x33, 0x33, 0x33, 0xEF, 0x07, 0x80, 0xF8, 0xE0, 0x25, 0x04, 0x54, ++ 0xAE, 0xFF, 0xE0, 0x25, 0xEF, 0x54, 0xEE, 0x72, 0x7F, 0x72, 0xF5, 0x4F, 0x48, 0x0E, 0x12, 0x80, ++ 0x72, 0xAF, 0x1B, 0x50, 0x54, 0x13, 0xC4, 0xEF, 0x0B, 0x06, 0x90, 0x07, 0x74, 0x05, 0xE0, 0x20, ++ 0x03, 0x80, 0xF0, 0x21, 0x75, 0xF0, 0x81, 0x74, 0x65, 0x75, 0x20, 0x64, 0xEF, 0x72, 0xAF, 0x49, ++ 0x20, 0x0F, 0x54, 0xC4, 0xFF, 0x7B, 0x16, 0xE0, 0x29, 0x79, 0x20, 0x7A, 0x90, 0xF4, 0x03, 0x12, ++ 0x44, 0xE0, 0x0D, 0x06, 0x64, 0x75, 0xF0, 0x10, 0xF8, 0x65, 0x75, 0x21, 0x60, 0x67, 0xE5, 0x22, ++ 0x7A, 0xFF, 0x7B, 0x33, 0x12, 0x18, 0x79, 0x20, 0x80, 0x78, 0xF4, 0x03, 0x76, 0x08, 0x34, 0x76, ++ 0x23, 0x06, 0x90, 0xBC, 0x13, 0x13, 0xFF, 0xE0, 0x92, 0x13, 0x3F, 0x54, 0x71, 0x11, 0xD2, 0x10, ++ 0x97, 0x07, 0x90, 0x58, 0x90, 0xF0, 0x03, 0x74, 0x54, 0xE0, 0x03, 0x06, 0x20, 0xE5, 0xF0, 0xDF, ++ 0x20, 0xF5, 0xF7, 0x54, 0x0E, 0x12, 0x80, 0x7F, 0x75, 0x06, 0x50, 0x48, 0x65, 0x75, 0x21, 0x64, ++ 0x64, 0x75, 0x22, 0xF8, 0xBD, 0x65, 0x75, 0x24, 0xE0, 0x0D, 0x06, 0x90, 0xE5, 0xF0, 0xEF, 0x54, ++ 0xF5, 0xFB, 0x54, 0x20, 0x00, 0x06, 0x90, 0x20, 0xF0, 0xFD, 0x54, 0xE0, 0xE0, 0xC8, 0x01, 0x90, ++ 0x12, 0xF0, 0x04, 0x44, 0x07, 0x90, 0x74, 0x02, 0x01, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xF0, ++ 0x8A, 0x0D, 0x90, 0xF0, 0x0D, 0x90, 0xFF, 0xE0, 0xFF, 0x6F, 0xE0, 0x8B, 0xE0, 0x0B, 0x07, 0x90, ++ 0x88, 0x78, 0xE4, 0xFD, 0x08, 0x6D, 0xEF, 0xF6, 0x02, 0x05, 0x7F, 0xF6, 0x66, 0xE5, 0x68, 0x03, ++ 0x02, 0xB1, 0x25, 0x60, 0xF6, 0x86, 0x78, 0xE4, 0x67, 0x75, 0xF6, 0x08, 0x07, 0x75, 0x75, 0x01, ++ 0x75, 0x9A, 0x76, 0x75, 0x78, 0x75, 0x07, 0x77, 0xEF, 0x73, 0xAF, 0x9C, 0x73, 0xF5, 0xFD, 0x54, ++ 0x54, 0xEF, 0x73, 0xAF, 0xC2, 0x73, 0xF5, 0xFE, 0x5D, 0x0E, 0x12, 0x10, 0x06, 0x90, 0x0B, 0x40, ++ 0xC4, 0xFF, 0xE0, 0x00, 0xE0, 0x20, 0x0F, 0x54, 0x7F, 0x27, 0x7E, 0x12, 0x65, 0x65, 0xEF, 0xD9, ++ 0x65, 0xEE, 0x03, 0x70, 0x8E, 0x04, 0x60, 0x64, 0xF1, 0x65, 0x8F, 0x64, 0xEF, 0x73, 0xAF, 0x24, ++ 0x73, 0xF5, 0xFD, 0x54, 0xE0, 0x9E, 0x07, 0x90, 0xE0, 0x30, 0x13, 0xC3, 0x7A, 0xFF, 0x7B, 0x23, ++ 0xAE, 0x00, 0x79, 0x20, 0x8F, 0x78, 0xAF, 0x77, 0xE0, 0x83, 0x8E, 0x82, 0xFD, 0xE0, 0xA3, 0xFC, ++ 0xAF, 0x40, 0x0D, 0x12, 0x02, 0x44, 0xEF, 0x73, 0x07, 0x90, 0x73, 0xF5, 0xF0, 0x02, 0x74, 0x9E, ++ 0x65, 0x65, 0x63, 0xE5, 0x62, 0xE5, 0x04, 0x70, 0x09, 0x60, 0x64, 0x65, 0x85, 0x62, 0x64, 0x85, ++ 0x67, 0x75, 0x63, 0x65, 0xA9, 0x62, 0xAA, 0x01, 0x27, 0x03, 0x12, 0x63, 0xAF, 0x67, 0xF5, 0xE4, ++ 0xFE, 0x54, 0xEF, 0x73, 0x07, 0x90, 0x73, 0xF5, 0x13, 0x13, 0xE0, 0x9E, 0x30, 0x1F, 0x54, 0x13, ++ 0xFF, 0x7B, 0x31, 0xE0, 0x0B, 0x79, 0x20, 0x7A, 0xE0, 0x23, 0x06, 0x90, 0x39, 0x0D, 0x12, 0xFF, ++ 0x20, 0x7A, 0xFF, 0x7B, 0x75, 0xAE, 0x14, 0x79, 0x82, 0x8F, 0x76, 0xAF, 0xFC, 0xE0, 0x83, 0x8E, ++ 0x12, 0xFD, 0xE0, 0xA3, 0x73, 0xAF, 0x40, 0x0D, 0xF5, 0x01, 0x44, 0xEF, 0x9E, 0x07, 0x90, 0x73, ++ 0x78, 0xF0, 0x08, 0x74, 0x19, 0x70, 0xE6, 0x8C, 0x54, 0xEF, 0x72, 0xAF, 0x90, 0x72, 0xF5, 0xFD, ++ 0x13, 0xE0, 0x54, 0x08, 0x1F, 0x54, 0x13, 0x13, 0xE0, 0x30, 0x00, 0x7F, 0x80, 0x01, 0x7F, 0x02, ++ 0xE6, 0x8C, 0x78, 0x36, 0x1F, 0x70, 0x0A, 0x64, 0x44, 0xEF, 0x72, 0xAF, 0x90, 0x72, 0xF5, 0x02, ++ 0x13, 0xE0, 0x54, 0x08, 0x1F, 0x54, 0x13, 0x13, 0xE0, 0x20, 0x00, 0x7F, 0xC3, 0x01, 0x7F, 0x02, ++ 0x9F, 0xE6, 0x8C, 0x78, 0x90, 0x15, 0x80, 0xF6, 0x13, 0xE0, 0x54, 0x08, 0x1F, 0x54, 0x13, 0x13, ++ 0xE0, 0x20, 0x01, 0x7F, 0x78, 0xFF, 0x7F, 0x02, 0xF6, 0x26, 0xEF, 0x8C, 0x0E, 0x12, 0x86, 0x7F, ++ 0x90, 0x0A, 0x40, 0x48, 0x54, 0xE0, 0xA0, 0x07, 0x60, 0x01, 0x64, 0x07, 0xEF, 0x72, 0xAF, 0x07, ++ 0x72, 0xF5, 0xFB, 0x54, 0xE0, 0x9E, 0x07, 0x90, 0xD3, 0x2A, 0xE0, 0x30, 0x94, 0xE6, 0x87, 0x78, ++ 0x94, 0xE6, 0x18, 0x00, 0x90, 0x11, 0x40, 0x00, 0x54, 0xE0, 0xA0, 0x07, 0x01, 0xBF, 0xFF, 0x07, ++ 0xEF, 0x72, 0xAF, 0x07, 0x72, 0xF5, 0x04, 0x44, 0x00, 0x76, 0x86, 0x78, 0x90, 0xFA, 0x76, 0x08, ++ 0x01, 0x74, 0x9E, 0x07, 0x54, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x08, 0x74, 0x54, 0xE0, 0xA0, 0x07, ++ 0x02, 0xBF, 0xFF, 0x07, 0x80, 0x01, 0x7F, 0x04, 0xEF, 0x00, 0x7F, 0x02, 0x33, 0x33, 0x01, 0x54, ++ 0xFF, 0xF8, 0x54, 0x33, 0x54, 0xEE, 0x72, 0xAE, 0x72, 0xF5, 0x4F, 0xF7, 0x13, 0xEF, 0x72, 0xAF, ++ 0x01, 0x54, 0x13, 0x13, 0xEE, 0x72, 0xAE, 0xFF, 0x01, 0x54, 0x13, 0x13, 0x72, 0xAE, 0xFF, 0x4F, ++ 0x54, 0x13, 0xC3, 0xEE, 0x01, 0x54, 0x4F, 0x01, 0xEE, 0x72, 0xAE, 0xFF, 0xF5, 0x4F, 0xFE, 0x54, ++ 0x4E, 0xA1, 0x22, 0x72, 0x54, 0xE6, 0x89, 0x78, 0xE4, 0xC3, 0xFF, 0x01, 0x94, 0x08, 0x74, 0x9F, ++ 0xFC, 0x05, 0x54, 0x00, 0x13, 0xC3, 0xE6, 0x18, 0x13, 0xE6, 0x08, 0xFE, 0x18, 0x6C, 0xEE, 0xFF, ++ 0xF6, 0x08, 0xEF, 0xF6, 0x60, 0x67, 0xE5, 0x22, 0x7A, 0xFF, 0x7B, 0x26, 0x12, 0x35, 0x79, 0x20, ++ 0x06, 0x90, 0xF4, 0x03, 0x01, 0x44, 0xE0, 0x0D, 0xAF, 0x75, 0xAE, 0xF0, 0x8E, 0x82, 0x8F, 0x76, ++ 0x40, 0x44, 0xE0, 0x83, 0xE6, 0x8D, 0x78, 0xF0, 0xE4, 0xF6, 0x40, 0x44, 0x90, 0xF6, 0x8A, 0x78, ++ 0x54, 0xE0, 0xA0, 0x07, 0x60, 0x02, 0x64, 0x07, 0x24, 0x64, 0x75, 0x06, 0xAF, 0xBD, 0x65, 0x75, ++ 0x13, 0xC3, 0xEF, 0x73, 0xAE, 0x51, 0xE0, 0x30, 0x8F, 0x78, 0xAF, 0x77, 0xE0, 0x83, 0x8E, 0x82, ++ 0x78, 0xE0, 0xA3, 0xFE, 0x03, 0x70, 0x66, 0x8E, 0x70, 0x66, 0x18, 0xEE, 0x06, 0x8A, 0x78, 0x10, ++ 0x02, 0x94, 0xD3, 0xE6, 0x64, 0x75, 0x32, 0x40, 0x70, 0x65, 0x75, 0x20, 0x8A, 0x78, 0xE4, 0x22, ++ 0xE6, 0x8D, 0x78, 0xF6, 0xAE, 0xF6, 0xBF, 0x54, 0x8F, 0x78, 0xAF, 0x77, 0xE0, 0x83, 0x8E, 0x82, ++ 0x08, 0xE0, 0xA3, 0xFE, 0xEE, 0x03, 0x70, 0x66, 0x06, 0x60, 0x66, 0x18, 0x75, 0x24, 0x64, 0x75, ++ 0x8D, 0x78, 0xBD, 0x65, 0xF6, 0x40, 0x44, 0xE6, 0xC8, 0x01, 0x90, 0x22, 0xF0, 0xFB, 0x54, 0xE0, ++ 0x75, 0x02, 0x60, 0x75, 0x22, 0x22, 0x0B, 0x61, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x09, 0x09, 0x09, 0x09, 0x25, 0x3A, 0x58, 0x52, 0x09, 0x00, 0x0A, 0x78, 0x58, 0x54, 0x09, 0x09, ++ 0x00, 0x3A, 0x64, 0x25, 0x00, 0x0A, 0x78, 0x25, 0x44, 0x78, 0x54, 0x09, 0x00, 0x0A, 0x73, 0x69, ++ 0x2D, 0x53, 0x4C, 0x09, 0x0A, 0x6B, 0x68, 0x43, 0x50, 0x09, 0x09, 0x00, 0x61, 0x46, 0x2D, 0x44, ++ 0x0A, 0x74, 0x6C, 0x75, 0x43, 0x41, 0x09, 0x00, 0x0A, 0x44, 0x2D, 0x4B, 0x4E, 0x09, 0x09, 0x00, ++ 0x41, 0x4D, 0x2D, 0x4F, 0x0A, 0x48, 0x43, 0x54, 0x29, 0x02, 0x12, 0x00, 0x30, 0xEF, 0x79, 0xAF, ++ 0x06, 0x90, 0x17, 0xE0, 0x08, 0x44, 0xE0, 0x74, 0x7A, 0xFF, 0x7B, 0xF0, 0x12, 0x3D, 0x79, 0x20, ++ 0x6E, 0x75, 0xF4, 0x03, 0xBD, 0x6F, 0x75, 0x24, 0x27, 0x6E, 0x75, 0x22, 0x22, 0xD9, 0x6F, 0x75, ++ 0x03, 0x60, 0x71, 0xE5, 0xAF, 0x2E, 0x02, 0x12, 0xE0, 0x30, 0xEF, 0x7A, 0xE6, 0xA4, 0x78, 0x09, ++ 0x40, 0x00, 0x94, 0xD3, 0xA4, 0x78, 0x16, 0x01, 0x90, 0x40, 0x70, 0xE6, 0x13, 0xE0, 0x4D, 0x06, ++ 0x30, 0x3F, 0x54, 0x13, 0x13, 0xE0, 0x2F, 0xE0, 0x1F, 0x54, 0x13, 0x13, 0xAE, 0x26, 0xE0, 0x30, ++ 0x8F, 0x7D, 0xAF, 0x7C, 0xE0, 0x83, 0x8E, 0x82, 0x13, 0x13, 0x13, 0xC4, 0xE0, 0x20, 0x01, 0x54, ++ 0x50, 0x06, 0x90, 0x0D, 0x13, 0x13, 0xC4, 0xE0, 0x30, 0x01, 0x54, 0x13, 0x6E, 0x75, 0x07, 0xE0, ++ 0xCC, 0x6F, 0x75, 0x20, 0x20, 0x6E, 0x75, 0x22, 0x22, 0x49, 0x6F, 0x75, 0xE0, 0xE9, 0x07, 0x90, ++ 0x02, 0x64, 0x07, 0x54, 0x6E, 0x75, 0x06, 0x60, 0xBD, 0x6F, 0x75, 0x24, 0x03, 0x60, 0x71, 0xE5, ++ 0x78, 0x33, 0x02, 0x12, 0x07, 0x64, 0xE6, 0xAC, 0x21, 0xAF, 0x4B, 0x70, 0x13, 0x13, 0x13, 0xEF, ++ 0xE0, 0x30, 0x1F, 0x54, 0x4E, 0x06, 0x90, 0x65, 0xE0, 0xA3, 0xFE, 0xE0, 0x06, 0xA6, 0xA9, 0x78, ++ 0x79, 0xAF, 0xF6, 0x08, 0xC4, 0x80, 0x54, 0xEF, 0x18, 0xFF, 0x0F, 0x54, 0x4F, 0xF7, 0x54, 0xE6, ++ 0x08, 0xFF, 0xE6, 0xF6, 0xAD, 0x7C, 0xAC, 0xE6, 0x8C, 0x82, 0x8D, 0x7D, 0xA3, 0xF0, 0xCF, 0x83, ++ 0x06, 0x90, 0xF0, 0xEF, 0x13, 0xC4, 0xE0, 0x4E, 0x01, 0x54, 0x13, 0x13, 0x78, 0x2B, 0xE0, 0x20, ++ 0x80, 0x08, 0x76, 0xAC, 0x60, 0x71, 0xE5, 0x25, 0xEF, 0x79, 0xAF, 0x21, 0x54, 0xC4, 0x80, 0x54, ++ 0xA9, 0x78, 0xFF, 0x0F, 0x4F, 0xF7, 0x54, 0xE6, 0x08, 0xFF, 0xE6, 0xF6, 0xAD, 0x7C, 0xAC, 0xE6, ++ 0x8C, 0x82, 0x8D, 0x7D, 0xA3, 0xF0, 0xCF, 0x83, 0x7A, 0xAF, 0xF0, 0xEF, 0x20, 0x13, 0xC3, 0xEF, ++ 0xF7, 0x21, 0x02, 0xE0, 0x7F, 0xAF, 0x7E, 0xAE, 0x83, 0x8E, 0x82, 0x8F, 0xF0, 0xBF, 0x54, 0xE0, ++ 0x7F, 0xAF, 0x7E, 0xAE, 0x83, 0x8E, 0x82, 0x8F, 0xE0, 0xA3, 0xFE, 0xE0, 0x70, 0x66, 0xA7, 0x78, ++ 0x66, 0x18, 0xEE, 0x03, 0xA3, 0x78, 0x5B, 0x70, 0x94, 0xC3, 0xE6, 0x06, 0x76, 0x68, 0x40, 0x02, ++ 0xAF, 0x7E, 0xAE, 0x02, 0x8E, 0x82, 0x8F, 0x7F, 0x13, 0x13, 0xE0, 0x83, 0xFF, 0x01, 0x54, 0x13, ++ 0xC4, 0xEE, 0x79, 0xAE, 0x01, 0x54, 0x13, 0x13, 0x78, 0x4C, 0x60, 0x6F, 0x07, 0xB4, 0xE6, 0xAC, ++ 0xEF, 0x21, 0xAF, 0x0B, 0x54, 0x13, 0x13, 0x13, 0x3B, 0xE0, 0x30, 0x1F, 0x75, 0x27, 0x6E, 0x75, ++ 0xAC, 0x78, 0x45, 0x6F, 0x70, 0x07, 0x64, 0xE6, 0x54, 0x21, 0xE5, 0x2E, 0xE6, 0x21, 0xF5, 0xF7, ++ 0x23, 0x60, 0x01, 0x64, 0x60, 0x08, 0x64, 0xE6, 0x74, 0x06, 0x90, 0x1E, 0xF0, 0x10, 0x44, 0xE0, ++ 0xAF, 0x7E, 0xAE, 0x22, 0x8E, 0x82, 0x8F, 0x7F, 0xA3, 0xFE, 0xE0, 0x83, 0xA6, 0xA6, 0x78, 0xE0, ++ 0xE4, 0xF6, 0x08, 0x06, 0x22, 0xF6, 0xA3, 0x78, 0x08, 0x60, 0x71, 0xE5, 0x90, 0x38, 0x02, 0x12, ++ 0x4D, 0x71, 0x63, 0x06, 0xC3, 0xEF, 0x79, 0xAF, 0x0A, 0xE0, 0x20, 0x13, 0x13, 0xEF, 0x79, 0xAF, ++ 0x30, 0x3F, 0x54, 0x13, 0x99, 0x7F, 0x27, 0xE0, 0x50, 0x48, 0x0E, 0x12, 0x76, 0x9D, 0x78, 0x27, ++ 0x6C, 0x76, 0x08, 0x02, 0x54, 0xEF, 0x79, 0xAF, 0xF0, 0x54, 0xC4, 0x02, 0xEE, 0x79, 0xAE, 0xFF, ++ 0xF5, 0x4F, 0xDF, 0x54, 0x24, 0x6E, 0x75, 0x79, 0x80, 0x2B, 0x6F, 0x75, 0x76, 0x99, 0x78, 0x07, ++ 0x36, 0x76, 0x08, 0x01, 0xE0, 0xE9, 0x07, 0x90, 0x02, 0x64, 0x07, 0x54, 0x78, 0xE4, 0x0B, 0x60, ++ 0xA6, 0x78, 0xF6, 0xA3, 0x80, 0xF6, 0x08, 0xF6, 0xEF, 0x7A, 0xAF, 0x57, 0xE0, 0x30, 0x13, 0xC3, ++ 0xAF, 0x7E, 0xAE, 0x4F, 0x8E, 0x82, 0x8F, 0x7F, 0x40, 0x54, 0xE0, 0x83, 0xE6, 0xA6, 0x78, 0xFF, ++ 0xF6, 0x4F, 0xBF, 0x54, 0x7F, 0xAF, 0x7E, 0xAE, 0x83, 0x8E, 0x82, 0x8F, 0xE0, 0xA3, 0xFE, 0xE0, ++ 0x03, 0x70, 0x66, 0x08, 0x70, 0x66, 0x18, 0xEE, 0x06, 0xA3, 0x78, 0x11, 0x02, 0x94, 0xC3, 0xE6, ++ 0x6E, 0x75, 0x1E, 0x40, 0x45, 0x6F, 0x75, 0x27, 0x7E, 0xAE, 0x16, 0x80, 0x82, 0x8F, 0x7F, 0xAF, ++ 0xFE, 0xE0, 0x83, 0x8E, 0xA6, 0x78, 0xE0, 0xA3, 0xF6, 0x08, 0x06, 0xA6, 0xF6, 0xA3, 0x78, 0xE4, ++ 0xE0, 0x67, 0x06, 0x90, 0x61, 0x02, 0xE0, 0x20, 0x12, 0x9B, 0x7F, 0x39, 0x09, 0x40, 0x48, 0x0E, ++ 0x0E, 0x12, 0x9D, 0x7F, 0x61, 0x02, 0x40, 0x48, 0xEF, 0x7A, 0xAF, 0x4C, 0xAF, 0x7D, 0xE0, 0x30, ++ 0xE0, 0x20, 0xEF, 0x79, 0xE6, 0x9C, 0x78, 0x77, 0x34, 0x70, 0x46, 0x18, 0xE0, 0x63, 0x06, 0x90, ++ 0x54, 0x13, 0x13, 0xFF, 0x07, 0xE0, 0x30, 0x3F, 0xE0, 0x75, 0x06, 0x90, 0xC2, 0xF0, 0x08, 0x44, ++ 0x71, 0x11, 0xC2, 0x10, 0xE6, 0xA1, 0x78, 0x58, 0x08, 0xFE, 0x07, 0x54, 0xFF, 0xE0, 0x25, 0xE6, ++ 0xEF, 0xFE, 0x33, 0xEE, 0x9C, 0x78, 0xC8, 0x24, 0x2A, 0x34, 0xEE, 0xF6, 0x21, 0x80, 0xF6, 0x18, ++ 0x54, 0xE6, 0xA2, 0x78, 0x06, 0x90, 0xFF, 0x01, 0x13, 0xFD, 0xE0, 0x63, 0x6F, 0x01, 0x54, 0x13, ++ 0x60, 0xE4, 0x01, 0x70, 0x75, 0x06, 0x90, 0x07, 0xF0, 0x08, 0x44, 0xE0, 0x71, 0xE6, 0xA2, 0x78, ++ 0x76, 0x9D, 0x78, 0x53, 0x6C, 0x76, 0x08, 0x02, 0x76, 0x9D, 0x78, 0x22, 0x6C, 0x76, 0x08, 0x02, ++ 0x2A, 0x76, 0x9B, 0x78, 0x90, 0xC8, 0x76, 0x08, 0x4D, 0x71, 0x67, 0x06, 0x13, 0xFF, 0xE0, 0x22, ++ 0x13, 0x3F, 0x54, 0x13, 0x11, 0xC2, 0x10, 0x92, 0xE0, 0x67, 0x06, 0x90, 0x30, 0x03, 0xE0, 0x30, ++ 0x06, 0x90, 0x1A, 0x10, 0xE0, 0x20, 0xE0, 0x67, 0x66, 0x06, 0x90, 0x5F, 0xE0, 0xA3, 0xFE, 0xE0, ++ 0xC3, 0xCE, 0x02, 0x78, 0xD8, 0x13, 0xCE, 0x13, 0x4C, 0xE0, 0x20, 0xF9, 0x11, 0xA2, 0x10, 0xC2, ++ 0x54, 0xC4, 0x33, 0xE4, 0x90, 0x0F, 0x44, 0x10, 0x90, 0xF0, 0x41, 0x0D, 0x10, 0x74, 0x61, 0x0D, ++ 0x40, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x18, 0x74, 0x38, 0x74, 0x60, 0x0D, 0x4C, 0x0D, 0x90, 0xF0, ++ 0x90, 0xF0, 0x15, 0x74, 0x12, 0x74, 0x6C, 0x0D, 0xF1, 0x07, 0x90, 0xF0, 0xF0, 0x30, 0x44, 0xE0, ++ 0x44, 0x3F, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x80, 0xCF, 0x54, 0xE0, 0xF2, 0xE0, 0xF0, 0x20, 0x44, ++ 0x90, 0xF0, 0xC0, 0x44, 0x4A, 0x80, 0xC2, 0x01, 0x11, 0xA2, 0x10, 0xD2, 0x54, 0xC4, 0x33, 0xE4, ++ 0x90, 0x0F, 0x44, 0xF0, 0x90, 0xF0, 0x61, 0x0D, 0x10, 0x74, 0x41, 0x0D, 0x40, 0x0D, 0x90, 0xF0, ++ 0x90, 0xF0, 0x38, 0x74, 0x18, 0x74, 0x60, 0x0D, 0x4C, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x12, 0x74, ++ 0x15, 0x74, 0x6C, 0x0D, 0xF1, 0x07, 0x90, 0xF0, 0x44, 0xCF, 0x54, 0xE0, 0x44, 0xE0, 0xF0, 0x20, ++ 0x07, 0x90, 0xF0, 0xC0, 0x30, 0x44, 0xE0, 0xF2, 0x3F, 0x54, 0xE0, 0xF0, 0x90, 0xF0, 0x80, 0x44, ++ 0x90, 0xE0, 0xC3, 0x01, 0xA2, 0xF0, 0x6D, 0x09, 0x54, 0x33, 0xE4, 0x10, 0x25, 0xE0, 0x25, 0x01, ++ 0x06, 0x90, 0xFF, 0xE0, 0xFB, 0x54, 0xE0, 0x63, 0xE5, 0x22, 0xF0, 0x4F, 0x7B, 0x26, 0x60, 0x71, ++ 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x20, 0x74, 0xE0, 0x07, 0x90, 0x06, 0x90, 0xF0, 0x01, ++ 0x13, 0xFF, 0xE0, 0x63, 0x13, 0x3F, 0x54, 0x13, 0x11, 0xD2, 0x10, 0x92, 0x99, 0x78, 0x58, 0x71, ++ 0x76, 0x08, 0x1D, 0x76, 0xEF, 0x79, 0xAF, 0x4C, 0x07, 0x54, 0x13, 0xC4, 0xE0, 0x30, 0x79, 0xAF, ++ 0x02, 0x54, 0xEF, 0x0A, 0x54, 0x33, 0x33, 0x33, 0xEF, 0x07, 0x80, 0xF8, 0xE0, 0x25, 0x04, 0x54, ++ 0xAE, 0xFF, 0xE0, 0x25, 0xEF, 0x54, 0xEE, 0x79, 0x7F, 0x79, 0xF5, 0x4F, 0x48, 0x0E, 0x12, 0x99, ++ 0x79, 0xAF, 0x1B, 0x50, 0x54, 0x13, 0xC4, 0xEF, 0x4B, 0x06, 0x90, 0x07, 0x74, 0x05, 0xE0, 0x20, ++ 0x03, 0x80, 0xF0, 0x21, 0x75, 0xF0, 0x81, 0x74, 0x6F, 0x75, 0x20, 0x6E, 0xEF, 0x79, 0xAF, 0x49, ++ 0x20, 0x0F, 0x54, 0xC4, 0xFF, 0x7B, 0x16, 0xE0, 0x29, 0x79, 0x20, 0x7A, 0x90, 0xF4, 0x03, 0x12, ++ 0x44, 0xE0, 0x4D, 0x06, 0x6E, 0x75, 0xF0, 0x10, 0xF8, 0x6F, 0x75, 0x21, 0x60, 0x71, 0xE5, 0x22, ++ 0x7A, 0xFF, 0x7B, 0x33, 0x12, 0x18, 0x79, 0x20, 0x99, 0x78, 0xF4, 0x03, 0x76, 0x08, 0x34, 0x76, ++ 0x63, 0x06, 0x90, 0xBC, 0x13, 0x13, 0xFF, 0xE0, 0x92, 0x13, 0x3F, 0x54, 0x71, 0x11, 0xD2, 0x10, ++ 0xE0, 0x07, 0x90, 0x58, 0x90, 0xF0, 0x03, 0x74, 0x54, 0xE0, 0x43, 0x06, 0x21, 0xE5, 0xF0, 0xDF, ++ 0x21, 0xF5, 0xF7, 0x54, 0x0E, 0x12, 0x99, 0x7F, 0x75, 0x06, 0x50, 0x48, 0x6F, 0x75, 0x21, 0x6E, ++ 0x6E, 0x75, 0x22, 0xF8, 0xBD, 0x6F, 0x75, 0x24, 0xE0, 0x4D, 0x06, 0x90, 0xE5, 0xF0, 0xEF, 0x54, ++ 0xF5, 0xFB, 0x54, 0x21, 0x40, 0x06, 0x90, 0x21, 0xF0, 0xFD, 0x54, 0xE0, 0xE0, 0xCA, 0x01, 0x90, ++ 0x12, 0xF0, 0x04, 0x44, 0x07, 0x90, 0x7E, 0x02, 0xFB, 0x54, 0xE0, 0xF0, 0x08, 0x44, 0xE0, 0xF0, ++ 0x8A, 0x0D, 0x90, 0xF0, 0x0D, 0x90, 0xFF, 0xE0, 0xFF, 0x6F, 0xE0, 0x8B, 0xE0, 0x0C, 0x07, 0x90, ++ 0xA1, 0x78, 0xE4, 0xFD, 0x08, 0x6D, 0xEF, 0xF6, 0x02, 0x05, 0x7F, 0xF6, 0x70, 0xE5, 0x68, 0x00, ++ 0x02, 0xB1, 0x25, 0x60, 0xF6, 0x9F, 0x78, 0xE4, 0x71, 0x75, 0xF6, 0x08, 0x07, 0x7C, 0x75, 0x01, ++ 0x75, 0xE3, 0x7D, 0x75, 0x7F, 0x75, 0x07, 0x7E, 0xEF, 0x7A, 0xAF, 0xE5, 0x7A, 0xF5, 0xFD, 0x54, ++ 0x54, 0xEF, 0x7A, 0xAF, 0xD2, 0x7A, 0xF5, 0xFE, 0x5D, 0x0E, 0x12, 0x10, 0x06, 0x90, 0x0B, 0x40, ++ 0xC4, 0xFF, 0xE0, 0x40, 0xE0, 0x20, 0x0F, 0x54, 0x7F, 0x27, 0x7E, 0x12, 0x6F, 0x65, 0xEF, 0xD9, ++ 0x65, 0xEE, 0x03, 0x70, 0x8E, 0x04, 0x60, 0x6E, 0xF1, 0x6F, 0x8F, 0x6E, 0xEF, 0x7A, 0xAF, 0x24, ++ 0x7A, 0xF5, 0xFD, 0x54, 0xE0, 0xE7, 0x07, 0x90, 0xE0, 0x30, 0x13, 0xC3, 0x7A, 0xFF, 0x7B, 0x23, ++ 0xAE, 0x00, 0x79, 0x20, 0x8F, 0x7F, 0xAF, 0x7E, 0xE0, 0x83, 0x8E, 0x82, 0xFD, 0xE0, 0xA3, 0xFC, ++ 0xAF, 0x40, 0x0D, 0x12, 0x02, 0x44, 0xEF, 0x7A, 0x07, 0x90, 0x7A, 0xF5, 0xF0, 0x02, 0x74, 0xE7, ++ 0x6F, 0x65, 0x6D, 0xE5, 0x6C, 0xE5, 0x04, 0x70, 0x09, 0x60, 0x6E, 0x65, 0x85, 0x6C, 0x6E, 0x85, ++ 0x71, 0x75, 0x6D, 0x6F, 0xA9, 0x6C, 0xAA, 0x01, 0x27, 0x03, 0x12, 0x6D, 0xAF, 0x71, 0xF5, 0xE4, ++ 0xFE, 0x54, 0xEF, 0x7A, 0x07, 0x90, 0x7A, 0xF5, 0x13, 0x13, 0xE0, 0xE7, 0x30, 0x1F, 0x54, 0x13, ++ 0xFF, 0x7B, 0x31, 0xE0, 0x0B, 0x79, 0x20, 0x7A, 0xE0, 0x63, 0x06, 0x90, 0x39, 0x0D, 0x12, 0xFF, ++ 0x20, 0x7A, 0xFF, 0x7B, 0x7C, 0xAE, 0x14, 0x79, 0x82, 0x8F, 0x7D, 0xAF, 0xFC, 0xE0, 0x83, 0x8E, ++ 0x12, 0xFD, 0xE0, 0xA3, 0x7A, 0xAF, 0x40, 0x0D, 0xF5, 0x01, 0x44, 0xEF, 0xE7, 0x07, 0x90, 0x7A, ++ 0x78, 0xF0, 0x08, 0x74, 0x19, 0x70, 0xE6, 0xA5, 0x54, 0xEF, 0x79, 0xAF, 0x90, 0x79, 0xF5, 0xFD, ++ 0x13, 0xE0, 0x83, 0x09, 0x1F, 0x54, 0x13, 0x13, 0xE0, 0x30, 0x00, 0x7F, 0x80, 0x01, 0x7F, 0x02, ++ 0xE6, 0xA5, 0x78, 0x36, 0x1F, 0x70, 0x0A, 0x64, 0x44, 0xEF, 0x79, 0xAF, 0x90, 0x79, 0xF5, 0x02, ++ 0x13, 0xE0, 0x83, 0x09, 0x1F, 0x54, 0x13, 0x13, 0xE0, 0x20, 0x00, 0x7F, 0xC3, 0x01, 0x7F, 0x02, ++ 0x9F, 0xE6, 0xA5, 0x78, 0x90, 0x15, 0x80, 0xF6, 0x13, 0xE0, 0x83, 0x09, 0x1F, 0x54, 0x13, 0x13, ++ 0xE0, 0x20, 0x01, 0x7F, 0x78, 0xFF, 0x7F, 0x02, 0xF6, 0x26, 0xEF, 0xA5, 0x0E, 0x12, 0x9F, 0x7F, ++ 0x90, 0x0A, 0x40, 0x48, 0x54, 0xE0, 0xE9, 0x07, 0x60, 0x01, 0x64, 0x07, 0xEF, 0x79, 0xAF, 0x07, ++ 0x79, 0xF5, 0xFB, 0x54, 0xE0, 0xE7, 0x07, 0x90, 0xD3, 0x2A, 0xE0, 0x30, 0x94, 0xE6, 0xA0, 0x78, ++ 0x94, 0xE6, 0x18, 0x00, 0x90, 0x11, 0x40, 0x00, 0x54, 0xE0, 0xE9, 0x07, 0x01, 0xBF, 0xFF, 0x07, ++ 0xEF, 0x79, 0xAF, 0x07, 0x79, 0xF5, 0x04, 0x44, 0x00, 0x76, 0x9F, 0x78, 0x90, 0xFA, 0x76, 0x08, ++ 0x01, 0x74, 0xE7, 0x07, 0x83, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x08, 0x74, 0x54, 0xE0, 0xE9, 0x07, ++ 0x02, 0xBF, 0xFF, 0x07, 0x80, 0x01, 0x7F, 0x04, 0xEF, 0x00, 0x7F, 0x02, 0x33, 0x33, 0x01, 0x54, ++ 0xFF, 0xF8, 0x54, 0x33, 0x54, 0xEE, 0x79, 0xAE, 0x79, 0xF5, 0x4F, 0xF7, 0x13, 0xEF, 0x79, 0xAF, ++ 0x01, 0x54, 0x13, 0x13, 0xEE, 0x79, 0xAE, 0xFF, 0x01, 0x54, 0x13, 0x13, 0x79, 0xAE, 0xFF, 0x4F, ++ 0x54, 0x13, 0xC3, 0xEE, 0x01, 0x54, 0x4F, 0x01, 0xEE, 0x79, 0xAE, 0xFF, 0xF5, 0x4F, 0xFE, 0x54, ++ 0x4E, 0xA1, 0x22, 0x79, 0x54, 0xE6, 0xA2, 0x78, 0xE4, 0xC3, 0xFF, 0x01, 0x94, 0x08, 0x74, 0x9F, ++ 0xFC, 0x05, 0x54, 0x00, 0x13, 0xC3, 0xE6, 0x18, 0x13, 0xE6, 0x08, 0xFE, 0x18, 0x6C, 0xEE, 0xFF, ++ 0xF6, 0x08, 0xEF, 0xF6, 0x60, 0x71, 0xE5, 0x22, 0x7A, 0xFF, 0x7B, 0x26, 0x12, 0x35, 0x79, 0x20, ++ 0x06, 0x90, 0xF4, 0x03, 0x01, 0x44, 0xE0, 0x4D, 0xAF, 0x7C, 0xAE, 0xF0, 0x8E, 0x82, 0x8F, 0x7D, ++ 0x40, 0x44, 0xE0, 0x83, 0xE6, 0xA6, 0x78, 0xF0, 0xE4, 0xF6, 0x40, 0x44, 0x90, 0xF6, 0xA3, 0x78, ++ 0x54, 0xE0, 0xE9, 0x07, 0x60, 0x02, 0x64, 0x07, 0x24, 0x6E, 0x75, 0x06, 0xAF, 0xBD, 0x6F, 0x75, ++ 0x13, 0xC3, 0xEF, 0x7A, 0xAE, 0x51, 0xE0, 0x30, 0x8F, 0x7F, 0xAF, 0x7E, 0xE0, 0x83, 0x8E, 0x82, ++ 0x78, 0xE0, 0xA3, 0xFE, 0x03, 0x70, 0x66, 0xA7, 0x70, 0x66, 0x18, 0xEE, 0x06, 0xA3, 0x78, 0x10, ++ 0x02, 0x94, 0xD3, 0xE6, 0x6E, 0x75, 0x32, 0x40, 0x70, 0x6F, 0x75, 0x20, 0xA3, 0x78, 0xE4, 0x22, ++ 0xE6, 0xA6, 0x78, 0xF6, 0xAE, 0xF6, 0xBF, 0x54, 0x8F, 0x7F, 0xAF, 0x7E, 0xE0, 0x83, 0x8E, 0x82, ++ 0x08, 0xE0, 0xA3, 0xFE, 0xEE, 0x03, 0x70, 0x66, 0x06, 0x60, 0x66, 0x18, 0x75, 0x24, 0x6E, 0x75, ++ 0xA6, 0x78, 0xBD, 0x6F, 0xF6, 0x40, 0x44, 0xE6, 0xCA, 0x01, 0x90, 0x22, 0xF0, 0xFB, 0x54, 0xE0, ++ 0x75, 0x02, 0x6A, 0x75, 0x22, 0x22, 0x24, 0x6B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x50, 0x53, 0x41, 0x09, 0x09, 0x64, 0x25, 0x3A, 0x43, 0x47, 0x41, 0x00, 0x09, 0x64, 0x25, 0x3A, ++ 0x25, 0x3A, 0x4D, 0x00, 0x48, 0x00, 0x09, 0x64, 0x0A, 0x64, 0x25, 0x3A, 0x62, 0x41, 0x09, 0x00, ++ 0x0A, 0x74, 0x73, 0x69, 0x61, 0x57, 0x09, 0x00, 0x00, 0x0A, 0x74, 0x69, 0x69, 0x78, 0x45, 0x09, ++ 0x09, 0x00, 0x0A, 0x74, 0x30, 0x31, 0x43, 0x44, 0x44, 0x09, 0x00, 0x0A, 0x30, 0x30, 0x31, 0x43, ++ 0x09, 0x00, 0x0A, 0x30, 0x0A, 0x4E, 0x43, 0x49, 0x48, 0x54, 0x09, 0x00, 0x09, 0x00, 0x0A, 0x44, ++ 0x0A, 0x43, 0x47, 0x41, 0x3A, 0x50, 0x09, 0x00, 0x0A, 0x64, 0x25, 0x20, 0x58, 0x45, 0x09, 0x00, ++ 0x01, 0x00, 0x0A, 0x43, 0x0A, 0x09, 0x08, 0x03, 0x00, 0x03, 0x08, 0x09, 0xF6, 0xF7, 0xF8, 0xFD, ++ 0x00, 0xFD, 0xF8, 0xF7, 0xB5, 0x00, 0x62, 0x00, 0x00, 0x01, 0xED, 0x00, 0xB5, 0x00, 0xED, 0x00, ++ 0x00, 0x00, 0x62, 0x00, 0x4B, 0xFF, 0x9E, 0xFF, 0x00, 0xFF, 0x13, 0xFF, 0x4B, 0xFF, 0x13, 0xFF, ++ 0x00, 0x00, 0x9E, 0xFF, 0x47, 0x06, 0x00, 0x00, 0xC8, 0x12, 0x8B, 0x0C, 0x19, 0x1F, 0xF8, 0x18, ++ 0x1F, 0x2B, 0x28, 0x25, 0xBA, 0x36, 0xFB, 0x30, 0xCE, 0x41, 0x56, 0x3C, 0x3F, 0x4C, 0x1C, 0x47, ++ 0xF5, 0x55, 0x33, 0x51, 0xD7, 0x5E, 0x82, 0x5A, 0xCF, 0x66, 0xF2, 0x62, 0xCA, 0x6D, 0x6D, 0x6A, ++ 0xB5, 0x73, 0xE2, 0x70, 0x84, 0x78, 0x41, 0x76, 0x29, 0x7C, 0x7D, 0x7A, 0x9D, 0x7E, 0x8A, 0x7D, ++ 0xD8, 0x7F, 0x62, 0x7F, 0x20, 0x00, 0xFF, 0x7F, 0x28, 0x08, 0x30, 0x10, 0x24, 0x04, 0x38, 0x18, ++ 0x2C, 0x0C, 0x34, 0x14, 0x22, 0x02, 0x3C, 0x1C, 0x2A, 0x0A, 0x32, 0x12, 0x26, 0x06, 0x3A, 0x1A, ++ 0x2E, 0x0E, 0x36, 0x16, 0x21, 0x01, 0x3E, 0x1E, 0x29, 0x09, 0x31, 0x11, 0x25, 0x05, 0x39, 0x19, ++ 0x2D, 0x0D, 0x35, 0x15, 0x23, 0x03, 0x3D, 0x1D, 0x2B, 0x0B, 0x33, 0x13, 0x27, 0x07, 0x3B, 0x1B, ++ 0x2F, 0x0F, 0x37, 0x17, 0x52, 0xA8, 0x3F, 0x1F, 0x54, 0xAA, 0x53, 0xA9, 0x8F, 0xE8, 0x55, 0xAB, ++ 0x8B, 0xCC, 0xA4, 0xF0, 0xFC, 0x2C, 0xA4, 0xF0, 0xA4, 0xF0, 0x8E, 0xE9, 0xF0, 0x8A, 0xFC, 0x2C, ++ 0xFC, 0x2C, 0xA4, 0xED, 0xA4, 0xF0, 0x8E, 0xEA, 0x8B, 0xF0, 0xA8, 0xCD, 0xCC, 0x2D, 0xA4, 0xF0, ++ 0xFD, 0xF0, 0x25, 0x38, 0xA4, 0xF0, 0x8F, 0xE9, 0xF0, 0x35, 0xCD, 0x2C, 0xF0, 0x8E, 0xEB, 0xFC, ++ 0xF0, 0xA9, 0xFE, 0xA4, 0xA4, 0xF0, 0x8F, 0xEB, 0x2E, 0xF0, 0xC5, 0xCF, 0xE4, 0xFE, 0x39, 0xCD, ++ 0xA4, 0xEA, 0xFC, 0x3C, 0xF0, 0x35, 0xCE, 0x2D, 0xFC, 0x3C, 0xE4, 0xFD, 0xE7, 0xA2, 0xEC, 0x22, ++ 0x13, 0xED, 0xFC, 0x13, 0xFE, 0x13, 0xEE, 0xFD, 0x22, 0xFF, 0x13, 0xEF, 0xFF, 0x33, 0xC3, 0xEF, ++ 0xED, 0xFE, 0x33, 0xEE, 0x33, 0xEC, 0xFD, 0x33, 0x73, 0xE5, 0x22, 0xFC, 0x7B, 0x3C, 0xE7, 0x30, ++ 0x79, 0x20, 0x7A, 0xFF, 0xEF, 0x76, 0xAF, 0x00, 0x12, 0x00, 0x7C, 0xFD, 0xFF, 0x7B, 0x40, 0x0D, ++ 0x09, 0x79, 0x20, 0x7A, 0xFD, 0xEF, 0x77, 0xAF, 0x0D, 0x12, 0x00, 0x7C, 0x7A, 0xFF, 0x7B, 0x40, ++ 0xAF, 0x11, 0x79, 0x20, 0x7C, 0xFD, 0xEF, 0x78, 0x40, 0x0D, 0x12, 0x00, 0x20, 0x7A, 0xFF, 0x7B, ++ 0x79, 0xAF, 0x17, 0x79, 0x00, 0x7C, 0xFD, 0xEF, 0x22, 0x40, 0x0D, 0x12, 0x79, 0xE5, 0x8A, 0x31, ++ 0x54, 0x33, 0x33, 0x33, 0x78, 0xE5, 0xFF, 0xF8, 0xE0, 0x54, 0x33, 0xC4, 0x90, 0x77, 0x45, 0x4F, ++ 0x7E, 0xF0, 0x00, 0x0D, 0x12, 0x00, 0x7F, 0x0D, 0x76, 0xAF, 0x4A, 0x2A, 0xFF, 0x03, 0x54, 0xEF, ++ 0xE0, 0xF2, 0x07, 0x90, 0xF0, 0x4F, 0xFC, 0x54, 0x60, 0x67, 0xE5, 0x22, 0x90, 0xCC, 0x31, 0x0E, ++ 0x54, 0xE0, 0x6A, 0x07, 0x44, 0xE0, 0xF0, 0xFE, 0x75, 0x22, 0xF0, 0x01, 0x65, 0x75, 0x2C, 0x64, ++ 0x67, 0xE5, 0x22, 0xFD, 0xCC, 0x31, 0x15, 0x60, 0xFF, 0xFC, 0xFD, 0xE4, 0x00, 0x7E, 0x14, 0xF1, ++ 0x77, 0x51, 0x9C, 0x7F, 0xE0, 0x6A, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, 0x30, 0xE0, 0x6B, 0x07, ++ 0x06, 0x7F, 0x0A, 0xE0, 0x64, 0x75, 0x5A, 0xD1, 0x97, 0x65, 0x75, 0x27, 0x60, 0x67, 0xE5, 0x22, ++ 0x31, 0x8A, 0x31, 0x16, 0x7E, 0x0F, 0xF1, 0xCE, 0x51, 0x9C, 0x7F, 0x00, 0x3F, 0x72, 0x75, 0x77, ++ 0xE0, 0x6A, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, 0x30, 0xE0, 0x6B, 0x07, 0xFF, 0xE4, 0x18, 0xE0, ++ 0x72, 0xE5, 0x5A, 0xD1, 0x72, 0x15, 0x0A, 0x60, 0xE0, 0x6A, 0x07, 0x90, 0x22, 0xF0, 0x01, 0x44, ++ 0x75, 0x27, 0x64, 0x75, 0xE4, 0x22, 0xB1, 0x65, 0xFB, 0xEF, 0xFC, 0xFD, 0xEE, 0xFF, 0x02, 0x24, ++ 0xFE, 0x00, 0x34, 0xFA, 0x83, 0x8A, 0x82, 0x8B, 0xF0, 0xA3, 0xF0, 0xE4, 0x01, 0x00, 0xBD, 0x0D, ++ 0x80, 0x64, 0xED, 0x0C, 0x22, 0xE3, 0x70, 0x4C, 0xE0, 0x6A, 0x07, 0x90, 0x7E, 0xF0, 0xFE, 0x54, ++ 0x51, 0x00, 0x7F, 0x05, 0x7F, 0x00, 0x7E, 0x77, 0x7D, 0x05, 0x7C, 0x9C, 0x8F, 0x25, 0x8E, 0x00, ++ 0x8D, 0x27, 0x8C, 0x26, 0xAD, 0xB6, 0xB1, 0x28, 0xAF, 0x27, 0xAC, 0x28, 0x8E, 0x25, 0xAE, 0x26, ++ 0x8C, 0x2A, 0x8F, 0x29, 0x75, 0x2C, 0x8D, 0x2B, 0x33, 0x75, 0x00, 0x32, 0x00, 0x34, 0x75, 0x40, ++ 0xD3, 0x01, 0x35, 0x75, 0x40, 0x94, 0x35, 0xE5, 0x00, 0x94, 0x34, 0xE5, 0x96, 0xA1, 0x02, 0x40, ++ 0xF5, 0x30, 0xF5, 0xE4, 0xC3, 0x2E, 0xF5, 0x2D, 0x33, 0x95, 0x2E, 0xE5, 0x40, 0x32, 0x95, 0xE4, ++ 0xE4, 0x7E, 0xA1, 0x02, 0xE5, 0xC3, 0x2F, 0xF5, 0xE4, 0x35, 0x95, 0x2F, 0x02, 0x40, 0x34, 0x95, ++ 0x30, 0xE5, 0x72, 0xA1, 0x31, 0xF5, 0x35, 0x25, 0x3C, 0xB4, 0x30, 0xE5, 0xB4, 0x31, 0xE5, 0x0B, ++ 0x97, 0xB1, 0x06, 0x3D, 0x3F, 0x8F, 0x3E, 0x8E, 0x3E, 0x8E, 0x97, 0xB1, 0x31, 0xAD, 0x3F, 0x8F, ++ 0x40, 0x8E, 0x99, 0xB1, 0x30, 0xAD, 0x41, 0x8F, 0x2B, 0xAE, 0x2C, 0xAF, 0x3A, 0x8E, 0x9D, 0xB1, ++ 0x31, 0xAD, 0x3B, 0x8F, 0x2B, 0xAE, 0x2C, 0xAF, 0x3C, 0x8E, 0x9D, 0xB1, 0x2D, 0xE5, 0x3D, 0x8F, ++ 0x40, 0x20, 0x94, 0xD3, 0x95, 0x40, 0x74, 0x37, 0x24, 0xE0, 0x25, 0x2D, 0xE4, 0x82, 0xF5, 0x94, ++ 0x83, 0xF5, 0x20, 0x34, 0x38, 0xF5, 0x93, 0xE4, 0xF5, 0x93, 0x01, 0x74, 0x25, 0x2D, 0xE5, 0x39, ++ 0xF5, 0x54, 0x24, 0xE0, 0x20, 0x34, 0xE4, 0x82, 0x93, 0xE4, 0x83, 0xF5, 0x93, 0x01, 0x74, 0xFE, ++ 0x9F, 0xE4, 0xC3, 0xFF, 0x9E, 0xE4, 0x37, 0xF5, 0x2F, 0x80, 0x36, 0xF5, 0xE0, 0x25, 0x2D, 0xE5, ++ 0x82, 0xF5, 0x94, 0x24, 0xF5, 0x20, 0x34, 0xE4, 0xF5, 0x93, 0xE4, 0x83, 0x93, 0x01, 0x74, 0x38, ++ 0x74, 0xC3, 0x39, 0xF5, 0x25, 0x2D, 0x95, 0x20, 0xF5, 0x94, 0x24, 0xE0, 0x20, 0x34, 0xE4, 0x82, ++ 0x93, 0xE4, 0x83, 0xF5, 0x01, 0x74, 0x36, 0xF5, 0xAE, 0x37, 0xF5, 0x93, 0xEE, 0x3D, 0xAF, 0x3C, ++ 0xFD, 0xE0, 0x95, 0x33, 0xAE, 0x06, 0xC0, 0xFC, 0x95, 0x33, 0xEE, 0x38, 0x55, 0x39, 0x85, 0xE0, ++ 0x53, 0xF5, 0x54, 0x8E, 0x06, 0xD0, 0x52, 0xF5, 0x04, 0xC0, 0x16, 0x31, 0x06, 0xC0, 0x05, 0xC0, ++ 0x40, 0xAE, 0x07, 0xC0, 0x33, 0xEE, 0x41, 0xAF, 0xFC, 0xFD, 0xE0, 0x95, 0x36, 0xAE, 0x06, 0xC0, ++ 0xE0, 0x95, 0x33, 0xEE, 0x8E, 0x55, 0x37, 0x85, 0xF5, 0x53, 0xF5, 0x54, 0x31, 0x06, 0xD0, 0x52, ++ 0xD0, 0x03, 0xD0, 0x16, 0xD0, 0x01, 0xD0, 0x02, 0xF5, 0x2B, 0xEF, 0x00, 0xF5, 0x3A, 0xEE, 0x45, ++ 0xF5, 0x39, 0xED, 0x44, 0xF5, 0x38, 0xEC, 0x43, 0xAF, 0x40, 0xAE, 0x42, 0x95, 0x33, 0xEE, 0x41, ++ 0xC0, 0xFC, 0xFD, 0xE0, 0xEE, 0x38, 0xAE, 0x06, 0x85, 0xE0, 0x95, 0x33, 0x54, 0x8E, 0x55, 0x39, ++ 0x52, 0xF5, 0x53, 0xF5, 0x16, 0x31, 0x06, 0xD0, 0x05, 0xC0, 0x04, 0xC0, 0x07, 0xC0, 0x06, 0xC0, ++ 0x3D, 0xAF, 0x3C, 0xAE, 0xE0, 0x95, 0x33, 0xEE, 0x06, 0xC0, 0xFC, 0xFD, 0x33, 0xEE, 0x36, 0xAE, ++ 0x37, 0x85, 0xE0, 0x95, 0xF5, 0x54, 0x8E, 0x55, 0xD0, 0x52, 0xF5, 0x53, 0xD0, 0x16, 0x31, 0x06, ++ 0xD0, 0x02, 0xD0, 0x03, 0xC3, 0x00, 0xD0, 0x01, 0x49, 0xF5, 0x9B, 0xEF, 0x48, 0xF5, 0x9A, 0xEE, ++ 0x47, 0xF5, 0x99, 0xED, 0x46, 0xF5, 0x98, 0xEC, 0xF5, 0x4C, 0xF5, 0xE4, 0x4A, 0x3E, 0x85, 0x4D, ++ 0xAF, 0x4B, 0x3F, 0x85, 0xAD, 0x4C, 0xAE, 0x4D, 0x31, 0x4A, 0xAC, 0x4B, 0x8E, 0x4D, 0x8F, 0x6D, ++ 0x8C, 0x4B, 0x8D, 0x4C, 0x25, 0x4D, 0xE5, 0x4A, 0xE5, 0x4D, 0xF5, 0x45, 0xF5, 0x44, 0x35, 0x4C, ++ 0x35, 0x4B, 0xE5, 0x4C, 0xE5, 0x4B, 0xF5, 0x43, 0xF5, 0x42, 0x35, 0x4A, 0xAA, 0x4B, 0xAB, 0x4A, ++ 0xAF, 0x30, 0xAD, 0x4A, 0xD1, 0x29, 0xAE, 0x2A, 0x4C, 0xF5, 0xE4, 0x41, 0x3E, 0x85, 0x4D, 0xF5, ++ 0x4B, 0x3F, 0x85, 0x4A, 0x4C, 0xAE, 0x4D, 0xAF, 0x4A, 0xAC, 0x4B, 0xAD, 0x4D, 0x8F, 0x6D, 0x31, ++ 0x4B, 0x8D, 0x4C, 0x8E, 0xE5, 0xC3, 0x4A, 0x8C, 0xF5, 0x45, 0x95, 0x4D, 0x95, 0x4C, 0xE5, 0x4D, ++ 0xE5, 0x4C, 0xF5, 0x44, 0xF5, 0x43, 0x95, 0x4B, 0x95, 0x4A, 0xE5, 0x4B, 0xAB, 0x4A, 0xF5, 0x42, ++ 0xAD, 0x4A, 0xAA, 0x4B, 0xAE, 0x2A, 0xAF, 0x31, 0xE4, 0x41, 0xD1, 0x29, 0x4D, 0xF5, 0x4C, 0xF5, ++ 0x85, 0x4A, 0x3A, 0x85, 0x4D, 0xAF, 0x4B, 0x3B, 0x4B, 0xAD, 0x4C, 0xAE, 0x6D, 0x31, 0x4A, 0xAC, ++ 0x4C, 0x8E, 0x4D, 0x8F, 0x4A, 0x8C, 0x4B, 0x8D, 0x49, 0x25, 0x4D, 0xE5, 0x4C, 0xE5, 0x4D, 0xF5, ++ 0x4C, 0xF5, 0x48, 0x35, 0x47, 0x35, 0x4B, 0xE5, 0x4A, 0xE5, 0x4B, 0xF5, 0x4A, 0xF5, 0x46, 0x35, ++ 0x4A, 0xAA, 0x4B, 0xAB, 0x3D, 0xD1, 0x30, 0xAD, 0xF5, 0x4C, 0xF5, 0xE4, 0x4A, 0x3A, 0x85, 0x4D, ++ 0xAF, 0x4B, 0x3B, 0x85, 0xAD, 0x4C, 0xAE, 0x4D, 0x31, 0x4A, 0xAC, 0x4B, 0x8E, 0x4D, 0x8F, 0x6D, ++ 0x8C, 0x4B, 0x8D, 0x4C, 0x4D, 0xE5, 0xC3, 0x4A, 0x4D, 0xF5, 0x49, 0x95, 0x48, 0x95, 0x4C, 0xE5, ++ 0x4B, 0xE5, 0x4C, 0xF5, 0x4B, 0xF5, 0x47, 0x95, 0x46, 0x95, 0x4A, 0xE5, 0x4B, 0xAB, 0x4A, 0xF5, ++ 0x31, 0xAD, 0x4A, 0xAA, 0x30, 0x05, 0x3D, 0xD1, 0x2D, 0x25, 0x33, 0xE5, 0x2F, 0x05, 0x2D, 0xF5, ++ 0x31, 0xE5, 0xF6, 0x41, 0xE4, 0x30, 0xF5, 0x04, 0x2E, 0x05, 0x2D, 0xF5, 0x32, 0xE5, 0xE7, 0x41, ++ 0x32, 0xF5, 0x13, 0xC3, 0xF5, 0x13, 0x33, 0xE5, 0x25, 0x35, 0xE5, 0x33, 0xE5, 0x35, 0xF5, 0xE0, ++ 0x34, 0xF5, 0x33, 0x34, 0xAD, 0x22, 0xD3, 0x41, 0xAE, 0x2A, 0xAF, 0x30, 0x8E, 0x82, 0x8F, 0x29, ++ 0xF0, 0x75, 0xED, 0x83, 0x82, 0x25, 0xA4, 0x02, 0xF0, 0xE5, 0x82, 0xF5, 0x83, 0xF5, 0x83, 0x35, ++ 0xE0, 0xA3, 0xFE, 0xE0, 0x29, 0x8E, 0x22, 0xFF, 0x2B, 0x8C, 0x2A, 0x8F, 0x2F, 0x75, 0x2C, 0x8D, ++ 0x30, 0x10, 0xD2, 0x01, 0x2F, 0x85, 0x11, 0x10, 0x90, 0x2F, 0xE5, 0x2D, 0x25, 0x93, 0xD6, 0x20, ++ 0xC2, 0x2E, 0xF5, 0xE0, 0x74, 0x0A, 0x80, 0x10, 0xF5, 0x2D, 0x25, 0x40, 0xD2, 0x2E, 0x05, 0x2D, ++ 0xD3, 0x2E, 0xE5, 0x10, 0x48, 0x40, 0x2D, 0x95, 0x99, 0xB1, 0x2D, 0xAD, 0x31, 0x8F, 0x30, 0x8E, ++ 0x99, 0xB1, 0x2E, 0xAD, 0x07, 0xAB, 0x06, 0xAA, 0x2A, 0xAF, 0x2D, 0xAD, 0x41, 0xD1, 0x29, 0xAE, ++ 0x30, 0xAA, 0x31, 0xAB, 0x2A, 0xAF, 0x2E, 0xAD, 0x41, 0xD1, 0x29, 0xAE, 0x2C, 0xAF, 0x2D, 0xAD, ++ 0x9D, 0xB1, 0x2B, 0xAE, 0x31, 0x8F, 0x30, 0x8E, 0x2C, 0xAF, 0x2E, 0xAD, 0x9D, 0xB1, 0x2B, 0xAE, ++ 0x07, 0xAB, 0x06, 0xAA, 0x3D, 0xD1, 0x2D, 0xAD, 0x30, 0xAA, 0x31, 0xAB, 0x3D, 0xD1, 0x2E, 0xAD, ++ 0x05, 0x90, 0x10, 0x30, 0xC3, 0x2F, 0xE5, 0x2F, 0x85, 0x40, 0x40, 0x94, 0xAE, 0x2C, 0xAF, 0x22, ++ 0x8E, 0x82, 0x8F, 0x2B, 0xF0, 0x75, 0xED, 0x83, 0x82, 0x25, 0xA4, 0x02, 0xF0, 0xE5, 0x82, 0xF5, ++ 0x83, 0xF5, 0x83, 0x35, 0xEB, 0xA3, 0xF0, 0xEA, 0x07, 0xAD, 0x22, 0xF0, 0xE0, 0x6A, 0x07, 0x90, ++ 0xE4, 0xF0, 0xFE, 0x54, 0xE0, 0x25, 0xEC, 0xFC, 0x82, 0xF5, 0x00, 0x24, 0xF5, 0x05, 0x34, 0xE4, ++ 0xA3, 0xFE, 0xE0, 0x83, 0x08, 0x05, 0xA8, 0xE0, 0x33, 0xC3, 0x05, 0x80, 0xD8, 0xCE, 0x33, 0xCE, ++ 0xF0, 0x75, 0xFF, 0xF9, 0x24, 0xA4, 0xEC, 0x02, 0xE5, 0x82, 0xF5, 0x9C, 0xF5, 0x00, 0x34, 0xF0, ++ 0xA3, 0xFA, 0xE0, 0x83, 0xEA, 0xFF, 0x2F, 0xE0, 0xF0, 0x75, 0xFE, 0x3E, 0x24, 0xA4, 0xEC, 0x02, ++ 0xE5, 0x82, 0xF5, 0x9C, 0xF5, 0x00, 0x34, 0xF0, 0xA3, 0xF0, 0xEE, 0x83, 0xBC, 0x0C, 0xF0, 0xEF, ++ 0xE5, 0x22, 0xB3, 0x80, 0x1F, 0xE0, 0x20, 0x7A, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x33, 0x79, ++ 0x90, 0x7A, 0xE5, 0xF4, 0xE1, 0x30, 0x3E, 0x08, 0xF0, 0xE4, 0xE0, 0x05, 0x74, 0xE0, 0x04, 0x80, ++ 0xF5, 0xE4, 0xF0, 0x2E, 0x7B, 0x1D, 0x80, 0x78, 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x3A, ++ 0x08, 0x90, 0x7A, 0xE5, 0x05, 0xE1, 0x30, 0x3E, 0x80, 0xF0, 0xE4, 0xE0, 0x40, 0x74, 0xE0, 0x04, ++ 0x01, 0x78, 0x75, 0xF0, 0x0F, 0x7D, 0xCE, 0x31, 0xFF, 0xE4, 0x00, 0x7C, 0x28, 0x12, 0x14, 0xF1, ++ 0x6A, 0x07, 0x90, 0x26, 0xF0, 0x01, 0x44, 0xE0, 0x75, 0x2A, 0x64, 0x75, 0xE4, 0x22, 0x68, 0x65, ++ 0x01, 0x7F, 0xFC, 0xFD, 0x26, 0x8C, 0x25, 0x8F, 0x07, 0x90, 0x27, 0x8D, 0xFE, 0x54, 0xE0, 0x6A, ++ 0x04, 0x28, 0x75, 0xF0, 0xE4, 0x00, 0x29, 0x75, 0x25, 0xE5, 0xFE, 0xFF, 0x40, 0x70, 0x01, 0x64, ++ 0xF9, 0x0F, 0x54, 0xEF, 0x0C, 0x70, 0x7A, 0xE5, 0x64, 0x20, 0x90, 0xE9, 0x95, 0x33, 0xFD, 0x93, ++ 0x13, 0x80, 0xFC, 0xE0, 0x24, 0xE0, 0x25, 0xE9, 0xE4, 0x82, 0xF5, 0x74, 0x83, 0xF5, 0x20, 0x34, ++ 0x74, 0xFC, 0x93, 0xE4, 0xE5, 0xFD, 0x93, 0x01, 0x02, 0x24, 0xFB, 0x29, 0x28, 0xE5, 0x29, 0xF5, ++ 0xF5, 0x00, 0x34, 0xFA, 0x8A, 0x82, 0x8B, 0x28, 0xA3, 0xF0, 0xEC, 0x83, 0x19, 0x80, 0xF0, 0xED, ++ 0x24, 0xFD, 0x29, 0xE5, 0xE5, 0x29, 0xF5, 0x02, 0x00, 0x34, 0xFC, 0x28, 0x82, 0x8D, 0x28, 0xF5, ++ 0x26, 0xE5, 0x83, 0x8C, 0x27, 0xE5, 0xA3, 0xF0, 0x00, 0xBF, 0x0F, 0xF0, 0x70, 0xEF, 0x0E, 0x01, ++ 0x01, 0x64, 0xEE, 0x03, 0x51, 0x22, 0x94, 0x70, 0xB8, 0x2A, 0x12, 0x98, 0x94, 0xD3, 0x76, 0xE5, ++ 0x75, 0x07, 0x40, 0x03, 0x65, 0x75, 0x2C, 0x64, 0x64, 0x75, 0x22, 0xDF, 0x12, 0x65, 0x75, 0x22, ++ 0x12, 0x98, 0x51, 0x22, 0x76, 0xE5, 0x6B, 0x2C, 0x40, 0x03, 0x94, 0xD3, 0x28, 0x64, 0x75, 0x07, ++ 0x22, 0x4E, 0x65, 0x75, 0x75, 0x22, 0x64, 0x75, 0x8E, 0x22, 0x3D, 0x65, 0x05, 0x2E, 0x8F, 0x2D, ++ 0x70, 0x2E, 0xE5, 0x2E, 0x14, 0x2D, 0x05, 0x02, 0x83, 0x8E, 0x82, 0xF5, 0x2E, 0x05, 0xF0, 0xED, ++ 0x2D, 0xAE, 0x2E, 0xE5, 0x2D, 0x05, 0x02, 0x70, 0x8E, 0x82, 0xF5, 0x14, 0x05, 0xF0, 0xEB, 0x83, ++ 0xAE, 0x2E, 0xE5, 0x2E, 0x05, 0x02, 0x70, 0x2D, 0x82, 0xF5, 0x14, 0x2D, 0x31, 0xE5, 0x83, 0x8E, ++ 0xE5, 0x2E, 0x05, 0xF0, 0x70, 0x2D, 0xAE, 0x2E, 0x14, 0x2D, 0x05, 0x02, 0x83, 0x8E, 0x82, 0xF5, ++ 0x05, 0xF0, 0x32, 0xE5, 0xAE, 0x2E, 0xE5, 0x2E, 0x05, 0x02, 0x70, 0x2D, 0x82, 0xF5, 0x14, 0x2D, ++ 0x33, 0xE5, 0x83, 0x8E, 0x07, 0x90, 0x22, 0xF0, 0xFE, 0x54, 0xE0, 0x6A, 0xF9, 0x54, 0xE0, 0xF0, ++ 0x90, 0xF0, 0x04, 0x44, 0x01, 0x74, 0x6C, 0x07, 0x6D, 0x07, 0x90, 0xF0, 0xF0, 0xFF, 0x74, 0xE0, ++ 0xE0, 0x6E, 0x07, 0x90, 0x90, 0xF0, 0xFF, 0x74, 0xE4, 0xE0, 0x6F, 0x07, 0xFF, 0x7B, 0x22, 0xF0, ++ 0x4F, 0x79, 0x20, 0x7A, 0xE4, 0xF4, 0x03, 0x12, 0x77, 0x75, 0x76, 0xF5, 0x01, 0x78, 0x75, 0x07, ++ 0x75, 0x03, 0x79, 0x75, 0x7C, 0x75, 0x00, 0x7B, 0xAF, 0x7B, 0xAE, 0x00, 0x08, 0x24, 0xEF, 0x7C, ++ 0x3E, 0xE4, 0x75, 0xF5, 0x7A, 0xE5, 0x74, 0xF5, 0x70, 0x3E, 0x08, 0x90, 0xF0, 0x14, 0x74, 0x05, ++ 0x0C, 0x74, 0x03, 0x80, 0x36, 0x08, 0x90, 0xF0, 0x74, 0xF0, 0x03, 0x74, 0x08, 0x90, 0xF0, 0x01, ++ 0xF0, 0x11, 0x74, 0x40, 0x74, 0x43, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x0E, 0xF0, 0x01, 0x74, 0x42, ++ 0x04, 0x44, 0x08, 0x90, 0x0F, 0x27, 0x12, 0xF0, 0x64, 0x75, 0x26, 0x11, 0xF9, 0x65, 0x75, 0x21, ++ 0x60, 0x66, 0xE5, 0x22, 0x7A, 0xFF, 0x7B, 0x29, 0x12, 0x1D, 0x79, 0x20, 0x64, 0x75, 0xF4, 0x03, ++ 0x20, 0x65, 0x75, 0x29, 0x90, 0x01, 0x67, 0x75, 0x44, 0xE0, 0xC8, 0x01, 0x09, 0x7F, 0xF0, 0x08, ++ 0x90, 0x68, 0x03, 0x12, 0x54, 0xE0, 0x07, 0x07, 0x44, 0xE0, 0xF0, 0xFE, 0x06, 0x90, 0xF0, 0x10, ++ 0x13, 0xC4, 0xE0, 0x12, 0x07, 0x64, 0x07, 0x54, 0x20, 0xE5, 0x0A, 0x70, 0xC3, 0x05, 0xE0, 0x20, ++ 0x06, 0xE0, 0x30, 0x13, 0x75, 0x2A, 0x64, 0x75, 0x63, 0xE5, 0x7D, 0x65, 0x04, 0x70, 0x65, 0x65, ++ 0x64, 0x65, 0x62, 0xE5, 0x64, 0x85, 0x09, 0x60, 0x63, 0x65, 0x85, 0x62, 0x90, 0x01, 0x67, 0x75, ++ 0xF5, 0xE0, 0x13, 0x06, 0xA9, 0x62, 0xAA, 0x73, 0x27, 0x03, 0x12, 0x63, 0x22, 0x67, 0xF5, 0xE4, ++ 0x54, 0xC4, 0x73, 0xE5, 0xE5, 0x24, 0xF5, 0x07, 0xF5, 0x0F, 0x54, 0x73, 0x61, 0x07, 0x90, 0x7A, ++ 0xE4, 0xF0, 0x50, 0x74, 0xF5, 0x07, 0x90, 0xF0, 0xE4, 0xF0, 0x03, 0x74, 0xF0, 0xF9, 0x07, 0x90, ++ 0x04, 0xF5, 0x07, 0x90, 0x5C, 0x08, 0x90, 0xF0, 0xE4, 0xF0, 0x03, 0x74, 0xF0, 0x5F, 0x08, 0x90, ++ 0xF0, 0x5E, 0x08, 0x90, 0xF0, 0x5D, 0x08, 0x90, 0x04, 0x60, 0x08, 0x90, 0x5C, 0x08, 0x90, 0xF0, ++ 0x0D, 0x90, 0xE4, 0xF0, 0x0D, 0x7E, 0xF0, 0x01, 0x4A, 0x51, 0x01, 0x7F, 0x74, 0x45, 0x0D, 0x90, ++ 0x0D, 0x90, 0xF0, 0x80, 0x0D, 0x90, 0xF0, 0x65, 0x0D, 0x90, 0xF0, 0x47, 0x0D, 0x90, 0xF0, 0x67, ++ 0xF0, 0xFF, 0x74, 0x89, 0xF1, 0x07, 0x90, 0xE4, 0xF2, 0x07, 0x90, 0xF0, 0xE5, 0xF0, 0xFC, 0x74, ++ 0xE5, 0x05, 0x60, 0x7A, 0x08, 0x01, 0xB4, 0x24, 0x74, 0x35, 0x08, 0x90, 0x06, 0x80, 0xF0, 0x19, ++ 0x74, 0x35, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x31, 0xF0, 0x0B, 0x74, 0x3D, 0x08, 0x90, 0x7A, 0xE5, ++ 0xE0, 0x06, 0x70, 0x3E, 0x80, 0xF0, 0x4C, 0x74, 0x2E, 0x74, 0xE0, 0x04, 0x3D, 0x08, 0x90, 0xF0, ++ 0x90, 0xF0, 0x09, 0x74, 0x07, 0x74, 0x38, 0x08, 0xF0, 0x05, 0x74, 0xF0, 0x74, 0xFF, 0x07, 0x90, ++ 0x07, 0x90, 0xF0, 0x08, 0xF0, 0x03, 0x74, 0xFE, 0x74, 0xFD, 0x07, 0x90, 0x00, 0x00, 0xF0, 0x07, ++ 0x90, 0x00, 0x00, 0x00, 0x02, 0x74, 0xFE, 0x07, 0xFD, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x06, 0x74, ++ 0x03, 0x74, 0x36, 0x08, 0x37, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x14, 0x74, 0x01, 0x74, 0x36, 0x08, ++ 0x6A, 0x07, 0x90, 0xF0, 0xF0, 0xF9, 0x54, 0xE0, 0x74, 0x6C, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x01, ++ 0x04, 0xE4, 0xE0, 0x6D, 0x6E, 0x07, 0x90, 0xF0, 0xF0, 0xFF, 0x74, 0xE0, 0xE0, 0x6F, 0x07, 0x90, ++ 0x07, 0x90, 0xF0, 0xE4, 0xF0, 0xE4, 0xE0, 0x70, 0x77, 0xF5, 0x76, 0xF5, 0xF5, 0x01, 0x78, 0x75, ++ 0x00, 0x7B, 0x75, 0x79, 0xE5, 0x00, 0x7C, 0x75, 0x07, 0x70, 0x14, 0x24, 0x75, 0x26, 0x64, 0x75, ++ 0x75, 0x22, 0xB3, 0x65, 0x65, 0x75, 0x2A, 0x64, 0x25, 0x8E, 0x22, 0xA8, 0x01, 0x7D, 0x26, 0x8F, ++ 0xFF, 0x2F, 0x20, 0x74, 0x85, 0xFE, 0x3E, 0xE4, 0x25, 0x85, 0x82, 0x26, 0x82, 0x8F, 0xE0, 0x83, ++ 0x0D, 0xF0, 0x83, 0x8E, 0x22, 0xE9, 0x04, 0xBD, 0x10, 0x60, 0x67, 0xE5, 0x20, 0x7A, 0xFF, 0x7B, ++ 0x03, 0x12, 0x25, 0x79, 0x07, 0x07, 0x90, 0xF4, 0xF0, 0x01, 0x44, 0xE0, 0x7A, 0xFF, 0x7B, 0x22, ++ 0x12, 0x2C, 0x79, 0x20, 0x01, 0x90, 0xF4, 0x03, 0xF7, 0x54, 0xE0, 0xC8, 0x54, 0x20, 0xE5, 0xF0, ++ 0xE5, 0x20, 0xF5, 0xEF, 0xF5, 0xEF, 0x54, 0x21, 0x61, 0x07, 0x90, 0x21, 0xE4, 0xF0, 0x50, 0x74, ++ 0x02, 0x60, 0x75, 0xF0, 0x22, 0x0B, 0x61, 0x75, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x43, 0x79, ++ 0x22, 0x64, 0x75, 0xF4, 0x22, 0x12, 0x65, 0x75, 0xE4, 0xFF, 0x26, 0x75, 0x28, 0xF5, 0x27, 0xF5, ++ 0x25, 0x75, 0x29, 0xF5, 0x71, 0x25, 0xAF, 0x01, 0xE5, 0x2A, 0x8F, 0x40, 0x26, 0x95, 0xC3, 0x2A, ++ 0x2A, 0x85, 0x03, 0x50, 0xD3, 0x2A, 0xE5, 0x26, 0x03, 0x40, 0x27, 0x95, 0xE5, 0x27, 0x2A, 0x85, ++ 0xF5, 0x29, 0x25, 0x2A, 0x28, 0x35, 0xE4, 0x29, 0x25, 0x05, 0x28, 0xF5, 0x94, 0xC3, 0x25, 0xE5, ++ 0xE5, 0xD2, 0x40, 0x40, 0xAF, 0x7B, 0xAE, 0x77, 0x8E, 0x09, 0x70, 0x7C, 0x75, 0x2C, 0x8F, 0x2B, ++ 0x19, 0x80, 0x07, 0x77, 0xF5, 0x04, 0x24, 0xEF, 0xF5, 0x3E, 0xE4, 0x2C, 0x77, 0xF5, 0xE4, 0x2B, ++ 0x27, 0x74, 0x76, 0x05, 0x7C, 0xF5, 0x7C, 0x25, 0xF5, 0x7B, 0x35, 0xE4, 0x71, 0xFF, 0xE4, 0x7B, ++ 0xE5, 0x32, 0x8F, 0x40, 0x78, 0x28, 0xAE, 0x29, 0x13, 0xC3, 0xCE, 0x06, 0xF9, 0xD8, 0x13, 0xCE, ++ 0xF5, 0xE4, 0x31, 0xF5, 0xAD, 0x26, 0xAB, 0x33, 0xAE, 0x2C, 0xAF, 0x27, 0xCB, 0x27, 0x02, 0x2B, ++ 0xF0, 0x75, 0x2D, 0x8F, 0x24, 0xA4, 0xEF, 0x02, 0xE5, 0x82, 0xF5, 0x9C, 0xF5, 0x00, 0x34, 0xF0, ++ 0xA3, 0xFE, 0xE0, 0x83, 0x06, 0xAA, 0xFB, 0xE0, 0x95, 0x33, 0xEE, 0xFF, 0xC0, 0xFC, 0xFD, 0xE0, ++ 0xEE, 0x07, 0xC0, 0x06, 0x8F, 0xE0, 0x95, 0x33, 0xF5, 0x54, 0x8E, 0x55, 0xD0, 0x52, 0xF5, 0x53, ++ 0x12, 0x06, 0xD0, 0x07, 0x31, 0x8F, 0x16, 0x21, 0x2F, 0x8D, 0x30, 0x8E, 0x2D, 0xE5, 0x2E, 0x8C, ++ 0x00, 0x24, 0xE0, 0x25, 0x34, 0xE4, 0x82, 0xF5, 0xE0, 0x83, 0xF5, 0x05, 0xFB, 0xE0, 0xA3, 0xFA, ++ 0xEE, 0x02, 0xAE, 0xFF, 0xFD, 0xE0, 0x95, 0x33, 0xC0, 0x06, 0xC0, 0xFC, 0x95, 0x33, 0xEE, 0x07, ++ 0x8E, 0x55, 0x8F, 0xE0, 0xF5, 0x53, 0xF5, 0x54, 0xD0, 0x07, 0xD0, 0x52, 0x16, 0x21, 0x12, 0x06, ++ 0xF5, 0x2F, 0x31, 0xE5, 0x3E, 0x30, 0xE5, 0x31, 0x2F, 0xE5, 0x30, 0xF5, 0xE5, 0x2F, 0xF5, 0x3D, ++ 0x2E, 0xF5, 0x3C, 0x2E, 0x30, 0xAE, 0x31, 0xAF, 0x75, 0xFC, 0x2F, 0xAD, 0x36, 0x8F, 0x1F, 0x32, ++ 0x34, 0x8D, 0x35, 0x8E, 0x33, 0xE5, 0x33, 0x8C, 0xE5, 0xFF, 0x34, 0x45, 0xE5, 0x07, 0x42, 0x35, ++ 0xEF, 0x07, 0x42, 0x36, 0x36, 0x75, 0x09, 0x70, 0xF5, 0x35, 0xF5, 0x01, 0xE5, 0x33, 0xF5, 0x34, ++ 0x17, 0xE7, 0x20, 0x33, 0x36, 0xAF, 0x32, 0x15, 0x34, 0xAD, 0x35, 0xAE, 0x21, 0x12, 0x33, 0xAC, ++ 0x8E, 0x36, 0x8F, 0x7C, 0x8C, 0x34, 0x8D, 0x35, 0xAF, 0xE4, 0x80, 0x33, 0xE4, 0x00, 0x7E, 0x33, ++ 0x25, 0x32, 0xE5, 0xFB, 0xAD, 0x32, 0xF5, 0xE0, 0x12, 0x06, 0xAC, 0x07, 0x30, 0xEE, 0xC0, 0x02, ++ 0x32, 0x05, 0x07, 0xE7, 0x80, 0x00, 0x7E, 0xFF, 0x07, 0x78, 0xEF, 0x0B, 0xCE, 0x13, 0xC3, 0xCE, ++ 0xFF, 0xF9, 0xD8, 0x13, 0xD9, 0x03, 0xBB, 0x0B, 0xFC, 0xE4, 0x32, 0xAF, 0x55, 0x75, 0xFE, 0xFD, ++ 0xC0, 0x54, 0x75, 0xA8, 0x52, 0xF5, 0x53, 0xF5, 0x8F, 0x16, 0x21, 0x12, 0x8D, 0x35, 0x8E, 0x36, ++ 0xE4, 0x33, 0x8C, 0x34, 0x36, 0xF5, 0x36, 0x25, 0x80, 0x34, 0x35, 0xE5, 0x35, 0xE4, 0x35, 0xF5, ++ 0xE4, 0x34, 0xF5, 0x34, 0x33, 0xF5, 0x33, 0x35, 0xE5, 0x22, 0x34, 0xAF, 0xAE, 0x1F, 0x70, 0x78, ++ 0xEF, 0x7C, 0xAF, 0x7B, 0x26, 0xF5, 0x10, 0x24, 0x25, 0xF5, 0x3E, 0xE4, 0x27, 0x74, 0x76, 0x05, ++ 0x7C, 0xF5, 0x7C, 0x25, 0xF5, 0x7B, 0x35, 0xE4, 0x01, 0x78, 0x75, 0x7B, 0x79, 0xE5, 0x24, 0x80, ++ 0x7C, 0xAF, 0x7B, 0xAE, 0x24, 0xEF, 0x0E, 0x70, 0xE4, 0x26, 0xF5, 0x15, 0x75, 0x25, 0xF5, 0x3E, ++ 0x0E, 0x80, 0x03, 0x79, 0xF5, 0x1A, 0x24, 0xEF, 0xF5, 0x3E, 0xE4, 0x26, 0x79, 0xF5, 0xE4, 0x25, ++ 0xFF, 0xE4, 0x78, 0xF5, 0x07, 0xC0, 0x40, 0x71, 0x40, 0x71, 0x08, 0x7F, 0x10, 0x7F, 0x07, 0xC0, ++ 0x07, 0xC0, 0x40, 0x71, 0x40, 0x71, 0x18, 0x7F, 0x20, 0x7F, 0x07, 0xC0, 0x33, 0x8F, 0x40, 0x71, ++ 0x31, 0xD0, 0x32, 0xD0, 0x05, 0xD0, 0x03, 0xD0, 0x25, 0xAE, 0x26, 0xAF, 0x7B, 0xCB, 0x27, 0x02, ++ 0x79, 0x20, 0x7A, 0xFF, 0xF4, 0x03, 0x12, 0x49, 0x75, 0x00, 0x7B, 0x75, 0xF5, 0xE4, 0x00, 0x7C, ++ 0x01, 0x78, 0x75, 0x76, 0x64, 0x75, 0x77, 0xF5, 0x3D, 0x65, 0x75, 0x22, 0xE5, 0x1F, 0xB1, 0x22, ++ 0x03, 0x94, 0xD3, 0x76, 0x64, 0x75, 0x07, 0x40, 0xB5, 0x65, 0x75, 0x2D, 0x30, 0x73, 0xE5, 0x22, ++ 0x17, 0x30, 0x06, 0xE7, 0xFA, 0x80, 0x00, 0x03, 0x75, 0x21, 0x64, 0x75, 0x90, 0x22, 0xF9, 0x65, ++ 0xF5, 0xE0, 0x46, 0x08, 0x30, 0x73, 0xE5, 0x25, 0xFF, 0x7B, 0x0E, 0xE7, 0x55, 0x79, 0x20, 0x7A, ++ 0x7C, 0xFD, 0x25, 0xE5, 0x40, 0x0D, 0x12, 0x00, 0x75, 0xE5, 0x75, 0x05, 0x02, 0x70, 0x74, 0xAE, ++ 0xF5, 0x14, 0x74, 0x05, 0xE5, 0x83, 0x8E, 0x82, 0x7A, 0xE5, 0xF0, 0x25, 0x26, 0xF5, 0x07, 0x70, ++ 0x80, 0x14, 0x27, 0x75, 0x00, 0x26, 0x75, 0x06, 0xE5, 0x0C, 0x27, 0x75, 0x75, 0x1F, 0x70, 0x77, ++ 0x76, 0x05, 0x07, 0x77, 0x7C, 0x25, 0x27, 0x74, 0x35, 0xE4, 0x7C, 0xF5, 0xAE, 0x7B, 0xF5, 0x7B, ++ 0xEF, 0x7C, 0xAF, 0x7B, 0x75, 0xF5, 0x08, 0x24, 0x74, 0xF5, 0x3E, 0xE4, 0x77, 0x15, 0x30, 0x80, ++ 0xE0, 0x3E, 0x08, 0x90, 0x7C, 0x00, 0x7E, 0xFF, 0x12, 0xA1, 0x7D, 0x00, 0x26, 0x8E, 0xC0, 0x02, ++ 0x40, 0x74, 0x27, 0x8F, 0x27, 0xF5, 0x27, 0x25, 0xF5, 0x26, 0x35, 0xE4, 0xAE, 0x27, 0xE5, 0x26, ++ 0xCE, 0x07, 0x78, 0x26, 0x13, 0xCE, 0x13, 0xC3, 0x27, 0xF5, 0xF9, 0xD8, 0x08, 0x90, 0x26, 0x8E, ++ 0xF0, 0x27, 0xE5, 0x3E, 0x7A, 0xFF, 0x7B, 0x22, 0x12, 0x5D, 0x79, 0x20, 0x7B, 0x75, 0xF4, 0x03, ++ 0x00, 0x7C, 0x75, 0x00, 0x75, 0x76, 0xF5, 0xE4, 0x65, 0x75, 0x2D, 0x64, 0x67, 0xE5, 0x22, 0xCE, ++ 0x21, 0x12, 0x0B, 0x60, 0x76, 0x80, 0x78, 0x8A, 0x0E, 0x76, 0x08, 0x00, 0x12, 0x80, 0x7F, 0x22, ++ 0x06, 0x50, 0x48, 0x0E, 0x75, 0x2D, 0x64, 0x75, 0xAE, 0x22, 0xEB, 0x65, 0x8F, 0x7C, 0xAF, 0x7B, ++ 0xEF, 0x83, 0x8E, 0x82, 0x82, 0xF5, 0x1F, 0x24, 0x83, 0xF5, 0x3E, 0xE4, 0xAE, 0xF0, 0x4D, 0x74, ++ 0x8F, 0x7C, 0xAF, 0x7B, 0xEF, 0x83, 0x8E, 0x82, 0x82, 0xF5, 0x20, 0x24, 0x83, 0xF5, 0x3E, 0xE4, ++ 0xAE, 0xF0, 0x4D, 0x74, 0x8F, 0x7C, 0xAF, 0x7B, 0xEF, 0x83, 0x8E, 0x82, 0x82, 0xF5, 0x21, 0x24, ++ 0x83, 0xF5, 0x3E, 0xE4, 0xAE, 0xF0, 0x4D, 0x74, 0x8F, 0x7C, 0xAF, 0x7B, 0xEF, 0x83, 0x8E, 0x82, ++ 0x82, 0xF5, 0x22, 0x24, 0x83, 0xF5, 0x3E, 0xE4, 0xAE, 0xF0, 0x4D, 0x74, 0x8F, 0x7C, 0xAF, 0x7B, ++ 0xEF, 0x83, 0x8E, 0x82, 0x82, 0xF5, 0x23, 0x24, 0x83, 0xF5, 0x3E, 0xE4, 0xE5, 0xF0, 0x4D, 0x74, ++ 0x1F, 0x03, 0xB4, 0x76, 0xE0, 0x89, 0x0D, 0x90, 0xF0, 0x24, 0x00, 0x90, 0xE0, 0x8A, 0x0D, 0x90, ++ 0xF0, 0x25, 0x00, 0x90, 0xE0, 0x8B, 0x0D, 0x90, 0xF0, 0x26, 0x00, 0x90, 0x75, 0x2A, 0x64, 0x75, ++ 0x05, 0x22, 0x68, 0x65, 0x25, 0x27, 0x74, 0x76, 0xE4, 0x7C, 0xF5, 0x7C, 0x7B, 0xF5, 0x7B, 0x35, ++ 0x00, 0x00, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++}; ++ ++/* GPHY firmware PHY-1V5-22F-IP-VR9-A22-T4406 */ ++static const unsigned char gphy_fe_fw_data_a12 [] = { ++ 0x80, 0x41, 0x03, 0x02, 0x32, 0x32, 0x32, 0x00, 0x80, 0x32, 0x32, 0x32, 0x7F, 0x54, 0xEF, 0xF9, ++ 0x80, 0x22, 0x99, 0xF5, 0x00, 0x00, 0x00, 0xF2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEB, ++ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDC, ++ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEF, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79, 0x0A, ++ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3D, 0x0C, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x0E, ++ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0xA8, 0x0E, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5, 0x0E, ++ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x0F, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8F, 0x0F, ++ 0x80, 0x00, 0x00, 0x00, 0x54, 0x90, 0xE5, 0x95, 0xC0, 0x03, 0xC4, 0x0F, 0xC0, 0x04, 0x74, 0xE0, ++ 0xC0, 0x82, 0xC0, 0xE0, 0x00, 0x04, 0x02, 0x83, 0x0F, 0x54, 0x90, 0xE5, 0xE0, 0xC0, 0x03, 0xC4, ++ 0xE0, 0xC0, 0x04, 0x74, 0x83, 0xC0, 0x82, 0xC0, 0xE5, 0x08, 0x04, 0x02, 0xC4, 0x0F, 0x54, 0x90, ++ 0x74, 0xE0, 0xC0, 0x03, 0xC0, 0xE0, 0xC0, 0x04, 0x02, 0x83, 0xC0, 0x82, 0x90, 0xE5, 0x10, 0x04, ++ 0x03, 0xC4, 0x0F, 0x54, 0x04, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, 0xC0, 0x04, 0x02, 0x83, 0xC0, ++ 0x54, 0x90, 0xE5, 0x18, 0xC0, 0x03, 0xC4, 0x0F, 0xC0, 0x04, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, ++ 0x20, 0x04, 0x02, 0x83, 0x0F, 0x54, 0x90, 0xE5, 0xE0, 0xC0, 0x03, 0xC4, 0xE0, 0xC0, 0x04, 0x74, ++ 0x83, 0xC0, 0x82, 0xC0, 0xE5, 0x28, 0x04, 0x02, 0xC4, 0x0F, 0x54, 0x90, 0x74, 0xE0, 0xC0, 0x03, ++ 0xC0, 0xE0, 0xC0, 0x04, 0x02, 0x83, 0xC0, 0x82, 0x90, 0xE5, 0x30, 0x04, 0x03, 0xC4, 0x0F, 0x54, ++ 0x04, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, 0xC0, 0x04, 0x02, 0x83, 0xC0, 0x54, 0x90, 0xE5, 0x38, ++ 0xC0, 0x03, 0xC4, 0x0F, 0xC0, 0x04, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, 0x40, 0x04, 0x02, 0x83, ++ 0x0F, 0x54, 0x90, 0xE5, 0xE0, 0xC0, 0x03, 0xC4, 0xE0, 0xC0, 0x04, 0x74, 0x83, 0xC0, 0x82, 0xC0, ++ 0xE5, 0x48, 0x04, 0x02, 0xC4, 0x0F, 0x54, 0x90, 0x74, 0xE0, 0xC0, 0x03, 0xC0, 0xE0, 0xC0, 0x04, ++ 0x02, 0x83, 0xC0, 0x82, 0x90, 0xE5, 0x50, 0x04, 0x03, 0xC4, 0x0F, 0x54, 0x04, 0x74, 0xE0, 0xC0, ++ 0x82, 0xC0, 0xE0, 0xC0, 0x04, 0x02, 0x83, 0xC0, 0x54, 0x90, 0xE5, 0x58, 0xC0, 0x03, 0xC4, 0x0F, ++ 0xC0, 0x04, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, 0x60, 0x04, 0x02, 0x83, 0x0F, 0x54, 0x90, 0xE5, ++ 0xE0, 0xC0, 0x03, 0xC4, 0xE0, 0xC0, 0x04, 0x74, 0x83, 0xC0, 0x82, 0xC0, 0xE5, 0x68, 0x04, 0x02, ++ 0xC4, 0x0F, 0x54, 0x90, 0x74, 0xE0, 0xC0, 0x03, 0xC0, 0xE0, 0xC0, 0x04, 0x02, 0x83, 0xC0, 0x82, ++ 0x90, 0xE5, 0x70, 0x04, 0x03, 0xC4, 0x0F, 0x54, 0x04, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, 0xC0, ++ 0x04, 0x02, 0x83, 0xC0, 0x03, 0xC4, 0xEF, 0x78, 0x73, 0x00, 0x04, 0x90, 0x01, 0x7B, 0x22, 0x90, ++ 0x00, 0x20, 0x90, 0x88, 0x23, 0x90, 0x9B, 0x01, 0x90, 0x9B, 0x01, 0xC2, 0xAE, 0x01, 0x00, 0x20, ++ 0x01, 0x1C, 0x26, 0x90, 0x00, 0x20, 0x90, 0xAE, 0x26, 0x90, 0xC1, 0x01, 0x90, 0xC1, 0x01, 0x1B, ++ 0xD4, 0x01, 0x00, 0x20, 0x01, 0xBE, 0x21, 0x90, 0x00, 0x20, 0x90, 0xD4, 0x21, 0x90, 0xE7, 0x01, ++ 0x90, 0xE7, 0x01, 0xBE, 0xFA, 0x01, 0x00, 0x20, 0x01, 0xFC, 0x27, 0x90, 0x00, 0x20, 0x90, 0xFA, ++ 0x27, 0x90, 0x0D, 0x21, 0x90, 0x0D, 0x21, 0xFC, 0x20, 0x21, 0x00, 0x20, 0x21, 0x73, 0x2C, 0x90, ++ 0x00, 0x20, 0x90, 0x20, 0x2E, 0x90, 0x33, 0x21, 0x90, 0x33, 0x21, 0x1B, 0x46, 0x21, 0x00, 0x20, ++ 0x21, 0x74, 0x2C, 0x90, 0x00, 0x20, 0x90, 0x46, 0x2E, 0x90, 0x59, 0x21, 0x90, 0x59, 0x21, 0x1B, ++ 0x6C, 0x21, 0x00, 0x20, 0x21, 0xCE, 0x2C, 0x90, 0x00, 0x20, 0x90, 0x6C, 0x2C, 0x90, 0x7F, 0x21, ++ 0x90, 0x7F, 0x21, 0xCE, 0x92, 0x21, 0x00, 0x20, 0x21, 0xD0, 0x26, 0x90, 0x2C, 0x20, 0x90, 0x92, ++ 0x21, 0x90, 0x88, 0x01, 0x90, 0x88, 0x01, 0x71, 0x9B, 0x01, 0xB9, 0x23, 0x01, 0xB3, 0x20, 0x90, ++ 0x9F, 0x20, 0x90, 0x9B, 0x20, 0x90, 0xAE, 0x01, 0x90, 0xC1, 0x01, 0xA9, 0xC1, 0x01, 0x8B, 0x22, ++ 0x01, 0x54, 0x20, 0x90, 0x54, 0x20, 0x90, 0xD4, 0x20, 0x90, 0xE7, 0x01, 0x90, 0xFA, 0x01, 0x75, ++ 0x0D, 0x21, 0x75, 0x20, 0x21, 0xE7, 0x20, 0x90, 0x50, 0x21, 0x90, 0x20, 0x20, 0x90, 0x33, 0x21, ++ 0x90, 0x46, 0x21, 0xE7, 0x59, 0x21, 0x50, 0x21, 0x21, 0xE9, 0x20, 0x90, 0xE9, 0x20, 0x90, 0x6C, ++ 0x20, 0x90, 0x7F, 0x21, 0x00, 0x92, 0x21, 0x90, 0xA4, 0xF0, 0x8D, 0xEF, 0x8C, 0xCF, 0xF0, 0xA8, ++ 0xCE, 0x28, 0xA4, 0xF0, 0x2E, 0xA4, 0xF0, 0x8D, 0x00, 0xBC, 0x22, 0xFE, 0x29, 0x00, 0xBE, 0x0B, ++ 0x84, 0xF0, 0x8D, 0xEF, 0x22, 0xF0, 0xAD, 0xFF, 0x75, 0xF8, 0xCC, 0xE4, 0x2F, 0xEF, 0x08, 0xF0, ++ 0xFE, 0x33, 0xEE, 0xFF, 0xEE, 0xFC, 0x33, 0xEC, 0x40, 0x98, 0xEC, 0x9D, 0x9D, 0xEE, 0xFC, 0x05, ++ 0xF0, 0xD5, 0x0F, 0xFE, 0xFD, 0xCE, 0xE4, 0xE9, 0xF5, 0xF8, 0xED, 0x22, 0x20, 0x84, 0xEE, 0xF0, ++ 0xAD, 0xFE, 0x1C, 0xD2, 0x08, 0xF0, 0x75, 0xF0, 0xED, 0xFF, 0x2F, 0xEF, 0x07, 0x40, 0xFD, 0x33, ++ 0xD5, 0x06, 0x50, 0x98, 0xC3, 0x22, 0xF2, 0xF0, 0xD5, 0x0F, 0xFD, 0x98, 0xEB, 0x22, 0xEA, 0xF0, ++ 0xEA, 0xF0, 0xF5, 0x9F, 0xE9, 0xF0, 0x42, 0x9E, 0xEC, 0xF0, 0x42, 0x9D, 0x64, 0xC8, 0x80, 0x64, ++ 0xF0, 0x45, 0x98, 0x80, 0xD0, 0x83, 0xD0, 0x22, 0x93, 0xE4, 0xF8, 0x82, 0x01, 0x74, 0x12, 0x70, ++ 0xA3, 0x0D, 0x70, 0x93, 0x74, 0xF8, 0x93, 0xA3, 0x82, 0xF5, 0x93, 0x01, 0x73, 0xE4, 0x83, 0x88, ++ 0x68, 0x93, 0x02, 0x74, 0xA3, 0xA3, 0xEF, 0x60, 0x8A, 0xDF, 0x80, 0xA3, 0xE4, 0x82, 0x89, 0x83, ++ 0xC8, 0x81, 0x75, 0x73, 0xE4, 0x47, 0x03, 0x02, 0x11, 0x12, 0x03, 0x60, 0xFF, 0xB0, 0x75, 0x6E, ++ 0x42, 0x51, 0x84, 0x71, 0xE0, 0x34, 0x07, 0x90, 0x04, 0x44, 0xF0, 0x54, 0x44, 0x07, 0x90, 0xF0, ++ 0x13, 0xC4, 0xFF, 0xE0, 0xE0, 0x20, 0x07, 0x54, 0xF1, 0x80, 0x00, 0x03, 0x74, 0x32, 0x07, 0x90, ++ 0x07, 0x90, 0xF0, 0xFF, 0xC2, 0x71, 0xF0, 0x33, 0xE0, 0x07, 0x07, 0x90, 0x43, 0xF0, 0x10, 0x44, ++ 0xFB, 0x80, 0x01, 0x87, 0x75, 0x07, 0x1B, 0x75, 0x11, 0x7E, 0x12, 0x1C, 0x98, 0x71, 0x6E, 0x7F, ++ 0x7B, 0x7F, 0x22, 0x7E, 0x3D, 0x41, 0x98, 0x71, 0xFF, 0x10, 0x24, 0xEF, 0xFE, 0xE0, 0x34, 0xEE, ++ 0x24, 0xF0, 0x54, 0xEF, 0x34, 0xEE, 0xFF, 0xFF, 0x1C, 0xE5, 0xFE, 0xFF, 0xF5, 0x02, 0x24, 0xFD, ++ 0xFC, 0x1B, 0xE5, 0x1C, 0x1B, 0xF5, 0x00, 0x34, 0x83, 0x8C, 0x82, 0x8D, 0xEF, 0xA3, 0xF0, 0xEE, ++ 0xF5, 0xE4, 0x22, 0xF0, 0xD2, 0xE8, 0xF5, 0xA8, 0xD2, 0xEA, 0xD2, 0xAC, 0x75, 0xE8, 0xD2, 0xE9, ++ 0xF8, 0x75, 0xF0, 0xF9, 0x75, 0xB9, 0xF5, 0xF1, 0xAF, 0xD2, 0x10, 0xB8, 0xF5, 0x20, 0x10, 0x75, ++ 0x01, 0x90, 0x22, 0x11, 0xE4, 0xF0, 0xEF, 0xB6, 0xF0, 0xB3, 0x01, 0x90, 0xB7, 0x01, 0x90, 0x22, ++ 0x90, 0xE4, 0xF0, 0xEF, 0x22, 0xF0, 0xB4, 0x01, 0xB5, 0x01, 0x90, 0xE4, 0x00, 0x00, 0x22, 0xF0, ++ 0x22, 0xF0, 0x90, 0x53, 0x00, 0x00, 0x00, 0x00, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF1, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF2, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF3, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF4, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF5, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF6, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF7, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF8, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF9, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xFA, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xFB, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xFC, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xFD, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xFE, 0x90, 0x22, 0x0F, 0x90, 0x43, 0xF0, 0xC0, 0xE0, 0xC0, ++ 0x82, 0xC0, 0x83, 0xC0, 0xD0, 0x75, 0xD0, 0xC0, 0x01, 0xA2, 0x63, 0x00, 0x82, 0xC0, 0x83, 0xC0, ++ 0xC0, 0x01, 0xA2, 0x63, 0xC0, 0x01, 0xC0, 0x00, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x05, 0xC0, 0x04, ++ 0x30, 0x07, 0xC0, 0x06, 0x99, 0xC2, 0x24, 0x99, 0x1A, 0xB5, 0x19, 0xE5, 0x18, 0x17, 0x30, 0x03, ++ 0x19, 0x05, 0x19, 0xAF, 0x82, 0x74, 0x00, 0x7E, 0xEE, 0x82, 0xF5, 0x2F, 0x83, 0xF5, 0x00, 0x34, ++ 0x0D, 0x11, 0xFF, 0xE0, 0x02, 0x80, 0x17, 0xC2, 0x07, 0xD0, 0x18, 0xC2, 0x05, 0xD0, 0x06, 0xD0, ++ 0x03, 0xD0, 0x04, 0xD0, 0x01, 0xD0, 0x02, 0xD0, 0xA2, 0x63, 0x00, 0xD0, 0xD0, 0x82, 0xD0, 0x01, ++ 0x01, 0xA2, 0x63, 0x83, 0x82, 0xD0, 0xD0, 0xD0, 0xF0, 0xD0, 0x83, 0xD0, 0xC0, 0x32, 0xE0, 0xD0, ++ 0xC0, 0xF0, 0xC0, 0xE0, 0xC0, 0x82, 0xC0, 0x83, 0x00, 0xD0, 0x75, 0xD0, 0xC0, 0x01, 0xA2, 0x63, ++ 0x63, 0x82, 0xC0, 0x83, 0x00, 0xC0, 0x01, 0xA2, 0x02, 0xC0, 0x01, 0xC0, 0x04, 0xC0, 0x03, 0xC0, ++ 0x06, 0xC0, 0x05, 0xC0, 0x07, 0x90, 0x07, 0xC0, 0x7A, 0xF5, 0xE0, 0x02, 0x54, 0xEF, 0x7A, 0xAF, ++ 0x13, 0x13, 0xC4, 0x40, 0x7B, 0xF5, 0x03, 0x54, 0xA4, 0x40, 0xF0, 0x75, 0x82, 0xF5, 0x00, 0x24, ++ 0xAF, 0x06, 0x34, 0xE4, 0x8F, 0x12, 0xF5, 0x82, 0x25, 0x20, 0x74, 0x13, 0x7B, 0xE5, 0xFF, 0x7B, ++ 0x01, 0x90, 0x05, 0x70, 0x90, 0x03, 0x80, 0xB8, 0xFC, 0xE0, 0xBA, 0x01, 0x17, 0x8C, 0xE0, 0xA3, ++ 0x7A, 0xAE, 0x18, 0xF5, 0x13, 0x13, 0xC4, 0xEE, 0x30, 0x01, 0x54, 0x13, 0xE5, 0xE1, 0x02, 0xE0, ++ 0x54, 0xEE, 0x7A, 0xAE, 0x05, 0x15, 0x71, 0x1F, 0x54, 0x06, 0x00, 0x86, 0x07, 0x78, 0x06, 0x04, ++ 0x06, 0x09, 0x81, 0x06, 0xC6, 0x06, 0x0D, 0xA8, 0x14, 0x04, 0x07, 0x0E, 0x07, 0x15, 0x66, 0x07, ++ 0x00, 0x00, 0x17, 0x26, 0x13, 0x85, 0x80, 0x08, 0x83, 0x12, 0x85, 0x82, 0x13, 0xC4, 0xFE, 0xE0, ++ 0x01, 0x54, 0x13, 0x13, 0xC2, 0x26, 0xE0, 0x30, 0x24, 0x82, 0xE5, 0xE8, 0xE4, 0x82, 0xF5, 0x80, ++ 0x83, 0xF5, 0x83, 0x35, 0xF0, 0x80, 0x44, 0xE0, 0x85, 0x82, 0x13, 0x85, 0x44, 0xEE, 0x83, 0x12, ++ 0x07, 0xA8, 0xF0, 0x80, 0xF6, 0x01, 0x44, 0xE6, 0x08, 0x02, 0xE8, 0xD2, 0x82, 0x13, 0x85, 0x80, ++ 0xE0, 0x83, 0x12, 0x85, 0x0F, 0x54, 0xC4, 0xFE, 0xEE, 0x2A, 0xE0, 0x30, 0xE0, 0x25, 0x02, 0x54, ++ 0xE6, 0x07, 0xA8, 0xFE, 0xF6, 0x4E, 0xFB, 0x54, 0x7B, 0x25, 0x7F, 0x74, 0x00, 0x7E, 0xE6, 0xF8, ++ 0x01, 0x7E, 0x02, 0x70, 0xC4, 0x01, 0x54, 0xEE, 0xFE, 0xE0, 0x54, 0x33, 0x54, 0xE6, 0x07, 0xA8, ++ 0x80, 0xF6, 0x4E, 0xDF, 0x82, 0x13, 0x85, 0x1E, 0xE0, 0x83, 0x12, 0x85, 0xA3, 0xF0, 0xFD, 0x54, ++ 0x54, 0xE0, 0xA3, 0xA3, 0x7F, 0x74, 0xF0, 0xDF, 0x76, 0xF8, 0x7B, 0x25, 0xE6, 0x07, 0xA8, 0x00, ++ 0x85, 0xF6, 0x20, 0x44, 0x12, 0x85, 0x82, 0x13, 0x13, 0xFE, 0xE0, 0x83, 0xFD, 0x01, 0x54, 0x13, ++ 0x13, 0x13, 0xC4, 0xEE, 0xFE, 0x4D, 0x01, 0x54, 0x13, 0xC4, 0xE0, 0xA3, 0x01, 0x54, 0x13, 0x13, ++ 0xC4, 0x01, 0x54, 0x4E, 0xA8, 0xFE, 0xF0, 0x54, 0xEF, 0x54, 0xE6, 0x07, 0x13, 0x85, 0xF6, 0x4E, ++ 0x83, 0x12, 0x85, 0x82, 0x13, 0x08, 0x54, 0xE0, 0xFE, 0x3F, 0x54, 0x13, 0x4E, 0xFD, 0x54, 0xE6, ++ 0x80, 0x08, 0x02, 0xF6, 0x7B, 0x25, 0x7F, 0x74, 0x03, 0x60, 0xE6, 0xF8, 0x85, 0x80, 0x08, 0x02, ++ 0x12, 0x85, 0x82, 0x13, 0x54, 0xC4, 0xE0, 0x83, 0x03, 0xE0, 0x20, 0x0F, 0xA8, 0x80, 0x08, 0x02, ++ 0x04, 0x44, 0xE6, 0x07, 0x80, 0x08, 0x02, 0xF6, 0x44, 0xE6, 0x07, 0xA8, 0x08, 0x02, 0xF6, 0x08, ++ 0x24, 0x13, 0xE5, 0x80, 0xE4, 0x82, 0xF5, 0x12, 0x83, 0xF5, 0x12, 0x35, 0x54, 0x13, 0xC4, 0xE0, ++ 0x60, 0x00, 0x7E, 0x07, 0xEE, 0x01, 0x7E, 0x02, 0x54, 0xC4, 0x01, 0x54, 0x07, 0xA8, 0xFE, 0xF0, ++ 0x4E, 0xEF, 0x54, 0xE6, 0x80, 0x08, 0x02, 0xF6, 0xEF, 0xB8, 0x08, 0x12, 0x08, 0x02, 0x03, 0x60, ++ 0x24, 0x13, 0xE5, 0x51, 0xE4, 0x82, 0xF5, 0x1C, 0x83, 0xF5, 0x12, 0x35, 0xA3, 0xF0, 0x17, 0xE5, ++ 0x02, 0xF0, 0x18, 0xE5, 0x08, 0x12, 0x80, 0x08, 0x16, 0x70, 0xEF, 0xB8, 0x1C, 0x24, 0x13, 0xE5, ++ 0x35, 0xE4, 0x82, 0xF5, 0xE0, 0x83, 0xF5, 0x12, 0x8E, 0xE0, 0xA3, 0xFE, 0x02, 0x18, 0xF5, 0x17, ++ 0x7B, 0xE5, 0x80, 0x08, 0x13, 0x92, 0xFF, 0x24, 0x12, 0xF8, 0x09, 0x12, 0x64, 0xEF, 0xB8, 0x08, ++ 0x12, 0x06, 0x60, 0x02, 0x03, 0xBF, 0xB8, 0x08, 0xE5, 0x18, 0x05, 0x08, 0x05, 0x02, 0x70, 0x18, ++ 0x51, 0x08, 0x02, 0x17, 0x0C, 0x70, 0x7B, 0xE5, 0xE0, 0x28, 0x06, 0x90, 0x90, 0xFF, 0x04, 0x54, ++ 0x0A, 0x80, 0x68, 0x06, 0xE0, 0x68, 0x06, 0x90, 0x90, 0xFF, 0x04, 0x54, 0x54, 0xE0, 0x28, 0x06, ++ 0x02, 0xF0, 0x4F, 0xFB, 0x7B, 0xE5, 0x80, 0x08, 0x06, 0x90, 0x1B, 0x70, 0x03, 0x54, 0xE0, 0x2F, ++ 0x6F, 0x06, 0x90, 0xFF, 0x4F, 0xFC, 0x54, 0xE0, 0x2E, 0x06, 0x90, 0xF0, 0xFF, 0x08, 0x54, 0xE0, ++ 0x80, 0x6E, 0x06, 0x90, 0x6F, 0x06, 0x90, 0x19, 0xFF, 0x03, 0x54, 0xE0, 0xE0, 0x2F, 0x06, 0x90, ++ 0xF0, 0x4F, 0xFC, 0x54, 0xE0, 0x6E, 0x06, 0x90, 0x90, 0xFF, 0x08, 0x54, 0x54, 0xE0, 0x2E, 0x06, ++ 0x02, 0xF0, 0x4F, 0xF7, 0x07, 0x90, 0x80, 0x08, 0x07, 0x54, 0xE0, 0x93, 0x2A, 0x06, 0x90, 0xFF, ++ 0x6F, 0x0F, 0x54, 0xE0, 0x7B, 0xE5, 0x09, 0x60, 0x07, 0x90, 0x05, 0x70, 0x90, 0x18, 0x80, 0x92, ++ 0x54, 0xE0, 0xDD, 0x07, 0x06, 0x90, 0xFF, 0x07, 0x0F, 0x54, 0xE0, 0x6A, 0xE5, 0x24, 0x60, 0x6F, ++ 0x1F, 0x01, 0xB4, 0x7B, 0xE0, 0xDC, 0x07, 0x90, 0x24, 0x13, 0xE5, 0xFF, 0xE4, 0x82, 0xF5, 0x2B, ++ 0x83, 0xF5, 0x12, 0x35, 0x13, 0xE5, 0xF0, 0xEF, 0x82, 0xF5, 0x2B, 0x24, 0xF5, 0x12, 0x35, 0xE4, ++ 0xE5, 0xF0, 0xE4, 0x83, 0xE5, 0x14, 0x70, 0x7B, 0xF5, 0x2A, 0x24, 0x13, 0x12, 0x35, 0xE4, 0x82, ++ 0x54, 0xE0, 0x83, 0xF5, 0x07, 0x90, 0xFF, 0x07, 0xE5, 0x12, 0x80, 0x93, 0xF5, 0x2A, 0x24, 0x13, ++ 0x12, 0x35, 0xE4, 0x82, 0x54, 0xE0, 0x83, 0xF5, 0x07, 0x90, 0xFF, 0x07, 0xF8, 0x54, 0xE0, 0xDD, ++ 0x08, 0x02, 0xF0, 0x4F, 0xEF, 0x7A, 0xAF, 0x80, 0xFA, 0x24, 0x1F, 0x54, 0xF8, 0x24, 0x2A, 0x60, ++ 0xF9, 0x24, 0x4D, 0x60, 0xFB, 0x24, 0x65, 0x60, 0x19, 0x24, 0x70, 0x60, 0x80, 0x01, 0x02, 0x60, ++ 0x85, 0x82, 0x13, 0x85, 0xA3, 0xA3, 0x83, 0x12, 0xEF, 0x54, 0xE0, 0xA3, 0x82, 0x13, 0x85, 0xF0, ++ 0xA3, 0x83, 0x12, 0x85, 0x21, 0x80, 0xA3, 0xA3, 0x0D, 0x24, 0x13, 0xE5, 0x35, 0xE4, 0x82, 0xF5, ++ 0xE0, 0x83, 0xF5, 0x12, 0x90, 0xF0, 0xEF, 0x54, 0x20, 0xE0, 0xFF, 0x01, 0x13, 0xE5, 0x52, 0xE0, ++ 0x82, 0xF5, 0x0D, 0x24, 0xF5, 0x12, 0x35, 0xE4, 0xFD, 0x54, 0xE0, 0x83, 0x11, 0x41, 0x80, 0xF0, ++ 0x08, 0x02, 0xBF, 0xB8, 0x18, 0xE5, 0x18, 0x05, 0x17, 0x05, 0x02, 0x70, 0x60, 0xEF, 0xB8, 0x11, ++ 0x24, 0x7B, 0xE5, 0x2F, 0x11, 0x13, 0x92, 0xFF, 0xE5, 0x25, 0x80, 0xCB, 0xF5, 0x2B, 0x24, 0x13, ++ 0x12, 0x35, 0xE4, 0x82, 0xF0, 0xE4, 0x83, 0xF5, 0x13, 0xE5, 0x16, 0x80, 0x82, 0xF5, 0x34, 0x24, ++ 0xF5, 0x12, 0x35, 0xE4, 0xA3, 0xF0, 0xE4, 0x83, 0x07, 0x07, 0x90, 0xF0, 0xF0, 0xEF, 0x54, 0xE0, ++ 0x05, 0x70, 0x7B, 0xE5, 0x80, 0xB8, 0x01, 0x90, 0xBA, 0x01, 0x90, 0x03, 0xA3, 0xF0, 0x17, 0xE5, ++ 0xD0, 0xF0, 0x18, 0xE5, 0xD0, 0x06, 0xD0, 0x07, 0xD0, 0x04, 0xD0, 0x05, 0xD0, 0x02, 0xD0, 0x03, ++ 0x63, 0x00, 0xD0, 0x01, 0x82, 0xD0, 0x01, 0xA2, 0xA2, 0x63, 0x83, 0xD0, 0xD0, 0xD0, 0xD0, 0x01, ++ 0xD0, 0x83, 0xD0, 0x82, 0x32, 0xE0, 0xD0, 0xF0, 0x1A, 0x24, 0x13, 0xE5, 0x35, 0xE4, 0x82, 0xF5, ++ 0xE0, 0x83, 0xF5, 0x12, 0x54, 0x13, 0x13, 0xC4, 0xE5, 0x22, 0xFF, 0x03, 0xF5, 0x1C, 0x24, 0x13, ++ 0x12, 0x35, 0xE4, 0x82, 0xF0, 0xE4, 0x83, 0xF5, 0xAD, 0x31, 0xF0, 0xA3, 0x1B, 0x24, 0x13, 0xE5, ++ 0x35, 0xE4, 0x82, 0xF5, 0xE0, 0x83, 0xF5, 0x12, 0xF9, 0x24, 0x1F, 0x54, 0xE9, 0x24, 0x75, 0x60, ++ 0x88, 0x21, 0x02, 0x70, 0x21, 0x02, 0x70, 0x14, 0x60, 0x1C, 0x24, 0x97, 0xAF, 0xAC, 0x21, 0x02, ++ 0x60, 0x14, 0xEF, 0x18, 0x60, 0xED, 0x24, 0x0E, 0x60, 0xFE, 0x24, 0x0A, 0x60, 0x16, 0x24, 0x06, ++ 0x85, 0xAC, 0x21, 0x02, 0x15, 0x85, 0x82, 0x16, 0xA3, 0xFC, 0xE0, 0x83, 0x13, 0xE5, 0xFD, 0xE0, ++ 0x82, 0xF5, 0x1C, 0x24, 0xF5, 0x12, 0x35, 0xE4, 0xA3, 0xF0, 0xEC, 0x83, 0x64, 0xEF, 0xF0, 0xED, ++ 0x85, 0x79, 0x70, 0x01, 0x15, 0x85, 0x82, 0x16, 0xC0, 0x83, 0xC0, 0x83, 0xA3, 0xFE, 0xE0, 0x82, ++ 0x13, 0xE5, 0xFF, 0xE0, 0x82, 0xF5, 0x1C, 0x24, 0xF5, 0x12, 0x35, 0xE4, 0x0C, 0x54, 0xE0, 0x83, ++ 0xFD, 0xF4, 0xE4, 0xFC, 0xEE, 0xFC, 0xF4, 0xEC, 0x5D, 0xEF, 0xFE, 0x5C, 0xD0, 0x82, 0xD0, 0xFF, ++ 0xE5, 0x1F, 0x80, 0x83, 0x60, 0xC3, 0x24, 0x18, 0x40, 0x70, 0x04, 0x03, 0x85, 0x82, 0x16, 0x85, ++ 0xFE, 0xE0, 0x83, 0x15, 0xE5, 0xFF, 0xE0, 0xA3, 0xF5, 0x1C, 0x24, 0x13, 0x12, 0x35, 0xE4, 0x82, ++ 0xF0, 0xEE, 0x83, 0xF5, 0x22, 0xF0, 0xEF, 0xA3, 0xE0, 0x2C, 0x06, 0x90, 0x90, 0xF0, 0x40, 0x44, ++ 0x44, 0xE0, 0x6C, 0x06, 0x85, 0x22, 0xF0, 0x40, 0x17, 0x85, 0x82, 0x18, 0xE5, 0xFF, 0xE0, 0x83, ++ 0xF5, 0x1D, 0x24, 0x13, 0x12, 0x35, 0xE4, 0x82, 0xF0, 0xEF, 0x83, 0xF5, 0x92, 0x13, 0xA2, 0x22, ++ 0xE4, 0x14, 0xA2, 0x14, 0x54, 0xF8, 0xC4, 0x33, 0xFF, 0x68, 0xC8, 0x0F, 0xF0, 0x54, 0xC4, 0xE4, ++ 0x82, 0x74, 0xFE, 0x48, 0x01, 0x74, 0xF9, 0x2F, 0xF5, 0x01, 0xAF, 0x3E, 0xAF, 0x16, 0x8F, 0x15, ++ 0x13, 0xC3, 0xEF, 0x18, 0xFF, 0x01, 0x54, 0x4F, 0x05, 0xAE, 0x18, 0xAD, 0x13, 0x13, 0x13, 0xEE, ++ 0x90, 0x4F, 0x06, 0x54, 0xE0, 0xF0, 0xBC, 0x01, 0xA4, 0x02, 0xF0, 0x75, 0x16, 0x25, 0xF0, 0xAE, ++ 0x35, 0xEE, 0x16, 0xF5, 0x22, 0x15, 0xF5, 0x15, 0x13, 0xE5, 0xAD, 0x31, 0x82, 0xF5, 0x1B, 0x24, ++ 0xF5, 0x12, 0x35, 0xE4, 0x1F, 0x54, 0xE0, 0x83, 0x28, 0x60, 0xF9, 0x24, 0x46, 0x60, 0xE9, 0x24, ++ 0x24, 0x52, 0x60, 0x14, 0xE5, 0x61, 0x70, 0x1C, 0xE5, 0x5D, 0x70, 0x18, 0xF5, 0x1C, 0x24, 0x13, ++ 0x12, 0x35, 0xE4, 0x82, 0x54, 0xE0, 0x83, 0xF5, 0x82, 0x16, 0x85, 0x04, 0xF0, 0x83, 0x15, 0x85, ++ 0x22, 0xF0, 0xE4, 0xA3, 0x3C, 0x64, 0x18, 0xE5, 0x13, 0xE5, 0x3E, 0x70, 0x82, 0xF5, 0x1C, 0x24, ++ 0xF5, 0x12, 0x35, 0xE4, 0x54, 0xE0, 0xA3, 0x83, 0x16, 0x85, 0xFF, 0x02, 0x83, 0x15, 0x85, 0x82, ++ 0xEF, 0xA3, 0xF0, 0xE4, 0x06, 0x90, 0x22, 0xF0, 0x40, 0x44, 0xE0, 0x2C, 0x6C, 0x06, 0x90, 0xF0, ++ 0xF0, 0x40, 0x44, 0xE0, 0x24, 0x13, 0xE5, 0x22, 0xE4, 0x82, 0xF5, 0x1D, 0x83, 0xF5, 0x12, 0x35, ++ 0x82, 0x18, 0x85, 0xE0, 0xF0, 0x83, 0x17, 0x85, 0xC0, 0xE0, 0xC0, 0x22, 0xC0, 0x83, 0xC0, 0xF0, ++ 0x75, 0xD0, 0xC0, 0x82, 0xA2, 0x63, 0x00, 0xD0, 0xC0, 0x83, 0xC0, 0x01, 0x01, 0xA2, 0x63, 0x82, ++ 0x01, 0xC0, 0x00, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x05, 0xC0, 0x04, 0xC0, 0x07, 0xC0, 0x06, 0xC0, ++ 0x74, 0x66, 0x07, 0x90, 0x01, 0x90, 0xF0, 0x04, 0xF0, 0x04, 0xE0, 0xB3, 0xE0, 0xB6, 0x01, 0x90, ++ 0xB3, 0x01, 0x90, 0xFF, 0x40, 0x9F, 0xD3, 0xE0, 0x90, 0xE9, 0xC2, 0x42, 0xC4, 0xE0, 0x44, 0x07, ++ 0x30, 0x07, 0x54, 0x13, 0x29, 0xE5, 0x35, 0xE0, 0x04, 0x70, 0x27, 0x65, 0x26, 0x65, 0x28, 0xE5, ++ 0x02, 0x60, 0x00, 0x7F, 0x2E, 0x8F, 0x01, 0x7F, 0x06, 0x60, 0x2E, 0xE5, 0x85, 0x26, 0x28, 0x85, ++ 0x07, 0x90, 0x27, 0x29, 0x0F, 0x54, 0xE0, 0x43, 0x11, 0x85, 0x90, 0xF5, 0x83, 0x10, 0x85, 0x82, ++ 0x14, 0xF5, 0x93, 0xE4, 0x25, 0xA9, 0x24, 0xAA, 0x90, 0x3B, 0x03, 0x12, 0x04, 0xE0, 0xB4, 0x01, ++ 0xB7, 0x01, 0x90, 0xF0, 0x01, 0x90, 0xFF, 0xE0, 0x9F, 0xD3, 0xE0, 0xB4, 0xE9, 0xC2, 0x43, 0x40, ++ 0xE0, 0x43, 0x07, 0x90, 0x54, 0x13, 0xC4, 0xFF, 0x35, 0xE0, 0x30, 0x07, 0x33, 0x65, 0x35, 0xE5, ++ 0x34, 0xE5, 0x04, 0x70, 0x00, 0x7F, 0x32, 0x65, 0x01, 0x7F, 0x02, 0x60, 0x3A, 0xE5, 0x3A, 0x8F, ++ 0x34, 0x85, 0x06, 0x60, 0x33, 0x35, 0x85, 0x32, 0xE0, 0x44, 0x07, 0x90, 0x90, 0xF5, 0x0F, 0x54, ++ 0x85, 0x82, 0x11, 0x85, 0x93, 0xE4, 0x83, 0x10, 0x30, 0xAA, 0x14, 0xF5, 0x03, 0x12, 0x31, 0xA9, ++ 0x82, 0x07, 0x90, 0x3B, 0x0A, 0xE0, 0x30, 0xE0, 0x90, 0xF0, 0x01, 0x74, 0x44, 0xE0, 0x34, 0x06, ++ 0x07, 0x90, 0xF0, 0x80, 0xE0, 0x30, 0xE0, 0xCC, 0xF0, 0x01, 0x74, 0x0A, 0xE0, 0x74, 0x06, 0x90, ++ 0xC2, 0xF0, 0x80, 0x44, 0xD2, 0xA4, 0x71, 0x15, 0x91, 0xA4, 0x71, 0x15, 0xD0, 0xE9, 0xD2, 0x0D, ++ 0xD0, 0x06, 0xD0, 0x07, 0xD0, 0x04, 0xD0, 0x05, 0xD0, 0x02, 0xD0, 0x03, 0x63, 0x00, 0xD0, 0x01, ++ 0x82, 0xD0, 0x01, 0xA2, 0xA2, 0x63, 0x83, 0xD0, 0xD0, 0xD0, 0xD0, 0x01, 0xD0, 0x83, 0xD0, 0x82, ++ 0x32, 0xE0, 0xD0, 0xF0, 0xFE, 0xE4, 0x15, 0xA2, 0xC3, 0x06, 0x78, 0x33, 0xCE, 0x33, 0xCE, 0x33, ++ 0x24, 0xFF, 0xF9, 0xD8, 0x74, 0x82, 0xF5, 0x2B, 0x83, 0xF5, 0x3E, 0x06, 0x00, 0x7C, 0xFD, 0xE0, ++ 0x90, 0x0B, 0x15, 0x20, 0x2D, 0xE0, 0x92, 0x07, 0xFC, 0x33, 0xE4, 0xFD, 0x07, 0x90, 0x09, 0x80, ++ 0xFD, 0x2D, 0xE0, 0xDC, 0xAA, 0xFC, 0x3C, 0xE4, 0x04, 0x60, 0xEC, 0x04, 0xFF, 0x7D, 0x00, 0x7C, ++ 0xF5, 0x2F, 0x03, 0x74, 0x3E, 0x06, 0x74, 0x82, 0xFF, 0xE0, 0x83, 0xF5, 0x3F, 0x54, 0x13, 0x13, ++ 0xA2, 0x19, 0xE0, 0x30, 0x33, 0xFE, 0xE4, 0x15, 0x33, 0xC3, 0x06, 0x78, 0xD8, 0xCE, 0x33, 0xCE, ++ 0xF5, 0x2B, 0x24, 0xF9, 0x3E, 0x06, 0x74, 0x82, 0xF0, 0xED, 0x83, 0xF5, 0x34, 0x06, 0x90, 0x22, ++ 0xE0, 0xA3, 0xFE, 0xE0, 0x32, 0x06, 0x90, 0xFF, 0xA3, 0xFE, 0x5E, 0xE0, 0x70, 0x4E, 0x5F, 0xE0, ++ 0x74, 0x06, 0x90, 0x14, 0xE0, 0xA3, 0xFE, 0xE0, 0x72, 0x06, 0x90, 0xFF, 0xA3, 0xFE, 0x5E, 0xE0, ++ 0x60, 0x4E, 0x5F, 0xE0, 0x07, 0x07, 0x90, 0x07, 0xF0, 0x10, 0x44, 0xE0, 0xC0, 0xE0, 0xC0, 0x22, ++ 0xC0, 0x83, 0xC0, 0xF0, 0x75, 0xD0, 0xC0, 0x82, 0xA2, 0x63, 0x00, 0xD0, 0xC0, 0x83, 0xC0, 0x01, ++ 0x01, 0xA2, 0x63, 0x82, 0x01, 0xC0, 0x00, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x05, 0xC0, 0x04, 0xC0, ++ 0x07, 0xC0, 0x06, 0xC0, 0x74, 0x66, 0x07, 0x90, 0xEA, 0xC2, 0xF0, 0x08, 0xE0, 0xB5, 0x01, 0x90, ++ 0xC3, 0xE0, 0xF0, 0x04, 0x07, 0x40, 0x32, 0x94, 0x01, 0x90, 0xA6, 0x91, 0xD2, 0xF0, 0xE4, 0xB5, ++ 0xD0, 0x07, 0xD0, 0xEA, 0xD0, 0x05, 0xD0, 0x06, 0xD0, 0x03, 0xD0, 0x04, 0xD0, 0x01, 0xD0, 0x02, ++ 0x01, 0xA2, 0x63, 0x00, 0x83, 0xD0, 0x82, 0xD0, 0xD0, 0x01, 0xA2, 0x63, 0xD0, 0x82, 0xD0, 0xD0, ++ 0xD0, 0xF0, 0xD0, 0x83, 0x01, 0x90, 0x32, 0xE0, 0xF0, 0x01, 0x74, 0xBD, 0xF0, 0xE2, 0x74, 0xA3, ++ 0xE0, 0xE0, 0x01, 0x90, 0xFF, 0x0F, 0x54, 0xC4, 0x74, 0xFE, 0x03, 0x54, 0x08, 0x06, 0xA8, 0x64, ++ 0x13, 0xC3, 0x02, 0x80, 0x7C, 0xF5, 0xFC, 0xD8, 0x54, 0x13, 0x13, 0xEF, 0xFF, 0x03, 0x54, 0x3F, ++ 0x07, 0xA8, 0x64, 0x74, 0xC3, 0x02, 0x80, 0x08, 0xF9, 0xFC, 0xD8, 0x13, 0x06, 0xE6, 0xC8, 0x78, ++ 0x40, 0x7C, 0x95, 0xC3, 0x78, 0xF6, 0xE4, 0x02, 0xC3, 0x06, 0xE6, 0xC3, 0xE4, 0x02, 0x40, 0x99, ++ 0xFA, 0xFB, 0xE4, 0xF6, 0xE0, 0xBD, 0x01, 0x90, 0xF5, 0xE0, 0xA3, 0xFE, 0xE0, 0x83, 0x8E, 0x82, ++ 0xE0, 0xA3, 0x7D, 0xF5, 0x01, 0x90, 0x7E, 0xF5, 0x02, 0x24, 0xE0, 0xBE, 0xBD, 0x01, 0x90, 0xF0, ++ 0xF0, 0x00, 0x34, 0xE0, 0xF8, 0x2A, 0xC4, 0x74, 0x00, 0x94, 0xD3, 0xE6, 0x13, 0xE9, 0x1E, 0x40, ++ 0x2A, 0xC4, 0x74, 0xFF, 0xD3, 0x16, 0xE6, 0xF8, 0xA1, 0x02, 0x50, 0x9F, 0xA8, 0x01, 0x74, 0xCC, ++ 0x02, 0x80, 0x08, 0x02, 0xFC, 0xD8, 0x33, 0xC3, 0xCC, 0xA1, 0x03, 0x42, 0x25, 0x01, 0x54, 0xEA, ++ 0xF5, 0xAF, 0x24, 0xE0, 0x01, 0x34, 0xE4, 0x82, 0x13, 0xE0, 0x83, 0xF5, 0x1F, 0x54, 0x13, 0x13, ++ 0xEE, 0x7E, 0xAE, 0xFF, 0x60, 0x5F, 0x07, 0x54, 0x2A, 0xC4, 0x74, 0x08, 0x80, 0x01, 0xA6, 0xF8, ++ 0xC4, 0x7E, 0xE5, 0x6B, 0xEA, 0xFF, 0x0F, 0x54, 0xB1, 0x16, 0x92, 0x13, 0x1B, 0x60, 0xEF, 0xFE, ++ 0x13, 0xC3, 0x7C, 0xE5, 0xE6, 0xC8, 0x78, 0xFF, 0x50, 0x40, 0x9F, 0xD3, 0x02, 0xA8, 0x01, 0x74, ++ 0xC3, 0x02, 0x80, 0x08, 0x42, 0xFC, 0xD8, 0x33, 0xEA, 0x41, 0x80, 0x03, 0xAF, 0x16, 0x92, 0x13, ++ 0xEF, 0xFE, 0xB1, 0x7D, 0xC3, 0xE9, 0x1A, 0x60, 0xC3, 0x78, 0xFF, 0x13, 0x40, 0x9F, 0xD3, 0xE6, ++ 0xA8, 0x01, 0x74, 0x2B, 0x02, 0x80, 0x08, 0x02, 0xFC, 0xD8, 0x33, 0xC3, 0x1C, 0x80, 0x03, 0x42, ++ 0x54, 0xC4, 0x7D, 0xE5, 0x13, 0xEA, 0xFF, 0x0F, 0xFE, 0xB1, 0x16, 0x92, 0x74, 0x0D, 0x60, 0xEF, ++ 0x08, 0x02, 0xA8, 0x01, 0x33, 0xC3, 0x02, 0x80, 0x03, 0x42, 0xFC, 0xD8, 0x04, 0x64, 0xEA, 0x0A, ++ 0xF4, 0x81, 0x02, 0x60, 0xE0, 0xAF, 0x01, 0x90, 0x90, 0xF0, 0xC7, 0x54, 0x54, 0xE0, 0xB1, 0x01, ++ 0x06, 0x90, 0xF0, 0xC7, 0x0F, 0x54, 0xE0, 0x36, 0x63, 0x03, 0x52, 0xFA, 0xA3, 0xE0, 0xFF, 0x02, ++ 0x5A, 0x0F, 0x54, 0xE0, 0x44, 0xEB, 0x03, 0x42, 0x08, 0x07, 0x90, 0x80, 0x07, 0xAC, 0x22, 0xF0, ++ 0xEC, 0x0F, 0x04, 0x53, 0xA2, 0x29, 0xE3, 0x30, 0x25, 0x33, 0xE4, 0x16, 0x33, 0xE4, 0xFF, 0xE0, ++ 0x2F, 0xAE, 0x74, 0xFE, 0x01, 0x74, 0x82, 0xF5, 0xE0, 0x83, 0xF5, 0x3E, 0x07, 0x54, 0xEC, 0xFF, ++ 0xA8, 0x01, 0x74, 0xFE, 0x02, 0x80, 0x08, 0x06, 0xFC, 0xD8, 0x33, 0xC3, 0x1D, 0x80, 0xFD, 0x5F, ++ 0x33, 0xE4, 0x16, 0xA2, 0xE4, 0xFF, 0xE0, 0x25, 0xAF, 0x74, 0xFE, 0x33, 0x74, 0x82, 0xF5, 0x2F, ++ 0x83, 0xF5, 0x3E, 0x01, 0x54, 0xEC, 0xFF, 0xE0, 0x5E, 0xEF, 0xFE, 0x07, 0x22, 0x05, 0xAF, 0xFD, ++ 0x83, 0xC0, 0xE0, 0xC0, 0xD0, 0xC0, 0x82, 0xC0, 0x63, 0x00, 0xD0, 0x75, 0x83, 0xC0, 0x01, 0xA2, ++ 0xA2, 0x63, 0x82, 0xC0, 0x90, 0x07, 0xC0, 0x01, 0xC4, 0xE0, 0x66, 0x07, 0xE0, 0x30, 0x0F, 0x54, ++ 0x00, 0x06, 0x90, 0x22, 0xF0, 0x80, 0x44, 0xE0, 0xE0, 0x40, 0x06, 0x90, 0xC2, 0xF0, 0x80, 0x44, ++ 0x44, 0x20, 0xE5, 0xE8, 0xE5, 0x20, 0xF5, 0x01, 0xF5, 0x01, 0x44, 0x21, 0x66, 0x07, 0x90, 0x21, ++ 0xD0, 0xF0, 0x10, 0x74, 0x01, 0xA2, 0x63, 0x07, 0x83, 0xD0, 0x82, 0xD0, 0xD0, 0x01, 0xA2, 0x63, ++ 0xD0, 0x82, 0xD0, 0xD0, 0x32, 0xE0, 0xD0, 0x83, 0xF0, 0xC0, 0xE0, 0xC0, 0xA2, 0x75, 0xA2, 0xC0, ++ 0x75, 0xD0, 0xC0, 0x02, 0x90, 0x85, 0x08, 0xD0, 0x42, 0x07, 0x90, 0x45, 0x13, 0x13, 0x13, 0xE0, ++ 0xE0, 0x30, 0x1F, 0x54, 0x44, 0x07, 0x90, 0x05, 0x07, 0x90, 0x03, 0x80, 0x0F, 0x54, 0xE0, 0x43, ++ 0x90, 0x75, 0x46, 0xF5, 0xA9, 0x3C, 0xAA, 0x0A, 0x3B, 0x03, 0x12, 0x3D, 0x85, 0x90, 0x46, 0x85, ++ 0x10, 0x85, 0x82, 0x11, 0xF5, 0x93, 0xE4, 0x83, 0x90, 0x45, 0x85, 0x14, 0xA2, 0xD0, 0xD0, 0xD0, ++ 0xE0, 0xD0, 0xF0, 0xD0, 0xC0, 0xE0, 0xC0, 0x32, 0x75, 0xA2, 0xC0, 0xF0, 0xD0, 0xC0, 0x02, 0xA2, ++ 0x85, 0x08, 0xD0, 0x75, 0x07, 0x90, 0x52, 0x90, 0x13, 0x13, 0xE0, 0x42, 0x30, 0x1F, 0x54, 0x13, ++ 0x07, 0x90, 0x05, 0xE0, 0x90, 0x03, 0x80, 0x44, 0x54, 0xE0, 0x43, 0x07, 0x75, 0x53, 0xF5, 0x0F, ++ 0x49, 0xAA, 0x0C, 0x90, 0x03, 0x12, 0x4A, 0xA9, 0x90, 0x53, 0x85, 0x3B, 0x85, 0x82, 0x11, 0x85, ++ 0x93, 0xE4, 0x83, 0x10, 0x52, 0x85, 0x14, 0xF5, 0xD0, 0xD0, 0xD0, 0x90, 0xD0, 0xF0, 0xD0, 0xA2, ++ 0xE0, 0xC0, 0x32, 0xE0, 0xA2, 0xC0, 0xF0, 0xC0, 0xC0, 0x02, 0xA2, 0x75, 0x08, 0xD0, 0x75, 0xD0, ++ 0x90, 0x45, 0x90, 0x85, 0x13, 0xE0, 0x42, 0x07, 0x1F, 0x54, 0x13, 0x13, 0x90, 0x05, 0xE0, 0x30, ++ 0x03, 0x80, 0x44, 0x07, 0xE0, 0x43, 0x07, 0x90, 0x46, 0xF5, 0x0F, 0x54, 0xAA, 0x0A, 0x90, 0x75, ++ 0x12, 0x3F, 0xA9, 0x3E, 0x46, 0x85, 0x3B, 0x03, 0x82, 0x11, 0x85, 0x90, 0xE4, 0x83, 0x10, 0x85, ++ 0x85, 0x14, 0xF5, 0x93, 0xD0, 0xD0, 0x90, 0x45, 0xF0, 0xD0, 0xA2, 0xD0, 0xC0, 0x32, 0xE0, 0xD0, ++ 0xC0, 0xF0, 0xC0, 0xE0, 0x02, 0xA2, 0x75, 0xA2, 0xD0, 0x75, 0xD0, 0xC0, 0x52, 0x90, 0x85, 0x08, ++ 0xE0, 0x42, 0x07, 0x90, 0x54, 0x13, 0x13, 0x13, 0x05, 0xE0, 0x30, 0x1F, 0x80, 0x44, 0x07, 0x90, ++ 0x43, 0x07, 0x90, 0x03, 0xF5, 0x0F, 0x54, 0xE0, 0x0C, 0x90, 0x75, 0x53, 0x4C, 0xA9, 0x4B, 0xAA, ++ 0x85, 0x3B, 0x03, 0x12, 0x11, 0x85, 0x90, 0x53, 0x83, 0x10, 0x85, 0x82, 0x14, 0xF5, 0x93, 0xE4, ++ 0xD0, 0x90, 0x52, 0x85, 0xD0, 0xA2, 0xD0, 0xD0, 0x32, 0xE0, 0xD0, 0xF0, 0xE0, 0x42, 0x07, 0x90, ++ 0x13, 0x13, 0x13, 0xFE, 0xE0, 0x30, 0x1F, 0x54, 0x2F, 0x80, 0x74, 0x04, 0x26, 0x17, 0x20, 0xFF, ++ 0xD2, 0x05, 0x18, 0x20, 0x0D, 0x00, 0x02, 0x18, 0x1A, 0xAE, 0xAC, 0xC2, 0x7C, 0xEE, 0x1A, 0x05, ++ 0xF5, 0x82, 0x24, 0x00, 0x00, 0x34, 0xEC, 0x82, 0xF0, 0xEF, 0x83, 0xF5, 0x19, 0x65, 0x1A, 0xE5, ++ 0x17, 0xD2, 0x02, 0x70, 0x7E, 0x22, 0xAC, 0xD2, 0xE4, 0xBD, 0x7F, 0x20, 0x08, 0x80, 0xFC, 0xFD, ++ 0x54, 0x13, 0x13, 0xE0, 0x00, 0x7C, 0xFD, 0x01, 0x70, 0x8F, 0x6F, 0x8E, 0x72, 0x8D, 0x71, 0x8C, ++ 0x70, 0x85, 0x11, 0xC2, 0x83, 0x6F, 0x85, 0x82, 0x70, 0xFF, 0x93, 0xE4, 0x20, 0x39, 0x21, 0x02, ++ 0x25, 0xB4, 0x1F, 0x11, 0x21, 0x11, 0xD2, 0x04, 0x0A, 0xB4, 0xEF, 0x2F, 0x12, 0x0D, 0x7F, 0x09, ++ 0x0A, 0x7F, 0xDC, 0x0F, 0x70, 0x85, 0x2C, 0x21, 0x83, 0x6F, 0x85, 0x82, 0x21, 0xFF, 0x93, 0xE4, ++ 0x85, 0x11, 0xC2, 0x2C, 0x6F, 0x85, 0x82, 0x70, 0xFB, 0x93, 0xE4, 0x83, 0x4F, 0x60, 0xBC, 0x24, ++ 0x64, 0x60, 0xE0, 0x24, 0x02, 0x60, 0xEC, 0x24, 0x73, 0x75, 0x29, 0x21, 0x73, 0xE5, 0xC3, 0x0C, ++ 0x80, 0x94, 0x80, 0x64, 0x2F, 0x21, 0x02, 0x50, 0x71, 0xAE, 0x72, 0xE5, 0x80, 0x08, 0x73, 0xA8, ++ 0xE7, 0xA2, 0xCE, 0x06, 0xD8, 0x13, 0xCE, 0x13, 0xF5, 0x0F, 0x54, 0xF8, 0x80, 0x64, 0xD3, 0x79, ++ 0x08, 0x40, 0x89, 0x94, 0x37, 0x24, 0x79, 0xE5, 0x06, 0x80, 0x79, 0xF5, 0x79, 0x25, 0x30, 0x74, ++ 0x79, 0xAF, 0x79, 0xF5, 0x74, 0xDC, 0x0F, 0x12, 0xF5, 0x73, 0x25, 0xFC, 0xC3, 0xBE, 0x80, 0x73, ++ 0x80, 0x64, 0x71, 0xE5, 0x10, 0x50, 0x80, 0x94, 0x72, 0x95, 0xE4, 0xC3, 0x95, 0xE4, 0x72, 0xF5, ++ 0x7F, 0x71, 0xF5, 0x71, 0xDC, 0x0F, 0x12, 0x2D, 0x71, 0x45, 0x72, 0xE5, 0x30, 0x7F, 0x05, 0x70, ++ 0xE4, 0xDC, 0x0F, 0x12, 0x72, 0xE5, 0x73, 0xF5, 0x2B, 0x60, 0x71, 0x45, 0x72, 0xAF, 0x71, 0xAE, ++ 0x0A, 0x7D, 0x00, 0x7C, 0xED, 0xAA, 0x02, 0x12, 0xAE, 0xFF, 0x30, 0x24, 0x74, 0x73, 0x05, 0x73, ++ 0xC6, 0xF8, 0x2E, 0x74, 0x71, 0xAE, 0xC6, 0xEF, 0x00, 0x7C, 0x72, 0xAF, 0x02, 0x12, 0x0A, 0x7D, ++ 0x8F, 0x71, 0x8E, 0xAA, 0xE5, 0xCF, 0x80, 0x72, 0x15, 0x14, 0x60, 0x73, 0x25, 0x74, 0x74, 0x73, ++ 0xFF, 0xE6, 0xF8, 0x73, 0x80, 0xDC, 0x0F, 0x12, 0xCF, 0xEB, 0xCF, 0xEE, 0x05, 0xDC, 0x0F, 0x12, ++ 0x70, 0x70, 0xE5, 0x70, 0x01, 0x6F, 0x05, 0x02, 0x07, 0xA8, 0x22, 0x32, 0xE7, 0x09, 0x00, 0xA9, ++ 0x09, 0x60, 0x47, 0x19, 0x18, 0x16, 0xE6, 0x08, 0xC3, 0x16, 0x01, 0x70, 0xA2, 0x22, 0xD3, 0x22, ++ 0x24, 0x33, 0xE4, 0x10, 0x54, 0xE6, 0xF8, 0x20, 0x01, 0x60, 0xC3, 0x37, 0x10, 0xC2, 0x22, 0xD3, ++ 0x02, 0x03, 0x56, 0x75, 0x10, 0xD2, 0x4C, 0x02, 0x02, 0x03, 0x56, 0x75, 0x01, 0x12, 0x4C, 0x02, ++ 0x32, 0x59, 0x48, 0x50, 0x56, 0x5F, 0x46, 0x32, 0x41, 0x5F, 0x39, 0x52, 0x00, 0x0A, 0x32, 0x32, ++ 0x4C, 0x4F, 0x54, 0x50, 0x44, 0x25, 0x20, 0x3A, 0x93, 0xAA, 0x00, 0x0A, 0x39, 0x4F, 0x66, 0x7D, ++ 0xF5, 0xE4, 0x0B, 0x22, 0xC2, 0x1A, 0xF5, 0x19, 0x22, 0x17, 0xC2, 0x18, 0xC2, 0x7F, 0x23, 0x7E, ++ 0x7E, 0x98, 0x03, 0x12, 0x12, 0x1C, 0x7F, 0x26, 0x26, 0x7E, 0x98, 0x03, 0x03, 0x12, 0x1B, 0x7F, ++ 0x7F, 0x21, 0x7E, 0x98, 0x98, 0x03, 0x12, 0xBE, 0xBE, 0x7F, 0x21, 0x7E, 0x7E, 0x98, 0x03, 0x12, ++ 0x12, 0xFC, 0x7F, 0x27, 0x27, 0x7E, 0x98, 0x03, 0x03, 0x12, 0xFC, 0x7F, 0x7F, 0x2C, 0x7E, 0x98, ++ 0x98, 0x03, 0x12, 0x73, 0x1B, 0x7F, 0x2E, 0x7E, 0x7E, 0x98, 0x03, 0x12, 0x12, 0x74, 0x7F, 0x2C, ++ 0x2E, 0x7E, 0x98, 0x03, 0x03, 0x12, 0x1B, 0x7F, 0x7F, 0x2C, 0x7E, 0x98, 0x98, 0x03, 0x12, 0xCE, ++ 0xCE, 0x7F, 0x2C, 0x7E, 0x7E, 0x98, 0x03, 0x12, 0x02, 0xD0, 0x7F, 0x26, 0xF5, 0xE4, 0x98, 0x03, ++ 0xF5, 0x27, 0xF5, 0x26, 0xF5, 0x33, 0xF5, 0x32, 0xF5, 0x2B, 0xF5, 0x2A, 0xF5, 0x37, 0xF5, 0x36, ++ 0xF5, 0x2D, 0xF5, 0x2C, 0x75, 0x39, 0xF5, 0x38, 0x3A, 0x75, 0x01, 0x2E, 0x01, 0x2F, 0x75, 0x01, ++ 0x75, 0x01, 0x3B, 0x75, 0x29, 0x75, 0x02, 0x28, 0x02, 0x34, 0x75, 0x51, 0x75, 0x56, 0x35, 0x75, ++ 0x25, 0x75, 0x01, 0x24, 0x01, 0x30, 0x75, 0xBB, 0xF5, 0xC5, 0x31, 0x75, 0x31, 0x21, 0xF5, 0x20, ++ 0x90, 0x22, 0x11, 0xC2, 0x30, 0xE0, 0xAB, 0x0D, 0x0D, 0x90, 0xF9, 0xE0, 0xF0, 0xFF, 0x74, 0xAB, ++ 0x00, 0x7F, 0x20, 0x7E, 0x31, 0x1B, 0x10, 0x12, 0xF8, 0x03, 0x12, 0x39, 0x88, 0x7D, 0xB5, 0x31, ++ 0xFF, 0xE4, 0x13, 0x7C, 0xA8, 0x7D, 0xD0, 0x31, 0xFF, 0xE4, 0x61, 0x7C, 0xFF, 0xE4, 0xF7, 0x31, ++ 0x01, 0x7F, 0x22, 0x31, 0x73, 0x31, 0x22, 0x31, 0x11, 0x12, 0x20, 0x51, 0x5E, 0x11, 0x12, 0x66, ++ 0x12, 0x47, 0x02, 0x12, 0x02, 0x12, 0x65, 0x02, 0x00, 0x07, 0x90, 0x60, 0xD2, 0xF0, 0x01, 0x74, ++ 0x07, 0xAD, 0x22, 0xE8, 0x90, 0x07, 0x70, 0xED, 0x44, 0xE0, 0x47, 0x07, 0x01, 0xBD, 0xF0, 0x01, ++ 0x47, 0x07, 0x90, 0x07, 0xF0, 0x02, 0x44, 0xE0, 0xAB, 0x0D, 0x90, 0x22, 0x0F, 0x54, 0xC4, 0xE0, ++ 0x30, 0x10, 0xC2, 0xFF, 0x10, 0xD2, 0x05, 0xE3, 0xEF, 0x0F, 0x07, 0x63, 0x93, 0x1A, 0x20, 0x90, ++ 0x30, 0x00, 0x7C, 0xFD, 0xE4, 0xC3, 0x07, 0x10, 0x9C, 0xE4, 0xFD, 0x9D, 0xAB, 0x0D, 0x90, 0xFC, ++ 0x20, 0x13, 0xC3, 0xE0, 0x7F, 0x7C, 0x04, 0xE0, 0x20, 0x7E, 0xFF, 0x7D, 0x10, 0x02, 0x10, 0x7F, ++ 0x90, 0x8E, 0x01, 0x28, 0x01, 0x74, 0x07, 0x07, 0x00, 0x07, 0x90, 0xF0, 0xE4, 0xF0, 0x04, 0x74, ++ 0x03, 0x07, 0x90, 0xF0, 0x04, 0x07, 0x90, 0xF0, 0x05, 0x07, 0x90, 0xF0, 0x07, 0x90, 0xF0, 0x04, ++ 0xF0, 0xFF, 0x74, 0x06, 0x74, 0x01, 0x07, 0x90, 0x44, 0xE0, 0xF0, 0x04, 0x10, 0xC2, 0xF0, 0x08, ++ 0x12, 0x02, 0x56, 0x75, 0x10, 0xD2, 0x4C, 0x02, 0x12, 0x02, 0x56, 0x75, 0x07, 0x90, 0x4C, 0x02, ++ 0xF0, 0x01, 0x74, 0x00, 0x43, 0x8C, 0xC2, 0x22, 0xF5, 0xE4, 0x01, 0x89, 0xD2, 0x8C, 0xF5, 0x8A, ++ 0x8E, 0xC2, 0x22, 0x8C, 0x43, 0xC2, 0x98, 0x75, 0x8D, 0x75, 0x20, 0x89, 0x22, 0x8E, 0xD2, 0xDE, ++ 0xE0, 0x47, 0x07, 0x90, 0xEF, 0xF0, 0xFE, 0x54, 0x90, 0xFF, 0x01, 0x54, 0x54, 0xE0, 0x48, 0x07, ++ 0xE4, 0xF0, 0x4F, 0xFE, 0xF0, 0x4A, 0x07, 0x90, 0xF0, 0x49, 0x07, 0x90, 0x4C, 0x07, 0x90, 0xED, ++ 0x07, 0x90, 0xEC, 0xF0, 0x90, 0x22, 0xF0, 0x4B, 0x54, 0xE0, 0x47, 0x07, 0x54, 0xEF, 0xF0, 0xFD, ++ 0xFF, 0xE0, 0x25, 0x01, 0xE0, 0x48, 0x07, 0x90, 0xF0, 0x4F, 0xFD, 0x54, 0x4E, 0x07, 0x90, 0xE4, ++ 0x4D, 0x07, 0x90, 0xF0, 0x07, 0x90, 0xED, 0xF0, 0x90, 0xEC, 0xF0, 0x50, 0x22, 0xF0, 0x4F, 0x07, ++ 0xAE, 0x01, 0x90, 0xE4, 0xA3, 0xF0, 0xA3, 0xF0, 0x78, 0xF0, 0xA3, 0xF0, 0xC3, 0x78, 0xF6, 0xC8, ++ 0xF6, 0xC4, 0x78, 0xF6, 0xF6, 0x08, 0xF6, 0x08, 0x01, 0x90, 0xF6, 0x08, 0xF0, 0xD0, 0x74, 0xE0, ++ 0x90, 0xF0, 0xE4, 0xA3, 0x30, 0x74, 0xE2, 0x01, 0x03, 0x74, 0xA3, 0xF0, 0xE4, 0x01, 0x90, 0xF0, ++ 0xA3, 0xF0, 0x30, 0x74, 0x90, 0xF0, 0x03, 0x74, 0x20, 0x74, 0xE6, 0x01, 0xF0, 0xE4, 0xA3, 0xF0, ++ 0x74, 0xE8, 0x01, 0x90, 0xE4, 0xA3, 0xF0, 0x20, 0x36, 0x06, 0x90, 0xF0, 0xA3, 0xF0, 0x0F, 0x74, ++ 0x07, 0x90, 0xF0, 0xE4, 0x44, 0xE0, 0xF0, 0x08, 0x22, 0x22, 0xF0, 0x80, 0x00, 0x00, 0x00, 0x00, ++ 0xE0, 0x43, 0x07, 0x90, 0xBF, 0xFF, 0x0F, 0x54, 0x30, 0xE0, 0x10, 0x02, 0x11, 0x12, 0x1C, 0xE5, ++ 0x75, 0xB9, 0x71, 0x5E, 0x25, 0x75, 0x01, 0x24, 0x07, 0x90, 0x22, 0xBB, 0xE5, 0x30, 0xE0, 0x44, ++ 0x66, 0x11, 0x12, 0x09, 0x75, 0x01, 0x30, 0x75, 0x00, 0x22, 0xC5, 0x31, 0x00, 0xC0, 0x00, 0xEE, ++ 0x90, 0x1E, 0x00, 0xDE, 0xD5, 0x49, 0x78, 0x00, 0x01, 0x19, 0xA4, 0x65, 0x00, 0x00, 0x00, 0xE1, ++ 0x20, 0x01, 0x20, 0x04, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, ++ 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x44, 0xAA, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x06, 0xFF, 0xFF, 0xFF, 0x3F, 0x40, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, ++ 0xFF, 0x00, 0x48, 0xFF, 0xFF, 0x00, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0xE0, 0x3F, 0xFF, ++ 0xFF, 0xFF, 0xFF, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x3A, 0xF8, 0x00, 0xFF, 0x7F, 0xFF, 0xF0, 0xF8, ++ 0xFF, 0x3C, 0x66, 0xFF, 0xFF, 0xC0, 0x43, 0xFF, 0xD0, 0xF0, 0xF0, 0xFF, 0xFF, 0x00, 0x00, 0x8C, ++ 0xA2, 0xFF, 0xFF, 0xFF, 0x33, 0xFE, 0xE4, 0x10, 0x33, 0xC3, 0x06, 0x78, 0xD8, 0xCE, 0x33, 0xCE, ++ 0xF5, 0x00, 0x24, 0xF9, 0x3E, 0x06, 0x74, 0x82, 0x57, 0xF5, 0x82, 0xAF, 0x7C, 0xFE, 0x58, 0x8F, ++ 0xAB, 0x33, 0x7D, 0x20, 0xA2, 0x92, 0x51, 0x56, 0x24, 0x33, 0xE4, 0x10, 0xF6, 0xE4, 0xF8, 0x7F, ++ 0x02, 0xB4, 0x56, 0xE5, 0x24, 0x58, 0xE5, 0x11, 0x35, 0xE4, 0xFF, 0x80, 0x20, 0x7C, 0xFE, 0x57, ++ 0x02, 0x7B, 0x73, 0x7D, 0x56, 0xE5, 0x92, 0x51, 0x19, 0x60, 0x02, 0x64, 0x03, 0x64, 0x56, 0xE5, ++ 0xC5, 0x21, 0x02, 0x60, 0x28, 0x24, 0x58, 0xE5, 0x35, 0xE4, 0x82, 0xF5, 0xE0, 0x83, 0xF5, 0x57, ++ 0x21, 0x02, 0xE0, 0x30, 0xE4, 0x10, 0xA2, 0xC5, 0x54, 0xF8, 0xC4, 0x33, 0xFF, 0x68, 0xC8, 0x0F, ++ 0xF0, 0x54, 0xC4, 0xE4, 0x82, 0x74, 0xFE, 0x48, 0x74, 0x82, 0xF5, 0x2F, 0x83, 0xF5, 0x3E, 0x01, ++ 0xF0, 0xA3, 0xF0, 0xE4, 0xF5, 0x2F, 0x84, 0x74, 0x3E, 0x01, 0x74, 0x82, 0xF0, 0xE4, 0x83, 0xF5, ++ 0x86, 0x74, 0xF0, 0xA3, 0x74, 0x82, 0xF5, 0x2F, 0x83, 0xF5, 0x3E, 0x01, 0x74, 0xA3, 0xF0, 0xE4, ++ 0x88, 0x74, 0xF0, 0x02, 0x74, 0x82, 0xF5, 0x2F, 0x83, 0xF5, 0x3E, 0x01, 0xF0, 0xA3, 0xF0, 0xE4, ++ 0xF5, 0x2F, 0x8E, 0x74, 0x3E, 0x01, 0x74, 0x82, 0xF0, 0xE4, 0x83, 0xF5, 0xF0, 0x02, 0x74, 0xA3, ++ 0xF5, 0x2F, 0x90, 0x74, 0x3E, 0x01, 0x74, 0x82, 0xF0, 0xE4, 0x83, 0xF5, 0x10, 0x30, 0xF0, 0xA3, ++ 0xEC, 0x01, 0x90, 0x05, 0x90, 0xE4, 0x04, 0x80, 0xA3, 0xF0, 0xEA, 0x01, 0xF9, 0x01, 0x90, 0xF0, ++ 0x90, 0xF0, 0x11, 0x74, 0x40, 0x74, 0xFA, 0x01, 0xFB, 0x01, 0x90, 0xF0, 0x90, 0xF0, 0x80, 0x74, ++ 0xF0, 0x74, 0xFC, 0x01, 0xFD, 0x01, 0x90, 0xF0, 0x90, 0xF0, 0xC0, 0x74, 0x80, 0x74, 0xFE, 0x01, ++ 0x01, 0x90, 0xE4, 0xF0, 0x10, 0x30, 0xF0, 0xFF, 0xBA, 0x01, 0x90, 0x05, 0x90, 0xE4, 0x04, 0x80, ++ 0xA3, 0xF0, 0xB8, 0x01, 0x90, 0xFF, 0xE4, 0xF0, 0x13, 0xE0, 0x0D, 0x07, 0x30, 0x3F, 0x54, 0x13, ++ 0x02, 0x7F, 0x02, 0xE0, 0xE0, 0x0D, 0x07, 0x90, 0x54, 0x13, 0x13, 0x13, 0x03, 0xE0, 0x30, 0x1F, ++ 0x90, 0x01, 0x07, 0x43, 0xC4, 0xE0, 0x0D, 0x07, 0xE0, 0x30, 0x0F, 0x54, 0x08, 0x07, 0x43, 0x03, ++ 0xE0, 0x0D, 0x07, 0x90, 0x07, 0x54, 0x13, 0xC4, 0x43, 0x03, 0xE0, 0x30, 0x00, 0x7E, 0x04, 0x07, ++ 0xC3, 0x05, 0x78, 0xEF, 0xCE, 0x33, 0xCE, 0x33, 0xE5, 0xFF, 0xF9, 0xD8, 0xF5, 0x08, 0x24, 0x58, ++ 0x57, 0x35, 0xE4, 0x82, 0x83, 0xC0, 0x83, 0xF5, 0x54, 0xE0, 0x82, 0xC0, 0xE0, 0xA3, 0xFC, 0xE0, ++ 0xEC, 0xFD, 0x1F, 0x54, 0x4F, 0xED, 0xFE, 0x4E, 0xD0, 0x82, 0xD0, 0xFF, 0xA3, 0xF0, 0xEE, 0x83, ++ 0x58, 0x85, 0xF0, 0xEF, 0x83, 0x57, 0x85, 0x82, 0xF0, 0x20, 0x44, 0xE0, 0xBF, 0x54, 0xE0, 0xA3, ++ 0xE4, 0x10, 0xA2, 0xF0, 0x20, 0x24, 0xFD, 0x33, 0xA2, 0xF6, 0xE4, 0xF8, 0xFB, 0x33, 0xFA, 0x10, ++ 0xEA, 0xFF, 0xE0, 0x25, 0xAE, 0x74, 0xFE, 0x33, 0x74, 0x82, 0xF5, 0x2F, 0x83, 0xF5, 0x3E, 0x01, ++ 0xF0, 0xA3, 0xF0, 0xE4, 0x78, 0x00, 0x7E, 0xEB, 0xCE, 0x33, 0xC3, 0x06, 0xF9, 0xD8, 0xCE, 0x33, ++ 0x82, 0xF5, 0x00, 0x24, 0xF5, 0x3E, 0x06, 0x74, 0x7F, 0x54, 0xE0, 0x83, 0xEF, 0x05, 0xAF, 0xF0, ++ 0xA4, 0x40, 0xF0, 0x75, 0x82, 0xF5, 0x80, 0x24, 0xF5, 0x06, 0x34, 0xE4, 0x7F, 0x54, 0xE0, 0x83, ++ 0x59, 0x8E, 0x22, 0xF0, 0x5B, 0x8C, 0x5A, 0x8F, 0x63, 0x8E, 0x5C, 0x8D, 0x64, 0xE5, 0x64, 0x8F, ++ 0x82, 0xF5, 0x28, 0x24, 0xF5, 0x63, 0x35, 0xE4, 0x92, 0x13, 0xE0, 0x83, 0x24, 0x64, 0xE5, 0x11, ++ 0xE4, 0x82, 0xF5, 0x2C, 0x83, 0xF5, 0x63, 0x35, 0x13, 0x13, 0xC4, 0xE0, 0x13, 0x01, 0x54, 0x13, ++ 0xFF, 0xE4, 0x12, 0x92, 0x60, 0xFD, 0x24, 0xEB, 0x70, 0x03, 0x24, 0x0B, 0x5D, 0xF5, 0xE4, 0x65, ++ 0x79, 0x80, 0x5E, 0xF5, 0xEF, 0x5B, 0x11, 0x30, 0x40, 0x0F, 0x94, 0xD3, 0xE0, 0x25, 0xEF, 0x55, ++ 0x82, 0xF5, 0x73, 0x24, 0xF5, 0x20, 0x34, 0xE4, 0xF5, 0x93, 0xE4, 0x83, 0x93, 0x01, 0x74, 0x61, ++ 0x5C, 0xE5, 0x62, 0xF5, 0xF5, 0x02, 0x24, 0xFD, 0xFC, 0x5B, 0xE5, 0x5C, 0x5B, 0xF5, 0x00, 0x34, ++ 0x83, 0x8C, 0x82, 0x8D, 0x61, 0x55, 0x93, 0xE4, 0x01, 0x74, 0x5F, 0xF5, 0xF5, 0x62, 0x55, 0x93, ++ 0x82, 0x5A, 0x85, 0x60, 0xE5, 0x83, 0x59, 0x85, 0xE5, 0xFD, 0xF4, 0x62, 0xE0, 0xFC, 0xF4, 0x61, ++ 0xE0, 0xA3, 0xFC, 0x5C, 0x5F, 0xE5, 0xFD, 0x5D, 0xE5, 0x5D, 0xF5, 0x4C, 0x5E, 0xF5, 0x4D, 0x60, ++ 0x5C, 0xE5, 0x1B, 0x80, 0xF5, 0x02, 0x24, 0xFD, 0xFC, 0x5B, 0xE5, 0x5C, 0x5B, 0xF5, 0x00, 0x34, ++ 0x83, 0x8C, 0x82, 0x8D, 0x5D, 0xF5, 0x93, 0xE4, 0xF5, 0x93, 0x01, 0x74, 0xFD, 0x5A, 0xE5, 0x5E, ++ 0x5A, 0xF5, 0x02, 0x24, 0x34, 0xFC, 0x59, 0xE5, 0x8D, 0x59, 0xF5, 0x00, 0xE5, 0x83, 0x8C, 0x82, ++ 0xE5, 0xA3, 0xF0, 0x5D, 0xEF, 0x0F, 0xF0, 0x5E, 0x02, 0x60, 0x20, 0x64, 0x11, 0x30, 0xC4, 0x41, ++ 0x24, 0x64, 0xE5, 0x0F, 0xE4, 0x82, 0xF5, 0x38, 0x83, 0xF5, 0x63, 0x35, 0xF0, 0xA3, 0xF0, 0xE4, ++ 0x70, 0x03, 0x64, 0xEB, 0x33, 0x11, 0xA2, 0x33, 0xE5, 0xFF, 0x01, 0x54, 0xF5, 0x28, 0x24, 0x64, ++ 0x63, 0x35, 0xE4, 0x82, 0x54, 0xE0, 0x83, 0xF5, 0xA2, 0xF0, 0x4F, 0xFE, 0x54, 0x33, 0xE4, 0x12, ++ 0x33, 0x33, 0xC4, 0x01, 0xFF, 0x80, 0x54, 0x33, 0x2C, 0x24, 0x64, 0xE5, 0x35, 0xE4, 0x82, 0xF5, ++ 0xE0, 0x83, 0xF5, 0x63, 0xF0, 0x4F, 0x7F, 0x54, 0x2B, 0x20, 0x90, 0x22, 0xF5, 0x93, 0x01, 0x74, ++ 0x00, 0x22, 0x22, 0x56, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xE0, 0x43, 0x07, 0x90, 0xE4, 0x0C, 0xE5, 0x30, 0xF0, 0xB3, 0x01, 0x90, 0x27, 0xA9, 0x26, 0xAA, ++ 0xE5, 0x3B, 0x03, 0x02, 0xE4, 0x05, 0x60, 0x2E, 0x27, 0xF5, 0x26, 0xF5, 0x3A, 0x30, 0x50, 0x22, ++ 0x6E, 0x69, 0x61, 0x4D, 0x30, 0x50, 0x00, 0x0A, 0x69, 0x6E, 0x49, 0x3A, 0x00, 0x0A, 0x30, 0x74, ++ 0x49, 0x3A, 0x30, 0x50, 0x31, 0x74, 0x69, 0x6E, 0x30, 0x50, 0x00, 0x0A, 0x74, 0x63, 0x41, 0x3A, ++ 0x0A, 0x65, 0x76, 0x69, 0x3A, 0x30, 0x50, 0x00, 0x41, 0x2F, 0x44, 0x43, 0x54, 0x53, 0x49, 0x42, ++ 0x0A, 0x53, 0x4E, 0x20, 0x3A, 0x30, 0x50, 0x00, 0x73, 0x65, 0x54, 0x09, 0x0A, 0x44, 0x50, 0x74, ++ 0x3A, 0x30, 0x50, 0x00, 0x65, 0x53, 0x09, 0x09, 0x0A, 0x70, 0x75, 0x74, 0x3A, 0x30, 0x50, 0x00, ++ 0x44, 0x50, 0x09, 0x09, 0x0A, 0x6E, 0x77, 0x6F, 0x3A, 0x30, 0x50, 0x00, 0x42, 0x4C, 0x09, 0x09, ++ 0x30, 0x50, 0x00, 0x0A, 0x09, 0x09, 0x09, 0x3A, 0x3D, 0x4C, 0x4F, 0x43, 0x00, 0x0A, 0x64, 0x25, ++ 0x09, 0x3A, 0x30, 0x50, 0x74, 0x69, 0x78, 0x45, 0x30, 0x50, 0x00, 0x0A, 0xE5, 0x00, 0x0A, 0x3A, ++ 0x7E, 0x10, 0x60, 0x2E, 0x12, 0x1D, 0x7F, 0x20, 0x2C, 0x75, 0x1B, 0x10, 0xD3, 0x2D, 0x75, 0x20, ++ 0xE5, 0x01, 0x2F, 0x75, 0x70, 0x2D, 0x65, 0x2B, 0x65, 0x2A, 0xE5, 0x04, 0x85, 0x09, 0x60, 0x2C, ++ 0x2D, 0x85, 0x2A, 0x2C, 0x01, 0x2F, 0x75, 0x2B, 0x2B, 0xA9, 0x2A, 0xAA, 0xE4, 0x3B, 0x03, 0x12, ++ 0xE5, 0x22, 0x2F, 0xF5, 0x7E, 0x3E, 0x60, 0x2F, 0x12, 0x26, 0x7F, 0x20, 0x06, 0x90, 0x1B, 0x10, ++ 0x13, 0xC4, 0xE0, 0x00, 0x01, 0x54, 0x13, 0x13, 0x90, 0x2A, 0xE0, 0x30, 0x54, 0xE0, 0x44, 0x07, ++ 0x60, 0x02, 0x64, 0x0F, 0x7F, 0x01, 0x7E, 0x0C, 0x31, 0xB5, 0xEF, 0xB1, 0x30, 0xB5, 0xEE, 0x0B, ++ 0x2A, 0xF5, 0xE4, 0x07, 0x06, 0x80, 0x2B, 0xF5, 0x24, 0x8E, 0xE8, 0xC2, 0x01, 0x90, 0x25, 0x8F, ++ 0xF0, 0xFE, 0x74, 0xB3, 0x21, 0x2C, 0x75, 0x22, 0x22, 0x1C, 0x2D, 0x75, 0x1A, 0x60, 0x2F, 0xE5, ++ 0x30, 0x7F, 0x20, 0x7E, 0x75, 0x1B, 0x10, 0x12, 0x29, 0x75, 0x02, 0x28, 0x01, 0x24, 0x75, 0x60, ++ 0x90, 0xCF, 0x25, 0x75, 0xFE, 0x74, 0xB3, 0x01, 0x2C, 0x75, 0x22, 0xF0, 0x41, 0x2D, 0x75, 0x21, ++ 0x60, 0x2F, 0xE5, 0x22, 0x7F, 0x20, 0x7E, 0x0D, 0x1B, 0x10, 0x12, 0x3A, 0xDF, 0x54, 0x20, 0xE5, ++ 0x20, 0xE5, 0x20, 0xF5, 0x41, 0x02, 0xE0, 0x30, 0xEF, 0x20, 0xAF, 0x7C, 0xE0, 0x30, 0x13, 0xC3, ++ 0x80, 0xFF, 0xE4, 0x04, 0xEF, 0x20, 0xAF, 0x5A, 0x30, 0x0F, 0x54, 0xC4, 0x06, 0x90, 0x5A, 0xE0, ++ 0x13, 0xC4, 0xE0, 0x12, 0x06, 0x64, 0x07, 0x54, 0x21, 0xE5, 0x2F, 0x70, 0x21, 0xF5, 0x10, 0x44, ++ 0x33, 0x65, 0x56, 0x74, 0x02, 0x74, 0x04, 0x70, 0x02, 0x60, 0x32, 0x65, 0x5B, 0x74, 0x9F, 0x41, ++ 0x04, 0x70, 0x37, 0x65, 0x36, 0x65, 0x02, 0x74, 0x9F, 0x41, 0x02, 0x60, 0x75, 0x02, 0x28, 0x75, ++ 0x24, 0x75, 0x92, 0x29, 0x33, 0x25, 0x75, 0x02, 0x12, 0x06, 0x90, 0x22, 0x54, 0x13, 0xC4, 0xE0, ++ 0x05, 0x94, 0xD3, 0x07, 0x20, 0x7E, 0x07, 0x40, 0x10, 0x02, 0x45, 0x7F, 0x51, 0x01, 0x7F, 0x1B, ++ 0x22, 0x28, 0x75, 0xA0, 0x22, 0xA9, 0x29, 0x75, 0xB4, 0xE6, 0x7F, 0x78, 0x06, 0x90, 0x0A, 0x01, ++ 0x54, 0xC4, 0xE0, 0x00, 0x0C, 0xE0, 0x20, 0x0F, 0xE0, 0x00, 0x06, 0x90, 0x30, 0x0F, 0x54, 0xC4, ++ 0x83, 0x41, 0x02, 0xE0, 0xE0, 0x00, 0x06, 0x90, 0x20, 0x0F, 0x54, 0xC4, 0xE0, 0xA3, 0x61, 0xE0, ++ 0x54, 0x13, 0x13, 0xC4, 0xFF, 0xE0, 0x25, 0x01, 0xE0, 0x00, 0x06, 0x90, 0x01, 0x54, 0x13, 0xC4, ++ 0x06, 0x90, 0xFD, 0x4F, 0x03, 0x54, 0xE0, 0x31, 0x90, 0x07, 0x60, 0x6D, 0x44, 0xE0, 0x35, 0x06, ++ 0x05, 0xAF, 0xF0, 0x02, 0xFF, 0x03, 0x54, 0xED, 0xE0, 0x31, 0x06, 0x90, 0xF0, 0x4F, 0xFC, 0x54, ++ 0xE0, 0x00, 0x06, 0x90, 0x90, 0xFF, 0x01, 0x54, 0xFE, 0xE0, 0x31, 0x06, 0x54, 0x13, 0x13, 0x13, ++ 0x07, 0x60, 0x6F, 0x01, 0xE0, 0x35, 0x06, 0x90, 0x90, 0xF0, 0x04, 0x44, 0x54, 0xE0, 0x00, 0x06, ++ 0x33, 0x33, 0x33, 0x01, 0x90, 0xFF, 0xF8, 0x54, 0x54, 0xE0, 0x31, 0x06, 0x90, 0xF0, 0x4F, 0xF7, ++ 0x54, 0xE0, 0x31, 0x06, 0x14, 0x14, 0x60, 0x03, 0x01, 0x7F, 0x22, 0x70, 0x28, 0x75, 0xA0, 0x51, ++ 0x74, 0x29, 0x75, 0x02, 0x75, 0x01, 0x24, 0x75, 0x7F, 0x22, 0xF7, 0x25, 0x75, 0xA0, 0x51, 0x01, ++ 0x29, 0x75, 0x02, 0x28, 0x01, 0x24, 0x75, 0x6A, 0x22, 0xE3, 0x25, 0x75, 0x75, 0x20, 0x2C, 0x75, ++ 0x90, 0x22, 0xD3, 0x2D, 0xC4, 0xE0, 0x00, 0x06, 0xE0, 0x30, 0x0F, 0x54, 0x51, 0xFF, 0xE4, 0x12, ++ 0x75, 0x7C, 0x91, 0xA0, 0x29, 0x75, 0x02, 0x28, 0x02, 0x24, 0x75, 0x88, 0x22, 0x1F, 0x25, 0x75, ++ 0x20, 0x7E, 0x56, 0x8F, 0x10, 0x02, 0x9A, 0x7F, 0x60, 0x2E, 0xE5, 0x1B, 0x7F, 0x20, 0x7E, 0x10, ++ 0x1B, 0x10, 0x12, 0x55, 0x75, 0x22, 0x2C, 0x75, 0x2F, 0x75, 0xE8, 0x2D, 0x30, 0x20, 0xE5, 0x01, ++ 0x2C, 0x75, 0x06, 0xE0, 0x01, 0x2D, 0x75, 0x26, 0x2D, 0x65, 0x2B, 0xE5, 0x2A, 0xE5, 0x04, 0x70, ++ 0x09, 0x60, 0x2C, 0x65, 0x85, 0x2A, 0x2C, 0x85, 0x2F, 0x75, 0x2B, 0x2D, 0xA9, 0x2A, 0xAA, 0x01, ++ 0x3B, 0x03, 0x12, 0x2B, 0x22, 0x2F, 0xF5, 0xE4, 0x07, 0x60, 0x2F, 0xE5, 0x61, 0x7F, 0x20, 0x7E, ++ 0x90, 0x1B, 0x10, 0x12, 0xC4, 0xE0, 0x00, 0x06, 0x03, 0x54, 0x13, 0x13, 0xE0, 0x13, 0xE0, 0x20, ++ 0x3F, 0x54, 0x13, 0x13, 0xA3, 0x0B, 0xE0, 0x20, 0x13, 0x13, 0xC4, 0xE0, 0x30, 0x01, 0x54, 0x13, ++ 0x01, 0x90, 0x0E, 0xE0, 0x20, 0x44, 0xE0, 0xAE, 0x23, 0x2C, 0x75, 0xF0, 0x22, 0x79, 0x2D, 0x75, ++ 0x75, 0x23, 0x2C, 0x75, 0xE5, 0x22, 0x27, 0x2D, 0x7E, 0x3F, 0x60, 0x2F, 0x12, 0x6D, 0x7F, 0x20, ++ 0x01, 0x90, 0x1B, 0x10, 0x01, 0x44, 0xE0, 0xAE, 0x12, 0x0C, 0x7F, 0xF0, 0x07, 0x90, 0xE2, 0x03, ++ 0x01, 0x44, 0xE0, 0x63, 0x02, 0x44, 0xE0, 0xF0, 0xFE, 0x54, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xF0, ++ 0x01, 0x0D, 0x90, 0xF0, 0xF0, 0xDF, 0x54, 0xE0, 0xE0, 0x21, 0x0D, 0x90, 0x90, 0xF0, 0xDF, 0x54, ++ 0x54, 0xE0, 0xF8, 0x07, 0x54, 0xE0, 0xF0, 0xFE, 0x20, 0xAF, 0xF0, 0xFD, 0x20, 0x13, 0xC3, 0xEF, ++ 0x2C, 0x75, 0x06, 0xE0, 0x01, 0x2D, 0x75, 0x26, 0x70, 0x2F, 0xE5, 0x22, 0x7E, 0x0E, 0x81, 0x02, ++ 0x12, 0x79, 0x7F, 0x20, 0x06, 0x90, 0x1B, 0x10, 0xA3, 0xFE, 0xE0, 0x00, 0xCE, 0x06, 0x78, 0xE0, ++ 0x13, 0xCE, 0x13, 0xC3, 0x01, 0x54, 0xF9, 0xD8, 0xE4, 0xFD, 0xE0, 0x25, 0x00, 0x06, 0x90, 0x33, ++ 0x54, 0x13, 0xC4, 0xE0, 0x4F, 0xED, 0xFF, 0x01, 0x90, 0xFF, 0x03, 0x54, 0xFC, 0xE0, 0x30, 0x06, ++ 0xFC, 0x54, 0xE0, 0xA3, 0xED, 0xFE, 0xEC, 0xFD, 0x06, 0x90, 0xFF, 0x4F, 0xA3, 0xF0, 0xEE, 0x30, ++ 0x07, 0x90, 0xF0, 0xEF, 0x01, 0x44, 0xE0, 0x7B, 0x31, 0x06, 0x90, 0xF0, 0xFF, 0x03, 0x54, 0xE0, ++ 0xE0, 0x7C, 0x07, 0x90, 0xF0, 0x4F, 0xF8, 0x54, 0x74, 0x94, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x01, ++ 0x07, 0x90, 0xF0, 0x95, 0xF0, 0x03, 0x74, 0x96, 0x95, 0x07, 0x90, 0xE4, 0x98, 0x07, 0x90, 0xF0, ++ 0x07, 0x90, 0xF0, 0x04, 0x07, 0x90, 0xF0, 0x99, 0xE4, 0xF0, 0x04, 0x9A, 0xF0, 0x99, 0x07, 0x90, ++ 0xE0, 0x7F, 0x07, 0x90, 0x90, 0xF0, 0x03, 0x44, 0x44, 0xE0, 0x03, 0x06, 0x07, 0x90, 0xF0, 0x04, ++ 0x01, 0x54, 0xE0, 0x80, 0x01, 0x06, 0x90, 0xFF, 0x13, 0x13, 0xC4, 0xE0, 0x6F, 0x01, 0x54, 0x13, ++ 0x20, 0x7E, 0x26, 0x60, 0xC4, 0xE0, 0x82, 0x7F, 0x54, 0x13, 0x13, 0x13, 0x00, 0x7C, 0xFD, 0x01, ++ 0x90, 0x28, 0x10, 0x12, 0x54, 0xE0, 0x01, 0x06, 0x13, 0x13, 0xC4, 0x80, 0xFF, 0x01, 0x54, 0x13, ++ 0xE0, 0x80, 0x07, 0x90, 0xF0, 0x4F, 0xFE, 0x54, 0xE0, 0x00, 0x06, 0x90, 0x54, 0x13, 0x13, 0xC4, ++ 0x27, 0xE0, 0x20, 0x03, 0x54, 0x13, 0x13, 0xE0, 0x1F, 0xE0, 0x20, 0x3F, 0x13, 0xC4, 0xE0, 0xA3, ++ 0x01, 0x54, 0x13, 0x13, 0x90, 0x14, 0xE0, 0x20, 0x54, 0xE0, 0x7F, 0x07, 0x06, 0x90, 0xF0, 0xFC, ++ 0xFB, 0x54, 0xE0, 0x03, 0x26, 0x2C, 0x75, 0xF0, 0x22, 0x01, 0x2D, 0x75, 0x01, 0x0D, 0x90, 0xE4, ++ 0x00, 0x0D, 0x90, 0xF0, 0xE0, 0xF0, 0x18, 0x74, 0xF0, 0x20, 0x0D, 0x90, 0x74, 0x0A, 0x0D, 0x90, ++ 0x0D, 0x90, 0xF0, 0x69, 0x0D, 0x90, 0xF0, 0x2A, 0xF0, 0x7C, 0x74, 0x06, 0xF0, 0x26, 0x0D, 0x90, ++ 0x74, 0xA2, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0xAA, 0xF0, 0x11, 0x74, 0x0C, 0xF0, 0x2C, 0x0D, 0x90, ++ 0x74, 0x02, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x30, 0x0D, 0x90, 0xF0, 0x22, 0xF0, 0x20, 0x74, 0x05, ++ 0xF0, 0x25, 0x0D, 0x90, 0x21, 0x0D, 0x90, 0xE4, 0xF8, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, ++ 0xF0, 0xFD, 0x54, 0xE0, 0xE0, 0xFD, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, 0x54, 0xE0, 0x03, 0x08, ++ 0x08, 0x90, 0xF0, 0xF8, 0xF0, 0x03, 0x74, 0x67, 0x90, 0xF0, 0x01, 0x74, 0x54, 0xE0, 0x10, 0x07, ++ 0x10, 0xF0, 0x75, 0x0F, 0xFD, 0xAB, 0x24, 0xA4, 0xFC, 0xF0, 0x35, 0xE4, 0xE0, 0x0F, 0x07, 0x90, ++ 0xA4, 0xAA, 0xF0, 0x75, 0x78, 0x2D, 0xF0, 0xAE, 0x3C, 0xEE, 0xF6, 0x85, 0xE6, 0x08, 0xF6, 0x18, ++ 0xF0, 0x6A, 0x08, 0x90, 0xE0, 0x0F, 0x07, 0x90, 0xF0, 0x75, 0x0F, 0x54, 0x90, 0xFF, 0xA4, 0x10, ++ 0xC4, 0xE0, 0x10, 0x07, 0xE5, 0xFD, 0x0F, 0x54, 0x4F, 0xED, 0xFC, 0xF0, 0x2D, 0xE6, 0x18, 0xFD, ++ 0xCF, 0x3C, 0xE4, 0xFF, 0xF6, 0x08, 0xAA, 0x24, 0xF6, 0x18, 0x3F, 0xE4, 0x08, 0x90, 0xE6, 0x08, ++ 0x07, 0x90, 0xF0, 0x69, 0x54, 0xC4, 0xE0, 0x0F, 0xE6, 0x18, 0xFD, 0x0F, 0x33, 0xE4, 0xFF, 0x2D, ++ 0x08, 0x0A, 0x24, 0xCF, 0x18, 0x3F, 0xE4, 0xF6, 0x90, 0xE6, 0x08, 0xF6, 0x90, 0xF0, 0x68, 0x08, ++ 0x01, 0x74, 0x6B, 0x08, 0x52, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x0B, 0x74, 0x07, 0x74, 0x51, 0x08, ++ 0x52, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x0A, 0x74, 0x06, 0x74, 0x51, 0x08, 0x39, 0x08, 0x90, 0xF0, ++ 0x90, 0xF0, 0x01, 0x74, 0x90, 0xF0, 0x40, 0x08, 0x0B, 0x74, 0x41, 0x08, 0xF0, 0x09, 0x74, 0xF0, ++ 0x74, 0x42, 0x08, 0x90, 0x01, 0x74, 0xF0, 0x03, 0x43, 0x08, 0x90, 0xF0, 0x74, 0xF0, 0x03, 0x74, ++ 0x08, 0x90, 0xF0, 0x01, 0xF0, 0x03, 0x74, 0x3E, 0x90, 0xF0, 0x01, 0x74, 0x03, 0x74, 0x54, 0x08, ++ 0x55, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x0F, 0x74, 0x90, 0xF0, 0x56, 0x08, 0x11, 0x74, 0x5B, 0x08, ++ 0x5D, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x03, 0x74, 0x01, 0x74, 0x54, 0x08, 0x7B, 0x07, 0x90, 0xF0, ++ 0x7C, 0x07, 0x90, 0xF0, 0x44, 0xF8, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x03, 0xF0, 0x01, 0x74, 0x9F, ++ 0xF0, 0x94, 0x07, 0x90, 0xF0, 0x95, 0x07, 0x90, 0xF0, 0x98, 0x07, 0x90, 0xF0, 0x99, 0x07, 0x90, ++ 0x74, 0x9C, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x03, 0x07, 0x90, 0xF0, 0x9D, 0xF0, 0xFF, 0x74, 0xA4, ++ 0x7F, 0x20, 0x7E, 0x22, 0x1B, 0x10, 0x12, 0x90, 0xAE, 0x01, 0x90, 0xE4, 0x75, 0xF0, 0xA3, 0xF0, ++ 0x29, 0x75, 0x02, 0x28, 0x01, 0x24, 0x75, 0x51, 0x22, 0xBB, 0x25, 0x75, 0x00, 0x00, 0x00, 0x22, ++ 0xE0, 0x44, 0x07, 0x90, 0xE4, 0x0C, 0xE5, 0x30, 0xF0, 0xB4, 0x01, 0x90, 0x33, 0xA9, 0x32, 0xAA, ++ 0xE5, 0x3B, 0x03, 0x02, 0xE4, 0x05, 0x60, 0x3A, 0x33, 0xF5, 0x32, 0xF5, 0x3A, 0x31, 0x50, 0x22, ++ 0x6E, 0x69, 0x61, 0x4D, 0x31, 0x50, 0x00, 0x0A, 0x69, 0x6E, 0x49, 0x3A, 0x00, 0x0A, 0x30, 0x74, ++ 0x49, 0x3A, 0x31, 0x50, 0x31, 0x74, 0x69, 0x6E, 0x31, 0x50, 0x00, 0x0A, 0x74, 0x63, 0x41, 0x3A, ++ 0x0A, 0x65, 0x76, 0x69, 0x3A, 0x31, 0x50, 0x00, 0x41, 0x2F, 0x44, 0x43, 0x54, 0x53, 0x49, 0x42, ++ 0x0A, 0x53, 0x4E, 0x20, 0x3A, 0x31, 0x50, 0x00, 0x4C, 0x44, 0x49, 0x09, 0x50, 0x00, 0x0A, 0x45, ++ 0x54, 0x09, 0x3A, 0x31, 0x50, 0x74, 0x73, 0x65, 0x50, 0x00, 0x0A, 0x44, 0x09, 0x09, 0x3A, 0x31, ++ 0x75, 0x74, 0x65, 0x53, 0x50, 0x00, 0x0A, 0x70, 0x09, 0x09, 0x3A, 0x31, 0x77, 0x6F, 0x44, 0x50, ++ 0x50, 0x00, 0x0A, 0x6E, 0x09, 0x09, 0x3A, 0x31, 0x00, 0x0A, 0x42, 0x4C, 0x09, 0x3A, 0x31, 0x50, ++ 0x4F, 0x43, 0x09, 0x09, 0x64, 0x25, 0x3D, 0x4C, 0x31, 0x50, 0x00, 0x0A, 0x78, 0x45, 0x09, 0x3A, ++ 0x00, 0x0A, 0x74, 0x69, 0x0A, 0x3A, 0x31, 0x50, 0x60, 0x3A, 0xE5, 0x00, 0x7F, 0x20, 0x7E, 0x10, ++ 0x1B, 0x10, 0x12, 0x1D, 0x75, 0x20, 0x38, 0x75, 0x3B, 0x75, 0xDD, 0x39, 0x65, 0x37, 0xE5, 0x01, ++ 0xE5, 0x04, 0x70, 0x39, 0x60, 0x38, 0x65, 0x36, 0x36, 0x38, 0x85, 0x09, 0x75, 0x37, 0x39, 0x85, ++ 0x36, 0xAA, 0x01, 0x3B, 0x03, 0x12, 0x37, 0xA9, 0x3B, 0xF5, 0xE4, 0x3B, 0x60, 0x3B, 0xE5, 0x22, ++ 0x7F, 0x20, 0x7E, 0x3E, 0x1B, 0x10, 0x12, 0x26, 0xE0, 0x40, 0x06, 0x90, 0x13, 0x13, 0x13, 0xC4, ++ 0xE0, 0x30, 0x01, 0x54, 0x43, 0x07, 0x90, 0x2A, 0x64, 0x0F, 0x54, 0xE0, 0x7E, 0x0C, 0x60, 0x02, ++ 0xEF, 0xB1, 0x7F, 0x01, 0xEE, 0x0B, 0x25, 0xB5, 0xE4, 0x07, 0x24, 0xB5, 0x37, 0xF5, 0x36, 0xF5, ++ 0xE8, 0xC2, 0x06, 0x80, 0x31, 0x8F, 0x30, 0x8E, 0x74, 0xB4, 0x01, 0x90, 0x75, 0x22, 0xF0, 0xFE, ++ 0x39, 0x75, 0x21, 0x38, 0x3B, 0xE5, 0x22, 0x26, 0x20, 0x7E, 0x1A, 0x60, 0x10, 0x12, 0x30, 0x7F, ++ 0x02, 0x34, 0x75, 0x1B, 0x75, 0x65, 0x35, 0x75, 0x31, 0x75, 0x01, 0x30, 0xB4, 0x01, 0x90, 0xD9, ++ 0x22, 0xF0, 0xFE, 0x74, 0x75, 0x21, 0x38, 0x75, 0xE5, 0x22, 0x4B, 0x39, 0x7E, 0x0D, 0x60, 0x3B, ++ 0x12, 0x3A, 0x7F, 0x20, 0x21, 0xE5, 0x1B, 0x10, 0x21, 0xF5, 0xDF, 0x54, 0xE0, 0x30, 0x21, 0xE5, ++ 0xAF, 0x5E, 0x41, 0x02, 0x13, 0xC3, 0xEF, 0x21, 0xE4, 0x04, 0xE0, 0x30, 0xAF, 0x32, 0x80, 0xFF, ++ 0x54, 0xC4, 0xEF, 0x21, 0x32, 0xE0, 0x30, 0x0F, 0xE0, 0x12, 0x06, 0x90, 0x07, 0x54, 0x13, 0xC4, ++ 0x07, 0x06, 0xBF, 0xFF, 0x75, 0x02, 0x38, 0x75, 0x90, 0x22, 0x5B, 0x39, 0xC4, 0xE0, 0x52, 0x06, ++ 0xD3, 0x07, 0x54, 0x13, 0x07, 0x40, 0x05, 0x94, 0x45, 0x7F, 0x20, 0x7E, 0x7F, 0x1B, 0x10, 0x02, ++ 0x75, 0x82, 0x51, 0x01, 0x35, 0x75, 0x24, 0x34, 0x80, 0x78, 0x22, 0x2D, 0x0A, 0x01, 0xB4, 0xE6, ++ 0xE0, 0x40, 0x06, 0x90, 0x20, 0x0F, 0x54, 0xC4, 0x06, 0x90, 0x0C, 0xE0, 0x54, 0xC4, 0xE0, 0x40, ++ 0x02, 0xE0, 0x30, 0x0F, 0x06, 0x90, 0x65, 0x41, 0x54, 0xC4, 0xE0, 0x40, 0x61, 0xE0, 0x20, 0x0F, ++ 0x13, 0xC4, 0xE0, 0xA3, 0x25, 0x01, 0x54, 0x13, 0x06, 0x90, 0xFF, 0xE0, 0x13, 0xC4, 0xE0, 0x40, ++ 0xFD, 0x4F, 0x01, 0x54, 0xE0, 0x71, 0x06, 0x90, 0x60, 0x6D, 0x03, 0x54, 0x75, 0x06, 0x90, 0x07, ++ 0xF0, 0x02, 0x44, 0xE0, 0x54, 0xED, 0x05, 0xAF, 0x06, 0x90, 0xFF, 0x03, 0xFC, 0x54, 0xE0, 0x71, ++ 0x06, 0x90, 0xF0, 0x4F, 0x01, 0x54, 0xE0, 0x40, 0x71, 0x06, 0x90, 0xFF, 0x13, 0x13, 0xFE, 0xE0, ++ 0x6F, 0x01, 0x54, 0x13, 0x06, 0x90, 0x07, 0x60, 0x04, 0x44, 0xE0, 0x75, 0x40, 0x06, 0x90, 0xF0, ++ 0x33, 0x01, 0x54, 0xE0, 0xF8, 0x54, 0x33, 0x33, 0x71, 0x06, 0x90, 0xFF, 0x4F, 0xF7, 0x54, 0xE0, ++ 0x71, 0x06, 0x90, 0xF0, 0x60, 0x03, 0x54, 0xE0, 0x22, 0x70, 0x14, 0x14, 0x82, 0x51, 0x01, 0x7F, ++ 0x75, 0x02, 0x34, 0x75, 0x30, 0x75, 0x7E, 0x35, 0x0B, 0x31, 0x75, 0x02, 0x51, 0x01, 0x7F, 0x22, ++ 0x02, 0x34, 0x75, 0x82, 0x75, 0x6F, 0x35, 0x75, 0x31, 0x75, 0x01, 0x30, 0x38, 0x75, 0x22, 0xED, ++ 0xDD, 0x39, 0x75, 0x20, 0x40, 0x06, 0x90, 0x22, 0x0F, 0x54, 0xC4, 0xE0, 0xE4, 0x12, 0xE0, 0x30, ++ 0x51, 0x82, 0x51, 0xFF, 0x02, 0x34, 0x75, 0xA6, 0x75, 0x8D, 0x35, 0x75, 0x31, 0x75, 0x02, 0x30, ++ 0x56, 0x8F, 0x22, 0x29, 0xA4, 0x7F, 0x20, 0x7E, 0xE5, 0x1B, 0x10, 0x02, 0x7E, 0x07, 0x60, 0x3B, ++ 0x12, 0x55, 0x7F, 0x20, 0x21, 0xAF, 0x1B, 0x10, 0x0F, 0x54, 0xC4, 0xEF, 0x75, 0x06, 0xE0, 0x20, ++ 0x39, 0x75, 0x20, 0x38, 0x90, 0xE4, 0x22, 0xDD, 0x90, 0xF0, 0x41, 0x0D, 0x18, 0x74, 0x40, 0x0D, ++ 0x0D, 0x90, 0xE0, 0xF0, 0x0D, 0x90, 0xF0, 0x60, 0xF0, 0x69, 0x74, 0x4A, 0xF0, 0x6A, 0x0D, 0x90, ++ 0x74, 0x46, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x7C, 0x0D, 0x90, 0xF0, 0x66, 0xF0, 0xAA, 0x74, 0xA2, ++ 0x74, 0x4C, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x11, 0x0D, 0x90, 0xF0, 0x6C, 0xF0, 0x30, 0x74, 0x42, ++ 0xF0, 0x62, 0x0D, 0x90, 0x74, 0x45, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x20, 0x90, 0xE4, 0xF0, 0x65, ++ 0x90, 0xF0, 0x61, 0x0D, 0x54, 0xE0, 0xF8, 0x07, 0x44, 0xE0, 0xF0, 0xFB, 0x07, 0x90, 0xF0, 0x08, ++ 0x01, 0x44, 0xE0, 0xFD, 0x04, 0x08, 0x90, 0xF0, 0x44, 0x8F, 0x54, 0xE0, 0x09, 0x90, 0xF0, 0x30, ++ 0xF0, 0x03, 0x74, 0x96, 0x90, 0xF0, 0x01, 0x74, 0x54, 0xE0, 0x10, 0x07, 0x10, 0xF0, 0x75, 0x0F, ++ 0xFD, 0xAB, 0x24, 0xA4, 0xFC, 0xF0, 0x35, 0xE4, 0xE0, 0x0F, 0x07, 0x90, 0xA4, 0xAA, 0xF0, 0x75, ++ 0x78, 0x2D, 0xF0, 0xAE, 0x3C, 0xEE, 0xF6, 0xA6, 0xE6, 0x08, 0xF6, 0x18, 0xF0, 0x99, 0x09, 0x90, ++ 0xE0, 0x0F, 0x07, 0x90, 0xF0, 0x75, 0x0F, 0x54, 0x90, 0xFF, 0xA4, 0x10, 0xC4, 0xE0, 0x10, 0x07, ++ 0xE5, 0xFD, 0x0F, 0x54, 0x4F, 0xED, 0xFC, 0xF0, 0x2D, 0xE6, 0x18, 0xFD, 0xCF, 0x3C, 0xE4, 0xFF, ++ 0xF6, 0x08, 0xAA, 0x24, 0xF6, 0x18, 0x3F, 0xE4, 0x09, 0x90, 0xE6, 0x08, 0x07, 0x90, 0xF0, 0x98, ++ 0x54, 0xC4, 0xE0, 0x0F, 0xE6, 0x18, 0xFD, 0x0F, 0x33, 0xE4, 0xFF, 0x2D, 0x08, 0x0A, 0x24, 0xCF, ++ 0x18, 0x3F, 0xE4, 0xF6, 0x90, 0xE6, 0x08, 0xF6, 0x90, 0xF0, 0x97, 0x09, 0x01, 0x74, 0x9A, 0x09, ++ 0x81, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x0B, 0x74, 0x07, 0x74, 0x80, 0x09, 0x81, 0x09, 0x90, 0xF0, ++ 0x90, 0xF0, 0x0A, 0x74, 0x06, 0x74, 0x80, 0x09, 0x68, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, ++ 0x90, 0xF0, 0x6F, 0x09, 0x0B, 0x74, 0x70, 0x09, 0xF0, 0x09, 0x74, 0xF0, 0x74, 0x71, 0x09, 0x90, ++ 0x01, 0x74, 0xF0, 0x03, 0x72, 0x09, 0x90, 0xF0, 0x74, 0xF0, 0x03, 0x74, 0x09, 0x90, 0xF0, 0x01, ++ 0xF0, 0x03, 0x74, 0x6D, 0x90, 0xF0, 0x01, 0x74, 0x03, 0x74, 0x83, 0x09, 0x84, 0x09, 0x90, 0xF0, ++ 0x90, 0xF0, 0x0F, 0x74, 0x90, 0xF0, 0x85, 0x09, 0x11, 0x74, 0x8A, 0x09, 0x8C, 0x09, 0x90, 0xF0, ++ 0x90, 0xF0, 0x03, 0x74, 0x01, 0x74, 0x83, 0x09, 0xC5, 0x07, 0x90, 0xF0, 0xC6, 0x07, 0x90, 0xF0, ++ 0x44, 0xF8, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x03, 0xF0, 0x01, 0x74, 0xE9, 0xF0, 0xDE, 0x07, 0x90, ++ 0xF0, 0xDF, 0x07, 0x90, 0xF0, 0xE2, 0x07, 0x90, 0xF0, 0xE3, 0x07, 0x90, 0x74, 0xE6, 0x07, 0x90, ++ 0x07, 0x90, 0xF0, 0x03, 0x07, 0x90, 0xF0, 0xE7, 0xF0, 0xFF, 0x74, 0xEE, 0x60, 0x3A, 0xE5, 0x22, ++ 0x7F, 0x20, 0x7E, 0x10, 0x1B, 0x10, 0x12, 0x5F, 0x75, 0x24, 0x38, 0x75, 0x3B, 0x75, 0x6C, 0x39, ++ 0x30, 0x21, 0xE5, 0x01, 0x38, 0x75, 0x06, 0xE0, 0x00, 0x39, 0x75, 0x26, 0x39, 0x65, 0x37, 0xE5, ++ 0x36, 0xE5, 0x04, 0x70, 0x09, 0x60, 0x38, 0x65, 0x85, 0x36, 0x38, 0x85, 0x3B, 0x75, 0x37, 0x39, ++ 0xA9, 0x36, 0xAA, 0x01, 0x3B, 0x03, 0x12, 0x37, 0x22, 0x3B, 0xF5, 0xE4, 0x07, 0x60, 0x3B, 0xE5, ++ 0x6B, 0x7F, 0x20, 0x7E, 0x90, 0x1B, 0x10, 0x12, 0xC4, 0xE0, 0x40, 0x06, 0x03, 0x54, 0x13, 0x13, ++ 0xE0, 0x13, 0xE0, 0x20, 0x3F, 0x54, 0x13, 0x13, 0xA3, 0x0B, 0xE0, 0x20, 0x13, 0x13, 0xC4, 0xE0, ++ 0x30, 0x01, 0x54, 0x13, 0x01, 0x90, 0x0E, 0xE0, 0x20, 0x44, 0xE0, 0xB0, 0x24, 0x38, 0x75, 0xF0, ++ 0x22, 0xFD, 0x39, 0x75, 0x75, 0x24, 0x38, 0x75, 0xE5, 0x22, 0xAB, 0x39, 0x7E, 0x3F, 0x60, 0x3B, ++ 0x12, 0x77, 0x7F, 0x20, 0x01, 0x90, 0x1B, 0x10, 0x01, 0x44, 0xE0, 0xB0, 0x12, 0x0C, 0x7F, 0xF0, ++ 0x07, 0x90, 0xED, 0x03, 0x04, 0x44, 0xE0, 0x63, 0x08, 0x44, 0xE0, 0xF0, 0xFB, 0x54, 0xE0, 0xF0, ++ 0xF7, 0x54, 0xE0, 0xF0, 0x41, 0x0D, 0x90, 0xF0, 0xF0, 0xDF, 0x54, 0xE0, 0xE0, 0x61, 0x0D, 0x90, ++ 0x90, 0xF0, 0xDF, 0x54, 0x54, 0xE0, 0xF8, 0x07, 0x54, 0xE0, 0xF0, 0xFB, 0x21, 0xAF, 0xF0, 0xF7, ++ 0x20, 0x13, 0xC3, 0xEF, 0x38, 0x75, 0x06, 0xE0, 0x00, 0x39, 0x75, 0x26, 0x70, 0x3B, 0xE5, 0x22, ++ 0x7E, 0x92, 0xA1, 0x02, 0x12, 0x83, 0x7F, 0x20, 0x06, 0x90, 0x1B, 0x10, 0xA3, 0xFE, 0xE0, 0x40, ++ 0xCE, 0x06, 0x78, 0xE0, 0x13, 0xCE, 0x13, 0xC3, 0x01, 0x54, 0xF9, 0xD8, 0xE4, 0xFD, 0xE0, 0x25, ++ 0x40, 0x06, 0x90, 0x33, 0x54, 0x13, 0xC4, 0xE0, 0x4F, 0xED, 0xFF, 0x01, 0x90, 0xFF, 0x03, 0x54, ++ 0xFC, 0xE0, 0x70, 0x06, 0xFC, 0x54, 0xE0, 0xA3, 0xED, 0xFE, 0xEC, 0xFD, 0x06, 0x90, 0xFF, 0x4F, ++ 0xA3, 0xF0, 0xEE, 0x70, 0x07, 0x90, 0xF0, 0xEF, 0x01, 0x44, 0xE0, 0xC5, 0x71, 0x06, 0x90, 0xF0, ++ 0xFF, 0x03, 0x54, 0xE0, 0xE0, 0xC6, 0x07, 0x90, 0xF0, 0x4F, 0xF8, 0x54, 0x74, 0xDE, 0x07, 0x90, ++ 0x07, 0x90, 0xF0, 0x01, 0x07, 0x90, 0xF0, 0xDF, 0xF0, 0x03, 0x74, 0xE0, 0xDF, 0x07, 0x90, 0xE4, ++ 0xE2, 0x07, 0x90, 0xF0, 0x07, 0x90, 0xF0, 0x04, 0x07, 0x90, 0xF0, 0xE3, 0xE4, 0xF0, 0x04, 0xE4, ++ 0xF0, 0xE3, 0x07, 0x90, 0xE0, 0xC9, 0x07, 0x90, 0x90, 0xF0, 0x03, 0x44, 0x44, 0xE0, 0x43, 0x06, ++ 0x07, 0x90, 0xF0, 0x04, 0x01, 0x54, 0xE0, 0xCA, 0x41, 0x06, 0x90, 0xFF, 0x13, 0x13, 0xC4, 0xE0, ++ 0x6F, 0x01, 0x54, 0x13, 0x20, 0x7E, 0x26, 0x60, 0xC4, 0xE0, 0x8C, 0x7F, 0x54, 0x13, 0x13, 0x13, ++ 0x00, 0x7C, 0xFD, 0x01, 0x90, 0x28, 0x10, 0x12, 0x54, 0xE0, 0x41, 0x06, 0x13, 0x13, 0xC4, 0x80, ++ 0xFF, 0x01, 0x54, 0x13, 0xE0, 0xCA, 0x07, 0x90, 0xF0, 0x4F, 0xFE, 0x54, 0xE0, 0x40, 0x06, 0x90, ++ 0x54, 0x13, 0x13, 0xC4, 0x27, 0xE0, 0x20, 0x03, 0x54, 0x13, 0x13, 0xE0, 0x1F, 0xE0, 0x20, 0x3F, ++ 0x13, 0xC4, 0xE0, 0xA3, 0x01, 0x54, 0x13, 0x13, 0x90, 0x14, 0xE0, 0x20, 0x54, 0xE0, 0xC9, 0x07, ++ 0x06, 0x90, 0xF0, 0xFC, 0xFB, 0x54, 0xE0, 0x43, 0x26, 0x38, 0x75, 0xF0, 0x22, 0x00, 0x39, 0x75, ++ 0x9A, 0x7F, 0x20, 0x7E, 0xE4, 0x1B, 0x10, 0x12, 0xF0, 0xB0, 0x01, 0x90, 0x34, 0x75, 0xF0, 0xA3, ++ 0x56, 0x35, 0x75, 0x02, 0x75, 0x01, 0x30, 0x75, 0x22, 0x22, 0xC5, 0x31, 0x00, 0x00, 0x00, 0x00, ++ 0xE0, 0x43, 0x07, 0x90, 0xE4, 0x32, 0xE5, 0x30, 0xF0, 0xB3, 0x01, 0x90, 0x27, 0xA9, 0x26, 0xAA, ++ 0x74, 0x3B, 0x03, 0x12, 0x2A, 0x27, 0xB5, 0x60, 0x26, 0xB5, 0x02, 0x74, 0x01, 0x24, 0x75, 0x25, ++ 0x7E, 0xBB, 0x25, 0x75, 0x8E, 0x51, 0x7F, 0x02, 0x8E, 0x27, 0x8F, 0x26, 0xE4, 0x29, 0x8F, 0x28, ++ 0x01, 0x90, 0x2E, 0xF5, 0xF0, 0xFE, 0x74, 0xB3, 0x60, 0x2E, 0xE5, 0x22, 0x26, 0xF5, 0xE4, 0x05, ++ 0x00, 0x22, 0x27, 0xF5, 0x00, 0x00, 0x00, 0xFF, 0xA2, 0x00, 0xAC, 0x00, 0x55, 0x4C, 0x99, 0x01, ++ 0x00, 0x00, 0x00, 0x00, 0x03, 0x12, 0x32, 0x7F, 0x11, 0xE8, 0xD2, 0xE2, 0x62, 0x07, 0x90, 0xC0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x04, 0x44, 0xE0, 0xF0, 0x08, 0x44, 0xE0, 0xF0, 0xFE, 0x54, 0xE0, ++ 0xF0, 0xFB, 0x54, 0xE0, 0xF0, 0xF7, 0x54, 0xE0, 0x00, 0x7F, 0x0D, 0x7E, 0x0D, 0x7E, 0xA3, 0x31, ++ 0xA3, 0x31, 0x20, 0x7F, 0x74, 0x08, 0x0D, 0x90, 0x90, 0xE0, 0xF0, 0xA9, 0x90, 0xF0, 0x28, 0x0D, ++ 0x54, 0xE0, 0x2A, 0x06, 0x07, 0x90, 0xFF, 0x07, 0xF8, 0x54, 0xE0, 0x93, 0x08, 0x90, 0xF0, 0x4F, ++ 0x80, 0x44, 0xE0, 0x47, 0xBF, 0x54, 0xE0, 0xF0, 0x08, 0x90, 0xE0, 0xF0, 0x08, 0x90, 0xF0, 0xAC, ++ 0xF0, 0x7F, 0x74, 0x4D, 0xB2, 0x08, 0x90, 0xE0, 0x06, 0x08, 0x90, 0xF0, 0x22, 0xF0, 0x6A, 0x74, ++ 0xE0, 0xAB, 0x0D, 0x90, 0x3F, 0x54, 0x13, 0x13, 0x90, 0x27, 0xE0, 0x30, 0xC3, 0xE0, 0x27, 0x06, ++ 0x0D, 0xE0, 0x30, 0x13, 0x01, 0x90, 0x76, 0x31, 0xC2, 0xF0, 0xEF, 0xA4, 0x80, 0x50, 0x7F, 0x10, ++ 0x7F, 0x10, 0xD2, 0x36, 0x90, 0x7A, 0x31, 0x6C, 0xF0, 0xEF, 0xA4, 0x01, 0x6C, 0x7F, 0x10, 0xC2, ++ 0x06, 0x90, 0x25, 0x80, 0x13, 0xC3, 0xE0, 0x27, 0x31, 0x0D, 0xE0, 0x30, 0xA4, 0x01, 0x90, 0x76, ++ 0x10, 0xC2, 0xF0, 0xEF, 0x0F, 0x80, 0x50, 0x7F, 0x68, 0x7F, 0x10, 0xD2, 0x01, 0x90, 0x7A, 0x31, ++ 0xC2, 0xF0, 0xEF, 0xA4, 0x31, 0x68, 0x7F, 0x10, 0xA5, 0x01, 0x90, 0x7A, 0x01, 0x90, 0xF0, 0xEF, ++ 0x01, 0x90, 0xE0, 0xA4, 0x01, 0x90, 0xF0, 0xA2, 0x01, 0x90, 0xE0, 0xA5, 0x0D, 0x90, 0xF0, 0xA3, ++ 0x13, 0x13, 0xE0, 0xAB, 0xE0, 0x30, 0x3F, 0x54, 0x7F, 0x10, 0xD2, 0x11, 0x90, 0x7A, 0x31, 0x6D, ++ 0xF0, 0xEF, 0xA6, 0x01, 0x6D, 0x7F, 0x10, 0xC2, 0x10, 0xD2, 0x0F, 0x80, 0x7A, 0x31, 0x6B, 0x7F, ++ 0xEF, 0xA6, 0x01, 0x90, 0x7F, 0x10, 0xC2, 0xF0, 0x90, 0x7A, 0x31, 0x6B, 0xF0, 0xEF, 0xA7, 0x01, ++ 0xE0, 0xA5, 0x01, 0x90, 0x90, 0xF0, 0x04, 0xF4, 0xF4, 0xE0, 0xA3, 0x01, 0x01, 0x90, 0xF0, 0x04, ++ 0x04, 0xF4, 0xE0, 0xA7, 0x10, 0xD2, 0x22, 0xF0, 0x06, 0x90, 0x50, 0x7F, 0x0F, 0x54, 0xE0, 0x26, ++ 0x80, 0x64, 0xD3, 0xFE, 0x04, 0x40, 0x87, 0x94, 0xFE, 0x2E, 0xF0, 0x74, 0x30, 0xFF, 0x2F, 0xEE, ++ 0x04, 0xF4, 0x03, 0x10, 0x26, 0x06, 0x90, 0xFF, 0x0F, 0x54, 0xC4, 0xE0, 0x7F, 0x03, 0xE0, 0x30, ++ 0xE4, 0x22, 0x22, 0x00, 0x20, 0x90, 0xED, 0xFD, 0x0F, 0xFC, 0x93, 0x43, 0x70, 0x06, 0xAA, 0xEF, ++ 0xF5, 0x14, 0x0E, 0x01, 0xEC, 0x83, 0x8A, 0x82, 0x11, 0xBD, 0x0D, 0xF0, 0x00, 0x22, 0x22, 0xE8, ++ 0xE0, 0x44, 0x07, 0x90, 0xE4, 0x32, 0xE5, 0x30, 0xF0, 0xB4, 0x01, 0x90, 0x33, 0xA9, 0x32, 0xAA, ++ 0x74, 0x3B, 0x03, 0x12, 0x2A, 0x33, 0xB5, 0x65, 0x32, 0xB5, 0x02, 0x74, 0x01, 0x30, 0x75, 0x25, ++ 0x7E, 0xC5, 0x31, 0x75, 0x8E, 0x56, 0x7F, 0x02, 0x8E, 0x33, 0x8F, 0x32, 0xE4, 0x35, 0x8F, 0x34, ++ 0x01, 0x90, 0x3A, 0xF5, 0xF0, 0xFE, 0x74, 0xB4, 0x60, 0x3A, 0xE5, 0x22, 0x32, 0xF5, 0xE4, 0x05, ++ 0x00, 0x22, 0x33, 0xF5, 0x00, 0x00, 0x00, 0xFF, 0xA2, 0x00, 0xAC, 0x00, 0x55, 0x4C, 0x99, 0x01, ++ 0x00, 0x00, 0x00, 0x00, 0x03, 0x12, 0x32, 0x7F, 0x11, 0xE8, 0xD2, 0xED, 0x62, 0x07, 0x90, 0xC0, ++ 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0x10, 0x44, 0xE0, 0xF0, 0x20, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, ++ 0xF0, 0xEF, 0x54, 0xE0, 0xF0, 0xDF, 0x54, 0xE0, 0x40, 0x7F, 0x0D, 0x7E, 0x0D, 0x7E, 0xA3, 0x31, ++ 0xA3, 0x31, 0x60, 0x7F, 0x74, 0x48, 0x0D, 0x90, 0x90, 0xE0, 0xF0, 0xA9, 0x90, 0xF0, 0x68, 0x0D, ++ 0x54, 0xE0, 0x6A, 0x06, 0x07, 0x90, 0xFF, 0x07, 0xF8, 0x54, 0xE0, 0xDD, 0x09, 0x90, 0xF0, 0x4F, ++ 0x80, 0x44, 0xE0, 0x76, 0xBF, 0x54, 0xE0, 0xF0, 0x09, 0x90, 0xE0, 0xF0, 0x09, 0x90, 0xF0, 0x11, ++ 0xF0, 0x7F, 0x74, 0x7C, 0x17, 0x09, 0x90, 0xE0, 0x06, 0x08, 0x90, 0xF0, 0x22, 0xF0, 0x6A, 0x74, ++ 0xE0, 0xAB, 0x0D, 0x90, 0x3F, 0x54, 0x13, 0x13, 0x90, 0x27, 0xE0, 0x30, 0xC3, 0xE0, 0x67, 0x06, ++ 0x0D, 0xE0, 0x30, 0x13, 0x01, 0x90, 0x76, 0x31, 0xC2, 0xF0, 0xEF, 0xAA, 0x80, 0x50, 0x7F, 0x10, ++ 0x7F, 0x10, 0xD2, 0x36, 0x90, 0x7A, 0x31, 0x6C, 0xF0, 0xEF, 0xAA, 0x01, 0x6C, 0x7F, 0x10, 0xC2, ++ 0x06, 0x90, 0x25, 0x80, 0x13, 0xC3, 0xE0, 0x67, 0x31, 0x0D, 0xE0, 0x30, 0xAA, 0x01, 0x90, 0x76, ++ 0x10, 0xC2, 0xF0, 0xEF, 0x0F, 0x80, 0x50, 0x7F, 0x68, 0x7F, 0x10, 0xD2, 0x01, 0x90, 0x7A, 0x31, ++ 0xC2, 0xF0, 0xEF, 0xAA, 0x31, 0x68, 0x7F, 0x10, 0xAB, 0x01, 0x90, 0x7A, 0x01, 0x90, 0xF0, 0xEF, ++ 0x01, 0x90, 0xE0, 0xAA, 0x01, 0x90, 0xF0, 0xA8, 0x01, 0x90, 0xE0, 0xAB, 0x0D, 0x90, 0xF0, 0xA9, ++ 0x13, 0x13, 0xE0, 0xAB, 0xE0, 0x30, 0x3F, 0x54, 0x7F, 0x10, 0xD2, 0x11, 0x90, 0x7A, 0x31, 0x6D, ++ 0xF0, 0xEF, 0xAC, 0x01, 0x6D, 0x7F, 0x10, 0xC2, 0x10, 0xD2, 0x0F, 0x80, 0x7A, 0x31, 0x6B, 0x7F, ++ 0xEF, 0xAC, 0x01, 0x90, 0x7F, 0x10, 0xC2, 0xF0, 0x90, 0x7A, 0x31, 0x6B, 0xF0, 0xEF, 0xAD, 0x01, ++ 0xE0, 0xAB, 0x01, 0x90, 0x90, 0xF0, 0x04, 0xF4, 0xF4, 0xE0, 0xA9, 0x01, 0x01, 0x90, 0xF0, 0x04, ++ 0x04, 0xF4, 0xE0, 0xAD, 0x10, 0xD2, 0x22, 0xF0, 0x06, 0x90, 0x50, 0x7F, 0x0F, 0x54, 0xE0, 0x66, ++ 0x80, 0x64, 0xD3, 0xFE, 0x04, 0x40, 0x87, 0x94, 0xFE, 0x2E, 0xF0, 0x74, 0x30, 0xFF, 0x2F, 0xEE, ++ 0x04, 0xF4, 0x03, 0x10, 0x66, 0x06, 0x90, 0xFF, 0x0F, 0x54, 0xC4, 0xE0, 0x7F, 0x03, 0xE0, 0x30, ++ 0xE4, 0x22, 0x22, 0x00, 0x20, 0x90, 0xED, 0xFD, 0x0F, 0xFC, 0x93, 0x43, 0x70, 0x06, 0xAA, 0xEF, ++ 0xF5, 0x14, 0x0E, 0x01, 0xEC, 0x83, 0x8A, 0x82, 0x11, 0xBD, 0x0D, 0xF0, 0x00, 0x22, 0x22, 0xE8, ++ 0xE0, 0x43, 0x07, 0x90, 0xE4, 0x0C, 0xE5, 0x30, 0xF0, 0xB3, 0x01, 0x90, 0x27, 0xA9, 0x26, 0xAA, ++ 0xE5, 0x3B, 0x03, 0x02, 0xE4, 0x05, 0x60, 0x2E, 0x27, 0xF5, 0x26, 0xF5, 0x3A, 0x30, 0x50, 0x22, ++ 0x42, 0x30, 0x31, 0x09, 0x50, 0x00, 0x0A, 0x54, 0x53, 0x09, 0x3A, 0x30, 0x70, 0x75, 0x74, 0x65, ++ 0x30, 0x50, 0x00, 0x0A, 0x69, 0x4C, 0x09, 0x3A, 0x55, 0x2D, 0x6B, 0x6E, 0x50, 0x00, 0x0A, 0x70, ++ 0x09, 0x09, 0x3A, 0x30, 0x6B, 0x6E, 0x69, 0x4C, 0x73, 0x6F, 0x4C, 0x2D, 0x50, 0x00, 0x0A, 0x73, ++ 0x4C, 0x09, 0x3A, 0x30, 0x2D, 0x6B, 0x6E, 0x69, 0x6E, 0x77, 0x6F, 0x44, 0x30, 0x50, 0x00, 0x0A, ++ 0x4D, 0x09, 0x09, 0x3A, 0x58, 0x00, 0x49, 0x44, 0x50, 0x00, 0x0A, 0x00, 0x45, 0x09, 0x3A, 0x30, ++ 0x0A, 0x74, 0x69, 0x78, 0x60, 0x2E, 0xE5, 0x00, 0x7F, 0x20, 0x7E, 0x10, 0x1B, 0x10, 0x12, 0x1D, ++ 0x75, 0x20, 0x2C, 0x75, 0x2F, 0x75, 0xEE, 0x2D, 0x12, 0x10, 0xC2, 0x01, 0x1E, 0x50, 0x4F, 0x11, ++ 0xA9, 0x7F, 0x27, 0x7E, 0x70, 0x2B, 0x65, 0xEF, 0x2A, 0x65, 0xEE, 0x03, 0xBE, 0x74, 0x10, 0x60, ++ 0x04, 0x70, 0x2B, 0x65, 0x2A, 0x65, 0x27, 0x74, 0x2C, 0x8E, 0x04, 0x60, 0x2B, 0xE5, 0x2D, 0x8F, ++ 0x04, 0x70, 0x2D, 0x65, 0x2C, 0x65, 0x2A, 0xE5, 0x2C, 0x85, 0x09, 0x60, 0x2B, 0x2D, 0x85, 0x2A, ++ 0xAA, 0x01, 0x2F, 0x75, 0x12, 0x2B, 0xA9, 0x2A, 0xF5, 0xE4, 0x3B, 0x03, 0xE6, 0x88, 0x78, 0x2F, ++ 0xC3, 0xFF, 0x01, 0x54, 0x08, 0x74, 0x9F, 0xE4, 0x05, 0x54, 0x00, 0x94, 0xC3, 0xE6, 0x18, 0xFC, ++ 0xE6, 0x08, 0xFE, 0x13, 0x6C, 0xEE, 0xFF, 0x13, 0x08, 0xEF, 0xF6, 0x18, 0x20, 0x7E, 0x22, 0xF6, ++ 0x10, 0x12, 0x27, 0x7F, 0xE4, 0x5F, 0x71, 0x1B, 0xE2, 0x03, 0x12, 0xFF, 0x31, 0x23, 0x06, 0x90, ++ 0xAA, 0x0D, 0x90, 0x48, 0x0F, 0x54, 0xC4, 0xE0, 0xAB, 0x0D, 0x90, 0xFF, 0x0F, 0x54, 0xC4, 0xE0, ++ 0x33, 0xE4, 0xFF, 0x2F, 0xFD, 0x00, 0x24, 0xCF, 0xFC, 0x04, 0x34, 0xEF, 0xE0, 0x0B, 0x07, 0x90, ++ 0xA4, 0x20, 0xF0, 0x75, 0xF0, 0x45, 0xEC, 0xFF, 0xED, 0xF6, 0x87, 0x78, 0xE4, 0xF6, 0x08, 0x4F, ++ 0x08, 0xF6, 0x81, 0x78, 0xAA, 0x76, 0x08, 0xF6, 0x90, 0xE6, 0x76, 0x08, 0x0D, 0x74, 0xFB, 0x07, ++ 0x22, 0x2C, 0x75, 0xF0, 0x22, 0x5A, 0x2D, 0x75, 0x13, 0x13, 0xFF, 0xE0, 0x92, 0x13, 0x3F, 0x54, ++ 0x27, 0x06, 0x90, 0x10, 0x03, 0xE0, 0x30, 0xE0, 0x90, 0x1A, 0x10, 0x30, 0x20, 0xE0, 0x27, 0x06, ++ 0x06, 0x90, 0x7A, 0xE0, 0xA3, 0xFE, 0xE0, 0x26, 0xCE, 0x02, 0x78, 0xE0, 0x13, 0xCE, 0x13, 0xC3, ++ 0xE0, 0x20, 0xF9, 0xD8, 0x90, 0x10, 0xC2, 0x67, 0x0F, 0x74, 0x01, 0x0D, 0x21, 0x0D, 0x90, 0xF0, ++ 0x0D, 0x90, 0xF0, 0x04, 0x9F, 0x54, 0xE0, 0x00, 0x0D, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x21, 0x74, ++ 0x45, 0x74, 0x0E, 0x0D, 0x0F, 0x0D, 0x90, 0xF0, 0xE4, 0xF0, 0x04, 0x74, 0xF0, 0x2D, 0x0D, 0x90, ++ 0xF0, 0x2E, 0x0D, 0x90, 0xF0, 0x2F, 0x0D, 0x90, 0xE0, 0x20, 0x0D, 0x90, 0x20, 0x44, 0x9F, 0x54, ++ 0x0C, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x36, 0x74, 0x12, 0x74, 0x2C, 0x0D, 0xF9, 0x07, 0x90, 0xF0, ++ 0xF0, 0xFC, 0x54, 0xE0, 0x44, 0xF3, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x04, 0xFC, 0x54, 0xE0, 0xFA, ++ 0xE0, 0xF0, 0x01, 0x44, 0x90, 0xF0, 0xF3, 0x54, 0x65, 0x80, 0xA4, 0x01, 0x0D, 0x90, 0x10, 0xD2, ++ 0xF0, 0x0F, 0x74, 0x21, 0x04, 0x01, 0x0D, 0x90, 0x00, 0x0D, 0x90, 0xF0, 0x44, 0x9F, 0x54, 0xE0, ++ 0x0D, 0x90, 0xF0, 0x20, 0x9F, 0x54, 0xE0, 0x20, 0x0D, 0x90, 0xE4, 0xF0, 0x0D, 0x90, 0xF0, 0x0D, ++ 0x0D, 0x90, 0xF0, 0x0E, 0x0D, 0x90, 0xF0, 0x0F, 0xF0, 0x21, 0x74, 0x2D, 0x74, 0x2E, 0x0D, 0x90, ++ 0x0D, 0x90, 0xF0, 0x45, 0xF0, 0x04, 0x74, 0x2F, 0x74, 0x0C, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x12, ++ 0xF0, 0x36, 0x74, 0x2C, 0xE0, 0xF9, 0x07, 0x90, 0x01, 0x44, 0xFC, 0x54, 0xF3, 0x54, 0xE0, 0xF0, ++ 0xFA, 0x07, 0x90, 0xF0, 0xF0, 0xFC, 0x54, 0xE0, 0x44, 0xF3, 0x54, 0xE0, 0x01, 0x90, 0xF0, 0x04, ++ 0x08, 0x90, 0xE0, 0xA5, 0x10, 0xA2, 0xF0, 0x45, 0x01, 0x54, 0x33, 0xE4, 0xE0, 0x25, 0xE0, 0x25, ++ 0x23, 0x06, 0x90, 0xFF, 0x4F, 0xFB, 0x54, 0xE0, 0x2F, 0xE5, 0x22, 0xF0, 0x20, 0x7E, 0x23, 0x60, ++ 0x10, 0x12, 0x4F, 0x7F, 0x76, 0x85, 0x78, 0x1B, 0x24, 0x76, 0x08, 0xF4, 0xE0, 0x95, 0x07, 0x90, ++ 0x90, 0xF0, 0x01, 0x44, 0x44, 0xE0, 0x99, 0x07, 0x07, 0x90, 0xF0, 0x01, 0x02, 0x44, 0xE0, 0x91, ++ 0x00, 0x06, 0x90, 0xF0, 0x0F, 0x54, 0xC4, 0xE0, 0xD3, 0x1B, 0xE0, 0x30, 0x94, 0xE6, 0x84, 0x78, ++ 0x94, 0xE6, 0x18, 0x00, 0x08, 0x09, 0x40, 0x00, 0x70, 0x18, 0x16, 0xE6, 0x06, 0x80, 0x16, 0x01, ++ 0x75, 0x27, 0x2C, 0x75, 0x07, 0x90, 0xA9, 0x2D, 0x07, 0x54, 0xE0, 0xA6, 0x09, 0x60, 0x01, 0x64, ++ 0xE0, 0x91, 0x07, 0x90, 0xE0, 0x30, 0x13, 0xC3, 0x91, 0x07, 0x90, 0x1E, 0x30, 0x13, 0xC3, 0xE0, ++ 0x81, 0x78, 0x09, 0xE0, 0x76, 0x08, 0x13, 0x76, 0xE4, 0x06, 0x80, 0x88, 0x08, 0xF6, 0x81, 0x78, ++ 0x26, 0x2C, 0x75, 0xF6, 0x90, 0x53, 0x2D, 0x75, 0xC4, 0xE0, 0x00, 0x06, 0xE0, 0x30, 0x0F, 0x54, ++ 0x23, 0x06, 0x90, 0x05, 0x06, 0x90, 0x07, 0x80, 0xE0, 0x20, 0xE0, 0x27, 0x78, 0x48, 0x31, 0x0A, ++ 0x08, 0xF4, 0x76, 0x85, 0xD3, 0x22, 0x24, 0x76, 0x94, 0xE6, 0x86, 0x78, 0x94, 0xE6, 0x18, 0x00, ++ 0x08, 0x08, 0x40, 0x00, 0x70, 0x18, 0x16, 0xE6, 0x78, 0x22, 0x16, 0x01, 0x08, 0xF4, 0x76, 0x85, ++ 0x07, 0x90, 0x24, 0x76, 0x07, 0x54, 0xE0, 0xA6, 0x88, 0x78, 0x44, 0x70, 0xFF, 0x01, 0x54, 0xE6, ++ 0xE0, 0x23, 0x06, 0x90, 0x54, 0x13, 0x13, 0xFD, 0x01, 0x70, 0x6F, 0x01, 0x90, 0x07, 0x60, 0xE4, ++ 0x44, 0xE0, 0x35, 0x06, 0x88, 0x78, 0xF0, 0x08, 0x10, 0x92, 0x13, 0xE6, 0x20, 0x7E, 0x51, 0x31, ++ 0x10, 0x12, 0x5E, 0x7F, 0x23, 0x06, 0x90, 0x1B, 0x54, 0x13, 0x13, 0xE0, 0x07, 0xE0, 0x30, 0x3F, ++ 0x67, 0x7F, 0x20, 0x7E, 0x7E, 0x1B, 0x10, 0x12, 0x12, 0x69, 0x7F, 0x20, 0xE4, 0x22, 0x1B, 0x10, ++ 0xF0, 0x01, 0x0D, 0x90, 0xE0, 0x00, 0x0D, 0x90, 0xE0, 0xF0, 0xF8, 0x54, 0xE0, 0xF0, 0x18, 0x44, ++ 0xF0, 0x20, 0x0D, 0x90, 0x74, 0x0A, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x69, 0x0D, 0x90, 0xF0, 0x2A, ++ 0xF0, 0x7C, 0x74, 0x06, 0xF0, 0x26, 0x0D, 0x90, 0x74, 0xA2, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0xAA, ++ 0xF0, 0x11, 0x74, 0x0C, 0xF0, 0x2C, 0x0D, 0x90, 0x74, 0x02, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x30, ++ 0x0D, 0x90, 0xF0, 0x22, 0xF0, 0x20, 0x74, 0x05, 0xF0, 0x25, 0x0D, 0x90, 0x21, 0x0D, 0x90, 0xE4, ++ 0xF8, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xE0, 0xFD, 0x07, 0x90, ++ 0x90, 0xF0, 0x01, 0x44, 0x54, 0xE0, 0x03, 0x08, 0xF0, 0x01, 0x44, 0xF8, 0xE0, 0xCC, 0x08, 0x90, ++ 0xE0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0x90, 0xF0, 0xFD, 0x54, 0x54, 0xE0, 0x10, 0x07, ++ 0x10, 0xF0, 0x75, 0x0F, 0xFD, 0xAB, 0x24, 0xA4, 0xFC, 0xF0, 0x35, 0xE4, 0xE0, 0x0F, 0x07, 0x90, ++ 0xA4, 0xAA, 0xF0, 0x75, 0xF0, 0xE5, 0xFF, 0x2D, 0xFC, 0x07, 0xAD, 0x3C, 0xCF, 0x08, 0x90, 0xEF, ++ 0x0F, 0x07, 0x90, 0xF0, 0x75, 0x0F, 0x54, 0xE0, 0xFF, 0xA4, 0x10, 0xF0, 0xE0, 0x10, 0x07, 0x90, ++ 0xFB, 0x0F, 0x54, 0xC4, 0xEB, 0xFA, 0xF0, 0xE5, 0x2B, 0xEC, 0xFB, 0x4F, 0xCF, 0x3A, 0xE4, 0xFF, ++ 0xE4, 0xFD, 0xAA, 0x24, 0x05, 0xAF, 0xFC, 0x3F, 0xCE, 0x08, 0x90, 0xED, 0x0F, 0x07, 0x90, 0xF0, ++ 0x0F, 0x54, 0xC4, 0xE0, 0xFF, 0x2B, 0xEC, 0xFB, 0x24, 0xCF, 0x33, 0xE4, 0x05, 0xAF, 0xFD, 0x0A, ++ 0xCD, 0x08, 0x90, 0xED, 0xD0, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x44, 0xE0, 0x60, 0x08, ++ 0x44, 0xE0, 0xF0, 0x01, 0x54, 0xE0, 0xF0, 0x02, 0x90, 0xE4, 0xF0, 0xFD, 0x90, 0xF0, 0x61, 0x08, ++ 0x54, 0xE0, 0x62, 0x08, 0xF0, 0x06, 0x44, 0xF8, 0xE0, 0x63, 0x08, 0x90, 0x90, 0xF0, 0xFA, 0x74, ++ 0x44, 0xE0, 0x67, 0x08, 0x07, 0x90, 0xF0, 0x01, 0x0F, 0x54, 0xE0, 0x10, 0xA4, 0x10, 0xF0, 0x75, ++ 0xE4, 0xFD, 0xAB, 0x24, 0x90, 0xFC, 0xF0, 0x35, 0x75, 0xE0, 0x0F, 0x07, 0x2D, 0xA4, 0xAA, 0xF0, ++ 0x3C, 0xF0, 0xE5, 0xFD, 0xED, 0x05, 0xAF, 0xFC, 0xF0, 0x6A, 0x08, 0x90, 0xE0, 0x0F, 0x07, 0x90, ++ 0xF0, 0x75, 0x0F, 0x54, 0x90, 0xFF, 0xA4, 0x10, 0xC4, 0xE0, 0x10, 0x07, 0xE5, 0xFB, 0x0F, 0x54, ++ 0x4F, 0xEB, 0xFA, 0xF0, 0xFF, 0x2B, 0xEC, 0xFB, 0x24, 0xCF, 0x3A, 0xE4, 0x3F, 0xE4, 0xFD, 0xAA, ++ 0xED, 0x05, 0xAF, 0xFC, 0xF0, 0x69, 0x08, 0x90, 0xE0, 0x0F, 0x07, 0x90, 0xFB, 0x0F, 0x54, 0xC4, ++ 0xE4, 0xFF, 0x2B, 0xEC, 0x0A, 0x24, 0xCF, 0x33, 0xFC, 0x3F, 0xE4, 0xFD, 0x90, 0xED, 0x05, 0xAF, ++ 0x90, 0xF0, 0x68, 0x08, 0x01, 0x74, 0x6B, 0x08, 0x52, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x0B, 0x74, ++ 0x07, 0x74, 0x51, 0x08, 0x52, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x0A, 0x74, 0x06, 0x74, 0x51, 0x08, ++ 0x39, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x54, 0xE0, 0x3A, 0x08, 0x08, 0x90, 0xF0, 0xFE, ++ 0xF0, 0x01, 0x74, 0x40, 0x74, 0x41, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x09, 0xF0, 0x01, 0x74, 0x42, ++ 0xF0, 0x43, 0x08, 0x90, 0xE0, 0x3E, 0x08, 0x90, 0x90, 0xF0, 0x01, 0x44, 0x44, 0xE0, 0x7B, 0x07, ++ 0x07, 0x90, 0xF0, 0x01, 0x01, 0x44, 0xE0, 0x94, 0x95, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, ++ 0xE0, 0x96, 0x07, 0x90, 0x03, 0x44, 0xF8, 0x54, 0x97, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x03, 0x74, ++ 0x54, 0xE0, 0x95, 0x07, 0x07, 0x90, 0xF0, 0xFE, 0x01, 0x44, 0xE0, 0x98, 0x99, 0x07, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x9A, 0x07, 0x90, 0x01, 0x44, 0xF8, 0x54, 0x9B, 0x07, 0x90, 0xF0, ++ 0x90, 0xF0, 0x03, 0x74, 0x54, 0xE0, 0x99, 0x07, 0x06, 0x90, 0xF0, 0xFE, 0xC4, 0xFF, 0xE0, 0x26, ++ 0x24, 0x07, 0x54, 0x13, 0x04, 0x1D, 0x60, 0xFE, 0x07, 0x90, 0x22, 0x70, 0xF0, 0x03, 0x74, 0x7F, ++ 0xE0, 0x9A, 0x07, 0x90, 0x02, 0x44, 0xF8, 0x54, 0x96, 0x07, 0x90, 0xF0, 0x44, 0xF8, 0x54, 0xE0, ++ 0x0D, 0x80, 0xF0, 0x03, 0x74, 0x7F, 0x07, 0x90, 0x05, 0x80, 0xF0, 0x01, 0x7F, 0x07, 0x90, 0xE4, ++ 0x7C, 0x07, 0x90, 0xF0, 0xF0, 0xF8, 0x54, 0xE0, 0xE0, 0x30, 0x06, 0x90, 0x78, 0xE0, 0xA3, 0xFE, ++ 0x13, 0xC3, 0xCE, 0x03, 0xF9, 0xD8, 0x13, 0xCE, 0x33, 0x33, 0x01, 0x54, 0xFF, 0xF8, 0x54, 0x33, ++ 0xE0, 0x7C, 0x07, 0x90, 0xF0, 0x4F, 0xF7, 0x54, 0xE0, 0x2F, 0x06, 0x90, 0x13, 0xC4, 0xC0, 0x54, ++ 0xFF, 0x03, 0x54, 0x13, 0xE0, 0x7D, 0x07, 0x90, 0xF0, 0x4F, 0xFC, 0x54, 0x74, 0x9C, 0x07, 0x90, ++ 0x07, 0x90, 0xF0, 0x03, 0xF0, 0xE4, 0xF0, 0x9D, 0x74, 0x54, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x03, ++ 0xF0, 0x0F, 0x74, 0x55, 0xF0, 0x56, 0x08, 0x90, 0xE0, 0x57, 0x08, 0x90, 0x04, 0x44, 0xE0, 0x54, ++ 0x58, 0x08, 0x90, 0xF0, 0x44, 0xE0, 0x54, 0xE0, 0x08, 0x90, 0xF0, 0x12, 0xE0, 0x54, 0xE0, 0x59, ++ 0x90, 0xF0, 0x17, 0x44, 0x54, 0xE0, 0x5A, 0x08, 0xF0, 0x26, 0x44, 0xC0, 0xE0, 0x5B, 0x08, 0x90, ++ 0x01, 0x44, 0xFC, 0x54, 0x3C, 0x44, 0xE0, 0xF0, 0x5D, 0x08, 0x90, 0xF0, 0xF0, 0x03, 0x44, 0xE0, ++ 0xF0, 0xF3, 0x54, 0xE0, 0xE0, 0x54, 0x08, 0x90, 0x90, 0xF0, 0xFD, 0x54, 0x44, 0xE0, 0x07, 0x07, ++ 0xE5, 0x22, 0xF0, 0x10, 0x7E, 0x4E, 0x60, 0x2F, 0x12, 0x32, 0x7F, 0x20, 0x01, 0x90, 0x1B, 0x10, ++ 0x01, 0x44, 0xE0, 0xAF, 0x03, 0x06, 0x90, 0xF0, 0xF0, 0x04, 0x44, 0xE0, 0x54, 0xE6, 0x7F, 0x78, ++ 0x33, 0xC4, 0xFC, 0x01, 0xE0, 0xFE, 0xE0, 0x54, 0xF0, 0x4E, 0xDF, 0x54, 0xE0, 0x35, 0x06, 0x90, ++ 0xEC, 0xF0, 0x01, 0x44, 0xE0, 0x25, 0xE0, 0x25, 0x34, 0x06, 0x90, 0xFF, 0x4F, 0xFB, 0x54, 0xE0, ++ 0x95, 0x07, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0x99, 0x07, 0x90, 0xE4, 0xF0, 0xFE, 0x54, ++ 0x08, 0xF6, 0x83, 0x78, 0xA6, 0x07, 0x90, 0xF6, 0x13, 0x13, 0x13, 0xE0, 0xE0, 0x30, 0x1F, 0x54, ++ 0x03, 0x06, 0x90, 0x0D, 0xF0, 0x02, 0x44, 0xE0, 0x74, 0xA6, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x08, ++ 0x14, 0x60, 0xE0, 0x97, 0xE0, 0x95, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, 0x03, 0x74, 0x97, 0x07, ++ 0x95, 0x07, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0xAF, 0x01, 0x90, 0x91, 0x07, 0x90, 0xFF, ++ 0x13, 0x13, 0xC4, 0xE0, 0xEF, 0xFE, 0x01, 0x54, 0x01, 0x54, 0x13, 0xC4, 0xDF, 0x54, 0xEF, 0xFD, ++ 0x54, 0x4E, 0xED, 0xFF, 0x54, 0x33, 0xC4, 0x01, 0x01, 0x90, 0x4F, 0xE0, 0xFF, 0xE0, 0xF0, 0xAF, ++ 0xE0, 0x91, 0x07, 0x90, 0x01, 0x54, 0x13, 0xC4, 0x13, 0x13, 0xEF, 0xFE, 0xFD, 0x01, 0x54, 0x13, ++ 0xFF, 0xF7, 0x54, 0xEF, 0x01, 0x54, 0x4E, 0xED, 0x54, 0x33, 0x33, 0x33, 0x01, 0x90, 0x4F, 0xF8, ++ 0xFF, 0xE0, 0xF0, 0xAF, 0xE0, 0x91, 0x07, 0x90, 0x01, 0x54, 0x13, 0xC3, 0x54, 0xC4, 0xEF, 0xFE, ++ 0x54, 0xEF, 0xFD, 0x01, 0x4E, 0xED, 0xFF, 0xEF, 0x54, 0xC4, 0x01, 0x54, 0x01, 0x90, 0x4F, 0xF0, ++ 0x07, 0x90, 0xF0, 0xAF, 0xF0, 0x62, 0x74, 0x91, 0xE0, 0xA6, 0x07, 0x90, 0x01, 0x64, 0x07, 0x54, ++ 0x54, 0xE0, 0x3E, 0x60, 0x60, 0x03, 0x64, 0x07, 0x82, 0x78, 0xD3, 0x37, 0x18, 0x00, 0x94, 0xE6, ++ 0x40, 0x00, 0x94, 0xE6, 0x16, 0xE6, 0x08, 0x08, 0x16, 0x01, 0x70, 0x18, 0x22, 0x2C, 0x75, 0x22, ++ 0x7E, 0x5A, 0x2D, 0x75, 0x12, 0x3F, 0x7F, 0x20, 0x01, 0x90, 0x1B, 0x10, 0xFE, 0x54, 0xE0, 0xAF, ++ 0x03, 0x06, 0x90, 0xF0, 0xF0, 0xFB, 0x54, 0xE0, 0xE0, 0x35, 0x06, 0x90, 0x22, 0xF0, 0x01, 0x44, ++ 0xE0, 0xA6, 0x07, 0x90, 0xBF, 0xFF, 0x07, 0x54, 0x81, 0x78, 0x08, 0x03, 0x76, 0x08, 0x13, 0x76, ++ 0x78, 0xE4, 0x22, 0x88, 0xF6, 0x08, 0xF6, 0x81, 0x99, 0x07, 0x90, 0x22, 0xF0, 0x01, 0x44, 0xE0, ++ 0xE0, 0xA4, 0x07, 0x90, 0x75, 0xF0, 0x04, 0x44, 0x2D, 0x75, 0x27, 0x2C, 0x2F, 0xE5, 0x22, 0xBE, ++ 0x20, 0x7E, 0x07, 0x60, 0x10, 0x12, 0x6B, 0x7F, 0x9D, 0x07, 0x90, 0x1B, 0x90, 0xF0, 0x03, 0x74, ++ 0x54, 0xE0, 0x9C, 0x07, 0x01, 0x90, 0xF0, 0xFE, 0xFE, 0x54, 0xE0, 0xAF, 0x02, 0x06, 0x90, 0xF0, ++ 0xE0, 0xA3, 0xF0, 0xE0, 0xE0, 0xF0, 0xFB, 0x54, 0xE4, 0xF0, 0xDF, 0x54, 0x75, 0xF6, 0x7F, 0x78, ++ 0x29, 0x75, 0x02, 0x28, 0x01, 0x24, 0x75, 0x51, 0x22, 0xBB, 0x25, 0x75, 0x00, 0x00, 0x00, 0x22, ++ 0xE0, 0x44, 0x07, 0x90, 0xE4, 0x0C, 0xE5, 0x30, 0xF0, 0xB4, 0x01, 0x90, 0x33, 0xA9, 0x32, 0xAA, ++ 0xE5, 0x3B, 0x03, 0x02, 0xE4, 0x05, 0x60, 0x3A, 0x33, 0xF5, 0x32, 0xF5, 0x3A, 0x31, 0x50, 0x22, ++ 0x42, 0x30, 0x31, 0x09, 0x50, 0x00, 0x0A, 0x54, 0x53, 0x09, 0x3A, 0x31, 0x70, 0x75, 0x74, 0x65, ++ 0x31, 0x50, 0x00, 0x0A, 0x69, 0x4C, 0x09, 0x3A, 0x55, 0x2D, 0x6B, 0x6E, 0x50, 0x00, 0x0A, 0x70, ++ 0x09, 0x09, 0x3A, 0x31, 0x6B, 0x6E, 0x69, 0x4C, 0x73, 0x6F, 0x4C, 0x2D, 0x50, 0x00, 0x0A, 0x73, ++ 0x4C, 0x09, 0x3A, 0x31, 0x2D, 0x6B, 0x6E, 0x69, 0x6E, 0x77, 0x6F, 0x44, 0x31, 0x50, 0x00, 0x0A, ++ 0x4D, 0x09, 0x09, 0x3A, 0x58, 0x00, 0x49, 0x44, 0x50, 0x00, 0x0A, 0x00, 0x45, 0x09, 0x3A, 0x31, ++ 0x0A, 0x74, 0x69, 0x78, 0x60, 0x3A, 0xE5, 0x00, 0x7F, 0x20, 0x7E, 0x10, 0x1B, 0x10, 0x12, 0x1D, ++ 0x75, 0x20, 0x38, 0x75, 0x3B, 0x75, 0xEE, 0x39, 0x12, 0x10, 0xD2, 0x01, 0x1E, 0x50, 0x4F, 0x11, ++ 0xA9, 0x7F, 0x27, 0x7E, 0x70, 0x37, 0x65, 0xEF, 0x36, 0x65, 0xEE, 0x03, 0xBE, 0x74, 0x10, 0x60, ++ 0x04, 0x70, 0x37, 0x65, 0x36, 0x65, 0x27, 0x74, 0x38, 0x8E, 0x04, 0x60, 0x37, 0xE5, 0x39, 0x8F, ++ 0x04, 0x70, 0x39, 0x65, 0x38, 0x65, 0x36, 0xE5, 0x38, 0x85, 0x09, 0x60, 0x37, 0x39, 0x85, 0x36, ++ 0xAA, 0x01, 0x3B, 0x75, 0x12, 0x37, 0xA9, 0x36, 0xF5, 0xE4, 0x3B, 0x03, 0xE6, 0xA9, 0x78, 0x3B, ++ 0xC3, 0xFF, 0x01, 0x54, 0x08, 0x74, 0x9F, 0xE4, 0x05, 0x54, 0x00, 0x94, 0xC3, 0xE6, 0x18, 0xFC, ++ 0xE6, 0x08, 0xFE, 0x13, 0x6C, 0xEE, 0xFF, 0x13, 0x08, 0xEF, 0xF6, 0x18, 0x20, 0x7E, 0x22, 0xF6, ++ 0x10, 0x12, 0x27, 0x7F, 0xE4, 0x5F, 0x71, 0x1B, 0xED, 0x03, 0x12, 0xFF, 0x31, 0x63, 0x06, 0x90, ++ 0xAA, 0x0D, 0x90, 0x48, 0x0F, 0x54, 0xC4, 0xE0, 0xAB, 0x0D, 0x90, 0xFF, 0x0F, 0x54, 0xC4, 0xE0, ++ 0x33, 0xE4, 0xFF, 0x2F, 0xFD, 0x00, 0x24, 0xCF, 0xFC, 0x04, 0x34, 0xEF, 0xE0, 0x0C, 0x07, 0x90, ++ 0xA4, 0x20, 0xF0, 0x75, 0xF0, 0x45, 0xEC, 0xFF, 0xED, 0xF6, 0xA8, 0x78, 0xE4, 0xF6, 0x08, 0x4F, ++ 0x08, 0xF6, 0xA2, 0x78, 0xAA, 0x76, 0x08, 0xF6, 0x90, 0xE6, 0x76, 0x08, 0x0D, 0x74, 0xFB, 0x07, ++ 0x22, 0x38, 0x75, 0xF0, 0x22, 0x5A, 0x39, 0x75, 0x13, 0x13, 0xFF, 0xE0, 0x92, 0x13, 0x3F, 0x54, ++ 0x67, 0x06, 0x90, 0x10, 0x03, 0xE0, 0x30, 0xE0, 0x90, 0x1A, 0x10, 0x30, 0x20, 0xE0, 0x67, 0x06, ++ 0x06, 0x90, 0x7A, 0xE0, 0xA3, 0xFE, 0xE0, 0x66, 0xCE, 0x02, 0x78, 0xE0, 0x13, 0xCE, 0x13, 0xC3, ++ 0xE0, 0x20, 0xF9, 0xD8, 0x90, 0x10, 0xC2, 0x67, 0x0F, 0x74, 0x41, 0x0D, 0x61, 0x0D, 0x90, 0xF0, ++ 0x0D, 0x90, 0xF0, 0x04, 0x9F, 0x54, 0xE0, 0x40, 0x4D, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x21, 0x74, ++ 0x45, 0x74, 0x4E, 0x0D, 0x4F, 0x0D, 0x90, 0xF0, 0xE4, 0xF0, 0x04, 0x74, 0xF0, 0x6D, 0x0D, 0x90, ++ 0xF0, 0x6E, 0x0D, 0x90, 0xF0, 0x6F, 0x0D, 0x90, 0xE0, 0x60, 0x0D, 0x90, 0x20, 0x44, 0x9F, 0x54, ++ 0x4C, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x36, 0x74, 0x12, 0x74, 0x6C, 0x0D, 0xF9, 0x07, 0x90, 0xF0, ++ 0xF0, 0x30, 0x44, 0xE0, 0x44, 0x3F, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x80, 0xCF, 0x54, 0xE0, 0xFA, ++ 0xE0, 0xF0, 0x20, 0x44, 0x90, 0xF0, 0xC0, 0x44, 0x65, 0x80, 0xAA, 0x01, 0x0D, 0x90, 0x10, 0xD2, ++ 0xF0, 0x0F, 0x74, 0x61, 0x04, 0x41, 0x0D, 0x90, 0x40, 0x0D, 0x90, 0xF0, 0x44, 0x9F, 0x54, 0xE0, ++ 0x0D, 0x90, 0xF0, 0x20, 0x9F, 0x54, 0xE0, 0x60, 0x0D, 0x90, 0xE4, 0xF0, 0x0D, 0x90, 0xF0, 0x4D, ++ 0x0D, 0x90, 0xF0, 0x4E, 0x0D, 0x90, 0xF0, 0x4F, 0xF0, 0x21, 0x74, 0x6D, 0x74, 0x6E, 0x0D, 0x90, ++ 0x0D, 0x90, 0xF0, 0x45, 0xF0, 0x04, 0x74, 0x6F, 0x74, 0x4C, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x12, ++ 0xF0, 0x36, 0x74, 0x6C, 0xE0, 0xF9, 0x07, 0x90, 0x20, 0x44, 0xCF, 0x54, 0xC0, 0x44, 0xE0, 0xF0, ++ 0xFA, 0x07, 0x90, 0xF0, 0xF0, 0x30, 0x44, 0xE0, 0x44, 0x3F, 0x54, 0xE0, 0x01, 0x90, 0xF0, 0x80, ++ 0x09, 0x90, 0xE0, 0xAB, 0x10, 0xA2, 0xF0, 0x74, 0x01, 0x54, 0x33, 0xE4, 0xE0, 0x25, 0xE0, 0x25, ++ 0x63, 0x06, 0x90, 0xFF, 0x4F, 0xFB, 0x54, 0xE0, 0x3B, 0xE5, 0x22, 0xF0, 0x20, 0x7E, 0x23, 0x60, ++ 0x10, 0x12, 0x4F, 0x7F, 0x76, 0xA6, 0x78, 0x1B, 0x24, 0x76, 0x08, 0xF4, 0xE0, 0xDF, 0x07, 0x90, ++ 0x90, 0xF0, 0x01, 0x44, 0x44, 0xE0, 0xE3, 0x07, 0x07, 0x90, 0xF0, 0x01, 0x02, 0x44, 0xE0, 0xDB, ++ 0x40, 0x06, 0x90, 0xF0, 0x0F, 0x54, 0xC4, 0xE0, 0xD3, 0x1B, 0xE0, 0x30, 0x94, 0xE6, 0xA5, 0x78, ++ 0x94, 0xE6, 0x18, 0x00, 0x08, 0x09, 0x40, 0x00, 0x70, 0x18, 0x16, 0xE6, 0x06, 0x80, 0x16, 0x01, ++ 0x75, 0x27, 0x38, 0x75, 0x07, 0x90, 0xA9, 0x39, 0x07, 0x54, 0xE0, 0xF0, 0x09, 0x60, 0x01, 0x64, ++ 0xE0, 0xDB, 0x07, 0x90, 0xE0, 0x30, 0x13, 0xC3, 0xDB, 0x07, 0x90, 0x1E, 0x30, 0x13, 0xC3, 0xE0, ++ 0xA2, 0x78, 0x09, 0xE0, 0x76, 0x08, 0x13, 0x76, 0xE4, 0x06, 0x80, 0x88, 0x08, 0xF6, 0xA2, 0x78, ++ 0x26, 0x38, 0x75, 0xF6, 0x90, 0x53, 0x39, 0x75, 0xC4, 0xE0, 0x40, 0x06, 0xE0, 0x30, 0x0F, 0x54, ++ 0x63, 0x06, 0x90, 0x05, 0x06, 0x90, 0x07, 0x80, 0xE0, 0x20, 0xE0, 0x67, 0x78, 0x48, 0x31, 0x0A, ++ 0x08, 0xF4, 0x76, 0xA6, 0xD3, 0x22, 0x24, 0x76, 0x94, 0xE6, 0xA7, 0x78, 0x94, 0xE6, 0x18, 0x00, ++ 0x08, 0x08, 0x40, 0x00, 0x70, 0x18, 0x16, 0xE6, 0x78, 0x22, 0x16, 0x01, 0x08, 0xF4, 0x76, 0xA6, ++ 0x07, 0x90, 0x24, 0x76, 0x07, 0x54, 0xE0, 0xF0, 0xA9, 0x78, 0x44, 0x70, 0xFF, 0x01, 0x54, 0xE6, ++ 0xE0, 0x63, 0x06, 0x90, 0x54, 0x13, 0x13, 0xFD, 0x01, 0x70, 0x6F, 0x01, 0x90, 0x07, 0x60, 0xE4, ++ 0x44, 0xE0, 0x75, 0x06, 0xA9, 0x78, 0xF0, 0x08, 0x10, 0x92, 0x13, 0xE6, 0x20, 0x7E, 0x51, 0x31, ++ 0x10, 0x12, 0x5E, 0x7F, 0x63, 0x06, 0x90, 0x1B, 0x54, 0x13, 0x13, 0xE0, 0x07, 0xE0, 0x30, 0x3F, ++ 0x67, 0x7F, 0x20, 0x7E, 0x7E, 0x1B, 0x10, 0x12, 0x12, 0x69, 0x7F, 0x20, 0xE4, 0x22, 0x1B, 0x10, ++ 0xF0, 0x41, 0x0D, 0x90, 0xE0, 0x40, 0x0D, 0x90, 0xE0, 0xF0, 0xF8, 0x54, 0xE0, 0xF0, 0x18, 0x44, ++ 0xF0, 0x60, 0x0D, 0x90, 0x74, 0x4A, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x69, 0x0D, 0x90, 0xF0, 0x6A, ++ 0xF0, 0x7C, 0x74, 0x46, 0xF0, 0x66, 0x0D, 0x90, 0x74, 0xA2, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0xAA, ++ 0xF0, 0x11, 0x74, 0x4C, 0xF0, 0x6C, 0x0D, 0x90, 0x74, 0x42, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x30, ++ 0x0D, 0x90, 0xF0, 0x62, 0xF0, 0x20, 0x74, 0x45, 0xF0, 0x65, 0x0D, 0x90, 0x61, 0x0D, 0x90, 0xE4, ++ 0xF8, 0x07, 0x90, 0xF0, 0xF0, 0x08, 0x44, 0xE0, 0xF0, 0xFB, 0x54, 0xE0, 0xE0, 0xFD, 0x07, 0x90, ++ 0x90, 0xF0, 0x01, 0x44, 0x54, 0xE0, 0x04, 0x08, 0xF0, 0x20, 0x44, 0x8F, 0xE0, 0x31, 0x09, 0x90, ++ 0xE0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0x90, 0xF0, 0xFD, 0x54, 0x54, 0xE0, 0x10, 0x07, ++ 0x10, 0xF0, 0x75, 0x0F, 0xFD, 0xAB, 0x24, 0xA4, 0xFC, 0xF0, 0x35, 0xE4, 0xE0, 0x0F, 0x07, 0x90, ++ 0xA4, 0xAA, 0xF0, 0x75, 0xF0, 0xE5, 0xFF, 0x2D, 0xFC, 0x07, 0xAD, 0x3C, 0x34, 0x09, 0x90, 0xEF, ++ 0x0F, 0x07, 0x90, 0xF0, 0x75, 0x0F, 0x54, 0xE0, 0xFF, 0xA4, 0x10, 0xF0, 0xE0, 0x10, 0x07, 0x90, ++ 0xFB, 0x0F, 0x54, 0xC4, 0xEB, 0xFA, 0xF0, 0xE5, 0x2B, 0xEC, 0xFB, 0x4F, 0xCF, 0x3A, 0xE4, 0xFF, ++ 0xE4, 0xFD, 0xAA, 0x24, 0x05, 0xAF, 0xFC, 0x3F, 0x33, 0x09, 0x90, 0xED, 0x0F, 0x07, 0x90, 0xF0, ++ 0x0F, 0x54, 0xC4, 0xE0, 0xFF, 0x2B, 0xEC, 0xFB, 0x24, 0xCF, 0x33, 0xE4, 0x05, 0xAF, 0xFD, 0x0A, ++ 0x32, 0x09, 0x90, 0xED, 0x35, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x44, 0xE0, 0x8F, 0x09, ++ 0x44, 0xE0, 0xF0, 0x01, 0x54, 0xE0, 0xF0, 0x02, 0x90, 0xE4, 0xF0, 0xFD, 0x90, 0xF0, 0x90, 0x09, ++ 0x54, 0xE0, 0x91, 0x09, 0xF0, 0x06, 0x44, 0xF8, 0xE0, 0x92, 0x09, 0x90, 0x90, 0xF0, 0xFA, 0x74, ++ 0x44, 0xE0, 0x96, 0x09, 0x07, 0x90, 0xF0, 0x01, 0x0F, 0x54, 0xE0, 0x10, 0xA4, 0x10, 0xF0, 0x75, ++ 0xE4, 0xFD, 0xAB, 0x24, 0x90, 0xFC, 0xF0, 0x35, 0x75, 0xE0, 0x0F, 0x07, 0x2D, 0xA4, 0xAA, 0xF0, ++ 0x3C, 0xF0, 0xE5, 0xFD, 0xED, 0x05, 0xAF, 0xFC, 0xF0, 0x99, 0x09, 0x90, 0xE0, 0x0F, 0x07, 0x90, ++ 0xF0, 0x75, 0x0F, 0x54, 0x90, 0xFF, 0xA4, 0x10, 0xC4, 0xE0, 0x10, 0x07, 0xE5, 0xFB, 0x0F, 0x54, ++ 0x4F, 0xEB, 0xFA, 0xF0, 0xFF, 0x2B, 0xEC, 0xFB, 0x24, 0xCF, 0x3A, 0xE4, 0x3F, 0xE4, 0xFD, 0xAA, ++ 0xED, 0x05, 0xAF, 0xFC, 0xF0, 0x98, 0x09, 0x90, 0xE0, 0x0F, 0x07, 0x90, 0xFB, 0x0F, 0x54, 0xC4, ++ 0xE4, 0xFF, 0x2B, 0xEC, 0x0A, 0x24, 0xCF, 0x33, 0xFC, 0x3F, 0xE4, 0xFD, 0x90, 0xED, 0x05, 0xAF, ++ 0x90, 0xF0, 0x97, 0x09, 0x01, 0x74, 0x9A, 0x09, 0x81, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x0B, 0x74, ++ 0x07, 0x74, 0x80, 0x09, 0x81, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x0A, 0x74, 0x06, 0x74, 0x80, 0x09, ++ 0x68, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x54, 0xE0, 0x69, 0x09, 0x09, 0x90, 0xF0, 0xFE, ++ 0xF0, 0x01, 0x74, 0x6F, 0x74, 0x70, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x09, 0xF0, 0x01, 0x74, 0x71, ++ 0xF0, 0x72, 0x09, 0x90, 0xE0, 0x6D, 0x09, 0x90, 0x90, 0xF0, 0x01, 0x44, 0x44, 0xE0, 0xC5, 0x07, ++ 0x07, 0x90, 0xF0, 0x01, 0x01, 0x44, 0xE0, 0xDE, 0xDF, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, ++ 0xE0, 0xE0, 0x07, 0x90, 0x03, 0x44, 0xF8, 0x54, 0xE1, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x03, 0x74, ++ 0x54, 0xE0, 0xDF, 0x07, 0x07, 0x90, 0xF0, 0xFE, 0x01, 0x44, 0xE0, 0xE2, 0xE3, 0x07, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0xE4, 0x07, 0x90, 0x01, 0x44, 0xF8, 0x54, 0xE5, 0x07, 0x90, 0xF0, ++ 0x90, 0xF0, 0x03, 0x74, 0x54, 0xE0, 0xE3, 0x07, 0x06, 0x90, 0xF0, 0xFE, 0xC4, 0xFF, 0xE0, 0x66, ++ 0x24, 0x07, 0x54, 0x13, 0x04, 0x1D, 0x60, 0xFE, 0x07, 0x90, 0x22, 0x70, 0xF0, 0x03, 0x74, 0xC9, ++ 0xE0, 0xE4, 0x07, 0x90, 0x02, 0x44, 0xF8, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x44, 0xF8, 0x54, 0xE0, ++ 0x0D, 0x80, 0xF0, 0x03, 0x74, 0xC9, 0x07, 0x90, 0x05, 0x80, 0xF0, 0x01, 0xC9, 0x07, 0x90, 0xE4, ++ 0xC6, 0x07, 0x90, 0xF0, 0xF0, 0xF8, 0x54, 0xE0, 0xE0, 0x70, 0x06, 0x90, 0x78, 0xE0, 0xA3, 0xFE, ++ 0x13, 0xC3, 0xCE, 0x03, 0xF9, 0xD8, 0x13, 0xCE, 0x33, 0x33, 0x01, 0x54, 0xFF, 0xF8, 0x54, 0x33, ++ 0xE0, 0xC6, 0x07, 0x90, 0xF0, 0x4F, 0xF7, 0x54, 0xE0, 0x6F, 0x06, 0x90, 0x13, 0xC4, 0xC0, 0x54, ++ 0xFF, 0x03, 0x54, 0x13, 0xE0, 0xC7, 0x07, 0x90, 0xF0, 0x4F, 0xFC, 0x54, 0x74, 0xE6, 0x07, 0x90, ++ 0x07, 0x90, 0xF0, 0x03, 0xF0, 0xE4, 0xF0, 0xE7, 0x74, 0x83, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x03, ++ 0xF0, 0x0F, 0x74, 0x84, 0xF0, 0x85, 0x09, 0x90, 0xE0, 0x86, 0x09, 0x90, 0x04, 0x44, 0xE0, 0x54, ++ 0x87, 0x09, 0x90, 0xF0, 0x44, 0xE0, 0x54, 0xE0, 0x09, 0x90, 0xF0, 0x12, 0xE0, 0x54, 0xE0, 0x88, ++ 0x90, 0xF0, 0x17, 0x44, 0x54, 0xE0, 0x89, 0x09, 0xF0, 0x26, 0x44, 0xC0, 0xE0, 0x8A, 0x09, 0x90, ++ 0x01, 0x44, 0xFC, 0x54, 0x3C, 0x44, 0xE0, 0xF0, 0x8C, 0x09, 0x90, 0xF0, 0xF0, 0x03, 0x44, 0xE0, ++ 0xF0, 0xF3, 0x54, 0xE0, 0xE0, 0x83, 0x09, 0x90, 0x90, 0xF0, 0xFD, 0x54, 0x44, 0xE0, 0x07, 0x07, ++ 0xE5, 0x22, 0xF0, 0x10, 0x7E, 0x4E, 0x60, 0x3B, 0x12, 0x32, 0x7F, 0x20, 0x01, 0x90, 0x1B, 0x10, ++ 0x01, 0x44, 0xE0, 0xB1, 0x43, 0x06, 0x90, 0xF0, 0xF0, 0x04, 0x44, 0xE0, 0x54, 0xE6, 0x80, 0x78, ++ 0x33, 0xC4, 0xFC, 0x01, 0xE0, 0xFE, 0xE0, 0x54, 0xF0, 0x4E, 0xDF, 0x54, 0xE0, 0x75, 0x06, 0x90, ++ 0xEC, 0xF0, 0x01, 0x44, 0xE0, 0x25, 0xE0, 0x25, 0x74, 0x06, 0x90, 0xFF, 0x4F, 0xFB, 0x54, 0xE0, ++ 0xDF, 0x07, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0xE3, 0x07, 0x90, 0xE4, 0xF0, 0xFE, 0x54, ++ 0x08, 0xF6, 0xA4, 0x78, 0xF0, 0x07, 0x90, 0xF6, 0x13, 0x13, 0x13, 0xE0, 0xE0, 0x30, 0x1F, 0x54, ++ 0x43, 0x06, 0x90, 0x0D, 0xF0, 0x02, 0x44, 0xE0, 0x74, 0xF0, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x08, ++ 0x14, 0x60, 0xE0, 0xE1, 0xE0, 0xDF, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, 0x03, 0x74, 0xE1, 0x07, ++ 0xDF, 0x07, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0xB1, 0x01, 0x90, 0xDB, 0x07, 0x90, 0xFF, ++ 0x13, 0x13, 0xC4, 0xE0, 0xEF, 0xFE, 0x01, 0x54, 0x01, 0x54, 0x13, 0xC4, 0xDF, 0x54, 0xEF, 0xFD, ++ 0x54, 0x4E, 0xED, 0xFF, 0x54, 0x33, 0xC4, 0x01, 0x01, 0x90, 0x4F, 0xE0, 0xFF, 0xE0, 0xF0, 0xB1, ++ 0xE0, 0xDB, 0x07, 0x90, 0x01, 0x54, 0x13, 0xC4, 0x13, 0x13, 0xEF, 0xFE, 0xFD, 0x01, 0x54, 0x13, ++ 0xFF, 0xF7, 0x54, 0xEF, 0x01, 0x54, 0x4E, 0xED, 0x54, 0x33, 0x33, 0x33, 0x01, 0x90, 0x4F, 0xF8, ++ 0xFF, 0xE0, 0xF0, 0xB1, 0xE0, 0xDB, 0x07, 0x90, 0x01, 0x54, 0x13, 0xC3, 0x54, 0xC4, 0xEF, 0xFE, ++ 0x54, 0xEF, 0xFD, 0x01, 0x4E, 0xED, 0xFF, 0xEF, 0x54, 0xC4, 0x01, 0x54, 0x01, 0x90, 0x4F, 0xF0, ++ 0x07, 0x90, 0xF0, 0xB1, 0xF0, 0x62, 0x74, 0xDB, 0xE0, 0xF0, 0x07, 0x90, 0x01, 0x64, 0x07, 0x54, ++ 0x54, 0xE0, 0x3E, 0x60, 0x60, 0x03, 0x64, 0x07, 0xA3, 0x78, 0xD3, 0x37, 0x18, 0x00, 0x94, 0xE6, ++ 0x40, 0x00, 0x94, 0xE6, 0x16, 0xE6, 0x08, 0x08, 0x16, 0x01, 0x70, 0x18, 0x22, 0x38, 0x75, 0x22, ++ 0x7E, 0x5A, 0x39, 0x75, 0x12, 0x3F, 0x7F, 0x20, 0x01, 0x90, 0x1B, 0x10, 0xFE, 0x54, 0xE0, 0xB1, ++ 0x43, 0x06, 0x90, 0xF0, 0xF0, 0xFB, 0x54, 0xE0, 0xE0, 0x75, 0x06, 0x90, 0x22, 0xF0, 0x01, 0x44, ++ 0xE0, 0xF0, 0x07, 0x90, 0xBF, 0xFF, 0x07, 0x54, 0xA2, 0x78, 0x08, 0x03, 0x76, 0x08, 0x13, 0x76, ++ 0x78, 0xE4, 0x22, 0x88, 0xF6, 0x08, 0xF6, 0xA2, 0xE3, 0x07, 0x90, 0x22, 0xF0, 0x01, 0x44, 0xE0, ++ 0xE0, 0xEE, 0x07, 0x90, 0x75, 0xF0, 0x04, 0x44, 0x39, 0x75, 0x27, 0x38, 0x3B, 0xE5, 0x22, 0xBE, ++ 0x20, 0x7E, 0x07, 0x60, 0x10, 0x12, 0x6B, 0x7F, 0xE7, 0x07, 0x90, 0x1B, 0x90, 0xF0, 0x03, 0x74, ++ 0x54, 0xE0, 0xE6, 0x07, 0x01, 0x90, 0xF0, 0xFE, 0xFE, 0x54, 0xE0, 0xB1, 0x42, 0x06, 0x90, 0xF0, ++ 0xE0, 0xA3, 0xF0, 0xE0, 0xE0, 0xF0, 0xFB, 0x54, 0xE4, 0xF0, 0xDF, 0x54, 0x75, 0xF6, 0x80, 0x78, ++ 0x35, 0x75, 0x02, 0x34, 0x01, 0x30, 0x75, 0x56, 0x22, 0xC5, 0x31, 0x75, 0x00, 0x00, 0x00, 0x22, ++ 0xE0, 0x43, 0x07, 0x90, 0xE4, 0x0C, 0xE5, 0x30, 0xF0, 0xB3, 0x01, 0x90, 0x27, 0xA9, 0x26, 0xAA, ++ 0xE5, 0x3B, 0x03, 0x02, 0xE4, 0x05, 0x60, 0x2E, 0x27, 0xF5, 0x26, 0xF5, 0x3A, 0x30, 0x50, 0x22, ++ 0x30, 0x30, 0x31, 0x09, 0x0A, 0x58, 0x54, 0x62, 0x3A, 0x30, 0x50, 0x00, 0x74, 0x65, 0x53, 0x09, ++ 0x00, 0x0A, 0x70, 0x75, 0x09, 0x3A, 0x30, 0x50, 0x74, 0x69, 0x61, 0x57, 0x50, 0x00, 0x0A, 0x50, ++ 0x09, 0x09, 0x3A, 0x30, 0x00, 0x49, 0x44, 0x4D, 0x00, 0x0A, 0x00, 0x58, 0x09, 0x3A, 0x30, 0x50, ++ 0x0A, 0x43, 0x47, 0x41, 0x3A, 0x30, 0x50, 0x00, 0x47, 0x41, 0x09, 0x09, 0x64, 0x25, 0x3D, 0x43, ++ 0x57, 0x50, 0x00, 0x20, 0x64, 0x25, 0x3D, 0x52, 0x30, 0x50, 0x00, 0x0A, 0x4B, 0x4F, 0x09, 0x3A, ++ 0x50, 0x00, 0x0A, 0x30, 0x09, 0x09, 0x3A, 0x30, 0x20, 0x3A, 0x43, 0x4C, 0x00, 0x0A, 0x64, 0x25, ++ 0x09, 0x3A, 0x30, 0x50, 0x0A, 0x31, 0x4B, 0x4F, 0x3A, 0x30, 0x50, 0x00, 0x32, 0x4B, 0x4F, 0x09, ++ 0x30, 0x50, 0x00, 0x0A, 0x4B, 0x4F, 0x09, 0x3A, 0x50, 0x00, 0x0A, 0x33, 0x4F, 0x09, 0x3A, 0x30, ++ 0x50, 0x0A, 0x34, 0x4B, 0x09, 0x09, 0x3A, 0x30, 0x00, 0x64, 0x25, 0x00, 0x09, 0x3A, 0x30, 0x50, ++ 0x63, 0x61, 0x72, 0x54, 0x50, 0x00, 0x0A, 0x6B, 0x53, 0x09, 0x3A, 0x30, 0x0A, 0x63, 0x6E, 0x79, ++ 0x3A, 0x30, 0x50, 0x00, 0x77, 0x6F, 0x44, 0x09, 0x25, 0x3A, 0x00, 0x6E, 0x50, 0x00, 0x0A, 0x78, ++ 0x45, 0x09, 0x3A, 0x30, 0x0A, 0x74, 0x69, 0x78, 0x3A, 0x30, 0x50, 0x00, 0x44, 0x4D, 0x09, 0x09, ++ 0x25, 0x3D, 0x4C, 0x4C, 0xE5, 0x00, 0x0A, 0x64, 0x7E, 0x2A, 0x60, 0x2E, 0x12, 0x1D, 0x7F, 0x20, ++ 0x2C, 0x75, 0x1B, 0x10, 0x8F, 0x2D, 0x75, 0x21, 0xE4, 0x01, 0x2F, 0x75, 0x08, 0xF6, 0x83, 0x78, ++ 0x78, 0xF6, 0x08, 0xF6, 0x88, 0x78, 0xF6, 0x8A, 0x12, 0xFF, 0x03, 0x76, 0x81, 0x78, 0xE2, 0x03, ++ 0x76, 0x08, 0xAA, 0x76, 0xE6, 0x83, 0x78, 0xE6, 0x31, 0x16, 0x01, 0x60, 0x00, 0x06, 0x90, 0x6E, ++ 0x54, 0xC4, 0xFF, 0xE0, 0x19, 0xE0, 0x30, 0x0F, 0xE0, 0x03, 0x06, 0x90, 0x54, 0x13, 0x13, 0xFF, ++ 0x0D, 0xE0, 0x20, 0x3F, 0x11, 0x12, 0x81, 0x7F, 0x75, 0x06, 0x50, 0x3A, 0x2D, 0x75, 0x2B, 0x2C, ++ 0x12, 0x10, 0xC2, 0x0E, 0x06, 0x50, 0x4F, 0x11, 0x75, 0x2B, 0x2C, 0x75, 0x2B, 0xE5, 0x0E, 0x2D, ++ 0x04, 0x70, 0x2D, 0x65, 0x2C, 0x65, 0x2A, 0xE5, 0x2C, 0x85, 0x09, 0x60, 0x2B, 0x2D, 0x85, 0x2A, ++ 0xAA, 0x01, 0x2F, 0x75, 0x12, 0x2B, 0xA9, 0x2A, 0xF5, 0xE4, 0x3B, 0x03, 0x90, 0x78, 0x22, 0x2F, ++ 0xFF, 0x01, 0x54, 0xE6, 0x74, 0x9F, 0xE4, 0xC3, 0x54, 0x00, 0x94, 0x08, 0xE6, 0x18, 0xFC, 0x05, ++ 0x08, 0xFE, 0x13, 0xC3, 0xEE, 0xFF, 0x13, 0xE6, 0xEF, 0xF6, 0x18, 0x6C, 0xE5, 0x22, 0xF6, 0x08, ++ 0x7E, 0x09, 0x60, 0x2F, 0x12, 0x29, 0x7F, 0x20, 0x94, 0x91, 0x1B, 0x10, 0x2C, 0x75, 0xA5, 0x31, ++ 0x58, 0x2D, 0x75, 0x22, 0x23, 0x06, 0x90, 0x22, 0x13, 0x13, 0xFF, 0xE0, 0x92, 0x13, 0x3F, 0x54, ++ 0x27, 0x06, 0x90, 0x10, 0x03, 0xE0, 0x30, 0xE0, 0x90, 0x1A, 0x10, 0x30, 0x20, 0xE0, 0x27, 0x06, ++ 0x06, 0x90, 0x49, 0xE0, 0xA3, 0xFE, 0xE0, 0x26, 0xCE, 0x02, 0x78, 0xE0, 0x13, 0xCE, 0x13, 0xC3, ++ 0xE0, 0x20, 0xF9, 0xD8, 0x90, 0x10, 0xC2, 0x36, 0x0F, 0x74, 0x01, 0x0D, 0x21, 0x0D, 0x90, 0xF0, ++ 0x07, 0x90, 0xF0, 0x04, 0xFC, 0x54, 0xE0, 0xF9, 0xF3, 0x54, 0xE0, 0xF0, 0x90, 0xF0, 0x04, 0x44, ++ 0x54, 0xE0, 0xFA, 0x07, 0xF0, 0x01, 0x44, 0xFC, 0xF0, 0xF3, 0x54, 0xE0, 0x74, 0x0C, 0x0D, 0x90, ++ 0x0D, 0x90, 0xF0, 0x38, 0x01, 0x90, 0xF0, 0x2C, 0xD2, 0x34, 0x80, 0xA6, 0x21, 0x0D, 0x90, 0x10, ++ 0x90, 0xF0, 0x0F, 0x74, 0xF0, 0x04, 0x01, 0x0D, 0xE0, 0xF9, 0x07, 0x90, 0x01, 0x44, 0xFC, 0x54, ++ 0xF3, 0x54, 0xE0, 0xF0, 0xFA, 0x07, 0x90, 0xF0, 0xF0, 0xFC, 0x54, 0xE0, 0x44, 0xF3, 0x54, 0xE0, ++ 0x0D, 0x90, 0xF0, 0x04, 0xF0, 0x38, 0x74, 0x2C, 0xF0, 0x0C, 0x0D, 0x90, 0xE0, 0xA7, 0x01, 0x90, ++ 0xF0, 0x45, 0x08, 0x90, 0x33, 0xE4, 0x10, 0xA2, 0xE0, 0x25, 0x01, 0x54, 0x90, 0xFF, 0xE0, 0x25, ++ 0x54, 0xE0, 0x23, 0x06, 0x22, 0xF0, 0x4F, 0xFB, 0x02, 0x70, 0x2F, 0xE5, 0x20, 0x7E, 0xE0, 0x41, ++ 0x10, 0x12, 0x34, 0x7F, 0x00, 0x0D, 0x90, 0x1B, 0xF0, 0xF8, 0x54, 0xE0, 0xE0, 0x20, 0x0D, 0x90, ++ 0x78, 0xF0, 0xF8, 0x54, 0x08, 0xF4, 0x76, 0x8D, 0x0D, 0x90, 0x24, 0x76, 0x54, 0xC4, 0xE0, 0xAA, ++ 0x0D, 0x90, 0xFF, 0x0F, 0x54, 0xC4, 0xE0, 0xAB, 0xE4, 0xFF, 0x2F, 0x0F, 0x00, 0x24, 0xCF, 0x33, ++ 0x04, 0x34, 0xEF, 0xFD, 0x0B, 0x07, 0x90, 0xFC, 0x20, 0xF0, 0x75, 0xE0, 0x45, 0xEC, 0xFF, 0xA4, ++ 0xED, 0xF6, 0x08, 0xF0, 0xE4, 0xF6, 0x08, 0x4F, 0x90, 0xF6, 0x89, 0x78, 0x30, 0x74, 0xA9, 0x0D, ++ 0x47, 0x08, 0x90, 0xF0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0x08, 0x44, 0xE0, 0xE0, 0x48, 0x08, 0x90, ++ 0x04, 0x44, 0xF3, 0x54, 0x4C, 0x08, 0x90, 0xF0, 0x44, 0x0F, 0x54, 0xE0, 0x08, 0x90, 0xF0, 0x20, ++ 0x70, 0x44, 0xE0, 0x4B, 0x80, 0x44, 0xE0, 0xF0, 0x47, 0x08, 0x90, 0xF0, 0xF0, 0xF7, 0x54, 0xE0, ++ 0xE0, 0x00, 0x06, 0x90, 0x30, 0x0F, 0x54, 0xC4, 0xA5, 0x31, 0x04, 0xE0, 0x06, 0x90, 0x1E, 0x80, ++ 0xE0, 0x20, 0xE0, 0x27, 0x13, 0x13, 0xE0, 0x20, 0x90, 0xFF, 0x01, 0x54, 0xFE, 0xE0, 0x23, 0x06, ++ 0x01, 0x54, 0x13, 0x13, 0x90, 0x05, 0x60, 0x6F, 0xA8, 0x31, 0x27, 0x06, 0xF4, 0x76, 0x8D, 0x78, ++ 0x80, 0x24, 0x76, 0x08, 0x12, 0x8D, 0x7F, 0x5B, 0x54, 0x50, 0x3A, 0x11, 0xF4, 0x76, 0x8D, 0x78, ++ 0x90, 0x24, 0x76, 0x08, 0xC3, 0xE0, 0x4F, 0x08, 0x24, 0x50, 0x05, 0x94, 0x54, 0xE6, 0x90, 0x78, ++ 0x06, 0x90, 0xFF, 0x01, 0x13, 0xFD, 0xE0, 0x23, 0x6F, 0x01, 0x54, 0x13, 0x60, 0xE4, 0x01, 0x70, ++ 0x35, 0x06, 0x90, 0x07, 0xF0, 0x08, 0x44, 0xE0, 0x13, 0xE6, 0x90, 0x78, 0xB1, 0x31, 0x10, 0x92, ++ 0x3F, 0x7F, 0x20, 0x7E, 0x90, 0x1B, 0x10, 0x12, 0x13, 0xE0, 0x23, 0x06, 0x30, 0x3F, 0x54, 0x13, ++ 0x20, 0x7E, 0x07, 0xE0, 0x10, 0x12, 0x48, 0x7F, 0x7F, 0x20, 0x7E, 0x1B, 0x1B, 0x10, 0x12, 0x4A, ++ 0x06, 0x40, 0x7B, 0x71, 0x75, 0x23, 0x2C, 0x75, 0x90, 0x22, 0xA1, 0x2D, 0xFF, 0xE0, 0x4F, 0x08, ++ 0x94, 0x80, 0x64, 0xD3, 0x78, 0x0C, 0x40, 0x85, 0x0A, 0x94, 0xE6, 0x89, 0x80, 0x06, 0x03, 0x50, ++ 0xC3, 0x22, 0xC3, 0x0E, 0x94, 0x80, 0x64, 0xEF, 0xE4, 0x04, 0x50, 0x83, 0xD3, 0xF6, 0x89, 0x78, ++ 0x60, 0x2F, 0xE5, 0x22, 0x7F, 0x20, 0x7E, 0x1D, 0x1B, 0x10, 0x12, 0x4C, 0x0A, 0x76, 0x83, 0x78, ++ 0x07, 0x76, 0x91, 0x78, 0xE0, 0x00, 0x0D, 0x90, 0x90, 0xF0, 0x07, 0x44, 0x44, 0xE0, 0x20, 0x0D, ++ 0x83, 0x78, 0xF0, 0x07, 0x76, 0x4E, 0x70, 0xE6, 0xE6, 0x91, 0x78, 0x0A, 0x40, 0x00, 0x94, 0xD3, ++ 0x4F, 0x08, 0x90, 0x23, 0x0A, 0x94, 0xD3, 0xE0, 0xE6, 0x16, 0x1A, 0x40, 0x90, 0xFF, 0x07, 0x54, ++ 0x54, 0xE0, 0x00, 0x0D, 0xE6, 0xF0, 0x4F, 0xF8, 0x90, 0xFF, 0x07, 0x54, 0x54, 0xE0, 0x20, 0x0D, ++ 0x22, 0xF0, 0x4F, 0xF8, 0x55, 0x7F, 0x20, 0x7E, 0xFD, 0xE6, 0x91, 0x78, 0x10, 0x12, 0x00, 0x7C, ++ 0x7F, 0x20, 0x7E, 0x28, 0x4F, 0x08, 0x90, 0x62, 0x00, 0x7C, 0xFD, 0xE0, 0x75, 0x28, 0x10, 0x12, ++ 0x2D, 0x75, 0x26, 0x2C, 0x20, 0x7E, 0x22, 0xDE, 0x10, 0x12, 0xC1, 0x7F, 0x7F, 0x20, 0x7E, 0x1B, ++ 0xE6, 0x9D, 0x78, 0xCA, 0x12, 0x00, 0x7C, 0xFD, 0x90, 0xE4, 0x28, 0x10, 0x90, 0xF0, 0xAF, 0x01, ++ 0x54, 0xE0, 0x03, 0x06, 0x78, 0xE4, 0xF0, 0xFB, 0xF6, 0x08, 0xF6, 0x84, 0xE0, 0x99, 0x07, 0x90, ++ 0x90, 0xF0, 0x01, 0x44, 0xC4, 0xE0, 0x00, 0x06, 0xE0, 0x20, 0x0F, 0x54, 0x13, 0xC4, 0xE0, 0x2F, ++ 0xE0, 0x30, 0x07, 0x54, 0xA3, 0xFE, 0xE0, 0x27, 0xCE, 0x06, 0x78, 0xE0, 0x13, 0xCE, 0x13, 0xC3, ++ 0xE0, 0x20, 0xF9, 0xD8, 0x31, 0x06, 0x90, 0x17, 0x13, 0x13, 0xFF, 0xE0, 0xE0, 0x20, 0x3F, 0x54, ++ 0x50, 0x7B, 0x71, 0x0B, 0x22, 0x2C, 0x75, 0x11, 0x22, 0x58, 0x2D, 0x75, 0x16, 0xE6, 0x88, 0x78, ++ 0x7B, 0x71, 0x0B, 0x60, 0x2C, 0x75, 0x07, 0x40, 0xDE, 0x2D, 0x75, 0x26, 0x2B, 0x2C, 0x75, 0x22, ++ 0x22, 0x0E, 0x2D, 0x75, 0x01, 0x0D, 0x90, 0xE4, 0x00, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x38, 0x74, ++ 0x90, 0xF0, 0x20, 0x0D, 0xAA, 0x74, 0xA2, 0x0D, 0x02, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x30, 0x74, ++ 0x90, 0xF0, 0x22, 0x0D, 0x20, 0x74, 0x05, 0x0D, 0x25, 0x0D, 0x90, 0xF0, 0x06, 0x0D, 0x90, 0xF0, ++ 0x90, 0xF0, 0x9C, 0x74, 0x90, 0xF0, 0x26, 0x0D, 0x89, 0x74, 0x0A, 0x0D, 0x2A, 0x0D, 0x90, 0xF0, ++ 0x0D, 0x90, 0xE4, 0xF0, 0x07, 0x90, 0xF0, 0x21, 0x01, 0x44, 0xE0, 0xF8, 0xFD, 0x54, 0xE0, 0xF0, ++ 0xFD, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x54, 0xE0, 0x03, 0x08, 0xF0, 0x01, 0x44, 0xF8, ++ 0xE0, 0x10, 0x07, 0x90, 0x54, 0xC4, 0x0F, 0x54, 0x08, 0x90, 0x04, 0xF0, 0x07, 0x90, 0xF0, 0xCF, ++ 0x54, 0xC4, 0xE0, 0x10, 0x07, 0x90, 0xFF, 0x0F, 0x0F, 0x54, 0xE0, 0x0F, 0x4F, 0xF0, 0x54, 0xC4, ++ 0xF0, 0xCE, 0x08, 0x90, 0xE0, 0x0F, 0x07, 0x90, 0x90, 0x0F, 0x54, 0xC4, 0x90, 0xF0, 0xCD, 0x08, ++ 0x01, 0x74, 0xD0, 0x08, 0xC5, 0x08, 0x90, 0xF0, 0x14, 0xF0, 0x03, 0x74, 0xCC, 0x08, 0x90, 0xF0, ++ 0x01, 0x74, 0xF0, 0x04, 0x60, 0x08, 0x90, 0xF0, 0x74, 0xF0, 0x03, 0x74, 0x08, 0x90, 0xF0, 0x01, ++ 0xF0, 0x13, 0x74, 0x61, 0x74, 0x62, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x03, 0xF0, 0xFA, 0x74, 0x63, ++ 0x74, 0x67, 0x08, 0x90, 0x01, 0x74, 0xF0, 0x03, 0x10, 0x07, 0x90, 0xF0, 0xC4, 0x0F, 0x54, 0xE0, ++ 0x90, 0x04, 0xF0, 0x54, 0x90, 0xF0, 0x6A, 0x08, 0xC4, 0xE0, 0x10, 0x07, 0x90, 0xFF, 0x0F, 0x54, ++ 0x54, 0xE0, 0x0F, 0x07, 0xF0, 0x54, 0xC4, 0x0F, 0x69, 0x08, 0x90, 0x4F, 0x0F, 0x07, 0x90, 0xF0, ++ 0x54, 0xC4, 0xFF, 0xE0, 0x68, 0x08, 0x90, 0x0F, 0x6B, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, ++ 0x0B, 0x74, 0x52, 0x08, 0x51, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x03, 0x74, 0x0A, 0x74, 0x52, 0x08, ++ 0x51, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x02, 0x74, 0x90, 0xF0, 0x39, 0x08, 0xF0, 0x04, 0x40, 0x08, ++ 0x74, 0x41, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x05, 0x08, 0x90, 0xF0, 0x42, 0xF0, 0x03, 0x74, 0x43, ++ 0x90, 0xF0, 0x01, 0x74, 0x03, 0x74, 0x3E, 0x08, 0xF0, 0x01, 0x74, 0xF0, 0x74, 0x3D, 0x08, 0x90, ++ 0x08, 0x90, 0xF0, 0x03, 0x01, 0x74, 0xF0, 0x3C, 0x7B, 0x07, 0x90, 0xF0, 0x30, 0x06, 0x90, 0xF0, ++ 0xE0, 0xA3, 0xFE, 0xE0, 0xC3, 0xCE, 0x03, 0x78, 0xD8, 0x13, 0xCE, 0x13, 0x33, 0x01, 0x54, 0xF9, ++ 0x08, 0x54, 0x33, 0x33, 0x07, 0x90, 0x01, 0x44, 0x06, 0x90, 0xF0, 0x7C, 0xC0, 0x54, 0xE0, 0x2F, ++ 0x54, 0x13, 0x13, 0xC4, 0x07, 0x90, 0xFF, 0x03, 0xFC, 0x54, 0xE0, 0x7D, 0x07, 0x90, 0xF0, 0x4F, ++ 0xF0, 0x15, 0x74, 0xA7, 0xF0, 0xA8, 0x07, 0x90, 0x07, 0x90, 0xF0, 0xE4, 0x90, 0xF0, 0x04, 0x95, ++ 0x90, 0xF0, 0x94, 0x07, 0x03, 0x74, 0x96, 0x07, 0x97, 0x07, 0x90, 0xF0, 0x07, 0x90, 0xE4, 0xF0, ++ 0x07, 0x90, 0xF0, 0x95, 0x90, 0xF0, 0x04, 0x99, 0x90, 0xF0, 0x98, 0x07, 0x90, 0xF0, 0x9A, 0x07, ++ 0x03, 0x74, 0x9B, 0x07, 0x07, 0x90, 0xE4, 0xF0, 0x08, 0x90, 0xF0, 0x99, 0xF0, 0x03, 0x74, 0x14, ++ 0xE0, 0x12, 0x08, 0x90, 0xE4, 0xF0, 0xFE, 0x54, 0x14, 0x08, 0x90, 0xFD, 0x60, 0x01, 0x64, 0xE0, ++ 0x94, 0xC3, 0xED, 0x0A, 0x00, 0x04, 0x50, 0xFF, 0x7E, 0xEE, 0x80, 0x0D, 0x7C, 0xD9, 0x7F, 0x20, ++ 0x28, 0x10, 0x12, 0x00, 0x74, 0x1C, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x43, 0x08, 0x90, 0xF0, 0x1E, ++ 0x08, 0x90, 0xF0, 0x20, 0x08, 0x90, 0xF0, 0x22, 0xF0, 0x03, 0x74, 0x09, 0xF0, 0x0B, 0x08, 0x90, ++ 0xF0, 0x0C, 0x08, 0x90, 0xF0, 0x0D, 0x08, 0x90, 0x0D, 0x00, 0xFD, 0xE4, 0x90, 0xFB, 0x80, 0xBD, ++ 0x42, 0x74, 0x1C, 0x08, 0x1E, 0x08, 0x90, 0xF0, 0x20, 0x08, 0x90, 0xF0, 0x22, 0x08, 0x90, 0xF0, ++ 0x09, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x04, 0x74, 0x90, 0xF0, 0x0B, 0x08, 0x90, 0xF0, 0x0C, 0x08, ++ 0x90, 0xF0, 0x0D, 0x08, 0x44, 0xE0, 0x12, 0x08, 0x08, 0x90, 0xF0, 0x01, 0xF0, 0x12, 0x74, 0x24, ++ 0x74, 0xFB, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x0D, 0x10, 0x44, 0xE0, 0x07, 0x2F, 0xE5, 0x22, 0xF0, ++ 0x20, 0x7E, 0x0E, 0x60, 0x10, 0x12, 0x6A, 0x7F, 0x76, 0x83, 0x78, 0x1B, 0x59, 0x2B, 0x12, 0x05, ++ 0x07, 0x50, 0x7B, 0x71, 0x75, 0x24, 0x2C, 0x75, 0x78, 0x22, 0x16, 0x2D, 0x2F, 0x70, 0xE6, 0x83, ++ 0x74, 0x34, 0x08, 0x90, 0x20, 0x7E, 0xF0, 0x40, 0x06, 0xC0, 0x73, 0x7F, 0x08, 0x90, 0x07, 0xC0, ++ 0x90, 0xFE, 0xE0, 0x37, 0xFD, 0xE0, 0x38, 0x08, 0xD0, 0xED, 0xFC, 0xEE, 0x12, 0x06, 0xD0, 0x07, ++ 0x2C, 0x75, 0x28, 0x10, 0x93, 0x2D, 0x75, 0x27, 0x01, 0x76, 0x86, 0x78, 0x22, 0xF4, 0x76, 0x08, ++ 0x48, 0x60, 0x2F, 0xE5, 0x92, 0x7F, 0x20, 0x7E, 0x78, 0x1B, 0x10, 0x12, 0x90, 0x64, 0x76, 0x83, ++ 0x0D, 0x74, 0x27, 0x08, 0x4B, 0x08, 0x90, 0xF0, 0xF0, 0x07, 0x44, 0xE0, 0xE0, 0x4A, 0x08, 0x90, ++ 0x90, 0xF0, 0x03, 0x44, 0x02, 0x74, 0x29, 0x08, 0x2A, 0x08, 0x90, 0xF0, 0x44, 0xE3, 0x54, 0xE0, ++ 0x08, 0x90, 0xF0, 0x14, 0xF0, 0x02, 0x74, 0x2E, 0x74, 0x61, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x07, ++ 0xF0, 0x03, 0x74, 0x62, 0xE0, 0x63, 0x08, 0x90, 0xF0, 0xFA, 0x74, 0xE4, 0x07, 0x50, 0x7B, 0x71, ++ 0x75, 0x24, 0x2C, 0x75, 0x78, 0x22, 0x16, 0x2D, 0x06, 0x70, 0xE6, 0x83, 0x75, 0x28, 0x2C, 0x75, ++ 0xE5, 0x22, 0xDF, 0x2D, 0x7E, 0x58, 0x60, 0x2F, 0x12, 0x80, 0x7F, 0x20, 0x83, 0x78, 0x1B, 0x10, ++ 0x08, 0x90, 0x0A, 0x76, 0xF0, 0x0D, 0x74, 0x27, 0x74, 0x29, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x04, ++ 0xE3, 0x54, 0xE0, 0x2A, 0xE0, 0xF0, 0x10, 0x44, 0x90, 0xF0, 0x02, 0x44, 0x54, 0xE0, 0x2D, 0x08, ++ 0x08, 0x90, 0xF0, 0xFB, 0xF0, 0x03, 0x74, 0x2E, 0xE0, 0x2F, 0x08, 0x90, 0x90, 0xF0, 0x01, 0x44, ++ 0x01, 0x74, 0x31, 0x08, 0x32, 0x08, 0x90, 0xF0, 0xF0, 0xCD, 0x74, 0xE0, 0x74, 0x61, 0x08, 0x90, ++ 0x08, 0x90, 0xF0, 0x04, 0x90, 0xF0, 0x14, 0x62, 0xE4, 0xE0, 0x63, 0x08, 0x71, 0xF0, 0xFA, 0x74, ++ 0x7F, 0x07, 0x40, 0x7B, 0x3A, 0x11, 0x12, 0x86, 0x2C, 0x75, 0x07, 0x50, 0x16, 0x2D, 0x75, 0x24, ++ 0xE6, 0x83, 0x78, 0x22, 0x08, 0x90, 0x0F, 0x70, 0x94, 0xC3, 0xE0, 0x4E, 0x75, 0x06, 0x50, 0x17, ++ 0x2D, 0x75, 0x28, 0x2C, 0x2F, 0xE5, 0x22, 0x16, 0x20, 0x7E, 0x2C, 0x60, 0x10, 0x12, 0x89, 0x7F, ++ 0x76, 0x83, 0x78, 0x1B, 0x2A, 0x08, 0x90, 0x14, 0xF0, 0xFD, 0x54, 0xE0, 0xE0, 0x2D, 0x08, 0x90, ++ 0x90, 0xF0, 0xFB, 0x54, 0x54, 0xE0, 0x31, 0x08, 0x08, 0x90, 0xF0, 0xFD, 0xF0, 0x07, 0x74, 0x61, ++ 0x74, 0x62, 0x08, 0x90, 0x8F, 0x11, 0xF0, 0x03, 0x40, 0x7B, 0x23, 0x12, 0x12, 0x86, 0x7F, 0x07, ++ 0x07, 0x50, 0x3A, 0x11, 0x75, 0x24, 0x2C, 0x75, 0x78, 0x22, 0x16, 0x2D, 0x2E, 0x70, 0xE6, 0x83, ++ 0xE0, 0x4E, 0x08, 0x90, 0x50, 0x0D, 0x94, 0xC3, 0x27, 0x2C, 0x75, 0x08, 0x80, 0x30, 0x2D, 0x75, ++ 0x27, 0x2C, 0x75, 0x06, 0xE4, 0x93, 0x2D, 0x75, 0xF0, 0x34, 0x08, 0x90, 0x44, 0x9F, 0x54, 0xE0, ++ 0x08, 0x90, 0xF0, 0x40, 0x06, 0x70, 0xE0, 0x37, 0x75, 0x26, 0x2C, 0x75, 0x90, 0x22, 0xDE, 0x2D, ++ 0x0D, 0x74, 0x27, 0x08, 0xED, 0x02, 0x7D, 0xF0, 0x08, 0x90, 0x0F, 0x54, 0x08, 0x90, 0xF0, 0x34, ++ 0x56, 0xF5, 0xE0, 0x37, 0xE0, 0x38, 0x08, 0x90, 0x56, 0xE5, 0x57, 0xF5, 0xE0, 0x95, 0x33, 0xFF, ++ 0x57, 0xE5, 0xC3, 0xFE, 0xE5, 0x57, 0xF5, 0x9F, 0x56, 0xF5, 0x9E, 0x56, 0xE0, 0x34, 0x08, 0x90, ++ 0x90, 0xF0, 0x10, 0x44, 0x56, 0xE5, 0x35, 0x08, 0x36, 0x08, 0x90, 0xF0, 0xE4, 0xF0, 0x57, 0xE5, ++ 0xF0, 0x34, 0x08, 0x90, 0xBF, 0x0A, 0xBD, 0x0D, 0x74, 0x27, 0x08, 0x90, 0xE5, 0x22, 0xF0, 0x05, ++ 0x7E, 0x3B, 0x60, 0x2F, 0x12, 0x9B, 0x7F, 0x20, 0x83, 0x78, 0x1B, 0x10, 0x06, 0x90, 0x05, 0x76, ++ 0x13, 0x13, 0xE0, 0x29, 0xE0, 0x30, 0x3F, 0x54, 0x02, 0x0D, 0x90, 0x50, 0x44, 0x8F, 0x54, 0xE0, ++ 0x0D, 0x90, 0xF0, 0x30, 0x8F, 0x54, 0xE0, 0x22, 0x90, 0xF0, 0x30, 0x44, 0x54, 0xE0, 0x05, 0x0D, ++ 0xF0, 0x20, 0x44, 0x8F, 0xE0, 0x25, 0x0D, 0x90, 0x20, 0x44, 0x8F, 0x54, 0x06, 0x90, 0x22, 0xF0, ++ 0x13, 0xFF, 0xE0, 0x29, 0x30, 0x3F, 0x54, 0x13, 0x4A, 0x31, 0x0D, 0xE0, 0xFD, 0x33, 0xFC, 0xE4, ++ 0xA9, 0x7F, 0x20, 0x7E, 0x78, 0x28, 0x10, 0x12, 0x0D, 0x70, 0xE6, 0x83, 0x4A, 0x7F, 0x20, 0x7E, ++ 0x75, 0x1B, 0x10, 0x12, 0x2D, 0x75, 0x29, 0x2C, 0x0A, 0x7F, 0x22, 0xAA, 0x06, 0x7D, 0x0D, 0x7E, ++ 0x10, 0xD2, 0x0D, 0x7C, 0x83, 0x8E, 0x82, 0x8F, 0x0F, 0x54, 0xC4, 0xE0, 0x40, 0x06, 0x94, 0xD3, ++ 0x4E, 0x08, 0x90, 0x36, 0x50, 0x19, 0x94, 0xE0, 0x8C, 0x82, 0x8D, 0x2E, 0xC4, 0xFD, 0xE0, 0x83, ++ 0xED, 0xFC, 0x0F, 0x54, 0xEC, 0xFD, 0x0F, 0x54, 0xC4, 0x0F, 0x54, 0x14, 0xF0, 0x4D, 0xF0, 0x54, ++ 0xFF, 0xE0, 0x82, 0x8F, 0xFE, 0x0F, 0x54, 0xC4, 0xFF, 0x0F, 0x54, 0xEF, 0x0F, 0x54, 0x14, 0xEE, ++ 0x4F, 0xF0, 0x54, 0xC4, 0x90, 0x10, 0xC2, 0xF0, 0x90, 0xE0, 0x06, 0x0D, 0x90, 0xF0, 0x26, 0x0D, ++ 0x90, 0xE0, 0x0A, 0x0D, 0xA2, 0xF0, 0x2A, 0x0D, 0x20, 0x7E, 0x22, 0x10, 0x10, 0x12, 0xAC, 0x7F, ++ 0x4F, 0x08, 0x90, 0x1B, 0xF6, 0x8A, 0x78, 0xE0, 0x29, 0x08, 0x90, 0xE4, 0x2A, 0x08, 0x90, 0xF0, ++ 0x44, 0xE3, 0x54, 0xE0, 0x08, 0x90, 0xF0, 0x08, 0xF0, 0x02, 0x74, 0x2E, 0xE0, 0x2D, 0x08, 0x90, ++ 0x90, 0xF0, 0xFB, 0x54, 0x07, 0x74, 0x61, 0x08, 0x62, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x05, 0x74, ++ 0xE4, 0xE0, 0x63, 0x08, 0x12, 0xF0, 0xFA, 0x74, 0x07, 0x50, 0x7B, 0x23, 0x75, 0x24, 0x2C, 0x75, ++ 0x75, 0x22, 0x16, 0x2D, 0x2D, 0x75, 0x2A, 0x2C, 0xFD, 0x01, 0x90, 0x45, 0xFF, 0x70, 0x54, 0xE0, ++ 0xE0, 0x4B, 0x08, 0x90, 0xF0, 0x4F, 0x8F, 0x54, 0xE0, 0xFD, 0x01, 0x90, 0x90, 0xFF, 0x0C, 0x54, ++ 0x54, 0xE0, 0x4A, 0x08, 0x90, 0xF0, 0x4F, 0xF3, 0x90, 0xE0, 0xFD, 0x01, 0xE0, 0x30, 0x4C, 0x08, ++ 0x0F, 0x54, 0xE0, 0x06, 0xE0, 0x06, 0x80, 0xF0, 0x20, 0x44, 0x0F, 0x54, 0xFD, 0x01, 0x90, 0xF0, ++ 0x48, 0x08, 0x90, 0xE0, 0xE0, 0x07, 0xE1, 0x30, 0x08, 0x44, 0xF3, 0x54, 0x54, 0xE0, 0x22, 0xF0, ++ 0xF0, 0x04, 0x44, 0xF3, 0x70, 0x2F, 0xE5, 0x22, 0x7E, 0xEC, 0x41, 0x02, 0x12, 0xB7, 0x7F, 0x20, ++ 0x78, 0xE4, 0x1B, 0x10, 0x06, 0x90, 0xF6, 0x88, 0x13, 0xC4, 0xE0, 0x26, 0xFE, 0x24, 0x07, 0x54, ++ 0x70, 0x04, 0x1D, 0x60, 0x7F, 0x07, 0x90, 0x22, 0x90, 0xF0, 0x03, 0x74, 0x54, 0xE0, 0x9A, 0x07, ++ 0xF0, 0x02, 0x44, 0xF8, 0xE0, 0x96, 0x07, 0x90, 0x03, 0x44, 0xF8, 0x54, 0x90, 0x0D, 0x80, 0xF0, ++ 0x01, 0x74, 0x7F, 0x07, 0xE4, 0x05, 0x80, 0xF0, 0xF0, 0x7F, 0x07, 0x90, 0x74, 0xA7, 0x07, 0x90, ++ 0x07, 0x90, 0xF0, 0x3F, 0xF0, 0x2A, 0x74, 0xA8, 0xE0, 0x99, 0x07, 0x90, 0xE4, 0xF0, 0xFE, 0x54, ++ 0xF0, 0xA8, 0x07, 0x90, 0xE0, 0xFD, 0x01, 0x90, 0x13, 0x13, 0x13, 0xC4, 0x01, 0x90, 0x01, 0x54, ++ 0x0E, 0xE0, 0x30, 0xFE, 0x08, 0x90, 0xFF, 0xE0, 0xF0, 0x8F, 0xE0, 0x4F, 0x04, 0xF0, 0xE5, 0xA4, ++ 0x90, 0xE0, 0x01, 0x80, 0x90, 0xF0, 0x4D, 0x08, 0x54, 0xE0, 0x48, 0x08, 0xF0, 0x04, 0x44, 0xF3, ++ 0xE0, 0x4A, 0x08, 0x90, 0x90, 0xF0, 0xF3, 0x54, 0x54, 0xE0, 0x4C, 0x08, 0xF0, 0x20, 0x44, 0x0F, ++ 0xE0, 0x4B, 0x08, 0x90, 0xE0, 0xF0, 0x70, 0x44, 0x22, 0xF0, 0x80, 0x44, 0x50, 0x7B, 0x23, 0x12, ++ 0x24, 0x2C, 0x75, 0x07, 0x22, 0x16, 0x2D, 0x75, 0x75, 0x02, 0x28, 0x75, 0x24, 0x75, 0x79, 0x29, ++ 0x01, 0x25, 0x75, 0x02, 0x75, 0x24, 0x2C, 0x75, 0x2E, 0x75, 0x16, 0x2D, 0x20, 0x7E, 0x22, 0x01, ++ 0x10, 0x12, 0xCF, 0x7F, 0xFB, 0x07, 0x90, 0x1B, 0x90, 0xF0, 0x01, 0x74, 0x3F, 0x74, 0xA8, 0x07, ++ 0x99, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xAF, 0x01, 0x90, 0xE4, 0x03, 0x06, 0x90, 0xF0, ++ 0xF0, 0xFB, 0x54, 0xE0, 0xF0, 0xDF, 0x54, 0xE0, 0xF6, 0x7F, 0x78, 0xE4, 0x74, 0x20, 0x06, 0x90, ++ 0x74, 0xA3, 0xF0, 0x80, 0x08, 0x90, 0xF0, 0xFF, 0xF0, 0xE4, 0xE0, 0x45, 0x75, 0x02, 0x28, 0x75, ++ 0x24, 0x75, 0x51, 0x29, 0xBB, 0x25, 0x75, 0x01, 0x76, 0x83, 0x78, 0x22, 0x25, 0x08, 0x90, 0x05, ++ 0x90, 0xF0, 0x03, 0x74, 0x90, 0xF0, 0x27, 0x08, 0x01, 0x74, 0x28, 0x08, 0x27, 0x08, 0x90, 0xF0, ++ 0x90, 0xF0, 0x0F, 0x74, 0x04, 0x74, 0x29, 0x08, 0x2D, 0x08, 0x90, 0xF0, 0x07, 0x74, 0xF0, 0x14, ++ 0x2E, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x04, 0x74, 0xF0, 0x14, 0x2F, 0x08, 0xF0, 0x30, 0x08, 0x90, ++ 0x74, 0x2F, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x01, 0xF0, 0x17, 0x74, 0x2A, 0x74, 0x2B, 0x08, 0x90, ++ 0x08, 0x90, 0xF0, 0x15, 0xF0, 0x04, 0x74, 0x31, 0x74, 0x33, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x40, ++ 0xF0, 0x03, 0x74, 0x2C, 0x74, 0x25, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x01, 0xF0, 0x0D, 0x74, 0x27, ++ 0x74, 0x2D, 0x08, 0x90, 0x90, 0xE4, 0xF0, 0x05, 0x7B, 0xF0, 0x31, 0x08, 0xFD, 0x7F, 0x7A, 0xFF, ++ 0x51, 0x91, 0x01, 0x7F, 0xEC, 0x7A, 0x00, 0x7B, 0x91, 0xFF, 0xFD, 0xE4, 0xE6, 0x91, 0x78, 0x51, ++ 0xA4, 0x08, 0xF0, 0x75, 0xE0, 0x74, 0xC3, 0xFF, 0x95, 0xE4, 0xFD, 0x9F, 0x75, 0xE6, 0xFC, 0xF0, ++ 0xFF, 0xA4, 0x04, 0xF0, 0xFF, 0x9F, 0xED, 0xC3, 0xEF, 0xF0, 0x95, 0xEC, 0xE4, 0xFA, 0x00, 0x7B, ++ 0x91, 0x02, 0x7F, 0xFD, 0x7A, 0x00, 0x7B, 0x51, 0xE4, 0x02, 0x7D, 0x40, 0x90, 0x51, 0x91, 0xFF, ++ 0x54, 0xE0, 0x2A, 0x08, 0x08, 0x90, 0xF0, 0xFE, 0x01, 0x44, 0xE0, 0x47, 0x04, 0x44, 0xE0, 0xF0, ++ 0x48, 0x08, 0x90, 0xF0, 0x44, 0xFC, 0x54, 0xE0, 0x08, 0x90, 0xF0, 0x01, 0xF0, 0x54, 0xE0, 0x4C, ++ 0x90, 0xF0, 0x04, 0x44, 0x54, 0xE0, 0x4B, 0x08, 0xF0, 0x06, 0x44, 0xF8, 0xF0, 0x08, 0x44, 0xE0, ++ 0xE0, 0x4A, 0x08, 0x90, 0x01, 0x44, 0xFC, 0x54, 0x47, 0x08, 0x90, 0xF0, 0xF0, 0xFB, 0x54, 0xE0, ++ 0x0F, 0x54, 0xEF, 0x22, 0xED, 0xFF, 0x10, 0x44, 0x60, 0x54, 0x33, 0xC4, 0x34, 0x08, 0x90, 0x4F, ++ 0x90, 0xFF, 0xEA, 0xF0, 0xF0, 0xEF, 0x35, 0x08, 0xEB, 0x36, 0x08, 0x90, 0x08, 0x90, 0xE4, 0xF0, ++ 0x22, 0x22, 0xF0, 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xE0, 0x43, 0x07, 0x90, 0xE4, 0x0C, 0xE5, 0x30, 0xF0, 0xB3, 0x01, 0x90, 0x27, 0xA9, 0x26, 0xAA, ++ 0xE5, 0x3B, 0x03, 0x02, 0xE4, 0x05, 0x60, 0x2E, 0x27, 0xF5, 0x26, 0xF5, 0x3A, 0x30, 0x50, 0x22, ++ 0x74, 0x61, 0x44, 0x09, 0x50, 0x00, 0x0A, 0x61, 0x09, 0x09, 0x3A, 0x30, 0x43, 0x4C, 0x6F, 0x4C, ++ 0x0A, 0x78, 0x25, 0x00, 0x61, 0x46, 0x4C, 0x00, 0x20, 0x20, 0x6C, 0x69, 0x78, 0x25, 0x20, 0x3A, ++ 0x58, 0x52, 0x00, 0x0A, 0x54, 0x41, 0x54, 0x53, 0x25, 0x20, 0x3A, 0x45, 0x0A, 0x00, 0x0A, 0x78, ++ 0x09, 0x3A, 0x30, 0x50, 0x4B, 0x4F, 0x4C, 0x09, 0x25, 0x20, 0x3A, 0x20, 0x50, 0x00, 0x0A, 0x64, ++ 0x09, 0x09, 0x3A, 0x30, 0x20, 0x4C, 0x56, 0x4C, 0x64, 0x25, 0x20, 0x3A, 0x30, 0x50, 0x00, 0x0A, ++ 0x50, 0x09, 0x09, 0x3A, 0x3A, 0x20, 0x52, 0x57, 0x20, 0x44, 0x25, 0x20, 0x30, 0x50, 0x00, 0x0A, ++ 0x53, 0x09, 0x09, 0x3A, 0x3A, 0x20, 0x52, 0x4E, 0x20, 0x64, 0x25, 0x20, 0x00, 0x0A, 0x42, 0x64, ++ 0x09, 0x3A, 0x30, 0x50, 0x4F, 0x52, 0x46, 0x09, 0x25, 0x20, 0x3A, 0x20, 0x70, 0x70, 0x20, 0x44, ++ 0x50, 0x00, 0x0A, 0x6D, 0x09, 0x09, 0x3A, 0x30, 0x3A, 0x51, 0x45, 0x4C, 0x44, 0x25, 0x20, 0x00, ++ 0x50, 0x00, 0x0A, 0x00, 0x09, 0x09, 0x3A, 0x30, 0x3A, 0x45, 0x46, 0x44, 0x3A, 0x30, 0x50, 0x00, ++ 0x2D, 0x2D, 0x09, 0x09, 0x0A, 0x2D, 0x2D, 0x2D, 0x3A, 0x30, 0x50, 0x00, 0x78, 0x54, 0x09, 0x09, ++ 0x6B, 0x61, 0x57, 0x2D, 0x20, 0x20, 0x3A, 0x65, 0x00, 0x0A, 0x64, 0x25, 0x09, 0x3A, 0x30, 0x50, ++ 0x2D, 0x78, 0x54, 0x09, 0x65, 0x69, 0x75, 0x51, 0x25, 0x20, 0x3A, 0x74, 0x50, 0x00, 0x0A, 0x64, ++ 0x09, 0x09, 0x3A, 0x30, 0x57, 0x2D, 0x78, 0x52, 0x3A, 0x65, 0x6B, 0x61, 0x64, 0x25, 0x20, 0x20, ++ 0x30, 0x50, 0x00, 0x0A, 0x52, 0x09, 0x09, 0x3A, 0x75, 0x51, 0x2D, 0x78, 0x3A, 0x74, 0x65, 0x69, ++ 0x0A, 0x64, 0x25, 0x20, 0x3A, 0x30, 0x50, 0x00, 0x6F, 0x4C, 0x09, 0x09, 0x0A, 0x52, 0x43, 0x53, ++ 0x3A, 0x30, 0x50, 0x00, 0x6F, 0x4C, 0x09, 0x09, 0x50, 0x00, 0x0A, 0x53, 0x09, 0x09, 0x3A, 0x30, ++ 0x5F, 0x44, 0x41, 0x42, 0x0A, 0x47, 0x49, 0x53, 0x26, 0x1F, 0x18, 0x00, 0x4E, 0x41, 0x36, 0x2D, ++ 0x9A, 0x84, 0x70, 0x5E, 0xFF, 0xEA, 0xCD, 0xB3, 0x20, 0x14, 0x0D, 0x08, 0xC9, 0x7F, 0x50, 0x33, ++ 0x02, 0x70, 0x2E, 0xE5, 0x20, 0x7E, 0xD9, 0x21, 0x10, 0x12, 0x1D, 0x7F, 0x03, 0x06, 0x90, 0x1B, ++ 0xF0, 0x04, 0x44, 0xE0, 0x54, 0xE6, 0x7F, 0x78, 0x33, 0xC4, 0xFC, 0x01, 0xE0, 0xFE, 0xE0, 0x54, ++ 0xF0, 0x4E, 0xDF, 0x54, 0xE0, 0x35, 0x06, 0x90, 0xEC, 0xF0, 0x01, 0x44, 0xE0, 0x25, 0xE0, 0x25, ++ 0x34, 0x06, 0x90, 0xFF, 0x4F, 0xFB, 0x54, 0xE0, 0x8B, 0x78, 0xE4, 0xF0, 0x78, 0xF6, 0x08, 0xF6, ++ 0xA1, 0x78, 0xF6, 0x89, 0x28, 0x3C, 0x75, 0xF6, 0x75, 0xE0, 0x3D, 0x75, 0x3F, 0x75, 0x27, 0x3E, ++ 0x6D, 0x07, 0x90, 0x5C, 0xF0, 0x0C, 0x44, 0xE0, 0x74, 0x6C, 0x07, 0x90, 0x06, 0x90, 0xF0, 0x08, ++ 0xA3, 0xFE, 0xE0, 0x30, 0xCE, 0x02, 0x78, 0xE0, 0x13, 0xCE, 0x13, 0xC3, 0xE0, 0x30, 0xF9, 0xD8, ++ 0xE4, 0xEE, 0xD2, 0x16, 0x08, 0xF6, 0x94, 0x78, 0x08, 0xF6, 0x08, 0xF6, 0x08, 0xF6, 0x08, 0xF6, ++ 0x08, 0xF6, 0x08, 0xF6, 0xD1, 0xF6, 0x08, 0xF6, 0x30, 0x06, 0x90, 0x42, 0xE0, 0xA3, 0xFE, 0xE0, ++ 0xC3, 0xCE, 0x02, 0x78, 0xD8, 0x13, 0xCE, 0x13, 0x2C, 0xE0, 0x30, 0xF9, 0x70, 0xE6, 0x9C, 0x78, ++ 0xFF, 0x01, 0x90, 0x27, 0x54, 0x13, 0x13, 0xE0, 0x16, 0xE0, 0x20, 0x3F, 0xFE, 0xE6, 0x8B, 0x78, ++ 0xE4, 0xFF, 0xE6, 0x08, 0xFA, 0x7B, 0xFD, 0xFC, 0xF8, 0xF9, 0xFF, 0x7A, 0xFF, 0x02, 0x12, 0xC3, ++ 0xEC, 0xD2, 0x06, 0x70, 0x01, 0x76, 0x9C, 0x78, 0xE0, 0x97, 0x07, 0x90, 0x07, 0x90, 0x14, 0x60, ++ 0x01, 0x44, 0xE0, 0x95, 0x97, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x03, 0x74, 0x54, 0xE0, 0x95, 0x07, ++ 0x01, 0x90, 0xF0, 0xFE, 0x02, 0x44, 0xE0, 0xAF, 0xFE, 0xE0, 0xF0, 0xFF, 0xE0, 0x91, 0x07, 0x90, ++ 0x54, 0x13, 0x13, 0xC4, 0xC4, 0xEE, 0xFD, 0x01, 0xFE, 0x01, 0x54, 0x13, 0xFF, 0xDF, 0x54, 0xEF, ++ 0x01, 0x54, 0x4D, 0xEE, 0xE0, 0x54, 0x33, 0xC4, 0xAF, 0x01, 0x90, 0x4F, 0x90, 0xFF, 0xE0, 0xF0, ++ 0xC4, 0xE0, 0x91, 0x07, 0xFE, 0x01, 0x54, 0x13, 0x13, 0x13, 0x13, 0xEF, 0xEF, 0xFD, 0x01, 0x54, ++ 0xED, 0xFF, 0xF7, 0x54, 0x33, 0x01, 0x54, 0x4E, 0xF8, 0x54, 0x33, 0x33, 0xAF, 0x01, 0x90, 0x4F, ++ 0x90, 0xFF, 0xE0, 0xF0, 0xC3, 0xE0, 0x91, 0x07, 0xFE, 0x01, 0x54, 0x13, 0x01, 0x54, 0xC4, 0xEF, ++ 0xEF, 0x54, 0xEF, 0xFD, 0x54, 0x4E, 0xED, 0xFF, 0xF0, 0x54, 0xC4, 0x01, 0xAF, 0x01, 0x90, 0x4F, ++ 0x91, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x62, 0x74, 0xFE, 0xE0, 0x30, 0x06, 0x02, 0x78, 0xE0, 0xA3, ++ 0xCE, 0x13, 0xC3, 0xCE, 0x20, 0xF9, 0xD8, 0x13, 0x08, 0x90, 0x0D, 0xE0, 0x9E, 0x78, 0xE0, 0x4E, ++ 0x4F, 0x08, 0x90, 0xF6, 0x71, 0xF6, 0x08, 0xE0, 0x30, 0x06, 0x90, 0xEB, 0xE0, 0xA3, 0xFE, 0xE0, ++ 0xC3, 0xCE, 0x02, 0x78, 0xD8, 0x13, 0xCE, 0x13, 0x05, 0xE0, 0x30, 0xF9, 0x80, 0x48, 0xF5, 0xE4, ++ 0xE4, 0xF7, 0xB1, 0x3F, 0x90, 0x48, 0xF5, 0x33, 0x40, 0x74, 0xC8, 0x09, 0x37, 0x08, 0x90, 0xF0, ++ 0x01, 0x94, 0xD3, 0xE0, 0x48, 0x75, 0x2A, 0x50, 0x7F, 0x20, 0x7E, 0x01, 0x1B, 0x10, 0x12, 0x27, ++ 0x31, 0x7F, 0x20, 0x7E, 0x07, 0xC0, 0x06, 0xC0, 0xE0, 0x37, 0x08, 0x90, 0x38, 0x08, 0x90, 0xFE, ++ 0x24, 0x00, 0x7C, 0xE0, 0x3E, 0xEC, 0xFD, 0x00, 0xD0, 0x07, 0xD0, 0xFC, 0x28, 0x10, 0x12, 0x06, ++ 0x11, 0x12, 0x10, 0xC2, 0xE5, 0x12, 0x40, 0x4F, 0x74, 0x0E, 0x70, 0x48, 0x70, 0x3F, 0x65, 0xF0, ++ 0x65, 0x2C, 0x74, 0x04, 0x61, 0x02, 0x60, 0x3E, 0xC2, 0xEC, 0xC2, 0xEA, 0x7F, 0x20, 0x7E, 0xEE, ++ 0x7C, 0x48, 0xAD, 0x35, 0x28, 0x10, 0x12, 0x00, 0x42, 0x7F, 0x20, 0x7E, 0xF0, 0x7D, 0x2C, 0x7C, ++ 0x90, 0x28, 0x10, 0x12, 0x54, 0xE0, 0x47, 0x07, 0x54, 0xE0, 0xF0, 0xFB, 0x07, 0x90, 0xF0, 0xEF, ++ 0xF0, 0xFF, 0x74, 0x68, 0xF0, 0x6C, 0x07, 0x90, 0xE0, 0x01, 0x0D, 0x90, 0x90, 0xF0, 0xDF, 0x54, ++ 0x54, 0xE0, 0x21, 0x0D, 0x0D, 0x90, 0xF0, 0xDF, 0x7F, 0x54, 0xE0, 0x04, 0x24, 0x0D, 0x90, 0xF0, ++ 0xF0, 0x7F, 0x54, 0xE0, 0xE0, 0x01, 0x0D, 0x90, 0x90, 0xF0, 0xEF, 0x54, 0x54, 0xE0, 0x21, 0x0D, ++ 0x08, 0x90, 0xF0, 0xEF, 0x02, 0x44, 0xE0, 0x52, 0x51, 0x08, 0x90, 0xF0, 0xF0, 0x02, 0x44, 0xE0, ++ 0xE0, 0x29, 0x06, 0x90, 0x90, 0xF0, 0xFE, 0x54, 0x54, 0xE0, 0x84, 0x01, 0x54, 0xE0, 0xF0, 0xFE, ++ 0x07, 0x90, 0xF0, 0xFD, 0xFE, 0x54, 0xE0, 0xAC, 0x05, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, ++ 0xF0, 0x10, 0x44, 0xE0, 0x74, 0xAD, 0x07, 0x90, 0x06, 0x90, 0xF0, 0x3C, 0xFB, 0x54, 0xE0, 0x03, ++ 0x35, 0x06, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0x74, 0x7F, 0x02, 0x7E, 0x29, 0x8F, 0x28, 0x8E, ++ 0x27, 0x8F, 0x26, 0x8E, 0x75, 0x01, 0x24, 0x75, 0x30, 0x22, 0xF7, 0x25, 0xF5, 0xA1, 0x02, 0x18, ++ 0xE6, 0x06, 0x8C, 0x78, 0x06, 0x01, 0x70, 0x18, 0x64, 0xE6, 0x8C, 0x78, 0x60, 0x46, 0x18, 0x01, ++ 0x90, 0xD8, 0x81, 0x02, 0xF5, 0xE0, 0x64, 0x08, 0x65, 0x08, 0x90, 0x57, 0xE5, 0x58, 0xF5, 0xE0, ++ 0x78, 0x57, 0xAE, 0x58, 0xE7, 0xA2, 0xCE, 0x06, 0xD8, 0x13, 0xCE, 0x13, 0x06, 0xAC, 0xFD, 0xF8, ++ 0x57, 0xAE, 0x58, 0xE5, 0xA2, 0xCE, 0x05, 0x78, 0x13, 0xCE, 0x13, 0xE7, 0xFF, 0x2D, 0xF8, 0xD8, ++ 0xEF, 0xFE, 0x3C, 0xEE, 0x58, 0xF5, 0x58, 0x25, 0xF5, 0x57, 0x35, 0xEE, 0xE6, 0x9E, 0x78, 0x57, ++ 0x7C, 0xED, 0x7D, 0xFF, 0x8F, 0x9A, 0xD1, 0x21, 0x90, 0x58, 0xAF, 0x59, 0xF0, 0xEF, 0x20, 0x06, ++ 0x94, 0xD3, 0x59, 0xE5, 0x40, 0x59, 0xAF, 0x0E, 0xEF, 0x0E, 0x7F, 0x02, 0x54, 0xC4, 0x0F, 0x54, ++ 0x06, 0x90, 0xFF, 0xF0, 0x0F, 0x54, 0xE0, 0x21, 0x90, 0xE4, 0xF0, 0x4F, 0xE0, 0xF0, 0x34, 0x08, ++ 0x40, 0x44, 0x9F, 0x54, 0x37, 0x08, 0x90, 0xF0, 0x7E, 0x5A, 0xF5, 0xE0, 0x78, 0x4F, 0x7F, 0x20, ++ 0xE6, 0x06, 0x08, 0x84, 0x70, 0x04, 0x86, 0x18, 0xFD, 0x14, 0x06, 0x01, 0x7E, 0x28, 0x10, 0x12, ++ 0xC0, 0x5F, 0x7F, 0x20, 0xE5, 0x07, 0xC0, 0x06, 0x08, 0x90, 0xFE, 0x5A, 0xEE, 0xFD, 0xE0, 0x38, ++ 0x07, 0xD0, 0xED, 0xFC, 0x10, 0x12, 0x06, 0xD0, 0x7F, 0x20, 0x7E, 0x28, 0xE6, 0x9F, 0x78, 0x6E, ++ 0xE0, 0x95, 0x33, 0xFD, 0x28, 0x10, 0x12, 0xFC, 0x7E, 0x7F, 0x20, 0x7E, 0x00, 0x7C, 0x59, 0xAD, ++ 0x7E, 0x28, 0x10, 0x12, 0xAD, 0x90, 0x7F, 0x20, 0x12, 0x57, 0xAC, 0x58, 0x5A, 0xE5, 0x28, 0x10, ++ 0x40, 0x01, 0x94, 0xD3, 0x22, 0xF5, 0xA1, 0x02, 0x64, 0xE6, 0x8C, 0x78, 0x70, 0x46, 0x18, 0x02, ++ 0x7F, 0x20, 0x7E, 0x47, 0x1B, 0x10, 0x12, 0xA3, 0x34, 0x08, 0x90, 0xE4, 0x9F, 0x54, 0xE0, 0xF0, ++ 0x56, 0xF5, 0xE4, 0xF0, 0x0F, 0x54, 0x56, 0xE5, 0x34, 0x08, 0x90, 0xFF, 0x4F, 0xF0, 0x54, 0xE0, ++ 0x7F, 0x20, 0x7E, 0xF0, 0xC0, 0x06, 0xC0, 0xAD, 0x37, 0x08, 0x90, 0x07, 0x08, 0x90, 0xFE, 0xE0, ++ 0xED, 0xFD, 0xE0, 0x38, 0x07, 0xD0, 0x06, 0xAC, 0x10, 0x12, 0x06, 0xD0, 0xE5, 0x56, 0x05, 0x28, ++ 0x0A, 0x94, 0xC3, 0x56, 0x50, 0x80, 0xCE, 0x40, 0x64, 0xE6, 0x8C, 0x78, 0x70, 0x46, 0x18, 0x03, ++ 0x7F, 0x20, 0x7E, 0x50, 0x1B, 0x10, 0x12, 0xB3, 0x34, 0x08, 0x90, 0xE4, 0x9F, 0x54, 0xE0, 0xF0, ++ 0xE4, 0xF0, 0x20, 0x44, 0x56, 0xE5, 0x56, 0xF5, 0x90, 0xFF, 0x0F, 0x54, 0x54, 0xE0, 0x34, 0x08, ++ 0x7E, 0xF0, 0x4F, 0xF0, 0xC0, 0xAD, 0x7F, 0x20, 0x90, 0x07, 0xC0, 0x06, 0xFE, 0xE0, 0x37, 0x08, ++ 0xE0, 0x38, 0x08, 0x90, 0x06, 0xAC, 0xED, 0xFD, 0x06, 0xD0, 0x07, 0xD0, 0x05, 0x28, 0x10, 0x12, ++ 0xC3, 0x56, 0xE5, 0x56, 0xCE, 0x40, 0x08, 0x94, 0xB1, 0x7F, 0x20, 0x7E, 0x80, 0x1B, 0x10, 0x12, ++ 0xE6, 0x8C, 0x78, 0x74, 0x46, 0x18, 0x04, 0x64, 0x06, 0x90, 0x6B, 0x70, 0xA3, 0xFE, 0xE0, 0x30, ++ 0xCE, 0x02, 0x78, 0xE0, 0x13, 0xCE, 0x13, 0xC3, 0xE0, 0x30, 0xF9, 0xD8, 0x7F, 0x20, 0x7E, 0x58, ++ 0x1B, 0x10, 0x12, 0xBD, 0xC9, 0x7F, 0x20, 0x7E, 0xFC, 0xE6, 0x98, 0x78, 0x12, 0xFD, 0xE6, 0x08, ++ 0x20, 0x7E, 0x28, 0x10, 0x9A, 0x78, 0xDC, 0x7F, 0xE6, 0x08, 0xFC, 0xE6, 0x28, 0x10, 0x12, 0xFD, ++ 0xEF, 0x7F, 0x20, 0x7E, 0xFC, 0xE6, 0x94, 0x78, 0x12, 0xFD, 0xE6, 0x08, 0x21, 0x7E, 0x28, 0x10, ++ 0x96, 0x78, 0x02, 0x7F, 0xE6, 0x08, 0xFC, 0xE6, 0x28, 0x10, 0x12, 0xFD, 0xBD, 0x7F, 0x20, 0x7E, ++ 0xE4, 0x1B, 0x10, 0x12, 0x08, 0xF6, 0x94, 0x78, 0x08, 0xF6, 0x08, 0xF6, 0x08, 0xF6, 0x08, 0xF6, ++ 0x08, 0xF6, 0x08, 0xF6, 0x90, 0x22, 0xC3, 0xF6, 0xD3, 0xE0, 0xAA, 0x07, 0x06, 0x40, 0xA0, 0x94, ++ 0x15, 0x7F, 0x21, 0x7E, 0x08, 0x90, 0x31, 0x80, 0x94, 0xC3, 0xE0, 0x4F, 0x78, 0x0E, 0x50, 0x03, ++ 0x94, 0x06, 0xE6, 0x89, 0x7E, 0x0A, 0x40, 0x03, 0x80, 0x21, 0x7F, 0x21, 0x89, 0x78, 0xE4, 0x1A, ++ 0x4E, 0x08, 0x90, 0xF6, 0x3C, 0x94, 0xD3, 0xE0, 0xA1, 0x78, 0x12, 0x40, 0x94, 0xD3, 0x06, 0xE6, ++ 0x7E, 0x0D, 0x40, 0x03, 0x12, 0x2B, 0x7F, 0x21, 0x22, 0xD3, 0x1B, 0x10, 0xF6, 0xA1, 0x78, 0xE4, ++ 0x07, 0x90, 0x22, 0xC3, 0x03, 0x54, 0xE0, 0xFA, 0xA4, 0x20, 0xF0, 0x75, 0xE5, 0xFF, 0x00, 0x24, ++ 0xAD, 0x0D, 0x34, 0xF0, 0x08, 0x90, 0xFC, 0x07, 0xF0, 0x40, 0x74, 0x34, 0xE0, 0x37, 0x08, 0x90, ++ 0xA4, 0x14, 0xF0, 0x75, 0xF5, 0x56, 0xF0, 0x85, 0x8C, 0x82, 0x8D, 0x57, 0x07, 0x54, 0xE0, 0x83, ++ 0x93, 0x48, 0x21, 0x90, 0xAC, 0x00, 0x7E, 0xFF, 0x12, 0x57, 0xAD, 0x56, 0x56, 0x8E, 0x98, 0x02, ++ 0xFF, 0xE4, 0x57, 0x8F, 0x39, 0x21, 0x90, 0xEF, 0x56, 0xE5, 0xFE, 0x93, 0x04, 0x40, 0x9E, 0xD3, ++ 0xF0, 0x0E, 0xBF, 0x0F, 0xEF, 0x21, 0x06, 0x90, 0x5B, 0x8C, 0x22, 0xF0, 0xFB, 0xE4, 0x5C, 0x8D, ++ 0x83, 0xF5, 0x82, 0xF5, 0x80, 0x64, 0xEF, 0xC3, 0x02, 0x50, 0x81, 0x94, 0xEF, 0xD3, 0x01, 0x7F, ++ 0xBF, 0x94, 0x80, 0x64, 0x3F, 0x7F, 0x02, 0x40, 0x04, 0xF0, 0x75, 0xEF, 0xF0, 0xAC, 0xFD, 0xA4, ++ 0x09, 0xE7, 0x20, 0xED, 0xFD, 0xE0, 0x25, 0x0B, 0x80, 0xFC, 0x33, 0xEC, 0xAF, 0xFA, 0xE4, 0xF3, ++ 0x12, 0x04, 0xAE, 0x05, 0x06, 0xAC, 0x98, 0x02, 0x78, 0xED, 0x07, 0xAD, 0x13, 0xC3, 0xCE, 0x07, ++ 0xF9, 0xD8, 0x13, 0xCE, 0xC3, 0x06, 0xAC, 0xFD, 0x40, 0x01, 0x94, 0xEC, 0x9A, 0x07, 0x74, 0x24, ++ 0x7E, 0x01, 0x74, 0xFF, 0x08, 0x07, 0xA8, 0x00, 0x33, 0xC3, 0x05, 0x80, 0xD8, 0xCE, 0x33, 0xCE, ++ 0xF5, 0x82, 0x25, 0xF9, 0x83, 0x35, 0xEE, 0x82, 0xC3, 0xEC, 0x83, 0xF5, 0x13, 0xED, 0xFC, 0x13, ++ 0x08, 0xBA, 0x0A, 0xFD, 0x05, 0x74, 0xC3, 0xBA, 0xFE, 0xEF, 0xFF, 0x9B, 0xF5, 0x82, 0x25, 0xE4, ++ 0x83, 0x35, 0xEE, 0x82, 0x00, 0x7C, 0x83, 0xF5, 0x82, 0xAF, 0x06, 0x7D, 0x98, 0x02, 0x12, 0xFE, ++ 0x82, 0x8F, 0x83, 0x8E, 0x95, 0x82, 0xE5, 0xD3, 0x95, 0x83, 0xE5, 0x5C, 0xE4, 0x07, 0x40, 0x5B, ++ 0x82, 0xF5, 0x83, 0xF5, 0xE5, 0xC3, 0x0D, 0x80, 0xF5, 0x82, 0x95, 0x5C, 0x95, 0x5B, 0xE5, 0x82, ++ 0xE5, 0x83, 0xF5, 0x83, 0x75, 0x82, 0xF5, 0x83, 0x22, 0xFF, 0x00, 0x83, 0xE0, 0x6C, 0x07, 0x90, ++ 0x47, 0xE5, 0x47, 0xF5, 0x50, 0xF7, 0xB1, 0xF0, 0x76, 0x9D, 0x78, 0x0A, 0xF0, 0x2C, 0x12, 0x10, ++ 0xE5, 0x56, 0x28, 0x02, 0x03, 0xE1, 0x20, 0x47, 0x90, 0x56, 0x28, 0x02, 0x13, 0xE0, 0xA9, 0x07, ++ 0x03, 0x54, 0x13, 0x13, 0x0E, 0x03, 0xBF, 0xFF, 0xE0, 0xA8, 0x07, 0x90, 0xE0, 0xF0, 0x08, 0x44, ++ 0x02, 0xF0, 0xF7, 0x54, 0x07, 0x90, 0x56, 0x28, 0x13, 0x13, 0xE0, 0xA9, 0x64, 0x03, 0x54, 0x13, ++ 0x02, 0x03, 0x60, 0x01, 0x08, 0x90, 0x3E, 0x28, 0x9E, 0x78, 0xE0, 0x4E, 0x4F, 0x08, 0x90, 0xF6, ++ 0x75, 0xF6, 0x08, 0xE0, 0x2B, 0x12, 0x06, 0x43, 0x47, 0x07, 0x90, 0xFE, 0xF0, 0x10, 0x44, 0xE0, ++ 0xE0, 0x90, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, 0x44, 0xE0, 0x84, 0x01, 0x44, 0xE0, 0xF0, 0x04, ++ 0x08, 0x90, 0xF0, 0x01, 0xFE, 0x54, 0xE0, 0x47, 0xFD, 0x01, 0x90, 0xF0, 0xFF, 0x70, 0x54, 0xE0, ++ 0xE0, 0x4B, 0x08, 0x90, 0xF0, 0x4F, 0x8F, 0x54, 0xE0, 0xFD, 0x01, 0x90, 0x90, 0xFF, 0x0C, 0x54, ++ 0x54, 0xE0, 0x4A, 0x08, 0x90, 0xF0, 0x4F, 0xF3, 0x90, 0xE0, 0xFD, 0x01, 0xE0, 0x30, 0x4C, 0x08, ++ 0x0F, 0x54, 0xE0, 0x06, 0xE0, 0x06, 0x80, 0xF0, 0x20, 0x44, 0x0F, 0x54, 0xFD, 0x01, 0x90, 0xF0, ++ 0x48, 0x08, 0x90, 0xE0, 0xE0, 0x08, 0xE1, 0x30, 0x08, 0x44, 0xF3, 0x54, 0xE0, 0x06, 0x80, 0xF0, ++ 0x04, 0x44, 0xF3, 0x54, 0x6D, 0x07, 0x90, 0xF0, 0xF0, 0xFB, 0x54, 0xE0, 0x74, 0x6C, 0x07, 0x90, ++ 0x01, 0x90, 0xF0, 0x08, 0x07, 0x90, 0xE0, 0xFA, 0x6F, 0x11, 0xF0, 0xAD, 0x07, 0x90, 0x18, 0x80, ++ 0x13, 0x13, 0xE0, 0xA9, 0xFF, 0x03, 0x54, 0x13, 0x90, 0x0B, 0x02, 0xBF, 0x44, 0xE0, 0xAC, 0x07, ++ 0x54, 0xE0, 0xF0, 0x10, 0x47, 0xE5, 0xF0, 0xEF, 0x11, 0x13, 0xE0, 0x30, 0x61, 0x08, 0x90, 0xAA, ++ 0xFF, 0x0F, 0x54, 0xE0, 0x90, 0x07, 0x07, 0xBF, 0x54, 0xE0, 0x47, 0x07, 0x90, 0x22, 0xF0, 0xEF, ++ 0x44, 0xE0, 0x47, 0x08, 0x54, 0xE0, 0xF0, 0x40, 0x07, 0x90, 0xF0, 0x7F, 0xF0, 0x08, 0x74, 0x6C, ++ 0xE0, 0xFB, 0x01, 0x90, 0xF0, 0x6C, 0x08, 0x90, 0x75, 0x18, 0x42, 0x75, 0x3F, 0x75, 0x2A, 0x3E, ++ 0xA9, 0x07, 0x90, 0xEC, 0x13, 0x13, 0xFF, 0xE0, 0x60, 0x03, 0x54, 0x13, 0x13, 0x13, 0xE0, 0x0A, ++ 0xFF, 0x03, 0x54, 0x13, 0x51, 0x02, 0x02, 0xBF, 0x08, 0x90, 0x22, 0x79, 0xF0, 0x01, 0x74, 0x60, ++ 0xE0, 0x61, 0x08, 0x90, 0x94, 0xC3, 0x0F, 0x54, 0xE0, 0x0B, 0x50, 0x07, 0xFE, 0xF0, 0x54, 0xFF, ++ 0x0F, 0x54, 0x04, 0xEF, 0x08, 0x90, 0xF0, 0x4E, 0x0F, 0x54, 0xE0, 0x61, 0x40, 0x06, 0x94, 0xC3, ++ 0x2A, 0x08, 0x90, 0x0E, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0x2D, 0x08, 0x90, 0x22, 0xF0, 0xFB, 0x54, ++ 0x74, 0x68, 0x07, 0x90, 0x30, 0xE0, 0xF0, 0xFF, 0x07, 0x90, 0x21, 0xE2, 0x01, 0x44, 0xE0, 0xAC, ++ 0x90, 0x0C, 0x31, 0xF0, 0x44, 0xE0, 0x47, 0x07, 0x01, 0x90, 0xF0, 0x04, 0x08, 0x44, 0xE0, 0x84, ++ 0x02, 0x44, 0xE0, 0xF0, 0x29, 0x3C, 0x75, 0xF0, 0x22, 0x43, 0x3D, 0x75, 0xC3, 0x7C, 0x50, 0x7D, ++ 0x07, 0x90, 0x01, 0x7F, 0xFB, 0x54, 0xE0, 0x47, 0x01, 0x54, 0xEF, 0xF0, 0xE0, 0x25, 0xE0, 0x25, ++ 0x48, 0x07, 0x90, 0xFF, 0x4F, 0xFB, 0x54, 0xE0, 0x07, 0x90, 0xE4, 0xF0, 0x07, 0x90, 0xF0, 0x52, ++ 0x90, 0xED, 0xF0, 0x51, 0xEC, 0xF0, 0x54, 0x07, 0xF0, 0x53, 0x07, 0x90, 0x74, 0x68, 0x07, 0x90, ++ 0x90, 0x22, 0xF0, 0x01, 0x02, 0x74, 0x68, 0x07, 0xE2, 0x20, 0xE0, 0xF0, 0x47, 0x07, 0x90, 0x0F, ++ 0xF0, 0xFB, 0x54, 0xE0, 0x74, 0x68, 0x07, 0x90, 0xED, 0x21, 0xF0, 0x01, 0xE0, 0x68, 0x07, 0x90, ++ 0x74, 0x05, 0xE0, 0x30, 0x69, 0x31, 0xF0, 0x01, 0x45, 0x08, 0x90, 0x22, 0xE4, 0x41, 0xF5, 0xE0, ++ 0x7C, 0xE2, 0x7D, 0xF0, 0x31, 0x01, 0x7F, 0x04, 0x47, 0x07, 0x90, 0x12, 0xF0, 0x04, 0x44, 0xE0, ++ 0x75, 0x29, 0x3C, 0x75, 0x90, 0x22, 0x87, 0x3D, 0x02, 0x74, 0x68, 0x07, 0xE2, 0x20, 0xE0, 0xF0, ++ 0x45, 0x08, 0x90, 0x08, 0x80, 0xF0, 0x41, 0xE5, 0x68, 0x07, 0x90, 0x54, 0x05, 0xE0, 0x30, 0xE0, ++ 0x51, 0xF0, 0x01, 0x74, 0x07, 0x90, 0x22, 0x36, 0xF0, 0x02, 0x74, 0x68, 0x0A, 0xE2, 0x20, 0xE0, ++ 0xE6, 0x06, 0x99, 0x78, 0x06, 0x01, 0x70, 0x18, 0x07, 0x90, 0x33, 0x80, 0xE0, 0x30, 0xE0, 0x68, ++ 0xF0, 0x01, 0x74, 0x2B, 0xE6, 0x06, 0x9B, 0x78, 0x06, 0x01, 0x70, 0x18, 0x40, 0x15, 0x40, 0xAF, ++ 0x51, 0x19, 0x70, 0xEF, 0x90, 0x0C, 0x31, 0x11, 0x44, 0xE0, 0x47, 0x07, 0x3C, 0x75, 0xF0, 0x04, ++ 0x43, 0x3D, 0x75, 0x29, 0xE6, 0x06, 0x99, 0x78, 0x06, 0x01, 0x70, 0x18, 0x90, 0x11, 0x51, 0x22, ++ 0x54, 0xE0, 0xAC, 0x07, 0x01, 0x90, 0xF0, 0xFE, 0xFD, 0x54, 0xE0, 0x84, 0x47, 0x07, 0x90, 0xF0, ++ 0xF0, 0xFB, 0x54, 0xE0, 0x74, 0x68, 0x07, 0x90, 0x3C, 0x75, 0xF0, 0x01, 0xE0, 0x3D, 0x75, 0x28, ++ 0x23, 0x06, 0x90, 0x22, 0x54, 0x13, 0x13, 0xE0, 0x05, 0xE0, 0x30, 0x3F, 0x80, 0x24, 0x0D, 0x90, ++ 0x04, 0x0D, 0x90, 0x03, 0xF0, 0x7F, 0x54, 0xE0, 0x74, 0x52, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x0A, ++ 0x01, 0x44, 0xE0, 0x05, 0x06, 0x90, 0x22, 0xF0, 0x13, 0x13, 0xE0, 0x23, 0xE0, 0x30, 0x3F, 0x54, ++ 0x24, 0x0D, 0x90, 0x05, 0x0D, 0x90, 0x03, 0x80, 0x80, 0x44, 0xE0, 0x04, 0x52, 0x08, 0x90, 0xF0, ++ 0x90, 0xF0, 0x08, 0x74, 0x54, 0xE0, 0x05, 0x08, 0x40, 0x75, 0xF0, 0xFE, 0x45, 0x08, 0x90, 0x50, ++ 0x7D, 0xF0, 0x41, 0xE5, 0xE4, 0xF4, 0x7C, 0x24, 0x90, 0x12, 0x31, 0xFF, 0x44, 0xE0, 0x47, 0x07, ++ 0x3C, 0x75, 0xF0, 0x04, 0xA6, 0x3D, 0x75, 0x29, 0xAC, 0x07, 0x90, 0x22, 0xF0, 0x10, 0x44, 0xE0, ++ 0xE0, 0x90, 0x07, 0x90, 0xE4, 0xF0, 0xFE, 0x54, 0xF0, 0x99, 0x07, 0x90, 0xE0, 0x84, 0x01, 0x90, ++ 0x90, 0xF0, 0xFE, 0x54, 0x01, 0x74, 0x60, 0x08, 0x6D, 0x07, 0x90, 0xF0, 0xF0, 0x04, 0x44, 0xE0, ++ 0xE0, 0x47, 0x08, 0x90, 0xE0, 0xF0, 0x40, 0x44, 0x90, 0xF0, 0x80, 0x44, 0x54, 0xE0, 0x48, 0x08, ++ 0xF0, 0x04, 0x44, 0xF3, 0xE0, 0x4C, 0x08, 0x90, 0x20, 0x44, 0x0F, 0x54, 0x4A, 0x08, 0x90, 0xF0, ++ 0xF0, 0xF3, 0x54, 0xE0, 0xE0, 0x4B, 0x08, 0x90, 0x90, 0xF0, 0x70, 0x44, 0x44, 0xE0, 0x47, 0x08, ++ 0x07, 0x90, 0xF0, 0x01, 0xF0, 0x09, 0x74, 0x6C, 0xE0, 0xAC, 0x07, 0x90, 0x90, 0xF0, 0xEF, 0x54, ++ 0x3C, 0x74, 0xAD, 0x07, 0x27, 0x3E, 0x75, 0xF0, 0x22, 0x5C, 0x3F, 0x75, 0x74, 0x6C, 0x07, 0x90, ++ 0x30, 0xE0, 0xF0, 0x02, 0x08, 0x90, 0x21, 0xE3, 0x01, 0x44, 0xE0, 0x2A, 0x2D, 0x08, 0x90, 0xF0, ++ 0xF0, 0x04, 0x44, 0xE0, 0x74, 0x60, 0x08, 0x90, 0x7F, 0x71, 0xF0, 0x15, 0xE0, 0x6C, 0x07, 0x90, ++ 0x91, 0x36, 0xE3, 0x30, 0x90, 0x32, 0x80, 0x69, 0x13, 0xE0, 0xA9, 0x07, 0x03, 0x54, 0x13, 0x13, ++ 0x0D, 0x03, 0xBF, 0xFF, 0xE0, 0xA8, 0x07, 0x90, 0xE0, 0xF0, 0x08, 0x44, 0x80, 0xF0, 0xF7, 0x54, ++ 0xA9, 0x07, 0x90, 0x18, 0x13, 0x13, 0xFF, 0xE0, 0x60, 0x03, 0x54, 0x13, 0x13, 0x13, 0xE0, 0x0A, ++ 0xFF, 0x03, 0x54, 0x13, 0x51, 0x02, 0x02, 0xBF, 0x6C, 0x07, 0x90, 0x79, 0x2E, 0xE0, 0x30, 0xE0, ++ 0x01, 0x74, 0x42, 0x15, 0xD3, 0x42, 0xE5, 0xF0, 0x04, 0x40, 0x43, 0x95, 0x14, 0x80, 0xAA, 0x11, ++ 0xE0, 0x2A, 0x08, 0x90, 0x90, 0xF0, 0x01, 0x44, 0x44, 0xE0, 0x2D, 0x08, 0x08, 0x90, 0xF0, 0x04, ++ 0xF0, 0x15, 0x74, 0x60, 0x06, 0x70, 0x42, 0xE5, 0x01, 0x76, 0x9D, 0x78, 0x90, 0x22, 0xF0, 0x91, ++ 0x44, 0xE0, 0x47, 0x08, 0x08, 0x90, 0xF0, 0x80, 0xF0, 0x0F, 0x74, 0x27, 0x74, 0x2F, 0x08, 0x90, ++ 0x08, 0x90, 0xF0, 0x03, 0xF0, 0x07, 0x74, 0x2D, 0x74, 0x25, 0x08, 0x90, 0x01, 0x90, 0xF0, 0x03, ++ 0x01, 0x54, 0xE0, 0xF9, 0xFF, 0xF0, 0x54, 0xC4, 0xE0, 0x05, 0x08, 0x90, 0xF0, 0x4F, 0xEF, 0x54, ++ 0x74, 0x25, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x01, 0xF0, 0x05, 0x74, 0x2D, 0x74, 0x27, 0x08, 0x90, ++ 0x06, 0x90, 0xF0, 0x0F, 0x13, 0x13, 0xE0, 0x23, 0xE0, 0x30, 0x3F, 0x54, 0x04, 0x0D, 0x90, 0x05, ++ 0x0D, 0x90, 0x03, 0x80, 0x80, 0x44, 0xE0, 0x24, 0x60, 0x42, 0x75, 0xF0, 0xF4, 0x7C, 0x24, 0x7D, ++ 0x04, 0x91, 0xFF, 0xE4, 0xE0, 0x47, 0x07, 0x90, 0x90, 0xF0, 0x10, 0x44, 0x2A, 0x74, 0xA8, 0x07, ++ 0x6C, 0x07, 0x90, 0xF0, 0x75, 0xF0, 0x08, 0x74, 0x3F, 0x75, 0x2C, 0x3E, 0xC4, 0x7D, 0x22, 0x34, ++ 0xFF, 0xE4, 0x09, 0x7C, 0xE0, 0x47, 0x07, 0x90, 0xEF, 0xF0, 0xEF, 0x54, 0x54, 0xC4, 0x01, 0x54, ++ 0x07, 0x90, 0xFF, 0xF0, 0xEF, 0x54, 0xE0, 0x48, 0x90, 0xE4, 0xF0, 0x4F, 0x90, 0xF0, 0x5A, 0x07, ++ 0xED, 0xF0, 0x59, 0x07, 0xF0, 0x5C, 0x07, 0x90, 0x5B, 0x07, 0x90, 0xEC, 0x6C, 0x07, 0x90, 0xF0, ++ 0x22, 0xF0, 0x01, 0x74, 0x74, 0x6C, 0x07, 0x90, 0x30, 0xE0, 0xF0, 0x02, 0x08, 0x74, 0x0C, 0xE3, ++ 0xE3, 0x30, 0xE0, 0xF0, 0x44, 0x42, 0x85, 0x23, 0x07, 0x90, 0x1F, 0x80, 0xE0, 0x30, 0xE0, 0x6C, ++ 0xF0, 0x01, 0x74, 0x17, 0x97, 0x78, 0x42, 0x15, 0x70, 0x18, 0xE6, 0x06, 0x42, 0xE5, 0x06, 0x01, ++ 0x9D, 0x78, 0x06, 0x70, 0xF0, 0x91, 0x02, 0x76, 0x23, 0x06, 0x90, 0x22, 0x54, 0x13, 0x13, 0xE0, ++ 0x05, 0xE0, 0x30, 0x3F, 0x80, 0x04, 0x0D, 0x90, 0x24, 0x0D, 0x90, 0x03, 0xF0, 0x7F, 0x54, 0xE0, ++ 0xE6, 0x06, 0x95, 0x78, 0x06, 0x01, 0x70, 0x18, 0x71, 0x0A, 0x42, 0x75, 0x47, 0x07, 0x90, 0xFE, ++ 0xF0, 0x10, 0x44, 0xE0, 0xE0, 0x47, 0x08, 0x90, 0x90, 0xF0, 0x7F, 0x54, 0x01, 0x74, 0x49, 0x08, ++ 0x6C, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x09, 0x74, 0x44, 0xE0, 0x05, 0x08, 0x08, 0x90, 0xF0, 0x10, ++ 0xF0, 0x0D, 0x74, 0x27, 0xE0, 0x61, 0x08, 0x90, 0x02, 0x44, 0xF0, 0x54, 0xF9, 0x01, 0x90, 0xF0, ++ 0xC4, 0xF0, 0x54, 0xE0, 0x90, 0xFF, 0x0F, 0x54, 0x54, 0xE0, 0x3D, 0x08, 0xE4, 0xF0, 0x4F, 0xE0, ++ 0xF0, 0x06, 0x08, 0x90, 0xE0, 0x07, 0x08, 0x90, 0x01, 0x44, 0xFC, 0x54, 0x6D, 0x07, 0x90, 0xF0, ++ 0xF0, 0xF7, 0x54, 0xE0, 0xA8, 0x07, 0x90, 0xE4, 0x2D, 0x3E, 0x75, 0xF0, 0x22, 0xD1, 0x3F, 0x75, ++ 0x75, 0x2C, 0x3E, 0x75, 0x08, 0x90, 0xF0, 0x3F, 0x01, 0x44, 0xE0, 0x05, 0x10, 0x44, 0xE0, 0xF0, ++ 0xEA, 0x01, 0x90, 0xF0, 0x03, 0x70, 0xF4, 0xE0, 0x60, 0xF4, 0xE0, 0xA3, 0xEB, 0x01, 0x90, 0x0E, ++ 0x70, 0xF0, 0x04, 0xE0, 0xEA, 0x01, 0x90, 0x06, 0xC2, 0xF0, 0x04, 0xE0, 0x90, 0xEE, 0xC2, 0xEC, ++ 0xFF, 0x74, 0x68, 0x07, 0x6C, 0x07, 0x90, 0xF0, 0x48, 0x08, 0x90, 0xF0, 0x44, 0xF3, 0x54, 0xE0, ++ 0x08, 0x90, 0xF0, 0x04, 0x0F, 0x54, 0xE0, 0x4C, 0x90, 0xF0, 0x20, 0x44, 0x54, 0xE0, 0x4A, 0x08, ++ 0x08, 0x90, 0xF0, 0xF3, 0x70, 0x44, 0xE0, 0x4B, 0x47, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, ++ 0x6C, 0x07, 0x90, 0x22, 0x2A, 0xE0, 0x30, 0xE0, 0x01, 0x74, 0x42, 0x15, 0x70, 0x42, 0xE5, 0xF0, ++ 0x01, 0x90, 0xC3, 0x21, 0xFF, 0x94, 0xE0, 0x89, 0xE0, 0x88, 0x01, 0x90, 0x0C, 0x50, 0xFF, 0x94, ++ 0xF0, 0x04, 0xE0, 0xA3, 0x01, 0x90, 0x06, 0x70, 0xF0, 0x04, 0xE0, 0x88, 0x04, 0x76, 0x9D, 0x78, ++ 0x44, 0xE5, 0xF0, 0x81, 0x14, 0x47, 0x60, 0x14, 0x02, 0x24, 0x44, 0x60, 0x08, 0x90, 0x11, 0x70, ++ 0xE0, 0x54, 0xE0, 0x3D, 0x90, 0xF0, 0x03, 0x44, 0x01, 0x74, 0x2F, 0x08, 0x90, 0x2F, 0x80, 0xF0, ++ 0x0B, 0x74, 0x6C, 0x07, 0x24, 0x42, 0xE5, 0xF0, 0xC3, 0x43, 0xF5, 0x06, 0xE0, 0x89, 0x01, 0x90, ++ 0x01, 0x90, 0xFF, 0x94, 0xFF, 0x94, 0xE0, 0x88, 0x42, 0xE5, 0x12, 0x50, 0x0C, 0x50, 0x08, 0x94, ++ 0xF0, 0x04, 0xE0, 0xA3, 0x01, 0x90, 0x06, 0x70, 0xF0, 0x04, 0xE0, 0x88, 0x44, 0x05, 0x6F, 0x11, ++ 0x6C, 0x07, 0x90, 0x22, 0x2C, 0xE3, 0x30, 0xE0, 0xE0, 0x07, 0x08, 0x90, 0x90, 0xF0, 0xFC, 0x54, ++ 0x90, 0xE0, 0xFC, 0x01, 0x90, 0xF0, 0x6C, 0x08, 0x05, 0x74, 0x67, 0x08, 0x60, 0x08, 0x90, 0xF0, ++ 0xE4, 0xF0, 0x01, 0x74, 0x3E, 0x75, 0x44, 0xF5, 0x51, 0x3F, 0x75, 0x2D, 0xE0, 0x6D, 0x07, 0x90, ++ 0x22, 0xF0, 0xF7, 0x54, 0xE0, 0x6C, 0x07, 0x90, 0x15, 0x0F, 0xE0, 0x30, 0xF0, 0x01, 0x74, 0x42, ++ 0x06, 0x70, 0x42, 0xE5, 0x03, 0x76, 0x9D, 0x78, 0x22, 0x22, 0xF0, 0x91, 0x00, 0x00, 0x00, 0x00, ++ 0xE0, 0x44, 0x07, 0x90, 0xE4, 0x0C, 0xE5, 0x30, 0xF0, 0xB4, 0x01, 0x90, 0x33, 0xA9, 0x32, 0xAA, ++ 0xE5, 0x3B, 0x03, 0x02, 0xE4, 0x05, 0x60, 0x3A, 0x33, 0xF5, 0x32, 0xF5, 0x3A, 0x31, 0x50, 0x22, ++ 0x30, 0x30, 0x31, 0x09, 0x0A, 0x58, 0x54, 0x62, 0x3A, 0x31, 0x50, 0x00, 0x74, 0x65, 0x53, 0x09, ++ 0x00, 0x0A, 0x70, 0x75, 0x09, 0x3A, 0x31, 0x50, 0x74, 0x69, 0x61, 0x57, 0x50, 0x00, 0x0A, 0x50, ++ 0x09, 0x09, 0x3A, 0x31, 0x00, 0x49, 0x44, 0x4D, 0x00, 0x0A, 0x00, 0x58, 0x09, 0x3A, 0x31, 0x50, ++ 0x0A, 0x43, 0x47, 0x41, 0x3A, 0x31, 0x50, 0x00, 0x47, 0x41, 0x09, 0x09, 0x64, 0x25, 0x3D, 0x43, ++ 0x57, 0x50, 0x00, 0x20, 0x64, 0x25, 0x3D, 0x52, 0x31, 0x50, 0x00, 0x0A, 0x4B, 0x4F, 0x09, 0x3A, ++ 0x50, 0x00, 0x0A, 0x30, 0x09, 0x09, 0x3A, 0x31, 0x20, 0x3A, 0x43, 0x4C, 0x00, 0x0A, 0x64, 0x25, ++ 0x09, 0x3A, 0x31, 0x50, 0x0A, 0x31, 0x4B, 0x4F, 0x3A, 0x31, 0x50, 0x00, 0x32, 0x4B, 0x4F, 0x09, ++ 0x31, 0x50, 0x00, 0x0A, 0x4B, 0x4F, 0x09, 0x3A, 0x50, 0x00, 0x0A, 0x33, 0x4F, 0x09, 0x3A, 0x31, ++ 0x50, 0x0A, 0x34, 0x4B, 0x09, 0x09, 0x3A, 0x31, 0x00, 0x64, 0x25, 0x00, 0x09, 0x3A, 0x31, 0x50, ++ 0x63, 0x61, 0x72, 0x54, 0x50, 0x00, 0x0A, 0x6B, 0x53, 0x09, 0x3A, 0x31, 0x0A, 0x63, 0x6E, 0x79, ++ 0x3A, 0x31, 0x50, 0x00, 0x77, 0x6F, 0x44, 0x09, 0x25, 0x3A, 0x00, 0x6E, 0x50, 0x00, 0x0A, 0x78, ++ 0x45, 0x09, 0x3A, 0x31, 0x0A, 0x74, 0x69, 0x78, 0x3A, 0x31, 0x50, 0x00, 0x44, 0x4D, 0x09, 0x09, ++ 0x25, 0x3D, 0x4C, 0x4C, 0xE5, 0x00, 0x0A, 0x64, 0x7E, 0x2A, 0x60, 0x3A, 0x12, 0x1D, 0x7F, 0x20, ++ 0x38, 0x75, 0x1B, 0x10, 0x8F, 0x39, 0x75, 0x21, 0xE4, 0x01, 0x3B, 0x75, 0x08, 0xF6, 0xA4, 0x78, ++ 0x78, 0xF6, 0x08, 0xF6, 0xA9, 0x78, 0xF6, 0xAB, 0x12, 0xFF, 0x03, 0x76, 0xA2, 0x78, 0xED, 0x03, ++ 0x76, 0x08, 0xAA, 0x76, 0xE6, 0xA4, 0x78, 0xE6, 0x31, 0x16, 0x01, 0x60, 0x40, 0x06, 0x90, 0x6E, ++ 0x54, 0xC4, 0xFF, 0xE0, 0x19, 0xE0, 0x30, 0x0F, 0xE0, 0x43, 0x06, 0x90, 0x54, 0x13, 0x13, 0xFF, ++ 0x0D, 0xE0, 0x20, 0x3F, 0x11, 0x12, 0xA2, 0x7F, 0x75, 0x06, 0x50, 0x3A, 0x39, 0x75, 0x2C, 0x38, ++ 0x12, 0x10, 0xD2, 0x29, 0x06, 0x50, 0x4F, 0x11, 0x75, 0x2C, 0x38, 0x75, 0x37, 0xE5, 0x29, 0x39, ++ 0x04, 0x70, 0x39, 0x65, 0x38, 0x65, 0x36, 0xE5, 0x38, 0x85, 0x09, 0x60, 0x37, 0x39, 0x85, 0x36, ++ 0xAA, 0x01, 0x3B, 0x75, 0x12, 0x37, 0xA9, 0x36, 0xF5, 0xE4, 0x3B, 0x03, 0xB1, 0x78, 0x22, 0x3B, ++ 0xFF, 0x01, 0x54, 0xE6, 0x74, 0x9F, 0xE4, 0xC3, 0x54, 0x00, 0x94, 0x08, 0xE6, 0x18, 0xFC, 0x05, ++ 0x08, 0xFE, 0x13, 0xC3, 0xEE, 0xFF, 0x13, 0xE6, 0xEF, 0xF6, 0x18, 0x6C, 0xE5, 0x22, 0xF6, 0x08, ++ 0x7E, 0x09, 0x60, 0x3B, 0x12, 0x29, 0x7F, 0x20, 0x1F, 0x91, 0x1B, 0x10, 0x38, 0x75, 0xA5, 0x31, ++ 0x58, 0x39, 0x75, 0x22, 0x63, 0x06, 0x90, 0x22, 0x13, 0x13, 0xFF, 0xE0, 0x92, 0x13, 0x3F, 0x54, ++ 0x67, 0x06, 0x90, 0x10, 0x03, 0xE0, 0x30, 0xE0, 0x90, 0x1A, 0x10, 0x30, 0x20, 0xE0, 0x67, 0x06, ++ 0x06, 0x90, 0x49, 0xE0, 0xA3, 0xFE, 0xE0, 0x66, 0xCE, 0x02, 0x78, 0xE0, 0x13, 0xCE, 0x13, 0xC3, ++ 0xE0, 0x20, 0xF9, 0xD8, 0x90, 0x10, 0xC2, 0x36, 0x0F, 0x74, 0x41, 0x0D, 0x61, 0x0D, 0x90, 0xF0, ++ 0x07, 0x90, 0xF0, 0x04, 0x3F, 0x54, 0xE0, 0xF9, 0xE0, 0xF0, 0x80, 0x44, 0x90, 0xF0, 0x30, 0x44, ++ 0x44, 0xE0, 0xFA, 0x07, 0x54, 0xE0, 0xF0, 0xC0, 0xF0, 0x20, 0x44, 0xCF, 0x74, 0x4C, 0x0D, 0x90, ++ 0x0D, 0x90, 0xF0, 0x38, 0x01, 0x90, 0xF0, 0x6C, 0xD2, 0x34, 0x80, 0xAC, 0x61, 0x0D, 0x90, 0x10, ++ 0x90, 0xF0, 0x0F, 0x74, 0xF0, 0x04, 0x41, 0x0D, 0xE0, 0xF9, 0x07, 0x90, 0xE0, 0xF0, 0xC0, 0x44, ++ 0x20, 0x44, 0xCF, 0x54, 0xFA, 0x07, 0x90, 0xF0, 0x44, 0x3F, 0x54, 0xE0, 0x44, 0xE0, 0xF0, 0x80, ++ 0x0D, 0x90, 0xF0, 0x30, 0xF0, 0x38, 0x74, 0x6C, 0xF0, 0x4C, 0x0D, 0x90, 0xE0, 0xAD, 0x01, 0x90, ++ 0xF0, 0x74, 0x09, 0x90, 0x33, 0xE4, 0x10, 0xA2, 0xE0, 0x25, 0x01, 0x54, 0x90, 0xFF, 0xE0, 0x25, ++ 0x54, 0xE0, 0x63, 0x06, 0x22, 0xF0, 0x4F, 0xFB, 0x02, 0x70, 0x3B, 0xE5, 0x20, 0x7E, 0xE0, 0x41, ++ 0x10, 0x12, 0x34, 0x7F, 0x40, 0x0D, 0x90, 0x1B, 0xF0, 0xF8, 0x54, 0xE0, 0xE0, 0x60, 0x0D, 0x90, ++ 0x78, 0xF0, 0xF8, 0x54, 0x08, 0xF4, 0x76, 0xAE, 0x0D, 0x90, 0x24, 0x76, 0x54, 0xC4, 0xE0, 0xAA, ++ 0x0D, 0x90, 0xFF, 0x0F, 0x54, 0xC4, 0xE0, 0xAB, 0xE4, 0xFF, 0x2F, 0x0F, 0x00, 0x24, 0xCF, 0x33, ++ 0x04, 0x34, 0xEF, 0xFD, 0x0C, 0x07, 0x90, 0xFC, 0x20, 0xF0, 0x75, 0xE0, 0x45, 0xEC, 0xFF, 0xA4, ++ 0xED, 0xF6, 0x08, 0xF0, 0xE4, 0xF6, 0x08, 0x4F, 0x90, 0xF6, 0xAA, 0x78, 0xC0, 0x74, 0xA9, 0x0D, ++ 0x76, 0x09, 0x90, 0xF0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0x08, 0x44, 0xE0, 0xE0, 0x77, 0x09, 0x90, ++ 0x04, 0x44, 0xF3, 0x54, 0x7B, 0x09, 0x90, 0xF0, 0x44, 0x0F, 0x54, 0xE0, 0x09, 0x90, 0xF0, 0x20, ++ 0x70, 0x44, 0xE0, 0x7A, 0x80, 0x44, 0xE0, 0xF0, 0x76, 0x09, 0x90, 0xF0, 0xF0, 0xF7, 0x54, 0xE0, ++ 0xE0, 0x40, 0x06, 0x90, 0x30, 0x0F, 0x54, 0xC4, 0xA5, 0x31, 0x04, 0xE0, 0x06, 0x90, 0x1E, 0x80, ++ 0xE0, 0x20, 0xE0, 0x67, 0x13, 0x13, 0xE0, 0x20, 0x90, 0xFF, 0x01, 0x54, 0xFE, 0xE0, 0x63, 0x06, ++ 0x01, 0x54, 0x13, 0x13, 0x90, 0x05, 0x60, 0x6F, 0xA8, 0x31, 0x67, 0x06, 0xF4, 0x76, 0xAE, 0x78, ++ 0x80, 0x24, 0x76, 0x08, 0x12, 0xAE, 0x7F, 0x5B, 0x54, 0x50, 0x3A, 0x11, 0xF4, 0x76, 0xAE, 0x78, ++ 0x90, 0x24, 0x76, 0x08, 0xC3, 0xE0, 0x7E, 0x09, 0x24, 0x50, 0x05, 0x94, 0x54, 0xE6, 0xB1, 0x78, ++ 0x06, 0x90, 0xFF, 0x01, 0x13, 0xFD, 0xE0, 0x63, 0x6F, 0x01, 0x54, 0x13, 0x60, 0xE4, 0x01, 0x70, ++ 0x75, 0x06, 0x90, 0x07, 0xF0, 0x08, 0x44, 0xE0, 0x13, 0xE6, 0xB1, 0x78, 0xB1, 0x31, 0x10, 0x92, ++ 0x3F, 0x7F, 0x20, 0x7E, 0x90, 0x1B, 0x10, 0x12, 0x13, 0xE0, 0x63, 0x06, 0x30, 0x3F, 0x54, 0x13, ++ 0x20, 0x7E, 0x07, 0xE0, 0x10, 0x12, 0x48, 0x7F, 0x7F, 0x20, 0x7E, 0x1B, 0x1B, 0x10, 0x12, 0x4A, ++ 0x06, 0x40, 0x7B, 0x71, 0x75, 0x28, 0x38, 0x75, 0x90, 0x22, 0x38, 0x39, 0xFF, 0xE0, 0x7E, 0x09, ++ 0x94, 0x80, 0x64, 0xD3, 0x78, 0x0C, 0x40, 0x85, 0x0A, 0x94, 0xE6, 0xAA, 0x80, 0x06, 0x03, 0x50, ++ 0xC3, 0x22, 0xC3, 0x0E, 0x94, 0x80, 0x64, 0xEF, 0xE4, 0x04, 0x50, 0x83, 0xD3, 0xF6, 0xAA, 0x78, ++ 0x7F, 0x20, 0x7E, 0x22, 0x1B, 0x10, 0x12, 0xC1, 0xCA, 0x7F, 0x20, 0x7E, 0xFD, 0xE6, 0xBE, 0x78, ++ 0x10, 0x12, 0x00, 0x7C, 0x01, 0x90, 0xE4, 0x28, 0x06, 0x90, 0xF0, 0xB1, 0xFB, 0x54, 0xE0, 0x43, ++ 0xA5, 0x78, 0xE4, 0xF0, 0x90, 0xF6, 0x08, 0xF6, 0x44, 0xE0, 0xE3, 0x07, 0x06, 0x90, 0xF0, 0x01, ++ 0x54, 0xC4, 0xE0, 0x40, 0x2F, 0xE0, 0x20, 0x0F, 0x54, 0x13, 0xC4, 0xE0, 0x27, 0xE0, 0x30, 0x07, ++ 0xE0, 0xA3, 0xFE, 0xE0, 0xC3, 0xCE, 0x06, 0x78, 0xD8, 0x13, 0xCE, 0x13, 0x17, 0xE0, 0x20, 0xF9, ++ 0xE0, 0x71, 0x06, 0x90, 0x54, 0x13, 0x13, 0xFF, 0x0B, 0xE0, 0x20, 0x3F, 0x11, 0x50, 0x7B, 0x71, ++ 0x75, 0x22, 0x38, 0x75, 0x78, 0x22, 0x58, 0x39, 0x60, 0x16, 0xE6, 0xA9, 0x40, 0x7B, 0x71, 0x0B, ++ 0x26, 0x38, 0x75, 0x07, 0x22, 0x69, 0x39, 0x75, 0x75, 0x2C, 0x38, 0x75, 0xE4, 0x22, 0x29, 0x39, ++ 0xF0, 0x41, 0x0D, 0x90, 0x74, 0x40, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x38, 0x0D, 0x90, 0xF0, 0x60, ++ 0xF0, 0xAA, 0x74, 0xA2, 0x74, 0x42, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x30, 0x0D, 0x90, 0xF0, 0x62, ++ 0xF0, 0x20, 0x74, 0x45, 0xF0, 0x65, 0x0D, 0x90, 0x74, 0x46, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x9C, ++ 0x0D, 0x90, 0xF0, 0x66, 0xF0, 0x89, 0x74, 0x4A, 0xF0, 0x6A, 0x0D, 0x90, 0x61, 0x0D, 0x90, 0xE4, ++ 0xF8, 0x07, 0x90, 0xF0, 0xF0, 0xFB, 0x54, 0xE0, 0xF0, 0x08, 0x44, 0xE0, 0x74, 0xFD, 0x07, 0x90, ++ 0x08, 0x90, 0xF0, 0x01, 0x8F, 0x54, 0xE0, 0x04, 0x90, 0xF0, 0x20, 0x44, 0x54, 0xE0, 0x10, 0x07, ++ 0xF0, 0x54, 0xC4, 0x0F, 0x34, 0x09, 0x90, 0x04, 0x10, 0x07, 0x90, 0xF0, 0x0F, 0x54, 0xC4, 0xE0, ++ 0x0F, 0x07, 0x90, 0xFF, 0xC4, 0x0F, 0x54, 0xE0, 0x90, 0x4F, 0xF0, 0x54, 0x90, 0xF0, 0x33, 0x09, ++ 0xC4, 0xE0, 0x0F, 0x07, 0x09, 0x90, 0x0F, 0x54, 0x09, 0x90, 0xF0, 0x32, 0xF0, 0x01, 0x74, 0x35, ++ 0x74, 0x2A, 0x09, 0x90, 0xF0, 0x14, 0xF0, 0x03, 0x04, 0x31, 0x09, 0x90, 0xF0, 0x01, 0x74, 0xF0, ++ 0x74, 0x8F, 0x09, 0x90, 0x01, 0x74, 0xF0, 0x03, 0x90, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x13, 0x74, ++ 0x03, 0x74, 0x91, 0x09, 0x92, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0xFA, 0x74, 0x03, 0x74, 0x96, 0x09, ++ 0xF0, 0x01, 0x74, 0xF0, 0xE0, 0x10, 0x07, 0x90, 0x54, 0xC4, 0x0F, 0x54, 0x09, 0x90, 0x04, 0xF0, ++ 0x07, 0x90, 0xF0, 0x99, 0x54, 0xC4, 0xE0, 0x10, 0x07, 0x90, 0xFF, 0x0F, 0x0F, 0x54, 0xE0, 0x0F, ++ 0x4F, 0xF0, 0x54, 0xC4, 0xF0, 0x98, 0x09, 0x90, 0xE0, 0x0F, 0x07, 0x90, 0x0F, 0x54, 0xC4, 0xFF, ++ 0xF0, 0x97, 0x09, 0x90, 0x74, 0x9A, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x01, 0xF0, 0x0B, 0x74, 0x81, ++ 0x74, 0x80, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x03, 0xF0, 0x0A, 0x74, 0x81, 0x74, 0x80, 0x09, 0x90, ++ 0x09, 0x90, 0xF0, 0x02, 0x09, 0x90, 0xF0, 0x68, 0x90, 0xF0, 0x04, 0x6F, 0x05, 0x74, 0x70, 0x09, ++ 0x71, 0x09, 0x90, 0xF0, 0x72, 0x09, 0x90, 0xF0, 0x74, 0xF0, 0x03, 0x74, 0x09, 0x90, 0xF0, 0x01, ++ 0xF0, 0x03, 0x74, 0x6D, 0x90, 0xF0, 0x01, 0x74, 0x03, 0x74, 0x6C, 0x09, 0x6B, 0x09, 0x90, 0xF0, ++ 0xF0, 0x01, 0x74, 0xF0, 0xF0, 0xC5, 0x07, 0x90, 0xE0, 0x70, 0x06, 0x90, 0x78, 0xE0, 0xA3, 0xFE, ++ 0x13, 0xC3, 0xCE, 0x03, 0xF9, 0xD8, 0x13, 0xCE, 0x33, 0x33, 0x01, 0x54, 0x44, 0x08, 0x54, 0x33, ++ 0xC6, 0x07, 0x90, 0x01, 0x6F, 0x06, 0x90, 0xF0, 0xC4, 0xC0, 0x54, 0xE0, 0x03, 0x54, 0x13, 0x13, ++ 0xC7, 0x07, 0x90, 0xFF, 0x4F, 0xFC, 0x54, 0xE0, 0xF1, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x15, 0x74, ++ 0xE4, 0xF0, 0xF2, 0x07, 0xDF, 0x07, 0x90, 0xF0, 0x07, 0x90, 0xF0, 0x04, 0x07, 0x90, 0xF0, 0xDE, ++ 0xF0, 0x03, 0x74, 0xE0, 0xF0, 0xE1, 0x07, 0x90, 0xDF, 0x07, 0x90, 0xE4, 0xE3, 0x07, 0x90, 0xF0, ++ 0x07, 0x90, 0xF0, 0x04, 0x07, 0x90, 0xF0, 0xE2, 0x07, 0x90, 0xF0, 0xE4, 0xF0, 0x03, 0x74, 0xE5, ++ 0xE3, 0x07, 0x90, 0xE4, 0x43, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x03, 0x74, 0x54, 0xE0, 0x41, 0x09, ++ 0xFD, 0xE4, 0xF0, 0xFE, 0xE0, 0x43, 0x09, 0x90, 0x0A, 0x60, 0x01, 0x64, 0xFF, 0x94, 0xC3, 0xED, ++ 0x0D, 0x00, 0x04, 0x50, 0x20, 0x7E, 0xEE, 0x80, 0x00, 0x7C, 0xD9, 0x7F, 0x90, 0x28, 0x10, 0x12, ++ 0x43, 0x74, 0x4B, 0x09, 0x4D, 0x09, 0x90, 0xF0, 0x4F, 0x09, 0x90, 0xF0, 0x51, 0x09, 0x90, 0xF0, ++ 0x38, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x03, 0x74, 0x90, 0xF0, 0x3A, 0x09, 0x90, 0xF0, 0x3B, 0x09, ++ 0xE4, 0xF0, 0x3C, 0x09, 0xBD, 0x0D, 0x00, 0xFD, 0x09, 0x90, 0xFB, 0x80, 0xF0, 0x42, 0x74, 0x4B, ++ 0xF0, 0x4D, 0x09, 0x90, 0xF0, 0x4F, 0x09, 0x90, 0xF0, 0x51, 0x09, 0x90, 0x74, 0x38, 0x09, 0x90, ++ 0x09, 0x90, 0xF0, 0x04, 0x09, 0x90, 0xF0, 0x3A, 0x09, 0x90, 0xF0, 0x3B, 0x09, 0x90, 0xF0, 0x3C, ++ 0x01, 0x44, 0xE0, 0x41, 0x53, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x12, 0x74, 0x0D, 0x74, 0xFB, 0x07, ++ 0x07, 0x07, 0x90, 0xF0, 0xF0, 0x10, 0x44, 0xE0, 0x60, 0x3B, 0xE5, 0x22, 0x7F, 0x20, 0x7E, 0x0D, ++ 0x1B, 0x10, 0x12, 0x6A, 0x05, 0x76, 0xA4, 0x78, 0x7B, 0x71, 0xBA, 0xD1, 0x38, 0x75, 0x07, 0x50, ++ 0xA1, 0x39, 0x75, 0x23, 0xE6, 0xA4, 0x78, 0x22, 0x09, 0x90, 0x2F, 0x70, 0xF0, 0x40, 0x74, 0x63, ++ 0x73, 0x7F, 0x20, 0x7E, 0x07, 0xC0, 0x06, 0xC0, 0xE0, 0x66, 0x09, 0x90, 0x67, 0x09, 0x90, 0xFE, ++ 0xFC, 0xEE, 0xFD, 0xE0, 0xD0, 0x07, 0xD0, 0xED, 0x28, 0x10, 0x12, 0x06, 0x75, 0x28, 0x38, 0x75, ++ 0xA7, 0x78, 0xAD, 0x39, 0x76, 0x08, 0x01, 0x76, 0xA4, 0x78, 0x22, 0xF4, 0x09, 0x90, 0x05, 0x76, ++ 0xF0, 0x03, 0x74, 0x54, 0xF0, 0x56, 0x09, 0x90, 0x74, 0x57, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x01, ++ 0xF0, 0x0F, 0x74, 0x56, 0x74, 0x58, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x04, 0x74, 0xF0, 0x14, 0x5C, ++ 0x09, 0x90, 0xF0, 0x07, 0xF0, 0x04, 0x74, 0x5D, 0x14, 0x5E, 0x09, 0x90, 0x5F, 0x09, 0x90, 0xF0, ++ 0x5E, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x17, 0x74, 0x59, 0x09, 0x5A, 0x09, 0x90, 0xF0, ++ 0x90, 0xF0, 0x15, 0x74, 0x04, 0x74, 0x60, 0x09, 0x62, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x40, 0x74, ++ 0x03, 0x74, 0x5B, 0x09, 0x54, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x0D, 0x74, 0x56, 0x09, ++ 0x5C, 0x09, 0x90, 0xF0, 0xE4, 0xF0, 0x05, 0x74, 0xF0, 0x60, 0x09, 0x90, 0x7F, 0x7A, 0xFF, 0x7B, ++ 0xF1, 0x01, 0x7F, 0xFD, 0x7A, 0x00, 0x7B, 0xB2, 0xFF, 0xFD, 0xE4, 0xEC, 0xB2, 0x78, 0xB2, 0xF1, ++ 0x08, 0xF0, 0x75, 0xE6, 0x74, 0xC3, 0xFF, 0xA4, 0xE4, 0xFD, 0x9F, 0xE0, 0xE6, 0xFC, 0xF0, 0x95, ++ 0xA4, 0x04, 0xF0, 0x75, 0x9F, 0xED, 0xC3, 0xFF, 0xF0, 0x95, 0xEC, 0xFF, 0xFA, 0x00, 0x7B, 0xEF, ++ 0x02, 0x7F, 0xFD, 0xE4, 0x00, 0x7B, 0xB2, 0xF1, 0x02, 0x7D, 0x40, 0x7A, 0xB2, 0xF1, 0xFF, 0xE4, ++ 0xE0, 0x59, 0x09, 0x90, 0x90, 0xF0, 0xFE, 0x54, 0x44, 0xE0, 0x76, 0x09, 0x44, 0xE0, 0xF0, 0x01, ++ 0x09, 0x90, 0xF0, 0x04, 0xFC, 0x54, 0xE0, 0x77, 0x90, 0xF0, 0x01, 0x44, 0x54, 0xE0, 0x7B, 0x09, ++ 0xF0, 0x04, 0x44, 0xF0, 0xE0, 0x7A, 0x09, 0x90, 0x06, 0x44, 0xF8, 0x54, 0x08, 0x44, 0xE0, 0xF0, ++ 0x79, 0x09, 0x90, 0xF0, 0x44, 0xFC, 0x54, 0xE0, 0x09, 0x90, 0xF0, 0x01, 0xFB, 0x54, 0xE0, 0x76, ++ 0x54, 0xEF, 0x22, 0xF0, 0xFF, 0x10, 0x44, 0x0F, 0x54, 0x33, 0xC4, 0xED, 0x09, 0x90, 0x4F, 0x60, ++ 0xFF, 0xEA, 0xF0, 0x63, 0xEF, 0x64, 0x09, 0x90, 0x65, 0x09, 0x90, 0xF0, 0x90, 0xE4, 0xF0, 0xEB, ++ 0x22, 0xF0, 0x63, 0x09, 0x48, 0x60, 0x3B, 0xE5, 0x92, 0x7F, 0x20, 0x7E, 0x78, 0x1B, 0x10, 0x12, ++ 0x90, 0x64, 0x76, 0xA4, 0x0D, 0x74, 0x56, 0x09, 0x7A, 0x09, 0x90, 0xF0, 0xF0, 0x07, 0x44, 0xE0, ++ 0xE0, 0x79, 0x09, 0x90, 0x90, 0xF0, 0x03, 0x44, 0x02, 0x74, 0x58, 0x09, 0x59, 0x09, 0x90, 0xF0, ++ 0x44, 0xE3, 0x54, 0xE0, 0x09, 0x90, 0xF0, 0x14, 0xF0, 0x02, 0x74, 0x5D, 0x74, 0x90, 0x09, 0x90, ++ 0x09, 0x90, 0xF0, 0x07, 0xF0, 0x03, 0x74, 0x91, 0xE0, 0x92, 0x09, 0x90, 0xF0, 0xFA, 0x74, 0xE4, ++ 0x50, 0x7B, 0x23, 0x12, 0x23, 0x38, 0x75, 0x07, 0x22, 0xA1, 0x39, 0x75, 0x70, 0xE6, 0xA4, 0x78, ++ 0x29, 0x38, 0x75, 0x06, 0x22, 0xFA, 0x39, 0x75, 0x1D, 0x60, 0x3B, 0xE5, 0x4C, 0x7F, 0x20, 0x7E, ++ 0x78, 0x1B, 0x10, 0x12, 0x78, 0x0A, 0x76, 0xA4, 0x90, 0x07, 0x76, 0xB2, 0x44, 0xE0, 0x40, 0x0D, ++ 0x0D, 0x90, 0xF0, 0x07, 0x07, 0x44, 0xE0, 0x60, 0xE6, 0xA4, 0x78, 0xF0, 0x0A, 0x76, 0x4E, 0x70, ++ 0xD3, 0xE6, 0xB2, 0x78, 0x23, 0x40, 0x00, 0x94, 0xE0, 0x7E, 0x09, 0x90, 0x40, 0x0A, 0x94, 0xD3, ++ 0x54, 0xE6, 0x16, 0x1A, 0x0D, 0x90, 0xFF, 0x07, 0xF8, 0x54, 0xE0, 0x40, 0x54, 0xE6, 0xF0, 0x4F, ++ 0x0D, 0x90, 0xFF, 0x07, 0xF8, 0x54, 0xE0, 0x60, 0x7E, 0x22, 0xF0, 0x4F, 0x78, 0x55, 0x7F, 0x20, ++ 0x7C, 0xFD, 0xE6, 0xB2, 0x28, 0x10, 0x12, 0x00, 0x62, 0x7F, 0x20, 0x7E, 0xE0, 0x7E, 0x09, 0x90, ++ 0x12, 0x00, 0x7C, 0xFD, 0x38, 0x75, 0x28, 0x10, 0x69, 0x39, 0x75, 0x26, 0x60, 0x3B, 0xE5, 0x22, ++ 0x7F, 0x20, 0x7E, 0x58, 0x1B, 0x10, 0x12, 0x80, 0x0A, 0x76, 0xA4, 0x78, 0x74, 0x56, 0x09, 0x90, ++ 0x09, 0x90, 0xF0, 0x0D, 0xF0, 0x04, 0x74, 0x58, 0xE0, 0x59, 0x09, 0x90, 0x10, 0x44, 0xE3, 0x54, ++ 0x02, 0x44, 0xE0, 0xF0, 0x5C, 0x09, 0x90, 0xF0, 0xF0, 0xFB, 0x54, 0xE0, 0x74, 0x5D, 0x09, 0x90, ++ 0x09, 0x90, 0xF0, 0x03, 0x01, 0x44, 0xE0, 0x5E, 0x60, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, ++ 0x74, 0xE0, 0x61, 0x09, 0x09, 0x90, 0xF0, 0xCD, 0xF0, 0x04, 0x74, 0x90, 0x14, 0x91, 0x09, 0x90, ++ 0x92, 0x09, 0x90, 0xF0, 0xFA, 0x74, 0xE4, 0xE0, 0x7B, 0x23, 0x12, 0xF0, 0xA7, 0x7F, 0x07, 0x40, ++ 0x50, 0x3A, 0x11, 0x12, 0x23, 0x38, 0x75, 0x07, 0x22, 0xA1, 0x39, 0x75, 0x70, 0xE6, 0xA4, 0x78, ++ 0x7D, 0x09, 0x90, 0x0F, 0x17, 0x94, 0xC3, 0xE0, 0x38, 0x75, 0x06, 0x50, 0x31, 0x39, 0x75, 0x29, ++ 0x60, 0x3B, 0xE5, 0x22, 0x7F, 0x20, 0x7E, 0x2C, 0x1B, 0x10, 0x12, 0x89, 0x14, 0x76, 0xA4, 0x78, ++ 0xE0, 0x59, 0x09, 0x90, 0x90, 0xF0, 0xFD, 0x54, 0x54, 0xE0, 0x5C, 0x09, 0x09, 0x90, 0xF0, 0xFB, ++ 0xFD, 0x54, 0xE0, 0x60, 0x90, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x07, 0x74, 0x03, 0x74, 0x91, 0x09, ++ 0x12, 0xAA, 0x31, 0xF0, 0x07, 0x40, 0x7B, 0x23, 0x11, 0x12, 0xA7, 0x7F, 0x75, 0x07, 0x50, 0x3A, ++ 0x39, 0x75, 0x23, 0x38, 0xA4, 0x78, 0x22, 0xA1, 0x90, 0x2E, 0x70, 0xE6, 0xC3, 0xE0, 0x7D, 0x09, ++ 0x08, 0x50, 0x0D, 0x94, 0x75, 0x27, 0x38, 0x75, 0x06, 0x80, 0xD4, 0x39, 0x75, 0x28, 0x38, 0x75, ++ 0x90, 0xE4, 0xAD, 0x39, 0xE0, 0xF0, 0x63, 0x09, 0x40, 0x44, 0x9F, 0x54, 0x66, 0x09, 0x90, 0xF0, ++ 0x75, 0x06, 0x70, 0xE0, 0x39, 0x75, 0x26, 0x38, 0x09, 0x90, 0x22, 0x69, 0xF0, 0x0D, 0x74, 0x56, ++ 0x54, 0xED, 0x02, 0x7D, 0x63, 0x09, 0x90, 0x0F, 0x66, 0x09, 0x90, 0xF0, 0x90, 0x56, 0xF5, 0xE0, ++ 0xF5, 0xE0, 0x67, 0x09, 0xFF, 0x56, 0xE5, 0x57, 0xFE, 0xE0, 0x95, 0x33, 0x9F, 0x57, 0xE5, 0xC3, ++ 0x56, 0xE5, 0x57, 0xF5, 0x90, 0x56, 0xF5, 0x9E, 0x44, 0xE0, 0x63, 0x09, 0x09, 0x90, 0xF0, 0x10, ++ 0xF0, 0x56, 0xE5, 0x64, 0xE5, 0x65, 0x09, 0x90, 0x90, 0xE4, 0xF0, 0x57, 0x0D, 0xF0, 0x63, 0x09, ++ 0x90, 0xBF, 0x0A, 0xBD, 0x05, 0x74, 0x56, 0x09, 0x3B, 0xE5, 0x22, 0xF0, 0x20, 0x7E, 0x3B, 0x60, ++ 0x10, 0x12, 0x9B, 0x7F, 0x76, 0xA4, 0x78, 0x1B, 0x69, 0x06, 0x90, 0x05, 0x54, 0x13, 0x13, 0xE0, ++ 0x50, 0xE0, 0x30, 0x3F, 0xE0, 0x42, 0x0D, 0x90, 0x30, 0x44, 0x8F, 0x54, 0x62, 0x0D, 0x90, 0xF0, ++ 0x44, 0x8F, 0x54, 0xE0, 0x0D, 0x90, 0xF0, 0x30, 0x8F, 0x54, 0xE0, 0x45, 0x90, 0xF0, 0x20, 0x44, ++ 0x54, 0xE0, 0x65, 0x0D, 0xF0, 0x20, 0x44, 0x8F, 0x69, 0x06, 0x90, 0x22, 0x13, 0x13, 0xFF, 0xE0, ++ 0xE0, 0x30, 0x3F, 0x54, 0xE4, 0x65, 0x51, 0x0D, 0x7E, 0xFD, 0x33, 0xFC, 0x12, 0xA9, 0x7F, 0x20, ++ 0xA4, 0x78, 0x28, 0x10, 0x7E, 0x0D, 0x70, 0xE6, 0x12, 0x4A, 0x7F, 0x20, 0x38, 0x75, 0x1B, 0x10, ++ 0xC5, 0x39, 0x75, 0x2A, 0x7E, 0x4A, 0x7F, 0x22, 0x7C, 0x46, 0x7D, 0x0D, 0x8F, 0x10, 0xD2, 0x0D, ++ 0xE0, 0x83, 0x8E, 0x82, 0xD3, 0x0F, 0x54, 0xC4, 0x36, 0x40, 0x06, 0x94, 0xE0, 0x7D, 0x09, 0x90, ++ 0x2E, 0x50, 0x19, 0x94, 0x83, 0x8C, 0x82, 0x8D, 0x54, 0xC4, 0xFD, 0xE0, 0x54, 0xED, 0xFC, 0x0F, ++ 0x14, 0xEC, 0xFD, 0x0F, 0x54, 0xC4, 0x0F, 0x54, 0x8F, 0xF0, 0x4D, 0xF0, 0xC4, 0xFF, 0xE0, 0x82, ++ 0xEF, 0xFE, 0x0F, 0x54, 0xEE, 0xFF, 0x0F, 0x54, 0xC4, 0x0F, 0x54, 0x14, 0xF0, 0x4F, 0xF0, 0x54, ++ 0x0D, 0x90, 0x10, 0xC2, 0x0D, 0x90, 0xE0, 0x46, 0x0D, 0x90, 0xF0, 0x66, 0x0D, 0x90, 0xE0, 0x4A, ++ 0x10, 0xA2, 0xF0, 0x6A, 0x7F, 0x20, 0x7E, 0x22, 0x1B, 0x10, 0x12, 0xAC, 0xE0, 0x7E, 0x09, 0x90, ++ 0xE4, 0xF6, 0xAB, 0x78, 0xF0, 0x58, 0x09, 0x90, 0xE0, 0x59, 0x09, 0x90, 0x08, 0x44, 0xE3, 0x54, ++ 0x5D, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x02, 0x74, 0x54, 0xE0, 0x5C, 0x09, 0x09, 0x90, 0xF0, 0xFB, ++ 0xF0, 0x07, 0x74, 0x90, 0x74, 0x91, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x05, 0x74, 0xE4, 0xE0, 0x92, ++ 0x23, 0x12, 0xF0, 0xFA, 0x75, 0x07, 0x50, 0x7B, 0x39, 0x75, 0x23, 0x38, 0x38, 0x75, 0x22, 0xA1, ++ 0x60, 0x39, 0x75, 0x2B, 0xE0, 0xFD, 0x01, 0x90, 0x90, 0xFF, 0x70, 0x54, 0x54, 0xE0, 0x7A, 0x09, ++ 0x90, 0xF0, 0x4F, 0x8F, 0x54, 0xE0, 0xFD, 0x01, 0x09, 0x90, 0xFF, 0x0C, 0xF3, 0x54, 0xE0, 0x79, ++ 0x01, 0x90, 0xF0, 0x4F, 0x09, 0x90, 0xE0, 0xFD, 0x06, 0xE0, 0x30, 0x7B, 0xF0, 0x0F, 0x54, 0xE0, ++ 0x54, 0xE0, 0x06, 0x80, 0xF0, 0x20, 0x44, 0x0F, 0xE0, 0xFD, 0x01, 0x90, 0x30, 0x77, 0x09, 0x90, ++ 0x54, 0xE0, 0x07, 0xE1, 0xF0, 0x08, 0x44, 0xF3, 0xF3, 0x54, 0xE0, 0x22, 0x22, 0xF0, 0x04, 0x44, ++ 0x02, 0x70, 0x3B, 0xE5, 0x20, 0x7E, 0x07, 0x81, 0x10, 0x12, 0xB7, 0x7F, 0xA9, 0x78, 0xE4, 0x1B, ++ 0x66, 0x06, 0x90, 0xF6, 0x54, 0x13, 0xC4, 0xE0, 0x60, 0xFE, 0x24, 0x07, 0x22, 0x70, 0x04, 0x1D, ++ 0x74, 0xC9, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x03, 0xF8, 0x54, 0xE0, 0xE4, 0x90, 0xF0, 0x02, 0x44, ++ 0x54, 0xE0, 0xE0, 0x07, 0xF0, 0x03, 0x44, 0xF8, 0x07, 0x90, 0x0D, 0x80, 0xF0, 0x01, 0x74, 0xC9, ++ 0x90, 0xE4, 0x05, 0x80, 0x90, 0xF0, 0xC9, 0x07, 0x3F, 0x74, 0xF1, 0x07, 0xF2, 0x07, 0x90, 0xF0, ++ 0x90, 0xF0, 0x2A, 0x74, 0x54, 0xE0, 0xE3, 0x07, 0x90, 0xE4, 0xF0, 0xFE, 0x90, 0xF0, 0xF2, 0x07, ++ 0xC4, 0xE0, 0xFD, 0x01, 0x54, 0x13, 0x13, 0x13, 0xFE, 0x01, 0x90, 0x01, 0xE0, 0x0E, 0xE0, 0x30, ++ 0x7E, 0x09, 0x90, 0xFF, 0xA4, 0xF0, 0x8F, 0xE0, 0x80, 0x04, 0xF0, 0xE5, 0x09, 0x90, 0xE0, 0x01, ++ 0x09, 0x90, 0xF0, 0x7C, 0xF3, 0x54, 0xE0, 0x77, 0x90, 0xF0, 0x04, 0x44, 0x54, 0xE0, 0x79, 0x09, ++ 0x09, 0x90, 0xF0, 0xF3, 0x0F, 0x54, 0xE0, 0x7B, 0x90, 0xF0, 0x20, 0x44, 0x44, 0xE0, 0x7A, 0x09, ++ 0x44, 0xE0, 0xF0, 0x70, 0x12, 0x22, 0xF0, 0x80, 0x07, 0x50, 0x7B, 0x23, 0x75, 0x23, 0x38, 0x75, ++ 0x75, 0x22, 0xA1, 0x39, 0x35, 0x75, 0x02, 0x34, 0x02, 0x30, 0x75, 0x83, 0x75, 0x15, 0x31, 0x75, ++ 0x39, 0x75, 0x23, 0x38, 0x01, 0x3A, 0x75, 0xA1, 0x7F, 0x20, 0x7E, 0x22, 0x1B, 0x10, 0x12, 0xCF, ++ 0x74, 0xFB, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x01, 0xF0, 0x3F, 0x74, 0xF2, 0xE0, 0xE3, 0x07, 0x90, ++ 0xE4, 0xF0, 0x01, 0x44, 0xF0, 0xB1, 0x01, 0x90, 0xE0, 0x43, 0x06, 0x90, 0xE0, 0xF0, 0xFB, 0x54, ++ 0xE4, 0xF0, 0xDF, 0x54, 0x90, 0xF6, 0x80, 0x78, 0x80, 0x74, 0x60, 0x06, 0xFF, 0x74, 0xA3, 0xF0, ++ 0x74, 0x09, 0x90, 0xF0, 0x75, 0xF0, 0xE4, 0xE0, 0x35, 0x75, 0x02, 0x34, 0x01, 0x30, 0x75, 0x56, ++ 0x22, 0xC5, 0x31, 0x75, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0xE0, 0x44, 0x07, 0x90, 0xE4, 0x0C, 0xE5, 0x30, 0xF0, 0xB4, 0x01, 0x90, 0x33, 0xA9, 0x32, 0xAA, ++ 0xE5, 0x3B, 0x03, 0x02, 0xE4, 0x05, 0x60, 0x3A, 0x33, 0xF5, 0x32, 0xF5, 0x3A, 0x31, 0x50, 0x22, ++ 0x74, 0x61, 0x44, 0x09, 0x50, 0x00, 0x0A, 0x61, 0x09, 0x09, 0x3A, 0x31, 0x43, 0x4C, 0x6F, 0x4C, ++ 0x0A, 0x78, 0x25, 0x00, 0x61, 0x46, 0x4C, 0x00, 0x20, 0x20, 0x6C, 0x69, 0x78, 0x25, 0x20, 0x3A, ++ 0x58, 0x52, 0x00, 0x0A, 0x54, 0x41, 0x54, 0x53, 0x25, 0x20, 0x3A, 0x45, 0x0A, 0x00, 0x0A, 0x78, ++ 0x09, 0x3A, 0x31, 0x50, 0x4B, 0x4F, 0x4C, 0x09, 0x25, 0x20, 0x3A, 0x20, 0x50, 0x00, 0x0A, 0x64, ++ 0x09, 0x09, 0x3A, 0x31, 0x20, 0x4C, 0x56, 0x4C, 0x64, 0x25, 0x20, 0x3A, 0x31, 0x50, 0x00, 0x0A, ++ 0x50, 0x09, 0x09, 0x3A, 0x3A, 0x20, 0x52, 0x57, 0x20, 0x44, 0x25, 0x20, 0x31, 0x50, 0x00, 0x0A, ++ 0x53, 0x09, 0x09, 0x3A, 0x3A, 0x20, 0x52, 0x4E, 0x20, 0x64, 0x25, 0x20, 0x00, 0x0A, 0x42, 0x64, ++ 0x09, 0x3A, 0x31, 0x50, 0x4F, 0x52, 0x46, 0x09, 0x25, 0x20, 0x3A, 0x20, 0x70, 0x70, 0x20, 0x44, ++ 0x50, 0x00, 0x0A, 0x6D, 0x09, 0x09, 0x3A, 0x31, 0x3A, 0x51, 0x45, 0x4C, 0x44, 0x25, 0x20, 0x00, ++ 0x50, 0x00, 0x0A, 0x00, 0x09, 0x09, 0x3A, 0x31, 0x3A, 0x45, 0x46, 0x44, 0x3A, 0x31, 0x50, 0x00, ++ 0x2D, 0x2D, 0x09, 0x09, 0x0A, 0x2D, 0x2D, 0x2D, 0x3A, 0x31, 0x50, 0x00, 0x78, 0x54, 0x09, 0x09, ++ 0x6B, 0x61, 0x57, 0x2D, 0x20, 0x20, 0x3A, 0x65, 0x00, 0x0A, 0x64, 0x25, 0x09, 0x3A, 0x31, 0x50, ++ 0x2D, 0x78, 0x54, 0x09, 0x65, 0x69, 0x75, 0x51, 0x25, 0x20, 0x3A, 0x74, 0x50, 0x00, 0x0A, 0x64, ++ 0x09, 0x09, 0x3A, 0x31, 0x57, 0x2D, 0x78, 0x52, 0x3A, 0x65, 0x6B, 0x61, 0x64, 0x25, 0x20, 0x20, ++ 0x31, 0x50, 0x00, 0x0A, 0x52, 0x09, 0x09, 0x3A, 0x75, 0x51, 0x2D, 0x78, 0x3A, 0x74, 0x65, 0x69, ++ 0x0A, 0x64, 0x25, 0x20, 0x3A, 0x31, 0x50, 0x00, 0x6F, 0x4C, 0x09, 0x09, 0x0A, 0x52, 0x43, 0x53, ++ 0x3A, 0x31, 0x50, 0x00, 0x6F, 0x4C, 0x09, 0x09, 0x50, 0x00, 0x0A, 0x53, 0x09, 0x09, 0x3A, 0x31, ++ 0x5F, 0x44, 0x41, 0x42, 0x0A, 0x47, 0x49, 0x53, 0x26, 0x1F, 0x18, 0x00, 0x4E, 0x41, 0x36, 0x2D, ++ 0x9A, 0x84, 0x70, 0x5E, 0xFF, 0xEA, 0xCD, 0xB3, 0x20, 0x14, 0x0D, 0x08, 0xC9, 0x7F, 0x50, 0x33, ++ 0x02, 0x70, 0x3A, 0xE5, 0x20, 0x7E, 0xD9, 0x21, 0x10, 0x12, 0x1D, 0x7F, 0x43, 0x06, 0x90, 0x1B, ++ 0xF0, 0x04, 0x44, 0xE0, 0x54, 0xE6, 0x80, 0x78, 0x33, 0xC4, 0xFC, 0x01, 0xE0, 0xFE, 0xE0, 0x54, ++ 0xF0, 0x4E, 0xDF, 0x54, 0xE0, 0x75, 0x06, 0x90, 0xEC, 0xF0, 0x01, 0x44, 0xE0, 0x25, 0xE0, 0x25, ++ 0x74, 0x06, 0x90, 0xFF, 0x4F, 0xFB, 0x54, 0xE0, 0xAC, 0x78, 0xE4, 0xF0, 0x78, 0xF6, 0x08, 0xF6, ++ 0xC2, 0x78, 0xF6, 0xAA, 0x2C, 0x49, 0x75, 0xF6, 0x75, 0x81, 0x4A, 0x75, 0x4C, 0x75, 0x27, 0x4B, ++ 0x6F, 0x07, 0x90, 0x57, 0xF0, 0x0C, 0x44, 0xE0, 0x74, 0x6E, 0x07, 0x90, 0x06, 0x90, 0xF0, 0x08, ++ 0xA3, 0xFE, 0xE0, 0x70, 0xCE, 0x02, 0x78, 0xE0, 0x13, 0xCE, 0x13, 0xC3, 0xE0, 0x30, 0xF9, 0xD8, ++ 0xE4, 0xEF, 0xD2, 0x16, 0x08, 0xF6, 0xB5, 0x78, 0x08, 0xF6, 0x08, 0xF6, 0x08, 0xF6, 0x08, 0xF6, ++ 0x08, 0xF6, 0x08, 0xF6, 0xD1, 0xF6, 0x08, 0xF6, 0x70, 0x06, 0x90, 0x3A, 0xE0, 0xA3, 0xFE, 0xE0, ++ 0xC3, 0xCE, 0x02, 0x78, 0xD8, 0x13, 0xCE, 0x13, 0x2C, 0xE0, 0x30, 0xF9, 0x70, 0xE6, 0xBD, 0x78, ++ 0xFF, 0x01, 0x90, 0x27, 0x54, 0x13, 0x13, 0xE0, 0x16, 0xE0, 0x20, 0x3F, 0xFE, 0xE6, 0xAC, 0x78, ++ 0xE4, 0xFF, 0xE6, 0x08, 0xFA, 0x7B, 0xFD, 0xFC, 0xF8, 0xF9, 0xFF, 0x7A, 0xFF, 0x02, 0x12, 0xC3, ++ 0xED, 0xD2, 0x06, 0x70, 0x01, 0x76, 0xBD, 0x78, 0xE0, 0xE1, 0x07, 0x90, 0x07, 0x90, 0x14, 0x60, ++ 0x01, 0x44, 0xE0, 0xDF, 0xE1, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x03, 0x74, 0x54, 0xE0, 0xDF, 0x07, ++ 0x01, 0x90, 0xF0, 0xFE, 0x02, 0x44, 0xE0, 0xB1, 0xFE, 0xE0, 0xF0, 0xFF, 0xE0, 0xDB, 0x07, 0x90, ++ 0x54, 0x13, 0x13, 0xC4, 0xC4, 0xEE, 0xFD, 0x01, 0xFE, 0x01, 0x54, 0x13, 0xFF, 0xDF, 0x54, 0xEF, ++ 0x01, 0x54, 0x4D, 0xEE, 0xE0, 0x54, 0x33, 0xC4, 0xB1, 0x01, 0x90, 0x4F, 0x90, 0xFF, 0xE0, 0xF0, ++ 0xC4, 0xE0, 0xDB, 0x07, 0xFE, 0x01, 0x54, 0x13, 0x13, 0x13, 0x13, 0xEF, 0xEF, 0xFD, 0x01, 0x54, ++ 0xED, 0xFF, 0xF7, 0x54, 0x33, 0x01, 0x54, 0x4E, 0xF8, 0x54, 0x33, 0x33, 0xB1, 0x01, 0x90, 0x4F, ++ 0x90, 0xFF, 0xE0, 0xF0, 0xC3, 0xE0, 0xDB, 0x07, 0xFE, 0x01, 0x54, 0x13, 0x01, 0x54, 0xC4, 0xEF, ++ 0xEF, 0x54, 0xEF, 0xFD, 0x54, 0x4E, 0xED, 0xFF, 0xF0, 0x54, 0xC4, 0x01, 0xB1, 0x01, 0x90, 0x4F, ++ 0xDB, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x62, 0x74, 0xFE, 0xE0, 0x70, 0x06, 0x02, 0x78, 0xE0, 0xA3, ++ 0xCE, 0x13, 0xC3, 0xCE, 0x20, 0xF9, 0xD8, 0x13, 0x09, 0x90, 0x0D, 0xE0, 0xBF, 0x78, 0xE0, 0x7D, ++ 0x7E, 0x09, 0x90, 0xF6, 0x71, 0xF6, 0x08, 0xE0, 0x70, 0x06, 0x90, 0xEB, 0xE0, 0xA3, 0xFE, 0xE0, ++ 0xC3, 0xCE, 0x02, 0x78, 0xD8, 0x13, 0xCE, 0x13, 0x05, 0xE0, 0x30, 0xF9, 0x80, 0x55, 0xF5, 0xE4, ++ 0xE4, 0xEF, 0xB1, 0x3F, 0x90, 0x55, 0xF5, 0x33, 0x40, 0x74, 0xC8, 0x09, 0x66, 0x09, 0x90, 0xF0, ++ 0x01, 0x94, 0xD3, 0xE0, 0x55, 0x75, 0x2A, 0x50, 0x7F, 0x20, 0x7E, 0x01, 0x1B, 0x10, 0x12, 0x27, ++ 0x31, 0x7F, 0x20, 0x7E, 0x07, 0xC0, 0x06, 0xC0, 0xE0, 0x66, 0x09, 0x90, 0x67, 0x09, 0x90, 0xFE, ++ 0x24, 0x00, 0x7C, 0xE0, 0x3E, 0xEC, 0xFD, 0x00, 0xD0, 0x07, 0xD0, 0xFC, 0x28, 0x10, 0x12, 0x06, ++ 0x11, 0x12, 0x10, 0xD2, 0xE5, 0x12, 0x40, 0x4F, 0x74, 0x0E, 0x70, 0x55, 0x70, 0x4C, 0x65, 0x56, ++ 0x65, 0x2B, 0x74, 0x04, 0x61, 0x02, 0x60, 0x4B, 0xC2, 0xED, 0xC2, 0xEA, 0x7F, 0x20, 0x7E, 0xEF, ++ 0x7C, 0x55, 0xAD, 0x35, 0x28, 0x10, 0x12, 0x00, 0x42, 0x7F, 0x20, 0x7E, 0x56, 0x7D, 0x2B, 0x7C, ++ 0x90, 0x28, 0x10, 0x12, 0x54, 0xE0, 0x47, 0x07, 0x54, 0xE0, 0xF0, 0xF7, 0x07, 0x90, 0xF0, 0xDF, ++ 0xF0, 0xFF, 0x74, 0x6A, 0xF0, 0x6E, 0x07, 0x90, 0xE0, 0x41, 0x0D, 0x90, 0x90, 0xF0, 0xDF, 0x54, ++ 0x54, 0xE0, 0x61, 0x0D, 0x0D, 0x90, 0xF0, 0xDF, 0x7F, 0x54, 0xE0, 0x44, 0x64, 0x0D, 0x90, 0xF0, ++ 0xF0, 0x7F, 0x54, 0xE0, 0xE0, 0x41, 0x0D, 0x90, 0x90, 0xF0, 0xEF, 0x54, 0x54, 0xE0, 0x61, 0x0D, ++ 0x09, 0x90, 0xF0, 0xEF, 0x02, 0x44, 0xE0, 0x81, 0x80, 0x09, 0x90, 0xF0, 0xF0, 0x02, 0x44, 0xE0, ++ 0xE0, 0x69, 0x06, 0x90, 0x90, 0xF0, 0xFE, 0x54, 0x54, 0xE0, 0x94, 0x01, 0x54, 0xE0, 0xF0, 0xFE, ++ 0x07, 0x90, 0xF0, 0xFD, 0xFE, 0x54, 0xE0, 0xF6, 0x05, 0x08, 0x90, 0xF0, 0xF0, 0x08, 0x44, 0xE0, ++ 0xF0, 0x80, 0x44, 0xE0, 0x74, 0xF7, 0x07, 0x90, 0x06, 0x90, 0xF0, 0x3C, 0xFB, 0x54, 0xE0, 0x43, ++ 0x75, 0x06, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0x7E, 0x7F, 0x02, 0x7E, 0x35, 0x8F, 0x34, 0x8E, ++ 0x33, 0x8F, 0x32, 0x8E, 0x75, 0x02, 0x30, 0x75, 0x30, 0x22, 0x0B, 0x31, 0xED, 0xA1, 0x02, 0x18, ++ 0xE6, 0x06, 0xAD, 0x78, 0x06, 0x01, 0x70, 0x18, 0x64, 0xE6, 0xAD, 0x78, 0x60, 0x46, 0x18, 0x01, ++ 0x90, 0xD8, 0x81, 0x02, 0xF5, 0xE0, 0x64, 0x08, 0x65, 0x08, 0x90, 0x57, 0xE5, 0x58, 0xF5, 0xE0, ++ 0x78, 0x57, 0xAE, 0x58, 0xE7, 0xA2, 0xCE, 0x06, 0xD8, 0x13, 0xCE, 0x13, 0x06, 0xAC, 0xFD, 0xF8, ++ 0x57, 0xAE, 0x58, 0xE5, 0xA2, 0xCE, 0x05, 0x78, 0x13, 0xCE, 0x13, 0xE7, 0xFF, 0x2D, 0xF8, 0xD8, ++ 0xEF, 0xFE, 0x3C, 0xEE, 0x58, 0xF5, 0x58, 0x25, 0xF5, 0x57, 0x35, 0xEE, 0xE6, 0xBF, 0x78, 0x57, ++ 0x7C, 0xED, 0x7D, 0xFF, 0x8F, 0x95, 0xD1, 0x21, 0x90, 0x58, 0xAF, 0x59, 0xF0, 0xEF, 0x60, 0x06, ++ 0x94, 0xD3, 0x59, 0xE5, 0x40, 0x59, 0xAF, 0x0E, 0xEF, 0x0E, 0x7F, 0x02, 0x54, 0xC4, 0x0F, 0x54, ++ 0x06, 0x90, 0xFF, 0xF0, 0x0F, 0x54, 0xE0, 0x61, 0x90, 0xE4, 0xF0, 0x4F, 0xE0, 0xF0, 0x63, 0x09, ++ 0x40, 0x44, 0x9F, 0x54, 0x66, 0x09, 0x90, 0xF0, 0x7E, 0x5A, 0xF5, 0xE0, 0x78, 0x4F, 0x7F, 0x20, ++ 0xE6, 0x06, 0x08, 0xA5, 0x70, 0x04, 0x86, 0x18, 0xFD, 0x14, 0x06, 0x01, 0x7E, 0x28, 0x10, 0x12, ++ 0xC0, 0x5F, 0x7F, 0x20, 0xE5, 0x07, 0xC0, 0x06, 0x09, 0x90, 0xFE, 0x5A, 0xEE, 0xFD, 0xE0, 0x67, ++ 0x07, 0xD0, 0xED, 0xFC, 0x10, 0x12, 0x06, 0xD0, 0x7F, 0x20, 0x7E, 0x28, 0xE6, 0xC0, 0x78, 0x6E, ++ 0xE0, 0x95, 0x33, 0xFD, 0x28, 0x10, 0x12, 0xFC, 0x7E, 0x7F, 0x20, 0x7E, 0x00, 0x7C, 0x59, 0xAD, ++ 0x7E, 0x28, 0x10, 0x12, 0xAD, 0x90, 0x7F, 0x20, 0x12, 0x57, 0xAC, 0x58, 0x5A, 0xE5, 0x28, 0x10, ++ 0x40, 0x01, 0x94, 0xD3, 0x22, 0xED, 0xA1, 0x02, 0x64, 0xE6, 0xAD, 0x78, 0x70, 0x46, 0x18, 0x02, ++ 0x7F, 0x20, 0x7E, 0x47, 0x1B, 0x10, 0x12, 0xA3, 0x63, 0x09, 0x90, 0xE4, 0x9F, 0x54, 0xE0, 0xF0, ++ 0x56, 0xF5, 0xE4, 0xF0, 0x0F, 0x54, 0x56, 0xE5, 0x63, 0x09, 0x90, 0xFF, 0x4F, 0xF0, 0x54, 0xE0, ++ 0x7F, 0x20, 0x7E, 0xF0, 0xC0, 0x06, 0xC0, 0xAD, 0x66, 0x09, 0x90, 0x07, 0x09, 0x90, 0xFE, 0xE0, ++ 0xED, 0xFD, 0xE0, 0x67, 0x07, 0xD0, 0x06, 0xAC, 0x10, 0x12, 0x06, 0xD0, 0xE5, 0x56, 0x05, 0x28, ++ 0x0A, 0x94, 0xC3, 0x56, 0x50, 0x80, 0xCE, 0x40, 0x64, 0xE6, 0xAD, 0x78, 0x70, 0x46, 0x18, 0x03, ++ 0x7F, 0x20, 0x7E, 0x50, 0x1B, 0x10, 0x12, 0xB3, 0x63, 0x09, 0x90, 0xE4, 0x9F, 0x54, 0xE0, 0xF0, ++ 0xE4, 0xF0, 0x20, 0x44, 0x56, 0xE5, 0x56, 0xF5, 0x90, 0xFF, 0x0F, 0x54, 0x54, 0xE0, 0x63, 0x09, ++ 0x7E, 0xF0, 0x4F, 0xF0, 0xC0, 0xAD, 0x7F, 0x20, 0x90, 0x07, 0xC0, 0x06, 0xFE, 0xE0, 0x66, 0x09, ++ 0xE0, 0x67, 0x09, 0x90, 0x06, 0xAC, 0xED, 0xFD, 0x06, 0xD0, 0x07, 0xD0, 0x05, 0x28, 0x10, 0x12, ++ 0xC3, 0x56, 0xE5, 0x56, 0xCE, 0x40, 0x08, 0x94, 0xB1, 0x7F, 0x20, 0x7E, 0x80, 0x1B, 0x10, 0x12, ++ 0xE6, 0xAD, 0x78, 0x6C, 0x46, 0x18, 0x04, 0x64, 0x06, 0x90, 0x63, 0x70, 0xA3, 0xFE, 0xE0, 0x70, ++ 0xCE, 0x02, 0x78, 0xE0, 0x13, 0xCE, 0x13, 0xC3, 0xE0, 0x30, 0xF9, 0xD8, 0x17, 0x10, 0x12, 0x50, ++ 0xC9, 0x7F, 0x20, 0x7E, 0xFC, 0xE6, 0xB9, 0x78, 0x12, 0xFD, 0xE6, 0x08, 0x20, 0x7E, 0x28, 0x10, ++ 0xBB, 0x78, 0xDC, 0x7F, 0xE6, 0x08, 0xFC, 0xE6, 0x28, 0x10, 0x12, 0xFD, 0xEF, 0x7F, 0x20, 0x7E, ++ 0xFC, 0xE6, 0xB5, 0x78, 0x12, 0xFD, 0xE6, 0x08, 0x21, 0x7E, 0x28, 0x10, 0xB7, 0x78, 0x02, 0x7F, ++ 0xE6, 0x08, 0xFC, 0xE6, 0x28, 0x10, 0x12, 0xFD, 0xE4, 0x17, 0x10, 0x12, 0x08, 0xF6, 0xB5, 0x78, ++ 0x08, 0xF6, 0x08, 0xF6, 0x08, 0xF6, 0x08, 0xF6, 0x08, 0xF6, 0x08, 0xF6, 0x90, 0x22, 0xC3, 0xF6, ++ 0xD3, 0xE0, 0xF4, 0x07, 0x06, 0x40, 0xA0, 0x94, 0x15, 0x7F, 0x21, 0x7E, 0x09, 0x90, 0x31, 0x80, ++ 0x94, 0xC3, 0xE0, 0x7E, 0x78, 0x0E, 0x50, 0x03, 0x94, 0x06, 0xE6, 0xAA, 0x7E, 0x0A, 0x40, 0x03, ++ 0x80, 0x21, 0x7F, 0x21, 0xAA, 0x78, 0xE4, 0x1A, 0x7D, 0x09, 0x90, 0xF6, 0x3C, 0x94, 0xD3, 0xE0, ++ 0xC2, 0x78, 0x12, 0x40, 0x94, 0xD3, 0x06, 0xE6, 0x7E, 0x0D, 0x40, 0x03, 0x12, 0x2B, 0x7F, 0x21, ++ 0x22, 0xD3, 0x1B, 0x10, 0xF6, 0xC2, 0x78, 0xE4, 0x07, 0x90, 0x22, 0xC3, 0x13, 0xC4, 0xE0, 0xFA, ++ 0x75, 0x03, 0x54, 0x13, 0x24, 0xA4, 0x20, 0xF0, 0xF0, 0xE5, 0xFF, 0x00, 0x07, 0xAD, 0x0D, 0x34, ++ 0x63, 0x09, 0x90, 0xFC, 0x90, 0xF0, 0x40, 0x74, 0x75, 0xE0, 0x66, 0x09, 0x85, 0xA4, 0x14, 0xF0, ++ 0x57, 0xF5, 0x56, 0xF0, 0x83, 0x8C, 0x82, 0x8D, 0x90, 0x07, 0x54, 0xE0, 0xFF, 0x93, 0x48, 0x21, ++ 0x56, 0xAC, 0x00, 0x7E, 0x02, 0x12, 0x57, 0xAD, 0x8F, 0x56, 0x8E, 0x98, 0xEF, 0xFF, 0xE4, 0x57, ++ 0x93, 0x39, 0x21, 0x90, 0xD3, 0x56, 0xE5, 0xFE, 0x0F, 0x04, 0x40, 0x9E, 0x90, 0xF0, 0x0E, 0xBF, ++ 0xF0, 0xEF, 0x61, 0x06, 0x8D, 0x5B, 0x8C, 0x22, 0xF5, 0xFB, 0xE4, 0x5C, 0xC3, 0x83, 0xF5, 0x82, ++ 0x94, 0x80, 0x64, 0xEF, 0x7F, 0x02, 0x50, 0x81, 0x64, 0xEF, 0xD3, 0x01, 0x40, 0xBF, 0x94, 0x80, ++ 0xEF, 0x3F, 0x7F, 0x02, 0xA4, 0x04, 0xF0, 0x75, 0xED, 0xF0, 0xAC, 0xFD, 0x0B, 0x09, 0xE7, 0x20, ++ 0xEC, 0xFD, 0xE0, 0x25, 0xF3, 0x80, 0xFC, 0x33, 0x05, 0xAF, 0xFA, 0xE4, 0x02, 0x12, 0x04, 0xAE, ++ 0xAD, 0x06, 0xAC, 0x98, 0x07, 0x78, 0xED, 0x07, 0xCE, 0x13, 0xC3, 0xCE, 0xFD, 0xF9, 0xD8, 0x13, ++ 0xEC, 0xC3, 0x06, 0xAC, 0x24, 0x40, 0x01, 0x94, 0xFF, 0x9A, 0x07, 0x74, 0x00, 0x7E, 0x01, 0x74, ++ 0x80, 0x08, 0x07, 0xA8, 0xCE, 0x33, 0xC3, 0x05, 0xF9, 0xD8, 0xCE, 0x33, 0x82, 0xF5, 0x82, 0x25, ++ 0xF5, 0x83, 0x35, 0xEE, 0x13, 0xC3, 0xEC, 0x83, 0xFD, 0x13, 0xED, 0xFC, 0xBA, 0x08, 0xBA, 0x0A, ++ 0x9B, 0x05, 0x74, 0xC3, 0xE4, 0xFE, 0xEF, 0xFF, 0x82, 0xF5, 0x82, 0x25, 0xF5, 0x83, 0x35, 0xEE, ++ 0x7D, 0x00, 0x7C, 0x83, 0xFE, 0x82, 0xAF, 0x06, 0x8E, 0x98, 0x02, 0x12, 0xD3, 0x82, 0x8F, 0x83, ++ 0x5C, 0x95, 0x82, 0xE5, 0x5B, 0x95, 0x83, 0xE5, 0xF5, 0xE4, 0x07, 0x40, 0x80, 0x82, 0xF5, 0x83, ++ 0x5C, 0xE5, 0xC3, 0x0D, 0x82, 0xF5, 0x82, 0x95, 0x83, 0x95, 0x5B, 0xE5, 0x83, 0xE5, 0x83, 0xF5, ++ 0x83, 0x75, 0x82, 0xF5, 0x90, 0x22, 0xFF, 0x00, 0xF5, 0xE0, 0x6E, 0x07, 0xF0, 0x54, 0xE5, 0x54, ++ 0x0A, 0x50, 0xEF, 0xB1, 0x10, 0x76, 0xBE, 0x78, 0x02, 0x56, 0x2B, 0x12, 0x54, 0xE5, 0x51, 0x28, ++ 0x02, 0x03, 0xE1, 0x20, 0x07, 0x90, 0x51, 0x28, 0x13, 0x13, 0xE0, 0xF3, 0xFF, 0x03, 0x54, 0x13, ++ 0x90, 0x0E, 0x03, 0xBF, 0x44, 0xE0, 0xF2, 0x07, 0x54, 0xE0, 0xF0, 0x08, 0x28, 0x02, 0xF0, 0xF7, ++ 0xF3, 0x07, 0x90, 0x51, 0x13, 0x13, 0x13, 0xE0, 0x01, 0x64, 0x03, 0x54, 0x28, 0x02, 0x03, 0x60, ++ 0x7D, 0x09, 0x90, 0x39, 0xF6, 0xBF, 0x78, 0xE0, 0xE0, 0x7E, 0x09, 0x90, 0x50, 0x75, 0xF6, 0x08, ++ 0xEA, 0x2A, 0x12, 0x06, 0xE0, 0x47, 0x07, 0x90, 0x90, 0xF0, 0x20, 0x44, 0x44, 0xE0, 0xDA, 0x07, ++ 0x01, 0x90, 0xF0, 0x01, 0x04, 0x44, 0xE0, 0x94, 0x01, 0x44, 0xE0, 0xF0, 0x76, 0x09, 0x90, 0xF0, ++ 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0xFD, 0x01, 0x90, 0x90, 0xFF, 0x70, 0x54, 0x54, 0xE0, 0x7A, 0x09, ++ 0x90, 0xF0, 0x4F, 0x8F, 0x54, 0xE0, 0xFD, 0x01, 0x09, 0x90, 0xFF, 0x0C, 0xF3, 0x54, 0xE0, 0x79, ++ 0x01, 0x90, 0xF0, 0x4F, 0x09, 0x90, 0xE0, 0xFD, 0x06, 0xE0, 0x30, 0x7B, 0xF0, 0x0F, 0x54, 0xE0, ++ 0x54, 0xE0, 0x06, 0x80, 0xF0, 0x20, 0x44, 0x0F, 0xE0, 0xFD, 0x01, 0x90, 0x30, 0x77, 0x09, 0x90, ++ 0x54, 0xE0, 0x08, 0xE1, 0xF0, 0x08, 0x44, 0xF3, 0x54, 0xE0, 0x06, 0x80, 0xF0, 0x04, 0x44, 0xF3, ++ 0xE0, 0x6F, 0x07, 0x90, 0x90, 0xF0, 0xFB, 0x54, 0x08, 0x74, 0x6E, 0x07, 0xFA, 0x01, 0x90, 0xF0, ++ 0xF7, 0x07, 0x90, 0xE0, 0x80, 0x6A, 0x11, 0xF0, 0xF3, 0x07, 0x90, 0x18, 0x13, 0x13, 0x13, 0xE0, ++ 0xBF, 0xFF, 0x03, 0x54, 0x07, 0x90, 0x0B, 0x02, 0x10, 0x44, 0xE0, 0xF6, 0xEF, 0x54, 0xE0, 0xF0, ++ 0x30, 0x54, 0xE5, 0xF0, 0xA5, 0x11, 0x13, 0xE0, 0xE0, 0x90, 0x09, 0x90, 0xBF, 0xFF, 0x0F, 0x54, ++ 0x07, 0x90, 0x07, 0x07, 0xDF, 0x54, 0xE0, 0x47, 0x09, 0x90, 0x22, 0xF0, 0x40, 0x44, 0xE0, 0x76, ++ 0x7F, 0x54, 0xE0, 0xF0, 0x6E, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x08, 0x74, 0x90, 0xE0, 0xFB, 0x01, ++ 0x75, 0xF0, 0x9B, 0x09, 0x4B, 0x75, 0x18, 0x4F, 0x4E, 0x4C, 0x75, 0x29, 0xE0, 0xF3, 0x07, 0x90, ++ 0x13, 0x13, 0x13, 0xFF, 0x0A, 0x60, 0x03, 0x54, 0x13, 0x13, 0x13, 0xE0, 0xBF, 0xFF, 0x03, 0x54, ++ 0xDB, 0x11, 0x02, 0x02, 0x8F, 0x09, 0x90, 0x22, 0x90, 0xF0, 0x01, 0x74, 0x54, 0xE0, 0x90, 0x09, ++ 0x07, 0x94, 0xC3, 0x0F, 0xFF, 0xE0, 0x0B, 0x50, 0xEF, 0xFE, 0xF0, 0x54, 0x4E, 0x0F, 0x54, 0x04, ++ 0x90, 0x09, 0x90, 0xF0, 0xC3, 0x0F, 0x54, 0xE0, 0x0E, 0x40, 0x06, 0x94, 0xE0, 0x59, 0x09, 0x90, ++ 0x90, 0xF0, 0xFE, 0x54, 0x54, 0xE0, 0x5C, 0x09, 0x90, 0x22, 0xF0, 0xFB, 0x44, 0xE0, 0xF6, 0x07, ++ 0x07, 0x90, 0xF0, 0x10, 0xFE, 0x54, 0xE0, 0xDA, 0x07, 0x90, 0xE4, 0xF0, 0x01, 0x90, 0xF0, 0xE3, ++ 0xFE, 0x54, 0xE0, 0x94, 0x8F, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x44, 0xE0, 0x6F, 0x07, ++ 0x09, 0x90, 0xF0, 0x04, 0x40, 0x44, 0xE0, 0x76, 0x80, 0x44, 0xE0, 0xF0, 0x77, 0x09, 0x90, 0xF0, ++ 0x44, 0xF3, 0x54, 0xE0, 0x09, 0x90, 0xF0, 0x04, 0x0F, 0x54, 0xE0, 0x7B, 0x90, 0xF0, 0x20, 0x44, ++ 0x54, 0xE0, 0x79, 0x09, 0x09, 0x90, 0xF0, 0xF3, 0x70, 0x44, 0xE0, 0x7A, 0x76, 0x09, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0x74, 0x6E, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x09, 0xEF, 0x54, 0xE0, 0xF6, ++ 0xF7, 0x07, 0x90, 0xF0, 0x75, 0xF0, 0x3C, 0x74, 0x4C, 0x75, 0x27, 0x4B, 0x07, 0x90, 0x22, 0x57, ++ 0xF0, 0x02, 0x74, 0x6E, 0x21, 0xE3, 0x30, 0xE0, 0xE0, 0x59, 0x09, 0x90, 0x90, 0xF0, 0x01, 0x44, ++ 0x44, 0xE0, 0x5C, 0x09, 0x09, 0x90, 0xF0, 0x04, 0xF0, 0x15, 0x74, 0x8F, 0x07, 0x90, 0xE1, 0x31, ++ 0xE3, 0x30, 0xE0, 0x6E, 0x80, 0x63, 0x51, 0x36, 0xF3, 0x07, 0x90, 0x32, 0x13, 0x13, 0x13, 0xE0, ++ 0xBF, 0xFF, 0x03, 0x54, 0x07, 0x90, 0x0D, 0x03, 0x08, 0x44, 0xE0, 0xF2, 0xF7, 0x54, 0xE0, 0xF0, ++ 0x90, 0x18, 0x80, 0xF0, 0xFF, 0xE0, 0xF3, 0x07, 0x54, 0x13, 0x13, 0x13, 0xE0, 0x0A, 0x60, 0x03, ++ 0x54, 0x13, 0x13, 0x13, 0x02, 0xBF, 0xFF, 0x03, 0x90, 0xDB, 0x11, 0x02, 0x30, 0xE0, 0x6E, 0x07, ++ 0x4F, 0x15, 0x2E, 0xE0, 0xE5, 0xF0, 0x01, 0x74, 0x50, 0x95, 0xD3, 0x4F, 0xA5, 0x11, 0x04, 0x40, ++ 0x09, 0x90, 0x14, 0x80, 0x01, 0x44, 0xE0, 0x59, 0x5C, 0x09, 0x90, 0xF0, 0xF0, 0x04, 0x44, 0xE0, ++ 0x74, 0x8F, 0x09, 0x90, 0x4F, 0xE5, 0xF0, 0x15, 0xBE, 0x78, 0x06, 0x70, 0x56, 0x71, 0x01, 0x76, ++ 0x76, 0x09, 0x90, 0x22, 0xF0, 0x80, 0x44, 0xE0, 0x74, 0x56, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x0F, ++ 0xF0, 0x03, 0x74, 0x5E, 0x74, 0x5C, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x07, 0xF0, 0x03, 0x74, 0x54, ++ 0xE0, 0xF9, 0x01, 0x90, 0x33, 0xC4, 0x01, 0x54, 0x80, 0x54, 0x33, 0x33, 0x05, 0x08, 0x90, 0xFF, ++ 0x4F, 0x7F, 0x54, 0xE0, 0x54, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x05, 0x74, 0x5C, 0x09, ++ 0x56, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x0F, 0x74, 0x13, 0xE0, 0x63, 0x06, 0x30, 0x3F, 0x54, 0x13, ++ 0x0D, 0x90, 0x05, 0xE0, 0x90, 0x03, 0x80, 0x44, 0x44, 0xE0, 0x64, 0x0D, 0x4F, 0x75, 0xF0, 0x80, ++ 0x7C, 0x24, 0x7D, 0x60, 0x51, 0xFF, 0xE4, 0xF4, 0x47, 0x07, 0x90, 0xF0, 0xF0, 0x20, 0x44, 0xE0, ++ 0x74, 0xF2, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x2A, 0xF0, 0x08, 0x74, 0x6E, 0x75, 0x2B, 0x4B, 0x75, ++ 0x90, 0x22, 0x21, 0x4C, 0x13, 0xE0, 0x63, 0x06, 0x30, 0x3F, 0x54, 0x13, 0x0D, 0x90, 0x05, 0xE0, ++ 0x90, 0x03, 0x80, 0x44, 0x54, 0xE0, 0x64, 0x0D, 0xB6, 0x78, 0xF0, 0x7F, 0x70, 0x18, 0xE6, 0x06, ++ 0x4F, 0x75, 0x06, 0x01, 0x90, 0xEA, 0x51, 0x0A, 0x44, 0xE0, 0x47, 0x07, 0x09, 0x90, 0xF0, 0x20, ++ 0x7F, 0x54, 0xE0, 0x76, 0x78, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x09, 0x74, 0x6E, 0x07, ++ 0x05, 0x08, 0x90, 0xF0, 0xF0, 0x80, 0x44, 0xE0, 0x74, 0x56, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x0D, ++ 0xF0, 0x54, 0xE0, 0x90, 0x90, 0xF0, 0x02, 0x44, 0x54, 0xE0, 0xF9, 0x01, 0x0F, 0x54, 0xC4, 0xF0, ++ 0x6C, 0x09, 0x90, 0xFF, 0x4F, 0xE0, 0x54, 0xE0, 0x08, 0x90, 0xE4, 0xF0, 0x08, 0x90, 0xF0, 0x06, ++ 0x3F, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x80, 0x44, 0x54, 0xE0, 0x6F, 0x07, 0x90, 0xE4, 0xF0, 0xF7, ++ 0x75, 0xF0, 0xF2, 0x07, 0x4C, 0x75, 0x2C, 0x4B, 0xC4, 0x7D, 0x22, 0x37, 0xFF, 0xE4, 0x09, 0x7C, ++ 0xE0, 0x47, 0x07, 0x90, 0xEF, 0xF0, 0xDF, 0x54, 0x33, 0xC4, 0x01, 0x54, 0x90, 0xFF, 0xE0, 0x54, ++ 0x54, 0xE0, 0x48, 0x07, 0xE4, 0xF0, 0x4F, 0xDF, 0xF0, 0x5E, 0x07, 0x90, 0xF0, 0x5D, 0x07, 0x90, ++ 0x60, 0x07, 0x90, 0xED, 0x07, 0x90, 0xEC, 0xF0, 0x07, 0x90, 0xF0, 0x5F, 0xF0, 0x01, 0x74, 0x6E, ++ 0x6E, 0x07, 0x90, 0x22, 0xE0, 0xF0, 0x02, 0x74, 0x74, 0x0C, 0xE3, 0x30, 0x30, 0xE0, 0xF0, 0x08, ++ 0x4F, 0x85, 0x23, 0xE3, 0x90, 0x63, 0x41, 0x51, 0x30, 0xE0, 0x6E, 0x07, 0x01, 0x74, 0x17, 0xE0, ++ 0x78, 0x4F, 0x15, 0xF0, 0x18, 0xE6, 0x06, 0xB8, 0xE5, 0x06, 0x01, 0x70, 0x78, 0x06, 0x70, 0x4F, ++ 0x71, 0x02, 0x76, 0xBE, 0x4B, 0x75, 0x22, 0x56, 0x56, 0x4C, 0x75, 0x2B, 0xE0, 0x05, 0x08, 0x90, ++ 0xE0, 0xF0, 0x08, 0x44, 0x90, 0xF0, 0x80, 0x44, 0xF4, 0xE0, 0xEC, 0x01, 0xE0, 0xA3, 0x03, 0x70, ++ 0x90, 0x0E, 0x60, 0xF4, 0x04, 0xE0, 0xED, 0x01, 0x90, 0x06, 0x70, 0xF0, 0x04, 0xE0, 0xEC, 0x01, ++ 0xC2, 0xED, 0xC2, 0xF0, 0x6A, 0x07, 0x90, 0xEF, 0x90, 0xF0, 0xFF, 0x74, 0x90, 0xF0, 0x6E, 0x07, ++ 0x54, 0xE0, 0x77, 0x09, 0xF0, 0x04, 0x44, 0xF3, 0xE0, 0x7B, 0x09, 0x90, 0x20, 0x44, 0x0F, 0x54, ++ 0x79, 0x09, 0x90, 0xF0, 0xF0, 0xF3, 0x54, 0xE0, 0xE0, 0x7A, 0x09, 0x90, 0x90, 0xF0, 0x70, 0x44, ++ 0x44, 0xE0, 0x76, 0x09, 0x90, 0x22, 0xF0, 0x01, 0x30, 0xE0, 0x6E, 0x07, 0x4F, 0x15, 0x2A, 0xE0, ++ 0xE5, 0xF0, 0x01, 0x74, 0xC3, 0x21, 0x70, 0x4F, 0xE0, 0x99, 0x01, 0x90, 0x01, 0x90, 0xFF, 0x94, ++ 0xFF, 0x94, 0xE0, 0x98, 0xE0, 0xA3, 0x0C, 0x50, 0x06, 0x70, 0xF0, 0x04, 0xE0, 0x98, 0x01, 0x90, ++ 0xBE, 0x78, 0xF0, 0x04, 0x56, 0x61, 0x04, 0x76, 0x60, 0x14, 0x51, 0xE5, 0x44, 0x60, 0x14, 0x47, ++ 0x11, 0x70, 0x02, 0x24, 0xE0, 0x6C, 0x09, 0x90, 0x03, 0x44, 0xE0, 0x54, 0x5E, 0x09, 0x90, 0xF0, ++ 0x80, 0xF0, 0x01, 0x74, 0x6E, 0x07, 0x90, 0x2F, 0xE5, 0xF0, 0x0B, 0x74, 0xF5, 0x06, 0x24, 0x4F, ++ 0x01, 0x90, 0xC3, 0x50, 0xFF, 0x94, 0xE0, 0x99, 0xE0, 0x98, 0x01, 0x90, 0x12, 0x50, 0xFF, 0x94, ++ 0x08, 0x94, 0x4F, 0xE5, 0xE0, 0xA3, 0x0C, 0x50, 0x06, 0x70, 0xF0, 0x04, 0xE0, 0x98, 0x01, 0x90, ++ 0x6A, 0x11, 0xF0, 0x04, 0x90, 0x22, 0x51, 0x05, 0x30, 0xE0, 0x6E, 0x07, 0x08, 0x90, 0x2C, 0xE3, ++ 0x3F, 0x54, 0xE0, 0x07, 0xFC, 0x01, 0x90, 0xF0, 0x9B, 0x09, 0x90, 0xE0, 0x96, 0x09, 0x90, 0xF0, ++ 0x90, 0xF0, 0x05, 0x74, 0x01, 0x74, 0x8F, 0x09, 0x51, 0xF5, 0xE4, 0xF0, 0x75, 0x2B, 0x4B, 0x75, ++ 0x07, 0x90, 0xB7, 0x4C, 0xF7, 0x54, 0xE0, 0x6F, 0x07, 0x90, 0x22, 0xF0, 0xE0, 0x30, 0xE0, 0x6E, ++ 0x74, 0x4F, 0x15, 0x0F, 0x4F, 0xE5, 0xF0, 0x01, 0xBE, 0x78, 0x06, 0x70, 0x56, 0x71, 0x03, 0x76, ++ 0x6A, 0x07, 0x90, 0x22, 0xE0, 0xF0, 0xFF, 0x74, 0x90, 0x21, 0xE2, 0x30, 0x44, 0xE0, 0xF6, 0x07, ++ 0xAD, 0x91, 0xF0, 0x01, 0xE0, 0x47, 0x07, 0x90, 0x90, 0xF0, 0x08, 0x44, 0x44, 0xE0, 0x94, 0x01, ++ 0x44, 0xE0, 0xF0, 0x08, 0x49, 0x75, 0xF0, 0x02, 0xE5, 0x4A, 0x75, 0x2C, 0x7C, 0x50, 0x7D, 0x22, ++ 0x90, 0x01, 0x7F, 0xC3, 0x54, 0xE0, 0x47, 0x07, 0x54, 0xEF, 0xF0, 0xF7, 0x33, 0x33, 0x33, 0x01, ++ 0x90, 0xFF, 0xF8, 0x54, 0x54, 0xE0, 0x48, 0x07, 0xE4, 0xF0, 0x4F, 0xF7, 0xF0, 0x56, 0x07, 0x90, ++ 0xF0, 0x55, 0x07, 0x90, 0x58, 0x07, 0x90, 0xED, 0x07, 0x90, 0xEC, 0xF0, 0x07, 0x90, 0xF0, 0x57, ++ 0xF0, 0x01, 0x74, 0x6A, 0x6A, 0x07, 0x90, 0x22, 0xE0, 0xF0, 0x02, 0x74, 0x90, 0x0F, 0xE2, 0x20, ++ 0x54, 0xE0, 0x47, 0x07, 0x07, 0x90, 0xF0, 0xF7, 0xF0, 0x01, 0x74, 0x6A, 0x07, 0x90, 0x2B, 0x80, ++ 0xE0, 0x30, 0xE0, 0x6A, 0xF0, 0x01, 0x74, 0x05, 0x90, 0x22, 0x0B, 0xB1, 0xF5, 0xE0, 0x74, 0x09, ++ 0x7D, 0xF0, 0xE4, 0x4E, 0x7F, 0x04, 0x7C, 0xE2, 0x90, 0xB3, 0x91, 0x01, 0x44, 0xE0, 0x47, 0x07, ++ 0x49, 0x75, 0xF0, 0x08, 0x4D, 0x4A, 0x75, 0x2D, 0x90, 0xF6, 0xB1, 0x22, 0x54, 0xE0, 0xF6, 0x07, ++ 0x01, 0x90, 0xF0, 0xFE, 0xFD, 0x54, 0xE0, 0x94, 0x47, 0x07, 0x90, 0xF0, 0xF0, 0xF7, 0x54, 0xE0, ++ 0x74, 0x6A, 0x07, 0x90, 0x49, 0x75, 0xF0, 0x01, 0x81, 0x4A, 0x75, 0x2C, 0x6A, 0x07, 0x90, 0x22, ++ 0xE0, 0xF0, 0x02, 0x74, 0x90, 0x08, 0xE2, 0x20, 0x4E, 0xE5, 0x74, 0x09, 0x90, 0xCA, 0x80, 0xF0, ++ 0x30, 0xE0, 0x6A, 0x07, 0x01, 0x74, 0x05, 0xE0, 0x22, 0x6C, 0xB1, 0xF0, 0xE0, 0x63, 0x06, 0x90, ++ 0x3F, 0x54, 0x13, 0x13, 0x90, 0x05, 0xE0, 0x30, 0x03, 0x80, 0x64, 0x0D, 0xE0, 0x44, 0x0D, 0x90, ++ 0x90, 0xF0, 0x80, 0x44, 0x08, 0x74, 0x81, 0x09, 0x05, 0x08, 0x90, 0xF0, 0xF0, 0xF7, 0x54, 0xE0, ++ 0x90, 0x50, 0x4D, 0x75, 0x4E, 0xE5, 0x74, 0x09, 0x7C, 0x24, 0x7D, 0xF0, 0x91, 0xFF, 0xE4, 0xF4, ++ 0x47, 0x07, 0x90, 0xB3, 0xF0, 0x08, 0x44, 0xE0, 0x75, 0x2D, 0x49, 0x75, 0x90, 0x22, 0xAF, 0x4A, ++ 0x02, 0x74, 0x6A, 0x07, 0xE2, 0x20, 0xE0, 0xF0, 0x06, 0xBA, 0x78, 0x0A, 0x01, 0x70, 0x18, 0xE6, ++ 0x90, 0x29, 0xA1, 0x06, 0x30, 0xE0, 0x6A, 0x07, 0x01, 0x74, 0x2B, 0xE0, 0x06, 0xBC, 0x78, 0xF0, ++ 0x01, 0x70, 0x18, 0xE6, 0x15, 0x4D, 0xAF, 0x06, 0x19, 0x70, 0xEF, 0x4D, 0xAD, 0x91, 0xF6, 0xB1, ++ 0xE0, 0x47, 0x07, 0x90, 0x75, 0xF0, 0x08, 0x44, 0x4A, 0x75, 0x2C, 0x49, 0x06, 0xBA, 0x78, 0xE5, ++ 0x01, 0x70, 0x18, 0xE6, 0x06, 0x90, 0x22, 0x06, 0x13, 0x13, 0xE0, 0x63, 0xE0, 0x30, 0x3F, 0x54, ++ 0x64, 0x0D, 0x90, 0x05, 0x0D, 0x90, 0x03, 0x80, 0x7F, 0x54, 0xE0, 0x44, 0x81, 0x09, 0x90, 0xF0, ++ 0x90, 0xF0, 0x0A, 0x74, 0x44, 0xE0, 0x05, 0x08, 0x22, 0x22, 0xF0, 0x08, 0x00, 0x00, 0x00, 0x00, ++ 0xE0, 0x43, 0x07, 0x90, 0xE4, 0x0C, 0xE5, 0x30, 0xF0, 0xB3, 0x01, 0x90, 0x27, 0xA9, 0x26, 0xAA, ++ 0xE5, 0x3B, 0x03, 0x02, 0xE4, 0x05, 0x60, 0x2E, 0x27, 0xF5, 0x26, 0xF5, 0x3A, 0x30, 0x50, 0x22, ++ 0x09, 0x09, 0x09, 0x09, 0x25, 0x3A, 0x58, 0x52, 0x50, 0x00, 0x0A, 0x78, 0x09, 0x09, 0x3A, 0x30, ++ 0x25, 0x58, 0x54, 0x09, 0x25, 0x00, 0x3A, 0x64, 0x50, 0x00, 0x0A, 0x78, 0x54, 0x09, 0x3A, 0x30, ++ 0x73, 0x69, 0x44, 0x78, 0x30, 0x50, 0x00, 0x0A, 0x53, 0x4C, 0x09, 0x3A, 0x6B, 0x68, 0x43, 0x2D, ++ 0x30, 0x50, 0x00, 0x0A, 0x50, 0x09, 0x09, 0x3A, 0x61, 0x46, 0x2D, 0x44, 0x0A, 0x74, 0x6C, 0x75, ++ 0x3A, 0x30, 0x50, 0x00, 0x4B, 0x43, 0x41, 0x09, 0x00, 0x0A, 0x44, 0x2D, 0x09, 0x3A, 0x30, 0x50, ++ 0x2D, 0x4F, 0x4E, 0x09, 0x43, 0x54, 0x41, 0x4D, 0x50, 0x00, 0x0A, 0x48, 0x41, 0x09, 0x3A, 0x30, ++ 0x0A, 0x73, 0x65, 0x52, 0x3A, 0x30, 0x50, 0x00, 0x3E, 0x2D, 0x09, 0x09, 0x00, 0x30, 0x31, 0x20, ++ 0x46, 0x2D, 0x00, 0x30, 0x48, 0x2D, 0x00, 0x44, 0x45, 0x2F, 0x00, 0x44, 0x2D, 0x00, 0x45, 0x45, ++ 0x25, 0x3A, 0x53, 0x50, 0x50, 0x00, 0x0A, 0x64, 0x43, 0x09, 0x3A, 0x30, 0x4B, 0x43, 0x41, 0x2D, ++ 0x30, 0x50, 0x00, 0x0A, 0x52, 0x09, 0x09, 0x3A, 0x4D, 0x53, 0x46, 0x58, 0x0A, 0x64, 0x25, 0x3D, ++ 0x3A, 0x30, 0x50, 0x00, 0x2D, 0x50, 0x4E, 0x09, 0x74, 0x69, 0x61, 0x57, 0x30, 0x50, 0x00, 0x0A, ++ 0x54, 0x09, 0x09, 0x3A, 0x4D, 0x53, 0x46, 0x58, 0x0A, 0x64, 0x25, 0x3D, 0x3A, 0x30, 0x50, 0x00, ++ 0x69, 0x62, 0x41, 0x09, 0x0A, 0x44, 0x2D, 0x6C, 0x60, 0x2E, 0xE5, 0x00, 0x07, 0x3F, 0x75, 0x2A, ++ 0x75, 0xA0, 0x40, 0x75, 0x42, 0x75, 0x07, 0x41, 0x8B, 0x78, 0xE4, 0xA2, 0x78, 0xF6, 0x08, 0xF6, ++ 0xF6, 0x08, 0xF6, 0x89, 0x2F, 0x75, 0xD7, 0x51, 0xEF, 0x3D, 0xAF, 0x01, 0x3D, 0xF5, 0xFD, 0x54, ++ 0x54, 0xEF, 0x3D, 0xAF, 0xC2, 0x3D, 0xF5, 0xFE, 0x4F, 0x11, 0x12, 0x10, 0x06, 0x90, 0x0B, 0x40, ++ 0xC4, 0xFF, 0xE0, 0x00, 0xE0, 0x20, 0x0F, 0x54, 0x7F, 0x2B, 0x7E, 0x12, 0x2D, 0x65, 0xEF, 0xC2, ++ 0x65, 0xEE, 0x03, 0x70, 0x8E, 0x04, 0x60, 0x2C, 0x71, 0x2D, 0x8F, 0x2C, 0xEF, 0x3D, 0xAF, 0x36, ++ 0x3D, 0xF5, 0xFD, 0x54, 0xE0, 0xA4, 0x07, 0x90, 0xE0, 0x30, 0x13, 0xC3, 0x7F, 0x20, 0x7E, 0x21, ++ 0xAD, 0x41, 0xAC, 0x1D, 0x8C, 0x82, 0x8D, 0x42, 0xA3, 0xFC, 0xE0, 0x83, 0x10, 0x12, 0xFD, 0xE0, ++ 0xEF, 0x3D, 0xAF, 0x28, 0x3D, 0xF5, 0x02, 0x44, 0x74, 0xA4, 0x07, 0x90, 0x2B, 0xE5, 0xF0, 0x02, ++ 0x04, 0x70, 0x2D, 0x65, 0x2C, 0x65, 0x2A, 0xE5, 0x2C, 0x85, 0x09, 0x60, 0x2B, 0x2D, 0x85, 0x2A, ++ 0xAA, 0x01, 0x2F, 0x75, 0x12, 0x2B, 0xA9, 0x2A, 0xF5, 0xE4, 0x3B, 0x03, 0xEF, 0x3D, 0xAF, 0x2F, ++ 0x3D, 0xF5, 0xFE, 0x54, 0xE0, 0xA4, 0x07, 0x90, 0x7E, 0x2B, 0xE3, 0x30, 0x90, 0x2B, 0x7F, 0x20, ++ 0x10, 0x12, 0x23, 0x06, 0x7F, 0x20, 0x7E, 0x20, 0xAD, 0x3F, 0xAC, 0x37, 0x8C, 0x82, 0x8D, 0x40, ++ 0xA3, 0xFC, 0xE0, 0x83, 0x10, 0x12, 0xFD, 0xE0, 0xEF, 0x3D, 0xAF, 0x28, 0x3D, 0xF5, 0x01, 0x44, ++ 0x74, 0xA4, 0x07, 0x90, 0x08, 0x90, 0xF0, 0x08, 0x13, 0x13, 0xE0, 0x5F, 0x30, 0x1F, 0x54, 0x13, ++ 0x91, 0x78, 0x14, 0xE0, 0x09, 0x0A, 0xB4, 0xE6, 0x44, 0xEF, 0x3C, 0xAF, 0x80, 0x3C, 0xF5, 0x02, ++ 0x06, 0x91, 0x78, 0x16, 0x91, 0x78, 0x11, 0x80, 0xAF, 0x09, 0x70, 0xE6, 0xFD, 0x54, 0xEF, 0x3C, ++ 0x03, 0x80, 0x3C, 0xF5, 0x90, 0x16, 0x91, 0x78, 0x08, 0x74, 0x5F, 0x08, 0xA6, 0x07, 0x90, 0xF0, ++ 0x78, 0x07, 0x54, 0xE0, 0x7F, 0xE6, 0xF6, 0x92, 0x02, 0x02, 0xB4, 0x00, 0x54, 0xEF, 0x01, 0x7F, ++ 0x33, 0x33, 0x33, 0x01, 0xAE, 0xFF, 0xF8, 0x54, 0xF7, 0x54, 0xEE, 0x3C, 0x7F, 0x3C, 0xF5, 0x4F, ++ 0x3A, 0x11, 0x12, 0x8B, 0x3C, 0xAF, 0x07, 0x50, 0xF5, 0xFB, 0x54, 0xEF, 0xA4, 0x07, 0x90, 0x3C, ++ 0x17, 0xE0, 0x30, 0xE0, 0xB4, 0xE6, 0x92, 0x78, 0x3C, 0xAF, 0x11, 0x01, 0xF5, 0x04, 0x44, 0xEF, ++ 0x76, 0x8B, 0x78, 0x3C, 0xF4, 0x76, 0x08, 0x01, 0xAF, 0xF0, 0x01, 0x74, 0x13, 0x13, 0xEF, 0x3C, ++ 0xE0, 0x20, 0x3F, 0x54, 0xEF, 0x3C, 0xAF, 0x11, 0x54, 0x13, 0x13, 0x13, 0x06, 0xE0, 0x20, 0x1F, ++ 0xB4, 0xE6, 0x92, 0x78, 0x3C, 0xAF, 0x07, 0x03, 0xF5, 0xFD, 0x54, 0xEF, 0xEF, 0x3C, 0xAF, 0x3C, ++ 0x54, 0x13, 0x13, 0x13, 0x3C, 0xAE, 0xFF, 0x01, 0x54, 0x13, 0x13, 0xEE, 0xAE, 0xFF, 0x4F, 0x01, ++ 0x13, 0xC3, 0xEE, 0x3C, 0x54, 0x4F, 0x01, 0x54, 0x3C, 0xAE, 0xFF, 0x01, 0x4F, 0xFE, 0x54, 0xEE, ++ 0x3D, 0xAF, 0x3C, 0xF5, 0x29, 0xE0, 0x30, 0xEF, 0xE0, 0x52, 0x08, 0x90, 0x90, 0xF0, 0xFD, 0x54, ++ 0x54, 0xE0, 0x43, 0x08, 0x07, 0x90, 0xF0, 0xFE, 0x1F, 0x54, 0xE0, 0x9F, 0x7C, 0x00, 0x7E, 0xFF, ++ 0x12, 0x0A, 0x7D, 0x00, 0x24, 0xEF, 0x98, 0x02, 0xF6, 0x8A, 0x78, 0x39, 0xF6, 0x18, 0x3E, 0xE4, ++ 0x12, 0x89, 0x7F, 0x22, 0x0E, 0x50, 0x3A, 0x11, 0xE0, 0x52, 0x08, 0x90, 0x90, 0xF0, 0x02, 0x44, ++ 0x44, 0xE0, 0x43, 0x08, 0x75, 0x22, 0xF0, 0x01, 0x2D, 0x75, 0x23, 0x2C, 0x0D, 0x06, 0x90, 0x57, ++ 0xF0, 0xEF, 0x54, 0xE0, 0xFB, 0x54, 0x20, 0xE5, 0x06, 0x90, 0x20, 0xF5, 0xFD, 0x54, 0xE0, 0x00, ++ 0xAE, 0x01, 0x90, 0xF0, 0xF0, 0x04, 0x44, 0xE0, 0xE0, 0xF8, 0x07, 0x90, 0xE0, 0xF0, 0x01, 0x44, ++ 0x90, 0xF0, 0xFD, 0x54, 0xC4, 0xE0, 0xAA, 0x0D, 0x90, 0xFF, 0x0F, 0x54, 0xC4, 0xE0, 0xAB, 0x0D, ++ 0xFF, 0x2F, 0x0F, 0x54, 0x24, 0xCF, 0x33, 0xE4, 0x34, 0xEF, 0xFD, 0x00, 0x07, 0x90, 0xFC, 0x04, ++ 0xF0, 0x75, 0xE0, 0x0B, 0xEC, 0xFF, 0xA4, 0x20, 0x8D, 0x78, 0xF0, 0x45, 0x08, 0x4F, 0xED, 0xF6, ++ 0x02, 0x04, 0x7F, 0xF6, 0x8E, 0x78, 0xE2, 0x03, 0xFF, 0x01, 0x54, 0xE6, 0x74, 0x9F, 0xE4, 0xC3, ++ 0x54, 0x00, 0x94, 0x08, 0xE6, 0x18, 0xFC, 0x05, 0x08, 0xFE, 0x13, 0xC3, 0xEE, 0xFF, 0x13, 0xE6, ++ 0xEF, 0xF6, 0x18, 0x6C, 0xE5, 0x22, 0xF6, 0x08, 0x7E, 0x35, 0x60, 0x2F, 0x12, 0x3B, 0x7F, 0x20, ++ 0x81, 0x78, 0x1B, 0x10, 0x76, 0x08, 0x34, 0x76, 0x23, 0x06, 0x90, 0xBC, 0x13, 0x13, 0xFF, 0xE0, ++ 0x92, 0x13, 0x3F, 0x54, 0x71, 0x11, 0xD2, 0x10, 0x9D, 0x07, 0x90, 0xA9, 0x90, 0xF0, 0x03, 0x74, ++ 0x54, 0xE0, 0x03, 0x06, 0x78, 0xE4, 0xF0, 0xDF, 0x20, 0xE5, 0xF6, 0x7F, 0x20, 0xF5, 0xF7, 0x54, ++ 0x11, 0x12, 0x81, 0x7F, 0x75, 0x06, 0x50, 0x3A, 0x2D, 0x75, 0x24, 0x2C, 0xFF, 0xE0, 0x22, 0xCA, ++ 0x3F, 0x54, 0x13, 0x13, 0xC2, 0x10, 0x92, 0x13, 0x27, 0x06, 0x90, 0x11, 0x03, 0xE0, 0x30, 0xE0, ++ 0x90, 0x1C, 0x10, 0x30, 0x30, 0xE0, 0x27, 0x06, 0x41, 0x81, 0x02, 0xE0, 0xE0, 0x26, 0x06, 0x90, ++ 0x78, 0xE0, 0xA3, 0xFE, 0x13, 0xC3, 0xCE, 0x02, 0xF9, 0xD8, 0x13, 0xCE, 0xC2, 0x72, 0xE0, 0x20, ++ 0xE4, 0x11, 0xA2, 0x10, 0x10, 0x54, 0xC4, 0x33, 0x90, 0xFF, 0x0F, 0x44, 0xC4, 0xE0, 0x01, 0x0D, ++ 0xC4, 0x01, 0x54, 0x13, 0x4F, 0x20, 0x54, 0x33, 0x21, 0x0D, 0x90, 0xF0, 0x54, 0x13, 0xC4, 0xE0, ++ 0x54, 0x33, 0xC4, 0x01, 0xF0, 0x10, 0x44, 0x20, 0x74, 0x00, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x18, ++ 0xF0, 0x38, 0x74, 0x20, 0xE0, 0x29, 0x06, 0x90, 0x0D, 0x90, 0x13, 0xC3, 0x09, 0xE0, 0x30, 0x0C, ++ 0x90, 0xF0, 0x11, 0x74, 0x80, 0xF0, 0x2C, 0x0D, 0xF0, 0x15, 0x74, 0x09, 0x74, 0x2C, 0x0D, 0x90, ++ 0x07, 0x90, 0xF0, 0x12, 0xFC, 0x54, 0xE0, 0xF9, 0xF3, 0x54, 0xE0, 0xF0, 0x90, 0xF0, 0x04, 0x44, ++ 0x54, 0xE0, 0xFA, 0x07, 0xF0, 0x01, 0x44, 0xFC, 0xF0, 0xF3, 0x54, 0xE0, 0x80, 0xA2, 0x01, 0x90, ++ 0xA2, 0x10, 0xD2, 0x70, 0xC4, 0x33, 0xE4, 0x11, 0x0F, 0x44, 0xF0, 0x54, 0x21, 0x0D, 0x90, 0xFF, ++ 0x54, 0x13, 0xC4, 0xE0, 0x54, 0x33, 0xC4, 0x01, 0x90, 0xF0, 0x4F, 0xE0, 0xC4, 0xE0, 0x01, 0x0D, ++ 0xC4, 0x01, 0x54, 0x13, 0x44, 0x20, 0x54, 0x33, 0x0D, 0x90, 0xF0, 0x10, 0xF0, 0x38, 0x74, 0x00, ++ 0x74, 0x20, 0x0D, 0x90, 0x06, 0x90, 0xF0, 0x18, 0x13, 0xC3, 0xE0, 0x29, 0x30, 0x0C, 0x0D, 0x90, ++ 0x11, 0x74, 0x09, 0xE0, 0x2C, 0x0D, 0x90, 0xF0, 0x74, 0x09, 0x80, 0xF0, 0x0D, 0x90, 0xF0, 0x12, ++ 0xF0, 0x15, 0x74, 0x2C, 0xE0, 0xF9, 0x07, 0x90, 0x01, 0x44, 0xFC, 0x54, 0xF3, 0x54, 0xE0, 0xF0, ++ 0xFA, 0x07, 0x90, 0xF0, 0xF0, 0xFC, 0x54, 0xE0, 0x44, 0xF3, 0x54, 0xE0, 0x01, 0x90, 0xF0, 0x04, ++ 0x08, 0x90, 0xE0, 0xA3, 0x10, 0xA2, 0xF0, 0x45, 0x01, 0x54, 0x33, 0xE4, 0xE0, 0x25, 0xE0, 0x25, ++ 0x23, 0x06, 0x90, 0xFF, 0x4F, 0xFB, 0x54, 0xE0, 0x2F, 0xE5, 0x22, 0xF0, 0xAC, 0xD1, 0x07, 0x60, ++ 0x71, 0x23, 0x06, 0x90, 0xEF, 0x3C, 0xAF, 0x9E, 0xE0, 0x20, 0x13, 0xC3, 0xEF, 0x3C, 0xAF, 0x0A, ++ 0x3F, 0x54, 0x13, 0x13, 0x7F, 0x27, 0xE0, 0x30, 0x3A, 0x11, 0x12, 0x81, 0x85, 0x78, 0x27, 0x50, ++ 0x76, 0x08, 0x02, 0x76, 0xEF, 0x3C, 0xAF, 0x6C, 0x54, 0xC4, 0x02, 0x54, 0x3C, 0xAE, 0xFF, 0xF0, ++ 0x4F, 0xDF, 0x54, 0xEE, 0x2C, 0x75, 0x3C, 0xF5, 0x1E, 0x2D, 0x75, 0x26, 0x81, 0x78, 0x07, 0x80, ++ 0x76, 0x08, 0x01, 0x76, 0xA6, 0x07, 0x90, 0x36, 0x64, 0x07, 0x54, 0xE0, 0xE4, 0x0B, 0x60, 0x02, ++ 0x78, 0xF6, 0x8F, 0x78, 0xF6, 0x08, 0xF6, 0x93, 0x3D, 0xAF, 0x57, 0x80, 0x30, 0x13, 0xC3, 0xEF, ++ 0x41, 0xAE, 0x4F, 0xE0, 0x82, 0x8F, 0x42, 0xAF, 0x54, 0xE0, 0x83, 0x8E, 0x93, 0x78, 0xFF, 0x40, ++ 0x4F, 0xBF, 0x54, 0xE6, 0xAF, 0x41, 0xAE, 0xF6, 0x8E, 0x82, 0x8F, 0x42, 0xA3, 0xFE, 0xE0, 0x83, ++ 0x70, 0x66, 0x08, 0xE0, 0x66, 0x18, 0xEE, 0x03, 0x8F, 0x78, 0x11, 0x70, 0x94, 0xC3, 0xE6, 0x06, ++ 0x75, 0x1E, 0x40, 0x02, 0x2D, 0x75, 0x27, 0x2C, 0xAE, 0x16, 0x80, 0x5E, 0x8F, 0x42, 0xAF, 0x41, ++ 0xE0, 0x83, 0x8E, 0x82, 0x78, 0xE0, 0xA3, 0xFE, 0x08, 0x06, 0xA6, 0x93, 0x8F, 0x78, 0xE4, 0xF6, ++ 0x27, 0x06, 0x90, 0xF6, 0x02, 0xE0, 0x20, 0xE0, 0x83, 0x7F, 0x0A, 0xC1, 0x40, 0x3A, 0x11, 0x12, ++ 0x12, 0x85, 0x7F, 0x09, 0x02, 0x40, 0x3A, 0x11, 0x3D, 0xAF, 0x1D, 0xC1, 0x7D, 0xE0, 0x30, 0xEF, ++ 0x20, 0xEF, 0x3C, 0xAF, 0x84, 0x78, 0x77, 0xE0, 0x70, 0x46, 0x18, 0xE6, 0x23, 0x06, 0x90, 0x34, ++ 0x13, 0x13, 0xFF, 0xE0, 0xE0, 0x30, 0x3F, 0x54, 0x35, 0x06, 0x90, 0x07, 0xF0, 0x08, 0x44, 0xE0, ++ 0x11, 0xC2, 0x10, 0xC2, 0x8D, 0x78, 0xA9, 0x71, 0xFE, 0x07, 0x54, 0xE6, 0xE0, 0x25, 0xE6, 0x08, ++ 0xFE, 0x33, 0xEE, 0xFF, 0x78, 0xC8, 0x24, 0xEF, 0x34, 0xEE, 0xF6, 0x84, 0x80, 0xF6, 0x18, 0x2A, ++ 0xE6, 0x8E, 0x78, 0x21, 0x90, 0xFF, 0x01, 0x54, 0xFD, 0xE0, 0x23, 0x06, 0x01, 0x54, 0x13, 0x13, ++ 0xE4, 0x01, 0x70, 0x6F, 0x06, 0x90, 0x07, 0x60, 0x08, 0x44, 0xE0, 0x35, 0xE6, 0x8E, 0x78, 0xF0, ++ 0x85, 0x78, 0xA4, 0x71, 0x76, 0x08, 0x02, 0x76, 0x85, 0x78, 0x22, 0x6C, 0x76, 0x08, 0x02, 0x76, ++ 0x76, 0x83, 0x78, 0x6C, 0xC8, 0x76, 0x08, 0x2A, 0x71, 0x27, 0x06, 0x90, 0x2F, 0xE5, 0x22, 0x9E, ++ 0x20, 0x7E, 0x24, 0x60, 0x10, 0x12, 0x46, 0x7F, 0x9D, 0x07, 0x90, 0x1B, 0x90, 0xF0, 0x01, 0x74, ++ 0xFF, 0xE0, 0x23, 0x06, 0x3F, 0x54, 0x13, 0x13, 0xD2, 0x10, 0x92, 0x13, 0x78, 0xA9, 0x71, 0x11, ++ 0x08, 0x1D, 0x76, 0x81, 0x3C, 0xAF, 0x4C, 0x76, 0x54, 0x13, 0xC4, 0xEF, 0x30, 0x3C, 0xAF, 0x07, ++ 0x54, 0xEF, 0x0A, 0xE0, 0x33, 0x33, 0x33, 0x02, 0x07, 0x80, 0xF8, 0x54, 0x25, 0x04, 0x54, 0xEF, ++ 0xFF, 0xE0, 0x25, 0xE0, 0x54, 0xEE, 0x3C, 0xAE, 0x3C, 0xF5, 0x4F, 0xEF, 0x11, 0x12, 0x81, 0x7F, ++ 0xAF, 0x1B, 0x50, 0x3A, 0x13, 0xC4, 0xEF, 0x3C, 0x06, 0x90, 0x07, 0x54, 0x05, 0xE0, 0x20, 0x0B, ++ 0x80, 0xF0, 0x21, 0x74, 0xF0, 0x81, 0x74, 0x03, 0x75, 0x2A, 0x2C, 0x75, 0x3C, 0xAF, 0x2B, 0x2D, ++ 0x0F, 0x54, 0xC4, 0xEF, 0x7E, 0x14, 0xE0, 0x20, 0x12, 0x52, 0x7F, 0x20, 0x06, 0x90, 0x1B, 0x10, ++ 0x10, 0x44, 0xE0, 0x0D, 0x24, 0x2C, 0x75, 0xF0, 0x22, 0xCA, 0x2D, 0x75, 0xDD, 0x7F, 0x20, 0x7E, ++ 0xE4, 0x1B, 0x10, 0x12, 0x78, 0xF6, 0x8F, 0x78, 0x76, 0x08, 0xF6, 0x81, 0x2A, 0x76, 0x08, 0x9B, ++ 0x78, 0xC8, 0x76, 0x08, 0x08, 0xFD, 0x76, 0x87, 0x93, 0x78, 0xE8, 0x76, 0x78, 0xF6, 0x08, 0xF6, ++ 0x08, 0x02, 0x76, 0x85, 0x99, 0x78, 0x6C, 0x76, 0xF6, 0x08, 0x01, 0x76, 0x06, 0x90, 0xF6, 0x08, ++ 0xA3, 0xFF, 0xE0, 0x08, 0xAD, 0x3F, 0xAC, 0xE0, 0x8C, 0x82, 0x8D, 0x40, 0xA3, 0xF0, 0xCF, 0x83, ++ 0x3F, 0xAE, 0xF0, 0xEF, 0x82, 0x8F, 0x40, 0xAF, 0x83, 0xC0, 0x83, 0x8E, 0xFF, 0xE0, 0x82, 0xC0, ++ 0xE0, 0x8F, 0x01, 0x90, 0x01, 0x54, 0x13, 0xC3, 0x13, 0xC4, 0xEF, 0xFE, 0x01, 0x54, 0x13, 0x13, ++ 0x7F, 0x54, 0xEF, 0xFD, 0x54, 0x4E, 0xED, 0xFF, 0x33, 0x33, 0xC4, 0x01, 0x4F, 0x80, 0x54, 0x33, ++ 0x83, 0xD0, 0x82, 0xD0, 0xAF, 0x3F, 0xAE, 0xF0, 0x8E, 0x82, 0x8F, 0x40, 0x08, 0x54, 0xE0, 0x83, ++ 0xFF, 0xF0, 0x54, 0xC4, 0x54, 0xEE, 0x3C, 0xAE, 0x3C, 0xF5, 0x4F, 0x7F, 0x0A, 0x06, 0x90, 0xE4, ++ 0x90, 0xF0, 0xA3, 0xF0, 0x54, 0xE0, 0x0D, 0x06, 0x54, 0xE0, 0xF0, 0xFE, 0x54, 0xE0, 0xF0, 0xF7, ++ 0x90, 0xE4, 0xF0, 0xFD, 0xA3, 0xF0, 0x90, 0x01, 0x9D, 0x07, 0x90, 0xF0, 0x2F, 0xE5, 0x22, 0xF0, ++ 0x20, 0x7E, 0x24, 0x60, 0x10, 0x12, 0x61, 0x7F, 0x0D, 0x06, 0x90, 0x1B, 0xF0, 0x01, 0x44, 0xE0, ++ 0x40, 0xAF, 0x3F, 0xAE, 0x83, 0x8E, 0x82, 0x8F, 0xF0, 0x40, 0x44, 0xE0, 0x44, 0xE6, 0x93, 0x78, ++ 0x78, 0xE4, 0xF6, 0x40, 0x07, 0x90, 0xF6, 0x8F, 0x07, 0x54, 0xE0, 0xA6, 0x06, 0x60, 0x02, 0x64, ++ 0x75, 0x23, 0x2C, 0x75, 0x3D, 0xAF, 0x57, 0x2D, 0x30, 0x13, 0xC3, 0xEF, 0x41, 0xAE, 0x51, 0xE0, ++ 0x82, 0x8F, 0x42, 0xAF, 0xFE, 0xE0, 0x83, 0x8E, 0x94, 0x78, 0xE0, 0xA3, 0xEE, 0x03, 0x70, 0x66, ++ 0x10, 0x70, 0x66, 0x18, 0xE6, 0x06, 0x8F, 0x78, 0x40, 0x02, 0x94, 0xD3, 0x27, 0x2C, 0x75, 0x32, ++ 0x22, 0xF0, 0x2D, 0x75, 0xF6, 0x8F, 0x78, 0xE4, 0x54, 0xE6, 0x93, 0x78, 0x41, 0xAE, 0xF6, 0xBF, ++ 0x82, 0x8F, 0x42, 0xAF, 0xFE, 0xE0, 0x83, 0x8E, 0x66, 0x08, 0xE0, 0xA3, 0x18, 0xEE, 0x03, 0x70, ++ 0x75, 0x06, 0x60, 0x66, 0x2D, 0x75, 0x23, 0x2C, 0xE6, 0x93, 0x78, 0x57, 0x22, 0xF6, 0x40, 0x44, ++ 0x03, 0x60, 0x2F, 0xE5, 0xAF, 0xD6, 0x2B, 0x12, 0xE0, 0x30, 0xEF, 0x3D, 0xE6, 0x90, 0x78, 0x09, ++ 0x40, 0x00, 0x94, 0xD3, 0x90, 0x78, 0x16, 0x01, 0x90, 0x40, 0x70, 0xE6, 0x13, 0xE0, 0x0D, 0x06, ++ 0x30, 0x3F, 0x54, 0x13, 0x13, 0xE0, 0x2F, 0xE0, 0x1F, 0x54, 0x13, 0x13, 0xAE, 0x26, 0xE0, 0x30, ++ 0x8F, 0x40, 0xAF, 0x3F, 0xE0, 0x83, 0x8E, 0x82, 0x13, 0x13, 0x13, 0xC4, 0xE0, 0x20, 0x01, 0x54, ++ 0x10, 0x06, 0x90, 0x0D, 0x13, 0x13, 0xC4, 0xE0, 0x30, 0x01, 0x54, 0x13, 0x2C, 0x75, 0x07, 0xE0, ++ 0x4C, 0x2D, 0x75, 0x28, 0x2A, 0x2C, 0x75, 0x22, 0x22, 0x2B, 0x2D, 0x75, 0xE0, 0xA6, 0x07, 0x90, ++ 0x02, 0x64, 0x07, 0x54, 0x2C, 0x75, 0x06, 0x60, 0x57, 0x2D, 0x75, 0x23, 0x02, 0x60, 0x2F, 0xE5, ++ 0x99, 0x78, 0x77, 0x31, 0x70, 0x07, 0x64, 0xE6, 0xEF, 0x20, 0xAF, 0x4B, 0x54, 0x13, 0x13, 0x13, ++ 0x65, 0xE0, 0x30, 0x1F, 0xE0, 0x0E, 0x06, 0x90, 0x78, 0xE0, 0xA3, 0xFE, 0x08, 0x06, 0xA6, 0x96, ++ 0xEF, 0x3C, 0xAF, 0xF6, 0x54, 0xC4, 0x80, 0x54, 0xE6, 0x18, 0xFF, 0x0F, 0xF6, 0x4F, 0xF7, 0x54, ++ 0xE6, 0x08, 0xFF, 0xE6, 0x40, 0xAD, 0x3F, 0xAC, 0x83, 0x8C, 0x82, 0x8D, 0xEF, 0xA3, 0xF0, 0xCF, ++ 0x0E, 0x06, 0x90, 0xF0, 0x13, 0x13, 0xC4, 0xE0, 0x20, 0x01, 0x54, 0x13, 0x99, 0x78, 0x2B, 0xE0, ++ 0x25, 0x80, 0x08, 0x76, 0x21, 0x60, 0x2F, 0xE5, 0x54, 0xEF, 0x3C, 0xAF, 0x0F, 0x54, 0xC4, 0x80, ++ 0xE6, 0x96, 0x78, 0xFF, 0xF6, 0x4F, 0xF7, 0x54, 0xE6, 0x08, 0xFF, 0xE6, 0x40, 0xAD, 0x3F, 0xAC, ++ 0x83, 0x8C, 0x82, 0x8D, 0xEF, 0xA3, 0xF0, 0xCF, 0xEF, 0x3D, 0xAF, 0xF0, 0xE0, 0x20, 0x13, 0xC3, ++ 0xAE, 0x76, 0x21, 0x02, 0x8F, 0x42, 0xAF, 0x41, 0xE0, 0x83, 0x8E, 0x82, 0xAE, 0xF0, 0xBF, 0x54, ++ 0x8F, 0x42, 0xAF, 0x41, 0xE0, 0x83, 0x8E, 0x82, 0x78, 0xE0, 0xA3, 0xFE, 0x03, 0x70, 0x66, 0x94, ++ 0x70, 0x66, 0x18, 0xEE, 0x06, 0x8F, 0x78, 0x5B, 0x02, 0x94, 0xC3, 0xE6, 0x02, 0x76, 0x68, 0x40, ++ 0x42, 0xAF, 0x41, 0xAE, 0x83, 0x8E, 0x82, 0x8F, 0x13, 0x13, 0x13, 0xE0, 0xAE, 0xFF, 0x01, 0x54, ++ 0x13, 0xC4, 0xEE, 0x3C, 0x6F, 0x01, 0x54, 0x13, 0x99, 0x78, 0x4C, 0x60, 0x0B, 0x07, 0xB4, 0xE6, ++ 0x13, 0xEF, 0x20, 0xAF, 0x1F, 0x54, 0x13, 0x13, 0x75, 0x3B, 0xE0, 0x30, 0x2D, 0x75, 0x27, 0x2C, ++ 0xE6, 0x99, 0x78, 0x5E, 0x2E, 0x70, 0x07, 0x64, 0xF7, 0x54, 0x20, 0xE5, 0x64, 0xE6, 0x20, 0xF5, ++ 0xE6, 0x23, 0x60, 0x01, 0x1E, 0x60, 0x08, 0x64, 0xE0, 0x34, 0x06, 0x90, 0x22, 0xF0, 0x10, 0x44, ++ 0x42, 0xAF, 0x41, 0xAE, 0x83, 0x8E, 0x82, 0x8F, 0xE0, 0xA3, 0xFE, 0xE0, 0x06, 0xA6, 0x93, 0x78, ++ 0x78, 0xE4, 0xF6, 0x08, 0x7E, 0x22, 0xF6, 0x8F, 0x12, 0xC1, 0x7F, 0x20, 0x78, 0xE4, 0x1B, 0x10, ++ 0x93, 0x78, 0xF6, 0x8F, 0x78, 0xF6, 0x08, 0xF6, 0xFA, 0x24, 0xE6, 0x99, 0x60, 0x14, 0x30, 0x60, ++ 0x44, 0x60, 0x14, 0x47, 0x3D, 0x70, 0x07, 0x24, 0xE0, 0x8F, 0x01, 0x90, 0xE0, 0x30, 0x13, 0xC3, ++ 0x76, 0x99, 0x78, 0x06, 0x90, 0x31, 0x80, 0x05, 0xC4, 0xE0, 0x08, 0x06, 0x54, 0x13, 0x13, 0x13, ++ 0x20, 0x99, 0x78, 0x01, 0x08, 0x76, 0x04, 0xE0, 0x07, 0x76, 0x1E, 0x80, 0x06, 0x90, 0x1A, 0x80, ++ 0x13, 0xC4, 0xE0, 0x08, 0x01, 0x54, 0x13, 0x13, 0xE0, 0x20, 0x99, 0x78, 0x80, 0x08, 0x76, 0x04, ++ 0x80, 0x07, 0x76, 0x07, 0x06, 0x99, 0x78, 0x03, 0x24, 0xE6, 0x99, 0x78, 0x24, 0x25, 0x60, 0xFA, ++ 0x24, 0x10, 0x60, 0xFE, 0x78, 0x37, 0x70, 0x03, 0xE4, 0x0A, 0x76, 0x97, 0x44, 0xE6, 0xF6, 0x18, ++ 0x78, 0x0A, 0x80, 0x80, 0xE4, 0x01, 0x76, 0x97, 0x54, 0xE6, 0xF6, 0x18, 0x44, 0xE6, 0xF6, 0x7F, ++ 0x1A, 0x80, 0xF6, 0x20, 0xE0, 0x8E, 0x01, 0x90, 0x78, 0xE0, 0xA3, 0xFE, 0x08, 0x06, 0xA6, 0x96, ++ 0x08, 0x06, 0x90, 0xF6, 0xFF, 0x80, 0x54, 0xE0, 0x7F, 0x54, 0xE6, 0x18, 0x20, 0x7E, 0xF6, 0x4F, ++ 0x99, 0x78, 0xCE, 0x7F, 0x00, 0x7C, 0xFD, 0xE6, 0x51, 0x28, 0x10, 0x02, 0xEF, 0x3C, 0xAF, 0x4F, ++ 0x90, 0x15, 0xE0, 0x30, 0x44, 0xE0, 0x34, 0x06, 0x20, 0x7E, 0xF0, 0x08, 0x10, 0x12, 0x6C, 0x7F, ++ 0x23, 0x2C, 0x75, 0x1B, 0x22, 0x57, 0x2D, 0x75, 0x75, 0x2B, 0x2C, 0x75, 0xAF, 0x22, 0xC2, 0x2D, ++ 0xFE, 0x54, 0xEF, 0x3C, 0x20, 0x7E, 0x3C, 0xF5, 0x10, 0x12, 0x7B, 0x7F, 0x06, 0x90, 0xE4, 0x1B, ++ 0xF0, 0xA3, 0xF0, 0x30, 0xE0, 0x09, 0x06, 0x90, 0x01, 0x64, 0x1F, 0x54, 0xBA, 0x61, 0x02, 0x60, ++ 0xE0, 0x0B, 0x06, 0x90, 0x01, 0x64, 0x1F, 0x54, 0xBA, 0x61, 0x02, 0x60, 0xE0, 0x0A, 0x06, 0x90, ++ 0xFF, 0xE0, 0xA3, 0xFE, 0xE0, 0x08, 0x06, 0x90, 0xF6, 0x96, 0x78, 0x5E, 0x08, 0x5F, 0xE0, 0xA3, ++ 0x30, 0xE6, 0x18, 0xF6, 0x06, 0x90, 0x0A, 0xE0, 0xFC, 0x54, 0xE0, 0x31, 0x27, 0x80, 0x01, 0x44, ++ 0xC4, 0xE6, 0x97, 0x78, 0x54, 0x13, 0x13, 0x13, 0x0A, 0xE0, 0x30, 0x01, 0xE0, 0x31, 0x06, 0x90, ++ 0x01, 0x44, 0xFC, 0x54, 0x97, 0x78, 0x28, 0x80, 0x13, 0x13, 0xC4, 0xE6, 0xE0, 0x30, 0x03, 0x54, ++ 0x31, 0x06, 0x90, 0x0D, 0xF0, 0xFC, 0x54, 0xE0, 0xF0, 0x08, 0x44, 0xE0, 0x97, 0x78, 0x1E, 0x80, ++ 0x54, 0x13, 0xC4, 0xE6, 0x0D, 0xE0, 0x30, 0x07, 0xE0, 0x31, 0x06, 0x90, 0xE0, 0xF0, 0xFC, 0x54, ++ 0x80, 0xF0, 0xF7, 0x54, 0xEF, 0x3C, 0xAF, 0x07, 0x3C, 0xF5, 0x01, 0x44, 0xE0, 0x8F, 0x01, 0x90, ++ 0xE0, 0x30, 0x13, 0xC3, 0x91, 0x01, 0x90, 0x17, 0x30, 0x13, 0xC3, 0xE0, 0x06, 0x90, 0x0E, 0xE0, ++ 0x03, 0x54, 0xE0, 0x31, 0x04, 0x01, 0xBF, 0xFF, 0xF0, 0x04, 0x44, 0xE0, 0x13, 0xE6, 0x96, 0x78, ++ 0x30, 0x3F, 0x54, 0x13, 0x06, 0x90, 0x09, 0xE0, 0x30, 0x44, 0xE0, 0x31, 0x78, 0x36, 0x80, 0xF0, ++ 0x13, 0x13, 0xE6, 0x96, 0x30, 0x1F, 0x54, 0x13, 0x06, 0x90, 0x24, 0xE0, 0xE2, 0x30, 0xE0, 0x08, ++ 0x31, 0x06, 0x90, 0x0B, 0x44, 0xCF, 0x54, 0xE0, 0x19, 0x80, 0xF0, 0x20, 0xE0, 0x0A, 0x06, 0x90, ++ 0x30, 0x31, 0x06, 0x90, 0x54, 0xE0, 0x0B, 0xE2, 0xF0, 0x10, 0x44, 0xCF, 0x06, 0x90, 0x07, 0x80, ++ 0xCF, 0x54, 0xE0, 0x31, 0x76, 0x7F, 0x78, 0xF0, 0x7F, 0x20, 0x7E, 0x01, 0x1B, 0x10, 0x12, 0x85, ++ 0xF6, 0x8F, 0x78, 0xE4, 0xE0, 0x31, 0x06, 0x90, 0x78, 0xFF, 0x03, 0x54, 0x9F, 0xC3, 0xE6, 0x8F, ++ 0x20, 0x7E, 0x0C, 0x50, 0x10, 0x12, 0x90, 0x7F, 0x06, 0x8F, 0x78, 0x1B, 0x06, 0x90, 0xE6, 0x80, ++ 0x13, 0x13, 0xE0, 0x31, 0x30, 0x1F, 0x54, 0x13, 0x20, 0x7E, 0x06, 0xE0, 0x04, 0x80, 0x92, 0x7F, ++ 0x96, 0x7F, 0x20, 0x7E, 0x90, 0x1B, 0x10, 0x12, 0x13, 0xE0, 0x31, 0x06, 0x30, 0x3F, 0x54, 0x13, ++ 0x20, 0x7E, 0x07, 0xE0, 0x10, 0x12, 0x9A, 0x7F, 0x7F, 0x20, 0x7E, 0x1B, 0x31, 0x06, 0x90, 0x9F, ++ 0x03, 0x54, 0xC4, 0xE0, 0x02, 0x00, 0x7C, 0xFD, 0x3C, 0xAF, 0x28, 0x10, 0xF5, 0x01, 0x44, 0xEF, ++ 0x01, 0x90, 0x22, 0x3C, 0xFB, 0x54, 0xE0, 0xAE, 0x02, 0x28, 0x75, 0xF0, 0x75, 0x51, 0x29, 0x75, ++ 0x25, 0x75, 0x01, 0x24, 0x20, 0x7E, 0x22, 0xBB, 0x10, 0x12, 0xA7, 0x7F, 0x76, 0x90, 0x78, 0x1B, ++ 0xE6, 0x9A, 0x78, 0x07, 0x07, 0x60, 0xFA, 0x24, 0x24, 0x08, 0x60, 0x14, 0x78, 0x1F, 0x70, 0x06, ++ 0x78, 0x07, 0x76, 0x9A, 0x13, 0xC4, 0xE6, 0x93, 0xE0, 0x30, 0x07, 0x54, 0x07, 0x54, 0xE6, 0x14, ++ 0x64, 0xE6, 0x08, 0xFE, 0x09, 0x70, 0x4E, 0x0A, 0x05, 0x76, 0x9A, 0x78, 0x9A, 0x78, 0x03, 0x80, ++ 0xE6, 0x9A, 0x78, 0x06, 0x35, 0x60, 0xFA, 0x24, 0x3F, 0x70, 0x05, 0x24, 0xFF, 0xE6, 0x93, 0x78, ++ 0x06, 0x90, 0xE6, 0x08, 0xA3, 0xF0, 0xCF, 0x0A, 0xE6, 0x18, 0xF0, 0xEF, 0x13, 0xC3, 0x20, 0x54, ++ 0x03, 0x06, 0x90, 0xFF, 0x4F, 0xEF, 0x54, 0xE0, 0x0A, 0x06, 0x90, 0xF0, 0xC4, 0x80, 0x54, 0xE0, ++ 0x90, 0xFF, 0x0F, 0x54, 0x54, 0xE0, 0x0D, 0x06, 0x80, 0xF0, 0x4F, 0xF7, 0xE6, 0x93, 0x78, 0x0E, ++ 0x90, 0xE6, 0x08, 0xFF, 0xF0, 0xCF, 0x90, 0x01, 0x78, 0xF0, 0xEF, 0xA3, 0x01, 0x64, 0xE6, 0x9A, ++ 0x93, 0x78, 0x0E, 0x60, 0xE6, 0x08, 0xFF, 0xE6, 0xCF, 0x10, 0x06, 0x90, 0xF0, 0xEF, 0xA3, 0xF0, ++ 0xE0, 0x34, 0x06, 0x90, 0x7E, 0xF0, 0x20, 0x44, 0x78, 0xB2, 0x7F, 0x20, 0x7C, 0xFD, 0xE6, 0x9A, ++ 0x28, 0x10, 0x12, 0x00, 0xE0, 0x0D, 0x06, 0x90, 0x78, 0xF0, 0x02, 0x44, 0x08, 0x54, 0xE6, 0x93, ++ 0x54, 0x33, 0x33, 0x33, 0x3C, 0xAE, 0xFF, 0xF8, 0x4F, 0xBF, 0x54, 0xEE, 0x3C, 0xAF, 0x3C, 0xF5, ++ 0x13, 0x13, 0xC4, 0xEF, 0x7F, 0x01, 0x54, 0x13, 0x02, 0xE0, 0x20, 0x00, 0x54, 0xEF, 0x01, 0x7F, ++ 0x33, 0x33, 0xC4, 0x01, 0xFF, 0x80, 0x54, 0x33, 0x54, 0xEE, 0x3C, 0xAE, 0x3C, 0xF5, 0x4F, 0x7F, ++ 0xB4, 0xE6, 0x99, 0x78, 0x06, 0x90, 0x07, 0x01, 0xDF, 0x54, 0xE0, 0x08, 0x00, 0x22, 0x22, 0xF0, ++ 0xE0, 0x44, 0x07, 0x90, 0xE4, 0x0C, 0xE5, 0x30, 0xF0, 0xB4, 0x01, 0x90, 0x33, 0xA9, 0x32, 0xAA, ++ 0xE5, 0x3B, 0x03, 0x02, 0xE4, 0x05, 0x60, 0x3A, 0x33, 0xF5, 0x32, 0xF5, 0x3A, 0x31, 0x50, 0x22, ++ 0x09, 0x09, 0x09, 0x09, 0x25, 0x3A, 0x58, 0x52, 0x50, 0x00, 0x0A, 0x78, 0x09, 0x09, 0x3A, 0x31, ++ 0x25, 0x58, 0x54, 0x09, 0x25, 0x00, 0x3A, 0x64, 0x50, 0x00, 0x0A, 0x78, 0x54, 0x09, 0x3A, 0x31, ++ 0x73, 0x69, 0x44, 0x78, 0x31, 0x50, 0x00, 0x0A, 0x53, 0x4C, 0x09, 0x3A, 0x6B, 0x68, 0x43, 0x2D, ++ 0x31, 0x50, 0x00, 0x0A, 0x50, 0x09, 0x09, 0x3A, 0x61, 0x46, 0x2D, 0x44, 0x0A, 0x74, 0x6C, 0x75, ++ 0x3A, 0x31, 0x50, 0x00, 0x4B, 0x43, 0x41, 0x09, 0x00, 0x0A, 0x44, 0x2D, 0x09, 0x3A, 0x31, 0x50, ++ 0x2D, 0x4F, 0x4E, 0x09, 0x43, 0x54, 0x41, 0x4D, 0x50, 0x00, 0x0A, 0x48, 0x41, 0x09, 0x3A, 0x31, ++ 0x0A, 0x73, 0x65, 0x52, 0x3A, 0x31, 0x50, 0x00, 0x3E, 0x2D, 0x09, 0x09, 0x00, 0x30, 0x31, 0x20, ++ 0x46, 0x2D, 0x00, 0x30, 0x48, 0x2D, 0x00, 0x44, 0x45, 0x2F, 0x00, 0x44, 0x2D, 0x00, 0x45, 0x45, ++ 0x25, 0x3A, 0x53, 0x50, 0x50, 0x00, 0x0A, 0x64, 0x43, 0x09, 0x3A, 0x31, 0x4B, 0x43, 0x41, 0x2D, ++ 0x31, 0x50, 0x00, 0x0A, 0x52, 0x09, 0x09, 0x3A, 0x4D, 0x53, 0x46, 0x58, 0x0A, 0x64, 0x25, 0x3D, ++ 0x3A, 0x31, 0x50, 0x00, 0x2D, 0x50, 0x4E, 0x09, 0x74, 0x69, 0x61, 0x57, 0x31, 0x50, 0x00, 0x0A, ++ 0x54, 0x09, 0x09, 0x3A, 0x4D, 0x53, 0x46, 0x58, 0x0A, 0x64, 0x25, 0x3D, 0x3A, 0x31, 0x50, 0x00, ++ 0x69, 0x62, 0x41, 0x09, 0x0A, 0x44, 0x2D, 0x6C, 0x60, 0x3A, 0xE5, 0x00, 0x07, 0x4C, 0x75, 0x2A, ++ 0x75, 0xEA, 0x4D, 0x75, 0x4F, 0x75, 0x07, 0x4E, 0xAC, 0x78, 0xE4, 0xEC, 0x78, 0xF6, 0x08, 0xF6, ++ 0xF6, 0x08, 0xF6, 0xAA, 0x3B, 0x75, 0xD7, 0x51, 0xEF, 0x4A, 0xAF, 0x01, 0x4A, 0xF5, 0xFD, 0x54, ++ 0x54, 0xEF, 0x4A, 0xAF, 0xD2, 0x4A, 0xF5, 0xFE, 0x4F, 0x11, 0x12, 0x10, 0x06, 0x90, 0x0B, 0x40, ++ 0xC4, 0xFF, 0xE0, 0x40, 0xE0, 0x20, 0x0F, 0x54, 0x7F, 0x2B, 0x7E, 0x12, 0x39, 0x65, 0xEF, 0xC2, ++ 0x65, 0xEE, 0x03, 0x70, 0x8E, 0x04, 0x60, 0x38, 0x71, 0x39, 0x8F, 0x38, 0xEF, 0x4A, 0xAF, 0x36, ++ 0x4A, 0xF5, 0xFD, 0x54, 0xE0, 0xEE, 0x07, 0x90, 0xE0, 0x30, 0x13, 0xC3, 0x7F, 0x20, 0x7E, 0x21, ++ 0xAD, 0x4E, 0xAC, 0x1D, 0x8C, 0x82, 0x8D, 0x4F, 0xA3, 0xFC, 0xE0, 0x83, 0x10, 0x12, 0xFD, 0xE0, ++ 0xEF, 0x4A, 0xAF, 0x28, 0x4A, 0xF5, 0x02, 0x44, 0x74, 0xEE, 0x07, 0x90, 0x37, 0xE5, 0xF0, 0x02, ++ 0x04, 0x70, 0x39, 0x65, 0x38, 0x65, 0x36, 0xE5, 0x38, 0x85, 0x09, 0x60, 0x37, 0x39, 0x85, 0x36, ++ 0xAA, 0x01, 0x3B, 0x75, 0x12, 0x37, 0xA9, 0x36, 0xF5, 0xE4, 0x3B, 0x03, 0xEF, 0x4A, 0xAF, 0x3B, ++ 0x4A, 0xF5, 0xFE, 0x54, 0xE0, 0xEE, 0x07, 0x90, 0x7E, 0x2B, 0xE3, 0x30, 0x90, 0x2B, 0x7F, 0x20, ++ 0x10, 0x12, 0x63, 0x06, 0x7F, 0x20, 0x7E, 0x20, 0xAD, 0x4C, 0xAC, 0x37, 0x8C, 0x82, 0x8D, 0x4D, ++ 0xA3, 0xFC, 0xE0, 0x83, 0x10, 0x12, 0xFD, 0xE0, 0xEF, 0x4A, 0xAF, 0x28, 0x4A, 0xF5, 0x01, 0x44, ++ 0x74, 0xEE, 0x07, 0x90, 0x09, 0x90, 0xF0, 0x08, 0x13, 0x13, 0xE0, 0x8E, 0x30, 0x1F, 0x54, 0x13, ++ 0xB2, 0x78, 0x14, 0xE0, 0x09, 0x0A, 0xB4, 0xE6, 0x44, 0xEF, 0x49, 0xAF, 0x80, 0x49, 0xF5, 0x02, ++ 0x06, 0xB2, 0x78, 0x16, 0xB2, 0x78, 0x11, 0x80, 0xAF, 0x09, 0x70, 0xE6, 0xFD, 0x54, 0xEF, 0x49, ++ 0x03, 0x80, 0x49, 0xF5, 0x90, 0x16, 0xB2, 0x78, 0x08, 0x74, 0x8E, 0x09, 0xF0, 0x07, 0x90, 0xF0, ++ 0x78, 0x07, 0x54, 0xE0, 0x7F, 0xE6, 0xF6, 0xB3, 0x02, 0x02, 0xB4, 0x00, 0x54, 0xEF, 0x01, 0x7F, ++ 0x33, 0x33, 0x33, 0x01, 0xAE, 0xFF, 0xF8, 0x54, 0xF7, 0x54, 0xEE, 0x49, 0x7F, 0x49, 0xF5, 0x4F, ++ 0x3A, 0x11, 0x12, 0xAC, 0x49, 0xAF, 0x07, 0x50, 0xF5, 0xFB, 0x54, 0xEF, 0xEE, 0x07, 0x90, 0x49, ++ 0x17, 0xE0, 0x30, 0xE0, 0xB4, 0xE6, 0xB3, 0x78, 0x49, 0xAF, 0x11, 0x01, 0xF5, 0x04, 0x44, 0xEF, ++ 0x76, 0xAC, 0x78, 0x49, 0xF4, 0x76, 0x08, 0x01, 0xAF, 0xF0, 0x01, 0x74, 0x13, 0x13, 0xEF, 0x49, ++ 0xE0, 0x20, 0x3F, 0x54, 0xEF, 0x49, 0xAF, 0x11, 0x54, 0x13, 0x13, 0x13, 0x06, 0xE0, 0x20, 0x1F, ++ 0xB4, 0xE6, 0xB3, 0x78, 0x49, 0xAF, 0x07, 0x03, 0xF5, 0xFD, 0x54, 0xEF, 0xEF, 0x49, 0xAF, 0x49, ++ 0x54, 0x13, 0x13, 0x13, 0x49, 0xAE, 0xFF, 0x01, 0x54, 0x13, 0x13, 0xEE, 0xAE, 0xFF, 0x4F, 0x01, ++ 0x13, 0xC3, 0xEE, 0x49, 0x54, 0x4F, 0x01, 0x54, 0x49, 0xAE, 0xFF, 0x01, 0x4F, 0xFE, 0x54, 0xEE, ++ 0x4A, 0xAF, 0x49, 0xF5, 0x29, 0xE0, 0x30, 0xEF, 0xE0, 0x81, 0x09, 0x90, 0x90, 0xF0, 0xFD, 0x54, ++ 0x54, 0xE0, 0x72, 0x09, 0x07, 0x90, 0xF0, 0xFE, 0x1F, 0x54, 0xE0, 0xE9, 0x7C, 0x00, 0x7E, 0xFF, ++ 0x12, 0x0A, 0x7D, 0x00, 0x24, 0xEF, 0x98, 0x02, 0xF6, 0xAB, 0x78, 0x39, 0xF6, 0x18, 0x3E, 0xE4, ++ 0x12, 0xAA, 0x7F, 0x22, 0x0E, 0x50, 0x3A, 0x11, 0xE0, 0x81, 0x09, 0x90, 0x90, 0xF0, 0x02, 0x44, ++ 0x44, 0xE0, 0x72, 0x09, 0x75, 0x22, 0xF0, 0x01, 0x39, 0x75, 0x23, 0x38, 0x4D, 0x06, 0x90, 0x57, ++ 0xF0, 0xEF, 0x54, 0xE0, 0xFB, 0x54, 0x21, 0xE5, 0x06, 0x90, 0x21, 0xF5, 0xFD, 0x54, 0xE0, 0x40, ++ 0xB0, 0x01, 0x90, 0xF0, 0xF0, 0x04, 0x44, 0xE0, 0xE0, 0xF8, 0x07, 0x90, 0xE0, 0xF0, 0xFB, 0x54, ++ 0x90, 0xF0, 0x08, 0x44, 0xC4, 0xE0, 0xAA, 0x0D, 0x90, 0xFF, 0x0F, 0x54, 0xC4, 0xE0, 0xAB, 0x0D, ++ 0xFF, 0x2F, 0x0F, 0x54, 0x24, 0xCF, 0x33, 0xE4, 0x34, 0xEF, 0xFD, 0x00, 0x07, 0x90, 0xFC, 0x04, ++ 0xF0, 0x75, 0xE0, 0x0C, 0xEC, 0xFF, 0xA4, 0x20, 0xAE, 0x78, 0xF0, 0x45, 0x08, 0x4F, 0xED, 0xF6, ++ 0x02, 0x04, 0x7F, 0xF6, 0xAF, 0x78, 0xED, 0x03, 0xFF, 0x01, 0x54, 0xE6, 0x74, 0x9F, 0xE4, 0xC3, ++ 0x54, 0x00, 0x94, 0x08, 0xE6, 0x18, 0xFC, 0x05, 0x08, 0xFE, 0x13, 0xC3, 0xEE, 0xFF, 0x13, 0xE6, ++ 0xEF, 0xF6, 0x18, 0x6C, 0xE5, 0x22, 0xF6, 0x08, 0x7E, 0x35, 0x60, 0x3B, 0x12, 0x3B, 0x7F, 0x20, ++ 0xA2, 0x78, 0x1B, 0x10, 0x76, 0x08, 0x34, 0x76, 0x63, 0x06, 0x90, 0xBC, 0x13, 0x13, 0xFF, 0xE0, ++ 0x92, 0x13, 0x3F, 0x54, 0x71, 0x11, 0xD2, 0x10, 0xE7, 0x07, 0x90, 0xA9, 0x90, 0xF0, 0x03, 0x74, ++ 0x54, 0xE0, 0x43, 0x06, 0x78, 0xE4, 0xF0, 0xDF, 0x21, 0xE5, 0xF6, 0x80, 0x21, 0xF5, 0xF7, 0x54, ++ 0x11, 0x12, 0xA2, 0x7F, 0x75, 0x06, 0x50, 0x3A, 0x39, 0x75, 0x24, 0x38, 0xFF, 0xE0, 0x22, 0xCA, ++ 0x3F, 0x54, 0x13, 0x13, 0xC2, 0x10, 0x92, 0x13, 0x67, 0x06, 0x90, 0x11, 0x03, 0xE0, 0x30, 0xE0, ++ 0x90, 0x1C, 0x10, 0x30, 0x30, 0xE0, 0x67, 0x06, 0x41, 0x81, 0x02, 0xE0, 0xE0, 0x66, 0x06, 0x90, ++ 0x78, 0xE0, 0xA3, 0xFE, 0x13, 0xC3, 0xCE, 0x02, 0xF9, 0xD8, 0x13, 0xCE, 0xC2, 0x72, 0xE0, 0x20, ++ 0xE4, 0x11, 0xA2, 0x10, 0x10, 0x54, 0xC4, 0x33, 0x90, 0xFF, 0x0F, 0x44, 0xC4, 0xE0, 0x41, 0x0D, ++ 0xC4, 0x01, 0x54, 0x13, 0x4F, 0x20, 0x54, 0x33, 0x61, 0x0D, 0x90, 0xF0, 0x54, 0x13, 0xC4, 0xE0, ++ 0x54, 0x33, 0xC4, 0x01, 0xF0, 0x10, 0x44, 0x20, 0x74, 0x40, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x18, ++ 0xF0, 0x38, 0x74, 0x60, 0xE0, 0x69, 0x06, 0x90, 0x0D, 0x90, 0x13, 0xC3, 0x09, 0xE0, 0x30, 0x4C, ++ 0x90, 0xF0, 0x11, 0x74, 0x80, 0xF0, 0x6C, 0x0D, 0xF0, 0x15, 0x74, 0x09, 0x74, 0x6C, 0x0D, 0x90, ++ 0x07, 0x90, 0xF0, 0x12, 0x30, 0x44, 0xE0, 0xF9, 0x3F, 0x54, 0xE0, 0xF0, 0x90, 0xF0, 0x80, 0x44, ++ 0x54, 0xE0, 0xFA, 0x07, 0xF0, 0x20, 0x44, 0xCF, 0xF0, 0xC0, 0x44, 0xE0, 0x80, 0xA8, 0x01, 0x90, ++ 0xA2, 0x10, 0xD2, 0x70, 0xC4, 0x33, 0xE4, 0x11, 0x0F, 0x44, 0xF0, 0x54, 0x61, 0x0D, 0x90, 0xFF, ++ 0x54, 0x13, 0xC4, 0xE0, 0x54, 0x33, 0xC4, 0x01, 0x90, 0xF0, 0x4F, 0xE0, 0xC4, 0xE0, 0x41, 0x0D, ++ 0xC4, 0x01, 0x54, 0x13, 0x44, 0x20, 0x54, 0x33, 0x0D, 0x90, 0xF0, 0x10, 0xF0, 0x38, 0x74, 0x40, ++ 0x74, 0x60, 0x0D, 0x90, 0x06, 0x90, 0xF0, 0x18, 0x13, 0xC3, 0xE0, 0x69, 0x30, 0x4C, 0x0D, 0x90, ++ 0x11, 0x74, 0x09, 0xE0, 0x6C, 0x0D, 0x90, 0xF0, 0x74, 0x09, 0x80, 0xF0, 0x0D, 0x90, 0xF0, 0x12, ++ 0xF0, 0x15, 0x74, 0x6C, 0xE0, 0xF9, 0x07, 0x90, 0x20, 0x44, 0xCF, 0x54, 0xC0, 0x44, 0xE0, 0xF0, ++ 0xFA, 0x07, 0x90, 0xF0, 0xF0, 0x30, 0x44, 0xE0, 0x44, 0x3F, 0x54, 0xE0, 0x01, 0x90, 0xF0, 0x80, ++ 0x09, 0x90, 0xE0, 0xA9, 0x10, 0xA2, 0xF0, 0x74, 0x01, 0x54, 0x33, 0xE4, 0xE0, 0x25, 0xE0, 0x25, ++ 0x63, 0x06, 0x90, 0xFF, 0x4F, 0xFB, 0x54, 0xE0, 0x3B, 0xE5, 0x22, 0xF0, 0xAC, 0xD1, 0x07, 0x60, ++ 0x71, 0x63, 0x06, 0x90, 0xEF, 0x49, 0xAF, 0x9E, 0xE0, 0x20, 0x13, 0xC3, 0xEF, 0x49, 0xAF, 0x0A, ++ 0x3F, 0x54, 0x13, 0x13, 0x7F, 0x27, 0xE0, 0x30, 0x3A, 0x11, 0x12, 0xA2, 0xA6, 0x78, 0x27, 0x50, ++ 0x76, 0x08, 0x02, 0x76, 0xEF, 0x49, 0xAF, 0x6C, 0x54, 0xC4, 0x02, 0x54, 0x49, 0xAE, 0xFF, 0xF0, ++ 0x4F, 0xDF, 0x54, 0xEE, 0x38, 0x75, 0x49, 0xF5, 0x1E, 0x39, 0x75, 0x26, 0xA2, 0x78, 0x07, 0x80, ++ 0x76, 0x08, 0x01, 0x76, 0xF0, 0x07, 0x90, 0x36, 0x64, 0x07, 0x54, 0xE0, 0xE4, 0x0B, 0x60, 0x02, ++ 0x78, 0xF6, 0xB0, 0x78, 0xF6, 0x08, 0xF6, 0xB4, 0x4A, 0xAF, 0x57, 0x80, 0x30, 0x13, 0xC3, 0xEF, ++ 0x4E, 0xAE, 0x4F, 0xE0, 0x82, 0x8F, 0x4F, 0xAF, 0x54, 0xE0, 0x83, 0x8E, 0xB4, 0x78, 0xFF, 0x40, ++ 0x4F, 0xBF, 0x54, 0xE6, 0xAF, 0x4E, 0xAE, 0xF6, 0x8E, 0x82, 0x8F, 0x4F, 0xA3, 0xFE, 0xE0, 0x83, ++ 0x70, 0x66, 0x08, 0xE0, 0x66, 0x18, 0xEE, 0x03, 0xB0, 0x78, 0x11, 0x70, 0x94, 0xC3, 0xE6, 0x06, ++ 0x75, 0x1E, 0x40, 0x02, 0x39, 0x75, 0x27, 0x38, 0xAE, 0x16, 0x80, 0x5E, 0x8F, 0x4F, 0xAF, 0x4E, ++ 0xE0, 0x83, 0x8E, 0x82, 0x78, 0xE0, 0xA3, 0xFE, 0x08, 0x06, 0xA6, 0xB4, 0xB0, 0x78, 0xE4, 0xF6, ++ 0x67, 0x06, 0x90, 0xF6, 0x02, 0xE0, 0x20, 0xE0, 0xA4, 0x7F, 0x0A, 0xC1, 0x40, 0x3A, 0x11, 0x12, ++ 0x12, 0xA6, 0x7F, 0x09, 0x02, 0x40, 0x3A, 0x11, 0x4A, 0xAF, 0x1D, 0xC1, 0x7D, 0xE0, 0x30, 0xEF, ++ 0x20, 0xEF, 0x49, 0xAF, 0xA5, 0x78, 0x77, 0xE0, 0x70, 0x46, 0x18, 0xE6, 0x63, 0x06, 0x90, 0x34, ++ 0x13, 0x13, 0xFF, 0xE0, 0xE0, 0x30, 0x3F, 0x54, 0x75, 0x06, 0x90, 0x07, 0xF0, 0x08, 0x44, 0xE0, ++ 0x11, 0xC2, 0x10, 0xC2, 0xAE, 0x78, 0xA9, 0x71, 0xFE, 0x07, 0x54, 0xE6, 0xE0, 0x25, 0xE6, 0x08, ++ 0xFE, 0x33, 0xEE, 0xFF, 0x78, 0xC8, 0x24, 0xEF, 0x34, 0xEE, 0xF6, 0xA5, 0x80, 0xF6, 0x18, 0x2A, ++ 0xE6, 0xAF, 0x78, 0x21, 0x90, 0xFF, 0x01, 0x54, 0xFD, 0xE0, 0x63, 0x06, 0x01, 0x54, 0x13, 0x13, ++ 0xE4, 0x01, 0x70, 0x6F, 0x06, 0x90, 0x07, 0x60, 0x08, 0x44, 0xE0, 0x75, 0xE6, 0xAF, 0x78, 0xF0, ++ 0xA6, 0x78, 0xA4, 0x71, 0x76, 0x08, 0x02, 0x76, 0xA6, 0x78, 0x22, 0x6C, 0x76, 0x08, 0x02, 0x76, ++ 0x76, 0xA4, 0x78, 0x6C, 0xC8, 0x76, 0x08, 0x2A, 0x71, 0x67, 0x06, 0x90, 0x3B, 0xE5, 0x22, 0x9E, ++ 0x20, 0x7E, 0x24, 0x60, 0x10, 0x12, 0x46, 0x7F, 0xE7, 0x07, 0x90, 0x1B, 0x90, 0xF0, 0x01, 0x74, ++ 0xFF, 0xE0, 0x63, 0x06, 0x3F, 0x54, 0x13, 0x13, 0xD2, 0x10, 0x92, 0x13, 0x78, 0xA9, 0x71, 0x11, ++ 0x08, 0x1D, 0x76, 0xA2, 0x49, 0xAF, 0x4C, 0x76, 0x54, 0x13, 0xC4, 0xEF, 0x30, 0x49, 0xAF, 0x07, ++ 0x54, 0xEF, 0x0A, 0xE0, 0x33, 0x33, 0x33, 0x02, 0x07, 0x80, 0xF8, 0x54, 0x25, 0x04, 0x54, 0xEF, ++ 0xFF, 0xE0, 0x25, 0xE0, 0x54, 0xEE, 0x49, 0xAE, 0x49, 0xF5, 0x4F, 0xEF, 0x11, 0x12, 0xA2, 0x7F, ++ 0xAF, 0x1B, 0x50, 0x3A, 0x13, 0xC4, 0xEF, 0x49, 0x06, 0x90, 0x07, 0x54, 0x05, 0xE0, 0x20, 0x4B, ++ 0x80, 0xF0, 0x21, 0x74, 0xF0, 0x81, 0x74, 0x03, 0x75, 0x2A, 0x38, 0x75, 0x49, 0xAF, 0x2B, 0x39, ++ 0x0F, 0x54, 0xC4, 0xEF, 0x7E, 0x14, 0xE0, 0x20, 0x12, 0x52, 0x7F, 0x20, 0x06, 0x90, 0x1B, 0x10, ++ 0x10, 0x44, 0xE0, 0x4D, 0x24, 0x38, 0x75, 0xF0, 0x22, 0xCA, 0x39, 0x75, 0xDD, 0x7F, 0x20, 0x7E, ++ 0xE4, 0x1B, 0x10, 0x12, 0x78, 0xF6, 0xB0, 0x78, 0x76, 0x08, 0xF6, 0xA2, 0x2A, 0x76, 0x08, 0x9B, ++ 0x78, 0xC8, 0x76, 0x08, 0x08, 0xFD, 0x76, 0xA8, 0xB4, 0x78, 0xE8, 0x76, 0x78, 0xF6, 0x08, 0xF6, ++ 0x08, 0x02, 0x76, 0xA6, 0xBA, 0x78, 0x6C, 0x76, 0xF6, 0x08, 0x01, 0x76, 0x06, 0x90, 0xF6, 0x08, ++ 0xA3, 0xFF, 0xE0, 0x48, 0xAD, 0x4C, 0xAC, 0xE0, 0x8C, 0x82, 0x8D, 0x4D, 0xA3, 0xF0, 0xCF, 0x83, ++ 0x4C, 0xAE, 0xF0, 0xEF, 0x82, 0x8F, 0x4D, 0xAF, 0x83, 0xC0, 0x83, 0x8E, 0xFF, 0xE0, 0x82, 0xC0, ++ 0xE0, 0x9F, 0x01, 0x90, 0x01, 0x54, 0x13, 0xC3, 0x13, 0xC4, 0xEF, 0xFE, 0x01, 0x54, 0x13, 0x13, ++ 0x7F, 0x54, 0xEF, 0xFD, 0x54, 0x4E, 0xED, 0xFF, 0x33, 0x33, 0xC4, 0x01, 0x4F, 0x80, 0x54, 0x33, ++ 0x83, 0xD0, 0x82, 0xD0, 0xAF, 0x4C, 0xAE, 0xF0, 0x8E, 0x82, 0x8F, 0x4D, 0x08, 0x54, 0xE0, 0x83, ++ 0xFF, 0xF0, 0x54, 0xC4, 0x54, 0xEE, 0x49, 0xAE, 0x49, 0xF5, 0x4F, 0x7F, 0x4A, 0x06, 0x90, 0xE4, ++ 0x90, 0xF0, 0xA3, 0xF0, 0x54, 0xE0, 0x4D, 0x06, 0x54, 0xE0, 0xF0, 0xFE, 0x54, 0xE0, 0xF0, 0xF7, ++ 0x90, 0xE4, 0xF0, 0xFD, 0xA3, 0xF0, 0xA0, 0x01, 0xE7, 0x07, 0x90, 0xF0, 0x3B, 0xE5, 0x22, 0xF0, ++ 0x20, 0x7E, 0x24, 0x60, 0x10, 0x12, 0x61, 0x7F, 0x4D, 0x06, 0x90, 0x1B, 0xF0, 0x01, 0x44, 0xE0, ++ 0x4D, 0xAF, 0x4C, 0xAE, 0x83, 0x8E, 0x82, 0x8F, 0xF0, 0x40, 0x44, 0xE0, 0x44, 0xE6, 0xB4, 0x78, ++ 0x78, 0xE4, 0xF6, 0x40, 0x07, 0x90, 0xF6, 0xB0, 0x07, 0x54, 0xE0, 0xF0, 0x06, 0x60, 0x02, 0x64, ++ 0x75, 0x23, 0x38, 0x75, 0x4A, 0xAF, 0x57, 0x39, 0x30, 0x13, 0xC3, 0xEF, 0x4E, 0xAE, 0x51, 0xE0, ++ 0x82, 0x8F, 0x4F, 0xAF, 0xFE, 0xE0, 0x83, 0x8E, 0xB5, 0x78, 0xE0, 0xA3, 0xEE, 0x03, 0x70, 0x66, ++ 0x10, 0x70, 0x66, 0x18, 0xE6, 0x06, 0xB0, 0x78, 0x40, 0x02, 0x94, 0xD3, 0x27, 0x38, 0x75, 0x32, ++ 0x22, 0xF0, 0x39, 0x75, 0xF6, 0xB0, 0x78, 0xE4, 0x54, 0xE6, 0xB4, 0x78, 0x4E, 0xAE, 0xF6, 0xBF, ++ 0x82, 0x8F, 0x4F, 0xAF, 0xFE, 0xE0, 0x83, 0x8E, 0x66, 0x08, 0xE0, 0xA3, 0x18, 0xEE, 0x03, 0x70, ++ 0x75, 0x06, 0x60, 0x66, 0x39, 0x75, 0x23, 0x38, 0xE6, 0xB4, 0x78, 0x57, 0x22, 0xF6, 0x40, 0x44, ++ 0x03, 0x60, 0x3B, 0xE5, 0xAF, 0xD6, 0x2B, 0x12, 0xE0, 0x30, 0xEF, 0x4A, 0xE6, 0xB1, 0x78, 0x09, ++ 0x40, 0x00, 0x94, 0xD3, 0xB1, 0x78, 0x16, 0x01, 0x90, 0x40, 0x70, 0xE6, 0x13, 0xE0, 0x4D, 0x06, ++ 0x30, 0x3F, 0x54, 0x13, 0x13, 0xE0, 0x2F, 0xE0, 0x1F, 0x54, 0x13, 0x13, 0xAE, 0x26, 0xE0, 0x30, ++ 0x8F, 0x4D, 0xAF, 0x4C, 0xE0, 0x83, 0x8E, 0x82, 0x13, 0x13, 0x13, 0xC4, 0xE0, 0x20, 0x01, 0x54, ++ 0x50, 0x06, 0x90, 0x0D, 0x13, 0x13, 0xC4, 0xE0, 0x30, 0x01, 0x54, 0x13, 0x38, 0x75, 0x07, 0xE0, ++ 0x4C, 0x39, 0x75, 0x28, 0x2A, 0x38, 0x75, 0x22, 0x22, 0x2B, 0x39, 0x75, 0xE0, 0xF0, 0x07, 0x90, ++ 0x02, 0x64, 0x07, 0x54, 0x38, 0x75, 0x06, 0x60, 0x57, 0x39, 0x75, 0x23, 0x02, 0x60, 0x3B, 0xE5, ++ 0xBA, 0x78, 0x77, 0x31, 0x70, 0x07, 0x64, 0xE6, 0xEF, 0x21, 0xAF, 0x4B, 0x54, 0x13, 0x13, 0x13, ++ 0x65, 0xE0, 0x30, 0x1F, 0xE0, 0x4E, 0x06, 0x90, 0x78, 0xE0, 0xA3, 0xFE, 0x08, 0x06, 0xA6, 0xB7, ++ 0xEF, 0x49, 0xAF, 0xF6, 0x54, 0xC4, 0x80, 0x54, 0xE6, 0x18, 0xFF, 0x0F, 0xF6, 0x4F, 0xF7, 0x54, ++ 0xE6, 0x08, 0xFF, 0xE6, 0x4D, 0xAD, 0x4C, 0xAC, 0x83, 0x8C, 0x82, 0x8D, 0xEF, 0xA3, 0xF0, 0xCF, ++ 0x4E, 0x06, 0x90, 0xF0, 0x13, 0x13, 0xC4, 0xE0, 0x20, 0x01, 0x54, 0x13, 0xBA, 0x78, 0x2B, 0xE0, ++ 0x25, 0x80, 0x08, 0x76, 0x21, 0x60, 0x3B, 0xE5, 0x54, 0xEF, 0x49, 0xAF, 0x0F, 0x54, 0xC4, 0x80, ++ 0xE6, 0xB7, 0x78, 0xFF, 0xF6, 0x4F, 0xF7, 0x54, 0xE6, 0x08, 0xFF, 0xE6, 0x4D, 0xAD, 0x4C, 0xAC, ++ 0x83, 0x8C, 0x82, 0x8D, 0xEF, 0xA3, 0xF0, 0xCF, 0xEF, 0x4A, 0xAF, 0xF0, 0xE0, 0x20, 0x13, 0xC3, ++ 0xAE, 0x76, 0x21, 0x02, 0x8F, 0x4F, 0xAF, 0x4E, 0xE0, 0x83, 0x8E, 0x82, 0xAE, 0xF0, 0xBF, 0x54, ++ 0x8F, 0x4F, 0xAF, 0x4E, 0xE0, 0x83, 0x8E, 0x82, 0x78, 0xE0, 0xA3, 0xFE, 0x03, 0x70, 0x66, 0xB5, ++ 0x70, 0x66, 0x18, 0xEE, 0x06, 0xB0, 0x78, 0x5B, 0x02, 0x94, 0xC3, 0xE6, 0x02, 0x76, 0x68, 0x40, ++ 0x4F, 0xAF, 0x4E, 0xAE, 0x83, 0x8E, 0x82, 0x8F, 0x13, 0x13, 0x13, 0xE0, 0xAE, 0xFF, 0x01, 0x54, ++ 0x13, 0xC4, 0xEE, 0x49, 0x6F, 0x01, 0x54, 0x13, 0xBA, 0x78, 0x4C, 0x60, 0x0B, 0x07, 0xB4, 0xE6, ++ 0x13, 0xEF, 0x21, 0xAF, 0x1F, 0x54, 0x13, 0x13, 0x75, 0x3B, 0xE0, 0x30, 0x39, 0x75, 0x27, 0x38, ++ 0xE6, 0xBA, 0x78, 0x5E, 0x2E, 0x70, 0x07, 0x64, 0xF7, 0x54, 0x21, 0xE5, 0x64, 0xE6, 0x21, 0xF5, ++ 0xE6, 0x23, 0x60, 0x01, 0x1E, 0x60, 0x08, 0x64, 0xE0, 0x74, 0x06, 0x90, 0x22, 0xF0, 0x10, 0x44, ++ 0x4F, 0xAF, 0x4E, 0xAE, 0x83, 0x8E, 0x82, 0x8F, 0xE0, 0xA3, 0xFE, 0xE0, 0x06, 0xA6, 0xB4, 0x78, ++ 0x78, 0xE4, 0xF6, 0x08, 0x7E, 0x22, 0xF6, 0xB0, 0x12, 0xC1, 0x7F, 0x20, 0x78, 0xE4, 0x1B, 0x10, ++ 0xB4, 0x78, 0xF6, 0xB0, 0x78, 0xF6, 0x08, 0xF6, 0xFA, 0x24, 0xE6, 0xBA, 0x60, 0x14, 0x30, 0x60, ++ 0x44, 0x60, 0x14, 0x47, 0x3D, 0x70, 0x07, 0x24, 0xE0, 0x9F, 0x01, 0x90, 0xE0, 0x30, 0x13, 0xC3, ++ 0x76, 0xBA, 0x78, 0x06, 0x90, 0x31, 0x80, 0x05, 0xC4, 0xE0, 0x48, 0x06, 0x54, 0x13, 0x13, 0x13, ++ 0x20, 0xBA, 0x78, 0x01, 0x08, 0x76, 0x04, 0xE0, 0x07, 0x76, 0x1E, 0x80, 0x06, 0x90, 0x1A, 0x80, ++ 0x13, 0xC4, 0xE0, 0x48, 0x01, 0x54, 0x13, 0x13, 0xE0, 0x20, 0xBA, 0x78, 0x80, 0x08, 0x76, 0x04, ++ 0x80, 0x07, 0x76, 0x07, 0x06, 0xBA, 0x78, 0x03, 0x24, 0xE6, 0xBA, 0x78, 0x24, 0x25, 0x60, 0xFA, ++ 0x24, 0x10, 0x60, 0xFE, 0x78, 0x37, 0x70, 0x03, 0xE4, 0x0A, 0x76, 0xB8, 0x44, 0xE6, 0xF6, 0x18, ++ 0x78, 0x0A, 0x80, 0x80, 0xE4, 0x01, 0x76, 0xB8, 0x54, 0xE6, 0xF6, 0x18, 0x44, 0xE6, 0xF6, 0x7F, ++ 0x1A, 0x80, 0xF6, 0x20, 0xE0, 0x9E, 0x01, 0x90, 0x78, 0xE0, 0xA3, 0xFE, 0x08, 0x06, 0xA6, 0xB7, ++ 0x48, 0x06, 0x90, 0xF6, 0xFF, 0x80, 0x54, 0xE0, 0x7F, 0x54, 0xE6, 0x18, 0x20, 0x7E, 0xF6, 0x4F, ++ 0xBA, 0x78, 0xCE, 0x7F, 0x00, 0x7C, 0xFD, 0xE6, 0x51, 0x28, 0x10, 0x02, 0xEF, 0x49, 0xAF, 0x4F, ++ 0x90, 0x15, 0xE0, 0x30, 0x44, 0xE0, 0x74, 0x06, 0x20, 0x7E, 0xF0, 0x08, 0x10, 0x12, 0x6C, 0x7F, ++ 0x23, 0x38, 0x75, 0x1B, 0x22, 0x57, 0x39, 0x75, 0x75, 0x2B, 0x38, 0x75, 0xAF, 0x22, 0xC2, 0x39, ++ 0xFE, 0x54, 0xEF, 0x49, 0x20, 0x7E, 0x49, 0xF5, 0x10, 0x12, 0x7B, 0x7F, 0x06, 0x90, 0xE4, 0x1B, ++ 0xF0, 0xA3, 0xF0, 0x70, 0xE0, 0x49, 0x06, 0x90, 0x01, 0x64, 0x1F, 0x54, 0xBA, 0x61, 0x02, 0x60, ++ 0xE0, 0x4B, 0x06, 0x90, 0x01, 0x64, 0x1F, 0x54, 0xBA, 0x61, 0x02, 0x60, 0xE0, 0x4A, 0x06, 0x90, ++ 0xFF, 0xE0, 0xA3, 0xFE, 0xE0, 0x48, 0x06, 0x90, 0xF6, 0xB7, 0x78, 0x5E, 0x08, 0x5F, 0xE0, 0xA3, ++ 0x30, 0xE6, 0x18, 0xF6, 0x06, 0x90, 0x0A, 0xE0, 0xFC, 0x54, 0xE0, 0x71, 0x27, 0x80, 0x01, 0x44, ++ 0xC4, 0xE6, 0xB8, 0x78, 0x54, 0x13, 0x13, 0x13, 0x0A, 0xE0, 0x30, 0x01, 0xE0, 0x71, 0x06, 0x90, ++ 0x01, 0x44, 0xFC, 0x54, 0xB8, 0x78, 0x28, 0x80, 0x13, 0x13, 0xC4, 0xE6, 0xE0, 0x30, 0x03, 0x54, ++ 0x71, 0x06, 0x90, 0x0D, 0xF0, 0xFC, 0x54, 0xE0, 0xF0, 0x08, 0x44, 0xE0, 0xB8, 0x78, 0x1E, 0x80, ++ 0x54, 0x13, 0xC4, 0xE6, 0x0D, 0xE0, 0x30, 0x07, 0xE0, 0x71, 0x06, 0x90, 0xE0, 0xF0, 0xFC, 0x54, ++ 0x80, 0xF0, 0xF7, 0x54, 0xEF, 0x49, 0xAF, 0x07, 0x49, 0xF5, 0x01, 0x44, 0xE0, 0x9F, 0x01, 0x90, ++ 0xE0, 0x30, 0x13, 0xC3, 0xA1, 0x01, 0x90, 0x17, 0x30, 0x13, 0xC3, 0xE0, 0x06, 0x90, 0x0E, 0xE0, ++ 0x03, 0x54, 0xE0, 0x71, 0x04, 0x01, 0xBF, 0xFF, 0xF0, 0x04, 0x44, 0xE0, 0x13, 0xE6, 0xB7, 0x78, ++ 0x30, 0x3F, 0x54, 0x13, 0x06, 0x90, 0x09, 0xE0, 0x30, 0x44, 0xE0, 0x71, 0x78, 0x36, 0x80, 0xF0, ++ 0x13, 0x13, 0xE6, 0xB7, 0x30, 0x1F, 0x54, 0x13, 0x06, 0x90, 0x24, 0xE0, 0xE2, 0x30, 0xE0, 0x48, ++ 0x71, 0x06, 0x90, 0x0B, 0x44, 0xCF, 0x54, 0xE0, 0x19, 0x80, 0xF0, 0x20, 0xE0, 0x4A, 0x06, 0x90, ++ 0x30, 0x71, 0x06, 0x90, 0x54, 0xE0, 0x0B, 0xE2, 0xF0, 0x10, 0x44, 0xCF, 0x06, 0x90, 0x07, 0x80, ++ 0xCF, 0x54, 0xE0, 0x71, 0x76, 0x80, 0x78, 0xF0, 0x7F, 0x20, 0x7E, 0x01, 0x1B, 0x10, 0x12, 0x85, ++ 0xF6, 0xB0, 0x78, 0xE4, 0xE0, 0x71, 0x06, 0x90, 0x78, 0xFF, 0x03, 0x54, 0x9F, 0xC3, 0xE6, 0xB0, ++ 0x20, 0x7E, 0x0C, 0x50, 0x10, 0x12, 0x90, 0x7F, 0x06, 0xB0, 0x78, 0x1B, 0x06, 0x90, 0xE6, 0x80, ++ 0x13, 0x13, 0xE0, 0x71, 0x30, 0x1F, 0x54, 0x13, 0x20, 0x7E, 0x06, 0xE0, 0x04, 0x80, 0x92, 0x7F, ++ 0x96, 0x7F, 0x20, 0x7E, 0x90, 0x1B, 0x10, 0x12, 0x13, 0xE0, 0x71, 0x06, 0x30, 0x3F, 0x54, 0x13, ++ 0x20, 0x7E, 0x07, 0xE0, 0x10, 0x12, 0x9A, 0x7F, 0x7F, 0x20, 0x7E, 0x1B, 0x71, 0x06, 0x90, 0x9F, ++ 0x03, 0x54, 0xC4, 0xE0, 0x02, 0x00, 0x7C, 0xFD, 0x49, 0xAF, 0x28, 0x10, 0xF5, 0x01, 0x44, 0xEF, ++ 0x01, 0x90, 0x22, 0x49, 0xFB, 0x54, 0xE0, 0xB0, 0x02, 0x34, 0x75, 0xF0, 0x75, 0x56, 0x35, 0x75, ++ 0x31, 0x75, 0x01, 0x30, 0x20, 0x7E, 0x22, 0xC5, 0x10, 0x12, 0xA7, 0x7F, 0x76, 0xB1, 0x78, 0x1B, ++ 0xE6, 0xBB, 0x78, 0x07, 0x07, 0x60, 0xFA, 0x24, 0x24, 0x08, 0x60, 0x14, 0x78, 0x1F, 0x70, 0x06, ++ 0x78, 0x07, 0x76, 0xBB, 0x13, 0xC4, 0xE6, 0xB4, 0xE0, 0x30, 0x07, 0x54, 0x07, 0x54, 0xE6, 0x14, ++ 0x64, 0xE6, 0x08, 0xFE, 0x09, 0x70, 0x4E, 0x0A, 0x05, 0x76, 0xBB, 0x78, 0xBB, 0x78, 0x03, 0x80, ++ 0xE6, 0xBB, 0x78, 0x06, 0x35, 0x60, 0xFA, 0x24, 0x3F, 0x70, 0x05, 0x24, 0xFF, 0xE6, 0xB4, 0x78, ++ 0x06, 0x90, 0xE6, 0x08, 0xA3, 0xF0, 0xCF, 0x4A, 0xE6, 0x18, 0xF0, 0xEF, 0x13, 0xC3, 0x20, 0x54, ++ 0x43, 0x06, 0x90, 0xFF, 0x4F, 0xEF, 0x54, 0xE0, 0x4A, 0x06, 0x90, 0xF0, 0xC4, 0x80, 0x54, 0xE0, ++ 0x90, 0xFF, 0x0F, 0x54, 0x54, 0xE0, 0x4D, 0x06, 0x80, 0xF0, 0x4F, 0xF7, 0xE6, 0xB4, 0x78, 0x0E, ++ 0x90, 0xE6, 0x08, 0xFF, 0xF0, 0xCF, 0xA0, 0x01, 0x78, 0xF0, 0xEF, 0xA3, 0x01, 0x64, 0xE6, 0xBB, ++ 0xB4, 0x78, 0x0E, 0x60, 0xE6, 0x08, 0xFF, 0xE6, 0xCF, 0x50, 0x06, 0x90, 0xF0, 0xEF, 0xA3, 0xF0, ++ 0xE0, 0x74, 0x06, 0x90, 0x7E, 0xF0, 0x20, 0x44, 0x78, 0xB2, 0x7F, 0x20, 0x7C, 0xFD, 0xE6, 0xBB, ++ 0x28, 0x10, 0x12, 0x00, 0xE0, 0x4D, 0x06, 0x90, 0x78, 0xF0, 0x02, 0x44, 0x08, 0x54, 0xE6, 0xB4, ++ 0x54, 0x33, 0x33, 0x33, 0x49, 0xAE, 0xFF, 0xF8, 0x4F, 0xBF, 0x54, 0xEE, 0x49, 0xAF, 0x49, 0xF5, ++ 0x13, 0x13, 0xC4, 0xEF, 0x7F, 0x01, 0x54, 0x13, 0x02, 0xE0, 0x20, 0x00, 0x54, 0xEF, 0x01, 0x7F, ++ 0x33, 0x33, 0xC4, 0x01, 0xFF, 0x80, 0x54, 0x33, 0x54, 0xEE, 0x49, 0xAE, 0x49, 0xF5, 0x4F, 0x7F, ++ 0xB4, 0xE6, 0xBA, 0x78, 0x06, 0x90, 0x07, 0x01, 0xDF, 0x54, 0xE0, 0x48, 0x00, 0x22, 0x22, 0xF0, ++ 0xE0, 0x43, 0x07, 0x90, 0xE4, 0x0C, 0xE5, 0x30, 0xF0, 0xB3, 0x01, 0x90, 0x27, 0xA9, 0x26, 0xAA, ++ 0xE5, 0x3B, 0x03, 0x02, 0xE4, 0x05, 0x60, 0x2E, 0x27, 0xF5, 0x26, 0xF5, 0x44, 0x43, 0x09, 0x22, ++ 0x4C, 0x44, 0x49, 0x20, 0x09, 0x00, 0x0A, 0x45, 0x41, 0x57, 0x44, 0x43, 0x00, 0x0A, 0x54, 0x49, ++ 0x4D, 0x44, 0x43, 0x09, 0x00, 0x0A, 0x41, 0x45, 0x2D, 0x2D, 0x2D, 0x2D, 0x44, 0x25, 0x00, 0x0A, ++ 0x44, 0x43, 0x00, 0x0A, 0x65, 0x6E, 0x6F, 0x44, 0x44, 0x43, 0x00, 0x0A, 0x2D, 0x47, 0x41, 0x49, ++ 0x74, 0x69, 0x78, 0x65, 0x43, 0x09, 0x00, 0x0A, 0x54, 0x45, 0x53, 0x44, 0x44, 0x43, 0x00, 0x0A, ++ 0x25, 0x2D, 0x4B, 0x50, 0x09, 0x00, 0x0A, 0x78, 0x64, 0x25, 0x3A, 0x52, 0x3A, 0x4F, 0x00, 0x20, ++ 0x00, 0x20, 0x64, 0x25, 0x64, 0x25, 0x3A, 0x53, 0x3A, 0x44, 0x00, 0x20, 0x00, 0x20, 0x64, 0x25, ++ 0x44, 0x25, 0x3A, 0x50, 0x6D, 0x09, 0x00, 0x0A, 0x68, 0x63, 0x74, 0x61, 0x00, 0x0A, 0x64, 0x65, ++ 0x0D, 0x60, 0x2E, 0xE5, 0xE0, 0xAE, 0x01, 0x90, 0x31, 0xF0, 0x10, 0x44, 0x84, 0x78, 0xE4, 0x08, ++ 0x13, 0x06, 0x90, 0xF6, 0xF6, 0x83, 0x78, 0xE0, 0xE0, 0x12, 0x06, 0x90, 0x07, 0x54, 0x13, 0xC4, ++ 0x0A, 0x06, 0xBF, 0xFF, 0xE0, 0x20, 0x20, 0xE5, 0x30, 0x13, 0xC3, 0x05, 0x2C, 0x75, 0x08, 0xE0, ++ 0xA9, 0x2D, 0x75, 0x26, 0x83, 0x78, 0x18, 0x80, 0x0C, 0xE0, 0x30, 0xE6, 0x0E, 0x70, 0xE6, 0x08, ++ 0x75, 0x26, 0x2C, 0x75, 0x06, 0x80, 0x77, 0x2D, 0x75, 0x22, 0x2C, 0x75, 0x2B, 0xE5, 0xCD, 0x2D, ++ 0x04, 0x70, 0x2D, 0x65, 0x2C, 0x65, 0x2A, 0xE5, 0x2C, 0x85, 0x09, 0x60, 0x2B, 0x2D, 0x85, 0x2A, ++ 0xAA, 0x01, 0x2F, 0x75, 0x12, 0x2B, 0xA9, 0x2A, 0xF5, 0xE4, 0x3B, 0x03, 0xE6, 0x83, 0x78, 0x2F, ++ 0x13, 0x06, 0x90, 0xFF, 0x22, 0xF0, 0xEF, 0xE0, 0x56, 0x7F, 0x20, 0x7E, 0xE4, 0x1B, 0x10, 0x12, ++ 0xF0, 0x7B, 0x07, 0x90, 0x74, 0x7C, 0x07, 0x90, 0x0D, 0x90, 0xF0, 0x02, 0xF0, 0x20, 0x74, 0x80, ++ 0x81, 0x0D, 0x90, 0xE4, 0xA2, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0xAA, 0x74, 0x36, 0x74, 0x8C, 0x0D, ++ 0xF8, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x0F, 0x74, 0xE4, 0x74, 0xF9, 0x07, 0xFA, 0x07, 0x90, 0xF0, ++ 0xFD, 0x07, 0x90, 0xF0, 0x74, 0xF0, 0x03, 0x74, 0x08, 0x90, 0xF0, 0x01, 0xF0, 0x44, 0x74, 0x03, ++ 0xF0, 0x04, 0x08, 0x90, 0x0B, 0x0A, 0x90, 0xE4, 0x0A, 0x0A, 0x90, 0xF0, 0x09, 0x0A, 0x90, 0xF0, ++ 0xFE, 0x09, 0x90, 0xF0, 0xFD, 0x09, 0x90, 0xF0, 0xFC, 0x09, 0x90, 0xF0, 0x08, 0x0A, 0x90, 0xF0, ++ 0x90, 0xF0, 0x03, 0x74, 0x90, 0xF0, 0x01, 0x0A, 0x90, 0xF0, 0xFB, 0x09, 0x90, 0xF0, 0xF4, 0x09, ++ 0x35, 0x74, 0x02, 0x0A, 0xF5, 0x09, 0x90, 0xF0, 0x03, 0x0A, 0x90, 0xF0, 0x90, 0xF0, 0x05, 0x74, ++ 0x90, 0xF0, 0xF6, 0x09, 0xDC, 0x74, 0x04, 0x0A, 0xF7, 0x09, 0x90, 0xF0, 0xFF, 0x09, 0x90, 0xF0, ++ 0x90, 0xF0, 0x01, 0x74, 0x90, 0xF0, 0x0C, 0x0A, 0x90, 0xF0, 0xFB, 0x09, 0x90, 0xF0, 0x08, 0x0A, ++ 0x90, 0xF0, 0xF4, 0x09, 0x90, 0xF0, 0x01, 0x0A, 0x0B, 0x74, 0xE6, 0x09, 0xE5, 0x09, 0x90, 0xF0, ++ 0x90, 0xF0, 0x03, 0x74, 0x0A, 0x74, 0xE6, 0x09, 0xE5, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x02, 0x74, ++ 0x04, 0x74, 0xCD, 0x09, 0xD4, 0x09, 0x90, 0xF0, 0x09, 0x90, 0xF0, 0x14, 0xF0, 0x01, 0x74, 0xD5, ++ 0x74, 0xD6, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x05, 0xF0, 0x03, 0x74, 0xD7, 0x90, 0xF0, 0x01, 0x74, ++ 0x74, 0x74, 0xD9, 0x09, 0xD2, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x03, 0x74, 0x18, 0x74, 0xD3, 0x09, ++ 0xD2, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x05, 0x74, 0xD0, 0x09, 0xB6, 0x07, 0x90, 0xF0, ++ 0x90, 0xF0, 0x03, 0x74, 0xE4, 0xF0, 0xB7, 0x07, 0xF0, 0xB8, 0x07, 0x90, 0xF0, 0xB7, 0x07, 0x90, ++ 0x74, 0xB0, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x1D, 0xF0, 0xFF, 0x74, 0xAE, 0x74, 0xAF, 0x07, 0x90, ++ 0x09, 0x90, 0xF0, 0x2A, 0xF0, 0x16, 0x74, 0xA4, 0x04, 0xA3, 0x09, 0x90, 0x09, 0x90, 0xE4, 0xF0, ++ 0x09, 0x90, 0xF0, 0xA5, 0xF0, 0x03, 0x74, 0xA8, 0x74, 0xA6, 0x09, 0x90, 0xFF, 0xE4, 0xF0, 0x0C, ++ 0x79, 0x08, 0x90, 0xFE, 0x08, 0x90, 0xFD, 0xE0, 0xFD, 0x5D, 0xE0, 0x14, 0xE0, 0xDE, 0x08, 0x90, ++ 0x09, 0x90, 0xFD, 0x5D, 0x64, 0x5D, 0xE0, 0x43, 0xC3, 0x11, 0x60, 0x01, 0xEE, 0xFF, 0x94, 0xEF, ++ 0x08, 0x50, 0x00, 0x94, 0x00, 0xBF, 0x0F, 0x00, 0xD5, 0x80, 0x0E, 0x01, 0x74, 0xB0, 0x09, 0x90, ++ 0x09, 0x90, 0xF0, 0x43, 0x09, 0x90, 0xF0, 0xB2, 0x09, 0x90, 0xF0, 0xB4, 0x09, 0x90, 0xF0, 0xB6, ++ 0xF0, 0x53, 0x74, 0xB8, 0xBB, 0x51, 0x03, 0x7F, 0x74, 0xB0, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x42, ++ 0x09, 0x90, 0xF0, 0xB2, 0x09, 0x90, 0xF0, 0xB4, 0x09, 0x90, 0xF0, 0xB6, 0xF0, 0x52, 0x74, 0xB8, ++ 0x74, 0x80, 0x00, 0x90, 0x74, 0xA3, 0xF0, 0x02, 0x90, 0x22, 0xF0, 0x05, 0xF0, 0xEF, 0x9D, 0x09, ++ 0xF0, 0x9F, 0x09, 0x90, 0xF0, 0xA0, 0x09, 0x90, 0xF0, 0xA1, 0x09, 0x90, 0x60, 0x2F, 0xE5, 0x22, ++ 0x7F, 0x20, 0x7E, 0x07, 0x1B, 0x10, 0x12, 0x1D, 0x60, 0x2F, 0xE5, 0x22, 0x7F, 0x20, 0x7E, 0x2F, ++ 0x1B, 0x10, 0x12, 0x30, 0x01, 0x76, 0x81, 0x78, 0x7F, 0xF4, 0x76, 0x08, 0x90, 0xBB, 0x51, 0x02, ++ 0x01, 0x74, 0x7B, 0x07, 0x00, 0x00, 0x90, 0xF0, 0x83, 0xAE, 0x82, 0xAF, 0x80, 0x94, 0xEF, 0xC3, ++ 0x40, 0x00, 0x94, 0xEE, 0xE4, 0xAB, 0x61, 0x02, 0xEC, 0x80, 0xA3, 0xF0, 0x11, 0x12, 0x81, 0x7F, ++ 0x61, 0x02, 0x40, 0x3A, 0x51, 0x1A, 0x7F, 0xAB, 0x07, 0x90, 0xE4, 0xBB, 0x56, 0xF5, 0xF0, 0x7B, ++ 0x78, 0x57, 0xF5, 0xE4, 0x13, 0x13, 0xE6, 0x83, 0xE0, 0x30, 0x3F, 0x54, 0x7F, 0x20, 0x7E, 0x42, ++ 0x1B, 0x10, 0x12, 0x38, 0xAF, 0x58, 0xF5, 0xE4, 0xE5, 0x00, 0x7E, 0x58, 0xB4, 0x00, 0x7C, 0x57, ++ 0x80, 0x7D, 0x04, 0x03, 0x20, 0x7D, 0x02, 0x80, 0xEC, 0x9D, 0xEF, 0xC3, 0xEE, 0xF8, 0x80, 0x64, ++ 0x50, 0x98, 0x80, 0x64, 0xAD, 0x57, 0xAB, 0x1A, 0xB1, 0x58, 0xAF, 0x56, 0xAD, 0x06, 0xAC, 0xD7, ++ 0x7F, 0x20, 0x7E, 0x07, 0x28, 0x10, 0x12, 0x3E, 0x05, 0xFD, 0x18, 0x20, 0xE5, 0xC8, 0x80, 0x58, ++ 0x0A, 0x03, 0xB4, 0x57, 0x71, 0x56, 0xAF, 0xFD, 0x08, 0x18, 0x30, 0xAC, 0x57, 0xAD, 0xFB, 0x80, ++ 0xF7, 0xB1, 0x56, 0xAF, 0x57, 0xE5, 0x57, 0x05, 0x40, 0x04, 0x94, 0xC3, 0xE5, 0x56, 0x05, 0x96, ++ 0x04, 0x94, 0xC3, 0x56, 0x83, 0x78, 0x8A, 0x40, 0xF6, 0xFE, 0x54, 0xE6, 0x78, 0xF6, 0x08, 0xE4, ++ 0xF6, 0x08, 0xF6, 0x81, 0x42, 0x7F, 0x20, 0x7E, 0x22, 0x1B, 0x10, 0x12, 0x5A, 0x8D, 0x59, 0x8F, ++ 0xE0, 0x81, 0x00, 0x90, 0x00, 0x90, 0x69, 0xF5, 0x6A, 0xF5, 0xE0, 0x80, 0x85, 0x6D, 0x59, 0x85, ++ 0x20, 0x7E, 0x6E, 0x5A, 0x6E, 0xAD, 0x5E, 0x7F, 0x10, 0x12, 0x6D, 0xAC, 0x75, 0x59, 0xE5, 0x28, ++ 0xF5, 0xA4, 0x08, 0xF0, 0x67, 0xF5, 0xE4, 0x68, 0x59, 0xAD, 0x5A, 0xAB, 0xBA, 0xB1, 0x08, 0x7F, ++ 0x5A, 0xAB, 0x5B, 0x8F, 0x07, 0x7F, 0x59, 0xAD, 0x33, 0xEF, 0xBA, 0xB1, 0xAD, 0xFE, 0xE0, 0x95, ++ 0x95, 0x33, 0xED, 0x5B, 0xED, 0xC3, 0xFC, 0xE0, 0xEC, 0x5E, 0xF5, 0x9F, 0x75, 0x5D, 0xF5, 0x9E, ++ 0x64, 0x75, 0x00, 0x63, 0x7F, 0x5A, 0xE5, 0xCD, 0x02, 0x03, 0xB4, 0x20, 0x66, 0x8F, 0x80, 0x7F, ++ 0xE5, 0x09, 0x65, 0x75, 0x66, 0x95, 0xC3, 0x65, 0x7B, 0xA1, 0x02, 0x40, 0x59, 0xAD, 0x5A, 0xAB, ++ 0xBA, 0xB1, 0x65, 0xAF, 0x5B, 0xAF, 0x5C, 0x8F, 0xE0, 0x95, 0x33, 0xEF, 0xED, 0x5C, 0xAD, 0xFE, ++ 0xFC, 0xE0, 0x95, 0x33, 0xF5, 0x9F, 0xED, 0xC3, 0xF5, 0x9E, 0xEC, 0x60, 0xC3, 0x67, 0xE5, 0x5F, ++ 0x02, 0x40, 0x05, 0x94, 0xFF, 0xE4, 0x4C, 0xA1, 0x6C, 0xF5, 0x6B, 0xF5, 0x7F, 0x24, 0x64, 0xE5, ++ 0x35, 0xE4, 0x6E, 0xF5, 0xAE, 0x6D, 0xF5, 0x63, 0xEE, 0x6B, 0xAD, 0x6D, 0xE5, 0xD3, 0x6B, 0xF5, ++ 0xE5, 0x00, 0x94, 0x5E, 0x94, 0x80, 0x64, 0x5D, 0xD3, 0x33, 0x40, 0x80, 0x00, 0x94, 0x60, 0xE5, ++ 0x80, 0x64, 0x5F, 0xE5, 0x26, 0x50, 0x80, 0x94, 0x80, 0x64, 0x6A, 0xE5, 0x64, 0x5B, 0xE5, 0xF8, ++ 0x1A, 0x40, 0x98, 0x80, 0xEE, 0x6C, 0xAE, 0x0F, 0x6C, 0xF5, 0x02, 0x44, 0x80, 0x64, 0x69, 0xE5, ++ 0x64, 0x5B, 0xE5, 0xF8, 0x00, 0x7E, 0x98, 0x80, 0x01, 0x7E, 0x02, 0x50, 0xE5, 0xC3, 0x3B, 0x80, ++ 0x94, 0x80, 0x64, 0x5D, 0xC3, 0x3E, 0x50, 0x80, 0x80, 0x64, 0x5F, 0xE5, 0x35, 0x40, 0x80, 0x94, ++ 0x04, 0xF4, 0x6A, 0xE5, 0xE5, 0xF8, 0x80, 0x64, 0x98, 0x80, 0x64, 0x5B, 0x02, 0x7F, 0x27, 0x50, ++ 0x44, 0xEE, 0x6C, 0xAE, 0xE5, 0x6C, 0xF5, 0x04, 0x64, 0x04, 0xF4, 0x69, 0x5B, 0xE5, 0xF8, 0x80, ++ 0x7E, 0x98, 0x80, 0x64, 0x7E, 0x02, 0x40, 0x00, 0x01, 0x54, 0xEE, 0x01, 0xED, 0x6C, 0xAD, 0xFE, ++ 0xF5, 0x4E, 0xFE, 0x54, 0x64, 0x60, 0xEF, 0x6C, 0xFF, 0x14, 0x65, 0xE5, 0x59, 0xAD, 0x5A, 0xAB, ++ 0x61, 0x8E, 0xD7, 0xB1, 0x68, 0xE5, 0x62, 0x8F, 0xAB, 0xFD, 0x67, 0x25, 0xE4, 0x6B, 0xAA, 0x6C, ++ 0xA1, 0xB1, 0xFE, 0xFF, 0x67, 0x25, 0x68, 0xE5, 0xAA, 0x62, 0xAB, 0xFD, 0xB1, 0x40, 0x7F, 0x61, ++ 0x7F, 0x20, 0x7E, 0xA1, 0xED, 0x6C, 0xAD, 0x67, 0x7E, 0x23, 0x10, 0x12, 0xAD, 0x6E, 0x7F, 0x20, ++ 0x12, 0xC3, 0xED, 0x6C, 0x20, 0x7E, 0x22, 0x10, 0x6C, 0xAD, 0x74, 0x7F, 0x21, 0x10, 0x12, 0xED, ++ 0x7A, 0x7F, 0x20, 0x7E, 0x7C, 0xED, 0x6B, 0xAD, 0x28, 0x10, 0x12, 0x00, 0x80, 0x7F, 0x20, 0x7E, ++ 0x61, 0xAC, 0x62, 0xAD, 0x20, 0x28, 0x10, 0x12, 0x67, 0x05, 0xFD, 0x18, 0x85, 0x5B, 0x5C, 0x85, ++ 0x60, 0x85, 0x5D, 0x5F, 0xB4, 0x65, 0xE5, 0x5E, 0x65, 0x05, 0x02, 0x3F, 0x94, 0xD3, 0x65, 0xE5, ++ 0x7E, 0x06, 0x40, 0x40, 0x80, 0x9A, 0x7F, 0x01, 0x7F, 0x00, 0x7E, 0x04, 0x64, 0x25, 0xEF, 0xCD, ++ 0x35, 0xEE, 0x64, 0xF5, 0x05, 0x63, 0xF5, 0x63, 0xE5, 0x13, 0x81, 0x65, 0x7E, 0x21, 0x70, 0x67, ++ 0x12, 0x86, 0x7F, 0x20, 0xF5, 0xE4, 0x1B, 0x10, 0xAF, 0x6C, 0xF5, 0x6B, 0x08, 0x44, 0xEF, 0x6C, ++ 0x68, 0xE5, 0x6C, 0xF5, 0xAB, 0xFD, 0x67, 0x25, 0xE4, 0x6B, 0xAA, 0x6C, 0xA1, 0xB1, 0xFE, 0xFF, ++ 0x8E, 0x82, 0x8F, 0x22, 0xF0, 0x75, 0xED, 0x83, 0x82, 0x25, 0xA4, 0x02, 0xF0, 0xE5, 0x82, 0xF5, ++ 0x83, 0xF5, 0x83, 0x35, 0xEB, 0xA3, 0xF0, 0xEA, 0x09, 0x90, 0x22, 0xF0, 0x90, 0xF0, 0xEB, 0xAA, ++ 0xF0, 0xEF, 0xAB, 0x09, 0x65, 0xF0, 0x75, 0xED, 0xFF, 0x1A, 0x24, 0xA4, 0x08, 0x34, 0xF0, 0xE5, ++ 0x83, 0xF5, 0x82, 0x8F, 0x90, 0x22, 0xFF, 0xE0, 0xF0, 0xEB, 0xAA, 0x09, 0xEF, 0xAB, 0x09, 0x90, ++ 0xF0, 0x75, 0xED, 0xF0, 0x1A, 0x24, 0xA4, 0x65, 0x34, 0xF0, 0xE5, 0xFF, 0xF5, 0x82, 0x8F, 0x08, ++ 0xA3, 0xFE, 0xE0, 0x83, 0x8F, 0x22, 0xFF, 0xE0, 0xE4, 0x05, 0xAA, 0x59, 0x5B, 0xF5, 0x5A, 0xF5, ++ 0x10, 0xF0, 0x75, 0xEF, 0xFD, 0x0A, 0x24, 0xA4, 0xFC, 0xF0, 0x35, 0xE4, 0x02, 0xF0, 0x75, 0xEA, ++ 0xE5, 0xFF, 0x2D, 0xA4, 0x5C, 0xF5, 0x3C, 0xF0, 0xF9, 0xE4, 0x5D, 0x8F, 0x00, 0x7E, 0xFF, 0xE9, ++ 0x03, 0xBA, 0x00, 0x7C, 0x80, 0x80, 0x7D, 0x04, 0xC3, 0x20, 0x7D, 0x02, 0x64, 0xEC, 0x9D, 0xEF, ++ 0x64, 0xEE, 0xF8, 0x80, 0x31, 0x50, 0x98, 0x80, 0x02, 0xAB, 0x01, 0xAF, 0xD7, 0xB1, 0x59, 0xAD, ++ 0xCE, 0x07, 0x78, 0xEF, 0xCE, 0x13, 0xE7, 0xA2, 0xF5, 0xF8, 0xD8, 0x13, 0xFF, 0x83, 0x8E, 0x82, ++ 0x12, 0x83, 0xAC, 0xFD, 0xA2, 0xEE, 0x98, 0x02, 0xEF, 0xFE, 0x13, 0xE7, 0xF5, 0x5B, 0x25, 0x13, ++ 0x5A, 0x35, 0xEE, 0x5B, 0x80, 0x09, 0x5A, 0xF5, 0x82, 0x5D, 0x85, 0xB3, 0xE5, 0x83, 0x5C, 0x85, ++ 0xE5, 0xA3, 0xF0, 0x5A, 0xE5, 0x22, 0xF0, 0x5B, 0x7E, 0x20, 0x60, 0x2F, 0x12, 0x27, 0x7F, 0x20, ++ 0x81, 0x78, 0x1B, 0x10, 0x76, 0x08, 0x00, 0x76, 0x76, 0x84, 0x78, 0x01, 0xC3, 0xE6, 0x18, 0x01, ++ 0x07, 0xE0, 0x30, 0x13, 0x34, 0x76, 0x81, 0x78, 0x7F, 0xBC, 0x76, 0x08, 0x3A, 0x11, 0x12, 0x81, ++ 0x2C, 0x75, 0x06, 0x50, 0xD9, 0x2D, 0x75, 0x22, 0x7F, 0x20, 0x7E, 0x22, 0x1B, 0x10, 0x12, 0x4A, ++ 0xE0, 0xAE, 0x01, 0x90, 0xE5, 0xF0, 0xEF, 0x54, 0xF5, 0xEF, 0x54, 0x20, 0x54, 0x21, 0xE5, 0x20, ++ 0x75, 0x21, 0xF5, 0xEF, 0x29, 0x75, 0x02, 0x28, 0x01, 0x24, 0x75, 0x51, 0x22, 0xBB, 0x25, 0x75, ++ 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x50, 0x7E, 0x81, 0x7E, 0x31, 0x2D, 0x59, 0x48, 0x32, 0x2D, 0x35, 0x56, 0x49, 0x2D, 0x46, 0x32, ++ 0x52, 0x56, 0x2D, 0x50, 0x32, 0x41, 0x2D, 0x39, 0x34, 0x54, 0x2D, 0x32, 0x81, 0x36, 0x30, 0x34, ++ 0x00, 0x00, 0x81, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++}; ++ ++ ++#endif /*__GPHY_IP_22F_FW__ */ +diff --git a/include/switch_api/gphy_fw_ge.h b/include/switch_api/gphy_fw_ge.h +new file mode 100644 +index 0000000..a4ed0e9 +--- /dev/null ++++ b/include/switch_api/gphy_fw_ge.h +@@ -0,0 +1,8216 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ \file gphy_fw_ge.h ++ \remarks implement GPHY driver firmware in VR9 platform ++ \Track bin : gphy_fw_ge.bin [ 1215-2010 ] ++ *****************************************************************************/ ++#ifndef __GPHY_IP_11G_FW__ ++#define __GPHY_IP_11G_FW__ ++ ++static const unsigned char gphy_ge_fw_data[] = { ++ 0x80, 0x05, 0x03, 0x02, 0x32, 0x32, 0x32, 0x00, 0x80, 0x32, 0x32, 0x32, 0x00, 0x00, 0x32, 0xF9, ++ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEB, ++ 0x61, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9C, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDC, ++ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0xE1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xA3, ++ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8D, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x0A, ++ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x0B, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x65, 0x0B, ++ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0x0B, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9D, ++ 0x80, 0x00, 0x00, 0x00, 0x54, 0x90, 0xE5, 0x98, 0xC0, 0x03, 0xC4, 0x0F, 0xC0, 0x04, 0x74, 0xE0, ++ 0xC0, 0x82, 0xC0, 0xE0, 0x00, 0x04, 0x02, 0x83, 0x0F, 0x54, 0x90, 0xE5, 0xE0, 0xC0, 0x03, 0xC4, ++ 0xE0, 0xC0, 0x04, 0x74, 0x83, 0xC0, 0x82, 0xC0, 0xE5, 0x08, 0x04, 0x02, 0xC4, 0x0F, 0x54, 0x90, ++ 0x74, 0xE0, 0xC0, 0x03, 0xC0, 0xE0, 0xC0, 0x04, 0x02, 0x83, 0xC0, 0x82, 0x90, 0xE5, 0x10, 0x04, ++ 0x03, 0xC4, 0x0F, 0x54, 0x04, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, 0xC0, 0x04, 0x02, 0x83, 0xC0, ++ 0x54, 0x90, 0xE5, 0x18, 0xC0, 0x03, 0xC4, 0x0F, 0xC0, 0x04, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, ++ 0x20, 0x04, 0x02, 0x83, 0x0F, 0x54, 0x90, 0xE5, 0xE0, 0xC0, 0x03, 0xC4, 0xE0, 0xC0, 0x04, 0x74, ++ 0x83, 0xC0, 0x82, 0xC0, 0xE5, 0x28, 0x04, 0x02, 0xC4, 0x0F, 0x54, 0x90, 0x74, 0xE0, 0xC0, 0x03, ++ 0xC0, 0xE0, 0xC0, 0x04, 0x02, 0x83, 0xC0, 0x82, 0x90, 0xE5, 0x30, 0x04, 0x03, 0xC4, 0x0F, 0x54, ++ 0x04, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, 0xC0, 0x04, 0x02, 0x83, 0xC0, 0x54, 0x90, 0xE5, 0x38, ++ 0xC0, 0x03, 0xC4, 0x0F, 0xC0, 0x04, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, 0x40, 0x04, 0x02, 0x83, ++ 0x0F, 0x54, 0x90, 0xE5, 0xE0, 0xC0, 0x03, 0xC4, 0xE0, 0xC0, 0x04, 0x74, 0x83, 0xC0, 0x82, 0xC0, ++ 0xE5, 0x48, 0x04, 0x02, 0xC4, 0x0F, 0x54, 0x90, 0x74, 0xE0, 0xC0, 0x03, 0xC0, 0xE0, 0xC0, 0x04, ++ 0x02, 0x83, 0xC0, 0x82, 0x90, 0xE5, 0x50, 0x04, 0x03, 0xC4, 0x0F, 0x54, 0x04, 0x74, 0xE0, 0xC0, ++ 0x82, 0xC0, 0xE0, 0xC0, 0x04, 0x02, 0x83, 0xC0, 0x54, 0x90, 0xE5, 0x58, 0xC0, 0x03, 0xC4, 0x0F, ++ 0xC0, 0x04, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, 0x60, 0x04, 0x02, 0x83, 0x0F, 0x54, 0x90, 0xE5, ++ 0xE0, 0xC0, 0x03, 0xC4, 0xE0, 0xC0, 0x04, 0x74, 0x83, 0xC0, 0x82, 0xC0, 0xE5, 0x68, 0x04, 0x02, ++ 0xC4, 0x0F, 0x54, 0x90, 0x74, 0xE0, 0xC0, 0x03, 0xC0, 0xE0, 0xC0, 0x04, 0x02, 0x83, 0xC0, 0x82, ++ 0x90, 0xE5, 0x70, 0x04, 0x03, 0xC4, 0x0F, 0x54, 0x04, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, 0xC0, ++ 0x04, 0x02, 0x83, 0xC0, 0x03, 0xC4, 0xEF, 0x78, 0x73, 0x00, 0x04, 0x90, 0x01, 0x00, 0x20, 0x90, ++ 0xA7, 0x22, 0x90, 0x88, 0x20, 0x90, 0x88, 0x01, 0x90, 0x9B, 0x01, 0x00, 0x9B, 0x01, 0x02, 0x20, ++ 0x01, 0xD6, 0x27, 0x90, 0x00, 0x20, 0x90, 0x9B, 0x24, 0x90, 0xAE, 0x01, 0x90, 0xAE, 0x01, 0xE2, ++ 0xC1, 0x01, 0x00, 0x20, 0x01, 0x65, 0x2E, 0x90, 0x19, 0x20, 0x90, 0xC1, 0x2F, 0x90, 0xD4, 0x01, ++ 0x90, 0xE7, 0x01, 0x97, 0xFA, 0x01, 0x63, 0x24, 0x21, 0x17, 0x27, 0x90, 0x37, 0x2D, 0x90, 0x0D, ++ 0x2F, 0x90, 0x20, 0x21, 0x90, 0x33, 0x21, 0xAF, 0x46, 0x21, 0x17, 0x30, 0x21, 0x99, 0x29, 0x90, ++ 0x00, 0x20, 0x90, 0x59, 0x23, 0x90, 0x6C, 0x21, 0x90, 0x7F, 0x21, 0x65, 0x92, 0x21, 0x00, 0x20, ++ 0x21, 0xD0, 0x20, 0x90, 0xA7, 0x21, 0x90, 0x92, 0x22, 0x90, 0x88, 0x01, 0x90, 0x88, 0x01, 0x09, ++ 0x88, 0x01, 0xC4, 0x20, 0x01, 0xDB, 0x22, 0x90, 0xB9, 0x25, 0x90, 0x9B, 0x22, 0x90, 0x9B, 0x01, ++ 0x90, 0xAE, 0x01, 0x49, 0xC1, 0x01, 0x67, 0x23, 0x01, 0x7B, 0x2D, 0x90, 0x10, 0x20, 0x90, 0xC1, ++ 0x2B, 0x90, 0xD4, 0x01, 0x90, 0xE7, 0x01, 0xA7, 0xFA, 0x01, 0xA5, 0x21, 0x01, 0x5A, 0x24, 0x90, ++ 0x44, 0x20, 0x90, 0xFA, 0x20, 0x90, 0x0D, 0x21, 0x90, 0x20, 0x21, 0x91, 0x33, 0x21, 0x74, 0x22, ++ 0x21, 0xCF, 0x20, 0x90, 0x4E, 0x20, 0x90, 0x33, 0x20, 0x90, 0x46, 0x21, 0x90, 0x59, 0x21, 0x76, ++ 0x7F, 0x21, 0x17, 0x20, 0x21, 0x00, 0x20, 0x90, 0x45, 0x20, 0x90, 0x7F, 0xBB, 0x00, 0x92, 0x21, ++ 0x82, 0x89, 0x06, 0x01, 0x22, 0xE0, 0x83, 0x8A, 0x22, 0xE7, 0x02, 0x50, 0xE3, 0x02, 0xFE, 0xBB, ++ 0x8A, 0x82, 0x89, 0x22, 0x22, 0x93, 0xE4, 0x83, 0xA4, 0xF0, 0x8D, 0xEF, 0x8C, 0xCF, 0xF0, 0xA8, ++ 0xCE, 0x28, 0xA4, 0xF0, 0x2E, 0xA4, 0xF0, 0x8D, 0x00, 0xBC, 0x22, 0xFE, 0x29, 0x00, 0xBE, 0x0B, ++ 0x84, 0xF0, 0x8D, 0xEF, 0x22, 0xF0, 0xAD, 0xFF, 0x75, 0xF8, 0xCC, 0xE4, 0x2F, 0xEF, 0x08, 0xF0, ++ 0xFE, 0x33, 0xEE, 0xFF, 0xEE, 0xFC, 0x33, 0xEC, 0x40, 0x98, 0xEC, 0x9D, 0x9D, 0xEE, 0xFC, 0x05, ++ 0xF0, 0xD5, 0x0F, 0xFE, 0xFD, 0xCE, 0xE4, 0xE9, 0xF5, 0xF8, 0xED, 0x22, 0x20, 0x84, 0xEE, 0xF0, ++ 0xAD, 0xFE, 0x1C, 0xD2, 0x08, 0xF0, 0x75, 0xF0, 0xED, 0xFF, 0x2F, 0xEF, 0x07, 0x40, 0xFD, 0x33, ++ 0xD5, 0x06, 0x50, 0x98, 0xC3, 0x22, 0xF2, 0xF0, 0xD5, 0x0F, 0xFD, 0x98, 0x8A, 0x22, 0xEA, 0xF0, ++ 0xE4, 0x82, 0x89, 0x83, 0x92, 0x81, 0x75, 0x73, 0xE4, 0x0B, 0x03, 0x02, 0x0E, 0x12, 0x03, 0x60, ++ 0xFF, 0xB0, 0x75, 0xA7, 0xAC, 0x31, 0x26, 0x71, 0x07, 0x90, 0x64, 0x71, 0x10, 0x44, 0xE0, 0x07, ++ 0x01, 0x87, 0x43, 0xF0, 0x19, 0x75, 0xFB, 0x80, 0x12, 0x1A, 0x75, 0x07, 0xA7, 0x7F, 0x0E, 0x7E, ++ 0x22, 0x7E, 0x3A, 0x71, 0x3A, 0x71, 0xA7, 0x7F, 0x24, 0xEF, 0x15, 0x41, 0x34, 0xEE, 0xFF, 0x10, ++ 0x54, 0xEF, 0xFE, 0xE0, 0xFF, 0xFF, 0x24, 0xF0, 0xFE, 0xFF, 0x34, 0xEE, 0x24, 0xFD, 0x1A, 0xE5, ++ 0xE5, 0x1A, 0xF5, 0x02, 0x00, 0x34, 0xFC, 0x19, 0x82, 0x8D, 0x19, 0xF5, 0xF0, 0xEE, 0x83, 0x8C, ++ 0x22, 0xF0, 0xEF, 0xA3, 0xF5, 0xA8, 0xF5, 0xE4, 0xD2, 0xAC, 0xD2, 0xE8, 0xD2, 0xE9, 0xD2, 0xEA, ++ 0xF0, 0xF9, 0x75, 0xE8, 0xF5, 0xF0, 0xF8, 0x75, 0x10, 0xB8, 0x75, 0xB9, 0x90, 0x22, 0xAF, 0xD2, ++ 0x13, 0x74, 0x4B, 0x07, 0x4C, 0x07, 0x90, 0xF0, 0xE4, 0xF0, 0x88, 0x74, 0xBD, 0x01, 0x90, 0xFF, ++ 0xA3, 0xE4, 0xF0, 0xEF, 0x90, 0xE4, 0x22, 0xF0, 0x22, 0xF0, 0xBF, 0x01, 0x83, 0xC0, 0xE0, 0xC0, ++ 0xD0, 0xC0, 0x82, 0xC0, 0x63, 0x00, 0xD0, 0x75, 0x83, 0xC0, 0x01, 0xA2, 0xA2, 0x63, 0x82, 0xC0, ++ 0xC0, 0x06, 0xC0, 0x01, 0x23, 0x99, 0x30, 0x07, 0x1B, 0xE5, 0x99, 0xC2, 0x19, 0x60, 0x1C, 0x65, ++ 0x1B, 0x05, 0x1B, 0xAF, 0x54, 0xEF, 0x00, 0x7E, 0xF5, 0xAC, 0x24, 0x7F, 0x00, 0x34, 0xEE, 0x82, ++ 0xF5, 0xE0, 0x83, 0xF5, 0x80, 0x0A, 0xC2, 0x99, 0xD0, 0x0B, 0xC2, 0x02, 0x63, 0x06, 0xD0, 0x07, ++ 0x82, 0xD0, 0x01, 0xA2, 0xA2, 0x63, 0x83, 0xD0, 0xD0, 0xD0, 0xD0, 0x01, 0xD0, 0x83, 0xD0, 0x82, ++ 0xFF, 0x7B, 0x32, 0xE0, 0x30, 0x79, 0x20, 0x7A, 0x02, 0xFC, 0xFD, 0xE4, 0x00, 0x00, 0xE5, 0x0C, ++ 0x22, 0xF0, 0x90, 0x53, 0x00, 0x00, 0x00, 0x00, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF1, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF2, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF3, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF4, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF5, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF6, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF7, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF8, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF9, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xFA, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xFB, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xFC, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xFD, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xFE, 0x90, 0x22, 0x0F, 0x90, 0x43, 0xF0, 0xC0, 0xE0, 0xC0, ++ 0x82, 0xC0, 0x83, 0xC0, 0xD0, 0x75, 0xD0, 0xC0, 0x01, 0xA2, 0x63, 0x00, 0x82, 0xC0, 0x83, 0xC0, ++ 0xC0, 0x01, 0xA2, 0x63, 0xC0, 0x01, 0xC0, 0x00, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x05, 0xC0, 0x04, ++ 0x90, 0x07, 0xC0, 0x06, 0xF5, 0xE0, 0x02, 0x07, 0xEF, 0x54, 0xAF, 0x54, 0x13, 0x13, 0x13, 0xC4, ++ 0xE0, 0x30, 0x01, 0x54, 0xAF, 0x6B, 0xC1, 0x02, 0x7F, 0x54, 0xEF, 0x54, 0x02, 0x70, 0xFC, 0x24, ++ 0xFD, 0x24, 0x92, 0xA1, 0xB4, 0xA1, 0x02, 0x70, 0x02, 0x70, 0xFE, 0x24, 0xFC, 0x24, 0xBD, 0xA1, ++ 0xDC, 0xA1, 0x02, 0x70, 0xA1, 0x02, 0x70, 0x14, 0x70, 0xF9, 0x24, 0xF6, 0x24, 0x33, 0xC1, 0x02, ++ 0xE1, 0x02, 0x60, 0x15, 0x00, 0x06, 0x90, 0x06, 0x13, 0x13, 0xC4, 0xE0, 0x30, 0x01, 0x54, 0x13, ++ 0xE8, 0xC2, 0x19, 0xE0, 0xE0, 0x80, 0x06, 0x90, 0x90, 0xF0, 0x80, 0x44, 0x44, 0xE0, 0x00, 0x06, ++ 0x20, 0xAF, 0xF0, 0x80, 0xF5, 0x01, 0x44, 0xEF, 0x90, 0x06, 0xE1, 0x20, 0xC4, 0xE0, 0x00, 0x06, ++ 0xE0, 0x20, 0x0F, 0x54, 0xFD, 0x54, 0xE0, 0x14, 0x03, 0x06, 0x90, 0xF0, 0xF0, 0xDF, 0x54, 0xE0, ++ 0x44, 0xEF, 0x20, 0xAF, 0x80, 0x20, 0xF5, 0x20, 0x00, 0x06, 0x90, 0x30, 0x25, 0x02, 0x54, 0xE0, ++ 0x20, 0xAE, 0xFF, 0xE0, 0x4F, 0xFB, 0x54, 0xEE, 0x06, 0x90, 0x20, 0xF5, 0x13, 0xC4, 0xE0, 0x03, ++ 0x00, 0x7F, 0x07, 0x54, 0x7F, 0x02, 0xE0, 0x20, 0x01, 0x54, 0xEF, 0x01, 0xE0, 0x54, 0x33, 0xC4, ++ 0xEE, 0x20, 0xAE, 0xFF, 0xF5, 0x4F, 0xDF, 0x54, 0x01, 0x06, 0x90, 0x20, 0x13, 0x13, 0xC4, 0xE0, ++ 0xFF, 0x01, 0x54, 0x13, 0xE0, 0x00, 0x06, 0x90, 0x54, 0x13, 0x13, 0xC4, 0xE0, 0xFF, 0x4F, 0x01, ++ 0x01, 0x54, 0x13, 0x13, 0xC4, 0x01, 0x54, 0x4F, 0xAE, 0xFF, 0xF0, 0x54, 0xEF, 0x54, 0xEE, 0x20, ++ 0xE0, 0x20, 0xF5, 0x4F, 0x13, 0x13, 0x08, 0x54, 0xAE, 0xFF, 0x3F, 0x54, 0xFD, 0x54, 0xEE, 0x20, ++ 0x06, 0x90, 0x45, 0x80, 0x13, 0xC4, 0xE0, 0x03, 0xE0, 0x30, 0x07, 0x54, 0x90, 0x06, 0xE1, 0x02, ++ 0xC4, 0xE0, 0x00, 0x06, 0xE0, 0x20, 0x0F, 0x54, 0xAF, 0x06, 0xE1, 0x02, 0x04, 0x44, 0xEF, 0x20, ++ 0x06, 0xE1, 0x20, 0xF5, 0x44, 0xEF, 0x20, 0xAF, 0xE1, 0x20, 0xF5, 0x08, 0x12, 0x06, 0x90, 0x06, ++ 0x54, 0x13, 0xC4, 0xE0, 0x60, 0x00, 0x7F, 0x07, 0xEF, 0x01, 0x7F, 0x02, 0x54, 0xC4, 0x01, 0x54, ++ 0x20, 0xAE, 0xFF, 0xF0, 0x4F, 0xEF, 0x54, 0xEE, 0x06, 0xE1, 0x20, 0xF5, 0xE0, 0x1A, 0x06, 0x90, ++ 0x13, 0x13, 0xC4, 0xFF, 0x02, 0x60, 0x03, 0x54, 0x06, 0x90, 0xDA, 0xC1, 0xF0, 0x1D, 0xE5, 0x1C, ++ 0xF0, 0x1E, 0xE5, 0xA3, 0x06, 0x90, 0x06, 0xE1, 0xC4, 0xFF, 0xE0, 0x1A, 0x03, 0x54, 0x13, 0x13, ++ 0x06, 0x90, 0x0D, 0x70, 0xA3, 0xFE, 0xE0, 0x1C, 0xF5, 0x1D, 0x8E, 0xE0, 0xF1, 0x06, 0xE1, 0x1E, ++ 0x1A, 0x06, 0x90, 0x2B, 0x13, 0xC4, 0xFF, 0xE0, 0x64, 0x03, 0x54, 0x13, 0xE0, 0x0A, 0x60, 0x02, ++ 0x54, 0x13, 0x13, 0xC4, 0x03, 0xBF, 0xFF, 0x03, 0xE5, 0x1E, 0x05, 0x08, 0x05, 0x02, 0x70, 0x1E, ++ 0x90, 0xDA, 0xC1, 0x1D, 0x54, 0xE0, 0x2A, 0x06, 0x08, 0x94, 0xC3, 0x0F, 0x06, 0xE1, 0x02, 0x40, ++ 0xE0, 0x8D, 0x07, 0x90, 0x90, 0xFF, 0x07, 0x54, 0x54, 0xE0, 0x2A, 0x06, 0x0A, 0x60, 0x6F, 0x0F, ++ 0xE0, 0x8C, 0x07, 0x90, 0xF0, 0x2B, 0x06, 0x90, 0x06, 0x90, 0xF0, 0xE4, 0x07, 0x54, 0xE0, 0x2A, ++ 0x8D, 0x07, 0x90, 0xFF, 0x4F, 0xF8, 0x54, 0xE0, 0xAF, 0x06, 0xE1, 0xF0, 0x7F, 0x54, 0xEF, 0x54, ++ 0x21, 0x60, 0xFA, 0x24, 0x34, 0x60, 0xFC, 0x24, 0x3D, 0x60, 0xFC, 0x24, 0x5F, 0x60, 0xFD, 0x24, ++ 0x64, 0x60, 0xFC, 0x24, 0x70, 0x60, 0xFB, 0x24, 0x7A, 0x70, 0x19, 0x24, 0xE0, 0x03, 0x06, 0x90, ++ 0x80, 0xF0, 0xEF, 0x54, 0x0D, 0x06, 0x90, 0x11, 0xF0, 0xEF, 0x54, 0xE0, 0xE0, 0xFF, 0x01, 0x90, ++ 0x90, 0x63, 0xE0, 0x20, 0x54, 0xE0, 0x0D, 0x06, 0x5A, 0x80, 0xF0, 0xFD, 0xE0, 0x14, 0x06, 0x90, ++ 0xA3, 0xF0, 0x7F, 0x54, 0x80, 0xF0, 0xE4, 0xE0, 0x1A, 0x06, 0x90, 0x4D, 0x13, 0x13, 0xC4, 0xE0, ++ 0xBF, 0xFF, 0x03, 0x54, 0x1E, 0x05, 0x08, 0x02, 0x02, 0x70, 0x1E, 0xE5, 0x06, 0x90, 0x1D, 0x05, ++ 0xC4, 0xFF, 0xE0, 0x1A, 0x03, 0x54, 0x13, 0x13, 0x0D, 0x12, 0x2C, 0x60, 0x90, 0x27, 0x80, 0xED, ++ 0x54, 0xE0, 0x22, 0x06, 0x1E, 0x80, 0xF0, 0xFE, 0xE0, 0x2A, 0x06, 0x90, 0x94, 0xC3, 0x0F, 0x54, ++ 0xA3, 0x13, 0x50, 0x08, 0x0E, 0x80, 0xF0, 0xE4, 0xE4, 0x34, 0x06, 0x90, 0x90, 0xF0, 0xA3, 0xF0, ++ 0x54, 0xE0, 0x07, 0x07, 0x07, 0xD0, 0xF0, 0xEF, 0x05, 0xD0, 0x06, 0xD0, 0x03, 0xD0, 0x04, 0xD0, ++ 0x01, 0xD0, 0x02, 0xD0, 0xA2, 0x63, 0x00, 0xD0, 0xD0, 0x82, 0xD0, 0x01, 0x01, 0xA2, 0x63, 0x83, ++ 0x82, 0xD0, 0xD0, 0xD0, 0xF0, 0xD0, 0x83, 0xD0, 0x90, 0x32, 0xE0, 0xD0, 0x54, 0xE0, 0x1B, 0x06, ++ 0x60, 0xF9, 0x24, 0x1F, 0x60, 0xE9, 0x24, 0x22, 0x3E, 0x60, 0x14, 0x39, 0x62, 0x70, 0x1C, 0x24, ++ 0x1E, 0xE5, 0x1D, 0xAE, 0x70, 0xEE, 0x5C, 0x70, 0x1C, 0x06, 0x90, 0x59, 0x90, 0x04, 0x54, 0xE0, ++ 0xA3, 0xF0, 0xB5, 0x01, 0xAF, 0x22, 0xF0, 0xE4, 0x70, 0x1D, 0xE5, 0x1E, 0xC4, 0x24, 0xEF, 0x45, ++ 0x06, 0x90, 0x40, 0x70, 0x06, 0x54, 0xE0, 0x1D, 0xAF, 0x01, 0x90, 0xFF, 0xEF, 0xA3, 0xF0, 0xE4, ++ 0x06, 0x90, 0x22, 0xF0, 0x40, 0x44, 0xE0, 0x2C, 0xEA, 0x79, 0x22, 0xF0, 0xEA, 0x74, 0xEA, 0x7D, ++ 0x04, 0x70, 0x1E, 0x65, 0x1D, 0x65, 0x01, 0x74, 0x0D, 0x09, 0x18, 0x60, 0x70, 0x1E, 0x65, 0xED, ++ 0x65, 0x01, 0x74, 0x04, 0x90, 0x0B, 0x60, 0x1D, 0x85, 0xE0, 0x1D, 0x06, 0x1D, 0x85, 0x82, 0x1E, ++ 0xC0, 0x22, 0xF0, 0x83, 0xC0, 0xF0, 0xC0, 0xE0, 0xC0, 0x82, 0xC0, 0x83, 0x00, 0xD0, 0x75, 0xD0, ++ 0xC0, 0x01, 0xA2, 0x63, 0x63, 0x82, 0xC0, 0x83, 0x00, 0xC0, 0x01, 0xA2, 0x02, 0xC0, 0x01, 0xC0, ++ 0x04, 0xC0, 0x03, 0xC0, 0x06, 0xC0, 0x05, 0xC0, 0x07, 0x90, 0x07, 0xC0, 0xF0, 0x04, 0x74, 0x65, ++ 0xE0, 0xBE, 0x01, 0x90, 0x01, 0x90, 0xF0, 0x04, 0xA3, 0xFF, 0xE0, 0xBD, 0x40, 0x9F, 0xD3, 0xE0, ++ 0xC2, 0xF0, 0xE4, 0x2D, 0x65, 0x5E, 0xE5, 0xE9, 0xE5, 0x04, 0x70, 0x5A, 0x7F, 0x59, 0x65, 0x5D, ++ 0x7F, 0x02, 0x60, 0x00, 0xE5, 0x71, 0x8F, 0x01, 0x85, 0x0C, 0x60, 0x71, 0x5A, 0x85, 0x57, 0x59, ++ 0x59, 0x5D, 0x85, 0x58, 0xAA, 0x5A, 0x5E, 0x85, 0x12, 0x5A, 0xA9, 0x59, 0x07, 0x90, 0xFF, 0x02, ++ 0xE0, 0x30, 0xE0, 0x7C, 0xF0, 0x01, 0x74, 0x0A, 0xE0, 0x34, 0x06, 0x90, 0x90, 0xF0, 0x80, 0x44, ++ 0x54, 0xE0, 0x2A, 0x06, 0x08, 0x94, 0xC3, 0x0F, 0xE0, 0xA3, 0x19, 0x50, 0x8C, 0x07, 0x90, 0xFF, ++ 0xE4, 0xFF, 0x2F, 0xE0, 0x04, 0x60, 0xFE, 0x33, 0xFF, 0x7F, 0x00, 0x7E, 0xEF, 0x2B, 0x06, 0x90, ++ 0x90, 0x05, 0x80, 0xF0, 0xF0, 0xE4, 0x2B, 0x06, 0xE9, 0xD2, 0x71, 0x11, 0x06, 0xD0, 0x07, 0xD0, ++ 0x04, 0xD0, 0x05, 0xD0, 0x02, 0xD0, 0x03, 0xD0, 0x00, 0xD0, 0x01, 0xD0, 0xD0, 0x01, 0xA2, 0x63, ++ 0x63, 0x83, 0xD0, 0x82, 0xD0, 0xD0, 0x01, 0xA2, 0x83, 0xD0, 0x82, 0xD0, 0xE0, 0xD0, 0xF0, 0xD0, ++ 0x34, 0x06, 0x90, 0x32, 0xE0, 0xA3, 0xFE, 0xE0, 0x32, 0x06, 0x90, 0xFF, 0xA3, 0xFE, 0x5E, 0xE0, ++ 0x60, 0x4E, 0x5F, 0xE0, 0x07, 0x07, 0x90, 0x07, 0xF0, 0x10, 0x44, 0xE0, 0xC0, 0xE0, 0xC0, 0x22, ++ 0xC0, 0x83, 0xC0, 0xF0, 0x75, 0xD0, 0xC0, 0x82, 0xA2, 0x63, 0x00, 0xD0, 0xC0, 0x83, 0xC0, 0x01, ++ 0x01, 0xA2, 0x63, 0x82, 0x01, 0xC0, 0x00, 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x05, 0xC0, 0x04, 0xC0, ++ 0x07, 0xC0, 0x06, 0xC0, 0x74, 0x65, 0x07, 0x90, 0xEA, 0xC2, 0xF0, 0x08, 0xE0, 0xBF, 0x01, 0x90, ++ 0xC3, 0xE0, 0xF0, 0x04, 0x07, 0x40, 0x32, 0x94, 0x01, 0x90, 0xF6, 0x11, 0xD2, 0xF0, 0xE4, 0xBF, ++ 0xD0, 0x07, 0xD0, 0xEA, 0xD0, 0x05, 0xD0, 0x06, 0xD0, 0x03, 0xD0, 0x04, 0xD0, 0x01, 0xD0, 0x02, ++ 0x01, 0xA2, 0x63, 0x00, 0x83, 0xD0, 0x82, 0xD0, 0xD0, 0x01, 0xA2, 0x63, 0xD0, 0x82, 0xD0, 0xD0, ++ 0xD0, 0xF0, 0xD0, 0x83, 0x01, 0x90, 0x32, 0xE0, 0xF0, 0x01, 0x74, 0xC2, 0xF0, 0xE2, 0x74, 0xA3, ++ 0xE0, 0xE0, 0x01, 0x90, 0xFF, 0x0F, 0x54, 0xC4, 0x74, 0xFE, 0x03, 0x54, 0x08, 0x06, 0xA8, 0x64, ++ 0x13, 0xC3, 0x02, 0x80, 0xEF, 0xF9, 0xFC, 0xD8, 0x3F, 0x54, 0x13, 0x13, 0x74, 0xFF, 0x03, 0x54, ++ 0x08, 0x07, 0xA8, 0x64, 0x13, 0xC3, 0x02, 0x80, 0x78, 0xFB, 0xFC, 0xD8, 0xC3, 0x06, 0xE6, 0x90, ++ 0xE4, 0x02, 0x40, 0x99, 0xE6, 0x8B, 0x78, 0xF6, 0x40, 0x9B, 0xC3, 0x06, 0x78, 0xF6, 0xE4, 0x29, ++ 0xF6, 0xF4, 0xE6, 0x92, 0x10, 0x70, 0xE6, 0x18, 0x25, 0xE6, 0x8A, 0x78, 0xBF, 0xF6, 0xFF, 0xE0, ++ 0x91, 0x78, 0x14, 0x08, 0x0E, 0x80, 0x01, 0x76, 0xC3, 0xE6, 0x8A, 0x78, 0xBF, 0xF6, 0xFF, 0x13, ++ 0x78, 0xE4, 0x04, 0x01, 0xFA, 0xE4, 0xF6, 0x91, 0xE0, 0xE1, 0x01, 0x90, 0x51, 0xFF, 0x07, 0x54, ++ 0x06, 0x60, 0xEF, 0x8D, 0xFA, 0xE6, 0x92, 0x78, 0x01, 0x90, 0x6A, 0x41, 0x54, 0xC4, 0xE0, 0xE1, ++ 0x8D, 0x51, 0xFF, 0x07, 0x78, 0x06, 0x60, 0xEF, 0x41, 0xFA, 0xE6, 0x8A, 0xE0, 0x01, 0x90, 0x6A, ++ 0xFF, 0x07, 0x54, 0xE0, 0x60, 0xEF, 0x8D, 0x51, 0xE6, 0x8A, 0x78, 0x07, 0x6A, 0x41, 0xFA, 0xF4, ++ 0x01, 0x90, 0xFC, 0xE4, 0xA3, 0xFE, 0xE0, 0xC2, 0x8E, 0x82, 0xF5, 0xE0, 0x55, 0xF5, 0xE0, 0x83, ++ 0x56, 0xF5, 0xE0, 0xA3, 0xE0, 0xC3, 0x01, 0x90, 0x90, 0xF0, 0x02, 0x24, 0x34, 0xE0, 0xC2, 0x01, ++ 0x8C, 0x74, 0xF0, 0x00, 0xD3, 0xE6, 0xF8, 0x2C, 0x1E, 0x40, 0x00, 0x94, 0x74, 0xFF, 0x13, 0xEB, ++ 0xE6, 0xF8, 0x2C, 0x8C, 0x50, 0x9F, 0xD3, 0x16, 0x74, 0x62, 0x41, 0x02, 0x08, 0x04, 0xA8, 0x01, ++ 0x33, 0xC3, 0x02, 0x80, 0x02, 0x42, 0xFC, 0xD8, 0x01, 0x90, 0x78, 0x80, 0x13, 0x13, 0xE0, 0xAE, ++ 0xFF, 0x1F, 0x54, 0x13, 0x54, 0xEE, 0x56, 0xAE, 0x08, 0x60, 0x5F, 0x07, 0xF8, 0x2C, 0x8C, 0x74, ++ 0x5E, 0x80, 0x03, 0xA6, 0x54, 0xC4, 0x56, 0xE5, 0xB9, 0x51, 0xFF, 0x0F, 0xE9, 0x1A, 0x60, 0xEF, ++ 0x78, 0xFF, 0x13, 0xC3, 0x9F, 0xD3, 0xE6, 0x90, 0x01, 0x74, 0x48, 0x40, 0x80, 0x08, 0x04, 0xA8, ++ 0xD8, 0x33, 0xC3, 0x02, 0x80, 0x02, 0x42, 0xFC, 0x51, 0x55, 0xAF, 0x39, 0x1A, 0x60, 0xEF, 0xB9, ++ 0xFF, 0x13, 0xC3, 0xEB, 0xD3, 0xE6, 0x8B, 0x78, 0x74, 0x27, 0x40, 0x9F, 0x08, 0x04, 0xA8, 0x01, ++ 0x33, 0xC3, 0x02, 0x80, 0x02, 0x42, 0xFC, 0xD8, 0x55, 0xE5, 0x18, 0x80, 0xFF, 0x0F, 0x54, 0xC4, ++ 0x60, 0xEF, 0xB9, 0x51, 0xA8, 0x01, 0x74, 0x0D, 0x02, 0x80, 0x08, 0x04, 0xFC, 0xD8, 0x33, 0xC3, ++ 0xEC, 0x0C, 0x02, 0x42, 0x02, 0x60, 0x04, 0x64, 0x01, 0x90, 0xA2, 0x21, 0xC7, 0x54, 0xE0, 0xAE, ++ 0x36, 0x06, 0x90, 0xF0, 0xFC, 0x0F, 0x54, 0xE0, 0x04, 0x63, 0x02, 0x52, 0xE0, 0xA3, 0xE0, 0xFF, ++ 0x42, 0x5C, 0x0F, 0x54, 0x80, 0x44, 0xEA, 0x02, 0xF0, 0x08, 0x07, 0x90, 0x53, 0xFE, 0xE4, 0x22, ++ 0x01, 0xBF, 0x07, 0x07, 0xAE, 0x01, 0x90, 0x09, 0xFE, 0x07, 0x54, 0xE0, 0x60, 0xEF, 0x18, 0x80, ++ 0xFF, 0xFE, 0x24, 0x15, 0x07, 0xA8, 0x01, 0x74, 0xC3, 0x02, 0x80, 0x08, 0xFF, 0xFC, 0xD8, 0x33, ++ 0xE0, 0xAD, 0x01, 0x90, 0x06, 0xAF, 0xFE, 0x5F, 0x0F, 0x07, 0x53, 0x22, 0x2B, 0xE3, 0x30, 0xEF, ++ 0x40, 0x0C, 0x94, 0xD3, 0xAE, 0x01, 0x90, 0x11, 0x13, 0x13, 0xC4, 0xE0, 0xEF, 0xFD, 0x03, 0x54, ++ 0xFE, 0x5D, 0x03, 0x54, 0x54, 0xEF, 0x1F, 0x80, 0x01, 0x74, 0xFF, 0x07, 0x80, 0x08, 0x07, 0xA8, ++ 0xD8, 0x33, 0xC3, 0x02, 0x01, 0x90, 0xFF, 0xFC, 0xEF, 0x07, 0x80, 0xAD, 0x90, 0xFF, 0x07, 0x54, ++ 0x5F, 0xE0, 0xAE, 0x01, 0x22, 0x06, 0xAF, 0xFE, 0x83, 0xC0, 0xE0, 0xC0, 0xD0, 0xC0, 0x82, 0xC0, ++ 0x63, 0x00, 0xD0, 0x75, 0x83, 0xC0, 0x01, 0xA2, 0xA2, 0x63, 0x82, 0xC0, 0x90, 0x07, 0xC0, 0x01, ++ 0xC4, 0xE0, 0x65, 0x07, 0xE0, 0x30, 0x0F, 0x54, 0x00, 0x06, 0x90, 0x16, 0xF0, 0x80, 0x44, 0xE0, ++ 0x20, 0xAF, 0xE8, 0xC2, 0xF5, 0x01, 0x44, 0xEF, 0x65, 0x07, 0x90, 0x20, 0xD0, 0xF0, 0x10, 0x74, ++ 0x01, 0xA2, 0x63, 0x07, 0x83, 0xD0, 0x82, 0xD0, 0xD0, 0x01, 0xA2, 0x63, 0xD0, 0x82, 0xD0, 0xD0, ++ 0x32, 0xE0, 0xD0, 0x83, 0xF0, 0xC0, 0xE0, 0xC0, 0xA2, 0x75, 0xA2, 0xC0, 0x75, 0xD0, 0xC0, 0x02, ++ 0x10, 0x85, 0x08, 0xD0, 0xA9, 0x13, 0xAA, 0x90, 0xFF, 0x02, 0x12, 0x14, 0xA2, 0xD0, 0xD0, 0xD0, ++ 0xE0, 0xD0, 0xF0, 0xD0, 0xC0, 0xE0, 0xC0, 0x32, 0x75, 0xA2, 0xC0, 0xF0, 0xD0, 0xC0, 0x02, 0xA2, ++ 0x85, 0x08, 0xD0, 0x75, 0x13, 0xAA, 0x90, 0x10, 0x02, 0x12, 0x14, 0xA9, 0xD0, 0xD0, 0xD0, 0xFF, ++ 0xD0, 0xF0, 0xD0, 0xA2, 0xE0, 0xC0, 0x32, 0xE0, 0xA2, 0xC0, 0xF0, 0xC0, 0xC0, 0x02, 0xA2, 0x75, ++ 0x08, 0xD0, 0x75, 0xD0, 0xE5, 0x90, 0x10, 0x85, 0x06, 0x0B, 0xB4, 0x10, 0x14, 0xA9, 0x13, 0xAA, ++ 0x11, 0xAA, 0x04, 0x80, 0x02, 0x12, 0x12, 0xA9, 0xD0, 0xD0, 0xD0, 0xFF, 0xD0, 0xF0, 0xD0, 0xA2, ++ 0x07, 0xA8, 0x32, 0xE0, 0xE7, 0x09, 0x00, 0xA9, 0x09, 0x60, 0x47, 0x19, 0x18, 0x16, 0xE6, 0x08, ++ 0xC3, 0x16, 0x01, 0x70, 0x90, 0x22, 0xD3, 0x22, 0x20, 0x74, 0x00, 0x0D, 0x7E, 0x00, 0x7F, 0xF0, ++ 0x8F, 0x23, 0x8E, 0x0D, 0x74, 0x01, 0x7D, 0x24, 0xE4, 0xFF, 0x2F, 0x20, 0x24, 0x85, 0xFE, 0x3E, ++ 0x83, 0x23, 0x85, 0x82, 0x8E, 0x82, 0x8F, 0xE0, 0xBD, 0x0D, 0xF0, 0x83, 0x8C, 0x22, 0xE9, 0x04, ++ 0xE4, 0x28, 0x8D, 0x27, 0xF5, 0x82, 0xF5, 0xFB, 0x64, 0xEF, 0xC3, 0x83, 0x50, 0x81, 0x94, 0x80, ++ 0xD3, 0x01, 0x7F, 0x02, 0x94, 0x80, 0x64, 0xEF, 0x7F, 0x02, 0x40, 0xBF, 0xF0, 0x75, 0xEF, 0x3F, ++ 0xAC, 0xFD, 0xA4, 0x04, 0xE7, 0x20, 0xED, 0xF0, 0xE0, 0x25, 0x0B, 0x09, 0xFC, 0x33, 0xEC, 0xFD, ++ 0xFA, 0xE4, 0xF3, 0x80, 0x04, 0xAE, 0x05, 0xAF, 0xAC, 0x98, 0x02, 0x12, 0xED, 0x07, 0xAD, 0x06, ++ 0xC3, 0xCE, 0x07, 0x78, 0xD8, 0x13, 0xCE, 0x13, 0x06, 0xAC, 0xFD, 0xF9, 0x01, 0x94, 0xEC, 0xC3, ++ 0x07, 0x74, 0x24, 0x40, 0x01, 0x74, 0xFF, 0x9A, 0x07, 0xA8, 0x00, 0x7E, 0xC3, 0x05, 0x80, 0x08, ++ 0xCE, 0x33, 0xCE, 0x33, 0x82, 0x25, 0xF9, 0xD8, 0x35, 0xEE, 0x82, 0xF5, 0xEC, 0x83, 0xF5, 0x83, ++ 0xED, 0xFC, 0x13, 0xC3, 0xBA, 0x0A, 0xFD, 0x13, 0x74, 0xC3, 0xBA, 0x08, 0xEF, 0xFF, 0x9B, 0x05, ++ 0x82, 0x25, 0xE4, 0xFE, 0x35, 0xEE, 0x82, 0xF5, 0x7C, 0x83, 0xF5, 0x83, 0xAF, 0x06, 0x7D, 0x00, ++ 0x02, 0x12, 0xFE, 0x82, 0x8F, 0x83, 0x8E, 0x98, 0x82, 0xE5, 0xD3, 0x82, 0x83, 0xE5, 0x28, 0x95, ++ 0x07, 0x40, 0x27, 0x95, 0xF5, 0x83, 0xF5, 0xE4, 0xC3, 0x0D, 0x80, 0x82, 0x82, 0x95, 0x28, 0xE5, ++ 0x27, 0xE5, 0x82, 0xF5, 0x83, 0xF5, 0x83, 0x95, 0x82, 0xF5, 0x83, 0xE5, 0xFF, 0x00, 0x83, 0x75, ++ 0x2A, 0x0A, 0x20, 0x22, 0xD2, 0x05, 0x0B, 0x20, 0x22, 0x99, 0x8F, 0x0B, 0x1C, 0xAE, 0xAC, 0xC2, ++ 0x7C, 0xEE, 0x1C, 0x05, 0x24, 0x7F, 0x54, 0x00, 0xEC, 0x82, 0xF5, 0xAC, 0x83, 0xF5, 0x00, 0x34, ++ 0x1C, 0xE5, 0xF0, 0xEF, 0x7F, 0x54, 0x1B, 0x65, 0x0A, 0xD2, 0x02, 0x70, 0x78, 0x22, 0xAC, 0xD2, ++ 0x7C, 0xFD, 0xE6, 0x82, 0x8A, 0x27, 0x8B, 0x00, 0x8C, 0x29, 0x89, 0x28, 0xC2, 0x2B, 0x8D, 0x2A, ++ 0xAA, 0x27, 0xAB, 0x0D, 0x12, 0x29, 0xA9, 0x28, 0x70, 0xFF, 0x7F, 0x02, 0x20, 0xEC, 0xA1, 0x02, ++ 0x25, 0xB4, 0x19, 0x0D, 0xA1, 0x0D, 0xD2, 0x04, 0x0A, 0xB4, 0xEF, 0xDF, 0x91, 0x0D, 0x7F, 0x08, ++ 0xA1, 0x0A, 0x7F, 0xB1, 0x7F, 0x02, 0x12, 0xDD, 0xC2, 0xDD, 0xA1, 0xFF, 0x7F, 0x02, 0x12, 0x0D, ++ 0x60, 0xBC, 0x24, 0xFB, 0x60, 0xE0, 0x24, 0x4E, 0x60, 0xEC, 0x24, 0x62, 0x75, 0xDA, 0xA1, 0x02, ++ 0xE5, 0xC3, 0x0C, 0x2C, 0x94, 0x80, 0x64, 0x2C, 0xA1, 0x02, 0x50, 0x80, 0xAE, 0x2B, 0xE5, 0xDF, ++ 0x08, 0x2C, 0xA8, 0x2A, 0xA2, 0xCE, 0x06, 0x80, 0x13, 0xCE, 0x13, 0xE7, 0x0F, 0x54, 0xF8, 0xD8, ++ 0x64, 0xD3, 0x32, 0xF5, 0x40, 0x89, 0x94, 0x80, 0x24, 0x32, 0xE5, 0x08, 0x80, 0x32, 0xF5, 0x37, ++ 0x25, 0x30, 0x74, 0x06, 0xAF, 0x32, 0xF5, 0x32, 0x74, 0xB1, 0x91, 0x32, 0xF5, 0x2C, 0x25, 0xFC, ++ 0xC3, 0xBF, 0x80, 0x2C, 0x80, 0x64, 0x2A, 0xE5, 0x0F, 0x50, 0x80, 0x94, 0x2B, 0x95, 0xE4, 0xC3, ++ 0x95, 0xE4, 0x2B, 0xF5, 0x7F, 0x2A, 0xF5, 0x2A, 0xE5, 0xB1, 0x91, 0x2D, 0x70, 0x2A, 0x45, 0x2B, ++ 0x91, 0x30, 0x7F, 0x04, 0x2C, 0xF5, 0xE4, 0xB1, 0x2A, 0x45, 0x2B, 0xE5, 0x2A, 0xAE, 0x2B, 0x60, ++ 0x00, 0x7C, 0x2B, 0xAF, 0x02, 0x12, 0x0A, 0x7D, 0x30, 0x24, 0xED, 0xAA, 0x05, 0x2C, 0xAE, 0xFF, ++ 0x2E, 0x2D, 0x74, 0x2C, 0xC6, 0xEF, 0xC6, 0xF8, 0x2B, 0xAF, 0x2A, 0xAE, 0x0A, 0x7D, 0x00, 0x7C, ++ 0x8E, 0xAA, 0x02, 0x12, 0x80, 0x2B, 0x8F, 0x2A, 0x60, 0x2C, 0xE5, 0xCF, 0x74, 0x2C, 0x15, 0x12, ++ 0xF8, 0x2C, 0x25, 0x2D, 0xB1, 0x91, 0xFF, 0xE6, 0xEB, 0xCF, 0xEF, 0x80, 0x74, 0xB1, 0x91, 0xCF, ++ 0xF5, 0x29, 0x25, 0x01, 0x28, 0x35, 0xE4, 0x29, 0xF1, 0x81, 0x28, 0xF5, 0x1B, 0x06, 0x90, 0x22, ++ 0x24, 0x1F, 0x54, 0xE0, 0x24, 0x5C, 0x60, 0xF9, 0x14, 0x7C, 0x60, 0xE9, 0x7F, 0xC1, 0x02, 0x70, ++ 0x02, 0x60, 0x1C, 0x24, 0x1E, 0xE5, 0x9F, 0xC1, 0x24, 0x11, 0x60, 0x14, 0x24, 0x24, 0x60, 0xED, ++ 0x24, 0x25, 0x60, 0xFE, 0x90, 0x36, 0x70, 0x16, 0x48, 0x80, 0xB5, 0x01, 0xE0, 0xB9, 0x01, 0x90, ++ 0x90, 0xE0, 0xA3, 0xFF, 0xF0, 0xCF, 0x1C, 0x06, 0x90, 0xF0, 0xEF, 0xA3, 0x54, 0xE0, 0xB9, 0x01, ++ 0x90, 0x22, 0xF0, 0x03, 0x2C, 0x80, 0xB3, 0x01, 0xE0, 0xB1, 0x01, 0x90, 0x90, 0xE0, 0xA3, 0xFF, ++ 0xF0, 0xCF, 0x1C, 0x06, 0xE4, 0xF0, 0xEF, 0xA3, 0x80, 0xB1, 0x01, 0x90, 0x06, 0x90, 0xE4, 0x56, ++ 0xE5, 0x50, 0x80, 0x1C, 0x60, 0xC3, 0x24, 0x1E, 0x15, 0x70, 0x04, 0x08, 0x80, 0xAF, 0x01, 0x90, ++ 0xB7, 0x01, 0x90, 0x03, 0xE0, 0xA3, 0xFF, 0xE0, 0xCF, 0x1C, 0x06, 0x90, 0xF0, 0xEF, 0xA3, 0xF0, ++ 0x06, 0x90, 0xE4, 0x22, 0x90, 0x2C, 0x80, 0x1C, 0x44, 0xE0, 0x2C, 0x06, 0xE4, 0x22, 0xF0, 0x40, ++ 0xF0, 0x1C, 0x06, 0x90, 0x85, 0x82, 0x1E, 0x85, 0x90, 0xE0, 0x83, 0x1D, 0x74, 0xF0, 0x1D, 0x06, ++ 0x12, 0x1E, 0xB5, 0xEB, 0x1D, 0xB5, 0x01, 0x74, 0x01, 0x90, 0xE4, 0x0D, 0xE4, 0x04, 0x80, 0xEA, ++ 0xF0, 0x1C, 0x06, 0x90, 0x12, 0x22, 0xF0, 0xA3, 0x01, 0x12, 0xB1, 0x01, 0xCA, 0x01, 0x12, 0xC0, ++ 0x57, 0x46, 0x55, 0x80, 0x48, 0x50, 0x47, 0x5F, 0x52, 0x56, 0x5F, 0x59, 0x50, 0x00, 0x0A, 0x39, ++ 0x3A, 0x4C, 0x4F, 0x54, 0x0A, 0x44, 0x25, 0x20, 0x7D, 0x93, 0xAA, 0x00, 0x22, 0x39, 0x4F, 0x66, ++ 0x69, 0x6E, 0x49, 0x0B, 0x09, 0x00, 0x0A, 0x74, 0x00, 0x0A, 0x30, 0x44, 0x0A, 0x31, 0x44, 0x09, ++ 0x32, 0x44, 0x09, 0x00, 0x45, 0x09, 0x00, 0x0A, 0x70, 0x65, 0x63, 0x78, 0x6E, 0x6F, 0x69, 0x74, ++ 0x45, 0x09, 0x00, 0x0A, 0x0A, 0x74, 0x69, 0x78, 0x8C, 0xC2, 0x01, 0x00, 0xE4, 0x01, 0x89, 0x43, ++ 0x8C, 0xF5, 0x8A, 0xF5, 0xE4, 0x22, 0x8C, 0xD2, 0x5A, 0xF5, 0x59, 0xF5, 0x60, 0xF5, 0x5F, 0xF5, ++ 0x5C, 0xF5, 0x5B, 0xF5, 0xF0, 0xAC, 0x01, 0x90, 0xF0, 0xA0, 0x00, 0x90, 0xD2, 0x01, 0x71, 0x75, ++ 0x02, 0x5D, 0x75, 0x08, 0x11, 0x1A, 0x5E, 0x75, 0x7B, 0xC4, 0x11, 0xCE, 0x79, 0x20, 0x7A, 0xFF, ++ 0xF8, 0x03, 0x12, 0x02, 0x4A, 0x11, 0x6C, 0x31, 0x61, 0x7C, 0xA8, 0x7D, 0xDC, 0x11, 0xFF, 0xE4, ++ 0x61, 0x7C, 0xA8, 0x7D, 0x03, 0x31, 0xFF, 0xE4, 0xAD, 0x11, 0xFF, 0xE4, 0xAD, 0x11, 0x01, 0x7F, ++ 0x02, 0x12, 0x2C, 0x31, 0x12, 0xFF, 0xE4, 0x29, 0x01, 0x02, 0x60, 0x02, 0xED, 0x07, 0xAD, 0xB6, ++ 0x07, 0x90, 0x07, 0x70, 0x01, 0x44, 0xE0, 0x47, 0x07, 0x01, 0xBD, 0xF0, 0xE0, 0x47, 0x07, 0x90, ++ 0x22, 0xF0, 0x02, 0x44, 0xF5, 0x1B, 0xF5, 0xE4, 0xC2, 0x0B, 0xC2, 0x1C, 0x8E, 0xC2, 0x22, 0x0A, ++ 0x43, 0xC2, 0x98, 0x75, 0x8D, 0x75, 0x20, 0x89, 0x22, 0x8E, 0xD2, 0xEF, 0xE0, 0x47, 0x07, 0x90, ++ 0xEF, 0xF0, 0xFE, 0x54, 0x90, 0xFF, 0x01, 0x54, 0x54, 0xE0, 0x48, 0x07, 0xE4, 0xF0, 0x4F, 0xFE, ++ 0xF0, 0x4A, 0x07, 0x90, 0xF0, 0x49, 0x07, 0x90, 0x4C, 0x07, 0x90, 0xED, 0x07, 0x90, 0xEC, 0xF0, ++ 0x90, 0x22, 0xF0, 0x4B, 0x54, 0xE0, 0x47, 0x07, 0x54, 0xEF, 0xF0, 0xFD, 0xFF, 0xE0, 0x25, 0x01, ++ 0xE0, 0x48, 0x07, 0x90, 0xF0, 0x4F, 0xFD, 0x54, 0x4E, 0x07, 0x90, 0xE4, 0x4D, 0x07, 0x90, 0xF0, ++ 0x07, 0x90, 0xED, 0xF0, 0x90, 0xEC, 0xF0, 0x50, 0x22, 0xF0, 0x4F, 0x07, 0xE0, 0x07, 0x07, 0x90, ++ 0xE0, 0xF0, 0x01, 0x44, 0x90, 0xF0, 0xEF, 0x54, 0x44, 0xE0, 0x00, 0x07, 0x54, 0xE0, 0xF0, 0x04, ++ 0x90, 0xE4, 0xF0, 0xFB, 0x90, 0xF0, 0x03, 0x07, 0x90, 0xF0, 0x04, 0x07, 0xF0, 0x04, 0x05, 0x07, ++ 0x74, 0x06, 0x07, 0x90, 0x07, 0x90, 0xF0, 0xFF, 0xF0, 0x04, 0x74, 0x01, 0xF0, 0xF7, 0x54, 0xE0, ++ 0x02, 0x12, 0x02, 0x7F, 0x00, 0x07, 0x90, 0x24, 0x22, 0xF0, 0x01, 0x74, 0xE0, 0x8B, 0x0D, 0x90, ++ 0xFF, 0x0F, 0x54, 0xC4, 0xE3, 0x30, 0x0C, 0xC2, 0x63, 0x0C, 0xD2, 0x05, 0x90, 0xEF, 0x0F, 0x07, ++ 0xFD, 0x93, 0x19, 0x20, 0x0C, 0x30, 0x00, 0x7C, 0x9D, 0xE4, 0xC3, 0x07, 0xFC, 0x9C, 0xE4, 0xFD, ++ 0xE0, 0x8B, 0x0D, 0x90, 0x20, 0x13, 0xC3, 0xFF, 0x7F, 0x7C, 0x04, 0xE0, 0xFF, 0x7B, 0xFF, 0x7D, ++ 0x0F, 0x79, 0x20, 0x7A, 0x7E, 0xE5, 0x0C, 0x02, 0x12, 0xD6, 0x7F, 0x27, 0x24, 0x7E, 0x3A, 0x03, ++ 0x03, 0x12, 0xE2, 0x7F, 0x7F, 0x2E, 0x7E, 0x3A, 0x3A, 0x03, 0x12, 0x65, 0x19, 0x7F, 0x20, 0x7E, ++ 0x7E, 0x3A, 0x03, 0x12, 0x12, 0x97, 0x7F, 0x2F, 0x24, 0x7E, 0x3A, 0x03, 0x03, 0x12, 0x63, 0x7F, ++ 0x7F, 0x27, 0x7E, 0x3A, 0x3A, 0x03, 0x12, 0x17, 0x37, 0x7F, 0x2D, 0x7E, 0x7E, 0x3A, 0x03, 0x12, ++ 0x12, 0xAF, 0x7F, 0x2F, 0x30, 0x7E, 0x3A, 0x03, 0x03, 0x12, 0x17, 0x7F, 0x7F, 0x29, 0x7E, 0x3A, ++ 0x3A, 0x03, 0x12, 0x99, 0x00, 0x7F, 0x20, 0x7E, 0x7E, 0x3A, 0x03, 0x12, 0x12, 0x65, 0x7F, 0x23, ++ 0x20, 0x7E, 0x3A, 0x03, 0x03, 0x02, 0xD0, 0x7F, 0x60, 0x71, 0xE5, 0x3A, 0x7A, 0xFF, 0x7B, 0x11, ++ 0x12, 0x21, 0x79, 0x20, 0x5B, 0x75, 0xF8, 0x03, 0x4F, 0x5C, 0x75, 0x22, 0x20, 0x90, 0x08, 0xD2, ++ 0xFF, 0x93, 0xE4, 0x49, 0xE0, 0xAC, 0x01, 0x90, 0x75, 0x06, 0x07, 0xB5, 0x60, 0x75, 0x22, 0x5F, ++ 0x65, 0x60, 0xE5, 0x82, 0xE5, 0x04, 0x70, 0x5C, 0x60, 0x5B, 0x65, 0x5F, 0x5F, 0x5B, 0x85, 0x08, ++ 0xD2, 0x60, 0x5C, 0x85, 0xA9, 0x5F, 0xAA, 0x08, 0xFF, 0x02, 0x12, 0x60, 0x7B, 0x22, 0x08, 0xC2, ++ 0x79, 0x20, 0x7A, 0xFF, 0xF8, 0x03, 0x12, 0x27, 0x75, 0x20, 0xF5, 0xE4, 0x5C, 0x75, 0x22, 0x5B, ++ 0xFF, 0x7B, 0x22, 0x62, 0x2C, 0x79, 0x20, 0x7A, 0x75, 0xF8, 0x03, 0x12, 0x5C, 0x75, 0x22, 0x5B, ++ 0xFF, 0x7B, 0x22, 0x72, 0x31, 0x79, 0x20, 0x7A, 0x75, 0xF8, 0x03, 0x12, 0x5C, 0x75, 0x22, 0x5B, ++ 0x90, 0xE4, 0x22, 0x97, 0x7B, 0xF0, 0xAC, 0x01, 0x79, 0x20, 0x7A, 0xFF, 0xF8, 0x03, 0x12, 0x36, ++ 0x75, 0x22, 0x5B, 0x75, 0x7B, 0x22, 0x4F, 0x5C, 0x79, 0x20, 0x7A, 0xFF, 0xF8, 0x03, 0x12, 0x42, ++ 0x75, 0x01, 0x5D, 0x75, 0x22, 0x22, 0xC5, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x1C, 0xC1, 0x8C, 0x01, 0xC0, 0x00, 0xEE, 0x00, 0x1F, 0x00, 0xDE, 0x00, 0x49, 0x79, 0x00, 0x90, ++ 0x08, 0xA4, 0x65, 0xD5, 0x00, 0x00, 0xE1, 0x01, 0x01, 0x20, 0x04, 0x00, 0x00, 0x03, 0x01, 0x20, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x80, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x0F, 0x00, 0x00, 0xAA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x83, 0xFF, 0xFF, 0x3F, 0x00, ++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x40, 0x00, 0x48, 0xFF, 0xFF, 0x00, 0x00, 0xFF, 0xFF, ++ 0xFF, 0xFF, 0xFF, 0xFF, 0xE0, 0x3F, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, ++ 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xF0, 0xF0, 0x38, 0x00, 0x00, 0xFF, 0x7F, 0xC0, 0x03, 0xFF, 0xFF, ++ 0xF0, 0xF0, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0xD0, 0xFF, 0xFF, 0xFF, 0xFF, 0x90, 0x22, 0xF5, 0xE4, ++ 0x61, 0x74, 0x4B, 0x07, 0x4C, 0x07, 0x90, 0xF0, 0x7F, 0xF0, 0xA8, 0x74, 0x8D, 0x03, 0x12, 0x0A, ++ 0x90, 0x96, 0x03, 0x12, 0xFF, 0xE0, 0x00, 0x06, 0x13, 0x13, 0x13, 0xC4, 0xE0, 0x30, 0x01, 0x54, ++ 0x7F, 0xE8, 0xC2, 0x30, 0xE4, 0xDB, 0x51, 0x03, 0x01, 0x90, 0x20, 0xF5, 0xF0, 0xA3, 0xF0, 0xAD, ++ 0xF0, 0xA1, 0x00, 0x90, 0x08, 0x60, 0x22, 0xE5, 0x74, 0x04, 0x20, 0x90, 0x22, 0xF5, 0x93, 0x01, ++ 0xE0, 0x00, 0x06, 0x90, 0xA3, 0xF0, 0x7F, 0x54, 0x06, 0x90, 0xF0, 0xE0, 0x7F, 0x54, 0xE0, 0x80, ++ 0x00, 0x07, 0x90, 0xF0, 0xD2, 0xF0, 0x01, 0x74, 0x90, 0x4C, 0x31, 0xE8, 0x44, 0xE0, 0x61, 0x07, ++ 0x44, 0xE0, 0xF0, 0x20, 0x44, 0xE0, 0xF0, 0x40, 0x54, 0xE0, 0xF0, 0x10, 0x54, 0xE0, 0xF0, 0xDF, ++ 0x54, 0xE0, 0xF0, 0xBF, 0x0B, 0x12, 0xF0, 0xEF, 0x01, 0x0D, 0x90, 0xC7, 0x7F, 0xF0, 0xDF, 0x74, ++ 0x12, 0x0D, 0x7E, 0x01, 0x0D, 0x90, 0xD1, 0x0B, 0xF0, 0x35, 0x74, 0x0C, 0x0D, 0x7E, 0x0C, 0x7F, ++ 0x90, 0xD1, 0x0B, 0x12, 0x2B, 0x74, 0x08, 0x0D, 0x7E, 0x08, 0x7F, 0xF0, 0xD1, 0x0B, 0x12, 0x0D, ++ 0xE0, 0xD4, 0x09, 0x90, 0xE0, 0xF0, 0x80, 0x44, 0x90, 0xF0, 0xBF, 0x54, 0x7F, 0x74, 0xD9, 0x09, ++ 0xFC, 0x07, 0x90, 0xF0, 0xC2, 0xF0, 0x6A, 0x74, 0x0B, 0x02, 0x02, 0x0C, 0xE0, 0x8B, 0x0D, 0x90, ++ 0x3F, 0x54, 0x13, 0x13, 0x90, 0x56, 0xE0, 0x30, 0xC3, 0xE0, 0x27, 0x06, 0x25, 0xE0, 0x30, 0x13, ++ 0x01, 0x54, 0xC4, 0xE0, 0x01, 0x74, 0xC3, 0xFF, 0x92, 0xFF, 0x24, 0x9F, 0x51, 0x58, 0x7F, 0x0C, ++ 0xA4, 0x00, 0x90, 0xB2, 0x06, 0x90, 0xF0, 0xEF, 0x13, 0xC4, 0xE0, 0x27, 0x92, 0x13, 0x07, 0x54, ++ 0x80, 0x58, 0x7F, 0x0C, 0x27, 0x06, 0x90, 0x7C, 0x01, 0x54, 0xC4, 0xE0, 0x01, 0x74, 0xC3, 0xFF, ++ 0x92, 0xFF, 0x24, 0x9F, 0x51, 0x78, 0x7F, 0x0C, 0xA4, 0x00, 0x90, 0xB2, 0x06, 0x90, 0xF0, 0xEF, ++ 0x13, 0xC4, 0xE0, 0x27, 0x92, 0x13, 0x07, 0x54, 0x80, 0x78, 0x7F, 0x0C, 0x27, 0x06, 0x90, 0x54, ++ 0x30, 0x13, 0xC3, 0xE0, 0xC4, 0xE0, 0x25, 0xE0, 0xC3, 0xFF, 0x01, 0x54, 0x24, 0x9F, 0x01, 0x74, ++ 0x7F, 0x0C, 0x92, 0xFF, 0x90, 0xB2, 0x51, 0x51, 0xF0, 0xEF, 0xA4, 0x00, 0xE0, 0x27, 0x06, 0x90, ++ 0x07, 0x54, 0x13, 0xC4, 0x7F, 0x0C, 0x92, 0x13, 0x90, 0x26, 0x80, 0x51, 0xC4, 0xE0, 0x27, 0x06, ++ 0xC3, 0xFF, 0x01, 0x54, 0x24, 0x9F, 0x01, 0x74, 0x7F, 0x0C, 0x92, 0xFF, 0x90, 0xB2, 0x51, 0x61, ++ 0xF0, 0xEF, 0xA4, 0x00, 0xE0, 0x27, 0x06, 0x90, 0x07, 0x54, 0x13, 0xC4, 0x7F, 0x0C, 0x92, 0x13, ++ 0x90, 0xB2, 0x51, 0x61, 0xF0, 0xEF, 0xA5, 0x00, 0xE0, 0xA4, 0x00, 0x90, 0xF0, 0xA2, 0x00, 0x90, ++ 0xE0, 0xA5, 0x00, 0x90, 0xF0, 0xA3, 0x00, 0x90, 0xE0, 0x27, 0x06, 0x90, 0xFF, 0x01, 0x54, 0xC4, ++ 0x9F, 0x01, 0x74, 0xC3, 0x0C, 0x92, 0xFF, 0x24, 0xB2, 0x51, 0x70, 0x7F, 0xEF, 0xA6, 0x00, 0x90, ++ 0x27, 0x06, 0x90, 0xF0, 0x54, 0x13, 0xC4, 0xE0, 0x0C, 0x92, 0x13, 0x07, 0xB2, 0x51, 0x70, 0x7F, ++ 0xEF, 0xA7, 0x00, 0x90, 0x27, 0x06, 0x90, 0xF0, 0xA5, 0x51, 0xC4, 0xE0, 0xEF, 0xA8, 0x00, 0x90, ++ 0x27, 0x06, 0x90, 0xF0, 0x54, 0x13, 0xC4, 0xE0, 0xAE, 0x51, 0x13, 0x07, 0xEF, 0xA9, 0x00, 0x90, ++ 0x27, 0x06, 0x90, 0xF0, 0x13, 0x13, 0xC4, 0xE0, 0x00, 0x90, 0xA5, 0x51, 0x90, 0xF0, 0xEF, 0xAA, ++ 0xC4, 0xE0, 0x27, 0x06, 0x54, 0x13, 0x13, 0x13, 0xAE, 0x51, 0x13, 0x01, 0xEF, 0xAB, 0x00, 0x90, ++ 0xA5, 0x00, 0x90, 0xF0, 0xF0, 0x04, 0xF4, 0xE0, 0xE0, 0xA3, 0x00, 0x90, 0x90, 0xF0, 0x04, 0xF4, ++ 0xF4, 0xE0, 0xA7, 0x00, 0x00, 0x90, 0xF0, 0x04, 0x04, 0xF4, 0xE0, 0xA9, 0xAB, 0x00, 0x90, 0xF0, ++ 0xF0, 0x04, 0xF4, 0xE0, 0xFF, 0x01, 0x54, 0x22, 0x9F, 0x01, 0x74, 0xC3, 0x0C, 0x92, 0xFF, 0x24, ++ 0x06, 0x90, 0x74, 0x7F, 0x0F, 0x54, 0xE0, 0x26, 0x80, 0x64, 0xD3, 0xFE, 0x04, 0x40, 0x87, 0x94, ++ 0xFE, 0x2E, 0xF0, 0x74, 0x30, 0xFF, 0x2F, 0xEE, 0x04, 0xF4, 0x03, 0x0C, 0x26, 0x06, 0x90, 0xFF, ++ 0x0F, 0x54, 0xC4, 0xE0, 0x7F, 0x03, 0xE0, 0x30, 0x8F, 0x22, 0x22, 0x00, 0x7D, 0x20, 0x7C, 0x23, ++ 0x7F, 0x23, 0xAB, 0x0C, 0x91, 0x06, 0x7E, 0x00, 0x64, 0x23, 0xE5, 0xB7, 0xFB, 0x20, 0x70, 0x02, ++ 0x40, 0x7F, 0xFC, 0xFD, 0xB7, 0x91, 0x06, 0x7E, 0x4C, 0x7D, 0x20, 0x7C, 0x80, 0x7F, 0x02, 0x7B, ++ 0xB7, 0x91, 0x06, 0x7E, 0xFD, 0xE4, 0x01, 0x7B, 0x7E, 0xC0, 0x7F, 0xFC, 0xE5, 0xB7, 0x91, 0x06, ++ 0x60, 0x02, 0x64, 0x23, 0x64, 0x23, 0xE5, 0x0D, 0x90, 0x41, 0x70, 0x03, 0x20, 0xE0, 0x28, 0x06, ++ 0x90, 0xE4, 0x3A, 0xE0, 0xA3, 0xF0, 0xB5, 0x01, 0xB9, 0x01, 0x90, 0xF0, 0x90, 0xF0, 0xA3, 0xF0, ++ 0xA3, 0xF0, 0xB3, 0x01, 0xE4, 0xF0, 0x06, 0x74, 0xF0, 0xB1, 0x01, 0x90, 0x01, 0x90, 0xF0, 0xA3, ++ 0xF0, 0xA3, 0xF0, 0xAF, 0xF0, 0xB7, 0x01, 0x90, 0x01, 0x90, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xEA, ++ 0xF0, 0xEC, 0x01, 0x90, 0xF0, 0xFF, 0x01, 0x90, 0x1E, 0xF5, 0x1D, 0xF5, 0xE0, 0x08, 0x06, 0x90, ++ 0xA3, 0xF0, 0xE0, 0x54, 0xF0, 0x1F, 0x54, 0xE0, 0xE0, 0x0D, 0x07, 0x90, 0x54, 0x13, 0x13, 0xFF, ++ 0x3C, 0xE0, 0x30, 0x3F, 0xE0, 0x08, 0x06, 0x90, 0xFD, 0xE0, 0xA3, 0xFC, 0x02, 0x7B, 0x00, 0x7A, ++ 0x05, 0x78, 0x04, 0xAE, 0xCE, 0x13, 0xC3, 0xCE, 0xFF, 0xF9, 0xD8, 0x13, 0xFC, 0xE0, 0x54, 0xEC, ++ 0xFD, 0x1F, 0x54, 0xED, 0x00, 0x7E, 0x4B, 0xEF, 0x33, 0xC3, 0x05, 0x78, 0xD8, 0xCE, 0x33, 0xCE, ++ 0x4E, 0xEC, 0xFF, 0xF9, 0xFF, 0x4F, 0xED, 0xFE, 0xEE, 0x08, 0x06, 0x90, 0xF0, 0xEF, 0xA3, 0xF0, ++ 0xE0, 0x0D, 0x07, 0x90, 0x13, 0x13, 0x13, 0xFF, 0xE0, 0x30, 0x1F, 0x54, 0x08, 0x06, 0x90, 0x3C, ++ 0xE0, 0xA3, 0xFC, 0xE0, 0x7B, 0x00, 0x7A, 0xFD, 0x78, 0x04, 0xAE, 0x01, 0x13, 0xC3, 0xCE, 0x05, ++ 0xF9, 0xD8, 0x13, 0xCE, 0xE0, 0x54, 0xEC, 0xFF, 0x1F, 0x54, 0xED, 0xFC, 0x7E, 0x4B, 0xEF, 0xFD, ++ 0xC3, 0x05, 0x78, 0x00, 0xCE, 0x33, 0xCE, 0x33, 0xEC, 0xFF, 0xF9, 0xD8, 0x4F, 0xED, 0xFE, 0x4E, ++ 0x08, 0x06, 0x90, 0xFF, 0xEF, 0xA3, 0xF0, 0xEE, 0x0D, 0x07, 0x90, 0xF0, 0x54, 0xC4, 0xFF, 0xE0, ++ 0x3C, 0xE0, 0x30, 0x0F, 0xE0, 0x08, 0x06, 0x90, 0xFD, 0xE0, 0xA3, 0xFC, 0x08, 0x7B, 0x00, 0x7A, ++ 0x05, 0x78, 0x04, 0xAE, 0xCE, 0x13, 0xC3, 0xCE, 0xFF, 0xF9, 0xD8, 0x13, 0xFC, 0xE0, 0x54, 0xEC, ++ 0xFD, 0x1F, 0x54, 0xED, 0x00, 0x7E, 0x4B, 0xEF, 0x33, 0xC3, 0x05, 0x78, 0xD8, 0xCE, 0x33, 0xCE, ++ 0x4E, 0xEC, 0xFF, 0xF9, 0xFF, 0x4F, 0xED, 0xFE, 0xEE, 0x08, 0x06, 0x90, 0xF0, 0xEF, 0xA3, 0xF0, ++ 0xE0, 0x0D, 0x07, 0x90, 0x54, 0x13, 0xC4, 0xFF, 0x3C, 0xE0, 0x30, 0x07, 0xE0, 0x08, 0x06, 0x90, ++ 0xFD, 0xE0, 0xA3, 0xFC, 0x04, 0x7B, 0x00, 0x7A, 0x05, 0x78, 0x04, 0xAE, 0xCE, 0x13, 0xC3, 0xCE, ++ 0xFF, 0xF9, 0xD8, 0x13, 0xFC, 0xE0, 0x54, 0xEC, 0xFD, 0x1F, 0x54, 0xED, 0x00, 0x7E, 0x4B, 0xEF, ++ 0x33, 0xC3, 0x05, 0x78, 0xD8, 0xCE, 0x33, 0xCE, 0x4E, 0xEC, 0xFF, 0xF9, 0xFF, 0x4F, 0xED, 0xFE, ++ 0xEE, 0x08, 0x06, 0x90, 0xF0, 0xEF, 0xA3, 0xF0, 0xE0, 0x0D, 0x07, 0x90, 0x13, 0xC3, 0x02, 0x54, ++ 0x12, 0x06, 0x90, 0xFF, 0x4F, 0xFE, 0x54, 0xE0, 0x0D, 0x07, 0x90, 0xF0, 0x25, 0x01, 0x54, 0xE0, ++ 0x06, 0x90, 0xFF, 0xE0, 0xFD, 0x54, 0xE0, 0x12, 0x06, 0x90, 0xF0, 0x4F, 0xDF, 0x54, 0xE0, 0x00, ++ 0x44, 0xE0, 0xA3, 0xF0, 0x8E, 0x22, 0xF0, 0x40, 0x8C, 0x25, 0x8F, 0x24, 0x90, 0x27, 0x8D, 0x26, ++ 0x13, 0xE0, 0x28, 0x06, 0x06, 0x90, 0x0C, 0x92, 0x13, 0xC4, 0xE0, 0x2C, 0x01, 0x54, 0x13, 0x13, ++ 0xE4, 0x0D, 0x92, 0x13, 0x60, 0x14, 0xEB, 0xFF, 0x60, 0xFE, 0x24, 0x0B, 0x70, 0x03, 0x24, 0x0F, ++ 0x02, 0x80, 0xE4, 0x69, 0x28, 0xF5, 0xFF, 0x74, 0x79, 0x80, 0x29, 0xF5, 0xEF, 0x5B, 0x0C, 0x30, ++ 0x40, 0x0F, 0x94, 0xD3, 0xE0, 0x25, 0xEF, 0x55, 0x82, 0xF5, 0x4C, 0x24, 0xF5, 0x20, 0x34, 0xE4, ++ 0xF5, 0x93, 0xE4, 0x83, 0x93, 0x01, 0x74, 0x2C, 0x27, 0xE5, 0x2D, 0xF5, 0xF5, 0x02, 0x24, 0xFD, ++ 0xFC, 0x26, 0xE5, 0x27, 0x26, 0xF5, 0x00, 0x34, 0x83, 0x8C, 0x82, 0x8D, 0x2C, 0x55, 0x93, 0xE4, ++ 0x01, 0x74, 0x2A, 0xF5, 0xF5, 0x2D, 0x55, 0x93, 0x82, 0x25, 0x85, 0x2B, 0xE5, 0x83, 0x24, 0x85, ++ 0xE5, 0xFD, 0xF4, 0x2D, 0xE0, 0xFC, 0xF4, 0x2C, 0xE0, 0xA3, 0xFC, 0x5C, 0x2A, 0xE5, 0xFD, 0x5D, ++ 0xE5, 0x28, 0xF5, 0x4C, 0x29, 0xF5, 0x4D, 0x2B, 0x27, 0xE5, 0x1B, 0x80, 0xF5, 0x02, 0x24, 0xFD, ++ 0xFC, 0x26, 0xE5, 0x27, 0x26, 0xF5, 0x00, 0x34, 0x83, 0x8C, 0x82, 0x8D, 0x28, 0xF5, 0x93, 0xE4, ++ 0xF5, 0x93, 0x01, 0x74, 0xFD, 0x25, 0xE5, 0x29, 0x25, 0xF5, 0x02, 0x24, 0x34, 0xFC, 0x24, 0xE5, ++ 0x8D, 0x24, 0xF5, 0x00, 0xE5, 0x83, 0x8C, 0x82, 0xE5, 0xA3, 0xF0, 0x28, 0xEF, 0x0F, 0xF0, 0x29, ++ 0x02, 0x60, 0x20, 0x64, 0x0C, 0x30, 0xD5, 0x81, 0x06, 0x90, 0xE4, 0x07, 0xF0, 0xA3, 0xF0, 0x38, ++ 0x70, 0x03, 0x64, 0xEB, 0x33, 0x0C, 0xA2, 0x23, 0x90, 0xFF, 0x01, 0x54, 0x54, 0xE0, 0x28, 0x06, ++ 0xA2, 0xF0, 0x4F, 0xFE, 0x54, 0x33, 0xE4, 0x0D, 0x33, 0x33, 0xC4, 0x01, 0xFF, 0x80, 0x54, 0x33, ++ 0xE0, 0x2C, 0x06, 0x90, 0xF0, 0x4F, 0x7F, 0x54, 0x01, 0x90, 0xE4, 0x22, 0xF0, 0xA3, 0xF0, 0xAD, ++ 0x78, 0xF6, 0x90, 0x78, 0x8C, 0x78, 0xF6, 0x8B, 0x08, 0xF6, 0x08, 0xF6, 0x78, 0xF6, 0x08, 0xF6, ++ 0x78, 0xAA, 0x76, 0x92, 0x78, 0x01, 0x76, 0x8A, 0x01, 0x90, 0xF6, 0x91, 0xF0, 0xC5, 0x74, 0xE0, ++ 0xF0, 0x67, 0x74, 0xA3, 0x74, 0xE2, 0x01, 0x90, 0x74, 0xA3, 0xF0, 0x70, 0x01, 0x90, 0xF0, 0x03, ++ 0xF0, 0x20, 0x74, 0xE4, 0x90, 0xF0, 0xE4, 0xA3, 0x40, 0x74, 0xE6, 0x01, 0xF0, 0xE4, 0xA3, 0xF0, ++ 0x74, 0xE8, 0x01, 0x90, 0x74, 0xA3, 0xF0, 0x40, 0x06, 0x90, 0xF0, 0x20, 0xF0, 0x0F, 0x74, 0x36, ++ 0x90, 0xF0, 0xE4, 0xA3, 0xE0, 0xF0, 0x08, 0x07, 0x22, 0xF0, 0x80, 0x44, 0x01, 0x0D, 0x90, 0xE4, ++ 0x21, 0x0D, 0x90, 0xF0, 0x41, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0xFF, 0x74, 0x90, 0xF0, 0x61, 0x0D, ++ 0x54, 0xE0, 0x00, 0x0D, 0x44, 0xE0, 0xF0, 0xF8, 0x90, 0xE0, 0xF0, 0x18, 0x90, 0xF0, 0x20, 0x0D, ++ 0x49, 0x74, 0x0A, 0x0D, 0x2A, 0x0D, 0x90, 0xF0, 0x06, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x5C, 0x74, ++ 0x90, 0xF0, 0x26, 0x0D, 0x4A, 0x74, 0x0B, 0x0D, 0x2B, 0x0D, 0x90, 0xF0, 0x82, 0x0D, 0x90, 0xF0, ++ 0x90, 0xF0, 0xAA, 0x74, 0x11, 0x74, 0x0C, 0x0D, 0x2C, 0x0D, 0x90, 0xF0, 0x02, 0x0D, 0x90, 0xF0, ++ 0x90, 0xF0, 0x30, 0x74, 0x90, 0xF0, 0x22, 0x0D, 0x20, 0x74, 0x05, 0x0D, 0x25, 0x0D, 0x90, 0xF0, ++ 0xF0, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x44, 0xE0, 0xF5, 0x07, 0x44, 0xE0, 0xF0, 0x01, ++ 0x54, 0xE0, 0xF0, 0x02, 0x08, 0x90, 0xF0, 0xFD, 0x01, 0x44, 0xE0, 0x5C, 0xFD, 0x09, 0x90, 0xF0, ++ 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0x74, 0x5F, 0x08, 0x90, 0x08, 0x90, 0xF0, 0xAB, ++ 0x90, 0xF0, 0x14, 0x5E, 0x0A, 0x74, 0x5D, 0x08, 0x60, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, ++ 0x54, 0xE0, 0xFF, 0x07, 0x07, 0x90, 0xF0, 0xFD, 0x01, 0x44, 0xE0, 0xFE, 0x02, 0x44, 0xE0, 0xF0, ++ 0xF7, 0x54, 0xE0, 0xF0, 0xFB, 0x54, 0xE0, 0xF0, 0xFD, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, ++ 0xF0, 0xFD, 0x54, 0xE0, 0xF0, 0xF7, 0x54, 0xE0, 0xF0, 0x04, 0x44, 0xE0, 0x00, 0x00, 0x00, 0x00, ++ 0xFE, 0x07, 0x90, 0x00, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0xFD, 0x07, 0x90, 0x90, 0xF0, 0xFE, 0x54, ++ 0x44, 0xE0, 0x33, 0x08, 0x08, 0x90, 0xF0, 0x01, 0x01, 0x44, 0xE0, 0x3A, 0x3B, 0x08, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0x08, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, ++ 0xE0, 0x3C, 0x08, 0x90, 0xE0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0x90, 0xF0, 0xFD, 0x54, ++ 0x44, 0xE0, 0x3D, 0x08, 0x44, 0xE0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x54, 0xE0, 0xF0, 0x08, ++ 0x08, 0x90, 0xF0, 0xFD, 0x01, 0x44, 0xE0, 0x38, 0x02, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xF0, ++ 0xFB, 0x54, 0xE0, 0xF0, 0x49, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, ++ 0xF0, 0xFB, 0x54, 0xE0, 0xF0, 0xF7, 0x54, 0xE0, 0x74, 0x4A, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x0F, ++ 0x08, 0x90, 0xF0, 0x4B, 0xFC, 0x54, 0xE0, 0x50, 0xE0, 0xF0, 0x01, 0x44, 0x10, 0x44, 0xC3, 0x54, ++ 0x52, 0x08, 0x90, 0xF0, 0xF0, 0x03, 0x44, 0xE0, 0xF0, 0xF3, 0x54, 0xE0, 0xE0, 0x49, 0x08, 0x90, ++ 0x90, 0xF0, 0xFD, 0x54, 0x44, 0xE0, 0x75, 0x07, 0x07, 0x90, 0xF0, 0x01, 0xF8, 0x54, 0xE0, 0x76, ++ 0x90, 0xF0, 0x03, 0x44, 0x01, 0x74, 0x99, 0x07, 0x8E, 0x07, 0x90, 0xF0, 0x8F, 0x07, 0x90, 0xF0, ++ 0x92, 0x07, 0x90, 0xF0, 0x93, 0x07, 0x90, 0xF0, 0x96, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, ++ 0xF0, 0x02, 0x44, 0xE0, 0xE0, 0x97, 0x07, 0x90, 0xE0, 0xF0, 0x01, 0x44, 0x90, 0xF0, 0x02, 0x44, ++ 0xFF, 0x74, 0x9E, 0x07, 0x00, 0x22, 0x22, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x61, 0x4D, 0x16, 0x41, 0x00, 0x0A, 0x6E, 0x69, 0x74, 0x69, 0x6E, 0x49, 0x63, 0x41, 0x00, 0x0A, ++ 0x01, 0x00, 0x0A, 0x74, 0x4F, 0x4E, 0x09, 0x09, 0x54, 0x41, 0x4D, 0x2D, 0x00, 0x0A, 0x48, 0x43, ++ 0x7B, 0x10, 0x08, 0x30, 0x79, 0x20, 0x7A, 0xFF, 0xF8, 0x03, 0x12, 0x0E, 0x54, 0xEF, 0x20, 0xAF, ++ 0xAF, 0x20, 0xF5, 0xDF, 0xE0, 0x30, 0xEF, 0x20, 0xAF, 0xE6, 0x21, 0x02, 0x13, 0xC3, 0xEF, 0x20, ++ 0x75, 0x07, 0xE0, 0x30, 0x5E, 0x75, 0x02, 0x5D, 0x20, 0xAF, 0x22, 0x79, 0x0F, 0x54, 0xC4, 0xEF, ++ 0x90, 0x2D, 0xE0, 0x30, 0xC4, 0xE0, 0x12, 0x06, 0xFF, 0x07, 0x54, 0x13, 0x75, 0x07, 0x07, 0xBF, ++ 0x5E, 0x75, 0x02, 0x5D, 0x06, 0x90, 0x22, 0x42, 0x13, 0xC4, 0xE0, 0x12, 0xBF, 0xFF, 0x07, 0x54, ++ 0x5D, 0x75, 0x07, 0x06, 0x4C, 0x5E, 0x75, 0x02, 0x02, 0x5D, 0x75, 0x22, 0x22, 0x47, 0x5E, 0x75, ++ 0xE0, 0x02, 0x06, 0x90, 0x78, 0xE0, 0xA3, 0xFE, 0x13, 0xC3, 0xCE, 0x05, 0xF9, 0xD8, 0x13, 0xCE, ++ 0x90, 0x0A, 0xE0, 0x30, 0xC4, 0xE0, 0x00, 0x06, 0xE0, 0x20, 0x0F, 0x54, 0x00, 0x06, 0x90, 0x18, ++ 0x0F, 0x54, 0xC4, 0xE0, 0x90, 0x0E, 0xE0, 0x30, 0xFF, 0xE0, 0x2F, 0x06, 0x64, 0x03, 0x54, 0xC4, ++ 0x21, 0x02, 0x60, 0x01, 0x00, 0x06, 0x90, 0xED, 0x0F, 0x54, 0xC4, 0xE0, 0x21, 0x02, 0xE0, 0x30, ++ 0xA3, 0xFE, 0xE0, 0x40, 0xCE, 0x06, 0x78, 0xE0, 0x13, 0xCE, 0x13, 0xC3, 0x01, 0x54, 0xF9, 0xD8, ++ 0x90, 0xFD, 0xE0, 0x25, 0xC4, 0xE0, 0x00, 0x06, 0x4D, 0x01, 0x54, 0x13, 0x31, 0x06, 0x90, 0xFD, ++ 0x6D, 0x03, 0x54, 0xE0, 0x06, 0x90, 0x07, 0x60, 0x02, 0x44, 0xE0, 0x35, 0xED, 0x05, 0xAF, 0xF0, ++ 0x90, 0xFF, 0x03, 0x54, 0x54, 0xE0, 0x31, 0x06, 0x90, 0xF0, 0x4F, 0xFC, 0x54, 0xE0, 0x00, 0x06, ++ 0x06, 0x90, 0xFF, 0x01, 0x13, 0xFE, 0xE0, 0x31, 0x01, 0x54, 0x13, 0x13, 0x90, 0x07, 0x60, 0x6F, ++ 0x44, 0xE0, 0x35, 0x06, 0x06, 0x90, 0xF0, 0x04, 0x01, 0x54, 0xE0, 0x00, 0x54, 0x33, 0x33, 0x33, ++ 0x06, 0x90, 0xFF, 0xF8, 0xF7, 0x54, 0xE0, 0x31, 0x06, 0x90, 0xF0, 0x4F, 0x54, 0xC4, 0xE0, 0x2F, ++ 0x70, 0x01, 0x64, 0x03, 0x31, 0x06, 0x90, 0x29, 0x44, 0x3F, 0x54, 0xE0, 0x1E, 0x80, 0xF0, 0x40, ++ 0xE0, 0x2F, 0x06, 0x90, 0xFF, 0x03, 0x54, 0xC4, 0x90, 0x13, 0x01, 0xBF, 0x54, 0xE0, 0x31, 0x06, ++ 0xF0, 0x40, 0x44, 0x3F, 0x44, 0xFC, 0x54, 0xE0, 0x44, 0xE0, 0xF0, 0x02, 0x07, 0x90, 0xF0, 0x08, ++ 0x01, 0x44, 0xE0, 0x75, 0x31, 0x06, 0x90, 0xF0, 0xFF, 0x03, 0x54, 0xE0, 0xE0, 0x76, 0x07, 0x90, ++ 0xF0, 0x4F, 0xF8, 0x54, 0xE0, 0x31, 0x06, 0x90, 0x90, 0xFF, 0x08, 0x54, 0x54, 0xE0, 0x76, 0x07, ++ 0x90, 0xF0, 0x4F, 0xF7, 0xFF, 0xE0, 0x31, 0x06, 0x54, 0x13, 0x13, 0xC4, 0x70, 0x01, 0x64, 0x03, ++ 0x03, 0x54, 0xE0, 0x15, 0x0C, 0x02, 0xBF, 0xFF, 0x02, 0x12, 0x0C, 0xD2, 0x02, 0x5D, 0x75, 0x0B, ++ 0x22, 0x74, 0x5E, 0x75, 0x06, 0x90, 0x40, 0x80, 0x03, 0x54, 0xE0, 0x31, 0x60, 0x14, 0x2C, 0x60, ++ 0x32, 0x70, 0x14, 0x0F, 0x02, 0x12, 0x0C, 0xD2, 0x02, 0x5D, 0x75, 0x0B, 0x22, 0x5B, 0x5E, 0x75, ++ 0x02, 0x12, 0x0C, 0xD2, 0x17, 0x06, 0x90, 0x0B, 0x07, 0x01, 0xB4, 0xE0, 0x75, 0x02, 0x5D, 0x75, ++ 0x75, 0x22, 0x3D, 0x5E, 0x5E, 0x75, 0x02, 0x5D, 0x0C, 0xD2, 0x22, 0x56, 0x75, 0x0B, 0x02, 0x12, ++ 0x5E, 0x75, 0x02, 0x5D, 0x5B, 0x75, 0x22, 0x51, 0xFE, 0x5C, 0x75, 0x21, 0x00, 0x06, 0x90, 0x22, ++ 0x0F, 0x54, 0xC4, 0xE0, 0x75, 0x06, 0xE0, 0x30, 0x5E, 0x75, 0x01, 0x5D, 0x90, 0xE4, 0x22, 0xCF, ++ 0x7B, 0xF0, 0xAC, 0x01, 0x79, 0x20, 0x7A, 0xFF, 0xF8, 0x03, 0x12, 0x08, 0x75, 0xB6, 0x01, 0x12, ++ 0x5C, 0x75, 0x20, 0x5B, 0x71, 0xE5, 0x22, 0x20, 0xFF, 0x7B, 0x11, 0x60, 0x02, 0x79, 0x20, 0x7A, ++ 0x75, 0xF8, 0x03, 0x12, 0x5C, 0x75, 0x21, 0x5B, 0xE5, 0x08, 0xD2, 0xFE, 0x70, 0x5C, 0x65, 0x60, ++ 0x65, 0x5F, 0xE5, 0x04, 0x85, 0x08, 0x60, 0x5B, 0x5C, 0x85, 0x5F, 0x5B, 0xAA, 0x08, 0xD2, 0x60, ++ 0x12, 0x60, 0xA9, 0x5F, 0x08, 0xC2, 0xFF, 0x02, 0xEF, 0x61, 0xAF, 0x22, 0x61, 0xF5, 0xFE, 0x54, ++ 0x75, 0x02, 0x5B, 0x75, 0x90, 0xE4, 0x38, 0x5C, 0xA3, 0xF0, 0x30, 0x06, 0x09, 0x06, 0x90, 0xF0, ++ 0x64, 0x1F, 0x54, 0xE0, 0x61, 0x02, 0x60, 0x01, 0x0B, 0x06, 0x90, 0xD8, 0x64, 0x1F, 0x54, 0xE0, ++ 0x61, 0x02, 0x60, 0x01, 0x0A, 0x06, 0x90, 0xD8, 0xE0, 0xA3, 0xFE, 0xE0, 0x08, 0x06, 0x90, 0xFF, ++ 0x6C, 0xF5, 0x5E, 0xE0, 0xF5, 0x5F, 0xE0, 0xA3, 0x12, 0x06, 0x90, 0x6D, 0x30, 0x13, 0xC3, 0xE0, ++ 0x06, 0x90, 0x0C, 0xE0, 0x13, 0x13, 0xE0, 0x14, 0x20, 0x1F, 0x54, 0x13, 0x06, 0x90, 0x12, 0xE0, ++ 0xE0, 0x30, 0xE0, 0x12, 0x14, 0x06, 0x90, 0x67, 0x54, 0x13, 0x13, 0xE0, 0x5C, 0xE0, 0x30, 0x3F, ++ 0xE0, 0x31, 0x06, 0x90, 0x02, 0x44, 0xFC, 0x54, 0x12, 0x06, 0x90, 0xF0, 0x30, 0x13, 0xC3, 0xE0, ++ 0x06, 0x90, 0x15, 0xE0, 0x13, 0x13, 0xE0, 0x14, 0x30, 0x1F, 0x54, 0x13, 0x06, 0x90, 0x09, 0xE0, ++ 0x08, 0x44, 0xE0, 0x31, 0x90, 0x07, 0x80, 0xF0, 0x54, 0xE0, 0x31, 0x06, 0x01, 0x90, 0xF0, 0xF7, ++ 0x13, 0xFF, 0xE0, 0xB0, 0x30, 0x3F, 0x54, 0x13, 0x01, 0x90, 0x13, 0xE0, 0x13, 0xFF, 0xE0, 0xB8, ++ 0x30, 0x3F, 0x54, 0x13, 0x06, 0x90, 0x07, 0xE0, 0x04, 0x44, 0xE0, 0x31, 0x40, 0xFC, 0x71, 0xF0, ++ 0xAF, 0x8D, 0x61, 0x02, 0x01, 0x44, 0xEF, 0x61, 0x8D, 0x61, 0x61, 0xF5, 0xA1, 0x00, 0x90, 0xE4, ++ 0xEF, 0x6C, 0xAF, 0xF0, 0x90, 0x0A, 0xE0, 0x30, 0x54, 0xE0, 0x31, 0x06, 0x80, 0x01, 0x44, 0xFC, ++ 0xEF, 0x6D, 0xAF, 0x27, 0x13, 0x13, 0x13, 0xC4, 0xE0, 0x30, 0x01, 0x54, 0x31, 0x06, 0x90, 0x0A, ++ 0x44, 0xFC, 0x54, 0xE0, 0xAF, 0x28, 0x80, 0x01, 0x13, 0xC4, 0xEF, 0x6D, 0x30, 0x03, 0x54, 0x13, ++ 0x06, 0x90, 0x0D, 0xE0, 0xFC, 0x54, 0xE0, 0x31, 0x08, 0x44, 0xE0, 0xF0, 0xAF, 0x1E, 0x80, 0xF0, ++ 0x13, 0xC4, 0xEF, 0x6D, 0xE0, 0x30, 0x07, 0x54, 0x31, 0x06, 0x90, 0x0D, 0xF0, 0xFC, 0x54, 0xE0, ++ 0xF0, 0xF7, 0x54, 0xE0, 0x61, 0xAF, 0x07, 0x80, 0xF5, 0x01, 0x44, 0xEF, 0xB0, 0x01, 0x90, 0x61, ++ 0x30, 0x13, 0xC3, 0xE0, 0x01, 0x90, 0x17, 0xE0, 0x13, 0xC3, 0xE0, 0xB8, 0x90, 0x0E, 0xE0, 0x30, ++ 0x54, 0xE0, 0x31, 0x06, 0x01, 0xBF, 0xFF, 0x03, 0x04, 0x44, 0xE0, 0x04, 0xEF, 0x6C, 0xAF, 0xF0, ++ 0x3F, 0x54, 0x13, 0x13, 0x90, 0x09, 0xE0, 0x30, 0x44, 0xE0, 0x31, 0x06, 0x3F, 0x80, 0xF0, 0x30, ++ 0x13, 0xEF, 0x6C, 0xAF, 0x1F, 0x54, 0x13, 0x13, 0x90, 0x24, 0xE0, 0x30, 0x30, 0xE0, 0x08, 0x06, ++ 0x06, 0x90, 0x0B, 0xE2, 0xCF, 0x54, 0xE0, 0x31, 0x80, 0xF0, 0x20, 0x44, 0x0A, 0x06, 0x90, 0x22, ++ 0x31, 0x06, 0x90, 0xE0, 0xE0, 0x0B, 0xE2, 0x30, 0x10, 0x44, 0xCF, 0x54, 0x90, 0x10, 0x80, 0xF0, ++ 0x54, 0xE0, 0x31, 0x06, 0x07, 0x80, 0xF0, 0xCF, 0x44, 0xEF, 0x61, 0xAF, 0xAF, 0x61, 0xF5, 0x01, ++ 0xE0, 0x30, 0xEF, 0x61, 0x7A, 0xFF, 0x7B, 0x16, 0x12, 0x14, 0x79, 0x20, 0x5B, 0x75, 0xF8, 0x03, ++ 0x33, 0x5C, 0x75, 0x02, 0xE0, 0x34, 0x06, 0x90, 0x22, 0xF0, 0x08, 0x44, 0x0C, 0xC2, 0x01, 0x7E, ++ 0xE0, 0x26, 0x06, 0x90, 0x07, 0x54, 0x13, 0xC4, 0x09, 0x04, 0xBD, 0xFD, 0xE0, 0x14, 0x06, 0x90, ++ 0xC3, 0xF0, 0x40, 0x44, 0x12, 0x06, 0x90, 0x22, 0x0F, 0x54, 0xC4, 0xE0, 0xE0, 0x0B, 0xE0, 0x30, ++ 0x54, 0x13, 0x13, 0x13, 0xF9, 0x02, 0x24, 0x01, 0x06, 0x90, 0x09, 0x80, 0x13, 0x13, 0xE0, 0x12, ++ 0x78, 0xF9, 0x01, 0x54, 0xE0, 0x30, 0xE6, 0x89, 0x13, 0xC3, 0xE6, 0x0A, 0x02, 0x24, 0x01, 0x54, ++ 0x78, 0x08, 0x80, 0xFC, 0x13, 0x13, 0xE6, 0x89, 0xE9, 0xFC, 0x01, 0x54, 0x0C, 0x60, 0xFD, 0x24, ++ 0xE4, 0x1B, 0x70, 0x04, 0x02, 0x64, 0xEC, 0xFE, 0x07, 0x80, 0x6A, 0x70, 0x64, 0xEC, 0x01, 0x7E, ++ 0x90, 0x61, 0x70, 0x03, 0x44, 0xE0, 0x14, 0x06, 0x0C, 0xD2, 0xF0, 0x80, 0x6C, 0xE9, 0x56, 0x80, ++ 0x83, 0x78, 0x3D, 0x70, 0xE6, 0x08, 0xFA, 0xE6, 0x70, 0x66, 0x86, 0x78, 0x66, 0x18, 0xEA, 0x03, ++ 0x0C, 0xD2, 0x16, 0x70, 0xE6, 0x06, 0x80, 0x78, 0x40, 0x07, 0x94, 0xC3, 0x14, 0x06, 0x90, 0x37, ++ 0xF0, 0x80, 0x44, 0xE0, 0x2C, 0x80, 0x07, 0x76, 0xFA, 0xE6, 0x83, 0x78, 0x78, 0xD3, 0xE6, 0x08, ++ 0x18, 0xEA, 0x96, 0x86, 0x40, 0x00, 0x7F, 0x96, 0xAE, 0x01, 0x7F, 0x02, 0xEC, 0x15, 0x80, 0x07, ++ 0x40, 0x02, 0x94, 0xC3, 0x9C, 0x03, 0x74, 0x06, 0x7F, 0x09, 0x80, 0xFE, 0x02, 0x01, 0xB9, 0x00, ++ 0x07, 0xAE, 0x01, 0x7F, 0xC4, 0x01, 0x54, 0xEE, 0xC0, 0x54, 0x33, 0x33, 0x14, 0x06, 0x90, 0xFF, ++ 0x4F, 0xBF, 0x54, 0xE0, 0x07, 0x0C, 0x30, 0xF0, 0xE0, 0x34, 0x06, 0x90, 0xA2, 0xF0, 0x40, 0x44, ++ 0x00, 0x22, 0x22, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x09, 0x09, 0x2E, 0x21, 0x58, 0x52, 0x09, 0x09, 0x0A, 0x78, 0x25, 0x3A, 0x09, 0x09, 0x09, 0x00, ++ 0x64, 0x25, 0x58, 0x54, 0x78, 0x25, 0x00, 0x3A, 0x54, 0x09, 0x00, 0x0A, 0x73, 0x69, 0x44, 0x78, ++ 0x41, 0x09, 0x00, 0x0A, 0x2D, 0x6C, 0x69, 0x62, 0x09, 0x00, 0x0A, 0x44, 0x43, 0x2D, 0x53, 0x4C, ++ 0x00, 0x0A, 0x6B, 0x68, 0x44, 0x50, 0x09, 0x09, 0x75, 0x61, 0x46, 0x2D, 0x00, 0x0A, 0x74, 0x6C, ++ 0x4B, 0x43, 0x41, 0x09, 0x00, 0x0A, 0x44, 0x2D, 0x41, 0x2D, 0x43, 0x09, 0x00, 0x0A, 0x4B, 0x43, ++ 0x58, 0x52, 0x09, 0x09, 0x3D, 0x4D, 0x53, 0x46, 0x00, 0x0A, 0x64, 0x25, 0x2D, 0x50, 0x4E, 0x09, ++ 0x74, 0x69, 0x61, 0x57, 0x09, 0x09, 0x00, 0x0A, 0x53, 0x46, 0x58, 0x54, 0x64, 0x25, 0x3D, 0x4D, ++ 0x41, 0x09, 0x00, 0x0A, 0x0A, 0x73, 0x65, 0x52, 0x2D, 0x09, 0x09, 0x00, 0x30, 0x31, 0x20, 0x3E, ++ 0x78, 0x00, 0x30, 0x00, 0x2D, 0x00, 0x73, 0x00, 0x2D, 0x00, 0x44, 0x46, 0x2F, 0x00, 0x44, 0x48, ++ 0x53, 0x2F, 0x00, 0x4D, 0x45, 0x45, 0x2F, 0x00, 0x50, 0x2D, 0x00, 0x45, 0x64, 0x25, 0x3A, 0x53, ++ 0x01, 0x02, 0x00, 0x0A, 0x02, 0x5B, 0x75, 0xBB, 0x90, 0x33, 0x5C, 0x75, 0x54, 0xE0, 0x0D, 0x06, ++ 0x20, 0xAF, 0xF0, 0xEF, 0xF5, 0xFB, 0x54, 0xEF, 0x00, 0x06, 0x90, 0x20, 0xF0, 0xFD, 0x54, 0xE0, ++ 0xE0, 0xAD, 0x01, 0x90, 0x11, 0xF0, 0x04, 0x44, 0xF0, 0x07, 0x90, 0xA2, 0xE4, 0xF0, 0x01, 0x74, ++ 0x90, 0xF6, 0x80, 0x78, 0xFF, 0xE0, 0x8A, 0x0D, 0xE0, 0x8B, 0x0D, 0x90, 0x07, 0x90, 0xFF, 0x6F, ++ 0xE4, 0xFD, 0xE0, 0x0B, 0xEF, 0xF6, 0x7E, 0x78, 0x90, 0xF6, 0x08, 0x6D, 0x61, 0x74, 0x4B, 0x07, ++ 0x4C, 0x07, 0x90, 0xF0, 0xE4, 0xF0, 0xA8, 0x74, 0x8D, 0x03, 0x12, 0xFF, 0x00, 0x00, 0x90, 0xE4, ++ 0x2F, 0x06, 0x90, 0xF0, 0x03, 0x54, 0xC4, 0xE0, 0x21, 0x03, 0xBF, 0xFF, 0xE0, 0x08, 0x06, 0x90, ++ 0xA3, 0xFE, 0xE0, 0x54, 0xFF, 0x1F, 0x54, 0xE0, 0x90, 0x0C, 0x44, 0xEE, 0xA3, 0xF0, 0x08, 0x06, ++ 0x06, 0x90, 0xF0, 0xEF, 0x02, 0x44, 0xE0, 0x12, 0x01, 0x44, 0xE0, 0xF0, 0x71, 0xE5, 0x22, 0xF0, ++ 0x17, 0x75, 0x28, 0x60, 0x9A, 0x18, 0x75, 0x07, 0x75, 0x07, 0x15, 0x75, 0x78, 0xE4, 0x9C, 0x16, ++ 0xF6, 0x08, 0xF6, 0x7A, 0xF6, 0x08, 0xF6, 0x08, 0x08, 0xD2, 0xA5, 0x11, 0x54, 0xEF, 0x62, 0xAF, ++ 0xAF, 0x62, 0xF5, 0xFD, 0xFE, 0x54, 0xEF, 0x62, 0x20, 0xAF, 0x62, 0xF5, 0x0F, 0x54, 0xC4, 0xEF, ++ 0xAF, 0x23, 0xE0, 0x20, 0xE0, 0x20, 0xEF, 0x20, 0xEF, 0x20, 0xAF, 0x1D, 0xE0, 0x20, 0x13, 0xC3, ++ 0xEF, 0x20, 0xAF, 0x15, 0x3F, 0x54, 0x13, 0x13, 0x90, 0x0B, 0xE0, 0x20, 0xFF, 0xE0, 0x00, 0x06, ++ 0x20, 0x0F, 0x54, 0xC4, 0x2E, 0x7E, 0x12, 0xE0, 0x65, 0xEF, 0x50, 0x7F, 0xEE, 0x03, 0x70, 0x5C, ++ 0x04, 0x60, 0x5B, 0x65, 0x5C, 0x8F, 0x5B, 0x8E, 0x62, 0xAF, 0x3A, 0x71, 0xF5, 0xFD, 0x54, 0xEF, ++ 0x9E, 0x07, 0x90, 0x62, 0x21, 0xE1, 0x30, 0xE0, 0x20, 0x7A, 0xFF, 0x7B, 0x16, 0x85, 0x02, 0x79, ++ 0x83, 0x15, 0x85, 0x82, 0xE0, 0xA3, 0xFC, 0xE0, 0xE5, 0x0C, 0x12, 0xFD, 0x44, 0xEF, 0x62, 0xAF, ++ 0x90, 0x62, 0xF5, 0x02, 0x02, 0x74, 0x9E, 0x07, 0x65, 0x60, 0xE5, 0xF0, 0xE5, 0x04, 0x70, 0x5C, ++ 0x60, 0x5B, 0x65, 0x5F, 0x5F, 0x5B, 0x85, 0x08, 0xD2, 0x60, 0x5C, 0x85, 0xA9, 0x5F, 0xAA, 0x08, ++ 0xFF, 0x02, 0x12, 0x60, 0x62, 0xAF, 0x08, 0xC2, 0xF5, 0xFE, 0x54, 0xEF, 0x9E, 0x07, 0x90, 0x62, ++ 0x36, 0xE3, 0x30, 0xE0, 0x20, 0x7A, 0xFF, 0x7B, 0x06, 0x90, 0x0D, 0x79, 0x13, 0xFF, 0xE0, 0x23, ++ 0xFD, 0x01, 0x54, 0x13, 0x0C, 0x12, 0x00, 0x7C, 0x7A, 0xFF, 0x7B, 0xE5, 0x85, 0x16, 0x79, 0x20, ++ 0x17, 0x85, 0x82, 0x18, 0xA3, 0xFC, 0xE0, 0x83, 0x0C, 0x12, 0xFD, 0xE0, 0xEF, 0x62, 0xAF, 0xE5, ++ 0x62, 0xF5, 0x01, 0x44, 0x74, 0x9E, 0x07, 0x90, 0x08, 0x90, 0xF0, 0x08, 0x13, 0x13, 0xE0, 0x54, ++ 0x30, 0x1F, 0x54, 0x13, 0x81, 0x78, 0x14, 0xE0, 0x09, 0x0A, 0xB4, 0xE6, 0x44, 0xEF, 0x61, 0xAF, ++ 0x80, 0x61, 0xF5, 0x02, 0x06, 0x81, 0x78, 0x16, 0x81, 0x78, 0x11, 0x80, 0xAF, 0x09, 0x70, 0xE6, ++ 0xFD, 0x54, 0xEF, 0x61, 0x03, 0x80, 0x61, 0xF5, 0x90, 0x16, 0x81, 0x78, 0x54, 0xE0, 0xA0, 0x07, ++ 0xF6, 0x82, 0x78, 0x07, 0x0B, 0x12, 0x7C, 0x7F, 0x78, 0x07, 0x40, 0xB2, 0x01, 0x64, 0xE6, 0x82, ++ 0x61, 0xAF, 0x07, 0x60, 0xF5, 0xFB, 0x54, 0xEF, 0x9E, 0x07, 0x90, 0x61, 0x26, 0xE0, 0x30, 0xE0, ++ 0xE6, 0x7D, 0x78, 0xD3, 0xE6, 0x18, 0x00, 0x94, 0x0D, 0x40, 0x00, 0x94, 0xB4, 0xE6, 0x82, 0x78, ++ 0x61, 0xAF, 0x07, 0x01, 0xF5, 0x04, 0x44, 0xEF, 0x76, 0x7C, 0x78, 0x61, 0xFA, 0x76, 0x08, 0x00, ++ 0x74, 0x9E, 0x07, 0x90, 0x08, 0x90, 0xF0, 0x01, 0xF0, 0x08, 0x74, 0x54, 0x7F, 0xE6, 0x82, 0x78, ++ 0x02, 0x02, 0xB4, 0x00, 0x54, 0xEF, 0x01, 0x7F, 0x33, 0x33, 0x33, 0x01, 0xAE, 0xFF, 0xF8, 0x54, ++ 0xF7, 0x54, 0xEE, 0x61, 0xAF, 0x61, 0xF5, 0x4F, 0x13, 0x13, 0xEF, 0x61, 0xFF, 0x01, 0x54, 0x13, ++ 0x13, 0xEE, 0x61, 0xAE, 0x4F, 0x01, 0x54, 0x13, 0xEE, 0x61, 0xAE, 0xFF, 0x01, 0x54, 0x13, 0xC3, ++ 0xFF, 0x01, 0x54, 0x4F, 0x54, 0xEE, 0x61, 0xAE, 0x61, 0xF5, 0x4F, 0xFE, 0x30, 0xEF, 0x62, 0xAF, ++ 0x06, 0x90, 0x32, 0xE0, 0x13, 0xC3, 0xE0, 0x29, 0x90, 0x29, 0xE0, 0x30, 0x54, 0xE0, 0xFE, 0x07, ++ 0x08, 0x90, 0xF0, 0xFD, 0xFE, 0x54, 0xE0, 0x3D, 0x99, 0x07, 0x90, 0xF0, 0xFF, 0x1F, 0x54, 0xE0, ++ 0x00, 0x7C, 0x00, 0x7E, 0x02, 0x12, 0x0A, 0x7D, 0x39, 0x24, 0xEF, 0x98, 0xE4, 0xF6, 0x7B, 0x78, ++ 0x22, 0xF6, 0x18, 0x3E, 0x0B, 0x12, 0x7A, 0x7F, 0x90, 0x0E, 0x50, 0xB2, 0x44, 0xE0, 0xFE, 0x07, ++ 0x08, 0x90, 0xF0, 0x02, 0x01, 0x44, 0xE0, 0x3D, 0x7F, 0x78, 0x22, 0xF0, 0xFF, 0x01, 0x54, 0xE6, ++ 0x74, 0x9F, 0xE4, 0xC3, 0x54, 0x00, 0x94, 0x08, 0xE6, 0x18, 0xFC, 0x05, 0x08, 0xFE, 0x13, 0xC3, ++ 0xEE, 0xFF, 0x13, 0xE6, 0xEF, 0xF6, 0x18, 0x6C, 0x7B, 0x22, 0xF6, 0x08, 0x79, 0x20, 0x7A, 0xFF, ++ 0xF8, 0x03, 0x12, 0x72, 0x30, 0x2E, 0x02, 0x02, 0xFF, 0x7B, 0x34, 0x08, 0x1A, 0x79, 0x20, 0x7A, ++ 0x78, 0xF8, 0x03, 0x12, 0x08, 0x34, 0x76, 0x72, 0x06, 0x90, 0xBC, 0x76, 0x13, 0xFF, 0xE0, 0x23, ++ 0x13, 0x3F, 0x54, 0x13, 0x0D, 0xD2, 0x0C, 0x92, 0x07, 0x90, 0xDB, 0xD1, 0xF0, 0x03, 0x74, 0x97, ++ 0xE0, 0x03, 0x06, 0x90, 0xAF, 0xF0, 0xDF, 0x54, 0xF7, 0x54, 0xEF, 0x20, 0x72, 0x7F, 0x20, 0xF5, ++ 0x50, 0xB2, 0x0B, 0x12, 0x23, 0x5B, 0x75, 0x06, 0x22, 0xAC, 0x5C, 0x75, 0x81, 0x02, 0x08, 0x20, ++ 0x7A, 0xFF, 0x7B, 0xBF, 0x12, 0x22, 0x79, 0x20, 0x78, 0xE4, 0xF8, 0x03, 0x72, 0x78, 0xF6, 0x87, ++ 0x9B, 0x76, 0x08, 0xF6, 0x08, 0x2A, 0x76, 0x08, 0x78, 0x78, 0xC8, 0x76, 0x76, 0x08, 0xFD, 0x76, ++ 0xF5, 0x69, 0xF5, 0xE8, 0x76, 0x76, 0x78, 0x6A, 0x6C, 0x76, 0x08, 0x02, 0xF5, 0x01, 0x64, 0x75, ++ 0x90, 0x66, 0xF5, 0x65, 0xFF, 0xE0, 0x08, 0x06, 0x18, 0x85, 0xE0, 0xA3, 0x83, 0x17, 0x85, 0x82, ++ 0xEF, 0xA3, 0xF0, 0xCF, 0x82, 0x18, 0x85, 0xF0, 0xC0, 0x83, 0x17, 0x85, 0xE0, 0x82, 0xC0, 0x83, ++ 0xB0, 0x01, 0x90, 0xFF, 0x54, 0x13, 0xC3, 0xE0, 0xC4, 0xEF, 0xFE, 0x01, 0x54, 0x13, 0x13, 0x13, ++ 0x54, 0xEF, 0xFD, 0x01, 0x4E, 0xED, 0xFF, 0x7F, 0x33, 0xC4, 0x01, 0x54, 0x80, 0x54, 0x33, 0x33, ++ 0xD0, 0x82, 0xD0, 0x4F, 0x18, 0x85, 0xF0, 0x83, 0x83, 0x17, 0x85, 0x82, 0x82, 0xC0, 0x83, 0xC0, ++ 0x06, 0x90, 0xFF, 0xE0, 0x13, 0xC4, 0xE0, 0x28, 0xFE, 0x03, 0x54, 0x13, 0xE0, 0xA1, 0x00, 0x90, ++ 0x7E, 0x9E, 0xC3, 0xFD, 0x7E, 0x02, 0x50, 0x00, 0x00, 0x7D, 0xED, 0x01, 0x01, 0x7D, 0x02, 0x70, ++ 0x90, 0xFE, 0x4D, 0xEE, 0xC3, 0xE0, 0x12, 0x06, 0xFD, 0x01, 0x54, 0x13, 0x4D, 0x01, 0x54, 0xE0, ++ 0xC4, 0xEF, 0xFE, 0x5E, 0x54, 0x13, 0x13, 0x13, 0x54, 0xEF, 0xFD, 0x01, 0x4E, 0xED, 0xFF, 0x7F, ++ 0x33, 0xC4, 0x01, 0x54, 0x80, 0x54, 0x33, 0x33, 0xD0, 0x82, 0xD0, 0x4F, 0x18, 0x85, 0xF0, 0x83, ++ 0x83, 0x17, 0x85, 0x82, 0xC4, 0x08, 0x54, 0xE0, 0xAE, 0xFF, 0xF0, 0x54, 0x7F, 0x54, 0xEE, 0x61, ++ 0xE4, 0x61, 0xF5, 0x4F, 0xF0, 0x0A, 0x06, 0x90, 0x06, 0x90, 0xF0, 0xA3, 0xFE, 0x54, 0xE0, 0x0D, ++ 0xF7, 0x54, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xF0, 0x06, 0x90, 0xE4, 0xF0, 0xF0, 0xA3, 0xF0, 0x14, ++ 0xF0, 0xB7, 0x01, 0x90, 0x07, 0x90, 0xF0, 0xA3, 0x06, 0x90, 0xF0, 0x97, 0xAF, 0xD0, 0xD1, 0x23, ++ 0x13, 0xC3, 0xEF, 0x61, 0xAF, 0x0A, 0xE0, 0x20, 0x13, 0x13, 0xEF, 0x61, 0xE0, 0x30, 0x3F, 0x54, ++ 0x12, 0x72, 0x7F, 0x27, 0x27, 0x50, 0xB2, 0x0B, 0x02, 0x76, 0x76, 0x78, 0xAF, 0x6C, 0x76, 0x08, ++ 0x02, 0x54, 0xEF, 0x61, 0xFF, 0xF0, 0x54, 0xC4, 0x54, 0xEE, 0x61, 0xAE, 0x61, 0xF5, 0x4F, 0xDF, ++ 0x75, 0x27, 0x5B, 0x75, 0x07, 0x80, 0xCF, 0x5C, 0x01, 0x76, 0x72, 0x78, 0x90, 0x36, 0x76, 0x08, ++ 0x54, 0xE0, 0xA0, 0x07, 0x60, 0x02, 0x64, 0x07, 0x87, 0x78, 0xE4, 0x0A, 0xF5, 0x69, 0xF5, 0xF6, ++ 0xAF, 0x4D, 0x80, 0x6A, 0x13, 0xC3, 0xEF, 0x62, 0x85, 0x45, 0xE0, 0x30, 0x15, 0x85, 0x82, 0x16, ++ 0x40, 0x54, 0xE0, 0x83, 0xEE, 0x69, 0xAE, 0xFF, 0xF5, 0x4F, 0xBF, 0x54, 0x82, 0x16, 0x85, 0x69, ++ 0xE0, 0x83, 0x15, 0x85, 0xB5, 0xE0, 0xA3, 0xFE, 0xB5, 0xEE, 0x15, 0x6A, 0x87, 0x78, 0x11, 0x69, ++ 0x94, 0xC3, 0xE6, 0x06, 0x75, 0x19, 0x40, 0x02, 0x5C, 0x75, 0x28, 0x5B, 0x85, 0x11, 0x80, 0x8D, ++ 0x15, 0x85, 0x82, 0x16, 0x69, 0xF5, 0xE0, 0x83, 0x6A, 0xF5, 0xE0, 0xA3, 0xF6, 0x87, 0x78, 0xE4, ++ 0xE0, 0x27, 0x06, 0x90, 0xA1, 0x02, 0xE0, 0x20, 0x12, 0x74, 0x7F, 0xEC, 0x09, 0x40, 0xB2, 0x0B, ++ 0x0B, 0x12, 0x76, 0x7F, 0xA1, 0x02, 0x40, 0xB2, 0xEF, 0x62, 0xAF, 0xFF, 0xA1, 0x02, 0xE0, 0x20, ++ 0xEF, 0x61, 0xAF, 0xFF, 0x78, 0x78, 0xE0, 0x20, 0x46, 0x18, 0xE6, 0x75, 0x06, 0x90, 0x34, 0x70, ++ 0x13, 0xFF, 0xE0, 0x23, 0x30, 0x3F, 0x54, 0x13, 0x06, 0x90, 0x07, 0xE0, 0x08, 0x44, 0xE0, 0x35, ++ 0xC2, 0x0C, 0xC2, 0xF0, 0x78, 0xDB, 0xD1, 0x0D, 0x07, 0x54, 0xE6, 0x7E, 0x25, 0xE6, 0x08, 0xFE, ++ 0x33, 0xEE, 0xFF, 0xE0, 0xC8, 0x24, 0xEF, 0xFE, 0xEE, 0xF6, 0x75, 0x78, 0xF6, 0x18, 0x2A, 0x34, ++ 0x7F, 0x78, 0x21, 0x80, 0xFF, 0x01, 0x54, 0xE6, 0xE0, 0x23, 0x06, 0x90, 0x54, 0x13, 0x13, 0xFD, ++ 0x01, 0x70, 0x6F, 0x01, 0x90, 0x07, 0x60, 0xE4, 0x44, 0xE0, 0x35, 0x06, 0x7F, 0x78, 0xF0, 0x08, ++ 0x78, 0xD6, 0xD1, 0xE6, 0x08, 0x02, 0x76, 0x76, 0x13, 0x80, 0x6C, 0x76, 0x02, 0x76, 0x76, 0x78, ++ 0x78, 0x6C, 0x76, 0x08, 0x08, 0x2A, 0x76, 0x74, 0x06, 0x90, 0xC8, 0x76, 0x90, 0xD0, 0xD1, 0x27, ++ 0xC3, 0xE0, 0x29, 0x06, 0x02, 0xE0, 0x20, 0x13, 0x66, 0xE5, 0x91, 0xC1, 0x04, 0x37, 0x60, 0x14, ++ 0x61, 0xAF, 0x79, 0x70, 0x09, 0xE0, 0x30, 0xEF, 0xFD, 0x76, 0x78, 0x78, 0x80, 0xE8, 0x76, 0x08, ++ 0x12, 0x78, 0x7F, 0x25, 0x1E, 0x50, 0xB2, 0x0B, 0x30, 0xEF, 0x62, 0xAF, 0x78, 0x78, 0x18, 0xE0, ++ 0x76, 0x08, 0x19, 0x76, 0x01, 0x0D, 0x90, 0x00, 0xF0, 0x20, 0x44, 0xE0, 0xE0, 0x21, 0x0D, 0x90, ++ 0x75, 0xF0, 0x20, 0x44, 0x61, 0xAF, 0x01, 0x66, 0x1A, 0xE0, 0x30, 0xEF, 0xFD, 0x76, 0x78, 0x78, ++ 0x90, 0xE8, 0x76, 0x08, 0x54, 0xE0, 0x01, 0x0D, 0x0D, 0x90, 0xF0, 0xDF, 0xDF, 0x54, 0xE0, 0x21, ++ 0x66, 0xF5, 0xE4, 0xF0, 0x78, 0x7F, 0x25, 0x80, 0x50, 0xB2, 0x0B, 0x12, 0xEF, 0x62, 0xAF, 0x1E, ++ 0x78, 0x18, 0xE0, 0x30, 0x08, 0x02, 0x76, 0x78, 0x0D, 0x90, 0x80, 0x76, 0xDF, 0x54, 0xE0, 0x01, ++ 0x21, 0x0D, 0x90, 0xF0, 0xF0, 0xDF, 0x54, 0xE0, 0xAF, 0x02, 0x66, 0x75, 0xE0, 0x30, 0xEF, 0x61, ++ 0x76, 0x78, 0x78, 0x19, 0xE8, 0x76, 0x08, 0xFD, 0xE0, 0x01, 0x0D, 0x90, 0x90, 0xF0, 0xDF, 0x54, ++ 0x54, 0xE0, 0x21, 0x0D, 0xF5, 0xE4, 0xF0, 0xDF, 0x78, 0x7F, 0x22, 0x66, 0x50, 0xB2, 0x0B, 0x12, ++ 0xEF, 0x62, 0xAF, 0x1E, 0x78, 0x18, 0xE0, 0x30, 0x08, 0x19, 0x76, 0x78, 0x0D, 0x90, 0x00, 0x76, ++ 0x20, 0x44, 0xE0, 0x01, 0x21, 0x0D, 0x90, 0xF0, 0xF0, 0x20, 0x44, 0xE0, 0x22, 0x01, 0x66, 0x75, ++ 0x13, 0x13, 0xFF, 0xE0, 0x92, 0x13, 0x3F, 0x54, 0x90, 0x0D, 0xC2, 0x0C, 0x30, 0xE0, 0x27, 0x06, ++ 0x0C, 0x30, 0x03, 0xE0, 0x27, 0x06, 0x90, 0x1A, 0x69, 0xE0, 0x20, 0xE0, 0xE0, 0x26, 0x06, 0x90, ++ 0x78, 0xE0, 0xA3, 0xFE, 0x13, 0xC3, 0xCE, 0x02, 0xF9, 0xD8, 0x13, 0xCE, 0xC2, 0x56, 0xE0, 0x20, ++ 0xE4, 0x0D, 0xA2, 0x0C, 0xF0, 0x54, 0xC4, 0x33, 0x90, 0xFF, 0x0F, 0x44, 0xC4, 0xE0, 0x01, 0x0D, ++ 0xC4, 0x01, 0x54, 0x13, 0x4F, 0xE0, 0x54, 0x33, 0x21, 0x0D, 0x90, 0xF0, 0x54, 0x13, 0xC4, 0xE0, ++ 0x54, 0x33, 0xC4, 0x01, 0xF0, 0x10, 0x44, 0xE0, 0xE0, 0x00, 0x0D, 0x90, 0x90, 0xF0, 0x9F, 0x54, ++ 0x54, 0xE0, 0x20, 0x0D, 0xF0, 0x20, 0x44, 0x9F, 0x74, 0x0C, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x15, ++ 0xF0, 0x12, 0x74, 0x2C, 0x74, 0xF1, 0x07, 0x90, 0x07, 0x90, 0xF0, 0xE4, 0xF0, 0xB1, 0x74, 0xF2, ++ 0x80, 0xA2, 0x00, 0x90, 0xA2, 0x0C, 0xD2, 0x54, 0xC4, 0x33, 0xE4, 0x0D, 0x0F, 0x44, 0xF0, 0x54, ++ 0x21, 0x0D, 0x90, 0xFF, 0x54, 0x13, 0xC4, 0xE0, 0x54, 0x33, 0xC4, 0x01, 0x90, 0xF0, 0x4F, 0xE0, ++ 0xC4, 0xE0, 0x01, 0x0D, 0xC4, 0x01, 0x54, 0x13, 0x44, 0xE0, 0x54, 0x33, 0x0D, 0x90, 0xF0, 0x10, ++ 0x9F, 0x54, 0xE0, 0x00, 0x90, 0xF0, 0x20, 0x44, 0x54, 0xE0, 0x20, 0x0D, 0x0D, 0x90, 0xF0, 0x9F, ++ 0xF0, 0x12, 0x74, 0x0C, 0x74, 0x2C, 0x0D, 0x90, 0x07, 0x90, 0xF0, 0x15, 0xF0, 0xB1, 0x74, 0xF1, ++ 0x74, 0xF2, 0x07, 0x90, 0x00, 0x90, 0xF0, 0xE4, 0x08, 0x90, 0xE0, 0xA3, 0x0C, 0xA2, 0xF0, 0x3E, ++ 0x01, 0x54, 0x33, 0xE4, 0x25, 0xE0, 0x25, 0xFC, 0x06, 0x90, 0xFE, 0xE0, 0xFB, 0x54, 0xE0, 0x23, ++ 0x33, 0xEC, 0xF0, 0x4E, 0xF8, 0x54, 0x33, 0x33, 0xF7, 0x54, 0xE0, 0xFF, 0x30, 0x22, 0xF0, 0x4F, ++ 0xFF, 0x7B, 0x2E, 0x08, 0x2B, 0x79, 0x20, 0x7A, 0x90, 0xF8, 0x03, 0x12, 0x44, 0xE0, 0x97, 0x07, ++ 0x06, 0x90, 0xF0, 0x01, 0x13, 0xFF, 0xE0, 0x23, 0x13, 0x3F, 0x54, 0x13, 0x0D, 0xD2, 0x0C, 0x92, ++ 0x72, 0x78, 0xDB, 0xD1, 0x76, 0x08, 0x1D, 0x76, 0x76, 0x78, 0x78, 0x4C, 0xF4, 0x76, 0x08, 0x01, ++ 0xC4, 0xEF, 0x61, 0xAF, 0x30, 0x07, 0x54, 0x13, 0x61, 0xAF, 0x0C, 0xE0, 0x33, 0x02, 0x54, 0xEF, ++ 0xF8, 0x54, 0x33, 0x33, 0x07, 0x90, 0x1D, 0x80, 0x07, 0x54, 0xE0, 0xA0, 0x04, 0x03, 0xBF, 0xFF, ++ 0x02, 0x80, 0x01, 0x7F, 0x61, 0xAE, 0x00, 0x7F, 0x54, 0x13, 0x13, 0xEE, 0x01, 0x54, 0x4F, 0x01, ++ 0xFF, 0xF0, 0x54, 0xC4, 0x54, 0xEE, 0x61, 0xAE, 0x61, 0xF5, 0x4F, 0xEF, 0x0B, 0x12, 0x72, 0x7F, ++ 0xAF, 0x1B, 0x50, 0xB2, 0x13, 0xC4, 0xEF, 0x61, 0x06, 0x90, 0x07, 0x54, 0x05, 0xE0, 0x20, 0x0B, ++ 0x80, 0xF0, 0x21, 0x74, 0xF0, 0x81, 0x74, 0x03, 0x75, 0x23, 0x5B, 0x75, 0x61, 0xAF, 0x5B, 0x5C, ++ 0x0F, 0x54, 0xC4, 0xEF, 0x7F, 0x1E, 0xE0, 0x20, 0xB2, 0x0B, 0x12, 0x78, 0xFF, 0x7B, 0x1E, 0x50, ++ 0x34, 0x79, 0x20, 0x7A, 0x90, 0xF8, 0x03, 0x12, 0x44, 0xE0, 0x0D, 0x06, 0x5B, 0x75, 0xF0, 0x10, ++ 0xAC, 0x5C, 0x75, 0x23, 0x76, 0x78, 0x78, 0x22, 0xF4, 0x76, 0x08, 0x01, 0x25, 0x08, 0x30, 0x22, ++ 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x40, 0x79, 0x0D, 0x06, 0x90, 0xF8, 0xF0, 0x01, 0x44, 0xE0, ++ 0x85, 0x82, 0x18, 0x85, 0x44, 0xE0, 0x83, 0x17, 0x69, 0xAF, 0xF0, 0x40, 0xF5, 0x40, 0x44, 0xEF, ++ 0x87, 0x78, 0xE4, 0x69, 0xA0, 0x07, 0x90, 0xF6, 0x64, 0x07, 0x54, 0xE0, 0x75, 0x06, 0x60, 0x02, ++ 0x5C, 0x75, 0x02, 0x5B, 0xEF, 0x62, 0xAF, 0x33, 0xE0, 0x30, 0x13, 0xC3, 0x82, 0x16, 0x85, 0x4C, ++ 0xE0, 0x83, 0x15, 0x85, 0xB5, 0xE0, 0xA3, 0xFE, 0xB5, 0xEE, 0x14, 0x6A, 0x87, 0x78, 0x10, 0x69, ++ 0x94, 0xD3, 0xE6, 0x06, 0x75, 0x32, 0x40, 0x02, 0x5C, 0x75, 0x29, 0x5B, 0x78, 0xE4, 0x22, 0x1A, ++ 0x69, 0xAF, 0xF6, 0x87, 0xF5, 0xBF, 0x54, 0xEF, 0x82, 0x16, 0x85, 0x69, 0xE0, 0x83, 0x15, 0x85, ++ 0x65, 0xE0, 0xA3, 0xFE, 0xEE, 0x03, 0x70, 0x6A, 0x06, 0x60, 0x69, 0x65, 0x75, 0x02, 0x5B, 0x75, ++ 0x69, 0xAF, 0x33, 0x5C, 0xF5, 0x40, 0x44, 0xEF, 0x08, 0x20, 0x22, 0x69, 0x7B, 0x7F, 0x41, 0x02, ++ 0x79, 0x20, 0x7A, 0xFF, 0xF8, 0x03, 0x12, 0x48, 0x07, 0x76, 0x88, 0x78, 0xFC, 0x24, 0x65, 0xE5, ++ 0xFE, 0x24, 0x0B, 0x60, 0x60, 0x14, 0x07, 0x60, 0x70, 0x06, 0x24, 0x07, 0x07, 0x65, 0x75, 0x33, ++ 0xC4, 0xEF, 0x69, 0xAF, 0x30, 0x07, 0x54, 0x13, 0x69, 0xAE, 0x28, 0xE0, 0x54, 0xEE, 0x6A, 0xAF, ++ 0x64, 0xEF, 0xFE, 0x07, 0x05, 0x70, 0x4E, 0x08, 0x80, 0x02, 0x65, 0x75, 0xAF, 0x69, 0xAE, 0x15, ++ 0x07, 0x54, 0xEE, 0x6A, 0x0A, 0x64, 0xEF, 0xFE, 0x75, 0x07, 0x70, 0x4E, 0x02, 0x80, 0x05, 0x65, ++ 0x65, 0xE5, 0x65, 0x05, 0x3D, 0x60, 0xFD, 0x24, 0x24, 0x7D, 0x60, 0x14, 0x41, 0x02, 0x70, 0xFE, ++ 0x60, 0x05, 0x24, 0x07, 0x90, 0x11, 0x41, 0x02, 0x69, 0xE5, 0x0A, 0x06, 0x6A, 0xE5, 0xA3, 0xF0, ++ 0xEF, 0x69, 0xAF, 0xF0, 0x13, 0xC3, 0x20, 0x54, 0x03, 0x06, 0x90, 0xFF, 0x4F, 0xEF, 0x54, 0xE0, ++ 0x0A, 0x06, 0x90, 0xF0, 0xC4, 0x80, 0x54, 0xE0, 0x90, 0xFF, 0x0F, 0x54, 0x54, 0xE0, 0x0D, 0x06, ++ 0x80, 0xF0, 0x4F, 0xF7, 0xA6, 0x89, 0x78, 0x5C, 0x28, 0x06, 0x90, 0x6A, 0x13, 0x13, 0xC4, 0xE0, ++ 0x90, 0xFF, 0x03, 0x54, 0xFE, 0xE0, 0xA1, 0x00, 0x00, 0x7F, 0x9F, 0xC3, 0x01, 0x7F, 0x02, 0x50, ++ 0x70, 0x00, 0x7E, 0xEE, 0xEF, 0x01, 0x7E, 0x02, 0x78, 0x36, 0x60, 0x4E, 0x08, 0x54, 0xE6, 0x89, ++ 0x14, 0x06, 0x90, 0xFF, 0x4F, 0xF7, 0x54, 0xE0, 0x10, 0x54, 0xE6, 0xF0, 0x3F, 0x54, 0x13, 0x13, ++ 0xFB, 0x54, 0xE0, 0xFF, 0x19, 0x80, 0xF0, 0x4F, 0x6A, 0xAF, 0x69, 0xAE, 0x78, 0x07, 0x54, 0xEE, ++ 0x08, 0xEF, 0xF6, 0x85, 0x90, 0x0A, 0x80, 0xF6, 0x69, 0xE5, 0xB7, 0x01, 0x6A, 0xE5, 0xA3, 0xF0, ++ 0x64, 0x65, 0xE5, 0xF0, 0x90, 0x11, 0x60, 0x01, 0x69, 0xE5, 0x10, 0x06, 0x6A, 0xE5, 0xA3, 0xF0, ++ 0x34, 0x06, 0x90, 0xF0, 0xF0, 0x20, 0x44, 0xE0, 0x20, 0x7A, 0xFF, 0x7B, 0x65, 0xAF, 0x50, 0x79, ++ 0x00, 0x7C, 0xFD, 0xEF, 0x90, 0xE5, 0x0C, 0x12, 0x44, 0xE0, 0x0D, 0x06, 0x69, 0xAF, 0xF0, 0x02, ++ 0x33, 0x08, 0x54, 0xEF, 0xF8, 0x54, 0x33, 0x33, 0xEE, 0x61, 0xAE, 0xFF, 0xF5, 0x4F, 0xBF, 0x54, ++ 0xEF, 0x61, 0xAF, 0x61, 0x13, 0x13, 0x13, 0xC4, 0x00, 0x7F, 0x01, 0x54, 0x7F, 0x02, 0xE0, 0x20, ++ 0x01, 0x54, 0xEF, 0x01, 0x33, 0x33, 0x33, 0xC4, 0xAE, 0xFF, 0x80, 0x54, 0x7F, 0x54, 0xEE, 0x61, ++ 0xE5, 0x61, 0xF5, 0x4F, 0x07, 0x01, 0xB4, 0x64, 0xE0, 0x08, 0x06, 0x90, 0xAF, 0xF0, 0xDF, 0x54, ++ 0xE0, 0x30, 0xEF, 0x62, 0xE6, 0x88, 0x78, 0x09, 0x40, 0x00, 0x94, 0xD3, 0x88, 0x78, 0x16, 0x01, ++ 0x90, 0x3E, 0x70, 0xE6, 0x13, 0xE0, 0x0D, 0x06, 0x30, 0x3F, 0x54, 0x13, 0x13, 0xE0, 0x2D, 0xE0, ++ 0x1F, 0x54, 0x13, 0x13, 0x85, 0x24, 0xE0, 0x30, 0x17, 0x85, 0x82, 0x18, 0x13, 0xC4, 0xE0, 0x83, ++ 0x01, 0x54, 0x13, 0x13, 0x90, 0x0D, 0xE0, 0x20, 0xC4, 0xE0, 0x10, 0x06, 0x54, 0x13, 0x13, 0x13, ++ 0x07, 0xE0, 0x30, 0x01, 0x75, 0x2A, 0x5B, 0x75, 0x75, 0x22, 0xD2, 0x5C, 0x5C, 0x75, 0x23, 0x5B, ++ 0x07, 0x90, 0x22, 0x5B, 0x07, 0x54, 0xE0, 0xA0, 0x06, 0x60, 0x02, 0x64, 0x75, 0x02, 0x5B, 0x75, ++ 0x08, 0x20, 0x33, 0x5C, 0x7B, 0x91, 0x81, 0x02, 0x79, 0x20, 0x7A, 0xFF, 0xF8, 0x03, 0x12, 0x5C, ++ 0xF6, 0x87, 0x78, 0xE4, 0x6A, 0xF5, 0x69, 0xF5, 0xFC, 0x24, 0x64, 0xE5, 0xFE, 0x24, 0x64, 0x60, ++ 0x70, 0x14, 0x7C, 0x60, 0x14, 0x97, 0x61, 0x02, 0x97, 0x61, 0x02, 0x70, 0x02, 0x60, 0x07, 0x24, ++ 0x06, 0x90, 0x95, 0x61, 0x13, 0xC4, 0xE0, 0x28, 0xFF, 0x03, 0x54, 0x13, 0xE0, 0xA1, 0x00, 0x90, ++ 0x7F, 0x9F, 0xC3, 0xFE, 0x7F, 0x02, 0x50, 0x00, 0x00, 0x7E, 0xEE, 0x01, 0x01, 0x7E, 0x02, 0x70, ++ 0x90, 0xFF, 0x4E, 0xEF, 0xC3, 0xE0, 0x12, 0x06, 0xFE, 0x01, 0x54, 0x13, 0x4E, 0x01, 0x54, 0xE0, ++ 0x75, 0x05, 0x60, 0x5F, 0x4F, 0x80, 0x02, 0x64, 0xE0, 0xB0, 0x01, 0x90, 0xE0, 0x30, 0x13, 0xC3, ++ 0x90, 0x15, 0x80, 0x02, 0xC4, 0xE0, 0x08, 0x06, 0x54, 0x13, 0x13, 0x13, 0x30, 0xE0, 0x20, 0x01, ++ 0x01, 0x90, 0x29, 0x80, 0x05, 0x60, 0xE0, 0xB0, 0x80, 0x05, 0x64, 0x75, 0x08, 0x06, 0x90, 0x2A, ++ 0x13, 0x13, 0xC4, 0xE0, 0x20, 0x01, 0x54, 0x13, 0x0F, 0x80, 0x02, 0xE0, 0x06, 0x90, 0x12, 0x80, ++ 0x13, 0xC4, 0xE0, 0x08, 0x01, 0x54, 0x13, 0x13, 0x75, 0x05, 0xE0, 0x20, 0x07, 0x80, 0x08, 0x64, ++ 0x80, 0x07, 0x64, 0x75, 0xE5, 0x64, 0x05, 0x02, 0x60, 0xFD, 0x24, 0x64, 0x02, 0x70, 0x14, 0x3F, ++ 0x60, 0x14, 0x37, 0x81, 0x02, 0x70, 0x14, 0x14, 0xFE, 0x24, 0x69, 0x81, 0x06, 0x24, 0x18, 0x60, ++ 0x82, 0x81, 0x02, 0x60, 0x80, 0x08, 0x6D, 0x75, 0x0A, 0x6D, 0x75, 0x03, 0xAF, 0x6C, 0xF5, 0xE4, ++ 0x80, 0x44, 0xEF, 0x6C, 0x6D, 0x75, 0x0B, 0x80, 0x6C, 0xF5, 0xE4, 0x01, 0x54, 0xEF, 0x6C, 0xAF, ++ 0xAF, 0x6C, 0xF5, 0x7F, 0x20, 0x44, 0xEF, 0x6C, 0x82, 0x81, 0x6C, 0xF5, 0xF5, 0x6C, 0xF5, 0xE4, ++ 0x12, 0x06, 0x90, 0x6D, 0xC4, 0x10, 0x54, 0xE0, 0xAE, 0xFF, 0x0F, 0x54, 0xFE, 0x54, 0xEE, 0x6D, ++ 0xE0, 0x6D, 0xF5, 0x4F, 0x13, 0x13, 0x08, 0x54, 0xAE, 0xFF, 0x3F, 0x54, 0xFD, 0x54, 0xEE, 0x6D, ++ 0xE0, 0x6D, 0xF5, 0x4F, 0xAE, 0xFF, 0x04, 0x54, 0xFB, 0x54, 0xEE, 0x6D, 0xE0, 0x6D, 0xF5, 0x4F, ++ 0xE0, 0x25, 0x02, 0x54, 0xAE, 0xFF, 0xE0, 0x25, 0xF7, 0x54, 0xEE, 0x6D, 0xE0, 0x6D, 0xF5, 0x4F, ++ 0x54, 0xC4, 0x01, 0x54, 0x6D, 0xAE, 0xFF, 0xF0, 0x4F, 0xEF, 0x54, 0xEE, 0x6C, 0xAF, 0x6D, 0xF5, ++ 0xF5, 0x80, 0x44, 0xEF, 0x78, 0x4B, 0x80, 0x6C, 0x07, 0x54, 0xE6, 0x7E, 0x08, 0xF7, 0x83, 0x79, ++ 0x78, 0xF7, 0x09, 0xE6, 0x6C, 0xF5, 0xE6, 0x83, 0x6D, 0xF5, 0xE6, 0x08, 0xE0, 0xB0, 0x01, 0x90, ++ 0x02, 0x60, 0x00, 0x7F, 0x06, 0x90, 0x01, 0x7F, 0x13, 0xC4, 0xE0, 0x08, 0x01, 0x54, 0x13, 0x13, ++ 0xC4, 0x01, 0x54, 0x4F, 0x80, 0x33, 0x33, 0x33, 0xAF, 0x01, 0x90, 0x0E, 0xA3, 0x6C, 0xF5, 0xE0, ++ 0x90, 0x6D, 0xF5, 0xE0, 0x54, 0xE0, 0x08, 0x06, 0x6C, 0xAE, 0xFF, 0x80, 0x4F, 0x7F, 0x54, 0xEE, ++ 0xFF, 0x7B, 0x6C, 0xF5, 0x66, 0x79, 0x20, 0x7A, 0xFD, 0xEF, 0x64, 0xAF, 0x0C, 0x12, 0x00, 0x7C, ++ 0x64, 0x64, 0xE5, 0xE5, 0xAF, 0x45, 0x70, 0x07, 0x13, 0x13, 0xEF, 0x20, 0x30, 0x1F, 0x54, 0x13, ++ 0x06, 0x90, 0x5B, 0xE0, 0x6C, 0xF5, 0xE0, 0x0E, 0x6D, 0xF5, 0xE0, 0xA3, 0x54, 0xEF, 0x61, 0xAF, ++ 0x0F, 0x54, 0xC4, 0x80, 0xEE, 0x6C, 0xAE, 0xFF, 0xF5, 0x4F, 0xF7, 0x54, 0x82, 0x18, 0x85, 0x6C, ++ 0xE5, 0x83, 0x17, 0x85, 0xE5, 0xA3, 0xF0, 0x6C, 0x06, 0x90, 0xF0, 0x6D, 0x13, 0xC4, 0xE0, 0x0E, ++ 0x01, 0x54, 0x13, 0x13, 0x75, 0x26, 0xE0, 0x20, 0x21, 0x80, 0x08, 0x64, 0xAF, 0x1E, 0x08, 0x30, ++ 0x80, 0x54, 0xEF, 0x61, 0xFF, 0x0F, 0x54, 0xC4, 0x54, 0xEE, 0x6C, 0xAE, 0x6C, 0xF5, 0x4F, 0xF7, ++ 0x85, 0x82, 0x18, 0x85, 0x6C, 0xE5, 0x83, 0x17, 0x6D, 0xE5, 0xA3, 0xF0, 0xEF, 0x62, 0xAF, 0xF0, ++ 0xE0, 0x30, 0x13, 0xC3, 0x82, 0x16, 0x85, 0x75, 0xE0, 0x83, 0x15, 0x85, 0xE0, 0xF0, 0xBF, 0x54, ++ 0x65, 0xE0, 0xA3, 0xFE, 0xEE, 0x03, 0x70, 0x6A, 0x4D, 0x70, 0x69, 0x65, 0xE6, 0x06, 0x87, 0x78, ++ 0x40, 0x02, 0x94, 0xC3, 0x85, 0x02, 0x76, 0x55, 0x15, 0x85, 0x82, 0x16, 0x13, 0x13, 0xE0, 0x83, ++ 0xFF, 0x01, 0x54, 0x13, 0xC4, 0xEE, 0x61, 0xAE, 0x01, 0x54, 0x13, 0x13, 0xE5, 0x3B, 0x60, 0x6F, ++ 0x0B, 0x07, 0xB4, 0x64, 0x13, 0xEF, 0x20, 0xAF, 0x1F, 0x54, 0x13, 0x13, 0x75, 0x2B, 0xE0, 0x30, ++ 0x5C, 0x75, 0x28, 0x5B, 0xB4, 0x64, 0xE5, 0x8D, 0x20, 0xAF, 0x20, 0x07, 0xF5, 0xF7, 0x54, 0xEF, ++ 0x34, 0x06, 0x90, 0x20, 0xF0, 0x10, 0x44, 0xE0, 0x82, 0x16, 0x85, 0x22, 0xE0, 0x83, 0x15, 0x85, ++ 0xE0, 0xA3, 0x69, 0xF5, 0x78, 0xE4, 0x6A, 0xF5, 0x90, 0x22, 0xF6, 0x87, 0x44, 0xE0, 0x03, 0x06, ++ 0x06, 0x90, 0xF0, 0x20, 0x04, 0x44, 0xE0, 0x34, 0x7A, 0xFF, 0x7B, 0xF0, 0x12, 0x79, 0x79, 0x20, ++ 0x78, 0xE4, 0xF8, 0x03, 0x06, 0x90, 0xF6, 0x87, 0x03, 0x54, 0xE0, 0x31, 0xE6, 0x87, 0x78, 0xFF, ++ 0x0E, 0x50, 0x9F, 0xC3, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x81, 0x79, 0x06, 0x87, 0x78, 0xF8, ++ 0x06, 0x90, 0xE4, 0x80, 0x13, 0xC4, 0xE0, 0x31, 0xFF, 0x03, 0x54, 0x13, 0x7B, 0x09, 0x01, 0xBF, ++ 0x79, 0x20, 0x7A, 0xFF, 0xF8, 0x03, 0x12, 0x83, 0xE0, 0x31, 0x06, 0x90, 0x54, 0x13, 0x13, 0xC4, ++ 0x03, 0xBF, 0xFF, 0x03, 0x7A, 0xFF, 0x7B, 0x09, 0x12, 0x85, 0x79, 0x20, 0x06, 0x90, 0xF8, 0x03, ++ 0x13, 0xFF, 0xE0, 0x31, 0x1F, 0x54, 0x13, 0x13, 0xE0, 0x30, 0xFF, 0x7B, 0x79, 0x20, 0x7A, 0x06, ++ 0x7A, 0x04, 0x80, 0x87, 0x12, 0x8B, 0x79, 0x20, 0x06, 0x90, 0xF8, 0x03, 0x03, 0x54, 0xE0, 0x31, ++ 0x1C, 0x02, 0xBF, 0xFF, 0xE0, 0x14, 0x06, 0x90, 0x13, 0x13, 0xC4, 0xFF, 0xFF, 0x7B, 0x03, 0x54, ++ 0x7A, 0x06, 0xE0, 0x30, 0x80, 0x8F, 0x79, 0x20, 0x79, 0x20, 0x7A, 0x04, 0xF8, 0x03, 0x12, 0x92, ++ 0xE0, 0x31, 0x06, 0x90, 0x54, 0x13, 0x13, 0xFF, 0x09, 0xE0, 0x30, 0x3F, 0x20, 0x7A, 0xFF, 0x7B, ++ 0x03, 0x12, 0x95, 0x79, 0x7A, 0xFF, 0x7B, 0xF8, 0x90, 0x9A, 0x79, 0x20, 0xFF, 0xE0, 0x31, 0x06, ++ 0xFD, 0x03, 0x54, 0xC4, 0x0C, 0x12, 0x00, 0x7C, 0x2E, 0x5B, 0x75, 0xE5, 0x22, 0x50, 0x5C, 0x75, ++ 0xE0, 0x14, 0x06, 0x90, 0x90, 0xF0, 0x7F, 0x54, 0x54, 0xE0, 0xAD, 0x01, 0x5D, 0x75, 0xF0, 0xFB, ++ 0xC5, 0x5E, 0x75, 0x01, 0x00, 0x00, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x30, 0x30, 0x31, 0x09, 0x65, 0x73, 0x61, 0x62, 0x20, 0x31, 0x54, 0x2D, 0x00, 0x0A, 0x53, 0x4E, ++ 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x02, 0x00, 0x79, 0x00, 0x00, 0x22, 0xF8, 0x00, 0x00, 0x00, 0x00, ++ 0x50, 0x53, 0x41, 0x09, 0x09, 0x64, 0x25, 0x3A, 0x43, 0x47, 0x41, 0x00, 0x09, 0x64, 0x25, 0x3A, ++ 0x25, 0x3A, 0x4D, 0x00, 0x48, 0x00, 0x09, 0x64, 0x0A, 0x64, 0x25, 0x3A, 0x62, 0x41, 0x09, 0x00, ++ 0x0A, 0x74, 0x73, 0x69, 0x61, 0x57, 0x09, 0x00, 0x00, 0x0A, 0x74, 0x69, 0x69, 0x78, 0x45, 0x09, ++ 0x09, 0x00, 0x0A, 0x74, 0x30, 0x31, 0x43, 0x44, 0x44, 0x09, 0x00, 0x0A, 0x30, 0x30, 0x31, 0x43, ++ 0x09, 0x00, 0x0A, 0x30, 0x0A, 0x4E, 0x43, 0x49, 0x48, 0x54, 0x09, 0x00, 0x09, 0x00, 0x0A, 0x44, ++ 0x0A, 0x43, 0x47, 0x41, 0x3A, 0x50, 0x09, 0x00, 0x0A, 0x64, 0x25, 0x20, 0x58, 0x45, 0x09, 0x00, ++ 0x09, 0x00, 0x0A, 0x43, 0x20, 0x43, 0x44, 0x41, 0x0A, 0x52, 0x45, 0x42, 0x08, 0x03, 0x01, 0x00, ++ 0x08, 0x09, 0x0A, 0x09, 0xF8, 0xFD, 0x00, 0x03, 0xF8, 0xF7, 0xF6, 0xF7, 0x62, 0x00, 0x00, 0xFD, ++ 0xED, 0x00, 0xB5, 0x00, 0xED, 0x00, 0x00, 0x01, 0x62, 0x00, 0xB5, 0x00, 0x9E, 0xFF, 0x00, 0x00, ++ 0x13, 0xFF, 0x4B, 0xFF, 0x13, 0xFF, 0x00, 0xFF, 0x9E, 0xFF, 0x4B, 0xFF, 0x00, 0x00, 0x00, 0x00, ++ 0x8B, 0x0C, 0x47, 0x06, 0xF8, 0x18, 0xC8, 0x12, 0x28, 0x25, 0x19, 0x1F, 0xFB, 0x30, 0x1F, 0x2B, ++ 0x56, 0x3C, 0xBA, 0x36, 0x1C, 0x47, 0xCE, 0x41, 0x33, 0x51, 0x3F, 0x4C, 0x82, 0x5A, 0xF5, 0x55, ++ 0xF2, 0x62, 0xD7, 0x5E, 0x6D, 0x6A, 0xCF, 0x66, 0xE2, 0x70, 0xCA, 0x6D, 0x41, 0x76, 0xB5, 0x73, ++ 0x7D, 0x7A, 0x84, 0x78, 0x8A, 0x7D, 0x29, 0x7C, 0x62, 0x7F, 0x9D, 0x7E, 0xFF, 0x7F, 0xD8, 0x7F, ++ 0x30, 0x10, 0x20, 0x00, 0x38, 0x18, 0x28, 0x08, 0x34, 0x14, 0x24, 0x04, 0x3C, 0x1C, 0x2C, 0x0C, ++ 0x32, 0x12, 0x22, 0x02, 0x3A, 0x1A, 0x2A, 0x0A, 0x36, 0x16, 0x26, 0x06, 0x3E, 0x1E, 0x2E, 0x0E, ++ 0x31, 0x11, 0x21, 0x01, 0x39, 0x19, 0x29, 0x09, 0x35, 0x15, 0x25, 0x05, 0x3D, 0x1D, 0x2D, 0x0D, ++ 0x33, 0x13, 0x23, 0x03, 0x3B, 0x1B, 0x2B, 0x0B, 0x37, 0x17, 0x27, 0x07, 0x3F, 0x1F, 0x2F, 0x0F, ++ 0x51, 0xA9, 0x50, 0xA8, 0x53, 0xAB, 0x52, 0xAA, 0xA4, 0xF0, 0x8F, 0xE8, 0xA4, 0xF0, 0x8B, 0xCC, ++ 0x8E, 0xE9, 0xFC, 0x2C, 0xFC, 0x2C, 0xA4, 0xF0, 0xA4, 0xED, 0xF0, 0x8A, 0x8E, 0xEA, 0xFC, 0x2C, ++ 0xA8, 0xCD, 0xA4, 0xF0, 0xA4, 0xF0, 0x8B, 0xF0, 0x25, 0x38, 0xCC, 0x2D, 0x8F, 0xE9, 0xFD, 0xF0, ++ 0xCD, 0x2C, 0xA4, 0xF0, 0xEB, 0xFC, 0xF0, 0x35, 0xFE, 0xA4, 0xF0, 0x8E, 0x8F, 0xEB, 0xF0, 0xA9, ++ 0xC5, 0xCF, 0xA4, 0xF0, 0x39, 0xCD, 0x2E, 0xF0, 0xFC, 0x3C, 0xE4, 0xFE, 0xCE, 0x2D, 0xA4, 0xEA, ++ 0xE4, 0xFD, 0xF0, 0x35, 0xEC, 0x22, 0xFC, 0x3C, 0xFC, 0x13, 0xE7, 0xA2, 0xEE, 0xFD, 0x13, 0xED, ++ 0x13, 0xEF, 0xFE, 0x13, 0xC3, 0xEF, 0x22, 0xFF, 0x33, 0xEE, 0xFF, 0x33, 0xFD, 0x33, 0xED, 0xFE, ++ 0x22, 0xFC, 0x33, 0xEC, 0xE7, 0x30, 0x62, 0xE5, 0x7A, 0xFF, 0x7B, 0x42, 0xAF, 0x00, 0x79, 0x20, ++ 0x7C, 0xFD, 0xEF, 0x65, 0xE5, 0x0C, 0x12, 0x00, 0x20, 0x7A, 0xFF, 0x7B, 0x66, 0xAF, 0x09, 0x79, ++ 0x00, 0x7C, 0xFD, 0xEF, 0x7B, 0xE5, 0x0C, 0x12, 0x79, 0x20, 0x7A, 0xFF, 0xEF, 0x67, 0xAF, 0x11, ++ 0x12, 0x00, 0x7C, 0xFD, 0xFF, 0x7B, 0xE5, 0x0C, 0x17, 0x79, 0x20, 0x7A, 0xFD, 0xEF, 0x68, 0xAF, ++ 0x0C, 0x12, 0x00, 0x7C, 0x06, 0x0B, 0x30, 0xE5, 0x12, 0xFA, 0x80, 0x00, 0x30, 0x22, 0x1F, 0x02, ++ 0xF7, 0x31, 0x0E, 0x08, 0xE0, 0x6A, 0x07, 0x90, 0xE0, 0xF0, 0xFE, 0x54, 0x22, 0xF0, 0x01, 0x44, ++ 0x75, 0x2D, 0x5B, 0x75, 0x31, 0x22, 0x9A, 0x5C, 0x33, 0x68, 0xE5, 0x94, 0xF8, 0x54, 0x33, 0x33, ++ 0xC4, 0x67, 0xE5, 0xFF, 0x4F, 0xE0, 0x54, 0x33, 0x0D, 0x90, 0x66, 0x45, 0x0D, 0x7E, 0xF0, 0x00, ++ 0x0B, 0x12, 0x00, 0x7F, 0xEF, 0x65, 0xAF, 0xD1, 0x90, 0xFF, 0x03, 0x54, 0x54, 0xE0, 0xF2, 0x07, ++ 0x22, 0xF0, 0x4F, 0xFC, 0x31, 0x15, 0x08, 0x30, 0xFC, 0xFD, 0xE4, 0xF7, 0x7E, 0x1D, 0xF1, 0xFF, ++ 0x51, 0xAC, 0x7F, 0x00, 0x6A, 0x07, 0x90, 0x8C, 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x6B, 0x07, 0x90, ++ 0x7F, 0x0A, 0xE0, 0x30, 0x75, 0x6F, 0xD1, 0x06, 0x5C, 0x75, 0x27, 0x5B, 0x08, 0x30, 0x22, 0xCE, ++ 0x31, 0x94, 0x31, 0x1B, 0xFC, 0xFD, 0xE4, 0xF9, 0x1D, 0xF1, 0x01, 0x7F, 0xAC, 0x7F, 0x00, 0x7E, ++ 0x61, 0x75, 0x8C, 0x51, 0x6A, 0x07, 0x90, 0x3F, 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x6B, 0x07, 0x90, ++ 0xE4, 0x18, 0xE0, 0x30, 0xE5, 0x6F, 0xD1, 0xFF, 0x15, 0x0A, 0x60, 0x61, 0x6A, 0x07, 0x90, 0x61, ++ 0xF0, 0x01, 0x44, 0xE0, 0x28, 0x5B, 0x75, 0x22, 0x22, 0xF6, 0x5C, 0x75, 0xEF, 0xFC, 0xFD, 0xE4, ++ 0xFF, 0x02, 0x24, 0xFB, 0x00, 0x34, 0xFA, 0xEE, 0x8A, 0x82, 0x8B, 0xFE, 0xA3, 0xF0, 0xE4, 0x83, ++ 0x00, 0xBD, 0x0D, 0xF0, 0x64, 0xED, 0x0C, 0x01, 0xE3, 0x70, 0x4C, 0x80, 0x6A, 0x07, 0x90, 0x22, ++ 0xF0, 0xFE, 0x54, 0xE0, 0x00, 0x7F, 0x05, 0x7E, 0x00, 0x7E, 0x8C, 0x51, 0x05, 0x7C, 0xAC, 0x7F, ++ 0x23, 0x8E, 0x00, 0x7D, 0x25, 0x8C, 0x24, 0x8F, 0xCB, 0xB1, 0x26, 0x8D, 0x25, 0xAC, 0x26, 0xAD, ++ 0x23, 0xAE, 0x24, 0xAF, 0x28, 0x8F, 0x27, 0x8E, 0x2A, 0x8D, 0x29, 0x8C, 0x75, 0x00, 0x30, 0x75, ++ 0x32, 0x75, 0x40, 0x31, 0x01, 0x33, 0x75, 0x00, 0x94, 0x33, 0xE5, 0xD3, 0x94, 0x32, 0xE5, 0x40, ++ 0xA1, 0x02, 0x40, 0x00, 0x2E, 0xF5, 0xE4, 0xAB, 0x2C, 0xF5, 0x2B, 0xF5, 0x95, 0x2C, 0xE5, 0xC3, ++ 0x30, 0x95, 0xE4, 0x31, 0x93, 0xA1, 0x02, 0x40, 0xC3, 0x2D, 0xF5, 0xE4, 0x33, 0x95, 0x2D, 0xE5, ++ 0x40, 0x32, 0x95, 0xE4, 0xE5, 0x87, 0xA1, 0x02, 0xF5, 0x33, 0x25, 0x2E, 0xB4, 0x2E, 0xE5, 0x2F, ++ 0x2F, 0xE5, 0x0B, 0x3C, 0xB1, 0x06, 0x3D, 0xB4, 0x8F, 0x3C, 0x8E, 0xAC, 0x8E, 0xAC, 0xB1, 0x3D, ++ 0xAD, 0x3D, 0x8F, 0x3C, 0x8E, 0xAE, 0xB1, 0x2F, 0xAD, 0x3F, 0x8F, 0x3E, 0xAE, 0x2A, 0xAF, 0x2E, ++ 0x8E, 0xB2, 0xB1, 0x29, 0xAD, 0x39, 0x8F, 0x38, 0xAE, 0x2A, 0xAF, 0x2F, 0x8E, 0xB2, 0xB1, 0x29, ++ 0xE5, 0x3B, 0x8F, 0x3A, 0x20, 0x94, 0xD3, 0x2B, 0x40, 0x74, 0x37, 0x40, 0xE0, 0x25, 0x2B, 0x95, ++ 0x82, 0xF5, 0x9E, 0x24, 0xF5, 0x20, 0x34, 0xE4, 0xF5, 0x93, 0xE4, 0x83, 0x93, 0x01, 0x74, 0x36, ++ 0x2B, 0xE5, 0x37, 0xF5, 0x5E, 0x24, 0xE0, 0x25, 0x34, 0xE4, 0x82, 0xF5, 0xE4, 0x83, 0xF5, 0x20, ++ 0x01, 0x74, 0xFE, 0x93, 0xE4, 0xC3, 0xFF, 0x93, 0xE4, 0x35, 0xF5, 0x9F, 0x80, 0x34, 0xF5, 0x9E, ++ 0x25, 0x2B, 0xE5, 0x2F, 0xF5, 0x9E, 0x24, 0xE0, 0x20, 0x34, 0xE4, 0x82, 0x93, 0xE4, 0x83, 0xF5, ++ 0x01, 0x74, 0x36, 0xF5, 0xC3, 0x37, 0xF5, 0x93, 0x2B, 0x95, 0x20, 0x74, 0x9E, 0x24, 0xE0, 0x25, ++ 0x34, 0xE4, 0x82, 0xF5, 0xE4, 0x83, 0xF5, 0x20, 0x74, 0x34, 0xF5, 0x93, 0x35, 0xF5, 0x93, 0x01, ++ 0x3B, 0xAF, 0x3A, 0xAE, 0xE0, 0x95, 0x33, 0xEE, 0x06, 0xC0, 0xFC, 0xFD, 0x33, 0xEE, 0x36, 0xAE, ++ 0x37, 0x85, 0xE0, 0x95, 0xF5, 0x52, 0x8E, 0x53, 0xD0, 0x50, 0xF5, 0x51, 0xC0, 0x20, 0x31, 0x06, ++ 0xC0, 0x05, 0xC0, 0x04, 0xAE, 0x07, 0xC0, 0x06, 0xEE, 0x3F, 0xAF, 0x3E, 0xFD, 0xE0, 0x95, 0x33, ++ 0xAE, 0x06, 0xC0, 0xFC, 0x95, 0x33, 0xEE, 0x34, 0x53, 0x35, 0x85, 0xE0, 0x51, 0xF5, 0x52, 0x8E, ++ 0x06, 0xD0, 0x50, 0xF5, 0x03, 0xD0, 0x20, 0x31, 0x01, 0xD0, 0x02, 0xD0, 0x2B, 0xEF, 0x00, 0xD0, ++ 0x3A, 0xEE, 0x43, 0xF5, 0x39, 0xED, 0x42, 0xF5, 0x38, 0xEC, 0x41, 0xF5, 0x3E, 0xAE, 0x40, 0xF5, ++ 0x33, 0xEE, 0x3F, 0xAF, 0xFC, 0xFD, 0xE0, 0x95, 0x36, 0xAE, 0x06, 0xC0, 0xE0, 0x95, 0x33, 0xEE, ++ 0x8E, 0x53, 0x37, 0x85, 0xF5, 0x51, 0xF5, 0x52, 0x31, 0x06, 0xD0, 0x50, 0xC0, 0x04, 0xC0, 0x20, ++ 0xC0, 0x06, 0xC0, 0x05, 0xAF, 0x3A, 0xAE, 0x07, 0x95, 0x33, 0xEE, 0x3B, 0xC0, 0xFC, 0xFD, 0xE0, ++ 0xEE, 0x34, 0xAE, 0x06, 0x85, 0xE0, 0x95, 0x33, 0x52, 0x8E, 0x53, 0x35, 0x50, 0xF5, 0x51, 0xF5, ++ 0x20, 0x31, 0x06, 0xD0, 0x02, 0xD0, 0x03, 0xD0, 0x00, 0xD0, 0x01, 0xD0, 0xF5, 0x9B, 0xEF, 0xC3, ++ 0xF5, 0x9A, 0xEE, 0x47, 0xF5, 0x99, 0xED, 0x46, 0xF5, 0x98, 0xEC, 0x45, 0x4A, 0xF5, 0xE4, 0x44, ++ 0x3C, 0x85, 0x4B, 0xF5, 0x49, 0x3D, 0x85, 0x48, 0x4A, 0xAE, 0x4B, 0xAF, 0x48, 0xAC, 0x49, 0xAD, ++ 0x4B, 0x8F, 0x77, 0x31, 0x49, 0x8D, 0x4A, 0x8E, 0x4B, 0xE5, 0x48, 0x8C, 0x4B, 0xF5, 0x43, 0x25, ++ 0x42, 0x35, 0x4A, 0xE5, 0x49, 0xE5, 0x4A, 0xF5, 0x49, 0xF5, 0x41, 0x35, 0x40, 0x35, 0x48, 0xE5, ++ 0x49, 0xAB, 0x48, 0xF5, 0x2E, 0xAD, 0x48, 0xAA, 0x27, 0xAE, 0x28, 0xAF, 0xF5, 0xE4, 0x56, 0xD1, ++ 0x85, 0x4B, 0xF5, 0x4A, 0x3D, 0x85, 0x48, 0x3C, 0xAE, 0x4B, 0xAF, 0x49, 0xAC, 0x49, 0xAD, 0x4A, ++ 0x8F, 0x77, 0x31, 0x48, 0x8D, 0x4A, 0x8E, 0x4B, 0xC3, 0x48, 0x8C, 0x49, 0x43, 0x95, 0x4B, 0xE5, ++ 0x4A, 0xE5, 0x4B, 0xF5, 0x4A, 0xF5, 0x42, 0x95, 0x41, 0x95, 0x49, 0xE5, 0x48, 0xE5, 0x49, 0xF5, ++ 0x48, 0xF5, 0x40, 0x95, 0x48, 0xAA, 0x49, 0xAB, 0x28, 0xAF, 0x2F, 0xAD, 0x56, 0xD1, 0x27, 0xAE, ++ 0xF5, 0x4A, 0xF5, 0xE4, 0x48, 0x38, 0x85, 0x4B, 0xAF, 0x49, 0x39, 0x85, 0xAD, 0x4A, 0xAE, 0x4B, ++ 0x31, 0x48, 0xAC, 0x49, 0x8E, 0x4B, 0x8F, 0x77, 0x8C, 0x49, 0x8D, 0x4A, 0x25, 0x4B, 0xE5, 0x48, ++ 0xE5, 0x4B, 0xF5, 0x47, 0xF5, 0x46, 0x35, 0x4A, 0x35, 0x49, 0xE5, 0x4A, 0xE5, 0x49, 0xF5, 0x45, ++ 0xF5, 0x44, 0x35, 0x48, 0xAA, 0x49, 0xAB, 0x48, 0xD1, 0x2E, 0xAD, 0x48, 0x4A, 0xF5, 0xE4, 0x52, ++ 0x38, 0x85, 0x4B, 0xF5, 0x49, 0x39, 0x85, 0x48, 0x4A, 0xAE, 0x4B, 0xAF, 0x48, 0xAC, 0x49, 0xAD, ++ 0x4B, 0x8F, 0x77, 0x31, 0x49, 0x8D, 0x4A, 0x8E, 0xE5, 0xC3, 0x48, 0x8C, 0xF5, 0x47, 0x95, 0x4B, ++ 0x95, 0x4A, 0xE5, 0x4B, 0xE5, 0x4A, 0xF5, 0x46, 0xF5, 0x45, 0x95, 0x49, 0x95, 0x48, 0xE5, 0x49, ++ 0xAB, 0x48, 0xF5, 0x44, 0xAD, 0x48, 0xAA, 0x49, 0x05, 0x52, 0xD1, 0x2F, 0x25, 0x31, 0xE5, 0x2E, ++ 0x05, 0x2B, 0xF5, 0x2B, 0xE5, 0x0B, 0x61, 0x2D, 0x2E, 0xF5, 0x04, 0x2F, 0x05, 0x2B, 0xF5, 0xE4, ++ 0xE5, 0xFC, 0x41, 0x2C, 0xF5, 0x13, 0xC3, 0x30, 0x13, 0x31, 0xE5, 0x30, 0x33, 0xE5, 0x31, 0xF5, ++ 0x33, 0xF5, 0xE0, 0x25, 0xF5, 0x33, 0x32, 0xE5, 0x22, 0xE8, 0x41, 0x32, 0x28, 0xAF, 0x2E, 0xAD, ++ 0x82, 0x8F, 0x27, 0xAE, 0x75, 0xED, 0x83, 0x8E, 0x25, 0xA4, 0x02, 0xF0, 0xE5, 0x82, 0xF5, 0x82, ++ 0xF5, 0x83, 0x35, 0xF0, 0xA3, 0xFE, 0xE0, 0x83, 0x8E, 0x22, 0xFF, 0xE0, 0x8C, 0x28, 0x8F, 0x27, ++ 0x75, 0x2A, 0x8D, 0x29, 0x0C, 0xD2, 0x01, 0x2D, 0x85, 0x11, 0x0C, 0x30, 0x2D, 0xE5, 0x2B, 0x2D, ++ 0x93, 0xE0, 0x20, 0x90, 0x2C, 0xF5, 0xE0, 0x25, 0x0A, 0x80, 0x0C, 0xC2, 0x2B, 0x25, 0x40, 0x74, ++ 0x2C, 0x05, 0x2B, 0xF5, 0x2C, 0xE5, 0x0C, 0xD2, 0x40, 0x2B, 0x95, 0xD3, 0xB1, 0x2B, 0xAD, 0x48, ++ 0x8F, 0x2E, 0x8E, 0xAE, 0xB1, 0x2C, 0xAD, 0x2F, 0xAB, 0x06, 0xAA, 0xAE, 0xAF, 0x2B, 0xAD, 0x07, ++ 0xD1, 0x27, 0xAE, 0x28, 0xAA, 0x2F, 0xAB, 0x56, 0xAF, 0x2C, 0xAD, 0x2E, 0xD1, 0x27, 0xAE, 0x28, ++ 0xAF, 0x2B, 0xAD, 0x56, 0xB1, 0x29, 0xAE, 0x2A, 0x8F, 0x2E, 0x8E, 0xB2, 0xAF, 0x2C, 0xAD, 0x2F, ++ 0xB1, 0x29, 0xAE, 0x2A, 0xAB, 0x06, 0xAA, 0xB2, 0xD1, 0x2B, 0xAD, 0x07, 0xAA, 0x2F, 0xAB, 0x52, ++ 0xD1, 0x2C, 0xAD, 0x2E, 0x90, 0x0C, 0x30, 0x52, 0x2D, 0xE5, 0x2D, 0x05, 0x40, 0x40, 0x94, 0xC3, ++ 0x2A, 0xAF, 0x22, 0x85, 0x82, 0x8F, 0x29, 0xAE, 0x75, 0xED, 0x83, 0x8E, 0x25, 0xA4, 0x02, 0xF0, ++ 0xE5, 0x82, 0xF5, 0x82, 0xF5, 0x83, 0x35, 0xF0, 0xA3, 0xF0, 0xEA, 0x83, 0xAD, 0x22, 0xF0, 0xEB, ++ 0x6A, 0x07, 0x90, 0x07, 0xF0, 0xFE, 0x54, 0xE0, 0x25, 0xEC, 0xFC, 0xE4, 0xF5, 0x00, 0x24, 0xE0, ++ 0x05, 0x34, 0xE4, 0x82, 0xFE, 0xE0, 0x83, 0xF5, 0x05, 0xA8, 0xE0, 0xA3, 0xC3, 0x05, 0x80, 0x08, ++ 0xCE, 0x33, 0xCE, 0x33, 0xEC, 0xFF, 0xF9, 0xD8, 0xAC, 0x24, 0xE0, 0x25, 0x34, 0xE4, 0x82, 0xF5, ++ 0xE0, 0x83, 0xF5, 0x00, 0x2F, 0xE0, 0xA3, 0xFA, 0xFE, 0x3E, 0xEA, 0xFF, 0x24, 0xE0, 0x25, 0xEC, ++ 0xE4, 0x82, 0xF5, 0xAC, 0x83, 0xF5, 0x00, 0x34, 0xEF, 0xA3, 0xF0, 0xEE, 0x80, 0xBC, 0x0C, 0xF0, ++ 0x69, 0xE5, 0x22, 0xB9, 0x7B, 0x1F, 0xE0, 0x20, 0x79, 0x20, 0x7A, 0xFF, 0xF8, 0x03, 0x12, 0x33, ++ 0x08, 0x90, 0x69, 0xE5, 0x05, 0xE1, 0x30, 0x3E, 0x80, 0xF0, 0xE4, 0xE0, 0x2E, 0x74, 0xE0, 0x04, ++ 0x67, 0xF5, 0xE4, 0xF0, 0xFF, 0x7B, 0x1D, 0x80, 0x3A, 0x79, 0x20, 0x7A, 0xE5, 0xF8, 0x03, 0x12, ++ 0x3E, 0x08, 0x90, 0x69, 0xE0, 0x05, 0xE1, 0x30, 0x04, 0x80, 0xF0, 0xE4, 0xF0, 0x40, 0x74, 0xE0, ++ 0x31, 0x01, 0x67, 0x75, 0x7C, 0x0F, 0x7D, 0xF9, 0xF1, 0xFF, 0xE4, 0x00, 0x90, 0xA6, 0xF1, 0x1D, ++ 0x44, 0xE0, 0x6A, 0x07, 0x5B, 0x75, 0xF0, 0x01, 0x3A, 0x5C, 0x75, 0x2D, 0x8C, 0x23, 0x8F, 0x22, ++ 0x90, 0x25, 0x8D, 0x24, 0x54, 0xE0, 0x6A, 0x07, 0x26, 0x75, 0xF0, 0xFE, 0x00, 0x27, 0x75, 0x04, ++ 0xE5, 0xFE, 0xFF, 0xE4, 0x70, 0x01, 0x64, 0x23, 0x0F, 0x54, 0xEF, 0x40, 0x70, 0x69, 0xE5, 0xF9, ++ 0x20, 0x90, 0xE9, 0x0C, 0x33, 0xFD, 0x93, 0x6E, 0x80, 0xFC, 0xE0, 0x95, 0xE0, 0x25, 0xE9, 0x13, ++ 0x82, 0xF5, 0x7E, 0x24, 0xF5, 0x20, 0x34, 0xE4, 0xFC, 0x93, 0xE4, 0x83, 0xFD, 0x93, 0x01, 0x74, ++ 0x24, 0xFB, 0x27, 0xE5, 0xE5, 0x27, 0xF5, 0x02, 0x00, 0x34, 0xFA, 0x26, 0x82, 0x8B, 0x26, 0xF5, ++ 0xF0, 0xEC, 0x83, 0x8A, 0x80, 0xF0, 0xED, 0xA3, 0xFD, 0x27, 0xE5, 0x19, 0x27, 0xF5, 0x02, 0x24, ++ 0x34, 0xFC, 0x26, 0xE5, 0x8D, 0x26, 0xF5, 0x00, 0xE5, 0x83, 0x8C, 0x82, 0xE5, 0xA3, 0xF0, 0x24, ++ 0xBF, 0x0F, 0xF0, 0x25, 0xEF, 0x0E, 0x01, 0x00, 0x64, 0xEE, 0x03, 0x70, 0x22, 0x94, 0x70, 0x01, ++ 0x01, 0x7F, 0xFC, 0xFD, 0x07, 0x90, 0x1D, 0xF1, 0xFE, 0x54, 0xE0, 0x6A, 0xF9, 0x54, 0xE0, 0xF0, ++ 0x90, 0xF0, 0x04, 0x44, 0x01, 0x74, 0x6C, 0x07, 0x6D, 0x07, 0x90, 0xF0, 0xF0, 0xFF, 0x74, 0xE0, ++ 0xE0, 0x6E, 0x07, 0x90, 0x90, 0xF0, 0xFF, 0x74, 0xE4, 0xE0, 0x6F, 0x07, 0xAD, 0x51, 0x22, 0xF0, ++ 0xE5, 0x04, 0x2B, 0x12, 0x03, 0x94, 0xD3, 0x65, 0x5B, 0x75, 0x07, 0x40, 0x7C, 0x5C, 0x75, 0x2D, ++ 0x22, 0x5B, 0x75, 0x22, 0x22, 0x24, 0x5C, 0x75, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x63, 0x79, ++ 0x66, 0xF5, 0xE4, 0xF8, 0xF5, 0x01, 0x67, 0x75, 0x90, 0xF9, 0x31, 0x68, 0x70, 0xE0, 0x3A, 0x06, ++ 0x64, 0xE0, 0xA3, 0x04, 0x90, 0x17, 0x60, 0xAA, 0x75, 0xE0, 0x3A, 0x06, 0x79, 0xA4, 0x40, 0xF0, ++ 0xF0, 0xE5, 0xF7, 0x79, 0xE0, 0xA3, 0xF7, 0x19, 0xF0, 0xD9, 0x09, 0x90, 0x78, 0x78, 0x0D, 0x80, ++ 0x76, 0x08, 0x27, 0x76, 0xD9, 0x09, 0x90, 0x00, 0xE4, 0xF0, 0x10, 0x74, 0x08, 0xF6, 0x76, 0x78, ++ 0xD7, 0x09, 0x90, 0xF6, 0xD4, 0x09, 0x90, 0xF0, 0x74, 0xF0, 0x95, 0x74, 0x90, 0xE4, 0xF0, 0x91, ++ 0x12, 0xF0, 0xD8, 0x09, 0x07, 0x90, 0xA0, 0x27, 0x01, 0x44, 0xE0, 0x6A, 0x07, 0x90, 0xE4, 0xF0, ++ 0x07, 0x90, 0xF0, 0xF1, 0xF0, 0xE4, 0x74, 0xF2, 0xE0, 0x38, 0x06, 0x90, 0xE0, 0xA3, 0x02, 0x70, ++ 0x06, 0x90, 0x1A, 0x60, 0x09, 0x90, 0xE0, 0x39, 0x06, 0x90, 0xF0, 0xD2, 0xE0, 0x30, 0xE0, 0x38, ++ 0x00, 0x0D, 0x90, 0x10, 0x12, 0x18, 0x44, 0xE0, 0x05, 0x80, 0xCC, 0x0B, 0xD2, 0x09, 0x90, 0xE4, ++ 0xCC, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x05, 0x74, 0xFF, 0x74, 0xD5, 0x09, 0x2F, 0x5B, 0x75, 0xF0, ++ 0x22, 0x01, 0x5C, 0x75, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x4F, 0x79, 0x65, 0xF5, 0xE4, 0xF8, ++ 0x75, 0x07, 0x66, 0x75, 0x68, 0x75, 0x01, 0x67, 0x00, 0x6A, 0x75, 0x03, 0xAE, 0x00, 0x6B, 0x75, ++ 0xEF, 0x6B, 0xAF, 0x6A, 0x64, 0xF5, 0x08, 0x24, 0x63, 0xF5, 0x3E, 0xE4, 0x08, 0x90, 0x69, 0xE5, ++ 0x74, 0x05, 0x70, 0x3E, 0x03, 0x80, 0xF0, 0x14, 0x90, 0xF0, 0x0C, 0x74, 0x03, 0x74, 0x36, 0x08, ++ 0xF0, 0x01, 0x74, 0xF0, 0x74, 0x40, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x11, 0xF0, 0x0E, 0x74, 0x43, ++ 0x74, 0x42, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x01, 0xE4, 0xF0, 0x04, 0x44, 0x75, 0xA0, 0x27, 0x12, ++ 0x5C, 0x75, 0x21, 0x5B, 0x22, 0x12, 0x22, 0xDF, 0xE5, 0x10, 0x31, 0xAD, 0x03, 0x94, 0xD3, 0x65, ++ 0x5B, 0x75, 0x07, 0x40, 0x94, 0x5C, 0x75, 0x28, 0x22, 0x5B, 0x75, 0x22, 0x22, 0x4E, 0x5C, 0x75, ++ 0x1F, 0x70, 0x67, 0xE5, 0x6B, 0xAF, 0x6A, 0xAE, 0xF5, 0x10, 0x24, 0xEF, 0xF5, 0x3E, 0xE4, 0x24, ++ 0x74, 0x65, 0x05, 0x23, 0xF5, 0x6B, 0x25, 0x28, 0x6A, 0x35, 0xE4, 0x6B, 0x67, 0x75, 0x6A, 0xF5, ++ 0xE5, 0x24, 0x80, 0x01, 0xAF, 0x6A, 0xAE, 0x68, 0xEF, 0x0E, 0x70, 0x6B, 0x24, 0xF5, 0x15, 0x24, ++ 0x23, 0xF5, 0x3E, 0xE4, 0x80, 0x03, 0x68, 0x75, 0x1A, 0x24, 0xEF, 0x0E, 0x3E, 0xE4, 0x24, 0xF5, ++ 0xF5, 0xE4, 0x23, 0xF5, 0xE4, 0x67, 0xF5, 0x68, 0xC0, 0xDC, 0x31, 0xFF, 0x31, 0x08, 0x7F, 0x07, ++ 0x7F, 0x07, 0xC0, 0xDC, 0xC0, 0xDC, 0x31, 0x10, 0x31, 0x18, 0x7F, 0x07, 0x7F, 0x07, 0xC0, 0xDC, ++ 0x8F, 0xDC, 0x31, 0x20, 0xD0, 0x30, 0xD0, 0x31, 0xD0, 0x03, 0xD0, 0x2F, 0xAE, 0x24, 0xAF, 0x05, ++ 0x8F, 0x2B, 0x8E, 0x23, 0xE5, 0x2C, 0x05, 0x2C, 0x05, 0x02, 0x70, 0x2C, 0x82, 0xF5, 0x14, 0x2B, ++ 0xF0, 0xED, 0x83, 0x8E, 0x2C, 0xE5, 0x2C, 0x05, 0x02, 0x70, 0x2B, 0xAE, 0xF5, 0x14, 0x2B, 0x05, ++ 0xEB, 0x83, 0x8E, 0x82, 0xE5, 0x2C, 0x05, 0xF0, 0x70, 0x2B, 0xAE, 0x2C, 0x14, 0x2B, 0x05, 0x02, ++ 0x83, 0x8E, 0x82, 0xF5, 0x05, 0xF0, 0x2F, 0xE5, 0xAE, 0x2C, 0xE5, 0x2C, 0x05, 0x02, 0x70, 0x2B, ++ 0x82, 0xF5, 0x14, 0x2B, 0x30, 0xE5, 0x83, 0x8E, 0xE5, 0x2C, 0x05, 0xF0, 0x70, 0x2B, 0xAE, 0x2C, ++ 0x14, 0x2B, 0x05, 0x02, 0x83, 0x8E, 0x82, 0xF5, 0x22, 0xF0, 0x31, 0xE5, 0x25, 0xEF, 0x2B, 0x8F, ++ 0xF5, 0xAC, 0x24, 0xE0, 0x00, 0x34, 0xE4, 0x82, 0xFE, 0xE0, 0x83, 0xF5, 0xAA, 0xFB, 0xE0, 0xA3, ++ 0x33, 0xEE, 0xFF, 0x06, 0xFC, 0xFD, 0xE0, 0x95, 0x07, 0xC0, 0x06, 0xC0, 0xE0, 0x95, 0x33, 0xEE, ++ 0x52, 0x8E, 0x53, 0x8F, 0x50, 0xF5, 0x51, 0xF5, 0x06, 0xD0, 0x07, 0xD0, 0x8F, 0x20, 0x21, 0x12, ++ 0x8D, 0x2E, 0x8E, 0x2F, 0xE5, 0x2C, 0x8C, 0x2D, 0x24, 0xE0, 0x25, 0x2B, 0xE4, 0x82, 0xF5, 0x00, ++ 0x83, 0xF5, 0x05, 0x34, 0xE0, 0xA3, 0xFA, 0xE0, 0x02, 0xAE, 0xFF, 0xFB, 0xE0, 0x95, 0x33, 0xEE, ++ 0x06, 0xC0, 0xFC, 0xFD, 0x33, 0xEE, 0x07, 0xC0, 0x53, 0x8F, 0xE0, 0x95, 0x51, 0xF5, 0x52, 0x8E, ++ 0x07, 0xD0, 0x50, 0xF5, 0x21, 0x12, 0x06, 0xD0, 0x2F, 0x2F, 0xE5, 0x20, 0x2E, 0xE5, 0x2F, 0xF5, ++ 0xE5, 0x2E, 0xF5, 0x3E, 0x2D, 0xF5, 0x3D, 0x2D, 0xF5, 0x3C, 0x2C, 0xE5, 0xAE, 0x2F, 0xAF, 0x2C, ++ 0xFC, 0x2D, 0xAD, 0x2E, 0x8F, 0x1F, 0x30, 0x75, 0x8D, 0x33, 0x8E, 0x34, 0xE5, 0x31, 0x8C, 0x32, ++ 0xFF, 0x32, 0x45, 0x31, 0x07, 0x42, 0x33, 0xE5, 0x07, 0x42, 0x34, 0xE5, 0x75, 0x09, 0x70, 0xEF, ++ 0x33, 0xF5, 0x01, 0x34, 0x31, 0xF5, 0x32, 0xF5, 0xE7, 0x20, 0x31, 0xE5, 0xAF, 0x30, 0x15, 0x17, ++ 0xAD, 0x33, 0xAE, 0x34, 0x12, 0x31, 0xAC, 0x32, 0x34, 0x8F, 0x86, 0x21, 0x32, 0x8D, 0x33, 0x8E, ++ 0xE4, 0x80, 0x31, 0x8C, 0x00, 0x7E, 0x31, 0xAF, 0x30, 0xE5, 0xFB, 0xE4, 0x30, 0xF5, 0xE0, 0x25, ++ 0x06, 0xAC, 0x07, 0xAD, 0xEE, 0x98, 0x02, 0x12, 0x05, 0x07, 0xE7, 0x30, 0x00, 0x7E, 0xFF, 0x30, ++ 0x78, 0xEF, 0x0B, 0x80, 0x13, 0xC3, 0xCE, 0x07, 0xF9, 0xD8, 0x13, 0xCE, 0x03, 0xBB, 0x0B, 0xFF, ++ 0xE4, 0x30, 0xAF, 0xD9, 0x75, 0xFE, 0xFD, 0xFC, 0x52, 0x75, 0xA8, 0x53, 0xF5, 0x51, 0xF5, 0xC0, ++ 0x20, 0x21, 0x12, 0x50, 0x33, 0x8E, 0x34, 0x8F, 0x31, 0x8C, 0x32, 0x8D, 0xF5, 0x34, 0x25, 0xE4, ++ 0x34, 0x33, 0xE5, 0x34, 0xE4, 0x33, 0xF5, 0x80, 0x32, 0xF5, 0x32, 0x35, 0xF5, 0x31, 0x35, 0xE4, ++ 0x22, 0x32, 0xAF, 0x31, 0xE4, 0xFF, 0x24, 0x75, 0x26, 0xF5, 0x25, 0xF5, 0x23, 0x75, 0x27, 0xF5, ++ 0x31, 0x23, 0xAF, 0x01, 0xE5, 0x28, 0x8F, 0xDC, 0x24, 0x95, 0xC3, 0x28, 0x28, 0x85, 0x03, 0x50, ++ 0xD3, 0x28, 0xE5, 0x24, 0x03, 0x40, 0x25, 0x95, 0xE5, 0x25, 0x28, 0x85, 0xF5, 0x27, 0x25, 0x28, ++ 0x26, 0x35, 0xE4, 0x27, 0x23, 0x05, 0x26, 0xF5, 0x94, 0xC3, 0x23, 0xE5, 0xE5, 0xD2, 0x40, 0x40, ++ 0xAF, 0x6A, 0xAE, 0x66, 0x8E, 0x09, 0x70, 0x6B, 0x75, 0x2A, 0x8F, 0x29, 0x19, 0x80, 0x07, 0x66, ++ 0xF5, 0x04, 0x24, 0xEF, 0xF5, 0x3E, 0xE4, 0x2A, 0x66, 0xF5, 0xE4, 0x29, 0x28, 0x74, 0x65, 0x05, ++ 0x6B, 0xF5, 0x6B, 0x25, 0xF5, 0x6A, 0x35, 0xE4, 0x31, 0xFF, 0xE4, 0x6A, 0xE5, 0x30, 0x8F, 0xDC, ++ 0x78, 0x26, 0xAE, 0x27, 0x13, 0xC3, 0xCE, 0x06, 0xF9, 0xD8, 0x13, 0xCE, 0xF5, 0xE4, 0x2F, 0xF5, ++ 0xAD, 0x24, 0xAB, 0x31, 0xAE, 0x2A, 0xAF, 0x25, 0x30, 0x81, 0x21, 0x29, 0x21, 0x12, 0x0B, 0x08, ++ 0x76, 0x72, 0x78, 0x94, 0x0E, 0x76, 0x08, 0x00, 0x12, 0x72, 0x7F, 0x22, 0x06, 0x50, 0xB2, 0x0B, ++ 0x75, 0x2E, 0x5B, 0x75, 0xE5, 0x22, 0x6B, 0x5C, 0x7B, 0x1D, 0x60, 0x71, 0x79, 0x20, 0x7A, 0xFF, ++ 0xF8, 0x03, 0x12, 0x1D, 0x75, 0x2C, 0x5B, 0x75, 0x08, 0xD2, 0x0C, 0x5C, 0xE0, 0xAD, 0x01, 0x90, ++ 0xE4, 0xF0, 0x08, 0x44, 0x8D, 0x03, 0x12, 0xFF, 0xE0, 0x12, 0x06, 0x90, 0x07, 0x54, 0x13, 0xC4, ++ 0x0E, 0x70, 0x07, 0x64, 0x20, 0xEF, 0x20, 0xAF, 0x20, 0xAF, 0x08, 0xE0, 0x30, 0x13, 0xC3, 0xEF, ++ 0x5B, 0x75, 0x06, 0xE0, 0x4E, 0x5C, 0x75, 0x2D, 0x5C, 0x65, 0x60, 0xE5, 0x5F, 0xE5, 0x04, 0x70, ++ 0x08, 0x60, 0x5B, 0x65, 0x85, 0x5F, 0x5B, 0x85, 0x08, 0xD2, 0x60, 0x5C, 0xE0, 0x13, 0x06, 0x90, ++ 0x5F, 0xAA, 0x62, 0xF5, 0x02, 0x12, 0x60, 0xA9, 0x22, 0x08, 0xC2, 0xFF, 0x54, 0xC4, 0x62, 0xE5, ++ 0xE5, 0x22, 0xF5, 0x07, 0xF5, 0x0F, 0x54, 0x62, 0xF5, 0x07, 0x90, 0x69, 0xE4, 0xF0, 0x03, 0x74, ++ 0xF0, 0xF9, 0x07, 0x90, 0x04, 0xF5, 0x07, 0x90, 0x5C, 0x08, 0x90, 0xF0, 0xE4, 0xF0, 0x03, 0x74, ++ 0xF0, 0x5F, 0x08, 0x90, 0xF0, 0x5E, 0x08, 0x90, 0xF0, 0x5D, 0x08, 0x90, 0x04, 0x60, 0x08, 0x90, ++ 0x5C, 0x08, 0x90, 0xF0, 0x0D, 0x90, 0xE4, 0xF0, 0x0D, 0x7E, 0xF0, 0x01, 0x0B, 0x12, 0x01, 0x7F, ++ 0x45, 0x0D, 0x90, 0xD1, 0x90, 0xF0, 0x80, 0x74, 0x90, 0xF0, 0x65, 0x0D, 0x90, 0xF0, 0x47, 0x0D, ++ 0x90, 0xF0, 0x67, 0x0D, 0xFF, 0x74, 0x89, 0x0D, 0x07, 0x90, 0xE4, 0xF0, 0x07, 0x90, 0xF0, 0xF1, ++ 0xF0, 0xFC, 0x74, 0xF2, 0x05, 0x60, 0x69, 0xE5, 0x01, 0xB4, 0x22, 0xE5, 0x35, 0x08, 0x90, 0x08, ++ 0x80, 0xF0, 0x19, 0x74, 0x35, 0x08, 0x90, 0x06, 0x90, 0xF0, 0x31, 0x74, 0x0B, 0x74, 0x3D, 0x08, ++ 0x90, 0x69, 0xE5, 0xF0, 0x06, 0x70, 0x3E, 0x08, 0xF0, 0x4C, 0x74, 0xE0, 0x74, 0xE0, 0x04, 0x80, ++ 0x08, 0x90, 0xF0, 0x2E, 0xF0, 0x09, 0x74, 0x3D, 0x74, 0x38, 0x08, 0x90, 0x05, 0x74, 0xF0, 0x07, ++ 0xFF, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x08, 0x74, 0x03, 0x74, 0xFE, 0x07, 0xFD, 0x07, 0x90, 0xF0, ++ 0x00, 0xF0, 0x07, 0x74, 0x00, 0x00, 0x00, 0x00, 0x74, 0xFE, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x02, ++ 0xF0, 0x06, 0x74, 0xFD, 0x74, 0x36, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x03, 0xF0, 0x14, 0x74, 0x37, ++ 0x74, 0x36, 0x08, 0x90, 0x07, 0x90, 0xF0, 0x01, 0xF9, 0x54, 0xE0, 0x6A, 0x6C, 0x07, 0x90, 0xF0, ++ 0x90, 0xF0, 0x01, 0x74, 0xE4, 0xE0, 0x6D, 0x07, 0x07, 0x90, 0xF0, 0x04, 0xFF, 0x74, 0xE0, 0x6E, ++ 0x6F, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0xE4, 0xE0, 0xE4, 0xE0, 0x70, 0x07, 0xF5, 0x65, 0xF5, 0xF0, ++ 0x01, 0x67, 0x75, 0x66, 0x6A, 0x75, 0x68, 0xF5, 0x00, 0x6B, 0x75, 0x00, 0xFE, 0x24, 0x22, 0xE5, ++ 0x70, 0x04, 0x0A, 0x60, 0x26, 0x5B, 0x75, 0x0E, 0x22, 0xC2, 0x5C, 0x75, 0x75, 0x27, 0x5B, 0x75, ++ 0x75, 0x22, 0xE8, 0x5C, 0x5C, 0x75, 0x2D, 0x5B, 0x08, 0x30, 0x22, 0x6C, 0x7A, 0xFF, 0x7B, 0x10, ++ 0x12, 0x25, 0x79, 0x20, 0x07, 0x90, 0xF8, 0x03, 0x10, 0x44, 0xE0, 0x07, 0xFF, 0x7B, 0x22, 0xF0, ++ 0x2C, 0x79, 0x20, 0x7A, 0x90, 0xF8, 0x03, 0x12, 0x54, 0xE0, 0xAD, 0x01, 0x20, 0xAF, 0xF0, 0xF7, ++ 0xF5, 0xEF, 0x54, 0xEF, 0x01, 0x5D, 0x75, 0x20, 0x22, 0xC5, 0x5E, 0x75, 0x20, 0x7A, 0xFF, 0x7B, ++ 0x03, 0x12, 0x43, 0x79, 0x22, 0x5B, 0x75, 0xF8, 0x22, 0x24, 0x5C, 0x75, 0x20, 0x7A, 0xFF, 0x7B, ++ 0x03, 0x12, 0x49, 0x79, 0x00, 0x6A, 0x75, 0xF8, 0xE4, 0x00, 0x6B, 0x75, 0x67, 0x75, 0x65, 0xF5, ++ 0x75, 0x66, 0xF5, 0x01, 0x5C, 0x75, 0x22, 0x5B, 0xBC, 0xB1, 0x22, 0x4E, 0x94, 0xD3, 0x65, 0xE5, ++ 0x75, 0x07, 0x40, 0x03, 0x5C, 0x75, 0x2E, 0x5B, 0x62, 0xE5, 0x22, 0x52, 0x30, 0x06, 0xE7, 0x30, ++ 0x80, 0x00, 0x03, 0x0B, 0x21, 0x5B, 0x75, 0xFA, 0x22, 0xDF, 0x5C, 0x75, 0xE0, 0x46, 0x08, 0x90, ++ 0x62, 0xE5, 0x23, 0xF5, 0x7B, 0x0E, 0xE7, 0x30, 0x79, 0x20, 0x7A, 0xFF, 0xFD, 0x23, 0xE5, 0x55, ++ 0x0C, 0x12, 0x00, 0x7C, 0xE5, 0x64, 0x05, 0xE5, 0x70, 0x63, 0xAE, 0x64, 0x14, 0x63, 0x05, 0x02, ++ 0x83, 0x8E, 0x82, 0xF5, 0xE5, 0xF0, 0x23, 0xE5, 0xF5, 0x07, 0x70, 0x69, 0x14, 0x25, 0x75, 0x24, ++ 0x24, 0x75, 0x06, 0x80, 0x0C, 0x25, 0x75, 0x00, 0x1F, 0x70, 0x66, 0xE5, 0x05, 0x07, 0x66, 0x75, ++ 0x25, 0x28, 0x74, 0x65, 0xE4, 0x6B, 0xF5, 0x6B, 0x6A, 0xF5, 0x6A, 0x35, 0x6B, 0xAF, 0x6A, 0xAE, ++ 0xF5, 0x08, 0x24, 0xEF, 0xF5, 0x3E, 0xE4, 0x64, 0x15, 0x30, 0x80, 0x63, 0x3E, 0x08, 0x90, 0x66, ++ 0x00, 0x7E, 0xFF, 0xE0, 0xA1, 0x7D, 0x00, 0x7C, 0x8E, 0x98, 0x02, 0x12, 0x74, 0x25, 0x8F, 0x24, ++ 0xF5, 0x25, 0x25, 0x40, 0x24, 0x35, 0xE4, 0x25, 0x25, 0xE5, 0x24, 0xF5, 0x07, 0x78, 0x24, 0xAE, ++ 0xCE, 0x13, 0xC3, 0xCE, 0xF5, 0xF9, 0xD8, 0x13, 0x90, 0x24, 0x8E, 0x25, 0x25, 0xE5, 0x3E, 0x08, ++ 0xFF, 0x7B, 0x22, 0xF0, 0x5D, 0x79, 0x20, 0x7A, 0x75, 0xF8, 0x03, 0x12, 0x6B, 0x75, 0x00, 0x6A, ++ 0x65, 0xF5, 0xE4, 0x00, 0x75, 0x2B, 0x5B, 0x75, 0xAE, 0x22, 0x8B, 0x5C, 0x8F, 0x6B, 0xAF, 0x6A, ++ 0xEF, 0x83, 0x8E, 0x82, 0x82, 0xF5, 0x1F, 0x24, 0x83, 0xF5, 0x3E, 0xE4, 0xAE, 0xF0, 0x4D, 0x74, ++ 0x8F, 0x6B, 0xAF, 0x6A, 0xEF, 0x83, 0x8E, 0x82, 0x82, 0xF5, 0x20, 0x24, 0x83, 0xF5, 0x3E, 0xE4, ++ 0xAE, 0xF0, 0x4D, 0x74, 0x8F, 0x6B, 0xAF, 0x6A, 0xEF, 0x83, 0x8E, 0x82, 0x82, 0xF5, 0x21, 0x24, ++ 0x83, 0xF5, 0x3E, 0xE4, 0xAE, 0xF0, 0x4D, 0x74, 0x8F, 0x6B, 0xAF, 0x6A, 0xEF, 0x83, 0x8E, 0x82, ++ 0x82, 0xF5, 0x22, 0x24, 0x83, 0xF5, 0x3E, 0xE4, 0xAE, 0xF0, 0x4D, 0x74, 0x8F, 0x6B, 0xAF, 0x6A, ++ 0xEF, 0x83, 0x8E, 0x82, 0x82, 0xF5, 0x23, 0x24, 0x83, 0xF5, 0x3E, 0xE4, 0xE5, 0xF0, 0x4D, 0x74, ++ 0x1F, 0x03, 0xB4, 0x65, 0xE0, 0x89, 0x0D, 0x90, 0xF0, 0x24, 0x00, 0x90, 0xE0, 0x8A, 0x0D, 0x90, ++ 0xF0, 0x25, 0x00, 0x90, 0xE0, 0x8B, 0x0D, 0x90, 0xF0, 0x26, 0x00, 0x90, 0x75, 0x2D, 0x5B, 0x75, ++ 0x05, 0x22, 0x3A, 0x5C, 0x25, 0x28, 0x74, 0x65, 0xE4, 0x6B, 0xF5, 0x6B, 0x6A, 0xF5, 0x6A, 0x35, ++ 0xD5, 0x09, 0x90, 0x22, 0xE4, 0x68, 0x60, 0xE0, 0x90, 0xF6, 0x75, 0x78, 0x18, 0xE0, 0x41, 0x08, ++ 0x02, 0x60, 0xE6, 0xF6, 0x74, 0x78, 0x06, 0x08, 0x41, 0x08, 0x90, 0xE6, 0xA6, 0x08, 0x90, 0xF0, ++ 0x60, 0xE6, 0xF6, 0xE0, 0x78, 0x06, 0x08, 0x02, 0x08, 0x90, 0xE6, 0x74, 0x09, 0x90, 0xF0, 0xA6, ++ 0xE6, 0xF6, 0xE0, 0x0B, 0x06, 0x08, 0x02, 0x60, 0x90, 0xE6, 0x74, 0x78, 0x90, 0xF0, 0x0B, 0x09, ++ 0xF6, 0xE0, 0x70, 0x09, 0x08, 0x02, 0x60, 0xE6, 0xE6, 0x74, 0x78, 0x06, 0xF0, 0x70, 0x09, 0x90, ++ 0xE6, 0x77, 0x78, 0xC3, 0xE6, 0x18, 0xFC, 0x94, 0x0C, 0x50, 0xFF, 0x94, 0x77, 0x78, 0xE6, 0x18, ++ 0xE4, 0x18, 0xF6, 0x26, 0x07, 0x80, 0xF6, 0x36, 0x76, 0x78, 0xFF, 0x74, 0xD3, 0xF6, 0x08, 0xF6, ++ 0x94, 0xE6, 0x79, 0x78, 0x94, 0xE6, 0x18, 0x00, 0x08, 0x08, 0x40, 0x00, 0x70, 0x18, 0x16, 0xE6, ++ 0x78, 0x22, 0x16, 0x01, 0x00, 0x90, 0xE6, 0x76, 0xE6, 0x08, 0xF0, 0x27, 0xF0, 0x4F, 0x00, 0x90, ++ 0x75, 0x2D, 0x5B, 0x75, 0x22, 0x22, 0x3A, 0x5C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x73, 0x65, 0x54, 0x09, 0x09, 0x00, 0x0A, 0x74, 0x74, 0x65, 0x53, 0x09, 0x00, 0x0A, 0x70, 0x75, ++ 0x42, 0x4C, 0x09, 0x09, 0x09, 0x09, 0x00, 0x0A, 0x4C, 0x4F, 0x43, 0x09, 0x0A, 0x64, 0x25, 0x3D, ++ 0x47, 0x09, 0x09, 0x00, 0x00, 0x0A, 0x45, 0x42, 0x69, 0x78, 0x45, 0x09, 0x01, 0x00, 0x0A, 0x74, ++ 0x4F, 0x4D, 0x41, 0x09, 0x53, 0x4E, 0x20, 0x4E, 0x08, 0x20, 0x00, 0x0A, 0x7B, 0x2F, 0x21, 0x02, ++ 0x79, 0x20, 0x7A, 0xFF, 0xF8, 0x03, 0x12, 0x10, 0xE0, 0x00, 0x06, 0x90, 0x78, 0xE0, 0xA3, 0xFE, ++ 0x13, 0xC3, 0xCE, 0x06, 0xF9, 0xD8, 0x13, 0xCE, 0xE0, 0x25, 0x01, 0x54, 0x00, 0x06, 0x90, 0xFD, ++ 0x54, 0x13, 0xC4, 0xE0, 0x03, 0x54, 0x4D, 0x01, 0x31, 0x06, 0x90, 0xFF, 0x4F, 0xFC, 0x54, 0xE0, ++ 0x75, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x31, 0x06, 0x90, 0x90, 0xFF, 0x03, 0x54, ++ 0x54, 0xE0, 0x76, 0x07, 0x90, 0xF0, 0x4F, 0xF8, 0x44, 0xE0, 0x8E, 0x07, 0x07, 0x90, 0xF0, 0x01, ++ 0x01, 0x44, 0xE0, 0x8F, 0x90, 0x07, 0x90, 0xF0, 0x44, 0xF0, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x02, ++ 0xFE, 0x54, 0xE0, 0x8F, 0x92, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x93, 0x07, 0x90, ++ 0x90, 0xF0, 0x01, 0x44, 0x54, 0xE0, 0x94, 0x07, 0xF0, 0x02, 0x44, 0xF0, 0xE0, 0x93, 0x07, 0x90, ++ 0x90, 0xF0, 0xFE, 0x54, 0x44, 0xE0, 0x79, 0x07, 0x0C, 0xD2, 0xF0, 0x03, 0x90, 0x0B, 0x02, 0x12, ++ 0x44, 0xE0, 0xBE, 0x07, 0x06, 0x90, 0xF0, 0x01, 0x03, 0x54, 0xE0, 0x31, 0xBF, 0x07, 0x90, 0xFF, ++ 0x4F, 0xF8, 0x54, 0xE0, 0xD7, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0xD8, 0x07, 0x90, ++ 0x90, 0xF0, 0x01, 0x44, 0x54, 0xE0, 0xD9, 0x07, 0xF0, 0x02, 0x44, 0xF0, 0xE0, 0xD8, 0x07, 0x90, ++ 0x90, 0xF0, 0xFE, 0x54, 0x44, 0xE0, 0xDB, 0x07, 0x07, 0x90, 0xF0, 0x01, 0x01, 0x44, 0xE0, 0xDC, ++ 0xDD, 0x07, 0x90, 0xF0, 0x44, 0xF0, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x02, 0xFE, 0x54, 0xE0, 0xDC, ++ 0xC2, 0x07, 0x90, 0xF0, 0xF0, 0x03, 0x44, 0xE0, 0xE0, 0x03, 0x06, 0x90, 0x90, 0xF0, 0x04, 0x44, ++ 0x54, 0xE0, 0x7A, 0x07, 0x06, 0x90, 0xFF, 0x01, 0xC4, 0xFE, 0xE0, 0x01, 0x54, 0x13, 0x13, 0x13, ++ 0x29, 0x60, 0x6F, 0x01, 0x20, 0x7A, 0xFF, 0x7B, 0xFF, 0xE0, 0x16, 0x79, 0x13, 0x13, 0x13, 0xC4, ++ 0x7C, 0xFD, 0x01, 0x54, 0xE5, 0x0C, 0x12, 0x00, 0xE0, 0x01, 0x06, 0x90, 0x13, 0xC4, 0x80, 0x54, ++ 0x01, 0x54, 0x13, 0x13, 0x7A, 0x07, 0x90, 0xFF, 0x4F, 0xFE, 0x54, 0xE0, 0x00, 0x06, 0x90, 0xF0, ++ 0x13, 0x13, 0xC4, 0xE0, 0xE0, 0x20, 0x03, 0x54, 0x13, 0x13, 0xE0, 0x2B, 0xE0, 0x20, 0x3F, 0x54, ++ 0xC4, 0xE0, 0xA3, 0x23, 0x54, 0x13, 0x13, 0x13, 0x18, 0xE0, 0x20, 0x01, 0xE0, 0x79, 0x07, 0x90, ++ 0xE0, 0xF0, 0xFC, 0x54, 0x90, 0xF0, 0xFC, 0x54, 0x54, 0xE0, 0x03, 0x06, 0x5B, 0x75, 0xF0, 0xFB, ++ 0x3C, 0x5C, 0x75, 0x24, 0x60, 0x71, 0xE5, 0x22, 0x7A, 0xFF, 0x7B, 0x18, 0x12, 0x00, 0x79, 0x20, ++ 0x5B, 0x75, 0xF8, 0x03, 0x24, 0x5C, 0x75, 0x22, 0x01, 0x90, 0x08, 0xD2, 0x20, 0x44, 0xE0, 0xAD, ++ 0xEF, 0x20, 0xAF, 0xF0, 0xAF, 0x39, 0xE0, 0x20, 0x13, 0xC3, 0xEF, 0x20, 0x90, 0x31, 0xE0, 0x20, ++ 0xFE, 0xE0, 0x00, 0x06, 0x07, 0x78, 0xE0, 0xA3, 0xCE, 0x13, 0xC3, 0xCE, 0x20, 0xF9, 0xD8, 0x13, ++ 0x06, 0x90, 0x24, 0xE0, 0x13, 0xC4, 0xE0, 0x00, 0x20, 0x03, 0x54, 0x13, 0x13, 0xE0, 0x18, 0xE0, ++ 0x20, 0x3F, 0x54, 0x13, 0x06, 0x90, 0x10, 0xE0, 0x13, 0xC4, 0xE0, 0x12, 0x06, 0x70, 0x07, 0x54, ++ 0x75, 0x24, 0x5B, 0x75, 0x60, 0xE5, 0x3C, 0x5C, 0x04, 0x70, 0x5C, 0x65, 0x5B, 0x65, 0x5F, 0xE5, ++ 0x5B, 0x85, 0x08, 0x60, 0x60, 0x5C, 0x85, 0x5F, 0x5F, 0xAA, 0x08, 0xD2, 0x02, 0x12, 0x60, 0xA9, ++ 0x22, 0x08, 0xC2, 0xFF, 0x7B, 0x09, 0x08, 0x30, 0x79, 0x20, 0x7A, 0xFF, 0xF8, 0x03, 0x12, 0x07, ++ 0xE0, 0x00, 0x06, 0x90, 0x54, 0x13, 0x13, 0xC4, 0x13, 0xE0, 0x20, 0x03, 0x54, 0x13, 0x13, 0xE0, ++ 0x0B, 0xE0, 0x20, 0x3F, 0x13, 0xC4, 0xE0, 0xA3, 0x01, 0x54, 0x13, 0x13, 0x75, 0x07, 0xE0, 0x30, ++ 0x5C, 0x75, 0x20, 0x5B, 0x5B, 0x75, 0x22, 0x3A, 0x5D, 0x5C, 0x75, 0x22, 0x09, 0x08, 0x30, 0x22, ++ 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x21, 0x79, 0x12, 0x06, 0x90, 0xF8, 0x54, 0x13, 0xC4, 0xE0, ++ 0x94, 0xD3, 0xFF, 0x07, 0xE4, 0x02, 0x40, 0x04, 0x94, 0xD3, 0xEF, 0xFF, 0x1F, 0x01, 0x40, 0x02, ++ 0xE0, 0xB5, 0x07, 0x90, 0x60, 0x6F, 0x03, 0x54, 0x90, 0x9C, 0x51, 0x02, 0xC4, 0xE0, 0x12, 0x06, ++ 0x70, 0x07, 0x54, 0x13, 0x24, 0x5B, 0x75, 0x06, 0x22, 0x3C, 0x5C, 0x75, 0x07, 0x90, 0x07, 0xAD, ++ 0xFE, 0x54, 0xE0, 0x96, 0xFD, 0x54, 0xE0, 0xF0, 0x75, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, ++ 0xE0, 0xAE, 0x07, 0x90, 0x90, 0xF0, 0x02, 0x44, 0x54, 0xE0, 0xB0, 0x07, 0x54, 0xE0, 0xF0, 0xFC, ++ 0xF0, 0x08, 0x44, 0xF3, 0x44, 0xCF, 0x54, 0xE0, 0x44, 0xE0, 0xF0, 0x10, 0x07, 0x90, 0xF0, 0xC0, ++ 0x02, 0x44, 0xE0, 0xAF, 0xFD, 0x54, 0xE0, 0xF0, 0x76, 0x07, 0x90, 0xF0, 0x44, 0xF8, 0x54, 0xE0, ++ 0x54, 0xED, 0xF0, 0x02, 0x07, 0x90, 0xFF, 0x03, 0xFC, 0x54, 0xE0, 0xB5, 0x07, 0x90, 0xF0, 0x4F, ++ 0x01, 0x44, 0xE0, 0x8E, 0x90, 0x07, 0x90, 0xF0, 0x44, 0xF0, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x03, ++ 0xFC, 0x54, 0xE0, 0xF1, 0xF3, 0x54, 0xE0, 0xF0, 0xE0, 0xF0, 0x04, 0x44, 0x20, 0x44, 0xCF, 0x54, ++ 0xC0, 0x44, 0xE0, 0xF0, 0x00, 0x0D, 0x90, 0xF0, 0xF0, 0xF8, 0x54, 0xE0, 0x44, 0x9F, 0x54, 0xE0, ++ 0x44, 0xE0, 0xF0, 0x20, 0x90, 0xE0, 0xF0, 0x18, 0x90, 0xF0, 0x20, 0x0D, 0x90, 0xE0, 0x00, 0x0D, ++ 0x90, 0xF0, 0x40, 0x0D, 0x90, 0xE0, 0x00, 0x0D, 0x90, 0xF0, 0x60, 0x0D, 0x59, 0x74, 0x0C, 0x0D, ++ 0x2C, 0x0D, 0x90, 0xF0, 0x4C, 0x0D, 0x90, 0xF0, 0x6C, 0x0D, 0x90, 0xF0, 0x01, 0x0D, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0x04, 0x44, 0xE0, 0xF0, 0xEF, 0x54, 0xE0, ++ 0xF0, 0xDF, 0x54, 0xE0, 0x21, 0x0D, 0x90, 0xE0, 0x01, 0x0D, 0x90, 0xF0, 0x41, 0x0D, 0x90, 0xE0, ++ 0x01, 0x0D, 0x90, 0xF0, 0x61, 0x0D, 0x90, 0xE0, 0x82, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0xAA, 0x74, ++ 0x44, 0xE0, 0xF5, 0x07, 0x07, 0x90, 0xF0, 0x01, 0xF8, 0x54, 0xE0, 0xF9, 0xE0, 0xF0, 0x04, 0x44, ++ 0x40, 0x44, 0x8F, 0x54, 0xFA, 0x07, 0x90, 0xF0, 0x44, 0xF8, 0x54, 0xE0, 0x54, 0xE0, 0xF0, 0x04, ++ 0xF0, 0x40, 0x44, 0x8F, 0xE0, 0xFD, 0x09, 0x90, 0xE4, 0xF0, 0x01, 0x44, 0xF0, 0x00, 0x0A, 0x90, ++ 0xF0, 0xFF, 0x09, 0x90, 0xF0, 0xFE, 0x09, 0x90, 0x04, 0x01, 0x0A, 0x90, 0x93, 0x09, 0x90, 0xF0, ++ 0xF0, 0xFD, 0x54, 0xE0, 0xE0, 0x92, 0x09, 0x90, 0xE0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, ++ 0x00, 0xF0, 0xF7, 0x54, 0x00, 0x00, 0x00, 0x00, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0xC7, 0x09, 0x90, ++ 0xE0, 0xF0, 0xFE, 0x54, 0xE0, 0xF0, 0xFD, 0x54, 0x90, 0xF0, 0x04, 0x44, 0x44, 0xE0, 0xCE, 0x09, ++ 0x44, 0xE0, 0xF0, 0x01, 0x09, 0x90, 0xF0, 0x02, 0x01, 0x44, 0xE0, 0xCF, 0xFB, 0x54, 0xE0, 0xF0, ++ 0xF7, 0x54, 0xE0, 0xF0, 0xD0, 0x09, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x04, 0x44, 0xE0, ++ 0xE0, 0xD1, 0x09, 0x90, 0xE0, 0xF0, 0x01, 0x44, 0x90, 0xF0, 0x08, 0x44, 0x90, 0xE0, 0xA8, 0x00, ++ 0x90, 0xF0, 0x3E, 0x08, 0x90, 0xE0, 0xA9, 0x00, 0x90, 0xF0, 0xA3, 0x08, 0x90, 0xE0, 0xAA, 0x00, ++ 0x90, 0xF0, 0x08, 0x09, 0x90, 0xE0, 0xAB, 0x00, 0x22, 0xF0, 0x6D, 0x09, 0x20, 0x7A, 0xFF, 0x7B, ++ 0x03, 0x12, 0x28, 0x79, 0xAD, 0x01, 0x90, 0xF8, 0xF0, 0xDF, 0x54, 0xE0, 0x54, 0xEF, 0x20, 0xAF, ++ 0x75, 0x20, 0xF5, 0xEF, 0x5E, 0x75, 0x01, 0x5D, 0xFF, 0x7B, 0x22, 0xC5, 0x30, 0x79, 0x20, 0x7A, ++ 0x22, 0xF8, 0x03, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x42, 0x30, 0x31, 0x09, 0x09, 0x00, 0x0A, 0x54, 0x75, 0x74, 0x65, 0x53, 0x09, 0x00, 0x0A, 0x70, ++ 0x6B, 0x6E, 0x69, 0x4C, 0x0A, 0x70, 0x55, 0x2D, 0x4C, 0x09, 0x09, 0x00, 0x2D, 0x6B, 0x6E, 0x69, ++ 0x73, 0x73, 0x6F, 0x4C, 0x4C, 0x09, 0x00, 0x0A, 0x2D, 0x6B, 0x6E, 0x69, 0x6E, 0x77, 0x6F, 0x44, ++ 0x09, 0x09, 0x00, 0x0A, 0x00, 0x49, 0x44, 0x4D, 0x00, 0x0A, 0x00, 0x58, 0x69, 0x78, 0x45, 0x09, ++ 0x01, 0x00, 0x0A, 0x74, 0x0D, 0x60, 0x71, 0xE5, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x00, 0x79, ++ 0xD2, 0xDC, 0x11, 0xF8, 0xEF, 0x20, 0xAF, 0x08, 0x20, 0x0F, 0x54, 0xC4, 0x20, 0xAF, 0x22, 0xE0, ++ 0x1C, 0xE0, 0x20, 0xEF, 0xC3, 0xEF, 0x20, 0xAF, 0x14, 0xE0, 0x20, 0x13, 0xC4, 0xEF, 0x20, 0xAF, ++ 0x20, 0x07, 0x54, 0x13, 0x20, 0xAF, 0x0A, 0xE0, 0x54, 0x13, 0x13, 0xEF, 0x1E, 0xE0, 0x30, 0x3F, ++ 0xCD, 0x7F, 0x26, 0x7E, 0x70, 0x60, 0x65, 0xEF, 0x5F, 0x65, 0xEE, 0x03, 0xE2, 0x74, 0x10, 0x60, ++ 0x04, 0x70, 0x60, 0x65, 0x5F, 0x65, 0x26, 0x74, 0x5B, 0x8E, 0x04, 0x60, 0x60, 0xE5, 0x5C, 0x8F, ++ 0x04, 0x70, 0x5C, 0x65, 0x5B, 0x65, 0x5F, 0xE5, 0x5B, 0x85, 0x08, 0x60, 0x60, 0x5C, 0x85, 0x5F, ++ 0x5F, 0xAA, 0x08, 0xD2, 0x02, 0x12, 0x60, 0xA9, 0x78, 0x08, 0xC2, 0xFF, 0x01, 0x54, 0xE6, 0x79, ++ 0x9F, 0xE4, 0xC3, 0xFF, 0x00, 0x94, 0x08, 0x74, 0x18, 0xFC, 0x05, 0x54, 0xFE, 0x13, 0xC3, 0xE6, ++ 0xFF, 0x13, 0xE6, 0x08, 0xF6, 0x18, 0x6C, 0xEE, 0x22, 0xF6, 0x08, 0xEF, 0x20, 0x7A, 0xFF, 0x7B, ++ 0x03, 0x12, 0x07, 0x79, 0x43, 0x20, 0x90, 0xF8, 0x02, 0x60, 0x93, 0xE4, 0x0A, 0x71, 0x09, 0xC2, ++ 0x90, 0x7F, 0x03, 0x12, 0xFF, 0xE0, 0x8A, 0x0D, 0xE0, 0x8B, 0x0D, 0x90, 0x07, 0x90, 0xFF, 0x6F, ++ 0xE4, 0xFD, 0xE0, 0x0B, 0xEF, 0xF6, 0x78, 0x78, 0x90, 0xF6, 0x08, 0x6D, 0x29, 0x31, 0x23, 0x06, ++ 0x74, 0xF3, 0x07, 0x90, 0x78, 0xE4, 0xF0, 0x0D, 0xF6, 0x08, 0xF6, 0x72, 0x08, 0xAA, 0x76, 0x08, ++ 0x5B, 0x75, 0xE6, 0x76, 0xFE, 0x5C, 0x75, 0x21, 0x13, 0xFF, 0xE0, 0x22, 0x13, 0x3F, 0x54, 0x13, ++ 0x06, 0x90, 0x0C, 0x92, 0xE0, 0x30, 0xE0, 0x27, 0x1A, 0x0C, 0x30, 0x03, 0xE0, 0x27, 0x06, 0x90, ++ 0x90, 0x55, 0xE0, 0x20, 0xFE, 0xE0, 0x26, 0x06, 0x02, 0x78, 0xE0, 0xA3, 0xCE, 0x13, 0xC3, 0xCE, ++ 0x20, 0xF9, 0xD8, 0x13, 0x0C, 0xC2, 0x42, 0xE0, 0x74, 0x01, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x0F, ++ 0x90, 0xF0, 0x04, 0x21, 0x54, 0xE0, 0x00, 0x0D, 0x0D, 0x90, 0xF0, 0x9F, 0x9F, 0x54, 0xE0, 0x20, ++ 0x90, 0xF0, 0x20, 0x44, 0x13, 0xE0, 0x8B, 0x0D, 0x24, 0x01, 0x54, 0x13, 0x0C, 0x0D, 0x90, 0x22, ++ 0x2C, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x12, 0x74, 0xE4, 0x74, 0xF1, 0x07, 0xF2, 0x07, 0x90, 0xF0, ++ 0x90, 0xF0, 0xB1, 0x74, 0x40, 0x80, 0xA4, 0x00, 0x0D, 0x90, 0x0C, 0xD2, 0xF0, 0x0F, 0x74, 0x21, ++ 0x04, 0x01, 0x0D, 0x90, 0x00, 0x0D, 0x90, 0xF0, 0x44, 0x9F, 0x54, 0xE0, 0x0D, 0x90, 0xF0, 0x20, ++ 0x9F, 0x54, 0xE0, 0x20, 0x0C, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x12, 0x74, 0x13, 0xE0, 0x8B, 0x0D, ++ 0x24, 0x01, 0x54, 0x13, 0x2C, 0x0D, 0x90, 0x22, 0xF1, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0xB1, 0x74, ++ 0xE4, 0x74, 0xF2, 0x07, 0xA5, 0x00, 0x90, 0xF0, 0x3E, 0x08, 0x90, 0xE0, 0xE4, 0x0C, 0xA2, 0xF0, ++ 0xFC, 0x01, 0x54, 0x33, 0xE0, 0x25, 0xE0, 0x25, 0x23, 0x06, 0x90, 0xFE, 0x4E, 0xFB, 0x54, 0xE0, ++ 0x33, 0x33, 0xEC, 0xF0, 0xFF, 0xF8, 0x54, 0x33, 0x4F, 0xF7, 0x54, 0xE0, 0x08, 0x30, 0x22, 0xF0, ++ 0x7A, 0xFF, 0x7B, 0x25, 0x12, 0x26, 0x79, 0x20, 0x76, 0x78, 0xF8, 0x03, 0x76, 0x08, 0xF4, 0x76, ++ 0x8F, 0x07, 0x90, 0x24, 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x93, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, ++ 0x44, 0xE0, 0x8B, 0x07, 0x06, 0x90, 0xF0, 0x02, 0x54, 0xC4, 0xE0, 0x00, 0x1B, 0xE0, 0x30, 0x0F, ++ 0xE6, 0x75, 0x78, 0xD3, 0xE6, 0x18, 0x00, 0x94, 0x09, 0x40, 0x00, 0x94, 0x18, 0x16, 0xE6, 0x08, ++ 0x80, 0x16, 0x01, 0x70, 0x26, 0x5B, 0x75, 0x06, 0x90, 0xCD, 0x5C, 0x75, 0x54, 0xE0, 0xA0, 0x07, ++ 0x60, 0x01, 0x64, 0x07, 0x8B, 0x07, 0x90, 0x09, 0x30, 0x13, 0xC3, 0xE0, 0x07, 0x90, 0x1D, 0xE0, ++ 0x13, 0xC3, 0xE0, 0x8B, 0xE0, 0x30, 0x72, 0x78, 0x08, 0x13, 0x76, 0x07, 0x05, 0x80, 0x88, 0x76, ++ 0x76, 0x08, 0x09, 0x76, 0x25, 0x5B, 0x75, 0xC4, 0x90, 0x6A, 0x5C, 0x75, 0xC4, 0xE0, 0x00, 0x06, ++ 0xE0, 0x30, 0x0F, 0x54, 0x23, 0x06, 0x90, 0x05, 0x06, 0x90, 0x07, 0x80, 0xE0, 0x20, 0xE0, 0x27, ++ 0x78, 0x29, 0x31, 0x0A, 0x08, 0xF4, 0x76, 0x76, 0xD3, 0x22, 0x24, 0x76, 0x94, 0xE6, 0x77, 0x78, ++ 0x94, 0xE6, 0x18, 0x00, 0x08, 0x08, 0x40, 0x00, 0x70, 0x18, 0x16, 0xE6, 0x78, 0x22, 0x16, 0x01, ++ 0x08, 0xF4, 0x76, 0x76, 0x07, 0x90, 0x24, 0x76, 0x07, 0x54, 0xE0, 0xA0, 0x79, 0x78, 0x4B, 0x70, ++ 0xFF, 0x01, 0x54, 0xE6, 0xE0, 0x23, 0x06, 0x90, 0x54, 0x13, 0x13, 0xFD, 0x01, 0x70, 0x6F, 0x01, ++ 0x90, 0x07, 0x60, 0xE4, 0x44, 0xE0, 0x35, 0x06, 0x79, 0x78, 0xF0, 0x08, 0x0C, 0x92, 0x13, 0xE6, ++ 0xFF, 0x7B, 0x32, 0x31, 0x32, 0x79, 0x20, 0x7A, 0x90, 0xF8, 0x03, 0x12, 0xFF, 0xE0, 0x23, 0x06, ++ 0x3F, 0x54, 0x13, 0x13, 0x7B, 0x09, 0xE0, 0x30, 0x79, 0x20, 0x7A, 0xFF, 0xF8, 0x03, 0x12, 0x38, ++ 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x3A, 0x79, 0x90, 0xE4, 0x22, 0xF8, 0x90, 0xF0, 0x01, 0x0D, ++ 0x90, 0xF0, 0x21, 0x0D, 0xFF, 0x74, 0x41, 0x0D, 0x61, 0x0D, 0x90, 0xF0, 0x00, 0x0D, 0x90, 0xF0, ++ 0xF0, 0xF8, 0x54, 0xE0, 0xF0, 0x18, 0x44, 0xE0, 0x20, 0x0D, 0x90, 0xE0, 0x0A, 0x0D, 0x90, 0xF0, ++ 0x90, 0xF0, 0x49, 0x74, 0x90, 0xF0, 0x2A, 0x0D, 0x5C, 0x74, 0x06, 0x0D, 0x26, 0x0D, 0x90, 0xF0, ++ 0x82, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0xAA, 0x74, 0x11, 0x74, 0x0C, 0x0D, 0x2C, 0x0D, 0x90, 0xF0, ++ 0x02, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x30, 0x74, 0x90, 0xF0, 0x22, 0x0D, 0x20, 0x74, 0x05, 0x0D, ++ 0x25, 0x0D, 0x90, 0xF0, 0xF0, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x44, 0xE0, 0xF5, 0x07, ++ 0x44, 0xE0, 0xF0, 0x01, 0x54, 0xE0, 0xF0, 0x02, 0x07, 0x90, 0xF0, 0xFD, 0xF8, 0x54, 0xE0, 0xF9, ++ 0x90, 0xF0, 0x04, 0x44, 0x44, 0xE0, 0xFD, 0x09, 0x44, 0xE0, 0xF0, 0x01, 0x54, 0xE0, 0xF0, 0x02, ++ 0x0A, 0x90, 0xF0, 0xFD, 0xF0, 0xAB, 0x74, 0x00, 0x14, 0xFF, 0x09, 0x90, 0xFE, 0x09, 0x90, 0xF0, ++ 0x90, 0xF0, 0x0A, 0x74, 0x01, 0x74, 0x01, 0x0A, 0x55, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, ++ 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xE0, 0x56, 0x08, 0x90, 0xE0, 0xF0, 0xF0, 0x54, ++ 0x90, 0xF0, 0x30, 0x44, 0x54, 0xE0, 0x57, 0x08, 0xF0, 0x06, 0x44, 0xF8, 0xE0, 0x58, 0x08, 0x90, ++ 0x90, 0xF0, 0xFA, 0x74, 0x44, 0xE0, 0x5C, 0x08, 0x08, 0x90, 0xF0, 0x01, 0xF0, 0xAB, 0x74, 0x5F, ++ 0x14, 0x5E, 0x08, 0x90, 0x5D, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x0A, 0x74, 0x01, 0x74, 0x60, 0x08, ++ 0xFF, 0x07, 0x90, 0xF0, 0xF0, 0xFD, 0x54, 0xE0, 0xE0, 0xFE, 0x07, 0x90, 0xE0, 0xF0, 0x01, 0x44, ++ 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xF7, 0x54, 0x90, 0xF0, 0xFB, 0x54, 0x44, 0xE0, 0xFD, 0x07, ++ 0x44, 0xE0, 0xF0, 0x01, 0x54, 0xE0, 0xF0, 0x02, 0x00, 0x00, 0xF0, 0xF7, 0x90, 0x00, 0x00, 0x00, ++ 0x54, 0xE0, 0xFE, 0x07, 0x07, 0x90, 0xF0, 0xFE, 0xFE, 0x54, 0xE0, 0xFD, 0x33, 0x08, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x34, 0x08, 0x90, 0x90, 0xF0, 0xFE, 0x54, 0x44, 0xE0, 0x3A, 0x08, ++ 0x08, 0x90, 0xF0, 0x01, 0x01, 0x44, 0xE0, 0x3B, 0x08, 0x44, 0xE0, 0xF0, 0x3C, 0x08, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x3D, 0x08, 0x90, 0xE0, 0xF0, 0x01, 0x44, 0x90, 0xF0, 0x08, 0x44, ++ 0x44, 0xE0, 0x38, 0x08, 0x07, 0x90, 0xF0, 0x01, 0x01, 0x44, 0xE0, 0x8E, 0x8F, 0x07, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x90, 0x07, 0x90, 0x03, 0x44, 0xF0, 0x54, 0x91, 0x07, 0x90, 0xF0, ++ 0x90, 0xF0, 0x03, 0x74, 0x54, 0xE0, 0x8F, 0x07, 0x07, 0x90, 0xF0, 0xFE, 0x01, 0x44, 0xE0, 0x92, ++ 0x93, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x94, 0x07, 0x90, 0x01, 0x44, 0xF0, 0x54, ++ 0x95, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x03, 0x74, 0x54, 0xE0, 0x93, 0x07, 0x06, 0x90, 0xF0, 0xFE, ++ 0x13, 0xC4, 0xE0, 0x26, 0xFE, 0x24, 0x07, 0x54, 0x70, 0x04, 0x1D, 0x60, 0x79, 0x07, 0x90, 0x22, ++ 0x90, 0xF0, 0x03, 0x74, 0x54, 0xE0, 0x90, 0x07, 0xF0, 0x02, 0x44, 0xF0, 0xE0, 0x94, 0x07, 0x90, ++ 0x02, 0x44, 0xF0, 0x54, 0x90, 0x0D, 0x80, 0xF0, 0x01, 0x74, 0x79, 0x07, 0xE4, 0x05, 0x80, 0xF0, ++ 0xF0, 0x79, 0x07, 0x90, 0xE0, 0x96, 0x07, 0x90, 0xE0, 0xF0, 0x02, 0x44, 0x90, 0xF0, 0x01, 0x44, ++ 0x44, 0xE0, 0x97, 0x07, 0x54, 0xE0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0xFE, 0x54, 0xE0, 0xF0, 0x02, ++ 0x08, 0x90, 0xF0, 0xFD, 0x01, 0x44, 0xE0, 0x49, 0x02, 0x44, 0xE0, 0xF0, 0xFB, 0x54, 0xE0, 0xF0, ++ 0xF7, 0x54, 0xE0, 0xF0, 0x4A, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x0F, 0x74, 0x90, 0xF0, 0x4B, 0x08, ++ 0x54, 0xE0, 0x4C, 0x08, 0xF0, 0x04, 0x44, 0xE0, 0xE0, 0x4D, 0x08, 0x90, 0x12, 0x44, 0xE0, 0x54, ++ 0x4E, 0x08, 0x90, 0xF0, 0x44, 0xE0, 0x54, 0xE0, 0x08, 0x90, 0xF0, 0x17, 0xC0, 0x54, 0xE0, 0x4F, ++ 0x90, 0xF0, 0x26, 0x44, 0x54, 0xE0, 0x50, 0x08, 0xF0, 0x01, 0x44, 0xFC, 0xF0, 0x3C, 0x44, 0xE0, ++ 0xE0, 0x52, 0x08, 0x90, 0xE0, 0xF0, 0x03, 0x44, 0x90, 0xF0, 0xF3, 0x54, 0x54, 0xE0, 0x49, 0x08, ++ 0x07, 0x90, 0xF0, 0xFD, 0x10, 0x44, 0xE0, 0x07, 0x08, 0x30, 0x22, 0xF0, 0x7A, 0xFF, 0x7B, 0x2B, ++ 0x12, 0x0F, 0x79, 0x20, 0x06, 0x90, 0xF8, 0x03, 0x04, 0x44, 0xE0, 0x03, 0x35, 0x06, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x8F, 0x07, 0x90, 0x90, 0xF0, 0xFE, 0x54, 0x54, 0xE0, 0x93, 0x07, ++ 0x78, 0xE4, 0xF0, 0xFE, 0xF6, 0x08, 0xF6, 0x74, 0xE0, 0xA0, 0x07, 0x90, 0x54, 0x13, 0x13, 0x13, ++ 0x0D, 0xE0, 0x30, 0x1F, 0xE0, 0x03, 0x06, 0x90, 0x90, 0xF0, 0x02, 0x44, 0x08, 0x74, 0xA0, 0x07, ++ 0x91, 0x07, 0x90, 0xF0, 0x90, 0x14, 0x60, 0xE0, 0x44, 0xE0, 0x8F, 0x07, 0x07, 0x90, 0xF0, 0x01, ++ 0xF0, 0x03, 0x74, 0x91, 0xE0, 0x8F, 0x07, 0x90, 0x90, 0xF0, 0xFE, 0x54, 0x44, 0xE0, 0xAE, 0x01, ++ 0xFF, 0xE0, 0xF0, 0x01, 0xE0, 0x8B, 0x07, 0x90, 0x54, 0x13, 0x13, 0xC4, 0xC4, 0xEF, 0xFE, 0x01, ++ 0xFD, 0x01, 0x54, 0x13, 0xFF, 0xDF, 0x54, 0xEF, 0x01, 0x54, 0x4E, 0xED, 0xE0, 0x54, 0x33, 0xC4, ++ 0xAE, 0x01, 0x90, 0x4F, 0x90, 0xFF, 0xE0, 0xF0, 0xC4, 0xE0, 0x8B, 0x07, 0xFE, 0x01, 0x54, 0x13, ++ 0x13, 0x13, 0x13, 0xEF, 0xEF, 0xFD, 0x01, 0x54, 0xED, 0xFF, 0xF7, 0x54, 0x33, 0x01, 0x54, 0x4E, ++ 0xF8, 0x54, 0x33, 0x33, 0xAE, 0x01, 0x90, 0x4F, 0x90, 0xFF, 0xE0, 0xF0, 0xC3, 0xE0, 0x8B, 0x07, ++ 0xFE, 0x01, 0x54, 0x13, 0x01, 0x54, 0xC4, 0xEF, 0xEF, 0x54, 0xEF, 0xFD, 0x54, 0x4E, 0xED, 0xFF, ++ 0xF0, 0x54, 0xC4, 0x01, 0xAE, 0x01, 0x90, 0x4F, 0x8B, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x62, 0x74, ++ 0x54, 0xE0, 0x23, 0x06, 0x08, 0x90, 0xF0, 0x0F, 0x01, 0x54, 0xE0, 0x53, 0xA0, 0x07, 0x90, 0xFF, ++ 0x01, 0x54, 0xC4, 0xE0, 0x06, 0x90, 0xFF, 0x4F, 0x13, 0xFE, 0xE0, 0x23, 0x6F, 0x01, 0x54, 0x13, ++ 0x54, 0xC4, 0x01, 0x54, 0x54, 0xE0, 0xFF, 0xF0, 0x90, 0xF0, 0x4F, 0xEF, 0x54, 0xE0, 0xA0, 0x07, ++ 0x60, 0x01, 0x64, 0x07, 0x07, 0x54, 0xE0, 0x40, 0x39, 0x60, 0x03, 0x64, 0xE6, 0x73, 0x78, 0xD3, ++ 0xE6, 0x18, 0x00, 0x94, 0x08, 0x40, 0x00, 0x94, 0x18, 0x16, 0xE6, 0x08, 0x22, 0x16, 0x01, 0x70, ++ 0x75, 0x21, 0x5B, 0x75, 0xFF, 0x7B, 0xFE, 0x5C, 0x19, 0x79, 0x20, 0x7A, 0x90, 0xF8, 0x03, 0x12, ++ 0x54, 0xE0, 0xAE, 0x01, 0x06, 0x90, 0xF0, 0xFE, 0xFB, 0x54, 0xE0, 0x03, 0x35, 0x06, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xA0, 0x07, 0x90, 0x22, 0xFF, 0x07, 0x54, 0xE0, 0x03, 0xBF, 0x72, 0x78, ++ 0x08, 0x13, 0x76, 0x06, 0x76, 0x22, 0x88, 0x76, 0xC4, 0x76, 0x08, 0x09, 0x93, 0x07, 0x90, 0x22, ++ 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x9E, 0x07, 0x90, 0x75, 0xF0, 0x04, 0x44, 0x5C, 0x75, 0x26, 0x5B, ++ 0x08, 0x30, 0x22, 0xE2, 0x7A, 0xFF, 0x7B, 0x09, 0x12, 0x3C, 0x79, 0x20, 0x07, 0x90, 0xF8, 0x03, ++ 0xF0, 0x03, 0x74, 0x97, 0xE0, 0x96, 0x07, 0x90, 0x90, 0xF0, 0xFE, 0x54, 0x54, 0xE0, 0xAE, 0x01, ++ 0x06, 0x90, 0xF0, 0xFE, 0xA3, 0xF0, 0xE0, 0x02, 0xF0, 0xFB, 0x54, 0xE0, 0xF0, 0xDF, 0x54, 0xE0, ++ 0x75, 0x01, 0x5D, 0x75, 0x22, 0x22, 0xC5, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x30, 0x30, 0x31, 0x09, 0x0A, 0x58, 0x54, 0x62, 0x65, 0x53, 0x09, 0x00, 0x0A, 0x70, 0x75, 0x74, ++ 0x61, 0x57, 0x09, 0x00, 0x0A, 0x50, 0x74, 0x69, 0x4D, 0x09, 0x09, 0x00, 0x58, 0x00, 0x49, 0x44, ++ 0x09, 0x00, 0x0A, 0x00, 0x0A, 0x43, 0x47, 0x41, 0x41, 0x09, 0x09, 0x00, 0x25, 0x3D, 0x43, 0x47, ++ 0x50, 0x00, 0x20, 0x64, 0x25, 0x3D, 0x52, 0x57, 0x09, 0x00, 0x0A, 0x64, 0x0A, 0x30, 0x4B, 0x4F, ++ 0x4C, 0x09, 0x09, 0x00, 0x25, 0x20, 0x3A, 0x43, 0x09, 0x00, 0x0A, 0x64, 0x0A, 0x31, 0x4B, 0x4F, ++ 0x4B, 0x4F, 0x09, 0x00, 0x09, 0x00, 0x0A, 0x32, 0x0A, 0x33, 0x4B, 0x4F, 0x4B, 0x4F, 0x09, 0x00, ++ 0x09, 0x09, 0x0A, 0x34, 0x00, 0x64, 0x25, 0x00, 0x61, 0x72, 0x54, 0x09, 0x00, 0x0A, 0x6B, 0x63, ++ 0x6E, 0x79, 0x53, 0x09, 0x09, 0x00, 0x0A, 0x63, 0x6E, 0x77, 0x6F, 0x44, 0x45, 0x09, 0x00, 0x0A, ++ 0x0A, 0x74, 0x69, 0x78, 0x4D, 0x09, 0x09, 0x00, 0x3D, 0x4C, 0x4C, 0x44, 0x00, 0x0A, 0x64, 0x25, ++ 0x60, 0x71, 0xE5, 0x01, 0x7A, 0xFF, 0x7B, 0x2C, 0x12, 0x00, 0x79, 0x20, 0x5B, 0x75, 0xF8, 0x03, ++ 0x5A, 0x5C, 0x75, 0x21, 0x78, 0xE4, 0x08, 0xD2, 0xF6, 0x08, 0xF6, 0x74, 0xF6, 0x08, 0xF6, 0x08, ++ 0x78, 0xF6, 0x7C, 0x78, 0x12, 0x03, 0x76, 0x7A, 0x72, 0x78, 0x7F, 0x03, 0x76, 0x08, 0xAA, 0x76, ++ 0x12, 0x74, 0x7F, 0xE6, 0x39, 0x31, 0xB2, 0x0B, 0xE0, 0x00, 0x06, 0x90, 0x30, 0x0F, 0x54, 0xC4, ++ 0x06, 0x90, 0x18, 0xE0, 0x13, 0x13, 0xE0, 0x03, 0xE0, 0x20, 0x3F, 0x54, 0x12, 0x72, 0x7F, 0x0D, ++ 0x06, 0x50, 0xB2, 0x0B, 0x75, 0x2C, 0x5B, 0x75, 0x20, 0xAF, 0xF2, 0x5C, 0x0F, 0x54, 0xC4, 0xEF, ++ 0xAF, 0x22, 0xE0, 0x20, 0xE0, 0x20, 0xEF, 0x20, 0xEF, 0x20, 0xAF, 0x1C, 0xE0, 0x20, 0x13, 0xC3, ++ 0xEF, 0x20, 0xAF, 0x14, 0x07, 0x54, 0x13, 0xC4, 0xAF, 0x0A, 0xE0, 0x20, 0x13, 0x13, 0xEF, 0x20, ++ 0xE0, 0x30, 0x3F, 0x54, 0x2C, 0x5B, 0x75, 0x06, 0xE5, 0xF2, 0x5C, 0x75, 0x70, 0x5C, 0x65, 0x60, ++ 0x65, 0x5F, 0xE5, 0x04, 0x85, 0x08, 0x60, 0x5B, 0x5C, 0x85, 0x5F, 0x5B, 0xAA, 0x08, 0xD2, 0x60, ++ 0x12, 0x60, 0xA9, 0x5F, 0x08, 0xC2, 0xFF, 0x02, 0xE6, 0x82, 0x78, 0x22, 0xC3, 0xFF, 0x01, 0x54, ++ 0x08, 0x74, 0x9F, 0xE4, 0x05, 0x54, 0x00, 0x94, 0xC3, 0xE6, 0x18, 0xFC, 0xE6, 0x08, 0xFE, 0x13, ++ 0x6C, 0xEE, 0xFF, 0x13, 0x08, 0xEF, 0xF6, 0x18, 0xFF, 0x7B, 0x22, 0xF6, 0x09, 0x79, 0x20, 0x7A, ++ 0x31, 0xF8, 0x03, 0x12, 0x24, 0x5B, 0x75, 0x6C, 0x22, 0xDC, 0x5C, 0x75, 0x01, 0x0D, 0x90, 0xE4, ++ 0x21, 0x0D, 0x90, 0xF0, 0x41, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0xFF, 0x74, 0x90, 0xF0, 0x61, 0x0D, ++ 0x54, 0xE0, 0x00, 0x0D, 0x44, 0xE0, 0xF0, 0xF8, 0x44, 0xE0, 0xF0, 0x60, 0x90, 0xE0, 0xF0, 0x18, ++ 0x90, 0xF0, 0x20, 0x0D, 0xAA, 0x74, 0x82, 0x0D, 0x02, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x30, 0x74, ++ 0x90, 0xF0, 0x22, 0x0D, 0x20, 0x74, 0x05, 0x0D, 0x25, 0x0D, 0x90, 0xF0, 0x06, 0x0D, 0x90, 0xF0, ++ 0x90, 0xF0, 0x9C, 0x74, 0x90, 0xF0, 0x26, 0x0D, 0x89, 0x74, 0x0A, 0x0D, 0x2A, 0x0D, 0x90, 0xF0, ++ 0x90, 0x34, 0x91, 0xF0, 0x01, 0x74, 0xF0, 0x07, 0xF5, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, ++ 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xE0, 0xF9, 0x07, 0x90, 0x04, 0x44, 0xF8, 0x54, ++ 0x0A, 0x90, 0xE4, 0xF0, 0x09, 0x90, 0xF0, 0x00, 0x09, 0x90, 0xF0, 0xFF, 0x0A, 0x90, 0xF0, 0xFE, ++ 0x90, 0xF0, 0x04, 0x01, 0x44, 0xE0, 0xF6, 0x09, 0x44, 0xE0, 0xF0, 0x01, 0x54, 0xE0, 0xF0, 0x02, ++ 0x09, 0x90, 0xF0, 0xFE, 0x01, 0x44, 0xE0, 0xFD, 0x02, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xF0, ++ 0x55, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, ++ 0xE0, 0x56, 0x08, 0x90, 0x03, 0x44, 0xF0, 0x54, 0xCF, 0x54, 0xE0, 0xF0, 0x57, 0x08, 0x90, 0xF0, ++ 0x44, 0xF8, 0x54, 0xE0, 0x08, 0x90, 0xF0, 0x03, 0xDC, 0x74, 0xE0, 0x58, 0x5C, 0x08, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0x5F, 0x08, 0x90, 0xE4, ++ 0x5E, 0x08, 0x90, 0xF0, 0x5D, 0x08, 0x90, 0xF0, 0x60, 0x08, 0x90, 0xF0, 0x07, 0x90, 0xF0, 0x04, ++ 0xFD, 0x54, 0xE0, 0xFF, 0xFE, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, ++ 0xF0, 0xF7, 0x54, 0xE0, 0xF0, 0xFB, 0x54, 0xE0, 0xE0, 0xFD, 0x07, 0x90, 0xE0, 0xF0, 0x01, 0x44, ++ 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xF7, 0x54, 0x00, 0xF0, 0xFB, 0x54, 0x00, 0x00, 0x00, 0x00, ++ 0xE0, 0xFE, 0x07, 0x90, 0x90, 0xF0, 0xFE, 0x54, 0x54, 0xE0, 0xFD, 0x07, 0x08, 0x90, 0xF0, 0xFE, ++ 0x02, 0x44, 0xE0, 0x33, 0x3A, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, ++ 0xE0, 0x3B, 0x08, 0x90, 0xE0, 0xF0, 0x01, 0x44, 0x90, 0xF0, 0x04, 0x44, 0x44, 0xE0, 0x3C, 0x08, ++ 0x44, 0xE0, 0xF0, 0x01, 0x08, 0x90, 0xF0, 0x04, 0x01, 0x44, 0xE0, 0x3D, 0x02, 0x44, 0xE0, 0xF0, ++ 0x08, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xF0, 0x38, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, ++ 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xFB, 0x54, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xE0, 0x36, 0x08, 0x90, ++ 0xE0, 0xF0, 0x01, 0x44, 0x90, 0xF0, 0x02, 0x44, 0x54, 0xE0, 0x37, 0x08, 0x54, 0xE0, 0xF0, 0x9F, ++ 0xF0, 0x05, 0x44, 0xE0, 0xE0, 0x36, 0x08, 0x90, 0xE0, 0xF0, 0xFD, 0x54, 0x90, 0xF0, 0xFB, 0x54, ++ 0x44, 0xE0, 0xA1, 0x07, 0x44, 0xE0, 0xF0, 0x04, 0x44, 0xE0, 0xF0, 0x10, 0x07, 0x90, 0xF0, 0x01, ++ 0x04, 0x44, 0xE0, 0xA2, 0x10, 0x44, 0xE0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0xFB, 0x54, 0xE0, 0xF0, ++ 0xEF, 0x54, 0xE0, 0xF0, 0xFE, 0x54, 0xE0, 0xF0, 0xA6, 0x07, 0x90, 0xF0, 0xF0, 0x30, 0x44, 0xE0, ++ 0xE0, 0x8F, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, 0x44, 0xE0, 0x8E, 0x07, 0x07, 0x90, 0xF0, 0x01, ++ 0xF0, 0x54, 0xE0, 0x90, 0x90, 0xF0, 0x03, 0x44, 0x03, 0x74, 0x91, 0x07, 0x8F, 0x07, 0x90, 0xF0, ++ 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0x93, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, 0x44, 0xE0, 0x92, 0x07, ++ 0x07, 0x90, 0xF0, 0x01, 0xF0, 0x54, 0xE0, 0x94, 0x90, 0xF0, 0x01, 0x44, 0x03, 0x74, 0x95, 0x07, ++ 0x93, 0x07, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0x74, 0x0F, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x03, ++ 0xFE, 0x54, 0xE0, 0x0E, 0xFD, 0x54, 0xE0, 0xF0, 0xFC, 0xFD, 0xE4, 0xF0, 0xE0, 0x0F, 0x08, 0x90, ++ 0x11, 0x60, 0x03, 0x64, 0xFF, 0x94, 0xED, 0xC3, 0x50, 0x00, 0x94, 0xEC, 0xBD, 0x0D, 0x00, 0x08, ++ 0x80, 0x0C, 0x01, 0x00, 0x7A, 0xFF, 0x7B, 0xE7, 0x12, 0x85, 0x79, 0x20, 0x08, 0x90, 0xE5, 0x0C, ++ 0xF0, 0x43, 0x74, 0x16, 0xF0, 0x18, 0x08, 0x90, 0xF0, 0x1A, 0x08, 0x90, 0xF0, 0x1C, 0x08, 0x90, ++ 0x74, 0x01, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x03, 0x08, 0x90, 0xF0, 0x02, 0x08, 0x90, 0xF0, 0x03, ++ 0xFC, 0xE4, 0xF0, 0x04, 0xBD, 0x0D, 0x00, 0xFD, 0xED, 0x0C, 0x01, 0x00, 0x70, 0x4C, 0x80, 0x64, ++ 0x16, 0x08, 0x90, 0xF4, 0x90, 0xF0, 0x42, 0x74, 0x90, 0xF0, 0x18, 0x08, 0x90, 0xF0, 0x1A, 0x08, ++ 0x90, 0xF0, 0x1C, 0x08, 0x04, 0x74, 0x01, 0x08, 0x02, 0x08, 0x90, 0xF0, 0x03, 0x08, 0x90, 0xF0, ++ 0x04, 0x08, 0x90, 0xF0, 0x0E, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, ++ 0x74, 0x1E, 0x08, 0x90, 0x07, 0x90, 0xF0, 0x12, 0xF0, 0x0D, 0x74, 0xF3, 0xE0, 0x07, 0x07, 0x90, ++ 0x22, 0xF0, 0x10, 0x44, 0xE0, 0x23, 0x06, 0x90, 0x54, 0x13, 0x13, 0xFF, 0x0C, 0x92, 0x13, 0x3F, ++ 0xE0, 0x27, 0x06, 0x90, 0x30, 0x03, 0xE0, 0x30, 0x06, 0x90, 0x1A, 0x0C, 0xE0, 0x20, 0xE0, 0x27, ++ 0x26, 0x06, 0x90, 0x3D, 0xE0, 0xA3, 0xFE, 0xE0, 0xC3, 0xCE, 0x02, 0x78, 0xD8, 0x13, 0xCE, 0x13, ++ 0x2A, 0xE0, 0x20, 0xF9, 0x0D, 0x90, 0x0C, 0xC2, 0xF0, 0x0F, 0x74, 0x01, 0x04, 0x21, 0x0D, 0x90, ++ 0xF1, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0xE4, 0x74, 0xB1, 0x74, 0xF2, 0x07, 0x0C, 0x0D, 0x90, 0xF0, ++ 0x90, 0xF0, 0x36, 0x74, 0x15, 0x74, 0x2C, 0x0D, 0xA6, 0x00, 0x90, 0xF0, 0x0C, 0xD2, 0x28, 0x80, ++ 0x74, 0x21, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x0F, 0x90, 0xF0, 0x04, 0x01, 0xB1, 0x74, 0xF1, 0x07, ++ 0xF2, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0xE4, 0x74, 0x36, 0x74, 0x2C, 0x0D, 0x0C, 0x0D, 0x90, 0xF0, ++ 0x90, 0xF0, 0x15, 0x74, 0x90, 0xE0, 0xA7, 0x00, 0xA2, 0xF0, 0x3E, 0x08, 0x54, 0x33, 0xE4, 0x0C, ++ 0xE0, 0x25, 0xFC, 0x01, 0x90, 0xFE, 0xE0, 0x25, 0x54, 0xE0, 0x23, 0x06, 0xEC, 0xF0, 0x4E, 0xFB, ++ 0x54, 0x33, 0x33, 0x33, 0x54, 0xE0, 0xFF, 0xF8, 0x22, 0xF0, 0x4F, 0xF7, 0x7B, 0x6E, 0x08, 0x30, ++ 0x79, 0x20, 0x7A, 0xFF, 0xF8, 0x03, 0x12, 0x11, 0xE0, 0x00, 0x0D, 0x90, 0x90, 0xF0, 0xF8, 0x54, ++ 0x54, 0xE0, 0x20, 0x0D, 0x7F, 0x78, 0xF0, 0xF8, 0x76, 0x08, 0xF4, 0x76, 0x8A, 0x0D, 0x90, 0x24, ++ 0x0D, 0x90, 0xFF, 0xE0, 0xFF, 0x6F, 0xE0, 0x8B, 0xE0, 0x0B, 0x07, 0x90, 0xF6, 0x08, 0xE4, 0xFD, ++ 0xF6, 0x08, 0x6D, 0xEF, 0xF6, 0x7B, 0x78, 0xE4, 0xE0, 0x89, 0x0D, 0x90, 0xE0, 0xF0, 0x10, 0x44, ++ 0x90, 0xF0, 0x20, 0x44, 0x44, 0xE0, 0x40, 0x08, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0x08, ++ 0x08, 0x90, 0xF0, 0x20, 0x0F, 0x54, 0xE0, 0x44, 0x90, 0xF0, 0x20, 0x44, 0x44, 0xE0, 0x43, 0x08, ++ 0x44, 0xE0, 0xF0, 0x70, 0x08, 0x90, 0xF0, 0x80, 0xF7, 0x54, 0xE0, 0x40, 0x00, 0x06, 0x90, 0xF0, ++ 0x0F, 0x54, 0xC4, 0xE0, 0x91, 0x04, 0xE0, 0x30, 0x90, 0x1E, 0x80, 0x34, 0x20, 0xE0, 0x27, 0x06, ++ 0x13, 0xE0, 0x20, 0xE0, 0xFF, 0x01, 0x54, 0x13, 0xE0, 0x23, 0x06, 0x90, 0x54, 0x13, 0x13, 0xFE, ++ 0x05, 0x60, 0x6F, 0x01, 0x91, 0x27, 0x06, 0x90, 0x76, 0x7F, 0x78, 0x37, 0x24, 0x76, 0x08, 0xF4, ++ 0x7F, 0x7F, 0x62, 0x80, 0x50, 0xB2, 0x0B, 0x12, 0x76, 0x7F, 0x78, 0x5B, 0x24, 0x76, 0x08, 0xF4, ++ 0xE0, 0x47, 0x08, 0x90, 0x50, 0x05, 0x94, 0xC3, 0xE6, 0x82, 0x78, 0x24, 0x90, 0xFF, 0x01, 0x54, ++ 0xFD, 0xE0, 0x23, 0x06, 0x01, 0x54, 0x13, 0x13, 0xE4, 0x01, 0x70, 0x6F, 0x06, 0x90, 0x07, 0x60, ++ 0x08, 0x44, 0xE0, 0x35, 0xE6, 0x82, 0x78, 0xF0, 0x91, 0x0C, 0x92, 0x13, 0x7A, 0xFF, 0x7B, 0x40, ++ 0x12, 0x19, 0x79, 0x20, 0x06, 0x90, 0xF8, 0x03, 0x13, 0xFF, 0xE0, 0x23, 0x30, 0x3F, 0x54, 0x13, ++ 0xFF, 0x7B, 0x09, 0xE0, 0x1F, 0x79, 0x20, 0x7A, 0x7B, 0xF8, 0x03, 0x12, 0x79, 0x20, 0x7A, 0xFF, ++ 0xF8, 0x03, 0x12, 0x21, 0x06, 0x40, 0xEF, 0xB1, 0x75, 0x26, 0x5B, 0x75, 0x90, 0x22, 0x15, 0x5C, ++ 0xFF, 0xE0, 0x47, 0x08, 0x94, 0x80, 0x64, 0xD3, 0x78, 0x0C, 0x40, 0x85, 0x0A, 0x94, 0xE6, 0x7B, ++ 0x80, 0x06, 0x03, 0x50, 0xC3, 0x22, 0xC3, 0x0E, 0x94, 0x80, 0x64, 0xEF, 0xE4, 0x04, 0x50, 0x83, ++ 0xD3, 0xF6, 0x7B, 0x78, 0x22, 0x08, 0x30, 0x22, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x23, 0x79, ++ 0x76, 0x74, 0x78, 0xF8, 0x0A, 0x76, 0x08, 0x00, 0x07, 0x76, 0x83, 0x78, 0xE0, 0x00, 0x0D, 0x90, ++ 0x90, 0xF0, 0x07, 0x44, 0x44, 0xE0, 0x20, 0x0D, 0x75, 0x78, 0xF0, 0x07, 0x70, 0x46, 0x18, 0xE6, ++ 0x76, 0x08, 0xF6, 0x50, 0xE6, 0x83, 0x78, 0x0A, 0x40, 0x00, 0x94, 0xD3, 0x47, 0x08, 0x90, 0x23, ++ 0x0A, 0x94, 0xD3, 0xE0, 0xE6, 0x16, 0x1A, 0x40, 0x90, 0xFF, 0x07, 0x54, 0x54, 0xE0, 0x00, 0x0D, ++ 0xE6, 0xF0, 0x4F, 0xF8, 0x90, 0xFF, 0x07, 0x54, 0x54, 0xE0, 0x20, 0x0D, 0x22, 0xF0, 0x4F, 0xF8, ++ 0x20, 0x7A, 0xFF, 0x7B, 0x83, 0x78, 0x29, 0x79, 0x7B, 0xE1, 0x0C, 0x12, 0x79, 0x20, 0x7A, 0xFF, ++ 0x47, 0x08, 0x90, 0x33, 0x00, 0x7C, 0xFD, 0xE0, 0x75, 0xE5, 0x0C, 0x12, 0x5C, 0x75, 0x27, 0x5B, ++ 0xFF, 0x7B, 0x22, 0x81, 0x77, 0x79, 0x20, 0x7A, 0x90, 0xF8, 0x03, 0x12, 0x54, 0xE0, 0xAE, 0x01, ++ 0x06, 0x90, 0xF0, 0xC0, 0xA3, 0xF0, 0xE0, 0x02, 0xF0, 0xFB, 0x54, 0xE0, 0xF6, 0x76, 0x78, 0xE4, ++ 0x07, 0x90, 0xF6, 0x08, 0x01, 0x44, 0xE0, 0x93, 0xEF, 0x20, 0xAF, 0xF0, 0x20, 0x0F, 0x54, 0xC4, ++ 0x20, 0xAF, 0x58, 0xE0, 0x52, 0xE0, 0x20, 0xEF, 0xC3, 0xEF, 0x20, 0xAF, 0x4A, 0xE0, 0x20, 0x13, ++ 0x13, 0xEF, 0x20, 0xAF, 0x30, 0x3F, 0x54, 0x13, 0x3E, 0x80, 0x02, 0xE0, 0xE0, 0x00, 0x06, 0x90, ++ 0x20, 0x0F, 0x54, 0xC4, 0xC4, 0xE0, 0x23, 0xE0, 0x30, 0x07, 0x54, 0x13, 0xFE, 0xE0, 0x1B, 0xE0, ++ 0x06, 0x78, 0xE0, 0xA3, 0xCE, 0x13, 0xC3, 0xCE, 0x20, 0xF9, 0xD8, 0x13, 0xEF, 0xB1, 0x0B, 0xE0, ++ 0x5B, 0x75, 0x11, 0x50, 0xDC, 0x5C, 0x75, 0x24, 0xE6, 0x7A, 0x78, 0x22, 0xB1, 0x0B, 0x60, 0x16, ++ 0x75, 0x07, 0x40, 0xEF, 0x5C, 0x75, 0x27, 0x5B, 0x5B, 0x75, 0x22, 0x81, 0xF2, 0x5C, 0x75, 0x2C, ++ 0x7A, 0xFF, 0x7B, 0x22, 0x12, 0x68, 0x79, 0x20, 0x08, 0x90, 0xF8, 0x03, 0x7C, 0x78, 0xE0, 0x47, ++ 0x23, 0x08, 0x90, 0xF6, 0xF0, 0xF8, 0x54, 0xE0, 0xE0, 0x24, 0x08, 0x90, 0x08, 0x44, 0xE3, 0x54, ++ 0x28, 0x08, 0x90, 0xF0, 0x44, 0xF8, 0x54, 0xE0, 0x08, 0x90, 0xF0, 0x02, 0xFB, 0x54, 0xE0, 0x27, ++ 0x56, 0x08, 0x90, 0xF0, 0x44, 0xF0, 0x54, 0xE0, 0x44, 0xE0, 0xF0, 0x07, 0x08, 0x90, 0xF0, 0x30, ++ 0xF8, 0x54, 0xE0, 0x57, 0x90, 0xF0, 0x05, 0x44, 0xE4, 0xE0, 0x58, 0x08, 0xB1, 0xF0, 0xDC, 0x74, ++ 0x75, 0x07, 0x50, 0xEF, 0x5C, 0x75, 0x26, 0x5B, 0x5B, 0x75, 0x22, 0x92, 0x48, 0x5C, 0x75, 0x2C, ++ 0x03, 0x08, 0x20, 0x22, 0x7B, 0x24, 0x29, 0x02, 0x79, 0x20, 0x7A, 0xFF, 0xF8, 0x03, 0x12, 0x3B, ++ 0x00, 0x76, 0x74, 0x78, 0x90, 0x05, 0x76, 0x08, 0x44, 0xE0, 0x1F, 0x08, 0x44, 0xE0, 0xF0, 0x01, ++ 0x08, 0x90, 0xF0, 0x02, 0x01, 0x44, 0xE0, 0x21, 0x02, 0x44, 0xE0, 0xF0, 0xFB, 0x54, 0xE0, 0xF0, ++ 0xF7, 0x54, 0xE0, 0xF0, 0x22, 0x08, 0x90, 0xF0, 0x44, 0xF8, 0x54, 0xE0, 0x08, 0x90, 0xF0, 0x01, ++ 0x04, 0x44, 0xE0, 0x21, 0x08, 0x44, 0xE0, 0xF0, 0x23, 0x08, 0x90, 0xF0, 0x44, 0xF8, 0x54, 0xE0, ++ 0x08, 0x90, 0xF0, 0x04, 0x01, 0x44, 0xE0, 0x27, 0x02, 0x44, 0xE0, 0xF0, 0xFB, 0x54, 0xE0, 0xF0, ++ 0x04, 0x44, 0xE0, 0xF0, 0x28, 0x08, 0x90, 0xF0, 0x44, 0xF8, 0x54, 0xE0, 0x08, 0x90, 0xF0, 0x04, ++ 0x01, 0x44, 0xE0, 0x29, 0x02, 0x44, 0xE0, 0xF0, 0x2A, 0x08, 0x90, 0xF0, 0x44, 0xE0, 0x54, 0xE0, ++ 0x08, 0x90, 0xF0, 0x05, 0x01, 0x44, 0xE0, 0x29, 0xFD, 0x54, 0xE0, 0xF0, 0x24, 0x08, 0x90, 0xF0, ++ 0x44, 0xE3, 0x54, 0xE0, 0x44, 0xE0, 0xF0, 0x14, 0x08, 0x90, 0xF0, 0x02, 0x15, 0x74, 0xE0, 0x25, ++ 0x24, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x2B, 0x08, 0x90, 0x90, 0xF0, 0x04, 0x44, ++ 0x40, 0x74, 0x2D, 0x08, 0x26, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0x44, 0xF9, 0x54, 0xE0, ++ 0x08, 0x90, 0xF0, 0x02, 0xFD, 0x54, 0xE0, 0x1F, 0x21, 0x08, 0x90, 0xF0, 0xF0, 0xFD, 0x54, 0xE0, ++ 0xE0, 0x27, 0x08, 0x90, 0x90, 0xF0, 0xFD, 0x54, 0x54, 0xE0, 0x2B, 0x08, 0x90, 0xE4, 0xF0, 0xFB, ++ 0xE0, 0xF0, 0x2E, 0x08, 0xE0, 0xF0, 0x9F, 0x54, 0xE0, 0xF0, 0x10, 0x44, 0x01, 0x44, 0xF0, 0x54, ++ 0x2F, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x7F, 0x74, 0xFF, 0x74, 0x30, 0x08, 0x08, 0x90, 0xE4, 0xF0, ++ 0x54, 0xE0, 0xF0, 0x2E, 0x44, 0xE0, 0xF0, 0x9F, 0x54, 0xE0, 0xF0, 0x10, 0x08, 0x90, 0xF0, 0xF0, ++ 0xF0, 0xEC, 0x74, 0x2F, 0x30, 0x08, 0x90, 0xE4, 0x2E, 0x08, 0x90, 0xF0, 0x9F, 0x54, 0xE0, 0xF0, ++ 0x10, 0x44, 0xE0, 0xF0, 0xF0, 0x54, 0xE0, 0xF0, 0x78, 0xF0, 0x02, 0x44, 0x33, 0x33, 0xE6, 0x83, ++ 0xFF, 0xF8, 0x54, 0x33, 0x9F, 0xE0, 0x74, 0xC3, 0xE0, 0x25, 0xE6, 0xFF, 0xC3, 0xFE, 0xE0, 0x25, ++ 0x08, 0x90, 0x9E, 0xEF, 0x90, 0xE4, 0xF0, 0x2F, 0x90, 0xF0, 0x30, 0x08, 0xE0, 0xF0, 0x2E, 0x08, ++ 0x40, 0x44, 0x9F, 0x54, 0x10, 0x44, 0xE0, 0xF0, 0x2F, 0x08, 0x90, 0xF0, 0xE4, 0xF0, 0x40, 0x74, ++ 0xF0, 0x30, 0x08, 0x90, 0xF0, 0x2E, 0x08, 0x90, 0xE0, 0x24, 0x08, 0x90, 0x90, 0xF0, 0xFE, 0x54, ++ 0x44, 0xE0, 0x40, 0x08, 0x44, 0xE0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x04, 0x08, 0x90, 0xF0, 0x10, ++ 0xF0, 0x54, 0xE0, 0x44, 0x90, 0xF0, 0x04, 0x44, 0x54, 0xE0, 0x43, 0x08, 0xF0, 0x06, 0x44, 0xF8, ++ 0xF0, 0x08, 0x44, 0xE0, 0xE0, 0x42, 0x08, 0x90, 0x01, 0x44, 0xFC, 0x54, 0x40, 0x08, 0x90, 0xF0, ++ 0xF0, 0xFB, 0x54, 0xE0, 0x50, 0xEF, 0x25, 0x12, 0x26, 0x5B, 0x75, 0x07, 0x22, 0x92, 0x5C, 0x75, ++ 0x18, 0xE6, 0x75, 0x78, 0x90, 0x2D, 0x70, 0x46, 0xE0, 0xF0, 0x2E, 0x08, 0x40, 0x44, 0x9F, 0x54, ++ 0x7A, 0xFF, 0x7B, 0xF0, 0x90, 0x41, 0x79, 0x20, 0xFE, 0xE0, 0x31, 0x08, 0xE0, 0x32, 0x08, 0x90, ++ 0xED, 0xFC, 0xEE, 0xFD, 0x75, 0xE5, 0x0C, 0x12, 0x5C, 0x75, 0x29, 0x5B, 0x76, 0x78, 0x78, 0x65, ++ 0xF4, 0x76, 0x08, 0x01, 0x7C, 0x08, 0x30, 0x22, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x4B, 0x79, ++ 0x76, 0x74, 0x78, 0xF8, 0x0A, 0x76, 0x08, 0x00, 0xE0, 0x21, 0x08, 0x90, 0xE0, 0xF0, 0x04, 0x44, ++ 0x90, 0xF0, 0x08, 0x44, 0x54, 0xE0, 0x23, 0x08, 0xF0, 0x04, 0x44, 0xF8, 0xE0, 0x24, 0x08, 0x90, ++ 0x10, 0x44, 0xE3, 0x54, 0x02, 0x44, 0xE0, 0xF0, 0x27, 0x08, 0x90, 0xF0, 0xF0, 0xFB, 0x54, 0xE0, ++ 0xE0, 0x28, 0x08, 0x90, 0x03, 0x44, 0xF8, 0x54, 0x29, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, ++ 0xE0, 0x2B, 0x08, 0x90, 0xE0, 0xF0, 0xE7, 0x54, 0xE0, 0xF0, 0x01, 0x44, 0x90, 0xF0, 0xFD, 0x54, ++ 0x74, 0xE0, 0x2C, 0x08, 0x08, 0x90, 0xF0, 0xCD, 0xF0, 0x54, 0xE0, 0x56, 0xE0, 0xF0, 0x04, 0x44, ++ 0x90, 0xF0, 0x30, 0x44, 0x54, 0xE0, 0x57, 0x08, 0xF0, 0x03, 0x44, 0xF8, 0xE0, 0x58, 0x08, 0x90, ++ 0xF0, 0xDC, 0x74, 0xE4, 0x40, 0xEF, 0x25, 0x12, 0x12, 0x78, 0x7F, 0x07, 0x07, 0x50, 0xB2, 0x0B, ++ 0x75, 0x26, 0x5B, 0x75, 0x78, 0x22, 0x92, 0x5C, 0x46, 0x18, 0xE6, 0x75, 0x08, 0x90, 0x0F, 0x70, ++ 0x94, 0xC3, 0xE0, 0x46, 0x75, 0x06, 0x50, 0x17, 0x5C, 0x75, 0x2A, 0x5B, 0x08, 0x30, 0x22, 0x0E, ++ 0x7A, 0xFF, 0x7B, 0x3B, 0x12, 0x51, 0x79, 0x20, 0x74, 0x78, 0xF8, 0x03, 0x76, 0x08, 0x00, 0x76, ++ 0x24, 0x08, 0x90, 0x14, 0xF0, 0xFD, 0x54, 0xE0, 0xE0, 0x27, 0x08, 0x90, 0x90, 0xF0, 0xFB, 0x54, ++ 0x54, 0xE0, 0x2B, 0x08, 0x08, 0x90, 0xF0, 0xFD, 0xF0, 0x54, 0xE0, 0x56, 0xE0, 0xF0, 0x07, 0x44, ++ 0x90, 0xF0, 0x30, 0x44, 0x54, 0xE0, 0x57, 0x08, 0xF0, 0x03, 0x44, 0xF8, 0x25, 0x12, 0x97, 0x51, ++ 0x7F, 0x07, 0x40, 0xEF, 0xB2, 0x0B, 0x12, 0x78, 0x5B, 0x75, 0x07, 0x50, 0x92, 0x5C, 0x75, 0x26, ++ 0xE6, 0x75, 0x78, 0x22, 0x2E, 0x70, 0x46, 0x18, 0xE0, 0x46, 0x08, 0x90, 0x50, 0x0D, 0x94, 0xC3, ++ 0x2A, 0x5B, 0x75, 0x08, 0x80, 0xF8, 0x5C, 0x75, 0x29, 0x5B, 0x75, 0x06, 0xE4, 0x65, 0x5C, 0x75, ++ 0xF0, 0x2E, 0x08, 0x90, 0x44, 0x9F, 0x54, 0xE0, 0x08, 0x90, 0xF0, 0x40, 0x06, 0x70, 0xE0, 0x31, ++ 0x75, 0x27, 0x5B, 0x75, 0x90, 0x22, 0x81, 0x5C, 0x44, 0xE0, 0x21, 0x08, 0x02, 0x7D, 0xF0, 0x08, ++ 0x2E, 0x08, 0x90, 0xE4, 0x9F, 0x54, 0xE0, 0xF0, 0xEF, 0x54, 0xE0, 0xF0, 0x0F, 0x54, 0xED, 0xF0, ++ 0xF0, 0x54, 0xE0, 0xFF, 0x08, 0x90, 0xF0, 0x4F, 0x22, 0xF5, 0xE0, 0x31, 0xE0, 0x32, 0x08, 0x90, ++ 0x22, 0xE5, 0x23, 0xF5, 0xE0, 0x95, 0x33, 0xFF, 0x23, 0xE5, 0xC3, 0xFE, 0xE5, 0x23, 0xF5, 0x9F, ++ 0x22, 0xF5, 0x9E, 0x22, 0xE0, 0x2E, 0x08, 0x90, 0x90, 0xF0, 0x10, 0x44, 0x22, 0xE5, 0x2F, 0x08, ++ 0x30, 0x08, 0x90, 0xF0, 0xE4, 0xF0, 0x23, 0xE5, 0xF0, 0x2E, 0x08, 0x90, 0xB0, 0x0A, 0xBD, 0x0D, ++ 0xE0, 0x21, 0x08, 0x90, 0x22, 0xF0, 0xF7, 0x54, 0x7B, 0x5E, 0x08, 0x30, 0x79, 0x20, 0x7A, 0xFF, ++ 0xF8, 0x03, 0x12, 0x57, 0x00, 0x76, 0x74, 0x78, 0x90, 0x64, 0x76, 0x08, 0x44, 0xE0, 0x21, 0x08, ++ 0x08, 0x90, 0xF0, 0x08, 0x07, 0x44, 0xE0, 0x43, 0x42, 0x08, 0x90, 0xF0, 0xF0, 0x03, 0x44, 0xE0, ++ 0xE0, 0x23, 0x08, 0x90, 0x02, 0x44, 0xF8, 0x54, 0x24, 0x08, 0x90, 0xF0, 0x44, 0xE3, 0x54, 0xE0, ++ 0x08, 0x90, 0xF0, 0x14, 0xF8, 0x54, 0xE0, 0x28, 0x90, 0xF0, 0x02, 0x44, 0x54, 0xE0, 0x56, 0x08, ++ 0xF0, 0x07, 0x44, 0xF0, 0xF0, 0x30, 0x44, 0xE0, 0xE0, 0x57, 0x08, 0x90, 0x03, 0x44, 0xF8, 0x54, ++ 0x58, 0x08, 0x90, 0xF0, 0xDC, 0x74, 0xE4, 0xE0, 0xEF, 0x25, 0x12, 0xF0, 0x5B, 0x75, 0x07, 0x50, ++ 0x92, 0x5C, 0x75, 0x26, 0xE6, 0x75, 0x78, 0x22, 0x06, 0x70, 0x46, 0x18, 0x75, 0x2B, 0x5B, 0x75, ++ 0x30, 0x22, 0x73, 0x5C, 0xFF, 0x7B, 0x40, 0x08, 0x5D, 0x79, 0x20, 0x7A, 0x78, 0xF8, 0x03, 0x12, ++ 0x08, 0x00, 0x76, 0x74, 0x06, 0x90, 0x05, 0x76, 0x13, 0x13, 0xE0, 0x29, 0xE0, 0x30, 0x3F, 0x54, ++ 0x02, 0x0D, 0x90, 0x56, 0x44, 0x8F, 0x54, 0xE0, 0x0D, 0x90, 0xF0, 0x30, 0x8F, 0x54, 0xE0, 0x22, ++ 0x90, 0xF0, 0x30, 0x44, 0x54, 0xE0, 0x05, 0x0D, 0xF0, 0x20, 0x44, 0x8F, 0xE0, 0x25, 0x0D, 0x90, ++ 0x20, 0x44, 0x8F, 0x54, 0x06, 0x90, 0x22, 0xF0, 0x13, 0xFF, 0xE0, 0x29, 0x30, 0x3F, 0x54, 0x13, ++ 0xE8, 0x71, 0x0F, 0xE0, 0xFD, 0x33, 0xFC, 0xE4, 0x20, 0x7A, 0xFF, 0x7B, 0x0C, 0x12, 0x65, 0x79, ++ 0xE6, 0x75, 0x78, 0xE5, 0x0F, 0x70, 0x46, 0x18, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x21, 0x79, ++ 0x27, 0x5B, 0x75, 0xF8, 0x22, 0x21, 0x5C, 0x75, 0x0D, 0x7E, 0x0A, 0x7F, 0x0D, 0x7C, 0x06, 0x7D, ++ 0x82, 0x8F, 0x0C, 0xD2, 0xC4, 0xE0, 0x83, 0x8E, 0x94, 0xD3, 0x0F, 0x54, 0x90, 0x36, 0x40, 0x04, ++ 0x94, 0xE0, 0x46, 0x08, 0x8D, 0x2E, 0x50, 0x19, 0xE0, 0x83, 0x8C, 0x82, 0x0F, 0x54, 0xC4, 0xFD, ++ 0x0F, 0x54, 0xED, 0xFC, 0x54, 0x14, 0xEC, 0xFD, 0xF0, 0x54, 0xC4, 0x0F, 0x82, 0x8F, 0xF0, 0x4D, ++ 0x54, 0xC4, 0xFF, 0xE0, 0x54, 0xEF, 0xFE, 0x0F, 0x14, 0xEE, 0xFF, 0x0F, 0x54, 0xC4, 0x0F, 0x54, ++ 0xC2, 0xF0, 0x4F, 0xF0, 0x06, 0x0D, 0x90, 0x0C, 0x26, 0x0D, 0x90, 0xE0, 0x0A, 0x0D, 0x90, 0xF0, ++ 0x2A, 0x0D, 0x90, 0xE0, 0x22, 0x0C, 0xA2, 0xF0, 0x81, 0x02, 0x08, 0x20, 0x7A, 0xFF, 0x7B, 0xD6, ++ 0x12, 0x70, 0x79, 0x20, 0x78, 0xE4, 0xF8, 0x03, 0x06, 0x90, 0xF6, 0x7A, 0xA3, 0xF0, 0xE0, 0x02, ++ 0xF0, 0x04, 0x44, 0xE0, 0xE0, 0x23, 0x06, 0x90, 0x90, 0xF0, 0x0F, 0x54, 0xC4, 0xE0, 0x26, 0x06, ++ 0x24, 0x07, 0x54, 0x13, 0x04, 0x1D, 0x60, 0xFE, 0x07, 0x90, 0x22, 0x70, 0xF0, 0x03, 0x74, 0x79, ++ 0xE0, 0x90, 0x07, 0x90, 0x02, 0x44, 0xF0, 0x54, 0x94, 0x07, 0x90, 0xF0, 0x44, 0xF0, 0x54, 0xE0, ++ 0x0D, 0x80, 0xF0, 0x02, 0x74, 0x79, 0x07, 0x90, 0x05, 0x80, 0xF0, 0x01, 0x79, 0x07, 0x90, 0xE4, ++ 0xA1, 0x07, 0x90, 0xF0, 0xF0, 0x08, 0x44, 0xE0, 0xF0, 0x20, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, ++ 0xE0, 0xA2, 0x07, 0x90, 0xE0, 0xF0, 0x08, 0x44, 0xE0, 0xF0, 0x20, 0x44, 0x90, 0xF0, 0x02, 0x44, ++ 0x54, 0xE0, 0x93, 0x07, 0x07, 0x90, 0xF0, 0xFE, 0xF7, 0x54, 0xE0, 0xA2, 0xDF, 0x54, 0xE0, 0xF0, ++ 0xFD, 0x54, 0xE0, 0xF0, 0x25, 0x12, 0x22, 0xF0, 0x75, 0x07, 0x50, 0xEF, 0x5C, 0x75, 0x26, 0x5B, ++ 0x5D, 0x75, 0x22, 0x92, 0x6A, 0x5E, 0x75, 0x02, 0x75, 0x26, 0x5B, 0x75, 0x71, 0x75, 0x92, 0x5C, ++ 0xFF, 0x7B, 0x22, 0x01, 0x7E, 0x79, 0x20, 0x7A, 0x90, 0xF8, 0x03, 0x12, 0x01, 0x74, 0xF3, 0x07, ++ 0xA2, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x3F, 0x74, 0x44, 0xE0, 0x93, 0x07, 0x01, 0x90, 0xF0, 0x01, ++ 0xC0, 0x54, 0xE0, 0xAE, 0x03, 0x06, 0x90, 0xF0, 0xF0, 0xFB, 0x54, 0xE0, 0xF0, 0xDF, 0x54, 0xE0, ++ 0x74, 0x20, 0x06, 0x90, 0x74, 0xA3, 0xF0, 0x80, 0x08, 0x90, 0xF0, 0xFF, 0xF0, 0xE4, 0xE0, 0x3E, ++ 0x75, 0x01, 0x5D, 0x75, 0x22, 0x22, 0xC5, 0x5E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x41, 0x47, 0x49, 0x47, 0x09, 0x09, 0x00, 0x0A, 0x2D, 0x49, 0x46, 0x4C, 0x65, 0x6D, 0x69, 0x54, ++ 0x00, 0x0A, 0x21, 0x72, 0x74, 0x65, 0x53, 0x09, 0x00, 0x0A, 0x70, 0x75, 0x0A, 0x50, 0x57, 0x09, ++ 0x47, 0x41, 0x09, 0x00, 0x09, 0x00, 0x0A, 0x43, 0x00, 0x3D, 0x47, 0x09, 0x00, 0x20, 0x64, 0x25, ++ 0x45, 0x09, 0x00, 0x0A, 0x00, 0x0A, 0x43, 0x58, 0x30, 0x4B, 0x4F, 0x09, 0x4F, 0x09, 0x00, 0x0A, ++ 0x00, 0x0A, 0x31, 0x4B, 0x32, 0x4B, 0x4F, 0x09, 0x4F, 0x09, 0x00, 0x0A, 0x00, 0x0A, 0x33, 0x4B, ++ 0x43, 0x44, 0x41, 0x09, 0x45, 0x09, 0x00, 0x0A, 0x53, 0x2D, 0x43, 0x58, 0x00, 0x23, 0x00, 0x0A, ++ 0x43, 0x4F, 0x4C, 0x09, 0x00, 0x0A, 0x31, 0x4B, 0x3A, 0x70, 0x09, 0x09, 0x00, 0x09, 0x64, 0x25, ++ 0x64, 0x25, 0x3A, 0x74, 0x3A, 0x6D, 0x00, 0x09, 0x6D, 0x00, 0x09, 0x78, 0x09, 0x64, 0x25, 0x3A, ++ 0x25, 0x3A, 0x64, 0x00, 0x09, 0x00, 0x0A, 0x44, 0x4B, 0x43, 0x4F, 0x4C, 0x09, 0x00, 0x0A, 0x32, ++ 0x4C, 0x3E, 0x2D, 0x09, 0x45, 0x4B, 0x43, 0x4F, 0x09, 0x00, 0x0A, 0x44, 0x4B, 0x43, 0x4F, 0x4C, ++ 0x09, 0x09, 0x0A, 0x33, 0x4E, 0x47, 0x49, 0x53, 0x64, 0x25, 0x00, 0x3A, 0x4E, 0x4C, 0x09, 0x00, ++ 0x0A, 0x50, 0x55, 0x4B, 0x78, 0x45, 0x09, 0x00, 0x00, 0x0A, 0x74, 0x69, 0x44, 0x4D, 0x09, 0x09, ++ 0x25, 0x3D, 0x4C, 0x4C, 0x08, 0x00, 0x0A, 0x64, 0x09, 0xAB, 0x08, 0x46, 0x8F, 0x75, 0x09, 0x10, ++ 0x9B, 0x09, 0x90, 0x23, 0x90, 0xF0, 0x17, 0x74, 0x2B, 0x74, 0x9A, 0x09, 0x26, 0x06, 0x90, 0xF0, ++ 0x54, 0x13, 0xC4, 0xE0, 0x03, 0xBF, 0xFF, 0x07, 0x80, 0x01, 0x7F, 0x04, 0xEF, 0x00, 0x7F, 0x02, ++ 0x33, 0x33, 0x01, 0x54, 0xFF, 0xF8, 0x54, 0x33, 0xE0, 0x99, 0x09, 0x90, 0xF0, 0x4F, 0xF7, 0x54, ++ 0x9C, 0x09, 0x90, 0xE4, 0x9E, 0x09, 0x90, 0xF0, 0x9F, 0x09, 0x90, 0xF0, 0xA0, 0x09, 0x90, 0xF0, ++ 0xA3, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x03, 0x74, 0xC3, 0xE0, 0xFF, 0x01, 0xA2, 0x09, 0x90, 0x13, ++ 0x74, 0x05, 0xE0, 0x30, 0x03, 0x80, 0xF0, 0x08, 0xE4, 0xF0, 0x0C, 0x74, 0x74, 0x08, 0x90, 0xFF, ++ 0x08, 0x90, 0xFE, 0xE0, 0xFE, 0x5E, 0xE0, 0x0F, 0xE0, 0xD9, 0x08, 0x90, 0x09, 0x90, 0xFE, 0x5E, ++ 0x64, 0x5E, 0xE0, 0x3E, 0xEF, 0x0A, 0x60, 0x03, 0x50, 0xFF, 0x94, 0xC3, 0x80, 0x0F, 0x00, 0x04, ++ 0x7A, 0xFF, 0x7B, 0xDC, 0xEF, 0xBC, 0x79, 0x20, 0x12, 0x00, 0x7C, 0xFD, 0x09, 0x90, 0xE5, 0x0C, ++ 0xF0, 0x43, 0x74, 0xAA, 0xF0, 0xAC, 0x09, 0x90, 0xF0, 0xAE, 0x09, 0x90, 0xF0, 0xB0, 0x09, 0x90, ++ 0x74, 0xB2, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x53, 0xF0, 0x03, 0x74, 0x95, 0xF0, 0x96, 0x09, 0x90, ++ 0xF0, 0x97, 0x09, 0x90, 0xF0, 0x98, 0x09, 0x90, 0x0F, 0x00, 0xFF, 0xE4, 0xE5, 0xFB, 0x80, 0xBF, ++ 0x90, 0x3E, 0x70, 0x23, 0x40, 0x74, 0xAA, 0x09, 0xAC, 0x09, 0x90, 0xF0, 0xAE, 0x09, 0x90, 0xF0, ++ 0xB0, 0x09, 0x90, 0xF0, 0xB2, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x50, 0x74, 0x04, 0x74, 0x95, 0x09, ++ 0x96, 0x09, 0x90, 0xF0, 0x97, 0x09, 0x90, 0xF0, 0x98, 0x09, 0x90, 0xF0, 0xFF, 0x01, 0x90, 0xF0, ++ 0x90, 0x13, 0xC3, 0xE0, 0xE0, 0x30, 0xA2, 0x09, 0xF0, 0x0B, 0x74, 0x04, 0xF0, 0x0F, 0x74, 0x22, ++ 0xAA, 0x09, 0x90, 0x22, 0x90, 0xF0, 0x42, 0x74, 0x90, 0xF0, 0xAC, 0x09, 0x90, 0xF0, 0xAE, 0x09, ++ 0x90, 0xF0, 0xB0, 0x09, 0x52, 0x74, 0xB2, 0x09, 0x08, 0x30, 0x22, 0xF0, 0x7A, 0xFF, 0x7B, 0x23, ++ 0x12, 0x14, 0x79, 0x20, 0x79, 0x78, 0xF8, 0x03, 0x60, 0x72, 0x78, 0xE6, 0x08, 0x1F, 0x76, 0x07, ++ 0x05, 0x80, 0x40, 0x76, 0x76, 0x08, 0x03, 0x76, 0xE6, 0x79, 0x78, 0xE8, 0x6F, 0x02, 0x12, 0xFF, ++ 0x0B, 0x12, 0x72, 0x7F, 0x78, 0x12, 0x50, 0xB2, 0x07, 0x60, 0xE6, 0x79, 0x75, 0x27, 0x5B, 0x75, ++ 0x75, 0x22, 0xC7, 0x5C, 0x5C, 0x75, 0x27, 0x5B, 0xFF, 0x7B, 0x22, 0x82, 0xB5, 0x79, 0x20, 0x7A, ++ 0x90, 0xF8, 0x03, 0x12, 0x54, 0xE0, 0xAE, 0x01, 0x07, 0x90, 0xF0, 0xC0, 0xF0, 0xFF, 0x74, 0xA8, ++ 0xE0, 0x93, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, 0x80, 0x74, 0x20, 0x06, 0xFF, 0x74, 0xA3, 0xF0, ++ 0x14, 0x06, 0x90, 0xF0, 0xF0, 0xDF, 0x54, 0xE0, 0xF0, 0xEF, 0x54, 0xE0, 0xE0, 0x03, 0x06, 0x90, ++ 0xE4, 0xF0, 0xDF, 0x54, 0x90, 0xCF, 0x11, 0xFF, 0x01, 0x74, 0xF3, 0x07, 0x01, 0x5D, 0x75, 0xF0, ++ 0x22, 0xC5, 0x5E, 0x75, 0x65, 0x60, 0x71, 0xE5, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x00, 0x79, ++ 0x21, 0x5B, 0x75, 0xF8, 0xD2, 0xEA, 0x5C, 0x75, 0x4B, 0x07, 0x90, 0x08, 0x90, 0xF0, 0x30, 0x74, ++ 0xD4, 0x74, 0x4C, 0x07, 0x12, 0xFF, 0xE4, 0xF0, 0x78, 0xE4, 0x8D, 0x03, 0xF6, 0x08, 0xF6, 0x72, ++ 0x78, 0xF6, 0x7E, 0x78, 0x08, 0x44, 0x76, 0x76, 0x06, 0x90, 0x5C, 0x76, 0x13, 0xC4, 0xE0, 0x26, ++ 0x94, 0xC3, 0x07, 0x54, 0x78, 0x06, 0x40, 0x03, 0x80, 0x01, 0x76, 0x79, 0x14, 0x06, 0x90, 0x14, ++ 0x13, 0x13, 0xC4, 0xE0, 0x00, 0x7F, 0x03, 0x54, 0x7F, 0x02, 0xE0, 0x30, 0xA6, 0x79, 0x78, 0x01, ++ 0xE6, 0x79, 0x78, 0x07, 0x07, 0x90, 0x07, 0x70, 0x20, 0x44, 0xE0, 0xA9, 0x12, 0x76, 0x7F, 0xF0, ++ 0x5B, 0x50, 0xB2, 0x0B, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x06, 0x79, 0x28, 0x06, 0x90, 0xF8, ++ 0x13, 0xC4, 0xFF, 0xE0, 0x60, 0x03, 0x54, 0x13, 0x08, 0x06, 0x90, 0x14, 0xE0, 0xA3, 0xFE, 0xE0, ++ 0xC3, 0xCE, 0x05, 0x78, 0xD8, 0x13, 0xCE, 0x13, 0x70, 0x0F, 0x54, 0xF9, 0x00, 0x90, 0xE4, 0x07, ++ 0x25, 0x80, 0xF0, 0xA1, 0xE0, 0xA1, 0x00, 0x90, 0x50, 0xFF, 0x94, 0xC3, 0xF0, 0x04, 0xE0, 0x1C, ++ 0xE0, 0x28, 0x06, 0x90, 0x54, 0x13, 0x13, 0xC4, 0x00, 0x90, 0xFF, 0x03, 0x9F, 0xC3, 0xE0, 0xA1, ++ 0x06, 0x90, 0x07, 0x40, 0x01, 0x44, 0xE0, 0x22, 0x22, 0x5B, 0x75, 0xF0, 0xAF, 0x2A, 0x5C, 0x75, ++ 0x54, 0xC4, 0xEF, 0x20, 0x22, 0xE0, 0x20, 0x0F, 0x20, 0xEF, 0x20, 0xAF, 0x20, 0xAF, 0x1C, 0xE0, ++ 0x20, 0x13, 0xC3, 0xEF, 0x20, 0xAF, 0x14, 0xE0, 0x54, 0x13, 0xC4, 0xEF, 0x0A, 0xE0, 0x20, 0x07, ++ 0x13, 0xEF, 0x20, 0xAF, 0x30, 0x3F, 0x54, 0x13, 0x5B, 0x75, 0x06, 0xE0, 0x2A, 0x5C, 0x75, 0x22, ++ 0x5C, 0x65, 0x60, 0xE5, 0x5F, 0xE5, 0x04, 0x70, 0x08, 0x60, 0x5B, 0x65, 0x85, 0x5F, 0x5B, 0x85, ++ 0x08, 0xD2, 0x60, 0x5C, 0x60, 0xA9, 0x5F, 0xAA, 0xC2, 0xFF, 0x02, 0x12, 0x01, 0x7F, 0x22, 0x08, ++ 0x20, 0x7B, 0x9A, 0x71, 0x7B, 0x9A, 0x71, 0x0F, 0xC4, 0xED, 0x0F, 0xC0, 0x44, 0xE0, 0x54, 0x33, ++ 0x09, 0x90, 0x4F, 0x10, 0x09, 0x90, 0xF0, 0xC2, 0xE4, 0xF0, 0xEB, 0xC3, 0xF0, 0xC4, 0x09, 0x90, ++ 0x02, 0x08, 0x20, 0x22, 0x09, 0x90, 0x51, 0x81, 0xF0, 0x03, 0x74, 0xB3, 0xF0, 0xB5, 0x09, 0x90, ++ 0x04, 0xB6, 0x09, 0x90, 0xB5, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x0D, 0x74, 0x04, 0x74, 0xB7, 0x09, ++ 0xBB, 0x09, 0x90, 0xF0, 0x05, 0x74, 0xF0, 0x14, 0xBC, 0x09, 0x90, 0xF0, 0x09, 0x90, 0xF0, 0x14, ++ 0xF0, 0x02, 0x74, 0xBD, 0x74, 0xBE, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x05, 0x90, 0xF0, 0x04, 0xB8, ++ 0x74, 0xE0, 0xB9, 0x09, 0x09, 0x90, 0xF0, 0x15, 0xF0, 0x05, 0x74, 0xBF, 0x74, 0xC1, 0x09, 0x90, ++ 0x09, 0x90, 0xF0, 0x20, 0xF0, 0x03, 0x74, 0xBA, 0x74, 0xB3, 0x09, 0x90, 0x7F, 0x7B, 0xF0, 0x01, ++ 0x04, 0x7F, 0xFD, 0xE4, 0xF0, 0x7B, 0x9A, 0x71, 0x7A, 0x78, 0x8E, 0x71, 0x05, 0x94, 0xC3, 0xE6, ++ 0x02, 0x50, 0xE0, 0x7F, 0x25, 0xEF, 0xF0, 0x7F, 0xFD, 0xE4, 0xFB, 0xE0, 0x9A, 0x71, 0x03, 0x7F, ++ 0xE4, 0x0D, 0x18, 0x7B, 0x7B, 0x9A, 0x71, 0xFF, 0x9A, 0x71, 0x0D, 0x40, 0xC2, 0x09, 0x90, 0xE4, ++ 0x7A, 0xFF, 0x7B, 0xF0, 0x12, 0x38, 0x79, 0x20, 0x72, 0x78, 0xF8, 0x03, 0x76, 0x08, 0x00, 0x76, ++ 0x12, 0x72, 0x7F, 0x7D, 0x06, 0x50, 0xB2, 0x0B, 0x75, 0x24, 0x5B, 0x75, 0x20, 0x22, 0x5F, 0x5C, ++ 0xFD, 0x81, 0x02, 0x08, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x3E, 0x79, 0x76, 0x72, 0x78, 0xF8, ++ 0x05, 0x76, 0x08, 0x00, 0x08, 0x00, 0x76, 0x08, 0xF0, 0x7B, 0x64, 0x76, 0x8E, 0x71, 0xFD, 0xE4, ++ 0xB7, 0x09, 0x90, 0xE4, 0xB8, 0x09, 0x90, 0xF0, 0xE4, 0xF0, 0x02, 0x74, 0xF0, 0xBC, 0x09, 0x90, ++ 0x74, 0xBE, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x05, 0x90, 0xE4, 0xF0, 0xCB, 0x90, 0xF0, 0xBD, 0x09, ++ 0x0D, 0x74, 0xB5, 0x09, 0xBB, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x90, 0xF0, 0xBF, 0x09, ++ 0xC0, 0x74, 0xC0, 0x09, 0xE6, 0x79, 0x78, 0xF0, 0x60, 0xEC, 0x09, 0x90, 0xF0, 0x01, 0x74, 0x11, ++ 0x74, 0xEB, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x05, 0xF0, 0x36, 0x74, 0xEA, 0xDC, 0x74, 0x0F, 0x80, ++ 0xEB, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x03, 0x74, 0x34, 0x74, 0xEA, 0x09, 0xE9, 0x09, 0x90, 0xF0, ++ 0x74, 0xF0, 0x03, 0x74, 0x06, 0x90, 0xF0, 0x01, 0x13, 0xC4, 0xE0, 0x26, 0xBF, 0xFF, 0x07, 0x54, ++ 0x09, 0x90, 0x0B, 0x03, 0x08, 0x44, 0xE0, 0xE9, 0x10, 0x44, 0xE0, 0xF0, 0x12, 0x72, 0x7F, 0xF0, ++ 0x02, 0x40, 0xB2, 0x0B, 0x09, 0x90, 0x46, 0xC1, 0xF0, 0x40, 0x74, 0xC2, 0xF6, 0x80, 0x78, 0xE4, ++ 0xE0, 0x46, 0x08, 0x90, 0x50, 0x2F, 0x94, 0xC3, 0x31, 0x08, 0x90, 0x1F, 0x40, 0x01, 0x94, 0xE0, ++ 0x2B, 0x08, 0x90, 0x17, 0xF0, 0x02, 0x44, 0xE0, 0x74, 0x07, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x0F, ++ 0x01, 0x44, 0xE0, 0x29, 0x1B, 0x80, 0x06, 0xF0, 0xE0, 0x2B, 0x08, 0x90, 0x90, 0xF0, 0xFD, 0x54, ++ 0x17, 0x74, 0x07, 0x08, 0x21, 0x08, 0x90, 0xF0, 0xF0, 0x04, 0x44, 0xE0, 0xE0, 0x29, 0x08, 0x90, ++ 0x90, 0xF0, 0xFE, 0x54, 0xC3, 0xE0, 0xAB, 0x08, 0x22, 0x50, 0x2F, 0x94, 0xE0, 0x96, 0x08, 0x90, ++ 0x1A, 0x40, 0x01, 0x94, 0xE0, 0x90, 0x08, 0x90, 0x90, 0xF0, 0x02, 0x44, 0x0F, 0x74, 0x6C, 0x08, ++ 0x8E, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0x06, 0x06, 0x80, 0x78, 0x08, 0x90, 0x1B, 0x80, ++ 0xFD, 0x54, 0xE0, 0x90, 0x6C, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x17, 0x74, 0x44, 0xE0, 0x86, 0x08, ++ 0x08, 0x90, 0xF0, 0x04, 0xFE, 0x54, 0xE0, 0x8E, 0x10, 0x09, 0x90, 0xF0, 0x2F, 0x94, 0xC3, 0xE0, ++ 0x08, 0x90, 0x24, 0x50, 0x01, 0x94, 0xE0, 0xFB, 0x08, 0x90, 0x1C, 0x40, 0x02, 0x44, 0xE0, 0xF5, ++ 0xD1, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x0F, 0x74, 0x44, 0xE0, 0xF3, 0x08, 0x80, 0x78, 0xF0, 0x01, ++ 0xF6, 0x26, 0x04, 0x74, 0x08, 0x90, 0x1B, 0x80, 0xFD, 0x54, 0xE0, 0xF5, 0xD1, 0x08, 0x90, 0xF0, ++ 0x90, 0xF0, 0x17, 0x74, 0x44, 0xE0, 0xEB, 0x08, 0x08, 0x90, 0xF0, 0x04, 0xFE, 0x54, 0xE0, 0xF3, ++ 0x75, 0x09, 0x90, 0xF0, 0x2F, 0x94, 0xC3, 0xE0, 0x09, 0x90, 0x24, 0x50, 0x01, 0x94, 0xE0, 0x60, ++ 0x09, 0x90, 0x1C, 0x40, 0x02, 0x44, 0xE0, 0x5A, 0x36, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x0F, 0x74, ++ 0x44, 0xE0, 0x58, 0x09, 0x80, 0x78, 0xF0, 0x01, 0xF6, 0x26, 0x08, 0x74, 0x09, 0x90, 0x1B, 0x80, ++ 0xFD, 0x54, 0xE0, 0x5A, 0x36, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x17, 0x74, 0x44, 0xE0, 0x50, 0x09, ++ 0x09, 0x90, 0xF0, 0x04, 0xFE, 0x54, 0xE0, 0x58, 0xE6, 0x80, 0x78, 0xF0, 0x09, 0x60, 0x0F, 0x64, ++ 0x00, 0x76, 0x74, 0x78, 0x80, 0x64, 0x76, 0x08, 0x12, 0x74, 0x7F, 0x0D, 0x06, 0x50, 0xB2, 0x0B, ++ 0x75, 0x27, 0x5B, 0x75, 0x09, 0x90, 0x06, 0x5C, 0x08, 0x44, 0xE0, 0xB5, 0x05, 0x22, 0x75, 0xF0, ++ 0xE5, 0xC2, 0x09, 0x90, 0x08, 0x90, 0xF0, 0x22, 0x24, 0xF5, 0xE0, 0x31, 0xE0, 0x32, 0x08, 0x90, ++ 0x08, 0x90, 0x25, 0xF5, 0x26, 0xF5, 0xE0, 0x96, 0xE0, 0x97, 0x08, 0x90, 0x08, 0x90, 0x27, 0xF5, ++ 0x28, 0xF5, 0xE0, 0xFB, 0xE0, 0xFC, 0x08, 0x90, 0x09, 0x90, 0x29, 0xF5, 0x2A, 0xF5, 0xE0, 0x60, ++ 0xE0, 0x61, 0x09, 0x90, 0xF5, 0xE4, 0x2B, 0xF5, 0x25, 0x23, 0xE5, 0x23, 0xF8, 0x24, 0x24, 0xE0, ++ 0xFC, 0xE6, 0x00, 0xC0, 0xAE, 0xFD, 0xE6, 0x08, 0xCE, 0x0A, 0x78, 0x04, 0xCE, 0x13, 0xE7, 0xA2, ++ 0xFF, 0xF8, 0xD8, 0x13, 0xFF, 0x9F, 0xED, 0xC3, 0x00, 0xD0, 0x9E, 0xEC, 0x07, 0xA6, 0x08, 0xF6, ++ 0x23, 0xE5, 0x23, 0x05, 0xE5, 0xD2, 0x04, 0xB4, 0x90, 0x10, 0x44, 0x22, 0x90, 0xF0, 0xC2, 0x09, ++ 0x24, 0xE5, 0x2F, 0x08, 0x30, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x25, 0xE5, 0x26, 0xE5, 0x94, 0x08, ++ 0x95, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x27, 0xE5, 0x28, 0xE5, 0xF9, 0x08, 0xFA, 0x08, 0x90, 0xF0, ++ 0x90, 0xF0, 0x29, 0xE5, 0x2A, 0xE5, 0x5E, 0x09, 0x5F, 0x09, 0x90, 0xF0, 0xE4, 0xF0, 0x2B, 0xE5, ++ 0xF0, 0xC2, 0x09, 0x90, 0x22, 0xE5, 0x22, 0x05, 0x02, 0x60, 0x0A, 0x64, 0x09, 0x90, 0x50, 0xC1, ++ 0xF7, 0x54, 0xE0, 0xB5, 0x08, 0x30, 0x22, 0xF0, 0x7A, 0xFF, 0x7B, 0x31, 0x12, 0x44, 0x79, 0x20, ++ 0x72, 0x78, 0xF8, 0x03, 0x76, 0x08, 0x01, 0x76, 0xB5, 0x09, 0x90, 0xF4, 0xF0, 0xFB, 0x54, 0xE0, ++ 0x54, 0xE6, 0x79, 0x78, 0x33, 0x33, 0x33, 0x01, 0x90, 0xFF, 0xF8, 0x54, 0x54, 0xE0, 0xE9, 0x09, ++ 0x90, 0xF0, 0x4F, 0xF7, 0x54, 0xE0, 0xB8, 0x09, 0x46, 0xD1, 0xF0, 0xFD, 0x74, 0xC2, 0x09, 0x90, ++ 0x08, 0x90, 0xF0, 0x40, 0x94, 0xD3, 0xE0, 0x31, 0x90, 0x1B, 0x40, 0x01, 0xD3, 0xE0, 0x96, 0x08, ++ 0x12, 0x40, 0x01, 0x94, 0xE0, 0xFB, 0x08, 0x90, 0x40, 0x01, 0x94, 0xD3, 0x60, 0x09, 0x90, 0x09, ++ 0x01, 0x94, 0xD3, 0xE0, 0x5B, 0x75, 0x07, 0x50, 0xB1, 0x5C, 0x75, 0x23, 0x12, 0x72, 0x7F, 0x22, ++ 0x0D, 0x50, 0xB2, 0x0B, 0xE0, 0xB5, 0x09, 0x90, 0x75, 0xF0, 0x08, 0x44, 0x5C, 0x75, 0x28, 0x5B, ++ 0x08, 0x30, 0x22, 0xE7, 0x7A, 0xFF, 0x7B, 0x10, 0x12, 0x1C, 0x79, 0x20, 0x72, 0x78, 0xF8, 0x03, ++ 0x76, 0x08, 0x05, 0x76, 0x47, 0x08, 0x90, 0xDC, 0x0A, 0x94, 0xD3, 0xE0, 0x08, 0x90, 0x1B, 0x40, ++ 0x94, 0xD3, 0xE0, 0xAC, 0x90, 0x12, 0x40, 0x0A, 0xD3, 0xE0, 0x11, 0x09, 0x09, 0x40, 0x0A, 0x94, ++ 0xE0, 0x76, 0x09, 0x90, 0x50, 0x0A, 0x94, 0xD3, 0x12, 0x72, 0x7F, 0x07, 0x06, 0x50, 0xB2, 0x0B, ++ 0x75, 0x27, 0x5B, 0x75, 0x30, 0x22, 0xC7, 0x5C, 0xFF, 0x7B, 0x11, 0x08, 0x21, 0x79, 0x20, 0x7A, ++ 0x78, 0xF8, 0x03, 0x12, 0x08, 0x00, 0x76, 0x72, 0x7F, 0x22, 0x0A, 0x76, 0xB2, 0x0B, 0x12, 0x72, ++ 0x72, 0x78, 0x1E, 0x50, 0x76, 0x08, 0x00, 0x76, 0x01, 0x28, 0x12, 0x05, 0x79, 0x78, 0x12, 0x50, ++ 0x75, 0x07, 0x60, 0xE6, 0x5C, 0x75, 0x28, 0x5B, 0x5B, 0x75, 0x22, 0xC4, 0xB1, 0x5C, 0x75, 0x23, ++ 0x47, 0x08, 0x90, 0x22, 0xF5, 0xE4, 0x0C, 0xD2, 0x25, 0x7A, 0x74, 0x22, 0xD3, 0xE6, 0xF8, 0x22, ++ 0x0E, 0x40, 0x00, 0x94, 0x12, 0x94, 0xD3, 0xE0, 0x7A, 0x74, 0x08, 0x40, 0x16, 0xF8, 0x22, 0x25, ++ 0x65, 0x74, 0x0C, 0xC2, 0x82, 0xF5, 0x82, 0x25, 0xF5, 0x83, 0x35, 0xE4, 0xE5, 0x22, 0x05, 0x83, ++ 0xD5, 0x04, 0xB4, 0x22, 0xE0, 0xF2, 0x07, 0x90, 0x7A, 0x24, 0x03, 0x54, 0x07, 0x54, 0xE6, 0xF8, ++ 0x00, 0x0D, 0x90, 0xFF, 0x4F, 0xF8, 0x54, 0xE0, 0xF2, 0x07, 0x90, 0xF0, 0xFF, 0x03, 0x54, 0xE0, ++ 0x9F, 0x01, 0x74, 0xC3, 0x2F, 0x7A, 0x74, 0xFF, 0x07, 0x54, 0xE6, 0xF8, 0x20, 0x0D, 0x90, 0xFF, ++ 0x4F, 0xF8, 0x54, 0xE0, 0xF2, 0x07, 0x90, 0xF0, 0x03, 0x54, 0xC4, 0xE0, 0xE6, 0xF8, 0x7A, 0x24, ++ 0x90, 0xFF, 0x07, 0x54, 0x54, 0xE0, 0x40, 0x0D, 0x90, 0xF0, 0x4F, 0xF8, 0xC4, 0xE0, 0xF2, 0x07, ++ 0xC3, 0xFF, 0x03, 0x54, 0xFF, 0x9F, 0x05, 0x74, 0xF8, 0x2F, 0x7A, 0x74, 0xFF, 0x07, 0x54, 0xE6, ++ 0xE0, 0x60, 0x0D, 0x90, 0xF0, 0x4F, 0xF8, 0x54, 0x7B, 0x26, 0x0C, 0x30, 0x79, 0x20, 0x7A, 0xFF, ++ 0xF8, 0x03, 0x12, 0x27, 0x7B, 0x22, 0xF5, 0xE4, 0x79, 0x20, 0x7A, 0xFF, 0x25, 0x7A, 0x74, 0x2C, ++ 0x0C, 0x12, 0xF8, 0x22, 0xE5, 0x22, 0x05, 0xE1, 0x04, 0x94, 0xC3, 0x22, 0x03, 0x12, 0xE9, 0x40, ++ 0x22, 0x0C, 0xA2, 0xF2, 0x7B, 0x12, 0x08, 0x30, 0x79, 0x20, 0x7A, 0xFF, 0xF8, 0x03, 0x12, 0x32, ++ 0x00, 0x76, 0x72, 0x78, 0x31, 0x32, 0x76, 0x08, 0x12, 0x72, 0x7F, 0xB3, 0x06, 0x50, 0xB2, 0x0B, ++ 0x75, 0x23, 0x5B, 0x75, 0x30, 0x22, 0xB1, 0x5C, 0xFF, 0x7B, 0x1E, 0x08, 0x4A, 0x79, 0x20, 0x7A, ++ 0x78, 0xF8, 0x03, 0x12, 0x08, 0x01, 0x76, 0x72, 0x09, 0x90, 0xF4, 0x76, 0x07, 0x44, 0xE0, 0xD7, ++ 0xD6, 0x09, 0x90, 0xF0, 0xF0, 0x03, 0x44, 0xE0, 0xE0, 0x29, 0x06, 0x90, 0x3F, 0x54, 0x13, 0x13, ++ 0x90, 0x4C, 0xE0, 0x30, 0xC4, 0xE0, 0x02, 0x0D, 0x94, 0xC3, 0x07, 0x54, 0xE0, 0x1A, 0x50, 0x03, ++ 0x0F, 0x54, 0xC4, 0xFF, 0x8F, 0x54, 0xEF, 0xFE, 0x54, 0x04, 0xEE, 0xFF, 0xF0, 0x54, 0xC4, 0x07, ++ 0x02, 0x7F, 0xF0, 0x4F, 0x0B, 0x12, 0x0D, 0x7E, 0x05, 0x0D, 0x90, 0xD1, 0x07, 0x54, 0xC4, 0xE0, ++ 0x50, 0x02, 0x94, 0xC3, 0xC4, 0xFF, 0xE0, 0x1A, 0xEF, 0xFE, 0x0F, 0x54, 0xEE, 0xFF, 0x8F, 0x54, ++ 0xC4, 0x07, 0x54, 0x04, 0xF0, 0x4F, 0xF0, 0x54, 0x0D, 0x7E, 0x05, 0x7F, 0x78, 0xD1, 0x0B, 0x12, ++ 0x08, 0xFE, 0xE6, 0x72, 0x00, 0x7C, 0xFF, 0xE6, 0x02, 0x12, 0x32, 0x7D, 0x70, 0x4C, 0xED, 0xAA, ++ 0xE6, 0x79, 0x78, 0x28, 0x09, 0x90, 0x0C, 0x70, 0x94, 0xC3, 0xE0, 0xEB, 0xE0, 0x03, 0x50, 0x05, ++ 0x08, 0x90, 0xF0, 0x04, 0x0F, 0x54, 0xE0, 0x56, 0x50, 0x05, 0x94, 0xC3, 0x0F, 0x54, 0xE0, 0x0C, ++ 0x44, 0x0F, 0x54, 0x04, 0xEA, 0x09, 0x90, 0x30, 0x12, 0x72, 0x7F, 0xF0, 0x12, 0x50, 0xB2, 0x0B, ++ 0x60, 0xE6, 0x79, 0x78, 0x2B, 0x5B, 0x75, 0x07, 0x22, 0x26, 0x5C, 0x75, 0x75, 0x29, 0x5B, 0x75, ++ 0x90, 0x22, 0xEF, 0x5C, 0x02, 0x74, 0x95, 0x09, 0x26, 0x06, 0x90, 0xF0, 0x54, 0x13, 0xC4, 0xE0, ++ 0x03, 0x94, 0xC3, 0x07, 0x06, 0x90, 0x1A, 0x50, 0x13, 0x13, 0xE0, 0x29, 0xE0, 0x30, 0x3F, 0x54, ++ 0xE6, 0x7A, 0x78, 0x08, 0x40, 0x03, 0x94, 0xD3, 0x96, 0x09, 0x90, 0x07, 0x05, 0x80, 0x02, 0x74, ++ 0x74, 0x96, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x0C, 0x09, 0x90, 0xF0, 0x97, 0x30, 0x22, 0xF0, 0x98, ++ 0xFF, 0x7B, 0x5B, 0x08, 0x56, 0x79, 0x20, 0x7A, 0x90, 0xF8, 0x03, 0x12, 0x44, 0xE0, 0xAF, 0x07, ++ 0x54, 0xE0, 0xF0, 0x02, 0x90, 0xE4, 0xF0, 0xFD, 0x90, 0xF0, 0xD2, 0x09, 0x7F, 0xF0, 0x01, 0x0D, ++ 0x12, 0x0D, 0x7E, 0x01, 0x09, 0x90, 0xD1, 0x0B, 0xF0, 0x02, 0x74, 0x9C, 0xF0, 0x9D, 0x09, 0x90, ++ 0xF0, 0x9E, 0x09, 0x90, 0xF0, 0x9F, 0x09, 0x90, 0xF0, 0xA0, 0x09, 0x90, 0x01, 0x76, 0x72, 0x78, ++ 0x31, 0x00, 0x76, 0x08, 0xA8, 0x00, 0x90, 0xB3, 0x64, 0xD3, 0xFF, 0xE0, 0x40, 0x80, 0x94, 0x80, ++ 0xA6, 0x85, 0x78, 0x06, 0xEF, 0x06, 0x80, 0x07, 0x85, 0x78, 0x04, 0xF4, 0x78, 0xE8, 0xC2, 0xF6, ++ 0x13, 0xFF, 0xE6, 0x85, 0x1F, 0x54, 0x13, 0x13, 0xE6, 0x85, 0x78, 0xF6, 0x40, 0x00, 0x94, 0xD3, ++ 0x46, 0x08, 0x90, 0x67, 0x50, 0x28, 0x94, 0xE0, 0xAB, 0x08, 0x90, 0x51, 0x28, 0x94, 0xC3, 0xE0, ++ 0x09, 0x90, 0x48, 0x50, 0x94, 0xC3, 0xE0, 0x10, 0x90, 0x3F, 0x50, 0x28, 0xC3, 0xE0, 0x75, 0x09, ++ 0x36, 0x50, 0x28, 0x94, 0xE0, 0xA8, 0x00, 0x90, 0x90, 0x0E, 0x71, 0xFF, 0x2F, 0xE0, 0x3E, 0x08, ++ 0xA9, 0x00, 0x90, 0xF0, 0x0E, 0x71, 0xFF, 0xE0, 0xE0, 0xA3, 0x08, 0x90, 0x00, 0x90, 0xF0, 0x2F, ++ 0x71, 0xFF, 0xE0, 0xAA, 0x08, 0x09, 0x90, 0x0E, 0x90, 0xF0, 0x2F, 0xE0, 0xFF, 0xE0, 0xAB, 0x00, ++ 0x09, 0x90, 0x0E, 0x71, 0xF0, 0x2F, 0xE0, 0x6D, 0xFF, 0x7B, 0x09, 0x80, 0x5E, 0x79, 0x20, 0x7A, ++ 0x78, 0xF8, 0x03, 0x12, 0x91, 0x80, 0x16, 0x85, 0xE0, 0xA8, 0x00, 0x90, 0xF0, 0x3E, 0x08, 0x90, ++ 0xE0, 0xA9, 0x00, 0x90, 0xF0, 0xA3, 0x08, 0x90, 0xE0, 0xAA, 0x00, 0x90, 0xF0, 0x08, 0x09, 0x90, ++ 0xE0, 0xAB, 0x00, 0x90, 0xF0, 0x6D, 0x09, 0x90, 0x9C, 0x09, 0x90, 0xE4, 0x9D, 0x09, 0x90, 0xF0, ++ 0x9E, 0x09, 0x90, 0xF0, 0x9F, 0x09, 0x90, 0xF0, 0xA0, 0x09, 0x90, 0xF0, 0x75, 0xE8, 0xD2, 0xF0, ++ 0x5C, 0x75, 0x2B, 0x5B, 0x7A, 0xFF, 0x7B, 0x26, 0x02, 0x30, 0x79, 0x20, 0xEF, 0xD3, 0xF8, 0x03, ++ 0x80, 0x94, 0x80, 0x64, 0x08, 0x7F, 0x03, 0x40, 0x64, 0xEF, 0xC3, 0x22, 0x7F, 0x80, 0x94, 0x80, ++ 0x7F, 0x02, 0x50, 0x00, 0x08, 0x30, 0x22, 0xF8, 0x7A, 0xFF, 0x7B, 0x10, 0x12, 0x50, 0x79, 0x20, ++ 0x72, 0x78, 0xF8, 0x03, 0x76, 0x08, 0x00, 0x76, 0x29, 0x06, 0x90, 0x0A, 0x13, 0x13, 0xFF, 0xE0, ++ 0xE0, 0x30, 0x3F, 0x54, 0x7F, 0x55, 0x71, 0x02, 0xB2, 0x0B, 0x12, 0x72, 0x5B, 0x75, 0x06, 0x50, ++ 0x16, 0x5C, 0x75, 0x2C, 0x0D, 0x22, 0x75, 0x22, 0x75, 0x0A, 0x23, 0x75, 0x25, 0x75, 0x0D, 0x24, ++ 0xE4, 0x0C, 0xD2, 0x06, 0x60, 0x14, 0xED, 0xFD, 0x16, 0x60, 0x14, 0x0D, 0x1B, 0x70, 0x02, 0x24, ++ 0xE0, 0xF2, 0x07, 0x90, 0x07, 0x90, 0x11, 0x80, 0x03, 0x54, 0xE0, 0xF2, 0x01, 0x74, 0xC3, 0xFF, ++ 0x07, 0x90, 0x14, 0x80, 0x54, 0xC4, 0xE0, 0xF2, 0x90, 0x0C, 0x80, 0x03, 0xC4, 0xE0, 0xF2, 0x07, ++ 0xC3, 0xFF, 0x03, 0x54, 0x25, 0x9F, 0x05, 0x74, 0xF5, 0xC7, 0x24, 0xE0, 0x20, 0x34, 0xE4, 0x82, ++ 0x93, 0xE4, 0x83, 0xF5, 0x93, 0x01, 0x74, 0xFE, 0x82, 0x23, 0x85, 0xFF, 0xE0, 0x83, 0x22, 0x85, ++ 0xD3, 0x0F, 0x54, 0xC4, 0x3D, 0x40, 0x06, 0x94, 0x83, 0x8E, 0x82, 0x8F, 0x50, 0x0C, 0x94, 0xE0, ++ 0x82, 0x25, 0x85, 0x34, 0xE0, 0x83, 0x24, 0x85, 0x0F, 0x54, 0xC4, 0xFC, 0x0F, 0x54, 0xEC, 0xFB, ++ 0x54, 0x14, 0xEB, 0xFC, 0xF0, 0x54, 0xC4, 0x0F, 0x23, 0x85, 0xF0, 0x4C, 0x83, 0x22, 0x85, 0x82, ++ 0x54, 0xC4, 0xFC, 0xE0, 0x54, 0xEC, 0xFB, 0x0F, 0x14, 0xEB, 0xFC, 0x0F, 0x54, 0xC4, 0x0F, 0x54, ++ 0xC2, 0xF0, 0x4C, 0xF0, 0x25, 0x20, 0x74, 0x0C, 0xE4, 0x25, 0xF5, 0x25, 0x24, 0xF5, 0x24, 0x35, ++ 0x23, 0x25, 0x20, 0x74, 0x35, 0xE4, 0x23, 0xF5, 0x0D, 0x22, 0xF5, 0x22, 0x60, 0x04, 0x64, 0xED, ++ 0xA2, 0x65, 0x61, 0x02, 0x08, 0x30, 0x22, 0x0C, 0x7A, 0xFF, 0x7B, 0x59, 0x12, 0x60, 0x79, 0x20, ++ 0x90, 0xE4, 0xF8, 0x03, 0x90, 0xF0, 0xAA, 0x07, 0x10, 0x74, 0xAB, 0x07, 0xB4, 0x07, 0x90, 0xF0, ++ 0x90, 0xF0, 0xE4, 0x74, 0x44, 0xE0, 0xAE, 0x07, 0x07, 0x90, 0xF0, 0x01, 0x01, 0x44, 0xE0, 0xAF, ++ 0xB1, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x12, 0x74, 0x90, 0xF0, 0xB2, 0x07, 0x54, 0xE0, 0xAF, 0x07, ++ 0x07, 0x90, 0xF0, 0xFE, 0xEF, 0x54, 0xE0, 0xA9, 0xA7, 0x07, 0x90, 0xF0, 0xF0, 0xDF, 0x54, 0xE0, ++ 0xF6, 0x82, 0x78, 0xE4, 0x18, 0xF6, 0x84, 0x78, 0x81, 0x78, 0x01, 0x76, 0x86, 0x78, 0x01, 0x76, ++ 0x07, 0x90, 0x22, 0xF6, 0x02, 0x60, 0xE0, 0xAC, 0x83, 0x78, 0xF8, 0x81, 0x13, 0xE7, 0xA2, 0xE6, ++ 0xE0, 0x95, 0x33, 0xFF, 0x30, 0x01, 0x7E, 0xE6, 0xFF, 0x7E, 0x02, 0xE0, 0xA4, 0xF0, 0x8F, 0xEE, ++ 0xE6, 0x81, 0x78, 0xFF, 0xA6, 0xF8, 0x86, 0x24, 0x7A, 0xFF, 0x7B, 0x07, 0x78, 0x68, 0x79, 0x20, ++ 0xE1, 0x0C, 0x12, 0x81, 0x20, 0x7A, 0xFF, 0x7B, 0x0C, 0x12, 0x70, 0x79, 0xE6, 0x81, 0x78, 0xDF, ++ 0x03, 0xB4, 0xFF, 0x7B, 0x79, 0x20, 0x7A, 0x09, 0xF8, 0x03, 0x12, 0x76, 0x20, 0x7A, 0x09, 0x80, ++ 0x84, 0x78, 0x7B, 0x79, 0x7B, 0xE1, 0x0C, 0x12, 0x79, 0x20, 0x7A, 0xFF, 0xE6, 0x81, 0x78, 0x81, ++ 0xE6, 0xF8, 0x86, 0x24, 0xE0, 0x95, 0x33, 0xFD, 0xE5, 0x0C, 0x12, 0xFC, 0xC3, 0xE6, 0x81, 0x78, ++ 0x0C, 0x50, 0x03, 0x94, 0xF6, 0x08, 0xE4, 0x06, 0x18, 0xF6, 0x84, 0x78, 0x50, 0x80, 0x01, 0x76, ++ 0x75, 0x2D, 0x5B, 0x75, 0x48, 0x80, 0xFB, 0x5C, 0xC3, 0xE6, 0x81, 0x78, 0x00, 0x7E, 0x03, 0x94, ++ 0x01, 0x7F, 0x04, 0x50, 0x00, 0x7F, 0x02, 0x80, 0xC3, 0xE6, 0x84, 0x78, 0x80, 0x64, 0xEE, 0x9F, ++ 0x98, 0x80, 0x74, 0xF8, 0x84, 0x78, 0x05, 0x50, 0xE4, 0x25, 0x80, 0x06, 0x78, 0xF6, 0x84, 0x78, ++ 0x94, 0xC3, 0xE6, 0x82, 0x06, 0x03, 0x50, 0x01, 0x78, 0xE4, 0x16, 0x80, 0x08, 0xC3, 0xF6, 0x82, ++ 0x94, 0x80, 0x64, 0xE6, 0x06, 0x03, 0x50, 0x8A, 0x5B, 0x75, 0x06, 0x80, 0xB1, 0x5C, 0x75, 0x23, ++ 0xC4, 0xE6, 0x81, 0x78, 0x07, 0x90, 0xF0, 0x54, 0xE6, 0x08, 0xF0, 0xAB, 0xF0, 0xAA, 0x07, 0x90, ++ 0x01, 0x64, 0xE6, 0x18, 0x84, 0x78, 0x1E, 0x70, 0xFF, 0x03, 0x54, 0xE6, 0xE0, 0xB4, 0x07, 0x90, ++ 0xF0, 0x4F, 0xFC, 0x54, 0x96, 0x01, 0x74, 0xC3, 0xE0, 0x25, 0x03, 0x54, 0xE0, 0xFF, 0xE0, 0x25, ++ 0xF0, 0x4F, 0xF3, 0x54, 0x64, 0xE6, 0x81, 0x78, 0x78, 0x24, 0x70, 0x02, 0x02, 0x24, 0xE6, 0x84, ++ 0x54, 0xC4, 0x03, 0x54, 0x07, 0x90, 0xFF, 0xF0, 0xCF, 0x54, 0xE0, 0xB4, 0x74, 0xC3, 0xF0, 0x4F, ++ 0x03, 0x54, 0x96, 0x03, 0x54, 0x33, 0x33, 0xC4, 0x54, 0xE0, 0xFF, 0xC0, 0x78, 0xF0, 0x4F, 0x3F, ++ 0xE7, 0xA2, 0xE6, 0x83, 0x78, 0x02, 0x24, 0x13, 0x83, 0x78, 0xF6, 0x85, 0x22, 0xE0, 0x30, 0xE6, ++ 0xE0, 0xB4, 0x07, 0x90, 0x85, 0x78, 0x03, 0x54, 0x44, 0xE6, 0x05, 0x70, 0xE6, 0x08, 0x80, 0x10, ++ 0x54, 0x33, 0x33, 0x33, 0x90, 0x02, 0x44, 0xF8, 0x90, 0xF0, 0xB1, 0x07, 0x12, 0x74, 0xB2, 0x07, ++ 0x07, 0x90, 0x22, 0xF0, 0x03, 0x54, 0xE0, 0xB4, 0x0A, 0x70, 0x85, 0x78, 0x33, 0x33, 0x33, 0xE6, ++ 0x02, 0x44, 0xF8, 0x54, 0x44, 0xE6, 0x03, 0x80, 0xB1, 0x07, 0x90, 0x10, 0xE6, 0x85, 0x78, 0xF0, ++ 0x54, 0x33, 0x33, 0x33, 0x07, 0x90, 0x46, 0xF8, 0x20, 0x22, 0xF0, 0xB2, 0x90, 0xC1, 0x02, 0x08, ++ 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x87, 0x79, 0x76, 0x83, 0x78, 0xF8, 0x76, 0x81, 0x78, 0x7F, ++ 0xE6, 0x81, 0x78, 0x01, 0xD3, 0xF9, 0x86, 0x24, 0xF5, 0x80, 0x64, 0xE7, 0xE6, 0x83, 0x78, 0xF0, ++ 0xF0, 0x95, 0x80, 0x64, 0x81, 0x78, 0x0A, 0x40, 0xF8, 0x86, 0x24, 0xE6, 0xF6, 0x83, 0x78, 0xE6, ++ 0xE6, 0x06, 0x81, 0x78, 0x90, 0xDA, 0x04, 0xB4, 0x13, 0xE0, 0xB4, 0x07, 0x24, 0x03, 0x54, 0x13, ++ 0xE7, 0xC3, 0xF9, 0x86, 0x24, 0x96, 0x83, 0x78, 0x33, 0x33, 0x33, 0x02, 0xE0, 0xFF, 0xF8, 0x54, ++ 0x86, 0x24, 0x03, 0x54, 0x96, 0xE7, 0xC3, 0xF9, 0x90, 0x4F, 0x02, 0x24, 0x90, 0xF0, 0xB1, 0x07, ++ 0xC4, 0xE0, 0xB4, 0x07, 0x03, 0x54, 0x13, 0x13, 0xC3, 0xF9, 0x86, 0x24, 0x02, 0x24, 0x96, 0xE7, ++ 0x54, 0x33, 0x33, 0x33, 0xC4, 0xE0, 0xFF, 0xF8, 0x86, 0x24, 0x03, 0x54, 0x96, 0xE7, 0xC3, 0xF9, ++ 0x90, 0x4F, 0x02, 0x24, 0x78, 0xF0, 0xB2, 0x07, 0x08, 0x00, 0x76, 0x72, 0x4A, 0x80, 0x0A, 0x76, ++ 0xE0, 0xAC, 0x07, 0x90, 0x5B, 0x75, 0x0F, 0x70, 0xE2, 0x5C, 0x75, 0x2E, 0x20, 0x7A, 0xFF, 0x7B, ++ 0x03, 0x02, 0x8F, 0x79, 0x12, 0x72, 0x7F, 0xF8, 0x07, 0x50, 0xB2, 0x0B, 0x75, 0x23, 0x5B, 0x75, ++ 0x90, 0x22, 0xB1, 0x5C, 0x7F, 0xE0, 0xAA, 0x07, 0x02, 0xE0, 0x20, 0x00, 0x54, 0xEF, 0x01, 0x7F, ++ 0x07, 0x90, 0xFF, 0x01, 0xFE, 0x54, 0xE0, 0xAA, 0x54, 0xE0, 0xF0, 0x4F, 0x78, 0xE4, 0xF0, 0xFD, ++ 0x78, 0x00, 0xF6, 0x83, 0xB4, 0xE6, 0x06, 0x83, 0x07, 0x90, 0xF8, 0x40, 0x02, 0x44, 0xE0, 0xAA, ++ 0x08, 0x30, 0x22, 0xF0, 0x7A, 0xFF, 0x7B, 0x1F, 0x12, 0x9B, 0x79, 0x20, 0x07, 0x90, 0xF8, 0x03, ++ 0xCF, 0x54, 0xE0, 0xAB, 0xF0, 0x54, 0xE0, 0xF0, 0x40, 0x44, 0xE0, 0xF0, 0x82, 0x78, 0xE4, 0xF0, ++ 0x22, 0xF6, 0x18, 0xF6, 0xE0, 0xAC, 0x07, 0x90, 0xFF, 0x7B, 0x22, 0x70, 0xAA, 0x79, 0x20, 0x7A, ++ 0x78, 0xDF, 0x0C, 0x12, 0x94, 0xC3, 0xE6, 0x81, 0x06, 0x06, 0x50, 0x03, 0x80, 0xF6, 0x08, 0xE4, ++ 0x2F, 0x5B, 0x75, 0x42, 0x12, 0x75, 0x5C, 0x75, 0x37, 0x80, 0xF2, 0x03, 0xC3, 0xE6, 0x82, 0x78, ++ 0x29, 0x50, 0x01, 0x94, 0xAB, 0x07, 0x90, 0x06, 0xE6, 0x18, 0xFF, 0xE0, 0xFD, 0xE6, 0x08, 0xFE, ++ 0x80, 0x08, 0x06, 0xA8, 0xD8, 0x33, 0xC3, 0x02, 0x54, 0xEF, 0xFE, 0xFC, 0x54, 0xEF, 0xFD, 0x0F, ++ 0x2E, 0xED, 0xFF, 0xF0, 0x90, 0x4F, 0x0F, 0x54, 0x80, 0xF0, 0xAB, 0x07, 0x23, 0x5B, 0x75, 0x06, ++ 0x78, 0xB1, 0x5C, 0x75, 0x03, 0x54, 0xE6, 0x81, 0xFF, 0xF0, 0x54, 0xC4, 0xE0, 0xAB, 0x07, 0x90, ++ 0xF0, 0x4F, 0xCF, 0x54, 0x09, 0x08, 0x30, 0x22, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0xAD, 0x79, ++ 0x00, 0x90, 0xE4, 0xF8, 0x5D, 0x75, 0xF0, 0xA1, 0x65, 0x5E, 0x75, 0x02, 0x75, 0x01, 0x71, 0x75, ++ 0x5C, 0x75, 0x22, 0x5B, 0x9B, 0x09, 0x90, 0x2A, 0x44, 0x1F, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x80, ++ 0x10, 0x44, 0xE0, 0xA9, 0xBA, 0x09, 0x90, 0xF0, 0x44, 0xF9, 0x54, 0xE0, 0x22, 0x22, 0xF0, 0x04, ++ 0x41, 0x52, 0x54, 0x09, 0x00, 0x0A, 0x4B, 0x43, 0x41, 0x42, 0x09, 0x09, 0x49, 0x53, 0x5F, 0x44, ++ 0x09, 0x00, 0x0A, 0x47, 0x3A, 0x64, 0x25, 0x09, 0x64, 0x25, 0x20, 0x00, 0x64, 0x25, 0x20, 0x00, ++ 0x00, 0x42, 0x64, 0x20, 0x20, 0x44, 0x25, 0x20, 0x00, 0x6D, 0x70, 0x70, 0x00, 0x44, 0x25, 0x20, ++ 0x09, 0x09, 0x00, 0x0A, 0x2D, 0x2D, 0x2D, 0x2D, 0x0A, 0x00, 0x0A, 0x2D, 0x31, 0x08, 0x00, 0x0A, ++ 0xFB, 0x08, 0x96, 0x08, 0x59, 0x08, 0x60, 0x09, 0x23, 0x09, 0xBE, 0x08, 0x71, 0xE5, 0x88, 0x09, ++ 0xFE, 0x01, 0x02, 0x70, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x00, 0x79, 0xB3, 0x09, 0x90, 0xF8, ++ 0xF0, 0x04, 0x44, 0xE0, 0x07, 0x90, 0x6D, 0x51, 0x20, 0x44, 0xE0, 0xA7, 0xBD, 0x07, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0xAA, 0x07, 0x90, 0x50, 0x44, 0x07, 0x54, 0x04, 0x44, 0xE0, 0xF0, ++ 0x92, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x03, 0x06, 0x90, 0x90, 0xF0, 0x04, 0x44, ++ 0x44, 0xE0, 0x35, 0x06, 0xD0, 0x91, 0xF0, 0x01, 0xE0, 0xA9, 0x07, 0x90, 0x90, 0xF0, 0x20, 0x44, ++ 0x44, 0xE0, 0x14, 0x06, 0x07, 0x90, 0xF0, 0x20, 0x08, 0x54, 0xE0, 0xB6, 0x90, 0xFF, 0xE0, 0x25, ++ 0x54, 0xE0, 0x14, 0x06, 0x90, 0xF0, 0x4F, 0xEF, 0x13, 0x74, 0x4B, 0x07, 0x4C, 0x07, 0x90, 0xF0, ++ 0x90, 0xF0, 0x88, 0x74, 0x54, 0xE0, 0x43, 0x08, 0xF0, 0x50, 0x44, 0x8F, 0xE0, 0xD4, 0x09, 0x90, ++ 0x90, 0xF0, 0x80, 0x44, 0x7F, 0x74, 0xD9, 0x09, 0x6C, 0xF5, 0xE4, 0xF0, 0x75, 0x25, 0x13, 0x75, ++ 0x10, 0x75, 0xC8, 0x14, 0x02, 0x08, 0x90, 0x0B, 0xE4, 0x62, 0xF5, 0xE0, 0x06, 0x90, 0x64, 0xF5, ++ 0x13, 0xFF, 0xE0, 0x31, 0x30, 0x3F, 0x54, 0x13, 0xEC, 0xD2, 0x02, 0xE0, 0x06, 0x90, 0xEE, 0xD2, ++ 0xE0, 0x30, 0xE0, 0x29, 0x60, 0x64, 0xE5, 0x04, 0x29, 0x06, 0x90, 0x0D, 0x41, 0xE0, 0x20, 0xE0, ++ 0x04, 0x64, 0x64, 0xE5, 0x06, 0x90, 0x3B, 0x70, 0xE0, 0x30, 0xE0, 0x29, 0x04, 0x64, 0x75, 0x05, ++ 0xF5, 0xE4, 0x03, 0x80, 0x47, 0x07, 0x90, 0x64, 0xF0, 0xFB, 0x54, 0xE0, 0x74, 0x66, 0x07, 0x90, ++ 0x07, 0x90, 0xF0, 0x01, 0x04, 0x44, 0xE0, 0x48, 0x07, 0x90, 0xE4, 0xF0, 0x07, 0x90, 0xF0, 0x52, ++ 0x07, 0x90, 0xF0, 0x51, 0x07, 0x90, 0xF0, 0x54, 0x07, 0x90, 0xF0, 0x53, 0x04, 0x44, 0xE0, 0x47, ++ 0xB5, 0xC8, 0x74, 0xF0, 0x25, 0x74, 0x07, 0x14, 0x51, 0x02, 0x13, 0xB5, 0xAE, 0x01, 0x90, 0x6D, ++ 0xF0, 0x04, 0x44, 0xE0, 0x07, 0x90, 0xFF, 0xE0, 0x13, 0xC4, 0xE0, 0x8B, 0xFE, 0x01, 0x54, 0x13, ++ 0x54, 0x13, 0xC4, 0xEF, 0x54, 0xEF, 0xFD, 0x01, 0x4E, 0xED, 0xFF, 0xDF, 0x33, 0xC4, 0x01, 0x54, ++ 0x90, 0x4F, 0xE0, 0x54, 0xE0, 0xF0, 0xAE, 0x01, 0x8B, 0x07, 0x90, 0xFF, 0x54, 0x13, 0xC4, 0xE0, ++ 0x13, 0xEF, 0xFE, 0x01, 0x01, 0x54, 0x13, 0x13, 0xF7, 0x54, 0xEF, 0xFD, 0x54, 0x4E, 0xED, 0xFF, ++ 0x33, 0x33, 0x33, 0x01, 0x90, 0x4F, 0xF8, 0x54, 0xE0, 0xF0, 0xAE, 0x01, 0x8B, 0x07, 0x90, 0xFF, ++ 0x54, 0x13, 0xC3, 0xE0, 0xC4, 0xEF, 0xFE, 0x01, 0xEF, 0xFD, 0x01, 0x54, 0xED, 0xFF, 0xEF, 0x54, ++ 0xFE, 0x01, 0x54, 0x4E, 0x4F, 0xF0, 0x54, 0xC4, 0xF0, 0xAE, 0x01, 0x90, 0x74, 0x8B, 0x07, 0x90, ++ 0x06, 0x90, 0xF0, 0x62, 0x13, 0x13, 0xE0, 0x31, 0xE0, 0x20, 0x3F, 0x54, 0x7F, 0xEE, 0xD2, 0x02, ++ 0xB2, 0x0B, 0x12, 0x72, 0xF5, 0xE4, 0x12, 0x50, 0x02, 0x69, 0x75, 0x67, 0x75, 0x08, 0x6A, 0x75, ++ 0x68, 0x75, 0x46, 0x6B, 0x01, 0x6C, 0x75, 0x0E, 0x05, 0x60, 0x6C, 0xE5, 0x51, 0x02, 0x0B, 0x20, ++ 0xEF, 0x20, 0xAF, 0xC3, 0x20, 0x0F, 0x54, 0xC4, 0x20, 0xAF, 0x40, 0xE0, 0x3A, 0xE0, 0x20, 0xEF, ++ 0xC3, 0xEF, 0x20, 0xAF, 0x32, 0xE0, 0x20, 0x13, 0xC4, 0xEF, 0x20, 0xAF, 0x20, 0x07, 0x54, 0x13, ++ 0x20, 0xAF, 0x28, 0xE0, 0x54, 0x13, 0x13, 0xEF, 0x1E, 0xE0, 0x20, 0x3F, 0x14, 0x65, 0x81, 0x74, ++ 0x28, 0x74, 0x04, 0x70, 0x12, 0x60, 0x13, 0x65, 0x14, 0xB5, 0xC8, 0x74, 0xB5, 0x25, 0x74, 0x09, ++ 0x40, 0x91, 0x04, 0x13, 0xCE, 0x91, 0x04, 0x40, 0x06, 0x90, 0x22, 0x50, 0xFB, 0x54, 0xE0, 0x03, ++ 0x35, 0x06, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xED, 0xC2, 0xEC, 0xC2, 0xEF, 0xC2, 0xEE, 0xC2, ++ 0x5B, 0x7F, 0x02, 0x7E, 0x5E, 0x8F, 0x5D, 0x8E, 0x5A, 0x8F, 0x59, 0x8E, 0xC2, 0x09, 0x90, 0x22, ++ 0x90, 0xF0, 0x20, 0x74, 0x54, 0xE0, 0xB4, 0x07, 0x31, 0x08, 0x90, 0x03, 0x90, 0xE0, 0x0F, 0x70, ++ 0x90, 0xF0, 0xB9, 0x07, 0x90, 0xE0, 0x96, 0x08, 0x80, 0xF0, 0xBA, 0x07, 0x07, 0x90, 0xE0, 0x0D, ++ 0x08, 0x90, 0xF0, 0xBA, 0x07, 0x90, 0xE0, 0x96, 0x07, 0x90, 0xF0, 0xB9, 0x54, 0xC4, 0xE0, 0xB4, ++ 0x08, 0x90, 0xFF, 0x03, 0x02, 0xBF, 0xE0, 0xFB, 0xBB, 0x07, 0x90, 0x0D, 0x60, 0x09, 0x90, 0xF0, ++ 0xBC, 0x07, 0x90, 0xE0, 0x07, 0x90, 0x22, 0xF0, 0x09, 0x90, 0xF0, 0xBC, 0x07, 0x90, 0xE0, 0x60, ++ 0x78, 0x22, 0xF0, 0xBB, 0x08, 0xC3, 0x76, 0x72, 0xFF, 0x7B, 0x50, 0x76, 0x13, 0x79, 0x20, 0x7A, ++ 0xFD, 0xEF, 0x67, 0xAF, 0x0C, 0x12, 0x00, 0x7C, 0x09, 0x90, 0xE4, 0xE5, 0x69, 0xAF, 0xF0, 0xC2, ++ 0xC4, 0x03, 0x54, 0xEF, 0xFF, 0xE0, 0x54, 0x33, 0x4F, 0x9F, 0x54, 0xE0, 0xEF, 0x67, 0xAF, 0xF0, ++ 0x3E, 0x24, 0xE0, 0x25, 0x34, 0xE4, 0x82, 0xF5, 0xE4, 0x83, 0xF5, 0x20, 0x01, 0x74, 0xFE, 0x93, ++ 0xF5, 0x22, 0x8E, 0x93, 0x08, 0x25, 0x75, 0x23, 0x02, 0x70, 0x69, 0xE5, 0x70, 0x14, 0xB5, 0x61, ++ 0x24, 0xB8, 0x61, 0x02, 0x14, 0x1F, 0x60, 0xFE, 0x02, 0x24, 0x4F, 0x60, 0xE7, 0x61, 0x02, 0x60, ++ 0x20, 0x7A, 0xFF, 0x7B, 0x23, 0x85, 0x19, 0x79, 0x83, 0x22, 0x85, 0x82, 0xE0, 0xA3, 0xFE, 0xE0, ++ 0x06, 0xAC, 0xFD, 0xFF, 0x6A, 0xAE, 0x7A, 0x80, 0x82, 0x8F, 0x6B, 0xAF, 0xFF, 0xE0, 0x83, 0x8E, ++ 0x1F, 0x7C, 0xB1, 0x7D, 0xEF, 0xEF, 0x0B, 0x12, 0x50, 0x68, 0x95, 0xC3, 0x7B, 0x68, 0x8F, 0x02, ++ 0x79, 0x20, 0x7A, 0xFF, 0x7C, 0xFD, 0xEF, 0x1D, 0xE5, 0x0C, 0x12, 0x00, 0x6B, 0x25, 0x65, 0x74, ++ 0x35, 0xE4, 0x6B, 0xF5, 0x80, 0x6A, 0xF5, 0x6A, 0xEF, 0x67, 0xAF, 0x7E, 0x46, 0x24, 0xE0, 0x25, ++ 0x34, 0xE4, 0x82, 0xF5, 0xE4, 0x83, 0xF5, 0x20, 0x01, 0x74, 0xFE, 0x93, 0xF5, 0x22, 0x8E, 0x93, ++ 0x8E, 0x82, 0xF5, 0x23, 0xFF, 0xE0, 0xA3, 0x83, 0xE7, 0xA2, 0x06, 0x78, 0xFE, 0xFB, 0xD8, 0x13, ++ 0xA2, 0x05, 0x78, 0xEF, 0xFB, 0xD8, 0x13, 0xE7, 0xE5, 0xFF, 0x2F, 0x2E, 0x90, 0x05, 0x70, 0x67, ++ 0xF0, 0xEF, 0x20, 0x06, 0x20, 0x7A, 0xFF, 0x7B, 0xFD, 0xEF, 0x24, 0x79, 0xFC, 0xE0, 0x95, 0x33, ++ 0x80, 0xE5, 0x0C, 0x12, 0x0A, 0x25, 0x75, 0x32, 0xE5, 0x24, 0xF5, 0xE4, 0x25, 0x95, 0xC3, 0x24, ++ 0x24, 0xE5, 0x25, 0x50, 0x90, 0xFF, 0x0F, 0x54, 0x54, 0xE0, 0xC2, 0x09, 0x7B, 0xF0, 0x4F, 0xF0, ++ 0x79, 0x20, 0x7A, 0xFF, 0x82, 0x23, 0x85, 0x2C, 0xE0, 0x83, 0x22, 0x85, 0xFD, 0xE0, 0xA3, 0xFC, ++ 0x05, 0xE5, 0x0C, 0x12, 0x7B, 0xD4, 0x80, 0x24, 0x79, 0x20, 0x7A, 0xFF, 0xF8, 0x03, 0x12, 0x30, ++ 0x24, 0xEF, 0x69, 0xAF, 0x33, 0xE4, 0xFF, 0x01, 0x7D, 0x00, 0x7C, 0xFE, 0xAA, 0x02, 0x12, 0x05, ++ 0x69, 0xE5, 0x69, 0x8D, 0x37, 0x70, 0x02, 0x64, 0x24, 0xEF, 0x67, 0xAF, 0x33, 0xE4, 0xFF, 0x01, ++ 0xF5, 0x03, 0x54, 0xEF, 0x7A, 0xFF, 0x7B, 0x67, 0x12, 0x32, 0x79, 0x20, 0x67, 0xE5, 0xF8, 0x03, ++ 0x68, 0xAF, 0x1D, 0x70, 0xC4, 0x0F, 0x54, 0xEF, 0x90, 0xFF, 0xF0, 0x54, 0x54, 0xE0, 0x21, 0x06, ++ 0xE4, 0xF0, 0x4F, 0x0F, 0xFF, 0x7B, 0x6C, 0xF5, 0x3B, 0x79, 0x20, 0x7A, 0x22, 0xF8, 0x03, 0x12, ++ 0x74, 0xC2, 0x09, 0x90, 0x08, 0x90, 0xF0, 0x40, 0x94, 0xD3, 0xE0, 0x47, 0x90, 0x67, 0x40, 0x0A, ++ 0xD3, 0xE0, 0xAC, 0x08, 0x5E, 0x40, 0x0A, 0x94, 0xE0, 0x11, 0x09, 0x90, 0x40, 0x0A, 0x94, 0xD3, ++ 0x76, 0x09, 0x90, 0x55, 0x0A, 0x94, 0xD3, 0xE0, 0x08, 0x90, 0x4C, 0x40, 0x28, 0x94, 0xE0, 0x46, ++ 0x08, 0x90, 0x44, 0x50, 0x94, 0xC3, 0xE0, 0xAB, 0x90, 0x3B, 0x50, 0x28, 0xC3, 0xE0, 0x10, 0x09, ++ 0x32, 0x50, 0x28, 0x94, 0xE0, 0x75, 0x09, 0x90, 0x50, 0x28, 0x94, 0xC3, 0x31, 0x08, 0x90, 0x29, ++ 0x40, 0x01, 0x94, 0xE0, 0x96, 0x08, 0x90, 0x21, 0x01, 0x94, 0xD3, 0xE0, 0x08, 0x90, 0x18, 0x40, ++ 0x94, 0xD3, 0xE0, 0xFB, 0x90, 0x0F, 0x40, 0x01, 0xD3, 0xE0, 0x60, 0x09, 0x06, 0x40, 0x01, 0x94, ++ 0xF6, 0x7E, 0x78, 0xE4, 0x7E, 0x78, 0x03, 0x80, 0xE6, 0x7E, 0x78, 0x06, 0x40, 0x64, 0x94, 0xD3, ++ 0x7A, 0xFF, 0x7B, 0x0B, 0x12, 0x08, 0x79, 0x20, 0x22, 0xD3, 0xF8, 0x03, 0x22, 0xC3, 0x22, 0xC3, ++ 0xE0, 0xF2, 0x07, 0x90, 0xBF, 0xFF, 0x03, 0x54, 0x01, 0x7F, 0x04, 0x01, 0x00, 0x7F, 0x02, 0x80, ++ 0x07, 0x90, 0x24, 0x8F, 0x54, 0xC4, 0xE0, 0xF2, 0x03, 0xBF, 0xFF, 0x03, 0x80, 0x01, 0x7F, 0x04, ++ 0x90, 0x00, 0x7F, 0x02, 0x54, 0xE0, 0xB4, 0x07, 0x01, 0xBE, 0xFE, 0x03, 0x80, 0x01, 0x7E, 0x04, ++ 0x90, 0x00, 0x7E, 0x02, 0xC4, 0xE0, 0xB4, 0x07, 0xBB, 0xFB, 0x03, 0x54, 0x01, 0x7B, 0x04, 0x03, ++ 0x00, 0x7B, 0x02, 0x80, 0xB1, 0x07, 0x90, 0xEE, 0x54, 0xE0, 0x0B, 0x70, 0xE0, 0x22, 0xF5, 0x07, ++ 0x80, 0x13, 0x13, 0x13, 0x13, 0x13, 0xE0, 0x09, 0xF5, 0x07, 0x54, 0x13, 0x07, 0x54, 0xE0, 0x22, ++ 0x90, 0xEB, 0x23, 0xF5, 0x0A, 0x70, 0xB2, 0x07, 0xF9, 0x07, 0x54, 0xE0, 0x13, 0x13, 0x13, 0xE0, ++ 0x13, 0xE0, 0x08, 0x80, 0x07, 0x54, 0x13, 0x13, 0x07, 0x54, 0xE0, 0xF9, 0x02, 0x7D, 0xEE, 0xFC, ++ 0x7D, 0x02, 0x24, 0xB5, 0x07, 0xB5, 0xEB, 0x01, 0x04, 0x05, 0x43, 0x05, 0x05, 0x43, 0x03, 0x80, ++ 0x64, 0x6F, 0xEB, 0x08, 0x33, 0x33, 0x33, 0x01, 0xE5, 0xFF, 0x08, 0x54, 0x01, 0x64, 0x6E, 0x24, ++ 0xE0, 0x25, 0xE0, 0x25, 0xFF, 0x4F, 0x04, 0x54, 0xE0, 0xAB, 0x07, 0x90, 0xC4, 0x6D, 0x0F, 0x54, ++ 0x90, 0x4F, 0xF0, 0x54, 0xE5, 0xF0, 0x23, 0x06, 0xFF, 0xFE, 0x24, 0x23, 0x54, 0xF8, 0xC4, 0xEF, ++ 0xFF, 0x68, 0xC8, 0x0F, 0xFF, 0x70, 0x54, 0xEF, 0xFE, 0x24, 0x22, 0xE5, 0x07, 0x54, 0xEB, 0xFB, ++ 0xFB, 0x4F, 0xEB, 0xFB, 0xFF, 0xFE, 0x24, 0xE9, 0xFA, 0x07, 0x54, 0xEF, 0xFF, 0xFE, 0x24, 0xEC, ++ 0x70, 0x54, 0xC4, 0xEF, 0x90, 0xEB, 0xFF, 0x4A, 0xF0, 0xCF, 0x24, 0x06, 0x22, 0xF0, 0xEF, 0xA3, ++ 0x0F, 0x00, 0xFF, 0xE4, 0x22, 0xFB, 0x0F, 0xBF, 0x74, 0x66, 0x07, 0x90, 0x07, 0x90, 0xF0, 0xFF, ++ 0x90, 0xF0, 0x14, 0x68, 0xFF, 0xE0, 0x31, 0x06, 0x3F, 0x54, 0x13, 0x13, 0xC1, 0x02, 0xE0, 0x20, ++ 0x66, 0x07, 0x90, 0x65, 0x20, 0x64, 0x45, 0xE0, 0x07, 0x90, 0x09, 0xE2, 0xBF, 0x54, 0xE0, 0xA9, ++ 0x90, 0x4E, 0x80, 0xF0, 0x44, 0xE0, 0xA9, 0x07, 0x07, 0x90, 0xF0, 0x40, 0x84, 0x54, 0xE0, 0x68, ++ 0x3D, 0x70, 0x84, 0x64, 0xE0, 0xA9, 0x07, 0x90, 0x01, 0x44, 0xFC, 0x54, 0x8A, 0x07, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0xD4, 0x09, 0x90, 0x90, 0xF0, 0xFE, 0x54, 0x54, 0xE0, 0xD7, 0x09, ++ 0xF0, 0x40, 0x44, 0x8F, 0xE0, 0xD6, 0x09, 0x90, 0x08, 0x44, 0xF3, 0x54, 0xD8, 0x09, 0x90, 0xF0, ++ 0x44, 0x0F, 0x54, 0xE0, 0x09, 0x90, 0xF0, 0x20, 0xF0, 0x60, 0x74, 0xF5, 0x80, 0x1C, 0x2E, 0x12, ++ 0xD1, 0xD7, 0xD1, 0x04, 0x68, 0x07, 0x90, 0xA3, 0x1D, 0xE0, 0x30, 0xE0, 0x12, 0xF0, 0x01, 0x74, ++ 0x09, 0x90, 0x3A, 0x2F, 0x0F, 0x54, 0xE0, 0xEA, 0x0D, 0x06, 0xBF, 0xFF, 0xE0, 0x47, 0x07, 0x90, ++ 0x80, 0xF0, 0xEF, 0x54, 0xC2, 0xA3, 0xD1, 0x04, 0x2E, 0x08, 0x90, 0xEE, 0x90, 0x65, 0xF5, 0xE0, ++ 0x40, 0x74, 0xC2, 0x09, 0x31, 0x08, 0x90, 0xF0, 0x01, 0x94, 0xD3, 0xE0, 0x08, 0x90, 0x1B, 0x40, ++ 0x94, 0xD3, 0xE0, 0x96, 0x90, 0x12, 0x40, 0x01, 0xD3, 0xE0, 0xFB, 0x08, 0x09, 0x40, 0x01, 0x94, ++ 0xE0, 0x60, 0x09, 0x90, 0x50, 0x01, 0x94, 0xD3, 0x81, 0x28, 0x12, 0x03, 0xE5, 0xC2, 0x09, 0x90, ++ 0x90, 0x22, 0xF0, 0x65, 0x90, 0xE0, 0x68, 0x07, 0xE7, 0x30, 0xA9, 0x07, 0xFC, 0x54, 0xE0, 0x13, ++ 0x8E, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x14, 0x06, 0x90, 0x22, 0xF0, 0x10, 0x44, ++ 0x44, 0xFC, 0x54, 0xE0, 0x06, 0x90, 0xF0, 0x01, 0xEF, 0x54, 0xE0, 0x14, 0x07, 0x90, 0x22, 0xF0, ++ 0x20, 0x44, 0xE0, 0xA9, 0x90, 0xA0, 0xF1, 0xF0, 0x90, 0xE0, 0x68, 0x07, 0xE2, 0x30, 0x8A, 0x07, ++ 0x01, 0x44, 0xE0, 0x05, 0x54, 0xE0, 0x22, 0xF0, 0x78, 0x22, 0xF0, 0xFE, 0x4D, 0x60, 0xE6, 0x79, ++ 0xE0, 0xAB, 0x07, 0x90, 0x13, 0x13, 0xC4, 0xFF, 0x30, 0x01, 0x54, 0x13, 0x07, 0x90, 0x3F, 0xE0, ++ 0xE1, 0x20, 0xE0, 0xAA, 0x67, 0x07, 0x90, 0x0A, 0x03, 0xE0, 0x20, 0xE0, 0x12, 0xEF, 0x80, 0x00, ++ 0x07, 0x90, 0xA4, 0x2F, 0xE0, 0x30, 0xE0, 0x67, 0x12, 0x29, 0x80, 0x02, 0xCE, 0xD1, 0x32, 0x2D, ++ 0xE0, 0xAB, 0x07, 0x90, 0x90, 0xF0, 0x7F, 0x54, 0x08, 0x74, 0x68, 0x07, 0xE9, 0x09, 0x90, 0xF0, ++ 0xF0, 0xEF, 0x54, 0xE0, 0xE0, 0x67, 0x07, 0x90, 0x80, 0x0C, 0xE0, 0x30, 0x67, 0x07, 0x90, 0x07, ++ 0x03, 0xE0, 0x30, 0xE0, 0x90, 0x81, 0x28, 0x02, 0x42, 0x74, 0x68, 0x07, 0x66, 0x07, 0x90, 0xF0, ++ 0xE0, 0xF0, 0xFF, 0x74, 0x07, 0x90, 0x64, 0x45, 0x06, 0xE2, 0x30, 0xA9, 0xF0, 0x40, 0x44, 0xE0, ++ 0x54, 0xE0, 0x04, 0x80, 0xD7, 0xD1, 0xF0, 0xBF, 0xE0, 0x68, 0x07, 0x90, 0x90, 0x30, 0xE7, 0x30, ++ 0x30, 0xE0, 0xAA, 0x07, 0xA0, 0xF1, 0x29, 0xE1, 0x74, 0x68, 0x07, 0x90, 0xEC, 0xD2, 0xF0, 0x40, ++ 0x07, 0x90, 0xED, 0xC2, 0xF7, 0x54, 0xE0, 0x47, 0x1C, 0x2E, 0x12, 0xF0, 0xE0, 0x66, 0x07, 0x90, ++ 0xE2, 0x30, 0x64, 0x45, 0x68, 0x07, 0x90, 0x07, 0x03, 0xE2, 0x20, 0xE0, 0x22, 0xF1, 0x2C, 0x12, ++ 0xE0, 0x68, 0x07, 0x90, 0x90, 0x0D, 0xE7, 0x30, 0x54, 0xE0, 0xA9, 0x07, 0x07, 0x90, 0xF0, 0xFC, ++ 0xF0, 0x01, 0x74, 0x8E, 0xE6, 0x79, 0x78, 0x22, 0x07, 0x90, 0x31, 0x60, 0xFC, 0x54, 0xE0, 0xA9, ++ 0x90, 0xF0, 0x01, 0x44, 0x01, 0x74, 0xBD, 0x09, 0xB5, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x0D, 0x74, ++ 0x80, 0x74, 0xAD, 0x07, 0xAA, 0x07, 0x90, 0xF0, 0xF0, 0xFD, 0x54, 0xE0, 0x74, 0xA8, 0x07, 0x90, ++ 0x13, 0x75, 0xF0, 0x02, 0xEB, 0x14, 0x75, 0x26, 0x90, 0x7D, 0x28, 0x02, 0x0D, 0x74, 0xB5, 0x09, ++ 0xA8, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x02, 0x74, 0x63, 0xE5, 0xF2, 0x09, 0xAA, 0x07, 0x90, 0xF0, ++ 0xF0, 0xFD, 0x54, 0xE0, 0x3D, 0x60, 0x63, 0xE5, 0xE0, 0xAA, 0x07, 0x90, 0x90, 0x0A, 0xE1, 0x20, ++ 0x20, 0xE0, 0x67, 0x07, 0x80, 0x00, 0x03, 0xE0, 0xF0, 0x09, 0x90, 0xEF, 0x90, 0xF0, 0x05, 0x74, ++ 0x0A, 0x74, 0xA8, 0x07, 0xF0, 0x02, 0x74, 0xF0, 0xE0, 0xAA, 0x07, 0x90, 0x90, 0xF0, 0xFD, 0x54, ++ 0x20, 0xE0, 0xAA, 0x07, 0x07, 0x90, 0x0A, 0xE1, 0xE0, 0x20, 0xE0, 0x67, 0xEF, 0x80, 0x00, 0x03, ++ 0xF2, 0x09, 0x90, 0xE4, 0xBD, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x05, 0x74, 0xE9, 0x09, ++ 0x90, 0xA4, 0xF1, 0xF0, 0x54, 0xE0, 0xA9, 0x07, 0xF0, 0x01, 0x44, 0xFC, 0x09, 0x90, 0x32, 0xB1, ++ 0xF0, 0x01, 0x74, 0xE9, 0x90, 0xCE, 0x26, 0x12, 0x30, 0xE0, 0x67, 0x07, 0x11, 0x80, 0x02, 0xE0, ++ 0x75, 0x26, 0x13, 0x75, 0x07, 0x90, 0xEB, 0x14, 0xE7, 0x30, 0xE0, 0x68, 0xEB, 0x26, 0x12, 0x03, ++ 0xC2, 0xEC, 0xC2, 0x22, 0xC2, 0xEE, 0xC2, 0xED, 0x66, 0x07, 0x90, 0xEF, 0x90, 0xF0, 0xFF, 0x74, ++ 0x90, 0xF0, 0x67, 0x07, 0x90, 0xF0, 0x68, 0x07, 0x90, 0xF0, 0x69, 0x07, 0xF4, 0xE0, 0xEA, 0x01, ++ 0xE0, 0xA3, 0x03, 0x70, 0x90, 0x0E, 0x60, 0xF4, 0x04, 0xE0, 0xEB, 0x01, 0x90, 0x06, 0x70, 0xF0, ++ 0x04, 0xE0, 0xEA, 0x01, 0x28, 0x13, 0x75, 0xF0, 0x22, 0x81, 0x14, 0x75, 0x90, 0x66, 0xF5, 0xE4, ++ 0x54, 0xE0, 0x68, 0x07, 0x90, 0x17, 0x70, 0x2C, 0x70, 0xE0, 0xAC, 0x07, 0xA9, 0x07, 0x90, 0x11, ++ 0xF0, 0x7F, 0x54, 0xE0, 0xC4, 0x7D, 0xF1, 0x91, 0xFF, 0xE4, 0x09, 0x7C, 0x07, 0x90, 0xBA, 0x81, ++ 0x24, 0x54, 0xE0, 0x68, 0x06, 0x20, 0xBF, 0xFF, 0xE0, 0xAC, 0x07, 0x90, 0x07, 0x90, 0x69, 0x60, ++ 0xE3, 0x20, 0xE0, 0x68, 0x66, 0x07, 0x90, 0x22, 0x30, 0x64, 0x45, 0xE0, 0x66, 0x05, 0x59, 0xE2, ++ 0x94, 0xC3, 0x66, 0xE5, 0x90, 0xB8, 0x40, 0x05, 0x54, 0xE0, 0xA9, 0x07, 0xF0, 0x02, 0x44, 0xFC, ++ 0xE0, 0x68, 0x07, 0x90, 0x90, 0x15, 0xE3, 0x30, 0x44, 0xE0, 0xD4, 0x09, 0x07, 0x90, 0xF0, 0x80, ++ 0xF0, 0x08, 0x74, 0x68, 0x2F, 0xE3, 0x20, 0xE0, 0x65, 0x80, 0xE1, 0x51, 0x74, 0x68, 0x07, 0x90, ++ 0x07, 0x90, 0xF0, 0xF7, 0xF0, 0xFF, 0x74, 0x67, 0xE0, 0xAC, 0x07, 0x90, 0x07, 0x90, 0x10, 0x70, ++ 0x24, 0x54, 0xE0, 0x68, 0x06, 0x20, 0xBF, 0xFF, 0xE0, 0xAC, 0x07, 0x90, 0x07, 0x90, 0x09, 0x60, ++ 0x64, 0x45, 0xE0, 0x66, 0x71, 0x08, 0xE2, 0x20, 0x51, 0xF6, 0x51, 0x32, 0x51, 0xC4, 0x41, 0xE1, ++ 0xAC, 0x07, 0x90, 0xE1, 0x07, 0x90, 0xFF, 0xE0, 0x64, 0x45, 0xE0, 0x66, 0x71, 0x06, 0xE2, 0x20, ++ 0x41, 0xF6, 0x51, 0x32, 0x68, 0x07, 0x90, 0xC4, 0x02, 0xE3, 0x20, 0xE0, 0x09, 0x90, 0xD6, 0x41, ++ 0x80, 0x44, 0xE0, 0xD4, 0xD9, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x11, 0x74, 0x08, 0x74, 0x68, 0x07, ++ 0xA9, 0x07, 0x90, 0xF0, 0x44, 0xFC, 0x54, 0xE0, 0x7F, 0x78, 0xF0, 0x02, 0xF6, 0x51, 0x58, 0x76, ++ 0xE0, 0x68, 0x07, 0x90, 0x90, 0x09, 0xE3, 0x20, 0x45, 0xE0, 0x66, 0x07, 0x02, 0xE2, 0x20, 0x64, ++ 0x08, 0x90, 0xC4, 0x41, 0xF0, 0x03, 0x74, 0x9B, 0xF0, 0x00, 0x09, 0x90, 0xF0, 0x65, 0x09, 0x90, ++ 0x9B, 0x08, 0x90, 0xE4, 0x00, 0x09, 0x90, 0xF0, 0x65, 0x09, 0x90, 0xF0, 0x68, 0x07, 0x90, 0xF0, ++ 0x09, 0xE3, 0x20, 0xE0, 0xE0, 0x66, 0x07, 0x90, 0xE2, 0x20, 0x64, 0x45, 0x90, 0xC4, 0x41, 0x02, ++ 0x03, 0x74, 0x9D, 0x08, 0x02, 0x09, 0x90, 0xF0, 0x67, 0x09, 0x90, 0xF0, 0x08, 0x90, 0xE4, 0xF0, ++ 0x09, 0x90, 0xF0, 0x9D, 0x09, 0x90, 0xF0, 0x02, 0x07, 0x90, 0xF0, 0x67, 0xE3, 0x20, 0xE0, 0x68, ++ 0x66, 0x07, 0x90, 0x09, 0x20, 0x64, 0x45, 0xE0, 0xC4, 0x41, 0x02, 0xE2, 0x74, 0x62, 0x08, 0x90, ++ 0x08, 0x90, 0xF0, 0x08, 0x09, 0x90, 0xF0, 0xC7, 0x09, 0x90, 0xF0, 0x2C, 0xF0, 0x1C, 0x74, 0x95, ++ 0x74, 0x96, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x08, 0xF0, 0x0E, 0x74, 0x97, 0x74, 0x98, 0x09, 0x90, ++ 0x07, 0x90, 0xF0, 0x0C, 0xE3, 0x20, 0xE0, 0x68, 0x66, 0x07, 0x90, 0x09, 0x20, 0x64, 0x45, 0xE0, ++ 0xC4, 0x41, 0x02, 0xE2, 0xE0, 0x23, 0x06, 0x90, 0x54, 0x13, 0x13, 0xFF, 0x0D, 0xE0, 0x30, 0x3F, ++ 0x74, 0x01, 0x0D, 0x90, 0x90, 0xE4, 0xF0, 0x1B, 0x80, 0xF0, 0x21, 0x0D, 0x0D, 0x90, 0xE4, 0x0B, ++ 0x0D, 0x90, 0xF0, 0x01, 0xF0, 0x1B, 0x74, 0x21, 0x74, 0x41, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x1B, ++ 0x07, 0x90, 0xF0, 0x61, 0xE3, 0x20, 0xE0, 0x68, 0x66, 0x07, 0x90, 0x09, 0x20, 0x64, 0x45, 0xE0, ++ 0x40, 0x80, 0x02, 0xE2, 0x74, 0xB5, 0x09, 0x90, 0x90, 0xE4, 0xF0, 0x0C, 0x90, 0xF0, 0xBD, 0x09, ++ 0x04, 0x74, 0xBB, 0x09, 0x09, 0x90, 0xE4, 0xF0, 0x07, 0x90, 0xF0, 0xB3, 0xE3, 0x20, 0xE0, 0x68, ++ 0x66, 0x07, 0x90, 0x09, 0x20, 0x64, 0x45, 0xE0, 0x18, 0x80, 0x02, 0xE2, 0xF4, 0x7C, 0x24, 0x7D, ++ 0xBA, 0x91, 0xFF, 0xE4, 0xE0, 0x68, 0x07, 0x90, 0x90, 0x09, 0xE3, 0x20, 0x45, 0xE0, 0x66, 0x07, ++ 0x02, 0xE2, 0x20, 0x64, 0x07, 0x90, 0x71, 0xA1, 0xF0, 0x52, 0x74, 0x68, 0x75, 0x2E, 0x13, 0x75, ++ 0x63, 0x75, 0xCC, 0x14, 0x07, 0x90, 0x22, 0xB0, 0xE0, 0x20, 0xE0, 0x67, 0x01, 0x61, 0x21, 0x02, ++ 0x95, 0x09, 0x90, 0x81, 0x90, 0xF0, 0x1B, 0x74, 0x0B, 0x74, 0x96, 0x09, 0x97, 0x09, 0x90, 0xF0, ++ 0x98, 0x09, 0x90, 0xF0, 0x07, 0x90, 0x22, 0xF0, 0x02, 0x44, 0xE0, 0xA8, 0xA9, 0x07, 0x90, 0xF0, ++ 0xF0, 0xDF, 0x54, 0xE0, 0x8E, 0x07, 0x90, 0xE4, 0xEA, 0x09, 0x90, 0xF0, 0x44, 0xF0, 0x54, 0xE0, ++ 0x09, 0x90, 0xF0, 0x02, 0xFD, 0x54, 0xE0, 0xBF, 0xB5, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x0F, 0x74, ++ 0x03, 0x74, 0xBD, 0x09, 0xBB, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x07, 0x74, 0x03, 0x74, 0xB3, 0x09, ++ 0x07, 0x90, 0x22, 0xF0, 0x64, 0x45, 0xE0, 0x66, 0x30, 0xA9, 0x07, 0x90, 0x44, 0xE0, 0x05, 0xE2, ++ 0xE0, 0x22, 0xF0, 0x40, 0x22, 0xF0, 0xBF, 0x54, 0x74, 0x66, 0x07, 0x90, 0x07, 0x90, 0xF0, 0xFF, ++ 0x90, 0xF0, 0x14, 0x68, 0x45, 0xE0, 0x66, 0x07, 0x09, 0xE2, 0x20, 0x64, 0xE0, 0xA9, 0x07, 0x90, ++ 0x81, 0xF0, 0xBF, 0x54, 0xA9, 0x07, 0x90, 0x20, 0xF0, 0x40, 0x44, 0xE0, 0xE0, 0x68, 0x07, 0x90, ++ 0x02, 0x60, 0x28, 0x54, 0x07, 0x90, 0x99, 0x81, 0x24, 0x54, 0xE0, 0x68, 0x20, 0x81, 0x02, 0x70, ++ 0xE0, 0x68, 0x07, 0x90, 0x81, 0x02, 0xE0, 0x20, 0xF0, 0x01, 0x74, 0x86, 0xE6, 0x16, 0x7F, 0x78, ++ 0x40, 0x0A, 0x94, 0xD3, 0x78, 0x3A, 0xF1, 0x02, 0x0A, 0x64, 0xE6, 0x7F, 0x22, 0x81, 0x02, 0x60, ++ 0xE0, 0xA7, 0x07, 0x90, 0x90, 0x7B, 0xE5, 0x30, 0x44, 0xE0, 0xA8, 0x07, 0x07, 0x90, 0xF0, 0x02, ++ 0xDF, 0x54, 0xE0, 0xA7, 0xA9, 0x07, 0x90, 0xF0, 0xF0, 0xEF, 0x54, 0xE0, 0xE0, 0xBA, 0x09, 0x90, ++ 0x02, 0x44, 0xF9, 0x54, 0xB3, 0x09, 0x90, 0xF0, 0xF0, 0xFB, 0x54, 0xE0, 0xE0, 0xAA, 0x07, 0x90, ++ 0x90, 0xF0, 0xFD, 0x54, 0x44, 0xE0, 0xAB, 0x07, 0x44, 0xE0, 0xF0, 0x30, 0x44, 0xE0, 0xF0, 0x40, ++ 0x07, 0x90, 0xF0, 0x80, 0xF0, 0x1A, 0x74, 0xAD, 0x07, 0x90, 0xFE, 0xE4, 0xFD, 0x54, 0xE0, 0xAA, ++ 0xC0, 0x25, 0x12, 0xF0, 0x13, 0xC3, 0xFF, 0xE0, 0x90, 0x06, 0xE0, 0x30, 0x60, 0xE0, 0xAC, 0x07, ++ 0x0A, 0xBE, 0x0E, 0x04, 0xA8, 0x07, 0x90, 0xE5, 0xF0, 0xFD, 0x54, 0xE0, 0x74, 0x68, 0x07, 0x90, ++ 0x07, 0x90, 0xF0, 0xFF, 0xF0, 0x2A, 0x74, 0xAD, 0xE0, 0x68, 0x07, 0x90, 0x02, 0x70, 0x24, 0x54, ++ 0x7F, 0x78, 0xF1, 0x81, 0x60, 0x02, 0x64, 0xE6, 0x07, 0x64, 0xE6, 0x0A, 0x79, 0x78, 0x58, 0x70, ++ 0x90, 0x53, 0x60, 0xE6, 0x44, 0xE0, 0xB8, 0x09, 0x09, 0x90, 0xF0, 0x01, 0x08, 0x44, 0xE0, 0xB5, ++ 0x04, 0x44, 0xE0, 0xF0, 0xBB, 0x09, 0x90, 0xF0, 0xF0, 0x04, 0x44, 0xE0, 0xE0, 0x95, 0x09, 0x90, ++ 0xE0, 0xF0, 0x08, 0x44, 0x90, 0xF0, 0x10, 0x44, 0x44, 0xE0, 0x96, 0x09, 0x09, 0x90, 0xF0, 0x08, ++ 0x08, 0x44, 0xE0, 0x97, 0x98, 0x09, 0x90, 0xF0, 0xF0, 0x08, 0x44, 0xE0, 0xE0, 0xD4, 0x09, 0x90, ++ 0x90, 0xF0, 0x40, 0x44, 0x11, 0x74, 0xD9, 0x09, 0xD4, 0x09, 0x90, 0xF0, 0xF0, 0x7F, 0x54, 0xE0, ++ 0x74, 0x68, 0x07, 0x90, 0x7F, 0x78, 0xF0, 0x08, 0x90, 0x07, 0x70, 0xE6, 0x20, 0xE0, 0x68, 0x07, ++ 0x07, 0x90, 0x07, 0xE2, 0xE5, 0x30, 0xE0, 0x68, 0xE9, 0x09, 0x90, 0x20, 0x90, 0xF0, 0x1D, 0x74, ++ 0x44, 0xE0, 0x47, 0x07, 0x54, 0xE0, 0xF0, 0x08, 0x07, 0x90, 0xF0, 0xEF, 0x80, 0x44, 0xE0, 0xA9, ++ 0x28, 0x13, 0x75, 0xF0, 0x11, 0xBC, 0x14, 0x75, 0x07, 0x90, 0x22, 0xBC, 0xEF, 0x54, 0xE0, 0x47, ++ 0x01, 0x54, 0xEF, 0xF0, 0xFF, 0xF0, 0x54, 0xC4, 0xE0, 0x48, 0x07, 0x90, 0xF0, 0x4F, 0xEF, 0x54, ++ 0x5A, 0x07, 0x90, 0xE4, 0x59, 0x07, 0x90, 0xF0, 0x07, 0x90, 0xED, 0xF0, 0x90, 0xEC, 0xF0, 0x5C, ++ 0x90, 0xF0, 0x5B, 0x07, 0x01, 0x74, 0x68, 0x07, 0x47, 0x07, 0x90, 0xF0, 0xF0, 0x10, 0x44, 0xE0, ++ 0x12, 0x32, 0xB1, 0x22, 0x09, 0x90, 0xA0, 0x27, 0x01, 0x44, 0xE0, 0xD4, 0xD7, 0x09, 0x90, 0xF0, ++ 0x44, 0x8F, 0x54, 0xE0, 0x09, 0x90, 0xF0, 0x60, 0xF3, 0x54, 0xE0, 0xD6, 0x90, 0xF0, 0x04, 0x44, ++ 0x54, 0xE0, 0xD8, 0x09, 0xF0, 0x10, 0x44, 0x0F, 0xE0, 0xD4, 0x09, 0x90, 0x90, 0xF0, 0x80, 0x44, ++ 0x7F, 0x74, 0xD9, 0x09, 0x68, 0x07, 0x90, 0xF0, 0x75, 0xF0, 0x08, 0x74, 0x14, 0x75, 0x25, 0x13, ++ 0x07, 0x90, 0x22, 0xC8, 0x13, 0xC4, 0xE0, 0xA7, 0xE0, 0x20, 0x07, 0x54, 0xA8, 0x07, 0x90, 0x1C, ++ 0xF0, 0x02, 0x44, 0xE0, 0xE0, 0xAA, 0x07, 0x90, 0x90, 0xF0, 0x04, 0x44, 0x44, 0xE0, 0xB3, 0x09, ++ 0x07, 0x90, 0xF0, 0x04, 0x20, 0x44, 0xE0, 0xA7, 0xA9, 0x07, 0x90, 0xF0, 0xF0, 0x10, 0x44, 0xE0, ++ 0xE0, 0xBA, 0x09, 0x90, 0x04, 0x44, 0xF9, 0x54, 0xA8, 0x07, 0x90, 0xF0, 0xF0, 0xFD, 0x54, 0xE0, ++ 0x0D, 0x90, 0xE4, 0x22, 0x0D, 0x90, 0xF0, 0x01, 0x0D, 0x90, 0xF0, 0x21, 0x0D, 0x90, 0xF0, 0x41, ++ 0x0D, 0x90, 0xF0, 0x61, 0xF0, 0x35, 0x74, 0x0C, 0xF0, 0x2C, 0x0D, 0x90, 0xF0, 0x4C, 0x0D, 0x90, ++ 0xF0, 0x6C, 0x0D, 0x90, 0xE0, 0xA9, 0x07, 0x90, 0x01, 0x44, 0xFC, 0x54, 0x95, 0x09, 0x90, 0xF0, ++ 0x90, 0xF0, 0x1A, 0x74, 0x62, 0xE5, 0x96, 0x09, 0x97, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x62, 0xE5, ++ 0x62, 0xE5, 0x98, 0x09, 0x66, 0xF5, 0xE4, 0xF0, 0xE5, 0x66, 0x05, 0x00, 0xF8, 0x0A, 0xB4, 0x66, ++ 0xE0, 0xA9, 0x07, 0x90, 0x02, 0x44, 0xFC, 0x54, 0x47, 0x07, 0x90, 0xF0, 0xF0, 0x20, 0x44, 0xE0, ++ 0xF0, 0xEF, 0x54, 0xE0, 0x61, 0x7E, 0xA8, 0x7F, 0x07, 0x90, 0x59, 0xD1, 0x08, 0x44, 0xE0, 0x47, ++ 0xD4, 0x09, 0x90, 0xF0, 0xF0, 0x80, 0x44, 0xE0, 0x74, 0xD9, 0x09, 0x90, 0x07, 0x90, 0xF0, 0x7F, ++ 0xF0, 0x08, 0x74, 0x68, 0xED, 0xD2, 0xEC, 0xC2, 0xE0, 0xA9, 0x07, 0x90, 0x75, 0xF0, 0x7F, 0x54, ++ 0x14, 0x75, 0x27, 0x13, 0x71, 0x84, 0xD1, 0xB5, 0xAD, 0x07, 0x90, 0x32, 0x90, 0xF0, 0x1A, 0x74, ++ 0x20, 0xE0, 0x69, 0x07, 0x80, 0x00, 0x03, 0xE0, 0xB5, 0x27, 0x02, 0xF6, 0xED, 0xC2, 0xEC, 0xD2, ++ 0xE0, 0x47, 0x07, 0x90, 0x7D, 0xF0, 0xF7, 0x54, 0xE4, 0x09, 0x7C, 0xC4, 0x78, 0xBA, 0x91, 0xFF, ++ 0x7F, 0x78, 0xE6, 0x79, 0x18, 0x76, 0x04, 0x60, 0x13, 0x76, 0x02, 0x80, 0x02, 0x7E, 0xA3, 0x7F, ++ 0xAC, 0x7F, 0xA1, 0xD1, 0x59, 0xD1, 0x0D, 0x7E, 0xE0, 0xAB, 0x07, 0x90, 0x75, 0xF0, 0x7F, 0x54, ++ 0x14, 0x75, 0x2B, 0x13, 0x63, 0xF5, 0xE4, 0x48, 0xCD, 0xEF, 0xCD, 0x22, 0xE0, 0x47, 0x07, 0x90, ++ 0x90, 0xF0, 0xF7, 0x54, 0x44, 0xE0, 0x48, 0x07, 0x90, 0xE4, 0xF0, 0x08, 0x90, 0xF0, 0x56, 0x07, ++ 0xED, 0xF0, 0x55, 0x07, 0xF0, 0x58, 0x07, 0x90, 0x57, 0x07, 0x90, 0xEE, 0x67, 0x07, 0x90, 0xF0, ++ 0x22, 0xF0, 0x01, 0x74, 0x74, 0xCC, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x01, 0x90, 0xF0, 0x04, 0x91, ++ 0xF0, 0x14, 0xCA, 0x09, 0x74, 0xBB, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x05, 0xF0, 0x01, 0x74, 0xB3, ++ 0xCD, 0xEF, 0xCD, 0x22, 0xE0, 0x47, 0x07, 0x90, 0x90, 0xF0, 0xDF, 0x54, 0x44, 0xE0, 0x48, 0x07, ++ 0x90, 0xE4, 0xF0, 0x20, 0x90, 0xF0, 0x5E, 0x07, 0xED, 0xF0, 0x5D, 0x07, 0xF0, 0x60, 0x07, 0x90, ++ 0x5F, 0x07, 0x90, 0xEE, 0x69, 0x07, 0x90, 0xF0, 0x22, 0xF0, 0x01, 0x74, 0x74, 0x66, 0x07, 0x90, ++ 0x07, 0x90, 0xF0, 0xFF, 0xE3, 0x20, 0xE0, 0x68, 0x66, 0x07, 0x90, 0x0E, 0x30, 0x64, 0x45, 0xE0, ++ 0x7F, 0x78, 0x05, 0xE2, 0xA1, 0x02, 0x70, 0xE6, 0x68, 0x07, 0x90, 0x71, 0x49, 0xE0, 0x30, 0xE0, ++ 0x78, 0xF0, 0x01, 0x74, 0x0D, 0x90, 0x16, 0x7F, 0x54, 0xC4, 0xE0, 0x0C, 0xE0, 0x66, 0xF5, 0x0F, ++ 0x85, 0x78, 0x0F, 0x54, 0xD3, 0x66, 0xE5, 0xF6, 0x02, 0x40, 0x01, 0x94, 0x85, 0x78, 0x66, 0x15, ++ 0x01, 0x94, 0xD3, 0xE6, 0xE5, 0x16, 0x01, 0x40, 0xF0, 0x54, 0xC4, 0x66, 0xF5, 0x46, 0x85, 0x78, ++ 0x0C, 0x0D, 0x90, 0x66, 0x90, 0xF0, 0x66, 0xE5, 0x66, 0xE5, 0x2C, 0x0D, 0x4C, 0x0D, 0x90, 0xF0, ++ 0x90, 0xF0, 0x66, 0xE5, 0x66, 0xE5, 0x6C, 0x0D, 0x09, 0x90, 0x22, 0xF0, 0x0F, 0x54, 0xE0, 0xEA, ++ 0x50, 0x06, 0x94, 0xC3, 0x54, 0xFF, 0xE0, 0x0B, 0x04, 0xEF, 0xFE, 0xF0, 0xF0, 0x4E, 0x0F, 0x54, ++ 0x90, 0xE6, 0x79, 0x78, 0x05, 0x60, 0xE9, 0x09, 0x80, 0xF0, 0x09, 0x74, 0xF0, 0x01, 0x74, 0x03, ++ 0xE0, 0xEA, 0x09, 0x90, 0x06, 0x64, 0x0F, 0x54, 0x09, 0x90, 0x39, 0x70, 0xE0, 0x30, 0xE0, 0xB8, ++ 0xBF, 0x09, 0x90, 0x32, 0xF0, 0x02, 0x44, 0xE0, 0x74, 0xB5, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x09, ++ 0xFE, 0x54, 0xE0, 0xB8, 0xBB, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x12, 0x74, 0x95, 0x09, ++ 0x96, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x62, 0xE5, 0x62, 0xE5, 0x97, 0x09, 0x98, 0x09, 0x90, 0xF0, ++ 0x22, 0xF0, 0x62, 0xE5, 0x74, 0xAD, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x50, 0xCF, 0x54, 0xE0, 0xAB, ++ 0x90, 0xF0, 0x10, 0x44, 0x54, 0xE0, 0xAA, 0x07, 0x07, 0x90, 0xF0, 0xFD, 0x64, 0x45, 0xE0, 0x66, ++ 0x30, 0xA9, 0x07, 0x90, 0x44, 0xE0, 0x06, 0xE2, 0x04, 0x80, 0xF0, 0x40, 0xF0, 0xBF, 0x54, 0xE0, ++ 0xE0, 0xAA, 0x07, 0x90, 0x90, 0x08, 0xE1, 0x20, 0x30, 0xE0, 0x67, 0x07, 0x90, 0x22, 0xF2, 0xE0, ++ 0x70, 0xE0, 0xAC, 0x07, 0xAB, 0x07, 0x90, 0x21, 0x03, 0x54, 0xC4, 0xE0, 0x1F, 0x60, 0x03, 0x64, ++ 0xE0, 0xAB, 0x07, 0x90, 0x0F, 0x54, 0xC4, 0xFF, 0xCF, 0x54, 0xEF, 0xFE, 0x54, 0x04, 0xEE, 0xFF, ++ 0xF0, 0x54, 0xC4, 0x03, 0x07, 0x90, 0xF0, 0x4F, 0xFD, 0x54, 0xE0, 0xAA, 0x90, 0xC1, 0x80, 0xF0, ++ 0x54, 0xE0, 0xAB, 0x07, 0x22, 0x22, 0xF0, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x74, 0x61, 0x44, 0x09, 0x09, 0x00, 0x0A, 0x61, 0x44, 0x41, 0x42, 0x09, 0x47, 0x49, 0x53, 0x5F, ++ 0x09, 0x0A, 0x00, 0x0A, 0x4B, 0x4F, 0x4C, 0x09, 0x64, 0x25, 0x20, 0x3A, 0x09, 0x09, 0x00, 0x0A, ++ 0x3A, 0x4C, 0x56, 0x4C, 0x0A, 0x64, 0x25, 0x20, 0x50, 0x09, 0x09, 0x00, 0x20, 0x3A, 0x52, 0x57, ++ 0x0A, 0x20, 0x44, 0x25, 0x53, 0x09, 0x09, 0x00, 0x20, 0x3A, 0x52, 0x4E, 0x64, 0x20, 0x64, 0x25, ++ 0x09, 0x00, 0x0A, 0x42, 0x4F, 0x52, 0x46, 0x09, 0x44, 0x25, 0x20, 0x3A, 0x6D, 0x70, 0x70, 0x20, ++ 0x09, 0x09, 0x00, 0x0A, 0x3A, 0x51, 0x45, 0x4C, 0x44, 0x25, 0x20, 0x00, 0x09, 0x00, 0x0A, 0x00, ++ 0x45, 0x46, 0x44, 0x09, 0x09, 0x09, 0x00, 0x3A, 0x43, 0x53, 0x6F, 0x4C, 0x09, 0x00, 0x0A, 0x52, ++ 0x53, 0x6F, 0x4C, 0x09, 0x71, 0xE5, 0x00, 0x0A, 0xFF, 0x7B, 0x48, 0x60, 0x00, 0x79, 0x20, 0x7A, ++ 0x90, 0xF8, 0x03, 0x12, 0x44, 0xE0, 0x35, 0x06, 0x78, 0xE4, 0xF0, 0x01, 0xF6, 0x08, 0xF6, 0x7D, ++ 0x75, 0xF6, 0x7B, 0x78, 0x14, 0x75, 0x24, 0x13, 0x25, 0x11, 0x75, 0x47, 0x75, 0xE6, 0x12, 0x75, ++ 0x06, 0x90, 0x0C, 0x10, 0x13, 0x13, 0xE0, 0x31, 0xE0, 0x30, 0x3F, 0x54, 0xA6, 0x07, 0x90, 0x15, ++ 0xF0, 0xCF, 0x54, 0xE0, 0x90, 0x62, 0xF5, 0xE4, 0x44, 0xE0, 0x43, 0x08, 0xEC, 0xD2, 0xF0, 0x70, ++ 0x06, 0x90, 0xEE, 0xD2, 0xE0, 0x30, 0xE0, 0x29, 0x60, 0x62, 0xE5, 0x04, 0x29, 0x06, 0x90, 0x0D, ++ 0x3B, 0xE0, 0x20, 0xE0, 0x04, 0x64, 0x62, 0xE5, 0x06, 0x90, 0x35, 0x70, 0xE0, 0x30, 0xE0, 0x29, ++ 0x04, 0x62, 0x75, 0x05, 0xF5, 0xE4, 0x03, 0x80, 0x47, 0x07, 0x90, 0x62, 0xF0, 0xFB, 0x54, 0xE0, ++ 0xE0, 0x48, 0x07, 0x90, 0xE4, 0xF0, 0x04, 0x44, 0xF0, 0x52, 0x07, 0x90, 0xF0, 0x51, 0x07, 0x90, ++ 0xF0, 0x54, 0x07, 0x90, 0xF0, 0x53, 0x07, 0x90, 0xE0, 0x47, 0x07, 0x90, 0x90, 0xF0, 0x04, 0x44, ++ 0x60, 0xE0, 0x91, 0x07, 0x8F, 0x07, 0x90, 0x14, 0xF0, 0x01, 0x44, 0xE0, 0x74, 0x91, 0x07, 0x90, ++ 0x07, 0x90, 0xF0, 0x03, 0xFE, 0x54, 0xE0, 0x8F, 0xAE, 0x01, 0x90, 0xF0, 0xF0, 0x02, 0x44, 0xE0, ++ 0x07, 0x90, 0xFF, 0xE0, 0x13, 0xC4, 0xE0, 0x8B, 0xFE, 0x01, 0x54, 0x13, 0x54, 0x13, 0xC4, 0xEF, ++ 0x54, 0xEF, 0xFD, 0x01, 0x4E, 0xED, 0xFF, 0xDF, 0x33, 0xC4, 0x01, 0x54, 0x90, 0x4F, 0xE0, 0x54, ++ 0xE0, 0xF0, 0xAE, 0x01, 0x8B, 0x07, 0x90, 0xFF, 0x54, 0x13, 0xC4, 0xE0, 0x13, 0xEF, 0xFE, 0x01, ++ 0x01, 0x54, 0x13, 0x13, 0xF7, 0x54, 0xEF, 0xFD, 0x54, 0x4E, 0xED, 0xFF, 0x33, 0x33, 0x33, 0x01, ++ 0x90, 0x4F, 0xF8, 0x54, 0xE0, 0xF0, 0xAE, 0x01, 0x8B, 0x07, 0x90, 0xFF, 0x54, 0x13, 0xC3, 0xE0, ++ 0xC4, 0xEF, 0xFE, 0x01, 0xEF, 0xFD, 0x01, 0x54, 0xED, 0xFF, 0xEF, 0x54, 0xFE, 0x01, 0x54, 0x4E, ++ 0x4F, 0xF0, 0x54, 0xC4, 0xF0, 0xAE, 0x01, 0x90, 0x74, 0x8B, 0x07, 0x90, 0x73, 0x51, 0xF0, 0x62, ++ 0x61, 0xF5, 0x33, 0xE4, 0x09, 0x60, 0x61, 0xE5, 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x12, 0x07, 0x79, ++ 0xEF, 0x20, 0xAF, 0xF8, 0x20, 0x0F, 0x54, 0xC4, 0x20, 0xAF, 0x42, 0xE0, 0x3C, 0xE0, 0x20, 0xEF, ++ 0xC3, 0xEF, 0x20, 0xAF, 0x34, 0xE0, 0x20, 0x13, 0xC4, 0xEF, 0x20, 0xAF, 0x20, 0x07, 0x54, 0x13, ++ 0x20, 0xAF, 0x2A, 0xE0, 0x54, 0x13, 0x13, 0xEF, 0x20, 0xE0, 0x20, 0x3F, 0x1C, 0x70, 0x61, 0xE5, ++ 0x12, 0x65, 0x88, 0x74, 0x27, 0x74, 0x04, 0x70, 0x10, 0x60, 0x11, 0x65, 0x12, 0x65, 0xE6, 0x74, ++ 0x25, 0x74, 0x04, 0x70, 0x7A, 0x70, 0x11, 0x65, 0x76, 0x50, 0x14, 0x91, 0xEE, 0xC2, 0xEC, 0xC2, ++ 0xE0, 0x47, 0x07, 0x90, 0xE0, 0xF0, 0xFB, 0x54, 0x90, 0xF0, 0xEF, 0x54, 0xFF, 0x74, 0x66, 0x07, ++ 0x68, 0x07, 0x90, 0xF0, 0x01, 0x0D, 0x90, 0xF0, 0xF0, 0xDF, 0x54, 0xE0, 0xE0, 0x21, 0x0D, 0x90, ++ 0x90, 0xF0, 0xDF, 0x54, 0x54, 0xE0, 0x01, 0x0D, 0x0D, 0x90, 0xF0, 0xEF, 0xEF, 0x54, 0xE0, 0x21, ++ 0x55, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x44, 0xE0, 0xFE, 0x07, 0x54, 0xE0, 0xF0, 0x02, ++ 0x07, 0x90, 0xF0, 0xF7, 0x02, 0x44, 0xE0, 0xFD, 0xF7, 0x54, 0xE0, 0xF0, 0xA6, 0x07, 0x90, 0xF0, ++ 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0xFB, 0x07, 0x90, 0xE0, 0xF0, 0x01, 0x44, 0x90, 0xF0, 0x10, 0x44, ++ 0x44, 0xE0, 0x35, 0x06, 0x02, 0x7E, 0xF0, 0x01, 0x5D, 0x8E, 0x56, 0x7F, 0x59, 0x8E, 0x5E, 0x8F, ++ 0x30, 0x22, 0x5A, 0x8F, 0x07, 0x81, 0x02, 0x0B, 0xE6, 0x06, 0x7E, 0x78, 0x06, 0x01, 0x70, 0x18, ++ 0x64, 0xE6, 0x7E, 0x78, 0x60, 0x46, 0x18, 0x01, 0x90, 0x64, 0x61, 0x02, 0xF5, 0xE0, 0x59, 0x08, ++ 0x5A, 0x08, 0x90, 0x23, 0xE5, 0x24, 0xF5, 0xE0, 0x78, 0x23, 0xAE, 0x24, 0xE7, 0xA2, 0xCE, 0x06, ++ 0xD8, 0x13, 0xCE, 0x13, 0x06, 0xAC, 0xFD, 0xF8, 0x23, 0xAE, 0x24, 0xE5, 0xA2, 0xCE, 0x05, 0x78, ++ 0x13, 0xCE, 0x13, 0xE7, 0xFF, 0x2D, 0xF8, 0xD8, 0xEF, 0xFE, 0x3C, 0xEE, 0x24, 0xF5, 0x24, 0x25, ++ 0xF5, 0x23, 0x35, 0xEE, 0x46, 0x08, 0x90, 0x23, 0xED, 0x7D, 0xFF, 0xE0, 0x0B, 0x12, 0x21, 0x7C, ++ 0xAF, 0x25, 0x8F, 0xEF, 0x20, 0x06, 0x90, 0x24, 0x25, 0xE5, 0xF0, 0xEF, 0xAF, 0x0E, 0x94, 0xD3, ++ 0x7F, 0x02, 0x40, 0x25, 0x0F, 0x54, 0xEF, 0x0E, 0xFF, 0xF0, 0x54, 0xC4, 0xE0, 0x21, 0x06, 0x90, ++ 0xF0, 0x4F, 0x0F, 0x54, 0x2E, 0x08, 0x90, 0xE4, 0x9F, 0x54, 0xE0, 0xF0, 0x90, 0xF0, 0x40, 0x44, ++ 0xF5, 0xE0, 0x31, 0x08, 0x7A, 0xFF, 0x7B, 0x26, 0x78, 0x12, 0x79, 0x20, 0xE6, 0x06, 0x08, 0x76, ++ 0x70, 0x04, 0x86, 0x18, 0xFD, 0x14, 0x06, 0x01, 0x7B, 0xE5, 0x0C, 0x12, 0x79, 0x20, 0x7A, 0xFF, ++ 0xFE, 0x26, 0xE5, 0x1E, 0xE0, 0x32, 0x08, 0x90, 0xED, 0xFC, 0xEE, 0xFD, 0x7B, 0xE5, 0x0C, 0x12, ++ 0x79, 0x20, 0x7A, 0xFF, 0x47, 0x08, 0x90, 0x29, 0x00, 0x7C, 0xFD, 0xE0, 0x7B, 0xE5, 0x0C, 0x12, ++ 0x79, 0x20, 0x7A, 0xFF, 0xFD, 0x25, 0xE5, 0x35, 0x0C, 0x12, 0x00, 0x7C, 0x7A, 0xFF, 0x7B, 0xE5, ++ 0xAD, 0x43, 0x79, 0x20, 0x12, 0x23, 0xAC, 0x24, 0x26, 0xE5, 0xE5, 0x0C, 0x40, 0x01, 0x94, 0xD3, ++ 0x22, 0x07, 0x81, 0x02, 0x64, 0xE6, 0x7E, 0x78, 0x70, 0x46, 0x18, 0x02, 0x7A, 0xFF, 0x7B, 0x44, ++ 0x12, 0x52, 0x79, 0x20, 0x90, 0xE4, 0xF8, 0x03, 0xE0, 0xF0, 0x2E, 0x08, 0xE4, 0xF0, 0x9F, 0x54, ++ 0x22, 0xE5, 0x22, 0xF5, 0x90, 0xFF, 0x0F, 0x54, 0x54, 0xE0, 0x2E, 0x08, 0x7B, 0xF0, 0x4F, 0xF0, ++ 0x79, 0x20, 0x7A, 0xFF, 0x31, 0x08, 0x90, 0x59, 0x08, 0x90, 0xFE, 0xE0, 0xED, 0xFD, 0xE0, 0x32, ++ 0x12, 0x06, 0xAC, 0xFF, 0x22, 0x05, 0xE5, 0x0C, 0x94, 0xC3, 0x22, 0xE5, 0x80, 0xD3, 0x40, 0x0A, ++ 0xE6, 0x7E, 0x78, 0x4D, 0x46, 0x18, 0x03, 0x64, 0xFF, 0x7B, 0x4D, 0x70, 0x5F, 0x79, 0x20, 0x7A, ++ 0xE4, 0xF8, 0x03, 0x12, 0xF0, 0x2E, 0x08, 0x90, 0x44, 0x9F, 0x54, 0xE0, 0xF5, 0xE4, 0xF0, 0x20, ++ 0x54, 0x22, 0xE5, 0x22, 0x08, 0x90, 0xFF, 0x0F, 0xF0, 0x54, 0xE0, 0x2E, 0xFF, 0x7B, 0xF0, 0x4F, ++ 0x59, 0x79, 0x20, 0x7A, 0xE0, 0x31, 0x08, 0x90, 0x32, 0x08, 0x90, 0xFE, 0xFF, 0xED, 0xFD, 0xE0, ++ 0x0C, 0x12, 0x06, 0xAC, 0xE5, 0x22, 0x05, 0xE5, 0x08, 0x94, 0xC3, 0x22, 0xFF, 0x7B, 0xD3, 0x40, ++ 0x5D, 0x79, 0x20, 0x7A, 0x90, 0xF8, 0x03, 0x12, 0xD3, 0xE0, 0x46, 0x08, 0x02, 0x40, 0x3C, 0x94, ++ 0x22, 0xC3, 0x22, 0xD3, 0xE0, 0xA4, 0x07, 0x90, 0x40, 0xA0, 0x94, 0xD3, 0x7A, 0xFF, 0x7B, 0x08, ++ 0x80, 0x66, 0x79, 0x20, 0x47, 0x08, 0x90, 0x17, 0x03, 0x94, 0xC3, 0xE0, 0x7B, 0x78, 0x13, 0x50, ++ 0x0A, 0x94, 0x06, 0xE6, 0xFF, 0x7B, 0x0F, 0x40, 0x6F, 0x79, 0x20, 0x7A, 0xD3, 0xF8, 0x03, 0x12, ++ 0x7B, 0x78, 0xE4, 0x22, 0x90, 0x22, 0xC3, 0xF6, 0xFF, 0x74, 0x66, 0x07, 0x62, 0x45, 0xE0, 0xF0, ++ 0x90, 0x21, 0xE2, 0x30, 0x44, 0xE0, 0xA6, 0x07, 0x75, 0x91, 0xF0, 0x01, 0xE0, 0x47, 0x07, 0x90, ++ 0x90, 0xF0, 0x04, 0x44, 0x44, 0xE0, 0xB9, 0x01, 0x44, 0xE0, 0xF0, 0x08, 0x13, 0x75, 0xF0, 0x02, ++ 0xAC, 0x14, 0x75, 0x24, 0x7C, 0x50, 0x7D, 0x22, 0x90, 0x01, 0x7F, 0xC3, 0x54, 0xE0, 0x47, 0x07, ++ 0x54, 0xEF, 0xF0, 0xFB, 0x25, 0xE0, 0x25, 0x01, 0x07, 0x90, 0xFF, 0xE0, 0xFB, 0x54, 0xE0, 0x48, ++ 0x90, 0xE4, 0xF0, 0x4F, 0x90, 0xF0, 0x52, 0x07, 0xED, 0xF0, 0x51, 0x07, 0xF0, 0x54, 0x07, 0x90, ++ 0x53, 0x07, 0x90, 0xEC, 0x66, 0x07, 0x90, 0xF0, 0x22, 0xF0, 0x01, 0x74, 0x74, 0x66, 0x07, 0x90, ++ 0x45, 0xE0, 0xF0, 0x04, 0x0F, 0xE2, 0x20, 0x62, 0xE0, 0x47, 0x07, 0x90, 0x90, 0xF0, 0xFB, 0x54, ++ 0x01, 0x74, 0x66, 0x07, 0x90, 0x2B, 0x80, 0xF0, 0x30, 0xE0, 0x66, 0x07, 0x01, 0x74, 0x05, 0xE0, ++ 0x22, 0xD4, 0x91, 0xF0, 0xE0, 0x3E, 0x08, 0x90, 0xF0, 0xE4, 0x64, 0xF5, 0x04, 0x7C, 0xE2, 0x7D, ++ 0x7B, 0x91, 0x01, 0x7F, 0xE0, 0x47, 0x07, 0x90, 0x75, 0xF0, 0x04, 0x44, 0x14, 0x75, 0x25, 0x13, ++ 0x68, 0xB1, 0x22, 0x47, 0xE0, 0xA6, 0x07, 0x90, 0x90, 0xF0, 0xFE, 0x54, 0x54, 0xE0, 0xB9, 0x01, ++ 0x07, 0x90, 0xF0, 0xFD, 0xFB, 0x54, 0xE0, 0x47, 0x66, 0x07, 0x90, 0xF0, 0x75, 0xF0, 0x01, 0x74, ++ 0x14, 0x75, 0x24, 0x13, 0x07, 0x90, 0x22, 0x47, 0xF0, 0x02, 0x74, 0x66, 0x20, 0x62, 0x45, 0xE0, ++ 0xCE, 0x80, 0x02, 0xE2, 0xE0, 0x66, 0x07, 0x90, 0x74, 0x1B, 0xE0, 0x30, 0x63, 0xAF, 0xF0, 0x01, ++ 0x70, 0xEF, 0x63, 0x15, 0x91, 0x68, 0xB1, 0x11, 0x47, 0x07, 0x90, 0x75, 0xF0, 0x04, 0x44, 0xE0, ++ 0x75, 0x24, 0x13, 0x75, 0x90, 0x22, 0xAC, 0x14, 0x04, 0x74, 0x66, 0x07, 0x62, 0x45, 0xE0, 0xF0, ++ 0x90, 0x08, 0xE2, 0x20, 0x64, 0xE5, 0x3E, 0x08, 0x90, 0x97, 0x80, 0xF0, 0x30, 0xE0, 0x66, 0x07, ++ 0x01, 0x74, 0x05, 0xE0, 0x22, 0xA2, 0xB1, 0xF0, 0xE0, 0x23, 0x06, 0x90, 0x3F, 0x54, 0x13, 0x13, ++ 0x20, 0x0C, 0x0D, 0x90, 0x36, 0x74, 0x0E, 0xE0, 0x2C, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x15, 0x74, ++ 0x0C, 0x80, 0x01, 0x0D, 0x90, 0xF0, 0x15, 0x74, 0x36, 0x74, 0x2C, 0x0D, 0x21, 0x0D, 0x90, 0xF0, ++ 0xF0, 0xEF, 0x54, 0xE0, 0x74, 0xFE, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x02, 0x01, 0x44, 0xE0, 0xFB, ++ 0x0D, 0x90, 0x22, 0xF0, 0x10, 0x44, 0xE0, 0x01, 0x21, 0x0D, 0x90, 0xF0, 0xF0, 0x10, 0x44, 0xE0, ++ 0x74, 0x0C, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x11, 0x07, 0x90, 0xF0, 0x2C, 0xF0, 0x08, 0x74, 0xFE, ++ 0xE0, 0xFB, 0x07, 0x90, 0x75, 0xF0, 0xFE, 0x54, 0x08, 0x90, 0x50, 0x63, 0xF0, 0x64, 0xE5, 0x3E, ++ 0xF4, 0x7C, 0x24, 0x7D, 0x7B, 0x91, 0xFF, 0xE4, 0xE0, 0x47, 0x07, 0x90, 0x75, 0xF0, 0x04, 0x44, ++ 0x14, 0x75, 0x25, 0x13, 0x07, 0x90, 0x22, 0x16, 0xF0, 0x0A, 0x74, 0x68, 0xE0, 0xA4, 0x07, 0x90, ++ 0x40, 0xA0, 0x94, 0xD3, 0x90, 0x88, 0xE1, 0x02, 0x30, 0xE0, 0x68, 0x07, 0x67, 0x75, 0x31, 0xE2, ++ 0x90, 0xB4, 0xD1, 0x06, 0x44, 0xE0, 0x47, 0x07, 0x07, 0x90, 0xF0, 0x10, 0x01, 0x44, 0xE0, 0x8A, ++ 0x40, 0x08, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0x47, 0x08, 0x90, 0x04, 0x13, 0xC3, 0xFF, ++ 0x01, 0x90, 0x68, 0xF5, 0x04, 0x44, 0xE0, 0xB9, 0x01, 0x44, 0xE0, 0xF0, 0x90, 0x1E, 0x80, 0xF0, ++ 0x30, 0xE0, 0x68, 0x07, 0x01, 0x74, 0x16, 0xE0, 0x90, 0x7E, 0xD1, 0xF0, 0x54, 0xE0, 0x56, 0x08, ++ 0x07, 0xBF, 0xFF, 0x0F, 0x47, 0x07, 0x90, 0x07, 0xF0, 0xEF, 0x54, 0xE0, 0x45, 0x08, 0x90, 0x22, ++ 0x90, 0xF0, 0x68, 0xE5, 0x44, 0xE0, 0x40, 0x08, 0x54, 0xE0, 0xF0, 0x40, 0x08, 0x90, 0xF0, 0x7F, ++ 0x0F, 0x54, 0xE0, 0x44, 0x43, 0x08, 0x90, 0xF0, 0x44, 0x8F, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x60, ++ 0xF0, 0x08, 0x74, 0x68, 0x75, 0x18, 0x65, 0x75, 0x12, 0x75, 0x27, 0x11, 0x08, 0x90, 0x22, 0xD9, ++ 0xF0, 0x01, 0x74, 0x55, 0xE0, 0x56, 0x08, 0x90, 0x94, 0xC3, 0x0F, 0x54, 0xE0, 0x0B, 0x50, 0x07, ++ 0xFE, 0xF0, 0x54, 0xFF, 0x0F, 0x54, 0x04, 0xEF, 0x08, 0x90, 0xF0, 0x4E, 0x0F, 0x54, 0xE0, 0x56, ++ 0x40, 0x06, 0x94, 0xC3, 0x24, 0x08, 0x90, 0x0E, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0x27, 0x08, 0x90, ++ 0x22, 0xF0, 0xFB, 0x54, 0x09, 0x7C, 0xC4, 0x7D, 0x07, 0x90, 0xFF, 0xE4, 0xEF, 0x54, 0xE0, 0x47, ++ 0x01, 0x54, 0xEF, 0xF0, 0xFF, 0xF0, 0x54, 0xC4, 0xE0, 0x48, 0x07, 0x90, 0xF0, 0x4F, 0xEF, 0x54, ++ 0x5A, 0x07, 0x90, 0xE4, 0x59, 0x07, 0x90, 0xF0, 0x07, 0x90, 0xED, 0xF0, 0x90, 0xEC, 0xF0, 0x5C, ++ 0x90, 0xF0, 0x5B, 0x07, 0x01, 0x74, 0x68, 0x07, 0x65, 0x75, 0x22, 0xF0, 0x90, 0xB4, 0xD1, 0x0A, ++ 0x44, 0xE0, 0x47, 0x07, 0x08, 0x90, 0xF0, 0x10, 0x7F, 0x54, 0xE0, 0x40, 0x41, 0x08, 0x90, 0xF0, ++ 0x90, 0xF0, 0x01, 0x74, 0x09, 0x74, 0x68, 0x07, 0xFB, 0x07, 0x90, 0xF0, 0xF0, 0x10, 0x44, 0xE0, ++ 0x74, 0xFD, 0x07, 0x90, 0x08, 0x90, 0xF0, 0x02, 0xF0, 0x54, 0xE0, 0x56, 0xE4, 0xF0, 0x02, 0x44, ++ 0xF0, 0xA2, 0x07, 0x90, 0x74, 0x5E, 0x08, 0x90, 0x11, 0x75, 0xF0, 0x40, 0x30, 0x12, 0x75, 0x27, ++ 0xE0, 0x68, 0x07, 0x90, 0xE5, 0x12, 0xE3, 0x20, 0x00, 0x94, 0xD3, 0x65, 0x30, 0xE0, 0x0B, 0x40, ++ 0x65, 0x15, 0xEE, 0xE0, 0x80, 0xF0, 0x01, 0x74, 0x08, 0x90, 0xE4, 0xE7, 0x08, 0x90, 0xF0, 0x5E, ++ 0x07, 0x60, 0xE0, 0x41, 0x85, 0x35, 0x29, 0x12, 0x90, 0x22, 0x65, 0x69, 0x30, 0xE0, 0x68, 0x07, ++ 0x08, 0x90, 0x26, 0xE3, 0xF0, 0x05, 0x74, 0x55, 0xE0, 0x29, 0x08, 0x90, 0x90, 0xF0, 0xFD, 0x54, ++ 0x0A, 0x74, 0xA2, 0x07, 0x93, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0xFE, 0x74, 0x68, 0x07, ++ 0x28, 0x11, 0x75, 0xF0, 0x22, 0x52, 0x12, 0x75, 0x75, 0x27, 0x11, 0x75, 0x07, 0x90, 0x88, 0x12, ++ 0x01, 0x44, 0xE0, 0xFB, 0x10, 0x44, 0xE0, 0xF0, 0xEA, 0x01, 0x90, 0xF0, 0x03, 0x70, 0xF4, 0xE0, ++ 0x60, 0xF4, 0xE0, 0xA3, 0xEB, 0x01, 0x90, 0x0E, 0x70, 0xF0, 0x04, 0xE0, 0xEA, 0x01, 0x90, 0x06, ++ 0xC2, 0xF0, 0x04, 0xE0, 0x90, 0xEE, 0xC2, 0xEC, 0xFF, 0x74, 0x66, 0x07, 0x68, 0x07, 0x90, 0xF0, ++ 0x44, 0x08, 0x90, 0xF0, 0x44, 0x0F, 0x54, 0xE0, 0x08, 0x90, 0xF0, 0x20, 0x70, 0x44, 0xE0, 0x43, ++ 0x40, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0x68, 0x07, 0x90, 0x22, 0xE0, 0xF0, 0x02, 0x74, ++ 0x12, 0x0C, 0xE3, 0x30, 0x07, 0x90, 0x35, 0x29, 0xE3, 0x30, 0xE0, 0x68, 0x90, 0xEA, 0xC1, 0x3F, ++ 0x20, 0xE0, 0x68, 0x07, 0x29, 0x02, 0x03, 0xE2, 0x68, 0x07, 0x90, 0x1D, 0x2C, 0xE0, 0x30, 0xE0, ++ 0x01, 0x74, 0x65, 0x15, 0xD3, 0x65, 0xE5, 0xF0, 0x05, 0x40, 0x67, 0x95, 0x80, 0x7E, 0x26, 0x12, ++ 0x24, 0x08, 0x90, 0x14, 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x27, 0x08, 0x90, 0x90, 0xF0, 0x04, 0x44, ++ 0x15, 0x74, 0x55, 0x08, 0x70, 0x65, 0xE5, 0xF0, 0x88, 0x27, 0x12, 0x03, 0x68, 0x07, 0x90, 0x22, ++ 0x0D, 0xE3, 0x30, 0xE0, 0xE0, 0xF0, 0x08, 0x74, 0x85, 0x16, 0xE3, 0x30, 0x26, 0x02, 0x69, 0x65, ++ 0x68, 0x07, 0x90, 0xEA, 0x09, 0xE0, 0x30, 0xE0, 0xD5, 0xF0, 0x01, 0x74, 0x27, 0x12, 0x03, 0x65, ++ 0x07, 0x90, 0x22, 0x88, 0xE0, 0x30, 0xE0, 0x68, 0xF0, 0x09, 0x74, 0x75, 0xA2, 0x07, 0x90, 0xE4, ++ 0x68, 0x07, 0x90, 0xF0, 0x12, 0xE3, 0x20, 0xE0, 0x94, 0xD3, 0x65, 0xE5, 0xE0, 0x0B, 0x40, 0x00, ++ 0x15, 0xEE, 0xE0, 0x30, 0xF0, 0x01, 0x74, 0x65, 0x07, 0x90, 0xE7, 0x80, 0xF0, 0x02, 0x74, 0x68, ++ 0x90, 0x66, 0x65, 0x85, 0x60, 0xE0, 0x41, 0x08, 0x85, 0x35, 0x31, 0x07, 0x1D, 0x80, 0x65, 0x69, ++ 0xE0, 0x68, 0x07, 0x90, 0x11, 0x04, 0xE2, 0x20, 0xE5, 0x12, 0x80, 0xCF, 0x12, 0x05, 0x70, 0x65, ++ 0x09, 0x80, 0x88, 0x27, 0x06, 0x24, 0x65, 0xE5, 0x26, 0x12, 0x67, 0xF5, 0x01, 0x90, 0xC3, 0x4D, ++ 0xFF, 0x94, 0xE0, 0xB2, 0xE0, 0xB1, 0x01, 0x90, 0x12, 0x50, 0xFF, 0x94, 0x08, 0x94, 0x66, 0xE5, ++ 0xE0, 0xA3, 0x0C, 0x50, 0x06, 0x70, 0xF0, 0x04, 0xE0, 0xB1, 0x01, 0x90, 0x90, 0x22, 0xF0, 0x04, ++ 0x54, 0xE0, 0x8A, 0x07, 0x90, 0xE4, 0xF0, 0xFE, 0x90, 0xF0, 0x93, 0x07, 0x54, 0xE0, 0xB9, 0x01, ++ 0x08, 0x90, 0xF0, 0xFE, 0xF0, 0x01, 0x74, 0x55, 0x74, 0x45, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x7F, ++ 0x40, 0x44, 0xE0, 0x40, 0x80, 0x44, 0xE0, 0xF0, 0x44, 0x08, 0x90, 0xF0, 0x44, 0x0F, 0x54, 0xE0, ++ 0x08, 0x90, 0xF0, 0x20, 0x70, 0x44, 0xE0, 0x43, 0x40, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, ++ 0x74, 0x68, 0x07, 0x90, 0x11, 0x75, 0xF0, 0x09, 0xE6, 0x12, 0x75, 0x25, 0x00, 0xFF, 0xE4, 0x22, ++ 0xFB, 0x06, 0xBF, 0x0F, 0xE0, 0xA5, 0x07, 0x90, 0x07, 0x90, 0x0A, 0x70, 0x0E, 0x54, 0xE0, 0x68, ++ 0xCF, 0x11, 0x02, 0x70, 0x40, 0x08, 0x90, 0x22, 0xF0, 0x80, 0x44, 0xE0, 0x74, 0x21, 0x08, 0x90, ++ 0x08, 0x90, 0xF0, 0x0F, 0xF0, 0x03, 0x74, 0x29, 0x74, 0x27, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x07, ++ 0xF0, 0x03, 0x74, 0x1F, 0xE0, 0xFB, 0x07, 0x90, 0x90, 0xF0, 0xEF, 0x54, 0x01, 0x74, 0x1F, 0x08, ++ 0x27, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x05, 0x74, 0x0D, 0x74, 0x21, 0x08, 0xFD, 0x07, 0x90, 0xF0, ++ 0x75, 0xF0, 0x08, 0x74, 0x24, 0x7D, 0x60, 0x65, 0xFF, 0xE4, 0xF4, 0x7C, 0x90, 0xBA, 0x26, 0x12, ++ 0x44, 0xE0, 0x47, 0x07, 0x07, 0x90, 0xF0, 0x10, 0xF0, 0x2A, 0x74, 0xA2, 0x74, 0x68, 0x07, 0x90, ++ 0x11, 0x75, 0xF0, 0x08, 0x2D, 0x12, 0x75, 0x28, 0x00, 0x00, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x20, 0x7A, 0xFF, 0x7B, 0x03, 0x02, 0x09, 0x79, 0x30, 0x31, 0x09, 0xF8, 0x73, 0x61, 0x62, 0x30, ++ 0x4E, 0x20, 0x58, 0x65, 0x8F, 0x00, 0x0A, 0x53, 0xC7, 0x0B, 0x12, 0x22, 0x01, 0x0D, 0x90, 0xE4, ++ 0x7E, 0x01, 0x7F, 0xF0, 0xD1, 0x0B, 0x12, 0x0D, 0x05, 0x76, 0x7A, 0x78, 0x08, 0x05, 0x76, 0x08, ++ 0x76, 0x08, 0x05, 0x76, 0x00, 0x0D, 0x90, 0x05, 0x44, 0xF8, 0x54, 0xE0, 0x0D, 0x90, 0xF0, 0x05, ++ 0xF8, 0x54, 0xE0, 0x20, 0x90, 0xF0, 0x05, 0x44, 0x54, 0xE0, 0x40, 0x0D, 0xF0, 0x05, 0x44, 0xF8, ++ 0xE0, 0x60, 0x0D, 0x90, 0x05, 0x44, 0xF8, 0x54, 0x82, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0xAA, 0x74, ++ 0x35, 0x74, 0x0C, 0x0D, 0x7E, 0x0C, 0x7F, 0xF0, 0xD1, 0x0B, 0x12, 0x0D, 0xE0, 0x29, 0x06, 0x90, ++ 0x13, 0x13, 0x13, 0xFF, 0xE0, 0x20, 0x1F, 0x54, 0x06, 0x0D, 0x90, 0x1A, 0x7F, 0xF0, 0x9C, 0x74, ++ 0x12, 0x0D, 0x7E, 0x06, 0x0D, 0x90, 0xD1, 0x0B, 0xF0, 0x89, 0x74, 0x0A, 0x0D, 0x7E, 0x0A, 0x7F, ++ 0x51, 0xD1, 0x0B, 0x12, 0xF5, 0x07, 0x90, 0xB7, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, ++ 0xF0, 0xFD, 0x54, 0xE0, 0x0D, 0x70, 0x22, 0xE5, 0xE0, 0x26, 0x06, 0x90, 0x07, 0x54, 0x13, 0xC4, ++ 0x40, 0x03, 0x94, 0xC3, 0xF9, 0x07, 0x90, 0x0C, 0x90, 0xF0, 0x44, 0x74, 0x80, 0xF0, 0xFA, 0x07, ++ 0xF9, 0x07, 0x90, 0x0C, 0x90, 0xF0, 0x10, 0x74, 0x32, 0x74, 0xFA, 0x07, 0x09, 0x90, 0xE4, 0xF0, ++ 0x09, 0x90, 0xF0, 0xF3, 0x09, 0x90, 0xF0, 0xF2, 0x0A, 0x90, 0xF0, 0xF1, 0x09, 0x90, 0xF0, 0x00, ++ 0x09, 0x90, 0xF0, 0xFF, 0x09, 0x90, 0xF0, 0xFE, 0x90, 0xF0, 0x04, 0xF4, 0x90, 0xF0, 0x01, 0x0A, ++ 0x03, 0x74, 0xF0, 0x09, 0xFD, 0x09, 0x90, 0xF0, 0xF0, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, ++ 0x90, 0xF0, 0xFD, 0x09, 0x03, 0x74, 0xE9, 0x09, 0xF6, 0x09, 0x90, 0xF0, 0xE9, 0x09, 0x90, 0xF0, ++ 0x90, 0xF0, 0x01, 0x74, 0x08, 0x74, 0x93, 0x09, 0x92, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x03, 0x74, ++ 0x00, 0xF0, 0x91, 0x09, 0x00, 0x00, 0x00, 0x00, 0x14, 0x92, 0x09, 0x90, 0x91, 0x09, 0x90, 0xF0, ++ 0xC7, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x04, 0x74, 0xF0, 0x14, 0xCE, 0x09, 0x74, 0xCF, 0x09, 0x90, ++ 0x09, 0x90, 0xF0, 0x01, 0xF0, 0x05, 0x74, 0xD0, 0x74, 0xD1, 0x09, 0x90, 0x09, 0x74, 0xF0, 0x0B, ++ 0x60, 0x22, 0xE5, 0xF0, 0xA8, 0x00, 0x90, 0x22, 0x3E, 0x08, 0x90, 0xE0, 0xA9, 0x00, 0x90, 0xF0, ++ 0xA3, 0x08, 0x90, 0xE0, 0xAA, 0x00, 0x90, 0xF0, 0x08, 0x09, 0x90, 0xE0, 0xAB, 0x00, 0x90, 0xF0, ++ 0x6D, 0x09, 0x90, 0xE0, 0xE4, 0x05, 0x80, 0xF0, 0xF0, 0xD2, 0x09, 0x90, 0x74, 0xCC, 0x09, 0x90, ++ 0x01, 0x74, 0xF0, 0x03, 0xCB, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x05, 0x74, 0x03, 0x74, 0xCA, 0x09, ++ 0xF0, 0x01, 0x74, 0xF0, 0x74, 0xD4, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x3F, 0xF0, 0x14, 0x74, 0xD8, ++ 0x74, 0xD7, 0x09, 0x90, 0x09, 0x90, 0xF0, 0xEE, 0xF0, 0x01, 0x74, 0xD6, 0x74, 0xD4, 0x09, 0x90, ++ 0x22, 0xE5, 0xF0, 0x33, 0x01, 0x7F, 0x04, 0x60, 0x02, 0x7F, 0x02, 0x80, 0x90, 0x60, 0x02, 0x12, ++ 0xC4, 0xE0, 0x26, 0x06, 0xC3, 0x07, 0x54, 0x13, 0x08, 0x40, 0x03, 0x94, 0xE0, 0xA9, 0x07, 0x90, ++ 0x14, 0x80, 0xFB, 0x54, 0x07, 0x90, 0x22, 0xE5, 0xE0, 0x0A, 0x60, 0xA9, 0xE0, 0xF0, 0xFB, 0x54, ++ 0x80, 0xF0, 0x08, 0x44, 0x04, 0x44, 0xE0, 0x08, 0xF7, 0x54, 0xE0, 0xF0, 0xA8, 0x07, 0x90, 0xF0, ++ 0x90, 0xF0, 0xFF, 0x74, 0xE4, 0xF0, 0xA7, 0x07, 0xF0, 0xA8, 0x07, 0x90, 0x74, 0xB0, 0x07, 0x90, ++ 0x07, 0x90, 0xF0, 0xAA, 0x02, 0x44, 0xE0, 0xAE, 0xAF, 0x07, 0x90, 0xF0, 0xF0, 0x02, 0x44, 0xE0, ++ 0xF0, 0xFD, 0x54, 0xE0, 0xE0, 0xA9, 0x07, 0x90, 0x01, 0x44, 0xFC, 0x54, 0x8F, 0x07, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x8E, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, 0x54, 0xE0, 0x90, 0x07, ++ 0xF0, 0x03, 0x44, 0xF0, 0x74, 0x91, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x03, 0xFE, 0x54, 0xE0, 0x8E, ++ 0x8F, 0x07, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0x93, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, ++ 0x44, 0xE0, 0x92, 0x07, 0x07, 0x90, 0xF0, 0x01, 0xF0, 0x54, 0xE0, 0x94, 0x90, 0xF0, 0x03, 0x44, ++ 0x03, 0x74, 0x95, 0x07, 0x92, 0x07, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0x93, 0x07, 0x90, ++ 0x90, 0xF0, 0xFE, 0x54, 0x0D, 0x74, 0xF3, 0x07, 0x26, 0x06, 0x90, 0xF0, 0x54, 0x13, 0xC4, 0xE0, ++ 0x60, 0xFE, 0x24, 0x07, 0x22, 0x70, 0x04, 0x1D, 0x74, 0x79, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x03, ++ 0xF0, 0x54, 0xE0, 0x94, 0x90, 0xF0, 0x02, 0x44, 0x54, 0xE0, 0x90, 0x07, 0xF0, 0x02, 0x44, 0xF0, ++ 0x07, 0x90, 0x0D, 0x80, 0xF0, 0x01, 0x74, 0x79, 0x90, 0xE4, 0x05, 0x80, 0x90, 0xF0, 0x79, 0x07, ++ 0x44, 0xE0, 0x07, 0x07, 0xE4, 0x22, 0xF0, 0x10, 0xF0, 0xF1, 0x07, 0x90, 0xE0, 0x27, 0x06, 0x90, ++ 0x90, 0x13, 0xE0, 0x30, 0xFE, 0xE0, 0x22, 0x06, 0x02, 0x78, 0xE0, 0xA3, 0xCE, 0x13, 0xC3, 0xCE, ++ 0x30, 0xF9, 0xD8, 0x13, 0x06, 0x90, 0x1A, 0xE0, 0xE0, 0x20, 0xE0, 0x27, 0x26, 0x06, 0x90, 0x1C, ++ 0xE0, 0xA3, 0xFE, 0xE0, 0xC3, 0xCE, 0x02, 0x78, 0xD8, 0x13, 0xCE, 0x13, 0x09, 0xE0, 0x20, 0xF9, ++ 0xE0, 0xF1, 0x07, 0x90, 0x80, 0xF0, 0x04, 0x44, 0xF1, 0x07, 0x90, 0x13, 0xF0, 0x01, 0x44, 0xE0, ++ 0xE0, 0xA8, 0x00, 0x90, 0xA3, 0xF0, 0x04, 0xF4, 0xF0, 0x04, 0xF4, 0xE0, 0xE0, 0x27, 0x06, 0x90, ++ 0x90, 0x13, 0xE0, 0x30, 0xFE, 0xE0, 0x22, 0x06, 0x02, 0x78, 0xE0, 0xA3, 0xCE, 0x13, 0xC3, 0xCE, ++ 0x30, 0xF9, 0xD8, 0x13, 0x06, 0x90, 0x1A, 0xE0, 0xE0, 0x20, 0xE0, 0x27, 0x26, 0x06, 0x90, 0x1C, ++ 0xE0, 0xA3, 0xFE, 0xE0, 0xC3, 0xCE, 0x03, 0x78, 0xD8, 0x13, 0xCE, 0x13, 0x09, 0xE0, 0x20, 0xF9, ++ 0xE0, 0xF1, 0x07, 0x90, 0x80, 0xF0, 0xE0, 0x44, 0xF1, 0x07, 0x90, 0x13, 0xF0, 0xB0, 0x44, 0xE0, ++ 0xE0, 0xAA, 0x00, 0x90, 0xA3, 0xF0, 0x04, 0xF4, 0xF0, 0x04, 0xF4, 0xE0, 0xE0, 0xF1, 0x07, 0x90, ++ 0xF0, 0xF2, 0x07, 0x90, 0x00, 0x00, 0x22, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x0D, 0x92, 0x0C, 0xA2, 0x72, 0x50, 0x34, 0x80, 0x6E, 0x65, 0x76, 0x65, 0x69, 0x4C, 0x20, 0x74, ++ 0x72, 0x65, 0x6B, 0x6E, 0x72, 0x72, 0x45, 0x20, 0x09, 0x00, 0x72, 0x6F, 0x65, 0x77, 0x6F, 0x50, ++ 0x67, 0x6E, 0x69, 0x72, 0x77, 0x6F, 0x44, 0x20, 0x09, 0x00, 0x0A, 0x6E, 0x65, 0x77, 0x6F, 0x50, ++ 0x67, 0x6E, 0x69, 0x72, 0x0A, 0x70, 0x55, 0x20, 0x20, 0x90, 0x01, 0x00, 0x70, 0x93, 0xE4, 0x06, ++ 0x0D, 0xC2, 0x00, 0x01, 0x60, 0x71, 0xE5, 0x22, 0x20, 0x5B, 0x75, 0x14, 0xD2, 0x7B, 0x5C, 0x75, ++ 0x4B, 0x07, 0x90, 0x08, 0x90, 0xF0, 0xF4, 0x74, 0x24, 0x74, 0x4C, 0x07, 0x65, 0x60, 0xE5, 0xF0, ++ 0xE5, 0x04, 0x70, 0x5C, 0x60, 0x5B, 0x65, 0x5F, 0x5F, 0x5B, 0x85, 0x08, 0xD2, 0x60, 0x5C, 0x85, ++ 0xA9, 0x5F, 0xAA, 0x08, 0xFF, 0x02, 0x12, 0x60, 0x30, 0x22, 0x08, 0xC2, 0xFF, 0x7B, 0x1C, 0x08, ++ 0x1B, 0x79, 0x20, 0x7A, 0xE4, 0xF8, 0x03, 0x12, 0xF0, 0xAD, 0x01, 0x90, 0x01, 0x90, 0xF0, 0xA3, ++ 0x01, 0x44, 0xE0, 0xAD, 0x07, 0x90, 0xE4, 0xF0, 0x20, 0xAF, 0xF0, 0xF0, 0x0C, 0xE0, 0x20, 0xEF, ++ 0xE0, 0x00, 0x06, 0x90, 0x54, 0x13, 0x13, 0x13, 0x06, 0xE0, 0x20, 0x1F, 0x75, 0x20, 0x5B, 0x75, ++ 0x7B, 0x22, 0xB3, 0x5C, 0x79, 0x20, 0x7A, 0xFF, 0xF8, 0x03, 0x12, 0x2B, 0xE0, 0xAD, 0x01, 0x90, ++ 0x90, 0xF0, 0xFE, 0x54, 0x0F, 0x74, 0xF0, 0x07, 0x01, 0x5D, 0x75, 0xF0, 0x22, 0xC5, 0x5E, 0x75, ++ 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++}; ++ ++/* GPHY firmware PHY_1V5_11G_IP_VR9_A22_T040B */ ++static const char gphy_ge_fw_data_a12 [] = { ++ 0x80, 0xF1, 0x02, 0x02, 0x32, 0x32, 0x32, 0x00, 0x80, 0x32, 0x32, 0x32, 0x00, 0x00, 0x32, 0xF9, ++ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEB, ++ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3B, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDC, ++ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x91, 0xE1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x94, ++ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8F, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFA, 0x0A, ++ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x0B, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x67, 0x0B, ++ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 0x0B, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9D, ++ 0x80, 0x00, 0x00, 0x00, 0x54, 0x90, 0xE5, 0x98, 0xC0, 0x03, 0xC4, 0x0F, 0xC0, 0x03, 0x74, 0xE0, ++ 0xC0, 0x82, 0xC0, 0xE0, 0x00, 0x03, 0x02, 0x83, 0x0F, 0x54, 0x90, 0xE5, 0xE0, 0xC0, 0x03, 0xC4, ++ 0xE0, 0xC0, 0x03, 0x74, 0x83, 0xC0, 0x82, 0xC0, 0xE5, 0x08, 0x03, 0x02, 0xC4, 0x0F, 0x54, 0x90, ++ 0x74, 0xE0, 0xC0, 0x03, 0xC0, 0xE0, 0xC0, 0x03, 0x02, 0x83, 0xC0, 0x82, 0x90, 0xE5, 0x10, 0x03, ++ 0x03, 0xC4, 0x0F, 0x54, 0x03, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, 0xC0, 0x03, 0x02, 0x83, 0xC0, ++ 0x54, 0x90, 0xE5, 0x18, 0xC0, 0x03, 0xC4, 0x0F, 0xC0, 0x03, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, ++ 0x20, 0x03, 0x02, 0x83, 0x0F, 0x54, 0x90, 0xE5, 0xE0, 0xC0, 0x03, 0xC4, 0xE0, 0xC0, 0x03, 0x74, ++ 0x83, 0xC0, 0x82, 0xC0, 0xE5, 0x28, 0x03, 0x02, 0xC4, 0x0F, 0x54, 0x90, 0x74, 0xE0, 0xC0, 0x03, ++ 0xC0, 0xE0, 0xC0, 0x03, 0x02, 0x83, 0xC0, 0x82, 0x90, 0xE5, 0x30, 0x03, 0x03, 0xC4, 0x0F, 0x54, ++ 0x03, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, 0xC0, 0x03, 0x02, 0x83, 0xC0, 0x54, 0x90, 0xE5, 0x38, ++ 0xC0, 0x03, 0xC4, 0x0F, 0xC0, 0x03, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, 0x40, 0x03, 0x02, 0x83, ++ 0x0F, 0x54, 0x90, 0xE5, 0xE0, 0xC0, 0x03, 0xC4, 0xE0, 0xC0, 0x03, 0x74, 0x83, 0xC0, 0x82, 0xC0, ++ 0xE5, 0x48, 0x03, 0x02, 0xC4, 0x0F, 0x54, 0x90, 0x74, 0xE0, 0xC0, 0x03, 0xC0, 0xE0, 0xC0, 0x03, ++ 0x02, 0x83, 0xC0, 0x82, 0x90, 0xE5, 0x50, 0x03, 0x03, 0xC4, 0x0F, 0x54, 0x03, 0x74, 0xE0, 0xC0, ++ 0x82, 0xC0, 0xE0, 0xC0, 0x03, 0x02, 0x83, 0xC0, 0x54, 0x90, 0xE5, 0x58, 0xC0, 0x03, 0xC4, 0x0F, ++ 0xC0, 0x03, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, 0x60, 0x03, 0x02, 0x83, 0x0F, 0x54, 0x90, 0xE5, ++ 0xE0, 0xC0, 0x03, 0xC4, 0xE0, 0xC0, 0x03, 0x74, 0x83, 0xC0, 0x82, 0xC0, 0xE5, 0x68, 0x03, 0x02, ++ 0xC4, 0x0F, 0x54, 0x90, 0x74, 0xE0, 0xC0, 0x03, 0xC0, 0xE0, 0xC0, 0x03, 0x02, 0x83, 0xC0, 0x82, ++ 0x90, 0xE5, 0x70, 0x03, 0x03, 0xC4, 0x0F, 0x54, 0x03, 0x74, 0xE0, 0xC0, 0x82, 0xC0, 0xE0, 0xC0, ++ 0x03, 0x02, 0x83, 0xC0, 0x03, 0xC4, 0xEF, 0x78, 0x73, 0x00, 0x03, 0x90, 0x01, 0x00, 0x20, 0x90, ++ 0x9A, 0x22, 0x90, 0x88, 0x20, 0x90, 0x88, 0x01, 0x90, 0x9B, 0x01, 0x00, 0x9B, 0x01, 0x02, 0x20, ++ 0x01, 0x9A, 0x28, 0x90, 0x00, 0x20, 0x90, 0x9B, 0x24, 0x90, 0xAE, 0x01, 0x90, 0xAE, 0x01, 0xE4, ++ 0xC1, 0x01, 0x00, 0x20, 0x01, 0x6B, 0x2D, 0x90, 0x00, 0x20, 0x90, 0xC1, 0x20, 0x90, 0xD4, 0x01, ++ 0x90, 0xD4, 0x01, 0xE7, 0xE7, 0x01, 0x48, 0x30, 0x01, 0xFE, 0x2A, 0x90, 0xC6, 0x27, 0x90, 0xFA, ++ 0x2D, 0x90, 0x0D, 0x21, 0x90, 0x20, 0x21, 0xA8, 0x33, 0x21, 0x7F, 0x32, 0x21, 0xAC, 0x2F, 0x90, ++ 0x33, 0x2A, 0x90, 0x46, 0x20, 0x90, 0x59, 0x21, 0x90, 0x6C, 0x21, 0x00, 0x7F, 0x21, 0xE0, 0x23, ++ 0x21, 0x17, 0x20, 0x90, 0xA6, 0x21, 0x90, 0x92, 0x22, 0x90, 0x88, 0x01, 0x90, 0x88, 0x01, 0x08, ++ 0x88, 0x01, 0xED, 0x20, 0x01, 0x8C, 0x20, 0x90, 0x56, 0x26, 0x90, 0x9B, 0x22, 0x90, 0x9B, 0x01, ++ 0x90, 0xAE, 0x01, 0x4D, 0xC1, 0x01, 0x75, 0x23, 0x01, 0xA1, 0x2C, 0x90, 0x45, 0x20, 0x90, 0xC1, ++ 0x2C, 0x90, 0xD4, 0x01, 0x90, 0xE7, 0x01, 0xD1, 0xFA, 0x01, 0x0B, 0x22, 0x01, 0xBE, 0x24, 0x90, ++ 0xC5, 0x24, 0x90, 0xFA, 0x20, 0x90, 0xFA, 0x01, 0x90, 0x0D, 0x21, 0x44, 0x20, 0x21, 0x91, 0x20, ++ 0x21, 0x97, 0x22, 0x90, 0xF5, 0x20, 0x90, 0x33, 0x20, 0x90, 0x33, 0x21, 0x90, 0x46, 0x21, 0x5E, ++ 0x59, 0x21, 0x76, 0x20, 0x21, 0x15, 0x20, 0x90, 0x00, 0x20, 0x90, 0x7F, 0x20, 0x90, 0x7F, 0x21, ++ 0x00, 0x92, 0x21, 0x10, 0xA4, 0xF0, 0x8D, 0xEF, 0x8C, 0xCF, 0xF0, 0xA8, 0xCE, 0x28, 0xA4, 0xF0, ++ 0x2E, 0xA4, 0xF0, 0x8D, 0x00, 0xBC, 0x22, 0xFE, 0x29, 0x00, 0xBE, 0x0B, 0x84, 0xF0, 0x8D, 0xEF, ++ 0x22, 0xF0, 0xAD, 0xFF, 0x75, 0xF8, 0xCC, 0xE4, 0x2F, 0xEF, 0x08, 0xF0, 0xFE, 0x33, 0xEE, 0xFF, ++ 0xEE, 0xFC, 0x33, 0xEC, 0x40, 0x98, 0xEC, 0x9D, 0x9D, 0xEE, 0xFC, 0x05, 0xF0, 0xD5, 0x0F, 0xFE, ++ 0xFD, 0xCE, 0xE4, 0xE9, 0xF5, 0xF8, 0xED, 0x22, 0x20, 0x84, 0xEE, 0xF0, 0xAD, 0xFE, 0x1C, 0xD2, ++ 0x08, 0xF0, 0x75, 0xF0, 0xED, 0xFF, 0x2F, 0xEF, 0x07, 0x40, 0xFD, 0x33, 0xD5, 0x06, 0x50, 0x98, ++ 0xC3, 0x22, 0xF2, 0xF0, 0xD5, 0x0F, 0xFD, 0x98, 0x8A, 0x22, 0xEA, 0xF0, 0xE4, 0x82, 0x89, 0x83, ++ 0x94, 0x81, 0x75, 0x73, 0xE4, 0xB0, 0x03, 0x02, 0xF0, 0xBF, 0x01, 0x90, 0x00, 0x00, 0x00, 0x22, ++ 0x22, 0xF0, 0x90, 0x53, 0x00, 0x00, 0x00, 0x00, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF1, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF2, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF3, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF4, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF5, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF6, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF7, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF8, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xF9, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xFA, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xFB, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xFC, 0x90, 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xFD, 0x90, ++ 0x53, 0x0F, 0x90, 0x43, 0x00, 0x22, 0xFE, 0x90, 0x22, 0x0F, 0x90, 0x43, 0x38, 0x3E, 0x2D, 0x09, ++ 0x73, 0x74, 0x69, 0x62, 0x0A, 0x64, 0x25, 0x20, 0x3E, 0x2D, 0x09, 0x00, 0x74, 0x69, 0x62, 0x39, ++ 0x64, 0x25, 0x20, 0x73, 0x2D, 0x09, 0x00, 0x0A, 0x69, 0x62, 0x37, 0x3E, 0x25, 0x20, 0x73, 0x74, ++ 0x09, 0x00, 0x0A, 0x64, 0x62, 0x36, 0x3E, 0x2D, 0x20, 0x73, 0x74, 0x69, 0x00, 0x0A, 0x64, 0x25, ++ 0x12, 0x03, 0x60, 0xE4, 0xB0, 0x75, 0xEE, 0x0E, 0x31, 0xCB, 0x71, 0xFF, 0x90, 0x09, 0x91, 0xAC, ++ 0x44, 0xE0, 0x07, 0x07, 0x87, 0x43, 0xF0, 0x10, 0x75, 0xFB, 0x80, 0x01, 0x1A, 0x75, 0x07, 0x19, ++ 0x7F, 0x0E, 0x7E, 0x12, 0x7E, 0xDF, 0x71, 0xEE, 0x71, 0x9A, 0x7F, 0x22, 0xEF, 0x15, 0x41, 0xDF, ++ 0xEE, 0xFF, 0x10, 0x24, 0xEF, 0xFE, 0xE0, 0x34, 0xFF, 0x24, 0xF0, 0x54, 0xFF, 0x34, 0xEE, 0xFF, ++ 0xFD, 0x1A, 0xE5, 0xFE, 0x1A, 0xF5, 0x02, 0x24, 0x34, 0xFC, 0x19, 0xE5, 0x8D, 0x19, 0xF5, 0x00, ++ 0xEE, 0x83, 0x8C, 0x82, 0xF0, 0xEF, 0xA3, 0xF0, 0xA8, 0xF5, 0xE4, 0x22, 0xAC, 0xD2, 0xE8, 0xF5, ++ 0xE9, 0xD2, 0xEA, 0xD2, 0xF9, 0x75, 0xE8, 0xD2, 0xF1, 0xF8, 0x75, 0xF0, 0xB8, 0x75, 0xB9, 0xF5, ++ 0x22, 0xAF, 0xD2, 0x10, 0x74, 0x4B, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x13, 0xF0, 0x88, 0x74, 0x4C, ++ 0x01, 0x90, 0xFF, 0xE4, 0xE4, 0xF0, 0xEF, 0xBD, 0xC0, 0x22, 0xF0, 0xA3, 0xC0, 0x83, 0xC0, 0xE0, ++ 0x75, 0xD0, 0xC0, 0x82, 0xA2, 0x63, 0x00, 0xD0, 0xC0, 0x83, 0xC0, 0x01, 0x01, 0xA2, 0x63, 0x82, ++ 0x07, 0xC0, 0x06, 0xC0, 0xC2, 0x23, 0x99, 0x30, 0xB5, 0x1B, 0xE5, 0x99, 0x0A, 0x30, 0x03, 0x1C, ++ 0x05, 0x1B, 0xAF, 0x17, 0x74, 0x00, 0x7E, 0x1B, 0x82, 0xF5, 0x2F, 0xAC, 0xF5, 0x00, 0x34, 0xEE, ++ 0x99, 0xF5, 0xE0, 0x83, 0x02, 0x80, 0x0A, 0xC2, 0x07, 0xD0, 0x0B, 0xC2, 0xA2, 0x63, 0x06, 0xD0, ++ 0xD0, 0x82, 0xD0, 0x01, 0x01, 0xA2, 0x63, 0x83, 0x82, 0xD0, 0xD0, 0xD0, 0xE0, 0xD0, 0x83, 0xD0, ++ 0xC0, 0xE0, 0xC0, 0x32, 0xC0, 0x83, 0xC0, 0xF0, 0x75, 0xD0, 0xC0, 0x82, 0xA2, 0x63, 0x00, 0xD0, ++ 0xC0, 0x83, 0xC0, 0x01, 0x01, 0xA2, 0x63, 0x82, 0x01, 0xC0, 0x00, 0xC0, 0x03, 0xC0, 0x02, 0xC0, ++ 0x05, 0xC0, 0x04, 0xC0, 0x07, 0xC0, 0x06, 0xC0, 0xE0, 0x02, 0x07, 0x90, 0x54, 0xAF, 0x54, 0xF5, ++ 0x13, 0x13, 0xC4, 0xEF, 0x30, 0x01, 0x54, 0x13, 0x65, 0xC1, 0x02, 0xE0, 0x54, 0xEF, 0x54, 0xAF, ++ 0x70, 0xFC, 0x24, 0x7F, 0x24, 0xA1, 0xA1, 0x02, 0xA1, 0x02, 0x70, 0xFD, 0x70, 0xFE, 0x24, 0xBB, ++ 0x24, 0xC4, 0xA1, 0x02, 0xA1, 0x02, 0x70, 0xFC, 0x02, 0x70, 0x14, 0xE3, 0xF9, 0x24, 0xFD, 0xA1, ++ 0x3A, 0xC1, 0x02, 0x70, 0x02, 0x60, 0x15, 0x24, 0x06, 0x90, 0xF7, 0xC1, 0x13, 0xC4, 0xE0, 0x00, ++ 0x01, 0x54, 0x13, 0x13, 0xC2, 0x19, 0xE0, 0x30, 0x80, 0x06, 0x90, 0xE8, 0xF0, 0x80, 0x44, 0xE0, ++ 0xE0, 0x00, 0x06, 0x90, 0xAF, 0xF0, 0x80, 0x44, 0x01, 0x44, 0xEF, 0x20, 0xF7, 0xC1, 0x20, 0xF5, ++ 0xE0, 0x00, 0x06, 0x90, 0x20, 0x0F, 0x54, 0xC4, 0x54, 0xE0, 0x16, 0xE0, 0x06, 0x90, 0xF0, 0xFD, ++ 0xDF, 0x54, 0xE0, 0x03, 0xAF, 0x0E, 0xC2, 0xF0, 0x20, 0x44, 0xEF, 0x20, 0x28, 0x80, 0x20, 0xF5, ++ 0xE0, 0x00, 0x06, 0x90, 0xE0, 0x25, 0x02, 0x54, 0xEE, 0x20, 0xAE, 0xFF, 0xF5, 0x4F, 0xFB, 0x54, ++ 0x20, 0x00, 0x7F, 0x20, 0x01, 0x7F, 0x02, 0x0E, 0xC4, 0x01, 0x54, 0xEF, 0xFF, 0xE0, 0x54, 0x33, ++ 0x54, 0xEE, 0x20, 0xAE, 0x20, 0xF5, 0x4F, 0xDF, 0xE0, 0x01, 0x06, 0x90, 0x13, 0x13, 0x13, 0xC4, ++ 0x90, 0xFF, 0x01, 0x54, 0xC4, 0xE0, 0x00, 0x06, 0x01, 0x54, 0x13, 0x13, 0x13, 0xE0, 0xFF, 0x4F, ++ 0x4F, 0x01, 0x54, 0x13, 0x54, 0xC4, 0x01, 0x54, 0x20, 0xAE, 0xFF, 0xF0, 0x4F, 0xEF, 0x54, 0xEE, ++ 0x54, 0xE0, 0x20, 0xF5, 0x54, 0x13, 0x13, 0x08, 0x20, 0xAE, 0xFF, 0x3F, 0x80, 0xFD, 0x54, 0xEE, ++ 0x02, 0x0E, 0x30, 0x3D, 0x06, 0x90, 0xF7, 0xC1, 0x54, 0xC4, 0xE0, 0x00, 0x02, 0xE0, 0x20, 0x0F, ++ 0x20, 0xAF, 0xF7, 0xC1, 0xF5, 0x04, 0x44, 0xEF, 0xAF, 0xF7, 0xC1, 0x20, 0x08, 0x44, 0xEF, 0x20, ++ 0xF7, 0xC1, 0x20, 0xF5, 0xE0, 0x12, 0x06, 0x90, 0x07, 0x54, 0x13, 0xC4, 0x02, 0x60, 0x00, 0x7F, ++ 0x54, 0xEF, 0x01, 0x7F, 0xF0, 0x54, 0xC4, 0x01, 0xEE, 0x20, 0xAE, 0xFF, 0xF5, 0x4F, 0xEF, 0x54, ++ 0x90, 0xF7, 0xC1, 0x20, 0xFF, 0xE0, 0x1A, 0x06, 0x54, 0x13, 0x13, 0xC4, 0xC1, 0x02, 0x60, 0x03, ++ 0x1C, 0x06, 0x90, 0xD4, 0xA3, 0xF0, 0x1D, 0xE5, 0xC1, 0xF0, 0x1E, 0xE5, 0x1A, 0x06, 0x90, 0xF7, ++ 0x13, 0xC4, 0xFF, 0xE0, 0x70, 0x03, 0x54, 0x13, 0x1C, 0x06, 0x90, 0x0D, 0xE0, 0xA3, 0xFE, 0xE0, ++ 0x1E, 0xF5, 0x1D, 0x8E, 0x1C, 0xF1, 0xF7, 0xC1, 0xE0, 0x1A, 0x06, 0x90, 0x13, 0x13, 0xC4, 0xFF, ++ 0x02, 0x64, 0x03, 0x54, 0xC4, 0xE0, 0x0A, 0x60, 0x03, 0x54, 0x13, 0x13, 0x08, 0x03, 0xBF, 0xFF, ++ 0x1E, 0xE5, 0x1E, 0x05, 0x1D, 0x05, 0x02, 0x70, 0x07, 0x90, 0xD4, 0xC1, 0x07, 0x54, 0xE0, 0x93, ++ 0x2A, 0x06, 0x90, 0xFF, 0x6F, 0x0F, 0x54, 0xE0, 0x07, 0x90, 0x0A, 0x60, 0x06, 0x90, 0xE0, 0x92, ++ 0xF0, 0xE4, 0xF0, 0x2B, 0xE0, 0x2A, 0x06, 0x90, 0x90, 0xFF, 0x07, 0x54, 0x54, 0xE0, 0x93, 0x07, ++ 0xC1, 0xF0, 0x4F, 0xF8, 0xEF, 0x54, 0xAF, 0xF7, 0xFA, 0x24, 0x7F, 0x54, 0xFC, 0x24, 0x21, 0x60, ++ 0xFC, 0x24, 0x34, 0x60, 0xFD, 0x24, 0x3D, 0x60, 0xFC, 0x24, 0x5F, 0x60, 0xFB, 0x24, 0x64, 0x60, ++ 0x19, 0x24, 0x67, 0x60, 0x06, 0x90, 0x71, 0x70, 0xEF, 0x54, 0xE0, 0x03, 0x90, 0x11, 0x80, 0xF0, ++ 0x54, 0xE0, 0x0D, 0x06, 0x01, 0x90, 0xF0, 0xEF, 0xE0, 0x20, 0xE0, 0xFF, 0x0D, 0x06, 0x90, 0x5A, ++ 0xF0, 0xFD, 0x54, 0xE0, 0x06, 0x90, 0x51, 0x80, 0x7F, 0x54, 0xE0, 0x14, 0xE4, 0xE0, 0xA3, 0xF0, ++ 0x90, 0x44, 0x80, 0xF0, 0xC4, 0xE0, 0x1A, 0x06, 0x03, 0x54, 0x13, 0x13, 0x08, 0x02, 0xBF, 0xFF, ++ 0x1E, 0xE5, 0x1E, 0x05, 0x1D, 0x05, 0x02, 0x70, 0xE0, 0x1A, 0x06, 0x90, 0x13, 0x13, 0xC4, 0xFF, ++ 0x23, 0x60, 0x03, 0x54, 0x80, 0x22, 0x0E, 0x12, 0x22, 0x06, 0x90, 0x1E, 0xF0, 0xFE, 0x54, 0xE0, ++ 0x06, 0x90, 0x15, 0x80, 0x80, 0xF0, 0xE4, 0x2B, 0x34, 0x06, 0x90, 0x0E, 0xF0, 0xA3, 0xF0, 0xE4, ++ 0xE0, 0x07, 0x07, 0x90, 0xD0, 0xF0, 0xEF, 0x54, 0xD0, 0x06, 0xD0, 0x07, 0xD0, 0x04, 0xD0, 0x05, ++ 0xD0, 0x02, 0xD0, 0x03, 0x63, 0x00, 0xD0, 0x01, 0x82, 0xD0, 0x01, 0xA2, 0xA2, 0x63, 0x83, 0xD0, ++ 0xD0, 0xD0, 0xD0, 0x01, 0xD0, 0x83, 0xD0, 0x82, 0x32, 0xE0, 0xD0, 0xF0, 0xE0, 0x1B, 0x06, 0x90, ++ 0xF9, 0x24, 0x1F, 0x54, 0xE9, 0x24, 0x22, 0x60, 0x60, 0x14, 0x39, 0x60, 0x70, 0x1C, 0x24, 0x3E, ++ 0xE5, 0x1D, 0xAE, 0x62, 0xEE, 0x5C, 0x70, 0x1E, 0x06, 0x90, 0x59, 0x70, 0x04, 0x54, 0xE0, 0x1C, ++ 0xF0, 0xB5, 0x01, 0x90, 0x22, 0xF0, 0xE4, 0xA3, 0x1D, 0xE5, 0x1E, 0xAF, 0x24, 0xEF, 0x45, 0x70, ++ 0x90, 0x40, 0x70, 0xC4, 0x54, 0xE0, 0x1D, 0x06, 0x01, 0x90, 0xFF, 0x06, 0xA3, 0xF0, 0xE4, 0xAF, ++ 0x90, 0x22, 0xF0, 0xEF, 0x44, 0xE0, 0x2C, 0x06, 0x79, 0x22, 0xF0, 0x40, 0x74, 0xEA, 0x7D, 0xEA, ++ 0x70, 0x1E, 0x65, 0xEA, 0x65, 0x01, 0x74, 0x04, 0x09, 0x18, 0x60, 0x1D, 0x1E, 0x65, 0xED, 0x0D, ++ 0x01, 0x74, 0x04, 0x70, 0x0B, 0x60, 0x1D, 0x65, 0xE0, 0x1D, 0x06, 0x90, 0x85, 0x82, 0x1E, 0x85, ++ 0x22, 0xF0, 0x83, 0x1D, 0xF0, 0xC0, 0xE0, 0xC0, 0x82, 0xC0, 0x83, 0xC0, 0xD0, 0x75, 0xD0, 0xC0, ++ 0x01, 0xA2, 0x63, 0x00, 0x82, 0xC0, 0x83, 0xC0, 0xC0, 0x01, 0xA2, 0x63, 0xC0, 0x01, 0xC0, 0x00, ++ 0xC0, 0x03, 0xC0, 0x02, 0xC0, 0x05, 0xC0, 0x04, 0x90, 0x07, 0xC0, 0x06, 0x04, 0x74, 0x66, 0x07, ++ 0xBE, 0x01, 0x90, 0xF0, 0x90, 0xF0, 0x04, 0xE0, 0xFF, 0xE0, 0xBD, 0x01, 0x9F, 0xD3, 0xE0, 0xA3, ++ 0xF0, 0xE4, 0x2C, 0x40, 0x60, 0xE5, 0xE9, 0xC2, 0x04, 0x70, 0x5C, 0x65, 0x5B, 0x65, 0x5F, 0xE5, ++ 0x02, 0x60, 0x00, 0x7F, 0x73, 0x8F, 0x01, 0x7F, 0x0C, 0x60, 0x73, 0xE5, 0x85, 0x59, 0x5B, 0x85, ++ 0x5F, 0x85, 0x5A, 0x5C, 0x5C, 0x60, 0x85, 0x5B, 0x5C, 0xA9, 0x5B, 0xAA, 0x07, 0x90, 0xEB, 0x51, ++ 0xE0, 0x30, 0xE0, 0x82, 0xF0, 0x01, 0x74, 0x0A, 0xE0, 0x34, 0x06, 0x90, 0x90, 0xF0, 0x80, 0x44, ++ 0xFF, 0xE0, 0x03, 0x06, 0x3F, 0x54, 0x13, 0x13, 0x90, 0x26, 0xE0, 0x30, 0x75, 0xE0, 0x2B, 0x06, ++ 0x56, 0xF5, 0x00, 0x55, 0xE0, 0x92, 0x07, 0x90, 0x56, 0xF5, 0x56, 0x25, 0xF5, 0x55, 0x35, 0xE4, ++ 0x75, 0x06, 0x60, 0x55, 0x56, 0x75, 0x00, 0x55, 0x2B, 0x06, 0x90, 0xFF, 0x80, 0xF0, 0x56, 0xE5, ++ 0x92, 0x07, 0x90, 0x09, 0x00, 0x55, 0x75, 0xE0, 0x73, 0x11, 0x56, 0xF5, 0x07, 0xD0, 0xE9, 0xD2, ++ 0x05, 0xD0, 0x06, 0xD0, 0x03, 0xD0, 0x04, 0xD0, 0x01, 0xD0, 0x02, 0xD0, 0xA2, 0x63, 0x00, 0xD0, ++ 0xD0, 0x82, 0xD0, 0x01, 0x01, 0xA2, 0x63, 0x83, 0x82, 0xD0, 0xD0, 0xD0, 0xF0, 0xD0, 0x83, 0xD0, ++ 0x90, 0x32, 0xE0, 0xD0, 0xFE, 0xE0, 0x34, 0x06, 0x90, 0xFF, 0xE0, 0xA3, 0x5E, 0xE0, 0x32, 0x06, ++ 0x5F, 0xE0, 0xA3, 0xFE, 0x90, 0x07, 0x60, 0x4E, 0x44, 0xE0, 0x07, 0x07, 0xC0, 0x22, 0xF0, 0x10, ++ 0xC0, 0xF0, 0xC0, 0xE0, 0xC0, 0x82, 0xC0, 0x83, 0x00, 0xD0, 0x75, 0xD0, 0xC0, 0x01, 0xA2, 0x63, ++ 0x63, 0x82, 0xC0, 0x83, 0x00, 0xC0, 0x01, 0xA2, 0x02, 0xC0, 0x01, 0xC0, 0x04, 0xC0, 0x03, 0xC0, ++ 0x06, 0xC0, 0x05, 0xC0, 0x07, 0x90, 0x07, 0xC0, 0xF0, 0x08, 0x74, 0x66, 0x01, 0x90, 0xEA, 0xC2, ++ 0xF0, 0x04, 0xE0, 0xBF, 0x32, 0x94, 0xC3, 0xE0, 0xF8, 0x11, 0x07, 0x40, 0xE4, 0xBF, 0x01, 0x90, ++ 0xD0, 0xEA, 0xD2, 0xF0, 0xD0, 0x06, 0xD0, 0x07, 0xD0, 0x04, 0xD0, 0x05, 0xD0, 0x02, 0xD0, 0x03, ++ 0x63, 0x00, 0xD0, 0x01, 0x82, 0xD0, 0x01, 0xA2, 0xA2, 0x63, 0x83, 0xD0, 0xD0, 0xD0, 0xD0, 0x01, ++ 0xD0, 0x83, 0xD0, 0x82, 0x32, 0xE0, 0xD0, 0xF0, 0x74, 0xC2, 0x01, 0x90, 0x74, 0xA3, 0xF0, 0x01, ++ 0x01, 0x90, 0xF0, 0xE2, 0x54, 0xC4, 0xE0, 0xE0, 0x03, 0x54, 0xFF, 0x0F, 0xA8, 0x64, 0x74, 0xFE, ++ 0x02, 0x80, 0x08, 0x06, 0xFC, 0xD8, 0x13, 0xC3, 0x13, 0x13, 0xEF, 0xF9, 0x03, 0x54, 0x3F, 0x54, ++ 0xA8, 0x64, 0x74, 0xFF, 0x02, 0x80, 0x08, 0x07, 0xFC, 0xD8, 0x13, 0xC3, 0xE6, 0x92, 0x78, 0xFB, ++ 0x40, 0x99, 0xC3, 0x06, 0x78, 0xF6, 0xE4, 0x02, 0xC3, 0x06, 0xE6, 0x8D, 0xE4, 0x29, 0x40, 0x9B, ++ 0xE6, 0x94, 0x78, 0xF6, 0xE6, 0x18, 0xF6, 0xF4, 0x8C, 0x78, 0x10, 0x70, 0xFF, 0xE0, 0x25, 0xE6, ++ 0x14, 0x08, 0xBF, 0xF6, 0x01, 0x76, 0x93, 0x78, 0x8C, 0x78, 0x0E, 0x80, 0xFF, 0x13, 0xC3, 0xE6, ++ 0x04, 0x01, 0xBF, 0xF6, 0xF6, 0x93, 0x78, 0xE4, 0x01, 0x90, 0xFA, 0xE4, 0x07, 0x54, 0xE0, 0xE1, ++ 0xEF, 0x8F, 0x51, 0xFF, 0x94, 0x78, 0x06, 0x60, 0x6C, 0x41, 0xFA, 0xE6, 0xE0, 0xE1, 0x01, 0x90, ++ 0xFF, 0x07, 0x54, 0xC4, 0x60, 0xEF, 0x8F, 0x51, 0xE6, 0x8C, 0x78, 0x06, 0x90, 0x6C, 0x41, 0xFA, ++ 0x54, 0xE0, 0xE0, 0x01, 0x8F, 0x51, 0xFF, 0x07, 0x78, 0x07, 0x60, 0xEF, 0xFA, 0xF4, 0xE6, 0x8C, ++ 0xFC, 0xE4, 0x6C, 0x41, 0xE0, 0xC2, 0x01, 0x90, 0xF5, 0xE0, 0xA3, 0xFE, 0xE0, 0x83, 0x8E, 0x82, ++ 0xE0, 0xA3, 0x57, 0xF5, 0x01, 0x90, 0x58, 0xF5, 0x02, 0x24, 0xE0, 0xC3, 0xC2, 0x01, 0x90, 0xF0, ++ 0xF0, 0x00, 0x34, 0xE0, 0xF8, 0x2C, 0x8E, 0x74, 0x00, 0x94, 0xD3, 0xE6, 0x13, 0xEB, 0x1E, 0x40, ++ 0x2C, 0x8E, 0x74, 0xFF, 0xD3, 0x16, 0xE6, 0xF8, 0x41, 0x02, 0x50, 0x9F, 0xA8, 0x01, 0x74, 0x64, ++ 0x02, 0x80, 0x08, 0x04, 0xFC, 0xD8, 0x33, 0xC3, 0x78, 0x80, 0x02, 0x42, 0xE0, 0xAE, 0x01, 0x90, ++ 0x54, 0x13, 0x13, 0x13, 0x58, 0xAE, 0xFF, 0x1F, 0x5F, 0x07, 0x54, 0xEE, 0x8E, 0x74, 0x08, 0x60, ++ 0x03, 0xA6, 0xF8, 0x2C, 0x58, 0xE5, 0x5E, 0x80, 0xFF, 0x0F, 0x54, 0xC4, 0x60, 0xEF, 0xBB, 0x51, ++ 0x13, 0xC3, 0xE9, 0x1A, 0xE6, 0x92, 0x78, 0xFF, 0x48, 0x40, 0x9F, 0xD3, 0x04, 0xA8, 0x01, 0x74, ++ 0xC3, 0x02, 0x80, 0x08, 0x42, 0xFC, 0xD8, 0x33, 0xAF, 0x39, 0x80, 0x02, 0xEF, 0xBB, 0x51, 0x57, ++ 0xC3, 0xEB, 0x1A, 0x60, 0x8D, 0x78, 0xFF, 0x13, 0x40, 0x9F, 0xD3, 0xE6, 0xA8, 0x01, 0x74, 0x27, ++ 0x02, 0x80, 0x08, 0x04, 0xFC, 0xD8, 0x33, 0xC3, 0x18, 0x80, 0x02, 0x42, 0x54, 0xC4, 0x57, 0xE5, ++ 0xBB, 0x51, 0xFF, 0x0F, 0x74, 0x0D, 0x60, 0xEF, 0x08, 0x04, 0xA8, 0x01, 0x33, 0xC3, 0x02, 0x80, ++ 0x02, 0x42, 0xFC, 0xD8, 0x04, 0x64, 0xEC, 0x0C, 0xA4, 0x21, 0x02, 0x60, 0xE0, 0xAE, 0x01, 0x90, ++ 0x90, 0xF0, 0xC7, 0x54, 0x54, 0xE0, 0x36, 0x06, 0x02, 0x52, 0xFC, 0x0F, 0xE0, 0xFF, 0x04, 0x63, ++ 0x0F, 0x54, 0xE0, 0xA3, 0xEA, 0x02, 0x42, 0x5C, 0x07, 0x90, 0x80, 0x44, 0xE4, 0x22, 0xF0, 0x08, ++ 0x07, 0x07, 0x53, 0xFE, 0x90, 0x09, 0x01, 0xBF, 0x54, 0xE0, 0xAE, 0x01, 0x18, 0x80, 0xFE, 0x07, ++ 0x24, 0x15, 0x60, 0xEF, 0x01, 0x74, 0xFF, 0xFE, 0x80, 0x08, 0x07, 0xA8, 0xD8, 0x33, 0xC3, 0x02, ++ 0x01, 0x90, 0xFF, 0xFC, 0xFE, 0x5F, 0xE0, 0xAD, 0x53, 0x22, 0x06, 0xAF, 0x30, 0xEF, 0x0F, 0x07, ++ 0x94, 0xD3, 0x2B, 0xE3, 0x90, 0x11, 0x40, 0x0C, 0xC4, 0xE0, 0xAE, 0x01, 0x03, 0x54, 0x13, 0x13, ++ 0x03, 0x54, 0xEF, 0xFD, 0x1F, 0x80, 0xFE, 0x5D, 0xFF, 0x07, 0x54, 0xEF, 0x07, 0xA8, 0x01, 0x74, ++ 0xC3, 0x02, 0x80, 0x08, 0xFF, 0xFC, 0xD8, 0x33, 0x80, 0xAD, 0x01, 0x90, 0x07, 0x54, 0xEF, 0x07, ++ 0xAE, 0x01, 0x90, 0xFF, 0xAF, 0xFE, 0x5F, 0xE0, 0xE0, 0xC0, 0x22, 0x06, 0x82, 0xC0, 0x83, 0xC0, ++ 0xD0, 0x75, 0xD0, 0xC0, 0x01, 0xA2, 0x63, 0x00, 0x82, 0xC0, 0x83, 0xC0, 0xC0, 0x01, 0xA2, 0x63, ++ 0x66, 0x07, 0x90, 0x07, 0x0F, 0x54, 0xC4, 0xE0, 0x90, 0x16, 0xE0, 0x30, 0x44, 0xE0, 0x00, 0x06, ++ 0xE8, 0xC2, 0xF0, 0x80, 0x44, 0xEF, 0x20, 0xAF, 0x90, 0x20, 0xF5, 0x01, 0x10, 0x74, 0x66, 0x07, ++ 0x63, 0x07, 0xD0, 0xF0, 0x82, 0xD0, 0x01, 0xA2, 0xA2, 0x63, 0x83, 0xD0, 0xD0, 0xD0, 0xD0, 0x01, ++ 0xD0, 0x83, 0xD0, 0x82, 0xE0, 0xC0, 0x32, 0xE0, 0xA2, 0xC0, 0xF0, 0xC0, 0xC0, 0x02, 0xA2, 0x75, ++ 0x08, 0xD0, 0x75, 0xD0, 0xAA, 0x90, 0x10, 0x85, 0x12, 0x14, 0xA9, 0x13, 0xD0, 0xD0, 0xEB, 0x02, ++ 0xF0, 0xD0, 0xA2, 0xD0, 0xC0, 0x32, 0xE0, 0xD0, 0xC0, 0xF0, 0xC0, 0xE0, 0x02, 0xA2, 0x75, 0xA2, ++ 0xD0, 0x75, 0xD0, 0xC0, 0x90, 0x10, 0x85, 0x08, 0x14, 0xA9, 0x13, 0xAA, 0xD0, 0xEB, 0x02, 0x12, ++ 0xD0, 0xA2, 0xD0, 0xD0, 0x32, 0xE0, 0xD0, 0xF0, 0xF0, 0xC0, 0xE0, 0xC0, 0xA2, 0x75, 0xA2, 0xC0, ++ 0x75, 0xD0, 0xC0, 0x02, 0x10, 0x85, 0x08, 0xD0, 0xB4, 0x10, 0xE5, 0x90, 0x13, 0xAA, 0x06, 0x0B, ++ 0x04, 0x80, 0x14, 0xA9, 0x12, 0xA9, 0x11, 0xAA, 0xD0, 0xEB, 0x02, 0x12, 0xD0, 0xA2, 0xD0, 0xD0, ++ 0x32, 0xE0, 0xD0, 0xF0, 0x00, 0xA9, 0x07, 0xA8, 0x47, 0x19, 0xE7, 0x09, 0xE6, 0x08, 0x09, 0x60, ++ 0x01, 0x70, 0x18, 0x16, 0xD3, 0x22, 0xC3, 0x16, 0x0A, 0x7F, 0xF0, 0x22, 0x24, 0x8E, 0x0D, 0x7E, ++ 0x01, 0x7D, 0x25, 0x8F, 0xFF, 0x2F, 0x20, 0x74, 0x85, 0xFE, 0x3E, 0xE4, 0x24, 0x85, 0x82, 0x25, ++ 0x82, 0x8F, 0xE0, 0x83, 0x0D, 0xF0, 0x83, 0x8E, 0x22, 0xE9, 0x04, 0xBD, 0x29, 0x8D, 0x28, 0x8C, ++ 0x82, 0xF5, 0xFB, 0xE4, 0xEF, 0xC3, 0x83, 0xF5, 0x81, 0x94, 0x80, 0x64, 0x01, 0x7F, 0x02, 0x50, ++ 0x80, 0x64, 0xEF, 0xD3, 0x02, 0x40, 0xBF, 0x94, 0x75, 0xEF, 0x3F, 0x7F, 0xFD, 0xA4, 0x04, 0xF0, ++ 0x20, 0xED, 0xF0, 0xAC, 0x25, 0x0B, 0x09, 0xE7, 0x33, 0xEC, 0xFD, 0xE0, 0xE4, 0xF3, 0x80, 0xFC, ++ 0xAE, 0x05, 0xAF, 0xFA, 0x84, 0x02, 0x12, 0x04, 0x07, 0xAD, 0x06, 0xAC, 0xCE, 0x07, 0x78, 0xED, ++ 0x13, 0xCE, 0x13, 0xC3, 0xAC, 0xFD, 0xF9, 0xD8, 0x94, 0xEC, 0xC3, 0x06, 0x74, 0x24, 0x40, 0x01, ++ 0x74, 0xFF, 0x9A, 0x07, 0xA8, 0x00, 0x7E, 0x01, 0x05, 0x80, 0x08, 0x07, 0x33, 0xCE, 0x33, 0xC3, ++ 0x25, 0xF9, 0xD8, 0xCE, 0xEE, 0x82, 0xF5, 0x82, 0x83, 0xF5, 0x83, 0x35, 0xFC, 0x13, 0xC3, 0xEC, ++ 0x0A, 0xFD, 0x13, 0xED, 0xC3, 0xBA, 0x08, 0xBA, 0xFF, 0x9B, 0x05, 0x74, 0x25, 0xE4, 0xFE, 0xEF, ++ 0xEE, 0x82, 0xF5, 0x82, 0x83, 0xF5, 0x83, 0x35, 0x06, 0x7D, 0x00, 0x7C, 0x12, 0xFE, 0x82, 0xAF, ++ 0x83, 0x8E, 0x84, 0x02, 0xE5, 0xD3, 0x82, 0x8F, 0xE5, 0x29, 0x95, 0x82, 0x40, 0x28, 0x95, 0x83, ++ 0x83, 0xF5, 0xE4, 0x07, 0x0D, 0x80, 0x82, 0xF5, 0x95, 0x29, 0xE5, 0xC3, 0xE5, 0x82, 0xF5, 0x82, ++ 0xF5, 0x83, 0x95, 0x28, 0xF5, 0x83, 0xE5, 0x83, 0x00, 0x83, 0x75, 0x82, 0x06, 0x90, 0x22, 0xFF, ++ 0x04, 0x44, 0xE0, 0x03, 0xE4, 0x0E, 0xA2, 0xF0, 0xFC, 0x01, 0x54, 0x33, 0xE0, 0x54, 0x33, 0xC4, ++ 0xDF, 0x54, 0xE0, 0xFE, 0x06, 0x90, 0xF0, 0x4E, 0x01, 0x44, 0xE0, 0x35, 0xE0, 0x25, 0xEC, 0xF0, ++ 0x90, 0xFF, 0xE0, 0x25, 0x54, 0xE0, 0x34, 0x06, 0x22, 0xF0, 0x4F, 0xFB, 0x20, 0x26, 0x0A, 0x20, ++ 0x0B, 0xD2, 0x05, 0x0B, 0xC2, 0x22, 0x99, 0x8F, 0x05, 0x1C, 0xAE, 0xAC, 0x00, 0x7C, 0xEE, 0x1C, ++ 0x82, 0xF5, 0xAC, 0x24, 0xF5, 0x00, 0x34, 0xEC, 0xE5, 0xF0, 0xEF, 0x83, 0x70, 0x1B, 0x65, 0x1C, ++ 0xD2, 0x0A, 0xD2, 0x02, 0x13, 0x13, 0x22, 0xAC, 0x7C, 0xFD, 0x01, 0x54, 0x8F, 0x3B, 0x8E, 0x00, ++ 0x8D, 0x3D, 0x8C, 0x3C, 0x85, 0x0D, 0xC2, 0x3E, 0x3B, 0x85, 0x82, 0x3C, 0xFF, 0x93, 0xE4, 0x83, ++ 0x18, 0xC1, 0x02, 0x70, 0xB4, 0x1E, 0x0D, 0x20, 0x0D, 0xD2, 0x04, 0x25, 0xB4, 0xEF, 0x0E, 0xC1, ++ 0x0D, 0x7F, 0x08, 0x0A, 0x0A, 0x7F, 0xDC, 0x91, 0x3C, 0x85, 0x0C, 0xC1, 0x83, 0x3B, 0x85, 0x82, ++ 0xC1, 0xFF, 0x93, 0xE4, 0x85, 0x0D, 0xC2, 0x0C, 0x3B, 0x85, 0x82, 0x3C, 0xFB, 0x93, 0xE4, 0x83, ++ 0x4E, 0x60, 0xBC, 0x24, 0x62, 0x60, 0xE0, 0x24, 0x02, 0x60, 0xEC, 0x24, 0x3F, 0x75, 0x09, 0xC1, ++ 0x3F, 0xE5, 0xC3, 0x0C, 0x80, 0x94, 0x80, 0x64, 0x0E, 0xC1, 0x02, 0x50, 0x3D, 0xAE, 0x3E, 0xE5, ++ 0x80, 0x08, 0x3F, 0xA8, 0xE7, 0xA2, 0xCE, 0x06, 0xD8, 0x13, 0xCE, 0x13, 0xF5, 0x0F, 0x54, 0xF8, ++ 0x80, 0x64, 0xD3, 0x45, 0x08, 0x40, 0x89, 0x94, 0x37, 0x24, 0x45, 0xE5, 0x06, 0x80, 0x45, 0xF5, ++ 0x45, 0x25, 0x30, 0x74, 0x45, 0xAF, 0x45, 0xF5, 0xFC, 0x74, 0xDC, 0x91, 0x3F, 0xF5, 0x3F, 0x25, ++ 0xE5, 0xC3, 0xBF, 0x80, 0x94, 0x80, 0x64, 0x3D, 0xC3, 0x0F, 0x50, 0x80, 0xF5, 0x3E, 0x95, 0xE4, ++ 0x3D, 0x95, 0xE4, 0x3E, 0x2D, 0x7F, 0x3D, 0xF5, 0x3E, 0xE5, 0xDC, 0x91, 0x04, 0x70, 0x3D, 0x45, ++ 0xDC, 0x91, 0x30, 0x7F, 0xE5, 0x3F, 0xF5, 0xE4, 0x60, 0x3D, 0x45, 0x3E, 0xAF, 0x3D, 0xAE, 0x2B, ++ 0x7D, 0x00, 0x7C, 0x3E, 0x96, 0x02, 0x12, 0x0A, 0xFF, 0x30, 0x24, 0xED, 0x3F, 0x05, 0x3F, 0xAE, ++ 0xF8, 0x2E, 0x40, 0x74, 0xAE, 0xC6, 0xEF, 0xC6, 0x7C, 0x3E, 0xAF, 0x3D, 0x12, 0x0A, 0x7D, 0x00, ++ 0x3D, 0x8E, 0x96, 0x02, 0xCF, 0x80, 0x3E, 0x8F, 0x12, 0x60, 0x3F, 0xE5, 0x40, 0x74, 0x3F, 0x15, ++ 0xE6, 0xF8, 0x3F, 0x25, 0x80, 0xDC, 0x91, 0xFF, 0xCF, 0xEB, 0xCF, 0xEF, 0x3C, 0x05, 0xDC, 0x91, ++ 0x02, 0x70, 0x3C, 0xE5, 0x17, 0xA1, 0x3B, 0x05, 0x7F, 0x20, 0x7E, 0x22, 0xFC, 0xFD, 0xE4, 0x30, ++ 0x06, 0x90, 0x0D, 0xA1, 0x1F, 0x54, 0xE0, 0x1B, 0x6E, 0x60, 0xF9, 0x24, 0x02, 0x70, 0xE9, 0x24, ++ 0x70, 0x14, 0xBE, 0xC1, 0x24, 0xC6, 0xC1, 0x02, 0xC1, 0x02, 0x60, 0x1C, 0x14, 0x1E, 0xE5, 0xE6, ++ 0xED, 0x24, 0x11, 0x60, 0xFE, 0x24, 0x34, 0x60, 0x16, 0x24, 0x35, 0x60, 0x01, 0x90, 0x46, 0x70, ++ 0x90, 0x58, 0x80, 0xB5, 0xFF, 0xE0, 0xB9, 0x01, 0x06, 0x90, 0xE0, 0xA3, 0xA3, 0xF0, 0xCF, 0x1C, ++ 0x06, 0x90, 0xF0, 0xEF, 0x0C, 0x54, 0xE0, 0x1C, 0xFF, 0xF4, 0xE4, 0xFE, 0x90, 0xFE, 0xF4, 0xEE, ++ 0x5E, 0xE0, 0xB9, 0x01, 0x5F, 0xE0, 0xA3, 0xF0, 0x01, 0x90, 0x22, 0xF0, 0x90, 0x2C, 0x80, 0xB3, ++ 0xFF, 0xE0, 0xB1, 0x01, 0x06, 0x90, 0xE0, 0xA3, 0xA3, 0xF0, 0xCF, 0x1C, 0x90, 0xE4, 0xF0, 0xEF, ++ 0x56, 0x80, 0xB1, 0x01, 0x1C, 0x06, 0x90, 0xE4, 0x1E, 0xE5, 0x50, 0x80, 0x08, 0x60, 0xC3, 0x24, ++ 0x90, 0x15, 0x70, 0x04, 0x03, 0x80, 0xAF, 0x01, 0xE0, 0xB7, 0x01, 0x90, 0x90, 0xE0, 0xA3, 0xFF, ++ 0xF0, 0xCF, 0x1C, 0x06, 0x22, 0xF0, 0xEF, 0xA3, 0x1C, 0x06, 0x90, 0xE4, 0x06, 0x90, 0x2C, 0x80, ++ 0x40, 0x44, 0xE0, 0x2C, 0x90, 0xE4, 0x22, 0xF0, 0x85, 0xF0, 0x1C, 0x06, 0x1D, 0x85, 0x82, 0x1E, ++ 0x06, 0x90, 0xE0, 0x83, 0xEB, 0x74, 0xF0, 0x1D, 0x74, 0x12, 0x1E, 0xB5, 0x0D, 0x1D, 0xB5, 0x01, ++ 0xEA, 0x01, 0x90, 0xE4, 0x90, 0xE4, 0x04, 0x80, 0xA3, 0xF0, 0x1C, 0x06, 0x01, 0x12, 0x22, 0xF0, ++ 0x57, 0x46, 0x82, 0x01, 0x48, 0x50, 0x47, 0x5F, 0x52, 0x56, 0x5F, 0x59, 0x32, 0x41, 0x5F, 0x39, ++ 0x50, 0x00, 0x0A, 0x32, 0x3A, 0x4C, 0x4F, 0x54, 0x0A, 0x44, 0x25, 0x20, 0x7D, 0x93, 0xAA, 0x00, ++ 0x22, 0x39, 0x4F, 0x66, 0x69, 0x6E, 0x49, 0x0B, 0x09, 0x00, 0x0A, 0x74, 0x00, 0x0A, 0x30, 0x44, ++ 0x0A, 0x31, 0x44, 0x09, 0x32, 0x44, 0x09, 0x00, 0x45, 0x09, 0x00, 0x0A, 0x70, 0x65, 0x63, 0x78, ++ 0x6E, 0x6F, 0x69, 0x74, 0x45, 0x09, 0x00, 0x0A, 0x0A, 0x74, 0x69, 0x78, 0x8C, 0xC2, 0x01, 0x00, ++ 0xE4, 0x01, 0x89, 0x43, 0x8C, 0xF5, 0x8A, 0xF5, 0x90, 0x22, 0x8C, 0xD2, 0x54, 0xE0, 0x47, 0x07, ++ 0x54, 0xEF, 0xF0, 0xFE, 0x07, 0x90, 0xFF, 0x01, 0xFE, 0x54, 0xE0, 0x48, 0x90, 0xE4, 0xF0, 0x4F, ++ 0x90, 0xF0, 0x4A, 0x07, 0xED, 0xF0, 0x49, 0x07, 0xF0, 0x4C, 0x07, 0x90, 0x4B, 0x07, 0x90, 0xEC, ++ 0xF5, 0xE4, 0x22, 0xF0, 0xF5, 0x5C, 0xF5, 0x5B, 0xF5, 0x62, 0xF5, 0x61, 0x90, 0x5E, 0xF5, 0x5D, ++ 0x90, 0xF0, 0xAC, 0x01, 0x75, 0xF0, 0xA0, 0x00, 0x08, 0xD2, 0x01, 0x73, 0x75, 0x02, 0x5F, 0x75, ++ 0xF7, 0x11, 0x1A, 0x60, 0x20, 0x7E, 0xED, 0x11, 0x0E, 0x12, 0x02, 0x7F, 0x11, 0x2E, 0x31, 0x1D, ++ 0x7C, 0xA8, 0x7D, 0x4E, 0x11, 0xFF, 0xE4, 0x61, 0x7C, 0xA8, 0x7D, 0x5B, 0x31, 0xFF, 0xE4, 0x61, ++ 0x11, 0xFF, 0xE4, 0x05, 0x11, 0x01, 0x7F, 0xD6, 0x12, 0x66, 0x31, 0xD6, 0xFF, 0xE4, 0x29, 0x02, ++ 0x02, 0x65, 0x02, 0x12, 0x07, 0xAD, 0xB6, 0x01, 0x90, 0x07, 0x70, 0xED, 0x44, 0xE0, 0x47, 0x07, ++ 0x01, 0xBD, 0xF0, 0x01, 0x47, 0x07, 0x90, 0x07, 0xF0, 0x02, 0x44, 0xE0, 0x1B, 0xF5, 0xE4, 0x22, ++ 0x0B, 0xC2, 0x1C, 0xF5, 0xC2, 0x22, 0x0A, 0xC2, 0xC2, 0x98, 0x75, 0x8E, 0x75, 0x20, 0x89, 0x43, ++ 0x8E, 0xD2, 0xDE, 0x8D, 0x47, 0x07, 0x90, 0x22, 0xF0, 0xFD, 0x54, 0xE0, 0x25, 0x01, 0x54, 0xEF, ++ 0x07, 0x90, 0xFF, 0xE0, 0xFD, 0x54, 0xE0, 0x48, 0x90, 0xE4, 0xF0, 0x4F, 0x90, 0xF0, 0x4E, 0x07, ++ 0xED, 0xF0, 0x4D, 0x07, 0xF0, 0x50, 0x07, 0x90, 0x4F, 0x07, 0x90, 0xEC, 0x0D, 0x90, 0x22, 0xF0, ++ 0x54, 0xC4, 0xE0, 0xAB, 0x0C, 0xC2, 0xFF, 0x0F, 0xD2, 0x05, 0xE3, 0x30, 0x0F, 0x07, 0x63, 0x0C, ++ 0x1D, 0x20, 0x90, 0xEF, 0x00, 0x7C, 0xFD, 0x93, 0xC3, 0x07, 0x0C, 0x30, 0xE4, 0xFD, 0x9D, 0xE4, ++ 0x0D, 0x90, 0xFC, 0x9C, 0x13, 0xC3, 0xE0, 0xAB, 0x7C, 0x04, 0xE0, 0x20, 0x7E, 0xFF, 0x7D, 0x7F, ++ 0x02, 0x13, 0x7F, 0x20, 0x07, 0x90, 0x0D, 0x0D, 0x01, 0x44, 0xE0, 0x07, 0xEF, 0x54, 0xE0, 0xF0, ++ 0x00, 0x07, 0x90, 0xF0, 0xF0, 0x04, 0x44, 0xE0, 0xF0, 0xFB, 0x54, 0xE0, 0x03, 0x07, 0x90, 0xE4, ++ 0x04, 0x07, 0x90, 0xF0, 0x05, 0x07, 0x90, 0xF0, 0x07, 0x90, 0xF0, 0x04, 0xF0, 0xFF, 0x74, 0x06, ++ 0x74, 0x01, 0x07, 0x90, 0x54, 0xE0, 0xF0, 0x04, 0x02, 0x7F, 0xF0, 0xF7, 0x90, 0x24, 0x02, 0x12, ++ 0x01, 0x74, 0x00, 0x07, 0x28, 0x7E, 0x22, 0xF0, 0x03, 0x12, 0x9A, 0x7F, 0x7F, 0x24, 0x7E, 0xDF, ++ 0xDF, 0x03, 0x12, 0xE4, 0x6B, 0x7F, 0x2D, 0x7E, 0x7E, 0xDF, 0x03, 0x12, 0x12, 0xE7, 0x7F, 0x20, ++ 0x30, 0x7E, 0xDF, 0x03, 0x03, 0x12, 0x48, 0x7F, 0x7F, 0x2A, 0x7E, 0xDF, 0xDF, 0x03, 0x12, 0xFE, ++ 0xC6, 0x7F, 0x27, 0x7E, 0x7E, 0xDF, 0x03, 0x12, 0x12, 0xA8, 0x7F, 0x2D, 0x32, 0x7E, 0xDF, 0x03, ++ 0x03, 0x12, 0x7F, 0x7F, 0x7F, 0x2F, 0x7E, 0xDF, 0xDF, 0x03, 0x12, 0xAC, 0x33, 0x7F, 0x2A, 0x7E, ++ 0x7E, 0xDF, 0x03, 0x12, 0x12, 0x00, 0x7F, 0x20, 0x23, 0x7E, 0xDF, 0x03, 0x03, 0x12, 0xE0, 0x7F, ++ 0x7F, 0x20, 0x7E, 0xDF, 0xDF, 0x03, 0x02, 0x17, 0x0F, 0x60, 0x73, 0xE5, 0x25, 0x7F, 0x20, 0x7E, ++ 0x75, 0x1D, 0x0E, 0x12, 0x5E, 0x75, 0x22, 0x5D, 0x90, 0x08, 0xD2, 0x4C, 0x93, 0xE4, 0x4D, 0x20, ++ 0xAC, 0x01, 0x90, 0xFF, 0x06, 0x07, 0xB5, 0xE0, 0x75, 0x22, 0x61, 0x75, 0x62, 0xE5, 0x79, 0x62, ++ 0x04, 0x70, 0x5E, 0x65, 0x5D, 0x65, 0x61, 0xE5, 0x5D, 0x85, 0x08, 0x60, 0x62, 0x5E, 0x85, 0x61, ++ 0x61, 0xAA, 0x08, 0xD2, 0x02, 0x12, 0x62, 0xA9, 0x22, 0x08, 0xC2, 0xEB, 0x2B, 0x7F, 0x20, 0x7E, ++ 0xE4, 0x1D, 0x0E, 0x12, 0x5D, 0x75, 0x20, 0xF5, 0x5D, 0x5E, 0x75, 0x22, 0x7F, 0x20, 0x7E, 0x22, ++ 0x1D, 0x0E, 0x12, 0x30, 0x75, 0x22, 0x5D, 0x75, 0x7E, 0x22, 0x6B, 0x5E, 0x12, 0x35, 0x7F, 0x20, ++ 0x5D, 0x75, 0x1D, 0x0E, 0x8C, 0x5E, 0x75, 0x22, 0x01, 0x90, 0xE4, 0x22, 0x20, 0x7E, 0xF0, 0xAC, ++ 0x0E, 0x12, 0x3A, 0x7F, 0x22, 0x5D, 0x75, 0x1D, 0x22, 0x4C, 0x5E, 0x75, 0x46, 0x7F, 0x20, 0x7E, ++ 0x75, 0x1D, 0x0E, 0x12, 0x60, 0x75, 0x01, 0x5F, 0x00, 0x22, 0x22, 0xC5, 0x00, 0x00, 0x00, 0x00, ++ 0xB9, 0xC1, 0xBF, 0x61, 0xC0, 0x00, 0xEE, 0x00, 0x1F, 0x00, 0xDE, 0x00, 0x49, 0x79, 0x40, 0x90, ++ 0x09, 0xA4, 0x65, 0xD5, 0x00, 0x00, 0xE1, 0x01, 0x01, 0x20, 0x04, 0x00, 0x00, 0x03, 0x01, 0x20, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x80, ++ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x0F, 0x00, 0x00, 0xAA, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0B, 0x04, 0xFF, 0xFF, 0x3F, 0x00, ++ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x40, 0x00, 0x48, 0xFF, 0xFF, 0x00, 0x00, 0xFF, 0xFF, ++ 0x00, 0x00, 0xFF, 0xFF, 0xE0, 0x3F, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, ++ 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xF0, 0xE0, 0x38, 0x00, 0x00, 0xFF, 0x7F, 0xC0, 0x03, 0xFF, 0xFF, ++ 0xF0, 0xF0, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0xD0, 0xFF, 0xFF, 0xFF, 0xFF, 0x20, 0x7C, 0x23, 0x8F, ++ 0x23, 0xAB, 0x0C, 0x7D, 0x06, 0x7E, 0x00, 0x7F, 0x0E, 0xC2, 0xBD, 0x51, 0x02, 0x64, 0x23, 0xE5, ++ 0xFD, 0xFB, 0x20, 0x70, 0x7E, 0x40, 0x7F, 0xFC, 0x7C, 0xBD, 0x51, 0x06, 0x7B, 0x4C, 0x7D, 0x20, ++ 0x7E, 0x80, 0x7F, 0x02, 0x7B, 0xBD, 0x51, 0x06, 0xFC, 0xFD, 0xE4, 0x01, 0x06, 0x7E, 0xC0, 0x7F, ++ 0x23, 0xE5, 0xBD, 0x51, 0x11, 0x60, 0x02, 0x64, 0x03, 0x64, 0x23, 0xE5, 0x6E, 0x21, 0x02, 0x60, ++ 0xE0, 0x28, 0x06, 0x90, 0x21, 0x02, 0xE0, 0x30, 0x01, 0x90, 0xE4, 0x6E, 0xF0, 0xA3, 0xF0, 0xB5, ++ 0xF0, 0xB9, 0x01, 0x90, 0x01, 0x90, 0xF0, 0xA3, 0x74, 0xA3, 0xF0, 0xB3, 0x90, 0xE4, 0xF0, 0x06, ++ 0xA3, 0xF0, 0xB1, 0x01, 0xAF, 0x01, 0x90, 0xF0, 0x90, 0xF0, 0xA3, 0xF0, 0xA3, 0xF0, 0xB7, 0x01, ++ 0xEA, 0x01, 0x90, 0xF0, 0x90, 0xF0, 0xA3, 0xF0, 0x90, 0xF0, 0xEC, 0x01, 0x20, 0x74, 0xED, 0x01, ++ 0xEE, 0x01, 0x90, 0xF0, 0x90, 0xF0, 0x80, 0x74, 0x11, 0x74, 0xF2, 0x01, 0xF3, 0x01, 0x90, 0xF0, ++ 0x90, 0xF0, 0x40, 0x74, 0x80, 0x74, 0xF4, 0x01, 0xF5, 0x01, 0x90, 0xF0, 0x90, 0xF0, 0xF0, 0x74, ++ 0xE0, 0x74, 0xF6, 0x01, 0xF7, 0x01, 0x90, 0xF0, 0x90, 0xF0, 0x80, 0x74, 0x17, 0x74, 0xF8, 0x01, ++ 0xF9, 0x01, 0x90, 0xF0, 0x90, 0xF0, 0xC0, 0x74, 0x80, 0x74, 0xFA, 0x01, 0xFB, 0x01, 0x90, 0xF0, ++ 0x90, 0xF0, 0x28, 0x74, 0x40, 0x74, 0xFC, 0x01, 0xFD, 0x01, 0x90, 0xF0, 0x90, 0xF0, 0x95, 0x74, ++ 0xEB, 0x74, 0xFE, 0x01, 0x01, 0x90, 0xE4, 0xF0, 0x1D, 0xF5, 0xF0, 0xFF, 0x06, 0x90, 0x1E, 0xF5, ++ 0xE0, 0x54, 0xE0, 0x08, 0x54, 0xE0, 0xA3, 0xF0, 0x07, 0x90, 0xF0, 0x1F, 0x13, 0xFF, 0xE0, 0x0D, ++ 0x30, 0x3F, 0x54, 0x13, 0x06, 0x90, 0x3C, 0xE0, 0xA3, 0xFC, 0xE0, 0x08, 0x00, 0x7A, 0xFD, 0xE0, ++ 0x04, 0xAE, 0x02, 0x7B, 0xC3, 0xCE, 0x05, 0x78, 0xD8, 0x13, 0xCE, 0x13, 0x54, 0xEC, 0xFF, 0xF9, ++ 0x54, 0xED, 0xFC, 0xE0, 0x4B, 0xEF, 0xFD, 0x1F, 0x05, 0x78, 0x00, 0x7E, 0x33, 0xCE, 0x33, 0xC3, ++ 0xFF, 0xF9, 0xD8, 0xCE, 0xED, 0xFE, 0x4E, 0xEC, 0x06, 0x90, 0xFF, 0x4F, 0xA3, 0xF0, 0xEE, 0x08, ++ 0x07, 0x90, 0xF0, 0xEF, 0x13, 0xFF, 0xE0, 0x0D, 0x1F, 0x54, 0x13, 0x13, 0x90, 0x3C, 0xE0, 0x30, ++ 0xFC, 0xE0, 0x08, 0x06, 0x7A, 0xFD, 0xE0, 0xA3, 0xAE, 0x01, 0x7B, 0x00, 0xCE, 0x05, 0x78, 0x04, ++ 0x13, 0xCE, 0x13, 0xC3, 0xEC, 0xFF, 0xF9, 0xD8, 0xED, 0xFC, 0xE0, 0x54, 0xEF, 0xFD, 0x1F, 0x54, ++ 0x78, 0x00, 0x7E, 0x4B, 0xCE, 0x33, 0xC3, 0x05, 0xF9, 0xD8, 0xCE, 0x33, 0xFE, 0x4E, 0xEC, 0xFF, ++ 0x90, 0xFF, 0x4F, 0xED, 0xF0, 0xEE, 0x08, 0x06, 0x90, 0xF0, 0xEF, 0xA3, 0xFF, 0xE0, 0x0D, 0x07, ++ 0x30, 0x0F, 0x54, 0xC4, 0x06, 0x90, 0x3C, 0xE0, 0xA3, 0xFC, 0xE0, 0x08, 0x00, 0x7A, 0xFD, 0xE0, ++ 0x04, 0xAE, 0x08, 0x7B, 0xC3, 0xCE, 0x05, 0x78, 0xD8, 0x13, 0xCE, 0x13, 0x54, 0xEC, 0xFF, 0xF9, ++ 0x54, 0xED, 0xFC, 0xE0, 0x4B, 0xEF, 0xFD, 0x1F, 0x05, 0x78, 0x00, 0x7E, 0x33, 0xCE, 0x33, 0xC3, ++ 0xFF, 0xF9, 0xD8, 0xCE, 0xED, 0xFE, 0x4E, 0xEC, 0x06, 0x90, 0xFF, 0x4F, 0xA3, 0xF0, 0xEE, 0x08, ++ 0x07, 0x90, 0xF0, 0xEF, 0xC4, 0xFF, 0xE0, 0x0D, 0x30, 0x07, 0x54, 0x13, 0x06, 0x90, 0x3C, 0xE0, ++ 0xA3, 0xFC, 0xE0, 0x08, 0x00, 0x7A, 0xFD, 0xE0, 0x04, 0xAE, 0x04, 0x7B, 0xC3, 0xCE, 0x05, 0x78, ++ 0xD8, 0x13, 0xCE, 0x13, 0x54, 0xEC, 0xFF, 0xF9, 0x54, 0xED, 0xFC, 0xE0, 0x4B, 0xEF, 0xFD, 0x1F, ++ 0x05, 0x78, 0x00, 0x7E, 0x33, 0xCE, 0x33, 0xC3, 0xFF, 0xF9, 0xD8, 0xCE, 0xED, 0xFE, 0x4E, 0xEC, ++ 0x06, 0x90, 0xFF, 0x4F, 0xA3, 0xF0, 0xEE, 0x08, 0x07, 0x90, 0xF0, 0xEF, 0x02, 0x54, 0xE0, 0x0D, ++ 0x90, 0xFF, 0x13, 0xC3, 0x54, 0xE0, 0x12, 0x06, 0x90, 0xF0, 0x4F, 0xFE, 0x54, 0xE0, 0x0D, 0x07, ++ 0xFF, 0xE0, 0x25, 0x01, 0xE0, 0x12, 0x06, 0x90, 0xF0, 0x4F, 0xFD, 0x54, 0x8F, 0x24, 0x8E, 0x22, ++ 0x8D, 0x26, 0x8C, 0x25, 0x28, 0x06, 0x90, 0x27, 0x0C, 0x92, 0x13, 0xE0, 0xE0, 0x2C, 0x06, 0x90, ++ 0x13, 0x13, 0x13, 0xC4, 0x92, 0x13, 0x01, 0x54, 0xEB, 0xFF, 0xE4, 0x0D, 0x24, 0x0B, 0x60, 0x14, ++ 0x24, 0x0F, 0x60, 0xFE, 0xE4, 0x69, 0x70, 0x03, 0xFF, 0x74, 0x02, 0x80, 0x29, 0xF5, 0x28, 0xF5, ++ 0x0C, 0x30, 0x79, 0x80, 0x94, 0xD3, 0xEF, 0x5B, 0xEF, 0x55, 0x40, 0x0F, 0x4C, 0x24, 0xE0, 0x25, ++ 0x34, 0xE4, 0x82, 0xF5, 0xE4, 0x83, 0xF5, 0x20, 0x74, 0x2C, 0xF5, 0x93, 0x2D, 0xF5, 0x93, 0x01, ++ 0x24, 0xFD, 0x27, 0xE5, 0xE5, 0x27, 0xF5, 0x02, 0x00, 0x34, 0xFC, 0x26, 0x82, 0x8D, 0x26, 0xF5, ++ 0x93, 0xE4, 0x83, 0x8C, 0x2A, 0xF5, 0x2C, 0x55, 0x55, 0x93, 0x01, 0x74, 0x85, 0x2B, 0xF5, 0x2D, ++ 0x24, 0x85, 0x82, 0x25, 0xF4, 0x2D, 0xE5, 0x83, 0xF4, 0x2C, 0xE5, 0xFD, 0xFC, 0x5C, 0xE0, 0xFC, ++ 0xFD, 0x5D, 0xE0, 0xA3, 0xF5, 0x4C, 0x2A, 0xE5, 0x4D, 0x2B, 0xE5, 0x28, 0x1B, 0x80, 0x29, 0xF5, ++ 0x24, 0xFD, 0x27, 0xE5, 0xE5, 0x27, 0xF5, 0x02, 0x00, 0x34, 0xFC, 0x26, 0x82, 0x8D, 0x26, 0xF5, ++ 0x93, 0xE4, 0x83, 0x8C, 0x01, 0x74, 0x28, 0xF5, 0xE5, 0x29, 0xF5, 0x93, 0x02, 0x24, 0xFD, 0x25, ++ 0x24, 0xE5, 0x25, 0xF5, 0xF5, 0x00, 0x34, 0xFC, 0x8C, 0x82, 0x8D, 0x24, 0xF0, 0x28, 0xE5, 0x83, ++ 0xF0, 0x29, 0xE5, 0xA3, 0x20, 0x64, 0xEF, 0x0F, 0xDB, 0x41, 0x02, 0x60, 0xE4, 0x07, 0x0C, 0x30, ++ 0xF0, 0x38, 0x06, 0x90, 0x64, 0xEB, 0xF0, 0xA3, 0xA2, 0x23, 0x70, 0x03, 0x01, 0x54, 0x33, 0x0C, ++ 0x28, 0x06, 0x90, 0xFF, 0x4F, 0xFE, 0x54, 0xE0, 0xE4, 0x0D, 0xA2, 0xF0, 0xC4, 0x01, 0x54, 0x33, ++ 0x54, 0x33, 0x33, 0x33, 0x06, 0x90, 0xFF, 0x80, 0x7F, 0x54, 0xE0, 0x2C, 0xE4, 0x22, 0xF0, 0x4F, ++ 0x07, 0x90, 0x22, 0xF5, 0xF0, 0x61, 0x74, 0x4B, 0x74, 0x4C, 0x07, 0x90, 0x0A, 0x7F, 0xF0, 0xA8, ++ 0x12, 0x32, 0x04, 0x12, 0x06, 0x90, 0xF7, 0x02, 0xC4, 0xFF, 0xE0, 0x00, 0x54, 0x13, 0x13, 0x13, ++ 0x30, 0xE0, 0x30, 0x01, 0x03, 0x7F, 0xE8, 0xC2, 0xF5, 0xE4, 0x8C, 0x11, 0xAD, 0x01, 0x90, 0x20, ++ 0x90, 0xF0, 0xA3, 0xF0, 0xE5, 0xF0, 0xA1, 0x00, 0x90, 0x08, 0x60, 0x22, 0x01, 0x74, 0x04, 0x20, ++ 0x90, 0x22, 0xF5, 0x93, 0x54, 0xE0, 0x00, 0x06, 0xE0, 0xA3, 0xF0, 0x7F, 0x80, 0x06, 0x90, 0xF0, ++ 0xF0, 0x7F, 0x54, 0xE0, 0x74, 0x00, 0x07, 0x90, 0xE8, 0xD2, 0xF0, 0x01, 0x07, 0x90, 0x97, 0x91, ++ 0x20, 0x44, 0xE0, 0x61, 0x40, 0x44, 0xE0, 0xF0, 0x10, 0x44, 0xE0, 0xF0, 0xDF, 0x54, 0xE0, 0xF0, ++ 0xBF, 0x54, 0xE0, 0xF0, 0xEF, 0x54, 0xE0, 0xF0, 0x00, 0x0D, 0x90, 0xF0, 0x7F, 0xF0, 0x20, 0x74, ++ 0x12, 0x0D, 0x7E, 0x00, 0x0D, 0x90, 0xCE, 0x0B, 0xF0, 0xDF, 0x74, 0x01, 0x0D, 0x7E, 0x01, 0x7F, ++ 0x90, 0xCE, 0x0B, 0x12, 0x36, 0x74, 0x0C, 0x0D, 0x7E, 0x0C, 0x7F, 0xF0, 0xCE, 0x0B, 0x12, 0x0D, ++ 0x74, 0x8B, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x4C, 0xF0, 0xA9, 0x74, 0x88, 0xE0, 0x2A, 0x06, 0x90, ++ 0x90, 0xFF, 0x07, 0x54, 0x54, 0xE0, 0x93, 0x07, 0x90, 0xF0, 0x4F, 0xF8, 0x44, 0xE0, 0xDB, 0x09, ++ 0x54, 0xE0, 0xF0, 0x80, 0x09, 0x90, 0xF0, 0xBF, 0xF0, 0x7F, 0x74, 0xE1, 0x74, 0x06, 0x08, 0x90, ++ 0x0C, 0xC2, 0xF0, 0x6A, 0x90, 0xD9, 0x01, 0x02, 0x13, 0xE0, 0xAB, 0x0D, 0x30, 0x3F, 0x54, 0x13, ++ 0x06, 0x90, 0x56, 0xE0, 0x13, 0xC3, 0xE0, 0x27, 0xE0, 0x25, 0xE0, 0x30, 0xFF, 0x01, 0x54, 0xC4, ++ 0x9F, 0x01, 0x74, 0xC3, 0x0C, 0x92, 0xFF, 0x24, 0x2D, 0xD1, 0x50, 0x7F, 0xEF, 0xA4, 0x00, 0x90, ++ 0x27, 0x06, 0x90, 0xF0, 0x54, 0x13, 0xC4, 0xE0, 0x0C, 0x92, 0x13, 0x07, 0x7C, 0x80, 0x50, 0x7F, ++ 0xE0, 0x27, 0x06, 0x90, 0xFF, 0x01, 0x54, 0xC4, 0x9F, 0x01, 0x74, 0xC3, 0x0C, 0x92, 0xFF, 0x24, ++ 0x2D, 0xD1, 0x6C, 0x7F, 0xEF, 0xA4, 0x00, 0x90, 0x27, 0x06, 0x90, 0xF0, 0x54, 0x13, 0xC4, 0xE0, ++ 0x0C, 0x92, 0x13, 0x07, 0x54, 0x80, 0x6C, 0x7F, 0xE0, 0x27, 0x06, 0x90, 0xE0, 0x30, 0x13, 0xC3, ++ 0x54, 0xC4, 0xE0, 0x25, 0x74, 0xC3, 0xFF, 0x01, 0xFF, 0x24, 0x9F, 0x01, 0x50, 0x7F, 0x0C, 0x92, ++ 0x00, 0x90, 0x2D, 0xD1, 0x90, 0xF0, 0xEF, 0xA4, 0xC4, 0xE0, 0x27, 0x06, 0x13, 0x07, 0x54, 0x13, ++ 0x50, 0x7F, 0x0C, 0x92, 0x06, 0x90, 0x26, 0x80, 0x54, 0xC4, 0xE0, 0x27, 0x74, 0xC3, 0xFF, 0x01, ++ 0xFF, 0x24, 0x9F, 0x01, 0x68, 0x7F, 0x0C, 0x92, 0x00, 0x90, 0x2D, 0xD1, 0x90, 0xF0, 0xEF, 0xA4, ++ 0xC4, 0xE0, 0x27, 0x06, 0x13, 0x07, 0x54, 0x13, 0x68, 0x7F, 0x0C, 0x92, 0x00, 0x90, 0x2D, 0xD1, ++ 0x90, 0xF0, 0xEF, 0xA5, 0x90, 0xE0, 0xA4, 0x00, 0x90, 0xF0, 0xA2, 0x00, 0x90, 0xE0, 0xA5, 0x00, ++ 0x90, 0xF0, 0xA3, 0x00, 0x13, 0xE0, 0xAB, 0x0D, 0x90, 0x3F, 0x54, 0x13, 0xE0, 0x30, 0x27, 0x06, ++ 0x54, 0xC4, 0xE0, 0x25, 0x74, 0xC3, 0xFF, 0x01, 0xFF, 0x24, 0x9F, 0x01, 0x6D, 0x7F, 0x0C, 0x92, ++ 0x00, 0x90, 0x2D, 0xD1, 0x90, 0xF0, 0xEF, 0xA6, 0xC4, 0xE0, 0x27, 0x06, 0x13, 0x07, 0x54, 0x13, ++ 0x6D, 0x7F, 0x0C, 0x92, 0xC4, 0xE0, 0x23, 0x80, 0xC3, 0xFF, 0x01, 0x54, 0x24, 0x9F, 0x01, 0x74, ++ 0x7F, 0x0C, 0x92, 0xFF, 0x90, 0x2D, 0xD1, 0x6B, 0xF0, 0xEF, 0xA6, 0x00, 0xE0, 0x27, 0x06, 0x90, ++ 0x07, 0x54, 0x13, 0xC4, 0x7F, 0x0C, 0x92, 0x13, 0x90, 0x2D, 0xD1, 0x6B, 0xF0, 0xEF, 0xA7, 0x00, ++ 0xE0, 0x27, 0x06, 0x90, 0x90, 0x20, 0xD1, 0xC4, 0xF0, 0xEF, 0xA8, 0x00, 0xE0, 0x27, 0x06, 0x90, ++ 0x07, 0x54, 0x13, 0xC4, 0x90, 0x29, 0xD1, 0x13, 0xF0, 0xEF, 0xA9, 0x00, 0xE0, 0x27, 0x06, 0x90, ++ 0xD1, 0x13, 0x13, 0xC4, 0xAA, 0x00, 0x90, 0x20, 0x06, 0x90, 0xF0, 0xEF, 0x13, 0xC4, 0xE0, 0x27, ++ 0x01, 0x54, 0x13, 0x13, 0x90, 0x29, 0xD1, 0x13, 0xF0, 0xEF, 0xAB, 0x00, 0xE0, 0xA5, 0x00, 0x90, ++ 0x90, 0xF0, 0x04, 0xF4, 0xF4, 0xE0, 0xA3, 0x00, 0x00, 0x90, 0xF0, 0x04, 0x04, 0xF4, 0xE0, 0xA7, ++ 0xA9, 0x00, 0x90, 0xF0, 0xF0, 0x04, 0xF4, 0xE0, 0xE0, 0xAB, 0x00, 0x90, 0x22, 0xF0, 0x04, 0xF4, ++ 0xC3, 0xFF, 0x01, 0x54, 0x24, 0x9F, 0x01, 0x74, 0x7F, 0x0C, 0x92, 0xFF, 0x26, 0x06, 0x90, 0x70, ++ 0xFE, 0x0F, 0x54, 0xE0, 0x94, 0x80, 0x64, 0xD3, 0x74, 0x04, 0x40, 0x87, 0xEE, 0xFE, 0x2E, 0xF0, ++ 0x0C, 0x30, 0xFF, 0x2F, 0xFF, 0x04, 0xF4, 0x03, 0xE0, 0x26, 0x06, 0x90, 0x30, 0x0F, 0x54, 0xC4, ++ 0x00, 0x7F, 0x03, 0xE0, 0x90, 0xE4, 0x22, 0x22, 0xA3, 0xF0, 0xAD, 0x01, 0xF6, 0x92, 0x78, 0xF0, ++ 0x78, 0xF6, 0x8D, 0x78, 0xF6, 0x08, 0xF6, 0x8E, 0xF6, 0x08, 0xF6, 0x08, 0xAA, 0x76, 0x94, 0x78, ++ 0x01, 0x76, 0x8C, 0x78, 0x90, 0xF6, 0x93, 0x78, 0xC5, 0x74, 0xE0, 0x01, 0x67, 0x74, 0xA3, 0xF0, ++ 0xE2, 0x01, 0x90, 0xF0, 0xA3, 0xF0, 0x70, 0x74, 0x90, 0xF0, 0x03, 0x74, 0x20, 0x74, 0xE4, 0x01, ++ 0xF0, 0xE4, 0xA3, 0xF0, 0x74, 0xE6, 0x01, 0x90, 0xE4, 0xA3, 0xF0, 0x40, 0xE8, 0x01, 0x90, 0xF0, ++ 0xA3, 0xF0, 0x40, 0x74, 0x90, 0xF0, 0x20, 0x74, 0x0F, 0x74, 0x36, 0x06, 0xF0, 0xE4, 0xA3, 0xF0, ++ 0xF0, 0x08, 0x07, 0x90, 0xF0, 0x80, 0x44, 0xE0, 0x0D, 0x90, 0xE4, 0x22, 0x0D, 0x90, 0xF0, 0x01, ++ 0x0D, 0x90, 0xF0, 0x21, 0xF0, 0xFF, 0x74, 0x41, 0xF0, 0x61, 0x0D, 0x90, 0xE0, 0x00, 0x0D, 0x90, ++ 0xE0, 0xF0, 0xF8, 0x54, 0xE0, 0xF0, 0x18, 0x44, 0xF0, 0x20, 0x0D, 0x90, 0x74, 0x0A, 0x0D, 0x90, ++ 0x0D, 0x90, 0xF0, 0x69, 0x0D, 0x90, 0xF0, 0x2A, 0xF0, 0x7C, 0x74, 0x06, 0xF0, 0x26, 0x0D, 0x90, ++ 0x74, 0xA2, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0xAA, 0xF0, 0x11, 0x74, 0x0C, 0xF0, 0x2C, 0x0D, 0x90, ++ 0x74, 0x02, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x30, 0x0D, 0x90, 0xF0, 0x22, 0xF0, 0x20, 0x74, 0x05, ++ 0xF0, 0x25, 0x0D, 0x90, 0x74, 0xF8, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x01, 0x01, 0x44, 0xE0, 0xFD, ++ 0x02, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xF0, 0x67, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, ++ 0xE0, 0x08, 0x0A, 0x90, 0xE0, 0xF0, 0x02, 0x44, 0x90, 0xF0, 0xFD, 0x54, 0x54, 0xE0, 0x10, 0x07, ++ 0x10, 0xF0, 0x75, 0x0F, 0xFD, 0xAB, 0x24, 0xA4, 0xFC, 0xF0, 0x35, 0xE4, 0xE0, 0x0F, 0x07, 0x90, ++ 0xA4, 0xAA, 0xF0, 0x75, 0x78, 0x2D, 0xF0, 0xAE, 0x3C, 0xEE, 0xF6, 0x7B, 0xE6, 0x08, 0xF6, 0x18, ++ 0xF0, 0x6A, 0x08, 0x90, 0xE0, 0x0F, 0x07, 0x90, 0xF0, 0x75, 0x0F, 0x54, 0x90, 0xFF, 0xA4, 0x10, ++ 0xC4, 0xE0, 0x10, 0x07, 0xE5, 0xFD, 0x0F, 0x54, 0x4F, 0xED, 0xFC, 0xF0, 0x2D, 0xE6, 0x18, 0xFD, ++ 0xCF, 0x3C, 0xE4, 0xFF, 0xF6, 0x08, 0xAA, 0x24, 0xF6, 0x18, 0x3F, 0xE4, 0x08, 0x90, 0xE6, 0x08, ++ 0x07, 0x90, 0xF0, 0x69, 0x54, 0xC4, 0xE0, 0x0F, 0xE6, 0x18, 0xFD, 0x0F, 0x33, 0xE4, 0xFF, 0x2D, ++ 0x08, 0x0A, 0x24, 0xCF, 0x18, 0x3F, 0xE4, 0xF6, 0x90, 0xE6, 0x08, 0xF6, 0x90, 0xF0, 0x68, 0x08, ++ 0x01, 0x74, 0x6B, 0x08, 0x52, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x0B, 0x74, 0x07, 0x74, 0x51, 0x08, ++ 0x52, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x0A, 0x74, 0x06, 0x74, 0x51, 0x08, 0x39, 0x08, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x40, 0x08, 0x90, 0x90, 0xF0, 0x01, 0x44, 0x44, 0xE0, 0x41, 0x08, ++ 0x44, 0xE0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x54, 0xE0, 0xF0, 0x08, 0x08, 0x90, 0xF0, 0xFD, ++ 0x01, 0x44, 0xE0, 0x42, 0x02, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xF0, 0x43, 0x08, 0x90, 0xF0, ++ 0x74, 0xF0, 0x03, 0x74, 0x08, 0x90, 0xF0, 0x01, 0x01, 0x44, 0xE0, 0x3E, 0x02, 0x44, 0xE0, 0xF0, ++ 0xFD, 0x54, 0xE0, 0xF0, 0xFB, 0x54, 0xE0, 0xF0, 0x54, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, ++ 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xFB, 0x54, 0xE0, 0xF0, 0xF7, 0x54, 0xE0, 0x74, 0x55, 0x08, 0x90, ++ 0x08, 0x90, 0xF0, 0x0F, 0x08, 0x90, 0xF0, 0x56, 0xFC, 0x54, 0xE0, 0x5B, 0xE0, 0xF0, 0x01, 0x44, ++ 0x10, 0x44, 0xC3, 0x54, 0x5D, 0x08, 0x90, 0xF0, 0xF0, 0x03, 0x44, 0xE0, 0xF0, 0xF3, 0x54, 0xE0, ++ 0xE0, 0x54, 0x08, 0x90, 0x90, 0xF0, 0xFD, 0x54, 0x44, 0xE0, 0x7B, 0x07, 0x07, 0x90, 0xF0, 0x01, ++ 0xF8, 0x54, 0xE0, 0x7C, 0x90, 0xF0, 0x03, 0x44, 0x01, 0x74, 0x9F, 0x07, 0x94, 0x07, 0x90, 0xF0, ++ 0x95, 0x07, 0x90, 0xF0, 0x98, 0x07, 0x90, 0xF0, 0x99, 0x07, 0x90, 0xF0, 0x9C, 0x07, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xE0, 0x9D, 0x07, 0x90, 0xE0, 0xF0, 0x01, 0x44, ++ 0x90, 0xF0, 0x02, 0x44, 0xFF, 0x74, 0xA4, 0x07, 0x00, 0x22, 0x22, 0xF0, 0x00, 0x00, 0x00, 0x00, ++ 0x61, 0x4D, 0x1C, 0x41, 0x00, 0x0A, 0x6E, 0x69, 0x74, 0x69, 0x6E, 0x49, 0x63, 0x41, 0x00, 0x0A, ++ 0x01, 0x00, 0x0A, 0x74, 0x4F, 0x4E, 0x09, 0x09, 0x54, 0x41, 0x4D, 0x2D, 0x00, 0x0A, 0x48, 0x43, ++ 0x7E, 0x0E, 0x08, 0x30, 0x12, 0x0E, 0x7F, 0x20, 0x20, 0xAF, 0x1D, 0x0E, 0xF5, 0xDF, 0x54, 0xEF, ++ 0xEF, 0x20, 0xAF, 0x20, 0x21, 0x02, 0xE0, 0x30, 0xEF, 0x20, 0xAF, 0xEE, 0xE0, 0x30, 0x13, 0xC3, ++ 0x02, 0x5F, 0x75, 0x07, 0x22, 0x3D, 0x60, 0x75, 0xC4, 0xEF, 0x20, 0xAF, 0xE0, 0x30, 0x0F, 0x54, ++ 0x12, 0x06, 0x90, 0x33, 0x54, 0x13, 0xC4, 0xE0, 0x07, 0xBF, 0xFF, 0x07, 0x02, 0x5F, 0x75, 0x07, ++ 0x22, 0x42, 0x60, 0x75, 0xE0, 0x12, 0x06, 0x90, 0x07, 0x54, 0x13, 0xC4, 0x0D, 0x06, 0xBF, 0xFF, ++ 0x75, 0x02, 0x5F, 0x75, 0x5F, 0x75, 0x4C, 0x60, 0x51, 0x60, 0x75, 0x02, 0x02, 0x5F, 0x75, 0x22, ++ 0x22, 0x47, 0x60, 0x75, 0x90, 0x0A, 0x0E, 0x30, 0xC4, 0xE0, 0x00, 0x06, 0xE0, 0x20, 0x0F, 0x54, ++ 0x00, 0x06, 0x90, 0x18, 0x0F, 0x54, 0xC4, 0xE0, 0x90, 0x0E, 0xE0, 0x30, 0xFF, 0xE0, 0x2F, 0x06, ++ 0x64, 0x03, 0x54, 0xC4, 0x21, 0x02, 0x60, 0x01, 0x00, 0x06, 0x90, 0xF5, 0x0F, 0x54, 0xC4, 0xE0, ++ 0x21, 0x02, 0xE0, 0x30, 0xA3, 0xFE, 0xE0, 0x34, 0xCE, 0x06, 0x78, 0xE0, 0x13, 0xCE, 0x13, 0xC3, ++ 0x01, 0x54, 0xF9, 0xD8, 0x90, 0xFD, 0xE0, 0x25, 0xC4, 0xE0, 0x00, 0x06, 0x4D, 0x01, 0x54, 0x13, ++ 0x31, 0x06, 0x90, 0xFD, 0x6D, 0x03, 0x54, 0xE0, 0x06, 0x90, 0x07, 0x60, 0x02, 0x44, 0xE0, 0x35, ++ 0xED, 0x05, 0xAF, 0xF0, 0x90, 0xFF, 0x03, 0x54, 0x54, 0xE0, 0x31, 0x06, 0x90, 0xF0, 0x4F, 0xFC, ++ 0x54, 0xE0, 0x00, 0x06, 0x06, 0x90, 0xFF, 0x01, 0x13, 0xFE, 0xE0, 0x31, 0x01, 0x54, 0x13, 0x13, ++ 0x90, 0x07, 0x60, 0x6F, 0x44, 0xE0, 0x35, 0x06, 0x06, 0x90, 0xF0, 0x04, 0x01, 0x54, 0xE0, 0x00, ++ 0x54, 0x33, 0x33, 0x33, 0x06, 0x90, 0xFF, 0xF8, 0xF7, 0x54, 0xE0, 0x31, 0x06, 0x90, 0xF0, 0x4F, ++ 0x54, 0xC4, 0xE0, 0x2F, 0x70, 0x01, 0x64, 0x03, 0x31, 0x06, 0x90, 0x29, 0x44, 0x3F, 0x54, 0xE0, ++ 0x1E, 0x80, 0xF0, 0x40, 0xE0, 0x2F, 0x06, 0x90, 0xFF, 0x03, 0x54, 0xC4, 0x90, 0x13, 0x01, 0xBF, ++ 0x54, 0xE0, 0x31, 0x06, 0xF0, 0x40, 0x44, 0x3F, 0x44, 0xFC, 0x54, 0xE0, 0x44, 0xE0, 0xF0, 0x02, ++ 0x07, 0x90, 0xF0, 0x08, 0x01, 0x44, 0xE0, 0x7B, 0x31, 0x06, 0x90, 0xF0, 0xFF, 0x03, 0x54, 0xE0, ++ 0xE0, 0x7C, 0x07, 0x90, 0xF0, 0x4F, 0xF8, 0x54, 0xE0, 0x31, 0x06, 0x90, 0x90, 0xFF, 0x08, 0x54, ++ 0x54, 0xE0, 0x7C, 0x07, 0x90, 0xF0, 0x4F, 0xF7, 0x54, 0xE0, 0x2F, 0x06, 0x13, 0x13, 0xC4, 0xC0, ++ 0x90, 0xFF, 0x03, 0x54, 0x54, 0xE0, 0x7D, 0x07, 0x90, 0xF0, 0x4F, 0xFC, 0xFF, 0xE0, 0x31, 0x06, ++ 0x54, 0x13, 0x13, 0xC4, 0x70, 0x01, 0x64, 0x03, 0x03, 0x54, 0xE0, 0x15, 0x0C, 0x02, 0xBF, 0xFF, ++ 0x01, 0x12, 0x0C, 0xD2, 0x02, 0x5F, 0x75, 0xD9, 0x22, 0x79, 0x60, 0x75, 0x06, 0x90, 0x40, 0x80, ++ 0x03, 0x54, 0xE0, 0x31, 0x60, 0x14, 0x2C, 0x60, 0x32, 0x70, 0x14, 0x0F, 0x01, 0x12, 0x0C, 0xD2, ++ 0x02, 0x5F, 0x75, 0xD9, 0x22, 0x60, 0x60, 0x75, 0x01, 0x12, 0x0C, 0xD2, 0x17, 0x06, 0x90, 0xD9, ++ 0x07, 0x01, 0xB4, 0xE0, 0x75, 0x02, 0x5F, 0x75, 0x75, 0x22, 0x7E, 0x60, 0x60, 0x75, 0x02, 0x5F, ++ 0x0C, 0xD2, 0x22, 0x5B, 0x75, 0xD9, 0x01, 0x12, 0x60, 0x75, 0x02, 0x5F, 0x5D, 0x75, 0x22, 0x56, ++ 0x06, 0x5E, 0x75, 0x22, 0x00, 0x06, 0x90, 0x22, 0x0F, 0x54, 0xC4, 0xE0, 0x75, 0x06, 0xE0, 0x30, ++ 0x60, 0x75, 0x01, 0x5F, 0x90, 0xE4, 0x22, 0xCF, 0x7E, 0xF0, 0xAC, 0x01, 0x12, 0x08, 0x7F, 0x20, ++ 0x01, 0x12, 0x1D, 0x0E, 0x20, 0x5D, 0x75, 0xB6, 0x22, 0x20, 0x5E, 0x75, 0x0F, 0x60, 0x73, 0xE5, ++ 0x02, 0x7F, 0x20, 0x7E, 0x75, 0x1D, 0x0E, 0x12, 0x5E, 0x75, 0x22, 0x5D, 0xE5, 0x08, 0xD2, 0x06, ++ 0x70, 0x5E, 0x65, 0x62, 0x65, 0x61, 0xE5, 0x04, 0x85, 0x08, 0x60, 0x5D, 0x5E, 0x85, 0x61, 0x5D, ++ 0xAA, 0x08, 0xD2, 0x62, 0x12, 0x62, 0xA9, 0x61, 0x08, 0xC2, 0xEB, 0x02, 0xEF, 0x63, 0xAF, 0x22, ++ 0x63, 0xF5, 0xFE, 0x54, 0x75, 0x02, 0x5D, 0x75, 0x90, 0xE4, 0x38, 0x5E, 0xA3, 0xF0, 0x30, 0x06, ++ 0x09, 0x06, 0x90, 0xF0, 0x64, 0x1F, 0x54, 0xE0, 0x61, 0x02, 0x60, 0x01, 0x0B, 0x06, 0x90, 0xDC, ++ 0x64, 0x1F, 0x54, 0xE0, 0x61, 0x02, 0x60, 0x01, 0x0A, 0x06, 0x90, 0xDC, 0xE0, 0xA3, 0xFE, 0xE0, ++ 0x08, 0x06, 0x90, 0xFF, 0x6E, 0xF5, 0x5E, 0xE0, 0xF5, 0x5F, 0xE0, 0xA3, 0x12, 0x06, 0x90, 0x6F, ++ 0x30, 0x13, 0xC3, 0xE0, 0x06, 0x90, 0x0C, 0xE0, 0x13, 0x13, 0xE0, 0x14, 0x20, 0x1F, 0x54, 0x13, ++ 0x06, 0x90, 0x12, 0xE0, 0xE0, 0x30, 0xE0, 0x12, 0x14, 0x06, 0x90, 0x67, 0x54, 0x13, 0x13, 0xE0, ++ 0x5C, 0xE0, 0x30, 0x3F, 0xE0, 0x31, 0x06, 0x90, 0x02, 0x44, 0xFC, 0x54, 0x12, 0x06, 0x90, 0xF0, ++ 0x30, 0x13, 0xC3, 0xE0, 0x06, 0x90, 0x15, 0xE0, 0x13, 0x13, 0xE0, 0x14, 0x30, 0x1F, 0x54, 0x13, ++ 0x06, 0x90, 0x09, 0xE0, 0x08, 0x44, 0xE0, 0x31, 0x90, 0x07, 0x80, 0xF0, 0x54, 0xE0, 0x31, 0x06, ++ 0x01, 0x90, 0xF0, 0xF7, 0x13, 0xFF, 0xE0, 0xB0, 0x30, 0x3F, 0x54, 0x13, 0x01, 0x90, 0x13, 0xE0, ++ 0x13, 0xFF, 0xE0, 0xB8, 0x30, 0x3F, 0x54, 0x13, 0x06, 0x90, 0x07, 0xE0, 0x04, 0x44, 0xE0, 0x31, ++ 0x40, 0xFE, 0x71, 0xF0, 0xAF, 0x91, 0x61, 0x02, 0x01, 0x44, 0xEF, 0x63, 0x91, 0x61, 0x63, 0xF5, ++ 0xA1, 0x00, 0x90, 0xE4, 0xEF, 0x6E, 0xAF, 0xF0, 0x90, 0x0A, 0xE0, 0x30, 0x54, 0xE0, 0x31, 0x06, ++ 0x80, 0x01, 0x44, 0xFC, 0xEF, 0x6F, 0xAF, 0x27, 0x13, 0x13, 0x13, 0xC4, 0xE0, 0x30, 0x01, 0x54, ++ 0x31, 0x06, 0x90, 0x0A, 0x44, 0xFC, 0x54, 0xE0, 0xAF, 0x28, 0x80, 0x01, 0x13, 0xC4, 0xEF, 0x6F, ++ 0x30, 0x03, 0x54, 0x13, 0x06, 0x90, 0x0D, 0xE0, 0xFC, 0x54, 0xE0, 0x31, 0x08, 0x44, 0xE0, 0xF0, ++ 0xAF, 0x1E, 0x80, 0xF0, 0x13, 0xC4, 0xEF, 0x6F, 0xE0, 0x30, 0x07, 0x54, 0x31, 0x06, 0x90, 0x0D, ++ 0xF0, 0xFC, 0x54, 0xE0, 0xF0, 0xF7, 0x54, 0xE0, 0x63, 0xAF, 0x07, 0x80, 0xF5, 0x01, 0x44, 0xEF, ++ 0xB0, 0x01, 0x90, 0x63, 0x30, 0x13, 0xC3, 0xE0, 0x01, 0x90, 0x17, 0xE0, 0x13, 0xC3, 0xE0, 0xB8, ++ 0x90, 0x0E, 0xE0, 0x30, 0x54, 0xE0, 0x31, 0x06, 0x01, 0xBF, 0xFF, 0x03, 0x04, 0x44, 0xE0, 0x04, ++ 0xEF, 0x6E, 0xAF, 0xF0, 0x3F, 0x54, 0x13, 0x13, 0x90, 0x09, 0xE0, 0x30, 0x44, 0xE0, 0x31, 0x06, ++ 0x3F, 0x80, 0xF0, 0x30, 0x13, 0xEF, 0x6E, 0xAF, 0x1F, 0x54, 0x13, 0x13, 0x90, 0x24, 0xE0, 0x30, ++ 0x30, 0xE0, 0x08, 0x06, 0x06, 0x90, 0x0B, 0xE2, 0xCF, 0x54, 0xE0, 0x31, 0x80, 0xF0, 0x20, 0x44, ++ 0x0A, 0x06, 0x90, 0x22, 0x31, 0x06, 0x90, 0xE0, 0xE0, 0x0B, 0xE2, 0x30, 0x10, 0x44, 0xCF, 0x54, ++ 0x90, 0x10, 0x80, 0xF0, 0x54, 0xE0, 0x31, 0x06, 0x07, 0x80, 0xF0, 0xCF, 0x44, 0xEF, 0x63, 0xAF, ++ 0xAF, 0x63, 0xF5, 0x01, 0xE0, 0x30, 0xEF, 0x63, 0x7F, 0x20, 0x7E, 0x14, 0x1D, 0x0E, 0x12, 0x14, ++ 0x75, 0x02, 0x5D, 0x75, 0x06, 0x90, 0x33, 0x5E, 0x08, 0x44, 0xE0, 0x34, 0x01, 0x7E, 0x22, 0xF0, ++ 0x06, 0x90, 0x0C, 0xC2, 0x13, 0xC4, 0xE0, 0x26, 0xBD, 0xFD, 0x07, 0x54, 0x06, 0x90, 0x09, 0x04, ++ 0x40, 0x44, 0xE0, 0x14, 0x90, 0x22, 0xC3, 0xF0, 0xC4, 0xE0, 0x12, 0x06, 0xE0, 0x30, 0x0F, 0x54, ++ 0x13, 0x13, 0xE0, 0x0B, 0x24, 0x01, 0x54, 0x13, 0x09, 0x80, 0xF9, 0x02, 0xE0, 0x12, 0x06, 0x90, ++ 0x01, 0x54, 0x13, 0x13, 0xE6, 0x8B, 0x78, 0xF9, 0xE6, 0x0A, 0xE0, 0x30, 0x01, 0x54, 0x13, 0xC3, ++ 0x80, 0xFC, 0x02, 0x24, 0xE6, 0x8B, 0x78, 0x08, 0x01, 0x54, 0x13, 0x13, 0xFD, 0x24, 0xE9, 0xFC, ++ 0x70, 0x04, 0x0C, 0x60, 0xEC, 0xFE, 0xE4, 0x1B, 0x6A, 0x70, 0x02, 0x64, 0x01, 0x7E, 0x07, 0x80, ++ 0x70, 0x03, 0x64, 0xEC, 0x14, 0x06, 0x90, 0x61, 0xF0, 0x80, 0x44, 0xE0, 0x56, 0x80, 0x0C, 0xD2, ++ 0x3D, 0x70, 0x6C, 0xE9, 0xFA, 0xE6, 0x85, 0x78, 0x88, 0x78, 0xE6, 0x08, 0xEA, 0x03, 0x70, 0x66, ++ 0x16, 0x70, 0x66, 0x18, 0x82, 0x78, 0x0C, 0xD2, 0x94, 0xC3, 0xE6, 0x06, 0x90, 0x37, 0x40, 0x07, ++ 0x44, 0xE0, 0x14, 0x06, 0x07, 0x76, 0xF0, 0x80, 0x85, 0x78, 0x2C, 0x80, 0xE6, 0x08, 0xFA, 0xE6, ++ 0x96, 0x88, 0x78, 0xD3, 0x7F, 0x96, 0x18, 0xEA, 0x7F, 0x02, 0x40, 0x00, 0x80, 0x07, 0xAE, 0x01, ++ 0x94, 0xC3, 0xEC, 0x15, 0x74, 0x06, 0x40, 0x02, 0x80, 0xFE, 0x9C, 0x03, 0xB9, 0x00, 0x7F, 0x09, ++ 0x01, 0x7F, 0x02, 0x01, 0x54, 0xEE, 0x07, 0xAE, 0x33, 0x33, 0xC4, 0x01, 0x90, 0xFF, 0xC0, 0x54, ++ 0x54, 0xE0, 0x14, 0x06, 0x30, 0xF0, 0x4F, 0xBF, 0x06, 0x90, 0x07, 0x0C, 0x40, 0x44, 0xE0, 0x34, ++ 0x22, 0x0C, 0xA2, 0xF0, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x09, 0x09, 0x44, 0x21, 0x58, 0x52, 0x09, 0x09, 0x0A, 0x78, 0x25, 0x3A, 0x09, 0x09, 0x09, 0x00, ++ 0x64, 0x25, 0x58, 0x54, 0x78, 0x25, 0x00, 0x3A, 0x54, 0x09, 0x00, 0x0A, 0x73, 0x69, 0x44, 0x78, ++ 0x41, 0x09, 0x00, 0x0A, 0x2D, 0x6C, 0x69, 0x62, 0x09, 0x00, 0x0A, 0x44, 0x43, 0x2D, 0x53, 0x4C, ++ 0x00, 0x0A, 0x6B, 0x68, 0x44, 0x50, 0x09, 0x09, 0x75, 0x61, 0x46, 0x2D, 0x00, 0x0A, 0x74, 0x6C, ++ 0x4B, 0x43, 0x41, 0x09, 0x00, 0x0A, 0x44, 0x2D, 0x41, 0x2D, 0x43, 0x09, 0x00, 0x0A, 0x4B, 0x43, ++ 0x58, 0x52, 0x09, 0x09, 0x3D, 0x4D, 0x53, 0x46, 0x00, 0x0A, 0x64, 0x25, 0x2D, 0x50, 0x4E, 0x09, ++ 0x74, 0x69, 0x61, 0x57, 0x09, 0x09, 0x00, 0x0A, 0x53, 0x46, 0x58, 0x54, 0x64, 0x25, 0x3D, 0x4D, ++ 0x41, 0x09, 0x00, 0x0A, 0x0A, 0x73, 0x65, 0x52, 0x2D, 0x09, 0x09, 0x00, 0x30, 0x31, 0x20, 0x3E, ++ 0x78, 0x00, 0x30, 0x00, 0x2D, 0x00, 0x73, 0x00, 0x2D, 0x00, 0x44, 0x46, 0x2F, 0x00, 0x44, 0x48, ++ 0x53, 0x2F, 0x00, 0x4D, 0x45, 0x45, 0x2F, 0x00, 0x50, 0x2D, 0x00, 0x45, 0x64, 0x25, 0x3A, 0x53, ++ 0x01, 0x02, 0x00, 0x0A, 0x02, 0x5D, 0x75, 0xBB, 0x90, 0x33, 0x5E, 0x75, 0x54, 0xE0, 0x0D, 0x06, ++ 0x20, 0xAF, 0xF0, 0xEF, 0xF5, 0xFB, 0x54, 0xEF, 0x00, 0x06, 0x90, 0x20, 0xF0, 0xFD, 0x54, 0xE0, ++ 0xE0, 0xAD, 0x01, 0x90, 0x11, 0xF0, 0x04, 0x44, 0xF8, 0x07, 0x90, 0xA2, 0xE4, 0xF0, 0x01, 0x74, ++ 0x90, 0xF6, 0x82, 0x78, 0xC4, 0xE0, 0xAA, 0x0D, 0x90, 0xFF, 0x0F, 0x54, 0xC4, 0xE0, 0xAB, 0x0D, ++ 0xFF, 0x2F, 0x0F, 0x54, 0x24, 0xCF, 0x33, 0xE4, 0x34, 0xEF, 0xFD, 0x00, 0x07, 0x90, 0xFC, 0x04, ++ 0xF0, 0x75, 0xE0, 0x0B, 0xEC, 0xFF, 0xA4, 0x20, 0x80, 0x78, 0xF0, 0x45, 0x08, 0x4F, 0xED, 0xF6, ++ 0x4B, 0x07, 0x90, 0xF6, 0x90, 0xF0, 0x61, 0x74, 0xA8, 0x74, 0x4C, 0x07, 0x12, 0xFF, 0xE4, 0xF0, ++ 0x90, 0xE4, 0x32, 0x04, 0x90, 0xF0, 0x00, 0x00, 0xC4, 0xE0, 0x2F, 0x06, 0xBF, 0xFF, 0x03, 0x54, ++ 0x06, 0x90, 0x21, 0x03, 0xE0, 0x54, 0xE0, 0x08, 0x54, 0xE0, 0xA3, 0xFE, 0x44, 0xEE, 0xFF, 0x1F, ++ 0x08, 0x06, 0x90, 0x0C, 0xF0, 0xEF, 0xA3, 0xF0, 0xE0, 0x12, 0x06, 0x90, 0xE0, 0xF0, 0x02, 0x44, ++ 0x22, 0xF0, 0x01, 0x44, 0x28, 0x60, 0x73, 0xE5, 0x75, 0x07, 0x17, 0x75, 0x15, 0x75, 0xA0, 0x18, ++ 0xA2, 0x16, 0x75, 0x07, 0xF6, 0x7C, 0x78, 0xE4, 0xF6, 0x08, 0xF6, 0x08, 0xA5, 0x11, 0xF6, 0x08, ++ 0x64, 0xAF, 0x08, 0xD2, 0xF5, 0xFD, 0x54, 0xEF, 0xEF, 0x64, 0xAF, 0x64, 0x64, 0xF5, 0xFE, 0x54, ++ 0xC4, 0xEF, 0x20, 0xAF, 0xE0, 0x20, 0x0F, 0x54, 0xEF, 0x20, 0xAF, 0x23, 0xAF, 0x1D, 0xE0, 0x20, ++ 0x13, 0xC3, 0xEF, 0x20, 0xAF, 0x15, 0xE0, 0x20, 0x13, 0x13, 0xEF, 0x20, 0xE0, 0x20, 0x3F, 0x54, ++ 0x00, 0x06, 0x90, 0x0B, 0x54, 0xC4, 0xFF, 0xE0, 0x12, 0xE0, 0x20, 0x0F, 0x56, 0x7F, 0x2D, 0x7E, ++ 0x70, 0x5E, 0x65, 0xEF, 0x5D, 0x65, 0xEE, 0x03, 0x5D, 0x8E, 0x04, 0x60, 0x4A, 0x71, 0x5E, 0x8F, ++ 0x54, 0xEF, 0x64, 0xAF, 0x90, 0x64, 0xF5, 0xFD, 0x30, 0xE0, 0xA4, 0x07, 0x20, 0x7E, 0x1F, 0xE1, ++ 0x16, 0x85, 0x02, 0x7F, 0x83, 0x15, 0x85, 0x82, 0xE0, 0xA3, 0xFC, 0xE0, 0x0D, 0x0D, 0x12, 0xFD, ++ 0x44, 0xEF, 0x64, 0xAF, 0x90, 0x64, 0xF5, 0x02, 0x02, 0x74, 0xA4, 0x07, 0x65, 0x62, 0xE5, 0xF0, ++ 0xE5, 0x04, 0x70, 0x5E, 0x60, 0x5D, 0x65, 0x61, 0x61, 0x5D, 0x85, 0x08, 0xD2, 0x62, 0x5E, 0x85, ++ 0xA9, 0x61, 0xAA, 0x08, 0xEB, 0x02, 0x12, 0x62, 0x64, 0xAF, 0x08, 0xC2, 0xF5, 0xFE, 0x54, 0xEF, ++ 0xA4, 0x07, 0x90, 0x64, 0x31, 0xE3, 0x30, 0xE0, 0x0D, 0x7F, 0x20, 0x7E, 0xE0, 0x23, 0x06, 0x90, ++ 0x01, 0x54, 0x13, 0x13, 0x12, 0x00, 0x7C, 0xFD, 0x20, 0x7E, 0x0D, 0x0D, 0x18, 0x85, 0x16, 0x7F, ++ 0x83, 0x17, 0x85, 0x82, 0xE0, 0xA3, 0xFC, 0xE0, 0x0D, 0x0D, 0x12, 0xFD, 0x44, 0xEF, 0x64, 0xAF, ++ 0x90, 0x64, 0xF5, 0x01, 0x08, 0x74, 0xA4, 0x07, 0x5F, 0x08, 0x90, 0xF0, 0x13, 0x13, 0x13, 0xE0, ++ 0xE0, 0x30, 0x1F, 0x54, 0xE6, 0x83, 0x78, 0x14, 0xAF, 0x09, 0x0A, 0xB4, 0x02, 0x44, 0xEF, 0x63, ++ 0x16, 0x80, 0x63, 0xF5, 0x80, 0x06, 0x83, 0x78, 0xE6, 0x83, 0x78, 0x11, 0x63, 0xAF, 0x09, 0x70, ++ 0xF5, 0xFD, 0x54, 0xEF, 0x78, 0x03, 0x80, 0x63, 0x08, 0x90, 0x16, 0x83, 0xF0, 0x08, 0x74, 0x5F, ++ 0xE0, 0xA6, 0x07, 0x90, 0x84, 0x78, 0x07, 0x54, 0x00, 0x7F, 0xE6, 0xF6, 0x7F, 0x02, 0x02, 0xB4, ++ 0x01, 0x54, 0xEF, 0x01, 0x54, 0x33, 0x33, 0x33, 0x63, 0xAE, 0xFF, 0xF8, 0x4F, 0xF7, 0x54, 0xEE, ++ 0x7E, 0x7F, 0x63, 0xF5, 0x50, 0xB4, 0x0B, 0x12, 0xEF, 0x63, 0xAF, 0x07, 0x63, 0xF5, 0xFB, 0x54, ++ 0xE0, 0xA4, 0x07, 0x90, 0x78, 0x17, 0xE0, 0x30, 0x01, 0xB4, 0xE6, 0x84, 0xEF, 0x63, 0xAF, 0x11, ++ 0x63, 0xF5, 0x04, 0x44, 0x01, 0x76, 0x7E, 0x78, 0x74, 0xF4, 0x76, 0x08, 0x63, 0xAF, 0xF0, 0x01, ++ 0x54, 0x13, 0x13, 0xEF, 0x11, 0xE0, 0x20, 0x3F, 0x13, 0xEF, 0x63, 0xAF, 0x1F, 0x54, 0x13, 0x13, ++ 0x78, 0x06, 0xE0, 0x20, 0x03, 0xB4, 0xE6, 0x84, 0xEF, 0x63, 0xAF, 0x07, 0x63, 0xF5, 0xFD, 0x54, ++ 0x13, 0xEF, 0x63, 0xAF, 0x01, 0x54, 0x13, 0x13, 0xEE, 0x63, 0xAE, 0xFF, 0x01, 0x54, 0x13, 0x13, ++ 0x63, 0xAE, 0xFF, 0x4F, 0x54, 0x13, 0xC3, 0xEE, 0x01, 0x54, 0x4F, 0x01, 0xEE, 0x63, 0xAE, 0xFF, ++ 0xF5, 0x4F, 0xFE, 0x54, 0xEF, 0x64, 0xAF, 0x63, 0x90, 0x29, 0xE0, 0x30, 0x54, 0xE0, 0x52, 0x08, ++ 0x08, 0x90, 0xF0, 0xFD, 0xFE, 0x54, 0xE0, 0x43, 0x9F, 0x07, 0x90, 0xF0, 0xFF, 0x1F, 0x54, 0xE0, ++ 0x00, 0x7C, 0x00, 0x7E, 0x02, 0x12, 0x0A, 0x7D, 0x39, 0x24, 0xEF, 0x84, 0xE4, 0xF6, 0x7D, 0x78, ++ 0x22, 0xF6, 0x18, 0x3E, 0x0B, 0x12, 0x7C, 0x7F, 0x90, 0x0E, 0x50, 0xB4, 0x44, 0xE0, 0x52, 0x08, ++ 0x08, 0x90, 0xF0, 0x02, 0x01, 0x44, 0xE0, 0x43, 0x81, 0x78, 0x22, 0xF0, 0xFF, 0x01, 0x54, 0xE6, ++ 0x74, 0x9F, 0xE4, 0xC3, 0x54, 0x00, 0x94, 0x08, 0xE6, 0x18, 0xFC, 0x05, 0x08, 0xFE, 0x13, 0xC3, ++ 0xEE, 0xFF, 0x13, 0xE6, 0xEF, 0xF6, 0x18, 0x6C, 0x7E, 0x22, 0xF6, 0x08, 0x12, 0x72, 0x7F, 0x20, ++ 0x02, 0x02, 0x1D, 0x0E, 0x34, 0x08, 0x30, 0x2E, 0x1A, 0x7F, 0x20, 0x7E, 0x78, 0x1D, 0x0E, 0x12, ++ 0x08, 0x34, 0x76, 0x74, 0x06, 0x90, 0xBC, 0x76, 0x13, 0xFF, 0xE0, 0x23, 0x13, 0x3F, 0x54, 0x13, ++ 0x0D, 0xD2, 0x0C, 0x92, 0x07, 0x90, 0xC5, 0x71, 0xF0, 0x03, 0x74, 0x9D, 0xE0, 0x03, 0x06, 0x90, ++ 0xC2, 0xF0, 0xDF, 0x54, 0xEF, 0x20, 0xAF, 0x0E, 0x20, 0xF5, 0xF7, 0x54, 0x0B, 0x12, 0x74, 0x7F, ++ 0x75, 0x06, 0x50, 0xB4, 0x5E, 0x75, 0x24, 0x5D, 0xFF, 0xE0, 0x22, 0xD2, 0x3F, 0x54, 0x13, 0x13, ++ 0xC2, 0x0C, 0x92, 0x13, 0x27, 0x06, 0x90, 0x0D, 0x03, 0xE0, 0x30, 0xE0, 0x90, 0x0F, 0x0C, 0x30, ++ 0x20, 0xE0, 0x27, 0x06, 0x13, 0xE0, 0x70, 0xE0, 0x20, 0x3F, 0x54, 0x13, 0x0C, 0xC2, 0x68, 0xE0, ++ 0x33, 0xE4, 0x0D, 0xA2, 0x44, 0xF0, 0x54, 0xC4, 0x0D, 0x90, 0xFF, 0x0F, 0x13, 0xC4, 0xE0, 0x01, ++ 0x33, 0xC4, 0x01, 0x54, 0xF0, 0x4F, 0xE0, 0x54, 0xE0, 0x21, 0x0D, 0x90, 0x01, 0x54, 0x13, 0xC4, ++ 0xE0, 0x54, 0x33, 0xC4, 0x90, 0xF0, 0x10, 0x44, 0x54, 0xE0, 0x00, 0x0D, 0x0D, 0x90, 0xF0, 0x9F, ++ 0x9F, 0x54, 0xE0, 0x20, 0x90, 0xF0, 0x20, 0x44, 0xC3, 0xE0, 0x29, 0x06, 0x0C, 0x0D, 0x90, 0x13, ++ 0x74, 0x09, 0xE0, 0x30, 0x0D, 0x90, 0xF0, 0x11, 0x09, 0x80, 0xF0, 0x2C, 0x90, 0xF0, 0x15, 0x74, ++ 0x12, 0x74, 0x2C, 0x0D, 0xF9, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0xE4, 0x74, 0xB1, 0x74, 0xFA, 0x07, ++ 0xA2, 0x00, 0x90, 0xF0, 0x0C, 0xD2, 0x66, 0x80, 0x33, 0xE4, 0x0D, 0xA2, 0x44, 0xF0, 0x54, 0xC4, ++ 0x0D, 0x90, 0xFF, 0x0F, 0x13, 0xC4, 0xE0, 0x21, 0x33, 0xC4, 0x01, 0x54, 0xF0, 0x4F, 0xE0, 0x54, ++ 0xE0, 0x01, 0x0D, 0x90, 0x01, 0x54, 0x13, 0xC4, 0xE0, 0x54, 0x33, 0xC4, 0x90, 0xF0, 0x10, 0x44, ++ 0x54, 0xE0, 0x00, 0x0D, 0xF0, 0x20, 0x44, 0x9F, 0xE0, 0x20, 0x0D, 0x90, 0x90, 0xF0, 0x9F, 0x54, ++ 0xC3, 0xE0, 0x29, 0x06, 0x0C, 0x0D, 0x90, 0x13, 0x74, 0x09, 0xE0, 0x30, 0x0D, 0x90, 0xF0, 0x11, ++ 0x09, 0x80, 0xF0, 0x2C, 0x90, 0xF0, 0x12, 0x74, 0x15, 0x74, 0x2C, 0x0D, 0xF9, 0x07, 0x90, 0xF0, ++ 0x90, 0xF0, 0xB1, 0x74, 0xE4, 0x74, 0xFA, 0x07, 0xA3, 0x00, 0x90, 0xF0, 0x45, 0x08, 0x90, 0xE0, ++ 0xE4, 0x0C, 0xA2, 0xF0, 0xFC, 0x01, 0x54, 0x33, 0xE0, 0x25, 0xE0, 0x25, 0x23, 0x06, 0x90, 0xFE, ++ 0x4E, 0xFB, 0x54, 0xE0, 0x33, 0x33, 0xEC, 0xF0, 0xFF, 0xF8, 0x54, 0x33, 0x4F, 0xF7, 0x54, 0xE0, ++ 0x08, 0x20, 0x22, 0xF0, 0x7E, 0xE3, 0xA1, 0x02, 0x12, 0x22, 0x7F, 0x20, 0x78, 0xE4, 0x1D, 0x0E, ++ 0x74, 0x78, 0xF6, 0x89, 0x9B, 0x76, 0x08, 0xF6, 0x08, 0x2A, 0x76, 0x08, 0x7A, 0x78, 0xC8, 0x76, ++ 0x76, 0x08, 0xFD, 0x76, 0xF5, 0x6B, 0xF5, 0xE8, 0x76, 0x78, 0x78, 0x6C, 0x6C, 0x76, 0x08, 0x02, ++ 0xF5, 0x01, 0x66, 0x75, 0x90, 0x68, 0xF5, 0x67, 0xFF, 0xE0, 0x08, 0x06, 0x18, 0x85, 0xE0, 0xA3, ++ 0x83, 0x17, 0x85, 0x82, 0xEF, 0xA3, 0xF0, 0xCF, 0x82, 0x18, 0x85, 0xF0, 0xC0, 0x83, 0x17, 0x85, ++ 0xE0, 0x82, 0xC0, 0x83, 0xB0, 0x01, 0x90, 0xFF, 0x54, 0x13, 0xC3, 0xE0, 0xC4, 0xEF, 0xFE, 0x01, ++ 0x54, 0x13, 0x13, 0x13, 0x54, 0xEF, 0xFD, 0x01, 0x4E, 0xED, 0xFF, 0x7F, 0x33, 0xC4, 0x01, 0x54, ++ 0x80, 0x54, 0x33, 0x33, 0xD0, 0x82, 0xD0, 0x4F, 0x18, 0x85, 0xF0, 0x83, 0x83, 0x17, 0x85, 0x82, ++ 0x82, 0xC0, 0x83, 0xC0, 0x06, 0x90, 0xFF, 0xE0, 0x13, 0xC4, 0xE0, 0x28, 0xFE, 0x03, 0x54, 0x13, ++ 0xE0, 0xA1, 0x00, 0x90, 0x7E, 0x9E, 0xC3, 0xFD, 0x7E, 0x02, 0x50, 0x00, 0x00, 0x7D, 0xED, 0x01, ++ 0x01, 0x7D, 0x02, 0x70, 0x90, 0xFE, 0x4D, 0xEE, 0xC3, 0xE0, 0x12, 0x06, 0xFD, 0x01, 0x54, 0x13, ++ 0x4D, 0x01, 0x54, 0xE0, 0xC4, 0xEF, 0xFE, 0x5E, 0x54, 0x13, 0x13, 0x13, 0x54, 0xEF, 0xFD, 0x01, ++ 0x4E, 0xED, 0xFF, 0x7F, 0x33, 0xC4, 0x01, 0x54, 0x80, 0x54, 0x33, 0x33, 0xD0, 0x82, 0xD0, 0x4F, ++ 0x18, 0x85, 0xF0, 0x83, 0x83, 0x17, 0x85, 0x82, 0xC4, 0x08, 0x54, 0xE0, 0xAE, 0xFF, 0xF0, 0x54, ++ 0x7F, 0x54, 0xEE, 0x63, 0xE4, 0x63, 0xF5, 0x4F, 0xF0, 0x0A, 0x06, 0x90, 0x06, 0x90, 0xF0, 0xA3, ++ 0xFE, 0x54, 0xE0, 0x0D, 0xF7, 0x54, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xF0, 0x06, 0x90, 0xE4, 0xF0, ++ 0xF0, 0xA3, 0xF0, 0x14, 0xF0, 0xB7, 0x01, 0x90, 0x07, 0x90, 0xF0, 0xA3, 0x06, 0x90, 0xF0, 0x9D, ++ 0xAF, 0xBA, 0x71, 0x23, 0x13, 0xC3, 0xEF, 0x63, 0xAF, 0x0A, 0xE0, 0x20, 0x13, 0x13, 0xEF, 0x63, ++ 0xE0, 0x30, 0x3F, 0x54, 0x12, 0x74, 0x7F, 0x27, 0x27, 0x50, 0xB4, 0x0B, 0x02, 0x76, 0x78, 0x78, ++ 0xAF, 0x6C, 0x76, 0x08, 0x02, 0x54, 0xEF, 0x63, 0xFF, 0xF0, 0x54, 0xC4, 0x54, 0xEE, 0x63, 0xAE, ++ 0x63, 0xF5, 0x4F, 0xDF, 0x75, 0x27, 0x5D, 0x75, 0x07, 0x80, 0x33, 0x5E, 0x01, 0x76, 0x74, 0x78, ++ 0x90, 0x36, 0x76, 0x08, 0x54, 0xE0, 0xA6, 0x07, 0x60, 0x02, 0x64, 0x07, 0x89, 0x78, 0xE4, 0x0A, ++ 0xF5, 0x6B, 0xF5, 0xF6, 0xAF, 0x4D, 0x80, 0x6C, 0x13, 0xC3, 0xEF, 0x64, 0x85, 0x45, 0xE0, 0x30, ++ 0x15, 0x85, 0x82, 0x16, 0x40, 0x54, 0xE0, 0x83, 0xEE, 0x6B, 0xAE, 0xFF, 0xF5, 0x4F, 0xBF, 0x54, ++ 0x82, 0x16, 0x85, 0x6B, 0xE0, 0x83, 0x15, 0x85, 0xB5, 0xE0, 0xA3, 0xFE, 0xB5, 0xEE, 0x15, 0x6C, ++ 0x89, 0x78, 0x11, 0x6B, 0x94, 0xC3, 0xE6, 0x06, 0x75, 0x19, 0x40, 0x02, 0x5E, 0x75, 0x27, 0x5D, ++ 0x85, 0x11, 0x80, 0xC1, 0x15, 0x85, 0x82, 0x16, 0x6B, 0xF5, 0xE0, 0x83, 0x6C, 0xF5, 0xE0, 0xA3, ++ 0xF6, 0x89, 0x78, 0xE4, 0xE0, 0x27, 0x06, 0x90, 0xE1, 0x02, 0xE0, 0x20, 0x12, 0x76, 0x7F, 0x1F, ++ 0x09, 0x40, 0xB4, 0x0B, 0x0B, 0x12, 0x78, 0x7F, 0xE1, 0x02, 0x40, 0xB4, 0xEF, 0x64, 0xAF, 0x32, ++ 0xE1, 0x02, 0xE0, 0x20, 0xEF, 0x63, 0xAF, 0x32, 0xE1, 0x02, 0xE0, 0x30, 0xE6, 0x77, 0x78, 0x32, ++ 0x42, 0x70, 0x46, 0x18, 0xE0, 0x54, 0x08, 0x90, 0x90, 0xF0, 0x02, 0x44, 0xFF, 0xE0, 0x23, 0x06, ++ 0x3F, 0x54, 0x13, 0x13, 0x90, 0x07, 0xE0, 0x30, 0x44, 0xE0, 0x35, 0x06, 0x08, 0x90, 0xF0, 0x08, ++ 0xFD, 0x54, 0xE0, 0x54, 0xC2, 0x0C, 0xC2, 0xF0, 0x78, 0xC5, 0x71, 0x0D, 0x07, 0x54, 0xE6, 0x80, ++ 0x25, 0xE6, 0x08, 0xFE, 0x33, 0xEE, 0xFF, 0xE0, 0xC8, 0x24, 0xEF, 0xFE, 0xEE, 0xF6, 0x77, 0x78, ++ 0xF6, 0x18, 0x2A, 0x34, 0x81, 0x78, 0x21, 0x80, 0xFF, 0x01, 0x54, 0xE6, 0xE0, 0x23, 0x06, 0x90, ++ 0x54, 0x13, 0x13, 0xFD, 0x01, 0x70, 0x6F, 0x01, 0x90, 0x07, 0x60, 0xE4, 0x44, 0xE0, 0x35, 0x06, ++ 0x81, 0x78, 0xF0, 0x08, 0x78, 0xC0, 0x71, 0xE6, 0x08, 0x02, 0x76, 0x78, 0x78, 0x22, 0x6C, 0x76, ++ 0x08, 0x02, 0x76, 0x78, 0x76, 0x78, 0x6C, 0x76, 0x76, 0x08, 0x2A, 0x76, 0x27, 0x06, 0x90, 0xC8, ++ 0x30, 0x22, 0xBA, 0x71, 0x20, 0x7E, 0x25, 0x08, 0x0E, 0x12, 0x2B, 0x7F, 0x9D, 0x07, 0x90, 0x1D, ++ 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x23, 0x06, 0x90, 0x54, 0x13, 0x13, 0xFF, 0x0C, 0x92, 0x13, 0x3F, ++ 0xC5, 0x71, 0x0D, 0xD2, 0x1D, 0x76, 0x74, 0x78, 0xAF, 0x4C, 0x76, 0x08, 0x13, 0xC4, 0xEF, 0x63, ++ 0x63, 0xAF, 0x07, 0x54, 0xEF, 0x0A, 0xE0, 0x30, 0x33, 0x33, 0x02, 0x54, 0x80, 0xF8, 0x54, 0x33, ++ 0x04, 0x54, 0xEF, 0x07, 0xE0, 0x25, 0xE0, 0x25, 0xEE, 0x63, 0xAE, 0xFF, 0xF5, 0x4F, 0xEF, 0x54, ++ 0x12, 0x74, 0x7F, 0x63, 0x1B, 0x50, 0xB4, 0x0B, 0xC4, 0xEF, 0x63, 0xAF, 0x90, 0x07, 0x54, 0x13, ++ 0xE0, 0x20, 0x0B, 0x06, 0xF0, 0x21, 0x74, 0x05, 0x81, 0x74, 0x03, 0x80, 0x23, 0x5D, 0x75, 0xF0, ++ 0xAF, 0x6B, 0x5E, 0x75, 0x54, 0xC4, 0xEF, 0x63, 0x14, 0xE0, 0x20, 0x0F, 0x34, 0x7F, 0x20, 0x7E, ++ 0x90, 0x1D, 0x0E, 0x12, 0x44, 0xE0, 0x0D, 0x06, 0x5D, 0x75, 0xF0, 0x10, 0xD2, 0x5E, 0x75, 0x24, ++ 0x23, 0x08, 0x30, 0x22, 0x40, 0x7F, 0x20, 0x7E, 0x90, 0x1D, 0x0E, 0x12, 0x44, 0xE0, 0x0D, 0x06, ++ 0x18, 0x85, 0xF0, 0x01, 0x83, 0x17, 0x85, 0x82, 0xF0, 0x40, 0x44, 0xE0, 0x44, 0xEF, 0x6B, 0xAF, ++ 0xE4, 0x6B, 0xF5, 0x40, 0x90, 0xF6, 0x89, 0x78, 0x54, 0xE0, 0xA6, 0x07, 0x60, 0x02, 0x64, 0x07, ++ 0x02, 0x5D, 0x75, 0x06, 0xAF, 0x33, 0x5E, 0x75, 0x13, 0xC3, 0xEF, 0x64, 0x85, 0x4C, 0xE0, 0x30, ++ 0x15, 0x85, 0x82, 0x16, 0xA3, 0xFE, 0xE0, 0x83, 0x14, 0x6C, 0xB5, 0xE0, 0x10, 0x6B, 0xB5, 0xEE, ++ 0xE6, 0x06, 0x89, 0x78, 0x40, 0x02, 0x94, 0xD3, 0x28, 0x5D, 0x75, 0x32, 0x22, 0x4C, 0x5E, 0x75, ++ 0xF6, 0x89, 0x78, 0xE4, 0x54, 0xEF, 0x6B, 0xAF, 0x85, 0x6B, 0xF5, 0xBF, 0x15, 0x85, 0x82, 0x16, ++ 0xA3, 0xFE, 0xE0, 0x83, 0x70, 0x6C, 0x65, 0xE0, 0x6B, 0x65, 0xEE, 0x03, 0x5D, 0x75, 0x06, 0x60, ++ 0x33, 0x5E, 0x75, 0x02, 0x44, 0xEF, 0x6B, 0xAF, 0x22, 0x6B, 0xF5, 0x40, 0x21, 0x02, 0x08, 0x20, ++ 0x7F, 0x20, 0x7E, 0xAB, 0x1D, 0x0E, 0x12, 0x48, 0x07, 0x76, 0x8A, 0x78, 0xFC, 0x24, 0x67, 0xE5, ++ 0xFE, 0x24, 0x0B, 0x60, 0x60, 0x14, 0x07, 0x60, 0x70, 0x06, 0x24, 0x07, 0x07, 0x67, 0x75, 0x33, ++ 0xC4, 0xEF, 0x6B, 0xAF, 0x30, 0x07, 0x54, 0x13, 0x6B, 0xAE, 0x28, 0xE0, 0x54, 0xEE, 0x6C, 0xAF, ++ 0x64, 0xEF, 0xFE, 0x07, 0x05, 0x70, 0x4E, 0x08, 0x80, 0x02, 0x67, 0x75, 0xAF, 0x6B, 0xAE, 0x15, ++ 0x07, 0x54, 0xEE, 0x6C, 0x0A, 0x64, 0xEF, 0xFE, 0x75, 0x07, 0x70, 0x4E, 0x02, 0x80, 0x05, 0x67, ++ 0x67, 0xE5, 0x67, 0x05, 0x3D, 0x60, 0xFD, 0x24, 0x24, 0x7D, 0x60, 0x14, 0x21, 0x02, 0x70, 0xFE, ++ 0x60, 0x05, 0x24, 0x37, 0x90, 0x41, 0x21, 0x02, 0x6B, 0xE5, 0x0A, 0x06, 0x6C, 0xE5, 0xA3, 0xF0, ++ 0xEF, 0x6B, 0xAF, 0xF0, 0x13, 0xC3, 0x20, 0x54, 0x03, 0x06, 0x90, 0xFF, 0x4F, 0xEF, 0x54, 0xE0, ++ 0x0A, 0x06, 0x90, 0xF0, 0xC4, 0x80, 0x54, 0xE0, 0x90, 0xFF, 0x0F, 0x54, 0x54, 0xE0, 0x0D, 0x06, ++ 0x80, 0xF0, 0x4F, 0xF7, 0xA6, 0x8B, 0x78, 0x5C, 0x28, 0x06, 0x90, 0x6C, 0x13, 0x13, 0xC4, 0xE0, ++ 0x90, 0xFF, 0x03, 0x54, 0xFE, 0xE0, 0xA1, 0x00, 0x00, 0x7F, 0x9F, 0xC3, 0x01, 0x7F, 0x02, 0x50, ++ 0x70, 0x00, 0x7E, 0xEE, 0xEF, 0x01, 0x7E, 0x02, 0x78, 0x36, 0x60, 0x4E, 0x08, 0x54, 0xE6, 0x8B, ++ 0x14, 0x06, 0x90, 0xFF, 0x4F, 0xF7, 0x54, 0xE0, 0x10, 0x54, 0xE6, 0xF0, 0x3F, 0x54, 0x13, 0x13, ++ 0xFB, 0x54, 0xE0, 0xFF, 0x19, 0x80, 0xF0, 0x4F, 0x6C, 0xAF, 0x6B, 0xAE, 0x78, 0x07, 0x54, 0xEE, ++ 0x08, 0xEF, 0xF6, 0x87, 0x90, 0x0A, 0x80, 0xF6, 0x6B, 0xE5, 0xB7, 0x01, 0x6C, 0xE5, 0xA3, 0xF0, ++ 0x64, 0x67, 0xE5, 0xF0, 0x90, 0x11, 0x60, 0x01, 0x6B, 0xE5, 0x10, 0x06, 0x6C, 0xE5, 0xA3, 0xF0, ++ 0x34, 0x06, 0x90, 0xF0, 0xF0, 0x20, 0x44, 0xE0, 0x50, 0x7F, 0x20, 0x7E, 0x00, 0x7C, 0x67, 0xAD, ++ 0x90, 0x0D, 0x0D, 0x12, 0x44, 0xE0, 0x0D, 0x06, 0x6B, 0xAF, 0xF0, 0x02, 0x33, 0x08, 0x54, 0xEF, ++ 0xF8, 0x54, 0x33, 0x33, 0xEE, 0x63, 0xAE, 0xFF, 0xF5, 0x4F, 0xBF, 0x54, 0xEF, 0x63, 0xAF, 0x63, ++ 0x13, 0x13, 0x13, 0xC4, 0x00, 0x7F, 0x01, 0x54, 0x7F, 0x02, 0xE0, 0x20, 0x01, 0x54, 0xEF, 0x01, ++ 0x33, 0x33, 0x33, 0xC4, 0xAE, 0xFF, 0x80, 0x54, 0x7F, 0x54, 0xEE, 0x63, 0xE5, 0x63, 0xF5, 0x4F, ++ 0x07, 0x01, 0xB4, 0x66, 0xE0, 0x08, 0x06, 0x90, 0xAF, 0xF0, 0xDF, 0x54, 0xE0, 0x30, 0xEF, 0x64, ++ 0xE6, 0x8A, 0x78, 0x09, 0x40, 0x00, 0x94, 0xD3, 0x8A, 0x78, 0x16, 0x01, 0x90, 0x3E, 0x70, 0xE6, ++ 0x13, 0xE0, 0x0D, 0x06, 0x30, 0x3F, 0x54, 0x13, 0x13, 0xE0, 0x2D, 0xE0, 0x1F, 0x54, 0x13, 0x13, ++ 0x85, 0x24, 0xE0, 0x30, 0x17, 0x85, 0x82, 0x18, 0x13, 0xC4, 0xE0, 0x83, 0x01, 0x54, 0x13, 0x13, ++ 0x90, 0x0D, 0xE0, 0x20, 0xC4, 0xE0, 0x10, 0x06, 0x54, 0x13, 0x13, 0x13, 0x07, 0xE0, 0x30, 0x01, ++ 0x75, 0x29, 0x5D, 0x75, 0x75, 0x22, 0xFE, 0x5E, 0x5E, 0x75, 0x23, 0x5D, 0x07, 0x90, 0x22, 0x6B, ++ 0x07, 0x54, 0xE0, 0xA6, 0x06, 0x60, 0x02, 0x64, 0x75, 0x02, 0x5D, 0x75, 0x08, 0x20, 0x33, 0x5E, ++ 0x7E, 0xB7, 0x61, 0x02, 0x12, 0x5C, 0x7F, 0x20, 0x78, 0xE4, 0x1D, 0x0E, 0x6B, 0xF5, 0xF6, 0x89, ++ 0x66, 0xE5, 0x6C, 0xF5, 0x64, 0x60, 0xFC, 0x24, 0x7C, 0x60, 0xFE, 0x24, 0x41, 0x02, 0x70, 0x14, ++ 0x02, 0x70, 0x14, 0xC1, 0x07, 0x24, 0xC1, 0x41, 0xBF, 0x41, 0x02, 0x60, 0xE0, 0x28, 0x06, 0x90, ++ 0x54, 0x13, 0x13, 0xC4, 0x00, 0x90, 0xFF, 0x03, 0xC3, 0xFE, 0xE0, 0xA1, 0x50, 0x00, 0x7F, 0x9F, ++ 0xEE, 0x01, 0x7F, 0x02, 0x02, 0x70, 0x00, 0x7E, 0x4E, 0xEF, 0x01, 0x7E, 0x12, 0x06, 0x90, 0xFF, ++ 0x54, 0x13, 0xC3, 0xE0, 0x54, 0xE0, 0xFE, 0x01, 0x60, 0x5F, 0x4E, 0x01, 0x02, 0x66, 0x75, 0x05, ++ 0x01, 0x90, 0x4F, 0x80, 0x13, 0xC3, 0xE0, 0xB0, 0x80, 0x02, 0xE0, 0x30, 0x08, 0x06, 0x90, 0x15, ++ 0x13, 0x13, 0xC4, 0xE0, 0x20, 0x01, 0x54, 0x13, 0x29, 0x80, 0x30, 0xE0, 0xE0, 0xB0, 0x01, 0x90, ++ 0x66, 0x75, 0x05, 0x60, 0x90, 0x2A, 0x80, 0x05, 0xC4, 0xE0, 0x08, 0x06, 0x54, 0x13, 0x13, 0x13, ++ 0x02, 0xE0, 0x20, 0x01, 0x12, 0x80, 0x0F, 0x80, 0xE0, 0x08, 0x06, 0x90, 0x13, 0x13, 0x13, 0xC4, ++ 0xE0, 0x20, 0x01, 0x54, 0x08, 0x66, 0x75, 0x05, 0x66, 0x75, 0x07, 0x80, 0x05, 0x02, 0x80, 0x07, ++ 0x24, 0x66, 0xE5, 0x66, 0x14, 0x3F, 0x60, 0xFD, 0x61, 0x61, 0x02, 0x70, 0x14, 0x14, 0x60, 0x14, ++ 0x93, 0x61, 0x02, 0x70, 0x18, 0x60, 0xFE, 0x24, 0x02, 0x60, 0x06, 0x24, 0x6F, 0x75, 0xAC, 0x61, ++ 0x75, 0x03, 0x80, 0x08, 0xF5, 0xE4, 0x0A, 0x6F, 0xEF, 0x6E, 0xAF, 0x6E, 0x0B, 0x80, 0x80, 0x44, ++ 0xE4, 0x01, 0x6F, 0x75, 0x6E, 0xAF, 0x6E, 0xF5, 0xF5, 0x7F, 0x54, 0xEF, 0xEF, 0x6E, 0xAF, 0x6E, ++ 0x6E, 0xF5, 0x20, 0x44, 0xF5, 0xE4, 0xAC, 0x61, 0x90, 0x6F, 0xF5, 0x6E, 0x54, 0xE0, 0x12, 0x06, ++ 0x0F, 0x54, 0xC4, 0x10, 0xEE, 0x6F, 0xAE, 0xFF, 0xF5, 0x4F, 0xFE, 0x54, 0x08, 0x54, 0xE0, 0x6F, ++ 0x3F, 0x54, 0x13, 0x13, 0xEE, 0x6F, 0xAE, 0xFF, 0xF5, 0x4F, 0xFD, 0x54, 0x04, 0x54, 0xE0, 0x6F, ++ 0xEE, 0x6F, 0xAE, 0xFF, 0xF5, 0x4F, 0xFB, 0x54, 0x02, 0x54, 0xE0, 0x6F, 0xE0, 0x25, 0xE0, 0x25, ++ 0xEE, 0x6F, 0xAE, 0xFF, 0xF5, 0x4F, 0xF7, 0x54, 0x01, 0x54, 0xE0, 0x6F, 0xFF, 0xF0, 0x54, 0xC4, ++ 0x54, 0xEE, 0x6F, 0xAE, 0x6F, 0xF5, 0x4F, 0xEF, 0x44, 0xEF, 0x6E, 0xAF, 0x80, 0x6E, 0xF5, 0x80, ++ 0xE6, 0x80, 0x78, 0x4B, 0x85, 0x79, 0x07, 0x54, 0x09, 0xE6, 0x08, 0xF7, 0xE6, 0x85, 0x78, 0xF7, ++ 0xE6, 0x08, 0x6E, 0xF5, 0x01, 0x90, 0x6F, 0xF5, 0x00, 0x7F, 0xE0, 0xB0, 0x01, 0x7F, 0x02, 0x60, ++ 0xE0, 0x08, 0x06, 0x90, 0x13, 0x13, 0x13, 0xC4, 0x54, 0x4F, 0x01, 0x54, 0x33, 0x33, 0xC4, 0x01, ++ 0x90, 0x0E, 0x80, 0x33, 0xF5, 0xE0, 0xAF, 0x01, 0xF5, 0xE0, 0xA3, 0x6E, 0x08, 0x06, 0x90, 0x6F, ++ 0xFF, 0x80, 0x54, 0xE0, 0x54, 0xEE, 0x6E, 0xAE, 0x6E, 0xF5, 0x4F, 0x7F, 0x66, 0x7F, 0x20, 0x7E, ++ 0x00, 0x7C, 0x66, 0xAD, 0xE5, 0x0D, 0x0D, 0x12, 0x70, 0x07, 0x64, 0x66, 0xEF, 0x20, 0xAF, 0x45, ++ 0x54, 0x13, 0x13, 0x13, 0x5B, 0xE0, 0x30, 0x1F, 0xE0, 0x0E, 0x06, 0x90, 0xE0, 0xA3, 0x6E, 0xF5, ++ 0x63, 0xAF, 0x6F, 0xF5, 0xC4, 0x80, 0x54, 0xEF, 0xAE, 0xFF, 0x0F, 0x54, 0xF7, 0x54, 0xEE, 0x6E, ++ 0x85, 0x6E, 0xF5, 0x4F, 0x17, 0x85, 0x82, 0x18, 0xF0, 0x6E, 0xE5, 0x83, 0xF0, 0x6F, 0xE5, 0xA3, ++ 0xE0, 0x0E, 0x06, 0x90, 0x13, 0x13, 0x13, 0xC4, 0xE0, 0x20, 0x01, 0x54, 0x08, 0x66, 0x75, 0x26, ++ 0x08, 0x30, 0x21, 0x80, 0xEF, 0x63, 0xAF, 0x1E, 0x54, 0xC4, 0x80, 0x54, 0x6E, 0xAE, 0xFF, 0x0F, ++ 0x4F, 0xF7, 0x54, 0xEE, 0x18, 0x85, 0x6E, 0xF5, 0x83, 0x17, 0x85, 0x82, 0xA3, 0xF0, 0x6E, 0xE5, ++ 0xAF, 0xF0, 0x6F, 0xE5, 0x13, 0xC3, 0xEF, 0x64, 0x85, 0x75, 0xE0, 0x30, 0x15, 0x85, 0x82, 0x16, ++ 0xBF, 0x54, 0xE0, 0x83, 0xA3, 0xFE, 0xE0, 0xF0, 0x70, 0x6C, 0x65, 0xE0, 0x6B, 0x65, 0xEE, 0x03, ++ 0x89, 0x78, 0x4D, 0x70, 0x94, 0xC3, 0xE6, 0x06, 0x76, 0x55, 0x40, 0x02, 0x82, 0x16, 0x85, 0x02, ++ 0xE0, 0x83, 0x15, 0x85, 0x54, 0x13, 0x13, 0x13, 0x63, 0xAE, 0xFF, 0x01, 0x13, 0x13, 0xC4, 0xEE, ++ 0x60, 0x6F, 0x01, 0x54, 0xB4, 0x66, 0xE5, 0x3B, 0x20, 0xAF, 0x0B, 0x07, 0x13, 0x13, 0x13, 0xEF, ++ 0xE0, 0x30, 0x1F, 0x54, 0x27, 0x5D, 0x75, 0x2B, 0xE5, 0xC1, 0x5E, 0x75, 0x20, 0x07, 0xB4, 0x66, ++ 0x54, 0xEF, 0x20, 0xAF, 0x90, 0x20, 0xF5, 0xF7, 0x44, 0xE0, 0x34, 0x06, 0x85, 0x22, 0xF0, 0x10, ++ 0x15, 0x85, 0x82, 0x16, 0x6B, 0xF5, 0xE0, 0x83, 0x6C, 0xF5, 0xE0, 0xA3, 0xF6, 0x89, 0x78, 0xE4, ++ 0x7E, 0x0E, 0xD2, 0x22, 0x12, 0x79, 0x7F, 0x20, 0x78, 0xE4, 0x1D, 0x0E, 0x06, 0x90, 0xF6, 0x89, ++ 0x03, 0x54, 0xE0, 0x31, 0xE6, 0x89, 0x78, 0xFF, 0x0C, 0x50, 0x9F, 0xC3, 0x81, 0x7F, 0x20, 0x7E, ++ 0x78, 0x1D, 0x0E, 0x12, 0xE6, 0x80, 0x06, 0x89, 0xE0, 0x31, 0x06, 0x90, 0x54, 0x13, 0x13, 0xC4, ++ 0x01, 0xBF, 0xFF, 0x03, 0x7F, 0x20, 0x7E, 0x07, 0x1D, 0x0E, 0x12, 0x83, 0xE0, 0x31, 0x06, 0x90, ++ 0x54, 0x13, 0x13, 0xC4, 0x03, 0xBF, 0xFF, 0x03, 0x7F, 0x20, 0x7E, 0x07, 0x1D, 0x0E, 0x12, 0x85, ++ 0xE0, 0x31, 0x06, 0x90, 0x54, 0x13, 0x13, 0x13, 0x06, 0xE0, 0x30, 0x1F, 0x87, 0x7F, 0x20, 0x7E, ++ 0x20, 0x7E, 0x04, 0x80, 0x0E, 0x12, 0x8B, 0x7F, 0x31, 0x06, 0x90, 0x1D, 0x64, 0x03, 0x54, 0xE0, ++ 0x90, 0x19, 0x70, 0x02, 0xC4, 0xE0, 0x14, 0x06, 0x03, 0x54, 0x13, 0x13, 0x7E, 0x06, 0xE0, 0x30, ++ 0x80, 0x8F, 0x7F, 0x20, 0x7F, 0x20, 0x7E, 0x04, 0x1D, 0x0E, 0x12, 0x92, 0xE0, 0x31, 0x06, 0x90, ++ 0x3F, 0x54, 0x13, 0x13, 0x7E, 0x07, 0xE0, 0x30, 0x12, 0x95, 0x7F, 0x20, 0x20, 0x7E, 0x1D, 0x0E, ++ 0x06, 0x90, 0x9A, 0x7F, 0x54, 0xC4, 0xE0, 0x31, 0x00, 0x7C, 0xFD, 0x03, 0x75, 0x0D, 0x0D, 0x12, ++ 0x5E, 0x75, 0x2D, 0x5D, 0x06, 0x90, 0x22, 0x56, 0x7F, 0x54, 0xE0, 0x14, 0xAD, 0x01, 0x90, 0xF0, ++ 0xF0, 0xFB, 0x54, 0xE0, 0x75, 0x01, 0x5F, 0x75, 0x22, 0x22, 0xC5, 0x60, 0x00, 0x00, 0x00, 0x00, ++ 0x0D, 0x92, 0x0C, 0xA2, 0x72, 0x50, 0x34, 0x80, 0x6E, 0x65, 0x76, 0x65, 0x69, 0x4C, 0x20, 0x74, ++ 0x72, 0x65, 0x6B, 0x6E, 0x72, 0x72, 0x45, 0x20, 0x09, 0x00, 0x72, 0x6F, 0x65, 0x77, 0x6F, 0x50, ++ 0x67, 0x6E, 0x69, 0x72, 0x77, 0x6F, 0x44, 0x20, 0x09, 0x00, 0x0A, 0x6E, 0x65, 0x77, 0x6F, 0x50, ++ 0x67, 0x6E, 0x69, 0x72, 0x0A, 0x70, 0x55, 0x20, 0x20, 0x90, 0x01, 0x00, 0x70, 0x93, 0xE4, 0x06, ++ 0x0D, 0xC2, 0x00, 0x01, 0x60, 0x73, 0xE5, 0x22, 0x20, 0x5D, 0x75, 0x2F, 0xD2, 0x96, 0x5E, 0x75, ++ 0x4B, 0x07, 0x90, 0x08, 0x90, 0xF0, 0xF4, 0x74, 0x24, 0x74, 0x4C, 0x07, 0x61, 0x07, 0x90, 0xF0, ++ 0xF0, 0x20, 0x44, 0xE0, 0xF0, 0x40, 0x44, 0xE0, 0xF0, 0x10, 0x44, 0xE0, 0xF0, 0xDF, 0x54, 0xE0, ++ 0xF0, 0xBF, 0x54, 0xE0, 0xF0, 0xEF, 0x54, 0xE0, 0x5E, 0x65, 0x62, 0xE5, 0x61, 0xE5, 0x04, 0x70, ++ 0x08, 0x60, 0x5D, 0x65, 0x85, 0x61, 0x5D, 0x85, 0x08, 0xD2, 0x62, 0x5E, 0x62, 0xA9, 0x61, 0xAA, ++ 0xC2, 0xEB, 0x02, 0x12, 0x08, 0x30, 0x22, 0x08, 0x7F, 0x20, 0x7E, 0x1A, 0x1D, 0x0E, 0x12, 0x1B, ++ 0xAD, 0x01, 0x90, 0xE4, 0x90, 0xF0, 0xA3, 0xF0, 0x44, 0xE0, 0xAD, 0x01, 0x90, 0xE4, 0xF0, 0x01, ++ 0xAF, 0xF0, 0xF8, 0x07, 0xE0, 0x20, 0xEF, 0x20, 0x00, 0x06, 0x90, 0x0C, 0x13, 0x13, 0x13, 0xE0, ++ 0xE0, 0x20, 0x1F, 0x54, 0x20, 0x5D, 0x75, 0x06, 0x22, 0xCC, 0x5E, 0x75, 0x2B, 0x7F, 0x20, 0x7E, ++ 0x90, 0x1D, 0x0E, 0x12, 0x54, 0xE0, 0xAD, 0x01, 0x07, 0x90, 0xF0, 0xFE, 0xF0, 0x0F, 0x74, 0xF8, ++ 0x75, 0x01, 0x5F, 0x75, 0x22, 0x22, 0xC5, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x50, 0x53, 0x41, 0x09, 0x09, 0x64, 0x25, 0x3A, 0x43, 0x47, 0x41, 0x00, 0x09, 0x64, 0x25, 0x3A, ++ 0x25, 0x3A, 0x4D, 0x00, 0x48, 0x00, 0x09, 0x64, 0x0A, 0x64, 0x25, 0x3A, 0x62, 0x41, 0x09, 0x00, ++ 0x0A, 0x74, 0x73, 0x69, 0x62, 0x41, 0x09, 0x00, 0x2D, 0x74, 0x73, 0x69, 0x69, 0x72, 0x54, 0x52, ++ 0x09, 0x00, 0x0A, 0x67, 0x74, 0x69, 0x61, 0x57, 0x45, 0x09, 0x00, 0x0A, 0x0A, 0x74, 0x69, 0x78, ++ 0x43, 0x44, 0x09, 0x00, 0x00, 0x0A, 0x30, 0x31, 0x31, 0x43, 0x44, 0x09, 0x0A, 0x30, 0x30, 0x30, ++ 0x43, 0x49, 0x09, 0x00, 0x09, 0x00, 0x0A, 0x4E, 0x0A, 0x44, 0x48, 0x54, 0x47, 0x41, 0x09, 0x00, ++ 0x09, 0x00, 0x0A, 0x43, 0x25, 0x20, 0x3A, 0x50, 0x09, 0x00, 0x0A, 0x64, 0x0A, 0x43, 0x58, 0x45, ++ 0x44, 0x41, 0x09, 0x00, 0x45, 0x42, 0x20, 0x43, 0x61, 0x00, 0x0A, 0x52, 0x64, 0x25, 0x70, 0x73, ++ 0x64, 0x25, 0x00, 0x3A, 0x00, 0x01, 0x00, 0x0A, 0x01, 0x0C, 0x01, 0x91, 0x01, 0x7B, 0x01, 0x5E, ++ 0x00, 0x0C, 0x01, 0x5E, 0xFF, 0x00, 0x00, 0x91, 0xFE, 0xF4, 0xFE, 0x6F, 0xFE, 0x85, 0xFE, 0xA2, ++ 0xFF, 0xF4, 0xFE, 0xA2, 0x00, 0x00, 0x00, 0x6F, 0x0C, 0x47, 0x06, 0x00, 0x18, 0xC8, 0x12, 0x8B, ++ 0x25, 0x19, 0x1F, 0xF8, 0x30, 0x1F, 0x2B, 0x28, 0x3C, 0xBA, 0x36, 0xFB, 0x47, 0xCE, 0x41, 0x56, ++ 0x51, 0x3F, 0x4C, 0x1C, 0x5A, 0xF5, 0x55, 0x33, 0x62, 0xD7, 0x5E, 0x82, 0x6A, 0xCF, 0x66, 0xF2, ++ 0x70, 0xCA, 0x6D, 0x6D, 0x76, 0xB5, 0x73, 0xE2, 0x7A, 0x84, 0x78, 0x41, 0x7D, 0x29, 0x7C, 0x7D, ++ 0x7F, 0x9D, 0x7E, 0x8A, 0x7F, 0xD8, 0x7F, 0x62, 0x10, 0x20, 0x00, 0xFF, 0x18, 0x28, 0x08, 0x30, ++ 0x14, 0x24, 0x04, 0x38, 0x1C, 0x2C, 0x0C, 0x34, 0x12, 0x22, 0x02, 0x3C, 0x1A, 0x2A, 0x0A, 0x32, ++ 0x16, 0x26, 0x06, 0x3A, 0x1E, 0x2E, 0x0E, 0x36, 0x11, 0x21, 0x01, 0x3E, 0x19, 0x29, 0x09, 0x31, ++ 0x15, 0x25, 0x05, 0x39, 0x1D, 0x2D, 0x0D, 0x35, 0x13, 0x23, 0x03, 0x3D, 0x1B, 0x2B, 0x0B, 0x33, ++ 0x17, 0x27, 0x07, 0x3B, 0x1F, 0x2F, 0x0F, 0x37, 0xA9, 0x50, 0xA8, 0x3F, 0xAB, 0x52, 0xAA, 0x51, ++ 0xF0, 0x8F, 0xE8, 0x53, 0xF0, 0x8B, 0xCC, 0xA4, 0xE9, 0xFC, 0x2C, 0xA4, 0x2C, 0xA4, 0xF0, 0x8E, ++ 0xED, 0xF0, 0x8A, 0xFC, 0xEA, 0xFC, 0x2C, 0xA4, 0xCD, 0xA4, 0xF0, 0x8E, 0xF0, 0x8B, 0xF0, 0xA8, ++ 0x38, 0xCC, 0x2D, 0xA4, 0xE9, 0xFD, 0xF0, 0x25, 0x2C, 0xA4, 0xF0, 0x8F, 0xFC, 0xF0, 0x35, 0xCD, ++ 0xA4, 0xF0, 0x8E, 0xEB, 0xEB, 0xF0, 0xA9, 0xFE, 0xCF, 0xA4, 0xF0, 0x8F, 0xCD, 0x2E, 0xF0, 0xC5, ++ 0x3C, 0xE4, 0xFE, 0x39, 0x2D, 0xA4, 0xEA, 0xFC, 0xFD, 0xF0, 0x35, 0xCE, 0x22, 0xFC, 0x3C, 0xE4, ++ 0x13, 0xE7, 0xA2, 0xEC, 0xFD, 0x13, 0xED, 0xFC, 0xEF, 0xFE, 0x13, 0xEE, 0xEF, 0x22, 0xFF, 0x13, ++ 0xEE, 0xFF, 0x33, 0xC3, 0x33, 0xED, 0xFE, 0x33, 0xFC, 0x33, 0xEC, 0xFD, 0x30, 0x64, 0xE5, 0x22, ++ 0x20, 0x7E, 0x32, 0xE7, 0x67, 0xAD, 0x00, 0x7F, 0x0D, 0x12, 0x00, 0x7C, 0x7F, 0x20, 0x7E, 0x0D, ++ 0x7C, 0x68, 0xAD, 0x09, 0x0D, 0x0D, 0x12, 0x00, 0x11, 0x7F, 0x20, 0x7E, 0x00, 0x7C, 0x69, 0xAD, ++ 0x7E, 0x0D, 0x0D, 0x12, 0xAD, 0x17, 0x7F, 0x20, 0x12, 0x00, 0x7C, 0x6A, 0x0B, 0x30, 0x0D, 0x0D, ++ 0xFA, 0x80, 0x00, 0x06, 0x22, 0x1F, 0x02, 0x12, 0x31, 0x0E, 0x08, 0x30, 0x70, 0x07, 0x90, 0xF0, ++ 0xF0, 0xFE, 0x54, 0xE0, 0xF0, 0x01, 0x44, 0xE0, 0x2C, 0x5D, 0x75, 0x22, 0x22, 0xAF, 0x5E, 0x75, ++ 0x6A, 0xE5, 0x9D, 0x31, 0x54, 0x33, 0x33, 0x33, 0x69, 0xE5, 0xFF, 0xF8, 0xE0, 0x54, 0x33, 0xC4, ++ 0x90, 0x68, 0x45, 0x4F, 0x7E, 0xF0, 0x00, 0x0D, 0x12, 0x00, 0x7F, 0x0D, 0x67, 0xAF, 0xCE, 0x0B, ++ 0xFF, 0x03, 0x54, 0xEF, 0xE0, 0xFA, 0x07, 0x90, 0xF0, 0x4F, 0xFC, 0x54, 0x19, 0x08, 0x30, 0x22, ++ 0x00, 0x7B, 0xF0, 0x31, 0xFD, 0xE4, 0x01, 0x7A, 0x91, 0x51, 0xFF, 0xFC, 0xAC, 0x7F, 0x00, 0x7E, ++ 0x07, 0x90, 0x5F, 0x71, 0x01, 0x44, 0xE0, 0x70, 0x71, 0x07, 0x90, 0xF0, 0x0A, 0xE0, 0x30, 0xE0, ++ 0x42, 0xF1, 0x06, 0x7F, 0x75, 0x27, 0x5D, 0x75, 0x30, 0x22, 0x95, 0x5E, 0x9D, 0x31, 0x1A, 0x08, ++ 0x00, 0x7B, 0xF2, 0x31, 0x8C, 0x51, 0x01, 0x7A, 0xAC, 0x7F, 0x00, 0x7E, 0x63, 0x75, 0x5F, 0x71, ++ 0x70, 0x07, 0x90, 0x3F, 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x71, 0x07, 0x90, 0xE4, 0x18, 0xE0, 0x30, ++ 0xE5, 0x42, 0xF1, 0xFF, 0x15, 0x0A, 0x60, 0x63, 0x70, 0x07, 0x90, 0x63, 0xF0, 0x01, 0x44, 0xE0, ++ 0x27, 0x5D, 0x75, 0x22, 0x22, 0xAF, 0x5E, 0x75, 0x00, 0x7A, 0x10, 0x7B, 0x7F, 0xFC, 0xFD, 0xE4, ++ 0x8C, 0x24, 0x8F, 0x01, 0x8A, 0x26, 0x8D, 0x25, 0xF1, 0x28, 0x8B, 0x27, 0x04, 0x29, 0x75, 0xE4, ++ 0xE4, 0x00, 0x2A, 0x75, 0xEF, 0xC3, 0xFE, 0xFF, 0x95, 0xEE, 0x28, 0x95, 0xEF, 0x55, 0x50, 0x27, ++ 0xE5, 0xFD, 0x0F, 0x54, 0x2C, 0x01, 0xB4, 0x24, 0x24, 0xE0, 0x25, 0xED, 0xE4, 0x82, 0xF5, 0x87, ++ 0x83, 0xF5, 0x20, 0x34, 0x74, 0xFC, 0x93, 0xE4, 0xE5, 0xFD, 0x93, 0x01, 0x02, 0x24, 0xFB, 0x2A, ++ 0x29, 0xE5, 0x2A, 0xF5, 0xF5, 0x00, 0x34, 0xFA, 0x8A, 0x82, 0x8B, 0x29, 0xA3, 0xF0, 0xEC, 0x83, ++ 0x19, 0x80, 0xF0, 0xED, 0x24, 0xFD, 0x2A, 0xE5, 0xE5, 0x2A, 0xF5, 0x02, 0x00, 0x34, 0xFC, 0x29, ++ 0x82, 0x8D, 0x29, 0xF5, 0x25, 0xE5, 0x83, 0x8C, 0x26, 0xE5, 0xA3, 0xF0, 0x00, 0xBF, 0x0F, 0xF0, ++ 0xA2, 0x80, 0x0E, 0x01, 0x20, 0x6B, 0xE5, 0x22, 0x20, 0x7E, 0x22, 0xE0, 0x0E, 0x12, 0x41, 0x7F, ++ 0x7B, 0x6B, 0xE5, 0x1D, 0x30, 0x00, 0x7A, 0x10, 0xFD, 0xE4, 0x05, 0xE1, 0x7D, 0x05, 0x80, 0xFC, ++ 0xE4, 0x01, 0x7C, 0x58, 0xE4, 0x91, 0x51, 0xFF, 0x20, 0x80, 0x69, 0xF5, 0x48, 0x7F, 0x20, 0x7E, ++ 0xE5, 0x1D, 0x0E, 0x12, 0x7A, 0x10, 0x7B, 0x6B, 0x05, 0xE1, 0x30, 0x00, 0x80, 0xFC, 0xFD, 0xE4, ++ 0x7C, 0xE0, 0x7D, 0x05, 0x51, 0xFF, 0xE4, 0x01, 0x01, 0x69, 0x75, 0x91, 0x2A, 0x12, 0xF2, 0x31, ++ 0x70, 0x07, 0x90, 0x84, 0xF0, 0x01, 0x44, 0xE0, 0x75, 0x2E, 0x5D, 0x75, 0xE4, 0x22, 0x64, 0x5E, ++ 0xFB, 0xEF, 0xFC, 0xFD, 0xEE, 0xFF, 0x02, 0x24, 0xFE, 0x00, 0x34, 0xFA, 0x83, 0x8A, 0x82, 0x8B, ++ 0xF0, 0xA3, 0xF0, 0xE4, 0x01, 0x00, 0xBD, 0x0D, 0x80, 0x64, 0xED, 0x0C, 0x22, 0xE3, 0x70, 0x4C, ++ 0xE0, 0x70, 0x07, 0x90, 0x7E, 0xF0, 0xFE, 0x54, 0x71, 0x00, 0x7F, 0x05, 0x7F, 0x00, 0x7E, 0x5F, ++ 0x7D, 0x05, 0x7C, 0xAC, 0x8F, 0x23, 0x8E, 0x00, 0x8D, 0x25, 0x8C, 0x24, 0xAD, 0x9C, 0xD1, 0x26, ++ 0xAF, 0x25, 0xAC, 0x26, 0x8E, 0x23, 0xAE, 0x24, 0x8C, 0x28, 0x8F, 0x27, 0x75, 0x2A, 0x8D, 0x29, ++ 0x31, 0x75, 0x00, 0x30, 0x00, 0x32, 0x75, 0x40, 0xD3, 0x01, 0x33, 0x75, 0x40, 0x94, 0x33, 0xE5, ++ 0x00, 0x94, 0x32, 0xE5, 0x7E, 0xC1, 0x02, 0x40, 0xF5, 0x2E, 0xF5, 0xE4, 0xC3, 0x2C, 0xF5, 0x2B, ++ 0x31, 0x95, 0x2C, 0xE5, 0x40, 0x30, 0x95, 0xE4, 0xE4, 0x66, 0xC1, 0x02, 0xE5, 0xC3, 0x2D, 0xF5, ++ 0xE4, 0x33, 0x95, 0x2D, 0x02, 0x40, 0x32, 0x95, 0x2E, 0xE5, 0x5A, 0xC1, 0x2F, 0xF5, 0x33, 0x25, ++ 0x3C, 0xB4, 0x2E, 0xE5, 0xB4, 0x2F, 0xE5, 0x0B, 0x23, 0xF1, 0x06, 0x3D, 0x3D, 0x8F, 0x3C, 0x8E, ++ 0x3C, 0x8E, 0x23, 0xF1, 0x2F, 0xAD, 0x3D, 0x8F, 0x3E, 0x8E, 0x25, 0xF1, 0x2E, 0xAD, 0x3F, 0x8F, ++ 0x29, 0xAE, 0x2A, 0xAF, 0x38, 0x8E, 0x29, 0xF1, 0x2F, 0xAD, 0x39, 0x8F, 0x29, 0xAE, 0x2A, 0xAF, ++ 0x3A, 0x8E, 0x29, 0xF1, 0x2B, 0xE5, 0x3B, 0x8F, 0x40, 0x20, 0x94, 0xD3, 0x95, 0x40, 0x74, 0x37, ++ 0x24, 0xE0, 0x25, 0x2B, 0xE4, 0x82, 0xF5, 0xA7, 0x83, 0xF5, 0x20, 0x34, 0x36, 0xF5, 0x93, 0xE4, ++ 0xF5, 0x93, 0x01, 0x74, 0x25, 0x2B, 0xE5, 0x37, 0xF5, 0x67, 0x24, 0xE0, 0x20, 0x34, 0xE4, 0x82, ++ 0x93, 0xE4, 0x83, 0xF5, 0x93, 0x01, 0x74, 0xFE, 0x9F, 0xE4, 0xC3, 0xFF, 0x9E, 0xE4, 0x35, 0xF5, ++ 0x2F, 0x80, 0x34, 0xF5, 0xE0, 0x25, 0x2B, 0xE5, 0x82, 0xF5, 0xA7, 0x24, 0xF5, 0x20, 0x34, 0xE4, ++ 0xF5, 0x93, 0xE4, 0x83, 0x93, 0x01, 0x74, 0x36, 0x74, 0xC3, 0x37, 0xF5, 0x25, 0x2B, 0x95, 0x20, ++ 0xF5, 0xA7, 0x24, 0xE0, 0x20, 0x34, 0xE4, 0x82, 0x93, 0xE4, 0x83, 0xF5, 0x01, 0x74, 0x34, 0xF5, ++ 0xAE, 0x35, 0xF5, 0x93, 0xEE, 0x3B, 0xAF, 0x3A, 0xFD, 0xE0, 0x95, 0x33, 0xAE, 0x06, 0xC0, 0xFC, ++ 0x95, 0x33, 0xEE, 0x36, 0x53, 0x37, 0x85, 0xE0, 0x51, 0xF5, 0x52, 0x8E, 0x06, 0xD0, 0x50, 0xF5, ++ 0x04, 0xC0, 0x29, 0x31, 0x06, 0xC0, 0x05, 0xC0, 0x3E, 0xAE, 0x07, 0xC0, 0x33, 0xEE, 0x3F, 0xAF, ++ 0xFC, 0xFD, 0xE0, 0x95, 0x34, 0xAE, 0x06, 0xC0, 0xE0, 0x95, 0x33, 0xEE, 0x8E, 0x53, 0x35, 0x85, ++ 0xF5, 0x51, 0xF5, 0x52, 0x31, 0x06, 0xD0, 0x50, 0xD0, 0x03, 0xD0, 0x29, 0xD0, 0x01, 0xD0, 0x02, ++ 0xF5, 0x2B, 0xEF, 0x00, 0xF5, 0x3A, 0xEE, 0x43, 0xF5, 0x39, 0xED, 0x42, 0xF5, 0x38, 0xEC, 0x41, ++ 0xAF, 0x3E, 0xAE, 0x40, 0x95, 0x33, 0xEE, 0x3F, 0xC0, 0xFC, 0xFD, 0xE0, 0xEE, 0x36, 0xAE, 0x06, ++ 0x85, 0xE0, 0x95, 0x33, 0x52, 0x8E, 0x53, 0x37, 0x50, 0xF5, 0x51, 0xF5, 0x29, 0x31, 0x06, 0xD0, ++ 0x05, 0xC0, 0x04, 0xC0, 0x07, 0xC0, 0x06, 0xC0, 0x3B, 0xAF, 0x3A, 0xAE, 0xE0, 0x95, 0x33, 0xEE, ++ 0x06, 0xC0, 0xFC, 0xFD, 0x33, 0xEE, 0x34, 0xAE, 0x35, 0x85, 0xE0, 0x95, 0xF5, 0x52, 0x8E, 0x53, ++ 0xD0, 0x50, 0xF5, 0x51, 0xD0, 0x29, 0x31, 0x06, 0xD0, 0x02, 0xD0, 0x03, 0xC3, 0x00, 0xD0, 0x01, ++ 0x47, 0xF5, 0x9B, 0xEF, 0x46, 0xF5, 0x9A, 0xEE, 0x45, 0xF5, 0x99, 0xED, 0x44, 0xF5, 0x98, 0xEC, ++ 0xF5, 0x4A, 0xF5, 0xE4, 0x48, 0x3C, 0x85, 0x4B, 0xAF, 0x49, 0x3D, 0x85, 0xAD, 0x4A, 0xAE, 0x4B, ++ 0x31, 0x48, 0xAC, 0x49, 0x8E, 0x4B, 0x8F, 0x80, 0x8C, 0x49, 0x8D, 0x4A, 0x25, 0x4B, 0xE5, 0x48, ++ 0xE5, 0x4B, 0xF5, 0x43, 0xF5, 0x42, 0x35, 0x4A, 0x35, 0x49, 0xE5, 0x4A, 0xE5, 0x49, 0xF5, 0x41, ++ 0xF5, 0x40, 0x35, 0x48, 0xAA, 0x49, 0xAB, 0x48, 0xAF, 0x2E, 0xAD, 0x48, 0xD1, 0x27, 0xAE, 0x28, ++ 0x4A, 0xF5, 0xE4, 0x83, 0x3C, 0x85, 0x4B, 0xF5, 0x49, 0x3D, 0x85, 0x48, 0x4A, 0xAE, 0x4B, 0xAF, ++ 0x48, 0xAC, 0x49, 0xAD, 0x4B, 0x8F, 0x80, 0x31, 0x49, 0x8D, 0x4A, 0x8E, 0xE5, 0xC3, 0x48, 0x8C, ++ 0xF5, 0x43, 0x95, 0x4B, 0x95, 0x4A, 0xE5, 0x4B, 0xE5, 0x4A, 0xF5, 0x42, 0xF5, 0x41, 0x95, 0x49, ++ 0x95, 0x48, 0xE5, 0x49, 0xAB, 0x48, 0xF5, 0x40, 0xAD, 0x48, 0xAA, 0x49, 0xAE, 0x28, 0xAF, 0x2F, ++ 0xE4, 0x83, 0xD1, 0x27, 0x4B, 0xF5, 0x4A, 0xF5, 0x85, 0x48, 0x38, 0x85, 0x4B, 0xAF, 0x49, 0x39, ++ 0x49, 0xAD, 0x4A, 0xAE, 0x80, 0x31, 0x48, 0xAC, 0x4A, 0x8E, 0x4B, 0x8F, 0x48, 0x8C, 0x49, 0x8D, ++ 0x47, 0x25, 0x4B, 0xE5, 0x4A, 0xE5, 0x4B, 0xF5, 0x4A, 0xF5, 0x46, 0x35, 0x45, 0x35, 0x49, 0xE5, ++ 0x48, 0xE5, 0x49, 0xF5, 0x48, 0xF5, 0x44, 0x35, 0x48, 0xAA, 0x49, 0xAB, 0x7F, 0xD1, 0x2E, 0xAD, ++ 0xF5, 0x4A, 0xF5, 0xE4, 0x48, 0x38, 0x85, 0x4B, 0xAF, 0x49, 0x39, 0x85, 0xAD, 0x4A, 0xAE, 0x4B, ++ 0x31, 0x48, 0xAC, 0x49, 0x8E, 0x4B, 0x8F, 0x80, 0x8C, 0x49, 0x8D, 0x4A, 0x4B, 0xE5, 0xC3, 0x48, ++ 0x4B, 0xF5, 0x47, 0x95, 0x46, 0x95, 0x4A, 0xE5, 0x49, 0xE5, 0x4A, 0xF5, 0x49, 0xF5, 0x45, 0x95, ++ 0x44, 0x95, 0x48, 0xE5, 0x49, 0xAB, 0x48, 0xF5, 0x2F, 0xAD, 0x48, 0xAA, 0x2E, 0x05, 0x7F, 0xD1, ++ 0x2B, 0x25, 0x31, 0xE5, 0x2D, 0x05, 0x2B, 0xF5, 0x2F, 0xE5, 0xDE, 0x61, 0xE4, 0x2E, 0xF5, 0x04, ++ 0x2C, 0x05, 0x2B, 0xF5, 0x30, 0xE5, 0xCF, 0x61, 0x30, 0xF5, 0x13, 0xC3, 0xF5, 0x13, 0x31, 0xE5, ++ 0x25, 0x33, 0xE5, 0x31, 0xE5, 0x33, 0xF5, 0xE0, 0x32, 0xF5, 0x33, 0x32, 0xAF, 0x22, 0xBB, 0x61, ++ 0x8F, 0x29, 0xAE, 0x2A, 0xED, 0x83, 0x8E, 0x82, 0xA4, 0x02, 0xF0, 0x75, 0x82, 0xF5, 0x82, 0x25, ++ 0x83, 0x35, 0xF0, 0xE5, 0xF0, 0xEA, 0x83, 0xF5, 0x22, 0xF0, 0xEB, 0xA3, 0x28, 0x8F, 0x27, 0x8E, ++ 0x2A, 0x8D, 0x29, 0x8C, 0xD2, 0x01, 0x2D, 0x75, 0x11, 0x0C, 0x30, 0x0C, 0xE5, 0x2B, 0x2D, 0x85, ++ 0xE9, 0x20, 0x90, 0x2D, 0xF5, 0xE0, 0x25, 0x93, 0x80, 0x0C, 0xC2, 0x2C, 0x25, 0x40, 0x74, 0x0A, ++ 0x05, 0x2B, 0xF5, 0x2B, 0xE5, 0x0C, 0xD2, 0x2C, 0x2B, 0x95, 0xD3, 0x2C, 0x2B, 0xAD, 0x48, 0x40, ++ 0x2E, 0x8E, 0x25, 0xF1, 0x2C, 0xAD, 0x2F, 0x8F, 0x06, 0xAA, 0x25, 0xF1, 0x2B, 0xAD, 0x07, 0xAB, ++ 0x27, 0xAE, 0x28, 0xAF, 0x2F, 0xAB, 0x83, 0xD1, 0x2C, 0xAD, 0x2E, 0xAA, 0x27, 0xAE, 0x28, 0xAF, ++ 0x2B, 0xAD, 0x83, 0xD1, 0x29, 0xAE, 0x2A, 0xAF, 0x2E, 0x8E, 0x29, 0xF1, 0x2C, 0xAD, 0x2F, 0x8F, ++ 0x29, 0xAE, 0x2A, 0xAF, 0x06, 0xAA, 0x29, 0xF1, 0x2B, 0xAD, 0x07, 0xAB, 0x2F, 0xAB, 0x7F, 0xD1, ++ 0x2C, 0xAD, 0x2E, 0xAA, 0x0C, 0x30, 0x7F, 0xD1, 0xE5, 0x2D, 0x05, 0x90, 0x40, 0x94, 0xC3, 0x2D, ++ 0xAD, 0x22, 0x85, 0x40, 0xAE, 0x28, 0xAF, 0x2E, 0x8E, 0x82, 0x8F, 0x27, 0xF0, 0x75, 0xED, 0x83, ++ 0x82, 0x25, 0xA4, 0x02, 0xF0, 0xE5, 0x82, 0xF5, 0x83, 0xF5, 0x83, 0x35, 0xE0, 0xA3, 0xFE, 0xE0, ++ 0x07, 0xAD, 0x22, 0xFF, 0xE0, 0x70, 0x07, 0x90, 0xE4, 0xF0, 0xFE, 0x54, 0xE0, 0x25, 0xEC, 0xFC, ++ 0x82, 0xF5, 0x00, 0x24, 0xF5, 0x05, 0x34, 0xE4, 0xA3, 0xFE, 0xE0, 0x83, 0x08, 0x05, 0xA8, 0xE0, ++ 0x33, 0xC3, 0x05, 0x80, 0xD8, 0xCE, 0x33, 0xCE, 0x25, 0xEC, 0xFF, 0xF9, 0xF5, 0xAC, 0x24, 0xE0, ++ 0x00, 0x34, 0xE4, 0x82, 0xFA, 0xE0, 0x83, 0xF5, 0xFF, 0x2F, 0xE0, 0xA3, 0xEC, 0xFE, 0x3E, 0xEA, ++ 0xAC, 0x24, 0xE0, 0x25, 0x34, 0xE4, 0x82, 0xF5, 0xEE, 0x83, 0xF5, 0x00, 0xF0, 0xEF, 0xA3, 0xF0, ++ 0xB9, 0x80, 0xBC, 0x0C, 0x12, 0x80, 0x71, 0x22, 0x67, 0xE5, 0xFD, 0x29, 0x40, 0x03, 0x94, 0xD3, ++ 0x2E, 0x5D, 0x75, 0x07, 0x22, 0xA0, 0x5E, 0x75, 0x75, 0x22, 0x5D, 0x75, 0x71, 0x22, 0x1D, 0x5E, ++ 0x09, 0x28, 0x12, 0x80, 0x94, 0xD3, 0x67, 0xE5, 0x75, 0x07, 0x40, 0x03, 0x5E, 0x75, 0x2A, 0x5D, ++ 0x5D, 0x75, 0x22, 0xAC, 0x4B, 0x5E, 0x75, 0x22, 0x0A, 0x08, 0x30, 0x22, 0x74, 0x78, 0x9D, 0x31, ++ 0x76, 0x08, 0x00, 0x76, 0x74, 0x7F, 0x22, 0x0E, 0x50, 0xB4, 0x0B, 0x12, 0x2E, 0x5D, 0x75, 0x06, ++ 0x22, 0xD3, 0x5E, 0x75, 0xE0, 0x73, 0x07, 0x90, 0x74, 0x07, 0x90, 0xFC, 0x90, 0xE4, 0xFE, 0xE0, ++ 0x90, 0xF0, 0x73, 0x07, 0x90, 0xF0, 0x74, 0x07, 0x54, 0xE0, 0x70, 0x07, 0x07, 0x90, 0xF0, 0xFE, ++ 0x90, 0xF0, 0xEC, 0x73, 0xF0, 0xEE, 0x74, 0x07, 0x70, 0x69, 0xE5, 0x22, 0xAF, 0x6C, 0xAE, 0x1F, ++ 0x10, 0x24, 0xEF, 0x6D, 0x3E, 0xE4, 0x24, 0xF5, 0x67, 0x05, 0x23, 0xF5, 0x6D, 0x25, 0x28, 0x74, ++ 0x35, 0xE4, 0x6D, 0xF5, 0x75, 0x6C, 0xF5, 0x6C, 0x24, 0x80, 0x01, 0x69, 0x6C, 0xAE, 0x6A, 0xE5, ++ 0x0E, 0x70, 0x6D, 0xAF, 0xF5, 0x15, 0x24, 0xEF, 0xF5, 0x3E, 0xE4, 0x24, 0x03, 0x6A, 0x75, 0x23, ++ 0x24, 0xEF, 0x0E, 0x80, 0xE4, 0x24, 0xF5, 0x1A, 0xE4, 0x23, 0xF5, 0x3E, 0x69, 0xF5, 0x6A, 0xF5, ++ 0xD5, 0x11, 0xFF, 0xE4, 0x08, 0x7F, 0x07, 0xC0, 0x07, 0xC0, 0xD5, 0x11, 0xD5, 0x11, 0x10, 0x7F, ++ 0x18, 0x7F, 0x07, 0xC0, 0x07, 0xC0, 0xD5, 0x11, 0xD5, 0x11, 0x20, 0x7F, 0x30, 0xD0, 0x31, 0x8F, ++ 0x03, 0xD0, 0x2F, 0xD0, 0x24, 0xAF, 0x05, 0xD0, 0x2B, 0x8E, 0x23, 0xAE, 0x2C, 0x05, 0x2C, 0x8F, ++ 0x02, 0x70, 0x2C, 0xE5, 0xF5, 0x14, 0x2B, 0x05, 0xED, 0x83, 0x8E, 0x82, 0xE5, 0x2C, 0x05, 0xF0, ++ 0x70, 0x2B, 0xAE, 0x2C, 0x14, 0x2B, 0x05, 0x02, 0x83, 0x8E, 0x82, 0xF5, 0x2C, 0x05, 0xF0, 0xEB, ++ 0x2B, 0xAE, 0x2C, 0xE5, 0x2B, 0x05, 0x02, 0x70, 0x8E, 0x82, 0xF5, 0x14, 0xF0, 0x2F, 0xE5, 0x83, ++ 0x2C, 0xE5, 0x2C, 0x05, 0x02, 0x70, 0x2B, 0xAE, 0xF5, 0x14, 0x2B, 0x05, 0xE5, 0x83, 0x8E, 0x82, ++ 0x2C, 0x05, 0xF0, 0x30, 0x2B, 0xAE, 0x2C, 0xE5, 0x2B, 0x05, 0x02, 0x70, 0x8E, 0x82, 0xF5, 0x14, ++ 0xF0, 0x31, 0xE5, 0x83, 0xEF, 0x2B, 0x8F, 0x22, 0xAC, 0x24, 0xE0, 0x25, 0x34, 0xE4, 0x82, 0xF5, ++ 0xE0, 0x83, 0xF5, 0x00, 0xFB, 0xE0, 0xA3, 0xFE, 0xEE, 0xFF, 0x06, 0xAA, 0xFD, 0xE0, 0x95, 0x33, ++ 0xC0, 0x06, 0xC0, 0xFC, 0x95, 0x33, 0xEE, 0x07, 0x8E, 0x53, 0x8F, 0xE0, 0xF5, 0x51, 0xF5, 0x52, ++ 0xD0, 0x07, 0xD0, 0x50, 0x29, 0x21, 0x12, 0x06, 0x2E, 0x8E, 0x2F, 0x8F, 0x2C, 0x8C, 0x2D, 0x8D, ++ 0xE0, 0x25, 0x2B, 0xE5, 0x82, 0xF5, 0x00, 0x24, 0xF5, 0x05, 0x34, 0xE4, 0xA3, 0xFA, 0xE0, 0x83, ++ 0xAE, 0xFF, 0xFB, 0xE0, 0x95, 0x33, 0xEE, 0x02, 0xC0, 0xFC, 0xFD, 0xE0, 0xEE, 0x07, 0xC0, 0x06, ++ 0x8F, 0xE0, 0x95, 0x33, 0xF5, 0x52, 0x8E, 0x53, 0xD0, 0x50, 0xF5, 0x51, 0x12, 0x06, 0xD0, 0x07, ++ 0x2F, 0xE5, 0x29, 0x21, 0xE5, 0x2F, 0xF5, 0x2F, 0x2E, 0xF5, 0x3E, 0x2E, 0xF5, 0x3D, 0x2D, 0xE5, ++ 0x3C, 0x2C, 0xE5, 0x2D, 0x2F, 0xAF, 0x2C, 0xF5, 0x2D, 0xAD, 0x2E, 0xAE, 0x1F, 0x30, 0x75, 0xFC, ++ 0x33, 0x8E, 0x34, 0x8F, 0x31, 0x8C, 0x32, 0x8D, 0x32, 0x45, 0x31, 0xE5, 0x42, 0x33, 0xE5, 0xFF, ++ 0x42, 0x34, 0xE5, 0x07, 0x09, 0x70, 0xEF, 0x07, 0xF5, 0x01, 0x34, 0x75, 0xF5, 0x32, 0xF5, 0x33, ++ 0x20, 0x31, 0xE5, 0x31, 0x30, 0x15, 0x17, 0xE7, 0x33, 0xAE, 0x34, 0xAF, 0x31, 0xAC, 0x32, 0xAD, ++ 0x8F, 0x8F, 0x21, 0x12, 0x8D, 0x33, 0x8E, 0x34, 0x80, 0x31, 0x8C, 0x32, 0x7E, 0x31, 0xAF, 0xE4, ++ 0xE5, 0xFB, 0xE4, 0x00, 0xF5, 0xE0, 0x25, 0x30, 0xAC, 0x07, 0xAD, 0x30, 0x84, 0x02, 0x12, 0x06, ++ 0x07, 0xE7, 0x30, 0xEE, 0x7E, 0xFF, 0x30, 0x05, 0xEF, 0x0B, 0x80, 0x00, 0xC3, 0xCE, 0x07, 0x78, ++ 0xD8, 0x13, 0xCE, 0x13, 0xBB, 0x0B, 0xFF, 0xF9, 0x30, 0xAF, 0xD9, 0x03, 0xFE, 0xFD, 0xFC, 0xE4, ++ 0x75, 0xA8, 0x53, 0x75, 0x51, 0xF5, 0xC0, 0x52, 0x21, 0x12, 0x50, 0xF5, 0x8E, 0x34, 0x8F, 0x29, ++ 0x8C, 0x32, 0x8D, 0x33, 0x34, 0x25, 0xE4, 0x31, 0x33, 0xE5, 0x34, 0xF5, 0x33, 0xF5, 0x80, 0x34, ++ 0xF5, 0x32, 0x35, 0xE4, 0x31, 0x35, 0xE4, 0x32, 0x32, 0xAF, 0x31, 0xF5, 0xFF, 0x24, 0x75, 0x22, ++ 0xF5, 0x25, 0xF5, 0xE4, 0x75, 0x27, 0xF5, 0x26, 0x23, 0xAF, 0x01, 0x23, 0x28, 0x8F, 0xD5, 0x11, ++ 0x95, 0xC3, 0x28, 0xE5, 0x85, 0x03, 0x50, 0x24, 0x28, 0xE5, 0x24, 0x28, 0x40, 0x25, 0x95, 0xD3, ++ 0x25, 0x28, 0x85, 0x03, 0x27, 0x25, 0x28, 0xE5, 0x35, 0xE4, 0x27, 0xF5, 0x05, 0x26, 0xF5, 0x26, ++ 0xC3, 0x23, 0xE5, 0x23, 0xD2, 0x40, 0x40, 0x94, 0x6C, 0xAE, 0x68, 0xE5, 0x09, 0x70, 0x6D, 0xAF, ++ 0x2A, 0x8F, 0x29, 0x8E, 0x80, 0x07, 0x68, 0x75, 0x04, 0x24, 0xEF, 0x19, 0x3E, 0xE4, 0x2A, 0xF5, ++ 0xF5, 0xE4, 0x29, 0xF5, 0x74, 0x67, 0x05, 0x68, 0xF5, 0x6D, 0x25, 0x28, 0x6C, 0x35, 0xE4, 0x6D, ++ 0xFF, 0xE4, 0x6C, 0xF5, 0x30, 0x8F, 0xD5, 0x11, 0x26, 0xAE, 0x27, 0xE5, 0xC3, 0xCE, 0x06, 0x78, ++ 0xD8, 0x13, 0xCE, 0x13, 0xE4, 0x2F, 0xF5, 0xF9, 0x24, 0xAB, 0x31, 0xF5, 0x2A, 0xAF, 0x25, 0xAD, ++ 0x7A, 0x01, 0x29, 0xAE, 0xE0, 0x70, 0x07, 0x90, 0xE0, 0xF0, 0xFE, 0x54, 0x04, 0x44, 0xF9, 0x54, ++ 0x72, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x74, 0xE0, 0x73, 0x07, 0x07, 0x90, 0xF0, 0xFF, ++ 0x0F, 0x74, 0xE0, 0x74, 0x75, 0x07, 0x90, 0xF0, 0x22, 0xF0, 0xE4, 0xE0, 0x5D, 0x7F, 0x20, 0x7E, ++ 0xE4, 0x1D, 0x0E, 0x12, 0x68, 0x75, 0x67, 0xF5, 0x01, 0x69, 0x75, 0x07, 0x75, 0x03, 0x6A, 0x75, ++ 0x6D, 0x75, 0x00, 0x6C, 0xAF, 0x6C, 0xAE, 0x00, 0x08, 0x24, 0xEF, 0x6D, 0x3E, 0xE4, 0x66, 0xF5, ++ 0x08, 0x90, 0x65, 0xF5, 0xF0, 0x03, 0x74, 0x3C, 0x90, 0xF0, 0x01, 0x74, 0x90, 0xF0, 0x47, 0x08, ++ 0x90, 0xF0, 0x48, 0x08, 0x0E, 0x74, 0x4B, 0x08, 0x4A, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, ++ 0xF0, 0x04, 0x4C, 0x08, 0x7F, 0x88, 0x22, 0x12, 0x71, 0x00, 0x7E, 0x42, 0x75, 0x84, 0x51, 0x06, ++ 0x5E, 0x75, 0x21, 0x5D, 0x24, 0x8E, 0x22, 0xD8, 0x27, 0x12, 0x25, 0x8F, 0x04, 0x26, 0x75, 0xE4, ++ 0xE4, 0x00, 0x27, 0x75, 0x29, 0xF5, 0x28, 0xF5, 0x85, 0x82, 0x27, 0x85, 0xF5, 0xE0, 0x83, 0x26, ++ 0xF5, 0xE0, 0xA3, 0x2A, 0xFF, 0x2A, 0xAE, 0x2B, 0xE0, 0x95, 0x33, 0xEE, 0x85, 0xE4, 0xFC, 0xFD, ++ 0x24, 0x85, 0x53, 0x25, 0xF5, 0x51, 0xF5, 0x52, 0x29, 0x21, 0x12, 0x50, 0x2F, 0x8E, 0x30, 0x8F, ++ 0x2D, 0x8C, 0x2E, 0x8D, 0xE5, 0x2C, 0xF5, 0xE4, 0x03, 0xE7, 0x30, 0x30, 0x85, 0x01, 0x2C, 0x75, ++ 0x2E, 0x85, 0x30, 0x2F, 0xE5, 0x00, 0x7E, 0x2F, 0xF5, 0x2C, 0x25, 0x30, 0x2F, 0x35, 0xEE, 0x2B, ++ 0x27, 0xE5, 0x2A, 0xF5, 0xF5, 0x02, 0x24, 0xFF, 0xFE, 0x26, 0xE5, 0x27, 0x26, 0xF5, 0x00, 0x34, ++ 0x83, 0x8E, 0x82, 0x8F, 0xA3, 0xF0, 0x2A, 0xE5, 0x05, 0xF0, 0x2B, 0xE5, 0x70, 0x29, 0xE5, 0x29, ++ 0xC3, 0x28, 0x05, 0x02, 0x28, 0xE5, 0x10, 0x94, 0x8C, 0x40, 0x00, 0x94, 0x4E, 0x08, 0x90, 0x22, ++ 0xE5, 0x23, 0xF5, 0xE0, 0x0B, 0xE7, 0x30, 0x64, 0x63, 0x7F, 0x20, 0x7E, 0x00, 0x7C, 0x23, 0xAD, ++ 0x05, 0x0D, 0x0D, 0x12, 0xAE, 0x66, 0xE5, 0x66, 0x05, 0x02, 0x70, 0x65, 0x82, 0xF5, 0x14, 0x65, ++ 0x23, 0xE5, 0x83, 0x8E, 0x70, 0x68, 0xE5, 0xF0, 0x07, 0x68, 0x75, 0x26, 0x28, 0x74, 0x67, 0x05, ++ 0x6D, 0xF5, 0x6D, 0x25, 0xF5, 0x6C, 0x35, 0xE4, 0xAF, 0x6C, 0xAE, 0x6C, 0x08, 0x24, 0xEF, 0x6D, ++ 0x3E, 0xE4, 0x66, 0xF5, 0x22, 0x12, 0x65, 0xF5, 0x7E, 0x42, 0x7F, 0x88, 0x15, 0x06, 0x80, 0x00, ++ 0x7E, 0x42, 0x7F, 0x68, 0x7E, 0x06, 0x61, 0x01, 0x12, 0x71, 0x7F, 0x20, 0xF5, 0xE4, 0x1D, 0x0E, ++ 0x01, 0x69, 0x75, 0x68, 0x21, 0x12, 0x6A, 0xF5, 0x3A, 0x06, 0x90, 0xF2, 0xA3, 0x04, 0x70, 0xE0, ++ 0x60, 0xAA, 0x64, 0xE0, 0x3A, 0x06, 0x90, 0x17, 0x40, 0xF0, 0x75, 0xE0, 0xF7, 0x7B, 0x79, 0xA4, ++ 0xF7, 0x19, 0xF0, 0xE5, 0x09, 0x90, 0xE0, 0xA3, 0x0D, 0x80, 0xF0, 0xE1, 0x27, 0x76, 0x7A, 0x78, ++ 0x90, 0x00, 0x76, 0x08, 0x10, 0x74, 0xE1, 0x09, 0x78, 0x78, 0xE4, 0xF0, 0x90, 0xF6, 0x08, 0xF6, ++ 0x90, 0xF0, 0xDF, 0x09, 0x85, 0x74, 0xDB, 0x09, 0xF0, 0x81, 0x74, 0xF0, 0x74, 0xDC, 0x09, 0x90, ++ 0x90, 0xE4, 0xF0, 0x01, 0x90, 0xF0, 0xE0, 0x09, 0x90, 0xF0, 0xF9, 0x07, 0xE4, 0x74, 0xFA, 0x07, ++ 0x38, 0x06, 0x90, 0xF0, 0xA3, 0x02, 0x70, 0xE0, 0x51, 0x2A, 0x60, 0xE0, 0x88, 0x22, 0x12, 0x84, ++ 0xE0, 0x39, 0x06, 0x90, 0x71, 0x00, 0x7E, 0xFF, 0x70, 0x07, 0x90, 0x06, 0xF0, 0x01, 0x44, 0xE0, ++ 0xE0, 0x38, 0x06, 0x90, 0x90, 0x0E, 0xE0, 0x30, 0x44, 0xE0, 0x00, 0x0D, 0x00, 0x7F, 0xF0, 0x18, ++ 0x0B, 0x12, 0x0D, 0x7E, 0xD2, 0x09, 0x90, 0xCE, 0x90, 0xF0, 0x05, 0x74, 0xFF, 0x74, 0xDD, 0x09, ++ 0x77, 0x78, 0xE4, 0xF0, 0xE6, 0x77, 0x78, 0xF6, 0x7C, 0x24, 0xE0, 0x25, 0x08, 0xF6, 0xE4, 0xF8, ++ 0x06, 0x77, 0x78, 0xF6, 0xED, 0x04, 0xB4, 0xE6, 0x75, 0x2F, 0x5D, 0x75, 0x71, 0x22, 0x69, 0x5E, ++ 0xD3, 0x67, 0xE5, 0x8D, 0x07, 0x40, 0x03, 0x94, 0x75, 0x2E, 0x5D, 0x75, 0xE5, 0x22, 0xBC, 0x5E, ++ 0x06, 0xE7, 0x30, 0x64, 0x00, 0x03, 0x0B, 0x30, 0x5D, 0x75, 0xFA, 0x80, 0xD8, 0x5E, 0x75, 0x21, ++ 0x60, 0x73, 0xE5, 0x22, 0x7F, 0x20, 0x7E, 0x1B, 0x1D, 0x0E, 0x12, 0x1D, 0x75, 0x2D, 0x5D, 0x75, ++ 0x08, 0xD2, 0x55, 0x5E, 0xE0, 0xAD, 0x01, 0x90, 0xE4, 0xF0, 0x08, 0x44, 0x32, 0x04, 0x12, 0xFF, ++ 0xE0, 0x12, 0x06, 0x90, 0x07, 0x54, 0x13, 0xC4, 0x0E, 0x70, 0x07, 0x64, 0x20, 0xEF, 0x20, 0xAF, ++ 0x20, 0xAF, 0x08, 0xE0, 0x30, 0x13, 0xC3, 0xEF, 0x5D, 0x75, 0x06, 0xE0, 0x76, 0x5E, 0x75, 0x2E, ++ 0xE0, 0x13, 0x06, 0x90, 0x19, 0x60, 0x64, 0x65, 0x25, 0x7F, 0x20, 0x7E, 0x75, 0x1D, 0x0E, 0x12, ++ 0x5E, 0x75, 0x2D, 0x5D, 0x13, 0x06, 0x90, 0x55, 0x54, 0xED, 0xFD, 0xE0, 0xF5, 0xE0, 0xF0, 0xBF, ++ 0x65, 0x62, 0xE5, 0x64, 0xE5, 0x04, 0x70, 0x5E, 0x60, 0x5D, 0x65, 0x61, 0x61, 0x5D, 0x85, 0x08, ++ 0xD2, 0x62, 0x5E, 0x85, 0x13, 0x06, 0x90, 0x08, 0xAA, 0x64, 0xF5, 0xE0, 0x12, 0x62, 0xA9, 0x61, ++ 0x08, 0xC2, 0xEB, 0x02, 0xC4, 0x64, 0xE5, 0x22, 0x22, 0xF5, 0x03, 0x54, 0x0F, 0x54, 0x64, 0xE5, ++ 0x07, 0x90, 0x6B, 0xF5, 0xF0, 0x03, 0x74, 0xFD, 0x03, 0x08, 0x90, 0xE4, 0xFD, 0x07, 0x90, 0xF0, ++ 0x08, 0x90, 0xF0, 0x04, 0xF0, 0x03, 0x74, 0x67, 0x6A, 0x08, 0x90, 0xE4, 0x69, 0x08, 0x90, 0xF0, ++ 0x68, 0x08, 0x90, 0xF0, 0x6B, 0x08, 0x90, 0xF0, 0x08, 0x90, 0xF0, 0x04, 0x90, 0xE4, 0xF0, 0x67, ++ 0x7E, 0xF0, 0x01, 0x0D, 0x12, 0x01, 0x7F, 0x0D, 0x0D, 0x90, 0xCE, 0x0B, 0xF0, 0x80, 0x74, 0x45, ++ 0xF0, 0x65, 0x0D, 0x90, 0xF0, 0x47, 0x0D, 0x90, 0xF0, 0x67, 0x0D, 0x90, 0x74, 0xA9, 0x0D, 0x90, ++ 0x90, 0xE4, 0xF0, 0xFF, 0x90, 0xF0, 0xF9, 0x07, 0xFC, 0x74, 0xFA, 0x07, 0x60, 0x6B, 0xE5, 0xF0, ++ 0xB4, 0x22, 0xE5, 0x05, 0x08, 0x90, 0x08, 0x01, 0xF0, 0x19, 0x74, 0x3B, 0x08, 0x90, 0x06, 0x80, ++ 0xF0, 0x31, 0x74, 0x3B, 0x74, 0x43, 0x08, 0x90, 0x01, 0x74, 0xF0, 0x03, 0x3E, 0x08, 0x90, 0xF0, ++ 0x74, 0xF0, 0x07, 0x74, 0x08, 0x90, 0xF0, 0x05, 0xF0, 0x0B, 0x74, 0x52, 0x74, 0x51, 0x08, 0x90, ++ 0x08, 0x90, 0xF0, 0x07, 0xF0, 0x0A, 0x74, 0x52, 0x74, 0x51, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x06, ++ 0xF0, 0x03, 0x74, 0x3C, 0x74, 0x3D, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x14, 0xF0, 0x01, 0x74, 0x3C, ++ 0xE0, 0x70, 0x07, 0x90, 0x90, 0xF0, 0xF9, 0x54, 0x01, 0x74, 0x72, 0x07, 0x73, 0x07, 0x90, 0xF0, ++ 0xF0, 0x04, 0xE4, 0xE0, 0xE0, 0x74, 0x07, 0x90, 0x90, 0xF0, 0xFF, 0x74, 0xE4, 0xE0, 0x75, 0x07, ++ 0x76, 0x07, 0x90, 0xF0, 0xF5, 0xF0, 0xE4, 0xE0, 0x75, 0x68, 0xF5, 0x67, 0x6A, 0xF5, 0x01, 0x69, ++ 0x75, 0x00, 0x6C, 0x75, 0x22, 0xE5, 0x00, 0x6D, 0x0A, 0x60, 0xFE, 0x24, 0x75, 0x0E, 0x70, 0x04, ++ 0x5E, 0x75, 0x23, 0x5D, 0x5D, 0x75, 0x22, 0x05, 0xE7, 0x5E, 0x75, 0x2B, 0x2E, 0x5D, 0x75, 0x22, ++ 0x22, 0x92, 0x5E, 0x75, 0x7E, 0x0E, 0x08, 0x30, 0x12, 0x33, 0x7F, 0x20, 0x07, 0x90, 0x1D, 0x0E, ++ 0x10, 0x44, 0xE0, 0x07, 0x20, 0x7E, 0x22, 0xF0, 0x0E, 0x12, 0x3A, 0x7F, 0xAD, 0x01, 0x90, 0x1D, ++ 0xF0, 0xF7, 0x54, 0xE0, 0x54, 0xEF, 0x20, 0xAF, 0x75, 0x20, 0xF5, 0xEF, 0x60, 0x75, 0x01, 0x5F, ++ 0x20, 0x7E, 0x22, 0xC5, 0x0E, 0x12, 0x51, 0x7F, 0x22, 0x5D, 0x75, 0x1D, 0x22, 0x1D, 0x5E, 0x75, ++ 0x57, 0x7F, 0x20, 0x7E, 0x75, 0x1D, 0x0E, 0x12, 0x6D, 0x75, 0x00, 0x6C, 0x67, 0xF5, 0xE4, 0x00, ++ 0xF5, 0x01, 0x69, 0x75, 0x22, 0x5D, 0x75, 0x68, 0x22, 0x4B, 0x5E, 0x75, 0x6B, 0x7F, 0x20, 0x7E, ++ 0x75, 0x1D, 0x0E, 0x12, 0x6D, 0x75, 0x00, 0x6C, 0x67, 0xF5, 0xE4, 0x00, 0x75, 0x27, 0x5D, 0x75, ++ 0xAE, 0x22, 0xC9, 0x5E, 0x8F, 0x6D, 0xAF, 0x6C, 0xEF, 0x83, 0x8E, 0x82, 0x82, 0xF5, 0x1F, 0x24, ++ 0x83, 0xF5, 0x3E, 0xE4, 0xAE, 0xF0, 0x4D, 0x74, 0x8F, 0x6D, 0xAF, 0x6C, 0xEF, 0x83, 0x8E, 0x82, ++ 0x82, 0xF5, 0x20, 0x24, 0x83, 0xF5, 0x3E, 0xE4, 0xAE, 0xF0, 0x4D, 0x74, 0x8F, 0x6D, 0xAF, 0x6C, ++ 0xEF, 0x83, 0x8E, 0x82, 0x82, 0xF5, 0x21, 0x24, 0x83, 0xF5, 0x3E, 0xE4, 0xAE, 0xF0, 0x4D, 0x74, ++ 0x8F, 0x6D, 0xAF, 0x6C, 0xEF, 0x83, 0x8E, 0x82, 0x82, 0xF5, 0x22, 0x24, 0x83, 0xF5, 0x3E, 0xE4, ++ 0xAE, 0xF0, 0x4D, 0x74, 0x8F, 0x6D, 0xAF, 0x6C, 0xEF, 0x83, 0x8E, 0x82, 0x82, 0xF5, 0x23, 0x24, ++ 0x83, 0xF5, 0x3E, 0xE4, 0xE5, 0xF0, 0x4D, 0x74, 0x1F, 0x03, 0xB4, 0x67, 0xE0, 0xA9, 0x0D, 0x90, ++ 0xF0, 0x24, 0x00, 0x90, 0xE0, 0xAA, 0x0D, 0x90, 0xF0, 0x25, 0x00, 0x90, 0xE0, 0xAB, 0x0D, 0x90, ++ 0xF0, 0x26, 0x00, 0x90, 0x75, 0x2E, 0x5D, 0x75, 0x05, 0x22, 0x64, 0x5E, 0x25, 0x28, 0x74, 0x67, ++ 0xE4, 0x6D, 0xF5, 0x6D, 0x6C, 0xF5, 0x6C, 0x35, 0x7B, 0x78, 0xD3, 0x22, 0x18, 0x00, 0x94, 0xE6, ++ 0x40, 0x00, 0x94, 0xE6, 0x16, 0xE6, 0x08, 0x72, 0x16, 0x01, 0x70, 0x18, 0xE0, 0xDD, 0x09, 0x90, ++ 0x30, 0x02, 0x03, 0x70, 0x77, 0x78, 0xE4, 0x47, 0x49, 0x08, 0x90, 0xF6, 0xE6, 0xF6, 0x18, 0xE0, ++ 0x7D, 0x78, 0x08, 0x60, 0x70, 0x18, 0xE6, 0x06, 0x76, 0x78, 0x06, 0x01, 0x49, 0x08, 0x90, 0xE6, ++ 0xAE, 0x08, 0x90, 0xF0, 0x60, 0xE6, 0xF6, 0xE0, 0x06, 0x7F, 0x78, 0x08, 0x01, 0x70, 0x18, 0xE6, ++ 0xE6, 0x76, 0x78, 0x06, 0xF0, 0xAE, 0x08, 0x90, 0xE0, 0x13, 0x09, 0x90, 0x08, 0x60, 0xE6, 0xF6, ++ 0xE6, 0x06, 0x81, 0x78, 0x06, 0x01, 0x70, 0x18, 0x90, 0xE6, 0x76, 0x78, 0x90, 0xF0, 0x13, 0x09, ++ 0xF6, 0xE0, 0x78, 0x09, 0x78, 0x08, 0x60, 0xE6, 0x18, 0xE6, 0x06, 0x83, 0x78, 0x06, 0x01, 0x70, ++ 0x09, 0x90, 0xE6, 0x76, 0xE4, 0x22, 0xF0, 0x78, 0x08, 0xF6, 0x78, 0x78, 0xF6, 0x77, 0x78, 0xF6, ++ 0x25, 0xE6, 0x77, 0x78, 0xF8, 0x7C, 0x24, 0xE0, 0xE6, 0x08, 0xFE, 0xE6, 0xF6, 0x26, 0x79, 0x78, ++ 0xF6, 0x36, 0xEE, 0x18, 0xE0, 0x13, 0x06, 0x90, 0x7E, 0x20, 0xE7, 0x30, 0x18, 0x7B, 0x7F, 0x20, ++ 0x00, 0x7C, 0xFD, 0xE6, 0x78, 0x0D, 0x0D, 0x12, 0xE0, 0x25, 0xE6, 0x77, 0xE6, 0xF8, 0x7C, 0x24, ++ 0xFD, 0xE6, 0x08, 0xFC, 0x82, 0x7F, 0x20, 0x7E, 0x78, 0x0D, 0x0D, 0x12, 0xC3, 0xE6, 0x06, 0x77, ++ 0xBC, 0x40, 0x04, 0x94, 0x90, 0xE6, 0x78, 0x78, 0x08, 0xF0, 0x27, 0x00, 0x4F, 0x00, 0x90, 0xE6, ++ 0x2E, 0x5D, 0x75, 0xF0, 0x22, 0x64, 0x5E, 0x75, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, ++ 0x73, 0x65, 0x54, 0x09, 0x09, 0x00, 0x0A, 0x74, 0x74, 0x65, 0x53, 0x09, 0x00, 0x0A, 0x70, 0x75, ++ 0x42, 0x4C, 0x09, 0x09, 0x09, 0x09, 0x00, 0x0A, 0x4C, 0x4F, 0x43, 0x09, 0x0A, 0x64, 0x25, 0x3D, ++ 0x47, 0x09, 0x09, 0x00, 0x00, 0x0A, 0x45, 0x42, 0x69, 0x78, 0x45, 0x09, 0x01, 0x00, 0x0A, 0x74, ++ 0x4F, 0x4D, 0x41, 0x09, 0x53, 0x4E, 0x20, 0x4E, 0x43, 0x09, 0x00, 0x0A, 0x44, 0x49, 0x20, 0x44, ++ 0x00, 0x0A, 0x45, 0x4C, 0x57, 0x44, 0x43, 0x09, 0x0A, 0x54, 0x49, 0x41, 0x44, 0x43, 0x09, 0x00, ++ 0x0A, 0x41, 0x45, 0x4D, 0x2D, 0x2D, 0x2D, 0x00, 0x25, 0x00, 0x0A, 0x2D, 0x43, 0x00, 0x0A, 0x44, ++ 0x6E, 0x6F, 0x44, 0x44, 0x43, 0x00, 0x0A, 0x65, 0x47, 0x41, 0x49, 0x44, 0x69, 0x78, 0x65, 0x2D, ++ 0x09, 0x00, 0x0A, 0x74, 0x45, 0x53, 0x44, 0x43, 0x43, 0x00, 0x0A, 0x54, 0x2D, 0x4B, 0x50, 0x44, ++ 0x00, 0x0A, 0x78, 0x25, 0x25, 0x3A, 0x52, 0x09, 0x4F, 0x00, 0x20, 0x64, 0x20, 0x64, 0x25, 0x3A, ++ 0x25, 0x3A, 0x53, 0x00, 0x44, 0x00, 0x20, 0x64, 0x20, 0x64, 0x25, 0x3A, 0x25, 0x3A, 0x50, 0x00, ++ 0x09, 0x00, 0x0A, 0x44, 0x63, 0x74, 0x61, 0x6D, 0x0A, 0x64, 0x65, 0x68, 0x02, 0x08, 0x20, 0x00, ++ 0x20, 0x7E, 0xA0, 0x21, 0x0E, 0x12, 0x10, 0x7F, 0x00, 0x06, 0x90, 0x1D, 0xE0, 0xA3, 0xFE, 0xE0, ++ 0xC3, 0xCE, 0x06, 0x78, 0xD8, 0x13, 0xCE, 0x13, 0x25, 0x01, 0x54, 0xF9, 0x06, 0x90, 0xFD, 0xE0, ++ 0x13, 0xC4, 0xE0, 0x00, 0x54, 0x4D, 0x01, 0x54, 0x06, 0x90, 0xFF, 0x03, 0xFC, 0x54, 0xE0, 0x31, ++ 0x07, 0x90, 0xF0, 0x4F, 0x01, 0x44, 0xE0, 0x7B, 0x31, 0x06, 0x90, 0xF0, 0xFF, 0x03, 0x54, 0xE0, ++ 0xE0, 0x7C, 0x07, 0x90, 0xF0, 0x4F, 0xF8, 0x54, 0xE0, 0x94, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, ++ 0x44, 0xE0, 0x95, 0x07, 0x07, 0x90, 0xF0, 0x01, 0xF8, 0x54, 0xE0, 0x96, 0x90, 0xF0, 0x03, 0x44, ++ 0x54, 0xE0, 0x95, 0x07, 0x07, 0x90, 0xF0, 0xFE, 0x01, 0x44, 0xE0, 0x98, 0x99, 0x07, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x9A, 0x07, 0x90, 0x02, 0x44, 0xF8, 0x54, 0x99, 0x07, 0x90, 0xF0, ++ 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0x7F, 0x07, 0x90, 0xD2, 0xF0, 0x03, 0x44, 0xD9, 0x01, 0x12, 0x0C, ++ 0xE0, 0xC5, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, 0x54, 0xE0, 0x31, 0x06, 0x07, 0x90, 0xFF, 0x03, ++ 0xF8, 0x54, 0xE0, 0xC6, 0x07, 0x90, 0xF0, 0x4F, 0x01, 0x44, 0xE0, 0xDE, 0xDF, 0x07, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0xE0, 0x07, 0x90, 0x03, 0x44, 0xF8, 0x54, 0xDF, 0x07, 0x90, 0xF0, ++ 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0xE2, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, 0x44, 0xE0, 0xE3, 0x07, ++ 0x07, 0x90, 0xF0, 0x01, 0xF8, 0x54, 0xE0, 0xE4, 0x90, 0xF0, 0x02, 0x44, 0x54, 0xE0, 0xE3, 0x07, ++ 0x07, 0x90, 0xF0, 0xFE, 0x03, 0x44, 0xE0, 0xC9, 0x03, 0x06, 0x90, 0xF0, 0xF0, 0x04, 0x44, 0xE0, ++ 0xE0, 0x80, 0x07, 0x90, 0x90, 0xFF, 0x01, 0x54, 0xC4, 0xE0, 0x01, 0x06, 0x54, 0x13, 0x13, 0x13, ++ 0x1F, 0x60, 0x6F, 0x01, 0x16, 0x7F, 0x20, 0x7E, 0x12, 0x13, 0xC4, 0xE0, 0x06, 0x90, 0x06, 0x0D, ++ 0x80, 0x54, 0xE0, 0x01, 0x13, 0x13, 0x13, 0xC4, 0x90, 0xFF, 0x01, 0x54, 0x54, 0xE0, 0x80, 0x07, ++ 0x90, 0xF0, 0x4F, 0xFE, 0xC4, 0xE0, 0x00, 0x06, 0x03, 0x54, 0x13, 0x13, 0xE0, 0x2B, 0xE0, 0x20, ++ 0x3F, 0x54, 0x13, 0x13, 0xA3, 0x23, 0xE0, 0x20, 0x13, 0x13, 0xC4, 0xE0, 0x20, 0x01, 0x54, 0x13, ++ 0x07, 0x90, 0x18, 0xE0, 0xFC, 0x54, 0xE0, 0x7F, 0xFC, 0x54, 0xE0, 0xF0, 0x03, 0x06, 0x90, 0xF0, ++ 0xF0, 0xFB, 0x54, 0xE0, 0x75, 0x22, 0x5D, 0x75, 0xE5, 0x22, 0xFC, 0x5E, 0x7E, 0x16, 0x60, 0x73, ++ 0x12, 0x00, 0x7F, 0x20, 0x5D, 0x75, 0x1D, 0x0E, 0x88, 0x5E, 0x75, 0x22, 0x01, 0x90, 0x08, 0xD2, ++ 0x20, 0x44, 0xE0, 0xAD, 0xEF, 0x20, 0xAF, 0xF0, 0xAF, 0x39, 0xE0, 0x20, 0x13, 0xC3, 0xEF, 0x20, ++ 0x90, 0x31, 0xE0, 0x20, 0xFE, 0xE0, 0x00, 0x06, 0x07, 0x78, 0xE0, 0xA3, 0xCE, 0x13, 0xC3, 0xCE, ++ 0x20, 0xF9, 0xD8, 0x13, 0x06, 0x90, 0x24, 0xE0, 0x13, 0xC4, 0xE0, 0x00, 0x20, 0x03, 0x54, 0x13, ++ 0x13, 0xE0, 0x18, 0xE0, 0x20, 0x3F, 0x54, 0x13, 0x06, 0x90, 0x10, 0xE0, 0x13, 0xC4, 0xE0, 0x12, ++ 0x06, 0x70, 0x07, 0x54, 0x75, 0x22, 0x5D, 0x75, 0x62, 0xE5, 0xFC, 0x5E, 0x04, 0x70, 0x5E, 0x65, ++ 0x5D, 0x65, 0x61, 0xE5, 0x5D, 0x85, 0x08, 0x60, 0x62, 0x5E, 0x85, 0x61, 0x61, 0xAA, 0x08, 0xD2, ++ 0x02, 0x12, 0x62, 0xA9, 0x22, 0x08, 0xC2, 0xEB, 0x7E, 0x07, 0x08, 0x30, 0x12, 0x07, 0x7F, 0x20, ++ 0x06, 0x90, 0x1D, 0x0E, 0x13, 0xC4, 0xE0, 0x00, 0x20, 0x03, 0x54, 0x13, 0x13, 0xE0, 0x13, 0xE0, ++ 0x20, 0x3F, 0x54, 0x13, 0xE0, 0xA3, 0x0B, 0xE0, 0x13, 0x13, 0x13, 0xC4, 0xE0, 0x30, 0x01, 0x54, ++ 0x20, 0x5D, 0x75, 0x07, 0x22, 0xAD, 0x5E, 0x75, 0x75, 0x22, 0x5D, 0x75, 0x30, 0x22, 0xBF, 0x5E, ++ 0x20, 0x7E, 0x07, 0x08, 0x0E, 0x12, 0x21, 0x7F, 0x12, 0x06, 0x90, 0x1D, 0x54, 0x13, 0xC4, 0xE0, ++ 0x94, 0xD3, 0xFF, 0x07, 0xE4, 0x02, 0x40, 0x04, 0x94, 0xD3, 0xEF, 0xFF, 0x1F, 0x01, 0x40, 0x02, ++ 0xE0, 0xBD, 0x07, 0x90, 0x60, 0x6F, 0x03, 0x54, 0x90, 0x18, 0x71, 0x02, 0xC4, 0xE0, 0x12, 0x06, ++ 0x70, 0x07, 0x54, 0x13, 0x22, 0x5D, 0x75, 0x06, 0x22, 0xFC, 0x5E, 0x75, 0x28, 0x7F, 0x20, 0x7E, ++ 0x90, 0x1D, 0x0E, 0x12, 0x54, 0xE0, 0xAD, 0x01, 0x20, 0xAF, 0xF0, 0xDF, 0xF5, 0xEF, 0x54, 0xEF, ++ 0x01, 0x5F, 0x75, 0x20, 0x22, 0xC5, 0x60, 0x75, 0x07, 0x90, 0x07, 0xAD, 0xFE, 0x54, 0xE0, 0x9C, ++ 0xFD, 0x54, 0xE0, 0xF0, 0x7B, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0xB6, 0x07, 0x90, ++ 0x90, 0xF0, 0x02, 0x44, 0x54, 0xE0, 0xB8, 0x07, 0x54, 0xE0, 0xF0, 0xFC, 0xF0, 0x08, 0x44, 0xF3, ++ 0x44, 0xCF, 0x54, 0xE0, 0x44, 0xE0, 0xF0, 0x10, 0x07, 0x90, 0xF0, 0xC0, 0x02, 0x44, 0xE0, 0xB7, ++ 0xFD, 0x54, 0xE0, 0xF0, 0x7C, 0x07, 0x90, 0xF0, 0x44, 0xF8, 0x54, 0xE0, 0x54, 0xED, 0xF0, 0x02, ++ 0x07, 0x90, 0xFF, 0x03, 0xFC, 0x54, 0xE0, 0xBD, 0x07, 0x90, 0xF0, 0x4F, 0x01, 0x44, 0xE0, 0x94, ++ 0x96, 0x07, 0x90, 0xF0, 0x44, 0xF8, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x03, 0xFC, 0x54, 0xE0, 0xF9, ++ 0xF3, 0x54, 0xE0, 0xF0, 0xE0, 0xF0, 0x04, 0x44, 0x20, 0x44, 0xCF, 0x54, 0xC0, 0x44, 0xE0, 0xF0, ++ 0x00, 0x0D, 0x90, 0xF0, 0xF0, 0xF8, 0x54, 0xE0, 0x44, 0x9F, 0x54, 0xE0, 0x44, 0xE0, 0xF0, 0x20, ++ 0x90, 0xE0, 0xF0, 0x18, 0x90, 0xF0, 0x20, 0x0D, 0x90, 0xE0, 0x00, 0x0D, 0x90, 0xF0, 0x40, 0x0D, ++ 0x90, 0xE0, 0x00, 0x0D, 0x90, 0xF0, 0x60, 0x0D, 0x03, 0xBD, 0x8C, 0x0D, 0xF0, 0x6D, 0x74, 0x05, ++ 0x59, 0x74, 0x03, 0x80, 0x01, 0x0D, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, ++ 0xF0, 0x04, 0x44, 0xE0, 0xF0, 0xEF, 0x54, 0xE0, 0xF0, 0xDF, 0x54, 0xE0, 0x21, 0x0D, 0x90, 0xE0, ++ 0x01, 0x0D, 0x90, 0xF0, 0x41, 0x0D, 0x90, 0xE0, 0x01, 0x0D, 0x90, 0xF0, 0x61, 0x0D, 0x90, 0xE0, ++ 0xA2, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0xAA, 0x74, 0x44, 0xE0, 0xFD, 0x07, 0x08, 0x90, 0xF0, 0x01, ++ 0xF8, 0x54, 0xE0, 0x03, 0xE0, 0xF0, 0x04, 0x44, 0x40, 0x44, 0x8F, 0x54, 0x04, 0x08, 0x90, 0xF0, ++ 0x44, 0xF8, 0x54, 0xE0, 0x54, 0xE0, 0xF0, 0x04, 0xF0, 0x40, 0x44, 0x8F, 0xE0, 0x08, 0x0A, 0x90, ++ 0x90, 0xF0, 0x01, 0x44, 0x01, 0x74, 0x0B, 0x0A, 0x0A, 0x90, 0xE4, 0xF0, 0x0A, 0x90, 0xF0, 0x0A, ++ 0x0A, 0x90, 0xF0, 0x09, 0x90, 0xF0, 0x04, 0x0C, 0x0B, 0x74, 0xE6, 0x09, 0x90, 0xF0, 0x14, 0xF0, ++ 0x54, 0xE0, 0xCD, 0x09, 0x54, 0xE0, 0xF0, 0xFE, 0x44, 0xE0, 0xF0, 0xFD, 0x09, 0x90, 0xF0, 0x04, ++ 0x01, 0x44, 0xE0, 0xD4, 0x02, 0x44, 0xE0, 0xF0, 0xD5, 0x09, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, ++ 0xF0, 0xFB, 0x54, 0xE0, 0xF0, 0xF7, 0x54, 0xE0, 0xE0, 0xD6, 0x09, 0x90, 0xE0, 0xF0, 0x01, 0x44, ++ 0x90, 0xF0, 0x04, 0x44, 0x01, 0x74, 0xD7, 0x09, 0xA8, 0x00, 0x90, 0xF0, 0x03, 0x78, 0xFF, 0xE0, ++ 0xD8, 0x13, 0xE7, 0xA2, 0x08, 0x90, 0x2F, 0xFB, 0x00, 0x90, 0xF0, 0x45, 0x78, 0xFF, 0xE0, 0xA9, ++ 0x13, 0xE7, 0xA2, 0x03, 0x90, 0x2F, 0xFB, 0xD8, 0x90, 0xF0, 0xAA, 0x08, 0xFF, 0xE0, 0xAA, 0x00, ++ 0xE7, 0xA2, 0x03, 0x78, 0x2F, 0xFB, 0xD8, 0x13, 0xF0, 0x0F, 0x09, 0x90, 0xE0, 0xAB, 0x00, 0x90, ++ 0xA2, 0x03, 0x78, 0xFF, 0xFB, 0xD8, 0x13, 0xE7, 0x74, 0x09, 0x90, 0x2F, 0x20, 0x7E, 0x22, 0xF0, ++ 0x0E, 0x02, 0x30, 0x7F, 0x13, 0x06, 0x90, 0x1D, 0xF6, 0x76, 0x78, 0xE0, 0x0D, 0x60, 0x73, 0xE5, ++ 0xE0, 0xAD, 0x01, 0x90, 0xB1, 0xF0, 0x10, 0x44, 0x77, 0x78, 0xE4, 0x3F, 0x12, 0x06, 0x90, 0xF6, ++ 0x54, 0x13, 0xC4, 0xE0, 0x06, 0xBF, 0xFF, 0x07, 0xEF, 0x20, 0xAF, 0x0E, 0xAF, 0x08, 0xE0, 0x20, ++ 0x13, 0xC3, 0xEF, 0x20, 0x75, 0x08, 0xE0, 0x30, 0x5E, 0x75, 0x28, 0x5D, 0x78, 0x18, 0x80, 0x30, ++ 0xE0, 0x30, 0xE6, 0x76, 0x70, 0xE6, 0x08, 0x0C, 0x27, 0x5D, 0x75, 0x0E, 0x80, 0x0F, 0x5E, 0x75, ++ 0x27, 0x5D, 0x75, 0x06, 0xE5, 0x04, 0x5E, 0x75, 0x70, 0x5E, 0x65, 0x62, 0x65, 0x61, 0xE5, 0x04, ++ 0x85, 0x08, 0x60, 0x5D, 0x5E, 0x85, 0x61, 0x5D, 0xAA, 0x08, 0xD2, 0x62, 0x12, 0x62, 0xA9, 0x61, ++ 0x08, 0xC2, 0xEB, 0x02, 0xFF, 0xE6, 0x76, 0x78, 0xE0, 0x13, 0x06, 0x90, 0x7E, 0x22, 0xF0, 0xEF, ++ 0x12, 0x73, 0x7F, 0x20, 0x90, 0xE4, 0x1D, 0x0E, 0x90, 0xF0, 0x7B, 0x07, 0x02, 0x74, 0x7C, 0x07, ++ 0x80, 0x0D, 0x90, 0xF0, 0xE4, 0xF0, 0x20, 0x74, 0xF0, 0x81, 0x0D, 0x90, 0x74, 0xA2, 0x0D, 0x90, ++ 0x0D, 0x90, 0xF0, 0xAA, 0xF0, 0x36, 0x74, 0x8C, 0x74, 0xF8, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x0F, ++ 0xF0, 0xE4, 0x74, 0xF9, 0xF0, 0xFA, 0x07, 0x90, 0x74, 0xFD, 0x07, 0x90, 0x01, 0x74, 0xF0, 0x03, ++ 0x03, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x44, 0x74, 0xE4, 0xF0, 0x04, 0x08, 0xF0, 0x0B, 0x0A, 0x90, ++ 0xF0, 0x0A, 0x0A, 0x90, 0xF0, 0x09, 0x0A, 0x90, 0xF0, 0xFE, 0x09, 0x90, 0xF0, 0xFD, 0x09, 0x90, ++ 0xF0, 0xFC, 0x09, 0x90, 0x74, 0x08, 0x0A, 0x90, 0x0A, 0x90, 0xF0, 0x03, 0x09, 0x90, 0xF0, 0x01, ++ 0x09, 0x90, 0xF0, 0xFB, 0x0A, 0x90, 0xF0, 0xF4, 0xF0, 0x35, 0x74, 0x02, 0xF0, 0xF5, 0x09, 0x90, ++ 0x74, 0x03, 0x0A, 0x90, 0x09, 0x90, 0xF0, 0x05, 0x0A, 0x90, 0xF0, 0xF6, 0xF0, 0xDC, 0x74, 0x04, ++ 0xF0, 0xF7, 0x09, 0x90, 0x74, 0xFF, 0x09, 0x90, 0x0A, 0x90, 0xF0, 0x01, 0x09, 0x90, 0xF0, 0x0C, ++ 0x0A, 0x90, 0xF0, 0xFB, 0x09, 0x90, 0xF0, 0x08, 0x0A, 0x90, 0xF0, 0xF4, 0x09, 0x90, 0xF0, 0x01, ++ 0xF0, 0x0B, 0x74, 0xE6, 0x74, 0xE5, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x03, 0xF0, 0x0A, 0x74, 0xE6, ++ 0x74, 0xE5, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x02, 0xF0, 0x04, 0x74, 0xCD, 0x14, 0xD4, 0x09, 0x90, ++ 0xD5, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x05, 0x74, 0xD6, 0x09, 0xD7, 0x09, 0x90, 0xF0, ++ 0x74, 0xF0, 0x03, 0x74, 0x09, 0x90, 0xF0, 0x01, 0xF0, 0x74, 0x74, 0xD9, 0x74, 0xD2, 0x09, 0x90, ++ 0x09, 0x90, 0xF0, 0x03, 0xF0, 0x18, 0x74, 0xD3, 0x74, 0xD2, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x01, ++ 0xF0, 0x05, 0x74, 0xD0, 0x74, 0xB6, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x03, 0x90, 0xE4, 0xF0, 0xB7, ++ 0x90, 0xF0, 0xB8, 0x07, 0x90, 0xF0, 0xB7, 0x07, 0x1D, 0x74, 0xB0, 0x07, 0xAE, 0x07, 0x90, 0xF0, ++ 0x90, 0xF0, 0xFF, 0x74, 0x2A, 0x74, 0xAF, 0x07, 0xA4, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x16, 0x74, ++ 0xF0, 0x04, 0xA3, 0x09, 0xA5, 0x09, 0x90, 0xE4, 0xA8, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x03, 0x74, ++ 0x0C, 0x74, 0xA6, 0x09, 0xFE, 0xFF, 0xE4, 0xF0, 0xE0, 0x79, 0x08, 0x90, 0x14, 0x08, 0x90, 0xFD, ++ 0x90, 0xFD, 0x5D, 0xE0, 0x5D, 0xE0, 0xDE, 0x08, 0x43, 0x09, 0x90, 0xFD, 0x01, 0x64, 0x5D, 0xE0, ++ 0xEF, 0xC3, 0x11, 0x60, 0x94, 0xEE, 0xFF, 0x94, 0x00, 0x08, 0x50, 0x00, 0x01, 0x00, 0xBF, 0x0F, ++ 0x90, 0xD5, 0x80, 0x0E, 0x43, 0x74, 0xB0, 0x09, 0xB2, 0x09, 0x90, 0xF0, 0xB4, 0x09, 0x90, 0xF0, ++ 0xB6, 0x09, 0x90, 0xF0, 0xB8, 0x09, 0x90, 0xF0, 0x7F, 0xF0, 0x53, 0x74, 0x90, 0xF2, 0xD1, 0x03, ++ 0x42, 0x74, 0xB0, 0x09, 0xB2, 0x09, 0x90, 0xF0, 0xB4, 0x09, 0x90, 0xF0, 0xB6, 0x09, 0x90, 0xF0, ++ 0xB8, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x52, 0x74, 0x02, 0x74, 0x80, 0x00, 0x05, 0x74, 0xA3, 0xF0, ++ 0x09, 0x90, 0x22, 0xF0, 0x90, 0xF0, 0xEF, 0x9D, 0x90, 0xF0, 0x9F, 0x09, 0x90, 0xF0, 0xA0, 0x09, ++ 0x22, 0xF0, 0xA1, 0x09, 0x7E, 0x07, 0x08, 0x30, 0x12, 0x3A, 0x7F, 0x20, 0x30, 0x22, 0x1D, 0x0E, ++ 0x20, 0x7E, 0x20, 0x08, 0x0E, 0x12, 0x44, 0x7F, 0x76, 0x74, 0x78, 0x1D, 0x01, 0x76, 0x08, 0x00, ++ 0x01, 0x76, 0x77, 0x78, 0x13, 0xC3, 0xE6, 0x18, 0x78, 0x07, 0xE0, 0x30, 0x08, 0x34, 0x76, 0x74, ++ 0x74, 0x7F, 0xBC, 0x76, 0x50, 0xB4, 0x0B, 0x12, 0x27, 0x5D, 0x75, 0x06, 0x22, 0x40, 0x5E, 0x75, ++ 0x7E, 0x30, 0x08, 0x30, 0x12, 0x4D, 0x7F, 0x20, 0x74, 0x78, 0x1D, 0x0E, 0x76, 0x08, 0x01, 0x76, ++ 0xD1, 0x02, 0x7F, 0xF4, 0x7B, 0x07, 0x90, 0xF2, 0x90, 0xF0, 0x01, 0x74, 0x82, 0xAF, 0x00, 0x00, ++ 0xEF, 0xC3, 0x83, 0xAE, 0x94, 0xEE, 0x80, 0x94, 0x02, 0x03, 0x40, 0x00, 0xF0, 0xE4, 0x16, 0x28, ++ 0x7F, 0xEB, 0x80, 0xA3, 0xB4, 0x0B, 0x12, 0x74, 0x28, 0x02, 0x03, 0x40, 0xD1, 0x1A, 0x7F, 0x16, ++ 0x07, 0x90, 0xE4, 0xF2, 0x22, 0xF5, 0xF0, 0x7B, 0x78, 0x23, 0xF5, 0xE4, 0x13, 0x13, 0xE6, 0x76, ++ 0xE0, 0x30, 0x3F, 0x54, 0x7F, 0x20, 0x7E, 0x43, 0x1D, 0x0E, 0x12, 0x55, 0xAF, 0x24, 0xF5, 0xE4, ++ 0xE5, 0x00, 0x7E, 0x24, 0xB4, 0x00, 0x7C, 0x23, 0x80, 0x7D, 0x04, 0x03, 0x20, 0x7D, 0x02, 0x80, ++ 0xEC, 0x9D, 0xEF, 0xC3, 0xEE, 0xF8, 0x80, 0x64, 0x50, 0x98, 0x80, 0x64, 0xAD, 0x23, 0xAB, 0x1B, ++ 0x12, 0x24, 0xAF, 0x22, 0x06, 0xAC, 0x5E, 0x2A, 0x20, 0x7E, 0x07, 0xAD, 0x0D, 0x12, 0x5B, 0x7F, ++ 0xFD, 0x0B, 0x20, 0x0D, 0xC7, 0x80, 0x24, 0x05, 0x03, 0xB4, 0x23, 0xE5, 0x22, 0xAF, 0xFD, 0x0B, ++ 0x30, 0x4C, 0x28, 0x12, 0xFB, 0x80, 0x09, 0x0B, 0x22, 0xAF, 0x23, 0xAD, 0x05, 0x7E, 0x2A, 0x12, ++ 0xC3, 0x23, 0xE5, 0x23, 0x93, 0x40, 0x04, 0x94, 0x22, 0xE5, 0x22, 0x05, 0x40, 0x04, 0x94, 0xC3, ++ 0xE6, 0x76, 0x78, 0x87, 0xE4, 0xF6, 0xFE, 0x54, 0x74, 0x78, 0xF6, 0x08, 0x7E, 0xF6, 0x08, 0xF6, ++ 0x12, 0x5F, 0x7F, 0x20, 0x8F, 0x22, 0x1D, 0x0E, 0xED, 0x83, 0x8E, 0x82, 0xA4, 0x02, 0xF0, 0x75, ++ 0x82, 0xF5, 0x82, 0x25, 0x83, 0x35, 0xF0, 0xE5, 0xF0, 0xEA, 0x83, 0xF5, 0x22, 0xF0, 0xEB, 0xA3, ++ 0x67, 0x7F, 0x20, 0x7E, 0x90, 0x1D, 0x0E, 0x12, 0x54, 0xE0, 0xAD, 0x01, 0x20, 0xAF, 0xF0, 0xEF, ++ 0xF5, 0xEF, 0x54, 0xEF, 0x01, 0x5F, 0x75, 0x20, 0x22, 0xC5, 0x60, 0x75, 0x26, 0x8D, 0x25, 0x8F, ++ 0xE0, 0x81, 0x00, 0x90, 0x00, 0x90, 0x35, 0xF5, 0x36, 0xF5, 0xE0, 0x80, 0x85, 0x39, 0x25, 0x85, ++ 0x20, 0x7E, 0x3A, 0x26, 0x3A, 0xAD, 0x7B, 0x7F, 0x0D, 0x12, 0x39, 0xAC, 0x75, 0x25, 0xE5, 0x0D, ++ 0xF5, 0xA4, 0x08, 0xF0, 0x33, 0xF5, 0xE4, 0x34, 0x25, 0xAD, 0x26, 0xAB, 0x41, 0x51, 0x08, 0x7F, ++ 0x26, 0xAB, 0x27, 0x8F, 0x07, 0x7F, 0x25, 0xAD, 0x33, 0xEF, 0x41, 0x51, 0xAD, 0xFE, 0xE0, 0x95, ++ 0x95, 0x33, 0xED, 0x27, 0xED, 0xC3, 0xFC, 0xE0, 0xEC, 0x2A, 0xF5, 0x9F, 0x75, 0x29, 0xF5, 0x9E, ++ 0x30, 0x75, 0x00, 0x2F, 0x7F, 0x26, 0xE5, 0xCD, 0x02, 0x03, 0xB4, 0x20, 0x32, 0x8F, 0x80, 0x7F, ++ 0xE5, 0x09, 0x31, 0x75, 0x32, 0x95, 0xC3, 0x31, 0x1B, 0x41, 0x02, 0x40, 0x25, 0xAD, 0x26, 0xAB, ++ 0x41, 0x51, 0x31, 0xAF, 0x27, 0xAF, 0x28, 0x8F, 0xE0, 0x95, 0x33, 0xEF, 0xED, 0x28, 0xAD, 0xFE, ++ 0xFC, 0xE0, 0x95, 0x33, 0xF5, 0x9F, 0xED, 0xC3, 0xF5, 0x9E, 0xEC, 0x2C, 0xC3, 0x33, 0xE5, 0x2B, ++ 0x02, 0x40, 0x05, 0x94, 0xFF, 0xE4, 0xEC, 0x21, 0x38, 0xF5, 0x37, 0xF5, 0x7F, 0x24, 0x30, 0xE5, ++ 0x35, 0xE4, 0x3A, 0xF5, 0xAE, 0x39, 0xF5, 0x2F, 0xEE, 0x37, 0xAD, 0x39, 0xE5, 0xD3, 0x37, 0xF5, ++ 0xE5, 0x00, 0x94, 0x2A, 0x94, 0x80, 0x64, 0x29, 0xD3, 0x33, 0x40, 0x80, 0x00, 0x94, 0x2C, 0xE5, ++ 0x80, 0x64, 0x2B, 0xE5, 0x26, 0x50, 0x80, 0x94, 0x80, 0x64, 0x36, 0xE5, 0x64, 0x27, 0xE5, 0xF8, ++ 0x1A, 0x40, 0x98, 0x80, 0xEE, 0x38, 0xAE, 0x0F, 0x38, 0xF5, 0x02, 0x44, 0x80, 0x64, 0x35, 0xE5, ++ 0x64, 0x27, 0xE5, 0xF8, 0x00, 0x7E, 0x98, 0x80, 0x01, 0x7E, 0x02, 0x50, 0xE5, 0xC3, 0x3B, 0x80, ++ 0x94, 0x80, 0x64, 0x29, 0xC3, 0x3E, 0x50, 0x80, 0x80, 0x64, 0x2B, 0xE5, 0x35, 0x40, 0x80, 0x94, ++ 0x04, 0xF4, 0x36, 0xE5, 0xE5, 0xF8, 0x80, 0x64, 0x98, 0x80, 0x64, 0x27, 0x02, 0x7F, 0x27, 0x50, ++ 0x44, 0xEE, 0x38, 0xAE, 0xE5, 0x38, 0xF5, 0x04, 0x64, 0x04, 0xF4, 0x35, 0x27, 0xE5, 0xF8, 0x80, ++ 0x7E, 0x98, 0x80, 0x64, 0x7E, 0x02, 0x40, 0x00, 0x01, 0x54, 0xEE, 0x01, 0xED, 0x38, 0xAD, 0xFE, ++ 0xF5, 0x4E, 0xFE, 0x54, 0x64, 0x60, 0xEF, 0x38, 0xFF, 0x14, 0x31, 0xE5, 0x25, 0xAD, 0x26, 0xAB, ++ 0x2D, 0x8E, 0x5E, 0x51, 0x34, 0xE5, 0x2E, 0x8F, 0xAB, 0xFD, 0x33, 0x25, 0xE4, 0x37, 0xAA, 0x38, ++ 0x17, 0x11, 0xFE, 0xFF, 0x33, 0x25, 0x34, 0xE5, 0xAA, 0x2E, 0xAB, 0xFD, 0x11, 0x40, 0x7F, 0x2D, ++ 0x7F, 0x20, 0x7E, 0x17, 0xED, 0x38, 0xAD, 0x84, 0x7E, 0x08, 0x0D, 0x12, 0xAD, 0x8B, 0x7F, 0x20, ++ 0x12, 0xC3, 0xED, 0x38, 0x20, 0x7E, 0x07, 0x0D, 0x38, 0xAD, 0x91, 0x7F, 0x06, 0x0D, 0x12, 0xED, ++ 0x97, 0x7F, 0x20, 0x7E, 0x7C, 0xED, 0x37, 0xAD, 0x0D, 0x0D, 0x12, 0x00, 0x9D, 0x7F, 0x20, 0x7E, ++ 0x2D, 0xAC, 0x2E, 0xAD, 0x20, 0x0D, 0x0D, 0x12, 0x33, 0x05, 0xFD, 0x0B, 0x85, 0x27, 0x28, 0x85, ++ 0x2C, 0x85, 0x29, 0x2B, 0xB4, 0x31, 0xE5, 0x2A, 0x31, 0x05, 0x02, 0x3F, 0x94, 0xD3, 0x31, 0xE5, ++ 0x7E, 0x06, 0x40, 0x40, 0x80, 0x9A, 0x7F, 0x01, 0x7F, 0x00, 0x7E, 0x04, 0x30, 0x25, 0xEF, 0xCD, ++ 0x35, 0xEE, 0x30, 0xF5, 0x05, 0x2F, 0xF5, 0x2F, 0xE5, 0xB3, 0x01, 0x31, 0x7E, 0x21, 0x70, 0x33, ++ 0x12, 0xA3, 0x7F, 0x20, 0xF5, 0xE4, 0x1D, 0x0E, 0xAF, 0x38, 0xF5, 0x37, 0x08, 0x44, 0xEF, 0x38, ++ 0x34, 0xE5, 0x38, 0xF5, 0xAB, 0xFD, 0x33, 0x25, 0xE4, 0x37, 0xAA, 0x38, 0x17, 0x11, 0xFE, 0xFF, ++ 0xAA, 0x09, 0x90, 0x22, 0x09, 0x90, 0xF0, 0xEB, 0xED, 0xF0, 0xEF, 0xAB, 0xA4, 0x65, 0xF0, 0x75, ++ 0xE5, 0xFF, 0x1A, 0x24, 0x8F, 0x08, 0x34, 0xF0, 0xE0, 0x83, 0xF5, 0x82, 0x09, 0x90, 0x22, 0xFF, ++ 0x90, 0xF0, 0xEB, 0xAA, 0xF0, 0xEF, 0xAB, 0x09, 0x65, 0xF0, 0x75, 0xED, 0xFF, 0x1A, 0x24, 0xA4, ++ 0x08, 0x34, 0xF0, 0xE5, 0x83, 0xF5, 0x82, 0x8F, 0xE0, 0xA3, 0xFE, 0xE0, 0x25, 0x8F, 0x22, 0xFF, ++ 0xF5, 0xE4, 0x05, 0xAA, 0xEF, 0x27, 0xF5, 0x26, 0xA4, 0x10, 0xF0, 0x75, 0xE4, 0xFD, 0x0A, 0x24, ++ 0xEA, 0xFC, 0xF0, 0x35, 0xA4, 0x02, 0xF0, 0x75, 0xF0, 0xE5, 0xFF, 0x2D, 0x8F, 0x28, 0xF5, 0x3C, ++ 0xE9, 0xF9, 0xE4, 0x29, 0x7C, 0x00, 0x7E, 0xFF, 0x04, 0x03, 0xBA, 0x00, 0x02, 0x80, 0x80, 0x7D, ++ 0xEF, 0xC3, 0x20, 0x7D, 0x80, 0x64, 0xEC, 0x9D, 0x80, 0x64, 0xEE, 0xF8, 0xAF, 0x31, 0x50, 0x98, ++ 0xAD, 0x02, 0xAB, 0x01, 0xEF, 0x5E, 0x51, 0x25, 0xA2, 0xCE, 0x07, 0x78, 0x13, 0xCE, 0x13, 0xE7, ++ 0x82, 0xF5, 0xF8, 0xD8, 0xFD, 0xFF, 0x83, 0x8E, 0x02, 0x12, 0x83, 0xAC, 0xE7, 0xA2, 0xEE, 0x84, ++ 0x13, 0xEF, 0xFE, 0x13, 0x27, 0xF5, 0x27, 0x25, 0xF5, 0x26, 0x35, 0xEE, 0xB3, 0x80, 0x09, 0x26, ++ 0x85, 0x82, 0x29, 0x85, 0x26, 0xE5, 0x83, 0x28, 0x27, 0xE5, 0xA3, 0xF0, 0x00, 0x22, 0x22, 0xF0, ++ 0x42, 0x30, 0x31, 0x09, 0x09, 0x00, 0x0A, 0x54, 0x75, 0x74, 0x65, 0x53, 0x09, 0x00, 0x0A, 0x70, ++ 0x6B, 0x6E, 0x69, 0x4C, 0x0A, 0x70, 0x55, 0x2D, 0x4C, 0x09, 0x09, 0x00, 0x2D, 0x6B, 0x6E, 0x69, ++ 0x73, 0x73, 0x6F, 0x4C, 0x4C, 0x09, 0x00, 0x0A, 0x2D, 0x6B, 0x6E, 0x69, 0x6E, 0x77, 0x6F, 0x44, ++ 0x09, 0x09, 0x00, 0x0A, 0x00, 0x49, 0x44, 0x4D, 0x00, 0x0A, 0x00, 0x58, 0x69, 0x78, 0x45, 0x09, ++ 0x01, 0x00, 0x0A, 0x74, 0x0B, 0x60, 0x73, 0xE5, 0x00, 0x7F, 0x20, 0x7E, 0x11, 0x1D, 0x0E, 0x12, ++ 0xAF, 0x08, 0xD2, 0xDA, 0x54, 0xC4, 0xEF, 0x20, 0x22, 0xE0, 0x20, 0x0F, 0x20, 0xEF, 0x20, 0xAF, ++ 0x20, 0xAF, 0x1C, 0xE0, 0x20, 0x13, 0xC3, 0xEF, 0x20, 0xAF, 0x14, 0xE0, 0x54, 0x13, 0xC4, 0xEF, ++ 0x0A, 0xE0, 0x20, 0x07, 0x13, 0xEF, 0x20, 0xAF, 0x30, 0x3F, 0x54, 0x13, 0x27, 0x7E, 0x1E, 0xE0, ++ 0x65, 0xEF, 0x7C, 0x7F, 0xEE, 0x03, 0x70, 0x62, 0x10, 0x60, 0x61, 0x65, 0x62, 0x65, 0x91, 0x74, ++ 0x27, 0x74, 0x04, 0x70, 0x04, 0x60, 0x61, 0x65, 0x5E, 0x8F, 0x5D, 0x8E, 0x5E, 0x65, 0x62, 0xE5, ++ 0x61, 0xE5, 0x04, 0x70, 0x08, 0x60, 0x5D, 0x65, 0x85, 0x61, 0x5D, 0x85, 0x08, 0xD2, 0x62, 0x5E, ++ 0x62, 0xA9, 0x61, 0xAA, 0xC2, 0xEB, 0x02, 0x12, 0xE6, 0x7B, 0x78, 0x08, 0xC3, 0xFF, 0x01, 0x54, ++ 0x08, 0x74, 0x9F, 0xE4, 0x05, 0x54, 0x00, 0x94, 0xC3, 0xE6, 0x18, 0xFC, 0xE6, 0x08, 0xFE, 0x13, ++ 0x6C, 0xEE, 0xFF, 0x13, 0x08, 0xEF, 0xF6, 0x18, 0x20, 0x7E, 0x22, 0xF6, 0x0E, 0x12, 0x07, 0x7F, ++ 0x43, 0x20, 0x90, 0x1D, 0x02, 0x60, 0x93, 0xE4, 0x42, 0x71, 0x09, 0xC2, 0x90, 0x24, 0x04, 0x12, ++ 0xC4, 0xE0, 0xAA, 0x0D, 0x90, 0xFF, 0x0F, 0x54, 0xC4, 0xE0, 0xAB, 0x0D, 0xFF, 0x2F, 0x0F, 0x54, ++ 0x24, 0xCF, 0x33, 0xE4, 0x34, 0xEF, 0xFD, 0x00, 0x07, 0x90, 0xFC, 0x04, 0xF0, 0x75, 0xE0, 0x0B, ++ 0xEC, 0xFF, 0xA4, 0x20, 0x7A, 0x78, 0xF0, 0x45, 0x08, 0x4F, 0xED, 0xF6, 0x23, 0x06, 0x90, 0xF6, ++ 0x07, 0x90, 0x3B, 0x31, 0xF0, 0x0D, 0x74, 0xFB, 0xF6, 0x74, 0x78, 0xE4, 0x76, 0x08, 0xF6, 0x08, ++ 0xE6, 0x76, 0x08, 0xAA, 0x75, 0x22, 0x5D, 0x75, 0xE0, 0x22, 0x3E, 0x5E, 0x54, 0x13, 0x13, 0xFF, ++ 0x0C, 0x92, 0x13, 0x3F, 0xE0, 0x27, 0x06, 0x90, 0x30, 0x03, 0xE0, 0x30, 0x06, 0x90, 0x1A, 0x0C, ++ 0xE0, 0x20, 0xE0, 0x27, 0x26, 0x06, 0x90, 0x6C, 0xE0, 0xA3, 0xFE, 0xE0, 0xC3, 0xCE, 0x02, 0x78, ++ 0xD8, 0x13, 0xCE, 0x13, 0x59, 0xE0, 0x20, 0xF9, 0x0D, 0x90, 0x0C, 0xC2, 0xF0, 0x0F, 0x74, 0x01, ++ 0x04, 0x21, 0x0D, 0x90, 0x00, 0x0D, 0x90, 0xF0, 0xF0, 0x9F, 0x54, 0xE0, 0x74, 0x0D, 0x0D, 0x90, ++ 0x0D, 0x90, 0xF0, 0x21, 0xF0, 0x45, 0x74, 0x0E, 0x74, 0x0F, 0x0D, 0x90, 0x90, 0xE4, 0xF0, 0x04, ++ 0x90, 0xF0, 0x2D, 0x0D, 0x90, 0xF0, 0x2E, 0x0D, 0x90, 0xF0, 0x2F, 0x0D, 0x54, 0xE0, 0x20, 0x0D, ++ 0xF0, 0x20, 0x44, 0x9F, 0x74, 0x0C, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x36, 0xF0, 0x12, 0x74, 0x2C, ++ 0x74, 0xF9, 0x07, 0x90, 0x07, 0x90, 0xF0, 0xE4, 0xF0, 0xB1, 0x74, 0xFA, 0x80, 0xA4, 0x00, 0x90, ++ 0x90, 0x0C, 0xD2, 0x57, 0x0F, 0x74, 0x21, 0x0D, 0x01, 0x0D, 0x90, 0xF0, 0x0D, 0x90, 0xF0, 0x04, ++ 0x9F, 0x54, 0xE0, 0x00, 0x90, 0xF0, 0x20, 0x44, 0x54, 0xE0, 0x20, 0x0D, 0x90, 0xE4, 0xF0, 0x9F, ++ 0x90, 0xF0, 0x0D, 0x0D, 0x90, 0xF0, 0x0E, 0x0D, 0x90, 0xF0, 0x0F, 0x0D, 0x21, 0x74, 0x2D, 0x0D, ++ 0x2E, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x45, 0x74, 0x04, 0x74, 0x2F, 0x0D, 0x0C, 0x0D, 0x90, 0xF0, ++ 0x90, 0xF0, 0x12, 0x74, 0x36, 0x74, 0x2C, 0x0D, 0xF9, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0xB1, 0x74, ++ 0xE4, 0x74, 0xFA, 0x07, 0xA5, 0x00, 0x90, 0xF0, 0x45, 0x08, 0x90, 0xE0, 0xE4, 0x0C, 0xA2, 0xF0, ++ 0xFC, 0x01, 0x54, 0x33, 0xE0, 0x25, 0xE0, 0x25, 0x23, 0x06, 0x90, 0xFE, 0x4E, 0xFB, 0x54, 0xE0, ++ 0x33, 0x33, 0xEC, 0xF0, 0xFF, 0xF8, 0x54, 0x33, 0x4F, 0xF7, 0x54, 0xE0, 0x08, 0x30, 0x22, 0xF0, ++ 0x7F, 0x20, 0x7E, 0x23, 0x1D, 0x0E, 0x12, 0x26, 0xF4, 0x76, 0x78, 0x78, 0x90, 0x24, 0x76, 0x08, ++ 0x44, 0xE0, 0x95, 0x07, 0x07, 0x90, 0xF0, 0x01, 0x01, 0x44, 0xE0, 0x99, 0x91, 0x07, 0x90, 0xF0, ++ 0xF0, 0x02, 0x44, 0xE0, 0xE0, 0x00, 0x06, 0x90, 0x30, 0x0F, 0x54, 0xC4, 0x78, 0xD3, 0x1B, 0xE0, ++ 0x00, 0x94, 0xE6, 0x77, 0x00, 0x94, 0xE6, 0x18, 0xE6, 0x08, 0x09, 0x40, 0x01, 0x70, 0x18, 0x16, ++ 0x75, 0x06, 0x80, 0x16, 0x5E, 0x75, 0x27, 0x5D, 0xA6, 0x07, 0x90, 0x7C, 0x64, 0x07, 0x54, 0xE0, ++ 0x90, 0x09, 0x60, 0x01, 0xC3, 0xE0, 0x91, 0x07, 0x1E, 0xE0, 0x30, 0x13, 0xE0, 0x91, 0x07, 0x90, ++ 0xE0, 0x30, 0x13, 0xC3, 0x76, 0x74, 0x78, 0x09, 0x88, 0x76, 0x08, 0x13, 0x78, 0xE4, 0x06, 0x80, ++ 0xF6, 0x08, 0xF6, 0x74, 0x75, 0x26, 0x5D, 0x75, 0x06, 0x90, 0x28, 0x5E, 0x54, 0xC4, 0xE0, 0x00, ++ 0x05, 0xE0, 0x30, 0x0F, 0x80, 0x23, 0x06, 0x90, 0x27, 0x06, 0x90, 0x07, 0x0A, 0xE0, 0x20, 0xE0, ++ 0x78, 0x78, 0x3B, 0x31, 0x76, 0x08, 0xF4, 0x76, 0x78, 0xD3, 0x22, 0x24, 0x00, 0x94, 0xE6, 0x79, ++ 0x00, 0x94, 0xE6, 0x18, 0xE6, 0x08, 0x08, 0x40, 0x01, 0x70, 0x18, 0x16, 0x78, 0x78, 0x22, 0x16, ++ 0x76, 0x08, 0xF4, 0x76, 0xA6, 0x07, 0x90, 0x24, 0x70, 0x07, 0x54, 0xE0, 0xE6, 0x7B, 0x78, 0x44, ++ 0x90, 0xFF, 0x01, 0x54, 0xFD, 0xE0, 0x23, 0x06, 0x01, 0x54, 0x13, 0x13, 0xE4, 0x01, 0x70, 0x6F, ++ 0x06, 0x90, 0x07, 0x60, 0x08, 0x44, 0xE0, 0x35, 0xE6, 0x7B, 0x78, 0xF0, 0x31, 0x0C, 0x92, 0x13, ++ 0x7F, 0x20, 0x7E, 0x44, 0x1D, 0x0E, 0x12, 0x32, 0xE0, 0x23, 0x06, 0x90, 0x3F, 0x54, 0x13, 0x13, ++ 0x7E, 0x07, 0xE0, 0x30, 0x12, 0x38, 0x7F, 0x20, 0x20, 0x7E, 0x1D, 0x0E, 0x0E, 0x12, 0x3A, 0x7F, ++ 0x90, 0xE4, 0x22, 0x1D, 0x90, 0xF0, 0x01, 0x0D, 0x90, 0xF0, 0x21, 0x0D, 0xFF, 0x74, 0x41, 0x0D, ++ 0x61, 0x0D, 0x90, 0xF0, 0x00, 0x0D, 0x90, 0xF0, 0xF0, 0xF8, 0x54, 0xE0, 0xF0, 0x18, 0x44, 0xE0, ++ 0x20, 0x0D, 0x90, 0xE0, 0x0A, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x59, 0x74, 0x90, 0xF0, 0x2A, 0x0D, ++ 0x6C, 0x74, 0x06, 0x0D, 0x26, 0x0D, 0x90, 0xF0, 0xA2, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0xAA, 0x74, ++ 0x11, 0x74, 0x0C, 0x0D, 0x2C, 0x0D, 0x90, 0xF0, 0x02, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0xB0, 0x74, ++ 0x90, 0xF0, 0x22, 0x0D, 0x20, 0x74, 0x05, 0x0D, 0x25, 0x0D, 0x90, 0xF0, 0xF8, 0x07, 0x90, 0xF0, ++ 0x90, 0xF0, 0x01, 0x74, 0x44, 0xE0, 0xFD, 0x07, 0x44, 0xE0, 0xF0, 0x01, 0x54, 0xE0, 0xF0, 0x02, ++ 0x08, 0x90, 0xF0, 0xFD, 0xF8, 0x54, 0xE0, 0x03, 0x90, 0xF0, 0x04, 0x44, 0x44, 0xE0, 0x08, 0x0A, ++ 0x44, 0xE0, 0xF0, 0x01, 0x54, 0xE0, 0xF0, 0x02, 0x07, 0x90, 0xF0, 0xFD, 0x0F, 0x54, 0xE0, 0x10, ++ 0xA4, 0x10, 0xF0, 0x75, 0xE4, 0xFD, 0xAB, 0x24, 0x90, 0xFC, 0xF0, 0x35, 0x75, 0xE0, 0x0F, 0x07, ++ 0x2D, 0xA4, 0xAA, 0xF0, 0x3C, 0xF0, 0xE5, 0xFF, 0xEF, 0xFC, 0x07, 0xAD, 0xF0, 0x0B, 0x0A, 0x90, ++ 0xE0, 0x0F, 0x07, 0x90, 0xF0, 0x75, 0x0F, 0x54, 0x90, 0xFF, 0xA4, 0x10, 0xC4, 0xE0, 0x10, 0x07, ++ 0xE5, 0xFB, 0x0F, 0x54, 0x4F, 0xEB, 0xFA, 0xF0, 0xFF, 0x2B, 0xEC, 0xFB, 0x24, 0xCF, 0x3A, 0xE4, ++ 0x3F, 0xE4, 0xFD, 0xAA, 0xED, 0x05, 0xAF, 0xFC, 0xF0, 0x0A, 0x0A, 0x90, 0xE0, 0x0F, 0x07, 0x90, ++ 0xFB, 0x0F, 0x54, 0xC4, 0xE4, 0xFF, 0x2B, 0xEC, 0x0A, 0x24, 0xCF, 0x33, 0xED, 0x05, 0xAF, 0xFD, ++ 0xF0, 0x09, 0x0A, 0x90, 0x74, 0x0C, 0x0A, 0x90, 0x08, 0x90, 0xF0, 0x01, 0x01, 0x44, 0xE0, 0x60, ++ 0x02, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xF0, 0x08, 0x90, 0xE4, 0xF0, 0x08, 0x90, 0xF0, 0x61, ++ 0xF8, 0x54, 0xE0, 0x62, 0x90, 0xF0, 0x06, 0x44, 0x74, 0xE0, 0x63, 0x08, 0x08, 0x90, 0xF0, 0xFA, ++ 0x01, 0x44, 0xE0, 0x67, 0x10, 0x07, 0x90, 0xF0, 0x75, 0x0F, 0x54, 0xE0, 0x24, 0xA4, 0x10, 0xF0, ++ 0x35, 0xE4, 0xFD, 0xAB, 0x07, 0x90, 0xFC, 0xF0, 0xF0, 0x75, 0xE0, 0x0F, 0xFD, 0x2D, 0xA4, 0xAA, ++ 0xFC, 0x3C, 0xF0, 0xE5, 0x90, 0xED, 0x05, 0xAF, 0x90, 0xF0, 0x6A, 0x08, 0x54, 0xE0, 0x0F, 0x07, ++ 0x10, 0xF0, 0x75, 0x0F, 0x07, 0x90, 0xFF, 0xA4, 0x54, 0xC4, 0xE0, 0x10, 0xF0, 0xE5, 0xFB, 0x0F, ++ 0xFB, 0x4F, 0xEB, 0xFA, 0xE4, 0xFF, 0x2B, 0xEC, 0xAA, 0x24, 0xCF, 0x3A, 0xFC, 0x3F, 0xE4, 0xFD, ++ 0x90, 0xED, 0x05, 0xAF, 0x90, 0xF0, 0x69, 0x08, 0xC4, 0xE0, 0x0F, 0x07, 0xEC, 0xFB, 0x0F, 0x54, ++ 0x33, 0xE4, 0xFF, 0x2B, 0xFD, 0x0A, 0x24, 0xCF, 0x05, 0xAF, 0x3F, 0xE4, 0x68, 0x08, 0x90, 0xED, ++ 0x6B, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x0B, 0x74, 0x52, 0x08, 0x51, 0x08, 0x90, 0xF0, ++ 0x90, 0xF0, 0x07, 0x74, 0x0A, 0x74, 0x52, 0x08, 0x51, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x06, 0x74, ++ 0x44, 0xE0, 0x39, 0x08, 0x08, 0x90, 0xF0, 0x01, 0xFE, 0x54, 0xE0, 0x3A, 0x40, 0x08, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x41, 0x08, 0x90, 0xE0, 0xF0, 0x01, 0x44, 0x90, 0xF0, 0x08, 0x44, ++ 0x44, 0xE0, 0x42, 0x08, 0x08, 0x90, 0xF0, 0x01, 0x01, 0x44, 0xE0, 0x43, 0x3E, 0x08, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x94, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, 0x44, 0xE0, 0x95, 0x07, ++ 0x07, 0x90, 0xF0, 0x01, 0xF8, 0x54, 0xE0, 0x96, 0x90, 0xF0, 0x03, 0x44, 0x03, 0x74, 0x97, 0x07, ++ 0x95, 0x07, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0x98, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, ++ 0x44, 0xE0, 0x99, 0x07, 0x07, 0x90, 0xF0, 0x01, 0xF8, 0x54, 0xE0, 0x9A, 0x90, 0xF0, 0x01, 0x44, ++ 0x03, 0x74, 0x9B, 0x07, 0x99, 0x07, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0x26, 0x06, 0x90, ++ 0x07, 0x54, 0x13, 0xC4, 0x1D, 0x60, 0xFE, 0x24, 0x90, 0x22, 0x70, 0x04, 0x03, 0x74, 0x7F, 0x07, ++ 0x96, 0x07, 0x90, 0xF0, 0x44, 0xF8, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x03, 0xF8, 0x54, 0xE0, 0x9A, ++ 0x80, 0xF0, 0x02, 0x44, 0x7F, 0x07, 0x90, 0x0D, 0x80, 0xF0, 0x01, 0x74, 0x07, 0x90, 0xE4, 0x05, ++ 0x07, 0x90, 0xF0, 0x7F, 0x02, 0x44, 0xE0, 0x9C, 0x01, 0x44, 0xE0, 0xF0, 0x9D, 0x07, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0xFE, 0x54, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, ++ 0xE0, 0x54, 0x08, 0x90, 0xE0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xFB, 0x54, ++ 0x90, 0xF0, 0xF7, 0x54, 0x0F, 0x74, 0x55, 0x08, 0x56, 0x08, 0x90, 0xF0, 0x57, 0x08, 0x90, 0xF0, ++ 0x44, 0xE0, 0x54, 0xE0, 0x08, 0x90, 0xF0, 0x04, 0xE0, 0x54, 0xE0, 0x58, 0x90, 0xF0, 0x12, 0x44, ++ 0x54, 0xE0, 0x59, 0x08, 0xF0, 0x17, 0x44, 0xE0, 0xE0, 0x5A, 0x08, 0x90, 0x26, 0x44, 0xC0, 0x54, ++ 0x5B, 0x08, 0x90, 0xF0, 0x44, 0xFC, 0x54, 0xE0, 0x44, 0xE0, 0xF0, 0x01, 0x08, 0x90, 0xF0, 0x3C, ++ 0x03, 0x44, 0xE0, 0x5D, 0xF3, 0x54, 0xE0, 0xF0, 0x54, 0x08, 0x90, 0xF0, 0xF0, 0xFD, 0x54, 0xE0, ++ 0xE0, 0x07, 0x07, 0x90, 0x22, 0xF0, 0x10, 0x44, 0x7E, 0x1E, 0x08, 0x30, 0x12, 0x0F, 0x7F, 0x20, ++ 0x0C, 0x12, 0x1D, 0x0E, 0x95, 0x07, 0x90, 0xAE, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0x99, 0x07, 0x90, ++ 0xE4, 0xF0, 0xFE, 0x54, 0x08, 0xF6, 0x76, 0x78, 0xA6, 0x07, 0x90, 0xF6, 0x13, 0x13, 0x13, 0xE0, ++ 0xE0, 0x30, 0x1F, 0x54, 0x03, 0x06, 0x90, 0x0D, 0xF0, 0x02, 0x44, 0xE0, 0x74, 0xA6, 0x07, 0x90, ++ 0x07, 0x90, 0xF0, 0x08, 0x14, 0x60, 0xE0, 0x97, 0xE0, 0x95, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, ++ 0x03, 0x74, 0x97, 0x07, 0x95, 0x07, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0xAE, 0x01, 0x90, ++ 0xE0, 0xF0, 0x01, 0x44, 0x91, 0x07, 0x90, 0xFF, 0x13, 0x13, 0xC4, 0xE0, 0xEF, 0xFE, 0x01, 0x54, ++ 0x01, 0x54, 0x13, 0xC4, 0xDF, 0x54, 0xEF, 0xFD, 0x54, 0x4E, 0xED, 0xFF, 0x54, 0x33, 0xC4, 0x01, ++ 0x01, 0x90, 0x4F, 0xE0, 0xFF, 0xE0, 0xF0, 0xAE, 0xE0, 0x91, 0x07, 0x90, 0x01, 0x54, 0x13, 0xC4, ++ 0x13, 0x13, 0xEF, 0xFE, 0xFD, 0x01, 0x54, 0x13, 0xFF, 0xF7, 0x54, 0xEF, 0x01, 0x54, 0x4E, 0xED, ++ 0x54, 0x33, 0x33, 0x33, 0x01, 0x90, 0x4F, 0xF8, 0xFF, 0xE0, 0xF0, 0xAE, 0xE0, 0x91, 0x07, 0x90, ++ 0x01, 0x54, 0x13, 0xC3, 0x54, 0xC4, 0xEF, 0xFE, 0x54, 0xEF, 0xFD, 0x01, 0x4E, 0xED, 0xFF, 0xEF, ++ 0x54, 0xC4, 0x01, 0x54, 0x01, 0x90, 0x4F, 0xF0, 0x07, 0x90, 0xF0, 0xAE, 0xF0, 0x62, 0x74, 0x91, ++ 0xE0, 0x23, 0x06, 0x90, 0x90, 0xF0, 0x0F, 0x54, 0x54, 0xE0, 0x5E, 0x08, 0x07, 0x90, 0xFF, 0x01, ++ 0x54, 0xC4, 0xE0, 0xA6, 0x90, 0xFF, 0x4F, 0x01, 0x13, 0xE0, 0x23, 0x06, 0x6F, 0x01, 0x54, 0x13, ++ 0x54, 0xC4, 0x01, 0x54, 0x54, 0xE0, 0xFF, 0xF0, 0x90, 0xF0, 0x4F, 0xEF, 0x54, 0xE0, 0xA6, 0x07, ++ 0x60, 0x01, 0x64, 0x07, 0x07, 0x54, 0xE0, 0x3E, 0x37, 0x60, 0x03, 0x64, 0xE6, 0x75, 0x78, 0xD3, ++ 0xE6, 0x18, 0x00, 0x94, 0x08, 0x40, 0x00, 0x94, 0x18, 0x16, 0xE6, 0x08, 0x22, 0x16, 0x01, 0x70, ++ 0x75, 0x22, 0x5D, 0x75, 0x20, 0x7E, 0x3E, 0x5E, 0x0E, 0x12, 0x19, 0x7F, 0xAE, 0x01, 0x90, 0x1D, ++ 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0x03, 0x06, 0x90, 0x90, 0xF0, 0xFB, 0x54, 0x44, 0xE0, 0x35, 0x06, ++ 0x90, 0x22, 0xF0, 0x01, 0x54, 0xE0, 0xA6, 0x07, 0x03, 0xBF, 0xFF, 0x07, 0x76, 0x74, 0x78, 0x08, ++ 0x88, 0x76, 0x08, 0x13, 0x74, 0x78, 0xE4, 0x22, 0x22, 0xF6, 0x08, 0xF6, 0xE0, 0x99, 0x07, 0x90, ++ 0x90, 0xF0, 0x01, 0x44, 0x44, 0xE0, 0xA4, 0x07, 0x5D, 0x75, 0xF0, 0x04, 0x91, 0x5E, 0x75, 0x27, ++ 0x07, 0x08, 0x30, 0x22, 0x3C, 0x7F, 0x20, 0x7E, 0x90, 0x1D, 0x0E, 0x12, 0x03, 0x74, 0x9D, 0x07, ++ 0x9C, 0x07, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0xAE, 0x01, 0x90, 0x90, 0xF0, 0xFE, 0x54, ++ 0xF0, 0xE0, 0x02, 0x06, 0xFB, 0x54, 0xE0, 0xA3, 0xDF, 0x54, 0xE0, 0xF0, 0x75, 0x0E, 0xC2, 0xF0, ++ 0x60, 0x75, 0x01, 0x5F, 0x00, 0x22, 0x22, 0xC5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x30, 0x30, 0x31, 0x09, 0x0A, 0x58, 0x54, 0x62, 0x65, 0x53, 0x09, 0x00, 0x0A, 0x70, 0x75, 0x74, ++ 0x61, 0x57, 0x09, 0x00, 0x0A, 0x50, 0x74, 0x69, 0x4D, 0x09, 0x09, 0x00, 0x58, 0x00, 0x49, 0x44, ++ 0x09, 0x00, 0x0A, 0x00, 0x0A, 0x43, 0x47, 0x41, 0x41, 0x09, 0x09, 0x00, 0x25, 0x3D, 0x43, 0x47, ++ 0x50, 0x00, 0x20, 0x64, 0x25, 0x3D, 0x52, 0x57, 0x09, 0x00, 0x0A, 0x64, 0x0A, 0x30, 0x4B, 0x4F, ++ 0x4C, 0x09, 0x09, 0x00, 0x25, 0x20, 0x3A, 0x43, 0x09, 0x00, 0x0A, 0x64, 0x0A, 0x31, 0x4B, 0x4F, ++ 0x4B, 0x4F, 0x09, 0x00, 0x09, 0x00, 0x0A, 0x32, 0x0A, 0x33, 0x4B, 0x4F, 0x4B, 0x4F, 0x09, 0x00, ++ 0x09, 0x09, 0x0A, 0x34, 0x00, 0x64, 0x25, 0x00, 0x61, 0x72, 0x54, 0x09, 0x00, 0x0A, 0x6B, 0x63, ++ 0x6E, 0x79, 0x53, 0x09, 0x09, 0x00, 0x0A, 0x63, 0x6E, 0x77, 0x6F, 0x44, 0x45, 0x09, 0x00, 0x0A, ++ 0x0A, 0x74, 0x69, 0x78, 0x4D, 0x09, 0x09, 0x00, 0x3D, 0x4C, 0x4C, 0x44, 0x00, 0x0A, 0x64, 0x25, ++ 0x60, 0x73, 0xE5, 0x01, 0x7F, 0x20, 0x7E, 0x2A, 0x1D, 0x0E, 0x12, 0x00, 0x75, 0x21, 0x5D, 0x75, ++ 0x08, 0xD2, 0x58, 0x5E, 0xF6, 0x76, 0x78, 0xE4, 0xF6, 0x08, 0xF6, 0x08, 0x7E, 0x78, 0xF6, 0x08, ++ 0x76, 0x7C, 0x78, 0xF6, 0x24, 0x04, 0x12, 0x03, 0xAA, 0x76, 0x74, 0x78, 0x7F, 0xE6, 0x76, 0x08, ++ 0xB4, 0x0B, 0x12, 0x76, 0x06, 0x90, 0x37, 0x31, 0x54, 0xC4, 0xE0, 0x00, 0x18, 0xE0, 0x30, 0x0F, ++ 0xE0, 0x03, 0x06, 0x90, 0x3F, 0x54, 0x13, 0x13, 0x7F, 0x0D, 0xE0, 0x20, 0xB4, 0x0B, 0x12, 0x74, ++ 0x5D, 0x75, 0x06, 0x50, 0x02, 0x5E, 0x75, 0x2D, 0xC4, 0xEF, 0x20, 0xAF, 0xE0, 0x20, 0x0F, 0x54, ++ 0xEF, 0x20, 0xAF, 0x22, 0xAF, 0x1C, 0xE0, 0x20, 0x13, 0xC3, 0xEF, 0x20, 0xAF, 0x14, 0xE0, 0x20, ++ 0x13, 0xC4, 0xEF, 0x20, 0xE0, 0x20, 0x07, 0x54, 0xEF, 0x20, 0xAF, 0x0A, 0x3F, 0x54, 0x13, 0x13, ++ 0x75, 0x06, 0xE0, 0x30, 0x5E, 0x75, 0x2D, 0x5D, 0x65, 0x62, 0xE5, 0x02, 0xE5, 0x04, 0x70, 0x5E, ++ 0x60, 0x5D, 0x65, 0x61, 0x61, 0x5D, 0x85, 0x08, 0xD2, 0x62, 0x5E, 0x85, 0xA9, 0x61, 0xAA, 0x08, ++ 0xEB, 0x02, 0x12, 0x62, 0x78, 0x22, 0x08, 0xC2, 0x01, 0x54, 0xE6, 0x84, 0x9F, 0xE4, 0xC3, 0xFF, ++ 0x00, 0x94, 0x08, 0x74, 0x18, 0xFC, 0x05, 0x54, 0xFE, 0x13, 0xC3, 0xE6, 0xFF, 0x13, 0xE6, 0x08, ++ 0xF6, 0x18, 0x6C, 0xEE, 0x22, 0xF6, 0x08, 0xEF, 0x09, 0x7F, 0x20, 0x7E, 0x31, 0x1D, 0x0E, 0x12, ++ 0x24, 0x5D, 0x75, 0x68, 0x22, 0xD0, 0x5E, 0x75, 0x01, 0x0D, 0x90, 0xE4, 0x21, 0x0D, 0x90, 0xF0, ++ 0x41, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0xFF, 0x74, 0x90, 0xF0, 0x61, 0x0D, 0x54, 0xE0, 0x00, 0x0D, ++ 0x54, 0xE0, 0xF0, 0xF8, 0xF0, 0x20, 0x44, 0x9F, 0xF0, 0x18, 0x44, 0xE0, 0x20, 0x0D, 0x90, 0xE0, ++ 0xA2, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0xAA, 0x74, 0x30, 0x74, 0x02, 0x0D, 0x22, 0x0D, 0x90, 0xF0, ++ 0x05, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x20, 0x74, 0x90, 0xF0, 0x25, 0x0D, 0x9C, 0x74, 0x06, 0x0D, ++ 0x26, 0x0D, 0x90, 0xF0, 0x0A, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x89, 0x74, 0x91, 0xF0, 0x2A, 0x0D, ++ 0xF8, 0x07, 0x90, 0x2C, 0x90, 0xF0, 0x01, 0x74, 0x44, 0xE0, 0xFD, 0x07, 0x44, 0xE0, 0xF0, 0x01, ++ 0x54, 0xE0, 0xF0, 0x02, 0x08, 0x90, 0xF0, 0xFD, 0xF8, 0x54, 0xE0, 0x03, 0x90, 0xF0, 0x04, 0x44, ++ 0x54, 0xE0, 0x10, 0x07, 0xF0, 0x54, 0xC4, 0x0F, 0x0B, 0x0A, 0x90, 0x04, 0x10, 0x07, 0x90, 0xF0, ++ 0x0F, 0x54, 0xC4, 0xE0, 0x0F, 0x07, 0x90, 0xFF, 0xC4, 0x0F, 0x54, 0xE0, 0x90, 0x4F, 0xF0, 0x54, ++ 0x90, 0xF0, 0x0A, 0x0A, 0xC4, 0xE0, 0x0F, 0x07, 0x0A, 0x90, 0x0F, 0x54, 0x0A, 0x90, 0xF0, 0x09, ++ 0xF0, 0x01, 0x74, 0x0C, 0xE0, 0x01, 0x0A, 0x90, 0xE0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, ++ 0x90, 0xF0, 0xFE, 0x54, 0x44, 0xE0, 0x08, 0x0A, 0x44, 0xE0, 0xF0, 0x01, 0x54, 0xE0, 0xF0, 0x02, ++ 0x08, 0x90, 0xF0, 0xFD, 0x01, 0x44, 0xE0, 0x60, 0x02, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xF0, ++ 0x61, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x13, 0x74, 0x54, 0xE0, 0x62, 0x08, 0xF0, 0x03, 0x44, 0xF8, ++ 0xE0, 0x63, 0x08, 0x90, 0x90, 0xF0, 0xDC, 0x74, 0x44, 0xE0, 0x67, 0x08, 0x44, 0xE0, 0xF0, 0x01, ++ 0x54, 0xE0, 0xF0, 0x02, 0x07, 0x90, 0xF0, 0xFD, 0x0F, 0x54, 0xE0, 0x10, 0x04, 0xF0, 0x54, 0xC4, ++ 0xF0, 0x6A, 0x08, 0x90, 0xE0, 0x10, 0x07, 0x90, 0xFF, 0x0F, 0x54, 0xC4, 0xE0, 0x0F, 0x07, 0x90, ++ 0x54, 0xC4, 0x0F, 0x54, 0x08, 0x90, 0x4F, 0xF0, 0x07, 0x90, 0xF0, 0x69, 0x54, 0xC4, 0xE0, 0x0F, ++ 0x68, 0x08, 0x90, 0x0F, 0x6B, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x01, 0x74, 0x0B, 0x74, 0x52, 0x08, ++ 0x51, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x03, 0x74, 0x0A, 0x74, 0x52, 0x08, 0x51, 0x08, 0x90, 0xF0, ++ 0x90, 0xF0, 0x02, 0x74, 0x44, 0xE0, 0x39, 0x08, 0x08, 0x90, 0xF0, 0x02, 0x01, 0x44, 0xE0, 0x40, ++ 0x02, 0x44, 0xE0, 0xF0, 0x41, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x04, 0x44, 0xE0, ++ 0xE0, 0x42, 0x08, 0x90, 0xE0, 0xF0, 0x01, 0x44, 0x90, 0xF0, 0x04, 0x44, 0x44, 0xE0, 0x43, 0x08, ++ 0x08, 0x90, 0xF0, 0x01, 0x01, 0x44, 0xE0, 0x3E, 0x02, 0x44, 0xE0, 0xF0, 0xFB, 0x54, 0xE0, 0xF0, ++ 0xFD, 0x54, 0xE0, 0xF0, 0x3C, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, ++ 0xE0, 0x3D, 0x08, 0x90, 0xE0, 0xF0, 0x9F, 0x54, 0x05, 0x44, 0xE0, 0x54, 0x3C, 0x08, 0x90, 0xF0, ++ 0xF0, 0xFD, 0x54, 0xE0, 0xF0, 0xFB, 0x54, 0xE0, 0xE0, 0xA7, 0x07, 0x90, 0xE0, 0xF0, 0x04, 0x44, ++ 0xE0, 0xF0, 0x10, 0x44, 0x90, 0xF0, 0x01, 0x44, 0x44, 0xE0, 0xA8, 0x07, 0x44, 0xE0, 0xF0, 0x04, ++ 0x44, 0xE0, 0xF0, 0x10, 0x54, 0xE0, 0xF0, 0x01, 0x54, 0xE0, 0xF0, 0xFB, 0x54, 0xE0, 0xF0, 0xEF, ++ 0x07, 0x90, 0xF0, 0xFE, 0x01, 0x44, 0xE0, 0x95, 0x94, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, ++ 0xE0, 0x96, 0x07, 0x90, 0x03, 0x44, 0xF8, 0x54, 0x97, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x03, 0x74, ++ 0x54, 0xE0, 0x95, 0x07, 0x07, 0x90, 0xF0, 0xFE, 0x01, 0x44, 0xE0, 0x99, 0x98, 0x07, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x9A, 0x07, 0x90, 0x01, 0x44, 0xF8, 0x54, 0x9B, 0x07, 0x90, 0xF0, ++ 0x90, 0xF0, 0x03, 0x74, 0x54, 0xE0, 0x99, 0x07, 0x08, 0x90, 0xF0, 0xFE, 0xF0, 0x03, 0x74, 0x14, ++ 0xE0, 0x12, 0x08, 0x90, 0xE4, 0xF0, 0xFE, 0x54, 0x08, 0x90, 0xFC, 0xFD, 0x01, 0x64, 0xE0, 0x14, ++ 0xED, 0xC3, 0x11, 0x60, 0x94, 0xEC, 0xFF, 0x94, 0x00, 0x08, 0x50, 0x00, 0x01, 0x00, 0xBD, 0x0D, ++ 0x7E, 0xE7, 0x80, 0x0C, 0x12, 0x85, 0x7F, 0x20, 0x08, 0x90, 0x0D, 0x0D, 0xF0, 0x43, 0x74, 0x1C, ++ 0xF0, 0x1E, 0x08, 0x90, 0xF0, 0x20, 0x08, 0x90, 0xF0, 0x22, 0x08, 0x90, 0x74, 0x09, 0x08, 0x90, ++ 0x08, 0x90, 0xF0, 0x03, 0x08, 0x90, 0xF0, 0x0B, 0x08, 0x90, 0xF0, 0x0C, 0xFC, 0xE4, 0xF0, 0x0D, ++ 0xBD, 0x0D, 0x00, 0xFD, 0xED, 0x0C, 0x01, 0x00, 0x70, 0x4C, 0x80, 0x64, 0x1C, 0x08, 0x90, 0xF4, ++ 0x90, 0xF0, 0x42, 0x74, 0x90, 0xF0, 0x1E, 0x08, 0x90, 0xF0, 0x20, 0x08, 0x90, 0xF0, 0x22, 0x08, ++ 0x04, 0x74, 0x09, 0x08, 0x0B, 0x08, 0x90, 0xF0, 0x0C, 0x08, 0x90, 0xF0, 0x0D, 0x08, 0x90, 0xF0, ++ 0x12, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0x74, 0x24, 0x08, 0x90, 0x07, 0x90, 0xF0, 0x12, ++ 0xF0, 0x0D, 0x74, 0xFB, 0xE0, 0x07, 0x07, 0x90, 0x22, 0xF0, 0x10, 0x44, 0xE0, 0x23, 0x06, 0x90, ++ 0x54, 0x13, 0x13, 0xFF, 0x0C, 0x92, 0x13, 0x3F, 0xE0, 0x27, 0x06, 0x90, 0x30, 0x03, 0xE0, 0x30, ++ 0x06, 0x90, 0x1A, 0x0C, 0xE0, 0x20, 0xE0, 0x27, 0x26, 0x06, 0x90, 0x3B, 0xE0, 0xA3, 0xFE, 0xE0, ++ 0xC3, 0xCE, 0x02, 0x78, 0xD8, 0x13, 0xCE, 0x13, 0x28, 0xE0, 0x20, 0xF9, 0x0D, 0x90, 0x0C, 0xC2, ++ 0xF0, 0x0F, 0x74, 0x01, 0x04, 0x21, 0x0D, 0x90, 0xF9, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0xE4, 0x74, ++ 0xB1, 0x74, 0xFA, 0x07, 0x0C, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0x38, 0x74, 0x90, 0xF0, 0x2C, 0x0D, ++ 0x26, 0x80, 0xA6, 0x00, 0x0D, 0x90, 0x0C, 0xD2, 0xF0, 0x0F, 0x74, 0x21, 0x04, 0x01, 0x0D, 0x90, ++ 0xF9, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0xB1, 0x74, 0xE4, 0x74, 0xFA, 0x07, 0x2C, 0x0D, 0x90, 0xF0, ++ 0x90, 0xF0, 0x38, 0x74, 0x90, 0xF0, 0x0C, 0x0D, 0x90, 0xE0, 0xA7, 0x00, 0xA2, 0xF0, 0x45, 0x08, ++ 0x54, 0x33, 0xE4, 0x0C, 0xE0, 0x25, 0xFC, 0x01, 0x90, 0xFE, 0xE0, 0x25, 0x54, 0xE0, 0x23, 0x06, ++ 0xEC, 0xF0, 0x4E, 0xFB, 0x54, 0x33, 0x33, 0x33, 0x54, 0xE0, 0xFF, 0xF8, 0x22, 0xF0, 0x4F, 0xF7, ++ 0xA1, 0x02, 0x08, 0x20, 0x7F, 0x20, 0x7E, 0x5C, 0x1D, 0x0E, 0x12, 0x11, 0xE0, 0x00, 0x0D, 0x90, ++ 0x90, 0xF0, 0xF8, 0x54, 0x54, 0xE0, 0x20, 0x0D, 0x81, 0x78, 0xF0, 0xF8, 0x76, 0x08, 0xF4, 0x76, ++ 0xAA, 0x0D, 0x90, 0x24, 0x0F, 0x54, 0xC4, 0xE0, 0xAB, 0x0D, 0x90, 0xFF, 0x0F, 0x54, 0xC4, 0xE0, ++ 0x33, 0xE4, 0xFF, 0x2F, 0xFD, 0x00, 0x24, 0xCF, 0xFC, 0x04, 0x34, 0xEF, 0xE0, 0x0B, 0x07, 0x90, ++ 0xA4, 0x20, 0xF0, 0x75, 0xF0, 0x45, 0xEC, 0xFF, 0x4F, 0xED, 0xF6, 0x08, 0x78, 0xE4, 0xF6, 0x08, ++ 0x0D, 0x90, 0xF6, 0x7D, 0x10, 0x44, 0xE0, 0xA9, 0x20, 0x44, 0xE0, 0xF0, 0x47, 0x08, 0x90, 0xF0, ++ 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0x08, 0x44, 0xE0, 0xE0, 0x48, 0x08, 0x90, 0x04, 0x44, 0xF3, 0x54, ++ 0x4C, 0x08, 0x90, 0xF0, 0x44, 0x0F, 0x54, 0xE0, 0x08, 0x90, 0xF0, 0x20, 0x70, 0x44, 0xE0, 0x4B, ++ 0x80, 0x44, 0xE0, 0xF0, 0x47, 0x08, 0x90, 0xF0, 0xF0, 0xF7, 0x54, 0xE0, 0xE0, 0x00, 0x06, 0x90, ++ 0x30, 0x0F, 0x54, 0xC4, 0x2C, 0x91, 0x04, 0xE0, 0x06, 0x90, 0x1E, 0x80, 0xE0, 0x20, 0xE0, 0x27, ++ 0x13, 0x13, 0xE0, 0x20, 0x90, 0xFF, 0x01, 0x54, 0xFE, 0xE0, 0x23, 0x06, 0x01, 0x54, 0x13, 0x13, ++ 0x90, 0x05, 0x60, 0x6F, 0x2F, 0x91, 0x27, 0x06, 0xF4, 0x76, 0x81, 0x78, 0x80, 0x24, 0x76, 0x08, ++ 0x12, 0x81, 0x7F, 0x5B, 0x54, 0x50, 0xB4, 0x0B, 0xF4, 0x76, 0x81, 0x78, 0x90, 0x24, 0x76, 0x08, ++ 0xC3, 0xE0, 0x4F, 0x08, 0x24, 0x50, 0x05, 0x94, 0x54, 0xE6, 0x84, 0x78, 0x06, 0x90, 0xFF, 0x01, ++ 0x13, 0xFD, 0xE0, 0x23, 0x6F, 0x01, 0x54, 0x13, 0x60, 0xE4, 0x01, 0x70, 0x35, 0x06, 0x90, 0x07, ++ 0xF0, 0x08, 0x44, 0xE0, 0x13, 0xE6, 0x84, 0x78, 0x38, 0x91, 0x0C, 0x92, 0x19, 0x7F, 0x20, 0x7E, ++ 0x90, 0x1D, 0x0E, 0x12, 0x13, 0xE0, 0x23, 0x06, 0x30, 0x3F, 0x54, 0x13, 0x20, 0x7E, 0x07, 0xE0, ++ 0x0E, 0x12, 0x1F, 0x7F, 0x7F, 0x20, 0x7E, 0x1D, 0x1D, 0x0E, 0x12, 0x21, 0x06, 0x40, 0xF7, 0xB1, ++ 0x75, 0x26, 0x5D, 0x75, 0x90, 0x22, 0x1D, 0x5E, 0xFF, 0xE0, 0x4F, 0x08, 0x94, 0x80, 0x64, 0xD3, ++ 0x78, 0x0C, 0x40, 0x85, 0x0A, 0x94, 0xE6, 0x7D, 0x80, 0x06, 0x03, 0x50, 0xC3, 0x22, 0xC3, 0x0E, ++ 0x94, 0x80, 0x64, 0xEF, 0xE4, 0x04, 0x50, 0x83, 0xD3, 0xF6, 0x7D, 0x78, 0x20, 0x08, 0x30, 0x22, ++ 0x23, 0x7F, 0x20, 0x7E, 0x78, 0x1D, 0x0E, 0x12, 0x08, 0x00, 0x76, 0x76, 0x85, 0x78, 0x0A, 0x76, ++ 0x0D, 0x90, 0x07, 0x76, 0x07, 0x44, 0xE0, 0x00, 0x20, 0x0D, 0x90, 0xF0, 0xF0, 0x07, 0x44, 0xE0, ++ 0x18, 0xE6, 0x77, 0x78, 0xF6, 0x50, 0x70, 0x46, 0x78, 0x0A, 0x76, 0x08, 0x94, 0xD3, 0xE6, 0x85, ++ 0x90, 0x23, 0x40, 0x00, 0xD3, 0xE0, 0x4F, 0x08, 0x1A, 0x40, 0x0A, 0x94, 0x07, 0x54, 0xE6, 0x16, ++ 0x00, 0x0D, 0x90, 0xFF, 0x4F, 0xF8, 0x54, 0xE0, 0x07, 0x54, 0xE6, 0xF0, 0x20, 0x0D, 0x90, 0xFF, ++ 0x4F, 0xF8, 0x54, 0xE0, 0x20, 0x7E, 0x22, 0xF0, 0x85, 0x78, 0x29, 0x7F, 0x00, 0x7C, 0xFD, 0xE6, ++ 0x7E, 0x0D, 0x0D, 0x12, 0x90, 0x33, 0x7F, 0x20, 0xFD, 0xE0, 0x4F, 0x08, 0x0D, 0x12, 0x00, 0x7C, ++ 0x28, 0x5D, 0x75, 0x0D, 0x22, 0x1F, 0x5E, 0x75, 0x77, 0x7F, 0x20, 0x7E, 0x90, 0x1D, 0x0E, 0x12, ++ 0x54, 0xE0, 0xAE, 0x01, 0x06, 0x90, 0xF0, 0xC0, 0xFB, 0x54, 0xE0, 0x03, 0x78, 0x78, 0xE4, 0xF0, ++ 0x90, 0xF6, 0x08, 0xF6, 0x44, 0xE0, 0x99, 0x07, 0x20, 0xAF, 0xF0, 0x01, 0x0F, 0x54, 0xC4, 0xEF, ++ 0xAF, 0x64, 0xE0, 0x20, 0xE0, 0x20, 0xEF, 0x20, 0xEF, 0x20, 0xAF, 0x5E, 0xE0, 0x20, 0x13, 0xC3, ++ 0xEF, 0x20, 0xAF, 0x56, 0x3F, 0x54, 0x13, 0x13, 0x80, 0x02, 0xE0, 0x30, 0x00, 0x06, 0x90, 0x4A, ++ 0x0F, 0x54, 0xC4, 0xE0, 0xE0, 0x2F, 0xE0, 0x20, 0x07, 0x54, 0x13, 0xC4, 0xE0, 0x27, 0xE0, 0x30, ++ 0x78, 0xE0, 0xA3, 0xFE, 0x13, 0xC3, 0xCE, 0x06, 0xF9, 0xD8, 0x13, 0xCE, 0x90, 0x17, 0xE0, 0x20, ++ 0xFF, 0xE0, 0x31, 0x06, 0x3F, 0x54, 0x13, 0x13, 0xB1, 0x0B, 0xE0, 0x20, 0x75, 0x11, 0x50, 0xF7, ++ 0x5E, 0x75, 0x24, 0x5D, 0x7C, 0x78, 0x22, 0xD0, 0x0B, 0x60, 0x16, 0xE6, 0x07, 0x40, 0xF7, 0xB1, ++ 0x75, 0x28, 0x5D, 0x75, 0x75, 0x22, 0x1F, 0x5E, 0x5E, 0x75, 0x2D, 0x5D, 0x08, 0x30, 0x22, 0x02, ++ 0x7F, 0x20, 0x7E, 0x55, 0x1D, 0x0E, 0x12, 0x57, 0x00, 0x76, 0x76, 0x78, 0x90, 0x64, 0x76, 0x08, ++ 0x44, 0xE0, 0x27, 0x08, 0x08, 0x90, 0xF0, 0x08, 0x07, 0x44, 0xE0, 0x4B, 0x4A, 0x08, 0x90, 0xF0, ++ 0xF0, 0x03, 0x44, 0xE0, 0xE0, 0x29, 0x08, 0x90, 0x02, 0x44, 0xF8, 0x54, 0x2A, 0x08, 0x90, 0xF0, ++ 0x44, 0xE3, 0x54, 0xE0, 0x08, 0x90, 0xF0, 0x14, 0xF8, 0x54, 0xE0, 0x2E, 0x90, 0xF0, 0x02, 0x44, ++ 0x07, 0x74, 0x61, 0x08, 0x62, 0x08, 0x90, 0xF0, 0x44, 0xF8, 0x54, 0xE0, 0x08, 0x90, 0xF0, 0x03, ++ 0x74, 0xE4, 0xE0, 0x63, 0xF7, 0xB1, 0xF0, 0xDC, 0x5D, 0x75, 0x07, 0x50, 0x98, 0x5E, 0x75, 0x26, ++ 0xE6, 0x77, 0x78, 0x22, 0x06, 0x70, 0x46, 0x18, 0x75, 0x2A, 0x5D, 0x75, 0x30, 0x22, 0xAB, 0x5E, ++ 0x20, 0x7E, 0x32, 0x08, 0x0E, 0x12, 0x51, 0x7F, 0x76, 0x76, 0x78, 0x1D, 0x14, 0x76, 0x08, 0x00, ++ 0xE0, 0x2A, 0x08, 0x90, 0x90, 0xF0, 0xFD, 0x54, 0x54, 0xE0, 0x2D, 0x08, 0x08, 0x90, 0xF0, 0xFB, ++ 0xFD, 0x54, 0xE0, 0x31, 0x61, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x07, 0x74, 0x54, 0xE0, 0x62, 0x08, ++ 0xF0, 0x03, 0x44, 0xF8, 0xB1, 0x47, 0x2D, 0x12, 0x7F, 0x07, 0x40, 0xF7, 0xB4, 0x0B, 0x12, 0x7A, ++ 0x5D, 0x75, 0x07, 0x50, 0x98, 0x5E, 0x75, 0x26, 0xE6, 0x77, 0x78, 0x22, 0x2E, 0x70, 0x46, 0x18, ++ 0xE0, 0x4E, 0x08, 0x90, 0x50, 0x0D, 0x94, 0xC3, 0x27, 0x5D, 0x75, 0x08, 0x80, 0x2E, 0x5E, 0x75, ++ 0x2A, 0x5D, 0x75, 0x06, 0xE4, 0x0B, 0x5E, 0x75, 0xF0, 0x34, 0x08, 0x90, 0x44, 0x9F, 0x54, 0xE0, ++ 0x08, 0x90, 0xF0, 0x40, 0x06, 0x70, 0xE0, 0x37, 0x75, 0x28, 0x5D, 0x75, 0x20, 0x22, 0x1F, 0x5E, ++ 0xC4, 0x21, 0x02, 0x08, 0x3B, 0x7F, 0x20, 0x7E, 0x78, 0x1D, 0x0E, 0x12, 0x08, 0x00, 0x76, 0x76, ++ 0x08, 0x90, 0x05, 0x76, 0x01, 0x44, 0xE0, 0x25, 0x02, 0x44, 0xE0, 0xF0, 0x27, 0x08, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xFB, 0x54, 0xE0, 0xF0, 0xF7, 0x54, 0xE0, ++ 0xE0, 0x28, 0x08, 0x90, 0x01, 0x44, 0xF8, 0x54, 0x27, 0x08, 0x90, 0xF0, 0xF0, 0x04, 0x44, 0xE0, ++ 0xF0, 0x08, 0x44, 0xE0, 0xE0, 0x29, 0x08, 0x90, 0x04, 0x44, 0xF8, 0x54, 0x2D, 0x08, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xFB, 0x54, 0xE0, 0xF0, 0x04, 0x44, 0xE0, ++ 0xE0, 0x2E, 0x08, 0x90, 0x04, 0x44, 0xF8, 0x54, 0x2F, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, ++ 0xF0, 0x02, 0x44, 0xE0, 0xE0, 0x30, 0x08, 0x90, 0x05, 0x44, 0xE0, 0x54, 0x2F, 0x08, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xE0, 0x2A, 0x08, 0x90, 0x14, 0x44, 0xE3, 0x54, ++ 0x02, 0x44, 0xE0, 0xF0, 0x2B, 0x08, 0x90, 0xF0, 0xF0, 0x15, 0x74, 0xE0, 0xE0, 0x2A, 0x08, 0x90, ++ 0x90, 0xF0, 0x01, 0x44, 0x44, 0xE0, 0x31, 0x08, 0x08, 0x90, 0xF0, 0x04, 0xF0, 0x40, 0x74, 0x33, ++ 0xE0, 0x2C, 0x08, 0x90, 0xE0, 0xF0, 0x01, 0x44, 0x02, 0x44, 0xF9, 0x54, 0x25, 0x08, 0x90, 0xF0, ++ 0xF0, 0xFD, 0x54, 0xE0, 0xE0, 0x27, 0x08, 0x90, 0x90, 0xF0, 0xFD, 0x54, 0x54, 0xE0, 0x2D, 0x08, ++ 0x08, 0x90, 0xF0, 0xFD, 0xFB, 0x54, 0xE0, 0x31, 0x08, 0x90, 0xE4, 0xF0, 0x54, 0xE0, 0xF0, 0x34, ++ 0x44, 0xE0, 0xF0, 0x9F, 0x54, 0xE0, 0xF0, 0x10, 0xF0, 0x01, 0x44, 0xF0, 0x74, 0x35, 0x08, 0x90, ++ 0x08, 0x90, 0xF0, 0x7F, 0xF0, 0xFF, 0x74, 0x36, 0x34, 0x08, 0x90, 0xE4, 0x9F, 0x54, 0xE0, 0xF0, ++ 0x10, 0x44, 0xE0, 0xF0, 0xF0, 0x54, 0xE0, 0xF0, 0x35, 0x08, 0x90, 0xF0, 0xE4, 0xF0, 0xEC, 0x74, ++ 0xF0, 0x36, 0x08, 0x90, 0xF0, 0x34, 0x08, 0x90, 0xF0, 0x9F, 0x54, 0xE0, 0xF0, 0x10, 0x44, 0xE0, ++ 0x44, 0xF0, 0x54, 0xE0, 0x85, 0x78, 0xF0, 0x02, 0x33, 0x33, 0x33, 0xE6, 0xC3, 0xFF, 0xF8, 0x54, ++ 0xFF, 0x9F, 0xE0, 0x74, 0x25, 0xE0, 0x25, 0xE6, 0xEF, 0xC3, 0xFE, 0xE0, 0x35, 0x08, 0x90, 0x9E, ++ 0x08, 0x90, 0xE4, 0xF0, 0x08, 0x90, 0xF0, 0x36, 0x54, 0xE0, 0xF0, 0x34, 0xF0, 0x40, 0x44, 0x9F, ++ 0xF0, 0x10, 0x44, 0xE0, 0x74, 0x35, 0x08, 0x90, 0x90, 0xE4, 0xF0, 0x40, 0x90, 0xF0, 0x36, 0x08, ++ 0x90, 0xF0, 0x34, 0x08, 0x54, 0xE0, 0x2A, 0x08, 0x08, 0x90, 0xF0, 0xFE, 0x01, 0x44, 0xE0, 0x47, ++ 0x04, 0x44, 0xE0, 0xF0, 0x48, 0x08, 0x90, 0xF0, 0x44, 0xFC, 0x54, 0xE0, 0x08, 0x90, 0xF0, 0x01, ++ 0xF0, 0x54, 0xE0, 0x4C, 0x90, 0xF0, 0x04, 0x44, 0x54, 0xE0, 0x4B, 0x08, 0xF0, 0x06, 0x44, 0xF8, ++ 0xF0, 0x08, 0x44, 0xE0, 0xE0, 0x4A, 0x08, 0x90, 0x01, 0x44, 0xFC, 0x54, 0x47, 0x08, 0x90, 0xF0, ++ 0xF0, 0xFB, 0x54, 0xE0, 0x50, 0xF7, 0x25, 0x12, 0x26, 0x5D, 0x75, 0x07, 0x22, 0x98, 0x5E, 0x75, ++ 0x18, 0xE6, 0x77, 0x78, 0x90, 0x33, 0x70, 0x46, 0xE0, 0xF0, 0x34, 0x08, 0x40, 0x44, 0x9F, 0x54, ++ 0x7F, 0x20, 0x7E, 0xF0, 0xC0, 0x06, 0xC0, 0x41, 0x37, 0x08, 0x90, 0x07, 0x08, 0x90, 0xFE, 0xE0, ++ 0xEE, 0xFD, 0xE0, 0x38, 0x07, 0xD0, 0xED, 0xFC, 0x0D, 0x12, 0x06, 0xD0, 0x2A, 0x5D, 0x75, 0x0D, ++ 0x78, 0x0B, 0x5E, 0x75, 0x08, 0x01, 0x76, 0x7A, 0x30, 0x22, 0xF4, 0x76, 0x20, 0x7E, 0x73, 0x08, ++ 0x0E, 0x12, 0x4B, 0x7F, 0x76, 0x76, 0x78, 0x1D, 0x0A, 0x76, 0x08, 0x00, 0xE0, 0x27, 0x08, 0x90, ++ 0xE0, 0xF0, 0x04, 0x44, 0x90, 0xF0, 0x08, 0x44, 0x54, 0xE0, 0x29, 0x08, 0xF0, 0x04, 0x44, 0xF8, ++ 0xE0, 0x2A, 0x08, 0x90, 0x10, 0x44, 0xE3, 0x54, 0x02, 0x44, 0xE0, 0xF0, 0x2D, 0x08, 0x90, 0xF0, ++ 0xF0, 0xFB, 0x54, 0xE0, 0xE0, 0x2E, 0x08, 0x90, 0x03, 0x44, 0xF8, 0x54, 0x2F, 0x08, 0x90, 0xF0, ++ 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0x31, 0x08, 0x90, 0xE0, 0xF0, 0xE7, 0x54, 0xE0, 0xF0, 0x01, 0x44, ++ 0x90, 0xF0, 0xFD, 0x54, 0x74, 0xE0, 0x32, 0x08, 0x08, 0x90, 0xF0, 0xCD, 0xF0, 0x04, 0x74, 0x61, ++ 0xE0, 0x62, 0x08, 0x90, 0x03, 0x44, 0xF8, 0x54, 0x63, 0x08, 0x90, 0xF0, 0xDC, 0x74, 0xE4, 0xE0, ++ 0xF7, 0x25, 0x12, 0xF0, 0x7A, 0x7F, 0x07, 0x40, 0x50, 0xB4, 0x0B, 0x12, 0x26, 0x5D, 0x75, 0x07, ++ 0x22, 0x98, 0x5E, 0x75, 0x18, 0xE6, 0x77, 0x78, 0x90, 0x0F, 0x70, 0x46, 0xC3, 0xE0, 0x4E, 0x08, ++ 0x06, 0x50, 0x17, 0x94, 0x75, 0x27, 0x5D, 0x75, 0x30, 0x22, 0x9F, 0x5E, 0x20, 0x7E, 0x3E, 0x08, ++ 0x0E, 0x12, 0x5D, 0x7F, 0x76, 0x76, 0x78, 0x1D, 0x05, 0x76, 0x08, 0x00, 0xE0, 0x29, 0x06, 0x90, ++ 0x3F, 0x54, 0x13, 0x13, 0x90, 0x52, 0xE0, 0x30, 0x54, 0xE0, 0x02, 0x0D, 0xF0, 0x30, 0x44, 0x8F, ++ 0xE0, 0x22, 0x0D, 0x90, 0x30, 0x44, 0x8F, 0x54, 0x05, 0x0D, 0x90, 0xF0, 0x44, 0x8F, 0x54, 0xE0, ++ 0x0D, 0x90, 0xF0, 0x20, 0x8F, 0x54, 0xE0, 0x25, 0x22, 0xF0, 0x20, 0x44, 0xE0, 0x29, 0x06, 0x90, ++ 0x54, 0x13, 0x13, 0xFF, 0x0D, 0xE0, 0x30, 0x3F, 0xFC, 0xE4, 0x1A, 0x71, 0x20, 0x7E, 0xFD, 0x33, ++ 0x0D, 0x12, 0x65, 0x7F, 0xE6, 0x77, 0x78, 0x0D, 0x0D, 0x70, 0x46, 0x18, 0x21, 0x7F, 0x20, 0x7E, ++ 0x75, 0x1D, 0x0E, 0x12, 0x5E, 0x75, 0x2B, 0x5D, 0x0A, 0x7F, 0x22, 0x7A, 0x06, 0x7D, 0x0D, 0x7E, ++ 0x0C, 0xD2, 0x0D, 0x7C, 0x83, 0x8E, 0x82, 0x8F, 0x0F, 0x54, 0xC4, 0xE0, 0x40, 0x06, 0x94, 0xD3, ++ 0x4E, 0x08, 0x90, 0x36, 0x50, 0x19, 0x94, 0xE0, 0x8C, 0x82, 0x8D, 0x2E, 0xC4, 0xFD, 0xE0, 0x83, ++ 0xED, 0xFC, 0x0F, 0x54, 0xEC, 0xFD, 0x0F, 0x54, 0xC4, 0x0F, 0x54, 0x14, 0xF0, 0x4D, 0xF0, 0x54, ++ 0xFF, 0xE0, 0x82, 0x8F, 0xFE, 0x0F, 0x54, 0xC4, 0xFF, 0x0F, 0x54, 0xEF, 0x0F, 0x54, 0x14, 0xEE, ++ 0x4F, 0xF0, 0x54, 0xC4, 0x90, 0x0C, 0xC2, 0xF0, 0x90, 0xE0, 0x06, 0x0D, 0x90, 0xF0, 0x26, 0x0D, ++ 0x90, 0xE0, 0x0A, 0x0D, 0xA2, 0xF0, 0x2A, 0x0D, 0x20, 0x7E, 0x22, 0x0C, 0x0E, 0x12, 0x68, 0x7F, ++ 0x4F, 0x08, 0x90, 0x1D, 0xF6, 0x7E, 0x78, 0xE0, 0xE0, 0x29, 0x08, 0x90, 0x90, 0xF0, 0xF8, 0x54, ++ 0x54, 0xE0, 0x2A, 0x08, 0xF0, 0x08, 0x44, 0xE3, 0xE0, 0x2E, 0x08, 0x90, 0x02, 0x44, 0xF8, 0x54, ++ 0x2D, 0x08, 0x90, 0xF0, 0xF0, 0xFB, 0x54, 0xE0, 0x74, 0x61, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x07, ++ 0xF8, 0x54, 0xE0, 0x62, 0x90, 0xF0, 0x05, 0x44, 0xE4, 0xE0, 0x63, 0x08, 0x12, 0xF0, 0xDC, 0x74, ++ 0x07, 0x50, 0xF7, 0x25, 0x75, 0x26, 0x5D, 0x75, 0x75, 0x22, 0x98, 0x5E, 0x5E, 0x75, 0x2C, 0x5D, ++ 0xF6, 0x01, 0x90, 0x1D, 0xFF, 0x70, 0x54, 0xE0, 0xE0, 0x4B, 0x08, 0x90, 0xF0, 0x4F, 0x8F, 0x54, ++ 0xE0, 0xF6, 0x01, 0x90, 0x90, 0xFF, 0x0C, 0x54, 0x54, 0xE0, 0x4A, 0x08, 0x90, 0xF0, 0x4F, 0xF3, ++ 0x90, 0xE0, 0xF6, 0x01, 0xE0, 0x30, 0x4C, 0x08, 0x0F, 0x54, 0xE0, 0x06, 0xE0, 0x06, 0x80, 0xF0, ++ 0x20, 0x44, 0x0F, 0x54, 0xF6, 0x01, 0x90, 0xF0, 0x48, 0x08, 0x90, 0xE0, 0xE0, 0x07, 0xE1, 0x30, ++ 0x08, 0x44, 0xF3, 0x54, 0x54, 0xE0, 0x22, 0xF0, 0xF0, 0x04, 0x44, 0xF3, 0x02, 0x08, 0x20, 0x22, ++ 0x20, 0x7E, 0xE6, 0x81, 0x0E, 0x12, 0x70, 0x7F, 0x7C, 0x78, 0xE4, 0x1D, 0x23, 0x06, 0x90, 0xF6, ++ 0xF0, 0x0F, 0x54, 0xE0, 0xE0, 0x26, 0x06, 0x90, 0x07, 0x54, 0x13, 0xC4, 0x1D, 0x60, 0xFE, 0x24, ++ 0x90, 0x22, 0x70, 0x04, 0x03, 0x74, 0x7F, 0x07, 0x96, 0x07, 0x90, 0xF0, 0x44, 0xF8, 0x54, 0xE0, ++ 0x07, 0x90, 0xF0, 0x03, 0xF8, 0x54, 0xE0, 0x9A, 0x80, 0xF0, 0x02, 0x44, 0x7F, 0x07, 0x90, 0x0D, ++ 0x80, 0xF0, 0x01, 0x74, 0x07, 0x90, 0xE4, 0x05, 0x07, 0x90, 0xF0, 0x7F, 0x08, 0x44, 0xE0, 0xA7, ++ 0x20, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xF0, 0xA8, 0x07, 0x90, 0xF0, 0xF0, 0x08, 0x44, 0xE0, ++ 0xF0, 0x20, 0x44, 0xE0, 0xF0, 0x02, 0x44, 0xE0, 0xE0, 0x99, 0x07, 0x90, 0x90, 0xF0, 0xFE, 0x54, ++ 0x54, 0xE0, 0xA8, 0x07, 0x54, 0xE0, 0xF0, 0xF7, 0x54, 0xE0, 0xF0, 0xDF, 0x01, 0x90, 0xF0, 0xFD, ++ 0x13, 0xC4, 0xE0, 0xF6, 0x01, 0x54, 0x13, 0x13, 0x30, 0xF7, 0x01, 0x90, 0xFF, 0xE0, 0x0E, 0xE0, ++ 0xE0, 0x4F, 0x08, 0x90, 0xE5, 0xA4, 0xF0, 0x8F, 0x01, 0x80, 0x04, 0xF0, 0x4D, 0x08, 0x90, 0xE0, ++ 0x48, 0x08, 0x90, 0xF0, 0x44, 0xF3, 0x54, 0xE0, 0x08, 0x90, 0xF0, 0x04, 0xF3, 0x54, 0xE0, 0x4A, ++ 0x4C, 0x08, 0x90, 0xF0, 0x44, 0x0F, 0x54, 0xE0, 0x08, 0x90, 0xF0, 0x20, 0x70, 0x44, 0xE0, 0x4B, ++ 0x80, 0x44, 0xE0, 0xF0, 0x25, 0x12, 0x22, 0xF0, 0x75, 0x07, 0x50, 0xF7, 0x5E, 0x75, 0x26, 0x5D, ++ 0x5F, 0x75, 0x22, 0x98, 0x6F, 0x60, 0x75, 0x02, 0x75, 0x26, 0x5D, 0x75, 0x73, 0x75, 0x98, 0x5E, ++ 0x20, 0x7E, 0x22, 0x01, 0x0E, 0x12, 0x7E, 0x7F, 0xFB, 0x07, 0x90, 0x1D, 0x90, 0xF0, 0x01, 0x74, ++ 0x3F, 0x74, 0xA8, 0x07, 0x99, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0xE0, 0xAE, 0x01, 0x90, ++ 0x90, 0xF0, 0xC0, 0x54, 0x54, 0xE0, 0x03, 0x06, 0x54, 0xE0, 0xF0, 0xFB, 0x0E, 0xC2, 0xF0, 0xDF, ++ 0x74, 0x20, 0x06, 0x90, 0x74, 0xA3, 0xF0, 0x80, 0x08, 0x90, 0xF0, 0xFF, 0xF0, 0xE4, 0xE0, 0x45, ++ 0x75, 0x01, 0x5F, 0x75, 0x90, 0x22, 0xC5, 0x60, 0x44, 0xE0, 0x27, 0x08, 0x02, 0x7D, 0xF0, 0x08, ++ 0x34, 0x08, 0x90, 0xE4, 0x9F, 0x54, 0xE0, 0xF0, 0xEF, 0x54, 0xE0, 0xF0, 0x0F, 0x54, 0xED, 0xF0, ++ 0xF0, 0x54, 0xE0, 0xFF, 0x08, 0x90, 0xF0, 0x4F, 0x22, 0xF5, 0xE0, 0x37, 0xE0, 0x38, 0x08, 0x90, ++ 0x22, 0xE5, 0x23, 0xF5, 0xE0, 0x95, 0x33, 0xFF, 0x23, 0xE5, 0xC3, 0xFE, 0xE5, 0x23, 0xF5, 0x9F, ++ 0x22, 0xF5, 0x9E, 0x22, 0xE0, 0x34, 0x08, 0x90, 0x90, 0xF0, 0x10, 0x44, 0x22, 0xE5, 0x35, 0x08, ++ 0x36, 0x08, 0x90, 0xF0, 0xE4, 0xF0, 0x23, 0xE5, 0xF0, 0x34, 0x08, 0x90, 0xB0, 0x0A, 0xBD, 0x0D, ++ 0xE0, 0x27, 0x08, 0x90, 0x22, 0xF0, 0xF7, 0x54, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, ++ 0x41, 0x47, 0x49, 0x47, 0x09, 0x09, 0x00, 0x0A, 0x2D, 0x49, 0x46, 0x4C, 0x65, 0x6D, 0x69, 0x54, ++ 0x00, 0x0A, 0x21, 0x72, 0x74, 0x65, 0x53, 0x09, 0x00, 0x0A, 0x70, 0x75, 0x0A, 0x50, 0x57, 0x09, ++ 0x47, 0x41, 0x09, 0x00, 0x09, 0x00, 0x0A, 0x43, 0x00, 0x3D, 0x47, 0x09, 0x00, 0x20, 0x64, 0x25, ++ 0x45, 0x09, 0x00, 0x0A, 0x00, 0x0A, 0x43, 0x58, 0x30, 0x4B, 0x4F, 0x09, 0x4F, 0x09, 0x00, 0x0A, ++ 0x00, 0x0A, 0x31, 0x4B, 0x32, 0x4B, 0x4F, 0x09, 0x4F, 0x09, 0x00, 0x0A, 0x00, 0x0A, 0x33, 0x4B, ++ 0x43, 0x44, 0x41, 0x09, 0x45, 0x09, 0x00, 0x0A, 0x53, 0x2D, 0x43, 0x58, 0x44, 0x25, 0x00, 0x0A, ++ 0x3A, 0x3A, 0x00, 0x20, 0x20, 0x44, 0x25, 0x20, 0x4D, 0x50, 0x09, 0x00, 0x09, 0x00, 0x0A, 0x55, ++ 0x4B, 0x43, 0x4F, 0x4C, 0x09, 0x00, 0x0A, 0x31, 0x25, 0x3A, 0x70, 0x09, 0x74, 0x00, 0x09, 0x64, ++ 0x09, 0x64, 0x25, 0x3A, 0x78, 0x3A, 0x6D, 0x00, 0x3A, 0x6D, 0x00, 0x09, 0x00, 0x09, 0x64, 0x25, ++ 0x44, 0x25, 0x3A, 0x64, 0x4C, 0x09, 0x00, 0x0A, 0x32, 0x4B, 0x43, 0x4F, 0x09, 0x09, 0x00, 0x0A, ++ 0x4F, 0x4C, 0x3E, 0x2D, 0x44, 0x45, 0x4B, 0x43, 0x4C, 0x09, 0x00, 0x0A, 0x33, 0x4B, 0x43, 0x4F, ++ 0x53, 0x09, 0x09, 0x0A, 0x3A, 0x4E, 0x47, 0x49, 0x00, 0x64, 0x25, 0x00, 0x4B, 0x4E, 0x4C, 0x09, ++ 0x00, 0x0A, 0x50, 0x55, 0x69, 0x78, 0x45, 0x09, 0x09, 0x00, 0x0A, 0x74, 0x4C, 0x44, 0x4D, 0x09, ++ 0x64, 0x25, 0x3D, 0x4C, 0x4E, 0x08, 0x00, 0x0A, 0x18, 0x09, 0xB3, 0x08, 0x1F, 0x18, 0x7D, 0x09, ++ 0x41, 0x36, 0x2D, 0x26, 0x84, 0x70, 0x5E, 0x4E, 0xEA, 0xCD, 0xB3, 0x9A, 0x14, 0x0D, 0x08, 0xFF, ++ 0x7F, 0x50, 0x33, 0x20, 0x90, 0x24, 0x8F, 0xC9, 0x16, 0x74, 0xA4, 0x09, 0x26, 0x06, 0x90, 0xF0, ++ 0x54, 0x13, 0xC4, 0xE0, 0x90, 0x03, 0x64, 0x07, 0x05, 0x60, 0xA3, 0x09, 0x80, 0xF0, 0x2B, 0x74, ++ 0xF0, 0x14, 0x74, 0x03, 0xE0, 0x26, 0x06, 0x90, 0x07, 0x54, 0x13, 0xC4, 0x04, 0x03, 0xBF, 0xFF, ++ 0x02, 0x80, 0x01, 0x7F, 0x54, 0xEF, 0x00, 0x7F, 0x33, 0x33, 0x33, 0x01, 0x90, 0xFF, 0xF8, 0x54, ++ 0x54, 0xE0, 0xA2, 0x09, 0xE4, 0xF0, 0x4F, 0xF7, 0xF0, 0xA5, 0x09, 0x90, 0x04, 0xA8, 0x09, 0x90, ++ 0xFF, 0x01, 0x90, 0xF0, 0x90, 0x13, 0xC3, 0xE0, 0xE0, 0x30, 0xA6, 0x09, 0xF0, 0x08, 0x74, 0x05, ++ 0x0C, 0x74, 0x03, 0x80, 0x90, 0xFD, 0xE4, 0xF0, 0xFF, 0xE0, 0x79, 0x08, 0xE0, 0x14, 0x08, 0x90, ++ 0x08, 0x90, 0xFF, 0x5F, 0xFF, 0x5F, 0xE0, 0xDE, 0xE0, 0x43, 0x09, 0x90, 0x60, 0x01, 0x64, 0x5F, ++ 0x94, 0xC3, 0xED, 0x0A, 0x00, 0x04, 0x50, 0xFF, 0x7E, 0xDC, 0x80, 0x0D, 0x7C, 0xCB, 0x7F, 0x20, ++ 0x0D, 0x0D, 0x12, 0x00, 0x74, 0xB0, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x23, 0x09, 0x90, 0xF0, 0xB2, ++ 0x09, 0x90, 0xF0, 0xB4, 0x09, 0x90, 0xF0, 0xB6, 0xF0, 0x43, 0x74, 0xB8, 0x74, 0x9D, 0x09, 0x90, ++ 0x09, 0x90, 0xF0, 0x03, 0x09, 0x90, 0xF0, 0x9F, 0x09, 0x90, 0xF0, 0xA0, 0xFD, 0xE4, 0xF0, 0xA1, ++ 0x80, 0xBD, 0x0D, 0x00, 0x70, 0x24, 0xE5, 0xFB, 0xB0, 0x09, 0x90, 0x3D, 0x90, 0xF0, 0x20, 0x74, ++ 0x90, 0xF0, 0xB2, 0x09, 0x90, 0xF0, 0xB4, 0x09, 0x90, 0xF0, 0xB6, 0x09, 0x40, 0x74, 0xB8, 0x09, ++ 0x09, 0x90, 0xE4, 0xF0, 0x09, 0x90, 0xF0, 0x9D, 0x09, 0x90, 0xF0, 0x9F, 0x09, 0x90, 0xF0, 0xA0, ++ 0x01, 0x90, 0xF0, 0xA1, 0x13, 0xC3, 0xE0, 0xFF, 0x30, 0xA6, 0x09, 0x90, 0x09, 0x74, 0x04, 0xE0, ++ 0x0D, 0x74, 0x22, 0xF0, 0x09, 0x90, 0x22, 0xF0, 0xF0, 0x22, 0x74, 0xB0, 0xF0, 0xB2, 0x09, 0x90, ++ 0xF0, 0xB4, 0x09, 0x90, 0xF0, 0xB6, 0x09, 0x90, 0x74, 0xB8, 0x09, 0x90, 0x30, 0x22, 0xF0, 0x42, ++ 0x20, 0x7E, 0x21, 0x08, 0x0E, 0x12, 0x14, 0x7F, 0xE6, 0x7B, 0x78, 0x1D, 0x07, 0x60, 0x74, 0x78, ++ 0x76, 0x08, 0x1F, 0x76, 0x76, 0x05, 0x80, 0x40, 0xE8, 0x76, 0x08, 0x03, 0xFF, 0xE6, 0x7B, 0x78, ++ 0x7F, 0x74, 0x02, 0x12, 0xB4, 0x0B, 0x12, 0x74, 0x7B, 0x78, 0x12, 0x50, 0x75, 0x07, 0x60, 0xE6, ++ 0x5E, 0x75, 0x28, 0x5D, 0x5D, 0x75, 0x22, 0x91, 0x4E, 0x5E, 0x75, 0x28, 0x7F, 0x20, 0x7E, 0x22, ++ 0x1D, 0x0E, 0x12, 0xC4, 0xE0, 0xAE, 0x01, 0x90, 0x90, 0xF0, 0xC0, 0x54, 0xFF, 0x74, 0xAF, 0x07, ++ 0x99, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0x74, 0x20, 0x06, 0x90, 0x74, 0xA3, 0xF0, 0x80, ++ 0x06, 0x90, 0xF0, 0xFF, 0xDF, 0x54, 0xE0, 0x14, 0xEF, 0x54, 0xE0, 0xF0, 0x03, 0x06, 0x90, 0xF0, ++ 0xF0, 0xDF, 0x54, 0xE0, 0xFF, 0xE4, 0x0E, 0xC2, 0x07, 0x90, 0xF5, 0x11, 0xF0, 0x01, 0x74, 0xFB, ++ 0x75, 0x01, 0x5F, 0x75, 0xE5, 0x22, 0xC5, 0x60, 0x7E, 0x63, 0x60, 0x73, 0x12, 0x00, 0x7F, 0x20, ++ 0x5D, 0x75, 0x1D, 0x0E, 0x0F, 0x5E, 0x75, 0x22, 0x07, 0x90, 0x08, 0xD2, 0xF0, 0x30, 0x74, 0x4B, ++ 0x74, 0x4C, 0x07, 0x90, 0xFF, 0xE4, 0xF0, 0xD4, 0xE4, 0x32, 0x04, 0x12, 0x08, 0xF6, 0x74, 0x78, ++ 0xF6, 0x80, 0x78, 0xF6, 0x44, 0x76, 0x78, 0x78, 0x90, 0x5C, 0x76, 0x08, 0xC4, 0xE0, 0x26, 0x06, ++ 0xC3, 0x07, 0x54, 0x13, 0x06, 0x40, 0x03, 0x94, 0x01, 0x76, 0x7B, 0x78, 0x06, 0x90, 0x14, 0x80, ++ 0x13, 0xC4, 0xE0, 0x14, 0x7F, 0x03, 0x54, 0x13, 0x02, 0xE0, 0x30, 0x00, 0x7B, 0x78, 0x01, 0x7F, ++ 0x7B, 0x78, 0x07, 0xA6, 0x90, 0x07, 0x70, 0xE6, 0x44, 0xE0, 0xB0, 0x07, 0x78, 0x7F, 0xF0, 0x20, ++ 0x50, 0xB4, 0x0B, 0x12, 0x7F, 0x20, 0x7E, 0x59, 0x1D, 0x0E, 0x12, 0x06, 0xE0, 0x28, 0x06, 0x90, ++ 0x13, 0x13, 0xC4, 0xFF, 0x14, 0x60, 0x03, 0x54, 0xE0, 0x08, 0x06, 0x90, 0x78, 0xE0, 0xA3, 0xFE, ++ 0x13, 0xC3, 0xCE, 0x05, 0xF9, 0xD8, 0x13, 0xCE, 0x07, 0x70, 0x0F, 0x54, 0xA1, 0x00, 0x90, 0xE4, ++ 0x90, 0x25, 0x80, 0xF0, 0xC3, 0xE0, 0xA1, 0x00, 0x1C, 0x50, 0xFF, 0x94, 0x90, 0xF0, 0x04, 0xE0, ++ 0xC4, 0xE0, 0x28, 0x06, 0x03, 0x54, 0x13, 0x13, 0xA1, 0x00, 0x90, 0xFF, 0x40, 0x9F, 0xC3, 0xE0, ++ 0x22, 0x06, 0x90, 0x07, 0xF0, 0x01, 0x44, 0xE0, 0x75, 0x22, 0x5D, 0x75, 0x20, 0xAF, 0x4D, 0x5E, ++ 0x0F, 0x54, 0xC4, 0xEF, 0xAF, 0x22, 0xE0, 0x20, 0xE0, 0x20, 0xEF, 0x20, 0xEF, 0x20, 0xAF, 0x1C, ++ 0xE0, 0x20, 0x13, 0xC3, 0xEF, 0x20, 0xAF, 0x14, 0x07, 0x54, 0x13, 0xC4, 0xAF, 0x0A, 0xE0, 0x20, ++ 0x13, 0x13, 0xEF, 0x20, 0xE0, 0x30, 0x3F, 0x54, 0x22, 0x5D, 0x75, 0x06, 0xE5, 0x4D, 0x5E, 0x75, ++ 0x70, 0x5E, 0x65, 0x62, 0x65, 0x61, 0xE5, 0x04, 0x85, 0x08, 0x60, 0x5D, 0x5E, 0x85, 0x61, 0x5D, ++ 0xAA, 0x08, 0xD2, 0x62, 0x12, 0x62, 0xA9, 0x61, 0x08, 0xC2, 0xEB, 0x02, 0x71, 0x01, 0x7F, 0x22, ++ 0x0F, 0x20, 0x7B, 0xB9, 0xC0, 0x7B, 0xB9, 0x71, 0x33, 0xC4, 0xED, 0x0F, 0x10, 0x44, 0xE0, 0x54, ++ 0xC8, 0x09, 0x90, 0x4F, 0xC9, 0x09, 0x90, 0xF0, 0x90, 0xE4, 0xF0, 0xEB, 0x22, 0xF0, 0xCA, 0x09, ++ 0x81, 0x02, 0x08, 0x20, 0xB9, 0x09, 0x90, 0x82, 0x90, 0xF0, 0x03, 0x74, 0x90, 0xF0, 0xBB, 0x09, ++ 0xF0, 0x04, 0xBC, 0x09, 0x74, 0xBB, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x0D, 0xF0, 0x04, 0x74, 0xBD, ++ 0x14, 0xC1, 0x09, 0x90, 0xF0, 0x05, 0x74, 0xF0, 0x14, 0xC2, 0x09, 0x90, 0x26, 0x06, 0x90, 0xF0, ++ 0x54, 0x13, 0xC4, 0xE0, 0x60, 0x03, 0x64, 0x07, 0xC3, 0x09, 0x90, 0x0E, 0x90, 0xF0, 0x02, 0x74, ++ 0x05, 0x74, 0xC4, 0x09, 0xE4, 0x05, 0x80, 0xF0, 0xF0, 0xC3, 0x09, 0x90, 0x74, 0xBE, 0x09, 0x90, ++ 0x09, 0x90, 0xF0, 0x06, 0x15, 0x74, 0xE0, 0xBF, 0xC5, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x05, 0x74, ++ 0x20, 0x74, 0xC7, 0x09, 0xC0, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x03, 0x74, 0x01, 0x74, 0xB9, 0x09, ++ 0xE4, 0x7F, 0x7B, 0xF0, 0x71, 0x04, 0x7F, 0xFD, 0x71, 0xF0, 0x7B, 0xB9, 0xE6, 0x7C, 0x78, 0xAD, ++ 0x7F, 0x05, 0x94, 0xC3, 0x7F, 0x02, 0x50, 0xE0, 0xE0, 0x25, 0xEF, 0xF0, 0x7F, 0xFD, 0xE4, 0xFB, ++ 0x7B, 0xB9, 0x71, 0x03, 0xFF, 0xE4, 0x0D, 0x18, 0x40, 0x7B, 0xB9, 0x71, 0xE4, 0xB9, 0x71, 0x0D, ++ 0xF0, 0xC8, 0x09, 0x90, 0x38, 0x7F, 0x20, 0x7E, 0x78, 0x1D, 0x0E, 0x12, 0x08, 0x00, 0x76, 0x74, ++ 0x74, 0x7F, 0x7D, 0x76, 0x50, 0xB4, 0x0B, 0x12, 0x24, 0x5D, 0x75, 0x06, 0x22, 0x90, 0x5E, 0x75, ++ 0xA1, 0x02, 0x08, 0x20, 0x7F, 0x20, 0x7E, 0x2A, 0x1D, 0x0E, 0x12, 0x3E, 0x00, 0x76, 0x74, 0x78, ++ 0x08, 0x05, 0x76, 0x08, 0x76, 0x08, 0x00, 0x76, 0xE4, 0xF0, 0x7B, 0x64, 0xE4, 0xAD, 0x71, 0xFD, ++ 0xF0, 0xBD, 0x09, 0x90, 0x74, 0xBE, 0x09, 0x90, 0x90, 0xE4, 0xF0, 0x02, 0x90, 0xF0, 0xC2, 0x09, ++ 0x05, 0x74, 0xC4, 0x09, 0xD1, 0x09, 0x90, 0xF0, 0x09, 0x90, 0xE4, 0xF0, 0x09, 0x90, 0xF0, 0xC3, ++ 0xF0, 0x0D, 0x74, 0xBB, 0x74, 0xC1, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x01, 0x06, 0x90, 0xF0, 0xC5, ++ 0x13, 0xC4, 0xE0, 0x26, 0x03, 0x64, 0x07, 0x54, 0x60, 0xC6, 0x09, 0x90, 0xF0, 0xC0, 0x74, 0x05, ++ 0xE0, 0x74, 0x03, 0x80, 0xE6, 0x7B, 0x78, 0xF0, 0x60, 0xF7, 0x09, 0x90, 0xF0, 0x01, 0x74, 0x0A, ++ 0x74, 0xF6, 0x09, 0x90, 0x74, 0x08, 0x80, 0x05, 0x09, 0x90, 0xF0, 0xDC, 0xF0, 0x03, 0x74, 0xF6, ++ 0x04, 0xF5, 0x09, 0x90, 0x26, 0x06, 0x90, 0xF0, 0x54, 0x13, 0xC4, 0xE0, 0x60, 0x03, 0x64, 0x07, ++ 0xF4, 0x09, 0x90, 0x09, 0x74, 0xF0, 0x03, 0x74, 0x74, 0x7F, 0xF0, 0x01, 0x40, 0xB4, 0x0B, 0x12, ++ 0x90, 0xCD, 0xC1, 0x02, 0x40, 0x74, 0xC8, 0x09, 0x82, 0x78, 0xE4, 0xF0, 0x4E, 0x08, 0x90, 0xF6, ++ 0x2F, 0x94, 0xC3, 0xE0, 0x08, 0x90, 0x37, 0x50, 0x01, 0x94, 0xE0, 0x37, 0x1D, 0x7F, 0x2F, 0x40, ++ 0x8D, 0xF1, 0x08, 0x7E, 0x90, 0x26, 0x70, 0xEF, 0x44, 0xE0, 0x31, 0x08, 0x06, 0x90, 0xF0, 0x02, ++ 0xC4, 0xFF, 0xE0, 0x26, 0x64, 0x07, 0x54, 0x13, 0x90, 0x0D, 0x60, 0x03, 0x0E, 0x74, 0x10, 0x08, ++ 0x2F, 0x08, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, 0x80, 0x06, 0x82, 0x78, 0x31, 0x08, 0x90, 0x1B, ++ 0xF0, 0xFD, 0x54, 0xE0, 0x74, 0x10, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x16, 0x04, 0x44, 0xE0, 0x27, ++ 0x2F, 0x08, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0xB3, 0x08, 0x90, 0x50, 0x2F, 0x94, 0xC3, ++ 0x9C, 0x08, 0x90, 0x38, 0x40, 0x01, 0x94, 0xE0, 0x7E, 0x82, 0x7F, 0x30, 0xEF, 0x8D, 0xF1, 0x08, ++ 0x08, 0x90, 0x27, 0x70, 0x02, 0x44, 0xE0, 0x96, 0x26, 0x06, 0x90, 0xF0, 0x13, 0xC4, 0xFF, 0xE0, ++ 0x03, 0x64, 0x07, 0x54, 0x08, 0x90, 0x0D, 0x60, 0xF0, 0x0E, 0x74, 0x75, 0xE0, 0x94, 0x08, 0x90, ++ 0x78, 0xF0, 0x01, 0x44, 0x80, 0x06, 0x06, 0x82, 0x96, 0x08, 0x90, 0x1B, 0xF0, 0xFD, 0x54, 0xE0, ++ 0x74, 0x75, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x16, 0x04, 0x44, 0xE0, 0x8C, 0x94, 0x08, 0x90, 0xF0, ++ 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0x18, 0x09, 0x90, 0x50, 0x2F, 0x94, 0xC3, 0x01, 0x09, 0x90, 0x3A, ++ 0x40, 0x01, 0x94, 0xE0, 0x7E, 0xE7, 0x7F, 0x32, 0xEF, 0x8D, 0xF1, 0x08, 0x08, 0x90, 0x29, 0x70, ++ 0x02, 0x44, 0xE0, 0xFB, 0x26, 0x06, 0x90, 0xF0, 0x13, 0xC4, 0xFF, 0xE0, 0x03, 0x64, 0x07, 0x54, ++ 0x08, 0x90, 0x0D, 0x60, 0xF0, 0x0E, 0x74, 0xDA, 0xE0, 0xF9, 0x08, 0x90, 0x78, 0xF0, 0x01, 0x44, ++ 0x26, 0x04, 0x74, 0x82, 0x90, 0x1B, 0x80, 0xF6, 0x54, 0xE0, 0xFB, 0x08, 0x08, 0x90, 0xF0, 0xFD, ++ 0xF0, 0x16, 0x74, 0xDA, 0xE0, 0xF1, 0x08, 0x90, 0x90, 0xF0, 0x04, 0x44, 0x54, 0xE0, 0xF9, 0x08, ++ 0x09, 0x90, 0xF0, 0xFE, 0x94, 0xC3, 0xE0, 0x7D, 0x90, 0x3A, 0x50, 0x2F, 0x94, 0xE0, 0x66, 0x09, ++ 0x7F, 0x32, 0x40, 0x01, 0xF1, 0x09, 0x7E, 0x4C, 0x29, 0x70, 0xEF, 0x8D, 0xE0, 0x60, 0x09, 0x90, ++ 0x90, 0xF0, 0x02, 0x44, 0xFF, 0xE0, 0x26, 0x06, 0x07, 0x54, 0x13, 0xC4, 0x0D, 0x60, 0x03, 0x64, ++ 0x74, 0x3F, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x0E, 0x01, 0x44, 0xE0, 0x5E, 0x74, 0x82, 0x78, 0xF0, ++ 0x80, 0xF6, 0x26, 0x08, 0x60, 0x09, 0x90, 0x1B, 0xF0, 0xFD, 0x54, 0xE0, 0x74, 0x3F, 0x09, 0x90, ++ 0x09, 0x90, 0xF0, 0x16, 0x04, 0x44, 0xE0, 0x56, 0x5E, 0x09, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, ++ 0x64, 0xE6, 0x82, 0x78, 0x78, 0x09, 0x60, 0x0F, 0x08, 0x00, 0x76, 0x76, 0x0D, 0x80, 0x64, 0x76, ++ 0x0B, 0x12, 0x76, 0x7F, 0x75, 0x06, 0x50, 0xB4, 0x5E, 0x75, 0x27, 0x5D, 0xBB, 0x09, 0x90, 0xD3, ++ 0xF0, 0x08, 0x44, 0xE0, 0x90, 0x05, 0x22, 0x75, 0x22, 0xE5, 0xC8, 0x09, 0x37, 0x08, 0x90, 0xF0, ++ 0x90, 0x24, 0xF5, 0xE0, 0xF5, 0xE0, 0x38, 0x08, 0x9C, 0x08, 0x90, 0x25, 0x90, 0x26, 0xF5, 0xE0, ++ 0xF5, 0xE0, 0x9D, 0x08, 0x01, 0x09, 0x90, 0x27, 0x90, 0x28, 0xF5, 0xE0, 0xF5, 0xE0, 0x02, 0x09, ++ 0x66, 0x09, 0x90, 0x29, 0x90, 0x2A, 0xF5, 0xE0, 0xF5, 0xE0, 0x67, 0x09, 0x23, 0xF5, 0xE4, 0x2B, ++ 0xE0, 0x25, 0x23, 0xE5, 0xC0, 0xF8, 0x24, 0x24, 0x08, 0xFC, 0xE6, 0x00, 0x04, 0xAE, 0xFD, 0xE6, ++ 0xA2, 0xCE, 0x0A, 0x78, 0x13, 0xCE, 0x13, 0xE7, 0xC3, 0xFF, 0xF8, 0xD8, 0xEC, 0xFF, 0x9F, 0xED, ++ 0xF6, 0x00, 0xD0, 0x9E, 0x05, 0x07, 0xA6, 0x08, 0xB4, 0x23, 0xE5, 0x23, 0x22, 0xE5, 0xD2, 0x04, ++ 0x09, 0x90, 0x10, 0x44, 0x08, 0x90, 0xF0, 0xC8, 0xF0, 0x24, 0xE5, 0x35, 0xE5, 0x36, 0x08, 0x90, ++ 0x08, 0x90, 0xF0, 0x25, 0xF0, 0x26, 0xE5, 0x9A, 0xE5, 0x9B, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x27, ++ 0xF0, 0x28, 0xE5, 0xFF, 0xE5, 0x00, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x29, 0xF0, 0x2A, 0xE5, 0x64, ++ 0xE5, 0x65, 0x09, 0x90, 0x90, 0xE4, 0xF0, 0x2B, 0x05, 0xF0, 0xC8, 0x09, 0x64, 0x22, 0xE5, 0x22, ++ 0xC1, 0x02, 0x60, 0x0A, 0xBB, 0x09, 0x90, 0xD7, 0xF0, 0xF7, 0x54, 0xE0, 0x78, 0xFD, 0xE4, 0x22, ++ 0x3C, 0x60, 0xE6, 0x7B, 0x82, 0x8F, 0xFC, 0xE4, 0xFB, 0xE0, 0x83, 0x8E, 0x50, 0x04, 0x94, 0xD3, ++ 0x94, 0xC3, 0xEB, 0x06, 0x7D, 0x1E, 0x50, 0x01, 0xFF, 0x24, 0xEF, 0x01, 0x34, 0xEE, 0x82, 0xF5, ++ 0xE0, 0x83, 0xF5, 0xFF, 0xEF, 0xF0, 0x01, 0x44, 0x82, 0xF5, 0xFF, 0x24, 0xF5, 0xFF, 0x34, 0xEE, ++ 0xFE, 0x54, 0xE0, 0x83, 0x2F, 0x02, 0x74, 0xF0, 0xFE, 0x3E, 0xE4, 0xFF, 0xC6, 0x04, 0xBC, 0x0C, ++ 0x30, 0x22, 0x05, 0xAF, 0x20, 0x7E, 0x2F, 0x08, 0x0E, 0x12, 0x44, 0x7F, 0x76, 0x74, 0x78, 0x1D, ++ 0xF4, 0x76, 0x08, 0x01, 0xE0, 0xBB, 0x09, 0x90, 0x78, 0xF0, 0xFB, 0x54, 0x01, 0x54, 0xE6, 0x7B, ++ 0x54, 0x33, 0x33, 0x33, 0x09, 0x90, 0xFF, 0xF8, 0xF7, 0x54, 0xE0, 0xF4, 0x09, 0x90, 0xF0, 0x4F, ++ 0xFD, 0x54, 0xE0, 0xBE, 0xCD, 0x26, 0x12, 0xF0, 0x74, 0xC8, 0x09, 0x90, 0x08, 0x90, 0xF0, 0x40, ++ 0x94, 0xD3, 0xE0, 0x37, 0x90, 0x1B, 0x40, 0x01, 0xD3, 0xE0, 0x9C, 0x08, 0x12, 0x40, 0x01, 0x94, ++ 0xE0, 0x01, 0x09, 0x90, 0x40, 0x01, 0x94, 0xD3, 0x66, 0x09, 0x90, 0x09, 0x01, 0x94, 0xD3, 0xE0, ++ 0x5D, 0x75, 0x07, 0x50, 0xD0, 0x5E, 0x75, 0x23, 0x12, 0x74, 0x7F, 0x22, 0x0D, 0x50, 0xB4, 0x0B, ++ 0xE0, 0xBB, 0x09, 0x90, 0x75, 0xF0, 0x08, 0x44, 0x5E, 0x75, 0x29, 0x5D, 0x08, 0x30, 0x22, 0xCB, ++ 0x7F, 0x20, 0x7E, 0x0E, 0x1D, 0x0E, 0x12, 0x1C, 0x05, 0x76, 0x74, 0x78, 0x90, 0xDC, 0x76, 0x08, ++ 0xD3, 0xE0, 0x4F, 0x08, 0x1B, 0x40, 0x0A, 0x94, 0xE0, 0xB4, 0x08, 0x90, 0x40, 0x0A, 0x94, 0xD3, ++ 0x19, 0x09, 0x90, 0x12, 0x0A, 0x94, 0xD3, 0xE0, 0x09, 0x90, 0x09, 0x40, 0x94, 0xD3, 0xE0, 0x7E, ++ 0x7F, 0x07, 0x50, 0x0A, 0xB4, 0x0B, 0x12, 0x74, 0x5D, 0x75, 0x06, 0x50, 0x91, 0x5E, 0x75, 0x28, ++ 0x0F, 0x08, 0x30, 0x22, 0x21, 0x7F, 0x20, 0x7E, 0x78, 0x1D, 0x0E, 0x12, 0x08, 0x00, 0x76, 0x74, ++ 0x7F, 0x22, 0x0A, 0x76, 0xB4, 0x0B, 0x12, 0x74, 0x74, 0x78, 0x3C, 0x50, 0x76, 0x08, 0x00, 0x76, ++ 0x50, 0xE7, 0x11, 0x05, 0x26, 0x06, 0x90, 0x31, 0x54, 0x13, 0xC4, 0xE0, 0x03, 0xBF, 0xFF, 0x07, ++ 0x00, 0x0D, 0x90, 0x13, 0xC3, 0x07, 0x54, 0xE0, 0x08, 0x40, 0x03, 0x94, 0xE0, 0x80, 0x0D, 0x90, ++ 0x22, 0xF0, 0x18, 0x44, 0x60, 0xE6, 0x7B, 0x78, 0x29, 0x5D, 0x75, 0x07, 0x22, 0xAA, 0x5E, 0x75, ++ 0x75, 0x23, 0x5D, 0x75, 0x90, 0x22, 0xD0, 0x5E, 0x0C, 0xD2, 0x4F, 0x08, 0x74, 0x22, 0xF5, 0xE4, ++ 0xF8, 0x22, 0x25, 0x7C, 0x00, 0x94, 0xD3, 0xE6, 0xD3, 0xE0, 0x0E, 0x40, 0x08, 0x40, 0x18, 0x94, ++ 0x22, 0x25, 0x7C, 0x74, 0x0C, 0xC2, 0x16, 0xF8, 0x82, 0x25, 0x65, 0x74, 0x35, 0xE4, 0x82, 0xF5, ++ 0x05, 0x83, 0xF5, 0x83, 0xB4, 0x22, 0xE5, 0x22, 0x07, 0x90, 0xD5, 0x04, 0x03, 0x54, 0xE0, 0xFA, ++ 0xE6, 0xF8, 0x7C, 0x24, 0x90, 0xFF, 0x07, 0x54, 0x54, 0xE0, 0x00, 0x0D, 0x90, 0xF0, 0x4F, 0xF8, ++ 0x54, 0xE0, 0xFA, 0x07, 0x74, 0xC3, 0xFF, 0x03, 0x74, 0xFF, 0x9F, 0x01, 0xE6, 0xF8, 0x2F, 0x7C, ++ 0x90, 0xFF, 0x07, 0x54, 0x54, 0xE0, 0x20, 0x0D, 0x90, 0xF0, 0x4F, 0xF8, 0xC4, 0xE0, 0xFA, 0x07, ++ 0x7C, 0x24, 0x03, 0x54, 0x07, 0x54, 0xE6, 0xF8, 0x40, 0x0D, 0x90, 0xFF, 0x4F, 0xF8, 0x54, 0xE0, ++ 0xFA, 0x07, 0x90, 0xF0, 0x03, 0x54, 0xC4, 0xE0, 0x05, 0x74, 0xC3, 0xFF, 0x7C, 0x74, 0xFF, 0x9F, ++ 0x54, 0xE6, 0xF8, 0x2F, 0x0D, 0x90, 0xFF, 0x07, 0xF8, 0x54, 0xE0, 0x60, 0x0C, 0x30, 0xF0, 0x4F, ++ 0x7F, 0x20, 0x7E, 0x26, 0x1D, 0x0E, 0x12, 0x27, 0x7E, 0x22, 0xF5, 0xE4, 0x74, 0x2C, 0x7F, 0x20, ++ 0xF8, 0x22, 0x25, 0x7C, 0x00, 0x7C, 0xFD, 0xE6, 0x05, 0x0D, 0x0D, 0x12, 0xC3, 0x22, 0xE5, 0x22, ++ 0xE7, 0x40, 0x04, 0x94, 0xA2, 0x19, 0x0E, 0x12, 0x08, 0x30, 0x22, 0x0C, 0x7F, 0x20, 0x7E, 0x10, ++ 0x1D, 0x0E, 0x12, 0x32, 0x00, 0x76, 0x74, 0x78, 0x51, 0x32, 0x76, 0x08, 0x12, 0x74, 0x7F, 0x93, ++ 0x06, 0x50, 0xB4, 0x0B, 0x75, 0x23, 0x5D, 0x75, 0x30, 0x22, 0xD0, 0x5E, 0x20, 0x7E, 0x1C, 0x08, ++ 0x0E, 0x12, 0x4A, 0x7F, 0x76, 0x74, 0x78, 0x1D, 0xF4, 0x76, 0x08, 0x01, 0xE0, 0xDF, 0x09, 0x90, ++ 0x90, 0xF0, 0x07, 0x44, 0x44, 0xE0, 0xDE, 0x09, 0x06, 0x90, 0xF0, 0x03, 0x13, 0x13, 0xE0, 0x29, ++ 0xE0, 0x30, 0x3F, 0x54, 0x02, 0x0D, 0x90, 0x4C, 0x07, 0x54, 0xC4, 0xE0, 0x50, 0x03, 0x94, 0xC3, ++ 0xC4, 0xFF, 0xE0, 0x1A, 0xEF, 0xFE, 0x0F, 0x54, 0xEE, 0xFF, 0x8F, 0x54, 0xC4, 0x07, 0x54, 0x04, ++ 0xF0, 0x4F, 0xF0, 0x54, 0x0D, 0x7E, 0x02, 0x7F, 0x90, 0xCE, 0x0B, 0x12, 0xC4, 0xE0, 0x05, 0x0D, ++ 0x94, 0xC3, 0x07, 0x54, 0xE0, 0x1A, 0x50, 0x02, 0x0F, 0x54, 0xC4, 0xFF, 0x8F, 0x54, 0xEF, 0xFE, ++ 0x54, 0x04, 0xEE, 0xFF, 0xF0, 0x54, 0xC4, 0x07, 0x05, 0x7F, 0xF0, 0x4F, 0x0B, 0x12, 0x0D, 0x7E, ++ 0xE6, 0x74, 0x78, 0xCE, 0xFF, 0xE6, 0x08, 0xFE, 0x32, 0x7D, 0x00, 0x7C, 0xED, 0x96, 0x02, 0x12, ++ 0x78, 0x26, 0x70, 0x4C, 0x0C, 0x70, 0xE6, 0x7B, 0xE0, 0xF6, 0x09, 0x90, 0x50, 0x05, 0x94, 0xC3, ++ 0xF0, 0x04, 0xE0, 0x03, 0xE0, 0x61, 0x08, 0x90, 0x94, 0xC3, 0x0F, 0x54, 0xE0, 0x0A, 0x50, 0x05, ++ 0x54, 0x04, 0x0F, 0x54, 0xF5, 0x09, 0x90, 0x0F, 0x12, 0x74, 0x7F, 0xF0, 0x12, 0x50, 0xB4, 0x0B, ++ 0x60, 0xE6, 0x7B, 0x78, 0x2C, 0x5D, 0x75, 0x07, 0x22, 0x43, 0x5E, 0x75, 0x75, 0x2A, 0x5D, 0x75, ++ 0x90, 0x22, 0xCF, 0x5E, 0x02, 0x74, 0x9D, 0x09, 0x26, 0x06, 0x90, 0xF0, 0x54, 0x13, 0xC4, 0xE0, ++ 0x03, 0x94, 0xC3, 0x07, 0x06, 0x90, 0x1A, 0x50, 0x13, 0x13, 0xE0, 0x29, 0xE0, 0x30, 0x3F, 0x54, ++ 0xE6, 0x7C, 0x78, 0x08, 0x40, 0x03, 0x94, 0xD3, 0x9F, 0x09, 0x90, 0x07, 0x05, 0x80, 0x02, 0x74, ++ 0x74, 0x9F, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x08, 0x09, 0x90, 0xF0, 0xA0, 0x20, 0x22, 0xF0, 0xA1, ++ 0x1A, 0x81, 0x02, 0x08, 0x56, 0x7F, 0x20, 0x7E, 0x90, 0x1D, 0x0E, 0x12, 0x44, 0xE0, 0xB7, 0x07, ++ 0x54, 0xE0, 0xF0, 0x02, 0x90, 0xE4, 0xF0, 0xFD, 0x90, 0xF0, 0xD9, 0x09, 0x44, 0xE0, 0xB0, 0x09, ++ 0x09, 0x90, 0xF0, 0x01, 0x01, 0x44, 0xE0, 0xB2, 0xB4, 0x09, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, ++ 0xE0, 0xB6, 0x09, 0x90, 0x90, 0xF0, 0x01, 0x44, 0x54, 0xE0, 0xB0, 0x09, 0x09, 0x90, 0xF0, 0xFE, ++ 0xFE, 0x54, 0xE0, 0xB2, 0xB4, 0x09, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0xB6, 0x09, 0x90, ++ 0xE4, 0xF0, 0xFE, 0x54, 0xF0, 0x01, 0x0D, 0x90, 0x0D, 0x7E, 0x01, 0x7F, 0x90, 0xCE, 0x0B, 0x12, ++ 0x02, 0x74, 0xA5, 0x09, 0x76, 0x74, 0x78, 0xF0, 0x00, 0x76, 0x08, 0x01, 0x00, 0x90, 0x93, 0x51, ++ 0xD3, 0xFF, 0xE0, 0xA8, 0x80, 0x94, 0x80, 0x64, 0x87, 0x78, 0x06, 0x40, 0x06, 0x80, 0x07, 0xA6, ++ 0x78, 0x04, 0xF4, 0xEF, 0xE8, 0xC2, 0xF6, 0x87, 0x75, 0xFC, 0xFD, 0xE4, 0x23, 0xF5, 0x04, 0x22, ++ 0x13, 0xE6, 0x87, 0x78, 0x1F, 0x54, 0x13, 0x13, 0xE6, 0x87, 0x78, 0xF6, 0x08, 0x90, 0x7A, 0x60, ++ 0x94, 0xC3, 0xE0, 0x4E, 0x90, 0x5E, 0x50, 0x1E, 0xC3, 0xE0, 0xB3, 0x08, 0x55, 0x50, 0x1E, 0x94, ++ 0xE0, 0x18, 0x09, 0x90, 0x50, 0x1E, 0x94, 0xC3, 0x7D, 0x09, 0x90, 0x4C, 0x1E, 0x94, 0xC3, 0xE0, ++ 0x00, 0x90, 0x43, 0x50, 0x91, 0xFF, 0xE0, 0xA8, 0x45, 0x08, 0x90, 0x2B, 0x90, 0xF0, 0x2F, 0xE0, ++ 0xFF, 0xE0, 0xA9, 0x00, 0x08, 0x90, 0x2B, 0x91, 0xF0, 0x2F, 0xE0, 0xAA, 0xE0, 0xAA, 0x00, 0x90, ++ 0x90, 0x2B, 0x91, 0xFF, 0x2F, 0xE0, 0x0F, 0x09, 0xAB, 0x00, 0x90, 0xF0, 0x2B, 0x91, 0xFF, 0xE0, ++ 0xE0, 0x74, 0x09, 0x90, 0x20, 0x7E, 0xF0, 0x2F, 0x0D, 0x12, 0x5E, 0x7F, 0x16, 0x87, 0x78, 0x0D, ++ 0x80, 0xFD, 0xFC, 0xE4, 0x00, 0xBD, 0x0D, 0x05, 0x23, 0xE5, 0x0C, 0x01, 0x02, 0x70, 0x23, 0x15, ++ 0x23, 0xE5, 0x22, 0x15, 0x81, 0x70, 0x22, 0x45, 0x62, 0x7F, 0x20, 0x7E, 0x22, 0xAC, 0x23, 0xAD, ++ 0x90, 0x0D, 0x0D, 0x12, 0x90, 0xE0, 0xA8, 0x00, 0x90, 0xF0, 0x45, 0x08, 0x90, 0xE0, 0xA9, 0x00, ++ 0x90, 0xF0, 0xAA, 0x08, 0x90, 0xE0, 0xAA, 0x00, 0x90, 0xF0, 0x0F, 0x09, 0x90, 0xE0, 0xAB, 0x00, ++ 0xE4, 0xF0, 0x74, 0x09, 0xF0, 0xA5, 0x09, 0x90, 0x74, 0x7F, 0xE8, 0xD2, 0x50, 0xB4, 0x0B, 0x12, ++ 0x2C, 0x5D, 0x75, 0x09, 0x12, 0x43, 0x5E, 0x75, 0xD3, 0x22, 0x19, 0x0E, 0x94, 0x80, 0x64, 0xEF, ++ 0x7F, 0x03, 0x40, 0x80, 0xEF, 0xC3, 0x22, 0x08, 0x80, 0x94, 0x80, 0x64, 0x02, 0x50, 0x00, 0x7F, ++ 0x30, 0x22, 0xF8, 0x7F, 0x20, 0x7E, 0x0E, 0x08, 0x0E, 0x12, 0x50, 0x7F, 0x76, 0x74, 0x78, 0x1D, ++ 0x0A, 0x76, 0x08, 0x00, 0xE0, 0x29, 0x06, 0x90, 0x3F, 0x54, 0x13, 0x13, 0xE4, 0x04, 0xE0, 0x30, ++ 0x7F, 0x80, 0x91, 0xFF, 0xB4, 0x0B, 0x12, 0x74, 0x06, 0x90, 0x15, 0x50, 0x13, 0x13, 0xE0, 0x29, ++ 0xE0, 0x30, 0x3F, 0x54, 0x91, 0x01, 0x7F, 0x04, 0x2D, 0x5D, 0x75, 0x80, 0x22, 0x8D, 0x5E, 0x75, ++ 0x75, 0x0D, 0x24, 0x75, 0x26, 0x75, 0x0A, 0x25, 0x06, 0x27, 0x75, 0x0D, 0xFE, 0xE4, 0x0C, 0xD2, ++ 0x0D, 0x60, 0x14, 0xEE, 0x24, 0x16, 0x60, 0x14, 0x90, 0x1B, 0x70, 0x02, 0x80, 0xE0, 0xFA, 0x07, ++ 0xFA, 0x07, 0x90, 0x11, 0xFD, 0x03, 0x54, 0xE0, 0x80, 0x01, 0x74, 0xC3, 0xFA, 0x07, 0x90, 0x14, ++ 0x03, 0x54, 0xC4, 0xE0, 0x07, 0x90, 0x0C, 0x80, 0x54, 0xC4, 0xE0, 0xFA, 0x74, 0xC3, 0xFD, 0x03, ++ 0xE0, 0x25, 0x9D, 0x05, 0x82, 0xF5, 0xD6, 0x24, 0xF5, 0x20, 0x34, 0xE4, 0xFC, 0x93, 0xE4, 0x83, ++ 0xFD, 0x93, 0x01, 0x74, 0x85, 0x82, 0x25, 0x85, 0xC4, 0xE0, 0x83, 0x24, 0xD3, 0xF9, 0x0F, 0x54, ++ 0x42, 0x40, 0x06, 0x94, 0x83, 0x8C, 0x82, 0x8D, 0x50, 0x11, 0x94, 0xE0, 0x36, 0x70, 0xEF, 0x39, ++ 0x85, 0x82, 0x27, 0x85, 0xFB, 0xE0, 0x83, 0x26, 0xFA, 0x0F, 0x54, 0xC4, 0xFB, 0x0F, 0x54, 0xEB, ++ 0x0F, 0x54, 0x14, 0xEA, 0x4B, 0xF0, 0x54, 0xC4, 0x82, 0x25, 0x85, 0xF0, 0xE0, 0x83, 0x24, 0x85, ++ 0x0F, 0x54, 0xC4, 0xFB, 0x0F, 0x54, 0xEB, 0xFA, 0x54, 0x14, 0xEA, 0xFB, 0xF0, 0x54, 0xC4, 0x0F, ++ 0x0C, 0xC2, 0xF0, 0x4B, 0xC3, 0xE9, 0x46, 0x80, 0x40, 0x50, 0x09, 0x94, 0x83, 0x8C, 0x82, 0x8D, ++ 0x40, 0x0D, 0x94, 0xE0, 0x01, 0x64, 0xEF, 0x37, 0x27, 0x85, 0x32, 0x70, 0x83, 0x26, 0x85, 0x82, ++ 0x54, 0xC4, 0xFB, 0xE0, 0x54, 0xEB, 0xFA, 0x0F, 0x04, 0xEA, 0xFB, 0x0F, 0x54, 0xC4, 0x0F, 0x54, ++ 0x85, 0xF0, 0x4B, 0xF0, 0x24, 0x85, 0x82, 0x25, 0xC4, 0xFB, 0xE0, 0x83, 0xEB, 0xFA, 0x0F, 0x54, ++ 0xEA, 0xFB, 0x0F, 0x54, 0xC4, 0x0F, 0x54, 0x04, 0xF0, 0x4B, 0xF0, 0x54, 0x27, 0x25, 0x20, 0x74, ++ 0x35, 0xE4, 0x27, 0xF5, 0x74, 0x26, 0xF5, 0x26, 0xF5, 0x25, 0x25, 0x20, 0x24, 0x35, 0xE4, 0x25, ++ 0xEE, 0x0E, 0x24, 0xF5, 0x02, 0x60, 0x04, 0x64, 0x0C, 0xA2, 0x90, 0x81, 0x4D, 0x08, 0x30, 0x22, ++ 0x69, 0x7F, 0x20, 0x7E, 0x90, 0x1D, 0x0E, 0x12, 0x54, 0xE0, 0xDF, 0x09, 0xF0, 0x60, 0x44, 0x8F, ++ 0xE0, 0xF9, 0x01, 0x90, 0x90, 0xFF, 0x0C, 0x54, 0x54, 0xE0, 0xDE, 0x09, 0x90, 0xF0, 0x4F, 0xF3, ++ 0x90, 0xE0, 0xF9, 0x01, 0xE0, 0x30, 0xE0, 0x09, 0x0F, 0x54, 0xE0, 0x06, 0xE0, 0x06, 0x80, 0xF0, ++ 0x60, 0x44, 0x0F, 0x54, 0xF9, 0x01, 0x90, 0xF0, 0xDC, 0x09, 0x90, 0xE0, 0xE0, 0x07, 0xE1, 0x30, ++ 0x08, 0x44, 0xF3, 0x54, 0x54, 0xE0, 0x22, 0xF0, 0xF0, 0x04, 0x44, 0xF3, 0x07, 0x90, 0xE4, 0x22, ++ 0x09, 0x90, 0xF0, 0x6D, 0x40, 0x44, 0xE0, 0xDB, 0x08, 0x90, 0xE4, 0xF0, 0x09, 0x90, 0xF0, 0x4D, ++ 0x80, 0x44, 0xE0, 0xDB, 0x4D, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0x7F, 0x74, 0x54, 0xE0, 0xDB, 0x09, ++ 0x01, 0x90, 0xF0, 0x7F, 0x13, 0xC4, 0xE0, 0xF9, 0x01, 0x54, 0x13, 0x13, 0x30, 0xFA, 0x01, 0x90, ++ 0xFF, 0xE0, 0x0E, 0xE0, 0xE0, 0x4F, 0x08, 0x90, 0xE5, 0xA4, 0xF0, 0x8F, 0x01, 0x80, 0x04, 0xF0, ++ 0x4D, 0x08, 0x90, 0xE0, 0xDF, 0x09, 0x90, 0xF0, 0x44, 0x8F, 0x54, 0xE0, 0x09, 0x90, 0xF0, 0x60, ++ 0xF3, 0x54, 0xE0, 0xDE, 0x90, 0xF0, 0x04, 0x44, 0x54, 0xE0, 0xE0, 0x09, 0xF0, 0x10, 0x44, 0x0F, ++ 0xE0, 0xDB, 0x09, 0x90, 0x90, 0xF0, 0x80, 0x44, 0x54, 0xE0, 0xDC, 0x09, 0xF0, 0x04, 0x44, 0xF3, ++ 0x75, 0x2E, 0x5D, 0x75, 0x30, 0x22, 0x57, 0x5E, 0x20, 0x7E, 0x57, 0x08, 0x0E, 0x12, 0x6F, 0x7F, ++ 0x07, 0x90, 0xE4, 0x1D, 0x07, 0x90, 0xF0, 0xB1, 0xF0, 0x10, 0x74, 0xB2, 0x74, 0xBC, 0x07, 0x90, ++ 0x07, 0x90, 0xF0, 0xE4, 0x01, 0x44, 0xE0, 0xB6, 0xB7, 0x07, 0x90, 0xF0, 0xF0, 0x01, 0x44, 0xE0, ++ 0x74, 0xB9, 0x07, 0x90, 0x07, 0x90, 0xF0, 0x12, 0x07, 0x90, 0xF0, 0xBA, 0xFE, 0x54, 0xE0, 0xB7, ++ 0xB0, 0x07, 0x90, 0xF0, 0xF0, 0xEF, 0x54, 0xE0, 0xE0, 0xAE, 0x07, 0x90, 0xE4, 0xF0, 0xDF, 0x54, ++ 0x78, 0xF6, 0x84, 0x78, 0x76, 0x18, 0xF6, 0x86, 0x76, 0x83, 0x78, 0x01, 0xF6, 0x88, 0x78, 0x01, ++ 0xB4, 0x07, 0x90, 0x22, 0xE1, 0x02, 0x60, 0xE0, 0xE6, 0x85, 0x78, 0x3D, 0xFF, 0x13, 0xE7, 0xA2, ++ 0xE6, 0xE0, 0x95, 0x33, 0xE0, 0x30, 0x01, 0x7E, 0xEE, 0xFF, 0x7E, 0x02, 0xFF, 0xA4, 0xF0, 0x8F, ++ 0x24, 0xE6, 0x83, 0x78, 0x07, 0xA6, 0xF8, 0x88, 0x77, 0x7F, 0x20, 0x7E, 0xFD, 0xE6, 0x83, 0x78, ++ 0x0D, 0x12, 0x00, 0x7C, 0x7F, 0x20, 0x7E, 0x0D, 0xE6, 0x84, 0x78, 0x7F, 0x12, 0x00, 0x7C, 0xFD, ++ 0x83, 0x78, 0x0D, 0x0D, 0x09, 0x03, 0xB4, 0xE6, 0x85, 0x7F, 0x20, 0x7E, 0x80, 0x1D, 0x0E, 0x12, ++ 0x7F, 0x20, 0x7E, 0x0D, 0xE6, 0x86, 0x78, 0x8A, 0x12, 0x00, 0x7C, 0xFD, 0x20, 0x7E, 0x0D, 0x0D, ++ 0x83, 0x78, 0x90, 0x7F, 0xF8, 0x88, 0x24, 0xE6, 0x95, 0x33, 0xFD, 0xE6, 0x0D, 0x12, 0xFC, 0xE0, ++ 0xE6, 0x83, 0x78, 0x0D, 0x50, 0x03, 0x94, 0xC3, 0x08, 0xE4, 0x06, 0x0C, 0xF6, 0x86, 0x78, 0xF6, ++ 0x80, 0x01, 0x76, 0x18, 0x30, 0x5D, 0x75, 0x50, 0x80, 0x40, 0x5E, 0x75, 0xE6, 0x83, 0x78, 0x48, ++ 0x7E, 0x03, 0x94, 0xC3, 0x7F, 0x04, 0x50, 0x00, 0x7F, 0x02, 0x80, 0x01, 0xE6, 0x86, 0x78, 0x00, ++ 0x64, 0xEE, 0x9F, 0xC3, 0x80, 0x74, 0xF8, 0x80, 0x78, 0x05, 0x50, 0x98, 0x25, 0x80, 0x06, 0x86, ++ 0xF6, 0x86, 0x78, 0xE4, 0xC3, 0xE6, 0x84, 0x78, 0x03, 0x50, 0x01, 0x94, 0xE4, 0x16, 0x80, 0x06, ++ 0xC3, 0xF6, 0x84, 0x78, 0x80, 0x64, 0xE6, 0x08, 0x03, 0x50, 0x8A, 0x94, 0x75, 0x06, 0x80, 0x06, ++ 0x5E, 0x75, 0x23, 0x5D, 0xE6, 0x83, 0x78, 0xD0, 0x90, 0xF0, 0x54, 0xC4, 0x08, 0xF0, 0xB2, 0x07, ++ 0xB1, 0x07, 0x90, 0xE6, 0x64, 0xE6, 0x18, 0xF0, 0x78, 0x1E, 0x70, 0x01, 0x03, 0x54, 0xE6, 0x86, ++ 0xBC, 0x07, 0x90, 0xFF, 0x4F, 0xFC, 0x54, 0xE0, 0x01, 0x74, 0xC3, 0xF0, 0x25, 0x03, 0x54, 0x96, ++ 0xFF, 0xE0, 0x25, 0xE0, 0x4F, 0xF3, 0x54, 0xE0, 0xE6, 0x83, 0x78, 0xF0, 0x24, 0x70, 0x02, 0x64, ++ 0x24, 0xE6, 0x86, 0x78, 0xC4, 0x03, 0x54, 0x02, 0x90, 0xFF, 0xF0, 0x54, 0x54, 0xE0, 0xBC, 0x07, ++ 0xC3, 0xF0, 0x4F, 0xCF, 0x54, 0x96, 0x03, 0x74, 0x33, 0x33, 0xC4, 0x03, 0xE0, 0xFF, 0xC0, 0x54, ++ 0xF0, 0x4F, 0x3F, 0x54, 0xA2, 0xE6, 0x85, 0x78, 0x02, 0x24, 0x13, 0xE7, 0x78, 0xF6, 0x87, 0x78, ++ 0xE0, 0x30, 0xE6, 0x85, 0xBC, 0x07, 0x90, 0x22, 0x78, 0x03, 0x54, 0xE0, 0xE6, 0x05, 0x70, 0x87, ++ 0x08, 0x80, 0x10, 0x44, 0x33, 0x33, 0x33, 0xE6, 0x02, 0x44, 0xF8, 0x54, 0xF0, 0xB9, 0x07, 0x90, ++ 0x74, 0xBA, 0x07, 0x90, 0x90, 0x22, 0xF0, 0x12, 0x54, 0xE0, 0xBC, 0x07, 0x70, 0x87, 0x78, 0x03, ++ 0x33, 0x33, 0xE6, 0x0A, 0x44, 0xF8, 0x54, 0x33, 0xE6, 0x03, 0x80, 0x02, 0x07, 0x90, 0x10, 0x44, ++ 0x87, 0x78, 0xF0, 0xB9, 0x33, 0x33, 0x33, 0xE6, 0x90, 0x46, 0xF8, 0x54, 0x22, 0xF0, 0xBA, 0x07, ++ 0x01, 0x02, 0x08, 0x20, 0x7F, 0x20, 0x7E, 0xD3, 0x1D, 0x0E, 0x12, 0x96, 0x7F, 0x76, 0x85, 0x78, ++ 0x01, 0x76, 0x83, 0x78, 0x24, 0xE6, 0x83, 0x78, 0xE7, 0xD3, 0xF9, 0x88, 0xF0, 0xF5, 0x80, 0x64, ++ 0x64, 0xE6, 0x85, 0x78, 0x40, 0xF0, 0x95, 0x80, 0xE6, 0x83, 0x78, 0x0A, 0xE6, 0xF8, 0x88, 0x24, ++ 0x78, 0xF6, 0x85, 0x78, 0xB4, 0xE6, 0x06, 0x83, 0x07, 0x90, 0xDA, 0x04, 0x13, 0x13, 0xE0, 0xBC, ++ 0x88, 0x24, 0x03, 0x54, 0x78, 0xE7, 0xC3, 0xF9, 0x02, 0x24, 0x96, 0x85, 0x54, 0x33, 0x33, 0x33, ++ 0x54, 0xE0, 0xFF, 0xF8, 0xF9, 0x88, 0x24, 0x03, 0x24, 0x96, 0xE7, 0xC3, 0x07, 0x90, 0x4F, 0x02, ++ 0x07, 0x90, 0xF0, 0xB9, 0x13, 0xC4, 0xE0, 0xBC, 0x24, 0x03, 0x54, 0x13, 0xE7, 0xC3, 0xF9, 0x88, ++ 0x33, 0x02, 0x24, 0x96, 0xF8, 0x54, 0x33, 0x33, 0x54, 0xC4, 0xE0, 0xFF, 0xF9, 0x88, 0x24, 0x03, ++ 0x24, 0x96, 0xE7, 0xC3, 0x07, 0x90, 0x4F, 0x02, 0x74, 0x78, 0xF0, 0xBA, 0x76, 0x08, 0x00, 0x76, ++ 0x90, 0x48, 0x80, 0x0A, 0x70, 0xE0, 0xB4, 0x07, 0x31, 0x5D, 0x75, 0x0D, 0x7E, 0x23, 0x5E, 0x75, ++ 0x02, 0x9E, 0x7F, 0x20, 0x74, 0x7F, 0x1D, 0x0E, 0x50, 0xB4, 0x0B, 0x12, 0x23, 0x5D, 0x75, 0x07, ++ 0x22, 0xD0, 0x5E, 0x75, 0xE0, 0xB1, 0x07, 0x90, 0xE0, 0x20, 0x00, 0x7F, 0xEF, 0x01, 0x7F, 0x02, ++ 0x90, 0xFF, 0x01, 0x54, 0x54, 0xE0, 0xB1, 0x07, 0xE0, 0xF0, 0x4F, 0xFE, 0xE4, 0xF0, 0xFD, 0x54, ++ 0x00, 0xF6, 0x85, 0x78, 0xE6, 0x06, 0x85, 0x78, 0x90, 0xF8, 0x7F, 0xB4, 0x44, 0xE0, 0xB1, 0x07, ++ 0x30, 0x22, 0xF0, 0x02, 0x20, 0x7E, 0x1D, 0x08, 0x0E, 0x12, 0xAA, 0x7F, 0xB2, 0x07, 0x90, 0x1D, ++ 0xF0, 0xCF, 0x54, 0xE0, 0xF0, 0xF0, 0x54, 0xE0, 0xF0, 0x40, 0x44, 0xE0, 0xF6, 0x84, 0x78, 0xE4, ++ 0x90, 0x22, 0xF6, 0x18, 0x70, 0xE0, 0xB4, 0x07, 0x7F, 0x20, 0x7E, 0x2B, 0xE6, 0x84, 0x78, 0xB9, ++ 0x12, 0x00, 0x7C, 0xFD, 0x83, 0x78, 0x0D, 0x0D, 0x03, 0x94, 0xC3, 0xE6, 0xE4, 0x06, 0x06, 0x50, ++ 0x47, 0x80, 0xF6, 0x08, 0xAF, 0x07, 0x90, 0xE4, 0x31, 0x5D, 0x75, 0xF0, 0x12, 0xBD, 0x5E, 0x75, ++ 0x37, 0x80, 0x19, 0x0E, 0xC3, 0xE6, 0x84, 0x78, 0x29, 0x50, 0x01, 0x94, 0xB2, 0x07, 0x90, 0x06, ++ 0xE6, 0x18, 0xFF, 0xE0, 0xFD, 0xE6, 0x08, 0xFE, 0x80, 0x08, 0x06, 0xA8, 0xD8, 0x33, 0xC3, 0x02, ++ 0x54, 0xEF, 0xFE, 0xFC, 0x54, 0xEF, 0xFD, 0x0F, 0x2E, 0xED, 0xFF, 0xF0, 0x90, 0x4F, 0x0F, 0x54, ++ 0x80, 0xF0, 0xB2, 0x07, 0x23, 0x5D, 0x75, 0x06, 0x78, 0xD0, 0x5E, 0x75, 0x03, 0x54, 0xE6, 0x83, ++ 0xFF, 0xF0, 0x54, 0xC4, 0xE0, 0xB2, 0x07, 0x90, 0xF0, 0x4F, 0xCF, 0x54, 0x09, 0x08, 0x30, 0x22, ++ 0xBC, 0x7F, 0x20, 0x7E, 0x31, 0x1D, 0x0E, 0x12, 0x00, 0x90, 0xE4, 0xF7, 0x5F, 0x75, 0xF0, 0xA1, ++ 0x6A, 0x60, 0x75, 0x02, 0x75, 0x01, 0x73, 0x75, 0x5E, 0x75, 0x22, 0x5D, 0xA4, 0x09, 0x90, 0x4D, ++ 0x44, 0x1F, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x80, 0x10, 0x44, 0xE0, 0xB0, 0xC0, 0x09, 0x90, 0xF0, ++ 0x44, 0xF9, 0x54, 0xE0, 0xE4, 0x22, 0xF0, 0x04, 0xFA, 0x07, 0x90, 0xFD, 0x24, 0x75, 0xFC, 0xE0, ++ 0x37, 0x25, 0x75, 0x08, 0xF0, 0x75, 0x03, 0x54, 0x00, 0x24, 0xA4, 0x20, 0x34, 0xF0, 0xE5, 0xFF, ++ 0x09, 0x90, 0xFE, 0x0D, 0xF0, 0x40, 0x74, 0xC8, 0xF5, 0x26, 0xF5, 0xE4, 0x8E, 0x82, 0x8F, 0x27, ++ 0x07, 0x54, 0xE0, 0x83, 0x93, 0xED, 0x20, 0x90, 0x82, 0x25, 0x85, 0xFF, 0xE0, 0x83, 0x24, 0x85, ++ 0x25, 0xA4, 0xF0, 0x8F, 0xF0, 0xE5, 0xFF, 0xE0, 0x25, 0xEF, 0xFE, 0x33, 0xEE, 0x27, 0xF5, 0x27, ++ 0x26, 0xF5, 0x26, 0x35, 0x25, 0x25, 0x65, 0x74, 0x35, 0xE4, 0x25, 0xF5, 0xEC, 0x24, 0xF5, 0x24, ++ 0x3F, 0x54, 0x13, 0x13, 0x75, 0x03, 0x54, 0xFC, 0x24, 0xA4, 0x20, 0xF0, 0xF0, 0xE5, 0xFF, 0x00, ++ 0x0D, 0xFE, 0x0D, 0x34, 0xE4, 0xB6, 0x04, 0xBD, 0x20, 0x90, 0xED, 0xFD, 0xE5, 0xFF, 0x93, 0xDE, ++ 0x40, 0x9F, 0xD3, 0x26, 0x0E, 0xBD, 0x0D, 0x04, 0x21, 0x06, 0x90, 0xF0, 0x22, 0x22, 0xF0, 0xED, ++ 0x41, 0x52, 0x54, 0x09, 0x00, 0x0A, 0x4B, 0x43, 0x41, 0x42, 0x09, 0x09, 0x49, 0x53, 0x5F, 0x44, ++ 0x09, 0x00, 0x0A, 0x47, 0x3A, 0x64, 0x25, 0x09, 0x64, 0x25, 0x20, 0x00, 0x64, 0x25, 0x20, 0x00, ++ 0x00, 0x42, 0x64, 0x20, 0x20, 0x44, 0x25, 0x20, 0x00, 0x6D, 0x70, 0x70, 0x20, 0x44, 0x25, 0x20, ++ 0x00, 0x43, 0x47, 0x41, 0x20, 0x44, 0x25, 0x20, 0x00, 0x74, 0x69, 0x42, 0x00, 0x44, 0x25, 0x20, ++ 0x09, 0x09, 0x00, 0x0A, 0x2D, 0x2D, 0x2D, 0x2D, 0x0A, 0x00, 0x0A, 0x2D, 0x37, 0x08, 0x00, 0x0A, ++ 0x01, 0x09, 0x9C, 0x08, 0x64, 0x08, 0x66, 0x09, 0x2E, 0x09, 0xC9, 0x08, 0x73, 0xE5, 0x93, 0x09, ++ 0xE3, 0x01, 0x02, 0x70, 0x00, 0x7F, 0x20, 0x7E, 0x90, 0x1D, 0x0E, 0x12, 0x44, 0xE0, 0xB9, 0x09, ++ 0x18, 0x51, 0xF0, 0x04, 0xE0, 0xAE, 0x07, 0x90, 0x90, 0xF0, 0x20, 0x44, 0x44, 0xE0, 0x98, 0x07, ++ 0x0C, 0x12, 0xF0, 0x01, 0x90, 0xAF, 0x91, 0xAE, 0x44, 0xE0, 0xB0, 0x07, 0x06, 0x90, 0xF0, 0x20, ++ 0x20, 0x44, 0xE0, 0x14, 0xBE, 0x07, 0x90, 0xF0, 0x25, 0x08, 0x54, 0xE0, 0x06, 0x90, 0xFF, 0xE0, ++ 0xEF, 0x54, 0xE0, 0x14, 0x07, 0x90, 0xF0, 0x4F, 0xF0, 0x13, 0x74, 0x4B, 0x74, 0x4C, 0x07, 0x90, ++ 0x08, 0x90, 0xF0, 0x88, 0x8F, 0x54, 0xE0, 0x4B, 0x90, 0xF0, 0x50, 0x44, 0x04, 0x74, 0x6D, 0x07, ++ 0x6C, 0xF5, 0xE4, 0xF0, 0x75, 0x25, 0x13, 0x75, 0x10, 0x75, 0xA7, 0x14, 0x31, 0x06, 0x90, 0x0B, ++ 0x13, 0x13, 0xFF, 0xE0, 0xE0, 0x30, 0x3F, 0x54, 0x90, 0xEC, 0xD2, 0x08, 0xFF, 0x74, 0xC7, 0x09, ++ 0x74, 0xEE, 0xD2, 0xF0, 0x07, 0x14, 0xB5, 0xA7, 0x13, 0xB5, 0x25, 0x74, 0x90, 0x18, 0x51, 0x02, ++ 0x44, 0xE0, 0xAE, 0x01, 0xFF, 0xE0, 0xF0, 0x04, 0xE0, 0x91, 0x07, 0x90, 0x54, 0x13, 0x13, 0xC4, ++ 0xC4, 0xEF, 0xFE, 0x01, 0xFD, 0x01, 0x54, 0x13, 0xFF, 0xDF, 0x54, 0xEF, 0x01, 0x54, 0x4E, 0xED, ++ 0xE0, 0x54, 0x33, 0xC4, 0xAE, 0x01, 0x90, 0x4F, 0x90, 0xFF, 0xE0, 0xF0, 0xC4, 0xE0, 0x91, 0x07, ++ 0xFE, 0x01, 0x54, 0x13, 0x13, 0x13, 0x13, 0xEF, 0xEF, 0xFD, 0x01, 0x54, 0xED, 0xFF, 0xF7, 0x54, ++ 0x33, 0x01, 0x54, 0x4E, 0xF8, 0x54, 0x33, 0x33, 0xAE, 0x01, 0x90, 0x4F, 0x90, 0xFF, 0xE0, 0xF0, ++ 0xC3, 0xE0, 0x91, 0x07, 0xFE, 0x01, 0x54, 0x13, 0x01, 0x54, 0xC4, 0xEF, 0xEF, 0x54, 0xEF, 0xFD, ++ 0x54, 0x4E, 0xED, 0xFF, 0x54, 0xC4, 0xFE, 0x01, 0x01, 0x90, 0x4F, 0xF0, 0x07, 0x90, 0xF0, 0xAE, ++ 0xF0, 0x62, 0x74, 0x91, 0xE0, 0x31, 0x06, 0x90, 0x3F, 0x54, 0x13, 0x13, 0xD2, 0x02, 0xE0, 0x20, ++ 0x12, 0x74, 0x7F, 0xEE, 0x12, 0x50, 0xB4, 0x0B, 0x75, 0x67, 0xF5, 0xE4, 0x6A, 0x75, 0x02, 0x69, ++ 0x4E, 0x6B, 0x75, 0x08, 0x75, 0x0E, 0x68, 0x75, 0x6C, 0xE5, 0x01, 0x6C, 0x0B, 0x20, 0x05, 0x60, ++ 0xAF, 0x6E, 0x51, 0x02, 0x54, 0xC4, 0xEF, 0x20, 0x40, 0xE0, 0x20, 0x0F, 0x20, 0xEF, 0x20, 0xAF, ++ 0x20, 0xAF, 0x3A, 0xE0, 0x20, 0x13, 0xC3, 0xEF, 0x20, 0xAF, 0x32, 0xE0, 0x54, 0x13, 0xC4, 0xEF, ++ 0x28, 0xE0, 0x20, 0x07, 0x13, 0xEF, 0x20, 0xAF, 0x20, 0x3F, 0x54, 0x13, 0x50, 0x74, 0x1E, 0xE0, ++ 0x04, 0x70, 0x14, 0x65, 0x13, 0x65, 0x2B, 0x74, 0xA7, 0x74, 0x12, 0x60, 0x74, 0x09, 0x14, 0xB5, ++ 0x04, 0x13, 0xB5, 0x25, 0x04, 0x40, 0x21, 0x91, 0x3B, 0x50, 0xAD, 0x91, 0xE0, 0x03, 0x06, 0x90, ++ 0x90, 0xF0, 0xFB, 0x54, 0x44, 0xE0, 0x35, 0x06, 0x06, 0x90, 0xF0, 0x01, 0xFE, 0x54, 0xE0, 0x29, ++ 0xB9, 0x01, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xE0, 0xB0, 0x07, 0x90, ++ 0xC2, 0xF0, 0xBF, 0x54, 0xC2, 0xED, 0xC2, 0xEC, 0x7E, 0xEF, 0xC2, 0xEE, 0x8E, 0x60, 0x7F, 0x02, ++ 0x8E, 0x60, 0x8F, 0x5F, 0x22, 0x5C, 0x8F, 0x5B, 0x74, 0xC8, 0x09, 0x90, 0x07, 0x90, 0xF0, 0x20, ++ 0x03, 0x54, 0xE0, 0xBC, 0x70, 0x37, 0x08, 0x90, 0x07, 0x90, 0xE0, 0x0F, 0x08, 0x90, 0xF0, 0xC1, ++ 0x07, 0x90, 0xE0, 0x9C, 0x0D, 0x80, 0xF0, 0xC2, 0xC2, 0x07, 0x90, 0xE0, 0x9C, 0x08, 0x90, 0xF0, ++ 0xC1, 0x07, 0x90, 0xE0, 0xBC, 0x07, 0x90, 0xF0, 0x03, 0x54, 0xC4, 0xE0, 0x01, 0x09, 0x90, 0xFF, ++ 0x0D, 0x02, 0xBF, 0xE0, 0xF0, 0xC3, 0x07, 0x90, 0xE0, 0x66, 0x09, 0x90, 0xF0, 0xC4, 0x07, 0x90, ++ 0xC4, 0x07, 0x90, 0x22, 0x66, 0x09, 0x90, 0xF0, 0xC3, 0x07, 0x90, 0xE0, 0x74, 0x78, 0x22, 0xF0, ++ 0x76, 0x08, 0xC3, 0x76, 0x7F, 0x20, 0x7E, 0x50, 0x7C, 0x67, 0xAD, 0x13, 0x0D, 0x0D, 0x12, 0x00, ++ 0xC8, 0x09, 0x90, 0xE4, 0xEF, 0x69, 0xAF, 0xF0, 0x33, 0xC4, 0x03, 0x54, 0xE0, 0xFF, 0xE0, 0x54, ++ 0xF0, 0x4F, 0x9F, 0x54, 0x25, 0xEF, 0x67, 0xAF, 0xF5, 0x4E, 0x24, 0xE0, 0x20, 0x34, 0xE4, 0x82, ++ 0x93, 0xE4, 0x83, 0xF5, 0x93, 0x01, 0x74, 0xFE, 0x25, 0xF5, 0x24, 0x8E, 0xE5, 0x08, 0x27, 0x75, ++ 0x00, 0x07, 0xB4, 0x69, 0xCE, 0x61, 0x02, 0x40, 0xF8, 0xBF, 0x22, 0x90, 0x02, 0x73, 0x28, 0x28, ++ 0x23, 0x02, 0x9E, 0x23, 0xD4, 0x22, 0x02, 0xA1, 0x02, 0xE5, 0x22, 0x02, 0x23, 0x02, 0x16, 0x23, ++ 0x7A, 0x23, 0x02, 0x5C, 0x19, 0x7F, 0x20, 0x7E, 0x85, 0x82, 0x25, 0x85, 0xFC, 0xE0, 0x83, 0x24, ++ 0x61, 0xFD, 0xE0, 0xA3, 0xAF, 0x6A, 0xAE, 0x99, 0x8E, 0x82, 0x8F, 0x6B, 0x7D, 0xFF, 0xE0, 0x83, ++ 0x12, 0x1F, 0x7C, 0xB1, 0x07, 0xAD, 0xEC, 0x0B, 0x68, 0x95, 0xC3, 0xED, 0x68, 0x8D, 0x02, 0x50, ++ 0x1D, 0x7F, 0x20, 0x7E, 0x0D, 0x12, 0x00, 0x7C, 0x25, 0x65, 0x74, 0x0D, 0xE4, 0x6B, 0xF5, 0x6B, ++ 0x6A, 0xF5, 0x6A, 0x35, 0x67, 0xAF, 0xCE, 0x61, 0x24, 0xE0, 0x25, 0xEF, 0xE4, 0x82, 0xF5, 0x56, ++ 0x83, 0xF5, 0x20, 0x34, 0x74, 0xFE, 0x93, 0xE4, 0x24, 0x8E, 0x93, 0x01, 0x82, 0xF5, 0x25, 0xF5, ++ 0xE0, 0xA3, 0x83, 0x8E, 0xA2, 0x06, 0x78, 0xFD, 0xFB, 0xD8, 0x13, 0xE7, 0x05, 0x78, 0xED, 0xFF, ++ 0xD8, 0x13, 0xE7, 0xA2, 0xFD, 0x2D, 0x2F, 0xFB, 0x05, 0x70, 0x67, 0xE5, 0xED, 0x20, 0x06, 0x90, ++ 0x7F, 0x20, 0x7E, 0xF0, 0x95, 0x33, 0xED, 0x24, 0x3D, 0x80, 0xFC, 0xE0, 0x75, 0xEF, 0x67, 0xAF, ++ 0x24, 0xA4, 0x20, 0xF0, 0xF0, 0xE5, 0xFF, 0x00, 0x82, 0x8F, 0x0D, 0x34, 0x54, 0xE0, 0x83, 0xF5, ++ 0x00, 0x7C, 0xFD, 0x0F, 0x2C, 0x7F, 0x20, 0x7E, 0x67, 0xAF, 0x1F, 0x80, 0x20, 0xF0, 0x75, 0xEF, ++ 0xFF, 0x0A, 0x24, 0xA4, 0x0D, 0x34, 0xF0, 0xE5, 0x83, 0xF5, 0x82, 0x8F, 0x0F, 0x54, 0xC4, 0xE0, ++ 0x0F, 0x54, 0x00, 0x7C, 0x7F, 0x20, 0x7E, 0xFD, 0x0D, 0x0D, 0x12, 0x34, 0x27, 0x75, 0x30, 0x80, ++ 0x26, 0xF5, 0xE4, 0x0A, 0x95, 0xC3, 0x26, 0xE5, 0xE5, 0x23, 0x50, 0x27, 0xFF, 0x0F, 0x54, 0x26, ++ 0xE0, 0xC8, 0x09, 0x90, 0xF0, 0x4F, 0xF0, 0x54, 0x3C, 0x7F, 0x20, 0x7E, 0x85, 0x82, 0x25, 0x85, ++ 0xFC, 0xE0, 0x83, 0x24, 0x12, 0xFD, 0xE0, 0xA3, 0x26, 0x05, 0x0D, 0x0D, 0x20, 0x7E, 0xD6, 0x80, ++ 0x0E, 0x12, 0x40, 0x7F, 0xEF, 0x69, 0xAF, 0x1D, 0xE4, 0xFF, 0x01, 0x24, 0x00, 0x7C, 0xFE, 0x33, ++ 0x02, 0x12, 0x07, 0x7D, 0xE5, 0x69, 0x8D, 0x96, 0x70, 0x02, 0x64, 0x69, 0xEF, 0x67, 0xAF, 0x33, ++ 0xE4, 0xFF, 0x01, 0x24, 0x03, 0x54, 0xEF, 0x33, 0x20, 0x7E, 0x67, 0xF5, 0x0E, 0x12, 0x42, 0x7F, ++ 0x70, 0x67, 0xE5, 0x1D, 0xEF, 0x68, 0xAF, 0x1B, 0x54, 0xC4, 0x0F, 0x54, 0x06, 0x90, 0xFF, 0xF0, ++ 0x0F, 0x54, 0xE0, 0x21, 0xF5, 0xE4, 0xF0, 0x4F, 0x7F, 0x20, 0x7E, 0x6C, 0x1D, 0x0E, 0x12, 0x4B, ++ 0xC8, 0x09, 0x90, 0x22, 0x90, 0xF0, 0x40, 0x74, 0xD3, 0xE0, 0x4F, 0x08, 0x67, 0x40, 0x0A, 0x94, ++ 0xE0, 0xB4, 0x08, 0x90, 0x40, 0x0A, 0x94, 0xD3, 0x19, 0x09, 0x90, 0x5E, 0x0A, 0x94, 0xD3, 0xE0, ++ 0x09, 0x90, 0x55, 0x40, 0x94, 0xD3, 0xE0, 0x7E, 0x90, 0x4C, 0x40, 0x0A, 0x94, 0xE0, 0x4E, 0x08, ++ 0x90, 0x44, 0x50, 0x28, 0xC3, 0xE0, 0xB3, 0x08, 0x3B, 0x50, 0x28, 0x94, 0xE0, 0x18, 0x09, 0x90, ++ 0x50, 0x28, 0x94, 0xC3, 0x7D, 0x09, 0x90, 0x32, 0x28, 0x94, 0xC3, 0xE0, 0x08, 0x90, 0x29, 0x50, ++ 0x01, 0x94, 0xE0, 0x37, 0x08, 0x90, 0x21, 0x40, 0x94, 0xD3, 0xE0, 0x9C, 0x90, 0x18, 0x40, 0x01, ++ 0xD3, 0xE0, 0x01, 0x09, 0x0F, 0x40, 0x01, 0x94, 0xE0, 0x66, 0x09, 0x90, 0x40, 0x01, 0x94, 0xD3, ++ 0x80, 0x78, 0xE4, 0x06, 0x78, 0x03, 0x80, 0xF6, 0x80, 0x78, 0x06, 0x80, 0x64, 0x94, 0xD3, 0xE6, ++ 0x20, 0x7E, 0x09, 0x40, 0x0E, 0x12, 0x08, 0x7F, 0xC3, 0x22, 0xD3, 0x1D, 0x90, 0x22, 0xC3, 0x22, ++ 0x54, 0xE0, 0xFA, 0x07, 0x01, 0xBF, 0xFF, 0x03, 0x80, 0x01, 0x7F, 0x04, 0x8F, 0x00, 0x7F, 0x02, ++ 0xFA, 0x07, 0x90, 0x26, 0x03, 0x54, 0xC4, 0xE0, 0x04, 0x03, 0xBF, 0xFF, 0x02, 0x80, 0x01, 0x7F, ++ 0x07, 0x90, 0x00, 0x7F, 0x03, 0x54, 0xE0, 0xBC, 0x04, 0x01, 0xBE, 0xFE, 0x02, 0x80, 0x01, 0x7E, ++ 0x07, 0x90, 0x00, 0x7E, 0x54, 0xC4, 0xE0, 0xBC, 0x03, 0xBB, 0xFB, 0x03, 0x80, 0x01, 0x7B, 0x04, ++ 0xEE, 0x00, 0x7B, 0x02, 0x70, 0xB9, 0x07, 0x90, 0x07, 0x54, 0xE0, 0x0B, 0x13, 0xE0, 0x24, 0xF5, ++ 0x09, 0x80, 0x13, 0x13, 0x13, 0x13, 0x13, 0xE0, 0x24, 0xF5, 0x07, 0x54, 0xF5, 0x07, 0x54, 0xE0, ++ 0x07, 0x90, 0xEB, 0x25, 0xE0, 0x0A, 0x70, 0xBA, 0xE0, 0xF9, 0x07, 0x54, 0x80, 0x13, 0x13, 0x13, ++ 0x13, 0x13, 0xE0, 0x08, 0xF9, 0x07, 0x54, 0x13, 0xFC, 0x07, 0x54, 0xE0, 0xB5, 0x02, 0x7D, 0xEE, ++ 0x01, 0x7D, 0x02, 0x26, 0x05, 0x07, 0xB5, 0xEB, 0x80, 0x04, 0x05, 0x43, 0x08, 0x05, 0x43, 0x03, ++ 0x01, 0x64, 0x6F, 0xEB, 0x54, 0x33, 0x33, 0x33, 0x26, 0xE5, 0xFF, 0x08, 0x25, 0x01, 0x64, 0x6E, ++ 0x54, 0xE0, 0x25, 0xE0, 0x90, 0xFF, 0x4F, 0x04, 0x54, 0xE0, 0xB2, 0x07, 0x54, 0xC4, 0x6D, 0x0F, ++ 0x06, 0x90, 0x4F, 0xF0, 0x25, 0xE5, 0xF0, 0x23, 0xEF, 0xFF, 0xFE, 0x24, 0x0F, 0x54, 0xF8, 0xC4, ++ 0xEF, 0xFF, 0x68, 0xC8, 0xE5, 0xFF, 0x70, 0x54, 0xFB, 0xFE, 0x24, 0x24, 0xFB, 0x07, 0x54, 0xEB, ++ 0xE9, 0xFB, 0x4F, 0xEB, 0xEF, 0xFF, 0xFE, 0x24, 0xEC, 0xFA, 0x07, 0x54, 0xEF, 0xFF, 0xFE, 0x24, ++ 0x4A, 0x70, 0x54, 0xC4, 0x06, 0x90, 0xEB, 0xFF, 0xA3, 0xF0, 0xCF, 0x24, 0xE4, 0x22, 0xF0, 0xEF, ++ 0xBF, 0x0F, 0x00, 0xFF, 0x90, 0x22, 0xFB, 0x06, 0xFF, 0x74, 0x68, 0x07, 0x6C, 0x07, 0x90, 0xF0, ++ 0x06, 0x90, 0xF0, 0x14, 0x13, 0xFF, 0xE0, 0x31, 0x20, 0x3F, 0x54, 0x13, 0x75, 0xC1, 0x02, 0xE0, ++ 0xE0, 0x68, 0x07, 0x90, 0x12, 0x05, 0xE2, 0x20, 0x50, 0xC1, 0x27, 0x2B, 0x90, 0x27, 0x2B, 0x12, ++ 0x54, 0xE0, 0xBE, 0x07, 0x70, 0x18, 0x64, 0x18, 0xB0, 0x07, 0x90, 0x77, 0x44, 0xFC, 0x54, 0xE0, ++ 0xA4, 0xF1, 0xF0, 0x01, 0xE0, 0xDB, 0x09, 0x90, 0x90, 0xF0, 0xFE, 0x54, 0x54, 0xE0, 0xF9, 0x01, ++ 0x09, 0x90, 0xFF, 0x70, 0x8F, 0x54, 0xE0, 0xDF, 0x01, 0x90, 0xF0, 0x4F, 0x0C, 0x54, 0xE0, 0xF9, ++ 0xDE, 0x09, 0x90, 0xFF, 0x4F, 0xF3, 0x54, 0xE0, 0xDB, 0x09, 0x90, 0xF0, 0xF0, 0x40, 0x44, 0xE0, ++ 0xE0, 0xF9, 0x01, 0x90, 0x30, 0xE0, 0x09, 0x90, 0x54, 0xE0, 0x06, 0xE0, 0x06, 0x80, 0xF0, 0x0F, ++ 0x44, 0x0F, 0x54, 0xE0, 0x01, 0x90, 0xF0, 0x60, 0x09, 0x90, 0xE0, 0xF9, 0x08, 0xE1, 0x30, 0xDC, ++ 0x44, 0xF3, 0x54, 0xE0, 0x06, 0x80, 0xF0, 0x08, 0x44, 0xF3, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x04, ++ 0x04, 0x44, 0xE0, 0x6D, 0x6C, 0x07, 0x90, 0xF0, 0x12, 0xF0, 0x08, 0x74, 0x05, 0x80, 0xC1, 0x2D, ++ 0x2F, 0x12, 0xA4, 0xF1, 0x6C, 0x07, 0x90, 0x2A, 0x1E, 0xE0, 0x30, 0xE0, 0x12, 0xF0, 0x01, 0x74, ++ 0x09, 0x90, 0x55, 0x2F, 0x0F, 0x54, 0xE0, 0xF5, 0x0E, 0x05, 0xBF, 0xFF, 0xE0, 0x47, 0x07, 0x90, ++ 0x80, 0xF0, 0xEF, 0x54, 0x2A, 0x2F, 0x12, 0x05, 0x08, 0x90, 0xEE, 0xC2, 0x65, 0xF5, 0xE0, 0x34, ++ 0x74, 0xC8, 0x09, 0x90, 0x08, 0x90, 0xF0, 0x40, 0x94, 0xD3, 0xE0, 0x37, 0x90, 0x1B, 0x40, 0x01, ++ 0xD3, 0xE0, 0x9C, 0x08, 0x12, 0x40, 0x01, 0x94, 0xE0, 0x01, 0x09, 0x90, 0x40, 0x01, 0x94, 0xD3, ++ 0x66, 0x09, 0x90, 0x09, 0x01, 0x94, 0xD3, 0xE0, 0x2B, 0x12, 0x03, 0x50, 0xC8, 0x09, 0x90, 0x50, ++ 0x22, 0xF0, 0x65, 0xE5, 0x60, 0xE6, 0x7B, 0x78, 0xB0, 0x07, 0x90, 0x3B, 0x44, 0xFC, 0x54, 0xE0, ++ 0x09, 0x90, 0xF0, 0x01, 0xE0, 0x54, 0xE0, 0xD1, 0x90, 0xF0, 0x05, 0x44, 0x01, 0x74, 0xC3, 0x09, ++ 0xBB, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x0D, 0x74, 0x90, 0xE0, 0xFC, 0x01, 0x90, 0xF0, 0xB5, 0x07, ++ 0x54, 0xE0, 0xB1, 0x07, 0x07, 0x90, 0xF0, 0xFD, 0xF0, 0x02, 0x74, 0xAF, 0x75, 0x27, 0x13, 0x75, ++ 0x94, 0xE1, 0xCD, 0x14, 0x74, 0xBB, 0x09, 0x90, 0x07, 0x90, 0xF0, 0x0D, 0xF0, 0x02, 0x74, 0xAF, ++ 0xE5, 0x00, 0x0A, 0x90, 0x90, 0xE4, 0xF0, 0x64, 0x90, 0xF0, 0x01, 0x08, 0x90, 0xF0, 0x02, 0x08, ++ 0x55, 0x74, 0x07, 0x08, 0xB1, 0x07, 0x90, 0xF0, 0xF0, 0xFD, 0x54, 0xE0, 0xE0, 0xB1, 0x07, 0x90, ++ 0x90, 0x0A, 0xE1, 0x20, 0x20, 0xE0, 0x6A, 0x07, 0x80, 0x00, 0x03, 0xE0, 0x08, 0x90, 0xE4, 0xEF, ++ 0x01, 0x90, 0xF0, 0x07, 0x0A, 0x90, 0xE0, 0xFE, 0x64, 0xE5, 0xF0, 0x00, 0x09, 0x90, 0x06, 0x60, ++ 0xF0, 0x05, 0x74, 0xFB, 0x74, 0xF4, 0x09, 0x90, 0x01, 0x90, 0xF0, 0x01, 0xE0, 0x30, 0xE0, 0xF8, ++ 0xB1, 0x9F, 0xB1, 0x04, 0xD1, 0x09, 0x90, 0x9F, 0x44, 0xE0, 0x54, 0xE0, 0x09, 0x90, 0xF0, 0x05, ++ 0xF0, 0x01, 0x74, 0xC3, 0xE0, 0xF8, 0x01, 0x90, 0x30, 0x13, 0xC3, 0xFF, 0x9F, 0xB1, 0x04, 0xE0, ++ 0x07, 0x90, 0x9F, 0xB1, 0xFC, 0x54, 0xE0, 0xB0, 0xF1, 0xF0, 0x01, 0x44, 0x6A, 0x07, 0x90, 0x97, ++ 0x03, 0xE0, 0x30, 0xE0, 0x75, 0x50, 0x2B, 0x02, 0x14, 0x75, 0x27, 0x13, 0xBE, 0x07, 0x90, 0xCD, ++ 0x02, 0xE3, 0x30, 0xE0, 0x12, 0x22, 0xCD, 0xF1, 0x07, 0x90, 0xF2, 0x2E, 0x20, 0x44, 0xE0, 0xB0, ++ 0xB3, 0x28, 0x12, 0xF0, 0xE0, 0xBE, 0x07, 0x90, 0x90, 0x13, 0xE4, 0x30, 0x20, 0xE0, 0x90, 0x07, ++ 0x44, 0xE0, 0x1A, 0xE0, 0x01, 0x90, 0xF0, 0x01, 0x05, 0x44, 0xE0, 0xB9, 0x07, 0x90, 0x22, 0xF0, ++ 0xFE, 0x54, 0xE0, 0x90, 0xB9, 0x01, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0xE6, 0x7B, 0x78, 0x22, ++ 0x07, 0x90, 0x3E, 0x60, 0xC4, 0xFF, 0xE0, 0xB2, 0x54, 0x13, 0x13, 0x13, 0x30, 0xE0, 0x30, 0x01, ++ 0xE0, 0xB1, 0x07, 0x90, 0x90, 0x0A, 0xE1, 0x20, 0x20, 0xE0, 0x6A, 0x07, 0x80, 0x00, 0x03, 0xE0, ++ 0x90, 0x97, 0xF1, 0xEF, 0x54, 0xE0, 0xB2, 0x07, 0x07, 0x90, 0xF0, 0x7F, 0xF0, 0x08, 0x74, 0x6C, ++ 0xE0, 0xF4, 0x09, 0x90, 0x90, 0xF0, 0xEF, 0x54, 0x30, 0xE0, 0x6A, 0x07, 0x07, 0x80, 0x0B, 0xE0, ++ 0xE0, 0x6A, 0x07, 0x90, 0x61, 0x02, 0xE0, 0x30, 0x6C, 0x07, 0x90, 0x50, 0x90, 0xF0, 0x42, 0x74, ++ 0xFF, 0x74, 0x68, 0x07, 0x07, 0x90, 0xE0, 0xF0, 0x06, 0xE2, 0x30, 0xB0, 0xF0, 0x40, 0x44, 0xE0, ++ 0x54, 0xE0, 0x04, 0x80, 0x27, 0x12, 0xF0, 0xBF, 0xBE, 0x07, 0x90, 0xA4, 0x72, 0xE3, 0x30, 0xE0, ++ 0xE0, 0xB1, 0x07, 0x90, 0x11, 0x6B, 0xE1, 0x30, 0x47, 0x07, 0x90, 0xB3, 0xF0, 0xFB, 0x54, 0xE0, ++ 0x74, 0x6C, 0x07, 0x90, 0xEC, 0xD2, 0xF0, 0x40, 0x07, 0x90, 0xED, 0xC2, 0xF7, 0x54, 0xE0, 0x47, ++ 0x90, 0xC1, 0xB1, 0xF0, 0x28, 0x74, 0x06, 0x08, 0x01, 0x08, 0x90, 0xF0, 0x90, 0xF0, 0xE4, 0x74, ++ 0x78, 0xF0, 0x02, 0x08, 0x05, 0x70, 0xE6, 0x7B, 0x04, 0xF4, 0x09, 0x90, 0x68, 0x07, 0x90, 0xF0, ++ 0x1E, 0xE0, 0x30, 0xE0, 0xC3, 0xF0, 0x01, 0x74, 0xE0, 0xB2, 0x01, 0x90, 0x01, 0x90, 0xFF, 0x94, ++ 0xFF, 0x94, 0xE0, 0xB1, 0xE0, 0xA3, 0x0C, 0x50, 0x06, 0x70, 0xF0, 0x04, 0xE0, 0xB1, 0x01, 0x90, ++ 0x07, 0x90, 0xF0, 0x04, 0xE2, 0x30, 0xE0, 0x68, 0xBE, 0x07, 0x90, 0x07, 0x02, 0xE4, 0x20, 0xE0, ++ 0x90, 0x22, 0xE0, 0x31, 0x30, 0xE0, 0xBE, 0x07, 0x07, 0x90, 0x0D, 0xE3, 0xFC, 0x54, 0xE0, 0xB0, ++ 0x94, 0x07, 0x90, 0xF0, 0x22, 0xF0, 0x01, 0x74, 0x74, 0x68, 0x07, 0x90, 0x07, 0x90, 0xF0, 0xFF, ++ 0x90, 0xF0, 0x14, 0x6C, 0x20, 0xE0, 0x68, 0x07, 0x27, 0x71, 0x04, 0xE2, 0x07, 0x90, 0x21, 0x80, ++ 0x40, 0x44, 0xE0, 0xB0, 0xBE, 0x07, 0x90, 0xF0, 0x02, 0xE5, 0x30, 0xE0, 0x07, 0x90, 0xBF, 0x21, ++ 0xE3, 0x30, 0xE0, 0x6C, 0x90, 0xBF, 0x21, 0x02, 0x54, 0xE0, 0xBE, 0x07, 0x21, 0x02, 0x70, 0x30, ++ 0x6C, 0x07, 0x90, 0xE0, 0x02, 0xE0, 0x20, 0xE0, 0x01, 0x74, 0xAC, 0x21, 0x16, 0x81, 0x78, 0xF0, ++ 0x0A, 0x94, 0xD3, 0xE6, 0x55, 0xF1, 0x02, 0x40, 0x64, 0xE6, 0x81, 0x78, 0x90, 0x47, 0x70, 0x0A, ++ 0x30, 0xE0, 0xAE, 0x07, 0x07, 0x90, 0x40, 0xE5, 0xF0, 0x10, 0x74, 0xB5, 0xE0, 0xAE, 0x07, 0x90, ++ 0x90, 0xF0, 0xDF, 0x54, 0x54, 0xE0, 0xB9, 0x09, 0x07, 0x90, 0xF0, 0xFB, 0x02, 0x44, 0xE0, 0xAF, ++ 0xB0, 0x07, 0x90, 0xF0, 0xF0, 0xEF, 0x54, 0xE0, 0xE0, 0xC0, 0x09, 0x90, 0x02, 0x44, 0xF9, 0x54, ++ 0xB1, 0x07, 0x90, 0xF0, 0xF0, 0xFD, 0x54, 0xE0, 0xE0, 0xB2, 0x07, 0x90, 0x90, 0xF0, 0x80, 0x44, ++ 0x54, 0xE0, 0xAF, 0x07, 0x81, 0x78, 0xF0, 0xFD, 0x60, 0x02, 0x64, 0xE6, 0x07, 0x64, 0xE6, 0x0A, ++ 0x7B, 0x78, 0x3A, 0x70, 0x90, 0x35, 0x60, 0xE6, 0x44, 0xE0, 0xBE, 0x09, 0x09, 0x90, 0xF0, 0x01, ++ 0x08, 0x44, 0xE0, 0xBB, 0x04, 0x44, 0xE0, 0xF0, 0xC1, 0x09, 0x90, 0xF0, 0xF0, 0x04, 0x44, 0xE0, ++ 0x74, 0x9C, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x0A, 0x7F, 0x54, 0xE0, 0xDB, 0x6D, 0x07, 0x90, 0xF0, ++ 0xF0, 0xFB, 0x54, 0xE0, 0x74, 0x6C, 0x07, 0x90, 0x9D, 0xD1, 0xF0, 0x08, 0x70, 0xE6, 0x81, 0x78, ++ 0xBE, 0x07, 0x90, 0x07, 0x07, 0xE4, 0x20, 0xE0, 0xE0, 0xBE, 0x07, 0x90, 0x90, 0x20, 0xE5, 0x30, ++ 0x1D, 0x74, 0xF4, 0x09, 0x47, 0x07, 0x90, 0xF0, 0xF0, 0x08, 0x44, 0xE0, 0xF0, 0xEF, 0x54, 0xE0, ++ 0xE0, 0xB0, 0x07, 0x90, 0x75, 0xF0, 0x80, 0x44, 0x14, 0x75, 0x2A, 0x13, 0x22, 0x2D, 0x51, 0x2D, ++ 0xB3, 0x11, 0xF2, 0xD1, 0x90, 0xA4, 0x27, 0x12, 0x44, 0xE0, 0xDB, 0x09, 0x09, 0x90, 0xF0, 0x01, ++ 0x8F, 0x54, 0xE0, 0xDF, 0x90, 0xF0, 0x60, 0x44, 0x54, 0xE0, 0xDE, 0x09, 0xF0, 0x04, 0x44, 0xF3, ++ 0xE0, 0xE0, 0x09, 0x90, 0x10, 0x44, 0x0F, 0x54, 0xDB, 0x09, 0x90, 0xF0, 0xF0, 0x80, 0x44, 0xE0, ++ 0xE0, 0xDC, 0x09, 0x90, 0x04, 0x44, 0xF3, 0x54, 0x6D, 0x07, 0x90, 0xF0, 0xF0, 0x04, 0x44, 0xE0, ++ 0x74, 0x6C, 0x07, 0x90, 0x13, 0x75, 0xF0, 0x08, 0xA7, 0x14, 0x75, 0x25, 0x66, 0xF5, 0xE4, 0x22, ++ 0xE0, 0xBE, 0x07, 0x90, 0xE0, 0x17, 0xE4, 0x20, 0x41, 0x02, 0xE5, 0x30, 0xB0, 0x07, 0x90, 0xBB, ++ 0xF0, 0x7F, 0x54, 0xE0, 0xC4, 0x7D, 0xE0, 0x31, 0xFF, 0xE4, 0x09, 0x7C, 0x07, 0x90, 0x8A, 0xA1, ++ 0xE3, 0x20, 0xE0, 0x6C, 0x68, 0x07, 0x90, 0x20, 0x5F, 0xE2, 0x30, 0xE0, 0x66, 0xE5, 0x66, 0x05, ++ 0x40, 0x0D, 0x94, 0xC3, 0xB0, 0x07, 0x90, 0xCB, 0x44, 0xFC, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x02, ++ 0xE3, 0x30, 0xE0, 0x6C, 0xDB, 0x09, 0x90, 0x29, 0xF0, 0x80, 0x44, 0xE0, 0x74, 0x6C, 0x07, 0x90, ++ 0x20, 0xE0, 0xF0, 0x08, 0x01, 0x90, 0x35, 0xE3, 0xE0, 0x20, 0xE0, 0xF9, 0xE0, 0x09, 0x90, 0x09, ++ 0x44, 0x0F, 0x54, 0xE0, 0x09, 0x90, 0xF0, 0x20, 0xF0, 0x0B, 0x74, 0x9C, 0x07, 0x90, 0x26, 0x81, ++ 0xF0, 0xF7, 0x74, 0x6C, 0x74, 0x6A, 0x07, 0x90, 0x07, 0x90, 0xF0, 0xFF, 0x30, 0x54, 0xE0, 0xBE, ++ 0x07, 0x60, 0x20, 0x64, 0xE0, 0x68, 0x07, 0x90, 0x71, 0x0C, 0xE2, 0x20, 0x90, 0x4F, 0xB1, 0x27, ++ 0x0B, 0x74, 0x9C, 0x09, 0x90, 0x8B, 0x61, 0xF0, 0x20, 0xE0, 0xF9, 0x01, 0x09, 0x90, 0x09, 0xE0, ++ 0x0F, 0x54, 0xE0, 0xE0, 0x90, 0xF0, 0x20, 0x44, 0x0B, 0x74, 0x9C, 0x09, 0x2A, 0x13, 0x75, 0xF0, ++ 0x90, 0xE3, 0x14, 0x75, 0x52, 0x74, 0x6C, 0x07, 0x68, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x02, 0x74, ++ 0x20, 0xE0, 0x68, 0x07, 0x27, 0x71, 0x06, 0xE2, 0x8B, 0x61, 0x4F, 0xB1, 0xE0, 0x6C, 0x07, 0x90, ++ 0x90, 0x0F, 0xE3, 0x30, 0x44, 0xE0, 0xDB, 0x09, 0x07, 0x90, 0xF0, 0x80, 0xF0, 0x08, 0x74, 0x6C, ++ 0x07, 0x90, 0x26, 0x81, 0xE0, 0x30, 0xE0, 0x6A, 0x90, 0x35, 0x80, 0x02, 0x13, 0xE0, 0xF8, 0x01, ++ 0x20, 0x3F, 0x54, 0x13, 0x90, 0x22, 0xC9, 0xE0, 0x30, 0xE0, 0x68, 0x07, 0x07, 0x90, 0x13, 0xE2, ++ 0xE6, 0x20, 0xE0, 0xB0, 0x40, 0x44, 0xE0, 0x1A, 0xB9, 0x01, 0x90, 0xF0, 0xF0, 0x0A, 0x44, 0xE0, ++ 0xB0, 0x07, 0x90, 0x22, 0xF0, 0xBF, 0x54, 0xE0, 0xE0, 0xB9, 0x01, 0x90, 0x22, 0xF0, 0xFD, 0x54, ++ 0xED, 0xC2, 0xEC, 0xC2, 0xEF, 0xC2, 0xEE, 0xC2, 0x74, 0x68, 0x07, 0x90, 0x07, 0x90, 0xF0, 0xFF, ++ 0x07, 0x90, 0xF0, 0x6A, 0x07, 0x90, 0xF0, 0x6C, 0x01, 0x90, 0xF0, 0x6E, 0x70, 0xF4, 0xE0, 0xEA, ++ 0xF4, 0xE0, 0xA3, 0x03, 0x01, 0x90, 0x0E, 0x60, 0xF0, 0x04, 0xE0, 0xEB, 0x01, 0x90, 0x06, 0x70, ++ 0xF0, 0x04, 0xE0, 0xEA, 0x75, 0x2B, 0x13, 0x75, 0xE4, 0x22, 0x50, 0x14, 0xF0, 0x81, 0x0D, 0x90, ++ 0x74, 0x8C, 0x0D, 0x90, 0x07, 0x90, 0xF0, 0x35, 0x04, 0x44, 0xE0, 0x47, 0xB0, 0x07, 0x90, 0xF0, ++ 0x44, 0xFC, 0x54, 0xE0, 0x09, 0x90, 0xF0, 0x01, 0xF0, 0x0A, 0x74, 0x9C, 0x00, 0x66, 0xF5, 0xE4, ++ 0x66, 0xE5, 0x66, 0x05, 0x90, 0xF8, 0x1E, 0xB4, 0x54, 0xE0, 0xB0, 0x07, 0xF0, 0x02, 0x44, 0xFC, ++ 0xE0, 0x47, 0x07, 0x90, 0xE0, 0xF0, 0x20, 0x44, 0x7F, 0xF0, 0xEF, 0x54, 0xB1, 0x61, 0x7E, 0xA8, ++ 0x47, 0x07, 0x90, 0xFB, 0xF0, 0x08, 0x44, 0xE0, 0xE0, 0x6D, 0x07, 0x90, 0x90, 0xF0, 0x04, 0x44, ++ 0x08, 0x74, 0x6C, 0x07, 0xD2, 0xEC, 0xC2, 0xF0, 0xB0, 0x07, 0x90, 0xED, 0xF0, 0x7F, 0x54, 0xE0, ++ 0x75, 0x26, 0x13, 0x75, 0x26, 0xD1, 0xB4, 0x14, 0x01, 0x90, 0x27, 0x71, 0x07, 0x90, 0xE0, 0xFB, ++ 0x01, 0x90, 0xF0, 0xB5, 0xF0, 0x54, 0xE0, 0xF8, 0xFF, 0x0F, 0x54, 0xC4, 0xE0, 0xD1, 0x09, 0x90, ++ 0xF0, 0x4F, 0xE0, 0x54, 0x06, 0x08, 0x90, 0xE4, 0x6E, 0x07, 0x90, 0xF0, 0x03, 0xE0, 0x20, 0xE0, ++ 0x02, 0xF6, 0x80, 0x00, 0x07, 0x90, 0xB4, 0x26, 0xFC, 0x54, 0xE0, 0xB0, 0x78, 0xF0, 0x02, 0x44, ++ 0xB1, 0x58, 0x76, 0x81, 0x6C, 0x07, 0x90, 0x4F, 0x02, 0xE3, 0x30, 0xE0, 0x07, 0x90, 0x3A, 0xA1, ++ 0xE2, 0x20, 0xE0, 0x68, 0x90, 0x3A, 0xA1, 0x02, 0x03, 0x74, 0xA1, 0x08, 0x06, 0x09, 0x90, 0xF0, ++ 0x6B, 0x09, 0x90, 0xF0, 0x08, 0x90, 0xE4, 0xF0, 0x09, 0x90, 0xF0, 0xA1, 0x09, 0x90, 0xF0, 0x06, ++ 0x07, 0x90, 0xF0, 0x6B, 0xE3, 0x20, 0xE0, 0x6C, 0x68, 0x07, 0x90, 0x07, 0x02, 0xE2, 0x20, 0xE0, ++ 0x08, 0x90, 0x3A, 0xA1, 0xF0, 0x03, 0x74, 0xA3, 0xF0, 0x08, 0x09, 0x90, 0xF0, 0x6D, 0x09, 0x90, ++ 0xA3, 0x08, 0x90, 0xE4, 0x08, 0x09, 0x90, 0xF0, 0x6D, 0x09, 0x90, 0xF0, 0x6C, 0x07, 0x90, 0xF0, ++ 0x07, 0xE3, 0x20, 0xE0, 0xE0, 0x68, 0x07, 0x90, 0xA1, 0x02, 0xE2, 0x20, 0x08, 0x90, 0xE4, 0x3A, ++ 0x09, 0x90, 0xF0, 0xB6, 0x09, 0x90, 0xF0, 0x1B, 0x09, 0x90, 0xF0, 0x80, 0xF0, 0x08, 0x74, 0x9C, ++ 0xE0, 0x6C, 0x07, 0x90, 0x90, 0x07, 0xE3, 0x20, 0x20, 0xE0, 0x68, 0x07, 0x7A, 0x80, 0x02, 0xE2, ++ 0xE0, 0x23, 0x06, 0x90, 0x54, 0x13, 0x13, 0xFF, 0x0D, 0xE0, 0x30, 0x3F, 0x74, 0x01, 0x0D, 0x90, ++ 0x90, 0xE4, 0xF0, 0x1B, 0x80, 0xF0, 0x21, 0x0D, 0x0D, 0x90, 0xE4, 0x0B, 0x0D, 0x90, 0xF0, 0x01, ++ 0xF0, 0x1B, 0x74, 0x21, 0x74, 0x41, 0x0D, 0x90, 0x0D, 0x90, 0xF0, 0x1B, 0x07, 0x90, 0xF0, 0x61, ++ 0xE3, 0x20, 0xE0, 0x6C, 0x68, 0x07, 0x90, 0x07, 0x02, 0xE2, 0x20, 0xE0, 0x09, 0x90, 0x3C, 0x80, ++ 0xF0, 0x0C, 0x74, 0xBB, 0xC3, 0x09, 0x90, 0xE4, 0xC1, 0x09, 0x90, 0xF0, 0xE4, 0xF0, 0x04, 0x74, ++ 0xF0, 0xB9, 0x09, 0x90, 0xE0, 0x6C, 0x07, 0x90, 0x90, 0x07, 0xE3, 0x20, 0x20, 0xE0, 0x68, 0x07, ++ 0x16, 0x80, 0x02, 0xE2, 0xF4, 0x7C, 0x24, 0x7D, 0x8A, 0xB1, 0xFF, 0xE4, 0xE0, 0x6C, 0x07, 0x90, ++ 0x90, 0x07, 0xE3, 0x20, 0x20, 0xE0, 0x68, 0x07, 0x8B, 0x61, 0x02, 0xE2, 0x74, 0x6C, 0x07, 0x90, ++ 0x13, 0x75, 0xF0, 0x52, 0x43, 0x14, 0x75, 0x2E, 0xE0, 0xFD, 0x01, 0x90, 0x90, 0x22, 0x64, 0xF5, ++ 0x0A, 0x74, 0xAF, 0x07, 0xB0, 0x07, 0x90, 0xF0, 0xF0, 0xDF, 0x54, 0xE0, 0x94, 0x07, 0x90, 0xE4, ++ 0xF5, 0x09, 0x90, 0xF0, 0x44, 0xF0, 0x54, 0xE0, 0x09, 0x90, 0xF0, 0x02, 0xFD, 0x54, 0xE0, 0xC5, ++ 0xBB, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x0F, 0x74, 0x03, 0x74, 0xC3, 0x09, 0xC1, 0x09, 0x90, 0xF0, ++ 0x90, 0xF0, 0x07, 0x74, 0x03, 0x74, 0xB9, 0x09, 0x07, 0x90, 0x22, 0xF0, 0xEF, 0x54, 0xE0, 0x47, ++ 0x01, 0x54, 0xEF, 0xF0, 0xFF, 0xF0, 0x54, 0xC4, 0xE0, 0x48, 0x07, 0x90, 0xF0, 0x4F, 0xEF, 0x54, ++ 0x5A, 0x07, 0x90, 0xE4, 0x59, 0x07, 0x90, 0xF0, 0x07, 0x90, 0xED, 0xF0, 0x90, 0xEC, 0xF0, 0x5C, ++ 0x90, 0xF0, 0x5B, 0x07, 0x01, 0x74, 0x6C, 0x07, 0x47, 0x07, 0x90, 0xF0, 0xF0, 0x10, 0x44, 0xE0, ++ 0xC2, 0xEC, 0xD2, 0x22, 0x47, 0x07, 0x90, 0xED, 0xF0, 0xF7, 0x54, 0xE0, 0x09, 0x7C, 0xC4, 0x7D, ++ 0x8A, 0xB1, 0xFF, 0xE4, 0x78, 0xE6, 0x7B, 0x78, 0x76, 0x04, 0x60, 0x81, 0x76, 0x02, 0x80, 0x18, ++ 0x7E, 0x07, 0x7F, 0x13, 0x7F, 0xC7, 0xD1, 0x03, 0xB1, 0x0C, 0x7E, 0xB2, 0xB2, 0x07, 0x90, 0xFB, ++ 0xF0, 0x7F, 0x54, 0xE0, 0x75, 0x28, 0x13, 0x75, 0xCD, 0x22, 0xC8, 0x14, 0x07, 0x90, 0xCD, 0xEF, ++ 0xF7, 0x54, 0xE0, 0x47, 0x48, 0x07, 0x90, 0xF0, 0xF0, 0x08, 0x44, 0xE0, 0x56, 0x07, 0x90, 0xE4, ++ 0x55, 0x07, 0x90, 0xF0, 0x07, 0x90, 0xED, 0xF0, 0x90, 0xEE, 0xF0, 0x58, 0x90, 0xF0, 0x57, 0x07, ++ 0x01, 0x74, 0x6A, 0x07, 0x09, 0x90, 0x22, 0xF0, 0xF0, 0x01, 0x74, 0xD2, 0x04, 0xE5, 0x09, 0x90, ++ 0xD0, 0x09, 0x90, 0xF0, 0x09, 0x90, 0xF0, 0x14, 0xF0, 0x05, 0x74, 0xC1, 0x74, 0xB9, 0x09, 0x90, ++ 0x90, 0x22, 0xF0, 0x01, 0xFF, 0x74, 0x68, 0x07, 0x6C, 0x07, 0x90, 0xF0, 0x0C, 0xE3, 0x20, 0xE0, ++ 0xE0, 0x68, 0x07, 0x90, 0x78, 0x05, 0xE2, 0x30, 0x02, 0x70, 0xE6, 0x81, 0x07, 0x90, 0x8B, 0x61, ++ 0xE0, 0x30, 0xE0, 0x6C, 0xF0, 0x01, 0x74, 0x37, 0x90, 0x16, 0x81, 0x78, 0xC4, 0xE0, 0x0C, 0x0D, ++ 0x66, 0xF5, 0x0F, 0x54, 0x78, 0x0F, 0x54, 0xE0, 0x66, 0xE5, 0xF6, 0x87, 0x40, 0x01, 0x94, 0xD3, ++ 0x78, 0x66, 0x15, 0x02, 0x94, 0xD3, 0xE6, 0x87, 0x16, 0x01, 0x40, 0x01, 0x54, 0xC4, 0x66, 0xE5, ++ 0x46, 0x87, 0x78, 0xF0, 0x0D, 0x90, 0x66, 0xF5, 0xF0, 0x66, 0xE5, 0x8C, 0x47, 0x07, 0x90, 0x22, ++ 0xF0, 0xFB, 0x54, 0xE0, 0xE0, 0x48, 0x07, 0x90, 0xE4, 0xF0, 0x04, 0x44, 0xF0, 0x52, 0x07, 0x90, ++ 0xF0, 0x51, 0x07, 0x90, 0x74, 0x54, 0x07, 0x90, 0x07, 0x90, 0xF0, 0xA0, 0xF0, 0x0F, 0x74, 0x53, ++ 0x74, 0x68, 0x07, 0x90, 0xCD, 0x22, 0xF0, 0x01, 0x07, 0x90, 0xCD, 0xEF, 0xDF, 0x54, 0xE0, 0x47, ++ 0x48, 0x07, 0x90, 0xF0, 0xF0, 0x20, 0x44, 0xE0, 0x5E, 0x07, 0x90, 0xE4, 0x5D, 0x07, 0x90, 0xF0, ++ 0x07, 0x90, 0xED, 0xF0, 0x90, 0xEE, 0xF0, 0x60, 0x90, 0xF0, 0x5F, 0x07, 0x01, 0x74, 0x6E, 0x07, ++ 0x07, 0x90, 0x22, 0xF0, 0x13, 0xC4, 0xE0, 0xAE, 0xE0, 0x20, 0x07, 0x54, 0xAF, 0x07, 0x90, 0x15, ++ 0xF0, 0x02, 0x44, 0xE0, 0xE0, 0xB9, 0x09, 0x90, 0x90, 0xF0, 0x04, 0x44, 0x44, 0xE0, 0xAE, 0x07, ++ 0x07, 0x90, 0xF0, 0x20, 0x10, 0x44, 0xE0, 0xB0, 0xC0, 0x09, 0x90, 0xF0, 0x44, 0xF9, 0x54, 0xE0, ++ 0x07, 0x90, 0xF0, 0x04, 0xFD, 0x54, 0xE0, 0xAF, 0x07, 0x90, 0x22, 0xF0, 0x07, 0x90, 0xE0, 0xBE, ++ 0x13, 0xE3, 0x30, 0xB0, 0xF0, 0xFC, 0x54, 0xE0, 0xE0, 0x94, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, ++ 0x44, 0xE0, 0x14, 0x06, 0xE0, 0x22, 0xF0, 0x10, 0x01, 0x44, 0xFC, 0x54, 0x14, 0x06, 0x90, 0xF0, ++ 0xF0, 0xEF, 0x54, 0xE0, 0xF5, 0x09, 0x90, 0x22, 0xC3, 0x0F, 0x54, 0xE0, 0x0B, 0x50, 0x05, 0x94, ++ 0xF0, 0x54, 0xFF, 0xE0, 0x54, 0x04, 0xEF, 0xFE, 0x78, 0xF0, 0x4E, 0x0F, 0x09, 0x90, 0xE6, 0x7B, ++ 0x74, 0x05, 0x60, 0xF4, 0x03, 0x80, 0xF0, 0x09, 0x90, 0xF0, 0x01, 0x74, 0x54, 0xE0, 0xF5, 0x09, ++ 0x05, 0xBF, 0xFF, 0x0F, 0xBE, 0x09, 0x90, 0x26, 0x1F, 0xE0, 0x30, 0xE0, 0xE0, 0xC5, 0x09, 0x90, ++ 0x90, 0xF0, 0x02, 0x44, 0x09, 0x74, 0xBB, 0x09, 0xBE, 0x09, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, ++ 0x74, 0xC1, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x01, 0x22, 0xF0, 0x04, 0x9C, 0x00, 0x00, 0x00, 0x22, ++ 0x74, 0x61, 0x44, 0x09, 0x09, 0x00, 0x0A, 0x61, 0x44, 0x41, 0x42, 0x09, 0x47, 0x49, 0x53, 0x5F, ++ 0x09, 0x0A, 0x00, 0x0A, 0x4B, 0x4F, 0x4C, 0x09, 0x64, 0x25, 0x20, 0x3A, 0x09, 0x09, 0x00, 0x0A, ++ 0x3A, 0x4C, 0x56, 0x4C, 0x0A, 0x64, 0x25, 0x20, 0x50, 0x09, 0x09, 0x00, 0x20, 0x3A, 0x52, 0x57, ++ 0x0A, 0x20, 0x44, 0x25, 0x53, 0x09, 0x09, 0x00, 0x20, 0x3A, 0x52, 0x4E, 0x64, 0x20, 0x64, 0x25, ++ 0x09, 0x00, 0x0A, 0x42, 0x4F, 0x52, 0x46, 0x09, 0x44, 0x25, 0x20, 0x3A, 0x6D, 0x70, 0x70, 0x20, ++ 0x09, 0x09, 0x00, 0x0A, 0x3A, 0x51, 0x45, 0x4C, 0x44, 0x25, 0x20, 0x00, 0x09, 0x00, 0x0A, 0x00, ++ 0x45, 0x46, 0x44, 0x09, 0x09, 0x09, 0x00, 0x3A, 0x43, 0x53, 0x6F, 0x4C, 0x09, 0x00, 0x0A, 0x52, ++ 0x53, 0x6F, 0x4C, 0x09, 0x73, 0xE5, 0x00, 0x0A, 0x20, 0x7E, 0x3E, 0x60, 0x0E, 0x12, 0x00, 0x7F, ++ 0x7F, 0x78, 0xE4, 0x1D, 0x78, 0xF6, 0x08, 0xF6, 0x0C, 0x12, 0xF6, 0x7D, 0x24, 0x13, 0x75, 0xAE, ++ 0x75, 0x04, 0x14, 0x75, 0x12, 0x75, 0x25, 0x11, 0x0C, 0x10, 0x75, 0x57, 0xE0, 0x6D, 0x07, 0x90, ++ 0x90, 0xF0, 0x0C, 0x44, 0x08, 0x74, 0x6C, 0x07, 0x31, 0x06, 0x90, 0xF0, 0x54, 0x13, 0x13, 0xE0, ++ 0x04, 0xE0, 0x30, 0x3F, 0xEE, 0xD2, 0xEC, 0xD2, 0xE0, 0x97, 0x07, 0x90, 0x07, 0x90, 0x14, 0x60, ++ 0x01, 0x44, 0xE0, 0x95, 0x97, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x03, 0x74, 0x54, 0xE0, 0x95, 0x07, ++ 0x01, 0x90, 0xF0, 0xFE, 0x02, 0x44, 0xE0, 0xAE, 0x90, 0xFF, 0xE0, 0xF0, 0xC4, 0xE0, 0x91, 0x07, ++ 0x01, 0x54, 0x13, 0x13, 0x13, 0xC4, 0xEF, 0xFE, 0xEF, 0xFD, 0x01, 0x54, 0xED, 0xFF, 0xDF, 0x54, ++ 0xC4, 0x01, 0x54, 0x4E, 0x4F, 0xE0, 0x54, 0x33, 0xF0, 0xAE, 0x01, 0x90, 0x07, 0x90, 0xFF, 0xE0, ++ 0x13, 0xC4, 0xE0, 0x91, 0xEF, 0xFE, 0x01, 0x54, 0x54, 0x13, 0x13, 0x13, 0x54, 0xEF, 0xFD, 0x01, ++ 0x4E, 0xED, 0xFF, 0xF7, 0x33, 0x33, 0x01, 0x54, 0x4F, 0xF8, 0x54, 0x33, 0xF0, 0xAE, 0x01, 0x90, ++ 0x07, 0x90, 0xFF, 0xE0, 0x13, 0xC3, 0xE0, 0x91, 0xEF, 0xFE, 0x01, 0x54, 0xFD, 0x01, 0x54, 0xC4, ++ 0xFF, 0xEF, 0x54, 0xEF, 0x01, 0x54, 0x4E, 0xED, 0xF0, 0x54, 0xC4, 0xFE, 0xAE, 0x01, 0x90, 0x4F, ++ 0x91, 0x07, 0x90, 0xF0, 0x51, 0xF0, 0x62, 0x74, 0xF5, 0x33, 0xE4, 0x33, 0x60, 0x63, 0xE5, 0x63, ++ 0x7F, 0x20, 0x7E, 0x07, 0x1D, 0x0E, 0x12, 0x07, 0xC4, 0xEF, 0x20, 0xAF, 0xE0, 0x20, 0x0F, 0x54, ++ 0xEF, 0x20, 0xAF, 0x46, 0xAF, 0x40, 0xE0, 0x20, 0x13, 0xC3, 0xEF, 0x20, 0xAF, 0x38, 0xE0, 0x20, ++ 0x13, 0xC4, 0xEF, 0x20, 0xE0, 0x20, 0x07, 0x54, 0xEF, 0x20, 0xAF, 0x2E, 0x3F, 0x54, 0x13, 0x13, ++ 0xE5, 0x24, 0xE0, 0x20, 0x74, 0x20, 0x70, 0x63, 0x70, 0x12, 0x65, 0xFF, 0x65, 0x26, 0x74, 0x04, ++ 0x74, 0x14, 0x60, 0x11, 0x70, 0x12, 0x65, 0x57, 0x65, 0x25, 0x74, 0x04, 0x41, 0x02, 0x60, 0x11, ++ 0x40, 0xD5, 0x71, 0x32, 0xC2, 0x32, 0x41, 0x02, 0x90, 0xEE, 0xC2, 0xEC, 0x54, 0xE0, 0x47, 0x07, ++ 0x54, 0xE0, 0xF0, 0xFB, 0x07, 0x90, 0xF0, 0xEF, 0xF0, 0xFF, 0x74, 0x68, 0xF0, 0x6C, 0x07, 0x90, ++ 0xE0, 0x01, 0x0D, 0x90, 0x90, 0xF0, 0xDF, 0x54, 0x54, 0xE0, 0x21, 0x0D, 0x0D, 0x90, 0xF0, 0xDF, ++ 0xEF, 0x54, 0xE0, 0x01, 0x21, 0x0D, 0x90, 0xF0, 0xF0, 0xEF, 0x54, 0xE0, 0x74, 0x60, 0x08, 0x90, ++ 0x08, 0x90, 0xF0, 0x01, 0xF0, 0x0A, 0x74, 0x52, 0x74, 0x51, 0x08, 0x90, 0x06, 0x90, 0xF0, 0x02, ++ 0xFE, 0x54, 0xE0, 0x29, 0xB9, 0x01, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, ++ 0xE0, 0xAC, 0x07, 0x90, 0x90, 0xF0, 0xFE, 0x54, 0x44, 0xE0, 0x05, 0x08, 0x44, 0xE0, 0xF0, 0x01, ++ 0x07, 0x90, 0xF0, 0x10, 0xF0, 0x3C, 0x74, 0xAD, 0xE0, 0x03, 0x06, 0x90, 0x90, 0xF0, 0xFB, 0x54, ++ 0x44, 0xE0, 0x35, 0x06, 0x02, 0x7E, 0xF0, 0x01, 0x5F, 0x8E, 0x5B, 0x7F, 0x5B, 0x8E, 0x60, 0x8F, ++ 0x30, 0x22, 0x5C, 0x8F, 0xC8, 0x61, 0x02, 0x0B, 0xE6, 0x06, 0x80, 0x78, 0x06, 0x01, 0x70, 0x18, ++ 0x64, 0xE6, 0x80, 0x78, 0x60, 0x46, 0x18, 0x01, 0x90, 0x21, 0x61, 0x02, 0xF5, 0xE0, 0x64, 0x08, ++ 0x65, 0x08, 0x90, 0x23, 0xE5, 0x24, 0xF5, 0xE0, 0x78, 0x23, 0xAE, 0x24, 0xE7, 0xA2, 0xCE, 0x06, ++ 0xD8, 0x13, 0xCE, 0x13, 0x06, 0xAC, 0xFD, 0xF8, 0x23, 0xAE, 0x24, 0xE5, 0xA2, 0xCE, 0x05, 0x78, ++ 0x13, 0xCE, 0x13, 0xE7, 0xFF, 0x2D, 0xF8, 0xD8, 0xEF, 0xFE, 0x3C, 0xEE, 0x24, 0xF5, 0x24, 0x25, ++ 0xF5, 0x23, 0x35, 0xEE, 0x4E, 0x08, 0x90, 0x23, 0xED, 0x7D, 0xFF, 0xE0, 0x0B, 0x12, 0x21, 0x7C, ++ 0xAF, 0x25, 0x8F, 0xEC, 0x20, 0x06, 0x90, 0x24, 0x25, 0xE5, 0xF0, 0xEF, 0xAF, 0x0E, 0x94, 0xD3, ++ 0x7F, 0x02, 0x40, 0x25, 0x0F, 0x54, 0xEF, 0x0E, 0xFF, 0xF0, 0x54, 0xC4, 0xE0, 0x21, 0x06, 0x90, ++ 0xF0, 0x4F, 0x0F, 0x54, 0x34, 0x08, 0x90, 0xE4, 0x9F, 0x54, 0xE0, 0xF0, 0x90, 0xF0, 0x40, 0x44, ++ 0xF5, 0xE0, 0x37, 0x08, 0x7F, 0x20, 0x7E, 0x26, 0x08, 0x78, 0x78, 0x12, 0x86, 0x18, 0xE6, 0x06, ++ 0x06, 0x01, 0x70, 0x04, 0x0D, 0x12, 0xFD, 0x14, 0x7F, 0x20, 0x7E, 0x0D, 0xC0, 0x06, 0xC0, 0x1E, ++ 0xFE, 0x26, 0xE5, 0x07, 0xE0, 0x38, 0x08, 0x90, 0xED, 0xFC, 0xEE, 0xFD, 0x06, 0xD0, 0x07, 0xD0, ++ 0x7E, 0x0D, 0x0D, 0x12, 0x90, 0x29, 0x7F, 0x20, 0xFD, 0xE0, 0x4F, 0x08, 0x0D, 0x12, 0x00, 0x7C, ++ 0x7F, 0x20, 0x7E, 0x0D, 0x7C, 0x25, 0xAD, 0x35, 0x0D, 0x0D, 0x12, 0x00, 0x43, 0x7F, 0x20, 0x7E, ++ 0x23, 0xAC, 0x24, 0xAD, 0xE5, 0x0D, 0x0D, 0x12, 0x01, 0x94, 0xD3, 0x26, 0xC8, 0x61, 0x02, 0x40, ++ 0xE6, 0x80, 0x78, 0x22, 0x46, 0x18, 0x02, 0x64, 0x20, 0x7E, 0x47, 0x70, 0x0E, 0x12, 0x52, 0x7F, ++ 0x08, 0x90, 0xE4, 0x1D, 0x54, 0xE0, 0xF0, 0x34, 0xF5, 0xE4, 0xF0, 0x9F, 0x54, 0x22, 0xE5, 0x22, ++ 0x08, 0x90, 0xFF, 0x0F, 0xF0, 0x54, 0xE0, 0x34, 0x20, 0x7E, 0xF0, 0x4F, 0x06, 0xC0, 0x59, 0x7F, ++ 0x08, 0x90, 0x07, 0xC0, 0x90, 0xFE, 0xE0, 0x37, 0xFD, 0xE0, 0x38, 0x08, 0xD0, 0x06, 0xAC, 0xED, ++ 0x12, 0x06, 0xD0, 0x07, 0x22, 0x05, 0x0D, 0x0D, 0x94, 0xC3, 0x22, 0xE5, 0x80, 0xCE, 0x40, 0x0A, ++ 0xE6, 0x80, 0x78, 0x50, 0x46, 0x18, 0x03, 0x64, 0x20, 0x7E, 0x4E, 0x70, 0x0E, 0x12, 0x5F, 0x7F, ++ 0x08, 0x90, 0xE4, 0x1D, 0x54, 0xE0, 0xF0, 0x34, 0xF0, 0x20, 0x44, 0x9F, 0xE5, 0x22, 0xF5, 0xE4, ++ 0xFF, 0x0F, 0x54, 0x22, 0xE0, 0x34, 0x08, 0x90, 0xF0, 0x4F, 0xF0, 0x54, 0x59, 0x7F, 0x20, 0x7E, ++ 0x07, 0xC0, 0x06, 0xC0, 0xE0, 0x37, 0x08, 0x90, 0x38, 0x08, 0x90, 0xFE, 0xAC, 0xED, 0xFD, 0xE0, ++ 0xD0, 0x07, 0xD0, 0x06, 0x0D, 0x0D, 0x12, 0x06, 0x22, 0xE5, 0x22, 0x05, 0x40, 0x08, 0x94, 0xC3, ++ 0x7F, 0x20, 0x7E, 0xCE, 0x1D, 0x0E, 0x12, 0x5D, 0xE0, 0x4E, 0x08, 0x90, 0x40, 0x3C, 0x94, 0xD3, ++ 0xC3, 0x22, 0xD3, 0x02, 0xAA, 0x07, 0x90, 0x22, 0xA0, 0x94, 0xD3, 0xE0, 0x20, 0x7E, 0x06, 0x40, ++ 0x15, 0x80, 0x66, 0x7F, 0xE0, 0x4F, 0x08, 0x90, 0x50, 0x03, 0x94, 0xC3, 0xE6, 0x7D, 0x78, 0x11, ++ 0x40, 0x0A, 0x94, 0x06, 0x7F, 0x20, 0x7E, 0x0D, 0x1D, 0x0E, 0x12, 0x6F, 0x78, 0xE4, 0x22, 0xD3, ++ 0x22, 0xC3, 0xF6, 0x7D, 0x74, 0x68, 0x07, 0x90, 0x30, 0xE0, 0xF0, 0xFF, 0x07, 0x90, 0x21, 0xE2, ++ 0x01, 0x44, 0xE0, 0xAC, 0x90, 0x30, 0x91, 0xF0, 0x44, 0xE0, 0x47, 0x07, 0x01, 0x90, 0xF0, 0x04, ++ 0x08, 0x44, 0xE0, 0xB9, 0x02, 0x44, 0xE0, 0xF0, 0x24, 0x13, 0x75, 0xF0, 0x22, 0x85, 0x14, 0x75, ++ 0xC3, 0x7C, 0x50, 0x7D, 0x07, 0x90, 0x01, 0x7F, 0xFB, 0x54, 0xE0, 0x47, 0x01, 0x54, 0xEF, 0xF0, ++ 0xE0, 0x25, 0xE0, 0x25, 0x48, 0x07, 0x90, 0xFF, 0x4F, 0xFB, 0x54, 0xE0, 0x07, 0x90, 0xE4, 0xF0, ++ 0x07, 0x90, 0xF0, 0x52, 0x90, 0xED, 0xF0, 0x51, 0xEC, 0xF0, 0x54, 0x07, 0xF0, 0x53, 0x07, 0x90, ++ 0x74, 0x68, 0x07, 0x90, 0x90, 0x22, 0xF0, 0x01, 0xF5, 0xE0, 0x45, 0x08, 0x7D, 0xF0, 0xE4, 0x65, ++ 0x7F, 0x04, 0x7C, 0xE2, 0x90, 0x36, 0x91, 0x01, 0x44, 0xE0, 0x47, 0x07, 0x13, 0x75, 0xF0, 0x04, ++ 0x0C, 0x14, 0x75, 0x25, 0x68, 0x07, 0x90, 0x22, 0xE0, 0xF0, 0x02, 0x74, 0x90, 0x0F, 0xE2, 0x20, ++ 0x54, 0xE0, 0x47, 0x07, 0x07, 0x90, 0xF0, 0xFB, 0xF0, 0x01, 0x74, 0x68, 0x07, 0x90, 0x0D, 0x80, ++ 0xE0, 0x30, 0xE0, 0x68, 0xF0, 0x01, 0x74, 0x05, 0x91, 0x22, 0x67, 0x91, 0xAC, 0x07, 0x90, 0xFE, ++ 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0xB9, 0x01, 0x90, 0x90, 0xF0, 0xFD, 0x54, 0x54, 0xE0, 0x47, 0x07, ++ 0x07, 0x90, 0xF0, 0xFB, 0xF0, 0x01, 0x74, 0x68, 0x75, 0x24, 0x13, 0x75, 0x90, 0x22, 0x04, 0x14, ++ 0x02, 0x74, 0x68, 0x07, 0xE2, 0x20, 0xE0, 0xF0, 0x90, 0xD0, 0x80, 0x02, 0x30, 0xE0, 0x68, 0x07, ++ 0x01, 0x74, 0x1B, 0xE0, 0x15, 0x64, 0xAF, 0xF0, 0x11, 0x70, 0xEF, 0x64, 0x30, 0x91, 0xFE, 0x91, ++ 0xE0, 0x47, 0x07, 0x90, 0x75, 0xF0, 0x04, 0x44, 0x14, 0x75, 0x24, 0x13, 0x08, 0x90, 0x22, 0x85, ++ 0xF0, 0x0A, 0x74, 0x52, 0xE0, 0x05, 0x08, 0x90, 0x22, 0xF0, 0x01, 0x44, 0x74, 0x68, 0x07, 0x90, ++ 0x20, 0xE0, 0xF0, 0x02, 0x08, 0x90, 0x08, 0xE2, 0xF0, 0x65, 0xE5, 0x45, 0x07, 0x90, 0x8D, 0x80, ++ 0xE0, 0x30, 0xE0, 0x68, 0xF0, 0x01, 0x74, 0x05, 0x90, 0x22, 0x2B, 0xB1, 0x08, 0x74, 0x52, 0x08, ++ 0x05, 0x08, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0x90, 0x50, 0x64, 0x75, 0x65, 0xE5, 0x45, 0x08, ++ 0x7C, 0x24, 0x7D, 0xF0, 0x91, 0xFF, 0xE4, 0xF4, 0x47, 0x07, 0x90, 0x36, 0xF0, 0x04, 0x44, 0xE0, ++ 0x75, 0x24, 0x13, 0x75, 0x90, 0x22, 0xCF, 0x14, 0xF5, 0xE0, 0x6C, 0x07, 0xF0, 0x68, 0xE5, 0x68, ++ 0xE0, 0xAA, 0x07, 0x90, 0x40, 0xA0, 0x94, 0xD3, 0xC1, 0xFF, 0xD1, 0x04, 0x20, 0x68, 0xE5, 0x44, ++ 0x44, 0xC1, 0x02, 0xE1, 0xE0, 0xA9, 0x07, 0x90, 0x54, 0x13, 0x13, 0x13, 0x03, 0xBF, 0xFF, 0x03, ++ 0xA8, 0x07, 0x90, 0x0D, 0xF0, 0x08, 0x44, 0xE0, 0xF0, 0xF7, 0x54, 0xE0, 0x07, 0x90, 0x44, 0xC1, ++ 0x13, 0x13, 0xE0, 0xA9, 0x64, 0x03, 0x54, 0x13, 0xC1, 0x02, 0x60, 0x01, 0x06, 0x67, 0x75, 0x2C, ++ 0x09, 0x7C, 0xC4, 0x7D, 0x90, 0x99, 0xD1, 0xFF, 0x44, 0xE0, 0x47, 0x07, 0x07, 0x90, 0xF0, 0x10, ++ 0x01, 0x44, 0xE0, 0x90, 0xB9, 0x01, 0x90, 0xF0, 0xF0, 0x04, 0x44, 0xE0, 0xF0, 0x01, 0x44, 0xE0, ++ 0xE0, 0x47, 0x08, 0x90, 0x90, 0xF0, 0xFE, 0x54, 0x54, 0xE0, 0xF6, 0x01, 0x08, 0x90, 0xFF, 0x70, ++ 0x8F, 0x54, 0xE0, 0x4B, 0x01, 0x90, 0xF0, 0x4F, 0x0C, 0x54, 0xE0, 0xF6, 0x4A, 0x08, 0x90, 0xFF, ++ 0x4F, 0xF3, 0x54, 0xE0, 0xF6, 0x01, 0x90, 0xF0, 0x4C, 0x08, 0x90, 0xE0, 0xE0, 0x06, 0xE0, 0x30, ++ 0x80, 0xF0, 0x0F, 0x54, 0x0F, 0x54, 0xE0, 0x06, 0x90, 0xF0, 0x20, 0x44, 0x90, 0xE0, 0xF6, 0x01, ++ 0xE1, 0x30, 0x48, 0x08, 0xF3, 0x54, 0xE0, 0x08, 0x80, 0xF0, 0x08, 0x44, 0xF3, 0x54, 0xE0, 0x06, ++ 0x90, 0xF0, 0x04, 0x44, 0x54, 0xE0, 0x6D, 0x07, 0x07, 0x90, 0xF0, 0xFB, 0xF0, 0x08, 0x74, 0x6C, ++ 0xE0, 0xF3, 0x01, 0x90, 0xF0, 0xAD, 0x07, 0x90, 0x18, 0x80, 0x5D, 0xD1, 0xE0, 0xA9, 0x07, 0x90, ++ 0x54, 0x13, 0x13, 0x13, 0x02, 0xBF, 0xFF, 0x03, 0xAC, 0x07, 0x90, 0x0B, 0xF0, 0x10, 0x44, 0xE0, ++ 0xF0, 0xEF, 0x54, 0xE0, 0xE0, 0x30, 0x68, 0xE5, 0x90, 0xC9, 0xD1, 0x13, 0x54, 0xE0, 0x61, 0x08, ++ 0x07, 0xBF, 0xFF, 0x0F, 0x47, 0x07, 0x90, 0x07, 0xF0, 0xEF, 0x54, 0xE0, 0x47, 0x08, 0x90, 0x22, ++ 0xF0, 0x40, 0x44, 0xE0, 0xF0, 0x7F, 0x54, 0xE0, 0x74, 0x6C, 0x07, 0x90, 0x01, 0x90, 0xF0, 0x08, ++ 0x08, 0x90, 0xE0, 0xF4, 0x66, 0x75, 0xF0, 0x6C, 0x27, 0x11, 0x75, 0x18, 0x90, 0xE2, 0x12, 0x75, ++ 0xFF, 0xE0, 0xA9, 0x07, 0x54, 0x13, 0x13, 0x13, 0xE0, 0x0A, 0x60, 0x03, 0x54, 0x13, 0x13, 0x13, ++ 0x02, 0xBF, 0xFF, 0x03, 0xC0, 0x29, 0x12, 0x03, 0x47, 0x07, 0x90, 0x22, 0xF0, 0xEF, 0x54, 0xE0, ++ 0xC4, 0x01, 0x54, 0xEF, 0x90, 0xFF, 0xF0, 0x54, 0x54, 0xE0, 0x48, 0x07, 0xE4, 0xF0, 0x4F, 0xEF, ++ 0xF0, 0x5A, 0x07, 0x90, 0xF0, 0x59, 0x07, 0x90, 0x5C, 0x07, 0x90, 0xED, 0x07, 0x90, 0xEC, 0xF0, ++ 0x07, 0x90, 0xF0, 0x5B, 0xF0, 0x01, 0x74, 0x6C, 0x60, 0x08, 0x90, 0x22, 0x90, 0xF0, 0x01, 0x74, ++ 0x54, 0xE0, 0x61, 0x08, 0x07, 0x94, 0xC3, 0x0F, 0xFF, 0xE0, 0x0B, 0x50, 0xEF, 0xFE, 0xF0, 0x54, ++ 0x4E, 0x0F, 0x54, 0x04, 0x61, 0x08, 0x90, 0xF0, 0xC3, 0x0F, 0x54, 0xE0, 0x0E, 0x40, 0x06, 0x94, ++ 0xE0, 0x2A, 0x08, 0x90, 0x90, 0xF0, 0xFE, 0x54, 0x54, 0xE0, 0x2D, 0x08, 0x75, 0x22, 0xF0, 0xFB, ++ 0x12, 0x75, 0x26, 0x11, 0x05, 0x08, 0x90, 0xFF, 0xF0, 0x01, 0x44, 0xE0, 0xF0, 0x10, 0x44, 0xE0, ++ 0xE0, 0xEA, 0x01, 0x90, 0xA3, 0x03, 0x70, 0xF4, 0x0E, 0x60, 0xF4, 0xE0, 0xE0, 0xEB, 0x01, 0x90, ++ 0x06, 0x70, 0xF0, 0x04, 0xE0, 0xEA, 0x01, 0x90, 0xEC, 0xC2, 0xF0, 0x04, 0x07, 0x90, 0xEE, 0xC2, ++ 0xF0, 0xFF, 0x74, 0x68, 0xF0, 0x6C, 0x07, 0x90, 0xE0, 0x48, 0x08, 0x90, 0x04, 0x44, 0xF3, 0x54, ++ 0x4C, 0x08, 0x90, 0xF0, 0x44, 0x0F, 0x54, 0xE0, 0x08, 0x90, 0xF0, 0x20, 0xF3, 0x54, 0xE0, 0x4A, ++ 0x4B, 0x08, 0x90, 0xF0, 0xF0, 0x70, 0x44, 0xE0, 0xE0, 0x47, 0x08, 0x90, 0x22, 0xF0, 0x01, 0x44, ++ 0xE0, 0x6C, 0x07, 0x90, 0x15, 0x26, 0xE0, 0x30, 0xF0, 0x01, 0x74, 0x66, 0x1D, 0x70, 0x66, 0xE5, ++ 0xB2, 0x01, 0x90, 0xC3, 0x90, 0xFF, 0x94, 0xE0, 0x94, 0xE0, 0xB1, 0x01, 0xA3, 0x0C, 0x50, 0xFF, ++ 0x70, 0xF0, 0x04, 0xE0, 0xB1, 0x01, 0x90, 0x06, 0xC1, 0xF0, 0x04, 0xE0, 0x14, 0x69, 0xE5, 0xFF, ++ 0x60, 0x14, 0x4D, 0x60, 0x70, 0x02, 0x24, 0x4A, 0x3D, 0x08, 0x90, 0x11, 0x44, 0xE0, 0x54, 0xE0, ++ 0x08, 0x90, 0xF0, 0x05, 0xF0, 0x01, 0x74, 0x2F, 0x07, 0x90, 0x35, 0x80, 0xF0, 0x0B, 0x74, 0x6C, ++ 0x06, 0x24, 0x66, 0xE5, 0x08, 0x90, 0x67, 0xF5, 0xF0, 0x28, 0x74, 0x06, 0xB2, 0x01, 0x90, 0xC3, ++ 0x90, 0xFF, 0x94, 0xE0, 0x94, 0xE0, 0xB1, 0x01, 0xE5, 0x12, 0x50, 0xFF, 0x50, 0x08, 0x94, 0x66, ++ 0x04, 0xE0, 0xA3, 0x0C, 0x90, 0x06, 0x70, 0xF0, 0x04, 0xE0, 0xB1, 0x01, 0x05, 0x5D, 0xD1, 0xF0, ++ 0x07, 0x90, 0x22, 0x69, 0xF0, 0x02, 0x74, 0x6C, 0x21, 0xE3, 0x30, 0xE0, 0xE0, 0x2A, 0x08, 0x90, ++ 0x90, 0xF0, 0x01, 0x44, 0x44, 0xE0, 0x2D, 0x08, 0x08, 0x90, 0xF0, 0x04, 0xF0, 0x15, 0x74, 0x60, ++ 0x07, 0x90, 0x73, 0x11, 0xE3, 0x30, 0xE0, 0x6C, 0x80, 0x2E, 0x31, 0x36, 0xA9, 0x07, 0x90, 0x32, ++ 0x13, 0x13, 0x13, 0xE0, 0xBF, 0xFF, 0x03, 0x54, 0x07, 0x90, 0x0D, 0x03, 0x08, 0x44, 0xE0, 0xA8, ++ 0xF7, 0x54, 0xE0, 0xF0, 0x90, 0x18, 0x80, 0xF0, 0xFF, 0xE0, 0xA9, 0x07, 0x54, 0x13, 0x13, 0x13, ++ 0xE0, 0x0A, 0x60, 0x03, 0x54, 0x13, 0x13, 0x13, 0x02, 0xBF, 0xFF, 0x03, 0x90, 0xC0, 0x31, 0x02, ++ 0x30, 0xE0, 0x6C, 0x07, 0x66, 0x15, 0x2C, 0xE0, 0xE5, 0xF0, 0x01, 0x74, 0x67, 0x95, 0xD3, 0x66, ++ 0x26, 0x12, 0x05, 0x40, 0x90, 0x14, 0x80, 0xC9, 0x44, 0xE0, 0x2A, 0x08, 0x08, 0x90, 0xF0, 0x01, ++ 0x04, 0x44, 0xE0, 0x2D, 0x60, 0x08, 0x90, 0xF0, 0xE5, 0xF0, 0x15, 0x74, 0x12, 0x03, 0x70, 0x66, ++ 0x90, 0x22, 0xFF, 0x26, 0x44, 0xE0, 0x47, 0x08, 0x08, 0x90, 0xF0, 0x80, 0xF0, 0x0F, 0x74, 0x27, ++ 0x74, 0x2F, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x03, 0xF0, 0x07, 0x74, 0x2D, 0x74, 0x25, 0x08, 0x90, ++ 0x01, 0x90, 0xF0, 0x03, 0x01, 0x54, 0xE0, 0xF2, 0xFF, 0xF0, 0x54, 0xC4, 0xE0, 0x05, 0x08, 0x90, ++ 0xF0, 0x4F, 0xEF, 0x54, 0x74, 0x25, 0x08, 0x90, 0x08, 0x90, 0xF0, 0x01, 0xF0, 0x05, 0x74, 0x2D, ++ 0x74, 0x27, 0x08, 0x90, 0x66, 0x75, 0xF0, 0x0F, 0x7C, 0x24, 0x7D, 0x60, 0x12, 0xFF, 0xE4, 0xF4, ++ 0x07, 0x90, 0x99, 0x26, 0x10, 0x44, 0xE0, 0x47, 0xA8, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x2A, 0x74, ++ 0x08, 0x74, 0x6C, 0x07, 0x29, 0x11, 0x75, 0xF0, 0x22, 0x99, 0x12, 0x75, 0xE0, 0x6C, 0x07, 0x90, ++ 0xE4, 0x37, 0xE3, 0x30, 0xF0, 0x07, 0x08, 0x90, 0xE0, 0x49, 0x08, 0x90, 0x73, 0x11, 0x07, 0x60, ++ 0x80, 0x66, 0x69, 0x85, 0xF5, 0x01, 0x90, 0x1D, 0x6C, 0x08, 0x90, 0xE0, 0x67, 0x08, 0x90, 0xF0, ++ 0x90, 0xF0, 0x05, 0x74, 0x01, 0x74, 0x60, 0x08, 0x69, 0xF5, 0xE4, 0xF0, 0x75, 0x27, 0x11, 0x75, ++ 0x07, 0x90, 0x60, 0x12, 0xF7, 0x54, 0xE0, 0x6D, 0x07, 0x90, 0x22, 0xF0, 0xE0, 0x30, 0xE0, 0x6C, ++ 0x74, 0x66, 0x15, 0x0C, 0x66, 0xE5, 0xF0, 0x01, 0x26, 0x12, 0x03, 0x70, 0x66, 0x75, 0x22, 0xFF, ++ 0x7C, 0xC4, 0x7D, 0x0A, 0x12, 0xFF, 0xE4, 0x09, 0x07, 0x90, 0x99, 0x26, 0x10, 0x44, 0xE0, 0x47, ++ 0x47, 0x08, 0x90, 0xF0, 0xF0, 0x7F, 0x54, 0xE0, 0x74, 0x49, 0x08, 0x90, 0x07, 0x90, 0xF0, 0x01, ++ 0xF0, 0x09, 0x74, 0x6C, 0xE0, 0x05, 0x08, 0x90, 0x90, 0xF0, 0x10, 0x44, 0x0D, 0x74, 0x27, 0x08, ++ 0x61, 0x08, 0x90, 0xF0, 0x44, 0xF0, 0x54, 0xE0, 0x01, 0x90, 0xF0, 0x02, 0xF0, 0x54, 0xE0, 0xF2, ++ 0xFF, 0x0F, 0x54, 0xC4, 0xE0, 0x3D, 0x08, 0x90, 0xF0, 0x4F, 0xE0, 0x54, 0x06, 0x08, 0x90, 0xE4, ++ 0x07, 0x08, 0x90, 0xF0, 0x07, 0x90, 0xF0, 0x04, 0xF7, 0x54, 0xE0, 0x6D, 0x07, 0x90, 0xE4, 0xF0, ++ 0x11, 0x75, 0xF0, 0xA8, 0xDC, 0x12, 0x75, 0x28, 0x6C, 0x07, 0x90, 0x22, 0xE0, 0xF0, 0x02, 0x74, ++ 0x74, 0x0C, 0xE3, 0x30, 0x30, 0xE0, 0xF0, 0x08, 0x66, 0x85, 0x15, 0xE3, 0x90, 0x2E, 0x21, 0x69, ++ 0x30, 0xE0, 0x6C, 0x07, 0x01, 0x74, 0x09, 0xE0, 0x03, 0x66, 0xD5, 0xF0, 0x22, 0xFF, 0x26, 0x12, ++ 0xE0, 0xAC, 0x07, 0x90, 0x90, 0xF0, 0x10, 0x44, 0x54, 0xE0, 0x90, 0x07, 0x90, 0xE4, 0xF0, 0xFE, ++ 0x90, 0xF0, 0x99, 0x07, 0x54, 0xE0, 0xB9, 0x01, 0x08, 0x90, 0xF0, 0xFE, 0xF0, 0x01, 0x74, 0x60, ++ 0xE0, 0x6D, 0x07, 0x90, 0x90, 0xF0, 0x04, 0x44, 0x44, 0xE0, 0x47, 0x08, 0x44, 0xE0, 0xF0, 0x40, ++ 0x08, 0x90, 0xF0, 0x80, 0xF3, 0x54, 0xE0, 0x48, 0x90, 0xF0, 0x04, 0x44, 0x54, 0xE0, 0x4C, 0x08, ++ 0xF0, 0x20, 0x44, 0x0F, 0xE0, 0x4A, 0x08, 0x90, 0x90, 0xF0, 0xF3, 0x54, 0x44, 0xE0, 0x4B, 0x08, ++ 0x08, 0x90, 0xF0, 0x70, 0x01, 0x44, 0xE0, 0x47, 0x6C, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x09, 0x74, ++ 0x54, 0xE0, 0xAC, 0x07, 0x07, 0x90, 0xF0, 0xEF, 0xF0, 0x3C, 0x74, 0xAD, 0x75, 0x25, 0x11, 0x75, ++ 0x22, 0x22, 0x57, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x07, 0x7F, 0x20, 0x7E, 0x09, 0x1D, 0x0E, 0x02, 0x62, 0x30, 0x30, 0x31, 0x58, 0x65, 0x73, 0x61, ++ 0x0A, 0x53, 0x4E, 0x20, 0x90, 0x22, 0x8F, 0x00, 0x20, 0x74, 0x00, 0x0D, 0x7E, 0x00, 0x7F, 0xF0, ++ 0xCE, 0x0B, 0x12, 0x0D, 0x01, 0x0D, 0x90, 0xE4, 0x7E, 0x01, 0x7F, 0xF0, 0xCE, 0x0B, 0x12, 0x0D, ++ 0x07, 0x76, 0x7C, 0x78, 0x08, 0x07, 0x76, 0x08, 0x76, 0x08, 0x07, 0x76, 0x00, 0x0D, 0x90, 0x07, ++ 0xF0, 0x07, 0x44, 0xE0, 0xE0, 0x20, 0x0D, 0x90, 0x90, 0xF0, 0x07, 0x44, 0x44, 0xE0, 0x40, 0x0D, ++ 0x0D, 0x90, 0xF0, 0x07, 0x07, 0x44, 0xE0, 0x60, 0xA2, 0x0D, 0x90, 0xF0, 0x90, 0xF0, 0xAA, 0x74, ++ 0x35, 0x74, 0x0C, 0x0D, 0x7E, 0x0C, 0x7F, 0xF0, 0xCE, 0x0B, 0x12, 0x0D, 0xE0, 0x29, 0x06, 0x90, ++ 0x13, 0x13, 0x13, 0xFF, 0x60, 0x14, 0x03, 0x54, 0x3D, 0x60, 0x14, 0x25, 0x24, 0x55, 0x60, 0x14, ++ 0x90, 0x79, 0x70, 0x03, 0x9C, 0x74, 0x06, 0x0D, 0x7E, 0x06, 0x7F, 0xF0, 0xCE, 0x0B, 0x12, 0x0D, ++ 0x74, 0x0A, 0x0D, 0x90, 0xC9, 0x0B, 0x12, 0x89, 0x7C, 0x7F, 0x03, 0x7E, 0x0D, 0x90, 0x4F, 0x80, ++ 0xF0, 0xAC, 0x74, 0x06, 0x0D, 0x7E, 0x06, 0x7F, 0x90, 0xCE, 0x0B, 0x12, 0x99, 0x74, 0x0A, 0x0D, ++ 0x7E, 0xC9, 0x0B, 0x12, 0x80, 0x89, 0x7F, 0x03, 0x06, 0x0D, 0x90, 0x34, 0x7F, 0xF0, 0x8C, 0x74, ++ 0x12, 0x0D, 0x7E, 0x06, 0x0D, 0x90, 0xCE, 0x0B, 0x12, 0x79, 0x74, 0x0A, 0x03, 0x7E, 0xC9, 0x0B, ++ 0x19, 0x80, 0x96, 0x7F, 0x74, 0x06, 0x0D, 0x90, 0x06, 0x7F, 0xF0, 0x7C, 0x0B, 0x12, 0x0D, 0x7E, ++ 0x0A, 0x0D, 0x90, 0xCE, 0x0B, 0x12, 0x69, 0x74, 0x7F, 0x03, 0x7E, 0xC9, 0x29, 0x06, 0x90, 0xA3, ++ 0x13, 0x13, 0x13, 0xE0, 0x7C, 0xFD, 0x03, 0x54, 0x0D, 0x0D, 0x12, 0x00, 0x07, 0x90, 0x32, 0x71, ++ 0x01, 0x44, 0xE0, 0xFD, 0x02, 0x44, 0xE0, 0xF0, 0xFD, 0x54, 0xE0, 0xF0, 0x70, 0x22, 0xE5, 0xF0, ++ 0x26, 0x06, 0x90, 0x0D, 0x54, 0x13, 0xC4, 0xE0, 0x03, 0x94, 0xC3, 0x07, 0x08, 0x90, 0x0C, 0x40, ++ 0xF0, 0x44, 0x74, 0x03, 0xF0, 0x04, 0x08, 0x90, 0x08, 0x90, 0x0C, 0x80, 0xF0, 0x10, 0x74, 0x03, ++ 0x74, 0x04, 0x08, 0x90, 0x90, 0xE4, 0xF0, 0x32, 0x90, 0xF0, 0xFE, 0x09, 0x90, 0xF0, 0xFD, 0x09, ++ 0x90, 0xF0, 0xFC, 0x09, 0x90, 0xF0, 0x0B, 0x0A, 0x90, 0xF0, 0x0A, 0x0A, 0x90, 0xF0, 0x09, 0x0A, ++ 0xF0, 0x04, 0xFF, 0x09, 0xF0, 0x0C, 0x0A, 0x90, 0x74, 0xFB, 0x09, 0x90, 0x0A, 0x90, 0xF0, 0x03, ++ 0x09, 0x90, 0xF0, 0x08, 0xF0, 0x01, 0x74, 0xFB, 0xF0, 0x08, 0x0A, 0x90, 0x74, 0xF4, 0x09, 0x90, ++ 0x0A, 0x90, 0xF0, 0x03, 0x06, 0x90, 0xF0, 0x01, 0x13, 0xC4, 0xE0, 0x26, 0x03, 0x64, 0x07, 0x54, ++ 0x60, 0xF4, 0x09, 0x90, 0xF0, 0x01, 0x74, 0x05, 0x09, 0x74, 0x03, 0x80, 0xE6, 0x09, 0x90, 0xF0, ++ 0x90, 0xF0, 0x0B, 0x74, 0x03, 0x74, 0xE5, 0x09, 0xE6, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x0A, 0x74, ++ 0x02, 0x74, 0xE5, 0x09, 0xCD, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x04, 0x74, 0xF0, 0x14, 0xD4, 0x09, ++ 0x74, 0xD5, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x01, 0xF0, 0x05, 0x74, 0xD6, 0x74, 0xD7, 0x09, 0x90, ++ 0x01, 0x74, 0xF0, 0x03, 0x60, 0x22, 0xE5, 0xF0, 0xA8, 0x00, 0x90, 0x22, 0x45, 0x08, 0x90, 0xE0, ++ 0xA9, 0x00, 0x90, 0xF0, 0xAA, 0x08, 0x90, 0xE0, 0xAA, 0x00, 0x90, 0xF0, 0x0F, 0x09, 0x90, 0xE0, ++ 0xAB, 0x00, 0x90, 0xF0, 0x74, 0x09, 0x90, 0xE0, 0xE4, 0x05, 0x80, 0xF0, 0xF0, 0xD9, 0x09, 0x90, ++ 0x74, 0xD2, 0x09, 0x90, 0x01, 0x74, 0xF0, 0x03, 0xD1, 0x09, 0x90, 0xF0, 0x90, 0xF0, 0x05, 0x74, ++ 0x03, 0x74, 0xD0, 0x09, 0xF0, 0x01, 0x74, 0xF0, 0x74, 0xDB, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x0F, ++ 0xF0, 0x05, 0x74, 0xDC, 0x74, 0xE0, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x14, 0xF0, 0xEE, 0x74, 0xDF, ++ 0x74, 0xDE, 0x09, 0x90, 0x09, 0x90, 0xF0, 0x01, 0xF0, 0x03, 0x74, 0xDB, 0x04, 0x60, 0x22, 0xE5, ++ 0x02, 0x80, 0x01, 0x7F, 0x02, 0x12, 0x02, 0x7F, 0x26, 0x06, 0x90, 0x65, 0x54, 0x13, 0xC4, 0xE0, ++ 0x03, 0x94, 0xC3, 0x07, 0x07, 0x90, 0x08, 0x40, 0xFB, 0x54, 0xE0, 0xB0, 0x22, 0xE5, 0x14, 0x80, ++ 0x60, 0xB0, 0x07, 0x90, 0xFB, 0x54, 0xE0, 0x0A, 0x08, 0x44, 0xE0, 0xF0, 0xE0, 0x08, 0x80, 0xF0, ++ 0xE0, 0xF0, 0x04, 0x44, 0x90, 0xF0, 0xF7, 0x54, 0xFF, 0x74, 0xAF, 0x07, 0xAE, 0x07, 0x90, 0xF0, ++ 0xAF, 0x07, 0x90, 0xF0, 0x90, 0xF0, 0x02, 0x74, 0xAA, 0x74, 0xB8, 0x07, 0xB6, 0x07, 0x90, 0xF0, ++ 0xF0, 0x02, 0x44, 0xE0, 0xE0, 0xB7, 0x07, 0x90, 0xE0, 0xF0, 0x02, 0x44, 0x90, 0xF0, 0xFD, 0x54, ++ 0x54, 0xE0, 0xB0, 0x07, 0xF0, 0x01, 0x44, 0xFC, 0xE0, 0x95, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, ++ 0x44, 0xE0, 0x94, 0x07, 0x07, 0x90, 0xF0, 0x01, 0xF8, 0x54, 0xE0, 0x96, 0x90, 0xF0, 0x03, 0x44, ++ 0x03, 0x74, 0x97, 0x07, 0x94, 0x07, 0x90, 0xF0, 0xF0, 0xFE, 0x54, 0xE0, 0xE0, 0x95, 0x07, 0x90, ++ 0x90, 0xF0, 0xFE, 0x54, 0x44, 0xE0, 0x99, 0x07, 0x07, 0x90, 0xF0, 0x01, 0x01, 0x44, 0xE0, 0x98, ++ 0x9A, 0x07, 0x90, 0xF0, 0x44, 0xF8, 0x54, 0xE0, 0x07, 0x90, 0xF0, 0x03, 0xF0, 0x03, 0x74, 0x9B, ++ 0xE0, 0x98, 0x07, 0x90, 0x90, 0xF0, 0xFE, 0x54, 0x54, 0xE0, 0x99, 0x07, 0x07, 0x90, 0xF0, 0xFE, ++ 0xF0, 0x0D, 0x74, 0xFB, 0xE0, 0x26, 0x06, 0x90, 0x07, 0x54, 0x13, 0xC4, 0x1D, 0x60, 0xFE, 0x24, ++ 0x90, 0x22, 0x70, 0x04, 0x03, 0x74, 0x7F, 0x07, 0x9A, 0x07, 0x90, 0xF0, 0x44, 0xF8, 0x54, 0xE0, ++ 0x07, 0x90, 0xF0, 0x02, 0xF8, 0x54, 0xE0, 0x96, 0x80, 0xF0, 0x03, 0x44, 0x7F, 0x07, 0x90, 0x0D, ++ 0x80, 0xF0, 0x01, 0x74, 0x07, 0x90, 0xE4, 0x05, 0x07, 0x90, 0xF0, 0x7F, 0x10, 0x44, 0xE0, 0x07, ++ 0x90, 0xE4, 0x22, 0xF0, 0x90, 0xF0, 0xF9, 0x07, 0x30, 0xE0, 0x27, 0x06, 0x06, 0x90, 0x13, 0xE0, ++ 0xA3, 0xFE, 0xE0, 0x22, 0xCE, 0x02, 0x78, 0xE0, 0x13, 0xCE, 0x13, 0xC3, 0xE0, 0x30, 0xF9, 0xD8, ++ 0x27, 0x06, 0x90, 0x1A, 0x1C, 0xE0, 0x20, 0xE0, 0xE0, 0x26, 0x06, 0x90, 0x78, 0xE0, 0xA3, 0xFE, ++ 0x13, 0xC3, 0xCE, 0x02, 0xF9, 0xD8, 0x13, 0xCE, 0x90, 0x09, 0xE0, 0x20, 0x44, 0xE0, 0xF9, 0x07, ++ 0x13, 0x80, 0xF0, 0x04, 0xE0, 0xF9, 0x07, 0x90, 0x90, 0xF0, 0x01, 0x44, 0xF4, 0xE0, 0xA8, 0x00, ++ 0xE0, 0xA3, 0xF0, 0x04, 0x90, 0xF0, 0x04, 0xF4, 0x30, 0xE0, 0x27, 0x06, 0x06, 0x90, 0x13, 0xE0, ++ 0xA3, 0xFE, 0xE0, 0x22, 0xCE, 0x02, 0x78, 0xE0, 0x13, 0xCE, 0x13, 0xC3, 0xE0, 0x30, 0xF9, 0xD8, ++ 0x27, 0x06, 0x90, 0x1A, 0x1C, 0xE0, 0x20, 0xE0, 0xE0, 0x26, 0x06, 0x90, 0x78, 0xE0, 0xA3, 0xFE, ++ 0x13, 0xC3, 0xCE, 0x03, 0xF9, 0xD8, 0x13, 0xCE, 0x90, 0x09, 0xE0, 0x20, 0x44, 0xE0, 0xF9, 0x07, ++ 0x13, 0x80, 0xF0, 0xE0, 0xE0, 0xF9, 0x07, 0x90, 0x90, 0xF0, 0xB0, 0x44, 0xF4, 0xE0, 0xAA, 0x00, ++ 0xE0, 0xA3, 0xF0, 0x04, 0x90, 0xF0, 0x04, 0xF4, 0x90, 0xE0, 0xF9, 0x07, 0x22, 0xF0, 0xFA, 0x07, ++ 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x30, 0x30, 0x31, 0x09, 0x65, 0x73, 0x61, 0x62, 0x20, 0x31, 0x54, 0x2D, 0x00, 0x0A, 0x53, 0x4E, ++ 0x00, 0x7F, 0x20, 0x7E, 0x22, 0x1D, 0x0E, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x50, 0x7E, 0x81, 0x7E, 0x31, 0x5F, 0x59, 0x48, 0x31, 0x5F, 0x35, 0x56, 0x49, 0x5F, 0x47, 0x31, ++ 0x52, 0x56, 0x5F, 0x50, 0x32, 0x41, 0x5F, 0x39, 0x30, 0x54, 0x5F, 0x32, 0x81, 0x42, 0x30, 0x34, ++ 0x00, 0x00, 0x81, 0x7E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, ++}; ++ ++#endif /*__GPHY_IP_11G_FW__ */ +diff --git a/include/switch_api/ifx_ethsw.h b/include/switch_api/ifx_ethsw.h +new file mode 100644 +index 0000000..fc55000 +--- /dev/null ++++ b/include/switch_api/ifx_ethsw.h +@@ -0,0 +1,3820 @@ ++/**************************************************************************** ++ ++ Copyright 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++*****************************************************************************/ ++#ifndef _IFX_ETHSW_H_ ++#define _IFX_ETHSW_H_ ++ ++#include "ifx_types.h" ++ ++/* =================================== */ ++/* Global typedef forward declarations */ ++/* =================================== */ ++ ++/* ============================= */ ++/* Local Macros & Definitions */ ++/* ============================= */ ++ ++/* IOCTL MAGIC */ ++#define IFX_ETHSW_MAGIC ('E') ++ ++/* Group definitions for Doxygen */ ++/** \defgroup ETHSW_IOCTL Ethernet Switch Application Interface ++ This chapter describes the entire interface for accessing and ++ configuring the services of the Ethernet switch module. Switching is done ++ based on the physical and virtual ports. */ ++/*@{*/ ++ ++/** \defgroup ETHSW_IOCTL_BRIDGE Ethernet Bridging Functions ++ Ethernet bridging (or switching) is the basic task of the device. It ++ provides individual configurations per port and standard global ++ switch features. ++*/ ++/** \defgroup ETHSW_IOCTL_VLAN VLAN Functions ++ This chapter describes VLAN bridging functionality. ++*/ ++/** \defgroup ETHSW_IOCTL_MULTICAST Multicast Functions ++ IGMP/MLD snooping configuration and support for IGMPv1, IGMPv2, IGMPv3, ++ MLDv1, and MLDv2. ++*/ ++/** \defgroup ETHSW_IOCTL_OAM Operation, Administration, and Management Functions ++ This chapter summarizes the functions that are provided to monitor the ++ data traffic passing through the device. ++*/ ++/** \defgroup ETHSW_IOCTL_QOS Quality of Service Functions ++ Switch and port configuration for Quality of Service (QoS). ++*/ ++ ++/*@}*/ ++ ++/* -------------------------------------------------------------------------- */ ++/* Structure and Enumeration Type Defintions */ ++/* -------------------------------------------------------------------------- */ ++ ++/** \addtogroup ETHSW_IOCTL_BRIDGE */ ++/*@{*/ ++ ++/** MAC Address Field Size. ++ Number of bytes used to store MAC address information. */ ++#define IFX_MAC_ADDRESS_LENGTH 6 ++ ++/** MAC Table Entry to be read. ++ Used by \ref IFX_ETHSW_MAC_TABLE_ENTRY_READ. */ ++typedef struct ++{ ++ /** Restart the get operation from the beginning of the table. Otherwise ++ return the next table entry (next to the entry that was returned ++ during the previous get operation). This boolean parameter is set by the ++ calling application. */ ++ IFX_boolean_t bInitial; ++ /** Indicates that the read operation got all last valid entries of the ++ table. This boolean parameter is set by the switch API ++ when the Switch API is called after the last valid one was returned already. */ ++ IFX_boolean_t bLast; ++ /** Get the MAC table entry belonging to the given Filtering Identifier (FID) ++ (not supported by all switches). */ ++ IFX_uint32_t nFId; ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. ++ ++ \remarks ++ This field is used as portmap field, when the MSB bit is set. ++ In portmap mode, every value bit represents an Ethernet port. ++ LSB represents Port 0 with incrementing counting. ++ The (MSB - 1) bit represent the last port. ++ The macro \ref IFX_ETHSW_PORTMAP_FLAG_SET allows to set the MSB bit, ++ marking it as portmap variable. ++ Checking the portmap flag can be done by ++ using the \ref IFX_ETHSW_PORTMAP_FLAG_GET macro. */ ++ IFX_uint32_t nPortId; ++ /** Aging Time, given in multiples of 1 second in a range from 1 s to 1,000,000 s. ++ The value read back in a GET command might differ slightly from the value ++ given in the SET command due to limited hardware timing resolution. ++ Filled out by the switch API implementation. */ ++ IFX_int32_t nAgeTimer; ++ /** Static Entry (value will be aged out after 'nAgeTimer' if the entry ++ is not set to static). */ ++ IFX_boolean_t bStaticEntry; ++ /** MAC Address. Filled out by the switch API implementation. */ ++ IFX_uint8_t nMAC[IFX_MAC_ADDRESS_LENGTH]; ++}IFX_ETHSW_MAC_tableRead_t; ++ ++/** Search for a MAC address entry in the address table. ++ Used by \ref IFX_ETHSW_MAC_TABLE_ENTRY_QUERY. */ ++typedef struct ++{ ++ /** MAC Address. This parameter needs to be provided for the search operation. ++ This is an input parameter. */ ++ IFX_uint8_t nMAC[IFX_MAC_ADDRESS_LENGTH]; ++ /** Get the MAC table entry belonging to the given Filtering Identifier (FID) ++ (not supported by all switches). ++ This is an input parameter. */ ++ IFX_uint32_t nFId; ++ /** MAC Address Found. Switch API sets this boolean variable in case ++ the requested MAC address 'nMAC' is found inside the address table, ++ otherwise it is set to FALSE. ++ This is an output parameter. */ ++ IFX_boolean_t bFound; ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. ++ ++ \remarks ++ This field is used as portmap field, when the MSB bit is set. ++ In portmap mode, every value bit represents an Ethernet port. ++ LSB represents Port 0 with incrementing counting. ++ The (MSB - 1) bit represent the last port. ++ The macro \ref IFX_ETHSW_PORTMAP_FLAG_SET allows to set the MSB bit, ++ marking it as portmap variable. ++ Checking the portmap flag can be done by ++ using the \ref IFX_ETHSW_PORTMAP_FLAG_GET macro. */ ++ IFX_uint32_t nPortId; ++ /** Aging Time, given in multiples of 1 second in a range from 1 s to 1,000,000 s. ++ The value read back in a GET command might differ slightly from the value ++ given in the SET command due to limited hardware timing resolution. ++ Filled out by the switch API implementation. ++ This is an output parameter. */ ++ IFX_int32_t nAgeTimer; ++ /** Static Entry (value will be aged out after 'nAgeTimer' if the entry ++ is not set to static). ++ This is an output parameter. */ ++ IFX_boolean_t bStaticEntry; ++}IFX_ETHSW_MAC_tableQuery_t; ++ ++/** MAC Table Entry to be added. ++ Used by \ref IFX_ETHSW_MAC_TABLE_ENTRY_ADD. */ ++typedef struct ++{ ++ /** Filtering Identifier (FID) (not supported by all switches) */ ++ IFX_uint32_t nFId; ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. ++ ++ \remarks ++ This field is used as portmap field, when the MSB bit is set. ++ In portmap mode, every value bit represents an Ethernet port. ++ LSB represents Port 0 with incrementing counting. ++ The (MSB - 1) bit represent the last port. ++ The macro \ref IFX_ETHSW_PORTMAP_FLAG_SET allows to set the MSB bit, ++ marking it as portmap variable. ++ Checking the portmap flag can be done by ++ using the \ref IFX_ETHSW_PORTMAP_FLAG_GET macro. */ ++ IFX_uint32_t nPortId; ++ /** Aging Time, given in multiples of 1 second in a range ++ from 1 s to 1,000,000 s. ++ The configured value might be rounded that it fits to the given hardware platform. */ ++ IFX_int32_t nAgeTimer; ++ /** Static Entry (value will be aged out if the entry is not set to static). The ++ switch API implementation uses the maximum age timer in case the entry ++ is not static. */ ++ IFX_boolean_t bStaticEntry; ++ /** Egress queue traffic class. ++ The queue index starts counting from zero. */ ++ IFX_uint8_t nTrafficClass; ++ /** MAC Address to add to the table. */ ++ IFX_uint8_t nMAC[IFX_MAC_ADDRESS_LENGTH]; ++}IFX_ETHSW_MAC_tableAdd_t; ++ ++/** MAC Table Entry to be removed. ++ Used by \ref IFX_ETHSW_MAC_TABLE_ENTRY_REMOVE. */ ++typedef struct ++{ ++ /** Filtering Identifier (FID) (not supported by all switches) */ ++ IFX_uint32_t nFId; ++ /** MAC Address to be removed from the table. */ ++ IFX_uint8_t nMAC[IFX_MAC_ADDRESS_LENGTH]; ++}IFX_ETHSW_MAC_tableRemove_t; ++ ++/** Packet forwarding. ++ Used by \ref IFX_ETHSW_STP_BPDU_Rule_t and \ref IFX_ETHSW_multicastSnoopCfg_t ++ and \ref IFX_ETHSW_8021X_EAPOL_Rule_t. */ ++typedef enum ++{ ++ /** Default; portmap is determined by the forwarding classification. */ ++ IFX_ETHSW_PORT_FORWARD_DEFAULT = 0, ++ /** Discard; discard packets. */ ++ IFX_ETHSW_PORT_FORWARD_DISCARD = 1, ++ /** Forward to the CPU port. This requires that the CPU port is previously ++ set by calling \ref IFX_ETHSW_CPU_PORT_CFG_SET. */ ++ IFX_ETHSW_PORT_FORWARD_CPU = 2, ++ /** Forward to a port, selected by the parameter 'nForwardPortId'. ++ Please note that this feature is not supported by all ++ hardware platforms. */ ++ IFX_ETHSW_PORT_FORWARD_PORT = 3 ++}IFX_ETHSW_portForward_t; ++ ++/** Spanning Tree Protocol port states. ++ Used by \ref IFX_ETHSW_STP_portCfg_t. */ ++typedef enum ++{ ++ /** Forwarding state. The port is allowed to transmit and receive ++ all packets. Address Learning is allowed. */ ++ IFX_ETHSW_STP_PORT_STATE_FORWARD = 0, ++ /** Disabled/Discarding state. The port entity will not transmit ++ and receive any packets. Learning is disabled in this state. */ ++ IFX_ETHSW_STP_PORT_STATE_DISABLE = 1, ++ /** Learning state. The port entity will only transmit and receive ++ Spanning Tree Protocol packets (BPDU). All other packets are discarded. ++ MAC table address learning is enabled for all good frames. */ ++ IFX_ETHSW_STP_PORT_STATE_LEARNING = 2, ++ /** Blocking/Listening. Only the Spanning Tree Protocol packets will ++ be received and transmitted. All other packets are discarded by ++ the port entity. MAC table address learning is disabled in this ++ state. */ ++ IFX_ETHSW_STP_PORT_STATE_BLOCKING = 3 ++}IFX_ETHSW_STP_PortState_t; ++ ++/** Configures the Spanning Tree Protocol state of an Ethernet port. ++ Used by \ref IFX_ETHSW_STP_PORT_CFG_SET ++ and \ref IFX_ETHSW_STP_PORT_CFG_GET. */ ++typedef struct ++{ ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. */ ++ IFX_uint8_t nPortId; ++ /** Spanning Tree Protocol state of the port. */ ++ IFX_ETHSW_STP_PortState_t ePortState; ++}IFX_ETHSW_STP_portCfg_t; ++ ++/** Spanning tree packet detection and forwarding. ++ Used by \ref IFX_ETHSW_STP_BPDU_RULE_SET ++ and \ref IFX_ETHSW_STP_BPDU_RULE_GET. */ ++typedef struct ++{ ++ /** Filter spanning tree packets and forward them, discard them or ++ disable the filter. */ ++ IFX_ETHSW_portForward_t eForwardPort; ++ /** Target port for forwarded packets; only used if selected by ++ 'eForwardPort'. Forwarding is done ++ if 'eForwardPort = IFX_ETHSW_PORT_FORWARD_PORT'. */ ++ IFX_uint8_t nForwardPortId; ++}IFX_ETHSW_STP_BPDU_Rule_t; ++ ++/** Describes the 802.1x port state. ++ Used by \ref IFX_ETHSW_8021X_portCfg_t. */ ++typedef enum ++{ ++ /** Receive and transmit direction are authorized. The port is allowed to ++ transmit and receive all packets and the address learning process is ++ also allowed. */ ++ IFX_ETHSW_8021X_PORT_STATE_AUTHORIZED = 0, ++ /** Receive and transmit direction are unauthorized. All the packets ++ except EAPOL are not allowed to transmit and receive. The address learning ++ process is disabled. */ ++ IFX_ETHSW_8021X_PORT_STATE_UNAUTHORIZED = 1, ++ /** Receive direction is authorized, transmit direction is unauthorized. ++ The port is allowed to receive all packets. Packet transmission to this ++ port is not allowed. The address learning process is also allowed. */ ++ IFX_ETHSW_8021X_PORT_STATE_RX_AUTHORIZED = 2, ++ /** Transmit direction is authorized, receive direction is unauthorized. ++ The port is allowed to transmit all packets. Packet reception on this ++ port is not allowed. The address learning process is disabled. */ ++ IFX_ETHSW_8021X_PORT_STATE_TX_AUTHORIZED = 3 ++}IFX_ETHSW_8021X_portState_t; ++ ++/** EAPOL frames filtering rule parameter. ++ Used by \ref IFX_ETHSW_8021X_EAPOL_RULE_GET ++ and \ref IFX_ETHSW_8021X_EAPOL_RULE_SET. */ ++typedef struct ++{ ++ /** Filter authentication packets and forward them, discard them or ++ disable the filter. */ ++ IFX_ETHSW_portForward_t eForwardPort; ++ /** Target port for forwarded packets, only used if selected by ++ 'eForwardPort'. Forwarding is done ++ if 'eForwardPort = IFX_ETHSW_PORT_FORWARD_PORT'. */ ++ IFX_uint8_t nForwardPortId; ++}IFX_ETHSW_8021X_EAPOL_Rule_t; ++ ++/** 802.1x port authentication status. ++ Used by \ref IFX_ETHSW_8021X_PORT_CFG_GET ++ and \ref IFX_ETHSW_8021X_PORT_CFG_SET. */ ++typedef struct ++{ ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. */ ++ IFX_uint32_t nPortId; ++ /** 802.1x state of the port. */ ++ IFX_ETHSW_8021X_portState_t eState; ++}IFX_ETHSW_8021X_portCfg_t; ++ ++/*@}*/ /* ETHSW_IOCTL_BRIDGE */ ++ ++/** \addtogroup ETHSW_IOCTL_VLAN */ ++/*@{*/ ++ ++/** VLAN port configuration for ingress packet filtering. Tagged packet and ++ untagged packet can be configured to be accepted or dropped (filtered out). ++ Used by \ref IFX_ETHSW_VLAN_portCfg_t. */ ++typedef enum ++{ ++ /** Admit all. Tagged and untagged packets are allowed. */ ++ IFX_ETHSW_VLAN_ADMIT_ALL = 0, ++ /** Untagged packets only (not supported yet). Tagged packets are dropped. */ ++ IFX_ETHSW_VLAN_ADMIT_UNTAGGED = 1, ++ /** Tagged packets only. Untagged packets are dropped. */ ++ IFX_ETHSW_VLAN_ADMIT_TAGGED = 2 ++}IFX_ETHSW_VLAN_Admit_t; ++ ++/** Add a VLAN ID group to the VLAN hardware table of the switch. ++ Used by \ref IFX_ETHSW_VLAN_ID_CREATE. */ ++typedef struct ++{ ++ /** VLAN ID. The valid range is from 0 to 4095. ++ An error code is delivered in case of range mismatch. */ ++ IFX_uint16_t nVId; ++ /** Filtering Identifier (FID) (not supported by all switches). */ ++ IFX_uint32_t nFId; ++}IFX_ETHSW_VLAN_IdCreate_t; ++ ++/** Read out the VLAN ID to FID assignment. The user provides the VLAN ID ++ parameter and the switch APi returns the FID parameter. ++ Used by \ref IFX_ETHSW_VLAN_ID_GET. */ ++typedef struct ++{ ++ /** VLAN ID. The valid range is from 0 to 4095. ++ An error code is delivered in case of range mismatch. */ ++ IFX_uint16_t nVId; ++ /** Filtering Identifier (FID) (not supported by all switches). */ ++ IFX_uint32_t nFId; ++}IFX_ETHSW_VLAN_IdGet_t; ++ ++/** Remove a VLAN ID from the switch VLAN table. ++ Used by \ref IFX_ETHSW_VLAN_ID_DELETE. */ ++typedef struct ++{ ++ /** VLAN ID. The valid range is from 0 to 4095. ++ An error code is delivered in case of range mismatch. */ ++ IFX_uint16_t nVId; ++}IFX_ETHSW_VLAN_IdDelete_t; ++ ++/** Adds a VLAN to a port and set its egress filter information. ++ Used by \ref IFX_ETHSW_VLAN_PORT_MEMBER_ADD. */ ++typedef struct ++{ ++ /** VLAN ID. The valid range is from 0 to 4095. ++ An error code is delivered in case of range mismatch. */ ++ IFX_uint16_t nVId; ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. ++ ++ \remarks ++ This field is used as portmap field, when the MSB bit is set. ++ In portmap mode, every value bit represents an Ethernet port. ++ LSB represents Port 0 with incrementing counting. ++ The (MSB - 1) bit represent the last port. ++ The macro \ref IFX_ETHSW_PORTMAP_FLAG_SET allows to set the MSB bit, ++ marking it as portmap variable. ++ Checking the portmap flag can be done by ++ using the \ref IFX_ETHSW_PORTMAP_FLAG_GET macro. */ ++ IFX_uint8_t nPortId; ++ /** Tag Member Egress. Enable egress tag-based support. ++ If enabled, all port egress traffic ++ from this VLAN group carries a VLAN group tag. */ ++ IFX_boolean_t bVLAN_TagEgress; ++}IFX_ETHSW_VLAN_portMemberAdd_t; ++ ++/** Remove the VLAN configuration from an Ethernet port. ++ Used by \ref IFX_ETHSW_VLAN_PORT_MEMBER_REMOVE. */ ++typedef struct ++{ ++ /** VLAN ID. The valid range is from 0 to 4095. ++ An error code is delivered in case of range mismatch. ++ If the selected VLAN ID is not found in the vLAN table, ++ an error code is delivered. */ ++ IFX_uint16_t nVId; ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. ++ ++ \remarks ++ This field is used as portmap field, when the MSB bit is set. ++ In portmap mode, every value bit represents an Ethernet port. ++ LSB represents Port 0 with incrementing counting. ++ The (MSB - 1) bit represent the last port. ++ The macro \ref IFX_ETHSW_PORTMAP_FLAG_SET allows to set the MSB bit, ++ marking it as portmap variable. ++ Checking the portmap flag can be done by ++ using the \ref IFX_ETHSW_PORTMAP_FLAG_GET macro. */ ++ IFX_uint8_t nPortId; ++}IFX_ETHSW_VLAN_portMemberRemove_t; ++ ++/** Read the VLAN port membership table. ++ Used by \ref IFX_ETHSW_VLAN_PORT_MEMBER_READ. */ ++typedef struct ++{ ++ /** Restart the get operation from the start of the table. Otherwise ++ return the next table entry (next to the entry that was returned ++ during the previous get operation). This parameter is always reset ++ during the read operation. This boolean parameter is set by the ++ calling application. */ ++ IFX_boolean_t bInitial; ++ /** Indicates that the read operation got all last valid entries of the ++ table. This boolean parameter is set by the switch API ++ when the Switch API is called after the last valid one was returned already. */ ++ IFX_boolean_t bLast; ++ /** VLAN ID. The valid range is from 0 to 4095. ++ An error code is delivered in case of range mismatch. */ ++ IFX_uint16_t nVId; ++ /** Ethernet Port number (zero-based counting). Every bit represents ++ an Ethernet port. ++ ++ \remarks ++ This field is used as portmap field, when the MSB bit is set. ++ In portmap mode, every value bit represents an Ethernet port. ++ LSB represents Port 0 with incrementing counting. ++ The (MSB - 1) bit represent the last port. ++ The macro \ref IFX_ETHSW_PORTMAP_FLAG_SET allows to set the MSB bit, ++ marking it as portmap variable. ++ Checking the portmap flag can be done by ++ using the \ref IFX_ETHSW_PORTMAP_FLAG_GET macro. */ ++ IFX_uint32_t nPortId; ++ /** Enable egress tag-Portmap. Every bit represents an Ethernet port. ++ This field is used as portmap field, and the MSB bit is ++ statically always set. LSB represents Port 0 with ++ incrementing counting. ++ The (MSB - 1) bit represent the last port. ++ All port egress traffic from this VLAN group carries a ++ VLAN group tag, in case the port bit is set. ++ ++ \remarks ++ Checking the portmap flag can be done by ++ using the \ref IFX_ETHSW_PORTMAP_FLAG_GET macro. */ ++ IFX_uint32_t nTagId; ++}IFX_ETHSW_VLAN_portMemberRead_t; ++ ++/** Port configuration for VLAN member violation. ++ Used by \ref IFX_ETHSW_VLAN_portCfg_t. */ ++typedef enum ++{ ++ /** No VLAN member violation. Ingress and egress packets violating the ++ membership pass and are not filtered out. */ ++ IFX_ETHSW_VLAN_MEMBER_VIOLATION_NO = 0, ++ /** VLAN member violation for ingress packets. Ingress packets violating ++ the membership are filtered out. Egress packets violating the ++ membership are not filtered out. */ ++ IFX_ETHSW_VLAN_MEMBER_VIOLATION_INGRESS = 1, ++ /** VLAN member violation for egress packets. Egress packets violating ++ the membership are filtered out. Ingress packets violating the ++ membership are not filtered out.*/ ++ IFX_ETHSW_VLAN_MEMBER_VIOLATION_EGRESS = 2, ++ /** VLAN member violation for ingress and egress packets. ++ Ingress and egress packets violating the membership are filtered out. */ ++ IFX_ETHSW_VLAN_MEMBER_VIOLATION_BOTH = 3 ++}IFX_ETHSW_VLAN_MemberViolation_t; ++ ++/** VLAN Port Configuration. ++ Used by \ref IFX_ETHSW_VLAN_PORT_CFG_GET ++ and \ref IFX_ETHSW_VLAN_PORT_CFG_SET. */ ++typedef struct ++{ ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. */ ++ IFX_uint8_t nPortId; ++ /** Port VLAN ID (PVID). The software shall ensure that the used VLAN has ++ been configured in advance on the hardware by ++ using \ref IFX_ETHSW_VLAN_ID_CREATE. */ ++ IFX_uint16_t nPortVId; ++ /** Drop ingress VLAN-tagged packets if the VLAN ID ++ is not listed in the active VLAN set. If disabled, all incoming ++ VLAN-tagged packets are forwarded using the FID tag members and ++ the port members of the PVID. */ ++ IFX_boolean_t bVLAN_UnknownDrop; ++ /** Reassign all ingress VLAN tagged packets to the port-based ++ VLAN ID (PVID). */ ++ IFX_boolean_t bVLAN_ReAssign; ++ /** VLAN ingress and egress membership violation mode. Allows admittance of ++ VLAN-tagged packets where the port is not a member of the VLAN ID ++ carried in the received and sent packet. */ ++ IFX_ETHSW_VLAN_MemberViolation_t eVLAN_MemberViolation; ++ /** Ingress VLAN-tagged or untagged packet filter configuration. */ ++ IFX_ETHSW_VLAN_Admit_t eAdmitMode; ++ /** Transparent VLAN Mode (TVM). All packets are handled as untagged ++ packets. Any existing tag is ignored and treated as packet payload. */ ++ IFX_boolean_t bTVM; ++}IFX_ETHSW_VLAN_portCfg_t; ++ ++/** This VLAN configuration supports replacing of the VID of received packets ++ with the PVID of the receiving port. ++ Used by \ref IFX_ETHSW_VLAN_RESERVED_ADD ++ and \ref IFX_ETHSW_VLAN_RESERVED_REMOVE. */ ++typedef struct ++{ ++ /** VID of the received packet to be replaced by the PVID. ++ The valid range is from 0 to 4095. ++ An error code is delivered in case of range mismatch. */ ++ IFX_uint16_t nVId; ++}IFX_ETHSW_VLAN_reserved_t; ++ ++/*@}*/ /* ETHSW_IOCTL_VLAN */ ++ ++/** \addtogroup ETHSW_IOCTL_QOS */ ++/*@{*/ ++ ++/** DSCP mapping table. ++ Used by \ref IFX_ETHSW_QOS_DSCP_CLASS_SET ++ and \ref IFX_ETHSW_QOS_DSCP_CLASS_GET. */ ++typedef struct ++{ ++ /** Traffic class associated with a particular DSCP value. ++ DSCP is the index to an array of resulting traffic class values. ++ The index starts counting from zero. */ ++ IFX_uint8_t nTrafficClass[64]; ++}IFX_ETHSW_QoS_DSCP_ClassCfg_t; ++ ++/** Traffic class associated with a particular 802.1P (PCP) priority mapping value. ++ This table is global for the entire switch device. Priority map entry structure. ++ Used by \ref IFX_ETHSW_QOS_PCP_CLASS_SET ++ and \ref IFX_ETHSW_QOS_PCP_CLASS_GET. */ ++typedef struct ++{ ++ /** Configures the PCP to traffic class mapping. ++ The queue index starts counting from zero. */ ++ IFX_uint8_t nTrafficClass[8]; ++}IFX_ETHSW_QoS_PCP_ClassCfg_t; ++ ++/** Ingress DSCP remarking attribute. This attribute defines on the ++ ingress port packets how these will be remarked on the egress port. ++ A packet is only remarked in case its ingress and its egress port ++ have remarking enabled. ++ Used by \ref IFX_ETHSW_QoS_portRemarkingCfg_t. */ ++typedef enum ++{ ++ /** No DSCP Remarking. No remarking is done on the egress port. */ ++ IFX_ETHSW_DSCP_REMARK_DISABLE = 0, ++ /** TC DSCP 6-Bit Remarking. The complete DSCP remarking is done based ++ on the traffic class. The traffic class to DSCP value mapping is ++ given in a device global table. */ ++ IFX_ETHSW_DSCP_REMARK_TC6 = 1, ++ /** TC DSCP 3-Bit Remarking. The upper 3-Bits of the DSCP field are ++ remarked based on the traffic class. The traffic class to DSCP value ++ mapping is given in a device global table. */ ++ IFX_ETHSW_DSCP_REMARK_TC3 = 2, ++ /** Drop Precedence Remarking. The Drop Precedence is remarked on the ++ egress side. */ ++ IFX_ETHSW_DSCP_REMARK_DP3 = 3, ++ /** TC Drop Precedence Remarking. The Drop Precedence is remarked on the ++ egress side and the upper 3-Bits of the DSCP field are ++ remarked based on the traffic class. The traffic class to DSCP value ++ mapping is given in a device global table. */ ++ IFX_ETHSW_DSCP_REMARK_DP3_TC3 = 4 ++}IFX_ETHSW_Qos_ingressRemarking_t; ++ ++/** Port Remarking Configuration. Ingress and Egress remarking options for ++ DSCP and PCP. Remarking is done either on the used traffic class or ++ the drop precedence. ++ Used by \ref IFX_ETHSW_QOS_PORT_REMARKING_CFG_SET ++ and \ref IFX_ETHSW_QOS_PORT_REMARKING_CFG_GET. */ ++typedef struct ++{ ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. */ ++ IFX_uint8_t nPortId; ++ /** Ingress DSCP Remarking. Specifies on ingress side how a packet should ++ be remarked. This DSCP remarking only works in case remarking is ++ enabled on the egress port. ++ This configuration requires that remarking is also enabled on the ++ egress port. DSCP remarking enable on either ingress or egress port ++ side does not perform any remark operation. */ ++ IFX_ETHSW_Qos_ingressRemarking_t eDSCP_IngressRemarkingEnable; ++ /** Egress DSCP Remarking. Applies remarking on egress packets in a ++ fashion as specified on the ingress port. This ingress port remarking ++ is configured by the parameter 'eDSCP_IngressRemarking'. ++ This configuration requires that remarking is also enabled on the ++ ingress port. DSCP remarking enable on either ingress or egress port ++ side does not perform any remark operation. */ ++ IFX_boolean_t bDSCP_EgressRemarkingEnable; ++ /** Ingress PCP Remarking. Applies remarking to all port ingress packets. ++ This configuration requires that remarking is also enabled on the ++ egress port. PCP remarking enable on either ingress or egress port ++ side does not perform any remark operation. */ ++ IFX_boolean_t bPCP_IngressRemarkingEnable; ++ /** Egress PCP Remarking. Applies remarking for all port egress packets. ++ This configuration requires that remarking is also enabled on the ++ ingress port. PCP remarking enable on either ingress or egress port ++ side does not perform any remark operation. */ ++ IFX_boolean_t bPCP_EgressRemarkingEnable; ++}IFX_ETHSW_QoS_portRemarkingCfg_t; ++ ++/** Traffic class to DSCP mapping table. ++ Used by \ref IFX_ETHSW_QOS_CLASS_DSCP_SET ++ and \ref IFX_ETHSW_QOS_CLASS_DSCP_GET. */ ++typedef struct ++{ ++ /** DSCP value (6-bit) associated with a particular Traffic class. ++ Traffic class is the index to an array of resulting DSCP values. ++ The index starts counting from zero. */ ++ IFX_uint8_t nDSCP[16]; ++}IFX_ETHSW_QoS_ClassDSCP_Cfg_t; ++ ++/** Traffic class associated with a particular 802.1P (PCP) priority mapping value. ++ This table is global for the entire switch device. Priority map entry structure. ++ Used by \ref IFX_ETHSW_QOS_CLASS_PCP_SET ++ and \ref IFX_ETHSW_QOS_CLASS_PCP_GET. */ ++typedef struct ++{ ++ /** Configures the traffic class to PCP (3-bit) mapping. ++ The queue index starts counting from zero. */ ++ IFX_uint8_t nPCP[16]; ++}IFX_ETHSW_QoS_ClassPCP_Cfg_t; ++ ++/** DSCP Drop Precedence to color code assignment. ++ Used by \ref IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t. */ ++typedef enum ++{ ++ /** Critical Packet. Metering never changes the drop precedence of these packets. */ ++ IFX_ETHSW_DROP_PRECEDENCE_CRITICAL = 0, ++ /** Green Drop Precedence Packet. Packet is marked with a 'low' drop precedence. */ ++ IFX_ETHSW_DROP_PRECEDENCE_GREEN = 1, ++ /** Yellow Drop Precedence Packet. Packet is marked with a 'middle' drop precedence. */ ++ IFX_ETHSW_DROP_PRECEDENCE_YELLOW = 2, ++ /** Red Drop Precedence Packet. Packet is marked with a 'high' drop precedence. */ ++ IFX_ETHSW_DROP_PRECEDENCE_RED = 3 ++}IFX_ETHSW_QoS_DropPrecedence_t; ++ ++/** DSCP to Drop Precedence assignment table configuration. ++ Used by \ref IFX_ETHSW_QOS_DSCP_DROP_PRECEDENCE_CFG_SET ++ and \ref IFX_ETHSW_QOS_DSCP_DROP_PRECEDENCE_CFG_GET. */ ++typedef struct ++{ ++ /** DSCP to drop precedence assignment. Every array entry represents the ++ drop precedence for one of the 64 existing DSCP values. ++ DSCP is the index to an array of resulting drop precedence values. ++ The index starts counting from zero. */ ++ IFX_ETHSW_QoS_DropPrecedence_t nDSCP_DropPrecedence[64]; ++}IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t; ++ ++/** Selection of the traffic class field. ++ Used by \ref IFX_ETHSW_QoS_portCfg_t. */ ++typedef enum ++{ ++ /** No traffic class assignment based on DSCP or PCP */ ++ IFX_ETHSW_QOS_CLASS_SELECT_NO = 0, ++ /** Traffic class assignment based on DSCP. PCP information is ignored. ++ The Port Class is used in case DSCP is not available in the packet. */ ++ IFX_ETHSW_QOS_CLASS_SELECT_DSCP = 1, ++ /** Traffic class assignment based on PCP. DSCP information is ignored. ++ The Port Class is used in case PCP is not available in the packet. */ ++ IFX_ETHSW_QOS_CLASS_SELECT_PCP = 2, ++ /** Traffic class assignment based on DSCP. Make the assignment based on ++ PCP in case the DSCP information is not available in the packet header. ++ The Port Class is used in case both are not available in the packet. */ ++ IFX_ETHSW_QOS_CLASS_SELECT_DSCP_PCP = 3, ++ /** Traffic class assignment based on PCP. Make the assignment based on ++ DSCP in case the PCP information is not available in the packet header. ++ The Port Class is used in case both are not available in the packet. */ ++ IFX_ETHSW_QOS_CLASS_SELECT_PCP_DSCP = 4 ++}IFX_ETHSW_QoS_ClassSelect_t; ++ ++/** Describes which priority information of ingress packets is used ++ (taken into account) to identify the packet priority and the related egress ++ priority queue. For DSCP, the priority to queue assignment is done ++ using \ref IFX_ETHSW_QOS_DSCP_CLASS_SET. For VLAN, the priority to queue ++ assignment is done using \ref IFX_ETHSW_QOS_PCP_CLASS_SET. ++ Used by \ref IFX_ETHSW_QOS_PORT_CFG_SET ++ and \ref IFX_ETHSW_QOS_PORT_CFG_GET. */ ++typedef struct ++{ ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. */ ++ IFX_uint8_t nPortId; ++ /** Select the packet header field on which to base the traffic class assignment. */ ++ IFX_ETHSW_QoS_ClassSelect_t eClassMode; ++ /** Default port priority in case no other priority ++ (such as VLAN-based PCP or IP-based DSCP) is used. */ ++ IFX_uint8_t nTrafficClass; ++}IFX_ETHSW_QoS_portCfg_t; ++ ++/** Configures a rate shaper instance with the rate and the burst size. ++ Used by \ref IFX_ETHSW_QOS_SHAPER_CFG_SET ++ and \ref IFX_ETHSW_QOS_SHAPER_CFG_GET. */ ++typedef struct ++{ ++ /** Rate shaper index (zero-based counting). */ ++ IFX_uint32_t nRateShaperId; ++ /** Enable/Disable the rate shaper. */ ++ IFX_boolean_t bEnable; ++ /** Committed Burst Size (CBS [bytes]) */ ++ IFX_uint32_t nCbs; ++ /** Rate [kbit/s] */ ++ IFX_uint32_t nRate; ++}IFX_ETHSW_QoS_ShaperCfg_t; ++ ++/** Assign one rate shaper instance to a QoS queue. ++ Used by \ref IFX_ETHSW_QOS_SHAPER_QUEUE_ASSIGN ++ and \ref IFX_ETHSW_QOS_SHAPER_QUEUE_DEASSIGN. */ ++typedef struct ++{ ++ /** Rate shaper index (zero-based counting). */ ++ IFX_uint8_t nRateShaperId; ++ /** QoS queue index (zero-based counting). */ ++ IFX_uint8_t nQueueId; ++}IFX_ETHSW_QoS_ShaperQueue_t; ++ ++/** Retrieve if a rate shaper instance is assigned to a QoS egress queue. ++ Used by \ref IFX_ETHSW_QOS_SHAPER_QUEUE_GET. */ ++typedef struct ++{ ++ /** QoS queue index (zero-based counting). ++ This parameter is the input parameter for the GET function. */ ++ IFX_uint8_t nQueueId; ++ /** Rate shaper instance assigned. ++ If IFX_TRUE, a rate shaper instance is assigned to the queue. Otherwise no shaper instance is assigned. */ ++ IFX_boolean_t bAssigned; ++ /** Rate shaper index (zero-based counting). Only a valid instance is returned in case 'bAssigned == IFX_TRUE'. */ ++ IFX_uint8_t nRateShaperId; ++}IFX_ETHSW_QoS_ShaperQueueGet_t; ++ ++/** Drop Probability Profile. Defines the drop probability profile. ++ Used by \ref IFX_ETHSW_QoS_WRED_Cfg_t. */ ++typedef enum ++{ ++ /** Pmin = 25%, Pmax = 75% (default) */ ++ IFX_ETHSW_QOS_WRED_PROFILE_P0 = 0, ++ /** Pmin = 25%, Pmax = 50% */ ++ IFX_ETHSW_QOS_WRED_PROFILE_P1 = 1, ++ /** Pmin = 50%, Pmax = 50% */ ++ IFX_ETHSW_QOS_WRED_PROFILE_P2 = 2, ++ /** Pmin = 50%, Pmax = 75% */ ++ IFX_ETHSW_QOS_WRED_PROFILE_P3 = 3 ++}IFX_ETHSW_QoS_WRED_Profile_t; ++ ++/** Configures the global probability profile of the device. ++ The min. and max. values are given in number of packet ++ buffer segments. The size of a segment can be ++ retrieved using \ref IFX_ETHSW_CAP_GET. ++ Used by \ref IFX_ETHSW_QOS_WRED_CFG_SET ++ and \ref IFX_ETHSW_QOS_WRED_CFG_GET. */ ++typedef struct ++{ ++ /** Drop Probability Profile. */ ++ IFX_ETHSW_QoS_WRED_Profile_t eProfile; ++ /** WRED Red Threshold Min [number of segments]. */ ++ IFX_uint32_t nRed_Min; ++ /** WRED Red Threshold Max [number of segments]. */ ++ IFX_uint32_t nRed_Max; ++ /** WRED Yellow Threshold Min [number of segments]. */ ++ IFX_uint32_t nYellow_Min; ++ /** WRED Yellow Threshold Max [number of segments]. */ ++ IFX_uint32_t nYellow_Max; ++ /** WRED Green Threshold Min [number of segments]. */ ++ IFX_uint32_t nGreen_Min; ++ /** WRED Green Threshold Max [number of segments]. */ ++ IFX_uint32_t nGreen_Max; ++}IFX_ETHSW_QoS_WRED_Cfg_t; ++ ++/** Configures the WRED threshold parameter. ++ The min. and max. values are given in number of packet ++ buffer segments. The size of a segment can be ++ retrieved using \ref IFX_ETHSW_CAP_GET. ++ Used by \ref IFX_ETHSW_QOS_WRED_QUEUE_CFG_SET ++ and \ref IFX_ETHSW_QOS_WRED_QUEUE_CFG_GET. */ ++typedef struct ++{ ++ /** QoS queue index (zero-based counting). */ ++ IFX_uint32_t nQueueId; ++ /** WRED Red Threshold Min [number of segments]. */ ++ IFX_uint32_t nRed_Min; ++ /** WRED Red Threshold Max [number of segments]. */ ++ IFX_uint32_t nRed_Max; ++ /** WRED Yellow Threshold Min [number of segments]. */ ++ IFX_uint32_t nYellow_Min; ++ /** WRED Yellow Threshold Max [number of segments]. */ ++ IFX_uint32_t nYellow_Max; ++ /** WRED Green Threshold Min [number of segments]. */ ++ IFX_uint32_t nGreen_Min; ++ /** WRED Green Threshold Max [number of segments]. */ ++ IFX_uint32_t nGreen_Max; ++}IFX_ETHSW_QoS_WRED_QueueCfg_t; ++ ++/** Configures the parameters of a rate meter instance. ++ Used by \ref IFX_ETHSW_QOS_METER_CFG_SET ++ and \ref IFX_ETHSW_QOS_METER_CFG_GET. */ ++typedef struct ++{ ++ /** Enable/Disable the meter shaper. */ ++ IFX_boolean_t bEnable; ++ /** Meter index (zero-based counting). */ ++ IFX_uint32_t nMeterId; ++ /** Committed Burst Size (CBS [Bytes]). */ ++ IFX_uint32_t nCbs; ++ /** Excess Burst Size (EBS [Bytes]). */ ++ IFX_uint32_t nEbs; ++ /** Rate [kbit/s] */ ++ IFX_uint32_t nRate; ++}IFX_ETHSW_QoS_meterCfg_t; ++ ++/** Specifies the direction for ingress and egress. ++ Used by \ref IFX_ETHSW_QoS_meterPort_t ++ and \ref IFX_ETHSW_QoS_meterPortGet_t. */ ++typedef enum ++{ ++ /** No direction. */ ++ IFX_ETHSW_DIRECTION_NONE = 0, ++ /** Ingress direction. */ ++ IFX_ETHSW_DIRECTION_INGRESS = 1, ++ /** Egress direction. */ ++ IFX_ETHSW_DIRECTION_EGRESS = 2, ++ /** Ingress and egress direction. */ ++ IFX_ETHSW_DIRECTION_BOTH = 3 ++}IFX_ETHSW_direction_t; ++ ++/** Assign a rate meter instance to an ingress and/or egress port. ++ Used by \ref IFX_ETHSW_QOS_METER_PORT_ASSIGN ++ and \ref IFX_ETHSW_QOS_METER_PORT_DEASSIGN. */ ++typedef struct ++{ ++ /** Meter index (zero-based counting). */ ++ IFX_uint32_t nMeterId; ++ /** Port assignment. Could be either ingress, egress or both. Setting it to ++ 'IFX_ETHSW_DIRECTION_NONE' would remove the queue for any port ++ assignment. */ ++ IFX_ETHSW_direction_t eDir; ++ /** Ingress Port Id. */ ++ IFX_uint32_t nPortIngressId; ++ /** Egress Port Id. */ ++ IFX_uint32_t nPortEgressId; ++}IFX_ETHSW_QoS_meterPort_t; ++ ++/** Reads out all meter instance to port assignments. ++ Used by \ref IFX_ETHSW_QOS_METER_PORT_GET. */ ++typedef struct ++{ ++ /** Restart the get operation from the start of the table. Otherwise ++ return the next table entry (next to the entry that was returned ++ during the previous get operation). This boolean parameter is set by the ++ calling application. */ ++ IFX_boolean_t bInitial; ++ /** Indicates that the read operation got all last valid entries of the ++ table. This boolean parameter is set by the switch API ++ when the Switch API is called after the last valid one was returned already. */ ++ IFX_boolean_t bLast; ++ /** Port assignment. Could be either ingress, egress or both. Setting it to ++ 'IFX_ETHSW_DIRECTION_NONE' would remove the queue for any port ++ assignment. */ ++ IFX_ETHSW_direction_t eDir; ++ /** Meter index (zero-based counting). */ ++ IFX_uint8_t nMeterId; ++ /** Ingress Port Id. */ ++ IFX_uint8_t nPortIngressId; ++ /** Egress Port Id. */ ++ IFX_uint8_t nPortEgressId; ++}IFX_ETHSW_QoS_meterPortGet_t; ++ ++/** Assigns one meter instances for storm control. ++ Used by \ref IFX_ETHSW_QOS_STORM_CFG_SET and \ref IFX_ETHSW_QOS_STORM_CFG_GET. */ ++typedef struct ++{ ++ /** Meter index 0 (zero-based counting). */ ++ IFX_int32_t nMeterId; ++ /** Meter instances used for broadcast traffic. */ ++ IFX_boolean_t bBroadcast; ++ /** Meter instances used for multicast traffic. */ ++ IFX_boolean_t bMulticast; ++ /** Meter instances used for unknown unicast traffic. */ ++ IFX_boolean_t bUnknownUnicast; ++}IFX_ETHSW_QoS_stormCfg_t; ++ ++/** Select the type of the egress queue scheduler. ++ Used by \ref IFX_ETHSW_QoS_schedulerCfg_t. */ ++typedef enum ++{ ++ /** Strict Priority. */ ++ IFX_ETHSW_QOS_SCHEDULER_STRICT = 0, ++ /** Weighted Fair Queuing. */ ++ IFX_ETHSW_QOS_SCHEDULER_WFQ = 1 ++}IFX_ETHSW_QoS_Scheduler_t; ++ ++/** Configures the egress queues attached to a single port, and that ++ are scheduled to transmit the queued Ethernet packets. ++ Used by \ref IFX_ETHSW_QOS_SCHEDULER_CFG_SET ++ and \ref IFX_ETHSW_QOS_SCHEDULER_CFG_GET. */ ++typedef struct ++{ ++ /** QoS queue index (zero-based counting). */ ++ IFX_uint8_t nQueueId; ++ /** Scheduler Type (Strict Priority/Weighted Fair Queuing). */ ++ IFX_ETHSW_QoS_Scheduler_t eType; ++ /** Weight in Token. Parameter used for WFQ configuration. ++ Sets the weight in token in relation to all remaining ++ queues on this egress port having WFQ configuration. ++ This parameter is only used ++ when 'eType=IFX_ETHSW_QOS_SCHEDULER_WFQ'. */ ++ IFX_uint32_t nWeight; ++}IFX_ETHSW_QoS_schedulerCfg_t; ++ ++/** Sets the Queue ID for one traffic class of one port. ++ Used by \ref IFX_ETHSW_QOS_QUEUE_PORT_SET ++ and \ref IFX_ETHSW_QOS_QUEUE_PORT_GET. */ ++typedef struct ++{ ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. ++ This is an input parameter for \ref IFX_ETHSW_QOS_QUEUE_PORT_GET. */ ++ IFX_uint8_t nPortId; ++ /** Traffic Class index (zero-based counting). ++ This is an input parameter for \ref IFX_ETHSW_QOS_QUEUE_PORT_GET. */ ++ IFX_uint8_t nTrafficClassId; ++ /** QoS queue index (zero-based counting). ++ This is an output parameter for \ref IFX_ETHSW_QOS_QUEUE_PORT_GET. */ ++ IFX_uint8_t nQueueId; ++}IFX_ETHSW_QoS_queuePort_t; ++ ++/*@}*/ /* ETHSW_IOCTL_QOS */ ++ ++/** \addtogroup ETHSW_IOCTL_MULTICAST */ ++/*@{*/ ++ ++/** Define setting the priority queue to an undefined value. ++ This disables the priority feature. */ ++#define IFX_ETHSW_TRAFFIC_CLASS_DISABLE 0xFF ++ ++/** Configure the IGMP snooping mode. ++ Used by \ref IFX_ETHSW_multicastSnoopCfg_t. */ ++typedef enum ++{ ++ /** IGMP management packet snooping and multicast level 3 table learning ++ is disabled. */ ++ IFX_ETHSW_MULTICAST_SNOOP_MODE_DISABLED = 0, ++ /** IGMP management packet snooping is enabled and used for the hardware ++ auto-learning to fill the multicast level 3 table. */ ++ IFX_ETHSW_MULTICAST_SNOOP_MODE_AUTOLEARNING = 1, ++ /** IGMP management packet snooping is enabled and forwarded to the ++ configured port. No autolearning of the multicast level 3 table. This ++ table has to be maintained by the management software. */ ++ IFX_ETHSW_MULTICAST_SNOOP_MODE_FORWARD = 2 ++}IFX_ETHSW_multicastSnoopMode_t; ++ ++/** Configure the IGMP report suppression mode. ++ Used by \ref IFX_ETHSW_multicastSnoopCfg_t. */ ++typedef enum ++{ ++ /** Report Suppression and Join Aggregation. */ ++ IFX_ETHSW_MULTICAST_REPORT_JOIN = 0, ++ /** Report Suppression. No Join Aggregation. */ ++ IFX_ETHSW_MULTICAST_REPORT = 1, ++ /** Transparent Mode. No Report Suppression and no Join Aggregation. */ ++ IFX_ETHSW_MULTICAST_TRANSPARENT = 2 ++}IFX_ETHSW_multicastReportSuppression_t; ++ ++/** Configure the switch multicast configuration. ++ Used by \ref IFX_ETHSW_MULTICAST_SNOOP_CFG_SET ++ and \ref IFX_ETHSW_MULTICAST_SNOOP_CFG_GET. */ ++typedef struct ++{ ++ /** Enables and configures the IGMP/MLD snooping feature. ++ Select autolearning or management packet forwarding mode. ++ Packet forwarding is done to the port selected in 'eForwardPort'. */ ++ IFX_ETHSW_multicastSnoopMode_t eIGMP_Mode; ++ /** IGMPv3 hardware support. ++ When enabled the IGMP table includes both the group table and ++ the source list table. Otherwise the table only includes the ++ group table. This feature is needed when supporting IGMPv3 and ++ MLDv2 protocols. */ ++ IFX_boolean_t bIGMPv3; ++ /** Enables snooped IGMP control packets treated as cross-VLAN packets. This ++ parameter is used for hardware auto-learning and snooping packets ++ forwarded to a dedicated port. This dedicated port can be selected ++ over 'eForwardPort'. */ ++ IFX_boolean_t bCrossVLAN; ++ /** Forward snooped packet, only used if forwarded mode ++ is selected ++ by 'eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_SNOOPFORWARD'. */ ++ IFX_ETHSW_portForward_t eForwardPort; ++ /** Target port for forwarded packets, only used if selected by ++ 'eForwardPort'. Forwarding is done ++ if 'eForwardPort = IFX_ETHSW_PORT_FORWARD_PORT'. */ ++ IFX_uint8_t nForwardPortId; ++ /** Snooping control class of service. ++ Snooping control packet can be forwarded to the 'nForwardPortId' when ++ selected in 'eIGMP_Mode'. The class of service of this port can be ++ selected for the snooped control packets, starting from zero. ++ The maximum possible service class depends ++ on the hardware platform used. The value ++ IFX_ETHSW_TRAFFIC_CLASS_DISABLE disables overwriting the given ++ class assignment. */ ++ IFX_uint8_t nClassOfService; ++ /** Robustness variable. ++ Used when the hardware-based IGMP/MLD snooping function is enabled. This ++ robust variable is used in case IGMP hardware learning is ++ enabled ('eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_AUTOLEARNING'). ++ Supported range: 1 ... 3 */ ++ IFX_uint8_t nRobust; ++ /** Query interval. ++ Used to define the query interval in units of 100 ms when the ++ hardware-based IGMP/MLD snooping function is enabled. ++ The automatically learned router port will be aged out if no IGMP/MLD ++ query frame is received from the router port ++ for (nQueryInterval * nRobust) seconds. ++ The supported range is from 100 ms to 25.5 s, with a default value ++ of 10 s. This query interval is used in case IGMP hardware learning is ++ enabled ('eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_AUTOLEARNING'). */ ++ IFX_uint8_t nQueryInterval; ++ /** IGMP/MLD report suppression and Join Aggregation control. ++ Whenever the report message is already sent out for the same multicast ++ group, the successive report message within the ++ query-max-responsetime with the same group ID will be filtered ++ by the switch. This is called report suppression. ++ Whenever the join message is already sent out for the same multicast ++ group, the successive join message with the same group ID will be filtered. ++ This is called join aggregation. This suppression control is used in ++ case IGMP hardware learning is ++ enable ('eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_AUTOLEARNING'). */ ++ IFX_ETHSW_multicastReportSuppression_t eSuppressionAggregation; ++ /** Hardware IGMP snooping fast leave option. ++ Allows the hardware to automatically clear the membership ++ when receiving the IGMP leave packet. This ++ fast leave option is used in case IGMP hardware learning is ++ enabled ('eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_AUTOLEARNING'). ++ Note: The fast-leave option shall only be enabled where only ++ one host is connected to each interface. ++ If fast-leave is enabled where more than one host is connected ++ to an interface, some hosts might be dropped inadvertently. ++ Fast-leave processing is supported only with IGMP version 2 hosts. */ ++ IFX_boolean_t bFastLeave; ++ /** Hardware router port auto-learning. Allows for the ++ ports on which a router is located to be learned automatically. This router port learning option is ++ used in case IGMP hardware learning is ++ enabled ('eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_AUTOLEARNING'). */ ++ IFX_boolean_t bLearningRouter; ++}IFX_ETHSW_multicastSnoopCfg_t; ++ ++/** Add an Ethernet port as router port to the switch hardware multicast table. ++ Used by \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_ADD ++ and \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_REMOVE. */ ++typedef struct ++{ ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. ++ ++ \remarks ++ This field is used as portmap field, when the MSB bit is set. ++ In portmap mode, every value bit represents an Ethernet port. ++ LSB represents Port 0 with incrementing counting. ++ The (MSB - 1) bit represent the last port. ++ The macro \ref IFX_ETHSW_PORTMAP_FLAG_SET allows to set the MSB bit, ++ marking it as portmap variable. ++ Checking the portmap flag can be done by ++ using the \ref IFX_ETHSW_PORTMAP_FLAG_GET macro. */ ++ IFX_uint8_t nPortId; ++}IFX_ETHSW_multicastRouter_t; ++ ++/** Check if a port has been selected as a router port. ++ Used by \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_READ. */ ++typedef struct ++{ ++ /** Restart the get operation from the start of the table. Otherwise ++ return the next table entry (next to the entry that was returned ++ during the previous get operation). This parameter is always reset ++ during the read operation. This boolean parameter is set by the ++ calling application. */ ++ IFX_boolean_t bInitial; ++ /** Indicates that the read operation got all last valid entries of the ++ table. This boolean parameter is set by the switch API ++ when the Switch API is called after the last valid one was returned already. */ ++ IFX_boolean_t bLast; ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. */ ++ IFX_uint8_t nPortId; ++}IFX_ETHSW_multicastRouterRead_t; ++ ++/** This is a union to describe the IPv4 and IPv6 parameter. ++ Used by \ref IFX_ETHSW_multicastTable_t ++ and \ref IFX_ETHSW_multicastTableRead_t. */ ++typedef union ++{ ++ /** Describe the IPv4 address. ++ Only used if the IPv4 address should be read or configured. ++ Cannot be used together with the IPv6 address fields. */ ++ IFX_uint32_t nIPv4; ++ /** Describe the IPv6 address. ++ Only used if the IPv6 address should be read or configured. ++ Cannot be used together with the IPv4 address fields. */ ++ IFX_uint16_t nIPv6[8]; ++}IFX_ETHSW_IP_t; ++ ++/** Selection to use IPv4 or IPv6. ++ Used by \ref IFX_ETHSW_multicastTable_t ++ and \ref IFX_ETHSW_multicastTableRead_t. */ ++typedef enum ++{ ++ /** IPv4 */ ++ IFX_ETHSW_IP_SELECT_IPV4 = 0, ++ /** IPv6 */ ++ IFX_ETHSW_IP_SELECT_IPV6 = 1 ++}IFX_ETHSW_IP_Select_t; ++ ++/** Defines the multicast group member mode. ++ Used by \ref IFX_ETHSW_multicastTable_t ++ and \ref IFX_ETHSW_multicastTableRead_t. */ ++typedef enum ++{ ++ /** Include source IP address membership mode. ++ Only supported for IGMPv3. */ ++ IFX_ETHSW_IGMP_MEMBER_INCLUDE = 0, ++ /** Exclude source IP address membership mode. ++ Only supported for IGMPv3. */ ++ IFX_ETHSW_IGMP_MEMBER_EXCLUDE = 1, ++ /** Group source IP address is 'don't care'. This means all source IP ++ addresses (*) are included for the multicast group membership. ++ This is the default mode for IGMPv1 and IGMPv2. */ ++ IFX_ETHSW_IGMP_MEMBER_DONT_CARE = 2 ++}IFX_ETHSW_IGMP_MemberMode_t; ++ ++/** Add a host as a member to a multicast group. ++ Used by \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_ADD and \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_REMOVE. */ ++typedef struct ++{ ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. */ ++ IFX_uint8_t nPortId; ++ /** Select the IP version of the 'uIP_Gda' and 'uIP_Gsa' fields. ++ Both fields support either IPv4 or IPv6. */ ++ IFX_ETHSW_IP_Select_t eIPVersion; ++ /** Group Destination IP address (GDA). */ ++ IFX_ETHSW_IP_t uIP_Gda; ++ /** Group Source IP address. Only used in case IGMPv3 support is enabled ++ and 'eModeMember != IFX_ETHSW_IGMP_MEMBER_DONT_CARE'. */ ++ IFX_ETHSW_IP_t uIP_Gsa; ++ /** Group member filter mode. ++ This parameter is ignored when deleting a multicast membership table entry. ++ The configurations 'IFX_ETHSW_IGMP_MEMBER_EXCLUDE' ++ and 'IFX_ETHSW_IGMP_MEMBER_INCLUDE' are only supported ++ if IGMPv3 is used. */ ++ IFX_ETHSW_IGMP_MemberMode_t eModeMember; ++}IFX_ETHSW_multicastTable_t; ++ ++/** Read out the multicast membership table. ++ Used by \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_READ. */ ++typedef struct ++{ ++ /** Restart the get operation from the beginning of the table. Otherwise ++ return the next table entry (next to the entry that was returned ++ during the previous get operation). This parameter is always reset ++ during the read operation. This boolean parameter is set by the ++ calling application. */ ++ IFX_boolean_t bInitial; ++ /** Indicates that the read operation got all last valid entries of the ++ table. This boolean parameter is set by the switch API ++ when the Switch API is called after the last valid one was returned already. */ ++ IFX_boolean_t bLast; ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. ++ ++ \remarks ++ This field is used as portmap field, when the MSB bit is set. ++ In portmap mode, every value bit represents an Ethernet port. ++ LSB represents Port 0 with incrementing counting. ++ The (MSB - 1) bit represent the last port. ++ The macro \ref IFX_ETHSW_PORTMAP_FLAG_SET allows to set the MSB bit, ++ marking it as portmap variable. ++ Checking the portmap flag can be done by ++ using the \ref IFX_ETHSW_PORTMAP_FLAG_GET macro. */ ++ IFX_uint8_t nPortId; ++ /** Select the IP version of the 'uIP_Gda' and 'uIP_Gsa' fields. ++ Both fields support either IPv4 or IPv6. */ ++ IFX_ETHSW_IP_Select_t eIPVersion; ++ /** Group Destination IP address (GDA). */ ++ IFX_ETHSW_IP_t uIP_Gda; ++ /** Group Source IP address. Only used in case IGMPv3 support is enabled. */ ++ IFX_ETHSW_IP_t uIP_Gsa; ++ /** Group member filter mode. ++ This parameter is ignored when deleting a multicast membership table entry. ++ The configurations 'IFX_ETHSW_IGMP_MEMBER_EXCLUDE' ++ and 'IFX_ETHSW_IGMP_MEMBER_INCLUDE' are only supported ++ if IGMPv3 is used. */ ++ IFX_ETHSW_IGMP_MemberMode_t eModeMember; ++}IFX_ETHSW_multicastTableRead_t; ++ ++/*@}*/ /* ETHSW_IOCTL_MULTICAST */ ++ ++/** \addtogroup ETHSW_IOCTL_OAM */ ++/*@{*/ ++ ++/** Maximum version information string length. */ ++#define IFX_ETHSW_VERSION_LEN 64 ++ ++/** Maximum String Length for the Capability String. */ ++#define IFX_ETHSW_CAP_STRING_LEN 128 ++ ++/** Sets the portmap flag of a PortID variable. ++ Some Switch API commands allow to use a port index as portmap variable. ++ This requires that the MSB bit is set to indicate that this variable ++ contains a portmap, instead of a port index. ++ In portmap mode, every value bit represents an Ethernet port. ++ LSB represents Port 0 with incrementing counting. ++ The (MSB - 1) bit represent the last port. */ ++#define IFX_ETHSW_PORTMAP_FLAG_SET(varType) (1 << ( sizeof(((varType *)0)->nPortId) * 8 - 1)) ++ ++/** Checks the portmap flag of a PortID variable. ++ Some Switch API commands allow to use a port index as portmap variable. ++ This requires that the MSB bit is set to indicate that this variable ++ contains a portmap, instead of a port index. ++ In portmap mode, every value bit represents an Ethernet port. ++ LSB represents Port 0 with incrementing counting. ++ The (MSB - 1) bit represent the last port. */ ++#define IFX_ETHSW_PORTMAP_FLAG_GET(varType) (1 << ( sizeof(((varType *)0)->nPortId) * 8 - 1)) ++ ++/** Data structure used to request the Switch API and device hardware ++ version information. A zero-based index is provided to the Switch API that ++ describes the request version information. ++ Used by \ref IFX_ETHSW_VERSION_GET. */ ++typedef struct ++{ ++ /** Version ID starting with 0. */ ++ IFX_uint16_t nId; ++ /** Name or ID of the version information. */ ++ IFX_char_t cName[IFX_ETHSW_VERSION_LEN]; ++ /** Version string information. */ ++ IFX_char_t cVersion[IFX_ETHSW_VERSION_LEN]; ++}IFX_ETHSW_version_t; ++ ++/** Switch API hardware initialization mode. ++ Used by \ref IFX_ETHSW_HW_Init_t. */ ++typedef enum ++{ ++ /** Access the switch hardware to read out status and capability ++ information. Then define the basic hardware configuration to bring ++ the hardware into a pre-defined state. */ ++ IFX_ETHSW_HW_INIT_WR = 0, ++ /** Access the switch hardware to read out status and capability ++ information. Do not write any hardware configuration to the device. ++ This means that the current existing hardware configuration remains ++ unchanged. */ ++ IFX_ETHSW_HW_INIT_RO = 1, ++ /** Initialize the switch software module but do not touch the switch ++ hardware. This means that no read or write operations are done on ++ the switch hardware. Status and capability information cannot be ++ retrieved from the hardware. */ ++ IFX_ETHSW_HW_INIT_NO = 2 ++}IFX_ETHSW_HW_InitMode_t; ++ ++/** Switch hardware platform initialization structure. ++ Used by \ref IFX_ETHSW_HW_INIT. */ ++typedef struct ++{ ++ /** Select the type of Switch API and hardware initialization. */ ++ IFX_ETHSW_HW_InitMode_t eInitMode; ++}IFX_ETHSW_HW_Init_t; ++ ++/** Aging Timer Value. ++ Used by \ref IFX_ETHSW_cfg_t. */ ++typedef enum ++{ ++ /** 1 second */ ++ IFX_ETHSW_AGETIMER_1_SEC = 1, ++ /** 10 seconds */ ++ IFX_ETHSW_AGETIMER_10_SEC = 2, ++ /** 300 seconds */ ++ IFX_ETHSW_AGETIMER_300_SEC = 3, ++ /** 1 hour */ ++ IFX_ETHSW_AGETIMER_1_HOUR = 4, ++ /** 24 hours */ ++ IFX_ETHSW_AGETIMER_1_DAY = 5 ++}IFX_ETHSW_ageTimer_t; ++ ++/** Ethernet port speed mode. ++ A port might support only a subset of the possible settings. ++ Used by \ref IFX_ETHSW_portLinkCfg_t. */ ++typedef enum ++{ ++ /** 10 Mbit/s */ ++ IFX_ETHSW_PORT_SPEED_10 = 10, ++ /** 100 Mbit/s */ ++ IFX_ETHSW_PORT_SPEED_100 = 100, ++ /** 200 Mbit/s */ ++ IFX_ETHSW_PORT_SPEED_200 = 200, ++ /** 1000 Mbit/s */ ++ IFX_ETHSW_PORT_SPEED_1000 = 1000 ++}IFX_ETHSW_portSpeed_t; ++ ++/** Ethernet port duplex status. ++ Used by \ref IFX_ETHSW_portLinkCfg_t. */ ++typedef enum ++{ ++ /** Port operates in full-duplex mode */ ++ IFX_ETHSW_DUPLEX_FULL = 0, ++ /** Port operates in half-duplex mode */ ++ IFX_ETHSW_DUPLEX_HALF = 1 ++}IFX_ETHSW_portDuplex_t; ++ ++/** Force the MAC and PHY link modus. ++ Used by \ref IFX_ETHSW_portLinkCfg_t. */ ++typedef enum ++{ ++ /** Link up. Any connected LED ++ still behaves based on the real PHY status. */ ++ IFX_ETHSW_PORT_LINK_UP = 0, ++ /** Link down. */ ++ IFX_ETHSW_PORT_LINK_DOWN = 1 ++}IFX_ETHSW_portLink_t; ++ ++/** Enumeration used for phone capability types. ++ Used by \ref IFX_ETHSW_cap_t. */ ++typedef enum ++{ ++ /** Number of physical Ethernet ports. */ ++ IFX_ETHSW_CAP_TYPE_PORT = 0, ++ /** Number of virtual Ethernet ports. */ ++ IFX_ETHSW_CAP_TYPE_VIRTUAL_PORT = 1, ++ /** Size of internal packet memory [in Bytes]. */ ++ IFX_ETHSW_CAP_TYPE_BUFFER_SIZE = 2, ++ /** Buffer segment size. ++ Byte size of a segment, used to store received packet data. */ ++ IFX_ETHSW_CAP_TYPE_SEGMENT_SIZE = 3, ++ /** Number of priority queues per device. */ ++ IFX_ETHSW_CAP_TYPE_PRIORITY_QUEUE = 4, ++ /** Number of meter instances. */ ++ IFX_ETHSW_CAP_TYPE_METER = 5, ++ /** Number of rate shaper instances. */ ++ IFX_ETHSW_CAP_TYPE_RATE_SHAPER = 6, ++ /** Number of VLAN groups that can be configured on the switch hardware. */ ++ IFX_ETHSW_CAP_TYPE_VLAN_GROUP = 7, ++ /** Number of Filtering Identifiers (FIDs) */ ++ IFX_ETHSW_CAP_TYPE_FID = 8, ++ /** Number of MAC table entries */ ++ IFX_ETHSW_CAP_TYPE_MAC_TABLE_SIZE = 9, ++ /** Number of multicast level 3 hardware table entries */ ++ IFX_ETHSW_CAP_TYPE_MULTICAST_TABLE_SIZE = 10, ++ /** Number of supported PPPoE sessions. */ ++ IFX_ETHSW_CAP_TYPE_PPPOE_SESSION = 11, ++ /** Last Capability Index */ ++ IFX_ETHSW_CAP_TYPE_LAST = 12 ++} IFX_ETHSW_capType_t; ++ ++/** Capability structure. ++ Used by \ref IFX_ETHSW_CAP_GET. */ ++typedef struct ++{ ++ /** Defines the capability type, see \ref IFX_ETHSW_capType_t.*/ ++ IFX_ETHSW_capType_t nCapType; ++ /** Description of the capability. */ ++ IFX_char_t cDesc[IFX_ETHSW_CAP_STRING_LEN]; ++ /** Defines if, what or how many are available. The definition of cap ++ depends on the type, see captype. */ ++ IFX_uint32_t nCap; ++} IFX_ETHSW_cap_t; ++ ++/** Global switch configuration. ++ Used by \ref IFX_ETHSW_CFG_SET and \ref IFX_ETHSW_CFG_GET. */ ++typedef struct ++{ ++ /** MAC table aging timer. After this timer expires the MAC table ++ entry is aged out. */ ++ IFX_ETHSW_ageTimer_t eMAC_TableAgeTimer; ++ /** VLAN Awareness. The switch is VLAN unaware if this variable is disabled. ++ In this mode, no VLAN-related APIs are supported and return with an error. ++ The existing VLAN configuration is discarded when VLAN is disabled again. */ ++ IFX_boolean_t bVLAN_Aware; ++ /** Maximum Ethernet packet length. */ ++ IFX_uint16_t nMaxPacketLen; ++ /** Automatic MAC address table learning limitation consecutive action. ++ These frame addresses are not learned, but there exists control as to whether ++ the frame is still forwarded or dropped. ++ ++ - IFX_FALSE: Drop ++ - IFX_TRUE: Forward ++ */ ++ IFX_boolean_t bLearningLimitAction; ++ /** Pause frame MAC source address mode. If enabled, use the alternative ++ address specified with 'nMAC'. */ ++ IFX_boolean_t bPauseMAC_ModeSrc; ++ /** Pause frame MAC source address. */ ++ IFX_uint8_t nPauseMAC_Src[IFX_MAC_ADDRESS_LENGTH]; ++}IFX_ETHSW_cfg_t; ++ ++/** Port Enable Options. ++ Used by \ref IFX_ETHSW_portCfg_t. */ ++typedef enum ++{ ++ /** The port is disabled in both directions. */ ++ IFX_ETHSW_PORT_DISABLE = 0, ++ /** The port is enabled in both directions (ingress and egress). */ ++ IFX_ETHSW_PORT_ENABLE_RXTX = 1, ++ /** The port is enabled in the receive (ingress) direction only. */ ++ IFX_ETHSW_PORT_ENABLE_RX = 2, ++ /** The port is enabled in the transmit (egress) direction only. */ ++ IFX_ETHSW_PORT_ENABLE_TX = 3 ++}IFX_ETHSW_portEnable_t; ++ ++/** Port Mirror Options. ++ Used by \ref IFX_ETHSW_portCfg_t. */ ++typedef enum ++{ ++ /** Mirror Feature is disabled. Normal port usage. */ ++ IFX_ETHSW_PORT_MONITOR_NONE = 0, ++ /** Port Ingress packets are mirrored to the monitor port. */ ++ IFX_ETHSW_PORT_MONITOR_RX = 1, ++ /** Port Egress packets are mirrored to the monitor port. */ ++ IFX_ETHSW_PORT_MONITOR_TX = 2, ++ /** Port Ingress and Egress packets are mirrored to the monitor port. */ ++ IFX_ETHSW_PORT_MONITOR_RXTX = 3, ++ /** Packet mirroring of 'unknown VLAN violation' frames. */ ++ IFX_ETHSW_PORT_MONITOR_VLAN_UNKNOWN = 4, ++ /** Packet mirroring of 'VLAN ingress or egress membership violation' frames. */ ++ IFX_ETHSW_PORT_MONITOR_VLAN_MEMBERSHIP = 16, ++ /** Packet mirroring of 'port state violation' frames. */ ++ IFX_ETHSW_PORT_MONITOR_PORT_STATE = 32, ++ /** Packet mirroring of 'MAC learning limit violation' frames. */ ++ IFX_ETHSW_PORT_MONITOR_LEARNING_LIMIT = 64, ++ /** Packet mirroring of 'port lock violation' frames. */ ++ IFX_ETHSW_PORT_MONITOR_PORT_LOCK = 128 ++}IFX_ETHSW_portMonitor_t; ++ ++/** Ethernet flow control status. ++ Used by \ref IFX_ETHSW_portCfg_t. */ ++typedef enum ++{ ++ /** Automatic flow control mode selection through auto-negotiation. */ ++ IFX_ETHSW_FLOW_AUTO = 0, ++ /** Receive flow control only */ ++ IFX_ETHSW_FLOW_RX = 1, ++ /** Transmit flow control only */ ++ IFX_ETHSW_FLOW_TX = 2, ++ /** Receive and Transmit flow control */ ++ IFX_ETHSW_FLOW_RXTX = 3, ++ /** No flow control */ ++ IFX_ETHSW_FLOW_OFF = 4 ++}IFX_ETHSW_portFlow_t; ++ ++/** Port Configuration. ++ Used by \ref IFX_ETHSW_PORT_CFG_GET and \ref IFX_ETHSW_PORT_CFG_SET. */ ++typedef struct ++{ ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. */ ++ IFX_uint8_t nPortId; ++ /** Enable Port (ingress only, egress only, both directions, or disabled). ++ This parameter is used for Spanning Tree Protocol and 802.1X applications. */ ++ IFX_ETHSW_portEnable_t eEnable; ++ /** Drop unknown unicast packets. ++ Do not send out unknown unicast packets on this port, ++ if the boolean parameter is enabled. By default packets of this type ++ are forwarded to this port. */ ++ IFX_boolean_t bUnicastUnknownDrop; ++ /** Drop unknown multicast packets. ++ Do not send out unknown multicast packets on this port, ++ if boolean parameter is enabled. By default packets of this type ++ are forwarded to this port. */ ++ IFX_boolean_t bMulticastUnknownDrop; ++ /** Drop reserved packet types ++ (destination address from '01 80 C2 00 00 00' to ++ '01 80 C2 00 00 2F') received on this port. */ ++ IFX_boolean_t bReservedPacketDrop; ++ /** Drop Broadcast packets received on this port. By default packets of this ++ type are forwarded to this port. */ ++ IFX_boolean_t bBroadcastDrop; ++ /** Enables MAC address table aging. ++ The MAC table entries learned on this port are removed after the ++ aging time has expired. ++ The aging time is a global parameter, common to all ports. */ ++ IFX_boolean_t bAging; ++ /** Automatic MAC address table learning locking on the port specified ++ by 'nPortId'. */ ++ IFX_boolean_t bLearningMAC_PortLock; ++ /** Automatic MAC address table learning limitation on this port. ++ The learning functionality is disabled when the limit value is zero. ++ The value 0xFFFF to allow unlimited learned address. */ ++ IFX_uint16_t nLearningLimit; ++ /** Port Flow Control Status. Enables the flow control function. */ ++ IFX_ETHSW_portFlow_t eFlowCtrl; ++ /** Port monitor feature. Allows forwarding of egress and/or ingress ++ packets to the monitor port. If enabled, the monitor port gets ++ a copy of the selected packet type. */ ++ IFX_ETHSW_portMonitor_t ePortMonitor; ++}IFX_ETHSW_portCfg_t; ++ ++/** Special tag Ethertype mode */ ++typedef enum ++{ ++ /** The EtherType field of the Special Tag of egress packets is always set ++ to a prefined value. This same defined value applies for all ++ switch ports. */ ++ IFX_ETHSW_CPU_ETHTYPE_PREDEFINED = 0, ++ /** The Ethertype field of the Special Tag of egress packets is set to ++ the FlowID parameter, which is a results of the switch flow ++ classification result. The switch flow table rule provides this ++ FlowID as action parameter. */ ++ IFX_ETHSW_CPU_ETHTYPE_FLOWID = 1 ++}IFX_ETHSW_CPU_SpecialTagEthType_t; ++ ++/** Defines one port that is directly connected to the software running on a CPU. ++ Used by \ref IFX_ETHSW_CPU_PORT_CFG_SET and \ref IFX_ETHSW_CPU_PORT_CFG_GET. */ ++typedef struct ++{ ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. */ ++ IFX_uint8_t nPortId; ++ /** CPU port validity. ++ Set command: set true to define a CPU port, set false to undo the setting. ++ Get command: true if defined as CPU, false if not defined as CPU port. */ ++ IFX_boolean_t bCPU_PortValid; ++ /** Special tag enable in ingress direction. */ ++ IFX_boolean_t bSpecialTagIngress; ++ /** Special tag enable in egress direction. */ ++ IFX_boolean_t bSpecialTagEgress; ++ /** Enable FCS check ++ ++ - IFX_FALSE: No check, forward all frames ++ - IFX_TRUE: Check FCS, drop frames with errors ++ */ ++ IFX_boolean_t bFcsCheck; ++ /** Enable FCS generation ++ ++ - IFX_FALSE: Forward packets without FCS ++ - IFX_TRUE: Generate FCS for all frames ++ */ ++ IFX_boolean_t bFcsGenerate; ++ /** Special tag Ethertype mode. */ ++ IFX_ETHSW_CPU_SpecialTagEthType_t bSpecialTagEthType; ++}IFX_ETHSW_CPU_PortCfg_t; ++ ++/** Ethernet layer-2 header selector, when adding or removing on ++ transmitted packets. ++ Used by \ref IFX_ETHSW_CPU_PortExtendCfg_t. */ ++typedef enum ++{ ++ /** No additional Ethernet header. */ ++ IFX_ETHSW_CPU_HEADER_NO = 0, ++ /** Additional Ethernet header. */ ++ IFX_ETHSW_CPU_HEADER_MAC = 1, ++ /** Additional Ethernet- and VLAN- header. */ ++ IFX_ETHSW_CPU_HEADER_VLAN = 2 ++}IFX_ETHSW_CPU_HeaderMode_t; ++ ++/** CPU Port Layer-2 Header extension. ++ Used by \ref IFX_ETHSW_CPU_PortExtendCfg_t. */ ++typedef struct ++{ ++ /** Packet MAC Source Address. */ ++ IFX_uint8_t nMAC_Src[IFX_MAC_ADDRESS_LENGTH]; ++ /** Packet MAC Destination Address. */ ++ IFX_uint8_t nMAC_Dst[IFX_MAC_ADDRESS_LENGTH]; ++ /** Packet EtherType Field. */ ++ IFX_uint16_t nEthertype; ++ /** VLAN Tag Priority Field. ++ Only used when adding VLAN tag is ++ enabled (eHeaderAdd=IFX_ETHSW_CPU_HEADER_VLAN). */ ++ IFX_uint8_t nVLAN_Prio; ++ /** VLAN Tag Canonical Format Identifier. ++ Only used when adding VLAN tag is ++ enabled (eHeaderAdd=IFX_ETHSW_CPU_HEADER_VLAN). */ ++ IFX_uint8_t nVLAN_CFI; ++ /** VLAN Tag VLAN ID. ++ Only used when adding VLAN tag is ++ enabled (eHeaderAdd=IFX_ETHSW_CPU_HEADER_VLAN). */ ++ IFX_uint16_t nVLAN_ID; ++}IFX_ETHSW_CPU_Header_t; ++ ++/** CPU port PAUSE frame handling. ++ Used by \ref IFX_ETHSW_CPU_PortExtendCfg_t. */ ++typedef enum ++{ ++ /** Forward all PAUSE frames coming from the switch macro towards ++ the DMA channel. These frames do not influence the packet transmission. */ ++ IFX_ETHSW_CPU_PAUSE_FORWARD = 0, ++ /** Dispatch all PAUSE frames coming from the switch macro towards ++ the DMA channel. These are filtered out and the packets transmission is ++ stopped and restarted accordingly. */ ++ IFX_ETHSW_CPU_PAUSE_DISPATCH = 1 ++}IFX_ETHSW_CPU_Pause_t; ++ ++/** Ethernet port interface mode. ++ A port might support only a subset of the possible settings. ++ Used by \ref IFX_ETHSW_portLinkCfg_t. */ ++typedef enum ++{ ++ /** Normal PHY interface (twisted pair), use the internal MII Interface. */ ++ IFX_ETHSW_PORT_HW_MII = 0, ++ /** Reduced MII interface in normal mode. */ ++ IFX_ETHSW_PORT_HW_RMII = 1, ++ /** GMII or MII, depending upon the speed. */ ++ IFX_ETHSW_PORT_HW_GMII = 2, ++ /** RGMII mode. */ ++ IFX_ETHSW_PORT_HW_RGMII = 3 ++}IFX_ETHSW_MII_Mode_t; ++ ++/** Ethernt port configuration for PHY or MAC mode. ++ Used by \ref IFX_ETHSW_portLinkCfg_t. */ ++typedef enum ++{ ++ /** MAC Mode. The Ethernet port is configured to work in MAC mode. */ ++ IFX_ETHSW_PORT_MAC = 0, ++ /** PHY Mode. The Ethernet port is configured to work in PHY mode. */ ++ IFX_ETHSW_PORT_PHY = 1 ++}IFX_ETHSW_MII_Type_t; ++ ++/** Ethernet port clock source configuration. ++ Used by \ref IFX_ETHSW_portLinkCfg_t. */ ++typedef enum ++{ ++ /** Clock Mode not applicable. */ ++ IFX_ETHSW_PORT_CLK_NA = 0, ++ /** Clock Master Mode. The port is configured to provide the clock as output signal. */ ++ IFX_ETHSW_PORT_CLK_MASTER = 1, ++ /** Clock Slave Mode. The port is configured to use the input clock signal. */ ++ IFX_ETHSW_PORT_CLK_SLAVE = 2 ++}IFX_ETHSW_clkMode_t; ++ ++/** Additional CPU port configuration for platforms where the CPU port is ++ fixed set on a dedicated port. ++ ++ Used by \ref IFX_ETHSW_CPU_PORT_EXTEND_CFG_SET ++ and \ref IFX_ETHSW_CPU_PORT_EXTEND_CFG_GET. */ ++typedef struct ++{ ++ /** Add Ethernet layer-2 header (also VLAN) to the transmit packet. ++ The corresponding header fields are set in 'sHeader'. */ ++ IFX_ETHSW_CPU_HeaderMode_t eHeaderAdd; ++ /** Remove Ethernet layer-2 header (also VLAN) for packets going from ++ Ethernet switch to the DMA. Only the first VLAN tag found is removed ++ and additional available VLAN tags remain untouched. */ ++ IFX_boolean_t bHeaderRemove; ++ /** Ethernet layer-2 header information. Used when adding a header to the ++ transmitted packet. The parameter 'eHeaderAdd' selects the mode if ++ a layer-2 header should be added (including VLAN). ++ This structure contains all fields of the Ethernet and VLAN header. */ ++ IFX_ETHSW_CPU_Header_t sHeader; ++ /** Describes how the port handles received PAUSE frames coming from the ++ switch. Either forward them to DMA or stop/start transmission. ++ Note that the parameter 'eFlowCtrl' of the ++ command 'IFX_ETHSW_PORT_CFG_SET' determines whether the switch ++ generates PAUSE frames. */ ++ IFX_ETHSW_CPU_Pause_t ePauseCtrl; ++ /** Remove the CRC (FCS) of all packets coming from the switch towards ++ the DMA channel. ++ Note that the FCS check and generation option can be configured ++ using 'IFX_ETHSW_CPU_PORT_CFG_SET'. */ ++ IFX_boolean_t bFcsRemove; ++ /** Port map of Ethernet switch ports that are assigned to the WAN side ++ (dedicated for applications where ports are grouped into WAN- and ++ LAN- segments). All ports that are not selected belong to the LAN segment. ++ The LSB bit represents port 0, the higher bits represent the higher ++ port numbers. */ ++ IFX_uint32_t nWAN_Ports; ++}IFX_ETHSW_CPU_PortExtendCfg_t; ++ ++/** Ethernet port link, speed status and flow control status. ++ Used by \ref IFX_ETHSW_PORT_LINK_CFG_GET ++ and \ref IFX_ETHSW_PORT_LINK_CFG_SET. */ ++typedef struct ++{ ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. */ ++ IFX_uint8_t nPortId; ++ /** Force Port Duplex Mode. ++ ++ - IFX_FALSE: Negotiate Duplex Mode. Auto-negotiation mode. Negotiated ++ duplex mode given in 'eDuplex' ++ during IFX_ETHSW_PORT_LINK_CFG_GET calls. ++ - IFX_TRUE: Force Duplex Mode. Force duplex mode in 'eDuplex'. ++ */ ++ IFX_boolean_t bDuplexForce; ++ /** Port Duplex Status. */ ++ IFX_ETHSW_portDuplex_t eDuplex; ++ /** Force Link Speed. ++ ++ - IFX_FALSE: Negotiate Link Speed. Negotiated speed given in ++ 'eSpeed' during IFX_ETHSW_PORT_LINK_CFG_GET calls. ++ - IFX_TRUE: Force Link Speed. Forced speed mode in 'eSpeed'. ++ */ ++ IFX_boolean_t bSpeedForce; ++ /** Ethernet port link up/down and speed status. */ ++ IFX_ETHSW_portSpeed_t eSpeed; ++ /** Force Link. ++ ++ - IFX_FALSE: Auto-negotiate Link. Current link status is given in ++ 'eLink' during IFX_ETHSW_PORT_LINK_CFG_GET calls. ++ - IFX_TRUE: Force Duplex Mode. Force duplex mode in 'eLink'. ++ */ ++ IFX_boolean_t bLinkForce; ++ /** Link Status. Read out the current link status. ++ Note that the link could be forced by setting 'bLinkForce'. */ ++ IFX_ETHSW_portLink_t eLink; ++ /** Selected interface mode (MII/RMII/RGMII/GMII). */ ++ IFX_ETHSW_MII_Mode_t eMII_Mode; ++ /** Select MAC or PHY mode (PHY = Reverse xMII). */ ++ IFX_ETHSW_MII_Type_t eMII_Type; ++ /** Interface Clock mode (used for RMII mode). */ ++ IFX_ETHSW_clkMode_t eClkMode; ++ /** 'Low Power Idle' Support for 'Energy Efficient Ethernet'. ++ Only enable this feature in case the attached PHY also supports it. */ ++ IFX_boolean_t bLPI; ++}IFX_ETHSW_portLinkCfg_t; ++ ++/** Ethernet Interface RGMII Clock Configuration. Only needed in case the ++ interface runs in RGMII mode. ++ Used by \ref IFX_ETHSW_PORT_RGMII_CLK_CFG_SET ++ and \ref IFX_ETHSW_PORT_RGMII_CLK_CFG_GET. */ ++typedef struct ++{ ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. */ ++ IFX_uint8_t nPortId; ++ /** Clock Delay RX [multiple of 500 ps]. */ ++ IFX_uint8_t nDelayRx; ++ /** Clock Delay TX [multiple of 500 ps]. */ ++ IFX_uint8_t nDelayTx; ++}IFX_ETHSW_portRGMII_ClkCfg_t; ++ ++/** Query whether the Ethernet switch hardware has detected a connected ++ PHY on the port. ++ Used by \ref IFX_ETHSW_PORT_PHY_QUERY. */ ++typedef struct ++{ ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. */ ++ IFX_uint8_t nPortId; ++ /** Check if the Ethernet switch hardware has detected a connected PHY ++ on this port. */ ++ IFX_boolean_t bPHY_Present; ++}IFX_ETHSW_portPHY_Query_t; ++ ++/** Ethernet PHY address definition. Defines the relationship between a ++ bridge port and the MDIO address of a PHY that is attached to this port. ++ Used by \ref IFX_ETHSW_PORT_PHY_ADDR_GET. */ ++typedef struct ++{ ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. */ ++ IFX_uint8_t nPortId; ++ /** Device address on the MDIO interface */ ++ IFX_uint8_t nAddressDev; ++}IFX_ETHSW_portPHY_Addr_t; ++ ++/** Port redirection control. ++ Used by \ref IFX_ETHSW_PORT_REDIRECT_GET ++ and \ref IFX_ETHSW_PORT_REDIRECT_SET. */ ++typedef struct ++{ ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. */ ++ IFX_uint8_t nPortId; ++ /** Port Redirect Option. ++ If enabled, all packets destined to 'nPortId' are redirected to the ++ CPU port. The destination port map in the status header information is ++ not changed so that the original destination port can be identified by ++ software. */ ++ IFX_boolean_t bRedirectEgress; ++ /** Port Ingress Direct Forwarding. ++ If enabled, all packets sourced from 'nPortId' are directly forwarded to queue 0 ++ of the CPU port. These packets are not modified and are not affected by ++ normal learning, look up, VLAN processing and queue selection. */ ++ IFX_boolean_t bRedirectIngress; ++}IFX_ETHSW_portRedirectCfg_t; ++ ++/** Port monitor configuration. ++ Used by \ref IFX_ETHSW_MONITOR_PORT_CFG_GET ++ and \ref IFX_ETHSW_MONITOR_PORT_CFG_SET. */ ++typedef struct ++{ ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. */ ++ IFX_uint8_t nPortId; ++ /** This port is used as a monitor port. To use this feature, the port ++ mirror function is enabled on one or more ports. */ ++ IFX_boolean_t bMonitorPort; ++}IFX_ETHSW_monitorPortCfg_t; ++ ++/** ++ RMON Counters - Type 1. ++ This structure contains the RMON counters of one Ethernet Switch Port. ++ Used by \ref IFX_ETHSW_RMON_GET. */ ++typedef struct ++{ ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. This parameter specifies for which MAC port the RMON1 ++ counter is read. It has to be set by the application before ++ calling \ref IFX_ETHSW_RMON_GET. */ ++ IFX_uint8_t nPortId; ++ /** Receive Packet Count (only packets that are accepted and not discarded). */ ++ IFX_uint32_t nRxGoodPkts; ++ /** Receive Unicast Packet Count. */ ++ IFX_uint32_t nRxUnicastPkts; ++ /** Receive Broadcast Packet Count. */ ++ IFX_uint32_t nRxBroadcastPkts; ++ /** Receive Multicast Packet Count. */ ++ IFX_uint32_t nRxMulticastPkts; ++ /** Receive FCS Error Packet Count. */ ++ IFX_uint32_t nRxFCSErrorPkts; ++ /** Receive Undersize Good Packet Count. */ ++ IFX_uint32_t nRxUnderSizeGoodPkts; ++ /** Receive Oversize Good Packet Count. */ ++ IFX_uint32_t nRxOversizeGoodPkts; ++ /** Receive Undersize Error Packet Count. */ ++ IFX_uint32_t nRxUnderSizeErrorPkts; ++ /** Receive Good Pause Packet Count. */ ++ IFX_uint32_t nRxGoodPausePkts; ++ /** Receive Oversize Error Packet Count. */ ++ IFX_uint32_t nRxOversizeErrorPkts; ++ /** Receive Align Error Packet Count. */ ++ IFX_uint32_t nRxAlignErrorPkts; ++ /** Filtered Packet Count. */ ++ IFX_uint32_t nRxFilteredPkts; ++ /** Receive Size 64 Packet Count. */ ++ IFX_uint32_t nRx64BytePkts; ++ /** Receive Size 65-127 Packet Count. */ ++ IFX_uint32_t nRx127BytePkts; ++ /** Receive Size 128-255 Packet Count. */ ++ IFX_uint32_t nRx255BytePkts; ++ /** Receive Size 256-511 Packet Count. */ ++ IFX_uint32_t nRx511BytePkts; ++ /** Receive Size 512-1023 Packet Count. */ ++ IFX_uint32_t nRx1023BytePkts; ++ /** Receive Size 1024-1522 (or more, if configured) Packet Count. */ ++ IFX_uint32_t nRxMaxBytePkts; ++ /** Transmit Packet Count. */ ++ IFX_uint32_t nTxGoodPkts; ++ /** Transmit Unicast Packet Count. */ ++ IFX_uint32_t nTxUnicastPkts; ++ /** Transmit Broadcast Packet Count. */ ++ IFX_uint32_t nTxBroadcastPkts; ++ /** Transmit Multicast Packet Count. */ ++ IFX_uint32_t nTxMulticastPkts; ++ /** Transmit Single Collision Count. */ ++ IFX_uint32_t nTxSingleCollCount; ++ /** Transmit Multiple Collision Count. */ ++ IFX_uint32_t nTxMultCollCount; ++ /** Transmit Late Collision Count. */ ++ IFX_uint32_t nTxLateCollCount; ++ /** Transmit Excessive Collision Count. */ ++ IFX_uint32_t nTxExcessCollCount; ++ /** Transmit Collision Count. */ ++ IFX_uint32_t nTxCollCount; ++ /** Transmit Pause Packet Count. */ ++ IFX_uint32_t nTxPauseCount; ++ /** Transmit Size 64 Packet Count. */ ++ IFX_uint32_t nTx64BytePkts; ++ /** Transmit Size 65-127 Packet Count. */ ++ IFX_uint32_t nTx127BytePkts; ++ /** Transmit Size 128-255 Packet Count. */ ++ IFX_uint32_t nTx255BytePkts; ++ /** Transmit Size 256-511 Packet Count. */ ++ IFX_uint32_t nTx511BytePkts; ++ /** Transmit Size 512-1023 Packet Count. */ ++ IFX_uint32_t nTx1023BytePkts; ++ /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */ ++ IFX_uint32_t nTxMaxBytePkts; ++ /** Transmit Drop Packet Count. */ ++ IFX_uint32_t nTxDroppedPkts; ++ /** Transmit Dropped Packet Count, based on Congestion Management. */ ++ IFX_uint32_t nTxAcmDroppedPkts; ++ /** Receive Dropped Packet Count. */ ++ IFX_uint32_t nRxDroppedPkts; ++ /** Receive Good Byte Count (64 bit). */ ++ IFX_uint64_t nRxGoodBytes; ++ /** Receive Bad Byte Count (64 bit). */ ++ IFX_uint64_t nRxBadBytes; ++ /** Transmit Good Byte Count (64 bit). */ ++ IFX_uint64_t nTxGoodBytes; ++}IFX_ETHSW_RMON_cnt_t; ++ ++/** RMON Counter Clear. ++ This structure specifies on which port the RMON counter should be deleted. ++ Used by \ref IFX_ETHSW_RMON_CLEAR. */ ++typedef struct ++{ ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. */ ++ IFX_uint8_t nPortId; ++}IFX_ETHSW_RMON_clear_t; ++ ++/** MDIO Interface Configuration. ++ Used by \ref IFX_ETHSW_MDIO_CFG_GET and \ref IFX_ETHSW_MDIO_CFG_SET. */ ++typedef struct ++{ ++ /** MDIO interface clock and data rate [in kHz]. */ ++ IFX_uint32_t nMDIO_Speed; ++ /** MDIO interface enable. */ ++ IFX_boolean_t bMDIO_Enable; ++}IFX_ETHSW_MDIO_cfg_t; ++ ++/** MDIO Register Access. ++ The 'nData' value is directly written to the device register ++ or read from the device. ++ Some PHY device registers have standard bit definitions as stated in ++ IEEE 802. ++ Used by \ref IFX_ETHSW_MDIO_DATA_READ and \ref IFX_ETHSW_MDIO_DATA_WRITE. */ ++typedef struct ++{ ++ /** Device address on the MDIO interface */ ++ IFX_uint8_t nAddressDev; ++ /** Register address inside the device. */ ++ IFX_uint8_t nAddressReg; ++ /** Exchange data word with the device (read / write). */ ++ IFX_uint16_t nData; ++}IFX_ETHSW_MDIO_data_t; ++ ++/** Enumeration for function status return. The upper four bits are reserved for ++ error classification */ ++typedef enum ++{ ++ IFX_ETHSW_statusOk = 0, ++ /** Invalid function parameter */ ++ IFX_ETHSW_statusParam = -2, ++ /** No space left in VLAN table */ ++ IFX_ETHSW_statusVLAN_Space = -3, ++ /** Requested VLAN ID not found in table */ ++ IFX_ETHSW_statusVLAN_ID = -4, ++ /** Invalid ioctl */ ++ IFX_ETHSW_statusInvalIoctl = -5, ++ /** Operation not supported by hardware */ ++ IFX_ETHSW_statusNoSupport = -6, ++ /** Timeout */ ++ IFX_ETHSW_statusTimeout = -7, ++ /** At least one value is out of range */ ++ IFX_ETHSW_statusValueRange = -8, ++ /** The PortId/QueueId/etc. is not available in this hardware or the ++ selected feature is not available on this port */ ++ IFX_ETHSW_statusPortInvalid = -9, ++ /** The interrupt is not available in this hardware */ ++ IFX_ETHSW_statusIRQ_Invalid = -10, ++ /** The MAC table is full, an entry could not be added */ ++ IFX_ETHSW_statusMAC_TableFull = -11, ++ /** Generic or unknown error occurred */ ++ IFX_ETHSW_statusErr = -1 ++}IFX_ETHSW_status_t; ++ ++/** Configures the Wake-on-LAN function. ++ Used by \ref IFX_ETHSW_WOL_CFG_SET and \ref IFX_ETHSW_WOL_CFG_GET. */ ++typedef struct ++{ ++ /** WoL MAC address. */ ++ IFX_uint8_t nWolMAC[6]; ++ /** WoL password. */ ++ IFX_uint8_t nWolPassword[6]; ++ /** WoL password enable. */ ++ IFX_boolean_t bWolPasswordEnable; ++}IFX_ETHSW_WoL_Cfg_t; ++ ++/** Enables Wake-on-LAN functionality on the port. ++ Used by \ref IFX_ETHSW_WOL_PORT_CFG_SET ++ and \ref IFX_ETHSW_WOL_PORT_CFG_GET. */ ++typedef struct ++{ ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. */ ++ IFX_uint8_t nPortId; ++ /** Enable Wake-on-LAN. */ ++ IFX_boolean_t bWakeOnLAN_Enable; ++}IFX_ETHSW_WoL_PortCfg_t; ++ ++/*@}*/ /* ETHSW_IOCTL_OAM */ ++ ++/* -------------------------------------------------------------------------- */ ++/* IOCTL Command Definitions */ ++/* -------------------------------------------------------------------------- */ ++ ++/** \addtogroup ETHSW_IOCTL_BRIDGE */ ++/*@{*/ ++ ++/** ++ Read an entry of the MAC table. ++ If the parameter 'bInitial=TRUE', the GET operation starts at the beginning ++ of the table. Otherwise it continues the GET operation at the entry that ++ follows the previous access. ++ The function sets all fields to zero in case the end of the table is reached. ++ In order to read out the complete table, this function can be called in a loop. ++ The Switch API sets 'bLast=IFX_TRUE' when the last entry is read out. ++ This 'bLast' parameter could be the loop exit criteria. ++ ++ \param IFX_ETHSW_MAC_tableRead_t Pointer to a MAC table entry ++ \ref IFX_ETHSW_MAC_tableRead_t structure that is filled out by the switch ++ implementation. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_MAC_TABLE_ENTRY_READ _IOWR(IFX_ETHSW_MAGIC, 0x01, IFX_ETHSW_MAC_tableRead_t) ++ ++/** ++ Search the MAC Address table for a specific address entry. ++ A MAC address is provided by the application and Switch API ++ performs a search operation on the hardware table. ++ Many hardware platforms provide an optimized and fast address search algorithm. ++ ++ \param IFX_ETHSW_MAC_tableQuery_t Pointer to a MAC table entry ++ \ref IFX_ETHSW_MAC_tableQuery_t structure that is filled out by the switch ++ implementation. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_MAC_TABLE_ENTRY_QUERY _IOWR(IFX_ETHSW_MAGIC, 0x02, IFX_ETHSW_MAC_tableQuery_t) ++ ++/** ++ Add a MAC table entry. If an entry already exists for the given MAC Address ++ and Filtering Database (FID), this entry is overwritten. If not, ++ a new entry is added. ++ ++ \param IFX_ETHSW_MAC_tableAdd_t Pointer to a MAC table entry ++ \ref IFX_ETHSW_MAC_tableAdd_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_MAC_TABLE_ENTRY_ADD _IOW(IFX_ETHSW_MAGIC, 0x03, IFX_ETHSW_MAC_tableAdd_t) ++ ++/** ++ Remove a single MAC entry from the MAC table. ++ ++ \param IFX_ETHSW_MAC_tableRemove_t Pointer to a MAC table entry ++ \ref IFX_ETHSW_MAC_tableRemove_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_MAC_TABLE_ENTRY_REMOVE _IOW(IFX_ETHSW_MAGIC, 0x04, IFX_ETHSW_MAC_tableRemove_t) ++ ++/** ++ Remove all MAC entries from the MAC table. ++ ++ \param IFX_void_t This command does not require any parameter structure ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_MAC_TABLE_CLEAR _IO(IFX_ETHSW_MAGIC, 0x05) ++ ++/** ++ Configure the Spanning Tree Protocol state of an Ethernet port. ++ The switch supports four Spanning Tree Port states (Disable/Discarding, ++ Blocking/Listening, Learning and Forwarding state) for every port, to enable ++ the Spanning Tree Protocol function when co-operating with software on ++ the CPU port. ++ Identified Spanning Tree Protocol packets can be redirected to the CPU port. ++ Depending on the hardware implementation, the CPU port assignement is fixed ++ or can be configured using \ref IFX_ETHSW_CPU_PORT_CFG_SET. ++ The current port state can be read back ++ using \ref IFX_ETHSW_STP_PORT_CFG_GET. ++ ++ \param IFX_ETHSW_STP_portCfg_t Pointer to \ref IFX_ETHSW_STP_portCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_STP_PORT_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x06, IFX_ETHSW_STP_portCfg_t) ++ ++/** ++ Read out the current Spanning Tree Protocol state of an Ethernet port. ++ This configuration can be set using \ref IFX_ETHSW_STP_PORT_CFG_SET. ++ ++ \param IFX_ETHSW_STP_portCfg_t Pointer to \ref IFX_ETHSW_STP_portCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_STP_PORT_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x07, IFX_ETHSW_STP_portCfg_t) ++ ++/** ++ Set the Spanning Tree configuration. This configuration includes the ++ filtering of detected spanning tree packets. These packets could be ++ redirected to one dedicated port (e.g. CPU port) or they could be discarded. ++ The current configuration can be read using \ref IFX_ETHSW_STP_BPDU_RULE_GET. ++ ++ \param IFX_ETHSW_STP_BPDU_Rule_t Pointer to \ref IFX_ETHSW_STP_BPDU_Rule_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_STP_BPDU_RULE_SET _IOW(IFX_ETHSW_MAGIC, 0x08, IFX_ETHSW_STP_BPDU_Rule_t) ++ ++/** ++ Read the Spanning Tree configuration. ++ The configuration can be modified using \ref IFX_ETHSW_STP_BPDU_RULE_SET. ++ ++ \param IFX_ETHSW_STP_BPDU_Rule_t Pointer to \ref IFX_ETHSW_STP_BPDU_Rule_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_STP_BPDU_RULE_GET _IOWR(IFX_ETHSW_MAGIC, 0x09, IFX_ETHSW_STP_BPDU_Rule_t) ++ ++/** ++ Read the IEEE 802.1x filter configuration. ++ The parameters can be modified using \ref IFX_ETHSW_8021X_EAPOL_RULE_SET. ++ ++ \param IFX_ETHSW_8021X_EAPOL_Rule_t Pointer to \ref IFX_ETHSW_8021X_EAPOL_Rule_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_8021X_EAPOL_RULE_GET _IOR(IFX_ETHSW_MAGIC, 0x0A, IFX_ETHSW_8021X_EAPOL_Rule_t) ++ ++/** ++ Set the IEEE 802.1x filter rule for a dedicated port. Filtered packets can be ++ redirected to one dedicated port (e.g. CPU port). ++ The switch supports the addition of a specific packet header to the filtered packets ++ that contains information like source port, priority and so on. ++ The parameters can be read using \ref IFX_ETHSW_8021X_EAPOL_RULE_GET. ++ ++ \param IFX_ETHSW_8021X_EAPOL_Rule_t Pointer to \ref IFX_ETHSW_8021X_EAPOL_Rule_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_8021X_EAPOL_RULE_SET _IOW(IFX_ETHSW_MAGIC, 0x0B, IFX_ETHSW_8021X_EAPOL_Rule_t) ++ ++/** ++ Get the 802.1x port status for a switch port. ++ A configuration can be set using \ref IFX_ETHSW_8021X_PORT_CFG_SET ++ ++ \param IFX_ETHSW_8021X_portCfg_t Pointer to a ++ 802.1x port authorized state port ++ configuration \ref IFX_ETHSW_8021X_portCfg_t ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_8021X_PORT_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x0C, IFX_ETHSW_8021X_portCfg_t) ++ ++/** ++ Set the 802.1x port status for a switch port. ++ The port configuration can be read using \ref IFX_ETHSW_8021X_PORT_CFG_GET. ++ ++ \param IFX_ETHSW_8021X_portCfg_t Pointer to a ++ 802.1x port authorized state port ++ configuration \ref IFX_ETHSW_8021X_portCfg_t ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_8021X_PORT_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x0D, IFX_ETHSW_8021X_portCfg_t) ++ ++/*@}*/ /* ETHSW_IOCTL_BRIDGE */ ++ ++/** \addtogroup ETHSW_IOCTL_VLAN */ ++/*@{*/ ++ ++/** ++ Add VLAN ID to a reserved VLAN list. ++ The switch supports replacing the VID of received packets with the PVID of ++ the receiving port. This function adds a VID to the list of VIDs to replace. ++ All switch devices support adding VID=0, VID=1 and VID=FFF to be replaced. ++ Some devices also allow adding other VIDs to be replaced. ++ An added VID could be removed again by ++ calling \ref IFX_ETHSW_VLAN_RESERVED_REMOVE. ++ This configuration applies to the whole switch device. ++ ++ \param IFX_ETHSW_VLAN_reserved_t Pointer to ++ an \ref IFX_ETHSW_VLAN_reserved_t structure element. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_VLAN_RESERVED_ADD _IOW(IFX_ETHSW_MAGIC, 0x0E, IFX_ETHSW_VLAN_reserved_t) ++ ++/** ++ Remove VLAN ID from a reserved VLAN group list. ++ This function removes a VID replacement configuration from the switch ++ hardware. This replacement configuration replaces the VID of received ++ packets with the PVID of the receiving port. This configuration can be ++ added using \ref IFX_ETHSW_VLAN_RESERVED_ADD. ++ This configuration applies to the whole switch device. ++ ++ \param IFX_ETHSW_VLAN_reserved_t Pointer to ++ an \ref IFX_ETHSW_VLAN_reserved_t structure element. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_VLAN_RESERVED_REMOVE _IOW(IFX_ETHSW_MAGIC, 0x0F, IFX_ETHSW_VLAN_reserved_t) ++ ++/** ++ Get VLAN Port Configuration. ++ This function returns the VLAN configuration of the given Port 'nPortId'. ++ ++ \param IFX_ETHSW_VLAN_portCfg_t Pointer to an ++ \ref IFX_ETHSW_VLAN_portCfg_t structure element. Based on the parameter ++ 'nPortId', the switch API implementation fills out the remaining structure ++ elements. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_VLAN_PORT_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x10, IFX_ETHSW_VLAN_portCfg_t) ++ ++/** ++ Set VLAN Port Configuration. ++ This function sets the VLAN configuration of the given Port 'nPortId'. ++ ++ \param IFX_ETHSW_VLAN_portCfg_t Pointer to an \ref IFX_ETHSW_VLAN_portCfg_t ++ structure element. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_VLAN_PORT_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x11, IFX_ETHSW_VLAN_portCfg_t) ++ ++/** ++ Add a VLAN ID group to the active VLAN set of the ++ Ethernet switch hardware. ++ Based on this configuration, VLAN group port members can ++ be added using \ref IFX_ETHSW_VLAN_PORT_MEMBER_ADD. ++ The VLAN ID configuration can be removed again by ++ calling \ref IFX_ETHSW_VLAN_ID_DELETE. ++ ++ \param IFX_ETHSW_VLAN_IdCreate_t Pointer to ++ an \ref IFX_ETHSW_VLAN_IdCreate_t structure element. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_VLAN_ID_CREATE _IOW(IFX_ETHSW_MAGIC, 0x12, IFX_ETHSW_VLAN_IdCreate_t) ++ ++/** ++ Remove a VLAN ID group from the active VLAN set of the switch ++ hardware. The VLAN ID group was set ++ using \ref IFX_ETHSW_VLAN_ID_CREATE. A VLAN ID group can only be ++ removed when no port group members are currently configured on the hardware. ++ This VLAN ID group membership configuration is done ++ using \ref IFX_ETHSW_VLAN_PORT_MEMBER_ADD and can be ++ removed again using \ref IFX_ETHSW_VLAN_PORT_MEMBER_REMOVE. ++ ++ \param IFX_ETHSW_VLAN_IdDelete_t Pointer to an ++ \ref IFX_ETHSW_VLAN_IdDelete_t structure element. ++ ++ \remarks A VLAN ID can only be removed in case it was created by ++ \ref IFX_ETHSW_VLAN_ID_CREATE and is currently not assigned ++ to any Ethernet port (done using \ref IFX_ETHSW_VLAN_PORT_MEMBER_ADD). ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_VLAN_ID_DELETE _IOW(IFX_ETHSW_MAGIC, 0x13, IFX_ETHSW_VLAN_IdDelete_t) ++ ++/** ++ Add Ethernet port to port members of a given VLAN group. ++ The assignment can be removed using \ref IFX_ETHSW_VLAN_PORT_MEMBER_REMOVE. ++ ++ \param IFX_ETHSW_VLAN_portMemberAdd_t Pointer to ++ an \ref IFX_ETHSW_VLAN_portMemberAdd_t structure element. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_VLAN_PORT_MEMBER_ADD _IOW(IFX_ETHSW_MAGIC, 0x14, IFX_ETHSW_VLAN_portMemberAdd_t) ++ ++/** ++ Remove Ethernet port from port members of a given VLAN group. ++ This assignment was done using \ref IFX_ETHSW_VLAN_PORT_MEMBER_ADD. ++ ++ \param IFX_ETHSW_VLAN_portMemberRemove_t Pointer to ++ an \ref IFX_ETHSW_VLAN_portMemberRemove_t structure element. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_VLAN_PORT_MEMBER_REMOVE _IOW(IFX_ETHSW_MAGIC, 0x15, IFX_ETHSW_VLAN_portMemberRemove_t) ++ ++/** ++ Read out all given VLAN group port memberships. Every command call ++ returns one VLAN and port membership pair with the corresponding ++ egress traffic tag behavior. Call the command in a loop till ++ Switch API sets the 'bLast' variable to read all VLAN port memberships. ++ Please set the 'bInitial' parameter for the first call starting the ++ read operation at the beginning of the VLAN table. ++ ++ \param IFX_ETHSW_VLAN_portMemberRead_t Pointer to ++ an \ref IFX_ETHSW_VLAN_portMemberRead_t structure element. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_VLAN_PORT_MEMBER_READ _IOR(IFX_ETHSW_MAGIC, 0x16, IFX_ETHSW_VLAN_portMemberRead_t) ++ ++/** ++ Read out the FID of a given VLAN ID. ++ This VLAN ID can be added using \ref IFX_ETHSW_VLAN_ID_CREATE. ++ This function returns an error in case no valid configuration is ++ available for the given VLAN ID. ++ ++ \param IFX_ETHSW_VLAN_IdGet_t Pointer to \ref IFX_ETHSW_VLAN_IdGet_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_VLAN_ID_GET _IOWR(IFX_ETHSW_MAGIC, 0x17, IFX_ETHSW_VLAN_IdGet_t) ++ ++/*@}*/ /* ETHSW_IOCTL_VLAN */ ++ ++/** \addtogroup ETHSW_IOCTL_QOS */ ++/*@{*/ ++ ++/** ++ Configures the Ethernet port based traffic class assignment of ingress packets. ++ It is used to identify the packet priority and the related egress ++ priority queue. For DSCP, the priority to queue assignment is done ++ using \ref IFX_ETHSW_QOS_DSCP_CLASS_SET. ++ For VLAN, the priority to queue assignment is done ++ using \ref IFX_ETHSW_QOS_PCP_CLASS_SET. The current port configuration can be ++ read using \ref IFX_ETHSW_QOS_PORT_CFG_GET. ++ ++ \param IFX_ETHSW_QoS_portCfg_t Pointer to a ++ QOS port priority control configuration \ref IFX_ETHSW_QoS_portCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_PORT_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x18, IFX_ETHSW_QoS_portCfg_t) ++ ++/** ++ Read out the current Ethernet port traffic class of ingress packets. ++ It is used to identify the packet priority and the related egress ++ priority queue. The port configuration can be set ++ using \ref IFX_ETHSW_QOS_PORT_CFG_SET. ++ ++ \param IFX_ETHSW_QoS_portCfg_t Pointer to a ++ QOS port priority control configuration \ref IFX_ETHSW_QoS_portCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_PORT_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x19, IFX_ETHSW_QoS_portCfg_t) ++ ++/** ++ Initialize the QoS 64 DSCP mapping to the switch priority queues. ++ This configuration applies for the whole switch device. The table ++ configuration can be read using \ref IFX_ETHSW_QOS_DSCP_CLASS_GET. ++ ++ \param IFX_ETHSW_QoS_DSCP_ClassCfg_t Pointer to the QoS filter parameters ++ \ref IFX_ETHSW_QoS_DSCP_ClassCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_DSCP_CLASS_SET _IOW(IFX_ETHSW_MAGIC, 0x1A, IFX_ETHSW_QoS_DSCP_ClassCfg_t) ++ ++/** ++ Read out the QoS 64 DSCP mapping to the switch priority queues. ++ The table configuration can be set using \ref IFX_ETHSW_QOS_DSCP_CLASS_SET. ++ ++ \param IFX_ETHSW_QoS_DSCP_ClassCfg_t Pointer to the QoS filter parameters ++ \ref IFX_ETHSW_QoS_DSCP_ClassCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_DSCP_CLASS_GET _IOWR(IFX_ETHSW_MAGIC, 0x1B, IFX_ETHSW_QoS_DSCP_ClassCfg_t) ++ ++/** ++ Configure the PCP to traffic class mapping table. ++ This configuration applies to the entire switch device. ++ The table configuration can be read using \ref IFX_ETHSW_QOS_PCP_CLASS_GET. ++ ++ \param IFX_ETHSW_QoS_PCP_ClassCfg_t Pointer to the QoS filter parameters ++ \ref IFX_ETHSW_QoS_PCP_ClassCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_PCP_CLASS_SET _IOW(IFX_ETHSW_MAGIC, 0x1C, IFX_ETHSW_QoS_PCP_ClassCfg_t) ++ ++/** ++ Read out the PCP to traffic class mapping table. ++ The table configuration can be set using \ref IFX_ETHSW_QOS_PCP_CLASS_SET. ++ ++ \param IFX_ETHSW_QoS_PCP_ClassCfg_t Pointer to the QoS filter parameters ++ \ref IFX_ETHSW_QoS_PCP_ClassCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_PCP_CLASS_GET _IOWR(IFX_ETHSW_MAGIC, 0x1D, IFX_ETHSW_QoS_PCP_ClassCfg_t) ++ ++/** ++ Configures the DSCP to Drop Precedence assignment mapping table. ++ This mapping table is used to identify the switch internally used drop ++ precedence based on the DSCP value of the incoming packet. ++ The current mapping table configuration can be read ++ using \ref IFX_ETHSW_QOS_DSCP_DROP_PRECEDENCE_CFG_GET. ++ ++ \param IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t Pointer to the QoS ++ DSCP drop precedence parameters ++ \ref IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_DSCP_DROP_PRECEDENCE_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x1E, IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t) ++ ++/** ++ Read out the current DSCP to Drop Precedence assignment mapping table. ++ The table can be configured ++ using \ref IFX_ETHSW_QOS_DSCP_DROP_PRECEDENCE_CFG_SET. ++ ++ \param IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t Pointer to the QoS ++ DSCP drop precedence parameters ++ \ref IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_DSCP_DROP_PRECEDENCE_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x1F, IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t) ++ ++/** ++ Port Remarking Configuration. Ingress and Egress remarking options for ++ DSCP and PCP. Remarking is done either on the used traffic class or ++ the drop precedence. ++ The current configuration can be read ++ using \ref IFX_ETHSW_QOS_PORT_REMARKING_CFG_GET. ++ ++ \param IFX_ETHSW_QoS_portRemarkingCfg_t Pointer to the remarking configuration ++ \ref IFX_ETHSW_QoS_portRemarkingCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_PORT_REMARKING_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x20, IFX_ETHSW_QoS_portRemarkingCfg_t) ++ ++/** ++ Read out the Port Remarking Configuration. Ingress and Egress remarking options for ++ DSCP and PCP. Remarking is done either on the used traffic class or ++ the drop precedence. ++ The current configuration can be set ++ using \ref IFX_ETHSW_QOS_PORT_REMARKING_CFG_SET. ++ ++ \param IFX_ETHSW_QoS_portRemarkingCfg_t Pointer to the QoS filter parameters ++ \ref IFX_ETHSW_QoS_portRemarkingCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_PORT_REMARKING_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x21, IFX_ETHSW_QoS_portRemarkingCfg_t) ++ ++/** ++ Configure the traffic class to DSCP mapping table. ++ This table is global and valid for the entire switch device. ++ The table can be read using \ref IFX_ETHSW_QOS_CLASS_DSCP_GET. ++ ++ \param IFX_ETHSW_QoS_ClassDSCP_Cfg_t Pointer to the DSCP mapping parameter ++ \ref IFX_ETHSW_QoS_ClassDSCP_Cfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_CLASS_DSCP_SET _IOW(IFX_ETHSW_MAGIC, 0x22, IFX_ETHSW_QoS_ClassDSCP_Cfg_t) ++ ++/** ++ Read out the current traffic class to DSCP mapping table. ++ The table can be written using \ref IFX_ETHSW_QOS_CLASS_DSCP_SET. ++ ++ \param IFX_ETHSW_QoS_ClassDSCP_Cfg_t Pointer to the DSCP mapping parameter ++ \ref IFX_ETHSW_QoS_ClassDSCP_Cfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_CLASS_DSCP_GET _IOWR(IFX_ETHSW_MAGIC, 0x23, IFX_ETHSW_QoS_ClassDSCP_Cfg_t) ++ ++/** ++ Configure the traffic class to 802.1P (PCP) priority mapping table. ++ This table is global and valid for the entire switch device. ++ The table can be read using \ref IFX_ETHSW_QOS_CLASS_PCP_GET. ++ ++ \param IFX_ETHSW_QoS_ClassPCP_Cfg_t Pointer to the PCP priority mapping parameter ++ \ref IFX_ETHSW_QoS_ClassPCP_Cfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_CLASS_PCP_SET _IOWR(IFX_ETHSW_MAGIC, 0x24, IFX_ETHSW_QoS_ClassPCP_Cfg_t) ++ ++/** ++ Read out the current traffic class to 802.1P (PCP) priority mapping table. ++ This table is global and valid for the entire switch device. ++ The table can be written using \ref IFX_ETHSW_QOS_CLASS_PCP_SET. ++ ++ \param IFX_ETHSW_QoS_ClassPCP_Cfg_t Pointer to the PCP priority mapping parameter ++ \ref IFX_ETHSW_QoS_ClassPCP_Cfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_CLASS_PCP_GET _IOWR(IFX_ETHSW_MAGIC, 0x25, IFX_ETHSW_QoS_ClassPCP_Cfg_t) ++ ++/** This command configures a rate shaper instance with the rate and the ++ burst size. This instance can be assigned to QoS queues by ++ using \ref IFX_ETHSW_QOS_SHAPER_QUEUE_ASSIGN. ++ The total number of available rate shapers can be retrieved by the ++ capability list using \ref IFX_ETHSW_CAP_GET. ++ ++ \param IFX_ETHSW_QoS_ShaperCfg_t Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_ShaperCfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_SHAPER_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x26, IFX_ETHSW_QoS_ShaperCfg_t) ++ ++/** This command retrieves the rate and the burst size configuration of a ++ rate shaper instance. A configuration can be modified ++ using \ref IFX_ETHSW_QOS_SHAPER_CFG_SET. ++ The total number of available rate shapers can be retrieved by the ++ capability list using \ref IFX_ETHSW_CAP_GET. ++ ++ \param IFX_ETHSW_QoS_ShaperCfg_t Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_ShaperCfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_SHAPER_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x27, IFX_ETHSW_QoS_ShaperCfg_t) ++ ++/** Assign one rate shaper instance to a QoS queue. The function returns with an ++ error in case there already are too many shaper instances assigned to a queue. ++ The queue instance can be enabled and configured ++ using \ref IFX_ETHSW_QOS_SHAPER_CFG_SET. ++ To remove a rate shaper instance from a QoS queue, ++ please use \ref IFX_ETHSW_QOS_SHAPER_QUEUE_DEASSIGN. ++ The total number of available rate shaper instances can be retrieved by the ++ capability list using \ref IFX_ETHSW_CAP_GET. ++ ++ \param IFX_ETHSW_QoS_ShaperQueue_t Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_ShaperQueue_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_SHAPER_QUEUE_ASSIGN _IOW(IFX_ETHSW_MAGIC, 0x28, IFX_ETHSW_QoS_ShaperQueue_t) ++ ++/** Deassign one rate shaper instance from a QoS queue. The function returns ++ with an error in case the requested instance is not currently assigned ++ to the queue. ++ The queue instance can be enabled and configured by ++ using \ref IFX_ETHSW_QOS_SHAPER_CFG_SET. ++ To assign a rate shaper instance to a QoS queue, ++ please use \ref IFX_ETHSW_QOS_SHAPER_QUEUE_ASSIGN. ++ The total number of available rate shapers can be retrieved by the ++ capability list using \ref IFX_ETHSW_CAP_GET. ++ ++ \param IFX_ETHSW_QoS_ShaperQueue_t Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_ShaperQueue_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_SHAPER_QUEUE_DEASSIGN _IOW(IFX_ETHSW_MAGIC, 0x29, IFX_ETHSW_QoS_ShaperQueue_t) ++ ++/** Check whether a rate shaper instance is assigned to the egress queue. ++ The egress queue index is the function input parameter. ++ The switch API sets the boolean parameter 'bAssigned == IFX_TRUE' in case a ++ rate shaper is assigned and then sets 'nRateShaperId' to describe the rater ++ shaper instance. ++ The parameter 'bAssigned == IFX_FALSE' in case no rate shaper instance ++ is currently assigned to the queue instance. ++ The commands \ref IFX_ETHSW_QOS_SHAPER_QUEUE_ASSIGN allow a ++ rate shaper instance to be assigned, and \ref IFX_ETHSW_QOS_SHAPER_CFG_SET allows ++ for configuration of a shaper instance. ++ The total number of available rate shapers can be retrieved by the ++ capability list using \ref IFX_ETHSW_CAP_GET. ++ ++ \param IFX_ETHSW_QoS_ShaperQueueGet_t Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_ShaperQueueGet_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_SHAPER_QUEUE_GET _IOW(IFX_ETHSW_MAGIC, 0x2A, IFX_ETHSW_QoS_ShaperQueueGet_t) ++ ++/** Configures the global WRED drop probability profile and thresholds of the device. ++ Given parameters are rounded to the segment size of the HW platform. ++ The supported segment size is given by the capability list by ++ using \ref IFX_ETHSW_CAP_GET. ++ ++ \param IFX_ETHSW_QoS_WRED_Cfg_t Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_WRED_Cfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_WRED_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x2B, IFX_ETHSW_QoS_WRED_Cfg_t) ++ ++/** Read out the global WRED drop probability profile and thresholds of the device. ++ Given parameters are rounded to the segment size of the HW platform. ++ The supported segment size is given by the capability list by ++ using \ref IFX_ETHSW_CAP_GET. ++ ++ \param IFX_ETHSW_QoS_WRED_Cfg_t Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_WRED_Cfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_WRED_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x2C, IFX_ETHSW_QoS_WRED_Cfg_t) ++ ++/** Configures the WRED drop thresholds for a dedicated egress queue. ++ Given parameters are rounded to the segment size of the HW platform. ++ The supported segment size is given by the capability list by ++ using \ref IFX_ETHSW_CAP_GET. ++ The command \ref IFX_ETHSW_QOS_WRED_QUEUE_CFG_GET retrieves the current ++ configuration. ++ ++ \param IFX_ETHSW_QoS_WRED_QueueCfg_t Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_WRED_QueueCfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_WRED_QUEUE_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x2D, IFX_ETHSW_QoS_WRED_QueueCfg_t) ++ ++/** Read out the WRED drop thresholds for a dedicated egress queue. ++ Given parameters are rounded to the segment size of the HW platform. ++ The supported segment size is given by the capability list by ++ using \ref IFX_ETHSW_CAP_GET. ++ The configuration can be changed by ++ using \ref IFX_ETHSW_QOS_WRED_QUEUE_CFG_SET. ++ ++ \param IFX_ETHSW_QoS_WRED_QueueCfg_t Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_WRED_QueueCfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_WRED_QUEUE_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x2E, IFX_ETHSW_QoS_WRED_QueueCfg_t) ++ ++/** This command configures the parameters of a rate meter instance. ++ This instance can be assigned to an ingress/egress port by ++ using \ref IFX_ETHSW_QOS_METER_PORT_ASSIGN. It can also be used by the ++ flow classification engine. ++ The total number of available rate meters can be retrieved by the ++ capability list using \ref IFX_ETHSW_CAP_GET. ++ The current configuration of a meter instance can be retrieved ++ using \ref IFX_ETHSW_QOS_METER_CFG_GET. ++ ++ \param IFX_ETHSW_QoS_meterCfg_t Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_meterCfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_METER_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x2F, IFX_ETHSW_QoS_meterCfg_t) ++ ++/** Configure the parameters of a rate meter instance. ++ This instance can be assigned to an ingress/egress port ++ using \ref IFX_ETHSW_QOS_METER_PORT_ASSIGN. It can also be used by the ++ flow classification engine. ++ The total number of available rate meters can be retrieved by the ++ capability list using \ref IFX_ETHSW_CAP_GET. ++ The current configuration of a meter instance can be retrieved ++ using \ref IFX_ETHSW_QOS_METER_CFG_GET. ++ ++ \param IFX_ETHSW_QoS_meterCfg_t Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_meterCfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_METER_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x30, IFX_ETHSW_QoS_meterCfg_t) ++ ++/** Assign a rate meter instance to an ingress and/or egress port. ++ A maximum of two meter IDs can be assigned to one single ingress port. ++ This meter instance to port assignment can be removed ++ using \ref IFX_ETHSW_QOS_METER_PORT_DEASSIGN. A list of all available ++ assignments can be read using \ref IFX_ETHSW_QOS_METER_PORT_GET. ++ ++ \param IFX_ETHSW_QoS_meterPort_t Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_meterPort_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_METER_PORT_ASSIGN _IOW(IFX_ETHSW_MAGIC, 0x31, IFX_ETHSW_QoS_meterPort_t) ++ ++/** Deassign a rate meter instance from an ingress and/or egress port. ++ A maximum of two meter IDs can be assigned to one single ingress port. ++ The meter instance is given to the command and the port configuration is ++ returned. An instance to port assignment can be done ++ using \ref IFX_ETHSW_QOS_METER_PORT_ASSIGN. A list of all available ++ assignments can be read using \ref IFX_ETHSW_QOS_METER_PORT_GET. ++ ++ \param IFX_ETHSW_QoS_meterPort_t Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_meterPort_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_METER_PORT_DEASSIGN _IOW(IFX_ETHSW_MAGIC, 0x32, IFX_ETHSW_QoS_meterPort_t) ++ ++/** Reads out all meter instance to port assignments that are done ++ using \ref IFX_ETHSW_QOS_METER_PORT_ASSIGN. All assignments are read from an ++ internal table where every read call retrieves the next entry of the table. ++ Setting the parameter 'bInitial' starts the read operation at the beginning ++ of the table. The returned parameter 'bLast' indicates that the last ++ element of the table was returned. ++ ++ \param IFX_ETHSW_QoS_meterPortGet_t Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_meterPortGet_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_METER_PORT_GET _IOWR(IFX_ETHSW_MAGIC, 0x33, IFX_ETHSW_QoS_meterPortGet_t) ++ ++/** This command configures one meter instances for storm control. ++ These instances can be used for ingress broadcast-, multicast- and ++ unknown unicast- packets. Some platforms support addition of additional meter ++ instances for this type of packet. ++ Repeated calls of \ref IFX_ETHSW_QOS_STORM_CFG_SET allow addition of ++ additional meter instances. ++ An assignment can be retrieved using \ref IFX_ETHSW_QOS_STORM_CFG_GET. ++ Setting the broadcast, multicast and unknown unicast packets boolean switch to zero ++ deletes all metering instance assignments. ++ ++ \param IFX_ETHSW_QoS_stormCfg_t Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_stormCfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_STORM_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x34, IFX_ETHSW_QoS_stormCfg_t) ++ ++/** Reads out the current meter instance assignment for storm control. This ++ configuration can be modified using \ref IFX_ETHSW_QOS_STORM_CFG_SET. ++ ++ \param IFX_ETHSW_QoS_stormCfg_t Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_stormCfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_STORM_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x35, IFX_ETHSW_QoS_stormCfg_t) ++ ++/** This configuration decides how the egress queues, attached to a single port, ++ are scheduled to transmit the queued Ethernet packets. ++ The configuration differentiates between 'Strict Priority' and ++ 'weighted fair queuing'. This applies when multiple egress queues are ++ assigned to an Ethernet port. ++ Using the WFQ feature on a port requires the configuration of weights on all ++ given queues that are assigned to that port. ++ Strict Priority means that no dedicated weight is configured and the ++ queue can transmit following its priority status. ++ The given configuration can be read out ++ using \ref IFX_ETHSW_QOS_SCHEDULER_CFG_GET. ++ ++ \param IFX_ETHSW_QoS_schedulerCfg_t Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_schedulerCfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_SCHEDULER_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x36, IFX_ETHSW_QoS_schedulerCfg_t) ++ ++/** Read out the current scheduler configuration of a given egress port. This ++ configuration can be modified ++ using \ref IFX_ETHSW_QOS_SCHEDULER_CFG_SET. ++ ++ \param IFX_ETHSW_QoS_schedulerCfg_t Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_schedulerCfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_SCHEDULER_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x37, IFX_ETHSW_QoS_schedulerCfg_t) ++ ++/** Sets the Queue ID for one traffic class of one port. ++ The total amount of supported ports, queues and traffic classes can be ++ retrieved from the capability list using \ref IFX_ETHSW_CAP_GET. ++ Please note that the device comes along with a ++ default configuration and assignment. ++ ++ \param IFX_ETHSW_QoS_queuePort_t Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_queuePort_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_QUEUE_PORT_SET _IOW(IFX_ETHSW_MAGIC, 0x38, IFX_ETHSW_QoS_queuePort_t) ++ ++/** Read out the traffic class and port assignment done ++ using \ref IFX_ETHSW_QOS_QUEUE_PORT_SET. ++ Please note that the device comes along with a ++ default configuration and assignment. ++ ++ \param IFX_ETHSW_QoS_queuePort_t Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_queuePort_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_QOS_QUEUE_PORT_GET _IOWR(IFX_ETHSW_MAGIC, 0x39, IFX_ETHSW_QoS_queuePort_t) ++ ++/*@}*/ /* ETHSW_IOCTL_QOS */ ++ ++/** \addtogroup ETHSW_IOCTL_MULTICAST */ ++/*@{*/ ++ ++/** ++ Configure the switch multicast configuration. The currently used ++ configuration can be read using \ref IFX_ETHSW_MULTICAST_SNOOP_CFG_GET. ++ ++ \param IFX_ETHSW_multicastSnoopCfg_t Pointer to the ++ multicast configuration \ref IFX_ETHSW_multicastSnoopCfg_t. ++ ++ \remarks IGMP/MLD snooping is disabled when ++ 'eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_SNOOPFORWARD'. ++ Then all other structure parameters are unused. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_MULTICAST_SNOOP_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x3A, IFX_ETHSW_multicastSnoopCfg_t) ++ ++/** ++ Read out the current switch multicast configuration. ++ The configuration can be set using \ref IFX_ETHSW_MULTICAST_SNOOP_CFG_SET. ++ ++ \param IFX_ETHSW_multicastSnoopCfg_t Pointer to the ++ multicast configuration \ref IFX_ETHSW_multicastSnoopCfg_t. ++ ++ \remarks IGMP/MLD snooping is disabled when ++ 'eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_SNOOPFORWARD'. ++ Then all other structure parameters are unused. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_MULTICAST_SNOOP_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x3B, IFX_ETHSW_multicastSnoopCfg_t) ++ ++/** ++ Add static router port to the switch hardware multicast table. ++ These added router ports will not be removed by the router port learning aging process. ++ The router port learning is enabled over the parameter 'bLearningRouter' ++ over the \ref IFX_ETHSW_MULTICAST_SNOOP_CFG_GET command. ++ Router port learning and static added entries can both be used together. ++ In case of a sofware IGMP stack/daemon environemtn, the router port learning does ++ not have to be configured on the switch hardware. Instead the router port ++ management is handled by the IGMP stack/daemon. ++ A port can be removed using \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_REMOVE. ++ ++ \param IFX_ETHSW_multicastRouter_t Pointer to \ref IFX_ETHSW_multicastRouter_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_MULTICAST_ROUTER_PORT_ADD _IOW(IFX_ETHSW_MAGIC, 0x3C, IFX_ETHSW_multicastRouter_t) ++ ++/** ++ Remove an Ethernet router port from the switch hardware multicast table. ++ A port can be added using \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_ADD. ++ ++ \param IFX_ETHSW_multicastRouter_t Pointer to \ref IFX_ETHSW_multicastRouter_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs (e.g. Ethernet port parameter out of range) ++*/ ++#define IFX_ETHSW_MULTICAST_ROUTER_PORT_REMOVE _IOW(IFX_ETHSW_MAGIC, 0x3D, IFX_ETHSW_multicastRouter_t) ++ ++/** ++ Check if a port has been selected as a router port, either by automatic learning or by manual setting. ++ A port can be added using \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_ADD. ++ A port can be removed again using \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_REMOVE. ++ ++ \param IFX_ETHSW_multicastRouterRead_t Pointer to \ref IFX_ETHSW_multicastRouterRead_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs (e.g. Ethernet port parameter out of range) ++*/ ++#define IFX_ETHSW_MULTICAST_ROUTER_PORT_READ _IOWR(IFX_ETHSW_MAGIC, 0x3E, IFX_ETHSW_multicastRouterRead_t) ++ ++/** ++ Adds a multicast group configuration to the multicast table. ++ No new entry is added in case this multicast group already ++ exists in the table. This commands adds a host member to ++ the multicast group. ++ A member can be removed again using \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_REMOVE. ++ ++ \param IFX_ETHSW_multicastTable_t Pointer ++ to \ref IFX_ETHSW_multicastTable_t. ++ ++ \remarks The Source IP parameter is ignored in case IGMPv3 support is ++ not enabled in the hardware. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_MULTICAST_TABLE_ENTRY_ADD _IOW(IFX_ETHSW_MAGIC, 0x3F, IFX_ETHSW_multicastTable_t) ++ ++/** ++ Remove an host member from a multicast group. The multicast group entry ++ is completely removed from the multicast table in case it has no ++ host member port left. ++ Group members can be added using \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_ADD. ++ ++ \param IFX_ETHSW_multicastTable_t Pointer ++ to \ref IFX_ETHSW_multicastTable_t. ++ ++ \remarks The Source IP parameter is ignored in case IGMPv3 support is ++ not enabled in the hardware. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_MULTICAST_TABLE_ENTRY_REMOVE _IOWR(IFX_ETHSW_MAGIC, 0x40, IFX_ETHSW_multicastTable_t) ++ ++/** ++ Read out the multicast membership table that is located inside the switch ++ hardware. The 'bInitial' parameter restarts the read operation at the beginning of ++ the table. Every following \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_READ call reads out ++ the next found entry. The 'bLast' parameter is set by the switch API in case ++ the last entry of the table is reached. ++ ++ \param IFX_ETHSW_multicastTableRead_t Pointer ++ to \ref IFX_ETHSW_multicastTableRead_t. ++ ++ \remarks The 'bInitial' parameter is reset during the read operation. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_MULTICAST_TABLE_ENTRY_READ _IOWR(IFX_ETHSW_MAGIC, 0x41, IFX_ETHSW_multicastTableRead_t) ++ ++/*@}*/ /* ETHSW_IOCTL_MULTICAST */ ++ ++/** \addtogroup ETHSW_IOCTL_OAM */ ++/*@{*/ ++ ++/** Hardware Initialization. This command should be called right after the ++ Switch API software module is initialized and loaded. ++ It accesses the hardware platform, retrieving platform capabilities and ++ performing the first basic configuration. ++ ++ \param IFX_ETHSW_HW_Init_t Pointer to pre-allocated initialization structure ++ \ref IFX_ETHSW_HW_Init_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_HW_INIT _IOW(IFX_ETHSW_MAGIC, 0x42, IFX_ETHSW_HW_Init_t) ++ ++/** ++ Retrieve the version string of the currently version index. The returned ++ string format might vary between the device platforms used. This ++ means that the version information cannot be compared between different ++ device platforms. ++ All returned version information is in the form of zero-terminated character strings. ++ The returned strings are empty ('') in case the given version ++ index is out of range. ++ ++ \param IFX_ETHSW_version_t* The parameter points to a ++ \ref IFX_ETHSW_version_t structure. ++ ++ \return Returns value as follows: ++ - IFX_SUCCESS: if successful ++ - IFX_ERROR: in case of an error ++ ++ \code ++ IFX_ETHSW_version_t param; ++ IFX_int32_t fd; ++ ++ memset (¶m, 0, sizeof(IFX_ETHSW_version_t)); ++ ++ while (1) ++ { ++ if (ioctl(fd, IFX_ETHSW_VERSION_GET, (IFX_int32_t) ¶m) ++ != IFX_SUCCESS) ++ { ++ printf("ERROR: TAPI version request failed!\n); ++ return IFX_ERROR; ++ } ++ ++ if ((strlen(param.cName) == 0) || (strlen(param.cVersion) == 0)) ++ // No more version entries found ++ break; ++ ++ printf("%s version: %s", param.cName, param.cVersion); ++ param.nId++; ++ } ++ ++ return IFX_SUCCESS; ++ \endcode ++*/ ++#define IFX_ETHSW_VERSION_GET _IOWR(IFX_ETHSW_MAGIC, 0x43, IFX_ETHSW_version_t) ++ ++/** This service returns the capability referenced by the provided index ++ (zero-based counting index value). The Switch API uses the index to return ++ the capability parameter from an internal list. For instance, ++ the capability list contains information about the amount of supported ++ features like number of supported VLAN groups or MAC table entries. ++ The command returns zero-length strings ('') in case the ++ requested index number is out of range. ++ ++ \param IFX_ETHSW_cap_t Pointer to pre-allocated capability ++ list structure \ref IFX_ETHSW_cap_t. ++ The switch API implementation fills out the structure with the supported ++ features, based on the provided 'nCapType' parameter. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++ ++ \code ++ IFX_ETHSW_cap_t param; ++ IFX_int32_t fd; ++ IFX_int32_t i; ++ ++ // Open tapi file descriptor * ++ fd = open("/dev/switchapi/1", O_RDWR, 0x644); ++ ++ for (i = 0; i < IFX_ETHSW_CAP_TYPE_LAST, i++) ++ { ++ memset(¶m, 0, sizeof(param)); ++ param.nCapType = i; ++ //Get the cap list ++ if (ioctl(fd, IFX_ETHSW_CAP_GET, (IFX_int32_t) ¶m) == IFX_ERROR) ++ return IFX_ERROR; ++ ++ printf("%s: %d\n", param.cDesc, param.nCap); ++ } ++ ++ // Close open fd ++ close(fd); ++ return IFX_SUCCESS; ++ \endcode ++*/ ++#define IFX_ETHSW_CAP_GET _IOWR(IFX_ETHSW_MAGIC, 0x44, IFX_ETHSW_cap_t) ++ ++/** ++ Modify the switch configuration. ++ The configuration can be read using \ref IFX_ETHSW_CFG_GET. ++ The switch can be enabled using \ref IFX_ETHSW_ENABLE. ++ ++ \param IFX_ETHSW_cfg_t Pointer to an \ref IFX_ETHSW_cfg_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x45, IFX_ETHSW_cfg_t) ++ ++/** ++ Read the global switch configuration. ++ This configuration can be set using \ref IFX_ETHSW_CFG_SET. ++ ++ \param IFX_ETHSW_cfg_t Pointer to an \ref IFX_ETHSW_cfg_t structure. ++ The structure is filled out by the switch implementation. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x46, IFX_ETHSW_cfg_t) ++ ++/** ++ Enables the whole switch. The switch device is enabled with the default ++ configuration in case no other configuration is applied. ++ The switch can be disabled using the \ref IFX_ETHSW_DISABLE command ++ ++ \param IFX_void_t This command does not require any parameter structure ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_ENABLE _IO(IFX_ETHSW_MAGIC, 0x47) ++ ++/** ++ Disables the whole switch. ++ The switch can be enabled using the \ref IFX_ETHSW_ENABLE command ++ ++ \param IFX_void_t This command does not require any parameter structure ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_DISABLE _IO(IFX_ETHSW_MAGIC, 0x48) ++ ++/** ++ Read out the current Ethernet port configuration. ++ ++ \param IFX_ETHSW_portCfg_t Pointer to a port configuration ++ \ref IFX_ETHSW_portCfg_t structure to fill out by the driver. ++ The parameter 'nPortId' tells the driver which port parameter is requested. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_PORT_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x49, IFX_ETHSW_portCfg_t) ++ ++/** ++ Set the Ethernet port configuration. ++ ++ \param IFX_ETHSW_portCfg_t Pointer to an \ref IFX_ETHSW_portCfg_t structure ++ to configure the switch port hardware. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_PORT_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x4A, IFX_ETHSW_portCfg_t) ++ ++/** ++ Defines one port that is directly connected to the software running on a CPU. ++ This allows for the redirecting of protocol-specific packets to the CPU port and ++ special packet treatment when sent by the CPU. ++ If the CPU port cannot be set, the function returns an error code. ++ ++ \param IFX_ETHSW_CPU_PortCfg_t Pointer to ++ an \ref IFX_ETHSW_CPU_PortCfg_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_CPU_PORT_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x4B, IFX_ETHSW_CPU_PortCfg_t) ++ ++/** ++ Get the port that is directly connected to the software running on a CPU and defined as ++ CPU port. This port assignment can be set using \ref IFX_ETHSW_CPU_PORT_CFG_SET ++ if it is not fixed and defined by the switch device architecture. ++ ++ \param IFX_ETHSW_CPU_PortCfg_t Pointer to ++ an \ref IFX_ETHSW_CPU_PortCfg_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_CPU_PORT_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x4C, IFX_ETHSW_CPU_PortCfg_t) ++ ++/** ++ Configure an additional CPU port configuration. This configuration applies to ++ devices where the CPU port is fixed to one dedicated port. ++ ++ \param IFX_ETHSW_CPU_PortExtendCfg_t Pointer to ++ an \ref IFX_ETHSW_CPU_PortExtendCfg_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_CPU_PORT_EXTEND_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x4D, IFX_ETHSW_CPU_PortExtendCfg_t) ++ ++/** ++ Reads out additional CPU port configuration. This configuration applies to ++ devices where the CPU port is fixed to one dedicated port. ++ ++ \param IFX_ETHSW_CPU_PortExtendCfg_t Pointer to ++ an \ref IFX_ETHSW_CPU_PortExtendCfg_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++ ++*/ ++#define IFX_ETHSW_CPU_PORT_EXTEND_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x4E, IFX_ETHSW_CPU_PortExtendCfg_t) ++ ++/** ++ Read out the Ethernet port's speed, link status, and flow control status. ++ The information for one single port 'nPortId' is returned. ++ An error code is returned if the selected port does not exist. ++ ++ \param IFX_ETHSW_portLinkCfg_t Pointer to ++ an \ref IFX_ETHSW_portLinkCfg_t structure to read out the port status. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_PORT_LINK_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x4F, IFX_ETHSW_portLinkCfg_t) ++ ++/** ++ Set the Ethernet port link, speed status and flow control status. ++ The configuration applies to a single port 'nPortId'. ++ ++ \param IFX_ETHSW_portLinkCfg_t Pointer to ++ an \ref IFX_ETHSW_portLinkCfg_t structure to set the port configuration. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_PORT_LINK_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x50, IFX_ETHSW_portLinkCfg_t) ++ ++/** ++ Configure the RGMII clocking parameter in case the Ethernet port is configured in RGMII mode. ++ The configuration can be read by calling \ref IFX_ETHSW_PORT_RGMII_CLK_CFG_GET. ++ It applies to a single port 'nPortId'. ++ ++ \param IFX_ETHSW_portRGMII_ClkCfg_t Pointer to ++ an \ref IFX_ETHSW_portRGMII_ClkCfg_t structure to set the port configuration. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_PORT_RGMII_CLK_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x51, IFX_ETHSW_portRGMII_ClkCfg_t) ++ ++/** ++ Read the RGMII clocking parameter in case the Ethernet port is configured in RGMII mode. ++ The configuration can be set by calling \ref IFX_ETHSW_PORT_RGMII_CLK_CFG_SET. ++ It applies to a single port 'nPortId'. ++ ++ \param IFX_ETHSW_portRGMII_ClkCfg_t Pointer to ++ an \ref IFX_ETHSW_portRGMII_ClkCfg_t structure to set the port configuration. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_PORT_RGMII_CLK_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x52, IFX_ETHSW_portRGMII_ClkCfg_t) ++ ++/** ++ Check whether the Ethernet switch hardware has detected an Ethernet PHY connected ++ to the given Ethernet port 'nPortId'. ++ ++ \param IFX_ETHSW_portPHY_Query_t Pointer to ++ an \ref IFX_ETHSW_portPHY_Query_t structure to set the port configuration. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_PORT_PHY_QUERY _IOWR(IFX_ETHSW_MAGIC, 0x53, IFX_ETHSW_portPHY_Query_t) ++ ++/** ++ Read out the MDIO device address of an Ethernet PHY that is connected to ++ an Ethernet port. This device address is useful when accessing PHY ++ registers using the commands \ref IFX_ETHSW_MDIO_DATA_WRITE ++ and \ref IFX_ETHSW_MDIO_DATA_READ. ++ ++ \param IFX_ETHSW_portPHY_Addr_t Pointer to \ref IFX_ETHSW_portPHY_Addr_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_PORT_PHY_ADDR_GET _IOWR(IFX_ETHSW_MAGIC, 0x54, IFX_ETHSW_portPHY_Addr_t) ++ ++/** ++ Ingress and egress packets of one specific Ethernet port can be redirected to ++ the CPU port. The ingress and egress packet redirection can be configured ++ individually. This command reads out the current configuration of a ++ dedicated port. A new configuration can be applied ++ by calling \ref IFX_ETHSW_PORT_REDIRECT_SET. ++ ++ \param IFX_ETHSW_portRedirectCfg_t Pointer ++ to \ref IFX_ETHSW_portRedirectCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ \remarks Not all hardware platforms support this feature. The function ++ returns an error if this feature is not supported. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_PORT_REDIRECT_GET _IOWR(IFX_ETHSW_MAGIC, 0x55, IFX_ETHSW_portRedirectCfg_t) ++ ++/** ++ Select ingress and egress packets of one specific Ethernet port that can be ++ redirected to a port that is configured as the 'CPU port'. The ingress and ++ egress packet direction can be configured individually. ++ The packet filter of the original port still ++ applies to the packet (for example, MAC address learning is done for the ++ selected port and not for the CPU port). ++ On CPU port side, no additional learning, forwarding look up, ++ VLAN processing and queue selection is performed for redirected packets. ++ Depending on the hardware platform used, the CPU port has to be set in ++ advance using \ref IFX_ETHSW_CPU_PORT_CFG_SET. ++ The currently used configuration can be read ++ using \ref IFX_ETHSW_PORT_REDIRECT_GET. ++ ++ \param IFX_ETHSW_portRedirectCfg_t Pointer ++ to \ref IFX_ETHSW_portRedirectCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ \remarks Not all hardware platforms support this feature. The function ++ returns an error if this feature is not supported. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_PORT_REDIRECT_SET _IOW(IFX_ETHSW_MAGIC, 0x56, IFX_ETHSW_portRedirectCfg_t) ++ ++/** ++ Reads out the current monitor options for a ++ dedicated Ethernet port. This configuration can be set ++ using \ref IFX_ETHSW_MONITOR_PORT_CFG_SET. ++ ++ \param IFX_ETHSW_monitorPortCfg_t Pointer ++ to \ref IFX_ETHSW_monitorPortCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_MONITOR_PORT_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x57, IFX_ETHSW_monitorPortCfg_t) ++ ++/** ++ Configures the monitor options for a ++ dedicated Ethernet port. This current configuration can be read back ++ using \ref IFX_ETHSW_MONITOR_PORT_CFG_GET. ++ ++ \param IFX_ETHSW_monitorPortCfg_t Pointer ++ to \ref IFX_ETHSW_monitorPortCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_MONITOR_PORT_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x58, IFX_ETHSW_monitorPortCfg_t) ++ ++/** ++ Read out the Ethernet port statistic counter (RMON counter). ++ The zero-based 'nPortId' structure element describes the physical switch ++ port for the requested statistic information. ++ ++ \param IFX_ETHSW_RMON_cnt_t Pointer to pre-allocated ++ \ref IFX_ETHSW_RMON_cnt_t structure. The structure element 'nPortId' is ++ an input parameter that describes from which port to read the RMON counter. ++ All remaining structure elements are filled with the counter values. ++ ++ \remarks The function returns an error in case the given 'nPortId' is ++ out of range. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_RMON_GET _IOWR(IFX_ETHSW_MAGIC, 0x59, IFX_ETHSW_RMON_cnt_t) ++ ++/** ++ Clears an Ethernet port traffic statistic counter (RMON counter). ++ ++ \param IFX_ETHSW_RMON_clear_t Pointer to a pre-allocated ++ \ref IFX_ETHSW_RMON_clear_t structure. The structure element 'nPortId' is ++ an input parameter stating on which port to clear all RMON counters. ++ ++ \remarks The function returns an error in case the given 'nPortId' is ++ out of range. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_RMON_CLEAR _IOW(IFX_ETHSW_MAGIC, 0x5A, IFX_ETHSW_RMON_clear_t) ++ ++/** ++ Read the MDIO interface configuration. ++ The parameters can be modified using \ref IFX_ETHSW_MDIO_CFG_SET. ++ ++ \param IFX_ETHSW_MDIO_cfg_t Pointer to \ref IFX_ETHSW_MDIO_cfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_MDIO_CFG_GET _IOR(IFX_ETHSW_MAGIC, 0x5B, IFX_ETHSW_MDIO_cfg_t) ++ ++/** ++ Set the MDIO interface configuration. ++ The parameters can be read using \ref IFX_ETHSW_MDIO_CFG_GET. ++ The given frequency is rounded off to fitting to the hardware support. ++ \ref IFX_ETHSW_MDIO_CFG_GET will return the exact programmed (rounded) frequency value. ++ ++ \param IFX_ETHSW_MDIO_cfg_t Pointer to \ref IFX_ETHSW_MDIO_cfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_MDIO_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x5C, IFX_ETHSW_MDIO_cfg_t) ++ ++/** ++ Read data from the MDIO Interface of the switch device. This function allows ++ various kinds of information to be read out for any attached device by register and ++ device addressing. ++ The 'nData' value (\ref IFX_ETHSW_MDIO_data_t) contains the read ++ device register. ++ A write operation can be done using \ref IFX_ETHSW_MDIO_DATA_WRITE. ++ ++ \param IFX_ETHSW_MDIO_data_t Pointer to \ref IFX_ETHSW_MDIO_data_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_MDIO_DATA_READ _IOWR(IFX_ETHSW_MAGIC, 0x5D, IFX_ETHSW_MDIO_data_t) ++ ++/** ++ Write data to the MDIO Interface of the switch device. This function allows ++ for configuration of any attached device by register and device addressing. ++ This applies to external and internal Ethernet PHYs as well. ++ The 'nData' value (\ref IFX_ETHSW_MDIO_data_t) is directly written to the ++ device register. ++ A read operation can be performed using \ref IFX_ETHSW_MDIO_DATA_READ. ++ ++ \param IFX_ETHSW_MDIO_data_t Pointer to \ref IFX_ETHSW_MDIO_data_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++ ++ \code ++ IFX_ETHSW_MDIO_data_t phy; ++ ++ // access the device 2 ++ phy.nAddressDev = 2; ++ // PHY register 0 ++ phy.nAddressReg = 0; ++ // copy the helper PHY register union to the data field to configure ++ phy.nData = 0x1235; ++ ++ if (ioctl(fd, IFX_ETHSW_MDIO_DATA_WRITE, (int)&phy)) ++ return IFX_ERROR; ++ ++ // access the device 5 ++ phy.nAddressDev = 5; ++ // Device specific register 20 ++ phy.nAddressReg = 20; ++ // set the data field to configure ++ phy.nData = 0x1234; ++ ++ if (ioctl(fd, IFX_ETHSW_MDIO_DATA_WRITE, (int)&phy)) ++ return IFX_ERROR; ++ ++ return IFX_SUCCESS; ++ \endcode ++*/ ++#define IFX_ETHSW_MDIO_DATA_WRITE _IOW(IFX_ETHSW_MAGIC, 0x5E, IFX_ETHSW_MDIO_data_t) ++ ++/** ++ Set the Wake-on-LAN configuration. ++ The parameters can be read using \ref IFX_ETHSW_WOL_CFG_GET. ++ ++ \param IFX_ETHSW_WoL_Cfg_t Pointer to \ref IFX_ETHSW_WoL_Cfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_WOL_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x5F, IFX_ETHSW_WoL_Cfg_t) ++ ++/** ++ Read the Wake-on-LAN configuration. ++ The parameters can be modified using \ref IFX_ETHSW_WOL_CFG_SET. ++ ++ \param IFX_ETHSW_WoL_Cfg_t Pointer to \ref IFX_ETHSW_WoL_Cfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_WOL_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x60, IFX_ETHSW_WoL_Cfg_t) ++ ++/** ++ Set the current Wake-On-LAN status for a dedicated port. The ++ Wake-On-LAN specific parameter can be configured ++ using \ref IFX_ETHSW_WOL_CFG_SET. ++ ++ \param IFX_ETHSW_WoL_PortCfg_t Pointer to \ref IFX_ETHSW_WoL_PortCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_WOL_PORT_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x61, IFX_ETHSW_WoL_PortCfg_t) ++ ++/** ++ Read out the current status of the Wake-On-LAN feature ++ on a dedicated port. This status can be changed ++ using \ref IFX_ETHSW_WOL_PORT_CFG_SET. ++ The Wake-On-LAN specific parameter can be configured ++ using \ref IFX_ETHSW_WOL_CFG_SET. ++ ++ \param IFX_ETHSW_WoL_PortCfg_t Pointer to \ref IFX_ETHSW_WoL_PortCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_ETHSW_WOL_PORT_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x62, IFX_ETHSW_WoL_PortCfg_t) ++ ++/*@}*/ /* ETHSW_IOCTL_OAM */ ++ ++#endif /* _IFX_ETHSW_H_ */ +diff --git a/include/switch_api/ifx_ethsw_PSB6970.h b/include/switch_api/ifx_ethsw_PSB6970.h +new file mode 100644 +index 0000000..766334d +--- /dev/null ++++ b/include/switch_api/ifx_ethsw_PSB6970.h +@@ -0,0 +1,647 @@ ++/**************************************************************************** ++ ++ Copyright 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++*****************************************************************************/ ++#ifndef _IFX_ETHSW_PSB6970_H_ ++#define _IFX_ETHSW_PSB6970_H_ ++ ++#include "ifx_types.h" ++ ++/* =================================== */ ++/* Global typedef forward declarations */ ++/* =================================== */ ++ ++/* ============================= */ ++/* Local Macros & Definitions */ ++/* ============================= */ ++ ++/* IOCTL MAGIC */ ++#define IFX_PSB6970_MAGIC ('P') ++ ++/* Group definitions for Doxygen */ ++/** \defgroup PSB6970_IOCTL XWAY-ARX100 / XWAY TANTOS-xG Family Specific Ethernet Switch API ++ This chapter describes the XWAY ARX100 Family, XWAY TANTOS-0G, ++ XWAY TANTOS-2G and XWAY TANTOS-3G specific interfaces for accessing and ++ configuring the services of the Ethernet switch module. */ ++/*@{*/ ++/** \defgroup PSB6970_IOCTL_DEBUG Debug Features ++ XWAY TANTOS specific features for system integration and debug sessions. ++*/ ++/** \defgroup PSB6970_IOCTL_OAM Operation, Administration, and Management Functions ++ This chapter summarizes the functions that are provided to monitor the ++ data traffic passing through the device. ++*/ ++/** \defgroup PSB6970_IOCTL_POWER Power Management ++ Configure the XWAY TANTOS hardware specific power management. ++*/ ++/** \defgroup PSB6970_IOCTL_QOS Quality of Service Functions ++ Switch and port configuration for QoS. ++*/ ++/*@}*/ ++ ++/** \addtogroup PSB6970_IOCTL_OAM */ ++/*@{*/ ++ ++/** Reset selection. ++ Used by \ref IFX_PSB6970_reset_t. */ ++typedef enum ++{ ++ /** On-chip Ethernet PHY reset */ ++ IFX_PSB6970_RESET_EPHY = 0 ++}IFX_PSB6970_resetMode_t; ++ ++/** Reset selection. ++ Used by \ref IFX_PSB6970_RESET. */ ++typedef struct ++{ ++ /** Reset selection. */ ++ IFX_PSB6970_resetMode_t eReset; ++}IFX_PSB6970_reset_t; ++ ++/*@}*/ /* PSB6970_IOCTL_OAM */ ++ ++/** \addtogroup PSB6970_IOCTL_QOS */ ++/*@{*/ ++ ++/** WFQ Algorithm Selector per port. ++ Used by \ref IFX_PSB6970_QoS_portShaperCfg_t. */ ++typedef enum ++{ ++ /** Weight. WFQ instances are configured to assign a weight (ratio) to a queue instance. ++ All WFQ egress queues are configured using a ratio. */ ++ IFX_PSB6970_QoS_WFQ_WEIGHT = 0, ++ /** Rate. WFQ instances are configured to limit the egress traffic to a configured rate. */ ++ IFX_PSB6970_QoS_WFQ_RATE = 1 ++}IFX_PSB6970_QoS_WFQ_t; ++ ++/** Port-specific QoS configuration. ++ Used by \ref IFX_PSB6970_QOS_PORT_SHAPER_CFG_SET ++ and \ref IFX_PSB6970_QOS_PORT_SHAPER_CFG_GET. */ ++typedef struct ++{ ++ /** Port index. */ ++ IFX_uint32_t nPort; ++ /** WFQ Algorithm. Selection between ratio behavior ++ and rate limitation. */ ++ IFX_PSB6970_QoS_WFQ_t eWFQ_Type; ++}IFX_PSB6970_QoS_portShaperCfg_t; ++ ++/** Port-specific configuration for the priority queue rate shaper. ++ Used by \ref IFX_PSB6970_QOS_PORT_SHAPER_STRICT_SET ++ and \ref IFX_PSB6970_QOS_PORT_SHAPER_STRICT_GET. */ ++typedef struct ++{ ++ /** Port index. */ ++ IFX_uint32_t nPort; ++ /** Priority queue index (counting from zero). */ ++ IFX_uint8_t nTrafficClass; ++ /** Maximum average rate [in Mbit/s]. */ ++ IFX_uint32_t nRate; ++}IFX_PSB6970_QoS_portShaperStrictCfg_t; ++ ++/** Port-specific configuration for the weight fair queuing rate shaper. ++ The egress queues could be scheduled by assigned weights, ++ or the traffic limited by configured rate shapers. ++ The \ref IFX_PSB6970_QOS_PORT_SHAPER_CFG_SET command configures ++ the queues to work in weight or rate shaper mode. ++ Used by \ref IFX_PSB6970_QOS_PORT_SHAPER_WFQ_SET ++ and \ref IFX_PSB6970_QOS_PORT_SHAPER_WFQ_GET. */ ++typedef struct ++{ ++ /** Port index. */ ++ IFX_uint32_t nPort; ++ /** Priority queue index (counting from zero). */ ++ IFX_uint8_t nTrafficClass; ++ /** Rate / Weight. ++ ++ - Weight: Maximum average rate [in ratio], in case eWFQ_Type=IFX_PSB6970_QoS_WFQ_WEIGHT. ++ - Rate: Maximum average rate [in Mbit/s], in case eWFQ_Type=IFX_PSB6970_QoS_WFQ_RATE. ++ */ ++ IFX_uint32_t nRate; ++}IFX_PSB6970_QoS_portShaperWFQ_Cfg_t; ++ ++/** Port-specific configuration for the ingress rate policing. ++ Used by \ref IFX_PSB6970_QOS_PORT_POLICER_SET ++ and \ref IFX_PSB6970_QOS_PORT_POLICER_GET. */ ++typedef struct ++{ ++ /** Port index. */ ++ IFX_uint32_t nPort; ++ /** Maximum average rate [in Mbit/s]. */ ++ IFX_uint32_t nRate; ++}IFX_PSB6970_QoS_portPolicerCfg_t; ++ ++/** Qos storm control for egress packets. Different packet types can be ++ discarded if the egress packet rate reaches a defined threshold. ++ Used by \ref IFX_PSB6970_QOS_STORM_SET and \ref IFX_PSB6970_QOS_STORM_GET. */ ++typedef struct ++{ ++ /** Storm control for received boardcast packets. */ ++ IFX_boolean_t bBroadcast; ++ /** Storm control for received multicast packets. */ ++ IFX_boolean_t bMulticast; ++ /** Storm control for received unicasst packets. */ ++ IFX_boolean_t bUnicast; ++ /** 10 Mbit/s link threshold [in Mbit/s] for the storm control to discard. */ ++ IFX_uint32_t nThreshold10M; ++ /** 100 Mbit/s link threshold [in Mbit/s] for the storm control ++ to discard. */ ++ IFX_uint32_t nThreshold100M; ++}IFX_PSB6970_QoS_stormCfg_t; ++ ++/** Multi-Field priority classification fields. ++ Used by \ref IFX_PSB6970_QoS_MfcMatchField_t. */ ++typedef enum ++{ ++ /** UDP/TCP Source Port Filter. */ ++ IFX_PSB6970_QOS_MF_SRCPORT = 1, ++ /** UDP/TCP Destination Port Filter. */ ++ IFX_PSB6970_QOS_MF_DSTPORT = 2, ++ /** IP Protocol Filter. */ ++ IFX_PSB6970_QOS_MF_PROTOCOL = 4, ++ /** Ethertype Filter. */ ++ IFX_PSB6970_QOS_MF_ETHERTYPE = 8 ++}IFX_PSB6970_QoS_MfPrioClassfields_t; ++ ++/** Qos multi-field priority classification configuration for Ethernet ports. ++ Used by \ref IFX_PSB6970_QOS_MFC_PORT_CFG_SET ++ and \ref IFX_PSB6970_QOS_MFC_PORT_CFG_GET. */ ++typedef struct ++{ ++ /** Port index. */ ++ IFX_uint32_t nPort; ++ /** Use the UDP/TCP Port MFC priority classification rules to assign the ++ traffic class for ingress packets that match against a rule. */ ++ IFX_boolean_t bPriorityPort; ++ /** Use the EtherType MFC priority classification rules to assign the ++ traffic class for ingress packets that match against a rule. */ ++ IFX_boolean_t bPriorityEtherType; ++}IFX_PSB6970_QoS_MfcPortCfg_t; ++ ++/** QoS multi-field priority classification match fields structure. ++ Used by \ref IFX_PSB6970_QoS_MfcCfg_t and \ref IFX_PSB6970_QOS_MFC_DEL. */ ++typedef struct ++{ ++ /** Source port base. */ ++ IFX_uint16_t nPortSrc; ++ /** Destination port base */ ++ IFX_uint16_t nPortDst; ++ /** Check from nPortSrc till smaller nPortSrc + nPortSrcRange. */ ++ IFX_uint16_t nPortSrcRange; ++ /** Check from nPortDst till smaller nPortDst + nPortDstRange. */ ++ IFX_uint16_t nPortDstRange; ++ /** Protocol type. */ ++ IFX_uint8_t nProtocol; ++ /** Ether type. */ ++ IFX_uint16_t nEtherType; ++ /** Select the filtering field.*/ ++ IFX_PSB6970_QoS_MfPrioClassfields_t eFieldSelection; ++}IFX_PSB6970_QoS_MfcMatchField_t; ++ ++/** QoS multi-field priority classification info structure. ++ Used by \ref IFX_PSB6970_QoS_MfcCfg_t. */ ++typedef struct ++{ ++ /** Egress priority queue priority queues, Q3 > Q2 > Q1 > Q0. ++ The queue index starts counting from zero. */ ++ IFX_uint8_t nTrafficClass; ++ /** Output port selection. */ ++ IFX_ETHSW_portForward_t ePortForward; ++}IFX_PSB6970_QoS_MfcInfo_t; ++ ++/** QoS multi-field priority classification rule config structure. ++ Used by \ref IFX_PSB6970_QoS_MfcEntryRead_t and \ref IFX_PSB6970_QOS_MFC_ADD. */ ++typedef struct ++{ ++ /** Match fields. */ ++ IFX_PSB6970_QoS_MfcMatchField_t sFilterMatchField; ++ /** Filter info. */ ++ IFX_PSB6970_QoS_MfcInfo_t sFilterInfo; ++}IFX_PSB6970_QoS_MfcCfg_t; ++ ++/** QoS multi-field priority classification rule get all structure. ++ Used by \ref IFX_PSB6970_QOS_MFC_ENTRY_READ. */ ++typedef struct ++{ ++ /** Restart the get operation from the beginning of the table. Otherwise ++ return the next table entry (next to the entry that was returned ++ during the previous get operation). This boolean parameter is set by the ++ calling application. */ ++ IFX_boolean_t bInitial; ++ /** Indicates that the read operation has reached the last valid entry in the ++ table. This boolean parameter is set by the switch API. */ ++ IFX_boolean_t bLast; ++ /** This filter is filled out by the switch API. */ ++ IFX_PSB6970_QoS_MfcCfg_t sFilter; ++}IFX_PSB6970_QoS_MfcEntryRead_t; ++ ++/*@}*/ /* PSB6970_IOCTL_QOS */ ++ ++/** \addtogroup PSB6970_IOCTL_POWER */ ++/*@{*/ ++ ++/** Parameter structure for configuring the power management. ++ Used by \ref IFX_PSB6970_POWER_MANAGEMENT_SET ++ and \ref IFX_PSB6970_POWER_MANAGEMENT_GET. */ ++typedef struct ++{ ++ /** Enable/disable power management on this switch device instance. */ ++ IFX_boolean_t bEnable; ++}IFX_PSB6970_powerManagement_t; ++ ++/*@}*/ /* PSB6970_IOCTL_POWER */ ++ ++/** \addtogroup PSB6970_IOCTL_DEBUG */ ++/*@{*/ ++ ++/** Register access parameter to directly read or write switch ++ internal registers. ++ Used by \ref IFX_PSB6970_REGISTER_SET and \ref IFX_PSB6970_REGISTER_GET. */ ++typedef struct ++{ ++ /** Register Address Offset for read or write access. */ ++ IFX_uint32_t nRegAddr; ++ /** Value to write to or read from 'nRegAddr'. */ ++ IFX_uint32_t nData; ++}IFX_PSB6970_register_t; ++ ++/*@}*/ /* PSB6970_IOCTL_DEBUG */ ++ ++/* ------------------------------------------------------------------------- */ ++/* IOCTL Command Definitions */ ++/* ------------------------------------------------------------------------- */ ++ ++/** \addtogroup PSB6970_IOCTL_OAM */ ++/*@{*/ ++ ++/** ++ Forces a hardware reset of the switch device or switch macro. The device ++ automatically comes back out of reset and contains the initial values. ++ All previous configurations are lost. ++ ++ \param IFX_PSB6970_reset_t Pointer to an \ref IFX_PSB6970_reset_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++ ++ \remarks Not supported for all devices ++*/ ++#define IFX_PSB6970_RESET _IOW(IFX_PSB6970_MAGIC, 0x01, IFX_PSB6970_reset_t) ++ ++/*@}*/ /* PSB6970_IOCTL_OAM */ ++ ++/** \addtogroup PSB6970_IOCTL_QOS */ ++/*@{*/ ++ ++/** ++ Configures the QoS rate shaper for the Ethernet port egress strict priority queues. ++ The current configuration can be ++ retrieved using \ref IFX_PSB6970_QOS_PORT_SHAPER_CFG_GET. ++ ++ \param IFX_PSB6970_QoS_portShaperCfg_t Pointer to the rate ++ shaping parameter \ref IFX_PSB6970_QoS_portShaperCfg_t for ++ the port-specific priority queue. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_PSB6970_QOS_PORT_SHAPER_CFG_SET _IOW(IFX_PSB6970_MAGIC, 0x02, IFX_PSB6970_QoS_portShaperCfg_t) ++ ++/** ++ Reads out the current rate shaper for the Ethernet port egress strict priority queues. ++ The configuration can be set using \ref IFX_PSB6970_QOS_PORT_SHAPER_CFG_SET. ++ ++ \param IFX_PSB6970_QoS_portShaperCfg_t Pointer to the rate ++ shaping parameter \ref IFX_PSB6970_QoS_portShaperCfg_t for ++ the port-specific priority queue. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_PSB6970_QOS_PORT_SHAPER_CFG_GET _IOWR(IFX_PSB6970_MAGIC, 0x03, IFX_PSB6970_QoS_portShaperCfg_t) ++ ++/** ++ Configures the rate shaper for the Ethernet port egress strict priority queues. ++ The current configuration can be ++ retrieved using \ref IFX_PSB6970_QOS_PORT_SHAPER_STRICT_GET. ++ ++ \param IFX_PSB6970_QoS_portShaperStrictCfg_t Pointer to the rate ++ shaping parameter \ref IFX_PSB6970_QoS_portShaperStrictCfg_t for ++ the port-specific priority queue. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_PSB6970_QOS_PORT_SHAPER_STRICT_SET _IOW(IFX_PSB6970_MAGIC, 0x04, IFX_PSB6970_QoS_portShaperStrictCfg_t) ++ ++/** ++ Reads out the current rate shaper for the Ethernet port egress strict priority queues. ++ The configuration can be set using \ref IFX_PSB6970_QOS_PORT_SHAPER_STRICT_SET. ++ ++ \param IFX_PSB6970_QoS_portShaperStrictCfg_t Pointer to the rate ++ shaping parameter \ref IFX_PSB6970_QoS_portShaperStrictCfg_t for ++ the port-specific priority queue. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_PSB6970_QOS_PORT_SHAPER_STRICT_GET _IOWR(IFX_PSB6970_MAGIC, 0x05, IFX_PSB6970_QoS_portShaperStrictCfg_t) ++ ++/** ++ Configures the rate shaper for the Ethernet port egress WFQ priority queues. ++ The current configuration can be ++ retrieved using \ref IFX_PSB6970_QOS_PORT_SHAPER_WFQ_GET. ++ ++ \param IFX_PSB6970_QoS_portShaperWFQ_Cfg_t Pointer to the rate ++ shaping parameter \ref IFX_PSB6970_QoS_portShaperWFQ_Cfg_t for ++ the port-specific priority queue. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_PSB6970_QOS_PORT_SHAPER_WFQ_SET _IOW(IFX_PSB6970_MAGIC, 0x06, IFX_PSB6970_QoS_portShaperWFQ_Cfg_t) ++ ++/** ++ Reads out the current rate shaper for the Ethernet port egress WFQ priority queues. ++ The configuration can be set using \ref IFX_PSB6970_QOS_PORT_SHAPER_WFQ_SET. ++ ++ \param IFX_PSB6970_QoS_portShaperWFQ_Cfg_t Pointer to the rate ++ shaping parameter \ref IFX_PSB6970_QoS_portShaperWFQ_Cfg_t for ++ the port-specific priority queue. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_PSB6970_QOS_PORT_SHAPER_WFQ_GET _IOWR(IFX_PSB6970_MAGIC, 0x07, IFX_PSB6970_QoS_portShaperWFQ_Cfg_t) ++ ++/** ++ Configures the Ethernet port rate policing for the ingress packets. ++ The current configuration can be ++ retrieved using \ref IFX_PSB6970_QOS_PORT_POLICER_GET. ++ ++ \param IFX_PSB6970_QoS_portPolicerCfg_t Pointer to the rate ++ policing parameter \ref IFX_PSB6970_QoS_portPolicerCfg_t for ++ the port. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_PSB6970_QOS_PORT_POLICER_SET _IOW(IFX_PSB6970_MAGIC, 0x08, IFX_PSB6970_QoS_portPolicerCfg_t) ++ ++/** ++ Read out the Ethernet port rate policing for the ingress packets. ++ The configuration can be set using \ref IFX_PSB6970_QOS_PORT_POLICER_SET. ++ ++ \param IFX_PSB6970_QoS_portPolicerCfg_t Pointer to the rate ++ policing parameter \ref IFX_PSB6970_QoS_portPolicerCfg_t for ++ the port. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_PSB6970_QOS_PORT_POLICER_GET _IOWR(IFX_PSB6970_MAGIC, 0x09, IFX_PSB6970_QoS_portPolicerCfg_t) ++ ++/** ++ Configure and apply the QoS Multi-field priority classification rules on ++ Ethernet port level. ++ ++ \param IFX_PSB6970_QoS_MfcPortCfg_t Pointer to a QOS Multi-field ++ classification rule \ref IFX_PSB6970_QoS_MfcPortCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_PSB6970_QOS_MFC_PORT_CFG_SET _IOW(IFX_PSB6970_MAGIC, 0x0A, IFX_PSB6970_QoS_MfcPortCfg_t) ++ ++/** ++ Read out the current status and configuration of the Ethernet port ++ level usage of the QoS Multi-field priority classification rules. ++ ++ \param IFX_PSB6970_QoS_MfcPortCfg_t Pointer to a QOS Multi-field ++ classification rule \ref IFX_PSB6970_QoS_MfcPortCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_PSB6970_QOS_MFC_PORT_CFG_GET _IOWR(IFX_PSB6970_MAGIC, 0x0B, IFX_PSB6970_QoS_MfcPortCfg_t) ++ ++/** ++ Set a QoS Multi-field priority classification rule. ++ ++ \param IFX_PSB6970_QoS_MfcCfg_t Pointer to a QOS Multi-field ++ classification rule \ref IFX_PSB6970_QoS_MfcCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_PSB6970_QOS_MFC_ADD _IOW(IFX_PSB6970_MAGIC, 0x0C, IFX_PSB6970_QoS_MfcCfg_t) ++ ++/** ++ Remove a QoS Multi-field priority classification rule. ++ ++ \param IFX_PSB6970_QoS_MfcMatchField_t Pointer to a ++ QOS Multi-field classification rule \ref IFX_PSB6970_QoS_MfcMatchField_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_PSB6970_QOS_MFC_DEL _IOW(IFX_PSB6970_MAGIC, 0x0D, IFX_PSB6970_QoS_MfcMatchField_t) ++ ++/** ++ Read an entry of the QoS Multi-field priority classification rules. ++ ++ If the parameter 'bInitial=TRUE', the GET operation starts at the beginning ++ of the rule set. Otherwise it continues at the entry that ++ follows the previous rule. ++ The function sets all fields to zero in case the end of the rule set has been reached. ++ To read out the complete rule set, this function can be called in a loop. ++ The Switch API sets 'bLast=IFX_TRUE' when the last entry has been read out. ++ This 'bLast' parameter could be the loop exit criteria. ++ ++ \param IFX_PSB6970_QoS_MfcEntryRead_t Pointer to a ++ QOS Multi-field classification rule \ref IFX_PSB6970_QoS_MfcEntryRead_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_PSB6970_QOS_MFC_ENTRY_READ _IOWR(IFX_PSB6970_MAGIC, 0x0E, IFX_PSB6970_QoS_MfcEntryRead_t) ++ ++/** ++ Set the egress storm control for different packet types. ++ It allows configuration of different threshold values for different link types. ++ The current configuration can be read out using \ref IFX_PSB6970_QOS_STORM_GET. ++ ++ \param IFX_PSB6970_QoS_stormCfg_t Pointer to a ++ QOS storm control configuration \ref IFX_PSB6970_QoS_stormCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_PSB6970_QOS_STORM_SET _IOW(IFX_PSB6970_MAGIC, 0x0F, IFX_PSB6970_QoS_stormCfg_t) ++ ++/** ++ Read out the current configuration for the egress storm control. ++ The storm control is used for different packet types. ++ The configuration can be set using \ref IFX_PSB6970_QOS_STORM_SET. ++ ++ \param IFX_PSB6970_QoS_stormCfg_t Pointer to a ++ QOS storm control configuration \ref IFX_PSB6970_QoS_stormCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_PSB6970_QOS_STORM_GET _IOWR(IFX_PSB6970_MAGIC, 0x10, IFX_PSB6970_QoS_stormCfg_t) ++ ++/*@}*/ /* PSB6970_IOCTL_QOS */ ++ ++/** \addtogroup PSB6970_IOCTL_POWER */ ++/*@{*/ ++ ++/** ++ Set the power management configuration. ++ The parameters can be read using \ref IFX_PSB6970_POWER_MANAGEMENT_GET. ++ ++ \param IFX_PSB6970_powerManagement_t Pointer to \ref IFX_PSB6970_powerManagement_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_PSB6970_POWER_MANAGEMENT_SET _IOW(IFX_PSB6970_MAGIC, 0x11, IFX_PSB6970_powerManagement_t) ++ ++/** ++ Read the power management configuration. ++ The parameters can be modified using \ref IFX_PSB6970_POWER_MANAGEMENT_SET. ++ ++ \param IFX_PSB6970_powerManagement_t Pointer to \ref IFX_PSB6970_powerManagement_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_PSB6970_POWER_MANAGEMENT_GET _IOWR(IFX_PSB6970_MAGIC, 0x12, IFX_PSB6970_powerManagement_t) ++ ++/*@}*/ /* PSB6970_IOCTL_POWER */ ++ ++/** \addtogroup PSB6970_IOCTL_DEBUG */ ++/*@{*/ ++ ++/** ++ Write to an internal register. The register offset defines which register to access ++ in which table. This routine only accesses the M4599_PDI and ++ the ETHSW_PDI of the switch. All PHY registers are accessed ++ via \ref IFX_ETHSW_MDIO_DATA_WRITE and \ref IFX_ETHSW_MDIO_DATA_READ. ++ Note that the switch API implementation checks that the given address is ++ inside the valid address range. It returns with an error in case an invalid ++ address is given. ++ ++ \param IFX_PSB6970_register_t Pointer to \ref IFX_PSB6970_register_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_PSB6970_REGISTER_SET _IOW(IFX_PSB6970_MAGIC, 0x13, IFX_PSB6970_register_t) ++ ++/** ++ Read an internal register. The register offset defines which register to access ++ in which table. This routine only accesses the M4599_PDI and ++ the ETHSW_PDI of the switch. All PHY registers are accessed ++ via \ref IFX_ETHSW_MDIO_DATA_WRITE and \ref IFX_ETHSW_MDIO_DATA_READ. ++ Note that the switch API implementation checks that the given address is ++ inside the valid address range. It returns with an error in case an invalid ++ address is given. ++ ++ \param IFX_PSB6970_register_t Pointer to \ref IFX_PSB6970_register_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_PSB6970_REGISTER_GET _IOWR(IFX_PSB6970_MAGIC, 0x14, IFX_PSB6970_register_t) ++ ++/*@}*/ /* PSB6970_IOCTL_DEBUG */ ++ ++#endif /* _IFX_ETHSW_PSB6970_H_ */ +diff --git a/include/switch_api/ifx_ethsw_PSB6970_core.h b/include/switch_api/ifx_ethsw_PSB6970_core.h +new file mode 100644 +index 0000000..a783710 +--- /dev/null ++++ b/include/switch_api/ifx_ethsw_PSB6970_core.h +@@ -0,0 +1,182 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ \file ifx_ethsw_ral.h ++ \remarks PSB6970 Core Layer header file, for Infineon Ethernet switch ++ drivers ++ *****************************************************************************/ ++#ifndef _IFX_ETHSW_PSB6970_CORE_H_ ++#define _IFX_ETHSW_PSB6970_CORE_H_ ++ ++#include "ifx_ethsw_api.h" ++#define IFX_PSB6970_MFC_ENTRY_MAX 8 ++#define IFX_PSB6970_MFC_RULES_MAX 24 ++#define IFX_PSB6970_REGISTER_NUMBER_MAX 0x122 ++#define IFX_PSB6970_VLAN_ENTRY_MAX 16 ++#define IFX_PSB6970_PORT_NUMBER_MAX 7 ++#define IFX_PSB6970_AR9_INTSW_PORT_NUMBER 3 ++#define IFX_PSB6970_TANTOSXG_PORT_NUMBER 7 ++#define IFX_AR9_REGISTER_NUMBER_MAX 0x1B4 ++/** Description */ ++typedef struct ++{ ++ /** Transparent Mode */ ++ IFX_boolean_t bTVM; ++ IFX_ETHSW_QoS_Scheduler_t eType; ++ IFX_boolean_t bPHYDown; ++ IFX_boolean_t eFlow; ++}IFX_PSB6970_portConfig_t; ++ ++/** Description */ ++typedef struct ++{ ++ IFX_boolean_t valid; ++ /* VLAN ID */ ++ IFX_uint16_t vid; ++ /* Forward ID */ ++ IFX_uint32_t fid; ++ /* Port Member */ ++ IFX_uint16_t pm; ++ /* Tag Member */ ++ IFX_uint16_t tm; ++}IFX_PSB6970_VLAN_tableEntry_t; ++ ++/** Description */ ++typedef struct ++{ ++ IFX_boolean_t bMF_ethertype; ++ IFX_uint16_t nVCET; ++}IFX_PSB6970_MFC_etherTypeEntry_t; ++typedef struct ++{ ++ IFX_boolean_t bMF_protocol; ++ IFX_uint8_t nPFR; ++}IFX_PSB6970_MFC_protocolEntry_t; ++typedef struct ++{ ++ IFX_boolean_t bMF_port; ++ IFX_boolean_t bPortSrc; ++ IFX_uint16_t nBasePt; ++ IFX_uint8_t nPRange; ++}IFX_PSB6970_MFC_portEntry_t; ++ ++typedef struct { ++ IFX_PSB6970_devType_t eDev; ++ IFX_PSB6970_portConfig_t PortConfig[IFX_PSB6970_PORT_NUMBER_MAX]; ++ IFX_boolean_t bVLAN_Aware; ++ IFX_PSB6970_VLAN_tableEntry_t VLAN_Table[IFX_PSB6970_VLAN_ENTRY_MAX]; ++ IFX_void_t *pRML_Dev; ++#ifdef IFX_ETHSW_API_COC ++ IFX_void_t *pPMCtx; ++#endif ++ IFX_uint8_t nPortNumber; ++ IFX_PSB6970_MFC_etherTypeEntry_t MFC_etherTypeEntrys[IFX_PSB6970_MFC_ENTRY_MAX]; ++ IFX_PSB6970_MFC_protocolEntry_t MFC_protocolEntrys[IFX_PSB6970_MFC_ENTRY_MAX]; ++ IFX_PSB6970_MFC_portEntry_t MFC_portEntrys[IFX_PSB6970_MFC_ENTRY_MAX]; ++ IFX_PSB6970_QoS_MfcCfg_t MFC_RulesEntrys[IFX_PSB6970_MFC_RULES_MAX]; ++ IFX_uint8_t RulesIndex; ++ IFX_uint32_t Registers[IFX_PSB6970_REGISTER_NUMBER_MAX]; ++ IFX_ETHSW_multicastSnoopMode_t eIGMP_Mode; ++ IFX_uint16_t vlan_table_index; ++} IFX_PSB6970_switchDev_t; ++ ++typedef struct ++{ ++ IFX_void_t *pDev; ++ IFX_PSB6970_devType_t eDev; ++}IFX_PSB6970_switchCoreInit_t; ++ ++typedef struct ++{ ++ IFX_uint8_t nTable_Index; ++ IFX_uint8_t nOP; // operation (1:add, 2:delete) ++ IFX_uint16_t nVId; ++ IFX_uint32_t nFId; ++}IFX_PSB6970_VLAN_Filter_registerOperation_t; ++ ++typedef enum ++{ ++ /** 1522 bytes */ ++ IFX_ETHSW_MAXPKTLEN_1522_BYTES = 0, ++ /** 1518 bytes */ ++ IFX_ETHSW_MAXPKTLEN_1518_BYTES = 1, ++ /** 1536 bytes */ ++ IFX_ETHSW_MAXPKTLEN_1536_BYTES = 2, ++ /** Reserved */ ++ IFX_ETHSW_MAXPKTLEN_RESERVED = 3 ++ ++}IFX_ETHSW_maxPacketLength_t; // xxx ++/** Command for access counter */ ++ ++typedef enum ++{ ++ IFX_PSB6970_CAC_INDIRECT_READ = 0, ++ IFX_PSB6970_CAC_GET_PORT_COUNTER = 1, ++ IFX_PSB6970_CAC_RESET_PORT_COUNTER = 2, ++ IFX_PSB6970_CAC_RESET_ALL_COUNTER = 3 ++}IFX_PSB6970_CAC_command_t; ++ ++/** Description */ ++typedef enum ++{ ++ /** Create a new address */ ++ IFX_PSB6970_MACTABLE_ENTRY_CREATE = 0x07, ++ IFX_PSB6970_MACTABLE_ENTRY_OVERWRITE = 0x0F, ++ IFX_PSB6970_MACTABLE_ENTRY_ERASE = 0x1F, ++ IFX_PSB6970_MACTABLE_ENTRY_SEARCH_EMPTY_ADDR = 0x20, ++ IFX_PSB6970_MACTABLE_ENTRY_SEARCH_BY_PORT = 0x29, ++ IFX_PSB6970_MACTABLE_ENTRY_SEARCH_BY_FID = 0x2A, ++ IFX_PSB6970_MACTABLE_ENTRY_SEARCH_BY_MAC = 0x2C, ++ IFX_PSB6970_MACTABLE_ENTRY_SEARCH_BY_MAC_AND_FID = 0x2E, ++ IFX_PSB6970_MACTABLE_ENTRY_SEARCH_BY_MAC_AND_PORT = 0x2D, ++ IFX_PSB6970_MACTABLE_ENTRY_SEARCH_BY_FID_AND_PORT = 0x2B, ++ IFX_PSB6970_MACTABLE_ENTRY_SEARCH_BY_MAC_FID_AND_PORT = 0x2F, ++ IFX_PSB6970_MACTABLE_INIT_TO_LOCATION = 0x34, ++ IFX_PSB6970_MACTABLE_INIT_TO_FIRST = 0x30 ++}IFX_PSB6970_MAC_tableCommand_t; ++ ++/** Description */ ++typedef enum ++{ ++ /** */ ++ IFX_PSB6970_MAC_COMMAND_OK = 0, ++ IFX_PSB6970_MAC_COMMAND_ALL_ENTRY_USED = 1, ++ IFX_PSB6970_MAC_COMMAND_ENTRY_NOT_FOUND = 2, ++ IFX_PSB6970_MAC_COMMAND_TEMP_STATE = 3, ++ IFX_PSB6970_MAC_COMMAND_ERROR = 5 ++}IFX_PSB6970_MAC_commandResult_t; ++ ++/**********************/ ++/* Function Prototype */ ++/**********************/ ++IFX_return_t IFX_PSB6970_VLAN_awareEnable(IFX_void_t *pDevCtx); ++IFX_return_t IFX_PSB6970_VLAN_awareDisable(IFX_void_t *pDevCtx); ++IFX_return_t IFX_PSB6970_PHY_PDN_Set(IFX_void_t *pDevCtx, IFX_uint8_t PHYAD); ++IFX_return_t IFX_PSB6970_PHY_PDN_Clear(IFX_void_t *pDevCtx, IFX_uint8_t PHYAD); ++IFX_return_t IFX_PSB6970_portDisable(IFX_void_t *pDevCtx, IFX_uint8_t nPortID); ++IFX_return_t IFX_PSB6970_portEnable(IFX_void_t *pDevCtx, IFX_uint8_t nPortID); ++IFX_boolean_t IFX_PSB6970_PHY_linkStatusGet(IFX_void_t *pDevCtx, IFX_uint8_t nPortID); ++IFX_boolean_t IFX_PSB6970_PHY_mediumDetectStatusGet(IFX_void_t *pDevCtx, IFX_uint8_t nPortID); ++IFX_boolean_t IFX_PSB6970_portLinkStatusGet(IFX_void_t *pDevCtx, IFX_uint8_t nPortID); ++IFX_return_t IFX_PSB6970_VLAN_Table_Init ( IFX_void_t *pDevCtx); ++IFX_return_t IFX_PSB6970_PortConfig_Init ( IFX_void_t *pDevCtx); ++IFX_return_t IFX_PSB6970_VLAN_Table_Clear ( IFX_void_t *pDevCtx ); ++IFX_boolean_t IFX_PSB6970_VLAN_Id_Exist ( IFX_void_t *pDevCtx, IFX_uint16_t vid ); ++IFX_return_t IFX_PSB6970_VLAN_Table_Print ( IFX_void_t *pDevCtx ); ++IFX_return_t IFX_PSB6970_PortConfig_Print ( IFX_void_t *pDevCtx ); ++IFX_uint8_t IFX_PSB6970_VLAN_Table_Index_Find ( IFX_void_t *pDevCtx, IFX_uint16_t vid ); ++IFX_uint8_t IFX_PSB6970_VLAN_Table_Entry_Avariable ( IFX_void_t *pDevCtx ); ++IFX_return_t IFX_PSB6970_VLAN_Table_Entry_Set ( IFX_void_t *pDevCtx, IFX_uint8_t table_index, IFX_PSB6970_VLAN_tableEntry_t *pTable_Entry ); ++IFX_return_t IFX_PSB6970_VLAN_Table_Entry_Get ( IFX_void_t *pDevCtx, IFX_uint8_t table_index, IFX_PSB6970_VLAN_tableEntry_t *pTable_Entry ); ++IFX_boolean_t IFX_PSB6970_switchStatusGet(IFX_void_t *pDevCtx); ++IFX_return_t IFX_PSB6970_switchDeviceEnable(IFX_void_t *pDevCtx); ++IFX_return_t IFX_PSB6970_switchDeviceDisable(IFX_void_t *pDevCtx); ++IFX_void_t *IFX_PSB6970_SwitchCoreInit(IFX_PSB6970_switchCoreInit_t *pInit ); ++IFX_return_t IFX_PSB6970_SwitchCoreCleanUP(IFX_void_t ); ++#endif /* _IFX_ETHSW_PSB6970_CORE_H_ */ +diff --git a/include/switch_api/ifx_ethsw_PSB6970_ll.h b/include/switch_api/ifx_ethsw_PSB6970_ll.h +new file mode 100644 +index 0000000..5284e37 +--- /dev/null ++++ b/include/switch_api/ifx_ethsw_PSB6970_ll.h +@@ -0,0 +1,1722 @@ ++/**************************************************************************** ++ ++ Copyright 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++*****************************************************************************/ ++#ifndef ____INCLUDE_IFX_ETHSW_PSB6970_LL_H ++#define ____INCLUDE_IFX_ETHSW_PSB6970_LL_H ++ ++#include "ifx_ethsw.h" ++#include "ifx_ethsw_PSB6970.h" ++ ++/* Group definitions for Doxygen */ ++/** \defgroup PSB6970_LL Ethernet Switch Application Kernel Interface ++ This chapter describes the entire interface to access and ++ configure the services of the switch module in OS kernel space. */ ++/*@{*/ ++/** \defgroup PSB6970_LL_BRIDGE Ethernet Bridging Functions ++ Ethernet bridging (or switching) is the basic task of the device. It ++ provides individual configurations per port and standard global ++ switch features. ++*/ ++/** \defgroup PSB6970_LL_DEBUG Debug Features ++ TANTOS specific features for system integration and debug sessions. ++*/ ++/** \defgroup PSB6970_LL_MULTICAST Multicast Functions ++ IGMP/MLD snooping configuration and support for IGMPv1, IGMPv2, IGMPv3, ++ MLDv1, and MLDv2. ++*/ ++/** \defgroup PSB6970_LL_OAM Operation, Administration, and Management Functions ++ This chapter summarizes the functions that are provided to monitor the ++ data traffic passing through the device. ++*/ ++/** \defgroup PSB6970_LL_POWER Power Management ++ Configure the TANTOS hardware specific power management. ++*/ ++/** \defgroup PSB6970_LL_QOS Quality of Service Functions ++ Switch and port configuration for Quality of Service (QoS). ++*/ ++/** \defgroup PSB6970_LL_VLAN VLAN Functions ++ This chapter describes VLAN bridging functionality. ++*/ ++/*@}*/ ++ ++/* ------------------------------------------------------------------------- */ ++/* Function Declaration */ ++/* ------------------------------------------------------------------------- */ ++ ++/** \addtogroup PSB6970_LL_BRIDGE */ ++/*@{*/ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_8021X_EAPOL_RULE_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_8021X_EAPOL_Rule_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_8021X_EAPOL_RuleGet(IFX_void_t *pDevCtx, IFX_ETHSW_8021X_EAPOL_Rule_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_8021X_EAPOL_RULE_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_8021X_EAPOL_Rule_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_8021X_EAPOL_RuleSet(IFX_void_t *pDevCtx, IFX_ETHSW_8021X_EAPOL_Rule_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_8021X_PORT_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a ++ 802.1x port authorized state port ++ configuration \ref IFX_ETHSW_8021X_portCfg_t ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_8021X_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_8021X_portCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_8021X_PORT_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a ++ 802.1x port authorized state port ++ configuration \ref IFX_ETHSW_8021X_portCfg_t ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_8021X_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_8021X_portCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MAC_TABLE_CLEAR command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_MAC_TableClear(IFX_void_t *pDevCtx); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MAC_TABLE_ENTRY_ADD command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a MAC table entry ++ \ref IFX_ETHSW_MAC_tableAdd_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_MAC_TableEntryAdd(IFX_void_t *pDevCtx, IFX_ETHSW_MAC_tableAdd_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MAC_TABLE_ENTRY_QUERY command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a MAC table entry ++ \ref IFX_ETHSW_MAC_tableQuery_t structure that is filled out by the switch ++ implementation. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_MAC_TableEntryQuery(IFX_void_t *pDevCtx, IFX_ETHSW_MAC_tableQuery_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MAC_TABLE_ENTRY_READ command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a MAC table entry ++ \ref IFX_ETHSW_MAC_tableRead_t structure that is filled out by the switch ++ implementation. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_MAC_TableEntryRead(IFX_void_t *pDevCtx, IFX_ETHSW_MAC_tableRead_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MAC_TABLE_ENTRY_REMOVE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a MAC table entry ++ \ref IFX_ETHSW_MAC_tableRemove_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_MAC_TableEntryRemove(IFX_void_t *pDevCtx, IFX_ETHSW_MAC_tableRemove_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_STP_BPDU_RULE_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_STP_BPDU_Rule_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_STP_BPDU_RuleGet(IFX_void_t *pDevCtx, IFX_ETHSW_STP_BPDU_Rule_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_STP_BPDU_RULE_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_STP_BPDU_Rule_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_STP_BPDU_RuleSet(IFX_void_t *pDevCtx, IFX_ETHSW_STP_BPDU_Rule_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_STP_PORT_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_STP_portCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_STP_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_STP_portCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_STP_PORT_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_STP_portCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_STP_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_STP_portCfg_t *pPar); ++ ++/*@}*/ /* PSB6970_LL_BRIDGE */ ++/** \addtogroup PSB6970_LL_VLAN */ ++/*@{*/ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VLAN_ID_CREATE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_VLAN_IdCreate_t structure element. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_VLAN_IdCreate(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_IdCreate_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VLAN_ID_DELETE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to an ++ \ref IFX_ETHSW_VLAN_IdDelete_t structure element. ++ ++ \remarks A VLAN ID can only be removed in case it was created by ++ \ref IFX_ETHSW_VLAN_ID_CREATE and is currently not assigned ++ to any Ethernet port (done using \ref IFX_ETHSW_VLAN_PORT_MEMBER_ADD). ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_VLAN_IdDelete(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_IdDelete_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VLAN_ID_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_VLAN_IdGet_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_VLAN_IdGet(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_IdGet_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VLAN_PORT_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to an ++ \ref IFX_ETHSW_VLAN_portCfg_t structure element. Based on the parameter ++ 'nPortId', the switch API implementation fills out the remaining structure ++ elements. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_VLAN_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_portCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VLAN_PORT_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to an \ref IFX_ETHSW_VLAN_portCfg_t ++ structure element. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_VLAN_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_portCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VLAN_PORT_MEMBER_ADD command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_VLAN_portMemberAdd_t structure element. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_VLAN_PortMemberAdd(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_portMemberAdd_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VLAN_PORT_MEMBER_READ command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_VLAN_portMemberRead_t structure element. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_VLAN_PortMemberRead(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_portMemberRead_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VLAN_PORT_MEMBER_REMOVE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_VLAN_portMemberRemove_t structure element. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_VLAN_PortMemberRemove(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_portMemberRemove_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VLAN_RESERVED_ADD command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_VLAN_reserved_t structure element. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_VLAN_ReservedAdd(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_reserved_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VLAN_RESERVED_REMOVE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_VLAN_reserved_t structure element. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_VLAN_ReservedRemove(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_reserved_t *pPar); ++ ++/*@}*/ /* PSB6970_LL_VLAN */ ++/** \addtogroup PSB6970_LL_QOS */ ++/*@{*/ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_DSCP_CLASS_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the QoS filter parameters ++ \ref IFX_ETHSW_QoS_DSCP_ClassCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_QoS_DSCP_ClassGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_DSCP_ClassCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_DSCP_CLASS_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the QoS filter parameters ++ \ref IFX_ETHSW_QoS_DSCP_ClassCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_QoS_DSCP_ClassSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_DSCP_ClassCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_PCP_CLASS_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the QoS filter parameters ++ \ref IFX_ETHSW_QoS_PCP_ClassCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_QoS_PCP_ClassGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_PCP_ClassCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_PCP_CLASS_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the QoS filter parameters ++ \ref IFX_ETHSW_QoS_PCP_ClassCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_QoS_PCP_ClassSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_PCP_ClassCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_PORT_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a ++ QOS port priority control configuration \ref IFX_ETHSW_QoS_portCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_QoS_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_portCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_PORT_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a ++ QOS port priority control configuration \ref IFX_ETHSW_QoS_portCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_QoS_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_portCfg_t *pPar); ++ ++/*@}*/ /* PSB6970_LL_QOS */ ++/** \addtogroup PSB6970_LL_MULTICAST */ ++/*@{*/ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_ADD command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_multicastRouter_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_MulticastRouterPortAdd(IFX_void_t *pDevCtx, IFX_ETHSW_multicastRouter_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_READ command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_multicastRouterRead_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs (e.g. Ethernet port parameter out of range) ++*/ ++IFX_return_t IFX_PSB6970_MulticastRouterPortRead(IFX_void_t *pDevCtx, IFX_ETHSW_multicastRouterRead_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_REMOVE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_multicastRouter_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs (e.g. Ethernet port parameter out of range) ++*/ ++IFX_return_t IFX_PSB6970_MulticastRouterPortRemove(IFX_void_t *pDevCtx, IFX_ETHSW_multicastRouter_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MULTICAST_SNOOP_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the ++ multicast configuration \ref IFX_ETHSW_multicastSnoopCfg_t. ++ ++ \remarks IGMP/MLD snooping is disabled when ++ 'eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_SNOOPFORWARD'. ++ Then all other structure parameters are unused. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_MulticastSnoopCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_multicastSnoopCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MULTICAST_SNOOP_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the ++ multicast configuration \ref IFX_ETHSW_multicastSnoopCfg_t. ++ ++ \remarks IGMP/MLD snooping is disabled when ++ 'eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_SNOOPFORWARD'. ++ Then all other structure parameters are unused. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_MulticastSnoopCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_multicastSnoopCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_ADD command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer ++ to \ref IFX_ETHSW_multicastTable_t. ++ ++ \remarks The Source IP parameter is ignored in case IGMPv3 support is ++ not enabled in the hardware. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_MulticastTableEntryAdd(IFX_void_t *pDevCtx, IFX_ETHSW_multicastTable_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_READ command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer ++ to \ref IFX_ETHSW_multicastTableRead_t. ++ ++ \remarks The 'bInitial' parameter is reset during the read operation. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_MulticastTableEntryRead(IFX_void_t *pDevCtx, IFX_ETHSW_multicastTableRead_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_REMOVE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer ++ to \ref IFX_ETHSW_multicastTable_t. ++ ++ \remarks The Source IP parameter is ignored in case IGMPv3 support is ++ not enabled in the hardware. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_MulticastTableEntryRemove(IFX_void_t *pDevCtx, IFX_ETHSW_multicastTable_t *pPar); ++ ++/*@}*/ /* PSB6970_LL_MULTICAST */ ++/** \addtogroup PSB6970_LL_OAM */ ++/*@{*/ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_CPU_PORT_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_CPU_PortCfg_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_CPU_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_CPU_PortCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_CPU_PORT_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_CPU_PortCfg_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_CPU_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_CPU_PortCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_CPU_PORT_EXTEND_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_CPU_PortExtendCfg_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++ ++*/ ++IFX_return_t IFX_PSB6970_CPU_PortExtendCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_CPU_PortExtendCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_CPU_PORT_EXTEND_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_CPU_PortExtendCfg_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_CPU_PortExtendCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_CPU_PortExtendCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_CAP_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to pre-allocated capability ++ list structure \ref IFX_ETHSW_cap_t. ++ The switch API implementation fills out the structure with the supported ++ features, based on the provided 'nCapType' parameter. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++ ++*/ ++IFX_return_t IFX_PSB6970_CapGet(IFX_void_t *pDevCtx, IFX_ETHSW_cap_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to an \ref IFX_ETHSW_cfg_t structure. ++ The structure is filled out by the switch implementation. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_CfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_cfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to an \ref IFX_ETHSW_cfg_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_CfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_cfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_DISABLE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_Disable(IFX_void_t *pDevCtx); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_ENABLE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_Enable(IFX_void_t *pDevCtx); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_HW_INIT command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to pre-allocated initialization structure ++ \ref IFX_ETHSW_HW_Init_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_HW_Init(IFX_void_t *pDevCtx, IFX_ETHSW_HW_Init_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MDIO_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_MDIO_cfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_MDIO_CfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_MDIO_cfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MDIO_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_MDIO_cfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_MDIO_CfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_MDIO_cfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MDIO_DATA_READ command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_MDIO_data_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_MDIO_DataRead(IFX_void_t *pDevCtx, IFX_ETHSW_MDIO_data_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MDIO_DATA_WRITE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_MDIO_data_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++ ++*/ ++IFX_return_t IFX_PSB6970_MDIO_DataWrite(IFX_void_t *pDevCtx, IFX_ETHSW_MDIO_data_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MONITOR_PORT_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer ++ to \ref IFX_ETHSW_monitorPortCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_MonitorPortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_monitorPortCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MONITOR_PORT_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer ++ to \ref IFX_ETHSW_monitorPortCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_MonitorPortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_monitorPortCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_PORT_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a port configuration ++ \ref IFX_ETHSW_portCfg_t structure to fill out by the driver. ++ The parameter 'nPortId' tells the driver which port parameter is requested. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_portCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_PORT_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to an \ref IFX_ETHSW_portCfg_t structure ++ to configure the switch port hardware. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_portCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_PORT_LINK_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_portLinkCfg_t structure to read out the port status. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_PortLinkCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_portLinkCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_PORT_LINK_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_portLinkCfg_t structure to set the port configuration. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_PortLinkCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_portLinkCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_PORT_PHY_ADDR_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_portPHY_Addr_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_PortPHY_AddrGet(IFX_void_t *pDevCtx, IFX_ETHSW_portPHY_Addr_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_PORT_PHY_QUERY command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_portPHY_Query_t structure to set the port configuration. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_PortPHY_Query(IFX_void_t *pDevCtx, IFX_ETHSW_portPHY_Query_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_PORT_RGMII_CLK_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_portRGMII_ClkCfg_t structure to set the port configuration. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_PortRGMII_ClkCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_portRGMII_ClkCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_PORT_RGMII_CLK_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_portRGMII_ClkCfg_t structure to set the port configuration. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_PortRGMII_ClkCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_portRGMII_ClkCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_PORT_REDIRECT_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer ++ to \ref IFX_ETHSW_portRedirectCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ \remarks Not all hardware platforms support this feature. The function ++ returns an error if this feature is not supported. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_PortRedirectGet(IFX_void_t *pDevCtx, IFX_ETHSW_portRedirectCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_PORT_REDIRECT_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer ++ to \ref IFX_ETHSW_portRedirectCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ \remarks Not all hardware platforms support this feature. The function ++ returns an error if this feature is not supported. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_PortRedirectSet(IFX_void_t *pDevCtx, IFX_ETHSW_portRedirectCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_RMON_CLEAR command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a pre-allocated ++ \ref IFX_ETHSW_RMON_clear_t structure. The structure element 'nPortId' is ++ an input parameter stating on which port to clear all RMON counters. ++ ++ \remarks The function returns an error in case the given 'nPortId' is ++ out of range. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_RMON_Clear(IFX_void_t *pDevCtx, IFX_ETHSW_RMON_clear_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_RMON_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to pre-allocated ++ \ref IFX_ETHSW_RMON_cnt_t structure. The structure element 'nPortId' is ++ an input parameter that describes from which port to read the RMON counter. ++ All remaining structure elements are filled with the counter values. ++ ++ \remarks The function returns an error in case the given 'nPortId' is ++ out of range. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_RMON_Get(IFX_void_t *pDevCtx, IFX_ETHSW_RMON_cnt_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VERSION_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar* The parameter points to a ++ \ref IFX_ETHSW_version_t structure. ++ ++ \return Returns value as follows: ++ - IFX_SUCCESS: if successful ++ - IFX_ERROR: in case of an error ++ ++*/ ++IFX_return_t IFX_PSB6970_VersionGet(IFX_void_t *pDevCtx, IFX_ETHSW_version_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_WOL_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_WoL_Cfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_WoL_CfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_WoL_Cfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_WOL_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_WoL_Cfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_WoL_CfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_WoL_Cfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_WOL_PORT_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_WoL_PortCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_WoL_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_WoL_PortCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_WOL_PORT_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_WoL_PortCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_WoL_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_WoL_PortCfg_t *pPar); ++ ++/*@}*/ /* PSB6970_LL_OAM */ ++/** \addtogroup PSB6970_LL_OAM */ ++/*@{*/ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_PSB6970_RESET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to an \ref IFX_PSB6970_reset_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++ ++ \remarks Not supported for all devices ++*/ ++IFX_return_t IFX_PSB6970_Reset(IFX_void_t *pDevCtx, IFX_PSB6970_reset_t *pPar); ++ ++/*@}*/ /* PSB6970_LL_OAM */ ++/** \addtogroup PSB6970_LL_QOS */ ++/*@{*/ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_PSB6970_QOS_MFC_ADD command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a QOS Multi-field ++ classification rule \ref IFX_PSB6970_QoS_MfcCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_QoS_MfcAdd(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_MfcCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_PSB6970_QOS_MFC_DEL command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a ++ QOS Multi-field classification rule \ref IFX_PSB6970_QoS_MfcMatchField_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_QoS_MfcDel(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_MfcMatchField_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_PSB6970_QOS_MFC_ENTRY_READ command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a ++ QOS Multi-field classification rule \ref IFX_PSB6970_QoS_MfcEntryRead_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_QoS_MfcEntryRead(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_MfcEntryRead_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_PSB6970_QOS_MFC_PORT_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a QOS Multi-field ++ classification rule \ref IFX_PSB6970_QoS_MfcPortCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_QoS_MfcPortCfgGet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_MfcPortCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_PSB6970_QOS_MFC_PORT_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a QOS Multi-field ++ classification rule \ref IFX_PSB6970_QoS_MfcPortCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_QoS_MfcPortCfgSet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_MfcPortCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_PSB6970_QOS_PORT_POLICER_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the rate ++ policing parameter \ref IFX_PSB6970_QoS_portPolicerCfg_t for ++ the port. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_QoS_PortPolicerGet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_portPolicerCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_PSB6970_QOS_PORT_POLICER_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the rate ++ policing parameter \ref IFX_PSB6970_QoS_portPolicerCfg_t for ++ the port. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_QoS_PortPolicerSet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_portPolicerCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_PSB6970_QOS_PORT_SHAPER_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the rate ++ shaping parameter \ref IFX_PSB6970_QoS_portShaperCfg_t for ++ the port-specific priority queue. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_QoS_PortShaperCfgGet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_portShaperCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_PSB6970_QOS_PORT_SHAPER_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the rate ++ shaping parameter \ref IFX_PSB6970_QoS_portShaperCfg_t for ++ the port-specific priority queue. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_QoS_PortShaperCfgSet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_portShaperCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_PSB6970_QOS_PORT_SHAPER_STRICT_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the rate ++ shaping parameter \ref IFX_PSB6970_QoS_portShaperStrictCfg_t for ++ the port-specific priority queue. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_QoS_PortShaperStrictGet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_portShaperStrictCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_PSB6970_QOS_PORT_SHAPER_STRICT_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the rate ++ shaping parameter \ref IFX_PSB6970_QoS_portShaperStrictCfg_t for ++ the port-specific priority queue. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_QoS_PortShaperStrictSet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_portShaperStrictCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_PSB6970_QOS_PORT_SHAPER_WFQ_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the rate ++ shaping parameter \ref IFX_PSB6970_QoS_portShaperWFQ_Cfg_t for ++ the port-specific priority queue. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_QoS_PortShaperWfqGet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_portShaperWFQ_Cfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_PSB6970_QOS_PORT_SHAPER_WFQ_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the rate ++ shaping parameter \ref IFX_PSB6970_QoS_portShaperWFQ_Cfg_t for ++ the port-specific priority queue. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_QoS_PortShaperWfqSet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_portShaperWFQ_Cfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_PSB6970_QOS_STORM_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a ++ QOS storm control configuration \ref IFX_PSB6970_QoS_stormCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_QoS_StormGet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_stormCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_PSB6970_QOS_STORM_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a ++ QOS storm control configuration \ref IFX_PSB6970_QoS_stormCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_QoS_StormSet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_stormCfg_t *pPar); ++ ++/*@}*/ /* PSB6970_LL_QOS */ ++/** \addtogroup PSB6970_LL_POWER */ ++/*@{*/ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_PSB6970_POWER_MANAGEMENT_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_PSB6970_powerManagement_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_PowerManagementGet(IFX_void_t *pDevCtx, IFX_PSB6970_powerManagement_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_PSB6970_POWER_MANAGEMENT_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_PSB6970_powerManagement_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_STATUS_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_PowerManagementSet(IFX_void_t *pDevCtx, IFX_PSB6970_powerManagement_t *pPar); ++ ++/*@}*/ /* PSB6970_LL_POWER */ ++/** \addtogroup PSB6970_LL_DEBUG */ ++/*@{*/ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_PSB6970_REGISTER_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_PSB6970_register_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_RegisterGet(IFX_void_t *pDevCtx, IFX_PSB6970_register_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_PSB6970_REGISTER_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_PSB6970_register_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_PSB6970_RegisterSet(IFX_void_t *pDevCtx, IFX_PSB6970_register_t *pPar); ++ ++/*@}*/ /* PSB6970_LL_DEBUG */ ++#endif /* ____INCLUDE_IFX_ETHSW_PSB6970_LL_H */ +diff --git a/include/switch_api/ifx_ethsw_api.h b/include/switch_api/ifx_ethsw_api.h +new file mode 100644 +index 0000000..724d0ee +--- /dev/null ++++ b/include/switch_api/ifx_ethsw_api.h +@@ -0,0 +1,172 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ \file ifx_ethsw_api.h" ++ \remarks ++ *****************************************************************************/ ++ ++#ifndef _IFX_SWITCH_API_H ++#define _IFX_SWITCH_API_H ++ ++#include "ifx_ethsw.h" ++#include "ifx_ethsw_PSB6970.h" ++#include "ifx_ethsw_ll_fkt.h" ++#include "regmapper.h" ++#include "Tantos3G.h" ++#include "AR9.h" ++#include "ifx_ethsw_flow.h" ++#include "VR9_switch.h" ++#include "VR9_top.h" ++ ++#ifdef IFXOS_SUPPORT ++ #define LINUX ++ /** This is the unsigned long datatype. ++ On 32bit systems it is 4 byte wide. ++ */ ++ typedef unsigned long IFX_ulong_t; ++ /** This is the size data type (32 or 64 bit) */ ++ typedef IFX_ulong_t IFX_size_t; ++ #include "ifxos_print.h" ++ #include "ifxos_thread.h" ++ #include "ifxos_memory_alloc.h" ++#else ++#ifdef __KERNEL__ ++ #include ++ #include ++ #include ++#endif ++#endif ++ ++#ifndef IFXOS_SUPPORT ++ #define IFXOS_PRINT_INT_RAW(fmt, args...) printk(fmt, ##args) ++ #define IFXOS_DBG_PRINT_USR(fmt, args...) printk(KERN_DEBUG fmt "\r", ##args) ++ #define IFXOS_USecSleep(n) udelay(n) ++ #define IFXOS_BlockAlloc(n) kmalloc(n, GFP_KERNEL) ++ #define IFXOS_BlockFree(n) kfree(n) ++#endif ++ ++#define PARAM_BUFFER_SIZE 2048 ++//#define GET_BITS(x, msb, lsb) (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) ++#define SET_BITS(x, msb, lsb, value) (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) ++#define IFX_ETHSW_DEV_MAX 2 ++#define SWITCH_API_MODULE_NAME "IFX ETHSW SWITCH API" ++#define SWITCH_API_DRIVER_VERSION "1.1.8.5" ++#define MICRO_CODE_VERSION "212" ++ ++extern unsigned int g_debug; ++#define IFX_ETHSW_DEBUG_PRINT(fmt, args...) ++ ++union ifx_sw_param ++{ ++ /* Ethernet Bridging Functions*/ ++ IFX_ETHSW_MAC_tableAdd_t MAC_tableAdd; ++ IFX_ETHSW_MAC_tableRead_t MAC_tableRead; ++ IFX_ETHSW_MAC_tableRemove_t MAC_tableRemove; ++ IFX_ETHSW_portCfg_t portcfg; ++ IFX_ETHSW_STP_portCfg_t STP_portCfg; ++ IFX_ETHSW_STP_BPDU_Rule_t STP_BPDU_Rule; ++ /* VLAN Functions */ ++ IFX_ETHSW_VLAN_IdCreate_t vlan_IdCreate; ++ IFX_ETHSW_VLAN_IdDelete_t vlan_IdDelete; ++ IFX_ETHSW_VLAN_IdGet_t vlan_IdGet; ++ IFX_ETHSW_VLAN_portCfg_t vlan_portcfg; ++ IFX_ETHSW_VLAN_portMemberAdd_t vlan_portMemberAdd; ++ IFX_ETHSW_VLAN_portMemberRead_t vlan_portMemberRead; ++ IFX_ETHSW_VLAN_portMemberRemove_t vlan_portMemberRemove; ++ IFX_ETHSW_VLAN_reserved_t vlan_Reserved; ++ IFX_ETHSW_VLAN_IdGet_t vlan_VidFid; ++ /* Operation, Administration, and Management Functions */ ++ IFX_ETHSW_cfg_t cfg_Data; ++ IFX_ETHSW_MDIO_cfg_t mdio_cfg; ++ IFX_ETHSW_MDIO_data_t mdio_Data; ++ IFX_ETHSW_portLinkCfg_t portlinkcfgGet; ++ IFX_ETHSW_portLinkCfg_t portlinkcfgSet; ++ IFX_ETHSW_portPHY_Addr_t phy_addr; ++ IFX_ETHSW_portRGMII_ClkCfg_t portRGMII_clkcfg; ++ IFX_ETHSW_CPU_PortExtendCfg_t portextendcfg; ++ IFX_ETHSW_portRedirectCfg_t portRedirectData; ++ IFX_ETHSW_RMON_clear_t RMON_clear; ++ IFX_ETHSW_RMON_cnt_t RMON_cnt; ++ IFX_FLOW_RMON_extendGet_t RMON_ExtendGet; ++ IFX_ETHSW_monitorPortCfg_t monitorPortCfg; ++ IFX_ETHSW_cap_t cap; ++ IFX_ETHSW_portPHY_Query_t phy_Query; ++ IFX_ETHSW_CPU_PortCfg_t CPU_PortCfg; ++ IFX_ETHSW_version_t Version; ++ IFX_PSB6970_reset_t Reset; ++ IFX_ETHSW_HW_Init_t HW_Init; ++ IFX_ETHSW_8021X_portCfg_t PNAC_portCfg; ++ IFX_ETHSW_8021X_EAPOL_Rule_t PNAC_EAPOL_Rule; ++ /* Multicast Functions */ ++ IFX_ETHSW_multicastRouter_t multicast_RouterPortAdd; ++ IFX_ETHSW_multicastRouter_t multicast_RouterPortRemove; ++ IFX_ETHSW_multicastRouterRead_t multicast_RouterPortRead; ++ IFX_ETHSW_multicastTable_t multicast_TableEntryAdd; ++ IFX_ETHSW_multicastTable_t multicast_TableEntryRemove; ++ IFX_ETHSW_multicastTableRead_t multicast_TableEntryRead; ++ IFX_ETHSW_multicastSnoopCfg_t multicast_SnoopCfgSet; ++ IFX_ETHSW_multicastSnoopCfg_t multicast_SnoopCfgGet; ++ /* Quality of Service Functions */ ++ IFX_ETHSW_QoS_portCfg_t qos_portcfg; ++ IFX_ETHSW_QoS_queuePort_t qos_queueport; ++ IFX_ETHSW_QoS_DSCP_ClassCfg_t qos_dscpclasscfgget; ++ IFX_ETHSW_QoS_DSCP_ClassCfg_t qos_dscpclasscfgset; ++ IFX_ETHSW_QoS_PCP_ClassCfg_t qos_pcpclasscfgget; ++ IFX_ETHSW_QoS_PCP_ClassCfg_t qos_pcpclasscfgset; ++ IFX_PSB6970_QoS_portShaperCfg_t qos_portShapterCfg; ++ IFX_PSB6970_QoS_portShaperStrictCfg_t qos_portShapterStrictCfg; ++ IFX_PSB6970_QoS_portShaperWFQ_Cfg_t qos_portShapterWFQ_Cfg; ++ IFX_PSB6970_QoS_portPolicerCfg_t qos_portPolicerCfg; ++ IFX_PSB6970_QoS_stormCfg_t qos_stormCfg; ++ IFX_PSB6970_QoS_MfcPortCfg_t qos_MfcPortCfg; ++ IFX_PSB6970_QoS_MfcCfg_t qos_MfcCfg; ++ IFX_PSB6970_QoS_MfcMatchField_t qos_MfcMatchField; ++ IFX_PSB6970_QoS_MfcEntryRead_t qos_MfcEntryRead; ++ IFX_ETHSW_QoS_ClassDSCP_Cfg_t qos_classdscpcfgget; ++ IFX_ETHSW_QoS_ClassDSCP_Cfg_t qos_classdscpcfgset; ++ IFX_ETHSW_QoS_ClassPCP_Cfg_t qos_classpcpcfgget; ++ IFX_ETHSW_QoS_ClassPCP_Cfg_t qos_classpcpcfgset; ++ IFX_ETHSW_QoS_ShaperCfg_t qos_shappercfg; ++ IFX_ETHSW_QoS_ShaperQueue_t qos_shapperqueue; ++ IFX_ETHSW_QoS_stormCfg_t qos_stormcfg; ++ IFX_ETHSW_QoS_schedulerCfg_t qos_schedulecfg; ++ IFX_ETHSW_QoS_WRED_Cfg_t qos_wredcfg; ++ IFX_ETHSW_QoS_WRED_QueueCfg_t qos_wredqueuecfg; ++ IFX_ETHSW_QoS_meterCfg_t qos_metercfg; ++ IFX_ETHSW_QoS_meterPort_t qos_meterport; ++ IFX_ETHSW_QoS_meterPortGet_t qos_meterportget; ++ IFX_ETHSW_QoS_portRemarkingCfg_t qos_portremarking; ++ /* Power Management Functions */ ++ IFX_PSB6970_powerManagement_t power_management; ++ /* Packet Classification Engine */ ++ IFX_FLOW_PCE_rule_t pce_rule; ++ IFX_FLOW_PCE_ruleDelete_t pce_ruledelete; ++ /* Debug Features */ ++#if defined(AR9) || defined(DANUBE) || defined(AMAZON_SE) ++ IFX_PSB6970_register_t register_access; ++#elif ( defined(VR9) || defined(AR10) || defined(HN1) ) ++ IFX_FLOW_register_t register_access; ++#endif ++}; ++ ++typedef enum ++{ ++ IFX_PSB6970_DEV_AR9 = 0, ++ IFX_PSB6970_DEV_TANTOS_3G, ++ IFX_PSB6970_DEV_TANTOS_0G, ++ IFX_PSB6970_DEV_MAX ++} IFX_PSB6970_devType_t; ++ ++typedef enum ++{ ++ IFX_FLOW_DEV_INT = 0, ++ IFX_FLOW_DEV_MAX ++} IFX_FLOW_devType_t; ++ ++#endif +diff --git a/include/switch_api/ifx_ethsw_core_platform.h b/include/switch_api/ifx_ethsw_core_platform.h +new file mode 100644 +index 0000000..51adcf6 +--- /dev/null ++++ b/include/switch_api/ifx_ethsw_core_platform.h +@@ -0,0 +1,94 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ \file ifx_ethsw_core_platform.h ++ \remarks Platform dependancy Core Layer header file, for Infineon Ethernet ++ switch drivers ++ *****************************************************************************/ ++#ifndef _IFX_ETHSW_CORE_PLATFORM_H_ ++#define _IFX_ETHSW_CORE_PLATFORM_H_ ++ ++#include "ifx_types.h" ++ ++/* ============================= */ ++/* Local Macros & Definitions */ ++/* ============================= */ ++#define SW_WRITE_REG32(data,addr) IFX_REG_W32((data), (volatile unsigned int *)addr) ++#define SW_READ_REG32(addr) IFX_REG_R32((volatile unsigned int *)addr) ++ ++#define VRX_RCU_BASE_ADDR (0xBF203000) ++#define VRX_INT_BASE_ADDR (0xBF107000) ++#define GSWIP_BASE_ADDR (0xBE108000) ++#define GSWIP_TOP_BASE_ADDR (GSWIP_BASE_ADDR + (0x0C40 * 4)) ++#define GSWIP_REG_ACCESS(addr) *((volatile IFX_int32_t *)(addr)) ++ ++//#define VR9_CHIP_ID_MAGIC_NUMBER (0x101C0083) ++/* GPHY0 Firmware Base Address Register */ ++#define GFS_ADD0 (VRX_RCU_BASE_ADDR + 0x20) ++#if defined(CONFIG_VR9) ++/* GPHY1 Firmware Base Address Register */ ++#define GFS_ADD1 (VRX_RCU_BASE_ADDR + 0x68) ++#endif /*CONFIG_VR9 */ ++#if defined(CONFIG_AR10) ++/* GPHY1 Firmware Base Address Register */ ++#define GFS_ADD1 (VRX_RCU_BASE_ADDR + 0x58) ++/* GPHY2 Firmware Base Address Register */ ++#define GFS_ADD2 (VRX_RCU_BASE_ADDR + 0xAC) ++#endif /*CONFIG_AR10 */ ++/* Chip Identification Register */ ++#define MPS_CHIPID (VRX_INT_BASE_ADDR + 0x344) ++/* GPHY01 MDIO Address Register */ ++#define GFMDIO_ADD (VRX_RCU_BASE_ADDR + 0x44) ++/* PHY Address Register PORT 5 */ ++#define PHY_ADDR_5 (GSWIP_BASE_ADDR + (0xC50 * 4)) ++/* PHY Address Register PORT 4 */ ++#define PHY_ADDR_4 (GSWIP_BASE_ADDR + (0xC51 * 4)) ++/* PHY Address Register PORT 3 */ ++#define PHY_ADDR_3 (GSWIP_BASE_ADDR + (0xC52 * 4)) ++/* PHY Address Register PORT 2 */ ++#define PHY_ADDR_2 (GSWIP_BASE_ADDR + (0xC53 * 4)) ++/* PHY Address Register PORT 1 */ ++#define PHY_ADDR_1 (GSWIP_BASE_ADDR + (0xC54 * 4)) ++/* PHY Address Register PORT 0 */ ++#define PHY_ADDR_0 (GSWIP_BASE_ADDR + (0xC55 * 4)) ++/* Transmit and Receive Buffer Control Register */ ++#define MAC_PDI_CTRL_6 (GSWIP_BASE_ADDR + (0x951 * 4)) ++/* Transmit and Receive Buffer Control Register */ ++#define PMAC_RX_IPG (GSWIP_BASE_ADDR + (0xCCB * 4)) ++/** MDC Clock Configuration Register 0 */ ++#define MDC_CFG_0_REG (GSWIP_TOP_BASE_ADDR + (0x0B * 4)) ++#define MDC_CFG_0_PEN_SET(port) (0x1 << port ) ++#define MDC_CFG_0_PEN_GET(port, reg_data) ((reg_data >> port ) & 0x1 ) ++/** MDC Clock Configuration Register 1 */ ++#define MDC_CFG_1_REG ++/** MDIO Control Register */ ++#define MDIO_CTRL_REG (GSWIP_TOP_BASE_ADDR + (8 * 4)) ++/** MDIO Busy*/ ++#define MDIO_CTRL_MBUSY 0x1000 ++#define MDIO_CTRL_OP_MASK 0x0C00 ++#define MDIO_CTRL_OP_WR 0x0400 ++#define MDIO_CTRL_OP_RD 0x0800 ++#define MDIO_CTRL_PHYAD_SET(arg) ((arg & 0x1F) << 5) ++#define MDIO_CTRL_PHYAD_GET(arg) ( (arg >> 5 ) & 0x1F) ++#define MDIO_CTRL_REGAD(arg) ( arg & 0x1F) ++/** MDIO Read Data Register */ ++#define MDIO_READ_REG (GSWIP_TOP_BASE_ADDR + (9 * 4)) ++#define MDIO_READ_RDATA(arg) (arg & 0xFFFF) ++/** MDIO Write Data Register */ ++#define MDIO_WRITE_REG (GSWIP_TOP_BASE_ADDR + (0x0A * 4)) ++#define MDIO_READ_WDATA(arg) (arg & 0xFFFF) ++ ++/**********************/ ++/* Function Prototype */ ++/**********************/ ++IFX_int32_t platform_device_reset_trigger(IFX_void_t); ++IFX_int32_t platform_device_reset_release(IFX_void_t); ++IFX_int32_t platform_device_init(IFX_void_t *pDevCtx); ++ ++#endif /* _IFX_ETHSW_CORE_PLATFORM_H_ */ +diff --git a/include/switch_api/ifx_ethsw_flow.h b/include/switch_api/ifx_ethsw_flow.h +new file mode 100644 +index 0000000..d556133 +--- /dev/null ++++ b/include/switch_api/ifx_ethsw_flow.h +@@ -0,0 +1,845 @@ ++/**************************************************************************** ++ ++ Copyright 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++*****************************************************************************/ ++#ifndef _IFX_FLOW_FLOW_H_ ++#define _IFX_FLOW_FLOW_H_ ++ ++#include "ifx_types.h" ++#include "ifx_ethsw.h" ++ ++/* =================================== */ ++/* Global typedef forward declarations */ ++/* =================================== */ ++ ++/* ============================= */ ++/* Local Macros & Definitions */ ++/* ============================= */ ++ ++/* IOCTL MAGIC */ ++#define IFX_FLOW_MAGIC ('F') ++ ++/* Group definitions for Doxygen */ ++/** \defgroup FLOW_IOCTL XWAY VRX200 and XWAY GRX200 Family Specific Ethernet Switch API ++ This chapter describes the XWAY VRX200 and XWAY GRX200 Family specific ++ interfaces for accessing and configuring the services of the Ethernet switch module. ++ These features are a device-specific enhancement of the generic Switch API part. */ ++/*@{*/ ++ ++/** \defgroup FLOW_IOCTL_DEBUG Debug Features ++ XWAY VRX200 and XWAY GRX200 Family specific features for system ++ integration and debug sessions. ++*/ ++/** \defgroup FLOW_IOCTL_IRQ Interrupt Handling ++ Configure XWAY VRX200 and XWAY GRX200 Family specific hardware ++ support to generate interrupts ++ and read out the interrupt sources. ++*/ ++/** \defgroup FLOW_IOCTL_OAM Operation, Administration, and Management Functions ++ This chapter summarizes the functions that are provided to monitor the ++ data traffic passing through the device. ++*/ ++/** \defgroup FLOW_IOCTL_CLASSUNIT Packet Classification Engine ++ Configures and controls the classification unit of the XWAY VRX200 ++ and XWAY GRX200 Family hardware. ++*/ ++ ++/*@}*/ ++ ++/* -------------------------------------------------------------------------- */ ++/* Structure and Enumeration Type Defintions */ ++/* -------------------------------------------------------------------------- */ ++ ++/** \addtogroup FLOW_IOCTL_DEBUG */ ++/*@{*/ ++ ++/** Register access parameter to directly read or write switch ++ internal registers. ++ Used by \ref IFX_FLOW_REGISTER_SET and \ref IFX_FLOW_REGISTER_GET. */ ++typedef struct ++{ ++ /** Register Address Offset for read or write access. */ ++ IFX_uint16_t nRegAddr; ++ /** Value to write to or read from 'nRegAddr'. */ ++ IFX_uint16_t nData; ++}IFX_FLOW_register_t; ++ ++/*@}*/ /* FLOW_IOCTL_DEBUG */ ++ ++/** \addtogroup FLOW_IOCTL_IRQ */ ++/*@{*/ ++ ++/** Interrupt Source Selector. ++ Used by \ref IFX_FLOW_irq_t. */ ++typedef enum ++{ ++ /** Wake-on-LAN Interrupt. ++ The parameter 'nPortId' specifies the relative MAC port. */ ++ IFX_FLOW_IRQ_WOL = 0, ++ /** Port Limit Alert Interrupt. This interrupt is asserted when the number ++ of learned MAC addresses exceeds the configured limit for ++ the ingress port. ++ The parameter 'nPortId' specifies the relative MAC port. */ ++ IFX_FLOW_IRQ_LIMIT_ALERT = 1, ++ /** Port Lock Alert Interrupt. ++ This interrupt is asserted when a source MAC address is learned on a ++ locked port and is received on another port. ++ The parameter 'nPortId' specifies the relative MAC port. */ ++ IFX_FLOW_IRQ_LOCK_ALERT = 2 ++}IFX_FLOW_irqSrc_t; ++ ++/** Interrupt bits. Depending on the hardware device type, not all interrupts might be available. ++ Used by \ref IFX_FLOW_IRQ_MASK_GET, \ref IFX_FLOW_IRQ_MASK_SET, ++ \ref IFX_FLOW_IRQ_GET and \ref IFX_FLOW_IRQ_STATUS_CLEAR. */ ++typedef struct ++{ ++ /** Ethernet Port number (zero-based counting). The valid range is hardware dependent. ++ An error code is delivered if the selected port is not ++ available. This port parameter is needed for some interrupts ++ that are specified by 'nIrqSrc'. For all other interrupts, this ++ parameter is "don't care". */ ++ IFX_uint32_t nPortId; ++ /** Interrupt source. */ ++ IFX_FLOW_irqSrc_t eIrqSrc; ++}IFX_FLOW_irq_t; ++ ++/*@}*/ /* FLOW_IOCTL_IRQ */ ++ ++/** \addtogroup FLOW_IOCTL_CLASSUNIT */ ++/*@{*/ ++ ++/** Rule selection for IPv4/IPv6. ++ Used by \ref IFX_FLOW_PCE_pattern_t. */ ++typedef enum ++{ ++ /** Rule Pattern for IP selection disabled. */ ++ IFX_FLOW_PCE_IP_DISABLED = 0, ++ /** Rule Pattern for IPv4. */ ++ IFX_FLOW_PCE_IP_V4 = 1, ++ /** Rule Pattern for IPv6. */ ++ IFX_FLOW_PCE_IP_V6 = 2 ++}IFX_FLOW_PCE_IP_t; ++ ++/** Packet Classification Engine Pattern Configuration. ++ Used by \ref IFX_FLOW_PCE_rule_t. */ ++typedef struct ++{ ++ /** Index */ ++ IFX_int32_t nIndex; ++ ++ /** Index is used (enabled) or set to unused (disabled) */ ++ IFX_boolean_t bEnable; ++ ++ /** Port ID used */ ++ IFX_boolean_t bPortIdEnable; ++ /** Port ID */ ++ IFX_uint8_t nPortId; ++ ++ /** DSCP value used */ ++ IFX_boolean_t bDSCP_Enable; ++ /** DSCP value */ ++ IFX_uint8_t nDSCP; ++ ++ /** PCP value used */ ++ IFX_boolean_t bPCP_Enable; ++ /** PCP value */ ++ IFX_uint8_t nPCP; ++ ++ /** Packet length used */ ++ IFX_boolean_t bPktLngEnable; ++ /** Packet length */ ++ IFX_uint16_t nPktLng; ++ /** Packet length Range */ ++ IFX_uint16_t nPktLngRange; ++ ++ /** Destination MAC address used */ ++ IFX_boolean_t bMAC_DstEnable; ++ /** Destination MAC address */ ++ IFX_uint8_t nMAC_Dst[6]; ++ /** Destination MAC address mask. ++ Please clear the bits of the nibbles that are not marked out and set all other bits. ++ The LSB bit represents the lowest data nibble, the next bit the next nibble, ++ and so on. */ ++ IFX_uint16_t nMAC_DstMask; ++ ++ /** Source MAC address used */ ++ IFX_boolean_t bMAC_SrcEnable; ++ /** Source MAC address */ ++ IFX_uint8_t nMAC_Src[6]; ++ /** Source MAC address mask. ++ Please clear the bits of the nibbles that are not marked out and set all other bits. ++ The LSB bit represents the lowest data nibble, the next bit the next nibble, ++ and so on. */ ++ IFX_uint16_t nMAC_SrcMask; ++ ++ /** MSB Application field used */ ++ IFX_boolean_t bAppDataMSB_Enable; ++ /** MSB Application field. ++ The first 2 bytes of the packet content following the IP header ++ for TCP/UDP packets (source port field), or the first 2 bytes of packet content ++ following the Ethertype for non-IP packets. Any part of this ++ content can be masked-out by a programmable bit ++ mask 'nAppMaskRangeMSB'. */ ++ IFX_uint16_t nAppDataMSB; ++ /** MSB Application mask/range selection. ++ If set to IFX_TRUE, the field 'nAppMaskRangeMSB' is used as a ++ range parameter, otherwise it is used as a nibble mask field. */ ++ IFX_boolean_t bAppMaskRangeMSB_Select; ++ /** MSB Application mask/range. When used as a range parameter, ++ 1 bit represents 1 nibble mask of the 'nAppDataMSB' field. ++ Please clear the bits of the nibbles that are not marked out and set all other bits. ++ The LSB bit represents the lowest data nibble, the next bit the next nibble, ++ and so on. */ ++ IFX_uint16_t nAppMaskRangeMSB; ++ ++ /** LSB Application used */ ++ IFX_boolean_t bAppDataLSB_Enable; ++ /** LSB Application field. ++ The following 2 bytes of the packet behind the 'nAppDataMSB' field. ++ This is the destination port field for TCP/UDP packets, ++ or byte 3 and byte 4 of the packet content following the Ethertype ++ for non-IP packets. Any part of this content can be masked-out ++ by a programmable bit mask 'nAppMaskRangeLSB'. */ ++ IFX_uint16_t nAppDataLSB; ++ /** LSB Application mask/range selection. ++ If set to IFX_TRUE, the field 'nAppMaskRangeLSB' is used as ++ a range parameter, otherwise it is used as a nibble mask field. */ ++ IFX_boolean_t bAppMaskRangeLSB_Select; ++ /** LSB Application mask/range. When used as a range parameter, ++ 1 bit represents 1 nibble mask of the 'nAppDataLSB' field. ++ Please clear the bits of the nibbles that are not marked out and set all other bits. ++ The LSB bit represents the lowest data nibble, the next bit the next nibble, ++ and so on. */ ++ IFX_uint16_t nAppMaskRangeLSB; ++ ++ /** DIP Selection. */ ++ IFX_FLOW_PCE_IP_t eDstIP_Select; ++ /** DIP */ ++ IFX_ETHSW_IP_t nDstIP; ++ /** DIP Nibble Mask. ++ 1 bit represents 1 nibble mask of the 'nDstIP' field. ++ Please clear the bits of the nibbles that are not marked out and set all other bits. ++ The LSB bit represents the lowest data nibble, the next bit the next nibble, ++ and so on. */ ++ IFX_uint32_t nDstIP_Mask; ++ ++ /** SIP Selection. */ ++ IFX_FLOW_PCE_IP_t eSrcIP_Select; ++ /** SIP */ ++ IFX_ETHSW_IP_t nSrcIP; ++ /** SIP Nibble Mask. ++ 1 bit represents 1 nibble mask of the 'nSrcIP' field. ++ Please clear the bits of the nibbles that are not marked out and set all other bits. ++ The LSB bit represents the lowest data nibble, the next bit the next nibble, ++ and so on. */ ++ IFX_uint32_t nSrcIP_Mask; ++ ++ /** Ethertype used. */ ++ IFX_boolean_t bEtherTypeEnable; ++ /** Ethertype */ ++ IFX_uint16_t nEtherType; ++ /** Ethertype Mask. ++ 1 bit represents 1 nibble mask of the 'nEtherType' field. ++ Please clear the bits of the nibbles that are not marked out and set all other bits. ++ The LSB bit represents the lowest data nibble, the next bit the next nibble, ++ and so on. */ ++ IFX_uint16_t nEtherTypeMask; ++ ++ /** IP protocol used */ ++ IFX_boolean_t bProtocolEnable; ++ /** IP protocol */ ++ IFX_uint8_t nProtocol; ++ /** IP protocol Mask. ++ 1 bit represents 1 nibble mask of the 'nProtocol' field. ++ Please clear the bits of the nibbles that are not marked out and set all other bits. ++ The LSB bit represents the lowest data nibble, the next bit the next nibble, ++ and so on. */ ++ IFX_uint8_t nProtocolMask; ++ ++ /** PPPoE used. */ ++ IFX_boolean_t bSessionIdEnable; ++ /** PPPoE */ ++ IFX_uint16_t nSessionId; ++ ++ /** VLAN used. */ ++ IFX_boolean_t bVid; ++ /** VLAN */ ++ IFX_uint16_t nVid; ++}IFX_FLOW_PCE_pattern_t; ++ ++/** IGMP Snooping Control. ++ Used by \ref IFX_FLOW_PCE_action_t. */ ++typedef enum ++{ ++ /** Disabled. IGMP Snooping is disabled. */ ++ IFX_FLOW_PCE_ACTION_IGMP_SNOOP_DISABLE = 0, ++ /** Default. Regular Packet. No IGMP Snooping action required. */ ++ IFX_FLOW_PCE_ACTION_IGMP_SNOOP_REGULAR = 1, ++ /** IGMP Report/Join Message. */ ++ IFX_FLOW_PCE_ACTION_IGMP_SNOOP_REPORT = 2, ++ /** IGMP Leave Message. */ ++ IFX_FLOW_PCE_ACTION_IGMP_SNOOP_LEAVE = 3, ++ /** Router Solicitation/Advertisement message. */ ++ IFX_FLOW_PCE_ACTION_IGMP_SNOOP_AD = 4, ++ /** IGMP Query Message. */ ++ IFX_FLOW_PCE_ACTION_IGMP_SNOOP_QUERY = 5, ++ /** IGMP Group Specific Query Message. */ ++ IFX_FLOW_PCE_ACTION_IGMP_SNOOP_QUERY_GROUP = 6, ++ /** IGMP General Query message without Router Solicitation. */ ++ IFX_FLOW_PCE_ACTION_IGMP_SNOOP_QUERY_NO_ROUTER = 7 ++}IFX_FLOW_PCE_ActionIGMP_Snoop_t; ++ ++/** MAC Address Learning control. ++ Used by \ref IFX_FLOW_PCE_action_t. */ ++typedef enum ++{ ++ /** MAC Address Learning action is disabled. MAC address learning is ++ not influenced by this rule. */ ++ IFX_FLOW_PCE_ACTION_LEARNING_DISABLE = 0, ++ /** Learning is based on the forwarding decision. If the packet is discarded, ++ the address is not learned. If the packet is forwarded to any egress port, ++ the address is learned. */ ++ IFX_FLOW_PCE_ACTION_LEARNING_REGULAR = 1, ++ /** Force No Learning. The address is not learned; forwarding decision ++ ignored. */ ++ IFX_FLOW_PCE_ACTION_LEARNING_FORCE_NOT = 2, ++ /** Force Learning. The address is learned, the forwarding decision ignored. ++ Note: The MAC Learning Control signals delivered to Port-Map filtering ++ and combined with Final Forwarding Decision. The result is used as a ++ feedback for MAC Address learning in the Bridging Table. */ ++ IFX_FLOW_PCE_ACTION_LEARNING_FORCE = 3 ++}IFX_FLOW_PCE_ActionLearning_t; ++ ++/** Flow Meter Assignment control. ++ Used by \ref IFX_FLOW_PCE_action_t. */ ++typedef enum ++{ ++ /** Action Disable. */ ++ IFX_FLOW_PCE_ACTION_METER_DISABLE = 0, ++ /** Action Enable. Assign Flow-Meter-Num to Meter-ID-0. */ ++ IFX_FLOW_PCE_ACTION_METER_1 = 1, ++ /** Action Enable. Assign Flow-Meter-Num to Meter-ID-1. */ ++ IFX_FLOW_PCE_ACTION_METER_2 = 2, ++ /** Action Enable. Assign pair of meters: Flow-Meter-Num to Meter-ID-0. ++ Flow-Meter-Num+1 to Meter-ID-1. */ ++ IFX_FLOW_PCE_ACTION_METER_1_2 = 3 ++}IFX_FLOW_PCE_ActionMeter_t; ++ ++/** Traffic Class Action Selector. ++ Used by \ref IFX_FLOW_PCE_action_t. */ ++typedef enum ++{ ++ /** Disabled. Traffic class action is disabled. */ ++ IFX_FLOW_PCE_ACTION_TRAFFIC_CLASS_DISABLE = 0, ++ /** Regular Class. Traffic class action is enabled and the CoS ++ classification traffic class is used. */ ++ IFX_FLOW_PCE_ACTION_TRAFFIC_CLASS_REGULAR = 1, ++ /** Alternative Class. Traffic class action is enabled and the ++ class of the 'nTrafficClassAlter' field is used. */ ++ IFX_FLOW_PCE_ACTION_TRAFFIC_CLASS_ALTERNATIVE = 2, ++}IFX_FLOW_PCE_ActionTrafficClass_t; ++ ++/** Interrupt Control Action Selector. ++ Used by \ref IFX_FLOW_PCE_action_t. */ ++typedef enum ++{ ++ /** Disabled. Interrupt Control Action is disabled for this rule. */ ++ IFX_FLOW_PCE_ACTION_IRQ_DISABLE = 0, ++ /** Regular Packet. The Interrupt Control Action is enabled, the packet is ++ treated as a regular packet and no interrupt event is generated. */ ++ IFX_FLOW_PCE_ACTION_IRQ_REGULAR = 1, ++ /** Interrupt Event. The Interrupt Control Action is enabled and an ++ interrupt event is generated. */ ++ IFX_FLOW_PCE_ACTION_IRQ_EVENT = 2 ++}IFX_FLOW_PCE_ActionIrq_t; ++ ++/** Cross State Action Selector. ++ Used by \ref IFX_FLOW_PCE_action_t. */ ++typedef enum ++{ ++ /** Disable. The Cross State Action is disabled. */ ++ IFX_FLOW_PCE_ACTION_CROSS_STATE_DISABLE = 0, ++ /** Regular Packet. The Cross State Action is enabled and the packet is ++ treated as a non-Cross-State packet (regular packet). Therefore it does ++ not ignore Port-State filtering rules. */ ++ IFX_FLOW_PCE_ACTION_CROSS_STATE_REGULAR = 1, ++ /** Cross-State packet. The Cross State Action is enabled and the packet is ++ treated as a Cross-State packet. It ignores the Port-State ++ filtering rules. */ ++ IFX_FLOW_PCE_ACTION_CROSS_STATE_CROSS = 2 ++}IFX_FLOW_PCE_ActionCrossState_t; ++ ++/** Critical Frame Action Selector. ++ Used by \ref IFX_FLOW_PCE_action_t. */ ++typedef enum ++{ ++ /** Disable. The Critical Frame Action is disabled. */ ++ IFX_FLOW_PCE_ACTION_CRITICAL_FRAME_DISABLE = 0, ++ /** Regular Packet. The Critical Frame Action is enabled and the packet is ++ treated as a non-Critical Frame. */ ++ IFX_FLOW_PCE_ACTION_CRITICAL_FRAME_REGULAR = 1, ++ /** Critical Packet. The Critical Frame Action is enabled and the packet is ++ treated as a Critical Frame. */ ++ IFX_FLOW_PCE_ACTION_CRITICAL_FRAME_CRITICAL = 2 ++}IFX_FLOW_PCE_ActionCriticalFrame_t; ++ ++/** Timestamp Action Selector. ++ Used by \ref IFX_FLOW_PCE_action_t. */ ++typedef enum ++{ ++ /** Disable. Timestamp Action is disabled for this rule. */ ++ IFX_FLOW_PCE_ACTION_TIMESTAMP_DISABLE = 0, ++ /** Regular Packet. The Timestamp Action is enabled for this rule. ++ The packet is treated as a regular packet and no timing information ++ is stored. */ ++ IFX_FLOW_PCE_ACTION_TIMESTAMP_REGULAR = 1, ++ /** Receive/Transmit Timing packet. Ingress and Egress Timestamps for ++ this packet should be stored. */ ++ IFX_FLOW_PCE_ACTION_TIMESTAMP_STORED = 2 ++}IFX_FLOW_PCE_ActionTimestamp_t; ++ ++/** Forwarding Group Action Selector. ++ This flow table action and the 'bFlowID_Action' action ++ can be used exclusively. ++ Used by \ref IFX_FLOW_PCE_action_t. */ ++typedef enum ++{ ++ /** Disable. Forwarding Group Action is disabled. */ ++ IFX_FLOW_PCE_ACTION_PORTMAP_DISABLE = 0, ++ /** Regular Packet. Forwarding Action enabled. Select Default ++ Port-Map (result of Default Forwarding Classification). */ ++ IFX_FLOW_PCE_ACTION_PORTMAP_REGULAR = 1, ++ /** Discard. Discard the packets. */ ++ IFX_FLOW_PCE_ACTION_PORTMAP_DISCARD = 2, ++ /** Forward to the CPU port. This requires that the CPU port is previously ++ set by calling \ref IFX_ETHSW_CPU_PORT_CFG_SET. */ ++ IFX_FLOW_PCE_ACTION_PORTMAP_CPU = 3, ++ /** Forward to a portmap, selected by the parameter 'nForwardPortMap'. ++ Please note that this feature is not supported by all ++ hardware platforms. */ ++ IFX_FLOW_PCE_ACTION_PORTMAP_ALTERNATIVE = 4, ++ /** The packet is treated as Multicast Router ++ Solicitation/Advertisement or Query packet. */ ++ IFX_FLOW_PCE_ACTION_PORTMAP_MULTICAST_ROUTER = 5, ++ /** The packet is interpreted as Multicast packet and learned in the ++ multicast group table. */ ++ IFX_FLOW_PCE_ACTION_PORTMAP_MULTICAST_HW_TABLE = 6 ++}IFX_FLOW_PCE_ActionPortmap_t; ++ ++/** VLAN Group Action Selector. ++ Used by \ref IFX_FLOW_PCE_action_t. */ ++typedef enum ++{ ++ /** Disabled. The VLAN Action is disabled. */ ++ IFX_FLOW_PCE_ACTION_VLAN_DISABLE = 0, ++ /** Regular VLAN. VLAN Action enabled. Select Default VLAN ID. */ ++ IFX_FLOW_PCE_ACTION_VLAN_REGULAR = 1, ++ /** Alternative VLAN. VLAN Action enabled. ++ Select Alternative VLAN as configured in 'nVLAN_Id'. It requires that ++ this VLAN ID is configured by ++ calling \ref IFX_ETHSW_VLAN_ID_CREATE in advance. */ ++ IFX_FLOW_PCE_ACTION_VLAN_ALTERNATIVE = 2 ++}IFX_FLOW_PCE_ActionVLAN_t; ++ ++/** Cross VLAN Action Selector. ++ Used by \ref IFX_FLOW_PCE_action_t. */ ++typedef enum ++{ ++ /** Disabled. The Cross VLAN Action is disabled. */ ++ IFX_FLOW_PCE_ACTION_CROSS_VLAN_DISABLE = 0, ++ /** Regular VLAN Packet. Do not ignore VLAN filtering rules. */ ++ IFX_FLOW_PCE_ACTION_CROSS_VLAN_REGULAR = 1, ++ /** Cross-VLAN packet. Ignore VLAN filtering rules.*/ ++ IFX_FLOW_PCE_ACTION_CROSS_VLAN_CROSS = 2 ++}IFX_FLOW_PCE_ActionCrossVLAN_t; ++ ++/** Packet Classification Engine Action Configuration. ++ Used by \ref IFX_FLOW_PCE_rule_t. */ ++typedef struct ++{ ++ /** Action "Traffic Class" Group. ++ Traffic class action enable */ ++ IFX_FLOW_PCE_ActionTrafficClass_t eTrafficClassAction; ++ /** Alternative Traffic class */ ++ IFX_uint8_t nTrafficClassAlternate; ++ ++ /** Action "IGMP Snooping" Group. ++ IGMP Snooping control and enable. Please note that the 'nPortMapAction' ++ configuration is ignored in case the IGMP snooping is enabled. ++ Here, on read operations, ++ 'nPortMapAction = IFX_FLOW_PCE_ACTION_PORTMAP_DISABLE' is returned. */ ++ IFX_FLOW_PCE_ActionIGMP_Snoop_t eSnoopingTypeAction; ++ ++ /** Action "Learning" Group. ++ Learning action control and enable */ ++ IFX_FLOW_PCE_ActionLearning_t eLearningAction; ++ ++ /** Action "Interrupt" Group. ++ Interrupt action generate and enable */ ++ IFX_FLOW_PCE_ActionIrq_t eIrqAction; ++ ++ /** Action "Cross State" Group. ++ Cross state action control and enable */ ++ IFX_FLOW_PCE_ActionCrossState_t eCrossStateAction; ++ ++ /** Action "Critical Frames" Group. ++ Critical Frame action control and enable */ ++ IFX_FLOW_PCE_ActionCriticalFrame_t eCritFrameAction; ++ ++ /** Action "Timestamp" Group. Time stamp action control and enable */ ++ IFX_FLOW_PCE_ActionTimestamp_t eTimestampAction; ++ ++ /** Action "Forwarding" Group. ++ Port map action enable. This port forwarding configuration is ignored ++ in case the action "IGMP Snooping" is enabled via the ++ parameter 'nSnoopingTypeAction'. */ ++ IFX_FLOW_PCE_ActionPortmap_t ePortMapAction; ++ /** Target portmap for forwarded packets, only used if selected by ++ 'nPortMapAction'. Forwarding is done ++ if 'nPortMapAction = IFX_FLOW_PCE_ACTION_PORTMAP_ALTERNATIVE'. ++ Every bit in the portmap represents one port (port 0 = LSB bit). */ ++ IFX_uint32_t nForwardPortMap; ++ ++ /** Action "Remarking" Group. Remarking action enable */ ++ IFX_boolean_t bRemarkAction; ++ /** PCP remarking enable. ++ Remarking enabling means that remarking is possible in case ++ the port configuration or metering enables remarking on that ++ packet. Disabling remarking means that it is forced to ++ not remarking this packet, independent of any port remarking of ++ metering configuration. */ ++ IFX_boolean_t bRemarkPCP; ++ /** DSCP remarking enable ++ Remarking enabling means that remarking is possible in case ++ the port configuration or metering enables remarking on that ++ packet. Disabling remarking means that it is forced to ++ not remarking this packet, independent of any port remarking of ++ metering configuration. */ ++ IFX_boolean_t bRemarkDSCP; ++ /** Class remarking enable ++ Remarking enabling means that remarking is possible in case ++ the port configuration or metering enables remarking on that ++ packet. Disabling remarking means that it is forced to ++ not remarking this packet, independent of any port remarking of ++ metering configuration. */ ++ IFX_boolean_t bRemarkClass; ++ ++ /** Action "Meter" Group. Meter action control and enable. */ ++ IFX_FLOW_PCE_ActionMeter_t eMeterAction; ++ /** Meter ID */ ++ IFX_uint8_t nMeterId; ++ ++ /** Action "RMON" Group. RMON action enable */ ++ IFX_boolean_t bRMON_Action; ++ /** Counter ID (The index starts counting from zero). */ ++ IFX_uint8_t nRMON_Id; ++ ++ /** Action "VLAN" Group. VLAN action enable */ ++ IFX_FLOW_PCE_ActionVLAN_t eVLAN_Action; ++ /** Alternative VLAN Id */ ++ IFX_uint16_t nVLAN_Id; ++ ++ /** Action "Cross VLAN" Group. Cross VLAN action enable */ ++ IFX_FLOW_PCE_ActionCrossVLAN_t eVLAN_CrossAction; ++ ++ /** Action "Flow ID". ++ The Switch supports enhancing the egress packets by a device specific ++ special tag header. This header contains detailed switch classification ++ results. One header file is a 'Flow ID', which can be explicitly set as ++ flow table action when hitting a table rule. ++ If selected, the Flow ID is given by the parameter 'nFlowID'. */ ++ IFX_boolean_t bFlowID_Action; ++ ++ /** Flow ID */ ++ IFX_uint16_t nFlowID; ++}IFX_FLOW_PCE_action_t; ++ ++/** Parameter to add/read a rule to/from the packet classification engine. ++ Used by \ref IFX_FLOW_PCE_RULE_WRITE and \ref IFX_FLOW_PCE_RULE_READ. */ ++typedef struct ++{ ++ /** Rule Pattern Part. */ ++ IFX_FLOW_PCE_pattern_t pattern; ++ /** Rule Action Part. */ ++ IFX_FLOW_PCE_action_t action; ++}IFX_FLOW_PCE_rule_t; ++ ++/** Parameter to delete a rule from the packet classification engine. ++ Used by \ref IFX_FLOW_PCE_RULE_DELETE. */ ++typedef struct ++{ ++ /** Action Index in the Packet Classification Engine. ++ It corresponds to the table rule index. */ ++ IFX_uint32_t nIndex; ++}IFX_FLOW_PCE_ruleDelete_t; ++ ++/*@}*/ /* FLOW_IOCTL_CLASSUNIT */ ++ ++/** \addtogroup FLOW_IOCTL_OAM */ ++/*@{*/ ++ ++/** Reset selection. ++ Used by \ref IFX_FLOW_reset_t. */ ++typedef enum ++{ ++ /** Switch Macro reset */ ++ IFX_FLOW_RESET_SWITCH = 0, ++ /** MDIO master interface reset */ ++ IFX_FLOW_RESET_MDIO = 1, ++}IFX_FLOW_resetMode_t; ++ ++/** Reset selection. ++ Used by \ref IFX_FLOW_RESET. */ ++typedef struct ++{ ++ /** Reset selection. */ ++ IFX_FLOW_resetMode_t eReset; ++}IFX_FLOW_reset_t; ++ ++/** Number of extended RMON counter. */ ++#define IFX_FLOW_RMON_EXTEND_NUM 24 ++ ++/** ++ Hardware platform extended RMON Counters. ++ This structure contains additional RMON counters of one Ethernet Switch Port. ++ These counters can be used by the packet classification engine and can be ++ freely assigned to dedicated packet rules and flows. ++ Used by \ref IFX_FLOW_RMON_EXTEND_GET. */ ++typedef struct ++{ ++ /** Ethernet Port number (zero-based counting). The valid range is hardware ++ dependent. An error code is delivered if the selected port is not ++ available. */ ++ IFX_uint8_t nPortId; ++ /** Traffic flow counters */ ++ IFX_uint32_t nTrafficFlowCnt[IFX_FLOW_RMON_EXTEND_NUM]; ++}IFX_FLOW_RMON_extendGet_t; ++ ++/*@}*/ /* FLOW_IOCTL_OAM */ ++ ++/* -------------------------------------------------------------------------- */ ++/* IOCTL Command Definitions */ ++/* -------------------------------------------------------------------------- */ ++ ++/** \addtogroup FLOW_IOCTL_DEBUG */ ++/*@{*/ ++ ++/** ++ Write to an internal register. The register offset defines which register to access in ++ which table. This routine only accesses the M4599_PDI and ++ the ETHSW_PDI of the switch. All PHY registers are accessed ++ via \ref IFX_ETHSW_MDIO_DATA_WRITE and \ref IFX_ETHSW_MDIO_DATA_READ. ++ Note that the switch API implementation checks whether the given address is ++ inside the valid address range. It returns with an error in case an invalid ++ address is given. ++ ++ \param IFX_FLOW_register_t Pointer to \ref IFX_FLOW_register_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_FLOW_REGISTER_SET _IOW(IFX_FLOW_MAGIC, 0x01, IFX_FLOW_register_t) ++ ++/** ++ Read an internal register. The register offset defines which register to access in ++ which table. This routine only accesses the M4599_PDI and ++ the ETHSW_PDI of the switch. All PHY registers are accessed ++ via \ref IFX_ETHSW_MDIO_DATA_WRITE and \ref IFX_ETHSW_MDIO_DATA_READ. ++ Note that the switch API implementation checks whether the given address is ++ inside the valid address range. It returns with an error in case an invalid ++ address is given. ++ ++ \param IFX_FLOW_register_t Pointer to \ref IFX_FLOW_register_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_FLOW_REGISTER_GET _IOWR(IFX_FLOW_MAGIC, 0x02, IFX_FLOW_register_t) ++ ++/*@}*/ /* FLOW_IOCTL_DEBUG */ ++ ++/** \addtogroup FLOW_IOCTL_IRQ */ ++/*@{*/ ++/** ++ Get the interrupt enable configuration. This assignment can be set using \ref IFX_FLOW_IRQ_MASK_SET. ++ ++ \param IFX_FLOW_irq_t Pointer to ++ an \ref IFX_FLOW_irq_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++ ++*/ ++#define IFX_FLOW_IRQ_MASK_GET _IOWR(IFX_FLOW_MAGIC, 0x03, IFX_FLOW_irq_t) ++ ++/** ++ Set the interrupt enable configuration. This assignment can be read using \ref IFX_FLOW_IRQ_MASK_GET. ++ Setting interrupts that are not supported by hardware results in an error response. ++ ++ \param IFX_FLOW_irq_t Pointer to ++ an \ref IFX_FLOW_irq_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++ ++*/ ++#define IFX_FLOW_IRQ_MASK_SET _IOW(IFX_FLOW_MAGIC, 0x04, IFX_FLOW_irq_t) ++ ++/** ++ Read the interrupt status. Interrupt status indications can be cleared using \ref IFX_FLOW_IRQ_STATUS_CLEAR. ++ ++ \param IFX_FLOW_irq_t Pointer to ++ an \ref IFX_FLOW_irq_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++ ++*/ ++#define IFX_FLOW_IRQ_GET _IOWR(IFX_FLOW_MAGIC, 0x05, IFX_FLOW_irq_t) ++ ++/** ++ Clear individual interrupt status bits. Interrupt status indications can be read using \ref IFX_FLOW_IRQ_GET. ++ ++ \param IFX_FLOW_irq_t Pointer to ++ an \ref IFX_FLOW_irq_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++ ++*/ ++#define IFX_FLOW_IRQ_STATUS_CLEAR _IOW(IFX_FLOW_MAGIC, 0x06, IFX_FLOW_irq_t) ++ ++/*@}*/ /* FLOW_IOCTL_IRQ */ ++ ++/** \addtogroup FLOW_IOCTL_CLASSUNIT */ ++/*@{*/ ++ ++/** ++ This command writes a rule pattern and action to the table of the packet ++ classification engine. The pattern part describes the parameter to identify an ++ incoming packet to which the dedicated actions should be applied. ++ A rule can be read using the command \ref IFX_FLOW_PCE_RULE_READ. ++ ++ \param IFX_FLOW_PCE_rule_t Pointer to \ref IFX_FLOW_PCE_rule_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_FLOW_PCE_RULE_WRITE _IOW(IFX_FLOW_MAGIC, 0x07, IFX_FLOW_PCE_rule_t) ++ ++/** ++ This command allows the reading out of a rule pattern and action of the ++ packet classification engine. ++ A rule can be written using the command \ref IFX_FLOW_PCE_RULE_WRITE. ++ ++ \param IFX_FLOW_PCE_rule_t Pointer to \ref IFX_FLOW_PCE_rule_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_FLOW_PCE_RULE_READ _IOWR(IFX_FLOW_MAGIC, 0x08, IFX_FLOW_PCE_rule_t) ++ ++/** ++ This command deletes a complete rule from the packet classification engine. ++ A delete operation is done on the rule of a dedicated index 'nIndex'. ++ A rule can be written over using the command \ref IFX_FLOW_PCE_RULE_WRITE. ++ ++ \param IFX_FLOW_PCE_ruleDelete_t Pointer to \ref IFX_FLOW_PCE_ruleDelete_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_FLOW_PCE_RULE_DELETE _IOW(IFX_FLOW_MAGIC, 0x09, IFX_FLOW_PCE_ruleDelete_t) ++ ++/*@}*/ /* FLOW_IOCTL_CLASSUNIT */ ++ ++/** \addtogroup FLOW_IOCTL_OAM */ ++/*@{*/ ++ ++/** ++ Forces a hardware reset of the switch device or switch macro. The device ++ automatically comes back out of reset and contains the initial values. ++ All previous configurations are lost. ++ ++ \param IFX_FLOW_reset_t Pointer to an \ref IFX_FLOW_reset_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++ ++ \remarks Not supported for all devices ++*/ ++#define IFX_FLOW_RESET _IOW(IFX_FLOW_MAGIC, 0x0A, IFX_FLOW_reset_t) ++ ++/** ++ Read out additional traffic flow (RMON) counters. ++ The zero-based 'nPortId' structure element describes the physical switch ++ port for the requested statistic information. ++ ++ \param IFX_FLOW_RMON_extendGet_t Pointer to a pre-allocated ++ \ref IFX_FLOW_RMON_extendGet_t structure. The structure element 'nPortId' is ++ an input parameter that describes from which port to read the RMON counter. ++ All remaining structure elements are filled with the counter values. ++ The counter assignment needs to be done during the flow definition, ++ for example in \ref IFX_FLOW_PCE_RULE_WRITE. ++ ++ \remarks The function returns an error in case the given 'nPortId' is ++ out of range. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++#define IFX_FLOW_RMON_EXTEND_GET _IOWR(IFX_FLOW_MAGIC, 0x0B, IFX_FLOW_RMON_extendGet_t) ++ ++/*@}*/ /* FLOW_IOCTL_OAM */ ++ ++#endif /* _IFX_FLOW_FLOW_H_ */ +diff --git a/include/switch_api/ifx_ethsw_flow_core.h b/include/switch_api/ifx_ethsw_flow_core.h +new file mode 100644 +index 0000000..6a0eb14 +--- /dev/null ++++ b/include/switch_api/ifx_ethsw_flow_core.h +@@ -0,0 +1,254 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ \file ifx_ethsw_flow_core.h ++ \remarks FLOW Core Layer header file, for Infineon Ethernet switch ++ drivers ++ *****************************************************************************/ ++#ifndef _IFX_ETHSW_FLOW_CORE_H_ ++#define _IFX_ETHSW_FLOW_CORE_H_ ++ ++//#include "ifx_ethsw_api.h" ++#include "ifx_ethsw_reg_access.h" ++#include "ifx_ethsw_pce.h" ++ ++ ++/**********************************/ ++/* External Variables & Functions */ ++/**********************************/ ++// checked: extern IFX_ETHSW_HL_DRV_CTX_t gHlDrvCtx; ++#define MAX_PORT_NUMBER 12 /* including virtual ports*/ ++#define MULTICAST_HW_TABLE_MAX 64 ++#define MAC_ADDRESS_LENGTH 6 ++ ++#define IFX_HW_VLAN_MAP_TABLE_MAX 64 ++#define IFX_FLOW_VLAN_ENTRY_MAX IFX_HW_VLAN_MAP_TABLE_MAX ++#define IFX_FLOW_PORT_NUMBER_MAX 7 ++#define IFX_HW_MAC_TABLE_MAX 2048 ++#define IFX_FLOW_INTERNAL_PORT_NUMBER 2 ++#define IFX_FLOW_EXTERNAL_PORT_NUMBER 3 ++#define IFX_FLOW_MULTICAST_SW_TBL_SIZE 64 ++#define IFX_FLOW_MULTICAST_HW_TBL_SIZE 64 ++ ++ ++//#define VRX_PLATFORM_CPU_PORT 6 ++#define VRX_CPU_PORT 6 ++#define ARX_CPU_PORT 6 ++#define GHN_CPU_PORT 2 ++#define VRX_PLATFORM_CAP_SEGNENT 256 ++#define VRX_PLATFORM_CAP_FID 64 ++#define IFX_ETHSW_RMON_COUNTER_OFFSET 64 ++#define IFX_ETHSW_FLOW_TOP_REG_OFFSET 0xC40 ++#define IFX_ETHSW_MAX_PACKET_LENGTH 9600 ++#define IFX_ETHSW_MAC_BRIDGE_TABLE_INDEX 0xB ++#define IFX_FLOW_PORT_STATE_LISTENING_ONLY 0 ++#define IFX_FLOW_PORT_STATE_RX_ENABLE_TX_DISABLE 1 ++#define IFX_FLOW_PORT_STATE_RX_DISABLE_TX_ENABLE 2 ++#define IFX_FLOW_PORT_STATE_LEARNING 4 ++#define IFX_FLOW_PORT_STATE_FORWARDING_ENABLE 7 ++#define RMON_EXTEND_TRAFFIC_FLOW_COUNT_1 0x28 ++/*PHY Reg 0x4 */ ++#define PHY_AN_ADV_10HDX 0x20 ++#define PHY_AN_ADV_10FDX 0x40 ++#define PHY_AN_ADV_100HDX 0x80 ++#define PHY_AN_ADV_100FDX 0x100 ++/*PHY Reg 0x9 */ ++#define PHY_AN_ADV_1000HDX 0x100 ++#define PHY_AN_ADV_1000FDX 0x200 ++ ++ ++#define DEFAULT_AGING_TIMEOUT 300 ++/* Define Aging Counter Mantissa Value */ ++#define AGETIMER_1_DAY 0xFB75 ++#define AGETIMER_1_HOUR 0xA7BA ++#define AGETIMER_300_SEC 0xDF84 ++#define AGETIMER_10_SEC 0x784 ++#define AGETIMER_1_SEC 0xBF ++ ++/* Define Duplex Mode */ ++#define DUPLEX_AUTO 0 ++#define DUPLEX_EN 1 ++#define DUPLEX_DIS 3 ++ ++/** Description */ ++typedef struct { ++ /* Cap Type */ ++ IFX_ETHSW_capType_t Cap_Type; ++ /* Description String */ ++ IFX_char_t Desci[IFX_ETHSW_CAP_STRING_LEN]; ++}IFX_ETHSW_CapDesc_t; ++ ++typedef struct { ++ /* STP State */ ++ IFX_ETHSW_STP_PortState_t ifx_stp_state; ++ /* 8021X State */ ++ IFX_ETHSW_8021X_portState_t ifx_8021_state; ++ /* PEN Register */ ++ IFX_uint8_t pen_reg; ++ /* PSTATE Register */ ++ IFX_uint8_t pstate_reg; ++ /* LRN limit */ ++ IFX_uint8_t lrnlim; ++}PORT_STATE_t; ++ ++/** Description */ ++typedef struct ++{ ++ /* Port Enable */ ++ IFX_boolean_t bPortEnable; ++ /** Transparent Mode */ ++ IFX_boolean_t bTVM; ++ /* Learning Limit Action */ ++ IFX_boolean_t bLearningLimitAction; ++ /* Automatic MAC address table learning locking */ ++ IFX_boolean_t bLearningPortLocked; ++ /* Automatic MAC address table learning limitation */ ++ IFX_uint16_t nLearningLimit; ++ /* Port State */ ++ IFX_uint16_t nPortState; ++ /* Port State for STP */ ++ IFX_ETHSW_STP_PortState_t ifx_stp_state; ++ /* Port State for 8021.x */ ++ IFX_ETHSW_8021X_portState_t ifx_8021x_state; ++}IFX_FLOW_portConfig_t; ++ ++/** Description */ ++typedef struct ++{ ++ /* 8021x Port Forwarding State */ ++ IFX_ETHSW_portForward_t eForwardPort; ++ /* 8021X Forwarding Port ID*/ ++ IFX_uint8_t n8021X_ForwardPortId; ++ /* STP port State */ ++ IFX_ETHSW_portForward_t eSTPPortState; ++ /* STP Port ID */ ++ IFX_uint16_t nSTP_PortID; ++}IFX_FLOW_STP_8021X_t; ++ ++/** Description */ ++typedef struct ++{ ++ IFX_boolean_t valid; ++ /* VLAN ID */ ++ IFX_uint16_t vid; ++ /* Forward ID */ ++ IFX_uint32_t fid; ++ /* Port Member */ ++ IFX_uint16_t pm; ++ /* Tag Member */ ++ IFX_uint16_t tm; ++ /* VID reserved */ ++ IFX_boolean_t reserved; ++}IFX_FLOW_VLAN_tableEntry_t; ++ ++typedef struct ++{ ++ /* PortMap */ ++ /* Src IP MSB index*/ ++ IFX_uint16_t SrcIp_MSB_Index; ++ /* Dis IP MSB index*/ ++ IFX_uint16_t DisIp_MSB_Index; ++ /* Src IP LSB index*/ ++ IFX_uint16_t SrcIp_LSB_Index; ++ /* Dis IP LSB index*/ ++ IFX_uint16_t DisIp_LSB_Index; ++ /* PortMap */ ++ IFX_uint16_t PortMap; ++ /* Membber Mode */ ++ IFX_uint16_t eModeMember; ++ /* Valid */ ++ IFX_boolean_t valid; ++} IFX_MulticastSW_table_Entry_t; ++ ++/** Description */ ++typedef struct ++{ ++ /* eIGMP_Mode */ ++ IFX_uint16_t eIGMP_Mode; ++ /* bIGMPv3 */ ++ IFX_boolean_t bIGMPv3; ++ /* eForwardPort */ ++ IFX_uint16_t eForwardPort; ++ /* nForwardPortId */ ++ IFX_uint8_t nForwardPortId; ++ /* bCrossVLAN */ ++ IFX_boolean_t bCrossVLAN; ++ /* nCOS */ ++ IFX_uint8_t nClassOfService; ++ /* Multicast SW Table */ ++ IFX_MulticastSW_table_Entry_t multicast_sw_table[IFX_FLOW_MULTICAST_SW_TBL_SIZE]; ++ /* Multicast Router Port */ ++ IFX_uint16_t eRouterPort; ++ /* SW Table side */ ++ IFX_uint8_t nSwTblSize; ++}IFX_FLOW_IGMP_t; ++ ++typedef struct { ++ IFX_FLOW_devType_t eDev; ++ IFX_FLOW_portConfig_t PortConfig[IFX_FLOW_PORT_NUMBER_MAX]; ++ IFX_boolean_t bVLAN_Aware; ++ IFX_FLOW_VLAN_tableEntry_t VLAN_Table[IFX_HW_VLAN_MAP_TABLE_MAX]; ++ IFX_FLOW_STP_8021X_t STP_8021x_Config; ++ IFX_FLOW_IGMP_t IGMP_Flags; ++ IFX_PCE_t PCE_Handler; ++ IFX_void_t *pRAL_Dev; ++ IFX_uint8_t nPortNumber; ++ IFX_uint8_t nTotalPortNumber; ++ IFX_uint8_t nManagementPortNumber; ++ IFX_uint32_t MAC_AgeTimer; ++ IFX_boolean_t bResetCalled; ++ IFX_boolean_t bHW_InitCalled; ++ IFX_uint8_t vlan_table_index; ++ IFX_uint16_t mac_table_index; ++ IFX_uint16_t multi_hw_table_index; ++ IFX_uint16_t multi_sw_table_index; ++ IFX_uint8_t nCPU_Port; ++ IFX_uint8_t multi_routerport_counter; ++ IFX_uint8_t meter_cnt; ++#ifdef IFX_ETHSW_API_COC ++ IFX_void_t *pPMCtx; ++#endif ++} IFX_FLOW_switchDev_t; ++ ++typedef struct ++{ ++ IFX_void_t *pDev; ++ IFX_FLOW_devType_t eDev; ++}IFX_FLOW_switchCoreInit_t; ++ ++typedef struct ++{ ++ IFX_uint8_t nTable_Index; ++ IFX_uint8_t nOP; // operation (1:add, 2:delete) ++ IFX_uint16_t nVId; ++ IFX_uint32_t nFId; ++}IFX_FLOW_VLAN_Filter_registerOperation_t; ++ ++/**********************/ ++/* Function Prototype */ ++/**********************/ ++ ++/**********************/ ++/* Function Prototype */ ++/**********************/ ++IFX_return_t IFX_FLOW_VLAN_Table_Print ( IFX_void_t *pDevCtx ); ++IFX_uint8_t IFX_FLOW_VLAN_Table_Index_Find ( IFX_void_t *pDevCtx, IFX_uint16_t vid ); ++ ++IFX_void_t *IFX_FLOW_SwitchCoreInit(IFX_FLOW_switchCoreInit_t *pInit ); ++void IFX_FLOW_SwitchCoreCleanUP(IFX_void_t ); ++ ++IFX_boolean_t IFX_FLOW_PHY_mediumDetectStatusGet(IFX_void_t *pDevCtx, IFX_uint8_t nPortID); ++IFX_return_t IFX_FLOW_PHY_PDN_Set(IFX_void_t *pDevCtx, IFX_uint8_t PHYAD); ++IFX_return_t IFX_FLOW_PHY_PDN_Clear(IFX_void_t *pDevCtx, IFX_uint8_t nPHYAD); ++IFX_boolean_t IFX_FLOW_PHY_Link_Status_Get(IFX_void_t *pDevCtx, IFX_uint8_t nPortID); ++ ++extern IFX_uint32_t ifx_ethsw_ll_DirectAccessRead(IFX_void_t *pDevCtx, IFX_int16_t Offset, IFX_int16_t Shift, IFX_int16_t Size, IFX_uint32_t * value); ++extern IFX_return_t ifx_ethsw_ll_DirectAccessWrite(IFX_void_t *pDevCtx, IFX_int16_t Offset, IFX_int16_t Shift, IFX_int16_t Size, IFX_uint32_t value); ++ ++#endif /* _IFX_ETHSW_PSB6970_CORE_H_ */ +diff --git a/include/switch_api/ifx_ethsw_flow_ll.h b/include/switch_api/ifx_ethsw_flow_ll.h +new file mode 100644 +index 0000000..e7a45a6 +--- /dev/null ++++ b/include/switch_api/ifx_ethsw_flow_ll.h +@@ -0,0 +1,2015 @@ ++/**************************************************************************** ++ ++ Copyright 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++*****************************************************************************/ ++#ifndef ____INCLUDE_IFX_ETHSW_FLOW_LL_H ++#define ____INCLUDE_IFX_ETHSW_FLOW_LL_H ++ ++#include "ifx_ethsw.h" ++#include "ifx_ethsw_flow.h" ++ ++/* Group definitions for Doxygen */ ++/** \defgroup FLOW_LL Ethernet Switch Application Kernel Interface ++ This chapter describes the entire interface to access and ++ configure the services of the switch module in OS kernel space. */ ++/*@{*/ ++/** \defgroup FLOW_LL_BRIDGE Ethernet Bridging Functions ++ Ethernet bridging (or switching) is the basic task of the device. It ++ provides individual configurations per port and standard global ++ switch features. ++*/ ++/** \defgroup FLOW_LL_CLASSUNIT Packet Classification Engine ++ Configures and controls the classification unit of the XWAY VRX200 ++ and XWAY GRX200 Family hardware. ++*/ ++/** \defgroup FLOW_LL_DEBUG Debug Features ++ XWAY VRX200 and XWAY GRX200 Family specific features for system ++ integration and debug sessions. ++*/ ++/** \defgroup FLOW_LL_IRQ Interrupt Handling ++ Configure XWAY VRX200 and XWAY GRX200 Family specific hardware ++ support to generate interrupts ++ and read out the interrupt sources. ++*/ ++/** \defgroup FLOW_LL_MULTICAST Multicast Functions ++ IGMP/MLD snooping configuration and support for IGMPv1, IGMPv2, IGMPv3, ++ MLDv1, and MLDv2. ++*/ ++/** \defgroup FLOW_LL_OAM Operation, Administration, and Management Functions ++ This chapter summarizes the functions that are provided to monitor the ++ data traffic passing through the device. ++*/ ++/** \defgroup FLOW_LL_QOS Quality of Service Functions ++ Switch and port configuration for Quality of Service (QoS). ++*/ ++/** \defgroup FLOW_LL_VLAN VLAN Functions ++ This chapter describes VLAN bridging functionality. ++*/ ++/*@}*/ ++ ++/* ------------------------------------------------------------------------- */ ++/* Function Declaration */ ++/* ------------------------------------------------------------------------- */ ++ ++/** \addtogroup FLOW_LL_BRIDGE */ ++/*@{*/ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_8021X_EAPOL_RULE_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_8021X_EAPOL_Rule_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_8021X_EAPOL_RuleGet(IFX_void_t *pDevCtx, IFX_ETHSW_8021X_EAPOL_Rule_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_8021X_EAPOL_RULE_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_8021X_EAPOL_Rule_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_8021X_EAPOL_RuleSet(IFX_void_t *pDevCtx, IFX_ETHSW_8021X_EAPOL_Rule_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_8021X_PORT_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a ++ 802.1x port authorized state port ++ configuration \ref IFX_ETHSW_8021X_portCfg_t ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_8021X_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_8021X_portCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_8021X_PORT_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a ++ 802.1x port authorized state port ++ configuration \ref IFX_ETHSW_8021X_portCfg_t ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_8021X_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_8021X_portCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MAC_TABLE_CLEAR command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_MAC_TableClear(IFX_void_t *pDevCtx); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MAC_TABLE_ENTRY_ADD command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a MAC table entry ++ \ref IFX_ETHSW_MAC_tableAdd_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_MAC_TableEntryAdd(IFX_void_t *pDevCtx, IFX_ETHSW_MAC_tableAdd_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MAC_TABLE_ENTRY_QUERY command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a MAC table entry ++ \ref IFX_ETHSW_MAC_tableQuery_t structure that is filled out by the switch ++ implementation. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_MAC_TableEntryQuery(IFX_void_t *pDevCtx, IFX_ETHSW_MAC_tableQuery_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MAC_TABLE_ENTRY_READ command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a MAC table entry ++ \ref IFX_ETHSW_MAC_tableRead_t structure that is filled out by the switch ++ implementation. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_MAC_TableEntryRead(IFX_void_t *pDevCtx, IFX_ETHSW_MAC_tableRead_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MAC_TABLE_ENTRY_REMOVE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a MAC table entry ++ \ref IFX_ETHSW_MAC_tableRemove_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_MAC_TableEntryRemove(IFX_void_t *pDevCtx, IFX_ETHSW_MAC_tableRemove_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_STP_BPDU_RULE_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_STP_BPDU_Rule_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_STP_BPDU_RuleGet(IFX_void_t *pDevCtx, IFX_ETHSW_STP_BPDU_Rule_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_STP_BPDU_RULE_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_STP_BPDU_Rule_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_STP_BPDU_RuleSet(IFX_void_t *pDevCtx, IFX_ETHSW_STP_BPDU_Rule_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_STP_PORT_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_STP_portCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_STP_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_STP_portCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_STP_PORT_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_STP_portCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_STP_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_STP_portCfg_t *pPar); ++ ++/*@}*/ /* FLOW_LL_BRIDGE */ ++/** \addtogroup FLOW_LL_VLAN */ ++/*@{*/ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VLAN_ID_CREATE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_VLAN_IdCreate_t structure element. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_VLAN_IdCreate(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_IdCreate_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VLAN_ID_DELETE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to an ++ \ref IFX_ETHSW_VLAN_IdDelete_t structure element. ++ ++ \remarks A VLAN ID can only be removed in case it was created by ++ \ref IFX_ETHSW_VLAN_ID_CREATE and is currently not assigned ++ to any Ethernet port (done using \ref IFX_ETHSW_VLAN_PORT_MEMBER_ADD). ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_VLAN_IdDelete(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_IdDelete_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VLAN_ID_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_VLAN_IdGet_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_VLAN_IdGet(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_IdGet_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VLAN_PORT_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to an ++ \ref IFX_ETHSW_VLAN_portCfg_t structure element. Based on the parameter ++ 'nPortId', the switch API implementation fills out the remaining structure ++ elements. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_VLAN_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_portCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VLAN_PORT_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to an \ref IFX_ETHSW_VLAN_portCfg_t ++ structure element. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_VLAN_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_portCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VLAN_PORT_MEMBER_ADD command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_VLAN_portMemberAdd_t structure element. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_VLAN_PortMemberAdd(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_portMemberAdd_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VLAN_PORT_MEMBER_READ command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_VLAN_portMemberRead_t structure element. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_VLAN_PortMemberRead(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_portMemberRead_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VLAN_PORT_MEMBER_REMOVE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_VLAN_portMemberRemove_t structure element. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_VLAN_PortMemberRemove(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_portMemberRemove_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VLAN_RESERVED_ADD command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_VLAN_reserved_t structure element. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_VLAN_ReservedAdd(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_reserved_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VLAN_RESERVED_REMOVE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_VLAN_reserved_t structure element. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_VLAN_ReservedRemove(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_reserved_t *pPar); ++ ++/*@}*/ /* FLOW_LL_VLAN */ ++/** \addtogroup FLOW_LL_QOS */ ++/*@{*/ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_CLASS_DSCP_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the DSCP mapping parameter ++ \ref IFX_ETHSW_QoS_ClassDSCP_Cfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_ClassDSCP_Get(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_ClassDSCP_Cfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_CLASS_DSCP_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the DSCP mapping parameter ++ \ref IFX_ETHSW_QoS_ClassDSCP_Cfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_ClassDSCP_Set(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_ClassDSCP_Cfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_CLASS_PCP_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the PCP priority mapping parameter ++ \ref IFX_ETHSW_QoS_ClassPCP_Cfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_ClassPCP_Get(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_ClassPCP_Cfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_CLASS_PCP_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the PCP priority mapping parameter ++ \ref IFX_ETHSW_QoS_ClassPCP_Cfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_ClassPCP_Set(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_ClassPCP_Cfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_DSCP_CLASS_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the QoS filter parameters ++ \ref IFX_ETHSW_QoS_DSCP_ClassCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_DSCP_ClassGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_DSCP_ClassCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_DSCP_CLASS_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the QoS filter parameters ++ \ref IFX_ETHSW_QoS_DSCP_ClassCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_DSCP_ClassSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_DSCP_ClassCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_DSCP_DROP_PRECEDENCE_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the QoS ++ DSCP drop precedence parameters ++ \ref IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_DSCP_DropPrecedenceCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_DSCP_DROP_PRECEDENCE_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the QoS ++ DSCP drop precedence parameters ++ \ref IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_DSCP_DropPrecedenceCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_METER_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_meterCfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_MeterCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_meterCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_METER_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_meterCfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_MeterCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_meterCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_METER_PORT_ASSIGN command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_meterPort_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_MeterPortAssign(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_meterPort_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_METER_PORT_DEASSIGN command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_meterPort_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_MeterPortDeassign(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_meterPort_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_METER_PORT_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_meterPortGet_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_MeterPortGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_meterPortGet_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_PCP_CLASS_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the QoS filter parameters ++ \ref IFX_ETHSW_QoS_PCP_ClassCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_PCP_ClassGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_PCP_ClassCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_PCP_CLASS_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the QoS filter parameters ++ \ref IFX_ETHSW_QoS_PCP_ClassCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_PCP_ClassSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_PCP_ClassCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_PORT_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a ++ QOS port priority control configuration \ref IFX_ETHSW_QoS_portCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_portCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_PORT_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a ++ QOS port priority control configuration \ref IFX_ETHSW_QoS_portCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_portCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_PORT_REMARKING_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the QoS filter parameters ++ \ref IFX_ETHSW_QoS_portRemarkingCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_PortRemarkingCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_portRemarkingCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_PORT_REMARKING_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the remarking configuration ++ \ref IFX_ETHSW_QoS_portRemarkingCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_PortRemarkingCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_portRemarkingCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_QUEUE_PORT_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_queuePort_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_QueuePortGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_queuePort_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_QUEUE_PORT_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_queuePort_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_QueuePortSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_queuePort_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_SCHEDULER_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_schedulerCfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_SchedulerCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_schedulerCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_SCHEDULER_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_schedulerCfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_SchedulerCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_schedulerCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_SHAPER_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_ShaperCfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_ShaperCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_ShaperCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_SHAPER_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_ShaperCfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_ShaperCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_ShaperCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_SHAPER_QUEUE_ASSIGN command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_ShaperQueue_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_ShaperQueueAssign(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_ShaperQueue_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_SHAPER_QUEUE_DEASSIGN command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_ShaperQueue_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_ShaperQueueDeassign(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_ShaperQueue_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_SHAPER_QUEUE_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_ShaperQueueGet_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_ShaperQueueGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_ShaperQueueGet_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_STORM_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_stormCfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_StormCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_stormCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_STORM_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_stormCfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_StormCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_stormCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_WRED_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_WRED_Cfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_WredCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_WRED_Cfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_WRED_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_WRED_Cfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_WredCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_WRED_Cfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_WRED_QUEUE_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_WRED_QueueCfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_WredQueueCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_WRED_QueueCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_QOS_WRED_QUEUE_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the parameters ++ structure \ref IFX_ETHSW_QoS_WRED_QueueCfg_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_QoS_WredQueueCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_WRED_QueueCfg_t *pPar); ++ ++/*@}*/ /* FLOW_LL_QOS */ ++/** \addtogroup FLOW_LL_MULTICAST */ ++/*@{*/ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_ADD command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_multicastRouter_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_MulticastRouterPortAdd(IFX_void_t *pDevCtx, IFX_ETHSW_multicastRouter_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_READ command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_multicastRouterRead_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs (e.g. Ethernet port parameter out of range) ++*/ ++IFX_return_t IFX_FLOW_MulticastRouterPortRead(IFX_void_t *pDevCtx, IFX_ETHSW_multicastRouterRead_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_REMOVE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_multicastRouter_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs (e.g. Ethernet port parameter out of range) ++*/ ++IFX_return_t IFX_FLOW_MulticastRouterPortRemove(IFX_void_t *pDevCtx, IFX_ETHSW_multicastRouter_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MULTICAST_SNOOP_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the ++ multicast configuration \ref IFX_ETHSW_multicastSnoopCfg_t. ++ ++ \remarks IGMP/MLD snooping is disabled when ++ 'eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_SNOOPFORWARD'. ++ Then all other structure parameters are unused. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_MulticastSnoopCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_multicastSnoopCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MULTICAST_SNOOP_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to the ++ multicast configuration \ref IFX_ETHSW_multicastSnoopCfg_t. ++ ++ \remarks IGMP/MLD snooping is disabled when ++ 'eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_SNOOPFORWARD'. ++ Then all other structure parameters are unused. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_MulticastSnoopCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_multicastSnoopCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_ADD command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer ++ to \ref IFX_ETHSW_multicastTable_t. ++ ++ \remarks The Source IP parameter is ignored in case IGMPv3 support is ++ not enabled in the hardware. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_MulticastTableEntryAdd(IFX_void_t *pDevCtx, IFX_ETHSW_multicastTable_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_READ command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer ++ to \ref IFX_ETHSW_multicastTableRead_t. ++ ++ \remarks The 'bInitial' parameter is reset during the read operation. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_MulticastTableEntryRead(IFX_void_t *pDevCtx, IFX_ETHSW_multicastTableRead_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_REMOVE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer ++ to \ref IFX_ETHSW_multicastTable_t. ++ ++ \remarks The Source IP parameter is ignored in case IGMPv3 support is ++ not enabled in the hardware. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_MulticastTableEntryRemove(IFX_void_t *pDevCtx, IFX_ETHSW_multicastTable_t *pPar); ++ ++/*@}*/ /* FLOW_LL_MULTICAST */ ++/** \addtogroup FLOW_LL_OAM */ ++/*@{*/ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_CPU_PORT_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_CPU_PortCfg_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_CPU_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_CPU_PortCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_CPU_PORT_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_CPU_PortCfg_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_CPU_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_CPU_PortCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_CPU_PORT_EXTEND_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_CPU_PortExtendCfg_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++ ++*/ ++IFX_return_t IFX_FLOW_CPU_PortExtendCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_CPU_PortExtendCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_CPU_PORT_EXTEND_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_CPU_PortExtendCfg_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_CPU_PortExtendCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_CPU_PortExtendCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_CAP_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to pre-allocated capability ++ list structure \ref IFX_ETHSW_cap_t. ++ The switch API implementation fills out the structure with the supported ++ features, based on the provided 'nCapType' parameter. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++ ++*/ ++IFX_return_t IFX_FLOW_CapGet(IFX_void_t *pDevCtx, IFX_ETHSW_cap_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to an \ref IFX_ETHSW_cfg_t structure. ++ The structure is filled out by the switch implementation. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_CfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_cfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to an \ref IFX_ETHSW_cfg_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_CfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_cfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_DISABLE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_Disable(IFX_void_t *pDevCtx); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_ENABLE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_Enable(IFX_void_t *pDevCtx); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_HW_INIT command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to pre-allocated initialization structure ++ \ref IFX_ETHSW_HW_Init_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_HW_Init(IFX_void_t *pDevCtx, IFX_ETHSW_HW_Init_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MDIO_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_MDIO_cfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_MDIO_CfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_MDIO_cfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MDIO_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_MDIO_cfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_MDIO_CfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_MDIO_cfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MDIO_DATA_READ command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_MDIO_data_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_MDIO_DataRead(IFX_void_t *pDevCtx, IFX_ETHSW_MDIO_data_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MDIO_DATA_WRITE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_MDIO_data_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++ ++*/ ++IFX_return_t IFX_FLOW_MDIO_DataWrite(IFX_void_t *pDevCtx, IFX_ETHSW_MDIO_data_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MONITOR_PORT_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer ++ to \ref IFX_ETHSW_monitorPortCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_MonitorPortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_monitorPortCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_MONITOR_PORT_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer ++ to \ref IFX_ETHSW_monitorPortCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_MonitorPortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_monitorPortCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_PORT_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a port configuration ++ \ref IFX_ETHSW_portCfg_t structure to fill out by the driver. ++ The parameter 'nPortId' tells the driver which port parameter is requested. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_portCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_PORT_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to an \ref IFX_ETHSW_portCfg_t structure ++ to configure the switch port hardware. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_portCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_PORT_LINK_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_portLinkCfg_t structure to read out the port status. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_PortLinkCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_portLinkCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_PORT_LINK_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_portLinkCfg_t structure to set the port configuration. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_PortLinkCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_portLinkCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_PORT_PHY_ADDR_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_portPHY_Addr_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_PortPHY_AddrGet(IFX_void_t *pDevCtx, IFX_ETHSW_portPHY_Addr_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_PORT_PHY_QUERY command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_portPHY_Query_t structure to set the port configuration. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_PortPHY_Query(IFX_void_t *pDevCtx, IFX_ETHSW_portPHY_Query_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_PORT_RGMII_CLK_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_portRGMII_ClkCfg_t structure to set the port configuration. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_PortRGMII_ClkCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_portRGMII_ClkCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_PORT_RGMII_CLK_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_ETHSW_portRGMII_ClkCfg_t structure to set the port configuration. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_PortRGMII_ClkCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_portRGMII_ClkCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_PORT_REDIRECT_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer ++ to \ref IFX_ETHSW_portRedirectCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ \remarks Not all hardware platforms support this feature. The function ++ returns an error if this feature is not supported. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_PortRedirectGet(IFX_void_t *pDevCtx, IFX_ETHSW_portRedirectCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_PORT_REDIRECT_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer ++ to \ref IFX_ETHSW_portRedirectCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ \remarks Not all hardware platforms support this feature. The function ++ returns an error if this feature is not supported. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_PortRedirectSet(IFX_void_t *pDevCtx, IFX_ETHSW_portRedirectCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_RMON_CLEAR command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a pre-allocated ++ \ref IFX_ETHSW_RMON_clear_t structure. The structure element 'nPortId' is ++ an input parameter stating on which port to clear all RMON counters. ++ ++ \remarks The function returns an error in case the given 'nPortId' is ++ out of range. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_RMON_Clear(IFX_void_t *pDevCtx, IFX_ETHSW_RMON_clear_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_RMON_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to pre-allocated ++ \ref IFX_ETHSW_RMON_cnt_t structure. The structure element 'nPortId' is ++ an input parameter that describes from which port to read the RMON counter. ++ All remaining structure elements are filled with the counter values. ++ ++ \remarks The function returns an error in case the given 'nPortId' is ++ out of range. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_RMON_Get(IFX_void_t *pDevCtx, IFX_ETHSW_RMON_cnt_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_VERSION_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar* The parameter points to a ++ \ref IFX_ETHSW_version_t structure. ++ ++ \return Returns value as follows: ++ - IFX_SUCCESS: if successful ++ - IFX_ERROR: in case of an error ++ ++*/ ++IFX_return_t IFX_FLOW_VersionGet(IFX_void_t *pDevCtx, IFX_ETHSW_version_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_WOL_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_WoL_Cfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_WoL_CfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_WoL_Cfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_WOL_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_WoL_Cfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_WoL_CfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_WoL_Cfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_WOL_PORT_CFG_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_WoL_PortCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_WoL_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_WoL_PortCfg_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_ETHSW_WOL_PORT_CFG_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_ETHSW_WoL_PortCfg_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_WoL_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_WoL_PortCfg_t *pPar); ++ ++/*@}*/ /* FLOW_LL_OAM */ ++/** \addtogroup FLOW_LL_DEBUG */ ++/*@{*/ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_FLOW_REGISTER_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_FLOW_register_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_RegisterGet(IFX_void_t *pDevCtx, IFX_FLOW_register_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_FLOW_REGISTER_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_FLOW_register_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_RegisterSet(IFX_void_t *pDevCtx, IFX_FLOW_register_t *pPar); ++ ++/*@}*/ /* FLOW_LL_DEBUG */ ++/** \addtogroup FLOW_LL_IRQ */ ++/*@{*/ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_FLOW_IRQ_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_FLOW_irq_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++ ++*/ ++IFX_return_t IFX_FLOW_IrqGet(IFX_void_t *pDevCtx, IFX_FLOW_irq_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_FLOW_IRQ_MASK_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_FLOW_irq_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++ ++*/ ++IFX_return_t IFX_FLOW_IrqMaskGet(IFX_void_t *pDevCtx, IFX_FLOW_irq_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_FLOW_IRQ_MASK_SET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_FLOW_irq_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++ ++*/ ++IFX_return_t IFX_FLOW_IrqMaskSet(IFX_void_t *pDevCtx, IFX_FLOW_irq_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_FLOW_IRQ_STATUS_CLEAR command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to ++ an \ref IFX_FLOW_irq_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++ ++*/ ++IFX_return_t IFX_FLOW_IrqStatusClear(IFX_void_t *pDevCtx, IFX_FLOW_irq_t *pPar); ++ ++/*@}*/ /* FLOW_LL_IRQ */ ++/** \addtogroup FLOW_LL_CLASSUNIT */ ++/*@{*/ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_FLOW_PCE_RULE_DELETE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_FLOW_PCE_ruleDelete_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_PceRuleDelete(IFX_void_t *pDevCtx, IFX_FLOW_PCE_ruleDelete_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_FLOW_PCE_RULE_READ command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_FLOW_PCE_rule_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_PceRuleRead(IFX_void_t *pDevCtx, IFX_FLOW_PCE_rule_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_FLOW_PCE_RULE_WRITE command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to \ref IFX_FLOW_PCE_rule_t. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_PceRuleWrite(IFX_void_t *pDevCtx, IFX_FLOW_PCE_rule_t *pPar); ++ ++/*@}*/ /* FLOW_LL_CLASSUNIT */ ++/** \addtogroup FLOW_LL_OAM */ ++/*@{*/ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_FLOW_RMON_EXTEND_GET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to a pre-allocated ++ \ref IFX_FLOW_RMON_extendGet_t structure. The structure element 'nPortId' is ++ an input parameter that describes from which port to read the RMON counter. ++ All remaining structure elements are filled with the counter values. ++ The counter assignment needs to be done during the flow definition, ++ for example in \ref IFX_FLOW_PCE_RULE_WRITE. ++ ++ \remarks The function returns an error in case the given 'nPortId' is ++ out of range. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++*/ ++IFX_return_t IFX_FLOW_RMON_ExtendGet(IFX_void_t *pDevCtx, IFX_FLOW_RMON_extendGet_t *pPar); ++ ++/** ++ This is the switch API low-level function for ++ the \ref IFX_FLOW_RESET command. ++ ++ \param pDevCtx This parameter is a pointer to the device context ++ which contains all information related to this special instance of the device. ++ \param pPar Pointer to an \ref IFX_FLOW_reset_t structure. ++ ++ \remarks The function returns an error code in case an error occurs. ++ The error code is described in \ref IFX_ETHSW_status_t. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurs ++ ++ \remarks Not supported for all devices ++*/ ++IFX_return_t IFX_FLOW_Reset(IFX_void_t *pDevCtx, IFX_FLOW_reset_t *pPar); ++ ++/*@}*/ /* FLOW_LL_OAM */ ++#endif /* ____INCLUDE_IFX_ETHSW_FLOW_LL_H */ +diff --git a/include/switch_api/ifx_ethsw_init.h b/include/switch_api/ifx_ethsw_init.h +new file mode 100644 +index 0000000..db11c6e +--- /dev/null ++++ b/include/switch_api/ifx_ethsw_init.h +@@ -0,0 +1,29 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ \file ifx_ethsw_init.h ++ \remarks Generic switch API header file, for Infineon Ethernet switch ++ drivers ++ *****************************************************************************/ ++#ifndef _IFX_ETHSW_INIT_H_ ++#define _IFX_ETHSW_INIT_H_ ++ ++#include "ifx_ethsw_linux.h" ++#include "ifx_ethsw_PSB6970_core.h" ++#include "ifx_ethsw_flow_core.h" ++#include "ifx_ethsw_ral.h" ++#include "ifx_ethsw_rml.h" ++#include "ifx_ethsw_reg_access.h" ++ ++typedef struct { ++ IFX_uint8_t minorNum; ++ IFX_void_t *pCoreDev; ++} IFX_ETHSW_coreHandle_t; ++ ++#endif /* _IFX_ETHSW_INIT_H_ */ +diff --git a/include/switch_api/ifx_ethsw_kernel_api.h b/include/switch_api/ifx_ethsw_kernel_api.h +new file mode 100644 +index 0000000..a7edfec +--- /dev/null ++++ b/include/switch_api/ifx_ethsw_kernel_api.h +@@ -0,0 +1,80 @@ ++/**************************************************************************** ++ ++ Copyright 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++*****************************************************************************/ ++#ifndef _IFX_ETHSW_KERNEL_API_H_ ++#define _IFX_ETHSW_KERNEL_API_H_ ++ ++/* Group definitions for Doxygen */ ++/** \defgroup ETHSW_KERNELAPI Ethernet Switch Linux Kernel Interface ++ This chapter describes the entire interface to access and ++ configure the services of the Ethernet switch module ++ within the Linux kernel space. */ ++ ++/*@{*/ ++ ++/** Definition of the device handle that is retrieved during ++ the \ref ifx_ethsw_kopen call. This handle is used to access the switch ++ device while calling \ref ifx_ethsw_kioctl. */ ++typedef unsigned int IFX_ETHSW_HANDLE; ++ ++/** ++ Request a device handle for a dedicated Ethernet switch device. The switch ++ device is identified by the given device name (e.g. "/dev/switch/1"). ++ The device handle is the return value of this function. This handle is ++ used to access the switch parameter and features while ++ calling \ref ifx_ethsw_kioctl. Please call the function ++ \ref ifx_ethsw_kclose to release a device handle that is not needed anymore. ++ ++ \param name Pointer to the device name of the requested Ethernet switch device. ++ ++ \remarks The client kernel module should check the function return value. ++ A returned zero indicates that the resource allocation failed. ++ ++ \return Return the device handle in case the requested device is available. ++ It returns a zero in case the device does not exist or is blocked ++ by another application. ++*/ ++IFX_ETHSW_HANDLE ifx_ethsw_kopen(char *name); ++ ++/** ++ Calls the switch API driver implementation with the given command and the ++ parameter argument. The called Ethernet switch device is identified by the ++ given device handle. This handle was previously requested by ++ calling \ref ifx_ethsw_kopen. ++ ++ \param handle Ethernet switch device handle, given by \ref ifx_ethsw_kopen. ++ \param command Switch API command to perform. ++ \param arg Command arguments. This argument is basically a reference to ++ the command parameter structure. ++ ++ \remarks The commands and arguments are the same as normally used over ++ the Linux ioctl interface from user space. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurred. ++*/ ++int ifx_ethsw_kioctl(IFX_ETHSW_HANDLE handle, unsigned int command, unsigned int arg); ++ ++/** ++ Releases an Ethernet switch device handle which was previously ++ allocated by \ref ifx_ethsw_kopen. ++ ++ \param handle Ethernet switch device handle, given by \ref ifx_ethsw_kopen. ++ ++ \return Return value as follows: ++ - IFX_SUCCESS: if successful ++ - An error code in case an error occurred. ++*/ ++int ifx_ethsw_kclose(IFX_ETHSW_HANDLE handle); ++ ++/*@}*/ ++ ++#endif /* _IFX_ETHSW_KERNEL_API_H_ */ +diff --git a/include/switch_api/ifx_ethsw_linux.h b/include/switch_api/ifx_ethsw_linux.h +new file mode 100644 +index 0000000..b039bd7 +--- /dev/null ++++ b/include/switch_api/ifx_ethsw_linux.h +@@ -0,0 +1,64 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ \file ifx_ethsw_linux.h ++ \remarks Generic switch API header file, for Infineon Ethernet switch ++ drivers ++ *****************************************************************************/ ++#ifndef _IFX_ETHSW_LINUX_H_ ++#define _IFX_ETHSW_LINUX_H_ ++ ++#include "ifx_ethsw_api.h" ++/* function type declaration for the default IOCTL low-level function in ++ case the command cannot be found in the low-level function table, ++ or in case no low-level function table is provided.. */ ++typedef int (*IFX_ioctl_default_fkt) (void*, int, int); ++typedef struct ++{ ++ IFX_ETHSW_lowLevelFkts_t *pLlTable; ++ void *pLlHandle; ++ char paramBuffer[PARAM_BUFFER_SIZE]; ++ /** Default callback handler. This handler is called in case the command ++ cannot be found in the low-level function table, or in case no low-level ++ function table is provided. ++ Provide a 'NULL' pointer in case no default handler is provided. */ ++ IFX_ioctl_default_fkt default_handler; ++}IFX_ETHSW_ioctlHandle_t; ++ ++typedef struct ++{ ++ IFX_boolean_t bInternalSwitch; ++ /** Number of similar Low Level External Switch Devices */ ++ IFX_uint8_t nExternalSwitchNum; ++ IFX_ETHSW_ioctlHandle_t *pIoctlHandle; ++ /** Array of pEthSWDev pointers associated with this driver context */ ++ IFX_void_t *pEthSWDev[IFX_ETHSW_DEV_MAX]; ++} IFX_ETHSW_IOCTL_WRAPPER_CTX_t; ++ ++typedef struct ++{ ++ IFX_ETHSW_lowLevelFkts_t *pLlTable; ++ /** Default callback handler. This handler is called in case the command ++ cannot be found in the low-level function table, or in case no low-level ++ function table is provided. ++ Provide a 'NULL' pointer in case no default handler is provided. */ ++ IFX_ioctl_default_fkt default_handler; ++}IFX_ETHSW_IOCTL_wrapperInit_t; ++ ++typedef struct { ++ unsigned char minor_number; ++} IFX_ETHSW_devoneData_t; ++ ++IFX_return_t IFX_ETHSW_Drv_Register(IFX_uint32_t Major); ++IFX_return_t IFX_ETHSW_Drv_UnRegister (IFX_uint32_t Major); ++IFX_void_t *IFX_ETHSW_IOCTL_WrapperInit(IFX_ETHSW_IOCTL_wrapperInit_t *pInit); ++IFX_return_t IFX_ETHSW_IOCTL_WrapperDeviceAdd(IFX_ETHSW_IOCTL_WRAPPER_CTX_t *pIoctlDev, IFX_void_t *pCoreDev, IFX_uint8_t nMinorNum); ++IFX_return_t IFX_ETHSW_IOCTL_WrapperCleanUp(IFX_void_t); ++ ++#endif /* _IFX_ETHSW_LINUX_H_ */ +diff --git a/include/switch_api/ifx_ethsw_ll_fkt.h b/include/switch_api/ifx_ethsw_ll_fkt.h +new file mode 100644 +index 0000000..87168ee +--- /dev/null ++++ b/include/switch_api/ifx_ethsw_ll_fkt.h +@@ -0,0 +1,41 @@ ++/**************************************************************************** ++ ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++*****************************************************************************/ ++#ifndef _IFX_ETHSW_LL_FKT_H ++#define _IFX_ETHSW_LL_FKT_H ++ ++#include "ifx_types.h" ++ ++/* general declaration fits for all low-level functions. */ ++typedef IFX_return_t (*IFX_ll_fkt) (IFX_void_t *, IFX_uint32_t); ++typedef struct IFX_ETHSW_lowLevelFkts_t IFX_ETHSW_lowLevelFkts_t; ++ ++/* Switch API low-level function tables to map all supported IOCTL commands */ ++struct IFX_ETHSW_lowLevelFkts_t ++{ ++ /* Some device have multiple tables to split the generic switch API features ++ and the device specific switch API features. Additional tables, if exist, ++ can be found under this next pointer. Every table comes along with a ++ different 'nType' parameter to differentiate. */ ++ IFX_ETHSW_lowLevelFkts_t *pNext; ++ /* IOCTL type of all commands listed in the table. */ ++ IFX_uint16_t nType; ++ /* Number of low-level functions listed in the table. */ ++ IFX_uint32_t nNumFkts; ++ /* Pointer to the first entry of the ioctl number table. This table is used ++ to check if the given ioctl command fits the the found low-level function ++ pointer under 'pFkts'. */ ++ // IFX_uint32_t *pIoctlCmds; ++ /* Pointer to the first entry of the function table. Table size is given ++ by the parameter 'nNumFkts'. */ ++ IFX_ll_fkt *pFkts; ++}; ++ ++#endif /* #ifndef _IFX_ETHSW_LL_FKT_H */ +diff --git a/include/switch_api/ifx_ethsw_pce.h b/include/switch_api/ifx_ethsw_pce.h +new file mode 100644 +index 0000000..451e6c3 +--- /dev/null ++++ b/include/switch_api/ifx_ethsw_pce.h +@@ -0,0 +1,385 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ \file ifx_ethsw_pce.h ++ \remarks implement PCE header structure. ++ *****************************************************************************/ ++ ++#ifndef _IFX_ETHSW_PCE_H_ ++#define _IFX_ETHSW_PCE_H_ ++ ++#include "ifx_types.h" ++#include "ifx_ethsw_flow.h" ++#include "ifx_ethsw_api.h" ++ ++/* Definitions */ ++#ifndef IFX_DEBUG_PCE ++ #define IFX_DEBUG_PCE \ ++ { \ ++ printk("DEBUG:\n\tFile %s\n\tLine %d\n", __FILE__, __LINE__);\ ++ } ++#endif ++ ++#ifndef IFX_RETURN_PCETM ++ #define IFX_RETURN_PCETM \ ++ { \ ++ printk("ERROR:\n\tFile %s\n\tLine %d\n", __FILE__, __LINE__); \ ++ return (-1); \ ++ } ++#endif ++ ++#ifndef IFX_RETURN_PCE ++ #define IFX_RETURN_PCE \ ++ { \ ++ printk("ERROR:\n\tFile %s\n\tLine %d\n", __FILE__, __LINE__); \ ++ return (-1); \ ++ } ++#endif ++ ++#define IFX_PCE_PKG_LNG_TBL_SIZE 16 ++#define IFX_PCE_DASA_MAC_TBL_SIZE 64 ++#define IFX_PCE_APPL_TBL_SIZE 64 ++#define IFX_PCE_IP_DASA_MSB_TBL_SIZE 16 ++#define IFX_PCE_IP_DASA_LSB_TBL_SIZE 64 ++#define IFX_PCE_PTCL_TBL_SIZE 32 ++#define IFX_PCE_PPPOE_TBL_SIZE 16 ++#define IFX_PCE_VLAN_ACT_TBL_SIZE 64 ++ ++#define IFX_PCE_TBL_SIZE 64 ++ ++#define IFX_FLOW_PCE_MICROCODE_VALUES 64 ++#define NUM_OF_PORTS_INCLUDE_CPU_PORT 7 ++ ++/* Switch API Micro Code V0.3 */ ++// parser's microcode output field type ++enum { ++ ++ OUT_MAC0 = 0, ++ OUT_MAC1, ++ OUT_MAC2, ++ OUT_MAC3, ++ OUT_MAC4, ++ OUT_MAC5, ++ OUT_ETHTYP, ++ OUT_VTAG0, ++ OUT_VTAG1, ++ OUT_ITAG0, ++ OUT_ITAG1, /*10 */ ++ OUT_ITAG2, ++ OUT_ITAG3, ++ OUT_IP0, ++ OUT_IP1, ++ OUT_IP2, ++ OUT_IP3, ++ OUT_SIP0, ++ OUT_SIP1, ++ OUT_SIP2, ++ OUT_SIP3, /*20*/ ++ OUT_SIP4, ++ OUT_SIP5, ++ OUT_SIP6, ++ OUT_SIP7, ++ OUT_DIP0, ++ OUT_DIP1, ++ OUT_DIP2, ++ OUT_DIP3, ++ OUT_DIP4, ++ OUT_DIP5, /*30*/ ++ OUT_DIP6, ++ OUT_DIP7, ++ OUT_SESID, ++ OUT_PROT, ++ OUT_APP0, ++ OUT_APP1, ++ OUT_IGMP0, ++ OUT_IGMP1, ++ OUT_IPOFF, /*39*/ ++ OUT_NONE = 63 ++}; ++ ++// parser's microcode length type ++#define INSTR 0 ++#define IPV6 1 ++#define LENACCU 2 ++ ++// parser's microcode flag type ++enum { ++ FLAG_ITAG = 0, ++ FLAG_VLAN, ++ FLAG_SNAP, ++ FLAG_PPPOE, ++ FLAG_IPV6, ++ FLAG_IPV6FL, ++ FLAG_IPV4, ++ FLAG_IGMP, ++ FLAG_TU, ++ FLAG_HOP, ++ FLAG_NN1, /*10 */ ++ FLAG_NN2, ++ FLAG_END, ++ FLAG_NO, /*13*/ ++}; ++ ++typedef struct { ++ unsigned short val_3; ++ unsigned short val_2; ++ unsigned short val_1; ++ unsigned short val_0; ++} IFX_FLOW_PCE_MICROCODE_ROW; ++ ++typedef IFX_FLOW_PCE_MICROCODE_ROW IFX_FLOW_PCE_MICROCODE[IFX_FLOW_PCE_MICROCODE_VALUES]; ++ ++/** Provides the address of the configured/fetched lookup table. */ ++typedef enum ++{ ++ /** Parser microcode table */ ++ IFX_ETHSW_PCE_PARS_INDEX = 0x00, ++ IFX_ETHSW_PCE_ACTVLAN_INDEX = 0x01, ++ IFX_ETHSW_PCE_VLANMAP_INDEX = 0x02, ++ IFX_ETHSW_PCE_PPPOE_INDEX = 0x03, ++ IFX_ETHSW_PCE_PROTOCOL_INDEX = 0x04, ++ IFX_ETHSW_PCE_APPLICATION_INDEX = 0x05, ++ IFX_ETHSW_PCE_IP_DASA_MSB_INDEX = 0x06, ++ IFX_ETHSW_PCE_IP_DASA_LSB_INDEX = 0x07, ++ IFX_ETHSW_PCE_PACKET_INDEX = 0x08, ++ IFX_ETHSW_PCE_PCP_INDEX = 0x09, ++ IFX_ETHSW_PCE_DSCP_INDEX = 0x0A, ++ IFX_ETHSW_PCE_MAC_BRIDGE_INDEX = 0x0B, ++ IFX_ETHSW_PCE_MAC_DASA_INDEX = 0x0C, ++ IFX_ETHSW_PCE_MULTICAST_SW_INDEX= 0x0D, ++ IFX_ETHSW_PCE_MULTICAST_HW_INDEX= 0x0E, ++ IFX_ETHSW_PCE_TFLOW_INDEX = 0x0F, ++ IFX_ETHSW_PCE_REMARKING_INDEX = 0x10, ++ IFX_ETHSW_PCE_QUEUE_MAP_INDEX = 0x11, ++ IFX_ETHSW_PCE_METER_INS_0_INDEX = 0x12, ++ IFX_ETHSW_PCE_METER_INS_1_INDEX = 0x13 ++}LOOKUP_TABLE_ADDRESS_t; ++ ++ ++/** Description */ ++typedef enum ++{ ++ /** */ ++ IFX_ETHSW_LOOKUP_TABLE_ACCESS_OP_MODE_ADRD = 0, ++ IFX_ETHSW_LOOKUP_TABLE_ACCESS_OP_MODE_ADWR = 1, ++ IFX_ETHSW_LOOKUP_TABLE_ACCESS_OP_MODE_KSRD = 2, ++ IFX_ETHSW_LOOKUP_TABLE_ACCESS_OP_MODE_KSWR = 3 ++}LOOKUP_TABLE_ACCESS_OPERATION_MODE_t; ++ ++typedef struct ++{ ++ /* key values */ ++ IFX_uint16_t key[8]; ++ /* mask nipples valid for the keys */ ++ IFX_uint16_t mask; ++ /* values */ ++ IFX_uint16_t val[5]; ++ /* choose the related table */ ++ IFX_uint16_t table; ++ /* address index/offset inside the table (zero based couting) */ ++ IFX_uint16_t table_index; ++ /* type: mask (0) or range (1) */ ++ IFX_uint16_t type:1; ++ /* entry is valid (1) or invalid (0) */ ++ IFX_uint16_t valid:1; ++ /* entry belongs to group in case it is not zero */ ++ IFX_uint16_t group:4; ++}IFX_ETHSW_XWAYFLOW_PCE_TABLE_ENTRY_t; ++ ++ ++typedef struct ++{ ++ /* Packet length */ ++ IFX_uint16_t pkg_lng; ++ /* Packet length range, in number of bytes */ ++ IFX_uint16_t pkg_lng_rng; ++}IFX_PCE_PKG_LNG_TBL_t; ++ ++typedef struct ++{ ++ /* MAC Address */ ++ IFX_uint8_t mac[6]; ++ /* MAC Address Mask */ ++ IFX_uint16_t mac_mask; ++} IFX_PCE_DASA_MAC_TBL_t; ++ ++typedef struct ++{ ++ /* Application data */ ++ IFX_uint16_t appl_data; ++ /* Mode = mask: Application data mask/ Mode = range: Application data range */ ++ IFX_uint16_t mask_range; ++ /* Type Flag: 0 --> Mask/ 11-->Range */ ++ IFX_uint8_t mask_range_type; ++} IFX_PCE_APPL_TBL_t; ++ ++typedef struct ++{ ++ /* IP address byte 15:8 */ ++ IFX_uint8_t ip_msb[8]; ++ /* Nibble mask */ ++ IFX_uint16_t mask; ++}IFX_PCE_IP_DASA_MSB_TBL_t; ++ ++typedef struct ++{ ++ /* IP address byte 7:0 */ ++ IFX_uint8_t ip_lsb[8]; ++ /* Nibble mask */ ++ IFX_uint16_t mask; ++}IFX_PCE_IP_DASA_LSB_TBL_t; ++ ++typedef struct ++{ ++ union { ++ /* Ethertype */ ++ IFX_uint16_t ethertype; ++ struct { ++ /* Protocol */ ++ IFX_uint16_t protocol:8; ++ /* Protocol Flags */ ++ IFX_uint16_t protocol_flags:8; ++ } prot; ++ } key; ++ union { ++ /* Ethertype Mask */ ++ IFX_uint16_t ethertype_mask; ++ struct { ++ /* reserved */ ++ IFX_uint16_t res:12; ++ /* Protocol Mask */ ++ IFX_uint16_t protocol_mask:2; ++ /* Protocol Flag Mask */ ++ IFX_uint16_t protocol_flag_mask:2; ++ } prot; ++ } mask; ++}IFX_PCE_PTCL_TBL_t; ++ ++typedef struct ++{ ++ /* PPPoE session ID */ ++ IFX_uint16_t sess_id; ++}IFX_PCE_PPPOE_TBL_t; ++ ++typedef struct ++{ ++ /* DSCP value */ ++ IFX_uint16_t dscp:7; ++ /* PCP value */ ++ IFX_uint16_t pcp:4; ++ /* Packet length */ ++ IFX_uint16_t pkt_lng_idx:5; ++ /* Destination MAC address */ ++ IFX_uint16_t dst_mac_addr_idx:8; ++ /* Source MAC address */ ++ IFX_uint16_t src_mac_addr_idx:8; ++ /* Destination Application field */ ++ IFX_uint16_t dst_appl_fld_idx:8; ++ /* Source Application field */ ++ IFX_uint16_t src_appl_fld_idx:8; ++ /* DIP MSB */ ++ IFX_uint16_t dip_msb_idx:8; ++ /* DIP LSB */ ++ IFX_uint16_t dip_lsb_idx:8; ++ /* SIP MSB */ ++ IFX_uint16_t sip_msb_idx:8; ++ /* SIP LSB */ ++ IFX_uint16_t sip_lsb_idx:8; ++ /* IP protocol */ ++ IFX_uint16_t ip_prot_idx:8; ++ /* Ethertype */ ++ IFX_uint16_t ethertype_idx:8; ++ /* PPPoE */ ++ IFX_uint16_t pppoe_idx:5; ++ /* VLAN */ ++ IFX_uint16_t vlan_idx:7; ++ /* Port ID */ ++ IFX_uint16_t port_id:8; ++}IFX_PCE_TBL_t; ++ ++typedef struct ++{ ++ /* table reference counter */ ++ IFX_uint16_t pkg_lng_tbl_cnt[IFX_PCE_PKG_LNG_TBL_SIZE]; ++ IFX_uint16_t dasa_mac_tbl_cnt[IFX_PCE_DASA_MAC_TBL_SIZE]; ++ IFX_uint16_t appl_tbl_cnt[IFX_PCE_APPL_TBL_SIZE]; ++ IFX_uint16_t ip_dasa_msb_tbl_cnt[IFX_PCE_IP_DASA_MSB_TBL_SIZE]; ++ IFX_uint16_t ip_dasa_lsb_tbl_cnt[IFX_PCE_IP_DASA_LSB_TBL_SIZE]; ++ IFX_uint16_t ptcl_tbl_cnt[IFX_PCE_PTCL_TBL_SIZE]; ++ IFX_uint16_t pppoe_tbl_cnt[IFX_PCE_PPPOE_TBL_SIZE]; ++ IFX_uint16_t vlan_act_tbl_cnt[IFX_PCE_VLAN_ACT_TBL_SIZE]; ++ /* cached tables */ ++ IFX_PCE_PKG_LNG_TBL_t pkg_lng_tbl[IFX_PCE_PKG_LNG_TBL_SIZE]; ++ IFX_PCE_DASA_MAC_TBL_t dasa_mac_tbl[IFX_PCE_DASA_MAC_TBL_SIZE]; ++ IFX_PCE_APPL_TBL_t appl_tbl[IFX_PCE_APPL_TBL_SIZE]; ++ IFX_PCE_IP_DASA_MSB_TBL_t ip_dasa_msb_tbl[IFX_PCE_IP_DASA_MSB_TBL_SIZE]; ++ IFX_PCE_IP_DASA_LSB_TBL_t ip_dasa_lsb_tbl[IFX_PCE_IP_DASA_LSB_TBL_SIZE]; ++ IFX_PCE_PTCL_TBL_t ptcl_tbl[IFX_PCE_PTCL_TBL_SIZE]; ++ IFX_PCE_PPPOE_TBL_t pppoe_tbl[IFX_PCE_PPPOE_TBL_SIZE]; ++}IFX_PCE_HANDLE_t; ++ ++typedef struct ++{ ++ /* Parameter for the sub-tables */ ++ IFX_PCE_HANDLE_t pce_sub_tbl; ++ IFX_PCE_TBL_t pce_tbl[IFX_PCE_TBL_SIZE]; ++ IFX_FLOW_PCE_action_t pce_act[IFX_PCE_TBL_SIZE]; ++ /* set if the entry is used */ ++ IFX_uint8_t pce_tbl_used[IFX_PCE_TBL_SIZE]; ++} IFX_PCE_t; ++ ++/* Function Declaration */ ++IFX_int32_t ifx_pce_table_init(IFX_PCE_t *pPCEHandle); ++IFX_int32_t ifx_pce_tm_pkg_lng_tbl_write(IFX_PCE_HANDLE_t *pTmHandle, IFX_PCE_PKG_LNG_TBL_t *pPar); ++IFX_int32_t ifx_pce_tm_pkg_lng_tbl_delete(IFX_PCE_HANDLE_t *pTmHandle, IFX_uint32_t index); ++IFX_int32_t ifx_pce_tm_pkg_lng_tbl_read(IFX_PCE_HANDLE_t *pTmHandle, IFX_int32_t index, IFX_PCE_PKG_LNG_TBL_t *pPar); ++IFX_int32_t ifx_pce_tm_dasa_mac_tbl_write(IFX_PCE_HANDLE_t *pTmHandle, IFX_PCE_DASA_MAC_TBL_t *pPar); ++IFX_int32_t ifx_pce_tm_dasa_mac_tbl_delete(IFX_PCE_HANDLE_t *pTmHandle, IFX_uint32_t index); ++IFX_int32_t ifx_pce_tm_dasa_mac_tbl_read(IFX_PCE_HANDLE_t *pTmHandle, IFX_int32_t index, IFX_PCE_DASA_MAC_TBL_t *pPar); ++IFX_int32_t ifx_pce_tm_appl_tbl_write(IFX_PCE_HANDLE_t *pTmHandle, IFX_PCE_APPL_TBL_t *pPar); ++IFX_int32_t ifx_pce_tm_appl_tbl_delete(IFX_PCE_HANDLE_t *pTmHandle, IFX_uint32_t index); ++IFX_int32_t ifx_pce_tm_appl_tbl_read(IFX_PCE_HANDLE_t *pTmHandle, IFX_int32_t index, IFX_PCE_APPL_TBL_t *pPar); ++IFX_int32_t ifx_pce_tm_ip_dasa_msb_tbl_write(IFX_PCE_HANDLE_t *pTmHandle, IFX_PCE_IP_DASA_MSB_TBL_t *pPar); ++IFX_int32_t ifx_pce_tm_ip_dasa_msb_tbl_delete(IFX_PCE_HANDLE_t *pTmHandle, IFX_uint32_t index); ++IFX_int32_t ifx_pce_tm_ip_dasa_msb_tbl_read(IFX_PCE_HANDLE_t *pTmHandle, IFX_int32_t index, IFX_PCE_IP_DASA_MSB_TBL_t *pPar); ++IFX_int32_t ifx_pce_tm_ip_dasa_lsb_tbl_write(IFX_PCE_HANDLE_t *pTmHandle, IFX_PCE_IP_DASA_LSB_TBL_t *pPar); ++IFX_int32_t ifx_pce_tm_ip_dasa_lsb_tbl_delete(IFX_PCE_HANDLE_t *pTmHandle, IFX_uint32_t index); ++IFX_int32_t ifx_pce_tm_ip_dasa_lsb_tbl_idx_delete(IFX_PCE_HANDLE_t *pTmHandle, IFX_uint32_t index); ++IFX_int32_t ifx_pce_tm_ip_dasa_msb_tbl_idx_delete(IFX_PCE_HANDLE_t *pTmHandle,IFX_uint32_t index); ++IFX_int32_t ifx_pce_tm_ip_dasa_lsb_tbl_read(IFX_PCE_HANDLE_t *pTmHandle, IFX_int32_t index, IFX_PCE_IP_DASA_LSB_TBL_t *pPar); ++IFX_int32_t ifx_pce_tm_ip_dasa_lsb_tbl_index_search(IFX_PCE_HANDLE_t *pTmHandle, IFX_PCE_IP_DASA_LSB_TBL_t *pPar); ++IFX_int32_t ifx_pce_tm_ptcl_tbl_write(IFX_PCE_HANDLE_t *pTmHandle, IFX_PCE_PTCL_TBL_t *pPar); ++IFX_int32_t ifx_pce_tm_ptcl_tbl_delete(IFX_PCE_HANDLE_t *pTmHandle, IFX_uint32_t index); ++IFX_int32_t ifx_pce_tm_ptcl_tbl_read(IFX_PCE_HANDLE_t *pTmHandle, IFX_int32_t index, IFX_PCE_PTCL_TBL_t *pPar); ++IFX_int32_t ifx_pce_tm_pppoe_tbl_write(IFX_PCE_HANDLE_t *pTmHandle, IFX_PCE_PPPOE_TBL_t *pPar); ++IFX_int32_t ifx_pce_tm_pppoe_tbl_delete(IFX_PCE_HANDLE_t *pTmHandle, IFX_uint32_t index); ++IFX_int32_t ifx_pce_tm_pppoe_tbl_read(IFX_PCE_HANDLE_t *pTmHandle, IFX_int32_t index, IFX_PCE_PPPOE_TBL_t *pPar); ++IFX_int32_t ifx_pce_tm_vlan_act_tbl_delete(IFX_PCE_HANDLE_t *pTmHandle, IFX_uint32_t index); ++IFX_int32_t ifx_pce_tm_print_tables(IFX_PCE_HANDLE_t *pTmHandle); ++IFX_int32_t get_ifx_pce_tm_vlan_act_tbl_index(IFX_PCE_HANDLE_t *pTmHandle,IFX_uint8_t index); ++IFX_int32_t ifx_pce_pattern_delete(IFX_PCE_t *pHandle, IFX_uint32_t index); ++IFX_int32_t ifx_pce_action_delete(IFX_PCE_t *pHandle, IFX_uint32_t index); ++IFX_int32_t ifx_pce_rule_read(IFX_PCE_t *pHandle, IFX_FLOW_PCE_rule_t *pPar); ++IFX_int32_t ifx_pce_rule_write(IFX_PCE_t *pHandle, IFX_FLOW_PCE_rule_t *pPar); ++IFX_return_t ifx_ethsw_xwayflow_pce_table_write(IFX_void_t *pDevCtx, IFX_ETHSW_XWAYFLOW_PCE_TABLE_ENTRY_t *pData); ++IFX_return_t ifx_ethsw_xwayflow_pce_table_read(IFX_void_t *pDevCtx, IFX_ETHSW_XWAYFLOW_PCE_TABLE_ENTRY_t *pData); ++IFX_return_t ifx_ethsw_xwayflow_pce_table_cam_write(IFX_void_t *pDevCtx, IFX_ETHSW_XWAYFLOW_PCE_TABLE_ENTRY_t *pData); ++ ++IFX_int32_t find_software_tbl_entry(IFX_PCE_HANDLE_t *pTmHandle, IFX_PCE_IP_DASA_LSB_TBL_t *pPar); ++IFX_int32_t find_software_msb_tbl_entry(IFX_PCE_HANDLE_t *pTmHandle, IFX_PCE_IP_DASA_MSB_TBL_t *pPar); ++extern IFX_uint32_t ifx_ethsw_ll_DirectAccessRead(IFX_void_t *pDevCtx, IFX_int16_t Offset, IFX_int16_t Shift, IFX_int16_t Size, IFX_uint32_t * value); ++extern IFX_return_t ifx_ethsw_ll_DirectAccessWrite(IFX_void_t *pDevCtx, IFX_int16_t Offset, IFX_int16_t Shift, IFX_int16_t Size, IFX_uint32_t value); ++ ++/* Micro Code Load */ ++//IFX_return_t IFX_VR9_Switch_PCE_Micro_Code_Int(IFX_void_t); ++IFX_return_t IFX_VR9_Switch_PCE_Micro_Code_Int(IFX_void_t *pDevCtx); ++ ++/* Debug Funtion */ ++IFX_int32_t ifx_pce_print_tables(IFX_PCE_t *pHandle); ++#endif /* _IFX_ETHSW_PCE_H_ */ +diff --git a/include/switch_api/ifx_ethsw_pm.h b/include/switch_api/ifx_ethsw_pm.h +new file mode 100644 +index 0000000..f021020 +--- /dev/null ++++ b/include/switch_api/ifx_ethsw_pm.h +@@ -0,0 +1,63 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ \file ifx_ethsw_pm.h ++ \remarks power management header file ++ ****************************************************************************/ ++#ifndef _IFX_ETHSW_PM_H_ ++#define _IFX_ETHSW_PM_H_ ++ ++#include ++#include ++#include ++ ++#if 0 ++// Support power management of external Tantos3G ++typedef enum ++{ ++ IFX_ETHSW_PM_MODULENR_TANTOS3G = 1, ++ IFX_ETHSW_PM_MODULENR_GSWIP = 2, ++ IFX_ETHSW_PM_MODULENR_MAX = 3 ++} IFX_PSB6970__t; ++#endif ++ ++#define IFX_ETHSW_PM_MODULENR_TANTOS3G 0x10 ++#define IFX_ETHSW_PM_MODULENR_GSWIP 0x20 ++ ++typedef struct { ++ IFX_void_t *pCoreDev; ++ IFX_boolean_t bPMThreadEnable; ++#ifndef IFXOS_SUPPORT ++ struct task_struct *pPMThread; ++ wait_queue_head_t PHY_wait; ++#endif ++#ifdef CONFIG_IFX_ETHSW_API_COC_PMCU ++ IFX_void_t *pPmcuCtx; ++#endif ++ IFX_void_t *pPlatCtx; ++} IFX_ETHSW_PM_CTX_t; ++ ++#ifdef IFXOS_SUPPORT ++ #define IFX_ETHSW_STACKSIZE 2048 ++ #define IFX_ETHSW_PRIORITY 64 ++ IFXOS_ThreadCtrl_t PHY_ThrCntrl; ++#endif ++ ++IFX_void_t *IFX_ETHSW_PM_powerManegementInit(IFX_void_t *pDev, IFX_uint8_t nModuleNr); ++IFX_return_t IFX_ETHSW_PM_powerManegementCleanUp(IFX_void_t *pCtx); ++IFX_boolean_t IFX_ETHSW_PM_powerManegementStatusGet(IFX_void_t *pCtx); ++IFX_return_t IFX_ETHSW_powerStateD0(IFX_void_t *pCtx); ++IFX_return_t IFX_ETHSW_powerStateD1(IFX_void_t *pCtx); ++IFX_return_t IFX_ETHSW_powerManagementActivated(IFX_void_t *pCtx); ++IFX_return_t IFX_ETHSW_powerManagementDeActivated(IFX_void_t *pCtx); ++IFX_return_t IFX_ETHSW_PM_linkForceSet(IFX_void_t *pCtx, IFX_uint8_t nPHYIdx, IFX_boolean_t bLinkForce); ++//IFX_return_t IFX_PSB6970_allPHY_powerup(IFX_void_t *pDevCtx); ++//IFX_return_t IFX_PSB6970_allPHY_powerdown(IFX_void_t *pDevCtx); ++ ++#endif /* _IFX_ETHSW_PM_H_ */ +diff --git a/include/switch_api/ifx_ethsw_pm_plat.h b/include/switch_api/ifx_ethsw_pm_plat.h +new file mode 100644 +index 0000000..3175cd6 +--- /dev/null ++++ b/include/switch_api/ifx_ethsw_pm_plat.h +@@ -0,0 +1,63 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ \file ifx_ethsw_pm_plat.h ++ \remarks power management header file for platform dependency. ++ ****************************************************************************/ ++#ifndef _IFX_ETHSW_PM_PLAT_H_ ++#define _IFX_ETHSW_PM_PLAT_H_ ++#include ++ ++/*********************************************/ ++/* Structure and Enumeration Type Defintions */ ++/*********************************************/ ++#if defined(CONFIG_VR9) ++ #define PHY_NO 6 ++#endif /* CONFIG_VR9 */ ++#if defined(CONFIG_AR9) ++ #define PHY_NO 5 ++#endif /* CONFIG_AR9 */ ++typedef struct { ++ IFX_boolean_t bStatus; // for debug ++ IFX_boolean_t bLinkForce; ++ IFX_uint8_t nPHYAddr; ++} IFX_ETHSW_PHY_t; ++ ++typedef struct { ++ IFX_void_t *pPMCtx; ++ IFX_uint8_t nPHYNum; ++ IFX_ETHSW_PHY_t PHY[PHY_NO]; ++} IFX_ETHSW_PMPlatCTX_t; ++ ++/************************/ ++/* Function Propotype */ ++/************************/ ++IFX_void_t *IFX_ETHSW_PM_PLAT_Init(IFX_void_t *pCtx, IFX_uint8_t nModuleNr); ++IFX_return_t IFX_ETHSW_PM_PLAT_CleanUp(IFX_void_t *pCtx); ++IFX_boolean_t IFX_ETHSW_PHY_MDstatusGet(IFX_void_t *pDevCtx, IFX_uint8_t nPHYAddr); ++IFX_boolean_t IFX_ETHSW_PHY_statusSet(IFX_void_t *pDevCtx, IFX_uint8_t nPHYIdx, IFX_boolean_t bStatus); ++IFX_boolean_t IFX_ETHSW_PHY_statusGet(IFX_void_t *pDevCtx, IFX_uint8_t nPHYIdx); ++IFX_return_t IFX_ETHSW_PHY_powerDown(IFX_void_t *pDevCtx, IFX_uint8_t nPHYNum); ++IFX_return_t IFX_ETHSW_PHY_powerUp(IFX_void_t *pDevCtx, IFX_uint8_t nPHYNum); ++IFX_return_t IFX_ETHSW_AllPHY_powerDown(IFX_void_t *pDevCtx, IFX_void_t *pPlatCtx); ++IFX_return_t IFX_ETHSW_AllPHY_powerUp(IFX_void_t *pDevCtx, IFX_void_t *pPlatCtx); ++IFX_int_t IFX_ETHSW_AllPHY_LinkStatus(IFX_void_t *pDevCtx, IFX_void_t *pPlatCtx); ++IFX_return_t IFX_ETHSW_PM_PLAT_linkForceSet(IFX_void_t *pPlatCtx, IFX_uint8_t nPHYIdx, IFX_boolean_t bLinkForce); ++IFX_return_t IFX_ETHSW_PM_PLAT_linkForceGet(IFX_void_t *pPlatCtx, IFX_uint8_t nPHYIdx, IFX_boolean_t *pLinkForce); ++IFX_return_t IFX_ETHSW_PHY_Link_Up(IFX_void_t *pCtx); ++IFX_int_t IFX_ETHSW_PHY_Link_Status(IFX_void_t *pCtx); ++IFX_return_t IFX_ETHSW_PHY_Link_Down(IFX_void_t *pCtx); ++IFX_return_t IFX_ETHSW_EXT_PHY_Link_Up(IFX_void_t *pCtx) ; ++IFX_return_t IFX_ETHSW_INT_PHY_Link_Down(IFX_void_t *pCtx); ++IFX_return_t IFX_ETHSW_EXT_PHY_Link_Down(IFX_void_t *pCtx); ++IFX_return_t IFX_ETHSW_INT_PHY_Link_Up(IFX_void_t *pCtx); ++IFX_return_t IFX_ETHSW_AllintPHY_powerUp(IFX_void_t *pDevCtx, IFX_void_t *pPlatCtx); ++IFX_return_t IFX_ETHSW_AllextPHY_powerUp(IFX_void_t *pDevCtx, IFX_void_t *pPlatCtx); ++ ++#endif /* _IFX_ETHSW_PM_PLAT_H_ */ +diff --git a/include/switch_api/ifx_ethsw_pm_pmcu.h b/include/switch_api/ifx_ethsw_pm_pmcu.h +new file mode 100644 +index 0000000..a1e3198 +--- /dev/null ++++ b/include/switch_api/ifx_ethsw_pm_pmcu.h +@@ -0,0 +1,36 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ \file ifx_ethsw_pm_pmcu.h ++ \remarks power management header file ++ ****************************************************************************/ ++#ifndef _IFX_ETHSW_PM_PMCU_H_ ++#define _IFX_ETHSW_PM_PMCU_H_ ++ ++#include ++#include ++ ++/*********************************************/ ++/* Structure and Enumeration Type Defintions */ ++/*********************************************/ ++typedef struct { ++ IFX_void_t *pPMCtx; ++ IFX_PMCU_STATE_t ePMCU_State; ++ IFX_uint8_t nModuleNr; ++} IFX_ETHSW_PM_PMCUCtx_t; ++ ++ ++/************************/ ++/* Function Declaration */ ++/************************/ ++IFX_void_t *IFX_ETHSW_PM_PMCU_Init(IFX_void_t *pCtx, IFX_uint8_t nModuleNr); ++IFX_return_t IFX_ETHSW_PM_PMCU_CleanUp(IFX_void_t *pCtx); ++IFX_return_t IFX_ETHSW_PM_PMCU_StateReq(IFX_PMCU_STATE_t newState); ++ ++#endif /* _IFX_ETHSW_PM_PMCU_H_ */ +diff --git a/include/switch_api/ifx_ethsw_ral.h b/include/switch_api/ifx_ethsw_ral.h +new file mode 100644 +index 0000000..20c7094 +--- /dev/null ++++ b/include/switch_api/ifx_ethsw_ral.h +@@ -0,0 +1,56 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ \file ifx_ethsw_ral.h ++ \remarks Register Access Layer header file, for Infineon Ethernet switch ++ drivers ++ *****************************************************************************/ ++#ifndef _IFX_ETHSW_RAL_H_ ++#define _IFX_ETHSW_RAL_H_ ++ ++#include "ifx_ethsw_api.h" ++ ++#define REG32_ACCESS(addr) *((volatile IFX_int32_t *)(addr)) ++ ++#define IFX_PSB6970_AR9_BASEADDR (KSEG1 | 0x1E108000) ++#define IFX_PSB6970_TANTOS_3G_BASEADDR (KSEG1 | 0x1E1080CC) ++#define IFX_DANUBE_PPE_BASEADDR (KSEG1 | 0x1E191804) ++#define IFX_AMAZON_SE_PPE_BASEADDR (KSEG1 | 0x1E191804) ++ ++#define IFX_PSB6970_MDIO_OP_SHIFT 10 ++#define IFX_PSB6970_MDIO_MBUSY_SHIFT 15 ++#define IFX_PSB6970_MDIO_WD_SHIFT 16 ++#define IFX_PSB6970_MDIO_READ_OPERATION 0x02 ++#define IFX_PSB6970_MDIO_WRITE_OPERATION 0x01 ++ ++#define IFX_DANUBE_MDIO_RA_SHIFT 31 ++#define IFX_DANUBE_MDIO_RW_SHIFT 30 ++#define IFX_DANUBE_MDIO_REGADDR_SHIFT 16 ++#define IFX_AMAZON_SE_MDIO_RA_SHIFT 31 ++#define IFX_AMAZON_SE_MDIO_RW_SHIFT 30 ++#define IFX_AMAZON_SE_MDIO_REGADDR_SHIFT 16 ++typedef struct ++{ ++ IFX_return_t (* register_write)(IFX_void_t *, IFX_int32_t, IFX_uint32_t); ++ IFX_return_t (* register_read)(IFX_void_t *, IFX_int32_t, IFX_uint32_t *); ++ IFX_PSB6970_devType_t eDev; ++ IFX_uint32_t nBaseAddress; ++} IFX_PSB6970_RAL_Dev_t; ++ ++typedef struct ++{ ++ IFX_PSB6970_devType_t eDev; ++}IFX_PSB6970_RAL_Init_t; ++ ++IFX_return_t IFX_PSB6970_RAL_Register_DirectRead(IFX_void_t *pDevCtx , IFX_int32_t RegAddr, IFX_uint32_t * value); ++IFX_return_t IFX_PSB6970_RAL_Register_DirectWrite(IFX_void_t *pDevCtx , IFX_int32_t RegAddr, IFX_uint32_t value); ++IFX_return_t IFX_PSB6970_RAL_Register_MDIORead(IFX_void_t *pDevCtx , IFX_int32_t RegAddr, IFX_uint32_t * value); ++IFX_return_t IFX_PSB6970_RAL_Register_MDIOWrite(IFX_void_t *pDevCtx , IFX_int32_t RegAddr, IFX_uint32_t value); ++IFX_void_t *IFX_PSB6970_RAL_init(IFX_PSB6970_RAL_Init_t *pInit); ++#endif /* _IFX_ETHSW_RAL_H_ */ +diff --git a/include/switch_api/ifx_ethsw_reg_access.h b/include/switch_api/ifx_ethsw_reg_access.h +new file mode 100644 +index 0000000..f2f00ce +--- /dev/null ++++ b/include/switch_api/ifx_ethsw_reg_access.h +@@ -0,0 +1,38 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ \file ifx_ethsw_reg_access.h" ++ \remarks ++ *****************************************************************************/ ++#ifndef _IFX_ETHSW_REG_ACCESS_H ++#define _IFX_ETHSW_REG_ACCESS_H ++ ++#include "ifx_ethsw_api.h" ++#include "ifx_ethsw_vr9_reg_access.h" ++ ++#define VR9_BASE_ADDRESS (KSEG1 | 0x1E108000) ++#define VR9_REG32_ACCESS(addr) *((volatile IFX_int32_t *)(addr)) ++ ++typedef struct ++{ ++ IFX_return_t (* register_write)(IFX_void_t *, IFX_int16_t, IFX_int16_t, IFX_int16_t, IFX_uint32_t); ++ IFX_uint32_t (* register_read)(IFX_void_t *, IFX_int16_t , IFX_int16_t , IFX_int16_t , IFX_uint32_t *); ++ IFX_FLOW_devType_t eDev; ++ IFX_uint32_t nBaseAddress; ++} IFX_FLOW_RAL_Dev_t; ++ ++typedef struct ++{ ++ IFX_FLOW_devType_t eDev; ++}IFX_FLOW_RAL_Init_t; ++ ++IFX_void_t *IFX_FLOW_RAL_init(IFX_FLOW_RAL_Init_t *pInit); ++ ++ ++#endif /* _IFX_ETHSW_REG_ACCESS.H */ +diff --git a/include/switch_api/ifx_ethsw_rml.h b/include/switch_api/ifx_ethsw_rml.h +new file mode 100644 +index 0000000..109aee6 +--- /dev/null ++++ b/include/switch_api/ifx_ethsw_rml.h +@@ -0,0 +1,49 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ \file ifx_ethsw_rml.h ++ \remarks Register Mapping Layer header file, for Infineon Ethernet switch ++ drivers ++ *****************************************************************************/ ++#ifndef _IFX_ETHSW_RML_H_ ++#define _IFX_ETHSW_RML_H_ ++ ++#include "ifx_ethsw_api.h" ++ ++typedef struct ++{ ++ IFX_return_t (* register_read)(IFX_void_t *, IFX_int32_t, IFX_uint32_t *); ++ IFX_return_t (* register_write)(IFX_void_t *, IFX_int32_t, IFX_uint32_t); ++ IFX_void_t *pRegAccessHandle; ++ IFX_uint32_t nBaseAddress; ++ IFX_ETHSW_regMapper_t *tableHandle; ++} IFX_PSB6970_RML_Dev_t; ++ ++typedef struct ++{ ++ IFX_return_t (* register_read)(IFX_void_t *, IFX_int32_t, IFX_uint32_t *); ++ IFX_return_t (* register_write)(IFX_void_t *, IFX_int32_t, IFX_uint32_t); ++ IFX_void_t *pRegAccessHandle; ++ IFX_uint32_t nBaseAddress; ++ IFX_PSB6970_devType_t eDev; ++}IFX_PSB6970_RML_Init_t; ++ ++ ++IFX_return_t IFX_PSB6970_RML_RegisterGet(IFX_void_t *pDevCtx , IFX_int32_t RegAddr, IFX_uint32_t * value); ++IFX_return_t IFX_PSB6970_RML_RegisterSet(IFX_void_t *pDevCtx , IFX_int32_t RegAddr, IFX_uint32_t value); ++IFX_return_t IFX_PSB6970_RML_Read(IFX_void_t * pDevCtx, ++ IFX_ETHSW_regMapperSelector_t commonbit, ++ IFX_uint32_t portIdx, ++ IFX_uint32_t *pvalue); ++IFX_return_t IFX_PSB6970_RML_Write(IFX_void_t *pDevCtx, ++ IFX_ETHSW_regMapperSelector_t commonbit, ++ IFX_uint32_t portIdx, ++ IFX_uint32_t value); ++IFX_void_t *IFX_PSB6970_RML_init(IFX_PSB6970_RML_Init_t *pInit); ++#endif /* _IFX_ETHSW_RML_H_ */ +diff --git a/include/switch_api/ifx_ethsw_vr9_reg_access.h b/include/switch_api/ifx_ethsw_vr9_reg_access.h +new file mode 100644 +index 0000000..e6fce10 +--- /dev/null ++++ b/include/switch_api/ifx_ethsw_vr9_reg_access.h +@@ -0,0 +1,23 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ \file ifx_ethsw_reg_access.h" ++ \remarks ++ *****************************************************************************/ ++#ifndef _IFX_ETHSW_REG_ACCESS_H ++#define _IFX_ETHSW_REG_ACCESS_H ++ ++#include "ifx_types.h" ++ ++IFX_int32_t ifx_ethsw_ll_DirectAccessRead ++(IFX_void_t *pDevCtx, IFX_int16_t Offset, IFX_int16_t Shift, IFX_int16_t Size, IFX_uint32_t * value); ++IFX_return_t ifx_ethsw_ll_DirectAccessWrite ++(IFX_void_t *pDevCtx, IFX_int16_t Offset, IFX_int16_t Shift, IFX_int16_t Size, IFX_uint32_t value); ++ ++#endif /* _IFX_ETHSW_REG_ACCESS.H */ +diff --git a/include/switch_api/ifx_switch_ll.h b/include/switch_api/ifx_switch_ll.h +new file mode 100644 +index 0000000..47b8aff +--- /dev/null ++++ b/include/switch_api/ifx_switch_ll.h +@@ -0,0 +1,101 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ \file ifx_ethsw_ll.h" ++ \remarks ++ *****************************************************************************/ ++ ++#ifndef _IFX_ETHSW_LL_ACCESS_H_ ++#define _IFX_ETHSW_LL_ACCESS_H_ ++ ++#include "ifx_ethsw.h" ++#include "regmapper.h" ++ ++#define INTERNAL_ACCESS 0 ++#define EXTERNAL_ACCESS 1 ++ ++#define AMAZON_S_SW (KSEG1 | 0x1E108000) ++#define BASE_ADDRESS (KSEG1 | 0x1E108000) ++#define REG32_ACCESS(addr) *((volatile IFX_int32_t *)(addr)) ++#define AMAZON_S_SW_REG(off) ((volatile IFX_int32_t*)(AMAZON_S_SW + (off))) ++ ++ ++#define IFX_DEV_TANTOS_3G_BASEADDR AMAZON_S_SW_REG(0x0cc) ++#define IFX_DEV_AR9_BASEADDR AMAZON_S_SW_REG(0x000) ++ ++ ++typedef enum ++{ ++ IFX_RML_DEV_TANTOS_3G, ++ IFX_RML_DEV_AR9 ++} IFX_RML_Dev_t; ++ ++typedef struct ++{ ++ /** ?? */ ++ IFX_return_t (* register_write)(IFX_void_t *, IFX_int32_t, IFX_uint32_t ); ++ /** ?? */ ++ IFX_int32_t (* register_read)(IFX_ETHSW_regMapper_t *, IFX_int32_t, IFX_uint32_t *); ++ /** ?? */ ++ IFX_void_t * pRegAccessHandle; ++ /** ?? */ ++ IFX_uint32_t nBaseAddress; ++ /** ?? */ ++ IFX_RML_Dev_t eDev; ++ /** Low Level Ethernet Switch driverName */ ++ IFX_char_t *drvName; ++} IFX_ETHSW_RML_Init_t; ++ ++ ++typedef struct ++{ ++ /** ?? */ ++ IFX_return_t (* register_write)(IFX_void_t *, IFX_int32_t, IFX_uint32_t ); ++ /** ?? */ ++ IFX_int32_t (* register_read)(IFX_ETHSW_regMapper_t *, IFX_int32_t, IFX_uint32_t *); ++ /** ?? */ ++ IFX_void_t *pRegAccessHandle; ++ /** ?? */ ++ IFX_uint32_t nBaseAddress; ++ /** ?? */ ++ IFX_RML_Dev_t eDev; ++ /** ?? */ ++ IFX_ETHSW_regMapper_t *tableHandle; ++} RML_Dev_t; ++ ++ ++/* AMAZON_S GPORT SWITCH Register */ ++ ++#define AMAZON_S_BASEADDR (KSEG1 | 0x1E108000) ++#define AMAZON_S_DF_PORTMAP (AMAZON_S_BASEADDR + 0x02C) ++ ++ ++IFX_return_t IFX_ethsw_RML_Read(RML_Dev_t* pCxtHandle, ++ IFX_ETHSW_regMapperSelector_t commonbit, ++ IFX_uint32_t portIdx, ++ IFX_uint32_t *value); ++IFX_return_t IFX_ethsw_RML_Write(RML_Dev_t *pCxtHandle, ++ IFX_ETHSW_regMapperSelector_t commonbit, ++ IFX_uint32_t portIdx, ++ IFX_uint32_t value); ++ ++IFX_return_t IFX_ethsw_RML_Tantos3G_Read(RML_Dev_t* pCxtHandle, ++ IFX_ETHSW_regMapperSelector_t commonbit, ++ IFX_uint32_t portIdx, ++ IFX_uint32_t *value); ++ ++IFX_return_t IFX_ethsw_RML_Tantos3G_Write(RML_Dev_t *pCxtHandle, ++ IFX_ETHSW_regMapperSelector_t commonbit, ++ IFX_uint32_t portIdx, ++ IFX_uint32_t value); ++ ++IFX_return_t IFX_Register_RML_init(IFX_ETHSW_RML_Init_t *pInit); ++ ++#endif ++ +diff --git a/include/switch_api/ifx_types.h b/include/switch_api/ifx_types.h +new file mode 100644 +index 0000000..c28aaae +--- /dev/null ++++ b/include/switch_api/ifx_types.h +@@ -0,0 +1,118 @@ ++#ifndef _IFX_TYPES_H ++#define _IFX_TYPES_H ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ Module : ifx_types.h ++*******************************************************************************/ ++ ++/** \defgroup IFX_BASIC_TYPES Basic IFX Data Types ++ This section describes the basic IFX data type definitions.*/ ++/*@{*/ ++ ++/** This is the character datatype. */ ++typedef char IFX_char_t; ++/** This is the integer datatype. */ ++typedef signed int IFX_int_t; ++/** This is the unsigned integer datatype. */ ++typedef unsigned int IFX_uint_t; ++ ++/** This is the unsigned 8-bit datatype. */ ++typedef unsigned char IFX_uint8_t; ++/** This is the signed 8-bit datatype. */ ++typedef signed char IFX_int8_t; ++/** This is the unsigned 16-bit datatype. */ ++typedef unsigned short IFX_uint16_t; ++/** This is the signed 16-bit datatype. */ ++typedef signed short IFX_int16_t; ++/** This is the unsigned 32-bit datatype. */ ++typedef unsigned int IFX_uint32_t; ++/** This is the signed 32-bit datatype. */ ++typedef signed int IFX_int32_t; ++/** This is the unsigned 64-bit datatype. */ ++typedef unsigned long long int IFX_uint64_t; ++/** This is the signed 64-bit datatype. */ ++typedef signed long long int IFX_int64_t; ++/** This is the float datatype. */ ++typedef float IFX_float_t; ++/** This is the void datatype. */ ++typedef void IFX_void_t; ++ ++/** This is the volatile unsigned 8-bit datatype. */ ++typedef volatile IFX_uint8_t IFX_vuint8_t; ++/** This is the volatile signed 8-bit datatype. */ ++typedef volatile IFX_int8_t IFX_vint8_t; ++/** This is the volatile unsigned 16-bit datatype. */ ++typedef volatile IFX_uint16_t IFX_vuint16_t; ++/** This is the volatile signed 16-bit datatype. */ ++typedef volatile IFX_int16_t IFX_vint16_t; ++/** This is the volatile unsigned 32-bit datatype. */ ++typedef volatile IFX_uint32_t IFX_vuint32_t; ++/** This is the volatile signed 32-bit datatype. */ ++typedef volatile IFX_int32_t IFX_vint32_t; ++/** This is the volatile unsigned 64-bit datatype. */ ++typedef volatile IFX_uint64_t IFX_vuint64_t; ++/** This is the volatile signed 64-bit datatype. */ ++typedef volatile IFX_int64_t IFX_vint64_t; ++/** This is the volatile float datatype. */ ++typedef volatile IFX_float_t IFX_vfloat_t; ++ ++ ++/** A type for handling boolean issues. */ ++typedef enum { ++ /** False. */ ++ IFX_FALSE = 0, ++ /** True. */ ++ IFX_TRUE = 1 ++} IFX_boolean_t; ++ ++ ++/** This type is used for parameters that should enable and disable a ++dedicated feature. */ ++typedef enum { ++ /** Disable. */ ++ IFX_DISABLE = 0, ++ /** Enable. */ ++ IFX_ENABLE = 1 ++} IFX_enDis_t; ++ ++/** This type is used for parameters that should enable and disable a dedicated ++ feature. */ ++typedef IFX_enDis_t IFX_operation_t; ++ ++/** This type has two states, even and odd.*/ ++typedef enum { ++ /** Even. */ ++ IFX_EVEN = 0, ++ /** Odd. */ ++ IFX_ODD = 1 ++} IFX_evenOdd_t; ++ ++ ++/** This type has two states, high and low. */ ++typedef enum { ++ /** Low. */ ++ IFX_LOW = 0, ++ /** High. */ ++ IFX_HIGH = 1 ++} IFX_highLow_t; ++ ++/** This type has two states, success and error. */ ++typedef enum { ++ /** Operation failed. */ ++ IFX_ERROR = (-1), ++ /** Operation succeeded. */ ++ IFX_SUCCESS = 0 ++} IFX_return_t; ++ ++#define IFX_NULL ((void *)0) ++/*@}*/ /* IFX_BASIC_TYPES */ ++ ++#endif /* _IFX_TYPES_H */ ++ +diff --git a/include/switch_api/ifxmips_gphy_sw.h b/include/switch_api/ifxmips_gphy_sw.h +new file mode 100644 +index 0000000..617b706 +--- /dev/null ++++ b/include/switch_api/ifxmips_gphy_sw.h +@@ -0,0 +1,124 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ ++ \file ifxmips_gphy_sw.h ++ \remarks implement GPHY driver on VR9 platform ++ *****************************************************************************/ ++ ++#ifndef _IFXMIPS_GPHY_SW_H_ ++#define _IFXMIPS_GPHY_SW_H_ ++ ++#include ++#include ++#include ++ ++/** default board related configuration */ ++#if defined(CONFIG_MII0_PORT_ENABLED) ++#define CONFIG_MAC0 1 ++#else ++#define CONFIG_MAC0 0 ++#endif ++ ++#if defined(CONFIG_MII1_PORT_ENABLED) ++#define CONFIG_MAC1 1 ++#else ++#define CONFIG_MAC1 0 ++#endif ++ ++#if defined(CONFIG_MII2_PORT_ENABLED) ++#define CONFIG_MAC2 1 ++#else ++#define CONFIG_MAC2 0 ++#endif ++ ++#if defined(CONFIG_MII3_PORT_ENABLED) ++#define CONFIG_MAC3 1 ++#else ++#define CONFIG_MAC3 0 ++#endif ++ ++#if defined(CONFIG_MII4_PORT_ENABLED) ++#define CONFIG_MAC4 1 ++#else ++#define CONFIG_MAC4 0 ++#endif ++ ++#if defined(CONFIG_MII5_PORT_ENABLED) ++#define CONFIG_MAC5 1 ++#else ++#define CONFIG_MAC5 0 ++#endif ++ ++#if defined(CONFIG_MII0_RGMII_MAC_MODE) ++#define MII0_MODE_SETUP RGMII_MODE ++#elif defined(CONFIG_MII0_RMII_MAC_MODE) ++#define MII0_MODE_SETUP RMII_MAC_MODE ++#elif defined(CONFIG_MII0_RMII_PHY_MODE) ++#define MII0_MODE_SETUP RMII_PHY_MODE ++#elif defined(CONFIG_MII0_MII_MAC_MODE) ++#define MII0_MODE_SETUP MII_MAC_MODE ++#elif defined(CONFIG_MII0_MII_PHY_MODE) ++#define MII0_MODE_SETUP MII_PHY_MODE ++#endif ++ ++#if defined(CONFIG_MII1_RGMII_MAC_MODE) ++#define MII1_MODE_SETUP RGMII_MODE ++#elif defined(CONFIG_MII1_RMII_MAC_MODE) ++#define MII1_MODE_SETUP RMII_MAC_MODE ++#elif defined(CONFIG_MII1_RMII_PHY_MODE) ++#define MII1_MODE_SETUP RMII_PHY_MODE ++#elif defined(CONFIG_MII1_MII_MAC_MODE) ++#define MII1_MODE_SETUP MII_MAC_MODE ++#elif defined(CONFIG_MII1_MII_PHY_MODE) ++#define MII1_MODE_SETUP MII_PHY_MODE ++#endif ++ ++#if defined(CONFIG_MII2_GMII_MODE) ++#define MII2_MODE_SETUP GMII_MAC_MODE ++#elif defined(CONFIG_MII2_MII_MAC_MODE) ++#define MII2_MODE_SETUP MII_MAC_MODE ++#endif ++ ++#if defined(CONFIG_MII3_MII_MAC_MODE) ++#define MII3_MODE_SETUP MII_MAC_MODE ++#endif ++ ++#if defined(CONFIG_MII4_GMII_MODE) ++#define MII4_MODE_SETUP GMII_MAC_MODE ++#elif defined(CONFIG_MII4_MII_MAC_MODE) ++#define MII4_MODE_SETUP MII_MAC_MODE ++#endif ++ ++#if defined(CONFIG_MII5_RGMII_MODE) ++#define MII5_MODE_SETUP RGMII_MODE ++#elif defined(CONFIG_MII5_MII_MAC_MODE) ++#define MII5_MODE_SETUP MII_PHY_MODE ++#endif ++ ++ ++#ifdef CONFIG_SW_ROUTING_MODE ++ #define CONFIG_PMAC_DMA_ENABLE 1 /*g_pmac_dma */ ++ #define CONFIG_DMA_PMAC_ENABLE 1 /*g_dma_pmac*/ ++#else ++ #define CONFIG_PMAC_DMA_ENABLE 0 /*g_pmac_dma */ ++ #define CONFIG_DMA_PMAC_ENABLE 0 /*g_dma_pmac*/ ++#endif ++ ++#if defined(CONFIG_PMAC_DMA_ENABLE) && CONFIG_PMAC_DMA_ENABLE ++ #define NUM_ETH_INF 2 ++#else ++ #define NUM_ETH_INF 1 ++#endif ++ ++ ++#define GPHY_FW_LEN 65536 ++static const char gphy_fw_data[GPHY_FW_LEN]; ++ ++#endif /*_IFXMIPS_GPHY_SW_H_ */ +diff --git a/include/switch_api/ifxmips_sw_reg.h b/include/switch_api/ifxmips_sw_reg.h +new file mode 100644 +index 0000000..b988218 +--- /dev/null ++++ b/include/switch_api/ifxmips_sw_reg.h +@@ -0,0 +1,300 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ \file ifxmips_sw_reg.h ++ \remarks implement GPHY driver on VR9 platform ++ *****************************************************************************/ ++#ifndef _IFXMIPS_SW_REG_H ++#define _IFXMIPS_SW_REG_H ++ ++/** ========================== */ ++/* Include files */ ++/** =========================== */ ++#include ++ ++/* ============================= */ ++/* Local Macros & Definitions */ ++/* ============================= */ ++ ++#define SW_WRITE_REG32(data,addr) IFX_REG_W32((data), (volatile unsigned int *)addr) ++#define SW_READ_REG32(addr) IFX_REG_R32((volatile unsigned int *)addr) ++ ++/** Registers Description */ ++ ++#define VR9_GPIO_BASE_ADDR (0xBE100B00) ++ ++/* Port 0 Direction Register */ ++#define P0_DIR (VR9_GPIO_BASE_ADDR + 0x18) ++/* Port 0 Alternate Function Select Register 0 */ ++#define P0_ALTSEL0 (VR9_GPIO_BASE_ADDR + 0x1C) ++/* Port 0 Alternate Function Select Register 1 */ ++#define P0_ALTSEL1 (VR9_GPIO_BASE_ADDR + 0x20) ++ ++ ++#define VR9_CGU_BASE_ADDR (0xBF103000) ++ ++/* Interface Clock Register */ ++#define IF_CLK (VR9_CGU_BASE_ADDR + 0x24) ++ ++ ++#define VR9_RCU_BASE_ADDR (0xBF203000) ++ ++/* Reset Request Register */ ++#define RST_REQ (VR9_RCU_BASE_ADDR + 0x10) ++/* GPHY0 Firmware Base Address Register */ ++#define GFS_ADD0 (VR9_RCU_BASE_ADDR + 0x20) ++/* GPHY1 Firmware Base Address Register */ ++#define GFS_ADD1 (VR9_RCU_BASE_ADDR + 0x68) ++ ++ ++#define VR9_PMU_BASE_ADDR (0xBF102000) ++ ++/* PMU Power down Control Register */ ++#define PMU_PWDCR (VR9_PMU_BASE_ADDR + 0x1C) ++ ++ ++#define VR9_SWIP_BASE_ADDR (0xBE108000) ++#define VR9_SWIP_TOP_BASE_ADDR (VR9_SWIP_BASE_ADDR + (0x0C40 * 4)) ++/** Switch Reset Control register */ ++#define ETHSW_SWRES_REG (VR9_SWIP_BASE_ADDR) ++/** Register Configuration Resets all registers to their default state (such as after a hardware reset). ++* 0B RUN reset is off, 1B STOP reset is active */ ++#define SWRES_R0 0x0001 ++/** Hardware Reset Reset all hardware modules except for the register settings. ++* 0B RUN reset is off, 1B STOP reset is active */ ++#define SWRES_R1 0x0002 ++ ++/** Ethernet Switch Clock Control Register */ ++#define ETHSW_CLK_REG (VR9_SWIP_BASE_ADDR + (1 * 4)) ++ ++/** MAC Frame Length Register */ ++#define MAC_FLEN_REG (VR9_SWIP_BASE_ADDR + (0x8C5 * 4) ) ++#define MAC_FLEN(arg) ( (arg & 0x3FFF)) ++ ++/** MAC Port Status Register */ ++#define MAC_0_PSTAT_REG (VR9_SWIP_BASE_ADDR + (0x900 * 4) ) ++#define MAC_1_PSTAT_REG (VR9_SWIP_BASE_ADDR + (0x90C * 4) ) ++#define MAC_2_PSTAT_REG (VR9_SWIP_BASE_ADDR + (0x918 * 4) ) ++#define MAC_3_PSTAT_REG (VR9_SWIP_BASE_ADDR + (0x924 * 4) ) ++#define MAC_4_PSTAT_REG (VR9_SWIP_BASE_ADDR + (0x930 * 4) ) ++#define MAC_5_PSTAT_REG (VR9_SWIP_BASE_ADDR + (0x93C * 4) ) ++#define MAC_6_PSTAT_REG (VR9_SWIP_BASE_ADDR + (0x948 * 4) ) ++ ++/** MAC Control Register 0 */ ++#define MAC_0_CTRL_0 (VR9_SWIP_BASE_ADDR + (0x903 * 4) ) ++#define MAC_1_CTRL_0 (VR9_SWIP_BASE_ADDR + (0x90F * 4) ) ++#define MAC_2_CTRL_0 (VR9_SWIP_BASE_ADDR + (0x91B * 4) ) ++#define MAC_3_CTRL_0 (VR9_SWIP_BASE_ADDR + (0x927 * 4) ) ++#define MAC_4_CTRL_0 (VR9_SWIP_BASE_ADDR + (0x933 * 4) ) ++#define MAC_5_CTRL_0 (VR9_SWIP_BASE_ADDR + (0x93F * 4) ) ++#define MAC_6_CTRL_0 (VR9_SWIP_BASE_ADDR + (0x94B * 4) ) ++ ++#define MAC_CTRL_0_FCON_MASK 0x0070 ++#define MAC_CTRL_0_FCON_AUTO 0x0000 ++#define MAC_CTRL_0_FCON_RX 0x0010 ++#define MAC_CTRL_0_FCON_TX 0x0020 ++#define MAC_CTRL_0_FCON_RXTX 0x0030 ++#define MAC_CTRL_0_FCON_NONE 0x0040 ++ ++#define MAC_CTRL_0_FDUP_MASK 0x000C ++#define MAC_CTRL_0_FDUP_AUTO 0x0000 ++#define MAC_CTRL_0_FDUP_EN 0x0004 ++#define MAC_CTRL_0_FDUP_DIS 0x000C ++ ++#define MAC_CTRL_0_GMII_MASK 0x0003 ++#define MAC_CTRL_0_GMII_AUTO 0x0000 ++#define MAC_CTRL_0_GMII_MII 0x0001 ++#define MAC_CTRL_0_GMII_RGMII 0x0002 ++ ++/** Ethernet Switch Fetch DMA Port Control ++ Controls per-port functions of the Fetch DMA */ ++#define FDMA_PCTRL_PORT6 (VR9_SWIP_BASE_ADDR + (0xAA4 * 4) ) ++/** Special Tag Insertion Enable(to egress frames )*/ ++#define FDMA_PCTRL_STEN (1 << 1) ++ ++/** VR9 Switch Subsystem Top Level Registers */ ++ ++/** Global Control Register 0 */ ++#define GLOB_CTRL_REG (VR9_SWIP_TOP_BASE_ADDR) ++/** Global Software Reset Reset all hardware modules excluding the register settings. ++* 0B OFF reset is off, 1B ON reset is active */ ++#define GLOB_CTRL_SWRES 0x0001 ++/** Global Hardware Reset Reset all hardware modules including the register settings. ++* 0B OFF reset is off, 1B ON reset is active */ ++#define GLOB_CTRL_HWRES 0x0002 ++/** Global Switch Macro Enable If set to OFF, the switch macro is inactive and frame forwarding is disabled. ++* 0B OFF switch macro is not active, 1B ON switch macro is active */ ++#define GLOB_CTRL_SE 0x8000 ++ ++/** MDIO Control Register */ ++#define MDIO_CTRL_REG (VR9_SWIP_TOP_BASE_ADDR + (8 * 4)) ++/** MDIO Busy*/ ++#define MDIO_CTRL_MBUSY 0x1000 ++#define MDIO_CTRL_OP_MASK 0x0C00 ++#define MDIO_CTRL_OP_WR 0x0400 ++#define MDIO_CTRL_OP_RD 0x0800 ++#define MDIO_CTRL_PHYAD_SET(arg) ((arg & 0x1F) << 5) ++#define MDIO_CTRL_PHYAD_GET(arg) ( (arg >> 5 ) & 0x1F) ++#define MDIO_CTRL_REGAD(arg) ( arg & 0x1F) ++ ++/** MDIO Read Data Register */ ++#define MDIO_READ_REG (VR9_SWIP_TOP_BASE_ADDR + (9 * 4)) ++#define MDIO_READ_RDATA(arg) (arg & 0xFFFF) ++ ++/** MDIO Write Data Register */ ++#define MDIO_WRITE_REG (VR9_SWIP_TOP_BASE_ADDR + (0x0A * 4)) ++#define MDIO_READ_WDATA(arg) (arg & 0xFFFF) ++ ++/** MDC Clock Configuration Register 0 */ ++#define MDC_CFG_0_REG (VR9_SWIP_TOP_BASE_ADDR + (0x0B * 4)) ++#define MDC_CFG_0_PEN_SET(port) (0x1 << port ) ++#define MDC_CFG_0_PEN_GET(port, reg_data) ((reg_data >> port ) & 0x1 ) ++/** MDC Clock Configuration Register 1 */ ++#define MDC_CFG_1_REG (VR9_SWIP_TOP_BASE_ADDR + (0x0C * 4)) ++ ++/** PHY Address Register PORT 5~0 */ ++#define PHY_ADDR_5 (VR9_SWIP_TOP_BASE_ADDR + (0x10 * 4)) ++#define PHY_ADDR_4 (VR9_SWIP_TOP_BASE_ADDR + (0x11 * 4)) ++#define PHY_ADDR_3 (VR9_SWIP_TOP_BASE_ADDR + (0x12 * 4)) ++#define PHY_ADDR_2 (VR9_SWIP_TOP_BASE_ADDR + (0x13 * 4)) ++#define PHY_ADDR_1 (VR9_SWIP_TOP_BASE_ADDR + (0x14 * 4)) ++#define PHY_ADDR_0 (VR9_SWIP_TOP_BASE_ADDR + (0x15 * 4)) ++/** Link Status Control */ ++#define PHY_ADDR_LINKST_MASK 0x6000 ++#define PHY_ADDR_LINKST_AUTO 0x0000 ++#define PHY_ADDR_LINKST_UP 0x2000 ++#define PHY_ADDR_LINKST_DOWN 0x4000 ++/** Speed Control */ ++#define PHY_ADDR_SPEED_MASK 0x1800 ++#define PHY_ADDR_SPEED_10 0x0000 ++#define PHY_ADDR_SPEED_100 0x0800 ++#define PHY_ADDR_SPEED_1000 0x1000 ++#define PHY_ADDR_SPEED_AUTO 0x1800 ++/** Full Duplex Control */ ++#define PHY_ADDR_FDUP_MASK 0x0600 ++#define PHY_ADDR_FDUP_AUTO 0x0000 ++#define PHY_ADDR_FDUP_EN 0x0200 ++#define PHY_ADDR_FDUP_DIS 0x0600 ++/** Flow Control Mode TX */ ++#define PHY_ADDR_FCONTX_MASK 0x0180 ++#define PHY_ADDR_FCONTX_AUTO 0x0000 ++#define PHY_ADDR_FCONTX_EN 0x0080 ++#define PHY_ADDR_FCONTX_DIS 0x0180 ++/** Flow Control Mode RX */ ++#define PHY_ADDR_FCONRX_MASK 0x0060 ++#define PHY_ADDR_FCONRX_AUTO 0x0000 ++#define PHY_ADDR_FCONRX_EN 0x0020 ++#define PHY_ADDR_FCONRX_DIS 0x0060 ++/** PHY Address */ ++#define PHY_ADDR_ADDR(arg) (arg & 0x1F) ++ ++/** PHY MDIO Polling Status per PORT */ ++#define MDIO_STAT_0_REG (VR9_SWIP_TOP_BASE_ADDR + (0x16 * 4)) ++#define MDIO_STAT_1_REG (VR9_SWIP_TOP_BASE_ADDR + (0x17 * 4)) ++#define MDIO_STAT_2_REG (VR9_SWIP_TOP_BASE_ADDR + (0x18 * 4)) ++#define MDIO_STAT_3_REG (VR9_SWIP_TOP_BASE_ADDR + (0x19 * 4)) ++#define MDIO_STAT_4_REG (VR9_SWIP_TOP_BASE_ADDR + (0x1A * 4)) ++#define MDIO_STAT_5_REG (VR9_SWIP_TOP_BASE_ADDR + (0x1B * 4)) ++/** PHY Active Status */ ++#define MDIO_STAT_PACT 0x0040 ++#define MDIO_STAT_LSTAT 0x0020 ++#define MDIO_STAT_SPEED(arg) ( (arg >> 0x3) & 0x03) ++#define MDIO_STAT_FDUP 0x0004 ++#define MDIO_STAT_RXPAUEN 0x0002 ++#define MDIO_STAT_TXPAUEN 0x0001 ++ ++/** xMII Control Registers */ ++/** xMII Port 0 Configuration register */ ++#define MII_CFG_0_REG (VR9_SWIP_TOP_BASE_ADDR + (0x36 * 4)) ++#define MII_CFG_1_REG (VR9_SWIP_TOP_BASE_ADDR + (0x38 * 4)) ++#define MII_CFG_2_REG (VR9_SWIP_TOP_BASE_ADDR + (0x3A * 4)) ++#define MII_CFG_3_REG (VR9_SWIP_TOP_BASE_ADDR + (0x3C * 4)) ++#define MII_CFG_4_REG (VR9_SWIP_TOP_BASE_ADDR + (0x3E * 4)) ++#define MII_CFG_5_REG (VR9_SWIP_TOP_BASE_ADDR + (0x40 * 4)) ++#define MII_CFG_RES 0x8000 ++#define MII_CFG_EN 0x4000 ++/** Bits are only valid in PHY Mode */ ++#define MII_CFG_CRS_SET(arg) ( (arg & 0x03) << 0x9) ++#define MII_CFG_CRS_GET(arg) ( (arg >> 0x9) & 0x03) ++/** RGMII In Band Status */ ++#define MII_CFG_RGMII_IBS 0x0100 ++/** RMII Reference Clock Direction of the Port */ ++#define MII_CFG_RMII_OUT 0x0080 ++/** xMII Port Interface Clock Rate */ ++#define MII_CFG_MIIRATE_MASK 0x0070 ++#define MII_CFG_MIIRATE_2_5MHZ 0x0000 ++#define MII_CFG_MIIRATE_25MHZ 0x0010 ++#define MII_CFG_MIIRATE_125MHZ 0x0020 ++#define MII_CFG_MIIRATE_50MHZ 0x0030 ++#define MII_CFG_MIIRATE_AUTO 0x0040 ++/** xMII Interface Mode */ ++#define MII_CFG_MIIMODE_MASK 0x000F ++#define MII_CFG_MIIMODE_MIIP 0x0000 ++#define MII_CFG_MIIMODE_MIIM 0x0001 ++#define MII_CFG_MIIMODE_RMIIP 0x0002 ++#define MII_CFG_MIIMODE_RMIIM 0x0003 ++#define MII_CFG_MIIMODE_RGMII 0x0004 ++ ++/** Configuration of Clock Delay for Port 0 (used for RGMII mode only)*/ ++#define MII_PCDU_0_REG (VR9_SWIP_TOP_BASE_ADDR + (0x37 * 4)) ++#define MII_PCDU_1_REG (VR9_SWIP_TOP_BASE_ADDR + (0x39 * 4)) ++#define MII_PCDU_5_REG (VR9_SWIP_TOP_BASE_ADDR + (0x41 * 4)) ++#define MII_PCDU_RXLOCK 0x8000 ++#define MII_PCDU_TXLOCK 0x4000 ++#define MII_PCDU_RXSEL_CLK_MASK 0x3000 ++#define MII_PCDU_RXSEL_CLK_AUTO 0x0000 ++#define MII_PCDU_RXSEL_CLK_RXCLK 0x1000 ++#define MII_PCDU_RXSEL_CLK_CLKREF 0x2000 ++#define MII_PCDU_RXINIT 0x0800 ++#define MII_PCDU_RXPD 0x0400 ++#define MII_PCDU_RXDLY_MASK 0x0380 ++ ++#define MII_PCDU_TXSEL_CLK_MASK 0x0060 ++#define MII_PCDU_TXSEL_CLK_AUTO 0x0000 ++#define MII_PCDU_TXSEL_CLK_TXCLK 0x0020 ++#define MII_PCDU_TXSEL_CLK_CLKREF 0x0040 ++#define MII_PCDU_TXINIT 0x0010 ++#define MII_PCDU_TXPD 0x0008 ++#define MII_PCDU_TXDLY_MASK 0x0007 ++ ++/** PMAC Header Control Register */ ++#define PMAC_HD_CTL_REG (VR9_SWIP_TOP_BASE_ADDR + (0x82 * 4)) ++#define PMAC_HD_CTL_FC 0x0400 ++#define PMAC_HD_CTL_CCRC 0x0200 ++#define PMAC_HD_CTL_RST 0x0100 ++#define PMAC_HD_CTL_AST 0x0080 ++#define PMAC_HD_CTL_RXSH 0x0040 ++#define PMAC_HD_CTL_RL2 0x0020 ++#define PMAC_HD_CTL_RC 0x0010 ++#define PMAC_HD_CTL_AS 0x0008 ++#define PMAC_HD_CTL_AC 0x0004 ++#define PMAC_HD_CTL_TAG 0x0002 ++#define PMAC_HD_CTL_ADD 0x0001 ++ ++/** PMAC Type/Length register */ ++#define PMAC_TL_REG (VR9_SWIP_TOP_BASE_ADDR + (0x83 * 4)) ++/** PMAC Source Address Register */ ++#define PMAC_SA1_REG (VR9_SWIP_TOP_BASE_ADDR + (0x84 * 4)) ++#define PMAC_SA2_REG (VR9_SWIP_TOP_BASE_ADDR + (0x85 * 4)) ++#define PMAC_SA3_REG (VR9_SWIP_TOP_BASE_ADDR + (0x86 * 4)) ++/** PMAC Destination Address Register */ ++#define PMAC_DA1_REG (VR9_SWIP_TOP_BASE_ADDR + (0x87 * 4)) ++#define PMAC_DA2_REG (VR9_SWIP_TOP_BASE_ADDR + (0x88 * 4)) ++#define PMAC_DA3_REG (VR9_SWIP_TOP_BASE_ADDR + (0x89 * 4)) ++/** PMAC VLAN register */ ++#define PMAC_VLAN_REG (VR9_SWIP_TOP_BASE_ADDR + (0x8A * 4)) ++/** PMAC Inter Packet Gap in RX Direction */ ++#define PMAC_RX_IPG_REG (VR9_SWIP_TOP_BASE_ADDR + (0x8B * 4)) ++/** PMAC Special Tag Ethertype */ ++#define PMAC_ST_ETYPE_REG (VR9_SWIP_TOP_BASE_ADDR + (0x8C * 4)) ++/** PMAC Ethernet WAN Group */ ++#define PMAC_EWAN_REG (VR9_SWIP_TOP_BASE_ADDR + (0x8D * 4)) ++ ++#endif /*_IFXMIPS_SW_REG_H */ +diff --git a/include/switch_api/regmapper.h b/include/switch_api/regmapper.h +new file mode 100644 +index 0000000..879e6dc +--- /dev/null ++++ b/include/switch_api/regmapper.h +@@ -0,0 +1,27 @@ ++/**************************************************************************** ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 85579 Neubiberg, Germany ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++ ***************************************************************************** ++ \file regmapper.h ++ \remarks switch API header file, for Infineon Ethernet switch drivers ++ *****************************************************************************/ ++ ++#ifndef _REGMAPPER_H ++#define _REGMAPPER_H ++ ++#include "ifx_types.h" ++#include "commonReg.h" ++ ++typedef struct ++{ ++ IFX_uint16_t nCommonBitEnum; ++ IFX_uint16_t nRegOffset; ++ IFX_uint8_t nBitPosition; ++ IFX_uint8_t nBitSize; ++}IFX_ETHSW_regMapper_t; ++#endif /* #ifndef _REGMAPPER_H */ +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0015-NET-MIPS-lantiq-make-etop-ethernet-work-on-ase-ar9.patch b/target/linux/lantiq/patches-3.3/0015-NET-MIPS-lantiq-make-etop-ethernet-work-on-ase-ar9.patch deleted file mode 100644 index 1a4f894346..0000000000 --- a/target/linux/lantiq/patches-3.3/0015-NET-MIPS-lantiq-make-etop-ethernet-work-on-ase-ar9.patch +++ /dev/null @@ -1,396 +0,0 @@ -From 204df03dd8524ab3ee8261feab44397dc890a840 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Wed, 10 Aug 2011 15:32:16 +0200 -Subject: [PATCH 15/70] NET: MIPS: lantiq: make etop ethernet work on ase/ar9 - -Extend the driver to handle the different DMA channel layout for AR9 and -Amazon-SE SoCs. The patch also adds support for the integrated PHY found -on Amazon-SE and the gigabit switch found inside the AR9. - -Signed-off-by: John Crispin -Cc: netdev@vger.kernel.org ---- - .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 22 +--- - .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 10 ++ - arch/mips/lantiq/xway/devices.c | 11 +- - drivers/net/ethernet/lantiq_etop.c | 171 ++++++++++++++++++-- - 4 files changed, 174 insertions(+), 40 deletions(-) - ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h -@@ -38,26 +38,8 @@ - - #define MIPS_CPU_TIMER_IRQ 7 - --#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0) --#define LTQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1) --#define LTQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2) --#define LTQ_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3) --#define LTQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4) --#define LTQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5) --#define LTQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6) --#define LTQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7) --#define LTQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8) --#define LTQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9) --#define LTQ_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10) --#define LTQ_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11) --#define LTQ_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25) --#define LTQ_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26) --#define LTQ_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27) --#define LTQ_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28) --#define LTQ_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29) --#define LTQ_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30) --#define LTQ_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16) --#define LTQ_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21) -+#define LTQ_DMA_ETOP ((ltq_is_ase()) ? \ -+ (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0)) - - #define LTQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24) - ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -@@ -82,6 +82,7 @@ - #define LTQ_PMU_SIZE 0x1000 - - #define PMU_DMA 0x0020 -+#define PMU_EPHY 0x0080 - #define PMU_USB 0x8041 - #define PMU_LED 0x0800 - #define PMU_GPT 0x1000 -@@ -93,6 +94,10 @@ - #define LTQ_ETOP_BASE_ADDR 0x1E180000 - #define LTQ_ETOP_SIZE 0x40000 - -+/* GBIT - gigabit switch */ -+#define LTQ_GBIT_BASE_ADDR 0x1E108000 -+#define LTQ_GBIT_SIZE 0x200 -+ - /* DMA */ - #define LTQ_DMA_BASE_ADDR 0x1E104100 - #define LTQ_DMA_SIZE 0x800 -@@ -147,6 +152,11 @@ extern void ltq_pmu_enable(unsigned int - extern void ltq_pmu_disable(unsigned int module); - extern void ltq_cgu_enable(unsigned int clk); - -+static inline int ltq_is_ase(void) -+{ -+ return (ltq_get_soc_type() == SOC_TYPE_AMAZON_SE); -+} -+ - static inline int ltq_is_ar9(void) - { - return (ltq_get_soc_type() == SOC_TYPE_AR9); ---- a/arch/mips/lantiq/xway/devices.c -+++ b/arch/mips/lantiq/xway/devices.c -@@ -74,18 +74,23 @@ void __init ltq_register_ase_asc(void) - } - - /* ethernet */ --static struct resource ltq_etop_resources = -- MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE); -+static struct resource ltq_etop_resources[] = { -+ MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE), -+ MEM_RES("gbit", LTQ_GBIT_BASE_ADDR, LTQ_GBIT_SIZE), -+}; - - static struct platform_device ltq_etop = { - .name = "ltq_etop", -- .resource = <q_etop_resources, -+ .resource = ltq_etop_resources, - .num_resources = 1, - }; - - void __init - ltq_register_etop(struct ltq_eth_data *eth) - { -+ /* only register the gphy on socs that have one */ -+ if (ltq_is_ar9() | ltq_is_vr9()) -+ ltq_etop.num_resources = 2; - if (eth) { - ltq_etop.dev.platform_data = eth; - platform_device_register(<q_etop); ---- a/drivers/net/ethernet/lantiq_etop.c -+++ b/drivers/net/ethernet/lantiq_etop.c -@@ -71,10 +71,43 @@ - #define ETOP_MII_REVERSE 0xe - #define ETOP_PLEN_UNDER 0x40 - #define ETOP_CGEN 0x800 -+#define ETOP_CFG_MII0 0x01 - --/* use 2 static channels for TX/RX */ -+#define LTQ_GBIT_MDIO_CTL 0xCC -+#define LTQ_GBIT_MDIO_DATA 0xd0 -+#define LTQ_GBIT_GCTL0 0x68 -+#define LTQ_GBIT_PMAC_HD_CTL 0x8c -+#define LTQ_GBIT_P0_CTL 0x4 -+#define LTQ_GBIT_PMAC_RX_IPG 0xa8 -+ -+#define PMAC_HD_CTL_AS (1 << 19) -+#define PMAC_HD_CTL_RXSH (1 << 22) -+ -+/* Switch Enable (0=disable, 1=enable) */ -+#define GCTL0_SE 0x80000000 -+/* Disable MDIO auto polling (0=disable, 1=enable) */ -+#define PX_CTL_DMDIO 0x00400000 -+ -+/* register information for the gbit's MDIO bus */ -+#define MDIO_XR9_REQUEST 0x00008000 -+#define MDIO_XR9_READ 0x00000800 -+#define MDIO_XR9_WRITE 0x00000400 -+#define MDIO_XR9_REG_MASK 0x1f -+#define MDIO_XR9_ADDR_MASK 0x1f -+#define MDIO_XR9_RD_MASK 0xffff -+#define MDIO_XR9_REG_OFFSET 0 -+#define MDIO_XR9_ADDR_OFFSET 5 -+#define MDIO_XR9_WR_OFFSET 16 -+ -+/* the newer xway socks have a embedded 3/7 port gbit multiplexer */ -+#define ltq_has_gbit() (ltq_is_ar9() || ltq_is_vr9()) -+ -+/* use 2 static channels for TX/RX -+ depending on the SoC we need to use different DMA channels for ethernet */ - #define LTQ_ETOP_TX_CHANNEL 1 --#define LTQ_ETOP_RX_CHANNEL 6 -+#define LTQ_ETOP_RX_CHANNEL ((ltq_is_ase()) ? (5) : \ -+ ((ltq_has_gbit()) ? (0) : (6))) -+ - #define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) - #define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) - -@@ -83,9 +116,15 @@ - #define ltq_etop_w32_mask(x, y, z) \ - ltq_w32_mask(x, y, ltq_etop_membase + (z)) - -+#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x)) -+#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y)) -+#define ltq_gbit_w32_mask(x, y, z) \ -+ ltq_w32_mask(x, y, ltq_gbit_membase + (z)) -+ - #define DRV_VERSION "1.0" - - static void __iomem *ltq_etop_membase; -+static void __iomem *ltq_gbit_membase; - - struct ltq_etop_chan { - int idx; -@@ -111,6 +150,9 @@ struct ltq_etop_priv { - spinlock_t lock; - }; - -+static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, -+ int phy_reg, u16 phy_data); -+ - static int - ltq_etop_alloc_skb(struct ltq_etop_chan *ch) - { -@@ -212,7 +254,7 @@ static irqreturn_t - ltq_etop_dma_irq(int irq, void *_priv) - { - struct ltq_etop_priv *priv = _priv; -- int ch = irq - LTQ_DMA_CH0_INT; -+ int ch = irq - LTQ_DMA_ETOP; - - napi_schedule(&priv->ch[ch].napi); - return IRQ_HANDLED; -@@ -245,15 +287,43 @@ ltq_etop_hw_exit(struct net_device *dev) - ltq_etop_free_channel(dev, &priv->ch[i]); - } - -+static void -+ltq_etop_gbit_init(void) -+{ -+ ltq_pmu_enable(PMU_SWITCH); -+ -+ ltq_gpio_request(42, 2, 1, "MDIO"); -+ ltq_gpio_request(43, 2, 1, "MDC"); -+ -+ ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); -+ /** Disable MDIO auto polling mode */ -+ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL); -+ /* set 1522 packet size */ -+ ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0); -+ /* disable pmac & dmac headers */ -+ ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0, -+ LTQ_GBIT_PMAC_HD_CTL); -+ /* Due to traffic halt when burst length 8, -+ replace default IPG value with 0x3B */ -+ ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG); -+} -+ - static int - ltq_etop_hw_init(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -+ unsigned int mii_mode = priv->pldata->mii_mode; - int i; - - ltq_pmu_enable(PMU_PPE); - -- switch (priv->pldata->mii_mode) { -+ if (ltq_has_gbit()) { -+ ltq_etop_gbit_init(); -+ /* force the etops link to the gbit to MII */ -+ mii_mode = PHY_INTERFACE_MODE_MII; -+ } -+ -+ switch (mii_mode) { - case PHY_INTERFACE_MODE_RMII: - ltq_etop_w32_mask(ETOP_MII_MASK, - ETOP_MII_REVERSE, LTQ_ETOP_CFG); -@@ -265,6 +335,18 @@ ltq_etop_hw_init(struct net_device *dev) - break; - - default: -+ if (ltq_is_ase()) { -+ ltq_pmu_enable(PMU_EPHY); -+ /* disable external MII */ -+ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG); -+ /* enable clock for internal PHY */ -+ ltq_cgu_enable(CGU_EPHY); -+ /* we need to write this magic to the internal phy to -+ make it work */ -+ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020); -+ pr_info("Selected EPHY mode\n"); -+ break; -+ } - netdev_err(dev, "unknown mii mode %d\n", - priv->pldata->mii_mode); - return -ENOTSUPP; -@@ -276,7 +358,7 @@ ltq_etop_hw_init(struct net_device *dev) - ltq_dma_init_port(DMA_PORT_ETOP); - - for (i = 0; i < MAX_DMA_CHAN; i++) { -- int irq = LTQ_DMA_CH0_INT + i; -+ int irq = LTQ_DMA_ETOP + i; - struct ltq_etop_chan *ch = &priv->ch[i]; - - ch->idx = ch->dma.nr = i; -@@ -340,6 +422,39 @@ static const struct ethtool_ops ltq_etop - }; - - static int -+ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr, -+ int phy_reg, u16 phy_data) -+{ -+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE | -+ (phy_data << MDIO_XR9_WR_OFFSET) | -+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | -+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); -+ -+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) -+ ; -+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); -+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) -+ ; -+ return 0; -+} -+ -+static int -+ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg) -+{ -+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ | -+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | -+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); -+ -+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) -+ ; -+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); -+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) -+ ; -+ val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK; -+ return val; -+} -+ -+static int - ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) - { - u32 val = MDIO_REQUEST | -@@ -380,14 +495,11 @@ ltq_etop_mdio_probe(struct net_device *d - { - struct ltq_etop_priv *priv = netdev_priv(dev); - struct phy_device *phydev = NULL; -- int phy_addr; - -- for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { -- if (priv->mii_bus->phy_map[phy_addr]) { -- phydev = priv->mii_bus->phy_map[phy_addr]; -- break; -- } -- } -+ if (ltq_is_ase()) -+ phydev = priv->mii_bus->phy_map[8]; -+ else -+ phydev = priv->mii_bus->phy_map[0]; - - if (!phydev) { - netdev_err(dev, "no PHY found\n"); -@@ -409,6 +521,9 @@ ltq_etop_mdio_probe(struct net_device *d - | SUPPORTED_Autoneg - | SUPPORTED_MII - | SUPPORTED_TP); -+ if (ltq_has_gbit()) -+ phydev->supported &= SUPPORTED_1000baseT_Half -+ | SUPPORTED_1000baseT_Full; - - phydev->advertising = phydev->supported; - priv->phydev = phydev; -@@ -434,8 +549,13 @@ ltq_etop_mdio_init(struct net_device *de - } - - priv->mii_bus->priv = dev; -- priv->mii_bus->read = ltq_etop_mdio_rd; -- priv->mii_bus->write = ltq_etop_mdio_wr; -+ if (ltq_has_gbit()) { -+ priv->mii_bus->read = ltq_etop_mdio_rd_xr9; -+ priv->mii_bus->write = ltq_etop_mdio_wr_xr9; -+ } else { -+ priv->mii_bus->read = ltq_etop_mdio_rd; -+ priv->mii_bus->write = ltq_etop_mdio_wr; -+ } - priv->mii_bus->name = "ltq_mii"; - snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", - priv->pdev->name, priv->pdev->id); -@@ -526,9 +646,9 @@ ltq_etop_tx(struct sk_buff *skb, struct - struct ltq_etop_priv *priv = netdev_priv(dev); - struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; - struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; -- int len; - unsigned long flags; - u32 byte_offset; -+ int len; - - len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; - -@@ -702,7 +822,7 @@ ltq_etop_probe(struct platform_device *p - { - struct net_device *dev; - struct ltq_etop_priv *priv; -- struct resource *res; -+ struct resource *res, *gbit_res; - int err; - int i; - -@@ -730,6 +850,23 @@ ltq_etop_probe(struct platform_device *p - goto err_out; - } - -+ if (ltq_has_gbit()) { -+ gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); -+ if (!gbit_res) { -+ dev_err(&pdev->dev, "failed to get gbit resource\n"); -+ err = -ENOENT; -+ goto err_out; -+ } -+ ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev, -+ gbit_res->start, resource_size(gbit_res)); -+ if (!ltq_gbit_membase) { -+ dev_err(&pdev->dev, "failed to remap gigabit switch %d\n", -+ pdev->id); -+ err = -ENOMEM; -+ goto err_out; -+ } -+ } -+ - dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); - strcpy(dev->name, "eth%d"); - dev->netdev_ops = <q_eth_netdev_ops; diff --git a/target/linux/lantiq/patches-3.3/0053-MIPS-lantiq-VPE-extensions.patch b/target/linux/lantiq/patches-3.3/0015-VPE-extensions.patch similarity index 94% rename from target/linux/lantiq/patches-3.3/0053-MIPS-lantiq-VPE-extensions.patch rename to target/linux/lantiq/patches-3.3/0015-VPE-extensions.patch index ef6f5ad3cb..2b04769098 100644 --- a/target/linux/lantiq/patches-3.3/0053-MIPS-lantiq-VPE-extensions.patch +++ b/target/linux/lantiq/patches-3.3/0015-VPE-extensions.patch @@ -1,7 +1,7 @@ -From 948bb4dd94209332253d2b69c28f44e2bb11f518 Mon Sep 17 00:00:00 2001 +From 1a3548545403c8f7cc02317643b616db6d0c9a4b Mon Sep 17 00:00:00 2001 From: John Crispin Date: Thu, 29 Sep 2011 20:30:40 +0200 -Subject: [PATCH 53/70] MIPS: lantiq: VPE extensions +Subject: [PATCH 15/25] VPE extensions --- arch/mips/Kconfig | 22 +++ @@ -17,9 +17,11 @@ Subject: [PATCH 53/70] MIPS: lantiq: VPE extensions create mode 100644 arch/mips/kernel/mtsched_proc.c create mode 100644 arch/mips/kernel/perf_proc.c +diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig +index 0e2ce5d..e152c85 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -1947,6 +1947,28 @@ config MIPS_VPE_LOADER +@@ -1948,6 +1948,28 @@ config MIPS_VPE_LOADER Includes a loader for loading an elf relocatable object onto another VPE and running it. @@ -48,6 +50,8 @@ Subject: [PATCH 53/70] MIPS: lantiq: VPE extensions config MIPS_MT_SMTC_IM_BACKSTOP bool "Use per-TC register bits as backstop for inhibited IM bits" depends on MIPS_MT_SMTC +diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h +index c9420aa..04bfb4b 100644 --- a/arch/mips/include/asm/mipsmtregs.h +++ b/arch/mips/include/asm/mipsmtregs.h @@ -28,14 +28,34 @@ @@ -157,9 +161,11 @@ Subject: [PATCH 53/70] MIPS: lantiq: VPE extensions /* GPR */ #define read_tc_gpr_sp() mftgpr(29) +diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile +index cacc340..477bcc3 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile -@@ -90,7 +90,8 @@ obj-$(CONFIG_MIPS32_O32) += binfmt_elfo3 +@@ -90,7 +90,8 @@ obj-$(CONFIG_MIPS32_O32) += binfmt_elfo32.o scall64-o32.o obj-$(CONFIG_KGDB) += kgdb.o obj-$(CONFIG_PROC_FS) += proc.o @@ -169,6 +175,8 @@ Subject: [PATCH 53/70] MIPS: lantiq: VPE extensions obj-$(CONFIG_64BIT) += cpu-bugs64.o obj-$(CONFIG_I8253) += i8253.o +diff --git a/arch/mips/kernel/mips-mt.c b/arch/mips/kernel/mips-mt.c +index c23d11f..11d6489 100644 --- a/arch/mips/kernel/mips-mt.c +++ b/arch/mips/kernel/mips-mt.c @@ -21,26 +21,96 @@ @@ -273,7 +281,7 @@ Subject: [PATCH 53/70] MIPS: lantiq: VPE extensions /* * Dump new MIPS MT state for the core. Does not leave TCs halted. -@@ -78,18 +148,18 @@ void mips_mt_regdump(unsigned long mvpct +@@ -78,18 +148,18 @@ void mips_mt_regdump(unsigned long mvpctl) if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) { printk(" VPE %d\n", i); printk(" VPEControl : %08lx\n", @@ -309,6 +317,9 @@ Subject: [PATCH 53/70] MIPS: lantiq: VPE extensions } /* +diff --git a/arch/mips/kernel/mtsched_proc.c b/arch/mips/kernel/mtsched_proc.c +new file mode 100644 +index 0000000..4dafded --- /dev/null +++ b/arch/mips/kernel/mtsched_proc.c @@ -0,0 +1,279 @@ @@ -591,6 +602,9 @@ Subject: [PATCH 53/70] MIPS: lantiq: VPE extensions + +/* Automagically create the entry */ +module_init(init_mtsched_proc); +diff --git a/arch/mips/kernel/perf_proc.c b/arch/mips/kernel/perf_proc.c +new file mode 100644 +index 0000000..7eec015 --- /dev/null +++ b/arch/mips/kernel/perf_proc.c @@ -0,0 +1,191 @@ @@ -785,6 +799,8 @@ Subject: [PATCH 53/70] MIPS: lantiq: VPE extensions + +/* Automagically create the entry */ +module_init(init_perf_proc); +diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c +index e309665..2de204f 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -7,6 +7,7 @@ @@ -795,7 +811,7 @@ Subject: [PATCH 53/70] MIPS: lantiq: VPE extensions #include #include #include -@@ -110,3 +111,19 @@ const struct seq_operations cpuinfo_op = +@@ -110,3 +111,19 @@ const struct seq_operations cpuinfo_op = { .stop = c_stop, .show = show_cpuinfo, }; @@ -815,9 +831,11 @@ Subject: [PATCH 53/70] MIPS: lantiq: VPE extensions + mips_proc = proc_mkdir("mips", NULL); + return(mips_proc); +} +diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c +index 0a42ff3..41f5258 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c -@@ -1334,6 +1334,13 @@ void smtc_get_new_mmu_context(struct mm_ +@@ -1334,6 +1334,13 @@ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu) asid = asid_cache(cpu); do { @@ -831,9 +849,11 @@ Subject: [PATCH 53/70] MIPS: lantiq: VPE extensions if (!((asid += ASID_INC) & ASID_MASK) ) { if (cpu_has_vtag_icache) flush_icache_all(); +diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c +index bfa12a4..e338ba5 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c -@@ -75,6 +75,58 @@ static struct kspd_notifications kspd_ev +@@ -75,6 +75,58 @@ static struct kspd_notifications kspd_events; static int kspd_events_reqd; #endif @@ -892,7 +912,7 @@ Subject: [PATCH 53/70] MIPS: lantiq: VPE extensions /* grab the likely amount of memory we will need. */ #ifdef CONFIG_MIPS_VPE_LOADER_TOM #define P_SIZE (2 * 1024 * 1024) -@@ -267,6 +319,13 @@ static void *alloc_progmem(unsigned long +@@ -267,6 +319,13 @@ static void *alloc_progmem(unsigned long len) void *addr; #ifdef CONFIG_MIPS_VPE_LOADER_TOM @@ -940,7 +960,7 @@ Subject: [PATCH 53/70] MIPS: lantiq: VPE extensions /* * The sde-kit passes 'memsize' to __start in $a3, so set something * here... Or set $a3 to zero and define DFLT_STACK_SIZE and -@@ -832,6 +911,9 @@ static int find_vpe_symbols(struct vpe * +@@ -832,6 +911,9 @@ static int find_vpe_symbols(struct vpe * v, Elf_Shdr * sechdrs, if ( (v->__start == 0) || (v->shared_ptr == NULL)) return -1; @@ -966,7 +986,7 @@ Subject: [PATCH 53/70] MIPS: lantiq: VPE extensions if (v->__start == 0) { printk(KERN_WARNING "VPE loader: program does not contain " "a __start symbol\n"); -@@ -1063,6 +1154,9 @@ static int vpe_open(struct inode *inode, +@@ -1063,6 +1154,9 @@ static int vpe_open(struct inode *inode, struct file *filp) struct vpe_notifications *not; struct vpe *v; int ret; @@ -976,7 +996,7 @@ Subject: [PATCH 53/70] MIPS: lantiq: VPE extensions if (minor != iminor(inode)) { /* assume only 1 device at the moment. */ -@@ -1088,7 +1182,12 @@ static int vpe_open(struct inode *inode, +@@ -1088,7 +1182,12 @@ static int vpe_open(struct inode *inode, struct file *filp) release_progmem(v->load_addr); cleanup_tc(get_tc(tclimit)); } @@ -990,7 +1010,7 @@ Subject: [PATCH 53/70] MIPS: lantiq: VPE extensions /* this of-course trashes what was there before... */ v->pbuffer = vmalloc(P_SIZE); if (!v->pbuffer) { -@@ -1096,11 +1195,14 @@ static int vpe_open(struct inode *inode, +@@ -1096,11 +1195,14 @@ static int vpe_open(struct inode *inode, struct file *filp) return -ENOMEM; } v->plen = P_SIZE; @@ -1196,3 +1216,6 @@ Subject: [PATCH 53/70] MIPS: lantiq: VPE extensions evpe(vpflags); emt(mtflags); +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0016-NET-MIPS-lantiq-non-existing-phy-was-not-handled-gra.patch b/target/linux/lantiq/patches-3.3/0016-NET-MIPS-lantiq-non-existing-phy-was-not-handled-gra.patch deleted file mode 100644 index 30053fd779..0000000000 --- a/target/linux/lantiq/patches-3.3/0016-NET-MIPS-lantiq-non-existing-phy-was-not-handled-gra.patch +++ /dev/null @@ -1,62 +0,0 @@ -From d6a9d52bfcc2d8f163e95920cf3678847bb97f18 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 15 Nov 2011 14:52:21 +0100 -Subject: [PATCH 16/70] NET: MIPS: lantiq: non existing phy was not handled - gracefully - -The code blindly assumed that that a PHY device was present causing a BadVA. -In addition the driver should not fail to load incase no PHY was found. -Instead we print the following line and continue with no attached PHY. - - etop: mdio probe failed - -Signed-off-by: John Crispin -Cc: netdev@vger.kernel.org ---- - drivers/net/ethernet/lantiq_etop.c | 14 ++++++++------ - 1 files changed, 8 insertions(+), 6 deletions(-) - ---- a/drivers/net/ethernet/lantiq_etop.c -+++ b/drivers/net/ethernet/lantiq_etop.c -@@ -614,7 +614,8 @@ ltq_etop_open(struct net_device *dev) - ltq_dma_open(&ch->dma); - napi_enable(&ch->napi); - } -- phy_start(priv->phydev); -+ if (priv->phydev) -+ phy_start(priv->phydev); - netif_tx_start_all_queues(dev); - return 0; - } -@@ -626,7 +627,8 @@ ltq_etop_stop(struct net_device *dev) - int i; - - netif_tx_stop_all_queues(dev); -- phy_stop(priv->phydev); -+ if (priv->phydev) -+ phy_stop(priv->phydev); - for (i = 0; i < MAX_DMA_CHAN; i++) { - struct ltq_etop_chan *ch = &priv->ch[i]; - -@@ -772,9 +774,10 @@ ltq_etop_init(struct net_device *dev) - if (err) - goto err_netdev; - ltq_etop_set_multicast_list(dev); -- err = ltq_etop_mdio_init(dev); -- if (err) -- goto err_netdev; -+ if (!ltq_etop_mdio_init(dev)) -+ dev->ethtool_ops = <q_etop_ethtool_ops; -+ else -+ pr_warn("etop: mdio probe failed\n");; - return 0; - - err_netdev: -@@ -870,7 +873,6 @@ ltq_etop_probe(struct platform_device *p - dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); - strcpy(dev->name, "eth%d"); - dev->netdev_ops = <q_eth_netdev_ops; -- dev->ethtool_ops = <q_etop_ethtool_ops; - priv = netdev_priv(dev); - priv->res = res; - priv->pdev = pdev; diff --git a/target/linux/lantiq/patches-3.3/0054-MIPS-lantiq-falcon-VPE-softdog.patch b/target/linux/lantiq/patches-3.3/0016-falcon-VPE-softdog.patch similarity index 93% rename from target/linux/lantiq/patches-3.3/0054-MIPS-lantiq-falcon-VPE-softdog.patch rename to target/linux/lantiq/patches-3.3/0016-falcon-VPE-softdog.patch index f48544b71f..00c9d1cca6 100644 --- a/target/linux/lantiq/patches-3.3/0054-MIPS-lantiq-falcon-VPE-softdog.patch +++ b/target/linux/lantiq/patches-3.3/0016-falcon-VPE-softdog.patch @@ -1,7 +1,7 @@ -From b7a07d349a9a05ac39f5d359a86519d93395b729 Mon Sep 17 00:00:00 2001 +From 79bbd1bfeb1dd9c66dd81605611d8d1db3e81822 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Thu, 29 Sep 2011 21:29:14 +0200 -Subject: [PATCH 54/70] MIPS: lantiq: falcon VPE softdog +Subject: [PATCH 16/25] falcon VPE softdog --- arch/mips/include/asm/mach-lantiq/falcon/vpe.h | 44 ++++++++++ @@ -10,6 +10,9 @@ Subject: [PATCH 54/70] MIPS: lantiq: falcon VPE softdog create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/vpe.h create mode 100644 arch/mips/lantiq/falcon/softdog_vpe.c +diff --git a/arch/mips/include/asm/mach-lantiq/falcon/vpe.h b/arch/mips/include/asm/mach-lantiq/falcon/vpe.h +new file mode 100644 +index 0000000..22a701b --- /dev/null +++ b/arch/mips/include/asm/mach-lantiq/falcon/vpe.h @@ -0,0 +1,44 @@ @@ -57,6 +60,9 @@ Subject: [PATCH 54/70] MIPS: lantiq: falcon VPE softdog +int32_t vpe1_sw_wdog_register_reset_handler(VPE_SW_WDOG_RESET reset_fn); + +#endif +diff --git a/arch/mips/lantiq/falcon/softdog_vpe.c b/arch/mips/lantiq/falcon/softdog_vpe.c +new file mode 100644 +index 0000000..85d22a2 --- /dev/null +++ b/arch/mips/lantiq/falcon/softdog_vpe.c @@ -0,0 +1,109 @@ @@ -169,3 +175,6 @@ Subject: [PATCH 54/70] MIPS: lantiq: falcon VPE softdog +MODULE_AUTHOR("LXDB"); +MODULE_DESCRIPTION("Software Watchdog For VPE1"); +MODULE_LICENSE("GPL"); +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0017-NET-MIPS-lantiq-return-value-of-request_irq-was-not-.patch b/target/linux/lantiq/patches-3.3/0017-NET-MIPS-lantiq-return-value-of-request_irq-was-not-.patch deleted file mode 100644 index 22ce8d6c8d..0000000000 --- a/target/linux/lantiq/patches-3.3/0017-NET-MIPS-lantiq-return-value-of-request_irq-was-not-.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 965d488202829699dd9d089adb4c8b605e9de6cd Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 15 Nov 2011 15:56:06 +0100 -Subject: [PATCH 17/70] NET: MIPS: lantiq: return value of request_irq was not - handled gracefully - -The return values of request_irq() were not checked leading to the following -error message. - -drivers/net/ethernet/lantiq_etop.c: In function 'ltq_etop_hw_init': -drivers/net/ethernet/lantiq_etop.c:368:15: warning: ignoring return value of 'request_irq', declared with attribute warn_unused_result -drivers/net/ethernet/lantiq_etop.c:377:15: warning: ignoring return value of 'request_irq', declared with attribute warn_unused_result - -Signed-off-by: John Crispin -Cc: netdev@vger.kernel.org ---- - drivers/net/ethernet/lantiq_etop.c | 14 ++++++++------ - 1 files changed, 8 insertions(+), 6 deletions(-) - ---- a/drivers/net/ethernet/lantiq_etop.c -+++ b/drivers/net/ethernet/lantiq_etop.c -@@ -313,6 +313,7 @@ ltq_etop_hw_init(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); - unsigned int mii_mode = priv->pldata->mii_mode; -+ int err = 0; - int i; - - ltq_pmu_enable(PMU_PPE); -@@ -357,7 +358,7 @@ ltq_etop_hw_init(struct net_device *dev) - - ltq_dma_init_port(DMA_PORT_ETOP); - -- for (i = 0; i < MAX_DMA_CHAN; i++) { -+ for (i = 0; i < MAX_DMA_CHAN && !err; i++) { - int irq = LTQ_DMA_ETOP + i; - struct ltq_etop_chan *ch = &priv->ch[i]; - -@@ -365,21 +366,22 @@ ltq_etop_hw_init(struct net_device *dev) - - if (IS_TX(i)) { - ltq_dma_alloc_tx(&ch->dma); -- request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, -+ err = request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, - "etop_tx", priv); - } else if (IS_RX(i)) { - ltq_dma_alloc_rx(&ch->dma); - for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; - ch->dma.desc++) - if (ltq_etop_alloc_skb(ch)) -- return -ENOMEM; -+ err = -ENOMEM; - ch->dma.desc = 0; -- request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, -+ err = request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, - "etop_rx", priv); - } -- ch->dma.irq = irq; -+ if (!err) -+ ch->dma.irq = irq; - } -- return 0; -+ return err; - } - - static void diff --git a/target/linux/lantiq/patches-3.3/0055-MIPS-lantiq-udp-in-kernel-redirect.patch b/target/linux/lantiq/patches-3.3/0017-udp-in-kernel-redirect.patch similarity index 91% rename from target/linux/lantiq/patches-3.3/0055-MIPS-lantiq-udp-in-kernel-redirect.patch rename to target/linux/lantiq/patches-3.3/0017-udp-in-kernel-redirect.patch index 98b43ab8ad..73ff0c67af 100644 --- a/target/linux/lantiq/patches-3.3/0055-MIPS-lantiq-udp-in-kernel-redirect.patch +++ b/target/linux/lantiq/patches-3.3/0017-udp-in-kernel-redirect.patch @@ -1,7 +1,7 @@ -From 186a2683b8fc1730dff28b2201d7508501a1dee4 Mon Sep 17 00:00:00 2001 +From dc3fad8c60650e2bd67d95edb01ca0eb3bb23b3d Mon Sep 17 00:00:00 2001 From: John Crispin Date: Thu, 29 Sep 2011 20:29:54 +0200 -Subject: [PATCH 55/70] MIPS: lantiq: udp in-kernel redirect +Subject: [PATCH 17/25] udp in-kernel redirect --- include/linux/udp_redirect.h | 57 +++++++++++++ @@ -13,6 +13,9 @@ Subject: [PATCH 55/70] MIPS: lantiq: udp in-kernel redirect create mode 100644 include/linux/udp_redirect.h create mode 100644 net/ipv4/udp_redirect_symb.c +diff --git a/include/linux/udp_redirect.h b/include/linux/udp_redirect.h +new file mode 100644 +index 0000000..de1e64f --- /dev/null +++ b/include/linux/udp_redirect.h @@ -0,0 +1,57 @@ @@ -73,6 +76,8 @@ Subject: [PATCH 55/70] MIPS: lantiq: udp in-kernel redirect +extern int udpredirect_getfrag(void *p, char * to, int offset, + int fraglen, int odd, struct sk_buff *skb); +#endif +diff --git a/net/Kconfig b/net/Kconfig +index b3904e8..be5e417 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -78,6 +78,12 @@ config INET @@ -88,9 +93,11 @@ Subject: [PATCH 55/70] MIPS: lantiq: udp in-kernel redirect if INET source "net/ipv4/Kconfig" source "net/ipv6/Kconfig" +diff --git a/net/ipv4/Makefile b/net/ipv4/Makefile +index 1d57fe0..9974d6e 100644 --- a/net/ipv4/Makefile +++ b/net/ipv4/Makefile -@@ -14,6 +14,9 @@ obj-y := route.o inetpeer.o protocol +@@ -14,6 +14,9 @@ obj-y := route.o inetpeer.o protocol.o \ inet_fragment.o ping.o obj-$(CONFIG_SYSCTL) += sysctl_net_ipv4.o @@ -100,6 +107,8 @@ Subject: [PATCH 55/70] MIPS: lantiq: udp in-kernel redirect obj-$(CONFIG_PROC_FS) += proc.o obj-$(CONFIG_IP_MULTIPLE_TABLES) += fib_rules.o obj-$(CONFIG_IP_MROUTE) += ipmr.o +diff --git a/net/ipv4/udp.c b/net/ipv4/udp.c +index 5d075b5..a2ee1bf 100644 --- a/net/ipv4/udp.c +++ b/net/ipv4/udp.c @@ -108,6 +108,10 @@ @@ -113,7 +122,7 @@ Subject: [PATCH 55/70] MIPS: lantiq: udp in-kernel redirect struct udp_table udp_table __read_mostly; EXPORT_SYMBOL(udp_table); -@@ -804,7 +808,7 @@ int udp_sendmsg(struct kiocb *iocb, stru +@@ -804,7 +808,7 @@ int udp_sendmsg(struct kiocb *iocb, struct sock *sk, struct msghdr *msg, u8 tos; int err, is_udplite = IS_UDPLITE(sk); int corkreq = up->corkflag || msg->msg_flags&MSG_MORE; @@ -122,7 +131,7 @@ Subject: [PATCH 55/70] MIPS: lantiq: udp in-kernel redirect struct sk_buff *skb; struct ip_options_data opt_copy; -@@ -821,7 +825,13 @@ int udp_sendmsg(struct kiocb *iocb, stru +@@ -821,7 +825,13 @@ int udp_sendmsg(struct kiocb *iocb, struct sock *sk, struct msghdr *msg, ipc.opt = NULL; ipc.tx_flags = 0; @@ -137,7 +146,7 @@ Subject: [PATCH 55/70] MIPS: lantiq: udp in-kernel redirect fl4 = &inet->cork.fl.u.ip4; if (up->pending) { -@@ -1625,6 +1635,7 @@ int __udp4_lib_rcv(struct sk_buff *skb, +@@ -1625,6 +1635,7 @@ int __udp4_lib_rcv(struct sk_buff *skb, struct udp_table *udptable, struct rtable *rt = skb_rtable(skb); __be32 saddr, daddr; struct net *net = dev_net(skb->dev); @@ -145,7 +154,7 @@ Subject: [PATCH 55/70] MIPS: lantiq: udp in-kernel redirect /* * Validate the packet. -@@ -1657,7 +1668,16 @@ int __udp4_lib_rcv(struct sk_buff *skb, +@@ -1657,7 +1668,16 @@ int __udp4_lib_rcv(struct sk_buff *skb, struct udp_table *udptable, sk = __udp4_lib_lookup_skb(skb, uh->source, uh->dest, udptable); if (sk != NULL) { @@ -172,6 +181,9 @@ Subject: [PATCH 55/70] MIPS: lantiq: udp in-kernel redirect /* ------------------------------------------------------------------------ */ #ifdef CONFIG_PROC_FS +diff --git a/net/ipv4/udp_redirect_symb.c b/net/ipv4/udp_redirect_symb.c +new file mode 100644 +index 0000000..5617e86 --- /dev/null +++ b/net/ipv4/udp_redirect_symb.c @@ -0,0 +1,186 @@ @@ -361,3 +373,6 @@ Subject: [PATCH 55/70] MIPS: lantiq: udp in-kernel redirect +EXPORT_SYMBOL(udp_do_redirect_fn); +EXPORT_SYMBOL(udpredirect_getfrag_fn); +#endif /* CONFIG_IFX_UDP_REDIRECT* */ +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0018-MIPS-lantiq-use-devres-managed-gpios.patch b/target/linux/lantiq/patches-3.3/0018-MIPS-lantiq-use-devres-managed-gpios.patch deleted file mode 100644 index c2887bf9e6..0000000000 --- a/target/linux/lantiq/patches-3.3/0018-MIPS-lantiq-use-devres-managed-gpios.patch +++ /dev/null @@ -1,259 +0,0 @@ -From 400943cf88102423ac10a19c56d053d9c1580a77 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 8 Mar 2012 08:37:25 +0100 -Subject: [PATCH 18/70] MIPS: lantiq: use devres managed gpios - -3.2 introduced devm_request_gpio() to allow managed gpios. - -The devres api requires a struct device pointer to work. Add a parameter to ltq_gpio_request() -so that managed gpios can work. - -Signed-off-by: John Crispin ---- - .../include/asm/mach-lantiq/falcon/lantiq_soc.h | 4 +--- - arch/mips/include/asm/mach-lantiq/lantiq.h | 4 ++++ - .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 --- - arch/mips/lantiq/falcon/gpio.c | 4 ++-- - arch/mips/lantiq/falcon/prom.c | 7 ------- - arch/mips/lantiq/xway/gpio.c | 4 ++-- - arch/mips/lantiq/xway/gpio_stp.c | 13 ++++++++----- - arch/mips/pci/pci-lantiq.c | 18 ++++++++++-------- - drivers/net/ethernet/lantiq_etop.c | 9 ++++++--- - drivers/tty/serial/lantiq.c | 12 ++++++++++++ - 10 files changed, 45 insertions(+), 33 deletions(-) - ---- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h -@@ -126,9 +126,7 @@ extern __iomem void *ltq_sys1_membase; - #define ltq_sys1_w32_mask(clear, set, reg) \ - ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg) - --/* gpio_request wrapper to help configure the pin */ --extern int ltq_gpio_request(unsigned int pin, unsigned int mux, -- unsigned int dir, const char *name); -+/* gpio wrapper to help configure the pin muxing */ - extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux); - - /* to keep the irq code generic we need to define these to 0 as falcon ---- a/arch/mips/include/asm/mach-lantiq/lantiq.h -+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h -@@ -37,6 +37,10 @@ extern unsigned int ltq_get_soc_type(voi - /* spinlock all ebu i/o */ - extern spinlock_t ebu_lock; - -+/* request a non-gpio and set the PIO config */ -+extern int ltq_gpio_request(struct device *dev, unsigned int pin, -+ unsigned int mux, unsigned int dir, const char *name); -+ - /* some irq helpers */ - extern void ltq_disable_irq(struct irq_data *data); - extern void ltq_mask_and_ack_irq(struct irq_data *data); ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -@@ -145,9 +145,6 @@ - extern __iomem void *ltq_ebu_membase; - extern __iomem void *ltq_cgu_membase; - --/* request a non-gpio and set the PIO config */ --extern int ltq_gpio_request(unsigned int pin, unsigned int mux, -- unsigned int dir, const char *name); - extern void ltq_pmu_enable(unsigned int module); - extern void ltq_pmu_disable(unsigned int module); - extern void ltq_cgu_enable(unsigned int clk); ---- a/arch/mips/lantiq/falcon/gpio.c -+++ b/arch/mips/lantiq/falcon/gpio.c -@@ -97,7 +97,7 @@ int ltq_gpio_mux_set(unsigned int pin, u - } - EXPORT_SYMBOL(ltq_gpio_mux_set); - --int ltq_gpio_request(unsigned int pin, unsigned int mux, -+int ltq_gpio_request(struct device *dev, unsigned int pin, unsigned int mux, - unsigned int dir, const char *name) - { - int port = pin / 100; -@@ -106,7 +106,7 @@ int ltq_gpio_request(unsigned int pin, u - if (offset >= PINS_PER_PORT || port >= MAX_PORTS) - return -EINVAL; - -- if (gpio_request(pin, name)) { -+ if (devm_gpio_request(dev, pin, name)) { - pr_err("failed to setup lantiq gpio: %s\n", name); - return -EBUSY; - } ---- a/arch/mips/lantiq/falcon/prom.c -+++ b/arch/mips/lantiq/falcon/prom.c -@@ -27,9 +27,6 @@ - #define TYPE_SHIFT 26 - #define TYPE_MASK 0x3C000000 - --#define MUXC_SIF_RX_PIN 112 --#define MUXC_SIF_TX_PIN 113 -- - /* this parameter allows us enable/disable asc1 via commandline */ - static int register_asc1; - static int __init -@@ -48,10 +45,6 @@ ltq_soc_setup(void) - falcon_register_gpio(); - if (register_asc1) { - ltq_register_asc(1); -- if (ltq_gpio_request(MUXC_SIF_RX_PIN, 3, 0, "asc1-rx")) -- pr_err("failed to request asc1-rx"); -- if (ltq_gpio_request(MUXC_SIF_TX_PIN, 3, 1, "asc1-tx")) -- pr_err("failed to request asc1-tx"); - ltq_sysctl_activate(SYSCTL_SYS1, ACTS_ASC1_ACT); - } - } ---- a/arch/mips/lantiq/xway/gpio.c -+++ b/arch/mips/lantiq/xway/gpio.c -@@ -50,14 +50,14 @@ int irq_to_gpio(unsigned int gpio) - } - EXPORT_SYMBOL(irq_to_gpio); - --int ltq_gpio_request(unsigned int pin, unsigned int mux, -+int ltq_gpio_request(struct device *dev, unsigned int pin, unsigned int mux, - unsigned int dir, const char *name) - { - int id = 0; - - if (pin >= (MAX_PORTS * PINS_PER_PORT)) - return -EINVAL; -- if (gpio_request(pin, name)) { -+ if (devm_gpio_request(dev, pin, name)) { - pr_err("failed to setup lantiq gpio: %s\n", name); - return -EBUSY; - } ---- a/arch/mips/lantiq/xway/gpio_stp.c -+++ b/arch/mips/lantiq/xway/gpio_stp.c -@@ -80,11 +80,6 @@ static struct gpio_chip ltq_stp_chip = { - - static int ltq_stp_hw_init(void) - { -- /* the 3 pins used to control the external stp */ -- ltq_gpio_request(4, 2, 1, "stp-st"); -- ltq_gpio_request(5, 2, 1, "stp-d"); -- ltq_gpio_request(6, 2, 1, "stp-sh"); -- - /* sane defaults */ - ltq_stp_w32(0, LTQ_STP_AR); - ltq_stp_w32(0, LTQ_STP_CPU0); -@@ -133,6 +128,14 @@ static int __devinit ltq_stp_probe(struc - dev_err(&pdev->dev, "failed to remap STP memory\n"); - return -ENOMEM; - } -+ -+ /* the 3 pins used to control the external stp */ -+ if (ltq_gpio_request(&pdev->dev, 4, 2, 1, "stp-st") || -+ ltq_gpio_request(&pdev->dev, 5, 2, 1, "stp-d") || -+ ltq_gpio_request(&pdev->dev, 6, 2, 1, "stp-sh")) { -+ dev_err(&pdev->dev, "failed to request needed gpios\n"); -+ return -EBUSY; -+ } - ret = gpiochip_add(<q_stp_chip); - if (!ret) - ret = ltq_stp_hw_init(); ---- a/arch/mips/pci/pci-lantiq.c -+++ b/arch/mips/pci/pci-lantiq.c -@@ -150,24 +150,26 @@ static u32 ltq_calc_bar11mask(void) - return bar11mask; - } - --static void ltq_pci_setup_gpio(int gpio) -+static void ltq_pci_setup_gpio(struct device *dev) - { -+ struct ltq_pci_data *conf = (struct ltq_pci_data *) dev->platform_data; - int i; - for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) { -- if (gpio & (1 << i)) { -- ltq_gpio_request(ltq_pci_gpio_map[i].pin, -+ if (conf->gpio & (1 << i)) { -+ ltq_gpio_request(dev, ltq_pci_gpio_map[i].pin, - ltq_pci_gpio_map[i].mux, - ltq_pci_gpio_map[i].dir, - ltq_pci_gpio_map[i].name); - } - } -- ltq_gpio_request(21, 0, 1, "pci-reset"); -- ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK; -+ ltq_gpio_request(dev, 21, 0, 1, "pci-reset"); -+ ltq_pci_req_mask = (conf->gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK; - } - --static int __devinit ltq_pci_startup(struct ltq_pci_data *conf) -+static int __devinit ltq_pci_startup(struct device *dev) - { - u32 temp_buffer; -+ struct ltq_pci_data *conf = (struct ltq_pci_data *) dev->platform_data; - - /* set clock to 33Mhz */ - if (ltq_is_ar9()) { -@@ -190,7 +192,7 @@ static int __devinit ltq_pci_startup(str - } - - /* setup pci clock and gpis used by pci */ -- ltq_pci_setup_gpio(conf->gpio); -+ ltq_pci_setup_gpio(dev); - - /* enable auto-switching between PCI and EBU */ - ltq_pci_w32(0xa, PCI_CR_CLK_CTRL); -@@ -275,7 +277,7 @@ static int __devinit ltq_pci_probe(struc - ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE); - ltq_pci_controller.io_map_base = - (unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1); -- ltq_pci_startup(ltq_pci_data); -+ ltq_pci_startup(&pdev->dev); - register_pci_controller(<q_pci_controller); - - return 0; ---- a/drivers/net/ethernet/lantiq_etop.c -+++ b/drivers/net/ethernet/lantiq_etop.c -@@ -292,9 +292,6 @@ ltq_etop_gbit_init(void) - { - ltq_pmu_enable(PMU_SWITCH); - -- ltq_gpio_request(42, 2, 1, "MDIO"); -- ltq_gpio_request(43, 2, 1, "MDC"); -- - ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); - /** Disable MDIO auto polling mode */ - ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL); -@@ -870,6 +867,12 @@ ltq_etop_probe(struct platform_device *p - err = -ENOMEM; - goto err_out; - } -+ if (ltq_gpio_request(&pdev->dev, 42, 2, 1, "MDIO") || -+ ltq_gpio_request(&pdev->dev, 43, 2, 1, "MDC")) { -+ dev_err(&pdev->dev, "failed to request MDIO gpios\n"); -+ err = -EBUSY; -+ goto err_out; -+ } - } - - dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); ---- a/drivers/tty/serial/lantiq.c -+++ b/drivers/tty/serial/lantiq.c -@@ -107,6 +107,9 @@ - #define ASCFSTAT_TXFREEMASK 0x3F000000 - #define ASCFSTAT_TXFREEOFF 24 - -+#define MUXC_SIF_RX_PIN 112 -+#define MUXC_SIF_TX_PIN 113 -+ - static void lqasc_tx_chars(struct uart_port *port); - static struct ltq_uart_port *lqasc_port[MAXPORTS]; - static struct uart_driver lqasc_reg; -@@ -529,6 +532,15 @@ lqasc_request_port(struct uart_port *por - if (port->membase == NULL) - return -ENOMEM; - } -+ if (ltq_is_falcon() && (port->line == 1)) { -+ struct ltq_uart_port *ltq_port = lqasc_port[pdev->id]; -+ if (ltq_gpio_request(&pdev->dev, MUXC_SIF_RX_PIN, -+ 3, 0, "asc1-rx")) -+ return -EBUSY; -+ if (ltq_gpio_request(&pdev->dev, MUXC_SIF_TX_PIN, -+ 3, 1, "asc1-tx")) -+ return -EBUSY; -+ } - return 0; - } - diff --git a/target/linux/lantiq/patches-3.3/0056-MIPS-lantiq-cache-split.patch b/target/linux/lantiq/patches-3.3/0018-cache-split.patch similarity index 93% rename from target/linux/lantiq/patches-3.3/0056-MIPS-lantiq-cache-split.patch rename to target/linux/lantiq/patches-3.3/0018-cache-split.patch index edaa588633..c571a45117 100644 --- a/target/linux/lantiq/patches-3.3/0056-MIPS-lantiq-cache-split.patch +++ b/target/linux/lantiq/patches-3.3/0018-cache-split.patch @@ -1,7 +1,7 @@ -From d137c7d096436ed5673d1555687423d627a07086 Mon Sep 17 00:00:00 2001 +From d38bc3854ee2fb9d3e6080b89dd6774dd5d39c2b Mon Sep 17 00:00:00 2001 From: John Crispin Date: Thu, 29 Sep 2011 20:31:54 +0200 -Subject: [PATCH 56/70] MIPS: lantiq: cache split +Subject: [PATCH 18/25] cache split --- arch/mips/Kconfig | 22 ++++++ @@ -9,9 +9,11 @@ Subject: [PATCH 56/70] MIPS: lantiq: cache split arch/mips/mm/c-r4k.c | 172 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 260 insertions(+), 0 deletions(-) +diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig +index e152c85..39e698f 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig -@@ -1954,6 +1954,28 @@ config IFX_VPE_EXT +@@ -1955,6 +1955,28 @@ config IFX_VPE_EXT help IFX included extensions in APRP @@ -40,9 +42,11 @@ Subject: [PATCH 56/70] MIPS: lantiq: cache split config PERFCTRS bool "34K Performance counters" depends on MIPS_MT && PROC_FS +diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c +index e338ba5..0511d11 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c -@@ -127,6 +127,13 @@ __setup("vpe1_wdog_timeout=", wdog_timeo +@@ -127,6 +127,13 @@ __setup("vpe1_wdog_timeout=", wdog_timeout); EXPORT_SYMBOL(vpe1_wdog_timeout); #endif @@ -122,9 +126,11 @@ Subject: [PATCH 56/70] MIPS: lantiq: cache split /* clear out any left overs from a previous program */ write_vpe_c0_status(0); write_vpe_c0_cause(0); +diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c +index de3475e..41aee8b 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c -@@ -1386,6 +1386,106 @@ static int __init setcoherentio(char *st +@@ -1389,6 +1389,106 @@ static int __init setcoherentio(char *str) __setup("coherentio", setcoherentio); #endif @@ -231,7 +237,7 @@ Subject: [PATCH 56/70] MIPS: lantiq: cache split void __cpuinit r4k_cache_init(void) { extern void build_clear_page(void); -@@ -1405,6 +1505,78 @@ void __cpuinit r4k_cache_init(void) +@@ -1408,6 +1508,78 @@ void __cpuinit r4k_cache_init(void) break; } @@ -310,3 +316,6 @@ Subject: [PATCH 56/70] MIPS: lantiq: cache split probe_pcache(); setup_scache(); +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0019-MIPS-add-clkdev.h.patch b/target/linux/lantiq/patches-3.3/0019-MIPS-add-clkdev.h.patch deleted file mode 100644 index cd799855f2..0000000000 --- a/target/linux/lantiq/patches-3.3/0019-MIPS-add-clkdev.h.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 7396c59a2be411a11c640d79417ff257f1b94eff Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 16 Feb 2012 20:23:36 +0100 -Subject: [PATCH 19/70] MIPS: add clkdev.h - -For clkdev to work on MIPS we need this file - -include/linux/clkdev.h:#include - -Signed-off-by: John Crispin ---- - arch/mips/include/asm/clkdev.h | 25 +++++++++++++++++++++++++ - 1 files changed, 25 insertions(+), 0 deletions(-) - create mode 100644 arch/mips/include/asm/clkdev.h - ---- /dev/null -+++ b/arch/mips/include/asm/clkdev.h -@@ -0,0 +1,25 @@ -+/* -+ * based on arch/arm/include/asm/clkdev.h -+ * -+ * Copyright (C) 2008 Russell King. -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ * Helper for the clk API to assist looking up a struct clk. -+ */ -+#ifndef __ASM_CLKDEV_H -+#define __ASM_CLKDEV_H -+ -+#include -+ -+#define __clk_get(clk) ({ 1; }) -+#define __clk_put(clk) do { } while (0) -+ -+static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size) -+{ -+ return kzalloc(size, GFP_KERNEL); -+} -+ -+#endif diff --git a/target/linux/lantiq/patches-3.3/201-owrt-mtd_split.patch b/target/linux/lantiq/patches-3.3/0019-owrt-mtd-split.patch similarity index 82% rename from target/linux/lantiq/patches-3.3/201-owrt-mtd_split.patch rename to target/linux/lantiq/patches-3.3/0019-owrt-mtd-split.patch index 91069da81f..601b50719b 100644 --- a/target/linux/lantiq/patches-3.3/201-owrt-mtd_split.patch +++ b/target/linux/lantiq/patches-3.3/0019-owrt-mtd-split.patch @@ -1,3 +1,54 @@ +From 2a295753a10823a47542c779a25bbb1f52c71281 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 10:27:13 +0200 +Subject: [PATCH 19/25] owrt mtd split + +--- + .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 1 + + arch/mips/lantiq/setup.c | 7 + + drivers/mtd/Kconfig | 4 + + drivers/mtd/mtdpart.c | 173 +++++++++++++++++++- + 4 files changed, 184 insertions(+), 1 deletions(-) + +diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +index 1ec8f2a..1ff93cc 100644 +--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +@@ -166,6 +166,7 @@ extern unsigned char ltq_boot_select(void); + + extern __iomem void *ltq_ebu_membase; + extern __iomem void *ltq_cgu_membase; ++extern unsigned long ltq_brn_boot; + + static inline int ltq_is_ase(void) + { +diff --git a/arch/mips/lantiq/setup.c b/arch/mips/lantiq/setup.c +index 1ff6c9d..708e969 100644 +--- a/arch/mips/lantiq/setup.c ++++ b/arch/mips/lantiq/setup.c +@@ -18,6 +18,9 @@ + #include "devices.h" + #include "prom.h" + ++/* set to 1 if the bootloader is BRN-BOOT instead of u-boot */ ++unsigned long ltq_brn_boot = 0; ++ + void __init plat_mem_setup(void) + { + /* assume 16M as default incase uboot fails to pass proper ramsize */ +@@ -38,6 +41,10 @@ void __init plat_mem_setup(void) + if (strict_strtoul(e, 0, &memsize)) + pr_warn("bad memsize specified\n"); + } ++ if (!strncmp(e, "BRN-BOOT", 8)){ ++ pr_info("Found BRN-BOOT instead of u-boot\n"); ++ ltq_brn_boot = 1; ++ } + envp++; + } + memsize *= 1024 * 1024; +diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig +index 982a98b..e2f3f3e 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -31,6 +31,10 @@ config MTD_ROOTFS_SPLIT @@ -11,9 +62,11 @@ config MTD_REDBOOT_PARTS tristate "RedBoot partition table parsing" ---help--- +diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c +index 855b70b..93711e2 100644 --- a/drivers/mtd/mtdpart.c +++ b/drivers/mtd/mtdpart.c -@@ -867,6 +867,168 @@ static int refresh_rootfs_split(struct m +@@ -867,6 +867,168 @@ static int refresh_rootfs_split(struct mtd_info *mtd) } #endif /* CONFIG_MTD_ROOTFS_SPLIT */ @@ -182,7 +235,7 @@ /* * This function, given a master MTD object and a partition table, creates * and registers slave MTD objects which are bound to the master according to -@@ -883,7 +1045,7 @@ int add_mtd_partitions(struct mtd_info * +@@ -883,7 +1045,7 @@ int add_mtd_partitions(struct mtd_info *master, struct mtd_part *slave; uint64_t cur_offset = 0; int i; @@ -191,7 +244,7 @@ int ret; #endif -@@ -900,6 +1062,15 @@ int add_mtd_partitions(struct mtd_info * +@@ -900,6 +1062,15 @@ int add_mtd_partitions(struct mtd_info *master, add_mtd_device(&slave->mtd); @@ -207,36 +260,6 @@ if (!strcmp(parts[i].name, "rootfs")) { #ifdef CONFIG_MTD_ROOTFS_ROOT_DEV if (ROOT_DEV == 0) { ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -@@ -166,6 +166,7 @@ extern unsigned char ltq_boot_select(voi - - extern __iomem void *ltq_ebu_membase; - extern __iomem void *ltq_cgu_membase; -+extern unsigned long ltq_brn_boot; - - static inline int ltq_is_ase(void) - { ---- a/arch/mips/lantiq/setup.c -+++ b/arch/mips/lantiq/setup.c -@@ -18,6 +18,9 @@ - #include "devices.h" - #include "prom.h" - -+/* set to 1 if the bootloader is BRN-BOOT instead of u-boot */ -+unsigned long ltq_brn_boot = 0; -+ - void __init plat_mem_setup(void) - { - /* assume 16M as default incase uboot fails to pass proper ramsize */ -@@ -38,6 +41,10 @@ void __init plat_mem_setup(void) - if (strict_strtoul(e, 0, &memsize)) - pr_warn("bad memsize specified\n"); - } -+ if (!strncmp(e, "BRN-BOOT", 8)){ -+ pr_info("Found BRN-BOOT instead of u-boot\n"); -+ ltq_brn_boot = 1; -+ } - envp++; - } - memsize *= 1024 * 1024; +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0020-MIPS-lantiq-helper-functions-for-SoC-detection.patch b/target/linux/lantiq/patches-3.3/0020-MIPS-lantiq-helper-functions-for-SoC-detection.patch deleted file mode 100644 index 9a9094980d..0000000000 --- a/target/linux/lantiq/patches-3.3/0020-MIPS-lantiq-helper-functions-for-SoC-detection.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 601e5ea89b1fd6fb8047ea7c23eae6eb1c90145f Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 21 Feb 2012 14:25:03 +0100 -Subject: [PATCH 20/70] MIPS: lantiq: helper functions for SoC detection - -Add additional functions for runtime soc detection. We need these for the -serial driver. - -Signed-off-by: John Crispin ---- - .../include/asm/mach-lantiq/falcon/lantiq_soc.h | 16 ++++++++++++++-- - .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 5 +++++ - 2 files changed, 19 insertions(+), 2 deletions(-) - ---- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h -@@ -134,8 +134,20 @@ extern int ltq_gpio_mux_set(unsigned int - #define LTQ_EIU_BASE_ADDR 0 - #define LTQ_EBU_PCC_ISTAT 0 - --#define ltq_is_ar9() 0 --#define ltq_is_vr9() 0 -+static inline int ltq_is_ar9(void) -+{ -+ return 0; -+} -+ -+static inline int ltq_is_vr9(void) -+{ -+ return 0; -+} -+ -+static inline int ltq_is_falcon(void) -+{ -+ return 1; -+} - - #endif /* CONFIG_SOC_FALCON */ - #endif /* _LTQ_XWAY_H__ */ ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -@@ -164,5 +164,10 @@ static inline int ltq_is_vr9(void) - return (ltq_get_soc_type() == SOC_TYPE_VR9); - } - -+static inline int ltq_is_falcon(void) -+{ -+ return 0; -+} -+ - #endif /* CONFIG_SOC_TYPE_XWAY */ - #endif /* _LTQ_XWAY_H__ */ diff --git a/target/linux/lantiq/patches-3.3/202-owrt-atm.patch b/target/linux/lantiq/patches-3.3/0020-owrt-atm.patch similarity index 56% rename from target/linux/lantiq/patches-3.3/202-owrt-atm.patch rename to target/linux/lantiq/patches-3.3/0020-owrt-atm.patch index a9ded7a903..db7c49f822 100644 --- a/target/linux/lantiq/patches-3.3/202-owrt-atm.patch +++ b/target/linux/lantiq/patches-3.3/0020-owrt-atm.patch @@ -1,3 +1,17 @@ +From 8d2a7d1fb561c9cb098c2b13ded34fe0f49dcca5 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 10:27:25 +0200 +Subject: [PATCH 20/25] owrt atm + +--- + arch/mips/lantiq/irq.c | 2 ++ + arch/mips/mm/cache.c | 2 ++ + net/atm/common.c | 6 ++++++ + net/atm/proc.c | 2 +- + 4 files changed, 11 insertions(+), 1 deletions(-) + +diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c +index 63dbb83..1e89104 100644 --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -10,6 +10,7 @@ @@ -8,17 +22,19 @@ #include #include -@@ -111,6 +112,7 @@ void ltq_mask_and_ack_irq(struct irq_dat - ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier); - ltq_icu_w32((1 << irq_nr), isr); +@@ -171,6 +172,7 @@ void ltq_disable_irq(struct irq_data *d) + ltq_icu_w32(ltq_icu_r32(LTQ_ICU_IM0_IER, im_nr) & ~(1 << irq_nr), + LTQ_ICU_IM0_IER, im_nr); } +EXPORT_SYMBOL(ltq_mask_and_ack_irq); - static void ltq_ack_irq(struct irq_data *d) + void ltq_mask_and_ack_irq(struct irq_data *d) { +diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c +index ef83ef1..c156456 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c -@@ -57,6 +57,8 @@ void (*_dma_cache_wback)(unsigned long s +@@ -58,6 +58,8 @@ void (*_dma_cache_wback)(unsigned long start, unsigned long size); void (*_dma_cache_inv)(unsigned long start, unsigned long size); EXPORT_SYMBOL(_dma_cache_wback_inv); @@ -27,20 +43,11 @@ #endif /* CONFIG_DMA_NONCOHERENT */ ---- a/net/atm/proc.c -+++ b/net/atm/proc.c -@@ -154,7 +154,7 @@ static void *vcc_seq_next(struct seq_fil - static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc) - { - static const char *const class_name[] = { -- "off", "UBR", "CBR", "VBR", "ABR"}; -+ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"}; - static const char *const aal_name[] = { - "---", "1", "2", "3/4", /* 0- 3 */ - "???", "5", "???", "???", /* 4- 7 */ +diff --git a/net/atm/common.c b/net/atm/common.c +index b4b44db..c30b397 100644 --- a/net/atm/common.c +++ b/net/atm/common.c -@@ -62,11 +62,17 @@ static void vcc_remove_socket(struct soc +@@ -62,11 +62,17 @@ static void vcc_remove_socket(struct sock *sk) write_unlock_irq(&vcc_sklist_lock); } @@ -58,3 +65,19 @@ if (sk_wmem_alloc_get(sk) && !atm_may_send(vcc, size)) { pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n", sk_wmem_alloc_get(sk), size, sk->sk_sndbuf); +diff --git a/net/atm/proc.c b/net/atm/proc.c +index 0d020de..9fdb539 100644 +--- a/net/atm/proc.c ++++ b/net/atm/proc.c +@@ -154,7 +154,7 @@ static void *vcc_seq_next(struct seq_file *seq, void *v, loff_t *pos) + static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc) + { + static const char *const class_name[] = { +- "off", "UBR", "CBR", "VBR", "ABR"}; ++ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"}; + static const char *const aal_name[] = { + "---", "1", "2", "3/4", /* 0- 3 */ + "???", "5", "???", "???", /* 4- 7 */ +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0021-MIPS-lantiq-convert-to-clkdev-api.patch b/target/linux/lantiq/patches-3.3/0021-MIPS-lantiq-convert-to-clkdev-api.patch deleted file mode 100644 index 48ceef206c..0000000000 --- a/target/linux/lantiq/patches-3.3/0021-MIPS-lantiq-convert-to-clkdev-api.patch +++ /dev/null @@ -1,285 +0,0 @@ -From 69f1bf02b0c6b132140326320d26aa4e91bc3290 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 8 Mar 2012 08:39:06 +0100 -Subject: [PATCH 21/70] MIPS: lantiq: convert to clkdev api - -* Change setup from HAVE_CLK -> HAVE_MACH_CLKDEV/CLKDEV_LOOKUP -* Add clk_activate/clk_deactivate -* Add better error paths to the clk_*() functions -* Change the way our static clocks are referenced - -Signed-off-by: John Crispin ---- - arch/mips/Kconfig | 3 +- - arch/mips/include/asm/mach-lantiq/lantiq.h | 20 ++---- - arch/mips/lantiq/clk.c | 96 +++++++++++++++------------ - arch/mips/lantiq/clk.h | 52 ++++++++++++++- - arch/mips/lantiq/prom.c | 1 - - 5 files changed, 111 insertions(+), 61 deletions(-) - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -228,7 +228,8 @@ config LANTIQ - select ARCH_REQUIRE_GPIOLIB - select SWAP_IO_SPACE - select BOOT_RAW -- select HAVE_CLK -+ select HAVE_MACH_CLKDEV -+ select CLKDEV_LOOKUP - select HAVE_OPROFILE - select MIPS_MACHINE - ---- a/arch/mips/include/asm/mach-lantiq/lantiq.h -+++ b/arch/mips/include/asm/mach-lantiq/lantiq.h -@@ -9,6 +9,7 @@ - #define _LANTIQ_H__ - - #include -+#include - #include - - /* generic reg access functions */ -@@ -22,18 +23,6 @@ - extern unsigned int ltq_get_cpu_ver(void); - extern unsigned int ltq_get_soc_type(void); - --/* clock speeds */ --#define CLOCK_60M 60000000 --#define CLOCK_83M 83333333 --#define CLOCK_100M 100000000 --#define CLOCK_111M 111111111 --#define CLOCK_133M 133333333 --#define CLOCK_167M 166666667 --#define CLOCK_200M 200000000 --#define CLOCK_266M 266666666 --#define CLOCK_333M 333333333 --#define CLOCK_400M 400000000 -- - /* spinlock all ebu i/o */ - extern spinlock_t ebu_lock; - -@@ -46,6 +35,13 @@ extern void ltq_disable_irq(struct irq_d - extern void ltq_mask_and_ack_irq(struct irq_data *data); - extern void ltq_enable_irq(struct irq_data *data); - -+/* clock handling */ -+extern int clk_activate(struct clk *clk); -+extern void clk_deactivate(struct clk *clk); -+extern struct clk *clk_get_cpu(void); -+extern struct clk *clk_get_fpi(void); -+extern struct clk *clk_get_io(void); -+ - /* find out what caused the last cpu reset */ - extern int ltq_reset_cause(void); - ---- a/arch/mips/lantiq/clk.c -+++ b/arch/mips/lantiq/clk.c -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -24,33 +25,29 @@ - #include "clk.h" - #include "prom.h" - --struct clk { -- const char *name; -- unsigned long rate; -- unsigned long (*get_rate) (void); --}; -+/* lantiq socs have 3 static clocks */ -+static struct clk cpu_clk_generic[3]; - --static struct clk *cpu_clk; --static int cpu_clk_cnt; -+void clkdev_add_static(unsigned long cpu, unsigned long fpi, unsigned long io) -+{ -+ cpu_clk_generic[0].rate = cpu; -+ cpu_clk_generic[1].rate = fpi; -+ cpu_clk_generic[2].rate = io; -+} - --/* lantiq socs have 3 static clocks */ --static struct clk cpu_clk_generic[] = { -- { -- .name = "cpu", -- .get_rate = ltq_get_cpu_hz, -- }, { -- .name = "fpi", -- .get_rate = ltq_get_fpi_hz, -- }, { -- .name = "io", -- .get_rate = ltq_get_io_region_clock, -- }, --}; -+struct clk *clk_get_cpu(void) -+{ -+ return &cpu_clk_generic[0]; -+} -+ -+struct clk *clk_get_fpi(void) -+{ -+ return &cpu_clk_generic[1]; -+} - --void clk_init(void) -+struct clk *clk_get_io(void) - { -- cpu_clk = cpu_clk_generic; -- cpu_clk_cnt = ARRAY_SIZE(cpu_clk_generic); -+ return &cpu_clk_generic[2]; - } - - static inline int clk_good(struct clk *clk) -@@ -73,36 +70,49 @@ unsigned long clk_get_rate(struct clk *c - } - EXPORT_SYMBOL(clk_get_rate); - --struct clk *clk_get(struct device *dev, const char *id) -+int clk_enable(struct clk *clk) - { -- int i; -+ if (unlikely(!clk_good(clk))) -+ return -1; - -- for (i = 0; i < cpu_clk_cnt; i++) -- if (!strcmp(id, cpu_clk[i].name)) -- return &cpu_clk[i]; -- BUG(); -- return ERR_PTR(-ENOENT); -+ if (clk->enable) -+ return clk->enable(clk); -+ -+ return -1; - } --EXPORT_SYMBOL(clk_get); -+EXPORT_SYMBOL(clk_enable); - --void clk_put(struct clk *clk) -+void clk_disable(struct clk *clk) - { -- /* not used */ -+ if (unlikely(!clk_good(clk))) -+ return; -+ -+ if (clk->disable) -+ clk->disable(clk); - } --EXPORT_SYMBOL(clk_put); -+EXPORT_SYMBOL(clk_disable); - --int clk_enable(struct clk *clk) -+int clk_activate(struct clk *clk) - { -- /* not used */ -- return 0; -+ if (unlikely(!clk_good(clk))) -+ return -1; -+ -+ if (clk->activate) -+ return clk->activate(clk); -+ -+ return -1; - } --EXPORT_SYMBOL(clk_enable); -+EXPORT_SYMBOL(clk_activate); - --void clk_disable(struct clk *clk) -+void clk_deactivate(struct clk *clk) - { -- /* not used */ -+ if (unlikely(!clk_good(clk))) -+ return; -+ -+ if (clk->deactivate) -+ clk->deactivate(clk); - } --EXPORT_SYMBOL(clk_disable); -+EXPORT_SYMBOL(clk_deactivate); - - static inline u32 ltq_get_counter_resolution(void) - { -@@ -126,7 +136,7 @@ void __init plat_time_init(void) - - ltq_soc_init(); - -- clk = clk_get(0, "cpu"); -+ clk = clk_get_cpu(); - mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution(); - write_c0_compare(read_c0_count()); - pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); ---- a/arch/mips/lantiq/clk.h -+++ b/arch/mips/lantiq/clk.h -@@ -9,10 +9,54 @@ - #ifndef _LTQ_CLK_H__ - #define _LTQ_CLK_H__ - --extern void clk_init(void); -+#include - --extern unsigned long ltq_get_cpu_hz(void); --extern unsigned long ltq_get_fpi_hz(void); --extern unsigned long ltq_get_io_region_clock(void); -+/* clock speeds */ -+#define CLOCK_60M 60000000 -+#define CLOCK_62_5M 62500000 -+#define CLOCK_83M 83333333 -+#define CLOCK_83_5M 83500000 -+#define CLOCK_98_304M 98304000 -+#define CLOCK_100M 100000000 -+#define CLOCK_111M 111111111 -+#define CLOCK_125M 125000000 -+#define CLOCK_133M 133333333 -+#define CLOCK_150M 150000000 -+#define CLOCK_166M 166666666 -+#define CLOCK_167M 166666667 -+#define CLOCK_196_608M 196608000 -+#define CLOCK_200M 200000000 -+#define CLOCK_250M 250000000 -+#define CLOCK_266M 266666666 -+#define CLOCK_300M 300000000 -+#define CLOCK_333M 333333333 -+#define CLOCK_393M 393215332 -+#define CLOCK_400M 400000000 -+#define CLOCK_500M 500000000 -+#define CLOCK_600M 600000000 -+ -+struct clk { -+ struct clk_lookup cl; -+ unsigned long rate; -+ unsigned long (*get_rate) (void); -+ unsigned int module; -+ unsigned int bits; -+ int (*enable) (struct clk *clk); -+ void (*disable) (struct clk *clk); -+ int (*activate) (struct clk *clk); -+ void (*deactivate) (struct clk *clk); -+ void (*reboot) (struct clk *clk); -+}; -+ -+extern void clkdev_add_static(unsigned long cpu, unsigned long fpi, -+ unsigned long io); -+ -+extern unsigned long ltq_danube_cpu_hz(void); -+extern unsigned long ltq_danube_fpi_hz(void); -+extern unsigned long ltq_danube_io_region_clock(void); -+ -+extern unsigned long ltq_vr9_cpu_hz(void); -+extern unsigned long ltq_vr9_fpi_hz(void); -+extern unsigned long ltq_vr9_io_region_clock(void); - - #endif ---- a/arch/mips/lantiq/prom.c -+++ b/arch/mips/lantiq/prom.c -@@ -103,7 +103,6 @@ EXPORT_SYMBOL(ltq_remap_resource); - void __init prom_init(void) - { - ltq_soc_detect(&soc_info); -- clk_init(); - snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s", - soc_info.name, soc_info.rev_type); - soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; diff --git a/target/linux/lantiq/patches-3.3/203-owrt-cmdline.patch b/target/linux/lantiq/patches-3.3/0021-owrt-cmdline.patch similarity index 64% rename from target/linux/lantiq/patches-3.3/203-owrt-cmdline.patch rename to target/linux/lantiq/patches-3.3/0021-owrt-cmdline.patch index cd7c95a9c7..61ddd08442 100644 --- a/target/linux/lantiq/patches-3.3/203-owrt-cmdline.patch +++ b/target/linux/lantiq/patches-3.3/0021-owrt-cmdline.patch @@ -1,3 +1,14 @@ +From 9189efcc94f8492f403162484c5d2fc35c9f3fd1 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 10:27:43 +0200 +Subject: [PATCH 21/25] owrt cmdline + +--- + arch/mips/lantiq/prom.c | 29 +++++++++++++++++++++++++++++ + 1 files changed, 29 insertions(+), 0 deletions(-) + +diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c +index 00ad59c..0fdef27 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -43,6 +43,34 @@ void prom_free_prom_memory(void) @@ -35,7 +46,7 @@ static void __init prom_init_cmdline(void) { int argc = fw_arg0; -@@ -59,6 +87,7 @@ static void __init prom_init_cmdline(voi +@@ -59,6 +87,7 @@ static void __init prom_init_cmdline(void) strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); } } @@ -43,3 +54,6 @@ } void __iomem *ltq_remap_resource(struct resource *res) +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0022-MIPS-lantiq-convert-xway-to-clkdev-api.patch b/target/linux/lantiq/patches-3.3/0022-MIPS-lantiq-convert-xway-to-clkdev-api.patch deleted file mode 100644 index 3e000f6173..0000000000 --- a/target/linux/lantiq/patches-3.3/0022-MIPS-lantiq-convert-xway-to-clkdev-api.patch +++ /dev/null @@ -1,718 +0,0 @@ -From de49a17fd2d9a73b9449f04061bb08eb5d73fe98 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 8 Mar 2012 11:18:22 +0100 -Subject: [PATCH 22/70] MIPS: lantiq: convert xway to clkdev api - -Unify xway/ase clock code and add clkdev hooks to sysctrl.c - -Signed-off-by: John Crispin ---- - .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 13 -- - arch/mips/lantiq/xway/Makefile | 6 +- - arch/mips/lantiq/xway/clk-ase.c | 48 ---- - arch/mips/lantiq/xway/clk-xway.c | 223 ------------------- - arch/mips/lantiq/xway/clk.c | 227 ++++++++++++++++++++ - arch/mips/lantiq/xway/sysctrl.c | 104 ++++++++- - 6 files changed, 325 insertions(+), 296 deletions(-) - delete mode 100644 arch/mips/lantiq/xway/clk-ase.c - delete mode 100644 arch/mips/lantiq/xway/clk-xway.c - create mode 100644 arch/mips/lantiq/xway/clk.c - ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -@@ -81,15 +81,6 @@ - #define LTQ_PMU_BASE_ADDR 0x1F102000 - #define LTQ_PMU_SIZE 0x1000 - --#define PMU_DMA 0x0020 --#define PMU_EPHY 0x0080 --#define PMU_USB 0x8041 --#define PMU_LED 0x0800 --#define PMU_GPT 0x1000 --#define PMU_PPE 0x2000 --#define PMU_FPI 0x4000 --#define PMU_SWITCH 0x10000000 -- - /* ETOP - ethernet */ - #define LTQ_ETOP_BASE_ADDR 0x1E180000 - #define LTQ_ETOP_SIZE 0x40000 -@@ -145,10 +136,6 @@ - extern __iomem void *ltq_ebu_membase; - extern __iomem void *ltq_cgu_membase; - --extern void ltq_pmu_enable(unsigned int module); --extern void ltq_pmu_disable(unsigned int module); --extern void ltq_cgu_enable(unsigned int clk); -- - static inline int ltq_is_ase(void) - { - return (ltq_get_soc_type() == SOC_TYPE_AMAZON_SE); ---- a/arch/mips/lantiq/xway/Makefile -+++ b/arch/mips/lantiq/xway/Makefile -@@ -1,7 +1,7 @@ --obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o -+obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o - --obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o --obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o -+obj-$(CONFIG_SOC_XWAY) += prom-xway.o -+obj-$(CONFIG_SOC_AMAZON_SE) += prom-ase.o - - obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o - obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o ---- a/arch/mips/lantiq/xway/clk-ase.c -+++ /dev/null -@@ -1,48 +0,0 @@ --/* -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- * -- * Copyright (C) 2011 John Crispin -- */ -- --#include --#include --#include --#include -- --#include --#include --#include -- --#include -- --/* cgu registers */ --#define LTQ_CGU_SYS 0x0010 -- --unsigned int ltq_get_io_region_clock(void) --{ -- return CLOCK_133M; --} --EXPORT_SYMBOL(ltq_get_io_region_clock); -- --unsigned int ltq_get_fpi_bus_clock(int fpi) --{ -- return CLOCK_133M; --} --EXPORT_SYMBOL(ltq_get_fpi_bus_clock); -- --unsigned int ltq_get_cpu_hz(void) --{ -- if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5)) -- return CLOCK_266M; -- else -- return CLOCK_133M; --} --EXPORT_SYMBOL(ltq_get_cpu_hz); -- --unsigned int ltq_get_fpi_hz(void) --{ -- return CLOCK_133M; --} --EXPORT_SYMBOL(ltq_get_fpi_hz); ---- a/arch/mips/lantiq/xway/clk-xway.c -+++ /dev/null -@@ -1,223 +0,0 @@ --/* -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- * -- * Copyright (C) 2010 John Crispin -- */ -- --#include --#include --#include --#include -- --#include --#include --#include -- --#include -- --static unsigned int ltq_ram_clocks[] = { -- CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M }; --#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3] -- --#define BASIC_FREQUENCY_1 35328000 --#define BASIC_FREQUENCY_2 36000000 --#define BASIS_REQUENCY_USB 12000000 -- --#define GET_BITS(x, msb, lsb) \ -- (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) -- --#define LTQ_CGU_PLL0_CFG 0x0004 --#define LTQ_CGU_PLL1_CFG 0x0008 --#define LTQ_CGU_PLL2_CFG 0x000C --#define LTQ_CGU_SYS 0x0010 --#define LTQ_CGU_UPDATE 0x0014 --#define LTQ_CGU_IF_CLK 0x0018 --#define LTQ_CGU_OSC_CON 0x001C --#define LTQ_CGU_SMD 0x0020 --#define LTQ_CGU_CT1SR 0x0028 --#define LTQ_CGU_CT2SR 0x002C --#define LTQ_CGU_PCMCR 0x0030 --#define LTQ_CGU_PCI_CR 0x0034 --#define LTQ_CGU_PD_PC 0x0038 --#define LTQ_CGU_FMR 0x003C -- --#define CGU_PLL0_PHASE_DIVIDER_ENABLE \ -- (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31)) --#define CGU_PLL0_BYPASS \ -- (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30)) --#define CGU_PLL0_CFG_DSMSEL \ -- (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28)) --#define CGU_PLL0_CFG_FRAC_EN \ -- (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27)) --#define CGU_PLL1_SRC \ -- (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31)) --#define CGU_PLL2_PHASE_DIVIDER_ENABLE \ -- (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20)) --#define CGU_SYS_FPI_SEL (1 << 6) --#define CGU_SYS_DDR_SEL 0x3 --#define CGU_PLL0_SRC (1 << 29) -- --#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17) --#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6) --#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2) --#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17) --#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13) -- --static unsigned int ltq_get_pll0_fdiv(void); -- --static inline unsigned int get_input_clock(int pll) --{ -- switch (pll) { -- case 0: -- if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC) -- return BASIS_REQUENCY_USB; -- else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) -- return BASIC_FREQUENCY_1; -- else -- return BASIC_FREQUENCY_2; -- case 1: -- if (CGU_PLL1_SRC) -- return BASIS_REQUENCY_USB; -- else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) -- return BASIC_FREQUENCY_1; -- else -- return BASIC_FREQUENCY_2; -- case 2: -- switch (CGU_PLL2_SRC) { -- case 0: -- return ltq_get_pll0_fdiv(); -- case 1: -- return CGU_PLL2_PHASE_DIVIDER_ENABLE ? -- BASIC_FREQUENCY_1 : -- BASIC_FREQUENCY_2; -- case 2: -- return BASIS_REQUENCY_USB; -- } -- default: -- return 0; -- } --} -- --static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den) --{ -- u64 res, clock = get_input_clock(pll); -- -- res = num * clock; -- do_div(res, den); -- return res; --} -- --static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N, -- unsigned int K) --{ -- unsigned int num = ((N + 1) << 10) + K; -- unsigned int den = (M + 1) << 10; -- -- return cal_dsm(pll, num, den); --} -- --static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N, -- unsigned int K) --{ -- unsigned int num = ((N + 1) << 11) + K + 512; -- unsigned int den = (M + 1) << 11; -- -- return cal_dsm(pll, num, den); --} -- --static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N, -- unsigned int K) --{ -- unsigned int num = K >= 512 ? -- ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584; -- unsigned int den = (M + 1) << 12; -- -- return cal_dsm(pll, num, den); --} -- --static inline unsigned int dsm(int pll, unsigned int M, unsigned int N, -- unsigned int K, unsigned int dsmsel, unsigned int phase_div_en) --{ -- if (!dsmsel) -- return mash_dsm(pll, M, N, K); -- else if (!phase_div_en) -- return mash_dsm(pll, M, N, K); -- else -- return ssff_dsm_2(pll, M, N, K); --} -- --static inline unsigned int ltq_get_pll0_fosc(void) --{ -- if (CGU_PLL0_BYPASS) -- return get_input_clock(0); -- else -- return !CGU_PLL0_CFG_FRAC_EN -- ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, -- CGU_PLL0_CFG_DSMSEL, -- CGU_PLL0_PHASE_DIVIDER_ENABLE) -- : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, -- CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL, -- CGU_PLL0_PHASE_DIVIDER_ENABLE); --} -- --static unsigned int ltq_get_pll0_fdiv(void) --{ -- unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1; -- -- return (ltq_get_pll0_fosc() + (div >> 1)) / div; --} -- --unsigned int ltq_get_io_region_clock(void) --{ -- unsigned int ret = ltq_get_pll0_fosc(); -- -- switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) { -- default: -- case 0: -- return (ret + 1) / 2; -- case 1: -- return (ret * 2 + 2) / 5; -- case 2: -- return (ret + 1) / 3; -- case 3: -- return (ret + 2) / 4; -- } --} --EXPORT_SYMBOL(ltq_get_io_region_clock); -- --unsigned int ltq_get_fpi_bus_clock(int fpi) --{ -- unsigned int ret = ltq_get_io_region_clock(); -- -- if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL)) -- ret >>= 1; -- return ret; --} --EXPORT_SYMBOL(ltq_get_fpi_bus_clock); -- --unsigned int ltq_get_cpu_hz(void) --{ -- switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) { -- case 0: -- return CLOCK_333M; -- case 4: -- return DDR_HZ; -- case 8: -- return DDR_HZ << 1; -- default: -- return DDR_HZ >> 1; -- } --} --EXPORT_SYMBOL(ltq_get_cpu_hz); -- --unsigned int ltq_get_fpi_hz(void) --{ -- unsigned int ddr_clock = DDR_HZ; -- -- if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40) -- return ddr_clock >> 1; -- return ddr_clock; --} --EXPORT_SYMBOL(ltq_get_fpi_hz); ---- /dev/null -+++ b/arch/mips/lantiq/xway/clk.c -@@ -0,0 +1,227 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2010 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include -+ -+#include "../clk.h" -+ -+static unsigned int ltq_ram_clocks[] = { -+ CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M }; -+#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3] -+ -+#define BASIC_FREQUENCY_1 35328000 -+#define BASIC_FREQUENCY_2 36000000 -+#define BASIS_REQUENCY_USB 12000000 -+ -+#define GET_BITS(x, msb, lsb) \ -+ (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) -+ -+/* legacy xway clock */ -+#define LTQ_CGU_PLL0_CFG 0x0004 -+#define LTQ_CGU_PLL1_CFG 0x0008 -+#define LTQ_CGU_PLL2_CFG 0x000C -+#define LTQ_CGU_SYS 0x0010 -+#define LTQ_CGU_UPDATE 0x0014 -+#define LTQ_CGU_IF_CLK 0x0018 -+#define LTQ_CGU_OSC_CON 0x001C -+#define LTQ_CGU_SMD 0x0020 -+#define LTQ_CGU_CT1SR 0x0028 -+#define LTQ_CGU_CT2SR 0x002C -+#define LTQ_CGU_PCMCR 0x0030 -+#define LTQ_CGU_PCI_CR 0x0034 -+#define LTQ_CGU_PD_PC 0x0038 -+#define LTQ_CGU_FMR 0x003C -+ -+#define CGU_PLL0_PHASE_DIVIDER_ENABLE \ -+ (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31)) -+#define CGU_PLL0_BYPASS \ -+ (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30)) -+#define CGU_PLL0_CFG_DSMSEL \ -+ (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28)) -+#define CGU_PLL0_CFG_FRAC_EN \ -+ (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27)) -+#define CGU_PLL1_SRC \ -+ (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31)) -+#define CGU_PLL2_PHASE_DIVIDER_ENABLE \ -+ (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20)) -+#define CGU_SYS_FPI_SEL (1 << 6) -+#define CGU_SYS_DDR_SEL 0x3 -+#define CGU_PLL0_SRC (1 << 29) -+ -+#define CGU_PLL0_CFG_PLLK GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17) -+#define CGU_PLL0_CFG_PLLN GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6) -+#define CGU_PLL0_CFG_PLLM GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2) -+#define CGU_PLL2_SRC GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17) -+#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13) -+ -+/* vr9 clock */ -+#define LTQ_CGU_SYS_VR9 0x0c -+#define LTQ_CGU_IF_CLK_VR9 0x24 -+ -+ -+static unsigned int ltq_get_pll0_fdiv(void); -+ -+static inline unsigned int get_input_clock(int pll) -+{ -+ switch (pll) { -+ case 0: -+ if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC) -+ return BASIS_REQUENCY_USB; -+ else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) -+ return BASIC_FREQUENCY_1; -+ else -+ return BASIC_FREQUENCY_2; -+ case 1: -+ if (CGU_PLL1_SRC) -+ return BASIS_REQUENCY_USB; -+ else if (CGU_PLL0_PHASE_DIVIDER_ENABLE) -+ return BASIC_FREQUENCY_1; -+ else -+ return BASIC_FREQUENCY_2; -+ case 2: -+ switch (CGU_PLL2_SRC) { -+ case 0: -+ return ltq_get_pll0_fdiv(); -+ case 1: -+ return CGU_PLL2_PHASE_DIVIDER_ENABLE ? -+ BASIC_FREQUENCY_1 : -+ BASIC_FREQUENCY_2; -+ case 2: -+ return BASIS_REQUENCY_USB; -+ } -+ default: -+ return 0; -+ } -+} -+ -+static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den) -+{ -+ u64 res, clock = get_input_clock(pll); -+ -+ res = num * clock; -+ do_div(res, den); -+ return res; -+} -+ -+static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N, -+ unsigned int K) -+{ -+ unsigned int num = ((N + 1) << 10) + K; -+ unsigned int den = (M + 1) << 10; -+ -+ return cal_dsm(pll, num, den); -+} -+ -+static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N, -+ unsigned int K) -+{ -+ unsigned int num = ((N + 1) << 11) + K + 512; -+ unsigned int den = (M + 1) << 11; -+ -+ return cal_dsm(pll, num, den); -+} -+ -+static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N, -+ unsigned int K) -+{ -+ unsigned int num = K >= 512 ? -+ ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584; -+ unsigned int den = (M + 1) << 12; -+ -+ return cal_dsm(pll, num, den); -+} -+ -+static inline unsigned int dsm(int pll, unsigned int M, unsigned int N, -+ unsigned int K, unsigned int dsmsel, unsigned int phase_div_en) -+{ -+ if (!dsmsel) -+ return mash_dsm(pll, M, N, K); -+ else if (!phase_div_en) -+ return mash_dsm(pll, M, N, K); -+ else -+ return ssff_dsm_2(pll, M, N, K); -+} -+ -+static inline unsigned int ltq_get_pll0_fosc(void) -+{ -+ if (CGU_PLL0_BYPASS) -+ return get_input_clock(0); -+ else -+ return !CGU_PLL0_CFG_FRAC_EN -+ ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, -+ CGU_PLL0_CFG_DSMSEL, -+ CGU_PLL0_PHASE_DIVIDER_ENABLE) -+ : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, -+ CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL, -+ CGU_PLL0_PHASE_DIVIDER_ENABLE); -+} -+ -+static unsigned int ltq_get_pll0_fdiv(void) -+{ -+ unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1; -+ -+ return (ltq_get_pll0_fosc() + (div >> 1)) / div; -+} -+ -+unsigned long ltq_danube_io_region_clock(void) -+{ -+ unsigned int ret = ltq_get_pll0_fosc(); -+ -+ switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) { -+ default: -+ case 0: -+ return (ret + 1) / 2; -+ case 1: -+ return (ret * 2 + 2) / 5; -+ case 2: -+ return (ret + 1) / 3; -+ case 3: -+ return (ret + 2) / 4; -+ } -+} -+ -+unsigned long ltq_danube_fpi_bus_clock(int fpi) -+{ -+ unsigned long ret = ltq_danube_io_region_clock(); -+ -+ if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL)) -+ ret >>= 1; -+ return ret; -+} -+ -+unsigned long ltq_danube_cpu_hz(void) -+{ -+ switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) { -+ case 0: -+ return CLOCK_333M; -+ case 4: -+ return DDR_HZ; -+ case 8: -+ return DDR_HZ << 1; -+ default: -+ return DDR_HZ >> 1; -+ } -+} -+ -+unsigned long ltq_danube_fpi_hz(void) -+{ -+ unsigned long ddr_clock = DDR_HZ; -+ -+ if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40) -+ return ddr_clock >> 1; -+ return ddr_clock; -+} ---- a/arch/mips/lantiq/xway/sysctrl.c -+++ b/arch/mips/lantiq/xway/sysctrl.c -@@ -8,17 +8,48 @@ - - #include - #include -+#include - - #include - -+#include "../clk.h" - #include "../devices.h" - - /* clock control register */ - #define LTQ_CGU_IFCCR 0x0018 -+/* system clock register */ -+#define LTQ_CGU_SYS 0x0010 - - /* the enable / disable registers */ - #define LTQ_PMU_PWDCR 0x1C - #define LTQ_PMU_PWDSR 0x20 -+#define LTQ_PMU_PWDCR1 0x24 -+#define LTQ_PMU_PWDSR1 0x28 -+ -+#define PWDCR(x) ((x) ? (LTQ_PMU_PWDCR1) : (LTQ_PMU_PWDCR)) -+#define PWDSR(x) ((x) ? (LTQ_PMU_PWDSR1) : (LTQ_PMU_PWDSR)) -+ -+/* CGU - clock generation unit */ -+#define CGU_EPHY 0x10 -+ -+/* PMU - power management unit */ -+#define PMU_DMA 0x0020 -+#define PMU_SPI 0x0100 -+#define PMU_EPHY 0x0080 -+#define PMU_USB 0x8041 -+#define PMU_STP 0x0800 -+#define PMU_GPT 0x1000 -+#define PMU_PPE 0x2000 -+#define PMU_FPI 0x4000 -+#define PMU_SWITCH 0x10000000 -+#define PMU_AHBS 0x2000 -+#define PMU_AHBM 0x8000 -+#define PMU_PCIE_CLK 0x80000000 -+ -+#define PMU1_PCIE_PHY 0x0001 -+#define PMU1_PCIE_CTL 0x0002 -+#define PMU1_PCIE_MSI 0x0020 -+#define PMU1_PCIE_PDI 0x0010 - - #define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y)) - #define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x)) -@@ -36,28 +67,64 @@ void __iomem *ltq_cgu_membase; - void __iomem *ltq_ebu_membase; - static void __iomem *ltq_pmu_membase; - --void ltq_cgu_enable(unsigned int clk) -+static int ltq_cgu_enable(struct clk *clk) -+{ -+ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk->bits, LTQ_CGU_IFCCR); -+ return 0; -+} -+ -+static void ltq_cgu_disable(struct clk *clk) - { -- ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk, LTQ_CGU_IFCCR); -+ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~clk->bits, LTQ_CGU_IFCCR); - } - --void ltq_pmu_enable(unsigned int module) -+static int ltq_pmu_enable(struct clk *clk) - { - int err = 1000000; - -- ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR); -- do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module)); -+ ltq_pmu_w32(ltq_pmu_r32(PWDCR(clk->module)) & ~clk->bits, -+ PWDCR(clk->module)); -+ do {} while (--err && (ltq_pmu_r32(PWDSR(clk->module)) & clk->bits)); - - if (!err) - panic("activating PMU module failed!\n"); -+ -+ return 0; -+} -+ -+static void ltq_pmu_disable(struct clk *clk) -+{ -+ ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | clk->bits, LTQ_PMU_PWDCR); -+} -+ -+static inline void clkdev_add_pmu(const char *dev, const char *con, -+ unsigned int module, unsigned int bits) -+{ -+ struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); -+ -+ clk->cl.dev_id = dev; -+ clk->cl.con_id = con; -+ clk->cl.clk = clk; -+ clk->enable = ltq_pmu_enable; -+ clk->disable = ltq_pmu_disable; -+ clk->module = module; -+ clk->bits = bits; -+ clkdev_add(&clk->cl); - } --EXPORT_SYMBOL(ltq_pmu_enable); - --void ltq_pmu_disable(unsigned int module) -+static inline void clkdev_add_cgu(const char *dev, const char *con, -+ unsigned int bits) - { -- ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR); -+ struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); -+ -+ clk->cl.dev_id = dev; -+ clk->cl.con_id = con; -+ clk->cl.clk = clk; -+ clk->enable = ltq_cgu_enable; -+ clk->disable = ltq_cgu_disable; -+ clk->bits = bits; -+ clkdev_add(&clk->cl); - } --EXPORT_SYMBOL(ltq_pmu_disable); - - void __init ltq_soc_init(void) - { -@@ -75,4 +142,23 @@ void __init ltq_soc_init(void) - - /* make sure to unprotect the memory region where flash is located */ - ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); -+ -+ /* add our clocks */ -+ clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA); -+ clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP); -+ clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI); -+ clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE); -+ if (ltq_is_ase()) { -+ if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5)) -+ clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M); -+ else -+ clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M); -+ clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY), -+ clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY); -+ } else { -+ clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(), -+ ltq_danube_io_region_clock()); -+ if (ltq_is_ar9()) -+ clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH); -+ } - } diff --git a/target/linux/lantiq/patches-3.3/204-owrt-dm9000-polling.patch b/target/linux/lantiq/patches-3.3/0022-owrt-dm9000-polling.patch similarity index 80% rename from target/linux/lantiq/patches-3.3/204-owrt-dm9000-polling.patch rename to target/linux/lantiq/patches-3.3/0022-owrt-dm9000-polling.patch index 7e898b810d..3adb8c6d4e 100644 --- a/target/linux/lantiq/patches-3.3/204-owrt-dm9000-polling.patch +++ b/target/linux/lantiq/patches-3.3/0022-owrt-dm9000-polling.patch @@ -1,3 +1,14 @@ +From 3c7089199784e3d53054869108cfa5666b42e7ea Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 10:28:51 +0200 +Subject: [PATCH 22/25] owrt dm9000 polling + +--- + drivers/net/ethernet/davicom/dm9000.c | 50 +++++++++++++++++++++++++++----- + 1 files changed, 42 insertions(+), 8 deletions(-) + +diff --git a/drivers/net/ethernet/davicom/dm9000.c b/drivers/net/ethernet/davicom/dm9000.c +index f801754..258a0c3 100644 --- a/drivers/net/ethernet/davicom/dm9000.c +++ b/drivers/net/ethernet/davicom/dm9000.c @@ -19,6 +19,7 @@ @@ -17,7 +28,7 @@ spinlock_t lock; struct mii_if_info mii; -@@ -845,6 +848,8 @@ static void dm9000_timeout(struct net_de +@@ -845,6 +848,8 @@ static void dm9000_timeout(struct net_device *dev) netif_stop_queue(dev); dm9000_reset(db); dm9000_init_dm9000(dev); @@ -26,7 +37,7 @@ /* We can accept TX packets again */ dev->trans_start = jiffies; /* prevent tx timeout */ netif_wake_queue(dev); -@@ -916,6 +921,12 @@ dm9000_start_xmit(struct sk_buff *skb, s +@@ -916,6 +921,12 @@ dm9000_start_xmit(struct sk_buff *skb, struct net_device *dev) /* free this SKB */ dev_kfree_skb(skb); @@ -39,7 +50,7 @@ return NETDEV_TX_OK; } -@@ -1157,6 +1168,18 @@ static void dm9000_poll_controller(struc +@@ -1157,6 +1168,18 @@ static void dm9000_poll_controller(struct net_device *dev) } #endif @@ -107,7 +118,7 @@ dm9000_schedule_poll(db); return 0; -@@ -1392,6 +1425,7 @@ dm9000_probe(struct platform_device *pde +@@ -1392,6 +1425,7 @@ dm9000_probe(struct platform_device *pdev) mutex_init(&db->addr_lock); INIT_DELAYED_WORK(&db->phy_poll, dm9000_poll_work); @@ -115,3 +126,6 @@ db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0023-MIPS-lantiq-convert-falcon-to-clkdev-api.patch b/target/linux/lantiq/patches-3.3/0023-MIPS-lantiq-convert-falcon-to-clkdev-api.patch deleted file mode 100644 index ddf07c4bba..0000000000 --- a/target/linux/lantiq/patches-3.3/0023-MIPS-lantiq-convert-falcon-to-clkdev-api.patch +++ /dev/null @@ -1,235 +0,0 @@ -From c87a0c58116b2b2d8ccee9bb64df652b563307c4 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 8 Mar 2012 11:19:11 +0100 -Subject: [PATCH 23/70] MIPS: lantiq: convert falcon to clkdev api - -Unify sysctrl/clock code and add clkdev hooks to sysctrl.c - -Signed-off-by: John Crispin ---- - .../include/asm/mach-lantiq/falcon/lantiq_soc.h | 8 +- - arch/mips/lantiq/falcon/Makefile | 2 +- - arch/mips/lantiq/falcon/sysctrl.c | 129 ++++++++++++-------- - 3 files changed, 80 insertions(+), 59 deletions(-) - ---- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h -@@ -95,6 +95,7 @@ - - /* Activation Status Register */ - #define ACTS_ASC1_ACT 0x00000800 -+#define ACTS_I2C_ACT 0x00004000 - #define ACTS_P0 0x00010000 - #define ACTS_P1 0x00010000 - #define ACTS_P2 0x00020000 -@@ -106,13 +107,6 @@ - #define ACTS_PADCTRL3 0x00200000 - #define ACTS_PADCTRL4 0x00400000 - --extern void ltq_sysctl_activate(int module, unsigned int mask); --extern void ltq_sysctl_deactivate(int module, unsigned int mask); --extern void ltq_sysctl_clken(int module, unsigned int mask); --extern void ltq_sysctl_clkdis(int module, unsigned int mask); --extern void ltq_sysctl_reboot(int module, unsigned int mask); --extern int ltq_gpe_is_activated(unsigned int mask); -- - /* global register ranges */ - extern __iomem void *ltq_ebu_membase; - extern __iomem void *ltq_sys1_membase; ---- a/arch/mips/lantiq/falcon/Makefile -+++ b/arch/mips/lantiq/falcon/Makefile -@@ -1,2 +1,2 @@ --obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o -+obj-y := prom.o reset.o sysctrl.o devices.o gpio.o - obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o ---- a/arch/mips/lantiq/falcon/sysctrl.c -+++ b/arch/mips/lantiq/falcon/sysctrl.c -@@ -9,11 +9,13 @@ - - #include - #include -+#include - #include - - #include - - #include "devices.h" -+#include "../clk.h" - - /* infrastructure control register */ - #define SYS1_INFRAC 0x00bc -@@ -38,6 +40,10 @@ - #define LTQ_SYSCTL_DEACT 0x0028 - /* reboot Register */ - #define LTQ_SYSCTL_RBT 0x002c -+/* CPU0 Clock Control Register */ -+#define LTQ_SYS1_CPU0CC 0x0040 -+/* clock divider bit */ -+#define LTQ_CPU0CC_CPUDIV 0x0001 - - static struct resource ltq_sysctl_res[] = { - MEM_RES("sys1", LTQ_SYS1_BASE_ADDR, LTQ_SYS1_SIZE), -@@ -64,79 +70,67 @@ void __iomem *ltq_ebu_membase; - #define ltq_status_r32(x) ltq_r32(ltq_status_membase + (x)) - - static inline void --ltq_sysctl_wait(int module, unsigned int mask, -+ltq_sysctl_wait(struct clk *clk, - unsigned int test, unsigned int reg) - { - int err = 1000000; - -- do {} while (--err && ((ltq_reg_r32(module, reg) -- & mask) != test)); -+ do {} while (--err && ((ltq_reg_r32(clk->module, reg) -+ & clk->bits) != test)); - if (!err) -- pr_err("module de/activation failed %d %08X %08X\n", -- module, mask, test); -+ pr_err("module de/activation failed %d %08X %08X %08X\n", -+ clk->module, clk->bits, test, -+ ltq_reg_r32(clk->module, reg) & clk->bits); - } - --void --ltq_sysctl_activate(int module, unsigned int mask) --{ -- if (module > SYSCTL_SYSGPE) -- return; -- -- ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN); -- ltq_reg_w32(module, mask, LTQ_SYSCTL_ACT); -- ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS); -+static int -+ltq_sysctl_activate(struct clk *clk) -+{ -+ ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKEN); -+ ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_ACT); -+ ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_ACTS); -+ return 0; - } --EXPORT_SYMBOL(ltq_sysctl_activate); - --void --ltq_sysctl_deactivate(int module, unsigned int mask) -+static void -+ltq_sysctl_deactivate(struct clk *clk) - { -- if (module > SYSCTL_SYSGPE) -- return; -- -- ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR); -- ltq_reg_w32(module, mask, LTQ_SYSCTL_DEACT); -- ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_ACTS); -+ ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKCLR); -+ ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_DEACT); -+ ltq_sysctl_wait(clk, 0, LTQ_SYSCTL_ACTS); - } --EXPORT_SYMBOL(ltq_sysctl_deactivate); - --void --ltq_sysctl_clken(int module, unsigned int mask) -+static int -+ltq_sysctl_clken(struct clk *clk) - { -- if (module > SYSCTL_SYSGPE) -- return; -- -- ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN); -- ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_CLKS); -+ ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKEN); -+ ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_CLKS); -+ return 0; - } --EXPORT_SYMBOL(ltq_sysctl_clken); - --void --ltq_sysctl_clkdis(int module, unsigned int mask) -+static void -+ltq_sysctl_clkdis(struct clk *clk) - { -- if (module > SYSCTL_SYSGPE) -- return; -- -- ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR); -- ltq_sysctl_wait(module, mask, 0, LTQ_SYSCTL_CLKS); -+ ltq_reg_w32(clk->module, clk->bits, LTQ_SYSCTL_CLKCLR); -+ ltq_sysctl_wait(clk, 0, LTQ_SYSCTL_CLKS); - } --EXPORT_SYMBOL(ltq_sysctl_clkdis); - --void --ltq_sysctl_reboot(int module, unsigned int mask) -+static void -+ltq_sysctl_reboot(struct clk *clk) - { - unsigned int act; -+ unsigned int bits; - -- if (module > SYSCTL_SYSGPE) -- return; -- -- act = ltq_reg_r32(module, LTQ_SYSCTL_ACT); -- if ((~act & mask) != 0) -- ltq_sysctl_activate(module, ~act & mask); -- ltq_reg_w32(module, act & mask, LTQ_SYSCTL_RBT); -- ltq_sysctl_wait(module, mask, mask, LTQ_SYSCTL_ACTS); -+ act = ltq_reg_r32(clk->module, LTQ_SYSCTL_ACT); -+ bits = ~act & clk->bits; -+ if (bits != 0) { -+ ltq_reg_w32(clk->module, bits, LTQ_SYSCTL_CLKEN); -+ ltq_reg_w32(clk->module, bits, LTQ_SYSCTL_ACT); -+ ltq_sysctl_wait(clk, bits, LTQ_SYSCTL_ACTS); -+ } -+ ltq_reg_w32(clk->module, act & clk->bits, LTQ_SYSCTL_RBT); -+ ltq_sysctl_wait(clk, clk->bits, LTQ_SYSCTL_ACTS); - } --EXPORT_SYMBOL(ltq_sysctl_reboot); - - /* enable the ONU core */ - static void -@@ -167,6 +161,24 @@ ltq_gpe_enable(void) - udelay(1); - } - -+static inline void -+clkdev_add_sys(const char *dev, unsigned int module, -+ unsigned int bits) -+{ -+ struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); -+ -+ clk->cl.dev_id = dev; -+ clk->cl.con_id = NULL; -+ clk->cl.clk = clk; -+ clk->module = module; -+ clk->activate = ltq_sysctl_activate; -+ clk->deactivate = ltq_sysctl_deactivate; -+ clk->enable = ltq_sysctl_clken; -+ clk->disable = ltq_sysctl_clkdis; -+ clk->reboot = ltq_sysctl_reboot; -+ clkdev_add(&clk->cl); -+} -+ - void __init - ltq_soc_init(void) - { -@@ -180,4 +192,19 @@ ltq_soc_init(void) - ltq_ebu_membase = ltq_remap_resource(<q_ebu_res); - - ltq_gpe_enable(); -+ -+ /* get our 3 static rates for cpu, fpi and io clocks */ -+ if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV) -+ clkdev_add_static(CLOCK_200M, CLOCK_100M, CLOCK_200M); -+ else -+ clkdev_add_static(CLOCK_400M, CLOCK_100M, CLOCK_200M); -+ -+ /* add our clock domains */ -+ clkdev_add_sys("falcon_gpio.0", SYSCTL_SYSETH, ACTS_PADCTRL0 | ACTS_P0); -+ clkdev_add_sys("falcon_gpio.1", SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1); -+ clkdev_add_sys("falcon_gpio.2", SYSCTL_SYSETH, ACTS_PADCTRL2 | ACTS_P2); -+ clkdev_add_sys("falcon_gpio.3", SYSCTL_SYS1, ACTS_PADCTRL3 | ACTS_P3); -+ clkdev_add_sys("falcon_gpio.4", SYSCTL_SYS1, ACTS_PADCTRL4 | ACTS_P4); -+ clkdev_add_sys("ltq_asc.1", SYSCTL_SYS1, ACTS_ASC1_ACT); -+ clkdev_add_sys("falcon_i2c", SYSCTL_SYS1, ACTS_I2C_ACT); - } diff --git a/target/linux/lantiq/patches-3.3/205-owrt-gpio-export.patch b/target/linux/lantiq/patches-3.3/0023-owrt-gpio-export.patch similarity index 69% rename from target/linux/lantiq/patches-3.3/205-owrt-gpio-export.patch rename to target/linux/lantiq/patches-3.3/0023-owrt-gpio-export.patch index df4928463c..234058f933 100644 --- a/target/linux/lantiq/patches-3.3/205-owrt-gpio-export.patch +++ b/target/linux/lantiq/patches-3.3/0023-owrt-gpio-export.patch @@ -1,3 +1,14 @@ +From 2489fa75bfd3bd196b862b497c41744aca34f851 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 10:29:10 +0200 +Subject: [PATCH 23/25] owrt gpio export + +--- + drivers/gpio/gpiolib.c | 17 ++++++++--------- + 1 files changed, 8 insertions(+), 9 deletions(-) + +diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c +index 17fdf4b..7b8d336 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c @@ -64,9 +64,9 @@ struct gpio_desc { @@ -24,7 +35,7 @@ } /* Warn when drivers omit gpio_request() calls -- legal but ill-advised -@@ -727,7 +727,6 @@ int gpio_export(unsigned gpio, bool dire +@@ -727,7 +727,6 @@ int gpio_export(unsigned gpio, bool direction_may_change) if (desc->chip->names && desc->chip->names[gpio - desc->chip->base]) ioname = desc->chip->names[gpio - desc->chip->base]; @@ -32,7 +43,7 @@ if (status == 0) { struct device *dev; -@@ -1351,11 +1350,11 @@ const char *gpiochip_is_requested(struct +@@ -1351,11 +1350,11 @@ const char *gpiochip_is_requested(struct gpio_chip *chip, unsigned offset) return NULL; if (test_bit(FLAG_REQUESTED, &gpio_desc[gpio].flags) == 0) return NULL; @@ -48,3 +59,6 @@ } EXPORT_SYMBOL_GPL(gpiochip_is_requested); +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0024-MIPS-lantiq-convert-dma-driver-to-clkdev-api.patch b/target/linux/lantiq/patches-3.3/0024-MIPS-lantiq-convert-dma-driver-to-clkdev-api.patch deleted file mode 100644 index 01ced689db..0000000000 --- a/target/linux/lantiq/patches-3.3/0024-MIPS-lantiq-convert-dma-driver-to-clkdev-api.patch +++ /dev/null @@ -1,57 +0,0 @@ -From d5904c1dd985d1e0944dd249927ad19c8522a943 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 8 Mar 2012 11:21:08 +0100 -Subject: [PATCH 24/70] MIPS: lantiq: convert dma driver to clkdev api - -Update from old pmu_{dis,en}able() to ckldev api. - -Signed-off-by: John Crispin ---- - arch/mips/lantiq/xway/Makefile.rej | 11 +++++++++++ - arch/mips/lantiq/xway/dma.c | 6 +++++- - 2 files changed, 16 insertions(+), 1 deletions(-) - create mode 100644 arch/mips/lantiq/xway/Makefile.rej - ---- /dev/null -+++ b/arch/mips/lantiq/xway/Makefile.rej -@@ -0,0 +1,11 @@ -+--- arch/mips/lantiq/xway/Makefile -++++ arch/mips/lantiq/xway/Makefile -+@@ -1,7 +1,4 @@ -+-obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o -+- -+-obj-$(CONFIG_SOC_XWAY) += prom-xway.o -+-obj-$(CONFIG_SOC_AMAZON_SE) += prom-ase.o -++obj-y := prom.o sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o -+ -+ obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o -+ obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o ---- a/arch/mips/lantiq/xway/dma.c -+++ b/arch/mips/lantiq/xway/dma.c -@@ -20,6 +20,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -216,6 +217,7 @@ EXPORT_SYMBOL_GPL(ltq_dma_init_port); - int __init - ltq_dma_init(void) - { -+ struct clk *clk; - int i; - - /* remap dma register range */ -@@ -224,7 +226,9 @@ ltq_dma_init(void) - panic("Failed to remap dma memory"); - - /* power up and reset the dma engine */ -- ltq_pmu_enable(PMU_DMA); -+ clk = clk_get_sys("ltq_dma", NULL); -+ WARN_ON(!clk); -+ clk_enable(clk); - ltq_dma_w32_mask(0, DMA_RESET, LTQ_DMA_CTRL); - - /* disable all interrupts */ diff --git a/target/linux/lantiq/patches-3.3/209-fritz_ram.patch b/target/linux/lantiq/patches-3.3/0024-fritzbox-ram.patch similarity index 55% rename from target/linux/lantiq/patches-3.3/209-fritz_ram.patch rename to target/linux/lantiq/patches-3.3/0024-fritzbox-ram.patch index 32aae6ea08..a63112dfe7 100644 --- a/target/linux/lantiq/patches-3.3/209-fritz_ram.patch +++ b/target/linux/lantiq/patches-3.3/0024-fritzbox-ram.patch @@ -1,3 +1,14 @@ +From 6824bc23dfaf2ff75cc6c6e9281e12ceb45fe1b3 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 10:30:01 +0200 +Subject: [PATCH 24/25] fritzbox ram + +--- + arch/mips/lantiq/setup.c | 6 ++++++ + 1 files changed, 6 insertions(+), 0 deletions(-) + +diff --git a/arch/mips/lantiq/setup.c b/arch/mips/lantiq/setup.c +index 708e969..114989d 100644 --- a/arch/mips/lantiq/setup.c +++ b/arch/mips/lantiq/setup.c @@ -40,6 +40,12 @@ void __init plat_mem_setup(void) @@ -13,3 +24,6 @@ } if (!strncmp(e, "BRN-BOOT", 8)){ pr_info("Found BRN-BOOT instead of u-boot\n"); +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0025-MIPS-lantiq-convert-gpio_stp-driver-to-clkdev-api.patch b/target/linux/lantiq/patches-3.3/0025-MIPS-lantiq-convert-gpio_stp-driver-to-clkdev-api.patch deleted file mode 100644 index 1f63f72a87..0000000000 --- a/target/linux/lantiq/patches-3.3/0025-MIPS-lantiq-convert-gpio_stp-driver-to-clkdev-api.patch +++ /dev/null @@ -1,55 +0,0 @@ -From b4c30090220ae84e03e35363fc2dc6cf3e4b00ed Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 8 Mar 2012 11:21:33 +0100 -Subject: [PATCH 25/70] MIPS: lantiq: convert gpio_stp driver to clkdev api - -Update from old pmu_{dis,en}able() to ckldev api. - -Signed-off-by: John Crispin ---- - arch/mips/lantiq/xway/gpio_stp.c | 12 +++++++++--- - 1 files changed, 9 insertions(+), 3 deletions(-) - ---- a/arch/mips/lantiq/xway/gpio_stp.c -+++ b/arch/mips/lantiq/xway/gpio_stp.c -@@ -15,6 +15,8 @@ - #include - #include - #include -+#include -+#include - - #include - -@@ -78,8 +80,10 @@ static struct gpio_chip ltq_stp_chip = { - .owner = THIS_MODULE, - }; - --static int ltq_stp_hw_init(void) -+static int ltq_stp_hw_init(struct device *dev) - { -+ struct clk *clk; -+ - /* sane defaults */ - ltq_stp_w32(0, LTQ_STP_AR); - ltq_stp_w32(0, LTQ_STP_CPU0); -@@ -105,7 +109,9 @@ static int ltq_stp_hw_init(void) - */ - ltq_stp_w32_mask(0, LTQ_STP_ADSL_SRC, LTQ_STP_CON0); - -- ltq_pmu_enable(PMU_LED); -+ clk = clk_get(dev, NULL); -+ WARN_ON(IS_ERR(clk)); -+ clk_enable(clk); - return 0; - } - -@@ -138,7 +144,7 @@ static int __devinit ltq_stp_probe(struc - } - ret = gpiochip_add(<q_stp_chip); - if (!ret) -- ret = ltq_stp_hw_init(); -+ ret = ltq_stp_hw_init(&pdev->dev); - - return ret; - } diff --git a/target/linux/lantiq/patches-3.3/535-svip_cp1.patch b/target/linux/lantiq/patches-3.3/0025-svip-cp1.patch similarity index 57% rename from target/linux/lantiq/patches-3.3/535-svip_cp1.patch rename to target/linux/lantiq/patches-3.3/0025-svip-cp1.patch index 84b483b6f1..50f2221dfe 100644 --- a/target/linux/lantiq/patches-3.3/535-svip_cp1.patch +++ b/target/linux/lantiq/patches-3.3/0025-svip-cp1.patch @@ -1,8 +1,19 @@ -Index: linux-3.3.8/arch/mips/lantiq/devices.c -=================================================================== ---- linux-3.3.8.orig/arch/mips/lantiq/devices.c 2012-07-31 09:45:42.315551926 +0200 -+++ linux-3.3.8/arch/mips/lantiq/devices.c 2012-07-31 09:46:14.051553281 +0200 -@@ -102,19 +102,29 @@ +From fcecdbe52ca3f17c798a080454d67df92d1e71f8 Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 3 Aug 2012 10:30:28 +0200 +Subject: [PATCH 25/25] svip cp1 + +--- + arch/mips/lantiq/devices.c | 10 ++++++++++ + arch/mips/lantiq/prom.c | 1 + + arch/mips/lantiq/setup.c | 15 +++++++++++++++ + 3 files changed, 26 insertions(+), 0 deletions(-) + +diff --git a/arch/mips/lantiq/devices.c b/arch/mips/lantiq/devices.c +index 2d7c46a..7128115 100644 +--- a/arch/mips/lantiq/devices.c ++++ b/arch/mips/lantiq/devices.c +@@ -102,19 +102,29 @@ void __init ltq_register_pci(struct ltq_pci_data *data) } #endif @@ -32,11 +43,11 @@ Index: linux-3.3.8/arch/mips/lantiq/devices.c (void*)CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE, &dma, GFP_ATOMIC)); +#endif } -Index: linux-3.3.8/arch/mips/lantiq/prom.c -=================================================================== ---- linux-3.3.8.orig/arch/mips/lantiq/prom.c 2012-07-31 09:45:42.315551926 +0200 -+++ linux-3.3.8/arch/mips/lantiq/prom.c 2012-07-31 10:31:28.759669332 +0200 -@@ -129,6 +129,7 @@ +diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c +index 0fdef27..cab608b 100644 +--- a/arch/mips/lantiq/prom.c ++++ b/arch/mips/lantiq/prom.c +@@ -129,6 +129,7 @@ err_res: } EXPORT_SYMBOL(ltq_remap_resource); @@ -44,10 +55,10 @@ Index: linux-3.3.8/arch/mips/lantiq/prom.c void __init prom_init(void) { ltq_soc_detect(&soc_info); -Index: linux-3.3.8/arch/mips/lantiq/setup.c -=================================================================== ---- linux-3.3.8.orig/arch/mips/lantiq/setup.c 2012-07-31 09:45:42.315551926 +0200 -+++ linux-3.3.8/arch/mips/lantiq/setup.c 2012-07-31 10:31:35.215669606 +0200 +diff --git a/arch/mips/lantiq/setup.c b/arch/mips/lantiq/setup.c +index 114989d..9aa0310 100644 +--- a/arch/mips/lantiq/setup.c ++++ b/arch/mips/lantiq/setup.c @@ -21,8 +21,15 @@ /* set to 1 if the bootloader is BRN-BOOT instead of u-boot */ unsigned long ltq_brn_boot = 0; @@ -64,7 +75,7 @@ Index: linux-3.3.8/arch/mips/lantiq/setup.c /* assume 16M as default incase uboot fails to pass proper ramsize */ unsigned long memsize = 16; char **envp = (char **) KSEG1ADDR(fw_arg2); -@@ -54,6 +61,14 @@ +@@ -54,6 +61,14 @@ void __init plat_mem_setup(void) envp++; } memsize *= 1024 * 1024; @@ -79,3 +90,6 @@ Index: linux-3.3.8/arch/mips/lantiq/setup.c add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); } +-- +1.7.9.1 + diff --git a/target/linux/lantiq/patches-3.3/0026-MIPS-lantiq-convert-falcon-gpio-to-clkdev-api.patch b/target/linux/lantiq/patches-3.3/0026-MIPS-lantiq-convert-falcon-gpio-to-clkdev-api.patch deleted file mode 100644 index bcc25ded2e..0000000000 --- a/target/linux/lantiq/patches-3.3/0026-MIPS-lantiq-convert-falcon-gpio-to-clkdev-api.patch +++ /dev/null @@ -1,66 +0,0 @@ -From e5bb79e897a95b688a93087f04848a043782a6a7 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 8 Mar 2012 11:22:03 +0100 -Subject: [PATCH 26/70] MIPS: lantiq: convert falcon gpio to clkdev api - -The falcon gpio clocks used to be enabled when registering the platform device. -Move this code into the driver and use clkdev api. - -Signed-off-by: John Crispin ---- - arch/mips/lantiq/falcon/devices.c | 5 ----- - arch/mips/lantiq/falcon/gpio.c | 10 ++++++++++ - 2 files changed, 10 insertions(+), 5 deletions(-) - ---- a/arch/mips/lantiq/falcon/devices.c -+++ b/arch/mips/lantiq/falcon/devices.c -@@ -111,9 +111,6 @@ falcon_register_gpio(void) - falcon_gpio1_res, ARRAY_SIZE(falcon_gpio1_res)); - platform_device_register_simple("falcon_gpio", 2, - falcon_gpio2_res, ARRAY_SIZE(falcon_gpio2_res)); -- ltq_sysctl_activate(SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1); -- ltq_sysctl_activate(SYSCTL_SYSETH, ACTS_PADCTRL0 | -- ACTS_PADCTRL2 | ACTS_P0 | ACTS_P2); - } - - void __init -@@ -123,6 +120,4 @@ falcon_register_gpio_extra(void) - falcon_gpio3_res, ARRAY_SIZE(falcon_gpio3_res)); - platform_device_register_simple("falcon_gpio", 4, - falcon_gpio4_res, ARRAY_SIZE(falcon_gpio4_res)); -- ltq_sysctl_activate(SYSCTL_SYS1, -- ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4); - } ---- a/arch/mips/lantiq/falcon/gpio.c -+++ b/arch/mips/lantiq/falcon/gpio.c -@@ -11,6 +11,7 @@ - #include - #include - #include -+#include - #include - - #include -@@ -71,6 +72,7 @@ struct falcon_gpio_port { - void __iomem *port; - unsigned int irq_base; - unsigned int chained_irq; -+ struct clk *clk; - }; - - static struct falcon_gpio_port ltq_gpio_port[MAX_PORTS]; -@@ -332,6 +334,14 @@ falcon_gpio_probe(struct platform_device - goto err; - } - -+ gpio_port->clk = clk_get(&pdev->dev, NULL); -+ if (IS_ERR(gpio_port->clk)) { -+ dev_err(&pdev->dev, "Could not get clock\n"); -+ ret = PTR_ERR(gpio_port->clk);; -+ goto err; -+ } -+ clk_enable(gpio_port->clk); -+ - if (irq > 0) { - /* irq_chip support */ - gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq; diff --git a/target/linux/lantiq/patches-3.3/0027-SERIAL-MIPS-lantiq-convert-serial-driver-to-clkdev-a.patch b/target/linux/lantiq/patches-3.3/0027-SERIAL-MIPS-lantiq-convert-serial-driver-to-clkdev-a.patch deleted file mode 100644 index 10ec3019db..0000000000 --- a/target/linux/lantiq/patches-3.3/0027-SERIAL-MIPS-lantiq-convert-serial-driver-to-clkdev-a.patch +++ /dev/null @@ -1,36 +0,0 @@ -From ded396701b769f4bd3960c353d40488fa5922a85 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 16 Feb 2012 20:17:16 +0100 -Subject: [PATCH 27/70] SERIAL: MIPS: lantiq: convert serial driver to clkdev - api - -Reference the FPI clock via its new access function. - -Signed-off-by: John Crispin -Cc: linux-serial@vger.kernel.org ---- - drivers/tty/serial/lantiq.c | 6 +++++- - 1 files changed, 5 insertions(+), 1 deletions(-) - ---- a/drivers/tty/serial/lantiq.c -+++ b/drivers/tty/serial/lantiq.c -@@ -540,6 +540,10 @@ lqasc_request_port(struct uart_port *por - if (ltq_gpio_request(&pdev->dev, MUXC_SIF_TX_PIN, - 3, 1, "asc1-tx")) - return -EBUSY; -+ ltq_port->clk = clk_get(&pdev->dev, NULL); -+ if (IS_ERR(ltq_port->clk)) -+ return PTR_ERR(ltq_port->clk); -+ clk_enable(ltq_port->clk); - } - return 0; - } -@@ -698,7 +702,7 @@ lqasc_probe(struct platform_device *pdev - if (lqasc_port[pdev->id] != NULL) - return -EBUSY; - -- clk = clk_get(&pdev->dev, "fpi"); -+ clk = clk_get_fpi(); - if (IS_ERR(clk)) { - pr_err("failed to get fpi clk\n"); - return -ENOENT; diff --git a/target/linux/lantiq/patches-3.3/0028-MIPS-lantiq-convert-falcon-debug-uart-to-clkdev-api.patch b/target/linux/lantiq/patches-3.3/0028-MIPS-lantiq-convert-falcon-debug-uart-to-clkdev-api.patch deleted file mode 100644 index 6390e787ca..0000000000 --- a/target/linux/lantiq/patches-3.3/0028-MIPS-lantiq-convert-falcon-debug-uart-to-clkdev-api.patch +++ /dev/null @@ -1,66 +0,0 @@ -From 7ab075944587e4fe7e2688b1df85452e3d86edb5 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 21 Feb 2012 14:25:21 +0100 -Subject: [PATCH 28/70] MIPS: lantiq: convert falcon debug uart to clkdev api - -On Falcon SoCs we have a secondary serial port that can be used to help -debug the voice core. For the port to work several clocking bits need to -be activated. We convert the code to clkdev api. - -Signed-off-by: John Crispin ---- - arch/mips/lantiq/falcon/prom.c | 4 +--- - drivers/tty/serial/lantiq.c | 7 ++++--- - 2 files changed, 5 insertions(+), 6 deletions(-) - ---- a/arch/mips/lantiq/falcon/prom.c -+++ b/arch/mips/lantiq/falcon/prom.c -@@ -43,10 +43,8 @@ ltq_soc_setup(void) - ltq_register_asc(0); - ltq_register_wdt(); - falcon_register_gpio(); -- if (register_asc1) { -+ if (register_asc1) - ltq_register_asc(1); -- ltq_sysctl_activate(SYSCTL_SYS1, ACTS_ASC1_ACT); -- } - } - - void __init ---- a/drivers/tty/serial/lantiq.c -+++ b/drivers/tty/serial/lantiq.c -@@ -117,6 +117,7 @@ static DEFINE_SPINLOCK(ltq_asc_lock); - - struct ltq_uart_port { - struct uart_port port; -+ struct clk *fpiclk; - struct clk *clk; - unsigned int tx_irq; - unsigned int rx_irq; -@@ -319,7 +320,7 @@ lqasc_startup(struct uart_port *port) - struct ltq_uart_port *ltq_port = to_ltq_uart_port(port); - int retval; - -- port->uartclk = clk_get_rate(ltq_port->clk); -+ port->uartclk = clk_get_rate(ltq_port->fpiclk); - - ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET), - port->membase + LTQ_ASC_CLC); -@@ -646,7 +647,7 @@ lqasc_console_setup(struct console *co, - - port = <q_port->port; - -- port->uartclk = clk_get_rate(ltq_port->clk); -+ port->uartclk = clk_get_rate(ltq_port->fpiclk); - - if (options) - uart_parse_options(options, &baud, &parity, &bits, &flow); -@@ -731,7 +732,7 @@ lqasc_probe(struct platform_device *pdev - port->irq = tx_irq; /* unused, just to be backward-compatibe */ - port->mapbase = mmres->start; - -- ltq_port->clk = clk; -+ ltq_port->fpiclk = clk; - - ltq_port->tx_irq = tx_irq; - ltq_port->rx_irq = rx_irq; diff --git a/target/linux/lantiq/patches-3.3/0029-NET-MIPS-lantiq-convert-etop-driver-to-clkdev-api.patch b/target/linux/lantiq/patches-3.3/0029-NET-MIPS-lantiq-convert-etop-driver-to-clkdev-api.patch deleted file mode 100644 index b00fbe45e9..0000000000 --- a/target/linux/lantiq/patches-3.3/0029-NET-MIPS-lantiq-convert-etop-driver-to-clkdev-api.patch +++ /dev/null @@ -1,118 +0,0 @@ -From 118d9f0abd69278cfdd7c5bde4743c0cab9b7618 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 8 Mar 2012 11:23:00 +0100 -Subject: [PATCH 29/70] NET: MIPS: lantiq: convert etop driver to clkdev api - -Update from old pmu_{dis,en}able() to ckldev api. - -Signed-off-by: John Crispin -Cc: netdev@vger.kernel.org ---- - drivers/net/ethernet/lantiq_etop.c | 49 ++++++++++++++++++++++++++++++----- - 1 files changed, 42 insertions(+), 7 deletions(-) - ---- a/drivers/net/ethernet/lantiq_etop.c -+++ b/drivers/net/ethernet/lantiq_etop.c -@@ -36,6 +36,7 @@ - #include - #include - #include -+#include - - #include - -@@ -148,6 +149,11 @@ struct ltq_etop_priv { - int tx_free[MAX_DMA_CHAN >> 1]; - - spinlock_t lock; -+ -+ struct clk *clk_ppe; -+ struct clk *clk_switch; -+ struct clk *clk_ephy; -+ struct clk *clk_ephycgu; - }; - - static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, -@@ -281,16 +287,27 @@ ltq_etop_hw_exit(struct net_device *dev) - struct ltq_etop_priv *priv = netdev_priv(dev); - int i; - -- ltq_pmu_disable(PMU_PPE); -+ clk_disable(priv->clk_ppe); -+ -+ if (ltq_has_gbit()) -+ clk_disable(priv->clk_switch); -+ -+ if (ltq_is_ase()) { -+ clk_disable(priv->clk_ephy); -+ clk_disable(priv->clk_ephycgu); -+ } -+ - for (i = 0; i < MAX_DMA_CHAN; i++) - if (IS_TX(i) || IS_RX(i)) - ltq_etop_free_channel(dev, &priv->ch[i]); - } - - static void --ltq_etop_gbit_init(void) -+ltq_etop_gbit_init(struct net_device *dev) - { -- ltq_pmu_enable(PMU_SWITCH); -+ struct ltq_etop_priv *priv = netdev_priv(dev); -+ -+ clk_enable(priv->clk_switch); - - ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); - /** Disable MDIO auto polling mode */ -@@ -313,10 +330,10 @@ ltq_etop_hw_init(struct net_device *dev) - int err = 0; - int i; - -- ltq_pmu_enable(PMU_PPE); -+ clk_enable(priv->clk_ppe); - - if (ltq_has_gbit()) { -- ltq_etop_gbit_init(); -+ ltq_etop_gbit_init(dev); - /* force the etops link to the gbit to MII */ - mii_mode = PHY_INTERFACE_MODE_MII; - } -@@ -334,11 +351,11 @@ ltq_etop_hw_init(struct net_device *dev) - - default: - if (ltq_is_ase()) { -- ltq_pmu_enable(PMU_EPHY); -+ clk_enable(priv->clk_ephy); - /* disable external MII */ - ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG); - /* enable clock for internal PHY */ -- ltq_cgu_enable(CGU_EPHY); -+ clk_enable(priv->clk_ephycgu); - /* we need to write this magic to the internal phy to - make it work */ - ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020); -@@ -883,6 +900,24 @@ ltq_etop_probe(struct platform_device *p - priv->pdev = pdev; - priv->pldata = dev_get_platdata(&pdev->dev); - priv->netdev = dev; -+ -+ priv->clk_ppe = clk_get(&pdev->dev, NULL); -+ if (IS_ERR(priv->clk_ppe)) -+ return PTR_ERR(priv->clk_ppe); -+ if (ltq_has_gbit()) { -+ priv->clk_switch = clk_get(&pdev->dev, "switch"); -+ if (IS_ERR(priv->clk_switch)) -+ return PTR_ERR(priv->clk_switch); -+ } -+ if (ltq_is_ase()) { -+ priv->clk_ephy = clk_get(&pdev->dev, "ephy"); -+ if (IS_ERR(priv->clk_ephy)) -+ return PTR_ERR(priv->clk_ephy); -+ priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu"); -+ if (IS_ERR(priv->clk_ephycgu)) -+ return PTR_ERR(priv->clk_ephycgu); -+ } -+ - spin_lock_init(&priv->lock); - - for (i = 0; i < MAX_DMA_CHAN; i++) { diff --git a/target/linux/lantiq/patches-3.3/0030-WDT-MIPS-lantiq-convert-watchdog-driver-to-clkdev-ap.patch b/target/linux/lantiq/patches-3.3/0030-WDT-MIPS-lantiq-convert-watchdog-driver-to-clkdev-ap.patch deleted file mode 100644 index 88c4c72ec2..0000000000 --- a/target/linux/lantiq/patches-3.3/0030-WDT-MIPS-lantiq-convert-watchdog-driver-to-clkdev-ap.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 7971cef3f4036da74066aa4ca9b78fd1c9573a6c Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 16 Feb 2012 20:17:50 +0100 -Subject: [PATCH 30/70] WDT: MIPS: lantiq: convert watchdog driver to clkdev - api - -Refrence the IO region clock via its new access function. - -Signed-off-by: John Crispin -Cc: linux-watchdog@vger.kernel.org ---- - drivers/watchdog/lantiq_wdt.c | 2 +- - 1 files changed, 1 insertions(+), 1 deletions(-) - ---- a/drivers/watchdog/lantiq_wdt.c -+++ b/drivers/watchdog/lantiq_wdt.c -@@ -206,7 +206,7 @@ ltq_wdt_probe(struct platform_device *pd - } - - /* we do not need to enable the clock as it is always running */ -- clk = clk_get(&pdev->dev, "io"); -+ clk = clk_get_io(); - WARN_ON(!clk); - ltq_io_region_clk_rate = clk_get_rate(clk); - clk_put(clk); diff --git a/target/linux/lantiq/patches-3.3/0031-MIPS-lantiq-unify-xway-prom-code.patch b/target/linux/lantiq/patches-3.3/0031-MIPS-lantiq-unify-xway-prom-code.patch deleted file mode 100644 index 130c69474e..0000000000 --- a/target/linux/lantiq/patches-3.3/0031-MIPS-lantiq-unify-xway-prom-code.patch +++ /dev/null @@ -1,239 +0,0 @@ -From 707d76cc9dc4ddfcea280b91df83bd726407518a Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 8 Mar 2012 11:44:55 +0100 -Subject: [PATCH 31/70] MIPS: lantiq: unify xway prom code - -The xway prom-ase.c and prom-xway.c files are redundant. Unify the 2 files. - -Signed-off-by: John Crispin ---- - arch/mips/lantiq/xway/Makefile | 5 +-- - arch/mips/lantiq/xway/Makefile.rej | 11 ----- - arch/mips/lantiq/xway/prom-ase.c | 48 ---------------------- - arch/mips/lantiq/xway/prom-xway.c | 64 ----------------------------- - arch/mips/lantiq/xway/prom.c | 79 ++++++++++++++++++++++++++++++++++++ - 5 files changed, 80 insertions(+), 127 deletions(-) - delete mode 100644 arch/mips/lantiq/xway/Makefile.rej - delete mode 100644 arch/mips/lantiq/xway/prom-ase.c - delete mode 100644 arch/mips/lantiq/xway/prom-xway.c - create mode 100644 arch/mips/lantiq/xway/prom.c - -Index: linux-3.3.8/arch/mips/lantiq/xway/Makefile -=================================================================== ---- linux-3.3.8.orig/arch/mips/lantiq/xway/Makefile 2012-07-31 08:34:35.000000000 +0200 -+++ linux-3.3.8/arch/mips/lantiq/xway/Makefile 2012-07-31 08:52:14.155414782 +0200 -@@ -1,7 +1,4 @@ --obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o -- --obj-$(CONFIG_SOC_XWAY) += prom-xway.o --obj-$(CONFIG_SOC_AMAZON_SE) += prom-ase.o -+obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o - - obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o - obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o -Index: linux-3.3.8/arch/mips/lantiq/xway/prom-ase.c -=================================================================== ---- linux-3.3.8.orig/arch/mips/lantiq/xway/prom-ase.c 2012-07-31 08:34:34.000000000 +0200 -+++ /dev/null 1970-01-01 00:00:00.000000000 +0000 -@@ -1,48 +0,0 @@ --/* -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- * -- * Copyright (C) 2010 John Crispin -- */ -- --#include --#include --#include --#include -- --#include -- --#include "devices.h" --#include "../prom.h" -- --#define SOC_AMAZON_SE "Amazon_SE" -- --#define PART_SHIFT 12 --#define PART_MASK 0x0FFFFFFF --#define REV_SHIFT 28 --#define REV_MASK 0xF0000000 -- --void __init ltq_soc_detect(struct ltq_soc_info *i) --{ -- i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; -- i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; -- sprintf(i->rev_type, "1.%d", i->rev); -- switch (i->partnum) { -- case SOC_ID_AMAZON_SE: -- i->name = SOC_AMAZON_SE; -- i->type = SOC_TYPE_AMAZON_SE; -- break; -- -- default: -- unreachable(); -- break; -- } --} -- --void __init ltq_soc_setup(void) --{ -- ltq_register_ase_asc(); -- ltq_register_gpio(); -- ltq_register_wdt(); --} -Index: linux-3.3.8/arch/mips/lantiq/xway/prom-xway.c -=================================================================== ---- linux-3.3.8.orig/arch/mips/lantiq/xway/prom-xway.c 2012-07-31 08:34:34.000000000 +0200 -+++ /dev/null 1970-01-01 00:00:00.000000000 +0000 -@@ -1,64 +0,0 @@ --/* -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- * -- * Copyright (C) 2010 John Crispin -- */ -- --#include --#include --#include --#include -- --#include -- --#include "devices.h" --#include "../prom.h" -- --#define SOC_DANUBE "Danube" --#define SOC_TWINPASS "Twinpass" --#define SOC_AR9 "AR9" -- --#define PART_SHIFT 12 --#define PART_MASK 0x0FFFFFFF --#define REV_SHIFT 28 --#define REV_MASK 0xF0000000 -- --void __init ltq_soc_detect(struct ltq_soc_info *i) --{ -- i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; -- i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; -- sprintf(i->rev_type, "1.%d", i->rev); -- switch (i->partnum) { -- case SOC_ID_DANUBE1: -- case SOC_ID_DANUBE2: -- i->name = SOC_DANUBE; -- i->type = SOC_TYPE_DANUBE; -- break; -- -- case SOC_ID_TWINPASS: -- i->name = SOC_TWINPASS; -- i->type = SOC_TYPE_DANUBE; -- break; -- -- case SOC_ID_ARX188: -- case SOC_ID_ARX168: -- case SOC_ID_ARX182: -- i->name = SOC_AR9; -- i->type = SOC_TYPE_AR9; -- break; -- -- default: -- unreachable(); -- break; -- } --} -- --void __init ltq_soc_setup(void) --{ -- ltq_register_asc(0); -- ltq_register_asc(1); -- ltq_register_gpio(); -- ltq_register_wdt(); --} -Index: linux-3.3.8/arch/mips/lantiq/xway/prom.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/lantiq/xway/prom.c 2012-07-31 08:52:14.155414782 +0200 -@@ -0,0 +1,79 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2010 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "../prom.h" -+#include "devices.h" -+ -+#define SOC_DANUBE "Danube" -+#define SOC_TWINPASS "Twinpass" -+#define SOC_AR9 "AR9" -+#define SOC_VR9 "VR9" -+ -+#define PART_SHIFT 12 -+#define PART_MASK 0x0FFFFFFF -+#define REV_SHIFT 28 -+#define REV_MASK 0xF0000000 -+ -+#define SOC_AMAZON_SE "Amazon_SE" -+ -+void __init ltq_soc_detect(struct ltq_soc_info *i) -+{ -+ i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; -+ i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; -+ sprintf(i->rev_type, "1.%d", i->rev); -+ switch (i->partnum) { -+ case SOC_ID_DANUBE1: -+ case SOC_ID_DANUBE2: -+ i->name = SOC_DANUBE; -+ i->type = SOC_TYPE_DANUBE; -+ break; -+ -+ case SOC_ID_TWINPASS: -+ i->name = SOC_TWINPASS; -+ i->type = SOC_TYPE_DANUBE; -+ break; -+ -+ case SOC_ID_ARX188: -+ case SOC_ID_ARX168: -+ case SOC_ID_ARX182: -+ i->name = SOC_AR9; -+ i->type = SOC_TYPE_AR9; -+ break; -+ -+ case SOC_ID_AMAZON_SE: -+ i->name = SOC_AMAZON_SE; -+ i->type = SOC_TYPE_AMAZON_SE; -+#ifdef CONFIG_PCI -+ panic("ase is only supported for non pci kernels"); -+#endif -+ break; -+ -+ default: -+ unreachable(); -+ break; -+ } -+} -+ -+void __init ltq_soc_setup(void) -+{ -+ if (ltq_is_ase()) { -+ ltq_register_ase_asc(); -+ } else { -+ ltq_register_asc(0); -+ ltq_register_asc(1); -+ } -+ ltq_register_gpio(); -+ ltq_register_wdt(); -+} diff --git a/target/linux/lantiq/patches-3.3/0032-MIPS-lantiq-add-vr9-support.patch b/target/linux/lantiq/patches-3.3/0032-MIPS-lantiq-add-vr9-support.patch deleted file mode 100644 index 54d5e95b22..0000000000 --- a/target/linux/lantiq/patches-3.3/0032-MIPS-lantiq-add-vr9-support.patch +++ /dev/null @@ -1,161 +0,0 @@ -From d1711082beab74da07c2fd330c462ef407cb5579 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 21 Feb 2012 09:48:11 +0100 -Subject: [PATCH 32/70] MIPS: lantiq: add vr9 support - -VR9 is a VDSL SoC made by Lantiq. It is very similar to the AR9. -This patch adds the clkdev init code and SoC detection for the VR9. - -Signed-off-by: John Crispin -Signed-off-by: Daniel Schwierzeck ---- - .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 + - arch/mips/lantiq/xway/clk.c | 83 ++++++++++++++++++++ - arch/mips/lantiq/xway/prom.c | 6 ++ - arch/mips/lantiq/xway/sysctrl.c | 12 +++- - 4 files changed, 103 insertions(+), 1 deletions(-) - ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -@@ -21,6 +21,9 @@ - #define SOC_ID_ARX188 0x16C - #define SOC_ID_ARX168 0x16D - #define SOC_ID_ARX182 0x16F -+#define SOC_ID_VRX288 0x1C0 /* VRX288 v1.1 */ -+#define SOC_ID_VRX268 0x1C2 /* VRX268 v1.1 */ -+#define SOC_ID_GRX288 0x1C9 /* GRX288 v1.1 */ - - /* SoC Types */ - #define SOC_TYPE_DANUBE 0x01 ---- a/arch/mips/lantiq/xway/clk.c -+++ b/arch/mips/lantiq/xway/clk.c -@@ -225,3 +225,86 @@ unsigned long ltq_danube_fpi_hz(void) - return ddr_clock >> 1; - return ddr_clock; - } -+ -+unsigned long ltq_vr9_cpu_hz(void) -+{ -+ unsigned int cpu_sel; -+ unsigned long clk; -+ -+ cpu_sel = (ltq_cgu_r32(LTQ_CGU_SYS_VR9) >> 4) & 0xf; -+ -+ switch (cpu_sel) { -+ case 0: -+ clk = CLOCK_600M; -+ break; -+ case 1: -+ clk = CLOCK_500M; -+ break; -+ case 2: -+ clk = CLOCK_393M; -+ break; -+ case 3: -+ clk = CLOCK_333M; -+ break; -+ case 5: -+ case 6: -+ clk = CLOCK_196_608M; -+ break; -+ case 7: -+ clk = CLOCK_167M; -+ break; -+ case 4: -+ case 8: -+ case 9: -+ clk = CLOCK_125M; -+ break; -+ default: -+ clk = 0; -+ break; -+ } -+ -+ return clk; -+} -+ -+unsigned long ltq_vr9_fpi_hz(void) -+{ -+ unsigned int ocp_sel, cpu_clk; -+ unsigned long clk; -+ -+ cpu_clk = ltq_vr9_cpu_hz(); -+ ocp_sel = ltq_cgu_r32(LTQ_CGU_SYS_VR9) & 0x3; -+ -+ switch (ocp_sel) { -+ case 0: -+ /* OCP ratio 1 */ -+ clk = cpu_clk; -+ break; -+ case 2: -+ /* OCP ratio 2 */ -+ clk = cpu_clk / 2; -+ break; -+ case 3: -+ /* OCP ratio 2.5 */ -+ clk = (cpu_clk * 2) / 5; -+ break; -+ case 4: -+ /* OCP ratio 3 */ -+ clk = cpu_clk / 3; -+ break; -+ default: -+ clk = 0; -+ break; -+ } -+ -+ return clk; -+} -+ -+unsigned long ltq_vr9_io_region_clock(void) -+{ -+ return ltq_vr9_fpi_hz(); -+} -+ -+unsigned long ltq_vr9_fpi_bus_clock(int fpi) -+{ -+ return ltq_vr9_fpi_hz(); -+} ---- a/arch/mips/lantiq/xway/prom.c -+++ b/arch/mips/lantiq/xway/prom.c -@@ -60,6 +60,12 @@ void __init ltq_soc_detect(struct ltq_so - #endif - break; - -+ case SOC_ID_VRX268: -+ case SOC_ID_VRX288: -+ i->name = SOC_VR9; -+ i->type = SOC_TYPE_VR9; -+ break; -+ - default: - unreachable(); - break; ---- a/arch/mips/lantiq/xway/sysctrl.c -+++ b/arch/mips/lantiq/xway/sysctrl.c -@@ -147,7 +147,8 @@ void __init ltq_soc_init(void) - clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA); - clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP); - clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI); -- clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE); -+ if (!ltq_is_vr9()) -+ clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE); - if (ltq_is_ase()) { - if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5)) - clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M); -@@ -155,6 +156,15 @@ void __init ltq_soc_init(void) - clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M); - clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY), - clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY); -+ } else if (ltq_is_vr9()) { -+ clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(), -+ ltq_vr9_io_region_clock()); -+ clkdev_add_pmu("ltq_pcie", "phy", 1, PMU1_PCIE_PHY); -+ clkdev_add_pmu("ltq_pcie", "bus", 0, PMU_PCIE_CLK); -+ clkdev_add_pmu("ltq_pcie", "msi", 1, PMU1_PCIE_MSI); -+ clkdev_add_pmu("ltq_pcie", "pdi", 1, PMU1_PCIE_PDI); -+ clkdev_add_pmu("ltq_pcie", "ctl", 1, PMU1_PCIE_CTL); -+ clkdev_add_pmu("ltq_pcie", "ahb", 0, PMU_AHBM | PMU_AHBS); - } else { - clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(), - ltq_danube_io_region_clock()); diff --git a/target/linux/lantiq/patches-3.3/0033-MIPS-lantiq-add-ipi-handlers-to-make-vsmp-work.patch b/target/linux/lantiq/patches-3.3/0033-MIPS-lantiq-add-ipi-handlers-to-make-vsmp-work.patch deleted file mode 100644 index a23a6d90e3..0000000000 --- a/target/linux/lantiq/patches-3.3/0033-MIPS-lantiq-add-ipi-handlers-to-make-vsmp-work.patch +++ /dev/null @@ -1,117 +0,0 @@ -From ec3b7d909fcc78e12625a4dd7ca27f63dddb3fa3 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 21 Feb 2012 21:09:01 +0100 -Subject: [PATCH 33/70] MIPS: lantiq: add ipi handlers to make vsmp work - -Add IPI handlers to the interrupt code. This patch makes MIPS_MT_SMP work -on lantiq SoCs. - -Signed-off-by: John Crispin ---- - arch/mips/lantiq/irq.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++ - arch/mips/lantiq/prom.c | 5 ++++ - 2 files changed, 66 insertions(+), 0 deletions(-) - ---- a/arch/mips/lantiq/irq.c -+++ b/arch/mips/lantiq/irq.c -@@ -9,6 +9,7 @@ - - #include - #include -+#include - - #include - #include -@@ -54,6 +55,14 @@ - #define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y)) - #define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x)) - -+/* our 2 ipi interrupts for VSMP */ -+#define MIPS_CPU_IPI_RESCHED_IRQ 0 -+#define MIPS_CPU_IPI_CALL_IRQ 1 -+ -+#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) -+int gic_present; -+#endif -+ - static unsigned short ltq_eiu_irq[MAX_EIU] = { - LTQ_EIU_IR0, - LTQ_EIU_IR1, -@@ -219,6 +228,47 @@ static void ltq_hw5_irqdispatch(void) - do_IRQ(MIPS_CPU_TIMER_IRQ); - } - -+#ifdef CONFIG_MIPS_MT_SMP -+void __init arch_init_ipiirq(int irq, struct irqaction *action) -+{ -+ setup_irq(irq, action); -+ irq_set_handler(irq, handle_percpu_irq); -+} -+ -+static void ltq_sw0_irqdispatch(void) -+{ -+ do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ); -+} -+ -+static void ltq_sw1_irqdispatch(void) -+{ -+ do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ); -+} -+static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id) -+{ -+ scheduler_ipi(); -+ return IRQ_HANDLED; -+} -+ -+static irqreturn_t ipi_call_interrupt(int irq, void *dev_id) -+{ -+ smp_call_function_interrupt(); -+ return IRQ_HANDLED; -+} -+ -+static struct irqaction irq_resched = { -+ .handler = ipi_resched_interrupt, -+ .flags = IRQF_PERCPU, -+ .name = "IPI_resched" -+}; -+ -+static struct irqaction irq_call = { -+ .handler = ipi_call_interrupt, -+ .flags = IRQF_PERCPU, -+ .name = "IPI_call" -+}; -+#endif -+ - asmlinkage void plat_irq_dispatch(void) - { - unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; -@@ -313,6 +363,17 @@ void __init arch_init_irq(void) - irq_set_chip_and_handler(i, <q_irq_type, - handle_level_irq); - -+#if defined(CONFIG_MIPS_MT_SMP) -+ if (cpu_has_vint) { -+ pr_info("Setting up IPI vectored interrupts\n"); -+ set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch); -+ set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch); -+ } -+ arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ, -+ &irq_resched); -+ arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call); -+#endif -+ - #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC) - set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | - IE_IRQ3 | IE_IRQ4 | IE_IRQ5); ---- a/arch/mips/lantiq/prom.c -+++ b/arch/mips/lantiq/prom.c -@@ -108,4 +108,9 @@ void __init prom_init(void) - soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; - pr_info("SoC: %s\n", soc_info.sys_type); - prom_init_cmdline(); -+ -+#if defined(CONFIG_MIPS_MT_SMP) -+ if (register_vsmp_smp_ops()) -+ panic("failed to register_vsmp_smp_ops()"); -+#endif - } diff --git a/target/linux/lantiq/patches-3.3/0034-MIPS-lantiq-add-additional-soc-ids.patch b/target/linux/lantiq/patches-3.3/0034-MIPS-lantiq-add-additional-soc-ids.patch deleted file mode 100644 index d73db6486c..0000000000 --- a/target/linux/lantiq/patches-3.3/0034-MIPS-lantiq-add-additional-soc-ids.patch +++ /dev/null @@ -1,149 +0,0 @@ -From c02c17b2d2bd9663ded7e9f59d6ef24fba239b33 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 12 Mar 2012 15:23:39 +0100 -Subject: [PATCH 34/70] MIPS: lantiq: add additional soc ids - ---- - .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 38 +++++++++++++++---- - arch/mips/lantiq/xway/prom.c | 35 ++++++++++++++++-- - 2 files changed, 61 insertions(+), 12 deletions(-) - ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -@@ -17,20 +17,32 @@ - #define SOC_ID_DANUBE1 0x129 - #define SOC_ID_DANUBE2 0x12B - #define SOC_ID_TWINPASS 0x12D --#define SOC_ID_AMAZON_SE 0x152 -+#define SOC_ID_AMAZON_SE_1 0x152 /* 50601 */ -+#define SOC_ID_AMAZON_SE_2 0x153 /* 50600 */ - #define SOC_ID_ARX188 0x16C --#define SOC_ID_ARX168 0x16D -+#define SOC_ID_ARX168_1 0x16D -+#define SOC_ID_ARX168_2 0x16E - #define SOC_ID_ARX182 0x16F --#define SOC_ID_VRX288 0x1C0 /* VRX288 v1.1 */ --#define SOC_ID_VRX268 0x1C2 /* VRX268 v1.1 */ --#define SOC_ID_GRX288 0x1C9 /* GRX288 v1.1 */ -+#define SOC_ID_GRX188 0x170 -+#define SOC_ID_GRX168 0x171 -+ -+#define SOC_ID_VRX288 0x1C0 /* v1.1 */ -+#define SOC_ID_VRX282 0x1C1 /* v1.1 */ -+#define SOC_ID_VRX268 0x1C2 /* v1.1 */ -+#define SOC_ID_GRX268 0x1C8 /* v1.1 */ -+#define SOC_ID_GRX288 0x1C9 /* v1.1 */ -+#define SOC_ID_VRX288_2 0x00B /* v1.2 */ -+#define SOC_ID_VRX268_2 0x00C /* v1.2 */ -+#define SOC_ID_GRX288_2 0x00D /* v1.2 */ -+#define SOC_ID_GRX282_2 0x00E /* v1.2 */ - - /* SoC Types */ - #define SOC_TYPE_DANUBE 0x01 - #define SOC_TYPE_TWINPASS 0x02 - #define SOC_TYPE_AR9 0x03 --#define SOC_TYPE_VR9 0x04 --#define SOC_TYPE_AMAZON_SE 0x05 -+#define SOC_TYPE_VR9_1 0x04 /* v1.1 */ -+#define SOC_TYPE_VR9_2 0x05 /* v1.2 */ -+#define SOC_TYPE_AMAZON_SE 0x06 - - /* ASC0/1 - serial port */ - #define LTQ_ASC0_BASE_ADDR 0x1E100400 -@@ -149,9 +161,19 @@ static inline int ltq_is_ar9(void) - return (ltq_get_soc_type() == SOC_TYPE_AR9); - } - -+static inline int ltq_is_vr9_1(void) -+{ -+ return (ltq_get_soc_type() == SOC_TYPE_VR9_1); -+} -+ -+static inline int ltq_is_vr9_2(void) -+{ -+ return (ltq_get_soc_type() == SOC_TYPE_VR9_2); -+} -+ - static inline int ltq_is_vr9(void) - { -- return (ltq_get_soc_type() == SOC_TYPE_VR9); -+ return (ltq_is_vr9_1() || ltq_is_vr9_2()); - } - - static inline int ltq_is_falcon(void) ---- a/arch/mips/lantiq/xway/prom.c -+++ b/arch/mips/lantiq/xway/prom.c -@@ -18,7 +18,9 @@ - - #define SOC_DANUBE "Danube" - #define SOC_TWINPASS "Twinpass" -+#define SOC_AMAZON_SE "Amazon_SE" - #define SOC_AR9 "AR9" -+#define SOC_GR9 "GR9" - #define SOC_VR9 "VR9" - - #define PART_SHIFT 12 -@@ -26,7 +28,6 @@ - #define REV_SHIFT 28 - #define REV_MASK 0xF0000000 - --#define SOC_AMAZON_SE "Amazon_SE" - - void __init ltq_soc_detect(struct ltq_soc_info *i) - { -@@ -46,13 +47,21 @@ void __init ltq_soc_detect(struct ltq_so - break; - - case SOC_ID_ARX188: -- case SOC_ID_ARX168: -+ case SOC_ID_ARX168_1: -+ case SOC_ID_ARX168_2: - case SOC_ID_ARX182: - i->name = SOC_AR9; - i->type = SOC_TYPE_AR9; - break; - -- case SOC_ID_AMAZON_SE: -+ case SOC_ID_GRX188: -+ case SOC_ID_GRX168: -+ i->name = SOC_GR9; -+ i->type = SOC_TYPE_AR9; -+ break; -+ -+ case SOC_ID_AMAZON_SE_1: -+ case SOC_ID_AMAZON_SE_2: - i->name = SOC_AMAZON_SE; - i->type = SOC_TYPE_AMAZON_SE; - #ifdef CONFIG_PCI -@@ -60,12 +69,30 @@ void __init ltq_soc_detect(struct ltq_so - #endif - break; - -+ case SOC_ID_VRX282: - case SOC_ID_VRX268: - case SOC_ID_VRX288: - i->name = SOC_VR9; -- i->type = SOC_TYPE_VR9; -+ i->type = SOC_TYPE_VR9_1; - break; - -+ case SOC_ID_GRX268: -+ case SOC_ID_GRX288: -+ i->name = SOC_GR9; -+ i->type = SOC_TYPE_VR9_1; -+ break; -+ -+ case SOC_ID_VRX268_2: -+ case SOC_ID_VRX288_2: -+ i->name = SOC_VR9; -+ i->type = SOC_TYPE_VR9_2; -+ break; -+ -+ case SOC_ID_GRX282_2: -+ case SOC_ID_GRX288_2: -+ i->name = SOC_GR9; -+ i->type = SOC_TYPE_VR9_2; -+ - default: - unreachable(); - break; diff --git a/target/linux/lantiq/patches-3.3/0035-SPI-MIPS-lantiq-add-FALC-ON-spi-driver.patch b/target/linux/lantiq/patches-3.3/0035-SPI-MIPS-lantiq-add-FALC-ON-spi-driver.patch deleted file mode 100644 index 2dec939836..0000000000 --- a/target/linux/lantiq/patches-3.3/0035-SPI-MIPS-lantiq-add-FALC-ON-spi-driver.patch +++ /dev/null @@ -1,617 +0,0 @@ -From efa434fed99cee45778d824b34ccabb473a978ec Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sat, 27 Aug 2011 18:12:26 +0200 -Subject: [PATCH 35/70] SPI: MIPS: lantiq: add FALC-ON spi driver - -The external bus unit (EBU) found on the FALC-ON SoC has spi emulation that is -designed for serial flash access. This driver has only been tested with m25p80 -type chips. The hardware has no support for other types of spi peripherals. - -Signed-off-by: Thomas Langer -Signed-off-by: John Crispin -Cc: spi-devel-general@lists.sourceforge.net ---- - arch/mips/lantiq/falcon/devices.c | 13 + - arch/mips/lantiq/falcon/devices.h | 4 + - arch/mips/lantiq/falcon/mach-easy98000.c | 27 ++ - drivers/spi/Kconfig | 4 + - drivers/spi/Makefile | 1 + - drivers/spi/spi-falcon.c | 483 ++++++++++++++++++++++++++++++ - 6 files changed, 532 insertions(+), 0 deletions(-) - create mode 100644 drivers/spi/spi-falcon.c - ---- a/arch/mips/lantiq/falcon/devices.c -+++ b/arch/mips/lantiq/falcon/devices.c -@@ -121,3 +121,16 @@ falcon_register_gpio_extra(void) - platform_device_register_simple("falcon_gpio", 4, - falcon_gpio4_res, ARRAY_SIZE(falcon_gpio4_res)); - } -+ -+/* spi flash */ -+static struct platform_device ltq_spi = { -+ .name = "falcon_spi", -+ .num_resources = 0, -+}; -+ -+void __init -+falcon_register_spi_flash(struct spi_board_info *data) -+{ -+ spi_register_board_info(data, 1); -+ platform_device_register(<q_spi); -+} ---- a/arch/mips/lantiq/falcon/devices.h -+++ b/arch/mips/lantiq/falcon/devices.h -@@ -11,10 +11,14 @@ - #ifndef _FALCON_DEVICES_H__ - #define _FALCON_DEVICES_H__ - -+#include -+#include -+ - #include "../devices.h" - - extern void falcon_register_nand(void); - extern void falcon_register_gpio(void); - extern void falcon_register_gpio_extra(void); -+extern void falcon_register_spi_flash(struct spi_board_info *data); - - #endif ---- a/arch/mips/lantiq/falcon/mach-easy98000.c -+++ b/arch/mips/lantiq/falcon/mach-easy98000.c -@@ -40,6 +40,21 @@ struct physmap_flash_data easy98000_nor_ - .parts = easy98000_nor_partitions, - }; - -+static struct flash_platform_data easy98000_spi_flash_platform_data = { -+ .name = "sflash", -+ .parts = easy98000_nor_partitions, -+ .nr_parts = ARRAY_SIZE(easy98000_nor_partitions) -+}; -+ -+static struct spi_board_info easy98000_spi_flash_data __initdata = { -+ .modalias = "m25p80", -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 10 * 1000 * 1000, -+ .mode = SPI_MODE_3, -+ .platform_data = &easy98000_spi_flash_platform_data -+}; -+ - /* setup gpio based spi bus/device for access to the eeprom on the board */ - #define SPI_GPIO_MRST 102 - #define SPI_GPIO_MTSR 103 -@@ -93,6 +108,13 @@ easy98000_init(void) - } - - static void __init -+easy98000sf_init(void) -+{ -+ easy98000_init_common(); -+ falcon_register_spi_flash(&easy98000_spi_flash_data); -+} -+ -+static void __init - easy98000nand_init(void) - { - easy98000_init_common(); -@@ -104,6 +126,11 @@ MIPS_MACHINE(LANTIQ_MACH_EASY98000, - "EASY98000 Eval Board", - easy98000_init); - -+MIPS_MACHINE(LANTIQ_MACH_EASY98000SF, -+ "EASY98000SF", -+ "EASY98000 Eval Board (Serial Flash)", -+ easy98000sf_init); -+ - MIPS_MACHINE(LANTIQ_MACH_EASY98000NAND, - "EASY98000NAND", - "EASY98000 Eval Board (NAND Flash)", ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -188,6 +188,10 @@ config SPI_MPC52xx - This drivers supports the MPC52xx SPI controller in master SPI - mode. - -+config SPI_FALCON -+ tristate "Falcon SPI controller support" -+ depends on SOC_FALCON -+ - config SPI_MPC52xx_PSC - tristate "Freescale MPC52xx PSC SPI controller" - depends on PPC_MPC52xx && EXPERIMENTAL ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -25,6 +25,7 @@ obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmi - obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o - spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o - obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o -+obj-$(CONFIG_SPI_FALCON) += spi-falcon.o - obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-lib.o - obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o - obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o ---- /dev/null -+++ b/drivers/spi/spi-falcon.c -@@ -0,0 +1,483 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2010 Thomas Langer -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define DRV_NAME "falcon_spi" -+ -+#define FALCON_SPI_XFER_BEGIN (1 << 0) -+#define FALCON_SPI_XFER_END (1 << 1) -+ -+/* Bus Read Configuration Register0 */ -+#define LTQ_BUSRCON0 0x00000010 -+/* Bus Write Configuration Register0 */ -+#define LTQ_BUSWCON0 0x00000018 -+/* Serial Flash Configuration Register */ -+#define LTQ_SFCON 0x00000080 -+/* Serial Flash Time Register */ -+#define LTQ_SFTIME 0x00000084 -+/* Serial Flash Status Register */ -+#define LTQ_SFSTAT 0x00000088 -+/* Serial Flash Command Register */ -+#define LTQ_SFCMD 0x0000008C -+/* Serial Flash Address Register */ -+#define LTQ_SFADDR 0x00000090 -+/* Serial Flash Data Register */ -+#define LTQ_SFDATA 0x00000094 -+/* Serial Flash I/O Control Register */ -+#define LTQ_SFIO 0x00000098 -+/* EBU Clock Control Register */ -+#define LTQ_EBUCC 0x000000C4 -+ -+/* Dummy Phase Length */ -+#define SFCMD_DUMLEN_OFFSET 16 -+#define SFCMD_DUMLEN_MASK 0x000F0000 -+/* Chip Select */ -+#define SFCMD_CS_OFFSET 24 -+#define SFCMD_CS_MASK 0x07000000 -+/* field offset */ -+#define SFCMD_ALEN_OFFSET 20 -+#define SFCMD_ALEN_MASK 0x00700000 -+/* SCK Rise-edge Position */ -+#define SFTIME_SCKR_POS_OFFSET 8 -+#define SFTIME_SCKR_POS_MASK 0x00000F00 -+/* SCK Period */ -+#define SFTIME_SCK_PER_OFFSET 0 -+#define SFTIME_SCK_PER_MASK 0x0000000F -+/* SCK Fall-edge Position */ -+#define SFTIME_SCKF_POS_OFFSET 12 -+#define SFTIME_SCKF_POS_MASK 0x0000F000 -+/* Device Size */ -+#define SFCON_DEV_SIZE_A23_0 0x03000000 -+#define SFCON_DEV_SIZE_MASK 0x0F000000 -+/* Read Data Position */ -+#define SFTIME_RD_POS_MASK 0x000F0000 -+/* Data Output */ -+#define SFIO_UNUSED_WD_MASK 0x0000000F -+/* Command Opcode mask */ -+#define SFCMD_OPC_MASK 0x000000FF -+/* dlen bytes of data to write */ -+#define SFCMD_DIR_WRITE 0x00000100 -+/* Data Length offset */ -+#define SFCMD_DLEN_OFFSET 9 -+/* Command Error */ -+#define SFSTAT_CMD_ERR 0x20000000 -+/* Access Command Pending */ -+#define SFSTAT_CMD_PEND 0x00400000 -+/* Frequency set to 100MHz. */ -+#define EBUCC_EBUDIV_SELF100 0x00000001 -+/* Serial Flash */ -+#define BUSRCON0_AGEN_SERIAL_FLASH 0xF0000000 -+/* 8-bit multiplexed */ -+#define BUSRCON0_PORTW_8_BIT_MUX 0x00000000 -+/* Serial Flash */ -+#define BUSWCON0_AGEN_SERIAL_FLASH 0xF0000000 -+/* Chip Select after opcode */ -+#define SFCMD_KEEP_CS_KEEP_SELECTED 0x00008000 -+ -+struct falcon_spi { -+ u32 sfcmd; /* for caching of opcode, direction, ... */ -+ struct spi_master *master; -+}; -+ -+int -+falcon_spi_xfer(struct spi_device *spi, -+ struct spi_transfer *t, -+ unsigned long flags) -+{ -+ struct device *dev = &spi->dev; -+ struct falcon_spi *priv = spi_master_get_devdata(spi->master); -+ const u8 *txp = t->tx_buf; -+ u8 *rxp = t->rx_buf; -+ unsigned int bytelen = ((8 * t->len + 7) / 8); -+ unsigned int len, alen, dumlen; -+ u32 val; -+ enum { -+ state_init, -+ state_command_prepare, -+ state_write, -+ state_read, -+ state_disable_cs, -+ state_end -+ } state = state_init; -+ -+ do { -+ switch (state) { -+ case state_init: /* detect phase of upper layer sequence */ -+ { -+ /* initial write ? */ -+ if (flags & FALCON_SPI_XFER_BEGIN) { -+ if (!txp) { -+ dev_err(dev, -+ "BEGIN without tx data!\n"); -+ return -1; -+ } -+ /* -+ * Prepare the parts of the sfcmd register, -+ * which should not -+ * change during a sequence! -+ * Only exception are the length fields, -+ * especially alen and dumlen. -+ */ -+ -+ priv->sfcmd = ((spi->chip_select -+ << SFCMD_CS_OFFSET) -+ & SFCMD_CS_MASK); -+ priv->sfcmd |= SFCMD_KEEP_CS_KEEP_SELECTED; -+ priv->sfcmd |= *txp; -+ txp++; -+ bytelen--; -+ if (bytelen) { -+ /* -+ * more data: -+ * maybe address and/or dummy -+ */ -+ state = state_command_prepare; -+ break; -+ } else { -+ dev_dbg(dev, "write cmd %02X\n", -+ priv->sfcmd & SFCMD_OPC_MASK); -+ } -+ } -+ /* continued write ? */ -+ if (txp && bytelen) { -+ state = state_write; -+ break; -+ } -+ /* read data? */ -+ if (rxp && bytelen) { -+ state = state_read; -+ break; -+ } -+ /* end of sequence? */ -+ if (flags & FALCON_SPI_XFER_END) -+ state = state_disable_cs; -+ else -+ state = state_end; -+ break; -+ } -+ /* collect tx data for address and dummy phase */ -+ case state_command_prepare: -+ { -+ /* txp is valid, already checked */ -+ val = 0; -+ alen = 0; -+ dumlen = 0; -+ while (bytelen > 0) { -+ if (alen < 3) { -+ val = (val<<8)|(*txp++); -+ alen++; -+ } else if ((dumlen < 15) && (*txp == 0)) { -+ /* -+ * assume dummy bytes are set to 0 -+ * from upper layer -+ */ -+ dumlen++; -+ txp++; -+ } else -+ break; -+ bytelen--; -+ } -+ priv->sfcmd &= ~(SFCMD_ALEN_MASK | SFCMD_DUMLEN_MASK); -+ priv->sfcmd |= (alen << SFCMD_ALEN_OFFSET) | -+ (dumlen << SFCMD_DUMLEN_OFFSET); -+ if (alen > 0) -+ ltq_ebu_w32(val, LTQ_SFADDR); -+ -+ dev_dbg(dev, "write cmd %02X, alen=%d " -+ "(addr=%06X) dumlen=%d\n", -+ priv->sfcmd & SFCMD_OPC_MASK, -+ alen, val, dumlen); -+ -+ if (bytelen > 0) { -+ /* continue with write */ -+ state = state_write; -+ } else if (flags & FALCON_SPI_XFER_END) { -+ /* end of sequence? */ -+ state = state_disable_cs; -+ } else { -+ /* -+ * go to end and expect another -+ * call (read or write) -+ */ -+ state = state_end; -+ } -+ break; -+ } -+ case state_write: -+ { -+ /* txp still valid */ -+ priv->sfcmd |= SFCMD_DIR_WRITE; -+ len = 0; -+ val = 0; -+ do { -+ if (bytelen--) -+ val |= (*txp++) << (8 * len++); -+ if ((flags & FALCON_SPI_XFER_END) -+ && (bytelen == 0)) { -+ priv->sfcmd &= -+ ~SFCMD_KEEP_CS_KEEP_SELECTED; -+ } -+ if ((len == 4) || (bytelen == 0)) { -+ ltq_ebu_w32(val, LTQ_SFDATA); -+ ltq_ebu_w32(priv->sfcmd -+ | (len<sfcmd &= ~(SFCMD_ALEN_MASK -+ | SFCMD_DUMLEN_MASK); -+ } -+ } while (bytelen); -+ state = state_end; -+ break; -+ } -+ case state_read: -+ { -+ /* read data */ -+ priv->sfcmd &= ~SFCMD_DIR_WRITE; -+ do { -+ if ((flags & FALCON_SPI_XFER_END) -+ && (bytelen <= 4)) { -+ priv->sfcmd &= -+ ~SFCMD_KEEP_CS_KEEP_SELECTED; -+ } -+ len = (bytelen > 4) ? 4 : bytelen; -+ bytelen -= len; -+ ltq_ebu_w32(priv->sfcmd -+ |(len<sfcmd &= ~(SFCMD_ALEN_MASK -+ | SFCMD_DUMLEN_MASK); -+ do { -+ val = ltq_ebu_r32(LTQ_SFSTAT); -+ if (val & SFSTAT_CMD_ERR) { -+ /* reset error status */ -+ dev_err(dev, "SFSTAT: CMD_ERR " -+ "(%x)\n", val); -+ ltq_ebu_w32(SFSTAT_CMD_ERR, -+ LTQ_SFSTAT); -+ return -1; -+ } -+ } while (val & SFSTAT_CMD_PEND); -+ val = ltq_ebu_r32(LTQ_SFDATA); -+ do { -+ *rxp = (val & 0xFF); -+ rxp++; -+ val >>= 8; -+ len--; -+ } while (len); -+ } while (bytelen); -+ state = state_end; -+ break; -+ } -+ case state_disable_cs: -+ { -+ priv->sfcmd &= ~SFCMD_KEEP_CS_KEEP_SELECTED; -+ ltq_ebu_w32(priv->sfcmd | (0 << SFCMD_DLEN_OFFSET), -+ LTQ_SFCMD); -+ val = ltq_ebu_r32(LTQ_SFSTAT); -+ if (val & SFSTAT_CMD_ERR) { -+ /* reset error status */ -+ dev_err(dev, "SFSTAT: CMD_ERR (%x)\n", val); -+ ltq_ebu_w32(SFSTAT_CMD_ERR, LTQ_SFSTAT); -+ return -1; -+ } -+ state = state_end; -+ break; -+ } -+ case state_end: -+ break; -+ } -+ } while (state != state_end); -+ -+ return 0; -+} -+ -+static int -+falcon_spi_setup(struct spi_device *spi) -+{ -+ struct device *dev = &spi->dev; -+ const u32 ebuclk = 100000000; -+ unsigned int i; -+ unsigned long flags; -+ -+ dev_dbg(dev, "setup\n"); -+ -+ if (spi->master->bus_num > 0 || spi->chip_select > 0) -+ return -ENODEV; -+ -+ spin_lock_irqsave(&ebu_lock, flags); -+ -+ if (ebuclk < spi->max_speed_hz) { -+ /* set EBU clock to 100 MHz */ -+ ltq_sys1_w32_mask(0, EBUCC_EBUDIV_SELF100, LTQ_EBUCC); -+ i = 1; /* divider */ -+ } else { -+ /* set EBU clock to 50 MHz */ -+ ltq_sys1_w32_mask(EBUCC_EBUDIV_SELF100, 0, LTQ_EBUCC); -+ -+ /* search for suitable divider */ -+ for (i = 1; i < 7; i++) { -+ if (ebuclk / i <= spi->max_speed_hz) -+ break; -+ } -+ } -+ -+ /* setup period of serial clock */ -+ ltq_ebu_w32_mask(SFTIME_SCKF_POS_MASK -+ | SFTIME_SCKR_POS_MASK -+ | SFTIME_SCK_PER_MASK, -+ (i << SFTIME_SCKR_POS_OFFSET) -+ | (i << (SFTIME_SCK_PER_OFFSET + 1)), -+ LTQ_SFTIME); -+ -+ /* -+ * set some bits of unused_wd, to not trigger HOLD/WP -+ * signals on non QUAD flashes -+ */ -+ ltq_ebu_w32((SFIO_UNUSED_WD_MASK & (0x8 | 0x4)), LTQ_SFIO); -+ -+ ltq_ebu_w32(BUSRCON0_AGEN_SERIAL_FLASH | BUSRCON0_PORTW_8_BIT_MUX, -+ LTQ_BUSRCON0); -+ ltq_ebu_w32(BUSWCON0_AGEN_SERIAL_FLASH, LTQ_BUSWCON0); -+ /* set address wrap around to maximum for 24-bit addresses */ -+ ltq_ebu_w32_mask(SFCON_DEV_SIZE_MASK, SFCON_DEV_SIZE_A23_0, LTQ_SFCON); -+ -+ spin_unlock_irqrestore(&ebu_lock, flags); -+ -+ return 0; -+} -+ -+static int -+falcon_spi_transfer(struct spi_device *spi, struct spi_message *m) -+{ -+ struct falcon_spi *priv = spi_master_get_devdata(spi->master); -+ struct spi_transfer *t; -+ unsigned long spi_flags; -+ unsigned long flags; -+ int ret = 0; -+ -+ priv->sfcmd = 0; -+ m->actual_length = 0; -+ -+ spi_flags = FALCON_SPI_XFER_BEGIN; -+ list_for_each_entry(t, &m->transfers, transfer_list) { -+ if (list_is_last(&t->transfer_list, &m->transfers)) -+ spi_flags |= FALCON_SPI_XFER_END; -+ -+ spin_lock_irqsave(&ebu_lock, flags); -+ ret = falcon_spi_xfer(spi, t, spi_flags); -+ spin_unlock_irqrestore(&ebu_lock, flags); -+ -+ if (ret) -+ break; -+ -+ m->actual_length += t->len; -+ -+ if (t->delay_usecs || t->cs_change) -+ BUG(); -+ -+ spi_flags = 0; -+ } -+ -+ m->status = ret; -+ m->complete(m->context); -+ -+ return 0; -+} -+ -+static void -+falcon_spi_cleanup(struct spi_device *spi) -+{ -+ struct device *dev = &spi->dev; -+ -+ dev_dbg(dev, "cleanup\n"); -+} -+ -+static int __devinit -+falcon_spi_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct falcon_spi *priv; -+ struct spi_master *master; -+ int ret; -+ -+ dev_dbg(dev, "probing\n"); -+ -+ master = spi_alloc_master(&pdev->dev, sizeof(*priv)); -+ if (!master) { -+ dev_err(dev, "no memory for spi_master\n"); -+ return -ENOMEM; -+ } -+ -+ priv = spi_master_get_devdata(master); -+ priv->master = master; -+ -+ master->mode_bits = SPI_MODE_3; -+ master->num_chipselect = 1; -+ master->bus_num = 0; -+ -+ master->setup = falcon_spi_setup; -+ master->transfer = falcon_spi_transfer; -+ master->cleanup = falcon_spi_cleanup; -+ -+ platform_set_drvdata(pdev, priv); -+ -+ ret = spi_register_master(master); -+ if (ret) -+ spi_master_put(master); -+ -+ return ret; -+} -+ -+static int __devexit -+falcon_spi_remove(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct falcon_spi *priv = platform_get_drvdata(pdev); -+ -+ dev_dbg(dev, "removed\n"); -+ -+ spi_unregister_master(priv->master); -+ -+ return 0; -+} -+ -+static struct platform_driver falcon_spi_driver = { -+ .probe = falcon_spi_probe, -+ .remove = __devexit_p(falcon_spi_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE -+ } -+}; -+ -+static int __init -+falcon_spi_init(void) -+{ -+ return platform_driver_register(&falcon_spi_driver); -+} -+ -+static void __exit -+falcon_spi_exit(void) -+{ -+ platform_driver_unregister(&falcon_spi_driver); -+} -+ -+module_init(falcon_spi_init); -+module_exit(falcon_spi_exit); -+ -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("Lantiq Falcon SPI controller driver"); diff --git a/target/linux/lantiq/patches-3.3/0036-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch b/target/linux/lantiq/patches-3.3/0036-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch deleted file mode 100644 index 8107450c12..0000000000 --- a/target/linux/lantiq/patches-3.3/0036-I2C-MIPS-lantiq-add-FALC-ON-i2c-bus-master.patch +++ /dev/null @@ -1,1204 +0,0 @@ -From 59e21a2ab9b7554acf2c15dc9ee191e76bebade7 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 4 Nov 2011 16:00:34 +0100 -Subject: [PATCH 36/70] I2C: MIPS: lantiq: add FALC-ON i2c bus master - -This patch adds the driver needed to make the I2C bus work on FALC-ON SoCs. - -Signed-off-by: Thomas Langer -Signed-off-by: John Crispin -Cc: linux-i2c@vger.kernel.org ---- - .../include/asm/mach-lantiq/falcon/lantiq_soc.h | 5 + - arch/mips/lantiq/falcon/clk.c | 44 - - arch/mips/lantiq/falcon/devices.c | 16 + - arch/mips/lantiq/falcon/devices.h | 1 + - arch/mips/lantiq/falcon/mach-easy98000.c | 1 + - drivers/i2c/busses/Kconfig | 10 + - drivers/i2c/busses/Makefile | 1 + - drivers/i2c/busses/i2c-falcon.c | 1040 ++++++++++++++++++++ - 8 files changed, 1074 insertions(+), 44 deletions(-) - delete mode 100644 arch/mips/lantiq/falcon/clk.c - create mode 100644 drivers/i2c/busses/i2c-falcon.c - ---- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h -@@ -72,6 +72,10 @@ - #define LTQ_PADCTRL4_BASE_ADDR 0x1E800600 - #define LTQ_PADCTRL4_SIZE 0x0100 - -+/* I2C */ -+#define GPON_I2C_BASE 0x1E200000 -+#define GPON_I2C_SIZE 0x00010000 -+ - /* CHIP ID */ - #define LTQ_STATUS_BASE_ADDR 0x1E802000 - -@@ -106,6 +110,7 @@ - #define ACTS_PADCTRL2 0x00200000 - #define ACTS_PADCTRL3 0x00200000 - #define ACTS_PADCTRL4 0x00400000 -+#define ACTS_I2C_ACT 0x00004000 - - /* global register ranges */ - extern __iomem void *ltq_ebu_membase; ---- a/arch/mips/lantiq/falcon/clk.c -+++ /dev/null -@@ -1,44 +0,0 @@ --/* -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- * -- * Copyright (C) 2011 Thomas Langer -- * Copyright (C) 2011 John Crispin -- */ -- --#include --#include -- --#include -- --#include "devices.h" -- --/* CPU0 Clock Control Register */ --#define LTQ_SYS1_CPU0CC 0x0040 --/* clock divider bit */ --#define LTQ_CPU0CC_CPUDIV 0x0001 -- --unsigned int --ltq_get_io_region_clock(void) --{ -- return CLOCK_200M; --} --EXPORT_SYMBOL(ltq_get_io_region_clock); -- --unsigned int --ltq_get_cpu_hz(void) --{ -- if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV) -- return CLOCK_200M; -- else -- return CLOCK_400M; --} --EXPORT_SYMBOL(ltq_get_cpu_hz); -- --unsigned int --ltq_get_fpi_hz(void) --{ -- return CLOCK_100M; --} --EXPORT_SYMBOL(ltq_get_fpi_hz); ---- a/arch/mips/lantiq/falcon/devices.c -+++ b/arch/mips/lantiq/falcon/devices.c -@@ -134,3 +134,19 @@ falcon_register_spi_flash(struct spi_boa - spi_register_board_info(data, 1); - platform_device_register(<q_spi); - } -+ -+/* i2c */ -+static struct resource falcon_i2c_resources[] = { -+ MEM_RES("i2c", GPON_I2C_BASE, GPON_I2C_SIZE), -+ IRQ_RES(i2c_lb, FALCON_IRQ_I2C_LBREQ), -+ IRQ_RES(i2c_b, FALCON_IRQ_I2C_BREQ), -+ IRQ_RES(i2c_err, FALCON_IRQ_I2C_I2C_ERR), -+ IRQ_RES(i2c_p, FALCON_IRQ_I2C_I2C_P), -+}; -+ -+void __init -+falcon_register_i2c(void) -+{ -+ platform_device_register_simple("i2c-falcon", 0, -+ falcon_i2c_resources, ARRAY_SIZE(falcon_i2c_resources)); -+} ---- a/arch/mips/lantiq/falcon/devices.h -+++ b/arch/mips/lantiq/falcon/devices.h -@@ -20,5 +20,6 @@ extern void falcon_register_nand(void); - extern void falcon_register_gpio(void); - extern void falcon_register_gpio_extra(void); - extern void falcon_register_spi_flash(struct spi_board_info *data); -+extern void falcon_register_i2c(void); - - #endif ---- a/arch/mips/lantiq/falcon/mach-easy98000.c -+++ b/arch/mips/lantiq/falcon/mach-easy98000.c -@@ -98,6 +98,7 @@ easy98000_init_common(void) - { - spi_register_board_info(&easy98000_spi_gpio_devices, 1); - platform_device_register(&easy98000_spi_gpio_device); -+ falcon_register_i2c(); - } - - static void __init ---- a/drivers/i2c/busses/Kconfig -+++ b/drivers/i2c/busses/Kconfig -@@ -369,6 +369,16 @@ config I2C_DESIGNWARE_PCI - This driver can also be built as a module. If so, the module - will be called i2c-designware-pci. - -+config I2C_FALCON -+ tristate "Falcon I2C interface" -+ depends on SOC_FALCON -+ help -+ If you say yes to this option, support will be included for the -+ Lantiq FALC-ON I2C core. -+ -+ This driver can also be built as a module. If so, the module -+ will be called i2c-falcon. -+ - config I2C_GPIO - tristate "GPIO-based bitbanging I2C" - depends on GENERIC_GPIO ---- a/drivers/i2c/busses/Makefile -+++ b/drivers/i2c/busses/Makefile -@@ -37,6 +37,7 @@ obj-$(CONFIG_I2C_DESIGNWARE_PLATFORM) += - i2c-designware-platform-objs := i2c-designware-platdrv.o i2c-designware-core.o - obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o - i2c-designware-pci-objs := i2c-designware-pcidrv.o i2c-designware-core.o -+obj-$(CONFIG_I2C_FALCON) += i2c-falcon.o - obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o - obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o - obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o ---- /dev/null -+++ b/drivers/i2c/busses/i2c-falcon.c -@@ -0,0 +1,1040 @@ -+/* -+ * Lantiq FALC(tm) ON - I2C bus adapter -+ * -+ * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33 -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ * -+ * Copyright (C) 2010 Thomas Langer -+ */ -+ -+/* -+ * CURRENT ISSUES: -+ * - no high speed support -+ * - supports only master mode -+ * - ten bit mode is not tested (no slave devices) -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+/* I2C Identification Register */ -+/* Module ID */ -+#define I2C_ID_ID_MASK 0x0000FF00 -+/* field offset */ -+#define I2C_ID_ID_OFFSET 8 -+/* Revision */ -+#define I2C_ID_REV_MASK 0x000000FF -+/* field offset */ -+#define I2C_ID_REV_OFFSET 0 -+ -+/* I2C Error Interrupt Request Source Status Register */ -+/* TXF_OFL */ -+#define I2C_ERR_IRQSS_TXF_OFL 0x00000008 -+/* TXF_UFL */ -+#define I2C_ERR_IRQSS_TXF_UFL 0x00000004 -+/* RXF_OFL */ -+#define I2C_ERR_IRQSS_RXF_OFL 0x00000002 -+/* RXF_UFL */ -+#define I2C_ERR_IRQSS_RXF_UFL 0x00000001 -+ -+/* I2C Bus Status Register */ -+/* Bus Status */ -+#define I2C_BUS_STAT_BS_MASK 0x00000003 -+/* I2C Bus is free. */ -+#define I2C_BUS_STAT_BS_FREE 0x00000000 -+/* -+ * The device is working as master and has claimed the control -+ * on the I2C-bus (busy master). -+ */ -+#define I2C_BUS_STAT_BS_BM 0x00000002 -+ -+/* I2C Interrupt Clear Register */ -+/* Clear */ -+#define I2C_ICR_BREQ_INT_CLR 0x00000008 -+/* Clear */ -+#define I2C_ICR_LBREQ_INT_CLR 0x00000004 -+ -+/* I2C RUN Control Register */ -+/* Enable */ -+#define I2C_RUN_CTRL_RUN_EN 0x00000001 -+ -+/* I2C Kernel Clock Control Register */ -+/* field offset */ -+#define I2C_CLC_RMC_OFFSET 8 -+/* Enable */ -+#define I2C_IMSC_I2C_P_INT_EN 0x00000020 -+/* Enable */ -+#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010 -+/* Enable */ -+#define I2C_IMSC_BREQ_INT_EN 0x00000008 -+/* Enable */ -+#define I2C_IMSC_LBREQ_INT_EN 0x00000004 -+ -+/* I2C Fractional Divider Configuration Register */ -+/* field offset */ -+#define I2C_FDIV_CFG_INC_OFFSET 16 -+/* field offset */ -+#define I2C_FDIV_CFG_DEC_OFFSET 0 -+ -+/* I2C Fractional Divider (highspeed mode) Configuration Register */ -+/* field offset */ -+#define I2C_FDIV_HIGH_CFG_INC_OFFSET 16 -+/* field offset */ -+#define I2C_FDIV_HIGH_CFG_DEC_OFFSET 0 -+ -+/* I2C Address Register */ -+/* Enable */ -+#define I2C_ADDR_CFG_SOPE_EN 0x00200000 -+/* Enable */ -+#define I2C_ADDR_CFG_SONA_EN 0x00100000 -+/* Enable */ -+#define I2C_ADDR_CFG_MnS_EN 0x00080000 -+ -+/* I2C Protocol Interrupt Request Source Status Register */ -+/* RX */ -+#define I2C_P_IRQSS_RX 0x00000040 -+/* TX_END */ -+#define I2C_P_IRQSS_TX_END 0x00000020 -+/* NACK */ -+#define I2C_P_IRQSS_NACK 0x00000010 -+/* AL */ -+#define I2C_P_IRQSS_AL 0x00000008 -+ -+/* I2C Raw Interrupt Status Register */ -+/* Read: Interrupt occurred. */ -+#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020 -+/* Read: Interrupt occurred. */ -+#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010 -+ -+/* I2C End Data Control Register */ -+/* -+ * Set End of Transmission - Note: Do not write '1' to this bit when bus is -+ * free. This will cause an abort after the first byte when a new transfer -+ * is started. -+ */ -+#define I2C_ENDD_CTRL_SETEND 0x00000002 -+/* TX FIFO Flow Control */ -+#define I2C_FIFO_CFG_TXFC 0x00020000 -+/* RX FIFO Flow Control */ -+#define I2C_FIFO_CFG_RXFC 0x00010000 -+/* Word aligned (character alignment of four characters) */ -+#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000 -+/* Word aligned (character alignment of four characters) */ -+#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200 -+/* 1 word */ -+#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000 -+/* 1 word */ -+#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000 -+ -+ -+/* I2C register structure */ -+struct gpon_reg_i2c { -+ /* I2C Kernel Clock Control Register */ -+ unsigned int clc; /* 0x00000000 */ -+ /* Reserved */ -+ unsigned int res_0; /* 0x00000004 */ -+ /* I2C Identification Register */ -+ unsigned int id; /* 0x00000008 */ -+ /* Reserved */ -+ unsigned int res_1; /* 0x0000000C */ -+ /* -+ * I2C RUN Control Register - This register enables and disables the I2C -+ * peripheral. Before enabling, the I2C has to be configured properly. -+ * After enabling no configuration is possible -+ */ -+ unsigned int run_ctrl; /* 0x00000010 */ -+ /* -+ * I2C End Data Control Register - This register is used to either turn -+ * around the data transmission direction or to address another slave -+ * without sending a stop condition. Also the software can stop the -+ * slave-transmitter by sending a not-accolade when working as -+ * master-receiver or even stop data transmission immediately when -+ * operating as master-transmitter. The writing to the bits of this -+ * control register is only effective when in MASTER RECEIVES BYTES, -+ * MASTER TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state -+ */ -+ unsigned int endd_ctrl; /* 0x00000014 */ -+ /* -+ * I2C Fractional Divider Configuration Register - These register is -+ * used to program the fractional divider of the I2C bus. Before the -+ * peripheral is switched on by setting the RUN-bit the two (fixed) -+ * values for the two operating frequencies are programmed into these -+ * (configuration) registers. The Register FDIV_HIGH_CFG has the same -+ * layout as I2C_FDIV_CFG. -+ */ -+ unsigned int fdiv_cfg; /* 0x00000018 */ -+ /* -+ * I2C Fractional Divider (highspeed mode) Configuration Register -+ * These register is used to program the fractional divider of the I2C -+ * bus. Before the peripheral is switched on by setting the RUN-bit the -+ * two (fixed) values for the two operating frequencies are programmed -+ * into these (configuration) registers. The Register FDIV_CFG has the -+ * same layout as I2C_FDIV_CFG. -+ */ -+ unsigned int fdiv_high_cfg; /* 0x0000001C */ -+ /* I2C Address Configuration Register */ -+ unsigned int addr_cfg; /* 0x00000020 */ -+ /* -+ * I2C Bus Status Register - This register gives a status information -+ * of the I2C. This additional information can be used by the software -+ * to start proper actions. -+ */ -+ unsigned int bus_stat; /* 0x00000024 */ -+ /* I2C FIFO Configuration Register */ -+ unsigned int fifo_cfg; /* 0x00000028 */ -+ /* I2C Maximum Received Packet Size Register */ -+ unsigned int mrps_ctrl; /* 0x0000002C */ -+ /* I2C Received Packet Size Status Register */ -+ unsigned int rps_stat; /* 0x00000030 */ -+ /* I2C Transmit Packet Size Register */ -+ unsigned int tps_ctrl; /* 0x00000034 */ -+ /* I2C Filled FIFO Stages Status Register */ -+ unsigned int ffs_stat; /* 0x00000038 */ -+ /* Reserved */ -+ unsigned int res_2; /* 0x0000003C */ -+ /* I2C Timing Configuration Register */ -+ unsigned int tim_cfg; /* 0x00000040 */ -+ /* Reserved */ -+ unsigned int res_3[7]; /* 0x00000044 */ -+ /* I2C Error Interrupt Request Source Mask Register */ -+ unsigned int err_irqsm; /* 0x00000060 */ -+ /* I2C Error Interrupt Request Source Status Register */ -+ unsigned int err_irqss; /* 0x00000064 */ -+ /* I2C Error Interrupt Request Source Clear Register */ -+ unsigned int err_irqsc; /* 0x00000068 */ -+ /* Reserved */ -+ unsigned int res_4; /* 0x0000006C */ -+ /* I2C Protocol Interrupt Request Source Mask Register */ -+ unsigned int p_irqsm; /* 0x00000070 */ -+ /* I2C Protocol Interrupt Request Source Status Register */ -+ unsigned int p_irqss; /* 0x00000074 */ -+ /* I2C Protocol Interrupt Request Source Clear Register */ -+ unsigned int p_irqsc; /* 0x00000078 */ -+ /* Reserved */ -+ unsigned int res_5; /* 0x0000007C */ -+ /* I2C Raw Interrupt Status Register */ -+ unsigned int ris; /* 0x00000080 */ -+ /* I2C Interrupt Mask Control Register */ -+ unsigned int imsc; /* 0x00000084 */ -+ /* I2C Masked Interrupt Status Register */ -+ unsigned int mis; /* 0x00000088 */ -+ /* I2C Interrupt Clear Register */ -+ unsigned int icr; /* 0x0000008C */ -+ /* I2C Interrupt Set Register */ -+ unsigned int isr; /* 0x00000090 */ -+ /* I2C DMA Enable Register */ -+ unsigned int dmae; /* 0x00000094 */ -+ /* Reserved */ -+ unsigned int res_6[8154]; /* 0x00000098 */ -+ /* I2C Transmit Data Register */ -+ unsigned int txd; /* 0x00008000 */ -+ /* Reserved */ -+ unsigned int res_7[4095]; /* 0x00008004 */ -+ /* I2C Receive Data Register */ -+ unsigned int rxd; /* 0x0000C000 */ -+ /* Reserved */ -+ unsigned int res_8[4095]; /* 0x0000C004 */ -+}; -+ -+/* mapping for access macros */ -+#define i2c ((struct gpon_reg_i2c *)priv->membase) -+#define reg_r32(reg) __raw_readl(reg) -+#define reg_w32(val, reg) __raw_writel(val, reg) -+#define reg_w32_mask(clear, set, reg) \ -+ reg_w32((reg_r32(reg) & ~(clear)) | (set), reg) -+#define reg_r32_table(reg, idx) reg_r32(&((uint32_t *)®)[idx]) -+#define reg_w32_table(val, reg, idx) reg_w32(val, &((uint32_t *)®)[idx]) -+ -+#define i2c_r32(reg) reg_r32(&i2c->reg) -+#define i2c_w32(val, reg) reg_w32(val, &i2c->reg) -+#define i2c_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &i2c->reg) -+ -+#define DRV_NAME "i2c-falcon" -+#define DRV_VERSION "1.01" -+ -+#define FALCON_I2C_BUSY_TIMEOUT 20 /* ms */ -+ -+#ifdef DEBUG -+#define FALCON_I2C_XFER_TIMEOUT (25 * HZ) -+#else -+#define FALCON_I2C_XFER_TIMEOUT HZ -+#endif -+#if defined(DEBUG) && 0 -+#define PRINTK(arg...) pr_info(arg) -+#else -+#define PRINTK(arg...) do {} while (0) -+#endif -+ -+#define FALCON_I2C_IMSC_DEFAULT_MASK (I2C_IMSC_I2C_P_INT_EN | \ -+ I2C_IMSC_I2C_ERR_INT_EN) -+ -+#define FALCON_I2C_ARB_LOST (1 << 0) -+#define FALCON_I2C_NACK (1 << 1) -+#define FALCON_I2C_RX_UFL (1 << 2) -+#define FALCON_I2C_RX_OFL (1 << 3) -+#define FALCON_I2C_TX_UFL (1 << 4) -+#define FALCON_I2C_TX_OFL (1 << 5) -+ -+struct falcon_i2c { -+ struct mutex mutex; -+ -+ enum { -+ FALCON_I2C_MODE_100 = 1, -+ FALCON_I2C_MODE_400 = 2, -+ FALCON_I2C_MODE_3400 = 3 -+ } mode; /* current speed mode */ -+ -+ struct clk *clk; /* clock input for i2c hardware block */ -+ struct gpon_reg_i2c __iomem *membase; /* base of mapped registers */ -+ int irq_lb, irq_b, irq_err, irq_p; /* last burst, burst, error, -+ protocol IRQs */ -+ -+ struct i2c_adapter adap; -+ struct device *dev; -+ -+ struct completion cmd_complete; -+ -+ /* message transfer data */ -+ /* current message */ -+ struct i2c_msg *current_msg; -+ /* number of messages to handle */ -+ int msgs_num; -+ /* current buffer */ -+ u8 *msg_buf; -+ /* remaining length of current buffer */ -+ u32 msg_buf_len; -+ /* error status of the current transfer */ -+ int msg_err; -+ -+ /* master status codes */ -+ enum { -+ STATUS_IDLE, -+ STATUS_ADDR, /* address phase */ -+ STATUS_WRITE, -+ STATUS_READ, -+ STATUS_READ_END, -+ STATUS_STOP -+ } status; -+}; -+ -+static irqreturn_t falcon_i2c_isr(int irq, void *dev_id); -+ -+static inline void enable_burst_irq(struct falcon_i2c *priv) -+{ -+ i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc); -+} -+static inline void disable_burst_irq(struct falcon_i2c *priv) -+{ -+ i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc); -+} -+ -+static void prepare_msg_send_addr(struct falcon_i2c *priv) -+{ -+ struct i2c_msg *msg = priv->current_msg; -+ int rd = !!(msg->flags & I2C_M_RD); -+ u16 addr = msg->addr; -+ -+ /* new i2c_msg */ -+ priv->msg_buf = msg->buf; -+ priv->msg_buf_len = msg->len; -+ if (rd) -+ priv->status = STATUS_READ; -+ else -+ priv->status = STATUS_WRITE; -+ -+ /* send slave address */ -+ if (msg->flags & I2C_M_TEN) { -+ i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd); -+ i2c_w32(addr & 0xff, txd); -+ } else -+ i2c_w32((addr & 0x7f) << 1 | rd, txd); -+} -+ -+static void set_tx_len(struct falcon_i2c *priv) -+{ -+ struct i2c_msg *msg = priv->current_msg; -+ int len = (msg->flags & I2C_M_TEN) ? 2 : 1; -+ -+ PRINTK("set_tx_len %cX\n", (msg->flags & I2C_M_RD) ? ('R') : ('T')); -+ -+ priv->status = STATUS_ADDR; -+ -+ if (!(msg->flags & I2C_M_RD)) { -+ len += msg->len; -+ } else { -+ /* set maximum received packet size (before rx int!) */ -+ i2c_w32(msg->len, mrps_ctrl); -+ } -+ i2c_w32(len, tps_ctrl); -+ enable_burst_irq(priv); -+} -+ -+static int falcon_i2c_hw_init(struct i2c_adapter *adap) -+{ -+ struct falcon_i2c *priv = i2c_get_adapdata(adap); -+ -+ /* disable bus */ -+ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); -+ -+#ifndef DEBUG -+ /* set normal operation clock divider */ -+ i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc); -+#else -+ /* for debugging a higher divider value! */ -+ i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc); -+#endif -+ -+ /* set frequency */ -+ if (priv->mode == FALCON_I2C_MODE_100) { -+ dev_dbg(priv->dev, "set standard mode (100 kHz)\n"); -+ i2c_w32(0, fdiv_high_cfg); -+ i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET) | -+ (499 << I2C_FDIV_CFG_DEC_OFFSET), -+ fdiv_cfg); -+ } else if (priv->mode == FALCON_I2C_MODE_400) { -+ dev_dbg(priv->dev, "set fast mode (400 kHz)\n"); -+ i2c_w32(0, fdiv_high_cfg); -+ i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET) | -+ (124 << I2C_FDIV_CFG_DEC_OFFSET), -+ fdiv_cfg); -+ } else if (priv->mode == FALCON_I2C_MODE_3400) { -+ dev_dbg(priv->dev, "set high mode (3.4 MHz)\n"); -+ i2c_w32(0, fdiv_cfg); -+ /* TODO recalculate value for 100MHz input */ -+ i2c_w32((41 << I2C_FDIV_HIGH_CFG_INC_OFFSET) | -+ (152 << I2C_FDIV_HIGH_CFG_DEC_OFFSET), -+ fdiv_high_cfg); -+ } else { -+ dev_warn(priv->dev, "unknown mode\n"); -+ return -ENODEV; -+ } -+ -+ /* configure fifo */ -+ i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */ -+ I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */ -+ I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */ -+ I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */ -+ I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */ -+ I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */ -+ fifo_cfg); -+ -+ /* configure address */ -+ i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data -+ in the fifo */ -+ I2C_ADDR_CFG_SONA_EN | /* generate stop when NA received */ -+ I2C_ADDR_CFG_MnS_EN | /* we are master device */ -+ 0, /* our slave address (not used!) */ -+ addr_cfg); -+ -+ /* enable bus */ -+ i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl); -+ -+ return 0; -+} -+ -+static int falcon_i2c_wait_bus_not_busy(struct falcon_i2c *priv) -+{ -+ int timeout = FALCON_I2C_BUSY_TIMEOUT; -+ -+ while ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) -+ != I2C_BUS_STAT_BS_FREE) { -+ if (timeout <= 0) { -+ dev_warn(priv->dev, "timeout waiting for bus ready\n"); -+ return -ETIMEDOUT; -+ } -+ timeout--; -+ mdelay(1); -+ } -+ -+ return 0; -+} -+ -+static void falcon_i2c_tx(struct falcon_i2c *priv, int last) -+{ -+ if (priv->msg_buf_len && priv->msg_buf) { -+ i2c_w32(*priv->msg_buf, txd); -+ -+ if (--priv->msg_buf_len) -+ priv->msg_buf++; -+ else -+ priv->msg_buf = NULL; -+ } else -+ last = 1; -+ -+ if (last) -+ disable_burst_irq(priv); -+} -+ -+static void falcon_i2c_rx(struct falcon_i2c *priv, int last) -+{ -+ u32 fifo_stat, timeout; -+ if (priv->msg_buf_len && priv->msg_buf) { -+ timeout = 5000000; -+ do { -+ fifo_stat = i2c_r32(ffs_stat); -+ } while (!fifo_stat && --timeout); -+ if (!timeout) { -+ last = 1; -+ PRINTK("\nrx timeout\n"); -+ goto err; -+ } -+ while (fifo_stat) { -+ *priv->msg_buf = i2c_r32(rxd); -+ if (--priv->msg_buf_len) -+ priv->msg_buf++; -+ else { -+ priv->msg_buf = NULL; -+ last = 1; -+ break; -+ } -+ #if 0 -+ fifo_stat = i2c_r32(ffs_stat); -+ #else -+ /* do not read more than burst size, otherwise no "last -+ burst" is generated and the transaction is blocked! */ -+ fifo_stat = 0; -+ #endif -+ } -+ } else { -+ last = 1; -+ } -+err: -+ if (last) { -+ disable_burst_irq(priv); -+ -+ if (priv->status == STATUS_READ_END) { -+ /* do the STATUS_STOP and complete() here, as sometimes -+ the tx_end is already seen before this is finished */ -+ priv->status = STATUS_STOP; -+ complete(&priv->cmd_complete); -+ } else { -+ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); -+ priv->status = STATUS_READ_END; -+ } -+ } -+} -+ -+static void falcon_i2c_xfer_init(struct falcon_i2c *priv) -+{ -+ /* enable interrupts */ -+ i2c_w32(FALCON_I2C_IMSC_DEFAULT_MASK, imsc); -+ -+ /* trigger transfer of first msg */ -+ set_tx_len(priv); -+} -+ -+static void dump_msgs(struct i2c_msg msgs[], int num, int rx) -+{ -+#if defined(DEBUG) -+ int i, j; -+ pr_info("Messages %d %s\n", num, rx ? "out" : "in"); -+ for (i = 0; i < num; i++) { -+ pr_info("%2d %cX Msg(%d) addr=0x%X: ", i, -+ (msgs[i].flags & I2C_M_RD) ? ('R') : ('T'), -+ msgs[i].len, msgs[i].addr); -+ if (!(msgs[i].flags & I2C_M_RD) || rx) { -+ for (j = 0; j < msgs[i].len; j++) -+ printk("%02X ", msgs[i].buf[j]); -+ } -+ printk("\n"); -+ } -+#endif -+} -+ -+static void falcon_i2c_release_bus(struct falcon_i2c *priv) -+{ -+ if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM) -+ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); -+} -+ -+static int falcon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], -+ int num) -+{ -+ struct falcon_i2c *priv = i2c_get_adapdata(adap); -+ int ret; -+ -+ dev_dbg(priv->dev, "xfer %u messages\n", num); -+ dump_msgs(msgs, num, 0); -+ -+ mutex_lock(&priv->mutex); -+ -+ INIT_COMPLETION(priv->cmd_complete); -+ priv->current_msg = msgs; -+ priv->msgs_num = num; -+ priv->msg_err = 0; -+ priv->status = STATUS_IDLE; -+ -+ /* wait for the bus to become ready */ -+ ret = falcon_i2c_wait_bus_not_busy(priv); -+ if (ret) -+ goto done; -+ -+ while (priv->msgs_num) { -+ /* start the transfers */ -+ falcon_i2c_xfer_init(priv); -+ -+ /* wait for transfers to complete */ -+ ret = wait_for_completion_interruptible_timeout( -+ &priv->cmd_complete, FALCON_I2C_XFER_TIMEOUT); -+ if (ret == 0) { -+ dev_err(priv->dev, "controller timed out\n"); -+ falcon_i2c_hw_init(adap); -+ ret = -ETIMEDOUT; -+ goto done; -+ } else if (ret < 0) -+ goto done; -+ -+ if (priv->msg_err) { -+ if (priv->msg_err & FALCON_I2C_NACK) -+ ret = -ENXIO; -+ else -+ ret = -EREMOTEIO; -+ goto done; -+ } -+ if (--priv->msgs_num) -+ priv->current_msg++; -+ } -+ /* no error? */ -+ ret = num; -+ -+done: -+ falcon_i2c_release_bus(priv); -+ -+ mutex_unlock(&priv->mutex); -+ -+ if (ret >= 0) -+ dump_msgs(msgs, num, 1); -+ -+ PRINTK("XFER ret %d\n", ret); -+ return ret; -+} -+ -+static irqreturn_t falcon_i2c_isr_burst(int irq, void *dev_id) -+{ -+ struct falcon_i2c *priv = dev_id; -+ struct i2c_msg *msg = priv->current_msg; -+ int last = (irq == priv->irq_lb); -+ -+ if (last) -+ PRINTK("LB "); -+ else -+ PRINTK("B "); -+ -+ if (msg->flags & I2C_M_RD) { -+ switch (priv->status) { -+ case STATUS_ADDR: -+ PRINTK("X"); -+ prepare_msg_send_addr(priv); -+ disable_burst_irq(priv); -+ break; -+ case STATUS_READ: -+ case STATUS_READ_END: -+ PRINTK("R"); -+ falcon_i2c_rx(priv, last); -+ break; -+ default: -+ disable_burst_irq(priv); -+ PRINTK("Status R %d\n", priv->status); -+ break; -+ } -+ } else { -+ switch (priv->status) { -+ case STATUS_ADDR: -+ PRINTK("x"); -+ prepare_msg_send_addr(priv); -+ break; -+ case STATUS_WRITE: -+ PRINTK("w"); -+ falcon_i2c_tx(priv, last); -+ break; -+ default: -+ disable_burst_irq(priv); -+ PRINTK("Status W %d\n", priv->status); -+ break; -+ } -+ } -+ -+ i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr); -+ return IRQ_HANDLED; -+} -+ -+static void falcon_i2c_isr_prot(struct falcon_i2c *priv) -+{ -+ u32 i_pro = i2c_r32(p_irqss); -+ -+ PRINTK("i2c-p"); -+ -+ /* not acknowledge */ -+ if (i_pro & I2C_P_IRQSS_NACK) { -+ priv->msg_err |= FALCON_I2C_NACK; -+ PRINTK(" nack"); -+ } -+ -+ /* arbitration lost */ -+ if (i_pro & I2C_P_IRQSS_AL) { -+ priv->msg_err |= FALCON_I2C_ARB_LOST; -+ PRINTK(" arb-lost"); -+ } -+ /* tx -> rx switch */ -+ if (i_pro & I2C_P_IRQSS_RX) -+ PRINTK(" rx"); -+ -+ /* tx end */ -+ if (i_pro & I2C_P_IRQSS_TX_END) -+ PRINTK(" txend"); -+ PRINTK("\n"); -+ -+ if (!priv->msg_err) { -+ /* tx -> rx switch */ -+ if (i_pro & I2C_P_IRQSS_RX) { -+ priv->status = STATUS_READ; -+ enable_burst_irq(priv); -+ } -+ if (i_pro & I2C_P_IRQSS_TX_END) { -+ if (priv->status == STATUS_READ) -+ priv->status = STATUS_READ_END; -+ else { -+ disable_burst_irq(priv); -+ priv->status = STATUS_STOP; -+ } -+ } -+ } -+ -+ i2c_w32(i_pro, p_irqsc); -+} -+ -+static irqreturn_t falcon_i2c_isr(int irq, void *dev_id) -+{ -+ u32 i_raw, i_err = 0; -+ struct falcon_i2c *priv = dev_id; -+ -+ i_raw = i2c_r32(mis); -+ PRINTK("i_raw 0x%08X\n", i_raw); -+ -+ /* error interrupt */ -+ if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) { -+ i_err = i2c_r32(err_irqss); -+ PRINTK("i_err 0x%08X bus_stat 0x%04X\n", -+ i_err, i2c_r32(bus_stat)); -+ -+ /* tx fifo overflow (8) */ -+ if (i_err & I2C_ERR_IRQSS_TXF_OFL) -+ priv->msg_err |= FALCON_I2C_TX_OFL; -+ -+ /* tx fifo underflow (4) */ -+ if (i_err & I2C_ERR_IRQSS_TXF_UFL) -+ priv->msg_err |= FALCON_I2C_TX_UFL; -+ -+ /* rx fifo overflow (2) */ -+ if (i_err & I2C_ERR_IRQSS_RXF_OFL) -+ priv->msg_err |= FALCON_I2C_RX_OFL; -+ -+ /* rx fifo underflow (1) */ -+ if (i_err & I2C_ERR_IRQSS_RXF_UFL) -+ priv->msg_err |= FALCON_I2C_RX_UFL; -+ -+ i2c_w32(i_err, err_irqsc); -+ } -+ -+ /* protocol interrupt */ -+ if (i_raw & I2C_RIS_I2C_P_INT_INTOCC) -+ falcon_i2c_isr_prot(priv); -+ -+ if ((priv->msg_err) || (priv->status == STATUS_STOP)) -+ complete(&priv->cmd_complete); -+ -+ return IRQ_HANDLED; -+} -+ -+static u32 falcon_i2c_functionality(struct i2c_adapter *adap) -+{ -+ return I2C_FUNC_I2C | -+ I2C_FUNC_10BIT_ADDR | -+ I2C_FUNC_SMBUS_EMUL; -+} -+ -+static struct i2c_algorithm falcon_i2c_algorithm = { -+ .master_xfer = falcon_i2c_xfer, -+ .functionality = falcon_i2c_functionality, -+}; -+ -+static int __devinit falcon_i2c_probe(struct platform_device *pdev) -+{ -+ int ret = 0; -+ struct falcon_i2c *priv; -+ struct i2c_adapter *adap; -+ struct resource *mmres, *ioarea, -+ *irqres_lb, *irqres_b, *irqres_err, *irqres_p; -+ struct clk *clk; -+ -+ dev_dbg(&pdev->dev, "probing\n"); -+ -+ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ irqres_lb = platform_get_resource_byname(pdev, IORESOURCE_IRQ, -+ "i2c_lb"); -+ irqres_b = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_b"); -+ irqres_err = platform_get_resource_byname(pdev, IORESOURCE_IRQ, -+ "i2c_err"); -+ irqres_p = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_p"); -+ -+ if (!mmres || !irqres_lb || !irqres_b || !irqres_err || !irqres_p) { -+ dev_err(&pdev->dev, "no resources\n"); -+ return -ENODEV; -+ } -+ -+ clk = clk_get_fpi(); -+ if (IS_ERR(clk)) { -+ dev_err(&pdev->dev, "failed to get fpi clk\n"); -+ return -ENOENT; -+ } -+ -+ if (clk_get_rate(clk) != 100000000) { -+ dev_err(&pdev->dev, "input clock is not 100MHz\n"); -+ return -ENOENT; -+ } -+ clk = clk_get(&pdev->dev, NULL); -+ if (IS_ERR(clk)) { -+ dev_err(&pdev->dev, "failed to get i2c clk\n"); -+ return -ENOENT; -+ } -+ -+ /* allocate private data */ -+ priv = kzalloc(sizeof(*priv), GFP_KERNEL); -+ if (!priv) { -+ dev_err(&pdev->dev, "can't allocate private data\n"); -+ return -ENOMEM; -+ } -+ -+ adap = &priv->adap; -+ i2c_set_adapdata(adap, priv); -+ adap->owner = THIS_MODULE; -+ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; -+ strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name)); -+ adap->algo = &falcon_i2c_algorithm; -+ -+ priv->mode = FALCON_I2C_MODE_100; -+ priv->clk = clk; -+ priv->dev = &pdev->dev; -+ -+ init_completion(&priv->cmd_complete); -+ mutex_init(&priv->mutex); -+ -+ if (ltq_gpio_request(&pdev->dev, 107, 0, 0, DRV_NAME":sda") || -+ ltq_gpio_request(&pdev->dev, 108, 0, 0, DRV_NAME":scl")) -+ { -+ dev_err(&pdev->dev, "I2C gpios not available\n"); -+ ret = -ENXIO; -+ goto err_free_priv; -+ } -+ -+ ioarea = request_mem_region(mmres->start, resource_size(mmres), -+ pdev->name); -+ -+ if (ioarea == NULL) { -+ dev_err(&pdev->dev, "I2C region already claimed\n"); -+ ret = -ENXIO; -+ goto err_free_gpio; -+ } -+ -+ /* map memory */ -+ priv->membase = ioremap_nocache(mmres->start & ~KSEG1, -+ resource_size(mmres)); -+ if (priv->membase == NULL) { -+ ret = -ENOMEM; -+ goto err_release_region; -+ } -+ -+ priv->irq_lb = irqres_lb->start; -+ ret = request_irq(priv->irq_lb, falcon_i2c_isr_burst, IRQF_DISABLED, -+ irqres_lb->name, priv); -+ if (ret) { -+ dev_err(&pdev->dev, "can't get last burst IRQ %d\n", -+ irqres_lb->start); -+ ret = -ENODEV; -+ goto err_unmap_mem; -+ } -+ -+ priv->irq_b = irqres_b->start; -+ ret = request_irq(priv->irq_b, falcon_i2c_isr_burst, IRQF_DISABLED, -+ irqres_b->name, priv); -+ if (ret) { -+ dev_err(&pdev->dev, "can't get burst IRQ %d\n", -+ irqres_b->start); -+ ret = -ENODEV; -+ goto err_free_lb_irq; -+ } -+ -+ priv->irq_err = irqres_err->start; -+ ret = request_irq(priv->irq_err, falcon_i2c_isr, IRQF_DISABLED, -+ irqres_err->name, priv); -+ if (ret) { -+ dev_err(&pdev->dev, "can't get error IRQ %d\n", -+ irqres_err->start); -+ ret = -ENODEV; -+ goto err_free_b_irq; -+ } -+ -+ priv->irq_p = irqres_p->start; -+ ret = request_irq(priv->irq_p, falcon_i2c_isr, IRQF_DISABLED, -+ irqres_p->name, priv); -+ if (ret) { -+ dev_err(&pdev->dev, "can't get protocol IRQ %d\n", -+ irqres_p->start); -+ ret = -ENODEV; -+ goto err_free_err_irq; -+ } -+ -+ dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase); -+ dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres_lb->start, -+ irqres_b->start, irqres_err->start, irqres_p->start); -+ -+ /* add our adapter to the i2c stack */ -+ ret = i2c_add_numbered_adapter(adap); -+ if (ret) { -+ dev_err(&pdev->dev, "can't register I2C adapter\n"); -+ goto err_free_p_irq; -+ } -+ -+ platform_set_drvdata(pdev, priv); -+ i2c_set_adapdata(adap, priv); -+ -+ /* print module version information */ -+ dev_dbg(&pdev->dev, "module id=%u revision=%u\n", -+ (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET, -+ (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET); -+ -+ /* initialize HW */ -+ ret = falcon_i2c_hw_init(adap); -+ if (ret) { -+ dev_err(&pdev->dev, "can't configure adapter\n"); -+ goto err_remove_adapter; -+ } -+ -+ dev_info(&pdev->dev, "version %s\n", DRV_VERSION); -+ -+ return 0; -+ -+err_remove_adapter: -+ i2c_del_adapter(adap); -+ platform_set_drvdata(pdev, NULL); -+ -+err_free_p_irq: -+ free_irq(priv->irq_p, priv); -+ -+err_free_err_irq: -+ free_irq(priv->irq_err, priv); -+ -+err_free_b_irq: -+ free_irq(priv->irq_b, priv); -+ -+err_free_lb_irq: -+ free_irq(priv->irq_lb, priv); -+ -+err_unmap_mem: -+ iounmap(priv->membase); -+ -+err_release_region: -+ release_mem_region(mmres->start, resource_size(mmres)); -+ -+err_free_gpio: -+ gpio_free(108); -+ gpio_free(107); -+ -+err_free_priv: -+ kfree(priv); -+ -+ return ret; -+} -+ -+static int __devexit falcon_i2c_remove(struct platform_device *pdev) -+{ -+ struct falcon_i2c *priv = platform_get_drvdata(pdev); -+ struct resource *mmres; -+ -+ /* disable bus */ -+ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); -+ -+ /* remove driver */ -+ platform_set_drvdata(pdev, NULL); -+ i2c_del_adapter(&priv->adap); -+ -+ free_irq(priv->irq_lb, priv); -+ free_irq(priv->irq_b, priv); -+ free_irq(priv->irq_err, priv); -+ free_irq(priv->irq_p, priv); -+ -+ iounmap(priv->membase); -+ -+ gpio_free(108); -+ gpio_free(107); -+ -+ kfree(priv); -+ -+ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ release_mem_region(mmres->start, resource_size(mmres)); -+ -+ dev_dbg(&pdev->dev, "removed\n"); -+ -+ return 0; -+} -+ -+static struct platform_driver falcon_i2c_driver = { -+ .probe = falcon_i2c_probe, -+ .remove = __devexit_p(falcon_i2c_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init falcon_i2c_init(void) -+{ -+ int ret; -+ -+ ret = platform_driver_register(&falcon_i2c_driver); -+ -+ if (ret) -+ pr_debug(DRV_NAME ": can't register platform driver\n"); -+ -+ return ret; -+} -+ -+static void __exit falcon_i2c_exit(void) -+{ -+ platform_driver_unregister(&falcon_i2c_driver); -+} -+ -+module_init(falcon_i2c_init); -+module_exit(falcon_i2c_exit); -+ -+MODULE_DESCRIPTION("Lantiq FALC(tm) ON - I2C bus adapter"); -+MODULE_ALIAS("platform:" DRV_NAME); -+MODULE_LICENSE("GPL"); -+MODULE_VERSION(DRV_VERSION); diff --git a/target/linux/lantiq/patches-3.3/0037-MIPS-lantiq-add-xway-nand-driver.patch b/target/linux/lantiq/patches-3.3/0037-MIPS-lantiq-add-xway-nand-driver.patch deleted file mode 100644 index 835c51e6a2..0000000000 --- a/target/linux/lantiq/patches-3.3/0037-MIPS-lantiq-add-xway-nand-driver.patch +++ /dev/null @@ -1,294 +0,0 @@ -From 50a9d37efdfa502fafe48a1de604cd5d84a0d5e9 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sat, 27 Aug 2011 20:08:14 +0200 -Subject: [PATCH 37/70] MIPS: lantiq: add xway nand driver - -This patch adds a nand driver for XWAY SoCs. The patch makes use of the -plat_nand driver. As with the EBU NOR driver merged in 3.0, we have the -endianess swap problem on read. To workaround this problem we make the -read_byte() callback available via the plat_nand driver causing the nand -layer to do byte reads. - -Signed-off-by: John Crispin - -TODO : memory ranges - cs lines - plat dev - ebu2 and not ebu1 ? ---- - .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 2 + - arch/mips/lantiq/xway/Makefile | 2 +- - arch/mips/lantiq/xway/devices.h | 1 + - arch/mips/lantiq/xway/nand.c | 216 ++++++++++++++++++++ - drivers/mtd/nand/plat_nand.c | 1 + - include/linux/mtd/nand.h | 1 + - 6 files changed, 222 insertions(+), 1 deletions(-) - create mode 100644 arch/mips/lantiq/xway/nand.c - ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -@@ -145,6 +145,8 @@ - /* register access macros for EBU and CGU */ - #define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) - #define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) -+#define ltq_ebu_w32_mask(x, y, z) \ -+ ltq_w32_mask(x, y, ltq_ebu_membase + (z)) - #define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y)) - #define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x)) - ---- a/arch/mips/lantiq/xway/Makefile -+++ b/arch/mips/lantiq/xway/Makefile -@@ -1,4 +1,4 @@ --obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o -+obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o - - obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o - obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o ---- a/arch/mips/lantiq/xway/devices.h -+++ b/arch/mips/lantiq/xway/devices.h -@@ -16,5 +16,6 @@ extern void ltq_register_gpio(void); - extern void ltq_register_gpio_stp(void); - extern void ltq_register_ase_asc(void); - extern void ltq_register_etop(struct ltq_eth_data *eth); -+extern void xway_register_nand(struct mtd_partition *parts, int count); - - #endif ---- /dev/null -+++ b/arch/mips/lantiq/xway/nand.c -@@ -0,0 +1,216 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2010 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include "devices.h" -+ -+/* nand registers */ -+#define LTQ_EBU_NAND_WAIT 0xB4 -+#define LTQ_EBU_NAND_ECC0 0xB8 -+#define LTQ_EBU_NAND_ECC_AC 0xBC -+#define LTQ_EBU_NAND_CON 0xB0 -+#define LTQ_EBU_ADDSEL1 0x24 -+ -+/* gpio definitions */ -+#define PIN_ALE 13 -+#define PIN_CLE 24 -+#define PIN_CS1 23 -+#define PIN_RDY 48 /* NFLASH_READY */ -+#define PIN_RD 49 /* NFLASH_READ_N */ -+ -+#define NAND_CMD_ALE (1 << 2) -+#define NAND_CMD_CLE (1 << 3) -+#define NAND_CMD_CS (1 << 4) -+#define NAND_WRITE_CMD_RESET 0xff -+#define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE) -+#define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE) -+#define NAND_WRITE_DATA (NAND_CMD_CS) -+#define NAND_READ_DATA (NAND_CMD_CS) -+#define NAND_WAIT_WR_C (1 << 3) -+#define NAND_WAIT_RD (0x1) -+ -+#define ADDSEL1_MASK(x) (x << 4) -+#define ADDSEL1_REGEN 1 -+#define BUSCON1_SETUP (1 << 22) -+#define BUSCON1_BCGEN_RES (0x3 << 12) -+#define BUSCON1_WAITWRC2 (2 << 8) -+#define BUSCON1_WAITRDC2 (2 << 6) -+#define BUSCON1_HOLDC1 (1 << 4) -+#define BUSCON1_RECOVC1 (1 << 2) -+#define BUSCON1_CMULT4 1 -+#define NAND_CON_NANDM 1 -+#define NAND_CON_CSMUX (1 << 1) -+#define NAND_CON_CS_P (1 << 4) -+#define NAND_CON_SE_P (1 << 5) -+#define NAND_CON_WP_P (1 << 6) -+#define NAND_CON_PRE_P (1 << 7) -+#define NAND_CON_IN_CS0 0 -+#define NAND_CON_OUT_CS0 0 -+#define NAND_CON_IN_CS1 (1 << 8) -+#define NAND_CON_OUT_CS1 (1 << 10) -+#define NAND_CON_CE (1 << 20) -+ -+#define NAND_BASE_ADDRESS (KSEG1 | 0x14000000) -+ -+static const char *part_probes[] = { "cmdlinepart", NULL }; -+ -+static void xway_select_chip(struct mtd_info *mtd, int chip) -+{ -+ switch (chip) { -+ case -1: -+ ltq_ebu_w32_mask(NAND_CON_CE, 0, LTQ_EBU_NAND_CON); -+ ltq_ebu_w32_mask(NAND_CON_NANDM, 0, LTQ_EBU_NAND_CON); -+ break; -+ case 0: -+ ltq_ebu_w32_mask(0, NAND_CON_NANDM, LTQ_EBU_NAND_CON); -+ ltq_ebu_w32_mask(0, NAND_CON_CE, LTQ_EBU_NAND_CON); -+ /* reset the nand chip */ -+ while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) -+ ; -+ ltq_w32(NAND_WRITE_CMD_RESET, -+ ((u32 *) (NAND_BASE_ADDRESS | NAND_WRITE_CMD))); -+ break; -+ default: -+ BUG(); -+ } -+} -+ -+static void xway_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl) -+{ -+ struct nand_chip *this = mtd->priv; -+ -+ if (ctrl & NAND_CTRL_CHANGE) { -+ if (ctrl & NAND_CLE) -+ this->IO_ADDR_W = (void __iomem *) -+ (NAND_BASE_ADDRESS | NAND_WRITE_CMD); -+ else if (ctrl & NAND_ALE) -+ this->IO_ADDR_W = (void __iomem *) -+ (NAND_BASE_ADDRESS | NAND_WRITE_ADDR); -+ } -+ -+ if (data != NAND_CMD_NONE) { -+ *(volatile u8*) ((u32) this->IO_ADDR_W) = data; -+ while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) -+ ; -+ } -+} -+ -+static int xway_dev_ready(struct mtd_info *mtd) -+{ -+ return ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_RD; -+} -+ -+void nand_write(unsigned int addr, unsigned int val) -+{ -+ ltq_w32(val, ((u32 *) (NAND_BASE_ADDRESS | addr))); -+ while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) -+ ; -+} -+ -+unsigned char xway_read_byte(struct mtd_info *mtd) -+{ -+ return ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA))); -+} -+ -+static void xway_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) -+{ -+ int i; -+ -+ for (i = 0; i < len; i++) -+ { -+ unsigned char res8 = ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA))); -+ buf[i] = res8; -+ } -+} -+ -+static void xway_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) -+{ -+ int i; -+ -+ for (i = 0; i < len; i++) -+ { -+ ltq_w8(buf[i], ((u32*)(NAND_BASE_ADDRESS | (NAND_WRITE_DATA)))); -+ while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0); -+ } -+} -+ -+int xway_probe(struct platform_device *pdev) -+{ -+ /* might need this later ? -+ ltq_gpio_request(PIN_CS1, 2, 1, "NAND_CS1"); -+ */ -+ ltq_gpio_request(&pdev->dev, PIN_CLE, 2, 1, "NAND_CLE"); -+ ltq_gpio_request(&pdev->dev, PIN_ALE, 2, 1, "NAND_ALE"); -+ if (ltq_is_ar9() || ltq_is_vr9()) { -+ ltq_gpio_request(&pdev->dev, PIN_RDY, 2, 0, "NAND_BSY"); -+ ltq_gpio_request(&pdev->dev, PIN_RD, 2, 1, "NAND_RD"); -+ } -+ -+ ltq_ebu_w32((NAND_BASE_ADDRESS & 0x1fffff00) -+ | ADDSEL1_MASK(3) | ADDSEL1_REGEN, LTQ_EBU_ADDSEL1); -+ -+ ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2 -+ | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1 -+ | BUSCON1_CMULT4, LTQ_EBU_BUSCON1); -+ -+ ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P -+ | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P -+ | NAND_CON_IN_CS0 | NAND_CON_OUT_CS0, LTQ_EBU_NAND_CON); -+ -+ ltq_w32(NAND_WRITE_CMD_RESET, -+ ((u32 *) (NAND_BASE_ADDRESS | NAND_WRITE_CMD))); -+ while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0) -+ ; -+ -+ return 0; -+} -+ -+static struct platform_nand_data falcon_flash_nand_data = { -+ .chip = { -+ .nr_chips = 1, -+ .chip_delay = 30, -+ .part_probe_types = part_probes, -+ }, -+ .ctrl = { -+ .probe = xway_probe, -+ .cmd_ctrl = xway_cmd_ctrl, -+ .dev_ready = xway_dev_ready, -+ .select_chip = xway_select_chip, -+ .read_byte = xway_read_byte, -+ .read_buf = xway_read_buf, -+ .write_buf = xway_write_buf, -+ } -+}; -+ -+static struct resource ltq_nand_res = -+ MEM_RES("nand", 0x14000000, 0x7ffffff); -+ -+static struct platform_device ltq_flash_nand = { -+ .name = "gen_nand", -+ .id = -1, -+ .num_resources = 1, -+ .resource = <q_nand_res, -+ .dev = { -+ .platform_data = &falcon_flash_nand_data, -+ }, -+}; -+ -+void __init xway_register_nand(struct mtd_partition *parts, int count) -+{ -+ falcon_flash_nand_data.chip.partitions = parts; -+ falcon_flash_nand_data.chip.nr_partitions = count; -+ platform_device_register(<q_flash_nand); -+} ---- a/drivers/mtd/nand/plat_nand.c -+++ b/drivers/mtd/nand/plat_nand.c -@@ -75,6 +75,7 @@ static int __devinit plat_nand_probe(str - data->chip.select_chip = pdata->ctrl.select_chip; - data->chip.write_buf = pdata->ctrl.write_buf; - data->chip.read_buf = pdata->ctrl.read_buf; -+ data->chip.read_byte = pdata->ctrl.read_byte; - data->chip.chip_delay = pdata->chip.chip_delay; - data->chip.options |= pdata->chip.options; - data->chip.bbt_options |= pdata->chip.bbt_options; ---- a/include/linux/mtd/nand.h -+++ b/include/linux/mtd/nand.h -@@ -652,6 +652,7 @@ struct platform_nand_ctrl { - void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); - void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); - void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); -+ unsigned char (*read_byte)(struct mtd_info *mtd); - void *priv; - }; - diff --git a/target/linux/lantiq/patches-3.3/0038-SPI-MIPS-lantiq-adds-spi-xway.patch b/target/linux/lantiq/patches-3.3/0038-SPI-MIPS-lantiq-adds-spi-xway.patch deleted file mode 100644 index f3d3da87d7..0000000000 --- a/target/linux/lantiq/patches-3.3/0038-SPI-MIPS-lantiq-adds-spi-xway.patch +++ /dev/null @@ -1,1137 +0,0 @@ -From 3e3dd3612431578cac22ed73064a38c0e30c5284 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 10 Oct 2011 22:29:13 +0200 -Subject: [PATCH 38/70] SPI: MIPS: lantiq: adds spi xway - ---- - .../mips/include/asm/mach-lantiq/lantiq_platform.h | 9 + - .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 2 + - drivers/spi/Kconfig | 8 + - drivers/spi/Makefile | 1 + - drivers/spi/spi-xway.c | 1068 ++++++++++++++++++++ - 5 files changed, 1088 insertions(+), 0 deletions(-) - create mode 100644 drivers/spi/spi-xway.c - ---- a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h -+++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h -@@ -50,4 +50,13 @@ struct ltq_eth_data { - int mii_mode; - }; - -+ -+struct ltq_spi_platform_data { -+ u16 num_chipselect; -+}; -+ -+struct ltq_spi_controller_data { -+ unsigned gpio; -+}; -+ - #endif ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h -@@ -27,6 +27,8 @@ - - #define LTQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15) - #define LTQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14) -+#define LTQ_SSC_TIR_AR9 (INT_NUM_IM0_IRL0 + 14) -+#define LTQ_SSC_RIR_AR9 (INT_NUM_IM0_IRL0 + 15) - #define LTQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16) - - #define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21) ---- a/drivers/spi/Kconfig -+++ b/drivers/spi/Kconfig -@@ -391,6 +391,14 @@ config SPI_NUC900 - help - SPI driver for Nuvoton NUC900 series ARM SoCs - -+config SPI_XWAY -+ tristate "Lantiq XWAY SPI controller" -+ depends on LANTIQ && SOC_TYPE_XWAY -+ select SPI_BITBANG -+ help -+ This driver supports the Lantiq SoC SPI controller in master -+ mode. -+ - # - # Add new SPI master controllers in alphabetical order above this line - # ---- a/drivers/spi/Makefile -+++ b/drivers/spi/Makefile -@@ -60,4 +60,5 @@ obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x - obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o - obj-$(CONFIG_SPI_TXX9) += spi-txx9.o - obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o -+obj-$(CONFIG_SPI_XWAY) += spi-xway.o - ---- /dev/null -+++ b/drivers/spi/spi-xway.c -@@ -0,0 +1,1068 @@ -+/* -+ * Lantiq SoC SPI controller -+ * -+ * Copyright (C) 2011 Daniel Schwierzeck -+ * -+ * This program is free software; you can distribute it and/or modify it -+ * under the terms of the GNU General Public License (Version 2) as -+ * published by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#define LTQ_SPI_CLC 0x00 /* Clock control */ -+#define LTQ_SPI_PISEL 0x04 /* Port input select */ -+#define LTQ_SPI_ID 0x08 /* Identification */ -+#define LTQ_SPI_CON 0x10 /* Control */ -+#define LTQ_SPI_STAT 0x14 /* Status */ -+#define LTQ_SPI_WHBSTATE 0x18 /* Write HW modified state */ -+#define LTQ_SPI_TB 0x20 /* Transmit buffer */ -+#define LTQ_SPI_RB 0x24 /* Receive buffer */ -+#define LTQ_SPI_RXFCON 0x30 /* Receive FIFO control */ -+#define LTQ_SPI_TXFCON 0x34 /* Transmit FIFO control */ -+#define LTQ_SPI_FSTAT 0x38 /* FIFO status */ -+#define LTQ_SPI_BRT 0x40 /* Baudrate timer */ -+#define LTQ_SPI_BRSTAT 0x44 /* Baudrate timer status */ -+#define LTQ_SPI_SFCON 0x60 /* Serial frame control */ -+#define LTQ_SPI_SFSTAT 0x64 /* Serial frame status */ -+#define LTQ_SPI_GPOCON 0x70 /* General purpose output control */ -+#define LTQ_SPI_GPOSTAT 0x74 /* General purpose output status */ -+#define LTQ_SPI_FGPO 0x78 /* Forced general purpose output */ -+#define LTQ_SPI_RXREQ 0x80 /* Receive request */ -+#define LTQ_SPI_RXCNT 0x84 /* Receive count */ -+#define LTQ_SPI_DMACON 0xEC /* DMA control */ -+#define LTQ_SPI_IRNEN 0xF4 /* Interrupt node enable */ -+#define LTQ_SPI_IRNICR 0xF8 /* Interrupt node interrupt capture */ -+#define LTQ_SPI_IRNCR 0xFC /* Interrupt node control */ -+ -+#define LTQ_SPI_CLC_SMC_SHIFT 16 /* Clock divider for sleep mode */ -+#define LTQ_SPI_CLC_SMC_MASK 0xFF -+#define LTQ_SPI_CLC_RMC_SHIFT 8 /* Clock divider for normal run mode */ -+#define LTQ_SPI_CLC_RMC_MASK 0xFF -+#define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */ -+#define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */ -+ -+#define LTQ_SPI_ID_TXFS_SHIFT 24 /* Implemented TX FIFO size */ -+#define LTQ_SPI_ID_TXFS_MASK 0x3F -+#define LTQ_SPI_ID_RXFS_SHIFT 16 /* Implemented RX FIFO size */ -+#define LTQ_SPI_ID_RXFS_MASK 0x3F -+#define LTQ_SPI_ID_REV_MASK 0x1F /* Hardware revision number */ -+#define LTQ_SPI_ID_CFG BIT(5) /* DMA interface support */ -+ -+#define LTQ_SPI_CON_BM_SHIFT 16 /* Data width selection */ -+#define LTQ_SPI_CON_BM_MASK 0x1F -+#define LTQ_SPI_CON_EM BIT(24) /* Echo mode */ -+#define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */ -+#define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */ -+#define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */ -+#define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */ -+#define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */ -+#define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */ -+#define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */ -+#define LTQ_SPI_CON_LB BIT(7) /* Loopback control */ -+#define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */ -+#define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */ -+#define LTQ_SPI_CON_HB BIT(4) /* Heading control */ -+#define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */ -+#define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */ -+ -+#define LTQ_SPI_STAT_RXBV_MASK 0x7 -+#define LTQ_SPI_STAT_RXBV_SHIFT 28 -+#define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */ -+#define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */ -+#define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */ -+#define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */ -+#define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */ -+#define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */ -+#define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */ -+#define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */ -+ -+#define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */ -+#define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */ -+#define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */ -+#define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */ -+#define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */ -+#define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */ -+#define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */ -+#define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */ -+#define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */ -+#define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */ -+#define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */ -+#define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */ -+#define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */ -+#define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */ -+#define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */ -+#define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */ -+#define LTQ_SPI_WHBSTATE_CLR_ERRORS 0x0F50 -+ -+#define LTQ_SPI_RXFCON_RXFITL_SHIFT 8 /* FIFO interrupt trigger level */ -+#define LTQ_SPI_RXFCON_RXFITL_MASK 0x3F -+#define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */ -+#define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */ -+ -+#define LTQ_SPI_TXFCON_TXFITL_SHIFT 8 /* FIFO interrupt trigger level */ -+#define LTQ_SPI_TXFCON_TXFITL_MASK 0x3F -+#define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */ -+#define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */ -+ -+#define LTQ_SPI_FSTAT_RXFFL_MASK 0x3f -+#define LTQ_SPI_FSTAT_RXFFL_SHIFT 0 -+#define LTQ_SPI_FSTAT_TXFFL_MASK 0x3f -+#define LTQ_SPI_FSTAT_TXFFL_SHIFT 8 -+ -+#define LTQ_SPI_GPOCON_ISCSBN_SHIFT 8 -+#define LTQ_SPI_GPOCON_INVOUTN_SHIFT 0 -+ -+#define LTQ_SPI_FGPO_SETOUTN_SHIFT 8 -+#define LTQ_SPI_FGPO_CLROUTN_SHIFT 0 -+ -+#define LTQ_SPI_RXREQ_RXCNT_MASK 0xFFFF /* Receive count value */ -+#define LTQ_SPI_RXCNT_TODO_MASK 0xFFFF /* Recevie to-do value */ -+ -+#define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */ -+#define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */ -+#define LTQ_SPI_IRNEN_T BIT(1) /* Transmit end interrupt request */ -+#define LTQ_SPI_IRNEN_R BIT(0) /* Receive end interrupt request */ -+#define LTQ_SPI_IRNEN_ALL 0xF -+ -+/* Hard-wired GPIOs used by SPI controller */ -+#define LTQ_SPI_GPIO_DI 16 -+#define LTQ_SPI_GPIO_DO 17 -+#define LTQ_SPI_GPIO_CLK 18 -+ -+struct ltq_spi { -+ struct spi_bitbang bitbang; -+ struct completion done; -+ spinlock_t lock; -+ -+ struct device *dev; -+ void __iomem *base; -+ struct clk *fpiclk; -+ struct clk *spiclk; -+ -+ int status; -+ int irq[3]; -+ -+ const u8 *tx; -+ u8 *rx; -+ u32 tx_cnt; -+ u32 rx_cnt; -+ u32 len; -+ struct spi_transfer *curr_transfer; -+ -+ u32 (*get_tx) (struct ltq_spi *); -+ -+ u16 txfs; -+ u16 rxfs; -+ unsigned dma_support:1; -+ unsigned cfg_mode:1; -+ -+}; -+ -+struct ltq_spi_controller_state { -+ void (*cs_activate) (struct spi_device *); -+ void (*cs_deactivate) (struct spi_device *); -+}; -+ -+struct ltq_spi_irq_map { -+ char *name; -+ irq_handler_t handler; -+}; -+ -+struct ltq_spi_cs_gpio_map { -+ unsigned gpio; -+ unsigned mux; -+}; -+ -+static inline struct ltq_spi *ltq_spi_to_hw(struct spi_device *spi) -+{ -+ return spi_master_get_devdata(spi->master); -+} -+ -+static inline u32 ltq_spi_reg_read(struct ltq_spi *hw, u32 reg) -+{ -+ return ioread32be(hw->base + reg); -+} -+ -+static inline void ltq_spi_reg_write(struct ltq_spi *hw, u32 val, u32 reg) -+{ -+ iowrite32be(val, hw->base + reg); -+} -+ -+static inline void ltq_spi_reg_setbit(struct ltq_spi *hw, u32 bits, u32 reg) -+{ -+ u32 val; -+ -+ val = ltq_spi_reg_read(hw, reg); -+ val |= bits; -+ ltq_spi_reg_write(hw, val, reg); -+} -+ -+static inline void ltq_spi_reg_clearbit(struct ltq_spi *hw, u32 bits, u32 reg) -+{ -+ u32 val; -+ -+ val = ltq_spi_reg_read(hw, reg); -+ val &= ~bits; -+ ltq_spi_reg_write(hw, val, reg); -+} -+ -+static void ltq_spi_hw_enable(struct ltq_spi *hw) -+{ -+ u32 clc; -+ -+ /* Power-up mdule */ -+ clk_enable(hw->spiclk); -+ -+ /* -+ * Set clock divider for run mode to 1 to -+ * run at same frequency as FPI bus -+ */ -+ clc = (1 << LTQ_SPI_CLC_RMC_SHIFT); -+ ltq_spi_reg_write(hw, clc, LTQ_SPI_CLC); -+} -+ -+static void ltq_spi_hw_disable(struct ltq_spi *hw) -+{ -+ /* Set clock divider to 0 and set module disable bit */ -+ ltq_spi_reg_write(hw, LTQ_SPI_CLC_DISS, LTQ_SPI_CLC); -+ -+ /* Power-down mdule */ -+ clk_disable(hw->spiclk); -+} -+ -+static void ltq_spi_reset_fifos(struct ltq_spi *hw) -+{ -+ u32 val; -+ -+ /* -+ * Enable and flush FIFOs. Set interrupt trigger level to -+ * half of FIFO count implemented in hardware. -+ */ -+ if (hw->txfs > 1) { -+ val = hw->txfs << (LTQ_SPI_TXFCON_TXFITL_SHIFT - 1); -+ val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU; -+ ltq_spi_reg_write(hw, val, LTQ_SPI_TXFCON); -+ } -+ -+ if (hw->rxfs > 1) { -+ val = hw->rxfs << (LTQ_SPI_RXFCON_RXFITL_SHIFT - 1); -+ val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU; -+ ltq_spi_reg_write(hw, val, LTQ_SPI_RXFCON); -+ } -+} -+ -+static inline int ltq_spi_wait_ready(struct ltq_spi *hw) -+{ -+ u32 stat; -+ unsigned long timeout; -+ -+ timeout = jiffies + msecs_to_jiffies(200); -+ -+ do { -+ stat = ltq_spi_reg_read(hw, LTQ_SPI_STAT); -+ if (!(stat & LTQ_SPI_STAT_BSY)) -+ return 0; -+ -+ cond_resched(); -+ } while (!time_after_eq(jiffies, timeout)); -+ -+ dev_err(hw->dev, "SPI wait ready timed out\n"); -+ -+ return -ETIMEDOUT; -+} -+ -+static void ltq_spi_config_mode_set(struct ltq_spi *hw) -+{ -+ if (hw->cfg_mode) -+ return; -+ -+ /* -+ * Putting the SPI module in config mode is only safe if no -+ * transfer is in progress as indicated by busy flag STATE.BSY. -+ */ -+ if (ltq_spi_wait_ready(hw)) { -+ ltq_spi_reset_fifos(hw); -+ hw->status = -ETIMEDOUT; -+ } -+ ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE); -+ -+ hw->cfg_mode = 1; -+} -+ -+static void ltq_spi_run_mode_set(struct ltq_spi *hw) -+{ -+ if (!hw->cfg_mode) -+ return; -+ -+ ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE); -+ -+ hw->cfg_mode = 0; -+} -+ -+static u32 ltq_spi_tx_word_u8(struct ltq_spi *hw) -+{ -+ const u8 *tx = hw->tx; -+ u32 data = *tx++; -+ -+ hw->tx_cnt++; -+ hw->tx++; -+ -+ return data; -+} -+ -+static u32 ltq_spi_tx_word_u16(struct ltq_spi *hw) -+{ -+ const u16 *tx = (u16 *) hw->tx; -+ u32 data = *tx++; -+ -+ hw->tx_cnt += 2; -+ hw->tx += 2; -+ -+ return data; -+} -+ -+static u32 ltq_spi_tx_word_u32(struct ltq_spi *hw) -+{ -+ const u32 *tx = (u32 *) hw->tx; -+ u32 data = *tx++; -+ -+ hw->tx_cnt += 4; -+ hw->tx += 4; -+ -+ return data; -+} -+ -+static void ltq_spi_bits_per_word_set(struct spi_device *spi) -+{ -+ struct ltq_spi *hw = ltq_spi_to_hw(spi); -+ u32 bm; -+ u8 bits_per_word = spi->bits_per_word; -+ -+ /* -+ * Use either default value of SPI device or value -+ * from current transfer. -+ */ -+ if (hw->curr_transfer && hw->curr_transfer->bits_per_word) -+ bits_per_word = hw->curr_transfer->bits_per_word; -+ -+ if (bits_per_word <= 8) -+ hw->get_tx = ltq_spi_tx_word_u8; -+ else if (bits_per_word <= 16) -+ hw->get_tx = ltq_spi_tx_word_u16; -+ else if (bits_per_word <= 32) -+ hw->get_tx = ltq_spi_tx_word_u32; -+ -+ /* CON.BM value = bits_per_word - 1 */ -+ bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_SHIFT; -+ -+ ltq_spi_reg_clearbit(hw, LTQ_SPI_CON_BM_MASK << -+ LTQ_SPI_CON_BM_SHIFT, LTQ_SPI_CON); -+ ltq_spi_reg_setbit(hw, bm, LTQ_SPI_CON); -+} -+ -+static void ltq_spi_speed_set(struct spi_device *spi) -+{ -+ struct ltq_spi *hw = ltq_spi_to_hw(spi); -+ u32 br, max_speed_hz, spi_clk; -+ u32 speed_hz = spi->max_speed_hz; -+ -+ /* -+ * Use either default value of SPI device or value -+ * from current transfer. -+ */ -+ if (hw->curr_transfer && hw->curr_transfer->speed_hz) -+ speed_hz = hw->curr_transfer->speed_hz; -+ -+ /* -+ * SPI module clock is derived from FPI bus clock dependent on -+ * divider value in CLC.RMS which is always set to 1. -+ */ -+ spi_clk = clk_get_rate(hw->fpiclk); -+ -+ /* -+ * Maximum SPI clock frequency in master mode is half of -+ * SPI module clock frequency. Maximum reload value of -+ * baudrate generator BR is 2^16. -+ */ -+ max_speed_hz = spi_clk / 2; -+ if (speed_hz >= max_speed_hz) -+ br = 0; -+ else -+ br = (max_speed_hz / speed_hz) - 1; -+ -+ if (br > 0xFFFF) -+ br = 0xFFFF; -+ -+ ltq_spi_reg_write(hw, br, LTQ_SPI_BRT); -+} -+ -+static void ltq_spi_clockmode_set(struct spi_device *spi) -+{ -+ struct ltq_spi *hw = ltq_spi_to_hw(spi); -+ u32 con; -+ -+ con = ltq_spi_reg_read(hw, LTQ_SPI_CON); -+ -+ /* -+ * SPI mode mapping in CON register: -+ * Mode CPOL CPHA CON.PO CON.PH -+ * 0 0 0 0 1 -+ * 1 0 1 0 0 -+ * 2 1 0 1 1 -+ * 3 1 1 1 0 -+ */ -+ if (spi->mode & SPI_CPHA) -+ con &= ~LTQ_SPI_CON_PH; -+ else -+ con |= LTQ_SPI_CON_PH; -+ -+ if (spi->mode & SPI_CPOL) -+ con |= LTQ_SPI_CON_PO; -+ else -+ con &= ~LTQ_SPI_CON_PO; -+ -+ /* Set heading control */ -+ if (spi->mode & SPI_LSB_FIRST) -+ con &= ~LTQ_SPI_CON_HB; -+ else -+ con |= LTQ_SPI_CON_HB; -+ -+ ltq_spi_reg_write(hw, con, LTQ_SPI_CON); -+} -+ -+static void ltq_spi_xmit_set(struct ltq_spi *hw, struct spi_transfer *t) -+{ -+ u32 con; -+ -+ con = ltq_spi_reg_read(hw, LTQ_SPI_CON); -+ -+ if (t) { -+ if (t->tx_buf && t->rx_buf) { -+ con &= ~(LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF); -+ } else if (t->rx_buf) { -+ con &= ~LTQ_SPI_CON_RXOFF; -+ con |= LTQ_SPI_CON_TXOFF; -+ } else if (t->tx_buf) { -+ con &= ~LTQ_SPI_CON_TXOFF; -+ con |= LTQ_SPI_CON_RXOFF; -+ } -+ } else -+ con |= (LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF); -+ -+ ltq_spi_reg_write(hw, con, LTQ_SPI_CON); -+} -+ -+static void ltq_spi_gpio_cs_activate(struct spi_device *spi) -+{ -+ struct ltq_spi_controller_data *cdata = spi->controller_data; -+ int val = spi->mode & SPI_CS_HIGH ? 1 : 0; -+ -+ gpio_set_value(cdata->gpio, val); -+} -+ -+static void ltq_spi_gpio_cs_deactivate(struct spi_device *spi) -+{ -+ struct ltq_spi_controller_data *cdata = spi->controller_data; -+ int val = spi->mode & SPI_CS_HIGH ? 0 : 1; -+ -+ gpio_set_value(cdata->gpio, val); -+} -+ -+static void ltq_spi_internal_cs_activate(struct spi_device *spi) -+{ -+ struct ltq_spi *hw = ltq_spi_to_hw(spi); -+ u32 fgpo; -+ -+ fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_CLROUTN_SHIFT)); -+ ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO); -+} -+ -+static void ltq_spi_internal_cs_deactivate(struct spi_device *spi) -+{ -+ struct ltq_spi *hw = ltq_spi_to_hw(spi); -+ u32 fgpo; -+ -+ fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT)); -+ ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO); -+} -+ -+static void ltq_spi_chipselect(struct spi_device *spi, int cs) -+{ -+ struct ltq_spi *hw = ltq_spi_to_hw(spi); -+ struct ltq_spi_controller_state *cstate = spi->controller_state; -+ -+ switch (cs) { -+ case BITBANG_CS_ACTIVE: -+ ltq_spi_bits_per_word_set(spi); -+ ltq_spi_speed_set(spi); -+ ltq_spi_clockmode_set(spi); -+ ltq_spi_run_mode_set(hw); -+ -+ cstate->cs_activate(spi); -+ break; -+ -+ case BITBANG_CS_INACTIVE: -+ cstate->cs_deactivate(spi); -+ -+ ltq_spi_config_mode_set(hw); -+ -+ break; -+ } -+} -+ -+static int ltq_spi_setup_transfer(struct spi_device *spi, -+ struct spi_transfer *t) -+{ -+ struct ltq_spi *hw = ltq_spi_to_hw(spi); -+ u8 bits_per_word = spi->bits_per_word; -+ -+ hw->curr_transfer = t; -+ -+ if (t && t->bits_per_word) -+ bits_per_word = t->bits_per_word; -+ -+ if (bits_per_word > 32) -+ return -EINVAL; -+ -+ ltq_spi_config_mode_set(hw); -+ -+ return 0; -+} -+ -+static const struct ltq_spi_cs_gpio_map ltq_spi_cs[] = { -+ { 15, 2 }, -+ { 22, 2 }, -+ { 13, 1 }, -+ { 10, 1 }, -+ { 9, 1 }, -+ { 11, 3 }, -+}; -+ -+static int ltq_spi_setup(struct spi_device *spi) -+{ -+ struct ltq_spi *hw = ltq_spi_to_hw(spi); -+ struct ltq_spi_controller_data *cdata = spi->controller_data; -+ struct ltq_spi_controller_state *cstate; -+ u32 gpocon, fgpo; -+ int ret; -+ -+ /* Set default word length to 8 if not set */ -+ if (!spi->bits_per_word) -+ spi->bits_per_word = 8; -+ -+ if (spi->bits_per_word > 32) -+ return -EINVAL; -+ -+ if (!spi->controller_state) { -+ cstate = kzalloc(sizeof(struct ltq_spi_controller_state), -+ GFP_KERNEL); -+ if (!cstate) -+ return -ENOMEM; -+ -+ spi->controller_state = cstate; -+ } else -+ return 0; -+ -+ /* -+ * Up to six GPIOs can be connected to the SPI module -+ * via GPIO alternate function to control the chip select lines. -+ * For more flexibility in board layout this driver can also control -+ * the CS lines via GPIO API. If GPIOs should be used, board setup code -+ * have to register the SPI device with struct ltq_spi_controller_data -+ * attached. -+ */ -+ if (cdata && cdata->gpio) { -+ ret = gpio_request(cdata->gpio, "spi-cs"); -+ if (ret) -+ return -EBUSY; -+ -+ ret = spi->mode & SPI_CS_HIGH ? 0 : 1; -+ gpio_direction_output(cdata->gpio, ret); -+ -+ cstate->cs_activate = ltq_spi_gpio_cs_activate; -+ cstate->cs_deactivate = ltq_spi_gpio_cs_deactivate; -+ } else { -+ ret = ltq_gpio_request(&spi->dev, ltq_spi_cs[spi->chip_select].gpio, -+ ltq_spi_cs[spi->chip_select].mux, -+ 1, "spi-cs"); -+ if (ret) -+ return -EBUSY; -+ -+ gpocon = (1 << (spi->chip_select + -+ LTQ_SPI_GPOCON_ISCSBN_SHIFT)); -+ -+ if (spi->mode & SPI_CS_HIGH) -+ gpocon |= (1 << spi->chip_select); -+ -+ fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT)); -+ -+ ltq_spi_reg_setbit(hw, gpocon, LTQ_SPI_GPOCON); -+ ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO); -+ -+ cstate->cs_activate = ltq_spi_internal_cs_activate; -+ cstate->cs_deactivate = ltq_spi_internal_cs_deactivate; -+ } -+ -+ return 0; -+} -+ -+static void ltq_spi_cleanup(struct spi_device *spi) -+{ -+ struct ltq_spi_controller_data *cdata = spi->controller_data; -+ struct ltq_spi_controller_state *cstate = spi->controller_state; -+ unsigned gpio; -+ -+ if (cdata && cdata->gpio) -+ gpio = cdata->gpio; -+ else -+ gpio = ltq_spi_cs[spi->chip_select].gpio; -+ -+ gpio_free(gpio); -+ kfree(cstate); -+} -+ -+static void ltq_spi_txfifo_write(struct ltq_spi *hw) -+{ -+ u32 fstat, data; -+ u16 fifo_space; -+ -+ /* Determine how much FIFOs are free for TX data */ -+ fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT); -+ fifo_space = hw->txfs - ((fstat >> LTQ_SPI_FSTAT_TXFFL_SHIFT) & -+ LTQ_SPI_FSTAT_TXFFL_MASK); -+ -+ if (!fifo_space) -+ return; -+ -+ while (hw->tx_cnt < hw->len && fifo_space) { -+ data = hw->get_tx(hw); -+ ltq_spi_reg_write(hw, data, LTQ_SPI_TB); -+ fifo_space--; -+ } -+} -+ -+static void ltq_spi_rxfifo_read(struct ltq_spi *hw) -+{ -+ u32 fstat, data, *rx32; -+ u16 fifo_fill; -+ u8 rxbv, shift, *rx8; -+ -+ /* Determine how much FIFOs are filled with RX data */ -+ fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT); -+ fifo_fill = ((fstat >> LTQ_SPI_FSTAT_RXFFL_SHIFT) -+ & LTQ_SPI_FSTAT_RXFFL_MASK); -+ -+ if (!fifo_fill) -+ return; -+ -+ /* -+ * The 32 bit FIFO is always used completely independent from the -+ * bits_per_word value. Thus four bytes have to be read at once -+ * per FIFO. -+ */ -+ rx32 = (u32 *) hw->rx; -+ while (hw->len - hw->rx_cnt >= 4 && fifo_fill) { -+ *rx32++ = ltq_spi_reg_read(hw, LTQ_SPI_RB); -+ hw->rx_cnt += 4; -+ hw->rx += 4; -+ fifo_fill--; -+ } -+ -+ /* -+ * If there are remaining bytes, read byte count from STAT.RXBV -+ * register and read the data byte-wise. -+ */ -+ while (fifo_fill && hw->rx_cnt < hw->len) { -+ rxbv = (ltq_spi_reg_read(hw, LTQ_SPI_STAT) >> -+ LTQ_SPI_STAT_RXBV_SHIFT) & LTQ_SPI_STAT_RXBV_MASK; -+ data = ltq_spi_reg_read(hw, LTQ_SPI_RB); -+ -+ shift = (rxbv - 1) * 8; -+ rx8 = hw->rx; -+ -+ while (rxbv) { -+ *rx8++ = (data >> shift) & 0xFF; -+ rxbv--; -+ shift -= 8; -+ hw->rx_cnt++; -+ hw->rx++; -+ } -+ -+ fifo_fill--; -+ } -+} -+ -+static void ltq_spi_rxreq_set(struct ltq_spi *hw) -+{ -+ u32 rxreq, rxreq_max, rxtodo; -+ -+ rxtodo = ltq_spi_reg_read(hw, LTQ_SPI_RXCNT) & LTQ_SPI_RXCNT_TODO_MASK; -+ -+ /* -+ * In RX-only mode the serial clock is activated only after writing -+ * the expected amount of RX bytes into RXREQ register. -+ * To avoid receive overflows at high clocks it is better to request -+ * only the amount of bytes that fits into all FIFOs. This value -+ * depends on the FIFO size implemented in hardware. -+ */ -+ rxreq = hw->len - hw->rx_cnt; -+ rxreq_max = hw->rxfs << 2; -+ rxreq = min(rxreq_max, rxreq); -+ -+ if (!rxtodo && rxreq) -+ ltq_spi_reg_write(hw, rxreq, LTQ_SPI_RXREQ); -+} -+ -+static inline void ltq_spi_complete(struct ltq_spi *hw) -+{ -+ complete(&hw->done); -+} -+ -+irqreturn_t ltq_spi_tx_irq(int irq, void *data) -+{ -+ struct ltq_spi *hw = data; -+ unsigned long flags; -+ int completed = 0; -+ -+ spin_lock_irqsave(&hw->lock, flags); -+ -+ if (hw->tx_cnt < hw->len) -+ ltq_spi_txfifo_write(hw); -+ -+ if (hw->tx_cnt == hw->len) -+ completed = 1; -+ -+ spin_unlock_irqrestore(&hw->lock, flags); -+ -+ if (completed) -+ ltq_spi_complete(hw); -+ -+ return IRQ_HANDLED; -+} -+ -+irqreturn_t ltq_spi_rx_irq(int irq, void *data) -+{ -+ struct ltq_spi *hw = data; -+ unsigned long flags; -+ int completed = 0; -+ -+ spin_lock_irqsave(&hw->lock, flags); -+ -+ if (hw->rx_cnt < hw->len) { -+ ltq_spi_rxfifo_read(hw); -+ -+ if (hw->tx && hw->tx_cnt < hw->len) -+ ltq_spi_txfifo_write(hw); -+ } -+ -+ if (hw->rx_cnt == hw->len) -+ completed = 1; -+ else if (!hw->tx) -+ ltq_spi_rxreq_set(hw); -+ -+ spin_unlock_irqrestore(&hw->lock, flags); -+ -+ if (completed) -+ ltq_spi_complete(hw); -+ -+ return IRQ_HANDLED; -+} -+ -+irqreturn_t ltq_spi_err_irq(int irq, void *data) -+{ -+ struct ltq_spi *hw = data; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&hw->lock, flags); -+ -+ /* Disable all interrupts */ -+ ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN); -+ -+ /* Clear all error flags */ -+ ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); -+ -+ /* Flush FIFOs */ -+ ltq_spi_reg_setbit(hw, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON); -+ ltq_spi_reg_setbit(hw, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON); -+ -+ hw->status = -EIO; -+ spin_unlock_irqrestore(&hw->lock, flags); -+ -+ ltq_spi_complete(hw); -+ -+ return IRQ_HANDLED; -+} -+ -+static int ltq_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) -+{ -+ struct ltq_spi *hw = ltq_spi_to_hw(spi); -+ u32 irq_flags = 0; -+ -+ hw->tx = t->tx_buf; -+ hw->rx = t->rx_buf; -+ hw->len = t->len; -+ hw->tx_cnt = 0; -+ hw->rx_cnt = 0; -+ hw->status = 0; -+ INIT_COMPLETION(hw->done); -+ -+ ltq_spi_xmit_set(hw, t); -+ -+ /* Enable error interrupts */ -+ ltq_spi_reg_setbit(hw, LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN); -+ -+ if (hw->tx) { -+ /* Initially fill TX FIFO with as much data as possible */ -+ ltq_spi_txfifo_write(hw); -+ irq_flags |= LTQ_SPI_IRNEN_T; -+ -+ /* Always enable RX interrupt in Full Duplex mode */ -+ if (hw->rx) -+ irq_flags |= LTQ_SPI_IRNEN_R; -+ } else if (hw->rx) { -+ /* Start RX clock */ -+ ltq_spi_rxreq_set(hw); -+ -+ /* Enable RX interrupt to receive data from RX FIFOs */ -+ irq_flags |= LTQ_SPI_IRNEN_R; -+ } -+ -+ /* Enable TX or RX interrupts */ -+ ltq_spi_reg_setbit(hw, irq_flags, LTQ_SPI_IRNEN); -+ wait_for_completion_interruptible(&hw->done); -+ -+ /* Disable all interrupts */ -+ ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN); -+ -+ /* -+ * Return length of current transfer for bitbang utility code if -+ * no errors occured during transmission. -+ */ -+ if (!hw->status) -+ hw->status = hw->len; -+ -+ return hw->status; -+} -+ -+static const struct ltq_spi_irq_map ltq_spi_irqs[] = { -+ { "spi_tx", ltq_spi_tx_irq }, -+ { "spi_rx", ltq_spi_rx_irq }, -+ { "spi_err", ltq_spi_err_irq }, -+}; -+ -+static int __init ltq_spi_probe(struct platform_device *pdev) -+{ -+ struct spi_master *master; -+ struct resource *r; -+ struct ltq_spi *hw; -+ struct ltq_spi_platform_data *pdata = pdev->dev.platform_data; -+ int ret, i; -+ u32 data, id; -+ -+ master = spi_alloc_master(&pdev->dev, sizeof(struct ltq_spi)); -+ if (!master) { -+ dev_err(&pdev->dev, "spi_alloc_master\n"); -+ ret = -ENOMEM; -+ goto err; -+ } -+ -+ hw = spi_master_get_devdata(master); -+ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (r == NULL) { -+ dev_err(&pdev->dev, "platform_get_resource\n"); -+ ret = -ENOENT; -+ goto err_master; -+ } -+ -+ r = devm_request_mem_region(&pdev->dev, r->start, resource_size(r), -+ pdev->name); -+ if (!r) { -+ dev_err(&pdev->dev, "devm_request_mem_region\n"); -+ ret = -ENXIO; -+ goto err_master; -+ } -+ -+ hw->base = devm_ioremap_nocache(&pdev->dev, r->start, resource_size(r)); -+ if (!hw->base) { -+ dev_err(&pdev->dev, "devm_ioremap_nocache\n"); -+ ret = -ENXIO; -+ goto err_master; -+ } -+ -+ hw->fpiclk = clk_get_fpi(); -+ if (IS_ERR(hw->fpiclk)) { -+ dev_err(&pdev->dev, "clk_get\n"); -+ ret = PTR_ERR(hw->fpiclk); -+ goto err_master; -+ } -+ -+ hw->spiclk = clk_get(&pdev->dev, NULL); -+ if (IS_ERR(hw->spiclk)) { -+ dev_err(&pdev->dev, "clk_get\n"); -+ ret = PTR_ERR(hw->spiclk); -+ goto err_master; -+ } -+ -+ memset(hw->irq, 0, sizeof(hw->irq)); -+ for (i = 0; i < ARRAY_SIZE(ltq_spi_irqs); i++) { -+ ret = platform_get_irq_byname(pdev, ltq_spi_irqs[i].name); -+ if (0 > ret) { -+ dev_err(&pdev->dev, "platform_get_irq_byname\n"); -+ goto err_irq; -+ } -+ -+ hw->irq[i] = ret; -+ ret = request_irq(hw->irq[i], ltq_spi_irqs[i].handler, -+ 0, ltq_spi_irqs[i].name, hw); -+ if (ret) { -+ dev_err(&pdev->dev, "request_irq\n"); -+ goto err_irq; -+ } -+ } -+ -+ hw->bitbang.master = spi_master_get(master); -+ hw->bitbang.chipselect = ltq_spi_chipselect; -+ hw->bitbang.setup_transfer = ltq_spi_setup_transfer; -+ hw->bitbang.txrx_bufs = ltq_spi_txrx_bufs; -+ -+ master->bus_num = pdev->id; -+ master->num_chipselect = pdata->num_chipselect; -+ master->setup = ltq_spi_setup; -+ master->cleanup = ltq_spi_cleanup; -+ -+ hw->dev = &pdev->dev; -+ init_completion(&hw->done); -+ spin_lock_init(&hw->lock); -+ -+ /* Set GPIO alternate functions to SPI */ -+ ltq_gpio_request(&pdev->dev, LTQ_SPI_GPIO_DI, 2, 0, "spi-di"); -+ ltq_gpio_request(&pdev->dev, LTQ_SPI_GPIO_DO, 2, 1, "spi-do"); -+ ltq_gpio_request(&pdev->dev, LTQ_SPI_GPIO_CLK, 2, 1, "spi-clk"); -+ -+ ltq_spi_hw_enable(hw); -+ -+ /* Read module capabilities */ -+ id = ltq_spi_reg_read(hw, LTQ_SPI_ID); -+ hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK; -+ hw->rxfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK; -+ hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0; -+ -+ ltq_spi_config_mode_set(hw); -+ -+ /* Enable error checking, disable TX/RX, set idle value high */ -+ data = LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN | -+ LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN | -+ LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF | LTQ_SPI_CON_IDLE; -+ ltq_spi_reg_write(hw, data, LTQ_SPI_CON); -+ -+ /* Enable master mode and clear error flags */ -+ ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETMS | -+ LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); -+ -+ /* Reset GPIO/CS registers */ -+ ltq_spi_reg_write(hw, 0x0, LTQ_SPI_GPOCON); -+ ltq_spi_reg_write(hw, 0xFF00, LTQ_SPI_FGPO); -+ -+ /* Enable and flush FIFOs */ -+ ltq_spi_reset_fifos(hw); -+ -+ ret = spi_bitbang_start(&hw->bitbang); -+ if (ret) { -+ dev_err(&pdev->dev, "spi_bitbang_start\n"); -+ goto err_bitbang; -+ } -+ -+ platform_set_drvdata(pdev, hw); -+ -+ pr_info("Lantiq SoC SPI controller rev %u (TXFS %u, RXFS %u, DMA %u)\n", -+ id & LTQ_SPI_ID_REV_MASK, hw->txfs, hw->rxfs, hw->dma_support); -+ -+ return 0; -+ -+err_bitbang: -+ ltq_spi_hw_disable(hw); -+ -+err_irq: -+ clk_put(hw->fpiclk); -+ -+ for (; i > 0; i--) -+ free_irq(hw->irq[i], hw); -+ -+err_master: -+ spi_master_put(master); -+ -+err: -+ return ret; -+} -+ -+static int __exit ltq_spi_remove(struct platform_device *pdev) -+{ -+ struct ltq_spi *hw = platform_get_drvdata(pdev); -+ int ret, i; -+ -+ ret = spi_bitbang_stop(&hw->bitbang); -+ if (ret) -+ return ret; -+ -+ platform_set_drvdata(pdev, NULL); -+ -+ ltq_spi_config_mode_set(hw); -+ ltq_spi_hw_disable(hw); -+ -+ for (i = 0; i < ARRAY_SIZE(hw->irq); i++) -+ if (0 < hw->irq[i]) -+ free_irq(hw->irq[i], hw); -+ -+ gpio_free(LTQ_SPI_GPIO_DI); -+ gpio_free(LTQ_SPI_GPIO_DO); -+ gpio_free(LTQ_SPI_GPIO_CLK); -+ -+ clk_put(hw->fpiclk); -+ spi_master_put(hw->bitbang.master); -+ -+ return 0; -+} -+ -+static struct platform_driver ltq_spi_driver = { -+ .driver = { -+ .name = "ltq_spi", -+ .owner = THIS_MODULE, -+ }, -+ .remove = __exit_p(ltq_spi_remove), -+}; -+ -+static int __init ltq_spi_init(void) -+{ -+ return platform_driver_probe(<q_spi_driver, ltq_spi_probe); -+} -+module_init(ltq_spi_init); -+ -+static void __exit ltq_spi_exit(void) -+{ -+ platform_driver_unregister(<q_spi_driver); -+} -+module_exit(ltq_spi_exit); -+ -+MODULE_DESCRIPTION("Lantiq SoC SPI controller driver"); -+MODULE_AUTHOR("Daniel Schwierzeck "); -+MODULE_LICENSE("GPL"); -+MODULE_ALIAS("platform:ltq-spi"); diff --git a/target/linux/lantiq/patches-3.3/0039-NET-adds-driver-for-lantiq-vr9-ethernet.patch b/target/linux/lantiq/patches-3.3/0039-NET-adds-driver-for-lantiq-vr9-ethernet.patch deleted file mode 100644 index 8b662871b8..0000000000 --- a/target/linux/lantiq/patches-3.3/0039-NET-adds-driver-for-lantiq-vr9-ethernet.patch +++ /dev/null @@ -1,1454 +0,0 @@ -From 239505c96aa66b4280b7726850235dcb707d2d91 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 9 Mar 2012 19:03:40 +0100 -Subject: [PATCH 39/70] NET: adds driver for lantiq vr9 ethernet - ---- - .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 2 +- - arch/mips/lantiq/xway/devices.c | 20 + - arch/mips/lantiq/xway/devices.h | 1 + - drivers/net/ethernet/Kconfig | 6 + - drivers/net/ethernet/Makefile | 1 + - drivers/net/ethernet/lantiq_vrx200.c | 1358 ++++++++++++++++++++ - 6 files changed, 1387 insertions(+), 1 deletions(-) - create mode 100644 drivers/net/ethernet/lantiq_vrx200.c - ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -@@ -102,7 +102,7 @@ - - /* GBIT - gigabit switch */ - #define LTQ_GBIT_BASE_ADDR 0x1E108000 --#define LTQ_GBIT_SIZE 0x200 -+#define LTQ_GBIT_SIZE 0x4000 - - /* DMA */ - #define LTQ_DMA_BASE_ADDR 0x1E104100 ---- a/arch/mips/lantiq/xway/devices.c -+++ b/arch/mips/lantiq/xway/devices.c -@@ -83,6 +83,7 @@ static struct platform_device ltq_etop = - .name = "ltq_etop", - .resource = ltq_etop_resources, - .num_resources = 1, -+ .id = -1, - }; - - void __init -@@ -96,3 +97,22 @@ ltq_register_etop(struct ltq_eth_data *e - platform_device_register(<q_etop); - } - } -+ -+/* ethernet */ -+static struct resource ltq_vrx200_resources[] = { -+ MEM_RES("gbit", LTQ_GBIT_BASE_ADDR, LTQ_GBIT_SIZE), -+}; -+ -+static struct platform_device ltq_vrx200 = { -+ .name = "ltq_vrx200", -+ .resource = ltq_vrx200_resources, -+ .num_resources = 1, -+ .id = -1, -+}; -+ -+void __init -+ltq_register_vrx200(struct ltq_eth_data *eth) -+{ -+ ltq_vrx200.dev.platform_data = eth; -+ platform_device_register(<q_vrx200); -+} ---- a/arch/mips/lantiq/xway/devices.h -+++ b/arch/mips/lantiq/xway/devices.h -@@ -17,5 +17,6 @@ extern void ltq_register_gpio_stp(void); - extern void ltq_register_ase_asc(void); - extern void ltq_register_etop(struct ltq_eth_data *eth); - extern void xway_register_nand(struct mtd_partition *parts, int count); -+extern void ltq_register_vrx200(struct ltq_eth_data *eth); - - #endif ---- a/drivers/net/ethernet/Kconfig -+++ b/drivers/net/ethernet/Kconfig -@@ -85,6 +85,12 @@ config LANTIQ_ETOP - ---help--- - Support for the MII0 inside the Lantiq SoC - -+config LANTIQ_VRX200 -+ tristate "Lantiq SoC vrx200 driver" -+ depends on SOC_TYPE_XWAY -+ ---help--- -+ Support for the MII0 inside the Lantiq SoC -+ - source "drivers/net/ethernet/marvell/Kconfig" - source "drivers/net/ethernet/mellanox/Kconfig" - source "drivers/net/ethernet/micrel/Kconfig" ---- a/drivers/net/ethernet/Makefile -+++ b/drivers/net/ethernet/Makefile -@@ -36,6 +36,7 @@ obj-$(CONFIG_IP1000) += icplus/ - obj-$(CONFIG_JME) += jme.o - obj-$(CONFIG_KORINA) += korina.o - obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o -+obj-$(CONFIG_LANTIQ_VRX200) += lantiq_vrx200.o - obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/ - obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/ - obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/ ---- /dev/null -+++ b/drivers/net/ethernet/lantiq_vrx200.c -@@ -0,0 +1,1358 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. -+ * -+ * Copyright (C) 2011 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include -+#include -+#include -+ -+#define LTQ_SWITCH_BASE 0x1E108000 -+#define LTQ_SWITCH_CORE_BASE LTQ_SWITCH_BASE -+#define LTQ_SWITCH_TOP_PDI_BASE LTQ_SWITCH_CORE_BASE -+#define LTQ_SWITCH_BM_PDI_BASE (LTQ_SWITCH_CORE_BASE + 4 * 0x40) -+#define LTQ_SWITCH_MAC_PDI_0_BASE (LTQ_SWITCH_CORE_BASE + 4 * 0x900) -+#define LTQ_SWITCH_MAC_PDI_X_BASE(x) (LTQ_SWITCH_MAC_PDI_0_BASE + x * 0x30) -+#define LTQ_SWITCH_TOPLEVEL_BASE (LTQ_SWITCH_BASE + 4 * 0xC40) -+#define LTQ_SWITCH_MDIO_PDI_BASE (LTQ_SWITCH_TOPLEVEL_BASE) -+#define LTQ_SWITCH_MII_PDI_BASE (LTQ_SWITCH_TOPLEVEL_BASE + 4 * 0x36) -+#define LTQ_SWITCH_PMAC_PDI_BASE (LTQ_SWITCH_TOPLEVEL_BASE + 4 * 0x82) -+ -+#define LTQ_ETHSW_MAC_CTRL0_PADEN (1 << 8) -+#define LTQ_ETHSW_MAC_CTRL0_FCS (1 << 7) -+#define LTQ_ETHSW_MAC_CTRL1_SHORTPRE (1 << 8) -+#define LTQ_ETHSW_MAC_CTRL2_MLEN (1 << 3) -+#define LTQ_ETHSW_MAC_CTRL2_LCHKL (1 << 2) -+#define LTQ_ETHSW_MAC_CTRL2_LCHKS_DIS 0 -+#define LTQ_ETHSW_MAC_CTRL2_LCHKS_UNTAG 1 -+#define LTQ_ETHSW_MAC_CTRL2_LCHKS_TAG 2 -+#define LTQ_ETHSW_MAC_CTRL6_RBUF_DLY_WP_SHIFT 9 -+#define LTQ_ETHSW_MAC_CTRL6_RXBUF_BYPASS (1 << 6) -+#define LTQ_ETHSW_GLOB_CTRL_SE (1 << 15) -+#define LTQ_ETHSW_MDC_CFG1_MCEN (1 << 8) -+#define LTQ_ETHSW_PMAC_HD_CTL_FC (1 << 10) -+#define LTQ_ETHSW_PMAC_HD_CTL_RC (1 << 4) -+#define LTQ_ETHSW_PMAC_HD_CTL_AC (1 << 2) -+#define ADVERTIZE_MPD (1 << 10) -+ -+#define MDIO_DEVAD_NONE (-1) -+ -+#define LTQ_ETH_RX_BUFFER_CNT PKTBUFSRX -+ -+#define LTQ_MDIO_DRV_NAME "ltq-mdio" -+#define LTQ_ETH_DRV_NAME "ltq-eth" -+ -+#define LTQ_ETHSW_MAX_GMAC 1 -+#define LTQ_ETHSW_PMAC 1 -+ -+#define ltq_setbits(a, set) \ -+ ltq_w32(ltq_r32(a) | (set), a) -+ -+enum ltq_reset_modules { -+ LTQ_RESET_CORE, -+ LTQ_RESET_DMA, -+ LTQ_RESET_ETH, -+ LTQ_RESET_PHY, -+ LTQ_RESET_HARD, -+ LTQ_RESET_SOFT, -+}; -+ -+static inline void -+dbg_ltq_writel(void *a, unsigned int b) -+{ -+ ltq_w32(b, a); -+} -+ -+int ltq_reset_once(enum ltq_reset_modules module, ulong usec); -+ -+struct ltq_ethsw_mac_pdi_x_regs { -+ u32 pstat; /* Port status */ -+ u32 pisr; /* Interrupt status */ -+ u32 pier; /* Interrupt enable */ -+ u32 ctrl_0; /* Control 0 */ -+ u32 ctrl_1; /* Control 1 */ -+ u32 ctrl_2; /* Control 2 */ -+ u32 ctrl_3; /* Control 3 */ -+ u32 ctrl_4; /* Control 4 */ -+ u32 ctrl_5; /* Control 5 */ -+ u32 ctrl_6; /* Control 6 */ -+ u32 bufst; /* TX/RX buffer control */ -+ u32 testen; /* Test enable */ -+}; -+ -+struct ltq_ethsw_mac_pdi_regs { -+ struct ltq_ethsw_mac_pdi_x_regs mac[12]; -+}; -+ -+struct ltq_ethsw_mdio_pdi_regs { -+ u32 glob_ctrl; /* Global control 0 */ -+ u32 rsvd0[7]; -+ u32 mdio_ctrl; /* MDIO control */ -+ u32 mdio_read; /* MDIO read data */ -+ u32 mdio_write; /* MDIO write data */ -+ u32 mdc_cfg_0; /* MDC clock configuration 0 */ -+ u32 mdc_cfg_1; /* MDC clock configuration 1 */ -+ u32 rsvd[3]; -+ u32 phy_addr_5; /* PHY address port 5 */ -+ u32 phy_addr_4; /* PHY address port 4 */ -+ u32 phy_addr_3; /* PHY address port 3 */ -+ u32 phy_addr_2; /* PHY address port 2 */ -+ u32 phy_addr_1; /* PHY address port 1 */ -+ u32 phy_addr_0; /* PHY address port 0 */ -+ u32 mdio_stat_0; /* MDIO PHY polling status port 0 */ -+ u32 mdio_stat_1; /* MDIO PHY polling status port 1 */ -+ u32 mdio_stat_2; /* MDIO PHY polling status port 2 */ -+ u32 mdio_stat_3; /* MDIO PHY polling status port 3 */ -+ u32 mdio_stat_4; /* MDIO PHY polling status port 4 */ -+ u32 mdio_stat_5; /* MDIO PHY polling status port 5 */ -+}; -+ -+struct ltq_ethsw_mii_pdi_regs { -+ u32 mii_cfg0; /* xMII port 0 configuration */ -+ u32 pcdu0; /* Port 0 clock delay configuration */ -+ u32 mii_cfg1; /* xMII port 1 configuration */ -+ u32 pcdu1; /* Port 1 clock delay configuration */ -+ u32 mii_cfg2; /* xMII port 2 configuration */ -+ u32 rsvd0; -+ u32 mii_cfg3; /* xMII port 3 configuration */ -+ u32 rsvd1; -+ u32 mii_cfg4; /* xMII port 4 configuration */ -+ u32 rsvd2; -+ u32 mii_cfg5; /* xMII port 5 configuration */ -+ u32 pcdu5; /* Port 5 clock delay configuration */ -+}; -+ -+struct ltq_ethsw_pmac_pdi_regs { -+ u32 hd_ctl; /* PMAC header control */ -+ u32 tl; /* PMAC type/length */ -+ u32 sa1; /* PMAC source address 1 */ -+ u32 sa2; /* PMAC source address 2 */ -+ u32 sa3; /* PMAC source address 3 */ -+ u32 da1; /* PMAC destination address 1 */ -+ u32 da2; /* PMAC destination address 2 */ -+ u32 da3; /* PMAC destination address 3 */ -+ u32 vlan; /* PMAC VLAN */ -+ u32 rx_ipg; /* PMAC interpacket gap in RX direction */ -+ u32 st_etype; /* PMAC special tag ethertype */ -+ u32 ewan; /* PMAC ethernet WAN group */ -+}; -+ -+struct ltq_mdio_phy_addr_reg { -+ union { -+ struct { -+ unsigned rsvd:1; -+ unsigned lnkst:2; /* Link status control */ -+ unsigned speed:2; /* Speed control */ -+ unsigned fdup:2; /* Full duplex control */ -+ unsigned fcontx:2; /* Flow control mode TX */ -+ unsigned fconrx:2; /* Flow control mode RX */ -+ unsigned addr:5; /* PHY address */ -+ } bits; -+ u16 val; -+ }; -+}; -+ -+enum ltq_mdio_phy_addr_lnkst { -+ LTQ_MDIO_PHY_ADDR_LNKST_AUTO = 0, -+ LTQ_MDIO_PHY_ADDR_LNKST_UP = 1, -+ LTQ_MDIO_PHY_ADDR_LNKST_DOWN = 2, -+}; -+ -+enum ltq_mdio_phy_addr_speed { -+ LTQ_MDIO_PHY_ADDR_SPEED_M10 = 0, -+ LTQ_MDIO_PHY_ADDR_SPEED_M100 = 1, -+ LTQ_MDIO_PHY_ADDR_SPEED_G1 = 2, -+ LTQ_MDIO_PHY_ADDR_SPEED_AUTO = 3, -+}; -+ -+enum ltq_mdio_phy_addr_fdup { -+ LTQ_MDIO_PHY_ADDR_FDUP_AUTO = 0, -+ LTQ_MDIO_PHY_ADDR_FDUP_ENABLE = 1, -+ LTQ_MDIO_PHY_ADDR_FDUP_DISABLE = 3, -+}; -+ -+enum ltq_mdio_phy_addr_fcon { -+ LTQ_MDIO_PHY_ADDR_FCON_AUTO = 0, -+ LTQ_MDIO_PHY_ADDR_FCON_ENABLE = 1, -+ LTQ_MDIO_PHY_ADDR_FCON_DISABLE = 3, -+}; -+ -+struct ltq_mii_mii_cfg_reg { -+ union { -+ struct { -+ unsigned res:1; /* Hardware reset */ -+ unsigned en:1; /* xMII interface enable */ -+ unsigned isol:1; /* xMII interface isolate */ -+ unsigned ldclkdis:1; /* Link down clock disable */ -+ unsigned rsvd:1; -+ unsigned crs:2; /* CRS sensitivity config */ -+ unsigned rgmii_ibs:1; /* RGMII In Band status */ -+ unsigned rmii:1; /* RMII ref clock direction */ -+ unsigned miirate:3; /* xMII interface clock rate */ -+ unsigned miimode:4; /* xMII interface mode */ -+ } bits; -+ u16 val; -+ }; -+}; -+ -+enum ltq_mii_mii_cfg_miirate { -+ LTQ_MII_MII_CFG_MIIRATE_M2P5 = 0, -+ LTQ_MII_MII_CFG_MIIRATE_M25 = 1, -+ LTQ_MII_MII_CFG_MIIRATE_M125 = 2, -+ LTQ_MII_MII_CFG_MIIRATE_M50 = 3, -+ LTQ_MII_MII_CFG_MIIRATE_AUTO = 4, -+}; -+ -+enum ltq_mii_mii_cfg_miimode { -+ LTQ_MII_MII_CFG_MIIMODE_MIIP = 0, -+ LTQ_MII_MII_CFG_MIIMODE_MIIM = 1, -+ LTQ_MII_MII_CFG_MIIMODE_RMIIP = 2, -+ LTQ_MII_MII_CFG_MIIMODE_RMIIM = 3, -+ LTQ_MII_MII_CFG_MIIMODE_RGMII = 4, -+}; -+ -+struct ltq_eth_priv { -+ struct ltq_dma_device *dma_dev; -+ struct mii_dev *bus; -+ struct eth_device *dev; -+ struct phy_device *phymap[LTQ_ETHSW_MAX_GMAC]; -+ int rx_num; -+}; -+ -+enum ltq_mdio_mbusy { -+ LTQ_MDIO_MBUSY_IDLE = 0, -+ LTQ_MDIO_MBUSY_BUSY = 1, -+}; -+ -+enum ltq_mdio_op { -+ LTQ_MDIO_OP_WRITE = 1, -+ LTQ_MDIO_OP_READ = 2, -+}; -+ -+struct ltq_mdio_access { -+ union { -+ struct { -+ unsigned rsvd:3; -+ unsigned mbusy:1; -+ unsigned op:2; -+ unsigned phyad:5; -+ unsigned regad:5; -+ } bits; -+ u16 val; -+ }; -+}; -+ -+enum LTQ_ETH_PORT_FLAGS { -+ LTQ_ETH_PORT_NONE = 0, -+ LTQ_ETH_PORT_PHY = 1, -+ LTQ_ETH_PORT_SWITCH = (1 << 1), -+ LTQ_ETH_PORT_MAC = (1 << 2), -+}; -+ -+struct ltq_eth_port_config { -+ u8 num; -+ u8 phy_addr; -+ u16 flags; -+ phy_interface_t phy_if; -+}; -+ -+struct ltq_eth_board_config { -+ const struct ltq_eth_port_config *ports; -+ int num_ports; -+}; -+ -+static const struct ltq_eth_port_config eth_port_config[] = { -+ /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */ -+ { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, -+ /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */ -+ { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, -+}; -+ -+static const struct ltq_eth_board_config board_config = { -+ .ports = eth_port_config, -+ .num_ports = ARRAY_SIZE(eth_port_config), -+}; -+ -+static struct ltq_ethsw_mac_pdi_regs *ltq_ethsw_mac_pdi_regs = -+ (struct ltq_ethsw_mac_pdi_regs *) CKSEG1ADDR(LTQ_SWITCH_MAC_PDI_0_BASE); -+ -+static struct ltq_ethsw_mdio_pdi_regs *ltq_ethsw_mdio_pdi_regs = -+ (struct ltq_ethsw_mdio_pdi_regs *) CKSEG1ADDR(LTQ_SWITCH_MDIO_PDI_BASE); -+ -+static struct ltq_ethsw_mii_pdi_regs *ltq_ethsw_mii_pdi_regs = -+ (struct ltq_ethsw_mii_pdi_regs *) CKSEG1ADDR(LTQ_SWITCH_MII_PDI_BASE); -+ -+static struct ltq_ethsw_pmac_pdi_regs *ltq_ethsw_pmac_pdi_regs = -+ (struct ltq_ethsw_pmac_pdi_regs *) CKSEG1ADDR(LTQ_SWITCH_PMAC_PDI_BASE); -+ -+ -+#define MAX_DMA_CHAN 0x8 -+#define MAX_DMA_CRC_LEN 0x4 -+#define MAX_DMA_DATA_LEN 0x600 -+ -+/* use 2 static channels for TX/RX -+ depending on the SoC we need to use different DMA channels for ethernet */ -+#define LTQ_ETOP_TX_CHANNEL 1 -+#define LTQ_ETOP_RX_CHANNEL 0 -+ -+#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) -+#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) -+ -+#define DRV_VERSION "1.0" -+ -+static void __iomem *ltq_vrx200_membase; -+ -+struct ltq_vrx200_chan { -+ int idx; -+ int tx_free; -+ struct net_device *netdev; -+ struct napi_struct napi; -+ struct ltq_dma_channel dma; -+ struct sk_buff *skb[LTQ_DESC_NUM]; -+}; -+ -+struct ltq_vrx200_priv { -+ struct net_device *netdev; -+ struct ltq_eth_data *pldata; -+ struct resource *res; -+ -+ struct mii_bus *mii_bus; -+ struct phy_device *phydev; -+ -+ struct ltq_vrx200_chan ch[MAX_DMA_CHAN]; -+ int tx_free[MAX_DMA_CHAN >> 1]; -+ -+ spinlock_t lock; -+ -+ struct clk *clk_ppe; -+}; -+ -+static int ltq_vrx200_mdio_wr(struct mii_bus *bus, int phy_addr, -+ int phy_reg, u16 phy_data); -+ -+static int -+ltq_vrx200_alloc_skb(struct ltq_vrx200_chan *ch) -+{ -+ ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN); -+ if (!ch->skb[ch->dma.desc]) -+ return -ENOMEM; -+ ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL, -+ ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN, -+ DMA_FROM_DEVICE); -+ ch->dma.desc_base[ch->dma.desc].addr = -+ CPHYSADDR(ch->skb[ch->dma.desc]->data); -+ ch->dma.desc_base[ch->dma.desc].ctl = -+ LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) | -+ MAX_DMA_DATA_LEN; -+ skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN); -+ return 0; -+} -+ -+static void -+ltq_vrx200_hw_receive(struct ltq_vrx200_chan *ch) -+{ -+ struct ltq_vrx200_priv *priv = netdev_priv(ch->netdev); -+ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; -+ struct sk_buff *skb = ch->skb[ch->dma.desc]; -+ int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&priv->lock, flags); -+ if (ltq_vrx200_alloc_skb(ch)) { -+ netdev_err(ch->netdev, -+ "failed to allocate new rx buffer, stopping DMA\n"); -+ ltq_dma_close(&ch->dma); -+ } -+ ch->dma.desc++; -+ ch->dma.desc %= LTQ_DESC_NUM; -+ spin_unlock_irqrestore(&priv->lock, flags); -+ -+ skb_put(skb, len); -+ skb->dev = ch->netdev; -+ skb->protocol = eth_type_trans(skb, ch->netdev); -+ netif_receive_skb(skb); -+} -+ -+static int -+ltq_vrx200_poll_rx(struct napi_struct *napi, int budget) -+{ -+ struct ltq_vrx200_chan *ch = container_of(napi, -+ struct ltq_vrx200_chan, napi); -+ struct ltq_vrx200_priv *priv = netdev_priv(ch->netdev); -+ int rx = 0; -+ int complete = 0; -+ unsigned long flags; -+ -+ while ((rx < budget) && !complete) { -+ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; -+ -+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { -+ ltq_vrx200_hw_receive(ch); -+ rx++; -+ } else { -+ complete = 1; -+ } -+ } -+ if (complete || !rx) { -+ napi_complete(&ch->napi); -+ spin_lock_irqsave(&priv->lock, flags); -+ ltq_dma_ack_irq(&ch->dma); -+ spin_unlock_irqrestore(&priv->lock, flags); -+ } -+ return rx; -+} -+ -+static int -+ltq_vrx200_poll_tx(struct napi_struct *napi, int budget) -+{ -+ struct ltq_vrx200_chan *ch = -+ container_of(napi, struct ltq_vrx200_chan, napi); -+ struct ltq_vrx200_priv *priv = netdev_priv(ch->netdev); -+ struct netdev_queue *txq = -+ netdev_get_tx_queue(ch->netdev, ch->idx >> 1); -+ unsigned long flags; -+ -+ spin_lock_irqsave(&priv->lock, flags); -+ while ((ch->dma.desc_base[ch->tx_free].ctl & -+ (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) { -+ dev_kfree_skb_any(ch->skb[ch->tx_free]); -+ ch->skb[ch->tx_free] = NULL; -+ memset(&ch->dma.desc_base[ch->tx_free], 0, -+ sizeof(struct ltq_dma_desc)); -+ ch->tx_free++; -+ ch->tx_free %= LTQ_DESC_NUM; -+ } -+ spin_unlock_irqrestore(&priv->lock, flags); -+ -+ if (netif_tx_queue_stopped(txq)) -+ netif_tx_start_queue(txq); -+ napi_complete(&ch->napi); -+ spin_lock_irqsave(&priv->lock, flags); -+ ltq_dma_ack_irq(&ch->dma); -+ spin_unlock_irqrestore(&priv->lock, flags); -+ return 1; -+} -+ -+static irqreturn_t -+ltq_vrx200_dma_irq(int irq, void *_priv) -+{ -+ struct ltq_vrx200_priv *priv = _priv; -+ int ch = irq - LTQ_DMA_ETOP; -+ -+ napi_schedule(&priv->ch[ch].napi); -+ return IRQ_HANDLED; -+} -+ -+static void -+ltq_vrx200_free_channel(struct net_device *dev, struct ltq_vrx200_chan *ch) -+{ -+ struct ltq_vrx200_priv *priv = netdev_priv(dev); -+ -+ ltq_dma_free(&ch->dma); -+ if (ch->dma.irq) -+ free_irq(ch->dma.irq, priv); -+ if (IS_RX(ch->idx)) { -+ int desc; -+ for (desc = 0; desc < LTQ_DESC_NUM; desc++) -+ dev_kfree_skb_any(ch->skb[ch->dma.desc]); -+ } -+} -+ -+static void -+ltq_vrx200_hw_exit(struct net_device *dev) -+{ -+ struct ltq_vrx200_priv *priv = netdev_priv(dev); -+ int i; -+ -+ clk_disable(priv->clk_ppe); -+ -+ for (i = 0; i < MAX_DMA_CHAN; i++) -+ if (IS_TX(i) || IS_RX(i)) -+ ltq_vrx200_free_channel(dev, &priv->ch[i]); -+} -+ -+static void *ltq_eth_phy_addr_reg(int num) -+{ -+ switch (num) { -+ case 0: -+ return <q_ethsw_mdio_pdi_regs->phy_addr_0; -+ case 1: -+ return <q_ethsw_mdio_pdi_regs->phy_addr_1; -+ case 2: -+ return <q_ethsw_mdio_pdi_regs->phy_addr_2; -+ case 3: -+ return <q_ethsw_mdio_pdi_regs->phy_addr_3; -+ case 4: -+ return <q_ethsw_mdio_pdi_regs->phy_addr_4; -+ case 5: -+ return <q_ethsw_mdio_pdi_regs->phy_addr_5; -+ } -+ -+ return NULL; -+} -+ -+static void *ltq_eth_mii_cfg_reg(int num) -+{ -+ switch (num) { -+ case 0: -+ return <q_ethsw_mii_pdi_regs->mii_cfg0; -+ case 1: -+ return <q_ethsw_mii_pdi_regs->mii_cfg1; -+ case 2: -+ return <q_ethsw_mii_pdi_regs->mii_cfg2; -+ case 3: -+ return <q_ethsw_mii_pdi_regs->mii_cfg3; -+ case 4: -+ return <q_ethsw_mii_pdi_regs->mii_cfg4; -+ case 5: -+ return <q_ethsw_mii_pdi_regs->mii_cfg5; -+ } -+ -+ return NULL; -+} -+ -+static void ltq_eth_gmac_update(struct phy_device *phydev, int num) -+{ -+ struct ltq_mdio_phy_addr_reg phy_addr_reg; -+ struct ltq_mii_mii_cfg_reg mii_cfg_reg; -+ void *phy_addr = ltq_eth_phy_addr_reg(num); -+ void *mii_cfg = ltq_eth_mii_cfg_reg(num); -+ -+ phy_addr_reg.val = ltq_r32(phy_addr); -+ mii_cfg_reg.val = ltq_r32(mii_cfg); -+ -+ phy_addr_reg.bits.addr = phydev->addr; -+ -+ if (phydev->link) -+ phy_addr_reg.bits.lnkst = LTQ_MDIO_PHY_ADDR_LNKST_UP; -+ else -+ phy_addr_reg.bits.lnkst = LTQ_MDIO_PHY_ADDR_LNKST_DOWN; -+ -+ switch (phydev->speed) { -+ case SPEED_1000: -+ phy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_G1; -+ mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M125; -+ break; -+ case SPEED_100: -+ phy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_M100; -+ switch (mii_cfg_reg.bits.miimode) { -+ case LTQ_MII_MII_CFG_MIIMODE_RMIIM: -+ case LTQ_MII_MII_CFG_MIIMODE_RMIIP: -+ mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M50; -+ break; -+ default: -+ mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M25; -+ break; -+ } -+ break; -+ default: -+ phy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_M10; -+ mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M2P5; -+ break; -+ } -+ -+ if (phydev->duplex == DUPLEX_FULL) -+ phy_addr_reg.bits.fdup = LTQ_MDIO_PHY_ADDR_FDUP_ENABLE; -+ else -+ phy_addr_reg.bits.fdup = LTQ_MDIO_PHY_ADDR_FDUP_DISABLE; -+ -+ dbg_ltq_writel(phy_addr, phy_addr_reg.val); -+ dbg_ltq_writel(mii_cfg, mii_cfg_reg.val); -+ udelay(1); -+} -+ -+ -+static void ltq_eth_port_config(struct ltq_vrx200_priv *priv, -+ const struct ltq_eth_port_config *port) -+{ -+ struct ltq_mii_mii_cfg_reg mii_cfg_reg; -+ void *mii_cfg = ltq_eth_mii_cfg_reg(port->num); -+ int setup_gpio = 0; -+ -+ mii_cfg_reg.val = ltq_r32(mii_cfg); -+ -+ -+ switch (port->num) { -+ case 0: /* xMII0 */ -+ case 1: /* xMII1 */ -+ switch (port->phy_if) { -+ case PHY_INTERFACE_MODE_MII: -+ if (port->flags & LTQ_ETH_PORT_PHY) -+ /* MII MAC mode, connected to external PHY */ -+ mii_cfg_reg.bits.miimode = -+ LTQ_MII_MII_CFG_MIIMODE_MIIM; -+ else -+ /* MII PHY mode, connected to external MAC */ -+ mii_cfg_reg.bits.miimode = -+ LTQ_MII_MII_CFG_MIIMODE_MIIP; -+ setup_gpio = 1; -+ break; -+ case PHY_INTERFACE_MODE_RMII: -+ if (port->flags & LTQ_ETH_PORT_PHY) -+ /* RMII MAC mode, connected to external PHY */ -+ mii_cfg_reg.bits.miimode = -+ LTQ_MII_MII_CFG_MIIMODE_RMIIM; -+ else -+ /* RMII PHY mode, connected to external MAC */ -+ mii_cfg_reg.bits.miimode = -+ LTQ_MII_MII_CFG_MIIMODE_RMIIP; -+ setup_gpio = 1; -+ break; -+ case PHY_INTERFACE_MODE_RGMII: -+ /* RGMII MAC mode, connected to external PHY */ -+ mii_cfg_reg.bits.miimode = -+ LTQ_MII_MII_CFG_MIIMODE_RGMII; -+ setup_gpio = 1; -+ break; -+ default: -+ break; -+ } -+ break; -+ case 2: /* internal GPHY0 */ -+ case 3: /* internal GPHY0 */ -+ case 4: /* internal GPHY1 */ -+ switch (port->phy_if) { -+ case PHY_INTERFACE_MODE_MII: -+ case PHY_INTERFACE_MODE_GMII: -+ /* MII MAC mode, connected to internal GPHY */ -+ mii_cfg_reg.bits.miimode = -+ LTQ_MII_MII_CFG_MIIMODE_MIIM; -+ setup_gpio = 1; -+ break; -+ default: -+ break; -+ } -+ break; -+ case 5: /* internal GPHY1 or xMII2 */ -+ switch (port->phy_if) { -+ case PHY_INTERFACE_MODE_MII: -+ /* MII MAC mode, connected to internal GPHY */ -+ mii_cfg_reg.bits.miimode = -+ LTQ_MII_MII_CFG_MIIMODE_MIIM; -+ setup_gpio = 1; -+ break; -+ case PHY_INTERFACE_MODE_RGMII: -+ /* RGMII MAC mode, connected to external PHY */ -+ mii_cfg_reg.bits.miimode = -+ LTQ_MII_MII_CFG_MIIMODE_RGMII; -+ setup_gpio = 1; -+ break; -+ default: -+ break; -+ } -+ break; -+ default: -+ break; -+ } -+ -+ /* Enable MII interface */ -+ mii_cfg_reg.bits.en = port->flags ? 1 : 0; -+ dbg_ltq_writel(mii_cfg, mii_cfg_reg.val); -+ -+} -+ -+static void ltq_eth_gmac_init(int num) -+{ -+ struct ltq_mdio_phy_addr_reg phy_addr_reg; -+ struct ltq_mii_mii_cfg_reg mii_cfg_reg; -+ void *phy_addr = ltq_eth_phy_addr_reg(num); -+ void *mii_cfg = ltq_eth_mii_cfg_reg(num); -+ struct ltq_ethsw_mac_pdi_x_regs *mac_pdi_regs; -+ -+ mac_pdi_regs = <q_ethsw_mac_pdi_regs->mac[num]; -+ -+ /* Reset PHY status to link down */ -+ phy_addr_reg.val = ltq_r32(phy_addr); -+ phy_addr_reg.bits.addr = num; -+ phy_addr_reg.bits.lnkst = LTQ_MDIO_PHY_ADDR_LNKST_DOWN; -+ phy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_M10; -+ phy_addr_reg.bits.fdup = LTQ_MDIO_PHY_ADDR_FDUP_DISABLE; -+ dbg_ltq_writel(phy_addr, phy_addr_reg.val); -+ -+ /* Reset and disable MII interface */ -+ mii_cfg_reg.val = ltq_r32(mii_cfg); -+ mii_cfg_reg.bits.en = 0; -+ mii_cfg_reg.bits.res = 1; -+ mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M2P5; -+ dbg_ltq_writel(mii_cfg, mii_cfg_reg.val); -+ -+ /* -+ * Enable padding of short frames, enable frame checksum generation -+ * in transmit direction -+ */ -+ dbg_ltq_writel(&mac_pdi_regs->ctrl_0, LTQ_ETHSW_MAC_CTRL0_PADEN | -+ LTQ_ETHSW_MAC_CTRL0_FCS); -+ -+ /* Set inter packet gap size to 12 bytes */ -+ dbg_ltq_writel(&mac_pdi_regs->ctrl_1, 12); -+ -+ /* -+ * Configure frame length checks: -+ * - allow jumbo frames -+ * - enable long length check -+ * - enable short length without VLAN tags -+ */ -+ dbg_ltq_writel(&mac_pdi_regs->ctrl_2, LTQ_ETHSW_MAC_CTRL2_MLEN | -+ LTQ_ETHSW_MAC_CTRL2_LCHKL | -+ LTQ_ETHSW_MAC_CTRL2_LCHKS_UNTAG); -+} -+ -+ -+static void ltq_eth_pmac_init(void) -+{ -+ struct ltq_ethsw_mac_pdi_x_regs *mac_pdi_regs; -+ -+ mac_pdi_regs = <q_ethsw_mac_pdi_regs->mac[LTQ_ETHSW_PMAC]; -+ -+ /* -+ * Enable padding of short frames, enable frame checksum generation -+ * in transmit direction -+ */ -+ dbg_ltq_writel(&mac_pdi_regs->ctrl_0, LTQ_ETHSW_MAC_CTRL0_PADEN | -+ LTQ_ETHSW_MAC_CTRL0_FCS); -+ -+ /* -+ * Configure frame length checks: -+ * - allow jumbo frames -+ * - enable long length check -+ * - enable short length without VLAN tags -+ */ -+ dbg_ltq_writel(&mac_pdi_regs->ctrl_2, LTQ_ETHSW_MAC_CTRL2_MLEN | -+ LTQ_ETHSW_MAC_CTRL2_LCHKL | -+ LTQ_ETHSW_MAC_CTRL2_LCHKS_UNTAG); -+ -+ /* -+ * Apply workaround for buffer congestion: -+ * - shorten preambel to 1 byte -+ * - set minimum inter packet gap size to 7 bytes -+ * - enable receive buffer bypass mode -+ */ -+ dbg_ltq_writel(&mac_pdi_regs->ctrl_1, LTQ_ETHSW_MAC_CTRL1_SHORTPRE | 7); -+ dbg_ltq_writel(&mac_pdi_regs->ctrl_6, -+ (6 << LTQ_ETHSW_MAC_CTRL6_RBUF_DLY_WP_SHIFT) | -+ LTQ_ETHSW_MAC_CTRL6_RXBUF_BYPASS); -+ -+ /* Set request assertion threshold to 8, IPG counter to 11 */ -+ dbg_ltq_writel(<q_ethsw_pmac_pdi_regs->rx_ipg, 0x8B); -+ -+ /* -+ * Configure frame header control: -+ * - enable reaction on pause frames (flow control) -+ * - remove CRC for packets from PMAC to DMA -+ * - add CRC for packets from DMA to PMAC -+ */ -+ dbg_ltq_writel(<q_ethsw_pmac_pdi_regs->hd_ctl, LTQ_ETHSW_PMAC_HD_CTL_FC | -+ /*LTQ_ETHSW_PMAC_HD_CTL_RC | */LTQ_ETHSW_PMAC_HD_CTL_AC); -+} -+ -+static int -+ltq_vrx200_hw_init(struct net_device *dev) -+{ -+ struct ltq_vrx200_priv *priv = netdev_priv(dev); -+ int err = 0; -+ int i; -+ -+ netdev_info(dev, "setting up dma\n"); -+ ltq_dma_init_port(DMA_PORT_ETOP); -+ -+ netdev_info(dev, "setting up pmu\n"); -+ clk_enable(priv->clk_ppe); -+ -+ /* Reset ethernet and switch subsystems */ -+ netdev_info(dev, "reset core\n"); -+ ltq_reset_once(BIT(8), 10); -+ -+ /* Enable switch macro */ -+ ltq_setbits(<q_ethsw_mdio_pdi_regs->glob_ctrl, -+ LTQ_ETHSW_GLOB_CTRL_SE); -+ -+ /* Disable MDIO auto-polling for all ports */ -+ dbg_ltq_writel(<q_ethsw_mdio_pdi_regs->mdc_cfg_0, 0); -+ -+ /* -+ * Enable and set MDIO management clock to 2.5 MHz. This is the -+ * maximum clock for FE PHYs. -+ * Formula for clock is: -+ * -+ * 50 MHz -+ * x = ----------- - 1 -+ * 2 * f_MDC -+ */ -+ dbg_ltq_writel(<q_ethsw_mdio_pdi_regs->mdc_cfg_1, -+ LTQ_ETHSW_MDC_CFG1_MCEN | 9); -+ -+ /* Init MAC connected to CPU */ -+ ltq_eth_pmac_init(); -+ -+ /* Init MACs connected to external MII interfaces */ -+ for (i = 0; i < LTQ_ETHSW_MAX_GMAC; i++) -+ ltq_eth_gmac_init(i); -+ -+ for (i = 0; i < MAX_DMA_CHAN && !err; i++) { -+ int irq = LTQ_DMA_ETOP + i; -+ struct ltq_vrx200_chan *ch = &priv->ch[i]; -+ -+ ch->idx = ch->dma.nr = i; -+ -+ if (IS_TX(i)) { -+ ltq_dma_alloc_tx(&ch->dma); -+ err = request_irq(irq, ltq_vrx200_dma_irq, IRQF_DISABLED, -+ "vrx200_tx", priv); -+ } else if (IS_RX(i)) { -+ ltq_dma_alloc_rx(&ch->dma); -+ for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; -+ ch->dma.desc++) -+ if (ltq_vrx200_alloc_skb(ch)) -+ err = -ENOMEM; -+ ch->dma.desc = 0; -+ err = request_irq(irq, ltq_vrx200_dma_irq, IRQF_DISABLED, -+ "vrx200_rx", priv); -+ } -+ if (!err) -+ ch->dma.irq = irq; -+ } -+ for (i = 0; i < board_config.num_ports; i++) -+ ltq_eth_port_config(priv, &board_config.ports[i]); -+ return err; -+} -+ -+static void -+ltq_vrx200_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) -+{ -+ strcpy(info->driver, "Lantiq ETOP"); -+ strcpy(info->bus_info, "internal"); -+ strcpy(info->version, DRV_VERSION); -+} -+ -+static int -+ltq_vrx200_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) -+{ -+ struct ltq_vrx200_priv *priv = netdev_priv(dev); -+ -+ return phy_ethtool_gset(priv->phydev, cmd); -+} -+ -+static int -+ltq_vrx200_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) -+{ -+ struct ltq_vrx200_priv *priv = netdev_priv(dev); -+ -+ return phy_ethtool_sset(priv->phydev, cmd); -+} -+ -+static int -+ltq_vrx200_nway_reset(struct net_device *dev) -+{ -+ struct ltq_vrx200_priv *priv = netdev_priv(dev); -+ -+ return phy_start_aneg(priv->phydev); -+} -+ -+static const struct ethtool_ops ltq_vrx200_ethtool_ops = { -+ .get_drvinfo = ltq_vrx200_get_drvinfo, -+ .get_settings = ltq_vrx200_get_settings, -+ .set_settings = ltq_vrx200_set_settings, -+ .nway_reset = ltq_vrx200_nway_reset, -+}; -+ -+static inline int ltq_mdio_poll(struct mii_bus *bus) -+{ -+ struct ltq_mdio_access acc; -+ unsigned cnt = 10000; -+ -+ while (likely(cnt--)) { -+ acc.val = ltq_r32(<q_ethsw_mdio_pdi_regs->mdio_ctrl); -+ if (!acc.bits.mbusy) -+ return 0; -+ } -+ -+ return 1; -+} -+ -+static int -+ltq_vrx200_mdio_wr(struct mii_bus *bus, int addr, int regnum, u16 val) -+{ -+ struct ltq_mdio_access acc; -+ int ret; -+ -+ acc.val = 0; -+ acc.bits.mbusy = LTQ_MDIO_MBUSY_BUSY; -+ acc.bits.op = LTQ_MDIO_OP_WRITE; -+ acc.bits.phyad = addr; -+ acc.bits.regad = regnum; -+ -+ ret = ltq_mdio_poll(bus); -+ if (ret) -+ return ret; -+ -+ dbg_ltq_writel(<q_ethsw_mdio_pdi_regs->mdio_write, val); -+ dbg_ltq_writel(<q_ethsw_mdio_pdi_regs->mdio_ctrl, acc.val); -+ -+ return 0; -+} -+ -+static int -+ltq_vrx200_mdio_rd(struct mii_bus *bus, int addr, int regnum) -+{ -+ struct ltq_mdio_access acc; -+ int ret; -+ -+ acc.val = 0; -+ acc.bits.mbusy = LTQ_MDIO_MBUSY_BUSY; -+ acc.bits.op = LTQ_MDIO_OP_READ; -+ acc.bits.phyad = addr; -+ acc.bits.regad = regnum; -+ -+ ret = ltq_mdio_poll(bus); -+ if (ret) -+ goto timeout; -+ -+ dbg_ltq_writel(<q_ethsw_mdio_pdi_regs->mdio_ctrl, acc.val); -+ -+ ret = ltq_mdio_poll(bus); -+ if (ret) -+ goto timeout; -+ -+ ret = ltq_r32(<q_ethsw_mdio_pdi_regs->mdio_read); -+ -+ return ret; -+timeout: -+ return -1; -+} -+ -+static void -+ltq_vrx200_mdio_link(struct net_device *dev) -+{ -+ struct ltq_vrx200_priv *priv = netdev_priv(dev); -+ ltq_eth_gmac_update(priv->phydev, 0); -+} -+ -+static int -+ltq_vrx200_mdio_probe(struct net_device *dev) -+{ -+ struct ltq_vrx200_priv *priv = netdev_priv(dev); -+ struct phy_device *phydev = NULL; -+ int val; -+ -+ phydev = priv->mii_bus->phy_map[0]; -+ -+ if (!phydev) { -+ netdev_err(dev, "no PHY found\n"); -+ return -ENODEV; -+ } -+ -+ phydev = phy_connect(dev, dev_name(&phydev->dev), <q_vrx200_mdio_link, -+ 0, 0); -+ -+ if (IS_ERR(phydev)) { -+ netdev_err(dev, "Could not attach to PHY\n"); -+ return PTR_ERR(phydev); -+ } -+ -+ phydev->supported &= (SUPPORTED_10baseT_Half -+ | SUPPORTED_10baseT_Full -+ | SUPPORTED_100baseT_Half -+ | SUPPORTED_100baseT_Full -+ | SUPPORTED_1000baseT_Half -+ | SUPPORTED_1000baseT_Full -+ | SUPPORTED_Autoneg -+ | SUPPORTED_MII -+ | SUPPORTED_TP); -+ phydev->advertising = phydev->supported; -+ priv->phydev = phydev; -+ -+ pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n", -+ dev->name, phydev->drv->name, -+ dev_name(&phydev->dev), phydev->irq); -+ -+ val = ltq_vrx200_mdio_rd(priv->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000); -+ val |= ADVERTIZE_MPD; -+ ltq_vrx200_mdio_wr(priv->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000, val); -+ ltq_vrx200_mdio_wr(priv->mii_bus, 0, 0, 0x1040); -+ -+ phy_start_aneg(phydev); -+ -+ return 0; -+} -+ -+static int -+ltq_vrx200_mdio_init(struct net_device *dev) -+{ -+ struct ltq_vrx200_priv *priv = netdev_priv(dev); -+ int i; -+ int err; -+ -+ priv->mii_bus = mdiobus_alloc(); -+ if (!priv->mii_bus) { -+ netdev_err(dev, "failed to allocate mii bus\n"); -+ err = -ENOMEM; -+ goto err_out; -+ } -+ -+ priv->mii_bus->priv = dev; -+ priv->mii_bus->read = ltq_vrx200_mdio_rd; -+ priv->mii_bus->write = ltq_vrx200_mdio_wr; -+ priv->mii_bus->name = "ltq_mii"; -+ snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0); -+ priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); -+ if (!priv->mii_bus->irq) { -+ err = -ENOMEM; -+ goto err_out_free_mdiobus; -+ } -+ -+ for (i = 0; i < PHY_MAX_ADDR; ++i) -+ priv->mii_bus->irq[i] = PHY_POLL; -+ -+ if (mdiobus_register(priv->mii_bus)) { -+ err = -ENXIO; -+ goto err_out_free_mdio_irq; -+ } -+ -+ if (ltq_vrx200_mdio_probe(dev)) { -+ err = -ENXIO; -+ goto err_out_unregister_bus; -+ } -+ return 0; -+ -+err_out_unregister_bus: -+ mdiobus_unregister(priv->mii_bus); -+err_out_free_mdio_irq: -+ kfree(priv->mii_bus->irq); -+err_out_free_mdiobus: -+ mdiobus_free(priv->mii_bus); -+err_out: -+ return err; -+} -+ -+static void -+ltq_vrx200_mdio_cleanup(struct net_device *dev) -+{ -+ struct ltq_vrx200_priv *priv = netdev_priv(dev); -+ -+ phy_disconnect(priv->phydev); -+ mdiobus_unregister(priv->mii_bus); -+ kfree(priv->mii_bus->irq); -+ mdiobus_free(priv->mii_bus); -+} -+ -+void phy_dump(struct net_device *dev) -+{ -+ struct ltq_vrx200_priv *priv = netdev_priv(dev); -+ int i; -+ for (i = 0; i < 0x1F; i++) { -+ unsigned int val = ltq_vrx200_mdio_rd(priv->mii_bus, 0, i); -+ printk("%d %4X\n", i, val); -+ } -+} -+ -+static int -+ltq_vrx200_open(struct net_device *dev) -+{ -+ struct ltq_vrx200_priv *priv = netdev_priv(dev); -+ int i; -+ unsigned long flags; -+ -+ for (i = 0; i < MAX_DMA_CHAN; i++) { -+ struct ltq_vrx200_chan *ch = &priv->ch[i]; -+ -+ if (!IS_TX(i) && (!IS_RX(i))) -+ continue; -+ napi_enable(&ch->napi); -+ spin_lock_irqsave(&priv->lock, flags); -+ ltq_dma_open(&ch->dma); -+ spin_unlock_irqrestore(&priv->lock, flags); -+ } -+ if (priv->phydev) { -+ phy_start(priv->phydev); -+ phy_dump(dev); -+ } -+ netif_tx_start_all_queues(dev); -+ return 0; -+} -+ -+static int -+ltq_vrx200_stop(struct net_device *dev) -+{ -+ struct ltq_vrx200_priv *priv = netdev_priv(dev); -+ int i; -+ unsigned long flags; -+ -+ netif_tx_stop_all_queues(dev); -+ if (priv->phydev) -+ phy_stop(priv->phydev); -+ for (i = 0; i < MAX_DMA_CHAN; i++) { -+ struct ltq_vrx200_chan *ch = &priv->ch[i]; -+ -+ if (!IS_RX(i) && !IS_TX(i)) -+ continue; -+ napi_disable(&ch->napi); -+ spin_lock_irqsave(&priv->lock, flags); -+ ltq_dma_close(&ch->dma); -+ spin_unlock_irqrestore(&priv->lock, flags); -+ } -+ return 0; -+} -+ -+static int -+ltq_vrx200_tx(struct sk_buff *skb, struct net_device *dev) -+{ -+ int queue = skb_get_queue_mapping(skb); -+ struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); -+ struct ltq_vrx200_priv *priv = netdev_priv(dev); -+ struct ltq_vrx200_chan *ch = &priv->ch[(queue << 1) | 1]; -+ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; -+ unsigned long flags; -+ u32 byte_offset; -+ int len; -+ -+ len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; -+ -+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { -+ netdev_err(dev, "tx ring full\n"); -+ netif_tx_stop_queue(txq); -+ return NETDEV_TX_BUSY; -+ } -+ -+ /* dma needs to start on a 16 byte aligned address */ -+ byte_offset = CPHYSADDR(skb->data) % 16; -+ ch->skb[ch->dma.desc] = skb; -+ -+ dev->trans_start = jiffies; -+ -+ spin_lock_irqsave(&priv->lock, flags); -+ desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len, -+ DMA_TO_DEVICE)) - byte_offset; -+ wmb(); -+ desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | -+ LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); -+ ch->dma.desc++; -+ ch->dma.desc %= LTQ_DESC_NUM; -+ spin_unlock_irqrestore(&priv->lock, flags); -+ -+ if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) -+ netif_tx_stop_queue(txq); -+ -+ return NETDEV_TX_OK; -+} -+ -+static int -+ltq_vrx200_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) -+{ -+ struct ltq_vrx200_priv *priv = netdev_priv(dev); -+ -+ /* TODO: mii-toll reports "No MII transceiver present!." ?!*/ -+ return phy_mii_ioctl(priv->phydev, rq, cmd); -+} -+ -+static u16 -+ltq_vrx200_select_queue(struct net_device *dev, struct sk_buff *skb) -+{ -+ /* we are currently only using the first queue */ -+ return 0; -+} -+ -+static int -+ltq_vrx200_init(struct net_device *dev) -+{ -+ struct ltq_vrx200_priv *priv = netdev_priv(dev); -+ struct sockaddr mac; -+ int err; -+ -+ ether_setup(dev); -+ dev->watchdog_timeo = 10 * HZ; -+ -+ err = ltq_vrx200_hw_init(dev); -+ if (err) -+ goto err_hw; -+ -+ memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); -+ if (!is_valid_ether_addr(mac.sa_data)) { -+ pr_warn("vrx200: invalid MAC, using random\n"); -+ random_ether_addr(mac.sa_data); -+ } -+ eth_mac_addr(dev, &mac); -+ -+ if (!ltq_vrx200_mdio_init(dev)) -+ dev->ethtool_ops = <q_vrx200_ethtool_ops; -+ else -+ pr_warn("vrx200: mdio probe failed\n");; -+ return 0; -+ -+err_hw: -+ ltq_vrx200_hw_exit(dev); -+ return err; -+} -+ -+static void -+ltq_vrx200_tx_timeout(struct net_device *dev) -+{ -+ int err; -+ -+ ltq_vrx200_hw_exit(dev); -+ err = ltq_vrx200_hw_init(dev); -+ if (err) -+ goto err_hw; -+ dev->trans_start = jiffies; -+ netif_wake_queue(dev); -+ return; -+ -+err_hw: -+ ltq_vrx200_hw_exit(dev); -+ netdev_err(dev, "failed to restart vrx200 after TX timeout\n"); -+} -+ -+static const struct net_device_ops ltq_eth_netdev_ops = { -+ .ndo_open = ltq_vrx200_open, -+ .ndo_stop = ltq_vrx200_stop, -+ .ndo_start_xmit = ltq_vrx200_tx, -+ .ndo_change_mtu = eth_change_mtu, -+ .ndo_do_ioctl = ltq_vrx200_ioctl, -+ .ndo_set_mac_address = eth_mac_addr, -+ .ndo_validate_addr = eth_validate_addr, -+ .ndo_select_queue = ltq_vrx200_select_queue, -+ .ndo_init = ltq_vrx200_init, -+ .ndo_tx_timeout = ltq_vrx200_tx_timeout, -+}; -+ -+static int __devinit -+ltq_vrx200_probe(struct platform_device *pdev) -+{ -+ struct net_device *dev; -+ struct ltq_vrx200_priv *priv; -+ struct resource *res; -+ int err; -+ int i; -+ -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ dev_err(&pdev->dev, "failed to get vrx200 resource\n"); -+ err = -ENOENT; -+ goto err_out; -+ } -+ -+ res = devm_request_mem_region(&pdev->dev, res->start, -+ resource_size(res), dev_name(&pdev->dev)); -+ if (!res) { -+ dev_err(&pdev->dev, "failed to request vrx200 resource\n"); -+ err = -EBUSY; -+ goto err_out; -+ } -+ -+ ltq_vrx200_membase = devm_ioremap_nocache(&pdev->dev, -+ res->start, resource_size(res)); -+ if (!ltq_vrx200_membase) { -+ dev_err(&pdev->dev, "failed to remap vrx200 engine %d\n", -+ pdev->id); -+ err = -ENOMEM; -+ goto err_out; -+ } -+ -+ if (ltq_gpio_request(&pdev->dev, 42, 2, 1, "MDIO") || -+ ltq_gpio_request(&pdev->dev, 43, 2, 1, "MDC")) { -+ dev_err(&pdev->dev, "failed to request MDIO gpios\n"); -+ err = -EBUSY; -+ goto err_out; -+ } -+ -+ dev = alloc_etherdev_mq(sizeof(struct ltq_vrx200_priv), 4); -+ strcpy(dev->name, "eth%d"); -+ dev->netdev_ops = <q_eth_netdev_ops; -+ priv = netdev_priv(dev); -+ priv->res = res; -+ priv->pldata = dev_get_platdata(&pdev->dev); -+ priv->netdev = dev; -+ -+ priv->clk_ppe = clk_get(&pdev->dev, NULL); -+ if (IS_ERR(priv->clk_ppe)) -+ return PTR_ERR(priv->clk_ppe); -+ -+ spin_lock_init(&priv->lock); -+ -+ for (i = 0; i < MAX_DMA_CHAN; i++) { -+ if (IS_TX(i)) -+ netif_napi_add(dev, &priv->ch[i].napi, -+ ltq_vrx200_poll_tx, 8); -+ else if (IS_RX(i)) -+ netif_napi_add(dev, &priv->ch[i].napi, -+ ltq_vrx200_poll_rx, 32); -+ priv->ch[i].netdev = dev; -+ } -+ -+ err = register_netdev(dev); -+ if (err) -+ goto err_free; -+ -+ platform_set_drvdata(pdev, dev); -+ return 0; -+ -+err_free: -+ kfree(dev); -+err_out: -+ return err; -+} -+ -+static int __devexit -+ltq_vrx200_remove(struct platform_device *pdev) -+{ -+ struct net_device *dev = platform_get_drvdata(pdev); -+ -+ if (dev) { -+ netif_tx_stop_all_queues(dev); -+ ltq_vrx200_hw_exit(dev); -+ ltq_vrx200_mdio_cleanup(dev); -+ unregister_netdev(dev); -+ } -+ return 0; -+} -+ -+static struct platform_driver ltq_mii_driver = { -+ .probe = ltq_vrx200_probe, -+ .remove = __devexit_p(ltq_vrx200_remove), -+ .driver = { -+ .name = "ltq_vrx200", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+module_platform_driver(ltq_mii_driver); -+ -+MODULE_AUTHOR("John Crispin "); -+MODULE_DESCRIPTION("Lantiq SoC ETOP"); -+MODULE_LICENSE("GPL"); diff --git a/target/linux/lantiq/patches-3.3/0040-MIPS-NET-several-fixes-to-etop-driver.patch b/target/linux/lantiq/patches-3.3/0040-MIPS-NET-several-fixes-to-etop-driver.patch deleted file mode 100644 index d859ad1720..0000000000 --- a/target/linux/lantiq/patches-3.3/0040-MIPS-NET-several-fixes-to-etop-driver.patch +++ /dev/null @@ -1,440 +0,0 @@ -From 45af082d0feb0c458d7636f6453702b8dcdfc823 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Wed, 21 Mar 2012 18:14:06 +0100 -Subject: [PATCH 40/70] MIPS: NET: several fixes to etop driver - ---- - drivers/net/ethernet/lantiq_etop.c | 208 +++++++++++++++++++----------------- - 1 files changed, 108 insertions(+), 100 deletions(-) - ---- a/drivers/net/ethernet/lantiq_etop.c -+++ b/drivers/net/ethernet/lantiq_etop.c -@@ -103,15 +103,6 @@ - /* the newer xway socks have a embedded 3/7 port gbit multiplexer */ - #define ltq_has_gbit() (ltq_is_ar9() || ltq_is_vr9()) - --/* use 2 static channels for TX/RX -- depending on the SoC we need to use different DMA channels for ethernet */ --#define LTQ_ETOP_TX_CHANNEL 1 --#define LTQ_ETOP_RX_CHANNEL ((ltq_is_ase()) ? (5) : \ -- ((ltq_has_gbit()) ? (0) : (6))) -- --#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) --#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) -- - #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x)) - #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y)) - #define ltq_etop_w32_mask(x, y, z) \ -@@ -128,8 +119,8 @@ static void __iomem *ltq_etop_membase; - static void __iomem *ltq_gbit_membase; - - struct ltq_etop_chan { -- int idx; - int tx_free; -+ int irq; - struct net_device *netdev; - struct napi_struct napi; - struct ltq_dma_channel dma; -@@ -145,8 +136,8 @@ struct ltq_etop_priv { - struct mii_bus *mii_bus; - struct phy_device *phydev; - -- struct ltq_etop_chan ch[MAX_DMA_CHAN]; -- int tx_free[MAX_DMA_CHAN >> 1]; -+ struct ltq_etop_chan txch; -+ struct ltq_etop_chan rxch; - - spinlock_t lock; - -@@ -207,8 +198,10 @@ ltq_etop_poll_rx(struct napi_struct *nap - { - struct ltq_etop_chan *ch = container_of(napi, - struct ltq_etop_chan, napi); -+ struct ltq_etop_priv *priv = netdev_priv(ch->netdev); - int rx = 0; - int complete = 0; -+ unsigned long flags; - - while ((rx < budget) && !complete) { - struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; -@@ -222,7 +215,9 @@ ltq_etop_poll_rx(struct napi_struct *nap - } - if (complete || !rx) { - napi_complete(&ch->napi); -+ spin_lock_irqsave(&priv->lock, flags); - ltq_dma_ack_irq(&ch->dma); -+ spin_unlock_irqrestore(&priv->lock, flags); - } - return rx; - } -@@ -234,7 +229,7 @@ ltq_etop_poll_tx(struct napi_struct *nap - container_of(napi, struct ltq_etop_chan, napi); - struct ltq_etop_priv *priv = netdev_priv(ch->netdev); - struct netdev_queue *txq = -- netdev_get_tx_queue(ch->netdev, ch->idx >> 1); -+ netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1); - unsigned long flags; - - spin_lock_irqsave(&priv->lock, flags); -@@ -252,7 +247,9 @@ ltq_etop_poll_tx(struct napi_struct *nap - if (netif_tx_queue_stopped(txq)) - netif_tx_start_queue(txq); - napi_complete(&ch->napi); -+ spin_lock_irqsave(&priv->lock, flags); - ltq_dma_ack_irq(&ch->dma); -+ spin_unlock_irqrestore(&priv->lock, flags); - return 1; - } - -@@ -260,9 +257,10 @@ static irqreturn_t - ltq_etop_dma_irq(int irq, void *_priv) - { - struct ltq_etop_priv *priv = _priv; -- int ch = irq - LTQ_DMA_ETOP; -- -- napi_schedule(&priv->ch[ch].napi); -+ if (irq == priv->txch.dma.irq) -+ napi_schedule(&priv->txch.napi); -+ else -+ napi_schedule(&priv->rxch.napi); - return IRQ_HANDLED; - } - -@@ -274,7 +272,7 @@ ltq_etop_free_channel(struct net_device - ltq_dma_free(&ch->dma); - if (ch->dma.irq) - free_irq(ch->dma.irq, priv); -- if (IS_RX(ch->idx)) { -+ if (ch == &priv->txch) { - int desc; - for (desc = 0; desc < LTQ_DESC_NUM; desc++) - dev_kfree_skb_any(ch->skb[ch->dma.desc]); -@@ -285,7 +283,6 @@ static void - ltq_etop_hw_exit(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int i; - - clk_disable(priv->clk_ppe); - -@@ -297,9 +294,8 @@ ltq_etop_hw_exit(struct net_device *dev) - clk_disable(priv->clk_ephycgu); - } - -- for (i = 0; i < MAX_DMA_CHAN; i++) -- if (IS_TX(i) || IS_RX(i)) -- ltq_etop_free_channel(dev, &priv->ch[i]); -+ ltq_etop_free_channel(dev, &priv->txch); -+ ltq_etop_free_channel(dev, &priv->rxch); - } - - static void -@@ -327,8 +323,6 @@ ltq_etop_hw_init(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); - unsigned int mii_mode = priv->pldata->mii_mode; -- int err = 0; -- int i; - - clk_enable(priv->clk_ppe); - -@@ -370,31 +364,50 @@ ltq_etop_hw_init(struct net_device *dev) - /* enable crc generation */ - ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG); - -+ return 0; -+} -+ -+static int -+ltq_etop_dma_init(struct net_device *dev) -+{ -+ struct ltq_etop_priv *priv = netdev_priv(dev); -+ int tx = 1; -+ int rx = ((ltq_is_ase()) ? (5) : \ -+ ((ltq_is_ar9()) ? (0) : (6))); -+ int tx_irq = LTQ_DMA_ETOP + tx; -+ int rx_irq = LTQ_DMA_ETOP + rx; -+ int err; -+ - ltq_dma_init_port(DMA_PORT_ETOP); - -- for (i = 0; i < MAX_DMA_CHAN && !err; i++) { -- int irq = LTQ_DMA_ETOP + i; -- struct ltq_etop_chan *ch = &priv->ch[i]; -- -- ch->idx = ch->dma.nr = i; -- -- if (IS_TX(i)) { -- ltq_dma_alloc_tx(&ch->dma); -- err = request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, -- "etop_tx", priv); -- } else if (IS_RX(i)) { -- ltq_dma_alloc_rx(&ch->dma); -- for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM; -- ch->dma.desc++) -- if (ltq_etop_alloc_skb(ch)) -- err = -ENOMEM; -- ch->dma.desc = 0; -- err = request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED, -- "etop_rx", priv); -+ priv->txch.dma.nr = tx; -+ ltq_dma_alloc_tx(&priv->txch.dma); -+ err = request_irq(tx_irq, ltq_etop_dma_irq, IRQF_DISABLED, -+ "eth_tx", priv); -+ if (err) { -+ netdev_err(dev, "failed to allocate tx irq\n"); -+ goto err_out; -+ } -+ priv->txch.dma.irq = tx_irq; -+ -+ priv->rxch.dma.nr = rx; -+ ltq_dma_alloc_rx(&priv->rxch.dma); -+ for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM; -+ priv->rxch.dma.desc++) { -+ if (ltq_etop_alloc_skb(&priv->rxch)) { -+ netdev_err(dev, "failed to allocate skbs\n"); -+ err = -ENOMEM; -+ goto err_out; - } -- if (!err) -- ch->dma.irq = irq; - } -+ priv->rxch.dma.desc = 0; -+ err = request_irq(rx_irq, ltq_etop_dma_irq, IRQF_DISABLED, -+ "eth_rx", priv); -+ if (err) -+ netdev_err(dev, "failed to allocate rx irq\n"); -+ else -+ priv->rxch.dma.irq = rx_irq; -+err_out: - return err; - } - -@@ -411,7 +424,10 @@ ltq_etop_get_settings(struct net_device - { - struct ltq_etop_priv *priv = netdev_priv(dev); - -- return phy_ethtool_gset(priv->phydev, cmd); -+ if (priv->phydev) -+ return phy_ethtool_gset(priv->phydev, cmd); -+ else -+ return 0; - } - - static int -@@ -419,7 +435,10 @@ ltq_etop_set_settings(struct net_device - { - struct ltq_etop_priv *priv = netdev_priv(dev); - -- return phy_ethtool_sset(priv->phydev, cmd); -+ if (priv->phydev) -+ return phy_ethtool_sset(priv->phydev, cmd); -+ else -+ return 0; - } - - static int -@@ -427,7 +446,10 @@ ltq_etop_nway_reset(struct net_device *d - { - struct ltq_etop_priv *priv = netdev_priv(dev); - -- return phy_start_aneg(priv->phydev); -+ if (priv->phydev) -+ return phy_start_aneg(priv->phydev); -+ else -+ return 0; - } - - static const struct ethtool_ops ltq_etop_ethtool_ops = { -@@ -620,18 +642,19 @@ static int - ltq_etop_open(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int i; -+ unsigned long flags; - -- for (i = 0; i < MAX_DMA_CHAN; i++) { -- struct ltq_etop_chan *ch = &priv->ch[i]; -+ napi_enable(&priv->txch.napi); -+ napi_enable(&priv->rxch.napi); -+ -+ spin_lock_irqsave(&priv->lock, flags); -+ ltq_dma_open(&priv->txch.dma); -+ ltq_dma_open(&priv->rxch.dma); -+ spin_unlock_irqrestore(&priv->lock, flags); - -- if (!IS_TX(i) && (!IS_RX(i))) -- continue; -- ltq_dma_open(&ch->dma); -- napi_enable(&ch->napi); -- } - if (priv->phydev) - phy_start(priv->phydev); -+ - netif_tx_start_all_queues(dev); - return 0; - } -@@ -640,19 +663,19 @@ static int - ltq_etop_stop(struct net_device *dev) - { - struct ltq_etop_priv *priv = netdev_priv(dev); -- int i; -+ unsigned long flags; - - netif_tx_stop_all_queues(dev); - if (priv->phydev) - phy_stop(priv->phydev); -- for (i = 0; i < MAX_DMA_CHAN; i++) { -- struct ltq_etop_chan *ch = &priv->ch[i]; -+ napi_disable(&priv->txch.napi); -+ napi_disable(&priv->rxch.napi); -+ -+ spin_lock_irqsave(&priv->lock, flags); -+ ltq_dma_close(&priv->txch.dma); -+ ltq_dma_close(&priv->rxch.dma); -+ spin_unlock_irqrestore(&priv->lock, flags); - -- if (!IS_RX(i) && !IS_TX(i)) -- continue; -- napi_disable(&ch->napi); -- ltq_dma_close(&ch->dma); -- } - return 0; - } - -@@ -662,16 +685,16 @@ ltq_etop_tx(struct sk_buff *skb, struct - int queue = skb_get_queue_mapping(skb); - struct netdev_queue *txq = netdev_get_tx_queue(dev, queue); - struct ltq_etop_priv *priv = netdev_priv(dev); -- struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; -- struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; -+ struct ltq_dma_desc *desc = -+ &priv->txch.dma.desc_base[priv->txch.dma.desc]; - unsigned long flags; - u32 byte_offset; - int len; - - len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; - -- if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) { -- dev_kfree_skb_any(skb); -+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || -+ priv->txch.skb[priv->txch.dma.desc]) { - netdev_err(dev, "tx ring full\n"); - netif_tx_stop_queue(txq); - return NETDEV_TX_BUSY; -@@ -679,7 +702,7 @@ ltq_etop_tx(struct sk_buff *skb, struct - - /* dma needs to start on a 16 byte aligned address */ - byte_offset = CPHYSADDR(skb->data) % 16; -- ch->skb[ch->dma.desc] = skb; -+ priv->txch.skb[priv->txch.dma.desc] = skb; - - dev->trans_start = jiffies; - -@@ -689,11 +712,11 @@ ltq_etop_tx(struct sk_buff *skb, struct - wmb(); - desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP | - LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK); -- ch->dma.desc++; -- ch->dma.desc %= LTQ_DESC_NUM; -+ priv->txch.dma.desc++; -+ priv->txch.dma.desc %= LTQ_DESC_NUM; - spin_unlock_irqrestore(&priv->lock, flags); - -- if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN) -+ if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN) - netif_tx_stop_queue(txq); - - return NETDEV_TX_OK; -@@ -778,6 +801,10 @@ ltq_etop_init(struct net_device *dev) - err = ltq_etop_hw_init(dev); - if (err) - goto err_hw; -+ err = ltq_etop_dma_init(dev); -+ if (err) -+ goto err_hw; -+ - ltq_etop_change_mtu(dev, 1500); - - memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr)); -@@ -813,6 +840,9 @@ ltq_etop_tx_timeout(struct net_device *d - err = ltq_etop_hw_init(dev); - if (err) - goto err_hw; -+ err = ltq_etop_dma_init(dev); -+ if (err) -+ goto err_hw; - dev->trans_start = jiffies; - netif_wake_queue(dev); - return; -@@ -836,14 +866,13 @@ static const struct net_device_ops ltq_e - .ndo_tx_timeout = ltq_etop_tx_timeout, - }; - --static int __init -+static int __devinit - ltq_etop_probe(struct platform_device *pdev) - { - struct net_device *dev; - struct ltq_etop_priv *priv; - struct resource *res, *gbit_res; - int err; -- int i; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { -@@ -920,15 +949,10 @@ ltq_etop_probe(struct platform_device *p - - spin_lock_init(&priv->lock); - -- for (i = 0; i < MAX_DMA_CHAN; i++) { -- if (IS_TX(i)) -- netif_napi_add(dev, &priv->ch[i].napi, -- ltq_etop_poll_tx, 8); -- else if (IS_RX(i)) -- netif_napi_add(dev, &priv->ch[i].napi, -- ltq_etop_poll_rx, 32); -- priv->ch[i].netdev = dev; -- } -+ netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8); -+ netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32); -+ priv->txch.netdev = dev; -+ priv->rxch.netdev = dev; - - err = register_netdev(dev); - if (err) -@@ -958,6 +982,7 @@ ltq_etop_remove(struct platform_device * - } - - static struct platform_driver ltq_mii_driver = { -+ .probe = ltq_etop_probe, - .remove = __devexit_p(ltq_etop_remove), - .driver = { - .name = "ltq_etop", -@@ -965,24 +990,7 @@ static struct platform_driver ltq_mii_dr - }, - }; - --int __init --init_ltq_etop(void) --{ -- int ret = platform_driver_probe(<q_mii_driver, ltq_etop_probe); -- -- if (ret) -- pr_err("ltq_etop: Error registering platfom driver!"); -- return ret; --} -- --static void __exit --exit_ltq_etop(void) --{ -- platform_driver_unregister(<q_mii_driver); --} -- --module_init(init_ltq_etop); --module_exit(exit_ltq_etop); -+module_platform_driver(ltq_mii_driver); - - MODULE_AUTHOR("John Crispin "); - MODULE_DESCRIPTION("Lantiq SoC ETOP"); diff --git a/target/linux/lantiq/patches-3.3/0041-MTD-MIPS-lantiq-use-module_platform_driver-inside-la.patch b/target/linux/lantiq/patches-3.3/0041-MTD-MIPS-lantiq-use-module_platform_driver-inside-la.patch deleted file mode 100644 index 32d604f805..0000000000 --- a/target/linux/lantiq/patches-3.3/0041-MTD-MIPS-lantiq-use-module_platform_driver-inside-la.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 94ca79b8bd9bf8ec5dcd993e0f004056f12f16f4 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 20 Feb 2012 12:15:25 +0100 -Subject: [PATCH 41/70] MTD: MIPS: lantiq: use module_platform_driver inside - lantiq map driver - -Reduce boilerplate code by converting driver to module_platform_driver. - -Signed-off-by: John Crispin -Cc: linux-mtd@lists.infradead.org ---- - drivers/mtd/maps/lantiq-flash.c | 22 +++------------------- - 1 files changed, 3 insertions(+), 19 deletions(-) - ---- a/drivers/mtd/maps/lantiq-flash.c -+++ b/drivers/mtd/maps/lantiq-flash.c -@@ -108,7 +108,7 @@ ltq_copy_to(struct map_info *map, unsign - spin_unlock_irqrestore(&ebu_lock, flags); - } - --static int __init -+static int __devinit - ltq_mtd_probe(struct platform_device *pdev) - { - struct physmap_flash_data *ltq_mtd_data = dev_get_platdata(&pdev->dev); -@@ -204,6 +204,7 @@ ltq_mtd_remove(struct platform_device *p - } - - static struct platform_driver ltq_mtd_driver = { -+ .probe = ltq_mtd_probe, - .remove = __devexit_p(ltq_mtd_remove), - .driver = { - .name = "ltq_nor", -@@ -211,24 +212,7 @@ static struct platform_driver ltq_mtd_dr - }, - }; - --static int __init --init_ltq_mtd(void) --{ -- int ret = platform_driver_probe(<q_mtd_driver, ltq_mtd_probe); -- -- if (ret) -- pr_err("ltq_nor: error registering platform driver"); -- return ret; --} -- --static void __exit --exit_ltq_mtd(void) --{ -- platform_driver_unregister(<q_mtd_driver); --} -- --module_init(init_ltq_mtd); --module_exit(exit_ltq_mtd); -+module_platform_driver(ltq_mtd_driver); - - MODULE_LICENSE("GPL"); - MODULE_AUTHOR("John Crispin "); diff --git a/target/linux/lantiq/patches-3.3/0042-WDT-MIPS-lantiq-use-module_platform_driver-inside-la.patch b/target/linux/lantiq/patches-3.3/0042-WDT-MIPS-lantiq-use-module_platform_driver-inside-la.patch deleted file mode 100644 index 3d4d61ee40..0000000000 --- a/target/linux/lantiq/patches-3.3/0042-WDT-MIPS-lantiq-use-module_platform_driver-inside-la.patch +++ /dev/null @@ -1,56 +0,0 @@ -From 9004f152deddba21ab7b0fa3ba0b243fb5cbd5a1 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 20 Feb 2012 12:16:31 +0100 -Subject: [PATCH 42/70] WDT: MIPS: lantiq: use module_platform_driver inside - lantiq watchdog driver - -Reduce boilerplate code by converting driver to module_platform_driver. - -Signed-off-by: John Crispin -Cc: linux-watchdog@vger.kernel.org ---- - drivers/watchdog/lantiq_wdt.c | 19 +++---------------- - 1 files changed, 3 insertions(+), 16 deletions(-) - ---- a/drivers/watchdog/lantiq_wdt.c -+++ b/drivers/watchdog/lantiq_wdt.c -@@ -182,7 +182,7 @@ static struct miscdevice ltq_wdt_miscdev - .fops = <q_wdt_fops, - }; - --static int __init -+static int __devinit - ltq_wdt_probe(struct platform_device *pdev) - { - struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -@@ -227,6 +227,7 @@ ltq_wdt_remove(struct platform_device *p - - - static struct platform_driver ltq_wdt_driver = { -+ .probe = ltq_wdt_probe, - .remove = __devexit_p(ltq_wdt_remove), - .driver = { - .name = "ltq_wdt", -@@ -234,21 +235,7 @@ static struct platform_driver ltq_wdt_dr - }, - }; - --static int __init --init_ltq_wdt(void) --{ -- return platform_driver_probe(<q_wdt_driver, ltq_wdt_probe); --} -- --static void __exit --exit_ltq_wdt(void) --{ -- return platform_driver_unregister(<q_wdt_driver); --} -- --module_init(init_ltq_wdt); --module_exit(exit_ltq_wdt); -- -+module_platform_driver(ltq_wdt_driver); - module_param(nowayout, int, 0); - MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"); - diff --git a/target/linux/lantiq/patches-3.3/0043-MIPS-lantiq-adds-GPTU-driver.patch b/target/linux/lantiq/patches-3.3/0043-MIPS-lantiq-adds-GPTU-driver.patch deleted file mode 100644 index 571b86a246..0000000000 --- a/target/linux/lantiq/patches-3.3/0043-MIPS-lantiq-adds-GPTU-driver.patch +++ /dev/null @@ -1,1039 +0,0 @@ -From 468364b5da3a0459a313bb9e477bff031f6a9b09 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 29 Sep 2011 17:16:38 +0200 -Subject: [PATCH 43/70] MIPS: lantiq: adds GPTU driver - ---- - arch/mips/include/asm/mach-lantiq/lantiq_timer.h | 155 ++++ - arch/mips/lantiq/xway/Makefile | 2 +- - arch/mips/lantiq/xway/sysctrl.c | 1 + - arch/mips/lantiq/xway/timer.c | 846 ++++++++++++++++++++++ - 4 files changed, 1003 insertions(+), 1 deletions(-) - create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h - create mode 100644 arch/mips/lantiq/xway/timer.c - ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h -@@ -0,0 +1,155 @@ -+#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ -+#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ -+ -+ -+/****************************************************************************** -+ Copyright (c) 2002, Infineon Technologies. All rights reserved. -+ -+ No Warranty -+ Because the program is licensed free of charge, there is no warranty for -+ the program, to the extent permitted by applicable law. Except when -+ otherwise stated in writing the copyright holders and/or other parties -+ provide the program "as is" without warranty of any kind, either -+ expressed or implied, including, but not limited to, the implied -+ warranties of merchantability and fitness for a particular purpose. The -+ entire risk as to the quality and performance of the program is with -+ you. should the program prove defective, you assume the cost of all -+ necessary servicing, repair or correction. -+ -+ In no event unless required by applicable law or agreed to in writing -+ will any copyright holder, or any other party who may modify and/or -+ redistribute the program as permitted above, be liable to you for -+ damages, including any general, special, incidental or consequential -+ damages arising out of the use or inability to use the program -+ (including but not limited to loss of data or data being rendered -+ inaccurate or losses sustained by you or third parties or a failure of -+ the program to operate with any other programs), even if such holder or -+ other party has been advised of the possibility of such damages. -+******************************************************************************/ -+ -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+/* -+ * Available Timer/Counter Index -+ */ -+#define TIMER(n, X) (n * 2 + (X ? 1 : 0)) -+#define TIMER_ANY 0x00 -+#define TIMER1A TIMER(1, 0) -+#define TIMER1B TIMER(1, 1) -+#define TIMER2A TIMER(2, 0) -+#define TIMER2B TIMER(2, 1) -+#define TIMER3A TIMER(3, 0) -+#define TIMER3B TIMER(3, 1) -+ -+/* -+ * Flag of Timer/Counter -+ * These flags specify the way in which timer is configured. -+ */ -+/* Bit size of timer/counter. */ -+#define TIMER_FLAG_16BIT 0x0000 -+#define TIMER_FLAG_32BIT 0x0001 -+/* Switch between timer and counter. */ -+#define TIMER_FLAG_TIMER 0x0000 -+#define TIMER_FLAG_COUNTER 0x0002 -+/* Stop or continue when overflowing/underflowing. */ -+#define TIMER_FLAG_ONCE 0x0000 -+#define TIMER_FLAG_CYCLIC 0x0004 -+/* Count up or counter down. */ -+#define TIMER_FLAG_UP 0x0000 -+#define TIMER_FLAG_DOWN 0x0008 -+/* Count on specific level or edge. */ -+#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000 -+#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040 -+#define TIMER_FLAG_RISE_EDGE 0x0010 -+#define TIMER_FLAG_FALL_EDGE 0x0020 -+#define TIMER_FLAG_ANY_EDGE 0x0030 -+/* Signal is syncronous to module clock or not. */ -+#define TIMER_FLAG_UNSYNC 0x0000 -+#define TIMER_FLAG_SYNC 0x0080 -+/* Different interrupt handle type. */ -+#define TIMER_FLAG_NO_HANDLE 0x0000 -+#if defined(__KERNEL__) -+ #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100 -+#endif // defined(__KERNEL__) -+#define TIMER_FLAG_SIGNAL 0x0300 -+/* Internal clock source or external clock source */ -+#define TIMER_FLAG_INT_SRC 0x0000 -+#define TIMER_FLAG_EXT_SRC 0x1000 -+ -+ -+/* -+ * ioctl Command -+ */ -+#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */ -+#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */ -+#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */ -+#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */ -+#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */ -+#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/ -+#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */ -+#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */ -+ -+/* -+ * Data Type Used to Call ioctl -+ */ -+struct gptu_ioctl_param { -+ unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * -+ * GPTU_SET_COUNTER, this field is ID of expected * -+ * timer/counter. If it's zero, a timer/counter would * -+ * be dynamically allocated and ID would be stored in * -+ * this field. * -+ * In command GPTU_GET_COUNT_VALUE, this field is * -+ * ignored. * -+ * In other command, this field is ID of timer/counter * -+ * allocated. */ -+ unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * -+ * GPTU_SET_COUNTER, this field contains flags to * -+ * specify how to configure timer/counter. * -+ * In command GPTU_START_TIMER, zero indicate start * -+ * and non-zero indicate resume timer/counter. * -+ * In other command, this field is ignored. */ -+ unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains * -+ * init/reload value. * -+ * In command GPTU_SET_TIMER, this field contains * -+ * frequency (0.001Hz) of timer. * -+ * In command GPTU_GET_COUNT_VALUE, current count * -+ * value would be stored in this field. * -+ * In command GPTU_CALCULATE_DIVIDER, this field * -+ * contains frequency wanted, and after calculation, * -+ * divider would be stored in this field to overwrite * -+ * the frequency. * -+ * In other command, this field is ignored. */ -+ int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * -+ * if signal is required, this field contains process * -+ * ID to which signal would be sent. * -+ * In other command, this field is ignored. */ -+ int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * -+ * if signal is required, this field contains signal * -+ * number which would be sent. * -+ * In other command, this field is ignored. */ -+}; -+ -+/* -+ * #################################### -+ * Data Type -+ * #################################### -+ */ -+typedef void (*timer_callback)(unsigned long arg); -+ -+extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long); -+extern int lq_free_timer(unsigned int); -+extern int lq_start_timer(unsigned int, int); -+extern int lq_stop_timer(unsigned int); -+extern int lq_reset_counter_flags(u32 timer, u32 flags); -+extern int lq_get_count_value(unsigned int, unsigned long *); -+extern u32 lq_cal_divider(unsigned long); -+extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long); -+extern int lq_set_counter(unsigned int timer, unsigned int flag, -+ u32 reload, unsigned long arg1, unsigned long arg2); -+ -+#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */ ---- a/arch/mips/lantiq/xway/Makefile -+++ b/arch/mips/lantiq/xway/Makefile -@@ -1,4 +1,4 @@ --obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o -+obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o timer.o - - obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o - obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o ---- a/arch/mips/lantiq/xway/sysctrl.c -+++ b/arch/mips/lantiq/xway/sysctrl.c -@@ -147,6 +147,7 @@ void __init ltq_soc_init(void) - clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA); - clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP); - clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI); -+ clkdev_add_pmu("ltq_gptu", NULL, 0, PMU_GPT); - if (!ltq_is_vr9()) - clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE); - if (ltq_is_ase()) { ---- /dev/null -+++ b/arch/mips/lantiq/xway/timer.c -@@ -0,0 +1,846 @@ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include "../clk.h" -+ -+#include -+#include -+#include -+ -+#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6 -+ -+#ifdef TIMER1A -+#define FIRST_TIMER TIMER1A -+#else -+#define FIRST_TIMER 2 -+#endif -+ -+/* -+ * GPTC divider is set or not. -+ */ -+#define GPTU_CLC_RMC_IS_SET 0 -+ -+/* -+ * Timer Interrupt (IRQ) -+ */ -+/* Must be adjusted when ICU driver is available */ -+#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) -+ -+/* -+ * Bits Operation -+ */ -+#define GET_BITS(x, msb, lsb) \ -+ (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) -+#define SET_BITS(x, msb, lsb, value) \ -+ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \ -+ (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) -+ -+/* -+ * GPTU Register Mapping -+ */ -+#define LQ_GPTU (KSEG1 + 0x1E100A00) -+#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000)) -+#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008)) -+#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -+#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -+#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -+#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ -+#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4)) -+#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8)) -+#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC)) -+ -+/* -+ * Clock Control Register -+ */ -+#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16) -+#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8) -+#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5)) -+#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3)) -+#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2)) -+#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1)) -+#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0)) -+ -+#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value)) -+#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value)) -+#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0) -+#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0) -+#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0) -+#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0) -+#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0) -+ -+/* -+ * ID Register -+ */ -+#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8) -+#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5) -+#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0) -+ -+/* -+ * Control Register of Timer/Counter nX -+ * n is the index of block (1 based index) -+ * X is either A or B -+ */ -+#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10)) -+#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9)) -+#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8)) -+#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6) -+#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5)) -+#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */ -+#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3)) -+#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2)) -+#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1)) -+#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0)) -+ -+#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10)) -+#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0) -+#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0) -+#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value)) -+#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0) -+#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0) -+#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0) -+#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0) -+#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0) -+ -+#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0) -+#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0) -+#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0) -+ -+#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) -+#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) -+ -+#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001) -+#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002) -+#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004) -+#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008) -+#define TIMER_FLAG_NONE_EDGE 0x0000 -+#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030) -+#define TIMER_FLAG_REAL 0x0000 -+#define TIMER_FLAG_INVERT 0x0040 -+#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040) -+#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070) -+#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080) -+#define TIMER_FLAG_CALLBACK_IN_HB 0x0200 -+#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300) -+#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000) -+ -+struct timer_dev_timer { -+ unsigned int f_irq_on; -+ unsigned int irq; -+ unsigned int flag; -+ unsigned long arg1; -+ unsigned long arg2; -+}; -+ -+struct timer_dev { -+ struct mutex gptu_mutex; -+ unsigned int number_of_timers; -+ unsigned int occupation; -+ unsigned int f_gptu_on; -+ struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2]; -+}; -+ -+unsigned long ltq_danube_fpi_bus_clock(int fpi); -+unsigned long ltq_vr9_fpi_bus_clock(int fpi); -+ -+unsigned int ltq_get_fpi_bus_clock(int fpi) { -+ if (ltq_is_ase()) -+ return CLOCK_133M; -+ else if (ltq_is_vr9()) -+ return ltq_vr9_fpi_bus_clock(fpi); -+ -+ return ltq_danube_fpi_bus_clock(fpi); -+} -+ -+ -+static long gptu_ioctl(struct file *, unsigned int, unsigned long); -+static int gptu_open(struct inode *, struct file *); -+static int gptu_release(struct inode *, struct file *); -+ -+static struct file_operations gptu_fops = { -+ .owner = THIS_MODULE, -+ .unlocked_ioctl = gptu_ioctl, -+ .open = gptu_open, -+ .release = gptu_release -+}; -+ -+static struct miscdevice gptu_miscdev = { -+ .minor = MISC_DYNAMIC_MINOR, -+ .name = "gptu", -+ .fops = &gptu_fops, -+}; -+ -+static struct timer_dev timer_dev; -+ -+static irqreturn_t timer_irq_handler(int irq, void *p) -+{ -+ unsigned int timer; -+ unsigned int flag; -+ struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p; -+ -+ timer = irq - TIMER_INTERRUPT; -+ if (timer < timer_dev.number_of_timers -+ && dev_timer == &timer_dev.timer[timer]) { -+ /* Clear interrupt. */ -+ ltq_w32(1 << timer, LQ_GPTU_IRNCR); -+ -+ /* Call user hanler or signal. */ -+ flag = dev_timer->flag; -+ if (!(timer & 0x01) -+ || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { -+ /* 16-bit timer or timer A of 32-bit timer */ -+ switch (TIMER_FLAG_MASK_HANDLE(flag)) { -+ case TIMER_FLAG_CALLBACK_IN_IRQ: -+ case TIMER_FLAG_CALLBACK_IN_HB: -+ if (dev_timer->arg1) -+ (*(timer_callback)dev_timer->arg1)(dev_timer->arg2); -+ break; -+ case TIMER_FLAG_SIGNAL: -+ send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0); -+ break; -+ } -+ } -+ } -+ return IRQ_HANDLED; -+} -+ -+static inline void lq_enable_gptu(void) -+{ -+ struct clk *clk = clk_get_sys("ltq_gptu", NULL); -+ clk_enable(clk); -+ -+ //ltq_pmu_enable(PMU_GPT); -+ -+ /* Set divider as 1, disable write protection for SPEN, enable module. */ -+ *LQ_GPTU_CLC = -+ GPTU_CLC_SMC_SET(0x00) | -+ GPTU_CLC_RMC_SET(0x01) | -+ GPTU_CLC_FSOE_SET(0) | -+ GPTU_CLC_SBWE_SET(1) | -+ GPTU_CLC_EDIS_SET(0) | -+ GPTU_CLC_SPEN_SET(0) | -+ GPTU_CLC_DISR_SET(0); -+} -+ -+static inline void lq_disable_gptu(void) -+{ -+ struct clk *clk = clk_get_sys("ltq_gptu", NULL); -+ ltq_w32(0x00, LQ_GPTU_IRNEN); -+ ltq_w32(0xfff, LQ_GPTU_IRNCR); -+ -+ /* Set divider as 0, enable write protection for SPEN, disable module. */ -+ *LQ_GPTU_CLC = -+ GPTU_CLC_SMC_SET(0x00) | -+ GPTU_CLC_RMC_SET(0x00) | -+ GPTU_CLC_FSOE_SET(0) | -+ GPTU_CLC_SBWE_SET(0) | -+ GPTU_CLC_EDIS_SET(0) | -+ GPTU_CLC_SPEN_SET(0) | -+ GPTU_CLC_DISR_SET(1); -+ -+ clk_enable(clk); -+} -+ -+int lq_request_timer(unsigned int timer, unsigned int flag, -+ unsigned long value, unsigned long arg1, unsigned long arg2) -+{ -+ int ret = 0; -+ unsigned int con_reg, irnen_reg; -+ int n, X; -+ -+ if (timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...", -+ timer, flag, value); -+ -+ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) -+ value &= 0xFFFF; -+ else -+ timer &= ~0x01; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ /* -+ * Allocate timer. -+ */ -+ if (timer < FIRST_TIMER) { -+ unsigned int mask; -+ unsigned int shift; -+ /* This takes care of TIMER1B which is the only choice for Voice TAPI system */ -+ unsigned int offset = TIMER2A; -+ -+ /* -+ * Pick up a free timer. -+ */ -+ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { -+ mask = 1 << offset; -+ shift = 1; -+ } else { -+ mask = 3 << offset; -+ shift = 2; -+ } -+ for (timer = offset; -+ timer < offset + timer_dev.number_of_timers; -+ timer += shift, mask <<= shift) -+ if (!(timer_dev.occupation & mask)) { -+ timer_dev.occupation |= mask; -+ break; -+ } -+ if (timer >= offset + timer_dev.number_of_timers) { -+ printk("failed![%d]\n", __LINE__); -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } else -+ ret = timer; -+ } else { -+ register unsigned int mask; -+ -+ /* -+ * Check if the requested timer is free. -+ */ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if ((timer_dev.occupation & mask)) { -+ printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", -+ __LINE__, mask, timer_dev.occupation); -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EBUSY; -+ } else { -+ timer_dev.occupation |= mask; -+ ret = 0; -+ } -+ } -+ -+ /* -+ * Prepare control register value. -+ */ -+ switch (TIMER_FLAG_MASK_EDGE(flag)) { -+ default: -+ case TIMER_FLAG_NONE_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x00); -+ break; -+ case TIMER_FLAG_RISE_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x01); -+ break; -+ case TIMER_FLAG_FALL_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x02); -+ break; -+ case TIMER_FLAG_ANY_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x03); -+ break; -+ } -+ if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER) -+ con_reg |= -+ TIMER_FLAG_MASK_SRC(flag) == -+ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : -+ GPTU_CON_SRC_EXT_SET(0); -+ else -+ con_reg |= -+ TIMER_FLAG_MASK_SRC(flag) == -+ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : -+ GPTU_CON_SRC_EG_SET(0); -+ con_reg |= -+ TIMER_FLAG_MASK_SYNC(flag) == -+ TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : -+ GPTU_CON_SYNC_SET(1); -+ con_reg |= -+ TIMER_FLAG_MASK_INVERT(flag) == -+ TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); -+ con_reg |= -+ TIMER_FLAG_MASK_SIZE(flag) == -+ TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : -+ GPTU_CON_EXT_SET(1); -+ con_reg |= -+ TIMER_FLAG_MASK_STOP(flag) == -+ TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); -+ con_reg |= -+ TIMER_FLAG_MASK_TYPE(flag) == -+ TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : -+ GPTU_CON_CNT_SET(1); -+ con_reg |= -+ TIMER_FLAG_MASK_DIR(flag) == -+ TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); -+ -+ /* -+ * Fill up running data. -+ */ -+ timer_dev.timer[timer - FIRST_TIMER].flag = flag; -+ timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1; -+ timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag; -+ -+ /* -+ * Enable GPTU module. -+ */ -+ if (!timer_dev.f_gptu_on) { -+ lq_enable_gptu(); -+ timer_dev.f_gptu_on = 1; -+ } -+ -+ /* -+ * Enable IRQ. -+ */ -+ if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) { -+ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL) -+ timer_dev.timer[timer - FIRST_TIMER].arg1 = -+ (unsigned long) find_task_by_vpid((int) arg1); -+ -+ irnen_reg = 1 << (timer - FIRST_TIMER); -+ -+ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL -+ || (TIMER_FLAG_MASK_HANDLE(flag) == -+ TIMER_FLAG_CALLBACK_IN_IRQ -+ && timer_dev.timer[timer - FIRST_TIMER].arg1)) { -+ enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); -+ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1; -+ } -+ } else -+ irnen_reg = 0; -+ -+ /* -+ * Write config register, reload value and enable interrupt. -+ */ -+ n = timer >> 1; -+ X = timer & 0x01; -+ *LQ_GPTU_CON(n, X) = con_reg; -+ *LQ_GPTU_RELOAD(n, X) = value; -+ /* printk("reload value = %d\n", (u32)value); */ -+ *LQ_GPTU_IRNEN |= irnen_reg; -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ printk("successful!\n"); -+ return ret; -+} -+EXPORT_SYMBOL(lq_request_timer); -+ -+int lq_free_timer(unsigned int timer) -+{ -+ unsigned int flag; -+ unsigned int mask; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ flag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ if (GPTU_CON_EN(n, X)) -+ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); -+ -+ *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1); -+ *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1); -+ -+ if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) { -+ disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); -+ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0; -+ } -+ -+ timer_dev.occupation &= ~mask; -+ if (!timer_dev.occupation && timer_dev.f_gptu_on) { -+ lq_disable_gptu(); -+ timer_dev.f_gptu_on = 0; -+ } -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(lq_free_timer); -+ -+int lq_start_timer(unsigned int timer, int is_resume) -+{ -+ unsigned int flag; -+ unsigned int mask; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ flag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == -+ TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1); -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(lq_start_timer); -+ -+int lq_stop_timer(unsigned int timer) -+{ -+ unsigned int flag; -+ unsigned int mask; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER -+ || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ flag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(lq_stop_timer); -+ -+int lq_reset_counter_flags(u32 timer, u32 flags) -+{ -+ unsigned int oflag; -+ unsigned int mask, con_reg; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ oflag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ switch (TIMER_FLAG_MASK_EDGE(flags)) { -+ default: -+ case TIMER_FLAG_NONE_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x00); -+ break; -+ case TIMER_FLAG_RISE_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x01); -+ break; -+ case TIMER_FLAG_FALL_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x02); -+ break; -+ case TIMER_FLAG_ANY_EDGE: -+ con_reg = GPTU_CON_EDGE_SET(0x03); -+ break; -+ } -+ if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER) -+ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0); -+ else -+ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0); -+ con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1); -+ con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); -+ con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1); -+ con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); -+ con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1); -+ con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); -+ -+ timer_dev.timer[timer - FIRST_TIMER].flag = flags; -+ if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT) -+ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags; -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ *LQ_GPTU_CON(n, X) = con_reg; -+ smp_wmb(); -+ printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *LQ_GPTU_CON(n, X)); -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return 0; -+} -+EXPORT_SYMBOL(lq_reset_counter_flags); -+ -+int lq_get_count_value(unsigned int timer, unsigned long *value) -+{ -+ unsigned int flag; -+ unsigned int mask; -+ int n, X; -+ -+ if (!timer_dev.f_gptu_on) -+ return -EINVAL; -+ -+ if (timer < FIRST_TIMER -+ || timer >= FIRST_TIMER + timer_dev.number_of_timers) -+ return -EINVAL; -+ -+ mutex_lock(&timer_dev.gptu_mutex); -+ -+ flag = timer_dev.timer[timer - FIRST_TIMER].flag; -+ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) -+ timer &= ~0x01; -+ -+ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; -+ if (((timer_dev.occupation & mask) ^ mask)) { -+ mutex_unlock(&timer_dev.gptu_mutex); -+ return -EINVAL; -+ } -+ -+ n = timer >> 1; -+ X = timer & 0x01; -+ -+ *value = *LQ_GPTU_COUNT(n, X); -+ -+ mutex_unlock(&timer_dev.gptu_mutex); -+ -+ return 0; -+} -+EXPORT_SYMBOL(lq_get_count_value); -+ -+u32 lq_cal_divider(unsigned long freq) -+{ -+ u64 module_freq, fpi = ltq_get_fpi_bus_clock(2); -+ u32 clock_divider = 1; -+ module_freq = fpi * 1000; -+ do_div(module_freq, clock_divider * freq); -+ return module_freq; -+} -+EXPORT_SYMBOL(lq_cal_divider); -+ -+int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic, -+ int is_ext_src, unsigned int handle_flag, unsigned long arg1, -+ unsigned long arg2) -+{ -+ unsigned long divider; -+ unsigned int flag; -+ -+ divider = lq_cal_divider(freq); -+ if (divider == 0) -+ return -EINVAL; -+ flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT) -+ | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE) -+ | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC) -+ | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN -+ | TIMER_FLAG_MASK_HANDLE(handle_flag); -+ -+ printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n", -+ timer, freq, divider); -+ return lq_request_timer(timer, flag, divider, arg1, arg2); -+} -+EXPORT_SYMBOL(lq_set_timer); -+ -+int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload, -+ unsigned long arg1, unsigned long arg2) -+{ -+ printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload); -+ return lq_request_timer(timer, flag, reload, arg1, arg2); -+} -+EXPORT_SYMBOL(lq_set_counter); -+ -+static long gptu_ioctl(struct file *file, unsigned int cmd, -+ unsigned long arg) -+{ -+ int ret; -+ struct gptu_ioctl_param param; -+ -+ if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param))) -+ return -EFAULT; -+ copy_from_user(¶m, (void *) arg, sizeof(param)); -+ -+ if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER -+ || GPTU_SET_COUNTER) && param.timer < 2) -+ || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER) -+ && !access_ok(VERIFY_WRITE, arg, -+ sizeof(struct gptu_ioctl_param))) -+ return -EFAULT; -+ -+ switch (cmd) { -+ case GPTU_REQUEST_TIMER: -+ ret = lq_request_timer(param.timer, param.flag, param.value, -+ (unsigned long) param.pid, -+ (unsigned long) param.sig); -+ if (ret > 0) { -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ timer, &ret, sizeof(&ret)); -+ ret = 0; -+ } -+ break; -+ case GPTU_FREE_TIMER: -+ ret = lq_free_timer(param.timer); -+ break; -+ case GPTU_START_TIMER: -+ ret = lq_start_timer(param.timer, param.flag); -+ break; -+ case GPTU_STOP_TIMER: -+ ret = lq_stop_timer(param.timer); -+ break; -+ case GPTU_GET_COUNT_VALUE: -+ ret = lq_get_count_value(param.timer, ¶m.value); -+ if (!ret) -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ value, ¶m.value, -+ sizeof(param.value)); -+ break; -+ case GPTU_CALCULATE_DIVIDER: -+ param.value = lq_cal_divider(param.value); -+ if (param.value == 0) -+ ret = -EINVAL; -+ else { -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ value, ¶m.value, -+ sizeof(param.value)); -+ ret = 0; -+ } -+ break; -+ case GPTU_SET_TIMER: -+ ret = lq_set_timer(param.timer, param.value, -+ TIMER_FLAG_MASK_STOP(param.flag) != -+ TIMER_FLAG_ONCE ? 1 : 0, -+ TIMER_FLAG_MASK_SRC(param.flag) == -+ TIMER_FLAG_EXT_SRC ? 1 : 0, -+ TIMER_FLAG_MASK_HANDLE(param.flag) == -+ TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL : -+ TIMER_FLAG_NO_HANDLE, -+ (unsigned long) param.pid, -+ (unsigned long) param.sig); -+ if (ret > 0) { -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ timer, &ret, sizeof(&ret)); -+ ret = 0; -+ } -+ break; -+ case GPTU_SET_COUNTER: -+ lq_set_counter(param.timer, param.flag, param.value, 0, 0); -+ if (ret > 0) { -+ copy_to_user(&((struct gptu_ioctl_param *) arg)-> -+ timer, &ret, sizeof(&ret)); -+ ret = 0; -+ } -+ break; -+ default: -+ ret = -ENOTTY; -+ } -+ -+ return ret; -+} -+ -+static int gptu_open(struct inode *inode, struct file *file) -+{ -+ return 0; -+} -+ -+static int gptu_release(struct inode *inode, struct file *file) -+{ -+ return 0; -+} -+ -+int __init lq_gptu_init(void) -+{ -+ int ret; -+ unsigned int i; -+ -+ ltq_w32(0, LQ_GPTU_IRNEN); -+ ltq_w32(0xfff, LQ_GPTU_IRNCR); -+ -+ memset(&timer_dev, 0, sizeof(timer_dev)); -+ mutex_init(&timer_dev.gptu_mutex); -+ -+ lq_enable_gptu(); -+ timer_dev.number_of_timers = GPTU_ID_CFG * 2; -+ lq_disable_gptu(); -+ if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2) -+ timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2; -+ printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers); -+ -+ ret = misc_register(&gptu_miscdev); -+ if (ret) { -+ printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret); -+ return ret; -+ } else { -+ printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor); -+ } -+ -+ for (i = 0; i < timer_dev.number_of_timers; i++) { -+ ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]); -+ if (ret) { -+ for (; i >= 0; i--) -+ free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]); -+ misc_deregister(&gptu_miscdev); -+ printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret); -+ return ret; -+ } else { -+ timer_dev.timer[i].irq = TIMER_INTERRUPT + i; -+ disable_irq(timer_dev.timer[i].irq); -+ printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq); -+ } -+ } -+ -+ return 0; -+} -+ -+void __exit lq_gptu_exit(void) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < timer_dev.number_of_timers; i++) { -+ if (timer_dev.timer[i].f_irq_on) -+ disable_irq(timer_dev.timer[i].irq); -+ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); -+ } -+ lq_disable_gptu(); -+ misc_deregister(&gptu_miscdev); -+} -+ -+module_init(lq_gptu_init); -+module_exit(lq_gptu_exit); diff --git a/target/linux/lantiq/patches-3.3/0044-MIPS-lantiq-adds-dwc_otg.patch b/target/linux/lantiq/patches-3.3/0044-MIPS-lantiq-adds-dwc_otg.patch deleted file mode 100644 index bece3c1f70..0000000000 --- a/target/linux/lantiq/patches-3.3/0044-MIPS-lantiq-adds-dwc_otg.patch +++ /dev/null @@ -1,15576 +0,0 @@ -From 5bd209cb056fcf421710a1cd1521596a242bc569 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 30 Sep 2011 14:37:36 +0200 -Subject: [PATCH 44/70] MIPS: lantiq: adds dwc_otg - ---- - drivers/usb/Kconfig | 2 + - drivers/usb/Makefile | 2 + - drivers/usb/core/hub.c | 4 +- - drivers/usb/dwc_otg/Kconfig | 37 + - drivers/usb/dwc_otg/Makefile | 39 + - drivers/usb/dwc_otg/dwc_otg_attr.c | 802 ++++++++ - drivers/usb/dwc_otg/dwc_otg_attr.h | 67 + - drivers/usb/dwc_otg/dwc_otg_cil.c | 3025 +++++++++++++++++++++++++++++++ - drivers/usb/dwc_otg/dwc_otg_cil.h | 911 ++++++++++ - drivers/usb/dwc_otg/dwc_otg_cil_ifx.h | 58 + - drivers/usb/dwc_otg/dwc_otg_cil_intr.c | 708 ++++++++ - drivers/usb/dwc_otg/dwc_otg_driver.c | 1274 +++++++++++++ - drivers/usb/dwc_otg/dwc_otg_driver.h | 84 + - drivers/usb/dwc_otg/dwc_otg_hcd.c | 2870 +++++++++++++++++++++++++++++ - drivers/usb/dwc_otg/dwc_otg_hcd.h | 676 +++++++ - drivers/usb/dwc_otg/dwc_otg_hcd_intr.c | 1841 +++++++++++++++++++ - drivers/usb/dwc_otg/dwc_otg_hcd_queue.c | 794 ++++++++ - drivers/usb/dwc_otg/dwc_otg_ifx.c | 100 + - drivers/usb/dwc_otg/dwc_otg_ifx.h | 85 + - drivers/usb/dwc_otg/dwc_otg_plat.h | 269 +++ - drivers/usb/dwc_otg/dwc_otg_regs.h | 1797 ++++++++++++++++++ - 21 files changed, 15443 insertions(+), 2 deletions(-) - create mode 100644 drivers/usb/dwc_otg/Kconfig - create mode 100644 drivers/usb/dwc_otg/Makefile - create mode 100644 drivers/usb/dwc_otg/dwc_otg_attr.c - create mode 100644 drivers/usb/dwc_otg/dwc_otg_attr.h - create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.c - create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.h - create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil_ifx.h - create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil_intr.c - create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.c - create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.h - create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.c - create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.h - create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_intr.c - create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_queue.c - create mode 100644 drivers/usb/dwc_otg/dwc_otg_ifx.c - create mode 100644 drivers/usb/dwc_otg/dwc_otg_ifx.h - create mode 100644 drivers/usb/dwc_otg/dwc_otg_plat.h - create mode 100644 drivers/usb/dwc_otg/dwc_otg_regs.h - ---- a/drivers/usb/Kconfig -+++ b/drivers/usb/Kconfig -@@ -130,6 +130,8 @@ source "drivers/usb/wusbcore/Kconfig" - - source "drivers/usb/host/Kconfig" - -+source "drivers/usb/dwc_otg/Kconfig" -+ - source "drivers/usb/musb/Kconfig" - - source "drivers/usb/renesas_usbhs/Kconfig" ---- a/drivers/usb/Makefile -+++ b/drivers/usb/Makefile -@@ -32,6 +32,8 @@ obj-$(CONFIG_USB_C67X00_HCD) += c67x00/ - - obj-$(CONFIG_USB_WUSB) += wusbcore/ - -+obj-$(CONFIG_DWC_OTG) += dwc_otg/ -+ - obj-$(CONFIG_USB_ACM) += class/ - obj-$(CONFIG_USB_PRINTER) += class/ - obj-$(CONFIG_USB_WDM) += class/ ---- a/drivers/usb/core/hub.c -+++ b/drivers/usb/core/hub.c -@@ -2935,11 +2935,11 @@ hub_port_init (struct usb_hub *hub, stru - udev->ttport = hdev->ttport; - } else if (udev->speed != USB_SPEED_HIGH - && hdev->speed == USB_SPEED_HIGH) { -- if (!hub->tt.hub) { -+/* if (!hub->tt.hub) { - dev_err(&udev->dev, "parent hub has no TT\n"); - retval = -EINVAL; - goto fail; -- } -+ }*/ - udev->tt = &hub->tt; - udev->ttport = port1; - } ---- /dev/null -+++ b/drivers/usb/dwc_otg/Kconfig -@@ -0,0 +1,37 @@ -+config DWC_OTG -+ tristate "Synopsis DWC_OTG support" -+ depends on USB -+ help -+ This driver supports Synopsis DWC_OTG IP core -+ embebbed on many SOCs (ralink, infineon, etc) -+ -+choice -+ prompt "USB Operation Mode" -+ depends on DWC_OTG -+ default DWC_OTG_HOST_ONLY -+ -+config DWC_OTG_HOST_ONLY -+ bool "HOST ONLY MODE" -+ depends on DWC_OTG -+ -+#config DWC_OTG_DEVICE_ONLY -+# bool "DEVICE ONLY MODE" -+# depends on DWC_OTG -+endchoice -+ -+choice -+ prompt "Platform" -+ depends on DWC_OTG -+ default DWC_OTG_LANTIQ -+ -+config DWC_OTG_LANTIQ -+ bool "Lantiq" -+ depends on LANTIQ -+ help -+ Danube USB Host Controller -+ platform support -+endchoice -+ -+config DWC_OTG_DEBUG -+ bool "Enable debug mode" -+ depends on DWC_OTG ---- /dev/null -+++ b/drivers/usb/dwc_otg/Makefile -@@ -0,0 +1,39 @@ -+# -+# Makefile for DWC_otg Highspeed USB controller driver -+# -+ -+ifeq ($(CONFIG_DWC_OTG_DEBUG),y) -+EXTRA_CFLAGS += -DDEBUG -+endif -+ -+# Use one of the following flags to compile the software in host-only or -+# device-only mode based on the configuration selected by the user -+ifeq ($(CONFIG_DWC_OTG_HOST_ONLY),y) -+ EXTRA_CFLAGS += -DDWC_OTG_HOST_ONLY -DDWC_HOST_ONLY -+ EXTRA_CFLAGS += -DDWC_OTG_EN_ISOC -DDWC_EN_ISOC -+else ifeq ($(CONFIG_DWC_OTG_DEVICE_ONLY),y) -+ EXTRA_CFLAGS += -DDWC_OTG_DEVICE_ONLY -+else -+ EXTRA_CFLAGS += -DDWC_OTG_MODE -+endif -+ -+# EXTRA_CFLAGS += -DDWC_HS_ELECT_TST -+# EXTRA_CFLAGS += -DDWC_OTG_EXT_CHG_PUMP -+ -+ifeq ($(CONFIG_DWC_OTG_LANTIQ),y) -+ EXTRA_CFLAGS += -Dlinux -D__LINUX__ -DDWC_OTG_IFX -DDWC_OTG_HOST_ONLY -DDWC_HOST_ONLY -D__KERNEL__ -+endif -+ifeq ($(CONFIG_DWC_OTG_LANTIQ),m) -+ EXTRA_CFLAGS += -Dlinux -D__LINUX__ -DDWC_OTG_IFX -DDWC_HOST_ONLY -DMODULE -D__KERNEL__ -DDEBUG -+endif -+ -+obj-$(CONFIG_DWC_OTG) := dwc_otg.o -+dwc_otg-objs := dwc_otg_hcd.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o -+#dwc_otg-objs += dwc_otg_pcd.o dwc_otg_pcd_intr.o -+dwc_otg-objs += dwc_otg_attr.o -+dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o -+dwc_otg-objs += dwc_otg_ifx.o -+dwc_otg-objs += dwc_otg_driver.o -+ -+#obj-$(CONFIG_DWC_OTG_IFX) := dwc_otg_ifx.o -+#dwc_otg_ifx-objs := dwc_otg_ifx.o ---- /dev/null -+++ b/drivers/usb/dwc_otg/dwc_otg_attr.c -@@ -0,0 +1,802 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_attr.c $ -+ * $Revision: 1.1.1.1 $ -+ * $Date: 2009-04-17 06:15:34 $ -+ * $Change: 537387 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+/** @file -+ * -+ * The diagnostic interface will provide access to the controller for -+ * bringing up the hardware and testing. The Linux driver attributes -+ * feature will be used to provide the Linux Diagnostic -+ * Interface. These attributes are accessed through sysfs. -+ */ -+ -+/** @page "Linux Module Attributes" -+ * -+ * The Linux module attributes feature is used to provide the Linux -+ * Diagnostic Interface. These attributes are accessed through sysfs. -+ * The diagnostic interface will provide access to the controller for -+ * bringing up the hardware and testing. -+ -+ -+ The following table shows the attributes. -+

Parameter NameMeaning
otg_capSpecifies the OTG capabilities. The driver will automatically detect the + value for this parameter if none is specified. + - 0: HNP and SRP capable (default, if available) + - 1: SRP Only capable + - 2: No HNP/SRP capable +
dma_enableSpecifies whether to use slave or DMA mode for accessing the data FIFOs. + The driver will automatically detect the value for this parameter if none is + specified. + - 0: Slave + - 1: DMA (default, if available) +
dma_burst_sizeThe DMA Burst size (applicable only for External DMA Mode). + - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32) +
speedSpecifies the maximum speed of operation in host and device mode. The + actual speed depends on the speed of the attached device and the value of + phy_type. + - 0: High Speed (default) + - 1: Full Speed +
host_support_fs_ls_low_powerSpecifies whether low power mode is supported when attached to a Full + Speed or Low Speed device in host mode. + - 0: Don't support low power mode (default) + - 1: Support low power mode +
host_ls_low_power_phy_clkSpecifies the PHY clock rate in low power mode when connected to a Low + Speed device in host mode. This parameter is applicable only if + HOST_SUPPORT_FS_LS_LOW_POWER is enabled. + - 0: 48 MHz (default) + - 1: 6 MHz +
enable_dynamic_fifo Specifies whether FIFOs may be resized by the driver software. + - 0: Use cC FIFO size parameters + - 1: Allow dynamic FIFO sizing (default) +
data_fifo_sizeTotal number of 4-byte words in the data FIFO memory. This memory + includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. + - Values: 32 to 32768 (default 8192) + + Note: The total FIFO memory depth in the FPGA configuration is 8192. +
dev_rx_fifo_sizeNumber of 4-byte words in the Rx FIFO in device mode when dynamic + FIFO sizing is enabled. + - Values: 16 to 32768 (default 1064) +
dev_nperio_tx_fifo_sizeNumber of 4-byte words in the non-periodic Tx FIFO in device mode when + dynamic FIFO sizing is enabled. + - Values: 16 to 32768 (default 1024) +
dev_perio_tx_fifo_size_n (n = 1 to 15)Number of 4-byte words in each of the periodic Tx FIFOs in device mode + when dynamic FIFO sizing is enabled. + - Values: 4 to 768 (default 256) +
host_rx_fifo_sizeNumber of 4-byte words in the Rx FIFO in host mode when dynamic FIFO + sizing is enabled. + - Values: 16 to 32768 (default 1024) +
host_nperio_tx_fifo_sizeNumber of 4-byte words in the non-periodic Tx FIFO in host mode when + dynamic FIFO sizing is enabled in the core. + - Values: 16 to 32768 (default 1024) +
host_perio_tx_fifo_sizeNumber of 4-byte words in the host periodic Tx FIFO when dynamic FIFO + sizing is enabled. + - Values: 16 to 32768 (default 1024) +
max_transfer_sizeThe maximum transfer size supported in bytes. + - Values: 2047 to 65,535 (default 65,535) +
max_packet_countThe maximum number of packets in a transfer. + - Values: 15 to 511 (default 511) +
host_channelsThe number of host channel registers to use. + - Values: 1 to 16 (default 12) + + Note: The FPGA configuration supports a maximum of 12 host channels. +
dev_endpointsThe number of endpoints in addition to EP0 available for device mode + operations. + - Values: 1 to 15 (default 6 IN and OUT) + + Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in + addition to EP0. +
phy_typeSpecifies the type of PHY interface to use. By default, the driver will + automatically detect the phy_type. + - 0: Full Speed + - 1: UTMI+ (default, if available) + - 2: ULPI +
phy_utmi_widthSpecifies the UTMI+ Data Width. This parameter is applicable for a + phy_type of UTMI+. Also, this parameter is applicable only if the + OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the + core has been configured to work at either data path width. + - Values: 8 or 16 bits (default 16) +
phy_ulpi_ddrSpecifies whether the ULPI operates at double or single data rate. This + parameter is only applicable if phy_type is ULPI. + - 0: single data rate ULPI interface with 8 bit wide data bus (default) + - 1: double data rate ULPI interface with 4 bit wide data bus +
i2c_enableSpecifies whether to use the I2C interface for full speed PHY. This + parameter is only applicable if PHY_TYPE is FS. + - 0: Disabled (default) + - 1: Enabled +
otg_en_multiple_tx_fifoSpecifies whether dedicatedto tx fifos are enabled for non periodic IN EPs. + The driver will automatically detect the value for this parameter if none is + specified. + - 0: Disabled + - 1: Enabled (default, if available) +
dev_tx_fifo_size_n (n = 1 to 15)Number of 4-byte words in each of the Tx FIFOs in device mode + when dynamic FIFO sizing is enabled. + - Values: 4 to 768 (default 256) +
-+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+
Name Description Access
mode Returns the current mode: 0 for device mode, 1 for host mode Read
hnpcapable Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register. -+ Read returns the current value. Read/Write
srpcapable Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register. -+ Read returns the current value. Read/Write
hnp Initiates the Host Negotiation Protocol. Read returns the status. Read/Write
srp Initiates the Session Request Protocol. Read returns the status. Read/Write
buspower Gets or sets the Power State of the bus (0 - Off or 1 - On) Read/Write
bussuspend Suspends the USB bus. Read/Write
busconnected Gets the connection status of the bus Read
gotgctl Gets or sets the Core Control Status Register. Read/Write
gusbcfg Gets or sets the Core USB Configuration Register Read/Write
grxfsiz Gets or sets the Receive FIFO Size Register Read/Write
gnptxfsiz Gets or sets the non-periodic Transmit Size Register Read/Write
gpvndctl Gets or sets the PHY Vendor Control Register Read/Write
ggpio Gets the value in the lower 16-bits of the General Purpose IO Register -+ or sets the upper 16 bits. Read/Write
guid Gets or sets the value of the User ID Register Read/Write
gsnpsid Gets the value of the Synopsys ID Regester Read
devspeed Gets or sets the device speed setting in the DCFG register Read/Write
enumspeed Gets the device enumeration Speed. Read
hptxfsiz Gets the value of the Host Periodic Transmit FIFO Read
hprt0 Gets or sets the value in the Host Port Control and Status Register Read/Write
regoffset Sets the register offset for the next Register Access Read/Write
regvalue Gets or sets the value of the register at the offset in the regoffset attribute. Read/Write
remote_wakeup On read, shows the status of Remote Wakeup. On write, initiates a remote -+ wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote -+ Wakeup signalling bit in the Device Control Register is set for 1 -+ milli-second. Read/Write
regdump Dumps the contents of core registers. Read
hcddump Dumps the current HCD state. Read
hcd_frrem Shows the average value of the Frame Remaining -+ field in the Host Frame Number/Frame Remaining register when an SOF interrupt -+ occurs. This can be used to determine the average interrupt latency. Also -+ shows the average Frame Remaining value for start_transfer and the "a" and -+ "b" sample points. The "a" and "b" sample points may be used during debugging -+ bto determine how long it takes to execute a section of the HCD code. Read
rd_reg_test Displays the time required to read the GNPTXFSIZ register many times -+ (the output shows the number of times the register is read). -+ Read
wr_reg_test Displays the time required to write the GNPTXFSIZ register many times -+ (the output shows the number of times the register is written). -+ Read
-+ -+ Example usage: -+ To get the current mode: -+ cat /sys/devices/lm0/mode -+ -+ To power down the USB: -+ echo 0 > /sys/devices/lm0/buspower -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include /* permission constants */ -+ -+#include -+ -+#include "dwc_otg_plat.h" -+#include "dwc_otg_attr.h" -+#include "dwc_otg_driver.h" -+// #include "dwc_otg_pcd.h" -+#include "dwc_otg_hcd.h" -+ -+// 20070316, winder added. -+#ifndef SZ_256K -+#define SZ_256K 0x00040000 -+#endif -+ -+/* -+ * MACROs for defining sysfs attribute -+ */ -+#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ -+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ -+{ \ -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\ -+ uint32_t val; \ -+ val = dwc_read_reg32 (_addr_); \ -+ val = (val & (_mask_)) >> _shift_; \ -+ return sprintf (buf, "%s = 0x%x\n", _string_, val); \ -+} -+#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ -+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count) \ -+{ \ -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\ -+ uint32_t set = simple_strtoul(buf, NULL, 16); \ -+ uint32_t clear = set; \ -+ clear = ((~clear) << _shift_) & _mask_; \ -+ set = (set << _shift_) & _mask_; \ -+ dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \ -+ dwc_modify_reg32(_addr_, clear, set); \ -+ return count; \ -+} -+ -+#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ -+DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ -+DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ -+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store); -+ -+#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ -+DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ -+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL); -+ -+/* -+ * MACROs for defining sysfs attribute for 32-bit registers -+ */ -+#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \ -+static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ -+{ \ -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\ -+ uint32_t val; \ -+ val = dwc_read_reg32 (_addr_); \ -+ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \ -+} -+#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \ -+static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count) \ -+{ \ -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\ -+ uint32_t val = simple_strtoul(buf, NULL, 16); \ -+ dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \ -+ dwc_write_reg32(_addr_, val); \ -+ return count; \ -+} -+ -+#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \ -+DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \ -+DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \ -+DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store); -+ -+#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \ -+DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \ -+DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL); -+ -+ -+/** @name Functions for Show/Store of Attributes */ -+/**@{*/ -+ -+/** -+ * Show the register offset of the Register Access. -+ */ -+static ssize_t regoffset_show( struct device *_dev, struct device_attribute *attr, char *buf) -+{ -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); -+ return snprintf(buf, sizeof("0xFFFFFFFF\n")+1,"0x%08x\n", otg_dev->reg_offset); -+} -+ -+/** -+ * Set the register offset for the next Register Access Read/Write -+ */ -+static ssize_t regoffset_store( struct device *_dev, struct device_attribute *attr, const char *buf, -+ size_t count ) -+{ -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); -+ uint32_t offset = simple_strtoul(buf, NULL, 16); -+ //dev_dbg(_dev, "Offset=0x%08x\n", offset); -+ if (offset < SZ_256K ) { -+ otg_dev->reg_offset = offset; -+ } -+ else { -+ dev_err( _dev, "invalid offset\n" ); -+ } -+ -+ return count; -+} -+DEVICE_ATTR(regoffset, S_IRUGO|S_IWUSR, regoffset_show, regoffset_store); -+ -+/** -+ * Show the value of the register at the offset in the reg_offset -+ * attribute. -+ */ -+static ssize_t regvalue_show( struct device *_dev, struct device_attribute *attr, char *buf) -+{ -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); -+ uint32_t val; -+ volatile uint32_t *addr; -+ -+ if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) { -+ /* Calculate the address */ -+ addr = (uint32_t*)(otg_dev->reg_offset + -+ (uint8_t*)otg_dev->base); -+ //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr); -+ val = dwc_read_reg32( addr ); -+ return snprintf(buf, sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n")+1, -+ "Reg@0x%06x = 0x%08x\n", -+ otg_dev->reg_offset, val); -+ } -+ else { -+ dev_err(_dev, "Invalid offset (0x%0x)\n", -+ otg_dev->reg_offset); -+ return sprintf(buf, "invalid offset\n" ); -+ } -+} -+ -+/** -+ * Store the value in the register at the offset in the reg_offset -+ * attribute. -+ * -+ */ -+static ssize_t regvalue_store( struct device *_dev, struct device_attribute *attr, const char *buf, -+ size_t count ) -+{ -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); -+ volatile uint32_t * addr; -+ uint32_t val = simple_strtoul(buf, NULL, 16); -+ //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val); -+ if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) { -+ /* Calculate the address */ -+ addr = (uint32_t*)(otg_dev->reg_offset + -+ (uint8_t*)otg_dev->base); -+ //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr); -+ dwc_write_reg32( addr, val ); -+ } -+ else { -+ dev_err(_dev, "Invalid Register Offset (0x%08x)\n", -+ otg_dev->reg_offset); -+ } -+ return count; -+} -+DEVICE_ATTR(regvalue, S_IRUGO|S_IWUSR, regvalue_show, regvalue_store); -+ -+/* -+ * Attributes -+ */ -+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<20),20,"Mode"); -+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<9),9,"Mode"); -+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<8),8,"Mode"); -+ -+//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); -+//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); -+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected,otg_dev->core_if->host_if->hprt0,0x01,0,"Bus Connected"); -+ -+DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl,&(otg_dev->core_if->core_global_regs->gotgctl),"GOTGCTL"); -+DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,&(otg_dev->core_if->core_global_regs->gusbcfg),"GUSBCFG"); -+DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,&(otg_dev->core_if->core_global_regs->grxfsiz),"GRXFSIZ"); -+DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,&(otg_dev->core_if->core_global_regs->gnptxfsiz),"GNPTXFSIZ"); -+DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,&(otg_dev->core_if->core_global_regs->gpvndctl),"GPVNDCTL"); -+DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,&(otg_dev->core_if->core_global_regs->ggpio),"GGPIO"); -+DWC_OTG_DEVICE_ATTR_REG32_RW(guid,&(otg_dev->core_if->core_global_regs->guid),"GUID"); -+DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,&(otg_dev->core_if->core_global_regs->gsnpsid),"GSNPSID"); -+DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dcfg),0x3,0,"Device Speed"); -+DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dsts),0x6,1,"Device Enumeration Speed"); -+ -+DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,&(otg_dev->core_if->core_global_regs->hptxfsiz),"HPTXFSIZ"); -+DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0,otg_dev->core_if->host_if->hprt0,"HPRT0"); -+ -+ -+/** -+ * @todo Add code to initiate the HNP. -+ */ -+/** -+ * Show the HNP status bit -+ */ -+static ssize_t hnp_show( struct device *_dev, struct device_attribute *attr, char *buf) -+{ -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); -+ gotgctl_data_t val; -+ val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl)); -+ return sprintf (buf, "HstNegScs = 0x%x\n", val.b.hstnegscs); -+} -+ -+/** -+ * Set the HNP Request bit -+ */ -+static ssize_t hnp_store( struct device *_dev, struct device_attribute *attr, const char *buf, -+ size_t count ) -+{ -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); -+ uint32_t in = simple_strtoul(buf, NULL, 16); -+ uint32_t *addr = (uint32_t *)&(otg_dev->core_if->core_global_regs->gotgctl); -+ gotgctl_data_t mem; -+ mem.d32 = dwc_read_reg32(addr); -+ mem.b.hnpreq = in; -+ dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32); -+ dwc_write_reg32(addr, mem.d32); -+ return count; -+} -+DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store); -+ -+/** -+ * @todo Add code to initiate the SRP. -+ */ -+/** -+ * Show the SRP status bit -+ */ -+static ssize_t srp_show( struct device *_dev, struct device_attribute *attr, char *buf) -+{ -+#ifndef DWC_HOST_ONLY -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); -+ gotgctl_data_t val; -+ val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl)); -+ return sprintf (buf, "SesReqScs = 0x%x\n", val.b.sesreqscs); -+#else -+ return sprintf(buf, "Host Only Mode!\n"); -+#endif -+} -+ -+/** -+ * Set the SRP Request bit -+ */ -+static ssize_t srp_store( struct device *_dev, struct device_attribute *attr, const char *buf, -+ size_t count ) -+{ -+#ifndef DWC_HOST_ONLY -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); -+ dwc_otg_pcd_initiate_srp(otg_dev->pcd); -+#endif -+ return count; -+} -+DEVICE_ATTR(srp, 0644, srp_show, srp_store); -+ -+/** -+ * @todo Need to do more for power on/off? -+ */ -+/** -+ * Show the Bus Power status -+ */ -+static ssize_t buspower_show( struct device *_dev, struct device_attribute *attr, char *buf) -+{ -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); -+ hprt0_data_t val; -+ val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0); -+ return sprintf (buf, "Bus Power = 0x%x\n", val.b.prtpwr); -+} -+ -+ -+/** -+ * Set the Bus Power status -+ */ -+static ssize_t buspower_store( struct device *_dev, struct device_attribute *attr, const char *buf, -+ size_t count ) -+{ -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); -+ uint32_t on = simple_strtoul(buf, NULL, 16); -+ uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0; -+ hprt0_data_t mem; -+ -+ mem.d32 = dwc_read_reg32(addr); -+ mem.b.prtpwr = on; -+ -+ //dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32); -+ dwc_write_reg32(addr, mem.d32); -+ -+ return count; -+} -+DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store); -+ -+/** -+ * @todo Need to do more for suspend? -+ */ -+/** -+ * Show the Bus Suspend status -+ */ -+static ssize_t bussuspend_show( struct device *_dev, struct device_attribute *attr, char *buf) -+{ -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); -+ hprt0_data_t val; -+ val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0); -+ return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp); -+} -+ -+/** -+ * Set the Bus Suspend status -+ */ -+static ssize_t bussuspend_store( struct device *_dev, struct device_attribute *attr, const char *buf, -+ size_t count ) -+{ -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); -+ uint32_t in = simple_strtoul(buf, NULL, 16); -+ uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0; -+ hprt0_data_t mem; -+ mem.d32 = dwc_read_reg32(addr); -+ mem.b.prtsusp = in; -+ dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32); -+ dwc_write_reg32(addr, mem.d32); -+ return count; -+} -+DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store); -+ -+/** -+ * Show the status of Remote Wakeup. -+ */ -+static ssize_t remote_wakeup_show( struct device *_dev, struct device_attribute *attr, char *buf) -+{ -+#ifndef DWC_HOST_ONLY -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); -+ dctl_data_t val; -+ val.d32 = dwc_read_reg32( &otg_dev->core_if->dev_if->dev_global_regs->dctl); -+ return sprintf( buf, "Remote Wakeup = %d Enabled = %d\n", -+ val.b.rmtwkupsig, otg_dev->pcd->remote_wakeup_enable); -+#else -+ return sprintf(buf, "Host Only Mode!\n"); -+#endif -+} -+ -+/** -+ * Initiate a remote wakeup of the host. The Device control register -+ * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable -+ * flag is set. -+ * -+ */ -+static ssize_t remote_wakeup_store( struct device *_dev, struct device_attribute *attr, const char *buf, -+ size_t count ) -+{ -+#ifndef DWC_HOST_ONLY -+ uint32_t val = simple_strtoul(buf, NULL, 16); -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); -+ if (val&1) { -+ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1); -+ } -+ else { -+ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0); -+ } -+#endif -+ return count; -+} -+DEVICE_ATTR(remote_wakeup, S_IRUGO|S_IWUSR, remote_wakeup_show, -+ remote_wakeup_store); -+ -+/** -+ * Dump global registers and either host or device registers (depending on the -+ * current mode of the core). -+ */ -+static ssize_t regdump_show( struct device *_dev, struct device_attribute *attr, char *buf) -+{ -+#ifdef DEBUG -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); -+ printk("%s otg_dev=0x%p\n", __FUNCTION__, otg_dev); -+ -+ dwc_otg_dump_global_registers( otg_dev->core_if); -+ if (dwc_otg_is_host_mode(otg_dev->core_if)) { -+ dwc_otg_dump_host_registers( otg_dev->core_if); -+ } else { -+ dwc_otg_dump_dev_registers( otg_dev->core_if); -+ } -+#endif -+ -+ return sprintf( buf, "Register Dump\n" ); -+} -+ -+DEVICE_ATTR(regdump, S_IRUGO|S_IWUSR, regdump_show, 0); -+ -+/** -+ * Dump the current hcd state. -+ */ -+static ssize_t hcddump_show( struct device *_dev, struct device_attribute *attr, char *buf) -+{ -+#ifndef DWC_DEVICE_ONLY -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); -+ dwc_otg_hcd_dump_state(otg_dev->hcd); -+#endif -+ return sprintf( buf, "HCD Dump\n" ); -+} -+ -+DEVICE_ATTR(hcddump, S_IRUGO|S_IWUSR, hcddump_show, 0); -+ -+/** -+ * Dump the average frame remaining at SOF. This can be used to -+ * determine average interrupt latency. Frame remaining is also shown for -+ * start transfer and two additional sample points. -+ */ -+static ssize_t hcd_frrem_show( struct device *_dev, struct device_attribute *attr, char *buf) -+{ -+#ifndef DWC_DEVICE_ONLY -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); -+ dwc_otg_hcd_dump_frrem(otg_dev->hcd); -+#endif -+ return sprintf( buf, "HCD Dump Frame Remaining\n" ); -+} -+ -+DEVICE_ATTR(hcd_frrem, S_IRUGO|S_IWUSR, hcd_frrem_show, 0); -+ -+/** -+ * Displays the time required to read the GNPTXFSIZ register many times (the -+ * output shows the number of times the register is read). -+ */ -+#define RW_REG_COUNT 10000000 -+#define MSEC_PER_JIFFIE 1000/HZ -+static ssize_t rd_reg_test_show( struct device *_dev, struct device_attribute *attr, char *buf) -+{ -+ int i; -+ int time; -+ int start_jiffies; -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); -+ -+ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n", -+ HZ, MSEC_PER_JIFFIE, loops_per_jiffy); -+ start_jiffies = jiffies; -+ for (i = 0; i < RW_REG_COUNT; i++) { -+ dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz); -+ } -+ time = jiffies - start_jiffies; -+ return sprintf( buf, "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n", -+ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time ); -+} -+ -+DEVICE_ATTR(rd_reg_test, S_IRUGO|S_IWUSR, rd_reg_test_show, 0); -+ -+/** -+ * Displays the time required to write the GNPTXFSIZ register many times (the -+ * output shows the number of times the register is written). -+ */ -+static ssize_t wr_reg_test_show( struct device *_dev, struct device_attribute *attr, char *buf) -+{ -+ int i; -+ int time; -+ int start_jiffies; -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); -+ uint32_t reg_val; -+ -+ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n", -+ HZ, MSEC_PER_JIFFIE, loops_per_jiffy); -+ reg_val = dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz); -+ start_jiffies = jiffies; -+ for (i = 0; i < RW_REG_COUNT; i++) { -+ dwc_write_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz, reg_val); -+ } -+ time = jiffies - start_jiffies; -+ return sprintf( buf, "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n", -+ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time); -+} -+ -+DEVICE_ATTR(wr_reg_test, S_IRUGO|S_IWUSR, wr_reg_test_show, 0); -+/**@}*/ -+ -+/** -+ * Create the device files -+ */ -+void dwc_otg_attr_create (struct device *_dev) -+{ -+ int retval; -+ -+ retval = device_create_file(_dev, &dev_attr_regoffset); -+ retval += device_create_file(_dev, &dev_attr_regvalue); -+ retval += device_create_file(_dev, &dev_attr_mode); -+ retval += device_create_file(_dev, &dev_attr_hnpcapable); -+ retval += device_create_file(_dev, &dev_attr_srpcapable); -+ retval += device_create_file(_dev, &dev_attr_hnp); -+ retval += device_create_file(_dev, &dev_attr_srp); -+ retval += device_create_file(_dev, &dev_attr_buspower); -+ retval += device_create_file(_dev, &dev_attr_bussuspend); -+ retval += device_create_file(_dev, &dev_attr_busconnected); -+ retval += device_create_file(_dev, &dev_attr_gotgctl); -+ retval += device_create_file(_dev, &dev_attr_gusbcfg); -+ retval += device_create_file(_dev, &dev_attr_grxfsiz); -+ retval += device_create_file(_dev, &dev_attr_gnptxfsiz); -+ retval += device_create_file(_dev, &dev_attr_gpvndctl); -+ retval += device_create_file(_dev, &dev_attr_ggpio); -+ retval += device_create_file(_dev, &dev_attr_guid); -+ retval += device_create_file(_dev, &dev_attr_gsnpsid); -+ retval += device_create_file(_dev, &dev_attr_devspeed); -+ retval += device_create_file(_dev, &dev_attr_enumspeed); -+ retval += device_create_file(_dev, &dev_attr_hptxfsiz); -+ retval += device_create_file(_dev, &dev_attr_hprt0); -+ retval += device_create_file(_dev, &dev_attr_remote_wakeup); -+ retval += device_create_file(_dev, &dev_attr_regdump); -+ retval += device_create_file(_dev, &dev_attr_hcddump); -+ retval += device_create_file(_dev, &dev_attr_hcd_frrem); -+ retval += device_create_file(_dev, &dev_attr_rd_reg_test); -+ retval += device_create_file(_dev, &dev_attr_wr_reg_test); -+ -+ if(retval != 0) -+ { -+ DWC_PRINT("cannot create sysfs device files.\n"); -+ // DWC_PRINT("killing own sysfs device files!\n"); -+ dwc_otg_attr_remove(_dev); -+ } -+} -+ -+/** -+ * Remove the device files -+ */ -+void dwc_otg_attr_remove (struct device *_dev) -+{ -+ device_remove_file(_dev, &dev_attr_regoffset); -+ device_remove_file(_dev, &dev_attr_regvalue); -+ device_remove_file(_dev, &dev_attr_mode); -+ device_remove_file(_dev, &dev_attr_hnpcapable); -+ device_remove_file(_dev, &dev_attr_srpcapable); -+ device_remove_file(_dev, &dev_attr_hnp); -+ device_remove_file(_dev, &dev_attr_srp); -+ device_remove_file(_dev, &dev_attr_buspower); -+ device_remove_file(_dev, &dev_attr_bussuspend); -+ device_remove_file(_dev, &dev_attr_busconnected); -+ device_remove_file(_dev, &dev_attr_gotgctl); -+ device_remove_file(_dev, &dev_attr_gusbcfg); -+ device_remove_file(_dev, &dev_attr_grxfsiz); -+ device_remove_file(_dev, &dev_attr_gnptxfsiz); -+ device_remove_file(_dev, &dev_attr_gpvndctl); -+ device_remove_file(_dev, &dev_attr_ggpio); -+ device_remove_file(_dev, &dev_attr_guid); -+ device_remove_file(_dev, &dev_attr_gsnpsid); -+ device_remove_file(_dev, &dev_attr_devspeed); -+ device_remove_file(_dev, &dev_attr_enumspeed); -+ device_remove_file(_dev, &dev_attr_hptxfsiz); -+ device_remove_file(_dev, &dev_attr_hprt0); -+ device_remove_file(_dev, &dev_attr_remote_wakeup); -+ device_remove_file(_dev, &dev_attr_regdump); -+ device_remove_file(_dev, &dev_attr_hcddump); -+ device_remove_file(_dev, &dev_attr_hcd_frrem); -+ device_remove_file(_dev, &dev_attr_rd_reg_test); -+ device_remove_file(_dev, &dev_attr_wr_reg_test); -+} ---- /dev/null -+++ b/drivers/usb/dwc_otg/dwc_otg_attr.h -@@ -0,0 +1,67 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_attr.h $ -+ * $Revision: 1.1.1.1 $ -+ * $Date: 2009-04-17 06:15:34 $ -+ * $Change: 510275 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+#if !defined(__DWC_OTG_ATTR_H__) -+#define __DWC_OTG_ATTR_H__ -+ -+/** @file -+ * This file contains the interface to the Linux device attributes. -+ */ -+extern struct device_attribute dev_attr_regoffset; -+extern struct device_attribute dev_attr_regvalue; -+ -+extern struct device_attribute dev_attr_mode; -+extern struct device_attribute dev_attr_hnpcapable; -+extern struct device_attribute dev_attr_srpcapable; -+extern struct device_attribute dev_attr_hnp; -+extern struct device_attribute dev_attr_srp; -+extern struct device_attribute dev_attr_buspower; -+extern struct device_attribute dev_attr_bussuspend; -+extern struct device_attribute dev_attr_busconnected; -+extern struct device_attribute dev_attr_gotgctl; -+extern struct device_attribute dev_attr_gusbcfg; -+extern struct device_attribute dev_attr_grxfsiz; -+extern struct device_attribute dev_attr_gnptxfsiz; -+extern struct device_attribute dev_attr_gpvndctl; -+extern struct device_attribute dev_attr_ggpio; -+extern struct device_attribute dev_attr_guid; -+extern struct device_attribute dev_attr_gsnpsid; -+extern struct device_attribute dev_attr_devspeed; -+extern struct device_attribute dev_attr_enumspeed; -+extern struct device_attribute dev_attr_hptxfsiz; -+extern struct device_attribute dev_attr_hprt0; -+ -+void dwc_otg_attr_create (struct device *_dev); -+void dwc_otg_attr_remove (struct device *_dev); -+ -+#endif ---- /dev/null -+++ b/drivers/usb/dwc_otg/dwc_otg_cil.c -@@ -0,0 +1,3025 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil.c $ -+ * $Revision: 1.1.1.1 $ -+ * $Date: 2009-04-17 06:15:34 $ -+ * $Change: 631780 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+/** @file -+ * -+ * The Core Interface Layer provides basic services for accessing and -+ * managing the DWC_otg hardware. These services are used by both the -+ * Host Controller Driver and the Peripheral Controller Driver. -+ * -+ * The CIL manages the memory map for the core so that the HCD and PCD -+ * don't have to do this separately. It also handles basic tasks like -+ * reading/writing the registers and data FIFOs in the controller. -+ * Some of the data access functions provide encapsulation of several -+ * operations required to perform a task, such as writing multiple -+ * registers to start a transfer. Finally, the CIL performs basic -+ * services that are not specific to either the host or device modes -+ * of operation. These services include management of the OTG Host -+ * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A -+ * Diagnostic API is also provided to allow testing of the controller -+ * hardware. -+ * -+ * The Core Interface Layer has the following requirements: -+ * - Provides basic controller operations. -+ * - Minimal use of OS services. -+ * - The OS services used will be abstracted by using inline functions -+ * or macros. -+ * -+ */ -+#include -+ -+#ifdef DEBUG -+#include -+#endif -+ -+#include "dwc_otg_plat.h" -+ -+#include "dwc_otg_regs.h" -+#include "dwc_otg_cil.h" -+ -+/** -+ * This function is called to initialize the DWC_otg CSR data -+ * structures. The register addresses in the device and host -+ * structures are initialized from the base address supplied by the -+ * caller. The calling function must make the OS calls to get the -+ * base address of the DWC_otg controller registers. The core_params -+ * argument holds the parameters that specify how the core should be -+ * configured. -+ * -+ * @param[in] _reg_base_addr Base address of DWC_otg core registers -+ * @param[in] _core_params Pointer to the core configuration parameters -+ * -+ */ -+dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr, -+ dwc_otg_core_params_t *_core_params) -+{ -+ dwc_otg_core_if_t *core_if = 0; -+ dwc_otg_dev_if_t *dev_if = 0; -+ dwc_otg_host_if_t *host_if = 0; -+ uint8_t *reg_base = (uint8_t *)_reg_base_addr; -+ int i = 0; -+ -+ DWC_DEBUGPL(DBG_CILV, "%s(%p,%p)\n", __func__, _reg_base_addr, _core_params); -+ -+ core_if = kmalloc( sizeof(dwc_otg_core_if_t), GFP_KERNEL); -+ if (core_if == 0) { -+ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_core_if_t failed\n"); -+ return 0; -+ } -+ memset(core_if, 0, sizeof(dwc_otg_core_if_t)); -+ -+ core_if->core_params = _core_params; -+ core_if->core_global_regs = (dwc_otg_core_global_regs_t *)reg_base; -+ /* -+ * Allocate the Device Mode structures. -+ */ -+ dev_if = kmalloc( sizeof(dwc_otg_dev_if_t), GFP_KERNEL); -+ if (dev_if == 0) { -+ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n"); -+ kfree( core_if ); -+ return 0; -+ } -+ -+ dev_if->dev_global_regs = -+ (dwc_otg_device_global_regs_t *)(reg_base + DWC_DEV_GLOBAL_REG_OFFSET); -+ -+ for (i=0; iin_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *) -+ (reg_base + DWC_DEV_IN_EP_REG_OFFSET + -+ (i * DWC_EP_REG_OFFSET)); -+ -+ dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *) -+ (reg_base + DWC_DEV_OUT_EP_REG_OFFSET + -+ (i * DWC_EP_REG_OFFSET)); -+ DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n", -+ i, &dev_if->in_ep_regs[i]->diepctl); -+ DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n", -+ i, &dev_if->out_ep_regs[i]->doepctl); -+ } -+ dev_if->speed = 0; // unknown -+ //dev_if->num_eps = MAX_EPS_CHANNELS; -+ //dev_if->num_perio_eps = 0; -+ -+ core_if->dev_if = dev_if; -+ /* -+ * Allocate the Host Mode structures. -+ */ -+ host_if = kmalloc( sizeof(dwc_otg_host_if_t), GFP_KERNEL); -+ if (host_if == 0) { -+ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_host_if_t failed\n"); -+ kfree( dev_if ); -+ kfree( core_if ); -+ return 0; -+ } -+ -+ host_if->host_global_regs = (dwc_otg_host_global_regs_t *) -+ (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET); -+ host_if->hprt0 = (uint32_t*)(reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET); -+ for (i=0; ihc_regs[i] = (dwc_otg_hc_regs_t *) -+ (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET + -+ (i * DWC_OTG_CHAN_REGS_OFFSET)); -+ DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n", -+ i, &host_if->hc_regs[i]->hcchar); -+ } -+ host_if->num_host_channels = MAX_EPS_CHANNELS; -+ core_if->host_if = host_if; -+ -+ for (i=0; idata_fifo[i] = -+ (uint32_t *)(reg_base + DWC_OTG_DATA_FIFO_OFFSET + -+ (i * DWC_OTG_DATA_FIFO_SIZE)); -+ DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n", -+ i, (unsigned)core_if->data_fifo[i]); -+ } // for loop. -+ -+ core_if->pcgcctl = (uint32_t*)(reg_base + DWC_OTG_PCGCCTL_OFFSET); -+ -+ /* -+ * Store the contents of the hardware configuration registers here for -+ * easy access later. -+ */ -+ core_if->hwcfg1.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg1); -+ core_if->hwcfg2.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg2); -+ core_if->hwcfg3.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg3); -+ core_if->hwcfg4.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg4); -+ -+ DWC_DEBUGPL(DBG_CILV,"hwcfg1=%08x\n",core_if->hwcfg1.d32); -+ DWC_DEBUGPL(DBG_CILV,"hwcfg2=%08x\n",core_if->hwcfg2.d32); -+ DWC_DEBUGPL(DBG_CILV,"hwcfg3=%08x\n",core_if->hwcfg3.d32); -+ DWC_DEBUGPL(DBG_CILV,"hwcfg4=%08x\n",core_if->hwcfg4.d32); -+ -+ -+ DWC_DEBUGPL(DBG_CILV,"op_mode=%0x\n",core_if->hwcfg2.b.op_mode); -+ DWC_DEBUGPL(DBG_CILV,"arch=%0x\n",core_if->hwcfg2.b.architecture); -+ DWC_DEBUGPL(DBG_CILV,"num_dev_ep=%d\n",core_if->hwcfg2.b.num_dev_ep); -+ DWC_DEBUGPL(DBG_CILV,"num_host_chan=%d\n",core_if->hwcfg2.b.num_host_chan); -+ DWC_DEBUGPL(DBG_CILV,"nonperio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.nonperio_tx_q_depth); -+ DWC_DEBUGPL(DBG_CILV,"host_perio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.host_perio_tx_q_depth); -+ DWC_DEBUGPL(DBG_CILV,"dev_token_q_depth=0x%0x\n",core_if->hwcfg2.b.dev_token_q_depth); -+ -+ DWC_DEBUGPL(DBG_CILV,"Total FIFO SZ=%d\n", core_if->hwcfg3.b.dfifo_depth); -+ DWC_DEBUGPL(DBG_CILV,"xfer_size_cntr_width=%0x\n", core_if->hwcfg3.b.xfer_size_cntr_width); -+ -+ /* -+ * Set the SRP sucess bit for FS-I2c -+ */ -+ core_if->srp_success = 0; -+ core_if->srp_timer_started = 0; -+ -+ return core_if; -+} -+/** -+ * This function frees the structures allocated by dwc_otg_cil_init(). -+ * -+ * @param[in] _core_if The core interface pointer returned from -+ * dwc_otg_cil_init(). -+ * -+ */ -+void dwc_otg_cil_remove( dwc_otg_core_if_t *_core_if ) -+{ -+ /* Disable all interrupts */ -+ dwc_modify_reg32( &_core_if->core_global_regs->gahbcfg, 1, 0); -+ dwc_write_reg32( &_core_if->core_global_regs->gintmsk, 0); -+ -+ if ( _core_if->dev_if ) { -+ kfree( _core_if->dev_if ); -+ } -+ if ( _core_if->host_if ) { -+ kfree( _core_if->host_if ); -+ } -+ kfree( _core_if ); -+} -+ -+/** -+ * This function enables the controller's Global Interrupt in the AHB Config -+ * register. -+ * -+ * @param[in] _core_if Programming view of DWC_otg controller. -+ */ -+extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if ) -+{ -+ gahbcfg_data_t ahbcfg = { .d32 = 0}; -+ ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ -+ dwc_modify_reg32(&_core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32); -+} -+/** -+ * This function disables the controller's Global Interrupt in the AHB Config -+ * register. -+ * -+ * @param[in] _core_if Programming view of DWC_otg controller. -+ */ -+extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if ) -+{ -+ gahbcfg_data_t ahbcfg = { .d32 = 0}; -+ ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ -+ dwc_modify_reg32(&_core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0); -+} -+ -+/** -+ * This function initializes the commmon interrupts, used in both -+ * device and host modes. -+ * -+ * @param[in] _core_if Programming view of the DWC_otg controller -+ * -+ */ -+static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t *_core_if) -+{ -+ dwc_otg_core_global_regs_t *global_regs = -+ _core_if->core_global_regs; -+ gintmsk_data_t intr_mask = { .d32 = 0}; -+ /* Clear any pending OTG Interrupts */ -+ dwc_write_reg32( &global_regs->gotgint, 0xFFFFFFFF); -+ /* Clear any pending interrupts */ -+ dwc_write_reg32( &global_regs->gintsts, 0xFFFFFFFF); -+ /* -+ * Enable the interrupts in the GINTMSK. -+ */ -+ intr_mask.b.modemismatch = 1; -+ intr_mask.b.otgintr = 1; -+ if (!_core_if->dma_enable) { -+ intr_mask.b.rxstsqlvl = 1; -+ } -+ intr_mask.b.conidstschng = 1; -+ intr_mask.b.wkupintr = 1; -+ intr_mask.b.disconnect = 1; -+ intr_mask.b.usbsuspend = 1; -+ intr_mask.b.sessreqintr = 1; -+ dwc_write_reg32( &global_regs->gintmsk, intr_mask.d32); -+} -+ -+/** -+ * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY -+ * type. -+ */ -+static void init_fslspclksel(dwc_otg_core_if_t *_core_if) -+{ -+ uint32_t val; -+ hcfg_data_t hcfg; -+ -+ if (((_core_if->hwcfg2.b.hs_phy_type == 2) && -+ (_core_if->hwcfg2.b.fs_phy_type == 1) && -+ (_core_if->core_params->ulpi_fs_ls)) || -+ (_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) -+ { -+ /* Full speed PHY */ -+ val = DWC_HCFG_48_MHZ; -+ } else { -+ /* High speed PHY running at full speed or high speed */ -+ val = DWC_HCFG_30_60_MHZ; -+ } -+ -+ DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val); -+ hcfg.d32 = dwc_read_reg32(&_core_if->host_if->host_global_regs->hcfg); -+ hcfg.b.fslspclksel = val; -+ dwc_write_reg32(&_core_if->host_if->host_global_regs->hcfg, hcfg.d32); -+} -+ -+/** -+ * Initializes the DevSpd field of the DCFG register depending on the PHY type -+ * and the enumeration speed of the device. -+ */ -+static void init_devspd(dwc_otg_core_if_t *_core_if) -+{ -+ uint32_t val; -+ dcfg_data_t dcfg; -+ -+ if (((_core_if->hwcfg2.b.hs_phy_type == 2) && -+ (_core_if->hwcfg2.b.fs_phy_type == 1) && -+ (_core_if->core_params->ulpi_fs_ls)) || -+ (_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) -+ { -+ /* Full speed PHY */ -+ val = 0x3; -+ } else if (_core_if->core_params->speed == DWC_SPEED_PARAM_FULL) { -+ /* High speed PHY running at full speed */ -+ val = 0x1; -+ } else { -+ /* High speed PHY running at high speed */ -+ val = 0x0; -+ } -+ -+ DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val); -+ dcfg.d32 = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->dcfg); -+ dcfg.b.devspd = val; -+ dwc_write_reg32(&_core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); -+} -+ -+/** -+ * This function calculates the number of IN EPS -+ * using GHWCFG1 and GHWCFG2 registers values -+ * -+ * @param _pcd the pcd structure. -+ */ -+static uint32_t calc_num_in_eps(dwc_otg_core_if_t * _core_if) -+{ -+ uint32_t num_in_eps = 0; -+ uint32_t num_eps = _core_if->hwcfg2.b.num_dev_ep; -+ uint32_t hwcfg1 = _core_if->hwcfg1.d32 >> 2; -+ uint32_t num_tx_fifos = _core_if->hwcfg4.b.num_in_eps; -+ int i; -+ for (i = 0; i < num_eps; ++i) { -+ if (!(hwcfg1 & 0x1)) -+ num_in_eps++; -+ hwcfg1 >>= 2; -+ } -+ if (_core_if->hwcfg4.b.ded_fifo_en) { -+ num_in_eps = (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps; -+ } -+ return num_in_eps; -+} -+ -+ -+/** -+ * This function calculates the number of OUT EPS -+ * using GHWCFG1 and GHWCFG2 registers values -+ * -+ * @param _pcd the pcd structure. -+ */ -+static uint32_t calc_num_out_eps(dwc_otg_core_if_t * _core_if) -+{ -+ uint32_t num_out_eps = 0; -+ uint32_t num_eps = _core_if->hwcfg2.b.num_dev_ep; -+ uint32_t hwcfg1 = _core_if->hwcfg1.d32 >> 2; -+ int i; -+ for (i = 0; i < num_eps; ++i) { -+ if (!(hwcfg1 & 0x2)) -+ num_out_eps++; -+ hwcfg1 >>= 2; -+ } -+ return num_out_eps; -+} -+/** -+ * This function initializes the DWC_otg controller registers and -+ * prepares the core for device mode or host mode operation. -+ * -+ * @param _core_if Programming view of the DWC_otg controller -+ * -+ */ -+void dwc_otg_core_init(dwc_otg_core_if_t *_core_if) -+{ -+ dwc_otg_core_global_regs_t * global_regs = _core_if->core_global_regs; -+ dwc_otg_dev_if_t *dev_if = _core_if->dev_if; -+ int i = 0; -+ gahbcfg_data_t ahbcfg = { .d32 = 0}; -+ gusbcfg_data_t usbcfg = { .d32 = 0 }; -+ gi2cctl_data_t i2cctl = {.d32 = 0}; -+ -+ DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n",_core_if); -+ -+ /* Common Initialization */ -+ -+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); -+ DWC_DEBUGPL(DBG_CIL, "USB config register: 0x%08x\n", usbcfg.d32); -+ -+ /* Program the ULPI External VBUS bit if needed */ -+ //usbcfg.b.ulpi_ext_vbus_drv = 1; -+ //usbcfg.b.ulpi_ext_vbus_drv = 0; -+ usbcfg.b.ulpi_ext_vbus_drv = -+ (_core_if->core_params->phy_ulpi_ext_vbus == DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0; -+ -+ /* Set external TS Dline pulsing */ -+ usbcfg.b.term_sel_dl_pulse = (_core_if->core_params->ts_dline == 1) ? 1 : 0; -+ dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32); -+ -+ /* Reset the Controller */ -+ dwc_otg_core_reset( _core_if ); -+ -+ /* Initialize parameters from Hardware configuration registers. */ -+#if 0 -+ dev_if->num_eps = _core_if->hwcfg2.b.num_dev_ep; -+ dev_if->num_perio_eps = _core_if->hwcfg4.b.num_dev_perio_in_ep; -+#else -+ dev_if->num_in_eps = calc_num_in_eps(_core_if); -+ dev_if->num_out_eps = calc_num_out_eps(_core_if); -+#endif -+ DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n", -+ _core_if->hwcfg4.b.num_dev_perio_in_ep); -+ DWC_DEBUGPL(DBG_CIL, "Is power optimization enabled? %s\n", -+ _core_if->hwcfg4.b.power_optimiz ? "Yes" : "No"); -+ DWC_DEBUGPL(DBG_CIL, "vbus_valid filter enabled? %s\n", -+ _core_if->hwcfg4.b.vbus_valid_filt_en ? "Yes" : "No"); -+ DWC_DEBUGPL(DBG_CIL, "iddig filter enabled? %s\n", -+ _core_if->hwcfg4.b.iddig_filt_en ? "Yes" : "No"); -+ -+ DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",_core_if->hwcfg4.b.num_dev_perio_in_ep); -+ for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++) { -+ dev_if->perio_tx_fifo_size[i] = -+ dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16; -+ DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n", i, -+ dev_if->perio_tx_fifo_size[i]); -+ } -+ for (i = 0; i < _core_if->hwcfg4.b.num_in_eps; i++) { -+ dev_if->tx_fifo_size[i] = -+ dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16; -+ DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n", i, -+ dev_if->perio_tx_fifo_size[i]); -+ } -+ -+ _core_if->total_fifo_size = _core_if->hwcfg3.b.dfifo_depth; -+ _core_if->rx_fifo_size = dwc_read_reg32(&global_regs->grxfsiz); -+ _core_if->nperio_tx_fifo_size = dwc_read_reg32(&global_regs->gnptxfsiz) >> 16; -+ -+ DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", _core_if->total_fifo_size); -+ DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", _core_if->rx_fifo_size); -+ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n", _core_if->nperio_tx_fifo_size); -+ -+ /* This programming sequence needs to happen in FS mode before any other -+ * programming occurs */ -+ if ((_core_if->core_params->speed == DWC_SPEED_PARAM_FULL) && -+ (_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) { -+ /* If FS mode with FS PHY */ -+ -+ /* core_init() is now called on every switch so only call the -+ * following for the first time through. */ -+ if (!_core_if->phy_init_done) { -+ _core_if->phy_init_done = 1; -+ DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n"); -+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); -+ usbcfg.b.physel = 1; -+ dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32); -+ -+ /* Reset after a PHY select */ -+ dwc_otg_core_reset( _core_if ); -+ } -+ -+ /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also -+ * do this on HNP Dev/Host mode switches (done in dev_init and -+ * host_init). */ -+ if (dwc_otg_is_host_mode(_core_if)) { -+ DWC_DEBUGPL(DBG_CIL, "host mode\n"); -+ init_fslspclksel(_core_if); -+ } else { -+ DWC_DEBUGPL(DBG_CIL, "device mode\n"); -+ init_devspd(_core_if); -+ } -+ -+ if (_core_if->core_params->i2c_enable) { -+ DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n"); -+ /* Program GUSBCFG.OtgUtmifsSel to I2C */ -+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); -+ usbcfg.b.otgutmifssel = 1; -+ dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32); -+ -+ /* Program GI2CCTL.I2CEn */ -+ i2cctl.d32 = dwc_read_reg32(&global_regs->gi2cctl); -+ i2cctl.b.i2cdevaddr = 1; -+ i2cctl.b.i2cen = 0; -+ dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32); -+ i2cctl.b.i2cen = 1; -+ dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32); -+ } -+ -+ } /* endif speed == DWC_SPEED_PARAM_FULL */ -+ else { -+ /* High speed PHY. */ -+ if (!_core_if->phy_init_done) { -+ _core_if->phy_init_done = 1; -+ DWC_DEBUGPL(DBG_CIL, "High spped PHY\n"); -+ /* HS PHY parameters. These parameters are preserved -+ * during soft reset so only program the first time. Do -+ * a soft reset immediately after setting phyif. */ -+ usbcfg.b.ulpi_utmi_sel = _core_if->core_params->phy_type; -+ if (usbcfg.b.ulpi_utmi_sel == 2) { // winder -+ DWC_DEBUGPL(DBG_CIL, "ULPI\n"); -+ /* ULPI interface */ -+ usbcfg.b.phyif = 0; -+ usbcfg.b.ddrsel = _core_if->core_params->phy_ulpi_ddr; -+ } else { -+ /* UTMI+ interface */ -+ if (_core_if->core_params->phy_utmi_width == 16) { -+ usbcfg.b.phyif = 1; -+ DWC_DEBUGPL(DBG_CIL, "UTMI+ 16\n"); -+ } else { -+ DWC_DEBUGPL(DBG_CIL, "UTMI+ 8\n"); -+ usbcfg.b.phyif = 0; -+ } -+ } -+ dwc_write_reg32( &global_regs->gusbcfg, usbcfg.d32); -+ -+ /* Reset after setting the PHY parameters */ -+ dwc_otg_core_reset( _core_if ); -+ } -+ } -+ -+ if ((_core_if->hwcfg2.b.hs_phy_type == 2) && -+ (_core_if->hwcfg2.b.fs_phy_type == 1) && -+ (_core_if->core_params->ulpi_fs_ls)) -+ { -+ DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n"); -+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); -+ usbcfg.b.ulpi_fsls = 1; -+ usbcfg.b.ulpi_clk_sus_m = 1; -+ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); -+ } else { -+ DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS=0\n"); -+ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); -+ usbcfg.b.ulpi_fsls = 0; -+ usbcfg.b.ulpi_clk_sus_m = 0; -+ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); -+ } -+ -+ /* Program the GAHBCFG Register.*/ -+ switch (_core_if->hwcfg2.b.architecture){ -+ -+ case DWC_SLAVE_ONLY_ARCH: -+ DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n"); -+ ahbcfg.b.nptxfemplvl_txfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY; -+ ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY; -+ _core_if->dma_enable = 0; -+ break; -+ -+ case DWC_EXT_DMA_ARCH: -+ DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n"); -+ ahbcfg.b.hburstlen = _core_if->core_params->dma_burst_size; -+ _core_if->dma_enable = (_core_if->core_params->dma_enable != 0); -+ break; -+ -+ case DWC_INT_DMA_ARCH: -+ DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n"); -+ //ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR; -+ ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR4; -+ _core_if->dma_enable = (_core_if->core_params->dma_enable != 0); -+ break; -+ } -+ ahbcfg.b.dmaenable = _core_if->dma_enable; -+ dwc_write_reg32(&global_regs->gahbcfg, ahbcfg.d32); -+ _core_if->en_multiple_tx_fifo = _core_if->hwcfg4.b.ded_fifo_en; -+ -+ /* -+ * Program the GUSBCFG register. -+ */ -+ usbcfg.d32 = dwc_read_reg32( &global_regs->gusbcfg ); -+ -+ switch (_core_if->hwcfg2.b.op_mode) { -+ case DWC_MODE_HNP_SRP_CAPABLE: -+ usbcfg.b.hnpcap = (_core_if->core_params->otg_cap == -+ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE); -+ usbcfg.b.srpcap = (_core_if->core_params->otg_cap != -+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); -+ break; -+ -+ case DWC_MODE_SRP_ONLY_CAPABLE: -+ usbcfg.b.hnpcap = 0; -+ usbcfg.b.srpcap = (_core_if->core_params->otg_cap != -+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); -+ break; -+ -+ case DWC_MODE_NO_HNP_SRP_CAPABLE: -+ usbcfg.b.hnpcap = 0; -+ usbcfg.b.srpcap = 0; -+ break; -+ -+ case DWC_MODE_SRP_CAPABLE_DEVICE: -+ usbcfg.b.hnpcap = 0; -+ usbcfg.b.srpcap = (_core_if->core_params->otg_cap != -+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); -+ break; -+ -+ case DWC_MODE_NO_SRP_CAPABLE_DEVICE: -+ usbcfg.b.hnpcap = 0; -+ usbcfg.b.srpcap = 0; -+ break; -+ -+ case DWC_MODE_SRP_CAPABLE_HOST: -+ usbcfg.b.hnpcap = 0; -+ usbcfg.b.srpcap = (_core_if->core_params->otg_cap != -+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); -+ break; -+ -+ case DWC_MODE_NO_SRP_CAPABLE_HOST: -+ usbcfg.b.hnpcap = 0; -+ usbcfg.b.srpcap = 0; -+ break; -+ } -+ -+ dwc_write_reg32( &global_regs->gusbcfg, usbcfg.d32); -+ -+ /* Enable common interrupts */ -+ dwc_otg_enable_common_interrupts( _core_if ); -+ -+ /* Do device or host intialization based on mode during PCD -+ * and HCD initialization */ -+ if (dwc_otg_is_host_mode( _core_if )) { -+ DWC_DEBUGPL(DBG_ANY, "Host Mode\n" ); -+ _core_if->op_state = A_HOST; -+ } else { -+ DWC_DEBUGPL(DBG_ANY, "Device Mode\n" ); -+ _core_if->op_state = B_PERIPHERAL; -+#ifdef DWC_DEVICE_ONLY -+ dwc_otg_core_dev_init( _core_if ); -+#endif -+ } -+} -+ -+ -+/** -+ * This function enables the Device mode interrupts. -+ * -+ * @param _core_if Programming view of DWC_otg controller -+ */ -+void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if) -+{ -+ gintmsk_data_t intr_mask = { .d32 = 0}; -+ dwc_otg_core_global_regs_t * global_regs = _core_if->core_global_regs; -+ -+ DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__); -+ -+ /* Disable all interrupts. */ -+ dwc_write_reg32( &global_regs->gintmsk, 0); -+ -+ /* Clear any pending interrupts */ -+ dwc_write_reg32( &global_regs->gintsts, 0xFFFFFFFF); -+ -+ /* Enable the common interrupts */ -+ dwc_otg_enable_common_interrupts( _core_if ); -+ -+ /* Enable interrupts */ -+ intr_mask.b.usbreset = 1; -+ intr_mask.b.enumdone = 1; -+ //intr_mask.b.epmismatch = 1; -+ intr_mask.b.inepintr = 1; -+ intr_mask.b.outepintr = 1; -+ intr_mask.b.erlysuspend = 1; -+ if (_core_if->en_multiple_tx_fifo == 0) { -+ intr_mask.b.epmismatch = 1; -+ } -+ -+ /** @todo NGS: Should this be a module parameter? */ -+ intr_mask.b.isooutdrop = 1; -+ intr_mask.b.eopframe = 1; -+ intr_mask.b.incomplisoin = 1; -+ intr_mask.b.incomplisoout = 1; -+ -+ dwc_modify_reg32( &global_regs->gintmsk, intr_mask.d32, intr_mask.d32); -+ -+ DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, -+ dwc_read_reg32( &global_regs->gintmsk)); -+} -+ -+/** -+ * This function initializes the DWC_otg controller registers for -+ * device mode. -+ * -+ * @param _core_if Programming view of DWC_otg controller -+ * -+ */ -+void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if) -+{ -+ dwc_otg_core_global_regs_t *global_regs = -+ _core_if->core_global_regs; -+ dwc_otg_dev_if_t *dev_if = _core_if->dev_if; -+ dwc_otg_core_params_t *params = _core_if->core_params; -+ dcfg_data_t dcfg = {.d32 = 0}; -+ grstctl_t resetctl = { .d32=0 }; -+ int i; -+ uint32_t rx_fifo_size; -+ fifosize_data_t nptxfifosize; -+ fifosize_data_t txfifosize; -+ dthrctl_data_t dthrctl; -+ -+ fifosize_data_t ptxfifosize; -+ -+ /* Restart the Phy Clock */ -+ dwc_write_reg32(_core_if->pcgcctl, 0); -+ -+ /* Device configuration register */ -+ init_devspd(_core_if); -+ dcfg.d32 = dwc_read_reg32( &dev_if->dev_global_regs->dcfg); -+ dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80; -+ dwc_write_reg32( &dev_if->dev_global_regs->dcfg, dcfg.d32 ); -+ -+ /* Configure data FIFO sizes */ -+ if ( _core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo ) { -+ -+ DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", _core_if->total_fifo_size); -+ DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", params->dev_rx_fifo_size); -+ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", params->dev_nperio_tx_fifo_size); -+ -+ /* Rx FIFO */ -+ DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n", -+ dwc_read_reg32(&global_regs->grxfsiz)); -+ rx_fifo_size = params->dev_rx_fifo_size; -+ dwc_write_reg32( &global_regs->grxfsiz, rx_fifo_size ); -+ DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n", -+ dwc_read_reg32(&global_regs->grxfsiz)); -+ -+ /** Set Periodic Tx FIFO Mask all bits 0 */ -+ _core_if->p_tx_msk = 0; -+ -+ /** Set Tx FIFO Mask all bits 0 */ -+ _core_if->tx_msk = 0; -+ if (_core_if->en_multiple_tx_fifo == 0) { -+ /* Non-periodic Tx FIFO */ -+ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", -+ dwc_read_reg32(&global_regs->gnptxfsiz)); -+ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; -+ nptxfifosize.b.startaddr = params->dev_rx_fifo_size; -+ dwc_write_reg32( &global_regs->gnptxfsiz, nptxfifosize.d32 ); -+ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", -+ dwc_read_reg32(&global_regs->gnptxfsiz)); -+ -+ -+ /**@todo NGS: Fix Periodic FIFO Sizing! */ -+ /* -+ * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15. -+ * Indexes of the FIFO size module parameters in the -+ * dev_perio_tx_fifo_size array and the FIFO size registers in -+ * the dptxfsiz array run from 0 to 14. -+ */ -+ /** @todo Finish debug of this */ -+ ptxfifosize.b.startaddr = -+ nptxfifosize.b.startaddr + nptxfifosize.b.depth; -+ for (i = 0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep;i++) { -+ ptxfifosize.b.depth = params->dev_perio_tx_fifo_size[i]; -+ DWC_DEBUGPL(DBG_CIL,"initial dptxfsiz_dieptxf[%d]=%08x\n", -+ i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i])); -+ dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i],ptxfifosize.d32); -+ DWC_DEBUGPL(DBG_CIL,"new dptxfsiz_dieptxf[%d]=%08x\n", -+ i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i])); -+ ptxfifosize.b.startaddr += ptxfifosize.b.depth; -+ } -+ } else { -+ -+ /* -+ * Tx FIFOs These FIFOs are numbered from 1 to 15. -+ * Indexes of the FIFO size module parameters in the -+ * dev_tx_fifo_size array and the FIFO size registers in -+ * the dptxfsiz_dieptxf array run from 0 to 14. -+ */ -+ -+ /* Non-periodic Tx FIFO */ -+ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", -+ dwc_read_reg32(&global_regs->gnptxfsiz)); -+ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; -+ nptxfifosize.b.startaddr = params->dev_rx_fifo_size; -+ dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32); -+ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", -+ dwc_read_reg32(&global_regs->gnptxfsiz)); -+ txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; -+ for (i = 1;i < _core_if->hwcfg4.b.num_dev_perio_in_ep;i++) { -+ txfifosize.b.depth = params->dev_tx_fifo_size[i]; -+ DWC_DEBUGPL(DBG_CIL,"initial dptxfsiz_dieptxf[%d]=%08x\n", -+ i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i])); -+ dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i - 1],txfifosize.d32); -+ DWC_DEBUGPL(DBG_CIL,"new dptxfsiz_dieptxf[%d]=%08x\n", -+ i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i-1])); -+ txfifosize.b.startaddr += txfifosize.b.depth; -+ } -+ } -+ } -+ /* Flush the FIFOs */ -+ dwc_otg_flush_tx_fifo(_core_if, 0x10); /* all Tx FIFOs */ -+ dwc_otg_flush_rx_fifo(_core_if); -+ -+ /* Flush the Learning Queue. */ -+ resetctl.b.intknqflsh = 1; -+ dwc_write_reg32( &_core_if->core_global_regs->grstctl, resetctl.d32); -+ -+ /* Clear all pending Device Interrupts */ -+ dwc_write_reg32( &dev_if->dev_global_regs->diepmsk, 0 ); -+ dwc_write_reg32( &dev_if->dev_global_regs->doepmsk, 0 ); -+ dwc_write_reg32( &dev_if->dev_global_regs->daint, 0xFFFFFFFF ); -+ dwc_write_reg32( &dev_if->dev_global_regs->daintmsk, 0 ); -+ -+ for (i = 0; i <= dev_if->num_in_eps; i++) { -+ depctl_data_t depctl; -+ depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl); -+ if (depctl.b.epena) { -+ depctl.d32 = 0; -+ depctl.b.epdis = 1; -+ depctl.b.snak = 1; -+ } else { -+ depctl.d32 = 0; -+ } -+ dwc_write_reg32( &dev_if->in_ep_regs[i]->diepctl, depctl.d32); -+ -+ dwc_write_reg32(&dev_if->in_ep_regs[i]->dieptsiz, 0); -+ dwc_write_reg32(&dev_if->in_ep_regs[i]->diepdma, 0); -+ dwc_write_reg32(&dev_if->in_ep_regs[i]->diepint, 0xFF); -+ } -+ for (i = 0; i <= dev_if->num_out_eps; i++) { -+ depctl_data_t depctl; -+ depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl); -+ if (depctl.b.epena) { -+ depctl.d32 = 0; -+ depctl.b.epdis = 1; -+ depctl.b.snak = 1; -+ } else { -+ depctl.d32 = 0; -+ } -+ dwc_write_reg32( &dev_if->out_ep_regs[i]->doepctl, depctl.d32); -+ -+ //dwc_write_reg32( &dev_if->in_ep_regs[i]->dieptsiz, 0); -+ dwc_write_reg32( &dev_if->out_ep_regs[i]->doeptsiz, 0); -+ //dwc_write_reg32( &dev_if->in_ep_regs[i]->diepdma, 0); -+ dwc_write_reg32( &dev_if->out_ep_regs[i]->doepdma, 0); -+ //dwc_write_reg32( &dev_if->in_ep_regs[i]->diepint, 0xFF); -+ dwc_write_reg32( &dev_if->out_ep_regs[i]->doepint, 0xFF); -+ } -+ -+ if (_core_if->en_multiple_tx_fifo && _core_if->dma_enable) { -+ dev_if->non_iso_tx_thr_en = _core_if->core_params->thr_ctl & 0x1; -+ dev_if->iso_tx_thr_en = (_core_if->core_params->thr_ctl >> 1) & 0x1; -+ dev_if->rx_thr_en = (_core_if->core_params->thr_ctl >> 2) & 0x1; -+ dev_if->rx_thr_length = _core_if->core_params->rx_thr_length; -+ dev_if->tx_thr_length = _core_if->core_params->tx_thr_length; -+ dthrctl.d32 = 0; -+ dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en; -+ dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en; -+ dthrctl.b.tx_thr_len = dev_if->tx_thr_length; -+ dthrctl.b.rx_thr_en = dev_if->rx_thr_en; -+ dthrctl.b.rx_thr_len = dev_if->rx_thr_length; -+ dwc_write_reg32(&dev_if->dev_global_regs->dtknqr3_dthrctl,dthrctl.d32); -+ DWC_DEBUGPL(DBG_CIL, "Non ISO Tx Thr - %d\nISO Tx Thr - %d\n" -+ "Rx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n", -+ dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en, -+ dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len, -+ dthrctl.b.rx_thr_len); -+ } -+ dwc_otg_enable_device_interrupts( _core_if ); -+ { -+ diepmsk_data_t msk = {.d32 = 0}; -+ msk.b.txfifoundrn = 1; -+ dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk, msk.d32,msk.d32); -+} -+} -+ -+/** -+ * This function enables the Host mode interrupts. -+ * -+ * @param _core_if Programming view of DWC_otg controller -+ */ -+void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if) -+{ -+ dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs; -+ gintmsk_data_t intr_mask = {.d32 = 0}; -+ -+ DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__); -+ -+ /* Disable all interrupts. */ -+ dwc_write_reg32(&global_regs->gintmsk, 0); -+ -+ /* Clear any pending interrupts. */ -+ dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF); -+ -+ /* Enable the common interrupts */ -+ dwc_otg_enable_common_interrupts(_core_if); -+ -+ /* -+ * Enable host mode interrupts without disturbing common -+ * interrupts. -+ */ -+ intr_mask.b.sofintr = 1; -+ intr_mask.b.portintr = 1; -+ intr_mask.b.hcintr = 1; -+ -+ //dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); -+ //dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32); -+ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); -+} -+ -+/** -+ * This function disables the Host Mode interrupts. -+ * -+ * @param _core_if Programming view of DWC_otg controller -+ */ -+void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if) -+{ -+ dwc_otg_core_global_regs_t *global_regs = -+ _core_if->core_global_regs; -+ gintmsk_data_t intr_mask = {.d32 = 0}; -+ -+ DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__); -+ -+ /* -+ * Disable host mode interrupts without disturbing common -+ * interrupts. -+ */ -+ intr_mask.b.sofintr = 1; -+ intr_mask.b.portintr = 1; -+ intr_mask.b.hcintr = 1; -+ intr_mask.b.ptxfempty = 1; -+ intr_mask.b.nptxfempty = 1; -+ -+ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0); -+} -+ -+#if 0 -+/* currently not used, keep it here as if needed later */ -+static int phy_read(dwc_otg_core_if_t * _core_if, int addr) -+{ -+ u32 val; -+ int timeout = 10; -+ -+ dwc_write_reg32(&_core_if->core_global_regs->gpvndctl, -+ 0x02000000 | (addr << 16)); -+ val = dwc_read_reg32(&_core_if->core_global_regs->gpvndctl); -+ while (((val & 0x08000000) == 0) && (timeout--)) { -+ udelay(1000); -+ val = dwc_read_reg32(&_core_if->core_global_regs->gpvndctl); -+ } -+ val = dwc_read_reg32(&_core_if->core_global_regs->gpvndctl); -+ printk("%s: addr=%02x regval=%02x\n", __func__, addr, val & 0x000000ff); -+ -+ return 0; -+} -+#endif -+ -+/** -+ * This function initializes the DWC_otg controller registers for -+ * host mode. -+ * -+ * This function flushes the Tx and Rx FIFOs and it flushes any entries in the -+ * request queues. Host channels are reset to ensure that they are ready for -+ * performing transfers. -+ * -+ * @param _core_if Programming view of DWC_otg controller -+ * -+ */ -+void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if) -+{ -+ dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs; -+ dwc_otg_host_if_t *host_if = _core_if->host_if; -+ dwc_otg_core_params_t *params = _core_if->core_params; -+ hprt0_data_t hprt0 = {.d32 = 0}; -+ fifosize_data_t nptxfifosize; -+ fifosize_data_t ptxfifosize; -+ int i; -+ hcchar_data_t hcchar; -+ hcfg_data_t hcfg; -+ dwc_otg_hc_regs_t *hc_regs; -+ int num_channels; -+ gotgctl_data_t gotgctl = {.d32 = 0}; -+ -+ DWC_DEBUGPL(DBG_CILV,"%s(%p)\n", __func__, _core_if); -+ -+ /* Restart the Phy Clock */ -+ dwc_write_reg32(_core_if->pcgcctl, 0); -+ -+ /* Initialize Host Configuration Register */ -+ init_fslspclksel(_core_if); -+ if (_core_if->core_params->speed == DWC_SPEED_PARAM_FULL) { -+ hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg); -+ hcfg.b.fslssupp = 1; -+ dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32); -+ } -+ -+ /* Configure data FIFO sizes */ -+ if (_core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { -+ DWC_DEBUGPL(DBG_CIL,"Total FIFO Size=%d\n", _core_if->total_fifo_size); -+ DWC_DEBUGPL(DBG_CIL,"Rx FIFO Size=%d\n", params->host_rx_fifo_size); -+ DWC_DEBUGPL(DBG_CIL,"NP Tx FIFO Size=%d\n", params->host_nperio_tx_fifo_size); -+ DWC_DEBUGPL(DBG_CIL,"P Tx FIFO Size=%d\n", params->host_perio_tx_fifo_size); -+ -+ /* Rx FIFO */ -+ DWC_DEBUGPL(DBG_CIL,"initial grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz)); -+ dwc_write_reg32(&global_regs->grxfsiz, params->host_rx_fifo_size); -+ DWC_DEBUGPL(DBG_CIL,"new grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz)); -+ -+ /* Non-periodic Tx FIFO */ -+ DWC_DEBUGPL(DBG_CIL,"initial gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz)); -+ nptxfifosize.b.depth = params->host_nperio_tx_fifo_size; -+ nptxfifosize.b.startaddr = params->host_rx_fifo_size; -+ dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32); -+ DWC_DEBUGPL(DBG_CIL,"new gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz)); -+ -+ /* Periodic Tx FIFO */ -+ DWC_DEBUGPL(DBG_CIL,"initial hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz)); -+ ptxfifosize.b.depth = params->host_perio_tx_fifo_size; -+ ptxfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; -+ dwc_write_reg32(&global_regs->hptxfsiz, ptxfifosize.d32); -+ DWC_DEBUGPL(DBG_CIL,"new hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz)); -+ } -+ -+ /* Clear Host Set HNP Enable in the OTG Control Register */ -+ gotgctl.b.hstsethnpen = 1; -+ dwc_modify_reg32( &global_regs->gotgctl, gotgctl.d32, 0); -+ -+ /* Make sure the FIFOs are flushed. */ -+ dwc_otg_flush_tx_fifo(_core_if, 0x10 /* all Tx FIFOs */); -+ dwc_otg_flush_rx_fifo(_core_if); -+ -+ /* Flush out any leftover queued requests. */ -+ num_channels = _core_if->core_params->host_channels; -+ for (i = 0; i < num_channels; i++) { -+ hc_regs = _core_if->host_if->hc_regs[i]; -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ hcchar.b.chen = 0; -+ hcchar.b.chdis = 1; -+ hcchar.b.epdir = 0; -+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); -+ } -+ -+ /* Halt all channels to put them into a known state. */ -+ for (i = 0; i < num_channels; i++) { -+ int count = 0; -+ hc_regs = _core_if->host_if->hc_regs[i]; -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ hcchar.b.chen = 1; -+ hcchar.b.chdis = 1; -+ hcchar.b.epdir = 0; -+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); -+ DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i); -+ do { -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ if (++count > 200) { -+ DWC_ERROR("%s: Unable to clear halt on channel %d\n", -+ __func__, i); -+ break; -+ } -+ udelay(100); -+ } while (hcchar.b.chen); -+ } -+ -+ /* Turn on the vbus power. */ -+ DWC_PRINT("Init: Port Power? op_state=%d\n", _core_if->op_state); -+ if (_core_if->op_state == A_HOST){ -+ hprt0.d32 = dwc_otg_read_hprt0(_core_if); -+ DWC_PRINT("Init: Power Port (%d)\n", hprt0.b.prtpwr); -+ if (hprt0.b.prtpwr == 0 ) { -+ hprt0.b.prtpwr = 1; -+ dwc_write_reg32(host_if->hprt0, hprt0.d32); -+ } -+ } -+ -+ dwc_otg_enable_host_interrupts( _core_if ); -+} -+ -+/** -+ * Prepares a host channel for transferring packets to/from a specific -+ * endpoint. The HCCHARn register is set up with the characteristics specified -+ * in _hc. Host channel interrupts that may need to be serviced while this -+ * transfer is in progress are enabled. -+ * -+ * @param _core_if Programming view of DWC_otg controller -+ * @param _hc Information needed to initialize the host channel -+ */ -+void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) -+{ -+ uint32_t intr_enable; -+ hcintmsk_data_t hc_intr_mask; -+ gintmsk_data_t gintmsk = {.d32 = 0}; -+ hcchar_data_t hcchar; -+ hcsplt_data_t hcsplt; -+ -+ uint8_t hc_num = _hc->hc_num; -+ dwc_otg_host_if_t *host_if = _core_if->host_if; -+ dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num]; -+ -+ /* Clear old interrupt conditions for this host channel. */ -+ hc_intr_mask.d32 = 0xFFFFFFFF; -+ hc_intr_mask.b.reserved = 0; -+ dwc_write_reg32(&hc_regs->hcint, hc_intr_mask.d32); -+ -+ /* Enable channel interrupts required for this transfer. */ -+ hc_intr_mask.d32 = 0; -+ hc_intr_mask.b.chhltd = 1; -+ if (_core_if->dma_enable) { -+ hc_intr_mask.b.ahberr = 1; -+ if (_hc->error_state && !_hc->do_split && -+ _hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { -+ hc_intr_mask.b.ack = 1; -+ if (_hc->ep_is_in) { -+ hc_intr_mask.b.datatglerr = 1; -+ if (_hc->ep_type != DWC_OTG_EP_TYPE_INTR) { -+ hc_intr_mask.b.nak = 1; -+ } -+ } -+ } -+ } else { -+ switch (_hc->ep_type) { -+ case DWC_OTG_EP_TYPE_CONTROL: -+ case DWC_OTG_EP_TYPE_BULK: -+ hc_intr_mask.b.xfercompl = 1; -+ hc_intr_mask.b.stall = 1; -+ hc_intr_mask.b.xacterr = 1; -+ hc_intr_mask.b.datatglerr = 1; -+ if (_hc->ep_is_in) { -+ hc_intr_mask.b.bblerr = 1; -+ } else { -+ hc_intr_mask.b.nak = 1; -+ hc_intr_mask.b.nyet = 1; -+ if (_hc->do_ping) { -+ hc_intr_mask.b.ack = 1; -+ } -+ } -+ -+ if (_hc->do_split) { -+ hc_intr_mask.b.nak = 1; -+ if (_hc->complete_split) { -+ hc_intr_mask.b.nyet = 1; -+ } -+ else { -+ hc_intr_mask.b.ack = 1; -+ } -+ } -+ -+ if (_hc->error_state) { -+ hc_intr_mask.b.ack = 1; -+ } -+ break; -+ case DWC_OTG_EP_TYPE_INTR: -+ hc_intr_mask.b.xfercompl = 1; -+ hc_intr_mask.b.nak = 1; -+ hc_intr_mask.b.stall = 1; -+ hc_intr_mask.b.xacterr = 1; -+ hc_intr_mask.b.datatglerr = 1; -+ hc_intr_mask.b.frmovrun = 1; -+ -+ if (_hc->ep_is_in) { -+ hc_intr_mask.b.bblerr = 1; -+ } -+ if (_hc->error_state) { -+ hc_intr_mask.b.ack = 1; -+ } -+ if (_hc->do_split) { -+ if (_hc->complete_split) { -+ hc_intr_mask.b.nyet = 1; -+ } -+ else { -+ hc_intr_mask.b.ack = 1; -+ } -+ } -+ break; -+ case DWC_OTG_EP_TYPE_ISOC: -+ hc_intr_mask.b.xfercompl = 1; -+ hc_intr_mask.b.frmovrun = 1; -+ hc_intr_mask.b.ack = 1; -+ -+ if (_hc->ep_is_in) { -+ hc_intr_mask.b.xacterr = 1; -+ hc_intr_mask.b.bblerr = 1; -+ } -+ break; -+ } -+ } -+ dwc_write_reg32(&hc_regs->hcintmsk, hc_intr_mask.d32); -+ -+ /* Enable the top level host channel interrupt. */ -+ intr_enable = (1 << hc_num); -+ dwc_modify_reg32(&host_if->host_global_regs->haintmsk, 0, intr_enable); -+ -+ /* Make sure host channel interrupts are enabled. */ -+ gintmsk.b.hcintr = 1; -+ dwc_modify_reg32(&_core_if->core_global_regs->gintmsk, 0, gintmsk.d32); -+ -+ /* -+ * Program the HCCHARn register with the endpoint characteristics for -+ * the current transfer. -+ */ -+ hcchar.d32 = 0; -+ hcchar.b.devaddr = _hc->dev_addr; -+ hcchar.b.epnum = _hc->ep_num; -+ hcchar.b.epdir = _hc->ep_is_in; -+ hcchar.b.lspddev = (_hc->speed == DWC_OTG_EP_SPEED_LOW); -+ hcchar.b.eptype = _hc->ep_type; -+ hcchar.b.mps = _hc->max_packet; -+ -+ dwc_write_reg32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32); -+ -+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num); -+ DWC_DEBUGPL(DBG_HCDV, " Dev Addr: %d\n", hcchar.b.devaddr); -+ DWC_DEBUGPL(DBG_HCDV, " Ep Num: %d\n", hcchar.b.epnum); -+ DWC_DEBUGPL(DBG_HCDV, " Is In: %d\n", hcchar.b.epdir); -+ DWC_DEBUGPL(DBG_HCDV, " Is Low Speed: %d\n", hcchar.b.lspddev); -+ DWC_DEBUGPL(DBG_HCDV, " Ep Type: %d\n", hcchar.b.eptype); -+ DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps); -+ DWC_DEBUGPL(DBG_HCDV, " Multi Cnt: %d\n", hcchar.b.multicnt); -+ -+ /* -+ * Program the HCSPLIT register for SPLITs -+ */ -+ hcsplt.d32 = 0; -+ if (_hc->do_split) { -+ DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n", _hc->hc_num, -+ _hc->complete_split ? "CSPLIT" : "SSPLIT"); -+ hcsplt.b.compsplt = _hc->complete_split; -+ hcsplt.b.xactpos = _hc->xact_pos; -+ hcsplt.b.hubaddr = _hc->hub_addr; -+ hcsplt.b.prtaddr = _hc->port_addr; -+ DWC_DEBUGPL(DBG_HCDV, " comp split %d\n", _hc->complete_split); -+ DWC_DEBUGPL(DBG_HCDV, " xact pos %d\n", _hc->xact_pos); -+ DWC_DEBUGPL(DBG_HCDV, " hub addr %d\n", _hc->hub_addr); -+ DWC_DEBUGPL(DBG_HCDV, " port addr %d\n", _hc->port_addr); -+ DWC_DEBUGPL(DBG_HCDV, " is_in %d\n", _hc->ep_is_in); -+ DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps); -+ DWC_DEBUGPL(DBG_HCDV, " xferlen: %d\n", _hc->xfer_len); -+ } -+ dwc_write_reg32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32); -+ -+} -+ -+/** -+ * Attempts to halt a host channel. This function should only be called in -+ * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under -+ * normal circumstances in DMA mode, the controller halts the channel when the -+ * transfer is complete or a condition occurs that requires application -+ * intervention. -+ * -+ * In slave mode, checks for a free request queue entry, then sets the Channel -+ * Enable and Channel Disable bits of the Host Channel Characteristics -+ * register of the specified channel to intiate the halt. If there is no free -+ * request queue entry, sets only the Channel Disable bit of the HCCHARn -+ * register to flush requests for this channel. In the latter case, sets a -+ * flag to indicate that the host channel needs to be halted when a request -+ * queue slot is open. -+ * -+ * In DMA mode, always sets the Channel Enable and Channel Disable bits of the -+ * HCCHARn register. The controller ensures there is space in the request -+ * queue before submitting the halt request. -+ * -+ * Some time may elapse before the core flushes any posted requests for this -+ * host channel and halts. The Channel Halted interrupt handler completes the -+ * deactivation of the host channel. -+ * -+ * @param _core_if Controller register interface. -+ * @param _hc Host channel to halt. -+ * @param _halt_status Reason for halting the channel. -+ */ -+void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if, -+ dwc_hc_t *_hc, -+ dwc_otg_halt_status_e _halt_status) -+{ -+ gnptxsts_data_t nptxsts; -+ hptxsts_data_t hptxsts; -+ hcchar_data_t hcchar; -+ dwc_otg_hc_regs_t *hc_regs; -+ dwc_otg_core_global_regs_t *global_regs; -+ dwc_otg_host_global_regs_t *host_global_regs; -+ -+ hc_regs = _core_if->host_if->hc_regs[_hc->hc_num]; -+ global_regs = _core_if->core_global_regs; -+ host_global_regs = _core_if->host_if->host_global_regs; -+ -+ WARN_ON(_halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS); -+ -+ if (_halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE || -+ _halt_status == DWC_OTG_HC_XFER_AHB_ERR) { -+ /* -+ * Disable all channel interrupts except Ch Halted. The QTD -+ * and QH state associated with this transfer has been cleared -+ * (in the case of URB_DEQUEUE), so the channel needs to be -+ * shut down carefully to prevent crashes. -+ */ -+ hcintmsk_data_t hcintmsk; -+ hcintmsk.d32 = 0; -+ hcintmsk.b.chhltd = 1; -+ dwc_write_reg32(&hc_regs->hcintmsk, hcintmsk.d32); -+ -+ /* -+ * Make sure no other interrupts besides halt are currently -+ * pending. Handling another interrupt could cause a crash due -+ * to the QTD and QH state. -+ */ -+ dwc_write_reg32(&hc_regs->hcint, ~hcintmsk.d32); -+ -+ /* -+ * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR -+ * even if the channel was already halted for some other -+ * reason. -+ */ -+ _hc->halt_status = _halt_status; -+ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ if (hcchar.b.chen == 0) { -+ /* -+ * The channel is either already halted or it hasn't -+ * started yet. In DMA mode, the transfer may halt if -+ * it finishes normally or a condition occurs that -+ * requires driver intervention. Don't want to halt -+ * the channel again. In either Slave or DMA mode, -+ * it's possible that the transfer has been assigned -+ * to a channel, but not started yet when an URB is -+ * dequeued. Don't want to halt a channel that hasn't -+ * started yet. -+ */ -+ return; -+ } -+ } -+ -+ if (_hc->halt_pending) { -+ /* -+ * A halt has already been issued for this channel. This might -+ * happen when a transfer is aborted by a higher level in -+ * the stack. -+ */ -+#ifdef DEBUG -+ DWC_PRINT("*** %s: Channel %d, _hc->halt_pending already set ***\n", -+ __func__, _hc->hc_num); -+ -+/* dwc_otg_dump_global_registers(_core_if); */ -+/* dwc_otg_dump_host_registers(_core_if); */ -+#endif -+ return; -+ } -+ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ hcchar.b.chen = 1; -+ hcchar.b.chdis = 1; -+ -+ if (!_core_if->dma_enable) { -+ /* Check for space in the request queue to issue the halt. */ -+ if (_hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || -+ _hc->ep_type == DWC_OTG_EP_TYPE_BULK) { -+ nptxsts.d32 = dwc_read_reg32(&global_regs->gnptxsts); -+ if (nptxsts.b.nptxqspcavail == 0) { -+ hcchar.b.chen = 0; -+ } -+ } else { -+ hptxsts.d32 = dwc_read_reg32(&host_global_regs->hptxsts); -+ if ((hptxsts.b.ptxqspcavail == 0) || (_core_if->queuing_high_bandwidth)) { -+ hcchar.b.chen = 0; -+ } -+ } -+ } -+ -+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); -+ -+ _hc->halt_status = _halt_status; -+ -+ if (hcchar.b.chen) { -+ _hc->halt_pending = 1; -+ _hc->halt_on_queue = 0; -+ } else { -+ _hc->halt_on_queue = 1; -+ } -+ -+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num); -+ DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32); -+ DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", _hc->halt_pending); -+ DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", _hc->halt_on_queue); -+ DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", _hc->halt_status); -+ -+ return; -+} -+ -+/** -+ * Clears the transfer state for a host channel. This function is normally -+ * called after a transfer is done and the host channel is being released. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ * @param _hc Identifies the host channel to clean up. -+ */ -+void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) -+{ -+ dwc_otg_hc_regs_t *hc_regs; -+ -+ _hc->xfer_started = 0; -+ -+ /* -+ * Clear channel interrupt enables and any unhandled channel interrupt -+ * conditions. -+ */ -+ hc_regs = _core_if->host_if->hc_regs[_hc->hc_num]; -+ dwc_write_reg32(&hc_regs->hcintmsk, 0); -+ dwc_write_reg32(&hc_regs->hcint, 0xFFFFFFFF); -+ -+#ifdef DEBUG -+ del_timer(&_core_if->hc_xfer_timer[_hc->hc_num]); -+ { -+ hcchar_data_t hcchar; -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ if (hcchar.b.chdis) { -+ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", -+ __func__, _hc->hc_num, hcchar.d32); -+ } -+ } -+#endif -+} -+ -+/** -+ * Sets the channel property that indicates in which frame a periodic transfer -+ * should occur. This is always set to the _next_ frame. This function has no -+ * effect on non-periodic transfers. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ * @param _hc Identifies the host channel to set up and its properties. -+ * @param _hcchar Current value of the HCCHAR register for the specified host -+ * channel. -+ */ -+static inline void hc_set_even_odd_frame(dwc_otg_core_if_t *_core_if, -+ dwc_hc_t *_hc, -+ hcchar_data_t *_hcchar) -+{ -+ if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR || -+ _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { -+ hfnum_data_t hfnum; -+ hfnum.d32 = dwc_read_reg32(&_core_if->host_if->host_global_regs->hfnum); -+ /* 1 if _next_ frame is odd, 0 if it's even */ -+ _hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1; -+#ifdef DEBUG -+ if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR && _hc->do_split && !_hc->complete_split) { -+ switch (hfnum.b.frnum & 0x7) { -+ case 7: -+ _core_if->hfnum_7_samples++; -+ _core_if->hfnum_7_frrem_accum += hfnum.b.frrem; -+ break; -+ case 0: -+ _core_if->hfnum_0_samples++; -+ _core_if->hfnum_0_frrem_accum += hfnum.b.frrem; -+ break; -+ default: -+ _core_if->hfnum_other_samples++; -+ _core_if->hfnum_other_frrem_accum += hfnum.b.frrem; -+ break; -+ } -+ } -+#endif -+ } -+} -+ -+#ifdef DEBUG -+static void hc_xfer_timeout(unsigned long _ptr) -+{ -+ hc_xfer_info_t *xfer_info = (hc_xfer_info_t *)_ptr; -+ int hc_num = xfer_info->hc->hc_num; -+ DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num); -+ DWC_WARN(" start_hcchar_val 0x%08x\n", xfer_info->core_if->start_hcchar_val[hc_num]); -+} -+#endif -+ -+/* -+ * This function does the setup for a data transfer for a host channel and -+ * starts the transfer. May be called in either Slave mode or DMA mode. In -+ * Slave mode, the caller must ensure that there is sufficient space in the -+ * request queue and Tx Data FIFO. -+ * -+ * For an OUT transfer in Slave mode, it loads a data packet into the -+ * appropriate FIFO. If necessary, additional data packets will be loaded in -+ * the Host ISR. -+ * -+ * For an IN transfer in Slave mode, a data packet is requested. The data -+ * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, -+ * additional data packets are requested in the Host ISR. -+ * -+ * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ -+ * register along with a packet count of 1 and the channel is enabled. This -+ * causes a single PING transaction to occur. Other fields in HCTSIZ are -+ * simply set to 0 since no data transfer occurs in this case. -+ * -+ * For a PING transfer in DMA mode, the HCTSIZ register is initialized with -+ * all the information required to perform the subsequent data transfer. In -+ * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the -+ * controller performs the entire PING protocol, then starts the data -+ * transfer. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ * @param _hc Information needed to initialize the host channel. The xfer_len -+ * value may be reduced to accommodate the max widths of the XferSize and -+ * PktCnt fields in the HCTSIZn register. The multi_count value may be changed -+ * to reflect the final xfer_len value. -+ */ -+void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) -+{ -+ hcchar_data_t hcchar; -+ hctsiz_data_t hctsiz; -+ uint16_t num_packets; -+ uint32_t max_hc_xfer_size = _core_if->core_params->max_transfer_size; -+ uint16_t max_hc_pkt_count = _core_if->core_params->max_packet_count; -+ dwc_otg_hc_regs_t *hc_regs = _core_if->host_if->hc_regs[_hc->hc_num]; -+ -+ hctsiz.d32 = 0; -+ -+ if (_hc->do_ping) { -+ if (!_core_if->dma_enable) { -+ dwc_otg_hc_do_ping(_core_if, _hc); -+ _hc->xfer_started = 1; -+ return; -+ } else { -+ hctsiz.b.dopng = 1; -+ } -+ } -+ -+ if (_hc->do_split) { -+ num_packets = 1; -+ -+ if (_hc->complete_split && !_hc->ep_is_in) { -+ /* For CSPLIT OUT Transfer, set the size to 0 so the -+ * core doesn't expect any data written to the FIFO */ -+ _hc->xfer_len = 0; -+ } else if (_hc->ep_is_in || (_hc->xfer_len > _hc->max_packet)) { -+ _hc->xfer_len = _hc->max_packet; -+ } else if (!_hc->ep_is_in && (_hc->xfer_len > 188)) { -+ _hc->xfer_len = 188; -+ } -+ -+ hctsiz.b.xfersize = _hc->xfer_len; -+ } else { -+ /* -+ * Ensure that the transfer length and packet count will fit -+ * in the widths allocated for them in the HCTSIZn register. -+ */ -+ if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR || -+ _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { -+ /* -+ * Make sure the transfer size is no larger than one -+ * (micro)frame's worth of data. (A check was done -+ * when the periodic transfer was accepted to ensure -+ * that a (micro)frame's worth of data can be -+ * programmed into a channel.) -+ */ -+ uint32_t max_periodic_len = _hc->multi_count * _hc->max_packet; -+ if (_hc->xfer_len > max_periodic_len) { -+ _hc->xfer_len = max_periodic_len; -+ } else { -+ } -+ } else if (_hc->xfer_len > max_hc_xfer_size) { -+ /* Make sure that xfer_len is a multiple of max packet size. */ -+ _hc->xfer_len = max_hc_xfer_size - _hc->max_packet + 1; -+ } -+ -+ if (_hc->xfer_len > 0) { -+ num_packets = (_hc->xfer_len + _hc->max_packet - 1) / _hc->max_packet; -+ if (num_packets > max_hc_pkt_count) { -+ num_packets = max_hc_pkt_count; -+ _hc->xfer_len = num_packets * _hc->max_packet; -+ } -+ } else { -+ /* Need 1 packet for transfer length of 0. */ -+ num_packets = 1; -+ } -+ -+ if (_hc->ep_is_in) { -+ /* Always program an integral # of max packets for IN transfers. */ -+ _hc->xfer_len = num_packets * _hc->max_packet; -+ } -+ -+ if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR || -+ _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { -+ /* -+ * Make sure that the multi_count field matches the -+ * actual transfer length. -+ */ -+ _hc->multi_count = num_packets; -+ -+ } -+ -+ if (_hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { -+ /* Set up the initial PID for the transfer. */ -+ if (_hc->speed == DWC_OTG_EP_SPEED_HIGH) { -+ if (_hc->ep_is_in) { -+ if (_hc->multi_count == 1) { -+ _hc->data_pid_start = DWC_OTG_HC_PID_DATA0; -+ } else if (_hc->multi_count == 2) { -+ _hc->data_pid_start = DWC_OTG_HC_PID_DATA1; -+ } else { -+ _hc->data_pid_start = DWC_OTG_HC_PID_DATA2; -+ } -+ } else { -+ if (_hc->multi_count == 1) { -+ _hc->data_pid_start = DWC_OTG_HC_PID_DATA0; -+ } else { -+ _hc->data_pid_start = DWC_OTG_HC_PID_MDATA; -+ } -+ } -+ } else { -+ _hc->data_pid_start = DWC_OTG_HC_PID_DATA0; -+ } -+ } -+ -+ hctsiz.b.xfersize = _hc->xfer_len; -+ } -+ -+ _hc->start_pkt_count = num_packets; -+ hctsiz.b.pktcnt = num_packets; -+ hctsiz.b.pid = _hc->data_pid_start; -+ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); -+ -+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num); -+ DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize); -+ DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt); -+ DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid); -+ -+ if (_core_if->dma_enable) { -+#ifdef DEBUG -+if(((uint32_t)_hc->xfer_buff)%4) -+printk("dwc_otg_hc_start_transfer _hc->xfer_buff not 4 byte alignment\n"); -+#endif -+ dwc_write_reg32(&hc_regs->hcdma, (uint32_t)_hc->xfer_buff); -+ } -+ -+ /* Start the split */ -+ if (_hc->do_split) { -+ hcsplt_data_t hcsplt; -+ hcsplt.d32 = dwc_read_reg32 (&hc_regs->hcsplt); -+ hcsplt.b.spltena = 1; -+ dwc_write_reg32(&hc_regs->hcsplt, hcsplt.d32); -+ } -+ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ hcchar.b.multicnt = _hc->multi_count; -+ hc_set_even_odd_frame(_core_if, _hc, &hcchar); -+#ifdef DEBUG -+ _core_if->start_hcchar_val[_hc->hc_num] = hcchar.d32; -+ if (hcchar.b.chdis) { -+ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", -+ __func__, _hc->hc_num, hcchar.d32); -+ } -+#endif -+ -+ /* Set host channel enable after all other setup is complete. */ -+ hcchar.b.chen = 1; -+ hcchar.b.chdis = 0; -+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); -+ -+ _hc->xfer_started = 1; -+ _hc->requests++; -+ -+ if (!_core_if->dma_enable && !_hc->ep_is_in && _hc->xfer_len > 0) { -+ /* Load OUT packet into the appropriate Tx FIFO. */ -+ dwc_otg_hc_write_packet(_core_if, _hc); -+ } -+ -+#ifdef DEBUG -+ /* Start a timer for this transfer. */ -+ _core_if->hc_xfer_timer[_hc->hc_num].function = hc_xfer_timeout; -+ _core_if->hc_xfer_info[_hc->hc_num].core_if = _core_if; -+ _core_if->hc_xfer_info[_hc->hc_num].hc = _hc; -+ _core_if->hc_xfer_timer[_hc->hc_num].data = (unsigned long)(&_core_if->hc_xfer_info[_hc->hc_num]); -+ _core_if->hc_xfer_timer[_hc->hc_num].expires = jiffies + (HZ*10); -+ add_timer(&_core_if->hc_xfer_timer[_hc->hc_num]); -+#endif -+} -+ -+/** -+ * This function continues a data transfer that was started by previous call -+ * to dwc_otg_hc_start_transfer. The caller must ensure there is -+ * sufficient space in the request queue and Tx Data FIFO. This function -+ * should only be called in Slave mode. In DMA mode, the controller acts -+ * autonomously to complete transfers programmed to a host channel. -+ * -+ * For an OUT transfer, a new data packet is loaded into the appropriate FIFO -+ * if there is any data remaining to be queued. For an IN transfer, another -+ * data packet is always requested. For the SETUP phase of a control transfer, -+ * this function does nothing. -+ * -+ * @return 1 if a new request is queued, 0 if no more requests are required -+ * for this transfer. -+ */ -+int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) -+{ -+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num); -+ -+ if (_hc->do_split) { -+ /* SPLITs always queue just once per channel */ -+ return 0; -+ } else if (_hc->data_pid_start == DWC_OTG_HC_PID_SETUP) { -+ /* SETUPs are queued only once since they can't be NAKed. */ -+ return 0; -+ } else if (_hc->ep_is_in) { -+ /* -+ * Always queue another request for other IN transfers. If -+ * back-to-back INs are issued and NAKs are received for both, -+ * the driver may still be processing the first NAK when the -+ * second NAK is received. When the interrupt handler clears -+ * the NAK interrupt for the first NAK, the second NAK will -+ * not be seen. So we can't depend on the NAK interrupt -+ * handler to requeue a NAKed request. Instead, IN requests -+ * are issued each time this function is called. When the -+ * transfer completes, the extra requests for the channel will -+ * be flushed. -+ */ -+ hcchar_data_t hcchar; -+ dwc_otg_hc_regs_t *hc_regs = _core_if->host_if->hc_regs[_hc->hc_num]; -+ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ hc_set_even_odd_frame(_core_if, _hc, &hcchar); -+ hcchar.b.chen = 1; -+ hcchar.b.chdis = 0; -+ DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n", hcchar.d32); -+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); -+ _hc->requests++; -+ return 1; -+ } else { -+ /* OUT transfers. */ -+ if (_hc->xfer_count < _hc->xfer_len) { -+ if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR || -+ _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { -+ hcchar_data_t hcchar; -+ dwc_otg_hc_regs_t *hc_regs; -+ hc_regs = _core_if->host_if->hc_regs[_hc->hc_num]; -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ hc_set_even_odd_frame(_core_if, _hc, &hcchar); -+ } -+ -+ /* Load OUT packet into the appropriate Tx FIFO. */ -+ dwc_otg_hc_write_packet(_core_if, _hc); -+ _hc->requests++; -+ return 1; -+ } else { -+ return 0; -+ } -+ } -+} -+ -+/** -+ * Starts a PING transfer. This function should only be called in Slave mode. -+ * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled. -+ */ -+void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) -+{ -+ hcchar_data_t hcchar; -+ hctsiz_data_t hctsiz; -+ dwc_otg_hc_regs_t *hc_regs = _core_if->host_if->hc_regs[_hc->hc_num]; -+ -+ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num); -+ -+ hctsiz.d32 = 0; -+ hctsiz.b.dopng = 1; -+ hctsiz.b.pktcnt = 1; -+ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); -+ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ hcchar.b.chen = 1; -+ hcchar.b.chdis = 0; -+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); -+} -+ -+/* -+ * This function writes a packet into the Tx FIFO associated with the Host -+ * Channel. For a channel associated with a non-periodic EP, the non-periodic -+ * Tx FIFO is written. For a channel associated with a periodic EP, the -+ * periodic Tx FIFO is written. This function should only be called in Slave -+ * mode. -+ * -+ * Upon return the xfer_buff and xfer_count fields in _hc are incremented by -+ * then number of bytes written to the Tx FIFO. -+ */ -+void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) -+{ -+ uint32_t i; -+ uint32_t remaining_count; -+ uint32_t byte_count; -+ uint32_t dword_count; -+ -+ uint32_t *data_buff = (uint32_t *)(_hc->xfer_buff); -+ uint32_t *data_fifo = _core_if->data_fifo[_hc->hc_num]; -+ -+ remaining_count = _hc->xfer_len - _hc->xfer_count; -+ if (remaining_count > _hc->max_packet) { -+ byte_count = _hc->max_packet; -+ } else { -+ byte_count = remaining_count; -+ } -+ -+ dword_count = (byte_count + 3) / 4; -+ -+ if ((((unsigned long)data_buff) & 0x3) == 0) { -+ /* xfer_buff is DWORD aligned. */ -+ for (i = 0; i < dword_count; i++, data_buff++) { -+ dwc_write_reg32(data_fifo, *data_buff); -+ } -+ } else { -+ /* xfer_buff is not DWORD aligned. */ -+ for (i = 0; i < dword_count; i++, data_buff++) { -+ dwc_write_reg32(data_fifo, get_unaligned(data_buff)); -+ } -+ } -+ -+ _hc->xfer_count += byte_count; -+ _hc->xfer_buff += byte_count; -+} -+ -+/** -+ * Gets the current USB frame number. This is the frame number from the last -+ * SOF packet. -+ */ -+uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if) -+{ -+ dsts_data_t dsts; -+ dsts.d32 = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->dsts); -+ -+ /* read current frame/microfreme number from DSTS register */ -+ return dsts.b.soffn; -+} -+ -+/** -+ * This function reads a setup packet from the Rx FIFO into the destination -+ * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl) -+ * Interrupt routine when a SETUP packet has been received in Slave mode. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ * @param _dest Destination buffer for packet data. -+ */ -+void dwc_otg_read_setup_packet(dwc_otg_core_if_t *_core_if, uint32_t *_dest) -+{ -+ /* Get the 8 bytes of a setup transaction data */ -+ -+ /* Pop 2 DWORDS off the receive data FIFO into memory */ -+ _dest[0] = dwc_read_reg32(_core_if->data_fifo[0]); -+ _dest[1] = dwc_read_reg32(_core_if->data_fifo[0]); -+ //_dest[0] = dwc_read_datafifo32(_core_if->data_fifo[0]); -+ //_dest[1] = dwc_read_datafifo32(_core_if->data_fifo[0]); -+} -+ -+ -+/** -+ * This function enables EP0 OUT to receive SETUP packets and configures EP0 -+ * IN for transmitting packets. It is normally called when the -+ * "Enumeration Done" interrupt occurs. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ * @param _ep The EP0 data. -+ */ -+void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) -+{ -+ dwc_otg_dev_if_t *dev_if = _core_if->dev_if; -+ dsts_data_t dsts; -+ depctl_data_t diepctl; -+ depctl_data_t doepctl; -+ dctl_data_t dctl ={.d32=0}; -+ -+ /* Read the Device Status and Endpoint 0 Control registers */ -+ dsts.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dsts); -+ diepctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl); -+ doepctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl); -+ -+ /* Set the MPS of the IN EP based on the enumeration speed */ -+ switch (dsts.b.enumspd) { -+ case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: -+ case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: -+ case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ: -+ diepctl.b.mps = DWC_DEP0CTL_MPS_64; -+ break; -+ case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ: -+ diepctl.b.mps = DWC_DEP0CTL_MPS_8; -+ break; -+ } -+ -+ dwc_write_reg32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); -+ -+ /* Enable OUT EP for receive */ -+ doepctl.b.epena = 1; -+ dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32); -+ -+#ifdef VERBOSE -+ DWC_DEBUGPL(DBG_PCDV,"doepctl0=%0x\n", -+ dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl)); -+ DWC_DEBUGPL(DBG_PCDV,"diepctl0=%0x\n", -+ dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl)); -+#endif -+ dctl.b.cgnpinnak = 1; -+ dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); -+ DWC_DEBUGPL(DBG_PCDV,"dctl=%0x\n", -+ dwc_read_reg32(&dev_if->dev_global_regs->dctl)); -+} -+ -+/** -+ * This function activates an EP. The Device EP control register for -+ * the EP is configured as defined in the ep structure. Note: This -+ * function is not used for EP0. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ * @param _ep The EP to activate. -+ */ -+void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) -+{ -+ dwc_otg_dev_if_t *dev_if = _core_if->dev_if; -+ depctl_data_t depctl; -+ volatile uint32_t *addr; -+ daint_data_t daintmsk = {.d32=0}; -+ -+ DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, _ep->num, -+ (_ep->is_in?"IN":"OUT")); -+ -+ /* Read DEPCTLn register */ -+ if (_ep->is_in == 1) { -+ addr = &dev_if->in_ep_regs[_ep->num]->diepctl; -+ daintmsk.ep.in = 1<<_ep->num; -+ } else { -+ addr = &dev_if->out_ep_regs[_ep->num]->doepctl; -+ daintmsk.ep.out = 1<<_ep->num; -+ } -+ -+ /* If the EP is already active don't change the EP Control -+ * register. */ -+ depctl.d32 = dwc_read_reg32(addr); -+ if (!depctl.b.usbactep) { -+ depctl.b.mps = _ep->maxpacket; -+ depctl.b.eptype = _ep->type; -+ depctl.b.txfnum = _ep->tx_fifo_num; -+ -+ if (_ep->type == DWC_OTG_EP_TYPE_ISOC) { -+ depctl.b.setd0pid = 1; // ??? -+ } else { -+ depctl.b.setd0pid = 1; -+ } -+ depctl.b.usbactep = 1; -+ -+ dwc_write_reg32(addr, depctl.d32); -+ DWC_DEBUGPL(DBG_PCDV,"DEPCTL=%08x\n", dwc_read_reg32(addr)); -+ } -+ -+ -+ /* Enable the Interrupt for this EP */ -+ dwc_modify_reg32(&dev_if->dev_global_regs->daintmsk, -+ 0, daintmsk.d32); -+ DWC_DEBUGPL(DBG_PCDV,"DAINTMSK=%0x\n", -+ dwc_read_reg32(&dev_if->dev_global_regs->daintmsk)); -+ _ep->stall_clear_flag = 0; -+ return; -+} -+ -+/** -+ * This function deactivates an EP. This is done by clearing the USB Active -+ * EP bit in the Device EP control register. Note: This function is not used -+ * for EP0. EP0 cannot be deactivated. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ * @param _ep The EP to deactivate. -+ */ -+void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) -+{ -+ depctl_data_t depctl ={.d32 = 0}; -+ volatile uint32_t *addr; -+ daint_data_t daintmsk = {.d32=0}; -+ -+ /* Read DEPCTLn register */ -+ if (_ep->is_in == 1) { -+ addr = &_core_if->dev_if->in_ep_regs[_ep->num]->diepctl; -+ daintmsk.ep.in = 1<<_ep->num; -+ } else { -+ addr = &_core_if->dev_if->out_ep_regs[_ep->num]->doepctl; -+ daintmsk.ep.out = 1<<_ep->num; -+ } -+ -+ depctl.b.usbactep = 0; -+ dwc_write_reg32(addr, depctl.d32); -+ -+ /* Disable the Interrupt for this EP */ -+ dwc_modify_reg32(&_core_if->dev_if->dev_global_regs->daintmsk, -+ daintmsk.d32, 0); -+ -+ return; -+} -+ -+/** -+ * This function does the setup for a data transfer for an EP and -+ * starts the transfer. For an IN transfer, the packets will be -+ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, -+ * the packets are unloaded from the Rx FIFO in the ISR. the ISR. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ * @param _ep The EP to start the transfer on. -+ */ -+void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) -+{ -+ /** @todo Refactor this funciton to check the transfer size -+ * count value does not execed the number bits in the Transfer -+ * count register. */ -+ depctl_data_t depctl; -+ deptsiz_data_t deptsiz; -+ gintmsk_data_t intr_mask = { .d32 = 0}; -+ -+#ifdef CHECK_PACKET_COUNTER_WIDTH -+ const uint32_t MAX_XFER_SIZE = -+ _core_if->core_params->max_transfer_size; -+ const uint32_t MAX_PKT_COUNT = -+ _core_if->core_params->max_packet_count; -+ uint32_t num_packets; -+ uint32_t transfer_len; -+ dwc_otg_dev_out_ep_regs_t *out_regs = -+ _core_if->dev_if->out_ep_regs[_ep->num]; -+ dwc_otg_dev_in_ep_regs_t *in_regs = -+ _core_if->dev_if->in_ep_regs[_ep->num]; -+ gnptxsts_data_t txstatus; -+ -+ int lvl = SET_DEBUG_LEVEL(DBG_PCD); -+ -+ -+ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d " -+ "xfer_buff=%p start_xfer_buff=%p\n", -+ _ep->num, (_ep->is_in?"IN":"OUT"), _ep->xfer_len, -+ _ep->xfer_count, _ep->xfer_buff, _ep->start_xfer_buff); -+ -+ transfer_len = _ep->xfer_len - _ep->xfer_count; -+ if (transfer_len > MAX_XFER_SIZE) { -+ transfer_len = MAX_XFER_SIZE; -+ } -+ if (transfer_len == 0) { -+ num_packets = 1; -+ /* OUT EP to recieve Zero-length packet set transfer -+ * size to maxpacket size. */ -+ if (!_ep->is_in) { -+ transfer_len = _ep->maxpacket; -+ } -+ } else { -+ num_packets = -+ (transfer_len + _ep->maxpacket - 1) / _ep->maxpacket; -+ if (num_packets > MAX_PKT_COUNT) { -+ num_packets = MAX_PKT_COUNT; -+ } -+ } -+ DWC_DEBUGPL(DBG_PCD, "transfer_len=%d #pckt=%d\n", transfer_len, -+ num_packets); -+ -+ deptsiz.b.xfersize = transfer_len; -+ deptsiz.b.pktcnt = num_packets; -+ -+ /* IN endpoint */ -+ if (_ep->is_in == 1) { -+ depctl.d32 = dwc_read_reg32(&in_regs->diepctl); -+ } else {/* OUT endpoint */ -+ depctl.d32 = dwc_read_reg32(&out_regs->doepctl); -+ } -+ -+ /* EP enable, IN data in FIFO */ -+ depctl.b.cnak = 1; -+ depctl.b.epena = 1; -+ /* IN endpoint */ -+ if (_ep->is_in == 1) { -+ txstatus.d32 = -+ dwc_read_reg32(&_core_if->core_global_regs->gnptxsts); -+ if (txstatus.b.nptxqspcavail == 0) { -+ DWC_DEBUGPL(DBG_ANY, "TX Queue Full (0x%0x)\n", -+ txstatus.d32); -+ return; -+ } -+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); -+ dwc_write_reg32(&in_regs->diepctl, depctl.d32); -+ /** -+ * Enable the Non-Periodic Tx FIFO empty interrupt, the -+ * data will be written into the fifo by the ISR. -+ */ -+ if (_core_if->dma_enable) { -+ dwc_write_reg32(&in_regs->diepdma, (uint32_t) _ep->xfer_buff); -+ } else { -+ if (_core_if->en_multiple_tx_fifo == 0) { -+ intr_mask.b.nptxfempty = 1; -+ dwc_modify_reg32( &_core_if->core_global_regs->gintsts, -+ intr_mask.d32, 0); -+ dwc_modify_reg32( &_core_if->core_global_regs->gintmsk, -+ intr_mask.d32, intr_mask.d32); -+ } else { -+ /* Enable the Tx FIFO Empty Interrupt for this EP */ -+ if (_ep->xfer_len > 0 && -+ _ep->type != DWC_OTG_EP_TYPE_ISOC) { -+ uint32_t fifoemptymsk = 0; -+ fifoemptymsk = (0x1 << _ep->num); -+ dwc_modify_reg32(&_core_if->dev_if->dev_global_regs-> -+ dtknqr4_fifoemptymsk,0, fifoemptymsk); -+ } -+ } -+ } -+ } else { /* OUT endpoint */ -+ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); -+ dwc_write_reg32(&out_regs->doepctl, depctl.d32); -+ if (_core_if->dma_enable) { -+ dwc_write_reg32(&out_regs->doepdma,(uint32_t) _ep->xfer_buff); -+ } -+ } -+ DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n", -+ dwc_read_reg32(&out_regs->doepctl), -+ dwc_read_reg32(&out_regs->doeptsiz)); -+ DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n", -+ dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk), -+ dwc_read_reg32(&_core_if->core_global_regs->gintmsk)); -+ -+ SET_DEBUG_LEVEL(lvl); -+#endif -+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__); -+ -+ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d " -+ "xfer_buff=%p start_xfer_buff=%p\n", -+ _ep->num, (_ep->is_in?"IN":"OUT"), _ep->xfer_len, -+ _ep->xfer_count, _ep->xfer_buff, _ep->start_xfer_buff); -+ -+ /* IN endpoint */ -+ if (_ep->is_in == 1) { -+ dwc_otg_dev_in_ep_regs_t * in_regs = _core_if->dev_if->in_ep_regs[_ep->num]; -+ gnptxsts_data_t gtxstatus; -+ gtxstatus.d32 = dwc_read_reg32(&_core_if->core_global_regs->gnptxsts); -+ if (_core_if->en_multiple_tx_fifo == 0 && -+ gtxstatus.b.nptxqspcavail == 0) { -+#ifdef DEBUG -+ DWC_PRINT("TX Queue Full (0x%0x)\n", gtxstatus.d32); -+#endif -+ //return; -+ MDELAY(100); //james -+ } -+ -+ depctl.d32 = dwc_read_reg32(&(in_regs->diepctl)); -+ deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz)); -+ -+ /* Zero Length Packet? */ -+ if (_ep->xfer_len == 0) { -+ deptsiz.b.xfersize = 0; -+ deptsiz.b.pktcnt = 1; -+ } else { -+ -+ /* Program the transfer size and packet count -+ * as follows: xfersize = N * maxpacket + -+ * short_packet pktcnt = N + (short_packet -+ * exist ? 1 : 0) -+ */ -+ deptsiz.b.xfersize = _ep->xfer_len; -+ deptsiz.b.pktcnt = (_ep->xfer_len - 1 + _ep->maxpacket) / _ep->maxpacket; -+ } -+ -+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); -+ -+ /* Write the DMA register */ -+ if (_core_if->dma_enable) { -+#if 1 // winder -+ dma_cache_wback_inv((unsigned long) _ep->xfer_buff, _ep->xfer_len); // winder -+ dwc_write_reg32 (&(in_regs->diepdma), -+ CPHYSADDR((uint32_t)_ep->xfer_buff)); // winder -+#else -+ dwc_write_reg32 (&(in_regs->diepdma), -+ (uint32_t)_ep->dma_addr); -+#endif -+ } else { -+ if (_ep->type != DWC_OTG_EP_TYPE_ISOC) { -+ /** -+ * Enable the Non-Periodic Tx FIFO empty interrupt, -+ * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, -+ * the data will be written into the fifo by the ISR. -+ */ -+ if (_core_if->en_multiple_tx_fifo == 0) { -+ intr_mask.b.nptxfempty = 1; -+ dwc_modify_reg32( &_core_if->core_global_regs->gintsts, -+ intr_mask.d32, 0); -+ dwc_modify_reg32( &_core_if->core_global_regs->gintmsk, -+ intr_mask.d32, intr_mask.d32); -+ } else { -+ /* Enable the Tx FIFO Empty Interrupt for this EP */ -+ if (_ep->xfer_len > 0) { -+ uint32_t fifoemptymsk = 0; -+ fifoemptymsk = 1 << _ep->num; -+ dwc_modify_reg32(&_core_if->dev_if->dev_global_regs-> -+ dtknqr4_fifoemptymsk,0,fifoemptymsk); -+ } -+ } -+ } -+ } -+ -+ /* EP enable, IN data in FIFO */ -+ depctl.b.cnak = 1; -+ depctl.b.epena = 1; -+ dwc_write_reg32(&in_regs->diepctl, depctl.d32); -+ -+ if (_core_if->dma_enable) { -+ depctl.d32 = dwc_read_reg32 (&_core_if->dev_if->in_ep_regs[0]->diepctl); -+ depctl.b.nextep = _ep->num; -+ dwc_write_reg32 (&_core_if->dev_if->in_ep_regs[0]->diepctl, depctl.d32); -+ -+ } -+ } else { -+ /* OUT endpoint */ -+ dwc_otg_dev_out_ep_regs_t * out_regs = _core_if->dev_if->out_ep_regs[_ep->num]; -+ -+ depctl.d32 = dwc_read_reg32(&(out_regs->doepctl)); -+ deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz)); -+ -+ /* Program the transfer size and packet count as follows: -+ * -+ * pktcnt = N -+ * xfersize = N * maxpacket -+ */ -+ if (_ep->xfer_len == 0) { -+ /* Zero Length Packet */ -+ deptsiz.b.xfersize = _ep->maxpacket; -+ deptsiz.b.pktcnt = 1; -+ } else { -+ deptsiz.b.pktcnt = (_ep->xfer_len + (_ep->maxpacket - 1)) / _ep->maxpacket; -+ deptsiz.b.xfersize = deptsiz.b.pktcnt * _ep->maxpacket; -+ } -+ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); -+ -+ DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n", -+ _ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt); -+ -+ if (_core_if->dma_enable) { -+#if 1 // winder -+ dwc_write_reg32 (&(out_regs->doepdma), -+ CPHYSADDR((uint32_t)_ep->xfer_buff)); // winder -+#else -+ dwc_write_reg32 (&(out_regs->doepdma), -+ (uint32_t)_ep->dma_addr); -+#endif -+ } -+ -+ if (_ep->type == DWC_OTG_EP_TYPE_ISOC) { -+ /** @todo NGS: dpid is read-only. Use setd0pid -+ * or setd1pid. */ -+ if (_ep->even_odd_frame) { -+ depctl.b.setd1pid = 1; -+ } else { -+ depctl.b.setd0pid = 1; -+ } -+ } -+ -+ /* EP enable */ -+ depctl.b.cnak = 1; -+ depctl.b.epena = 1; -+ -+ dwc_write_reg32(&out_regs->doepctl, depctl.d32); -+ -+ DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n", -+ dwc_read_reg32(&out_regs->doepctl), -+ dwc_read_reg32(&out_regs->doeptsiz)); -+ DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n", -+ dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk), -+ dwc_read_reg32(&_core_if->core_global_regs->gintmsk)); -+ } -+} -+ -+ -+/** -+ * This function does the setup for a data transfer for EP0 and starts -+ * the transfer. For an IN transfer, the packets will be loaded into -+ * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are -+ * unloaded from the Rx FIFO in the ISR. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ * @param _ep The EP0 data. -+ */ -+void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) -+{ -+ volatile depctl_data_t depctl; -+ volatile deptsiz0_data_t deptsiz; -+ gintmsk_data_t intr_mask = { .d32 = 0}; -+ -+ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d " -+ "xfer_buff=%p start_xfer_buff=%p total_len=%d\n", -+ _ep->num, (_ep->is_in?"IN":"OUT"), _ep->xfer_len, -+ _ep->xfer_count, _ep->xfer_buff, _ep->start_xfer_buff, -+ _ep->total_len); -+ _ep->total_len = _ep->xfer_len; -+ -+ /* IN endpoint */ -+ if (_ep->is_in == 1) { -+ dwc_otg_dev_in_ep_regs_t * in_regs = _core_if->dev_if->in_ep_regs[0]; -+ gnptxsts_data_t gtxstatus; -+ gtxstatus.d32 = dwc_read_reg32(&_core_if->core_global_regs->gnptxsts); -+ if (_core_if->en_multiple_tx_fifo == 0 && -+ gtxstatus.b.nptxqspcavail == 0) { -+#ifdef DEBUG -+ deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz); -+ DWC_DEBUGPL(DBG_PCD,"DIEPCTL0=%0x\n", -+ dwc_read_reg32(&in_regs->diepctl)); -+ DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n", -+ deptsiz.d32, deptsiz.b.xfersize,deptsiz.b.pktcnt); -+ DWC_PRINT("TX Queue or FIFO Full (0x%0x)\n", gtxstatus.d32); -+#endif /* */ -+ printk("TX Queue or FIFO Full!!!!\n"); // test-only -+ //return; -+ MDELAY(100); //james -+ } -+ -+ depctl.d32 = dwc_read_reg32(&in_regs->diepctl); -+ deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz); -+ -+ /* Zero Length Packet? */ -+ if (_ep->xfer_len == 0) { -+ deptsiz.b.xfersize = 0; -+ deptsiz.b.pktcnt = 1; -+ } else { -+ /* Program the transfer size and packet count -+ * as follows: xfersize = N * maxpacket + -+ * short_packet pktcnt = N + (short_packet -+ * exist ? 1 : 0) -+ */ -+ if (_ep->xfer_len > _ep->maxpacket) { -+ _ep->xfer_len = _ep->maxpacket; -+ deptsiz.b.xfersize = _ep->maxpacket; -+ } -+ else { -+ deptsiz.b.xfersize = _ep->xfer_len; -+ } -+ deptsiz.b.pktcnt = 1; -+ -+ } -+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); -+ DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", -+ _ep->xfer_len, deptsiz.b.xfersize,deptsiz.b.pktcnt, deptsiz.d32); -+ -+ /* Write the DMA register */ -+ if (_core_if->dma_enable) { -+ dwc_write_reg32(&(in_regs->diepdma), (uint32_t) _ep->dma_addr); -+ } -+ -+ /* EP enable, IN data in FIFO */ -+ depctl.b.cnak = 1; -+ depctl.b.epena = 1; -+ dwc_write_reg32(&in_regs->diepctl, depctl.d32); -+ -+ /** -+ * Enable the Non-Periodic Tx FIFO empty interrupt, the -+ * data will be written into the fifo by the ISR. -+ */ -+ if (!_core_if->dma_enable) { -+ if (_core_if->en_multiple_tx_fifo == 0) { -+ intr_mask.b.nptxfempty = 1; -+ dwc_modify_reg32(&_core_if->core_global_regs->gintsts, intr_mask.d32, 0); -+ dwc_modify_reg32(&_core_if->core_global_regs->gintmsk, intr_mask.d32, -+ intr_mask.d32); -+ } else { -+ /* Enable the Tx FIFO Empty Interrupt for this EP */ -+ if (_ep->xfer_len > 0) { -+ uint32_t fifoemptymsk = 0; -+ fifoemptymsk |= 1 << _ep->num; -+ dwc_modify_reg32(&_core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk, -+ 0, fifoemptymsk); -+ } -+ -+ } -+ } -+ } else { -+ /* OUT endpoint */ -+ dwc_otg_dev_out_ep_regs_t * out_regs = _core_if->dev_if->out_ep_regs[_ep->num]; -+ -+ depctl.d32 = dwc_read_reg32(&out_regs->doepctl); -+ deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz); -+ -+ /* Program the transfer size and packet count as follows: -+ * xfersize = N * (maxpacket + 4 - (maxpacket % 4)) -+ * pktcnt = N */ -+ if (_ep->xfer_len == 0) { -+ /* Zero Length Packet */ -+ deptsiz.b.xfersize = _ep->maxpacket; -+ deptsiz.b.pktcnt = 1; -+ } else { -+ deptsiz.b.pktcnt = (_ep->xfer_len + (_ep->maxpacket - 1)) / _ep->maxpacket; -+ deptsiz.b.xfersize = deptsiz.b.pktcnt * _ep->maxpacket; -+ } -+ -+ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); -+ DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n", -+ _ep->xfer_len, deptsiz.b.xfersize,deptsiz.b.pktcnt); -+ -+ if (_core_if->dma_enable) { -+ dwc_write_reg32(&(out_regs->doepdma), (uint32_t) _ep->dma_addr); -+ } -+ -+ /* EP enable */ -+ depctl.b.cnak = 1; -+ depctl.b.epena = 1; -+ dwc_write_reg32 (&(out_regs->doepctl), depctl.d32); -+ } -+} -+ -+/** -+ * This function continues control IN transfers started by -+ * dwc_otg_ep0_start_transfer, when the transfer does not fit in a -+ * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one -+ * bit for the packet count. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ * @param _ep The EP0 data. -+ */ -+void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) -+{ -+ depctl_data_t depctl; -+ deptsiz0_data_t deptsiz; -+ gintmsk_data_t intr_mask = { .d32 = 0}; -+ -+ if (_ep->is_in == 1) { -+ dwc_otg_dev_in_ep_regs_t *in_regs = -+ _core_if->dev_if->in_ep_regs[0]; -+ gnptxsts_data_t tx_status = {.d32 = 0}; -+ -+ tx_status.d32 = dwc_read_reg32( &_core_if->core_global_regs->gnptxsts ); -+ /** @todo Should there be check for room in the Tx -+ * Status Queue. If not remove the code above this comment. */ -+ -+ depctl.d32 = dwc_read_reg32(&in_regs->diepctl); -+ deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz); -+ -+ /* Program the transfer size and packet count -+ * as follows: xfersize = N * maxpacket + -+ * short_packet pktcnt = N + (short_packet -+ * exist ? 1 : 0) -+ */ -+ deptsiz.b.xfersize = (_ep->total_len - _ep->xfer_count) > _ep->maxpacket ? _ep->maxpacket : -+ (_ep->total_len - _ep->xfer_count); -+ deptsiz.b.pktcnt = 1; -+ _ep->xfer_len += deptsiz.b.xfersize; -+ -+ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); -+ DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", -+ _ep->xfer_len, -+ deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32); -+ -+ /* Write the DMA register */ -+ if (_core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) { -+ dwc_write_reg32 (&(in_regs->diepdma), -+ CPHYSADDR((uint32_t)_ep->dma_addr)); // winder -+ } -+ -+ /* EP enable, IN data in FIFO */ -+ depctl.b.cnak = 1; -+ depctl.b.epena = 1; -+ dwc_write_reg32(&in_regs->diepctl, depctl.d32); -+ -+ /** -+ * Enable the Non-Periodic Tx FIFO empty interrupt, the -+ * data will be written into the fifo by the ISR. -+ */ -+ if (!_core_if->dma_enable) { -+ /* First clear it from GINTSTS */ -+ intr_mask.b.nptxfempty = 1; -+ dwc_write_reg32( &_core_if->core_global_regs->gintsts, -+ intr_mask.d32 ); -+ -+ dwc_modify_reg32( &_core_if->core_global_regs->gintmsk, -+ intr_mask.d32, intr_mask.d32); -+ } -+ -+ } -+ -+} -+ -+#ifdef DEBUG -+void dump_msg(const u8 *buf, unsigned int length) -+{ -+ unsigned int start, num, i; -+ char line[52], *p; -+ -+ if (length >= 512) -+ return; -+ start = 0; -+ while (length > 0) { -+ num = min(length, 16u); -+ p = line; -+ for (i = 0; i < num; ++i) { -+ if (i == 8) -+ *p++ = ' '; -+ sprintf(p, " %02x", buf[i]); -+ p += 3; -+ } -+ *p = 0; -+ DWC_PRINT( "%6x: %s\n", start, line); -+ buf += num; -+ start += num; -+ length -= num; -+ } -+} -+#else -+static inline void dump_msg(const u8 *buf, unsigned int length) -+{ -+} -+#endif -+ -+/** -+ * This function writes a packet into the Tx FIFO associated with the -+ * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For -+ * periodic EPs the periodic Tx FIFO associated with the EP is written -+ * with all packets for the next micro-frame. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ * @param _ep The EP to write packet for. -+ * @param _dma Indicates if DMA is being used. -+ */ -+void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma) -+{ -+ /** -+ * The buffer is padded to DWORD on a per packet basis in -+ * slave/dma mode if the MPS is not DWORD aligned. The last -+ * packet, if short, is also padded to a multiple of DWORD. -+ * -+ * ep->xfer_buff always starts DWORD aligned in memory and is a -+ * multiple of DWORD in length -+ * -+ * ep->xfer_len can be any number of bytes -+ * -+ * ep->xfer_count is a multiple of ep->maxpacket until the last -+ * packet -+ * -+ * FIFO access is DWORD */ -+ -+ uint32_t i; -+ uint32_t byte_count; -+ uint32_t dword_count; -+ uint32_t *fifo; -+ uint32_t *data_buff = (uint32_t *)_ep->xfer_buff; -+ -+ //DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, _core_if, _ep); -+ if (_ep->xfer_count >= _ep->xfer_len) { -+ DWC_WARN("%s() No data for EP%d!!!\n", __func__, _ep->num); -+ return; -+ } -+ -+ /* Find the byte length of the packet either short packet or MPS */ -+ if ((_ep->xfer_len - _ep->xfer_count) < _ep->maxpacket) { -+ byte_count = _ep->xfer_len - _ep->xfer_count; -+ } -+ else { -+ byte_count = _ep->maxpacket; -+ } -+ -+ /* Find the DWORD length, padded by extra bytes as neccessary if MPS -+ * is not a multiple of DWORD */ -+ dword_count = (byte_count + 3) / 4; -+ -+#ifdef VERBOSE -+ dump_msg(_ep->xfer_buff, byte_count); -+#endif -+ if (_ep->type == DWC_OTG_EP_TYPE_ISOC) { -+ /**@todo NGS Where are the Periodic Tx FIFO addresses -+ * intialized? What should this be? */ -+ fifo = _core_if->data_fifo[_ep->tx_fifo_num]; -+ } else { -+ fifo = _core_if->data_fifo[_ep->num]; -+ } -+ -+ DWC_DEBUGPL((DBG_PCDV|DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n", -+ fifo, data_buff, *data_buff, byte_count); -+ -+ -+ if (!_dma) { -+ for (i=0; ixfer_count += byte_count; -+ _ep->xfer_buff += byte_count; -+#if 1 // winder, why do we need this?? -+ _ep->dma_addr += byte_count; -+#endif -+} -+ -+/** -+ * Set the EP STALL. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ * @param _ep The EP to set the stall on. -+ */ -+void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) -+{ -+ depctl_data_t depctl; -+ volatile uint32_t *depctl_addr; -+ -+ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _ep->num, -+ (_ep->is_in?"IN":"OUT")); -+ -+ if (_ep->is_in == 1) { -+ depctl_addr = &(_core_if->dev_if->in_ep_regs[_ep->num]->diepctl); -+ depctl.d32 = dwc_read_reg32(depctl_addr); -+ -+ /* set the disable and stall bits */ -+ if (depctl.b.epena) { -+ depctl.b.epdis = 1; -+ } -+ depctl.b.stall = 1; -+ dwc_write_reg32(depctl_addr, depctl.d32); -+ -+ } else { -+ depctl_addr = &(_core_if->dev_if->out_ep_regs[_ep->num]->doepctl); -+ depctl.d32 = dwc_read_reg32(depctl_addr); -+ -+ /* set the stall bit */ -+ depctl.b.stall = 1; -+ dwc_write_reg32(depctl_addr, depctl.d32); -+ } -+ DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr)); -+ return; -+} -+ -+/** -+ * Clear the EP STALL. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ * @param _ep The EP to clear stall from. -+ */ -+void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) -+{ -+ depctl_data_t depctl; -+ volatile uint32_t *depctl_addr; -+ -+ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _ep->num, -+ (_ep->is_in?"IN":"OUT")); -+ -+ if (_ep->is_in == 1) { -+ depctl_addr = &(_core_if->dev_if->in_ep_regs[_ep->num]->diepctl); -+ } else { -+ depctl_addr = &(_core_if->dev_if->out_ep_regs[_ep->num]->doepctl); -+ } -+ -+ depctl.d32 = dwc_read_reg32(depctl_addr); -+ -+ /* clear the stall bits */ -+ depctl.b.stall = 0; -+ -+ /* -+ * USB Spec 9.4.5: For endpoints using data toggle, regardless -+ * of whether an endpoint has the Halt feature set, a -+ * ClearFeature(ENDPOINT_HALT) request always results in the -+ * data toggle being reinitialized to DATA0. -+ */ -+ if (_ep->type == DWC_OTG_EP_TYPE_INTR || -+ _ep->type == DWC_OTG_EP_TYPE_BULK) { -+ depctl.b.setd0pid = 1; /* DATA0 */ -+ } -+ -+ dwc_write_reg32(depctl_addr, depctl.d32); -+ DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr)); -+ return; -+} -+ -+/** -+ * This function reads a packet from the Rx FIFO into the destination -+ * buffer. To read SETUP data use dwc_otg_read_setup_packet. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ * @param _dest Destination buffer for the packet. -+ * @param _bytes Number of bytes to copy to the destination. -+ */ -+void dwc_otg_read_packet(dwc_otg_core_if_t *_core_if, -+ uint8_t *_dest, -+ uint16_t _bytes) -+{ -+ int i; -+ int word_count = (_bytes + 3) / 4; -+ -+ volatile uint32_t *fifo = _core_if->data_fifo[0]; -+ uint32_t *data_buff = (uint32_t *)_dest; -+ -+ /** -+ * @todo Account for the case where _dest is not dword aligned. This -+ * requires reading data from the FIFO into a uint32_t temp buffer, -+ * then moving it into the data buffer. -+ */ -+ -+ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__, -+ _core_if, _dest, _bytes); -+ -+ for (i=0; idev_if->dev_global_regs->dcfg; -+ DWC_PRINT("DCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->dev_if->dev_global_regs->dctl; -+ DWC_PRINT("DCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->dev_if->dev_global_regs->dsts; -+ DWC_PRINT("DSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->dev_if->dev_global_regs->diepmsk; -+ DWC_PRINT("DIEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->dev_if->dev_global_regs->doepmsk; -+ DWC_PRINT("DOEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->dev_if->dev_global_regs->daint; -+ DWC_PRINT("DAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->dev_if->dev_global_regs->dtknqr1; -+ DWC_PRINT("DTKNQR1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ if (_core_if->hwcfg2.b.dev_token_q_depth > 6) { -+ addr=&_core_if->dev_if->dev_global_regs->dtknqr2; -+ DWC_PRINT("DTKNQR2 @0x%08X : 0x%08X\n", -+ (uint32_t)addr,dwc_read_reg32(addr)); -+ } -+ -+ addr=&_core_if->dev_if->dev_global_regs->dvbusdis; -+ DWC_PRINT("DVBUSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ -+ addr=&_core_if->dev_if->dev_global_regs->dvbuspulse; -+ DWC_PRINT("DVBUSPULSE @0x%08X : 0x%08X\n", -+ (uint32_t)addr,dwc_read_reg32(addr)); -+ -+ if (_core_if->hwcfg2.b.dev_token_q_depth > 14) { -+ addr = &_core_if->dev_if->dev_global_regs->dtknqr3_dthrctl; -+ DWC_PRINT("DTKNQR3 @0x%08X : 0x%08X\n", -+ (uint32_t)addr, dwc_read_reg32(addr)); -+ } -+ -+ if (_core_if->hwcfg2.b.dev_token_q_depth > 22) { -+ addr = &_core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk; -+ DWC_PRINT("DTKNQR4 @0x%08X : 0x%08X\n", (uint32_t) addr, -+ dwc_read_reg32(addr)); -+ } -+ for (i = 0; i <= _core_if->dev_if->num_in_eps; i++) { -+ DWC_PRINT("Device IN EP %d Registers\n", i); -+ addr=&_core_if->dev_if->in_ep_regs[i]->diepctl; -+ DWC_PRINT("DIEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->dev_if->in_ep_regs[i]->diepint; -+ DWC_PRINT("DIEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->dev_if->in_ep_regs[i]->dieptsiz; -+ DWC_PRINT("DIETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->dev_if->in_ep_regs[i]->diepdma; -+ DWC_PRINT("DIEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ -+addr = &_core_if->dev_if->in_ep_regs[i]->dtxfsts; -+ DWC_PRINT("DTXFSTS @0x%08X : 0x%08X\n", (uint32_t) addr, -+ dwc_read_reg32(addr)); -+ } -+ for (i = 0; i <= _core_if->dev_if->num_out_eps; i++) { -+ DWC_PRINT("Device OUT EP %d Registers\n", i); -+ addr=&_core_if->dev_if->out_ep_regs[i]->doepctl; -+ DWC_PRINT("DOEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->dev_if->out_ep_regs[i]->doepfn; -+ DWC_PRINT("DOEPFN @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->dev_if->out_ep_regs[i]->doepint; -+ DWC_PRINT("DOEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->dev_if->out_ep_regs[i]->doeptsiz; -+ DWC_PRINT("DOETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->dev_if->out_ep_regs[i]->doepdma; -+ DWC_PRINT("DOEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ } -+ return; -+} -+ -+/** -+ * This function reads the host registers and prints them -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ */ -+void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if) -+{ -+ int i; -+ volatile uint32_t *addr; -+ -+ DWC_PRINT("Host Global Registers\n"); -+ addr=&_core_if->host_if->host_global_regs->hcfg; -+ DWC_PRINT("HCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->host_if->host_global_regs->hfir; -+ DWC_PRINT("HFIR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->host_if->host_global_regs->hfnum; -+ DWC_PRINT("HFNUM @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->host_if->host_global_regs->hptxsts; -+ DWC_PRINT("HPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->host_if->host_global_regs->haint; -+ DWC_PRINT("HAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->host_if->host_global_regs->haintmsk; -+ DWC_PRINT("HAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=_core_if->host_if->hprt0; -+ DWC_PRINT("HPRT0 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ -+ for (i=0; i<_core_if->core_params->host_channels; i++) { -+ DWC_PRINT("Host Channel %d Specific Registers\n", i); -+ addr=&_core_if->host_if->hc_regs[i]->hcchar; -+ DWC_PRINT("HCCHAR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->host_if->hc_regs[i]->hcsplt; -+ DWC_PRINT("HCSPLT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->host_if->hc_regs[i]->hcint; -+ DWC_PRINT("HCINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->host_if->hc_regs[i]->hcintmsk; -+ DWC_PRINT("HCINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->host_if->hc_regs[i]->hctsiz; -+ DWC_PRINT("HCTSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->host_if->hc_regs[i]->hcdma; -+ DWC_PRINT("HCDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ -+ } -+ return; -+} -+ -+/** -+ * This function reads the core global registers and prints them -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ */ -+void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if) -+{ -+ int i; -+ volatile uint32_t *addr; -+ -+ DWC_PRINT("Core Global Registers\n"); -+ addr=&_core_if->core_global_regs->gotgctl; -+ DWC_PRINT("GOTGCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->core_global_regs->gotgint; -+ DWC_PRINT("GOTGINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->core_global_regs->gahbcfg; -+ DWC_PRINT("GAHBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->core_global_regs->gusbcfg; -+ DWC_PRINT("GUSBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->core_global_regs->grstctl; -+ DWC_PRINT("GRSTCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->core_global_regs->gintsts; -+ DWC_PRINT("GINTSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->core_global_regs->gintmsk; -+ DWC_PRINT("GINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->core_global_regs->grxstsr; -+ DWC_PRINT("GRXSTSR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ //addr=&_core_if->core_global_regs->grxstsp; -+ //DWC_PRINT("GRXSTSP @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->core_global_regs->grxfsiz; -+ DWC_PRINT("GRXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->core_global_regs->gnptxfsiz; -+ DWC_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->core_global_regs->gnptxsts; -+ DWC_PRINT("GNPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->core_global_regs->gi2cctl; -+ DWC_PRINT("GI2CCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->core_global_regs->gpvndctl; -+ DWC_PRINT("GPVNDCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->core_global_regs->ggpio; -+ DWC_PRINT("GGPIO @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->core_global_regs->guid; -+ DWC_PRINT("GUID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->core_global_regs->gsnpsid; -+ DWC_PRINT("GSNPSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->core_global_regs->ghwcfg1; -+ DWC_PRINT("GHWCFG1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->core_global_regs->ghwcfg2; -+ DWC_PRINT("GHWCFG2 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->core_global_regs->ghwcfg3; -+ DWC_PRINT("GHWCFG3 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->core_global_regs->ghwcfg4; -+ DWC_PRINT("GHWCFG4 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ addr=&_core_if->core_global_regs->hptxfsiz; -+ DWC_PRINT("HPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); -+ -+ for (i=0; i<_core_if->hwcfg4.b.num_dev_perio_in_ep; i++) { -+ addr=&_core_if->core_global_regs->dptxfsiz_dieptxf[i]; -+ DWC_PRINT("DPTXFSIZ[%d] @0x%08X : 0x%08X\n",i,(uint32_t)addr,dwc_read_reg32(addr)); -+ } -+ -+} -+#endif -+ -+/** -+ * Flush a Tx FIFO. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ * @param _num Tx FIFO to flush. -+ */ -+extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if, -+ const int _num ) -+{ -+ dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs; -+ volatile grstctl_t greset = { .d32 = 0}; -+ int count = 0; -+ -+ DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "Flush Tx FIFO %d\n", _num); -+ -+ greset.b.txfflsh = 1; -+ greset.b.txfnum = _num; -+ dwc_write_reg32( &global_regs->grstctl, greset.d32 ); -+ -+ do { -+ greset.d32 = dwc_read_reg32( &global_regs->grstctl); -+ if (++count > 10000){ -+ DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", -+ __func__, greset.d32, -+ dwc_read_reg32( &global_regs->gnptxsts)); -+ break; -+ } -+ -+ udelay(1); -+ } while (greset.b.txfflsh == 1); -+ /* Wait for 3 PHY Clocks*/ -+ UDELAY(1); -+} -+ -+/** -+ * Flush Rx FIFO. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ */ -+extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if ) -+{ -+ dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs; -+ volatile grstctl_t greset = { .d32 = 0}; -+ int count = 0; -+ -+ DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__); -+ /* -+ * -+ */ -+ greset.b.rxfflsh = 1; -+ dwc_write_reg32( &global_regs->grstctl, greset.d32 ); -+ -+ do { -+ greset.d32 = dwc_read_reg32( &global_regs->grstctl); -+ if (++count > 10000){ -+ DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, -+ greset.d32); -+ break; -+ } -+ } while (greset.b.rxfflsh == 1); -+ /* Wait for 3 PHY Clocks*/ -+ UDELAY(1); -+} -+ -+/** -+ * Do core a soft reset of the core. Be careful with this because it -+ * resets all the internal state machines of the core. -+ */ -+ -+void dwc_otg_core_reset(dwc_otg_core_if_t *_core_if) -+{ -+ dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs; -+ volatile grstctl_t greset = { .d32 = 0}; -+ int count = 0; -+ -+ DWC_DEBUGPL(DBG_CILV, "%s\n", __func__); -+ /* Wait for AHB master IDLE state. */ -+ do { -+ UDELAY(10); -+ greset.d32 = dwc_read_reg32( &global_regs->grstctl); -+ if (++count > 100000){ -+ DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x %x\n", __func__, -+ greset.d32, greset.b.ahbidle); -+ return; -+ } -+ } while (greset.b.ahbidle == 0); -+ -+// winder add. -+#if 1 -+ /* Note: Actually, I don't exactly why we need to put delay here. */ -+ MDELAY(100); -+#endif -+ /* Core Soft Reset */ -+ count = 0; -+ greset.b.csftrst = 1; -+ dwc_write_reg32( &global_regs->grstctl, greset.d32 ); -+// winder add. -+#if 1 -+ /* Note: Actually, I don't exactly why we need to put delay here. */ -+ MDELAY(100); -+#endif -+ do { -+ greset.d32 = dwc_read_reg32( &global_regs->grstctl); -+ if (++count > 10000){ -+ DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", __func__, -+ greset.d32); -+ break; -+ } -+ udelay(1); -+ } while (greset.b.csftrst == 1); -+ /* Wait for 3 PHY Clocks*/ -+ //DWC_PRINT("100ms\n"); -+ MDELAY(100); -+} -+ -+ -+ -+/** -+ * Register HCD callbacks. The callbacks are used to start and stop -+ * the HCD for interrupt processing. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ * @param _cb the HCD callback structure. -+ * @param _p pointer to be passed to callback function (usb_hcd*). -+ */ -+extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if, -+ dwc_otg_cil_callbacks_t *_cb, -+ void *_p) -+{ -+ _core_if->hcd_cb = _cb; -+ _cb->p = _p; -+} -+ -+/** -+ * Register PCD callbacks. The callbacks are used to start and stop -+ * the PCD for interrupt processing. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ * @param _cb the PCD callback structure. -+ * @param _p pointer to be passed to callback function (pcd*). -+ */ -+extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if, -+ dwc_otg_cil_callbacks_t *_cb, -+ void *_p) -+{ -+ _core_if->pcd_cb = _cb; -+ _cb->p = _p; -+} -+ ---- /dev/null -+++ b/drivers/usb/dwc_otg/dwc_otg_cil.h -@@ -0,0 +1,911 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil.h $ -+ * $Revision: 1.1.1.1 $ -+ * $Date: 2009-04-17 06:15:34 $ -+ * $Change: 631780 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+#if !defined(__DWC_CIL_H__) -+#define __DWC_CIL_H__ -+ -+#include "dwc_otg_plat.h" -+ -+#include "dwc_otg_regs.h" -+#ifdef DEBUG -+#include "linux/timer.h" -+#endif -+ -+/* the OTG capabilities. */ -+#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0 -+#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1 -+#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 -+/* the maximum speed of operation in host and device mode. */ -+#define DWC_SPEED_PARAM_HIGH 0 -+#define DWC_SPEED_PARAM_FULL 1 -+/* the PHY clock rate in low power mode when connected to a -+ * Low Speed device in host mode. */ -+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 -+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 -+/* the type of PHY interface to use. */ -+#define DWC_PHY_TYPE_PARAM_FS 0 -+#define DWC_PHY_TYPE_PARAM_UTMI 1 -+#define DWC_PHY_TYPE_PARAM_ULPI 2 -+/* whether to use the internal or external supply to -+ * drive the vbus with a ULPI phy. */ -+#define DWC_PHY_ULPI_INTERNAL_VBUS 0 -+#define DWC_PHY_ULPI_EXTERNAL_VBUS 1 -+/* EP type. */ -+ -+/** -+ * @file -+ * This file contains the interface to the Core Interface Layer. -+ */ -+ -+/** -+ * The dwc_ep structure represents the state of a single -+ * endpoint when acting in device mode. It contains the data items -+ * needed for an endpoint to be activated and transfer packets. -+ */ -+typedef struct dwc_ep { -+ /** EP number used for register address lookup */ -+ uint8_t num; -+ /** EP direction 0 = OUT */ -+ unsigned is_in : 1; -+ /** EP active. */ -+ unsigned active : 1; -+ -+ /** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO -+ If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/ -+ unsigned tx_fifo_num : 4; -+ /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */ -+ unsigned type : 2; -+#define DWC_OTG_EP_TYPE_CONTROL 0 -+#define DWC_OTG_EP_TYPE_ISOC 1 -+#define DWC_OTG_EP_TYPE_BULK 2 -+#define DWC_OTG_EP_TYPE_INTR 3 -+ -+ /** DATA start PID for INTR and BULK EP */ -+ unsigned data_pid_start : 1; -+ /** Frame (even/odd) for ISOC EP */ -+ unsigned even_odd_frame : 1; -+ /** Max Packet bytes */ -+ unsigned maxpacket : 11; -+ -+ /** @name Transfer state */ -+ /** @{ */ -+ -+ /** -+ * Pointer to the beginning of the transfer buffer -- do not modify -+ * during transfer. -+ */ -+ -+ uint32_t dma_addr; -+ -+ uint8_t *start_xfer_buff; -+ /** pointer to the transfer buffer */ -+ uint8_t *xfer_buff; -+ /** Number of bytes to transfer */ -+ unsigned xfer_len : 19; -+ /** Number of bytes transferred. */ -+ unsigned xfer_count : 19; -+ /** Sent ZLP */ -+ unsigned sent_zlp : 1; -+ /** Total len for control transfer */ -+ unsigned total_len : 19; -+ -+ /** stall clear flag */ -+ unsigned stall_clear_flag : 1; -+ -+ /** @} */ -+} dwc_ep_t; -+ -+/* -+ * Reasons for halting a host channel. -+ */ -+typedef enum dwc_otg_halt_status { -+ DWC_OTG_HC_XFER_NO_HALT_STATUS, -+ DWC_OTG_HC_XFER_COMPLETE, -+ DWC_OTG_HC_XFER_URB_COMPLETE, -+ DWC_OTG_HC_XFER_ACK, -+ DWC_OTG_HC_XFER_NAK, -+ DWC_OTG_HC_XFER_NYET, -+ DWC_OTG_HC_XFER_STALL, -+ DWC_OTG_HC_XFER_XACT_ERR, -+ DWC_OTG_HC_XFER_FRAME_OVERRUN, -+ DWC_OTG_HC_XFER_BABBLE_ERR, -+ DWC_OTG_HC_XFER_DATA_TOGGLE_ERR, -+ DWC_OTG_HC_XFER_AHB_ERR, -+ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE, -+ DWC_OTG_HC_XFER_URB_DEQUEUE -+} dwc_otg_halt_status_e; -+ -+/** -+ * Host channel descriptor. This structure represents the state of a single -+ * host channel when acting in host mode. It contains the data items needed to -+ * transfer packets to an endpoint via a host channel. -+ */ -+typedef struct dwc_hc { -+ /** Host channel number used for register address lookup */ -+ uint8_t hc_num; -+ -+ /** Device to access */ -+ unsigned dev_addr : 7; -+ -+ /** EP to access */ -+ unsigned ep_num : 4; -+ -+ /** EP direction. 0: OUT, 1: IN */ -+ unsigned ep_is_in : 1; -+ -+ /** -+ * EP speed. -+ * One of the following values: -+ * - DWC_OTG_EP_SPEED_LOW -+ * - DWC_OTG_EP_SPEED_FULL -+ * - DWC_OTG_EP_SPEED_HIGH -+ */ -+ unsigned speed : 2; -+#define DWC_OTG_EP_SPEED_LOW 0 -+#define DWC_OTG_EP_SPEED_FULL 1 -+#define DWC_OTG_EP_SPEED_HIGH 2 -+ -+ /** -+ * Endpoint type. -+ * One of the following values: -+ * - DWC_OTG_EP_TYPE_CONTROL: 0 -+ * - DWC_OTG_EP_TYPE_ISOC: 1 -+ * - DWC_OTG_EP_TYPE_BULK: 2 -+ * - DWC_OTG_EP_TYPE_INTR: 3 -+ */ -+ unsigned ep_type : 2; -+ -+ /** Max packet size in bytes */ -+ unsigned max_packet : 11; -+ -+ /** -+ * PID for initial transaction. -+ * 0: DATA0,
-+ * 1: DATA2,
-+ * 2: DATA1,
-+ * 3: MDATA (non-Control EP), -+ * SETUP (Control EP) -+ */ -+ unsigned data_pid_start : 2; -+#define DWC_OTG_HC_PID_DATA0 0 -+#define DWC_OTG_HC_PID_DATA2 1 -+#define DWC_OTG_HC_PID_DATA1 2 -+#define DWC_OTG_HC_PID_MDATA 3 -+#define DWC_OTG_HC_PID_SETUP 3 -+ -+ /** Number of periodic transactions per (micro)frame */ -+ unsigned multi_count: 2; -+ -+ /** @name Transfer State */ -+ /** @{ */ -+ -+ /** Pointer to the current transfer buffer position. */ -+ uint8_t *xfer_buff; -+ /** Total number of bytes to transfer. */ -+ uint32_t xfer_len; -+ /** Number of bytes transferred so far. */ -+ uint32_t xfer_count; -+ /** Packet count at start of transfer.*/ -+ uint16_t start_pkt_count; -+ -+ /** -+ * Flag to indicate whether the transfer has been started. Set to 1 if -+ * it has been started, 0 otherwise. -+ */ -+ uint8_t xfer_started; -+ -+ /** -+ * Set to 1 to indicate that a PING request should be issued on this -+ * channel. If 0, process normally. -+ */ -+ uint8_t do_ping; -+ -+ /** -+ * Set to 1 to indicate that the error count for this transaction is -+ * non-zero. Set to 0 if the error count is 0. -+ */ -+ uint8_t error_state; -+ -+ /** -+ * Set to 1 to indicate that this channel should be halted the next -+ * time a request is queued for the channel. This is necessary in -+ * slave mode if no request queue space is available when an attempt -+ * is made to halt the channel. -+ */ -+ uint8_t halt_on_queue; -+ -+ /** -+ * Set to 1 if the host channel has been halted, but the core is not -+ * finished flushing queued requests. Otherwise 0. -+ */ -+ uint8_t halt_pending; -+ -+ /** -+ * Reason for halting the host channel. -+ */ -+ dwc_otg_halt_status_e halt_status; -+ -+ /* -+ * Split settings for the host channel -+ */ -+ uint8_t do_split; /**< Enable split for the channel */ -+ uint8_t complete_split; /**< Enable complete split */ -+ uint8_t hub_addr; /**< Address of high speed hub */ -+ -+ uint8_t port_addr; /**< Port of the low/full speed device */ -+ /** Split transaction position -+ * One of the following values: -+ * - DWC_HCSPLIT_XACTPOS_MID -+ * - DWC_HCSPLIT_XACTPOS_BEGIN -+ * - DWC_HCSPLIT_XACTPOS_END -+ * - DWC_HCSPLIT_XACTPOS_ALL */ -+ uint8_t xact_pos; -+ -+ /** Set when the host channel does a short read. */ -+ uint8_t short_read; -+ -+ /** -+ * Number of requests issued for this channel since it was assigned to -+ * the current transfer (not counting PINGs). -+ */ -+ uint8_t requests; -+ -+ /** -+ * Queue Head for the transfer being processed by this channel. -+ */ -+ struct dwc_otg_qh *qh; -+ -+ /** @} */ -+ -+ /** Entry in list of host channels. */ -+ struct list_head hc_list_entry; -+} dwc_hc_t; -+ -+/** -+ * The following parameters may be specified when starting the module. These -+ * parameters define how the DWC_otg controller should be configured. -+ * Parameter values are passed to the CIL initialization function -+ * dwc_otg_cil_init. -+ */ -+ -+typedef struct dwc_otg_core_params -+{ -+ int32_t opt; -+//#define dwc_param_opt_default 1 -+ /** -+ * Specifies the OTG capabilities. The driver will automatically -+ * detect the value for this parameter if none is specified. -+ * 0 - HNP and SRP capable (default) -+ * 1 - SRP Only capable -+ * 2 - No HNP/SRP capable -+ */ -+ int32_t otg_cap; -+#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0 -+#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1 -+#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 -+//#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE -+ /** -+ * Specifies whether to use slave or DMA mode for accessing the data -+ * FIFOs. The driver will automatically detect the value for this -+ * parameter if none is specified. -+ * 0 - Slave -+ * 1 - DMA (default, if available) -+ */ -+ int32_t dma_enable; -+//#define dwc_param_dma_enable_default 1 -+ /** The DMA Burst size (applicable only for External DMA -+ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32) -+ */ -+ int32_t dma_burst_size; /* Translate this to GAHBCFG values */ -+//#define dwc_param_dma_burst_size_default 32 -+ /** -+ * Specifies the maximum speed of operation in host and device mode. -+ * The actual speed depends on the speed of the attached device and -+ * the value of phy_type. The actual speed depends on the speed of the -+ * attached device. -+ * 0 - High Speed (default) -+ * 1 - Full Speed -+ */ -+ int32_t speed; -+//#define dwc_param_speed_default 0 -+#define DWC_SPEED_PARAM_HIGH 0 -+#define DWC_SPEED_PARAM_FULL 1 -+ -+ /** Specifies whether low power mode is supported when attached -+ * to a Full Speed or Low Speed device in host mode. -+ * 0 - Don't support low power mode (default) -+ * 1 - Support low power mode -+ */ -+ int32_t host_support_fs_ls_low_power; -+//#define dwc_param_host_support_fs_ls_low_power_default 0 -+ /** Specifies the PHY clock rate in low power mode when connected to a -+ * Low Speed device in host mode. This parameter is applicable only if -+ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS -+ * then defaults to 6 MHZ otherwise 48 MHZ. -+ * -+ * 0 - 48 MHz -+ * 1 - 6 MHz -+ */ -+ int32_t host_ls_low_power_phy_clk; -+//#define dwc_param_host_ls_low_power_phy_clk_default 0 -+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 -+#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 -+ /** -+ * 0 - Use cC FIFO size parameters -+ * 1 - Allow dynamic FIFO sizing (default) -+ */ -+ int32_t enable_dynamic_fifo; -+//#define dwc_param_enable_dynamic_fifo_default 1 -+ /** Total number of 4-byte words in the data FIFO memory. This -+ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic -+ * Tx FIFOs. -+ * 32 to 32768 (default 8192) -+ * Note: The total FIFO memory depth in the FPGA configuration is 8192. -+ */ -+ int32_t data_fifo_size; -+//#define dwc_param_data_fifo_size_default 8192 -+ /** Number of 4-byte words in the Rx FIFO in device mode when dynamic -+ * FIFO sizing is enabled. -+ * 16 to 32768 (default 1064) -+ */ -+ int32_t dev_rx_fifo_size; -+//#define dwc_param_dev_rx_fifo_size_default 1064 -+ /** Number of 4-byte words in the non-periodic Tx FIFO in device mode -+ * when dynamic FIFO sizing is enabled. -+ * 16 to 32768 (default 1024) -+ */ -+ int32_t dev_nperio_tx_fifo_size; -+//#define dwc_param_dev_nperio_tx_fifo_size_default 1024 -+ /** Number of 4-byte words in each of the periodic Tx FIFOs in device -+ * mode when dynamic FIFO sizing is enabled. -+ * 4 to 768 (default 256) -+ */ -+ uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS]; -+//#define dwc_param_dev_perio_tx_fifo_size_default 256 -+ /** Number of 4-byte words in the Rx FIFO in host mode when dynamic -+ * FIFO sizing is enabled. -+ * 16 to 32768 (default 1024) -+ */ -+ int32_t host_rx_fifo_size; -+//#define dwc_param_host_rx_fifo_size_default 1024 -+ /** Number of 4-byte words in the non-periodic Tx FIFO in host mode -+ * when Dynamic FIFO sizing is enabled in the core. -+ * 16 to 32768 (default 1024) -+ */ -+ int32_t host_nperio_tx_fifo_size; -+//#define dwc_param_host_nperio_tx_fifo_size_default 1024 -+ /** Number of 4-byte words in the host periodic Tx FIFO when dynamic -+ * FIFO sizing is enabled. -+ * 16 to 32768 (default 1024) -+ */ -+ int32_t host_perio_tx_fifo_size; -+//#define dwc_param_host_perio_tx_fifo_size_default 1024 -+ /** The maximum transfer size supported in bytes. -+ * 2047 to 65,535 (default 65,535) -+ */ -+ int32_t max_transfer_size; -+//#define dwc_param_max_transfer_size_default 65535 -+ /** The maximum number of packets in a transfer. -+ * 15 to 511 (default 511) -+ */ -+ int32_t max_packet_count; -+//#define dwc_param_max_packet_count_default 511 -+ /** The number of host channel registers to use. -+ * 1 to 16 (default 12) -+ * Note: The FPGA configuration supports a maximum of 12 host channels. -+ */ -+ int32_t host_channels; -+//#define dwc_param_host_channels_default 12 -+ /** The number of endpoints in addition to EP0 available for device -+ * mode operations. -+ * 1 to 15 (default 6 IN and OUT) -+ * Note: The FPGA configuration supports a maximum of 6 IN and OUT -+ * endpoints in addition to EP0. -+ */ -+ int32_t dev_endpoints; -+//#define dwc_param_dev_endpoints_default 6 -+ /** -+ * Specifies the type of PHY interface to use. By default, the driver -+ * will automatically detect the phy_type. -+ * -+ * 0 - Full Speed PHY -+ * 1 - UTMI+ (default) -+ * 2 - ULPI -+ */ -+ int32_t phy_type; -+#define DWC_PHY_TYPE_PARAM_FS 0 -+#define DWC_PHY_TYPE_PARAM_UTMI 1 -+#define DWC_PHY_TYPE_PARAM_ULPI 2 -+//#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI -+ /** -+ * Specifies the UTMI+ Data Width. This parameter is -+ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI -+ * PHY_TYPE, this parameter indicates the data width between -+ * the MAC and the ULPI Wrapper.) Also, this parameter is -+ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set -+ * to "8 and 16 bits", meaning that the core has been -+ * configured to work at either data path width. -+ * -+ * 8 or 16 bits (default 16) -+ */ -+ int32_t phy_utmi_width; -+//#define dwc_param_phy_utmi_width_default 16 -+ /** -+ * Specifies whether the ULPI operates at double or single -+ * data rate. This parameter is only applicable if PHY_TYPE is -+ * ULPI. -+ * -+ * 0 - single data rate ULPI interface with 8 bit wide data -+ * bus (default) -+ * 1 - double data rate ULPI interface with 4 bit wide data -+ * bus -+ */ -+ int32_t phy_ulpi_ddr; -+//#define dwc_param_phy_ulpi_ddr_default 0 -+ /** -+ * Specifies whether to use the internal or external supply to -+ * drive the vbus with a ULPI phy. -+ */ -+ int32_t phy_ulpi_ext_vbus; -+#define DWC_PHY_ULPI_INTERNAL_VBUS 0 -+#define DWC_PHY_ULPI_EXTERNAL_VBUS 1 -+//#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS -+ /** -+ * Specifies whether to use the I2Cinterface for full speed PHY. This -+ * parameter is only applicable if PHY_TYPE is FS. -+ * 0 - No (default) -+ * 1 - Yes -+ */ -+ int32_t i2c_enable; -+//#define dwc_param_i2c_enable_default 0 -+ -+ int32_t ulpi_fs_ls; -+//#define dwc_param_ulpi_fs_ls_default 0 -+ -+ int32_t ts_dline; -+//#define dwc_param_ts_dline_default 0 -+ -+ /** -+ * Specifies whether dedicated transmit FIFOs are -+ * enabled for non periodic IN endpoints in device mode -+ * 0 - No -+ * 1 - Yes -+ */ -+ int32_t en_multiple_tx_fifo; -+#define dwc_param_en_multiple_tx_fifo_default 1 -+ -+ /** Number of 4-byte words in each of the Tx FIFOs in device -+ * mode when dynamic FIFO sizing is enabled. -+ * 4 to 768 (default 256) -+ */ -+ uint32_t dev_tx_fifo_size[MAX_TX_FIFOS]; -+#define dwc_param_dev_tx_fifo_size_default 256 -+ -+ /** Thresholding enable flag- -+ * bit 0 - enable non-ISO Tx thresholding -+ * bit 1 - enable ISO Tx thresholding -+ * bit 2 - enable Rx thresholding -+ */ -+ uint32_t thr_ctl; -+#define dwc_param_thr_ctl_default 0 -+ -+ /** Thresholding length for Tx -+ * FIFOs in 32 bit DWORDs -+ */ -+ uint32_t tx_thr_length; -+#define dwc_param_tx_thr_length_default 64 -+ -+ /** Thresholding length for Rx -+ * FIFOs in 32 bit DWORDs -+ */ -+ uint32_t rx_thr_length; -+#define dwc_param_rx_thr_length_default 64 -+} dwc_otg_core_params_t; -+ -+#ifdef DEBUG -+struct dwc_otg_core_if; -+typedef struct hc_xfer_info -+{ -+ struct dwc_otg_core_if *core_if; -+ dwc_hc_t *hc; -+} hc_xfer_info_t; -+#endif -+ -+/** -+ * The dwc_otg_core_if structure contains information needed to manage -+ * the DWC_otg controller acting in either host or device mode. It -+ * represents the programming view of the controller as a whole. -+ */ -+typedef struct dwc_otg_core_if -+{ -+ /** Parameters that define how the core should be configured.*/ -+ dwc_otg_core_params_t *core_params; -+ -+ /** Core Global registers starting at offset 000h. */ -+ dwc_otg_core_global_regs_t *core_global_regs; -+ -+ /** Device-specific information */ -+ dwc_otg_dev_if_t *dev_if; -+ /** Host-specific information */ -+ dwc_otg_host_if_t *host_if; -+ -+ /* -+ * Set to 1 if the core PHY interface bits in USBCFG have been -+ * initialized. -+ */ -+ uint8_t phy_init_done; -+ -+ /* -+ * SRP Success flag, set by srp success interrupt in FS I2C mode -+ */ -+ uint8_t srp_success; -+ uint8_t srp_timer_started; -+ -+ /* Common configuration information */ -+ /** Power and Clock Gating Control Register */ -+ volatile uint32_t *pcgcctl; -+#define DWC_OTG_PCGCCTL_OFFSET 0xE00 -+ -+ /** Push/pop addresses for endpoints or host channels.*/ -+ uint32_t *data_fifo[MAX_EPS_CHANNELS]; -+#define DWC_OTG_DATA_FIFO_OFFSET 0x1000 -+#define DWC_OTG_DATA_FIFO_SIZE 0x1000 -+ -+ /** Total RAM for FIFOs (Bytes) */ -+ uint16_t total_fifo_size; -+ /** Size of Rx FIFO (Bytes) */ -+ uint16_t rx_fifo_size; -+ /** Size of Non-periodic Tx FIFO (Bytes) */ -+ uint16_t nperio_tx_fifo_size; -+ -+ /** 1 if DMA is enabled, 0 otherwise. */ -+ uint8_t dma_enable; -+ -+ /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */ -+ uint8_t en_multiple_tx_fifo; -+ -+ /** Set to 1 if multiple packets of a high-bandwidth transfer is in -+ * process of being queued */ -+ uint8_t queuing_high_bandwidth; -+ -+ /** Hardware Configuration -- stored here for convenience.*/ -+ hwcfg1_data_t hwcfg1; -+ hwcfg2_data_t hwcfg2; -+ hwcfg3_data_t hwcfg3; -+ hwcfg4_data_t hwcfg4; -+ -+ /** The operational State, during transations -+ * (a_host>>a_peripherial and b_device=>b_host) this may not -+ * match the core but allows the software to determine -+ * transitions. -+ */ -+ uint8_t op_state; -+ -+ /** -+ * Set to 1 if the HCD needs to be restarted on a session request -+ * interrupt. This is required if no connector ID status change has -+ * occurred since the HCD was last disconnected. -+ */ -+ uint8_t restart_hcd_on_session_req; -+ -+ /** HCD callbacks */ -+ /** A-Device is a_host */ -+#define A_HOST (1) -+ /** A-Device is a_suspend */ -+#define A_SUSPEND (2) -+ /** A-Device is a_peripherial */ -+#define A_PERIPHERAL (3) -+ /** B-Device is operating as a Peripheral. */ -+#define B_PERIPHERAL (4) -+ /** B-Device is operating as a Host. */ -+#define B_HOST (5) -+ -+ /** HCD callbacks */ -+ struct dwc_otg_cil_callbacks *hcd_cb; -+ /** PCD callbacks */ -+ struct dwc_otg_cil_callbacks *pcd_cb; -+ -+ /** Device mode Periodic Tx FIFO Mask */ -+ uint32_t p_tx_msk; -+ /** Device mode Periodic Tx FIFO Mask */ -+ uint32_t tx_msk; -+ -+#ifdef DEBUG -+ uint32_t start_hcchar_val[MAX_EPS_CHANNELS]; -+ -+ hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS]; -+ struct timer_list hc_xfer_timer[MAX_EPS_CHANNELS]; -+ -+#if 1 // winder -+ uint32_t hfnum_7_samples; -+ uint32_t hfnum_7_frrem_accum; -+ uint32_t hfnum_0_samples; -+ uint32_t hfnum_0_frrem_accum; -+ uint32_t hfnum_other_samples; -+ uint32_t hfnum_other_frrem_accum; -+#else -+ uint32_t hfnum_7_samples; -+ uint64_t hfnum_7_frrem_accum; -+ uint32_t hfnum_0_samples; -+ uint64_t hfnum_0_frrem_accum; -+ uint32_t hfnum_other_samples; -+ uint64_t hfnum_other_frrem_accum; -+#endif -+ resource_size_t phys_addr; /* Added to support PLB DMA : phys-virt mapping */ -+#endif -+ -+} dwc_otg_core_if_t; -+ -+/* -+ * The following functions support initialization of the CIL driver component -+ * and the DWC_otg controller. -+ */ -+extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr, -+ dwc_otg_core_params_t *_core_params); -+extern void dwc_otg_cil_remove(dwc_otg_core_if_t *_core_if); -+extern void dwc_otg_core_init(dwc_otg_core_if_t *_core_if); -+extern void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if); -+extern void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if); -+extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if ); -+extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if ); -+ -+/** @name Device CIL Functions -+ * The following functions support managing the DWC_otg controller in device -+ * mode. -+ */ -+/**@{*/ -+extern void dwc_otg_wakeup(dwc_otg_core_if_t *_core_if); -+extern void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest); -+extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if); -+extern void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); -+extern void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); -+extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); -+extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); -+extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); -+extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); -+extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma); -+extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); -+extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); -+extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if); -+extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if); -+/**@}*/ -+ -+/** @name Host CIL Functions -+ * The following functions support managing the DWC_otg controller in host -+ * mode. -+ */ -+/**@{*/ -+extern void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); -+extern void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if, -+ dwc_hc_t *_hc, -+ dwc_otg_halt_status_e _halt_status); -+extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); -+extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); -+extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); -+extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); -+extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); -+extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if); -+extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if); -+ -+/** -+ * This function Reads HPRT0 in preparation to modify. It keeps the -+ * WC bits 0 so that if they are read as 1, they won't clear when you -+ * write it back -+ */ -+static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t *_core_if) -+{ -+ hprt0_data_t hprt0; -+ hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0); -+ hprt0.b.prtena = 0; -+ hprt0.b.prtconndet = 0; -+ hprt0.b.prtenchng = 0; -+ hprt0.b.prtovrcurrchng = 0; -+ return hprt0.d32; -+} -+ -+extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if); -+/**@}*/ -+ -+/** @name Common CIL Functions -+ * The following functions support managing the DWC_otg controller in either -+ * device or host mode. -+ */ -+/**@{*/ -+ -+extern void dwc_otg_read_packet(dwc_otg_core_if_t *core_if, -+ uint8_t *dest, -+ uint16_t bytes); -+ -+extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if); -+ -+extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if, -+ const int _num ); -+extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if ); -+extern void dwc_otg_core_reset( dwc_otg_core_if_t *_core_if ); -+ -+#define NP_TXFIFO_EMPTY -1 -+#define MAX_NP_TXREQUEST_Q_SLOTS 8 -+/** -+ * This function returns the endpoint number of the request at -+ * the top of non-periodic TX FIFO, or -1 if the request FIFO is -+ * empty. -+ */ -+static inline int dwc_otg_top_nptxfifo_epnum(dwc_otg_core_if_t *_core_if) { -+ gnptxsts_data_t txstatus = {.d32 = 0}; -+ -+ txstatus.d32 = dwc_read_reg32(&_core_if->core_global_regs->gnptxsts); -+ return (txstatus.b.nptxqspcavail == MAX_NP_TXREQUEST_Q_SLOTS ? -+ -1 : txstatus.b.nptxqtop_chnep); -+} -+/** -+ * This function returns the Core Interrupt register. -+ */ -+static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t *_core_if) { -+ return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) & -+ dwc_read_reg32(&_core_if->core_global_regs->gintmsk)); -+} -+ -+/** -+ * This function returns the OTG Interrupt register. -+ */ -+static inline uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *_core_if) { -+ return (dwc_read_reg32 (&_core_if->core_global_regs->gotgint)); -+} -+ -+/** -+ * This function reads the Device All Endpoints Interrupt register and -+ * returns the IN endpoint interrupt bits. -+ */ -+static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *_core_if) { -+ uint32_t v; -+ v = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daint) & -+ dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk); -+ return (v & 0xffff); -+ -+} -+ -+/** -+ * This function reads the Device All Endpoints Interrupt register and -+ * returns the OUT endpoint interrupt bits. -+ */ -+static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *_core_if) { -+ uint32_t v; -+ v = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daint) & -+ dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk); -+ return ((v & 0xffff0000) >> 16); -+} -+ -+/** -+ * This function returns the Device IN EP Interrupt register -+ */ -+static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t *_core_if, -+ dwc_ep_t *_ep) -+{ -+ dwc_otg_dev_if_t *dev_if = _core_if->dev_if; -+ uint32_t v, msk, emp; -+ msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk); -+ emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk); -+ msk |= ((emp >> _ep->num) & 0x1) << 7; -+ v = dwc_read_reg32(&dev_if->in_ep_regs[_ep->num]->diepint) & msk; -+/* -+ dwc_otg_dev_if_t *dev_if = _core_if->dev_if; -+ uint32_t v; -+ v = dwc_read_reg32(&dev_if->in_ep_regs[_ep->num]->diepint) & -+ dwc_read_reg32(&dev_if->dev_global_regs->diepmsk); -+*/ -+ return v; -+} -+/** -+ * This function returns the Device OUT EP Interrupt register -+ */ -+static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *_core_if, -+ dwc_ep_t *_ep) -+{ -+ dwc_otg_dev_if_t *dev_if = _core_if->dev_if; -+ uint32_t v; -+ v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) & -+ dwc_read_reg32(&dev_if->dev_global_regs->doepmsk); -+ return v; -+} -+ -+/** -+ * This function returns the Host All Channel Interrupt register -+ */ -+static inline uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if) -+{ -+ return (dwc_read_reg32 (&_core_if->host_if->host_global_regs->haint)); -+} -+ -+static inline uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) -+{ -+ return (dwc_read_reg32 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint)); -+} -+ -+ -+/** -+ * This function returns the mode of the operation, host or device. -+ * -+ * @return 0 - Device Mode, 1 - Host Mode -+ */ -+static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t *_core_if) { -+ return (dwc_read_reg32( &_core_if->core_global_regs->gintsts ) & 0x1); -+} -+ -+static inline uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t *_core_if) -+{ -+ return (dwc_otg_mode(_core_if) != DWC_HOST_MODE); -+} -+static inline uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t *_core_if) -+{ -+ return (dwc_otg_mode(_core_if) == DWC_HOST_MODE); -+} -+ -+extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if ); -+ -+ -+/**@}*/ -+ -+/** -+ * DWC_otg CIL callback structure. This structure allows the HCD and -+ * PCD to register functions used for starting and stopping the PCD -+ * and HCD for role change on for a DRD. -+ */ -+typedef struct dwc_otg_cil_callbacks -+{ -+ /** Start function for role change */ -+ int (*start) (void *_p); -+ /** Stop Function for role change */ -+ int (*stop) (void *_p); -+ /** Disconnect Function for role change */ -+ int (*disconnect) (void *_p); -+ /** Resume/Remote wakeup Function */ -+ int (*resume_wakeup) (void *_p); -+ /** Suspend function */ -+ int (*suspend) (void *_p); -+ /** Session Start (SRP) */ -+ int (*session_start) (void *_p); -+ /** Pointer passed to start() and stop() */ -+ void *p; -+} dwc_otg_cil_callbacks_t; -+ -+ -+ -+extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if, -+ dwc_otg_cil_callbacks_t *_cb, -+ void *_p); -+extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if, -+ dwc_otg_cil_callbacks_t *_cb, -+ void *_p); -+ -+ -+#endif ---- /dev/null -+++ b/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h -@@ -0,0 +1,58 @@ -+/****************************************************************************** -+** -+** FILE NAME : dwc_otg_cil_ifx.h -+** PROJECT : Twinpass/Danube -+** MODULES : DWC OTG USB -+** -+** DATE : 07 Sep. 2007 -+** AUTHOR : Sung Winder -+** DESCRIPTION : Default param value. -+** COPYRIGHT : Copyright (c) 2007 -+** Infineon Technologies AG -+** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park, -+** Hsin-chu City, 300 Taiwan. -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 12 April 2007 Sung Winder Initiate Version -+*******************************************************************************/ -+#if !defined(__DWC_OTG_CIL_IFX_H__) -+#define __DWC_OTG_CIL_IFX_H__ -+ -+/* ================ Default param value ================== */ -+#define dwc_param_opt_default 1 -+#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE -+#define dwc_param_dma_enable_default 1 -+#define dwc_param_dma_burst_size_default 32 -+#define dwc_param_speed_default DWC_SPEED_PARAM_HIGH -+#define dwc_param_host_support_fs_ls_low_power_default 0 -+#define dwc_param_host_ls_low_power_phy_clk_default DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ -+#define dwc_param_enable_dynamic_fifo_default 1 -+#define dwc_param_data_fifo_size_default 2048 -+#define dwc_param_dev_rx_fifo_size_default 1024 -+#define dwc_param_dev_nperio_tx_fifo_size_default 1024 -+#define dwc_param_dev_perio_tx_fifo_size_default 768 -+#define dwc_param_host_rx_fifo_size_default 640 -+#define dwc_param_host_nperio_tx_fifo_size_default 640 -+#define dwc_param_host_perio_tx_fifo_size_default 768 -+#define dwc_param_max_transfer_size_default 65535 -+#define dwc_param_max_packet_count_default 511 -+#define dwc_param_host_channels_default 16 -+#define dwc_param_dev_endpoints_default 6 -+#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI -+#define dwc_param_phy_utmi_width_default 16 -+#define dwc_param_phy_ulpi_ddr_default 0 -+#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS -+#define dwc_param_i2c_enable_default 0 -+#define dwc_param_ulpi_fs_ls_default 0 -+#define dwc_param_ts_dline_default 0 -+ -+/* ======================================================= */ -+ -+#endif // __DWC_OTG_CIL_IFX_H__ -+ ---- /dev/null -+++ b/drivers/usb/dwc_otg/dwc_otg_cil_intr.c -@@ -0,0 +1,708 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil_intr.c $ -+ * $Revision: 1.1.1.1 $ -+ * $Date: 2009-04-17 06:15:34 $ -+ * $Change: 553126 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+/** @file -+ * -+ * The Core Interface Layer provides basic services for accessing and -+ * managing the DWC_otg hardware. These services are used by both the -+ * Host Controller Driver and the Peripheral Controller Driver. -+ * -+ * This file contains the Common Interrupt handlers. -+ */ -+#include "dwc_otg_plat.h" -+#include "dwc_otg_regs.h" -+#include "dwc_otg_cil.h" -+ -+#ifdef DEBUG -+inline const char *op_state_str( dwc_otg_core_if_t *_core_if ) -+{ -+ return (_core_if->op_state==A_HOST?"a_host": -+ (_core_if->op_state==A_SUSPEND?"a_suspend": -+ (_core_if->op_state==A_PERIPHERAL?"a_peripheral": -+ (_core_if->op_state==B_PERIPHERAL?"b_peripheral": -+ (_core_if->op_state==B_HOST?"b_host": -+ "unknown"))))); -+} -+#endif -+ -+/** This function will log a debug message -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ */ -+int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *_core_if) -+{ -+ gintsts_data_t gintsts; -+ DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n", -+ dwc_otg_mode(_core_if) ? "Host" : "Device"); -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.modemismatch = 1; -+ dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32); -+ return 1; -+} -+ -+/** Start the HCD. Helper function for using the HCD callbacks. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ */ -+static inline void hcd_start( dwc_otg_core_if_t *_core_if ) -+{ -+ if (_core_if->hcd_cb && _core_if->hcd_cb->start) { -+ _core_if->hcd_cb->start( _core_if->hcd_cb->p ); -+ } -+} -+/** Stop the HCD. Helper function for using the HCD callbacks. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ */ -+static inline void hcd_stop( dwc_otg_core_if_t *_core_if ) -+{ -+ if (_core_if->hcd_cb && _core_if->hcd_cb->stop) { -+ _core_if->hcd_cb->stop( _core_if->hcd_cb->p ); -+ } -+} -+/** Disconnect the HCD. Helper function for using the HCD callbacks. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ */ -+static inline void hcd_disconnect( dwc_otg_core_if_t *_core_if ) -+{ -+ if (_core_if->hcd_cb && _core_if->hcd_cb->disconnect) { -+ _core_if->hcd_cb->disconnect( _core_if->hcd_cb->p ); -+ } -+} -+/** Inform the HCD the a New Session has begun. Helper function for -+ * using the HCD callbacks. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ */ -+static inline void hcd_session_start( dwc_otg_core_if_t *_core_if ) -+{ -+ if (_core_if->hcd_cb && _core_if->hcd_cb->session_start) { -+ _core_if->hcd_cb->session_start( _core_if->hcd_cb->p ); -+ } -+} -+ -+/** Start the PCD. Helper function for using the PCD callbacks. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ */ -+static inline void pcd_start( dwc_otg_core_if_t *_core_if ) -+{ -+ if (_core_if->pcd_cb && _core_if->pcd_cb->start ) { -+ _core_if->pcd_cb->start( _core_if->pcd_cb->p ); -+ } -+} -+/** Stop the PCD. Helper function for using the PCD callbacks. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ */ -+static inline void pcd_stop( dwc_otg_core_if_t *_core_if ) -+{ -+ if (_core_if->pcd_cb && _core_if->pcd_cb->stop ) { -+ _core_if->pcd_cb->stop( _core_if->pcd_cb->p ); -+ } -+} -+/** Suspend the PCD. Helper function for using the PCD callbacks. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ */ -+static inline void pcd_suspend( dwc_otg_core_if_t *_core_if ) -+{ -+ if (_core_if->pcd_cb && _core_if->pcd_cb->suspend ) { -+ _core_if->pcd_cb->suspend( _core_if->pcd_cb->p ); -+ } -+} -+/** Resume the PCD. Helper function for using the PCD callbacks. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ */ -+static inline void pcd_resume( dwc_otg_core_if_t *_core_if ) -+{ -+ if (_core_if->pcd_cb && _core_if->pcd_cb->resume_wakeup ) { -+ _core_if->pcd_cb->resume_wakeup( _core_if->pcd_cb->p ); -+ } -+} -+ -+/** -+ * This function handles the OTG Interrupts. It reads the OTG -+ * Interrupt Register (GOTGINT) to determine what interrupt has -+ * occurred. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ */ -+int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t *_core_if) -+{ -+ dwc_otg_core_global_regs_t *global_regs = -+ _core_if->core_global_regs; -+ gotgint_data_t gotgint; -+ gotgctl_data_t gotgctl; -+ gintmsk_data_t gintmsk; -+ -+ gotgint.d32 = dwc_read_reg32( &global_regs->gotgint); -+ gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl); -+ DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32, -+ op_state_str(_core_if)); -+ //DWC_DEBUGPL(DBG_CIL, "gotgctl=%08x\n", gotgctl.d32 ); -+ -+ if (gotgint.b.sesenddet) { -+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " -+ "Session End Detected++ (%s)\n", -+ op_state_str(_core_if)); -+ gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl); -+ -+ if (_core_if->op_state == B_HOST) { -+ pcd_start( _core_if ); -+ _core_if->op_state = B_PERIPHERAL; -+ } else { -+ /* If not B_HOST and Device HNP still set. HNP -+ * Did not succeed!*/ -+ if (gotgctl.b.devhnpen) { -+ DWC_DEBUGPL(DBG_ANY, "Session End Detected\n"); -+ DWC_ERROR( "Device Not Connected/Responding!\n" ); -+ } -+ -+ /* If Session End Detected the B-Cable has -+ * been disconnected. */ -+ /* Reset PCD and Gadget driver to a -+ * clean state. */ -+ pcd_stop(_core_if); -+ } -+ gotgctl.d32 = 0; -+ gotgctl.b.devhnpen = 1; -+ dwc_modify_reg32( &global_regs->gotgctl, -+ gotgctl.d32, 0); -+ } -+ if (gotgint.b.sesreqsucstschng) { -+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " -+ "Session Reqeust Success Status Change++\n"); -+ gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl); -+ if (gotgctl.b.sesreqscs) { -+ if ((_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) && -+ (_core_if->core_params->i2c_enable)) { -+ _core_if->srp_success = 1; -+ } -+ else { -+ pcd_resume( _core_if ); -+ /* Clear Session Request */ -+ gotgctl.d32 = 0; -+ gotgctl.b.sesreq = 1; -+ dwc_modify_reg32( &global_regs->gotgctl, -+ gotgctl.d32, 0); -+ } -+ } -+ } -+ if (gotgint.b.hstnegsucstschng) { -+ /* Print statements during the HNP interrupt handling -+ * can cause it to fail.*/ -+ gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); -+ if (gotgctl.b.hstnegscs) { -+ if (dwc_otg_is_host_mode(_core_if) ) { -+ _core_if->op_state = B_HOST; -+ /* -+ * Need to disable SOF interrupt immediately. -+ * When switching from device to host, the PCD -+ * interrupt handler won't handle the -+ * interrupt if host mode is already set. The -+ * HCD interrupt handler won't get called if -+ * the HCD state is HALT. This means that the -+ * interrupt does not get handled and Linux -+ * complains loudly. -+ */ -+ gintmsk.d32 = 0; -+ gintmsk.b.sofintr = 1; -+ dwc_modify_reg32(&global_regs->gintmsk, -+ gintmsk.d32, 0); -+ pcd_stop(_core_if); -+ /* -+ * Initialize the Core for Host mode. -+ */ -+ hcd_start( _core_if ); -+ _core_if->op_state = B_HOST; -+ } -+ } else { -+ gotgctl.d32 = 0; -+ gotgctl.b.hnpreq = 1; -+ gotgctl.b.devhnpen = 1; -+ dwc_modify_reg32( &global_regs->gotgctl, -+ gotgctl.d32, 0); -+ DWC_DEBUGPL( DBG_ANY, "HNP Failed\n"); -+ DWC_ERROR( "Device Not Connected/Responding\n" ); -+ } -+ } -+ if (gotgint.b.hstnegdet) { -+ /* The disconnect interrupt is set at the same time as -+ * Host Negotiation Detected. During the mode -+ * switch all interrupts are cleared so the disconnect -+ * interrupt handler will not get executed. -+ */ -+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " -+ "Host Negotiation Detected++ (%s)\n", -+ (dwc_otg_is_host_mode(_core_if)?"Host":"Device")); -+ if (dwc_otg_is_device_mode(_core_if)){ -+ DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",_core_if->op_state); -+ hcd_disconnect( _core_if ); -+ pcd_start( _core_if ); -+ _core_if->op_state = A_PERIPHERAL; -+ } else { -+ /* -+ * Need to disable SOF interrupt immediately. When -+ * switching from device to host, the PCD interrupt -+ * handler won't handle the interrupt if host mode is -+ * already set. The HCD interrupt handler won't get -+ * called if the HCD state is HALT. This means that -+ * the interrupt does not get handled and Linux -+ * complains loudly. -+ */ -+ gintmsk.d32 = 0; -+ gintmsk.b.sofintr = 1; -+ dwc_modify_reg32(&global_regs->gintmsk, -+ gintmsk.d32, 0); -+ pcd_stop( _core_if ); -+ hcd_start( _core_if ); -+ _core_if->op_state = A_HOST; -+ } -+ } -+ if (gotgint.b.adevtoutchng) { -+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " -+ "A-Device Timeout Change++\n"); -+ } -+ if (gotgint.b.debdone) { -+ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " -+ "Debounce Done++\n"); -+ } -+ -+ /* Clear GOTGINT */ -+ dwc_write_reg32 (&_core_if->core_global_regs->gotgint, gotgint.d32); -+ -+ return 1; -+} -+ -+/** -+ * This function handles the Connector ID Status Change Interrupt. It -+ * reads the OTG Interrupt Register (GOTCTL) to determine whether this -+ * is a Device to Host Mode transition or a Host Mode to Device -+ * Transition. -+ * -+ * This only occurs when the cable is connected/removed from the PHY -+ * connector. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ */ -+int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t *_core_if) -+{ -+ uint32_t count = 0; -+ -+ gintsts_data_t gintsts = { .d32 = 0 }; -+ gintmsk_data_t gintmsk = { .d32 = 0 }; -+ gotgctl_data_t gotgctl = { .d32 = 0 }; -+ -+ /* -+ * Need to disable SOF interrupt immediately. If switching from device -+ * to host, the PCD interrupt handler won't handle the interrupt if -+ * host mode is already set. The HCD interrupt handler won't get -+ * called if the HCD state is HALT. This means that the interrupt does -+ * not get handled and Linux complains loudly. -+ */ -+ gintmsk.b.sofintr = 1; -+ dwc_modify_reg32(&_core_if->core_global_regs->gintmsk, gintmsk.d32, 0); -+ -+ DWC_DEBUGPL(DBG_CIL, " ++Connector ID Status Change Interrupt++ (%s)\n", -+ (dwc_otg_is_host_mode(_core_if)?"Host":"Device")); -+ gotgctl.d32 = dwc_read_reg32(&_core_if->core_global_regs->gotgctl); -+ DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32); -+ DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts); -+ -+ /* B-Device connector (Device Mode) */ -+ if (gotgctl.b.conidsts) { -+ /* Wait for switch to device mode. */ -+ while (!dwc_otg_is_device_mode(_core_if) ){ -+ DWC_PRINT("Waiting for Peripheral Mode, Mode=%s\n", -+ (dwc_otg_is_host_mode(_core_if)?"Host":"Peripheral")); -+ MDELAY(100); -+ if (++count > 10000) *(uint32_t*)NULL=0; -+ } -+ _core_if->op_state = B_PERIPHERAL; -+ dwc_otg_core_init(_core_if); -+ dwc_otg_enable_global_interrupts(_core_if); -+ pcd_start( _core_if ); -+ } else { -+ /* A-Device connector (Host Mode) */ -+ while (!dwc_otg_is_host_mode(_core_if) ) { -+ DWC_PRINT("Waiting for Host Mode, Mode=%s\n", -+ (dwc_otg_is_host_mode(_core_if)?"Host":"Peripheral")); -+ MDELAY(100); -+ if (++count > 10000) *(uint32_t*)NULL=0; -+ } -+ _core_if->op_state = A_HOST; -+ /* -+ * Initialize the Core for Host mode. -+ */ -+ dwc_otg_core_init(_core_if); -+ dwc_otg_enable_global_interrupts(_core_if); -+ hcd_start( _core_if ); -+ } -+ -+ /* Set flag and clear interrupt */ -+ gintsts.b.conidstschng = 1; -+ dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32); -+ -+ return 1; -+} -+ -+/** -+ * This interrupt indicates that a device is initiating the Session -+ * Request Protocol to request the host to turn on bus power so a new -+ * session can begin. The handler responds by turning on bus power. If -+ * the DWC_otg controller is in low power mode, the handler brings the -+ * controller out of low power mode before turning on bus power. -+ * -+ * @param _core_if Programming view of DWC_otg controller. -+ */ -+int32_t dwc_otg_handle_session_req_intr( dwc_otg_core_if_t *_core_if ) -+{ -+#ifndef DWC_HOST_ONLY // winder -+ hprt0_data_t hprt0; -+#endif -+ gintsts_data_t gintsts; -+ -+#ifndef DWC_HOST_ONLY -+ DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n"); -+ -+ if (dwc_otg_is_device_mode(_core_if) ) { -+ DWC_PRINT("SRP: Device mode\n"); -+ } else { -+ DWC_PRINT("SRP: Host mode\n"); -+ -+ /* Turn on the port power bit. */ -+ hprt0.d32 = dwc_otg_read_hprt0( _core_if ); -+ hprt0.b.prtpwr = 1; -+ dwc_write_reg32(_core_if->host_if->hprt0, hprt0.d32); -+ -+ /* Start the Connection timer. So a message can be displayed -+ * if connect does not occur within 10 seconds. */ -+ hcd_session_start( _core_if ); -+ } -+#endif -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.sessreqintr = 1; -+ dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32); -+ -+ return 1; -+} -+ -+/** -+ * This interrupt indicates that the DWC_otg controller has detected a -+ * resume or remote wakeup sequence. If the DWC_otg controller is in -+ * low power mode, the handler must brings the controller out of low -+ * power mode. The controller automatically begins resume -+ * signaling. The handler schedules a time to stop resume signaling. -+ */ -+int32_t dwc_otg_handle_wakeup_detected_intr( dwc_otg_core_if_t *_core_if ) -+{ -+ gintsts_data_t gintsts; -+ -+ DWC_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n"); -+ -+ if (dwc_otg_is_device_mode(_core_if) ) { -+ dctl_data_t dctl = {.d32=0}; -+ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", -+ dwc_read_reg32( &_core_if->dev_if->dev_global_regs->dsts)); -+#ifdef PARTIAL_POWER_DOWN -+ if (_core_if->hwcfg4.b.power_optimiz) { -+ pcgcctl_data_t power = {.d32=0}; -+ -+ power.d32 = dwc_read_reg32( _core_if->pcgcctl ); -+ DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", power.d32); -+ -+ power.b.stoppclk = 0; -+ dwc_write_reg32( _core_if->pcgcctl, power.d32); -+ -+ power.b.pwrclmp = 0; -+ dwc_write_reg32( _core_if->pcgcctl, power.d32); -+ -+ power.b.rstpdwnmodule = 0; -+ dwc_write_reg32( _core_if->pcgcctl, power.d32); -+ } -+#endif -+ /* Clear the Remote Wakeup Signalling */ -+ dctl.b.rmtwkupsig = 1; -+ dwc_modify_reg32( &_core_if->dev_if->dev_global_regs->dctl, -+ dctl.d32, 0 ); -+ -+ if (_core_if->pcd_cb && _core_if->pcd_cb->resume_wakeup) { -+ _core_if->pcd_cb->resume_wakeup( _core_if->pcd_cb->p ); -+ } -+ -+ } else { -+ /* -+ * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms -+ * so that OPT tests pass with all PHYs). -+ */ -+ hprt0_data_t hprt0 = {.d32=0}; -+ pcgcctl_data_t pcgcctl = {.d32=0}; -+ /* Restart the Phy Clock */ -+ pcgcctl.b.stoppclk = 1; -+ dwc_modify_reg32(_core_if->pcgcctl, pcgcctl.d32, 0); -+ UDELAY(10); -+ -+ /* Now wait for 70 ms. */ -+ hprt0.d32 = dwc_otg_read_hprt0( _core_if ); -+ DWC_DEBUGPL(DBG_ANY,"Resume: HPRT0=%0x\n", hprt0.d32); -+ MDELAY(70); -+ hprt0.b.prtres = 0; /* Resume */ -+ dwc_write_reg32(_core_if->host_if->hprt0, hprt0.d32); -+ DWC_DEBUGPL(DBG_ANY,"Clear Resume: HPRT0=%0x\n", dwc_read_reg32(_core_if->host_if->hprt0)); -+ } -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.wkupintr = 1; -+ dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32); -+ -+ return 1; -+} -+ -+/** -+ * This interrupt indicates that a device has been disconnected from -+ * the root port. -+ */ -+int32_t dwc_otg_handle_disconnect_intr( dwc_otg_core_if_t *_core_if) -+{ -+ gintsts_data_t gintsts; -+ -+ DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n", -+ (dwc_otg_is_host_mode(_core_if)?"Host":"Device"), -+ op_state_str(_core_if)); -+ -+/** @todo Consolidate this if statement. */ -+#ifndef DWC_HOST_ONLY -+ if (_core_if->op_state == B_HOST) { -+ /* If in device mode Disconnect and stop the HCD, then -+ * start the PCD. */ -+ hcd_disconnect( _core_if ); -+ pcd_start( _core_if ); -+ _core_if->op_state = B_PERIPHERAL; -+ } else if (dwc_otg_is_device_mode(_core_if)) { -+ gotgctl_data_t gotgctl = { .d32 = 0 }; -+ gotgctl.d32 = dwc_read_reg32(&_core_if->core_global_regs->gotgctl); -+ if (gotgctl.b.hstsethnpen==1) { -+ /* Do nothing, if HNP in process the OTG -+ * interrupt "Host Negotiation Detected" -+ * interrupt will do the mode switch. -+ */ -+ } else if (gotgctl.b.devhnpen == 0) { -+ /* If in device mode Disconnect and stop the HCD, then -+ * start the PCD. */ -+ hcd_disconnect( _core_if ); -+ pcd_start( _core_if ); -+ _core_if->op_state = B_PERIPHERAL; -+ } else { -+ DWC_DEBUGPL(DBG_ANY,"!a_peripheral && !devhnpen\n"); -+ } -+ } else { -+ if (_core_if->op_state == A_HOST) { -+ /* A-Cable still connected but device disconnected. */ -+ hcd_disconnect( _core_if ); -+ } -+ } -+#endif -+/* Without OTG, we should use the disconnect function!? winder added.*/ -+#if 1 // NO OTG, so host only!! -+ hcd_disconnect( _core_if ); -+#endif -+ -+ gintsts.d32 = 0; -+ gintsts.b.disconnect = 1; -+ dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32); -+ return 1; -+} -+/** -+ * This interrupt indicates that SUSPEND state has been detected on -+ * the USB. -+ * -+ * For HNP the USB Suspend interrupt signals the change from -+ * "a_peripheral" to "a_host". -+ * -+ * When power management is enabled the core will be put in low power -+ * mode. -+ */ -+int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t *_core_if ) -+{ -+ dsts_data_t dsts; -+ gintsts_data_t gintsts; -+ -+ //805141:.removed DWC_DEBUGPL(DBG_ANY,"USB SUSPEND\n"); -+ -+ if (dwc_otg_is_device_mode( _core_if ) ) { -+ /* Check the Device status register to determine if the Suspend -+ * state is active. */ -+ dsts.d32 = dwc_read_reg32( &_core_if->dev_if->dev_global_regs->dsts); -+ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32); -+ DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d " -+ "HWCFG4.power Optimize=%d\n", -+ dsts.b.suspsts, _core_if->hwcfg4.b.power_optimiz); -+ -+ -+#ifdef PARTIAL_POWER_DOWN -+/** @todo Add a module parameter for power management. */ -+ -+ if (dsts.b.suspsts && _core_if->hwcfg4.b.power_optimiz) { -+ pcgcctl_data_t power = {.d32=0}; -+ DWC_DEBUGPL(DBG_CIL, "suspend\n"); -+ -+ power.b.pwrclmp = 1; -+ dwc_write_reg32( _core_if->pcgcctl, power.d32); -+ -+ power.b.rstpdwnmodule = 1; -+ dwc_modify_reg32( _core_if->pcgcctl, 0, power.d32); -+ -+ power.b.stoppclk = 1; -+ dwc_modify_reg32( _core_if->pcgcctl, 0, power.d32); -+ -+ } else { -+ DWC_DEBUGPL(DBG_ANY,"disconnect?\n"); -+ } -+#endif -+ /* PCD callback for suspend. */ -+ pcd_suspend(_core_if); -+ } else { -+ if (_core_if->op_state == A_PERIPHERAL) { -+ DWC_DEBUGPL(DBG_ANY,"a_peripheral->a_host\n"); -+ /* Clear the a_peripheral flag, back to a_host. */ -+ pcd_stop( _core_if ); -+ hcd_start( _core_if ); -+ _core_if->op_state = A_HOST; -+ } -+ } -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.usbsuspend = 1; -+ dwc_write_reg32( &_core_if->core_global_regs->gintsts, gintsts.d32); -+ -+ return 1; -+} -+ -+ -+/** -+ * This function returns the Core Interrupt register. -+ */ -+static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t *_core_if) -+{ -+ gintsts_data_t gintsts; -+ gintmsk_data_t gintmsk; -+ gintmsk_data_t gintmsk_common = {.d32=0}; -+ gintmsk_common.b.wkupintr = 1; -+ gintmsk_common.b.sessreqintr = 1; -+ gintmsk_common.b.conidstschng = 1; -+ gintmsk_common.b.otgintr = 1; -+ gintmsk_common.b.modemismatch = 1; -+ gintmsk_common.b.disconnect = 1; -+ gintmsk_common.b.usbsuspend = 1; -+ /** @todo: The port interrupt occurs while in device -+ * mode. Added code to CIL to clear the interrupt for now! -+ */ -+ gintmsk_common.b.portintr = 1; -+ -+ gintsts.d32 = dwc_read_reg32(&_core_if->core_global_regs->gintsts); -+ gintmsk.d32 = dwc_read_reg32(&_core_if->core_global_regs->gintmsk); -+#ifdef DEBUG -+ /* if any common interrupts set */ -+ if (gintsts.d32 & gintmsk_common.d32) { -+ DWC_DEBUGPL(DBG_ANY, "gintsts=%08x gintmsk=%08x\n", -+ gintsts.d32, gintmsk.d32); -+ } -+#endif -+ -+ return ((gintsts.d32 & gintmsk.d32 ) & gintmsk_common.d32); -+ -+} -+ -+/** -+ * Common interrupt handler. -+ * -+ * The common interrupts are those that occur in both Host and Device mode. -+ * This handler handles the following interrupts: -+ * - Mode Mismatch Interrupt -+ * - Disconnect Interrupt -+ * - OTG Interrupt -+ * - Connector ID Status Change Interrupt -+ * - Session Request Interrupt. -+ * - Resume / Remote Wakeup Detected Interrupt. -+ * -+ */ -+extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if ) -+{ -+ int retval = 0; -+ gintsts_data_t gintsts; -+ -+ gintsts.d32 = dwc_otg_read_common_intr(_core_if); -+ -+ if (gintsts.b.modemismatch) { -+ retval |= dwc_otg_handle_mode_mismatch_intr( _core_if ); -+ } -+ if (gintsts.b.otgintr) { -+ retval |= dwc_otg_handle_otg_intr( _core_if ); -+ } -+ if (gintsts.b.conidstschng) { -+ retval |= dwc_otg_handle_conn_id_status_change_intr( _core_if ); -+ } -+ if (gintsts.b.disconnect) { -+ retval |= dwc_otg_handle_disconnect_intr( _core_if ); -+ } -+ if (gintsts.b.sessreqintr) { -+ retval |= dwc_otg_handle_session_req_intr( _core_if ); -+ } -+ if (gintsts.b.wkupintr) { -+ retval |= dwc_otg_handle_wakeup_detected_intr( _core_if ); -+ } -+ if (gintsts.b.usbsuspend) { -+ retval |= dwc_otg_handle_usb_suspend_intr( _core_if ); -+ } -+ if (gintsts.b.portintr && dwc_otg_is_device_mode(_core_if)) { -+ /* The port interrupt occurs while in device mode with HPRT0 -+ * Port Enable/Disable. -+ */ -+ gintsts.d32 = 0; -+ gintsts.b.portintr = 1; -+ dwc_write_reg32(&_core_if->core_global_regs->gintsts, -+ gintsts.d32); -+ retval |= 1; -+ -+ } -+ return retval; -+} ---- /dev/null -+++ b/drivers/usb/dwc_otg/dwc_otg_driver.c -@@ -0,0 +1,1274 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.c $ -+ * $Revision: 1.1.1.1 $ -+ * $Date: 2009-04-17 06:15:34 $ -+ * $Change: 631780 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+/** @file -+ * The dwc_otg_driver module provides the initialization and cleanup entry -+ * points for the DWC_otg driver. This module will be dynamically installed -+ * after Linux is booted using the insmod command. When the module is -+ * installed, the dwc_otg_init function is called. When the module is -+ * removed (using rmmod), the dwc_otg_cleanup function is called. -+ * -+ * This module also defines a data structure for the dwc_otg_driver, which is -+ * used in conjunction with the standard ARM lm_device structure. These -+ * structures allow the OTG driver to comply with the standard Linux driver -+ * model in which devices and drivers are registered with a bus driver. This -+ * has the benefit that Linux can expose attributes of the driver and device -+ * in its special sysfs file system. Users can then read or write files in -+ * this file system to perform diagnostics on the driver components or the -+ * device. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+#include -+#include /* permission constants */ -+#include -+#include -+ -+#include "dwc_otg_plat.h" -+#include "dwc_otg_attr.h" -+#include "dwc_otg_driver.h" -+#include "dwc_otg_cil.h" -+#include "dwc_otg_cil_ifx.h" -+ -+// #include "dwc_otg_pcd.h" // device -+#include "dwc_otg_hcd.h" // host -+ -+#include "dwc_otg_ifx.h" // for Infineon platform specific. -+ -+#define DWC_DRIVER_VERSION "2.60a 22-NOV-2006" -+#define DWC_DRIVER_DESC "HS OTG USB Controller driver" -+ -+const char dwc_driver_name[] = "dwc_otg"; -+ -+static unsigned long dwc_iomem_base = IFX_USB_IOMEM_BASE; -+int dwc_irq = LTQ_USB_INT; -+//int dwc_irq = 54; -+//int dwc_irq = IFXMIPS_USB_OC_INT; -+ -+extern int ifx_usb_hc_init(unsigned long base_addr, int irq); -+extern void ifx_usb_hc_remove(void); -+ -+/*-------------------------------------------------------------------------*/ -+/* Encapsulate the module parameter settings */ -+ -+static dwc_otg_core_params_t dwc_otg_module_params = { -+ .opt = -1, -+ .otg_cap = -1, -+ .dma_enable = -1, -+ .dma_burst_size = -1, -+ .speed = -1, -+ .host_support_fs_ls_low_power = -1, -+ .host_ls_low_power_phy_clk = -1, -+ .enable_dynamic_fifo = -1, -+ .data_fifo_size = -1, -+ .dev_rx_fifo_size = -1, -+ .dev_nperio_tx_fifo_size = -1, -+ .dev_perio_tx_fifo_size = /* dev_perio_tx_fifo_size_1 */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 15 */ -+ .host_rx_fifo_size = -1, -+ .host_nperio_tx_fifo_size = -1, -+ .host_perio_tx_fifo_size = -1, -+ .max_transfer_size = -1, -+ .max_packet_count = -1, -+ .host_channels = -1, -+ .dev_endpoints = -1, -+ .phy_type = -1, -+ .phy_utmi_width = -1, -+ .phy_ulpi_ddr = -1, -+ .phy_ulpi_ext_vbus = -1, -+ .i2c_enable = -1, -+ .ulpi_fs_ls = -1, -+ .ts_dline = -1, -+ .en_multiple_tx_fifo = -1, -+ .dev_tx_fifo_size = { /* dev_tx_fifo_size */ -+ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 -+ }, /* 15 */ -+ .thr_ctl = -1, -+ .tx_thr_length = -1, -+ .rx_thr_length = -1, -+}; -+ -+/** -+ * This function shows the Driver Version. -+ */ -+static ssize_t version_show(struct device_driver *dev, char *buf) -+{ -+ return snprintf(buf, sizeof(DWC_DRIVER_VERSION)+2,"%s\n", -+ DWC_DRIVER_VERSION); -+} -+static DRIVER_ATTR(version, S_IRUGO, version_show, NULL); -+ -+/** -+ * Global Debug Level Mask. -+ */ -+uint32_t g_dbg_lvl = 0xff; /* OFF */ -+ -+/** -+ * This function shows the driver Debug Level. -+ */ -+static ssize_t dbg_level_show(struct device_driver *_drv, char *_buf) -+{ -+ return sprintf(_buf, "0x%0x\n", g_dbg_lvl); -+} -+/** -+ * This function stores the driver Debug Level. -+ */ -+static ssize_t dbg_level_store(struct device_driver *_drv, const char *_buf, -+ size_t _count) -+{ -+ g_dbg_lvl = simple_strtoul(_buf, NULL, 16); -+ return _count; -+} -+static DRIVER_ATTR(debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store); -+ -+/** -+ * This function is called during module intialization to verify that -+ * the module parameters are in a valid state. -+ */ -+static int check_parameters(dwc_otg_core_if_t *core_if) -+{ -+ int i; -+ int retval = 0; -+ -+/* Checks if the parameter is outside of its valid range of values */ -+#define DWC_OTG_PARAM_TEST(_param_,_low_,_high_) \ -+ ((dwc_otg_module_params._param_ < (_low_)) || \ -+ (dwc_otg_module_params._param_ > (_high_))) -+ -+/* If the parameter has been set by the user, check that the parameter value is -+ * within the value range of values. If not, report a module error. */ -+#define DWC_OTG_PARAM_ERR(_param_,_low_,_high_,_string_) \ -+ do { \ -+ if (dwc_otg_module_params._param_ != -1) { \ -+ if (DWC_OTG_PARAM_TEST(_param_,(_low_),(_high_))) { \ -+ DWC_ERROR("`%d' invalid for parameter `%s'\n", \ -+ dwc_otg_module_params._param_, _string_); \ -+ dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \ -+ retval ++; \ -+ } \ -+ } \ -+ } while (0) -+ -+ DWC_OTG_PARAM_ERR(opt,0,1,"opt"); -+ DWC_OTG_PARAM_ERR(otg_cap,0,2,"otg_cap"); -+ DWC_OTG_PARAM_ERR(dma_enable,0,1,"dma_enable"); -+ DWC_OTG_PARAM_ERR(speed,0,1,"speed"); -+ DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power,0,1,"host_support_fs_ls_low_power"); -+ DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk,0,1,"host_ls_low_power_phy_clk"); -+ DWC_OTG_PARAM_ERR(enable_dynamic_fifo,0,1,"enable_dynamic_fifo"); -+ DWC_OTG_PARAM_ERR(data_fifo_size,32,32768,"data_fifo_size"); -+ DWC_OTG_PARAM_ERR(dev_rx_fifo_size,16,32768,"dev_rx_fifo_size"); -+ DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size,16,32768,"dev_nperio_tx_fifo_size"); -+ DWC_OTG_PARAM_ERR(host_rx_fifo_size,16,32768,"host_rx_fifo_size"); -+ DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size,16,32768,"host_nperio_tx_fifo_size"); -+ DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size,16,32768,"host_perio_tx_fifo_size"); -+ DWC_OTG_PARAM_ERR(max_transfer_size,2047,524288,"max_transfer_size"); -+ DWC_OTG_PARAM_ERR(max_packet_count,15,511,"max_packet_count"); -+ DWC_OTG_PARAM_ERR(host_channels,1,16,"host_channels"); -+ DWC_OTG_PARAM_ERR(dev_endpoints,1,15,"dev_endpoints"); -+ DWC_OTG_PARAM_ERR(phy_type,0,2,"phy_type"); -+ DWC_OTG_PARAM_ERR(phy_ulpi_ddr,0,1,"phy_ulpi_ddr"); -+ DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus,0,1,"phy_ulpi_ext_vbus"); -+ DWC_OTG_PARAM_ERR(i2c_enable,0,1,"i2c_enable"); -+ DWC_OTG_PARAM_ERR(ulpi_fs_ls,0,1,"ulpi_fs_ls"); -+ DWC_OTG_PARAM_ERR(ts_dline,0,1,"ts_dline"); -+ -+ if (dwc_otg_module_params.dma_burst_size != -1) { -+ if (DWC_OTG_PARAM_TEST(dma_burst_size,1,1) && -+ DWC_OTG_PARAM_TEST(dma_burst_size,4,4) && -+ DWC_OTG_PARAM_TEST(dma_burst_size,8,8) && -+ DWC_OTG_PARAM_TEST(dma_burst_size,16,16) && -+ DWC_OTG_PARAM_TEST(dma_burst_size,32,32) && -+ DWC_OTG_PARAM_TEST(dma_burst_size,64,64) && -+ DWC_OTG_PARAM_TEST(dma_burst_size,128,128) && -+ DWC_OTG_PARAM_TEST(dma_burst_size,256,256)) -+ { -+ DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n", -+ dwc_otg_module_params.dma_burst_size); -+ dwc_otg_module_params.dma_burst_size = 32; -+ retval ++; -+ } -+ } -+ -+ if (dwc_otg_module_params.phy_utmi_width != -1) { -+ if (DWC_OTG_PARAM_TEST(phy_utmi_width,8,8) && -+ DWC_OTG_PARAM_TEST(phy_utmi_width,16,16)) -+ { -+ DWC_ERROR("`%d' invalid for parameter `phy_utmi_width'\n", -+ dwc_otg_module_params.phy_utmi_width); -+ //dwc_otg_module_params.phy_utmi_width = 16; -+ dwc_otg_module_params.phy_utmi_width = 8; -+ retval ++; -+ } -+ } -+ -+ for (i=0; i<15; i++) { -+ /** @todo should be like above */ -+ //DWC_OTG_PARAM_ERR(dev_perio_tx_fifo_size[i],4,768,"dev_perio_tx_fifo_size"); -+ if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) { -+ if (DWC_OTG_PARAM_TEST(dev_perio_tx_fifo_size[i],4,768)) { -+ DWC_ERROR("`%d' invalid for parameter `%s_%d'\n", -+ dwc_otg_module_params.dev_perio_tx_fifo_size[i], "dev_perio_tx_fifo_size", i); -+ dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default; -+ retval ++; -+ } -+ } -+ } -+ -+ DWC_OTG_PARAM_ERR(en_multiple_tx_fifo, 0, 1, "en_multiple_tx_fifo"); -+ for (i = 0; i < 15; i++) { -+ /** @todo should be like above */ -+ //DWC_OTG_PARAM_ERR(dev_tx_fifo_size[i],4,768,"dev_tx_fifo_size"); -+ if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) { -+ if (DWC_OTG_PARAM_TEST(dev_tx_fifo_size[i], 4, 768)) { -+ DWC_ERROR("`%d' invalid for parameter `%s_%d'\n", -+ dwc_otg_module_params.dev_tx_fifo_size[i], -+ "dev_tx_fifo_size", i); -+ dwc_otg_module_params.dev_tx_fifo_size[i] = -+ dwc_param_dev_tx_fifo_size_default; -+ retval++; -+ } -+ } -+ } -+ DWC_OTG_PARAM_ERR(thr_ctl, 0, 7, "thr_ctl"); -+ DWC_OTG_PARAM_ERR(tx_thr_length, 8, 128, "tx_thr_length"); -+ DWC_OTG_PARAM_ERR(rx_thr_length, 8, 128, "rx_thr_length"); -+ -+ /* At this point, all module parameters that have been set by the user -+ * are valid, and those that have not are left unset. Now set their -+ * default values and/or check the parameters against the hardware -+ * configurations of the OTG core. */ -+ -+ -+ -+/* This sets the parameter to the default value if it has not been set by the -+ * user */ -+#define DWC_OTG_PARAM_SET_DEFAULT(_param_) \ -+ ({ \ -+ int changed = 1; \ -+ if (dwc_otg_module_params._param_ == -1) { \ -+ changed = 0; \ -+ dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \ -+ } \ -+ changed; \ -+ }) -+ -+/* This checks the macro agains the hardware configuration to see if it is -+ * valid. It is possible that the default value could be invalid. In this -+ * case, it will report a module error if the user touched the parameter. -+ * Otherwise it will adjust the value without any error. */ -+#define DWC_OTG_PARAM_CHECK_VALID(_param_,_str_,_is_valid_,_set_valid_) \ -+ ({ \ -+ int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \ -+ int error = 0; \ -+ if (!(_is_valid_)) { \ -+ if (changed) { \ -+ DWC_ERROR("`%d' invalid for parameter `%s'. Check HW configuration.\n", dwc_otg_module_params._param_,_str_); \ -+ error = 1; \ -+ } \ -+ dwc_otg_module_params._param_ = (_set_valid_); \ -+ } \ -+ error; \ -+ }) -+ -+ /* OTG Cap */ -+ retval += DWC_OTG_PARAM_CHECK_VALID(otg_cap,"otg_cap", -+ ({ -+ int valid; -+ valid = 1; -+ switch (dwc_otg_module_params.otg_cap) { -+ case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE: -+ if (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) valid = 0; -+ break; -+ case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE: -+ if ((core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) && -+ (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) && -+ (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) && -+ (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) -+ { -+ valid = 0; -+ } -+ break; -+ case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE: -+ /* always valid */ -+ break; -+ } -+ valid; -+ }), -+ (((core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) || -+ (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) || -+ (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) || -+ (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ? -+ DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE : -+ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE)); -+ -+ retval += DWC_OTG_PARAM_CHECK_VALID(dma_enable,"dma_enable", -+ ((dwc_otg_module_params.dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1, -+ 0); -+ -+ retval += DWC_OTG_PARAM_CHECK_VALID(opt,"opt", -+ 1, -+ 0); -+ -+ DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size); -+ -+ retval += DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power, -+ "host_support_fs_ls_low_power", -+ 1, 0); -+ -+ retval += DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo, -+ "enable_dynamic_fifo", -+ ((dwc_otg_module_params.enable_dynamic_fifo == 0) || -+ (core_if->hwcfg2.b.dynamic_fifo == 1)), 0); -+ -+ -+ retval += DWC_OTG_PARAM_CHECK_VALID(data_fifo_size, -+ "data_fifo_size", -+ (dwc_otg_module_params.data_fifo_size <= core_if->hwcfg3.b.dfifo_depth), -+ core_if->hwcfg3.b.dfifo_depth); -+ -+ retval += DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size, -+ "dev_rx_fifo_size", -+ (dwc_otg_module_params.dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)), -+ dwc_read_reg32(&core_if->core_global_regs->grxfsiz)); -+ -+ retval += DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size, -+ "dev_nperio_tx_fifo_size", -+ (dwc_otg_module_params.dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)), -+ (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)); -+ -+ retval += DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size, -+ "host_rx_fifo_size", -+ (dwc_otg_module_params.host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)), -+ dwc_read_reg32(&core_if->core_global_regs->grxfsiz)); -+ -+ -+ retval += DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size, -+ "host_nperio_tx_fifo_size", -+ (dwc_otg_module_params.host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)), -+ (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)); -+ -+ retval += DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size, -+ "host_perio_tx_fifo_size", -+ (dwc_otg_module_params.host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))), -+ ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))); -+ -+ retval += DWC_OTG_PARAM_CHECK_VALID(max_transfer_size, -+ "max_transfer_size", -+ (dwc_otg_module_params.max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))), -+ ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1)); -+ -+ retval += DWC_OTG_PARAM_CHECK_VALID(max_packet_count, -+ "max_packet_count", -+ (dwc_otg_module_params.max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))), -+ ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1)); -+ -+ retval += DWC_OTG_PARAM_CHECK_VALID(host_channels, -+ "host_channels", -+ (dwc_otg_module_params.host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)), -+ (core_if->hwcfg2.b.num_host_chan + 1)); -+ -+ retval += DWC_OTG_PARAM_CHECK_VALID(dev_endpoints, -+ "dev_endpoints", -+ (dwc_otg_module_params.dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)), -+ core_if->hwcfg2.b.num_dev_ep); -+ -+/* -+ * Define the following to disable the FS PHY Hardware checking. This is for -+ * internal testing only. -+ * -+ * #define NO_FS_PHY_HW_CHECKS -+ */ -+ -+#ifdef NO_FS_PHY_HW_CHECKS -+ retval += DWC_OTG_PARAM_CHECK_VALID(phy_type, -+ "phy_type", 1, 0); -+#else -+ retval += DWC_OTG_PARAM_CHECK_VALID(phy_type, -+ "phy_type", -+ ({ -+ int valid = 0; -+ if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_UTMI) && -+ ((core_if->hwcfg2.b.hs_phy_type == 1) || -+ (core_if->hwcfg2.b.hs_phy_type == 3))) -+ { -+ valid = 1; -+ } -+ else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_ULPI) && -+ ((core_if->hwcfg2.b.hs_phy_type == 2) || -+ (core_if->hwcfg2.b.hs_phy_type == 3))) -+ { -+ valid = 1; -+ } -+ else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) && -+ (core_if->hwcfg2.b.fs_phy_type == 1)) -+ { -+ valid = 1; -+ } -+ valid; -+ }), -+ ({ -+ int set = DWC_PHY_TYPE_PARAM_FS; -+ if (core_if->hwcfg2.b.hs_phy_type) { -+ if ((core_if->hwcfg2.b.hs_phy_type == 3) || -+ (core_if->hwcfg2.b.hs_phy_type == 1)) { -+ set = DWC_PHY_TYPE_PARAM_UTMI; -+ } -+ else { -+ set = DWC_PHY_TYPE_PARAM_ULPI; -+ } -+ } -+ set; -+ })); -+#endif -+ -+ retval += DWC_OTG_PARAM_CHECK_VALID(speed,"speed", -+ (dwc_otg_module_params.speed == 0) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1, -+ dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS ? 1 : 0); -+ -+ retval += DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk, -+ "host_ls_low_power_phy_clk", -+ ((dwc_otg_module_params.host_ls_low_power_phy_clk == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1), -+ ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)); -+ -+ DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr); -+ DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus); -+ DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width); -+ DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls); -+ DWC_OTG_PARAM_SET_DEFAULT(ts_dline); -+ -+#ifdef NO_FS_PHY_HW_CHECKS -+ retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable, -+ "i2c_enable", 1, 0); -+#else -+ retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable, -+ "i2c_enable", -+ (dwc_otg_module_params.i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1, -+ 0); -+#endif -+ -+ for (i=0; i<16; i++) { -+ -+ int changed = 1; -+ int error = 0; -+ -+ if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] == -1) { -+ changed = 0; -+ dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default; -+ } -+ if (!(dwc_otg_module_params.dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) { -+ if (changed) { -+ DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_perio_tx_fifo_size[i],i); -+ error = 1; -+ } -+ dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]); -+ } -+ retval += error; -+ } -+ -+ retval += DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo, -+ "en_multiple_tx_fifo", -+ ((dwc_otg_module_params.en_multiple_tx_fifo == 1) && -+ (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1, 0); -+ -+ for (i = 0; i < 16; i++) { -+ int changed = 1; -+ int error = 0; -+ if (dwc_otg_module_params.dev_tx_fifo_size[i] == -1) { -+ changed = 0; -+ dwc_otg_module_params.dev_tx_fifo_size[i] = -+ dwc_param_dev_tx_fifo_size_default; -+ } -+ if (!(dwc_otg_module_params.dev_tx_fifo_size[i] <= -+ (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) { -+ if (changed) { -+ DWC_ERROR("%d' invalid for parameter `dev_perio_fifo_size_%d'." -+ "Check HW configuration.\n",dwc_otg_module_params.dev_tx_fifo_size[i],i); -+ error = 1; -+ } -+ dwc_otg_module_params.dev_tx_fifo_size[i] = -+ dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]); -+ } -+ retval += error; -+ } -+ DWC_OTG_PARAM_SET_DEFAULT(thr_ctl); -+ DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length); -+ DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length); -+ return retval; -+} // check_parameters -+ -+ -+/** -+ * This function is the top level interrupt handler for the Common -+ * (Device and host modes) interrupts. -+ */ -+static irqreturn_t dwc_otg_common_irq(int _irq, void *_dev) -+{ -+ dwc_otg_device_t *otg_dev = _dev; -+ int32_t retval = IRQ_NONE; -+ -+ retval = dwc_otg_handle_common_intr( otg_dev->core_if ); -+ -+ mask_and_ack_ifx_irq (_irq); -+ -+ return IRQ_RETVAL(retval); -+} -+ -+ -+/** -+ * This function is called when a DWC_OTG device is unregistered with the -+ * dwc_otg_driver. This happens, for example, when the rmmod command is -+ * executed. The device may or may not be electrically present. If it is -+ * present, the driver stops device processing. Any resources used on behalf -+ * of this device are freed. -+ * -+ * @return -+ */ -+static int -+dwc_otg_driver_remove(struct platform_device *_dev) -+{ -+ //dwc_otg_device_t *otg_dev = dev_get_drvdata(&_dev->dev); -+ dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev); -+ -+ DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev); -+ -+ if (otg_dev == NULL) { -+ /* Memory allocation for the dwc_otg_device failed. */ -+ return 0; -+ } -+ -+ /* -+ * Free the IRQ -+ */ -+ if (otg_dev->common_irq_installed) { -+ free_irq( otg_dev->irq, otg_dev ); -+ } -+ -+#ifndef DWC_DEVICE_ONLY -+ if (otg_dev->hcd != NULL) { -+ dwc_otg_hcd_remove(&_dev->dev); -+ } -+#endif -+ printk("after removehcd\n"); -+ -+// Note: Integrate HOST and DEVICE(Gadget) is not planned yet. -+#ifndef DWC_HOST_ONLY -+ if (otg_dev->pcd != NULL) { -+ dwc_otg_pcd_remove(otg_dev); -+ } -+#endif -+ if (otg_dev->core_if != NULL) { -+ dwc_otg_cil_remove( otg_dev->core_if ); -+ } -+ printk("after removecil\n"); -+ -+ /* -+ * Remove the device attributes -+ */ -+ dwc_otg_attr_remove(&_dev->dev); -+ printk("after removeattr\n"); -+ -+ /* -+ * Return the memory. -+ */ -+ if (otg_dev->base != NULL) { -+ iounmap(otg_dev->base); -+ } -+ if (otg_dev->phys_addr != 0) { -+ release_mem_region(otg_dev->phys_addr, otg_dev->base_len); -+ } -+ kfree(otg_dev); -+ -+ /* -+ * Clear the drvdata pointer. -+ */ -+ //dev_set_drvdata(&_dev->dev, 0); -+ platform_set_drvdata(_dev, 0); -+ return 0; -+} -+ -+/** -+ * This function is called when an DWC_OTG device is bound to a -+ * dwc_otg_driver. It creates the driver components required to -+ * control the device (CIL, HCD, and PCD) and it initializes the -+ * device. The driver components are stored in a dwc_otg_device -+ * structure. A reference to the dwc_otg_device is saved in the -+ * lm_device. This allows the driver to access the dwc_otg_device -+ * structure on subsequent calls to driver methods for this device. -+ * -+ * @return -+ */ -+static int __devinit -+dwc_otg_driver_probe(struct platform_device *_dev) -+{ -+ int retval = 0; -+ dwc_otg_device_t *dwc_otg_device; -+ int pin = (int)_dev->dev.platform_data; -+ int32_t snpsid; -+ struct resource *res; -+ gusbcfg_data_t usbcfg = {.d32 = 0}; -+ -+ // GPIOs -+ if(pin >= 0) -+ { -+ gpio_request(pin, "usb_power"); -+ gpio_direction_output(pin, 1); -+ gpio_set_value(pin, 1); -+ gpio_export(pin, 0); -+ } -+ dev_dbg(&_dev->dev, "dwc_otg_driver_probe (%p)\n", _dev); -+ -+ dwc_otg_device = kmalloc(sizeof(dwc_otg_device_t), GFP_KERNEL); -+ if (dwc_otg_device == 0) { -+ dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n"); -+ retval = -ENOMEM; -+ goto fail; -+ } -+ memset(dwc_otg_device, 0, sizeof(*dwc_otg_device)); -+ dwc_otg_device->reg_offset = 0xFFFFFFFF; -+ -+ /* -+ * Retrieve the memory and IRQ resources. -+ */ -+ dwc_otg_device->irq = platform_get_irq(_dev, 0); -+ if (dwc_otg_device->irq == 0) { -+ dev_err(&_dev->dev, "no device irq\n"); -+ retval = -ENODEV; -+ goto fail; -+ } -+ dev_dbg(&_dev->dev, "OTG - device irq: %d\n", dwc_otg_device->irq); -+ res = platform_get_resource(_dev, IORESOURCE_MEM, 0); -+ if (res == NULL) { -+ dev_err(&_dev->dev, "no CSR address\n"); -+ retval = -ENODEV; -+ goto fail; -+ } -+ dev_dbg(&_dev->dev, "OTG - ioresource_mem start0x%08x: end:0x%08x\n", -+ (unsigned)res->start, (unsigned)res->end); -+ dwc_otg_device->phys_addr = res->start; -+ dwc_otg_device->base_len = res->end - res->start + 1; -+ if (request_mem_region(dwc_otg_device->phys_addr, dwc_otg_device->base_len, -+ dwc_driver_name) == NULL) { -+ dev_err(&_dev->dev, "request_mem_region failed\n"); -+ retval = -EBUSY; -+ goto fail; -+ } -+ -+ /* -+ * Map the DWC_otg Core memory into virtual address space. -+ */ -+ dwc_otg_device->base = ioremap_nocache(dwc_otg_device->phys_addr, dwc_otg_device->base_len); -+ if (dwc_otg_device->base == NULL) { -+ dev_err(&_dev->dev, "ioremap() failed\n"); -+ retval = -ENOMEM; -+ goto fail; -+ } -+ dev_dbg(&_dev->dev, "mapped base=0x%08x\n", (unsigned)dwc_otg_device->base); -+ -+ /* -+ * Attempt to ensure this device is really a DWC_otg Controller. -+ * Read and verify the SNPSID register contents. The value should be -+ * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX". -+ */ -+ snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)dwc_otg_device->base + 0x40)); -+ if ((snpsid & 0xFFFFF000) != 0x4F542000) { -+ dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n", snpsid); -+ retval = -EINVAL; -+ goto fail; -+ } -+ -+ /* -+ * Initialize driver data to point to the global DWC_otg -+ * Device structure. -+ */ -+ platform_set_drvdata(_dev, dwc_otg_device); -+ dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device); -+ dwc_otg_device->core_if = dwc_otg_cil_init( dwc_otg_device->base, &dwc_otg_module_params); -+ if (dwc_otg_device->core_if == 0) { -+ dev_err(&_dev->dev, "CIL initialization failed!\n"); -+ retval = -ENOMEM; -+ goto fail; -+ } -+ -+ /* -+ * Validate parameter values. -+ */ -+ if (check_parameters(dwc_otg_device->core_if) != 0) { -+ retval = -EINVAL; -+ goto fail; -+ } -+ -+ /* Added for PLB DMA phys virt mapping */ -+ //dwc_otg_device->core_if->phys_addr = dwc_otg_device->phys_addr; -+ /* -+ * Create Device Attributes in sysfs -+ */ -+ dwc_otg_attr_create (&_dev->dev); -+ -+ /* -+ * Disable the global interrupt until all the interrupt -+ * handlers are installed. -+ */ -+ dwc_otg_disable_global_interrupts( dwc_otg_device->core_if ); -+ /* -+ * Install the interrupt handler for the common interrupts before -+ * enabling common interrupts in core_init below. -+ */ -+ DWC_DEBUGPL( DBG_CIL, "registering (common) handler for irq%d\n", dwc_otg_device->irq); -+ -+ retval = request_irq((unsigned int)dwc_otg_device->irq, dwc_otg_common_irq, -+ //SA_INTERRUPT|SA_SHIRQ, "dwc_otg", (void *)dwc_otg_device ); -+ IRQF_SHARED, "dwc_otg", (void *)dwc_otg_device ); -+ //IRQF_DISABLED, "dwc_otg", (void *)dwc_otg_device ); -+ if (retval != 0) { -+ DWC_ERROR("request of irq%d failed retval: %d\n", dwc_otg_device->irq, retval); -+ retval = -EBUSY; -+ goto fail; -+ } else { -+ dwc_otg_device->common_irq_installed = 1; -+ } -+ -+ /* -+ * Initialize the DWC_otg core. -+ */ -+ dwc_otg_core_init( dwc_otg_device->core_if ); -+ -+ -+#ifndef DWC_HOST_ONLY // otg device mode. (gadget.) -+ /* -+ * Initialize the PCD -+ */ -+ retval = dwc_otg_pcd_init(dwc_otg_device); -+ if (retval != 0) { -+ DWC_ERROR("dwc_otg_pcd_init failed\n"); -+ dwc_otg_device->pcd = NULL; -+ goto fail; -+ } -+#endif // DWC_HOST_ONLY -+ -+#ifndef DWC_DEVICE_ONLY // otg host mode. (HCD) -+ /* -+ * Initialize the HCD -+ */ -+#if 1 /*fscz*/ -+ /* force_host_mode */ -+ usbcfg.d32 = dwc_read_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg); -+ usbcfg.b.force_host_mode = 1; -+ dwc_write_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg, usbcfg.d32); -+#endif -+ retval = dwc_otg_hcd_init(&_dev->dev, dwc_otg_device); -+ if (retval != 0) { -+ DWC_ERROR("dwc_otg_hcd_init failed\n"); -+ dwc_otg_device->hcd = NULL; -+ goto fail; -+ } -+#endif // DWC_DEVICE_ONLY -+ -+ /* -+ * Enable the global interrupt after all the interrupt -+ * handlers are installed. -+ */ -+ dwc_otg_enable_global_interrupts( dwc_otg_device->core_if ); -+#if 0 /*fscz*/ -+ usbcfg.d32 = dwc_read_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg); -+ usbcfg.b.force_host_mode = 0; -+ dwc_write_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg, usbcfg.d32); -+#endif -+ -+ -+ return 0; -+ -+fail: -+ dwc_otg_driver_remove(_dev); -+ return retval; -+} -+ -+/** -+ * This structure defines the methods to be called by a bus driver -+ * during the lifecycle of a device on that bus. Both drivers and -+ * devices are registered with a bus driver. The bus driver matches -+ * devices to drivers based on information in the device and driver -+ * structures. -+ * -+ * The probe function is called when the bus driver matches a device -+ * to this driver. The remove function is called when a device is -+ * unregistered with the bus driver. -+ */ -+struct platform_driver dwc_otg_driver = { -+ .probe = dwc_otg_driver_probe, -+ .remove = dwc_otg_driver_remove, -+// .suspend = dwc_otg_driver_suspend, -+// .resume = dwc_otg_driver_resume, -+ .driver = { -+ .name = dwc_driver_name, -+ .owner = THIS_MODULE, -+ }, -+}; -+EXPORT_SYMBOL(dwc_otg_driver); -+ -+/** -+ * This function is called when the dwc_otg_driver is installed with the -+ * insmod command. It registers the dwc_otg_driver structure with the -+ * appropriate bus driver. This will cause the dwc_otg_driver_probe function -+ * to be called. In addition, the bus driver will automatically expose -+ * attributes defined for the device and driver in the special sysfs file -+ * system. -+ * -+ * @return -+ */ -+static int __init dwc_otg_init(void) -+{ -+ int retval = 0; -+ -+ printk(KERN_INFO "%s: version %s\n", dwc_driver_name, DWC_DRIVER_VERSION); -+ -+ // ifxmips setup -+ retval = ifx_usb_hc_init(dwc_iomem_base, dwc_irq); -+ if (retval < 0) -+ { -+ printk(KERN_ERR "%s retval=%d\n", __func__, retval); -+ return retval; -+ } -+ dwc_otg_power_on(); // ifx only!! -+ -+ -+ retval = platform_driver_register(&dwc_otg_driver); -+ -+ if (retval < 0) { -+ printk(KERN_ERR "%s retval=%d\n", __func__, retval); -+ goto error1; -+ } -+ -+ retval = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version); -+ if (retval < 0) -+ { -+ printk(KERN_ERR "%s retval=%d\n", __func__, retval); -+ goto error2; -+ } -+ retval = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel); -+ if (retval < 0) -+ { -+ printk(KERN_ERR "%s retval=%d\n", __func__, retval); -+ goto error3; -+ } -+ return retval; -+ -+ -+error3: -+ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version); -+error2: -+ driver_unregister(&dwc_otg_driver.driver); -+error1: -+ ifx_usb_hc_remove(); -+ return retval; -+} -+module_init(dwc_otg_init); -+ -+/** -+ * This function is called when the driver is removed from the kernel -+ * with the rmmod command. The driver unregisters itself with its bus -+ * driver. -+ * -+ */ -+static void __exit dwc_otg_cleanup(void) -+{ -+ printk(KERN_DEBUG "dwc_otg_cleanup()\n"); -+ -+ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel); -+ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version); -+ -+ platform_driver_unregister(&dwc_otg_driver); -+ ifx_usb_hc_remove(); -+ -+ printk(KERN_INFO "%s module removed\n", dwc_driver_name); -+} -+module_exit(dwc_otg_cleanup); -+ -+MODULE_DESCRIPTION(DWC_DRIVER_DESC); -+MODULE_AUTHOR("Synopsys Inc."); -+MODULE_LICENSE("GPL"); -+ -+module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444); -+MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None"); -+module_param_named(opt, dwc_otg_module_params.opt, int, 0444); -+MODULE_PARM_DESC(opt, "OPT Mode"); -+module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444); -+MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled"); -+module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444); -+MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256"); -+module_param_named(speed, dwc_otg_module_params.speed, int, 0444); -+MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed"); -+module_param_named(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444); -+MODULE_PARM_DESC(host_support_fs_ls_low_power, "Support Low Power w/FS or LS 0=Support 1=Don't Support"); -+module_param_named(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444); -+MODULE_PARM_DESC(host_ls_low_power_phy_clk, "Low Speed Low Power Clock 0=48Mhz 1=6Mhz"); -+module_param_named(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444); -+MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing"); -+module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444); -+MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768"); -+module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444); -+MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); -+module_param_named(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444); -+MODULE_PARM_DESC(dev_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768"); -+module_param_named(dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444); -+MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO 4-768"); -+module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444); -+MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); -+module_param_named(host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444); -+MODULE_PARM_DESC(host_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768"); -+module_param_named(host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444); -+MODULE_PARM_DESC(host_perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768"); -+module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444); -+/** @todo Set the max to 512K, modify checks */ -+MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535"); -+module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444); -+MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511"); -+module_param_named(host_channels, dwc_otg_module_params.host_channels, int, 0444); -+MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16"); -+module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444); -+MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15"); -+module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444); -+MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI"); -+module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444); -+MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits"); -+module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444); -+MODULE_PARM_DESC(phy_ulpi_ddr, "ULPI at double or single data rate 0=Single 1=Double"); -+module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444); -+MODULE_PARM_DESC(phy_ulpi_ext_vbus, "ULPI PHY using internal or external vbus 0=Internal"); -+module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444); -+MODULE_PARM_DESC(i2c_enable, "FS PHY Interface"); -+module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444); -+MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only"); -+module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444); -+MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs"); -+module_param_named(debug, g_dbg_lvl, int, 0444); -+MODULE_PARM_DESC(debug, "0"); -+module_param_named(en_multiple_tx_fifo, -+ dwc_otg_module_params.en_multiple_tx_fifo, int, 0444); -+MODULE_PARM_DESC(en_multiple_tx_fifo, -+ "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled"); -+module_param_named(dev_tx_fifo_size_1, -+ dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_2, -+ dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_3, -+ dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_4, -+ dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_5, -+ dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_6, -+ dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_7, -+ dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_8, -+ dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_9, -+ dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_10, -+ dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_11, -+ dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_12, -+ dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_13, -+ dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_14, -+ dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768"); -+module_param_named(dev_tx_fifo_size_15, -+ dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444); -+MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768"); -+module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444); -+MODULE_PARM_DESC(thr_ctl, "Thresholding enable flag bit" -+ "0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled"); -+module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444); -+MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs"); -+module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444); -+MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs"); -+module_param_named (iomem_base, dwc_iomem_base, ulong, 0444); -+MODULE_PARM_DESC (dwc_iomem_base, "The base address of the DWC_OTG register."); -+module_param_named (irq, dwc_irq, int, 0444); -+MODULE_PARM_DESC (dwc_irq, "The interrupt number"); -+ -+/** @page "Module Parameters" -+ * -+ * The following parameters may be specified when starting the module. -+ * These parameters define how the DWC_otg controller should be -+ * configured. Parameter values are passed to the CIL initialization -+ * function dwc_otg_cil_init -+ * -+ * Example: modprobe dwc_otg speed=1 otg_cap=1 -+ * -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+*/ ---- /dev/null -+++ b/drivers/usb/dwc_otg/dwc_otg_driver.h -@@ -0,0 +1,84 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.h $ -+ * $Revision: 1.1.1.1 $ -+ * $Date: 2009-04-17 06:15:34 $ -+ * $Change: 510275 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+#if !defined(__DWC_OTG_DRIVER_H__) -+#define __DWC_OTG_DRIVER_H__ -+ -+/** @file -+ * This file contains the interface to the Linux driver. -+ */ -+#include "dwc_otg_cil.h" -+ -+/* Type declarations */ -+struct dwc_otg_pcd; -+struct dwc_otg_hcd; -+ -+/** -+ * This structure is a wrapper that encapsulates the driver components used to -+ * manage a single DWC_otg controller. -+ */ -+typedef struct dwc_otg_device -+{ -+ /** Base address returned from ioremap() */ -+ void *base; -+ -+ /** Pointer to the core interface structure. */ -+ dwc_otg_core_if_t *core_if; -+ -+ /** Register offset for Diagnostic API.*/ -+ uint32_t reg_offset; -+ -+ /** Pointer to the PCD structure. */ -+ struct dwc_otg_pcd *pcd; -+ -+ /** Pointer to the HCD structure. */ -+ struct dwc_otg_hcd *hcd; -+ -+ /** Flag to indicate whether the common IRQ handler is installed. */ -+ uint8_t common_irq_installed; -+ -+ /** Interrupt request number. */ -+ unsigned int irq; -+ -+ /** Physical address of Control and Status registers, used by -+ * release_mem_region(). -+ */ -+ resource_size_t phys_addr; -+ -+ /** Length of memory region, used by release_mem_region(). */ -+ unsigned long base_len; -+} dwc_otg_device_t; -+ -+//#define dev_dbg(fake, format, arg...) printk(KERN_CRIT __FILE__ ":%d: " format "\n" , __LINE__, ## arg) -+ -+#endif ---- /dev/null -+++ b/drivers/usb/dwc_otg/dwc_otg_hcd.c -@@ -0,0 +1,2870 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd.c $ -+ * $Revision: 1.1.1.1 $ -+ * $Date: 2009-04-17 06:15:34 $ -+ * $Change: 631780 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+#ifndef DWC_DEVICE_ONLY -+ -+/** -+ * @file -+ * -+ * This file contains the implementation of the HCD. In Linux, the HCD -+ * implements the hc_driver API. -+ */ -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "dwc_otg_driver.h" -+#include "dwc_otg_hcd.h" -+#include "dwc_otg_regs.h" -+ -+#include -+#include "dwc_otg_ifx.h" // for Infineon platform specific. -+extern atomic_t release_later; -+ -+static u64 dma_mask = DMA_BIT_MASK(32); -+ -+static const char dwc_otg_hcd_name [] = "dwc_otg_hcd"; -+static const struct hc_driver dwc_otg_hc_driver = -+{ -+ .description = dwc_otg_hcd_name, -+ .product_desc = "DWC OTG Controller", -+ .hcd_priv_size = sizeof(dwc_otg_hcd_t), -+ .irq = dwc_otg_hcd_irq, -+ .flags = HCD_MEMORY | HCD_USB2, -+ //.reset = -+ .start = dwc_otg_hcd_start, -+ //.suspend = -+ //.resume = -+ .stop = dwc_otg_hcd_stop, -+ .urb_enqueue = dwc_otg_hcd_urb_enqueue, -+ .urb_dequeue = dwc_otg_hcd_urb_dequeue, -+ .endpoint_disable = dwc_otg_hcd_endpoint_disable, -+ .get_frame_number = dwc_otg_hcd_get_frame_number, -+ .hub_status_data = dwc_otg_hcd_hub_status_data, -+ .hub_control = dwc_otg_hcd_hub_control, -+ //.hub_suspend = -+ //.hub_resume = -+}; -+ -+ -+/** -+ * Work queue function for starting the HCD when A-Cable is connected. -+ * The dwc_otg_hcd_start() must be called in a process context. -+ */ -+static void hcd_start_func(struct work_struct *work) -+{ -+ struct dwc_otg_hcd *priv = -+ container_of(work, struct dwc_otg_hcd, start_work); -+ struct usb_hcd *usb_hcd = (struct usb_hcd *)priv->_p; -+ DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, usb_hcd); -+ if (usb_hcd) { -+ dwc_otg_hcd_start(usb_hcd); -+ } -+} -+ -+ -+/** -+ * HCD Callback function for starting the HCD when A-Cable is -+ * connected. -+ * -+ * @param _p void pointer to the struct usb_hcd -+ */ -+static int32_t dwc_otg_hcd_start_cb(void *_p) -+{ -+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_p); -+ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; -+ hprt0_data_t hprt0; -+ if (core_if->op_state == B_HOST) { -+ /* -+ * Reset the port. During a HNP mode switch the reset -+ * needs to occur within 1ms and have a duration of at -+ * least 50ms. -+ */ -+ hprt0.d32 = dwc_otg_read_hprt0 (core_if); -+ hprt0.b.prtrst = 1; -+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); -+ ((struct usb_hcd *)_p)->self.is_b_host = 1; -+ } else { -+ ((struct usb_hcd *)_p)->self.is_b_host = 0; -+ } -+ /* Need to start the HCD in a non-interrupt context. */ -+ INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func); -+ dwc_otg_hcd->_p = _p; -+ schedule_work(&dwc_otg_hcd->start_work); -+ return 1; -+} -+ -+ -+/** -+ * HCD Callback function for stopping the HCD. -+ * -+ * @param _p void pointer to the struct usb_hcd -+ */ -+static int32_t dwc_otg_hcd_stop_cb( void *_p ) -+{ -+ struct usb_hcd *usb_hcd = (struct usb_hcd *)_p; -+ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p); -+ dwc_otg_hcd_stop( usb_hcd ); -+ return 1; -+} -+static void del_xfer_timers(dwc_otg_hcd_t *_hcd) -+{ -+#ifdef DEBUG -+ int i; -+ int num_channels = _hcd->core_if->core_params->host_channels; -+ for (i = 0; i < num_channels; i++) { -+ del_timer(&_hcd->core_if->hc_xfer_timer[i]); -+ } -+#endif /* */ -+} -+ -+static void del_timers(dwc_otg_hcd_t *_hcd) -+{ -+ del_xfer_timers(_hcd); -+ del_timer(&_hcd->conn_timer); -+} -+ -+/** -+ * Processes all the URBs in a single list of QHs. Completes them with -+ * -ETIMEDOUT and frees the QTD. -+ */ -+static void kill_urbs_in_qh_list(dwc_otg_hcd_t * _hcd, -+ struct list_head *_qh_list) -+{ -+ struct list_head *qh_item; -+ dwc_otg_qh_t *qh; -+ struct list_head *qtd_item; -+ dwc_otg_qtd_t *qtd; -+ -+ list_for_each(qh_item, _qh_list) { -+ qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry); -+ for (qtd_item = qh->qtd_list.next; qtd_item != &qh->qtd_list; -+ qtd_item = qh->qtd_list.next) { -+ qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry); -+ if (qtd->urb != NULL) { -+ dwc_otg_hcd_complete_urb(_hcd, qtd->urb,-ETIMEDOUT); -+ } -+ dwc_otg_hcd_qtd_remove_and_free(qtd); -+ } -+ } -+} -+ -+/** -+ * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic -+ * and periodic schedules. The QTD associated with each URB is removed from -+ * the schedule and freed. This function may be called when a disconnect is -+ * detected or when the HCD is being stopped. -+ */ -+static void kill_all_urbs(dwc_otg_hcd_t *_hcd) -+{ -+ kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_deferred); -+ kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_inactive); -+ kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_active); -+ kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_inactive); -+ kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_ready); -+ kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_assigned); -+ kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_queued); -+} -+ -+/** -+ * HCD Callback function for disconnect of the HCD. -+ * -+ * @param _p void pointer to the struct usb_hcd -+ */ -+static int32_t dwc_otg_hcd_disconnect_cb( void *_p ) -+{ -+ gintsts_data_t intr; -+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p); -+ -+ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p); -+ -+ /* -+ * Set status flags for the hub driver. -+ */ -+ dwc_otg_hcd->flags.b.port_connect_status_change = 1; -+ dwc_otg_hcd->flags.b.port_connect_status = 0; -+ -+ /* -+ * Shutdown any transfers in process by clearing the Tx FIFO Empty -+ * interrupt mask and status bits and disabling subsequent host -+ * channel interrupts. -+ */ -+ intr.d32 = 0; -+ intr.b.nptxfempty = 1; -+ intr.b.ptxfempty = 1; -+ intr.b.hcintr = 1; -+ dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0); -+ dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0); -+ -+ del_timers(dwc_otg_hcd); -+ -+ /* -+ * Turn off the vbus power only if the core has transitioned to device -+ * mode. If still in host mode, need to keep power on to detect a -+ * reconnection. -+ */ -+ if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) { -+ if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) { -+ hprt0_data_t hprt0 = { .d32=0 }; -+ DWC_PRINT("Disconnect: PortPower off\n"); -+ hprt0.b.prtpwr = 0; -+ dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32); -+ } -+ -+ dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if ); -+ } -+ -+ /* Respond with an error status to all URBs in the schedule. */ -+ kill_all_urbs(dwc_otg_hcd); -+ -+ if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) { -+ /* Clean up any host channels that were in use. */ -+ int num_channels; -+ int i; -+ dwc_hc_t *channel; -+ dwc_otg_hc_regs_t *hc_regs; -+ hcchar_data_t hcchar; -+ -+ num_channels = dwc_otg_hcd->core_if->core_params->host_channels; -+ -+ if (!dwc_otg_hcd->core_if->dma_enable) { -+ /* Flush out any channel requests in slave mode. */ -+ for (i = 0; i < num_channels; i++) { -+ channel = dwc_otg_hcd->hc_ptr_array[i]; -+ if (list_empty(&channel->hc_list_entry)) { -+ hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i]; -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ if (hcchar.b.chen) { -+ hcchar.b.chen = 0; -+ hcchar.b.chdis = 1; -+ hcchar.b.epdir = 0; -+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); -+ } -+ } -+ } -+ } -+ -+ for (i = 0; i < num_channels; i++) { -+ channel = dwc_otg_hcd->hc_ptr_array[i]; -+ if (list_empty(&channel->hc_list_entry)) { -+ hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i]; -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ if (hcchar.b.chen) { -+ /* Halt the channel. */ -+ hcchar.b.chdis = 1; -+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); -+ } -+ -+ dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, channel); -+ list_add_tail(&channel->hc_list_entry, -+ &dwc_otg_hcd->free_hc_list); -+ } -+ } -+ } -+ -+ /* A disconnect will end the session so the B-Device is no -+ * longer a B-host. */ -+ ((struct usb_hcd *)_p)->self.is_b_host = 0; -+ -+ return 1; -+} -+ -+/** -+ * Connection timeout function. An OTG host is required to display a -+ * message if the device does not connect within 10 seconds. -+ */ -+void dwc_otg_hcd_connect_timeout( unsigned long _ptr ) -+{ -+ DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int)_ptr); -+ DWC_PRINT( "Connect Timeout\n"); -+ DWC_ERROR( "Device Not Connected/Responding\n" ); -+} -+ -+/** -+ * Start the connection timer. An OTG host is required to display a -+ * message if the device does not connect within 10 seconds. The -+ * timer is deleted if a port connect interrupt occurs before the -+ * timer expires. -+ */ -+static void dwc_otg_hcd_start_connect_timer( dwc_otg_hcd_t *_hcd) -+{ -+ init_timer( &_hcd->conn_timer ); -+ _hcd->conn_timer.function = dwc_otg_hcd_connect_timeout; -+ _hcd->conn_timer.data = (unsigned long)0; -+ _hcd->conn_timer.expires = jiffies + (HZ*10); -+ add_timer( &_hcd->conn_timer ); -+} -+ -+/** -+ * HCD Callback function for disconnect of the HCD. -+ * -+ * @param _p void pointer to the struct usb_hcd -+ */ -+static int32_t dwc_otg_hcd_session_start_cb( void *_p ) -+{ -+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p); -+ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p); -+ dwc_otg_hcd_start_connect_timer( dwc_otg_hcd ); -+ return 1; -+} -+ -+/** -+ * HCD Callback structure for handling mode switching. -+ */ -+static dwc_otg_cil_callbacks_t hcd_cil_callbacks = { -+ .start = dwc_otg_hcd_start_cb, -+ .stop = dwc_otg_hcd_stop_cb, -+ .disconnect = dwc_otg_hcd_disconnect_cb, -+ .session_start = dwc_otg_hcd_session_start_cb, -+ .p = 0, -+}; -+ -+ -+/** -+ * Reset tasklet function -+ */ -+static void reset_tasklet_func (unsigned long data) -+{ -+ dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t*)data; -+ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; -+ hprt0_data_t hprt0; -+ -+ DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n"); -+ -+ hprt0.d32 = dwc_otg_read_hprt0 (core_if); -+ hprt0.b.prtrst = 1; -+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); -+ mdelay (60); -+ -+ hprt0.b.prtrst = 0; -+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); -+ dwc_otg_hcd->flags.b.port_reset_change = 1; -+ -+ return; -+} -+ -+static struct tasklet_struct reset_tasklet = { -+ .next = NULL, -+ .state = 0, -+ .count = ATOMIC_INIT(0), -+ .func = reset_tasklet_func, -+ .data = 0, -+}; -+ -+/** -+ * Initializes the HCD. This function allocates memory for and initializes the -+ * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the -+ * USB bus with the core and calls the hc_driver->start() function. It returns -+ * a negative error on failure. -+ */ -+int init_hcd_usecs(dwc_otg_hcd_t *_hcd); -+ -+int __devinit dwc_otg_hcd_init(struct device *_dev, dwc_otg_device_t * dwc_otg_device) -+{ -+ struct usb_hcd *hcd = NULL; -+ dwc_otg_hcd_t *dwc_otg_hcd = NULL; -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); -+ -+ int num_channels; -+ int i; -+ dwc_hc_t *channel; -+ -+ int retval = 0; -+ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n"); -+ -+ /* -+ * Allocate memory for the base HCD plus the DWC OTG HCD. -+ * Initialize the base HCD. -+ */ -+ hcd = usb_create_hcd(&dwc_otg_hc_driver, _dev, dev_name(_dev)); -+ if (hcd == NULL) { -+ retval = -ENOMEM; -+ goto error1; -+ } -+ dev_set_drvdata(_dev, dwc_otg_device); /* fscz restore */ -+ hcd->regs = otg_dev->base; -+ hcd->rsrc_start = (int)otg_dev->base; -+ -+ hcd->self.otg_port = 1; -+ -+ /* Initialize the DWC OTG HCD. */ -+ dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); -+ dwc_otg_hcd->core_if = otg_dev->core_if; -+ otg_dev->hcd = dwc_otg_hcd; -+ -+ /* Register the HCD CIL Callbacks */ -+ dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if, -+ &hcd_cil_callbacks, hcd); -+ -+ /* Initialize the non-periodic schedule. */ -+ INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive); -+ INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active); -+ INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_deferred); -+ -+ /* Initialize the periodic schedule. */ -+ INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive); -+ INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready); -+ INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned); -+ INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued); -+ -+ /* -+ * Create a host channel descriptor for each host channel implemented -+ * in the controller. Initialize the channel descriptor array. -+ */ -+ INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list); -+ num_channels = dwc_otg_hcd->core_if->core_params->host_channels; -+ for (i = 0; i < num_channels; i++) { -+ channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL); -+ if (channel == NULL) { -+ retval = -ENOMEM; -+ DWC_ERROR("%s: host channel allocation failed\n", __func__); -+ goto error2; -+ } -+ memset(channel, 0, sizeof(dwc_hc_t)); -+ channel->hc_num = i; -+ dwc_otg_hcd->hc_ptr_array[i] = channel; -+#ifdef DEBUG -+ init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]); -+#endif -+ -+ DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel); -+ } -+ -+ /* Initialize the Connection timeout timer. */ -+ init_timer( &dwc_otg_hcd->conn_timer ); -+ -+ /* Initialize reset tasklet. */ -+ reset_tasklet.data = (unsigned long) dwc_otg_hcd; -+ dwc_otg_hcd->reset_tasklet = &reset_tasklet; -+ -+ /* Set device flags indicating whether the HCD supports DMA. */ -+ if (otg_dev->core_if->dma_enable) { -+ DWC_PRINT("Using DMA mode\n"); -+ //_dev->dma_mask = (void *)~0; -+ //_dev->coherent_dma_mask = ~0; -+ _dev->dma_mask = &dma_mask; -+ _dev->coherent_dma_mask = DMA_BIT_MASK(32); -+ } else { -+ DWC_PRINT("Using Slave mode\n"); -+ _dev->dma_mask = (void *)0; -+ _dev->coherent_dma_mask = 0; -+ } -+ -+ init_hcd_usecs(dwc_otg_hcd); -+ /* -+ * Finish generic HCD initialization and start the HCD. This function -+ * allocates the DMA buffer pool, registers the USB bus, requests the -+ * IRQ line, and calls dwc_otg_hcd_start method. -+ */ -+ retval = usb_add_hcd(hcd, otg_dev->irq, IRQF_SHARED); -+ if (retval < 0) { -+ goto error2; -+ } -+ -+ /* -+ * Allocate space for storing data on status transactions. Normally no -+ * data is sent, but this space acts as a bit bucket. This must be -+ * done after usb_add_hcd since that function allocates the DMA buffer -+ * pool. -+ */ -+ if (otg_dev->core_if->dma_enable) { -+ dwc_otg_hcd->status_buf = -+ dma_alloc_coherent(_dev, -+ DWC_OTG_HCD_STATUS_BUF_SIZE, -+ &dwc_otg_hcd->status_buf_dma, -+ GFP_KERNEL | GFP_DMA); -+ } else { -+ dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE, -+ GFP_KERNEL); -+ } -+ if (dwc_otg_hcd->status_buf == NULL) { -+ retval = -ENOMEM; -+ DWC_ERROR("%s: status_buf allocation failed\n", __func__); -+ goto error3; -+ } -+ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n", -+ dev_name(_dev), hcd->self.busnum); -+ -+ return 0; -+ -+ /* Error conditions */ -+error3: -+ usb_remove_hcd(hcd); -+error2: -+ dwc_otg_hcd_free(hcd); -+ usb_put_hcd(hcd); -+error1: -+ return retval; -+} -+ -+/** -+ * Removes the HCD. -+ * Frees memory and resources associated with the HCD and deregisters the bus. -+ */ -+void dwc_otg_hcd_remove(struct device *_dev) -+{ -+ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); -+ dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd; -+ struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd); -+ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n"); -+ -+ /* Turn off all interrupts */ -+ dwc_write_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0); -+ dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0); -+ -+ usb_remove_hcd(hcd); -+ -+ dwc_otg_hcd_free(hcd); -+ -+ usb_put_hcd(hcd); -+ -+ return; -+} -+ -+ -+/* ========================================================================= -+ * Linux HC Driver Functions -+ * ========================================================================= */ -+ -+/** -+ * Initializes dynamic portions of the DWC_otg HCD state. -+ */ -+static void hcd_reinit(dwc_otg_hcd_t *_hcd) -+{ -+ struct list_head *item; -+ int num_channels; -+ int i; -+ dwc_hc_t *channel; -+ -+ _hcd->flags.d32 = 0; -+ -+ _hcd->non_periodic_qh_ptr = &_hcd->non_periodic_sched_active; -+ _hcd->available_host_channels = _hcd->core_if->core_params->host_channels; -+ -+ /* -+ * Put all channels in the free channel list and clean up channel -+ * states. -+ */ -+ item = _hcd->free_hc_list.next; -+ while (item != &_hcd->free_hc_list) { -+ list_del(item); -+ item = _hcd->free_hc_list.next; -+ } -+ num_channels = _hcd->core_if->core_params->host_channels; -+ for (i = 0; i < num_channels; i++) { -+ channel = _hcd->hc_ptr_array[i]; -+ list_add_tail(&channel->hc_list_entry, &_hcd->free_hc_list); -+ dwc_otg_hc_cleanup(_hcd->core_if, channel); -+ } -+ -+ /* Initialize the DWC core for host mode operation. */ -+ dwc_otg_core_host_init(_hcd->core_if); -+} -+ -+/** Initializes the DWC_otg controller and its root hub and prepares it for host -+ * mode operation. Activates the root port. Returns 0 on success and a negative -+ * error code on failure. */ -+int dwc_otg_hcd_start(struct usb_hcd *_hcd) -+{ -+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd); -+ dwc_otg_core_if_t * core_if = dwc_otg_hcd->core_if; -+ struct usb_bus *bus; -+ -+ // int retval; -+ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n"); -+ -+ bus = hcd_to_bus(_hcd); -+ -+ /* Initialize the bus state. If the core is in Device Mode -+ * HALT the USB bus and return. */ -+ if (dwc_otg_is_device_mode (core_if)) { -+ _hcd->state = HC_STATE_HALT; -+ return 0; -+ } -+ _hcd->state = HC_STATE_RUNNING; -+ -+ /* Initialize and connect root hub if one is not already attached */ -+ if (bus->root_hub) { -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n"); -+ /* Inform the HUB driver to resume. */ -+ usb_hcd_resume_root_hub(_hcd); -+ } -+ else { -+#if 0 -+ struct usb_device *udev; -+ udev = usb_alloc_dev(NULL, bus, 0); -+ if (!udev) { -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n"); -+ return -ENODEV; -+ } -+ udev->speed = USB_SPEED_HIGH; -+ /* Not needed - VJ -+ if ((retval = usb_hcd_register_root_hub(udev, _hcd)) != 0) { -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error registering %d\n", retval); -+ return -ENODEV; -+ } -+ */ -+#else -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n"); -+#endif -+ } -+ -+ hcd_reinit(dwc_otg_hcd); -+ -+ return 0; -+} -+ -+static void qh_list_free(dwc_otg_hcd_t *_hcd, struct list_head *_qh_list) -+{ -+ struct list_head *item; -+ dwc_otg_qh_t *qh; -+ -+ if (_qh_list->next == NULL) { -+ /* The list hasn't been initialized yet. */ -+ return; -+ } -+ -+ /* Ensure there are no QTDs or URBs left. */ -+ kill_urbs_in_qh_list(_hcd, _qh_list); -+ -+ for (item = _qh_list->next; item != _qh_list; item = _qh_list->next) { -+ qh = list_entry(item, dwc_otg_qh_t, qh_list_entry); -+ dwc_otg_hcd_qh_remove_and_free(_hcd, qh); -+ } -+} -+ -+/** -+ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are -+ * stopped. -+ */ -+void dwc_otg_hcd_stop(struct usb_hcd *_hcd) -+{ -+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd); -+ hprt0_data_t hprt0 = { .d32=0 }; -+ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n"); -+ -+ /* Turn off all host-specific interrupts. */ -+ dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if ); -+ -+ /* -+ * The root hub should be disconnected before this function is called. -+ * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) -+ * and the QH lists (via ..._hcd_endpoint_disable). -+ */ -+ -+ /* Turn off the vbus power */ -+ DWC_PRINT("PortPower off\n"); -+ hprt0.b.prtpwr = 0; -+ dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32); -+ -+ return; -+} -+ -+ -+/** Returns the current frame number. */ -+int dwc_otg_hcd_get_frame_number(struct usb_hcd *_hcd) -+{ -+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd); -+ hfnum_data_t hfnum; -+ -+ hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if-> -+ host_if->host_global_regs->hfnum); -+ -+#ifdef DEBUG_SOF -+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", hfnum.b.frnum); -+#endif -+ return hfnum.b.frnum; -+} -+ -+/** -+ * Frees secondary storage associated with the dwc_otg_hcd structure contained -+ * in the struct usb_hcd field. -+ */ -+void dwc_otg_hcd_free(struct usb_hcd *_hcd) -+{ -+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd); -+ int i; -+ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n"); -+ -+ del_timers(dwc_otg_hcd); -+ -+ /* Free memory for QH/QTD lists */ -+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive); -+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_deferred); -+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active); -+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive); -+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready); -+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned); -+ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued); -+ -+ /* Free memory for the host channels. */ -+ for (i = 0; i < MAX_EPS_CHANNELS; i++) { -+ dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i]; -+ if (hc != NULL) { -+ DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", i, hc); -+ kfree(hc); -+ } -+ } -+ -+ if (dwc_otg_hcd->core_if->dma_enable) { -+ if (dwc_otg_hcd->status_buf_dma) { -+ dma_free_coherent(_hcd->self.controller, -+ DWC_OTG_HCD_STATUS_BUF_SIZE, -+ dwc_otg_hcd->status_buf, -+ dwc_otg_hcd->status_buf_dma); -+ } -+ } else if (dwc_otg_hcd->status_buf != NULL) { -+ kfree(dwc_otg_hcd->status_buf); -+ } -+ -+ return; -+} -+ -+ -+#ifdef DEBUG -+static void dump_urb_info(struct urb *_urb, char* _fn_name) -+{ -+ DWC_PRINT("%s, urb %p\n", _fn_name, _urb); -+ DWC_PRINT(" Device address: %d\n", usb_pipedevice(_urb->pipe)); -+ DWC_PRINT(" Endpoint: %d, %s\n", usb_pipeendpoint(_urb->pipe), -+ (usb_pipein(_urb->pipe) ? "IN" : "OUT")); -+ DWC_PRINT(" Endpoint type: %s\n", -+ ({char *pipetype; -+ switch (usb_pipetype(_urb->pipe)) { -+ case PIPE_CONTROL: pipetype = "CONTROL"; break; -+ case PIPE_BULK: pipetype = "BULK"; break; -+ case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break; -+ case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break; -+ default: pipetype = "UNKNOWN"; break; -+ }; pipetype;})); -+ DWC_PRINT(" Speed: %s\n", -+ ({char *speed; -+ switch (_urb->dev->speed) { -+ case USB_SPEED_HIGH: speed = "HIGH"; break; -+ case USB_SPEED_FULL: speed = "FULL"; break; -+ case USB_SPEED_LOW: speed = "LOW"; break; -+ default: speed = "UNKNOWN"; break; -+ }; speed;})); -+ DWC_PRINT(" Max packet size: %d\n", -+ usb_maxpacket(_urb->dev, _urb->pipe, usb_pipeout(_urb->pipe))); -+ DWC_PRINT(" Data buffer length: %d\n", _urb->transfer_buffer_length); -+ DWC_PRINT(" Transfer buffer: %p, Transfer DMA: %p\n", -+ _urb->transfer_buffer, (void *)_urb->transfer_dma); -+ DWC_PRINT(" Setup buffer: %p, Setup DMA: %p\n", -+ _urb->setup_packet, (void *)_urb->setup_dma); -+ DWC_PRINT(" Interval: %d\n", _urb->interval); -+ if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) { -+ int i; -+ for (i = 0; i < _urb->number_of_packets; i++) { -+ DWC_PRINT(" ISO Desc %d:\n", i); -+ DWC_PRINT(" offset: %d, length %d\n", -+ _urb->iso_frame_desc[i].offset, -+ _urb->iso_frame_desc[i].length); -+ } -+ } -+} -+ -+static void dump_channel_info(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *qh) -+{ -+ if (qh->channel != NULL) { -+ dwc_hc_t *hc = qh->channel; -+ struct list_head *item; -+ dwc_otg_qh_t *qh_item; -+ int num_channels = _hcd->core_if->core_params->host_channels; -+ int i; -+ -+ dwc_otg_hc_regs_t *hc_regs; -+ hcchar_data_t hcchar; -+ hcsplt_data_t hcsplt; -+ hctsiz_data_t hctsiz; -+ uint32_t hcdma; -+ -+ hc_regs = _hcd->core_if->host_if->hc_regs[hc->hc_num]; -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt); -+ hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); -+ hcdma = dwc_read_reg32(&hc_regs->hcdma); -+ -+ DWC_PRINT(" Assigned to channel %p:\n", hc); -+ DWC_PRINT(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32); -+ DWC_PRINT(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma); -+ DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n", -+ hc->dev_addr, hc->ep_num, hc->ep_is_in); -+ DWC_PRINT(" ep_type: %d\n", hc->ep_type); -+ DWC_PRINT(" max_packet: %d\n", hc->max_packet); -+ DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start); -+ DWC_PRINT(" xfer_started: %d\n", hc->xfer_started); -+ DWC_PRINT(" halt_status: %d\n", hc->halt_status); -+ DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff); -+ DWC_PRINT(" xfer_len: %d\n", hc->xfer_len); -+ DWC_PRINT(" qh: %p\n", hc->qh); -+ DWC_PRINT(" NP inactive sched:\n"); -+ list_for_each(item, &_hcd->non_periodic_sched_inactive) { -+ qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry); -+ DWC_PRINT(" %p\n", qh_item); -+ } DWC_PRINT(" NP active sched:\n"); -+ list_for_each(item, &_hcd->non_periodic_sched_deferred) { -+ qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry); -+ DWC_PRINT(" %p\n", qh_item); -+ } DWC_PRINT(" NP deferred sched:\n"); -+ list_for_each(item, &_hcd->non_periodic_sched_active) { -+ qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry); -+ DWC_PRINT(" %p\n", qh_item); -+ } DWC_PRINT(" Channels: \n"); -+ for (i = 0; i < num_channels; i++) { -+ dwc_hc_t *hc = _hcd->hc_ptr_array[i]; -+ DWC_PRINT(" %2d: %p\n", i, hc); -+ } -+ } -+} -+#endif // DEBUG -+ -+/** Starts processing a USB transfer request specified by a USB Request Block -+ * (URB). mem_flags indicates the type of memory allocation to use while -+ * processing this URB. */ -+int dwc_otg_hcd_urb_enqueue(struct usb_hcd *_hcd, -+ struct urb *_urb, -+ gfp_t _mem_flags) -+{ -+ unsigned long flags; -+ int retval; -+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd); -+ dwc_otg_qtd_t *qtd; -+ -+ local_irq_save(flags); -+ retval = usb_hcd_link_urb_to_ep(_hcd, _urb); -+ if (retval) { -+ local_irq_restore(flags); -+ return retval; -+ } -+#ifdef DEBUG -+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { -+ dump_urb_info(_urb, "dwc_otg_hcd_urb_enqueue"); -+ } -+#endif // DEBUG -+ if (!dwc_otg_hcd->flags.b.port_connect_status) { -+ /* No longer connected. */ -+ local_irq_restore(flags); -+ return -ENODEV; -+ } -+ -+ qtd = dwc_otg_hcd_qtd_create (_urb); -+ if (qtd == NULL) { -+ local_irq_restore(flags); -+ DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n"); -+ return -ENOMEM; -+ } -+ -+ retval = dwc_otg_hcd_qtd_add (qtd, dwc_otg_hcd); -+ if (retval < 0) { -+ DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. " -+ "Error status %d\n", retval); -+ dwc_otg_hcd_qtd_free(qtd); -+ } -+ -+ local_irq_restore (flags); -+ return retval; -+} -+ -+/** Aborts/cancels a USB transfer request. Always returns 0 to indicate -+ * success. */ -+int dwc_otg_hcd_urb_dequeue(struct usb_hcd *_hcd, struct urb *_urb, int _status) -+{ -+ unsigned long flags; -+ dwc_otg_hcd_t *dwc_otg_hcd; -+ dwc_otg_qtd_t *urb_qtd; -+ dwc_otg_qh_t *qh; -+ int retval; -+ //struct usb_host_endpoint *_ep = NULL; -+ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n"); -+ -+ local_irq_save(flags); -+ -+ retval = usb_hcd_check_unlink_urb(_hcd, _urb, _status); -+ if (retval) { -+ local_irq_restore(flags); -+ return retval; -+ } -+ -+ dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd); -+ urb_qtd = (dwc_otg_qtd_t *)_urb->hcpriv; -+ if (urb_qtd == NULL) { -+ printk("urb_qtd is NULL for _urb %08x\n",(unsigned)_urb); -+ goto done; -+ } -+ qh = (dwc_otg_qh_t *) urb_qtd->qtd_qh_ptr; -+ if (qh == NULL) { -+ goto done; -+ } -+ -+#ifdef DEBUG -+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { -+ dump_urb_info(_urb, "dwc_otg_hcd_urb_dequeue"); -+ if (urb_qtd == qh->qtd_in_process) { -+ dump_channel_info(dwc_otg_hcd, qh); -+ } -+ } -+#endif // DEBUG -+ -+ if (urb_qtd == qh->qtd_in_process) { -+ /* The QTD is in process (it has been assigned to a channel). */ -+ -+ if (dwc_otg_hcd->flags.b.port_connect_status) { -+ /* -+ * If still connected (i.e. in host mode), halt the -+ * channel so it can be used for other transfers. If -+ * no longer connected, the host registers can't be -+ * written to halt the channel since the core is in -+ * device mode. -+ */ -+ dwc_otg_hc_halt(dwc_otg_hcd->core_if, qh->channel, -+ DWC_OTG_HC_XFER_URB_DEQUEUE); -+ } -+ } -+ -+ /* -+ * Free the QTD and clean up the associated QH. Leave the QH in the -+ * schedule if it has any remaining QTDs. -+ */ -+ dwc_otg_hcd_qtd_remove_and_free(urb_qtd); -+ if (urb_qtd == qh->qtd_in_process) { -+ dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0); -+ qh->channel = NULL; -+ qh->qtd_in_process = NULL; -+ } else if (list_empty(&qh->qtd_list)) { -+ dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh); -+ } -+ -+done: -+ local_irq_restore(flags); -+ _urb->hcpriv = NULL; -+ -+ /* Higher layer software sets URB status. */ -+ usb_hcd_unlink_urb_from_ep(_hcd, _urb); -+ usb_hcd_giveback_urb(_hcd, _urb, _status); -+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { -+ DWC_PRINT("Called usb_hcd_giveback_urb()\n"); -+ DWC_PRINT(" urb->status = %d\n", _urb->status); -+ } -+ -+ return 0; -+} -+ -+ -+/** Frees resources in the DWC_otg controller related to a given endpoint. Also -+ * clears state in the HCD related to the endpoint. Any URBs for the endpoint -+ * must already be dequeued. */ -+void dwc_otg_hcd_endpoint_disable(struct usb_hcd *_hcd, -+ struct usb_host_endpoint *_ep) -+ -+{ -+ dwc_otg_qh_t *qh; -+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd); -+ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, " -+ "endpoint=%d\n", _ep->desc.bEndpointAddress, -+ dwc_ep_addr_to_endpoint(_ep->desc.bEndpointAddress)); -+ -+ qh = (dwc_otg_qh_t *)(_ep->hcpriv); -+ if (qh != NULL) { -+#ifdef DEBUG -+ /** Check that the QTD list is really empty */ -+ if (!list_empty(&qh->qtd_list)) { -+ DWC_WARN("DWC OTG HCD EP DISABLE:" -+ " QTD List for this endpoint is not empty\n"); -+ } -+#endif // DEBUG -+ -+ dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh); -+ _ep->hcpriv = NULL; -+ } -+ -+ return; -+} -+extern int dwc_irq; -+/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if -+ * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid -+ * interrupt. -+ * -+ * This function is called by the USB core when an interrupt occurs */ -+irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *_hcd) -+{ -+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd); -+ -+ mask_and_ack_ifx_irq (dwc_irq); -+ return IRQ_RETVAL(dwc_otg_hcd_handle_intr(dwc_otg_hcd)); -+} -+ -+/** Creates Status Change bitmap for the root hub and root port. The bitmap is -+ * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 -+ * is the status change indicator for the single root port. Returns 1 if either -+ * change indicator is 1, otherwise returns 0. */ -+int dwc_otg_hcd_hub_status_data(struct usb_hcd *_hcd, char *_buf) -+{ -+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd); -+ -+ _buf[0] = 0; -+ _buf[0] |= (dwc_otg_hcd->flags.b.port_connect_status_change || -+ dwc_otg_hcd->flags.b.port_reset_change || -+ dwc_otg_hcd->flags.b.port_enable_change || -+ dwc_otg_hcd->flags.b.port_suspend_change || -+ dwc_otg_hcd->flags.b.port_over_current_change) << 1; -+ -+#ifdef DEBUG -+ if (_buf[0]) { -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:" -+ " Root port status changed\n"); -+ DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n", -+ dwc_otg_hcd->flags.b.port_connect_status_change); -+ DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n", -+ dwc_otg_hcd->flags.b.port_reset_change); -+ DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n", -+ dwc_otg_hcd->flags.b.port_enable_change); -+ DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n", -+ dwc_otg_hcd->flags.b.port_suspend_change); -+ DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n", -+ dwc_otg_hcd->flags.b.port_over_current_change); -+ } -+#endif // DEBUG -+ return (_buf[0] != 0); -+} -+ -+#ifdef DWC_HS_ELECT_TST -+/* -+ * Quick and dirty hack to implement the HS Electrical Test -+ * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature. -+ * -+ * This code was copied from our userspace app "hset". It sends a -+ * Get Device Descriptor control sequence in two parts, first the -+ * Setup packet by itself, followed some time later by the In and -+ * Ack packets. Rather than trying to figure out how to add this -+ * functionality to the normal driver code, we just hijack the -+ * hardware, using these two function to drive the hardware -+ * directly. -+ */ -+ -+dwc_otg_core_global_regs_t *global_regs; -+dwc_otg_host_global_regs_t *hc_global_regs; -+dwc_otg_hc_regs_t *hc_regs; -+uint32_t *data_fifo; -+ -+static void do_setup(void) -+{ -+ gintsts_data_t gintsts; -+ hctsiz_data_t hctsiz; -+ hcchar_data_t hcchar; -+ haint_data_t haint; -+ hcint_data_t hcint; -+ -+ /* Enable HAINTs */ -+ dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001); -+ -+ /* Enable HCINTs */ -+ dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+ -+ /* Read HAINT */ -+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); -+ //fprintf(stderr, "HAINT: %08x\n", haint.d32); -+ -+ /* Read HCINT */ -+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); -+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); -+ -+ /* Clear HCINT */ -+ dwc_write_reg32(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ dwc_write_reg32(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+ -+ /* -+ * Send Setup packet (Get Device Descriptor) -+ */ -+ -+ /* Make sure channel is disabled */ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ if (hcchar.b.chen) { -+ //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32); -+ hcchar.b.chdis = 1; -+ // hcchar.b.chen = 1; -+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); -+ //sleep(1); -+ MDELAY(1000); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+ -+ /* Read HAINT */ -+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); -+ //fprintf(stderr, "HAINT: %08x\n", haint.d32); -+ -+ /* Read HCINT */ -+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); -+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); -+ -+ /* Clear HCINT */ -+ dwc_write_reg32(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ dwc_write_reg32(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); -+ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ //if (hcchar.b.chen) { -+ // fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32); -+ //} -+ } -+ -+ /* Set HCTSIZ */ -+ hctsiz.d32 = 0; -+ hctsiz.b.xfersize = 8; -+ hctsiz.b.pktcnt = 1; -+ hctsiz.b.pid = DWC_OTG_HC_PID_SETUP; -+ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); -+ -+ /* Set HCCHAR */ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; -+ hcchar.b.epdir = 0; -+ hcchar.b.epnum = 0; -+ hcchar.b.mps = 8; -+ hcchar.b.chen = 1; -+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); -+ -+ /* Fill FIFO with Setup data for Get Device Descriptor */ -+ data_fifo = (uint32_t *)((char *)global_regs + 0x1000); -+ dwc_write_reg32(data_fifo++, 0x01000680); -+ dwc_write_reg32(data_fifo++, 0x00080000); -+ -+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); -+ //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32); -+ -+ /* Wait for host channel interrupt */ -+ do { -+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); -+ } while (gintsts.b.hcintr == 0); -+ -+ //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32); -+ -+ /* Disable HCINTs */ -+ dwc_write_reg32(&hc_regs->hcintmsk, 0x0000); -+ -+ /* Disable HAINTs */ -+ dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000); -+ -+ /* Read HAINT */ -+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); -+ //fprintf(stderr, "HAINT: %08x\n", haint.d32); -+ -+ /* Read HCINT */ -+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); -+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); -+ -+ /* Clear HCINT */ -+ dwc_write_reg32(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ dwc_write_reg32(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+} -+ -+static void do_in_ack(void) -+{ -+ gintsts_data_t gintsts; -+ hctsiz_data_t hctsiz; -+ hcchar_data_t hcchar; -+ haint_data_t haint; -+ hcint_data_t hcint; -+ host_grxsts_data_t grxsts; -+ -+ /* Enable HAINTs */ -+ dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001); -+ -+ /* Enable HCINTs */ -+ dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+ -+ /* Read HAINT */ -+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); -+ //fprintf(stderr, "HAINT: %08x\n", haint.d32); -+ -+ /* Read HCINT */ -+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); -+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); -+ -+ /* Clear HCINT */ -+ dwc_write_reg32(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ dwc_write_reg32(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+ -+ /* -+ * Receive Control In packet -+ */ -+ -+ /* Make sure channel is disabled */ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ if (hcchar.b.chen) { -+ //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32); -+ hcchar.b.chdis = 1; -+ hcchar.b.chen = 1; -+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); -+ //sleep(1); -+ MDELAY(1000); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+ -+ /* Read HAINT */ -+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); -+ //fprintf(stderr, "HAINT: %08x\n", haint.d32); -+ -+ /* Read HCINT */ -+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); -+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); -+ -+ /* Clear HCINT */ -+ dwc_write_reg32(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ dwc_write_reg32(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); -+ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ //if (hcchar.b.chen) { -+ // fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32); -+ //} -+ } -+ -+ /* Set HCTSIZ */ -+ hctsiz.d32 = 0; -+ hctsiz.b.xfersize = 8; -+ hctsiz.b.pktcnt = 1; -+ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1; -+ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); -+ -+ /* Set HCCHAR */ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; -+ hcchar.b.epdir = 1; -+ hcchar.b.epnum = 0; -+ hcchar.b.mps = 8; -+ hcchar.b.chen = 1; -+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); -+ -+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); -+ //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32); -+ -+ /* Wait for receive status queue interrupt */ -+ do { -+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); -+ } while (gintsts.b.rxstsqlvl == 0); -+ -+ //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32); -+ -+ /* Read RXSTS */ -+ grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp); -+ //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32); -+ -+ /* Clear RXSTSQLVL in GINTSTS */ -+ gintsts.d32 = 0; -+ gintsts.b.rxstsqlvl = 1; -+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); -+ -+ switch (grxsts.b.pktsts) { -+ case DWC_GRXSTS_PKTSTS_IN: -+ /* Read the data into the host buffer */ -+ if (grxsts.b.bcnt > 0) { -+ int i; -+ int word_count = (grxsts.b.bcnt + 3) / 4; -+ -+ data_fifo = (uint32_t *)((char *)global_regs + 0x1000); -+ -+ for (i = 0; i < word_count; i++) { -+ (void)dwc_read_reg32(data_fifo++); -+ } -+ } -+ -+ //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.b.bcnt); -+ break; -+ -+ default: -+ //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n"); -+ break; -+ } -+ -+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); -+ //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32); -+ -+ /* Wait for receive status queue interrupt */ -+ do { -+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); -+ } while (gintsts.b.rxstsqlvl == 0); -+ -+ //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32); -+ -+ /* Read RXSTS */ -+ grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp); -+ //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32); -+ -+ /* Clear RXSTSQLVL in GINTSTS */ -+ gintsts.d32 = 0; -+ gintsts.b.rxstsqlvl = 1; -+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); -+ -+ switch (grxsts.b.pktsts) { -+ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP: -+ break; -+ -+ default: -+ //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n"); -+ break; -+ } -+ -+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); -+ //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32); -+ -+ /* Wait for host channel interrupt */ -+ do { -+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); -+ } while (gintsts.b.hcintr == 0); -+ -+ //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32); -+ -+ /* Read HAINT */ -+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); -+ //fprintf(stderr, "HAINT: %08x\n", haint.d32); -+ -+ /* Read HCINT */ -+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); -+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); -+ -+ /* Clear HCINT */ -+ dwc_write_reg32(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ dwc_write_reg32(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+ -+ // usleep(100000); -+ // mdelay(100); -+ MDELAY(1); -+ -+ /* -+ * Send handshake packet -+ */ -+ -+ /* Read HAINT */ -+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); -+ //fprintf(stderr, "HAINT: %08x\n", haint.d32); -+ -+ /* Read HCINT */ -+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); -+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); -+ -+ /* Clear HCINT */ -+ dwc_write_reg32(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ dwc_write_reg32(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+ -+ /* Make sure channel is disabled */ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ if (hcchar.b.chen) { -+ //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32); -+ hcchar.b.chdis = 1; -+ hcchar.b.chen = 1; -+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); -+ //sleep(1); -+ MDELAY(1000); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+ -+ /* Read HAINT */ -+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); -+ //fprintf(stderr, "HAINT: %08x\n", haint.d32); -+ -+ /* Read HCINT */ -+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); -+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); -+ -+ /* Clear HCINT */ -+ dwc_write_reg32(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ dwc_write_reg32(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); -+ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ //if (hcchar.b.chen) { -+ // fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32); -+ //} -+ } -+ -+ /* Set HCTSIZ */ -+ hctsiz.d32 = 0; -+ hctsiz.b.xfersize = 0; -+ hctsiz.b.pktcnt = 1; -+ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1; -+ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); -+ -+ /* Set HCCHAR */ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; -+ hcchar.b.epdir = 0; -+ hcchar.b.epnum = 0; -+ hcchar.b.mps = 8; -+ hcchar.b.chen = 1; -+ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); -+ -+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); -+ //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32); -+ -+ /* Wait for host channel interrupt */ -+ do { -+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); -+ } while (gintsts.b.hcintr == 0); -+ -+ //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32); -+ -+ /* Disable HCINTs */ -+ dwc_write_reg32(&hc_regs->hcintmsk, 0x0000); -+ -+ /* Disable HAINTs */ -+ dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000); -+ -+ /* Read HAINT */ -+ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); -+ //fprintf(stderr, "HAINT: %08x\n", haint.d32); -+ -+ /* Read HCINT */ -+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); -+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); -+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); -+ -+ /* Clear HCINT */ -+ dwc_write_reg32(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ dwc_write_reg32(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+} -+#endif /* DWC_HS_ELECT_TST */ -+ -+/** Handles hub class-specific requests.*/ -+int dwc_otg_hcd_hub_control(struct usb_hcd *_hcd, -+ u16 _typeReq, -+ u16 _wValue, -+ u16 _wIndex, -+ char *_buf, -+ u16 _wLength) -+{ -+ int retval = 0; -+ -+ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd); -+ dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd (_hcd)->core_if; -+ struct usb_hub_descriptor *desc; -+ hprt0_data_t hprt0 = {.d32 = 0}; -+ -+ uint32_t port_status; -+ -+ switch (_typeReq) { -+ case ClearHubFeature: -+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "ClearHubFeature 0x%x\n", _wValue); -+ switch (_wValue) { -+ case C_HUB_LOCAL_POWER: -+ case C_HUB_OVER_CURRENT: -+ /* Nothing required here */ -+ break; -+ default: -+ retval = -EINVAL; -+ DWC_ERROR ("DWC OTG HCD - " -+ "ClearHubFeature request %xh unknown\n", _wValue); -+ } -+ break; -+ case ClearPortFeature: -+ if (!_wIndex || _wIndex > 1) -+ goto error; -+ -+ switch (_wValue) { -+ case USB_PORT_FEAT_ENABLE: -+ DWC_DEBUGPL (DBG_ANY, "DWC OTG HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); -+ hprt0.d32 = dwc_otg_read_hprt0 (core_if); -+ hprt0.b.prtena = 1; -+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); -+ break; -+ case USB_PORT_FEAT_SUSPEND: -+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); -+ hprt0.d32 = dwc_otg_read_hprt0 (core_if); -+ hprt0.b.prtres = 1; -+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); -+ /* Clear Resume bit */ -+ mdelay (100); -+ hprt0.b.prtres = 0; -+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); -+ break; -+ case USB_PORT_FEAT_POWER: -+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_POWER\n"); -+ hprt0.d32 = dwc_otg_read_hprt0 (core_if); -+ hprt0.b.prtpwr = 0; -+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); -+ break; -+ case USB_PORT_FEAT_INDICATOR: -+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); -+ /* Port inidicator not supported */ -+ break; -+ case USB_PORT_FEAT_C_CONNECTION: -+ /* Clears drivers internal connect status change -+ * flag */ -+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); -+ dwc_otg_hcd->flags.b.port_connect_status_change = 0; -+ break; -+ case USB_PORT_FEAT_C_RESET: -+ /* Clears the driver's internal Port Reset Change -+ * flag */ -+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); -+ dwc_otg_hcd->flags.b.port_reset_change = 0; -+ break; -+ case USB_PORT_FEAT_C_ENABLE: -+ /* Clears the driver's internal Port -+ * Enable/Disable Change flag */ -+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); -+ dwc_otg_hcd->flags.b.port_enable_change = 0; -+ break; -+ case USB_PORT_FEAT_C_SUSPEND: -+ /* Clears the driver's internal Port Suspend -+ * Change flag, which is set when resume signaling on -+ * the host port is complete */ -+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); -+ dwc_otg_hcd->flags.b.port_suspend_change = 0; -+ break; -+ case USB_PORT_FEAT_C_OVER_CURRENT: -+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); -+ dwc_otg_hcd->flags.b.port_over_current_change = 0; -+ break; -+ default: -+ retval = -EINVAL; -+ DWC_ERROR ("DWC OTG HCD - " -+ "ClearPortFeature request %xh " -+ "unknown or unsupported\n", _wValue); -+ } -+ break; -+ case GetHubDescriptor: -+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "GetHubDescriptor\n"); -+ desc = (struct usb_hub_descriptor *)_buf; -+ desc->bDescLength = 9; -+ desc->bDescriptorType = 0x29; -+ desc->bNbrPorts = 1; -+ desc->wHubCharacteristics = 0x08; -+ desc->bPwrOn2PwrGood = 1; -+ desc->bHubContrCurrent = 0; -+ desc->u.hs.DeviceRemovable[0] = 0; -+ desc->u.hs.DeviceRemovable[1] = 0xff; -+ break; -+ case GetHubStatus: -+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "GetHubStatus\n"); -+ memset (_buf, 0, 4); -+ break; -+ case GetPortStatus: -+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "GetPortStatus\n"); -+ -+ if (!_wIndex || _wIndex > 1) -+ goto error; -+ -+ port_status = 0; -+ -+ if (dwc_otg_hcd->flags.b.port_connect_status_change) -+ port_status |= (1 << USB_PORT_FEAT_C_CONNECTION); -+ -+ if (dwc_otg_hcd->flags.b.port_enable_change) -+ port_status |= (1 << USB_PORT_FEAT_C_ENABLE); -+ -+ if (dwc_otg_hcd->flags.b.port_suspend_change) -+ port_status |= (1 << USB_PORT_FEAT_C_SUSPEND); -+ -+ if (dwc_otg_hcd->flags.b.port_reset_change) -+ port_status |= (1 << USB_PORT_FEAT_C_RESET); -+ -+ if (dwc_otg_hcd->flags.b.port_over_current_change) { -+ DWC_ERROR("Device Not Supported\n"); -+ port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT); -+ } -+ -+ if (!dwc_otg_hcd->flags.b.port_connect_status) { -+ printk("DISCONNECTED PORT\n"); -+ /* -+ * The port is disconnected, which means the core is -+ * either in device mode or it soon will be. Just -+ * return 0's for the remainder of the port status -+ * since the port register can't be read if the core -+ * is in device mode. -+ */ -+#if 1 // winder. -+ *((u32 *) _buf) = cpu_to_le32(port_status); -+#else -+ *((__le32 *) _buf) = cpu_to_le32(port_status); -+#endif -+ break; -+ } -+ -+ hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0); -+ DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32); -+ -+ if (hprt0.b.prtconnsts) -+ port_status |= (1 << USB_PORT_FEAT_CONNECTION); -+ -+ if (hprt0.b.prtena) -+ port_status |= (1 << USB_PORT_FEAT_ENABLE); -+ -+ if (hprt0.b.prtsusp) -+ port_status |= (1 << USB_PORT_FEAT_SUSPEND); -+ -+ if (hprt0.b.prtovrcurract) -+ port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT); -+ -+ if (hprt0.b.prtrst) -+ port_status |= (1 << USB_PORT_FEAT_RESET); -+ -+ if (hprt0.b.prtpwr) -+ port_status |= (1 << USB_PORT_FEAT_POWER); -+ -+ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) -+ port_status |= USB_PORT_STAT_HIGH_SPEED; -+ -+ else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED) -+ port_status |= (1 << USB_PORT_FEAT_LOWSPEED); -+ -+ if (hprt0.b.prttstctl) -+ port_status |= (1 << USB_PORT_FEAT_TEST); -+ -+ /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ -+#if 1 // winder. -+ *((u32 *) _buf) = cpu_to_le32(port_status); -+#else -+ *((__le32 *) _buf) = cpu_to_le32(port_status); -+#endif -+ -+ break; -+ case SetHubFeature: -+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "SetHubFeature\n"); -+ /* No HUB features supported */ -+ break; -+ case SetPortFeature: -+ if (_wValue != USB_PORT_FEAT_TEST && (!_wIndex || _wIndex > 1)) -+ goto error; -+ -+ if (!dwc_otg_hcd->flags.b.port_connect_status) { -+ /* -+ * The port is disconnected, which means the core is -+ * either in device mode or it soon will be. Just -+ * return without doing anything since the port -+ * register can't be written if the core is in device -+ * mode. -+ */ -+ break; -+ } -+ -+ switch (_wValue) { -+ case USB_PORT_FEAT_SUSPEND: -+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); -+ if (_hcd->self.otg_port == _wIndex -+ && _hcd->self.b_hnp_enable) { -+ gotgctl_data_t gotgctl = {.d32=0}; -+ gotgctl.b.hstsethnpen = 1; -+ dwc_modify_reg32(&core_if->core_global_regs-> -+ gotgctl, 0, gotgctl.d32); -+ core_if->op_state = A_SUSPEND; -+ } -+ hprt0.d32 = dwc_otg_read_hprt0 (core_if); -+ hprt0.b.prtsusp = 1; -+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); -+ //DWC_PRINT( "SUSPEND: HPRT0=%0x\n", hprt0.d32); -+ /* Suspend the Phy Clock */ -+ { -+ pcgcctl_data_t pcgcctl = {.d32=0}; -+ pcgcctl.b.stoppclk = 1; -+ dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32); -+ } -+ -+ /* For HNP the bus must be suspended for at least 200ms.*/ -+ if (_hcd->self.b_hnp_enable) { -+ mdelay(200); -+ //DWC_PRINT( "SUSPEND: wait complete! (%d)\n", _hcd->state); -+ } -+ break; -+ case USB_PORT_FEAT_POWER: -+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "SetPortFeature - USB_PORT_FEAT_POWER\n"); -+ hprt0.d32 = dwc_otg_read_hprt0 (core_if); -+ hprt0.b.prtpwr = 1; -+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); -+ break; -+ case USB_PORT_FEAT_RESET: -+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "SetPortFeature - USB_PORT_FEAT_RESET\n"); -+ hprt0.d32 = dwc_otg_read_hprt0 (core_if); -+ /* TODO: Is this for OTG protocol?? -+ * We shoudl remove OTG totally for Danube system. -+ * But, in the future, maybe we need this. -+ */ -+#if 1 // winder -+ hprt0.b.prtrst = 1; -+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); -+#else -+ /* When B-Host the Port reset bit is set in -+ * the Start HCD Callback function, so that -+ * the reset is started within 1ms of the HNP -+ * success interrupt. */ -+ if (!_hcd->self.is_b_host) { -+ hprt0.b.prtrst = 1; -+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); -+ } -+#endif -+ /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ -+ MDELAY (60); -+ hprt0.b.prtrst = 0; -+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); -+ break; -+ -+#ifdef DWC_HS_ELECT_TST -+ case USB_PORT_FEAT_TEST: -+ { -+ uint32_t t; -+ gintmsk_data_t gintmsk; -+ -+ t = (_wIndex >> 8); /* MSB wIndex USB */ -+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t); -+ printk("USB_PORT_FEAT_TEST %d\n", t); -+ if (t < 6) { -+ hprt0.d32 = dwc_otg_read_hprt0 (core_if); -+ hprt0.b.prttstctl = t; -+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); -+ } else { -+ /* Setup global vars with reg addresses (quick and -+ * dirty hack, should be cleaned up) -+ */ -+ global_regs = core_if->core_global_regs; -+ hc_global_regs = core_if->host_if->host_global_regs; -+ hc_regs = (dwc_otg_hc_regs_t *)((char *)global_regs + 0x500); -+ data_fifo = (uint32_t *)((char *)global_regs + 0x1000); -+ -+ if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */ -+ /* Save current interrupt mask */ -+ gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); -+ -+ /* Disable all interrupts while we muck with -+ * the hardware directly -+ */ -+ dwc_write_reg32(&global_regs->gintmsk, 0); -+ -+ /* 15 second delay per the test spec */ -+ mdelay(15000); -+ -+ /* Drive suspend on the root port */ -+ hprt0.d32 = dwc_otg_read_hprt0 (core_if); -+ hprt0.b.prtsusp = 1; -+ hprt0.b.prtres = 0; -+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); -+ -+ /* 15 second delay per the test spec */ -+ mdelay(15000); -+ -+ /* Drive resume on the root port */ -+ hprt0.d32 = dwc_otg_read_hprt0 (core_if); -+ hprt0.b.prtsusp = 0; -+ hprt0.b.prtres = 1; -+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); -+ mdelay(100); -+ -+ /* Clear the resume bit */ -+ hprt0.b.prtres = 0; -+ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); -+ -+ /* Restore interrupts */ -+ dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); -+ } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */ -+ /* Save current interrupt mask */ -+ gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); -+ -+ /* Disable all interrupts while we muck with -+ * the hardware directly -+ */ -+ dwc_write_reg32(&global_regs->gintmsk, 0); -+ -+ /* 15 second delay per the test spec */ -+ mdelay(15000); -+ -+ /* Send the Setup packet */ -+ do_setup(); -+ -+ /* 15 second delay so nothing else happens for awhile */ -+ mdelay(15000); -+ -+ /* Restore interrupts */ -+ dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); -+ } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */ -+ /* Save current interrupt mask */ -+ gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); -+ -+ /* Disable all interrupts while we muck with -+ * the hardware directly -+ */ -+ dwc_write_reg32(&global_regs->gintmsk, 0); -+ -+ /* Send the Setup packet */ -+ do_setup(); -+ -+ /* 15 second delay so nothing else happens for awhile */ -+ mdelay(15000); -+ -+ /* Send the In and Ack packets */ -+ do_in_ack(); -+ -+ /* 15 second delay so nothing else happens for awhile */ -+ mdelay(15000); -+ -+ /* Restore interrupts */ -+ dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); -+ } -+ } -+ break; -+ } -+#endif /* DWC_HS_ELECT_TST */ -+ -+ case USB_PORT_FEAT_INDICATOR: -+ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " -+ "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); -+ /* Not supported */ -+ break; -+ default: -+ retval = -EINVAL; -+ DWC_ERROR ("DWC OTG HCD - " -+ "SetPortFeature request %xh " -+ "unknown or unsupported\n", _wValue); -+ break; -+ } -+ break; -+ default: -+error: -+ retval = -EINVAL; -+ DWC_WARN ("DWC OTG HCD - " -+ "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n", -+ _typeReq, _wIndex, _wValue); -+ break; -+ } -+ -+ return retval; -+} -+ -+ -+/** -+ * Assigns transactions from a QTD to a free host channel and initializes the -+ * host channel to perform the transactions. The host channel is removed from -+ * the free list. -+ * -+ * @param _hcd The HCD state structure. -+ * @param _qh Transactions from the first QTD for this QH are selected and -+ * assigned to a free host channel. -+ */ -+static void assign_and_init_hc(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh) -+{ -+ dwc_hc_t *hc; -+ dwc_otg_qtd_t *qtd; -+ struct urb *urb; -+ -+ DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, _hcd, _qh); -+ -+ hc = list_entry(_hcd->free_hc_list.next, dwc_hc_t, hc_list_entry); -+ -+ /* Remove the host channel from the free list. */ -+ list_del_init(&hc->hc_list_entry); -+ -+ qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); -+ urb = qtd->urb; -+ _qh->channel = hc; -+ _qh->qtd_in_process = qtd; -+ -+ /* -+ * Use usb_pipedevice to determine device address. This address is -+ * 0 before the SET_ADDRESS command and the correct address afterward. -+ */ -+ hc->dev_addr = usb_pipedevice(urb->pipe); -+ hc->ep_num = usb_pipeendpoint(urb->pipe); -+ -+ if (urb->dev->speed == USB_SPEED_LOW) { -+ hc->speed = DWC_OTG_EP_SPEED_LOW; -+ } else if (urb->dev->speed == USB_SPEED_FULL) { -+ hc->speed = DWC_OTG_EP_SPEED_FULL; -+ } else { -+ hc->speed = DWC_OTG_EP_SPEED_HIGH; -+ } -+ hc->max_packet = dwc_max_packet(_qh->maxp); -+ -+ hc->xfer_started = 0; -+ hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS; -+ hc->error_state = (qtd->error_count > 0); -+ hc->halt_on_queue = 0; -+ hc->halt_pending = 0; -+ hc->requests = 0; -+ -+ /* -+ * The following values may be modified in the transfer type section -+ * below. The xfer_len value may be reduced when the transfer is -+ * started to accommodate the max widths of the XferSize and PktCnt -+ * fields in the HCTSIZn register. -+ */ -+ hc->do_ping = _qh->ping_state; -+ hc->ep_is_in = (usb_pipein(urb->pipe) != 0); -+ hc->data_pid_start = _qh->data_toggle; -+ hc->multi_count = 1; -+ -+ if (_hcd->core_if->dma_enable) { -+ hc->xfer_buff = (uint8_t *)(u32)urb->transfer_dma + urb->actual_length; -+ } else { -+ hc->xfer_buff = (uint8_t *)urb->transfer_buffer + urb->actual_length; -+ } -+ hc->xfer_len = urb->transfer_buffer_length - urb->actual_length; -+ hc->xfer_count = 0; -+ -+ /* -+ * Set the split attributes -+ */ -+ hc->do_split = 0; -+ if (_qh->do_split) { -+ hc->do_split = 1; -+ hc->xact_pos = qtd->isoc_split_pos; -+ hc->complete_split = qtd->complete_split; -+ hc->hub_addr = urb->dev->tt->hub->devnum; -+ hc->port_addr = urb->dev->ttport; -+ } -+ -+ switch (usb_pipetype(urb->pipe)) { -+ case PIPE_CONTROL: -+ hc->ep_type = DWC_OTG_EP_TYPE_CONTROL; -+ switch (qtd->control_phase) { -+ case DWC_OTG_CONTROL_SETUP: -+ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n"); -+ hc->do_ping = 0; -+ hc->ep_is_in = 0; -+ hc->data_pid_start = DWC_OTG_HC_PID_SETUP; -+ if (_hcd->core_if->dma_enable) { -+ hc->xfer_buff = (uint8_t *)(u32)urb->setup_dma; -+ } else { -+ hc->xfer_buff = (uint8_t *)urb->setup_packet; -+ } -+ hc->xfer_len = 8; -+ break; -+ case DWC_OTG_CONTROL_DATA: -+ DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n"); -+ hc->data_pid_start = qtd->data_toggle; -+ break; -+ case DWC_OTG_CONTROL_STATUS: -+ /* -+ * Direction is opposite of data direction or IN if no -+ * data. -+ */ -+ DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n"); -+ if (urb->transfer_buffer_length == 0) { -+ hc->ep_is_in = 1; -+ } else { -+ hc->ep_is_in = (usb_pipein(urb->pipe) != USB_DIR_IN); -+ } -+ if (hc->ep_is_in) { -+ hc->do_ping = 0; -+ } -+ hc->data_pid_start = DWC_OTG_HC_PID_DATA1; -+ hc->xfer_len = 0; -+ if (_hcd->core_if->dma_enable) { -+ hc->xfer_buff = (uint8_t *)_hcd->status_buf_dma; -+ } else { -+ hc->xfer_buff = (uint8_t *)_hcd->status_buf; -+ } -+ break; -+ } -+ break; -+ case PIPE_BULK: -+ hc->ep_type = DWC_OTG_EP_TYPE_BULK; -+ break; -+ case PIPE_INTERRUPT: -+ hc->ep_type = DWC_OTG_EP_TYPE_INTR; -+ break; -+ case PIPE_ISOCHRONOUS: -+ { -+ struct usb_iso_packet_descriptor *frame_desc; -+ frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index]; -+ hc->ep_type = DWC_OTG_EP_TYPE_ISOC; -+ if (_hcd->core_if->dma_enable) { -+ hc->xfer_buff = (uint8_t *)(u32)urb->transfer_dma; -+ } else { -+ hc->xfer_buff = (uint8_t *)urb->transfer_buffer; -+ } -+ hc->xfer_buff += frame_desc->offset + qtd->isoc_split_offset; -+ hc->xfer_len = frame_desc->length - qtd->isoc_split_offset; -+ -+ if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) { -+ if (hc->xfer_len <= 188) { -+ hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL; -+ } -+ else { -+ hc->xact_pos = DWC_HCSPLIT_XACTPOS_BEGIN; -+ } -+ } -+ } -+ break; -+ } -+ -+ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || -+ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { -+ /* -+ * This value may be modified when the transfer is started to -+ * reflect the actual transfer length. -+ */ -+ hc->multi_count = dwc_hb_mult(_qh->maxp); -+ } -+ -+ dwc_otg_hc_init(_hcd->core_if, hc); -+ hc->qh = _qh; -+} -+#define DEBUG_HOST_CHANNELS -+#ifdef DEBUG_HOST_CHANNELS -+static int last_sel_trans_num_per_scheduled = 0; -+module_param(last_sel_trans_num_per_scheduled, int, 0444); -+ -+static int last_sel_trans_num_nonper_scheduled = 0; -+module_param(last_sel_trans_num_nonper_scheduled, int, 0444); -+ -+static int last_sel_trans_num_avail_hc_at_start = 0; -+module_param(last_sel_trans_num_avail_hc_at_start, int, 0444); -+ -+static int last_sel_trans_num_avail_hc_at_end = 0; -+module_param(last_sel_trans_num_avail_hc_at_end, int, 0444); -+#endif /* DEBUG_HOST_CHANNELS */ -+ -+/** -+ * This function selects transactions from the HCD transfer schedule and -+ * assigns them to available host channels. It is called from HCD interrupt -+ * handler functions. -+ * -+ * @param _hcd The HCD state structure. -+ * -+ * @return The types of new transactions that were assigned to host channels. -+ */ -+dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *_hcd) -+{ -+ struct list_head *qh_ptr; -+ dwc_otg_qh_t *qh; -+ int num_channels; -+ unsigned long flags; -+ dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE; -+ -+#ifdef DEBUG_SOF -+ DWC_DEBUGPL(DBG_HCD, " Select Transactions\n"); -+#endif /* */ -+ -+#ifdef DEBUG_HOST_CHANNELS -+ last_sel_trans_num_per_scheduled = 0; -+ last_sel_trans_num_nonper_scheduled = 0; -+ last_sel_trans_num_avail_hc_at_start = _hcd->available_host_channels; -+#endif /* DEBUG_HOST_CHANNELS */ -+ -+ /* Process entries in the periodic ready list. */ -+ num_channels = _hcd->core_if->core_params->host_channels; -+ qh_ptr = _hcd->periodic_sched_ready.next; -+ while (qh_ptr != &_hcd->periodic_sched_ready -+ && !list_empty(&_hcd->free_hc_list)) { -+ -+ // Make sure we leave one channel for non periodic transactions. -+ local_irq_save(flags); -+ if (_hcd->available_host_channels <= 1) { -+ local_irq_restore(flags); -+ break; -+ } -+ _hcd->available_host_channels--; -+ local_irq_restore(flags); -+#ifdef DEBUG_HOST_CHANNELS -+ last_sel_trans_num_per_scheduled++; -+#endif /* DEBUG_HOST_CHANNELS */ -+ -+ qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry); -+ assign_and_init_hc(_hcd, qh); -+ -+ /* -+ * Move the QH from the periodic ready schedule to the -+ * periodic assigned schedule. -+ */ -+ qh_ptr = qh_ptr->next; -+ local_irq_save(flags); -+ list_move(&qh->qh_list_entry, &_hcd->periodic_sched_assigned); -+ local_irq_restore(flags); -+ ret_val = DWC_OTG_TRANSACTION_PERIODIC; -+ } -+ -+ /* -+ * Process entries in the deferred portion of the non-periodic list. -+ * A NAK put them here and, at the right time, they need to be -+ * placed on the sched_inactive list. -+ */ -+ qh_ptr = _hcd->non_periodic_sched_deferred.next; -+ while (qh_ptr != &_hcd->non_periodic_sched_deferred) { -+ uint16_t frame_number = -+ dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd)); -+ qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry); -+ qh_ptr = qh_ptr->next; -+ -+ if (dwc_frame_num_le(qh->sched_frame, frame_number)) { -+ // NAK did this -+ /* -+ * Move the QH from the non periodic deferred schedule to -+ * the non periodic inactive schedule. -+ */ -+ local_irq_save(flags); -+ list_move(&qh->qh_list_entry, -+ &_hcd->non_periodic_sched_inactive); -+ local_irq_restore(flags); -+ } -+ } -+ -+ /* -+ * Process entries in the inactive portion of the non-periodic -+ * schedule. Some free host channels may not be used if they are -+ * reserved for periodic transfers. -+ */ -+ qh_ptr = _hcd->non_periodic_sched_inactive.next; -+ num_channels = _hcd->core_if->core_params->host_channels; -+ while (qh_ptr != &_hcd->non_periodic_sched_inactive -+ && !list_empty(&_hcd->free_hc_list)) { -+ -+ local_irq_save(flags); -+ if (_hcd->available_host_channels < 1) { -+ local_irq_restore(flags); -+ break; -+ } -+ _hcd->available_host_channels--; -+ local_irq_restore(flags); -+#ifdef DEBUG_HOST_CHANNELS -+ last_sel_trans_num_nonper_scheduled++; -+#endif /* DEBUG_HOST_CHANNELS */ -+ -+ qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry); -+ assign_and_init_hc(_hcd, qh); -+ -+ /* -+ * Move the QH from the non-periodic inactive schedule to the -+ * non-periodic active schedule. -+ */ -+ qh_ptr = qh_ptr->next; -+ local_irq_save(flags); -+ list_move(&qh->qh_list_entry, &_hcd->non_periodic_sched_active); -+ local_irq_restore(flags); -+ -+ if (ret_val == DWC_OTG_TRANSACTION_NONE) { -+ ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC; -+ } else { -+ ret_val = DWC_OTG_TRANSACTION_ALL; -+ } -+ -+ } -+#ifdef DEBUG_HOST_CHANNELS -+ last_sel_trans_num_avail_hc_at_end = _hcd->available_host_channels; -+#endif /* DEBUG_HOST_CHANNELS */ -+ -+ return ret_val; -+} -+ -+/** -+ * Attempts to queue a single transaction request for a host channel -+ * associated with either a periodic or non-periodic transfer. This function -+ * assumes that there is space available in the appropriate request queue. For -+ * an OUT transfer or SETUP transaction in Slave mode, it checks whether space -+ * is available in the appropriate Tx FIFO. -+ * -+ * @param _hcd The HCD state structure. -+ * @param _hc Host channel descriptor associated with either a periodic or -+ * non-periodic transfer. -+ * @param _fifo_dwords_avail Number of DWORDs available in the periodic Tx -+ * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic -+ * transfers. -+ * -+ * @return 1 if a request is queued and more requests may be needed to -+ * complete the transfer, 0 if no more requests are required for this -+ * transfer, -1 if there is insufficient space in the Tx FIFO. -+ */ -+static int queue_transaction(dwc_otg_hcd_t *_hcd, -+ dwc_hc_t *_hc, -+ uint16_t _fifo_dwords_avail) -+{ -+ int retval; -+ -+ if (_hcd->core_if->dma_enable) { -+ if (!_hc->xfer_started) { -+ dwc_otg_hc_start_transfer(_hcd->core_if, _hc); -+ _hc->qh->ping_state = 0; -+ } -+ retval = 0; -+ } else if (_hc->halt_pending) { -+ /* Don't queue a request if the channel has been halted. */ -+ retval = 0; -+ } else if (_hc->halt_on_queue) { -+ dwc_otg_hc_halt(_hcd->core_if, _hc, _hc->halt_status); -+ retval = 0; -+ } else if (_hc->do_ping) { -+ if (!_hc->xfer_started) { -+ dwc_otg_hc_start_transfer(_hcd->core_if, _hc); -+ } -+ retval = 0; -+ } else if (!_hc->ep_is_in || -+ _hc->data_pid_start == DWC_OTG_HC_PID_SETUP) { -+ if ((_fifo_dwords_avail * 4) >= _hc->max_packet) { -+ if (!_hc->xfer_started) { -+ dwc_otg_hc_start_transfer(_hcd->core_if, _hc); -+ retval = 1; -+ } else { -+ retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc); -+ } -+ } else { -+ retval = -1; -+ } -+ } else { -+ if (!_hc->xfer_started) { -+ dwc_otg_hc_start_transfer(_hcd->core_if, _hc); -+ retval = 1; -+ } else { -+ retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc); -+ } -+ } -+ -+ return retval; -+} -+ -+/** -+ * Processes active non-periodic channels and queues transactions for these -+ * channels to the DWC_otg controller. After queueing transactions, the NP Tx -+ * FIFO Empty interrupt is enabled if there are more transactions to queue as -+ * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx -+ * FIFO Empty interrupt is disabled. -+ */ -+static void process_non_periodic_channels(dwc_otg_hcd_t *_hcd) -+{ -+ gnptxsts_data_t tx_status; -+ struct list_head *orig_qh_ptr; -+ dwc_otg_qh_t *qh; -+ int status; -+ int no_queue_space = 0; -+ int no_fifo_space = 0; -+ int more_to_do = 0; -+ -+ dwc_otg_core_global_regs_t *global_regs = _hcd->core_if->core_global_regs; -+ -+ DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n"); -+#ifdef DEBUG -+ tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); -+ DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (before queue): %d\n", -+ tx_status.b.nptxqspcavail); -+ DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n", -+ tx_status.b.nptxfspcavail); -+#endif -+ /* -+ * Keep track of the starting point. Skip over the start-of-list -+ * entry. -+ */ -+ if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) { -+ _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next; -+ } -+ orig_qh_ptr = _hcd->non_periodic_qh_ptr; -+ -+ /* -+ * Process once through the active list or until no more space is -+ * available in the request queue or the Tx FIFO. -+ */ -+ do { -+ tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); -+ if (!_hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) { -+ no_queue_space = 1; -+ break; -+ } -+ -+ qh = list_entry(_hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry); -+ status = queue_transaction(_hcd, qh->channel, tx_status.b.nptxfspcavail); -+ -+ if (status > 0) { -+ more_to_do = 1; -+ } else if (status < 0) { -+ no_fifo_space = 1; -+ break; -+ } -+ -+ /* Advance to next QH, skipping start-of-list entry. */ -+ _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next; -+ if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) { -+ _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next; -+ } -+ -+ } while (_hcd->non_periodic_qh_ptr != orig_qh_ptr); -+ -+ if (!_hcd->core_if->dma_enable) { -+ gintmsk_data_t intr_mask = {.d32 = 0}; -+ intr_mask.b.nptxfempty = 1; -+ -+#ifdef DEBUG -+ tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); -+ DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (after queue): %d\n", -+ tx_status.b.nptxqspcavail); -+ DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (after queue): %d\n", -+ tx_status.b.nptxfspcavail); -+#endif -+ if (more_to_do || no_queue_space || no_fifo_space) { -+ /* -+ * May need to queue more transactions as the request -+ * queue or Tx FIFO empties. Enable the non-periodic -+ * Tx FIFO empty interrupt. (Always use the half-empty -+ * level to ensure that new requests are loaded as -+ * soon as possible.) -+ */ -+ dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32); -+ } else { -+ /* -+ * Disable the Tx FIFO empty interrupt since there are -+ * no more transactions that need to be queued right -+ * now. This function is called from interrupt -+ * handlers to queue more transactions as transfer -+ * states change. -+ */ -+ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0); -+ } -+ } -+} -+ -+/** -+ * Processes periodic channels for the next frame and queues transactions for -+ * these channels to the DWC_otg controller. After queueing transactions, the -+ * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions -+ * to queue as Periodic Tx FIFO or request queue space becomes available. -+ * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. -+ */ -+static void process_periodic_channels(dwc_otg_hcd_t *_hcd) -+{ -+ hptxsts_data_t tx_status; -+ struct list_head *qh_ptr; -+ dwc_otg_qh_t *qh; -+ int status; -+ int no_queue_space = 0; -+ int no_fifo_space = 0; -+ -+ dwc_otg_host_global_regs_t *host_regs; -+ host_regs = _hcd->core_if->host_if->host_global_regs; -+ -+ DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n"); -+#ifdef DEBUG -+ tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); -+ DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (before queue): %d\n", -+ tx_status.b.ptxqspcavail); -+ DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n", -+ tx_status.b.ptxfspcavail); -+#endif -+ -+ qh_ptr = _hcd->periodic_sched_assigned.next; -+ while (qh_ptr != &_hcd->periodic_sched_assigned) { -+ tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); -+ if (tx_status.b.ptxqspcavail == 0) { -+ no_queue_space = 1; -+ break; -+ } -+ -+ qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry); -+ -+ /* -+ * Set a flag if we're queuing high-bandwidth in slave mode. -+ * The flag prevents any halts to get into the request queue in -+ * the middle of multiple high-bandwidth packets getting queued. -+ */ -+ if ((!_hcd->core_if->dma_enable) && -+ (qh->channel->multi_count > 1)) -+ { -+ _hcd->core_if->queuing_high_bandwidth = 1; -+ } -+ -+ status = queue_transaction(_hcd, qh->channel, tx_status.b.ptxfspcavail); -+ if (status < 0) { -+ no_fifo_space = 1; -+ break; -+ } -+ -+ /* -+ * In Slave mode, stay on the current transfer until there is -+ * nothing more to do or the high-bandwidth request count is -+ * reached. In DMA mode, only need to queue one request. The -+ * controller automatically handles multiple packets for -+ * high-bandwidth transfers. -+ */ -+ if (_hcd->core_if->dma_enable || -+ (status == 0 || -+ qh->channel->requests == qh->channel->multi_count)) { -+ qh_ptr = qh_ptr->next; -+ /* -+ * Move the QH from the periodic assigned schedule to -+ * the periodic queued schedule. -+ */ -+ list_move(&qh->qh_list_entry, &_hcd->periodic_sched_queued); -+ -+ /* done queuing high bandwidth */ -+ _hcd->core_if->queuing_high_bandwidth = 0; -+ } -+ } -+ -+ if (!_hcd->core_if->dma_enable) { -+ dwc_otg_core_global_regs_t *global_regs; -+ gintmsk_data_t intr_mask = {.d32 = 0}; -+ -+ global_regs = _hcd->core_if->core_global_regs; -+ intr_mask.b.ptxfempty = 1; -+#ifdef DEBUG -+ tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); -+ DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (after queue): %d\n", -+ tx_status.b.ptxqspcavail); -+ DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (after queue): %d\n", -+ tx_status.b.ptxfspcavail); -+#endif -+ if (!(list_empty(&_hcd->periodic_sched_assigned)) || -+ no_queue_space || no_fifo_space) { -+ /* -+ * May need to queue more transactions as the request -+ * queue or Tx FIFO empties. Enable the periodic Tx -+ * FIFO empty interrupt. (Always use the half-empty -+ * level to ensure that new requests are loaded as -+ * soon as possible.) -+ */ -+ dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32); -+ } else { -+ /* -+ * Disable the Tx FIFO empty interrupt since there are -+ * no more transactions that need to be queued right -+ * now. This function is called from interrupt -+ * handlers to queue more transactions as transfer -+ * states change. -+ */ -+ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0); -+ } -+ } -+} -+ -+/** -+ * This function processes the currently active host channels and queues -+ * transactions for these channels to the DWC_otg controller. It is called -+ * from HCD interrupt handler functions. -+ * -+ * @param _hcd The HCD state structure. -+ * @param _tr_type The type(s) of transactions to queue (non-periodic, -+ * periodic, or both). -+ */ -+void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *_hcd, -+ dwc_otg_transaction_type_e _tr_type) -+{ -+#ifdef DEBUG_SOF -+ DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n"); -+#endif -+ /* Process host channels associated with periodic transfers. */ -+ if ((_tr_type == DWC_OTG_TRANSACTION_PERIODIC || -+ _tr_type == DWC_OTG_TRANSACTION_ALL) && -+ !list_empty(&_hcd->periodic_sched_assigned)) { -+ -+ process_periodic_channels(_hcd); -+ } -+ -+ /* Process host channels associated with non-periodic transfers. */ -+ if ((_tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC || -+ _tr_type == DWC_OTG_TRANSACTION_ALL)) { -+ if (!list_empty(&_hcd->non_periodic_sched_active)) { -+ process_non_periodic_channels(_hcd); -+ } else { -+ /* -+ * Ensure NP Tx FIFO empty interrupt is disabled when -+ * there are no non-periodic transfers to process. -+ */ -+ gintmsk_data_t gintmsk = {.d32 = 0}; -+ gintmsk.b.nptxfempty = 1; -+ dwc_modify_reg32(&_hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0); -+ } -+ } -+} -+ -+/** -+ * Sets the final status of an URB and returns it to the device driver. Any -+ * required cleanup of the URB is performed. -+ */ -+void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t * _hcd, struct urb *_urb, -+ int _status) -+ __releases(_hcd->lock) -+__acquires(_hcd->lock) -+{ -+#ifdef DEBUG -+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { -+ DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n", -+ __func__, _urb, usb_pipedevice(_urb->pipe), -+ usb_pipeendpoint(_urb->pipe), -+ usb_pipein(_urb->pipe) ? "IN" : "OUT", _status); -+ if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) { -+ int i; -+ for (i = 0; i < _urb->number_of_packets; i++) { -+ DWC_PRINT(" ISO Desc %d status: %d\n", -+ i, _urb->iso_frame_desc[i].status); -+ } -+ } -+ } -+#endif -+ -+ _urb->status = _status; -+ _urb->hcpriv = NULL; -+ usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(_hcd), _urb); -+ spin_unlock(&_hcd->lock); -+ usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(_hcd), _urb, _status); -+ spin_lock(&_hcd->lock); -+} -+ -+/* -+ * Returns the Queue Head for an URB. -+ */ -+dwc_otg_qh_t *dwc_urb_to_qh(struct urb *_urb) -+{ -+ struct usb_host_endpoint *ep = dwc_urb_to_endpoint(_urb); -+ return (dwc_otg_qh_t *)ep->hcpriv; -+} -+ -+#ifdef DEBUG -+void dwc_print_setup_data (uint8_t *setup) -+{ -+ int i; -+ if (CHK_DEBUG_LEVEL(DBG_HCD)){ -+ DWC_PRINT("Setup Data = MSB "); -+ for (i=7; i>=0; i--) DWC_PRINT ("%02x ", setup[i]); -+ DWC_PRINT("\n"); -+ DWC_PRINT(" bmRequestType Tranfer = %s\n", (setup[0]&0x80) ? "Device-to-Host" : "Host-to-Device"); -+ DWC_PRINT(" bmRequestType Type = "); -+ switch ((setup[0]&0x60) >> 5) { -+ case 0: DWC_PRINT("Standard\n"); break; -+ case 1: DWC_PRINT("Class\n"); break; -+ case 2: DWC_PRINT("Vendor\n"); break; -+ case 3: DWC_PRINT("Reserved\n"); break; -+ } -+ DWC_PRINT(" bmRequestType Recipient = "); -+ switch (setup[0]&0x1f) { -+ case 0: DWC_PRINT("Device\n"); break; -+ case 1: DWC_PRINT("Interface\n"); break; -+ case 2: DWC_PRINT("Endpoint\n"); break; -+ case 3: DWC_PRINT("Other\n"); break; -+ default: DWC_PRINT("Reserved\n"); break; -+ } -+ DWC_PRINT(" bRequest = 0x%0x\n", setup[1]); -+ DWC_PRINT(" wValue = 0x%0x\n", *((uint16_t *)&setup[2])); -+ DWC_PRINT(" wIndex = 0x%0x\n", *((uint16_t *)&setup[4])); -+ DWC_PRINT(" wLength = 0x%0x\n\n", *((uint16_t *)&setup[6])); -+ } -+} -+#endif -+ -+void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *_hcd) { -+#ifdef DEBUG -+#if 0 -+ DWC_PRINT("Frame remaining at SOF:\n"); -+ DWC_PRINT(" samples %u, accum %llu, avg %llu\n", -+ _hcd->frrem_samples, _hcd->frrem_accum, -+ (_hcd->frrem_samples > 0) ? -+ _hcd->frrem_accum/_hcd->frrem_samples : 0); -+ -+ DWC_PRINT("\n"); -+ DWC_PRINT("Frame remaining at start_transfer (uframe 7):\n"); -+ DWC_PRINT(" samples %u, accum %u, avg %u\n", -+ _hcd->core_if->hfnum_7_samples, _hcd->core_if->hfnum_7_frrem_accum, -+ (_hcd->core_if->hfnum_7_samples > 0) ? -+ _hcd->core_if->hfnum_7_frrem_accum/_hcd->core_if->hfnum_7_samples : 0); -+ DWC_PRINT("Frame remaining at start_transfer (uframe 0):\n"); -+ DWC_PRINT(" samples %u, accum %u, avg %u\n", -+ _hcd->core_if->hfnum_0_samples, _hcd->core_if->hfnum_0_frrem_accum, -+ (_hcd->core_if->hfnum_0_samples > 0) ? -+ _hcd->core_if->hfnum_0_frrem_accum/_hcd->core_if->hfnum_0_samples : 0); -+ DWC_PRINT("Frame remaining at start_transfer (uframe 1-6):\n"); -+ DWC_PRINT(" samples %u, accum %u, avg %u\n", -+ _hcd->core_if->hfnum_other_samples, _hcd->core_if->hfnum_other_frrem_accum, -+ (_hcd->core_if->hfnum_other_samples > 0) ? -+ _hcd->core_if->hfnum_other_frrem_accum/_hcd->core_if->hfnum_other_samples : 0); -+ -+ DWC_PRINT("\n"); -+ DWC_PRINT("Frame remaining at sample point A (uframe 7):\n"); -+ DWC_PRINT(" samples %u, accum %llu, avg %llu\n", -+ _hcd->hfnum_7_samples_a, _hcd->hfnum_7_frrem_accum_a, -+ (_hcd->hfnum_7_samples_a > 0) ? -+ _hcd->hfnum_7_frrem_accum_a/_hcd->hfnum_7_samples_a : 0); -+ DWC_PRINT("Frame remaining at sample point A (uframe 0):\n"); -+ DWC_PRINT(" samples %u, accum %llu, avg %llu\n", -+ _hcd->hfnum_0_samples_a, _hcd->hfnum_0_frrem_accum_a, -+ (_hcd->hfnum_0_samples_a > 0) ? -+ _hcd->hfnum_0_frrem_accum_a/_hcd->hfnum_0_samples_a : 0); -+ DWC_PRINT("Frame remaining at sample point A (uframe 1-6):\n"); -+ DWC_PRINT(" samples %u, accum %llu, avg %llu\n", -+ _hcd->hfnum_other_samples_a, _hcd->hfnum_other_frrem_accum_a, -+ (_hcd->hfnum_other_samples_a > 0) ? -+ _hcd->hfnum_other_frrem_accum_a/_hcd->hfnum_other_samples_a : 0); -+ -+ DWC_PRINT("\n"); -+ DWC_PRINT("Frame remaining at sample point B (uframe 7):\n"); -+ DWC_PRINT(" samples %u, accum %llu, avg %llu\n", -+ _hcd->hfnum_7_samples_b, _hcd->hfnum_7_frrem_accum_b, -+ (_hcd->hfnum_7_samples_b > 0) ? -+ _hcd->hfnum_7_frrem_accum_b/_hcd->hfnum_7_samples_b : 0); -+ DWC_PRINT("Frame remaining at sample point B (uframe 0):\n"); -+ DWC_PRINT(" samples %u, accum %llu, avg %llu\n", -+ _hcd->hfnum_0_samples_b, _hcd->hfnum_0_frrem_accum_b, -+ (_hcd->hfnum_0_samples_b > 0) ? -+ _hcd->hfnum_0_frrem_accum_b/_hcd->hfnum_0_samples_b : 0); -+ DWC_PRINT("Frame remaining at sample point B (uframe 1-6):\n"); -+ DWC_PRINT(" samples %u, accum %llu, avg %llu\n", -+ _hcd->hfnum_other_samples_b, _hcd->hfnum_other_frrem_accum_b, -+ (_hcd->hfnum_other_samples_b > 0) ? -+ _hcd->hfnum_other_frrem_accum_b/_hcd->hfnum_other_samples_b : 0); -+#endif -+#endif -+} -+ -+void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *_hcd) -+{ -+#ifdef DEBUG -+ int num_channels; -+ int i; -+ gnptxsts_data_t np_tx_status; -+ hptxsts_data_t p_tx_status; -+ -+ num_channels = _hcd->core_if->core_params->host_channels; -+ DWC_PRINT("\n"); -+ DWC_PRINT("************************************************************\n"); -+ DWC_PRINT("HCD State:\n"); -+ DWC_PRINT(" Num channels: %d\n", num_channels); -+ for (i = 0; i < num_channels; i++) { -+ dwc_hc_t *hc = _hcd->hc_ptr_array[i]; -+ DWC_PRINT(" Channel %d:\n", i); -+ DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n", -+ hc->dev_addr, hc->ep_num, hc->ep_is_in); -+ DWC_PRINT(" speed: %d\n", hc->speed); -+ DWC_PRINT(" ep_type: %d\n", hc->ep_type); -+ DWC_PRINT(" max_packet: %d\n", hc->max_packet); -+ DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start); -+ DWC_PRINT(" multi_count: %d\n", hc->multi_count); -+ DWC_PRINT(" xfer_started: %d\n", hc->xfer_started); -+ DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff); -+ DWC_PRINT(" xfer_len: %d\n", hc->xfer_len); -+ DWC_PRINT(" xfer_count: %d\n", hc->xfer_count); -+ DWC_PRINT(" halt_on_queue: %d\n", hc->halt_on_queue); -+ DWC_PRINT(" halt_pending: %d\n", hc->halt_pending); -+ DWC_PRINT(" halt_status: %d\n", hc->halt_status); -+ DWC_PRINT(" do_split: %d\n", hc->do_split); -+ DWC_PRINT(" complete_split: %d\n", hc->complete_split); -+ DWC_PRINT(" hub_addr: %d\n", hc->hub_addr); -+ DWC_PRINT(" port_addr: %d\n", hc->port_addr); -+ DWC_PRINT(" xact_pos: %d\n", hc->xact_pos); -+ DWC_PRINT(" requests: %d\n", hc->requests); -+ DWC_PRINT(" qh: %p\n", hc->qh); -+ if (hc->xfer_started) { -+ hfnum_data_t hfnum; -+ hcchar_data_t hcchar; -+ hctsiz_data_t hctsiz; -+ hcint_data_t hcint; -+ hcintmsk_data_t hcintmsk; -+ hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); -+ hcchar.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcchar); -+ hctsiz.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hctsiz); -+ hcint.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcint); -+ hcintmsk.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcintmsk); -+ DWC_PRINT(" hfnum: 0x%08x\n", hfnum.d32); -+ DWC_PRINT(" hcchar: 0x%08x\n", hcchar.d32); -+ DWC_PRINT(" hctsiz: 0x%08x\n", hctsiz.d32); -+ DWC_PRINT(" hcint: 0x%08x\n", hcint.d32); -+ DWC_PRINT(" hcintmsk: 0x%08x\n", hcintmsk.d32); -+ } -+ if (hc->xfer_started && (hc->qh != NULL) && (hc->qh->qtd_in_process != NULL)) { -+ dwc_otg_qtd_t *qtd; -+ struct urb *urb; -+ qtd = hc->qh->qtd_in_process; -+ urb = qtd->urb; -+ DWC_PRINT(" URB Info:\n"); -+ DWC_PRINT(" qtd: %p, urb: %p\n", qtd, urb); -+ if (urb != NULL) { -+ DWC_PRINT(" Dev: %d, EP: %d %s\n", -+ usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe), -+ usb_pipein(urb->pipe) ? "IN" : "OUT"); -+ DWC_PRINT(" Max packet size: %d\n", -+ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); -+ DWC_PRINT(" transfer_buffer: %p\n", urb->transfer_buffer); -+ DWC_PRINT(" transfer_dma: %p\n", (void *)urb->transfer_dma); -+ DWC_PRINT(" transfer_buffer_length: %d\n", urb->transfer_buffer_length); -+ DWC_PRINT(" actual_length: %d\n", urb->actual_length); -+ } -+ } -+ } -+ //DWC_PRINT(" non_periodic_channels: %d\n", _hcd->non_periodic_channels); -+ //DWC_PRINT(" periodic_channels: %d\n", _hcd->periodic_channels); -+ DWC_PRINT(" available_channels: %d\n", _hcd->available_host_channels); -+ DWC_PRINT(" periodic_usecs: %d\n", _hcd->periodic_usecs); -+ np_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->core_global_regs->gnptxsts); -+ DWC_PRINT(" NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail); -+ DWC_PRINT(" NP Tx FIFO Space Avail: %d\n", np_tx_status.b.nptxfspcavail); -+ p_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hptxsts); -+ DWC_PRINT(" P Tx Req Queue Space Avail: %d\n", p_tx_status.b.ptxqspcavail); -+ DWC_PRINT(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail); -+ dwc_otg_hcd_dump_frrem(_hcd); -+ dwc_otg_dump_global_registers(_hcd->core_if); -+ dwc_otg_dump_host_registers(_hcd->core_if); -+ DWC_PRINT("************************************************************\n"); -+ DWC_PRINT("\n"); -+#endif -+} -+#endif /* DWC_DEVICE_ONLY */ ---- /dev/null -+++ b/drivers/usb/dwc_otg/dwc_otg_hcd.h -@@ -0,0 +1,676 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd.h $ -+ * $Revision: 1.1.1.1 $ -+ * $Date: 2009-04-17 06:15:34 $ -+ * $Change: 537387 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+#ifndef DWC_DEVICE_ONLY -+#if !defined(__DWC_HCD_H__) -+#define __DWC_HCD_H__ -+ -+#include -+#include -+#include -+ -+struct lm_device; -+struct dwc_otg_device; -+ -+#include "dwc_otg_cil.h" -+//#include "dwc_otg_ifx.h" // winder -+ -+ -+/** -+ * @file -+ * -+ * This file contains the structures, constants, and interfaces for -+ * the Host Contoller Driver (HCD). -+ * -+ * The Host Controller Driver (HCD) is responsible for translating requests -+ * from the USB Driver into the appropriate actions on the DWC_otg controller. -+ * It isolates the USBD from the specifics of the controller by providing an -+ * API to the USBD. -+ */ -+ -+/** -+ * Phases for control transfers. -+ */ -+typedef enum dwc_otg_control_phase { -+ DWC_OTG_CONTROL_SETUP, -+ DWC_OTG_CONTROL_DATA, -+ DWC_OTG_CONTROL_STATUS -+} dwc_otg_control_phase_e; -+ -+/** Transaction types. */ -+typedef enum dwc_otg_transaction_type { -+ DWC_OTG_TRANSACTION_NONE, -+ DWC_OTG_TRANSACTION_PERIODIC, -+ DWC_OTG_TRANSACTION_NON_PERIODIC, -+ DWC_OTG_TRANSACTION_ALL -+} dwc_otg_transaction_type_e; -+ -+/** -+ * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, -+ * interrupt, or isochronous transfer. A single QTD is created for each URB -+ * (of one of these types) submitted to the HCD. The transfer associated with -+ * a QTD may require one or multiple transactions. -+ * -+ * A QTD is linked to a Queue Head, which is entered in either the -+ * non-periodic or periodic schedule for execution. When a QTD is chosen for -+ * execution, some or all of its transactions may be executed. After -+ * execution, the state of the QTD is updated. The QTD may be retired if all -+ * its transactions are complete or if an error occurred. Otherwise, it -+ * remains in the schedule so more transactions can be executed later. -+ */ -+struct dwc_otg_qh; -+typedef struct dwc_otg_qtd { -+ /** -+ * Determines the PID of the next data packet for the data phase of -+ * control transfers. Ignored for other transfer types.
-+ * One of the following values: -+ * - DWC_OTG_HC_PID_DATA0 -+ * - DWC_OTG_HC_PID_DATA1 -+ */ -+ uint8_t data_toggle; -+ -+ /** Current phase for control transfers (Setup, Data, or Status). */ -+ dwc_otg_control_phase_e control_phase; -+ -+ /** Keep track of the current split type -+ * for FS/LS endpoints on a HS Hub */ -+ uint8_t complete_split; -+ -+ /** How many bytes transferred during SSPLIT OUT */ -+ uint32_t ssplit_out_xfer_count; -+ -+ /** -+ * Holds the number of bus errors that have occurred for a transaction -+ * within this transfer. -+ */ -+ uint8_t error_count; -+ -+ /** -+ * Index of the next frame descriptor for an isochronous transfer. A -+ * frame descriptor describes the buffer position and length of the -+ * data to be transferred in the next scheduled (micro)frame of an -+ * isochronous transfer. It also holds status for that transaction. -+ * The frame index starts at 0. -+ */ -+ int isoc_frame_index; -+ -+ /** Position of the ISOC split on full/low speed */ -+ uint8_t isoc_split_pos; -+ -+ /** Position of the ISOC split in the buffer for the current frame */ -+ uint16_t isoc_split_offset; -+ -+ /** URB for this transfer */ -+ struct urb *urb; -+ -+ /** This list of QTDs */ -+ struct list_head qtd_list_entry; -+ -+ /* Field to track the qh pointer */ -+ struct dwc_otg_qh *qtd_qh_ptr; -+} dwc_otg_qtd_t; -+ -+/** -+ * A Queue Head (QH) holds the static characteristics of an endpoint and -+ * maintains a list of transfers (QTDs) for that endpoint. A QH structure may -+ * be entered in either the non-periodic or periodic schedule. -+ */ -+typedef struct dwc_otg_qh { -+ /** -+ * Endpoint type. -+ * One of the following values: -+ * - USB_ENDPOINT_XFER_CONTROL -+ * - USB_ENDPOINT_XFER_ISOC -+ * - USB_ENDPOINT_XFER_BULK -+ * - USB_ENDPOINT_XFER_INT -+ */ -+ uint8_t ep_type; -+ uint8_t ep_is_in; -+ -+ /** wMaxPacketSize Field of Endpoint Descriptor. */ -+ uint16_t maxp; -+ -+ /** -+ * Determines the PID of the next data packet for non-control -+ * transfers. Ignored for control transfers.
-+ * One of the following values: -+ * - DWC_OTG_HC_PID_DATA0 -+ * - DWC_OTG_HC_PID_DATA1 -+ */ -+ uint8_t data_toggle; -+ -+ /** Ping state if 1. */ -+ uint8_t ping_state; -+ -+ /** -+ * List of QTDs for this QH. -+ */ -+ struct list_head qtd_list; -+ -+ /** Host channel currently processing transfers for this QH. */ -+ dwc_hc_t *channel; -+ -+ /** QTD currently assigned to a host channel for this QH. */ -+ dwc_otg_qtd_t *qtd_in_process; -+ -+ /** Full/low speed endpoint on high-speed hub requires split. */ -+ uint8_t do_split; -+ -+ /** @name Periodic schedule information */ -+ /** @{ */ -+ -+ /** Bandwidth in microseconds per (micro)frame. */ -+ uint8_t usecs; -+ -+ /** Interval between transfers in (micro)frames. */ -+ uint16_t interval; -+ -+ /** -+ * (micro)frame to initialize a periodic transfer. The transfer -+ * executes in the following (micro)frame. -+ */ -+ uint16_t sched_frame; -+ -+ /** (micro)frame at which last start split was initialized. */ -+ uint16_t start_split_frame; -+ -+ /** @} */ -+ -+ uint16_t speed; -+ uint16_t frame_usecs[8]; -+ /** Entry for QH in either the periodic or non-periodic schedule. */ -+ struct list_head qh_list_entry; -+} dwc_otg_qh_t; -+ -+/** -+ * This structure holds the state of the HCD, including the non-periodic and -+ * periodic schedules. -+ */ -+typedef struct dwc_otg_hcd { -+ spinlock_t lock; -+ -+ /** DWC OTG Core Interface Layer */ -+ dwc_otg_core_if_t *core_if; -+ -+ /** Internal DWC HCD Flags */ -+ volatile union dwc_otg_hcd_internal_flags { -+ uint32_t d32; -+ struct { -+ unsigned port_connect_status_change : 1; -+ unsigned port_connect_status : 1; -+ unsigned port_reset_change : 1; -+ unsigned port_enable_change : 1; -+ unsigned port_suspend_change : 1; -+ unsigned port_over_current_change : 1; -+ unsigned reserved : 27; -+ } b; -+ } flags; -+ -+ /** -+ * Inactive items in the non-periodic schedule. This is a list of -+ * Queue Heads. Transfers associated with these Queue Heads are not -+ * currently assigned to a host channel. -+ */ -+ struct list_head non_periodic_sched_inactive; -+ -+ /** -+ * Deferred items in the non-periodic schedule. This is a list of -+ * Queue Heads. Transfers associated with these Queue Heads are not -+ * currently assigned to a host channel. -+ * When we get an NAK, the QH goes here. -+ */ -+ struct list_head non_periodic_sched_deferred; -+ -+ /** -+ * Active items in the non-periodic schedule. This is a list of -+ * Queue Heads. Transfers associated with these Queue Heads are -+ * currently assigned to a host channel. -+ */ -+ struct list_head non_periodic_sched_active; -+ -+ /** -+ * Pointer to the next Queue Head to process in the active -+ * non-periodic schedule. -+ */ -+ struct list_head *non_periodic_qh_ptr; -+ -+ /** -+ * Inactive items in the periodic schedule. This is a list of QHs for -+ * periodic transfers that are _not_ scheduled for the next frame. -+ * Each QH in the list has an interval counter that determines when it -+ * needs to be scheduled for execution. This scheduling mechanism -+ * allows only a simple calculation for periodic bandwidth used (i.e. -+ * must assume that all periodic transfers may need to execute in the -+ * same frame). However, it greatly simplifies scheduling and should -+ * be sufficient for the vast majority of OTG hosts, which need to -+ * connect to a small number of peripherals at one time. -+ * -+ * Items move from this list to periodic_sched_ready when the QH -+ * interval counter is 0 at SOF. -+ */ -+ struct list_head periodic_sched_inactive; -+ -+ /** -+ * List of periodic QHs that are ready for execution in the next -+ * frame, but have not yet been assigned to host channels. -+ * -+ * Items move from this list to periodic_sched_assigned as host -+ * channels become available during the current frame. -+ */ -+ struct list_head periodic_sched_ready; -+ -+ /** -+ * List of periodic QHs to be executed in the next frame that are -+ * assigned to host channels. -+ * -+ * Items move from this list to periodic_sched_queued as the -+ * transactions for the QH are queued to the DWC_otg controller. -+ */ -+ struct list_head periodic_sched_assigned; -+ -+ /** -+ * List of periodic QHs that have been queued for execution. -+ * -+ * Items move from this list to either periodic_sched_inactive or -+ * periodic_sched_ready when the channel associated with the transfer -+ * is released. If the interval for the QH is 1, the item moves to -+ * periodic_sched_ready because it must be rescheduled for the next -+ * frame. Otherwise, the item moves to periodic_sched_inactive. -+ */ -+ struct list_head periodic_sched_queued; -+ -+ /** -+ * Total bandwidth claimed so far for periodic transfers. This value -+ * is in microseconds per (micro)frame. The assumption is that all -+ * periodic transfers may occur in the same (micro)frame. -+ */ -+ uint16_t periodic_usecs; -+ -+ /** -+ * Total bandwidth claimed so far for all periodic transfers -+ * in a frame. -+ * This will include a mixture of HS and FS transfers. -+ * Units are microseconds per (micro)frame. -+ * We have a budget per frame and have to schedule -+ * transactions accordingly. -+ * Watch out for the fact that things are actually scheduled for the -+ * "next frame". -+ */ -+ uint16_t frame_usecs[8]; -+ -+ /** -+ * Frame number read from the core at SOF. The value ranges from 0 to -+ * DWC_HFNUM_MAX_FRNUM. -+ */ -+ uint16_t frame_number; -+ -+ /** -+ * Free host channels in the controller. This is a list of -+ * dwc_hc_t items. -+ */ -+ struct list_head free_hc_list; -+ -+ /** -+ * Number of available host channels. -+ */ -+ int available_host_channels; -+ -+ /** -+ * Array of pointers to the host channel descriptors. Allows accessing -+ * a host channel descriptor given the host channel number. This is -+ * useful in interrupt handlers. -+ */ -+ dwc_hc_t *hc_ptr_array[MAX_EPS_CHANNELS]; -+ -+ /** -+ * Buffer to use for any data received during the status phase of a -+ * control transfer. Normally no data is transferred during the status -+ * phase. This buffer is used as a bit bucket. -+ */ -+ uint8_t *status_buf; -+ -+ /** -+ * DMA address for status_buf. -+ */ -+ dma_addr_t status_buf_dma; -+#define DWC_OTG_HCD_STATUS_BUF_SIZE 64 -+ -+ /** -+ * Structure to allow starting the HCD in a non-interrupt context -+ * during an OTG role change. -+ */ -+ struct work_struct start_work; -+ struct usb_hcd *_p; -+ -+ /** -+ * Connection timer. An OTG host must display a message if the device -+ * does not connect. Started when the VBus power is turned on via -+ * sysfs attribute "buspower". -+ */ -+ struct timer_list conn_timer; -+ -+ /* Tasket to do a reset */ -+ struct tasklet_struct *reset_tasklet; -+ -+#ifdef DEBUG -+ uint32_t frrem_samples; -+ uint64_t frrem_accum; -+ -+ uint32_t hfnum_7_samples_a; -+ uint64_t hfnum_7_frrem_accum_a; -+ uint32_t hfnum_0_samples_a; -+ uint64_t hfnum_0_frrem_accum_a; -+ uint32_t hfnum_other_samples_a; -+ uint64_t hfnum_other_frrem_accum_a; -+ -+ uint32_t hfnum_7_samples_b; -+ uint64_t hfnum_7_frrem_accum_b; -+ uint32_t hfnum_0_samples_b; -+ uint64_t hfnum_0_frrem_accum_b; -+ uint32_t hfnum_other_samples_b; -+ uint64_t hfnum_other_frrem_accum_b; -+#endif -+ -+} dwc_otg_hcd_t; -+ -+/** Gets the dwc_otg_hcd from a struct usb_hcd */ -+static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd) -+{ -+ return (dwc_otg_hcd_t *)(hcd->hcd_priv); -+} -+ -+/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */ -+static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd) -+{ -+ return container_of((void *)dwc_otg_hcd, struct usb_hcd, hcd_priv); -+} -+ -+/** @name HCD Create/Destroy Functions */ -+/** @{ */ -+extern int __devinit dwc_otg_hcd_init(struct device *_dev, dwc_otg_device_t * dwc_otg_device); -+extern void dwc_otg_hcd_remove(struct device *_dev); -+/** @} */ -+ -+/** @name Linux HC Driver API Functions */ -+/** @{ */ -+ -+extern int dwc_otg_hcd_start(struct usb_hcd *hcd); -+extern void dwc_otg_hcd_stop(struct usb_hcd *hcd); -+extern int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd); -+extern void dwc_otg_hcd_free(struct usb_hcd *hcd); -+ -+extern int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd, -+ struct urb *urb, -+ gfp_t mem_flags); -+extern int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd, -+ struct urb *urb, -+ int status); -+extern irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd); -+ -+extern void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd, -+ struct usb_host_endpoint *ep); -+ -+extern int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd, -+ char *buf); -+extern int dwc_otg_hcd_hub_control(struct usb_hcd *hcd, -+ u16 typeReq, -+ u16 wValue, -+ u16 wIndex, -+ char *buf, -+ u16 wLength); -+ -+/** @} */ -+ -+/** @name Transaction Execution Functions */ -+/** @{ */ -+extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *_hcd); -+extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *_hcd, -+ dwc_otg_transaction_type_e _tr_type); -+extern void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *_hcd, struct urb *_urb, -+ int _status); -+/** @} */ -+ -+/** @name Interrupt Handler Functions */ -+/** @{ */ -+extern int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *_dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *_dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *_dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *_dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *_dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr (dwc_otg_hcd_t *_dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_disconnect_intr (dwc_otg_hcd_t *_dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *_dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *_dwc_otg_hcd, uint32_t _num); -+extern int32_t dwc_otg_hcd_handle_session_req_intr (dwc_otg_hcd_t *_dwc_otg_hcd); -+extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr (dwc_otg_hcd_t *_dwc_otg_hcd); -+/** @} */ -+ -+ -+/** @name Schedule Queue Functions */ -+/** @{ */ -+ -+/* Implemented in dwc_otg_hcd_queue.c */ -+extern dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *_hcd, struct urb *_urb); -+extern void dwc_otg_hcd_qh_init (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, struct urb *_urb); -+extern void dwc_otg_hcd_qh_free (dwc_otg_qh_t *_qh); -+extern int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh); -+extern void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh); -+extern void dwc_otg_hcd_qh_deactivate (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int sched_csplit); -+extern int dwc_otg_hcd_qh_deferr (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int delay); -+ -+/** Remove and free a QH */ -+static inline void dwc_otg_hcd_qh_remove_and_free (dwc_otg_hcd_t *_hcd, -+ dwc_otg_qh_t *_qh) -+{ -+ dwc_otg_hcd_qh_remove (_hcd, _qh); -+ dwc_otg_hcd_qh_free (_qh); -+} -+ -+/** Allocates memory for a QH structure. -+ * @return Returns the memory allocate or NULL on error. */ -+static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc (void) -+{ -+#ifdef _SC_BUILD_ -+ return (dwc_otg_qh_t *) kmalloc (sizeof(dwc_otg_qh_t), GFP_ATOMIC); -+#else -+ return (dwc_otg_qh_t *) kmalloc (sizeof(dwc_otg_qh_t), GFP_KERNEL); -+#endif -+} -+ -+extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *urb); -+extern void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, struct urb *urb); -+extern int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd); -+ -+/** Allocates memory for a QTD structure. -+ * @return Returns the memory allocate or NULL on error. */ -+static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc (void) -+{ -+#ifdef _SC_BUILD_ -+ return (dwc_otg_qtd_t *) kmalloc (sizeof(dwc_otg_qtd_t), GFP_ATOMIC); -+#else -+ return (dwc_otg_qtd_t *) kmalloc (sizeof(dwc_otg_qtd_t), GFP_KERNEL); -+#endif -+} -+ -+/** Frees the memory for a QTD structure. QTD should already be removed from -+ * list. -+ * @param[in] _qtd QTD to free.*/ -+static inline void dwc_otg_hcd_qtd_free (dwc_otg_qtd_t *_qtd) -+{ -+ kfree (_qtd); -+} -+ -+/** Removes a QTD from list. -+ * @param[in] _qtd QTD to remove from list. */ -+static inline void dwc_otg_hcd_qtd_remove (dwc_otg_qtd_t *_qtd) -+{ -+ unsigned long flags; -+ local_irq_save (flags); -+ list_del (&_qtd->qtd_list_entry); -+ local_irq_restore (flags); -+} -+ -+/** Remove and free a QTD */ -+static inline void dwc_otg_hcd_qtd_remove_and_free (dwc_otg_qtd_t *_qtd) -+{ -+ dwc_otg_hcd_qtd_remove (_qtd); -+ dwc_otg_hcd_qtd_free (_qtd); -+} -+ -+/** @} */ -+ -+ -+/** @name Internal Functions */ -+/** @{ */ -+dwc_otg_qh_t *dwc_urb_to_qh(struct urb *_urb); -+void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *_hcd); -+void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *_hcd); -+/** @} */ -+ -+ -+/** Gets the usb_host_endpoint associated with an URB. */ -+static inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *_urb) -+{ -+ struct usb_device *dev = _urb->dev; -+ int ep_num = usb_pipeendpoint(_urb->pipe); -+ if (usb_pipein(_urb->pipe)) -+ return dev->ep_in[ep_num]; -+ else -+ return dev->ep_out[ep_num]; -+} -+ -+/** -+ * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is -+ * qualified with its direction (possible 32 endpoints per device). -+ */ -+#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) \ -+ ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \ -+ ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4) -+ -+/** Gets the QH that contains the list_head */ -+#define dwc_list_to_qh(_list_head_ptr_) (container_of(_list_head_ptr_,dwc_otg_qh_t,qh_list_entry)) -+ -+/** Gets the QTD that contains the list_head */ -+#define dwc_list_to_qtd(_list_head_ptr_) (container_of(_list_head_ptr_,dwc_otg_qtd_t,qtd_list_entry)) -+ -+/** Check if QH is non-periodic */ -+#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == USB_ENDPOINT_XFER_BULK) || \ -+ (_qh_ptr_->ep_type == USB_ENDPOINT_XFER_CONTROL)) -+ -+/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */ -+#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03)) -+ -+/** Packet size for any kind of endpoint descriptor */ -+#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) -+ -+/** -+ * Returns true if _frame1 is less than or equal to _frame2. The comparison is -+ * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the -+ * frame number when the max frame number is reached. -+ */ -+static inline int dwc_frame_num_le(uint16_t _frame1, uint16_t _frame2) -+{ -+ return ((_frame2 - _frame1) & DWC_HFNUM_MAX_FRNUM) <= -+ (DWC_HFNUM_MAX_FRNUM >> 1); -+} -+ -+/** -+ * Returns true if _frame1 is greater than _frame2. The comparison is done -+ * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame -+ * number when the max frame number is reached. -+ */ -+static inline int dwc_frame_num_gt(uint16_t _frame1, uint16_t _frame2) -+{ -+ return (_frame1 != _frame2) && -+ (((_frame1 - _frame2) & DWC_HFNUM_MAX_FRNUM) < -+ (DWC_HFNUM_MAX_FRNUM >> 1)); -+} -+ -+/** -+ * Increments _frame by the amount specified by _inc. The addition is done -+ * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value. -+ */ -+static inline uint16_t dwc_frame_num_inc(uint16_t _frame, uint16_t _inc) -+{ -+ return (_frame + _inc) & DWC_HFNUM_MAX_FRNUM; -+} -+ -+static inline uint16_t dwc_full_frame_num (uint16_t _frame) -+{ -+ return ((_frame) & DWC_HFNUM_MAX_FRNUM) >> 3; -+} -+ -+static inline uint16_t dwc_micro_frame_num (uint16_t _frame) -+{ -+ return (_frame) & 0x7; -+} -+ -+#ifdef DEBUG -+/** -+ * Macro to sample the remaining PHY clocks left in the current frame. This -+ * may be used during debugging to determine the average time it takes to -+ * execute sections of code. There are two possible sample points, "a" and -+ * "b", so the _letter argument must be one of these values. -+ * -+ * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For -+ * example, "cat /sys/devices/lm0/hcd_frrem". -+ */ -+#define dwc_sample_frrem(_hcd, _qh, _letter) \ -+{ \ -+ hfnum_data_t hfnum; \ -+ dwc_otg_qtd_t *qtd; \ -+ qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \ -+ if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \ -+ hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \ -+ switch (hfnum.b.frnum & 0x7) { \ -+ case 7: \ -+ _hcd->hfnum_7_samples_##_letter++; \ -+ _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \ -+ break; \ -+ case 0: \ -+ _hcd->hfnum_0_samples_##_letter++; \ -+ _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \ -+ break; \ -+ default: \ -+ _hcd->hfnum_other_samples_##_letter++; \ -+ _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \ -+ break; \ -+ } \ -+ } \ -+} -+#else // DEBUG -+#define dwc_sample_frrem(_hcd, _qh, _letter) -+#endif // DEBUG -+#endif // __DWC_HCD_H__ -+#endif /* DWC_DEVICE_ONLY */ ---- /dev/null -+++ b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c -@@ -0,0 +1,1841 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_intr.c $ -+ * $Revision: 1.1.1.1 $ -+ * $Date: 2009-04-17 06:15:34 $ -+ * $Change: 553126 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+#ifndef DWC_DEVICE_ONLY -+ -+#include "dwc_otg_driver.h" -+#include "dwc_otg_hcd.h" -+#include "dwc_otg_regs.h" -+ -+const int erratum_usb09_patched = 0; -+const int deferral_on = 1; -+const int nak_deferral_delay = 8; -+const int nyet_deferral_delay = 1; -+/** @file -+ * This file contains the implementation of the HCD Interrupt handlers. -+ */ -+ -+/** This function handles interrupts for the HCD. */ -+int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *_dwc_otg_hcd) -+{ -+ int retval = 0; -+ -+ dwc_otg_core_if_t *core_if = _dwc_otg_hcd->core_if; -+ gintsts_data_t gintsts; -+#ifdef DEBUG -+ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; -+#endif -+ -+ /* Check if HOST Mode */ -+ if (dwc_otg_is_host_mode(core_if)) { -+ gintsts.d32 = dwc_otg_read_core_intr(core_if); -+ if (!gintsts.d32) { -+ return 0; -+ } -+ -+#ifdef DEBUG -+ /* Don't print debug message in the interrupt handler on SOF */ -+# ifndef DEBUG_SOF -+ if (gintsts.d32 != DWC_SOF_INTR_MASK) -+# endif -+ DWC_DEBUGPL (DBG_HCD, "\n"); -+#endif -+ -+#ifdef DEBUG -+# ifndef DEBUG_SOF -+ if (gintsts.d32 != DWC_SOF_INTR_MASK) -+# endif -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n", gintsts.d32); -+#endif -+ -+ if (gintsts.b.sofintr) { -+ retval |= dwc_otg_hcd_handle_sof_intr (_dwc_otg_hcd); -+ } -+ if (gintsts.b.rxstsqlvl) { -+ retval |= dwc_otg_hcd_handle_rx_status_q_level_intr (_dwc_otg_hcd); -+ } -+ if (gintsts.b.nptxfempty) { -+ retval |= dwc_otg_hcd_handle_np_tx_fifo_empty_intr (_dwc_otg_hcd); -+ } -+ if (gintsts.b.i2cintr) { -+ /** @todo Implement i2cintr handler. */ -+ } -+ if (gintsts.b.portintr) { -+ retval |= dwc_otg_hcd_handle_port_intr (_dwc_otg_hcd); -+ } -+ if (gintsts.b.hcintr) { -+ retval |= dwc_otg_hcd_handle_hc_intr (_dwc_otg_hcd); -+ } -+ if (gintsts.b.ptxfempty) { -+ retval |= dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (_dwc_otg_hcd); -+ } -+#ifdef DEBUG -+# ifndef DEBUG_SOF -+ if (gintsts.d32 != DWC_SOF_INTR_MASK) -+# endif -+ { -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Finished Servicing Interrupts\n"); -+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n", -+ dwc_read_reg32(&global_regs->gintsts)); -+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n", -+ dwc_read_reg32(&global_regs->gintmsk)); -+ } -+#endif -+ -+#ifdef DEBUG -+# ifndef DEBUG_SOF -+ if (gintsts.d32 != DWC_SOF_INTR_MASK) -+# endif -+ DWC_DEBUGPL (DBG_HCD, "\n"); -+#endif -+ -+ } -+ -+ return retval; -+} -+ -+#ifdef DWC_TRACK_MISSED_SOFS -+#warning Compiling code to track missed SOFs -+#define FRAME_NUM_ARRAY_SIZE 1000 -+/** -+ * This function is for debug only. -+ */ -+static inline void track_missed_sofs(uint16_t _curr_frame_number) { -+ static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE]; -+ static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE]; -+ static int frame_num_idx = 0; -+ static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM; -+ static int dumped_frame_num_array = 0; -+ -+ if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) { -+ if ((((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) != _curr_frame_number)) { -+ frame_num_array[frame_num_idx] = _curr_frame_number; -+ last_frame_num_array[frame_num_idx++] = last_frame_num; -+ } -+ } else if (!dumped_frame_num_array) { -+ int i; -+ printk(KERN_EMERG USB_DWC "Frame Last Frame\n"); -+ printk(KERN_EMERG USB_DWC "----- ----------\n"); -+ for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) { -+ printk(KERN_EMERG USB_DWC "0x%04x 0x%04x\n", -+ frame_num_array[i], last_frame_num_array[i]); -+ } -+ dumped_frame_num_array = 1; -+ } -+ last_frame_num = _curr_frame_number; -+} -+#endif -+ -+/** -+ * Handles the start-of-frame interrupt in host mode. Non-periodic -+ * transactions may be queued to the DWC_otg controller for the current -+ * (micro)frame. Periodic transactions may be queued to the controller for the -+ * next (micro)frame. -+ */ -+int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *_hcd) -+{ -+ hfnum_data_t hfnum; -+ struct list_head *qh_entry; -+ dwc_otg_qh_t *qh; -+ dwc_otg_transaction_type_e tr_type; -+ gintsts_data_t gintsts = {.d32 = 0}; -+ -+ hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); -+ -+#ifdef DEBUG_SOF -+ DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n"); -+#endif -+ -+ _hcd->frame_number = hfnum.b.frnum; -+ -+#ifdef DEBUG -+ _hcd->frrem_accum += hfnum.b.frrem; -+ _hcd->frrem_samples++; -+#endif -+ -+#ifdef DWC_TRACK_MISSED_SOFS -+ track_missed_sofs(_hcd->frame_number); -+#endif -+ -+ /* Determine whether any periodic QHs should be executed. */ -+ qh_entry = _hcd->periodic_sched_inactive.next; -+ while (qh_entry != &_hcd->periodic_sched_inactive) { -+ qh = list_entry(qh_entry, dwc_otg_qh_t, qh_list_entry); -+ qh_entry = qh_entry->next; -+ if (dwc_frame_num_le(qh->sched_frame, _hcd->frame_number)) { -+ /* -+ * Move QH to the ready list to be executed next -+ * (micro)frame. -+ */ -+ list_move(&qh->qh_list_entry, &_hcd->periodic_sched_ready); -+ } -+ } -+ -+ tr_type = dwc_otg_hcd_select_transactions(_hcd); -+ if (tr_type != DWC_OTG_TRANSACTION_NONE) { -+ dwc_otg_hcd_queue_transactions(_hcd, tr_type); -+ } -+ -+ /* Clear interrupt */ -+ gintsts.b.sofintr = 1; -+ dwc_write_reg32(&_hcd->core_if->core_global_regs->gintsts, gintsts.d32); -+ -+ return 1; -+} -+ -+/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at -+ * least one packet in the Rx FIFO. The packets are moved from the FIFO to -+ * memory if the DWC_otg controller is operating in Slave mode. */ -+int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *_dwc_otg_hcd) -+{ -+ host_grxsts_data_t grxsts; -+ dwc_hc_t *hc = NULL; -+ -+ DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n"); -+ -+ grxsts.d32 = dwc_read_reg32(&_dwc_otg_hcd->core_if->core_global_regs->grxstsp); -+ -+ hc = _dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum]; -+ -+ /* Packet Status */ -+ DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum); -+ DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt); -+ DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid, hc->data_pid_start); -+ DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts); -+ -+ switch (grxsts.b.pktsts) { -+ case DWC_GRXSTS_PKTSTS_IN: -+ /* Read the data into the host buffer. */ -+ if (grxsts.b.bcnt > 0) { -+ dwc_otg_read_packet(_dwc_otg_hcd->core_if, -+ hc->xfer_buff, -+ grxsts.b.bcnt); -+ -+ /* Update the HC fields for the next packet received. */ -+ hc->xfer_count += grxsts.b.bcnt; -+ hc->xfer_buff += grxsts.b.bcnt; -+ } -+ -+ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP: -+ case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR: -+ case DWC_GRXSTS_PKTSTS_CH_HALTED: -+ /* Handled in interrupt, just ignore data */ -+ break; -+ default: -+ DWC_ERROR ("RX_STS_Q Interrupt: Unknown status %d\n", grxsts.b.pktsts); -+ break; -+ } -+ -+ return 1; -+} -+ -+/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More -+ * data packets may be written to the FIFO for OUT transfers. More requests -+ * may be written to the non-periodic request queue for IN transfers. This -+ * interrupt is enabled only in Slave mode. */ -+int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd) -+{ -+ DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n"); -+ dwc_otg_hcd_queue_transactions(_dwc_otg_hcd, -+ DWC_OTG_TRANSACTION_NON_PERIODIC); -+ return 1; -+} -+ -+/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data -+ * packets may be written to the FIFO for OUT transfers. More requests may be -+ * written to the periodic request queue for IN transfers. This interrupt is -+ * enabled only in Slave mode. */ -+int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd) -+{ -+ DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n"); -+ dwc_otg_hcd_queue_transactions(_dwc_otg_hcd, -+ DWC_OTG_TRANSACTION_PERIODIC); -+ return 1; -+} -+ -+/** There are multiple conditions that can cause a port interrupt. This function -+ * determines which interrupt conditions have occurred and handles them -+ * appropriately. */ -+int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *_dwc_otg_hcd) -+{ -+ int retval = 0; -+ hprt0_data_t hprt0; -+ hprt0_data_t hprt0_modify; -+ -+ hprt0.d32 = dwc_read_reg32(_dwc_otg_hcd->core_if->host_if->hprt0); -+ hprt0_modify.d32 = dwc_read_reg32(_dwc_otg_hcd->core_if->host_if->hprt0); -+ -+ /* Clear appropriate bits in HPRT0 to clear the interrupt bit in -+ * GINTSTS */ -+ -+ hprt0_modify.b.prtena = 0; -+ hprt0_modify.b.prtconndet = 0; -+ hprt0_modify.b.prtenchng = 0; -+ hprt0_modify.b.prtovrcurrchng = 0; -+ -+ /* Port Connect Detected -+ * Set flag and clear if detected */ -+ if (hprt0.b.prtconndet) { -+ DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x " -+ "Port Connect Detected--\n", hprt0.d32); -+ _dwc_otg_hcd->flags.b.port_connect_status_change = 1; -+ _dwc_otg_hcd->flags.b.port_connect_status = 1; -+ hprt0_modify.b.prtconndet = 1; -+ -+ /* B-Device has connected, Delete the connection timer. */ -+ del_timer( &_dwc_otg_hcd->conn_timer ); -+ -+ /* The Hub driver asserts a reset when it sees port connect -+ * status change flag */ -+ retval |= 1; -+ } -+ -+ /* Port Enable Changed -+ * Clear if detected - Set internal flag if disabled */ -+ if (hprt0.b.prtenchng) { -+ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " -+ "Port Enable Changed--\n", hprt0.d32); -+ hprt0_modify.b.prtenchng = 1; -+ if (hprt0.b.prtena == 1) { -+ int do_reset = 0; -+ dwc_otg_core_params_t *params = _dwc_otg_hcd->core_if->core_params; -+ dwc_otg_core_global_regs_t *global_regs = _dwc_otg_hcd->core_if->core_global_regs; -+ dwc_otg_host_if_t *host_if = _dwc_otg_hcd->core_if->host_if; -+ -+ /* Check if we need to adjust the PHY clock speed for -+ * low power and adjust it */ -+ if (params->host_support_fs_ls_low_power) -+ { -+ gusbcfg_data_t usbcfg; -+ -+ usbcfg.d32 = dwc_read_reg32 (&global_regs->gusbcfg); -+ -+ if ((hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED) || -+ (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED)) -+ { -+ /* -+ * Low power -+ */ -+ hcfg_data_t hcfg; -+ if (usbcfg.b.phylpwrclksel == 0) { -+ /* Set PHY low power clock select for FS/LS devices */ -+ usbcfg.b.phylpwrclksel = 1; -+ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); -+ do_reset = 1; -+ } -+ -+ hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg); -+ -+ if ((hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED) && -+ (params->host_ls_low_power_phy_clk == -+ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) -+ { -+ /* 6 MHZ */ -+ DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 6 MHz (Low Power)\n"); -+ if (hcfg.b.fslspclksel != DWC_HCFG_6_MHZ) { -+ hcfg.b.fslspclksel = DWC_HCFG_6_MHZ; -+ dwc_write_reg32(&host_if->host_global_regs->hcfg, -+ hcfg.d32); -+ do_reset = 1; -+ } -+ } -+ else { -+ /* 48 MHZ */ -+ DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 48 MHz ()\n"); -+ if (hcfg.b.fslspclksel != DWC_HCFG_48_MHZ) { -+ hcfg.b.fslspclksel = DWC_HCFG_48_MHZ; -+ dwc_write_reg32(&host_if->host_global_regs->hcfg, -+ hcfg.d32); -+ do_reset = 1; -+ } -+ } -+ } -+ else { -+ /* -+ * Not low power -+ */ -+ if (usbcfg.b.phylpwrclksel == 1) { -+ usbcfg.b.phylpwrclksel = 0; -+ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); -+ do_reset = 1; -+ } -+ } -+ -+ if (do_reset) { -+ tasklet_schedule(_dwc_otg_hcd->reset_tasklet); -+ } -+ } -+ -+ if (!do_reset) { -+ /* Port has been enabled set the reset change flag */ -+ _dwc_otg_hcd->flags.b.port_reset_change = 1; -+ } -+ -+ } else { -+ _dwc_otg_hcd->flags.b.port_enable_change = 1; -+ } -+ retval |= 1; -+ } -+ -+ /** Overcurrent Change Interrupt */ -+ if (hprt0.b.prtovrcurrchng) { -+ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " -+ "Port Overcurrent Changed--\n", hprt0.d32); -+ _dwc_otg_hcd->flags.b.port_over_current_change = 1; -+ hprt0_modify.b.prtovrcurrchng = 1; -+ retval |= 1; -+ } -+ -+ /* Clear Port Interrupts */ -+ dwc_write_reg32(_dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32); -+ -+ return retval; -+} -+ -+ -+/** This interrupt indicates that one or more host channels has a pending -+ * interrupt. There are multiple conditions that can cause each host channel -+ * interrupt. This function determines which conditions have occurred for each -+ * host channel interrupt and handles them appropriately. */ -+int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *_dwc_otg_hcd) -+{ -+ int i; -+ int retval = 0; -+ haint_data_t haint; -+ -+ /* Clear appropriate bits in HCINTn to clear the interrupt bit in -+ * GINTSTS */ -+ -+ haint.d32 = dwc_otg_read_host_all_channels_intr(_dwc_otg_hcd->core_if); -+ -+ for (i=0; i<_dwc_otg_hcd->core_if->core_params->host_channels; i++) { -+ if (haint.b2.chint & (1 << i)) { -+ retval |= dwc_otg_hcd_handle_hc_n_intr (_dwc_otg_hcd, i); -+ } -+ } -+ -+ return retval; -+} -+ -+/* Macro used to clear one channel interrupt */ -+#define clear_hc_int(_hc_regs_,_intr_) \ -+do { \ -+ hcint_data_t hcint_clear = {.d32 = 0}; \ -+ hcint_clear.b._intr_ = 1; \ -+ dwc_write_reg32(&((_hc_regs_)->hcint), hcint_clear.d32); \ -+} while (0) -+ -+/* -+ * Macro used to disable one channel interrupt. Channel interrupts are -+ * disabled when the channel is halted or released by the interrupt handler. -+ * There is no need to handle further interrupts of that type until the -+ * channel is re-assigned. In fact, subsequent handling may cause crashes -+ * because the channel structures are cleaned up when the channel is released. -+ */ -+#define disable_hc_int(_hc_regs_,_intr_) \ -+do { \ -+ hcintmsk_data_t hcintmsk = {.d32 = 0}; \ -+ hcintmsk.b._intr_ = 1; \ -+ dwc_modify_reg32(&((_hc_regs_)->hcintmsk), hcintmsk.d32, 0); \ -+} while (0) -+ -+/** -+ * Gets the actual length of a transfer after the transfer halts. _halt_status -+ * holds the reason for the halt. -+ * -+ * For IN transfers where _halt_status is DWC_OTG_HC_XFER_COMPLETE, -+ * *_short_read is set to 1 upon return if less than the requested -+ * number of bytes were transferred. Otherwise, *_short_read is set to 0 upon -+ * return. _short_read may also be NULL on entry, in which case it remains -+ * unchanged. -+ */ -+static uint32_t get_actual_xfer_length(dwc_hc_t *_hc, -+ dwc_otg_hc_regs_t *_hc_regs, -+ dwc_otg_qtd_t *_qtd, -+ dwc_otg_halt_status_e _halt_status, -+ int *_short_read) -+{ -+ hctsiz_data_t hctsiz; -+ uint32_t length; -+ -+ if (_short_read != NULL) { -+ *_short_read = 0; -+ } -+ hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz); -+ -+ if (_halt_status == DWC_OTG_HC_XFER_COMPLETE) { -+ if (_hc->ep_is_in) { -+ length = _hc->xfer_len - hctsiz.b.xfersize; -+ if (_short_read != NULL) { -+ *_short_read = (hctsiz.b.xfersize != 0); -+ } -+ } else if (_hc->qh->do_split) { -+ length = _qtd->ssplit_out_xfer_count; -+ } else { -+ length = _hc->xfer_len; -+ } -+ } else { -+ /* -+ * Must use the hctsiz.pktcnt field to determine how much data -+ * has been transferred. This field reflects the number of -+ * packets that have been transferred via the USB. This is -+ * always an integral number of packets if the transfer was -+ * halted before its normal completion. (Can't use the -+ * hctsiz.xfersize field because that reflects the number of -+ * bytes transferred via the AHB, not the USB). -+ */ -+ length = (_hc->start_pkt_count - hctsiz.b.pktcnt) * _hc->max_packet; -+ } -+ -+ return length; -+} -+ -+/** -+ * Updates the state of the URB after a Transfer Complete interrupt on the -+ * host channel. Updates the actual_length field of the URB based on the -+ * number of bytes transferred via the host channel. Sets the URB status -+ * if the data transfer is finished. -+ * -+ * @return 1 if the data transfer specified by the URB is completely finished, -+ * 0 otherwise. -+ */ -+static int update_urb_state_xfer_comp(dwc_hc_t *_hc, -+ dwc_otg_hc_regs_t * _hc_regs, struct urb *_urb, -+ dwc_otg_qtd_t * _qtd, int *status) -+{ -+ int xfer_done = 0; -+ int short_read = 0; -+ -+ _urb->actual_length += get_actual_xfer_length(_hc, _hc_regs, _qtd, -+ DWC_OTG_HC_XFER_COMPLETE, -+ &short_read); -+ -+ if (short_read || (_urb->actual_length == _urb->transfer_buffer_length)) { -+ xfer_done = 1; -+ if (short_read && (_urb->transfer_flags & URB_SHORT_NOT_OK)) { -+ *status = -EREMOTEIO; -+ } else { -+ *status = 0; -+ } -+ } -+ -+#ifdef DEBUG -+ { -+ hctsiz_data_t hctsiz; -+ hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz); -+ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n", -+ __func__, (_hc->ep_is_in ? "IN" : "OUT"), _hc->hc_num); -+ DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", _hc->xfer_len); -+ DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n", hctsiz.b.xfersize); -+ DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n", -+ _urb->transfer_buffer_length); -+ DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", _urb->actual_length); -+ DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n", -+ short_read, xfer_done); -+ } -+#endif -+ -+ return xfer_done; -+} -+ -+/* -+ * Save the starting data toggle for the next transfer. The data toggle is -+ * saved in the QH for non-control transfers and it's saved in the QTD for -+ * control transfers. -+ */ -+static void save_data_toggle(dwc_hc_t *_hc, -+ dwc_otg_hc_regs_t *_hc_regs, -+ dwc_otg_qtd_t *_qtd) -+{ -+ hctsiz_data_t hctsiz; -+ hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz); -+ -+ if (_hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) { -+ dwc_otg_qh_t *qh = _hc->qh; -+ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) { -+ qh->data_toggle = DWC_OTG_HC_PID_DATA0; -+ } else { -+ qh->data_toggle = DWC_OTG_HC_PID_DATA1; -+ } -+ } else { -+ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) { -+ _qtd->data_toggle = DWC_OTG_HC_PID_DATA0; -+ } else { -+ _qtd->data_toggle = DWC_OTG_HC_PID_DATA1; -+ } -+ } -+} -+ -+/** -+ * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic -+ * QHs, removes the QH from the active non-periodic schedule. If any QTDs are -+ * still linked to the QH, the QH is added to the end of the inactive -+ * non-periodic schedule. For periodic QHs, removes the QH from the periodic -+ * schedule if no more QTDs are linked to the QH. -+ */ -+static void deactivate_qh(dwc_otg_hcd_t *_hcd, -+ dwc_otg_qh_t *_qh, -+ int free_qtd) -+{ -+ int continue_split = 0; -+ dwc_otg_qtd_t *qtd; -+ -+ DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, _hcd, _qh, free_qtd); -+ -+ qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); -+ -+ if (qtd->complete_split) { -+ continue_split = 1; -+ } -+ else if ((qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID) || -+ (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END)) -+ { -+ continue_split = 1; -+ } -+ -+ if (free_qtd) { -+ /* -+ * Note that this was previously a call to -+ * dwc_otg_hcd_qtd_remove_and_free(qtd), which frees the qtd. -+ * However, that call frees the qtd memory, and we continue in the -+ * interrupt logic to access it many more times, including writing -+ * to it. With slub debugging on, it is clear that we were writing -+ * to memory we had freed. -+ * Call this instead, and now I have moved the freeing of the memory to -+ * the end of processing this interrupt. -+ */ -+ //dwc_otg_hcd_qtd_remove_and_free(qtd); -+ dwc_otg_hcd_qtd_remove(qtd); -+ -+ continue_split = 0; -+ } -+ -+ _qh->channel = NULL; -+ _qh->qtd_in_process = NULL; -+ dwc_otg_hcd_qh_deactivate(_hcd, _qh, continue_split); -+} -+ -+/** -+ * Updates the state of an Isochronous URB when the transfer is stopped for -+ * any reason. The fields of the current entry in the frame descriptor array -+ * are set based on the transfer state and the input _halt_status. Completes -+ * the Isochronous URB if all the URB frames have been completed. -+ * -+ * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be -+ * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE. -+ */ -+static dwc_otg_halt_status_e -+update_isoc_urb_state(dwc_otg_hcd_t *_hcd, -+ dwc_hc_t *_hc, -+ dwc_otg_hc_regs_t *_hc_regs, -+ dwc_otg_qtd_t *_qtd, -+ dwc_otg_halt_status_e _halt_status) -+{ -+ struct urb *urb = _qtd->urb; -+ dwc_otg_halt_status_e ret_val = _halt_status; -+ struct usb_iso_packet_descriptor *frame_desc; -+ -+ frame_desc = &urb->iso_frame_desc[_qtd->isoc_frame_index]; -+ switch (_halt_status) { -+ case DWC_OTG_HC_XFER_COMPLETE: -+ frame_desc->status = 0; -+ frame_desc->actual_length = -+ get_actual_xfer_length(_hc, _hc_regs, _qtd, -+ _halt_status, NULL); -+ break; -+ case DWC_OTG_HC_XFER_FRAME_OVERRUN: -+ urb->error_count++; -+ if (_hc->ep_is_in) { -+ frame_desc->status = -ENOSR; -+ } else { -+ frame_desc->status = -ECOMM; -+ } -+ frame_desc->actual_length = 0; -+ break; -+ case DWC_OTG_HC_XFER_BABBLE_ERR: -+ urb->error_count++; -+ frame_desc->status = -EOVERFLOW; -+ /* Don't need to update actual_length in this case. */ -+ break; -+ case DWC_OTG_HC_XFER_XACT_ERR: -+ urb->error_count++; -+ frame_desc->status = -EPROTO; -+ frame_desc->actual_length = -+ get_actual_xfer_length(_hc, _hc_regs, _qtd, -+ _halt_status, NULL); -+ default: -+ DWC_ERROR("%s: Unhandled _halt_status (%d)\n", __func__, -+ _halt_status); -+ BUG(); -+ break; -+ } -+ -+ if (++_qtd->isoc_frame_index == urb->number_of_packets) { -+ /* -+ * urb->status is not used for isoc transfers. -+ * The individual frame_desc statuses are used instead. -+ */ -+ dwc_otg_hcd_complete_urb(_hcd, urb, 0); -+ ret_val = DWC_OTG_HC_XFER_URB_COMPLETE; -+ } else { -+ ret_val = DWC_OTG_HC_XFER_COMPLETE; -+ } -+ -+ return ret_val; -+} -+ -+/** -+ * Releases a host channel for use by other transfers. Attempts to select and -+ * queue more transactions since at least one host channel is available. -+ * -+ * @param _hcd The HCD state structure. -+ * @param _hc The host channel to release. -+ * @param _qtd The QTD associated with the host channel. This QTD may be freed -+ * if the transfer is complete or an error has occurred. -+ * @param _halt_status Reason the channel is being released. This status -+ * determines the actions taken by this function. -+ */ -+static void release_channel(dwc_otg_hcd_t *_hcd, -+ dwc_hc_t *_hc, -+ dwc_otg_qtd_t *_qtd, -+ dwc_otg_halt_status_e _halt_status, -+ int *must_free) -+{ -+ dwc_otg_transaction_type_e tr_type; -+ int free_qtd; -+ dwc_otg_qh_t * _qh; -+ int deact = 1; -+ int retry_delay = 1; -+ unsigned long flags; -+ -+ DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d\n", __func__, -+ _hc->hc_num, _halt_status); -+ -+ switch (_halt_status) { -+ case DWC_OTG_HC_XFER_NYET: -+ case DWC_OTG_HC_XFER_NAK: -+ if (_halt_status == DWC_OTG_HC_XFER_NYET) { -+ retry_delay = nyet_deferral_delay; -+ } else { -+ retry_delay = nak_deferral_delay; -+ } -+ free_qtd = 0; -+ if (deferral_on && _hc->do_split) { -+ _qh = _hc->qh; -+ if (_qh) { -+ deact = dwc_otg_hcd_qh_deferr(_hcd, _qh , retry_delay); -+ } -+ } -+ break; -+ case DWC_OTG_HC_XFER_URB_COMPLETE: -+ free_qtd = 1; -+ break; -+ case DWC_OTG_HC_XFER_AHB_ERR: -+ case DWC_OTG_HC_XFER_STALL: -+ case DWC_OTG_HC_XFER_BABBLE_ERR: -+ free_qtd = 1; -+ break; -+ case DWC_OTG_HC_XFER_XACT_ERR: -+ if (_qtd->error_count >= 3) { -+ DWC_DEBUGPL(DBG_HCDV, " Complete URB with transaction error\n"); -+ free_qtd = 1; -+ //_qtd->urb->status = -EPROTO; -+ dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EPROTO); -+ } else { -+ free_qtd = 0; -+ } -+ break; -+ case DWC_OTG_HC_XFER_URB_DEQUEUE: -+ /* -+ * The QTD has already been removed and the QH has been -+ * deactivated. Don't want to do anything except release the -+ * host channel and try to queue more transfers. -+ */ -+ goto cleanup; -+ case DWC_OTG_HC_XFER_NO_HALT_STATUS: -+ DWC_ERROR("%s: No halt_status, channel %d\n", __func__, _hc->hc_num); -+ free_qtd = 0; -+ break; -+ default: -+ free_qtd = 0; -+ break; -+ } -+ if (free_qtd) { -+ /* Only change must_free to true (do not set to zero here -- it is -+ * pre-initialized to zero). -+ */ -+ *must_free = 1; -+ } -+ if (deact) { -+ deactivate_qh(_hcd, _hc->qh, free_qtd); -+ } -+ cleanup: -+ /* -+ * Release the host channel for use by other transfers. The cleanup -+ * function clears the channel interrupt enables and conditions, so -+ * there's no need to clear the Channel Halted interrupt separately. -+ */ -+ dwc_otg_hc_cleanup(_hcd->core_if, _hc); -+ list_add_tail(&_hc->hc_list_entry, &_hcd->free_hc_list); -+ -+ local_irq_save(flags); -+ _hcd->available_host_channels++; -+ local_irq_restore(flags); -+ /* Try to queue more transfers now that there's a free channel, */ -+ /* unless erratum_usb09_patched is set */ -+ if (!erratum_usb09_patched) { -+ tr_type = dwc_otg_hcd_select_transactions(_hcd); -+ if (tr_type != DWC_OTG_TRANSACTION_NONE) { -+ dwc_otg_hcd_queue_transactions(_hcd, tr_type); -+ } -+ } -+} -+ -+/** -+ * Halts a host channel. If the channel cannot be halted immediately because -+ * the request queue is full, this function ensures that the FIFO empty -+ * interrupt for the appropriate queue is enabled so that the halt request can -+ * be queued when there is space in the request queue. -+ * -+ * This function may also be called in DMA mode. In that case, the channel is -+ * simply released since the core always halts the channel automatically in -+ * DMA mode. -+ */ -+static void halt_channel(dwc_otg_hcd_t *_hcd, -+ dwc_hc_t *_hc, -+ dwc_otg_qtd_t *_qtd, -+ dwc_otg_halt_status_e _halt_status, int *must_free) -+{ -+ if (_hcd->core_if->dma_enable) { -+ release_channel(_hcd, _hc, _qtd, _halt_status, must_free); -+ return; -+ } -+ -+ /* Slave mode processing... */ -+ dwc_otg_hc_halt(_hcd->core_if, _hc, _halt_status); -+ -+ if (_hc->halt_on_queue) { -+ gintmsk_data_t gintmsk = {.d32 = 0}; -+ dwc_otg_core_global_regs_t *global_regs; -+ global_regs = _hcd->core_if->core_global_regs; -+ -+ if (_hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || -+ _hc->ep_type == DWC_OTG_EP_TYPE_BULK) { -+ /* -+ * Make sure the Non-periodic Tx FIFO empty interrupt -+ * is enabled so that the non-periodic schedule will -+ * be processed. -+ */ -+ gintmsk.b.nptxfempty = 1; -+ dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32); -+ } else { -+ /* -+ * Move the QH from the periodic queued schedule to -+ * the periodic assigned schedule. This allows the -+ * halt to be queued when the periodic schedule is -+ * processed. -+ */ -+ list_move(&_hc->qh->qh_list_entry, -+ &_hcd->periodic_sched_assigned); -+ -+ /* -+ * Make sure the Periodic Tx FIFO Empty interrupt is -+ * enabled so that the periodic schedule will be -+ * processed. -+ */ -+ gintmsk.b.ptxfempty = 1; -+ dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32); -+ } -+ } -+} -+ -+/** -+ * Performs common cleanup for non-periodic transfers after a Transfer -+ * Complete interrupt. This function should be called after any endpoint type -+ * specific handling is finished to release the host channel. -+ */ -+static void complete_non_periodic_xfer(dwc_otg_hcd_t *_hcd, -+ dwc_hc_t *_hc, -+ dwc_otg_hc_regs_t *_hc_regs, -+ dwc_otg_qtd_t *_qtd, -+ dwc_otg_halt_status_e _halt_status, int *must_free) -+{ -+ hcint_data_t hcint; -+ -+ _qtd->error_count = 0; -+ -+ hcint.d32 = dwc_read_reg32(&_hc_regs->hcint); -+ if (hcint.b.nyet) { -+ /* -+ * Got a NYET on the last transaction of the transfer. This -+ * means that the endpoint should be in the PING state at the -+ * beginning of the next transfer. -+ */ -+ _hc->qh->ping_state = 1; -+ clear_hc_int(_hc_regs,nyet); -+ } -+ -+ /* -+ * Always halt and release the host channel to make it available for -+ * more transfers. There may still be more phases for a control -+ * transfer or more data packets for a bulk transfer at this point, -+ * but the host channel is still halted. A channel will be reassigned -+ * to the transfer when the non-periodic schedule is processed after -+ * the channel is released. This allows transactions to be queued -+ * properly via dwc_otg_hcd_queue_transactions, which also enables the -+ * Tx FIFO Empty interrupt if necessary. -+ */ -+ if (_hc->ep_is_in) { -+ /* -+ * IN transfers in Slave mode require an explicit disable to -+ * halt the channel. (In DMA mode, this call simply releases -+ * the channel.) -+ */ -+ halt_channel(_hcd, _hc, _qtd, _halt_status, must_free); -+ } else { -+ /* -+ * The channel is automatically disabled by the core for OUT -+ * transfers in Slave mode. -+ */ -+ release_channel(_hcd, _hc, _qtd, _halt_status, must_free); -+ } -+} -+ -+/** -+ * Performs common cleanup for periodic transfers after a Transfer Complete -+ * interrupt. This function should be called after any endpoint type specific -+ * handling is finished to release the host channel. -+ */ -+static void complete_periodic_xfer(dwc_otg_hcd_t *_hcd, -+ dwc_hc_t *_hc, -+ dwc_otg_hc_regs_t *_hc_regs, -+ dwc_otg_qtd_t *_qtd, -+ dwc_otg_halt_status_e _halt_status, int *must_free) -+{ -+ hctsiz_data_t hctsiz; -+ _qtd->error_count = 0; -+ -+ hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz); -+ if (!_hc->ep_is_in || hctsiz.b.pktcnt == 0) { -+ /* Core halts channel in these cases. */ -+ release_channel(_hcd, _hc, _qtd, _halt_status, must_free); -+ } else { -+ /* Flush any outstanding requests from the Tx queue. */ -+ halt_channel(_hcd, _hc, _qtd, _halt_status, must_free); -+ } -+} -+ -+/** -+ * Handles a host channel Transfer Complete interrupt. This handler may be -+ * called in either DMA mode or Slave mode. -+ */ -+static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t *_hcd, -+ dwc_hc_t *_hc, -+ dwc_otg_hc_regs_t *_hc_regs, -+ dwc_otg_qtd_t *_qtd, int *must_free) -+{ -+ int urb_xfer_done; -+ dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE; -+ struct urb *urb = _qtd->urb; -+ int pipe_type = usb_pipetype(urb->pipe); -+ int status = -EINPROGRESS; -+ -+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " -+ "Transfer Complete--\n", _hc->hc_num); -+ -+ /* -+ * Handle xfer complete on CSPLIT. -+ */ -+ if (_hc->qh->do_split) { -+ _qtd->complete_split = 0; -+ } -+ -+ /* Update the QTD and URB states. */ -+ switch (pipe_type) { -+ case PIPE_CONTROL: -+ switch (_qtd->control_phase) { -+ case DWC_OTG_CONTROL_SETUP: -+ if (urb->transfer_buffer_length > 0) { -+ _qtd->control_phase = DWC_OTG_CONTROL_DATA; -+ } else { -+ _qtd->control_phase = DWC_OTG_CONTROL_STATUS; -+ } -+ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n"); -+ halt_status = DWC_OTG_HC_XFER_COMPLETE; -+ break; -+ case DWC_OTG_CONTROL_DATA: { -+ urb_xfer_done = update_urb_state_xfer_comp(_hc, _hc_regs,urb, _qtd, &status); -+ if (urb_xfer_done) { -+ _qtd->control_phase = DWC_OTG_CONTROL_STATUS; -+ DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n"); -+ } else { -+ save_data_toggle(_hc, _hc_regs, _qtd); -+ } -+ halt_status = DWC_OTG_HC_XFER_COMPLETE; -+ break; -+ } -+ case DWC_OTG_CONTROL_STATUS: -+ DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n"); -+ if (status == -EINPROGRESS) { -+ status = 0; -+ } -+ dwc_otg_hcd_complete_urb(_hcd, urb, status); -+ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; -+ break; -+ } -+ -+ complete_non_periodic_xfer(_hcd, _hc, _hc_regs, _qtd, -+ halt_status, must_free); -+ break; -+ case PIPE_BULK: -+ DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n"); -+ urb_xfer_done = update_urb_state_xfer_comp(_hc, _hc_regs, urb, _qtd, &status); -+ if (urb_xfer_done) { -+ dwc_otg_hcd_complete_urb(_hcd, urb, status); -+ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; -+ } else { -+ halt_status = DWC_OTG_HC_XFER_COMPLETE; -+ } -+ -+ save_data_toggle(_hc, _hc_regs, _qtd); -+ complete_non_periodic_xfer(_hcd, _hc, _hc_regs, _qtd,halt_status, must_free); -+ break; -+ case PIPE_INTERRUPT: -+ DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n"); -+ update_urb_state_xfer_comp(_hc, _hc_regs, urb, _qtd, &status); -+ -+ /* -+ * Interrupt URB is done on the first transfer complete -+ * interrupt. -+ */ -+ dwc_otg_hcd_complete_urb(_hcd, urb, status); -+ save_data_toggle(_hc, _hc_regs, _qtd); -+ complete_periodic_xfer(_hcd, _hc, _hc_regs, _qtd, -+ DWC_OTG_HC_XFER_URB_COMPLETE, must_free); -+ break; -+ case PIPE_ISOCHRONOUS: -+ DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n"); -+ if (_qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) -+ { -+ halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd, -+ DWC_OTG_HC_XFER_COMPLETE); -+ } -+ complete_periodic_xfer(_hcd, _hc, _hc_regs, _qtd, halt_status, must_free); -+ break; -+ } -+ -+ disable_hc_int(_hc_regs,xfercompl); -+ -+ return 1; -+} -+ -+/** -+ * Handles a host channel STALL interrupt. This handler may be called in -+ * either DMA mode or Slave mode. -+ */ -+static int32_t handle_hc_stall_intr(dwc_otg_hcd_t *_hcd, -+ dwc_hc_t *_hc, -+ dwc_otg_hc_regs_t *_hc_regs, -+ dwc_otg_qtd_t *_qtd, int *must_free) -+{ -+ struct urb *urb = _qtd->urb; -+ int pipe_type = usb_pipetype(urb->pipe); -+ -+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " -+ "STALL Received--\n", _hc->hc_num); -+ -+ if (pipe_type == PIPE_CONTROL) { -+ dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EPIPE); -+ } -+ -+ if (pipe_type == PIPE_BULK || pipe_type == PIPE_INTERRUPT) { -+ dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EPIPE); -+ /* -+ * USB protocol requires resetting the data toggle for bulk -+ * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT) -+ * setup command is issued to the endpoint. Anticipate the -+ * CLEAR_FEATURE command since a STALL has occurred and reset -+ * the data toggle now. -+ */ -+ _hc->qh->data_toggle = 0; -+ } -+ -+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_STALL, must_free); -+ disable_hc_int(_hc_regs,stall); -+ -+ return 1; -+} -+ -+/* -+ * Updates the state of the URB when a transfer has been stopped due to an -+ * abnormal condition before the transfer completes. Modifies the -+ * actual_length field of the URB to reflect the number of bytes that have -+ * actually been transferred via the host channel. -+ */ -+static void update_urb_state_xfer_intr(dwc_hc_t *_hc, -+ dwc_otg_hc_regs_t *_hc_regs, -+ struct urb *_urb, -+ dwc_otg_qtd_t *_qtd, -+ dwc_otg_halt_status_e _halt_status) -+{ -+ uint32_t bytes_transferred = get_actual_xfer_length(_hc, _hc_regs, _qtd, -+ _halt_status, NULL); -+ _urb->actual_length += bytes_transferred; -+ -+#ifdef DEBUG -+ { -+ hctsiz_data_t hctsiz; -+ hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz); -+ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n", -+ __func__, (_hc->ep_is_in ? "IN" : "OUT"), _hc->hc_num); -+ DWC_DEBUGPL(DBG_HCDV, " _hc->start_pkt_count %d\n", _hc->start_pkt_count); -+ DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt); -+ DWC_DEBUGPL(DBG_HCDV, " _hc->max_packet %d\n", _hc->max_packet); -+ DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n", bytes_transferred); -+ DWC_DEBUGPL(DBG_HCDV, " _urb->actual_length %d\n", _urb->actual_length); -+ DWC_DEBUGPL(DBG_HCDV, " _urb->transfer_buffer_length %d\n", -+ _urb->transfer_buffer_length); -+ } -+#endif -+} -+ -+/** -+ * Handles a host channel NAK interrupt. This handler may be called in either -+ * DMA mode or Slave mode. -+ */ -+static int32_t handle_hc_nak_intr(dwc_otg_hcd_t *_hcd, -+ dwc_hc_t *_hc, -+ dwc_otg_hc_regs_t *_hc_regs, -+ dwc_otg_qtd_t *_qtd, int *must_free) -+{ -+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " -+ "NAK Received--\n", _hc->hc_num); -+ -+ /* -+ * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and -+ * interrupt. Re-start the SSPLIT transfer. -+ */ -+ if (_hc->do_split) { -+ if (_hc->complete_split) { -+ _qtd->error_count = 0; -+ } -+ _qtd->complete_split = 0; -+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NAK, must_free); -+ goto handle_nak_done; -+ } -+ -+ switch (usb_pipetype(_qtd->urb->pipe)) { -+ case PIPE_CONTROL: -+ case PIPE_BULK: -+ if (_hcd->core_if->dma_enable && _hc->ep_is_in) { -+ /* -+ * NAK interrupts are enabled on bulk/control IN -+ * transfers in DMA mode for the sole purpose of -+ * resetting the error count after a transaction error -+ * occurs. The core will continue transferring data. -+ */ -+ _qtd->error_count = 0; -+ goto handle_nak_done; -+ } -+ -+ /* -+ * NAK interrupts normally occur during OUT transfers in DMA -+ * or Slave mode. For IN transfers, more requests will be -+ * queued as request queue space is available. -+ */ -+ _qtd->error_count = 0; -+ -+ if (!_hc->qh->ping_state) { -+ update_urb_state_xfer_intr(_hc, _hc_regs, _qtd->urb, -+ _qtd, DWC_OTG_HC_XFER_NAK); -+ save_data_toggle(_hc, _hc_regs, _qtd); -+ if (_qtd->urb->dev->speed == USB_SPEED_HIGH) { -+ _hc->qh->ping_state = 1; -+ } -+ } -+ -+ /* -+ * Halt the channel so the transfer can be re-started from -+ * the appropriate point or the PING protocol will -+ * start/continue. -+ */ -+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NAK, must_free); -+ break; -+ case PIPE_INTERRUPT: -+ _qtd->error_count = 0; -+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NAK, must_free); -+ break; -+ case PIPE_ISOCHRONOUS: -+ /* Should never get called for isochronous transfers. */ -+ BUG(); -+ break; -+ } -+ -+ handle_nak_done: -+ disable_hc_int(_hc_regs,nak); -+ -+ return 1; -+} -+ -+/** -+ * Handles a host channel ACK interrupt. This interrupt is enabled when -+ * performing the PING protocol in Slave mode, when errors occur during -+ * either Slave mode or DMA mode, and during Start Split transactions. -+ */ -+static int32_t handle_hc_ack_intr(dwc_otg_hcd_t *_hcd, -+ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) -+{ -+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " -+ "ACK Received--\n", _hc->hc_num); -+ -+ if (_hc->do_split) { -+ /* -+ * Handle ACK on SSPLIT. -+ * ACK should not occur in CSPLIT. -+ */ -+ if ((!_hc->ep_is_in) && (_hc->data_pid_start != DWC_OTG_HC_PID_SETUP)) { -+ _qtd->ssplit_out_xfer_count = _hc->xfer_len; -+ } -+ if (!(_hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !_hc->ep_is_in)) { -+ /* Don't need complete for isochronous out transfers. */ -+ _qtd->complete_split = 1; -+ } -+ -+ /* ISOC OUT */ -+ if ((_hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && !_hc->ep_is_in) { -+ switch (_hc->xact_pos) { -+ case DWC_HCSPLIT_XACTPOS_ALL: -+ break; -+ case DWC_HCSPLIT_XACTPOS_END: -+ _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL; -+ _qtd->isoc_split_offset = 0; -+ break; -+ case DWC_HCSPLIT_XACTPOS_BEGIN: -+ case DWC_HCSPLIT_XACTPOS_MID: -+ /* -+ * For BEGIN or MID, calculate the length for -+ * the next microframe to determine the correct -+ * SSPLIT token, either MID or END. -+ */ -+ do { -+ struct usb_iso_packet_descriptor *frame_desc; -+ -+ frame_desc = &_qtd->urb->iso_frame_desc[_qtd->isoc_frame_index]; -+ _qtd->isoc_split_offset += 188; -+ -+ if ((frame_desc->length - _qtd->isoc_split_offset) <= 188) { -+ _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_END; -+ } -+ else { -+ _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_MID; -+ } -+ -+ } while(0); -+ break; -+ } -+ } else { -+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_ACK, must_free); -+ } -+ } else { -+ _qtd->error_count = 0; -+ -+ if (_hc->qh->ping_state) { -+ _hc->qh->ping_state = 0; -+ /* -+ * Halt the channel so the transfer can be re-started -+ * from the appropriate point. This only happens in -+ * Slave mode. In DMA mode, the ping_state is cleared -+ * when the transfer is started because the core -+ * automatically executes the PING, then the transfer. -+ */ -+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_ACK, must_free); -+ } else { -+ halt_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free); -+ } -+ } -+ -+ /* -+ * If the ACK occurred when _not_ in the PING state, let the channel -+ * continue transferring data after clearing the error count. -+ */ -+ -+ disable_hc_int(_hc_regs,ack); -+ -+ return 1; -+} -+ -+/** -+ * Handles a host channel NYET interrupt. This interrupt should only occur on -+ * Bulk and Control OUT endpoints and for complete split transactions. If a -+ * NYET occurs at the same time as a Transfer Complete interrupt, it is -+ * handled in the xfercomp interrupt handler, not here. This handler may be -+ * called in either DMA mode or Slave mode. -+ */ -+static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t *_hcd, -+ dwc_hc_t *_hc, -+ dwc_otg_hc_regs_t *_hc_regs, -+ dwc_otg_qtd_t *_qtd, int *must_free) -+{ -+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " -+ "NYET Received--\n", _hc->hc_num); -+ -+ /* -+ * NYET on CSPLIT -+ * re-do the CSPLIT immediately on non-periodic -+ */ -+ if ((_hc->do_split) && (_hc->complete_split)) { -+ if ((_hc->ep_type == DWC_OTG_EP_TYPE_INTR) || -+ (_hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) { -+ int frnum = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd)); -+ -+ if (dwc_full_frame_num(frnum) != -+ dwc_full_frame_num(_hc->qh->sched_frame)) { -+ /* -+ * No longer in the same full speed frame. -+ * Treat this as a transaction error. -+ */ -+#if 0 -+ /** @todo Fix system performance so this can -+ * be treated as an error. Right now complete -+ * splits cannot be scheduled precisely enough -+ * due to other system activity, so this error -+ * occurs regularly in Slave mode. -+ */ -+ _qtd->error_count++; -+#endif -+ _qtd->complete_split = 0; -+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_XACT_ERR, must_free); -+ /** @todo add support for isoc release */ -+ goto handle_nyet_done; -+ } -+ } -+ -+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NYET, must_free); -+ goto handle_nyet_done; -+ } -+ -+ _hc->qh->ping_state = 1; -+ _qtd->error_count = 0; -+ -+ update_urb_state_xfer_intr(_hc, _hc_regs, _qtd->urb, _qtd, -+ DWC_OTG_HC_XFER_NYET); -+ save_data_toggle(_hc, _hc_regs, _qtd); -+ -+ /* -+ * Halt the channel and re-start the transfer so the PING -+ * protocol will start. -+ */ -+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NYET, must_free); -+ -+handle_nyet_done: -+ disable_hc_int(_hc_regs,nyet); -+ clear_hc_int(_hc_regs, nyet); -+ return 1; -+} -+ -+/** -+ * Handles a host channel babble interrupt. This handler may be called in -+ * either DMA mode or Slave mode. -+ */ -+static int32_t handle_hc_babble_intr(dwc_otg_hcd_t *_hcd, -+ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) -+{ -+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " -+ "Babble Error--\n", _hc->hc_num); -+ if (_hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { -+ dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EOVERFLOW); -+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_BABBLE_ERR, must_free); -+ } else { -+ dwc_otg_halt_status_e halt_status; -+ halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd, -+ DWC_OTG_HC_XFER_BABBLE_ERR); -+ halt_channel(_hcd, _hc, _qtd, halt_status, must_free); -+ } -+ disable_hc_int(_hc_regs,bblerr); -+ return 1; -+} -+ -+/** -+ * Handles a host channel AHB error interrupt. This handler is only called in -+ * DMA mode. -+ */ -+static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t *_hcd, -+ dwc_hc_t *_hc, -+ dwc_otg_hc_regs_t *_hc_regs, -+ dwc_otg_qtd_t *_qtd) -+{ -+ hcchar_data_t hcchar; -+ hcsplt_data_t hcsplt; -+ hctsiz_data_t hctsiz; -+ uint32_t hcdma; -+ struct urb *urb = _qtd->urb; -+ -+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " -+ "AHB Error--\n", _hc->hc_num); -+ -+ hcchar.d32 = dwc_read_reg32(&_hc_regs->hcchar); -+ hcsplt.d32 = dwc_read_reg32(&_hc_regs->hcsplt); -+ hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz); -+ hcdma = dwc_read_reg32(&_hc_regs->hcdma); -+ -+ DWC_ERROR("AHB ERROR, Channel %d\n", _hc->hc_num); -+ DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32); -+ DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma); -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n"); -+ DWC_ERROR(" Device address: %d\n", usb_pipedevice(urb->pipe)); -+ DWC_ERROR(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe), -+ (usb_pipein(urb->pipe) ? "IN" : "OUT")); -+ DWC_ERROR(" Endpoint type: %s\n", -+ ({char *pipetype; -+ switch (usb_pipetype(urb->pipe)) { -+ case PIPE_CONTROL: pipetype = "CONTROL"; break; -+ case PIPE_BULK: pipetype = "BULK"; break; -+ case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break; -+ case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break; -+ default: pipetype = "UNKNOWN"; break; -+ }; pipetype;})); -+ DWC_ERROR(" Speed: %s\n", -+ ({char *speed; -+ switch (urb->dev->speed) { -+ case USB_SPEED_HIGH: speed = "HIGH"; break; -+ case USB_SPEED_FULL: speed = "FULL"; break; -+ case USB_SPEED_LOW: speed = "LOW"; break; -+ default: speed = "UNKNOWN"; break; -+ }; speed;})); -+ DWC_ERROR(" Max packet size: %d\n", -+ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); -+ DWC_ERROR(" Data buffer length: %d\n", urb->transfer_buffer_length); -+ DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n", -+ urb->transfer_buffer, (void *)(u32)urb->transfer_dma); -+ DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n", -+ urb->setup_packet, (void *)(u32)urb->setup_dma); -+ DWC_ERROR(" Interval: %d\n", urb->interval); -+ -+ dwc_otg_hcd_complete_urb(_hcd, urb, -EIO); -+ -+ /* -+ * Force a channel halt. Don't call halt_channel because that won't -+ * write to the HCCHARn register in DMA mode to force the halt. -+ */ -+ dwc_otg_hc_halt(_hcd->core_if, _hc, DWC_OTG_HC_XFER_AHB_ERR); -+ -+ disable_hc_int(_hc_regs,ahberr); -+ return 1; -+} -+ -+/** -+ * Handles a host channel transaction error interrupt. This handler may be -+ * called in either DMA mode or Slave mode. -+ */ -+static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t *_hcd, -+ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) -+{ -+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " -+ "Transaction Error--\n", _hc->hc_num); -+ -+ switch (usb_pipetype(_qtd->urb->pipe)) { -+ case PIPE_CONTROL: -+ case PIPE_BULK: -+ _qtd->error_count++; -+ if (!_hc->qh->ping_state) { -+ update_urb_state_xfer_intr(_hc, _hc_regs, _qtd->urb, -+ _qtd, DWC_OTG_HC_XFER_XACT_ERR); -+ save_data_toggle(_hc, _hc_regs, _qtd); -+ if (!_hc->ep_is_in && _qtd->urb->dev->speed == USB_SPEED_HIGH) { -+ _hc->qh->ping_state = 1; -+ } -+ } -+ -+ /* -+ * Halt the channel so the transfer can be re-started from -+ * the appropriate point or the PING protocol will start. -+ */ -+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_XACT_ERR, must_free); -+ break; -+ case PIPE_INTERRUPT: -+ _qtd->error_count++; -+ if ((_hc->do_split) && (_hc->complete_split)) { -+ _qtd->complete_split = 0; -+ } -+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_XACT_ERR, must_free); -+ break; -+ case PIPE_ISOCHRONOUS: -+ { -+ dwc_otg_halt_status_e halt_status; -+ halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd, -+ DWC_OTG_HC_XFER_XACT_ERR); -+ -+ halt_channel(_hcd, _hc, _qtd, halt_status, must_free); -+ } -+ break; -+ } -+ -+ -+ disable_hc_int(_hc_regs,xacterr); -+ -+ return 1; -+} -+ -+/** -+ * Handles a host channel frame overrun interrupt. This handler may be called -+ * in either DMA mode or Slave mode. -+ */ -+static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t *_hcd, -+ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) -+{ -+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " -+ "Frame Overrun--\n", _hc->hc_num); -+ -+ switch (usb_pipetype(_qtd->urb->pipe)) { -+ case PIPE_CONTROL: -+ case PIPE_BULK: -+ break; -+ case PIPE_INTERRUPT: -+ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN, must_free); -+ break; -+ case PIPE_ISOCHRONOUS: -+ { -+ dwc_otg_halt_status_e halt_status; -+ halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd, -+ DWC_OTG_HC_XFER_FRAME_OVERRUN); -+ -+ halt_channel(_hcd, _hc, _qtd, halt_status, must_free); -+ } -+ break; -+ } -+ -+ disable_hc_int(_hc_regs,frmovrun); -+ -+ return 1; -+} -+ -+/** -+ * Handles a host channel data toggle error interrupt. This handler may be -+ * called in either DMA mode or Slave mode. -+ */ -+static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t *_hcd, -+ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) -+{ -+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " -+ "Data Toggle Error--\n", _hc->hc_num); -+ -+ if (_hc->ep_is_in) { -+ _qtd->error_count = 0; -+ } else { -+ DWC_ERROR("Data Toggle Error on OUT transfer," -+ "channel %d\n", _hc->hc_num); -+ } -+ -+ disable_hc_int(_hc_regs,datatglerr); -+ -+ return 1; -+} -+ -+#ifdef DEBUG -+/** -+ * This function is for debug only. It checks that a valid halt status is set -+ * and that HCCHARn.chdis is clear. If there's a problem, corrective action is -+ * taken and a warning is issued. -+ * @return 1 if halt status is ok, 0 otherwise. -+ */ -+static inline int halt_status_ok(dwc_otg_hcd_t *_hcd, -+ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) -+{ -+ hcchar_data_t hcchar; -+ hctsiz_data_t hctsiz; -+ hcint_data_t hcint; -+ hcintmsk_data_t hcintmsk; -+ hcsplt_data_t hcsplt; -+ -+ if (_hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) { -+ /* -+ * This code is here only as a check. This condition should -+ * never happen. Ignore the halt if it does occur. -+ */ -+ hcchar.d32 = dwc_read_reg32(&_hc_regs->hcchar); -+ hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz); -+ hcint.d32 = dwc_read_reg32(&_hc_regs->hcint); -+ hcintmsk.d32 = dwc_read_reg32(&_hc_regs->hcintmsk); -+ hcsplt.d32 = dwc_read_reg32(&_hc_regs->hcsplt); -+ DWC_WARN("%s: _hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, " -+ "channel %d, hcchar 0x%08x, hctsiz 0x%08x, " -+ "hcint 0x%08x, hcintmsk 0x%08x, " -+ "hcsplt 0x%08x, qtd->complete_split %d\n", -+ __func__, _hc->hc_num, hcchar.d32, hctsiz.d32, -+ hcint.d32, hcintmsk.d32, -+ hcsplt.d32, _qtd->complete_split); -+ -+ DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n", -+ __func__, _hc->hc_num); -+ DWC_WARN("\n"); -+ clear_hc_int(_hc_regs,chhltd); -+ return 0; -+ } -+ -+ /* -+ * This code is here only as a check. hcchar.chdis should -+ * never be set when the halt interrupt occurs. Halt the -+ * channel again if it does occur. -+ */ -+ hcchar.d32 = dwc_read_reg32(&_hc_regs->hcchar); -+ if (hcchar.b.chdis) { -+ DWC_WARN("%s: hcchar.chdis set unexpectedly, " -+ "hcchar 0x%08x, trying to halt again\n", -+ __func__, hcchar.d32); -+ clear_hc_int(_hc_regs,chhltd); -+ _hc->halt_pending = 0; -+ halt_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free); -+ return 0; -+ } -+ -+ return 1; -+} -+#endif -+ -+/** -+ * Handles a host Channel Halted interrupt in DMA mode. This handler -+ * determines the reason the channel halted and proceeds accordingly. -+ */ -+static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *_hcd, -+ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) -+{ -+ hcint_data_t hcint; -+ hcintmsk_data_t hcintmsk; -+ -+ if (_hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE || -+ _hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR) { -+ /* -+ * Just release the channel. A dequeue can happen on a -+ * transfer timeout. In the case of an AHB Error, the channel -+ * was forced to halt because there's no way to gracefully -+ * recover. -+ */ -+ release_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free); -+ return; -+ } -+ -+ /* Read the HCINTn register to determine the cause for the halt. */ -+ hcint.d32 = dwc_read_reg32(&_hc_regs->hcint); -+ hcintmsk.d32 = dwc_read_reg32(&_hc_regs->hcintmsk); -+ -+ if (hcint.b.xfercomp) { -+ /** @todo This is here because of a possible hardware bug. Spec -+ * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT -+ * interrupt w/ACK bit set should occur, but I only see the -+ * XFERCOMP bit, even with it masked out. This is a workaround -+ * for that behavior. Should fix this when hardware is fixed. -+ */ -+ if ((_hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && (!_hc->ep_is_in)) { -+ handle_hc_ack_intr(_hcd, _hc, _hc_regs, _qtd, must_free); -+ } -+ handle_hc_xfercomp_intr(_hcd, _hc, _hc_regs, _qtd, must_free); -+ } else if (hcint.b.stall) { -+ handle_hc_stall_intr(_hcd, _hc, _hc_regs, _qtd, must_free); -+ } else if (hcint.b.xacterr) { -+ /* -+ * Must handle xacterr before nak or ack. Could get a xacterr -+ * at the same time as either of these on a BULK/CONTROL OUT -+ * that started with a PING. The xacterr takes precedence. -+ */ -+ handle_hc_xacterr_intr(_hcd, _hc, _hc_regs, _qtd, must_free); -+ } else if (hcint.b.nyet) { -+ /* -+ * Must handle nyet before nak or ack. Could get a nyet at the -+ * same time as either of those on a BULK/CONTROL OUT that -+ * started with a PING. The nyet takes precedence. -+ */ -+ handle_hc_nyet_intr(_hcd, _hc, _hc_regs, _qtd, must_free); -+ } else if (hcint.b.bblerr) { -+ handle_hc_babble_intr(_hcd, _hc, _hc_regs, _qtd, must_free); -+ } else if (hcint.b.frmovrun) { -+ handle_hc_frmovrun_intr(_hcd, _hc, _hc_regs, _qtd, must_free); -+ } else if (hcint.b.datatglerr) { -+ handle_hc_datatglerr_intr(_hcd, _hc, _hc_regs, _qtd, must_free); -+ _hc->qh->data_toggle = 0; -+ halt_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free); -+ } else if (hcint.b.nak && !hcintmsk.b.nak) { -+ /* -+ * If nak is not masked, it's because a non-split IN transfer -+ * is in an error state. In that case, the nak is handled by -+ * the nak interrupt handler, not here. Handle nak here for -+ * BULK/CONTROL OUT transfers, which halt on a NAK to allow -+ * rewinding the buffer pointer. -+ */ -+ handle_hc_nak_intr(_hcd, _hc, _hc_regs, _qtd, must_free); -+ } else if (hcint.b.ack && !hcintmsk.b.ack) { -+ /* -+ * If ack is not masked, it's because a non-split IN transfer -+ * is in an error state. In that case, the ack is handled by -+ * the ack interrupt handler, not here. Handle ack here for -+ * split transfers. Start splits halt on ACK. -+ */ -+ handle_hc_ack_intr(_hcd, _hc, _hc_regs, _qtd, must_free); -+ } else { -+ if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR || -+ _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { -+ /* -+ * A periodic transfer halted with no other channel -+ * interrupts set. Assume it was halted by the core -+ * because it could not be completed in its scheduled -+ * (micro)frame. -+ */ -+#ifdef DEBUG -+ DWC_PRINT("%s: Halt channel %d (assume incomplete periodic transfer)\n", -+ __func__, _hc->hc_num); -+#endif /* */ -+ halt_channel(_hcd, _hc, _qtd, -+ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE, must_free); -+ } else { -+#ifdef DEBUG -+ DWC_ERROR("%s: Channel %d, DMA Mode -- ChHltd set, but reason " -+ "for halting is unknown, nyet %d, hcint 0x%08x, intsts 0x%08x\n", -+ __func__, _hc->hc_num, hcint.b.nyet, hcint.d32, -+ dwc_read_reg32(&_hcd->core_if->core_global_regs->gintsts)); -+#endif -+ halt_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free); -+ } -+ } -+} -+ -+/** -+ * Handles a host channel Channel Halted interrupt. -+ * -+ * In slave mode, this handler is called only when the driver specifically -+ * requests a halt. This occurs during handling other host channel interrupts -+ * (e.g. nak, xacterr, stall, nyet, etc.). -+ * -+ * In DMA mode, this is the interrupt that occurs when the core has finished -+ * processing a transfer on a channel. Other host channel interrupts (except -+ * ahberr) are disabled in DMA mode. -+ */ -+static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t *_hcd, -+ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) -+{ -+ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " -+ "Channel Halted--\n", _hc->hc_num); -+ -+ if (_hcd->core_if->dma_enable) { -+ handle_hc_chhltd_intr_dma(_hcd, _hc, _hc_regs, _qtd, must_free); -+ } else { -+#ifdef DEBUG -+ if (!halt_status_ok(_hcd, _hc, _hc_regs, _qtd, must_free)) { -+ return 1; -+ } -+#endif /* */ -+ release_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free); -+ } -+ -+ return 1; -+} -+ -+/** Handles interrupt for a specific Host Channel */ -+int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *_dwc_otg_hcd, uint32_t _num) -+{ -+ int must_free = 0; -+ int retval = 0; -+ hcint_data_t hcint; -+ hcintmsk_data_t hcintmsk; -+ dwc_hc_t *hc; -+ dwc_otg_hc_regs_t *hc_regs; -+ dwc_otg_qtd_t *qtd; -+ -+ DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", _num); -+ -+ hc = _dwc_otg_hcd->hc_ptr_array[_num]; -+ hc_regs = _dwc_otg_hcd->core_if->host_if->hc_regs[_num]; -+ qtd = list_entry(hc->qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); -+ -+ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); -+ hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk); -+ DWC_DEBUGPL(DBG_HCDV, " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n", -+ hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32)); -+ hcint.d32 = hcint.d32 & hcintmsk.d32; -+ -+ if (!_dwc_otg_hcd->core_if->dma_enable) { -+ if ((hcint.b.chhltd) && (hcint.d32 != 0x2)) { -+ hcint.b.chhltd = 0; -+ } -+ } -+ -+ if (hcint.b.xfercomp) { -+ retval |= handle_hc_xfercomp_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); -+ /* -+ * If NYET occurred at same time as Xfer Complete, the NYET is -+ * handled by the Xfer Complete interrupt handler. Don't want -+ * to call the NYET interrupt handler in this case. -+ */ -+ hcint.b.nyet = 0; -+ } -+ if (hcint.b.chhltd) { -+ retval |= handle_hc_chhltd_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); -+ } -+ if (hcint.b.ahberr) { -+ retval |= handle_hc_ahberr_intr(_dwc_otg_hcd, hc, hc_regs, qtd); -+ } -+ if (hcint.b.stall) { -+ retval |= handle_hc_stall_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); -+ } -+ if (hcint.b.nak) { -+ retval |= handle_hc_nak_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); -+ } -+ if (hcint.b.ack) { -+ retval |= handle_hc_ack_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); -+ } -+ if (hcint.b.nyet) { -+ retval |= handle_hc_nyet_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); -+ } -+ if (hcint.b.xacterr) { -+ retval |= handle_hc_xacterr_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); -+ } -+ if (hcint.b.bblerr) { -+ retval |= handle_hc_babble_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); -+ } -+ if (hcint.b.frmovrun) { -+ retval |= handle_hc_frmovrun_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); -+ } -+ if (hcint.b.datatglerr) { -+ retval |= handle_hc_datatglerr_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); -+ } -+ -+ /* -+ * Logic to free the qtd here, at the end of the hc intr -+ * processing, if the handling of this interrupt determined -+ * that it needs to be freed. -+ */ -+ if (must_free) { -+ /* Free the qtd here now that we are done using it. */ -+ dwc_otg_hcd_qtd_free(qtd); -+ } -+ return retval; -+} -+ -+#endif /* DWC_DEVICE_ONLY */ ---- /dev/null -+++ b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c -@@ -0,0 +1,794 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_queue.c $ -+ * $Revision: 1.1.1.1 $ -+ * $Date: 2009-04-17 06:15:34 $ -+ * $Change: 537387 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+#ifndef DWC_DEVICE_ONLY -+ -+/** -+ * @file -+ * -+ * This file contains the functions to manage Queue Heads and Queue -+ * Transfer Descriptors. -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "dwc_otg_driver.h" -+#include "dwc_otg_hcd.h" -+#include "dwc_otg_regs.h" -+ -+/** -+ * This function allocates and initializes a QH. -+ * -+ * @param _hcd The HCD state structure for the DWC OTG controller. -+ * @param[in] _urb Holds the information about the device/endpoint that we need -+ * to initialize the QH. -+ * -+ * @return Returns pointer to the newly allocated QH, or NULL on error. */ -+dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *_hcd, struct urb *_urb) -+{ -+ dwc_otg_qh_t *qh; -+ -+ /* Allocate memory */ -+ /** @todo add memflags argument */ -+ qh = dwc_otg_hcd_qh_alloc (); -+ if (qh == NULL) { -+ return NULL; -+ } -+ -+ dwc_otg_hcd_qh_init (_hcd, qh, _urb); -+ return qh; -+} -+ -+/** Free each QTD in the QH's QTD-list then free the QH. QH should already be -+ * removed from a list. QTD list should already be empty if called from URB -+ * Dequeue. -+ * -+ * @param[in] _qh The QH to free. -+ */ -+void dwc_otg_hcd_qh_free (dwc_otg_qh_t *_qh) -+{ -+ dwc_otg_qtd_t *qtd; -+ struct list_head *pos; -+ unsigned long flags; -+ -+ /* Free each QTD in the QTD list */ -+ local_irq_save (flags); -+ for (pos = _qh->qtd_list.next; -+ pos != &_qh->qtd_list; -+ pos = _qh->qtd_list.next) -+ { -+ list_del (pos); -+ qtd = dwc_list_to_qtd (pos); -+ dwc_otg_hcd_qtd_free (qtd); -+ } -+ local_irq_restore (flags); -+ -+ kfree (_qh); -+ return; -+} -+ -+/** Initializes a QH structure. -+ * -+ * @param[in] _hcd The HCD state structure for the DWC OTG controller. -+ * @param[in] _qh The QH to init. -+ * @param[in] _urb Holds the information about the device/endpoint that we need -+ * to initialize the QH. */ -+#define SCHEDULE_SLOP 10 -+void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, struct urb *_urb) -+{ -+ memset (_qh, 0, sizeof (dwc_otg_qh_t)); -+ -+ /* Initialize QH */ -+ switch (usb_pipetype(_urb->pipe)) { -+ case PIPE_CONTROL: -+ _qh->ep_type = USB_ENDPOINT_XFER_CONTROL; -+ break; -+ case PIPE_BULK: -+ _qh->ep_type = USB_ENDPOINT_XFER_BULK; -+ break; -+ case PIPE_ISOCHRONOUS: -+ _qh->ep_type = USB_ENDPOINT_XFER_ISOC; -+ break; -+ case PIPE_INTERRUPT: -+ _qh->ep_type = USB_ENDPOINT_XFER_INT; -+ break; -+ } -+ -+ _qh->ep_is_in = usb_pipein(_urb->pipe) ? 1 : 0; -+ -+ _qh->data_toggle = DWC_OTG_HC_PID_DATA0; -+ _qh->maxp = usb_maxpacket(_urb->dev, _urb->pipe, !(usb_pipein(_urb->pipe))); -+ INIT_LIST_HEAD(&_qh->qtd_list); -+ INIT_LIST_HEAD(&_qh->qh_list_entry); -+ _qh->channel = NULL; -+ -+ /* FS/LS Enpoint on HS Hub -+ * NOT virtual root hub */ -+ _qh->do_split = 0; -+ _qh->speed = _urb->dev->speed; -+ if (((_urb->dev->speed == USB_SPEED_LOW) || -+ (_urb->dev->speed == USB_SPEED_FULL)) && -+ (_urb->dev->tt) && (_urb->dev->tt->hub) && (_urb->dev->tt->hub->devnum != 1)) { -+ DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n", -+ usb_pipeendpoint(_urb->pipe), _urb->dev->tt->hub->devnum, -+ _urb->dev->ttport); -+ _qh->do_split = 1; -+ } -+ -+ if (_qh->ep_type == USB_ENDPOINT_XFER_INT || -+ _qh->ep_type == USB_ENDPOINT_XFER_ISOC) { -+ /* Compute scheduling parameters once and save them. */ -+ hprt0_data_t hprt; -+ -+ /** @todo Account for split transfers in the bus time. */ -+ int bytecount = dwc_hb_mult(_qh->maxp) * dwc_max_packet(_qh->maxp); -+ _qh->usecs = NS_TO_US(usb_calc_bus_time(_urb->dev->speed, -+ usb_pipein(_urb->pipe), -+ (_qh->ep_type == USB_ENDPOINT_XFER_ISOC),bytecount)); -+ -+ /* Start in a slightly future (micro)frame. */ -+ _qh->sched_frame = dwc_frame_num_inc(_hcd->frame_number, SCHEDULE_SLOP); -+ _qh->interval = _urb->interval; -+#if 0 -+ /* Increase interrupt polling rate for debugging. */ -+ if (_qh->ep_type == USB_ENDPOINT_XFER_INT) { -+ _qh->interval = 8; -+ } -+#endif -+ hprt.d32 = dwc_read_reg32(_hcd->core_if->host_if->hprt0); -+ if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) && -+ ((_urb->dev->speed == USB_SPEED_LOW) || -+ (_urb->dev->speed == USB_SPEED_FULL))) -+ { -+ _qh->interval *= 8; -+ _qh->sched_frame |= 0x7; -+ _qh->start_split_frame = _qh->sched_frame; -+ } -+ } -+ -+ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n"); -+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", _qh); -+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n", -+ _urb->dev->devnum); -+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n", -+ usb_pipeendpoint(_urb->pipe), -+ usb_pipein(_urb->pipe) == USB_DIR_IN ? "IN" : "OUT"); -+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", -+ ({ char *speed; switch (_urb->dev->speed) { -+ case USB_SPEED_LOW: speed = "low"; break; -+ case USB_SPEED_FULL: speed = "full"; break; -+ case USB_SPEED_HIGH: speed = "high"; break; -+ default: speed = "?"; break; -+ }; speed;})); -+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n", -+ ({ char *type; switch (_qh->ep_type) { -+ case USB_ENDPOINT_XFER_ISOC: type = "isochronous"; break; -+ case USB_ENDPOINT_XFER_INT: type = "interrupt"; break; -+ case USB_ENDPOINT_XFER_CONTROL: type = "control"; break; -+ case USB_ENDPOINT_XFER_BULK: type = "bulk"; break; -+ default: type = "?"; break; -+ }; type;})); -+#ifdef DEBUG -+ if (_qh->ep_type == USB_ENDPOINT_XFER_INT) { -+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n", -+ _qh->usecs); -+ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n", -+ _qh->interval); -+ } -+#endif -+ -+ return; -+} -+ -+/** -+ * Microframe scheduler -+ * track the total use in hcd->frame_usecs -+ * keep each qh use in qh->frame_usecs -+ * when surrendering the qh then donate the time back -+ */ -+const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 }; -+ -+/* -+ * called from dwc_otg_hcd.c:dwc_otg_hcd_init -+ */ -+int init_hcd_usecs(dwc_otg_hcd_t *_hcd) -+{ -+ int i; -+ for (i=0; i<8; i++) { -+ _hcd->frame_usecs[i] = max_uframe_usecs[i]; -+ } -+ return 0; -+} -+ -+static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) -+{ -+ int i; -+ unsigned short utime; -+ int t_left; -+ int ret; -+ int done; -+ -+ ret = -1; -+ utime = _qh->usecs; -+ t_left = utime; -+ i = 0; -+ done = 0; -+ while (done == 0) { -+ /* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */ -+ if (utime <= _hcd->frame_usecs[i]) { -+ _hcd->frame_usecs[i] -= utime; -+ _qh->frame_usecs[i] += utime; -+ t_left -= utime; -+ ret = i; -+ done = 1; -+ return ret; -+ } else { -+ i++; -+ if (i == 8) { -+ done = 1; -+ ret = -1; -+ } -+ } -+ } -+ return ret; -+} -+ -+/* -+ * use this for FS apps that can span multiple uframes -+ */ -+static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) -+{ -+ int i; -+ int j; -+ unsigned short utime; -+ int t_left; -+ int ret; -+ int done; -+ unsigned short xtime; -+ -+ ret = -1; -+ utime = _qh->usecs; -+ t_left = utime; -+ i = 0; -+ done = 0; -+loop: -+ while (done == 0) { -+ if(_hcd->frame_usecs[i] <= 0) { -+ i++; -+ if (i == 8) { -+ done = 1; -+ ret = -1; -+ } -+ goto loop; -+ } -+ -+ /* -+ * we need n consequtive slots -+ * so use j as a start slot j plus j+1 must be enough time (for now) -+ */ -+ xtime= _hcd->frame_usecs[i]; -+ for (j = i+1 ; j < 8 ; j++ ) { -+ /* -+ * if we add this frame remaining time to xtime we may -+ * be OK, if not we need to test j for a complete frame -+ */ -+ if ((xtime+_hcd->frame_usecs[j]) < utime) { -+ if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) { -+ j = 8; -+ ret = -1; -+ continue; -+ } -+ } -+ if (xtime >= utime) { -+ ret = i; -+ j = 8; /* stop loop with a good value ret */ -+ continue; -+ } -+ /* add the frame time to x time */ -+ xtime += _hcd->frame_usecs[j]; -+ /* we must have a fully available next frame or break */ -+ if ((xtime < utime) -+ && (_hcd->frame_usecs[j] == max_uframe_usecs[j])) { -+ ret = -1; -+ j = 8; /* stop loop with a bad value ret */ -+ continue; -+ } -+ } -+ if (ret >= 0) { -+ t_left = utime; -+ for (j = i; (t_left>0) && (j < 8); j++ ) { -+ t_left -= _hcd->frame_usecs[j]; -+ if ( t_left <= 0 ) { -+ _qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left; -+ _hcd->frame_usecs[j]= -t_left; -+ ret = i; -+ done = 1; -+ } else { -+ _qh->frame_usecs[j] += _hcd->frame_usecs[j]; -+ _hcd->frame_usecs[j] = 0; -+ } -+ } -+ } else { -+ i++; -+ if (i == 8) { -+ done = 1; -+ ret = -1; -+ } -+ } -+ } -+ return ret; -+} -+ -+static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) -+{ -+ int ret; -+ ret = -1; -+ -+ if (_qh->speed == USB_SPEED_HIGH) { -+ /* if this is a hs transaction we need a full frame */ -+ ret = find_single_uframe(_hcd, _qh); -+ } else { -+ /* if this is a fs transaction we may need a sequence of frames */ -+ ret = find_multi_uframe(_hcd, _qh); -+ } -+ return ret; -+} -+ -+/** -+ * Checks that the max transfer size allowed in a host channel is large enough -+ * to handle the maximum data transfer in a single (micro)frame for a periodic -+ * transfer. -+ * -+ * @param _hcd The HCD state structure for the DWC OTG controller. -+ * @param _qh QH for a periodic endpoint. -+ * -+ * @return 0 if successful, negative error code otherwise. -+ */ -+static int check_max_xfer_size(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh) -+{ -+ int status; -+ uint32_t max_xfer_size; -+ uint32_t max_channel_xfer_size; -+ -+ status = 0; -+ -+ max_xfer_size = dwc_max_packet(_qh->maxp) * dwc_hb_mult(_qh->maxp); -+ max_channel_xfer_size = _hcd->core_if->core_params->max_transfer_size; -+ -+ if (max_xfer_size > max_channel_xfer_size) { -+ DWC_NOTICE("%s: Periodic xfer length %d > " -+ "max xfer length for channel %d\n", -+ __func__, max_xfer_size, max_channel_xfer_size); -+ status = -ENOSPC; -+ } -+ -+ return status; -+} -+ -+/** -+ * Schedules an interrupt or isochronous transfer in the periodic schedule. -+ * -+ * @param _hcd The HCD state structure for the DWC OTG controller. -+ * @param _qh QH for the periodic transfer. The QH should already contain the -+ * scheduling information. -+ * -+ * @return 0 if successful, negative error code otherwise. -+ */ -+static int schedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh) -+{ -+ int status = 0; -+ -+ int frame; -+ status = find_uframe(_hcd, _qh); -+ frame = -1; -+ if (status == 0) { -+ frame = 7; -+ } else { -+ if (status > 0 ) -+ frame = status-1; -+ } -+ -+ /* Set the new frame up */ -+ if (frame > -1) { -+ _qh->sched_frame &= ~0x7; -+ _qh->sched_frame |= (frame & 7); -+ } -+ -+ if (status != -1 ) -+ status = 0; -+ if (status) { -+ DWC_NOTICE("%s: Insufficient periodic bandwidth for " -+ "periodic transfer.\n", __func__); -+ return status; -+ } -+ -+ status = check_max_xfer_size(_hcd, _qh); -+ if (status) { -+ DWC_NOTICE("%s: Channel max transfer size too small " -+ "for periodic transfer.\n", __func__); -+ return status; -+ } -+ -+ /* Always start in the inactive schedule. */ -+ list_add_tail(&_qh->qh_list_entry, &_hcd->periodic_sched_inactive); -+ -+ -+ /* Update claimed usecs per (micro)frame. */ -+ _hcd->periodic_usecs += _qh->usecs; -+ -+ /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */ -+ hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated += _qh->usecs / _qh->interval; -+ if (_qh->ep_type == USB_ENDPOINT_XFER_INT) { -+ hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs++; -+ DWC_DEBUGPL(DBG_HCD, "Scheduled intr: qh %p, usecs %d, period %d\n", -+ _qh, _qh->usecs, _qh->interval); -+ } else { -+ hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs++; -+ DWC_DEBUGPL(DBG_HCD, "Scheduled isoc: qh %p, usecs %d, period %d\n", -+ _qh, _qh->usecs, _qh->interval); -+ } -+ -+ return status; -+} -+ -+/** -+ * This function adds a QH to either the non periodic or periodic schedule if -+ * it is not already in the schedule. If the QH is already in the schedule, no -+ * action is taken. -+ * -+ * @return 0 if successful, negative error code otherwise. -+ */ -+int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh) -+{ -+ unsigned long flags; -+ int status = 0; -+ -+ local_irq_save(flags); -+ -+ if (!list_empty(&_qh->qh_list_entry)) { -+ /* QH already in a schedule. */ -+ goto done; -+ } -+ -+ /* Add the new QH to the appropriate schedule */ -+ if (dwc_qh_is_non_per(_qh)) { -+ /* Always start in the inactive schedule. */ -+ list_add_tail(&_qh->qh_list_entry, &_hcd->non_periodic_sched_inactive); -+ } else { -+ status = schedule_periodic(_hcd, _qh); -+ } -+ -+ done: -+ local_irq_restore(flags); -+ -+ return status; -+} -+ -+/** -+ * This function adds a QH to the non periodic deferred schedule. -+ * -+ * @return 0 if successful, negative error code otherwise. -+ */ -+int dwc_otg_hcd_qh_add_deferred(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) -+{ -+ unsigned long flags; -+ local_irq_save(flags); -+ if (!list_empty(&_qh->qh_list_entry)) { -+ /* QH already in a schedule. */ -+ goto done; -+ } -+ -+ /* Add the new QH to the non periodic deferred schedule */ -+ if (dwc_qh_is_non_per(_qh)) { -+ list_add_tail(&_qh->qh_list_entry, -+ &_hcd->non_periodic_sched_deferred); -+ } -+done: -+ local_irq_restore(flags); -+ return 0; -+} -+ -+/** -+ * Removes an interrupt or isochronous transfer from the periodic schedule. -+ * -+ * @param _hcd The HCD state structure for the DWC OTG controller. -+ * @param _qh QH for the periodic transfer. -+ */ -+static void deschedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh) -+{ -+ int i; -+ list_del_init(&_qh->qh_list_entry); -+ -+ -+ /* Update claimed usecs per (micro)frame. */ -+ _hcd->periodic_usecs -= _qh->usecs; -+ -+ for (i = 0; i < 8; i++) { -+ _hcd->frame_usecs[i] += _qh->frame_usecs[i]; -+ _qh->frame_usecs[i] = 0; -+ } -+ /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */ -+ hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated -= _qh->usecs / _qh->interval; -+ -+ if (_qh->ep_type == USB_ENDPOINT_XFER_INT) { -+ hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs--; -+ DWC_DEBUGPL(DBG_HCD, "Descheduled intr: qh %p, usecs %d, period %d\n", -+ _qh, _qh->usecs, _qh->interval); -+ } else { -+ hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs--; -+ DWC_DEBUGPL(DBG_HCD, "Descheduled isoc: qh %p, usecs %d, period %d\n", -+ _qh, _qh->usecs, _qh->interval); -+ } -+} -+ -+/** -+ * Removes a QH from either the non-periodic or periodic schedule. Memory is -+ * not freed. -+ * -+ * @param[in] _hcd The HCD state structure. -+ * @param[in] _qh QH to remove from schedule. */ -+void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh) -+{ -+ unsigned long flags; -+ -+ local_irq_save(flags); -+ -+ if (list_empty(&_qh->qh_list_entry)) { -+ /* QH is not in a schedule. */ -+ goto done; -+ } -+ -+ if (dwc_qh_is_non_per(_qh)) { -+ if (_hcd->non_periodic_qh_ptr == &_qh->qh_list_entry) { -+ _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next; -+ } -+ list_del_init(&_qh->qh_list_entry); -+ } else { -+ deschedule_periodic(_hcd, _qh); -+ } -+ -+ done: -+ local_irq_restore(flags); -+} -+ -+/** -+ * Defers a QH. For non-periodic QHs, removes the QH from the active -+ * non-periodic schedule. The QH is added to the deferred non-periodic -+ * schedule if any QTDs are still attached to the QH. -+ */ -+int dwc_otg_hcd_qh_deferr(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh, int delay) -+{ -+ int deact = 1; -+ unsigned long flags; -+ local_irq_save(flags); -+ if (dwc_qh_is_non_per(_qh)) { -+ _qh->sched_frame = -+ dwc_frame_num_inc(_hcd->frame_number, -+ delay); -+ _qh->channel = NULL; -+ _qh->qtd_in_process = NULL; -+ deact = 0; -+ dwc_otg_hcd_qh_remove(_hcd, _qh); -+ if (!list_empty(&_qh->qtd_list)) { -+ /* Add back to deferred non-periodic schedule. */ -+ dwc_otg_hcd_qh_add_deferred(_hcd, _qh); -+ } -+ } -+ local_irq_restore(flags); -+ return deact; -+} -+ -+/** -+ * Deactivates a QH. For non-periodic QHs, removes the QH from the active -+ * non-periodic schedule. The QH is added to the inactive non-periodic -+ * schedule if any QTDs are still attached to the QH. -+ * -+ * For periodic QHs, the QH is removed from the periodic queued schedule. If -+ * there are any QTDs still attached to the QH, the QH is added to either the -+ * periodic inactive schedule or the periodic ready schedule and its next -+ * scheduled frame is calculated. The QH is placed in the ready schedule if -+ * the scheduled frame has been reached already. Otherwise it's placed in the -+ * inactive schedule. If there are no QTDs attached to the QH, the QH is -+ * completely removed from the periodic schedule. -+ */ -+void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int sched_next_periodic_split) -+{ -+ unsigned long flags; -+ local_irq_save(flags); -+ -+ if (dwc_qh_is_non_per(_qh)) { -+ dwc_otg_hcd_qh_remove(_hcd, _qh); -+ if (!list_empty(&_qh->qtd_list)) { -+ /* Add back to inactive non-periodic schedule. */ -+ dwc_otg_hcd_qh_add(_hcd, _qh); -+ } -+ } else { -+ uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd)); -+ -+ if (_qh->do_split) { -+ /* Schedule the next continuing periodic split transfer */ -+ if (sched_next_periodic_split) { -+ -+ _qh->sched_frame = frame_number; -+ if (dwc_frame_num_le(frame_number, -+ dwc_frame_num_inc(_qh->start_split_frame, 1))) { -+ /* -+ * Allow one frame to elapse after start -+ * split microframe before scheduling -+ * complete split, but DONT if we are -+ * doing the next start split in the -+ * same frame for an ISOC out. -+ */ -+ if ((_qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (_qh->ep_is_in != 0)) { -+ _qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, 1); -+ } -+ } -+ } else { -+ _qh->sched_frame = dwc_frame_num_inc(_qh->start_split_frame, -+ _qh->interval); -+ if (dwc_frame_num_le(_qh->sched_frame, frame_number)) { -+ _qh->sched_frame = frame_number; -+ } -+ _qh->sched_frame |= 0x7; -+ _qh->start_split_frame = _qh->sched_frame; -+ } -+ } else { -+ _qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, _qh->interval); -+ if (dwc_frame_num_le(_qh->sched_frame, frame_number)) { -+ _qh->sched_frame = frame_number; -+ } -+ } -+ -+ if (list_empty(&_qh->qtd_list)) { -+ dwc_otg_hcd_qh_remove(_hcd, _qh); -+ } else { -+ /* -+ * Remove from periodic_sched_queued and move to -+ * appropriate queue. -+ */ -+ if (dwc_frame_num_le(_qh->sched_frame, frame_number)) { -+ list_move(&_qh->qh_list_entry, -+ &_hcd->periodic_sched_ready); -+ } else { -+ list_move(&_qh->qh_list_entry, -+ &_hcd->periodic_sched_inactive); -+ } -+ } -+ } -+ -+ local_irq_restore(flags); -+} -+ -+/** -+ * This function allocates and initializes a QTD. -+ * -+ * @param[in] _urb The URB to create a QTD from. Each URB-QTD pair will end up -+ * pointing to each other so each pair should have a unique correlation. -+ * -+ * @return Returns pointer to the newly allocated QTD, or NULL on error. */ -+dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *_urb) -+{ -+ dwc_otg_qtd_t *qtd; -+ -+ qtd = dwc_otg_hcd_qtd_alloc (); -+ if (qtd == NULL) { -+ return NULL; -+ } -+ -+ dwc_otg_hcd_qtd_init (qtd, _urb); -+ return qtd; -+} -+ -+/** -+ * Initializes a QTD structure. -+ * -+ * @param[in] _qtd The QTD to initialize. -+ * @param[in] _urb The URB to use for initialization. */ -+void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *_qtd, struct urb *_urb) -+{ -+ memset (_qtd, 0, sizeof (dwc_otg_qtd_t)); -+ _qtd->urb = _urb; -+ if (usb_pipecontrol(_urb->pipe)) { -+ /* -+ * The only time the QTD data toggle is used is on the data -+ * phase of control transfers. This phase always starts with -+ * DATA1. -+ */ -+ _qtd->data_toggle = DWC_OTG_HC_PID_DATA1; -+ _qtd->control_phase = DWC_OTG_CONTROL_SETUP; -+ } -+ -+ /* start split */ -+ _qtd->complete_split = 0; -+ _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL; -+ _qtd->isoc_split_offset = 0; -+ -+ /* Store the qtd ptr in the urb to reference what QTD. */ -+ _urb->hcpriv = _qtd; -+ return; -+} -+ -+/** -+ * This function adds a QTD to the QTD-list of a QH. It will find the correct -+ * QH to place the QTD into. If it does not find a QH, then it will create a -+ * new QH. If the QH to which the QTD is added is not currently scheduled, it -+ * is placed into the proper schedule based on its EP type. -+ * -+ * @param[in] _qtd The QTD to add -+ * @param[in] _dwc_otg_hcd The DWC HCD structure -+ * -+ * @return 0 if successful, negative error code otherwise. -+ */ -+int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * _qtd, dwc_otg_hcd_t * _dwc_otg_hcd) -+{ -+ struct usb_host_endpoint *ep; -+ dwc_otg_qh_t *qh; -+ unsigned long flags; -+ int retval = 0; -+ struct urb *urb = _qtd->urb; -+ -+ local_irq_save(flags); -+ -+ /* -+ * Get the QH which holds the QTD-list to insert to. Create QH if it -+ * doesn't exist. -+ */ -+ ep = dwc_urb_to_endpoint(urb); -+ qh = (dwc_otg_qh_t *)ep->hcpriv; -+ if (qh == NULL) { -+ qh = dwc_otg_hcd_qh_create (_dwc_otg_hcd, urb); -+ if (qh == NULL) { -+ retval = -1; -+ goto done; -+ } -+ ep->hcpriv = qh; -+ } -+ -+ _qtd->qtd_qh_ptr = qh; -+ retval = dwc_otg_hcd_qh_add(_dwc_otg_hcd, qh); -+ if (retval == 0) { -+ list_add_tail(&_qtd->qtd_list_entry, &qh->qtd_list); -+ } -+ -+ done: -+ local_irq_restore(flags); -+ return retval; -+} -+ -+#endif /* DWC_DEVICE_ONLY */ ---- /dev/null -+++ b/drivers/usb/dwc_otg/dwc_otg_ifx.c -@@ -0,0 +1,100 @@ -+/****************************************************************************** -+** -+** FILE NAME : dwc_otg_ifx.c -+** PROJECT : Twinpass/Danube -+** MODULES : DWC OTG USB -+** -+** DATE : 12 Auguest 2007 -+** AUTHOR : Sung Winder -+** DESCRIPTION : Platform specific initialization. -+** COPYRIGHT : Copyright (c) 2007 -+** Infineon Technologies AG -+** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park, -+** Hsin-chu City, 300 Taiwan. -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 12 Auguest 2007 Sung Winder Initiate Version -+*******************************************************************************/ -+#include "dwc_otg_ifx.h" -+ -+#include -+#include -+#include -+#include -+ -+#include -+//#include -+#include -+ -+#define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00) -+ -+#define IFXMIPS_GPIO_P0_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0010)) -+#define IFXMIPS_GPIO_P1_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0040)) -+#define IFXMIPS_GPIO_P0_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0014)) -+#define IFXMIPS_GPIO_P1_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0044)) -+#define IFXMIPS_GPIO_P0_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0018)) -+#define IFXMIPS_GPIO_P1_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0048)) -+#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x001C)) -+#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x004C)) -+#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0020)) -+#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0050)) -+#define IFXMIPS_GPIO_P0_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0024)) -+#define IFXMIPS_GPIO_P1_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0054)) -+#define IFXMIPS_GPIO_P0_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0028)) -+#define IFXMIPS_GPIO_P1_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0058)) -+#define IFXMIPS_GPIO_P0_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x002C)) -+#define IFXMIPS_GPIO_P1_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x005C)) -+#define IFXMIPS_GPIO_P0_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0030)) -+#define IFXMIPS_GPIO_P1_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0060)) -+ -+ -+#define writel ltq_w32 -+#define readl ltq_r32 -+void dwc_otg_power_on (void) -+{ -+ // clear power -+ writel(readl(DANUBE_PMU_PWDCR) | 0x41, DANUBE_PMU_PWDCR); -+ // set clock gating -+ writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR); -+ // set power -+ writel(readl(DANUBE_PMU_PWDCR) & ~0x1, DANUBE_PMU_PWDCR); -+ writel(readl(DANUBE_PMU_PWDCR) & ~0x40, DANUBE_PMU_PWDCR); -+ writel(readl(DANUBE_PMU_PWDCR) & ~0x8000, DANUBE_PMU_PWDCR); -+ -+#if 1//defined (DWC_HOST_ONLY) -+ // make the hardware be a host controller (default) -+ //clear_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG); -+ writel(readl(DANUBE_RCU_UBSCFG) & ~(1< -+#include -+ -+// 20070316, winder added. -+#ifndef SZ_256K -+#define SZ_256K 0x00040000 -+#endif -+ -+extern void dwc_otg_power_on (void); -+ -+/* FIXME: The current Linux-2.6 do not have these header files, but anyway, we need these. */ -+// #include -+// #include -+ -+/* winder, I used the Danube parameter as default. * -+ * We could change this through module param. */ -+#define IFX_USB_IOMEM_BASE 0x1e101000 -+#define IFX_USB_IOMEM_SIZE SZ_256K -+#define IFX_USB_IRQ LTQ_USB_INT -+ -+/** -+ * This function is called to set correct clock gating and power. -+ * For Twinpass/Danube board. -+ */ -+#ifndef DANUBE_RCU_BASE_ADDR -+#define DANUBE_RCU_BASE_ADDR (0xBF203000) -+#endif -+ -+#ifndef DANUBE_CGU -+#define DANUBE_CGU (0xBF103000) -+#endif -+#ifndef DANUBE_CGU_IFCCR -+/***CGU Interface Clock Control Register***/ -+#define DANUBE_CGU_IFCCR ((volatile u32*)(DANUBE_CGU+ 0x0018)) -+#endif -+ -+#ifndef DANUBE_PMU -+#define DANUBE_PMU (KSEG1+0x1F102000) -+#endif -+#ifndef DANUBE_PMU_PWDCR -+/* PMU Power down Control Register */ -+#define DANUBE_PMU_PWDCR ((volatile u32*)(DANUBE_PMU+0x001C)) -+#endif -+ -+ -+#define DANUBE_RCU_UBSCFG ((volatile u32*)(DANUBE_RCU_BASE_ADDR + 0x18)) -+#define DANUBE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device -+#define DANUBE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end -+#define DANUBE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end -+ -+extern void ltq_mask_and_ack_irq(struct irq_data *d); -+ -+static void inline mask_and_ack_ifx_irq(int x) -+{ -+ struct irq_data d; -+ d.irq = x; -+ ltq_mask_and_ack_irq(&d); -+} -+#endif //__DWC_OTG_IFX_H__ ---- /dev/null -+++ b/drivers/usb/dwc_otg/dwc_otg_plat.h -@@ -0,0 +1,269 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/platform/dwc_otg_plat.h $ -+ * $Revision: 1.1.1.1 $ -+ * $Date: 2009-04-17 06:15:34 $ -+ * $Change: 510301 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+#if !defined(__DWC_OTG_PLAT_H__) -+#define __DWC_OTG_PLAT_H__ -+ -+#include -+#include -+#include -+#include -+#include -+ -+/** -+ * @file -+ * -+ * This file contains the Platform Specific constants, interfaces -+ * (functions and macros) for Linux. -+ * -+ */ -+/*#if !defined(__LINUX__) -+#error "The contents of this file is Linux specific!!!" -+#endif -+*/ -+#include -+#define writel ltq_w32 -+#define readl ltq_r32 -+ -+/** -+ * Reads the content of a register. -+ * -+ * @param _reg address of register to read. -+ * @return contents of the register. -+ * -+ -+ * Usage:
-+ * uint32_t dev_ctl = dwc_read_reg32(&dev_regs->dctl); -+ */ -+static __inline__ uint32_t dwc_read_reg32( volatile uint32_t *_reg) -+{ -+ return readl(_reg); -+}; -+ -+/** -+ * Writes a register with a 32 bit value. -+ * -+ * @param _reg address of register to read. -+ * @param _value to write to _reg. -+ * -+ * Usage:
-+ * dwc_write_reg32(&dev_regs->dctl, 0); -+ */ -+static __inline__ void dwc_write_reg32( volatile uint32_t *_reg, const uint32_t _value) -+{ -+ writel( _value, _reg ); -+}; -+ -+/** -+ * This function modifies bit values in a register. Using the -+ * algorithm: (reg_contents & ~clear_mask) | set_mask. -+ * -+ * @param _reg address of register to read. -+ * @param _clear_mask bit mask to be cleared. -+ * @param _set_mask bit mask to be set. -+ * -+ * Usage:
-+ * // Clear the SOF Interrupt Mask bit and
-+ * // set the OTG Interrupt mask bit, leaving all others as they were. -+ * dwc_modify_reg32(&dev_regs->gintmsk, DWC_SOF_INT, DWC_OTG_INT); -+ */ -+static __inline__ -+ void dwc_modify_reg32( volatile uint32_t *_reg, const uint32_t _clear_mask, const uint32_t _set_mask) -+{ -+ writel( (readl(_reg) & ~_clear_mask) | _set_mask, _reg ); -+}; -+ -+ -+/** -+ * Wrapper for the OS micro-second delay function. -+ * @param[in] _usecs Microseconds of delay -+ */ -+static __inline__ void UDELAY( const uint32_t _usecs ) -+{ -+ udelay( _usecs ); -+} -+ -+/** -+ * Wrapper for the OS milli-second delay function. -+ * @param[in] _msecs milliseconds of delay -+ */ -+static __inline__ void MDELAY( const uint32_t _msecs ) -+{ -+ mdelay( _msecs ); -+} -+ -+/** -+ * Wrapper for the Linux spin_lock. On the ARM (Integrator) -+ * spin_lock() is a nop. -+ * -+ * @param _lock Pointer to the spinlock. -+ */ -+static __inline__ void SPIN_LOCK( spinlock_t *_lock ) -+{ -+ spin_lock(_lock); -+} -+ -+/** -+ * Wrapper for the Linux spin_unlock. On the ARM (Integrator) -+ * spin_lock() is a nop. -+ * -+ * @param _lock Pointer to the spinlock. -+ */ -+static __inline__ void SPIN_UNLOCK( spinlock_t *_lock ) -+{ -+ spin_unlock(_lock); -+} -+ -+/** -+ * Wrapper (macro) for the Linux spin_lock_irqsave. On the ARM -+ * (Integrator) spin_lock() is a nop. -+ * -+ * @param _l Pointer to the spinlock. -+ * @param _f unsigned long for irq flags storage. -+ */ -+#define SPIN_LOCK_IRQSAVE( _l, _f ) { \ -+ spin_lock_irqsave(_l,_f); \ -+ } -+ -+/** -+ * Wrapper (macro) for the Linux spin_unlock_irqrestore. On the ARM -+ * (Integrator) spin_lock() is a nop. -+ * -+ * @param _l Pointer to the spinlock. -+ * @param _f unsigned long for irq flags storage. -+ */ -+#define SPIN_UNLOCK_IRQRESTORE( _l,_f ) {\ -+ spin_unlock_irqrestore(_l,_f); \ -+ } -+ -+ -+/* -+ * Debugging support vanishes in non-debug builds. -+ */ -+ -+ -+/** -+ * The Debug Level bit-mask variable. -+ */ -+extern uint32_t g_dbg_lvl; -+/** -+ * Set the Debug Level variable. -+ */ -+static inline uint32_t SET_DEBUG_LEVEL( const uint32_t _new ) -+{ -+ uint32_t old = g_dbg_lvl; -+ g_dbg_lvl = _new; -+ return old; -+} -+ -+/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */ -+#define DBG_CIL (0x2) -+/** When debug level has the DBG_CILV bit set, display CIL Verbose debug -+ * messages */ -+#define DBG_CILV (0x20) -+/** When debug level has the DBG_PCD bit set, display PCD (Device) debug -+ * messages */ -+#define DBG_PCD (0x4) -+/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug -+ * messages */ -+#define DBG_PCDV (0x40) -+/** When debug level has the DBG_HCD bit set, display Host debug messages */ -+#define DBG_HCD (0x8) -+/** When debug level has the DBG_HCDV bit set, display Verbose Host debug -+ * messages */ -+#define DBG_HCDV (0x80) -+/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host -+ * mode. */ -+#define DBG_HCD_URB (0x800) -+ -+/** When debug level has any bit set, display debug messages */ -+#define DBG_ANY (0xFF) -+ -+/** All debug messages off */ -+#define DBG_OFF 0 -+ -+/** Prefix string for DWC_DEBUG print macros. */ -+#define USB_DWC "DWC_otg: " -+ -+/** -+ * Print a debug message when the Global debug level variable contains -+ * the bit defined in lvl. -+ * -+ * @param[in] lvl - Debug level, use one of the DBG_ constants above. -+ * @param[in] x - like printf -+ * -+ * Example:

-+ * -+ * DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr); -+ * -+ *
-+ * results in:
-+ * -+ * usb-DWC_otg: dwc_otg_cil_init(ca867000) -+ * -+ */ -+#ifdef DEBUG -+ -+# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)printk( KERN_DEBUG USB_DWC x ); }while(0) -+# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x ) -+ -+# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl) -+ -+#else -+ -+# define DWC_DEBUGPL(lvl, x...) do{}while(0) -+# define DWC_DEBUGP(x...) -+ -+# define CHK_DEBUG_LEVEL(level) (0) -+ -+#endif /*DEBUG*/ -+ -+/** -+ * Print an Error message. -+ */ -+#define DWC_ERROR(x...) printk( KERN_ERR USB_DWC x ) -+/** -+ * Print a Warning message. -+ */ -+#define DWC_WARN(x...) printk( KERN_WARNING USB_DWC x ) -+/** -+ * Print a notice (normal but significant message). -+ */ -+#define DWC_NOTICE(x...) printk( KERN_NOTICE USB_DWC x ) -+/** -+ * Basic message printing. -+ */ -+#define DWC_PRINT(x...) printk( KERN_INFO USB_DWC x ) -+ -+#endif -+ ---- /dev/null -+++ b/drivers/usb/dwc_otg/dwc_otg_regs.h -@@ -0,0 +1,1797 @@ -+/* ========================================================================== -+ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_regs.h $ -+ * $Revision: 1.1.1.1 $ -+ * $Date: 2009-04-17 06:15:34 $ -+ * $Change: 631780 $ -+ * -+ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, -+ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless -+ * otherwise expressly agreed to in writing between Synopsys and you. -+ * -+ * The Software IS NOT an item of Licensed Software or Licensed Product under -+ * any End User Software License Agreement or Agreement for Licensed Product -+ * with Synopsys or any supplement thereto. You are permitted to use and -+ * redistribute this Software in source and binary forms, with or without -+ * modification, provided that redistributions of source code must retain this -+ * notice. You may not view, use, disclose, copy or distribute this file or -+ * any information contained herein except pursuant to this license grant from -+ * Synopsys. If you do not agree with this notice, including the disclaimer -+ * below, then you are not authorized to use the Software. -+ * -+ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, -+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH -+ * DAMAGE. -+ * ========================================================================== */ -+ -+#ifndef __DWC_OTG_REGS_H__ -+#define __DWC_OTG_REGS_H__ -+ -+/** -+ * @file -+ * -+ * This file contains the data structures for accessing the DWC_otg core registers. -+ * -+ * The application interfaces with the HS OTG core by reading from and -+ * writing to the Control and Status Register (CSR) space through the -+ * AHB Slave interface. These registers are 32 bits wide, and the -+ * addresses are 32-bit-block aligned. -+ * CSRs are classified as follows: -+ * - Core Global Registers -+ * - Device Mode Registers -+ * - Device Global Registers -+ * - Device Endpoint Specific Registers -+ * - Host Mode Registers -+ * - Host Global Registers -+ * - Host Port CSRs -+ * - Host Channel Specific Registers -+ * -+ * Only the Core Global registers can be accessed in both Device and -+ * Host modes. When the HS OTG core is operating in one mode, either -+ * Device or Host, the application must not access registers from the -+ * other mode. When the core switches from one mode to another, the -+ * registers in the new mode of operation must be reprogrammed as they -+ * would be after a power-on reset. -+ */ -+ -+/****************************************************************************/ -+/** DWC_otg Core registers . -+ * The dwc_otg_core_global_regs structure defines the size -+ * and relative field offsets for the Core Global registers. -+ */ -+typedef struct dwc_otg_core_global_regs -+{ -+ /** OTG Control and Status Register. Offset: 000h */ -+ volatile uint32_t gotgctl; -+ /** OTG Interrupt Register. Offset: 004h */ -+ volatile uint32_t gotgint; -+ /**Core AHB Configuration Register. Offset: 008h */ -+ volatile uint32_t gahbcfg; -+#define DWC_GLBINTRMASK 0x0001 -+#define DWC_DMAENABLE 0x0020 -+#define DWC_NPTXEMPTYLVL_EMPTY 0x0080 -+#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000 -+#define DWC_PTXEMPTYLVL_EMPTY 0x0100 -+#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000 -+ -+ -+ /**Core USB Configuration Register. Offset: 00Ch */ -+ volatile uint32_t gusbcfg; -+ /**Core Reset Register. Offset: 010h */ -+ volatile uint32_t grstctl; -+ /**Core Interrupt Register. Offset: 014h */ -+ volatile uint32_t gintsts; -+ /**Core Interrupt Mask Register. Offset: 018h */ -+ volatile uint32_t gintmsk; -+ /**Receive Status Queue Read Register (Read Only). Offset: 01Ch */ -+ volatile uint32_t grxstsr; -+ /**Receive Status Queue Read & POP Register (Read Only). Offset: 020h*/ -+ volatile uint32_t grxstsp; -+ /**Receive FIFO Size Register. Offset: 024h */ -+ volatile uint32_t grxfsiz; -+ /**Non Periodic Transmit FIFO Size Register. Offset: 028h */ -+ volatile uint32_t gnptxfsiz; -+ /**Non Periodic Transmit FIFO/Queue Status Register (Read -+ * Only). Offset: 02Ch */ -+ volatile uint32_t gnptxsts; -+ /**I2C Access Register. Offset: 030h */ -+ volatile uint32_t gi2cctl; -+ /**PHY Vendor Control Register. Offset: 034h */ -+ volatile uint32_t gpvndctl; -+ /**General Purpose Input/Output Register. Offset: 038h */ -+ volatile uint32_t ggpio; -+ /**User ID Register. Offset: 03Ch */ -+ volatile uint32_t guid; -+ /**Synopsys ID Register (Read Only). Offset: 040h */ -+ volatile uint32_t gsnpsid; -+ /**User HW Config1 Register (Read Only). Offset: 044h */ -+ volatile uint32_t ghwcfg1; -+ /**User HW Config2 Register (Read Only). Offset: 048h */ -+ volatile uint32_t ghwcfg2; -+#define DWC_SLAVE_ONLY_ARCH 0 -+#define DWC_EXT_DMA_ARCH 1 -+#define DWC_INT_DMA_ARCH 2 -+ -+#define DWC_MODE_HNP_SRP_CAPABLE 0 -+#define DWC_MODE_SRP_ONLY_CAPABLE 1 -+#define DWC_MODE_NO_HNP_SRP_CAPABLE 2 -+#define DWC_MODE_SRP_CAPABLE_DEVICE 3 -+#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4 -+#define DWC_MODE_SRP_CAPABLE_HOST 5 -+#define DWC_MODE_NO_SRP_CAPABLE_HOST 6 -+ -+ /**User HW Config3 Register (Read Only). Offset: 04Ch */ -+ volatile uint32_t ghwcfg3; -+ /**User HW Config4 Register (Read Only). Offset: 050h*/ -+ volatile uint32_t ghwcfg4; -+ /** Reserved Offset: 054h-0FFh */ -+ uint32_t reserved[43]; -+ /** Host Periodic Transmit FIFO Size Register. Offset: 100h */ -+ volatile uint32_t hptxfsiz; -+ /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, -+ otherwise Device Transmit FIFO#n Register. -+ * Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15). */ -+ //volatile uint32_t dptxfsiz[15]; -+ volatile uint32_t dptxfsiz_dieptxf[15]; -+} dwc_otg_core_global_regs_t; -+ -+/** -+ * This union represents the bit fields of the Core OTG Control -+ * and Status Register (GOTGCTL). Set the bits using the bit -+ * fields then write the d32 value to the register. -+ */ -+typedef union gotgctl_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct -+ { -+ unsigned reserved31_21 : 11; -+ unsigned currmod : 1; -+ unsigned bsesvld : 1; -+ unsigned asesvld : 1; -+ unsigned reserved17 : 1; -+ unsigned conidsts : 1; -+ unsigned reserved15_12 : 4; -+ unsigned devhnpen : 1; -+ unsigned hstsethnpen : 1; -+ unsigned hnpreq : 1; -+ unsigned hstnegscs : 1; -+ unsigned reserved7_2 : 6; -+ unsigned sesreq : 1; -+ unsigned sesreqscs : 1; -+ } b; -+} gotgctl_data_t; -+ -+/** -+ * This union represents the bit fields of the Core OTG Interrupt Register -+ * (GOTGINT). Set/clear the bits using the bit fields then write the d32 -+ * value to the register. -+ */ -+typedef union gotgint_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct -+ { -+ /** Current Mode */ -+ unsigned reserved31_20 : 12; -+ /** Debounce Done */ -+ unsigned debdone : 1; -+ /** A-Device Timeout Change */ -+ unsigned adevtoutchng : 1; -+ /** Host Negotiation Detected */ -+ unsigned hstnegdet : 1; -+ unsigned reserver16_10 : 7; -+ /** Host Negotiation Success Status Change */ -+ unsigned hstnegsucstschng : 1; -+ /** Session Request Success Status Change */ -+ unsigned sesreqsucstschng : 1; -+ unsigned reserved3_7 : 5; -+ /** Session End Detected */ -+ unsigned sesenddet : 1; -+ /** Current Mode */ -+ unsigned reserved1_0 : 2; -+ } b; -+} gotgint_data_t; -+ -+ -+/** -+ * This union represents the bit fields of the Core AHB Configuration -+ * Register (GAHBCFG). Set/clear the bits using the bit fields then -+ * write the d32 value to the register. -+ */ -+typedef union gahbcfg_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct -+ { -+#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1 -+#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 -+ unsigned reserved9_31 : 23; -+ unsigned ptxfemplvl : 1; -+ unsigned nptxfemplvl_txfemplvl : 1; -+#define DWC_GAHBCFG_DMAENABLE 1 -+ unsigned reserved : 1; -+ unsigned dmaenable : 1; -+#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0 -+#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1 -+#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3 -+#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5 -+#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7 -+ unsigned hburstlen : 4; -+ unsigned glblintrmsk : 1; -+#define DWC_GAHBCFG_GLBINT_ENABLE 1 -+ -+ } b; -+} gahbcfg_data_t; -+ -+/** -+ * This union represents the bit fields of the Core USB Configuration -+ * Register (GUSBCFG). Set the bits using the bit fields then write -+ * the d32 value to the register. -+ */ -+typedef union gusbcfg_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct -+ { -+ unsigned corrupt_tx_packet: 1; /*fscz*/ -+ unsigned force_device_mode: 1; -+ unsigned force_host_mode: 1; -+ unsigned reserved23_28 : 6; -+ unsigned term_sel_dl_pulse : 1; -+ unsigned ulpi_int_vbus_indicator : 1; -+ unsigned ulpi_ext_vbus_drv : 1; -+ unsigned ulpi_clk_sus_m : 1; -+ unsigned ulpi_auto_res : 1; -+ unsigned ulpi_fsls : 1; -+ unsigned otgutmifssel : 1; -+ unsigned phylpwrclksel : 1; -+ unsigned nptxfrwnden : 1; -+ unsigned usbtrdtim : 4; -+ unsigned hnpcap : 1; -+ unsigned srpcap : 1; -+ unsigned ddrsel : 1; -+ unsigned physel : 1; -+ unsigned fsintf : 1; -+ unsigned ulpi_utmi_sel : 1; -+ unsigned phyif : 1; -+ unsigned toutcal : 3; -+ } b; -+} gusbcfg_data_t; -+ -+/** -+ * This union represents the bit fields of the Core Reset Register -+ * (GRSTCTL). Set/clear the bits using the bit fields then write the -+ * d32 value to the register. -+ */ -+typedef union grstctl_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct -+ { -+ /** AHB Master Idle. Indicates the AHB Master State -+ * Machine is in IDLE condition. */ -+ unsigned ahbidle : 1; -+ /** DMA Request Signal. Indicated DMA request is in -+ * probress. Used for debug purpose. */ -+ unsigned dmareq : 1; -+ /** Reserved */ -+ unsigned reserved29_11 : 19; -+ /** TxFIFO Number (TxFNum) (Device and Host). -+ * -+ * This is the FIFO number which needs to be flushed, -+ * using the TxFIFO Flush bit. This field should not -+ * be changed until the TxFIFO Flush bit is cleared by -+ * the core. -+ * - 0x0 : Non Periodic TxFIFO Flush -+ * - 0x1 : Periodic TxFIFO #1 Flush in device mode -+ * or Periodic TxFIFO in host mode -+ * - 0x2 : Periodic TxFIFO #2 Flush in device mode. -+ * - ... -+ * - 0xF : Periodic TxFIFO #15 Flush in device mode -+ * - 0x10: Flush all the Transmit NonPeriodic and -+ * Transmit Periodic FIFOs in the core -+ */ -+ unsigned txfnum : 5; -+ /** TxFIFO Flush (TxFFlsh) (Device and Host). -+ * -+ * This bit is used to selectively flush a single or -+ * all transmit FIFOs. The application must first -+ * ensure that the core is not in the middle of a -+ * transaction.

The application should write into -+ * this bit, only after making sure that neither the -+ * DMA engine is writing into the TxFIFO nor the MAC -+ * is reading the data out of the FIFO.

The -+ * application should wait until the core clears this -+ * bit, before performing any operations. This bit -+ * will takes 8 clocks (slowest of PHY or AHB clock) -+ * to clear. -+ */ -+ unsigned txfflsh : 1; -+ /** RxFIFO Flush (RxFFlsh) (Device and Host) -+ * -+ * The application can flush the entire Receive FIFO -+ * using this bit.

The application must first -+ * ensure that the core is not in the middle of a -+ * transaction.

The application should write into -+ * this bit, only after making sure that neither the -+ * DMA engine is reading from the RxFIFO nor the MAC -+ * is writing the data in to the FIFO.

The -+ * application should wait until the bit is cleared -+ * before performing any other operations. This bit -+ * will takes 8 clocks (slowest of PHY or AHB clock) -+ * to clear. -+ */ -+ unsigned rxfflsh : 1; -+ /** In Token Sequence Learning Queue Flush -+ * (INTknQFlsh) (Device Only) -+ */ -+ unsigned intknqflsh : 1; -+ /** Host Frame Counter Reset (Host Only)
-+ * -+ * The application can reset the (micro)frame number -+ * counter inside the core, using this bit. When the -+ * (micro)frame counter is reset, the subsequent SOF -+ * sent out by the core, will have a (micro)frame -+ * number of 0. -+ */ -+ unsigned hstfrm : 1; -+ /** Hclk Soft Reset -+ * -+ * The application uses this bit to reset the control logic in -+ * the AHB clock domain. Only AHB clock domain pipelines are -+ * reset. -+ */ -+ unsigned hsftrst : 1; -+ /** Core Soft Reset (CSftRst) (Device and Host) -+ * -+ * The application can flush the control logic in the -+ * entire core using this bit. This bit resets the -+ * pipelines in the AHB Clock domain as well as the -+ * PHY Clock domain. -+ * -+ * The state machines are reset to an IDLE state, the -+ * control bits in the CSRs are cleared, all the -+ * transmit FIFOs and the receive FIFO are flushed. -+ * -+ * The status mask bits that control the generation of -+ * the interrupt, are cleared, to clear the -+ * interrupt. The interrupt status bits are not -+ * cleared, so the application can get the status of -+ * any events that occurred in the core after it has -+ * set this bit. -+ * -+ * Any transactions on the AHB are terminated as soon -+ * as possible following the protocol. Any -+ * transactions on the USB are terminated immediately. -+ * -+ * The configuration settings in the CSRs are -+ * unchanged, so the software doesn't have to -+ * reprogram these registers (Device -+ * Configuration/Host Configuration/Core System -+ * Configuration/Core PHY Configuration). -+ * -+ * The application can write to this bit, any time it -+ * wants to reset the core. This is a self clearing -+ * bit and the core clears this bit after all the -+ * necessary logic is reset in the core, which may -+ * take several clocks, depending on the current state -+ * of the core. -+ */ -+ unsigned csftrst : 1; -+ } b; -+} grstctl_t; -+ -+ -+/** -+ * This union represents the bit fields of the Core Interrupt Mask -+ * Register (GINTMSK). Set/clear the bits using the bit fields then -+ * write the d32 value to the register. -+ */ -+typedef union gintmsk_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct -+ { -+ unsigned wkupintr : 1; -+ unsigned sessreqintr : 1; -+ unsigned disconnect : 1; -+ unsigned conidstschng : 1; -+ unsigned reserved27 : 1; -+ unsigned ptxfempty : 1; -+ unsigned hcintr : 1; -+ unsigned portintr : 1; -+ unsigned reserved22_23 : 2; -+ unsigned incomplisoout : 1; -+ unsigned incomplisoin : 1; -+ unsigned outepintr : 1; -+ unsigned inepintr : 1; -+ unsigned epmismatch : 1; -+ unsigned reserved16 : 1; -+ unsigned eopframe : 1; -+ unsigned isooutdrop : 1; -+ unsigned enumdone : 1; -+ unsigned usbreset : 1; -+ unsigned usbsuspend : 1; -+ unsigned erlysuspend : 1; -+ unsigned i2cintr : 1; -+ unsigned reserved8 : 1; -+ unsigned goutnakeff : 1; -+ unsigned ginnakeff : 1; -+ unsigned nptxfempty : 1; -+ unsigned rxstsqlvl : 1; -+ unsigned sofintr : 1; -+ unsigned otgintr : 1; -+ unsigned modemismatch : 1; -+ unsigned reserved0 : 1; -+ } b; -+} gintmsk_data_t; -+/** -+ * This union represents the bit fields of the Core Interrupt Register -+ * (GINTSTS). Set/clear the bits using the bit fields then write the -+ * d32 value to the register. -+ */ -+typedef union gintsts_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+#define DWC_SOF_INTR_MASK 0x0008 -+ /** register bits */ -+ struct -+ { -+#define DWC_HOST_MODE 1 -+ unsigned wkupintr : 1; -+ unsigned sessreqintr : 1; -+ unsigned disconnect : 1; -+ unsigned conidstschng : 1; -+ unsigned reserved27 : 1; -+ unsigned ptxfempty : 1; -+ unsigned hcintr : 1; -+ unsigned portintr : 1; -+ unsigned reserved22_23 : 2; -+ unsigned incomplisoout : 1; -+ unsigned incomplisoin : 1; -+ unsigned outepintr : 1; -+ unsigned inepint: 1; -+ unsigned epmismatch : 1; -+ unsigned intokenrx : 1; -+ unsigned eopframe : 1; -+ unsigned isooutdrop : 1; -+ unsigned enumdone : 1; -+ unsigned usbreset : 1; -+ unsigned usbsuspend : 1; -+ unsigned erlysuspend : 1; -+ unsigned i2cintr : 1; -+ unsigned reserved8 : 1; -+ unsigned goutnakeff : 1; -+ unsigned ginnakeff : 1; -+ unsigned nptxfempty : 1; -+ unsigned rxstsqlvl : 1; -+ unsigned sofintr : 1; -+ unsigned otgintr : 1; -+ unsigned modemismatch : 1; -+ unsigned curmode : 1; -+ } b; -+} gintsts_data_t; -+ -+ -+/** -+ * This union represents the bit fields in the Device Receive Status Read and -+ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 -+ * element then read out the bits using the bit elements. -+ */ -+typedef union device_grxsts_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned reserved : 7; -+ unsigned fn : 4; -+#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet -+#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete -+ -+#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK -+#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete -+#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet -+ unsigned pktsts : 4; -+ unsigned dpid : 2; -+ unsigned bcnt : 11; -+ unsigned epnum : 4; -+ } b; -+} device_grxsts_data_t; -+ -+/** -+ * This union represents the bit fields in the Host Receive Status Read and -+ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 -+ * element then read out the bits using the bit elements. -+ */ -+typedef union host_grxsts_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned reserved31_21 : 11; -+#define DWC_GRXSTS_PKTSTS_IN 0x2 -+#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3 -+#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5 -+#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7 -+ unsigned pktsts : 4; -+ unsigned dpid : 2; -+ unsigned bcnt : 11; -+ unsigned chnum : 4; -+ } b; -+} host_grxsts_data_t; -+ -+/** -+ * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, -+ * GNPTXFSIZ, DPTXFSIZn). Read the register into the d32 element then -+ * read out the bits using the bit elements. -+ */ -+typedef union fifosize_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned depth : 16; -+ unsigned startaddr : 16; -+ } b; -+} fifosize_data_t; -+ -+/** -+ * This union represents the bit fields in the Non-Periodic Transmit -+ * FIFO/Queue Status Register (GNPTXSTS). Read the register into the -+ * d32 element then read out the bits using the bit -+ * elements. -+ */ -+typedef union gnptxsts_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned reserved : 1; -+ /** Top of the Non-Periodic Transmit Request Queue -+ * - bits 30:27 - Channel/EP Number -+ * - bits 26:25 - Token Type -+ * - bit 24 - Terminate (Last entry for the selected -+ * channel/EP) -+ * - 2'b00 - IN/OUT -+ * - 2'b01 - Zero Length OUT -+ * - 2'b10 - PING/Complete Split -+ * - 2'b11 - Channel Halt -+ -+ */ -+ unsigned nptxqtop_chnep : 4; -+ unsigned nptxqtop_token : 2; -+ unsigned nptxqtop_terminate : 1; -+ unsigned nptxqspcavail : 8; -+ unsigned nptxfspcavail : 16; -+ } b; -+} gnptxsts_data_t; -+ -+/** -+ * This union represents the bit fields in the Transmit -+ * FIFO Status Register (DTXFSTS). Read the register into the -+ * d32 element then read out the bits using the bit -+ * elements. -+ */ -+typedef union dtxfsts_data /* fscz */ //* -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned reserved : 16; -+ unsigned txfspcavail : 16; -+ } b; -+} dtxfsts_data_t; -+ -+/** -+ * This union represents the bit fields in the I2C Control Register -+ * (I2CCTL). Read the register into the d32 element then read out the -+ * bits using the bit elements. -+ */ -+typedef union gi2cctl_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned bsydne : 1; -+ unsigned rw : 1; -+ unsigned reserved : 2; -+ unsigned i2cdevaddr : 2; -+ unsigned i2csuspctl : 1; -+ unsigned ack : 1; -+ unsigned i2cen : 1; -+ unsigned addr : 7; -+ unsigned regaddr : 8; -+ unsigned rwdata : 8; -+ } b; -+} gi2cctl_data_t; -+ -+/** -+ * This union represents the bit fields in the User HW Config1 -+ * Register. Read the register into the d32 element then read -+ * out the bits using the bit elements. -+ */ -+typedef union hwcfg1_data { -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned ep_dir15 : 2; -+ unsigned ep_dir14 : 2; -+ unsigned ep_dir13 : 2; -+ unsigned ep_dir12 : 2; -+ unsigned ep_dir11 : 2; -+ unsigned ep_dir10 : 2; -+ unsigned ep_dir9 : 2; -+ unsigned ep_dir8 : 2; -+ unsigned ep_dir7 : 2; -+ unsigned ep_dir6 : 2; -+ unsigned ep_dir5 : 2; -+ unsigned ep_dir4 : 2; -+ unsigned ep_dir3 : 2; -+ unsigned ep_dir2 : 2; -+ unsigned ep_dir1 : 2; -+ unsigned ep_dir0 : 2; -+ } b; -+} hwcfg1_data_t; -+ -+/** -+ * This union represents the bit fields in the User HW Config2 -+ * Register. Read the register into the d32 element then read -+ * out the bits using the bit elements. -+ */ -+typedef union hwcfg2_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /* GHWCFG2 */ -+ unsigned reserved31 : 1; -+ unsigned dev_token_q_depth : 5; -+ unsigned host_perio_tx_q_depth : 2; -+ unsigned nonperio_tx_q_depth : 2; -+ unsigned rx_status_q_depth : 2; -+ unsigned dynamic_fifo : 1; -+ unsigned perio_ep_supported : 1; -+ unsigned num_host_chan : 4; -+ unsigned num_dev_ep : 4; -+ unsigned fs_phy_type : 2; -+#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 -+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1 -+#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2 -+#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 -+ unsigned hs_phy_type : 2; -+ unsigned point2point : 1; -+ unsigned architecture : 2; -+#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0 -+#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1 -+#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2 -+#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 -+#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 -+#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 -+#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 -+ unsigned op_mode : 3; -+ } b; -+} hwcfg2_data_t; -+ -+/** -+ * This union represents the bit fields in the User HW Config3 -+ * Register. Read the register into the d32 element then read -+ * out the bits using the bit elements. -+ */ -+typedef union hwcfg3_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /* GHWCFG3 */ -+ unsigned dfifo_depth : 16; -+ unsigned reserved15_13 : 3; -+ unsigned ahb_phy_clock_synch : 1; -+ unsigned synch_reset_type : 1; -+ unsigned optional_features : 1; -+ unsigned vendor_ctrl_if : 1; -+ unsigned i2c : 1; -+ unsigned otg_func : 1; -+ unsigned packet_size_cntr_width : 3; -+ unsigned xfer_size_cntr_width : 4; -+ } b; -+} hwcfg3_data_t; -+ -+/** -+ * This union represents the bit fields in the User HW Config4 -+ * Register. Read the register into the d32 element then read -+ * out the bits using the bit elements. -+ */ -+typedef union hwcfg4_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+unsigned reserved31_30 : 2; /* fscz */ -+ unsigned num_in_eps : 4; -+ unsigned ded_fifo_en : 1; -+ -+ unsigned session_end_filt_en : 1; -+ unsigned b_valid_filt_en : 1; -+ unsigned a_valid_filt_en : 1; -+ unsigned vbus_valid_filt_en : 1; -+ unsigned iddig_filt_en : 1; -+ unsigned num_dev_mode_ctrl_ep : 4; -+ unsigned utmi_phy_data_width : 2; -+ unsigned min_ahb_freq : 9; -+ unsigned power_optimiz : 1; -+ unsigned num_dev_perio_in_ep : 4; -+ } b; -+} hwcfg4_data_t; -+ -+//////////////////////////////////////////// -+// Device Registers -+/** -+ * Device Global Registers. Offsets 800h-BFFh -+ * -+ * The following structures define the size and relative field offsets -+ * for the Device Mode Registers. -+ * -+ * These registers are visible only in Device mode and must not be -+ * accessed in Host mode, as the results are unknown. -+ */ -+typedef struct dwc_otg_dev_global_regs -+{ -+ /** Device Configuration Register. Offset 800h */ -+ volatile uint32_t dcfg; -+ /** Device Control Register. Offset: 804h */ -+ volatile uint32_t dctl; -+ /** Device Status Register (Read Only). Offset: 808h */ -+ volatile uint32_t dsts; -+ /** Reserved. Offset: 80Ch */ -+ uint32_t unused; -+ /** Device IN Endpoint Common Interrupt Mask -+ * Register. Offset: 810h */ -+ volatile uint32_t diepmsk; -+ /** Device OUT Endpoint Common Interrupt Mask -+ * Register. Offset: 814h */ -+ volatile uint32_t doepmsk; -+ /** Device All Endpoints Interrupt Register. Offset: 818h */ -+ volatile uint32_t daint; -+ /** Device All Endpoints Interrupt Mask Register. Offset: -+ * 81Ch */ -+ volatile uint32_t daintmsk; -+ /** Device IN Token Queue Read Register-1 (Read Only). -+ * Offset: 820h */ -+ volatile uint32_t dtknqr1; -+ /** Device IN Token Queue Read Register-2 (Read Only). -+ * Offset: 824h */ -+ volatile uint32_t dtknqr2; -+ /** Device VBUS discharge Register. Offset: 828h */ -+ volatile uint32_t dvbusdis; -+ /** Device VBUS Pulse Register. Offset: 82Ch */ -+ volatile uint32_t dvbuspulse; -+ /** Device IN Token Queue Read Register-3 (Read Only). -+ * Device Thresholding control register (Read/Write) -+ * Offset: 830h */ -+ volatile uint32_t dtknqr3_dthrctl; -+ /** Device IN Token Queue Read Register-4 (Read Only). / -+ * Device IN EPs empty Inr. Mask Register (Read/Write) -+ * Offset: 834h */ -+ volatile uint32_t dtknqr4_fifoemptymsk; -+} dwc_otg_device_global_regs_t; -+ -+/** -+ * This union represents the bit fields in the Device Configuration -+ * Register. Read the register into the d32 member then -+ * set/clear the bits using the bit elements. Write the -+ * d32 member to the dcfg register. -+ */ -+typedef union dcfg_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned reserved31_23 : 9; -+ /** In Endpoint Mis-match count */ -+ unsigned epmscnt : 5; -+ unsigned reserved13_17 : 5; -+ /** Periodic Frame Interval */ -+#define DWC_DCFG_FRAME_INTERVAL_80 0 -+#define DWC_DCFG_FRAME_INTERVAL_85 1 -+#define DWC_DCFG_FRAME_INTERVAL_90 2 -+#define DWC_DCFG_FRAME_INTERVAL_95 3 -+ unsigned perfrint : 2; -+ /** Device Addresses */ -+ unsigned devaddr : 7; -+ unsigned reserved3 : 1; -+ /** Non Zero Length Status OUT Handshake */ -+#define DWC_DCFG_SEND_STALL 1 -+ unsigned nzstsouthshk : 1; -+ /** Device Speed */ -+ unsigned devspd : 2; -+ } b; -+} dcfg_data_t; -+ -+/** -+ * This union represents the bit fields in the Device Control -+ * Register. Read the register into the d32 member then -+ * set/clear the bits using the bit elements. -+ */ -+typedef union dctl_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned reserved : 20; -+ /** Power-On Programming Done */ -+ unsigned pwronprgdone : 1; -+ /** Clear Global OUT NAK */ -+ unsigned cgoutnak : 1; -+ /** Set Global OUT NAK */ -+ unsigned sgoutnak : 1; -+ /** Clear Global Non-Periodic IN NAK */ -+ unsigned cgnpinnak : 1; -+ /** Set Global Non-Periodic IN NAK */ -+ unsigned sgnpinnak : 1; -+ /** Test Control */ -+ unsigned tstctl : 3; -+ /** Global OUT NAK Status */ -+ unsigned goutnaksts : 1; -+ /** Global Non-Periodic IN NAK Status */ -+ unsigned gnpinnaksts : 1; -+ /** Soft Disconnect */ -+ unsigned sftdiscon : 1; -+ /** Remote Wakeup */ -+ unsigned rmtwkupsig : 1; -+ } b; -+} dctl_data_t; -+ -+/** -+ * This union represents the bit fields in the Device Status -+ * Register. Read the register into the d32 member then -+ * set/clear the bits using the bit elements. -+ */ -+typedef union dsts_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned reserved22_31 : 10; -+ /** Frame or Microframe Number of the received SOF */ -+ unsigned soffn : 14; -+ unsigned reserved4_7: 4; -+ /** Erratic Error */ -+ unsigned errticerr : 1; -+ /** Enumerated Speed */ -+#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 -+#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 -+#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2 -+#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3 -+ unsigned enumspd : 2; -+ /** Suspend Status */ -+ unsigned suspsts : 1; -+ } b; -+} dsts_data_t; -+ -+ -+/** -+ * This union represents the bit fields in the Device IN EP Interrupt -+ * Register and the Device IN EP Common Mask Register. -+ * -+ * - Read the register into the d32 member then set/clear the -+ * bits using the bit elements. -+ */ -+typedef union diepint_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned reserved07_31 : 23; -+ unsigned txfifoundrn : 1; -+ /** IN Endpoint HAK Effective mask */ -+ unsigned emptyintr : 1; -+ /** IN Endpoint NAK Effective mask */ -+ unsigned inepnakeff : 1; -+ /** IN Token Received with EP mismatch mask */ -+ unsigned intknepmis : 1; -+ /** IN Token received with TxF Empty mask */ -+ unsigned intktxfemp : 1; -+ /** TimeOUT Handshake mask (non-ISOC EPs) */ -+ unsigned timeout : 1; -+ /** AHB Error mask */ -+ unsigned ahberr : 1; -+ /** Endpoint disable mask */ -+ unsigned epdisabled : 1; -+ /** Transfer complete mask */ -+ unsigned xfercompl : 1; -+ } b; -+} diepint_data_t; -+/** -+ * This union represents the bit fields in the Device IN EP Common -+ * Interrupt Mask Register. -+ */ -+typedef union diepint_data diepmsk_data_t; -+ -+/** -+ * This union represents the bit fields in the Device OUT EP Interrupt -+ * Registerand Device OUT EP Common Interrupt Mask Register. -+ * -+ * - Read the register into the d32 member then set/clear the -+ * bits using the bit elements. -+ */ -+typedef union doepint_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned reserved04_31 : 27; -+ /** OUT Token Received when Endpoint Disabled */ -+ unsigned outtknepdis : 1; -+ /** Setup Phase Done (contorl EPs) */ -+ unsigned setup : 1; -+ /** AHB Error */ -+ unsigned ahberr : 1; -+ /** Endpoint disable */ -+ unsigned epdisabled : 1; -+ /** Transfer complete */ -+ unsigned xfercompl : 1; -+ } b; -+} doepint_data_t; -+/** -+ * This union represents the bit fields in the Device OUT EP Common -+ * Interrupt Mask Register. -+ */ -+typedef union doepint_data doepmsk_data_t; -+ -+ -+/** -+ * This union represents the bit fields in the Device All EP Interrupt -+ * and Mask Registers. -+ * - Read the register into the d32 member then set/clear the -+ * bits using the bit elements. -+ */ -+typedef union daint_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** OUT Endpoint bits */ -+ unsigned out : 16; -+ /** IN Endpoint bits */ -+ unsigned in : 16; -+ } ep; -+ struct { -+ /** OUT Endpoint bits */ -+ unsigned outep15 : 1; -+ unsigned outep14 : 1; -+ unsigned outep13 : 1; -+ unsigned outep12 : 1; -+ unsigned outep11 : 1; -+ unsigned outep10 : 1; -+ unsigned outep9 : 1; -+ unsigned outep8 : 1; -+ unsigned outep7 : 1; -+ unsigned outep6 : 1; -+ unsigned outep5 : 1; -+ unsigned outep4 : 1; -+ unsigned outep3 : 1; -+ unsigned outep2 : 1; -+ unsigned outep1 : 1; -+ unsigned outep0 : 1; -+ /** IN Endpoint bits */ -+ unsigned inep15 : 1; -+ unsigned inep14 : 1; -+ unsigned inep13 : 1; -+ unsigned inep12 : 1; -+ unsigned inep11 : 1; -+ unsigned inep10 : 1; -+ unsigned inep9 : 1; -+ unsigned inep8 : 1; -+ unsigned inep7 : 1; -+ unsigned inep6 : 1; -+ unsigned inep5 : 1; -+ unsigned inep4 : 1; -+ unsigned inep3 : 1; -+ unsigned inep2 : 1; -+ unsigned inep1 : 1; -+ unsigned inep0 : 1; -+ } b; -+} daint_data_t; -+ -+/** -+ * This union represents the bit fields in the Device IN Token Queue -+ * Read Registers. -+ * - Read the register into the d32 member. -+ * - READ-ONLY Register -+ */ -+typedef union dtknq1_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** EP Numbers of IN Tokens 0 ... 4 */ -+ unsigned epnums0_5 : 24; -+ /** write pointer has wrapped. */ -+ unsigned wrap_bit : 1; -+ /** Reserved */ -+ unsigned reserved05_06 : 2; -+ /** In Token Queue Write Pointer */ -+ unsigned intknwptr : 5; -+ }b; -+} dtknq1_data_t; -+ -+/** -+ * This union represents Threshold control Register -+ * - Read and write the register into the d32 member. -+ * - READ-WRITABLE Register -+ */ -+typedef union dthrctl_data //* /*fscz */ -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** Reserved */ -+ unsigned reserved26_31 : 6; -+ /** Rx Thr. Length */ -+ unsigned rx_thr_len : 9; -+ /** Rx Thr. Enable */ -+ unsigned rx_thr_en : 1; -+ /** Reserved */ -+ unsigned reserved11_15 : 5; -+ /** Tx Thr. Length */ -+ unsigned tx_thr_len : 9; -+ /** ISO Tx Thr. Enable */ -+ unsigned iso_thr_en : 1; -+ /** non ISO Tx Thr. Enable */ -+ unsigned non_iso_thr_en : 1; -+ -+ }b; -+} dthrctl_data_t; -+ -+/** -+ * Device Logical IN Endpoint-Specific Registers. Offsets -+ * 900h-AFCh -+ * -+ * There will be one set of endpoint registers per logical endpoint -+ * implemented. -+ * -+ * These registers are visible only in Device mode and must not be -+ * accessed in Host mode, as the results are unknown. -+ */ -+typedef struct dwc_otg_dev_in_ep_regs -+{ -+ /** Device IN Endpoint Control Register. Offset:900h + -+ * (ep_num * 20h) + 00h */ -+ volatile uint32_t diepctl; -+ /** Reserved. Offset:900h + (ep_num * 20h) + 04h */ -+ uint32_t reserved04; -+ /** Device IN Endpoint Interrupt Register. Offset:900h + -+ * (ep_num * 20h) + 08h */ -+ volatile uint32_t diepint; -+ /** Reserved. Offset:900h + (ep_num * 20h) + 0Ch */ -+ uint32_t reserved0C; -+ /** Device IN Endpoint Transfer Size -+ * Register. Offset:900h + (ep_num * 20h) + 10h */ -+ volatile uint32_t dieptsiz; -+ /** Device IN Endpoint DMA Address Register. Offset:900h + -+ * (ep_num * 20h) + 14h */ -+ volatile uint32_t diepdma; -+ /** Reserved. Offset:900h + (ep_num * 20h) + 18h - 900h + -+ * (ep_num * 20h) + 1Ch*/ -+ volatile uint32_t dtxfsts; -+ /** Reserved. Offset:900h + (ep_num * 20h) + 1Ch - 900h + -+ * (ep_num * 20h) + 1Ch*/ -+ uint32_t reserved18; -+} dwc_otg_dev_in_ep_regs_t; -+ -+/** -+ * Device Logical OUT Endpoint-Specific Registers. Offsets: -+ * B00h-CFCh -+ * -+ * There will be one set of endpoint registers per logical endpoint -+ * implemented. -+ * -+ * These registers are visible only in Device mode and must not be -+ * accessed in Host mode, as the results are unknown. -+ */ -+typedef struct dwc_otg_dev_out_ep_regs -+{ -+ /** Device OUT Endpoint Control Register. Offset:B00h + -+ * (ep_num * 20h) + 00h */ -+ volatile uint32_t doepctl; -+ /** Device OUT Endpoint Frame number Register. Offset: -+ * B00h + (ep_num * 20h) + 04h */ -+ volatile uint32_t doepfn; -+ /** Device OUT Endpoint Interrupt Register. Offset:B00h + -+ * (ep_num * 20h) + 08h */ -+ volatile uint32_t doepint; -+ /** Reserved. Offset:B00h + (ep_num * 20h) + 0Ch */ -+ uint32_t reserved0C; -+ /** Device OUT Endpoint Transfer Size Register. Offset: -+ * B00h + (ep_num * 20h) + 10h */ -+ volatile uint32_t doeptsiz; -+ /** Device OUT Endpoint DMA Address Register. Offset:B00h -+ * + (ep_num * 20h) + 14h */ -+ volatile uint32_t doepdma; -+ /** Reserved. Offset:B00h + (ep_num * 20h) + 18h - B00h + -+ * (ep_num * 20h) + 1Ch */ -+ uint32_t unused[2]; -+} dwc_otg_dev_out_ep_regs_t; -+ -+/** -+ * This union represents the bit fields in the Device EP Control -+ * Register. Read the register into the d32 member then -+ * set/clear the bits using the bit elements. -+ */ -+typedef union depctl_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** Endpoint Enable */ -+ unsigned epena : 1; -+ /** Endpoint Disable */ -+ unsigned epdis : 1; -+ /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) -+ * Writing to this field sets the Endpoint DPID (DPID) -+ * field in this register to DATA1 Set Odd -+ * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) -+ * Writing to this field sets the Even/Odd -+ * (micro)frame (EO_FrNum) field to odd (micro) frame. -+ */ -+ unsigned setd1pid : 1; -+ /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) -+ * Writing to this field sets the Endpoint DPID (DPID) -+ * field in this register to DATA0. Set Even -+ * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) -+ * Writing to this field sets the Even/Odd -+ * (micro)frame (EO_FrNum) field to even (micro) -+ * frame. -+ */ -+ unsigned setd0pid : 1; -+ /** Set NAK */ -+ unsigned snak : 1; -+ /** Clear NAK */ -+ unsigned cnak : 1; -+ /** Tx Fifo Number -+ * IN EPn/IN EP0 -+ * OUT EPn/OUT EP0 - reserved */ -+ unsigned txfnum : 4; -+ /** Stall Handshake */ -+ unsigned stall : 1; -+ /** Snoop Mode -+ * OUT EPn/OUT EP0 -+ * IN EPn/IN EP0 - reserved */ -+ unsigned snp : 1; -+ /** Endpoint Type -+ * 2'b00: Control -+ * 2'b01: Isochronous -+ * 2'b10: Bulk -+ * 2'b11: Interrupt */ -+ unsigned eptype : 2; -+ /** NAK Status */ -+ unsigned naksts : 1; -+ /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) -+ * This field contains the PID of the packet going to -+ * be received or transmitted on this endpoint. The -+ * application should program the PID of the first -+ * packet going to be received or transmitted on this -+ * endpoint , after the endpoint is -+ * activated. Application use the SetD1PID and -+ * SetD0PID fields of this register to program either -+ * D0 or D1 PID. -+ * -+ * The encoding for this field is -+ * - 0: D0 -+ * - 1: D1 -+ */ -+ unsigned dpid : 1; -+ /** USB Active Endpoint */ -+ unsigned usbactep : 1; -+ /** Next Endpoint -+ * IN EPn/IN EP0 -+ * OUT EPn/OUT EP0 - reserved */ -+ unsigned nextep : 4; -+ /** Maximum Packet Size -+ * IN/OUT EPn -+ * IN/OUT EP0 - 2 bits -+ * 2'b00: 64 Bytes -+ * 2'b01: 32 -+ * 2'b10: 16 -+ * 2'b11: 8 */ -+#define DWC_DEP0CTL_MPS_64 0 -+#define DWC_DEP0CTL_MPS_32 1 -+#define DWC_DEP0CTL_MPS_16 2 -+#define DWC_DEP0CTL_MPS_8 3 -+ unsigned mps : 11; -+ } b; -+} depctl_data_t; -+ -+/** -+ * This union represents the bit fields in the Device EP Transfer -+ * Size Register. Read the register into the d32 member then -+ * set/clear the bits using the bit elements. -+ */ -+typedef union deptsiz_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned reserved : 1; -+ /** Multi Count - Periodic IN endpoints */ -+ unsigned mc : 2; -+ /** Packet Count */ -+ unsigned pktcnt : 10; -+ /** Transfer size */ -+ unsigned xfersize : 19; -+ } b; -+} deptsiz_data_t; -+ -+/** -+ * This union represents the bit fields in the Device EP 0 Transfer -+ * Size Register. Read the register into the d32 member then -+ * set/clear the bits using the bit elements. -+ */ -+typedef union deptsiz0_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned reserved31 : 1; -+ /**Setup Packet Count (DOEPTSIZ0 Only) */ -+ unsigned supcnt : 2; -+ /** Reserved */ -+ unsigned reserved28_20 : 9; -+ /** Packet Count */ -+ unsigned pktcnt : 1; -+ /** Reserved */ -+ unsigned reserved18_7 : 12; -+ /** Transfer size */ -+ unsigned xfersize : 7; -+ } b; -+} deptsiz0_data_t; -+ -+ -+/** Maximum number of Periodic FIFOs */ -+#define MAX_PERIO_FIFOS 15 -+/** Maximum number of TX FIFOs */ -+#define MAX_TX_FIFOS 15 -+/** Maximum number of Endpoints/HostChannels */ -+#define MAX_EPS_CHANNELS 16 -+//#define MAX_EPS_CHANNELS 4 -+ -+/** -+ * The dwc_otg_dev_if structure contains information needed to manage -+ * the DWC_otg controller acting in device mode. It represents the -+ * programming view of the device-specific aspects of the controller. -+ */ -+typedef struct dwc_otg_dev_if { -+ /** Pointer to device Global registers. -+ * Device Global Registers starting at offset 800h -+ */ -+ dwc_otg_device_global_regs_t *dev_global_regs; -+#define DWC_DEV_GLOBAL_REG_OFFSET 0x800 -+ -+ /** -+ * Device Logical IN Endpoint-Specific Registers 900h-AFCh -+ */ -+ dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; -+#define DWC_DEV_IN_EP_REG_OFFSET 0x900 -+#define DWC_EP_REG_OFFSET 0x20 -+ -+ /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */ -+ dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS]; -+#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00 -+ -+ /* Device configuration information*/ -+ uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */ -+ //uint8_t num_eps; /**< Number of EPs range: 0-16 (includes EP0) */ -+ //uint8_t num_perio_eps; /**< # of Periodic EP range: 0-15 */ -+ /*fscz */ -+ uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */ -+ uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/ -+ -+ /** Size of periodic FIFOs (Bytes) */ -+ uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS]; -+ -+ /** Size of Tx FIFOs (Bytes) */ -+ uint16_t tx_fifo_size[MAX_TX_FIFOS]; -+ -+ /** Thresholding enable flags and length varaiables **/ -+ uint16_t rx_thr_en; -+ uint16_t iso_tx_thr_en; -+ uint16_t non_iso_tx_thr_en; -+ -+ uint16_t rx_thr_length; -+ uint16_t tx_thr_length; -+} dwc_otg_dev_if_t; -+ -+/** -+ * This union represents the bit fields in the Power and Clock Gating Control -+ * Register. Read the register into the d32 member then set/clear the -+ * bits using the bit elements. -+ */ -+typedef union pcgcctl_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ -+ /** register bits */ -+ struct { -+ unsigned reserved31_05 : 27; -+ /** PHY Suspended */ -+ unsigned physuspended : 1; -+ /** Reset Power Down Modules */ -+ unsigned rstpdwnmodule : 1; -+ /** Power Clamp */ -+ unsigned pwrclmp : 1; -+ /** Gate Hclk */ -+ unsigned gatehclk : 1; -+ /** Stop Pclk */ -+ unsigned stoppclk : 1; -+ } b; -+} pcgcctl_data_t; -+ -+///////////////////////////////////////////////// -+// Host Mode Register Structures -+// -+/** -+ * The Host Global Registers structure defines the size and relative -+ * field offsets for the Host Mode Global Registers. Host Global -+ * Registers offsets 400h-7FFh. -+*/ -+typedef struct dwc_otg_host_global_regs -+{ -+ /** Host Configuration Register. Offset: 400h */ -+ volatile uint32_t hcfg; -+ /** Host Frame Interval Register. Offset: 404h */ -+ volatile uint32_t hfir; -+ /** Host Frame Number / Frame Remaining Register. Offset: 408h */ -+ volatile uint32_t hfnum; -+ /** Reserved. Offset: 40Ch */ -+ uint32_t reserved40C; -+ /** Host Periodic Transmit FIFO/ Queue Status Register. Offset: 410h */ -+ volatile uint32_t hptxsts; -+ /** Host All Channels Interrupt Register. Offset: 414h */ -+ volatile uint32_t haint; -+ /** Host All Channels Interrupt Mask Register. Offset: 418h */ -+ volatile uint32_t haintmsk; -+} dwc_otg_host_global_regs_t; -+ -+/** -+ * This union represents the bit fields in the Host Configuration Register. -+ * Read the register into the d32 member then set/clear the bits using -+ * the bit elements. Write the d32 member to the hcfg register. -+ */ -+typedef union hcfg_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ -+ /** register bits */ -+ struct { -+ /** Reserved */ -+ //unsigned reserved31_03 : 29; -+ /** FS/LS Only Support */ -+ unsigned fslssupp : 1; -+ /** FS/LS Phy Clock Select */ -+#define DWC_HCFG_30_60_MHZ 0 -+#define DWC_HCFG_48_MHZ 1 -+#define DWC_HCFG_6_MHZ 2 -+ unsigned fslspclksel : 2; -+ } b; -+} hcfg_data_t; -+ -+/** -+ * This union represents the bit fields in the Host Frame Remaing/Number -+ * Register. -+ */ -+typedef union hfir_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ -+ /** register bits */ -+ struct { -+ unsigned reserved : 16; -+ unsigned frint : 16; -+ } b; -+} hfir_data_t; -+ -+/** -+ * This union represents the bit fields in the Host Frame Remaing/Number -+ * Register. -+ */ -+typedef union hfnum_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ -+ /** register bits */ -+ struct { -+ unsigned frrem : 16; -+#define DWC_HFNUM_MAX_FRNUM 0x3FFF -+ unsigned frnum : 16; -+ } b; -+} hfnum_data_t; -+ -+typedef union hptxsts_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ -+ /** register bits */ -+ struct { -+ /** Top of the Periodic Transmit Request Queue -+ * - bit 24 - Terminate (last entry for the selected channel) -+ * - bits 26:25 - Token Type -+ * - 2'b00 - Zero length -+ * - 2'b01 - Ping -+ * - 2'b10 - Disable -+ * - bits 30:27 - Channel Number -+ * - bit 31 - Odd/even microframe -+ */ -+ unsigned ptxqtop_odd : 1; -+ unsigned ptxqtop_chnum : 4; -+ unsigned ptxqtop_token : 2; -+ unsigned ptxqtop_terminate : 1; -+ unsigned ptxqspcavail : 8; -+ unsigned ptxfspcavail : 16; -+ } b; -+} hptxsts_data_t; -+ -+/** -+ * This union represents the bit fields in the Host Port Control and Status -+ * Register. Read the register into the d32 member then set/clear the -+ * bits using the bit elements. Write the d32 member to the -+ * hprt0 register. -+ */ -+typedef union hprt0_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned reserved19_31 : 13; -+#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0 -+#define DWC_HPRT0_PRTSPD_FULL_SPEED 1 -+#define DWC_HPRT0_PRTSPD_LOW_SPEED 2 -+ unsigned prtspd : 2; -+ unsigned prttstctl : 4; -+ unsigned prtpwr : 1; -+ unsigned prtlnsts : 2; -+ unsigned reserved9 : 1; -+ unsigned prtrst : 1; -+ unsigned prtsusp : 1; -+ unsigned prtres : 1; -+ unsigned prtovrcurrchng : 1; -+ unsigned prtovrcurract : 1; -+ unsigned prtenchng : 1; -+ unsigned prtena : 1; -+ unsigned prtconndet : 1; -+ unsigned prtconnsts : 1; -+ } b; -+} hprt0_data_t; -+ -+/** -+ * This union represents the bit fields in the Host All Interrupt -+ * Register. -+ */ -+typedef union haint_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned reserved : 16; -+ unsigned ch15 : 1; -+ unsigned ch14 : 1; -+ unsigned ch13 : 1; -+ unsigned ch12 : 1; -+ unsigned ch11 : 1; -+ unsigned ch10 : 1; -+ unsigned ch9 : 1; -+ unsigned ch8 : 1; -+ unsigned ch7 : 1; -+ unsigned ch6 : 1; -+ unsigned ch5 : 1; -+ unsigned ch4 : 1; -+ unsigned ch3 : 1; -+ unsigned ch2 : 1; -+ unsigned ch1 : 1; -+ unsigned ch0 : 1; -+ } b; -+ struct { -+ unsigned reserved : 16; -+ unsigned chint : 16; -+ } b2; -+} haint_data_t; -+ -+/** -+ * This union represents the bit fields in the Host All Interrupt -+ * Register. -+ */ -+typedef union haintmsk_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ unsigned reserved : 16; -+ unsigned ch15 : 1; -+ unsigned ch14 : 1; -+ unsigned ch13 : 1; -+ unsigned ch12 : 1; -+ unsigned ch11 : 1; -+ unsigned ch10 : 1; -+ unsigned ch9 : 1; -+ unsigned ch8 : 1; -+ unsigned ch7 : 1; -+ unsigned ch6 : 1; -+ unsigned ch5 : 1; -+ unsigned ch4 : 1; -+ unsigned ch3 : 1; -+ unsigned ch2 : 1; -+ unsigned ch1 : 1; -+ unsigned ch0 : 1; -+ } b; -+ struct { -+ unsigned reserved : 16; -+ unsigned chint : 16; -+ } b2; -+} haintmsk_data_t; -+ -+/** -+ * Host Channel Specific Registers. 500h-5FCh -+ */ -+typedef struct dwc_otg_hc_regs -+{ -+ /** Host Channel 0 Characteristic Register. Offset: 500h + (chan_num * 20h) + 00h */ -+ volatile uint32_t hcchar; -+ /** Host Channel 0 Split Control Register. Offset: 500h + (chan_num * 20h) + 04h */ -+ volatile uint32_t hcsplt; -+ /** Host Channel 0 Interrupt Register. Offset: 500h + (chan_num * 20h) + 08h */ -+ volatile uint32_t hcint; -+ /** Host Channel 0 Interrupt Mask Register. Offset: 500h + (chan_num * 20h) + 0Ch */ -+ volatile uint32_t hcintmsk; -+ /** Host Channel 0 Transfer Size Register. Offset: 500h + (chan_num * 20h) + 10h */ -+ volatile uint32_t hctsiz; -+ /** Host Channel 0 DMA Address Register. Offset: 500h + (chan_num * 20h) + 14h */ -+ volatile uint32_t hcdma; -+ /** Reserved. Offset: 500h + (chan_num * 20h) + 18h - 500h + (chan_num * 20h) + 1Ch */ -+ uint32_t reserved[2]; -+} dwc_otg_hc_regs_t; -+ -+/** -+ * This union represents the bit fields in the Host Channel Characteristics -+ * Register. Read the register into the d32 member then set/clear the -+ * bits using the bit elements. Write the d32 member to the -+ * hcchar register. -+ */ -+typedef union hcchar_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ -+ /** register bits */ -+ struct { -+ /** Channel enable */ -+ unsigned chen : 1; -+ /** Channel disable */ -+ unsigned chdis : 1; -+ /** -+ * Frame to transmit periodic transaction. -+ * 0: even, 1: odd -+ */ -+ unsigned oddfrm : 1; -+ /** Device address */ -+ unsigned devaddr : 7; -+ /** Packets per frame for periodic transfers. 0 is reserved. */ -+ unsigned multicnt : 2; -+ /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */ -+ unsigned eptype : 2; -+ /** 0: Full/high speed device, 1: Low speed device */ -+ unsigned lspddev : 1; -+ unsigned reserved : 1; -+ /** 0: OUT, 1: IN */ -+ unsigned epdir : 1; -+ /** Endpoint number */ -+ unsigned epnum : 4; -+ /** Maximum packet size in bytes */ -+ unsigned mps : 11; -+ } b; -+} hcchar_data_t; -+ -+typedef union hcsplt_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ -+ /** register bits */ -+ struct { -+ /** Split Enble */ -+ unsigned spltena : 1; -+ /** Reserved */ -+ unsigned reserved : 14; -+ /** Do Complete Split */ -+ unsigned compsplt : 1; -+ /** Transaction Position */ -+#define DWC_HCSPLIT_XACTPOS_MID 0 -+#define DWC_HCSPLIT_XACTPOS_END 1 -+#define DWC_HCSPLIT_XACTPOS_BEGIN 2 -+#define DWC_HCSPLIT_XACTPOS_ALL 3 -+ unsigned xactpos : 2; -+ /** Hub Address */ -+ unsigned hubaddr : 7; -+ /** Port Address */ -+ unsigned prtaddr : 7; -+ } b; -+} hcsplt_data_t; -+ -+ -+/** -+ * This union represents the bit fields in the Host All Interrupt -+ * Register. -+ */ -+typedef union hcint_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ /** register bits */ -+ struct { -+ /** Reserved */ -+ unsigned reserved : 21; -+ /** Data Toggle Error */ -+ unsigned datatglerr : 1; -+ /** Frame Overrun */ -+ unsigned frmovrun : 1; -+ /** Babble Error */ -+ unsigned bblerr : 1; -+ /** Transaction Err */ -+ unsigned xacterr : 1; -+ /** NYET Response Received */ -+ unsigned nyet : 1; -+ /** ACK Response Received */ -+ unsigned ack : 1; -+ /** NAK Response Received */ -+ unsigned nak : 1; -+ /** STALL Response Received */ -+ unsigned stall : 1; -+ /** AHB Error */ -+ unsigned ahberr : 1; -+ /** Channel Halted */ -+ unsigned chhltd : 1; -+ /** Transfer Complete */ -+ unsigned xfercomp : 1; -+ } b; -+} hcint_data_t; -+ -+/** -+ * This union represents the bit fields in the Host Channel Transfer Size -+ * Register. Read the register into the d32 member then set/clear the -+ * bits using the bit elements. Write the d32 member to the -+ * hcchar register. -+ */ -+typedef union hctsiz_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ -+ /** register bits */ -+ struct { -+ /** Do PING protocol when 1 */ -+ unsigned dopng : 1; -+ /** -+ * Packet ID for next data packet -+ * 0: DATA0 -+ * 1: DATA2 -+ * 2: DATA1 -+ * 3: MDATA (non-Control), SETUP (Control) -+ */ -+#define DWC_HCTSIZ_DATA0 0 -+#define DWC_HCTSIZ_DATA1 2 -+#define DWC_HCTSIZ_DATA2 1 -+#define DWC_HCTSIZ_MDATA 3 -+#define DWC_HCTSIZ_SETUP 3 -+ unsigned pid : 2; -+ /** Data packets to transfer */ -+ unsigned pktcnt : 10; -+ /** Total transfer size in bytes */ -+ unsigned xfersize : 19; -+ } b; -+} hctsiz_data_t; -+ -+/** -+ * This union represents the bit fields in the Host Channel Interrupt Mask -+ * Register. Read the register into the d32 member then set/clear the -+ * bits using the bit elements. Write the d32 member to the -+ * hcintmsk register. -+ */ -+typedef union hcintmsk_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ -+ /** register bits */ -+ struct { -+ unsigned reserved : 21; -+ unsigned datatglerr : 1; -+ unsigned frmovrun : 1; -+ unsigned bblerr : 1; -+ unsigned xacterr : 1; -+ unsigned nyet : 1; -+ unsigned ack : 1; -+ unsigned nak : 1; -+ unsigned stall : 1; -+ unsigned ahberr : 1; -+ unsigned chhltd : 1; -+ unsigned xfercompl : 1; -+ } b; -+} hcintmsk_data_t; -+ -+/** OTG Host Interface Structure. -+ * -+ * The OTG Host Interface Structure structure contains information -+ * needed to manage the DWC_otg controller acting in host mode. It -+ * represents the programming view of the host-specific aspects of the -+ * controller. -+ */ -+typedef struct dwc_otg_host_if { -+ /** Host Global Registers starting at offset 400h.*/ -+ dwc_otg_host_global_regs_t *host_global_regs; -+#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400 -+ -+ /** Host Port 0 Control and Status Register */ -+ volatile uint32_t *hprt0; -+#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440 -+ -+ -+ /** Host Channel Specific Registers at offsets 500h-5FCh. */ -+ dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; -+#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500 -+#define DWC_OTG_CHAN_REGS_OFFSET 0x20 -+ -+ -+ /* Host configuration information */ -+ /** Number of Host Channels (range: 1-16) */ -+ uint8_t num_host_channels; -+ /** Periodic EPs supported (0: no, 1: yes) */ -+ uint8_t perio_eps_supported; -+ /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */ -+ uint16_t perio_tx_fifo_size; -+ -+} dwc_otg_host_if_t; -+ -+#endif diff --git a/target/linux/lantiq/patches-3.3/0045-dwc_otg-remove-bogus-halt_channel.patch b/target/linux/lantiq/patches-3.3/0045-dwc_otg-remove-bogus-halt_channel.patch deleted file mode 100644 index fb66b5d1fe..0000000000 --- a/target/linux/lantiq/patches-3.3/0045-dwc_otg-remove-bogus-halt_channel.patch +++ /dev/null @@ -1,21 +0,0 @@ -From 0cb5a616c2f1aaca4e8946155e84982ae96aae4a Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 23 Mar 2012 16:14:33 +0100 -Subject: [PATCH 45/70] dwc_otg: remove bogus halt_channel - -https://lists.openwrt.org/pipermail/openwrt-devel/2012-March/014524.html ---- - drivers/usb/dwc_otg/dwc_otg_hcd_intr.c | 2 -- - 1 files changed, 0 insertions(+), 2 deletions(-) - ---- a/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c -+++ b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c -@@ -1278,8 +1278,6 @@ static int32_t handle_hc_ack_intr(dwc_ot - * automatically executes the PING, then the transfer. - */ - halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_ACK, must_free); -- } else { -- halt_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free); - } - } - diff --git a/target/linux/lantiq/patches-3.3/0046-MIPS-adds-ifxhcd.patch b/target/linux/lantiq/patches-3.3/0046-MIPS-adds-ifxhcd.patch deleted file mode 100644 index 5c5fad1ad6..0000000000 --- a/target/linux/lantiq/patches-3.3/0046-MIPS-adds-ifxhcd.patch +++ /dev/null @@ -1,16604 +0,0 @@ -From 518d6418815f8ee4189b5ac3455a580fa5f3d3a6 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sun, 11 Mar 2012 15:59:39 +0100 -Subject: [PATCH 46/70] MIPS: adds ifxhcd - ---- - arch/mips/lantiq/xway/Makefile | 2 +- - arch/mips/lantiq/xway/dev-ifxhcd.c | 45 + - arch/mips/lantiq/xway/dev-ifxhcd.h | 17 + - arch/mips/lantiq/xway/sysctrl.c | 2 + - drivers/usb/Kconfig | 2 + - drivers/usb/Makefile | 2 + - drivers/usb/ifxhcd/Kconfig | 58 + - drivers/usb/ifxhcd/Makefile | 85 + - drivers/usb/ifxhcd/TagHistory | 171 ++ - drivers/usb/ifxhcd/ifxhcd.c | 2523 +++++++++++++++++++++++ - drivers/usb/ifxhcd/ifxhcd.h | 628 ++++++ - drivers/usb/ifxhcd/ifxhcd_es.c | 549 +++++ - drivers/usb/ifxhcd/ifxhcd_intr.c | 3742 +++++++++++++++++++++++++++++++++++ - drivers/usb/ifxhcd/ifxhcd_queue.c | 418 ++++ - drivers/usb/ifxhcd/ifxusb_cif.c | 1458 ++++++++++++++ - drivers/usb/ifxhcd/ifxusb_cif.h | 665 +++++++ - drivers/usb/ifxhcd/ifxusb_cif_d.c | 458 +++++ - drivers/usb/ifxhcd/ifxusb_cif_h.c | 846 ++++++++ - drivers/usb/ifxhcd/ifxusb_ctl.c | 1385 +++++++++++++ - drivers/usb/ifxhcd/ifxusb_driver.c | 970 +++++++++ - drivers/usb/ifxhcd/ifxusb_plat.h | 1018 ++++++++++ - drivers/usb/ifxhcd/ifxusb_regs.h | 1420 +++++++++++++ - drivers/usb/ifxhcd/ifxusb_version.h | 5 + - 23 files changed, 16468 insertions(+), 1 deletions(-) - create mode 100644 arch/mips/lantiq/xway/dev-ifxhcd.c - create mode 100644 arch/mips/lantiq/xway/dev-ifxhcd.h - create mode 100644 drivers/usb/ifxhcd/Kconfig - create mode 100644 drivers/usb/ifxhcd/Makefile - create mode 100644 drivers/usb/ifxhcd/TagHistory - create mode 100644 drivers/usb/ifxhcd/ifxhcd.c - create mode 100644 drivers/usb/ifxhcd/ifxhcd.h - create mode 100644 drivers/usb/ifxhcd/ifxhcd_es.c - create mode 100644 drivers/usb/ifxhcd/ifxhcd_intr.c - create mode 100644 drivers/usb/ifxhcd/ifxhcd_queue.c - create mode 100644 drivers/usb/ifxhcd/ifxusb_cif.c - create mode 100644 drivers/usb/ifxhcd/ifxusb_cif.h - create mode 100644 drivers/usb/ifxhcd/ifxusb_cif_d.c - create mode 100644 drivers/usb/ifxhcd/ifxusb_cif_h.c - create mode 100644 drivers/usb/ifxhcd/ifxusb_ctl.c - create mode 100644 drivers/usb/ifxhcd/ifxusb_driver.c - create mode 100644 drivers/usb/ifxhcd/ifxusb_plat.h - create mode 100644 drivers/usb/ifxhcd/ifxusb_regs.h - create mode 100644 drivers/usb/ifxhcd/ifxusb_version.h - ---- a/arch/mips/lantiq/xway/Makefile -+++ b/arch/mips/lantiq/xway/Makefile -@@ -1,4 +1,4 @@ --obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o timer.o -+obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o timer.o dev-ifxhcd.o - - obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o - obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o ---- /dev/null -+++ b/arch/mips/lantiq/xway/dev-ifxhcd.c -@@ -0,0 +1,45 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * Copyright (C) 2012 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+#include -+#include -+ -+static u64 dmamask = (u32)0x1fffffff; -+ -+static struct platform_device platform_dev = { -+ .name = "ifxusb_hcd", -+ .dev.dma_mask = &dmamask, -+}; -+ -+int __init -+xway_register_hcd(int *pins) -+{ -+ platform_dev.dev.platform_data = pins; -+ return platform_device_register(&platform_dev); -+} ---- /dev/null -+++ b/arch/mips/lantiq/xway/dev-ifxhcd.h -@@ -0,0 +1,17 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * Copyright (C) 2012 John Crispin -+ */ -+ -+#ifndef _LTQ_DEV_HCD_H__ -+#define _LTQ_DEV_HCD_H__ -+ -+#include -+ -+extern void __init xway_register_hcd(int *pin); -+ -+#endif ---- a/arch/mips/lantiq/xway/sysctrl.c -+++ b/arch/mips/lantiq/xway/sysctrl.c -@@ -166,6 +166,8 @@ void __init ltq_soc_init(void) - clkdev_add_pmu("ltq_pcie", "pdi", 1, PMU1_PCIE_PDI); - clkdev_add_pmu("ltq_pcie", "ctl", 1, PMU1_PCIE_CTL); - clkdev_add_pmu("ltq_pcie", "ahb", 0, PMU_AHBM | PMU_AHBS); -+ clkdev_add_pmu("usb0", NULL, 0, (1<<6) | 1); -+ clkdev_add_pmu("usb1", NULL, 0, (1<<26) | (1<<27)); - } else { - clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(), - ltq_danube_io_region_clock()); ---- a/drivers/usb/Kconfig -+++ b/drivers/usb/Kconfig -@@ -184,4 +184,6 @@ source "drivers/usb/gadget/Kconfig" - - source "drivers/usb/otg/Kconfig" - -+source "drivers/usb/ifxhcd/Kconfig" -+ - endif # USB_SUPPORT ---- a/drivers/usb/Makefile -+++ b/drivers/usb/Makefile -@@ -58,3 +58,5 @@ obj-$(CONFIG_USB_RENESAS_USBHS) += renes - obj-$(CONFIG_USB_GADGET) += gadget/ - - obj-$(CONFIG_USB_COMMON) += usb-common.o -+ -+obj-$(CONFIG_USB_HOST_IFX) += ifxhcd/ ---- /dev/null -+++ b/drivers/usb/ifxhcd/Kconfig -@@ -0,0 +1,58 @@ -+ -+config USB_HOST_IFX -+ tristate "Infineon USB Host Controller Driver" -+ depends on USB -+ default n -+ help -+ Infineon USB Host Controller -+ -+config USB_HOST_IFX_B -+ bool "USB host mode on core 1 and 2" -+ depends on USB_HOST_IFX -+ help -+ Both cores run as host -+ -+#config USB_HOST_IFX_1 -+#config USB_HOST_IFX_2 -+ -+#config IFX_DANUBE -+#config IFX_AMAZON_SE -+config IFX_AR9 -+ depends on USB_HOST_IFX -+ bool "AR9" -+ -+config IFX_VR9 -+ depends on USB_HOST_IFX -+ bool "VR9" -+ -+#config USB_HOST_IFX_FORCE_USB11 -+# bool "Forced USB1.1" -+# depends on USB_HOST_IFX -+# default n -+# help -+# force to be USB 1.1 -+ -+#config USB_HOST_IFX_WITH_HS_ELECT_TST -+# bool "With HS_Electrical Test" -+# depends on USB_HOST_IFX -+# default n -+# help -+# With USBIF HSET routines -+ -+#config USB_HOST_IFX_WITH_ISO -+# bool "With ISO transfer" -+# depends on USB_HOST_IFX -+# default n -+# help -+# With USBIF ISO transfer -+ -+config USB_HOST_IFX_UNALIGNED_ADJ -+ bool "Adjust" -+ depends on USB_HOST_IFX -+ help -+ USB_HOST_IFX_UNALIGNED_ADJ -+ -+#config USB_HOST_IFX_UNALIGNED_CHK -+#config USB_HOST_IFX_UNALIGNED_NONE -+ -+ ---- /dev/null -+++ b/drivers/usb/ifxhcd/Makefile -@@ -0,0 +1,85 @@ -+ -+# -+# Makefile for USB Core files and filesystem -+# -+ ifxusb_host-objs := ifxusb_driver.o -+ ifxusb_host-objs += ifxusb_ctl.o -+ ifxusb_host-objs += ifxusb_cif.o -+ ifxusb_host-objs += ifxusb_cif_h.o -+ ifxusb_host-objs += ifxhcd.o -+ ifxusb_host-objs += ifxhcd_es.o -+ ifxusb_host-objs += ifxhcd_intr.o -+ ifxusb_host-objs += ifxhcd_queue.o -+ -+ifeq ($(CONFIG_IFX_TWINPASS),y) -+ EXTRA_CFLAGS += -D__IS_TWINPASS__ -+endif -+ifeq ($(CONFIG_IFX_DANUBE),y) -+ EXTRA_CFLAGS += -D__IS_DANUBE__ -+endif -+ifeq ($(CONFIG_IFX_AMAZON_SE),y) -+ EXTRA_CFLAGS += -D__IS_AMAZON_SE__ -+endif -+ifeq ($(CONFIG_IFX_AR9),y) -+ EXTRA_CFLAGS += -D__IS_AR9__ -+endif -+ifeq ($(CONFIG_IFX_AMAZON_S),y) -+ EXTRA_CFLAGS += -D__IS_AR9__ -+endif -+ifeq ($(CONFIG_IFX_VR9),y) -+ EXTRA_CFLAGS += -D__IS_VR9__ -+endif -+ -+ifeq ($(CONFIG_USB_HOST_IFX),y) -+ EXTRA_CFLAGS += -Dlinux -D__LINUX__ -+ EXTRA_CFLAGS += -D__IS_HOST__ -+ EXTRA_CFLAGS += -D__KERNEL__ -+endif -+ -+ifeq ($(CONFIG_USB_HOST_IFX),m) -+ EXTRA_CFLAGS += -Dlinux -D__LINUX__ -+ EXTRA_CFLAGS += -D__IS_HOST__ -+ EXTRA_CFLAGS += -D__KERNEL__ -+endif -+ -+ifeq ($(CONFIG_USB_DEBUG),y) -+ EXTRA_CFLAGS += -D__DEBUG__ -+ EXTRA_CFLAGS += -D__ENABLE_DUMP__ -+endif -+ -+ifeq ($(CONFIG_USB_HOST_IFX_B),y) -+ EXTRA_CFLAGS += -D__IS_DUAL__ -+endif -+ifeq ($(CONFIG_USB_HOST_IFX_1),y) -+ EXTRA_CFLAGS += -D__IS_FIRST__ -+endif -+ifeq ($(CONFIG_USB_HOST_IFX_2),y) -+ EXTRA_CFLAGS += -D__IS_SECOND__ -+endif -+ -+ifeq ($(CONFIG_USB_HOST_IFX_FORCE_USB11),y) -+ EXTRA_CFLAGS += -D__FORCE_USB11__ -+endif -+ifeq ($(CONFIG_USB_HOST_IFX_WITH_HS_ELECT_TST),y) -+ EXTRA_CFLAGS += -D__WITH_HS_ELECT_TST__ -+endif -+ifeq ($(CONFIG_USB_HOST_IFX_WITH_ISO),y) -+ EXTRA_CFLAGS += -D__EN_ISOC__ -+endif -+ifeq ($(CONFIG_USB_HOST_IFX_UNALIGNED_ADJ),y) -+ EXTRA_CFLAGS += -D__UNALIGNED_BUFFER_ADJ__ -+endif -+ifeq ($(CONFIG_USB_HOST_IFX_UNALIGNED_CHK),y) -+ EXTRA_CFLAGS += -D__UNALIGNED_BUFFER_CHK__ -+endif -+ -+# EXTRA_CFLAGS += -D__DYN_SOF_INTR__ -+ EXTRA_CFLAGS += -D__UEIP__ -+# EXTRA_CFLAGS += -D__EN_ISOC__ -+# EXTRA_CFLAGS += -D__EN_ISOC_SPLIT__ -+ -+## 20110628 AVM/WK New flag for less SOF IRQs -+ EXTRA_CFLAGS += -D__USE_TIMER_4_SOF__ -+ -+obj-$(CONFIG_USB_HOST_IFX) += ifxusb_host.o -+ ---- /dev/null -+++ b/drivers/usb/ifxhcd/TagHistory -@@ -0,0 +1,171 @@ -+ -+ -++----------------------------------------------------------------------+ -+| TAG: svn://embeddedvm/home/SVN/drivers/usb_host20/tags/5.18-r240-non_musb_ar9_vr9-SOF_Timer_Fixed -+| Erzeugt mit SVN-Tagger Version 3.74. -++----------------------------------------------------------------------+ -+FIX - Korrektur bei der SOF-Timer/IRQ Steuerung. (Bug in Tag 5.17) -+FIX - Fehlerbehandlung an mehreren Stellen korrigiert bzw. eingebaut. -+ -+ -+ -++----------------------------------------------------------------------+ -+| TAG: svn://embeddedvm/home/SVN/drivers/usb_host20/tags/5.17-r237-non_musb_ar9_vr9-2_6_32_41_Kompatibel -+| Erzeugt mit SVN-Tagger Version 3.73. -++----------------------------------------------------------------------+ -+FIX - Kompatiblität zum Update auf Kernel 2.6.32-41. Weiterhin für 28er geeignet. -+ENH - Reduktion der Interrruptlast durch Nutzung eines hrtimers anstatt SOF-IRQ. -+ -+ -+ -++----------------------------------------------------------------------+ -+| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.16-r208-non_musb_ar9_vr9-20110421_Zero_Paket_Optimiert -+| Erzeugt mit SVN-Tagger Version 3.66. -++----------------------------------------------------------------------+ -+ -+FIX - VR9 / AR9 - Zero Packet. Optimierung korrigiert. -+ -+ -+ -++----------------------------------------------------------------------+ -+| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.15-r205-non_musb_ar9_vr9-20110421_Zero_Paket_WA_funktioniert -+| Erzeugt mit SVN-Tagger Version 3.66. -++----------------------------------------------------------------------+ -+ -+FIX - VR9 / AR9 - "Zero Packet" funktioniert nun wirklich. Letzter Tag hatte einen Bug. -+ -+ -+ -++----------------------------------------------------------------------+ -+| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.14-r202-non_musb_ar9_vr9-20110420_Zero_Paket_WA -+| Erzeugt mit SVN-Tagger Version 3.66. -++----------------------------------------------------------------------+ -+ -+FIX - VR9 / AR9 - Zero Packet Workaround: ZLP wird nun geschickt wenn URB_ZERO_PACKET aktiv ist. -+ Wird von LTE Altair Firmware benoetig. -+ -+ -+ -++----------------------------------------------------------------------+ -+| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.13-r199-non_musb_ar9_vr9-20110310_Init_Fix -+| Erzeugt mit SVN-Tagger Version 3.64. -++----------------------------------------------------------------------+ -+ -+FIX - VR9 / AR9 - Timing der Initialisierungsphase angepasst zum Kernel 2.6.28 mit UGW-4.3.1. -+ -+ -+ -++----------------------------------------------------------------------+ -+| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.12-r184-non_musb_ar9_vr9-20110118_Full_Speed_Fix -+| Erzeugt mit SVN-Tagger Version 3.58. -++----------------------------------------------------------------------+ -+AR9/VR9 (3370,6840,7320): -+Makefile - FIX - (Workaround) Debug Modus hilft gegen Enumerationsfehler bei Full Speed Drucker. -+ -+ -+ -++----------------------------------------------------------------------+ -+| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.11-r175-non_musb_ar9_vr9-20101220_VR9_2_Ports_DMA_Fix -+| Erzeugt mit SVN-Tagger Version 3.58. -++----------------------------------------------------------------------+ -+ -+FIX - VR9 - Workaround DMA Burst Size. Wenn beiden USB Ports benutzt werden, geht der USB Host nicht mehr. -+ -+ -+ -++----------------------------------------------------------------------+ -+| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.10-r169-non_musb_ar9_vr9-Fix_Spontan_Reboot -+| Erzeugt mit SVN-Tagger Version 3.58. -++----------------------------------------------------------------------+ -+ -+FIX - Endlosschleife führte zu einem spontanen Reboot. -+ -+ -+ -++----------------------------------------------------------------------+ -+| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.9-r166-non_musb_ar9_vr9-20101112_deferred_completion -+| Erzeugt mit SVN-Tagger Version 3.58. -++----------------------------------------------------------------------+ -+ -+ENH - Deferred URB Completion Mechanismus eingebaut. Nun ca. 10% schneller bei usb-storage. -+ -+FIX - PING Flow Control gefixt. -+FIX - Channel Halt wird nun immer angerufen. (Split Transaction wurde nicht erfolgreich gestoppt). -+FIX - Spinlock Benutzung verbessert. Mehr Stabilitaet. -+ -+CHG - Ubersetztungsoption __DEBUG__ ist nun abhaengig von CONFIG_USB_DEBUG -+ -+ -+ -++----------------------------------------------------------------------+ -+| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.8-r149-non_musb_ar9_vr9-20100827_LTE_Interrupt_EP_Fix -+| Erzeugt mit SVN-Tagger Version 3.57. -++----------------------------------------------------------------------+ -+AR9/VR9 - FIX - Interrupt Packets gingen verloren, wegen falschem Timing beim OddFrame Bit. -+ -+ -+ -++----------------------------------------------------------------------+ -+| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.7-r142-non_musb_ar9_vr9-20100728_Unaligned_Buf_Fix -+| Erzeugt mit SVN-Tagger Version 3.57. -++----------------------------------------------------------------------+ -+FIX - "Unaligned Data" Flag wieder nach Transfer geloescht. -+ -+ -+ -++----------------------------------------------------------------------+ -+| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.6-r133-non_musb_ar9_vr9-20100714_Toggle_Datenverlust_Fix -+| Erzeugt mit SVN-Tagger Version 3.57. -++----------------------------------------------------------------------+ -+TL5508 - Einige UMTS Modems funktionierten nicht korrekt an der 7320 (AR9). -+FIX - USB Data Toggle des usbcore benutzen. Datenverlust nach EP-Halt. -+ -+ -+ -++----------------------------------------------------------------------+ -+| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.5-r130-non_musb_ar9_vr9-20100712_USB_Ports_abschaltbar -+| Erzeugt mit SVN-Tagger Version 3.57. -++----------------------------------------------------------------------+ -+Power - Fix - Beide USB Port abschaltbar bei rmmod. -+rmmod - FIX - URB_Dequeue funktionierte beim Entladen des Treibers nicht (mehrere Ursachen). -+ -+ -+ -++----------------------------------------------------------------------+ -+| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.4-r126-non_musb_ar9_vr9-20100701_Lost_Interrupt_Workaround -+| Erzeugt mit SVN-Tagger Version 3.57. -++----------------------------------------------------------------------+ -+FIX - Workaround wegen verpasstem Interrupt, bei Full-Speed Interrupt EP. -+ -+ -++----------------------------------------------------------------------+ -+| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.3-r123-non_musb_ar9_vr9-20100630_UMTS_Fixes -+| Erzeugt mit SVN-Tagger Version 3.57. -++----------------------------------------------------------------------+ -+FIX - Full-Speed Interrupt Endpoint hinter Hi-Speed Hub funktioniert nun (UMTS Modems) -+FIX - usb_hcd_link_urb_from_ep API von USBCore muss benutzt werden. -+FIX - Interrupt URBs nicht bei NAK completen. -+ -+ -++----------------------------------------------------------------------+ -+| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.2-r114-non_musb_ar9_vr9-20100520_StickAndSurf_funktioniert -+| Erzeugt mit SVN-Tagger Version 3.56. -++----------------------------------------------------------------------+ -+- Merge mit neuen LANTIQ Sourcen "3.0alpha B100312" -+- Fix - Spin_lock eingebaut, Stick&Surf funktioniert nun -+ -+- DEP - CONFIG_USB_HOST_IFX_WITH_ISO wird nicht unterstuetzt: In der Kernel Config deaktivieren. -+ -+ -+ -++----------------------------------------------------------------------+ -+| TAG: svn://EmbeddedVM/home/SVN/drivers/usb_host20/tags/5.1-r107-non_musb_ar9_vr9-20100505_IFXUSB_Host_mit_Energiemonitor -+| Erzeugt mit SVN-Tagger Version 3.56. -++----------------------------------------------------------------------+ -+USB Host Treiber für AR9 und VR9 -+-------------------------------- -+FIX - Toggle Error nach STALL - Einfacher Workaround - Nun werden Massenspeicherpartitionen erkannt! -+AVM_POWERMETER - USB Energiemonitor Support. -+ -+Bekanntes Problem: Stick and Surf funktioniert nur sporadisch, weil CONTROL_IRQ manchmal ausbleibt. -+ ---- /dev/null -+++ b/drivers/usb/ifxhcd/ifxhcd.c -@@ -0,0 +1,2523 @@ -+/***************************************************************************** -+ ** FILE NAME : ifxhcd.c -+ ** PROJECT : IFX USB sub-system V3 -+ ** MODULES : IFX USB sub-system Host and Device driver -+ ** SRC VERSION : 1.0 -+ ** DATE : 1/Jan/2009 -+ ** AUTHOR : Chen, Howard -+ ** DESCRIPTION : This file contains the structures, constants, and interfaces for -+ ** the Host Contoller Driver (HCD). -+ ** -+ ** The Host Controller Driver (HCD) is responsible for translating requests -+ ** from the USB Driver into the appropriate actions on the IFXUSB controller. -+ ** It isolates the USBD from the specifics of the controller by providing an -+ ** API to the USBD. -+ *****************************************************************************/ -+ -+/*! -+ \file ifxhcd.c -+ \ingroup IFXUSB_DRIVER_V3 -+ \brief This file contains the implementation of the HCD. In Linux, -+ the HCD implements the hc_driver API. -+*/ -+ -+#include -+#include "ifxusb_version.h" -+ -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include -+ -+ -+#include "ifxusb_plat.h" -+#include "ifxusb_regs.h" -+#include "ifxusb_cif.h" -+#include "ifxhcd.h" -+ -+#include -+ -+#ifdef CONFIG_AVM_POWERMETER -+#include -+#endif /*--- #ifdef CONFIG_AVM_POWERMETER ---*/ -+ -+#ifdef __DEBUG__ -+ static void dump_urb_info(struct urb *_urb, char* _fn_name); -+ static void dump_channel_info(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh); -+#endif -+ -+ -+/*! -+ \brief Sets the final status of an URB and returns it to the device driver. Any -+ required cleanup of the URB is performed. -+ */ -+void ifxhcd_complete_urb(ifxhcd_hcd_t *_ifxhcd, ifxhcd_urbd_t *_urbd, int _status) -+{ -+ struct urb *urb=NULL; -+ unsigned long flags = 0; -+ -+ /*== AVM/BC 20101111 Function called with Lock ==*/ -+ //SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags); -+ -+ if (!list_empty(&_urbd->urbd_list_entry)) -+ list_del_init (&_urbd->urbd_list_entry); -+ -+ if(!_urbd->urb) -+ { -+ IFX_ERROR("%s: invalid urb\n",__func__); -+ /*== AVM/BC 20101111 Function called with Lock ==*/ -+ //SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); -+ return; -+ } -+ -+ urb=_urbd->urb; -+ -+ #ifdef __DEBUG__ -+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) -+ { -+ IFX_PRINT("%s: _urbd %p, urb %p, device %d, ep %d %s/%s, status=%d\n", -+ __func__, _urbd,_urbd->urb, usb_pipedevice(_urbd->urb->pipe), -+ usb_pipeendpoint(_urbd->urb->pipe), -+ usb_pipein(_urbd->urb->pipe) ? "IN" : "OUT", -+ (_urbd->is_in) ? "IN" : "OUT", -+ _status); -+ if (_urbd->epqh->ep_type == IFXUSB_EP_TYPE_ISOC) -+ { -+ int i; -+ for (i = 0; i < _urbd->urb->number_of_packets; i++) -+ IFX_PRINT(" ISO Desc %d status: %d\n", i, _urbd->urb->iso_frame_desc[i].status); -+ } -+ } -+ #endif -+ -+ if (!_urbd->epqh) -+ IFX_ERROR("%s: invalid epqd\n",__func__); -+ -+ #if defined(__UNALIGNED_BUFFER_ADJ__) -+ else if(_urbd->is_active) -+ { -+ if( _urbd->epqh->aligned_checked && -+ _urbd->epqh->using_aligned_buf && -+ _urbd->xfer_buff && -+ _urbd->is_in ) -+ memcpy(_urbd->xfer_buff,_urbd->epqh->aligned_buf,_urbd->xfer_len); -+ _urbd->epqh->using_aligned_buf=0; -+ _urbd->epqh->using_aligned_setup=0; -+ _urbd->epqh->aligned_checked=0; -+ } -+ #endif -+ -+ urb->status = _status; -+ urb->hcpriv=NULL; -+ kfree(_urbd); -+ -+ usb_hcd_unlink_urb_from_ep(ifxhcd_to_syshcd(_ifxhcd), urb); -+ SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); -+ -+// usb_hcd_giveback_urb(ifxhcd_to_syshcd(_ifxhcd), urb); -+ usb_hcd_giveback_urb(ifxhcd_to_syshcd(_ifxhcd), urb, _status); -+ -+ /*== AVM/BC 20100630 - 2.6.28 needs HCD link/unlink URBs ==*/ -+ SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags); -+} -+ -+/*== AVM/BC 20101111 URB Complete deferred -+ * Must be called with Spinlock -+ */ -+ -+/*! -+ \brief Inserts an urbd structur in the completion list. The urbd will be -+ later completed by select_eps_sub -+ */ -+void defer_ifxhcd_complete_urb(ifxhcd_hcd_t *_ifxhcd, ifxhcd_urbd_t *_urbd, int _status) -+{ -+ -+ _urbd->status = _status; -+ -+ //Unlink Urbd from epqh / Insert it into the complete list -+ list_move_tail(&_urbd->urbd_list_entry, &_ifxhcd->urbd_complete_list); -+ -+} -+ -+/*! -+ \brief Processes all the URBs in a single EPQHs. Completes them with -+ status and frees the URBD. -+ */ -+//static -+void kill_all_urbs_in_epqh(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh, int _status) -+{ -+ struct list_head *urbd_item; -+ ifxhcd_urbd_t *urbd; -+ -+ if(!_epqh) -+ return; -+ -+ for (urbd_item = _epqh->urbd_list.next; -+ urbd_item != &_epqh->urbd_list; -+ urbd_item = _epqh->urbd_list.next) -+ { -+ urbd = list_entry(urbd_item, ifxhcd_urbd_t, urbd_list_entry); -+ ifxhcd_complete_urb(_ifxhcd, urbd, _status); -+ } -+} -+ -+ -+/*! -+ \brief Free all EPS in one Processes all the URBs in a single list of EPQHs. Completes them with -+ -ETIMEDOUT and frees the URBD. -+ */ -+//static -+void epqh_list_free(ifxhcd_hcd_t *_ifxhcd, struct list_head *_epqh_list) -+{ -+ struct list_head *item; -+ ifxhcd_epqh_t *epqh; -+ -+ if (!_epqh_list) -+ return; -+ if (_epqh_list->next == NULL) /* The list hasn't been initialized yet. */ -+ return; -+ -+ /* Ensure there are no URBDs or URBs left. */ -+ for (item = _epqh_list->next; item != _epqh_list; item = _epqh_list->next) -+ { -+ epqh = list_entry(item, ifxhcd_epqh_t, epqh_list_entry); -+ kill_all_urbs_in_epqh(_ifxhcd, epqh, -ETIMEDOUT); -+ ifxhcd_epqh_free(epqh); -+ } -+} -+ -+ -+ -+//static -+void epqh_list_free_all(ifxhcd_hcd_t *_ifxhcd) -+{ -+ unsigned long flags; -+ -+ /*== AVM/BC 20101111 - 2.6.28 Needs Spinlock ==*/ -+ SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags); -+ -+ epqh_list_free(_ifxhcd, &_ifxhcd->epqh_np_active ); -+ epqh_list_free(_ifxhcd, &_ifxhcd->epqh_np_ready ); -+ epqh_list_free(_ifxhcd, &_ifxhcd->epqh_intr_active ); -+ epqh_list_free(_ifxhcd, &_ifxhcd->epqh_intr_ready ); -+ #ifdef __EN_ISOC__ -+ epqh_list_free(_ifxhcd, &_ifxhcd->epqh_isoc_active ); -+ epqh_list_free(_ifxhcd, &_ifxhcd->epqh_isoc_ready ); -+ #endif -+ epqh_list_free(_ifxhcd, &_ifxhcd->epqh_stdby ); -+ -+ SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); -+ -+} -+ -+ -+/*! -+ \brief This function is called to handle the disconnection of host port. -+ */ -+int32_t ifxhcd_disconnect(ifxhcd_hcd_t *_ifxhcd) -+{ -+ IFX_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _ifxhcd); -+ -+ /* Set status flags for the hub driver. */ -+ _ifxhcd->flags.b.port_connect_status_change = 1; -+ _ifxhcd->flags.b.port_connect_status = 0; -+ -+ /* -+ * Shutdown any transfers in process by clearing the Tx FIFO Empty -+ * interrupt mask and status bits and disabling subsequent host -+ * channel interrupts. -+ */ -+ { -+ gint_data_t intr = { .d32 = 0 }; -+ intr.b.nptxfempty = 1; -+ intr.b.ptxfempty = 1; -+ intr.b.hcintr = 1; -+ ifxusb_mreg (&_ifxhcd->core_if.core_global_regs->gintmsk, intr.d32, 0); -+ ifxusb_mreg (&_ifxhcd->core_if.core_global_regs->gintsts, intr.d32, 0); -+ } -+ -+ /* Respond with an error status to all URBs in the schedule. */ -+ epqh_list_free_all(_ifxhcd); -+ -+ /* Clean up any host channels that were in use. */ -+ { -+ int num_channels; -+ ifxhcd_hc_t *channel; -+ ifxusb_hc_regs_t *hc_regs; -+ hcchar_data_t hcchar; -+ int i; -+ -+ num_channels = _ifxhcd->core_if.params.host_channels; -+ -+ for (i = 0; i < num_channels; i++) -+ { -+ channel = &_ifxhcd->ifxhc[i]; -+ if (list_empty(&channel->hc_list_entry)) -+ { -+ hc_regs = _ifxhcd->core_if.hc_regs[i]; -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ if (hcchar.b.chen) -+ { -+ /* Halt the channel. */ -+ hcchar.b.chdis = 1; -+ ifxusb_wreg(&hc_regs->hcchar, hcchar.d32); -+ } -+ list_add_tail(&channel->hc_list_entry, &_ifxhcd->free_hc_list); -+ ifxhcd_hc_cleanup(&_ifxhcd->core_if, channel); -+ } -+ } -+ } -+ return 1; -+} -+ -+ -+/*! -+ \brief Frees secondary storage associated with the ifxhcd_hcd structure contained -+ in the struct usb_hcd field. -+ */ -+static void ifxhcd_freeextra(struct usb_hcd *_syshcd) -+{ -+ ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd(_syshcd); -+ -+ IFX_DEBUGPL(DBG_HCD, "IFXUSB HCD FREE\n"); -+ -+ /* Free memory for EPQH/URBD lists */ -+ epqh_list_free_all(ifxhcd); -+ -+ /* Free memory for the host channels. */ -+ ifxusb_free_buf(ifxhcd->status_buf); -+ return; -+} -+#ifdef __USE_TIMER_4_SOF__ -+static enum hrtimer_restart ifxhcd_timer_func(struct hrtimer *timer) { -+ ifxhcd_hcd_t *ifxhcd = container_of(timer, ifxhcd_hcd_t, hr_timer); -+ -+ ifxhcd_handle_intr(ifxhcd); -+ -+ return HRTIMER_NORESTART; -+} -+#endif -+ -+/*! -+ \brief Initializes the HCD. This function allocates memory for and initializes the -+ static parts of the usb_hcd and ifxhcd_hcd structures. It also registers the -+ USB bus with the core and calls the hc_driver->start() function. It returns -+ a negative error on failure. -+ */ -+int ifxhcd_init(ifxhcd_hcd_t *_ifxhcd) -+{ -+ int retval = 0; -+ struct usb_hcd *syshcd = NULL; -+ -+ IFX_DEBUGPL(DBG_HCD, "IFX USB HCD INIT\n"); -+ -+ spin_lock_init(&_ifxhcd->lock); -+#ifdef __USE_TIMER_4_SOF__ -+ hrtimer_init(&_ifxhcd->hr_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); -+ _ifxhcd->hr_timer.function = ifxhcd_timer_func; -+#endif -+ _ifxhcd->hc_driver.description = _ifxhcd->core_if.core_name; -+ _ifxhcd->hc_driver.product_desc = "IFX USB Controller"; -+ //_ifxhcd->hc_driver.hcd_priv_size = sizeof(ifxhcd_hcd_t); -+ _ifxhcd->hc_driver.hcd_priv_size = sizeof(unsigned long); -+ _ifxhcd->hc_driver.irq = ifxhcd_irq; -+ _ifxhcd->hc_driver.flags = HCD_MEMORY | HCD_USB2; -+ _ifxhcd->hc_driver.start = ifxhcd_start; -+ _ifxhcd->hc_driver.stop = ifxhcd_stop; -+ //_ifxhcd->hc_driver.reset = -+ //_ifxhcd->hc_driver.suspend = -+ //_ifxhcd->hc_driver.resume = -+ _ifxhcd->hc_driver.urb_enqueue = ifxhcd_urb_enqueue; -+ _ifxhcd->hc_driver.urb_dequeue = ifxhcd_urb_dequeue; -+ _ifxhcd->hc_driver.endpoint_disable = ifxhcd_endpoint_disable; -+ _ifxhcd->hc_driver.get_frame_number = ifxhcd_get_frame_number; -+ _ifxhcd->hc_driver.hub_status_data = ifxhcd_hub_status_data; -+ _ifxhcd->hc_driver.hub_control = ifxhcd_hub_control; -+ //_ifxhcd->hc_driver.hub_suspend = -+ //_ifxhcd->hc_driver.hub_resume = -+ -+ /* Allocate memory for and initialize the base HCD and */ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) -+ syshcd = usb_create_hcd(&_ifxhcd->hc_driver, _ifxhcd->dev, _ifxhcd->core_if.core_name); -+#else -+ syshcd = usb_create_hcd(&_ifxhcd->hc_driver, _ifxhcd->dev, _ifxhcd->dev->bus_id); -+#endif -+ -+ if (syshcd == NULL) -+ { -+ retval = -ENOMEM; -+ goto error1; -+ } -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) -+ syshcd->has_tt = 1; -+#endif -+ -+ syshcd->rsrc_start = (unsigned long)_ifxhcd->core_if.core_global_regs; -+ syshcd->regs = (void *)_ifxhcd->core_if.core_global_regs; -+ syshcd->self.otg_port = 0; -+ -+ //*((unsigned long *)(&(syshcd->hcd_priv)))=(unsigned long)_ifxhcd; -+ //*((unsigned long *)(&(syshcd->hcd_priv[0])))=(unsigned long)_ifxhcd; -+ syshcd->hcd_priv[0]=(unsigned long)_ifxhcd; -+ _ifxhcd->syshcd=syshcd; -+ -+ INIT_LIST_HEAD(&_ifxhcd->epqh_np_active ); -+ INIT_LIST_HEAD(&_ifxhcd->epqh_np_ready ); -+ INIT_LIST_HEAD(&_ifxhcd->epqh_intr_active ); -+ INIT_LIST_HEAD(&_ifxhcd->epqh_intr_ready ); -+ #ifdef __EN_ISOC__ -+ INIT_LIST_HEAD(&_ifxhcd->epqh_isoc_active ); -+ INIT_LIST_HEAD(&_ifxhcd->epqh_isoc_ready ); -+ #endif -+ INIT_LIST_HEAD(&_ifxhcd->epqh_stdby ); -+ INIT_LIST_HEAD(&_ifxhcd->urbd_complete_list); -+ -+ /* -+ * Create a host channel descriptor for each host channel implemented -+ * in the controller. Initialize the channel descriptor array. -+ */ -+ INIT_LIST_HEAD(&_ifxhcd->free_hc_list); -+ { -+ int num_channels = _ifxhcd->core_if.params.host_channels; -+ int i; -+ for (i = 0; i < num_channels; i++) -+ { -+ _ifxhcd->ifxhc[i].hc_num = i; -+ IFX_DEBUGPL(DBG_HCDV, "HCD Added channel #%d\n", i); -+ } -+ } -+ -+ /* Set device flags indicating whether the HCD supports DMA. */ -+ if(_ifxhcd->dev->dma_mask) -+ *(_ifxhcd->dev->dma_mask) = ~0; -+ _ifxhcd->dev->coherent_dma_mask = ~0; -+ -+ /* -+ * Finish generic HCD initialization and start the HCD. This function -+ * allocates the DMA buffer pool, registers the USB bus, requests the -+ * IRQ line, and calls ifxusb_hcd_start method. -+ */ -+// retval = usb_add_hcd(syshcd, _ifxhcd->core_if.irq, SA_INTERRUPT|SA_SHIRQ); -+ retval = usb_add_hcd(syshcd, _ifxhcd->core_if.irq, IRQF_DISABLED | IRQF_SHARED ); -+ if (retval < 0) -+ goto error2; -+ -+ /* -+ * Allocate space for storing data on status transactions. Normally no -+ * data is sent, but this space acts as a bit bucket. This must be -+ * done after usb_add_hcd since that function allocates the DMA buffer -+ * pool. -+ */ -+ _ifxhcd->status_buf = ifxusb_alloc_buf(IFXHCD_STATUS_BUF_SIZE, 1); -+ -+ if (_ifxhcd->status_buf) -+ { -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) -+ IFX_DEBUGPL(DBG_HCD, "IFX USB HCD Initialized, bus=%s, usbbus=%d\n", _ifxhcd->core_if.core_name, syshcd->self.busnum); -+#else -+ IFX_DEBUGPL(DBG_HCD, "IFX USB HCD Initialized, bus=%s, usbbus=%d\n", _ifxhcd->dev->bus_id, syshcd->self.busnum); -+#endif -+ return 0; -+ } -+ IFX_ERROR("%s: status_buf allocation failed\n", __func__); -+ -+ /* Error conditions */ -+ usb_remove_hcd(syshcd); -+error2: -+ ifxhcd_freeextra(syshcd); -+ usb_put_hcd(syshcd); -+error1: -+ return retval; -+} -+ -+/*! -+ \brief Removes the HCD. -+ Frees memory and resources associated with the HCD and deregisters the bus. -+ */ -+void ifxhcd_remove(ifxhcd_hcd_t *_ifxhcd) -+{ -+ struct usb_hcd *syshcd = ifxhcd_to_syshcd(_ifxhcd); -+ -+ IFX_DEBUGPL(DBG_HCD, "IFX USB HCD REMOVE\n"); -+ -+/* == AVM/WK 20100709 - Fix: Order changed, disable IRQs not before remove_hcd == */ -+ -+ usb_remove_hcd(syshcd); -+ -+ /* Turn off all interrupts */ -+ ifxusb_wreg (&_ifxhcd->core_if.core_global_regs->gintmsk, 0); -+ ifxusb_mreg (&_ifxhcd->core_if.core_global_regs->gahbcfg, 1, 0); -+ -+ ifxhcd_freeextra(syshcd); -+ -+ usb_put_hcd(syshcd); -+ -+ return; -+} -+ -+ -+/* ========================================================================= -+ * Linux HC Driver Functions -+ * ========================================================================= */ -+ -+/*! -+ \brief Initializes the IFXUSB controller and its root hub and prepares it for host -+ mode operation. Activates the root port. Returns 0 on success and a negative -+ error code on failure. -+ Called by USB stack. -+ */ -+int ifxhcd_start(struct usb_hcd *_syshcd) -+{ -+ ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd (_syshcd); -+ ifxusb_core_if_t *core_if = &ifxhcd->core_if; -+ struct usb_bus *bus; -+ -+ IFX_DEBUGPL(DBG_HCD, "IFX USB HCD START\n"); -+ -+ bus = hcd_to_bus(_syshcd); -+ -+ /* Initialize the bus state. */ -+ _syshcd->state = HC_STATE_RUNNING; -+ -+ /* Initialize and connect root hub if one is not already attached */ -+ if (bus->root_hub) -+ { -+ IFX_DEBUGPL(DBG_HCD, "IFX USB HCD Has Root Hub\n"); -+ /* Inform the HUB driver to resume. */ -+ usb_hcd_resume_root_hub(_syshcd); -+ } -+ -+ ifxhcd->flags.d32 = 0; -+ -+ /* Put all channels in the free channel list and clean up channel states.*/ -+ { -+ struct list_head *item; -+ item = ifxhcd->free_hc_list.next; -+ while (item != &ifxhcd->free_hc_list) -+ { -+ list_del(item); -+ item = ifxhcd->free_hc_list.next; -+ } -+ } -+ { -+ int num_channels = ifxhcd->core_if.params.host_channels; -+ int i; -+ for (i = 0; i < num_channels; i++) -+ { -+ ifxhcd_hc_t *channel; -+ channel = &ifxhcd->ifxhc[i]; -+ list_add_tail(&channel->hc_list_entry, &ifxhcd->free_hc_list); -+ ifxhcd_hc_cleanup(&ifxhcd->core_if, channel); -+ } -+ } -+ /* Initialize the USB core for host mode operation. */ -+ -+ ifxusb_host_enable_interrupts(core_if); -+ ifxusb_enable_global_interrupts(core_if); -+ ifxusb_phy_power_on (core_if); -+ -+ ifxusb_vbus_init(core_if); -+ -+ /* Turn on the vbus power. */ -+ { -+ hprt0_data_t hprt0; -+ hprt0.d32 = ifxusb_read_hprt0(core_if); -+ -+ IFX_PRINT("Init: Power Port (%d)\n", hprt0.b.prtpwr); -+ if (hprt0.b.prtpwr == 0 ) -+ { -+ hprt0.b.prtpwr = 1; -+ ifxusb_wreg(core_if->hprt0, hprt0.d32); -+ ifxusb_vbus_on(core_if); -+ } -+ } -+ return 0; -+} -+ -+ -+/*! -+ \brief Halts the IFXUSB host mode operations in a clean manner. USB transfers are -+ stopped. -+ */ -+void ifxhcd_stop(struct usb_hcd *_syshcd) -+{ -+ ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd(_syshcd); -+ hprt0_data_t hprt0 = { .d32=0 }; -+ -+ IFX_DEBUGPL(DBG_HCD, "IFX USB HCD STOP\n"); -+ -+ /* Turn off all interrupts. */ -+ ifxusb_disable_global_interrupts(&ifxhcd->core_if ); -+ ifxusb_host_disable_interrupts(&ifxhcd->core_if ); -+#ifdef __USE_TIMER_4_SOF__ -+ hrtimer_cancel(&ifxhcd->hr_timer); -+#endif -+ /* -+ * The root hub should be disconnected before this function is called. -+ * The disconnect will clear the URBD lists (via ..._hcd_urb_dequeue) -+ * and the EPQH lists (via ..._hcd_endpoint_disable). -+ */ -+ -+ /* Turn off the vbus power */ -+ IFX_PRINT("PortPower off\n"); -+ -+ ifxusb_vbus_off(&ifxhcd->core_if ); -+ -+ ifxusb_vbus_free(&ifxhcd->core_if ); -+ -+ hprt0.b.prtpwr = 0; -+ ifxusb_wreg(ifxhcd->core_if.hprt0, hprt0.d32); -+ return; -+} -+ -+/*! -+ \brief Returns the current frame number -+ */ -+int ifxhcd_get_frame_number(struct usb_hcd *_syshcd) -+{ -+ ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd(_syshcd); -+ hfnum_data_t hfnum; -+ -+ hfnum.d32 = ifxusb_rreg(&ifxhcd->core_if.host_global_regs->hfnum); -+ -+ return hfnum.b.frnum; -+} -+ -+/*! -+ \brief Starts processing a USB transfer request specified by a USB Request Block -+ (URB). mem_flags indicates the type of memory allocation to use while -+ processing this URB. -+ */ -+int ifxhcd_urb_enqueue( struct usb_hcd *_syshcd, -+ /*--- struct usb_host_endpoint *_sysep, Parameter im 2.6.28 entfallen ---*/ -+ struct urb *_urb, -+ gfp_t _mem_flags) -+{ -+ int retval = 0; -+ ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd (_syshcd); -+ struct usb_host_endpoint *_sysep = ifxhcd_urb_to_endpoint(_urb); -+ ifxhcd_epqh_t *epqh; -+ -+ #ifdef __DEBUG__ -+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) -+ dump_urb_info(_urb, "ifxusb_hcd_urb_enqueue"); -+ #endif //__DEBUG__ -+ -+ if (!ifxhcd->flags.b.port_connect_status) /* No longer connected. */ -+ return -ENODEV; -+ -+ #ifndef __EN_ISOC__ -+ if(usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) -+ { -+ IFX_ERROR("ISOC transfer not supported!!!\n"); -+ return -ENODEV; -+ } -+ #endif -+ -+ retval=ifxhcd_urbd_create (ifxhcd,_urb); -+ -+ if (retval) -+ { -+ IFX_ERROR("IFXUSB HCD URB Enqueue failed creating URBD\n"); -+ return retval; -+ } -+ epqh = (ifxhcd_epqh_t *) _sysep->hcpriv; -+ ifxhcd_epqh_ready(ifxhcd, epqh); -+ -+ select_eps(ifxhcd); -+ //enable_sof(ifxhcd); -+ { -+ gint_data_t gintsts; -+ gintsts.d32=0; -+ gintsts.b.sofintr = 1; -+ ifxusb_mreg(&ifxhcd->core_if.core_global_regs->gintmsk, 0,gintsts.d32); -+ } -+ -+ return retval; -+} -+ -+/*! -+ \brief Aborts/cancels a USB transfer request. Always returns 0 to indicate -+ success. -+ */ -+int ifxhcd_urb_dequeue( struct usb_hcd *_syshcd, -+ struct urb *_urb, int status /* Parameter neu in 2.6.28 */) -+{ -+ unsigned long flags; -+ ifxhcd_hcd_t *ifxhcd; -+ ifxhcd_urbd_t *urbd; -+ ifxhcd_epqh_t *epqh; -+ int is_active=0; -+ int rc; -+ -+ struct usb_host_endpoint *_sysep; -+ -+ IFX_DEBUGPL(DBG_HCD, "IFXUSB HCD URB Dequeue\n"); -+ -+ #ifndef __EN_ISOC__ -+ if(usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) -+ return 0; -+ #endif -+ -+ _sysep = ifxhcd_urb_to_endpoint(_urb); -+ -+ ifxhcd = syshcd_to_ifxhcd(_syshcd); -+ -+ SPIN_LOCK_IRQSAVE(&ifxhcd->lock, flags); -+ -+ /*== AVM/BC 20100630 - 2.6.28 needs HCD link/unlink URBs ==*/ -+ rc = usb_hcd_check_unlink_urb(_syshcd, _urb, status); -+ if (rc) { -+ SPIN_UNLOCK_IRQRESTORE(&ifxhcd->lock, flags); -+ return rc; -+ } -+ -+ urbd = (ifxhcd_urbd_t *) _urb->hcpriv; -+ -+ if(_sysep) -+ epqh = (ifxhcd_epqh_t *) _sysep->hcpriv; -+ else -+ epqh = (ifxhcd_epqh_t *) urbd->epqh; -+ -+ if(epqh!=urbd->epqh) -+ IFX_ERROR("%s inconsistant epqh %p %p\n",__func__,epqh,urbd->epqh); -+ -+ #ifdef __DEBUG__ -+ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) -+ { -+ dump_urb_info(_urb, "ifxhcd_urb_dequeue"); -+ if (epqh->is_active) -+ dump_channel_info(ifxhcd, epqh); -+ } -+ #endif //__DEBUG__ -+ -+ if(!epqh->hc) -+ epqh->is_active=0; -+ else if (!ifxhcd->flags.b.port_connect_status) -+ epqh->is_active=0; -+ else if (epqh->is_active && urbd->is_active) -+ { -+ /*== AVM/WK 20100709 - halt channel only if really started ==*/ -+ //if (epqh->hc->xfer_started && !epqh->hc->wait_for_sof) { -+ /*== AVM/WK 20101112 - halt channel if started ==*/ -+ if (epqh->hc->xfer_started) { -+ /* -+ * If still connected (i.e. in host mode), halt the -+ * channel so it can be used for other transfers. If -+ * no longer connected, the host registers can't be -+ * written to halt the channel since the core is in -+ * device mode. -+ */ -+ /* == 20110803 AVM/WK FIX propagate status == */ -+ if (_urb->status == -EINPROGRESS) { -+ _urb->status = status; -+ } -+ ifxhcd_hc_halt(&ifxhcd->core_if, epqh->hc, HC_XFER_URB_DEQUEUE); -+ epqh->hc = NULL; -+ is_active=1; -+ } -+ } -+ -+ if(is_active) -+ { -+ SPIN_UNLOCK_IRQRESTORE(&ifxhcd->lock, flags); -+ } -+ else -+ { -+ list_del_init(&urbd->urbd_list_entry); -+ kfree (urbd); -+ -+ /*== AVM/BC 20100630 - 2.6.28 needs HCD link/unlink URBs ==*/ -+ usb_hcd_unlink_urb_from_ep(_syshcd, _urb); -+ -+ SPIN_UNLOCK_IRQRESTORE(&ifxhcd->lock, flags); -+ _urb->hcpriv = NULL; -+// usb_hcd_giveback_urb(_syshcd, _urb); -+ usb_hcd_giveback_urb(_syshcd, _urb, status /* neu in 2.6.28 */); -+ select_eps(ifxhcd); -+ } -+ -+ return 0; -+} -+ -+ -+ -+/*! -+ \brief Frees resources in the IFXUSB controller related to a given endpoint. Also -+ clears state in the HCD related to the endpoint. Any URBs for the endpoint -+ must already be dequeued. -+ */ -+void ifxhcd_endpoint_disable( struct usb_hcd *_syshcd, -+ struct usb_host_endpoint *_sysep) -+{ -+ ifxhcd_epqh_t *epqh; -+ ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd(_syshcd); -+ unsigned long flags; -+ -+ int retry = 0; -+ -+ IFX_DEBUGPL(DBG_HCD, "IFXUSB HCD EP DISABLE: _bEndpointAddress=0x%02x, " -+ "endpoint=%d\n", _sysep->desc.bEndpointAddress, -+ ifxhcd_ep_addr_to_endpoint(_sysep->desc.bEndpointAddress)); -+ -+ SPIN_LOCK_IRQSAVE(&ifxhcd->lock, flags); -+ if((uint32_t)_sysep>=0x80000000 && (uint32_t)_sysep->hcpriv>=(uint32_t)0x80000000) -+ { -+ epqh = (ifxhcd_epqh_t *)(_sysep->hcpriv); -+ if (epqh && epqh->sysep==_sysep) -+ { -+ -+#if 1 /*== AVM/BC 20101111 CHG Option active: Kill URBs when disabling EP ==*/ -+ while (!list_empty(&epqh->urbd_list)) -+ { -+ if (retry++ > 250) -+ { -+ IFX_WARN("IFXUSB HCD EP DISABLE:" -+ " URBD List for this endpoint is not empty\n"); -+ break; -+ } -+ kill_all_urbs_in_epqh(ifxhcd, epqh, -ETIMEDOUT); -+ } -+#else -+ while (!list_empty(&epqh->urbd_list)) -+ { -+ /** Check that the QTD list is really empty */ -+ if (retry++ > 250) -+ { -+ IFX_WARN("IFXUSB HCD EP DISABLE:" -+ " URBD List for this endpoint is not empty\n"); -+ break; -+ } -+ SPIN_UNLOCK_IRQRESTORE(&ifxhcd->lock, flags); -+ schedule_timeout_uninterruptible(1); -+ SPIN_LOCK_IRQSAVE(&ifxhcd->lock, flags); -+ } -+#endif -+ -+ ifxhcd_epqh_free(epqh); -+ _sysep->hcpriv = NULL; -+ } -+ } -+ SPIN_UNLOCK_IRQRESTORE(&ifxhcd->lock, flags); -+} -+ -+ -+/*! -+ \brief Handles host mode interrupts for the IFXUSB controller. Returns IRQ_NONE if -+ * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid -+ * interrupt. -+ * -+ * This function is called by the USB core when an interrupt occurs -+ */ -+irqreturn_t ifxhcd_irq(struct usb_hcd *_syshcd) -+{ -+ ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd (_syshcd); -+ int32_t retval=0; -+ -+ //mask_and_ack_ifx_irq (ifxhcd->core_if.irq); -+ retval = ifxhcd_handle_intr(ifxhcd); -+ return IRQ_RETVAL(retval); -+} -+ -+ -+/*! -+ \brief Handles host mode Over Current Interrupt -+ */ -+irqreturn_t ifxhcd_oc_irq(int _irq , void *_dev) -+{ -+ ifxhcd_hcd_t *ifxhcd = _dev; -+ int32_t retval=1; -+ -+ ifxhcd->flags.b.port_over_current_change = 1; -+ ifxusb_vbus_off(&ifxhcd->core_if); -+ IFX_DEBUGP("OC INTERRUPT # %d\n",ifxhcd->core_if.core_no); -+ -+ //mask_and_ack_ifx_irq (_irq); -+ return IRQ_RETVAL(retval); -+} -+ -+/*! -+ \brief Creates Status Change bitmap for the root hub and root port. The bitmap is -+ returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 -+ is the status change indicator for the single root port. Returns 1 if either -+ change indicator is 1, otherwise returns 0. -+ */ -+int ifxhcd_hub_status_data(struct usb_hcd *_syshcd, char *_buf) -+{ -+ ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd (_syshcd); -+ -+ _buf[0] = 0; -+ _buf[0] |= (ifxhcd->flags.b.port_connect_status_change || -+ ifxhcd->flags.b.port_reset_change || -+ ifxhcd->flags.b.port_enable_change || -+ ifxhcd->flags.b.port_suspend_change || -+ ifxhcd->flags.b.port_over_current_change) << 1; -+ -+ #ifdef __DEBUG__ -+ if (_buf[0]) -+ { -+ IFX_DEBUGPL(DBG_HCD, "IFXUSB HCD HUB STATUS DATA:" -+ " Root port status changed\n"); -+ IFX_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n", -+ ifxhcd->flags.b.port_connect_status_change); -+ IFX_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n", -+ ifxhcd->flags.b.port_reset_change); -+ IFX_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n", -+ ifxhcd->flags.b.port_enable_change); -+ IFX_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n", -+ ifxhcd->flags.b.port_suspend_change); -+ IFX_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n", -+ ifxhcd->flags.b.port_over_current_change); -+ } -+ #endif //__DEBUG__ -+ return (_buf[0] != 0); -+} -+ -+#ifdef __WITH_HS_ELECT_TST__ -+ extern void do_setup(ifxusb_core_if_t *_core_if) ; -+ extern void do_in_ack(ifxusb_core_if_t *_core_if); -+#endif //__WITH_HS_ELECT_TST__ -+ -+/*! -+ \brief Handles hub class-specific requests. -+ */ -+int ifxhcd_hub_control( struct usb_hcd *_syshcd, -+ u16 _typeReq, -+ u16 _wValue, -+ u16 _wIndex, -+ char *_buf, -+ u16 _wLength) -+{ -+ int retval = 0; -+ -+ ifxhcd_hcd_t *ifxhcd = syshcd_to_ifxhcd (_syshcd); -+ ifxusb_core_if_t *core_if = &ifxhcd->core_if; -+ struct usb_hub_descriptor *desc; -+ hprt0_data_t hprt0 = {.d32 = 0}; -+ -+ uint32_t port_status; -+ -+ switch (_typeReq) -+ { -+ case ClearHubFeature: -+ IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " -+ "ClearHubFeature 0x%x\n", _wValue); -+ switch (_wValue) -+ { -+ case C_HUB_LOCAL_POWER: -+ case C_HUB_OVER_CURRENT: -+ /* Nothing required here */ -+ break; -+ default: -+ retval = -EINVAL; -+ IFX_ERROR ("IFXUSB HCD - " -+ "ClearHubFeature request %xh unknown\n", _wValue); -+ } -+ break; -+ case ClearPortFeature: -+ if (!_wIndex || _wIndex > 1) -+ goto error; -+ -+ switch (_wValue) -+ { -+ case USB_PORT_FEAT_ENABLE: -+ IFX_DEBUGPL (DBG_ANY, "IFXUSB HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); -+ hprt0.d32 = ifxusb_read_hprt0 (core_if); -+ hprt0.b.prtena = 1; -+ ifxusb_wreg(core_if->hprt0, hprt0.d32); -+ break; -+ case USB_PORT_FEAT_SUSPEND: -+ IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); -+ hprt0.d32 = ifxusb_read_hprt0 (core_if); -+ hprt0.b.prtres = 1; -+ ifxusb_wreg(core_if->hprt0, hprt0.d32); -+ /* Clear Resume bit */ -+ mdelay (100); -+ hprt0.b.prtres = 0; -+ ifxusb_wreg(core_if->hprt0, hprt0.d32); -+ break; -+ case USB_PORT_FEAT_POWER: -+ IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_POWER\n"); -+ #ifdef __IS_DUAL__ -+ ifxusb_vbus_off(core_if); -+ #else -+ ifxusb_vbus_off(core_if); -+ #endif -+ hprt0.d32 = ifxusb_read_hprt0 (core_if); -+ hprt0.b.prtpwr = 0; -+ ifxusb_wreg(core_if->hprt0, hprt0.d32); -+ break; -+ case USB_PORT_FEAT_INDICATOR: -+ IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); -+ /* Port inidicator not supported */ -+ break; -+ case USB_PORT_FEAT_C_CONNECTION: -+ /* Clears drivers internal connect status change -+ * flag */ -+ IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); -+ ifxhcd->flags.b.port_connect_status_change = 0; -+ break; -+ case USB_PORT_FEAT_C_RESET: -+ /* Clears the driver's internal Port Reset Change -+ * flag */ -+ IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); -+ ifxhcd->flags.b.port_reset_change = 0; -+ break; -+ case USB_PORT_FEAT_C_ENABLE: -+ /* Clears the driver's internal Port -+ * Enable/Disable Change flag */ -+ IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); -+ ifxhcd->flags.b.port_enable_change = 0; -+ break; -+ case USB_PORT_FEAT_C_SUSPEND: -+ /* Clears the driver's internal Port Suspend -+ * Change flag, which is set when resume signaling on -+ * the host port is complete */ -+ IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); -+ ifxhcd->flags.b.port_suspend_change = 0; -+ break; -+ case USB_PORT_FEAT_C_OVER_CURRENT: -+ IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " -+ "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); -+ ifxhcd->flags.b.port_over_current_change = 0; -+ break; -+ default: -+ retval = -EINVAL; -+ IFX_ERROR ("IFXUSB HCD - " -+ "ClearPortFeature request %xh " -+ "unknown or unsupported\n", _wValue); -+ } -+ break; -+ case GetHubDescriptor: -+ IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " -+ "GetHubDescriptor\n"); -+ desc = (struct usb_hub_descriptor *)_buf; -+ desc->bDescLength = 9; -+ desc->bDescriptorType = 0x29; -+ desc->bNbrPorts = 1; -+ desc->wHubCharacteristics = 0x08; -+ desc->bPwrOn2PwrGood = 1; -+ desc->bHubContrCurrent = 0; -+// desc->bitmap[0] = 0; -+// desc->bitmap[1] = 0xff; -+ break; -+ case GetHubStatus: -+ IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " -+ "GetHubStatus\n"); -+ memset (_buf, 0, 4); -+ break; -+ case GetPortStatus: -+ IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " -+ "GetPortStatus\n"); -+ if (!_wIndex || _wIndex > 1) -+ goto error; -+ -+# ifdef CONFIG_AVM_POWERMETER -+ { -+ /* first port only, but 2 Hosts */ -+ static unsigned char ucOldPower1 = 255; -+ static unsigned char ucOldPower2 = 255; -+ -+ unsigned char ucNewPower = 0; -+ struct usb_device *childdev = _syshcd->self.root_hub->children[0]; -+ -+ if (childdev != NULL) { -+ ucNewPower = (childdev->actconfig != NULL) -+ ? childdev->actconfig->desc.bMaxPower -+ : 50;/* default: 50 means 100 mA*/ -+ } -+ if (_syshcd->self.busnum == 1) { -+ if (ucOldPower1 != ucNewPower) { -+ ucOldPower1 = ucNewPower; -+ printk (KERN_INFO "IFXHCD#1: AVM Powermeter changed to %u mA\n", ucNewPower*2); -+ PowerManagmentRessourceInfo(powerdevice_usb_host, ucNewPower*2); -+ } -+ } else { -+ if (ucOldPower2 != ucNewPower) { -+ ucOldPower2 = ucNewPower; -+ printk (KERN_INFO "IFXHCD#2: AVM Powermeter changed to %u mA\n", ucNewPower*2); -+ PowerManagmentRessourceInfo(powerdevice_usb_host2, ucNewPower*2); -+ } -+ } -+ } -+# endif /*--- #ifdef CONFIG_AVM_POWERMETER ---*/ -+ -+ port_status = 0; -+ if (ifxhcd->flags.b.port_connect_status_change) -+ port_status |= (1 << USB_PORT_FEAT_C_CONNECTION); -+ if (ifxhcd->flags.b.port_enable_change) -+ port_status |= (1 << USB_PORT_FEAT_C_ENABLE); -+ if (ifxhcd->flags.b.port_suspend_change) -+ port_status |= (1 << USB_PORT_FEAT_C_SUSPEND); -+ if (ifxhcd->flags.b.port_reset_change) -+ port_status |= (1 << USB_PORT_FEAT_C_RESET); -+ if (ifxhcd->flags.b.port_over_current_change) -+ { -+ IFX_ERROR("Device Not Supported\n"); -+ port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT); -+ } -+ if (!ifxhcd->flags.b.port_connect_status) -+ { -+ /* -+ * The port is disconnected, which means the core is -+ * either in device mode or it soon will be. Just -+ * return 0's for the remainder of the port status -+ * since the port register can't be read if the core -+ * is in device mode. -+ */ -+ *((u32 *) _buf) = cpu_to_le32(port_status); -+ break; -+ } -+ -+ hprt0.d32 = ifxusb_rreg(core_if->hprt0); -+ IFX_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32); -+ if (hprt0.b.prtconnsts) -+ port_status |= (1 << USB_PORT_FEAT_CONNECTION); -+ if (hprt0.b.prtena) -+ port_status |= (1 << USB_PORT_FEAT_ENABLE); -+ if (hprt0.b.prtsusp) -+ port_status |= (1 << USB_PORT_FEAT_SUSPEND); -+ if (hprt0.b.prtovrcurract) -+ port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT); -+ if (hprt0.b.prtrst) -+ port_status |= (1 << USB_PORT_FEAT_RESET); -+ if (hprt0.b.prtpwr) -+ port_status |= (1 << USB_PORT_FEAT_POWER); -+/* if (hprt0.b.prtspd == IFXUSB_HPRT0_PRTSPD_HIGH_SPEED) -+ port_status |= (1 << USB_PORT_FEAT_HIGHSPEED); -+ else if (hprt0.b.prtspd == IFXUSB_HPRT0_PRTSPD_LOW_SPEED) -+ port_status |= (1 << USB_PORT_FEAT_LOWSPEED);*/ -+ if (hprt0.b.prttstctl) -+ port_status |= (1 << USB_PORT_FEAT_TEST); -+ /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ -+ *((u32 *) _buf) = cpu_to_le32(port_status); -+ break; -+ case SetHubFeature: -+ IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " -+ "SetHubFeature\n"); -+ /* No HUB features supported */ -+ break; -+ case SetPortFeature: -+ if (_wValue != USB_PORT_FEAT_TEST && (!_wIndex || _wIndex > 1)) -+ goto error; -+ /* -+ * The port is disconnected, which means the core is -+ * either in device mode or it soon will be. Just -+ * return without doing anything since the port -+ * register can't be written if the core is in device -+ * mode. -+ */ -+ if (!ifxhcd->flags.b.port_connect_status) -+ break; -+ switch (_wValue) -+ { -+ case USB_PORT_FEAT_SUSPEND: -+ IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " -+ "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); -+ hprt0.d32 = ifxusb_read_hprt0 (core_if); -+ hprt0.b.prtsusp = 1; -+ ifxusb_wreg(core_if->hprt0, hprt0.d32); -+ //IFX_PRINT( "SUSPEND: HPRT0=%0x\n", hprt0.d32); -+ /* Suspend the Phy Clock */ -+ { -+ pcgcctl_data_t pcgcctl = {.d32=0}; -+ pcgcctl.b.stoppclk = 1; -+ ifxusb_wreg(core_if->pcgcctl, pcgcctl.d32); -+ } -+ break; -+ case USB_PORT_FEAT_POWER: -+ IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " -+ "SetPortFeature - USB_PORT_FEAT_POWER\n"); -+ ifxusb_vbus_on (core_if); -+ hprt0.d32 = ifxusb_read_hprt0 (core_if); -+ hprt0.b.prtpwr = 1; -+ ifxusb_wreg(core_if->hprt0, hprt0.d32); -+ break; -+ case USB_PORT_FEAT_RESET: -+ IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " -+ "SetPortFeature - USB_PORT_FEAT_RESET\n"); -+ hprt0.d32 = ifxusb_read_hprt0 (core_if); -+ hprt0.b.prtrst = 1; -+ ifxusb_wreg(core_if->hprt0, hprt0.d32); -+ /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ -+ MDELAY (60); -+ hprt0.b.prtrst = 0; -+ ifxusb_wreg(core_if->hprt0, hprt0.d32); -+ break; -+ #ifdef __WITH_HS_ELECT_TST__ -+ case USB_PORT_FEAT_TEST: -+ { -+ uint32_t t; -+ gint_data_t gintmsk; -+ t = (_wIndex >> 8); /* MSB wIndex USB */ -+ IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " -+ "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t); -+ warn("USB_PORT_FEAT_TEST %d\n", t); -+ if (t < 6) -+ { -+ hprt0.d32 = ifxusb_read_hprt0 (core_if); -+ hprt0.b.prttstctl = t; -+ ifxusb_wreg(core_if->hprt0, hprt0.d32); -+ } -+ else if (t == 6) /* HS_HOST_PORT_SUSPEND_RESUME */ -+ { -+ /* Save current interrupt mask */ -+ gintmsk.d32 = ifxusb_rreg(&core_if->core_global_regs->gintmsk); -+ -+ /* Disable all interrupts while we muck with -+ * the hardware directly -+ */ -+ ifxusb_wreg(&core_if->core_global_regs->gintmsk, 0); -+ -+ /* 15 second delay per the test spec */ -+ mdelay(15000); -+ -+ /* Drive suspend on the root port */ -+ hprt0.d32 = ifxusb_read_hprt0 (core_if); -+ hprt0.b.prtsusp = 1; -+ hprt0.b.prtres = 0; -+ ifxusb_wreg(core_if->hprt0, hprt0.d32); -+ -+ /* 15 second delay per the test spec */ -+ mdelay(15000); -+ -+ /* Drive resume on the root port */ -+ hprt0.d32 = ifxusb_read_hprt0 (core_if); -+ hprt0.b.prtsusp = 0; -+ hprt0.b.prtres = 1; -+ ifxusb_wreg(core_if->hprt0, hprt0.d32); -+ mdelay(100); -+ -+ /* Clear the resume bit */ -+ hprt0.b.prtres = 0; -+ ifxusb_wreg(core_if->hprt0, hprt0.d32); -+ -+ /* Restore interrupts */ -+ ifxusb_wreg(&core_if->core_global_regs->gintmsk, gintmsk.d32); -+ } -+ else if (t == 7) /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */ -+ { -+ /* Save current interrupt mask */ -+ gintmsk.d32 = ifxusb_rreg(&core_if->core_global_regs->gintmsk); -+ -+ /* Disable all interrupts while we muck with -+ * the hardware directly -+ */ -+ ifxusb_wreg(&core_if->core_global_regs->gintmsk, 0); -+ -+ /* 15 second delay per the test spec */ -+ mdelay(15000); -+ -+ /* Send the Setup packet */ -+ do_setup(core_if); -+ -+ /* 15 second delay so nothing else happens for awhile */ -+ mdelay(15000); -+ -+ /* Restore interrupts */ -+ ifxusb_wreg(&core_if->core_global_regs->gintmsk, gintmsk.d32); -+ } -+ -+ else if (t == 8) /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */ -+ { -+ /* Save current interrupt mask */ -+ gintmsk.d32 = ifxusb_rreg(&core_if->core_global_regs->gintmsk); -+ -+ /* Disable all interrupts while we muck with -+ * the hardware directly -+ */ -+ ifxusb_wreg(&core_if->core_global_regs->gintmsk, 0); -+ -+ /* Send the Setup packet */ -+ do_setup(core_if); -+ -+ /* 15 second delay so nothing else happens for awhile */ -+ mdelay(15000); -+ -+ /* Send the In and Ack packets */ -+ do_in_ack(core_if); -+ -+ /* 15 second delay so nothing else happens for awhile */ -+ mdelay(15000); -+ -+ /* Restore interrupts */ -+ ifxusb_wreg(&core_if->core_global_regs->gintmsk, gintmsk.d32); -+ } -+ } -+ break; -+ #endif //__WITH_HS_ELECT_TST__ -+ case USB_PORT_FEAT_INDICATOR: -+ IFX_DEBUGPL (DBG_HCD, "IFXUSB HCD HUB CONTROL - " -+ "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); -+ /* Not supported */ -+ break; -+ default: -+ retval = -EINVAL; -+ IFX_ERROR ("IFXUSB HCD - " -+ "SetPortFeature request %xh " -+ "unknown or unsupported\n", _wValue); -+ } -+ break; -+ default: -+ error: -+ retval = -EINVAL; -+ IFX_WARN ("IFXUSB HCD - " -+ "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n", -+ _typeReq, _wIndex, _wValue); -+ } -+ return retval; -+} -+ -+ -+/*! -+ \brief Assigns transactions from a URBD to a free host channel and initializes the -+ host channel to perform the transactions. The host channel is removed from -+ the free list. -+ \param _ifxhcd The HCD state structure. -+ \param _epqh Transactions from the first URBD for this EPQH are selected and assigned to a free host channel. -+ */ -+static int assign_and_init_hc(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh) -+{ -+ ifxhcd_hc_t *ifxhc; -+ ifxhcd_urbd_t *urbd; -+ struct urb *urb; -+ -+ IFX_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, _ifxhcd, _epqh); -+ -+ if(list_empty(&_epqh->urbd_list)) -+ return 0; -+ -+ ifxhc = list_entry(_ifxhcd->free_hc_list.next, ifxhcd_hc_t, hc_list_entry); -+ /* Remove the host channel from the free list. */ -+ list_del_init(&ifxhc->hc_list_entry); -+ -+ urbd = list_entry(_epqh->urbd_list.next, ifxhcd_urbd_t, urbd_list_entry); -+ urb = urbd->urb; -+ -+ _epqh->hc = ifxhc; -+ _epqh->urbd = urbd; -+ ifxhc->epqh = _epqh; -+ -+ urbd->is_active=1; -+ -+ /* -+ * Use usb_pipedevice to determine device address. This address is -+ * 0 before the SET_ADDRESS command and the correct address afterward. -+ */ -+ ifxhc->dev_addr = usb_pipedevice(urb->pipe); -+ ifxhc->ep_num = usb_pipeendpoint(urb->pipe); -+ -+ ifxhc->xfer_started = 0; -+ -+ if (urb->dev->speed == USB_SPEED_LOW) ifxhc->speed = IFXUSB_EP_SPEED_LOW; -+ else if (urb->dev->speed == USB_SPEED_FULL) ifxhc->speed = IFXUSB_EP_SPEED_FULL; -+ else ifxhc->speed = IFXUSB_EP_SPEED_HIGH; -+ -+ ifxhc->mps = _epqh->mps; -+ ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; -+ -+ ifxhc->ep_type = _epqh->ep_type; -+ -+ if(_epqh->ep_type==IFXUSB_EP_TYPE_CTRL) -+ { -+ ifxhc->control_phase=IFXHCD_CONTROL_SETUP; -+ ifxhc->is_in = 0; -+ ifxhc->data_pid_start = IFXUSB_HC_PID_SETUP; -+ ifxhc->xfer_buff = urbd->setup_buff; -+ ifxhc->xfer_len = 8; -+ ifxhc->xfer_count = 0; -+ ifxhc->short_rw =(urb->transfer_flags & URB_ZERO_PACKET)?1:0; -+ } -+ else -+ { -+ ifxhc->is_in = urbd->is_in; -+ ifxhc->xfer_buff = urbd->xfer_buff; -+ ifxhc->xfer_len = urbd->xfer_len; -+ ifxhc->xfer_count = 0; -+ /* == AVM/WK 20100710 Fix - Use toggle of usbcore ==*/ -+ //ifxhc->data_pid_start = _epqh->data_toggle; -+ ifxhc->data_pid_start = usb_gettoggle (urb->dev, usb_pipeendpoint(urb->pipe), usb_pipeout (urb->pipe)) -+ ? IFXUSB_HC_PID_DATA1 -+ : IFXUSB_HC_PID_DATA0; -+ if(ifxhc->is_in) -+ ifxhc->short_rw =0; -+ else -+ ifxhc->short_rw =(urb->transfer_flags & URB_ZERO_PACKET)?1:0; -+ -+ #ifdef __EN_ISOC__ -+ if(_epqh->ep_type==IFXUSB_EP_TYPE_ISOC) -+ { -+ struct usb_iso_packet_descriptor *frame_desc; -+ frame_desc = &urb->iso_frame_desc[urbd->isoc_frame_index]; -+ ifxhc->xfer_buff += frame_desc->offset + urbd->isoc_split_offset; -+ ifxhc->xfer_len = frame_desc->length - urbd->isoc_split_offset; -+ if (ifxhc->isoc_xact_pos == IFXUSB_HCSPLIT_XACTPOS_ALL) -+ { -+ if (ifxhc->xfer_len <= 188) -+ ifxhc->isoc_xact_pos = IFXUSB_HCSPLIT_XACTPOS_ALL; -+ else -+ ifxhc->isoc_xact_pos = IFXUSB_HCSPLIT_XACTPOS_BEGIN; -+ } -+ } -+ #endif -+ } -+ -+ ifxhc->do_ping=0; -+ if (_ifxhcd->core_if.snpsid < 0x4f54271a && ifxhc->speed == IFXUSB_EP_SPEED_HIGH) -+ ifxhc->do_ping=1; -+ -+ -+ /* Set the split attributes */ -+ ifxhc->split = 0; -+ if (_epqh->need_split) { -+ ifxhc->split = 1; -+ ifxhc->hub_addr = urb->dev->tt->hub->devnum; -+ ifxhc->port_addr = urb->dev->ttport; -+ } -+ -+ //ifxhc->uint16_t pkt_count_limit -+ -+ { -+ hcint_data_t hc_intr_mask; -+ uint8_t hc_num = ifxhc->hc_num; -+ ifxusb_hc_regs_t *hc_regs = _ifxhcd->core_if.hc_regs[hc_num]; -+ -+ /* Clear old interrupt conditions for this host channel. */ -+ hc_intr_mask.d32 = 0xFFFFFFFF; -+ hc_intr_mask.b.reserved = 0; -+ ifxusb_wreg(&hc_regs->hcint, hc_intr_mask.d32); -+ -+ /* Enable channel interrupts required for this transfer. */ -+ hc_intr_mask.d32 = 0; -+ hc_intr_mask.b.chhltd = 1; -+ hc_intr_mask.b.ahberr = 1; -+ -+ ifxusb_wreg(&hc_regs->hcintmsk, hc_intr_mask.d32); -+ -+ /* Enable the top level host channel interrupt. */ -+ { -+ uint32_t intr_enable; -+ intr_enable = (1 << hc_num); -+ ifxusb_mreg(&_ifxhcd->core_if.host_global_regs->haintmsk, 0, intr_enable); -+ } -+ -+ /* Make sure host channel interrupts are enabled. */ -+ { -+ gint_data_t gintmsk ={.d32 = 0}; -+ gintmsk.b.hcintr = 1; -+ ifxusb_mreg(&_ifxhcd->core_if.core_global_regs->gintmsk, 0, gintmsk.d32); -+ } -+ -+ /* -+ * Program the HCCHARn register with the endpoint characteristics for -+ * the current transfer. -+ */ -+ { -+ hcchar_data_t hcchar; -+ -+ hcchar.d32 = 0; -+ hcchar.b.devaddr = ifxhc->dev_addr; -+ hcchar.b.epnum = ifxhc->ep_num; -+ hcchar.b.lspddev = (ifxhc->speed == IFXUSB_EP_SPEED_LOW); -+ hcchar.b.eptype = ifxhc->ep_type; -+ hcchar.b.mps = ifxhc->mps; -+ ifxusb_wreg(&hc_regs->hcchar, hcchar.d32); -+ -+ IFX_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, ifxhc->hc_num); -+ IFX_DEBUGPL(DBG_HCDV, " Dev Addr: %d\n" , hcchar.b.devaddr); -+ IFX_DEBUGPL(DBG_HCDV, " Ep Num: %d\n" , hcchar.b.epnum); -+ IFX_DEBUGPL(DBG_HCDV, " Is Low Speed: %d\n", hcchar.b.lspddev); -+ IFX_DEBUGPL(DBG_HCDV, " Ep Type: %d\n" , hcchar.b.eptype); -+ IFX_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n" , hcchar.b.mps); -+ IFX_DEBUGPL(DBG_HCDV, " Multi Cnt: %d\n" , hcchar.b.multicnt); -+ } -+ /* Program the HCSPLIT register for SPLITs */ -+ { -+ hcsplt_data_t hcsplt; -+ -+ hcsplt.d32 = 0; -+ if (ifxhc->split) -+ { -+ IFX_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n", ifxhc->hc_num, -+ (ifxhc->split==2) ? "CSPLIT" : "SSPLIT"); -+ hcsplt.b.spltena = 1; -+ hcsplt.b.compsplt = (ifxhc->split==2); -+ #ifdef __EN_ISOC__ -+ if(_epqh->ep_type==IFXUSB_EP_TYPE_ISOC) -+ hcsplt.b.xactpos = ifxhc->isoc_xact_pos; -+ else -+ #endif -+ hcsplt.b.xactpos = IFXUSB_HCSPLIT_XACTPOS_ALL; -+ hcsplt.b.hubaddr = ifxhc->hub_addr; -+ hcsplt.b.prtaddr = ifxhc->port_addr; -+ IFX_DEBUGPL(DBG_HCDV, " comp split %d\n" , hcsplt.b.compsplt); -+ IFX_DEBUGPL(DBG_HCDV, " xact pos %d\n" , hcsplt.b.xactpos); -+ IFX_DEBUGPL(DBG_HCDV, " hub addr %d\n" , hcsplt.b.hubaddr); -+ IFX_DEBUGPL(DBG_HCDV, " port addr %d\n" , hcsplt.b.prtaddr); -+ IFX_DEBUGPL(DBG_HCDV, " is_in %d\n" , ifxhc->is_in); -+ IFX_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n" , ifxhc->mps); -+ IFX_DEBUGPL(DBG_HCDV, " xferlen: %d\n" , ifxhc->xfer_len); -+ } -+ ifxusb_wreg(&hc_regs->hcsplt, hcsplt.d32); -+ } -+ } -+ -+ ifxhc->nak_retry_r=ifxhc->nak_retry=0; -+ ifxhc->nak_countdown_r=ifxhc->nak_countdown=0; -+ -+ if (ifxhc->split) -+ { -+ if(ifxhc->is_in) -+ { -+ } -+ else -+ { -+ } -+ } -+ else if(_epqh->ep_type==IFXUSB_EP_TYPE_CTRL) -+ { -+ if(ifxhc->is_in) -+ { -+ } -+ else -+ { -+ } -+ } -+ else if(_epqh->ep_type==IFXUSB_EP_TYPE_BULK) -+ { -+ if(ifxhc->is_in) -+ { -+// ifxhc->nak_retry_r=ifxhc->nak_retry=nak_retry_max; -+// ifxhc->nak_countdown_r=ifxhc->nak_countdown=nak_countdown_max; -+ } -+ else -+ { -+ } -+ } -+ else if(_epqh->ep_type==IFXUSB_EP_TYPE_INTR) -+ { -+ if(ifxhc->is_in) -+ { -+ } -+ else -+ { -+ } -+ } -+ else if(_epqh->ep_type==IFXUSB_EP_TYPE_ISOC) -+ { -+ if(ifxhc->is_in) -+ { -+ } -+ else -+ { -+ } -+ } -+ -+ return 1; -+} -+ -+/*! -+ \brief This function selects transactions from the HCD transfer schedule and -+ assigns them to available host channels. It is called from HCD interrupt -+ handler functions. -+ */ -+static void select_eps_sub(ifxhcd_hcd_t *_ifxhcd) -+{ -+ struct list_head *epqh_ptr; -+ struct list_head *urbd_ptr; -+ ifxhcd_epqh_t *epqh; -+ ifxhcd_urbd_t *urbd; -+ int ret_val=0; -+ -+ /*== AVM/BC 20101111 Function called with Lock ==*/ -+ -+// #ifdef __DEBUG__ -+// IFX_DEBUGPL(DBG_HCD, " ifxhcd_select_ep\n"); -+// #endif -+ -+ /* Process entries in the periodic ready list. */ -+ #ifdef __EN_ISOC__ -+ epqh_ptr = _ifxhcd->epqh_isoc_ready.next; -+ while (epqh_ptr != &_ifxhcd->epqh_isoc_ready && !list_empty(&_ifxhcd->free_hc_list)) -+ { -+ epqh = list_entry(epqh_ptr, ifxhcd_epqh_t, epqh_list_entry); -+ epqh_ptr = epqh_ptr->next; -+ if(epqh->period_do) -+ { -+ if(assign_and_init_hc(_ifxhcd, epqh)) -+ { -+ IFX_DEBUGPL(DBG_HCD, " select_eps ISOC\n"); -+ list_move_tail(&epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_active); -+ epqh->is_active=1; -+ ret_val=1; -+ epqh->period_do=0; -+ } -+ } -+ } -+ #endif -+ -+ epqh_ptr = _ifxhcd->epqh_intr_ready.next; -+ while (epqh_ptr != &_ifxhcd->epqh_intr_ready && !list_empty(&_ifxhcd->free_hc_list)) -+ { -+ epqh = list_entry(epqh_ptr, ifxhcd_epqh_t, epqh_list_entry); -+ epqh_ptr = epqh_ptr->next; -+ if(epqh->period_do) -+ { -+ if(assign_and_init_hc(_ifxhcd, epqh)) -+ { -+ IFX_DEBUGPL(DBG_HCD, " select_eps INTR\n"); -+ list_move_tail(&epqh->epqh_list_entry, &_ifxhcd->epqh_intr_active); -+ epqh->is_active=1; -+ ret_val=1; -+ epqh->period_do=0; -+ } -+ } -+ } -+ -+ epqh_ptr = _ifxhcd->epqh_np_ready.next; -+ while (epqh_ptr != &_ifxhcd->epqh_np_ready && !list_empty(&_ifxhcd->free_hc_list)) // may need to preserve at lease one for period -+ { -+ epqh = list_entry(epqh_ptr, ifxhcd_epqh_t, epqh_list_entry); -+ epqh_ptr = epqh_ptr->next; -+ if(assign_and_init_hc(_ifxhcd, epqh)) -+ { -+ IFX_DEBUGPL(DBG_HCD, " select_eps CTRL/BULK\n"); -+ list_move_tail(&epqh->epqh_list_entry, &_ifxhcd->epqh_np_active); -+ epqh->is_active=1; -+ ret_val=1; -+ } -+ } -+ if(ret_val) -+ /*== AVM/BC 20101111 Function called with Lock ==*/ -+ process_channels_sub(_ifxhcd); -+ -+ /* AVM/BC 20101111 Urbds completion loop */ -+ while (!list_empty(&_ifxhcd->urbd_complete_list)) -+ { -+ urbd_ptr = _ifxhcd->urbd_complete_list.next; -+ list_del_init(urbd_ptr); -+ -+ urbd = list_entry(urbd_ptr, ifxhcd_urbd_t, urbd_list_entry); -+ -+ ifxhcd_complete_urb(_ifxhcd, urbd, urbd->status); -+ -+ } -+ -+} -+ -+static void select_eps_func(unsigned long data) -+{ -+ unsigned long flags; -+ -+ ifxhcd_hcd_t *ifxhcd; -+ ifxhcd=((ifxhcd_hcd_t *)data); -+ -+ /* AVM/BC 20101111 select_eps_in_use flag removed */ -+ -+ SPIN_LOCK_IRQSAVE(&ifxhcd->lock, flags); -+ -+ /*if(ifxhcd->select_eps_in_use){ -+ SPIN_UNLOCK_IRQRESTORE(&ifxhcd->lock, flags); -+ return; -+ } -+ ifxhcd->select_eps_in_use=1; -+ */ -+ -+ select_eps_sub(ifxhcd); -+ -+ //ifxhcd->select_eps_in_use=0; -+ -+ SPIN_UNLOCK_IRQRESTORE(&ifxhcd->lock, flags); -+} -+ -+void select_eps(ifxhcd_hcd_t *_ifxhcd) -+{ -+ if(in_irq()) -+ { -+ if(!_ifxhcd->select_eps.func) -+ { -+ _ifxhcd->select_eps.next = NULL; -+ _ifxhcd->select_eps.state = 0; -+ atomic_set( &_ifxhcd->select_eps.count, 0); -+ _ifxhcd->select_eps.func = select_eps_func; -+ _ifxhcd->select_eps.data = (unsigned long)_ifxhcd; -+ } -+ tasklet_schedule(&_ifxhcd->select_eps); -+ } -+ else -+ { -+ unsigned long flags; -+ -+ /* AVM/BC 20101111 select_eps_in_use flag removed */ -+ -+ SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags); -+ -+ /*if(_ifxhcd->select_eps_in_use){ -+ printk ("select_eps non_irq: busy\n"); -+ SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); -+ return; -+ } -+ _ifxhcd->select_eps_in_use=1; -+ */ -+ -+ select_eps_sub(_ifxhcd); -+ -+ //_ifxhcd->select_eps_in_use=0; -+ -+ SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); -+ } -+} -+ -+/*! -+ \brief -+ */ -+static void process_unaligned( ifxhcd_epqh_t *_epqh) -+{ -+ #if defined(__UNALIGNED_BUFFER_ADJ__) -+ if(!_epqh->aligned_checked) -+ { -+ uint32_t xfer_len; -+ xfer_len=_epqh->urbd->xfer_len; -+ if(_epqh->urbd->is_in && xfer_len<_epqh->mps) -+ xfer_len = _epqh->mps; -+ _epqh->using_aligned_buf=0; -+ -+ if(xfer_len > 0 && ((unsigned long)_epqh->urbd->xfer_buff) & 3) -+ { -+ if( _epqh->aligned_buf -+ && _epqh->aligned_buf_len > 0 -+ && _epqh->aligned_buf_len < xfer_len -+ ) -+ { -+ ifxusb_free_buf(_epqh->aligned_buf); -+ _epqh->aligned_buf=NULL; -+ _epqh->aligned_buf_len=0; -+ } -+ if(! _epqh->aligned_buf || ! _epqh->aligned_buf_len) -+ { -+ _epqh->aligned_buf = ifxusb_alloc_buf(xfer_len, _epqh->urbd->is_in); -+ if(_epqh->aligned_buf) -+ _epqh->aligned_buf_len = xfer_len; -+ } -+ if(_epqh->aligned_buf) -+ { -+ if(!_epqh->urbd->is_in) -+ memcpy(_epqh->aligned_buf, _epqh->urbd->xfer_buff, xfer_len); -+ _epqh->using_aligned_buf=1; -+ _epqh->hc->xfer_buff = _epqh->aligned_buf; -+ } -+ else -+ IFX_WARN("%s():%d\n",__func__,__LINE__); -+ } -+ if(_epqh->ep_type==IFXUSB_EP_TYPE_CTRL) -+ { -+ _epqh->using_aligned_setup=0; -+ if(((unsigned long)_epqh->urbd->setup_buff) & 3) -+ { -+ if(! _epqh->aligned_setup) -+ _epqh->aligned_setup = ifxusb_alloc_buf(8,0); -+ if(_epqh->aligned_setup) -+ { -+ memcpy(_epqh->aligned_setup, _epqh->urbd->setup_buff, 8); -+ _epqh->using_aligned_setup=1; -+ } -+ else -+ IFX_WARN("%s():%d\n",__func__,__LINE__); -+ _epqh->hc->xfer_buff = _epqh->aligned_setup; -+ } -+ } -+ } -+ #elif defined(__UNALIGNED_BUFFER_CHK__) -+ if(!_epqh->aligned_checked) -+ { -+ if(_epqh->urbd->is_in) -+ { -+ if(_epqh->urbd->xfer_len==0) -+ IFX_WARN("%s():%d IN xfer while length is zero \n",__func__,__LINE__); -+ else{ -+ if(_epqh->urbd->xfer_len < _epqh->mps) -+ IFX_WARN("%s():%d IN xfer while length < mps \n",__func__,__LINE__); -+ -+ if(((unsigned long)_epqh->urbd->xfer_buff) & 3) -+ IFX_WARN("%s():%d IN xfer Buffer UNALIGNED\n",__func__,__LINE__); -+ } -+ } -+ else -+ { -+ if(_epqh->urbd->xfer_len > 0 && (((unsigned long)_epqh->urbd->xfer_buff) & 3) ) -+ IFX_WARN("%s():%d OUT xfer Buffer UNALIGNED\n",__func__,__LINE__); -+ } -+ -+ if(_epqh->ep_type==IFXUSB_EP_TYPE_CTRL) -+ { -+ if(((unsigned long)_epqh->urbd->setup_buff) & 3) -+ IFX_WARN("%s():%d SETUP xfer Buffer UNALIGNED\n",__func__,__LINE__); -+ } -+ } -+ #endif -+ _epqh->aligned_checked=1; -+} -+ -+ -+/*! -+ \brief -+ */ -+void process_channels_sub(ifxhcd_hcd_t *_ifxhcd) -+{ -+ ifxhcd_epqh_t *epqh; -+ struct list_head *epqh_item; -+ struct ifxhcd_hc *hc; -+ -+ #ifdef __EN_ISOC__ -+ if (!list_empty(&_ifxhcd->epqh_isoc_active)) -+ { -+ for (epqh_item = _ifxhcd->epqh_isoc_active.next; -+ epqh_item != &_ifxhcd->epqh_isoc_active; -+ ) -+ { -+ epqh = list_entry(epqh_item, ifxhcd_epqh_t, epqh_list_entry); -+ epqh_item = epqh_item->next; -+ hc=epqh->hc; -+ if(hc && !hc->xfer_started && epqh->period_do) -+ { -+ if(hc->split==0 -+ || hc->split==1 -+ ) -+ { -+ //epqh->ping_state = 0; -+ process_unaligned(epqh); -+ hc->wait_for_sof=epqh->wait_for_sof; -+ epqh->wait_for_sof=0; -+ ifxhcd_hc_start(&_ifxhcd->core_if, hc); -+ epqh->period_do=0; -+ { -+ gint_data_t gintsts = {.d32 = 0}; -+ gintsts.b.sofintr = 1; -+ ifxusb_mreg(&_ifxhcd->core_if.core_global_regs->gintmsk,0, gintsts.d32); -+ } -+ } -+ } -+ } -+ } -+ #endif -+ -+ if (!list_empty(&_ifxhcd->epqh_intr_active)) -+ { -+ for (epqh_item = _ifxhcd->epqh_intr_active.next; -+ epqh_item != &_ifxhcd->epqh_intr_active; -+ ) -+ { -+ epqh = list_entry(epqh_item, ifxhcd_epqh_t, epqh_list_entry); -+ epqh_item = epqh_item->next; -+ hc=epqh->hc; -+ if(hc && !hc->xfer_started && epqh->period_do) -+ { -+ if(hc->split==0 -+ || hc->split==1 -+ ) -+ { -+ //epqh->ping_state = 0; -+ process_unaligned(epqh); -+ hc->wait_for_sof=epqh->wait_for_sof; -+ epqh->wait_for_sof=0; -+ ifxhcd_hc_start(&_ifxhcd->core_if, hc); -+ epqh->period_do=0; -+#ifdef __USE_TIMER_4_SOF__ -+ /* AVM/WK change: let hc_start decide, if irq is needed */ -+#else -+ { -+ gint_data_t gintsts = {.d32 = 0}; -+ gintsts.b.sofintr = 1; -+ ifxusb_mreg(&_ifxhcd->core_if.core_global_regs->gintmsk,0, gintsts.d32); -+ } -+#endif -+ } -+ } -+ -+ } -+ } -+ -+ if (!list_empty(&_ifxhcd->epqh_np_active)) -+ { -+ for (epqh_item = _ifxhcd->epqh_np_active.next; -+ epqh_item != &_ifxhcd->epqh_np_active; -+ ) -+ { -+ epqh = list_entry(epqh_item, ifxhcd_epqh_t, epqh_list_entry); -+ epqh_item = epqh_item->next; -+ hc=epqh->hc; -+ if(hc) -+ { -+ if(!hc->xfer_started) -+ { -+ if(hc->split==0 -+ || hc->split==1 -+ //|| hc->split_counter == 0 -+ ) -+ { -+ //epqh->ping_state = 0; -+ process_unaligned(epqh); -+ hc->wait_for_sof=epqh->wait_for_sof; -+ epqh->wait_for_sof=0; -+ ifxhcd_hc_start(&_ifxhcd->core_if, hc); -+ } -+ } -+ } -+ } -+ } -+} -+ -+void process_channels(ifxhcd_hcd_t *_ifxhcd) -+{ -+ unsigned long flags; -+ -+ /* AVM/WK Fix: use spin_lock instead busy flag -+ **/ -+ SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags); -+ -+ //if(_ifxhcd->process_channels_in_use) -+ // return; -+ //_ifxhcd->process_channels_in_use=1; -+ -+ process_channels_sub(_ifxhcd); -+ //_ifxhcd->process_channels_in_use=0; -+ SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); -+} -+ -+ -+#ifdef __HC_XFER_TIMEOUT__ -+ static void hc_xfer_timeout(unsigned long _ptr) -+ { -+ hc_xfer_info_t *xfer_info = (hc_xfer_info_t *)_ptr; -+ int hc_num = xfer_info->hc->hc_num; -+ IFX_WARN("%s: timeout on channel %d\n", __func__, hc_num); -+ IFX_WARN(" start_hcchar_val 0x%08x\n", xfer_info->hc->start_hcchar_val); -+ } -+#endif -+ -+void ifxhcd_hc_dumb_rx(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc,uint8_t *dump_buf) -+{ -+ ifxusb_hc_regs_t *hc_regs = _core_if->hc_regs[_ifxhc->hc_num]; -+ hctsiz_data_t hctsiz= { .d32=0 }; -+ hcchar_data_t hcchar; -+ -+ -+ _ifxhc->xfer_len = _ifxhc->mps; -+ hctsiz.b.xfersize = _ifxhc->mps; -+ hctsiz.b.pktcnt = 0; -+ hctsiz.b.pid = _ifxhc->data_pid_start; -+ ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32); -+ -+ ifxusb_wreg(&hc_regs->hcdma, (uint32_t)(CPHYSADDR( ((uint32_t)(dump_buf))))); -+ -+ { -+ hcint_data_t hcint= { .d32=0 }; -+// hcint.b.nak =1; -+// hcint.b.nyet=1; -+// hcint.b.ack =1; -+ hcint.d32 =0xFFFFFFFF; -+ ifxusb_wreg(&hc_regs->hcint, hcint.d32); -+ } -+ -+ /* Set host channel enable after all other setup is complete. */ -+ hcchar.b.chen = 1; -+ hcchar.b.chdis = 0; -+ hcchar.b.epdir = 1; -+ IFX_DEBUGPL(DBG_HCDV, " HCCHART: 0x%08x\n", hcchar.d32); -+ ifxusb_wreg(&hc_regs->hcchar, hcchar.d32); -+} -+ -+/*! -+ \brief This function trigger a data transfer for a host channel and -+ starts the transfer. -+ -+ For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ -+ register along with a packet count of 1 and the channel is enabled. This -+ causes a single PING transaction to occur. Other fields in HCTSIZ are -+ simply set to 0 since no data transfer occurs in this case. -+ -+ For a PING transfer in DMA mode, the HCTSIZ register is initialized with -+ all the information required to perform the subsequent data transfer. In -+ addition, the Do Ping bit is set in the HCTSIZ register. In this case, the -+ controller performs the entire PING protocol, then starts the data -+ transfer. -+ \param _core_if Pointer of core_if structure -+ \param _ifxhc Information needed to initialize the host channel. The xfer_len -+ value may be reduced to accommodate the max widths of the XferSize and -+ PktCnt fields in the HCTSIZn register. The multi_count value may be changed -+ to reflect the final xfer_len value. -+ */ -+void ifxhcd_hc_start(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc) -+{ -+ hctsiz_data_t hctsiz= { .d32=0 }; -+ hcchar_data_t hcchar; -+ uint32_t max_hc_xfer_size = _core_if->params.max_transfer_size; -+ uint16_t max_hc_pkt_count = _core_if->params.max_packet_count; -+ ifxusb_hc_regs_t *hc_regs = _core_if->hc_regs[_ifxhc->hc_num]; -+ hfnum_data_t hfnum; -+ -+ hctsiz.b.dopng = 0; -+// if(_ifxhc->do_ping && !_ifxhc->is_in) hctsiz.b.dopng = 1; -+ -+ _ifxhc->nak_countdown=_ifxhc->nak_countdown_r; -+ -+ /* AVM/BC 20101111 Workaround: Always PING if HI-Speed Out and xfer_len > 0 */ -+ if(/*_ifxhc->do_ping &&*/ -+ (!_ifxhc->is_in) && -+ (_ifxhc->speed == IFXUSB_EP_SPEED_HIGH) && -+ ((_ifxhc->ep_type == IFXUSB_EP_TYPE_BULK) || ((_ifxhc->ep_type == IFXUSB_EP_TYPE_CTRL) && (_ifxhc->control_phase != IFXHCD_CONTROL_SETUP))) && -+ _ifxhc->xfer_len -+ ) -+ hctsiz.b.dopng = 1; -+ -+ _ifxhc->xfer_started = 1; -+ -+ if(_ifxhc->epqh->pkt_count_limit > 0 && _ifxhc->epqh->pkt_count_limit < max_hc_pkt_count ) -+ { -+ max_hc_pkt_count=_ifxhc->epqh->pkt_count_limit; -+ if(max_hc_pkt_count * _ifxhc->mps < max_hc_xfer_size) -+ max_hc_xfer_size = max_hc_pkt_count * _ifxhc->mps; -+ } -+ if (_ifxhc->split > 0) -+ { -+ { -+ gint_data_t gintsts = {.d32 = 0}; -+ gintsts.b.sofintr = 1; -+ ifxusb_mreg(&_core_if->core_global_regs->gintmsk,0, gintsts.d32); -+ } -+ -+ _ifxhc->start_pkt_count = 1; -+ if(!_ifxhc->is_in && _ifxhc->split>1) // OUT CSPLIT -+ _ifxhc->xfer_len = 0; -+ if (_ifxhc->xfer_len > _ifxhc->mps) -+ _ifxhc->xfer_len = _ifxhc->mps; -+ if (_ifxhc->xfer_len > 188) -+ _ifxhc->xfer_len = 188; -+ } -+ else if(_ifxhc->is_in) -+ { -+ _ifxhc->short_rw = 0; -+ if (_ifxhc->xfer_len > 0) -+ { -+ if (_ifxhc->xfer_len > max_hc_xfer_size) -+ _ifxhc->xfer_len = max_hc_xfer_size - _ifxhc->mps + 1; -+ _ifxhc->start_pkt_count = (_ifxhc->xfer_len + _ifxhc->mps - 1) / _ifxhc->mps; -+ if (_ifxhc->start_pkt_count > max_hc_pkt_count) -+ _ifxhc->start_pkt_count = max_hc_pkt_count; -+ } -+ else /* Need 1 packet for transfer length of 0. */ -+ _ifxhc->start_pkt_count = 1; -+ _ifxhc->xfer_len = _ifxhc->start_pkt_count * _ifxhc->mps; -+ } -+ else //non-split out -+ { -+ if (_ifxhc->xfer_len == 0) -+ { -+ /*== AVM/BC WK 20110421 ZERO PACKET Workaround: Is not an error ==*/ -+ //if(_ifxhc->short_rw==0) -+ // printk(KERN_INFO "%s() line %d: ZLP write without short_rw set!\n",__func__,__LINE__); -+ _ifxhc->start_pkt_count = 1; -+ } -+ else -+ { -+ if (_ifxhc->xfer_len > max_hc_xfer_size) -+ { -+ _ifxhc->start_pkt_count = (max_hc_xfer_size / _ifxhc->mps); -+ _ifxhc->xfer_len = _ifxhc->start_pkt_count * _ifxhc->mps; -+ } -+ else -+ { -+ _ifxhc->start_pkt_count = (_ifxhc->xfer_len+_ifxhc->mps-1) / _ifxhc->mps; -+// if(_ifxhc->start_pkt_count * _ifxhc->mps == _ifxhc->xfer_len ) -+// _ifxhc->start_pkt_count += _ifxhc->short_rw; -+ /*== AVM/BC WK 20110421 ZERO PACKET Workaround / check if short_rw is needed ==*/ -+ if(_ifxhc->start_pkt_count * _ifxhc->mps != _ifxhc->xfer_len ) -+ _ifxhc->short_rw = 0; -+ } -+ } -+ } -+ -+ #ifdef __EN_ISOC__ -+ if (_ifxhc->ep_type == IFXUSB_EP_TYPE_ISOC) -+ { -+ /* Set up the initial PID for the transfer. */ -+ #if 1 -+ _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0; -+ #else -+ if (_ifxhc->speed == IFXUSB_EP_SPEED_HIGH) -+ { -+ if (_ifxhc->is_in) -+ { -+ if (_ifxhc->multi_count == 1) -+ _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0; -+ else if (_ifxhc->multi_count == 2) -+ _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1; -+ else -+ _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA2; -+ } -+ else -+ { -+ if (_ifxhc->multi_count == 1) -+ _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0; -+ else -+ _ifxhc->data_pid_start = IFXUSB_HC_PID_MDATA; -+ } -+ } -+ else -+ _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0; -+ #endif -+ } -+ #endif -+ -+ hctsiz.b.xfersize = _ifxhc->xfer_len; -+ hctsiz.b.pktcnt = _ifxhc->start_pkt_count; -+ hctsiz.b.pid = _ifxhc->data_pid_start; -+ -+ ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32); -+ -+ -+ IFX_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _ifxhc->hc_num); -+ IFX_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize); -+ IFX_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n" , hctsiz.b.pktcnt); -+ IFX_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid); -+ IFX_DEBUGPL(DBG_HCDV, " DMA: 0x%08x\n", (uint32_t)(CPHYSADDR( ((uint32_t)(_ifxhc->xfer_buff))+ _ifxhc->xfer_count ))); -+ ifxusb_wreg(&hc_regs->hcdma, (uint32_t)(CPHYSADDR( ((uint32_t)(_ifxhc->xfer_buff))+ _ifxhc->xfer_count ))); -+ -+ /* Start the split */ -+ if (_ifxhc->split>0) -+ { -+ hcsplt_data_t hcsplt; -+ hcsplt.d32 = ifxusb_rreg (&hc_regs->hcsplt); -+ hcsplt.b.spltena = 1; -+ if (_ifxhc->split>1) -+ hcsplt.b.compsplt = 1; -+ else -+ hcsplt.b.compsplt = 0; -+ -+ #ifdef __EN_ISOC__ -+ if (_ifxhc->ep_type == IFXUSB_EP_TYPE_ISOC) -+ hcsplt.b.xactpos = _ifxhc->isoc_xact_pos; -+ else -+ #endif -+ hcsplt.b.xactpos = IFXUSB_HCSPLIT_XACTPOS_ALL;// if not ISO -+ ifxusb_wreg(&hc_regs->hcsplt, hcsplt.d32); -+ IFX_DEBUGPL(DBG_HCDV, " SPLIT: XACT_POS:0x%08x\n", hcsplt.d32); -+ } -+ -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+// hcchar.b.multicnt = _ifxhc->multi_count; -+ hcchar.b.multicnt = 1; -+ -+ #ifdef __DEBUG__ -+ _ifxhc->start_hcchar_val = hcchar.d32; -+ if (hcchar.b.chdis) -+ IFX_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", -+ __func__, _ifxhc->hc_num, hcchar.d32); -+ #endif -+ -+ /* Set host channel enable after all other setup is complete. */ -+ hcchar.b.chen = 1; -+ hcchar.b.chdis = 0; -+ hcchar.b.epdir = _ifxhc->is_in; -+ _ifxhc->hcchar=hcchar.d32; -+ -+ IFX_DEBUGPL(DBG_HCDV, " HCCHART: 0x%08x\n", _ifxhc->hcchar); -+ -+ /* == 20110901 AVM/WK Fix: Clear IRQ flags in any case ==*/ -+ { -+ hcint_data_t hcint= { .d32=0 }; -+ hcint.d32 =0xFFFFFFFF; -+ ifxusb_wreg(&hc_regs->hcint, hcint.d32); -+ } -+ -+ if(_ifxhc->wait_for_sof==0) -+ { -+ hcint_data_t hcint; -+ -+ hcint.d32=ifxusb_rreg(&hc_regs->hcintmsk); -+ -+ hcint.b.nak =0; -+ hcint.b.ack =0; -+ /* == 20110901 AVM/WK Fix: We don't need NOT YET IRQ ==*/ -+ hcint.b.nyet=0; -+ if(_ifxhc->nak_countdown_r) -+ hcint.b.nak =1; -+ ifxusb_wreg(&hc_regs->hcintmsk, hcint.d32); -+ -+ /* AVM WK / BC 20100827 -+ * MOVED. Oddframe updated inmediatly before write HCChar Register. -+ */ -+ if (_ifxhc->ep_type == IFXUSB_EP_TYPE_INTR || _ifxhc->ep_type == IFXUSB_EP_TYPE_ISOC) -+ { -+ hfnum.d32 = ifxusb_rreg(&_core_if->host_global_regs->hfnum); -+ /* 1 if _next_ frame is odd, 0 if it's even */ -+ hcchar.b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1; -+ _ifxhc->hcchar=hcchar.d32; -+ } -+ -+ ifxusb_wreg(&hc_regs->hcchar, _ifxhc->hcchar); -+#ifdef __USE_TIMER_4_SOF__ -+ } else { -+ //activate SOF IRQ -+ gint_data_t gintsts = {.d32 = 0}; -+ gintsts.b.sofintr = 1; -+ ifxusb_mreg(&_core_if->core_global_regs->gintmsk,0, gintsts.d32); -+#endif -+ } -+ -+ #ifdef __HC_XFER_TIMEOUT__ -+ /* Start a timer for this transfer. */ -+ init_timer(&_ifxhc->hc_xfer_timer); -+ _ifxhc->hc_xfer_timer.function = hc_xfer_timeout; -+ _ifxhc->hc_xfer_timer.core_if = _core_if; -+ _ifxhc->hc_xfer_timer.hc = _ifxhc; -+ _ifxhc->hc_xfer_timer.data = (unsigned long)(&_ifxhc->hc_xfer_info); -+ _ifxhc->hc_xfer_timer.expires = jiffies + (HZ*10); -+ add_timer(&_ifxhc->hc_xfer_timer); -+ #endif -+} -+ -+/*! -+ \brief Attempts to halt a host channel. This function should only be called -+ to abort a transfer in DMA mode. Under normal circumstances in DMA mode, the -+ controller halts the channel when the transfer is complete or a condition -+ occurs that requires application intervention. -+ -+ In DMA mode, always sets the Channel Enable and Channel Disable bits of the -+ HCCHARn register. The controller ensures there is space in the request -+ queue before submitting the halt request. -+ -+ Some time may elapse before the core flushes any posted requests for this -+ host channel and halts. The Channel Halted interrupt handler completes the -+ deactivation of the host channel. -+ */ -+void ifxhcd_hc_halt(ifxusb_core_if_t *_core_if, -+ ifxhcd_hc_t *_ifxhc, -+ ifxhcd_halt_status_e _halt_status) -+{ -+ hcchar_data_t hcchar; -+ ifxusb_hc_regs_t *hc_regs; -+ -+ hc_regs = _core_if->hc_regs[_ifxhc->hc_num]; -+ -+ WARN_ON(_halt_status == HC_XFER_NO_HALT_STATUS); -+ -+ if (_halt_status == HC_XFER_URB_DEQUEUE || -+ _halt_status == HC_XFER_AHB_ERR) -+ { -+ /* -+ * Disable all channel interrupts except Ch Halted. The URBD -+ * and EPQH state associated with this transfer has been cleared -+ * (in the case of URB_DEQUEUE), so the channel needs to be -+ * shut down carefully to prevent crashes. -+ */ -+ hcint_data_t hcintmsk; -+ hcintmsk.d32 = 0; -+ hcintmsk.b.chhltd = 1; -+ ifxusb_wreg(&hc_regs->hcintmsk, hcintmsk.d32); -+ -+ /* -+ * Make sure no other interrupts besides halt are currently -+ * pending. Handling another interrupt could cause a crash due -+ * to the URBD and EPQH state. -+ */ -+ ifxusb_wreg(&hc_regs->hcint, ~hcintmsk.d32); -+ -+ /* -+ * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR -+ * even if the channel was already halted for some other -+ * reason. -+ */ -+ _ifxhc->halt_status = _halt_status; -+ -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ if (hcchar.b.chen == 0) -+ { -+ /* -+ * The channel is either already halted or it hasn't -+ * started yet. In DMA mode, the transfer may halt if -+ * it finishes normally or a condition occurs that -+ * requires driver intervention. Don't want to halt -+ * the channel again. In either Slave or DMA mode, -+ * it's possible that the transfer has been assigned -+ * to a channel, but not started yet when an URB is -+ * dequeued. Don't want to halt a channel that hasn't -+ * started yet. -+ */ -+ return; -+ } -+ } -+ -+ if (_ifxhc->halting) -+ { -+ /* -+ * A halt has already been issued for this channel. This might -+ * happen when a transfer is aborted by a higher level in -+ * the stack. -+ */ -+ #ifdef __DEBUG__ -+ IFX_PRINT("*** %s: Channel %d, _hc->halting already set ***\n", -+ __func__, _ifxhc->hc_num); -+ #endif -+ //ifxusb_dump_global_registers(_core_if); */ -+ //ifxusb_dump_host_registers(_core_if); */ -+ return; -+ } -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ /* == AVM/WK 20100709 halt channel only if enabled ==*/ -+ if (hcchar.b.chen) { -+ _ifxhc->halting = 1; -+ hcchar.b.chdis = 1; -+ -+ ifxusb_wreg(&hc_regs->hcchar, hcchar.d32); -+ _ifxhc->halt_status = _halt_status; -+ } -+ -+ IFX_DEBUGPL(DBG_HCDV, "%s: Channel %d\n" , __func__, _ifxhc->hc_num); -+ IFX_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n" , hcchar.d32); -+ IFX_DEBUGPL(DBG_HCDV, " halting: %d\n" , _ifxhc->halting); -+ IFX_DEBUGPL(DBG_HCDV, " halt_status: %d\n" , _ifxhc->halt_status); -+ -+ return; -+} -+ -+/*! -+ \brief Clears a host channel. -+ */ -+void ifxhcd_hc_cleanup(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc) -+{ -+ ifxusb_hc_regs_t *hc_regs; -+ -+ _ifxhc->xfer_started = 0; -+ /* -+ * Clear channel interrupt enables and any unhandled channel interrupt -+ * conditions. -+ */ -+ hc_regs = _core_if->hc_regs[_ifxhc->hc_num]; -+ ifxusb_wreg(&hc_regs->hcintmsk, 0); -+ ifxusb_wreg(&hc_regs->hcint, 0xFFFFFFFF); -+ -+ #ifdef __HC_XFER_TIMEOUT__ -+ del_timer(&_ifxhc->hc_xfer_timer); -+ #endif -+ #ifdef __DEBUG__ -+ { -+ hcchar_data_t hcchar; -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ if (hcchar.b.chdis) -+ IFX_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", __func__, _ifxhc->hc_num, hcchar.d32); -+ } -+ #endif -+} -+ -+ -+ -+ -+ -+ -+ -+ -+#ifdef __DEBUG__ -+ static void dump_urb_info(struct urb *_urb, char* _fn_name) -+ { -+ IFX_PRINT("%s, urb %p\n" , _fn_name, _urb); -+ IFX_PRINT(" Device address: %d\n", usb_pipedevice(_urb->pipe)); -+ IFX_PRINT(" Endpoint: %d, %s\n" , usb_pipeendpoint(_urb->pipe), -+ (usb_pipein(_urb->pipe) ? "IN" : "OUT")); -+ IFX_PRINT(" Endpoint type: %s\n", -+ ({ char *pipetype; -+ switch (usb_pipetype(_urb->pipe)) { -+ case PIPE_CONTROL: pipetype = "CONTROL"; break; -+ case PIPE_BULK: pipetype = "BULK"; break; -+ case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break; -+ case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break; -+ default: pipetype = "UNKNOWN"; break; -+ }; -+ pipetype; -+ })); -+ IFX_PRINT(" Speed: %s\n", -+ ({ char *speed; -+ switch (_urb->dev->speed) { -+ case USB_SPEED_HIGH: speed = "HIGH"; break; -+ case USB_SPEED_FULL: speed = "FULL"; break; -+ case USB_SPEED_LOW: speed = "LOW"; break; -+ default: speed = "UNKNOWN"; break; -+ }; -+ speed; -+ })); -+ IFX_PRINT(" Max packet size: %d\n", -+ usb_maxpacket(_urb->dev, _urb->pipe, usb_pipeout(_urb->pipe))); -+ IFX_PRINT(" Data buffer length: %d\n", _urb->transfer_buffer_length); -+ IFX_PRINT(" Transfer buffer: %p, Transfer DMA: %p\n", -+ _urb->transfer_buffer, (void *)_urb->transfer_dma); -+ IFX_PRINT(" Setup buffer: %p, Setup DMA: %p\n", -+ _urb->setup_packet, (void *)_urb->setup_dma); -+ IFX_PRINT(" Interval: %d\n", _urb->interval); -+ if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) -+ { -+ int i; -+ for (i = 0; i < _urb->number_of_packets; i++) -+ { -+ IFX_PRINT(" ISO Desc %d:\n", i); -+ IFX_PRINT(" offset: %d, length %d\n", -+ _urb->iso_frame_desc[i].offset, -+ _urb->iso_frame_desc[i].length); -+ } -+ } -+ } -+ -+ static void dump_channel_info(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh) -+ { -+ if (_epqh->hc != NULL) -+ { -+ ifxhcd_hc_t *hc = _epqh->hc; -+ struct list_head *item; -+ ifxhcd_epqh_t *epqh_item; -+ -+ ifxusb_hc_regs_t *hc_regs; -+ -+ hcchar_data_t hcchar; -+ hcsplt_data_t hcsplt; -+ hctsiz_data_t hctsiz; -+ uint32_t hcdma; -+ -+ hc_regs = _ifxhcd->core_if.hc_regs[hc->hc_num]; -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ hcsplt.d32 = ifxusb_rreg(&hc_regs->hcsplt); -+ hctsiz.d32 = ifxusb_rreg(&hc_regs->hctsiz); -+ hcdma = ifxusb_rreg(&hc_regs->hcdma); -+ -+ IFX_PRINT(" Assigned to channel %d:\n" , hc->hc_num); -+ IFX_PRINT(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32); -+ IFX_PRINT(" hctsiz 0x%08x, hcdma 0x%08x\n" , hctsiz.d32, hcdma); -+ IFX_PRINT(" dev_addr: %d, ep_num: %d, is_in: %d\n", -+ hc->dev_addr, hc->ep_num, hc->is_in); -+ IFX_PRINT(" ep_type: %d\n" , hc->ep_type); -+ IFX_PRINT(" max_packet_size: %d\n", hc->mps); -+ IFX_PRINT(" data_pid_start: %d\n" , hc->data_pid_start); -+ IFX_PRINT(" xfer_started: %d\n" , hc->xfer_started); -+ IFX_PRINT(" halt_status: %d\n" , hc->halt_status); -+ IFX_PRINT(" xfer_buff: %p\n" , hc->xfer_buff); -+ IFX_PRINT(" xfer_len: %d\n" , hc->xfer_len); -+ IFX_PRINT(" epqh: %p\n" , hc->epqh); -+ IFX_PRINT(" NP Active:\n"); -+ list_for_each(item, &_ifxhcd->epqh_np_active) -+ { -+ epqh_item = list_entry(item, ifxhcd_epqh_t, epqh_list_entry); -+ IFX_PRINT(" %p\n", epqh_item); -+ } -+ IFX_PRINT(" NP Ready:\n"); -+ list_for_each(item, &_ifxhcd->epqh_np_ready) -+ { -+ epqh_item = list_entry(item, ifxhcd_epqh_t, epqh_list_entry); -+ IFX_PRINT(" %p\n", epqh_item); -+ } -+ IFX_PRINT(" INTR Active:\n"); -+ list_for_each(item, &_ifxhcd->epqh_intr_active) -+ { -+ epqh_item = list_entry(item, ifxhcd_epqh_t, epqh_list_entry); -+ IFX_PRINT(" %p\n", epqh_item); -+ } -+ IFX_PRINT(" INTR Ready:\n"); -+ list_for_each(item, &_ifxhcd->epqh_intr_ready) -+ { -+ epqh_item = list_entry(item, ifxhcd_epqh_t, epqh_list_entry); -+ IFX_PRINT(" %p\n", epqh_item); -+ } -+ #ifdef __EN_ISOC__ -+ IFX_PRINT(" ISOC Active:\n"); -+ list_for_each(item, &_ifxhcd->epqh_isoc_active) -+ { -+ epqh_item = list_entry(item, ifxhcd_epqh_t, epqh_list_entry); -+ IFX_PRINT(" %p\n", epqh_item); -+ } -+ IFX_PRINT(" ISOC Ready:\n"); -+ list_for_each(item, &_ifxhcd->epqh_isoc_ready) -+ { -+ epqh_item = list_entry(item, ifxhcd_epqh_t, epqh_list_entry); -+ IFX_PRINT(" %p\n", epqh_item); -+ } -+ #endif -+ IFX_PRINT(" Standby:\n"); -+ list_for_each(item, &_ifxhcd->epqh_stdby) -+ { -+ epqh_item = list_entry(item, ifxhcd_epqh_t, epqh_list_entry); -+ IFX_PRINT(" %p\n", epqh_item); -+ } -+ } -+ } -+#endif //__DEBUG__ -+ -+ -+/*! -+ \brief This function writes a packet into the Tx FIFO associated with the Host -+ Channel. For a channel associated with a non-periodic EP, the non-periodic -+ Tx FIFO is written. For a channel associated with a periodic EP, the -+ periodic Tx FIFO is written. This function should only be called in Slave -+ mode. -+ -+ Upon return the xfer_buff and xfer_count fields in _hc are incremented by -+ then number of bytes written to the Tx FIFO. -+ */ -+ -+#ifdef __ENABLE_DUMP__ -+ void ifxhcd_dump_state(ifxhcd_hcd_t *_ifxhcd) -+ { -+ int num_channels; -+ int i; -+ num_channels = _ifxhcd->core_if.params.host_channels; -+ IFX_PRINT("\n"); -+ IFX_PRINT("************************************************************\n"); -+ IFX_PRINT("HCD State:\n"); -+ IFX_PRINT(" Num channels: %d\n", num_channels); -+ for (i = 0; i < num_channels; i++) { -+ ifxhcd_hc_t *hc = &_ifxhcd->ifxhc[i]; -+ IFX_PRINT(" Channel %d:\n", hc->hc_num); -+ IFX_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n", -+ hc->dev_addr, hc->ep_num, hc->is_in); -+ IFX_PRINT(" speed: %d\n" , hc->speed); -+ IFX_PRINT(" ep_type: %d\n" , hc->ep_type); -+ IFX_PRINT(" mps: %d\n", hc->mps); -+ IFX_PRINT(" data_pid_start: %d\n" , hc->data_pid_start); -+ IFX_PRINT(" xfer_started: %d\n" , hc->xfer_started); -+ IFX_PRINT(" xfer_buff: %p\n" , hc->xfer_buff); -+ IFX_PRINT(" xfer_len: %d\n" , hc->xfer_len); -+ IFX_PRINT(" xfer_count: %d\n" , hc->xfer_count); -+ IFX_PRINT(" halting: %d\n" , hc->halting); -+ IFX_PRINT(" halt_status: %d\n" , hc->halt_status); -+ IFX_PRINT(" split: %d\n" , hc->split); -+ IFX_PRINT(" hub_addr: %d\n" , hc->hub_addr); -+ IFX_PRINT(" port_addr: %d\n" , hc->port_addr); -+ #ifdef __EN_ISOC__ -+ IFX_PRINT(" isoc_xact_pos: %d\n" , hc->isoc_xact_pos); -+ #endif -+ IFX_PRINT(" epqh: %p\n" , hc->epqh); -+ IFX_PRINT(" short_rw: %d\n" , hc->short_rw); -+ IFX_PRINT(" do_ping: %d\n" , hc->do_ping); -+ IFX_PRINT(" control_phase: %d\n" , hc->control_phase); -+ IFX_PRINT(" pkt_count_limit: %d\n", hc->epqh->pkt_count_limit); -+ IFX_PRINT(" start_pkt_count: %d\n" , hc->start_pkt_count); -+ } -+ IFX_PRINT("************************************************************\n"); -+ IFX_PRINT("\n"); -+ } -+#endif //__ENABLE_DUMP__ -+ ---- /dev/null -+++ b/drivers/usb/ifxhcd/ifxhcd.h -@@ -0,0 +1,628 @@ -+/***************************************************************************** -+ ** FILE NAME : ifxhcd.h -+ ** PROJECT : IFX USB sub-system V3 -+ ** MODULES : IFX USB sub-system Host and Device driver -+ ** SRC VERSION : 1.0 -+ ** DATE : 1/Jan/2009 -+ ** AUTHOR : Chen, Howard -+ ** DESCRIPTION : This file contains the structures, constants, and interfaces for -+ ** the Host Contoller Driver (HCD). -+ ** -+ ** The Host Controller Driver (HCD) is responsible for translating requests -+ ** from the USB Driver into the appropriate actions on the IFXUSB controller. -+ ** It isolates the USBD from the specifics of the controller by providing an -+ ** API to the USBD. -+ ** FUNCTIONS : -+ ** COMPILER : gcc -+ ** REFERENCE : Synopsys DWC-OTG Driver 2.7 -+ ** COPYRIGHT : -+ ** Version Control Section ** -+ ** $Author$ -+ ** $Date$ -+ ** $Revisions$ -+ ** $Log$ Revision history -+*****************************************************************************/ -+ -+/*! -+ \defgroup IFXUSB_HCD HCD Interface -+ \ingroup IFXUSB_DRIVER_V3 -+ \brief The Host Controller Driver (HCD) is responsible for translating requests -+ from the USB Driver into the appropriate actions on the IFXUSB controller. -+ It isolates the USBD from the specifics of the controller by providing an -+ API to the USBD. -+ */ -+ -+ -+/*! -+ \file ifxhcd.h -+ \ingroup IFXUSB_DRIVER_V3 -+ \brief This file contains the structures, constants, and interfaces for -+ the Host Contoller Driver (HCD). -+ */ -+ -+#if !defined(__IFXHCD_H__) -+#define __IFXHCD_H__ -+ -+#include -+#include -+ -+#ifdef __USE_TIMER_4_SOF__ -+#include -+#endif -+#include -+ -+#include "ifxusb_cif.h" -+#include "ifxusb_plat.h" -+ -+ -+ -+/*! -+ \addtogroup IFXUSB_HCD -+ */ -+/*@{*/ -+ -+/* Phases for control transfers.*/ -+typedef enum ifxhcd_control_phase { -+ IFXHCD_CONTROL_SETUP, -+ IFXHCD_CONTROL_DATA, -+ IFXHCD_CONTROL_STATUS -+} ifxhcd_control_phase_e; -+ -+/* Reasons for halting a host channel. */ -+typedef enum ifxhcd_halt_status -+{ -+ HC_XFER_NO_HALT_STATUS, // Initial -+ HC_XFER_COMPLETE, // Xact complete without error, upward -+ HC_XFER_URB_COMPLETE, // Xfer complete without error, short upward -+ HC_XFER_STALL, // HC stopped abnormally, upward/downward -+ HC_XFER_XACT_ERR, // HC stopped abnormally, upward -+ HC_XFER_FRAME_OVERRUN, // HC stopped abnormally, upward -+ HC_XFER_BABBLE_ERR, // HC stopped abnormally, upward -+ HC_XFER_AHB_ERR, // HC stopped abnormally, upward -+ HC_XFER_DATA_TOGGLE_ERR, -+ HC_XFER_URB_DEQUEUE, // HC stopper manually, downward -+ HC_XFER_NAK // HC stopped by nak monitor, downward -+} ifxhcd_halt_status_e; -+ -+struct ifxhcd_urbd; -+struct ifxhcd_hc ; -+struct ifxhcd_epqh ; -+struct ifxhcd_hcd; -+ -+/*! -+ \brief A URB Descriptor (URBD) holds the state of a bulk, control, -+ interrupt, or isochronous transfer. A single URBD is created for each URB -+ (of one of these types) submitted to the HCD. The transfer associated with -+ a URBD may require one or multiple transactions. -+ -+ A URBD is linked to a EP Queue Head, which is entered in either the -+ isoc, intr or non-periodic schedule for execution. When a URBD is chosen for -+ execution, some or all of its transactions may be executed. After -+ execution, the state of the URBD is updated. The URBD may be retired if all -+ its transactions are complete or if an error occurred. Otherwise, it -+ remains in the schedule so more transactions can be executed later. -+ */ -+typedef struct ifxhcd_urbd { -+ struct list_head urbd_list_entry; // Hook for EPQH->urbd_list and ifxhcd->urbd_complete_list -+ struct urb *urb; /*!< URB for this transfer */ -+ //struct urb { -+ // struct list_head urb_list; -+ // struct list_head anchor_list; -+ // struct usb_anchor * anchor; -+ // struct usb_device * dev; -+ // struct usb_host_endpoint * ep; -+ // unsigned int pipe; -+ // int status; -+ // unsigned int transfer_flags; -+ // void * transfer_buffer; -+ // dma_addr_t transfer_dma; -+ // u32 transfer_buffer_length; -+ // u32 actual_length; -+ // unsigned char * setup_packet; -+ // dma_addr_t setup_dma; -+ // int start_frame; -+ // int number_of_packets; -+ // int interval; -+ // int error_count; -+ // void * context; -+ // usb_complete_t complete; -+ // struct usb_iso_packet_descriptor iso_frame_desc[0]; -+ //}; -+ //urb_list For use by current owner of the URB. -+ //anchor_list membership in the list of an anchor -+ //anchor to anchor URBs to a common mooring -+ //dev Identifies the USB device to perform the request. -+ //ep Points to the endpoint's data structure. Will -+ // eventually replace pipe. -+ //pipe Holds endpoint number, direction, type, and more. -+ // Create these values with the eight macros available; u -+ // sb_{snd,rcv}TYPEpipe(dev,endpoint), where the TYPE is -+ // "ctrl", "bulk", "int" or "iso". For example -+ // usb_sndbulkpipe or usb_rcvintpipe. Endpoint numbers -+ // range from zero to fifteen. Note that "in" endpoint two -+ // is a different endpoint (and pipe) from "out" endpoint -+ // two. The current configuration controls the existence, -+ // type, and maximum packet size of any given endpoint. -+ //status This is read in non-iso completion functions to get -+ // the status of the particular request. ISO requests -+ // only use it to tell whether the URB was unlinked; -+ // detailed status for each frame is in the fields of -+ // the iso_frame-desc. -+ //transfer_flags A variety of flags may be used to affect how URB -+ // submission, unlinking, or operation are handled. -+ // Different kinds of URB can use different flags. -+ // URB_SHORT_NOT_OK -+ // URB_ISO_ASAP -+ // URB_NO_TRANSFER_DMA_MAP -+ // URB_NO_SETUP_DMA_MAP -+ // URB_NO_FSBR -+ // URB_ZERO_PACKET -+ // URB_NO_INTERRUPT -+ //transfer_buffer This identifies the buffer to (or from) which the I/O -+ // request will be performed (unless URB_NO_TRANSFER_DMA_MAP -+ // is set). This buffer must be suitable for DMA; allocate it -+ // with kmalloc or equivalent. For transfers to "in" -+ // endpoints, contents of this buffer will be modified. This -+ // buffer is used for the data stage of control transfers. -+ //transfer_dma When transfer_flags includes URB_NO_TRANSFER_DMA_MAP, the -+ // device driver is saying that it provided this DMA address, -+ // which the host controller driver should use in preference -+ // to the transfer_buffer. -+ //transfer_buffer_length How big is transfer_buffer. The transfer may be broken -+ // up into chunks according to the current maximum packet size -+ // for the endpoint, which is a function of the configuration -+ // and is encoded in the pipe. When the length is zero, neither -+ // transfer_buffer nor transfer_dma is used. -+ //actual_length This is read in non-iso completion functions, and it tells -+ // how many bytes (out of transfer_buffer_length) were transferred. -+ // It will normally be the same as requested, unless either an error -+ // was reported or a short read was performed. The URB_SHORT_NOT_OK -+ // transfer flag may be used to make such short reads be reported -+ // as errors. -+ //setup_packet Only used for control transfers, this points to eight bytes of -+ // setup data. Control transfers always start by sending this data -+ // to the device. Then transfer_buffer is read or written, if needed. -+ //setup_dma For control transfers with URB_NO_SETUP_DMA_MAP set, the device -+ // driver has provided this DMA address for the setup packet. The -+ // host controller driver should use this in preference to setup_packet. -+ //start_frame Returns the initial frame for isochronous transfers. -+ //number_of_packets Lists the number of ISO transfer buffers. -+ //interval Specifies the polling interval for interrupt or isochronous transfers. -+ // The units are frames (milliseconds) for for full and low speed devices, -+ // and microframes (1/8 millisecond) for highspeed ones. -+ //error_count Returns the number of ISO transfers that reported errors. -+ //context For use in completion functions. This normally points to request-specific -+ // driver context. -+ //complete Completion handler. This URB is passed as the parameter to the completion -+ // function. The completion function may then do what it likes with the URB, -+ // including resubmitting or freeing it. -+ //iso_frame_desc[0] Used to provide arrays of ISO transfer buffers and to collect the transfer -+ // status for each buffer. -+ -+ struct ifxhcd_epqh *epqh; -+ // Actual data portion, not SETUP or STATUS in case of CTRL XFER -+ // DMA adjusted -+ uint8_t *setup_buff; /*!< Pointer to the entire transfer buffer. (CPU accessable)*/ -+ uint8_t *xfer_buff; /*!< Pointer to the entire transfer buffer. (CPU accessable)*/ -+ uint32_t xfer_len; /*!< Total number of bytes to transfer in this xfer. */ -+ unsigned is_in :1; -+ unsigned is_active:1; -+ -+ // For ALL XFER -+ uint8_t error_count; /*!< Holds the number of bus errors that have occurred for a transaction -+ within this transfer. -+ */ -+ /*== AVM/BC 20101111 Needed for URB Complete List ==*/ -+ int status; -+ // For ISOC XFER only -+ #ifdef __EN_ISOC__ -+ int isoc_frame_index; /*!< Index of the next frame descriptor for an isochronous transfer. A -+ frame descriptor describes the buffer position and length of the -+ data to be transferred in the next scheduled (micro)frame of an -+ isochronous transfer. It also holds status for that transaction. -+ The frame index starts at 0. -+ */ -+ // For SPLITed ISOC XFER only -+ uint8_t isoc_split_pos; /*!< Position of the ISOC split on full/low speed */ -+ uint16_t isoc_split_offset;/*!< Position of the ISOC split in the buffer for the current frame */ -+ #endif -+} ifxhcd_urbd_t; -+ -+/*! -+ \brief A EP Queue Head (EPQH) holds the static characteristics of an endpoint and -+ maintains a list of transfers (URBDs) for that endpoint. A EPQH structure may -+ be entered in either the isoc, intr or non-periodic schedule. -+ */ -+ -+typedef struct ifxhcd_epqh { -+ struct list_head epqh_list_entry; // Hook for EP Queues -+ struct list_head urbd_list; /*!< List of URBDs for this EPQH. */ -+ struct ifxhcd_hc *hc; /*!< Host channel currently processing transfers for this EPQH. */ -+ struct ifxhcd_urbd *urbd; /*!< URBD currently assigned to a host channel for this EPQH. */ -+ struct usb_host_endpoint *sysep; -+ uint8_t ep_type; /*!< Endpoint type. One of the following values: -+ - IFXUSB_EP_TYPE_CTRL -+ - IFXUSB_EP_TYPE_ISOC -+ - IFXUSB_EP_TYPE_BULK -+ - IFXUSB_EP_TYPE_INTR -+ */ -+ uint16_t mps; /*!< wMaxPacketSize Field of Endpoint Descriptor. */ -+ -+ /* == AVM/WK 20100710 Fix - Use toggle of usbcore ==*/ -+ /*uint8_t data_toggle;*/ /*!< Determines the PID of the next data packet -+ One of the following values: -+ - IFXHCD_HC_PID_DATA0 -+ - IFXHCD_HC_PID_DATA1 -+ */ -+ uint8_t is_active; -+ -+ uint8_t pkt_count_limit; -+ #ifdef __EPQD_DESTROY_TIMEOUT__ -+ struct timer_list destroy_timer; -+ #endif -+ -+ uint16_t wait_for_sof; -+ uint8_t need_split; /*!< Full/low speed endpoint on high-speed hub requires split. */ -+ uint16_t interval; /*!< Interval between transfers in (micro)frames. (for INTR)*/ -+ -+ uint16_t period_counter; /*!< Interval between transfers in (micro)frames. */ -+ uint8_t period_do; -+ -+ uint8_t aligned_checked; -+ -+ #if defined(__UNALIGNED_BUFFER_ADJ__) -+ uint8_t using_aligned_setup; -+ uint8_t *aligned_setup; -+ uint8_t using_aligned_buf; -+ uint8_t *aligned_buf; -+ unsigned aligned_buf_len : 19; -+ #endif -+ -+ uint8_t *dump_buf; -+} ifxhcd_epqh_t; -+ -+ -+#if defined(__HC_XFER_TIMEOUT__) -+ struct ifxusb_core_if; -+ struct ifxhcd_hc; -+ typedef struct hc_xfer_info -+ { -+ struct ifxusb_core_if *core_if; -+ struct ifxhcd_hc *hc; -+ } hc_xfer_info_t; -+#endif //defined(__HC_XFER_TIMEOUT__) -+ -+ -+/*! -+ \brief Host channel descriptor. This structure represents the state of a single -+ host channel when acting in host mode. It contains the data items needed to -+ transfer packets to an endpoint via a host channel. -+ */ -+typedef struct ifxhcd_hc -+{ -+ struct list_head hc_list_entry ; // Hook to free hc -+ struct ifxhcd_epqh *epqh ; /*!< EP Queue Head for the transfer being processed by this channel. */ -+ -+ uint8_t hc_num ; /*!< Host channel number used for register address lookup */ -+ uint8_t *xfer_buff ; /*!< Pointer to the entire transfer buffer. */ -+ uint32_t xfer_count ; /*!< Number of bytes transferred so far. The offset of the begin of the buf */ -+ uint32_t xfer_len ; /*!< Total number of bytes to transfer in this xfer. */ -+ uint16_t start_pkt_count ; /*!< Packet count at start of transfer. Used to calculate the actual xfer size*/ -+ ifxhcd_halt_status_e halt_status; /*!< Reason for halting the host channel. */ -+ -+ unsigned dev_addr : 7; /*!< Device to access */ -+ unsigned ep_num : 4; /*!< EP to access */ -+ unsigned is_in : 1; /*!< EP direction. 0: OUT, 1: IN */ -+ unsigned speed : 2; /*!< EP speed. */ -+ unsigned ep_type : 2; /*!< Endpoint type. */ -+ unsigned mps :11; /*!< Max packet size in bytes */ -+ unsigned data_pid_start : 2; /*!< PID for initial transaction. */ -+ unsigned do_ping : 1; /*!< Set to 1 to indicate that a PING request should be issued on this -+ channel. If 0, process normally. -+ */ -+ -+ unsigned xfer_started : 1; /*!< Flag to indicate whether the transfer has been started. Set to 1 if -+ it has been started, 0 otherwise. -+ */ -+ unsigned halting : 1; /*!< Set to 1 if the host channel has been halted, but the core is not -+ finished flushing queued requests. Otherwise 0. -+ */ -+ unsigned short_rw : 1; /*!< When Tx, means termination needed. -+ When Rx, indicate Short Read */ -+ /* Split settings for the host channel */ -+ unsigned split : 2; /*!< Split: 0-Non Split, 1-SSPLIT, 2&3 CSPLIT */ -+ -+ /*== AVM/BC 20100701 - Workaround FullSpeed Interrupts with HiSpeed Hub ==*/ -+ unsigned nyet_count; -+ -+ /* nak monitor */ -+ unsigned nak_retry_r : 16; -+ unsigned nak_retry : 16; -+ #define nak_retry_max 40000 -+ unsigned nak_countdown : 8; -+ unsigned nak_countdown_r: 8; -+ #define nak_countdown_max 1 -+ -+ uint16_t wait_for_sof; -+ ifxhcd_control_phase_e control_phase; /*!< Current phase for control transfers (Setup, Data, or Status). */ -+ uint32_t ssplit_out_xfer_count; /*!< How many bytes transferred during SSPLIT OUT */ -+ #ifdef __DEBUG__ -+ uint32_t start_hcchar_val; -+ #endif -+ #ifdef __HC_XFER_TIMEOUT__ -+ hc_xfer_info_t hc_xfer_info; -+ struct timer_list hc_xfer_timer; -+ #endif -+ uint32_t hcchar; -+ -+ /* Split settings for the host channel */ -+ uint8_t hub_addr; /*!< Address of high speed hub */ -+ uint8_t port_addr; /*!< Port of the low/full speed device */ -+ #ifdef __EN_ISOC__ -+ uint8_t isoc_xact_pos; /*!< Split transaction position */ -+ #endif -+} ifxhcd_hc_t; -+ -+ -+/*! -+ \brief This structure holds the state of the HCD, including the non-periodic and -+ periodic schedules. -+ */ -+typedef struct ifxhcd_hcd -+{ -+ struct device *dev; -+ struct hc_driver hc_driver; -+ ifxusb_core_if_t core_if; /*!< Pointer to the core interface structure. */ -+ struct usb_hcd *syshcd; -+ -+ volatile union ifxhcd_internal_flags -+ { -+ uint32_t d32; -+ struct -+ { -+ unsigned port_connect_status_change : 1; -+ unsigned port_connect_status : 1; -+ unsigned port_reset_change : 1; -+ unsigned port_enable_change : 1; -+ unsigned port_suspend_change : 1; -+ unsigned port_over_current_change : 1; -+ unsigned reserved : 27; -+ } b; -+ } flags; /*!< Internal HCD Flags */ -+ -+ struct ifxhcd_hc ifxhc[MAX_EPS_CHANNELS]; /*!< Array of pointers to the host channel descriptors. Allows accessing -+ a host channel descriptor given the host channel number. This is -+ useful in interrupt handlers. -+ */ -+ struct list_head free_hc_list; /*!< Free host channels in the controller. This is a list of ifxhcd_hc_t items. */ -+ uint8_t *status_buf; /*!< Buffer to use for any data received during the status phase of a -+ control transfer. Normally no data is transferred during the status -+ phase. This buffer is used as a bit bucket. -+ */ -+ #define IFXHCD_STATUS_BUF_SIZE 64 -+ -+ struct list_head epqh_np_active; // with URBD, with HC -+ struct list_head epqh_np_ready; // with URBD, No HC -+ -+ struct list_head epqh_intr_active; // with URBD, with HC -+ struct list_head epqh_intr_ready; // with URBD, no pass, No HC -+ -+ #ifdef __EN_ISOC__ -+ struct list_head epqh_isoc_active; // with URBD, with HC -+ struct list_head epqh_isoc_ready; // with URBD, no pass, No HC -+ #endif -+ -+ /*== AVM/BC 20101111 URB Complete List ==*/ -+ struct list_head urbd_complete_list; -+ -+ struct list_head epqh_stdby; -+ -+ /* AVM/BC 20101111 flags removed */ -+ //unsigned process_channels_in_use : 1; -+ //unsigned select_eps_in_use : 1; -+ -+ struct tasklet_struct select_eps; /*!< Tasket to do a reset */ -+ uint32_t lastframe; -+ spinlock_t lock; -+#ifdef __USE_TIMER_4_SOF__ -+ struct hrtimer hr_timer; -+#endif -+} ifxhcd_hcd_t; -+ -+/* Gets the ifxhcd_hcd from a struct usb_hcd */ -+static inline ifxhcd_hcd_t *syshcd_to_ifxhcd(struct usb_hcd *syshcd) -+{ -+ return (ifxhcd_hcd_t *)(syshcd->hcd_priv[0]); -+} -+ -+/* Gets the struct usb_hcd that contains a ifxhcd_hcd_t. */ -+static inline struct usb_hcd *ifxhcd_to_syshcd(ifxhcd_hcd_t *ifxhcd) -+{ -+ return (struct usb_hcd *)(ifxhcd->syshcd); -+} -+ -+/*! \brief HCD Create/Destroy Functions */ -+/*@{*/ -+ extern int ifxhcd_init (ifxhcd_hcd_t *_ifxhcd); -+ extern void ifxhcd_remove(ifxhcd_hcd_t *_ifxhcd); -+/*@}*/ -+ -+/*! \brief Linux HC Driver API Functions */ -+/*@{*/ -+extern int ifxhcd_start(struct usb_hcd *hcd); -+extern void ifxhcd_stop (struct usb_hcd *hcd); -+extern int ifxhcd_get_frame_number(struct usb_hcd *hcd); -+ -+ -+/*! -+ \brief This function does the setup for a data transfer for a host channel and -+ starts the transfer. May be called in either Slave mode or DMA mode. In -+ Slave mode, the caller must ensure that there is sufficient space in the -+ request queue and Tx Data FIFO. -+ -+ For an OUT transfer in Slave mode, it loads a data packet into the -+ appropriate FIFO. If necessary, additional data packets will be loaded in -+ the Host ISR. -+ -+ For an IN transfer in Slave mode, a data packet is requested. The data -+ packets are unloaded from the Rx FIFO in the Host ISR. If necessary, -+ additional data packets are requested in the Host ISR. -+ -+ For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ -+ register along with a packet count of 1 and the channel is enabled. This -+ causes a single PING transaction to occur. Other fields in HCTSIZ are -+ simply set to 0 since no data transfer occurs in this case. -+ -+ For a PING transfer in DMA mode, the HCTSIZ register is initialized with -+ all the information required to perform the subsequent data transfer. In -+ addition, the Do Ping bit is set in the HCTSIZ register. In this case, the -+ controller performs the entire PING protocol, then starts the data -+ transfer. -+ -+ @param _ifxhc Information needed to initialize the host channel. The xfer_len -+ value may be reduced to accommodate the max widths of the XferSize and -+ PktCnt fields in the HCTSIZn register. The multi_count value may be changed -+ to reflect the final xfer_len value. -+ */ -+extern void ifxhcd_hc_start(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc); -+ -+//extern int ifxhcd_urb_enqueue(struct usb_hcd *_syshcd, struct usb_host_endpoint *_sysep, struct urb *_urb, gfp_t mem_flags); -+//extern int ifxhcd_urb_dequeue(struct usb_hcd *_syshcd, struct urb *_urb); -+extern irqreturn_t ifxhcd_irq(struct usb_hcd *_syshcd); -+int ifxhcd_urb_enqueue( struct usb_hcd *_syshcd, -+ /*--- struct usb_host_endpoint *_sysep, Parameter im 2.6.28 entfallen ---*/ -+ struct urb *_urb, -+ gfp_t _mem_flags); -+int ifxhcd_urb_dequeue( struct usb_hcd *_syshcd, -+ struct urb *_urb, int status /* Parameter neu in 2.6.28 */); -+ -+extern void ifxhcd_endpoint_disable(struct usb_hcd *_syshcd, struct usb_host_endpoint *_sysep); -+ -+extern int ifxhcd_hub_status_data(struct usb_hcd *_syshcd, char *_buf); -+extern int ifxhcd_hub_control( struct usb_hcd *_syshcd, -+ u16 _typeReq, -+ u16 _wValue, -+ u16 _wIndex, -+ char *_buf, -+ u16 _wLength); -+ -+/*@}*/ -+ -+/*! \brief Transaction Execution Functions */ -+/*@{*/ -+extern void ifxhcd_complete_urb (ifxhcd_hcd_t *_ifxhcd, ifxhcd_urbd_t *_urbd, int _status); -+ -+/*@}*/ -+ -+/*! \brief Deferred Transaction Execution Functions */ -+/*@{*/ -+ -+/*== AVM/BC 20101111 URB Complete List ==*/ -+extern void defer_ifxhcd_complete_urb (ifxhcd_hcd_t *_ifxhcd, ifxhcd_urbd_t *_urbd, int _status); -+ -+/*! -+ \brief Clears the transfer state for a host channel. This function is normally -+ called after a transfer is done and the host channel is being released. -+ */ -+extern void ifxhcd_hc_cleanup(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc); -+ -+/*! -+ \brief Attempts to halt a host channel. This function should only be called in -+ Slave mode or to abort a transfer in either Slave mode or DMA mode. Under -+ normal circumstances in DMA mode, the controller halts the channel when the -+ transfer is complete or a condition occurs that requires application -+ intervention. -+ -+ In slave mode, checks for a free request queue entry, then sets the Channel -+ Enable and Channel Disable bits of the Host Channel Characteristics -+ register of the specified channel to intiate the halt. If there is no free -+ request queue entry, sets only the Channel Disable bit of the HCCHARn -+ register to flush requests for this channel. In the latter case, sets a -+ flag to indicate that the host channel needs to be halted when a request -+ queue slot is open. -+ -+ In DMA mode, always sets the Channel Enable and Channel Disable bits of the -+ HCCHARn register. The controller ensures there is space in the request -+ queue before submitting the halt request. -+ -+ Some time may elapse before the core flushes any posted requests for this -+ host channel and halts. The Channel Halted interrupt handler completes the -+ deactivation of the host channel. -+ */ -+extern void ifxhcd_hc_halt(ifxusb_core_if_t *_core_if, -+ ifxhcd_hc_t *_ifxhc, -+ ifxhcd_halt_status_e _halt_status); -+ -+/*! -+ \brief Prepares a host channel for transferring packets to/from a specific -+ endpoint. The HCCHARn register is set up with the characteristics specified -+ in _ifxhc. Host channel interrupts that may need to be serviced while this -+ transfer is in progress are enabled. -+ */ -+extern void ifxhcd_hc_init(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc); -+ -+/*! -+ \brief This function is called to handle the disconnection of host port. -+ */ -+int32_t ifxhcd_disconnect(ifxhcd_hcd_t *_ifxhcd); -+/*@}*/ -+ -+/*! \brief Interrupt Handler Functions */ -+/*@{*/ -+extern irqreturn_t ifxhcd_oc_irq(int _irq, void *_dev); -+ -+extern int32_t ifxhcd_handle_oc_intr(ifxhcd_hcd_t *_ifxhcd); -+extern int32_t ifxhcd_handle_intr (ifxhcd_hcd_t *_ifxhcd); -+/*@}*/ -+ -+ -+/*! \brief Schedule Queue Functions */ -+/*@{*/ -+extern ifxhcd_epqh_t *ifxhcd_epqh_create (ifxhcd_hcd_t *_ifxhcd, struct urb *_urb); -+extern void ifxhcd_epqh_free ( ifxhcd_epqh_t *_epqh); -+extern void select_eps (ifxhcd_hcd_t *_ifxhcd); -+extern void process_channels(ifxhcd_hcd_t *_ifxhcd); -+extern void process_channels_sub(ifxhcd_hcd_t *_ifxhcd); -+extern void complete_channel(ifxhcd_hcd_t *_ifxhcd, ifxhcd_hc_t *_ifxhc, ifxhcd_urbd_t *_urbd); -+extern void ifxhcd_epqh_ready(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh); -+extern void ifxhcd_epqh_active(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh); -+extern void ifxhcd_epqh_idle(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh); -+extern void ifxhcd_epqh_idle_periodic(ifxhcd_epqh_t *_epqh); -+extern int ifxhcd_urbd_create (ifxhcd_hcd_t *_ifxhcd,struct urb *_urb); -+/*@}*/ -+ -+/*! \brief Gets the usb_host_endpoint associated with an URB. */ -+static inline struct usb_host_endpoint *ifxhcd_urb_to_endpoint(struct urb *_urb) -+{ -+ struct usb_device *dev = _urb->dev; -+ int ep_num = usb_pipeendpoint(_urb->pipe); -+ -+ return (usb_pipein(_urb->pipe))?(dev->ep_in[ep_num]):(dev->ep_out[ep_num]); -+} -+ -+/*! -+ * \brief Gets the endpoint number from a _bEndpointAddress argument. The endpoint is -+ * qualified with its direction (possible 32 endpoints per device). -+ */ -+#define ifxhcd_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \ -+ ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4) -+ -+ -+/* AVM/WK: not needed? -+ -+extern struct usb_device *usb_alloc_dev (struct usb_device *parent, struct usb_bus *, unsigned port); -+extern int usb_add_hcd (struct usb_hcd *syshcd, unsigned int irqnum, unsigned long irqflags); -+extern void usb_remove_hcd (struct usb_hcd *syshcd); -+extern struct usb_hcd *usb_create_hcd (const struct hc_driver *driver, struct device *dev, char *bus_name); -+extern void usb_hcd_giveback_urb (struct usb_hcd *syshcd, struct urb *urb); -+extern void usb_put_hcd (struct usb_hcd *syshcd); -+extern long usb_calc_bus_time (int speed, int is_input, int isoc, int bytecount); -+ -+*/ -+/** Internal Functions */ -+void ifxhcd_dump_state(ifxhcd_hcd_t *_ifxhcd); -+extern char *syserr(int errno); -+ -+/*@}*//*IFXUSB_HCD*/ -+ -+#endif // __IFXHCD_H__ ---- /dev/null -+++ b/drivers/usb/ifxhcd/ifxhcd_es.c -@@ -0,0 +1,549 @@ -+/***************************************************************************** -+ ** FILE NAME : ifxhcd_es.c -+ ** PROJECT : IFX USB sub-system V3 -+ ** MODULES : IFX USB sub-system Host and Device driver -+ ** SRC VERSION : 1.0 -+ ** DATE : 1/Jan/2009 -+ ** AUTHOR : Chen, Howard -+ ** DESCRIPTION : The file contain function to enable host mode USB-IF Electrical Test function. -+ *****************************************************************************/ -+ -+/*! -+ \file ifxhcd_es.c -+ \ingroup IFXUSB_DRIVER_V3 -+ \brief The file contain function to enable host mode USB-IF Electrical Test function. -+*/ -+ -+#include -+#include "ifxusb_version.h" -+ -+#include -+ -+#include -+ -+#include -+ -+#include "ifxusb_plat.h" -+#include "ifxusb_regs.h" -+#include "ifxusb_cif.h" -+#include "ifxhcd.h" -+ -+ -+#ifdef __WITH_HS_ELECT_TST__ -+ /* -+ * Quick and dirty hack to implement the HS Electrical Test -+ * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature. -+ * -+ * This code was copied from our userspace app "hset". It sends a -+ * Get Device Descriptor control sequence in two parts, first the -+ * Setup packet by itself, followed some time later by the In and -+ * Ack packets. Rather than trying to figure out how to add this -+ * functionality to the normal driver code, we just hijack the -+ * hardware, using these two function to drive the hardware -+ * directly. -+ */ -+ -+ -+ void do_setup(ifxusb_core_if_t *_core_if) -+ { -+ -+ ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; -+ ifxusb_host_global_regs_t *hc_global_regs = _core_if->host_global_regs; -+ ifxusb_hc_regs_t *hc_regs = _core_if->hc_regs[0]; -+ uint32_t *data_fifo = _core_if->data_fifo[0]; -+ -+ gint_data_t gintsts; -+ hctsiz_data_t hctsiz; -+ hcchar_data_t hcchar; -+ haint_data_t haint; -+ hcint_data_t hcint; -+ -+ -+ /* Enable HAINTs */ -+ ifxusb_wreg(&hc_global_regs->haintmsk, 0x0001); -+ -+ /* Enable HCINTs */ -+ ifxusb_wreg(&hc_regs->hcintmsk, 0x04a3); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+ -+ /* Read HAINT */ -+ haint.d32 = ifxusb_rreg(&hc_global_regs->haint); -+ //fprintf(stderr, "HAINT: %08x\n", haint.d32); -+ -+ /* Read HCINT */ -+ hcint.d32 = ifxusb_rreg(&hc_regs->hcint); -+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); -+ -+ /* Clear HCINT */ -+ ifxusb_wreg(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ ifxusb_wreg(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ ifxusb_wreg(&global_regs->gintsts, gintsts.d32); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+ -+ /* -+ * Send Setup packet (Get Device Descriptor) -+ */ -+ -+ /* Make sure channel is disabled */ -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ if (hcchar.b.chen) { -+ //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32); -+ hcchar.b.chdis = 1; -+ // hcchar.b.chen = 1; -+ ifxusb_wreg(&hc_regs->hcchar, hcchar.d32); -+ //sleep(1); -+ mdelay(1000); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+ -+ /* Read HAINT */ -+ haint.d32 = ifxusb_rreg(&hc_global_regs->haint); -+ //fprintf(stderr, "HAINT: %08x\n", haint.d32); -+ -+ /* Read HCINT */ -+ hcint.d32 = ifxusb_rreg(&hc_regs->hcint); -+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); -+ -+ /* Clear HCINT */ -+ ifxusb_wreg(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ ifxusb_wreg(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ ifxusb_wreg(&global_regs->gintsts, gintsts.d32); -+ -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ //if (hcchar.b.chen) { -+ // fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32); -+ //} -+ } -+ -+ /* Set HCTSIZ */ -+ hctsiz.d32 = 0; -+ hctsiz.b.xfersize = 8; -+ hctsiz.b.pktcnt = 1; -+ hctsiz.b.pid = IFXUSB_HC_PID_SETUP; -+ ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32); -+ -+ /* Set HCCHAR */ -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ hcchar.b.eptype = IFXUSB_EP_TYPE_CTRL; -+ hcchar.b.epdir = 0; -+ hcchar.b.epnum = 0; -+ hcchar.b.mps = 8; -+ hcchar.b.chen = 1; -+ ifxusb_wreg(&hc_regs->hcchar, hcchar.d32); -+ -+ /* Fill FIFO with Setup data for Get Device Descriptor */ -+ ifxusb_wreg(data_fifo++, 0x01000680); -+ ifxusb_wreg(data_fifo++, 0x00080000); -+ -+ gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); -+ //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32); -+ -+ /* Wait for host channel interrupt */ -+ do { -+ gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); -+ } while (gintsts.b.hcintr == 0); -+ -+ //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32); -+ -+ /* Disable HCINTs */ -+ ifxusb_wreg(&hc_regs->hcintmsk, 0x0000); -+ -+ /* Disable HAINTs */ -+ ifxusb_wreg(&hc_global_regs->haintmsk, 0x0000); -+ -+ /* Read HAINT */ -+ haint.d32 = ifxusb_rreg(&hc_global_regs->haint); -+ //fprintf(stderr, "HAINT: %08x\n", haint.d32); -+ -+ /* Read HCINT */ -+ hcint.d32 = ifxusb_rreg(&hc_regs->hcint); -+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); -+ -+ /* Clear HCINT */ -+ ifxusb_wreg(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ ifxusb_wreg(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ ifxusb_wreg(&global_regs->gintsts, gintsts.d32); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+ } -+ -+ void do_in_ack(ifxusb_core_if_t *_core_if) -+ { -+ -+ ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; -+ ifxusb_host_global_regs_t *hc_global_regs = _core_if->host_global_regs; -+ ifxusb_hc_regs_t *hc_regs = _core_if->hc_regs[0]; -+ uint32_t *data_fifo = _core_if->data_fifo[0]; -+ -+ gint_data_t gintsts; -+ hctsiz_data_t hctsiz; -+ hcchar_data_t hcchar; -+ haint_data_t haint; -+ hcint_data_t hcint; -+ grxsts_data_t grxsts; -+ -+ /* Enable HAINTs */ -+ ifxusb_wreg(&hc_global_regs->haintmsk, 0x0001); -+ -+ /* Enable HCINTs */ -+ ifxusb_wreg(&hc_regs->hcintmsk, 0x04a3); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+ -+ /* Read HAINT */ -+ haint.d32 = ifxusb_rreg(&hc_global_regs->haint); -+ //fprintf(stderr, "HAINT: %08x\n", haint.d32); -+ -+ /* Read HCINT */ -+ hcint.d32 = ifxusb_rreg(&hc_regs->hcint); -+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); -+ -+ /* Clear HCINT */ -+ ifxusb_wreg(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ ifxusb_wreg(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ ifxusb_wreg(&global_regs->gintsts, gintsts.d32); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+ -+ /* -+ * Receive Control In packet -+ */ -+ -+ /* Make sure channel is disabled */ -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ if (hcchar.b.chen) { -+ //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32); -+ hcchar.b.chdis = 1; -+ hcchar.b.chen = 1; -+ ifxusb_wreg(&hc_regs->hcchar, hcchar.d32); -+ //sleep(1); -+ mdelay(1000); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+ -+ /* Read HAINT */ -+ haint.d32 = ifxusb_rreg(&hc_global_regs->haint); -+ //fprintf(stderr, "HAINT: %08x\n", haint.d32); -+ -+ /* Read HCINT */ -+ hcint.d32 = ifxusb_rreg(&hc_regs->hcint); -+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); -+ -+ /* Clear HCINT */ -+ ifxusb_wreg(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ ifxusb_wreg(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ ifxusb_wreg(&global_regs->gintsts, gintsts.d32); -+ -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ //if (hcchar.b.chen) { -+ // fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32); -+ //} -+ } -+ -+ /* Set HCTSIZ */ -+ hctsiz.d32 = 0; -+ hctsiz.b.xfersize = 8; -+ hctsiz.b.pktcnt = 1; -+ hctsiz.b.pid = IFXUSB_HC_PID_DATA1; -+ ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32); -+ -+ /* Set HCCHAR */ -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ hcchar.b.eptype = IFXUSB_EP_TYPE_CTRL; -+ hcchar.b.epdir = 1; -+ hcchar.b.epnum = 0; -+ hcchar.b.mps = 8; -+ hcchar.b.chen = 1; -+ ifxusb_wreg(&hc_regs->hcchar, hcchar.d32); -+ -+ gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); -+ //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32); -+ -+ /* Wait for receive status queue interrupt */ -+ do { -+ gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); -+ } while (gintsts.b.rxstsqlvl == 0); -+ -+ //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32); -+ -+ /* Read RXSTS */ -+ grxsts.d32 = ifxusb_rreg(&global_regs->grxstsp); -+ //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32); -+ -+ /* Clear RXSTSQLVL in GINTSTS */ -+ gintsts.d32 = 0; -+ gintsts.b.rxstsqlvl = 1; -+ ifxusb_wreg(&global_regs->gintsts, gintsts.d32); -+ -+ switch (grxsts.hb.pktsts) { -+ case IFXUSB_HSTS_DATA_UPDT: -+ /* Read the data into the host buffer */ -+ if (grxsts.hb.bcnt > 0) { -+ int i; -+ int word_count = (grxsts.hb.bcnt + 3) / 4; -+ -+ for (i = 0; i < word_count; i++) { -+ (void)ifxusb_rreg(data_fifo++); -+ } -+ } -+ -+ //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.hb.bcnt); -+ break; -+ -+ default: -+ //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n"); -+ break; -+ } -+ -+ gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); -+ //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32); -+ -+ /* Wait for receive status queue interrupt */ -+ do { -+ gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); -+ } while (gintsts.b.rxstsqlvl == 0); -+ -+ //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32); -+ -+ /* Read RXSTS */ -+ grxsts.d32 = ifxusb_rreg(&global_regs->grxstsp); -+ //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32); -+ -+ /* Clear RXSTSQLVL in GINTSTS */ -+ gintsts.d32 = 0; -+ gintsts.b.rxstsqlvl = 1; -+ ifxusb_wreg(&global_regs->gintsts, gintsts.d32); -+ -+ switch (grxsts.hb.pktsts) { -+ case IFXUSB_HSTS_XFER_COMP: -+ break; -+ -+ default: -+ //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n"); -+ break; -+ } -+ -+ gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); -+ //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32); -+ -+ /* Wait for host channel interrupt */ -+ do { -+ gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); -+ } while (gintsts.b.hcintr == 0); -+ -+ //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32); -+ -+ /* Read HAINT */ -+ haint.d32 = ifxusb_rreg(&hc_global_regs->haint); -+ //fprintf(stderr, "HAINT: %08x\n", haint.d32); -+ -+ /* Read HCINT */ -+ hcint.d32 = ifxusb_rreg(&hc_regs->hcint); -+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); -+ -+ /* Clear HCINT */ -+ ifxusb_wreg(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ ifxusb_wreg(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ ifxusb_wreg(&global_regs->gintsts, gintsts.d32); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+ -+ // usleep(100000); -+ // mdelay(100); -+ mdelay(1); -+ -+ /* -+ * Send handshake packet -+ */ -+ -+ /* Read HAINT */ -+ haint.d32 = ifxusb_rreg(&hc_global_regs->haint); -+ //fprintf(stderr, "HAINT: %08x\n", haint.d32); -+ -+ /* Read HCINT */ -+ hcint.d32 = ifxusb_rreg(&hc_regs->hcint); -+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); -+ -+ /* Clear HCINT */ -+ ifxusb_wreg(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ ifxusb_wreg(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ ifxusb_wreg(&global_regs->gintsts, gintsts.d32); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+ -+ /* Make sure channel is disabled */ -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ if (hcchar.b.chen) { -+ //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32); -+ hcchar.b.chdis = 1; -+ hcchar.b.chen = 1; -+ ifxusb_wreg(&hc_regs->hcchar, hcchar.d32); -+ //sleep(1); -+ mdelay(1000); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+ -+ /* Read HAINT */ -+ haint.d32 = ifxusb_rreg(&hc_global_regs->haint); -+ //fprintf(stderr, "HAINT: %08x\n", haint.d32); -+ -+ /* Read HCINT */ -+ hcint.d32 = ifxusb_rreg(&hc_regs->hcint); -+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); -+ -+ /* Clear HCINT */ -+ ifxusb_wreg(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ ifxusb_wreg(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ ifxusb_wreg(&global_regs->gintsts, gintsts.d32); -+ -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ //if (hcchar.b.chen) { -+ // fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32); -+ //} -+ } -+ -+ /* Set HCTSIZ */ -+ hctsiz.d32 = 0; -+ hctsiz.b.xfersize = 0; -+ hctsiz.b.pktcnt = 1; -+ hctsiz.b.pid = IFXUSB_HC_PID_DATA1; -+ ifxusb_wreg(&hc_regs->hctsiz, hctsiz.d32); -+ -+ /* Set HCCHAR */ -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ hcchar.b.eptype = IFXUSB_EP_TYPE_CTRL; -+ hcchar.b.epdir = 0; -+ hcchar.b.epnum = 0; -+ hcchar.b.mps = 8; -+ hcchar.b.chen = 1; -+ ifxusb_wreg(&hc_regs->hcchar, hcchar.d32); -+ -+ gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); -+ //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32); -+ -+ /* Wait for host channel interrupt */ -+ do { -+ gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); -+ } while (gintsts.b.hcintr == 0); -+ -+ //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32); -+ -+ /* Disable HCINTs */ -+ ifxusb_wreg(&hc_regs->hcintmsk, 0x0000); -+ -+ /* Disable HAINTs */ -+ ifxusb_wreg(&hc_global_regs->haintmsk, 0x0000); -+ -+ /* Read HAINT */ -+ haint.d32 = ifxusb_rreg(&hc_global_regs->haint); -+ //fprintf(stderr, "HAINT: %08x\n", haint.d32); -+ -+ /* Read HCINT */ -+ hcint.d32 = ifxusb_rreg(&hc_regs->hcint); -+ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); -+ -+ /* Read HCCHAR */ -+ hcchar.d32 = ifxusb_rreg(&hc_regs->hcchar); -+ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); -+ -+ /* Clear HCINT */ -+ ifxusb_wreg(&hc_regs->hcint, hcint.d32); -+ -+ /* Clear HAINT */ -+ ifxusb_wreg(&hc_global_regs->haint, haint.d32); -+ -+ /* Clear GINTSTS */ -+ ifxusb_wreg(&global_regs->gintsts, gintsts.d32); -+ -+ /* Read GINTSTS */ -+ gintsts.d32 = ifxusb_rreg(&global_regs->gintsts); -+ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); -+ } -+#endif //__WITH_HS_ELECT_TST__ -+ ---- /dev/null -+++ b/drivers/usb/ifxhcd/ifxhcd_intr.c -@@ -0,0 +1,3742 @@ -+/***************************************************************************** -+ ** FILE NAME : ifxhcd_intr.c -+ ** PROJECT : IFX USB sub-system V3 -+ ** MODULES : IFX USB sub-system Host and Device driver -+ ** SRC VERSION : 1.0 -+ ** DATE : 1/Jan/2009 -+ ** AUTHOR : Chen, Howard -+ ** DESCRIPTION : This file contains the implementation of the HCD Interrupt handlers. -+ *****************************************************************************/ -+ -+/*! -+ \file ifxhcd_intr.c -+ \ingroup IFXUSB_DRIVER_V3 -+ \brief This file contains the implementation of the HCD Interrupt handlers. -+*/ -+ -+ -+#include -+#include "ifxusb_version.h" -+ -+#include "ifxusb_plat.h" -+#include "ifxusb_regs.h" -+#include "ifxusb_cif.h" -+ -+#include "ifxhcd.h" -+ -+/* AVM/WK 20100520*/ -+#ifdef __EN_ISOC__ -+#error AVM/WK: CONFIG_USB_HOST_IFX_WITH_ISO currently not supported! -+#endif -+ -+/* Macro used to clear one channel interrupt */ -+#define clear_hc_int(_hc_regs_,_intr_) \ -+ do { \ -+ hcint_data_t hcint_clear = {.d32 = 0}; \ -+ hcint_clear.b._intr_ = 1; \ -+ ifxusb_wreg(&((_hc_regs_)->hcint), hcint_clear.d32); \ -+ } while (0) -+ -+/* -+ * Macro used to disable one channel interrupt. Channel interrupts are -+ * disabled when the channel is halted or released by the interrupt handler. -+ * There is no need to handle further interrupts of that type until the -+ * channel is re-assigned. In fact, subsequent handling may cause crashes -+ * because the channel structures are cleaned up when the channel is released. -+ */ -+#define disable_hc_int(_hc_regs_,_intr_) \ -+ do { \ -+ hcint_data_t hcintmsk = {.d32 = 0}; \ -+ hcintmsk.b._intr_ = 1; \ -+ ifxusb_mreg(&((_hc_regs_)->hcintmsk), hcintmsk.d32, 0); \ -+ } while (0) -+ -+#define enable_hc_int(_hc_regs_,_intr_) \ -+ do { \ -+ hcint_data_t hcintmsk = {.d32 = 0}; \ -+ hcintmsk.b._intr_ = 1; \ -+ ifxusb_mreg(&((_hc_regs_)->hcintmsk),0, hcintmsk.d32); \ -+ } while (0) -+ -+/* -+ * Save the starting data toggle for the next transfer. The data toggle is -+ * saved in the QH for non-control transfers and it's saved in the QTD for -+ * control transfers. -+ */ -+uint8_t read_data_toggle(ifxusb_hc_regs_t *_hc_regs) -+{ -+ hctsiz_data_t hctsiz; -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ return(hctsiz.b.pid); -+} -+ -+ -+static void release_channel_dump(ifxhcd_hc_t *ifxhc, -+ struct urb *urb, -+ ifxhcd_epqh_t *epqh, -+ ifxhcd_urbd_t *urbd, -+ ifxhcd_halt_status_e halt_status) -+{ -+ #ifdef __DEBUG__ -+ printk(KERN_INFO); -+ switch (halt_status) -+ { -+ case HC_XFER_NO_HALT_STATUS: -+ printk("HC_XFER_NO_HALT_STATUS");break; -+ case HC_XFER_URB_COMPLETE: -+ printk("HC_XFER_URB_COMPLETE");break; -+ case HC_XFER_AHB_ERR: -+ printk("HC_XFER_AHB_ERR");break; -+ case HC_XFER_STALL: -+ printk("HC_XFER_STALL");break; -+ case HC_XFER_BABBLE_ERR: -+ printk("HC_XFER_BABBLE_ERR");break; -+ case HC_XFER_XACT_ERR: -+ printk("HC_XFER_XACT_ERR");break; -+ case HC_XFER_URB_DEQUEUE: -+ printk("HC_XFER_URB_DEQUEUE");break; -+ case HC_XFER_FRAME_OVERRUN: -+ printk("HC_XFER_FRAME_OVERRUN");break; -+ case HC_XFER_DATA_TOGGLE_ERR: -+ printk("HC_XFER_DATA_TOGGLE_ERR");break; -+ case HC_XFER_NAK: -+ printk("HC_XFER_NAK");break; -+ case HC_XFER_COMPLETE: -+ printk("HC_XFER_COMPLETE");break; -+ default: -+ printk("KNOWN");break; -+ } -+ if(ifxhc) -+ printk("Ch %d %s%s S%d " , ifxhc->hc_num -+ ,(ifxhc->ep_type == IFXUSB_EP_TYPE_CTRL)?"CTRL-": -+ ((ifxhc->ep_type == IFXUSB_EP_TYPE_BULK)?"BULK-": -+ ((ifxhc->ep_type == IFXUSB_EP_TYPE_INTR)?"INTR-": -+ ((ifxhc->ep_type == IFXUSB_EP_TYPE_ISOC)?"ISOC-":"????" -+ ) -+ ) -+ ) -+ ,(ifxhc->is_in)?"IN":"OUT" -+ ,(ifxhc->split) -+ ); -+ else -+ printk(" [NULL HC] "); -+ printk("urb=%p epqh=%p urbd=%p\n",urb,epqh,urbd); -+ -+ if(urb) -+ { -+ printk(KERN_INFO " Device address: %d\n", usb_pipedevice(urb->pipe)); -+ printk(KERN_INFO " Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe), -+ (usb_pipein(urb->pipe) ? "IN" : "OUT")); -+ printk(KERN_INFO " Endpoint type: %s\n", -+ ({char *pipetype; -+ switch (usb_pipetype(urb->pipe)) { -+ case PIPE_CONTROL: pipetype = "CTRL"; break; -+ case PIPE_BULK: pipetype = "BULK"; break; -+ case PIPE_INTERRUPT: pipetype = "INTR"; break; -+ case PIPE_ISOCHRONOUS: pipetype = "ISOC"; break; -+ default: pipetype = "????"; break; -+ }; pipetype;})); -+ printk(KERN_INFO " Speed: %s\n", -+ ({char *speed; -+ switch (urb->dev->speed) { -+ case USB_SPEED_HIGH: speed = "HS"; break; -+ case USB_SPEED_FULL: speed = "FS"; break; -+ case USB_SPEED_LOW: speed = "LS"; break; -+ default: speed = "????"; break; -+ }; speed;})); -+ printk(KERN_INFO " Max packet size: %d\n", -+ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); -+ printk(KERN_INFO " Data buffer length: %d\n", urb->transfer_buffer_length); -+ printk(KERN_INFO " Transfer buffer: %p, Transfer DMA: %p\n", -+ urb->transfer_buffer, (void *)urb->transfer_dma); -+ printk(KERN_INFO " Setup buffer: %p, Setup DMA: %p\n", -+ urb->setup_packet, (void *)urb->setup_dma); -+ printk(KERN_INFO " Interval: %d\n", urb->interval); -+ switch (urb->status) -+ { -+ case HC_XFER_NO_HALT_STATUS: -+ printk(KERN_INFO " STATUS:HC_XFER_NO_HALT_STATUS\n");break; -+ case HC_XFER_URB_COMPLETE: -+ printk(KERN_INFO " STATUS:HC_XFER_URB_COMPLETE\n");break; -+ case HC_XFER_AHB_ERR: -+ printk(KERN_INFO " STATUS:HC_XFER_AHB_ERR\n");break; -+ case HC_XFER_STALL: -+ printk(KERN_INFO " STATUS:HC_XFER_STALL\n");break; -+ case HC_XFER_BABBLE_ERR: -+ printk(KERN_INFO " STATUS:HC_XFER_BABBLE_ERR\n");break; -+ case HC_XFER_XACT_ERR: -+ printk(KERN_INFO " STATUS:HC_XFER_XACT_ERR\n");break; -+ case HC_XFER_URB_DEQUEUE: -+ printk(KERN_INFO " STATUS:HC_XFER_URB_DEQUEUE\n");break; -+ case HC_XFER_FRAME_OVERRUN: -+ printk(KERN_INFO " STATUS:HC_XFER_FRAME_OVERRUN\n");break; -+ case HC_XFER_DATA_TOGGLE_ERR: -+ printk(KERN_INFO " STATUS:HC_XFER_DATA_TOGGLE_ERR\n");break; -+ case HC_XFER_COMPLETE: -+ printk(KERN_INFO " STATUS:HC_XFER_COMPLETE\n");break; -+ default: -+ printk(KERN_INFO " STATUS:KNOWN\n");break; -+ } -+ } -+ #endif -+} -+ -+ -+static void release_channel(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxhcd_halt_status_e _halt_status) -+{ -+ ifxusb_hc_regs_t *hc_regs = _ifxhcd->core_if.hc_regs[_ifxhc->hc_num]; -+ struct urb *urb = NULL; -+ ifxhcd_epqh_t *epqh = NULL; -+ ifxhcd_urbd_t *urbd = NULL; -+ -+ IFX_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d\n", -+ __func__, _ifxhc->hc_num, _halt_status); -+ -+ epqh=_ifxhc->epqh; -+ -+ if(!epqh) -+ IFX_ERROR("%s epqh=null\n",__func__); -+ else -+ { -+ urbd=epqh->urbd; -+ if(!urbd) -+ IFX_ERROR("%s urbd=null\n",__func__); -+ else -+ { -+ urb=urbd->urb; -+ if(!urb) -+ IFX_ERROR("%s urb =null\n",__func__); -+ else { -+ /* == AVM/WK 20100710 Fix - Use toggle of usbcore ==*/ -+ unsigned toggle = (read_data_toggle(hc_regs) == IFXUSB_HC_PID_DATA0)? 0: 1; -+ usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe), usb_pipeout(urb->pipe), toggle); -+ } -+ } -+ //epqh->data_toggle = read_data_toggle(hc_regs); -+ -+ } -+ -+ switch (_halt_status) -+ { -+ case HC_XFER_NO_HALT_STATUS: -+ IFX_ERROR("%s: No halt_status, channel %d\n", __func__, _ifxhc->hc_num); -+ break; -+ case HC_XFER_COMPLETE: -+ IFX_ERROR("%s: Inavalid halt_status HC_XFER_COMPLETE, channel %d\n", __func__, _ifxhc->hc_num); -+ break; -+ case HC_XFER_URB_COMPLETE: -+ case HC_XFER_URB_DEQUEUE: -+ case HC_XFER_AHB_ERR: -+ case HC_XFER_XACT_ERR: -+ case HC_XFER_FRAME_OVERRUN: -+ if(urbd && urb) { -+ /* == 20110803 AVM/WK FIX set status, if still in progress == */ -+ if (urb->status == -EINPROGRESS) { -+ switch (_halt_status) { -+ case HC_XFER_URB_COMPLETE: -+ urb->status = 0; -+ break; -+ case HC_XFER_URB_DEQUEUE: -+ urb->status = -ECONNRESET; -+ break; -+ case HC_XFER_AHB_ERR: -+ case HC_XFER_XACT_ERR: -+ case HC_XFER_FRAME_OVERRUN: -+ urb->status = -EPROTO; -+ break; -+ default: -+ break; -+ } -+ } -+ /*== AVM/BC 20101111 Deferred Complete ==*/ -+ defer_ifxhcd_complete_urb(_ifxhcd, urbd, urb->status); -+ } -+ else -+ { -+ IFX_WARN("WARNING %s():%d urbd=%p urb=%p\n",__func__,__LINE__,urbd,urb); -+ release_channel_dump(_ifxhc,urb,epqh,urbd,_halt_status); -+ } -+ if(epqh) -+ ifxhcd_epqh_idle(_ifxhcd, epqh); -+ else -+ { -+ IFX_WARN("WARNING %s():%d epqh=%p\n",__func__,__LINE__,epqh); -+ release_channel_dump(_ifxhc,urb,epqh,urbd,_halt_status); -+ } -+ -+ list_add_tail(&_ifxhc->hc_list_entry, &_ifxhcd->free_hc_list); -+ ifxhcd_hc_cleanup(&_ifxhcd->core_if, _ifxhc); -+ break; -+ case HC_XFER_STALL: -+ release_channel_dump(_ifxhc,urb,epqh,urbd,_halt_status); -+ if(urbd) -+ /*== AVM/BC 20101111 Deferred Complete ==*/ -+ defer_ifxhcd_complete_urb(_ifxhcd, urbd, -EPIPE); -+ else -+ IFX_WARN("WARNING %s():%d urbd=%p urb=%p\n",__func__,__LINE__,urbd,urb); -+ if(epqh) -+ { -+// epqh->data_toggle = 0; -+ ifxhcd_epqh_idle(_ifxhcd, epqh); -+ } -+ else -+ IFX_WARN("WARNING %s():%d epqh=%p\n",__func__,__LINE__,epqh); -+ list_add_tail(&_ifxhc->hc_list_entry, &_ifxhcd->free_hc_list); -+ ifxhcd_hc_cleanup(&_ifxhcd->core_if, _ifxhc); -+ break; -+ case HC_XFER_NAK: -+ release_channel_dump(_ifxhc,urb,epqh,urbd,_halt_status); -+ if(urbd) -+ { -+ //ifxhcd_complete_urb(_ifxhcd, urbd, -ETIMEDOUT); -+ urb->status = 0; -+ /*== AVM/BC 20101111 Deferred Complete ==*/ -+ defer_ifxhcd_complete_urb(_ifxhcd, urbd, urb->status); -+ } -+ else -+ IFX_WARN("WARNING %s():%d urbd=%p urb=%p\n",__func__,__LINE__,urbd,urb); -+ if(epqh) -+ ifxhcd_epqh_idle(_ifxhcd, epqh); -+ else -+ IFX_WARN("WARNING %s():%d epqh=%p\n",__func__,__LINE__,epqh); -+ list_add_tail(&_ifxhc->hc_list_entry, &_ifxhcd->free_hc_list); -+ ifxhcd_hc_cleanup(&_ifxhcd->core_if, _ifxhc); -+ break; -+ case HC_XFER_BABBLE_ERR: -+ case HC_XFER_DATA_TOGGLE_ERR: -+ release_channel_dump(_ifxhc,urb,epqh,urbd,_halt_status); -+ if(urbd) -+ /*== AVM/BC 20101111 Deferred Complete ==*/ -+ defer_ifxhcd_complete_urb(_ifxhcd, urbd, -EOVERFLOW); -+ else -+ IFX_WARN("WARNING %s():%d urbd=%p urb=%p\n",__func__,__LINE__,urbd,urb); -+ if(epqh) -+ ifxhcd_epqh_idle(_ifxhcd, epqh); -+ else -+ IFX_WARN("WARNING %s():%d epqh=%p\n",__func__,__LINE__,epqh); -+ list_add_tail(&_ifxhc->hc_list_entry, &_ifxhcd->free_hc_list); -+ ifxhcd_hc_cleanup(&_ifxhcd->core_if, _ifxhc); -+ break; -+ } -+ select_eps(_ifxhcd); -+} -+ -+/* -+ * Updates the state of the URB after a Transfer Complete interrupt on the -+ * host channel. Updates the actual_length field of the URB based on the -+ * number of bytes transferred via the host channel. Sets the URB status -+ * if the data transfer is finished. -+ * -+ * @return 1 if the data transfer specified by the URB is completely finished, -+ * 0 otherwise. -+ */ -+static int update_urb_state_xfer_comp(ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ struct urb *_urb, -+ ifxhcd_urbd_t *_urbd) -+{ -+ int xfer_done = 0; -+ -+ if (_ifxhc->is_in) -+ { -+ hctsiz_data_t hctsiz; -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ _urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); -+ if ((hctsiz.b.xfersize != 0) || (_urb->actual_length >= _urb->transfer_buffer_length)) -+ { -+ xfer_done = 1; -+ _urb->status = 0; -+ /* 20110805 AVM/WK Workaround: catch overflow error here, hardware does not */ -+ if (_urb->actual_length > _urb->transfer_buffer_length) { -+ _urb->status = -EOVERFLOW; -+ } -+ #if 0 -+ if (_urb->actual_length < _urb->transfer_buffer_length && _urb->transfer_flags & URB_SHORT_NOT_OK) -+ _urb->status = -EREMOTEIO; -+ #endif -+ } -+ -+ } -+ else -+ { -+ if (_ifxhc->split) -+ _urb->actual_length += _ifxhc->ssplit_out_xfer_count; -+ else -+ _urb->actual_length += _ifxhc->xfer_len; -+ -+ if (_urb->actual_length >= _urb->transfer_buffer_length) -+ { -+ /*== AVM/BC WK 20110421 ZERO PACKET Workaround ==*/ -+ if ((_ifxhc->short_rw == 1) && ( _ifxhc->xfer_len > 0) && ( _ifxhc->xfer_len % _ifxhc->mps == 0 )) -+ { -+ _ifxhc->short_rw = 0; -+ //Transfer not finished. Another iteration for ZLP. -+ } -+ else -+ { -+ xfer_done = 1; -+ } -+ _urb->status = 0; -+ } -+ } -+ -+ #ifdef __DEBUG__ -+ { -+ hctsiz_data_t hctsiz; -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ IFX_DEBUGPL(DBG_HCDV, "IFXUSB: %s: %s, channel %d\n", -+ __func__, (_ifxhc->is_in ? "IN" : "OUT"), _ifxhc->hc_num); -+ IFX_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", _ifxhc->xfer_len); -+ IFX_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n", hctsiz.b.xfersize); -+ IFX_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n", -+ _urb->transfer_buffer_length); -+ IFX_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", _urb->actual_length); -+ } -+ #endif -+ return xfer_done; -+} -+ -+/*== AVM/BC 20101111 Function called with Lock ==*/ -+ -+void complete_channel(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxhcd_urbd_t *_urbd) -+{ -+ ifxusb_hc_regs_t *hc_regs = _ifxhcd->core_if.hc_regs[_ifxhc->hc_num]; -+ struct urb *urb = NULL; -+ ifxhcd_epqh_t *epqh = NULL; -+ int urb_xfer_done; -+ -+ IFX_DEBUGPL(DBG_HCD, "--Complete Channel %d : \n", _ifxhc->hc_num); -+ -+ if(!_urbd) -+ { -+ IFX_ERROR("ERROR %s():%d urbd=%p\n",__func__,__LINE__,_urbd); -+ return; -+ } -+ -+ urb = _urbd->urb; -+ epqh = _urbd->epqh; -+ -+ if(!urb || !epqh) -+ { -+ IFX_ERROR("ERROR %s():%d urb=%p epqh=%p\n",__func__,__LINE__,urb,epqh); -+ return; -+ } -+ -+ _ifxhc->do_ping=0; -+ -+ if (_ifxhc->split) -+ _ifxhc->split = 1; -+ -+ switch (epqh->ep_type) -+ { -+ case IFXUSB_EP_TYPE_CTRL: -+ switch (_ifxhc->control_phase) -+ { -+ case IFXHCD_CONTROL_SETUP: -+ IFX_DEBUGPL(DBG_HCDV, " Control setup transaction done\n"); -+ if (_urbd->xfer_len > 0) -+ { -+ _ifxhc->control_phase = IFXHCD_CONTROL_DATA; -+ _ifxhc->is_in = _urbd->is_in; -+ _ifxhc->xfer_len = _urbd->xfer_len; -+ #if defined(__UNALIGNED_BUFFER_ADJ__) -+ if(epqh->using_aligned_buf) -+ _ifxhc->xfer_buff = epqh->aligned_buf; -+ else -+ #endif -+ _ifxhc->xfer_buff = _urbd->xfer_buff; -+ } -+ else -+ { -+ _ifxhc->control_phase = IFXHCD_CONTROL_STATUS; -+ _ifxhc->is_in = 1; -+ _ifxhc->xfer_len = 0; -+ _ifxhc->xfer_buff = _ifxhcd->status_buf; -+ } -+ if(_ifxhc->is_in) -+ _ifxhc->short_rw =0; -+ else -+ _ifxhc->short_rw =(urb->transfer_flags & URB_ZERO_PACKET)?1:0; -+ _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1; -+ _ifxhc->xfer_count = 0; -+ _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; -+ /*== AVM/BC 20101111 Lock not needed ==*/ -+ process_channels_sub(_ifxhcd); -+ break; -+ case IFXHCD_CONTROL_DATA: -+ urb_xfer_done = update_urb_state_xfer_comp(_ifxhc, hc_regs, urb, _urbd); -+ if (urb_xfer_done) -+ { -+ _ifxhc->control_phase = IFXHCD_CONTROL_STATUS; -+ _ifxhc->is_in = (_urbd->is_in)?0:1; -+ _ifxhc->xfer_len = 0; -+ _ifxhc->xfer_count = 0; -+ _ifxhc->xfer_buff = _ifxhcd->status_buf; -+ _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; -+ _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1; -+ if(_ifxhc->is_in) -+ _ifxhc->short_rw =0; -+ else -+ _ifxhc->short_rw =1; -+ } -+ else // continue -+ { -+ _ifxhc->xfer_len = _urbd->xfer_len - urb->actual_length; -+ _ifxhc->xfer_count = urb->actual_length; -+ _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; -+ _ifxhc->data_pid_start = read_data_toggle(hc_regs); -+ } -+ /*== AVM/BC 20101111 Lock not needed ==*/ -+ process_channels_sub(_ifxhcd); -+ break; -+ case IFXHCD_CONTROL_STATUS: -+ if (urb->status == -EINPROGRESS) -+ urb->status = 0; -+ release_channel(_ifxhcd,_ifxhc,HC_XFER_URB_COMPLETE); -+ break; -+ } -+ break; -+ case IFXUSB_EP_TYPE_BULK: -+ IFX_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n"); -+ urb_xfer_done = update_urb_state_xfer_comp(_ifxhc, hc_regs, urb, _urbd); -+ if (urb_xfer_done) -+ release_channel(_ifxhcd,_ifxhc,HC_XFER_URB_COMPLETE); -+ else -+ { -+ _ifxhc->xfer_len = _urbd->xfer_len - urb->actual_length; -+ _ifxhc->xfer_count = urb->actual_length; -+ _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; -+ _ifxhc->data_pid_start = read_data_toggle(hc_regs); -+ /*== AVM/BC 20101111 Lock not needed ==*/ -+ process_channels_sub(_ifxhcd); -+ } -+ break; -+ case IFXUSB_EP_TYPE_INTR: -+ urb_xfer_done = update_urb_state_xfer_comp(_ifxhc, hc_regs, urb, _urbd); -+ release_channel(_ifxhcd,_ifxhc,HC_XFER_URB_COMPLETE); -+ break; -+ case IFXUSB_EP_TYPE_ISOC: -+// if (_urbd->isoc_split_pos == IFXUSB_HCSPLIT_XACTPOS_ALL) -+// halt_status = update_isoc_urb_state(_ifxhcd, _ifxhc, hc_regs, _urbd, HC_XFER_COMPLETE); -+// complete_periodic_xfer(_ifxhcd, _ifxhc, hc_regs, _urbd, halt_status); -+ urb_xfer_done = update_urb_state_xfer_comp(_ifxhc, hc_regs, urb, _urbd); -+ release_channel(_ifxhcd,_ifxhc,HC_XFER_URB_COMPLETE); -+ break; -+ } -+} -+ -+ -+ -+void showint(uint32_t val_hcint -+ ,uint32_t val_hcintmsk -+ ,uint32_t val_hctsiz) -+{ -+#ifdef __DEBUG__ -+ hcint_data_t hcint = {.d32 = val_hcint}; -+ hcint_data_t hcintmsk = {.d32 = val_hcintmsk}; -+ -+ printk(KERN_INFO " WITH FLAG: Sz:%08x I:%08X/M:%08X %s%s%s%s%s%s%s%s%s%s\n" -+ ,val_hctsiz,hcint.d32 ,hcintmsk.d32 -+ ,(hcint.b.datatglerr || hcintmsk.b.datatglerr)? -+ ( -+ (hcint.b.datatglerr && hcintmsk.b.datatglerr)?"datatglerr[*/*] ": -+ ( -+ (hcint.b.datatglerr)?"datatglerr[*/] ":"datatglerr[/*] " -+ ) -+ ) -+ :"" -+ ,(hcint.b.frmovrun || hcintmsk.b.frmovrun)? -+ ( -+ (hcint.b.frmovrun && hcintmsk.b.frmovrun)?"frmovrun[*/*] ": -+ ( -+ (hcint.b.frmovrun)?"frmovrun[*/] ":"frmovrun[/*] " -+ ) -+ ) -+ :"" -+ ,(hcint.b.bblerr || hcintmsk.b.bblerr)? -+ ( -+ (hcint.b.bblerr && hcintmsk.b.bblerr)?"bblerr[*/*] ": -+ ( -+ (hcint.b.bblerr)?"bblerr[*/] ":"bblerr[/*] " -+ ) -+ ) -+ :"" -+ ,(hcint.b.xacterr || hcintmsk.b.xacterr)? -+ ( -+ (hcint.b.xacterr && hcintmsk.b.xacterr)?"xacterr[*/*] ": -+ ( -+ (hcint.b.xacterr)?"xacterr[*/] ":"xacterr[/*] " -+ ) -+ ) -+ :"" -+ ,(hcint.b.nyet || hcintmsk.b.nyet)? -+ ( -+ (hcint.b.nyet && hcintmsk.b.nyet)?"nyet[*/*] ": -+ ( -+ (hcint.b.nyet)?"nyet[*/] ":"nyet[/*] " -+ ) -+ ) -+ :"" -+ ,(hcint.b.nak || hcintmsk.b.nak)? -+ ( -+ (hcint.b.nak && hcintmsk.b.nak)?"nak[*/*] ": -+ ( -+ (hcint.b.nak)?"nak[*/] ":"nak[/*] " -+ ) -+ ) -+ :"" -+ ,(hcint.b.ack || hcintmsk.b.ack)? -+ ( -+ (hcint.b.ack && hcintmsk.b.ack)?"ack[*/*] ": -+ ( -+ (hcint.b.ack)?"ack[*/] ":"ack[/*] " -+ ) -+ ) -+ :"" -+ ,(hcint.b.stall || hcintmsk.b.stall)? -+ ( -+ (hcint.b.stall && hcintmsk.b.stall)?"stall[*/*] ": -+ ( -+ (hcint.b.stall)?"stall[*/] ":"stall[/*] " -+ ) -+ ) -+ :"" -+ ,(hcint.b.ahberr || hcintmsk.b.ahberr)? -+ ( -+ (hcint.b.ahberr && hcintmsk.b.ahberr)?"ahberr[*/*] ": -+ ( -+ (hcint.b.ahberr)?"ahberr[*/] ":"ahberr[/*] " -+ ) -+ ) -+ :"" -+ ,(hcint.b.xfercomp || hcintmsk.b.xfercomp)? -+ ( -+ (hcint.b.xfercomp && hcintmsk.b.xfercomp)?"xfercomp[*/*] ": -+ ( -+ (hcint.b.xfercomp)?"xfercomp[*/] ":"xfercomp[/*] " -+ ) -+ ) -+ :"" -+ ); -+#endif -+} -+ -+ -+extern void ifxhcd_hc_dumb_rx(ifxusb_core_if_t *_core_if, ifxhcd_hc_t *_ifxhc,uint8_t *dump_buf); -+ -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+static int32_t chhltd_ctrlbulk_rx_nonsplit(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ hcint_data_t hcint; -+ hcint_data_t hcintmsk; -+ hctsiz_data_t hctsiz; -+ -+ hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); -+ hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nak); -+ disable_hc_int(_hc_regs,nyet); -+ _ifxhc->do_ping = 0; -+ -+ if(_ifxhc->halt_status == HC_XFER_NAK) -+ { -+ if(_ifxhc->nak_retry_r) -+ { -+ _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); -+ _ifxhc->nak_retry--; -+ if(_ifxhc->nak_retry) -+ { -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ _ifxhc->data_pid_start = read_data_toggle(_hc_regs); -+ _ifxhc->wait_for_sof = 1; -+ _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ else -+ { -+ _ifxhc->wait_for_sof = 0; -+ release_channel(_ifxhcd, _ifxhc, _ifxhc->halt_status); -+ } -+ } -+ else -+ { -+ _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ _ifxhc->data_pid_start = read_data_toggle(_hc_regs); -+ _ifxhc->wait_for_sof = 1; -+ _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ return 1; -+ } -+ -+ if (hcint.b.xfercomp) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ return 1; -+ } -+ else if (hcint.b.stall) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ // ZLP shortcut -+ #if 0 -+ if(hctsiz.b.pktcnt==0) -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ else -+ #endif -+ { -+ // Stall FIFO compensation. -+ #if 0 -+ int sz1,sz2; -+ sz2=_ifxhc->start_pkt_count - hctsiz.b.pktcnt; -+ sz2*=_ifxhc->mps; -+ sz1=_ifxhc->xfer_len - hctsiz.b.xfersize; -+ sz2-=sz1; -+ if(sz2) -+ ifxhcd_hc_dumb_rx(&_ifxhcd->core_if, _ifxhc,_ifxhc->epqh->dump_buf); -+ #endif -+ _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); -+ } -+ return 1; -+ } -+ else if (hcint.b.bblerr) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ -+ // ZLP shortcut -+ #if 0 -+ if(hctsiz.b.pktcnt==0) -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ else -+ #endif -+ _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); -+ return 1; -+ } -+ else if (hcint.b.xacterr) -+ { -+ // ZLP shortcut -+ #if 1 -+ if(hctsiz.b.pktcnt==0) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ } -+ else -+ #endif -+ { -+ _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ _ifxhc->data_pid_start = read_data_toggle(_hc_regs); -+ -+ /* 20110803 AVM/WK FIX: Reset error count on any handshake */ -+ if (hcint.b.nak || hcint.b.nyet || hcint.b.ack) { -+ _urbd->error_count = 1; -+ } else { -+ _urbd->error_count++; -+ } -+ -+ if (_urbd->error_count >= 3) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); -+ } -+ else -+ { -+ _ifxhc->wait_for_sof = 1; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ } -+ return 1; -+ } -+ else if(hcint.b.datatglerr ) -+ { -+ _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); -+ #if 1 -+ if(_ifxhc->data_pid_start == IFXUSB_HC_PID_DATA0) -+ _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1; -+ else -+ _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0; -+ _ifxhc->wait_for_sof = 1; -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ #else -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_DATA_TOGGLE_ERR); -+ #endif -+ return 1; -+ } -+ else if(hcint.b.frmovrun ) -+ { -+IFX_WARN("%s() %d Warning CTRLBULK IN SPLIT0 FRMOVRUN [should be Period only]\n",__func__,__LINE__); -+showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN); -+ return 1; -+ } -+ else if(hcint.b.nyet ) -+ { -+IFX_WARN("%s() %d Warning CTRLBULK IN SPLIT0 NYET [should be Out only]\n",__func__,__LINE__); -+showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ } -+ return 0; -+} -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+static int32_t chhltd_ctrlbulk_tx_nonsplit(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ hcint_data_t hcint; -+ hcint_data_t hcintmsk; -+ hctsiz_data_t hctsiz; -+ int out_nak_enh = 0; -+ -+#ifdef __DEBUG__ -+static int first=0; -+#endif -+ -+ if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH) -+ out_nak_enh = 1; -+ -+ hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); -+ hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ -+#ifdef __DEBUG__ -+if(!first&& _ifxhc->ep_type == IFXUSB_EP_TYPE_BULK -+ &&(hcint.b.stall || hcint.b.datatglerr || hcint.b.frmovrun || hcint.b.bblerr || hcint.b.xacterr) && !hcint.b.ack) -+{ -+ showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ first=1; -+ printk(KERN_INFO " [%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X] \n" -+ ,*(_ifxhc->xfer_buff+ 0),*(_ifxhc->xfer_buff+ 1),*(_ifxhc->xfer_buff+ 2),*(_ifxhc->xfer_buff+ 3) -+ ,*(_ifxhc->xfer_buff+ 4),*(_ifxhc->xfer_buff+ 5),*(_ifxhc->xfer_buff+ 6),*(_ifxhc->xfer_buff+ 7) -+ ,*(_ifxhc->xfer_buff+ 8),*(_ifxhc->xfer_buff+ 9),*(_ifxhc->xfer_buff+10),*(_ifxhc->xfer_buff+11) -+ ,*(_ifxhc->xfer_buff+12),*(_ifxhc->xfer_buff+13),*(_ifxhc->xfer_buff+14),*(_ifxhc->xfer_buff+15)); -+ -+ printk(KERN_INFO " [_urbd->urb->actual_length:%08X _ifxhc->start_pkt_count:%08X hctsiz.b.pktcnt:%08X ,_urbd->xfer_len:%08x] \n" -+ ,_urbd->urb->actual_length -+ ,_ifxhc->start_pkt_count -+ ,hctsiz.b.pktcnt -+ ,_urbd->xfer_len); -+} -+#endif -+ -+ if(_ifxhc->halt_status == HC_XFER_NAK) -+ { -+ if(_ifxhc->nak_retry_r) -+ { -+ _ifxhc->nak_retry--; -+ if(_ifxhc->nak_retry) -+ { -+ if(_ifxhc->xfer_len!=0) -+ _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ _ifxhc->data_pid_start = read_data_toggle(_hc_regs); -+ _ifxhc->wait_for_sof = 1; -+ _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ else -+ { -+ _ifxhc->wait_for_sof = 0; -+ release_channel(_ifxhcd, _ifxhc, _ifxhc->halt_status); -+ } -+ } -+ else -+ { -+ if(_ifxhc->xfer_len!=0) -+ _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ _ifxhc->data_pid_start = read_data_toggle(_hc_regs); -+ _ifxhc->wait_for_sof = 1; -+ _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ return 1; -+ } -+ -+ if (hcint.b.xfercomp) -+ { -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nak); -+ disable_hc_int(_hc_regs,nyet); -+ _urbd->error_count =0; -+ if(_ifxhc->xfer_len==0 && !hcint.b.ack && hcint.b.nak) -+ { -+ // Walkaround: When sending ZLP and receive NAK but also issue CMPT intr -+ // Solution: NoSplit: Resend at next SOF -+ // Split : Resend at next SOF with SSPLIT -+ if(hcint.b.nyet && !out_nak_enh) -+ _ifxhc->do_ping = 1; -+ else -+ _ifxhc->do_ping = 0; -+ _ifxhc->xfer_len = 0; -+ _ifxhc->xfer_count = 0; -+ _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; -+ _ifxhc->wait_for_sof = 1; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ else -+ { -+ _ifxhc->wait_for_sof = 0; -+ _ifxhc->do_ping = 0; -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ } -+ return 1; -+ } -+ else if (hcint.b.stall) -+ { -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nak); -+ disable_hc_int(_hc_regs,nyet); -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ _ifxhc->do_ping =0; -+ -+ // ZLP shortcut -+ #if 1 -+ if(hctsiz.b.pktcnt==0) -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ else -+ #endif -+ { -+ if(_ifxhc->xfer_len!=0) -+ _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); -+ } -+ return 1; -+ } -+ else if (hcint.b.xacterr) -+ { -+ // ZLP shortcut -+ #if 1 -+ if(hctsiz.b.pktcnt==0) -+ { -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nak); -+ disable_hc_int(_hc_regs,nyet); -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ _ifxhc->do_ping =0; -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ } -+ else -+ #endif -+ { -+ if(_ifxhc->xfer_len!=0) -+ _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ _ifxhc->data_pid_start = read_data_toggle(_hc_regs); -+ -+ if (hcint.b.nak || hcint.b.nyet || hcint.b.ack) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =1; -+ enable_hc_int(_hc_regs,ack); -+ enable_hc_int(_hc_regs,nak); -+ enable_hc_int(_hc_regs,nyet); -+ if(!out_nak_enh) -+ _ifxhc->do_ping =1; -+ else -+ _ifxhc->do_ping =0; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ else -+ { -+ _urbd->error_count ++ ; -+ if (_urbd->error_count == 3) -+ { -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nak); -+ disable_hc_int(_hc_regs,nyet); -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ _ifxhc->do_ping =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); -+ } -+ else -+ { -+ enable_hc_int(_hc_regs,ack); -+ enable_hc_int(_hc_regs,nak); -+ enable_hc_int(_hc_regs,nyet); -+ _ifxhc->wait_for_sof =1; -+ if(!out_nak_enh) -+ _ifxhc->do_ping =1; -+ else -+ _ifxhc->do_ping =0; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ } -+ } -+ return 1; -+ } -+ else if(hcint.b.bblerr ) -+ { -+IFX_WARN("%s() %d Warning CTRLBULK OUT SPLIT0 BABBLE [should be IN only]\n",__func__,__LINE__); -+showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ _ifxhc->do_ping = 0; -+ if(_ifxhc->xfer_len!=0) -+ _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); -+ return 1; -+ } -+ else if(hcint.b.nak || hcint.b.nyet) -+ { -+ if(!out_nak_enh) -+ { -+ // ZLP shortcut -+ #if 1 -+ if(hctsiz.b.pktcnt==0) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ _ifxhc->do_ping =0; -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ } -+ else -+ #endif -+ { -+ if(!out_nak_enh) -+ _ifxhc->do_ping =1; -+ else -+ _ifxhc->do_ping =0; -+ if(_ifxhc->xfer_len!=0) -+ { -+ _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ } -+ _ifxhc->data_pid_start = read_data_toggle(_hc_regs); -+ _ifxhc->wait_for_sof = 1; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ return 1; -+ } -+ } -+ else if(hcint.b.datatglerr ) -+ { -+IFX_WARN("%s() %d Warning CTRLBULK OUT SPLIT0 DATATGLERR [should be IN only]\n",__func__,__LINE__); -+showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ _ifxhc->do_ping =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_DATA_TOGGLE_ERR); -+ return 1; -+ } -+ else if(hcint.b.frmovrun ) -+ { -+IFX_WARN("%s() %d Warning CTRLBULK OUT SPLIT0 FRMOVRUN [should be PERIODIC only]\n",__func__,__LINE__); -+showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ _ifxhc->do_ping =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN); -+ return 1; -+ } -+ return 0; -+} -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+static int32_t chhltd_intr_rx_nonsplit(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ hcint_data_t hcint; -+ hcint_data_t hcintmsk; -+ hctsiz_data_t hctsiz; -+ -+ hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); -+ hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nak); -+ disable_hc_int(_hc_regs,nyet); -+ _ifxhc->do_ping =0; -+ -+ if(_ifxhc->halt_status == HC_XFER_NAK) -+ { -+ if(_ifxhc->nak_retry_r) -+ { -+ _ifxhc->nak_retry--; -+ if(_ifxhc->nak_retry) -+ { -+ if(_ifxhc->xfer_len!=0) -+ _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ _ifxhc->data_pid_start = read_data_toggle(_hc_regs); -+ _ifxhc->wait_for_sof = 1; -+ _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ else -+ { -+ _ifxhc->wait_for_sof = 0; -+ release_channel(_ifxhcd, _ifxhc, _ifxhc->halt_status); -+ } -+ } -+ else -+ { -+ if(_ifxhc->xfer_len!=0) -+ _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ _ifxhc->data_pid_start = read_data_toggle(_hc_regs); -+ _ifxhc->wait_for_sof = 1; -+ _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ return 1; -+ } -+ -+ if(hcint.b.xfercomp ) -+ { -+ _urbd->error_count =0; -+ //restart INTR immediately -+ #if 1 -+ if(hctsiz.b.pktcnt>0) -+ { -+ // TODO Re-initialize Channel (in next b_interval - 1 uF/F) -+ _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; -+ if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ else -+ #endif -+ { -+ _ifxhc->wait_for_sof =0; -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ } -+ return 1; -+ } -+ else if (hcint.b.stall) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ -+ // Don't care shortcut -+ #if 0 -+ if(hctsiz.b.pktcnt==0) -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ else -+ #endif -+ { -+ // Stall FIFO compensation. -+ #if 0 -+ int sz1,sz2; -+ sz2=_ifxhc->start_pkt_count - hctsiz.b.pktcnt; -+ sz2*=_ifxhc->mps; -+ sz1=_ifxhc->xfer_len - hctsiz.b.xfersize; -+ sz2-=sz1; -+ if(sz2) -+ ifxhcd_hc_dumb_rx(&_ifxhcd->core_if, _ifxhc,_ifxhc->epqh->dump_buf); -+ #endif -+ _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); -+ } -+ return 1; -+ } -+ -+ -+ else if (hcint.b.bblerr) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ -+ // Don't care shortcut -+ #if 0 -+ if(hctsiz.b.pktcnt==0) -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ else -+ #endif -+ { -+ _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); -+ } -+ return 1; -+ } -+ else if (hcint.b.nak || hcint.b.datatglerr || hcint.b.frmovrun) -+ { -+ _urbd->error_count =0; -+ //restart INTR immediately -+ #if 1 -+ if(hctsiz.b.pktcnt>0) -+ { -+ // TODO Re-initialize Channel (in next b_interval - 1 uF/F) -+ _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; -+ if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ else -+ #endif -+ { -+ _ifxhc->wait_for_sof =0; -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ } -+ return 1; -+ } -+ else if (hcint.b.xacterr) -+ { -+ // ZLP shortcut -+ #if 1 -+ if(hctsiz.b.pktcnt==0) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ } -+ else -+ #endif -+ { -+ /* 20110803 AVM/WK FIX: Reset error count on any handshake */ -+ if (hcint.b.nak || hcint.b.nyet || hcint.b.ack) { -+ _urbd->error_count = 1; -+ } else { -+ _urbd->error_count++; -+ } -+ -+ if(_urbd->error_count>=3) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); -+ } -+ else -+ { -+ _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ } -+ return 1; -+ } -+ else if(hcint.b.nyet ) -+ { -+IFX_WARN("%s() %d Warning INTR IN SPLIT0 NYET [should be OUT only]\n",__func__,__LINE__); -+showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ return 1; -+ } -+ return 0; -+} -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+static int32_t chhltd_intr_tx_nonsplit(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ hcint_data_t hcint; -+ hcint_data_t hcintmsk; -+ hctsiz_data_t hctsiz; -+ int out_nak_enh = 0; -+ -+ if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH) -+ out_nak_enh = 1; -+ -+ hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); -+ hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ -+ if(_ifxhc->halt_status == HC_XFER_NAK) -+ { -+ if(_ifxhc->nak_retry_r) -+ { -+ _ifxhc->nak_retry--; -+ if(_ifxhc->nak_retry) -+ { -+ if(_ifxhc->xfer_len!=0) -+ _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ _ifxhc->data_pid_start = read_data_toggle(_hc_regs); -+ _ifxhc->wait_for_sof = 1; -+ _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ else -+ { -+ _ifxhc->wait_for_sof = 0; -+ release_channel(_ifxhcd, _ifxhc, _ifxhc->halt_status); -+ } -+ } -+ else -+ { -+ if(_ifxhc->xfer_len!=0) -+ _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ _ifxhc->data_pid_start = read_data_toggle(_hc_regs); -+ _ifxhc->wait_for_sof = 1; -+ _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ return 1; -+ } -+ -+ if(hcint.b.xfercomp ) -+ { -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nak); -+ disable_hc_int(_hc_regs,nyet); -+ _urbd->error_count =0; -+ //restart INTR immediately -+ #if 0 -+ if(hctsiz.b.pktcnt>0) -+ { -+ // TODO Re-initialize Channel (in next b_interval - 1 uF/F) -+ _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; -+ if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; -+ if(hcint.b.nyet && !out_nak_enh ) -+ _ifxhc->do_ping =1; -+ else -+ _ifxhc->do_ping =0; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ else -+ #endif -+ { -+ _ifxhc->wait_for_sof =0; -+ _ifxhc->do_ping =0; -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ } -+ return 1; -+ } -+ else if (hcint.b.stall) -+ { -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nyet); -+ disable_hc_int(_hc_regs,nak); -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ _ifxhc->do_ping =0; -+ -+ // Don't care shortcut -+ #if 0 -+ if(hctsiz.b.pktcnt==0) -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ else -+ #endif -+ { -+ if(_ifxhc->xfer_len!=0)// !_ifxhc->is_in -+ _urbd->urb->actual_length += ((_ifxhc->start_pkt_count - hctsiz.b.pktcnt ) * _ifxhc->mps); -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); -+ } -+ return 1; -+ } -+ else if(hcint.b.nak || hcint.b.frmovrun ) -+ { -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nyet); -+ disable_hc_int(_hc_regs,nak); -+ _urbd->error_count =0; -+ //restart INTR immediately -+ #if 0 -+ if(hctsiz.b.pktcnt>0) -+ { -+ // TODO Re-initialize Channel (in next b_interval - 1 uF/F) -+ _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; -+ if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; -+ if(!out_nak_enh ) -+ _ifxhc->do_ping =1; -+ else -+ _ifxhc->do_ping =0; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ else -+ #endif -+ { -+ _ifxhc->wait_for_sof =0; -+ _ifxhc->do_ping =0; -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ } -+ return 1; -+ } -+ else if(hcint.b.xacterr ) -+ { -+ // ZLP shortcut -+ #if 1 -+ if(hctsiz.b.pktcnt==0) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ _ifxhc->do_ping =0; -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ } -+ else -+ #endif -+ { -+ /* 20110803 AVM/WK FIX: Reset error count on any handshake */ -+ if (hcint.b.nak || hcint.b.nyet || hcint.b.ack) { -+ _urbd->error_count = 1; -+ } else { -+ _urbd->error_count++; -+ } -+ -+ if(_urbd->error_count>=3) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ _ifxhc->do_ping =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); -+ } -+ else -+ { -+ //_ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; -+ //if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; -+ _ifxhc->wait_for_sof=1; -+ if(!out_nak_enh ) -+ _ifxhc->do_ping =1; -+ else -+ _ifxhc->do_ping =0; -+ -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ } -+ return 1; -+ } -+ else if(hcint.b.bblerr ) -+ { -+IFX_WARN("%s() %d Warning INTR OUT SPLIT0 BABBLEERR [should be IN only]\n",__func__,__LINE__); -+showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ _ifxhc->do_ping =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); -+ return 1; -+ } -+ else if(hcint.b.datatglerr ) -+ { -+IFX_WARN("%s() %d Warning INTR OUT SPLIT0 DATATGLERR\n",__func__,__LINE__); -+showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ _ifxhc->do_ping =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_DATA_TOGGLE_ERR); -+ return 1; -+ } -+ return 0; -+} -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+static int32_t chhltd_isoc_rx_nonsplit(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ #if defined(__EN_ISOC__) -+ hcint_data_t hcint; -+ hcint_data_t hcintmsk; -+ hctsiz_data_t hctsiz; -+ -+ hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); -+ hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ -+ if (hcint.b.xfercomp || hcint.b.frmovrun) -+ { -+ _urbd->error_count=0; -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nak); -+ disable_hc_int(_hc_regs,nyet); -+ _ifxhc->wait_for_sof = 0; -+ if (hcint.b.xfercomp) -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ else -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN); -+ } -+ else if (hcint.b.xacterr || hcint.b.bblerr) -+ { -+ #ifndef VR9Skip -+ if(hctsiz.b.pktcnt==0) -+ { -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ } -+ else -+ { -+ int sz1,sz2; -+ sz2=_ifxhc->start_pkt_count - hctsiz.b.pktcnt; -+ sz2*=_ifxhc->mps; -+ sz1=_ifxhc->xfer_len - hctsiz.b.xfersize; -+ sz2-=sz1; -+ if(sz2) -+ ifxhcd_hc_dumb_rx(&_ifxhcd->core_if, _ifxhc,_ifxhc->epqh->dump_buf); -+ _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ _ifxhc->data_pid_start = read_data_toggle(_hc_regs); -+ _urbd->error_count++; -+ if(_urbd->error_count>=3) -+ { -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof = 0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); -+ } -+ else -+ { -+ _ifxhc->wait_for_sof = 1; -+ enable_hc_int(_hc_regs,ack); -+ enable_hc_int(_hc_regs,nak); -+ enable_hc_int(_hc_regs,nyet); -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ } -+ #endif -+ } -+ else if(hcint.b.datatglerr ) -+ { -+ warning -+ } -+ else if(hcint.b.stall ) -+ { -+ warning -+ } -+ #else -+ #endif -+ return 0; -+} -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+static int32_t chhltd_isoc_tx_nonsplit(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ #if defined(__EN_ISOC__) -+ hcint_data_t hcint; -+ hcint_data_t hcintmsk; -+ hctsiz_data_t hctsiz; -+ int out_nak_enh = 0; -+ -+ if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH) -+ out_nak_enh = 1; -+ -+ hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); -+ hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ -+ if (hcint.b.xfercomp) -+ { -+ _urbd->error_count=0; -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nak); -+ disable_hc_int(_hc_regs,nyet); -+ _ifxhc->wait_for_sof = 0; -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ return 1; -+ } -+ else if (hcint.b.frmovrun) -+ { -+ #ifndef VR9Skip -+ _urbd->error_count=0; -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nak); -+ disable_hc_int(_hc_regs,nyet); -+ _ifxhc->wait_for_sof = 0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN); -+ #endif -+ } -+ else if(hcint.b.datatglerr ) -+ { -+ warning -+ } -+ else if(hcint.b.bblerr ) -+ { -+ #ifndef VR9Skip -+ if(hctsiz.b.pktcnt==0) -+ { -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ } -+ else -+ { -+ int sz1,sz2; -+ sz2=_ifxhc->start_pkt_count - hctsiz.b.pktcnt; -+ sz2*=_ifxhc->mps; -+ sz1=_ifxhc->xfer_len - hctsiz.b.xfersize; -+ sz2-=sz1; -+ if(sz2) -+ ifxhcd_hc_dumb_rx(&_ifxhcd->core_if, _ifxhc,_ifxhc->epqh->dump_buf); -+ _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ _ifxhc->data_pid_start = read_data_toggle(_hc_regs); -+ _urbd->error_count++; -+ if(_urbd->error_count>=3) -+ { -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof = 0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); -+ } -+ else -+ { -+ _ifxhc->wait_for_sof = 1; -+ enable_hc_int(_hc_regs,ack); -+ enable_hc_int(_hc_regs,nak); -+ enable_hc_int(_hc_regs,nyet); -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ } -+ #endif -+ } -+ else if(hcint.b.xacterr ) -+ { -+ if(hctsiz.b.pktcnt==0) -+ { -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ return 1; -+ } -+ _urbd->error_count++; -+ if(_urbd->error_count>=3) -+ { -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof = 0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); -+ } -+ else -+ { -+ _ifxhc->wait_for_sof = 1; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ return 1; -+ } -+ else if(hcint.b.stall ) -+ { -+ warning -+ } -+ #else -+ #endif -+ return 0; -+} -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+static int32_t chhltd_ctrlbulk_rx_ssplit(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ hcint_data_t hcint; -+ hcint_data_t hcintmsk; -+ hctsiz_data_t hctsiz; -+ -+ hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); -+ hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nak); -+ disable_hc_int(_hc_regs,nyet); -+ -+ _ifxhc->do_ping =0; -+ -+ if (hcint.b.ack) -+ { -+ _urbd->error_count=0; -+ _ifxhc->split=2; -+ _ifxhc->wait_for_sof = 8; -+ _ifxhc->data_pid_start = read_data_toggle(_hc_regs); -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if (hcint.b.nak) -+ { -+ _ifxhc->wait_for_sof = 1; -+ _urbd->error_count = 0; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if (hcint.b.xacterr) -+ { -+ _urbd->error_count++; -+ if(_urbd->error_count>=3) -+ { -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); -+ } -+ else -+ { -+ _ifxhc->wait_for_sof =1; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ return 1; -+ } -+ else if(hcint.b.bblerr ) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); -+ return 1; -+ } -+ else if(hcint.b.stall ) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); -+ return 1; -+ } -+ else if(hcint.b.datatglerr ) -+ { -+IFX_WARN("%s() %d Warning CTRLBULK IN SPLIT1 HC_XFER_DATA_TOGGLE_ERR\n",__func__,__LINE__); -+showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_DATA_TOGGLE_ERR); -+ return 1; -+ } -+ else if(hcint.b.frmovrun ) -+ { -+IFX_WARN("%s() %d Warning CTRLBULK IN SPLIT1 HC_XFER_FRAME_OVERRUN\n",__func__,__LINE__); -+showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN); -+ return 1; -+ } -+ else if(hcint.b.nyet ) -+ { -+IFX_WARN("%s() %d Warning CTRLBULK IN SPLIT1 NYET\n",__func__,__LINE__); -+showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ } -+ else if(hcint.b.xfercomp ) -+ { -+IFX_WARN("%s() %d Warning CTRLBULK IN SPLIT1 COMPLETE\n",__func__,__LINE__); -+showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ } -+ return 0; -+} -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+static int32_t chhltd_ctrlbulk_tx_ssplit(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ hcint_data_t hcint; -+ hcint_data_t hcintmsk; -+ hctsiz_data_t hctsiz; -+ int out_nak_enh = 0; -+ -+#ifdef __DEBUG__ -+static int first=0; -+#endif -+ -+ if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH) -+ out_nak_enh = 1; -+ -+ hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); -+ hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nak); -+ disable_hc_int(_hc_regs,nyet); -+ -+#ifdef __DEBUG__ -+ if(!first&& _ifxhc->ep_type == IFXUSB_EP_TYPE_BULK -+ &&(hcint.b.stall || hcint.b.datatglerr || hcint.b.frmovrun || hcint.b.bblerr || hcint.b.xacterr) && !hcint.b.ack) -+ { -+ showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ first=1; -+ printk(KERN_INFO " [%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X] \n" -+ ,*(_ifxhc->xfer_buff+ 0),*(_ifxhc->xfer_buff+ 1),*(_ifxhc->xfer_buff+ 2),*(_ifxhc->xfer_buff+ 3) -+ ,*(_ifxhc->xfer_buff+ 4),*(_ifxhc->xfer_buff+ 5),*(_ifxhc->xfer_buff+ 6),*(_ifxhc->xfer_buff+ 7) -+ ,*(_ifxhc->xfer_buff+ 8),*(_ifxhc->xfer_buff+ 9),*(_ifxhc->xfer_buff+10),*(_ifxhc->xfer_buff+11) -+ ,*(_ifxhc->xfer_buff+12),*(_ifxhc->xfer_buff+13),*(_ifxhc->xfer_buff+14),*(_ifxhc->xfer_buff+15)); -+ -+ printk(KERN_INFO " [_urbd->urb->actual_length:%08X _ifxhc->start_pkt_count:%08X hctsiz.b.pktcnt:%08X ,_urbd->xfer_len:%08x] \n" -+ ,_urbd->urb->actual_length -+ ,_ifxhc->start_pkt_count -+ ,hctsiz.b.pktcnt -+ ,_urbd->xfer_len); -+ } -+#endif -+ -+ if (hcint.b.ack ) -+ { -+ _urbd->error_count=0; -+ if (_ifxhc->ep_type == IFXUSB_EP_TYPE_BULK || _ifxhc->control_phase != IFXHCD_CONTROL_SETUP) -+ _ifxhc->ssplit_out_xfer_count = _ifxhc->xfer_len; -+ _ifxhc->split=2; -+ _ifxhc->wait_for_sof =8; -+ _ifxhc->data_pid_start =read_data_toggle(_hc_regs); -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.nyet) -+ { -+IFX_WARN("%s() %d Warning CTRLBULK OUT SPLIT1 NYET\n",__func__,__LINE__); -+showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ _urbd->error_count=0; -+ if (_ifxhc->ep_type == IFXUSB_EP_TYPE_BULK || _ifxhc->control_phase != IFXHCD_CONTROL_SETUP) -+ _ifxhc->ssplit_out_xfer_count = _ifxhc->xfer_len; -+ _ifxhc->split=2; -+ _ifxhc->wait_for_sof =1; -+ _ifxhc->data_pid_start =read_data_toggle(_hc_regs); -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.nak ) -+ { -+ _ifxhc->wait_for_sof =1; -+ if(!out_nak_enh ) -+ _ifxhc->do_ping =1; -+ else -+ _ifxhc->do_ping =0; -+ _urbd->error_count =0; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.xacterr ) -+ { -+ _urbd->error_count++; -+ if(_urbd->error_count>=3) -+ { -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof =0; -+ _ifxhc->do_ping =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); -+ } -+ else -+ { -+ _ifxhc->wait_for_sof =1; -+ _ifxhc->do_ping =1; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ return 1; -+ } -+ else if(hcint.b.datatglerr ) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ _ifxhc->do_ping =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_DATA_TOGGLE_ERR); -+ return 1; -+ } -+ else if(hcint.b.bblerr ) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ _ifxhc->do_ping =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); -+ return 1; -+ } -+ else if(hcint.b.stall ) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ _ifxhc->do_ping =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); -+ return 1; -+ } -+ else if(hcint.b.frmovrun ) -+ { -+IFX_WARN("%s() %d Warning CTRLBULK OUT SPLIT1 HC_XFER_FRAME_OVERRUN\n",__func__,__LINE__); -+showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ _ifxhc->do_ping =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN); -+ return 1; -+ } -+ else if(hcint.b.xfercomp ) -+ { -+ printk(KERN_INFO "%s() %d Warning CTRLBULK OUT SPLIT1 COMPLETE\n",__func__,__LINE__); -+ } -+ return 0; -+} -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+static int32_t chhltd_intr_rx_ssplit(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ hcint_data_t hcint; -+ hcint_data_t hcintmsk; -+ hctsiz_data_t hctsiz; -+ -+ hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); -+ hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nak); -+ disable_hc_int(_hc_regs,nyet); -+ -+ _ifxhc->do_ping =0; -+ -+ if (hcint.b.ack ) -+ { -+ /*== AVM/BC 20100701 - Workaround FullSpeed Interrupts with HiSpeed Hub ==*/ -+ _ifxhc->nyet_count=0; -+ -+ _urbd->error_count=0; -+ _ifxhc->split=2; -+ _ifxhc->wait_for_sof = 0; -+ _ifxhc->data_pid_start = read_data_toggle(_hc_regs); -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.nak ) -+ { -+ _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; -+ if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; -+ _urbd->error_count=0; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.xacterr ) -+ { -+ hcchar_data_t hcchar; -+ hcchar.d32 = ifxusb_rreg(&_hc_regs->hcchar); -+ _urbd->error_count=hcchar.b.multicnt; -+ if(_urbd->error_count>=3) -+ { -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof = 0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); -+ } -+ else -+ { -+ _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; -+ if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ return 1; -+ } -+ else if(hcint.b.stall ) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); -+ return 1; -+ } -+ else if(hcint.b.bblerr ) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); -+ return 1; -+ } -+ else if(hcint.b.frmovrun ) -+ { -+ _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; -+ if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.datatglerr ) -+ { -+IFX_WARN( "%s() %d Warning INTR IN SPLIT1 DATATGLERR\n",__func__,__LINE__); -+showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_DATA_TOGGLE_ERR); -+ return 1; -+ } -+ else if(hcint.b.xfercomp ) -+ { -+IFX_WARN("%s() %d Warning INTR IN SPLIT1 COMPLETE\n",__func__,__LINE__); -+showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ } -+ return 0; -+} -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+static int32_t chhltd_intr_tx_ssplit(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ hcint_data_t hcint; -+ hcint_data_t hcintmsk; -+ hctsiz_data_t hctsiz; -+ int out_nak_enh = 0; -+ -+ if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH) -+ out_nak_enh = 1; -+ -+ hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); -+ hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nak); -+ disable_hc_int(_hc_regs,nyet); -+ -+ if (hcint.b.ack ) -+ { -+ /*== AVM/BC 20100701 - Workaround FullSpeed Interrupts with HiSpeed Hub ==*/ -+ _ifxhc->nyet_count=0; -+ -+ _urbd->error_count=0; -+ _ifxhc->ssplit_out_xfer_count = _ifxhc->xfer_len; -+ _ifxhc->split=2; -+ _ifxhc->wait_for_sof = 0; -+ _ifxhc->data_pid_start = read_data_toggle(_hc_regs); -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.nyet) -+ { -+IFX_WARN("%s() %d Warning INTR OUT SPLIT1 NYET\n",__func__,__LINE__); -+showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ _urbd->error_count=0; -+ _ifxhc->ssplit_out_xfer_count = _ifxhc->xfer_len; -+ _ifxhc->split=2; -+ _ifxhc->wait_for_sof = 0; -+ _ifxhc->data_pid_start = read_data_toggle(_hc_regs); -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.nak ) -+ { -+ _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; -+ if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; -+ _urbd->error_count =0; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.frmovrun ) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; -+ if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.xacterr ) -+ { -+ hcchar_data_t hcchar; -+ hcchar.d32 = ifxusb_rreg(&_hc_regs->hcchar); -+ _urbd->error_count=hcchar.b.multicnt; -+ if(_urbd->error_count>=3) -+ { -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); -+ } -+ else -+ { -+ enable_hc_int(_hc_regs,ack); -+ enable_hc_int(_hc_regs,nak); -+ enable_hc_int(_hc_regs,nyet); -+ _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; -+ if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ return 1; -+ } -+ else if(hcint.b.datatglerr ) -+ { -+IFX_WARN("%s() %d Warning INTR IN SPLIT1 DATATGLERR\n",__func__,__LINE__); -+showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_DATA_TOGGLE_ERR); -+ return 1; -+ } -+ else if(hcint.b.bblerr ) -+ { -+IFX_WARN("%s() %d Warning INTR IN SPLIT1 BABBLEERR\n",__func__,__LINE__); -+showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); -+ return 1; -+ } -+ else if(hcint.b.stall ) -+ { -+IFX_WARN("%s() %d Warning INTR IN SPLIT1 STALL\n",__func__,__LINE__); -+showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof =0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); -+ return 1; -+ } -+ else if(hcint.b.xfercomp ) -+ { -+IFX_WARN("%s() %d Warning INTR IN SPLIT1 COMPLETE\n",__func__,__LINE__); -+showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ } -+ return 0; -+} -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+static int32_t chhltd_isoc_rx_ssplit(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ #if defined(__EN_ISOC__) && defined(__EN_ISOC_SPLIT__) -+ hcint_data_t hcint; -+ hcint_data_t hcintmsk; -+ hctsiz_data_t hctsiz; -+ -+ hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); -+ hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ if (hcint.b.ack ) -+ { -+ Do Complete Split -+ } -+ else if(hcint.b.frmovrun ) -+ { -+ Rewind Buffer Pointers -+ Retry Start Split (in next b_interval ¡V 1 uF) -+ } -+ else if(hcint.b.datatglerr ) -+ { -+ warning -+ } -+ else if(hcint.b.bblerr ) -+ { -+ warning -+ } -+ else if(hcint.b.xacterr ) -+ { -+ warning -+ } -+ else if(hcint.b.stall ) -+ { -+ warning -+ } -+ else if(hcint.b.nak ) -+ { -+ warning -+ } -+ else if(hcint.b.xfercomp ) -+ { -+ warning -+ } -+ else if(hcint.b.nyet) -+ { -+ warning -+ } -+ #endif -+ return 0; -+} -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+static int32_t chhltd_isoc_tx_ssplit(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ #if defined(__EN_ISOC__) && defined(__EN_ISOC_SPLIT__) -+ hcint_data_t hcint; -+ hcint_data_t hcintmsk; -+ hctsiz_data_t hctsiz; -+ int out_nak_enh = 0; -+ -+ if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH) -+ out_nak_enh = 1; -+ -+ hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); -+ hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ if (hcint.b.ack ) -+ { -+ Do Next Start Split (in next b_interval ¡V 1 uF) -+ } -+ else if(hcint.b.frmovrun ) -+ { -+ Do Next Transaction in next frame. -+ } -+ else if(hcint.b.datatglerr ) -+ { -+ warning -+ } -+ else if(hcint.b.bblerr ) -+ { -+ warning -+ } -+ else if(hcint.b.xacterr ) -+ { -+ warning -+ } -+ else if(hcint.b.stall ) -+ { -+ warning -+ } -+ else if(hcint.b.nak ) -+ { -+ warning -+ } -+ else if(hcint.b.xfercomp ) -+ { -+ warning -+ } -+ else if(hcint.b.nyet) -+ { -+ warning -+ } -+ #endif -+ return 0; -+} -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+static int32_t chhltd_ctrlbulk_rx_csplit(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ hcint_data_t hcint; -+ hcint_data_t hcintmsk; -+ hctsiz_data_t hctsiz; -+ -+ hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); -+ hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nak); -+ disable_hc_int(_hc_regs,nyet); -+ -+ _ifxhc->do_ping = 0; -+ -+ if (hcint.b.xfercomp) -+ { -+ _urbd->error_count =0; -+ _ifxhc->wait_for_sof = 0; -+ _ifxhc->split=1; -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ return 1; -+ } -+ else if (hcint.b.nak) -+ { -+ _urbd->error_count=0; -+ -+ _ifxhc->split = 1; -+ _ifxhc->wait_for_sof = 1; -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.nyet) -+ { -+ _urbd->error_count=0; -+ _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; -+ _ifxhc->wait_for_sof = 1; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.stall || hcint.b.bblerr ) -+ { -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof = 0; -+ if (hcint.b.stall) -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); -+ else if(hcint.b.bblerr ) -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); -+ return 1; -+ } -+ else if(hcint.b.xacterr ) -+ { -+ _urbd->error_count++; -+ if(_urbd->error_count>=3) -+ { -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof = 0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); -+ } -+ else -+ { -+ _ifxhc->split=1; -+ _ifxhc->wait_for_sof = 1; -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ return 1; -+ } -+ else if(hcint.b.datatglerr ) -+ { -+ if(_ifxhc->data_pid_start == IFXUSB_HC_PID_DATA0) -+ _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1; -+ else -+ _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0; -+ _ifxhc->split=1; -+ _ifxhc->wait_for_sof = 1; -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.frmovrun ) -+ { -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof = 0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN); -+ return 1; -+ } -+ return 0; -+} -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+static int32_t chhltd_ctrlbulk_tx_csplit(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ hcint_data_t hcint; -+ hcint_data_t hcintmsk; -+ hctsiz_data_t hctsiz; -+ int out_nak_enh = 0; -+ -+#if 1 -+static int first=0; -+#endif -+ -+ if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH) -+ out_nak_enh = 1; -+ -+ hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); -+ hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nak); -+ disable_hc_int(_hc_regs,nyet); -+ -+#if 1 -+ if(!first&& _ifxhc->ep_type == IFXUSB_EP_TYPE_BULK -+ &&(hcint.b.stall || hcint.b.datatglerr || hcint.b.frmovrun || hcint.b.bblerr || hcint.b.xacterr) && !hcint.b.ack) -+ { -+ showint( hcint.d32,hcintmsk.d32,hctsiz.d32); -+ first=1; -+ printk(KERN_INFO " [%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X] \n" -+ ,*(_ifxhc->xfer_buff+ 0),*(_ifxhc->xfer_buff+ 1),*(_ifxhc->xfer_buff+ 2),*(_ifxhc->xfer_buff+ 3) -+ ,*(_ifxhc->xfer_buff+ 4),*(_ifxhc->xfer_buff+ 5),*(_ifxhc->xfer_buff+ 6),*(_ifxhc->xfer_buff+ 7) -+ ,*(_ifxhc->xfer_buff+ 8),*(_ifxhc->xfer_buff+ 9),*(_ifxhc->xfer_buff+10),*(_ifxhc->xfer_buff+11) -+ ,*(_ifxhc->xfer_buff+12),*(_ifxhc->xfer_buff+13),*(_ifxhc->xfer_buff+14),*(_ifxhc->xfer_buff+15)); -+ -+ printk(KERN_INFO " [_urbd->urb->actual_length:%08X _ifxhc->start_pkt_count:%08X hctsiz.b.pktcnt:%08X ,_urbd->xfer_len:%08x] \n" -+ ,_urbd->urb->actual_length -+ ,_ifxhc->start_pkt_count -+ ,hctsiz.b.pktcnt -+ ,_urbd->xfer_len); -+ } -+#endif -+ -+ if(hcint.b.xfercomp ) -+ { -+ _urbd->error_count=0; -+ _ifxhc->split=1; -+ _ifxhc->do_ping= 0; -+ #if 0 -+ if(_ifxhc->xfer_len==0 && !hcint.b.ack && (hcint.b.nak || hcint.b.nyet)) -+ { -+ // Walkaround: When sending ZLP and receive NYEY or NAK but also issue CMPT intr -+ // Solution: NoSplit: Resend at next SOF -+ // Split : Resend at next SOF with SSPLIT -+ _ifxhc->xfer_len = 0; -+ _ifxhc->xfer_count = 0; -+ _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; -+ _ifxhc->wait_for_sof = 1; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ else -+ #endif -+ { -+ _ifxhc->wait_for_sof = 0; -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ } -+ return 1; -+ } -+ else if(hcint.b.nak ) -+ { -+ _urbd->error_count=0; -+ -+ _ifxhc->split = 1; -+ _ifxhc->wait_for_sof = 1; -+ if(!out_nak_enh ) -+ _ifxhc->do_ping =1; -+ else -+ _ifxhc->do_ping =0; -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.nyet) -+ { -+ //Retry Complete Split -+ // Issue Retry instantly on next SOF, without gothrough process_channels -+ _urbd->error_count=0; -+ _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; -+ _ifxhc->wait_for_sof = 1; -+ _ifxhc->do_ping = 0; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.stall ) -+ { -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof = 0; -+ _ifxhc->do_ping = 0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); -+ return 1; -+ } -+ else if(hcint.b.xacterr ) -+ { -+ _urbd->error_count++; -+ if(_urbd->error_count>=3) -+ { -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof = 0; -+ _ifxhc->do_ping = 0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); -+ } -+ else -+ { -+ _ifxhc->split=1; -+ _ifxhc->wait_for_sof = 1; -+ if(!out_nak_enh ) -+ _ifxhc->do_ping =1; -+ else -+ _ifxhc->do_ping =0; -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ return 1; -+ } -+ else if(hcint.b.datatglerr ) -+ { -+ if(_ifxhc->data_pid_start == IFXUSB_HC_PID_DATA0) -+ _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1; -+ else -+ _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0; -+ _ifxhc->split=1; -+ _ifxhc->wait_for_sof = 1; -+ if(!out_nak_enh ) -+ _ifxhc->do_ping =1; -+ else -+ _ifxhc->do_ping =0; -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.frmovrun ) -+ { -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof = 0; -+ _ifxhc->do_ping = 0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN); -+ return 1; -+ } -+ else if(hcint.b.bblerr ) -+ { -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof = 0; -+ _ifxhc->do_ping = 0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); -+ return 1; -+ } -+ return 0; -+} -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+static int32_t chhltd_intr_rx_csplit(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ hcint_data_t hcint; -+ hcint_data_t hcintmsk; -+ hctsiz_data_t hctsiz; -+ -+ hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); -+ hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nak); -+ disable_hc_int(_hc_regs,nyet); -+ _ifxhc->do_ping = 0; -+ -+ if (hcint.b.xfercomp ) -+ { -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof = 0; -+ _ifxhc->split=1; -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ return 1; -+ } -+ else if(hcint.b.nak ) -+ { -+ _urbd->error_count=0; -+ _ifxhc->split = 1; -+ _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; -+ if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.nyet) -+ { -+ _urbd->error_count=0; -+ _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; -+ _ifxhc->wait_for_sof = 0; -+ -+ /*== AVM/BC 20100701 - Workaround FullSpeed Interrupts with HiSpeed Hub ==*/ -+ _ifxhc->nyet_count++; -+ if(_ifxhc->nyet_count > 2) { -+ _ifxhc->split = 1; -+ _ifxhc->nyet_count = 0; -+ _ifxhc->wait_for_sof = 5; -+ } -+ -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.frmovrun || hcint.b.bblerr || hcint.b.stall ) -+ { -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof = 0; -+ if (hcint.b.stall) -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); -+ else if(hcint.b.bblerr ) -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); -+ else if(hcint.b.frmovrun ) -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN); -+ return 1; -+ } -+ else if(hcint.b.xacterr ) -+ { -+ hcchar_data_t hcchar; -+ hcchar.d32 = ifxusb_rreg(&_hc_regs->hcchar); -+ _urbd->error_count=hcchar.b.multicnt; -+ if(_urbd->error_count>=3) -+ { -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof = 0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); -+ } -+ else -+ { -+ _ifxhc->split=1; -+ _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; -+ if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ return 1; -+ } -+ else if(hcint.b.datatglerr ) -+ { -+ if(_ifxhc->data_pid_start == IFXUSB_HC_PID_DATA0) -+ _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1; -+ else -+ _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0; -+ _ifxhc->split=1; -+ _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; -+ if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ return 0; -+} -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+static int32_t chhltd_intr_tx_csplit(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ hcint_data_t hcint; -+ hcint_data_t hcintmsk; -+ hctsiz_data_t hctsiz; -+ int out_nak_enh = 0; -+ -+ if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH) -+ out_nak_enh = 1; -+ -+ hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); -+ hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nak); -+ disable_hc_int(_hc_regs,nyet); -+ -+ if(hcint.b.xfercomp ) -+ { -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof = 0; -+ _ifxhc->split=1; -+ _ifxhc->do_ping = 0; -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ return 1; -+ } -+ else if(hcint.b.nak ) -+ { -+ _urbd->error_count=0; -+ _ifxhc->split = 1; -+ _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; -+ if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; -+ if(!out_nak_enh ) -+ _ifxhc->do_ping =1; -+ else -+ _ifxhc->do_ping =0; -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.nyet) -+ { -+ _urbd->error_count=0; -+ _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; -+ _ifxhc->wait_for_sof = 0; -+ _ifxhc->do_ping = 0; -+ -+ /*== AVM/BC 20100701 - Workaround FullSpeed Interrupts with HiSpeed Hub ==*/ -+ _ifxhc->nyet_count++; -+ if(_ifxhc->nyet_count > 2) { -+ _ifxhc->split = 1; -+ _ifxhc->nyet_count = 0; -+ _ifxhc->wait_for_sof = 5; -+ } -+ -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.stall || hcint.b.frmovrun) -+ { -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof = 0; -+ _ifxhc->do_ping = 0; -+ if (hcint.b.stall) -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); -+ else if(hcint.b.frmovrun ) -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_FRAME_OVERRUN); -+ return 1; -+ } -+ else if(hcint.b.xacterr ) -+ { -+ hcchar_data_t hcchar; -+ hcchar.d32 = ifxusb_rreg(&_hc_regs->hcchar); -+ _urbd->error_count=hcchar.b.multicnt; -+ if(_urbd->error_count>=3) -+ { -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof = 0; -+ _ifxhc->do_ping = 0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_XACT_ERR); -+ } -+ else -+ { -+ _ifxhc->split=1; -+ _ifxhc->wait_for_sof = _ifxhc->epqh->interval-1; -+ if(!_ifxhc->wait_for_sof) _ifxhc->wait_for_sof=1; -+ if(!out_nak_enh ) -+ _ifxhc->do_ping =1; -+ else -+ _ifxhc->do_ping =0; -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ } -+ return 1; -+ } -+ else if(hcint.b.datatglerr ) -+ { -+ if(_ifxhc->data_pid_start == IFXUSB_HC_PID_DATA0) -+ _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA1; -+ else -+ _ifxhc->data_pid_start = IFXUSB_HC_PID_DATA0; -+ _ifxhc->split=1; -+ if(!out_nak_enh ) -+ _ifxhc->do_ping =1; -+ else -+ _ifxhc->do_ping =0; -+ _ifxhc->xfer_len = _urbd->xfer_len - _urbd->urb->actual_length; -+ _ifxhc->xfer_count = _urbd->urb->actual_length; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.bblerr ) -+ { -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof = 0; -+ _ifxhc->do_ping = 0; -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_BABBLE_ERR); -+ return 1; -+ } -+ return 0; -+} -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+static int32_t chhltd_isoc_rx_csplit(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ #if defined(__EN_ISOC__) && defined(__EN_ISOC_SPLIT__) -+ hcint_data_t hcint; -+ hcint_data_t hcintmsk; -+ hctsiz_data_t hctsiz; -+ -+ hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); -+ hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ if(hcint.b.xfercomp ) -+ { -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nak); -+ disable_hc_int(_hc_regs,nyet); -+ _urbd->error_count=0; -+ _ifxhc->wait_for_sof = 0; -+ _ifxhc->split=1; -+ complete_channel(_ifxhcd, _ifxhc, _urbd); -+ return 1; -+ } -+ else if(hcint.b.nak ) -+ { -+ Retry Start Split (in next b_interval ¡V 1 uF) -+ } -+ else if(hcint.b.nyet) -+ { -+ //Do Next Complete Split -+ // Issue Retry instantly on next SOF, without gothrough process_channels -+ _urbd->error_count=0; -+ //disable_hc_int(_hc_regs,ack); -+ //disable_hc_int(_hc_regs,nak); -+ //disable_hc_int(_hc_regs,datatglerr); -+ _ifxhc->halt_status = HC_XFER_NO_HALT_STATUS; -+ _ifxhc->wait_for_sof = 1; -+ ifxhcd_hc_start(&_ifxhcd->core_if, _ifxhc); -+ return 1; -+ } -+ else if(hcint.b.frmovrun || hcint.b.stall || hcint.b.bblerr) -+ { -+ _urbd->error_count=0; -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nyet); -+ disable_hc_int(_hc_regs,nak); -+ _ifxhc->wait_for_sof = 0; -+ -+ //if(hctsiz.b.pktcnt==0) -+ //{ -+ // complete_channel(_ifxhcd, _ifxhc, _urbd); -+ // return 1; -+ //} -+ //else -+ // _urbd->urb->actual_length += (_ifxhc->xfer_len - hctsiz.b.xfersize); -+ if (hcint.b.stall) -+ release_channel(_ifxhcd, _ifxhc, HC_XFER_STALL); -+ else if(hcint.b.frmovrun ) -+ else if(hcint.b.bblerr ) -+ return 1; -+ } -+ else if(hcint.b.xacterr ) -+ { -+ Rewind Buffer Pointers -+ if (HCCHARn.EC = = 3) // ERR response received -+ { -+ Record ERR error -+ Do Next Start Split (in next frame) -+ } -+ else -+ { -+ De-allocate Channel -+ } -+ } -+ else if(hcint.b.datatglerr ) -+ { -+ warning -+ } -+ else if(hcint.b.ack ) -+ { -+ warning -+ } -+ #endif -+ return 0; -+} -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+static int32_t chhltd_isoc_tx_csplit(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ #if defined(__EN_ISOC__) && defined(__EN_ISOC_SPLIT__) -+ hcint_data_t hcint; -+ hcint_data_t hcintmsk; -+ hctsiz_data_t hctsiz; -+ int out_nak_enh = 0; -+ -+ if (_ifxhcd->core_if.snpsid >= 0x4f54271a && _ifxhc->speed == IFXUSB_EP_SPEED_HIGH) -+ out_nak_enh = 1; -+ -+ hcint.d32 = ifxusb_rreg(&_hc_regs->hcint); -+ hcintmsk.d32 = ifxusb_rreg(&_hc_regs->hcintmsk); -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ warning -+ #endif -+ return 0; -+} -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+static int32_t handle_hc_chhltd_intr(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ IFX_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: Channel Halted--\n", _ifxhc->hc_num); -+ -+ _ifxhc->halting = 0; -+ _ifxhc->xfer_started = 0; -+ -+ if (_ifxhc->halt_status == HC_XFER_URB_DEQUEUE || -+ _ifxhc->halt_status == HC_XFER_AHB_ERR) { -+ /* -+ * Just release the channel. A dequeue can happen on a -+ * transfer timeout. In the case of an AHB Error, the channel -+ * was forced to halt because there's no way to gracefully -+ * recover. -+ */ -+ release_channel(_ifxhcd, _ifxhc, _ifxhc->halt_status); -+ return 1; -+ } -+ -+ if (_ifxhc->ep_type == IFXUSB_EP_TYPE_CTRL || _ifxhc->ep_type == IFXUSB_EP_TYPE_BULK) -+ { -+ if (_ifxhc->split==0) -+ { -+ if(_ifxhc->is_in) -+ return (chhltd_ctrlbulk_rx_nonsplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); -+ else -+ return (chhltd_ctrlbulk_tx_nonsplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); -+ } -+ else if(_ifxhc->split==1) -+ { -+ if(_ifxhc->is_in) -+ return (chhltd_ctrlbulk_rx_ssplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); -+ else -+ return (chhltd_ctrlbulk_tx_ssplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); -+ } -+ else if(_ifxhc->split==2) -+ { -+ if(_ifxhc->is_in) -+ return (chhltd_ctrlbulk_rx_csplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); -+ else -+ return (chhltd_ctrlbulk_tx_csplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); -+ } -+ } -+ else if(_ifxhc->ep_type == IFXUSB_EP_TYPE_INTR) -+ { -+ if (_ifxhc->split==0) -+ { -+ if(_ifxhc->is_in) -+ return (chhltd_intr_rx_nonsplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); -+ else -+ return (chhltd_intr_tx_nonsplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); -+ } -+ else if(_ifxhc->split==1) -+ { -+ if(_ifxhc->is_in) -+ return (chhltd_intr_rx_ssplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); -+ else -+ return (chhltd_intr_tx_ssplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); -+ } -+ else if(_ifxhc->split==2) -+ { -+ if(_ifxhc->is_in) -+ return (chhltd_intr_rx_csplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); -+ else -+ return (chhltd_intr_tx_csplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); -+ } -+ } -+ else if(_ifxhc->ep_type == IFXUSB_EP_TYPE_ISOC) -+ { -+ if (_ifxhc->split==0) -+ { -+ if(_ifxhc->is_in) -+ return (chhltd_isoc_rx_nonsplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); -+ else -+ return (chhltd_isoc_tx_nonsplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); -+ } -+ else if(_ifxhc->split==1) -+ { -+ if(_ifxhc->is_in) -+ return (chhltd_isoc_rx_ssplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); -+ else -+ return (chhltd_isoc_tx_ssplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); -+ } -+ else if(_ifxhc->split==2) -+ { -+ if(_ifxhc->is_in) -+ return (chhltd_isoc_rx_csplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); -+ else -+ return (chhltd_isoc_tx_csplit(_ifxhcd,_ifxhc,_hc_regs,_urbd)); -+ } -+ } -+ return 0; -+} -+ -+/* -+ * Handles a host channel AHB error interrupt. This handler is only called in -+ * DMA mode. -+ */ -+static void hc_other_intr_dump(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ #ifdef __DEBUG__ -+ hcchar_data_t hcchar; -+ hcsplt_data_t hcsplt; -+ hctsiz_data_t hctsiz; -+ uint32_t hcdma; -+ struct urb *urb = _urbd->urb; -+ hcchar.d32 = ifxusb_rreg(&_hc_regs->hcchar); -+ hcsplt.d32 = ifxusb_rreg(&_hc_regs->hcsplt); -+ hctsiz.d32 = ifxusb_rreg(&_hc_regs->hctsiz); -+ hcdma = ifxusb_rreg(&_hc_regs->hcdma); -+ -+ IFX_ERROR("Channel %d\n", _ifxhc->hc_num); -+ IFX_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32); -+ IFX_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma); -+ IFX_ERROR(" Device address: %d\n", usb_pipedevice(urb->pipe)); -+ IFX_ERROR(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe), -+ (usb_pipein(urb->pipe) ? "IN" : "OUT")); -+ IFX_ERROR(" Endpoint type: %s\n", -+ ({char *pipetype; -+ switch (usb_pipetype(urb->pipe)) { -+ case PIPE_CONTROL: pipetype = "CTRL"; break; -+ case PIPE_BULK: pipetype = "BULK"; break; -+ case PIPE_INTERRUPT: pipetype = "INTR"; break; -+ case PIPE_ISOCHRONOUS: pipetype = "ISOC"; break; -+ default: pipetype = "????"; break; -+ }; pipetype;})); -+ IFX_ERROR(" Speed: %s\n", -+ ({char *speed; -+ switch (urb->dev->speed) { -+ case USB_SPEED_HIGH: speed = "HS"; break; -+ case USB_SPEED_FULL: speed = "FS"; break; -+ case USB_SPEED_LOW: speed = "LS"; break; -+ default: speed = "????"; break; -+ }; speed;})); -+ IFX_ERROR(" Max packet size: %d\n", -+ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); -+ IFX_ERROR(" Data buffer length: %d\n", urb->transfer_buffer_length); -+ IFX_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n", -+ urb->transfer_buffer, (void *)urb->transfer_dma); -+ IFX_ERROR(" Setup buffer: %p, Setup DMA: %p\n", -+ urb->setup_packet, (void *)urb->setup_dma); -+ IFX_ERROR(" Interval: %d\n", urb->interval); -+ #endif //__DEBUG__ -+} -+ -+/* -+ * Handles a host channel ACK interrupt. This interrupt is enabled when -+ * errors occur, and during Start Split transactions. -+ */ -+static int32_t handle_hc_ack_intr(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ _urbd->error_count=0; -+ if(_ifxhc->nak_countdown_r) -+ { -+ _ifxhc->nak_retry=_ifxhc->nak_retry_r; -+ _ifxhc->nak_countdown=_ifxhc->nak_countdown_r; -+ } -+ else -+ disable_hc_int(_hc_regs,nak); -+ disable_hc_int(_hc_regs,ack); -+ return 1; -+} -+ -+/* -+ * Handles a host channel ACK interrupt. This interrupt is enabled when -+ * errors occur, and during Start Split transactions. -+ */ -+static int32_t handle_hc_nak_intr(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ -+ _urbd->error_count=0; -+ -+ if(_ifxhc->nak_countdown_r) -+ { -+ _ifxhc->nak_countdown--; -+ if(!_ifxhc->nak_countdown) -+ { -+ _ifxhc->nak_countdown=_ifxhc->nak_countdown_r; -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nak); -+ ifxhcd_hc_halt(&_ifxhcd->core_if, _ifxhc, HC_XFER_NAK); -+ } -+ else -+ enable_hc_int(_hc_regs,ack); -+ } -+ else -+ { -+ disable_hc_int(_hc_regs,ack); -+ disable_hc_int(_hc_regs,nak); -+ } -+ return 1; -+} -+ -+/* -+ * Handles a host channel AHB error interrupt. This handler is only called in -+ * DMA mode. -+ */ -+static int32_t handle_hc_ahberr_intr(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ IFX_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " -+ "AHB Error--\n", _ifxhc->hc_num); -+ hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd); -+ -+ ifxhcd_hc_halt(&_ifxhcd->core_if, _ifxhc, HC_XFER_AHB_ERR); -+ return 1; -+} -+ -+/* -+ * Datatoggle -+ */ -+static int32_t handle_hc_datatglerr_intr(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ IFX_ERROR( "--Host Channel %d Interrupt: " -+ "DATATOGGLE Error--\n", _ifxhc->hc_num); -+ hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd); -+ disable_hc_int(_hc_regs,datatglerr); -+ return 1; -+} -+ -+ -+ -+/* -+ * Interrupts which should not been triggered -+ */ -+static int32_t handle_hc_frmovrun_intr(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ IFX_ERROR( "--Host Channel %d Interrupt: " -+ "FrameOverRun Error--\n", _ifxhc->hc_num); -+ hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd); -+ disable_hc_int(_hc_regs,frmovrun); -+ return 1; -+} -+ -+static int32_t handle_hc_bblerr_intr(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ IFX_ERROR( "--Host Channel %d Interrupt: " -+ "BBL Error--\n", _ifxhc->hc_num); -+ hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd); -+ disable_hc_int(_hc_regs,bblerr); -+ return 1; -+} -+ -+static int32_t handle_hc_xacterr_intr(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ IFX_ERROR( "--Host Channel %d Interrupt: " -+ "XACT Error--\n", _ifxhc->hc_num); -+ hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd); -+ disable_hc_int(_hc_regs,xacterr); -+ return 1; -+} -+ -+static int32_t handle_hc_nyet_intr(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ IFX_ERROR( "--Host Channel %d Interrupt: " -+ "NYET--\n", _ifxhc->hc_num); -+ hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd); -+ _urbd->error_count=0; -+ disable_hc_int(_hc_regs,nyet); -+ return 1; -+} -+ -+static int32_t handle_hc_stall_intr(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ IFX_ERROR( "--Host Channel %d Interrupt: " -+ "STALL--\n", _ifxhc->hc_num); -+ hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd); -+ disable_hc_int(_hc_regs,stall); -+ return 1; -+} -+ -+static int32_t handle_hc_xfercomp_intr(ifxhcd_hcd_t *_ifxhcd, -+ ifxhcd_hc_t *_ifxhc, -+ ifxusb_hc_regs_t *_hc_regs, -+ ifxhcd_urbd_t *_urbd) -+{ -+ IFX_ERROR( "--Host Channel %d Interrupt: " -+ "XFERCOMP--\n", _ifxhc->hc_num); -+ hc_other_intr_dump(_ifxhcd,_ifxhc,_hc_regs,_urbd); -+ disable_hc_int(_hc_regs,xfercomp); -+ return 1; -+} -+ -+ -+ -+/* This interrupt indicates that the specified host channels has a pending -+ * interrupt. There are multiple conditions that can cause each host channel -+ * interrupt. This function determines which conditions have occurred for this -+ * host channel interrupt and handles them appropriately. */ -+static int32_t handle_hc_n_intr (ifxhcd_hcd_t *_ifxhcd, uint32_t _num) -+{ -+ uint32_t hcintval,hcintmsk; -+ hcint_data_t hcint; -+ ifxhcd_hc_t *ifxhc; -+ ifxusb_hc_regs_t *hc_regs; -+ ifxhcd_urbd_t *urbd; -+ unsigned long flags; -+ -+ int retval = 0; -+ -+ IFX_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", _num); -+ -+ /*== AVM/BC 20101111 Lock needed ==*/ -+ SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags); -+ -+ ifxhc = &_ifxhcd->ifxhc[_num]; -+ hc_regs = _ifxhcd->core_if.hc_regs[_num]; -+ -+ hcintval = ifxusb_rreg(&hc_regs->hcint); -+ hcintmsk = ifxusb_rreg(&hc_regs->hcintmsk); -+ hcint.d32 = hcintval & hcintmsk; -+ IFX_DEBUGPL(DBG_HCDV, " 0x%08x & 0x%08x = 0x%08x\n", -+ hcintval, hcintmsk, hcint.d32); -+ -+ urbd = list_entry(ifxhc->epqh->urbd_list.next, ifxhcd_urbd_t, urbd_list_entry); -+ -+ if (hcint.b.datatglerr) -+ retval |= handle_hc_datatglerr_intr(_ifxhcd, ifxhc, hc_regs, urbd); -+ if (hcint.b.frmovrun) -+ retval |= handle_hc_frmovrun_intr(_ifxhcd, ifxhc, hc_regs, urbd); -+ if (hcint.b.bblerr) -+ retval |= handle_hc_bblerr_intr(_ifxhcd, ifxhc, hc_regs, urbd); -+ if (hcint.b.xacterr) -+ retval |= handle_hc_xacterr_intr(_ifxhcd, ifxhc, hc_regs, urbd); -+ if (hcint.b.nyet) -+ retval |= handle_hc_nyet_intr(_ifxhcd, ifxhc, hc_regs, urbd); -+ if (hcint.b.ack) -+ retval |= handle_hc_ack_intr(_ifxhcd, ifxhc, hc_regs, urbd); -+ if (hcint.b.nak) -+ retval |= handle_hc_nak_intr(_ifxhcd, ifxhc, hc_regs, urbd); -+ if (hcint.b.stall) -+ retval |= handle_hc_stall_intr(_ifxhcd, ifxhc, hc_regs, urbd); -+ if (hcint.b.ahberr) { -+ clear_hc_int(hc_regs, ahberr); -+ retval |= handle_hc_ahberr_intr(_ifxhcd, ifxhc, hc_regs, urbd); -+ } -+ if (hcint.b.chhltd) { -+ /* == 20110901 AVM/WK Fix: Flag must not be cleared after restart of channel ==*/ -+ clear_hc_int(hc_regs, chhltd); -+ retval |= handle_hc_chhltd_intr(_ifxhcd, ifxhc, hc_regs, urbd); -+ } -+ if (hcint.b.xfercomp) -+ retval |= handle_hc_xfercomp_intr(_ifxhcd, ifxhc, hc_regs, urbd); -+ -+ /* == 20110901 AVM/WK Fix: Never clear possibly new intvals ==*/ -+ //ifxusb_wreg(&hc_regs->hcint,hcintval); -+ -+ SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); -+ -+ return retval; -+} -+ -+ -+ -+ -+ -+ -+static uint8_t update_interval_counter(ifxhcd_epqh_t *_epqh,uint32_t _diff) -+{ -+ if(_diff>=_epqh->period_counter) -+ { -+ _epqh->period_do=1; -+ if(_diff>_epqh->interval) -+ _epqh->period_counter=1; -+ else -+ _epqh->period_counter=_epqh->period_counter+_epqh->interval-_diff; -+ return 1; -+ } -+ _epqh->period_counter=_epqh->period_counter-_diff; -+ return 0; -+} -+ -+ -+ -+ -+/* -+ * Handles the start-of-frame interrupt in host mode. Non-periodic -+ * transactions may be queued to the DWC_otg controller for the current -+ * (micro)frame. Periodic transactions may be queued to the controller for the -+ * next (micro)frame. -+ */ -+static int32_t handle_sof_intr (ifxhcd_hcd_t *_ifxhcd) -+{ -+ #ifdef __DYN_SOF_INTR__ -+ uint8_t with_count_down=0; -+ #endif -+ uint8_t active_on=0; -+ uint8_t ready_on=0; -+ struct list_head *epqh_entry; -+ ifxhcd_epqh_t *epqh; -+ hfnum_data_t hfnum; -+ uint32_t fndiff; -+ -+ unsigned long flags; -+#ifdef __USE_TIMER_4_SOF__ -+ uint32_t wait_for_sof = 0x10000; -+#endif -+ -+ SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags); -+ -+ { -+ int num_channels; -+ ifxusb_hc_regs_t *hc_regs; -+ int i; -+ num_channels = _ifxhcd->core_if.params.host_channels; -+ -+// AVM/WK moved block here due to use of SOF timer -+ hfnum.d32 = ifxusb_rreg(&_ifxhcd->core_if.host_global_regs->hfnum); -+ fndiff = hfnum.b.frnum; -+ fndiff+= 0x00004000; -+ fndiff-= _ifxhcd->lastframe ; -+ fndiff&= 0x00003FFF; -+ if(!fndiff) fndiff =1; -+ -+ for (i = 0; i < num_channels; i++) -+ { -+ if(_ifxhcd->ifxhc[i].wait_for_sof && _ifxhcd->ifxhc[i].xfer_started) -+ { -+#ifdef __USE_TIMER_4_SOF__ -+ if (_ifxhcd->ifxhc[i].wait_for_sof > fndiff) { -+ _ifxhcd->ifxhc[i].wait_for_sof -= fndiff; -+ } else { -+ _ifxhcd->ifxhc[i].wait_for_sof = 0; -+ } -+#else -+ _ifxhcd->ifxhc[i].wait_for_sof--; -+#endif -+ if(_ifxhcd->ifxhc[i].wait_for_sof==0) -+ { -+ hcint_data_t hcint= { .d32=0 }; -+ hc_regs = _ifxhcd->core_if.hc_regs[i]; -+ -+ hcint.d32 =0xFFFFFFFF; -+ ifxusb_wreg(&hc_regs->hcint, hcint.d32); -+ -+ hcint.d32=ifxusb_rreg(&hc_regs->hcintmsk); -+ hcint.b.nak =0; -+ hcint.b.ack =0; -+ /* == 20110901 AVM/WK Fix: We don't need NOT YET IRQ ==*/ -+ hcint.b.nyet=0; -+ _ifxhcd->ifxhc[i].nak_countdown=_ifxhcd->ifxhc[i].nak_countdown_r; -+ if(_ifxhcd->ifxhc[i].nak_countdown_r) -+ hcint.b.nak =1; -+ ifxusb_wreg(&hc_regs->hcintmsk, hcint.d32); -+ -+ /* AVM WK / BC 20100827 -+ * FIX: Packet was ignored because of wrong Oddframe bit -+ */ -+ if (_ifxhcd->ifxhc[i].ep_type == IFXUSB_EP_TYPE_INTR || _ifxhcd->ifxhc[i].ep_type == IFXUSB_EP_TYPE_ISOC) -+ { -+ hcchar_data_t hcchar; -+ hcchar.d32 = _ifxhcd->ifxhc[i].hcchar; -+ hfnum.d32 = ifxusb_rreg(&_ifxhcd->core_if.host_global_regs->hfnum); -+ /* 1 if _next_ frame is odd, 0 if it's even */ -+ hcchar.b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1; -+ _ifxhcd->ifxhc[i].hcchar = hcchar.d32; -+ } -+ -+ ifxusb_wreg(&hc_regs->hcchar, _ifxhcd->ifxhc[i].hcchar); -+ -+ } -+ } -+ else -+ _ifxhcd->ifxhc[i].wait_for_sof=0; -+ -+#ifdef __USE_TIMER_4_SOF__ -+ if (_ifxhcd->ifxhc[i].wait_for_sof && (wait_for_sof > _ifxhcd->ifxhc[i].wait_for_sof)) { -+ wait_for_sof = _ifxhcd->ifxhc[i].wait_for_sof; -+ } -+#endif -+ } -+ } -+ -+ // ISOC Active -+ #ifdef __EN_ISOC__ -+ #error ISOC not supported: missing SOF code -+ epqh_entry = _ifxhcd->epqh_isoc_active.next; -+ while (epqh_entry != &_ifxhcd->epqh_isoc_active) -+ { -+ epqh = list_entry(epqh_entry, ifxhcd_epqh_t, epqh_list_entry); -+ epqh_entry = epqh_entry->next; -+ #ifdef __DYN_SOF_INTR__ -+ with_count_down=1; -+ #endif -+ active_on+=update_interval_counter(epqh,fndiff); -+ } -+ -+ // ISOC Ready -+ epqh_entry = _ifxhcd->epqh_isoc_ready.next; -+ while (epqh_entry != &_ifxhcd->epqh_isoc_ready) -+ { -+ epqh = list_entry(epqh_entry, ifxhcd_epqh_t, epqh_list_entry); -+ epqh_entry = epqh_entry->next; -+ #ifdef __DYN_SOF_INTR__ -+ with_count_down=1; -+ #endif -+ ready_on+=update_interval_counter(epqh,fndiff); -+ } -+ #endif -+ -+ // INTR Active -+ epqh_entry = _ifxhcd->epqh_intr_active.next; -+ while (epqh_entry != &_ifxhcd->epqh_intr_active) -+ { -+ epqh = list_entry(epqh_entry, ifxhcd_epqh_t, epqh_list_entry); -+ epqh_entry = epqh_entry->next; -+ #ifdef __DYN_SOF_INTR__ -+ with_count_down=1; -+ #endif -+#ifdef __USE_TIMER_4_SOF__ -+ if (update_interval_counter(epqh,fndiff)) { -+ active_on ++; -+ wait_for_sof = 1; -+ } else { -+ if (epqh->period_counter && (wait_for_sof > epqh->period_counter)) { -+ wait_for_sof = epqh->period_counter; -+ } -+ } -+#else -+ active_on+=update_interval_counter(epqh,fndiff); -+#endif -+ } -+ -+ // INTR Ready -+ epqh_entry = _ifxhcd->epqh_intr_ready.next; -+ while (epqh_entry != &_ifxhcd->epqh_intr_ready) -+ { -+ epqh = list_entry(epqh_entry, ifxhcd_epqh_t, epqh_list_entry); -+ epqh_entry = epqh_entry->next; -+ #ifdef __DYN_SOF_INTR__ -+ with_count_down=1; -+ #endif -+#ifdef __USE_TIMER_4_SOF__ -+ if (update_interval_counter(epqh,fndiff)) { -+ ready_on ++; -+ wait_for_sof = 1; -+ } else { -+ if (epqh->period_counter && (wait_for_sof > epqh->period_counter)) { -+ wait_for_sof = epqh->period_counter; -+ } -+ } -+#else -+ ready_on+=update_interval_counter(epqh,fndiff); -+#endif -+ } -+ -+ // Stdby -+ epqh_entry = _ifxhcd->epqh_stdby.next; -+ while (epqh_entry != &_ifxhcd->epqh_stdby) -+ { -+ epqh = list_entry(epqh_entry, ifxhcd_epqh_t, epqh_list_entry); -+ epqh_entry = epqh_entry->next; -+ if(epqh->period_counter > 0 ) { -+#ifdef __USE_TIMER_4_SOF__ -+ if (epqh->period_counter > fndiff) { -+ epqh->period_counter -= fndiff; -+ } else { -+ epqh->period_counter = 0; -+ } -+#else -+ epqh->period_counter --; -+#endif -+ #ifdef __DYN_SOF_INTR__ -+ with_count_down=1; -+ #endif -+ } -+ if(epqh->period_counter == 0) { -+ ifxhcd_epqh_idle_periodic(epqh); -+ } -+#ifdef __USE_TIMER_4_SOF__ -+ else { -+ if (wait_for_sof > epqh->period_counter) { -+ wait_for_sof = epqh->period_counter; -+ } -+ } -+#endif -+ } -+ SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); -+ -+ if(ready_on) -+ select_eps(_ifxhcd); -+ else if(active_on) -+ process_channels(_ifxhcd); -+ -+ /* Clear interrupt */ -+ { -+ gint_data_t gintsts; -+ gintsts.d32=0; -+ gintsts.b.sofintr = 1; -+ ifxusb_wreg(&_ifxhcd->core_if.core_global_regs->gintsts, gintsts.d32); -+ -+ #ifdef __DYN_SOF_INTR__ -+ if(!with_count_down) -+ ifxusb_mreg(&_ifxhcd->core_if.core_global_regs->gintmsk, gintsts.d32,0); -+ #endif -+#ifdef __USE_TIMER_4_SOF__ -+ wait_for_sof &= 0xFFFF; // reduce to 16 Bits. -+ -+ if(wait_for_sof == 1) { -+ // enable SOF -+ gint_data_t gintsts; -+ gintsts.d32=0; -+ gintsts.b.sofintr = 1; -+ ifxusb_mreg(&_ifxhcd->core_if.core_global_regs->gintmsk, 0,gintsts.d32); -+ } else { -+ // disable SOF -+ ifxusb_mreg(&_ifxhcd->core_if.core_global_regs->gintmsk, gintsts.d32,0); -+ if (wait_for_sof > 1) { -+ // use timer, not SOF IRQ -+ hprt0_data_t hprt0; -+ ktime_t ktime; -+ hprt0.d32 = ifxusb_read_hprt0 (&_ifxhcd->core_if); -+ if (hprt0.b.prtspd == IFXUSB_HPRT0_PRTSPD_HIGH_SPEED) { -+ ktime = ktime_set(0, wait_for_sof * 125 * 1000); /*--- wakeup in n*125usec ---*/ -+ } else { -+ ktime = ktime_set(0, wait_for_sof * (1000*1000)); /*--- wakeup in n*1000usec ---*/ -+ } -+ hrtimer_start(&_ifxhcd->hr_timer, ktime, HRTIMER_MODE_REL); -+ } -+ } -+#endif -+ } -+ _ifxhcd->lastframe=hfnum.b.frnum; -+ return 1; -+} -+ -+ -+ -+/* There are multiple conditions that can cause a port interrupt. This function -+ * determines which interrupt conditions have occurred and handles them -+ * appropriately. */ -+static int32_t handle_port_intr (ifxhcd_hcd_t *_ifxhcd) -+{ -+ int retval = 0; -+ hprt0_data_t hprt0; -+ hprt0_data_t hprt0_modify; -+ -+ hprt0.d32 = -+ hprt0_modify.d32 = ifxusb_rreg(_ifxhcd->core_if.hprt0); -+ -+ /* Clear appropriate bits in HPRT0 to clear the interrupt bit in -+ * GINTSTS */ -+ -+ hprt0_modify.b.prtena = 0; -+ hprt0_modify.b.prtconndet = 0; -+ hprt0_modify.b.prtenchng = 0; -+ hprt0_modify.b.prtovrcurrchng = 0; -+ -+ /* Port Connect Detected -+ * Set flag and clear if detected */ -+ if (hprt0.b.prtconndet) { -+ IFX_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x " -+ "Port Connect Detected--\n", hprt0.d32); -+ _ifxhcd->flags.b.port_connect_status_change = 1; -+ _ifxhcd->flags.b.port_connect_status = 1; -+ hprt0_modify.b.prtconndet = 1; -+ -+ /* The Hub driver asserts a reset when it sees port connect -+ * status change flag */ -+ retval |= 1; -+ } -+ -+ /* Port Enable Changed -+ * Clear if detected - Set internal flag if disabled */ -+ if (hprt0.b.prtenchng) { -+ -+ IFX_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " -+ "Port Enable Changed--\n", hprt0.d32); -+ hprt0_modify.b.prtenchng = 1; -+ if (hprt0.b.prtena == 1) -+ /* Port has been enabled set the reset change flag */ -+ _ifxhcd->flags.b.port_reset_change = 1; -+ else -+ _ifxhcd->flags.b.port_enable_change = 1; -+ retval |= 1; -+ } -+ -+ /* Overcurrent Change Interrupt */ -+ -+ if (hprt0.b.prtovrcurrchng) { -+ IFX_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " -+ "Port Overcurrent Changed--\n", hprt0.d32); -+ _ifxhcd->flags.b.port_over_current_change = 1; -+ hprt0_modify.b.prtovrcurrchng = 1; -+ retval |= 1; -+ } -+ -+ /* Clear Port Interrupts */ -+ ifxusb_wreg(_ifxhcd->core_if.hprt0, hprt0_modify.d32); -+ return retval; -+} -+ -+/* -+ * This interrupt indicates that SUSPEND state has been detected on -+ * the USB. -+ * No Functioning in Host Mode -+ */ -+static int32_t handle_usb_suspend_intr(ifxhcd_hcd_t *_ifxhcd) -+{ -+ gint_data_t gintsts; -+ IFX_DEBUGP("USB SUSPEND RECEIVED!\n"); -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.usbsuspend = 1; -+ ifxusb_wreg(&_ifxhcd->core_if.core_global_regs->gintsts, gintsts.d32); -+ return 1; -+} -+ -+/* -+ * This interrupt indicates that the IFXUSB controller has detected a -+ * resume or remote wakeup sequence. If the IFXUSB controller is in -+ * low power mode, the handler must brings the controller out of low -+ * power mode. The controller automatically begins resume -+ * signaling. The handler schedules a time to stop resume signaling. -+ */ -+static int32_t handle_wakeup_detected_intr(ifxhcd_hcd_t *_ifxhcd) -+{ -+ gint_data_t gintsts; -+ hprt0_data_t hprt0 = {.d32=0}; -+ pcgcctl_data_t pcgcctl = {.d32=0}; -+ ifxusb_core_if_t *core_if = &_ifxhcd->core_if; -+ -+ IFX_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n"); -+ -+ /* -+ * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms -+ * so that OPT tests pass with all PHYs). -+ */ -+ /* Restart the Phy Clock */ -+ pcgcctl.b.stoppclk = 1; -+ ifxusb_mreg(core_if->pcgcctl, pcgcctl.d32, 0); -+ UDELAY(10); -+ -+ /* Now wait for 70 ms. */ -+ hprt0.d32 = ifxusb_read_hprt0( core_if ); -+ IFX_DEBUGPL(DBG_ANY,"Resume: HPRT0=%0x\n", hprt0.d32); -+ MDELAY(70); -+ hprt0.b.prtres = 0; /* Resume */ -+ ifxusb_wreg(core_if->hprt0, hprt0.d32); -+ IFX_DEBUGPL(DBG_ANY,"Clear Resume: HPRT0=%0x\n", ifxusb_rreg(core_if->hprt0)); -+ -+ /* Clear interrupt */ -+ gintsts.d32 = 0; -+ gintsts.b.wkupintr = 1; -+ ifxusb_wreg(&core_if->core_global_regs->gintsts, gintsts.d32); -+ return 1; -+} -+ -+/* -+ * This interrupt indicates that a device is initiating the Session -+ * Request Protocol to request the host to turn on bus power so a new -+ * session can begin. The handler responds by turning on bus power. If -+ * the DWC_otg controller is in low power mode, the handler brings the -+ * controller out of low power mode before turning on bus power. -+ */ -+static int32_t handle_session_req_intr(ifxhcd_hcd_t *_ifxhcd) -+{ -+ /* Clear interrupt */ -+ gint_data_t gintsts = { .d32 = 0 }; -+ gintsts.b.sessreqintr = 1; -+ ifxusb_wreg(&_ifxhcd->core_if.core_global_regs->gintsts, gintsts.d32); -+ return 1; -+} -+ -+/* -+ * This interrupt indicates that a device has been disconnected from -+ * the root port. -+ */ -+static int32_t handle_disconnect_intr(ifxhcd_hcd_t *_ifxhcd) -+{ -+ gint_data_t gintsts; -+ -+ ifxhcd_disconnect(_ifxhcd); -+ -+ gintsts.d32 = 0; -+ gintsts.b.disconnect = 1; -+ ifxusb_wreg(&_ifxhcd->core_if.core_global_regs->gintsts, gintsts.d32); -+ return 1; -+} -+ -+/* -+ * This function handles the Connector ID Status Change Interrupt. It -+ * reads the OTG Interrupt Register (GOTCTL) to determine whether this -+ * is a Device to Host Mode transition or a Host Mode to Device -+ * Transition. -+ * This only occurs when the cable is connected/removed from the PHY -+ * connector. -+ */ -+static int32_t handle_conn_id_status_change_intr(ifxhcd_hcd_t *_ifxhcd) -+{ -+ gint_data_t gintsts; -+ -+ IFX_WARN("ID Status Change Interrupt: currently in %s mode\n", -+ ifxusb_mode(&_ifxhcd->core_if) ? "Host" : "Device"); -+ -+ gintsts.d32 = 0; -+ gintsts.b.conidstschng = 1; -+ ifxusb_wreg(&_ifxhcd->core_if.core_global_regs->gintsts, gintsts.d32); -+ return 1; -+} -+ -+static int32_t handle_otg_intr(ifxhcd_hcd_t *_ifxhcd) -+{ -+ ifxusb_core_global_regs_t *global_regs = _ifxhcd->core_if.core_global_regs; -+ gotgint_data_t gotgint; -+ gotgint.d32 = ifxusb_rreg( &global_regs->gotgint); -+ /* Clear GOTGINT */ -+ ifxusb_wreg (&global_regs->gotgint, gotgint.d32); -+ return 1; -+} -+ -+/** This function will log a debug message */ -+static int32_t handle_mode_mismatch_intr(ifxhcd_hcd_t *_ifxhcd) -+{ -+ gint_data_t gintsts; -+ -+ IFX_WARN("Mode Mismatch Interrupt: currently in %s mode\n", -+ ifxusb_mode(&_ifxhcd->core_if) ? "Host" : "Device"); -+ gintsts.d32 = 0; -+ gintsts.b.modemismatch = 1; -+ ifxusb_wreg(&_ifxhcd->core_if.core_global_regs->gintsts, gintsts.d32); -+ return 1; -+} -+ -+/** This function handles interrupts for the HCD. */ -+int32_t ifxhcd_handle_intr (ifxhcd_hcd_t *_ifxhcd) -+{ -+ int retval = 0; -+ -+ ifxusb_core_if_t *core_if = &_ifxhcd->core_if; -+ /* AVM/BC 20101111 Unnecesary variable removed*/ -+ //gint_data_t gintsts,gintsts2; -+ gint_data_t gintsts; -+ -+ /* Check if HOST Mode */ -+ if (ifxusb_is_device_mode(core_if)) -+ { -+ IFX_ERROR("%s() CRITICAL! IN DEVICE MODE\n", __func__); -+ return 0; -+ } -+ -+ gintsts.d32 = ifxusb_read_core_intr(core_if); -+ -+ if (!gintsts.d32) -+ return 0; -+ -+ //Common INT -+ if (gintsts.b.modemismatch) -+ { -+ retval |= handle_mode_mismatch_intr(_ifxhcd); -+ gintsts.b.modemismatch=0; -+ } -+ if (gintsts.b.otgintr) -+ { -+ retval |= handle_otg_intr(_ifxhcd); -+ gintsts.b.otgintr=0; -+ } -+ if (gintsts.b.conidstschng) -+ { -+ retval |= handle_conn_id_status_change_intr(_ifxhcd); -+ gintsts.b.conidstschng=0; -+ } -+ if (gintsts.b.disconnect) -+ { -+ retval |= handle_disconnect_intr(_ifxhcd); -+ gintsts.b.disconnect=0; -+ } -+ if (gintsts.b.sessreqintr) -+ { -+ retval |= handle_session_req_intr(_ifxhcd); -+ gintsts.b.sessreqintr=0; -+ } -+ if (gintsts.b.wkupintr) -+ { -+ retval |= handle_wakeup_detected_intr(_ifxhcd); -+ gintsts.b.wkupintr=0; -+ } -+ if (gintsts.b.usbsuspend) -+ { -+ retval |= handle_usb_suspend_intr(_ifxhcd); -+ gintsts.b.usbsuspend=0; -+ } -+ -+ //Host Int -+ if (gintsts.b.sofintr) -+ { -+ retval |= handle_sof_intr (_ifxhcd); -+ gintsts.b.sofintr=0; -+ } -+ if (gintsts.b.portintr) -+ { -+ retval |= handle_port_intr (_ifxhcd); -+ gintsts.b.portintr=0; -+ } -+ if (gintsts.b.hcintr) -+ { -+ int i; -+ haint_data_t haint; -+ haint.d32 = ifxusb_read_host_all_channels_intr(core_if); -+ for (i=0; i< core_if->params.host_channels; i++) -+ if (haint.b2.chint & (1 << i)) -+ retval |= handle_hc_n_intr (_ifxhcd, i); -+ gintsts.b.hcintr=0; -+ } -+ return retval; -+} ---- /dev/null -+++ b/drivers/usb/ifxhcd/ifxhcd_queue.c -@@ -0,0 +1,418 @@ -+/***************************************************************************** -+ ** FILE NAME : ifxhcd_queue.c -+ ** PROJECT : IFX USB sub-system V3 -+ ** MODULES : IFX USB sub-system Host and Device driver -+ ** SRC VERSION : 1.0 -+ ** DATE : 1/Jan/2009 -+ ** AUTHOR : Chen, Howard -+ ** DESCRIPTION : This file contains the functions to manage Queue Heads and Queue -+ ** Transfer Descriptors. -+ *****************************************************************************/ -+ -+/*! -+ \file ifxhcd_queue.c -+ \ingroup IFXUSB_DRIVER_V3 -+ \brief This file contains the functions to manage Queue Heads and Queue -+ Transfer Descriptors. -+*/ -+#include -+#include "ifxusb_version.h" -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "ifxusb_plat.h" -+#include "ifxusb_regs.h" -+#include "ifxusb_cif.h" -+#include "ifxhcd.h" -+ -+#ifdef __EPQD_DESTROY_TIMEOUT__ -+ #define epqh_self_destroy_timeout 5 -+ static void eqph_destroy_func(unsigned long _ptr) -+ { -+ ifxhcd_epqh_t *epqh=(ifxhcd_epqh_t *)_ptr; -+ if(epqh) -+ { -+ ifxhcd_epqh_free (epqh); -+ } -+ } -+#endif -+ -+#define SCHEDULE_SLOP 10 -+ -+/*! -+ \brief This function allocates and initializes a EPQH. -+ -+ \param _ifxhcd The HCD state structure for the USB Host controller. -+ \param[in] _urb Holds the information about the device/endpoint that we need -+ to initialize the EPQH. -+ -+ \return Returns pointer to the newly allocated EPQH, or NULL on error. -+ */ -+ifxhcd_epqh_t *ifxhcd_epqh_create (ifxhcd_hcd_t *_ifxhcd, struct urb *_urb) -+{ -+ ifxhcd_epqh_t *epqh; -+ -+ hprt0_data_t hprt0; -+ struct usb_host_endpoint *sysep = ifxhcd_urb_to_endpoint(_urb); -+ -+ /* Allocate memory */ -+// epqh=(ifxhcd_epqh_t *) kmalloc (sizeof(ifxhcd_epqh_t), GFP_KERNEL); -+ epqh=(ifxhcd_epqh_t *) kmalloc (sizeof(ifxhcd_epqh_t), GFP_ATOMIC); -+ -+ if(epqh == NULL) -+ return NULL; -+ -+ memset (epqh, 0, sizeof (ifxhcd_epqh_t)); -+ -+ epqh->sysep=sysep; -+ -+ /* Initialize EPQH */ -+ switch (usb_pipetype(_urb->pipe)) -+ { -+ case PIPE_CONTROL : epqh->ep_type = IFXUSB_EP_TYPE_CTRL; break; -+ case PIPE_BULK : epqh->ep_type = IFXUSB_EP_TYPE_BULK; break; -+ case PIPE_ISOCHRONOUS: epqh->ep_type = IFXUSB_EP_TYPE_ISOC; break; -+ case PIPE_INTERRUPT : epqh->ep_type = IFXUSB_EP_TYPE_INTR; break; -+ } -+ -+ //epqh->data_toggle = IFXUSB_HC_PID_DATA0; -+ -+ epqh->mps = usb_maxpacket(_urb->dev, _urb->pipe, !(usb_pipein(_urb->pipe))); -+ -+ hprt0.d32 = ifxusb_read_hprt0 (&_ifxhcd->core_if); -+ -+ INIT_LIST_HEAD(&epqh->urbd_list); -+ INIT_LIST_HEAD(&epqh->epqh_list_entry); -+ epqh->hc = NULL; -+ -+ epqh->dump_buf = ifxusb_alloc_buf(epqh->mps, 0); -+ -+ /* FS/LS Enpoint on HS Hub -+ * NOT virtual root hub */ -+ epqh->need_split = 0; -+ epqh->pkt_count_limit=0; -+ if(epqh->ep_type == IFXUSB_EP_TYPE_BULK && !(usb_pipein(_urb->pipe)) ) -+ epqh->pkt_count_limit=4; -+ if (hprt0.b.prtspd == IFXUSB_HPRT0_PRTSPD_HIGH_SPEED && -+ ((_urb->dev->speed == USB_SPEED_LOW) || -+ (_urb->dev->speed == USB_SPEED_FULL)) && -+ (_urb->dev->tt) && (_urb->dev->tt->hub->devnum != 1)) -+ { -+ IFX_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n", -+ usb_pipeendpoint(_urb->pipe), _urb->dev->tt->hub->devnum, -+ _urb->dev->ttport); -+ epqh->need_split = 1; -+ epqh->pkt_count_limit=1; -+ } -+ -+ if (epqh->ep_type == IFXUSB_EP_TYPE_INTR || -+ epqh->ep_type == IFXUSB_EP_TYPE_ISOC) -+ { -+ /* Compute scheduling parameters once and save them. */ -+ epqh->interval = _urb->interval; -+ if(epqh->need_split) -+ epqh->interval *= 8; -+ } -+ -+ epqh->period_counter=0; -+ epqh->is_active=0; -+ -+ #ifdef __EPQD_DESTROY_TIMEOUT__ -+ /* Start a timer for this transfer. */ -+ init_timer(&epqh->destroy_timer); -+ epqh->destroy_timer.function = eqph_destroy_func; -+ epqh->destroy_timer.data = (unsigned long)(epqh); -+ #endif -+ -+ #ifdef __DEBUG__ -+ IFX_DEBUGPL(DBG_HCD , "IFXUSB HCD EPQH Initialized\n"); -+ IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - epqh = %p\n", epqh); -+ IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - Device Address = %d EP %d, %s\n", -+ _urb->dev->devnum, -+ usb_pipeendpoint(_urb->pipe), -+ usb_pipein(_urb->pipe) == USB_DIR_IN ? "IN" : "OUT"); -+ IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - Speed = %s\n", -+ ({ char *speed; switch (_urb->dev->speed) { -+ case USB_SPEED_LOW: speed = "low" ; break; -+ case USB_SPEED_FULL: speed = "full"; break; -+ case USB_SPEED_HIGH: speed = "high"; break; -+ default: speed = "?"; break; -+ }; speed;})); -+ IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - Type = %s\n", -+ ({ -+ char *type; switch (epqh->ep_type) -+ { -+ case IFXUSB_EP_TYPE_ISOC: type = "isochronous"; break; -+ case IFXUSB_EP_TYPE_INTR: type = "interrupt" ; break; -+ case IFXUSB_EP_TYPE_CTRL: type = "control" ; break; -+ case IFXUSB_EP_TYPE_BULK: type = "bulk" ; break; -+ default: type = "?"; break; -+ }; -+ type; -+ })); -+ if (epqh->ep_type == IFXUSB_EP_TYPE_INTR) -+ IFX_DEBUGPL(DBG_HCDV, "IFXUSB HCD EPQH - interval = %d\n", epqh->interval); -+ #endif -+ -+ return epqh; -+} -+ -+ -+ -+ -+ -+ -+/*! -+ \brief Free the EPQH. EPQH should already be removed from a list. -+ URBD list should already be empty if called from URB Dequeue. -+ -+ \param[in] _epqh The EPQH to free. -+ */ -+void ifxhcd_epqh_free (ifxhcd_epqh_t *_epqh) -+{ -+ unsigned long flags; -+ -+ if(_epqh->sysep) _epqh->sysep->hcpriv=NULL; -+ _epqh->sysep=NULL; -+ -+ if(!_epqh) -+ return; -+ -+ /* Free each QTD in the QTD list */ -+ local_irq_save (flags); -+ if (!list_empty(&_epqh->urbd_list)) -+ IFX_WARN("%s() invalid epqh state\n",__func__); -+ -+ #if defined(__UNALIGNED_BUFFER_ADJ__) -+ if(_epqh->aligned_buf) -+ ifxusb_free_buf(_epqh->aligned_buf); -+ if(_epqh->aligned_setup) -+ ifxusb_free_buf(_epqh->aligned_setup); -+ #endif -+ -+ if (!list_empty(&_epqh->epqh_list_entry)) -+ list_del_init(&_epqh->epqh_list_entry); -+ -+ #ifdef __EPQD_DESTROY_TIMEOUT__ -+ del_timer(&_epqh->destroy_timer); -+ #endif -+ if(_epqh->dump_buf) -+ ifxusb_free_buf(_epqh->dump_buf); -+ _epqh->dump_buf=0; -+ -+ -+ kfree (_epqh); -+ local_irq_restore (flags); -+} -+ -+/*! -+ \brief This function adds a EPQH to -+ -+ \return 0 if successful, negative error code otherwise. -+ */ -+void ifxhcd_epqh_ready(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh) -+{ -+ unsigned long flags; -+ local_irq_save(flags); -+ if (list_empty(&_epqh->epqh_list_entry)) -+ { -+ #ifdef __EN_ISOC__ -+ if (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC) -+ list_add_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_ready); -+ else -+ #endif -+ if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR) -+ list_add_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_ready); -+ else -+ list_add_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_ready); -+ _epqh->is_active=0; -+ } -+ else if(!_epqh->is_active) -+ { -+ #ifdef __EN_ISOC__ -+ if (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC) -+ list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_ready); -+ else -+ #endif -+ if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR) -+ list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_ready); -+ else -+ list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_ready); -+ } -+ #ifdef __EPQD_DESTROY_TIMEOUT__ -+ del_timer(&_epqh->destroy_timer); -+ #endif -+ local_irq_restore(flags); -+} -+ -+void ifxhcd_epqh_active(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh) -+{ -+ unsigned long flags; -+ local_irq_save(flags); -+ if (list_empty(&_epqh->epqh_list_entry)) -+ IFX_WARN("%s() invalid epqh state\n",__func__); -+ #ifdef __EN_ISOC__ -+ if (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC) -+ list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_active); -+ else -+ #endif -+ if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR) -+ list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_active); -+ else -+ list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_active); -+ _epqh->is_active=1; -+ #ifdef __EPQD_DESTROY_TIMEOUT__ -+ del_timer(&_epqh->destroy_timer); -+ #endif -+ local_irq_restore(flags); -+} -+ -+void ifxhcd_epqh_idle(ifxhcd_hcd_t *_ifxhcd, ifxhcd_epqh_t *_epqh) -+{ -+ unsigned long flags; -+ local_irq_save(flags); -+ -+ if (list_empty(&_epqh->urbd_list)) -+ { -+ if(_epqh->ep_type == IFXUSB_EP_TYPE_ISOC || _epqh->ep_type == IFXUSB_EP_TYPE_INTR) -+ { -+ list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_stdby); -+ } -+ else -+ { -+ list_del_init(&_epqh->epqh_list_entry); -+ #ifdef __EPQD_DESTROY_TIMEOUT__ -+ del_timer(&_epqh->destroy_timer); -+ _epqh->destroy_timer.expires = jiffies + (HZ*epqh_self_destroy_timeout); -+ add_timer(&_epqh->destroy_timer ); -+ #endif -+ } -+ } -+ else -+ { -+ #ifdef __EN_ISOC__ -+ if (_epqh->ep_type == IFXUSB_EP_TYPE_ISOC) -+ list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_isoc_ready); -+ else -+ #endif -+ if(_epqh->ep_type == IFXUSB_EP_TYPE_INTR) -+ list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_intr_ready); -+ else -+ list_move_tail(&_epqh->epqh_list_entry, &_ifxhcd->epqh_np_ready); -+ } -+ _epqh->is_active=0; -+ local_irq_restore(flags); -+} -+ -+ -+void ifxhcd_epqh_idle_periodic(ifxhcd_epqh_t *_epqh) -+{ -+ unsigned long flags; -+ if(_epqh->ep_type != IFXUSB_EP_TYPE_ISOC && _epqh->ep_type != IFXUSB_EP_TYPE_INTR) -+ return; -+ -+ local_irq_save(flags); -+ -+ if (list_empty(&_epqh->epqh_list_entry)) -+ IFX_WARN("%s() invalid epqh state\n",__func__); -+ if (!list_empty(&_epqh->urbd_list)) -+ IFX_WARN("%s() invalid epqh state(not empty)\n",__func__); -+ -+ _epqh->is_active=0; -+ list_del_init(&_epqh->epqh_list_entry); -+ #ifdef __EPQD_DESTROY_TIMEOUT__ -+ del_timer(&_epqh->destroy_timer); -+ _epqh->destroy_timer.expires = jiffies + (HZ*epqh_self_destroy_timeout); -+ add_timer(&_epqh->destroy_timer ); -+ #endif -+ -+ local_irq_restore(flags); -+} -+ -+ -+int ifxhcd_urbd_create (ifxhcd_hcd_t *_ifxhcd,struct urb *_urb) -+{ -+ ifxhcd_urbd_t *urbd; -+ struct usb_host_endpoint *sysep; -+ ifxhcd_epqh_t *epqh; -+ unsigned long flags; -+ /* == AVM/WK 20100714 retval correctly initialized ==*/ -+ int retval = -ENOMEM; -+ -+ /*== AVM/BC 20100630 - Spinlock ==*/ -+ //local_irq_save(flags); -+ SPIN_LOCK_IRQSAVE(&_ifxhcd->lock, flags); -+ -+// urbd = (ifxhcd_urbd_t *) kmalloc (sizeof(ifxhcd_urbd_t), GFP_KERNEL); -+ urbd = (ifxhcd_urbd_t *) kmalloc (sizeof(ifxhcd_urbd_t), GFP_ATOMIC); -+ if (urbd != NULL) /* Initializes a QTD structure.*/ -+ { -+ retval = 0; -+ memset (urbd, 0, sizeof (ifxhcd_urbd_t)); -+ -+ sysep = ifxhcd_urb_to_endpoint(_urb); -+ epqh = (ifxhcd_epqh_t *)sysep->hcpriv; -+ if (epqh == NULL) -+ { -+ epqh = ifxhcd_epqh_create (_ifxhcd, _urb); -+ if (epqh == NULL) -+ { -+ retval = -ENOSPC; -+ kfree(urbd); -+ //local_irq_restore (flags); -+ SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); -+ return retval; -+ } -+ sysep->hcpriv = epqh; -+ } -+ -+ INIT_LIST_HEAD(&urbd->urbd_list_entry); -+ -+ /*== AVM/BC 20100630 - 2.6.28 needs HCD link/unlink URBs ==*/ -+ retval = usb_hcd_link_urb_to_ep(ifxhcd_to_syshcd(_ifxhcd), _urb); -+ -+ if (unlikely(retval)){ -+ kfree(urbd); -+ kfree(epqh); -+ SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); -+ return retval; -+ } -+ -+ list_add_tail(&urbd->urbd_list_entry, &epqh->urbd_list); -+ urbd->urb = _urb; -+ _urb->hcpriv = urbd; -+ -+ urbd->epqh=epqh; -+ urbd->is_in=usb_pipein(_urb->pipe) ? 1 : 0;; -+ -+ urbd->xfer_len=_urb->transfer_buffer_length; -+#define URB_NO_SETUP_DMA_MAP 0 -+ -+ if(urbd->xfer_len>0) -+ { -+ if(_urb->transfer_flags && URB_NO_TRANSFER_DMA_MAP) -+ urbd->xfer_buff = (uint8_t *) (KSEG1ADDR((uint32_t *)_urb->transfer_dma)); -+ else -+ urbd->xfer_buff = (uint8_t *) _urb->transfer_buffer; -+ } -+ if(epqh->ep_type == IFXUSB_EP_TYPE_CTRL) -+ { -+ if(_urb->transfer_flags && URB_NO_SETUP_DMA_MAP) -+ urbd->setup_buff = (uint8_t *) (KSEG1ADDR((uint32_t *)_urb->setup_dma)); -+ else -+ urbd->setup_buff = (uint8_t *) _urb->setup_packet; -+ } -+ } -+ //local_irq_restore (flags); -+ SPIN_UNLOCK_IRQRESTORE(&_ifxhcd->lock, flags); -+ return retval; -+} -+ ---- /dev/null -+++ b/drivers/usb/ifxhcd/ifxusb_cif.c -@@ -0,0 +1,1458 @@ -+/***************************************************************************** -+ ** FILE NAME : ifxusb_cif.c -+ ** PROJECT : IFX USB sub-system V3 -+ ** MODULES : IFX USB sub-system Host and Device driver -+ ** SRC VERSION : 1.0 -+ ** DATE : 1/Jan/2009 -+ ** AUTHOR : Chen, Howard -+ ** DESCRIPTION : The Core Interface provides basic services for accessing and -+ ** managing the IFX USB hardware. These services are used by both the -+ ** Host Controller Driver and the Peripheral Controller Driver. -+ *****************************************************************************/ -+ -+/*! -+ \file ifxusb_cif.c -+ \ingroup IFXUSB_DRIVER_V3 -+ \brief This file contains the interface to the IFX USB Core. -+*/ -+ -+#include -+#include -+#include "ifxusb_version.h" -+ -+#include -+#include -+ -+ -+#include -+#include -+#include -+#include -+ -+#if defined(__UEIP__) -+// #include -+// #include -+#endif -+ -+ -+#include "ifxusb_plat.h" -+#include "ifxusb_regs.h" -+#include "ifxusb_cif.h" -+ -+ -+#ifdef __IS_DEVICE__ -+ #include "ifxpcd.h" -+#endif -+ -+#ifdef __IS_HOST__ -+ #include "ifxhcd.h" -+#endif -+ -+#include -+ -+#include -+ -+#if defined(__UEIP__) -+// #include -+ //#include -+#endif -+ -+//#include -+//#include -+#if defined(__UEIP__) -+// #include -+ //#include -+#endif -+ -+ -+ -+#if defined(__UEIP__) -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) -+ #ifndef USB_CTRL_PMU_SETUP -+ #define USB_CTRL_PMU_SETUP(__x) USB0_CTRL_PMU_SETUP(__x) -+ #endif -+ #ifndef USB_PHY_PMU_SETUP -+ #define USB_PHY_PMU_SETUP(__x) USB0_PHY_PMU_SETUP(__x) -+ #endif -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) -+#endif // defined(__UEIP__) -+ -+/*! -+ \brief This function is called to allocate buffer of specified size. -+ The allocated buffer is mapped into DMA accessable address. -+ \param size Size in BYTE to be allocated -+ \param clear 0: don't do clear after buffer allocated, other: do clear to zero -+ \return 0/NULL: Fail; uncached pointer of allocated buffer -+ */ -+void *ifxusb_alloc_buf(size_t size, int clear) -+{ -+ uint32_t *cached,*uncached; -+ uint32_t totalsize,page; -+ -+ if(!size) -+ return 0; -+ -+ size=(size+3)&0xFFFFFFFC; -+ totalsize=size + 12; -+ page=get_order(totalsize); -+ -+ cached = (void *) __get_free_pages(( GFP_ATOMIC | GFP_DMA), page); -+ -+ if(!cached) -+ { -+ IFX_PRINT("%s Allocation Failed size:%d\n",__func__,size); -+ return NULL; -+ } -+ -+ uncached = (uint32_t *)(KSEG1ADDR(cached)); -+ if(clear) -+ memset(uncached, 0, totalsize); -+ -+ *(uncached+0)=totalsize; -+ *(uncached+1)=page; -+ *(uncached+2)=(uint32_t)cached; -+ return (void *)(uncached+3); -+} -+ -+ -+/*! -+ \brief This function is called to free allocated buffer. -+ \param vaddr the uncached pointer of the buffer -+ */ -+void ifxusb_free_buf(void *vaddr) -+{ -+ uint32_t totalsize,page; -+ uint32_t *cached,*uncached; -+ -+ if(vaddr != NULL) -+ { -+ uncached=vaddr; -+ uncached-=3; -+ totalsize=*(uncached+0); -+ page=*(uncached+1); -+ cached=(uint32_t *)(*(uncached+2)); -+ if(totalsize && page==get_order(totalsize) && cached==(uint32_t *)(KSEG0ADDR(uncached))) -+ { -+ free_pages((unsigned long)cached, page); -+ return; -+ } -+ // the memory is not allocated by ifxusb_alloc_buf. Allowed but must be careful. -+ return; -+ } -+} -+ -+ -+ -+/*! -+ \brief This function is called to initialize the IFXUSB CSR data -+ structures. The register addresses in the device and host -+ structures are initialized from the base address supplied by the -+ caller. The calling function must make the OS calls to get the -+ base address of the IFXUSB controller registers. -+ -+ \param _core_if Pointer of core_if structure -+ \param _irq irq number -+ \param _reg_base_addr Base address of IFXUSB core registers -+ \param _fifo_base_addr Fifo base address -+ \param _fifo_dbg_addr Fifo debug address -+ \return 0: success; -+ */ -+int ifxusb_core_if_init(ifxusb_core_if_t *_core_if, -+ int _irq, -+ uint32_t _reg_base_addr, -+ uint32_t _fifo_base_addr, -+ uint32_t _fifo_dbg_addr) -+{ -+ int retval = 0; -+ uint32_t *reg_base =NULL; -+ uint32_t *fifo_base =NULL; -+ uint32_t *fifo_dbg =NULL; -+ -+ int i; -+ -+ IFX_DEBUGPL(DBG_CILV, "%s(%p,%d,0x%08X,0x%08X,0x%08X)\n", __func__, -+ _core_if, -+ _irq, -+ _reg_base_addr, -+ _fifo_base_addr, -+ _fifo_dbg_addr); -+ -+ if( _core_if == NULL) -+ { -+ IFX_ERROR("%s() invalid _core_if\n", __func__); -+ retval = -ENOMEM; -+ goto fail; -+ } -+ -+ //memset(_core_if, 0, sizeof(ifxusb_core_if_t)); -+ -+ _core_if->irq=_irq; -+ -+ reg_base =ioremap_nocache(_reg_base_addr , IFXUSB_IOMEM_SIZE ); -+ fifo_base =ioremap_nocache(_fifo_base_addr, IFXUSB_FIFOMEM_SIZE); -+ fifo_dbg =ioremap_nocache(_fifo_dbg_addr , IFXUSB_FIFODBG_SIZE); -+ if( reg_base == NULL || fifo_base == NULL || fifo_dbg == NULL) -+ { -+ IFX_ERROR("%s() usb ioremap() failed\n", __func__); -+ retval = -ENOMEM; -+ goto fail; -+ } -+ -+ _core_if->core_global_regs = (ifxusb_core_global_regs_t *)reg_base; -+ -+ /* -+ * Attempt to ensure this device is really a IFXUSB Controller. -+ * Read and verify the SNPSID register contents. The value should be -+ * 0x45F42XXX -+ */ -+ { -+ int32_t snpsid; -+ snpsid = ifxusb_rreg(&_core_if->core_global_regs->gsnpsid); -+ if ((snpsid & 0xFFFFF000) != 0x4F542000) -+ { -+ IFX_ERROR("%s() snpsid error(0x%08x) failed\n", __func__,snpsid); -+ retval = -EINVAL; -+ goto fail; -+ } -+ _core_if->snpsid=snpsid; -+ } -+ -+ #ifdef __IS_HOST__ -+ _core_if->host_global_regs = (ifxusb_host_global_regs_t *) -+ ((uint32_t)reg_base + IFXUSB_HOST_GLOBAL_REG_OFFSET); -+ _core_if->hprt0 = (uint32_t*)((uint32_t)reg_base + IFXUSB_HOST_PORT_REGS_OFFSET); -+ -+ for (i=0; ihc_regs[i] = (ifxusb_hc_regs_t *) -+ ((uint32_t)reg_base + IFXUSB_HOST_CHAN_REGS_OFFSET + -+ (i * IFXUSB_CHAN_REGS_OFFSET)); -+ IFX_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n", -+ i, &_core_if->hc_regs[i]->hcchar); -+ } -+ #endif //__IS_HOST__ -+ -+ #ifdef __IS_DEVICE__ -+ _core_if->dev_global_regs = -+ (ifxusb_device_global_regs_t *)((uint32_t)reg_base + IFXUSB_DEV_GLOBAL_REG_OFFSET); -+ -+ for (i=0; iin_ep_regs[i] = (ifxusb_dev_in_ep_regs_t *) -+ ((uint32_t)reg_base + IFXUSB_DEV_IN_EP_REG_OFFSET + -+ (i * IFXUSB_EP_REG_OFFSET)); -+ _core_if->out_ep_regs[i] = (ifxusb_dev_out_ep_regs_t *) -+ ((uint32_t)reg_base + IFXUSB_DEV_OUT_EP_REG_OFFSET + -+ (i * IFXUSB_EP_REG_OFFSET)); -+ IFX_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p/%p %p/0x%08X/0x%08X\n", -+ i, &_core_if->in_ep_regs[i]->diepctl, _core_if->in_ep_regs[i], -+ reg_base,IFXUSB_DEV_IN_EP_REG_OFFSET,(i * IFXUSB_EP_REG_OFFSET) -+ ); -+ IFX_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p/%p %p/0x%08X/0x%08X\n", -+ i, &_core_if->out_ep_regs[i]->doepctl, _core_if->out_ep_regs[i], -+ reg_base,IFXUSB_DEV_OUT_EP_REG_OFFSET,(i * IFXUSB_EP_REG_OFFSET) -+ ); -+ } -+ #endif //__IS_DEVICE__ -+ -+ /* Setting the FIFO and other Address. */ -+ for (i=0; idata_fifo[i] = fifo_base + (i * IFXUSB_DATA_FIFO_SIZE); -+ IFX_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n", -+ i, (unsigned)_core_if->data_fifo[i]); -+ } -+ -+ _core_if->data_fifo_dbg = fifo_dbg; -+ _core_if->pcgcctl = (uint32_t*)(((uint32_t)reg_base) + IFXUSB_PCGCCTL_OFFSET); -+ -+ /* -+ * Store the contents of the hardware configuration registers here for -+ * easy access later. -+ */ -+ _core_if->hwcfg1.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg1); -+ _core_if->hwcfg2.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg2); -+ _core_if->hwcfg3.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg3); -+ _core_if->hwcfg4.d32 = ifxusb_rreg(&_core_if->core_global_regs->ghwcfg4); -+ -+ IFX_DEBUGPL(DBG_CILV,"hwcfg1=%08x\n",_core_if->hwcfg1.d32); -+ IFX_DEBUGPL(DBG_CILV,"hwcfg2=%08x\n",_core_if->hwcfg2.d32); -+ IFX_DEBUGPL(DBG_CILV,"hwcfg3=%08x\n",_core_if->hwcfg3.d32); -+ IFX_DEBUGPL(DBG_CILV,"hwcfg4=%08x\n",_core_if->hwcfg4.d32); -+ -+ -+ #ifdef __DED_FIFO__ -+ IFX_PRINT("Waiting for PHY Clock Lock!\n"); -+ while(!( ifxusb_rreg(&_core_if->core_global_regs->grxfsiz) & (1<<9))) -+ { -+ } -+ IFX_PRINT("PHY Clock Locked!\n"); -+ //ifxusb_clean_spram(_core_if,128*1024/4); -+ #endif -+ -+ /* Create new workqueue and init works */ -+#if 0 -+ _core_if->wq_usb = create_singlethread_workqueue(_core_if->core_name); -+ -+ if(_core_if->wq_usb == 0) -+ { -+ IFX_DEBUGPL(DBG_CIL, "Creation of wq_usb failed\n"); -+ retval = -EINVAL; -+ goto fail; -+ } -+ -+ #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+ INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change, core_if); -+ INIT_WORK(&core_if->w_wkp, w_wakeup_detected, core_if); -+ #else -+ INIT_WORK(&core_if->w_conn_id, w_conn_id_status_change); -+ INIT_DELAYED_WORK(&core_if->w_wkp, w_wakeup_detected); -+ #endif -+#endif -+ return 0; -+ -+fail: -+ if( reg_base != NULL) iounmap(reg_base ); -+ if( fifo_base != NULL) iounmap(fifo_base); -+ if( fifo_dbg != NULL) iounmap(fifo_dbg ); -+ return retval; -+} -+ -+/*! -+ \brief This function free the mapped address in the IFXUSB CSR data structures. -+ \param _core_if Pointer of core_if structure -+ */ -+void ifxusb_core_if_remove(ifxusb_core_if_t *_core_if) -+{ -+ /* Disable all interrupts */ -+ if( _core_if->core_global_regs != NULL) -+ { -+ ifxusb_mreg( &_core_if->core_global_regs->gahbcfg, 1, 0); -+ ifxusb_wreg( &_core_if->core_global_regs->gintmsk, 0); -+ } -+ -+ if( _core_if->core_global_regs != NULL) iounmap(_core_if->core_global_regs ); -+ if( _core_if->data_fifo[0] != NULL) iounmap(_core_if->data_fifo[0] ); -+ if( _core_if->data_fifo_dbg != NULL) iounmap(_core_if->data_fifo_dbg ); -+ -+#if 0 -+ if (_core_if->wq_usb) -+ destroy_workqueue(_core_if->wq_usb); -+#endif -+ memset(_core_if, 0, sizeof(ifxusb_core_if_t)); -+} -+ -+ -+ -+ -+/*! -+ \brief This function enbles the controller's Global Interrupt in the AHB Config register. -+ \param _core_if Pointer of core_if structure -+ */ -+void ifxusb_enable_global_interrupts( ifxusb_core_if_t *_core_if ) -+{ -+ gahbcfg_data_t ahbcfg ={ .d32 = 0}; -+ ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ -+ ifxusb_mreg(&_core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32); -+} -+ -+/*! -+ \brief This function disables the controller's Global Interrupt in the AHB Config register. -+ \param _core_if Pointer of core_if structure -+ */ -+void ifxusb_disable_global_interrupts( ifxusb_core_if_t *_core_if ) -+{ -+ gahbcfg_data_t ahbcfg ={ .d32 = 0}; -+ ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ -+ ifxusb_mreg(&_core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0); -+} -+ -+ -+ -+ -+/*! -+ \brief Flush Tx and Rx FIFO. -+ \param _core_if Pointer of core_if structure -+ */ -+void ifxusb_flush_both_fifo( ifxusb_core_if_t *_core_if ) -+{ -+ ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; -+ volatile grstctl_t greset ={ .d32 = 0}; -+ int count = 0; -+ -+ IFX_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__); -+ greset.b.rxfflsh = 1; -+ greset.b.txfflsh = 1; -+ greset.b.txfnum = 0x10; -+ greset.b.intknqflsh=1; -+ greset.b.hstfrm=1; -+ ifxusb_wreg( &global_regs->grstctl, greset.d32 ); -+ -+ do -+ { -+ greset.d32 = ifxusb_rreg( &global_regs->grstctl); -+ if (++count > 10000) -+ { -+ IFX_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, greset.d32); -+ break; -+ } -+ } while (greset.b.rxfflsh == 1 || greset.b.txfflsh == 1); -+ /* Wait for 3 PHY Clocks*/ -+ UDELAY(1); -+} -+ -+/*! -+ \brief Flush a Tx FIFO. -+ \param _core_if Pointer of core_if structure -+ \param _num Tx FIFO to flush. ( 0x10 for ALL TX FIFO ) -+ */ -+void ifxusb_flush_tx_fifo( ifxusb_core_if_t *_core_if, const int _num ) -+{ -+ ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; -+ volatile grstctl_t greset ={ .d32 = 0}; -+ int count = 0; -+ -+ IFX_DEBUGPL((DBG_CIL|DBG_PCDV), "Flush Tx FIFO %d\n", _num); -+ -+ greset.b.intknqflsh=1; -+ greset.b.txfflsh = 1; -+ greset.b.txfnum = _num; -+ ifxusb_wreg( &global_regs->grstctl, greset.d32 ); -+ -+ do -+ { -+ greset.d32 = ifxusb_rreg( &global_regs->grstctl); -+ if (++count > 10000&&(_num==0 ||_num==0x10)) -+ { -+ IFX_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", -+ __func__, greset.d32, -+ ifxusb_rreg( &global_regs->gnptxsts)); -+ break; -+ } -+ } while (greset.b.txfflsh == 1); -+ /* Wait for 3 PHY Clocks*/ -+ UDELAY(1); -+} -+ -+ -+/*! -+ \brief Flush Rx FIFO. -+ \param _core_if Pointer of core_if structure -+ */ -+void ifxusb_flush_rx_fifo( ifxusb_core_if_t *_core_if ) -+{ -+ ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; -+ volatile grstctl_t greset ={ .d32 = 0}; -+ int count = 0; -+ -+ IFX_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__); -+ greset.b.rxfflsh = 1; -+ ifxusb_wreg( &global_regs->grstctl, greset.d32 ); -+ -+ do -+ { -+ greset.d32 = ifxusb_rreg( &global_regs->grstctl); -+ if (++count > 10000) -+ { -+ IFX_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, greset.d32); -+ break; -+ } -+ } while (greset.b.rxfflsh == 1); -+ /* Wait for 3 PHY Clocks*/ -+ UDELAY(1); -+} -+ -+ -+#define SOFT_RESET_DELAY 100 -+ -+/*! -+ \brief Do a soft reset of the core. Be careful with this because it -+ resets all the internal state machines of the core. -+ \param _core_if Pointer of core_if structure -+ */ -+int ifxusb_core_soft_reset(ifxusb_core_if_t *_core_if) -+{ -+ ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; -+ volatile grstctl_t greset ={ .d32 = 0}; -+ int count = 0; -+ -+ IFX_DEBUGPL(DBG_CILV, "%s\n", __func__); -+ /* Wait for AHB master IDLE state. */ -+ do -+ { -+ UDELAY(10); -+ greset.d32 = ifxusb_rreg( &global_regs->grstctl); -+ if (++count > 100000) -+ { -+ IFX_WARN("%s() HANG! AHB Idle GRSTCTL=%0x %x\n", __func__, -+ greset.d32, greset.b.ahbidle); -+ break; -+ } -+ } while (greset.b.ahbidle == 0); -+ -+ UDELAY(1); -+ -+ /* Core Soft Reset */ -+ count = 0; -+ greset.b.csftrst = 1; -+ ifxusb_wreg( &global_regs->grstctl, greset.d32 ); -+ -+ #ifdef SOFT_RESET_DELAY -+ MDELAY(SOFT_RESET_DELAY); -+ #endif -+ -+ do -+ { -+ UDELAY(10); -+ greset.d32 = ifxusb_rreg( &global_regs->grstctl); -+ if (++count > 100000) -+ { -+ IFX_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", __func__, greset.d32); -+ return -1; -+ } -+ } while (greset.b.csftrst == 1); -+ -+ #ifdef SOFT_RESET_DELAY -+ MDELAY(SOFT_RESET_DELAY); -+ #endif -+ -+ -+ #if defined(__IS_VR9__) -+ if(_core_if->core_no==0) -+ { -+ set_bit (4, VR9_RCU_USBRESET2); -+ MDELAY(50); -+ clear_bit (4, VR9_RCU_USBRESET2); -+ } -+ else -+ { -+ set_bit (5, VR9_RCU_USBRESET2); -+ MDELAY(50); -+ clear_bit (5, VR9_RCU_USBRESET2); -+ } -+ MDELAY(50); -+ #endif //defined(__IS_VR9__) -+ -+ IFX_PRINT("USB core #%d soft-reset\n",_core_if->core_no); -+ -+ return 0; -+} -+ -+/*! -+ \brief Turn on the USB Core Power -+ \param _core_if Pointer of core_if structure -+*/ -+void ifxusb_power_on (ifxusb_core_if_t *_core_if) -+{ -+ struct clk *clk0 = clk_get_sys("usb0", NULL); -+ struct clk *clk1 = clk_get_sys("usb1", NULL); -+ // set clock gating -+ IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); -+ #if defined(__UEIP__) -+ -+ #if defined(__IS_TWINPASS) || defined(__IS_DANUBE__) -+ set_bit (4, (volatile unsigned long *)DANUBE_CGU_IFCCR); -+ set_bit (5, (volatile unsigned long *)DANUBE_CGU_IFCCR); -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined(__IS_AMAZON_SE__) -+ // clear_bit (4, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR); -+ clear_bit (5, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR); -+ #endif //defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) -+ set_bit (0, (volatile unsigned long *)AR9_CGU_IFCCR); -+ set_bit (1, (volatile unsigned long *)AR9_CGU_IFCCR); -+ #endif //defined(__IS_AR9__) -+ #if defined(__IS_VR9__) -+// set_bit (0, (volatile unsigned long *)VR9_CGU_IFCCR); -+// set_bit (1, (volatile unsigned long *)VR9_CGU_IFCCR); -+ #endif //defined(__IS_VR9__) -+ -+ MDELAY(50); -+ -+ // set power -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) -+ USB_CTRL_PMU_SETUP(IFX_PMU_ENABLE); -+ //#if defined(__IS_TWINPASS__) -+ // ifxusb_enable_afe_oc(); -+ //#endif -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) || defined(__IS_VR9__) -+ if(_core_if->core_no==0) -+ clk_enable(clk0); -+// USB0_CTRL_PMU_SETUP(IFX_PMU_ENABLE); -+ else -+ clk_enable(clk1); -+// USB1_CTRL_PMU_SETUP(IFX_PMU_ENABLE); -+ #endif //defined(__IS_AR9__) || defined(__IS_VR9__) -+ -+ if(_core_if->core_global_regs) -+ { -+ // PHY configurations. -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined(__IS_AMAZON_SE__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_AR9__) -+ #if defined(__IS_VR9__) -+ //ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_VR9__) -+ } -+ #else //defined(__UEIP__) -+ #if defined(__IS_TWINPASS) || defined(__IS_DANUBE__) -+ set_bit (4, (volatile unsigned long *)DANUBE_CGU_IFCCR); -+ set_bit (5, (volatile unsigned long *)DANUBE_CGU_IFCCR); -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined(__IS_AMAZON_SE__) -+ // clear_bit (4, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR); -+ clear_bit (5, (volatile unsigned long *)AMAZON_SE_CGU_IFCCR); -+ #endif //defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) -+ set_bit (0, (volatile unsigned long *)AMAZON_S_CGU_IFCCR); -+ set_bit (1, (volatile unsigned long *)AMAZON_S_CGU_IFCCR); -+ #endif //defined(__IS_AR9__) -+ -+ MDELAY(50); -+ -+ // set power -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ clear_bit (6, (volatile unsigned long *)DANUBE_PMU_PWDCR);//USB -+ clear_bit (9, (volatile unsigned long *)DANUBE_PMU_PWDCR);//DSL -+ clear_bit (15, (volatile unsigned long *)DANUBE_PMU_PWDCR);//AHB -+ #if defined(__IS_TWINPASS__) -+ ifxusb_enable_afe_oc(); -+ #endif -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined(__IS_AMAZON_SE__) -+ clear_bit (6, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR); -+ clear_bit (9, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR); -+ clear_bit (15, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR); -+ #endif //defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) -+ if(_core_if->core_no==0) -+ clear_bit (6, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB -+ else -+ clear_bit (27, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB -+ clear_bit (9, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//DSL -+ clear_bit (15, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//AHB -+ #endif //defined(__IS_AR9__) -+ -+ if(_core_if->core_global_regs) -+ { -+ // PHY configurations. -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined(__IS_AMAZON_SE__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_AR9__) -+ } -+ -+ #endif //defined(__UEIP__) -+} -+ -+/*! -+ \brief Turn off the USB Core Power -+ \param _core_if Pointer of core_if structure -+*/ -+void ifxusb_power_off (ifxusb_core_if_t *_core_if) -+{ -+ struct clk *clk0 = clk_get_sys("usb0", NULL); -+ struct clk *clk1 = clk_get_sys("usb1", NULL); -+ ifxusb_phy_power_off (_core_if); -+ -+ // set power -+ #if defined(__UEIP__) -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) -+ USB_CTRL_PMU_SETUP(IFX_PMU_DISABLE); -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) || defined(__IS_VR9__) -+ if(_core_if->core_no==0) -+ clk_disable(clk0); -+ //USB0_CTRL_PMU_SETUP(IFX_PMU_DISABLE); -+ else -+ clk_disable(clk1); -+ //USB1_CTRL_PMU_SETUP(IFX_PMU_DISABLE); -+ #endif //defined(__IS_AR9__) || defined(__IS_VR9__) -+ #else //defined(__UEIP__) -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ set_bit (6, (volatile unsigned long *)DANUBE_PMU_PWDCR);//USB -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined(__IS_AMAZON_SE__) -+ set_bit (6, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);//USB -+ #endif //defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) -+ if(_core_if->core_no==0) -+ set_bit (6, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB -+ else -+ set_bit (27, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//USB -+ #endif //defined(__IS_AR9__) -+ #endif //defined(__UEIP__) -+} -+ -+/*! -+ \brief Turn on the USB PHY Power -+ \param _core_if Pointer of core_if structure -+*/ -+void ifxusb_phy_power_on (ifxusb_core_if_t *_core_if) -+{ -+ struct clk *clk0 = clk_get_sys("usb0", NULL); -+ struct clk *clk1 = clk_get_sys("usb1", NULL); -+ #if defined(__UEIP__) -+ if(_core_if->core_global_regs) -+ { -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined(__IS_AMAZON_SE__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_AR9__) -+ #if defined(__IS_VR9_S__) -+ if(_core_if->core_no==0) -+ set_bit (0, VR9_RCU_USB_ANA_CFG1A); -+ else -+ set_bit (0, VR9_RCU_USB_ANA_CFG1B); -+ #endif //defined(__IS_VR9__) -+ } -+ -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) -+ USB_PHY_PMU_SETUP(IFX_PMU_ENABLE); -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) || defined(__IS_VR9__) -+ if(_core_if->core_no==0) -+ clk_enable(clk0); -+ //USB0_PHY_PMU_SETUP(IFX_PMU_ENABLE); -+ else -+ clk_enable(clk1); -+ //USB1_PHY_PMU_SETUP(IFX_PMU_ENABLE); -+ #endif //defined(__IS_AR9__) || defined(__IS_VR9__) -+ -+ // PHY configurations. -+ if(_core_if->core_global_regs) -+ { -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined(__IS_AMAZON_SE__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_AR9__) -+ #if defined(__IS_VR9_S__) -+ if(_core_if->core_no==0) -+ set_bit (0, VR9_RCU_USB_ANA_CFG1A); -+ else -+ set_bit (0, VR9_RCU_USB_ANA_CFG1B); -+ #endif //defined(__IS_VR9__) -+ } -+ #else //defined(__UEIP__) -+ // PHY configurations. -+ if(_core_if->core_global_regs) -+ { -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined(__IS_AMAZON_SE__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_AR9__) -+ } -+ -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ clear_bit (0, (volatile unsigned long *)DANUBE_PMU_PWDCR);//PHY -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined(__IS_AMAZON_SE__) -+ clear_bit (0, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR); -+ #endif //defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) -+ if(_core_if->core_no==0) -+ clear_bit (0, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY -+ else -+ clear_bit (26, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY -+ #endif //defined(__IS_AR9__) -+ -+ // PHY configurations. -+ if(_core_if->core_global_regs) -+ { -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined(__IS_AMAZON_SE__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_AR9__) -+ } -+ #endif //defined(__UEIP__) -+} -+ -+ -+/*! -+ \brief Turn off the USB PHY Power -+ \param _core_if Pointer of core_if structure -+*/ -+void ifxusb_phy_power_off (ifxusb_core_if_t *_core_if) -+{ -+ struct clk *clk0 = clk_get_sys("usb0", NULL); -+ struct clk *clk1 = clk_get_sys("usb1", NULL); -+ #if defined(__UEIP__) -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) -+ USB_PHY_PMU_SETUP(IFX_PMU_DISABLE); -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) || defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) || defined(__IS_VR9__) -+ if(_core_if->core_no==0) -+ clk_disable(clk0); -+ //USB0_PHY_PMU_SETUP(IFX_PMU_DISABLE); -+ else -+ clk_disable(clk1); -+ //USB1_PHY_PMU_SETUP(IFX_PMU_DISABLE); -+ #endif // defined(__IS_AR9__) || defined(__IS_VR9__) -+ #else //defined(__UEIP__) -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ set_bit (0, (volatile unsigned long *)DANUBE_PMU_PWDCR);//PHY -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined(__IS_AMAZON_SE__) -+ set_bit (0, (volatile unsigned long *)AMAZON_SE_PMU_PWDCR);//PHY -+ #endif //defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) -+ if(_core_if->core_no==0) -+ set_bit (0, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY -+ else -+ set_bit (26, (volatile unsigned long *)AMAZON_S_PMU_PWDCR);//PHY -+ #endif //defined(__IS_AR9__) -+ #endif //defined(__UEIP__) -+} -+ -+ -+/*! -+ \brief Reset on the USB Core RCU -+ \param _core_if Pointer of core_if structure -+ */ -+#if defined(__IS_VR9__) -+ int already_hard_reset=0; -+#endif -+void ifxusb_hard_reset(ifxusb_core_if_t *_core_if) -+{ -+ #if defined(__UEIP__) -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined (__IS_HOST__) -+ clear_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); -+ #elif defined (__IS_DEVICE__) -+ set_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); -+ #endif -+ #endif //defined(__IS_AMAZON_SE__) -+ -+ #if defined(__IS_AMAZON_SE__) -+ #if defined (__IS_HOST__) -+ clear_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); -+ #elif defined (__IS_DEVICE__) -+ set_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); -+ #endif -+ #endif //defined(__IS_AMAZON_SE__) -+ -+ #if defined(__IS_AR9__) -+ if(_core_if->core_no==0) -+ { -+ #if defined (__IS_HOST__) -+ clear_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG); -+ #elif defined (__IS_DEVICE__) -+ set_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG); -+ #endif -+ } -+ else -+ { -+ #if defined (__IS_HOST__) -+ clear_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG); -+ #elif defined (__IS_DEVICE__) -+ set_bit (AR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG); -+ #endif -+ } -+ #endif //defined(__IS_AR9__) -+ -+ #if defined(__IS_VR9__) -+ if(_core_if->core_no==0) -+ { -+ #if defined (__IS_HOST__) -+ clear_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG); -+ #elif defined (__IS_DEVICE__) -+ set_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG); -+ #endif -+ } -+ else -+ { -+ #if defined (__IS_HOST__) -+ clear_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG); -+ #elif defined (__IS_DEVICE__) -+ set_bit (VR9_USBCFG_HDSEL_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG); -+ #endif -+ } -+ #endif //defined(__IS_VR9__) -+ -+ -+ // set the HC's byte-order to big-endian -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ set_bit (DANUBE_USBCFG_HOST_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); -+ clear_bit (DANUBE_USBCFG_SLV_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined(__IS_AMAZON_SE__) -+ set_bit (AMAZON_SE_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); -+ clear_bit (AMAZON_SE_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); -+ #endif //defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) -+ if(_core_if->core_no==0) -+ { -+ set_bit (AR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG); -+ clear_bit (AR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)AR9_RCU_USB1CFG); -+ } -+ else -+ { -+ set_bit (AR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG); -+ clear_bit (AR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)AR9_RCU_USB2CFG); -+ } -+ #endif //defined(__IS_AR9__) -+ #if defined(__IS_VR9__) -+ if(_core_if->core_no==0) -+ { -+ set_bit (VR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG); -+ clear_bit (VR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)VR9_RCU_USB1CFG); -+ } -+ else -+ { -+ set_bit (VR9_USBCFG_HOST_END_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG); -+ clear_bit (VR9_USBCFG_SLV_END_BIT, (volatile unsigned long *)VR9_RCU_USB2CFG); -+ } -+ #endif //defined(__IS_VR9__) -+ -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ set_bit (4, DANUBE_RCU_RESET); -+ MDELAY(500); -+ clear_bit (4, DANUBE_RCU_RESET); -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ -+ #if defined(__IS_AMAZON_SE__) -+ set_bit (4, AMAZON_SE_RCU_RESET); -+ MDELAY(500); -+ clear_bit (4, AMAZON_SE_RCU_RESET); -+ MDELAY(500); -+ #endif //defined(__IS_AMAZON_SE__) -+ -+ #if defined(__IS_AR9__) -+ if(_core_if->core_no==0) -+ { -+ set_bit (4, AR9_RCU_USBRESET); -+ MDELAY(500); -+ clear_bit (4, AR9_RCU_USBRESET); -+ } -+ else -+ { -+ set_bit (28, AR9_RCU_USBRESET); -+ MDELAY(500); -+ clear_bit (28, AR9_RCU_USBRESET); -+ } -+ MDELAY(500); -+ #endif //defined(__IS_AR9__) -+ #if defined(__IS_VR9__) -+ if(!already_hard_reset) -+ { -+ set_bit (4, VR9_RCU_USBRESET); -+ MDELAY(500); -+ clear_bit (4, VR9_RCU_USBRESET); -+ MDELAY(500); -+ already_hard_reset=1; -+ } -+ #endif //defined(__IS_VR9__) -+ -+ #if defined(__IS_TWINPASS__) -+ ifxusb_enable_afe_oc(); -+ #endif -+ -+ if(_core_if->core_global_regs) -+ { -+ // PHY configurations. -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined(__IS_AMAZON_SE__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_AR9__) -+ #if defined(__IS_VR9__) -+ // ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_VR9__) -+ } -+ #else //defined(__UEIP__) -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined (__IS_HOST__) -+ clear_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); -+ #elif defined (__IS_DEVICE__) -+ set_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); -+ #endif -+ #endif //defined(__IS_AMAZON_SE__) -+ -+ #if defined(__IS_AMAZON_SE__) -+ #if defined (__IS_HOST__) -+ clear_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); -+ #elif defined (__IS_DEVICE__) -+ set_bit (AMAZON_SE_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); -+ #endif -+ #endif //defined(__IS_AMAZON_SE__) -+ -+ #if defined(__IS_AR9__) -+ if(_core_if->core_no==0) -+ { -+ #if defined (__IS_HOST__) -+ clear_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG); -+ #elif defined (__IS_DEVICE__) -+ set_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG); -+ #endif -+ } -+ else -+ { -+ #if defined (__IS_HOST__) -+ clear_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG); -+ #elif defined (__IS_DEVICE__) -+ set_bit (AMAZON_S_USBCFG_HDSEL_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG); -+ #endif -+ } -+ #endif //defined(__IS_AR9__) -+ -+ // set the HC's byte-order to big-endian -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ set_bit (DANUBE_USBCFG_HOST_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); -+ clear_bit (DANUBE_USBCFG_SLV_END_BIT, (volatile unsigned long *)DANUBE_RCU_USBCFG); -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined(__IS_AMAZON_SE__) -+ set_bit (AMAZON_SE_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); -+ clear_bit (AMAZON_SE_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_SE_RCU_USBCFG); -+ #endif //defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) -+ if(_core_if->core_no==0) -+ { -+ set_bit (AMAZON_S_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG); -+ clear_bit (AMAZON_S_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB1CFG); -+ } -+ else -+ { -+ set_bit (AMAZON_S_USBCFG_HOST_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG); -+ clear_bit (AMAZON_S_USBCFG_SLV_END_BIT, (volatile unsigned long *)AMAZON_S_RCU_USB2CFG); -+ } -+ #endif //defined(__IS_AR9__) -+ -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ set_bit (4, DANUBE_RCU_RESET); -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined(__IS_AMAZON_SE__) -+ set_bit (4, AMAZON_SE_RCU_RESET); -+ #endif //defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) -+ if(_core_if->core_no==0) -+ { -+ set_bit (4, AMAZON_S_RCU_USBRESET); -+ } -+ else -+ { -+ set_bit (28, AMAZON_S_RCU_USBRESET); -+ } -+ #endif //defined(__IS_AR9__) -+ -+ MDELAY(500); -+ -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ clear_bit (4, DANUBE_RCU_RESET); -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined(__IS_AMAZON_SE__) -+ clear_bit (4, AMAZON_SE_RCU_RESET); -+ #endif //defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) -+ if(_core_if->core_no==0) -+ { -+ clear_bit (4, AMAZON_S_RCU_USBRESET); -+ } -+ else -+ { -+ clear_bit (28, AMAZON_S_RCU_USBRESET); -+ } -+ #endif //defined(__IS_AR9__) -+ -+ MDELAY(500); -+ -+ #if defined(__IS_TWINPASS__) -+ ifxusb_enable_afe_oc(); -+ #endif -+ -+ if(_core_if->core_global_regs) -+ { -+ // PHY configurations. -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined(__IS_AMAZON_SE__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) -+ ifxusb_wreg (&_core_if->core_global_regs->guid,0x14014); -+ #endif //defined(__IS_AR9__) -+ } -+ #endif //defined(__UEIP__) -+} -+ -+#if defined(__GADGET_LED__) || defined(__HOST_LED__) -+ #if defined(__UEIP__) -+ static void *g_usb_led_trigger = NULL; -+ #endif -+ -+ void ifxusb_led_init(ifxusb_core_if_t *_core_if) -+ { -+ #if defined(__UEIP__) -+ if ( !g_usb_led_trigger ) -+ { -+ ifx_led_trigger_register("usb_link", &g_usb_led_trigger); -+ if ( g_usb_led_trigger != NULL ) -+ { -+ struct ifx_led_trigger_attrib attrib = {0}; -+ attrib.delay_on = 250; -+ attrib.delay_off = 250; -+ attrib.timeout = 2000; -+ attrib.def_value = 1; -+ attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE; -+ IFX_DEBUGP("Reg USB LED!!\n"); -+ ifx_led_trigger_set_attrib(g_usb_led_trigger, &attrib); -+ } -+ } -+ #endif //defined(__UEIP__) -+ } -+ -+ void ifxusb_led_free(ifxusb_core_if_t *_core_if) -+ { -+ #if defined(__UEIP__) -+ if ( g_usb_led_trigger ) -+ { -+ ifx_led_trigger_deregister(g_usb_led_trigger); -+ g_usb_led_trigger = NULL; -+ } -+ #endif //defined(__UEIP__) -+ } -+ -+ /*! -+ \brief Turn off the USB 5V VBus Power -+ \param _core_if Pointer of core_if structure -+ */ -+ void ifxusb_led(ifxusb_core_if_t *_core_if) -+ { -+ #if defined(__UEIP__) -+ if(g_usb_led_trigger) -+ ifx_led_trigger_activate(g_usb_led_trigger); -+ #else -+ #endif //defined(__UEIP__) -+ } -+#endif // defined(__GADGET_LED__) || defined(__HOST_LED__) -+ -+ -+ -+#if defined(__IS_HOST__) && defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__) -+/*! -+ \brief Turn on the OC Int -+ */ -+ void ifxusb_oc_int_on() -+ { -+ #if defined(__UEIP__) -+ #else -+ #if defined(__IS_TWINPASS__) -+ irq_enable(DANUBE_USB_OC_INT); -+ #endif -+ #endif //defined(__UEIP__) -+ } -+/*! -+ \brief Turn off the OC Int -+ */ -+ void ifxusb_oc_int_off() -+ { -+ #if defined(__UEIP__) -+ #else -+ #if defined(__IS_TWINPASS__) -+ irq_disable(DANUBE_USB_OC_INT); -+ #endif -+ #endif //defined(__UEIP__) -+ } -+#endif //defined(__IS_HOST__) && defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__) -+ -+/* internal routines for debugging */ -+void ifxusb_dump_msg(const u8 *buf, unsigned int length) -+{ -+#ifdef __DEBUG__ -+ unsigned int start, num, i; -+ char line[52], *p; -+ -+ if (length >= 512) -+ return; -+ start = 0; -+ while (length > 0) -+ { -+ num = min(length, 16u); -+ p = line; -+ for (i = 0; i < num; ++i) -+ { -+ if (i == 8) -+ *p++ = ' '; -+ sprintf(p, " %02x", buf[i]); -+ p += 3; -+ } -+ *p = 0; -+ IFX_PRINT( "%6x: %s\n", start, line); -+ buf += num; -+ start += num; -+ length -= num; -+ } -+#endif -+} -+ -+/* This functions reads the SPRAM and prints its content */ -+void ifxusb_dump_spram(ifxusb_core_if_t *_core_if) -+{ -+#ifdef __ENABLE_DUMP__ -+ volatile uint8_t *addr, *start_addr, *end_addr; -+ uint32_t size; -+ IFX_PRINT("SPRAM Data:\n"); -+ start_addr = (void*)_core_if->core_global_regs; -+ IFX_PRINT("Base Address: 0x%8X\n", (uint32_t)start_addr); -+ -+ start_addr = (void*)_core_if->data_fifo_dbg; -+ IFX_PRINT("Starting Address: 0x%8X\n", (uint32_t)start_addr); -+ -+ size=_core_if->hwcfg3.b.dfifo_depth; -+ size<<=2; -+ size+=0x200; -+ size&=0x0003FFFC; -+ -+ end_addr = (void*)_core_if->data_fifo_dbg; -+ end_addr += size; -+ -+ for(addr = start_addr; addr < end_addr; addr+=16) -+ { -+ IFX_PRINT("0x%8X:\t%02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X\n", (uint32_t)addr, -+ addr[ 0], addr[ 1], addr[ 2], addr[ 3], -+ addr[ 4], addr[ 5], addr[ 6], addr[ 7], -+ addr[ 8], addr[ 9], addr[10], addr[11], -+ addr[12], addr[13], addr[14], addr[15] -+ ); -+ } -+ return; -+#endif //__ENABLE_DUMP__ -+} -+ -+ -+ -+ -+/* This function reads the core global registers and prints them */ -+void ifxusb_dump_registers(ifxusb_core_if_t *_core_if) -+{ -+#ifdef __ENABLE_DUMP__ -+ int i; -+ volatile uint32_t *addr; -+ #ifdef __IS_DEVICE__ -+ volatile uint32_t *addri,*addro; -+ #endif -+ -+ IFX_PRINT("Core Global Registers\n"); -+ addr=&_core_if->core_global_regs->gotgctl; -+ IFX_PRINT("GOTGCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->core_global_regs->gotgint; -+ IFX_PRINT("GOTGINT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->core_global_regs->gahbcfg; -+ IFX_PRINT("GAHBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->core_global_regs->gusbcfg; -+ IFX_PRINT("GUSBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->core_global_regs->grstctl; -+ IFX_PRINT("GRSTCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->core_global_regs->gintsts; -+ IFX_PRINT("GINTSTS @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->core_global_regs->gintmsk; -+ IFX_PRINT("GINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->core_global_regs->gi2cctl; -+ IFX_PRINT("GI2CCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->core_global_regs->gpvndctl; -+ IFX_PRINT("GPVNDCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->core_global_regs->ggpio; -+ IFX_PRINT("GGPIO @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->core_global_regs->guid; -+ IFX_PRINT("GUID @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->core_global_regs->gsnpsid; -+ IFX_PRINT("GSNPSID @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->core_global_regs->ghwcfg1; -+ IFX_PRINT("GHWCFG1 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->core_global_regs->ghwcfg2; -+ IFX_PRINT("GHWCFG2 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->core_global_regs->ghwcfg3; -+ IFX_PRINT("GHWCFG3 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->core_global_regs->ghwcfg4; -+ IFX_PRINT("GHWCFG4 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ -+ addr=_core_if->pcgcctl; -+ IFX_PRINT("PCGCCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ -+ addr=&_core_if->core_global_regs->grxfsiz; -+ IFX_PRINT("GRXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ -+ #ifdef __IS_HOST__ -+ addr=&_core_if->core_global_regs->gnptxfsiz; -+ IFX_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->core_global_regs->hptxfsiz; -+ IFX_PRINT("HPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ #endif //__IS_HOST__ -+ -+ #ifdef __IS_DEVICE__ -+ #ifdef __DED_FIFO__ -+ addr=&_core_if->core_global_regs->gnptxfsiz; -+ IFX_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ for (i=0; i<= _core_if->hwcfg4.b.num_in_eps; i++) -+ { -+ addr=&_core_if->core_global_regs->dptxfsiz_dieptxf[i]; -+ IFX_PRINT("DPTXFSIZ[%d] @0x%08X : 0x%08X\n",i,(uint32_t)addr,ifxusb_rreg(addr)); -+ } -+ #else -+ addr=&_core_if->core_global_regs->gnptxfsiz; -+ IFX_PRINT("TXFSIZ[00] @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ for (i=0; i< _core_if->hwcfg4.b.num_dev_perio_in_ep; i++) -+ { -+ addr=&_core_if->core_global_regs->dptxfsiz_dieptxf[i]; -+ IFX_PRINT("TXFSIZ[%02d] @0x%08X : 0x%08X\n",i+1,(uint32_t)addr,ifxusb_rreg(addr)); -+ } -+ #endif -+ #endif //__IS_DEVICE__ -+ -+ #ifdef __IS_HOST__ -+ IFX_PRINT("Host Global Registers\n"); -+ addr=&_core_if->host_global_regs->hcfg; -+ IFX_PRINT("HCFG @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->host_global_regs->hfir; -+ IFX_PRINT("HFIR @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->host_global_regs->hfnum; -+ IFX_PRINT("HFNUM @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->host_global_regs->hptxsts; -+ IFX_PRINT("HPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->host_global_regs->haint; -+ IFX_PRINT("HAINT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->host_global_regs->haintmsk; -+ IFX_PRINT("HAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr= _core_if->hprt0; -+ IFX_PRINT("HPRT0 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ -+ for (i=0; ihc_regs[i]->hcchar; -+ IFX_PRINT("HCCHAR @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->hc_regs[i]->hcsplt; -+ IFX_PRINT("HCSPLT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->hc_regs[i]->hcint; -+ IFX_PRINT("HCINT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->hc_regs[i]->hcintmsk; -+ IFX_PRINT("HCINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->hc_regs[i]->hctsiz; -+ IFX_PRINT("HCTSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->hc_regs[i]->hcdma; -+ IFX_PRINT("HCDMA @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ } -+ #endif //__IS_HOST__ -+ -+ #ifdef __IS_DEVICE__ -+ IFX_PRINT("Device Global Registers\n"); -+ addr=&_core_if->dev_global_regs->dcfg; -+ IFX_PRINT("DCFG @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->dev_global_regs->dctl; -+ IFX_PRINT("DCTL @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->dev_global_regs->dsts; -+ IFX_PRINT("DSTS @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->dev_global_regs->diepmsk; -+ IFX_PRINT("DIEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->dev_global_regs->doepmsk; -+ IFX_PRINT("DOEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->dev_global_regs->daintmsk; -+ IFX_PRINT("DAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->dev_global_regs->daint; -+ IFX_PRINT("DAINT @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->dev_global_regs->dvbusdis; -+ IFX_PRINT("DVBUSID @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ addr=&_core_if->dev_global_regs->dvbuspulse; -+ IFX_PRINT("DVBUSPULSE @0x%08X : 0x%08X\n", (uint32_t)addr,ifxusb_rreg(addr)); -+ -+ addr=&_core_if->dev_global_regs->dtknqr1; -+ IFX_PRINT("DTKNQR1 @0x%08X : 0x%08X\n",(uint32_t)addr,ifxusb_rreg(addr)); -+ if (_core_if->hwcfg2.b.dev_token_q_depth > 6) { -+ addr=&_core_if->dev_global_regs->dtknqr2; -+ IFX_PRINT("DTKNQR2 @0x%08X : 0x%08X\n", (uint32_t)addr,ifxusb_rreg(addr)); -+ } -+ -+ if (_core_if->hwcfg2.b.dev_token_q_depth > 14) -+ { -+ addr=&_core_if->dev_global_regs->dtknqr3_dthrctl; -+ IFX_PRINT("DTKNQR3_DTHRCTL @0x%08X : 0x%08X\n", (uint32_t)addr, ifxusb_rreg(addr)); -+ } -+ -+ if (_core_if->hwcfg2.b.dev_token_q_depth > 22) -+ { -+ addr=&_core_if->dev_global_regs->dtknqr4_fifoemptymsk; -+ IFX_PRINT("DTKNQR4 @0x%08X : 0x%08X\n", (uint32_t)addr, ifxusb_rreg(addr)); -+ } -+ -+ //for (i=0; i<= MAX_EPS_CHANNELS; i++) -+ //for (i=0; i<= 10; i++) -+ for (i=0; i<= 3; i++) -+ { -+ IFX_PRINT("Device EP %d Registers\n", i); -+ addri=&_core_if->in_ep_regs[i]->diepctl;addro=&_core_if->out_ep_regs[i]->doepctl; -+ IFX_PRINT("DEPCTL I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro)); -+ addro=&_core_if->out_ep_regs[i]->doepfn; -+ IFX_PRINT("DEPFN I: O: 0x%08X\n",ifxusb_rreg(addro)); -+ addri=&_core_if->in_ep_regs[i]->diepint;addro=&_core_if->out_ep_regs[i]->doepint; -+ IFX_PRINT("DEPINT I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro)); -+ addri=&_core_if->in_ep_regs[i]->dieptsiz;addro=&_core_if->out_ep_regs[i]->doeptsiz; -+ IFX_PRINT("DETSIZ I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro)); -+ addri=&_core_if->in_ep_regs[i]->diepdma;addro=&_core_if->out_ep_regs[i]->doepdma; -+ IFX_PRINT("DEPDMA I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro)); -+ addri=&_core_if->in_ep_regs[i]->dtxfsts; -+ IFX_PRINT("DTXFSTS I: 0x%08X\n",ifxusb_rreg(addri) ); -+ addri=&_core_if->in_ep_regs[i]->diepdmab;addro=&_core_if->out_ep_regs[i]->doepdmab; -+ IFX_PRINT("DEPDMAB I: 0x%08X O: 0x%08X\n",ifxusb_rreg(addri),ifxusb_rreg(addro)); -+ } -+ #endif //__IS_DEVICE__ -+#endif //__ENABLE_DUMP__ -+} -+ -+void ifxusb_clean_spram(ifxusb_core_if_t *_core_if,uint32_t dwords) -+{ -+ volatile uint32_t *addr1,*addr2, *start_addr, *end_addr; -+ -+ if(!dwords) -+ return; -+ -+ start_addr = (uint32_t *)_core_if->data_fifo_dbg; -+ -+ end_addr = (uint32_t *)_core_if->data_fifo_dbg; -+ end_addr += dwords; -+ -+ IFX_PRINT("Clearning SPRAM: 0x%8X-0x%8X\n", (uint32_t)start_addr,(uint32_t)end_addr); -+ for(addr1 = start_addr; addr1 < end_addr; addr1+=4) -+ { -+ for(addr2 = addr1; addr2 < addr1+4; addr2++) -+ *addr2=0x00000000; -+ } -+ IFX_PRINT("Clearning SPRAM: 0x%8X-0x%8X Done\n", (uint32_t)start_addr,(uint32_t)end_addr); -+ return; -+} -+ ---- /dev/null -+++ b/drivers/usb/ifxhcd/ifxusb_cif.h -@@ -0,0 +1,665 @@ -+/***************************************************************************** -+ ** FILE NAME : ifxusb_cif.h -+ ** PROJECT : IFX USB sub-system V3 -+ ** MODULES : IFX USB sub-system Host and Device driver -+ ** SRC VERSION : 1.0 -+ ** DATE : 1/Jan/2009 -+ ** AUTHOR : Chen, Howard -+ ** DESCRIPTION : The Core Interface provides basic services for accessing and -+ ** managing the IFX USB hardware. These services are used by both the -+ ** Host Controller Driver and the Peripheral Controller Driver. -+ ** FUNCTIONS : -+ ** COMPILER : gcc -+ ** REFERENCE : IFX hardware ref handbook for each plateforms -+ ** COPYRIGHT : -+ ** Version Control Section ** -+ ** $Author$ -+ ** $Date$ -+ ** $Revisions$ -+ ** $Log$ Revision history -+*****************************************************************************/ -+ -+/*! -+ \defgroup IFXUSB_DRIVER_V3 IFX USB SS Project -+ \brief IFX USB subsystem V3.x -+ */ -+ -+/*! -+ \defgroup IFXUSB_CIF Core Interface APIs -+ \ingroup IFXUSB_DRIVER_V3 -+ \brief The Core Interface provides basic services for accessing and -+ managing the IFXUSB hardware. These services are used by both the -+ Host Controller Driver and the Peripheral Controller Driver. -+ */ -+ -+ -+/*! -+ \file ifxusb_cif.h -+ \ingroup IFXUSB_DRIVER_V3 -+ \brief This file contains the interface to the IFX USB Core. -+ */ -+ -+#if !defined(__IFXUSB_CIF_H__) -+#define __IFXUSB_CIF_H__ -+ -+#include -+ -+#include -+#include -+ -+#include "ifxusb_plat.h" -+#include "ifxusb_regs.h" -+ -+#ifdef __DEBUG__ -+ #include "linux/timer.h" -+#endif -+ -+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+#define IFXUSB_PARAM_SPEED_HIGH 0 -+#define IFXUSB_PARAM_SPEED_FULL 1 -+ -+#define IFXUSB_EP_SPEED_LOW 0 -+#define IFXUSB_EP_SPEED_FULL 1 -+#define IFXUSB_EP_SPEED_HIGH 2 -+ -+#define IFXUSB_EP_TYPE_CTRL 0 -+#define IFXUSB_EP_TYPE_ISOC 1 -+#define IFXUSB_EP_TYPE_BULK 2 -+#define IFXUSB_EP_TYPE_INTR 3 -+ -+#define IFXUSB_HC_PID_DATA0 0 -+#define IFXUSB_HC_PID_DATA2 1 -+#define IFXUSB_HC_PID_DATA1 2 -+#define IFXUSB_HC_PID_MDATA 3 -+#define IFXUSB_HC_PID_SETUP 3 -+ -+ -+/*! -+ \addtogroup IFXUSB_CIF -+ */ -+/*@{*/ -+ -+/*! -+ \struct ifxusb_params -+ \brief IFXUSB Parameters structure. -+ This structure is used for both importing from insmod stage and run-time storage. -+ These parameters define how the IFXUSB controller should be configured. -+ */ -+typedef struct ifxusb_params -+{ -+ int32_t dma_burst_size; /*!< The DMA Burst size (applicable only for Internal DMA -+ Mode). 0(for single), 1(incr), 4(incr4), 8(incr8) 16(incr16) -+ */ -+ /* Translate this to GAHBCFG values */ -+ int32_t speed; /*!< Specifies the maximum speed of operation in host and device mode. -+ The actual speed depends on the speed of the attached device and -+ the value of phy_type. The actual speed depends on the speed of the -+ attached device. -+ 0 - High Speed (default) -+ 1 - Full Speed -+ */ -+ -+ int32_t data_fifo_size; /*!< Total number of dwords in the data FIFO memory. This -+ memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic -+ Tx FIFOs. -+ 32 to 32768 -+ */ -+ #ifdef __IS_DEVICE__ -+ int32_t rx_fifo_size; /*!< Number of dwords in the Rx FIFO in device mode. -+ 16 to 32768 -+ */ -+ -+ -+ int32_t tx_fifo_size[MAX_EPS_CHANNELS]; /*!< Number of dwords in each of the Tx FIFOs in device mode. -+ 4 to 768 -+ */ -+ #ifdef __DED_FIFO__ -+ int32_t thr_ctl; /*!< Threshold control on/off */ -+ int32_t tx_thr_length; /*!< Threshold length for Tx */ -+ int32_t rx_thr_length; /*!< Threshold length for Rx*/ -+ #endif -+ #else //__IS_HOST__ -+ int32_t host_channels; /*!< The number of host channel registers to use. -+ 1 to 16 -+ */ -+ -+ int32_t rx_fifo_size; /*!< Number of dwords in the Rx FIFO in host mode. -+ 16 to 32768 -+ */ -+ -+ int32_t nperio_tx_fifo_size;/*!< Number of dwords in the non-periodic Tx FIFO in host mode. -+ 16 to 32768 -+ */ -+ -+ int32_t perio_tx_fifo_size; /*!< Number of dwords in the host periodic Tx FIFO. -+ 16 to 32768 -+ */ -+ #endif //__IS_HOST__ -+ -+ int32_t max_transfer_size; /*!< The maximum transfer size supported in bytes. -+ 2047 to 65,535 -+ */ -+ -+ int32_t max_packet_count; /*!< The maximum number of packets in a transfer. -+ 15 to 511 (default 511) -+ */ -+ int32_t phy_utmi_width; /*!< Specifies the UTMI+ Data Width. -+ 8 or 16 bits (default 16) -+ */ -+ -+ int32_t turn_around_time_hs; /*!< Specifies the Turn-Around time at HS*/ -+ int32_t turn_around_time_fs; /*!< Specifies the Turn-Around time at FS*/ -+ -+ int32_t timeout_cal_hs; /*!< Specifies the Timeout_Calibration at HS*/ -+ int32_t timeout_cal_fs; /*!< Specifies the Timeout_Calibration at FS*/ -+} ifxusb_params_t; -+ -+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+/*! -+ \struct ifxusb_core_if -+ \brief The ifx_core_if structure contains information needed to manage -+ the IFX USB controller acting in either host or device mode. It -+ represents the programming view of the controller as a whole. -+ */ -+typedef struct ifxusb_core_if -+{ -+ ifxusb_params_t params; /*!< Run-time Parameters */ -+ -+ uint8_t core_no; /*!< core number (used as id when multi-core case */ -+ char *core_name; /*!< core name used for registration and informative purpose*/ -+ int irq; /*!< irq number this core is hooked */ -+ -+ /***************************************************************** -+ * Structures and pointers to physical register interface. -+ *****************************************************************/ -+ /** Core Global registers starting at offset 000h. */ -+ ifxusb_core_global_regs_t *core_global_regs; /*!< pointer to Core Global Registers, offset at 000h */ -+ -+ /** Host-specific registers */ -+ #ifdef __IS_HOST__ -+ /** Host Global Registers starting at offset 400h.*/ -+ ifxusb_host_global_regs_t *host_global_regs; /*!< pointer to Host Global Registers, offset at 400h */ -+ #define IFXUSB_HOST_GLOBAL_REG_OFFSET 0x400 -+ /** Host Port 0 Control and Status Register */ -+ volatile uint32_t *hprt0; /*!< pointer to HPRT0 Registers, offset at 440h */ -+ #define IFXUSB_HOST_PORT_REGS_OFFSET 0x440 -+ /** Host Channel Specific Registers at offsets 500h-5FCh. */ -+ ifxusb_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; /*!< pointer to Host-Channel n Registers, offset at 500h */ -+ #define IFXUSB_HOST_CHAN_REGS_OFFSET 0x500 -+ #define IFXUSB_CHAN_REGS_OFFSET 0x20 -+ #endif -+ -+ /** Device-specific registers */ -+ #ifdef __IS_DEVICE__ -+ /** Device Global Registers starting at offset 800h */ -+ ifxusb_device_global_regs_t *dev_global_regs; /*!< pointer to Device Global Registers, offset at 800h */ -+ #define IFXUSB_DEV_GLOBAL_REG_OFFSET 0x800 -+ -+ /** Device Logical IN Endpoint-Specific Registers 900h-AFCh */ -+ ifxusb_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; /*!< pointer to Device IN-EP Registers, offset at 900h */ -+ #define IFXUSB_DEV_IN_EP_REG_OFFSET 0x900 -+ #define IFXUSB_EP_REG_OFFSET 0x20 -+ /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */ -+ ifxusb_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];/*!< pointer to Device OUT-EP Registers, offset at 900h */ -+ #define IFXUSB_DEV_OUT_EP_REG_OFFSET 0xB00 -+ #endif -+ -+ /** Power and Clock Gating Control Register */ -+ volatile uint32_t *pcgcctl; /*!< pointer to Power and Clock Gating Control Registers, offset at E00h */ -+ #define IFXUSB_PCGCCTL_OFFSET 0xE00 -+ -+ /** Push/pop addresses for endpoints or host channels.*/ -+ uint32_t *data_fifo[MAX_EPS_CHANNELS]; /*!< pointer to FIFO access windows, offset at 1000h */ -+ #define IFXUSB_DATA_FIFO_OFFSET 0x1000 -+ #define IFXUSB_DATA_FIFO_SIZE 0x1000 -+ -+ uint32_t *data_fifo_dbg; /*!< pointer to FIFO debug windows, offset at 1000h */ -+ -+ /** Hardware Configuration -- stored here for convenience.*/ -+ hwcfg1_data_t hwcfg1; /*!< preserved Hardware Configuration 1 */ -+ hwcfg2_data_t hwcfg2; /*!< preserved Hardware Configuration 2 */ -+ hwcfg3_data_t hwcfg3; /*!< preserved Hardware Configuration 3 */ -+ hwcfg4_data_t hwcfg4; /*!< preserved Hardware Configuration 3 */ -+ uint32_t snpsid; /*!< preserved SNPSID */ -+ -+ /***************************************************************** -+ * Run-time informations. -+ *****************************************************************/ -+ /* Set to 1 if the core PHY interface bits in USBCFG have been initialized. */ -+ uint8_t phy_init_done; /*!< indicated PHY is initialized. */ -+ -+ #ifdef __IS_HOST__ -+ uint8_t queuing_high_bandwidth; /*!< Host mode, Queueing High Bandwidth. */ -+ #endif -+} ifxusb_core_if_t; -+ -+/*@}*//*IFXUSB_CIF*/ -+ -+ -+/*! -+ \fn void *ifxusb_alloc_buf(size_t size, int clear) -+ \brief This function is called to allocate buffer of specified size. -+ The allocated buffer is mapped into DMA accessable address. -+ \param size Size in BYTE to be allocated -+ \param clear 0: don't do clear after buffer allocated, other: do clear to zero -+ \return 0/NULL: Fail; uncached pointer of allocated buffer -+ \ingroup IFXUSB_CIF -+ */ -+extern void *ifxusb_alloc_buf(size_t size, int clear); -+ -+/*! -+ \fn void ifxusb_free_buf(void *vaddr) -+ \brief This function is called to free allocated buffer. -+ \param vaddr the uncached pointer of the buffer -+ \ingroup IFXUSB_CIF -+ */ -+extern void ifxusb_free_buf(void *vaddr); -+ -+/*! -+ \fn int ifxusb_core_if_init(ifxusb_core_if_t *_core_if, -+ int _irq, -+ uint32_t _reg_base_addr, -+ uint32_t _fifo_base_addr, -+ uint32_t _fifo_dbg_addr) -+ \brief This function is called to initialize the IFXUSB CSR data -+ structures. The register addresses in the device and host -+ structures are initialized from the base address supplied by the -+ caller. The calling function must make the OS calls to get the -+ base address of the IFXUSB controller registers. -+ \param _core_if Pointer of core_if structure -+ \param _irq irq number -+ \param _reg_base_addr Base address of IFXUSB core registers -+ \param _fifo_base_addr Fifo base address -+ \param _fifo_dbg_addr Fifo debug address -+ \return 0: success; -+ \ingroup IFXUSB_CIF -+ */ -+extern int ifxusb_core_if_init(ifxusb_core_if_t *_core_if, -+ int _irq, -+ uint32_t _reg_base_addr, -+ uint32_t _fifo_base_addr, -+ uint32_t _fifo_dbg_addr); -+ -+ -+/*! -+ \fn void ifxusb_core_if_remove(ifxusb_core_if_t *_core_if) -+ \brief This function free the mapped address in the IFXUSB CSR data structures. -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+ */ -+extern void ifxusb_core_if_remove(ifxusb_core_if_t *_core_if); -+ -+/*! -+ \fn void ifxusb_enable_global_interrupts( ifxusb_core_if_t *_core_if ) -+ \brief This function enbles the controller's Global Interrupt in the AHB Config register. -+ \param _core_if Pointer of core_if structure -+ */ -+extern void ifxusb_enable_global_interrupts( ifxusb_core_if_t *_core_if ); -+ -+/*! -+ \fn void ifxusb_disable_global_interrupts( ifxusb_core_if_t *_core_if ) -+ \brief This function disables the controller's Global Interrupt in the AHB Config register. -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+ */ -+extern void ifxusb_disable_global_interrupts( ifxusb_core_if_t *_core_if ); -+ -+/*! -+ \fn void ifxusb_flush_tx_fifo( ifxusb_core_if_t *_core_if, const int _num ) -+ \brief Flush a Tx FIFO. -+ \param _core_if Pointer of core_if structure -+ \param _num Tx FIFO to flush. ( 0x10 for ALL TX FIFO ) -+ \ingroup IFXUSB_CIF -+ */ -+extern void ifxusb_flush_tx_fifo( ifxusb_core_if_t *_core_if, const int _num ); -+ -+/*! -+ \fn void ifxusb_flush_rx_fifo( ifxusb_core_if_t *_core_if ) -+ \brief Flush Rx FIFO. -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+ */ -+extern void ifxusb_flush_rx_fifo( ifxusb_core_if_t *_core_if ); -+ -+/*! -+ \fn void ifxusb_flush_both_fifo( ifxusb_core_if_t *_core_if ) -+ \brief Flush ALL Rx and Tx FIFO. -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+ */ -+extern void ifxusb_flush_both_fifo( ifxusb_core_if_t *_core_if ); -+ -+ -+/*! -+ \fn int ifxusb_core_soft_reset(ifxusb_core_if_t *_core_if) -+ \brief Do core a soft reset of the core. Be careful with this because it -+ resets all the internal state machines of the core. -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+ */ -+extern int ifxusb_core_soft_reset(ifxusb_core_if_t *_core_if); -+ -+ -+/*! -+ \brief Turn on the USB Core Power -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+*/ -+extern void ifxusb_power_on (ifxusb_core_if_t *_core_if); -+ -+/*! -+ \fn void ifxusb_power_off (ifxusb_core_if_t *_core_if) -+ \brief Turn off the USB Core Power -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+*/ -+extern void ifxusb_power_off (ifxusb_core_if_t *_core_if); -+ -+/*! -+ \fn void ifxusb_phy_power_on (ifxusb_core_if_t *_core_if) -+ \brief Turn on the USB PHY Power -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+*/ -+extern void ifxusb_phy_power_on (ifxusb_core_if_t *_core_if); -+ -+/*! -+ \fn void ifxusb_phy_power_off (ifxusb_core_if_t *_core_if) -+ \brief Turn off the USB PHY Power -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+*/ -+extern void ifxusb_phy_power_off (ifxusb_core_if_t *_core_if); -+ -+/*! -+ \fn void ifxusb_hard_reset(ifxusb_core_if_t *_core_if) -+ \brief Reset on the USB Core RCU -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+ */ -+extern void ifxusb_hard_reset(ifxusb_core_if_t *_core_if); -+ -+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+ -+#ifdef __IS_HOST__ -+ /*! -+ \fn void ifxusb_host_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params) -+ \brief This function initializes the IFXUSB controller registers for Host mode. -+ This function flushes the Tx and Rx FIFOs and it flushes any entries in the -+ request queues. -+ \param _core_if Pointer of core_if structure -+ \param _params parameters to be set -+ \ingroup IFXUSB_CIF -+ */ -+ extern void ifxusb_host_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params); -+ -+ /*! -+ \fn void ifxusb_host_enable_interrupts(ifxusb_core_if_t *_core_if) -+ \brief This function enables the Host mode interrupts. -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+ */ -+ extern void ifxusb_host_enable_interrupts(ifxusb_core_if_t *_core_if); -+ -+ /*! -+ \fn void ifxusb_host_disable_interrupts(ifxusb_core_if_t *_core_if) -+ \brief This function disables the Host mode interrupts. -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+ */ -+ extern void ifxusb_host_disable_interrupts(ifxusb_core_if_t *_core_if); -+ -+ #if defined(__IS_TWINPASS__) -+ extern void ifxusb_enable_afe_oc(void); -+ #endif -+ -+ /*! -+ \fn void ifxusb_vbus_init(ifxusb_core_if_t *_core_if) -+ \brief This function init the VBUS control. -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+ */ -+ extern void ifxusb_vbus_init(ifxusb_core_if_t *_core_if); -+ -+ /*! -+ \fn void ifxusb_vbus_free(ifxusb_core_if_t *_core_if) -+ \brief This function free the VBUS control. -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+ */ -+ extern void ifxusb_vbus_free(ifxusb_core_if_t *_core_if); -+ -+ /*! -+ \fn void ifxusb_vbus_on(ifxusb_core_if_t *_core_if) -+ \brief Turn on the USB 5V VBus Power -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+ */ -+ extern void ifxusb_vbus_on(ifxusb_core_if_t *_core_if); -+ -+ /*! -+ \fn void ifxusb_vbus_off(ifxusb_core_if_t *_core_if) -+ \brief Turn off the USB 5V VBus Power -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+ */ -+ extern void ifxusb_vbus_off(ifxusb_core_if_t *_core_if); -+ -+ /*! -+ \fn int ifxusb_vbus(ifxusb_core_if_t *_core_if) -+ \brief Read Current VBus status -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+ */ -+ extern int ifxusb_vbus(ifxusb_core_if_t *_core_if); -+ -+ #if defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__) -+ /*! -+ \fn void ifxusb_oc_int_on(void) -+ \brief Turn on the OC interrupt -+ \ingroup IFXUSB_CIF -+ */ -+ extern void ifxusb_oc_int_on(void); -+ -+ /*! -+ \fn void ifxusb_oc_int_off(void) -+ \brief Turn off the OC interrupt -+ \ingroup IFXUSB_CIF -+ */ -+ extern void ifxusb_oc_int_off(void); -+ #endif //defined(__DO_OC_INT__) && defined(__DO_OC_INT_ENABLE__) -+#endif -+ -+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+ -+#ifdef __IS_DEVICE__ -+ /*! -+ \fn void ifxusb_dev_enable_interrupts(ifxusb_core_if_t *_core_if) -+ \brief This function enables the Device mode interrupts. -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+ */ -+ extern void ifxusb_dev_enable_interrupts(ifxusb_core_if_t *_core_if); -+ -+ /*! -+ \fn uint32_t ifxusb_dev_get_frame_number(ifxusb_core_if_t *_core_if) -+ \brief Gets the current USB frame number. This is the frame number from the last SOF packet. -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+ */ -+ extern uint32_t ifxusb_dev_get_frame_number(ifxusb_core_if_t *_core_if); -+ -+ /*! -+ \fn void ifxusb_dev_ep_set_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _is_in) -+ \brief Set the EP STALL. -+ \param _core_if Pointer of core_if structure -+ \param _epno EP number -+ \param _is_in 1: is IN transfer -+ \ingroup IFXUSB_CIF -+ */ -+ extern void ifxusb_dev_ep_set_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _is_in); -+ -+ /*! -+ \fn void ifxusb_dev_ep_clear_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _ep_type, uint8_t _is_in) -+ \brief Set the EP STALL. -+ \param _core_if Pointer of core_if structure -+ \param _epno EP number -+ \param _ep_type EP Type -+ \ingroup IFXUSB_CIF -+ */ -+ extern void ifxusb_dev_ep_clear_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _ep_type, uint8_t _is_in); -+ -+ /*! -+ \fn void ifxusb_dev_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params) -+ \brief This function initializes the IFXUSB controller registers for Device mode. -+ This function flushes the Tx and Rx FIFOs and it flushes any entries in the -+ request queues. -+ This function validate the imported parameters and store the result in the CIF structure. -+ After -+ \param _core_if Pointer of core_if structure -+ \param _params structure of inported parameters -+ \ingroup IFXUSB_CIF -+ */ -+ extern void ifxusb_dev_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params); -+#endif -+ -+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+#if defined(__GADGET_LED__) || defined(__HOST_LED__) -+ /*! -+ \fn void ifxusb_led_init(ifxusb_core_if_t *_core_if) -+ \brief This function init the LED control. -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+ */ -+ extern void ifxusb_led_init(ifxusb_core_if_t *_core_if); -+ -+ /*! -+ \fn void ifxusb_led_free(ifxusb_core_if_t *_core_if) -+ \brief This function free the LED control. -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+ */ -+ extern void ifxusb_led_free(ifxusb_core_if_t *_core_if); -+ -+ /*! -+ \fn void ifxusb_led(ifxusb_core_if_t *_core_if) -+ \brief This function trigger the LED access. -+ \param _core_if Pointer of core_if structure -+ \ingroup IFXUSB_CIF -+ */ -+ extern void ifxusb_led(ifxusb_core_if_t *_core_if); -+#endif -+ -+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+/* internal routines for debugging */ -+extern void ifxusb_dump_msg(const u8 *buf, unsigned int length); -+extern void ifxusb_dump_spram(ifxusb_core_if_t *_core_if); -+extern void ifxusb_dump_registers(ifxusb_core_if_t *_core_if); -+extern void ifxusb_clean_spram(ifxusb_core_if_t *_core_if,uint32_t dwords); -+ -+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+static inline uint32_t ifxusb_read_core_intr(ifxusb_core_if_t *_core_if) -+{ -+ return (ifxusb_rreg(&_core_if->core_global_regs->gintsts) & -+ (ifxusb_rreg(&_core_if->core_global_regs->gintmsk) -+#ifdef __USE_TIMER_4_SOF__ -+ | IFXUSB_SOF_INTR_MASK -+#endif -+ )); -+} -+ -+static inline uint32_t ifxusb_read_otg_intr (ifxusb_core_if_t *_core_if) -+{ -+ return (ifxusb_rreg (&_core_if->core_global_regs->gotgint)); -+} -+ -+static inline uint32_t ifxusb_mode(ifxusb_core_if_t *_core_if) -+{ -+ return (ifxusb_rreg( &_core_if->core_global_regs->gintsts ) & 0x1); -+} -+static inline uint8_t ifxusb_is_device_mode(ifxusb_core_if_t *_core_if) -+{ -+ return (ifxusb_mode(_core_if) != 1); -+} -+static inline uint8_t ifxusb_is_host_mode(ifxusb_core_if_t *_core_if) -+{ -+ return (ifxusb_mode(_core_if) == 1); -+} -+ -+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+#ifdef __IS_HOST__ -+ static inline uint32_t ifxusb_read_hprt0(ifxusb_core_if_t *_core_if) -+ { -+ hprt0_data_t hprt0; -+ hprt0.d32 = ifxusb_rreg(_core_if->hprt0); -+ hprt0.b.prtena = 0; -+ hprt0.b.prtconndet = 0; -+ hprt0.b.prtenchng = 0; -+ hprt0.b.prtovrcurrchng = 0; -+ return hprt0.d32; -+ } -+ -+ static inline uint32_t ifxusb_read_host_all_channels_intr (ifxusb_core_if_t *_core_if) -+ { -+ return (ifxusb_rreg (&_core_if->host_global_regs->haint)); -+ } -+ -+ static inline uint32_t ifxusb_read_host_channel_intr (ifxusb_core_if_t *_core_if, int hc_num) -+ { -+ return (ifxusb_rreg (&_core_if->hc_regs[hc_num]->hcint)); -+ } -+#endif -+ -+#ifdef __IS_DEVICE__ -+ static inline uint32_t ifxusb_read_dev_all_in_ep_intr(ifxusb_core_if_t *_core_if) -+ { -+ uint32_t v; -+ v = ifxusb_rreg(&_core_if->dev_global_regs->daint) & -+ ifxusb_rreg(&_core_if->dev_global_regs->daintmsk); -+ return (v & 0xffff); -+ } -+ -+ static inline uint32_t ifxusb_read_dev_all_out_ep_intr(ifxusb_core_if_t *_core_if) -+ { -+ uint32_t v; -+ v = ifxusb_rreg(&_core_if->dev_global_regs->daint) & -+ ifxusb_rreg(&_core_if->dev_global_regs->daintmsk); -+ return ((v & 0xffff0000) >> 16); -+ } -+ -+ static inline uint32_t ifxusb_read_dev_in_ep_intr(ifxusb_core_if_t *_core_if, int _ep_num) -+ { -+ uint32_t v; -+ v = ifxusb_rreg(&_core_if->in_ep_regs[_ep_num]->diepint) & -+ ifxusb_rreg(&_core_if->dev_global_regs->diepmsk); -+ return v; -+ } -+ -+ static inline uint32_t ifxusb_read_dev_out_ep_intr(ifxusb_core_if_t *_core_if, int _ep_num) -+ { -+ uint32_t v; -+ v = ifxusb_rreg(&_core_if->out_ep_regs[_ep_num]->doepint) & -+ ifxusb_rreg(&_core_if->dev_global_regs->doepmsk); -+ return v; -+ } -+ -+#endif -+ -+extern void ifxusb_attr_create (void *_dev); -+ -+extern void ifxusb_attr_remove (void *_dev); -+ -+/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+#endif // !defined(__IFXUSB_CIF_H__) -+ -+ ---- /dev/null -+++ b/drivers/usb/ifxhcd/ifxusb_cif_d.c -@@ -0,0 +1,458 @@ -+/***************************************************************************** -+ ** FILE NAME : ifxusb_cif_d.c -+ ** PROJECT : IFX USB sub-system V3 -+ ** MODULES : IFX USB sub-system Host and Device driver -+ ** SRC VERSION : 1.0 -+ ** DATE : 1/Jan/2009 -+ ** AUTHOR : Chen, Howard -+ ** DESCRIPTION : The Core Interface provides basic services for accessing and -+ ** managing the IFX USB hardware. These services are used by the -+ ** Peripheral Controller Driver only. -+ *****************************************************************************/ -+ -+/*! -+ \file ifxusb_cif_d.c -+ \ingroup IFXUSB_DRIVER_V3 -+ \brief This file contains the interface to the IFX USB Core. -+*/ -+ -+#include -+#include "ifxusb_version.h" -+ -+ -+#include -+#include -+ -+#ifdef __DEBUG__ -+ #include -+#endif -+ -+#include "ifxusb_plat.h" -+#include "ifxusb_regs.h" -+#include "ifxusb_cif.h" -+ -+#include "ifxpcd.h" -+ -+ -+ -+/*! -+ \brief Initializes the DevSpd field of the DCFG register depending on the PHY type -+ and the enumeration speed of the device. -+ \param _core_if Pointer of core_if structure -+ */ -+void ifxusb_dev_init_spd(ifxusb_core_if_t *_core_if) -+{ -+ uint32_t val; -+ dcfg_data_t dcfg; -+ -+ IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); -+ if (_core_if->params.speed == IFXUSB_PARAM_SPEED_FULL) -+ /* High speed PHY running at full speed */ -+ val = 0x1; -+ else -+ /* High speed PHY running at high speed and full speed*/ -+ val = 0x0; -+ -+ IFX_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val); -+ dcfg.d32 = ifxusb_rreg(&_core_if->dev_global_regs->dcfg); -+ dcfg.b.devspd = val; -+ ifxusb_wreg(&_core_if->dev_global_regs->dcfg, dcfg.d32); -+} -+ -+ -+/*! -+ \brief This function enables the Device mode interrupts. -+ \param _core_if Pointer of core_if structure -+ */ -+void ifxusb_dev_enable_interrupts(ifxusb_core_if_t *_core_if) -+{ -+ gint_data_t intr_mask ={ .d32 = 0}; -+ ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; -+ -+ IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); -+ IFX_DEBUGPL(DBG_CIL, "%s()\n", __func__); -+ -+ /* Clear any pending OTG Interrupts */ -+ ifxusb_wreg( &global_regs->gotgint, 0xFFFFFFFF); -+ -+ /* Clear any pending interrupts */ -+ ifxusb_wreg( &global_regs->gintsts, 0xFFFFFFFF); -+ -+ /* Enable the interrupts in the GINTMSK.*/ -+ intr_mask.b.modemismatch = 1; -+ intr_mask.b.conidstschng = 1; -+ intr_mask.b.wkupintr = 1; -+ intr_mask.b.disconnect = 1; -+ intr_mask.b.usbsuspend = 1; -+ -+ intr_mask.b.usbreset = 1; -+ intr_mask.b.enumdone = 1; -+ intr_mask.b.inepintr = 1; -+ intr_mask.b.outepintr = 1; -+ intr_mask.b.erlysuspend = 1; -+ #ifndef __DED_FIFO__ -+// intr_mask.b.epmismatch = 1; -+ #endif -+ -+ ifxusb_mreg( &global_regs->gintmsk, intr_mask.d32, intr_mask.d32); -+ IFX_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, ifxusb_rreg( &global_regs->gintmsk)); -+} -+ -+/*! -+ \brief Gets the current USB frame number. This is the frame number from the last SOF packet. -+ \param _core_if Pointer of core_if structure -+ */ -+uint32_t ifxusb_dev_get_frame_number(ifxusb_core_if_t *_core_if) -+{ -+ dsts_data_t dsts; -+ IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); -+ dsts.d32 = ifxusb_rreg(&_core_if->dev_global_regs->dsts); -+ /* read current frame/microfreme number from DSTS register */ -+ return dsts.b.soffn; -+} -+ -+ -+/*! -+ \brief Set the EP STALL. -+ */ -+void ifxusb_dev_ep_set_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _is_in) -+{ -+ depctl_data_t depctl; -+ volatile uint32_t *depctl_addr; -+ -+ IFX_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _epno, (_is_in?"IN":"OUT")); -+ -+ depctl_addr = (_is_in)? (&(_core_if->in_ep_regs [_epno]->diepctl)): -+ (&(_core_if->out_ep_regs[_epno]->doepctl)); -+ depctl.d32 = ifxusb_rreg(depctl_addr); -+ depctl.b.stall = 1; -+ -+ if (_is_in && depctl.b.epena) -+ depctl.b.epdis = 1; -+ -+ ifxusb_wreg(depctl_addr, depctl.d32); -+ IFX_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",ifxusb_rreg(depctl_addr)); -+ return; -+} -+ -+/*! -+\brief Clear the EP STALL. -+ */ -+void ifxusb_dev_ep_clear_stall(ifxusb_core_if_t *_core_if, uint8_t _epno, uint8_t _ep_type, uint8_t _is_in) -+{ -+ depctl_data_t depctl; -+ volatile uint32_t *depctl_addr; -+ -+ IFX_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _epno, (_is_in?"IN":"OUT")); -+ -+ depctl_addr = (_is_in)? (&(_core_if->in_ep_regs [_epno]->diepctl)): -+ (&(_core_if->out_ep_regs[_epno]->doepctl)); -+ -+ depctl.d32 = ifxusb_rreg(depctl_addr); -+ /* clear the stall bits */ -+ depctl.b.stall = 0; -+ -+ /* -+ * USB Spec 9.4.5: For endpoints using data toggle, regardless -+ * of whether an endpoint has the Halt feature set, a -+ * ClearFeature(ENDPOINT_HALT) request always results in the -+ * data toggle being reinitialized to DATA0. -+ */ -+ if (_ep_type == IFXUSB_EP_TYPE_INTR || _ep_type == IFXUSB_EP_TYPE_BULK) -+ depctl.b.setd0pid = 1; /* DATA0 */ -+ -+ ifxusb_wreg(depctl_addr, depctl.d32); -+ IFX_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",ifxusb_rreg(depctl_addr)); -+ return; -+} -+ -+/*! -+ \brief This function initializes the IFXUSB controller registers for Device mode. -+ This function flushes the Tx and Rx FIFOs and it flushes any entries in the -+ request queues. -+ \param _core_if Pointer of core_if structure -+ \param _params parameters to be set -+ */ -+void ifxusb_dev_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params) -+{ -+ ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; -+ -+ gusbcfg_data_t usbcfg ={.d32 = 0}; -+ gahbcfg_data_t ahbcfg ={.d32 = 0}; -+ dcfg_data_t dcfg ={.d32 = 0}; -+ grstctl_t resetctl ={.d32 = 0}; -+ gotgctl_data_t gotgctl ={.d32 = 0}; -+ -+ uint32_t dir; -+ int i; -+ -+ IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); -+ IFX_DEBUGPL(DBG_CILV, "%s(%p)\n",__func__,_core_if); -+ -+ /* Copy Params */ -+ _core_if->params.dma_burst_size = _params->dma_burst_size; -+ _core_if->params.speed = _params->speed; -+ if(_params->max_transfer_size < 2048 || _params->max_transfer_size > ((1 << (_core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1) ) -+ _core_if->params.max_transfer_size = ((1 << (_core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1); -+ else -+ _core_if->params.max_transfer_size = _params->max_transfer_size; -+ -+ if(_params->max_packet_count < 16 || _params->max_packet_count > ((1 << (_core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1) ) -+ _core_if->params.max_packet_count= ((1 << (_core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1); -+ else -+ _core_if->params.max_packet_count= _params->max_packet_count; -+ _core_if->params.phy_utmi_width = _params->phy_utmi_width; -+ _core_if->params.turn_around_time_hs = _params->turn_around_time_hs; -+ _core_if->params.turn_around_time_fs = _params->turn_around_time_fs; -+ _core_if->params.timeout_cal_hs = _params->timeout_cal_hs; -+ _core_if->params.timeout_cal_fs = _params->timeout_cal_fs; -+ -+ #ifdef __DED_FIFO__ -+ _core_if->params.thr_ctl = _params->thr_ctl; -+ _core_if->params.tx_thr_length = _params->tx_thr_length; -+ _core_if->params.rx_thr_length = _params->rx_thr_length; -+ #endif -+ -+ /* Reset the Controller */ -+ do -+ { -+ while(ifxusb_core_soft_reset( _core_if )) -+ ifxusb_hard_reset(_core_if); -+ } while (ifxusb_is_host_mode(_core_if)); -+ -+ usbcfg.d32 = ifxusb_rreg(&global_regs->gusbcfg); -+ #if 0 -+ #if defined(__DED_FIFO__) -+ usbcfg.b.ForceDevMode = 1; -+ usbcfg.b.ForceHstMode = 0; -+ #endif -+ #endif -+ usbcfg.b.term_sel_dl_pulse = 0; -+ ifxusb_wreg (&global_regs->gusbcfg, usbcfg.d32); -+ -+ /* This programming sequence needs to happen in FS mode before any other -+ * programming occurs */ -+ /* High speed PHY. */ -+ if (!_core_if->phy_init_done) -+ { -+ _core_if->phy_init_done = 1; -+ /* HS PHY parameters. These parameters are preserved -+ * during soft reset so only program the first time. Do -+ * a soft reset immediately after setting phyif. */ -+ usbcfg.b.ulpi_utmi_sel = 0; //UTMI+ -+ usbcfg.b.phyif = ( _core_if->params.phy_utmi_width == 16)?1:0; -+ ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32); -+ /* Reset after setting the PHY parameters */ -+ ifxusb_core_soft_reset( _core_if ); -+ } -+ -+ /* Program the GAHBCFG Register.*/ -+ switch (_core_if->params.dma_burst_size) -+ { -+ case 0 : -+ ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_SINGLE; -+ break; -+ case 1 : -+ ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR; -+ break; -+ case 4 : -+ ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR4; -+ break; -+ case 8 : -+ ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR8; -+ break; -+ case 16: -+ ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR16; -+ break; -+ } -+ ahbcfg.b.dmaenable = 1; -+ ifxusb_wreg(&global_regs->gahbcfg, ahbcfg.d32); -+ -+ /* Program the GUSBCFG register. */ -+ usbcfg.d32 = ifxusb_rreg( &global_regs->gusbcfg ); -+ usbcfg.b.hnpcap = 0; -+ usbcfg.b.srpcap = 0; -+ ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32); -+ -+ /* Restart the Phy Clock */ -+ ifxusb_wreg(_core_if->pcgcctl, 0); -+ -+ /* Device configuration register */ -+ ifxusb_dev_init_spd(_core_if); -+ dcfg.d32 = ifxusb_rreg( &_core_if->dev_global_regs->dcfg); -+ dcfg.b.perfrint = IFXUSB_DCFG_FRAME_INTERVAL_80; -+ #if defined(__DED_FIFO__) -+ #if defined(__DESC_DMA__) -+ dcfg.b.descdma = 1; -+ #else -+ dcfg.b.descdma = 0; -+ #endif -+ #endif -+ -+ ifxusb_wreg( &_core_if->dev_global_regs->dcfg, dcfg.d32 ); -+ -+ /* Configure data FIFO sizes */ -+ _core_if->params.data_fifo_size = _core_if->hwcfg3.b.dfifo_depth; -+ _core_if->params.rx_fifo_size = ifxusb_rreg(&global_regs->grxfsiz); -+ IFX_DEBUGPL(DBG_CIL, "Initial: FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size); -+ IFX_DEBUGPL(DBG_CIL, " Rx FIFO Size=0x%06X\n", _core_if->params.rx_fifo_size); -+ -+ _core_if->params.tx_fifo_size[0]= ifxusb_rreg(&global_regs->gnptxfsiz) >> 16; -+ -+ #ifdef __DED_FIFO__ -+ for (i=1; i <= _core_if->hwcfg4.b.num_in_eps; i++) -+ _core_if->params.tx_fifo_size[i] = -+ ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i-1]) >> 16; -+ #else -+ for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++) -+ _core_if->params.tx_fifo_size[i+1] = -+ ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i]) >> 16; -+ #endif -+ -+ #ifdef __DEBUG__ -+ #ifdef __DED_FIFO__ -+ for (i=0; i <= _core_if->hwcfg4.b.num_in_eps; i++) -+ IFX_DEBUGPL(DBG_CIL, " Tx[%02d] FIFO Size=0x%06X\n",i, _core_if->params.tx_fifo_size[i]); -+ #else -+ IFX_DEBUGPL(DBG_CIL, " NPTx FIFO Size=0x%06X\n", _core_if->params.tx_fifo_size[0]); -+ for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++) -+ IFX_DEBUGPL(DBG_CIL, " PTx[%02d] FIFO Size=0x%06X\n",i, _core_if->params.tx_fifo_size[i+1]); -+ #endif -+ #endif -+ -+ { -+ fifosize_data_t txfifosize; -+ if(_params->data_fifo_size >=0 && _params->data_fifo_size < _core_if->params.data_fifo_size) -+ _core_if->params.data_fifo_size = _params->data_fifo_size; -+ -+ -+ if(_params->rx_fifo_size >=0 && _params->rx_fifo_size < _core_if->params.rx_fifo_size) -+ _core_if->params.rx_fifo_size = _params->rx_fifo_size; -+ if(_core_if->params.data_fifo_size < _core_if->params.rx_fifo_size) -+ _core_if->params.rx_fifo_size = _core_if->params.data_fifo_size; -+ ifxusb_wreg( &global_regs->grxfsiz, _core_if->params.rx_fifo_size); -+ -+ for (i=0; i < MAX_EPS_CHANNELS; i++) -+ if(_params->tx_fifo_size[i] >=0 && _params->tx_fifo_size[i] < _core_if->params.tx_fifo_size[i]) -+ _core_if->params.tx_fifo_size[i] = _params->tx_fifo_size[i]; -+ -+ txfifosize.b.startaddr = _core_if->params.rx_fifo_size; -+ #ifdef __DED_FIFO__ -+ if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[0] > _core_if->params.data_fifo_size) -+ _core_if->params.tx_fifo_size[0]= _core_if->params.data_fifo_size - txfifosize.b.startaddr; -+ txfifosize.b.depth=_core_if->params.tx_fifo_size[0]; -+ ifxusb_wreg( &global_regs->gnptxfsiz, txfifosize.d32); -+ txfifosize.b.startaddr += _core_if->params.tx_fifo_size[0]; -+ for (i=1; i <= _core_if->hwcfg4.b.num_in_eps; i++) -+ { -+ if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[i] > _core_if->params.data_fifo_size) -+ _core_if->params.tx_fifo_size[i]= _core_if->params.data_fifo_size - txfifosize.b.startaddr; -+ txfifosize.b.depth=_core_if->params.tx_fifo_size[i]; -+ ifxusb_wreg( &global_regs->dptxfsiz_dieptxf[i-1], txfifosize.d32); -+ txfifosize.b.startaddr += _core_if->params.tx_fifo_size[i]; -+ } -+ #else -+ if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[0] > _core_if->params.data_fifo_size) -+ _core_if->params.tx_fifo_size[0]= _core_if->params.data_fifo_size - txfifosize.b.startaddr; -+ txfifosize.b.depth=_core_if->params.tx_fifo_size[0]; -+ ifxusb_wreg( &global_regs->gnptxfsiz, txfifosize.d32); -+ txfifosize.b.startaddr += _core_if->params.tx_fifo_size[0]; -+ for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++) -+ { -+ if(txfifosize.b.startaddr + _core_if->params.tx_fifo_size[i+1] > _core_if->params.data_fifo_size) -+ _core_if->params.tx_fifo_size[i+1]= _core_if->params.data_fifo_size - txfifosize.b.startaddr; -+ //txfifosize.b.depth=_core_if->params.tx_fifo_size[i+1]; -+ ifxusb_wreg( &global_regs->dptxfsiz_dieptxf[i], txfifosize.d32); -+ txfifosize.b.startaddr += _core_if->params.tx_fifo_size[i+1]; -+ } -+ #endif -+ } -+ -+ #ifdef __DEBUG__ -+ { -+ fifosize_data_t fifosize; -+ IFX_DEBUGPL(DBG_CIL, "Result : FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size); -+ -+ IFX_DEBUGPL(DBG_CIL, " Rx FIFO =0x%06X Sz=0x%06X\n", 0,ifxusb_rreg(&global_regs->grxfsiz)); -+ #ifdef __DED_FIFO__ -+ fifosize.d32=ifxusb_rreg(&global_regs->gnptxfsiz); -+ IFX_DEBUGPL(DBG_CIL, " Tx[00] FIFO =0x%06X Sz=0x%06X\n", fifosize.b.startaddr,fifosize.b.depth); -+ for (i=1; i <= _core_if->hwcfg4.b.num_in_eps; i++) -+ { -+ fifosize.d32=ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i-1]); -+ IFX_DEBUGPL(DBG_CIL, " Tx[%02d] FIFO 0x%06X Sz=0x%06X\n",i, fifosize.b.startaddr,fifosize.b.depth); -+ } -+ #else -+ fifosize.d32=ifxusb_rreg(&global_regs->gnptxfsiz); -+ IFX_DEBUGPL(DBG_CIL, " NPTx FIFO =0x%06X Sz=0x%06X\n", fifosize.b.startaddr,fifosize.b.depth); -+ for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++) -+ { -+ fifosize.d32=ifxusb_rreg(&global_regs->dptxfsiz_dieptxf[i]); -+ IFX_DEBUGPL(DBG_CIL, " PTx[%02d] FIFO 0x%06X Sz=0x%06X\n",i, fifosize.b.startaddr,fifosize.b.depth); -+ } -+ #endif -+ } -+ #endif -+ -+ /* Clear Host Set HNP Enable in the OTG Control Register */ -+ gotgctl.b.hstsethnpen = 1; -+ ifxusb_mreg( &global_regs->gotgctl, gotgctl.d32, 0); -+ -+ /* Flush the FIFOs */ -+ ifxusb_flush_tx_fifo(_core_if, 0x10); /* all Tx FIFOs */ -+ ifxusb_flush_rx_fifo(_core_if); -+ -+ /* Flush the Learning Queue. */ -+ resetctl.b.intknqflsh = 1; -+ ifxusb_wreg( &global_regs->grstctl, resetctl.d32); -+ -+ /* Clear all pending Device Interrupts */ -+ ifxusb_wreg( &_core_if->dev_global_regs->diepmsk , 0 ); -+ ifxusb_wreg( &_core_if->dev_global_regs->doepmsk , 0 ); -+ ifxusb_wreg( &_core_if->dev_global_regs->daint , 0xFFFFFFFF ); -+ ifxusb_wreg( &_core_if->dev_global_regs->daintmsk, 0 ); -+ -+ dir=_core_if->hwcfg1.d32; -+ for (i=0; i <= _core_if->hwcfg2.b.num_dev_ep ; i++,dir>>=2) -+ { -+ depctl_data_t depctl; -+ if((dir&0x03)==0 || (dir&0x03) ==1) -+ { -+ depctl.d32 = ifxusb_rreg(&_core_if->in_ep_regs[i]->diepctl); -+ if (depctl.b.epena) -+ { -+ depctl.d32 = 0; -+ depctl.b.epdis = 1; -+ depctl.b.snak = 1; -+ } -+ else -+ depctl.d32 = 0; -+ ifxusb_wreg( &_core_if->in_ep_regs[i]->diepctl, depctl.d32); -+ #ifndef __DESC_DMA__ -+ ifxusb_wreg( &_core_if->in_ep_regs[i]->dieptsiz, 0); -+ #endif -+ ifxusb_wreg( &_core_if->in_ep_regs[i]->diepdma, 0); -+ ifxusb_wreg( &_core_if->in_ep_regs[i]->diepint, 0xFF); -+ } -+ -+ if((dir&0x03)==0 || (dir&0x03) ==2) -+ { -+ depctl.d32 = ifxusb_rreg(&_core_if->out_ep_regs[i]->doepctl); -+ if (depctl.b.epena) -+ { -+ depctl.d32 = 0; -+ depctl.b.epdis = 1; -+ depctl.b.snak = 1; -+ } -+ else -+ depctl.d32 = 0; -+ ifxusb_wreg( &_core_if->out_ep_regs[i]->doepctl, depctl.d32); -+ #ifndef __DESC_DMA__ -+ ifxusb_wreg( &_core_if->out_ep_regs[i]->doeptsiz, 0); -+ #endif -+ ifxusb_wreg( &_core_if->out_ep_regs[i]->doepdma, 0); -+ ifxusb_wreg( &_core_if->out_ep_regs[i]->doepint, 0xFF); -+ } -+ } -+} -+ ---- /dev/null -+++ b/drivers/usb/ifxhcd/ifxusb_cif_h.c -@@ -0,0 +1,846 @@ -+/***************************************************************************** -+ ** FILE NAME : ifxusb_cif_h.c -+ ** PROJECT : IFX USB sub-system V3 -+ ** MODULES : IFX USB sub-system Host and Device driver -+ ** SRC VERSION : 1.0 -+ ** DATE : 1/Jan/2009 -+ ** AUTHOR : Chen, Howard -+ ** DESCRIPTION : The Core Interface provides basic services for accessing and -+ ** managing the IFX USB hardware. These services are used by the -+ ** Host Controller Driver only. -+ *****************************************************************************/ -+ -+/*! -+ \file ifxusb_cif_h.c -+ \ingroup IFXUSB_DRIVER_V3 -+ \brief This file contains the interface to the IFX USB Core. -+*/ -+#include -+#include "ifxusb_version.h" -+ -+#include -+#include -+ -+#ifdef __DEBUG__ -+ #include -+#endif -+#include -+#include -+#include -+#if defined(__UEIP__) -+// #include -+#endif -+ -+//#include -+#if defined(__UEIP__) -+// #include -+#endif -+ -+#include "ifxusb_plat.h" -+#include "ifxusb_regs.h" -+#include "ifxusb_cif.h" -+ -+#include "ifxhcd.h" -+ -+#if !defined(__UEIP__) -+ #undef __USING_LED_AS_GPIO__ -+#endif -+ -+ -+/*! -+ \brief This function enables the Host mode interrupts. -+ \param _core_if Pointer of core_if structure -+ */ -+void ifxusb_host_enable_interrupts(ifxusb_core_if_t *_core_if) -+{ -+ gint_data_t intr_mask ={ .d32 = 0}; -+ ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; -+ -+ IFX_DEBUGPL(DBG_CIL, "%s()\n", __func__); -+ -+ /* Clear any pending OTG Interrupts */ -+ ifxusb_wreg( &global_regs->gotgint, 0xFFFFFFFF); -+ -+ /* Clear any pending interrupts */ -+ ifxusb_wreg( &global_regs->gintsts, 0xFFFFFFFF); -+ -+ /* Enable the interrupts in the GINTMSK.*/ -+ -+ /* Common interrupts */ -+ intr_mask.b.modemismatch = 1; -+ intr_mask.b.conidstschng = 1; -+ intr_mask.b.wkupintr = 1; -+ intr_mask.b.disconnect = 1; -+ intr_mask.b.usbsuspend = 1; -+ -+ /* Host interrupts */ -+ intr_mask.b.sofintr = 1; -+ intr_mask.b.portintr = 1; -+ intr_mask.b.hcintr = 1; -+ -+ ifxusb_mreg( &global_regs->gintmsk, intr_mask.d32, intr_mask.d32); -+ IFX_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, ifxusb_rreg( &global_regs->gintmsk)); -+} -+ -+/*! -+ \brief This function disables the Host mode interrupts. -+ \param _core_if Pointer of core_if structure -+ */ -+void ifxusb_host_disable_interrupts(ifxusb_core_if_t *_core_if) -+{ -+ ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; -+ -+ IFX_DEBUGPL(DBG_CILV, "%s()\n", __func__); -+ -+ #if 1 -+ ifxusb_wreg( &global_regs->gintmsk, 0); -+ #else -+ /* Common interrupts */ -+ { -+ gint_data_t intr_mask ={.d32 = 0}; -+ intr_mask.b.modemismatch = 1; -+ intr_mask.b.rxstsqlvl = 1; -+ intr_mask.b.conidstschng = 1; -+ intr_mask.b.wkupintr = 1; -+ intr_mask.b.disconnect = 1; -+ intr_mask.b.usbsuspend = 1; -+ -+ /* Host interrupts */ -+ intr_mask.b.sofintr = 1; -+ intr_mask.b.portintr = 1; -+ intr_mask.b.hcintr = 1; -+ intr_mask.b.ptxfempty = 1; -+ intr_mask.b.nptxfempty = 1; -+ ifxusb_mreg(&global_regs->gintmsk, intr_mask.d32, 0); -+ } -+ #endif -+} -+ -+/*! -+ \brief This function initializes the IFXUSB controller registers for Host mode. -+ This function flushes the Tx and Rx FIFOs and it flushes any entries in the -+ request queues. -+ \param _core_if Pointer of core_if structure -+ \param _params parameters to be set -+ */ -+void ifxusb_host_core_init(ifxusb_core_if_t *_core_if, ifxusb_params_t *_params) -+{ -+ ifxusb_core_global_regs_t *global_regs = _core_if->core_global_regs; -+ -+ gusbcfg_data_t usbcfg ={.d32 = 0}; -+ gahbcfg_data_t ahbcfg ={.d32 = 0}; -+ gotgctl_data_t gotgctl ={.d32 = 0}; -+ -+ int i; -+ -+ IFX_DEBUGPL(DBG_CILV, "%s(%p)\n",__func__,_core_if); -+ -+ /* Copy Params */ -+ -+ _core_if->params.dma_burst_size = _params->dma_burst_size; -+ _core_if->params.speed = _params->speed; -+ _core_if->params.max_transfer_size = _params->max_transfer_size; -+ _core_if->params.max_packet_count = _params->max_packet_count; -+ _core_if->params.phy_utmi_width = _params->phy_utmi_width; -+ _core_if->params.turn_around_time_hs = _params->turn_around_time_hs; -+ _core_if->params.turn_around_time_fs = _params->turn_around_time_fs; -+ _core_if->params.timeout_cal_hs = _params->timeout_cal_hs; -+ _core_if->params.timeout_cal_fs = _params->timeout_cal_fs; -+ -+ /* Reset the Controller */ -+ do -+ { -+ while(ifxusb_core_soft_reset( _core_if )) -+ ifxusb_hard_reset(_core_if); -+ } while (ifxusb_is_device_mode(_core_if)); -+ -+ usbcfg.d32 = ifxusb_rreg(&global_regs->gusbcfg); -+// usbcfg.b.ulpi_ext_vbus_drv = 1; -+ usbcfg.b.term_sel_dl_pulse = 0; -+ ifxusb_wreg (&global_regs->gusbcfg, usbcfg.d32); -+ -+ /* This programming sequence needs to happen in FS mode before any other -+ * programming occurs */ -+ /* High speed PHY. */ -+ if (!_core_if->phy_init_done) -+ { -+ _core_if->phy_init_done = 1; -+ /* HS PHY parameters. These parameters are preserved -+ * during soft reset so only program the first time. Do -+ * a soft reset immediately after setting phyif. */ -+ usbcfg.b.ulpi_utmi_sel = 0; //UTMI+ -+ usbcfg.b.phyif = ( _core_if->params.phy_utmi_width == 16)?1:0; -+ ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32); -+ /* Reset after setting the PHY parameters */ -+ ifxusb_core_soft_reset( _core_if ); -+ } -+ -+ usbcfg.d32 = ifxusb_rreg(&global_regs->gusbcfg); -+// usbcfg.b.ulpi_fsls = 0; -+// usbcfg.b.ulpi_clk_sus_m = 0; -+ ifxusb_wreg(&global_regs->gusbcfg, usbcfg.d32); -+ -+ /* Program the GAHBCFG Register.*/ -+ switch (_core_if->params.dma_burst_size) -+ { -+ case 0 : -+ ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_SINGLE; -+ break; -+ case 1 : -+ ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR; -+ break; -+ case 4 : -+ ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR4; -+ break; -+ case 8 : -+ ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR8; -+ break; -+ case 16: -+ ahbcfg.b.hburstlen = IFXUSB_GAHBCFG_INT_DMA_BURST_INCR16; -+ break; -+ } -+ ahbcfg.b.dmaenable = 1; -+ ifxusb_wreg(&global_regs->gahbcfg, ahbcfg.d32); -+ -+ /* Program the GUSBCFG register. */ -+ usbcfg.d32 = ifxusb_rreg( &global_regs->gusbcfg ); -+ usbcfg.b.hnpcap = 0; -+ usbcfg.b.srpcap = 0; -+ ifxusb_wreg( &global_regs->gusbcfg, usbcfg.d32); -+ -+ /* Restart the Phy Clock */ -+ ifxusb_wreg(_core_if->pcgcctl, 0); -+ -+ /* Initialize Host Configuration Register */ -+ { -+ hcfg_data_t hcfg; -+ hcfg.d32 = ifxusb_rreg(&_core_if->host_global_regs->hcfg); -+ hcfg.b.fslspclksel = IFXUSB_HCFG_30_60_MHZ; -+ if (_params->speed == IFXUSB_PARAM_SPEED_FULL) -+ hcfg.b.fslssupp = 1; -+ ifxusb_wreg(&_core_if->host_global_regs->hcfg, hcfg.d32); -+ } -+ -+ _core_if->params.host_channels=(_core_if->hwcfg2.b.num_host_chan + 1); -+ -+ if(_params->host_channels>0 && _params->host_channels < _core_if->params.host_channels) -+ _core_if->params.host_channels = _params->host_channels; -+ -+ /* Configure data FIFO sizes */ -+ _core_if->params.data_fifo_size = _core_if->hwcfg3.b.dfifo_depth; -+ _core_if->params.rx_fifo_size = ifxusb_rreg(&global_regs->grxfsiz); -+ _core_if->params.nperio_tx_fifo_size= ifxusb_rreg(&global_regs->gnptxfsiz) >> 16; -+ _core_if->params.perio_tx_fifo_size = ifxusb_rreg(&global_regs->hptxfsiz) >> 16; -+ IFX_DEBUGPL(DBG_CIL, "Initial: FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size); -+ IFX_DEBUGPL(DBG_CIL, " Rx FIFO Size=0x%06X\n", _core_if->params.rx_fifo_size); -+ IFX_DEBUGPL(DBG_CIL, " NPTx FIFO Size=0x%06X\n", _core_if->params.nperio_tx_fifo_size); -+ IFX_DEBUGPL(DBG_CIL, " PTx FIFO Size=0x%06X\n", _core_if->params.perio_tx_fifo_size); -+ -+ { -+ fifosize_data_t txfifosize; -+ if(_params->data_fifo_size >=0 && _params->data_fifo_size < _core_if->params.data_fifo_size) -+ _core_if->params.data_fifo_size = _params->data_fifo_size; -+ -+ if( _params->rx_fifo_size >= 0 && _params->rx_fifo_size < _core_if->params.rx_fifo_size) -+ _core_if->params.rx_fifo_size = _params->rx_fifo_size; -+ if( _params->nperio_tx_fifo_size >=0 && _params->nperio_tx_fifo_size < _core_if->params.nperio_tx_fifo_size) -+ _core_if->params.nperio_tx_fifo_size = _params->nperio_tx_fifo_size; -+ if( _params->perio_tx_fifo_size >=0 && _params->perio_tx_fifo_size < _core_if->params.perio_tx_fifo_size) -+ _core_if->params.perio_tx_fifo_size = _params->perio_tx_fifo_size; -+ -+ if(_core_if->params.data_fifo_size < _core_if->params.rx_fifo_size) -+ _core_if->params.rx_fifo_size = _core_if->params.data_fifo_size; -+ ifxusb_wreg( &global_regs->grxfsiz, _core_if->params.rx_fifo_size); -+ txfifosize.b.startaddr = _core_if->params.rx_fifo_size; -+ -+ if(txfifosize.b.startaddr + _core_if->params.nperio_tx_fifo_size > _core_if->params.data_fifo_size) -+ _core_if->params.nperio_tx_fifo_size = _core_if->params.data_fifo_size - txfifosize.b.startaddr; -+ txfifosize.b.depth=_core_if->params.nperio_tx_fifo_size; -+ ifxusb_wreg( &global_regs->gnptxfsiz, txfifosize.d32); -+ txfifosize.b.startaddr += _core_if->params.nperio_tx_fifo_size; -+ -+ if(txfifosize.b.startaddr + _core_if->params.perio_tx_fifo_size > _core_if->params.data_fifo_size) -+ _core_if->params.perio_tx_fifo_size = _core_if->params.data_fifo_size - txfifosize.b.startaddr; -+ txfifosize.b.depth=_core_if->params.perio_tx_fifo_size; -+ ifxusb_wreg( &global_regs->hptxfsiz, txfifosize.d32); -+ txfifosize.b.startaddr += _core_if->params.perio_tx_fifo_size; -+ } -+ -+ #ifdef __DEBUG__ -+ { -+ fifosize_data_t fifosize; -+ IFX_DEBUGPL(DBG_CIL, "Result : FIFO Size=0x%06X\n" , _core_if->params.data_fifo_size); -+ -+ fifosize.d32=ifxusb_rreg(&global_regs->grxfsiz); -+ IFX_DEBUGPL(DBG_CIL, " Rx FIFO =0x%06X 0x%06X\n", fifosize.b.startaddr,fifosize.b.depth); -+ fifosize.d32=ifxusb_rreg(&global_regs->gnptxfsiz); -+ IFX_DEBUGPL(DBG_CIL, " NPTx FIFO =0x%06X 0x%06X\n", fifosize.b.startaddr,fifosize.b.depth); -+ fifosize.d32=ifxusb_rreg(&global_regs->hptxfsiz); -+ IFX_DEBUGPL(DBG_CIL, " PTx FIFO =0x%06X 0x%06X\n", fifosize.b.startaddr,fifosize.b.depth); -+ } -+ #endif -+ -+ /* Clear Host Set HNP Enable in the OTG Control Register */ -+ gotgctl.b.hstsethnpen = 1; -+ ifxusb_mreg( &global_regs->gotgctl, gotgctl.d32, 0); -+ -+ /* Flush the FIFOs */ -+ ifxusb_flush_tx_fifo(_core_if, 0x10); /* all Tx FIFOs */ -+ ifxusb_flush_rx_fifo(_core_if); -+ -+ for (i = 0; i < _core_if->hwcfg2.b.num_host_chan + 1; i++) -+ { -+ hcchar_data_t hcchar; -+ hcchar.d32 = ifxusb_rreg(&_core_if->hc_regs[i]->hcchar); -+ hcchar.b.chen = 0; -+ hcchar.b.chdis = 1; -+ hcchar.b.epdir = 0; -+ ifxusb_wreg(&_core_if->hc_regs[i]->hcchar, hcchar.d32); -+ } -+ /* Halt all channels to put them into a known state. */ -+ for (i = 0; i < _core_if->hwcfg2.b.num_host_chan + 1; i++) -+ { -+ hcchar_data_t hcchar; -+ int count = 0; -+ -+ hcchar.d32 = ifxusb_rreg(&_core_if->hc_regs[i]->hcchar); -+ hcchar.b.chen = 1; -+ hcchar.b.chdis = 1; -+ hcchar.b.epdir = 0; -+ ifxusb_wreg(&_core_if->hc_regs[i]->hcchar, hcchar.d32); -+ -+ IFX_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i); -+ do{ -+ hcchar.d32 = ifxusb_rreg(&_core_if->hc_regs[i]->hcchar); -+ if (++count > 1000) -+ { -+ IFX_ERROR("%s: Unable to clear halt on channel %d\n", __func__, i); -+ break; -+ } -+ } while (hcchar.b.chen); -+ } -+} -+ -+////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+#if defined(__UEIP__) -+ #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS) -+ int ifxusb_vbus_status =-1; -+ #endif -+ -+ #if defined(IFX_GPIO_USB_VBUS1) || defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1) -+ int ifxusb_vbus1_status =-1; -+ #endif -+ -+ #if defined(IFX_GPIO_USB_VBUS2) || defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2) -+ int ifxusb_vbus2_status =-1; -+ #endif -+ -+ #if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS) -+ static void *g_usb_vbus_trigger = NULL; -+ #endif -+ #if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1) -+ static void *g_usb_vbus1_trigger = NULL; -+ #endif -+ #if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2) -+ static void *g_usb_vbus2_trigger = NULL; -+ #endif -+ -+ #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) -+ int ifxusb_vbus_gpio_inited=0; -+ #endif -+ -+#else //defined(__UEIP__) -+ int ifxusb_vbus_gpio_inited=0; -+#endif -+ -+////////////////////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+void ifxusb_vbus_init(ifxusb_core_if_t *_core_if) -+{ -+ #if defined(__UEIP__) -+ #if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS) -+ if ( !g_usb_vbus_trigger ) -+ { -+ ifx_led_trigger_register("USB_VBUS", &g_usb_vbus_trigger); -+ if ( g_usb_vbus_trigger != NULL ) -+ { -+ struct ifx_led_trigger_attrib attrib = {0}; -+ attrib.delay_on = 0; -+ attrib.delay_off = 0; -+ attrib.timeout = 0; -+ attrib.def_value = 0; -+ attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE; -+ IFX_DEBUGP("Reg USB power!!\n"); -+ ifx_led_trigger_set_attrib(g_usb_vbus_trigger, &attrib); -+ ifxusb_vbus_status =0; -+ } -+ } -+ #endif -+ #if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1) -+ if(_core_if->core_no==0 && !g_usb_vbus1_trigger ) -+ { -+ ifx_led_trigger_register("USB_VBUS1", &g_usb_vbus1_trigger); -+ if ( g_usb_vbus1_trigger != NULL ) -+ { -+ struct ifx_led_trigger_attrib attrib = {0}; -+ attrib.delay_on = 0; -+ attrib.delay_off = 0; -+ attrib.timeout = 0; -+ attrib.def_value = 0; -+ attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE; -+ IFX_DEBUGP("Reg USB1 power!!\n"); -+ ifx_led_trigger_set_attrib(g_usb_vbus1_trigger, &attrib); -+ ifxusb_vbus1_status =0; -+ } -+ } -+ #endif -+ #if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2) -+ if(_core_if->core_no==1 && !g_usb_vbus2_trigger ) -+ { -+ ifx_led_trigger_register("USB_VBUS2", &g_usb_vbus2_trigger); -+ if ( g_usb_vbus2_trigger != NULL ) -+ { -+ struct ifx_led_trigger_attrib attrib = {0}; -+ attrib.delay_on = 0; -+ attrib.delay_off = 0; -+ attrib.timeout = 0; -+ attrib.def_value = 0; -+ attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE; -+ IFX_DEBUGP("Reg USB2 power!!\n"); -+ ifx_led_trigger_set_attrib(g_usb_vbus2_trigger, &attrib); -+ ifxusb_vbus2_status =0; -+ } -+ } -+ #endif -+ -+ #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) -+ /* == 20100712 AVM/WK use gpio_inited as bitmask == */ -+ if(ifxusb_vbus_gpio_inited == 0) -+ { -+ if(!ifx_gpio_register(IFX_GPIO_MODULE_USB)) -+ { -+ IFX_DEBUGP("Register USB VBus through GPIO OK!!\n"); -+ #ifdef IFX_GPIO_USB_VBUS -+ ifxusb_vbus_status =0; -+ #endif //IFX_GPIO_USB_VBUS -+ #ifdef IFX_GPIO_USB_VBUS1 -+ ifxusb_vbus1_status=0; -+ #endif //IFX_GPIO_USB_VBUS1 -+ #ifdef IFX_GPIO_USB_VBUS2 -+ ifxusb_vbus2_status=0; -+ #endif //IFX_GPIO_USB_VBUS2 -+ ifxusb_vbus_gpio_inited|= (1<<_core_if->core_no); -+ } -+ else -+ IFX_PRINT("Register USB VBus Failed!!\n"); -+ } else { -+ ifxusb_vbus_gpio_inited|= (1<<_core_if->core_no); -+ } -+ #endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) -+ #endif //defined(__UEIP__) -+} -+ -+void ifxusb_vbus_free(ifxusb_core_if_t *_core_if) -+{ -+ #if defined(__UEIP__) -+ #if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS) -+ if ( g_usb_vbus_trigger ) -+ { -+ ifx_led_trigger_deregister(g_usb_vbus_trigger); -+ g_usb_vbus_trigger = NULL; -+ ifxusb_vbus_status =-1; -+ } -+ #endif -+ #if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1) -+ if(_core_if->core_no==0 && g_usb_vbus1_trigger ) -+ { -+ ifx_led_trigger_deregister(g_usb_vbus1_trigger); -+ g_usb_vbus1_trigger = NULL; -+ ifxusb_vbus1_status =-1; -+ } -+ #endif -+ #if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2) -+ if(_core_if->core_no==1 && g_usb_vbus2_trigger ) -+ { -+ ifx_led_trigger_deregister(g_usb_vbus2_trigger); -+ g_usb_vbus2_trigger = NULL; -+ ifxusb_vbus2_status =-1; -+ } -+ #endif -+ -+ #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) -+ /* == 20100712 AVM/WK use gpio_inited as bitmask == */ -+ if((ifxusb_vbus_gpio_inited & (1<<_core_if->core_no)) == ifxusb_vbus_gpio_inited) -+ { -+ ifx_gpio_deregister(IFX_GPIO_MODULE_USB); -+ #ifdef IFX_GPIO_USB_VBUS -+ ifxusb_vbus_status =-1; -+ #endif //IFX_GPIO_USB_VBUS -+ #ifdef IFX_GPIO_USB_VBUS1 -+ ifxusb_vbus1_status=-1; -+ #endif //IFX_GPIO_USB_VBUS1 -+ #ifdef IFX_GPIO_USB_VBUS2 -+ ifxusb_vbus2_status=-1; -+ #endif //IFX_GPIO_USB_VBUS2 -+ } -+ ifxusb_vbus_gpio_inited &= ~(1<<_core_if->core_no); -+ #endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) -+ #endif //defined(__UEIP__) -+} -+ -+ -+/*! -+ \brief Turn on the USB 5V VBus Power -+ \param _core_if Pointer of core_if structure -+ */ -+void ifxusb_vbus_on(ifxusb_core_if_t *_core_if) -+{ -+ IFX_DEBUGP("SENDING VBus POWER UP\n"); -+ #if defined(__UEIP__) -+ #if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS) -+ if ( g_usb_vbus_trigger && ifxusb_vbus_status==0) -+ { -+ ifx_led_trigger_activate(g_usb_vbus_trigger); -+ IFX_DEBUGP("Enable USB power!!\n"); -+ ifxusb_vbus_status=1; -+ } -+ #endif -+ #if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1) -+ if(_core_if->core_no==0 && g_usb_vbus1_trigger && ifxusb_vbus1_status==0) -+ { -+ ifx_led_trigger_activate(g_usb_vbus1_trigger); -+ IFX_DEBUGP("Enable USB1 power!!\n"); -+ ifxusb_vbus1_status=1; -+ } -+ #endif -+ #if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2) -+ if(_core_if->core_no==1 && g_usb_vbus2_trigger && ifxusb_vbus2_status==0) -+ { -+ ifx_led_trigger_activate(g_usb_vbus2_trigger); -+ IFX_DEBUGP("Enable USB2 power!!\n"); -+ ifxusb_vbus2_status=1; -+ } -+ #endif -+ -+ #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) -+ if(ifxusb_vbus_gpio_inited) -+ { -+ #if defined(IFX_GPIO_USB_VBUS) -+ if(ifxusb_vbus_status==0) -+ { -+ ifx_gpio_output_set(IFX_GPIO_USB_VBUS,IFX_GPIO_MODULE_USB); -+ ifxusb_vbus_status=1; -+ } -+ #endif -+ #if defined(IFX_GPIO_USB_VBUS1) -+ if(_core_if->core_no==0 && ifxusb_vbus1_status==0) -+ { -+ ifx_gpio_output_set(IFX_GPIO_USB_VBUS1,IFX_GPIO_MODULE_USB); -+ ifxusb_vbus1_status=1; -+ } -+ #endif -+ #if defined(IFX_GPIO_USB_VBUS2) -+ if(_core_if->core_no==1 && ifxusb_vbus2_status==0) -+ { -+ ifx_gpio_output_set(IFX_GPIO_USB_VBUS2,IFX_GPIO_MODULE_USB); -+ ifxusb_vbus2_status=1; -+ } -+ #endif -+ } -+ #endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) -+ #else -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ ifxusb_vbus_status=1; -+ //usb_set_vbus_on(); -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined(__IS_AMAZON_SE__) -+ set_bit (4, (volatile unsigned long *)AMAZON_SE_GPIO_P0_OUT); -+ ifxusb_vbus_status=1; -+ #endif //defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) -+ if(_core_if->core_no==0) -+ { -+ if (bsp_port_reserve_pin(1, 13, PORT_MODULE_USB) != 0) -+ { -+ IFX_PRINT("Can't enable USB1 5.5V power!!\n"); -+ return; -+ } -+ bsp_port_clear_altsel0(1, 13, PORT_MODULE_USB); -+ bsp_port_clear_altsel1(1, 13, PORT_MODULE_USB); -+ bsp_port_set_dir_out(1, 13, PORT_MODULE_USB); -+ bsp_port_set_pudsel(1, 13, PORT_MODULE_USB); -+ bsp_port_set_puden(1, 13, PORT_MODULE_USB); -+ bsp_port_set_output(1, 13, PORT_MODULE_USB); -+ IFX_DEBUGP("Enable USB1 power!!\n"); -+ ifxusb_vbus1_status=1; -+ } -+ else -+ { -+ if (bsp_port_reserve_pin(3, 4, PORT_MODULE_USB) != 0) -+ { -+ IFX_PRINT("Can't enable USB2 5.5V power!!\n"); -+ return; -+ } -+ bsp_port_clear_altsel0(3, 4, PORT_MODULE_USB); -+ bsp_port_clear_altsel1(3, 4, PORT_MODULE_USB); -+ bsp_port_set_dir_out(3, 4, PORT_MODULE_USB); -+ bsp_port_set_pudsel(3, 4, PORT_MODULE_USB); -+ bsp_port_set_puden(3, 4, PORT_MODULE_USB); -+ bsp_port_set_output(3, 4, PORT_MODULE_USB); -+ IFX_DEBUGP("Enable USB2 power!!\n"); -+ ifxusb_vbus2_status=1; -+ } -+ #endif //defined(__IS_AR9__) -+ #if defined(__IS_VR9__) -+ if(_core_if->core_no==0) -+ { -+ ifxusb_vbus1_status=1; -+ } -+ else -+ { -+ ifxusb_vbus2_status=1; -+ } -+ #endif //defined(__IS_VR9__) -+ #endif //defined(__UEIP__) -+} -+ -+ -+/*! -+ \brief Turn off the USB 5V VBus Power -+ \param _core_if Pointer of core_if structure -+ */ -+void ifxusb_vbus_off(ifxusb_core_if_t *_core_if) -+{ -+ IFX_DEBUGP("SENDING VBus POWER OFF\n"); -+ -+ #if defined(__UEIP__) -+ #if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS) -+ if ( g_usb_vbus_trigger && ifxusb_vbus_status==1) -+ { -+ ifx_led_trigger_deactivate(g_usb_vbus_trigger); -+ IFX_DEBUGP("Disable USB power!!\n"); -+ ifxusb_vbus_status=0; -+ } -+ #endif -+ #if defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1) -+ if(_core_if->core_no==0 && g_usb_vbus1_trigger && ifxusb_vbus1_status==1) -+ { -+ ifx_led_trigger_deactivate(g_usb_vbus1_trigger); -+ IFX_DEBUGP("Disable USB1 power!!\n"); -+ ifxusb_vbus1_status=0; -+ } -+ #endif -+ #if defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2) -+ if(_core_if->core_no==1 && g_usb_vbus2_trigger && ifxusb_vbus2_status==1) -+ { -+ ifx_led_trigger_deactivate(g_usb_vbus2_trigger); -+ IFX_DEBUGP("Disable USB2 power!!\n"); -+ ifxusb_vbus2_status=0; -+ } -+ #endif -+ -+ #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) -+ if(ifxusb_vbus_gpio_inited) -+ { -+ #if defined(IFX_GPIO_USB_VBUS) -+ if(ifxusb_vbus_status==1) -+ { -+ ifx_gpio_output_clear(IFX_GPIO_USB_VBUS,IFX_GPIO_MODULE_USB); -+ ifxusb_vbus_status=0; -+ } -+ #endif -+ #if defined(IFX_GPIO_USB_VBUS1) -+ if(_core_if->core_no==0 && ifxusb_vbus1_status==1) -+ { -+ ifx_gpio_output_clear(IFX_GPIO_USB_VBUS1,IFX_GPIO_MODULE_USB); -+ ifxusb_vbus1_status=0; -+ } -+ #endif -+ #if defined(IFX_GPIO_USB_VBUS2) -+ if(_core_if->core_no==1 && ifxusb_vbus2_status==1) -+ { -+ ifx_gpio_output_clear(IFX_GPIO_USB_VBUS2,IFX_GPIO_MODULE_USB); -+ ifxusb_vbus2_status=0; -+ } -+ #endif -+ } -+ #endif //defined(IFX_GPIO_USB_VBUS) || defined(IFX_GPIO_USB_VBUS1) || defined(IFX_GPIO_USB_VBUS2) -+ #else -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ ifxusb_vbus_status=0; -+ //usb_set_vbus_on(); -+ #endif //defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+ #if defined(__IS_AMAZON_SE__) -+ clear_bit (4, (volatile unsigned long *)AMAZON_SE_GPIO_P0_OUT); -+ ifxusb_vbus_status=0; -+ #endif //defined(__IS_AMAZON_SE__) -+ #if defined(__IS_AR9__) -+ if(_core_if->core_no==0) -+ { -+ if (bsp_port_reserve_pin(1, 13, PORT_MODULE_USB) != 0) { -+ IFX_PRINT("Can't Disable USB1 5.5V power!!\n"); -+ return; -+ } -+ bsp_port_clear_altsel0(1, 13, PORT_MODULE_USB); -+ bsp_port_clear_altsel1(1, 13, PORT_MODULE_USB); -+ bsp_port_set_dir_out(1, 13, PORT_MODULE_USB); -+ bsp_port_set_pudsel(1, 13, PORT_MODULE_USB); -+ bsp_port_set_puden(1, 13, PORT_MODULE_USB); -+ bsp_port_clear_output(1, 13, PORT_MODULE_USB); -+ IFX_DEBUGP("Disable USB1 power!!\n"); -+ ifxusb_vbus1_status=0; -+ } -+ else -+ { -+ if (bsp_port_reserve_pin(3, 4, PORT_MODULE_USB) != 0) { -+ IFX_PRINT("Can't Disable USB2 5.5V power!!\n"); -+ return; -+ } -+ bsp_port_clear_altsel0(3, 4, PORT_MODULE_USB); -+ bsp_port_clear_altsel1(3, 4, PORT_MODULE_USB); -+ bsp_port_set_dir_out(3, 4, PORT_MODULE_USB); -+ bsp_port_set_pudsel(3, 4, PORT_MODULE_USB); -+ bsp_port_set_puden(3, 4, PORT_MODULE_USB); -+ bsp_port_clear_output(3, 4, PORT_MODULE_USB); -+ IFX_DEBUGP("Disable USB2 power!!\n"); -+ -+ ifxusb_vbus2_status=0; -+ } -+ #endif //defined(__IS_AR9__) -+ #if defined(__IS_VR9__) -+ if(_core_if->core_no==0) -+ { -+ ifxusb_vbus1_status=0; -+ } -+ else -+ { -+ ifxusb_vbus2_status=0; -+ } -+ #endif //defined(__IS_VR9__) -+ #endif //defined(__UEIP__) -+} -+ -+ -+ -+/*! -+ \brief Read Current VBus status -+ \param _core_if Pointer of core_if structure -+ */ -+int ifxusb_vbus(ifxusb_core_if_t *_core_if) -+{ -+#if defined(__UEIP__) -+ #if defined(IFX_GPIO_USB_VBUS) || defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDLED_USB_VBUS) -+ return (ifxusb_vbus_status); -+ #endif -+ -+ #if defined(IFX_GPIO_USB_VBUS1) || defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDLED_USB_VBUS1) -+ if(_core_if->core_no==0) -+ return (ifxusb_vbus1_status); -+ #endif -+ -+ #if defined(IFX_GPIO_USB_VBUS2) || defined(IFX_LEDGPIO_USB_VBUS2) || defined(IFX_LEDLED_USB_VBUS2) -+ if(_core_if->core_no==1) -+ return (ifxusb_vbus2_status); -+ #endif -+#else //defined(__UEIP__) -+#endif -+ return -1; -+} -+ -+#if defined(__UEIP__) -+#else -+ #if defined(__IS_TWINPASS__) -+ #define ADSL_BASE 0x20000 -+ #define CRI_BASE 0x31F00 -+ #define CRI_CCR0 CRI_BASE + 0x00 -+ #define CRI_CCR1 CRI_BASE + 0x01*4 -+ #define CRI_CDC0 CRI_BASE + 0x02*4 -+ #define CRI_CDC1 CRI_BASE + 0x03*4 -+ #define CRI_RST CRI_BASE + 0x04*4 -+ #define CRI_MASK0 CRI_BASE + 0x05*4 -+ #define CRI_MASK1 CRI_BASE + 0x06*4 -+ #define CRI_MASK2 CRI_BASE + 0x07*4 -+ #define CRI_STATUS0 CRI_BASE + 0x08*4 -+ #define CRI_STATUS1 CRI_BASE + 0x09*4 -+ #define CRI_STATUS2 CRI_BASE + 0x0A*4 -+ #define CRI_AMASK0 CRI_BASE + 0x0B*4 -+ #define CRI_AMASK1 CRI_BASE + 0x0C*4 -+ #define CRI_UPDCTL CRI_BASE + 0x0D*4 -+ #define CRI_MADST CRI_BASE + 0x0E*4 -+ // 0x0f is missing -+ #define CRI_EVENT0 CRI_BASE + 0x10*4 -+ #define CRI_EVENT1 CRI_BASE + 0x11*4 -+ #define CRI_EVENT2 CRI_BASE + 0x12*4 -+ -+ #define IRI_I_ENABLE 0x32000 -+ #define STY_SMODE 0x3c004 -+ #define AFE_TCR_0 0x3c0dc -+ #define AFE_ADDR_ADDR 0x3c0e8 -+ #define AFE_RDATA_ADDR 0x3c0ec -+ #define AFE_WDATA_ADDR 0x3c0f0 -+ #define AFE_CONFIG 0x3c0f4 -+ #define AFE_SERIAL_CFG 0x3c0fc -+ -+ #define DFE_BASE_ADDR 0xBE116000 -+ //#define DFE_BASE_ADDR 0x9E116000 -+ -+ #define MEI_FR_ARCINT_C (DFE_BASE_ADDR + 0x0000001C) -+ #define MEI_DBG_WADDR_C (DFE_BASE_ADDR + 0x00000024) -+ #define MEI_DBG_RADDR_C (DFE_BASE_ADDR + 0x00000028) -+ #define MEI_DBG_DATA_C (DFE_BASE_ADDR + 0x0000002C) -+ #define MEI_DBG_DECO_C (DFE_BASE_ADDR + 0x00000030) -+ #define MEI_DBG_MASTER_C (DFE_BASE_ADDR + 0x0000003C) -+ -+ static void WriteARCmem(uint32_t addr, uint32_t data) -+ { -+ writel(1 ,(volatile uint32_t *)MEI_DBG_MASTER_C); -+ writel(1 ,(volatile uint32_t *)MEI_DBG_DECO_C ); -+ writel(addr ,(volatile uint32_t *)MEI_DBG_WADDR_C ); -+ writel(data ,(volatile uint32_t *)MEI_DBG_DATA_C ); -+ while( (ifxusb_rreg((volatile uint32_t *)MEI_FR_ARCINT_C) & 0x20) != 0x20 ){}; -+ writel(0 ,(volatile uint32_t *)MEI_DBG_MASTER_C); -+ IFX_DEBUGP("WriteARCmem %08x %08x\n",addr,data); -+ }; -+ -+ static uint32_t ReadARCmem(uint32_t addr) -+ { -+ u32 data; -+ writel(1 ,(volatile uint32_t *)MEI_DBG_MASTER_C); -+ writel(1 ,(volatile uint32_t *)MEI_DBG_DECO_C ); -+ writel(addr ,(volatile uint32_t *)MEI_DBG_RADDR_C ); -+ while( (ifxusb_rreg((volatile uint32_t *)MEI_FR_ARCINT_C) & 0x20) != 0x20 ){}; -+ data = ifxusb_rreg((volatile uint32_t *)MEI_DBG_DATA_C ); -+ writel(0 ,(volatile uint32_t *)MEI_DBG_MASTER_C); -+ IFX_DEBUGP("ReadARCmem %08x %08x\n",addr,data); -+ return data; -+ }; -+ -+ void ifxusb_enable_afe_oc(void) -+ { -+ /* Start the clock */ -+ WriteARCmem(CRI_UPDCTL ,0x00000008); -+ WriteARCmem(CRI_CCR0 ,0x00000014); -+ WriteARCmem(CRI_CCR1 ,0x00000500); -+ WriteARCmem(AFE_CONFIG ,0x000001c8); -+ WriteARCmem(AFE_SERIAL_CFG,0x00000016); // (DANUBE_PCI_CFG_BASE+(1< -+#include "ifxusb_version.h" -+ -+ -+#include -+#include -+#include -+#include -+ -+#include "ifxusb_plat.h" -+#include "ifxusb_regs.h" -+#include "ifxusb_cif.h" -+ -+#ifdef __IS_DEVICE__ -+ #include "ifxpcd.h" -+#endif -+ -+#ifdef __IS_HOST__ -+ #include "ifxhcd.h" -+#endif -+ -+#include -+#include -+#include -+ -+ -+#ifdef __IS_HOST__ -+ extern char ifxusb_driver_name[]; -+ -+ #ifdef __IS_DUAL__ -+ extern ifxhcd_hcd_t ifxusb_hcd_1; -+ extern ifxhcd_hcd_t ifxusb_hcd_2; -+ extern char ifxusb_hcd_name_1[]; -+ extern char ifxusb_hcd_name_2[]; -+ #else -+ extern ifxhcd_hcd_t ifxusb_hcd; -+ extern char ifxusb_hcd_name[]; -+ #endif -+ -+#endif -+ -+#ifdef __IS_DEVICE__ -+ extern char ifxusb_driver_name[]; -+ -+ extern ifxpcd_pcd_t ifxusb_pcd; -+ extern char ifxusb_pcd_name[]; -+#endif -+ -+ -+//Attributes for sysfs (for 2.6 only) -+ -+extern struct device_attribute dev_attr_dbglevel; -+ -+#ifdef __IS_DUAL__ -+ extern struct device_attribute dev_attr_dump_params_1; -+ extern struct device_attribute dev_attr_dump_params_2; -+#else -+ extern struct device_attribute dev_attr_dump_params; -+#endif -+ -+#ifdef __IS_DUAL__ -+ extern struct device_attribute dev_attr_mode_1; -+ extern struct device_attribute dev_attr_mode_2; -+#else -+ extern struct device_attribute dev_attr_mode; -+#endif -+ -+#ifdef __IS_HOST__ -+ #ifdef __IS_DUAL__ -+ extern struct device_attribute dev_attr_buspower_1; -+ extern struct device_attribute dev_attr_buspower_2; -+ extern struct device_attribute dev_attr_bussuspend_1; -+ extern struct device_attribute dev_attr_bussuspend_2; -+ extern struct device_attribute dev_attr_busconnected_1; -+ extern struct device_attribute dev_attr_busconnected_2; -+ extern struct device_attribute dev_attr_connectspeed_1; -+ extern struct device_attribute dev_attr_connectspeed_1; -+ #else -+ extern struct device_attribute dev_attr_buspower; -+ extern struct device_attribute dev_attr_bussuspend; -+ extern struct device_attribute dev_attr_busconnected; -+ extern struct device_attribute dev_attr_connectspeed; -+ #endif -+#endif //__IS_HOST__ -+ -+#ifdef __IS_DEVICE__ -+ extern struct device_attribute dev_attr_devspeed; -+ extern struct device_attribute dev_attr_enumspeed; -+#endif //__IS_DEVICE__ -+ -+#ifdef __ENABLE_DUMP__ -+ #ifdef __IS_DUAL__ -+ extern struct device_attribute dev_attr_dump_reg_1; -+ extern struct device_attribute dev_attr_dump_reg_2; -+ extern struct device_attribute dev_attr_dump_spram_1; -+ extern struct device_attribute dev_attr_dump_spram_2; -+ #ifdef __IS_HOST__ -+ extern struct device_attribute dev_attr_dump_host_state_1; -+ extern struct device_attribute dev_attr_dump_host_state_2; -+ #else -+ #endif -+ #else -+ extern struct device_attribute dev_attr_dump_reg; -+ extern struct device_attribute dev_attr_dump_spram; -+ #ifdef __IS_HOST__ -+ extern struct device_attribute dev_attr_dump_host_state; -+ #else -+ #endif -+ #endif -+#endif //__ENABLE_DUMP__ -+ -+ -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+static ssize_t procfs_dbglevel_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+{ -+ #ifdef __IS_HOST__ -+ return sprintf( buf, "%08X\n",h_dbg_lvl ); -+ #else -+ return sprintf( buf, "%08X\n",d_dbg_lvl ); -+ #endif -+} -+ -+static ssize_t procfs_dbglevel_store(struct file *file, const char *buffer, unsigned long count, void *data) -+{ -+ char buf[10]; -+ int i = 0; -+ uint32_t value; -+ if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1)) -+ return -EFAULT; -+ value = simple_strtoul(buf, NULL, 16); -+ #ifdef __IS_HOST__ -+ h_dbg_lvl =value; -+ #else -+ d_dbg_lvl =value; -+ #endif -+ //turn on and off power -+ return count; -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_dbglevel_show( struct device *_dev, struct device_attribute *attr,char *buf) -+#else -+ static ssize_t sysfs_dbglevel_show( struct device *_dev, char *buf) -+#endif -+{ -+ #ifdef __IS_HOST__ -+ return sprintf( buf, "%08X\n",h_dbg_lvl ); -+ #else -+ return sprintf( buf, "%08X\n",d_dbg_lvl ); -+ #endif -+} -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_dbglevel_store( struct device *_dev, struct device_attribute *attr,const char *buffer, size_t count ) -+#else -+ static ssize_t sysfs_dbglevel_store( struct device *_dev, const char *buffer, size_t count ) -+#endif -+{ -+ char buf[10]; -+ int i = 0; -+ uint32_t value; -+ if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1)) -+ return -EFAULT; -+ value = simple_strtoul(buf, NULL, 16); -+ #ifdef __IS_HOST__ -+ h_dbg_lvl =value; -+ #else -+ d_dbg_lvl =value; -+ #endif -+ //turn on and off power -+ return count; -+} -+ -+DEVICE_ATTR(dbglevel, S_IRUGO|S_IWUSR, sysfs_dbglevel_show, sysfs_dbglevel_store); -+ -+ -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+static void ifxusb_dump_params(ifxusb_core_if_t *_core_if); -+ -+#ifdef __IS_DUAL__ -+ static void dump_params_1(void) -+ { -+ ifxusb_dump_params(&ifxusb_hcd_1.core_if); -+ } -+ static void dump_params_2(void) -+ { -+ ifxusb_dump_params(&ifxusb_hcd_2.core_if); -+ } -+ -+ static ssize_t procfs_dump_params_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ dump_params_1(); -+ return 0; -+ } -+ static ssize_t procfs_dump_params_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ dump_params_2(); -+ return 0; -+ } -+ -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_dump_params_show_1( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_dump_params_show_1( struct device *_dev,char *buf) -+ #endif -+ { -+ dump_params_1(); -+ return 0; -+ } -+ DEVICE_ATTR(dump_params_1, S_IRUGO|S_IWUSR, sysfs_dump_params_show_1, NULL); -+ -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_dump_params_show_2( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_dump_params_show_2( struct device *_dev,char *buf) -+ #endif -+ { -+ dump_params_2(); -+ return 0; -+ } -+ -+ DEVICE_ATTR(dump_params_2, S_IRUGO|S_IWUSR, sysfs_dump_params_show_2, NULL); -+#else -+ static void dump_params(void) -+ { -+ #ifdef __IS_HOST__ -+ ifxusb_dump_params(&ifxusb_hcd.core_if); -+ #else -+ ifxusb_dump_params(&ifxusb_pcd.core_if); -+ #endif -+ } -+ -+ static ssize_t procfs_dump_params_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ dump_params(); -+ return 0; -+ } -+ -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_dump_params_show( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_dump_params_show( struct device *_dev,char *buf) -+ #endif -+ { -+ dump_params(); -+ return 0; -+ } -+ DEVICE_ATTR(dump_params, S_IRUGO|S_IWUSR, sysfs_dump_params_show, NULL); -+#endif -+ -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+#ifdef __IS_DUAL__ -+ static ssize_t mode_show_1(char *buf) -+ { -+ if((ifxusb_rreg(&ifxusb_hcd_1.core_if.core_global_regs->gintsts ) & 0x1) == 1) -+ return sprintf( buf, "HOST\n" ); -+ else -+ return sprintf( buf, "DEVICE(INCORRECT!)\n" ); -+ } -+ -+ static ssize_t mode_show_2(char *buf) -+ { -+ if((ifxusb_rreg(&ifxusb_hcd_2.core_if.core_global_regs->gintsts ) & 0x1) == 1) -+ return sprintf( buf, "HOST\n" ); -+ else -+ return sprintf( buf, "DEVICE(INCORRECT!)\n" ); -+ } -+ -+ static ssize_t procfs_mode_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ return mode_show_1(buf); -+ } -+ static ssize_t procfs_mode_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ return mode_show_2(buf); -+ } -+ -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_mode_show_1( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_mode_show_1( struct device *_dev,char *buf) -+ #endif -+ { -+ return mode_show_1(buf); -+ } -+ -+ DEVICE_ATTR(mode_1, S_IRUGO|S_IWUSR, sysfs_mode_show_1, 0); -+ -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_mode_show_2( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_mode_show_2( struct device *_dev,char *buf) -+ #endif -+ { -+ return mode_show_2(buf); -+ } -+ DEVICE_ATTR(mode_2, S_IRUGO|S_IWUSR, sysfs_mode_show_2, NULL); -+#else -+ static ssize_t mode_show(char *buf) -+ { -+ #ifdef __IS_HOST__ -+ if((ifxusb_rreg(&ifxusb_hcd.core_if.core_global_regs->gintsts ) & 0x1) == 1) -+ return sprintf( buf, "HOST\n" ); -+ else -+ return sprintf( buf, "DEVICE(INCORRECT!)\n" ); -+ #else -+ if((ifxusb_rreg(&ifxusb_pcd.core_if.core_global_regs->gintsts ) & 0x1) != 1) -+ return sprintf( buf, "DEVICE\n" ); -+ else -+ return sprintf( buf, "HOST(INCORRECT!)\n" ); -+ #endif -+ } -+ static ssize_t procfs_mode_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ return mode_show(buf); -+ } -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_mode_show( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_mode_show( struct device *_dev, char *buf) -+ #endif -+ { -+ return mode_show(buf); -+ } -+ DEVICE_ATTR(mode, S_IRUGO|S_IWUSR, sysfs_mode_show, NULL); -+#endif -+ -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+#ifdef __IS_HOST__ -+ #ifdef __IS_DUAL__ -+ static ssize_t buspower_show_1(char *buf) -+ { -+ if(ifxusb_vbus (&ifxusb_hcd_1.core_if)==1) return sprintf( buf, "1\n" ); -+ if(ifxusb_vbus (&ifxusb_hcd_1.core_if)==0) return sprintf( buf, "0\n" ); -+ return sprintf( buf, "UNKNOWN\n" ); -+ } -+ static void buspower_store_1(uint32_t value) -+ { -+ if (value==1) ifxusb_vbus_on (&ifxusb_hcd_1.core_if); -+ else if(value==0) ifxusb_vbus_off(&ifxusb_hcd_1.core_if); -+ } -+ static ssize_t buspower_show_2(char *buf) -+ { -+ if(ifxusb_vbus (&ifxusb_hcd_2.core_if)==1) return sprintf( buf, "1\n" ); -+ if(ifxusb_vbus (&ifxusb_hcd_2.core_if)==0) return sprintf( buf, "0\n" ); -+ return sprintf( buf, "UNKNOWN\n" ); -+ } -+ static void buspower_store_2(uint32_t value) -+ { -+ if (value==1) ifxusb_vbus_on (&ifxusb_hcd_2.core_if); -+ else if(value==0) ifxusb_vbus_off(&ifxusb_hcd_2.core_if); -+ } -+ static ssize_t procfs_buspower_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ return buspower_show_1(buf); -+ } -+ static ssize_t procfs_buspower_store_1(struct file *file, const char *buffer, unsigned long count, void *data) -+ { -+ char buf[10]; -+ int i = 0; -+ uint32_t value; -+ if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1)) -+ return -EFAULT; -+ value = simple_strtoul(buf, NULL, 16); -+ buspower_store_1(value); -+ return count; -+ } -+ static ssize_t procfs_buspower_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ return buspower_show_2(buf); -+ } -+ static ssize_t procfs_buspower_store_2(struct file *file, const char *buffer, unsigned long count, void *data) -+ { -+ char buf[10]; -+ int i = 0; -+ uint32_t value; -+ if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1)) -+ return -EFAULT; -+ value = simple_strtoul(buf, NULL, 16); -+ buspower_store_2(value); -+ return count; -+ } -+ -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_buspower_show_1( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_buspower_show_1( struct device *_dev,char *buf) -+ #endif -+ { -+ return buspower_show_1(buf); -+ } -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_buspower_store_1( struct device *_dev, struct device_attribute *attr,const char *buffer, size_t count ) -+ #else -+ static ssize_t sysfs_buspower_store_1( struct device *_dev, const char *buffer, size_t count ) -+ #endif -+ { -+ char buf[10]; -+ int i = 0; -+ uint32_t value; -+ if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1)) -+ return -EFAULT; -+ value = simple_strtoul(buf, NULL, 16); -+ buspower_store_1(value); -+ return count; -+ } -+ DEVICE_ATTR(buspower_1, S_IRUGO|S_IWUSR, sysfs_buspower_show_1, sysfs_buspower_store_1); -+ -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_buspower_show_2( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_buspower_show_2( struct device *_dev,char *buf) -+ #endif -+ { -+ return buspower_show_2(buf); -+ } -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_buspower_store_2( struct device *_dev, struct device_attribute *attr,const char *buffer, size_t count ) -+ #else -+ static ssize_t sysfs_buspower_store_2( struct device *_dev, const char *buffer, size_t count ) -+ #endif -+ { -+ char buf[10]; -+ int i = 0; -+ uint32_t value; -+ if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1)) -+ return -EFAULT; -+ value = simple_strtoul(buf, NULL, 16); -+ buspower_store_2(value); -+ return count; -+ } -+ DEVICE_ATTR(buspower_2, S_IRUGO|S_IWUSR, sysfs_buspower_show_2, sysfs_buspower_store_2); -+ #else -+ static ssize_t buspower_show(char *buf) -+ { -+ if(ifxusb_vbus (&ifxusb_hcd.core_if)==1) return sprintf( buf, "1\n" ); -+ if(ifxusb_vbus (&ifxusb_hcd.core_if)==0) return sprintf( buf, "0\n" ); -+ return sprintf( buf, "UNKNOWN\n" ); -+ } -+ static void buspower_store(uint32_t value) -+ { -+ if (value==1) ifxusb_vbus_on (&ifxusb_hcd.core_if); -+ else if(value==0) ifxusb_vbus_off(&ifxusb_hcd.core_if); -+ } -+ static ssize_t procfs_buspower_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ return buspower_show(buf); -+ } -+ static ssize_t procfs_buspower_store(struct file *file, const char *buffer, unsigned long count, void *data) -+ { -+ char buf[10]; -+ int i = 0; -+ uint32_t value; -+ if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1)) -+ return -EFAULT; -+ value = simple_strtoul(buf, NULL, 16); -+ buspower_store(value); -+ return count; -+ } -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_buspower_show( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_buspower_show( struct device *_dev, char *buf) -+ #endif -+ { -+ return buspower_show(buf); -+ } -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_buspower_store( struct device *_dev, struct device_attribute *attr,const char *buffer, size_t count ) -+ #else -+ static ssize_t sysfs_buspower_store( struct device *_dev, const char *buffer, size_t count ) -+ #endif -+ { -+ char buf[10]; -+ int i = 0; -+ uint32_t value; -+ if (copy_from_user(buf, &buffer[i], sizeof("0xFFFFFFFF\n")+1)) -+ return -EFAULT; -+ value = simple_strtoul(buf, NULL, 16); -+ buspower_store(value); -+ return count; -+ } -+ DEVICE_ATTR(buspower, S_IRUGO|S_IWUSR, sysfs_buspower_show, sysfs_buspower_store); -+ #endif -+ -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+ -+ #ifdef __IS_DUAL__ -+ static ssize_t bussuspend_show_1(char *buf) -+ { -+ hprt0_data_t val; -+ val.d32 = ifxusb_rreg(ifxusb_hcd_1.core_if.hprt0); -+ return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp); -+ } -+ static ssize_t bussuspend_show_2(char *buf) -+ { -+ hprt0_data_t val; -+ val.d32 = ifxusb_rreg(ifxusb_hcd_2.core_if.hprt0); -+ return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp); -+ } -+ -+ static ssize_t procfs_bussuspend_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ return bussuspend_show_1(buf); -+ } -+ static ssize_t procfs_bussuspend_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ return bussuspend_show_2(buf); -+ } -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_bussuspend_show_1( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_bussuspend_show_1( struct device *_dev,char *buf) -+ #endif -+ { -+ return bussuspend_show_1(buf); -+ } -+ DEVICE_ATTR(bussuspend_1, S_IRUGO|S_IWUSR, sysfs_bussuspend_show_1, 0); -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_bussuspend_show_2( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_bussuspend_show_2( struct device *_dev,char *buf) -+ #endif -+ { -+ return bussuspend_show_2(buf); -+ } -+ DEVICE_ATTR(bussuspend_2, S_IRUGO|S_IWUSR, sysfs_bussuspend_show_2, 0); -+ #else -+ static ssize_t bussuspend_show(char *buf) -+ { -+ hprt0_data_t val; -+ val.d32 = ifxusb_rreg(ifxusb_hcd.core_if.hprt0); -+ return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp); -+ } -+ static ssize_t procfs_bussuspend_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ return bussuspend_show(buf); -+ } -+ -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_bussuspend_show( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_bussuspend_show( struct device *_dev, char *buf) -+ #endif -+ { -+ return bussuspend_show(buf); -+ } -+ DEVICE_ATTR(bussuspend, S_IRUGO|S_IWUSR, sysfs_bussuspend_show, 0); -+ #endif -+ -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+ #ifdef __IS_DUAL__ -+ static ssize_t busconnected_show_1(char *buf) -+ { -+ hprt0_data_t val; -+ val.d32 = ifxusb_rreg(ifxusb_hcd_1.core_if.hprt0); -+ return sprintf (buf, "Bus Connected = 0x%x\n", val.b.prtconnsts); -+ } -+ static ssize_t busconnected_show_2(char *buf) -+ { -+ hprt0_data_t val; -+ val.d32 = ifxusb_rreg(ifxusb_hcd_2.core_if.hprt0); -+ return sprintf (buf, "Bus Connected = 0x%x\n", val.b.prtconnsts); -+ } -+ -+ static ssize_t procfs_busconnected_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ return busconnected_show_1(buf); -+ } -+ static ssize_t procfs_busconnected_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ return busconnected_show_2(buf); -+ } -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_busconnected_show_1( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_busconnected_show_1( struct device *_dev,char *buf) -+ #endif -+ { -+ return busconnected_show_1(buf); -+ } -+ DEVICE_ATTR(busconnected_1, S_IRUGO|S_IWUSR, sysfs_busconnected_show_1, 0); -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_busconnected_show_2( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_busconnected_show_2( struct device *_dev,char *buf) -+ #endif -+ { -+ return busconnected_show_2(buf); -+ } -+ DEVICE_ATTR(busconnected_2, S_IRUGO|S_IWUSR, sysfs_busconnected_show_2, 0); -+ #else -+ static ssize_t busconnected_show(char *buf) -+ { -+ hprt0_data_t val; -+ val.d32 = ifxusb_rreg(ifxusb_hcd.core_if.hprt0); -+ return sprintf (buf, "Bus Connected = 0x%x\n", val.b.prtconnsts); -+ } -+ static ssize_t procfs_busconnected_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ return busconnected_show(buf); -+ } -+ -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_busconnected_show( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_busconnected_show( struct device *_dev, char *buf) -+ #endif -+ { -+ return busconnected_show(buf); -+ } -+ DEVICE_ATTR(busconnected, S_IRUGO|S_IWUSR, sysfs_busconnected_show, 0); -+ #endif -+ -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+ #ifdef __IS_DUAL__ -+ static ssize_t connectspeed_show_1(char *buf) -+ { -+ hprt0_data_t val; -+ val.d32 = ifxusb_rreg(ifxusb_hcd_1.core_if.hprt0); -+ if( val.b.prtspd ==0) return sprintf (buf, "Bus Speed = High (%d)\n", val.b.prtspd); -+ if( val.b.prtspd ==1) return sprintf (buf, "Bus Speed = Full (%d)\n", val.b.prtspd); -+ if( val.b.prtspd ==2) return sprintf (buf, "Bus Speed = Low (%d)\n", val.b.prtspd); -+ return sprintf (buf, "Bus Speed = Unknown (%d)\n", val.b.prtspd); -+ } -+ static ssize_t connectspeed_show_2(char *buf) -+ { -+ hprt0_data_t val; -+ val.d32 = ifxusb_rreg(ifxusb_hcd_2.core_if.hprt0); -+ if( val.b.prtspd ==0) return sprintf (buf, "Bus Speed = High (%d)\n", val.b.prtspd); -+ if( val.b.prtspd ==1) return sprintf (buf, "Bus Speed = Full (%d)\n", val.b.prtspd); -+ if( val.b.prtspd ==2) return sprintf (buf, "Bus Speed = Low (%d)\n", val.b.prtspd); -+ return sprintf (buf, "Bus Speed = Unknown (%d)\n", val.b.prtspd); -+ } -+ -+ static ssize_t procfs_connectspeed_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ return connectspeed_show_1(buf); -+ } -+ static ssize_t procfs_connectspeed_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ return connectspeed_show_2(buf); -+ } -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_connectspeed_show_1( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_connectspeed_show_1( struct device *_dev,char *buf) -+ #endif -+ { -+ return connectspeed_show_1(buf); -+ } -+ DEVICE_ATTR(connectspeed_1, S_IRUGO|S_IWUSR, sysfs_connectspeed_show_1, 0); -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_connectspeed_show_2( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_connectspeed_show_2( struct device *_dev,char *buf) -+ #endif -+ { -+ return connectspeed_show_2(buf); -+ } -+ DEVICE_ATTR(connectspeed_2, S_IRUGO|S_IWUSR, sysfs_connectspeed_show_2, 0); -+ #else -+ static ssize_t connectspeed_show(char *buf) -+ { -+ hprt0_data_t val; -+ val.d32 = ifxusb_rreg(ifxusb_hcd.core_if.hprt0); -+ if( val.b.prtspd ==0) return sprintf (buf, "Bus Speed = High (%d)\n", val.b.prtspd); -+ if( val.b.prtspd ==1) return sprintf (buf, "Bus Speed = Full (%d)\n", val.b.prtspd); -+ if( val.b.prtspd ==2) return sprintf (buf, "Bus Speed = Low (%d)\n", val.b.prtspd); -+ return sprintf (buf, "Bus Speed = Unknown (%d)\n", val.b.prtspd); -+ } -+ -+ static ssize_t procfs_connectspeed_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ return connectspeed_show(buf); -+ } -+ -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_connectspeed_show( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_connectspeed_show( struct device *_dev, char *buf) -+ #endif -+ { -+ return connectspeed_show(buf); -+ } -+ DEVICE_ATTR(connectspeed, S_IRUGO|S_IWUSR, sysfs_connectspeed_show, 0); -+ #endif -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+#endif -+ -+ -+#ifdef __IS_DEVICE__ -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+ static ssize_t devspeed_show(char *buf) -+ { -+ dcfg_data_t val; -+ val.d32 = ifxusb_rreg(&ifxusb_pcd.core_if.dev_global_regs->dcfg); -+ if( val.b.devspd ==0) return sprintf (buf, "Dev Speed = High (%d)\n", val.b.devspd); -+ if( val.b.devspd ==1) return sprintf (buf, "Dev Speed = Full (%d)\n", val.b.devspd); -+ if( val.b.devspd ==3) return sprintf (buf, "Dev Speed = Full (%d)\n", val.b.devspd); -+ return sprintf (buf, "Dev Speed = Unknown (%d)\n", val.b.devspd); -+ } -+ -+ static ssize_t procfs_devspeed_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ return devspeed_show(buf); -+ } -+ -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_devspeed_show( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_devspeed_show( struct device *_dev, char *buf) -+ #endif -+ { -+ return devspeed_show(buf); -+ } -+ DEVICE_ATTR(devspeed, S_IRUGO|S_IWUSR, sysfs_devspeed_show, 0); -+ -+ static ssize_t enumspeed_show(char *buf) -+ { -+ dsts_data_t val; -+ val.d32 = ifxusb_rreg(&ifxusb_pcd.core_if.dev_global_regs->dsts); -+ if( val.b.enumspd ==0) return sprintf (buf, "Enum Speed = High (%d)\n", val.b.enumspd); -+ if( val.b.enumspd ==1) return sprintf (buf, "Enum Speed = Full (%d)\n", val.b.enumspd); -+ if( val.b.enumspd ==2) return sprintf (buf, "Enum Speed = Low (%d)\n", val.b.enumspd); -+ return sprintf (buf, "Enum Speed = invalid(%d)\n", val.b.enumspd); -+ } -+ -+ static ssize_t procfs_enumspeed_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ return enumspeed_show(buf); -+ } -+ -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_enumspeed_show( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_enumspeed_show( struct device *_dev, char *buf) -+ #endif -+ { -+ return enumspeed_show(buf); -+ } -+ DEVICE_ATTR(enumspeed, S_IRUGO|S_IWUSR, sysfs_enumspeed_show, 0); -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+#endif -+ -+ -+////////////////////////////////////////////////////////////////////////////////// -+#ifdef __ENABLE_DUMP__ -+ -+ #ifdef __IS_DUAL__ -+ static void dump_reg_1(void) -+ { -+ ifxusb_dump_registers(&ifxusb_hcd_1.core_if); -+ } -+ static void dump_reg_2(void) -+ { -+ ifxusb_dump_registers(&ifxusb_hcd_2.core_if); -+ } -+ -+ static ssize_t procfs_dump_reg_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ dump_reg_1(); -+ return 0; -+ } -+ static ssize_t procfs_dump_reg_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ dump_reg_2(); -+ return 0; -+ } -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_dump_reg_show_1( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_dump_reg_show_1( struct device *_dev,char *buf) -+ #endif -+ { -+ dump_reg_1(); -+ return 0; -+ } -+ DEVICE_ATTR(dump_reg_1, S_IRUGO|S_IWUSR, sysfs_dump_reg_show_1, 0); -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_dump_reg_show_2( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_dump_reg_show_2( struct device *_dev,char *buf) -+ #endif -+ { -+ dump_reg_2(); -+ return 0; -+ } -+ DEVICE_ATTR(dump_reg_2, S_IRUGO|S_IWUSR, sysfs_dump_reg_show_2, 0); -+ #else -+ static void dump_reg(void) -+ { -+ #ifdef __IS_HOST__ -+ ifxusb_dump_registers(&ifxusb_hcd.core_if); -+ #endif -+ #ifdef __IS_DEVICE__ -+ ifxusb_dump_registers(&ifxusb_pcd.core_if); -+ #endif -+ } -+ static ssize_t procfs_dump_reg_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ dump_reg(); -+ return 0; -+ } -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_dump_reg_show( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_dump_reg_show( struct device *_dev,char *buf) -+ #endif -+ { -+ dump_reg(); -+ return 0; -+ } -+ DEVICE_ATTR(dump_reg, S_IRUGO|S_IWUSR, sysfs_dump_reg_show, 0); -+ #endif -+ -+ -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+ #ifdef __IS_DUAL__ -+ static void dump_spram_1(void) -+ { -+ ifxusb_dump_spram(&ifxusb_hcd_1.core_if); -+ } -+ static void dump_spram_2(void) -+ { -+ ifxusb_dump_spram(&ifxusb_hcd_2.core_if); -+ } -+ -+ static ssize_t procfs_dump_spram_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ dump_spram_1(); -+ return 0; -+ } -+ static ssize_t procfs_dump_spram_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ dump_spram_2(); -+ return 0; -+ } -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_dump_spram_show_1( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_dump_spram_show_1( struct device *_dev,char *buf) -+ #endif -+ { -+ dump_spram_1(); -+ return 0; -+ } -+ DEVICE_ATTR(dump_spram_1, S_IRUGO|S_IWUSR, sysfs_dump_spram_show_1, 0); -+ -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_dump_spram_show_2( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_dump_spram_show_2( struct device *_dev,char *buf) -+ #endif -+ { -+ dump_spram_2(); -+ return 0; -+ } -+ DEVICE_ATTR(dump_spram_2, S_IRUGO|S_IWUSR, sysfs_dump_spram_show_2, 0); -+ #else -+ static void dump_spram(void) -+ { -+ #ifdef __IS_HOST__ -+ ifxusb_dump_spram(&ifxusb_hcd.core_if); -+ #endif -+ #ifdef __IS_DEVICE__ -+ ifxusb_dump_spram(&ifxusb_pcd.core_if); -+ #endif -+ } -+ static ssize_t procfs_dump_spram_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ dump_spram(); -+ return 0; -+ } -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_dump_spram_show( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_dump_spram_show( struct device *_dev,char *buf) -+ #endif -+ { -+ dump_spram(); -+ return 0; -+ } -+ DEVICE_ATTR(dump_spram, S_IRUGO|S_IWUSR, sysfs_dump_spram_show, 0); -+ #endif -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+ #ifdef __IS_HOST__ -+ #ifdef __IS_DUAL__ -+ static ssize_t procfs_dump_host_state_show_1(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ ifxhcd_dump_state(&ifxusb_hcd_1); -+ return 0; -+ } -+ static ssize_t procfs_dump_host_state_show_2(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ ifxhcd_dump_state(&ifxusb_hcd_2); -+ return 0; -+ } -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_dump_host_state_show_1( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_dump_host_state_show_1( struct device *_dev,char *buf) -+ #endif -+ { -+ ifxhcd_dump_state(&ifxusb_hcd_1); -+ return 0; -+ } -+ DEVICE_ATTR(dump_host_state_1, S_IRUGO|S_IWUSR, sysfs_dump_host_state_show_1, 0); -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_dump_host_state_show_2( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_dump_host_state_show_2( struct device *_dev,char *buf) -+ #endif -+ { -+ ifxhcd_dump_state(&ifxusb_hcd_2); -+ return 0; -+ } -+ DEVICE_ATTR(dump_host_state_2, S_IRUGO|S_IWUSR, sysfs_dump_host_state_show_2, 0); -+ #else -+ static ssize_t procfs_dump_host_state_show(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+ { -+ ifxhcd_dump_state(&ifxusb_hcd); -+ return 0; -+ } -+ #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ static ssize_t sysfs_dump_host_state_show( struct device *_dev, struct device_attribute *attr,char *buf) -+ #else -+ static ssize_t sysfs_dump_host_state_show( struct device *_dev,char *buf) -+ #endif -+ { -+ ifxhcd_dump_state(&ifxusb_hcd); -+ return 0; -+ } -+ DEVICE_ATTR(dump_host_state, S_IRUGO|S_IWUSR, sysfs_dump_host_state_show, 0); -+ #endif -+ -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+///////////////////////////////////////////////////////////////////////////////////////////////////// -+ -+ #endif //IS_HOST_ -+ -+#endif //__ENABLE_DUMP__ -+ -+////////////////////////////////////////////////////////////////////////////////// -+ -+static int ifx_proc_addproc(char *funcname, read_proc_t *hookfuncr, write_proc_t *hookfuncw); -+static void ifx_proc_delproc(char *funcname); -+ -+////////////////////////////////////////////////////////////////////////////////// -+ -+/*! -+ \brief This function create the sysfs and procfs entries -+ \param[in] _dev Pointer of device structure, if applied -+ */ -+void ifxusb_attr_create (void *_dev) -+{ -+ int error; -+ -+ struct device *dev = (struct device *) _dev; -+ -+ IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); -+ error = ifx_proc_addproc("dbglevel", procfs_dbglevel_show, procfs_dbglevel_store); -+ error = device_create_file(dev, &dev_attr_dbglevel); -+ -+ #ifdef __IS_DUAL__ -+ error = ifx_proc_addproc("dump_params_1", procfs_dump_params_show_1, NULL); -+ error = ifx_proc_addproc("dump_params_2", procfs_dump_params_show_2, NULL); -+ error = device_create_file(dev, &dev_attr_dump_params_1); -+ error = device_create_file(dev, &dev_attr_dump_params_2); -+ #else -+ error = ifx_proc_addproc("dump_params", procfs_dump_params_show, NULL); -+ error = device_create_file(dev, &dev_attr_dump_params); -+ #endif -+ -+ #ifdef __IS_DUAL__ -+ error = ifx_proc_addproc("mode_1", procfs_mode_show_1, NULL); -+ error = ifx_proc_addproc("mode_2", procfs_mode_show_2, NULL); -+ error = device_create_file(dev, &dev_attr_mode_1); -+ error = device_create_file(dev, &dev_attr_mode_2); -+ #else -+ error = ifx_proc_addproc("mode", procfs_mode_show, NULL); -+ error = device_create_file(dev, &dev_attr_mode); -+ #endif -+ -+ #ifdef __IS_HOST__ -+ #ifdef __IS_DUAL__ -+ error = ifx_proc_addproc("buspower_1", procfs_buspower_show_1, procfs_buspower_store_1); -+ error = ifx_proc_addproc("buspower_2", procfs_buspower_show_2, procfs_buspower_store_2); -+ error = device_create_file(dev, &dev_attr_buspower_1); -+ error = device_create_file(dev, &dev_attr_buspower_2); -+ #else -+ error = ifx_proc_addproc("buspower", procfs_buspower_show, procfs_buspower_store); -+ error = device_create_file(dev, &dev_attr_buspower); -+ #endif -+ -+ #ifdef __IS_DUAL__ -+ error = ifx_proc_addproc("bussuspend_1", procfs_bussuspend_show_1, NULL); -+ error = ifx_proc_addproc("bussuspend_2", procfs_bussuspend_show_2, NULL); -+ error = device_create_file(dev, &dev_attr_bussuspend_1); -+ error = device_create_file(dev, &dev_attr_bussuspend_2); -+ #else -+ error = ifx_proc_addproc("bussuspend", procfs_bussuspend_show, NULL); -+ error = device_create_file(dev, &dev_attr_bussuspend); -+ #endif -+ -+ #ifdef __IS_DUAL__ -+ error = ifx_proc_addproc("busconnected_1", procfs_busconnected_show_1, NULL); -+ error = ifx_proc_addproc("busconnected_2", procfs_busconnected_show_2, NULL); -+ error = device_create_file(dev, &dev_attr_busconnected_1); -+ error = device_create_file(dev, &dev_attr_busconnected_2); -+ #else -+ error = ifx_proc_addproc("busconnected", procfs_busconnected_show, NULL); -+ error = device_create_file(dev, &dev_attr_busconnected); -+ #endif -+ -+ #ifdef __IS_DUAL__ -+ error = ifx_proc_addproc("connectspeed_1", procfs_connectspeed_show_1, NULL); -+ error = ifx_proc_addproc("connectspeed_2", procfs_connectspeed_show_2, NULL); -+ error = device_create_file(dev, &dev_attr_connectspeed_1); -+ error = device_create_file(dev, &dev_attr_connectspeed_2); -+ #else -+ error = ifx_proc_addproc("connectspeed", procfs_connectspeed_show, NULL); -+ error = device_create_file(dev, &dev_attr_connectspeed); -+ #endif -+ #endif -+ -+ #ifdef __IS_DEVICE__ -+ error = ifx_proc_addproc("devspeed", procfs_devspeed_show, NULL); -+ error = device_create_file(dev, &dev_attr_devspeed); -+ error = ifx_proc_addproc("enumspeed", procfs_enumspeed_show, NULL); -+ error = device_create_file(dev, &dev_attr_enumspeed); -+ #endif -+ -+ ////////////////////////////////////////////////////// -+ #ifdef __ENABLE_DUMP__ -+ #ifdef __IS_DUAL__ -+ error = ifx_proc_addproc("dump_reg_1", procfs_dump_reg_show_1, NULL); -+ error = ifx_proc_addproc("dump_reg_2", procfs_dump_reg_show_2, NULL); -+ error = device_create_file(dev, &dev_attr_dump_reg_1); -+ error = device_create_file(dev, &dev_attr_dump_reg_2); -+ #else -+ error = ifx_proc_addproc("dump_reg", procfs_dump_reg_show, NULL); -+ error = device_create_file(dev, &dev_attr_dump_reg); -+ #endif -+ -+ #ifdef __IS_DUAL__ -+ error = ifx_proc_addproc("dump_spram_1", procfs_dump_spram_show_1, NULL); -+ error = ifx_proc_addproc("dump_spram_2", procfs_dump_spram_show_2, NULL); -+ error = device_create_file(dev, &dev_attr_dump_spram_1); -+ error = device_create_file(dev, &dev_attr_dump_spram_2); -+ #else -+ error = ifx_proc_addproc("dump_spram", procfs_dump_spram_show, NULL); -+ error = device_create_file(dev, &dev_attr_dump_spram); -+ #endif -+ -+ #ifdef __IS_HOST__ -+ #ifdef __IS_DUAL__ -+ error = ifx_proc_addproc("dump_host_state_1", procfs_dump_host_state_show_1, NULL); -+ error = ifx_proc_addproc("dump_host_state_2", procfs_dump_host_state_show_2, NULL); -+ error = device_create_file(dev, &dev_attr_dump_host_state_1); -+ error = device_create_file(dev, &dev_attr_dump_host_state_2); -+ #else -+ error = ifx_proc_addproc("dump_host_state", procfs_dump_host_state_show, NULL); -+ error = device_create_file(dev, &dev_attr_dump_host_state); -+ #endif -+ #endif -+ #endif //__ENABLE_DUMP__ -+ ////////////////////////////////////////////////////// -+} -+ -+ -+/*! -+ \brief This function remove the sysfs and procfs entries -+ \param[in] _dev Pointer of device structure, if applied -+ */ -+void ifxusb_attr_remove (void *_dev) -+{ -+ struct device *dev = (struct device *) _dev; -+ -+ IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); -+ ifx_proc_delproc("dbglevel"); -+ device_remove_file(dev, &dev_attr_dbglevel); -+ -+ #ifdef __IS_DUAL__ -+ ifx_proc_delproc("dump_params_1"); -+ ifx_proc_delproc("dump_params_2"); -+ device_remove_file(dev, &dev_attr_dump_params_1); -+ device_remove_file(dev, &dev_attr_dump_params_2); -+ #else -+ ifx_proc_delproc("dump_params"); -+ device_remove_file(dev, &dev_attr_dump_params); -+ #endif -+ -+ #ifdef __IS_DUAL__ -+ ifx_proc_delproc("mode_1"); -+ ifx_proc_delproc("mode_2"); -+ device_remove_file(dev, &dev_attr_mode_1); -+ device_remove_file(dev, &dev_attr_mode_2); -+ #else -+ ifx_proc_delproc("mode"); -+ device_remove_file(dev, &dev_attr_mode); -+ #endif -+ -+ #ifdef __IS_HOST__ -+ #ifdef __IS_DUAL__ -+ ifx_proc_delproc("buspower_1"); -+ ifx_proc_delproc("buspower_2"); -+ device_remove_file(dev, &dev_attr_buspower_1); -+ device_remove_file(dev, &dev_attr_buspower_2); -+ #else -+ ifx_proc_delproc("buspower"); -+ device_remove_file(dev, &dev_attr_buspower); -+ #endif -+ -+ #ifdef __IS_DUAL__ -+ ifx_proc_delproc("bussuspend_1"); -+ ifx_proc_delproc("bussuspend_2"); -+ device_remove_file(dev, &dev_attr_bussuspend_1); -+ device_remove_file(dev, &dev_attr_bussuspend_2); -+ #else -+ ifx_proc_delproc("bussuspend"); -+ device_remove_file(dev, &dev_attr_bussuspend); -+ #endif -+ -+ #ifdef __IS_DUAL__ -+ ifx_proc_delproc("busconnected_1"); -+ ifx_proc_delproc("busconnected_2"); -+ device_remove_file(dev, &dev_attr_busconnected_1); -+ device_remove_file(dev, &dev_attr_busconnected_2); -+ #else -+ ifx_proc_delproc("busconnected"); -+ device_remove_file(dev, &dev_attr_busconnected); -+ #endif -+ -+ #ifdef __IS_DUAL__ -+ ifx_proc_delproc("connectspeed_1"); -+ ifx_proc_delproc("connectspeed_2"); -+ device_remove_file(dev, &dev_attr_connectspeed_1); -+ device_remove_file(dev, &dev_attr_connectspeed_2); -+ #else -+ ifx_proc_delproc("connectspeed"); -+ device_remove_file(dev, &dev_attr_connectspeed); -+ #endif -+ #endif -+ -+ #ifdef __IS_DEVICE__ -+ ifx_proc_delproc("devspeed"); -+ device_remove_file(dev, &dev_attr_devspeed); -+ ifx_proc_delproc("enumspeed"); -+ device_remove_file(dev, &dev_attr_enumspeed); -+ #endif -+ -+ #ifdef __ENABLE_DUMP__ -+ #ifdef __IS_DUAL__ -+ ifx_proc_delproc("dump_reg_1"); -+ ifx_proc_delproc("dump_reg_2"); -+ device_remove_file(dev, &dev_attr_dump_reg_1); -+ device_remove_file(dev, &dev_attr_dump_reg_2); -+ #else -+ ifx_proc_delproc("dump_reg"); -+ device_remove_file(dev, &dev_attr_dump_reg); -+ #endif -+ -+ #ifdef __IS_DUAL__ -+ ifx_proc_delproc("dump_spram_1"); -+ ifx_proc_delproc("dump_spram_2"); -+ device_remove_file(dev, &dev_attr_dump_spram_1); -+ device_remove_file(dev, &dev_attr_dump_spram_2); -+ #else -+ ifx_proc_delproc("dump_spram"); -+ device_remove_file(dev, &dev_attr_dump_spram); -+ #endif -+ -+ #ifdef __IS_HOST__ -+ #ifdef __IS_DUAL__ -+ ifx_proc_delproc("dump_host_state_1"); -+ ifx_proc_delproc("dump_host_state_2"); -+ device_remove_file(dev, &dev_attr_dump_host_state_1); -+ device_remove_file(dev, &dev_attr_dump_host_state_2); -+ #else -+ ifx_proc_delproc("dump_host_state"); -+ device_remove_file(dev, &dev_attr_dump_host_state); -+ #endif -+ #endif -+ #endif //__ENABLE_DUMP__ -+ /* AVM/WK fix: del IFXUSB root dir*/ -+ ifx_proc_delproc(NULL); -+} -+ -+static struct proc_dir_entry * proc_ifx_root = NULL; -+ -+/* initialize the proc file system and make a dir named /proc/[name] */ -+static void ifx_proc_init(void) -+{ -+ IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); -+ proc_ifx_root = proc_mkdir(ifxusb_driver_name, (void *)0); -+ if (!proc_ifx_root){ -+ IFX_PRINT("%s proc initialization failed! \n", ifxusb_driver_name); -+ return; -+ } -+} -+ -+/* proc file system add function for debugging. */ -+static int ifx_proc_addproc(char *funcname, read_proc_t *hookfuncr, write_proc_t *hookfuncw) -+{ -+ struct proc_dir_entry *pe; -+ IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); -+ if (!proc_ifx_root) -+ ifx_proc_init(); -+ -+ if (hookfuncw == NULL) -+ { -+ pe = create_proc_read_entry(funcname, S_IRUGO, proc_ifx_root, hookfuncr, NULL); -+ if (!pe) -+ { -+ IFX_PRINT("ERROR in creating read proc entry (%s)! \n", funcname); -+ return -1; -+ } -+ } -+ else -+ { -+ pe = create_proc_entry(funcname, S_IRUGO | S_IWUGO, proc_ifx_root); -+ if (pe) -+ { -+ pe->read_proc = hookfuncr; -+ pe->write_proc = hookfuncw; -+ } -+ else -+ { -+ IFX_PRINT("ERROR in creating proc entry (%s)! \n", funcname); -+ return -1; -+ } -+ } -+ return 0; -+} -+ -+ -+/* proc file system del function for removing module. */ -+static void ifx_proc_delproc(char *funcname) -+{ -+/* AVM/WK Fix*/ -+ if (funcname != NULL) { -+ remove_proc_entry(funcname, proc_ifx_root); -+ } else { -+ remove_proc_entry(ifxusb_driver_name, NULL); -+ proc_ifx_root = NULL; -+ } -+} -+ -+static void ifxusb_dump_params(ifxusb_core_if_t *_core_if) -+{ -+ ifxusb_params_t *params=&_core_if->params; -+ -+ #ifdef __IS_HOST__ -+ IFX_PRINT("IFXUSB Dump Parameters ( Host Mode) \n"); -+ #endif //__IS_HOST__ -+ #ifdef __IS_DEVICE__ -+ IFX_PRINT("IFXUSB Dump Parameters ( Device Mode) \n"); -+ #endif //__IS_DEVICE__ -+ -+ #ifdef __DESC_DMA__ -+ IFX_PRINT("DMA: Hermes DMA\n"); -+ #else -+ IFX_PRINT("DMA: Non-Desc DMA\n"); -+ #endif -+ IFX_PRINT(" Burst size: %d\n",params->dma_burst_size); -+ -+ if (params->speed==1) -+ IFX_PRINT("Full Speed only\n"); -+ else if(params->speed==0) -+ IFX_PRINT("Full/Hign Speed\n"); -+ else -+ IFX_PRINT("Unkonwn setting (%d) for Speed\n",params->speed); -+ -+ IFX_PRINT("Total Data FIFO size: %d(0x%06X) DWord, %d(0x%06X) Bytes\n", -+ params->data_fifo_size,params->data_fifo_size, -+ params->data_fifo_size*4, params->data_fifo_size*4 -+ ); -+ -+ #ifdef __IS_DEVICE__ -+ IFX_PRINT("Rx FIFO size: %d(0x%06X) DWord, %d(0x%06X) Bytes\n", -+ params->rx_fifo_size,params->rx_fifo_size, -+ params->rx_fifo_size*4, params->rx_fifo_size*4 -+ ); -+ { -+ int i; -+ for(i=0;itx_fifo_size[i],params->tx_fifo_size[i], -+ params->tx_fifo_size[i]*4, params->tx_fifo_size[i]*4 -+ ); -+ } -+ } -+ #ifdef __DED_FIFO__ -+ IFX_PRINT("Treshold : %s Rx:%d Tx:%d \n", -+ (params->thr_ctl)?"On":"Off",params->tx_thr_length,params->rx_thr_length); -+ #endif -+ #else //__IS_HOST__ -+ IFX_PRINT("Host Channels: %d\n",params->host_channels); -+ -+ IFX_PRINT("Rx FIFO size: %d(0x%06X) DWord, %d(0x%06X) Bytes\n", -+ params->data_fifo_size,params->data_fifo_size, -+ params->data_fifo_size*4, params->data_fifo_size*4 -+ ); -+ -+ IFX_PRINT("NP Tx FIFO size: %d(0x%06X) DWord, %d(0x%06X) Bytes\n", -+ params->nperio_tx_fifo_size,params->nperio_tx_fifo_size, -+ params->nperio_tx_fifo_size*4, params->nperio_tx_fifo_size*4 -+ ); -+ -+ IFX_PRINT(" P Tx FIFO size: %d(0x%06X) DWord, %d(0x%06X) Bytes\n", -+ params->perio_tx_fifo_size,params->perio_tx_fifo_size, -+ params->perio_tx_fifo_size*4, params->perio_tx_fifo_size*4 -+ ); -+ #endif //__IS_HOST__ -+ -+ IFX_PRINT("Max Transfer size: %d(0x%06X) Bytes\n", -+ params->max_transfer_size,params->max_transfer_size -+ ); -+ IFX_PRINT("Max Packet Count: %d(0x%06X)\n", -+ params->max_packet_count,params->max_packet_count -+ ); -+ -+ IFX_PRINT("PHY UTMI Width: %d\n",params->phy_utmi_width); -+ -+ IFX_PRINT("Turn Around Time: HS:%d FS:%d\n",params->turn_around_time_hs,params->turn_around_time_fs); -+ IFX_PRINT("Timeout Calibration: HS:%d FS:%d\n",params->timeout_cal_hs,params->timeout_cal_fs); -+ -+ -+ IFX_PRINT("==================================================\n"); -+ IFX_PRINT("End of Parameters Dump\n"); -+ IFX_PRINT("==================================================\n"); -+} -+ -+ ---- /dev/null -+++ b/drivers/usb/ifxhcd/ifxusb_driver.c -@@ -0,0 +1,970 @@ -+/***************************************************************************** -+ ** FILE NAME : ifxusb_driver.c -+ ** PROJECT : IFX USB sub-system V3 -+ ** MODULES : IFX USB sub-system Host and Device driver -+ ** SRC VERSION : 1.0 -+ ** DATE : 1/Jan/2009 -+ ** AUTHOR : Chen, Howard -+ ** DESCRIPTION : The provides the initialization and cleanup entry -+ ** points for the IFX USB driver. This module can be -+ ** dynamically loaded with insmod command or built-in -+ ** with kernel. When loaded or executed the ifxusb_driver_init -+ ** function is called. When the module is removed (using rmmod), -+ ** the ifxusb_driver_cleanup function is called. -+ *****************************************************************************/ -+ -+/*! -+ \file ifxusb_driver.c -+ \brief This file contains the loading/unloading interface to the Linux driver. -+*/ -+ -+#include -+#include "ifxusb_version.h" -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+#include -+#include /* permission constants */ -+#include -+#include -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) -+ #include -+#endif -+ -+#include -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) -+ #include -+#endif -+ -+#include "ifxusb_plat.h" -+ -+#include "ifxusb_cif.h" -+ -+#ifdef __IS_HOST__ -+ #include "ifxhcd.h" -+ -+ #define USB_DRIVER_DESC "IFX USB HCD driver" -+ const char ifxusb_driver_name[] = "ifxusb_hcd"; -+ -+ #ifdef __IS_DUAL__ -+ ifxhcd_hcd_t ifxusb_hcd_1; -+ ifxhcd_hcd_t ifxusb_hcd_2; -+ const char ifxusb_hcd_name_1[] = "ifxusb_hcd_1"; -+ const char ifxusb_hcd_name_2[] = "ifxusb_hcd_2"; -+ #else -+ ifxhcd_hcd_t ifxusb_hcd; -+ const char ifxusb_hcd_name[] = "ifxusb_hcd"; -+ #endif -+ -+ #if defined(__DO_OC_INT__) -+ static unsigned int oc_int_installed=0; -+ static ifxhcd_hcd_t *oc_int_id=NULL; -+ #endif -+#endif -+ -+#ifdef __IS_DEVICE__ -+ #include "ifxpcd.h" -+ -+ #define USB_DRIVER_DESC "IFX USB PCD driver" -+ const char ifxusb_driver_name[] = "ifxusb_pcd"; -+ -+ ifxpcd_pcd_t ifxusb_pcd; -+ const char ifxusb_pcd_name[] = "ifxusb_pcd"; -+#endif -+ -+/* Global Debug Level Mask. */ -+#ifdef __IS_HOST__ -+ uint32_t h_dbg_lvl = 0x00; -+#endif -+ -+#ifdef __IS_DEVICE__ -+ uint32_t d_dbg_lvl = 0x00; -+#endif -+ -+ifxusb_params_t ifxusb_module_params; -+ -+static void parse_parms(void); -+ -+ -+#include -+#define IFX_USB0_IR (INT_NUM_IM1_IRL0 + 22) -+#define IFX_USB1_IR (INT_NUM_IM2_IRL0 + 19) -+ -+/*! -+ \brief This function is called when a driver is unregistered. This happens when -+ the rmmod command is executed. The device may or may not be electrically -+ present. If it is present, the driver stops device processing. Any resources -+ used on behalf of this device are freed. -+*/ -+static int ifxusb_driver_remove(struct platform_device *_dev) -+{ -+ IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); -+ #ifdef __IS_HOST__ -+ #if defined(__DO_OC_INT__) -+ #if defined(__DO_OC_INT_ENABLE__) -+ ifxusb_oc_int_off(); -+ #endif -+ -+ if(oc_int_installed && oc_int_id) -+ free_irq((unsigned int)IFXUSB_OC_IRQ, oc_int_id ); -+ oc_int_installed=0; -+ oc_int_id=NULL; -+ #endif -+ -+ #if defined(__IS_DUAL__) -+ ifxhcd_remove(&ifxusb_hcd_1); -+ ifxusb_core_if_remove(&ifxusb_hcd_1.core_if ); -+ ifxhcd_remove(&ifxusb_hcd_2); -+ ifxusb_core_if_remove(&ifxusb_hcd_2.core_if ); -+ #else -+ ifxhcd_remove(&ifxusb_hcd); -+ ifxusb_core_if_remove(&ifxusb_hcd.core_if ); -+ #endif -+ #endif -+ -+ #ifdef __IS_DEVICE__ -+ ifxpcd_remove(); -+ ifxusb_core_if_remove(&ifxusb_pcd.core_if ); -+ #endif -+ -+ /* Remove the device attributes */ -+ -+ ifxusb_attr_remove(&_dev->dev); -+ -+ return 0; -+} -+ -+ -+/* Function to setup the structures to control one usb core running as host*/ -+#ifdef __IS_HOST__ -+/*! -+ \brief inlined by ifxusb_driver_probe(), handling host mode probing. Run at each host core. -+*/ -+ static inline int ifxusb_driver_probe_h(ifxhcd_hcd_t *_hcd, -+ int _irq, -+ uint32_t _iobase, -+ uint32_t _fifomem, -+ uint32_t _fifodbg -+ ) -+ { -+ int retval = 0; -+ -+ IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); -+ -+#ifdef __DEV_NEW__ -+ ifxusb_power_off (&_hcd->core_if); -+ ifxusb_phy_power_off (&_hcd->core_if); // Test -+ mdelay(500); -+#endif //__DEV_NEW__ -+ ifxusb_power_on (&_hcd->core_if); -+ mdelay(50); -+ ifxusb_phy_power_on (&_hcd->core_if); // Test -+ mdelay(50); -+ ifxusb_hard_reset(&_hcd->core_if); -+ retval =ifxusb_core_if_init(&_hcd->core_if, -+ _irq, -+ _iobase, -+ _fifomem, -+ _fifodbg); -+ if(retval) -+ return retval; -+ -+ ifxusb_host_core_init(&_hcd->core_if,&ifxusb_module_params); -+ -+ ifxusb_disable_global_interrupts( &_hcd->core_if); -+ -+ /* The driver is now initialized and need to be registered into Linux USB sub-system */ -+ -+ retval = ifxhcd_init(_hcd); // hook the hcd into usb ss -+ -+ if (retval != 0) -+ { -+ IFX_ERROR("_hcd_init failed\n"); -+ return retval; -+ } -+ -+ //ifxusb_enable_global_interrupts( _hcd->core_if ); // this should be done at hcd_start , including hcd_interrupt -+ return 0; -+ } -+#endif //__IS_HOST__ -+ -+#ifdef __IS_DEVICE__ -+/*! -+ \brief inlined by ifxusb_driver_probe(), handling device mode probing. -+*/ -+ static inline int ifxusb_driver_probe_d(ifxpcd_pcd_t *_pcd, -+ int _irq, -+ uint32_t _iobase, -+ uint32_t _fifomem, -+ uint32_t _fifodbg -+ ) -+ { -+ int retval = 0; -+ -+ IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); -+#ifdef __DEV_NEW__ -+ ifxusb_power_off (&_pcd->core_if); -+ ifxusb_phy_power_off (&_pcd->core_if); // Test -+ mdelay(500); -+#endif // __DEV_NEW__ -+ ifxusb_power_on (&_pcd->core_if); -+ mdelay(50); -+ ifxusb_phy_power_on (&_pcd->core_if); // Test -+ mdelay(50); -+ ifxusb_hard_reset(&_pcd->core_if); -+ retval =ifxusb_core_if_init(&_pcd->core_if, -+ _irq, -+ _iobase, -+ _fifomem, -+ _fifodbg); -+ if(retval) -+ return retval; -+ -+ IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); -+ ifxusb_dev_core_init(&_pcd->core_if,&ifxusb_module_params); -+ -+ IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); -+ ifxusb_disable_global_interrupts( &_pcd->core_if); -+ -+ /* The driver is now initialized and need to be registered into -+ Linux USB Gadget sub-system -+ */ -+ retval = ifxpcd_init(); -+ IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); -+ -+ if (retval != 0) -+ { -+ IFX_ERROR("_pcd_init failed\n"); -+ return retval; -+ } -+ //ifxusb_enable_global_interrupts( _pcd->core_if ); // this should be done at gadget bind or start -+ return 0; -+ } -+#endif //__IS_DEVICE__ -+ -+ -+ -+/*! -+ \brief This function is called by module management in 2.6 kernel or by ifxusb_driver_init with 2.4 kernel -+ It is to probe and setup IFXUSB core(s). -+*/ -+static int ifxusb_driver_probe(struct platform_device *_dev) -+{ -+ int retval = 0; -+ int *pins = _dev->dev.platform_data; -+ if (ltq_is_vr9()) { -+ gpio_request(6, "id1"); -+ gpio_request(9, "id2"); -+ gpio_direction_input(6); -+ gpio_direction_input(9); -+ } -+ if (pins) { -+ if (pins[0]) { -+ gpio_request(pins[0], "vbus1"); -+ gpio_direction_output(pins[0], 1); -+ } -+ if (pins[1] && ltq_is_vr9()) { -+ gpio_request(pins[1], "vbus2"); -+ gpio_direction_output(pins[1], 1); -+ } -+ } -+ // Parsing and store the parameters -+ IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); -+ parse_parms(); -+ -+ #ifdef __IS_HOST__ -+ #if defined(__IS_DUAL__) -+ memset(&ifxusb_hcd_1, 0, sizeof(ifxhcd_hcd_t)); -+ memset(&ifxusb_hcd_2, 0, sizeof(ifxhcd_hcd_t)); -+ -+ ifxusb_hcd_1.core_if.core_no=0; -+ ifxusb_hcd_2.core_if.core_no=1; -+ ifxusb_hcd_1.core_if.core_name=(char *)ifxusb_hcd_name_1; -+ ifxusb_hcd_2.core_if.core_name=(char *)ifxusb_hcd_name_2; -+ -+ ifxusb_hcd_1.dev=&_dev->dev; -+ ifxusb_hcd_2.dev=&_dev->dev; -+ -+ retval = ifxusb_driver_probe_h(&ifxusb_hcd_1, -+ IFX_USB0_IR, -+ IFXUSB1_IOMEM_BASE, -+ IFXUSB1_FIFOMEM_BASE, -+ IFXUSB1_FIFODBG_BASE -+ ); -+ if(retval) -+ goto ifxusb_driver_probe_fail; -+ -+ retval = ifxusb_driver_probe_h(&ifxusb_hcd_2, -+ IFX_USB1_IR, -+ IFXUSB2_IOMEM_BASE, -+ IFXUSB2_FIFOMEM_BASE, -+ IFXUSB2_FIFODBG_BASE -+ ); -+ if(retval) -+ goto ifxusb_driver_probe_fail; -+ -+ #elif defined(__IS_FIRST__) -+ memset(&ifxusb_hcd, 0, sizeof(ifxhcd_hcd_t)); -+ -+ ifxusb_hcd.core_if.core_no=0; -+ ifxusb_hcd.core_if.core_name=(char *)ifxusb_hcd_name; -+ -+ ifxusb_hcd.dev=&_dev->dev; -+ -+ retval = ifxusb_driver_probe_h(&ifxusb_hcd, -+ IFX_USB0_IR, -+ IFXUSB1_IOMEM_BASE, -+ IFXUSB1_FIFOMEM_BASE, -+ IFXUSB1_FIFODBG_BASE -+ ); -+ if(retval) -+ goto ifxusb_driver_probe_fail; -+ -+ #elif defined(__IS_SECOND__) -+ memset(&ifxusb_hcd, 0, sizeof(ifxhcd_hcd_t)); -+ -+ ifxusb_hcd.core_if.core_no=1; -+ ifxusb_hcd.core_if.core_name=(char *)ifxusb_hcd_name; -+ -+ ifxusb_hcd.dev=&_dev->dev; -+ -+ retval = ifxusb_driver_probe_h(&ifxusb_hcd, -+ IFX_USB1_IR, -+ IFXUSB2_IOMEM_BASE, -+ IFXUSB2_FIFOMEM_BASE, -+ IFXUSB2_FIFODBG_BASE -+ ); -+ if(retval) -+ goto ifxusb_driver_probe_fail; -+ -+ #else -+ memset(&ifxusb_hcd, 0, sizeof(ifxhcd_hcd_t)); -+ -+ ifxusb_hcd.core_if.core_no=0; -+ ifxusb_hcd.core_if.core_name=(char *)ifxusb_hcd_name; -+ -+ ifxusb_hcd.dev=&_dev->dev; -+ -+ retval = ifxusb_driver_probe_h(&ifxusb_hcd, -+ IFXUSB_IRQ, -+ IFXUSB_IOMEM_BASE, -+ IFXUSB_FIFOMEM_BASE, -+ IFXUSB_FIFODBG_BASE -+ ); -+ if(retval) -+ goto ifxusb_driver_probe_fail; -+ #endif -+ -+ #if defined(__DO_OC_INT__) -+ IFXUSB_DEBUGPL( DBG_CIL, "registering (overcurrent) handler for irq%d\n", IFXUSB_OC_IRQ); -+ #if defined(__IS_DUAL__) -+ request_irq((unsigned int)IFXUSB_OC_IRQ, &ifx_hcd_oc_irq, -+// SA_INTERRUPT|SA_SHIRQ, "ifxusb_oc", (void *)&ifxusb_hcd_1); -+ IRQF_DISABLED | IRQF_SHARED, "ifxusb_oc", (void *)&ifxusb_hcd_1); -+ oc_int_id=&ifxusb_hcd_1; -+ #else -+ request_irq((unsigned int)IFXUSB_OC_IRQ, &ifx_hcd_oc_irq, -+// SA_INTERRUPT|SA_SHIRQ, "ifxusb_oc", (void *)&ifxusb_hcd); -+ IRQF_DISABLED | IRQF_SHARED, "ifxusb_oc", (void *)&ifxusb_hcd); -+ oc_int_id=&ifxusb_hcd; -+ #endif -+ oc_int_installed=1; -+ -+ #if defined(__DO_OC_INT_ENABLE__) -+ ifxusb_oc_int_on(); -+ #endif -+ #endif -+ -+ #endif -+ -+ #ifdef __IS_DEVICE__ -+ memset(&ifxusb_pcd, 0, sizeof(ifxpcd_pcd_t)); -+ ifxusb_pcd.core_if.core_name=(char *)&ifxusb_pcd_name[0]; -+ -+ ifxusb_pcd.dev=&_dev->dev; -+ -+ #if defined(__IS_FIRST__) -+ ifxusb_pcd.core_if.core_no=0; -+ retval = ifxusb_driver_probe_d(&ifxusb_pcd, -+ IFXUSB1_IRQ, -+ IFXUSB1_IOMEM_BASE, -+ IFXUSB1_FIFOMEM_BASE, -+ IFXUSB1_FIFODBG_BASE -+ ); -+ #elif defined(__IS_SECOND__) -+ ifxusb_pcd.core_if.core_no=1; -+ retval = ifxusb_driver_probe_d(&ifxusb_pcd, -+ IFXUSB2_IRQ, -+ IFXUSB2_IOMEM_BASE, -+ IFXUSB2_FIFOMEM_BASE, -+ IFXUSB2_FIFODBG_BASE -+ ); -+ #else -+ ifxusb_pcd.core_if.core_no=0; -+ retval = ifxusb_driver_probe_d(&ifxusb_pcd, -+ IFXUSB_IRQ, -+ IFXUSB_IOMEM_BASE, -+ IFXUSB_FIFOMEM_BASE, -+ IFXUSB_FIFODBG_BASE -+ ); -+ #endif -+ if(retval) -+ goto ifxusb_driver_probe_fail; -+ #endif -+ -+ ifxusb_attr_create(&_dev->dev); -+ -+ return 0; -+ -+ifxusb_driver_probe_fail: -+ ifxusb_driver_remove(_dev); -+ return retval; -+} -+ -+ -+ -+/*! -+ \brief This function is called when the ifxusb_driver is installed with the insmod command. -+*/ -+ -+ -+static struct platform_driver ifxusb_driver = { -+ .driver = { -+ .name = ifxusb_driver_name, -+ .owner = THIS_MODULE, -+ }, -+ .probe = ifxusb_driver_probe, -+ .remove = ifxusb_driver_remove, -+}; -+ -+int __init ifxusb_driver_init(void) -+{ -+ int retval = 0; -+ -+ IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); -+ IFX_PRINT("%s: version %s\n", ifxusb_driver_name, IFXUSB_VERSION); -+ -+ retval = platform_driver_register(&ifxusb_driver); -+ -+ if (retval < 0) { -+ IFX_ERROR("%s retval=%d\n", __func__, retval); -+ return retval; -+ } -+ return retval; -+} -+ -+#if 0 // 2.4 -+ int __init ifxusb_driver_init(void) -+ { -+ int retval = 0; -+ IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); -+ IFX_PRINT("%s: version %s\n", ifxusb_driver_name, IFXUSB_VERSION); -+ retval = ifxusb_driver_probe(); -+ -+ if (retval < 0) { -+ IFX_ERROR("%s retval=%d\n", __func__, retval); -+ return retval; -+ } -+ -+ return retval; -+ } -+#endif -+ -+module_init(ifxusb_driver_init); -+ -+ -+/*! -+ \brief This function is called when the driver is removed from the kernel -+ with the rmmod command. The driver unregisters itself with its bus -+ driver. -+*/ -+ -+void __exit ifxusb_driver_cleanup(void) -+{ -+ IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); -+ -+ platform_driver_unregister(&ifxusb_driver); -+ -+ IFX_PRINT("%s module removed\n", ifxusb_driver_name); -+} -+#if 0 -+ void __exit ifxusb_driver_cleanup(void) -+ { -+ IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); -+ ifxusb_driver_remove(); -+ IFX_PRINT("%s module removed\n", ifxusb_driver_name); -+ } -+#endif -+module_exit(ifxusb_driver_cleanup); -+ -+ -+ -+MODULE_DESCRIPTION(USB_DRIVER_DESC); -+MODULE_AUTHOR("Infineon"); -+MODULE_LICENSE("GPL"); -+ -+ -+ -+// Parameters set when loaded -+//static long dbg_lvl =0xFFFFFFFF; -+static long dbg_lvl =0; -+static short dma_burst_size =-1; -+static short speed =-1; -+static long data_fifo_size =-1; -+#ifdef __IS_DEVICE__ -+ static long rx_fifo_size =-1; -+ #ifdef __DED_FIFO__ -+ static long tx_fifo_size_00 =-1; -+ static long tx_fifo_size_01 =-1; -+ static long tx_fifo_size_02 =-1; -+ static long tx_fifo_size_03 =-1; -+ static long tx_fifo_size_04 =-1; -+ static long tx_fifo_size_05 =-1; -+ static long tx_fifo_size_06 =-1; -+ static long tx_fifo_size_07 =-1; -+ static long tx_fifo_size_08 =-1; -+ static long tx_fifo_size_09 =-1; -+ static long tx_fifo_size_10 =-1; -+ static long tx_fifo_size_11 =-1; -+ static long tx_fifo_size_12 =-1; -+ static long tx_fifo_size_13 =-1; -+ static long tx_fifo_size_14 =-1; -+ static long tx_fifo_size_15 =-1; -+ static short thr_ctl=-1; -+ static long tx_thr_length =-1; -+ static long rx_thr_length =-1; -+ #else -+ static long nperio_tx_fifo_size =-1; -+ static long perio_tx_fifo_size_01 =-1; -+ static long perio_tx_fifo_size_02 =-1; -+ static long perio_tx_fifo_size_03 =-1; -+ static long perio_tx_fifo_size_04 =-1; -+ static long perio_tx_fifo_size_05 =-1; -+ static long perio_tx_fifo_size_06 =-1; -+ static long perio_tx_fifo_size_07 =-1; -+ static long perio_tx_fifo_size_08 =-1; -+ static long perio_tx_fifo_size_09 =-1; -+ static long perio_tx_fifo_size_10 =-1; -+ static long perio_tx_fifo_size_11 =-1; -+ static long perio_tx_fifo_size_12 =-1; -+ static long perio_tx_fifo_size_13 =-1; -+ static long perio_tx_fifo_size_14 =-1; -+ static long perio_tx_fifo_size_15 =-1; -+ #endif -+ static short dev_endpoints =-1; -+#endif -+ -+#ifdef __IS_HOST__ -+ static long rx_fifo_size =-1; -+ static long nperio_tx_fifo_size =-1; -+ static long perio_tx_fifo_size =-1; -+ static short host_channels =-1; -+#endif -+ -+static long max_transfer_size =-1; -+static long max_packet_count =-1; -+static long phy_utmi_width =-1; -+static long turn_around_time_hs =-1; -+static long turn_around_time_fs =-1; -+static long timeout_cal_hs =-1; -+static long timeout_cal_fs =-1; -+ -+/*! -+ \brief Parsing the parameters taken when module load -+*/ -+static void parse_parms(void) -+{ -+ -+ IFX_DEBUGPL(DBG_ENTRY, "%s() %d\n", __func__, __LINE__ ); -+ #ifdef __IS_HOST__ -+ h_dbg_lvl=dbg_lvl; -+ #endif -+ #ifdef __IS_DEVICE__ -+ d_dbg_lvl=dbg_lvl; -+ #endif -+ -+ switch(dma_burst_size) -+ { -+ case 0: -+ case 1: -+ case 4: -+ case 8: -+ case 16: -+ ifxusb_module_params.dma_burst_size=dma_burst_size; -+ break; -+ default: -+ ifxusb_module_params.dma_burst_size=default_param_dma_burst_size; -+ } -+ -+ if(speed==0 || speed==1) -+ ifxusb_module_params.speed=speed; -+ else -+ ifxusb_module_params.speed=default_param_speed; -+ -+ if(max_transfer_size>=2048 && max_transfer_size<=65535) -+ ifxusb_module_params.max_transfer_size=max_transfer_size; -+ else -+ ifxusb_module_params.max_transfer_size=default_param_max_transfer_size; -+ -+ if(max_packet_count>=15 && max_packet_count<=511) -+ ifxusb_module_params.max_packet_count=max_packet_count; -+ else -+ ifxusb_module_params.max_packet_count=default_param_max_packet_count; -+ -+ switch(phy_utmi_width) -+ { -+ case 8: -+ case 16: -+ ifxusb_module_params.phy_utmi_width=phy_utmi_width; -+ break; -+ default: -+ ifxusb_module_params.phy_utmi_width=default_param_phy_utmi_width; -+ } -+ -+ if(turn_around_time_hs>=0 && turn_around_time_hs<=7) -+ ifxusb_module_params.turn_around_time_hs=turn_around_time_hs; -+ else -+ ifxusb_module_params.turn_around_time_hs=default_param_turn_around_time_hs; -+ -+ if(turn_around_time_fs>=0 && turn_around_time_fs<=7) -+ ifxusb_module_params.turn_around_time_fs=turn_around_time_fs; -+ else -+ ifxusb_module_params.turn_around_time_fs=default_param_turn_around_time_fs; -+ -+ if(timeout_cal_hs>=0 && timeout_cal_hs<=7) -+ ifxusb_module_params.timeout_cal_hs=timeout_cal_hs; -+ else -+ ifxusb_module_params.timeout_cal_hs=default_param_timeout_cal_hs; -+ -+ if(timeout_cal_fs>=0 && timeout_cal_fs<=7) -+ ifxusb_module_params.timeout_cal_fs=timeout_cal_fs; -+ else -+ ifxusb_module_params.timeout_cal_fs=default_param_timeout_cal_fs; -+ -+ if(data_fifo_size>=32 && data_fifo_size<=32768) -+ ifxusb_module_params.data_fifo_size=data_fifo_size; -+ else -+ ifxusb_module_params.data_fifo_size=default_param_data_fifo_size; -+ -+ #ifdef __IS_HOST__ -+ if(host_channels>=1 && host_channels<=16) -+ ifxusb_module_params.host_channels=host_channels; -+ else -+ ifxusb_module_params.host_channels=default_param_host_channels; -+ -+ if(rx_fifo_size>=16 && rx_fifo_size<=32768) -+ ifxusb_module_params.rx_fifo_size=rx_fifo_size; -+ else -+ ifxusb_module_params.rx_fifo_size=default_param_rx_fifo_size; -+ -+ if(nperio_tx_fifo_size>=16 && nperio_tx_fifo_size<=32768) -+ ifxusb_module_params.nperio_tx_fifo_size=nperio_tx_fifo_size; -+ else -+ ifxusb_module_params.nperio_tx_fifo_size=default_param_nperio_tx_fifo_size; -+ -+ if(perio_tx_fifo_size>=16 && perio_tx_fifo_size<=32768) -+ ifxusb_module_params.perio_tx_fifo_size=perio_tx_fifo_size; -+ else -+ ifxusb_module_params.perio_tx_fifo_size=default_param_perio_tx_fifo_size; -+ #endif //__IS_HOST__ -+ -+ #ifdef __IS_DEVICE__ -+ if(rx_fifo_size>=16 && rx_fifo_size<=32768) -+ ifxusb_module_params.rx_fifo_size=rx_fifo_size; -+ else -+ ifxusb_module_params.rx_fifo_size=default_param_rx_fifo_size; -+ #ifdef __DED_FIFO__ -+ if(tx_fifo_size_00>=16 && tx_fifo_size_00<=32768) -+ ifxusb_module_params.tx_fifo_size[ 0]=tx_fifo_size_00; -+ else -+ ifxusb_module_params.tx_fifo_size[ 0]=default_param_tx_fifo_size_00; -+ if(tx_fifo_size_01>=0 && tx_fifo_size_01<=32768) -+ ifxusb_module_params.tx_fifo_size[ 1]=tx_fifo_size_01; -+ else -+ ifxusb_module_params.tx_fifo_size[ 1]=default_param_tx_fifo_size_01; -+ if(tx_fifo_size_02>=0 && tx_fifo_size_02<=32768) -+ ifxusb_module_params.tx_fifo_size[ 2]=tx_fifo_size_02; -+ else -+ ifxusb_module_params.tx_fifo_size[ 2]=default_param_tx_fifo_size_02; -+ if(tx_fifo_size_03>=0 && tx_fifo_size_03<=32768) -+ ifxusb_module_params.tx_fifo_size[ 3]=tx_fifo_size_03; -+ else -+ ifxusb_module_params.tx_fifo_size[ 3]=default_param_tx_fifo_size_03; -+ if(tx_fifo_size_04>=0 && tx_fifo_size_04<=32768) -+ ifxusb_module_params.tx_fifo_size[ 4]=tx_fifo_size_04; -+ else -+ ifxusb_module_params.tx_fifo_size[ 4]=default_param_tx_fifo_size_04; -+ if(tx_fifo_size_05>=0 && tx_fifo_size_05<=32768) -+ ifxusb_module_params.tx_fifo_size[ 5]=tx_fifo_size_05; -+ else -+ ifxusb_module_params.tx_fifo_size[ 5]=default_param_tx_fifo_size_05; -+ if(tx_fifo_size_06>=0 && tx_fifo_size_06<=32768) -+ ifxusb_module_params.tx_fifo_size[ 6]=tx_fifo_size_06; -+ else -+ ifxusb_module_params.tx_fifo_size[ 6]=default_param_tx_fifo_size_06; -+ if(tx_fifo_size_07>=0 && tx_fifo_size_07<=32768) -+ ifxusb_module_params.tx_fifo_size[ 7]=tx_fifo_size_07; -+ else -+ ifxusb_module_params.tx_fifo_size[ 7]=default_param_tx_fifo_size_07; -+ if(tx_fifo_size_08>=0 && tx_fifo_size_08<=32768) -+ ifxusb_module_params.tx_fifo_size[ 8]=tx_fifo_size_08; -+ else -+ ifxusb_module_params.tx_fifo_size[ 8]=default_param_tx_fifo_size_08; -+ if(tx_fifo_size_09>=0 && tx_fifo_size_09<=32768) -+ ifxusb_module_params.tx_fifo_size[ 9]=tx_fifo_size_09; -+ else -+ ifxusb_module_params.tx_fifo_size[ 9]=default_param_tx_fifo_size_09; -+ if(tx_fifo_size_10>=0 && tx_fifo_size_10<=32768) -+ ifxusb_module_params.tx_fifo_size[10]=tx_fifo_size_10; -+ else -+ ifxusb_module_params.tx_fifo_size[10]=default_param_tx_fifo_size_10; -+ if(tx_fifo_size_11>=0 && tx_fifo_size_11<=32768) -+ ifxusb_module_params.tx_fifo_size[11]=tx_fifo_size_11; -+ else -+ ifxusb_module_params.tx_fifo_size[11]=default_param_tx_fifo_size_11; -+ if(tx_fifo_size_12>=0 && tx_fifo_size_12<=32768) -+ ifxusb_module_params.tx_fifo_size[12]=tx_fifo_size_12; -+ else -+ ifxusb_module_params.tx_fifo_size[12]=default_param_tx_fifo_size_12; -+ if(tx_fifo_size_13>=0 && tx_fifo_size_13<=32768) -+ ifxusb_module_params.tx_fifo_size[13]=tx_fifo_size_13; -+ else -+ ifxusb_module_params.tx_fifo_size[13]=default_param_tx_fifo_size_13; -+ if(tx_fifo_size_14>=0 && tx_fifo_size_14<=32768) -+ ifxusb_module_params.tx_fifo_size[14]=tx_fifo_size_14; -+ else -+ ifxusb_module_params.tx_fifo_size[14]=default_param_tx_fifo_size_14; -+ if(tx_fifo_size_15>=0 && tx_fifo_size_15<=32768) -+ ifxusb_module_params.tx_fifo_size[15]=tx_fifo_size_15; -+ else -+ ifxusb_module_params.tx_fifo_size[15]=default_param_tx_fifo_size_15; -+ if(thr_ctl==0 || thr_ctl==1) -+ ifxusb_module_params.thr_ctl=thr_ctl; -+ else -+ ifxusb_module_params.thr_ctl=default_param_thr_ctl; -+ if(tx_thr_length>=16 && tx_thr_length<=511) -+ ifxusb_module_params.tx_thr_length=tx_thr_length; -+ else -+ ifxusb_module_params.tx_thr_length=default_param_tx_thr_length; -+ if(rx_thr_length>=16 && rx_thr_length<=511) -+ ifxusb_module_params.rx_thr_length=rx_thr_length; -+ else -+ ifxusb_module_params.rx_thr_length=default_param_rx_thr_length; -+ #else //__DED_FIFO__ -+ if(nperio_tx_fifo_size>=16 && nperio_tx_fifo_size<=32768) -+ ifxusb_module_params.tx_fifo_size[ 0]=nperio_tx_fifo_size; -+ else -+ ifxusb_module_params.tx_fifo_size[ 0]=default_param_nperio_tx_fifo_size; -+ if(perio_tx_fifo_size_01>=0 && perio_tx_fifo_size_01<=32768) -+ ifxusb_module_params.tx_fifo_size[ 1]=perio_tx_fifo_size_01; -+ else -+ ifxusb_module_params.tx_fifo_size[ 1]=default_param_perio_tx_fifo_size_01; -+ if(perio_tx_fifo_size_02>=0 && perio_tx_fifo_size_02<=32768) -+ ifxusb_module_params.tx_fifo_size[ 2]=perio_tx_fifo_size_02; -+ else -+ ifxusb_module_params.tx_fifo_size[ 2]=default_param_perio_tx_fifo_size_02; -+ if(perio_tx_fifo_size_03>=0 && perio_tx_fifo_size_03<=32768) -+ ifxusb_module_params.tx_fifo_size[ 3]=perio_tx_fifo_size_03; -+ else -+ ifxusb_module_params.tx_fifo_size[ 3]=default_param_perio_tx_fifo_size_03; -+ if(perio_tx_fifo_size_04>=0 && perio_tx_fifo_size_04<=32768) -+ ifxusb_module_params.tx_fifo_size[ 4]=perio_tx_fifo_size_04; -+ else -+ ifxusb_module_params.tx_fifo_size[ 4]=default_param_perio_tx_fifo_size_04; -+ if(perio_tx_fifo_size_05>=0 && perio_tx_fifo_size_05<=32768) -+ ifxusb_module_params.tx_fifo_size[ 5]=perio_tx_fifo_size_05; -+ else -+ ifxusb_module_params.tx_fifo_size[ 5]=default_param_perio_tx_fifo_size_05; -+ if(perio_tx_fifo_size_06>=0 && perio_tx_fifo_size_06<=32768) -+ ifxusb_module_params.tx_fifo_size[ 6]=perio_tx_fifo_size_06; -+ else -+ ifxusb_module_params.tx_fifo_size[ 6]=default_param_perio_tx_fifo_size_06; -+ if(perio_tx_fifo_size_07>=0 && perio_tx_fifo_size_07<=32768) -+ ifxusb_module_params.tx_fifo_size[ 7]=perio_tx_fifo_size_07; -+ else -+ ifxusb_module_params.tx_fifo_size[ 7]=default_param_perio_tx_fifo_size_07; -+ if(perio_tx_fifo_size_08>=0 && perio_tx_fifo_size_08<=32768) -+ ifxusb_module_params.tx_fifo_size[ 8]=perio_tx_fifo_size_08; -+ else -+ ifxusb_module_params.tx_fifo_size[ 8]=default_param_perio_tx_fifo_size_08; -+ if(perio_tx_fifo_size_09>=0 && perio_tx_fifo_size_09<=32768) -+ ifxusb_module_params.tx_fifo_size[ 9]=perio_tx_fifo_size_09; -+ else -+ ifxusb_module_params.tx_fifo_size[ 9]=default_param_perio_tx_fifo_size_09; -+ if(perio_tx_fifo_size_10>=0 && perio_tx_fifo_size_10<=32768) -+ ifxusb_module_params.tx_fifo_size[10]=perio_tx_fifo_size_10; -+ else -+ ifxusb_module_params.tx_fifo_size[10]=default_param_perio_tx_fifo_size_10; -+ if(perio_tx_fifo_size_11>=0 && perio_tx_fifo_size_11<=32768) -+ ifxusb_module_params.tx_fifo_size[11]=perio_tx_fifo_size_11; -+ else -+ ifxusb_module_params.tx_fifo_size[11]=default_param_perio_tx_fifo_size_11; -+ if(perio_tx_fifo_size_12>=0 && perio_tx_fifo_size_12<=32768) -+ ifxusb_module_params.tx_fifo_size[12]=perio_tx_fifo_size_12; -+ else -+ ifxusb_module_params.tx_fifo_size[12]=default_param_perio_tx_fifo_size_12; -+ if(perio_tx_fifo_size_13>=0 && perio_tx_fifo_size_13<=32768) -+ ifxusb_module_params.tx_fifo_size[13]=perio_tx_fifo_size_13; -+ else -+ ifxusb_module_params.tx_fifo_size[13]=default_param_perio_tx_fifo_size_13; -+ if(perio_tx_fifo_size_14>=0 && perio_tx_fifo_size_14<=32768) -+ ifxusb_module_params.tx_fifo_size[14]=perio_tx_fifo_size_14; -+ else -+ ifxusb_module_params.tx_fifo_size[14]=default_param_perio_tx_fifo_size_14; -+ if(perio_tx_fifo_size_15>=0 && perio_tx_fifo_size_15<=32768) -+ ifxusb_module_params.tx_fifo_size[15]=perio_tx_fifo_size_15; -+ else -+ ifxusb_module_params.tx_fifo_size[15]=default_param_perio_tx_fifo_size_15; -+ #endif //__DED_FIFO__ -+ #endif //__IS_DEVICE__ -+} -+ -+ -+ -+ -+ -+ -+ -+module_param(dbg_lvl, long, 0444); -+MODULE_PARM_DESC(dbg_lvl, "Debug level."); -+ -+module_param(dma_burst_size, short, 0444); -+MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 0, 1, 4, 8, 16"); -+ -+module_param(speed, short, 0444); -+MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed"); -+ -+module_param(data_fifo_size, long, 0444); -+MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768"); -+ -+#ifdef __IS_DEVICE__ -+ module_param(rx_fifo_size, long, 0444); -+ MODULE_PARM_DESC(rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); -+ -+ #ifdef __DED_FIFO__ -+ module_param(tx_fifo_size_00, long, 0444); -+ MODULE_PARM_DESC(tx_fifo_size_00, "Number of words in the Tx FIFO #00 16-32768"); -+ module_param(tx_fifo_size_01, long, 0444); -+ MODULE_PARM_DESC(tx_fifo_size_01, "Number of words in the Tx FIFO #01 0-32768"); -+ module_param(tx_fifo_size_02, long, 0444); -+ MODULE_PARM_DESC(tx_fifo_size_02, "Number of words in the Tx FIFO #02 0-32768"); -+ module_param(tx_fifo_size_03, long, 0444); -+ MODULE_PARM_DESC(tx_fifo_size_03, "Number of words in the Tx FIFO #03 0-32768"); -+ module_param(tx_fifo_size_04, long, 0444); -+ MODULE_PARM_DESC(tx_fifo_size_04, "Number of words in the Tx FIFO #04 0-32768"); -+ module_param(tx_fifo_size_05, long, 0444); -+ MODULE_PARM_DESC(tx_fifo_size_05, "Number of words in the Tx FIFO #05 0-32768"); -+ module_param(tx_fifo_size_06, long, 0444); -+ MODULE_PARM_DESC(tx_fifo_size_06, "Number of words in the Tx FIFO #06 0-32768"); -+ module_param(tx_fifo_size_07, long, 0444); -+ MODULE_PARM_DESC(tx_fifo_size_07, "Number of words in the Tx FIFO #07 0-32768"); -+ module_param(tx_fifo_size_08, long, 0444); -+ MODULE_PARM_DESC(tx_fifo_size_08, "Number of words in the Tx FIFO #08 0-32768"); -+ module_param(tx_fifo_size_09, long, 0444); -+ MODULE_PARM_DESC(tx_fifo_size_09, "Number of words in the Tx FIFO #09 0-32768"); -+ module_param(tx_fifo_size_10, long, 0444); -+ MODULE_PARM_DESC(tx_fifo_size_10, "Number of words in the Tx FIFO #10 0-32768"); -+ module_param(tx_fifo_size_11, long, 0444); -+ MODULE_PARM_DESC(tx_fifo_size_11, "Number of words in the Tx FIFO #11 0-32768"); -+ module_param(tx_fifo_size_12, long, 0444); -+ MODULE_PARM_DESC(tx_fifo_size_12, "Number of words in the Tx FIFO #12 0-32768"); -+ module_param(tx_fifo_size_13, long, 0444); -+ MODULE_PARM_DESC(tx_fifo_size_13, "Number of words in the Tx FIFO #13 0-32768"); -+ module_param(tx_fifo_size_14, long, 0444); -+ MODULE_PARM_DESC(tx_fifo_size_14, "Number of words in the Tx FIFO #14 0-32768"); -+ module_param(tx_fifo_size_15, long, 0444); -+ MODULE_PARM_DESC(tx_fifo_size_15, "Number of words in the Tx FIFO #15 0-32768"); -+ -+ module_param(thr_ctl, short, 0444); -+ MODULE_PARM_DESC(thr_ctl, "0=Without 1=With Theshold Ctrl"); -+ -+ module_param(tx_thr_length, long, 0444); -+ MODULE_PARM_DESC(tx_thr_length, "TX Threshold length"); -+ -+ module_param(rx_thr_length, long, 0444); -+ MODULE_PARM_DESC(rx_thr_length, "RX Threshold length"); -+ -+ #else -+ module_param(nperio_tx_fifo_size, long, 0444); -+ MODULE_PARM_DESC(nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768"); -+ -+ module_param(perio_tx_fifo_size_01, long, 0444); -+ MODULE_PARM_DESC(perio_tx_fifo_size_01, "Number of words in the periodic Tx FIFO #01 0-32768"); -+ module_param(perio_tx_fifo_size_02, long, 0444); -+ MODULE_PARM_DESC(perio_tx_fifo_size_02, "Number of words in the periodic Tx FIFO #02 0-32768"); -+ module_param(perio_tx_fifo_size_03, long, 0444); -+ MODULE_PARM_DESC(perio_tx_fifo_size_03, "Number of words in the periodic Tx FIFO #03 0-32768"); -+ module_param(perio_tx_fifo_size_04, long, 0444); -+ MODULE_PARM_DESC(perio_tx_fifo_size_04, "Number of words in the periodic Tx FIFO #04 0-32768"); -+ module_param(perio_tx_fifo_size_05, long, 0444); -+ MODULE_PARM_DESC(perio_tx_fifo_size_05, "Number of words in the periodic Tx FIFO #05 0-32768"); -+ module_param(perio_tx_fifo_size_06, long, 0444); -+ MODULE_PARM_DESC(perio_tx_fifo_size_06, "Number of words in the periodic Tx FIFO #06 0-32768"); -+ module_param(perio_tx_fifo_size_07, long, 0444); -+ MODULE_PARM_DESC(perio_tx_fifo_size_07, "Number of words in the periodic Tx FIFO #07 0-32768"); -+ module_param(perio_tx_fifo_size_08, long, 0444); -+ MODULE_PARM_DESC(perio_tx_fifo_size_08, "Number of words in the periodic Tx FIFO #08 0-32768"); -+ module_param(perio_tx_fifo_size_09, long, 0444); -+ MODULE_PARM_DESC(perio_tx_fifo_size_09, "Number of words in the periodic Tx FIFO #09 0-32768"); -+ module_param(perio_tx_fifo_size_10, long, 0444); -+ MODULE_PARM_DESC(perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO #10 0-32768"); -+ module_param(perio_tx_fifo_size_11, long, 0444); -+ MODULE_PARM_DESC(perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO #11 0-32768"); -+ module_param(perio_tx_fifo_size_12, long, 0444); -+ MODULE_PARM_DESC(perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO #12 0-32768"); -+ module_param(perio_tx_fifo_size_13, long, 0444); -+ MODULE_PARM_DESC(perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO #13 0-32768"); -+ module_param(perio_tx_fifo_size_14, long, 0444); -+ MODULE_PARM_DESC(perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO #14 0-32768"); -+ module_param(perio_tx_fifo_size_15, long, 0444); -+ MODULE_PARM_DESC(perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO #15 0-32768"); -+ #endif//__DED_FIFO__ -+ module_param(dev_endpoints, short, 0444); -+ MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15"); -+#endif -+ -+#ifdef __IS_HOST__ -+ module_param(rx_fifo_size, long, 0444); -+ MODULE_PARM_DESC(rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); -+ -+ module_param(nperio_tx_fifo_size, long, 0444); -+ MODULE_PARM_DESC(nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768"); -+ -+ module_param(perio_tx_fifo_size, long, 0444); -+ MODULE_PARM_DESC(perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768"); -+ -+ module_param(host_channels, short, 0444); -+ MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16"); -+#endif -+ -+module_param(max_transfer_size, long, 0444); -+MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535"); -+ -+module_param(max_packet_count, long, 0444); -+MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511"); -+ -+module_param(phy_utmi_width, long, 0444); -+MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits"); -+ -+module_param(turn_around_time_hs, long, 0444); -+MODULE_PARM_DESC(turn_around_time_hs, "Turn-Around time for HS"); -+ -+module_param(turn_around_time_fs, long, 0444); -+MODULE_PARM_DESC(turn_around_time_fs, "Turn-Around time for FS"); -+ -+module_param(timeout_cal_hs, long, 0444); -+MODULE_PARM_DESC(timeout_cal_hs, "Timeout Cal for HS"); -+ -+module_param(timeout_cal_fs, long, 0444); -+MODULE_PARM_DESC(timeout_cal_fs, "Timeout Cal for FS"); -+ -+ ---- /dev/null -+++ b/drivers/usb/ifxhcd/ifxusb_plat.h -@@ -0,0 +1,1018 @@ -+/***************************************************************************** -+ ** FILE NAME : ifxusb_plat.h -+ ** PROJECT : IFX USB sub-system V3 -+ ** MODULES : IFX USB sub-system Host and Device driver -+ ** SRC VERSION : 1.0 -+ ** DATE : 1/Jan/2009 -+ ** AUTHOR : Chen, Howard -+ ** DESCRIPTION : This file contains the Platform Specific constants, interfaces -+ ** (functions and macros). -+ ** FUNCTIONS : -+ ** COMPILER : gcc -+ ** REFERENCE : IFX hardware ref handbook for each plateforms -+ ** COPYRIGHT : -+ ** Version Control Section ** -+ ** $Author$ -+ ** $Date$ -+ ** $Revisions$ -+ ** $Log$ Revision history -+ *****************************************************************************/ -+ -+ -+/*! -+ \defgroup IFXUSB_PLATEFORM_DEFINITION Platform Specific constants, interfaces (functions and macros). -+ \ingroup IFXUSB_DRIVER_V3 -+ \brief Maintain plateform specific definitions and macros in this file. -+ Each plateform has its own definition zone. -+ */ -+ -+/*! -+ \defgroup IFXUSB_PLATEFORM_MEM_ADDR Definition of memory address and size and default parameters -+ \ingroup IFXUSB_PLATEFORM_DEFINITION -+ */ -+ -+/*! -+ \defgroup IFXUSB_DBG_ROUTINE Routines for debug message -+ \ingroup IFXUSB_PLATEFORM_DEFINITION -+ */ -+ -+ -+/*! \file ifxusb_plat.h -+ \ingroup IFXUSB_DRIVER_V3 -+ \brief This file contains the Platform Specific constants, interfaces (functions and macros). -+*/ -+ -+#if !defined(__IFXUSB_PLAT_H__) -+#define __IFXUSB_PLAT_H__ -+ -+ -+#include -+#include -+#include -+#include -+#include -+ -+ -+#define IFXUSB_IOMEM_SIZE 0x00001000 -+#define IFXUSB_FIFOMEM_SIZE 0x00010000 -+#define IFXUSB_FIFODBG_SIZE 0x00020000 -+ -+ -+ -+/*! -+ \addtogroup IFXUSB_PLATEFORM_MEM_ADDR -+ */ -+/*@{*/ -+#if defined(__UEIP__) -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+// #define IFXUSB_IRQ 54 -+ #define IFXUSB_IOMEM_BASE 0x1e101000 -+ #define IFXUSB_FIFOMEM_BASE 0x1e120000 -+ #define IFXUSB_FIFODBG_BASE 0x1e140000 -+// #define IFXUSB_OC_IRQ 151 -+ -+ #ifndef DANUBE_RCU_BASE_ADDR -+ #define DANUBE_RCU_BASE_ADDR (0xBF203000) -+ #endif -+ -+ #ifndef DANUBE_CGU -+ #define DANUBE_CGU (0xBF103000) -+ #endif -+ #ifndef DANUBE_CGU_IFCCR -+ #define DANUBE_CGU_IFCCR ((volatile unsigned long *)(DANUBE_CGU+ 0x0018)) -+ #endif -+ #ifndef DANUBE_PMU -+ #define DANUBE_PMU (KSEG1+0x1F102000) -+ #endif -+ #ifndef DANUBE_PMU_PWDCR -+ #define DANUBE_PMU_PWDCR ((volatile unsigned long *)(DANUBE_PMU+0x001C)) -+ #endif -+ -+ #ifndef DANUBE_GPIO_P0_OUT -+ #define DANUBE_GPIO_P0_OUT (0xBF103000+0x10) -+ #define DANUBE_GPIO_P0_DIR (0xBF103000+0x18) -+ #define DANUBE_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) -+ #define DANUBE_GPIO_P0_ALTSEL1 (0xBF103000+0x20) -+ #define DANUBE_GPIO_P0_OD (0xBF103000+0x24) -+ #define DANUBE_GPIO_P0_PUDSEL (0xBF103000+0x2C) -+ #define DANUBE_GPIO_P0_PUDEN (0xBF103000+0x30) -+ #define DANUBE_GPIO_P1_OUT (0xBF103000+0x40) -+ #define DANUBE_GPIO_P1_DIR (0xBF103000+0x48) -+ #define DANUBE_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) -+ #define DANUBE_GPIO_P1_ALTSEL1 (0xBF103000+0x50) -+ #define DANUBE_GPIO_P1_OD (0xBF103000+0x54) -+ #define DANUBE_GPIO_P1_PUDSEL (0xBF103000+0x5C) -+ #define DANUBE_GPIO_P1_PUDEN (0xBF103000+0x60) -+ #endif -+ -+ #define DANUBE_RCU_USBCFG ((volatile unsigned long *)(DANUBE_RCU_BASE_ADDR + 0x18)) -+ #define DANUBE_RCU_RESET ((volatile unsigned long *)(DANUBE_RCU_BASE_ADDR + 0x10)) -+ #define DANUBE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device -+ #define DANUBE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end -+ #define DANUBE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end -+ -+ #define default_param_dma_burst_size 4 -+ -+ #define default_param_speed IFXUSB_PARAM_SPEED_HIGH -+ -+ #define default_param_max_transfer_size -1 //(Max, hwcfg) -+ #define default_param_max_packet_count -1 //(Max, hwcfg) -+ #define default_param_phy_utmi_width 16 -+ -+ #define default_param_turn_around_time_hs 4 -+ #define default_param_turn_around_time_fs 4 -+ #define default_param_timeout_cal_hs -1 //(NoChange) -+ #define default_param_timeout_cal_fs -1 //(NoChange) -+ -+ #define default_param_data_fifo_size -1 //(Max, hwcfg) -+ -+ #ifdef __IS_HOST__ -+ #define default_param_host_channels -1 //(Max, hwcfg) -+ #define default_param_rx_fifo_size 640 -+ #define default_param_nperio_tx_fifo_size 640 -+ #define default_param_perio_tx_fifo_size 768 -+ #endif //__IS_HOST__ -+ -+ #ifdef __IS_DEVICE__ -+ #ifdef __DED_INTR__ -+ #define default_param_rx_fifo_size 1024 -+ #define default_param_nperio_tx_fifo_size 1016 -+ #define default_param_perio_tx_fifo_size_01 8 -+ #else -+ #define default_param_rx_fifo_size 1024 -+ #define default_param_nperio_tx_fifo_size 1024 -+ #define default_param_perio_tx_fifo_size_01 0 -+ #endif -+ #define default_param_perio_tx_fifo_size_02 0 -+ #define default_param_perio_tx_fifo_size_03 0 -+ #define default_param_perio_tx_fifo_size_04 0 -+ #define default_param_perio_tx_fifo_size_05 0 -+ #define default_param_perio_tx_fifo_size_06 0 -+ #define default_param_perio_tx_fifo_size_07 0 -+ #define default_param_perio_tx_fifo_size_08 0 -+ #define default_param_perio_tx_fifo_size_09 0 -+ #define default_param_perio_tx_fifo_size_10 0 -+ #define default_param_perio_tx_fifo_size_11 0 -+ #define default_param_perio_tx_fifo_size_12 0 -+ #define default_param_perio_tx_fifo_size_13 0 -+ #define default_param_perio_tx_fifo_size_14 0 -+ #define default_param_perio_tx_fifo_size_15 0 -+ #endif //__IS_DEVICE__ -+ -+ #elif defined(__IS_AMAZON_SE__) -+ //#include -+ //#include -+ -+// #define IFXUSB_IRQ 31 -+ #define IFXUSB_IOMEM_BASE 0x1e101000 -+ #define IFXUSB_FIFOMEM_BASE 0x1e120000 -+ #define IFXUSB_FIFODBG_BASE 0x1e140000 -+// #define IFXUSB_OC_IRQ 20 -+ -+ #ifndef AMAZON_SE_RCU_BASE_ADDR -+ #define AMAZON_SE_RCU_BASE_ADDR (0xBF203000) -+ #endif -+ #define AMAZON_SE_RCU_USBCFG ((volatile unsigned long *)(AMAZON_SE_RCU_BASE_ADDR + 0x18)) -+ #define AMAZON_SE_RCU_RESET ((volatile unsigned long *)(AMAZON_SE_RCU_BASE_ADDR + 0x10)) -+ #define AMAZON_SE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device -+ #define AMAZON_SE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end -+ #define AMAZON_SE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end -+ -+ #ifndef AMAZON_SE_GPIO_P0_OUT -+ #define AMAZON_SE_GPIO_P0_OUT (0xBF103000+0x10) -+ #define AMAZON_SE_GPIO_P0_DIR (0xBF103000+0x18) -+ #define AMAZON_SE_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) -+ #define AMAZON_SE_GPIO_P0_ALTSEL1 (0xBF103000+0x20) -+ #define AMAZON_SE_GPIO_P0_OD (0xBF103000+0x24) -+ #define AMAZON_SE_GPIO_P0_PUDSEL (0xBF103000+0x2C) -+ #define AMAZON_SE_GPIO_P0_PUDEN (0xBF103000+0x30) -+ #define AMAZON_SE_GPIO_P1_OUT (0xBF103000+0x40) -+ #define AMAZON_SE_GPIO_P1_DIR (0xBF103000+0x48) -+ #define AMAZON_SE_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) -+ #define AMAZON_SE_GPIO_P1_ALTSEL1 (0xBF103000+0x50) -+ #define AMAZON_SE_GPIO_P1_OD (0xBF103000+0x54) -+ #define AMAZON_SE_GPIO_P1_PUDSEL (0xBF103000+0x5C) -+ #define AMAZON_SE_GPIO_P1_PUDEN (0xBF103000+0x60) -+ #endif -+ -+ #ifndef AMAZON_SE_CGU -+ #define AMAZON_SE_CGU (0xBF103000) -+ #endif -+ #ifndef AMAZON_SE_CGU_IFCCR -+ #define AMAZON_SE_CGU_IFCCR ((volatile unsigned long *)(AMAZON_SE_CGU+ 0x0018)) -+ #endif -+ #ifndef AMAZON_SE_PMU -+ #define AMAZON_SE_PMU (KSEG1+0x1F102000) -+ #endif -+ #ifndef AMAZON_SE_PMU_PWDCR -+ #define AMAZON_SE_PMU_PWDCR ((volatile unsigned long *)(AMAZON_SE_PMU+0x001C)) -+ #endif -+ -+ #define default_param_dma_burst_size 4 -+ -+ #define default_param_speed IFXUSB_PARAM_SPEED_HIGH -+ -+ #define default_param_max_transfer_size -1 //(Max, hwcfg) -+ #define default_param_max_packet_count -1 //(Max, hwcfg) -+ #define default_param_phy_utmi_width 16 -+ -+ #define default_param_turn_around_time_hs 4 //(NoChange) -+ #define default_param_turn_around_time_fs 4 //(NoChange) -+ #define default_param_timeout_cal_hs -1 //(NoChange) -+ #define default_param_timeout_cal_fs -1 //(NoChange) -+ -+ #define default_param_data_fifo_size -1 //(Max, hwcfg) -+ -+ #ifdef __IS_HOST__ -+ #define default_param_host_channels -1 //(Max, hwcfg) -+ #define default_param_rx_fifo_size 240 -+ #define default_param_nperio_tx_fifo_size 240 -+ #define default_param_perio_tx_fifo_size 32 -+ #endif //__IS_HOST__ -+ #ifdef __IS_DEVICE__ -+ #ifdef __DED_INTR__ -+ #define default_param_rx_fifo_size 256 -+ #define default_param_nperio_tx_fifo_size 248 -+ #define default_param_perio_tx_fifo_size_01 8 -+ #else -+ #define default_param_rx_fifo_size 256 -+ #define default_param_nperio_tx_fifo_size 256 -+ #define default_param_perio_tx_fifo_size_01 0 -+ #endif -+ #define default_param_perio_tx_fifo_size_02 0 -+ #define default_param_perio_tx_fifo_size_03 0 -+ #define default_param_perio_tx_fifo_size_04 0 -+ #define default_param_perio_tx_fifo_size_05 0 -+ #define default_param_perio_tx_fifo_size_06 0 -+ #define default_param_perio_tx_fifo_size_07 0 -+ #define default_param_perio_tx_fifo_size_08 0 -+ #define default_param_perio_tx_fifo_size_09 0 -+ #define default_param_perio_tx_fifo_size_10 0 -+ #define default_param_perio_tx_fifo_size_11 0 -+ #define default_param_perio_tx_fifo_size_12 0 -+ #define default_param_perio_tx_fifo_size_13 0 -+ #define default_param_perio_tx_fifo_size_14 0 -+ #define default_param_perio_tx_fifo_size_15 0 -+ #endif //__IS_DEVICE__ -+ -+ #elif defined(__IS_AR9__) -+// #define IFXUSB1_IRQ 54 -+ #define IFXUSB1_IOMEM_BASE 0x1E101000 -+ #define IFXUSB1_FIFOMEM_BASE 0x1E120000 -+ #define IFXUSB1_FIFODBG_BASE 0x1E140000 -+ -+// #define IFXUSB2_IRQ 83 -+ #define IFXUSB2_IOMEM_BASE 0x1E106000 -+ #define IFXUSB2_FIFOMEM_BASE 0x1E1E0000 -+ #define IFXUSB2_FIFODBG_BASE 0x1E1C0000 -+ -+// #define IFXUSB_OC_IRQ 60 -+ -+ #ifndef AR9_RCU_BASE_ADDR -+ #define AR9_RCU_BASE_ADDR (0xBF203000) -+ #endif -+ -+ #ifndef AR9_CGU -+ #define AR9_CGU (0xBF103000) -+ #endif -+ #ifndef AR9_CGU_IFCCR -+ #define AR9_CGU_IFCCR ((volatile unsigned long *)(AR9_CGU+ 0x0018)) -+ #endif -+ -+ #ifndef AR9_PMU -+ #define AR9_PMU (KSEG1+0x1F102000) -+ #endif -+ #ifndef AR9_PMU_PWDCR -+ #define AR9_PMU_PWDCR ((volatile unsigned long *)(AR9_PMU+0x001C)) -+ #endif -+ -+ #ifndef AR9_GPIO_P0_OUT -+ #define AR9_GPIO_P0_OUT (0xBF103000+0x10) -+ #define AR9_GPIO_P0_DIR (0xBF103000+0x18) -+ #define AR9_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) -+ #define AR9_GPIO_P0_ALTSEL1 (0xBF103000+0x20) -+ #define AR9_GPIO_P0_OD (0xBF103000+0x24) -+ #define AR9_GPIO_P0_PUDSEL (0xBF103000+0x2C) -+ #define AR9_GPIO_P0_PUDEN (0xBF103000+0x30) -+ #define AR9_GPIO_P1_OUT (0xBF103000+0x40) -+ #define AR9_GPIO_P1_DIR (0xBF103000+0x48) -+ #define AR9_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) -+ #define AR9_GPIO_P1_ALTSEL1 (0xBF103000+0x50) -+ #define AR9_GPIO_P1_OD (0xBF103000+0x54) -+ #define AR9_GPIO_P1_PUDSEL (0xBF103000+0x5C) -+ #define AR9_GPIO_P1_PUDEN (0xBF103000+0x60) -+ #endif -+ -+ #define AR9_RCU_USB1CFG ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x18)) -+ #define AR9_RCU_USB2CFG ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x34)) -+ #define AR9_RCU_USBRESET ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x10)) -+ #define AR9_USBCFG_ARB 7 // -+ #define AR9_USBCFG_HDSEL_BIT 11 // 0:host, 1:device -+ #define AR9_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end -+ #define AR9_USBCFG_SLV_END_BIT 17 // 0:little_end, 1:big_end -+ -+ #define default_param_dma_burst_size 4 -+ -+ #define default_param_speed IFXUSB_PARAM_SPEED_HIGH -+ -+ #define default_param_max_transfer_size -1 //(Max, hwcfg) -+ #define default_param_max_packet_count -1 //(Max, hwcfg) -+ #define default_param_phy_utmi_width 16 -+ -+ #define default_param_turn_around_time_hs 4 //(NoChange) -+ #define default_param_turn_around_time_fs 4 //(NoChange) -+ #define default_param_timeout_cal_hs -1 //(NoChange) -+ #define default_param_timeout_cal_fs -1 //(NoChange) -+ -+ #define default_param_data_fifo_size -1 //(Max, hwcfg) -+ -+ #ifdef __IS_HOST__ -+ #define default_param_host_channels -1 //(Max, hwcfg) -+ #define default_param_rx_fifo_size 240 -+ #define default_param_nperio_tx_fifo_size 240 -+ #define default_param_perio_tx_fifo_size 32 -+ #endif //__IS_HOST__ -+ #ifdef __IS_DEVICE__ -+ #ifdef __DED_INTR__ -+ #define default_param_rx_fifo_size 256 -+// #define default_param_nperio_tx_fifo_size 248 -+// #define default_param_perio_tx_fifo_size_01 8 -+ #define default_param_nperio_tx_fifo_size 252 -+ #define default_param_perio_tx_fifo_size_01 4 -+ #else -+ #define default_param_rx_fifo_size 256 -+ #define default_param_nperio_tx_fifo_size 256 -+ #define default_param_perio_tx_fifo_size_01 0 -+ #endif -+ #define default_param_perio_tx_fifo_size_02 0 -+ #define default_param_perio_tx_fifo_size_03 0 -+ #define default_param_perio_tx_fifo_size_04 0 -+ #define default_param_perio_tx_fifo_size_05 0 -+ #define default_param_perio_tx_fifo_size_06 0 -+ #define default_param_perio_tx_fifo_size_07 0 -+ #define default_param_perio_tx_fifo_size_08 0 -+ #define default_param_perio_tx_fifo_size_09 0 -+ #define default_param_perio_tx_fifo_size_10 0 -+ #define default_param_perio_tx_fifo_size_11 0 -+ #define default_param_perio_tx_fifo_size_12 0 -+ #define default_param_perio_tx_fifo_size_13 0 -+ #define default_param_perio_tx_fifo_size_14 0 -+ #define default_param_perio_tx_fifo_size_15 0 -+ #endif //__IS_DEVICE__ -+ -+ #elif defined(__IS_VR9__) -+// #define IFXUSB1_IRQ 54 -+ #define IFXUSB1_IOMEM_BASE 0x1E101000 -+ #define IFXUSB1_FIFOMEM_BASE 0x1E120000 -+ #define IFXUSB1_FIFODBG_BASE 0x1E140000 -+ -+// #define IFXUSB2_IRQ 83 -+ #define IFXUSB2_IOMEM_BASE 0x1E106000 -+ #define IFXUSB2_FIFOMEM_BASE 0x1E1E0000 -+ #define IFXUSB2_FIFODBG_BASE 0x1E1C0000 -+// #define IFXUSB_OC_IRQ 60 -+ -+ #ifndef VR9_RCU_BASE_ADDR -+ #define VR9_RCU_BASE_ADDR (0xBF203000) -+ #endif -+ -+ #ifndef VR9_CGU -+ #define VR9_CGU (0xBF103000) -+ #endif -+ #ifndef VR9_CGU_IFCCR -+ #define VR9_CGU_IFCCR ((volatile unsigned long *)(VR9_CGU+ 0x0018)) -+ #endif -+ -+ #ifndef VR9_PMU -+ #define VR9_PMU (KSEG1+0x1F102000) -+ #endif -+ #ifndef VR9_PMU_PWDCR -+ #define VR9_PMU_PWDCR ((volatile unsigned long *)(VR9_PMU+0x001C)) -+ #endif -+ -+ #ifndef VR9_GPIO_P0_OUT -+ #define VR9_GPIO_P0_OUT (0xBF103000+0x10) -+ #define VR9_GPIO_P0_DIR (0xBF103000+0x18) -+ #define VR9_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) -+ #define VR9_GPIO_P0_ALTSEL1 (0xBF103000+0x20) -+ #define VR9_GPIO_P0_OD (0xBF103000+0x24) -+ #define VR9_GPIO_P0_PUDSEL (0xBF103000+0x2C) -+ #define VR9_GPIO_P0_PUDEN (0xBF103000+0x30) -+ #define VR9_GPIO_P1_OUT (0xBF103000+0x40) -+ #define VR9_GPIO_P1_DIR (0xBF103000+0x48) -+ #define VR9_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) -+ #define VR9_GPIO_P1_ALTSEL1 (0xBF103000+0x50) -+ #define VR9_GPIO_P1_OD (0xBF103000+0x54) -+ #define VR9_GPIO_P1_PUDSEL (0xBF103000+0x5C) -+ #define VR9_GPIO_P1_PUDEN (0xBF103000+0x60) -+ #endif -+ -+ #define VR9_RCU_USB1CFG ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x18)) -+ #define VR9_RCU_USB2CFG ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x34)) -+ #define VR9_RCU_USB_ANA_CFG1A ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x38)) -+ #define VR9_RCU_USB_ANA_CFG1B ((volatile unsigned long *)(AR9_RCU_BASE_ADDR + 0x3C)) -+ #define VR9_RCU_USBRESET ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x10)) -+ #define VR9_RCU_USBRESET2 ((volatile unsigned long *)(VR9_RCU_BASE_ADDR + 0x48)) -+ #define VR9_USBCFG_ARB 7 // -+ #define VR9_USBCFG_HDSEL_BIT 11 // 0:host, 1:device -+ #define VR9_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end -+ #define VR9_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end -+ -+ /*== AVM/BC 20101220 Workaround VR9 DMA burst size == -+ * Using 2 Devices in diferent ports cause a general USB Host Error. -+ * Workaround found in UGW4.3 -+ */ -+// #define default_param_dma_burst_size 4 //(ALL) -+ //WA for AHB -+ #define default_param_dma_burst_size 0 //(ALL) -+ -+ #define default_param_speed IFXUSB_PARAM_SPEED_HIGH -+ -+ #define default_param_max_transfer_size -1 //(Max, hwcfg) -+ #define default_param_max_packet_count -1 //(Max, hwcfg) -+ #define default_param_phy_utmi_width 16 -+ -+ #define default_param_turn_around_time_hs 6 //(NoChange) snpsid >= 0x4f54260a -+ #define default_param_turn_around_time_fs 6 //(NoChange) snpsid >= 0x4f54260a -+ #define default_param_timeout_cal_hs -1 //(NoChange) -+ #define default_param_timeout_cal_fs -1 //(NoChange) -+ -+ #define default_param_data_fifo_size -1 //(Max, hwcfg) -+ -+ #ifdef __IS_HOST__ -+ #define default_param_host_channels -1 //(Max, hwcfg) -+ #define default_param_rx_fifo_size 240 -+ #define default_param_nperio_tx_fifo_size 240 -+ #define default_param_perio_tx_fifo_size 32 -+ #endif //__IS_HOST__ -+ #ifdef __IS_DEVICE__ -+#if 0 -+ #define default_param_rx_fifo_size 256 -+ #define default_param_tx_fifo_size_00 -1 -+ #define default_param_tx_fifo_size_01 -1 -+ #define default_param_tx_fifo_size_02 -1 -+#else -+ #define default_param_rx_fifo_size 256 -+ #define default_param_tx_fifo_size_00 32 -+ #define default_param_tx_fifo_size_01 200 -+ #define default_param_tx_fifo_size_02 8 -+#endif -+ #define default_param_tx_fifo_size_03 -1 -+ #define default_param_tx_fifo_size_04 -1 -+ #define default_param_tx_fifo_size_05 -1 -+ #define default_param_tx_fifo_size_06 -1 -+ #define default_param_tx_fifo_size_07 -1 -+ #define default_param_tx_fifo_size_08 -1 -+ #define default_param_tx_fifo_size_09 -1 -+ #define default_param_tx_fifo_size_10 -1 -+ #define default_param_tx_fifo_size_11 -1 -+ #define default_param_tx_fifo_size_12 -1 -+ #define default_param_tx_fifo_size_13 -1 -+ #define default_param_tx_fifo_size_14 -1 -+ #define default_param_tx_fifo_size_15 -1 -+ #define default_param_dma_unalgned_tx -1 -+ #define default_param_dma_unalgned_rx -1 -+ #define default_param_thr_ctl -1 -+ #define default_param_tx_thr_length -1 -+ #define default_param_rx_thr_length -1 -+ #endif //__IS_DEVICE__ -+ #else // __IS_VR9__ -+ #error "Please choose one platform!!" -+ #endif // __IS_VR9__ -+ -+#else //UEIP -+ #if defined(__IS_TWINPASS__) || defined(__IS_DANUBE__) -+// #define IFXUSB_IRQ 54 -+ #define IFXUSB_IOMEM_BASE 0x1e101000 -+ #define IFXUSB_FIFOMEM_BASE 0x1e120000 -+ #define IFXUSB_FIFODBG_BASE 0x1e140000 -+// #define IFXUSB_OC_IRQ 151 -+ -+ -+ #ifndef DANUBE_RCU_BASE_ADDR -+ #define DANUBE_RCU_BASE_ADDR (0xBF203000) -+ #endif -+ -+ #ifndef DANUBE_CGU -+ #define DANUBE_CGU (0xBF103000) -+ #endif -+ #ifndef DANUBE_CGU_IFCCR -+ #define DANUBE_CGU_IFCCR ((volatile unsigned long *)(DANUBE_CGU+ 0x0018)) -+ #endif -+ #ifndef DANUBE_PMU -+ #define DANUBE_PMU (KSEG1+0x1F102000) -+ #endif -+ #ifndef DANUBE_PMU_PWDCR -+ #define DANUBE_PMU_PWDCR ((volatile unsigned long *)(DANUBE_PMU+0x001C)) -+ #endif -+ -+ #ifndef DANUBE_GPIO_P0_OUT -+ #define DANUBE_GPIO_P0_OUT (0xBF103000+0x10) -+ #define DANUBE_GPIO_P0_DIR (0xBF103000+0x18) -+ #define DANUBE_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) -+ #define DANUBE_GPIO_P0_ALTSEL1 (0xBF103000+0x20) -+ #define DANUBE_GPIO_P0_OD (0xBF103000+0x24) -+ #define DANUBE_GPIO_P0_PUDSEL (0xBF103000+0x2C) -+ #define DANUBE_GPIO_P0_PUDEN (0xBF103000+0x30) -+ #define DANUBE_GPIO_P1_OUT (0xBF103000+0x40) -+ #define DANUBE_GPIO_P1_DIR (0xBF103000+0x48) -+ #define DANUBE_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) -+ #define DANUBE_GPIO_P1_ALTSEL1 (0xBF103000+0x50) -+ #define DANUBE_GPIO_P1_OD (0xBF103000+0x54) -+ #define DANUBE_GPIO_P1_PUDSEL (0xBF103000+0x5C) -+ #define DANUBE_GPIO_P1_PUDEN (0xBF103000+0x60) -+ #endif -+ -+ -+ #define DANUBE_RCU_USBCFG ((volatile unsigned long *)(DANUBE_RCU_BASE_ADDR + 0x18)) -+ #define DANUBE_RCU_RESET ((volatile unsigned long *)(DANUBE_RCU_BASE_ADDR + 0x10)) -+ #define DANUBE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device -+ #define DANUBE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end -+ #define DANUBE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end -+ -+ #define default_param_dma_burst_size 4 -+ -+ #define default_param_speed IFXUSB_PARAM_SPEED_HIGH -+ -+ #define default_param_max_transfer_size -1 //(Max, hwcfg) -+ #define default_param_max_packet_count -1 //(Max, hwcfg) -+ #define default_param_phy_utmi_width 16 -+ -+ #define default_param_turn_around_time_hs 4 //(NoChange) -+ #define default_param_turn_around_time_fs 4 //(NoChange) -+ #define default_param_timeout_cal_hs -1 //(NoChange) -+ #define default_param_timeout_cal_fs -1 //(NoChange) -+ -+ #define default_param_data_fifo_size -1 //(Max, hwcfg) -+ #ifdef __IS_HOST__ -+ #define default_param_host_channels -1 //(Max, hwcfg) -+ #define default_param_rx_fifo_size 640 -+ #define default_param_nperio_tx_fifo_size 640 -+ #define default_param_perio_tx_fifo_size 768 -+ #endif //__IS_HOST__ -+ -+ #ifdef __IS_DEVICE__ -+ #ifdef __DED_INTR__ -+ #define default_param_rx_fifo_size 1024 -+ #define default_param_nperio_tx_fifo_size 1016 -+ #define default_param_perio_tx_fifo_size_01 8 -+ #else -+ #define default_param_rx_fifo_size 1024 -+ #define default_param_nperio_tx_fifo_size 1024 -+ #define default_param_perio_tx_fifo_size_01 0 -+ #endif -+ #define default_param_perio_tx_fifo_size_02 0 -+ #define default_param_perio_tx_fifo_size_03 0 -+ #define default_param_perio_tx_fifo_size_04 0 -+ #define default_param_perio_tx_fifo_size_05 0 -+ #define default_param_perio_tx_fifo_size_06 0 -+ #define default_param_perio_tx_fifo_size_07 0 -+ #define default_param_perio_tx_fifo_size_08 0 -+ #define default_param_perio_tx_fifo_size_09 0 -+ #define default_param_perio_tx_fifo_size_10 0 -+ #define default_param_perio_tx_fifo_size_11 0 -+ #define default_param_perio_tx_fifo_size_12 0 -+ #define default_param_perio_tx_fifo_size_13 0 -+ #define default_param_perio_tx_fifo_size_14 0 -+ #define default_param_perio_tx_fifo_size_15 0 -+ #endif //__IS_DEVICE__ -+ -+ #elif defined(__IS_AMAZON_SE__) -+ #include -+ //#include -+ -+// #define IFXUSB_IRQ 31 -+ #define IFXUSB_IOMEM_BASE 0x1e101000 -+ #define IFXUSB_FIFOMEM_BASE 0x1e120000 -+ #define IFXUSB_FIFODBG_BASE 0x1e140000 -+// #define IFXUSB_OC_IRQ 20 -+ -+ #define AMAZON_SE_RCU_USBCFG ((volatile unsigned long *)(AMAZON_SE_RCU_BASE_ADDR + 0x18)) -+ #define AMAZON_SE_RCU_RESET ((volatile unsigned long *)(AMAZON_SE_RCU_BASE_ADDR + 0x10)) -+ #define AMAZON_SE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device -+ #define AMAZON_SE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end -+ #define AMAZON_SE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end -+ -+ #ifndef AMAZON_SE_GPIO_P0_OUT -+ #define AMAZON_SE_GPIO_P0_OUT (0xBF103000+0x10) -+ #define AMAZON_SE_GPIO_P0_DIR (0xBF103000+0x18) -+ #define AMAZON_SE_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) -+ #define AMAZON_SE_GPIO_P0_ALTSEL1 (0xBF103000+0x20) -+ #define AMAZON_SE_GPIO_P0_OD (0xBF103000+0x24) -+ #define AMAZON_SE_GPIO_P0_PUDSEL (0xBF103000+0x2C) -+ #define AMAZON_SE_GPIO_P0_PUDEN (0xBF103000+0x30) -+ #define AMAZON_SE_GPIO_P1_OUT (0xBF103000+0x40) -+ #define AMAZON_SE_GPIO_P1_DIR (0xBF103000+0x48) -+ #define AMAZON_SE_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) -+ #define AMAZON_SE_GPIO_P1_ALTSEL1 (0xBF103000+0x50) -+ #define AMAZON_SE_GPIO_P1_OD (0xBF103000+0x54) -+ #define AMAZON_SE_GPIO_P1_PUDSEL (0xBF103000+0x5C) -+ #define AMAZON_SE_GPIO_P1_PUDEN (0xBF103000+0x60) -+ #endif -+ -+ -+ #ifndef AMAZON_SE_CGU -+ #define AMAZON_SE_CGU (0xBF103000) -+ #endif -+ #ifndef AMAZON_SE_CGU_IFCCR -+ #define AMAZON_SE_CGU_IFCCR ((volatile unsigned long *)(AMAZON_SE_CGU+ 0x0018)) -+ #endif -+ #ifndef AMAZON_SE_PMU -+ #define AMAZON_SE_PMU (KSEG1+0x1F102000) -+ #endif -+ #ifndef AMAZON_SE_PMU_PWDCR -+ #define AMAZON_SE_PMU_PWDCR ((volatile unsigned long *)(AMAZON_SE_PMU+0x001C)) -+ #endif -+ -+ #define default_param_dma_burst_size 4 -+ -+ #define default_param_speed IFXUSB_PARAM_SPEED_HIGH -+ -+ #define default_param_max_transfer_size -1 //(Max, hwcfg) -+ #define default_param_max_packet_count -1 //(Max, hwcfg) -+ #define default_param_phy_utmi_width 16 -+ -+ #define default_param_turn_around_time_hs 4 //(NoChange) -+ #define default_param_turn_around_time_fs 4 //(NoChange) -+ #define default_param_timeout_cal_hs -1 //(NoChange) -+ #define default_param_timeout_cal_fs -1 //(NoChange) -+ -+ #define default_param_data_fifo_size -1 //(Max, hwcfg) -+ -+ #ifdef __IS_HOST__ -+ #define default_param_host_channels -1 //(Max, hwcfg) -+ #define default_param_rx_fifo_size 240 -+ #define default_param_nperio_tx_fifo_size 240 -+ #define default_param_perio_tx_fifo_size 32 -+ #endif //__IS_HOST__ -+ #ifdef __IS_DEVICE__ -+ #ifdef __DED_INTR__ -+ #define default_param_rx_fifo_size 256 -+ #define default_param_nperio_tx_fifo_size 248 -+ #define default_param_perio_tx_fifo_size_01 8 -+ #else -+ #define default_param_rx_fifo_size 256 -+ #define default_param_nperio_tx_fifo_size 256 -+ #define default_param_perio_tx_fifo_size_01 0 -+ #endif -+ #define default_param_perio_tx_fifo_size_02 0 -+ #define default_param_perio_tx_fifo_size_03 0 -+ #define default_param_perio_tx_fifo_size_04 0 -+ #define default_param_perio_tx_fifo_size_05 0 -+ #define default_param_perio_tx_fifo_size_06 0 -+ #define default_param_perio_tx_fifo_size_07 0 -+ #define default_param_perio_tx_fifo_size_08 0 -+ #define default_param_perio_tx_fifo_size_09 0 -+ #define default_param_perio_tx_fifo_size_10 0 -+ #define default_param_perio_tx_fifo_size_11 0 -+ #define default_param_perio_tx_fifo_size_12 0 -+ #define default_param_perio_tx_fifo_size_13 0 -+ #define default_param_perio_tx_fifo_size_14 0 -+ #define default_param_perio_tx_fifo_size_15 0 -+ #endif //__IS_DEVICE__ -+ -+ #elif defined(__IS_AR9__) -+// #define IFXUSB1_IRQ 54 -+ #define IFXUSB1_IOMEM_BASE 0x1E101000 -+ #define IFXUSB1_FIFOMEM_BASE 0x1E120000 -+ #define IFXUSB1_FIFODBG_BASE 0x1E140000 -+ -+// #define IFXUSB2_IRQ 83 -+ #define IFXUSB2_IOMEM_BASE 0x1E106000 -+ #define IFXUSB2_FIFOMEM_BASE 0x1E1E0000 -+ #define IFXUSB2_FIFODBG_BASE 0x1E1C0000 -+ -+// #define IFXUSB_OC_IRQ 60 -+ -+ #ifndef AMAZON_S_RCU_BASE_ADDR -+ #define AMAZON_S_RCU_BASE_ADDR (0xBF203000) -+ #endif -+ -+ #ifndef AMAZON_S_CGU -+ #define AMAZON_S_CGU (0xBF103000) -+ #endif -+ #ifndef AMAZON_S_CGU_IFCCR -+ #define AMAZON_S_CGU_IFCCR ((volatile unsigned long *)(AMAZON_S_CGU+ 0x0018)) -+ #endif -+ -+ #ifndef AMAZON_S_PMU -+ #define AMAZON_S_PMU (KSEG1+0x1F102000) -+ #endif -+ #ifndef AMAZON_S_PMU_PWDCR -+ #define AMAZON_S_PMU_PWDCR ((volatile unsigned long *)(AMAZON_S_PMU+0x001C)) -+ #endif -+ -+ #ifndef AMAZON_S_GPIO_P0_OUT -+ #define AMAZON_S_GPIO_P0_OUT (0xBF103000+0x10) -+ #define AMAZON_S_GPIO_P0_DIR (0xBF103000+0x18) -+ #define AMAZON_S_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) -+ #define AMAZON_S_GPIO_P0_ALTSEL1 (0xBF103000+0x20) -+ #define AMAZON_S_GPIO_P0_OD (0xBF103000+0x24) -+ #define AMAZON_S_GPIO_P0_PUDSEL (0xBF103000+0x2C) -+ #define AMAZON_S_GPIO_P0_PUDEN (0xBF103000+0x30) -+ #define AMAZON_S_GPIO_P1_OUT (0xBF103000+0x40) -+ #define AMAZON_S_GPIO_P1_DIR (0xBF103000+0x48) -+ #define AMAZON_S_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) -+ #define AMAZON_S_GPIO_P1_ALTSEL1 (0xBF103000+0x50) -+ #define AMAZON_S_GPIO_P1_OD (0xBF103000+0x54) -+ #define AMAZON_S_GPIO_P1_PUDSEL (0xBF103000+0x5C) -+ #define AMAZON_S_GPIO_P1_PUDEN (0xBF103000+0x60) -+ #endif -+ -+ #define AMAZON_S_RCU_USB1CFG ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x18)) -+ #define AMAZON_S_RCU_USB2CFG ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x34)) -+ #define AMAZON_S_RCU_USBRESET ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x10)) -+ #define AMAZON_S_USBCFG_ARB 7 // -+ #define AMAZON_S_USBCFG_HDSEL_BIT 11 // 0:host, 1:device -+ #define AMAZON_S_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end -+ #define AMAZON_S_USBCFG_SLV_END_BIT 17 // 0:little_end, 1:big_end -+ -+ #define default_param_dma_burst_size 4 -+ -+ #define default_param_speed IFXUSB_PARAM_SPEED_HIGH -+ -+ #define default_param_max_transfer_size -1 //(Max, hwcfg) -+ #define default_param_max_packet_count -1 //(Max, hwcfg) -+ #define default_param_phy_utmi_width 16 -+ -+ #define default_param_turn_around_time_hs 4 //(NoChange) -+ #define default_param_turn_around_time_fs 4 //(NoChange) -+ #define default_param_timeout_cal_hs -1 //(NoChange) -+ #define default_param_timeout_cal_fs -1 //(NoChange) -+ -+ #define default_param_data_fifo_size -1 //(Max, hwcfg) -+ -+ #ifdef __IS_HOST__ -+ #define default_param_host_channels -1 //(Max, hwcfg) -+ #define default_param_rx_fifo_size 240 -+ #define default_param_nperio_tx_fifo_size 240 -+ #define default_param_perio_tx_fifo_size 32 -+ #endif //__IS_HOST__ -+ #ifdef __IS_DEVICE__ -+ #ifdef __DED_INTR__ -+ #define default_param_rx_fifo_size 256 -+ #define default_param_nperio_tx_fifo_size 248 -+ #define default_param_perio_tx_fifo_size_01 8 -+ #else -+ #define default_param_rx_fifo_size 256 -+ #define default_param_nperio_tx_fifo_size 256 -+ #define default_param_perio_tx_fifo_size_01 0 -+ #endif -+ #define default_param_perio_tx_fifo_size_02 0 -+ #define default_param_perio_tx_fifo_size_03 0 -+ #define default_param_perio_tx_fifo_size_04 0 -+ #define default_param_perio_tx_fifo_size_05 0 -+ #define default_param_perio_tx_fifo_size_06 0 -+ #define default_param_perio_tx_fifo_size_07 0 -+ #define default_param_perio_tx_fifo_size_08 0 -+ #define default_param_perio_tx_fifo_size_09 0 -+ #define default_param_perio_tx_fifo_size_10 0 -+ #define default_param_perio_tx_fifo_size_11 0 -+ #define default_param_perio_tx_fifo_size_12 0 -+ #define default_param_perio_tx_fifo_size_13 0 -+ #define default_param_perio_tx_fifo_size_14 0 -+ #define default_param_perio_tx_fifo_size_15 0 -+ #endif //__IS_DEVICE__ -+ -+ #elif defined(__IS_VR9__) -+// #define IFXUSB1_IRQ 54 -+ #define IFXUSB1_IOMEM_BASE 0x1E101000 -+ #define IFXUSB1_FIFOMEM_BASE 0x1E120000 -+ #define IFXUSB1_FIFODBG_BASE 0x1E140000 -+ -+// #define IFXUSB2_IRQ 83 -+ #define IFXUSB2_IOMEM_BASE 0x1E106000 -+ #define IFXUSB2_FIFOMEM_BASE 0x1E1E0000 -+ #define IFXUSB2_FIFODBG_BASE 0x1E1C0000 -+// #define IFXUSB_OC_IRQ 60 -+ -+ #ifndef AMAZON_S_RCU_BASE_ADDR -+ #define AMAZON_S_RCU_BASE_ADDR (0xBF203000) -+ #endif -+ -+ #ifndef AMAZON_S_CGU -+ #define AMAZON_S_CGU (0xBF103000) -+ #endif -+ #ifndef AMAZON_S_CGU_IFCCR -+ #define AMAZON_S_CGU_IFCCR ((volatile unsigned long *)(AMAZON_S_CGU+ 0x0018)) -+ #endif -+ -+ #ifndef AMAZON_S_PMU -+ #define AMAZON_S_PMU (KSEG1+0x1F102000) -+ #endif -+ #ifndef AMAZON_S_PMU_PWDCR -+ #define AMAZON_S_PMU_PWDCR ((volatile unsigned long *)(AMAZON_S_PMU+0x001C)) -+ #endif -+ -+ #ifndef AMAZON_S_GPIO_P0_OUT -+ #define AMAZON_S_GPIO_P0_OUT (0xBF103000+0x10) -+ #define AMAZON_S_GPIO_P0_DIR (0xBF103000+0x18) -+ #define AMAZON_S_GPIO_P0_ALTSEL0 (0xBF103000+0x1C) -+ #define AMAZON_S_GPIO_P0_ALTSEL1 (0xBF103000+0x20) -+ #define AMAZON_S_GPIO_P0_OD (0xBF103000+0x24) -+ #define AMAZON_S_GPIO_P0_PUDSEL (0xBF103000+0x2C) -+ #define AMAZON_S_GPIO_P0_PUDEN (0xBF103000+0x30) -+ #define AMAZON_S_GPIO_P1_OUT (0xBF103000+0x40) -+ #define AMAZON_S_GPIO_P1_DIR (0xBF103000+0x48) -+ #define AMAZON_S_GPIO_P1_ALTSEL0 (0xBF103000+0x4C) -+ #define AMAZON_S_GPIO_P1_ALTSEL1 (0xBF103000+0x50) -+ #define AMAZON_S_GPIO_P1_OD (0xBF103000+0x54) -+ #define AMAZON_S_GPIO_P1_PUDSEL (0xBF103000+0x5C) -+ #define AMAZON_S_GPIO_P1_PUDEN (0xBF103000+0x60) -+ #endif -+ -+ #define AMAZON_S_RCU_USB1CFG ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x18)) -+ #define AMAZON_S_RCU_USB2CFG ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x34)) -+ #define AMAZON_S_RCU_USBRESET ((volatile unsigned long *)(AMAZON_S_RCU_BASE_ADDR + 0x10)) -+ #define AMAZON_S_USBCFG_ARB 7 // -+ #define AMAZON_S_USBCFG_HDSEL_BIT 11 // 0:host, 1:device -+ #define AMAZON_S_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end -+ #define AMAZON_S_USBCFG_SLV_END_BIT 17 // 0:little_end, 1:big_end -+ -+ #define default_param_dma_burst_size 4 //(ALL) -+ -+ #define default_param_speed IFXUSB_PARAM_SPEED_HIGH -+ -+ #define default_param_max_transfer_size -1 //(Max, hwcfg) -+ #define default_param_max_packet_count -1 //(Max, hwcfg) -+ #define default_param_phy_utmi_width 16 -+ -+ #define default_param_turn_around_time_hs 6 //(NoChange) snpsid >= 0x4f54260a -+ #define default_param_turn_around_time_fs 6 //(NoChange) snpsid >= 0x4f54260a -+ #define default_param_timeout_cal_hs -1 //(NoChange) -+ #define default_param_timeout_cal_fs -1 //(NoChange) -+ -+ #define default_param_data_fifo_size -1 //(Max, hwcfg) -+ -+ #ifdef __IS_HOST__ -+ #define default_param_host_channels -1 //(Max, hwcfg) -+ #define default_param_rx_fifo_size 240 -+ #define default_param_nperio_tx_fifo_size 240 -+ #define default_param_perio_tx_fifo_size 32 -+ #endif //__IS_HOST__ -+ #ifdef __IS_DEVICE__ -+ #define default_param_rx_fifo_size 256 -+ #define default_param_tx_fifo_size_00 -1 -+ #define default_param_tx_fifo_size_01 -1 -+ #define default_param_tx_fifo_size_02 -1 -+ #define default_param_tx_fifo_size_03 -1 -+ #define default_param_tx_fifo_size_04 -1 -+ #define default_param_tx_fifo_size_05 -1 -+ #define default_param_tx_fifo_size_06 -1 -+ #define default_param_tx_fifo_size_07 -1 -+ #define default_param_tx_fifo_size_08 -1 -+ #define default_param_tx_fifo_size_09 -1 -+ #define default_param_tx_fifo_size_10 -1 -+ #define default_param_tx_fifo_size_11 -1 -+ #define default_param_tx_fifo_size_12 -1 -+ #define default_param_tx_fifo_size_13 -1 -+ #define default_param_tx_fifo_size_14 -1 -+ #define default_param_tx_fifo_size_15 -1 -+ #define default_param_dma_unalgned_tx -1 -+ #define default_param_dma_unalgned_rx -1 -+ #define default_param_thr_ctl -1 -+ #define default_param_tx_thr_length -1 -+ #define default_param_rx_thr_length -1 -+ #endif //__IS_DEVICE__ -+ #else // __IS_VR9__ -+ #error "Please choose one platform!!" -+ #endif // __IS_VR9__ -+#endif //UEIP -+ -+/*@}*//*IFXUSB_PLATEFORM_MEM_ADDR*/ -+ -+///////////////////////////////////////////////////////////////////////// -+ -+#ifdef __IS_HOST__ -+ #ifdef CONFIG_USB_HOST_IFX_FORCE_USB11 -+ #undef default_param_speed -+ #define default_param_speed IFXUSB_PARAM_SPEED_FULL -+ #endif -+#endif -+#ifdef __IS_DEVICE__ -+ #ifndef CONFIG_USB_GADGET_DUALSPEED -+ #undef default_param_speed -+ #define default_param_speed IFXUSB_PARAM_SPEED_FULL -+ #endif -+#endif -+ -+///////////////////////////////////////////////////////////////////////// -+ -+static __inline__ void UDELAY( const uint32_t _usecs ) -+{ -+ udelay( _usecs ); -+} -+ -+static __inline__ void MDELAY( const uint32_t _msecs ) -+{ -+ mdelay( _msecs ); -+} -+ -+static __inline__ void SPIN_LOCK( spinlock_t *_lock ) -+{ -+ spin_lock(_lock); -+} -+ -+static __inline__ void SPIN_UNLOCK( spinlock_t *_lock ) -+{ -+ spin_unlock(_lock); -+} -+ -+#define SPIN_LOCK_IRQSAVE( _l, _f ) \ -+ { \ -+ spin_lock_irqsave(_l,_f); \ -+ } -+ -+#define SPIN_UNLOCK_IRQRESTORE( _l,_f ) \ -+ { \ -+ spin_unlock_irqrestore(_l,_f); \ -+ } -+ -+///////////////////////////////////////////////////////////////////////// -+/*! -+ \addtogroup IFXUSB_DBG_ROUTINE -+ */ -+/*@{*/ -+#ifdef __IS_HOST__ -+ extern uint32_t h_dbg_lvl; -+#endif -+ -+#ifdef __IS_DEVICE__ -+ extern uint32_t d_dbg_lvl; -+#endif -+ -+/*! \brief When debug level has the DBG_CIL bit set, display CIL Debug messages. */ -+#define DBG_CIL (0x2) -+/*! \brief When debug level has the DBG_CILV bit set, display CIL Verbose debug messages */ -+#define DBG_CILV (0x20) -+/*! \brief When debug level has the DBG_PCD bit set, display PCD (Device) debug messages */ -+#define DBG_PCD (0x4) -+/*! \brief When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug messages */ -+#define DBG_PCDV (0x40) -+/*! \brief When debug level has the DBG_HCD bit set, display Host debug messages */ -+#define DBG_HCD (0x8) -+/*! \brief When debug level has the DBG_HCDV bit set, display Verbose Host debug messages */ -+#define DBG_HCDV (0x80) -+/*! \brief When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host mode. */ -+#define DBG_HCD_URB (0x800) -+/*! \brief When debug level has any bit set, display debug messages */ -+#define DBG_ANY (0xFF) -+/*! \brief All debug messages off */ -+#define DBG_OFF 0 -+ -+#define DBG_ENTRY (0x8000) -+ -+#define IFXUSB "IFXUSB: " -+ -+/*! -+ \fn inline uint32_t SET_DEBUG_LEVEL( const uint32_t _new ) -+ \brief Set the Debug Level variable. -+ \param _new 32-bit mask of debug level. -+ \return previous debug level -+ */ -+static inline uint32_t SET_DEBUG_LEVEL( const uint32_t _new ) -+{ -+ #ifdef __IS_HOST__ -+ uint32_t old = h_dbg_lvl; -+ h_dbg_lvl = _new; -+ #endif -+ -+ #ifdef __IS_DEVICE__ -+ uint32_t old = d_dbg_lvl; -+ d_dbg_lvl = _new; -+ #endif -+ return old; -+} -+ -+#ifdef __DEBUG__ -+ #ifdef __IS_HOST__ -+ # define IFX_DEBUGPL(lvl, x...) do{ if ((lvl)&h_dbg_lvl)printk( KERN_DEBUG IFXUSB x ); }while(0) -+ # define CHK_DEBUG_LEVEL(level) ((level) & h_dbg_lvl) -+ #endif -+ -+ #ifdef __IS_DEVICE__ -+ # define IFX_DEBUGPL(lvl, x...) do{ if ((lvl)&d_dbg_lvl)printk( KERN_DEBUG IFXUSB x ); }while(0) -+ # define CHK_DEBUG_LEVEL(level) ((level) & d_dbg_lvl) -+ #endif -+ -+ # define IFX_DEBUGP(x...) IFX_DEBUGPL(DBG_ANY, x ) -+#else -+ # define IFX_DEBUGPL(lvl, x...) do{}while(0) -+ # define IFX_DEBUGP(x...) -+ # define CHK_DEBUG_LEVEL(level) (0) -+#endif //__DEBUG__ -+ -+/* Print an Error message. */ -+#define IFX_ERROR(x...) printk( KERN_ERR IFXUSB x ) -+/* Print a Warning message. */ -+#define IFX_WARN(x...) printk( KERN_WARNING IFXUSB x ) -+/* Print a notice (normal but significant message). */ -+#define IFX_NOTICE(x...) printk( KERN_NOTICE IFXUSB x ) -+/* Basic message printing. */ -+#define IFX_PRINT(x...) printk( KERN_INFO IFXUSB x ) -+ -+/*@}*//*IFXUSB_DBG_ROUTINE*/ -+ -+ -+#endif //__IFXUSB_PLAT_H__ -+ ---- /dev/null -+++ b/drivers/usb/ifxhcd/ifxusb_regs.h -@@ -0,0 +1,1420 @@ -+/***************************************************************************** -+ ** FILE NAME : ifxusb_regs.h -+ ** PROJECT : IFX USB sub-system V3 -+ ** MODULES : IFX USB sub-system Host and Device driver -+ ** SRC VERSION : 1.0 -+ ** DATE : 1/Jan/2009 -+ ** AUTHOR : Chen, Howard -+ ** DESCRIPTION : This file contains the data structures for accessing the IFXUSB core -+ ** registers. -+ ** The application interfaces with the USB core by reading from and -+ ** writing to the Control and Status Register (CSR) space through the -+ ** AHB Slave interface. These registers are 32 bits wide, and the -+ ** addresses are 32-bit-block aligned. -+ ** CSRs are classified as follows: -+ ** - Core Global Registers -+ ** - Device Mode Registers -+ ** - Device Global Registers -+ ** - Device Endpoint Specific Registers -+ ** - Host Mode Registers -+ ** - Host Global Registers -+ ** - Host Port CSRs -+ ** - Host Channel Specific Registers -+ ** -+ ** Only the Core Global registers can be accessed in both Device and -+ ** Host modes. When the USB core is operating in one mode, either -+ ** Device or Host, the application must not access registers from the -+ ** other mode. When the core switches from one mode to another, the -+ ** registers in the new mode of operation must be reprogrammed as they -+ ** would be after a power-on reset. -+ ** FUNCTIONS : -+ ** COMPILER : gcc -+ ** REFERENCE : Synopsys DWC-OTG Driver 2.7 -+ ** COPYRIGHT : -+ ** Version Control Section ** -+ ** $Author$ -+ ** $Date$ -+ ** $Revisions$ -+ ** $Log$ Revision history -+*****************************************************************************/ -+ -+ -+ -+/*! -+ \defgroup IFXUSB_CSR_DEFINITION Control and Status Register bit-map definition -+ \ingroup IFXUSB_DRIVER_V3 -+ \brief Data structures for accessing the IFXUSB core registers. -+ The application interfaces with the USB core by reading from and -+ writing to the Control and Status Register (CSR) space through the -+ AHB Slave interface. These registers are 32 bits wide, and the -+ addresses are 32-bit-block aligned. -+ CSRs are classified as follows: -+ - Core Global Registers -+ - Device Mode Registers -+ - Device Global Registers -+ - Device Endpoint Specific Registers -+ - Host Mode Registers -+ - Host Global Registers -+ - Host Port CSRs -+ - Host Channel Specific Registers -+ -+ Only the Core Global registers can be accessed in both Device andHost modes. -+ When the USB core is operating in one mode, either Device or Host, the -+ application must not access registers from the other mode. When the core -+ switches from one mode to another, the registers in the new mode of operation -+ must be reprogrammed as they would be after a power-on reset. -+ */ -+ -+/*! -+ \defgroup IFXUSB_CSR_DEVICE_GLOBAL_REG Device Mode Registers -+ \ingroup IFXUSB_CSR_DEFINITION -+ \brief Bit-mapped structure to access Device Mode Global Registers -+ */ -+ -+/*! -+ \defgroup IFXUSB_CSR_DEVICE_EP_REG Device Mode EP Registers -+ \ingroup IFXUSB_CSR_DEFINITION -+ \brief Bit-mapped structure to access Device Mode EP Registers -+ There will be one set of endpoint registers per logical endpoint -+ implemented. -+ These registers are visible only in Device mode and must not be -+ accessed in Host mode, as the results are unknown. -+ */ -+ -+/*! -+ \defgroup IFXUSB_CSR_DEVICE_DMA_DESC Device mode scatter dma descriptor strusture -+ \ingroup IFXUSB_CSR_DEFINITION -+ \brief Bit-mapped structure to DMA descriptor -+ */ -+ -+ -+/*! -+ \defgroup IFXUSB_CSR_HOST_GLOBAL_REG Host Mode Registers -+ \ingroup IFXUSB_CSR_DEFINITION -+ \brief Bit-mapped structure to access Host Mode Global Registers -+ */ -+ -+/*! -+ \defgroup IFXUSB_CSR_HOST_HC_REG Host Mode HC Registers -+ \ingroup IFXUSB_CSR_DEFINITION -+ \brief Bit-mapped structure to access Host Mode Host Channel Registers -+ There will be one set of endpoint registers per host channel -+ implemented. -+ These registers are visible only in Host mode and must not be -+ accessed in Device mode, as the results are unknown. -+ */ -+ -+/*! -+ \defgroup IFXUSB_CSR_PWR_CLK_GATING_REG Power and Clock Gating Control Register -+ \ingroup IFXUSB_CSR_DEFINITION -+ \brief Bit-mapped structure to Power and Clock Gating Control Register -+ */ -+ -+ -+ -+ -+ -+ -+ -+ -+/*! -+ \defgroup IFXUSB_CSR_CORE_GLOBAL_REG Core Global Registers -+ \ingroup IFXUSB_CSR_DEFINITION -+ \brief Bit-mapped structure to access Core Global Registers -+ */ -+/*! -+ \defgroup IFXUSB_CSR_CORE_GLOBAL_REG Core Global Registers -+ \ingroup IFXUSB_CSR_DEFINITION -+ \brief Bit-mapped structure to access Core Global Registers -+ */ -+ -+ -+ -+ -+ -+ -+ -+ -+ -+/*! -+ \file ifxusb_regs.h -+ \ingroup IFXUSB_DRIVER_V3 -+ \brief This file contains the data structures for accessing the IFXUSB core registers. -+ */ -+ -+ -+#ifndef __IFXUSB_REGS_H__ -+#define __IFXUSB_REGS_H__ -+ -+/****************************************************************************/ -+ -+#define MAX_PERIO_FIFOS 15 /** Maximum number of Periodic FIFOs */ -+#define MAX_TX_FIFOS 15 /** Maximum number of Periodic FIFOs */ -+#define MAX_EPS_CHANNELS 16 /** Maximum number of Endpoints/HostChannels */ -+ -+/****************************************************************************/ -+ -+/*! -+ \addtogroup IFXUSB_CSR_ACCESS_MACROS -+ */ -+/*@{*/ -+ -+//#define RecordRegRW -+ -+/*! -+ \fn static __inline__ uint32_t ifxusb_rreg( volatile uint32_t *_reg) -+ \brief Reads the content of a register. -+ \param _reg address of register to read. -+ \return contents of the register. -+ */ -+static __inline__ uint32_t ifxusb_rreg( volatile uint32_t *_reg) -+{ -+ #ifdef RecordRegRW -+ uint32_t r; -+ r=*(_reg); -+ return (r); -+ #else -+ return (*(_reg)); -+ #endif -+}; -+ -+ -+/*! -+ \fn static __inline__ void ifxusb_wreg( volatile uint32_t *_reg, const uint32_t _value) -+ \brief Writes a register with a 32 bit value. -+ \param _reg address of register to write. -+ \param _value value to write to _reg. -+ */ -+static __inline__ void ifxusb_wreg( volatile uint32_t *_reg, const uint32_t _value) -+{ -+ #ifdef RecordRegRW -+ printk(KERN_INFO "[W %p<-%08X]\n",_reg,_value); -+ #else -+ *(_reg)=_value; -+ #endif -+}; -+ -+/*! -+ \fn static __inline__ void ifxusb_mreg( volatile uint32_t *_reg, const uint32_t _clear_mask, const uint32_t _set_mask) -+ \brief Modifies bit values in a register. Using the -+ algorithm: (reg_contents & ~clear_mask) | set_mask. -+ \param _reg address of register to modify. -+ \param _clear_mask bit mask to be cleared. -+ \param _set_mask bit mask to be set. -+ */ -+static __inline__ void ifxusb_mreg( volatile uint32_t *_reg, const uint32_t _clear_mask, const uint32_t _set_mask) -+{ -+ uint32_t v; -+ #ifdef RecordRegRW -+ uint32_t r; -+ v= *(_reg); -+ r=v; -+ r&=(~_clear_mask); -+ r|= _set_mask; -+ *(_reg)=r ; -+ printk(KERN_INFO "[M %p->%08X+%08X/%08X<-%08X]\n",_reg,r,_clear_mask,_set_mask,r); -+ #else -+ v= *(_reg); -+ v&=(~_clear_mask); -+ v|= _set_mask; -+ *(_reg)=v ; -+ #endif -+}; -+ -+/*@}*//*IFXUSB_CSR_ACCESS_MACROS*/ -+/****************************************************************************/ -+ -+/*! -+ \addtogroup IFXUSB_CSR_CORE_GLOBAL_REG -+ */ -+/*@{*/ -+ -+/*! -+ \struct ifxusb_core_global_regs -+ \brief IFXUSB Core registers . -+ The ifxusb_core_global_regs structure defines the size -+ and relative field offsets for the Core Global registers. -+ */ -+typedef struct ifxusb_core_global_regs -+{ -+ volatile uint32_t gotgctl; /*!< 000h OTG Control and Status Register. */ -+ volatile uint32_t gotgint; /*!< 004h OTG Interrupt Register. */ -+ volatile uint32_t gahbcfg; /*!< 008h Core AHB Configuration Register. */ -+ volatile uint32_t gusbcfg; /*!< 00Ch Core USB Configuration Register. */ -+ volatile uint32_t grstctl; /*!< 010h Core Reset Register. */ -+ volatile uint32_t gintsts; /*!< 014h Core Interrupt Register. */ -+ volatile uint32_t gintmsk; /*!< 018h Core Interrupt Mask Register. */ -+ volatile uint32_t grxstsr; /*!< 01Ch Receive Status Queue Read Register (Read Only). */ -+ volatile uint32_t grxstsp; /*!< 020h Receive Status Queue Read & POP Register (Read Only). */ -+ volatile uint32_t grxfsiz; /*!< 024h Receive FIFO Size Register. */ -+ volatile uint32_t gnptxfsiz; /*!< 028h Non Periodic Transmit FIFO Size Register. */ -+ volatile uint32_t gnptxsts; /*!< 02Ch Non Periodic Transmit FIFO/Queue Status Register (Read Only). */ -+ volatile uint32_t gi2cctl; /*!< 030h I2C Access Register. */ -+ volatile uint32_t gpvndctl; /*!< 034h PHY Vendor Control Register. */ -+ volatile uint32_t ggpio; /*!< 038h General Purpose Input/Output Register. */ -+ volatile uint32_t guid; /*!< 03Ch User ID Register. */ -+ volatile uint32_t gsnpsid; /*!< 040h Synopsys ID Register (Read Only). */ -+ volatile uint32_t ghwcfg1; /*!< 044h User HW Config1 Register (Read Only). */ -+ volatile uint32_t ghwcfg2; /*!< 048h User HW Config2 Register (Read Only). */ -+ volatile uint32_t ghwcfg3; /*!< 04Ch User HW Config3 Register (Read Only). */ -+ volatile uint32_t ghwcfg4; /*!< 050h User HW Config4 Register (Read Only). */ -+ volatile uint32_t reserved[43]; /*!< 054h Reserved 054h-0FFh */ -+ volatile uint32_t hptxfsiz; /*!< 100h Host Periodic Transmit FIFO Size Register. */ -+ volatile uint32_t dptxfsiz_dieptxf[15];/*!< 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15. -+ Device Periodic Transmit FIFO#n Register if dedicated -+ fifos are disabled, otherwise Device Transmit FIFO#n -+ Register. -+ */ -+} ifxusb_core_global_regs_t; -+ -+/*! -+ \brief Bits of the Core OTG Control and Status Register (GOTGCTL). -+ */ -+typedef union gotgctl_data -+{ -+ uint32_t d32; -+ struct{ -+ unsigned reserved21_31 : 11; -+ unsigned currmod : 1 ; /*!< 20 */ -+ unsigned bsesvld : 1 ; /*!< 19 */ -+ unsigned asesvld : 1 ; /*!< 18 */ -+ unsigned reserved17 : 1 ; -+ unsigned conidsts : 1 ; /*!< 16 */ -+ unsigned reserved12_15 : 4 ; -+ unsigned devhnpen : 1 ; /*!< 11 */ -+ unsigned hstsethnpen : 1 ; /*!< 10 */ -+ unsigned hnpreq : 1 ; /*!< 09 */ -+ unsigned hstnegscs : 1 ; /*!< 08 */ -+ unsigned reserved2_7 : 6 ; -+ unsigned sesreq : 1 ; /*!< 01 */ -+ unsigned sesreqscs : 1 ; /*!< 00 */ -+ } b; -+} gotgctl_data_t; -+ -+/*! -+ \brief Bit fields of the Core OTG Interrupt Register (GOTGINT). -+ */ -+typedef union gotgint_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned reserved31_20 : 12; -+ unsigned debdone : 1 ; /*!< 19 Debounce Done */ -+ unsigned adevtoutchng : 1 ; /*!< 18 A-Device Timeout Change */ -+ unsigned hstnegdet : 1 ; /*!< 17 Host Negotiation Detected */ -+ unsigned reserver10_16 : 7 ; -+ unsigned hstnegsucstschng : 1 ; /*!< 09 Host Negotiation Success Status Change */ -+ unsigned sesreqsucstschng : 1 ; /*!< 08 Session Request Success Status Change */ -+ unsigned reserved3_7 : 5 ; -+ unsigned sesenddet : 1 ; /*!< 02 Session End Detected */ -+ unsigned reserved0_1 : 2 ; -+ } b; -+} gotgint_data_t; -+ -+/*! -+ \brief Bit fields of the Core AHB Configuration Register (GAHBCFG). -+ */ -+typedef union gahbcfg_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned reserved9_31 : 23; -+ unsigned ptxfemplvl : 1 ; /*!< 08 Periodic FIFO empty level trigger condition*/ -+ unsigned nptxfemplvl : 1 ; /*!< 07 Non-Periodic FIFO empty level trigger condition*/ -+ #define IFXUSB_GAHBCFG_TXFEMPTYLVL_EMPTY 1 -+ #define IFXUSB_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 -+ unsigned reserved : 1 ; -+ unsigned dmaenable : 1 ; /*!< 05 DMA enable*/ -+ #define IFXUSB_GAHBCFG_DMAENABLE 1 -+ unsigned hburstlen : 4 ; /*!< 01-04 DMA Burst-length*/ -+ #define IFXUSB_GAHBCFG_INT_DMA_BURST_SINGLE 0 -+ #define IFXUSB_GAHBCFG_INT_DMA_BURST_INCR 1 -+ #define IFXUSB_GAHBCFG_INT_DMA_BURST_INCR4 3 -+ #define IFXUSB_GAHBCFG_INT_DMA_BURST_INCR8 5 -+ #define IFXUSB_GAHBCFG_INT_DMA_BURST_INCR16 7 -+ unsigned glblintrmsk : 1 ; /*!< 00 USB Global Interrupt Enable */ -+ #define IFXUSB_GAHBCFG_GLBINT_ENABLE 1 -+ } b; -+} gahbcfg_data_t; -+ -+/*! -+ \brief Bit fields of the Core USB Configuration Register (GUSBCFG). -+*/ -+typedef union gusbcfg_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned reserved31 : 1; -+ unsigned ForceDevMode : 1; /*!< 30 Force Device Mode */ -+ unsigned ForceHstMode : 1; /*!< 29 Force Host Mode */ -+ unsigned TxEndDelay : 1; /*!< 28 Tx End Delay */ -+ unsigned reserved2723 : 5; -+ unsigned term_sel_dl_pulse : 1; /*!< 22 TermSel DLine Pulsing Selection */ -+ unsigned reserved2117 : 5; -+ unsigned otgutmifssel : 1; /*!< 16 UTMIFS Select */ -+ unsigned phylpwrclksel : 1; /*!< 15 PHY Low-Power Clock Select */ -+ unsigned reserved14 : 1; -+ unsigned usbtrdtim : 4; /*!< 13-10 USB Turnaround Time */ -+ unsigned hnpcap : 1; /*!< 09 HNP-Capable */ -+ unsigned srpcap : 1; /*!< 08 SRP-Capable */ -+ unsigned reserved07 : 1; -+ unsigned physel : 1; /*!< 06 USB 2.0 High-Speed PHY or -+ USB 1.1 Full-Speed Serial -+ Transceiver Select */ -+ unsigned fsintf : 1; /*!< 05 Full-Speed Serial Interface Select */ -+ unsigned ulpi_utmi_sel : 1; /*!< 04 ULPI or UTMI+ Select */ -+ unsigned phyif : 1; /*!< 03 PHY Interface */ -+ unsigned toutcal : 3; /*!< 00-02 HS/FS Timeout Calibration */ -+ }b; -+} gusbcfg_data_t; -+ -+/*! -+ \brief Bit fields of the Core Reset Register (GRSTCTL). -+ */ -+typedef union grstctl_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned ahbidle : 1; /*!< 31 AHB Master Idle. Indicates the AHB Master State -+ Machine is in IDLE condition. */ -+ unsigned dmareq : 1; /*!< 30 DMA Request Signal. Indicated DMA request is in -+ probress. Used for debug purpose. */ -+ unsigned reserved11_29 :19; -+ unsigned txfnum : 5; /*!< 10-06 TxFIFO Number (TxFNum) to be flushed. -+ 0x00: Non Periodic TxFIFO Flush or TxFIFO 0 -+ 0x01-0x0F: Periodic TxFIFO Flush or TxFIFO n -+ 0x10: Flush all TxFIFO -+ */ -+ unsigned txfflsh : 1; /*!< 05 TxFIFO Flush */ -+ unsigned rxfflsh : 1; /*!< 04 RxFIFO Flush */ -+ unsigned intknqflsh : 1; /*!< 03 In Token Sequence Learning Queue Flush (Device Only) */ -+ unsigned hstfrm : 1; /*!< 02 Host Frame Counter Reset (Host Only) */ -+ unsigned hsftrst : 1; /*!< 01 Hclk Soft Reset */ -+ -+ unsigned csftrst : 1; /*!< 00 Core Soft Reset -+ The application can flush the control logic in the -+ entire core using this bit. This bit resets the -+ pipelines in the AHB Clock domain as well as the -+ PHY Clock domain. -+ The state machines are reset to an IDLE state, the -+ control bits in the CSRs are cleared, all the -+ transmit FIFOs and the receive FIFO are flushed. -+ The status mask bits that control the generation of -+ the interrupt, are cleared, to clear the -+ interrupt. The interrupt status bits are not -+ cleared, so the application can get the status of -+ any events that occurred in the core after it has -+ set this bit. -+ Any transactions on the AHB are terminated as soon -+ as possible following the protocol. Any -+ transactions on the USB are terminated immediately. -+ The configuration settings in the CSRs are -+ unchanged, so the software doesn't have to -+ reprogram these registers (Device -+ Configuration/Host Configuration/Core System -+ Configuration/Core PHY Configuration). -+ The application can write to this bit, any time it -+ wants to reset the core. This is a self clearing -+ bit and the core clears this bit after all the -+ necessary logic is reset in the core, which may -+ take several clocks, depending on the current state -+ of the core. -+ */ -+ }b; -+} grstctl_t; -+ -+/*! -+ \brief Bit fields of the Core Interrupt Mask Register (GINTMSK) and -+ Core Interrupt Register (GINTSTS). -+ */ -+typedef union gint_data -+{ -+ uint32_t d32; -+ #define IFXUSB_SOF_INTR_MASK 0x0008 -+ struct -+ { -+ unsigned wkupintr : 1; /*!< 31 Resume/Remote Wakeup Detected Interrupt */ -+ unsigned sessreqintr : 1; /*!< 30 Session Request/New Session Detected Interrupt */ -+ unsigned disconnect : 1; /*!< 29 Disconnect Detected Interrupt */ -+ unsigned conidstschng : 1; /*!< 28 Connector ID Status Change */ -+ unsigned reserved27 : 1; -+ unsigned ptxfempty : 1; /*!< 26 Periodic TxFIFO Empty */ -+ unsigned hcintr : 1; /*!< 25 Host Channels Interrupt */ -+ unsigned portintr : 1; /*!< 24 Host Port Interrupt */ -+ unsigned reserved23 : 1; -+ unsigned fetsuspmsk : 1; /*!< 22 Data Fetch Suspended */ -+ unsigned incomplisoout : 1; /*!< 21 Incomplete IsochronousOUT/Period Transfer */ -+ unsigned incomplisoin : 1; /*!< 20 Incomplete Isochronous IN Transfer */ -+ unsigned outepintr : 1; /*!< 19 OUT Endpoints Interrupt */ -+ unsigned inepintr : 1; /*!< 18 IN Endpoints Interrupt */ -+ unsigned epmismatch : 1; /*!< 17 Endpoint Mismatch Interrupt */ -+ unsigned reserved16 : 1; -+ unsigned eopframe : 1; /*!< 15 End of Periodic Frame Interrupt */ -+ unsigned isooutdrop : 1; /*!< 14 Isochronous OUT Packet Dropped Interrupt */ -+ unsigned enumdone : 1; /*!< 13 Enumeration Done */ -+ unsigned usbreset : 1; /*!< 12 USB Reset */ -+ unsigned usbsuspend : 1; /*!< 11 USB Suspend */ -+ unsigned erlysuspend : 1; /*!< 10 Early Suspend */ -+ unsigned i2cintr : 1; /*!< 09 I2C Interrupt */ -+ unsigned reserved8 : 1; -+ unsigned goutnakeff : 1; /*!< 07 Global OUT NAK Effective */ -+ unsigned ginnakeff : 1; /*!< 06 Global Non-periodic IN NAK Effective */ -+ unsigned nptxfempty : 1; /*!< 05 Non-periodic TxFIFO Empty */ -+ unsigned rxstsqlvl : 1; /*!< 04 Receive FIFO Non-Empty */ -+ unsigned sofintr : 1; /*!< 03 Start of (u)Frame */ -+ unsigned otgintr : 1; /*!< 02 OTG Interrupt */ -+ unsigned modemismatch : 1; /*!< 01 Mode Mismatch Interrupt */ -+ unsigned reserved0 : 1; -+ } b; -+} gint_data_t; -+ -+/*! -+ \brief Bit fields in the Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) -+ */ -+typedef union grxsts_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned reserved : 7; -+ unsigned fn : 4; /*!< 24-21 Frame Number */ -+ unsigned pktsts : 4; /*!< 20-17 Packet Status */ -+ #define IFXUSB_DSTS_DATA_UPDT 0x2 // OUT Data Packet -+ #define IFXUSB_DSTS_XFER_COMP 0x3 // OUT Data Transfer Complete -+ #define IFXUSB_DSTS_GOUT_NAK 0x1 // Global OUT NAK -+ #define IFXUSB_DSTS_SETUP_COMP 0x4 // Setup Phase Complete -+ #define IFXUSB_DSTS_SETUP_UPDT 0x6 // SETUP Packet -+ unsigned dpid : 2; /*!< 16-15 Data PID */ -+ unsigned bcnt :11; /*!< 14-04 Byte Count */ -+ unsigned epnum : 4; /*!< 03-00 Endpoint Number */ -+ } db; -+ struct -+ { -+ unsigned reserved :11; -+ unsigned pktsts : 4; /*!< 20-17 Packet Status */ -+ #define IFXUSB_HSTS_DATA_UPDT 0x2 // OUT Data Packet -+ #define IFXUSB_HSTS_XFER_COMP 0x3 // OUT Data Transfer Complete -+ #define IFXUSB_HSTS_DATA_TOGGLE_ERR 0x5 // DATA TOGGLE Error -+ #define IFXUSB_HSTS_CH_HALTED 0x7 // Channel Halted -+ unsigned dpid : 2; /*!< 16-15 Data PID */ -+ unsigned bcnt :11; /*!< 14-04 Byte Count */ -+ unsigned chnum : 4; /*!< 03-00 Channel Number */ -+ } hb; -+} grxsts_data_t; -+ -+/*! -+ \brief Bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn). -+ */ -+typedef union fifosize_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned depth : 16; /*!< 31-16 TxFIFO Depth (in DWord)*/ -+ unsigned startaddr : 16; /*!< 15-00 RAM Starting address */ -+ } b; -+} fifosize_data_t; -+ -+/*! -+ \brief Bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS). -+ */ -+ -+typedef union gnptxsts_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned reserved : 1; -+ unsigned nptxqtop_chnep : 4; /*!< 30-27 Channel/EP Number of top of the Non-Periodic -+ Transmit Request Queue -+ */ -+ unsigned nptxqtop_token : 2; /*!< 26-25 Token Type top of the Non-Periodic -+ Transmit Request Queue -+ 0 - IN/OUT -+ 1 - Zero Length OUT -+ 2 - PING/Complete Split -+ 3 - Channel Halt -+ */ -+ unsigned nptxqtop_terminate : 1; /*!< 24 Terminate (Last entry for the selected -+ channel/EP)*/ -+ unsigned nptxqspcavail : 8; /*!< 23-16 Transmit Request Queue Space Available */ -+ unsigned nptxfspcavail :16; /*!< 15-00 TxFIFO Space Avail (in DWord)*/ -+ }b; -+} gnptxsts_data_t; -+ -+ -+/*! -+ \brief Bit fields in the Transmit FIFO Status Register (DTXFSTS). -+ */ -+typedef union dtxfsts_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned reserved : 16; -+ unsigned txfspcavail : 16; /*!< 15-00 TxFIFO Space Avail (in DWord)*/ -+ }b; -+} dtxfsts_data_t; -+ -+ -+/*! -+ \brief Bit fields in the I2C Control Register (I2CCTL). -+ */ -+typedef union gi2cctl_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned bsydne : 1; /*!< 31 I2C Busy/Done*/ -+ unsigned rw : 1; /*!< 30 Read/Write Indicator */ -+ unsigned reserved : 2; -+ unsigned i2cdevaddr : 2; /*!< 27-26 I2C Device Address */ -+ unsigned i2csuspctl : 1; /*!< 25 I2C Suspend Control */ -+ unsigned ack : 1; /*!< 24 I2C ACK */ -+ unsigned i2cen : 1; /*!< 23 I2C Enable */ -+ unsigned addr : 7; /*!< 22-16 I2C Address */ -+ unsigned regaddr : 8; /*!< 15-08 I2C Register Addr */ -+ unsigned rwdata : 8; /*!< I2C Read/Write Data */ -+ } b; -+} gi2cctl_data_t; -+ -+ -+/*! -+ \brief Bit fields in the User HW Config1 Register. -+ */ -+typedef union hwcfg1_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned ep_dir15 : 2; /*!< Direction of each EP -+ 0: BIDIR (IN and OUT) endpoint -+ 1: IN endpoint -+ 2: OUT endpoint -+ 3: Reserved -+ */ -+ unsigned ep_dir14 : 2; -+ unsigned ep_dir13 : 2; -+ unsigned ep_dir12 : 2; -+ unsigned ep_dir11 : 2; -+ unsigned ep_dir10 : 2; -+ unsigned ep_dir09 : 2; -+ unsigned ep_dir08 : 2; -+ unsigned ep_dir07 : 2; -+ unsigned ep_dir06 : 2; -+ unsigned ep_dir05 : 2; -+ unsigned ep_dir04 : 2; -+ unsigned ep_dir03 : 2; -+ unsigned ep_dir02 : 2; -+ unsigned ep_dir01 : 2; -+ unsigned ep_dir00 : 2; -+ }b; -+} hwcfg1_data_t; -+ -+/*! -+ \brief Bit fields in the User HW Config2 Register. -+ */ -+typedef union hwcfg2_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned reserved31 : 1; -+ unsigned dev_token_q_depth : 5; /*!< 30-26 Device Mode IN Token Sequence Learning Queue Depth */ -+ unsigned host_perio_tx_q_depth : 2; /*!< 25-24 Host Mode Periodic Request Queue Depth */ -+ unsigned nonperio_tx_q_depth : 2; /*!< 23-22 Non-periodic Request Queue Depth */ -+ unsigned rx_status_q_depth : 2; /*!< 21-20 Multi Processor Interrupt Enabled */ -+ unsigned dynamic_fifo : 1; /*!< 19 Dynamic FIFO Sizing Enabled */ -+ unsigned perio_ep_supported : 1; /*!< 18 Periodic OUT Channels Supported in Host Mode */ -+ unsigned num_host_chan : 4; /*!< 17-14 Number of Host Channels */ -+ unsigned num_dev_ep : 4; /*!< 13-10 Number of Device Endpoints */ -+ unsigned fs_phy_type : 2; /*!< 09-08 Full-Speed PHY Interface Type */ -+ #define IFXUSB_HWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0 -+ #define IFXUSB_HWCFG2_FS_PHY_TYPE_DEDICATE 1 -+ #define IFXUSB_HWCFG2_FS_PHY_TYPE_UTMI 2 -+ #define IFXUSB_HWCFG2_FS_PHY_TYPE_ULPI 3 -+ unsigned hs_phy_type : 2; /*!< 07-06 High-Speed PHY Interface Type */ -+ #define IFXUSB_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 -+ #define IFXUSB_HWCFG2_HS_PHY_TYPE_UTMI 1 -+ #define IFXUSB_HWCFG2_HS_PHY_TYPE_ULPI 2 -+ #define IFXUSB_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 -+ unsigned point2point : 1; /*!< 05 Point-to-Point */ -+ unsigned architecture : 2; /*!< 04-03 Architecture */ -+ #define IFXUSB_HWCFG2_ARCH_SLAVE_ONLY 0 -+ #define IFXUSB_HWCFG2_ARCH_EXT_DMA 1 -+ #define IFXUSB_HWCFG2_ARCH_INT_DMA 2 -+ unsigned op_mode : 3; /*!< 02-00 Mode of Operation */ -+ #define IFXUSB_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0 -+ #define IFXUSB_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1 -+ #define IFXUSB_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2 -+ #define IFXUSB_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 -+ #define IFXUSB_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 -+ #define IFXUSB_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 -+ #define IFXUSB_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 -+ } b; -+} hwcfg2_data_t; -+ -+/*! -+ \brief Bit fields in the User HW Config3 Register. -+ */ -+typedef union hwcfg3_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned dfifo_depth :16; /*!< 31-16 DFIFO Depth */ -+ unsigned reserved15_12 : 4; -+ unsigned synch_reset_type : 1; /*!< 11 Reset Style for Clocked always Blocks in RTL */ -+ unsigned optional_features : 1; /*!< 10 Optional Features Removed */ -+ unsigned vendor_ctrl_if : 1; /*!< 09 Vendor Control Interface Support */ -+ unsigned i2c : 1; /*!< 08 I2C Selection */ -+ unsigned otg_func : 1; /*!< 07 OTG Function Enabled */ -+ unsigned packet_size_cntr_width : 3; /*!< 06-04 Width of Packet Size Counters */ -+ unsigned xfer_size_cntr_width : 4; /*!< 03-00 Width of Transfer Size Counters */ -+ } b; -+} hwcfg3_data_t; -+ -+/*! -+ \brief Bit fields in the User HW Config4 -+ * Register. Read the register into the d32 element then read -+ * out the bits using the bit elements. -+ */ -+typedef union hwcfg4_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned desc_dma_dyn : 1; /*!< 31 Scatter/Gather DMA */ -+ unsigned desc_dma : 1; /*!< 30 Scatter/Gather DMA configuration */ -+ unsigned num_in_eps : 4; /*!< 29-26 Number of Device Mode IN Endpoints Including Control Endpoints */ -+ unsigned ded_fifo_en : 1; /*!< 25 Enable Dedicated Transmit FIFO for device IN Endpoints */ -+ unsigned session_end_filt_en : 1; /*!< 24 session_end Filter Enabled */ -+ unsigned b_valid_filt_en : 1; /*!< 23 b_valid Filter Enabled */ -+ unsigned a_valid_filt_en : 1; /*!< 22 a_valid Filter Enabled */ -+ unsigned vbus_valid_filt_en : 1; /*!< 21 vbus_valid Filter Enabled */ -+ unsigned iddig_filt_en : 1; /*!< 20 iddig Filter Enable */ -+ unsigned num_dev_mode_ctrl_ep : 4; /*!< 19-16 Number of Device Mode Control Endpoints in Addition to Endpoint 0 */ -+ unsigned utmi_phy_data_width : 2; /*!< 15-14 UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width */ -+ unsigned reserved13_06 : 8; -+ unsigned min_ahb_freq : 1; /*!< 05 Minimum AHB Frequency Less Than 60 MHz */ -+ unsigned power_optimiz : 1; /*!< 04 Enable Power Optimization? */ -+ unsigned num_dev_perio_in_ep : 4; /*!< 03-00 Number of Device Mode Periodic IN Endpoints */ -+ } b; -+} hwcfg4_data_t; -+ -+/*@}*//*IFXUSB_CSR_CORE_GLOBAL_REG*/ -+ -+/****************************************************************************/ -+/*! -+ \addtogroup IFXUSB_CSR_DEVICE_GLOBAL_REG -+ */ -+/*@{*/ -+ -+/*! -+ \struct ifxusb_dev_global_regs -+ \brief IFXUSB Device Mode Global registers. Offsets 800h-BFFh -+ The ifxusb_dev_global_regs structure defines the size -+ and relative field offsets for the Device Global registers. -+ These registers are visible only in Device mode and must not be -+ accessed in Host mode, as the results are unknown. -+ */ -+typedef struct ifxusb_dev_global_regs -+{ -+ volatile uint32_t dcfg; /*!< 800h Device Configuration Register. */ -+ volatile uint32_t dctl; /*!< 804h Device Control Register. */ -+ volatile uint32_t dsts; /*!< 808h Device Status Register (Read Only). */ -+ uint32_t unused; -+ volatile uint32_t diepmsk; /*!< 810h Device IN Endpoint Common Interrupt Mask Register. */ -+ volatile uint32_t doepmsk; /*!< 814h Device OUT Endpoint Common Interrupt Mask Register. */ -+ volatile uint32_t daint; /*!< 818h Device All Endpoints Interrupt Register. */ -+ volatile uint32_t daintmsk; /*!< 81Ch Device All Endpoints Interrupt Mask Register. */ -+ volatile uint32_t dtknqr1; /*!< 820h Device IN Token Queue Read Register-1 (Read Only). */ -+ volatile uint32_t dtknqr2; /*!< 824h Device IN Token Queue Read Register-2 (Read Only). */ -+ volatile uint32_t dvbusdis; /*!< 828h Device VBUS discharge Register.*/ -+ volatile uint32_t dvbuspulse; /*!< 82Ch Device VBUS Pulse Register. */ -+ volatile uint32_t dtknqr3_dthrctl; /*!< 830h Device IN Token Queue Read Register-3 (Read Only). -+ Device Thresholding control register (Read/Write) -+ */ -+ volatile uint32_t dtknqr4_fifoemptymsk; /*!< 834h Device IN Token Queue Read Register-4 (Read Only). -+ Device IN EPs empty Inr. Mask Register (Read/Write) -+ */ -+} ifxusb_device_global_regs_t; -+ -+/*! -+ \brief Bit fields in the Device Configuration Register. -+ */ -+ -+typedef union dcfg_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned reserved31_26 : 6; -+ unsigned perschintvl : 2; /*!< 25-24 Periodic Scheduling Interval */ -+ unsigned descdma : 1; /*!< 23 Enable Descriptor DMA in Device mode */ -+ unsigned epmscnt : 5; /*!< 22-18 In Endpoint Mis-match count */ -+ unsigned reserved13_17 : 5; -+ unsigned perfrint : 2; /*!< 12-11 Periodic Frame Interval */ -+ #define IFXUSB_DCFG_FRAME_INTERVAL_80 0 -+ #define IFXUSB_DCFG_FRAME_INTERVAL_85 1 -+ #define IFXUSB_DCFG_FRAME_INTERVAL_90 2 -+ #define IFXUSB_DCFG_FRAME_INTERVAL_95 3 -+ unsigned devaddr : 7; /*!< 10-04 Device Addresses */ -+ unsigned reserved3 : 1; -+ unsigned nzstsouthshk : 1; /*!< 02 Non Zero Length Status OUT Handshake */ -+ #define IFXUSB_DCFG_SEND_STALL 1 -+ unsigned devspd : 2; /*!< 01-00 Device Speed */ -+ } b; -+} dcfg_data_t; -+ -+/*! -+ \brief Bit fields in the Device Control Register. -+ */ -+typedef union dctl_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned reserved16_31 :16; -+ unsigned ifrmnum : 1; /*!< 15 Ignore Frame Number for ISOC EPs */ -+ unsigned gmc : 2; /*!< 14-13 Global Multi Count */ -+ unsigned gcontbna : 1; /*!< 12 Global Continue on BNA */ -+ unsigned pwronprgdone : 1; /*!< 11 Power-On Programming Done */ -+ unsigned cgoutnak : 1; /*!< 10 Clear Global OUT NAK */ -+ unsigned sgoutnak : 1; /*!< 09 Set Global OUT NAK */ -+ unsigned cgnpinnak : 1; /*!< 08 Clear Global Non-Periodic IN NAK */ -+ unsigned sgnpinnak : 1; /*!< 07 Set Global Non-Periodic IN NAK */ -+ unsigned tstctl : 3; /*!< 06-04 Test Control */ -+ unsigned goutnaksts : 1; /*!< 03 Global OUT NAK Status */ -+ unsigned gnpinnaksts : 1; /*!< 02 Global Non-Periodic IN NAK Status */ -+ unsigned sftdiscon : 1; /*!< 01 Soft Disconnect */ -+ unsigned rmtwkupsig : 1; /*!< 00 Remote Wakeup */ -+ } b; -+} dctl_data_t; -+ -+ -+/*! -+ \brief Bit fields in the Device Status Register. -+ */ -+typedef union dsts_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned reserved22_31 :10; -+ unsigned soffn :14; /*!< 21-08 Frame or Microframe Number of the received SOF */ -+ unsigned reserved4_7 : 4; -+ unsigned errticerr : 1; /*!< 03 Erratic Error */ -+ unsigned enumspd : 2; /*!< 02-01 Enumerated Speed */ -+ #define IFXUSB_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 -+ #define IFXUSB_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 -+ #define IFXUSB_DSTS_ENUMSPD_LS_PHY_6MHZ 2 -+ #define IFXUSB_DSTS_ENUMSPD_FS_PHY_48MHZ 3 -+ unsigned suspsts : 1; /*!< 00 Suspend Status */ -+ } b; -+} dsts_data_t; -+ -+/*! -+ \brief Bit fields in the Device IN EP Interrupt Register -+ and the Device IN EP Common Mask Register. -+ */ -+typedef union diepint_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned reserved14_31 :18; -+ unsigned nakmsk : 1; /*!< 13 NAK interrupt Mask */ -+ unsigned reserved10_12 : 3; -+ unsigned bna : 1; /*!< 09 BNA Interrupt mask */ -+ unsigned txfifoundrn : 1; /*!< 08 Fifo Underrun Mask */ -+ unsigned emptyintr : 1; /*!< 07 IN Endpoint HAK Effective mask */ -+ unsigned inepnakeff : 1; /*!< 06 IN Endpoint HAK Effective mask */ -+ unsigned intknepmis : 1; /*!< 05 IN Token Received with EP mismatch mask */ -+ unsigned intktxfemp : 1; /*!< 04 IN Token received with TxF Empty mask */ -+ unsigned timeout : 1; /*!< 03 TimeOUT Handshake mask (non-ISOC EPs) */ -+ unsigned ahberr : 1; /*!< 02 AHB Error mask */ -+ unsigned epdisabled : 1; /*!< 01 Endpoint disable mask */ -+ unsigned xfercompl : 1; /*!< 00 Transfer complete mask */ -+ } b; -+} diepint_data_t; -+ -+ -+/*! -+ \brief Bit fields in the Device OUT EP Interrupt Register and -+ Device OUT EP Common Interrupt Mask Register. -+ */ -+typedef union doepint_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned reserved15_31 :17; -+ unsigned nyetmsk : 1; /*!< 14 NYET Interrupt */ -+ unsigned nakmsk : 1; /*!< 13 NAK Interrupt */ -+ unsigned bbleerrmsk : 1; /*!< 12 Babble Interrupt */ -+ unsigned reserved10_11 : 2; -+ unsigned bna : 1; /*!< 09 BNA Interrupt */ -+ unsigned outpkterr : 1; /*!< 08 OUT packet Error */ -+ unsigned reserved07 : 1; -+ unsigned back2backsetup : 1; /*!< 06 Back-to-Back SETUP Packets Received */ -+ unsigned stsphsercvd : 1; /*!< 05 */ -+ unsigned outtknepdis : 1; /*!< 04 OUT Token Received when Endpoint Disabled */ -+ unsigned setup : 1; /*!< 03 Setup Phase Done (contorl EPs) */ -+ unsigned ahberr : 1; /*!< 02 AHB Error */ -+ unsigned epdisabled : 1; /*!< 01 Endpoint disable */ -+ unsigned xfercompl : 1; /*!< 00 Transfer complete */ -+ } b; -+} doepint_data_t; -+ -+ -+/*! -+ \brief Bit fields in the Device All EP Interrupt Registers. -+ */ -+typedef union daint_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned out : 16; /*!< 31-16 OUT Endpoint bits */ -+ unsigned in : 16; /*!< 15-00 IN Endpoint bits */ -+ } eps; -+ struct -+ { -+ /** OUT Endpoint bits */ -+ unsigned outep15 : 1; -+ unsigned outep14 : 1; -+ unsigned outep13 : 1; -+ unsigned outep12 : 1; -+ unsigned outep11 : 1; -+ unsigned outep10 : 1; -+ unsigned outep09 : 1; -+ unsigned outep08 : 1; -+ unsigned outep07 : 1; -+ unsigned outep06 : 1; -+ unsigned outep05 : 1; -+ unsigned outep04 : 1; -+ unsigned outep03 : 1; -+ unsigned outep02 : 1; -+ unsigned outep01 : 1; -+ unsigned outep00 : 1; -+ /** IN Endpoint bits */ -+ unsigned inep15 : 1; -+ unsigned inep14 : 1; -+ unsigned inep13 : 1; -+ unsigned inep12 : 1; -+ unsigned inep11 : 1; -+ unsigned inep10 : 1; -+ unsigned inep09 : 1; -+ unsigned inep08 : 1; -+ unsigned inep07 : 1; -+ unsigned inep06 : 1; -+ unsigned inep05 : 1; -+ unsigned inep04 : 1; -+ unsigned inep03 : 1; -+ unsigned inep02 : 1; -+ unsigned inep01 : 1; -+ unsigned inep00 : 1; -+ } ep; -+} daint_data_t; -+ -+ -+/*! -+ \brief Bit fields in the Device IN Token Queue Read Registers. -+ */ -+typedef union dtknq1_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned epnums0_5 :24; /*!< 31-08 EP Numbers of IN Tokens 0 ... 4 */ -+ unsigned wrap_bit : 1; /*!< 07 write pointer has wrapped */ -+ unsigned reserved05_06 : 2; -+ unsigned intknwptr : 5; /*!< 04-00 In Token Queue Write Pointer */ -+ }b; -+} dtknq1_data_t; -+ -+ -+/*! -+ \brief Bit fields in Threshold control Register -+ */ -+typedef union dthrctl_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned reserved26_31 : 6; -+ unsigned rx_thr_len : 9; /*!< 25-17 Rx Thr. Length */ -+ unsigned rx_thr_en : 1; /*!< 16 Rx Thr. Enable */ -+ unsigned reserved11_15 : 5; -+ unsigned tx_thr_len : 9; /*!< 10-02 Tx Thr. Length */ -+ unsigned iso_thr_en : 1; /*!< 01 ISO Tx Thr. Enable */ -+ unsigned non_iso_thr_en : 1; /*!< 00 non ISO Tx Thr. Enable */ -+ } b; -+} dthrctl_data_t; -+ -+/*@}*//*IFXUSB_CSR_DEVICE_GLOBAL_REG*/ -+ -+/****************************************************************************/ -+ -+/*! -+ \addtogroup IFXUSB_CSR_DEVICE_EP_REG -+ */ -+/*@{*/ -+ -+/*! -+ \struct ifxusb_dev_in_ep_regs -+ \brief Device Logical IN Endpoint-Specific Registers. -+ There will be one set of endpoint registers per logical endpoint -+ implemented. -+ each EP's IN EP Register are offset at : -+ 900h + * (ep_num * 20h) -+ */ -+ -+typedef struct ifxusb_dev_in_ep_regs -+{ -+ volatile uint32_t diepctl; /*!< 00h: Endpoint Control Register */ -+ uint32_t reserved04; /*!< 04h: */ -+ volatile uint32_t diepint; /*!< 08h: Endpoint Interrupt Register */ -+ uint32_t reserved0C; /*!< 0Ch: */ -+ volatile uint32_t dieptsiz; /*!< 10h: Endpoint Transfer Size Register.*/ -+ volatile uint32_t diepdma; /*!< 14h: Endpoint DMA Address Register. */ -+ volatile uint32_t dtxfsts; /*!< 18h: Endpoint Transmit FIFO Status Register. */ -+ volatile uint32_t diepdmab; /*!< 1Ch: Endpoint DMA Buffer Register. */ -+} ifxusb_dev_in_ep_regs_t; -+ -+/*! -+ \brief Device Logical OUT Endpoint-Specific Registers. -+ There will be one set of endpoint registers per logical endpoint -+ implemented. -+ each EP's OUT EP Register are offset at : -+ B00h + * (ep_num * 20h) + 00h -+ */ -+typedef struct ifxusb_dev_out_ep_regs -+{ -+ volatile uint32_t doepctl; /*!< 00h: Endpoint Control Register */ -+ volatile uint32_t doepfn; /*!< 04h: Endpoint Frame number Register */ -+ volatile uint32_t doepint; /*!< 08h: Endpoint Interrupt Register */ -+ uint32_t reserved0C; /*!< 0Ch: */ -+ volatile uint32_t doeptsiz; /*!< 10h: Endpoint Transfer Size Register.*/ -+ volatile uint32_t doepdma; /*!< 14h: Endpoint DMA Address Register. */ -+ uint32_t reserved18; /*!< 18h: */ -+ volatile uint32_t doepdmab; /*!< 1Ch: Endpoint DMA Buffer Register. */ -+} ifxusb_dev_out_ep_regs_t; -+ -+ -+/*! -+ \brief Bit fields in the Device EP Control -+ Register. -+ */ -+typedef union depctl_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned epena : 1; /*!< 31 Endpoint Enable */ -+ unsigned epdis : 1; /*!< 30 Endpoint Disable */ -+ unsigned setd1pid : 1; /*!< 29 Set DATA1 PID (INTR/Bulk IN and OUT endpoints) */ -+ unsigned setd0pid : 1; /*!< 28 Set DATA0 PID (INTR/Bulk IN and OUT endpoints) */ -+ unsigned snak : 1; /*!< 27 Set NAK */ -+ unsigned cnak : 1; /*!< 26 Clear NAK */ -+ unsigned txfnum : 4; /*!< 25-22 Tx Fifo Number */ -+ unsigned stall : 1; /*!< 21 Stall Handshake */ -+ unsigned snp : 1; /*!< 20 Snoop Mode */ -+ unsigned eptype : 2; /*!< 19-18 Endpoint Type -+ 0: Control -+ 1: Isochronous -+ 2: Bulk -+ 3: Interrupt -+ */ -+ unsigned naksts : 1; /*!< 17 NAK Status */ -+ unsigned dpid : 1; /*!< 16 Endpoint DPID (INTR/Bulk IN and OUT endpoints) */ -+ unsigned usbactep : 1; /*!< 15 USB Active Endpoint */ -+ unsigned nextep : 4; /*!< 14-11 Next Endpoint */ -+ unsigned mps :11; /*!< 10-00 Maximum Packet Size */ -+ #define IFXUSB_DEP0CTL_MPS_64 0 -+ #define IFXUSB_DEP0CTL_MPS_32 1 -+ #define IFXUSB_DEP0CTL_MPS_16 2 -+ #define IFXUSB_DEP0CTL_MPS_8 3 -+ } b; -+} depctl_data_t; -+ -+ -+/*! -+ \brief Bit fields in the Device EP Transfer Size Register. (EP0 and EPn) -+ */ -+typedef union deptsiz_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned reserved31 : 1; -+ unsigned supcnt : 2; /*!< 30-29 Setup Packet Count */ -+ unsigned reserved20_28 : 9; -+ unsigned pktcnt : 1; /*!< 19 Packet Count */ -+ unsigned reserved7_18 :12; -+ unsigned xfersize : 7; /*!< 06-00 Transfer size */ -+ }b0; -+ struct -+ { -+ unsigned reserved : 1; -+ unsigned mc : 2; /*!< 30-29 Multi Count */ -+ unsigned pktcnt :10; /*!< 28-19 Packet Count */ -+ unsigned xfersize :19; /*!< 18-00 Transfer size */ -+ } b; -+} deptsiz_data_t; -+ -+/*@}*//*IFXUSB_CSR_DEVICE_EP_REG*/ -+/****************************************************************************/ -+ -+/*! -+ \addtogroup IFXUSB_CSR_DEVICE_DMA_DESC -+ */ -+/*@{*/ -+/*! -+ \struct desc_sts_data -+ \brief Bit fields in the DMA Descriptor status quadlet. -+ */ -+typedef union desc_sts_data -+{ -+ struct -+ { -+ unsigned bs : 2; /*!< 31-30 Buffer Status */ -+ #define BS_HOST_READY 0x0 -+ #define BS_DMA_BUSY 0x1 -+ #define BS_DMA_DONE 0x2 -+ #define BS_HOST_BUSY 0x3 -+ unsigned sts : 2; /*!< 29-28 Receive/Trasmit Status */ -+ #define RTS_SUCCESS 0x0 -+ #define RTS_BUFFLUSH 0x1 -+ #define RTS_RESERVED 0x2 -+ #define RTS_BUFERR 0x3 -+ unsigned l : 1; /*!< 27 Last */ -+ unsigned sp : 1; /*!< 26 Short Packet */ -+ unsigned ioc : 1; /*!< 25 Interrupt On Complete */ -+ unsigned sr : 1; /*!< 24 Setup Packet received */ -+ unsigned mtrf : 1; /*!< 23 Multiple Transfer */ -+ unsigned reserved16_22 : 7; -+ unsigned bytes :16; /*!< 15-00 Transfer size in bytes */ -+ } b; -+ uint32_t d32; /*!< DMA Descriptor data buffer pointer */ -+} desc_sts_data_t; -+ -+/*@}*//*IFXUSB_CSR_DEVICE_DMA_DESC*/ -+/****************************************************************************/ -+ -+/*! -+ \addtogroup IFXUSB_CSR_HOST_GLOBAL_REG -+ */ -+/*@{*/ -+/*! -+ \struct ifxusb_host_global_regs -+ \brief IFXUSB Host Mode Global registers. Offsets 400h-7FFh -+ The ifxusb_host_global_regs structure defines the size -+ and relative field offsets for the Host Global registers. -+ These registers are visible only in Host mode and must not be -+ accessed in Device mode, as the results are unknown. -+ */ -+typedef struct ifxusb_host_global_regs -+{ -+ volatile uint32_t hcfg; /*!< 400h Host Configuration Register. */ -+ volatile uint32_t hfir; /*!< 404h Host Frame Interval Register. */ -+ volatile uint32_t hfnum; /*!< 408h Host Frame Number / Frame Remaining Register. */ -+ uint32_t reserved40C; -+ volatile uint32_t hptxsts; /*!< 410h Host Periodic Transmit FIFO/ Queue Status Register. */ -+ volatile uint32_t haint; /*!< 414h Host All Channels Interrupt Register. */ -+ volatile uint32_t haintmsk; /*!< 418h Host All Channels Interrupt Mask Register. */ -+} ifxusb_host_global_regs_t; -+ -+/*! -+ \brief Bit fields in the Host Configuration Register. -+ */ -+typedef union hcfg_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned reserved31_03 :29; -+ unsigned fslssupp : 1; /*!< 02 FS/LS Only Support */ -+ unsigned fslspclksel : 2; /*!< 01-00 FS/LS Phy Clock Select */ -+ #define IFXUSB_HCFG_30_60_MHZ 0 -+ #define IFXUSB_HCFG_48_MHZ 1 -+ #define IFXUSB_HCFG_6_MHZ 2 -+ } b; -+} hcfg_data_t; -+ -+/*! -+ \brief Bit fields in the Host Frame Interval Register. -+ */ -+typedef union hfir_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned reserved : 16; -+ unsigned frint : 16; /*!< 15-00 Frame Interval */ -+ } b; -+} hfir_data_t; -+ -+/*! -+ \brief Bit fields in the Host Frame Time Remaing/Number Register. -+ */ -+typedef union hfnum_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned frrem : 16; /*!< 31-16 Frame Time Remaining */ -+ unsigned frnum : 16; /*!< 15-00 Frame Number*/ -+ #define IFXUSB_HFNUM_MAX_FRNUM 0x3FFF -+ } b; -+} hfnum_data_t; -+ -+/*! -+ \brief Bit fields in the Host Periodic Transmit FIFO/Queue Status Register -+ */ -+typedef union hptxsts_data -+{ -+ /** raw register data */ -+ uint32_t d32; -+ struct -+ { -+ /** Top of the Periodic Transmit Request Queue -+ * - bit 24 - Terminate (last entry for the selected channel) -+ */ -+ unsigned ptxqtop_odd : 1; /*!< 31 Top of the Periodic Transmit Request -+ Queue Odd/even microframe*/ -+ unsigned ptxqtop_chnum : 4; /*!< 30-27 Top of the Periodic Transmit Request -+ Channel Number */ -+ unsigned ptxqtop_token : 2; /*!< 26-25 Top of the Periodic Transmit Request -+ Token Type -+ 0 - Zero length -+ 1 - Ping -+ 2 - Disable -+ */ -+ unsigned ptxqtop_terminate : 1; /*!< 24 Top of the Periodic Transmit Request -+ Terminate (last entry for the selected channel)*/ -+ unsigned ptxqspcavail : 8; /*!< 23-16 Periodic Transmit Request Queue Space Available */ -+ unsigned ptxfspcavail :16; /*!< 15-00 Periodic Transmit Data FIFO Space Available */ -+ } b; -+} hptxsts_data_t; -+ -+/*! -+ \brief Bit fields in the Host Port Control and Status Register. -+ */ -+typedef union hprt0_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned reserved19_31 :13; -+ unsigned prtspd : 2; /*!< 18-17 Port Speed */ -+ #define IFXUSB_HPRT0_PRTSPD_HIGH_SPEED 0 -+ #define IFXUSB_HPRT0_PRTSPD_FULL_SPEED 1 -+ #define IFXUSB_HPRT0_PRTSPD_LOW_SPEED 2 -+ unsigned prttstctl : 4; /*!< 16-13 Port Test Control */ -+ unsigned prtpwr : 1; /*!< 12 Port Power */ -+ unsigned prtlnsts : 2; /*!< 11-10 Port Line Status */ -+ unsigned reserved9 : 1; -+ unsigned prtrst : 1; /*!< 08 Port Reset */ -+ unsigned prtsusp : 1; /*!< 07 Port Suspend */ -+ unsigned prtres : 1; /*!< 06 Port Resume */ -+ unsigned prtovrcurrchng : 1; /*!< 05 Port Overcurrent Change */ -+ unsigned prtovrcurract : 1; /*!< 04 Port Overcurrent Active */ -+ unsigned prtenchng : 1; /*!< 03 Port Enable/Disable Change */ -+ unsigned prtena : 1; /*!< 02 Port Enable */ -+ unsigned prtconndet : 1; /*!< 01 Port Connect Detected */ -+ unsigned prtconnsts : 1; /*!< 00 Port Connect Status */ -+ }b; -+} hprt0_data_t; -+ -+/*! -+ \brief Bit fields in the Host All Interrupt Register. -+ */ -+typedef union haint_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned reserved : 16; -+ unsigned ch15 : 1; -+ unsigned ch14 : 1; -+ unsigned ch13 : 1; -+ unsigned ch12 : 1; -+ unsigned ch11 : 1; -+ unsigned ch10 : 1; -+ unsigned ch09 : 1; -+ unsigned ch08 : 1; -+ unsigned ch07 : 1; -+ unsigned ch06 : 1; -+ unsigned ch05 : 1; -+ unsigned ch04 : 1; -+ unsigned ch03 : 1; -+ unsigned ch02 : 1; -+ unsigned ch01 : 1; -+ unsigned ch00 : 1; -+ } b; -+ struct -+ { -+ unsigned reserved : 16; -+ unsigned chint : 16; -+ } b2; -+} haint_data_t; -+/*@}*//*IFXUSB_CSR_HOST_GLOBAL_REG*/ -+/****************************************************************************/ -+/*! -+ \addtogroup IFXUSB_CSR_HOST_HC_REG -+ */ -+/*@{*/ -+/*! -+ \brief Host Channel Specific Registers -+ There will be one set of hc registers per host channelimplemented. -+ each HC's Register are offset at : -+ 500h + * (hc_num * 20h) -+ */ -+typedef struct ifxusb_hc_regs -+{ -+ volatile uint32_t hcchar; /*!< 00h Host Channel Characteristic Register.*/ -+ volatile uint32_t hcsplt; /*!< 04h Host Channel Split Control Register.*/ -+ volatile uint32_t hcint; /*!< 08h Host Channel Interrupt Register. */ -+ volatile uint32_t hcintmsk; /*!< 0Ch Host Channel Interrupt Mask Register. */ -+ volatile uint32_t hctsiz; /*!< 10h Host Channel Transfer Size Register. */ -+ volatile uint32_t hcdma; /*!< 14h Host Channel DMA Address Register. */ -+ uint32_t reserved[2]; /*!< 18h Reserved. */ -+} ifxusb_hc_regs_t; -+ -+ -+/*! -+ \brief Bit fields in the Host Channel Characteristics Register. -+ */ -+typedef union hcchar_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned chen : 1; /*!< 31 Channel enable */ -+ unsigned chdis : 1; /*!< 30 Channel disable */ -+ unsigned oddfrm : 1; /*!< 29 Frame to transmit periodic transaction */ -+ unsigned devaddr : 7; /*!< 28-22 Device address */ -+ unsigned multicnt : 2; /*!< 21-20 Packets per frame for periodic transfers */ -+ unsigned eptype : 2; /*!< 19-18 0: Control, 1: Isoc, 2: Bulk, 3: Intr */ -+ unsigned lspddev : 1; /*!< 17 0: Full/high speed device, 1: Low speed device */ -+ unsigned reserved : 1; -+ unsigned epdir : 1; /*!< 15 0: OUT, 1: IN */ -+ unsigned epnum : 4; /*!< 14-11 Endpoint number */ -+ unsigned mps :11; /*!< 10-00 Maximum packet size in bytes */ -+ } b; -+} hcchar_data_t; -+ -+/*! -+ \brief Bit fields in the Host Channel Split Control Register -+ */ -+typedef union hcsplt_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned spltena : 1; /*!< 31 Split Enble */ -+ unsigned reserved :14; -+ unsigned compsplt : 1; /*!< 16 Do Complete Split */ -+ unsigned xactpos : 2; /*!< 15-14 Transaction Position */ -+ #define IFXUSB_HCSPLIT_XACTPOS_MID 0 -+ #define IFXUSB_HCSPLIT_XACTPOS_END 1 -+ #define IFXUSB_HCSPLIT_XACTPOS_BEGIN 2 -+ #define IFXUSB_HCSPLIT_XACTPOS_ALL 3 -+ unsigned hubaddr : 7; /*!< 13-07 Hub Address */ -+ unsigned prtaddr : 7; /*!< 06-00 Port Address */ -+ } b; -+} hcsplt_data_t; -+ -+/*! -+ \brief Bit fields in the Host Interrupt Register. -+ */ -+typedef union hcint_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned reserved :21; -+ unsigned datatglerr : 1; /*!< 10 Data Toggle Error */ -+ unsigned frmovrun : 1; /*!< 09 Frame Overrun */ -+ unsigned bblerr : 1; /*!< 08 Babble Error */ -+ unsigned xacterr : 1; /*!< 07 Transaction Err */ -+ unsigned nyet : 1; /*!< 06 NYET Response Received */ -+ unsigned ack : 1; /*!< 05 ACK Response Received */ -+ unsigned nak : 1; /*!< 04 NAK Response Received */ -+ unsigned stall : 1; /*!< 03 STALL Response Received */ -+ unsigned ahberr : 1; /*!< 02 AHB Error */ -+ unsigned chhltd : 1; /*!< 01 Channel Halted */ -+ unsigned xfercomp : 1; /*!< 00 Channel Halted */ -+ }b; -+} hcint_data_t; -+ -+ -+/*! -+ \brief Bit fields in the Host Channel Transfer Size -+ Register. -+ */ -+typedef union hctsiz_data -+{ -+ uint32_t d32; -+ struct -+ { -+ /** */ -+ unsigned dopng : 1; /*!< 31 Do PING protocol when 1 */ -+ /** -+ * Packet ID for next data packet -+ * 0: DATA0 -+ * 1: DATA2 -+ * 2: DATA1 -+ * 3: MDATA (non-Control), SETUP (Control) -+ */ -+ unsigned pid : 2; /*!< 30-29 Packet ID for next data packet -+ 0: DATA0 -+ 1: DATA2 -+ 2: DATA1 -+ 3: MDATA (non-Control), SETUP (Control) -+ */ -+ #define IFXUSB_HCTSIZ_DATA0 0 -+ #define IFXUSB_HCTSIZ_DATA1 2 -+ #define IFXUSB_HCTSIZ_DATA2 1 -+ #define IFXUSB_HCTSIZ_MDATA 3 -+ #define IFXUSB_HCTSIZ_SETUP 3 -+ unsigned pktcnt :10; /*!< 28-19 Data packets to transfer */ -+ unsigned xfersize :19; /*!< 18-00 Total transfer size in bytes */ -+ }b; -+} hctsiz_data_t; -+ -+/*@}*//*IFXUSB_CSR_HOST_HC_REG*/ -+ -+/****************************************************************************/ -+ -+/*! -+ \addtogroup IFXUSB_CSR_PWR_CLK_GATING_REG -+ */ -+/*@{*/ -+/*! -+ \brief Bit fields in the Power and Clock Gating Control Register -+ */ -+typedef union pcgcctl_data -+{ -+ uint32_t d32; -+ struct -+ { -+ unsigned reserved : 27; -+ unsigned physuspended : 1; /*!< 04 PHY Suspended */ -+ unsigned rstpdwnmodule : 1; /*!< 03 Reset Power Down Modules */ -+ unsigned pwrclmp : 1; /*!< 02 Power Clamp */ -+ unsigned gatehclk : 1; /*!< 01 Gate Hclk */ -+ unsigned stoppclk : 1; /*!< 00 Stop Pclk */ -+ } b; -+} pcgcctl_data_t; -+/*@}*//*IFXUSB_CSR_PWR_CLK_GATING_REG*/ -+ -+/****************************************************************************/ -+ -+#endif //__IFXUSB_REGS_H__ ---- /dev/null -+++ b/drivers/usb/ifxhcd/ifxusb_version.h -@@ -0,0 +1,5 @@ -+ -+#ifndef IFXUSB_VERSION -+#define IFXUSB_VERSION "3.0alpha B100312" -+#endif -+ diff --git a/target/linux/lantiq/patches-3.3/0047-MIPS-adds-gptu-driver.patch b/target/linux/lantiq/patches-3.3/0047-MIPS-adds-gptu-driver.patch deleted file mode 100644 index fc4af1c01e..0000000000 --- a/target/linux/lantiq/patches-3.3/0047-MIPS-adds-gptu-driver.patch +++ /dev/null @@ -1,189 +0,0 @@ -From 4dd444aa83346f37a2efcb10a2e3c83db2bf4ca5 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Wed, 14 Mar 2012 15:37:19 +0100 -Subject: [PATCH 47/70] MIPS: adds gptu driver - ---- - arch/mips/lantiq/xway/gptu.c | 176 ++++++++++++++++++++++++++++++++++++++++++ - 1 files changed, 176 insertions(+), 0 deletions(-) - create mode 100644 arch/mips/lantiq/xway/gptu.c - ---- /dev/null -+++ b/arch/mips/lantiq/xway/gptu.c -@@ -0,0 +1,176 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2012 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include "../clk.h" -+ -+#include "../devices.h" -+ -+#define ltq_gptu_w32(x, y) ltq_w32((x), ltq_gptu_membase + (y)) -+#define ltq_gptu_r32(x) ltq_r32(ltq_gptu_membase + (x)) -+ -+ -+/* the magic ID byte of the core */ -+#define GPTU_MAGIC 0x59 -+/* clock control register */ -+#define GPTU_CLC 0x00 -+/* id register */ -+#define GPTU_ID 0x08 -+/* interrupt node enable */ -+#define GPTU_IRNEN 0xf4 -+/* interrupt control register */ -+#define GPTU_IRCR 0xf8 -+/* interrupt capture register */ -+#define GPTU_IRNCR 0xfc -+/* there are 3 identical blocks of 2 timers. calculate register offsets */ -+#define GPTU_SHIFT(x) (x % 2 ? 4 : 0) -+#define GPTU_BASE(x) (((x >> 1) * 0x20) + 0x10) -+/* timer control register */ -+#define GPTU_CON(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x00) -+/* timer auto reload register */ -+#define GPTU_RUN(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x08) -+/* timer manual reload register */ -+#define GPTU_RLD(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x10) -+/* timer count register */ -+#define GPTU_CNT(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x18) -+ -+/* GPTU_CON(x) */ -+#define CON_CNT BIT(2) -+#define CON_EDGE_FALL BIT(7) -+#define CON_SYNC BIT(8) -+#define CON_CLK_INT BIT(10) -+ -+/* GPTU_RUN(x) */ -+#define RUN_SEN BIT(0) -+#define RUN_RL BIT(2) -+ -+/* set clock to runmode */ -+#define CLC_RMC BIT(8) -+/* bring core out of suspend */ -+#define CLC_SUSPEND BIT(4) -+/* the disable bit */ -+#define CLC_DISABLE BIT(0) -+ -+#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) -+ -+enum gptu_timer { -+ TIMER1A = 0, -+ TIMER1B, -+ TIMER2A, -+ TIMER2B, -+ TIMER3A, -+ TIMER3B -+}; -+ -+static struct resource ltq_gptu_resource = -+ MEM_RES("GPTU", LTQ_GPTU_BASE_ADDR, LTQ_GPTU_SIZE); -+ -+static void __iomem *ltq_gptu_membase; -+ -+static irqreturn_t timer_irq_handler(int irq, void *priv) -+{ -+ int timer = irq - TIMER_INTERRUPT; -+ ltq_gptu_w32(1 << timer, GPTU_IRNCR); -+ return IRQ_HANDLED; -+} -+ -+static void gptu_hwinit(void) -+{ -+ struct clk *clk = clk_get_sys("ltq_gptu", NULL); -+ clk_enable(clk); -+ ltq_gptu_w32(0x00, GPTU_IRNEN); -+ ltq_gptu_w32(0xff, GPTU_IRNCR); -+ ltq_gptu_w32(CLC_RMC | CLC_SUSPEND, GPTU_CLC); -+} -+ -+static void gptu_hwexit(void) -+{ -+ ltq_gptu_w32(0x00, GPTU_IRNEN); -+ ltq_gptu_w32(0xff, GPTU_IRNCR); -+ ltq_gptu_w32(CLC_DISABLE, GPTU_CLC); -+} -+ -+static int ltq_gptu_enable(struct clk *clk) -+{ -+ int ret = request_irq(TIMER_INTERRUPT + clk->bits, timer_irq_handler, -+ IRQF_TIMER, "timer", NULL); -+ if (ret) { -+ pr_err("gptu: failed to request irq\n"); -+ return ret; -+ } -+ -+ ltq_gptu_w32(CON_CNT | CON_EDGE_FALL | CON_SYNC | CON_CLK_INT, -+ GPTU_CON(clk->bits)); -+ ltq_gptu_w32(1, GPTU_RLD(clk->bits)); -+ ltq_gptu_w32(ltq_gptu_r32(GPTU_IRNEN) | clk->bits, GPTU_IRNEN); -+ ltq_gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits)); -+ return 0; -+} -+ -+static void ltq_gptu_disable(struct clk *clk) -+{ -+ ltq_gptu_w32(0, GPTU_RUN(clk->bits)); -+ ltq_gptu_w32(0, GPTU_CON(clk->bits)); -+ ltq_gptu_w32(0, GPTU_RLD(clk->bits)); -+ ltq_gptu_w32(ltq_gptu_r32(GPTU_IRNEN) & ~clk->bits, GPTU_IRNEN); -+ free_irq(TIMER_INTERRUPT + clk->bits, NULL); -+} -+ -+static inline void clkdev_add_gptu(const char *con, unsigned int timer) -+{ -+ struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); -+ -+ clk->cl.dev_id = "ltq_gptu"; -+ clk->cl.con_id = con; -+ clk->cl.clk = clk; -+ clk->enable = ltq_gptu_enable; -+ clk->disable = ltq_gptu_disable; -+ clk->bits = timer; -+ clkdev_add(&clk->cl); -+} -+ -+static int __init gptu_setup(void) -+{ -+ /* remap gptu register range */ -+ ltq_gptu_membase = ltq_remap_resource(<q_gptu_resource); -+ if (!ltq_gptu_membase) -+ panic("Failed to remap gptu memory"); -+ -+ /* power up the core */ -+ gptu_hwinit(); -+ -+ /* the gptu has a ID register */ -+ if (((ltq_gptu_r32(GPTU_ID) >> 8) & 0xff) != GPTU_MAGIC) { -+ pr_err("gptu: failed to find magic\n"); -+ gptu_hwexit(); -+ return -ENAVAIL; -+ } -+ -+ /* register the clocks */ -+ clkdev_add_gptu("timer1a", TIMER1A); -+ clkdev_add_gptu("timer1b", TIMER1B); -+ clkdev_add_gptu("timer2a", TIMER2A); -+ clkdev_add_gptu("timer2b", TIMER2B); -+ clkdev_add_gptu("timer3a", TIMER3A); -+ clkdev_add_gptu("timer3b", TIMER3B); -+ -+ pr_info("gptu: 6 timers loaded\n"); -+ -+ return 0; -+} -+ -+arch_initcall(gptu_setup); diff --git a/target/linux/lantiq/patches-3.3/0048-MIPS-lantiq-pci-rename-variable-inside.patch b/target/linux/lantiq/patches-3.3/0048-MIPS-lantiq-pci-rename-variable-inside.patch deleted file mode 100644 index ed3974d618..0000000000 --- a/target/linux/lantiq/patches-3.3/0048-MIPS-lantiq-pci-rename-variable-inside.patch +++ /dev/null @@ -1,70 +0,0 @@ -From 202f1bad2707e843dccc0fb08233692f8c845f90 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 8 Mar 2012 12:00:17 +0100 -Subject: [PATCH 48/70] MIPS: lantiq: pci: rename variable inside - -* rename a global var inside the pci code ---- - arch/mips/pci/ops-lantiq.c | 6 +++--- - arch/mips/pci/pci-lantiq.c | 6 +++--- - arch/mips/pci/pci-lantiq.h | 2 +- - 3 files changed, 7 insertions(+), 7 deletions(-) - ---- a/arch/mips/pci/ops-lantiq.c -+++ b/arch/mips/pci/ops-lantiq.c -@@ -41,7 +41,7 @@ static int ltq_pci_config_access(unsigne - - spin_lock_irqsave(&ebu_lock, flags); - -- cfg_base = (unsigned long) ltq_pci_mapped_cfg; -+ cfg_base = (unsigned long) ltq_pci_cfgbase; - cfg_base |= (bus->number << LTQ_PCI_CFG_BUSNUM_SHF) | (devfn << - LTQ_PCI_CFG_FUNNUM_SHF) | (where & ~0x3); - -@@ -55,11 +55,11 @@ static int ltq_pci_config_access(unsigne - wmb(); - - /* clean possible Master abort */ -- cfg_base = (unsigned long) ltq_pci_mapped_cfg; -+ cfg_base = (unsigned long) ltq_pci_cfgbase; - cfg_base |= (0x0 << LTQ_PCI_CFG_FUNNUM_SHF) + 4; - temp = ltq_r32(((u32 *)(cfg_base))); - temp = swab32(temp); -- cfg_base = (unsigned long) ltq_pci_mapped_cfg; -+ cfg_base = (unsigned long) ltq_pci_cfgbase; - cfg_base |= (0x68 << LTQ_PCI_CFG_FUNNUM_SHF) + 4; - ltq_w32(temp, ((u32 *)cfg_base)); - ---- a/arch/mips/pci/pci-lantiq.c -+++ b/arch/mips/pci/pci-lantiq.c -@@ -65,8 +65,8 @@ - #define ltq_pci_w32(x, y) ltq_w32((x), ltq_pci_membase + (y)) - #define ltq_pci_r32(x) ltq_r32(ltq_pci_membase + (x)) - --#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y)) --#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x)) -+#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_cfgbase + (y)) -+#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_cfgbase + (x)) - - struct ltq_pci_gpio_map { - int pin; -@@ -273,7 +273,7 @@ static int __devinit ltq_pci_probe(struc - pci_probe_only = 0; - ltq_pci_irq_map = ltq_pci_data->irq; - ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE); -- ltq_pci_mapped_cfg = -+ ltq_pci_cfgbase = - ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE); - ltq_pci_controller.io_map_base = - (unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1); ---- a/arch/mips/pci/pci-lantiq.h -+++ b/arch/mips/pci/pci-lantiq.h -@@ -9,7 +9,7 @@ - #ifndef _LTQ_PCI_H__ - #define _LTQ_PCI_H__ - --extern __iomem void *ltq_pci_mapped_cfg; -+extern __iomem void *ltq_pci_cfgbase; - extern int ltq_pci_read_config_dword(struct pci_bus *bus, - unsigned int devfn, int where, int size, u32 *val); - extern int ltq_pci_write_config_dword(struct pci_bus *bus, diff --git a/target/linux/lantiq/patches-3.3/0049-MIPS-lantiq-pci-give-xway-pci-support-its-own-kbuild.patch b/target/linux/lantiq/patches-3.3/0049-MIPS-lantiq-pci-give-xway-pci-support-its-own-kbuild.patch deleted file mode 100644 index 3cc71876ff..0000000000 --- a/target/linux/lantiq/patches-3.3/0049-MIPS-lantiq-pci-give-xway-pci-support-its-own-kbuild.patch +++ /dev/null @@ -1,38 +0,0 @@ -From e5ae2eed68a7ccd406bde12ecfc12c88a52aeb06 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 8 Mar 2012 13:13:31 +0100 -Subject: [PATCH 49/70] MIPS: lantiq: pci: give xway pci support its own - kbuild symbol - ---- - arch/mips/lantiq/Kconfig | 5 +++++ - arch/mips/pci/Makefile | 2 +- - 2 files changed, 6 insertions(+), 1 deletions(-) - ---- a/arch/mips/lantiq/Kconfig -+++ b/arch/mips/lantiq/Kconfig -@@ -19,8 +19,13 @@ config SOC_XWAY - - config SOC_FALCON - bool "FALCON" -+ - endchoice - -+config PCI_LANTIQ -+ bool "PCI Support" -+ depends on SOC_XWAY && PCI -+ - source "arch/mips/lantiq/xway/Kconfig" - source "arch/mips/lantiq/falcon/Kconfig" - ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -41,7 +41,7 @@ obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1 - obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o - obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o - obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o --obj-$(CONFIG_SOC_XWAY) += pci-lantiq.o ops-lantiq.o -+obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o - obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o - obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o - obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o diff --git a/target/linux/lantiq/patches-3.3/0050-MIPS-lantiq-pci-move-pcibios-code-into-fixup-lantiq..patch b/target/linux/lantiq/patches-3.3/0050-MIPS-lantiq-pci-move-pcibios-code-into-fixup-lantiq..patch deleted file mode 100644 index c616be5934..0000000000 --- a/target/linux/lantiq/patches-3.3/0050-MIPS-lantiq-pci-move-pcibios-code-into-fixup-lantiq..patch +++ /dev/null @@ -1,121 +0,0 @@ -From a4f83d3f635603b982f11e7f1cb22057958ff52b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 8 Mar 2012 15:53:10 +0100 -Subject: [PATCH 50/70] MIPS: lantiq: pci: move pcibios code into - fixup-lantiq.c - ---- - arch/mips/pci/Makefile | 1 + - arch/mips/pci/fixup-lantiq.c | 42 ++++++++++++++++++++++++++++++++++++++++++ - arch/mips/pci/pci-lantiq.c | 24 ++---------------------- - 3 files changed, 45 insertions(+), 22 deletions(-) - create mode 100644 arch/mips/pci/fixup-lantiq.c - ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1 - obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o - obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o - obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o -+obj-$(CONFIG_LANTIQ) += fixup-lantiq.o - obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o - obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o - obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o ---- /dev/null -+++ b/arch/mips/pci/fixup-lantiq.c -@@ -0,0 +1,42 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2012 John Crispin -+ */ -+ -+#include -+#include -+ -+int (*ltqpci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin) = NULL; -+int (*ltqpci_plat_arch_init)(struct pci_dev *dev) = NULL; -+int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL; -+int *ltq_pci_irq_map; -+ -+int pcibios_plat_dev_init(struct pci_dev *dev) -+{ -+ if (ltqpci_plat_arch_init) -+ return ltqpci_plat_arch_init(dev); -+ -+ if (ltqpci_plat_dev_init) -+ return ltqpci_plat_dev_init(dev); -+ -+ return 0; -+} -+ -+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ if (ltqpci_map_irq) -+ return ltqpci_map_irq(dev, slot, pin); -+ if (ltq_pci_irq_map[slot]) { -+ dev_info(&dev->dev, "SLOT:%d PIN:%d IRQ:%d\n", slot, pin, ltq_pci_irq_map[slot]); -+ return ltq_pci_irq_map[slot]; -+ } -+ printk(KERN_ERR "lq_pci: trying to map irq for unknown slot %d\n", -+ slot); -+ -+ return 0; -+} -+ -+ ---- a/arch/mips/pci/pci-lantiq.c -+++ b/arch/mips/pci/pci-lantiq.c -@@ -93,16 +93,14 @@ static struct ltq_pci_gpio_map ltq_pci_g - { 37, 2, 0, "pci-req4" }, - }; - --__iomem void *ltq_pci_mapped_cfg; -+__iomem void *ltq_pci_cfgbase; - static __iomem void *ltq_pci_membase; - --int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL; -- - /* Since the PCI REQ pins can be reused for other functionality, make it - possible to exclude those from interpretation by the PCI controller */ - static int ltq_pci_req_mask = 0xf; - --static int *ltq_pci_irq_map; -+extern int *ltq_pci_irq_map; - - struct pci_ops ltq_pci_ops = { - .read = ltq_pci_read_config_dword, -@@ -131,14 +129,6 @@ static struct pci_controller ltq_pci_con - .io_offset = 0x00000000UL, - }; - --int pcibios_plat_dev_init(struct pci_dev *dev) --{ -- if (ltqpci_plat_dev_init) -- return ltqpci_plat_dev_init(dev); -- -- return 0; --} -- - static u32 ltq_calc_bar11mask(void) - { - u32 mem, bar11mask; -@@ -256,16 +246,6 @@ static int __devinit ltq_pci_startup(str - return 0; - } - --int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) --{ -- if (ltq_pci_irq_map[slot]) -- return ltq_pci_irq_map[slot]; -- printk(KERN_ERR "lq_pci: trying to map irq for unknown slot %d\n", -- slot); -- -- return 0; --} -- - static int __devinit ltq_pci_probe(struct platform_device *pdev) - { - struct ltq_pci_data *ltq_pci_data = diff --git a/target/linux/lantiq/patches-3.3/0051-MIPS-lantiq-pcie-add-pcie-driver.patch b/target/linux/lantiq/patches-3.3/0051-MIPS-lantiq-pcie-add-pcie-driver.patch deleted file mode 100644 index cd63f74b61..0000000000 --- a/target/linux/lantiq/patches-3.3/0051-MIPS-lantiq-pcie-add-pcie-driver.patch +++ /dev/null @@ -1,3475 +0,0 @@ -From 5497be6394beeac27c136b254dcdfd0d741289de Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 8 Mar 2012 15:57:33 +0100 -Subject: [PATCH 51/70] MIPS: lantiq: pcie: add pcie driver - ---- - arch/mips/Kconfig | 1 + - arch/mips/lantiq/Kconfig | 4 - - arch/mips/lantiq/xway/Kconfig | 21 + - arch/mips/pci/Makefile | 2 + - arch/mips/pci/fixup-lantiq-pcie.c | 81 +++ - arch/mips/pci/pci.c | 25 + - arch/mips/pci/pcie-lantiq-msi.c | 399 +++++++++++ - arch/mips/pci/pcie-lantiq-phy.c | 408 ++++++++++++ - arch/mips/pci/pcie-lantiq.c | 1146 ++++++++++++++++++++++++++++++++ - arch/mips/pci/pcie-lantiq.h | 1305 +++++++++++++++++++++++++++++++++++++ - 10 files changed, 3388 insertions(+), 4 deletions(-) - create mode 100644 arch/mips/pci/fixup-lantiq-pcie.c - create mode 100644 arch/mips/pci/pcie-lantiq-msi.c - create mode 100644 arch/mips/pci/pcie-lantiq-phy.c - create mode 100644 arch/mips/pci/pcie-lantiq.c - create mode 100644 arch/mips/pci/pcie-lantiq.h - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -2393,6 +2393,7 @@ config PCI_DOMAINS - bool - - source "drivers/pci/Kconfig" -+source "drivers/pci/pcie/Kconfig" - - # - # ISA support is now enabled via select. Too many systems still have the one ---- a/arch/mips/lantiq/Kconfig -+++ b/arch/mips/lantiq/Kconfig -@@ -22,10 +22,6 @@ config SOC_FALCON - - endchoice - --config PCI_LANTIQ -- bool "PCI Support" -- depends on SOC_XWAY && PCI -- - source "arch/mips/lantiq/xway/Kconfig" - source "arch/mips/lantiq/falcon/Kconfig" - ---- a/arch/mips/lantiq/xway/Kconfig -+++ b/arch/mips/lantiq/xway/Kconfig -@@ -8,6 +8,27 @@ config LANTIQ_MACH_EASY50712 - - endmenu - -+choice -+ prompt "PCI" -+ default PCI_LANTIQ_NONE -+ -+config PCI_LANTIQ_NONE -+ bool "None" -+ -+config PCI_LANTIQ -+ bool "PCI Support" -+ depends on PCI -+ -+config PCIE_LANTIQ -+ bool "PCIE Support" -+ select ARCH_SUPPORTS_MSI -+ -+endchoice -+ -+config PCIE_LANTIQ_MSI -+ bool -+ depends on PCIE_LANTIQ && PCI_MSI -+ default y - endif - - if SOC_AMAZON_SE ---- a/arch/mips/pci/Makefile -+++ b/arch/mips/pci/Makefile -@@ -43,6 +43,8 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1 - obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o - obj-$(CONFIG_LANTIQ) += fixup-lantiq.o - obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o -+obj-$(CONFIG_PCIE_LANTIQ) += pcie-lantiq-phy.o pcie-lantiq.o fixup-lantiq-pcie.o -+obj-$(CONFIG_PCIE_LANTIQ_MSI) += pcie-lantiq-msi.o - obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o - obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o - obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o ---- /dev/null -+++ b/arch/mips/pci/fixup-lantiq-pcie.c -@@ -0,0 +1,81 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_fixup_pcie.c -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCIe -+** -+** DATE : 02 Mar 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Version $Date $Author $Comment -+** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+/*! -+ \file ifxmips_fixup_pcie.c -+ \ingroup IFX_PCIE -+ \brief PCIe Fixup functions source file -+*/ -+#include -+#include -+#include -+ -+#include -+ -+#include "pcie-lantiq.h" -+ -+#define PCI_VENDOR_ID_INFINEON 0x15D1 -+#define PCI_DEVICE_ID_INFINEON_DANUBE 0x000F -+#define PCI_DEVICE_ID_INFINEON_PCIE 0x0011 -+#define PCI_VENDOR_ID_LANTIQ 0x1BEF -+#define PCI_DEVICE_ID_LANTIQ_PCIE 0x0011 -+ -+ -+ -+static void __devinit -+ifx_pcie_fixup_resource(struct pci_dev *dev) -+{ -+ u32 reg; -+ -+ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s: fixup host controller %s (%04x:%04x)\n", -+ __func__, pci_name(dev), dev->vendor, dev->device); -+ -+ /* Setup COMMAND register */ -+ reg = PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER /* | -+ PCI_COMMAND_INTX_DISABLE */| PCI_COMMAND_SERR; -+ pci_write_config_word(dev, PCI_COMMAND, reg); -+ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); -+} -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, ifx_pcie_fixup_resource); -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_VENDOR_ID_LANTIQ, ifx_pcie_fixup_resource); -+ -+static void __devinit -+ifx_pcie_rc_class_early_fixup(struct pci_dev *dev) -+{ -+ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: enter\n", __func__, pci_name(dev)); -+ -+ if (dev->devfn == PCI_DEVFN(0, 0) && -+ (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { -+ -+ dev->class = (PCI_CLASS_BRIDGE_PCI << 8) | (dev->class & 0xff); -+ -+ printk(KERN_INFO "%s: fixed pcie host bridge to pci-pci bridge\n", __func__); -+ } -+ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s: exit\n", __func__, pci_name(dev)); -+} -+ -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INFINEON, PCI_DEVICE_ID_INFINEON_PCIE, -+ ifx_pcie_rc_class_early_fixup); -+ -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LANTIQ, PCI_DEVICE_ID_LANTIQ_PCIE, -+ ifx_pcie_rc_class_early_fixup); ---- a/arch/mips/pci/pci.c -+++ b/arch/mips/pci/pci.c -@@ -201,6 +201,31 @@ static int __init pcibios_init(void) - - subsys_initcall(pcibios_init); - -+int pcibios_host_nr(void) -+{ -+ int count; -+ struct pci_controller *hose; -+ for (count = 0, hose = hose_head; hose; hose = hose->next, count++) { -+ ; -+ } -+ return count; -+} -+EXPORT_SYMBOL(pcibios_host_nr); -+ -+int pcibios_1st_host_bus_nr(void) -+{ -+ int bus_nr = 0; -+ struct pci_controller *hose = hose_head; -+ -+ if (hose != NULL) { -+ if (hose->bus != NULL) { -+ bus_nr = hose->bus->subordinate + 1; -+ } -+ } -+ return bus_nr; -+} -+EXPORT_SYMBOL(pcibios_1st_host_bus_nr); -+ - static int pcibios_enable_resources(struct pci_dev *dev, int mask) - { - u16 cmd, old_cmd; ---- /dev/null -+++ b/arch/mips/pci/pcie-lantiq-msi.c -@@ -0,0 +1,399 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie_msi.c -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCI MSI sub module -+** -+** DATE : 02 Mar 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe MSI Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Date $Author $Comment -+** 02 Mar,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+/*! -+ \defgroup IFX_PCIE_MSI MSI OS APIs -+ \ingroup IFX_PCIE -+ \brief PCIe bus driver OS interface functions -+*/ -+ -+/*! -+ \file ifxmips_pcie_msi.c -+ \ingroup IFX_PCIE -+ \brief PCIe MSI OS interface file -+*/ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "pcie-lantiq.h" -+ -+#define IFX_MSI_IRQ_NUM 16 -+#define SM(_v, _f) (((_v) << _f##_S) & (_f)) -+ -+#define IFX_MSI_PIC_REG_BASE (KSEG1 | 0x1F700000) -+#define IFX_PCIE_MSI_IR0 (INT_NUM_IM4_IRL0 + 27) -+#define IFX_PCIE_MSI_IR1 (INT_NUM_IM4_IRL0 + 28) -+#define IFX_PCIE_MSI_IR2 (INT_NUM_IM4_IRL0 + 29) -+#define IFX_PCIE_MSI_IR3 (INT_NUM_IM0_IRL0 + 30) -+ -+#define IFX_MSI_PCI_INT_DISABLE 0x80000000 -+#define IFX_MSI_PIC_INT_LINE 0x30000000 -+#define IFX_MSI_PIC_MSG_ADDR 0x0FFF0000 -+#define IFX_MSI_PIC_MSG_DATA 0x0000FFFF -+#define IFX_MSI_PIC_BIG_ENDIAN 1 -+#define IFX_MSI_PIC_INT_LINE_S 28 -+#define IFX_MSI_PIC_MSG_ADDR_S 16 -+#define IFX_MSI_PIC_MSG_DATA_S 0x0 -+ -+enum { -+ IFX_PCIE_MSI_IDX0 = 0, -+ IFX_PCIE_MSI_IDX1, -+ IFX_PCIE_MSI_IDX2, -+ IFX_PCIE_MSI_IDX3, -+}; -+ -+typedef struct ifx_msi_irq_idx { -+ const int irq; -+ const int idx; -+}ifx_msi_irq_idx_t; -+ -+struct ifx_msi_pic { -+ volatile u32 pic_table[IFX_MSI_IRQ_NUM]; -+ volatile u32 pic_endian; /* 0x40 */ -+}; -+typedef struct ifx_msi_pic *ifx_msi_pic_t; -+ -+typedef struct ifx_msi_irq { -+ const volatile ifx_msi_pic_t msi_pic_p; -+ const u32 msi_phy_base; -+ const ifx_msi_irq_idx_t msi_irq_idx[IFX_MSI_IRQ_NUM]; -+ /* -+ * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is -+ * in use. -+ */ -+ u16 msi_free_irq_bitmask; -+ -+ /* -+ * Each bit in msi_multiple_irq_bitmask tells that the device using -+ * this bit in msi_free_irq_bitmask is also using the next bit. This -+ * is used so we can disable all of the MSI interrupts when a device -+ * uses multiple. -+ */ -+ u16 msi_multiple_irq_bitmask; -+}ifx_msi_irq_t; -+ -+static ifx_msi_irq_t msi_irqs[IFX_PCIE_CORE_NR] = { -+ { -+ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI_PIC_REG_BASE, -+ .msi_phy_base = PCIE_MSI_PHY_BASE, -+ .msi_irq_idx = { -+ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ }, -+ .msi_free_irq_bitmask = 0, -+ .msi_multiple_irq_bitmask= 0, -+ }, -+#ifdef CONFIG_IFX_PCIE_2ND_CORE -+ { -+ .msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI1_PIC_REG_BASE, -+ .msi_phy_base = PCIE1_MSI_PHY_BASE, -+ .msi_irq_idx = { -+ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ {IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1}, -+ {IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3}, -+ }, -+ .msi_free_irq_bitmask = 0, -+ .msi_multiple_irq_bitmask= 0, -+ -+ }, -+#endif /* CONFIG_IFX_PCIE_2ND_CORE */ -+}; -+ -+/* -+ * This lock controls updates to msi_free_irq_bitmask, -+ * msi_multiple_irq_bitmask and pic register settting -+ */ -+static DEFINE_SPINLOCK(ifx_pcie_msi_lock); -+ -+void pcie_msi_pic_init(int pcie_port) -+{ -+ spin_lock(&ifx_pcie_msi_lock); -+ msi_irqs[pcie_port].msi_pic_p->pic_endian = IFX_MSI_PIC_BIG_ENDIAN; -+ spin_unlock(&ifx_pcie_msi_lock); -+} -+ -+/** -+ * \fn int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) -+ * \brief Called when a driver request MSI interrupts instead of the -+ * legacy INT A-D. This routine will allocate multiple interrupts -+ * for MSI devices that support them. A device can override this by -+ * programming the MSI control bits [6:4] before calling -+ * pci_enable_msi(). -+ * -+ * \param[in] pdev Device requesting MSI interrupts -+ * \param[in] desc MSI descriptor -+ * -+ * \return -EINVAL Invalid pcie root port or invalid msi bit -+ * \return 0 OK -+ * \ingroup IFX_PCIE_MSI -+ */ -+int -+arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) -+{ -+ int irq, pos; -+ u16 control; -+ int irq_idx; -+ int irq_step; -+ int configured_private_bits; -+ int request_private_bits; -+ struct msi_msg msg; -+ u16 search_mask; -+ struct ifx_pci_controller *ctrl = pdev->bus->sysdata; -+ int pcie_port = ctrl->port; -+ -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s %s enter\n", __func__, pci_name(pdev)); -+ -+ /* XXX, skip RC MSI itself */ -+ if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) { -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s RC itself doesn't use MSI interrupt\n", __func__); -+ return -EINVAL; -+ } -+ -+ /* -+ * Read the MSI config to figure out how many IRQs this device -+ * wants. Most devices only want 1, which will give -+ * configured_private_bits and request_private_bits equal 0. -+ */ -+ pci_read_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &control); -+ -+ /* -+ * If the number of private bits has been configured then use -+ * that value instead of the requested number. This gives the -+ * driver the chance to override the number of interrupts -+ * before calling pci_enable_msi(). -+ */ -+ configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4; -+ if (configured_private_bits == 0) { -+ /* Nothing is configured, so use the hardware requested size */ -+ request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1; -+ } -+ else { -+ /* -+ * Use the number of configured bits, assuming the -+ * driver wanted to override the hardware request -+ * value. -+ */ -+ request_private_bits = configured_private_bits; -+ } -+ -+ /* -+ * The PCI 2.3 spec mandates that there are at most 32 -+ * interrupts. If this device asks for more, only give it one. -+ */ -+ if (request_private_bits > 5) { -+ request_private_bits = 0; -+ } -+again: -+ /* -+ * The IRQs have to be aligned on a power of two based on the -+ * number being requested. -+ */ -+ irq_step = (1 << request_private_bits); -+ -+ /* Mask with one bit for each IRQ */ -+ search_mask = (1 << irq_step) - 1; -+ -+ /* -+ * We're going to search msi_free_irq_bitmask_lock for zero -+ * bits. This represents an MSI interrupt number that isn't in -+ * use. -+ */ -+ spin_lock(&ifx_pcie_msi_lock); -+ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos += irq_step) { -+ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & (search_mask << pos)) == 0) { -+ msi_irqs[pcie_port].msi_free_irq_bitmask |= search_mask << pos; -+ msi_irqs[pcie_port].msi_multiple_irq_bitmask |= (search_mask >> 1) << pos; -+ break; -+ } -+ } -+ spin_unlock(&ifx_pcie_msi_lock); -+ -+ /* Make sure the search for available interrupts didn't fail */ -+ if (pos >= IFX_MSI_IRQ_NUM) { -+ if (request_private_bits) { -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s: Unable to find %d free " -+ "interrupts, trying just one", __func__, 1 << request_private_bits); -+ request_private_bits = 0; -+ goto again; -+ } -+ else { -+ printk(KERN_ERR "%s: Unable to find a free MSI interrupt\n", __func__); -+ return -EINVAL; -+ } -+ } -+ irq = msi_irqs[pcie_port].msi_irq_idx[pos].irq; -+ irq_idx = msi_irqs[pcie_port].msi_irq_idx[pos].idx; -+ -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pos %d, irq %d irq_idx %d\n", pos, irq, irq_idx); -+ -+ /* -+ * Initialize MSI. This has to match the memory-write endianess from the device -+ * Address bits [23:12] -+ */ -+ spin_lock(&ifx_pcie_msi_lock); -+ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] = SM(irq_idx, IFX_MSI_PIC_INT_LINE) | -+ SM((msi_irqs[pcie_port].msi_phy_base >> 12), IFX_MSI_PIC_MSG_ADDR) | -+ SM((1 << pos), IFX_MSI_PIC_MSG_DATA); -+ -+ /* Enable this entry */ -+ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~IFX_MSI_PCI_INT_DISABLE; -+ spin_unlock(&ifx_pcie_msi_lock); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "pic_table[%d]: 0x%08x\n", -+ pos, msi_irqs[pcie_port].msi_pic_p->pic_table[pos]); -+ -+ /* Update the number of IRQs the device has available to it */ -+ control &= ~PCI_MSI_FLAGS_QSIZE; -+ control |= (request_private_bits << 4); -+ pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, control); -+ -+ irq_set_msi_desc(irq, desc); -+ msg.address_hi = 0x0; -+ msg.address_lo = msi_irqs[pcie_port].msi_phy_base; -+ msg.data = SM((1 << pos), IFX_MSI_PIC_MSG_DATA); -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "msi_data: pos %d 0x%08x\n", pos, msg.data); -+ -+ write_msi_msg(irq, &msg); -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); -+ return 0; -+} -+ -+static int -+pcie_msi_irq_to_port(unsigned int irq, int *port) -+{ -+ int ret = 0; -+ -+ if (irq == IFX_PCIE_MSI_IR0 || irq == IFX_PCIE_MSI_IR1 || -+ irq == IFX_PCIE_MSI_IR2 || irq == IFX_PCIE_MSI_IR3) { -+ *port = IFX_PCIE_PORT0; -+ } -+#ifdef CONFIG_IFX_PCIE_2ND_CORE -+ else if (irq == IFX_PCIE1_MSI_IR0 || irq == IFX_PCIE1_MSI_IR1 || -+ irq == IFX_PCIE1_MSI_IR2 || irq == IFX_PCIE1_MSI_IR3) { -+ *port = IFX_PCIE_PORT1; -+ } -+#endif /* CONFIG_IFX_PCIE_2ND_CORE */ -+ else { -+ printk(KERN_ERR "%s: Attempted to teardown illegal " -+ "MSI interrupt (%d)\n", __func__, irq); -+ ret = -EINVAL; -+ } -+ return ret; -+} -+ -+/** -+ * \fn void arch_teardown_msi_irq(unsigned int irq) -+ * \brief Called when a device no longer needs its MSI interrupts. All -+ * MSI interrupts for the device are freed. -+ * -+ * \param irq The devices first irq number. There may be multple in sequence. -+ * \return none -+ * \ingroup IFX_PCIE_MSI -+ */ -+void -+arch_teardown_msi_irq(unsigned int irq) -+{ -+ int pos; -+ int number_irqs; -+ u16 bitmask; -+ int pcie_port; -+ -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s enter\n", __func__); -+ -+ BUG_ON(irq > (INT_NUM_IM4_IRL0 + 31)); -+ -+ if (pcie_msi_irq_to_port(irq, &pcie_port) != 0) { -+ return; -+ } -+ -+ /* Shift the mask to the correct bit location, not always correct -+ * Probally, the first match will be chosen. -+ */ -+ for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos++) { -+ if ((msi_irqs[pcie_port].msi_irq_idx[pos].irq == irq) -+ && (msi_irqs[pcie_port].msi_free_irq_bitmask & ( 1 << pos))) { -+ break; -+ } -+ } -+ if (pos >= IFX_MSI_IRQ_NUM) { -+ printk(KERN_ERR "%s: Unable to find a matched MSI interrupt\n", __func__); -+ return; -+ } -+ spin_lock(&ifx_pcie_msi_lock); -+ /* Disable this entry */ -+ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] |= IFX_MSI_PCI_INT_DISABLE; -+ msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~(IFX_MSI_PIC_INT_LINE | IFX_MSI_PIC_MSG_ADDR | IFX_MSI_PIC_MSG_DATA); -+ spin_unlock(&ifx_pcie_msi_lock); -+ /* -+ * Count the number of IRQs we need to free by looking at the -+ * msi_multiple_irq_bitmask. Each bit set means that the next -+ * IRQ is also owned by this device. -+ */ -+ number_irqs = 0; -+ while (((pos + number_irqs) < IFX_MSI_IRQ_NUM) && -+ (msi_irqs[pcie_port].msi_multiple_irq_bitmask & (1 << (pos + number_irqs)))) { -+ number_irqs++; -+ } -+ number_irqs++; -+ -+ /* Mask with one bit for each IRQ */ -+ bitmask = (1 << number_irqs) - 1; -+ -+ bitmask <<= pos; -+ if ((msi_irqs[pcie_port].msi_free_irq_bitmask & bitmask) != bitmask) { -+ printk(KERN_ERR "%s: Attempted to teardown MSI " -+ "interrupt (%d) not in use\n", __func__, irq); -+ return; -+ } -+ /* Checks are done, update the in use bitmask */ -+ spin_lock(&ifx_pcie_msi_lock); -+ msi_irqs[pcie_port].msi_free_irq_bitmask &= ~bitmask; -+ msi_irqs[pcie_port].msi_multiple_irq_bitmask &= ~(bitmask >> 1); -+ spin_unlock(&ifx_pcie_msi_lock); -+ IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__); -+} -+ -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Chuanhua.Lei@infineon.com"); -+MODULE_SUPPORTED_DEVICE("Infineon PCIe IP builtin MSI PIC module"); -+MODULE_DESCRIPTION("Infineon PCIe IP builtin MSI PIC driver"); -+ ---- /dev/null -+++ b/arch/mips/pci/pcie-lantiq-phy.c -@@ -0,0 +1,408 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie_phy.c -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCIe PHY sub module -+** -+** DATE : 14 May 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Version $Date $Author $Comment -+** 0.0.1 14 May,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+/*! -+ \file ifxmips_pcie_phy.c -+ \ingroup IFX_PCIE -+ \brief PCIe PHY PLL register programming source file -+*/ -+#include -+#include -+#include -+#include -+ -+#include "pcie-lantiq.h" -+ -+/* PCIe PDI only supports 16 bit operation */ -+ -+#define IFX_PCIE_PHY_REG_WRITE16(__addr, __data) \ -+ ((*(volatile u16 *) (__addr)) = (__data)) -+ -+#define IFX_PCIE_PHY_REG_READ16(__addr) \ -+ (*(volatile u16 *) (__addr)) -+ -+#define IFX_PCIE_PHY_REG16(__addr) \ -+ (*(volatile u16 *) (__addr)) -+ -+#define IFX_PCIE_PHY_REG(__reg, __value, __mask) do { \ -+ u16 read_data; \ -+ u16 write_data; \ -+ read_data = IFX_PCIE_PHY_REG_READ16((__reg)); \ -+ write_data = (read_data & ((u16)~(__mask))) | (((u16)(__value)) & ((u16)(__mask)));\ -+ IFX_PCIE_PHY_REG_WRITE16((__reg), write_data); \ -+} while (0) -+ -+#define IFX_PCIE_PLL_TIMEOUT 1000 /* Tunnable */ -+ -+static void -+pcie_phy_comm_setup(int pcie_port) -+{ -+ /* PLL Setting */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); -+ -+ /* increase the bias reference voltage */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); -+ -+ /* Endcnt */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); -+ -+ /* force */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); -+ -+ /* predrv_ser_en */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); -+ -+ /* ctrl_lim */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); -+ -+ /* ctrl */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); -+ -+ /* predrv_ser_en */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); -+ -+ /* RTERM*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); -+ -+ /* Improved 100MHz clock output */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); -+ -+ /* Reduced CDR BW to avoid glitches */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); -+} -+ -+#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE -+static void -+pcie_phy_36mhz_mode_setup(int pcie_port) -+{ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); -+ -+ /* en_ext_mmd_div_ratio */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); -+ -+ /* ext_mmd_div_ratio*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); -+ -+ /* pll_ensdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); -+ -+ /* en_const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); -+ -+ /* mmd */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); -+ -+ /* lf_mode */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); -+ -+ /* const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); -+ -+ /* const sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); -+ -+ /* pllmod */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); -+} -+#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ -+ -+#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE -+static void -+pcie_phy_36mhz_ssc_mode_setup(int pcie_port) -+{ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); -+ -+ /* PLL Setting */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL1(pcie_port), 0x120e, 0xFFFF); -+ -+ /* Increase the bias reference voltage */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x39D7, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x0900, 0xFFFF); -+ -+ /* Endcnt */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_EI(pcie_port), 0x0004, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_A_CTRL(pcie_port), 0x6803, 0xFFFF); -+ -+ /* Force */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0008, 0x0008); -+ -+ /* Predrv_ser_en */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL2(pcie_port), 0x0706, 0xFFFF); -+ -+ /* ctrl_lim */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL3(pcie_port), 0x1FFF, 0xFFFF); -+ -+ /* ctrl */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_A_CTRL1(pcie_port), 0x0800, 0xFF00); -+ -+ /* predrv_ser_en */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4702, 0x7F00); -+ -+ /* RTERM*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL2(pcie_port), 0x2e00, 0xFFFF); -+ -+ /* en_ext_mmd_div_ratio */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); -+ -+ /* ext_mmd_div_ratio*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); -+ -+ /* pll_ensdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0400, 0x0400); -+ -+ /* en_const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); -+ -+ /* mmd */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); -+ -+ /* lf_mode */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); -+ -+ /* const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); -+ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0100); -+ /* const sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); -+ -+ /* pllmod */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1c72, 0xFFFF); -+ -+ /* improved 100MHz clock output */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL2(pcie_port), 0x3096, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_A_CTRL2(pcie_port), 0x4707, 0xFFFF); -+ -+ /* reduced CDR BW to avoid glitches */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CDR(pcie_port), 0x0235, 0xFFFF); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); -+} -+#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE */ -+ -+#ifdef CONFIG_IFX_PCIE_PHY_25MHZ_MODE -+static void -+pcie_phy_25mhz_mode_setup(int pcie_port) -+{ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); -+ /* en_const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); -+ -+ /* pll_ensdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0000, 0x0200); -+ -+ /* en_ext_mmd_div_ratio*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0002, 0x0002); -+ -+ /* ext_mmd_div_ratio*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0040, 0x0070); -+ -+ /* mmd */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x6000, 0xe000); -+ -+ /* lf_mode */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x4000, 0x4000); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); -+} -+#endif /* CONFIG_IFX_PCIE_PHY_25MHZ_MODE */ -+ -+#ifdef CONFIG_IFX_PCIE_PHY_100MHZ_MODE -+static void -+pcie_phy_100mhz_mode_setup(int pcie_port) -+{ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d enter\n", __func__, pcie_port); -+ /* en_ext_mmd_div_ratio */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0002); -+ -+ /* ext_mmd_div_ratio*/ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL3(pcie_port), 0x0000, 0x0070); -+ -+ /* pll_ensdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0200, 0x0200); -+ -+ /* en_const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x0100, 0x0100); -+ -+ /* mmd */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL3(pcie_port), 0x2000, 0xe000); -+ -+ /* lf_mode */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_A_CTRL2(pcie_port), 0x0000, 0x4000); -+ -+ /* const_sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL1(pcie_port), 0x38e4, 0xFFFF); -+ -+ /* const sdm */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL2(pcie_port), 0x00ee, 0x00FF); -+ -+ /* pllmod */ -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL7(pcie_port), 0x0002, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL6(pcie_port), 0x3a04, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL5(pcie_port), 0xfae3, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_PLL_CTRL4(pcie_port), 0x1b72, 0xFFFF); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "%s pcie_port %d exit\n", __func__, pcie_port); -+} -+#endif /* CONFIG_IFX_PCIE_PHY_100MHZ_MODE */ -+ -+static int -+pcie_phy_wait_startup_ready(int pcie_port) -+{ -+ int i; -+ -+ for (i = 0; i < IFX_PCIE_PLL_TIMEOUT; i++) { -+ if ((IFX_PCIE_PHY_REG16(PCIE_PHY_PLL_STATUS(pcie_port)) & 0x0040) != 0) { -+ break; -+ } -+ udelay(10); -+ } -+ if (i >= IFX_PCIE_PLL_TIMEOUT) { -+ printk(KERN_ERR "%s PLL Link timeout\n", __func__); -+ return -1; -+ } -+ return 0; -+} -+ -+static void -+pcie_phy_load_enable(int pcie_port, int slice) -+{ -+ /* Set the load_en of tx/rx slice to '1' */ -+ switch (slice) { -+ case 1: -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0010, 0x0010); -+ break; -+ case 2: -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0010, 0x0010); -+ break; -+ case 3: -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0002, 0x0002); -+ break; -+ } -+} -+ -+static void -+pcie_phy_load_disable(int pcie_port, int slice) -+{ -+ /* set the load_en of tx/rx slice to '0' */ -+ switch (slice) { -+ case 1: -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_CTRL1(pcie_port), 0x0000, 0x0010); -+ break; -+ case 2: -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_CTRL1(pcie_port), 0x0000, 0x0010); -+ break; -+ case 3: -+ IFX_PCIE_PHY_REG(PCIE_PHY_RX1_CTRL1(pcie_port), 0x0000, 0x0002); -+ break; -+ } -+} -+ -+static void pcie_phy_load_war(int pcie_port) -+{ -+ int slice; -+ -+ for (slice = 1; slice < 4; slice++) { -+ pcie_phy_load_enable(pcie_port, slice); -+ udelay(1); -+ pcie_phy_load_disable(pcie_port, slice); -+ } -+} -+ -+static void pcie_phy_tx2_modulation(int pcie_port) -+{ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD1(pcie_port), 0x1FFE, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD2(pcie_port), 0xFFFE, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0601, 0xFFFF); -+ mdelay(1); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX2_MOD3(pcie_port), 0x0001, 0xFFFF); -+} -+ -+static void pcie_phy_tx1_modulation(int pcie_port) -+{ -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD1(pcie_port), 0x1FFE, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD2(pcie_port), 0xFFFE, 0xFFFF); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0601, 0xFFFF); -+ mdelay(1); -+ IFX_PCIE_PHY_REG(PCIE_PHY_TX1_MOD3(pcie_port), 0x0001, 0xFFFF); -+} -+ -+static void pcie_phy_tx_modulation_war(int pcie_port) -+{ -+ int i; -+#define PCIE_PHY_MODULATION_NUM 5 -+ for (i = 0; i < PCIE_PHY_MODULATION_NUM; i++) { -+ pcie_phy_tx2_modulation(pcie_port); -+ pcie_phy_tx1_modulation(pcie_port); -+ } -+#undef PCIE_PHY_MODULATION_NUM -+} -+ -+void pcie_phy_clock_mode_setup(int pcie_port) -+{ -+ pcie_pdi_big_endian(pcie_port); -+ -+ /* Enable PDI to access PCIe PHY register */ -+ pcie_pdi_pmu_enable(pcie_port); -+ -+ /* Configure PLL and PHY clock */ -+ pcie_phy_comm_setup(pcie_port); -+ -+#ifdef CONFIG_IFX_PCIE_PHY_36MHZ_MODE -+ pcie_phy_36mhz_mode_setup(pcie_port); -+#elif defined(CONFIG_IFX_PCIE_PHY_36MHZ_SSC_MODE) -+ pcie_phy_36mhz_ssc_mode_setup(pcie_port); -+#elif defined(CONFIG_IFX_PCIE_PHY_25MHZ_MODE) -+ pcie_phy_25mhz_mode_setup(pcie_port); -+#elif defined (CONFIG_IFX_PCIE_PHY_100MHZ_MODE) -+ pcie_phy_100mhz_mode_setup(pcie_port); -+#else -+ #error "PCIE PHY Clock Mode must be chosen first!!!!" -+#endif /* CONFIG_IFX_PCIE_PHY_36MHZ_MODE */ -+ -+ /* Enable PCIe PHY and make PLL setting take effect */ -+ pcie_phy_pmu_enable(pcie_port); -+ -+ /* Check if we are in startup_ready status */ -+ pcie_phy_wait_startup_ready(pcie_port); -+ -+ pcie_phy_load_war(pcie_port); -+ -+ /* Apply TX modulation workarounds */ -+ pcie_phy_tx_modulation_war(pcie_port); -+ -+#ifdef IFX_PCI_PHY_REG_DUMP -+ IFX_PCIE_PRINT(PCIE_MSG_PHY, "Modified PHY register dump\n"); -+ pcie_phy_reg_dump(pcie_port); -+#endif -+} -+ ---- /dev/null -+++ b/arch/mips/pci/pcie-lantiq.c -@@ -0,0 +1,1146 @@ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define CONFIG_IFX_PCIE_1ST_CORE -+ -+#include "pcie-lantiq.h" -+ -+#define IFX_PCIE_IR (INT_NUM_IM4_IRL0 + 25) -+#define IFX_PCIE_INTA (INT_NUM_IM4_IRL0 + 8) -+#define IFX_PCIE_INTB (INT_NUM_IM4_IRL0 + 9) -+#define IFX_PCIE_INTC (INT_NUM_IM4_IRL0 + 10) -+#define IFX_PCIE_INTD (INT_NUM_IM4_IRL0 + 11) -+#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) -+#define SM(_v, _f) (((_v) << _f##_S) & (_f)) -+#define IFX_REG_SET_BIT(_f, _r) \ -+ IFX_REG_W32((IFX_REG_R32((_r)) &~ (_f)) | (_f), (_r)) -+#define IFX_PCIE_LTSSM_ENABLE_TIMEOUT 10 -+#define IFX_PCIE_PHY_LINK_UP_TIMEOUT 1000 -+#define IFX_PCIE_PHY_LOOP_CNT 5 -+ -+static DEFINE_SPINLOCK(ifx_pcie_lock); -+ -+int pcibios_1st_host_bus_nr(void); -+ -+unsigned int g_pcie_debug_flag = PCIE_MSG_ANY & (~PCIE_MSG_CFG); -+ -+static ifx_pcie_irq_t pcie_irqs[IFX_PCIE_CORE_NR] = { -+ { -+ .ir_irq = { -+ .irq = IFX_PCIE_IR, -+ .name = "ifx_pcie_rc0", -+ }, -+ -+ .legacy_irq = { -+ { -+ .irq_bit = PCIE_IRN_INTA, -+ .irq = IFX_PCIE_INTA, -+ }, -+ { -+ .irq_bit = PCIE_IRN_INTB, -+ .irq = IFX_PCIE_INTB, -+ }, -+ { -+ .irq_bit = PCIE_IRN_INTC, -+ .irq = IFX_PCIE_INTC, -+ }, -+ { -+ .irq_bit = PCIE_IRN_INTD, -+ .irq = IFX_PCIE_INTD, -+ }, -+ }, -+ }, -+}; -+ -+static inline int pcie_ltssm_enable(int pcie_port) -+{ -+ int i; -+ -+ IFX_REG_W32(PCIE_RC_CCR_LTSSM_ENABLE, PCIE_RC_CCR(pcie_port)); /* Enable LTSSM */ -+ -+ /* Wait for the link to come up */ -+ for (i = 0; i < IFX_PCIE_LTSSM_ENABLE_TIMEOUT; i++) { -+ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_RETRAIN_PENDING)) { -+ break; -+ } -+ udelay(10); -+ } -+ if (i >= IFX_PCIE_LTSSM_ENABLE_TIMEOUT) { -+ IFX_PCIE_PRINT(PCIE_MSG_INIT, "%s link timeout!!!!!\n", __func__); -+ return -1; -+ } -+ return 0; -+} -+ -+static inline void pcie_status_register_clear(int pcie_port) -+{ -+ IFX_REG_W32(0, PCIE_RC_DR(pcie_port)); -+ IFX_REG_W32(0, PCIE_PCICMDSTS(pcie_port)); -+ IFX_REG_W32(0, PCIE_DCTLSTS(pcie_port)); -+ IFX_REG_W32(0, PCIE_LCTLSTS(pcie_port)); -+ IFX_REG_W32(0, PCIE_SLCTLSTS(pcie_port)); -+ IFX_REG_W32(0, PCIE_RSTS(pcie_port)); -+ IFX_REG_W32(0, PCIE_UES_R(pcie_port)); -+ IFX_REG_W32(0, PCIE_UEMR(pcie_port)); -+ IFX_REG_W32(0, PCIE_UESR(pcie_port)); -+ IFX_REG_W32(0, PCIE_CESR(pcie_port)); -+ IFX_REG_W32(0, PCIE_CEMR(pcie_port)); -+ IFX_REG_W32(0, PCIE_RESR(pcie_port)); -+ IFX_REG_W32(0, PCIE_PVCCRSR(pcie_port)); -+ IFX_REG_W32(0, PCIE_VC0_RSR0(pcie_port)); -+ IFX_REG_W32(0, PCIE_TPFCS(pcie_port)); -+ IFX_REG_W32(0, PCIE_TNPFCS(pcie_port)); -+ IFX_REG_W32(0, PCIE_TCFCS(pcie_port)); -+ IFX_REG_W32(0, PCIE_QSR(pcie_port)); -+ IFX_REG_W32(0, PCIE_IOBLSECS(pcie_port)); -+} -+ -+static inline int ifx_pcie_link_up(int pcie_port) -+{ -+ return (IFX_REG_R32(PCIE_PHY_SR(pcie_port)) & PCIE_PHY_SR_PHY_LINK_UP) ? 1 : 0; -+} -+ -+static inline void pcie_mem_io_setup(int pcie_port) -+{ -+ unsigned int reg; -+ /* -+ * BAR[0:1] readonly register -+ * RC contains only minimal BARs for packets mapped to this device -+ * Mem/IO filters defines a range of memory occupied by memory mapped IO devices that -+ * reside on the downstream side fo the bridge. -+ */ -+ reg = SM((PCIE_MEM_PHY_PORT_TO_END(pcie_port) >> 20), PCIE_MBML_MEM_LIMIT_ADDR) -+ | SM((PCIE_MEM_PHY_PORT_TO_BASE(pcie_port) >> 20), PCIE_MBML_MEM_BASE_ADDR); -+ IFX_REG_W32(reg, PCIE_MBML(pcie_port)); -+ -+ /* PCIe_PBML, same as MBML */ -+ IFX_REG_W32(IFX_REG_R32(PCIE_MBML(pcie_port)), PCIE_PMBL(pcie_port)); -+ -+ /* IO Address Range */ -+ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 12), PCIE_IOBLSECS_IO_LIMIT_ADDR) -+ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 12), PCIE_IOBLSECS_IO_BASE_ADDR); -+ reg |= PCIE_IOBLSECS_32BIT_IO_ADDR; -+ IFX_REG_W32(reg, PCIE_IOBLSECS(pcie_port)); -+ -+ reg = SM((PCIE_IO_PHY_PORT_TO_END(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT) -+ | SM((PCIE_IO_PHY_PORT_TO_BASE(pcie_port) >> 16), PCIE_IO_BANDL_UPPER_16BIT_IO_BASE); -+ IFX_REG_W32(reg, PCIE_IO_BANDL(pcie_port)); -+} -+ -+static inline void pcie_msi_setup(int pcie_port) -+{ -+ unsigned int reg; -+ -+ /* XXX, MSI stuff should only apply to EP */ -+ /* MSI Capability: Only enable 32-bit addresses */ -+ reg = IFX_REG_R32(PCIE_MCAPR(pcie_port)); -+ reg &= ~PCIE_MCAPR_ADDR64_CAP; -+ reg |= PCIE_MCAPR_MSI_ENABLE; -+ -+ /* Disable multiple message */ -+ reg &= ~(PCIE_MCAPR_MULTI_MSG_CAP | PCIE_MCAPR_MULTI_MSG_ENABLE); -+ IFX_REG_W32(reg, PCIE_MCAPR(pcie_port)); -+} -+ -+static inline void pcie_pm_setup(int pcie_port) -+{ -+ unsigned int reg; -+ -+ /* Enable PME, Soft reset enabled */ -+ reg = IFX_REG_R32(PCIE_PM_CSR(pcie_port)); -+ reg |= PCIE_PM_CSR_PME_ENABLE | PCIE_PM_CSR_SW_RST; -+ IFX_REG_W32(reg, PCIE_PM_CSR(pcie_port)); -+} -+ -+static inline void pcie_bus_setup(int pcie_port) -+{ -+ unsigned int reg; -+ -+ reg = SM(0, PCIE_BNR_PRIMARY_BUS_NUM) | SM(1, PCIE_PNR_SECONDARY_BUS_NUM) | SM(0xFF, PCIE_PNR_SUB_BUS_NUM); -+ IFX_REG_W32(reg, PCIE_BNR(pcie_port)); -+} -+ -+static inline void pcie_device_setup(int pcie_port) -+{ -+ unsigned int reg; -+ -+ /* Device capability register, set up Maximum payload size */ -+ reg = IFX_REG_R32(PCIE_DCAP(pcie_port)); -+ reg |= PCIE_DCAP_ROLE_BASE_ERR_REPORT; -+ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCAP_MAX_PAYLOAD_SIZE); -+ -+ /* Only available for EP */ -+ reg &= ~(PCIE_DCAP_EP_L0S_LATENCY | PCIE_DCAP_EP_L1_LATENCY); -+ IFX_REG_W32(reg, PCIE_DCAP(pcie_port)); -+ -+ /* Device control and status register */ -+ /* Set Maximum Read Request size for the device as a Requestor */ -+ reg = IFX_REG_R32(PCIE_DCTLSTS(pcie_port)); -+ -+ /* -+ * Request size can be larger than the MPS used, but the completions returned -+ * for the read will be bounded by the MPS size. -+ * In our system, Max request size depends on AHB burst size. It is 64 bytes. -+ * but we set it as 128 as minimum one. -+ */ -+ reg |= SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_READ_SIZE) -+ | SM(PCIE_MAX_PAYLOAD_128, PCIE_DCTLSTS_MAX_PAYLOAD_SIZE); -+ -+ /* Enable relaxed ordering, no snoop, and all kinds of errors */ -+ reg |= PCIE_DCTLSTS_RELAXED_ORDERING_EN | PCIE_DCTLSTS_ERR_EN | PCIE_DCTLSTS_NO_SNOOP_EN; -+ -+ IFX_REG_W32(reg, PCIE_DCTLSTS(pcie_port)); -+} -+ -+static inline void pcie_link_setup(int pcie_port) -+{ -+ unsigned int reg; -+ -+ /* -+ * XXX, Link capability register, bit 18 for EP CLKREQ# dynamic clock management for L1, L2/3 CPM -+ * L0s is reported during link training via TS1 order set by N_FTS -+ */ -+ reg = IFX_REG_R32(PCIE_LCAP(pcie_port)); -+ reg &= ~PCIE_LCAP_L0S_EIXT_LATENCY; -+ reg |= SM(3, PCIE_LCAP_L0S_EIXT_LATENCY); -+ IFX_REG_W32(reg, PCIE_LCAP(pcie_port)); -+ -+ /* Link control and status register */ -+ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); -+ -+ /* Link Enable, ASPM enabled */ -+ reg &= ~PCIE_LCTLSTS_LINK_DISABLE; -+ -+#ifdef CONFIG_PCIEASPM -+ /* -+ * We use the same physical reference clock that the platform provides on the connector -+ * It paved the way for ASPM to calculate the new exit Latency -+ */ -+ reg |= PCIE_LCTLSTS_SLOT_CLK_CFG; -+ reg |= PCIE_LCTLSTS_COM_CLK_CFG; -+ /* -+ * We should disable ASPM by default except that we have dedicated power management support -+ * Enable ASPM will cause the system hangup/instability, performance degration -+ */ -+ reg |= PCIE_LCTLSTS_ASPM_ENABLE; -+#else -+ reg &= ~PCIE_LCTLSTS_ASPM_ENABLE; -+#endif /* CONFIG_PCIEASPM */ -+ -+ /* -+ * The maximum size of any completion with data packet is bounded by the MPS setting -+ * in device control register -+ */ -+ /* RCB may cause multiple split transactions, two options available, we use 64 byte RCB */ -+ reg &= ~ PCIE_LCTLSTS_RCB128; -+ IFX_REG_W32(reg, PCIE_LCTLSTS(pcie_port)); -+} -+ -+static inline void pcie_error_setup(int pcie_port) -+{ -+ unsigned int reg; -+ -+ /* -+ * Forward ERR_COR, ERR_NONFATAL, ERR_FATAL to the backbone -+ * Poisoned write TLPs and completions indicating poisoned TLPs will set the PCIe_PCICMDSTS.MDPE -+ */ -+ reg = IFX_REG_R32(PCIE_INTRBCTRL(pcie_port)); -+ reg |= PCIE_INTRBCTRL_SERR_ENABLE | PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE; -+ -+ IFX_REG_W32(reg, PCIE_INTRBCTRL(pcie_port)); -+ -+ /* Uncorrectable Error Mask Register, Unmask all bits in PCIE_UESR */ -+ reg = IFX_REG_R32(PCIE_UEMR(pcie_port)); -+ reg &= ~PCIE_ALL_UNCORRECTABLE_ERR; -+ IFX_REG_W32(reg, PCIE_UEMR(pcie_port)); -+ -+ /* Uncorrectable Error Severity Register, ALL errors are FATAL */ -+ IFX_REG_W32(PCIE_ALL_UNCORRECTABLE_ERR, PCIE_UESR(pcie_port)); -+ -+ /* Correctable Error Mask Register, unmask all bits */ -+ reg = IFX_REG_R32(PCIE_CEMR(pcie_port)); -+ reg &= ~PCIE_CORRECTABLE_ERR; -+ IFX_REG_W32(reg, PCIE_CEMR(pcie_port)); -+ -+ /* Advanced Error Capabilities and Control Registr */ -+ reg = IFX_REG_R32(PCIE_AECCR(pcie_port)); -+ reg |= PCIE_AECCR_ECRC_CHECK_EN | PCIE_AECCR_ECRC_GEN_EN; -+ IFX_REG_W32(reg, PCIE_AECCR(pcie_port)); -+ -+ /* Root Error Command Register, Report all types of errors */ -+ reg = IFX_REG_R32(PCIE_RECR(pcie_port)); -+ reg |= PCIE_RECR_ERR_REPORT_EN; -+ IFX_REG_W32(reg, PCIE_RECR(pcie_port)); -+ -+ /* Clear the Root status register */ -+ reg = IFX_REG_R32(PCIE_RESR(pcie_port)); -+ IFX_REG_W32(reg, PCIE_RESR(pcie_port)); -+} -+ -+static inline void pcie_root_setup(int pcie_port) -+{ -+ unsigned int reg; -+ -+ /* Root control and capabilities register */ -+ reg = IFX_REG_R32(PCIE_RCTLCAP(pcie_port)); -+ reg |= PCIE_RCTLCAP_SERR_ENABLE | PCIE_RCTLCAP_PME_INT_EN; -+ IFX_REG_W32(reg, PCIE_RCTLCAP(pcie_port)); -+} -+ -+static inline void pcie_vc_setup(int pcie_port) -+{ -+ unsigned int reg; -+ -+ /* Port VC Capability Register 2 */ -+ reg = IFX_REG_R32(PCIE_PVC2(pcie_port)); -+ reg &= ~PCIE_PVC2_VC_ARB_WRR; -+ reg |= PCIE_PVC2_VC_ARB_16P_FIXED_WRR; -+ IFX_REG_W32(reg, PCIE_PVC2(pcie_port)); -+ -+ /* VC0 Resource Capability Register */ -+ reg = IFX_REG_R32(PCIE_VC0_RC(pcie_port)); -+ reg &= ~PCIE_VC0_RC_REJECT_SNOOP; -+ IFX_REG_W32(reg, PCIE_VC0_RC(pcie_port)); -+} -+ -+static inline void pcie_port_logic_setup(int pcie_port) -+{ -+ unsigned int reg; -+ -+ /* FTS number, default 12, increase to 63, may increase time from/to L0s to L0 */ -+ reg = IFX_REG_R32(PCIE_AFR(pcie_port)); -+ reg &= ~(PCIE_AFR_FTS_NUM | PCIE_AFR_COM_FTS_NUM); -+ reg |= SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_FTS_NUM) -+ | SM(PCIE_AFR_FTS_NUM_DEFAULT, PCIE_AFR_COM_FTS_NUM); -+ /* L0s and L1 entry latency */ -+ reg &= ~(PCIE_AFR_L0S_ENTRY_LATENCY | PCIE_AFR_L1_ENTRY_LATENCY); -+ reg |= SM(PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L0S_ENTRY_LATENCY) -+ | SM(PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT, PCIE_AFR_L1_ENTRY_LATENCY); -+ IFX_REG_W32(reg, PCIE_AFR(pcie_port)); -+ -+ /* Port Link Control Register */ -+ reg = IFX_REG_R32(PCIE_PLCR(pcie_port)); -+ reg |= PCIE_PLCR_DLL_LINK_EN; /* Enable the DLL link */ -+ IFX_REG_W32(reg, PCIE_PLCR(pcie_port)); -+ -+ /* Lane Skew Register */ -+ reg = IFX_REG_R32(PCIE_LSR(pcie_port)); -+ /* Enable ACK/NACK and FC */ -+ reg &= ~(PCIE_LSR_ACKNAK_DISABLE | PCIE_LSR_FC_DISABLE); -+ IFX_REG_W32(reg, PCIE_LSR(pcie_port)); -+ -+ /* Symbol Timer Register and Filter Mask Register 1 */ -+ reg = IFX_REG_R32(PCIE_STRFMR(pcie_port)); -+ -+ /* Default SKP interval is very accurate already, 5us */ -+ /* Enable IO/CFG transaction */ -+ reg |= PCIE_STRFMR_RX_CFG_TRANS_ENABLE | PCIE_STRFMR_RX_IO_TRANS_ENABLE; -+ /* Disable FC WDT */ -+ reg &= ~PCIE_STRFMR_FC_WDT_DISABLE; -+ IFX_REG_W32(reg, PCIE_STRFMR(pcie_port)); -+ -+ /* Filter Masker Register 2 */ -+ reg = IFX_REG_R32(PCIE_FMR2(pcie_port)); -+ reg |= PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 | PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1; -+ IFX_REG_W32(reg, PCIE_FMR2(pcie_port)); -+ -+ /* VC0 Completion Receive Queue Control Register */ -+ reg = IFX_REG_R32(PCIE_VC0_CRQCR(pcie_port)); -+ reg &= ~PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE; -+ reg |= SM(PCIE_VC0_TLP_QUEUE_MODE_BYPASS, PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE); -+ IFX_REG_W32(reg, PCIE_VC0_CRQCR(pcie_port)); -+} -+ -+static inline void pcie_rc_cfg_reg_setup(int pcie_port) -+{ -+ /* diable ltssm */ -+ IFX_REG_W32(0, PCIE_RC_CCR(pcie_port)); -+ -+ pcie_mem_io_setup(pcie_port); -+ pcie_msi_setup(pcie_port); -+ pcie_pm_setup(pcie_port); -+ pcie_bus_setup(pcie_port); -+ pcie_device_setup(pcie_port); -+ pcie_link_setup(pcie_port); -+ pcie_error_setup(pcie_port); -+ pcie_root_setup(pcie_port); -+ pcie_vc_setup(pcie_port); -+ pcie_port_logic_setup(pcie_port); -+} -+ -+static int ifx_pcie_wait_phy_link_up(int pcie_port) -+{ -+ int i; -+ -+ /* Wait for PHY link is up */ -+ for (i = 0; i < IFX_PCIE_PHY_LINK_UP_TIMEOUT; i++) { -+ if (ifx_pcie_link_up(pcie_port)) { -+ break; -+ } -+ udelay(100); -+ } -+ if (i >= IFX_PCIE_PHY_LINK_UP_TIMEOUT) { -+ printk(KERN_ERR "%s timeout\n", __func__); -+ return -1; -+ } -+ -+ /* Check data link up or not */ -+ if (!(IFX_REG_R32(PCIE_RC_DR(pcie_port)) & PCIE_RC_DR_DLL_UP)) { -+ printk(KERN_ERR "%s DLL link is still down\n", __func__); -+ return -1; -+ } -+ -+ /* Check Data link active or not */ -+ if (!(IFX_REG_R32(PCIE_LCTLSTS(pcie_port)) & PCIE_LCTLSTS_DLL_ACTIVE)) { -+ printk(KERN_ERR "%s DLL is not active\n", __func__); -+ return -1; -+ } -+ return 0; -+} -+ -+static inline int pcie_app_loigc_setup(int pcie_port) -+{ -+ IFX_REG_W32(PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS, PCIE_AHB_CTRL(pcie_port)); -+ -+ /* Pull PCIe EP out of reset */ -+ pcie_device_rst_deassert(pcie_port); -+ -+ /* Start LTSSM training between RC and EP */ -+ pcie_ltssm_enable(pcie_port); -+ -+ /* Check PHY status after enabling LTSSM */ -+ if (ifx_pcie_wait_phy_link_up(pcie_port) != 0) { -+ return -1; -+ } -+ return 0; -+} -+ -+/* -+ * Must be done after ltssm due to based on negotiated link -+ * width and payload size -+ * Update the Replay Time Limit. Empirically, some PCIe -+ * devices take a little longer to respond than expected under -+ * load. As a workaround for this we configure the Replay Time -+ * Limit to the value expected for a 512 byte MPS instead of -+ * our actual 128 byte MPS. The numbers below are directly -+ * from the PCIe spec table 3-4/5. -+ */ -+static inline void pcie_replay_time_update(int pcie_port) -+{ -+ unsigned int reg; -+ int nlw; -+ int rtl; -+ -+ reg = IFX_REG_R32(PCIE_LCTLSTS(pcie_port)); -+ -+ nlw = MS(reg, PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH); -+ switch (nlw) { -+ case PCIE_MAX_LENGTH_WIDTH_X1: -+ rtl = 1677; -+ break; -+ case PCIE_MAX_LENGTH_WIDTH_X2: -+ rtl = 867; -+ break; -+ case PCIE_MAX_LENGTH_WIDTH_X4: -+ rtl = 462; -+ break; -+ case PCIE_MAX_LENGTH_WIDTH_X8: -+ rtl = 258; -+ break; -+ default: -+ rtl = 1677; -+ break; -+ } -+ reg = IFX_REG_R32(PCIE_ALTRT(pcie_port)); -+ reg &= ~PCIE_ALTRT_REPLAY_TIME_LIMIT; -+ reg |= SM(rtl, PCIE_ALTRT_REPLAY_TIME_LIMIT); -+ IFX_REG_W32(reg, PCIE_ALTRT(pcie_port)); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s PCIE_ALTRT 0x%08x\n", -+ __func__, IFX_REG_R32(PCIE_ALTRT(pcie_port))); -+} -+ -+/* -+ * Table 359 Enhanced Configuration Address Mapping1) -+ * 1) This table is defined in Table 7-1, page 341, PCI Express Base Specification v1.1 -+ * Memory Address PCI Express Configuration Space -+ * A[(20+n-1):20] Bus Number 1 < n < 8 -+ * A[19:15] Device Number -+ * A[14:12] Function Number -+ * A[11:8] Extended Register Number -+ * A[7:2] Register Number -+ * A[1:0] Along with size of the access, used to generate Byte Enables -+ * For VR9, only the address bits [22:0] are mapped to the configuration space: -+ * . Address bits [22:20] select the target bus (1-of-8)1) -+ * . Address bits [19:15] select the target device (1-of-32) on the bus -+ * . Address bits [14:12] select the target function (1-of-8) within the device. -+ * . Address bits [11:2] selects the target dword (1-of-1024) within the selected function.s configuration space -+ * . Address bits [1:0] define the start byte location within the selected dword. -+ */ -+static inline unsigned int pcie_bus_addr(u8 bus_num, u16 devfn, int where) -+{ -+ unsigned int addr; -+ u8 bus; -+ -+ if (!bus_num) { -+ /* type 0 */ -+ addr = ((PCI_SLOT(devfn) & 0x1F) << 15) | ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF)& ~3); -+ } else { -+ bus = bus_num; -+ /* type 1, only support 8 buses */ -+ addr = ((bus & 0x7) << 20) | ((PCI_SLOT(devfn) & 0x1F) << 15) | -+ ((PCI_FUNC(devfn) & 0x7) << 12) | ((where & 0xFFF) & ~3); -+ } -+ IFX_PCIE_PRINT(PCIE_MSG_CFG, "%s: bus addr : %02x:%02x.%01x/%02x, addr=%08x\n", -+ __func__, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn), where, addr); -+ return addr; -+} -+ -+static int pcie_valid_config(int pcie_port, int bus, int dev) -+{ -+ /* RC itself */ -+ if ((bus == 0) && (dev == 0)) -+ return 1; -+ -+ /* No physical link */ -+ if (!ifx_pcie_link_up(pcie_port)) -+ return 0; -+ -+ /* Bus zero only has RC itself -+ * XXX, check if EP will be integrated -+ */ -+ if ((bus == 0) && (dev != 0)) -+ return 0; -+ -+ /* Maximum 8 buses supported for VRX */ -+ if (bus > 9) -+ return 0; -+ -+ /* -+ * PCIe is PtP link, one bus only supports only one device -+ * except bus zero and PCIe switch which is virtual bus device -+ * The following two conditions really depends on the system design -+ * and attached the device. -+ * XXX, how about more new switch -+ */ -+ if ((bus == 1) && (dev != 0)) -+ return 0; -+ -+ if ((bus >= 3) && (dev != 0)) -+ return 0; -+ return 1; -+} -+ -+static inline unsigned int ifx_pcie_cfg_rd(int pcie_port, unsigned int reg) -+{ -+ return IFX_REG_R32((volatile unsigned int *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); -+} -+ -+static inline void ifx_pcie_cfg_wr(int pcie_port, unsigned int reg, unsigned int val) -+{ -+ IFX_REG_W32( val, (volatile unsigned int *)(PCIE_CFG_PORT_TO_BASE(pcie_port) + reg)); -+} -+ -+static inline unsigned int ifx_pcie_rc_cfg_rd(int pcie_port, unsigned int reg) -+{ -+ return IFX_REG_R32((volatile unsigned int *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); -+} -+ -+static inline void ifx_pcie_rc_cfg_wr(int pcie_port, unsigned int reg, unsigned int val) -+{ -+ IFX_REG_W32(val, (volatile unsigned int *)(PCIE_RC_PORT_TO_BASE(pcie_port) + reg)); -+} -+ -+unsigned int ifx_pcie_bus_enum_read_hack(int where, unsigned int value) -+{ -+ unsigned int tvalue = value; -+ -+ if (where == PCI_PRIMARY_BUS) { -+ u8 primary, secondary, subordinate; -+ -+ primary = tvalue & 0xFF; -+ secondary = (tvalue >> 8) & 0xFF; -+ subordinate = (tvalue >> 16) & 0xFF; -+ primary += pcibios_1st_host_bus_nr(); -+ secondary += pcibios_1st_host_bus_nr(); -+ subordinate += pcibios_1st_host_bus_nr(); -+ tvalue = (tvalue & 0xFF000000) | (unsigned int)primary | (unsigned int)(secondary << 8) | (unsigned int)(subordinate << 16); -+ } -+ return tvalue; -+} -+ -+unsigned int ifx_pcie_bus_enum_write_hack(int where, unsigned int value) -+{ -+ unsigned int tvalue = value; -+ -+ if (where == PCI_PRIMARY_BUS) { -+ u8 primary, secondary, subordinate; -+ -+ primary = tvalue & 0xFF; -+ secondary = (tvalue >> 8) & 0xFF; -+ subordinate = (tvalue >> 16) & 0xFF; -+ if (primary > 0 && primary != 0xFF) -+ primary -= pcibios_1st_host_bus_nr(); -+ if (secondary > 0 && secondary != 0xFF) -+ secondary -= pcibios_1st_host_bus_nr(); -+ if (subordinate > 0 && subordinate != 0xFF) -+ subordinate -= pcibios_1st_host_bus_nr(); -+ tvalue = (tvalue & 0xFF000000) | (unsigned int)primary | (unsigned int)(secondary << 8) | (unsigned int)(subordinate << 16); -+ } else if (where == PCI_SUBORDINATE_BUS) { -+ u8 subordinate = tvalue & 0xFF; -+ subordinate = subordinate > 0 ? subordinate - pcibios_1st_host_bus_nr() : 0; -+ tvalue = subordinate; -+ } -+ return tvalue; -+} -+ -+/** -+ * \fn static int ifx_pcie_read_config(struct pci_bus *bus, unsigned int devfn, -+ * int where, int size, unsigned int *value) -+ * \brief Read a value from configuration space -+ * -+ * \param[in] bus Pointer to pci bus -+ * \param[in] devfn PCI device function number -+ * \param[in] where PCI register number -+ * \param[in] size Register read size -+ * \param[out] value Pointer to return value -+ * \return PCIBIOS_BAD_REGISTER_NUMBER Invalid register number -+ * \return PCIBIOS_FUNC_NOT_SUPPORTED PCI function not supported -+ * \return PCIBIOS_DEVICE_NOT_FOUND PCI device not found -+ * \return PCIBIOS_SUCCESSFUL OK -+ * \ingroup IFX_PCIE_OS -+ */ -+static int ifx_pcie_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, unsigned int *value) -+{ -+ unsigned int data = 0; -+ int bus_number = bus->number; -+ static const unsigned int mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0}; -+ int ret = PCIBIOS_SUCCESSFUL; -+ struct ifx_pci_controller *ctrl = bus->sysdata; -+ int pcie_port = ctrl->port; -+ -+ if (unlikely(size != 1 && size != 2 && size != 4)){ -+ ret = PCIBIOS_BAD_REGISTER_NUMBER; -+ goto out; -+ } -+ -+ /* Make sure the address is aligned to natural boundary */ -+ if (unlikely(((size - 1) & where))) { -+ ret = PCIBIOS_BAD_REGISTER_NUMBER; -+ goto out; -+ } -+ -+ /* -+ * If we are second controller, we have to cheat OS so that it assume -+ * its bus number starts from 0 in host controller -+ */ -+ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); -+ -+ /* -+ * We need to force the bus number to be zero on the root -+ * bus. Linux numbers the 2nd root bus to start after all -+ * busses on root 0. -+ */ -+ if (bus->parent == NULL) -+ bus_number = 0; -+ -+ /* -+ * PCIe only has a single device connected to it. It is -+ * always device ID 0. Don't bother doing reads for other -+ * device IDs on the first segment. -+ */ -+ if ((bus_number == 0) && (PCI_SLOT(devfn) != 0)) { -+ ret = PCIBIOS_FUNC_NOT_SUPPORTED; -+ goto out; -+ } -+ -+ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { -+ *value = 0xffffffff; -+ ret = PCIBIOS_DEVICE_NOT_FOUND; -+ goto out; -+ } -+ -+ IFX_PCIE_PRINT(PCIE_MSG_READ_CFG, "%s: %02x:%02x.%01x/%02x:%01d\n", __func__, bus_number, -+ PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); -+ -+ PCIE_IRQ_LOCK(ifx_pcie_lock); -+ if (bus_number == 0) { /* RC itself */ -+ unsigned int t; -+ -+ t = (where & ~3); -+ data = ifx_pcie_rc_cfg_rd(pcie_port, t); -+ IFX_PCIE_PRINT(PCIE_MSG_READ_CFG, "%s: rd local cfg, offset:%08x, data:%08x\n", -+ __func__, t, data); -+ } else { -+ unsigned int addr = pcie_bus_addr(bus_number, devfn, where); -+ -+ data = ifx_pcie_cfg_rd(pcie_port, addr); -+ if (pcie_port == IFX_PCIE_PORT0) { -+#ifdef CONFIG_IFX_PCIE_HW_SWAP -+ data = le32_to_cpu(data); -+#endif /* CONFIG_IFX_PCIE_HW_SWAP */ -+ } else { -+#ifdef CONFIG_IFX_PCIE1_HW_SWAP -+ data = le32_to_cpu(data); -+#endif /* CONFIG_IFX_PCIE_HW_SWAP */ -+ } -+ } -+ /* To get a correct PCI topology, we have to restore the bus number to OS */ -+ data = ifx_pcie_bus_enum_hack(bus, devfn, where, data, pcie_port, 1); -+ -+ PCIE_IRQ_UNLOCK(ifx_pcie_lock); -+ IFX_PCIE_PRINT(PCIE_MSG_READ_CFG, "%s: read config: data=%08x raw=%08x\n", -+ __func__, (data >> (8 * (where & 3))) & mask[size & 7], data); -+ -+ *value = (data >> (8 * (where & 3))) & mask[size & 7]; -+out: -+ return ret; -+} -+ -+static unsigned int ifx_pcie_size_to_value(int where, int size, unsigned int data, unsigned int value) -+{ -+ unsigned int shift; -+ unsigned int tdata = data; -+ -+ switch (size) { -+ case 1: -+ shift = (where & 0x3) << 3; -+ tdata &= ~(0xffU << shift); -+ tdata |= ((value & 0xffU) << shift); -+ break; -+ case 2: -+ shift = (where & 3) << 3; -+ tdata &= ~(0xffffU << shift); -+ tdata |= ((value & 0xffffU) << shift); -+ break; -+ case 4: -+ tdata = value; -+ break; -+ } -+ return tdata; -+} -+ -+/** -+ * \fn static static int ifx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, -+ * int where, int size, unsigned int value) -+ * \brief Write a value to PCI configuration space -+ * -+ * \param[in] bus Pointer to pci bus -+ * \param[in] devfn PCI device function number -+ * \param[in] where PCI register number -+ * \param[in] size The register size to be written -+ * \param[in] value The valule to be written -+ * \return PCIBIOS_BAD_REGISTER_NUMBER Invalid register number -+ * \return PCIBIOS_DEVICE_NOT_FOUND PCI device not found -+ * \return PCIBIOS_SUCCESSFUL OK -+ * \ingroup IFX_PCIE_OS -+ */ -+static int ifx_pcie_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, unsigned int value) -+{ -+ int bus_number = bus->number; -+ int ret = PCIBIOS_SUCCESSFUL; -+ struct ifx_pci_controller *ctrl = bus->sysdata; -+ int pcie_port = ctrl->port; -+ unsigned int tvalue = value; -+ unsigned int data; -+ -+ /* Make sure the address is aligned to natural boundary */ -+ if (unlikely(((size - 1) & where))) { -+ ret = PCIBIOS_BAD_REGISTER_NUMBER; -+ goto out; -+ } -+ /* -+ * If we are second controller, we have to cheat OS so that it assume -+ * its bus number starts from 0 in host controller -+ */ -+ bus_number = ifx_pcie_bus_nr_deduct(bus_number, pcie_port); -+ -+ /* -+ * We need to force the bus number to be zero on the root -+ * bus. Linux numbers the 2nd root bus to start after all -+ * busses on root 0. -+ */ -+ if (bus->parent == NULL) -+ bus_number = 0; -+ -+ if (pcie_valid_config(pcie_port, bus_number, PCI_SLOT(devfn)) == 0) { -+ ret = PCIBIOS_DEVICE_NOT_FOUND; -+ goto out; -+ } -+ -+ IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG, "%s: %02x:%02x.%01x/%02x:%01d value=%08x\n", __func__, -+ bus_number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, value); -+ -+ /* XXX, some PCIe device may need some delay */ -+ PCIE_IRQ_LOCK(ifx_pcie_lock); -+ -+ /* -+ * To configure the correct bus topology using native way, we have to cheat Os so that -+ * it can configure the PCIe hardware correctly. -+ */ -+ tvalue = ifx_pcie_bus_enum_hack(bus, devfn, where, value, pcie_port, 0); -+ -+ if (bus_number == 0) { /* RC itself */ -+ unsigned int t; -+ -+ t = (where & ~3); -+ IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG,"%s: wr local cfg, offset:%08x, fill:%08x\n", __func__, t, value); -+ data = ifx_pcie_rc_cfg_rd(pcie_port, t); -+ IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG,"%s: rd local cfg, offset:%08x, data:%08x\n", __func__, t, data); -+ -+ data = ifx_pcie_size_to_value(where, size, data, tvalue); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG,"%s: wr local cfg, offset:%08x, value:%08x\n", __func__, t, data); -+ ifx_pcie_rc_cfg_wr(pcie_port, t, data); -+ IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG,"%s: rd local cfg, offset:%08x, value:%08x\n", -+ __func__, t, ifx_pcie_rc_cfg_rd(pcie_port, t)); -+ } else { -+ unsigned int addr = pcie_bus_addr(bus_number, devfn, where); -+ -+ IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG,"%s: wr cfg, offset:%08x, fill:%08x\n", __func__, addr, value); -+ data = ifx_pcie_cfg_rd(pcie_port, addr); -+ if (pcie_port == IFX_PCIE_PORT0) { -+#ifdef CONFIG_IFX_PCIE_HW_SWAP -+ data = le32_to_cpu(data); -+#endif /* CONFIG_IFX_PCIE_HW_SWAP */ -+ } else { -+#ifdef CONFIG_IFX_PCIE1_HW_SWAP -+ data = le32_to_cpu(data); -+#endif /* CONFIG_IFX_PCIE_HW_SWAP */ -+ } -+ IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG,"%s: rd cfg, offset:%08x, data:%08x\n", __func__, addr, data); -+ -+ data = ifx_pcie_size_to_value(where, size, data, tvalue); -+ if (pcie_port == IFX_PCIE_PORT0) { -+#ifdef CONFIG_IFX_PCIE_HW_SWAP -+ data = cpu_to_le32(data); -+#endif /* CONFIG_IFX_PCIE_HW_SWAP */ -+ } else { -+#ifdef CONFIG_IFX_PCIE1_HW_SWAP -+ data = cpu_to_le32(data); -+#endif /* CONFIG_IFX_PCIE_HW_SWAP */ -+ } -+ IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG, "%s: wr cfg, offset:%08x, value:%08x\n", __func__, addr, data); -+ ifx_pcie_cfg_wr(pcie_port, addr, data); -+ IFX_PCIE_PRINT(PCIE_MSG_WRITE_CFG, "%s: rd cfg, offset:%08x, value:%08x\n", -+ __func__, addr, ifx_pcie_cfg_rd(pcie_port, addr)); -+ } -+ PCIE_IRQ_UNLOCK(ifx_pcie_lock); -+out: -+ return ret; -+} -+ -+static struct resource ifx_pcie_io_resource = { -+ .name = "PCIe0 I/O space", -+ .start = PCIE_IO_PHY_BASE, -+ .end = PCIE_IO_PHY_END, -+ .flags = IORESOURCE_IO, -+}; -+ -+static struct resource ifx_pcie_mem_resource = { -+ .name = "PCIe0 Memory space", -+ .start = PCIE_MEM_PHY_BASE, -+ .end = PCIE_MEM_PHY_END, -+ .flags = IORESOURCE_MEM, -+}; -+ -+static struct pci_ops ifx_pcie_ops = { -+ .read = ifx_pcie_read_config, -+ .write = ifx_pcie_write_config, -+}; -+ -+static struct ifx_pci_controller ifx_pcie_controller[IFX_PCIE_CORE_NR] = { -+ { -+ .pcic = { -+ .pci_ops = &ifx_pcie_ops, -+ .mem_resource = &ifx_pcie_mem_resource, -+ .io_resource = &ifx_pcie_io_resource, -+ }, -+ .port = IFX_PCIE_PORT0, -+ }, -+}; -+ -+static inline void pcie_core_int_clear_all(int pcie_port) -+{ -+ unsigned int reg; -+ reg = IFX_REG_R32(PCIE_IRNCR(pcie_port)); -+ reg &= PCIE_RC_CORE_COMBINED_INT; -+ IFX_REG_W32(reg, PCIE_IRNCR(pcie_port)); -+} -+ -+static irqreturn_t pcie_rc_core_isr(int irq, void *dev_id) -+{ -+ struct ifx_pci_controller *ctrl = (struct ifx_pci_controller *)dev_id; -+ int pcie_port = ctrl->port; -+ -+ IFX_PCIE_PRINT(PCIE_MSG_ISR, "PCIe RC error intr %d\n", irq); -+ pcie_core_int_clear_all(pcie_port); -+ return IRQ_HANDLED; -+} -+ -+static int pcie_rc_core_int_init(int pcie_port) -+{ -+ int ret; -+ -+ /* Enable core interrupt */ -+ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNEN(pcie_port)); -+ -+ /* Clear it first */ -+ IFX_REG_SET_BIT(PCIE_RC_CORE_COMBINED_INT, PCIE_IRNCR(pcie_port)); -+ ret = request_irq(pcie_irqs[pcie_port].ir_irq.irq, pcie_rc_core_isr, IRQF_DISABLED, -+ pcie_irqs[pcie_port].ir_irq.name, &ifx_pcie_controller[pcie_port]); -+ if (ret) -+ printk(KERN_ERR "%s request irq %d failed\n", __func__, IFX_PCIE_IR); -+ -+ return ret; -+} -+ -+int ifx_pcie_bios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -+{ -+ unsigned int irq_bit = 0; -+ int irq = 0; -+ struct ifx_pci_controller *ctrl = dev->bus->sysdata; -+ int pcie_port = ctrl->port; -+ -+ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s port %d dev %s slot %d pin %d \n", __func__, pcie_port, pci_name(dev), slot, pin); -+ -+ if ((pin == PCIE_LEGACY_DISABLE) || (pin > PCIE_LEGACY_INT_MAX)) { -+ printk(KERN_WARNING "WARNING: dev %s: invalid interrupt pin %d\n", pci_name(dev), pin); -+ return -1; -+ } -+ /* Pin index so minus one */ -+ irq_bit = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq_bit; -+ irq = pcie_irqs[pcie_port].legacy_irq[pin - 1].irq; -+ IFX_REG_SET_BIT(irq_bit, PCIE_IRNEN(pcie_port)); -+ IFX_REG_SET_BIT(irq_bit, PCIE_IRNCR(pcie_port)); -+ IFX_PCIE_PRINT(PCIE_MSG_FIXUP, "%s dev %s irq %d assigned\n", __func__, pci_name(dev), irq); -+ return irq; -+} -+ -+/** -+ * \fn int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev) -+ * \brief Called to perform platform specific PCI setup -+ * -+ * \param[in] dev The Linux PCI device structure for the device to map -+ * \return OK -+ * \ingroup IFX_PCIE_OS -+ */ -+int ifx_pcie_bios_plat_dev_init(struct pci_dev *dev) -+{ -+ u16 config; -+ unsigned int dconfig; -+ int pos; -+ /* Enable reporting System errors and parity errors on all devices */ -+ /* Enable parity checking and error reporting */ -+ pci_read_config_word(dev, PCI_COMMAND, &config); -+ config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR /*| PCI_COMMAND_INVALIDATE | -+ PCI_COMMAND_FAST_BACK*/; -+ pci_write_config_word(dev, PCI_COMMAND, config); -+ -+ if (dev->subordinate) { -+ /* Set latency timers on sub bridges */ -+ pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 0x40); /* XXX, */ -+ /* More bridge error detection */ -+ pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config); -+ config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR; -+ pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config); -+ } -+ /* Enable the PCIe normal error reporting */ -+ pos = pci_find_capability(dev, PCI_CAP_ID_EXP); -+ if (pos) { -+ /* Disable system error generation in response to error messages */ -+ pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &config); -+ config &= ~(PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE | PCI_EXP_RTCTL_SEFEE); -+ pci_write_config_word(dev, pos + PCI_EXP_RTCTL, config); -+ -+ /* Clear PCIE Capability's Device Status */ -+ pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &config); -+ pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, config); -+ -+ /* Update Device Control */ -+ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config); -+ /* Correctable Error Reporting */ -+ config |= PCI_EXP_DEVCTL_CERE; -+ /* Non-Fatal Error Reporting */ -+ config |= PCI_EXP_DEVCTL_NFERE; -+ /* Fatal Error Reporting */ -+ config |= PCI_EXP_DEVCTL_FERE; -+ /* Unsupported Request */ -+ config |= PCI_EXP_DEVCTL_URRE; -+ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config); -+ } -+ -+ /* Find the Advanced Error Reporting capability */ -+ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR); -+ if (pos) { -+ /* Clear Uncorrectable Error Status */ -+ pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &dconfig); -+ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, dconfig); -+ /* Enable reporting of all uncorrectable errors */ -+ /* Uncorrectable Error Mask - turned on bits disable errors */ -+ pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0); -+ /* -+ * Leave severity at HW default. This only controls if -+ * errors are reported as uncorrectable or -+ * correctable, not if the error is reported. -+ */ -+ /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */ -+ /* Clear Correctable Error Status */ -+ pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig); -+ pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig); -+ /* Enable reporting of all correctable errors */ -+ /* Correctable Error Mask - turned on bits disable errors */ -+ pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0); -+ /* Advanced Error Capabilities */ -+ pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig); -+ /* ECRC Generation Enable */ -+ if (dconfig & PCI_ERR_CAP_ECRC_GENC) -+ dconfig |= PCI_ERR_CAP_ECRC_GENE; -+ /* ECRC Check Enable */ -+ if (dconfig & PCI_ERR_CAP_ECRC_CHKC) -+ dconfig |= PCI_ERR_CAP_ECRC_CHKE; -+ pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig); -+ -+ /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */ -+ /* Enable Root Port's interrupt in response to error messages */ -+ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, -+ PCI_ERR_ROOT_CMD_COR_EN | -+ PCI_ERR_ROOT_CMD_NONFATAL_EN | -+ PCI_ERR_ROOT_CMD_FATAL_EN); -+ /* Clear the Root status register */ -+ pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig); -+ pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig); -+ } -+ /* WAR, only 128 MRRS is supported, force all EPs to support this value */ -+ pcie_set_readrq(dev, 128); -+ return 0; -+} -+ -+static void pcie_phy_rst(int pcie_port) -+{ -+ pcie_phy_rst_assert(pcie_port); -+ pcie_phy_rst_deassert(pcie_port); -+ /* Make sure PHY PLL is stable */ -+ udelay(20); -+} -+ -+static int pcie_rc_initialize(int pcie_port) -+{ -+ int i; -+ -+ pcie_rcu_endian_setup(pcie_port); -+ -+ pcie_ep_gpio_rst_init(pcie_port); -+ -+ /* -+ * XXX, PCIe elastic buffer bug will cause not to be detected. One more -+ * reset PCIe PHY will solve this issue -+ */ -+ for (i = 0; i < IFX_PCIE_PHY_LOOP_CNT; i++) { -+ /* Disable PCIe PHY Analog part for sanity check */ -+ pcie_phy_pmu_disable(pcie_port); -+ pcie_phy_rst(pcie_port); -+ /* PCIe Core reset enabled, low active, sw programmed */ -+ pcie_core_rst_assert(pcie_port); -+ /* Put PCIe EP in reset status */ -+ pcie_device_rst_assert(pcie_port); -+ /* PCI PHY & Core reset disabled, high active, sw programmed */ -+ pcie_core_rst_deassert(pcie_port); -+ /* Already in a quiet state, program PLL, enable PHY, check ready bit */ -+ pcie_phy_clock_mode_setup(pcie_port); -+ /* Enable PCIe PHY and Clock */ -+ pcie_core_pmu_setup(pcie_port); -+ /* Clear status registers */ -+ pcie_status_register_clear(pcie_port); -+#ifdef CONFIG_PCI_MSI -+ pcie_msi_init(pcie_port); -+#endif /* CONFIG_PCI_MSI */ -+ pcie_rc_cfg_reg_setup(pcie_port); -+ -+ /* Once link is up, break out */ -+ if (pcie_app_loigc_setup(pcie_port) == 0) -+ break; -+ } -+ if (i >= IFX_PCIE_PHY_LOOP_CNT) { -+ printk(KERN_ERR "%s link up failed!!!!!\n", __func__); -+ return -EIO; -+ } -+ /* NB, don't increase ACK/NACK timer timeout value, which will cause a lot of COR errors */ -+ pcie_replay_time_update(pcie_port); -+ return 0; -+} -+ -+static int inline ifx_pcie_startup_port_nr(void) -+{ -+ int pcie_port = IFX_PCIE_PORT0; -+ -+ pcie_port = IFX_PCIE_PORT0; -+ return pcie_port; -+} -+ -+/** -+ * \fn static int __init ifx_pcie_bios_init(void) -+ * \brief Initialize the IFX PCIe controllers -+ * -+ * \return -EIO PCIe PHY link is not up -+ * \return -ENOMEM Configuration/IO space failed to map -+ * \return 0 OK -+ * \ingroup IFX_PCIE_OS -+ */ -+extern int (*ltqpci_plat_arch_init)(struct pci_dev *dev); -+extern int (*ltqpci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin); -+static int __devinit ltq_pcie_probe(struct platform_device *pdev) -+{ -+ char ver_str[128] = {0}; -+ void __iomem *io_map_base; -+ int pcie_port; -+ int startup_port; -+ ltqpci_map_irq = ifx_pcie_bios_map_irq; -+ ltqpci_plat_arch_init = ifx_pcie_bios_plat_dev_init; -+ /* Enable AHB Master/ Slave */ -+ pcie_ahb_pmu_setup(); -+ -+ startup_port = ifx_pcie_startup_port_nr(); -+ -+ ltq_gpio_request(&pdev->dev, IFX_PCIE_GPIO_RESET, 0, 1, "pcie-reset"); -+ -+ for (pcie_port = startup_port; pcie_port < IFX_PCIE_CORE_NR; pcie_port++){ -+ if (pcie_rc_initialize(pcie_port) == 0) { -+ /* Otherwise, warning will pop up */ -+ io_map_base = ioremap(PCIE_IO_PHY_PORT_TO_BASE(pcie_port), PCIE_IO_SIZE); -+ if (io_map_base == NULL) -+ return -ENOMEM; -+ ifx_pcie_controller[pcie_port].pcic.io_map_base = (unsigned long)io_map_base; -+ register_pci_controller(&ifx_pcie_controller[pcie_port].pcic); -+ /* XXX, clear error status */ -+ pcie_rc_core_int_init(pcie_port); -+ } -+ } -+ -+ printk(KERN_INFO "%s", ver_str); -+return 0; -+} -+ -+static struct platform_driver ltq_pcie_driver = { -+ .probe = ltq_pcie_probe, -+ .driver = { -+ .name = "pcie-xway", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+int __init pciebios_init(void) -+{ -+ return platform_driver_register(<q_pcie_driver); -+} -+ -+arch_initcall(pciebios_init); ---- /dev/null -+++ b/arch/mips/pci/pcie-lantiq.h -@@ -0,0 +1,1305 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifxmips_pcie_reg.h -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : PCIe module -+** -+** DATE : 02 Mar 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : PCIe Root Complex Driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Version $Date $Author $Comment -+** 0.0.1 17 Mar,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+#ifndef IFXMIPS_PCIE_REG_H -+#define IFXMIPS_PCIE_REG_H -+#include -+#include -+#include -+#include -+/*! -+ \file ifxmips_pcie_reg.h -+ \ingroup IFX_PCIE -+ \brief header file for PCIe module register definition -+*/ -+/* PCIe Address Mapping Base */ -+#define PCIE_CFG_PHY_BASE 0x1D000000UL -+#define PCIE_CFG_BASE (KSEG1 + PCIE_CFG_PHY_BASE) -+#define PCIE_CFG_SIZE (8 * 1024 * 1024) -+ -+#define PCIE_MEM_PHY_BASE 0x1C000000UL -+#define PCIE_MEM_BASE (KSEG1 + PCIE_MEM_PHY_BASE) -+#define PCIE_MEM_SIZE (16 * 1024 * 1024) -+#define PCIE_MEM_PHY_END (PCIE_MEM_PHY_BASE + PCIE_MEM_SIZE - 1) -+ -+#define PCIE_IO_PHY_BASE 0x1D800000UL -+#define PCIE_IO_BASE (KSEG1 + PCIE_IO_PHY_BASE) -+#define PCIE_IO_SIZE (1 * 1024 * 1024) -+#define PCIE_IO_PHY_END (PCIE_IO_PHY_BASE + PCIE_IO_SIZE - 1) -+ -+#define PCIE_RC_CFG_BASE (KSEG1 + 0x1D900000) -+#define PCIE_APP_LOGIC_REG (KSEG1 + 0x1E100900) -+#define PCIE_MSI_PHY_BASE 0x1F600000UL -+ -+#define PCIE_PDI_PHY_BASE 0x1F106800UL -+#define PCIE_PDI_BASE (KSEG1 + PCIE_PDI_PHY_BASE) -+#define PCIE_PDI_SIZE 0x400 -+ -+#define PCIE1_CFG_PHY_BASE 0x19000000UL -+#define PCIE1_CFG_BASE (KSEG1 + PCIE1_CFG_PHY_BASE) -+#define PCIE1_CFG_SIZE (8 * 1024 * 1024) -+ -+#define PCIE1_MEM_PHY_BASE 0x18000000UL -+#define PCIE1_MEM_BASE (KSEG1 + PCIE1_MEM_PHY_BASE) -+#define PCIE1_MEM_SIZE (16 * 1024 * 1024) -+#define PCIE1_MEM_PHY_END (PCIE1_MEM_PHY_BASE + PCIE1_MEM_SIZE - 1) -+ -+#define PCIE1_IO_PHY_BASE 0x19800000UL -+#define PCIE1_IO_BASE (KSEG1 + PCIE1_IO_PHY_BASE) -+#define PCIE1_IO_SIZE (1 * 1024 * 1024) -+#define PCIE1_IO_PHY_END (PCIE1_IO_PHY_BASE + PCIE1_IO_SIZE - 1) -+ -+#define PCIE1_RC_CFG_BASE (KSEG1 + 0x19900000) -+#define PCIE1_APP_LOGIC_REG (KSEG1 + 0x1E100700) -+#define PCIE1_MSI_PHY_BASE 0x1F400000UL -+ -+#define PCIE1_PDI_PHY_BASE 0x1F700400UL -+#define PCIE1_PDI_BASE (KSEG1 + PCIE1_PDI_PHY_BASE) -+#define PCIE1_PDI_SIZE 0x400 -+ -+#define PCIE_CFG_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_CFG_BASE) : (PCIE_CFG_BASE)) -+#define PCIE_MEM_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_BASE) : (PCIE_MEM_BASE)) -+#define PCIE_IO_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_BASE) : (PCIE_IO_BASE)) -+#define PCIE_MEM_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_MEM_PHY_BASE) : (PCIE_MEM_PHY_BASE)) -+#define PCIE_MEM_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_MEM_PHY_END) : (PCIE_MEM_PHY_END)) -+#define PCIE_IO_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_IO_PHY_BASE) : (PCIE_IO_PHY_BASE)) -+#define PCIE_IO_PHY_PORT_TO_END(X) ((X) > 0 ? (PCIE1_IO_PHY_END) : (PCIE_IO_PHY_END)) -+#define PCIE_APP_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_APP_LOGIC_REG) : (PCIE_APP_LOGIC_REG)) -+#define PCIE_RC_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_RC_CFG_BASE) : (PCIE_RC_CFG_BASE)) -+#define PCIE_PHY_PORT_TO_BASE(X) ((X) > 0 ? (PCIE1_PDI_BASE) : (PCIE_PDI_BASE)) -+ -+/* PCIe Application Logic Register */ -+/* RC Core Control Register */ -+#define PCIE_RC_CCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x10) -+/* This should be enabled after initializing configuratin registers -+ * Also should check link status retraining bit -+ */ -+#define PCIE_RC_CCR_LTSSM_ENABLE 0x00000001 /* Enable LTSSM to continue link establishment */ -+ -+/* RC Core Debug Register */ -+#define PCIE_RC_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x14) -+#define PCIE_RC_DR_DLL_UP 0x00000001 /* Data Link Layer Up */ -+#define PCIE_RC_DR_CURRENT_POWER_STATE 0x0000000E /* Current Power State */ -+#define PCIE_RC_DR_CURRENT_POWER_STATE_S 1 -+#define PCIE_RC_DR_CURRENT_LTSSM_STATE 0x000001F0 /* Current LTSSM State */ -+#define PCIE_RC_DR_CURRENT_LTSSM_STATE_S 4 -+ -+#define PCIE_RC_DR_PM_DEV_STATE 0x00000E00 /* Power Management D-State */ -+#define PCIE_RC_DR_PM_DEV_STATE_S 9 -+ -+#define PCIE_RC_DR_PM_ENABLED 0x00001000 /* Power Management State from PMU */ -+#define PCIE_RC_DR_PME_EVENT_ENABLED 0x00002000 /* Power Management Event Enable State */ -+#define PCIE_RC_DR_AUX_POWER_ENABLED 0x00004000 /* Auxiliary Power Enable */ -+ -+/* Current Power State Definition */ -+enum { -+ PCIE_RC_DR_D0 = 0, -+ PCIE_RC_DR_D1, /* Not supported */ -+ PCIE_RC_DR_D2, /* Not supported */ -+ PCIE_RC_DR_D3, -+ PCIE_RC_DR_UN, -+}; -+ -+/* PHY Link Status Register */ -+#define PCIE_PHY_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x18) -+#define PCIE_PHY_SR_PHY_LINK_UP 0x00000001 /* PHY Link Up/Down Indicator */ -+ -+/* Electromechanical Control Register */ -+#define PCIE_EM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x1C) -+#define PCIE_EM_CR_CARD_IS_PRESENT 0x00000001 /* Card Presence Detect State */ -+#define PCIE_EM_CR_MRL_OPEN 0x00000002 /* MRL Sensor State */ -+#define PCIE_EM_CR_POWER_FAULT_SET 0x00000004 /* Power Fault Detected */ -+#define PCIE_EM_CR_MRL_SENSOR_SET 0x00000008 /* MRL Sensor Changed */ -+#define PCIE_EM_CR_PRESENT_DETECT_SET 0x00000010 /* Card Presense Detect Changed */ -+#define PCIE_EM_CR_CMD_CPL_INT_SET 0x00000020 /* Command Complete Interrupt */ -+#define PCIE_EM_CR_SYS_INTERLOCK_SET 0x00000040 /* System Electromechanical IterLock Engaged */ -+#define PCIE_EM_CR_ATTENTION_BUTTON_SET 0x00000080 /* Attention Button Pressed */ -+ -+/* Interrupt Status Register */ -+#define PCIE_IR_SR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x20) -+#define PCIE_IR_SR_PME_CAUSE_MSI 0x00000002 /* MSI caused by PME */ -+#define PCIE_IR_SR_HP_PME_WAKE_GEN 0x00000004 /* Hotplug PME Wake Generation */ -+#define PCIE_IR_SR_HP_MSI 0x00000008 /* Hotplug MSI */ -+#define PCIE_IR_SR_AHB_LU_ERR 0x00000030 /* AHB Bridge Lookup Error Signals */ -+#define PCIE_IR_SR_AHB_LU_ERR_S 4 -+#define PCIE_IR_SR_INT_MSG_NUM 0x00003E00 /* Interrupt Message Number */ -+#define PCIE_IR_SR_INT_MSG_NUM_S 9 -+#define PCIE_IR_SR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ -+#define PCIE_IR_SR_AER_INT_MSG_NUM_S 27 -+ -+/* Message Control Register */ -+#define PCIE_MSG_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x30) -+#define PCIE_MSG_CR_GEN_PME_TURN_OFF_MSG 0x00000001 /* Generate PME Turn Off Message */ -+#define PCIE_MSG_CR_GEN_UNLOCK_MSG 0x00000002 /* Generate Unlock Message */ -+ -+#define PCIE_VDM_DR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x34) -+ -+/* Vendor-Defined Message Requester ID Register */ -+#define PCIE_VDM_RID(X) (PCIE_APP_PORT_TO_BASE (X) + 0x38) -+#define PCIE_VDM_RID_VENROR_MSG_REQ_ID 0x0000FFFF -+#define PCIE_VDM_RID_VDMRID_S 0 -+ -+/* ASPM Control Register */ -+#define PCIE_ASPM_CR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x40) -+#define PCIE_ASPM_CR_HOT_RST 0x00000001 /* Hot Reset Request to the downstream device */ -+#define PCIE_ASPM_CR_REQ_EXIT_L1 0x00000002 /* Request to Exit L1 */ -+#define PCIE_ASPM_CR_REQ_ENTER_L1 0x00000004 /* Request to Enter L1 */ -+ -+/* Vendor Message DW0 Register */ -+#define PCIE_VM_MSG_DW0(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x50) -+#define PCIE_VM_MSG_DW0_TYPE 0x0000001F /* Message type */ -+#define PCIE_VM_MSG_DW0_TYPE_S 0 -+#define PCIE_VM_MSG_DW0_FORMAT 0x00000060 /* Format */ -+#define PCIE_VM_MSG_DW0_FORMAT_S 5 -+#define PCIE_VM_MSG_DW0_TC 0x00007000 /* Traffic Class */ -+#define PCIE_VM_MSG_DW0_TC_S 12 -+#define PCIE_VM_MSG_DW0_ATTR 0x000C0000 /* Atrributes */ -+#define PCIE_VM_MSG_DW0_ATTR_S 18 -+#define PCIE_VM_MSG_DW0_EP_TLP 0x00100000 /* Poisoned TLP */ -+#define PCIE_VM_MSG_DW0_TD 0x00200000 /* TLP Digest */ -+#define PCIE_VM_MSG_DW0_LEN 0xFFC00000 /* Length */ -+#define PCIE_VM_MSG_DW0_LEN_S 22 -+ -+/* Format Definition */ -+enum { -+ PCIE_VM_MSG_FORMAT_00 = 0, /* 3DW Hdr, no data*/ -+ PCIE_VM_MSG_FORMAT_01, /* 4DW Hdr, no data */ -+ PCIE_VM_MSG_FORMAT_10, /* 3DW Hdr, with data */ -+ PCIE_VM_MSG_FORMAT_11, /* 4DW Hdr, with data */ -+}; -+ -+/* Traffic Class Definition */ -+enum { -+ PCIE_VM_MSG_TC0 = 0, -+ PCIE_VM_MSG_TC1, -+ PCIE_VM_MSG_TC2, -+ PCIE_VM_MSG_TC3, -+ PCIE_VM_MSG_TC4, -+ PCIE_VM_MSG_TC5, -+ PCIE_VM_MSG_TC6, -+ PCIE_VM_MSG_TC7, -+}; -+ -+/* Attributes Definition */ -+enum { -+ PCIE_VM_MSG_ATTR_00 = 0, /* RO and No Snoop cleared */ -+ PCIE_VM_MSG_ATTR_01, /* RO cleared , No Snoop set */ -+ PCIE_VM_MSG_ATTR_10, /* RO set, No Snoop cleared*/ -+ PCIE_VM_MSG_ATTR_11, /* RO and No Snoop set */ -+}; -+ -+/* Payload Size Definition */ -+#define PCIE_VM_MSG_LEN_MIN 0 -+#define PCIE_VM_MSG_LEN_MAX 1024 -+ -+/* Vendor Message DW1 Register */ -+#define PCIE_VM_MSG_DW1(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x54) -+#define PCIE_VM_MSG_DW1_FUNC_NUM 0x00000070 /* Function Number */ -+#define PCIE_VM_MSG_DW1_FUNC_NUM_S 8 -+#define PCIE_VM_MSG_DW1_CODE 0x00FF0000 /* Message Code */ -+#define PCIE_VM_MSG_DW1_CODE_S 16 -+#define PCIE_VM_MSG_DW1_TAG 0xFF000000 /* Tag */ -+#define PCIE_VM_MSG_DW1_TAG_S 24 -+ -+#define PCIE_VM_MSG_DW2(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x58) -+#define PCIE_VM_MSG_DW3(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x5C) -+ -+/* Vendor Message Request Register */ -+#define PCIE_VM_MSG_REQR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x60) -+#define PCIE_VM_MSG_REQR_REQ 0x00000001 /* Vendor Message Request */ -+ -+ -+/* AHB Slave Side Band Control Register */ -+#define PCIE_AHB_SSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x70) -+#define PCIE_AHB_SSB_REQ_BCM 0x00000001 /* Slave Reques BCM filed */ -+#define PCIE_AHB_SSB_REQ_EP 0x00000002 /* Slave Reques EP filed */ -+#define PCIE_AHB_SSB_REQ_TD 0x00000004 /* Slave Reques TD filed */ -+#define PCIE_AHB_SSB_REQ_ATTR 0x00000018 /* Slave Reques Attribute number */ -+#define PCIE_AHB_SSB_REQ_ATTR_S 3 -+#define PCIE_AHB_SSB_REQ_TC 0x000000E0 /* Slave Request TC Field */ -+#define PCIE_AHB_SSB_REQ_TC_S 5 -+ -+/* AHB Master SideBand Ctrl Register */ -+#define PCIE_AHB_MSB(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x74) -+#define PCIE_AHB_MSB_RESP_ATTR 0x00000003 /* Master Response Attribute number */ -+#define PCIE_AHB_MSB_RESP_ATTR_S 0 -+#define PCIE_AHB_MSB_RESP_BAD_EOT 0x00000004 /* Master Response Badeot filed */ -+#define PCIE_AHB_MSB_RESP_BCM 0x00000008 /* Master Response BCM filed */ -+#define PCIE_AHB_MSB_RESP_EP 0x00000010 /* Master Response EP filed */ -+#define PCIE_AHB_MSB_RESP_TD 0x00000020 /* Master Response TD filed */ -+#define PCIE_AHB_MSB_RESP_FUN_NUM 0x000003C0 /* Master Response Function number */ -+#define PCIE_AHB_MSB_RESP_FUN_NUM_S 6 -+ -+/* AHB Control Register, fixed bus enumeration exception */ -+#define PCIE_AHB_CTRL(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0x78) -+#define PCIE_AHB_CTRL_BUS_ERROR_SUPPRESS 0x00000001 -+ -+/* Interrupt Enalbe Register */ -+#define PCIE_IRNEN(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF4) -+#define PCIE_IRNCR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xF8) -+#define PCIE_IRNICR(X) (volatile u32*)(PCIE_APP_PORT_TO_BASE(X) + 0xFC) -+ -+/* PCIe interrupt enable/control/capture register definition */ -+#define PCIE_IRN_AER_REPORT 0x00000001 /* AER Interrupt */ -+#define PCIE_IRN_AER_MSIX 0x00000002 /* Advanced Error MSI-X Interrupt */ -+#define PCIE_IRN_PME 0x00000004 /* PME Interrupt */ -+#define PCIE_IRN_HOTPLUG 0x00000008 /* Hotplug Interrupt */ -+#define PCIE_IRN_RX_VDM_MSG 0x00000010 /* Vendor-Defined Message Interrupt */ -+#define PCIE_IRN_RX_CORRECTABLE_ERR_MSG 0x00000020 /* Correctable Error Message Interrupt */ -+#define PCIE_IRN_RX_NON_FATAL_ERR_MSG 0x00000040 /* Non-fatal Error Message */ -+#define PCIE_IRN_RX_FATAL_ERR_MSG 0x00000080 /* Fatal Error Message */ -+#define PCIE_IRN_RX_PME_MSG 0x00000100 /* PME Message Interrupt */ -+#define PCIE_IRN_RX_PME_TURNOFF_ACK 0x00000200 /* PME Turnoff Ack Message Interrupt */ -+#define PCIE_IRN_AHB_BR_FATAL_ERR 0x00000400 /* AHB Fatal Error Interrupt */ -+#define PCIE_IRN_LINK_AUTO_BW_STATUS 0x00000800 /* Link Auto Bandwidth Status Interrupt */ -+#define PCIE_IRN_BW_MGT 0x00001000 /* Bandwidth Managment Interrupt */ -+#define PCIE_IRN_INTA 0x00002000 /* INTA */ -+#define PCIE_IRN_INTB 0x00004000 /* INTB */ -+#define PCIE_IRN_INTC 0x00008000 /* INTC */ -+#define PCIE_IRN_INTD 0x00010000 /* INTD */ -+#define PCIE_IRN_WAKEUP 0x00020000 /* Wake up Interrupt */ -+ -+#define PCIE_RC_CORE_COMBINED_INT (PCIE_IRN_AER_REPORT | PCIE_IRN_AER_MSIX | PCIE_IRN_PME | \ -+ PCIE_IRN_HOTPLUG | PCIE_IRN_RX_VDM_MSG | PCIE_IRN_RX_CORRECTABLE_ERR_MSG |\ -+ PCIE_IRN_RX_NON_FATAL_ERR_MSG | PCIE_IRN_RX_FATAL_ERR_MSG | \ -+ PCIE_IRN_RX_PME_MSG | PCIE_IRN_RX_PME_TURNOFF_ACK | PCIE_IRN_AHB_BR_FATAL_ERR | \ -+ PCIE_IRN_LINK_AUTO_BW_STATUS | PCIE_IRN_BW_MGT) -+/* PCIe RC Configuration Register */ -+#define PCIE_VDID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x00) -+ -+/* Bit definition from pci_reg.h */ -+#define PCIE_PCICMDSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x04) -+#define PCIE_CCRID(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x08) -+#define PCIE_CLSLTHTBR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x0C) /* EP only */ -+/* BAR0, BAR1,Only necessary if the bridges implements a device-specific register set or memory buffer */ -+#define PCIE_BAR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10) /* Not used*/ -+#define PCIE_BAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14) /* Not used */ -+ -+#define PCIE_BNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x18) /* Mandatory */ -+/* Bus Number Register bits */ -+#define PCIE_BNR_PRIMARY_BUS_NUM 0x000000FF -+#define PCIE_BNR_PRIMARY_BUS_NUM_S 0 -+#define PCIE_PNR_SECONDARY_BUS_NUM 0x0000FF00 -+#define PCIE_PNR_SECONDARY_BUS_NUM_S 8 -+#define PCIE_PNR_SUB_BUS_NUM 0x00FF0000 -+#define PCIE_PNR_SUB_BUS_NUM_S 16 -+ -+/* IO Base/Limit Register bits */ -+#define PCIE_IOBLSECS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x1C) /* RC only */ -+#define PCIE_IOBLSECS_32BIT_IO_ADDR 0x00000001 -+#define PCIE_IOBLSECS_IO_BASE_ADDR 0x000000F0 -+#define PCIE_IOBLSECS_IO_BASE_ADDR_S 4 -+#define PCIE_IOBLSECS_32BIT_IOLIMT 0x00000100 -+#define PCIE_IOBLSECS_IO_LIMIT_ADDR 0x0000F000 -+#define PCIE_IOBLSECS_IO_LIMIT_ADDR_S 12 -+ -+/* Non-prefetchable Memory Base/Limit Register bit */ -+#define PCIE_MBML(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x20) /* RC only */ -+#define PCIE_MBML_MEM_BASE_ADDR 0x0000FFF0 -+#define PCIE_MBML_MEM_BASE_ADDR_S 4 -+#define PCIE_MBML_MEM_LIMIT_ADDR 0xFFF00000 -+#define PCIE_MBML_MEM_LIMIT_ADDR_S 20 -+ -+/* Prefetchable Memory Base/Limit Register bit */ -+#define PCIE_PMBL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x24) /* RC only */ -+#define PCIE_PMBL_64BIT_ADDR 0x00000001 -+#define PCIE_PMBL_UPPER_12BIT 0x0000FFF0 -+#define PCIE_PMBL_UPPER_12BIT_S 4 -+#define PCIE_PMBL_E64MA 0x00010000 -+#define PCIE_PMBL_END_ADDR 0xFFF00000 -+#define PCIE_PMBL_END_ADDR_S 20 -+#define PCIE_PMBU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x28) /* RC only */ -+#define PCIE_PMLU32(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x2C) /* RC only */ -+ -+/* I/O Base/Limit Upper 16 bits register */ -+#define PCIE_IO_BANDL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x30) /* RC only */ -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE 0x0000FFFF -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_BASE_S 0 -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT 0xFFFF0000 -+#define PCIE_IO_BANDL_UPPER_16BIT_IO_LIMIT_S 16 -+ -+#define PCIE_CPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x34) -+#define PCIE_EBBAR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x38) -+ -+/* Interrupt and Secondary Bridge Control Register */ -+#define PCIE_INTRBCTRL(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x3C) -+ -+#define PCIE_INTRBCTRL_INT_LINE 0x000000FF -+#define PCIE_INTRBCTRL_INT_LINE_S 0 -+#define PCIE_INTRBCTRL_INT_PIN 0x0000FF00 -+#define PCIE_INTRBCTRL_INT_PIN_S 8 -+#define PCIE_INTRBCTRL_PARITY_ERR_RESP_ENABLE 0x00010000 /* #PERR */ -+#define PCIE_INTRBCTRL_SERR_ENABLE 0x00020000 /* #SERR */ -+#define PCIE_INTRBCTRL_ISA_ENABLE 0x00040000 /* ISA enable, IO 64KB only */ -+#define PCIE_INTRBCTRL_VGA_ENABLE 0x00080000 /* VGA enable */ -+#define PCIE_INTRBCTRL_VGA_16BIT_DECODE 0x00100000 /* VGA 16bit decode */ -+#define PCIE_INTRBCTRL_RST_SECONDARY_BUS 0x00400000 /* Secondary bus rest, hot rest, 1ms */ -+/* Others are read only */ -+enum { -+ PCIE_INTRBCTRL_INT_NON = 0, -+ PCIE_INTRBCTRL_INTA, -+ PCIE_INTRBCTRL_INTB, -+ PCIE_INTRBCTRL_INTC, -+ PCIE_INTRBCTRL_INTD, -+}; -+ -+#define PCIE_PM_CAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x40) -+ -+/* Power Management Control and Status Register */ -+#define PCIE_PM_CSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x44) -+ -+#define PCIE_PM_CSR_POWER_STATE 0x00000003 /* Power State */ -+#define PCIE_PM_CSR_POWER_STATE_S 0 -+#define PCIE_PM_CSR_SW_RST 0x00000008 /* Soft Reset Enabled */ -+#define PCIE_PM_CSR_PME_ENABLE 0x00000100 /* PME Enable */ -+#define PCIE_PM_CSR_PME_STATUS 0x00008000 /* PME status */ -+ -+/* MSI Capability Register for EP */ -+#define PCIE_MCAPR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x50) -+ -+#define PCIE_MCAPR_MSI_CAP_ID 0x000000FF /* MSI Capability ID */ -+#define PCIE_MCAPR_MSI_CAP_ID_S 0 -+#define PCIE_MCAPR_MSI_NEXT_CAP_PTR 0x0000FF00 /* Next Capability Pointer */ -+#define PCIE_MCAPR_MSI_NEXT_CAP_PTR_S 8 -+#define PCIE_MCAPR_MSI_ENABLE 0x00010000 /* MSI Enable */ -+#define PCIE_MCAPR_MULTI_MSG_CAP 0x000E0000 /* Multiple Message Capable */ -+#define PCIE_MCAPR_MULTI_MSG_CAP_S 17 -+#define PCIE_MCAPR_MULTI_MSG_ENABLE 0x00700000 /* Multiple Message Enable */ -+#define PCIE_MCAPR_MULTI_MSG_ENABLE_S 20 -+#define PCIE_MCAPR_ADDR64_CAP 0X00800000 /* 64-bit Address Capable */ -+ -+/* MSI Message Address Register */ -+#define PCIE_MA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x54) -+ -+#define PCIE_MA_ADDR_MASK 0xFFFFFFFC /* Message Address */ -+ -+/* MSI Message Upper Address Register */ -+#define PCIE_MUA(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x58) -+ -+/* MSI Message Data Register */ -+#define PCIE_MD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x5C) -+ -+#define PCIE_MD_DATA 0x0000FFFF /* Message Data */ -+#define PCIE_MD_DATA_S 0 -+ -+/* PCI Express Capability Register */ -+#define PCIE_XCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70) -+ -+#define PCIE_XCAP_ID 0x000000FF /* PCI Express Capability ID */ -+#define PCIE_XCAP_ID_S 0 -+#define PCIE_XCAP_NEXT_CAP 0x0000FF00 /* Next Capability Pointer */ -+#define PCIE_XCAP_NEXT_CAP_S 8 -+#define PCIE_XCAP_VER 0x000F0000 /* PCI Express Capability Version */ -+#define PCIE_XCAP_VER_S 16 -+#define PCIE_XCAP_DEV_PORT_TYPE 0x00F00000 /* Device Port Type */ -+#define PCIE_XCAP_DEV_PORT_TYPE_S 20 -+#define PCIE_XCAP_SLOT_IMPLEMENTED 0x01000000 /* Slot Implemented */ -+#define PCIE_XCAP_MSG_INT_NUM 0x3E000000 /* Interrupt Message Number */ -+#define PCIE_XCAP_MSG_INT_NUM_S 25 -+ -+/* Device Capability Register */ -+#define PCIE_DCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74) -+ -+#define PCIE_DCAP_MAX_PAYLOAD_SIZE 0x00000007 /* Max Payload size */ -+#define PCIE_DCAP_MAX_PAYLOAD_SIZE_S 0 -+#define PCIE_DCAP_PHANTOM_FUNC 0x00000018 /* Phanton Function, not supported */ -+#define PCIE_DCAP_PHANTOM_FUNC_S 3 -+#define PCIE_DCAP_EXT_TAG 0x00000020 /* Extended Tag Field */ -+#define PCIE_DCAP_EP_L0S_LATENCY 0x000001C0 /* EP L0s latency only */ -+#define PCIE_DCAP_EP_L0S_LATENCY_S 6 -+#define PCIE_DCAP_EP_L1_LATENCY 0x00000E00 /* EP L1 latency only */ -+#define PCIE_DCAP_EP_L1_LATENCY_S 9 -+#define PCIE_DCAP_ROLE_BASE_ERR_REPORT 0x00008000 /* Role Based ERR */ -+ -+/* Maximum payload size supported */ -+enum { -+ PCIE_MAX_PAYLOAD_128 = 0, -+ PCIE_MAX_PAYLOAD_256, -+ PCIE_MAX_PAYLOAD_512, -+ PCIE_MAX_PAYLOAD_1024, -+ PCIE_MAX_PAYLOAD_2048, -+ PCIE_MAX_PAYLOAD_4096, -+}; -+ -+/* Device Control and Status Register */ -+#define PCIE_DCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x78) -+ -+#define PCIE_DCTLSTS_CORRECTABLE_ERR_EN 0x00000001 /* COR-ERR */ -+#define PCIE_DCTLSTS_NONFATAL_ERR_EN 0x00000002 /* Non-fatal ERR */ -+#define PCIE_DCTLSTS_FATAL_ERR_EN 0x00000004 /* Fatal ERR */ -+#define PCIE_DCTLSYS_UR_REQ_EN 0x00000008 /* UR ERR */ -+#define PCIE_DCTLSTS_RELAXED_ORDERING_EN 0x00000010 /* Enable relaxing ordering */ -+#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE 0x000000E0 /* Max payload mask */ -+#define PCIE_DCTLSTS_MAX_PAYLOAD_SIZE_S 5 -+#define PCIE_DCTLSTS_EXT_TAG_EN 0x00000100 /* Extended tag field */ -+#define PCIE_DCTLSTS_PHANTOM_FUNC_EN 0x00000200 /* Phantom Function Enable */ -+#define PCIE_DCTLSTS_AUX_PM_EN 0x00000400 /* AUX Power PM Enable */ -+#define PCIE_DCTLSTS_NO_SNOOP_EN 0x00000800 /* Enable no snoop, except root port*/ -+#define PCIE_DCTLSTS_MAX_READ_SIZE 0x00007000 /* Max Read Request size*/ -+#define PCIE_DCTLSTS_MAX_READ_SIZE_S 12 -+#define PCIE_DCTLSTS_CORRECTABLE_ERR 0x00010000 /* COR-ERR Detected */ -+#define PCIE_DCTLSTS_NONFATAL_ERR 0x00020000 /* Non-Fatal ERR Detected */ -+#define PCIE_DCTLSTS_FATAL_ER 0x00040000 /* Fatal ERR Detected */ -+#define PCIE_DCTLSTS_UNSUPPORTED_REQ 0x00080000 /* UR Detected */ -+#define PCIE_DCTLSTS_AUX_POWER 0x00100000 /* Aux Power Detected */ -+#define PCIE_DCTLSTS_TRANSACT_PENDING 0x00200000 /* Transaction pending */ -+ -+#define PCIE_DCTLSTS_ERR_EN (PCIE_DCTLSTS_CORRECTABLE_ERR_EN | \ -+ PCIE_DCTLSTS_NONFATAL_ERR_EN | PCIE_DCTLSTS_FATAL_ERR_EN | \ -+ PCIE_DCTLSYS_UR_REQ_EN) -+ -+/* Link Capability Register */ -+#define PCIE_LCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7C) -+#define PCIE_LCAP_MAX_LINK_SPEED 0x0000000F /* Max link speed, 0x1 by default */ -+#define PCIE_LCAP_MAX_LINK_SPEED_S 0 -+#define PCIE_LCAP_MAX_LENGTH_WIDTH 0x000003F0 /* Maxium Length Width */ -+#define PCIE_LCAP_MAX_LENGTH_WIDTH_S 4 -+#define PCIE_LCAP_ASPM_LEVEL 0x00000C00 /* Active State Link PM Support */ -+#define PCIE_LCAP_ASPM_LEVEL_S 10 -+#define PCIE_LCAP_L0S_EIXT_LATENCY 0x00007000 /* L0s Exit Latency */ -+#define PCIE_LCAP_L0S_EIXT_LATENCY_S 12 -+#define PCIE_LCAP_L1_EXIT_LATENCY 0x00038000 /* L1 Exit Latency */ -+#define PCIE_LCAP_L1_EXIT_LATENCY_S 15 -+#define PCIE_LCAP_CLK_PM 0x00040000 /* Clock Power Management */ -+#define PCIE_LCAP_SDER 0x00080000 /* Surprise Down Error Reporting */ -+#define PCIE_LCAP_DLL_ACTIVE_REPROT 0x00100000 /* Data Link Layer Active Reporting Capable */ -+#define PCIE_LCAP_PORT_NUM 0xFF0000000 /* Port number */ -+#define PCIE_LCAP_PORT_NUM_S 24 -+ -+/* Maximum Length width definition */ -+#define PCIE_MAX_LENGTH_WIDTH_RES 0x00 -+#define PCIE_MAX_LENGTH_WIDTH_X1 0x01 /* Default */ -+#define PCIE_MAX_LENGTH_WIDTH_X2 0x02 -+#define PCIE_MAX_LENGTH_WIDTH_X4 0x04 -+#define PCIE_MAX_LENGTH_WIDTH_X8 0x08 -+#define PCIE_MAX_LENGTH_WIDTH_X12 0x0C -+#define PCIE_MAX_LENGTH_WIDTH_X16 0x10 -+#define PCIE_MAX_LENGTH_WIDTH_X32 0x20 -+ -+/* Active State Link PM definition */ -+enum { -+ PCIE_ASPM_RES0 = 0, -+ PCIE_ASPM_L0S_ENTRY_SUPPORT, /* L0s */ -+ PCIE_ASPM_RES1, -+ PCIE_ASPM_L0S_L1_ENTRY_SUPPORT, /* L0s and L1, default */ -+}; -+ -+/* L0s Exit Latency definition */ -+enum { -+ PCIE_L0S_EIXT_LATENCY_L64NS = 0, /* < 64 ns */ -+ PCIE_L0S_EIXT_LATENCY_B64A128, /* > 64 ns < 128 ns */ -+ PCIE_L0S_EIXT_LATENCY_B128A256, /* > 128 ns < 256 ns */ -+ PCIE_L0S_EIXT_LATENCY_B256A512, /* > 256 ns < 512 ns */ -+ PCIE_L0S_EIXT_LATENCY_B512TO1U, /* > 512 ns < 1 us */ -+ PCIE_L0S_EIXT_LATENCY_B1A2U, /* > 1 us < 2 us */ -+ PCIE_L0S_EIXT_LATENCY_B2A4U, /* > 2 us < 4 us */ -+ PCIE_L0S_EIXT_LATENCY_M4US, /* > 4 us */ -+}; -+ -+/* L1 Exit Latency definition */ -+enum { -+ PCIE_L1_EXIT_LATENCY_L1US = 0, /* < 1 us */ -+ PCIE_L1_EXIT_LATENCY_B1A2, /* > 1 us < 2 us */ -+ PCIE_L1_EXIT_LATENCY_B2A4, /* > 2 us < 4 us */ -+ PCIE_L1_EXIT_LATENCY_B4A8, /* > 4 us < 8 us */ -+ PCIE_L1_EXIT_LATENCY_B8A16, /* > 8 us < 16 us */ -+ PCIE_L1_EXIT_LATENCY_B16A32, /* > 16 us < 32 us */ -+ PCIE_L1_EXIT_LATENCY_B32A64, /* > 32 us < 64 us */ -+ PCIE_L1_EXIT_LATENCY_M64US, /* > 64 us */ -+}; -+ -+/* Link Control and Status Register */ -+#define PCIE_LCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x80) -+#define PCIE_LCTLSTS_ASPM_ENABLE 0x00000003 /* Active State Link PM Control */ -+#define PCIE_LCTLSTS_ASPM_ENABLE_S 0 -+#define PCIE_LCTLSTS_RCB128 0x00000008 /* Read Completion Boundary 128*/ -+#define PCIE_LCTLSTS_LINK_DISABLE 0x00000010 /* Link Disable */ -+#define PCIE_LCTLSTS_RETRIAN_LINK 0x00000020 /* Retrain Link */ -+#define PCIE_LCTLSTS_COM_CLK_CFG 0x00000040 /* Common Clock Configuration */ -+#define PCIE_LCTLSTS_EXT_SYNC 0x00000080 /* Extended Synch */ -+#define PCIE_LCTLSTS_CLK_PM_EN 0x00000100 /* Enable Clock Powerm Management */ -+#define PCIE_LCTLSTS_LINK_SPEED 0x000F0000 /* Link Speed */ -+#define PCIE_LCTLSTS_LINK_SPEED_S 16 -+#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH 0x03F00000 /* Negotiated Link Width */ -+#define PCIE_LCTLSTS_NEGOTIATED_LINK_WIDTH_S 20 -+#define PCIE_LCTLSTS_RETRAIN_PENDING 0x08000000 /* Link training is ongoing */ -+#define PCIE_LCTLSTS_SLOT_CLK_CFG 0x10000000 /* Slot Clock Configuration */ -+#define PCIE_LCTLSTS_DLL_ACTIVE 0x20000000 /* Data Link Layer Active */ -+ -+/* Slot Capabilities Register */ -+#define PCIE_SLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x84) -+ -+/* Slot Capabilities */ -+#define PCIE_SLCTLSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x88) -+ -+/* Root Control and Capability Register */ -+#define PCIE_RCTLCAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x8C) -+#define PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR 0x00000001 /* #SERR on COR-ERR */ -+#define PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR 0x00000002 /* #SERR on Non-Fatal ERR */ -+#define PCIE_RCTLCAP_SERR_ON_FATAL_ERR 0x00000004 /* #SERR on Fatal ERR */ -+#define PCIE_RCTLCAP_PME_INT_EN 0x00000008 /* PME Interrupt Enable */ -+#define PCIE_RCTLCAP_SERR_ENABLE (PCIE_RCTLCAP_SERR_ON_CORRECTABLE_ERR | \ -+ PCIE_RCTLCAP_SERR_ON_NONFATAL_ERR | PCIE_RCTLCAP_SERR_ON_FATAL_ERR) -+/* Root Status Register */ -+#define PCIE_RSTS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x90) -+#define PCIE_RSTS_PME_REQ_ID 0x0000FFFF /* PME Request ID */ -+#define PCIE_RSTS_PME_REQ_ID_S 0 -+#define PCIE_RSTS_PME_STATUS 0x00010000 /* PME Status */ -+#define PCIE_RSTS_PME_PENDING 0x00020000 /* PME Pending */ -+ -+/* PCI Express Enhanced Capability Header */ -+#define PCIE_ENHANCED_CAP(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x100) -+#define PCIE_ENHANCED_CAP_ID 0x0000FFFF /* PCI Express Extended Capability ID */ -+#define PCIE_ENHANCED_CAP_ID_S 0 -+#define PCIE_ENHANCED_CAP_VER 0x000F0000 /* Capability Version */ -+#define PCIE_ENHANCED_CAP_VER_S 16 -+#define PCIE_ENHANCED_CAP_NEXT_OFFSET 0xFFF00000 /* Next Capability Offset */ -+#define PCIE_ENHANCED_CAP_NEXT_OFFSET_S 20 -+ -+/* Uncorrectable Error Status Register */ -+#define PCIE_UES_R(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x104) -+#define PCIE_DATA_LINK_PROTOCOL_ERR 0x00000010 /* Data Link Protocol Error Status */ -+#define PCIE_SURPRISE_DOWN_ERROR 0x00000020 /* Surprise Down Error Status */ -+#define PCIE_POISONED_TLP 0x00001000 /* Poisoned TLP Status */ -+#define PCIE_FC_PROTOCOL_ERR 0x00002000 /* Flow Control Protocol Error Status */ -+#define PCIE_COMPLETION_TIMEOUT 0x00004000 /* Completion Timeout Status */ -+#define PCIE_COMPLETOR_ABORT 0x00008000 /* Completer Abort Error */ -+#define PCIE_UNEXPECTED_COMPLETION 0x00010000 /* Unexpected Completion Status */ -+#define PCIE_RECEIVER_OVERFLOW 0x00020000 /* Receive Overflow Status */ -+#define PCIE_MALFORNED_TLP 0x00040000 /* Malformed TLP Stauts */ -+#define PCIE_ECRC_ERR 0x00080000 /* ECRC Error Stauts */ -+#define PCIE_UR_REQ 0x00100000 /* Unsupported Request Error Status */ -+#define PCIE_ALL_UNCORRECTABLE_ERR (PCIE_DATA_LINK_PROTOCOL_ERR | PCIE_SURPRISE_DOWN_ERROR | \ -+ PCIE_POISONED_TLP | PCIE_FC_PROTOCOL_ERR | PCIE_COMPLETION_TIMEOUT | \ -+ PCIE_COMPLETOR_ABORT | PCIE_UNEXPECTED_COMPLETION | PCIE_RECEIVER_OVERFLOW |\ -+ PCIE_MALFORNED_TLP | PCIE_ECRC_ERR | PCIE_UR_REQ) -+ -+/* Uncorrectable Error Mask Register, Mask means no report */ -+#define PCIE_UEMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x108) -+ -+/* Uncorrectable Error Severity Register */ -+#define PCIE_UESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x10C) -+ -+/* Correctable Error Status Register */ -+#define PCIE_CESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x110) -+#define PCIE_RX_ERR 0x00000001 /* Receive Error Status */ -+#define PCIE_BAD_TLP 0x00000040 /* Bad TLP Status */ -+#define PCIE_BAD_DLLP 0x00000080 /* Bad DLLP Status */ -+#define PCIE_REPLAY_NUM_ROLLOVER 0x00000100 /* Replay Number Rollover Status */ -+#define PCIE_REPLAY_TIMER_TIMEOUT_ERR 0x00001000 /* Reply Timer Timeout Status */ -+#define PCIE_ADVISORY_NONFTAL_ERR 0x00002000 /* Advisory Non-Fatal Error Status */ -+#define PCIE_CORRECTABLE_ERR (PCIE_RX_ERR | PCIE_BAD_TLP | PCIE_BAD_DLLP | PCIE_REPLAY_NUM_ROLLOVER |\ -+ PCIE_REPLAY_TIMER_TIMEOUT_ERR | PCIE_ADVISORY_NONFTAL_ERR) -+ -+/* Correctable Error Mask Register */ -+#define PCIE_CEMR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x114) -+ -+/* Advanced Error Capabilities and Control Register */ -+#define PCIE_AECCR(X) (volatile u32*)(PCIE_RC_CFG_BASE + 0x118) -+#define PCIE_AECCR_FIRST_ERR_PTR 0x0000001F /* First Error Pointer */ -+#define PCIE_AECCR_FIRST_ERR_PTR_S 0 -+#define PCIE_AECCR_ECRC_GEN_CAP 0x00000020 /* ECRC Generation Capable */ -+#define PCIE_AECCR_ECRC_GEN_EN 0x00000040 /* ECRC Generation Enable */ -+#define PCIE_AECCR_ECRC_CHECK_CAP 0x00000080 /* ECRC Check Capable */ -+#define PCIE_AECCR_ECRC_CHECK_EN 0x00000100 /* ECRC Check Enable */ -+ -+/* Header Log Register 1 */ -+#define PCIE_HLR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x11C) -+ -+/* Header Log Register 2 */ -+#define PCIE_HLR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x120) -+ -+/* Header Log Register 3 */ -+#define PCIE_HLR3(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x124) -+ -+/* Header Log Register 4 */ -+#define PCIE_HLR4(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x128) -+ -+/* Root Error Command Register */ -+#define PCIE_RECR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x12C) -+#define PCIE_RECR_CORRECTABLE_ERR_REPORT_EN 0x00000001 /* COR-ERR */ -+#define PCIE_RECR_NONFATAL_ERR_REPORT_EN 0x00000002 /* Non-Fatal ERR */ -+#define PCIE_RECR_FATAL_ERR_REPORT_EN 0x00000004 /* Fatal ERR */ -+#define PCIE_RECR_ERR_REPORT_EN (PCIE_RECR_CORRECTABLE_ERR_REPORT_EN | \ -+ PCIE_RECR_NONFATAL_ERR_REPORT_EN | PCIE_RECR_FATAL_ERR_REPORT_EN) -+ -+/* Root Error Status Register */ -+#define PCIE_RESR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x130) -+#define PCIE_RESR_CORRECTABLE_ERR 0x00000001 /* COR-ERR Receveid */ -+#define PCIE_RESR_MULTI_CORRECTABLE_ERR 0x00000002 /* Multiple COR-ERR Received */ -+#define PCIE_RESR_FATAL_NOFATAL_ERR 0x00000004 /* ERR Fatal/Non-Fatal Received */ -+#define PCIE_RESR_MULTI_FATAL_NOFATAL_ERR 0x00000008 /* Multiple ERR Fatal/Non-Fatal Received */ -+#define PCIE_RESR_FIRST_UNCORRECTABLE_FATAL_ERR 0x00000010 /* First UN-COR Fatal */ -+#define PCIR_RESR_NON_FATAL_ERR 0x00000020 /* Non-Fatal Error Message Received */ -+#define PCIE_RESR_FATAL_ERR 0x00000040 /* Fatal Message Received */ -+#define PCIE_RESR_AER_INT_MSG_NUM 0xF8000000 /* Advanced Error Interrupt Message Number */ -+#define PCIE_RESR_AER_INT_MSG_NUM_S 27 -+ -+/* Error Source Indentification Register */ -+#define PCIE_ESIR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x134) -+#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID 0x0000FFFF -+#define PCIE_ESIR_CORRECTABLE_ERR_SRC_ID_S 0 -+#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID 0xFFFF0000 -+#define PCIE_ESIR_FATAL_NON_FATAL_SRC_ID_S 16 -+ -+/* VC Enhanced Capability Header */ -+#define PCIE_VC_ECH(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x140) -+ -+/* Port VC Capability Register */ -+#define PCIE_PVC1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x144) -+#define PCIE_PVC1_EXT_VC_CNT 0x00000007 /* Extended VC Count */ -+#define PCIE_PVC1_EXT_VC_CNT_S 0 -+#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT 0x00000070 /* Low Priority Extended VC Count */ -+#define PCIE_PVC1_LOW_PRI_EXT_VC_CNT_S 4 -+#define PCIE_PVC1_REF_CLK 0x00000300 /* Reference Clock */ -+#define PCIE_PVC1_REF_CLK_S 8 -+#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE 0x00000C00 /* Port Arbitration Table Entry Size */ -+#define PCIE_PVC1_PORT_ARB_TAB_ENTRY_SIZE_S 10 -+ -+/* Extended Virtual Channel Count Defintion */ -+#define PCIE_EXT_VC_CNT_MIN 0 -+#define PCIE_EXT_VC_CNT_MAX 7 -+ -+/* Port Arbitration Table Entry Size Definition */ -+enum { -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S1BIT = 0, -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S2BIT, -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S4BIT, -+ PCIE_PORT_ARB_TAB_ENTRY_SIZE_S8BIT, -+}; -+ -+/* Port VC Capability Register 2 */ -+#define PCIE_PVC2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x148) -+#define PCIE_PVC2_VC_ARB_16P_FIXED_WRR 0x00000001 /* HW Fixed arbitration, 16 phase WRR */ -+#define PCIE_PVC2_VC_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ -+#define PCIE_PVC2_VC_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ -+#define PCIE_PVC2_VC_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ -+#define PCIE_PVC2_VC_ARB_WRR 0x0000000F -+#define PCIE_PVC2_VC_ARB_TAB_OFFSET 0xFF000000 /* VC arbitration table offset, not support */ -+#define PCIE_PVC2_VC_ARB_TAB_OFFSET_S 24 -+ -+/* Port VC Control and Status Register */ -+#define PCIE_PVCCRSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x14C) -+#define PCIE_PVCCRSR_LOAD_VC_ARB_TAB 0x00000001 /* Load VC Arbitration Table */ -+#define PCIE_PVCCRSR_VC_ARB_SEL 0x0000000E /* VC Arbitration Select */ -+#define PCIE_PVCCRSR_VC_ARB_SEL_S 1 -+#define PCIE_PVCCRSR_VC_ARB_TAB_STATUS 0x00010000 /* Arbitration Status */ -+ -+/* VC0 Resource Capability Register */ -+#define PCIE_VC0_RC(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x150) -+#define PCIE_VC0_RC_PORT_ARB_HW_FIXED 0x00000001 /* HW Fixed arbitration */ -+#define PCIE_VC0_RC_PORT_ARB_32P_WRR 0x00000002 /* 32 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_64P_WRR 0x00000004 /* 64 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_128P_WRR 0x00000008 /* 128 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_TM_128P_WRR 0x00000010 /* Time-based 128 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB_TM_256P_WRR 0x00000020 /* Time-based 256 phase WRR */ -+#define PCIE_VC0_RC_PORT_ARB (PCIE_VC0_RC_PORT_ARB_HW_FIXED | PCIE_VC0_RC_PORT_ARB_32P_WRR |\ -+ PCIE_VC0_RC_PORT_ARB_64P_WRR | PCIE_VC0_RC_PORT_ARB_128P_WRR | \ -+ PCIE_VC0_RC_PORT_ARB_TM_128P_WRR | PCIE_VC0_RC_PORT_ARB_TM_256P_WRR) -+ -+#define PCIE_VC0_RC_REJECT_SNOOP 0x00008000 /* Reject Snoop Transactioin */ -+#define PCIE_VC0_RC_MAX_TIMESLOTS 0x007F0000 /* Maximum time Slots */ -+#define PCIE_VC0_RC_MAX_TIMESLOTS_S 16 -+#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET 0xFF000000 /* Port Arbitration Table Offset */ -+#define PCIE_VC0_RC_PORT_ARB_TAB_OFFSET_S 24 -+ -+/* VC0 Resource Control Register */ -+#define PCIE_VC0_RC0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x154) -+#define PCIE_VC0_RC0_TVM0 0x00000001 /* TC0 and VC0 */ -+#define PCIE_VC0_RC0_TVM1 0x00000002 /* TC1 and VC1 */ -+#define PCIE_VC0_RC0_TVM2 0x00000004 /* TC2 and VC2 */ -+#define PCIE_VC0_RC0_TVM3 0x00000008 /* TC3 and VC3 */ -+#define PCIE_VC0_RC0_TVM4 0x00000010 /* TC4 and VC4 */ -+#define PCIE_VC0_RC0_TVM5 0x00000020 /* TC5 and VC5 */ -+#define PCIE_VC0_RC0_TVM6 0x00000040 /* TC6 and VC6 */ -+#define PCIE_VC0_RC0_TVM7 0x00000080 /* TC7 and VC7 */ -+#define PCIE_VC0_RC0_TC_VC 0x000000FF /* TC/VC mask */ -+ -+#define PCIE_VC0_RC0_LOAD_PORT_ARB_TAB 0x00010000 /* Load Port Arbitration Table */ -+#define PCIE_VC0_RC0_PORT_ARB_SEL 0x000E0000 /* Port Arbitration Select */ -+#define PCIE_VC0_RC0_PORT_ARB_SEL_S 17 -+#define PCIE_VC0_RC0_VC_ID 0x07000000 /* VC ID */ -+#define PCIE_VC0_RC0_VC_ID_S 24 -+#define PCIE_VC0_RC0_VC_EN 0x80000000 /* VC Enable */ -+ -+/* VC0 Resource Status Register */ -+#define PCIE_VC0_RSR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x158) -+#define PCIE_VC0_RSR0_PORT_ARB_TAB_STATUS 0x00010000 /* Port Arbitration Table Status,not used */ -+#define PCIE_VC0_RSR0_VC_NEG_PENDING 0x00020000 /* VC Negotiation Pending */ -+ -+/* Ack Latency Timer and Replay Timer Register */ -+#define PCIE_ALTRT(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x700) -+#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT 0x0000FFFF /* Round Trip Latency Time Limit */ -+#define PCIE_ALTRT_ROUND_TRIP_LATENCY_LIMIT_S 0 -+#define PCIE_ALTRT_REPLAY_TIME_LIMIT 0xFFFF0000 /* Replay Time Limit */ -+#define PCIE_ALTRT_REPLAY_TIME_LIMIT_S 16 -+ -+/* Other Message Register */ -+#define PCIE_OMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x704) -+ -+/* Port Force Link Register */ -+#define PCIE_PFLR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x708) -+#define PCIE_PFLR_LINK_NUM 0x000000FF /* Link Number */ -+#define PCIE_PFLR_LINK_NUM_S 0 -+#define PCIE_PFLR_FORCE_LINK 0x00008000 /* Force link */ -+#define PCIE_PFLR_LINK_STATE 0x003F0000 /* Link State */ -+#define PCIE_PFLR_LINK_STATE_S 16 -+#define PCIE_PFLR_LOW_POWER_ENTRY_CNT 0xFF000000 /* Low Power Entrance Count, only for EP */ -+#define PCIE_PFLR_LOW_POWER_ENTRY_CNT_S 24 -+ -+/* Ack Frequency Register */ -+#define PCIE_AFR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x70C) -+#define PCIE_AFR_AF 0x000000FF /* Ack Frequency */ -+#define PCIE_AFR_AF_S 0 -+#define PCIE_AFR_FTS_NUM 0x0000FF00 /* The number of Fast Training Sequence from L0S to L0 */ -+#define PCIE_AFR_FTS_NUM_S 8 -+#define PCIE_AFR_COM_FTS_NUM 0x00FF0000 /* N_FTS; when common clock is used*/ -+#define PCIE_AFR_COM_FTS_NUM_S 16 -+#define PCIE_AFR_L0S_ENTRY_LATENCY 0x07000000 /* L0s Entrance Latency */ -+#define PCIE_AFR_L0S_ENTRY_LATENCY_S 24 -+#define PCIE_AFR_L1_ENTRY_LATENCY 0x38000000 /* L1 Entrance Latency */ -+#define PCIE_AFR_L1_ENTRY_LATENCY_S 27 -+#define PCIE_AFR_FTS_NUM_DEFAULT 32 -+#define PCIE_AFR_L0S_ENTRY_LATENCY_DEFAULT 7 -+#define PCIE_AFR_L1_ENTRY_LATENCY_DEFAULT 5 -+ -+/* Port Link Control Register */ -+#define PCIE_PLCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x710) -+#define PCIE_PLCR_OTHER_MSG_REQ 0x00000001 /* Other Message Request */ -+#define PCIE_PLCR_SCRAMBLE_DISABLE 0x00000002 /* Scramble Disable */ -+#define PCIE_PLCR_LOOPBACK_EN 0x00000004 /* Loopback Enable */ -+#define PCIE_PLCR_LTSSM_HOT_RST 0x00000008 /* Force LTSSM to the hot reset */ -+#define PCIE_PLCR_DLL_LINK_EN 0x00000020 /* Enable Link initialization */ -+#define PCIE_PLCR_FAST_LINK_SIM_EN 0x00000080 /* Sets all internal timers to fast mode for simulation purposes */ -+#define PCIE_PLCR_LINK_MODE 0x003F0000 /* Link Mode Enable Mask */ -+#define PCIE_PLCR_LINK_MODE_S 16 -+#define PCIE_PLCR_CORRUPTED_CRC_EN 0x02000000 /* Enabled Corrupt CRC */ -+ -+/* Lane Skew Register */ -+#define PCIE_LSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x714) -+#define PCIE_LSR_LANE_SKEW_NUM 0x00FFFFFF /* Insert Lane Skew for Transmit, not applicable */ -+#define PCIE_LSR_LANE_SKEW_NUM_S 0 -+#define PCIE_LSR_FC_DISABLE 0x01000000 /* Disable of Flow Control */ -+#define PCIE_LSR_ACKNAK_DISABLE 0x02000000 /* Disable of Ack/Nak */ -+#define PCIE_LSR_LANE_DESKEW_DISABLE 0x80000000 /* Disable of Lane-to-Lane Skew */ -+ -+/* Symbol Number Register */ -+#define PCIE_SNR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x718) -+#define PCIE_SNR_TS 0x0000000F /* Number of TS Symbol */ -+#define PCIE_SNR_TS_S 0 -+#define PCIE_SNR_SKP 0x00000700 /* Number of SKP Symbol */ -+#define PCIE_SNR_SKP_S 8 -+#define PCIE_SNR_REPLAY_TIMER 0x0007C000 /* Timer Modifier for Replay Timer */ -+#define PCIE_SNR_REPLAY_TIMER_S 14 -+#define PCIE_SNR_ACKNAK_LATENCY_TIMER 0x00F80000 /* Timer Modifier for Ack/Nak Latency Timer */ -+#define PCIE_SNR_ACKNAK_LATENCY_TIMER_S 19 -+#define PCIE_SNR_FC_TIMER 0x1F000000 /* Timer Modifier for Flow Control Watchdog Timer */ -+#define PCIE_SNR_FC_TIMER_S 28 -+ -+/* Symbol Timer Register and Filter Mask Register 1 */ -+#define PCIE_STRFMR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x71C) -+#define PCIE_STRFMR_SKP_INTERVAL 0x000007FF /* SKP lnterval Value */ -+#define PCIE_STRFMR_SKP_INTERVAL_S 0 -+#define PCIE_STRFMR_FC_WDT_DISABLE 0x00008000 /* Disable of FC Watchdog Timer */ -+#define PCIE_STRFMR_TLP_FUNC_MISMATCH_OK 0x00010000 /* Mask Function Mismatch Filtering for Incoming Requests */ -+#define PCIE_STRFMR_POISONED_TLP_OK 0x00020000 /* Mask Poisoned TLP Filtering */ -+#define PCIE_STRFMR_BAR_MATCH_OK 0x00040000 /* Mask BAR Match Filtering */ -+#define PCIE_STRFMR_TYPE1_CFG_REQ_OK 0x00080000 /* Mask Type 1 Configuration Request Filtering */ -+#define PCIE_STRFMR_LOCKED_REQ_OK 0x00100000 /* Mask Locked Request Filtering */ -+#define PCIE_STRFMR_CPL_TAG_ERR_RULES_OK 0x00200000 /* Mask Tag Error Rules for Received Completions */ -+#define PCIE_STRFMR_CPL_REQUESTOR_ID_MISMATCH_OK 0x00400000 /* Mask Requester ID Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_FUNC_MISMATCH_OK 0x00800000 /* Mask Function Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_TC_MISMATCH_OK 0x01000000 /* Mask Traffic Class Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_ATTR_MISMATCH_OK 0x02000000 /* Mask Attribute Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_CPL_LENGTH_MISMATCH_OK 0x04000000 /* Mask Length Mismatch Error for Received Completions */ -+#define PCIE_STRFMR_TLP_ECRC_ERR_OK 0x08000000 /* Mask ECRC Error Filtering */ -+#define PCIE_STRFMR_CPL_TLP_ECRC_OK 0x10000000 /* Mask ECRC Error Filtering for Completions */ -+#define PCIE_STRFMR_RX_TLP_MSG_NO_DROP 0x20000000 /* Send Message TLPs */ -+#define PCIE_STRFMR_RX_IO_TRANS_ENABLE 0x40000000 /* Mask Filtering of received I/O Requests */ -+#define PCIE_STRFMR_RX_CFG_TRANS_ENABLE 0x80000000 /* Mask Filtering of Received Configuration Requests */ -+ -+#define PCIE_DEF_SKP_INTERVAL 700 /* 1180 ~1538 , 125MHz * 2, 250MHz * 1 */ -+ -+/* Filter Masker Register 2 */ -+#define PCIE_FMR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x720) -+#define PCIE_FMR2_VENDOR_MSG0_PASSED_TO_TRGT1 0x00000001 /* Mask RADM Filtering and Error Handling Rules */ -+#define PCIE_FMR2_VENDOR_MSG1_PASSED_TO_TRGT1 0x00000002 /* Mask RADM Filtering and Error Handling Rules */ -+ -+/* Debug Register 0 */ -+#define PCIE_DBR0(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x728) -+ -+/* Debug Register 1 */ -+#define PCIE_DBR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x72C) -+ -+/* Transmit Posted FC Credit Status Register */ -+#define PCIE_TPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x730) -+#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS 0x00000FFF /* Transmit Posted Data FC Credits */ -+#define PCIE_TPFCS_TX_P_DATA_FC_CREDITS_S 0 -+#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS 0x000FF000 /* Transmit Posted Header FC Credits */ -+#define PCIE_TPFCS_TX_P_HDR_FC_CREDITS_S 12 -+ -+/* Transmit Non-Posted FC Credit Status */ -+#define PCIE_TNPFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x734) -+#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS 0x00000FFF /* Transmit Non-Posted Data FC Credits */ -+#define PCIE_TNPFCS_TX_NP_DATA_FC_CREDITS_S 0 -+#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS 0x000FF000 /* Transmit Non-Posted Header FC Credits */ -+#define PCIE_TNPFCS_TX_NP_HDR_FC_CREDITS_S 12 -+ -+/* Transmit Complete FC Credit Status Register */ -+#define PCIE_TCFCS(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x738) -+#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS 0x00000FFF /* Transmit Completion Data FC Credits */ -+#define PCIE_TCFCS_TX_CPL_DATA_FC_CREDITS_S 0 -+#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS 0x000FF000 /* Transmit Completion Header FC Credits */ -+#define PCIE_TCFCS_TX_CPL_HDR_FC_CREDITS_S 12 -+ -+/* Queue Status Register */ -+#define PCIE_QSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x73C) -+#define PCIE_QSR_WAIT_UPDATE_FC_DLL 0x00000001 /* Received TLP FC Credits Not Returned */ -+#define PCIE_QSR_TX_RETRY_BUF_NOT_EMPTY 0x00000002 /* Transmit Retry Buffer Not Empty */ -+#define PCIE_QSR_RX_QUEUE_NOT_EMPTY 0x00000004 /* Received Queue Not Empty */ -+ -+/* VC Transmit Arbitration Register 1 */ -+#define PCIE_VCTAR1(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x740) -+#define PCIE_VCTAR1_WRR_WEIGHT_VC0 0x000000FF /* WRR Weight for VC0 */ -+#define PCIE_VCTAR1_WRR_WEIGHT_VC1 0x0000FF00 /* WRR Weight for VC1 */ -+#define PCIE_VCTAR1_WRR_WEIGHT_VC2 0x00FF0000 /* WRR Weight for VC2 */ -+#define PCIE_VCTAR1_WRR_WEIGHT_VC3 0xFF000000 /* WRR Weight for VC3 */ -+ -+/* VC Transmit Arbitration Register 2 */ -+#define PCIE_VCTAR2(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x744) -+#define PCIE_VCTAR2_WRR_WEIGHT_VC4 0x000000FF /* WRR Weight for VC4 */ -+#define PCIE_VCTAR2_WRR_WEIGHT_VC5 0x0000FF00 /* WRR Weight for VC5 */ -+#define PCIE_VCTAR2_WRR_WEIGHT_VC6 0x00FF0000 /* WRR Weight for VC6 */ -+#define PCIE_VCTAR2_WRR_WEIGHT_VC7 0xFF000000 /* WRR Weight for VC7 */ -+ -+/* VC0 Posted Receive Queue Control Register */ -+#define PCIE_VC0_PRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x748) -+#define PCIE_VC0_PRQCR_P_DATA_CREDITS 0x00000FFF /* VC0 Posted Data Credits */ -+#define PCIE_VC0_PRQCR_P_DATA_CREDITS_S 0 -+#define PCIE_VC0_PRQCR_P_HDR_CREDITS 0x000FF000 /* VC0 Posted Header Credits */ -+#define PCIE_VC0_PRQCR_P_HDR_CREDITS_S 12 -+#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE 0x00E00000 /* VC0 Posted TLP Queue Mode */ -+#define PCIE_VC0_PRQCR_P_TLP_QUEUE_MODE_S 20 -+#define PCIE_VC0_PRQCR_TLP_RELAX_ORDER 0x40000000 /* TLP Type Ordering for VC0 */ -+#define PCIE_VC0_PRQCR_VC_STRICT_ORDER 0x80000000 /* VC0 Ordering for Receive Queues */ -+ -+/* VC0 Non-Posted Receive Queue Control */ -+#define PCIE_VC0_NPRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x74C) -+#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS 0x00000FFF /* VC0 Non-Posted Data Credits */ -+#define PCIE_VC0_NPRQCR_NP_DATA_CREDITS_S 0 -+#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS 0x000FF000 /* VC0 Non-Posted Header Credits */ -+#define PCIE_VC0_NPRQCR_NP_HDR_CREDITS_S 12 -+#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE 0x00E00000 /* VC0 Non-Posted TLP Queue Mode */ -+#define PCIE_VC0_NPRQCR_NP_TLP_QUEUE_MODE_S 20 -+ -+/* VC0 Completion Receive Queue Control */ -+#define PCIE_VC0_CRQCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x750) -+#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS 0x00000FFF /* VC0 Completion TLP Queue Mode */ -+#define PCIE_VC0_CRQCR_CPL_DATA_CREDITS_S 0 -+#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS 0x000FF000 /* VC0 Completion Header Credits */ -+#define PCIE_VC0_CRQCR_CPL_HDR_CREDITS_S 12 -+#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE 0x00E00000 /* VC0 Completion Data Credits */ -+#define PCIE_VC0_CRQCR_CPL_TLP_QUEUE_MODE_S 21 -+ -+/* Applicable to the above three registers */ -+enum { -+ PCIE_VC0_TLP_QUEUE_MODE_STORE_FORWARD = 1, -+ PCIE_VC0_TLP_QUEUE_MODE_CUT_THROUGH = 2, -+ PCIE_VC0_TLP_QUEUE_MODE_BYPASS = 4, -+}; -+ -+/* VC0 Posted Buffer Depth Register */ -+#define PCIE_VC0_PBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7A8) -+#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Posted Data Queue Depth */ -+#define PCIE_VC0_PBD_P_DATA_QUEUE_ENTRIES_S 0 -+#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Posted Header Queue Depth */ -+#define PCIE_VC0_PBD_P_HDR_QUEUE_ENTRIES_S 16 -+ -+/* VC0 Non-Posted Buffer Depth Register */ -+#define PCIE_VC0_NPBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7AC) -+#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES 0x00003FFF /* VC0 Non-Posted Data Queue Depth */ -+#define PCIE_VC0_NPBD_NP_DATA_QUEUE_ENTRIES_S 0 -+#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Non-Posted Header Queue Depth */ -+#define PCIE_VC0_NPBD_NP_HDR_QUEUE_ENTRIES_S 16 -+ -+/* VC0 Completion Buffer Depth Register */ -+#define PCIE_VC0_CBD(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x7B0) -+#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES 0x00003FFF /* C0 Completion Data Queue Depth */ -+#define PCIE_VC0_CBD_CPL_DATA_QUEUE_ENTRIES_S 0 -+#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES 0x03FF0000 /* VC0 Completion Header Queue Depth */ -+#define PCIE_VC0_CBD_CPL_HDR_QUEUE_ENTRIES_S 16 -+ -+/* PHY Status Register, all zeros in VR9 */ -+#define PCIE_PHYSR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x810) -+ -+/* PHY Control Register, all zeros in VR9 */ -+#define PCIE_PHYCR(X) (volatile u32*)(PCIE_RC_PORT_TO_BASE(X) + 0x814) -+ -+/* -+ * PCIe PDI PHY register definition, suppose all the following -+ * stuff is confidential. -+ * XXX, detailed bit definition -+ */ -+#define PCIE_PHY_PLL_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x22 << 1)) -+#define PCIE_PHY_PLL_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x23 << 1)) -+#define PCIE_PHY_PLL_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x24 << 1)) -+#define PCIE_PHY_PLL_CTRL4(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x25 << 1)) -+#define PCIE_PHY_PLL_CTRL5(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x26 << 1)) -+#define PCIE_PHY_PLL_CTRL6(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x27 << 1)) -+#define PCIE_PHY_PLL_CTRL7(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x28 << 1)) -+#define PCIE_PHY_PLL_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x29 << 1)) -+#define PCIE_PHY_PLL_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2A << 1)) -+#define PCIE_PHY_PLL_A_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2B << 1)) -+#define PCIE_PHY_PLL_STATUS(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x2C << 1)) -+ -+#define PCIE_PHY_TX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x30 << 1)) -+#define PCIE_PHY_TX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x31 << 1)) -+#define PCIE_PHY_TX1_CTRL3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x32 << 1)) -+#define PCIE_PHY_TX1_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x33 << 1)) -+#define PCIE_PHY_TX1_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x34 << 1)) -+#define PCIE_PHY_TX1_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x35 << 1)) -+#define PCIE_PHY_TX1_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x36 << 1)) -+#define PCIE_PHY_TX1_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x37 << 1)) -+ -+#define PCIE_PHY_TX2_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x38 << 1)) -+#define PCIE_PHY_TX2_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x39 << 1)) -+#define PCIE_PHY_TX2_A_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3B << 1)) -+#define PCIE_PHY_TX2_A_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3C << 1)) -+#define PCIE_PHY_TX2_MOD1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3D << 1)) -+#define PCIE_PHY_TX2_MOD2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3E << 1)) -+#define PCIE_PHY_TX2_MOD3(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x3F << 1)) -+ -+#define PCIE_PHY_RX1_CTRL1(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x50 << 1)) -+#define PCIE_PHY_RX1_CTRL2(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x51 << 1)) -+#define PCIE_PHY_RX1_CDR(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x52 << 1)) -+#define PCIE_PHY_RX1_EI(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x53 << 1)) -+#define PCIE_PHY_RX1_A_CTRL(X) (PCIE_PHY_PORT_TO_BASE(X) + (0x55 << 1)) -+ -+/* Interrupt related stuff */ -+#define PCIE_LEGACY_DISABLE 0 -+#define PCIE_LEGACY_INTA 1 -+#define PCIE_LEGACY_INTB 2 -+#define PCIE_LEGACY_INTC 3 -+#define PCIE_LEGACY_INTD 4 -+#define PCIE_LEGACY_INT_MAX PCIE_LEGACY_INTD -+ -+#define PCIE_IRQ_LOCK(lock) do { \ -+ unsigned long flags; \ -+ spin_lock_irqsave(&(lock), flags); -+#define PCIE_IRQ_UNLOCK(lock) \ -+ spin_unlock_irqrestore(&(lock), flags); \ -+} while (0) -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) -+#define IRQF_SHARED SA_SHIRQ -+#endif -+ -+#define PCIE_MSG_MSI 0x00000001 -+#define PCIE_MSG_ISR 0x00000002 -+#define PCIE_MSG_FIXUP 0x00000004 -+#define PCIE_MSG_READ_CFG 0x00000008 -+#define PCIE_MSG_WRITE_CFG 0x00000010 -+#define PCIE_MSG_CFG (PCIE_MSG_READ_CFG | PCIE_MSG_WRITE_CFG) -+#define PCIE_MSG_REG 0x00000020 -+#define PCIE_MSG_INIT 0x00000040 -+#define PCIE_MSG_ERR 0x00000080 -+#define PCIE_MSG_PHY 0x00000100 -+#define PCIE_MSG_ANY 0x000001ff -+ -+#define IFX_PCIE_PORT0 0 -+#define IFX_PCIE_PORT1 1 -+ -+#ifdef CONFIG_IFX_PCIE_2ND_CORE -+#define IFX_PCIE_CORE_NR 2 -+#else -+#define IFX_PCIE_CORE_NR 1 -+#endif -+ -+//#define IFX_PCIE_ERROR_INT -+ -+//#define IFX_PCIE_DBG -+ -+#if defined(IFX_PCIE_DBG) -+#define IFX_PCIE_PRINT(_m, _fmt, args...) do { \ -+ if (g_pcie_debug_flag & (_m)) { \ -+ ifx_pcie_debug((_fmt), ##args); \ -+ } \ -+} while (0) -+ -+#define INLINE -+#else -+#define IFX_PCIE_PRINT(_m, _fmt, args...) \ -+ do {} while(0) -+#define INLINE inline -+#endif -+ -+struct ifx_pci_controller { -+ struct pci_controller pcic; -+ -+ /* RC specific, per host bus information */ -+ u32 port; /* Port index, 0 -- 1st core, 1 -- 2nd core */ -+}; -+ -+typedef struct ifx_pcie_ir_irq { -+ const unsigned int irq; -+ const char name[16]; -+}ifx_pcie_ir_irq_t; -+ -+typedef struct ifx_pcie_legacy_irq{ -+ const u32 irq_bit; -+ const int irq; -+}ifx_pcie_legacy_irq_t; -+ -+typedef struct ifx_pcie_irq { -+ ifx_pcie_ir_irq_t ir_irq; -+ ifx_pcie_legacy_irq_t legacy_irq[PCIE_LEGACY_INT_MAX]; -+}ifx_pcie_irq_t; -+ -+extern u32 g_pcie_debug_flag; -+extern void ifx_pcie_debug(const char *fmt, ...); -+extern void pcie_phy_clock_mode_setup(int pcie_port); -+extern void pcie_msi_pic_init(int pcie_port); -+extern u32 ifx_pcie_bus_enum_read_hack(int where, u32 value); -+extern u32 ifx_pcie_bus_enum_write_hack(int where, u32 value); -+ -+ -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define IFX_PCIE_GPIO_RESET 38 -+#define IFX_REG_R32 ltq_r32 -+#define IFX_REG_W32 ltq_w32 -+#define CONFIG_IFX_PCIE_HW_SWAP -+#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) -+#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) -+#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ -+ -+#define IFX_RCU (KSEG1 | 0x1F203000) -+#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ -+#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ -+#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ -+#define CONFIG_IFX_PCIE_PHY_36MHZ_MODE -+ -+#define IFX_PMU1_MODULE_PCIE_PHY (0) -+#define IFX_PMU1_MODULE_PCIE_CTRL (1) -+#define IFX_PMU1_MODULE_PDI (4) -+#define IFX_PMU1_MODULE_MSI (5) -+ -+#define IFX_PMU_MODULE_PCIE_L0_CLK (31) -+ -+ -+static inline void pcie_ep_gpio_rst_init(int pcie_port) -+{ -+} -+ -+static inline void pcie_ahb_pmu_setup(void) -+{ -+ struct clk *clk; -+ clk = clk_get_sys("ltq_pcie", "ahb"); -+ clk_enable(clk); -+ //ltq_pmu_enable(PMU_AHBM | PMU_AHBS); -+} -+ -+static inline void pcie_rcu_endian_setup(int pcie_port) -+{ -+ u32 reg; -+ -+ reg = IFX_REG_R32(IFX_RCU_AHB_ENDIAN); -+#ifdef CONFIG_IFX_PCIE_HW_SWAP -+ reg |= IFX_RCU_AHB_BE_PCIE_M; -+ reg |= IFX_RCU_AHB_BE_PCIE_S; -+ reg &= ~IFX_RCU_AHB_BE_XBAR_M; -+#else -+ reg |= IFX_RCU_AHB_BE_PCIE_M; -+ reg &= ~IFX_RCU_AHB_BE_PCIE_S; -+ reg &= ~IFX_RCU_AHB_BE_XBAR_M; -+#endif /* CONFIG_IFX_PCIE_HW_SWAP */ -+ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -+ IFX_PCIE_PRINT(PCIE_MSG_REG, "%s IFX_RCU_AHB_ENDIAN: 0x%08x\n", __func__, IFX_REG_R32(IFX_RCU_AHB_ENDIAN)); -+} -+ -+static inline void pcie_phy_pmu_enable(int pcie_port) -+{ -+ struct clk *clk; -+ clk = clk_get_sys("ltq_pcie", "phy"); -+ clk_enable(clk); -+ //ltq_pmu1_enable(1<PCIe and PDI endianness */ -+ reg |= IFX_RCU_AHB_BE_PCIE_PDI; -+ IFX_REG_W32(reg, IFX_RCU_AHB_ENDIAN); -+} -+ -+static inline void pcie_pdi_pmu_enable(int pcie_port) -+{ -+ struct clk *clk; -+ clk = clk_get_sys("ltq_pcie", "pdi"); -+ clk_enable(clk); -+ //ltq_pmu1_enable(1< 1) { -+ tbus_number -= pcibios_1st_host_bus_nr(); -+ } -+#endif /* CONFIG_IFX_PCI */ -+ return tbus_number; -+} -+ -+static inline u32 -+ifx_pcie_bus_enum_hack(struct pci_bus *bus, u32 devfn, int where, u32 value, int pcie_port, int read) -+{ -+ struct pci_dev *pdev; -+ u32 tvalue = value; -+ -+ /* Sanity check */ -+ pdev = pci_get_slot(bus, devfn); -+ if (pdev == NULL) { -+ return tvalue; -+ } -+ -+ /* Only care about PCI bridge */ -+ if (pdev->hdr_type != PCI_HEADER_TYPE_BRIDGE) { -+ return tvalue; -+ } -+ -+ if (read) { /* Read hack */ -+ #ifdef CONFIG_IFX_PCI -+ if (pcibios_host_nr() > 1) { -+ tvalue = ifx_pcie_bus_enum_read_hack(where, tvalue); -+ } -+ #endif /* CONFIG_IFX_PCI */ -+ } -+ else { /* Write hack */ -+ #ifdef CONFIG_IFX_PCI -+ if (pcibios_host_nr() > 1) { -+ tvalue = ifx_pcie_bus_enum_write_hack(where, tvalue); -+ } -+ #endif -+ } -+ return tvalue; -+} -+ -+#endif /* IFXMIPS_PCIE_VR9_H */ -+ diff --git a/target/linux/lantiq/patches-3.3/0052-MIPS-lantiq-make-GPIO3-work-on-AR9.patch b/target/linux/lantiq/patches-3.3/0052-MIPS-lantiq-make-GPIO3-work-on-AR9.patch deleted file mode 100644 index 287d963114..0000000000 --- a/target/linux/lantiq/patches-3.3/0052-MIPS-lantiq-make-GPIO3-work-on-AR9.patch +++ /dev/null @@ -1,223 +0,0 @@ -From 85859883ce603bf0db782c03294873dad39176e5 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sat, 13 Aug 2011 13:59:50 +0200 -Subject: [PATCH 52/70] MIPS: lantiq: make GPIO3 work on AR9 - -There are 3 16bit and 1 8bit gpio ports on AR9. The gpio driver needs a hack -at 2 places to make the different register layout of the GPIO3 work properly -with the driver. Before only GPIO0-2 were supported. As the GPIO number scheme -clashes with the new size, we also move the other gpio chips to new offsets. - -Signed-off-by: John Crispin -Signed-off-by: Thomas Langer ---- - .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 2 + - arch/mips/lantiq/xway/devices.c | 3 + - arch/mips/lantiq/xway/gpio.c | 84 ++++++++++++++++---- - arch/mips/lantiq/xway/gpio_ebu.c | 3 +- - arch/mips/lantiq/xway/gpio_stp.c | 3 +- - 5 files changed, 75 insertions(+), 20 deletions(-) - ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -@@ -126,7 +126,9 @@ - #define LTQ_GPIO0_BASE_ADDR 0x1E100B10 - #define LTQ_GPIO1_BASE_ADDR 0x1E100B40 - #define LTQ_GPIO2_BASE_ADDR 0x1E100B70 -+#define LTQ_GPIO3_BASE_ADDR 0x1E100BA0 - #define LTQ_GPIO_SIZE 0x30 -+#define LTQ_GPIO3_SIZE 0x10 - - /* SSC */ - #define LTQ_SSC_BASE_ADDR 0x1e100800 ---- a/arch/mips/lantiq/xway/devices.c -+++ b/arch/mips/lantiq/xway/devices.c -@@ -34,6 +34,7 @@ static struct resource ltq_gpio_resource - MEM_RES("gpio0", LTQ_GPIO0_BASE_ADDR, LTQ_GPIO_SIZE), - MEM_RES("gpio1", LTQ_GPIO1_BASE_ADDR, LTQ_GPIO_SIZE), - MEM_RES("gpio2", LTQ_GPIO2_BASE_ADDR, LTQ_GPIO_SIZE), -+ MEM_RES("gpio3", LTQ_GPIO3_BASE_ADDR, LTQ_GPIO3_SIZE), - }; - - void __init ltq_register_gpio(void) -@@ -47,6 +48,8 @@ void __init ltq_register_gpio(void) - if (ltq_is_ar9() || ltq_is_vr9()) { - platform_device_register_simple("ltq_gpio", 2, - <q_gpio_resource[2], 1); -+ platform_device_register_simple("ltq_gpio", 3, -+ <q_gpio_resource[3], 1); - } - } - ---- a/arch/mips/lantiq/xway/gpio.c -+++ b/arch/mips/lantiq/xway/gpio.c -@@ -23,9 +23,17 @@ - #define LTQ_GPIO_OD 0x14 - #define LTQ_GPIO_PUDSEL 0x1C - #define LTQ_GPIO_PUDEN 0x20 -+#define LTQ_GPIO3_OD 0x24 -+#define LTQ_GPIO3_ALTSEL1 0x24 -+#define LTQ_GPIO3_PUDSEL 0x28 -+#define LTQ_GPIO3_PUDEN 0x2C - -+/* PORT3 only has 8 pins and its register layout -+ is slightly different */ - #define PINS_PER_PORT 16 --#define MAX_PORTS 3 -+#define PINS_PORT3 8 -+#define MAX_PORTS 4 -+#define MAX_PIN 56 - - #define ltq_gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p))) - #define ltq_gpio_setbit(m, r, p) ltq_w32_mask(0, (1 << p), m + r) -@@ -55,7 +63,7 @@ int ltq_gpio_request(struct device *dev, - { - int id = 0; - -- if (pin >= (MAX_PORTS * PINS_PER_PORT)) -+ if (pin >= MAX_PIN) - return -EINVAL; - if (devm_gpio_request(dev, pin, name)) { - pr_err("failed to setup lantiq gpio: %s\n", name); -@@ -75,12 +83,21 @@ int ltq_gpio_request(struct device *dev, - else - ltq_gpio_clearbit(ltq_gpio_port[id].membase, - LTQ_GPIO_ALTSEL0, pin); -- if (mux & 0x1) -- ltq_gpio_setbit(ltq_gpio_port[id].membase, -- LTQ_GPIO_ALTSEL1, pin); -- else -- ltq_gpio_clearbit(ltq_gpio_port[id].membase, -- LTQ_GPIO_ALTSEL1, pin); -+ if (id == 3) { -+ if (mux & 0x1) -+ ltq_gpio_setbit(ltq_gpio_port[1].membase, -+ LTQ_GPIO3_ALTSEL1, pin); -+ else -+ ltq_gpio_clearbit(ltq_gpio_port[1].membase, -+ LTQ_GPIO3_ALTSEL1, pin); -+ } else { -+ if (mux & 0x1) -+ ltq_gpio_setbit(ltq_gpio_port[id].membase, -+ LTQ_GPIO_ALTSEL1, pin); -+ else -+ ltq_gpio_clearbit(ltq_gpio_port[id].membase, -+ LTQ_GPIO_ALTSEL1, pin); -+ } - return 0; - } - EXPORT_SYMBOL(ltq_gpio_request); -@@ -106,10 +123,19 @@ static int ltq_gpio_direction_input(stru - { - struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); - -- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); -+ if (chip->ngpio == PINS_PORT3) { -+ ltq_gpio_clearbit(ltq_gpio_port[0].membase, -+ LTQ_GPIO3_OD, offset); -+ ltq_gpio_setbit(ltq_gpio_port[0].membase, -+ LTQ_GPIO3_PUDSEL, offset); -+ ltq_gpio_setbit(ltq_gpio_port[0].membase, -+ LTQ_GPIO3_PUDEN, offset); -+ } else { -+ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); -+ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset); -+ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset); -+ } - ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); -- ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset); -- ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset); - - return 0; - } -@@ -119,10 +145,19 @@ static int ltq_gpio_direction_output(str - { - struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); - -- ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); -+ if (chip->ngpio == PINS_PORT3) { -+ ltq_gpio_setbit(ltq_gpio_port[0].membase, -+ LTQ_GPIO3_OD, offset); -+ ltq_gpio_clearbit(ltq_gpio_port[0].membase, -+ LTQ_GPIO3_PUDSEL, offset); -+ ltq_gpio_clearbit(ltq_gpio_port[0].membase, -+ LTQ_GPIO3_PUDEN, offset); -+ } else { -+ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); -+ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset); -+ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset); -+ } - ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); -- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset); -- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset); - ltq_gpio_set(chip, offset, value); - - return 0; -@@ -133,7 +168,11 @@ static int ltq_gpio_req(struct gpio_chip - struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); - - ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL0, offset); -- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset); -+ if (chip->ngpio == PINS_PORT3) -+ ltq_gpio_clearbit(ltq_gpio_port[1].membase, -+ LTQ_GPIO3_ALTSEL1, offset); -+ else -+ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset); - return 0; - } - -@@ -146,6 +185,16 @@ static int ltq_gpio_probe(struct platfor - pdev->id); - return -EINVAL; - } -+ -+ /* dirty hack - The registers of port3 are not mapped linearly. -+ Port 3 may only load if Port 1/2 are mapped */ -+ if ((pdev->id == 3) && (!ltq_gpio_port[1].membase -+ || !ltq_gpio_port[2].membase)) { -+ dev_err(&pdev->dev, -+ "ports 1/2 need to be loaded before port 3 works\n"); -+ return -ENOMEM; -+ } -+ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) { - dev_err(&pdev->dev, "failed to get memory for gpio port %d\n", -@@ -175,7 +224,10 @@ static int ltq_gpio_probe(struct platfor - ltq_gpio_port[pdev->id].chip.set = ltq_gpio_set; - ltq_gpio_port[pdev->id].chip.request = ltq_gpio_req; - ltq_gpio_port[pdev->id].chip.base = PINS_PER_PORT * pdev->id; -- ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT; -+ if (pdev->id == 3) -+ ltq_gpio_port[pdev->id].chip.ngpio = PINS_PORT3; -+ else -+ ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT; - platform_set_drvdata(pdev, <q_gpio_port[pdev->id]); - return gpiochip_add(<q_gpio_port[pdev->id].chip); - } ---- a/arch/mips/lantiq/xway/gpio_ebu.c -+++ b/arch/mips/lantiq/xway/gpio_ebu.c -@@ -61,9 +61,8 @@ static struct gpio_chip ltq_ebu_chip = { - .label = "ltq_ebu", - .direction_output = ltq_ebu_direction_output, - .set = ltq_ebu_set, -- .base = 72, -+ .base = 100, - .ngpio = 16, -- .can_sleep = 1, - .owner = THIS_MODULE, - }; - ---- a/arch/mips/lantiq/xway/gpio_stp.c -+++ b/arch/mips/lantiq/xway/gpio_stp.c -@@ -74,9 +74,8 @@ static struct gpio_chip ltq_stp_chip = { - .label = "ltq_stp", - .direction_output = ltq_stp_direction_output, - .set = ltq_stp_set, -- .base = 48, -+ .base = 200, - .ngpio = 24, -- .can_sleep = 1, - .owner = THIS_MODULE, - }; - diff --git a/target/linux/lantiq/patches-3.3/0057-MIPS-clean-up-clock-code.patch b/target/linux/lantiq/patches-3.3/0057-MIPS-clean-up-clock-code.patch deleted file mode 100644 index fe04f85527..0000000000 --- a/target/linux/lantiq/patches-3.3/0057-MIPS-clean-up-clock-code.patch +++ /dev/null @@ -1,308 +0,0 @@ -From 580d6aef484b22b5da88588d9a2d944b4f06dc98 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 20 Mar 2012 08:26:04 +0100 -Subject: [PATCH 57/70] MIPS: clean up clock code - ---- - arch/mips/lantiq/clk.c | 11 +++ - arch/mips/lantiq/clk.h | 3 +- - arch/mips/lantiq/xway/devices.c | 2 +- - arch/mips/lantiq/xway/sysctrl.c | 166 ++++++++++++++++++++++++++++++--------- - 4 files changed, 143 insertions(+), 39 deletions(-) - ---- a/arch/mips/lantiq/clk.c -+++ b/arch/mips/lantiq/clk.c -@@ -44,6 +44,7 @@ struct clk *clk_get_fpi(void) - { - return &cpu_clk_generic[1]; - } -+EXPORT_SYMBOL_GPL(clk_get_fpi); - - struct clk *clk_get_io(void) - { -@@ -70,6 +71,16 @@ unsigned long clk_get_rate(struct clk *c - } - EXPORT_SYMBOL(clk_get_rate); - -+int clk_set_rate(struct clk *clk, unsigned long rate) -+{ -+ if (unlikely(!clk_good(clk))) -+ return 0; -+ -+ clk->rate = rate; -+ return 0; -+} -+EXPORT_SYMBOL(clk_set_rate); -+ - int clk_enable(struct clk *clk) - { - if (unlikely(!clk_good(clk))) ---- a/arch/mips/lantiq/clk.h -+++ b/arch/mips/lantiq/clk.h -@@ -12,6 +12,7 @@ - #include - - /* clock speeds */ -+#define CLOCK_33M 33333333 - #define CLOCK_60M 60000000 - #define CLOCK_62_5M 62500000 - #define CLOCK_83M 83333333 -@@ -38,9 +39,9 @@ - struct clk { - struct clk_lookup cl; - unsigned long rate; -- unsigned long (*get_rate) (void); - unsigned int module; - unsigned int bits; -+ unsigned long (*get_rate) (void); - int (*enable) (struct clk *clk); - void (*disable) (struct clk *clk); - int (*activate) (struct clk *clk); ---- a/arch/mips/lantiq/xway/devices.c -+++ b/arch/mips/lantiq/xway/devices.c -@@ -59,7 +59,7 @@ static struct resource ltq_stp_resource - - void __init ltq_register_gpio_stp(void) - { -- platform_device_register_simple("ltq_stp", 0, <q_stp_resource, 1); -+ platform_device_register_simple("ltq_stp", -1, <q_stp_resource, 1); - } - - /* asc ports - amazon se has its own serial mapping */ ---- a/arch/mips/lantiq/xway/sysctrl.c -+++ b/arch/mips/lantiq/xway/sysctrl.c -@@ -16,40 +16,57 @@ - #include "../devices.h" - - /* clock control register */ --#define LTQ_CGU_IFCCR 0x0018 -+#define CGU_IFCCR 0x0018 - /* system clock register */ --#define LTQ_CGU_SYS 0x0010 -- --/* the enable / disable registers */ --#define LTQ_PMU_PWDCR 0x1C --#define LTQ_PMU_PWDSR 0x20 --#define LTQ_PMU_PWDCR1 0x24 --#define LTQ_PMU_PWDSR1 0x28 -- --#define PWDCR(x) ((x) ? (LTQ_PMU_PWDCR1) : (LTQ_PMU_PWDCR)) --#define PWDSR(x) ((x) ? (LTQ_PMU_PWDSR1) : (LTQ_PMU_PWDSR)) -- --/* CGU - clock generation unit */ --#define CGU_EPHY 0x10 -+#define CGU_SYS 0x0010 -+/* pci control register */ -+#define CGU_PCICR 0x0034 -+/* ephy configuration register */ -+#define CGU_EPHY 0x10 -+/* power control register */ -+#define PMU_PWDCR 0x1C -+/* power status register */ -+#define PMU_PWDSR 0x20 -+/* power control register */ -+#define PMU_PWDCR1 0x24 -+/* power status register */ -+#define PMU_PWDSR1 0x28 -+/* power control register */ -+#define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR)) -+/* power status register */ -+#define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR)) - - /* PMU - power management unit */ --#define PMU_DMA 0x0020 --#define PMU_SPI 0x0100 --#define PMU_EPHY 0x0080 --#define PMU_USB 0x8041 --#define PMU_STP 0x0800 --#define PMU_GPT 0x1000 --#define PMU_PPE 0x2000 --#define PMU_FPI 0x4000 --#define PMU_SWITCH 0x10000000 --#define PMU_AHBS 0x2000 --#define PMU_AHBM 0x8000 --#define PMU_PCIE_CLK 0x80000000 -- --#define PMU1_PCIE_PHY 0x0001 --#define PMU1_PCIE_CTL 0x0002 --#define PMU1_PCIE_MSI 0x0020 --#define PMU1_PCIE_PDI 0x0010 -+#define PMU_USB0_P BIT(0) -+#define PMU_PCI BIT(4) -+#define PMU_DMA BIT(5) -+#define PMU_USB0 BIT(5) -+#define PMU_SPI BIT(8) -+#define PMU_EPHY BIT(7) -+#define PMU_EBU BIT(10) -+#define PMU_STP BIT(11) -+#define PMU_GPT BIT(12) -+#define PMU_PPE BIT(13) -+#define PMU_AHBS BIT(13) /* vr9 */ -+#define PMU_FPI BIT(14) -+#define PMU_AHBM BIT(15) -+#define PMU_PPE_QSB BIT(18) -+#define PMU_PPE_SLL01 BIT(19) -+#define PMU_PPE_TC BIT(21) -+#define PMU_PPE_EMA BIT(22) -+#define PMU_PPE_DPLUM BIT(23) -+#define PMU_PPE_DPLUS BIT(24) -+#define PMU_USB1_P BIT(26) -+#define PMU_USB1 BIT(27) -+#define PMU_SWITCH BIT(28) -+#define PMU_PPE_TOP BIT(29) -+#define PMU_GPHY BIT(30) -+#define PMU_PCIE_CLK BIT(31) -+ -+#define PMU1_PCIE_PHY BIT(0) -+#define PMU1_PCIE_CTL BIT(1) -+#define PMU1_PCIE_PDI BIT(4) -+#define PMU1_PCIE_MSI BIT(5) - - #define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y)) - #define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x)) -@@ -69,13 +86,13 @@ static void __iomem *ltq_pmu_membase; - - static int ltq_cgu_enable(struct clk *clk) - { -- ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk->bits, LTQ_CGU_IFCCR); -+ ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | clk->bits, CGU_IFCCR); - return 0; - } - - static void ltq_cgu_disable(struct clk *clk) - { -- ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~clk->bits, LTQ_CGU_IFCCR); -+ ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~clk->bits, CGU_IFCCR); - } - - static int ltq_pmu_enable(struct clk *clk) -@@ -94,9 +111,49 @@ static int ltq_pmu_enable(struct clk *cl - - static void ltq_pmu_disable(struct clk *clk) - { -- ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | clk->bits, LTQ_PMU_PWDCR); -+ ltq_pmu_w32(ltq_pmu_r32(PWDCR(clk->module)) | clk->bits, -+ PWDCR(clk->module)); - } - -+static int ltq_pci_enable(struct clk *clk) -+{ -+ unsigned int ifccr = ltq_cgu_r32(CGU_IFCCR); -+ /* set clock bus speed */ -+ if (ltq_is_ar9()) { -+ ifccr &= ~0x1f00000; -+ if (clk->rate == CLOCK_33M) -+ ifccr |= 0xe00000; -+ else -+ ifccr |= 0x700000; /* 62.5M */ -+ } else { -+ ifccr &= ~0xf00000; -+ if (clk->rate == CLOCK_33M) -+ ifccr |= 0x800000; -+ else -+ ifccr |= 0x400000; /* 62.5M */ -+ } -+ ltq_cgu_w32(ifccr, CGU_IFCCR); -+ return 0; -+} -+ -+static int ltq_pci_ext_enable(struct clk *clk) -+{ -+ /* enable external pci clock */ -+ ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) & ~(1 << 16), -+ CGU_IFCCR); -+ ltq_cgu_w32((1 << 30), CGU_PCICR); -+ return 0; -+} -+ -+static void ltq_pci_ext_disable(struct clk *clk) -+{ -+ /* enable external pci clock */ -+ ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16), -+ CGU_IFCCR); -+ ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR); -+} -+ -+/* manage the clock gates via PMU */ - static inline void clkdev_add_pmu(const char *dev, const char *con, - unsigned int module, unsigned int bits) - { -@@ -112,6 +169,7 @@ static inline void clkdev_add_pmu(const - clkdev_add(&clk->cl); - } - -+/* manage the clock generator */ - static inline void clkdev_add_cgu(const char *dev, const char *con, - unsigned int bits) - { -@@ -126,6 +184,33 @@ static inline void clkdev_add_cgu(const - clkdev_add(&clk->cl); - } - -+/* pci needs its own enable function */ -+static inline void clkdev_add_pci(void) -+{ -+ struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); -+ struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL); -+ -+ /* main pci clock */ -+ clk->cl.dev_id = "ltq_pci"; -+ clk->cl.con_id = NULL; -+ clk->cl.clk = clk; -+ clk->rate = CLOCK_33M; -+ clk->enable = ltq_pci_enable; -+ clk->disable = ltq_pmu_disable; -+ clk->module = 0; -+ clk->bits = PMU_PCI; -+ clkdev_add(&clk->cl); -+ -+ /* use internal/external bus clock */ -+ clk_ext->cl.dev_id = "ltq_pci"; -+ clk_ext->cl.con_id = "external"; -+ clk_ext->cl.clk = clk_ext; -+ clk_ext->enable = ltq_pci_ext_enable; -+ clk_ext->disable = ltq_pci_ext_disable; -+ clkdev_add(&clk_ext->cl); -+ -+} -+ - void __init ltq_soc_init(void) - { - ltq_pmu_membase = ltq_remap_resource(<q_pmu_resource); -@@ -144,14 +229,16 @@ void __init ltq_soc_init(void) - ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); - - /* add our clocks */ -+ clkdev_add_pmu("ltq_fpi", NULL, 0, PMU_FPI); - clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA); - clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP); - clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI); - clkdev_add_pmu("ltq_gptu", NULL, 0, PMU_GPT); -+ clkdev_add_pmu("ltq_ebu", NULL, 0, PMU_EBU); - if (!ltq_is_vr9()) - clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE); - if (ltq_is_ase()) { -- if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5)) -+ if (ltq_cgu_r32(CGU_SYS) & (1 << 5)) - clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M); - else - clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M); -@@ -166,11 +253,16 @@ void __init ltq_soc_init(void) - clkdev_add_pmu("ltq_pcie", "pdi", 1, PMU1_PCIE_PDI); - clkdev_add_pmu("ltq_pcie", "ctl", 1, PMU1_PCIE_CTL); - clkdev_add_pmu("ltq_pcie", "ahb", 0, PMU_AHBM | PMU_AHBS); -- clkdev_add_pmu("usb0", NULL, 0, (1<<6) | 1); -- clkdev_add_pmu("usb1", NULL, 0, (1<<26) | (1<<27)); -+ clkdev_add_pmu("usb0", NULL, 0, PMU_USB0 | PMU_USB0_P); -+ clkdev_add_pmu("usb1", NULL, 0, PMU_USB1 | PMU_USB1_P); -+ clkdev_add_pmu("ltq_vrx200", NULL, 0, -+ PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM | -+ PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | -+ PMU_PPE_QSB); - } else { - clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(), - ltq_danube_io_region_clock()); -+ clkdev_add_pci(); - if (ltq_is_ar9()) - clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH); - } diff --git a/target/linux/lantiq/patches-3.3/0058-MIPS-cleanup-reset-code.patch b/target/linux/lantiq/patches-3.3/0058-MIPS-cleanup-reset-code.patch deleted file mode 100644 index 47e491dc41..0000000000 --- a/target/linux/lantiq/patches-3.3/0058-MIPS-cleanup-reset-code.patch +++ /dev/null @@ -1,98 +0,0 @@ -From f2e6a9e24af6d3e3ca14e66269c9621cecb9836b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 16 Mar 2012 15:49:32 +0100 -Subject: [PATCH 58/70] MIPS: cleanup reset code - ---- - arch/mips/lantiq/xway/reset.c | 59 ++++++++++++++++++++++++++++++++++------ - 1 files changed, 50 insertions(+), 9 deletions(-) - ---- a/arch/mips/lantiq/xway/reset.c -+++ b/arch/mips/lantiq/xway/reset.c -@@ -11,6 +11,7 @@ - #include - #include - #include -+#include - #include - - #include -@@ -20,12 +21,45 @@ - #define ltq_rcu_w32(x, y) ltq_w32((x), ltq_rcu_membase + (y)) - #define ltq_rcu_r32(x) ltq_r32(ltq_rcu_membase + (x)) - --/* register definitions */ --#define LTQ_RCU_RST 0x0010 --#define LTQ_RCU_RST_ALL 0x40000000 -- --#define LTQ_RCU_RST_STAT 0x0014 --#define LTQ_RCU_STAT_SHIFT 26 -+/* reset request register */ -+#define RCU_RST_REQ 0x0010 -+/* reset status register */ -+#define RCU_RST_STAT 0x0014 -+ -+/* reset cause */ -+#define RCU_STAT_SHIFT 26 -+/* Global SW Reset */ -+#define RCU_RD_SRST BIT(30) -+/* Memory Controller */ -+#define RCU_RD_MC BIT(14) -+/* PCI core */ -+#define RCU_RD_PCI BIT(13) -+/* Voice DFE/AFE */ -+#define RCU_RD_DFE_AFE BIT(12) -+/* DSL AFE */ -+#define RCU_RD_DSL_AFE BIT(11) -+/* SDIO core */ -+#define RCU_RD_SDIO BIT(10) -+/* DMA core */ -+#define RCU_RD_DMA BIT(9) -+/* PPE core */ -+#define RCU_RD_PPE BIT(8) -+/* ARC/DFE core */ -+#define RCU_RD_ARC_DFE BIT(7) -+/* AHB bus */ -+#define RCU_RD_AHB BIT(6) -+/* Ethernet MAC1 */ -+#define RCU_RD_ENET_MAC1 BIT(5) -+/* USB and Phy core */ -+#define RCU_RD_USB BIT(4) -+/* CPU1 subsystem */ -+#define RCU_RD_CPU1 BIT(3) -+/* FPI bus */ -+#define RCU_RD_FPI BIT(2) -+/* CPU0 subsystem */ -+#define RCU_RD_CPU0 BIT(1) -+/* HW reset via HRST pin */ -+#define RCU_RD_HRST BIT(0) - - static struct resource ltq_rcu_resource = - MEM_RES("rcu", LTQ_RCU_BASE_ADDR, LTQ_RCU_SIZE); -@@ -36,16 +70,23 @@ static void __iomem *ltq_rcu_membase; - /* This function is used by the watchdog driver */ - int ltq_reset_cause(void) - { -- u32 val = ltq_rcu_r32(LTQ_RCU_RST_STAT); -- return val >> LTQ_RCU_STAT_SHIFT; -+ u32 val = ltq_rcu_r32(RCU_RST_STAT); -+ return val >> RCU_STAT_SHIFT; - } - EXPORT_SYMBOL_GPL(ltq_reset_cause); - -+void ltq_reset_once(unsigned int module, ulong usec) -+{ -+ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ); -+ udelay(usec); -+ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ); -+} -+ - static void ltq_machine_restart(char *command) - { - pr_notice("System restart\n"); - local_irq_disable(); -- ltq_rcu_w32(ltq_rcu_r32(LTQ_RCU_RST) | LTQ_RCU_RST_ALL, LTQ_RCU_RST); -+ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | RCU_RD_SRST, RCU_RST_REQ); - unreachable(); - } - diff --git a/target/linux/lantiq/patches-3.3/0059-MIPS-lantiq-fixes-ar9-vr9-clock.patch b/target/linux/lantiq/patches-3.3/0059-MIPS-lantiq-fixes-ar9-vr9-clock.patch deleted file mode 100644 index 5379e6a729..0000000000 --- a/target/linux/lantiq/patches-3.3/0059-MIPS-lantiq-fixes-ar9-vr9-clock.patch +++ /dev/null @@ -1,107 +0,0 @@ -From bbe68381c786d73ff4dc8b8b10deaa9db7700a9d Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Sat, 17 Mar 2012 09:58:07 +0100 -Subject: [PATCH 59/70] MIPS: lantiq: fixes ar9/vr9 clock - ---- - arch/mips/lantiq/clk.h | 4 +++- - arch/mips/lantiq/xway/clk.c | 29 ++++++++++++++++++++++++----- - arch/mips/lantiq/xway/sysctrl.c | 13 ++++++++----- - 3 files changed, 35 insertions(+), 11 deletions(-) - ---- a/arch/mips/lantiq/clk.h -+++ b/arch/mips/lantiq/clk.h -@@ -56,8 +56,10 @@ extern unsigned long ltq_danube_cpu_hz(v - extern unsigned long ltq_danube_fpi_hz(void); - extern unsigned long ltq_danube_io_region_clock(void); - -+extern unsigned long ltq_ar9_cpu_hz(void); -+extern unsigned long ltq_ar9_fpi_hz(void); -+ - extern unsigned long ltq_vr9_cpu_hz(void); - extern unsigned long ltq_vr9_fpi_hz(void); --extern unsigned long ltq_vr9_io_region_clock(void); - - #endif ---- a/arch/mips/lantiq/xway/clk.c -+++ b/arch/mips/lantiq/xway/clk.c -@@ -217,6 +217,30 @@ unsigned long ltq_danube_cpu_hz(void) - } - } - -+unsigned long ltq_ar9_sys_hz(void) -+{ -+ if (((ltq_cgu_r32(LTQ_CGU_SYS) >> 3) & 0x3) == 0x2) -+ return CLOCK_393M; -+ return CLOCK_333M; -+} -+ -+unsigned long ltq_ar9_fpi_hz(void) -+{ -+ unsigned long sys = ltq_ar9_sys_hz(); -+ -+ if (ltq_cgu_r32(LTQ_CGU_SYS) & BIT(0)) -+ return sys; -+ return sys >> 1; -+} -+ -+unsigned long ltq_ar9_cpu_hz(void) -+{ -+ if (ltq_cgu_r32(LTQ_CGU_SYS) & BIT(2)) -+ return ltq_ar9_fpi_hz(); -+ else -+ return ltq_ar9_sys_hz(); -+} -+ - unsigned long ltq_danube_fpi_hz(void) - { - unsigned long ddr_clock = DDR_HZ; -@@ -299,11 +323,6 @@ unsigned long ltq_vr9_fpi_hz(void) - return clk; - } - --unsigned long ltq_vr9_io_region_clock(void) --{ -- return ltq_vr9_fpi_hz(); --} -- - unsigned long ltq_vr9_fpi_bus_clock(int fpi) - { - return ltq_vr9_fpi_hz(); ---- a/arch/mips/lantiq/xway/sysctrl.c -+++ b/arch/mips/lantiq/xway/sysctrl.c -@@ -237,6 +237,8 @@ void __init ltq_soc_init(void) - clkdev_add_pmu("ltq_ebu", NULL, 0, PMU_EBU); - if (!ltq_is_vr9()) - clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE); -+ if (!ltq_is_ase()) -+ clkdev_add_pci(); - if (ltq_is_ase()) { - if (ltq_cgu_r32(CGU_SYS) & (1 << 5)) - clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M); -@@ -246,7 +248,7 @@ void __init ltq_soc_init(void) - clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY); - } else if (ltq_is_vr9()) { - clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(), -- ltq_vr9_io_region_clock()); -+ ltq_vr9_fpi_hz()); - clkdev_add_pmu("ltq_pcie", "phy", 1, PMU1_PCIE_PHY); - clkdev_add_pmu("ltq_pcie", "bus", 0, PMU_PCIE_CLK); - clkdev_add_pmu("ltq_pcie", "msi", 1, PMU1_PCIE_MSI); -@@ -259,11 +261,12 @@ void __init ltq_soc_init(void) - PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM | - PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | - PMU_PPE_QSB); -+ } else if (ltq_is_ar9()) { -+ clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), -+ ltq_ar9_fpi_hz()); -+ clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH); - } else { - clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(), -- ltq_danube_io_region_clock()); -- clkdev_add_pci(); -- if (ltq_is_ar9()) -- clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH); -+ ltq_danube_io_region_clock()); - } - } diff --git a/target/linux/lantiq/patches-3.3/0060-MIPS-lantiq-fixes-danube-clock.patch b/target/linux/lantiq/patches-3.3/0060-MIPS-lantiq-fixes-danube-clock.patch deleted file mode 100644 index 02b98f1044..0000000000 --- a/target/linux/lantiq/patches-3.3/0060-MIPS-lantiq-fixes-danube-clock.patch +++ /dev/null @@ -1,52 +0,0 @@ -From e8f13d2824871027e8b6d374a2db3672db043915 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Mon, 19 Mar 2012 15:53:37 +0100 -Subject: [PATCH 60/70] MIPS: lantiq: fixes danube clock - ---- - arch/mips/lantiq/xway/clk.c | 20 ++++++++++---------- - 1 files changed, 10 insertions(+), 10 deletions(-) - ---- a/arch/mips/lantiq/xway/clk.c -+++ b/arch/mips/lantiq/xway/clk.c -@@ -181,7 +181,7 @@ unsigned long ltq_danube_io_region_clock - { - unsigned int ret = ltq_get_pll0_fosc(); - -- switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) { -+ switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0x3) { - default: - case 0: - return (ret + 1) / 2; -@@ -203,6 +203,15 @@ unsigned long ltq_danube_fpi_bus_clock(i - return ret; - } - -+unsigned long ltq_danube_fpi_hz(void) -+{ -+ unsigned long ddr_clock = DDR_HZ; -+ -+ if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40) -+ return ddr_clock >> 1; -+ return ddr_clock; -+} -+ - unsigned long ltq_danube_cpu_hz(void) - { - switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) { -@@ -241,15 +250,6 @@ unsigned long ltq_ar9_cpu_hz(void) - return ltq_ar9_sys_hz(); - } - --unsigned long ltq_danube_fpi_hz(void) --{ -- unsigned long ddr_clock = DDR_HZ; -- -- if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40) -- return ddr_clock >> 1; -- return ddr_clock; --} -- - unsigned long ltq_vr9_cpu_hz(void) - { - unsigned int cpu_sel; diff --git a/target/linux/lantiq/patches-3.3/0061-MIPS-adds-dsl-clocks.patch b/target/linux/lantiq/patches-3.3/0061-MIPS-adds-dsl-clocks.patch deleted file mode 100644 index edc153e5c5..0000000000 --- a/target/linux/lantiq/patches-3.3/0061-MIPS-adds-dsl-clocks.patch +++ /dev/null @@ -1,61 +0,0 @@ -From 77da4ad0d8dfe7c5f46a06296a04a992a961c1a3 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 20 Mar 2012 13:05:11 +0100 -Subject: [PATCH 61/70] MIPS: adds dsl clocks - ---- - arch/mips/lantiq/xway/sysctrl.c | 15 +++++++++++++-- - 1 files changed, 13 insertions(+), 2 deletions(-) - ---- a/arch/mips/lantiq/xway/sysctrl.c -+++ b/arch/mips/lantiq/xway/sysctrl.c -@@ -41,8 +41,9 @@ - #define PMU_PCI BIT(4) - #define PMU_DMA BIT(5) - #define PMU_USB0 BIT(5) -+#define PMU_EPHY BIT(7) /* ase */ - #define PMU_SPI BIT(8) --#define PMU_EPHY BIT(7) -+#define PMU_DFE BIT(9) - #define PMU_EBU BIT(10) - #define PMU_STP BIT(11) - #define PMU_GPT BIT(12) -@@ -147,7 +148,7 @@ static int ltq_pci_ext_enable(struct clk - - static void ltq_pci_ext_disable(struct clk *clk) - { -- /* enable external pci clock */ -+ /* disable external pci clock (internal) */ - ltq_cgu_w32(ltq_cgu_r32(CGU_IFCCR) | (1 << 16), - CGU_IFCCR); - ltq_cgu_w32((1 << 31) | (1 << 30), CGU_PCICR); -@@ -246,6 +247,9 @@ void __init ltq_soc_init(void) - clkdev_add_static(CLOCK_133M, CLOCK_133M, CLOCK_133M); - clkdev_add_cgu("ltq_etop", "ephycgu", CGU_EPHY), - clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY); -+ clkdev_add_pmu("ltq_dsl", NULL, 0, -+ PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | -+ PMU_AHBS | PMU_DFE); - } else if (ltq_is_vr9()) { - clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(), - ltq_vr9_fpi_hz()); -@@ -261,12 +265,19 @@ void __init ltq_soc_init(void) - PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM | - PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | - PMU_PPE_QSB); -+ clkdev_add_pmu("ltq_dsl", NULL, 0, PMU_DFE | PMU_AHBS); - } else if (ltq_is_ar9()) { - clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), - ltq_ar9_fpi_hz()); - clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH); -+ clkdev_add_pmu("ltq_dsl", NULL, 0, -+ PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | -+ PMU_PPE_QSB | PMU_AHBS | PMU_DFE); - } else { - clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(), - ltq_danube_io_region_clock()); -+ clkdev_add_pmu("ltq_dsl", NULL, 0, -+ PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | -+ PMU_PPE_QSB | PMU_AHBS | PMU_DFE); - } - } diff --git a/target/linux/lantiq/patches-3.3/0062-MIPS-lantiq-dont-always-register-asc0.patch b/target/linux/lantiq/patches-3.3/0062-MIPS-lantiq-dont-always-register-asc0.patch deleted file mode 100644 index edcd0d755f..0000000000 --- a/target/linux/lantiq/patches-3.3/0062-MIPS-lantiq-dont-always-register-asc0.patch +++ /dev/null @@ -1,26 +0,0 @@ -From d9acb5a4a0b3781a63f805695319fc8d2d4ec427 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Tue, 20 Mar 2012 08:22:11 +0100 -Subject: [PATCH 62/70] MIPS: lantiq: dont always register asc0 - ---- - arch/mips/lantiq/xway/prom.c | 6 ++---- - 1 files changed, 2 insertions(+), 4 deletions(-) - ---- a/arch/mips/lantiq/xway/prom.c -+++ b/arch/mips/lantiq/xway/prom.c -@@ -101,12 +101,10 @@ void __init ltq_soc_detect(struct ltq_so - - void __init ltq_soc_setup(void) - { -- if (ltq_is_ase()) { -+ if (ltq_is_ase()) - ltq_register_ase_asc(); -- } else { -- ltq_register_asc(0); -+ else - ltq_register_asc(1); -- } - ltq_register_gpio(); - ltq_register_wdt(); - } diff --git a/target/linux/lantiq/patches-3.3/0064-MIPS-lantiq-adds-bootsel-helper.patch b/target/linux/lantiq/patches-3.3/0064-MIPS-lantiq-adds-bootsel-helper.patch deleted file mode 100644 index dcf3d8b10f..0000000000 --- a/target/linux/lantiq/patches-3.3/0064-MIPS-lantiq-adds-bootsel-helper.patch +++ /dev/null @@ -1,59 +0,0 @@ -From 7746053f44b55a7cd914e1b7753cde7ac39e6fd6 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Wed, 21 Mar 2012 14:17:37 +0100 -Subject: [PATCH 64/70] MIPS: lantiq: adds bootsel helper - ---- - .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 12 ++++++++++++ - arch/mips/lantiq/xway/reset.c | 12 +++++++++++- - 2 files changed, 23 insertions(+), 1 deletions(-) - ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h -@@ -144,6 +144,18 @@ - #define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000) - #define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344)) - -+/* BOOT_SEL - find what boot media we have */ -+#define BS_EXT_ROM 0x0 -+#define BS_FLASH 0x1 -+#define BS_MII0 0x2 -+#define BS_PCI 0x3 -+#define BS_UART1 0x4 -+#define BS_SPI 0x5 -+#define BS_NAND 0x6 -+#define BS_RMII0 0x7 -+ -+extern unsigned char ltq_boot_select(void); -+ - /* register access macros for EBU and CGU */ - #define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) - #define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) ---- a/arch/mips/lantiq/xway/reset.c -+++ b/arch/mips/lantiq/xway/reset.c -@@ -27,7 +27,11 @@ - #define RCU_RST_STAT 0x0014 - - /* reset cause */ --#define RCU_STAT_SHIFT 26 -+#define RCU_STAT_SHIFT 26 -+/* boot selection */ -+#define RCU_BOOT_SEL_SHIFT 26 -+#define RCU_BOOT_SEL_MASK 0x7 -+ - /* Global SW Reset */ - #define RCU_RD_SRST BIT(30) - /* Memory Controller */ -@@ -75,6 +79,12 @@ int ltq_reset_cause(void) - } - EXPORT_SYMBOL_GPL(ltq_reset_cause); - -+unsigned char ltq_boot_select(void) -+{ -+ u32 val = ltq_rcu_r32(RCU_RST_STAT); -+ return (val >> RCU_BOOT_SEL_SHIFT) & RCU_BOOT_SEL_MASK; -+} -+ - void ltq_reset_once(unsigned int module, ulong usec) - { - ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ); diff --git a/target/linux/lantiq/patches-3.3/0065-MIPS-lantiq-adds-USB_ARCH_HAS_HCD-to-CONFIG_LANTIQ.patch b/target/linux/lantiq/patches-3.3/0065-MIPS-lantiq-adds-USB_ARCH_HAS_HCD-to-CONFIG_LANTIQ.patch deleted file mode 100644 index 45b7d7be62..0000000000 --- a/target/linux/lantiq/patches-3.3/0065-MIPS-lantiq-adds-USB_ARCH_HAS_HCD-to-CONFIG_LANTIQ.patch +++ /dev/null @@ -1,19 +0,0 @@ -From 495ab2cb0a347dd8270634e42993418eb8122c9e Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Fri, 23 Mar 2012 11:28:22 +0100 -Subject: [PATCH 65/70] MIPS: lantiq: adds USB_ARCH_HAS_HCD to CONFIG_LANTIQ - ---- - arch/mips/Kconfig | 1 + - 1 files changed, 1 insertions(+), 0 deletions(-) - ---- a/arch/mips/Kconfig -+++ b/arch/mips/Kconfig -@@ -232,6 +232,7 @@ config LANTIQ - select CLKDEV_LOOKUP - select HAVE_OPROFILE - select MIPS_MACHINE -+ select USB_ARCH_HAS_HCD - - config LASAT - bool "LASAT Networks platforms" diff --git a/target/linux/lantiq/patches-3.3/0066-MIPS-lantiq-fixes-bad-PMU_USB0-0-define.patch b/target/linux/lantiq/patches-3.3/0066-MIPS-lantiq-fixes-bad-PMU_USB0-0-define.patch deleted file mode 100644 index f2ed0a3225..0000000000 --- a/target/linux/lantiq/patches-3.3/0066-MIPS-lantiq-fixes-bad-PMU_USB0-0-define.patch +++ /dev/null @@ -1,20 +0,0 @@ -From 307d2969597246720e7fdfad2a28a2561fb0b951 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 5 Apr 2012 21:51:05 +0200 -Subject: [PATCH 66/70] MIPS: lantiq: fixes bad PMU_USB0(0) define - ---- - arch/mips/lantiq/xway/sysctrl.c | 2 +- - 1 files changed, 1 insertions(+), 1 deletions(-) - ---- a/arch/mips/lantiq/xway/sysctrl.c -+++ b/arch/mips/lantiq/xway/sysctrl.c -@@ -40,7 +40,7 @@ - #define PMU_USB0_P BIT(0) - #define PMU_PCI BIT(4) - #define PMU_DMA BIT(5) --#define PMU_USB0 BIT(5) -+#define PMU_USB0 BIT(6) - #define PMU_EPHY BIT(7) /* ase */ - #define PMU_SPI BIT(8) - #define PMU_DFE BIT(9) diff --git a/target/linux/lantiq/patches-3.3/0067-MIPS-lantiq-fix-dwc_otg-usb-for-ase.patch b/target/linux/lantiq/patches-3.3/0067-MIPS-lantiq-fix-dwc_otg-usb-for-ase.patch deleted file mode 100644 index a95506ab24..0000000000 --- a/target/linux/lantiq/patches-3.3/0067-MIPS-lantiq-fix-dwc_otg-usb-for-ase.patch +++ /dev/null @@ -1,51 +0,0 @@ -From 6f421cda8e6e43f74b8f8a7f63db67c6d3ac9ba3 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Wed, 11 Apr 2012 18:43:50 +0200 -Subject: [PATCH 67/70] MIPS: lantiq: fix dwc_otg usb for ase - -changed irq number and pmu settings. little bit of fiddling to get the now variable -irq into resources. - -Signed-off-by: Conor O'Gorman ---- - .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 1 + - drivers/usb/dwc_otg/dwc_otg_driver.c | 3 +++ - drivers/usb/dwc_otg/dwc_otg_ifx.c | 5 ++++- - 3 files changed, 8 insertions(+), 1 deletions(-) - ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h -@@ -36,6 +36,7 @@ - - #define LTQ_TIMER6_INT (INT_NUM_IM1_IRL0 + 23) - #define LTQ_USB_INT (INT_NUM_IM1_IRL0 + 22) -+#define LTQ_USB_ASE_INT (INT_NUM_IM0_IRL0 + 31) - #define LTQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23) - - #define MIPS_CPU_TIMER_IRQ 7 ---- a/drivers/usb/dwc_otg/dwc_otg_driver.c -+++ b/drivers/usb/dwc_otg/dwc_otg_driver.c -@@ -860,6 +860,9 @@ static int __init dwc_otg_init(void) - - printk(KERN_INFO "%s: version %s\n", dwc_driver_name, DWC_DRIVER_VERSION); - -+ if (ltq_is_ase()) -+ dwc_irq = LTQ_USB_ASE_INT; -+ - // ifxmips setup - retval = ifx_usb_hc_init(dwc_iomem_base, dwc_irq); - if (retval < 0) ---- a/drivers/usb/dwc_otg/dwc_otg_ifx.c -+++ b/drivers/usb/dwc_otg/dwc_otg_ifx.c -@@ -61,7 +61,10 @@ void dwc_otg_power_on (void) - // clear power - writel(readl(DANUBE_PMU_PWDCR) | 0x41, DANUBE_PMU_PWDCR); - // set clock gating -- writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR); -+ if (ltq_is_ase()) -+ writel(readl(DANUBE_CGU_IFCCR) & ~0x20, DANUBE_CGU_IFCCR); -+ else -+ writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR); - // set power - writel(readl(DANUBE_PMU_PWDCR) & ~0x1, DANUBE_PMU_PWDCR); - writel(readl(DANUBE_PMU_PWDCR) & ~0x40, DANUBE_PMU_PWDCR); diff --git a/target/linux/lantiq/patches-3.3/0068-MIPS-lantiq-stp-fix-for-ase-add-get-clock-disabled.patch b/target/linux/lantiq/patches-3.3/0068-MIPS-lantiq-stp-fix-for-ase-add-get-clock-disabled.patch deleted file mode 100644 index 9970485ef4..0000000000 --- a/target/linux/lantiq/patches-3.3/0068-MIPS-lantiq-stp-fix-for-ase-add-get-clock-disabled.patch +++ /dev/null @@ -1,83 +0,0 @@ -From 0ea046d777bf567cfd89c7d968c0b962e3e7589b Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Wed, 11 Apr 2012 18:47:53 +0200 -Subject: [PATCH 68/70] MIPS: lantiq: stp, fix for ase, add get, clock - disabled - -Lantiq serial-to-parallel hardware gpio module -Added gpio pins as used for amazon se (ase) -Added get to enable reporting of gpio status -Changed to use software update, as hw clock was not running on ase. Clock -really only needed if hw flashing was implemented. - -Signed-off-by: Conor O'Gorman ---- - arch/mips/lantiq/xway/gpio_stp.c | 22 +++++++++++++--------- - 1 files changed, 13 insertions(+), 9 deletions(-) - ---- a/arch/mips/lantiq/xway/gpio_stp.c -+++ b/arch/mips/lantiq/xway/gpio_stp.c -@@ -27,6 +27,7 @@ - #define LTQ_STP_AR 0x10 - - #define LTQ_STP_CON_SWU (1 << 31) -+#define LTQ_STP_SWU_MASK (1 << 31) - #define LTQ_STP_2HZ 0 - #define LTQ_STP_4HZ (1 << 23) - #define LTQ_STP_8HZ (2 << 23) -@@ -60,6 +61,12 @@ static void ltq_stp_set(struct gpio_chip - else - ltq_stp_shadow &= ~(1 << offset); - ltq_stp_w32(ltq_stp_shadow, LTQ_STP_CPU0); -+ ltq_stp_w32_mask(LTQ_STP_SWU_MASK, LTQ_STP_CON_SWU, LTQ_STP_CON0); -+} -+ -+static int ltq_stp_get(struct gpio_chip *chip, unsigned offset) -+{ -+ return !!(ltq_stp_r32(LTQ_STP_CPU0) & (1<dev, 4, 2, 1, "stp-st") || -- ltq_gpio_request(&pdev->dev, 5, 2, 1, "stp-d") || -- ltq_gpio_request(&pdev->dev, 6, 2, 1, "stp-sh")) { -+ pin = ltq_is_ase() ? 1 : 4; -+ if (ltq_gpio_request(&pdev->dev, pin, 2, 1, "stp-st") || -+ ltq_gpio_request(&pdev->dev, pin+1, 2, 1, "stp-d") || -+ ltq_gpio_request(&pdev->dev, pin+2, 2, 1, "stp-sh")) { - dev_err(&pdev->dev, "failed to request needed gpios\n"); - return -EBUSY; - } diff --git a/target/linux/lantiq/patches-3.3/0069-MIPS-lantiq-fix-spi-for-ase-update-for-clkdev-and-pl.patch b/target/linux/lantiq/patches-3.3/0069-MIPS-lantiq-fix-spi-for-ase-update-for-clkdev-and-pl.patch deleted file mode 100644 index 7d6a2ea92b..0000000000 --- a/target/linux/lantiq/patches-3.3/0069-MIPS-lantiq-fix-spi-for-ase-update-for-clkdev-and-pl.patch +++ /dev/null @@ -1,188 +0,0 @@ -From e765119d933dd84de2c095d422f1609486775f79 Mon Sep 17 00:00:00 2001 -From: John Crispin -Date: Thu, 12 Apr 2012 13:25:42 +0200 -Subject: [PATCH 69/70] MIPS: lantiq: fix spi for ase, update for clkdev and - platform driver - -irqs, gpios, chipselects -updated to use module_platform_driver() -clkdev is a bit hacky, using ltq_spi.0, as specifying no device numbering led to -the mtd driver not hooking up to an spi flash. - -Signed-off-by: Conor O'Gorman ---- - .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 4 ++ - arch/mips/lantiq/xway/sysctrl.c | 2 +- - drivers/spi/spi-xway.c | 58 ++++++++++---------- - 3 files changed, 35 insertions(+), 29 deletions(-) - ---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h -+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h -@@ -30,6 +30,10 @@ - #define LTQ_SSC_TIR_AR9 (INT_NUM_IM0_IRL0 + 14) - #define LTQ_SSC_RIR_AR9 (INT_NUM_IM0_IRL0 + 15) - #define LTQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16) -+#define LTQ_SSC_RIR_ASE (INT_NUM_IM0_IRL0 + 16) -+#define LTQ_SSC_TIR_ASE (INT_NUM_IM0_IRL0 + 17) -+#define LTQ_SSC_EIR_ASE (INT_NUM_IM0_IRL0 + 18) -+#define LTQ_SSC_FIR_ASE (INT_NUM_IM0_IRL0 + 19) - - #define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21) - #define LTQ_MEI_INT (INT_NUM_IM1_IRL0 + 23) ---- a/arch/mips/lantiq/xway/sysctrl.c -+++ b/arch/mips/lantiq/xway/sysctrl.c -@@ -233,7 +233,7 @@ void __init ltq_soc_init(void) - clkdev_add_pmu("ltq_fpi", NULL, 0, PMU_FPI); - clkdev_add_pmu("ltq_dma", NULL, 0, PMU_DMA); - clkdev_add_pmu("ltq_stp", NULL, 0, PMU_STP); -- clkdev_add_pmu("ltq_spi", NULL, 0, PMU_SPI); -+ clkdev_add_pmu("ltq_spi.0", NULL, 0, PMU_SPI); - clkdev_add_pmu("ltq_gptu", NULL, 0, PMU_GPT); - clkdev_add_pmu("ltq_ebu", NULL, 0, PMU_EBU); - if (!ltq_is_vr9()) ---- a/drivers/spi/spi-xway.c -+++ b/drivers/spi/spi-xway.c -@@ -143,9 +143,9 @@ - #define LTQ_SPI_IRNEN_ALL 0xF - - /* Hard-wired GPIOs used by SPI controller */ --#define LTQ_SPI_GPIO_DI 16 --#define LTQ_SPI_GPIO_DO 17 --#define LTQ_SPI_GPIO_CLK 18 -+#define LTQ_SPI_GPIO_DI (ltq_is_ase()? 8 : 16) -+#define LTQ_SPI_GPIO_DO (ltq_is_ase()? 9 : 17) -+#define LTQ_SPI_GPIO_CLK (ltq_is_ase()? 10 : 18) - - struct ltq_spi { - struct spi_bitbang bitbang; -@@ -229,7 +229,7 @@ static void ltq_spi_hw_enable(struct ltq - u32 clc; - - /* Power-up mdule */ -- clk_enable(hw->spiclk); -+ clk_enable(hw->spiclk); - - /* - * Set clock divider for run mode to 1 to -@@ -245,7 +245,7 @@ static void ltq_spi_hw_disable(struct lt - ltq_spi_reg_write(hw, LTQ_SPI_CLC_DISS, LTQ_SPI_CLC); - - /* Power-down mdule */ -- clk_disable(hw->spiclk); -+ clk_disable(hw->spiclk); - } - - static void ltq_spi_reset_fifos(struct ltq_spi *hw) -@@ -284,7 +284,7 @@ static inline int ltq_spi_wait_ready(str - cond_resched(); - } while (!time_after_eq(jiffies, timeout)); - -- dev_err(hw->dev, "SPI wait ready timed out\n"); -+ dev_err(hw->dev, "SPI wait ready timed out stat: %x\n", stat); - - return -ETIMEDOUT; - } -@@ -556,6 +556,12 @@ static const struct ltq_spi_cs_gpio_map - { 11, 3 }, - }; - -+static const struct ltq_spi_cs_gpio_map ltq_spi_cs_ase[] = { -+ { 7, 2 }, -+ { 15, 1 }, -+ { 14, 1 }, -+}; -+ - static int ltq_spi_setup(struct spi_device *spi) - { - struct ltq_spi *hw = ltq_spi_to_hw(spi); -@@ -600,8 +606,10 @@ static int ltq_spi_setup(struct spi_devi - cstate->cs_activate = ltq_spi_gpio_cs_activate; - cstate->cs_deactivate = ltq_spi_gpio_cs_deactivate; - } else { -- ret = ltq_gpio_request(&spi->dev, ltq_spi_cs[spi->chip_select].gpio, -- ltq_spi_cs[spi->chip_select].mux, -+ struct ltq_spi_cs_gpio_map *cs_map = -+ ltq_is_ase() ? ltq_spi_cs_ase : ltq_spi_cs; -+ ret = ltq_gpio_request(&spi->dev, cs_map[spi->chip_select].gpio, -+ cs_map[spi->chip_select].mux, - 1, "spi-cs"); - if (ret) - return -EBUSY; -@@ -633,7 +641,8 @@ static void ltq_spi_cleanup(struct spi_d - if (cdata && cdata->gpio) - gpio = cdata->gpio; - else -- gpio = ltq_spi_cs[spi->chip_select].gpio; -+ gpio = ltq_is_ase() ? ltq_spi_cs_ase[spi->chip_select].gpio : -+ ltq_spi_cs[spi->chip_select].gpio; - - gpio_free(gpio); - kfree(cstate); -@@ -868,7 +877,8 @@ static const struct ltq_spi_irq_map ltq_ - { "spi_err", ltq_spi_err_irq }, - }; - --static int __init ltq_spi_probe(struct platform_device *pdev) -+static int __devinit -+ltq_spi_probe(struct platform_device *pdev) - { - struct spi_master *master; - struct resource *r; -@@ -910,14 +920,14 @@ static int __init ltq_spi_probe(struct p - - hw->fpiclk = clk_get_fpi(); - if (IS_ERR(hw->fpiclk)) { -- dev_err(&pdev->dev, "clk_get\n"); -+ dev_err(&pdev->dev, "fpi clk\n"); - ret = PTR_ERR(hw->fpiclk); - goto err_master; - } - - hw->spiclk = clk_get(&pdev->dev, NULL); - if (IS_ERR(hw->spiclk)) { -- dev_err(&pdev->dev, "clk_get\n"); -+ dev_err(&pdev->dev, "spi clk\n"); - ret = PTR_ERR(hw->spiclk); - goto err_master; - } -@@ -1014,7 +1024,8 @@ err: - return ret; - } - --static int __exit ltq_spi_remove(struct platform_device *pdev) -+static int __devexit -+ltq_spi_remove(struct platform_device *pdev) - { - struct ltq_spi *hw = platform_get_drvdata(pdev); - int ret, i; -@@ -1043,24 +1054,15 @@ static int __exit ltq_spi_remove(struct - } - - static struct platform_driver ltq_spi_driver = { -+ .probe = ltq_spi_probe, -+ .remove = __devexit_p(ltq_spi_remove), - .driver = { -- .name = "ltq_spi", -- .owner = THIS_MODULE, -- }, -- .remove = __exit_p(ltq_spi_remove), -+ .name = "ltq_spi", -+ .owner = THIS_MODULE, -+ }, - }; - --static int __init ltq_spi_init(void) --{ -- return platform_driver_probe(<q_spi_driver, ltq_spi_probe); --} --module_init(ltq_spi_init); -- --static void __exit ltq_spi_exit(void) --{ -- platform_driver_unregister(<q_spi_driver); --} --module_exit(ltq_spi_exit); -+module_platform_driver(ltq_spi_driver); - - MODULE_DESCRIPTION("Lantiq SoC SPI controller driver"); - MODULE_AUTHOR("Daniel Schwierzeck "); diff --git a/target/linux/lantiq/patches-3.3/0070-icu-multi-base.patch b/target/linux/lantiq/patches-3.3/0070-icu-multi-base.patch deleted file mode 100644 index d7e098f909..0000000000 --- a/target/linux/lantiq/patches-3.3/0070-icu-multi-base.patch +++ /dev/null @@ -1,233 +0,0 @@ -Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h -=================================================================== ---- linux-3.3.8.orig/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h 2012-07-31 08:34:35.000000000 +0200 -+++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h 2012-07-31 08:34:46.063369976 +0200 -@@ -9,6 +9,8 @@ - #ifndef _LANTIQ_XWAY_IRQ_H__ - #define _LANTIQ_XWAY_IRQ_H__ - -+#define IM_NUM 5 -+ - #define INT_NUM_IRQ0 8 - #define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) - #define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32) -Index: linux-3.3.8/arch/mips/lantiq/irq.c -=================================================================== ---- linux-3.3.8.orig/arch/mips/lantiq/irq.c 2012-07-31 08:34:35.000000000 +0200 -+++ linux-3.3.8/arch/mips/lantiq/irq.c 2012-07-31 08:51:40.203413329 +0200 -@@ -48,8 +48,8 @@ - */ - #define LTQ_ICU_EBU_IRQ 22 - --#define ltq_icu_w32(x, y) ltq_w32((x), ltq_icu_membase + (y)) --#define ltq_icu_r32(x) ltq_r32(ltq_icu_membase + (x)) -+#define ltq_icu_w32(x, y, m) ltq_w32((x), ltq_icu_membase[m] + (y)) -+#define ltq_icu_r32(x, m) ltq_r32(ltq_icu_membase[m] + (x)) - - #define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y)) - #define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x)) -@@ -63,11 +63,78 @@ - LTQ_EIU_IR5, - }; - --static struct resource ltq_icu_resource = { -- .name = "icu", -- .start = LTQ_ICU_BASE_ADDR, -- .end = LTQ_ICU_BASE_ADDR + LTQ_ICU_SIZE - 1, -- .flags = IORESOURCE_MEM, -+static struct resource ltq_icu_resource[IM_NUM] = { -+{ -+ .name = "icu_im0", -+ .start = LTQ_ICU_BASE_ADDR, -+ .end = LTQ_ICU_BASE_ADDR + LTQ_ICU_OFFSET - 1, -+ .flags = IORESOURCE_MEM, -+}, -+#if IM_NUM >= 2 -+{ -+ .name = "icu_im1", -+#ifdef LTQ_ICU_BASE_ADDR1 -+ .start = LTQ_ICU_BASE_ADDR1, -+ .end = LTQ_ICU_BASE_ADDR1 + LTQ_ICU_OFFSET - 1, -+#else -+ .start = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 1), -+ .end = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 2) - 1, -+#endif -+ .flags = IORESOURCE_MEM, -+}, -+#endif -+#if IM_NUM >= 3 -+{ -+ .name = "icu_im2", -+#ifdef LTQ_ICU_BASE_ADDR2 -+ .start = LTQ_ICU_BASE_ADDR2, -+ .end = LTQ_ICU_BASE_ADDR2 + LTQ_ICU_OFFSET - 1, -+#else -+ .start = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 2), -+ .end = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 3) - 1, -+#endif -+ .flags = IORESOURCE_MEM, -+}, -+#endif -+#if IM_NUM >= 4 -+{ -+ .name = "icu_im3", -+#ifdef LTQ_ICU_BASE_ADDR3 -+ .start = LTQ_ICU_BASE_ADDR3, -+ .end = LTQ_ICU_BASE_ADDR3 + LTQ_ICU_OFFSET - 1, -+#else -+ .start = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 3), -+ .end = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 4) - 1, -+#endif -+ .flags = IORESOURCE_MEM, -+}, -+#endif -+#if IM_NUM >= 5 -+{ -+ .name = "icu_im4", -+#ifdef LTQ_ICU_BASE_ADDR4 -+ .start = LTQ_ICU_BASE_ADDR4, -+ .end = LTQ_ICU_BASE_ADDR4 + LTQ_ICU_OFFSET - 1, -+#else -+ .start = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 4), -+ .end = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 5) - 1, -+#endif -+ .flags = IORESOURCE_MEM, -+}, -+#endif -+#if IM_NUM >= 6 -+{ -+ .name = "icu_im5", -+#ifdef LTQ_ICU_BASE_ADDR5 -+ .start = LTQ_ICU_BASE_ADDR5, -+ .end = LTQ_ICU_BASE_ADDR5 + LTQ_ICU_OFFSET - 1, -+#else -+ .start = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 5), -+ .end = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 6) - 1, -+#endif -+ .flags = IORESOURCE_MEM, -+}, -+#endif - }; - - static struct resource ltq_eiu_resource = { -@@ -77,50 +144,56 @@ - .flags = IORESOURCE_MEM, - }; - --static void __iomem *ltq_icu_membase; -+static void __iomem *ltq_icu_membase[IM_NUM]; - static void __iomem *ltq_eiu_membase; - - void ltq_disable_irq(struct irq_data *d) - { -- u32 ier = LTQ_ICU_IM0_IER; - int irq_nr = d->irq - INT_NUM_IRQ0; -+ unsigned int im_nr; - -- ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); -+ im_nr = (irq_nr / INT_NUM_IM_OFFSET); - irq_nr %= INT_NUM_IM_OFFSET; -- ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier); -+ -+ ltq_icu_w32(ltq_icu_r32(LTQ_ICU_IM0_IER, im_nr) & ~(1 << irq_nr), -+ LTQ_ICU_IM0_IER, im_nr); - } - - void ltq_mask_and_ack_irq(struct irq_data *d) - { -- u32 ier = LTQ_ICU_IM0_IER; -- u32 isr = LTQ_ICU_IM0_ISR; - int irq_nr = d->irq - INT_NUM_IRQ0; -+ unsigned int im_nr; - -- ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); -- isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); -+ irq_nr -= INT_NUM_IRQ0; -+ im_nr = (irq_nr / INT_NUM_IM_OFFSET); - irq_nr %= INT_NUM_IM_OFFSET; -- ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier); -- ltq_icu_w32((1 << irq_nr), isr); -+ -+ ltq_icu_w32(ltq_icu_r32(LTQ_ICU_IM0_IER, im_nr) & ~(1 << irq_nr), LTQ_ICU_IM0_IER, im_nr); -+ ltq_icu_w32((1 << irq_nr), LTQ_ICU_IM0_ISR, im_nr); - } - - static void ltq_ack_irq(struct irq_data *d) - { -- u32 isr = LTQ_ICU_IM0_ISR; - int irq_nr = d->irq - INT_NUM_IRQ0; -+ unsigned int im_nr; - -- isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); -+ irq_nr -= INT_NUM_IRQ0; -+ im_nr = (irq_nr / INT_NUM_IM_OFFSET); - irq_nr %= INT_NUM_IM_OFFSET; -- ltq_icu_w32((1 << irq_nr), isr); -+ -+ ltq_icu_w32((1 << irq_nr), LTQ_ICU_IM0_ISR, im_nr); - } - - void ltq_enable_irq(struct irq_data *d) - { -- u32 ier = LTQ_ICU_IM0_IER; - int irq_nr = d->irq - INT_NUM_IRQ0; -+ unsigned int im_nr; - -- ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); -+ irq_nr -= INT_NUM_IRQ0; -+ im_nr = (irq_nr / INT_NUM_IM_OFFSET); - irq_nr %= INT_NUM_IM_OFFSET; -- ltq_icu_w32(ltq_icu_r32(ier) | (1 << irq_nr), ier); -+ -+ ltq_icu_w32(ltq_icu_r32(LTQ_ICU_IM0_IER, im_nr) | (1 << irq_nr), LTQ_ICU_IM0_IER, im_nr); - } - - static unsigned int ltq_startup_eiu_irq(struct irq_data *d) -@@ -187,7 +260,7 @@ - { - u32 irq; - -- irq = ltq_icu_r32(LTQ_ICU_IM0_IOSR + (module * LTQ_ICU_OFFSET)); -+ irq = ltq_icu_r32(LTQ_ICU_IM0_IOSR, module); - if (irq == 0) - return; - -@@ -250,8 +323,19 @@ - { - int i; - -- if (insert_resource(&iomem_resource, <q_icu_resource) < 0) -- panic("Failed to insert icu memory"); -+ for (i=0; i < IM_NUM; i++) { -+ if (insert_resource(&iomem_resource, <q_icu_resource[i]) < 0) -+ panic("Failed to insert icu memory\n"); -+ -+ if (request_mem_region(ltq_icu_resource[i].start, -+ resource_size(<q_icu_resource[i]), "icu") < 0) -+ panic("Failed to request icu memory\n"); -+ -+ ltq_icu_membase[i] = ioremap_nocache(ltq_icu_resource[i].start, -+ resource_size(<q_icu_resource[i])); -+ if (!ltq_icu_membase[i]) -+ panic("Failed to remap icu memory\n"); -+ } - - if (request_mem_region(ltq_icu_resource.start, - resource_size(<q_icu_resource), "icu") < 0) -@@ -277,11 +361,11 @@ - } - - /* make sure all irqs are turned off by default */ -- for (i = 0; i < 5; i++) -- ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET)); -- -- /* clear all possibly pending interrupts */ -- ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET)); -+ for (i = 0; i < IM_NUM; i++) -+ ltq_icu_w32(0, LTQ_ICU_IM0_IER, i); -+ /* clear all possibly pending interrupts */ -+ ltq_icu_w32(~0, LTQ_ICU_IM0_ISR, i); -+ } - - mips_cpu_irq_init(); - diff --git a/target/linux/lantiq/patches-3.3/0072-fix_i2c_clock.patch b/target/linux/lantiq/patches-3.3/0072-fix_i2c_clock.patch deleted file mode 100644 index 310b33f29f..0000000000 --- a/target/linux/lantiq/patches-3.3/0072-fix_i2c_clock.patch +++ /dev/null @@ -1,32 +0,0 @@ -Index: linux-3.3.8/arch/mips/lantiq/falcon/sysctrl.c -=================================================================== ---- linux-3.3.8.orig/arch/mips/lantiq/falcon/sysctrl.c 2012-08-02 15:14:10.811781411 +0200 -+++ linux-3.3.8/arch/mips/lantiq/falcon/sysctrl.c 2012-08-02 15:16:24.587787128 +0200 -@@ -171,6 +171,7 @@ - clk->cl.con_id = NULL; - clk->cl.clk = clk; - clk->module = module; -+ clk->bits = bits; - clk->activate = ltq_sysctl_activate; - clk->deactivate = ltq_sysctl_deactivate; - clk->enable = ltq_sysctl_clken; -@@ -206,5 +207,5 @@ - clkdev_add_sys("falcon_gpio.3", SYSCTL_SYS1, ACTS_PADCTRL3 | ACTS_P3); - clkdev_add_sys("falcon_gpio.4", SYSCTL_SYS1, ACTS_PADCTRL4 | ACTS_P4); - clkdev_add_sys("ltq_asc.1", SYSCTL_SYS1, ACTS_ASC1_ACT); -- clkdev_add_sys("falcon_i2c", SYSCTL_SYS1, ACTS_I2C_ACT); -+ clkdev_add_sys("i2c-falcon.0", SYSCTL_SYS1, ACTS_I2C_ACT); - } -Index: linux-3.3.8/drivers/i2c/busses/i2c-falcon.c -=================================================================== ---- linux-3.3.8.orig/drivers/i2c/busses/i2c-falcon.c 2012-08-02 15:14:10.939781415 +0200 -+++ linux-3.3.8/drivers/i2c/busses/i2c-falcon.c 2012-08-02 15:15:59.667786063 +0200 -@@ -824,7 +824,7 @@ - dev_err(&pdev->dev, "failed to get i2c clk\n"); - return -ENOENT; - } -- -+ clk_activate(clk); - /* allocate private data */ - priv = kzalloc(sizeof(*priv), GFP_KERNEL); - if (!priv) { diff --git a/target/linux/lantiq/patches-3.3/100-falcon_bsp_header.patch b/target/linux/lantiq/patches-3.3/100-falcon_bsp_header.patch deleted file mode 100644 index 61105504c0..0000000000 --- a/target/linux/lantiq/patches-3.3/100-falcon_bsp_header.patch +++ /dev/null @@ -1,13633 +0,0 @@ ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/gpon_reg_base.h -@@ -0,0 +1,376 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+ -+#ifndef _gpon_reg_base_h -+#define _gpon_reg_base_h -+ -+/** \addtogroup GPON_BASE -+ @{ -+*/ -+ -+#ifndef KSEG1 -+#define KSEG1 0xA0000000 -+#endif -+ -+/** address range for ebu -+ 0x18000000--0x180000FF */ -+#define GPON_EBU_BASE (KSEG1 | 0x18000000) -+#define GPON_EBU_END (KSEG1 | 0x180000FF) -+#define GPON_EBU_SIZE 0x00000100 -+/** address range for gpearb -+ 0x1D400100--0x1D4001FF */ -+#define GPON_GPEARB_BASE (KSEG1 | 0x1D400100) -+#define GPON_GPEARB_END (KSEG1 | 0x1D4001FF) -+#define GPON_GPEARB_SIZE 0x00000100 -+/** address range for tmu -+ 0x1D404000--0x1D404FFF */ -+#define GPON_TMU_BASE (KSEG1 | 0x1D404000) -+#define GPON_TMU_END (KSEG1 | 0x1D404FFF) -+#define GPON_TMU_SIZE 0x00001000 -+/** address range for iqm -+ 0x1D410000--0x1D41FFFF */ -+#define GPON_IQM_BASE (KSEG1 | 0x1D410000) -+#define GPON_IQM_END (KSEG1 | 0x1D41FFFF) -+#define GPON_IQM_SIZE 0x00010000 -+/** address range for octrlg -+ 0x1D420000--0x1D42FFFF */ -+#define GPON_OCTRLG_BASE (KSEG1 | 0x1D420000) -+#define GPON_OCTRLG_END (KSEG1 | 0x1D42FFFF) -+#define GPON_OCTRLG_SIZE 0x00010000 -+/** address range for octrll0 -+ 0x1D440000--0x1D4400FF */ -+#define GPON_OCTRLL0_BASE (KSEG1 | 0x1D440000) -+#define GPON_OCTRLL0_END (KSEG1 | 0x1D4400FF) -+#define GPON_OCTRLL0_SIZE 0x00000100 -+/** address range for octrll1 -+ 0x1D440100--0x1D4401FF */ -+#define GPON_OCTRLL1_BASE (KSEG1 | 0x1D440100) -+#define GPON_OCTRLL1_END (KSEG1 | 0x1D4401FF) -+#define GPON_OCTRLL1_SIZE 0x00000100 -+/** address range for octrll2 -+ 0x1D440200--0x1D4402FF */ -+#define GPON_OCTRLL2_BASE (KSEG1 | 0x1D440200) -+#define GPON_OCTRLL2_END (KSEG1 | 0x1D4402FF) -+#define GPON_OCTRLL2_SIZE 0x00000100 -+/** address range for octrll3 -+ 0x1D440300--0x1D4403FF */ -+#define GPON_OCTRLL3_BASE (KSEG1 | 0x1D440300) -+#define GPON_OCTRLL3_END (KSEG1 | 0x1D4403FF) -+#define GPON_OCTRLL3_SIZE 0x00000100 -+/** address range for octrlc -+ 0x1D441000--0x1D4410FF */ -+#define GPON_OCTRLC_BASE (KSEG1 | 0x1D441000) -+#define GPON_OCTRLC_END (KSEG1 | 0x1D4410FF) -+#define GPON_OCTRLC_SIZE 0x00000100 -+/** address range for ictrlg -+ 0x1D450000--0x1D45FFFF */ -+#define GPON_ICTRLG_BASE (KSEG1 | 0x1D450000) -+#define GPON_ICTRLG_END (KSEG1 | 0x1D45FFFF) -+#define GPON_ICTRLG_SIZE 0x00010000 -+/** address range for ictrll0 -+ 0x1D460000--0x1D4601FF */ -+#define GPON_ICTRLL0_BASE (KSEG1 | 0x1D460000) -+#define GPON_ICTRLL0_END (KSEG1 | 0x1D4601FF) -+#define GPON_ICTRLL0_SIZE 0x00000200 -+/** address range for ictrll1 -+ 0x1D460200--0x1D4603FF */ -+#define GPON_ICTRLL1_BASE (KSEG1 | 0x1D460200) -+#define GPON_ICTRLL1_END (KSEG1 | 0x1D4603FF) -+#define GPON_ICTRLL1_SIZE 0x00000200 -+/** address range for ictrll2 -+ 0x1D460400--0x1D4605FF */ -+#define GPON_ICTRLL2_BASE (KSEG1 | 0x1D460400) -+#define GPON_ICTRLL2_END (KSEG1 | 0x1D4605FF) -+#define GPON_ICTRLL2_SIZE 0x00000200 -+/** address range for ictrll3 -+ 0x1D460600--0x1D4607FF */ -+#define GPON_ICTRLL3_BASE (KSEG1 | 0x1D460600) -+#define GPON_ICTRLL3_END (KSEG1 | 0x1D4607FF) -+#define GPON_ICTRLL3_SIZE 0x00000200 -+/** address range for ictrlc0 -+ 0x1D461000--0x1D4610FF */ -+#define GPON_ICTRLC0_BASE (KSEG1 | 0x1D461000) -+#define GPON_ICTRLC0_END (KSEG1 | 0x1D4610FF) -+#define GPON_ICTRLC0_SIZE 0x00000100 -+/** address range for ictrlc1 -+ 0x1D461100--0x1D4611FF */ -+#define GPON_ICTRLC1_BASE (KSEG1 | 0x1D461100) -+#define GPON_ICTRLC1_END (KSEG1 | 0x1D4611FF) -+#define GPON_ICTRLC1_SIZE 0x00000100 -+/** address range for fsqm -+ 0x1D500000--0x1D5FFFFF */ -+#define GPON_FSQM_BASE (KSEG1 | 0x1D500000) -+#define GPON_FSQM_END (KSEG1 | 0x1D5FFFFF) -+#define GPON_FSQM_SIZE 0x00100000 -+/** address range for pctrl -+ 0x1D600000--0x1D6001FF */ -+#define GPON_PCTRL_BASE (KSEG1 | 0x1D600000) -+#define GPON_PCTRL_END (KSEG1 | 0x1D6001FF) -+#define GPON_PCTRL_SIZE 0x00000200 -+/** address range for link0 -+ 0x1D600200--0x1D6002FF */ -+#define GPON_LINK0_BASE (KSEG1 | 0x1D600200) -+#define GPON_LINK0_END (KSEG1 | 0x1D6002FF) -+#define GPON_LINK0_SIZE 0x00000100 -+/** address range for link1 -+ 0x1D600300--0x1D6003FF */ -+#define GPON_LINK1_BASE (KSEG1 | 0x1D600300) -+#define GPON_LINK1_END (KSEG1 | 0x1D6003FF) -+#define GPON_LINK1_SIZE 0x00000100 -+/** address range for link2 -+ 0x1D600400--0x1D6004FF */ -+#define GPON_LINK2_BASE (KSEG1 | 0x1D600400) -+#define GPON_LINK2_END (KSEG1 | 0x1D6004FF) -+#define GPON_LINK2_SIZE 0x00000100 -+/** address range for disp -+ 0x1D600500--0x1D6005FF */ -+#define GPON_DISP_BASE (KSEG1 | 0x1D600500) -+#define GPON_DISP_END (KSEG1 | 0x1D6005FF) -+#define GPON_DISP_SIZE 0x00000100 -+/** address range for merge -+ 0x1D600600--0x1D6006FF */ -+#define GPON_MERGE_BASE (KSEG1 | 0x1D600600) -+#define GPON_MERGE_END (KSEG1 | 0x1D6006FF) -+#define GPON_MERGE_SIZE 0x00000100 -+/** address range for tbm -+ 0x1D600700--0x1D6007FF */ -+#define GPON_TBM_BASE (KSEG1 | 0x1D600700) -+#define GPON_TBM_END (KSEG1 | 0x1D6007FF) -+#define GPON_TBM_SIZE 0x00000100 -+/** address range for pe0 -+ 0x1D610000--0x1D61FFFF */ -+#define GPON_PE0_BASE (KSEG1 | 0x1D610000) -+#define GPON_PE0_END (KSEG1 | 0x1D61FFFF) -+#define GPON_PE0_SIZE 0x00010000 -+/** address range for pe1 -+ 0x1D620000--0x1D62FFFF */ -+#define GPON_PE1_BASE (KSEG1 | 0x1D620000) -+#define GPON_PE1_END (KSEG1 | 0x1D62FFFF) -+#define GPON_PE1_SIZE 0x00010000 -+/** address range for pe2 -+ 0x1D630000--0x1D63FFFF */ -+#define GPON_PE2_BASE (KSEG1 | 0x1D630000) -+#define GPON_PE2_END (KSEG1 | 0x1D63FFFF) -+#define GPON_PE2_SIZE 0x00010000 -+/** address range for pe3 -+ 0x1D640000--0x1D64FFFF */ -+#define GPON_PE3_BASE (KSEG1 | 0x1D640000) -+#define GPON_PE3_END (KSEG1 | 0x1D64FFFF) -+#define GPON_PE3_SIZE 0x00010000 -+/** address range for pe4 -+ 0x1D650000--0x1D65FFFF */ -+#define GPON_PE4_BASE (KSEG1 | 0x1D650000) -+#define GPON_PE4_END (KSEG1 | 0x1D65FFFF) -+#define GPON_PE4_SIZE 0x00010000 -+/** address range for pe5 -+ 0x1D660000--0x1D66FFFF */ -+#define GPON_PE5_BASE (KSEG1 | 0x1D660000) -+#define GPON_PE5_END (KSEG1 | 0x1D66FFFF) -+#define GPON_PE5_SIZE 0x00010000 -+/** address range for sys_gpe -+ 0x1D700000--0x1D7000FF */ -+#define GPON_SYS_GPE_BASE (KSEG1 | 0x1D700000) -+#define GPON_SYS_GPE_END (KSEG1 | 0x1D7000FF) -+#define GPON_SYS_GPE_SIZE 0x00000100 -+/** address range for eim -+ 0x1D800000--0x1D800FFF */ -+#define GPON_EIM_BASE (KSEG1 | 0x1D800000) -+#define GPON_EIM_END (KSEG1 | 0x1D800FFF) -+#define GPON_EIM_SIZE 0x00001000 -+/** address range for sxgmii -+ 0x1D808800--0x1D8088FF */ -+#define GPON_SXGMII_BASE (KSEG1 | 0x1D808800) -+#define GPON_SXGMII_END (KSEG1 | 0x1D8088FF) -+#define GPON_SXGMII_SIZE 0x00000100 -+/** address range for sgmii -+ 0x1D808C00--0x1D808CFF */ -+#define GPON_SGMII_BASE (KSEG1 | 0x1D808C00) -+#define GPON_SGMII_END (KSEG1 | 0x1D808CFF) -+#define GPON_SGMII_SIZE 0x00000100 -+/** address range for gpio0 -+ 0x1D810000--0x1D81007F */ -+#define GPON_GPIO0_BASE (KSEG1 | 0x1D810000) -+#define GPON_GPIO0_END (KSEG1 | 0x1D81007F) -+#define GPON_GPIO0_SIZE 0x00000080 -+/** address range for gpio2 -+ 0x1D810100--0x1D81017F */ -+#define GPON_GPIO2_BASE (KSEG1 | 0x1D810100) -+#define GPON_GPIO2_END (KSEG1 | 0x1D81017F) -+#define GPON_GPIO2_SIZE 0x00000080 -+/** address range for sys_eth -+ 0x1DB00000--0x1DB000FF */ -+#define GPON_SYS_ETH_BASE (KSEG1 | 0x1DB00000) -+#define GPON_SYS_ETH_END (KSEG1 | 0x1DB000FF) -+#define GPON_SYS_ETH_SIZE 0x00000100 -+/** address range for padctrl0 -+ 0x1DB01000--0x1DB010FF */ -+#define GPON_PADCTRL0_BASE (KSEG1 | 0x1DB01000) -+#define GPON_PADCTRL0_END (KSEG1 | 0x1DB010FF) -+#define GPON_PADCTRL0_SIZE 0x00000100 -+/** address range for padctrl2 -+ 0x1DB02000--0x1DB020FF */ -+#define GPON_PADCTRL2_BASE (KSEG1 | 0x1DB02000) -+#define GPON_PADCTRL2_END (KSEG1 | 0x1DB020FF) -+#define GPON_PADCTRL2_SIZE 0x00000100 -+/** address range for gtc -+ 0x1DC05000--0x1DC052D4 */ -+#define GPON_GTC_BASE (KSEG1 | 0x1DC05000) -+#define GPON_GTC_END (KSEG1 | 0x1DC052D4) -+#define GPON_GTC_SIZE 0x000002D5 -+/** address range for pma -+ 0x1DD00000--0x1DD003FF */ -+#define GPON_PMA_BASE (KSEG1 | 0x1DD00000) -+#define GPON_PMA_END (KSEG1 | 0x1DD003FF) -+#define GPON_PMA_SIZE 0x00000400 -+/** address range for fcsic -+ 0x1DD00600--0x1DD0061F */ -+#define GPON_FCSIC_BASE (KSEG1 | 0x1DD00600) -+#define GPON_FCSIC_END (KSEG1 | 0x1DD0061F) -+#define GPON_FCSIC_SIZE 0x00000020 -+/** address range for pma_int200 -+ 0x1DD00700--0x1DD0070F */ -+#define GPON_PMA_INT200_BASE (KSEG1 | 0x1DD00700) -+#define GPON_PMA_INT200_END (KSEG1 | 0x1DD0070F) -+#define GPON_PMA_INT200_SIZE 0x00000010 -+/** address range for pma_inttx -+ 0x1DD00720--0x1DD0072F */ -+#define GPON_PMA_INTTX_BASE (KSEG1 | 0x1DD00720) -+#define GPON_PMA_INTTX_END (KSEG1 | 0x1DD0072F) -+#define GPON_PMA_INTTX_SIZE 0x00000010 -+/** address range for pma_intrx -+ 0x1DD00740--0x1DD0074F */ -+#define GPON_PMA_INTRX_BASE (KSEG1 | 0x1DD00740) -+#define GPON_PMA_INTRX_END (KSEG1 | 0x1DD0074F) -+#define GPON_PMA_INTRX_SIZE 0x00000010 -+/** address range for gtc_pma -+ 0x1DEFFF00--0x1DEFFFFF */ -+#define GPON_GTC_PMA_BASE (KSEG1 | 0x1DEFFF00) -+#define GPON_GTC_PMA_END (KSEG1 | 0x1DEFFFFF) -+#define GPON_GTC_PMA_SIZE 0x00000100 -+/** address range for sys -+ 0x1DF00000--0x1DF000FF */ -+#define GPON_SYS_BASE (KSEG1 | 0x1DF00000) -+#define GPON_SYS_END (KSEG1 | 0x1DF000FF) -+#define GPON_SYS_SIZE 0x00000100 -+/** address range for asc1 -+ 0x1E100B00--0x1E100BFF */ -+#define GPON_ASC1_BASE (KSEG1 | 0x1E100B00) -+#define GPON_ASC1_END (KSEG1 | 0x1E100BFF) -+#define GPON_ASC1_SIZE 0x00000100 -+/** address range for asc0 -+ 0x1E100C00--0x1E100CFF */ -+#define GPON_ASC0_BASE (KSEG1 | 0x1E100C00) -+#define GPON_ASC0_END (KSEG1 | 0x1E100CFF) -+#define GPON_ASC0_SIZE 0x00000100 -+/** address range for i2c -+ 0x1E200000--0x1E20FFFF */ -+#define GPON_I2C_BASE (KSEG1 | 0x1E200000) -+#define GPON_I2C_END (KSEG1 | 0x1E20FFFF) -+#define GPON_I2C_SIZE 0x00010000 -+/** address range for gpio1 -+ 0x1E800100--0x1E80017F */ -+#define GPON_GPIO1_BASE (KSEG1 | 0x1E800100) -+#define GPON_GPIO1_END (KSEG1 | 0x1E80017F) -+#define GPON_GPIO1_SIZE 0x00000080 -+/** address range for gpio3 -+ 0x1E800200--0x1E80027F */ -+#define GPON_GPIO3_BASE (KSEG1 | 0x1E800200) -+#define GPON_GPIO3_END (KSEG1 | 0x1E80027F) -+#define GPON_GPIO3_SIZE 0x00000080 -+/** address range for gpio4 -+ 0x1E800300--0x1E80037F */ -+#define GPON_GPIO4_BASE (KSEG1 | 0x1E800300) -+#define GPON_GPIO4_END (KSEG1 | 0x1E80037F) -+#define GPON_GPIO4_SIZE 0x00000080 -+/** address range for padctrl1 -+ 0x1E800400--0x1E8004FF */ -+#define GPON_PADCTRL1_BASE (KSEG1 | 0x1E800400) -+#define GPON_PADCTRL1_END (KSEG1 | 0x1E8004FF) -+#define GPON_PADCTRL1_SIZE 0x00000100 -+/** address range for padctrl3 -+ 0x1E800500--0x1E8005FF */ -+#define GPON_PADCTRL3_BASE (KSEG1 | 0x1E800500) -+#define GPON_PADCTRL3_END (KSEG1 | 0x1E8005FF) -+#define GPON_PADCTRL3_SIZE 0x00000100 -+/** address range for padctrl4 -+ 0x1E800600--0x1E8006FF */ -+#define GPON_PADCTRL4_BASE (KSEG1 | 0x1E800600) -+#define GPON_PADCTRL4_END (KSEG1 | 0x1E8006FF) -+#define GPON_PADCTRL4_SIZE 0x00000100 -+/** address range for status -+ 0x1E802000--0x1E80207F */ -+#define GPON_STATUS_BASE (KSEG1 | 0x1E802000) -+#define GPON_STATUS_END (KSEG1 | 0x1E80207F) -+#define GPON_STATUS_SIZE 0x00000080 -+/** address range for dcdc_1v0 -+ 0x1E803000--0x1E8033FF */ -+#define GPON_DCDC_1V0_BASE (KSEG1 | 0x1E803000) -+#define GPON_DCDC_1V0_END (KSEG1 | 0x1E8033FF) -+#define GPON_DCDC_1V0_SIZE 0x00000400 -+/** address range for dcdc_ddr -+ 0x1E804000--0x1E8043FF */ -+#define GPON_DCDC_DDR_BASE (KSEG1 | 0x1E804000) -+#define GPON_DCDC_DDR_END (KSEG1 | 0x1E8043FF) -+#define GPON_DCDC_DDR_SIZE 0x00000400 -+/** address range for dcdc_apd -+ 0x1E805000--0x1E8053FF */ -+#define GPON_DCDC_APD_BASE (KSEG1 | 0x1E805000) -+#define GPON_DCDC_APD_END (KSEG1 | 0x1E8053FF) -+#define GPON_DCDC_APD_SIZE 0x00000400 -+/** address range for sys1 -+ 0x1EF00000--0x1EF000FF */ -+#define GPON_SYS1_BASE (KSEG1 | 0x1EF00000) -+#define GPON_SYS1_END (KSEG1 | 0x1EF000FF) -+#define GPON_SYS1_SIZE 0x00000100 -+/** address range for sbs0ctrl -+ 0x1F080000--0x1F0801FF */ -+#define GPON_SBS0CTRL_BASE (KSEG1 | 0x1F080000) -+#define GPON_SBS0CTRL_END (KSEG1 | 0x1F0801FF) -+#define GPON_SBS0CTRL_SIZE 0x00000200 -+/** address range for sbs0red -+ 0x1F080200--0x1F08027F */ -+#define GPON_SBS0RED_BASE (KSEG1 | 0x1F080200) -+#define GPON_SBS0RED_END (KSEG1 | 0x1F08027F) -+#define GPON_SBS0RED_SIZE 0x00000080 -+/** address range for sbs0ram -+ 0x1F200000--0x1F32FFFF */ -+#define GPON_SBS0RAM_BASE (KSEG1 | 0x1F200000) -+#define GPON_SBS0RAM_END (KSEG1 | 0x1F32FFFF) -+#define GPON_SBS0RAM_SIZE 0x00130000 -+/** address range for ddrdb -+ 0x1F701000--0x1F701FFF */ -+#define GPON_DDRDB_BASE (KSEG1 | 0x1F701000) -+#define GPON_DDRDB_END (KSEG1 | 0x1F701FFF) -+#define GPON_DDRDB_SIZE 0x00001000 -+/** address range for sbiu -+ 0x1F880000--0x1F8800FF */ -+#define GPON_SBIU_BASE (KSEG1 | 0x1F880000) -+#define GPON_SBIU_END (KSEG1 | 0x1F8800FF) -+#define GPON_SBIU_SIZE 0x00000100 -+/** address range for icu0 -+ 0x1F880200--0x1F8802DF */ -+#define GPON_ICU0_BASE (KSEG1 | 0x1F880200) -+#define GPON_ICU0_END (KSEG1 | 0x1F8802DF) -+#define GPON_ICU0_SIZE 0x000000E0 -+/** address range for icu1 -+ 0x1F880300--0x1F8803DF */ -+#define GPON_ICU1_BASE (KSEG1 | 0x1F880300) -+#define GPON_ICU1_END (KSEG1 | 0x1F8803DF) -+#define GPON_ICU1_SIZE 0x000000E0 -+/** address range for wdt -+ 0x1F8803F0--0x1F8803FF */ -+#define GPON_WDT_BASE (KSEG1 | 0x1F8803F0) -+#define GPON_WDT_END (KSEG1 | 0x1F8803FF) -+#define GPON_WDT_SIZE 0x00000010 -+ -+/*! @} */ /* GPON_BASE */ -+ -+#endif /* _gpon_reg_base_h */ -+ ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/i2c_reg.h -@@ -0,0 +1,830 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+ -+#ifndef _i2c_reg_h -+#define _i2c_reg_h -+ -+/** \addtogroup I2C_REGISTER -+ @{ -+*/ -+/* access macros */ -+#define i2c_r32(reg) reg_r32(&i2c->reg) -+#define i2c_w32(val, reg) reg_w32(val, &i2c->reg) -+#define i2c_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &i2c->reg) -+#define i2c_r32_table(reg, idx) reg_r32_table(i2c->reg, idx) -+#define i2c_w32_table(val, reg, idx) reg_w32_table(val, i2c->reg, idx) -+#define i2c_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, i2c->reg, idx) -+#define i2c_adr_table(reg, idx) adr_table(i2c->reg, idx) -+ -+ -+/** I2C register structure */ -+struct gpon_reg_i2c -+{ -+ /** I2C Kernel Clock Control Register */ -+ unsigned int clc; /* 0x00000000 */ -+ /** Reserved */ -+ unsigned int res_0; /* 0x00000004 */ -+ /** I2C Identification Register */ -+ unsigned int id; /* 0x00000008 */ -+ /** Reserved */ -+ unsigned int res_1; /* 0x0000000C */ -+ /** I2C RUN Control Register -+ This register enables and disables the I2C peripheral. Before enabling, the I2C has to be configured properly. After enabling no configuration is possible */ -+ unsigned int run_ctrl; /* 0x00000010 */ -+ /** I2C End Data Control Register -+ This register is used to either turn around the data transmission direction or to address another slave without sending a stop condition. Also the software can stop the slave-transmitter by sending a not-accolade when working as master-receiver or even stop data transmission immediately when operating as master-transmitter. The writing to the bits of this control register is only effective when in MASTER RECEIVES BYTES, MASTER TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state */ -+ unsigned int endd_ctrl; /* 0x00000014 */ -+ /** I2C Fractional Divider Configuration Register -+ These register is used to program the fractional divider of the I2C bus. Before the peripheral is switched on by setting the RUN-bit the two (fixed) values for the two operating frequencies are programmed into these (configuration) registers. The Register FDIV_HIGH_CFG has the same layout as I2C_FDIV_CFG. */ -+ unsigned int fdiv_cfg; /* 0x00000018 */ -+ /** I2C Fractional Divider (highspeed mode) Configuration Register -+ These register is used to program the fractional divider of the I2C bus. Before the peripheral is switched on by setting the RUN-bit the two (fixed) values for the two operating frequencies are programmed into these (configuration) registers. The Register FDIV_CFG has the same layout as I2C_FDIV_CFG. */ -+ unsigned int fdiv_high_cfg; /* 0x0000001C */ -+ /** I2C Address Configuration Register */ -+ unsigned int addr_cfg; /* 0x00000020 */ -+ /** I2C Bus Status Register -+ This register gives a status information of the I2C. This additional information can be used by the software to start proper actions. */ -+ unsigned int bus_stat; /* 0x00000024 */ -+ /** I2C FIFO Configuration Register */ -+ unsigned int fifo_cfg; /* 0x00000028 */ -+ /** I2C Maximum Received Packet Size Register */ -+ unsigned int mrps_ctrl; /* 0x0000002C */ -+ /** I2C Received Packet Size Status Register */ -+ unsigned int rps_stat; /* 0x00000030 */ -+ /** I2C Transmit Packet Size Register */ -+ unsigned int tps_ctrl; /* 0x00000034 */ -+ /** I2C Filled FIFO Stages Status Register */ -+ unsigned int ffs_stat; /* 0x00000038 */ -+ /** Reserved */ -+ unsigned int res_2; /* 0x0000003C */ -+ /** I2C Timing Configuration Register */ -+ unsigned int tim_cfg; /* 0x00000040 */ -+ /** Reserved */ -+ unsigned int res_3[7]; /* 0x00000044 */ -+ /** I2C Error Interrupt Request Source Mask Register */ -+ unsigned int err_irqsm; /* 0x00000060 */ -+ /** I2C Error Interrupt Request Source Status Register */ -+ unsigned int err_irqss; /* 0x00000064 */ -+ /** I2C Error Interrupt Request Source Clear Register */ -+ unsigned int err_irqsc; /* 0x00000068 */ -+ /** Reserved */ -+ unsigned int res_4; /* 0x0000006C */ -+ /** I2C Protocol Interrupt Request Source Mask Register */ -+ unsigned int p_irqsm; /* 0x00000070 */ -+ /** I2C Protocol Interrupt Request Source Status Register */ -+ unsigned int p_irqss; /* 0x00000074 */ -+ /** I2C Protocol Interrupt Request Source Clear Register */ -+ unsigned int p_irqsc; /* 0x00000078 */ -+ /** Reserved */ -+ unsigned int res_5; /* 0x0000007C */ -+ /** I2C Raw Interrupt Status Register */ -+ unsigned int ris; /* 0x00000080 */ -+ /** I2C Interrupt Mask Control Register */ -+ unsigned int imsc; /* 0x00000084 */ -+ /** I2C Masked Interrupt Status Register */ -+ unsigned int mis; /* 0x00000088 */ -+ /** I2C Interrupt Clear Register */ -+ unsigned int icr; /* 0x0000008C */ -+ /** I2C Interrupt Set Register */ -+ unsigned int isr; /* 0x00000090 */ -+ /** I2C DMA Enable Register */ -+ unsigned int dmae; /* 0x00000094 */ -+ /** Reserved */ -+ unsigned int res_6[8154]; /* 0x00000098 */ -+ /** I2C Transmit Data Register */ -+ unsigned int txd; /* 0x00008000 */ -+ /** Reserved */ -+ unsigned int res_7[4095]; /* 0x00008004 */ -+ /** I2C Receive Data Register */ -+ unsigned int rxd; /* 0x0000C000 */ -+ /** Reserved */ -+ unsigned int res_8[4095]; /* 0x0000C004 */ -+}; -+ -+ -+/* Fields of "I2C Kernel Clock Control Register" */ -+/** Clock Divider for Optional Run Mode (AHB peripherals) -+ Max 8-bit divider value. Note: As long as the new divider value ORMC is not valid, the register returns 0x0000 00xx on reading. */ -+#define I2C_CLC_ORMC_MASK 0x00FF0000 -+/** field offset */ -+#define I2C_CLC_ORMC_OFFSET 16 -+/** Clock Divider for Normal Run Mode -+ Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long as the new divider value RMC is not valid, the register returns 0x0000 00xx on reading. */ -+#define I2C_CLC_RMC_MASK 0x0000FF00 -+/** field offset */ -+#define I2C_CLC_RMC_OFFSET 8 -+/** Fast Shut-Off Enable Bit */ -+#define I2C_CLC_FSOE 0x00000020 -+/* Disable -+#define I2C_CLC_FSOE_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_CLC_FSOE_EN 0x00000020 -+/** Suspend Bit Write Enable for OCDS */ -+#define I2C_CLC_SBWE 0x00000010 -+/* Disable -+#define I2C_CLC_SBWE_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_CLC_SBWE_EN 0x00000010 -+/** Disable External Request Disable */ -+#define I2C_CLC_EDIS 0x00000008 -+/* Enable -+#define I2C_CLC_EDIS_EN 0x00000000 */ -+/** Disable */ -+#define I2C_CLC_EDIS_DIS 0x00000008 -+/** Suspend Enable Bit for OCDS */ -+#define I2C_CLC_SPEN 0x00000004 -+/* Disable -+#define I2C_CLC_SPEN_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_CLC_SPEN_EN 0x00000004 -+/** Disable Status Bit -+ Bit DISS can be modified only by writing to bit DISR */ -+#define I2C_CLC_DISS 0x00000002 -+/* Enable -+#define I2C_CLC_DISS_EN 0x00000000 */ -+/** Disable */ -+#define I2C_CLC_DISS_DIS 0x00000002 -+/** Disable Request Bit */ -+#define I2C_CLC_DISR 0x00000001 -+/* Module disable not requested -+#define I2C_CLC_DISR_OFF 0x00000000 */ -+/** Module disable requested */ -+#define I2C_CLC_DISR_ON 0x00000001 -+ -+/* Fields of "I2C Identification Register" */ -+/** Module ID */ -+#define I2C_ID_ID_MASK 0x0000FF00 -+/** field offset */ -+#define I2C_ID_ID_OFFSET 8 -+/** Revision */ -+#define I2C_ID_REV_MASK 0x000000FF -+/** field offset */ -+#define I2C_ID_REV_OFFSET 0 -+ -+/* Fields of "I2C RUN Control Register" */ -+/** Enabling I2C Interface -+ Only when this bit is set to zero, the configuration registers of the I2C peripheral are writable by SW. */ -+#define I2C_RUN_CTRL_RUN 0x00000001 -+/* Disable -+#define I2C_RUN_CTRL_RUN_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_RUN_CTRL_RUN_EN 0x00000001 -+ -+/* Fields of "I2C End Data Control Register" */ -+/** Set End of Transmission -+ Note:Do not write '1' to this bit when bus is free. This will cause an abort after the first byte when a new transfer is started. */ -+#define I2C_ENDD_CTRL_SETEND 0x00000002 -+/* No-Operation -+#define I2C_ENDD_CTRL_SETEND_NOP 0x00000000 */ -+/** Master Receives Bytes */ -+#define I2C_ENDD_CTRL_SETEND_MRB 0x00000002 -+/** Set Restart Condition */ -+#define I2C_ENDD_CTRL_SETRSC 0x00000001 -+/* No-Operation -+#define I2C_ENDD_CTRL_SETRSC_NOP 0x00000000 */ -+/** Master Restart */ -+#define I2C_ENDD_CTRL_SETRSC_RESTART 0x00000001 -+ -+/* Fields of "I2C Fractional Divider Configuration Register" */ -+/** Decrement Value of fractional divider */ -+#define I2C_FDIV_CFG_INC_MASK 0x00FF0000 -+/** field offset */ -+#define I2C_FDIV_CFG_INC_OFFSET 16 -+/** Increment Value of fractional divider */ -+#define I2C_FDIV_CFG_DEC_MASK 0x000007FF -+/** field offset */ -+#define I2C_FDIV_CFG_DEC_OFFSET 0 -+ -+/* Fields of "I2C Fractional Divider (highspeed mode) Configuration Register" */ -+/** Decrement Value of fractional divider */ -+#define I2C_FDIV_HIGH_CFG_INC_MASK 0x00FF0000 -+/** field offset */ -+#define I2C_FDIV_HIGH_CFG_INC_OFFSET 16 -+/** Increment Value of fractional divider */ -+#define I2C_FDIV_HIGH_CFG_DEC_MASK 0x000007FF -+/** field offset */ -+#define I2C_FDIV_HIGH_CFG_DEC_OFFSET 0 -+ -+/* Fields of "I2C Address Configuration Register" */ -+/** Stop on Packet End -+ If device works as receiver a not acknowledge is generated in both cases. After successful transmission of a master code (during high speed mode) SOPE is not considered till a stop condition is manually generated by SETEND. */ -+#define I2C_ADDR_CFG_SOPE 0x00200000 -+/* Disable -+#define I2C_ADDR_CFG_SOPE_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_ADDR_CFG_SOPE_EN 0x00200000 -+/** Stop on Not Acknowledge -+ After successful transmission of a master code (during high speed mode) SONA is not considered till a stop condition is manually generated by SETEND. */ -+#define I2C_ADDR_CFG_SONA 0x00100000 -+/* Disable -+#define I2C_ADDR_CFG_SONA_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_ADDR_CFG_SONA_EN 0x00100000 -+/** Master Enable */ -+#define I2C_ADDR_CFG_MnS 0x00080000 -+/* Disable -+#define I2C_ADDR_CFG_MnS_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_ADDR_CFG_MnS_EN 0x00080000 -+/** Master Code Enable */ -+#define I2C_ADDR_CFG_MCE 0x00040000 -+/* Disable -+#define I2C_ADDR_CFG_MCE_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_ADDR_CFG_MCE_EN 0x00040000 -+/** General Call Enable */ -+#define I2C_ADDR_CFG_GCE 0x00020000 -+/* Disable -+#define I2C_ADDR_CFG_GCE_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_ADDR_CFG_GCE_EN 0x00020000 -+/** Ten Bit Address Mode */ -+#define I2C_ADDR_CFG_TBAM 0x00010000 -+/* 7-bit address mode enabled. -+#define I2C_ADDR_CFG_TBAM_7bit 0x00000000 */ -+/** 10-bit address mode enabled. */ -+#define I2C_ADDR_CFG_TBAM_10bit 0x00010000 -+/** I2C Bus device address -+ This is the address of this device. (Watch out for reserved addresses by referring to Phillips Spec V2.1) This could either be a 7bit- address (bits [7:1]) or a 10bit- address (bits [9:0]). Note:The validity of the bits are in accordance with the TBAM bit. Bit-1 (Bit-0) is the LSB of the device address. */ -+#define I2C_ADDR_CFG_ADR_MASK 0x000003FF -+/** field offset */ -+#define I2C_ADDR_CFG_ADR_OFFSET 0 -+ -+/* Fields of "I2C Bus Status Register" */ -+/** Read / not Write */ -+#define I2C_BUS_STAT_RNW 0x00000004 -+/* Write to I2C Bus. -+#define I2C_BUS_STAT_RNW_WRITE 0x00000000 */ -+/** Read from I2C Bus. */ -+#define I2C_BUS_STAT_RNW_READ 0x00000004 -+/** Bus Status */ -+#define I2C_BUS_STAT_BS_MASK 0x00000003 -+/** field offset */ -+#define I2C_BUS_STAT_BS_OFFSET 0 -+/** I2C Bus is free. */ -+#define I2C_BUS_STAT_BS_FREE 0x00000000 -+/** A start condition has been detected on the bus (bus busy). */ -+#define I2C_BUS_STAT_BS_SC 0x00000001 -+/** The device is working as master and has claimed the control on the I2C-bus (busy master). */ -+#define I2C_BUS_STAT_BS_BM 0x00000002 -+/** A remote master has accessed this device as slave. */ -+#define I2C_BUS_STAT_BS_RM 0x00000003 -+ -+/* Fields of "I2C FIFO Configuration Register" */ -+/** TX FIFO Flow Control */ -+#define I2C_FIFO_CFG_TXFC 0x00020000 -+/* TX FIFO not as Flow Controller -+#define I2C_FIFO_CFG_TXFC_TXNFC 0x00000000 */ -+/** RX FIFO Flow Control */ -+#define I2C_FIFO_CFG_RXFC 0x00010000 -+/* RX FIFO not as Flow Controller -+#define I2C_FIFO_CFG_RXFC_RXNFC 0x00000000 */ -+/** The reset value depends on the used character sizes of the peripheral. The maximum selectable alignment depends on the maximum number of characters per stage. */ -+#define I2C_FIFO_CFG_TXFA_MASK 0x00003000 -+/** field offset */ -+#define I2C_FIFO_CFG_TXFA_OFFSET 12 -+/** Byte aligned (character alignment) */ -+#define I2C_FIFO_CFG_TXFA_TXFA0 0x00000000 -+/** Half word aligned (character alignment of two characters) */ -+#define I2C_FIFO_CFG_TXFA_TXFA1 0x00001000 -+/** Word aligned (character alignment of four characters) */ -+#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000 -+/** Double word aligned (character alignment of eight */ -+#define I2C_FIFO_CFG_TXFA_TXFA3 0x00003000 -+/** The reset value depends on the used character sizes of the peripheral. The maximum selectable alignment depends on the maximum number of characters per stage. */ -+#define I2C_FIFO_CFG_RXFA_MASK 0x00000300 -+/** field offset */ -+#define I2C_FIFO_CFG_RXFA_OFFSET 8 -+/** Byte aligned (character alignment) */ -+#define I2C_FIFO_CFG_RXFA_RXFA0 0x00000000 -+/** Half word aligned (character alignment of two characters) */ -+#define I2C_FIFO_CFG_RXFA_RXFA1 0x00000100 -+/** Word aligned (character alignment of four characters) */ -+#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200 -+/** Double word aligned (character alignment of eight */ -+#define I2C_FIFO_CFG_RXFA_RXFA3 0x00000300 -+/** DMA controller does not support a burst size of 2 words. The reset value is the half of the FIFO size. The maximum selectable burst size is smaller than the FIFO size. */ -+#define I2C_FIFO_CFG_TXBS_MASK 0x00000030 -+/** field offset */ -+#define I2C_FIFO_CFG_TXBS_OFFSET 4 -+/** 1 word */ -+#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000 -+/** 2 words */ -+#define I2C_FIFO_CFG_TXBS_TXBS1 0x00000010 -+/** 4 words */ -+#define I2C_FIFO_CFG_TXBS_TXBS2 0x00000020 -+/** 8 words */ -+#define I2C_FIFO_CFG_TXBS_TXBS3 0x00000030 -+/** DMA controller does not support a burst size of 2 words. The reset value is the half of the FIFO size. The maximum selectable burst size is smaller than the FIFO size. */ -+#define I2C_FIFO_CFG_RXBS_MASK 0x00000003 -+/** field offset */ -+#define I2C_FIFO_CFG_RXBS_OFFSET 0 -+/** 1 word */ -+#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000 -+/** 2 words */ -+#define I2C_FIFO_CFG_RXBS_RXBS1 0x00000001 -+/** 4 words */ -+#define I2C_FIFO_CFG_RXBS_RXBS2 0x00000002 -+/** 8 words */ -+#define I2C_FIFO_CFG_RXBS_RXBS3 0x00000003 -+ -+/* Fields of "I2C Maximum Received Packet Size Register" */ -+/** MRPS */ -+#define I2C_MRPS_CTRL_MRPS_MASK 0x00003FFF -+/** field offset */ -+#define I2C_MRPS_CTRL_MRPS_OFFSET 0 -+ -+/* Fields of "I2C Received Packet Size Status Register" */ -+/** RPS */ -+#define I2C_RPS_STAT_RPS_MASK 0x00003FFF -+/** field offset */ -+#define I2C_RPS_STAT_RPS_OFFSET 0 -+ -+/* Fields of "I2C Transmit Packet Size Register" */ -+/** TPS */ -+#define I2C_TPS_CTRL_TPS_MASK 0x00003FFF -+/** field offset */ -+#define I2C_TPS_CTRL_TPS_OFFSET 0 -+ -+/* Fields of "I2C Filled FIFO Stages Status Register" */ -+/** FFS */ -+#define I2C_FFS_STAT_FFS_MASK 0x0000000F -+/** field offset */ -+#define I2C_FFS_STAT_FFS_OFFSET 0 -+ -+/* Fields of "I2C Timing Configuration Register" */ -+/** SDA Delay Stages for Start/Stop bit in High Speed Mode -+ The actual delay is calculated as the value of this field + 3 */ -+#define I2C_TIM_CFG_HS_SDA_DEL_MASK 0x00070000 -+/** field offset */ -+#define I2C_TIM_CFG_HS_SDA_DEL_OFFSET 16 -+/** Enable Fast Mode SCL Low period timing */ -+#define I2C_TIM_CFG_FS_SCL_LOW 0x00008000 -+/* Disable -+#define I2C_TIM_CFG_FS_SCL_LOW_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_TIM_CFG_FS_SCL_LOW_EN 0x00008000 -+/** SCL Delay Stages for Hold Time Start (Restart) Bit. -+ The actual delay is calculated as the value of this field + 2 */ -+#define I2C_TIM_CFG_SCL_DEL_HD_STA_MASK 0x00000E00 -+/** field offset */ -+#define I2C_TIM_CFG_SCL_DEL_HD_STA_OFFSET 9 -+/** SDA Delay Stages for Start/Stop bit in High Speed Mode -+ The actual delay is calculated as the value of this field + 3 */ -+#define I2C_TIM_CFG_HS_SDA_DEL_HD_DAT_MASK 0x000001C0 -+/** field offset */ -+#define I2C_TIM_CFG_HS_SDA_DEL_HD_DAT_OFFSET 6 -+/** SDA Delay Stages for Start/Stop bit in High Speed Mode -+ The actual delay is calculated as the value of this field + 3 */ -+#define I2C_TIM_CFG_SDA_DEL_HD_DAT_MASK 0x0000003F -+/** field offset */ -+#define I2C_TIM_CFG_SDA_DEL_HD_DAT_OFFSET 0 -+ -+/* Fields of "I2C Error Interrupt Request Source Mask Register" */ -+/** Enables the corresponding error interrupt. */ -+#define I2C_ERR_IRQSM_TXF_OFL 0x00000008 -+/* Disable -+#define I2C_ERR_IRQSM_TXF_OFL_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_ERR_IRQSM_TXF_OFL_EN 0x00000008 -+/** Enables the corresponding error interrupt. */ -+#define I2C_ERR_IRQSM_TXF_UFL 0x00000004 -+/* Disable -+#define I2C_ERR_IRQSM_TXF_UFL_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_ERR_IRQSM_TXF_UFL_EN 0x00000004 -+/** Enables the corresponding error interrupt. */ -+#define I2C_ERR_IRQSM_RXF_OFL 0x00000002 -+/* Disable -+#define I2C_ERR_IRQSM_RXF_OFL_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_ERR_IRQSM_RXF_OFL_EN 0x00000002 -+/** Enables the corresponding error interrupt. */ -+#define I2C_ERR_IRQSM_RXF_UFL 0x00000001 -+/* Disable -+#define I2C_ERR_IRQSM_RXF_UFL_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_ERR_IRQSM_RXF_UFL_EN 0x00000001 -+ -+/* Fields of "I2C Error Interrupt Request Source Status Register" */ -+/** TXF_OFL */ -+#define I2C_ERR_IRQSS_TXF_OFL 0x00000008 -+/* Nothing -+#define I2C_ERR_IRQSS_TXF_OFL_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_ERR_IRQSS_TXF_OFL_INTOCC 0x00000008 -+/** TXF_UFL */ -+#define I2C_ERR_IRQSS_TXF_UFL 0x00000004 -+/* Nothing -+#define I2C_ERR_IRQSS_TXF_UFL_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_ERR_IRQSS_TXF_UFL_INTOCC 0x00000004 -+/** RXF_OFL */ -+#define I2C_ERR_IRQSS_RXF_OFL 0x00000002 -+/* Nothing -+#define I2C_ERR_IRQSS_RXF_OFL_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_ERR_IRQSS_RXF_OFL_INTOCC 0x00000002 -+/** RXF_UFL */ -+#define I2C_ERR_IRQSS_RXF_UFL 0x00000001 -+/* Nothing -+#define I2C_ERR_IRQSS_RXF_UFL_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_ERR_IRQSS_RXF_UFL_INTOCC 0x00000001 -+ -+/* Fields of "I2C Error Interrupt Request Source Clear Register" */ -+/** TXF_OFL */ -+#define I2C_ERR_IRQSC_TXF_OFL 0x00000008 -+/* No-Operation -+#define I2C_ERR_IRQSC_TXF_OFL_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_ERR_IRQSC_TXF_OFL_CLR 0x00000008 -+/** TXF_UFL */ -+#define I2C_ERR_IRQSC_TXF_UFL 0x00000004 -+/* No-Operation -+#define I2C_ERR_IRQSC_TXF_UFL_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_ERR_IRQSC_TXF_UFL_CLR 0x00000004 -+/** RXF_OFL */ -+#define I2C_ERR_IRQSC_RXF_OFL 0x00000002 -+/* No-Operation -+#define I2C_ERR_IRQSC_RXF_OFL_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_ERR_IRQSC_RXF_OFL_CLR 0x00000002 -+/** RXF_UFL */ -+#define I2C_ERR_IRQSC_RXF_UFL 0x00000001 -+/* No-Operation -+#define I2C_ERR_IRQSC_RXF_UFL_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_ERR_IRQSC_RXF_UFL_CLR 0x00000001 -+ -+/* Fields of "I2C Protocol Interrupt Request Source Mask Register" */ -+/** Enables the corresponding interrupt. */ -+#define I2C_P_IRQSM_RX 0x00000040 -+/* Disable -+#define I2C_P_IRQSM_RX_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_P_IRQSM_RX_EN 0x00000040 -+/** Enables the corresponding interrupt. */ -+#define I2C_P_IRQSM_TX_END 0x00000020 -+/* Disable -+#define I2C_P_IRQSM_TX_END_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_P_IRQSM_TX_END_EN 0x00000020 -+/** Enables the corresponding interrupt. */ -+#define I2C_P_IRQSM_NACK 0x00000010 -+/* Disable -+#define I2C_P_IRQSM_NACK_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_P_IRQSM_NACK_EN 0x00000010 -+/** Enables the corresponding interrupt. */ -+#define I2C_P_IRQSM_AL 0x00000008 -+/* Disable -+#define I2C_P_IRQSM_AL_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_P_IRQSM_AL_EN 0x00000008 -+/** Enables the corresponding interrupt. */ -+#define I2C_P_IRQSM_MC 0x00000004 -+/* Disable -+#define I2C_P_IRQSM_MC_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_P_IRQSM_MC_EN 0x00000004 -+/** Enables the corresponding interrupt. */ -+#define I2C_P_IRQSM_GC 0x00000002 -+/* Disable -+#define I2C_P_IRQSM_GC_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_P_IRQSM_GC_EN 0x00000002 -+/** Enables the corresponding interrupt. */ -+#define I2C_P_IRQSM_AM 0x00000001 -+/* Disable -+#define I2C_P_IRQSM_AM_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_P_IRQSM_AM_EN 0x00000001 -+ -+/* Fields of "I2C Protocol Interrupt Request Source Status Register" */ -+/** RX */ -+#define I2C_P_IRQSS_RX 0x00000040 -+/* Nothing -+#define I2C_P_IRQSS_RX_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_P_IRQSS_RX_INTOCC 0x00000040 -+/** TX_END */ -+#define I2C_P_IRQSS_TX_END 0x00000020 -+/* Nothing -+#define I2C_P_IRQSS_TX_END_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_P_IRQSS_TX_END_INTOCC 0x00000020 -+/** NACK */ -+#define I2C_P_IRQSS_NACK 0x00000010 -+/* Nothing -+#define I2C_P_IRQSS_NACK_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_P_IRQSS_NACK_INTOCC 0x00000010 -+/** AL */ -+#define I2C_P_IRQSS_AL 0x00000008 -+/* Nothing -+#define I2C_P_IRQSS_AL_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_P_IRQSS_AL_INTOCC 0x00000008 -+/** MC */ -+#define I2C_P_IRQSS_MC 0x00000004 -+/* Nothing -+#define I2C_P_IRQSS_MC_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_P_IRQSS_MC_INTOCC 0x00000004 -+/** GC */ -+#define I2C_P_IRQSS_GC 0x00000002 -+/* Nothing -+#define I2C_P_IRQSS_GC_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_P_IRQSS_GC_INTOCC 0x00000002 -+/** AM */ -+#define I2C_P_IRQSS_AM 0x00000001 -+/* Nothing -+#define I2C_P_IRQSS_AM_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_P_IRQSS_AM_INTOCC 0x00000001 -+ -+/* Fields of "I2C Protocol Interrupt Request Source Clear Register" */ -+/** RX */ -+#define I2C_P_IRQSC_RX 0x00000040 -+/* No-Operation -+#define I2C_P_IRQSC_RX_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_P_IRQSC_RX_CLR 0x00000040 -+/** TX_END */ -+#define I2C_P_IRQSC_TX_END 0x00000020 -+/* No-Operation -+#define I2C_P_IRQSC_TX_END_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_P_IRQSC_TX_END_CLR 0x00000020 -+/** NACK */ -+#define I2C_P_IRQSC_NACK 0x00000010 -+/* No-Operation -+#define I2C_P_IRQSC_NACK_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_P_IRQSC_NACK_CLR 0x00000010 -+/** AL */ -+#define I2C_P_IRQSC_AL 0x00000008 -+/* No-Operation -+#define I2C_P_IRQSC_AL_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_P_IRQSC_AL_CLR 0x00000008 -+/** MC */ -+#define I2C_P_IRQSC_MC 0x00000004 -+/* No-Operation -+#define I2C_P_IRQSC_MC_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_P_IRQSC_MC_CLR 0x00000004 -+/** GC */ -+#define I2C_P_IRQSC_GC 0x00000002 -+/* No-Operation -+#define I2C_P_IRQSC_GC_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_P_IRQSC_GC_CLR 0x00000002 -+/** AM */ -+#define I2C_P_IRQSC_AM 0x00000001 -+/* No-Operation -+#define I2C_P_IRQSC_AM_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_P_IRQSC_AM_CLR 0x00000001 -+ -+/* Fields of "I2C Raw Interrupt Status Register" */ -+/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */ -+#define I2C_RIS_I2C_P_INT 0x00000020 -+/* Nothing -+#define I2C_RIS_I2C_P_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020 -+/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */ -+#define I2C_RIS_I2C_ERR_INT 0x00000010 -+/* Nothing -+#define I2C_RIS_I2C_ERR_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010 -+/** BREQ_INT */ -+#define I2C_RIS_BREQ_INT 0x00000008 -+/* Nothing -+#define I2C_RIS_BREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_RIS_BREQ_INT_INTOCC 0x00000008 -+/** LBREQ_INT */ -+#define I2C_RIS_LBREQ_INT 0x00000004 -+/* Nothing -+#define I2C_RIS_LBREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_RIS_LBREQ_INT_INTOCC 0x00000004 -+/** SREQ_INT */ -+#define I2C_RIS_SREQ_INT 0x00000002 -+/* Nothing -+#define I2C_RIS_SREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_RIS_SREQ_INT_INTOCC 0x00000002 -+/** LSREQ_INT */ -+#define I2C_RIS_LSREQ_INT 0x00000001 -+/* Nothing -+#define I2C_RIS_LSREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_RIS_LSREQ_INT_INTOCC 0x00000001 -+ -+/* Fields of "I2C Interrupt Mask Control Register" */ -+/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */ -+#define I2C_IMSC_I2C_P_INT 0x00000020 -+/* Disable -+#define I2C_IMSC_I2C_P_INT_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_IMSC_I2C_P_INT_EN 0x00000020 -+/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */ -+#define I2C_IMSC_I2C_ERR_INT 0x00000010 -+/* Disable -+#define I2C_IMSC_I2C_ERR_INT_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010 -+/** BREQ_INT */ -+#define I2C_IMSC_BREQ_INT 0x00000008 -+/* Disable -+#define I2C_IMSC_BREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_IMSC_BREQ_INT_EN 0x00000008 -+/** LBREQ_INT */ -+#define I2C_IMSC_LBREQ_INT 0x00000004 -+/* Disable -+#define I2C_IMSC_LBREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_IMSC_LBREQ_INT_EN 0x00000004 -+/** SREQ_INT */ -+#define I2C_IMSC_SREQ_INT 0x00000002 -+/* Disable -+#define I2C_IMSC_SREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_IMSC_SREQ_INT_EN 0x00000002 -+/** LSREQ_INT */ -+#define I2C_IMSC_LSREQ_INT 0x00000001 -+/* Disable -+#define I2C_IMSC_LSREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_IMSC_LSREQ_INT_EN 0x00000001 -+ -+/* Fields of "I2C Masked Interrupt Status Register" */ -+/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */ -+#define I2C_MIS_I2C_P_INT 0x00000020 -+/* Nothing -+#define I2C_MIS_I2C_P_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_MIS_I2C_P_INT_INTOCC 0x00000020 -+/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */ -+#define I2C_MIS_I2C_ERR_INT 0x00000010 -+/* Nothing -+#define I2C_MIS_I2C_ERR_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_MIS_I2C_ERR_INT_INTOCC 0x00000010 -+/** BREQ_INT */ -+#define I2C_MIS_BREQ_INT 0x00000008 -+/* Nothing -+#define I2C_MIS_BREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_MIS_BREQ_INT_INTOCC 0x00000008 -+/** LBREQ_INT */ -+#define I2C_MIS_LBREQ_INT 0x00000004 -+/* Nothing -+#define I2C_MIS_LBREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_MIS_LBREQ_INT_INTOCC 0x00000004 -+/** SREQ_INT */ -+#define I2C_MIS_SREQ_INT 0x00000002 -+/* Nothing -+#define I2C_MIS_SREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_MIS_SREQ_INT_INTOCC 0x00000002 -+/** LSREQ_INT */ -+#define I2C_MIS_LSREQ_INT 0x00000001 -+/* Nothing -+#define I2C_MIS_LSREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_MIS_LSREQ_INT_INTOCC 0x00000001 -+ -+/* Fields of "I2C Interrupt Clear Register" */ -+/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */ -+#define I2C_ICR_I2C_P_INT 0x00000020 -+/* No-Operation -+#define I2C_ICR_I2C_P_INT_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_ICR_I2C_P_INT_CLR 0x00000020 -+/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */ -+#define I2C_ICR_I2C_ERR_INT 0x00000010 -+/* No-Operation -+#define I2C_ICR_I2C_ERR_INT_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_ICR_I2C_ERR_INT_CLR 0x00000010 -+/** BREQ_INT */ -+#define I2C_ICR_BREQ_INT 0x00000008 -+/* No-Operation -+#define I2C_ICR_BREQ_INT_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_ICR_BREQ_INT_CLR 0x00000008 -+/** LBREQ_INT */ -+#define I2C_ICR_LBREQ_INT 0x00000004 -+/* No-Operation -+#define I2C_ICR_LBREQ_INT_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_ICR_LBREQ_INT_CLR 0x00000004 -+/** SREQ_INT */ -+#define I2C_ICR_SREQ_INT 0x00000002 -+/* No-Operation -+#define I2C_ICR_SREQ_INT_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_ICR_SREQ_INT_CLR 0x00000002 -+/** LSREQ_INT */ -+#define I2C_ICR_LSREQ_INT 0x00000001 -+/* No-Operation -+#define I2C_ICR_LSREQ_INT_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_ICR_LSREQ_INT_CLR 0x00000001 -+ -+/* Fields of "I2C Interrupt Set Register" */ -+/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */ -+#define I2C_ISR_I2C_P_INT 0x00000020 -+/* No-Operation -+#define I2C_ISR_I2C_P_INT_NOP 0x00000000 */ -+/** Set */ -+#define I2C_ISR_I2C_P_INT_SET 0x00000020 -+/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */ -+#define I2C_ISR_I2C_ERR_INT 0x00000010 -+/* No-Operation -+#define I2C_ISR_I2C_ERR_INT_NOP 0x00000000 */ -+/** Set */ -+#define I2C_ISR_I2C_ERR_INT_SET 0x00000010 -+/** BREQ_INT */ -+#define I2C_ISR_BREQ_INT 0x00000008 -+/* No-Operation -+#define I2C_ISR_BREQ_INT_NOP 0x00000000 */ -+/** Set */ -+#define I2C_ISR_BREQ_INT_SET 0x00000008 -+/** LBREQ_INT */ -+#define I2C_ISR_LBREQ_INT 0x00000004 -+/* No-Operation -+#define I2C_ISR_LBREQ_INT_NOP 0x00000000 */ -+/** Set */ -+#define I2C_ISR_LBREQ_INT_SET 0x00000004 -+/** SREQ_INT */ -+#define I2C_ISR_SREQ_INT 0x00000002 -+/* No-Operation -+#define I2C_ISR_SREQ_INT_NOP 0x00000000 */ -+/** Set */ -+#define I2C_ISR_SREQ_INT_SET 0x00000002 -+/** LSREQ_INT */ -+#define I2C_ISR_LSREQ_INT 0x00000001 -+/* No-Operation -+#define I2C_ISR_LSREQ_INT_NOP 0x00000000 */ -+/** Set */ -+#define I2C_ISR_LSREQ_INT_SET 0x00000001 -+ -+/* Fields of "I2C DMA Enable Register" */ -+/** BREQ_INT */ -+#define I2C_DMAE_BREQ_INT 0x00000008 -+/* Disable -+#define I2C_DMAE_BREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_DMAE_BREQ_INT_EN 0x00000008 -+/** LBREQ_INT */ -+#define I2C_DMAE_LBREQ_INT 0x00000004 -+/* Disable -+#define I2C_DMAE_LBREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_DMAE_LBREQ_INT_EN 0x00000004 -+/** SREQ_INT */ -+#define I2C_DMAE_SREQ_INT 0x00000002 -+/* Disable -+#define I2C_DMAE_SREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_DMAE_SREQ_INT_EN 0x00000002 -+/** LSREQ_INT */ -+#define I2C_DMAE_LSREQ_INT 0x00000001 -+/* Disable -+#define I2C_DMAE_LSREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_DMAE_LSREQ_INT_EN 0x00000001 -+ -+/* Fields of "I2C Transmit Data Register" */ -+/** Characters to be transmitted */ -+#define I2C_TXD_TXD_MASK 0xFFFFFFFF -+/** field offset */ -+#define I2C_TXD_TXD_OFFSET 0 -+ -+/* Fields of "I2C Receive Data Register" */ -+/** Received characters */ -+#define I2C_RXD_RXD_MASK 0xFFFFFFFF -+/** field offset */ -+#define I2C_RXD_RXD_OFFSET 0 -+ -+/*! @} */ /* I2C_REGISTER */ -+ -+#endif /* _i2c_reg_h */ ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/icu0_reg.h -@@ -0,0 +1,4324 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+ -+#ifndef _icu0_reg_h -+#define _icu0_reg_h -+ -+/** \addtogroup ICU0_REGISTER -+ @{ -+*/ -+/* access macros */ -+#define icu0_r32(reg) reg_r32(&icu0->reg) -+#define icu0_w32(val, reg) reg_w32(val, &icu0->reg) -+#define icu0_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &icu0->reg) -+#define icu0_r32_table(reg, idx) reg_r32_table(icu0->reg, idx) -+#define icu0_w32_table(val, reg, idx) reg_w32_table(val, icu0->reg, idx) -+#define icu0_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, icu0->reg, idx) -+#define icu0_adr_table(reg, idx) adr_table(icu0->reg, idx) -+ -+ -+/** ICU0 register structure */ -+struct gpon_reg_icu0 -+{ -+ /** IM0 Interrupt Status Register -+ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */ -+ unsigned int im0_isr; /* 0x00000000 */ -+ /** Reserved */ -+ unsigned int res_0; /* 0x00000004 */ -+ /** IM0 Interrupt Enable Register -+ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM0_IOSR register and are not signalled via the interrupt line towards the controller. */ -+ unsigned int im0_ier; /* 0x00000008 */ -+ /** Reserved */ -+ unsigned int res_1; /* 0x0000000C */ -+ /** IM0 Interrupt Output Status Register -+ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM0_IER register. */ -+ unsigned int im0_iosr; /* 0x00000010 */ -+ /** Reserved */ -+ unsigned int res_2; /* 0x00000014 */ -+ /** IM0 Interrupt Request Set Register -+ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ -+ unsigned int im0_irsr; /* 0x00000018 */ -+ /** Reserved */ -+ unsigned int res_3; /* 0x0000001C */ -+ /** IM0 Interrupt Mode Register -+ This register shows the type of interrupt for each bit. */ -+ unsigned int im0_imr; /* 0x00000020 */ -+ /** Reserved */ -+ unsigned int res_4; /* 0x00000024 */ -+ /** IM1 Interrupt Status Register -+ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */ -+ unsigned int im1_isr; /* 0x00000028 */ -+ /** Reserved */ -+ unsigned int res_5; /* 0x0000002C */ -+ /** IM1 Interrupt Enable Register -+ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM1_IOSR register and are not signalled via the interrupt line towards the controller. */ -+ unsigned int im1_ier; /* 0x00000030 */ -+ /** Reserved */ -+ unsigned int res_6; /* 0x00000034 */ -+ /** IM1 Interrupt Output Status Register -+ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM1_IER register. */ -+ unsigned int im1_iosr; /* 0x00000038 */ -+ /** Reserved */ -+ unsigned int res_7; /* 0x0000003C */ -+ /** IM1 Interrupt Request Set Register -+ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ -+ unsigned int im1_irsr; /* 0x00000040 */ -+ /** Reserved */ -+ unsigned int res_8; /* 0x00000044 */ -+ /** IM1 Interrupt Mode Register -+ This register shows the type of interrupt for each bit. */ -+ unsigned int im1_imr; /* 0x00000048 */ -+ /** Reserved */ -+ unsigned int res_9; /* 0x0000004C */ -+ /** IM2 Interrupt Status Register -+ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */ -+ unsigned int im2_isr; /* 0x00000050 */ -+ /** Reserved */ -+ unsigned int res_10; /* 0x00000054 */ -+ /** IM2 Interrupt Enable Register -+ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM2_IOSR register and are not signalled via the interrupt line towards the controller. */ -+ unsigned int im2_ier; /* 0x00000058 */ -+ /** Reserved */ -+ unsigned int res_11; /* 0x0000005C */ -+ /** IM2 Interrupt Output Status Register -+ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM2_IER register. */ -+ unsigned int im2_iosr; /* 0x00000060 */ -+ /** Reserved */ -+ unsigned int res_12; /* 0x00000064 */ -+ /** IM2 Interrupt Request Set Register -+ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ -+ unsigned int im2_irsr; /* 0x00000068 */ -+ /** Reserved */ -+ unsigned int res_13; /* 0x0000006C */ -+ /** IM2 Interrupt Mode Register -+ This register shows the type of interrupt for each bit. */ -+ unsigned int im2_imr; /* 0x00000070 */ -+ /** Reserved */ -+ unsigned int res_14; /* 0x00000074 */ -+ /** IM3 Interrupt Status Register -+ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */ -+ unsigned int im3_isr; /* 0x00000078 */ -+ /** Reserved */ -+ unsigned int res_15; /* 0x0000007C */ -+ /** IM3 Interrupt Enable Register -+ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM3_IOSR register and are not signalled via the interrupt line towards the controller. */ -+ unsigned int im3_ier; /* 0x00000080 */ -+ /** Reserved */ -+ unsigned int res_16; /* 0x00000084 */ -+ /** IM3 Interrupt Output Status Register -+ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM3_IER register. */ -+ unsigned int im3_iosr; /* 0x00000088 */ -+ /** Reserved */ -+ unsigned int res_17; /* 0x0000008C */ -+ /** IM3 Interrupt Request Set Register -+ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ -+ unsigned int im3_irsr; /* 0x00000090 */ -+ /** Reserved */ -+ unsigned int res_18; /* 0x00000094 */ -+ /** IM3 Interrupt Mode Register -+ This register shows the type of interrupt for each bit. */ -+ unsigned int im3_imr; /* 0x00000098 */ -+ /** Reserved */ -+ unsigned int res_19; /* 0x0000009C */ -+ /** IM4 Interrupt Status Register -+ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */ -+ unsigned int im4_isr; /* 0x000000A0 */ -+ /** Reserved */ -+ unsigned int res_20; /* 0x000000A4 */ -+ /** IM4 Interrupt Enable Register -+ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM4_IOSR register and are not signalled via the interrupt line towards the controller. */ -+ unsigned int im4_ier; /* 0x000000A8 */ -+ /** Reserved */ -+ unsigned int res_21; /* 0x000000AC */ -+ /** IM4 Interrupt Output Status Register -+ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM4_IER register. */ -+ unsigned int im4_iosr; /* 0x000000B0 */ -+ /** Reserved */ -+ unsigned int res_22; /* 0x000000B4 */ -+ /** IM4 Interrupt Request Set Register -+ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ -+ unsigned int im4_irsr; /* 0x000000B8 */ -+ /** Reserved */ -+ unsigned int res_23; /* 0x000000BC */ -+ /** IM4 Interrupt Mode Register -+ This register shows the type of interrupt for each bit. */ -+ unsigned int im4_imr; /* 0x000000C0 */ -+ /** Reserved */ -+ unsigned int res_24; /* 0x000000C4 */ -+ /** ICU Interrupt Vector Register (5 bit variant) -+ Shows the leftmost pending interrupt request. If e.g. bit 14 of the IOSR register is set, 15 is reported, because the 15th interrupt request is active. */ -+ unsigned int icu_ivec; /* 0x000000C8 */ -+ /** Reserved */ -+ unsigned int res_25; /* 0x000000CC */ -+ /** ICU Interrupt Vector Register (6 bit variant) -+ Shows the leftmost pending interrupt request. If e.g. bit 14 of the IOSR register is set, 15 is reported, because the 15th interrupt request is active. */ -+ unsigned int icu_ivec_6; /* 0x000000D0 */ -+ /** Reserved */ -+ unsigned int res_26[3]; /* 0x000000D4 */ -+}; -+ -+ -+/* Fields of "IM0 Interrupt Status Register" */ -+/** PCM Transmit Crash Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_PCM_HW2_CRASH 0x80000000 -+/* Nothing -+#define ICU0_IM0_ISR_PCM_HW2_CRASH_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_PCM_HW2_CRASH_INTACK 0x80000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_PCM_HW2_CRASH_INTOCC 0x80000000 -+/** PCM Transmit Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_PCM_TX 0x40000000 -+/* Nothing -+#define ICU0_IM0_ISR_PCM_TX_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_PCM_TX_INTACK 0x40000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_PCM_TX_INTOCC 0x40000000 -+/** PCM Receive Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_PCM_RX 0x20000000 -+/* Nothing -+#define ICU0_IM0_ISR_PCM_RX_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_PCM_RX_INTACK 0x20000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_PCM_RX_INTOCC 0x20000000 -+/** Secure Hash Algorithm Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM0_ISR_SHA1_HASH 0x10000000 -+/* Nothing -+#define ICU0_IM0_ISR_SHA1_HASH_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_SHA1_HASH_INTACK 0x10000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_SHA1_HASH_INTOCC 0x10000000 -+/** Advanced Encryption Standard Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM0_ISR_AES_AES 0x08000000 -+/* Nothing -+#define ICU0_IM0_ISR_AES_AES_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_AES_AES_INTACK 0x08000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_AES_AES_INTOCC 0x08000000 -+/** SSC Frame Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM0_ISR_SSC0_F 0x00020000 -+/* Nothing -+#define ICU0_IM0_ISR_SSC0_F_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_SSC0_F_INTACK 0x00020000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_SSC0_F_INTOCC 0x00020000 -+/** SSC Error Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM0_ISR_SSC0_E 0x00010000 -+/* Nothing -+#define ICU0_IM0_ISR_SSC0_E_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_SSC0_E_INTACK 0x00010000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_SSC0_E_INTOCC 0x00010000 -+/** SSC Receive Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM0_ISR_SSC0_R 0x00008000 -+/* Nothing -+#define ICU0_IM0_ISR_SSC0_R_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_SSC0_R_INTACK 0x00008000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_SSC0_R_INTOCC 0x00008000 -+/** SSC Transmit Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM0_ISR_SSC0_T 0x00004000 -+/* Nothing -+#define ICU0_IM0_ISR_SSC0_T_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_SSC0_T_INTACK 0x00004000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_SSC0_T_INTOCC 0x00004000 -+/** I2C Peripheral Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_I2C_I2C_P_INT 0x00002000 -+/* Nothing -+#define ICU0_IM0_ISR_I2C_I2C_P_INT_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_I2C_I2C_P_INT_INTACK 0x00002000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_I2C_I2C_P_INT_INTOCC 0x00002000 -+/** I2C Error Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_I2C_I2C_ERR_INT 0x00001000 -+/* Nothing -+#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_INTACK 0x00001000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_INTOCC 0x00001000 -+/** I2C Burst Data Transfer Request -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_I2C_BREQ_INT 0x00000800 -+/* Nothing -+#define ICU0_IM0_ISR_I2C_BREQ_INT_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_I2C_BREQ_INT_INTACK 0x00000800 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_I2C_BREQ_INT_INTOCC 0x00000800 -+/** I2C Last Burst Data Transfer Request -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_I2C_LBREQ_INT 0x00000400 -+/* Nothing -+#define ICU0_IM0_ISR_I2C_LBREQ_INT_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_I2C_LBREQ_INT_INTACK 0x00000400 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_I2C_LBREQ_INT_INTOCC 0x00000400 -+/** I2C Single Data Transfer Request -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_I2C_SREQ_INT 0x00000200 -+/* Nothing -+#define ICU0_IM0_ISR_I2C_SREQ_INT_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_I2C_SREQ_INT_INTACK 0x00000200 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_I2C_SREQ_INT_INTOCC 0x00000200 -+/** I2C Last Single Data Transfer Request -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_I2C_LSREQ_INT 0x00000100 -+/* Nothing -+#define ICU0_IM0_ISR_I2C_LSREQ_INT_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_I2C_LSREQ_INT_INTACK 0x00000100 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_I2C_LSREQ_INT_INTOCC 0x00000100 -+/** HOST IF Mailbox1 Transmit Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_HOST_MB1_TIR 0x00000010 -+/* Nothing -+#define ICU0_IM0_ISR_HOST_MB1_TIR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_HOST_MB1_TIR_INTACK 0x00000010 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_HOST_MB1_TIR_INTOCC 0x00000010 -+/** HOST IF Mailbox1 Receive Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_HOST_MB1_RIR 0x00000008 -+/* Nothing -+#define ICU0_IM0_ISR_HOST_MB1_RIR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_HOST_MB1_RIR_INTACK 0x00000008 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_HOST_MB1_RIR_INTOCC 0x00000008 -+/** HOST IF Mailbox0 Transmit Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_HOST_MB0_TIR 0x00000004 -+/* Nothing -+#define ICU0_IM0_ISR_HOST_MB0_TIR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_HOST_MB0_TIR_INTACK 0x00000004 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_HOST_MB0_TIR_INTOCC 0x00000004 -+/** HOST IF Mailbox0 Receive Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_HOST_MB0_RIR 0x00000002 -+/* Nothing -+#define ICU0_IM0_ISR_HOST_MB0_RIR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_HOST_MB0_RIR_INTACK 0x00000002 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_HOST_MB0_RIR_INTOCC 0x00000002 -+/** HOST IF Event Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_HOST_EIR 0x00000001 -+/* Nothing -+#define ICU0_IM0_ISR_HOST_EIR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_HOST_EIR_INTACK 0x00000001 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_HOST_EIR_INTOCC 0x00000001 -+ -+/* Fields of "IM0 Interrupt Enable Register" */ -+/** PCM Transmit Crash Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_PCM_HW2_CRASH 0x80000000 -+/* Disable -+#define ICU0_IM0_IER_PCM_HW2_CRASH_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_PCM_HW2_CRASH_EN 0x80000000 -+/** PCM Transmit Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_PCM_TX 0x40000000 -+/* Disable -+#define ICU0_IM0_IER_PCM_TX_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_PCM_TX_EN 0x40000000 -+/** PCM Receive Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_PCM_RX 0x20000000 -+/* Disable -+#define ICU0_IM0_IER_PCM_RX_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_PCM_RX_EN 0x20000000 -+/** Secure Hash Algorithm Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_SHA1_HASH 0x10000000 -+/* Disable -+#define ICU0_IM0_IER_SHA1_HASH_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_SHA1_HASH_EN 0x10000000 -+/** Advanced Encryption Standard Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_AES_AES 0x08000000 -+/* Disable -+#define ICU0_IM0_IER_AES_AES_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_AES_AES_EN 0x08000000 -+/** SSC Frame Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_SSC0_F 0x00020000 -+/* Disable -+#define ICU0_IM0_IER_SSC0_F_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_SSC0_F_EN 0x00020000 -+/** SSC Error Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_SSC0_E 0x00010000 -+/* Disable -+#define ICU0_IM0_IER_SSC0_E_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_SSC0_E_EN 0x00010000 -+/** SSC Receive Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_SSC0_R 0x00008000 -+/* Disable -+#define ICU0_IM0_IER_SSC0_R_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_SSC0_R_EN 0x00008000 -+/** SSC Transmit Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_SSC0_T 0x00004000 -+/* Disable -+#define ICU0_IM0_IER_SSC0_T_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_SSC0_T_EN 0x00004000 -+/** I2C Peripheral Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_I2C_I2C_P_INT 0x00002000 -+/* Disable -+#define ICU0_IM0_IER_I2C_I2C_P_INT_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_I2C_I2C_P_INT_EN 0x00002000 -+/** I2C Error Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_I2C_I2C_ERR_INT 0x00001000 -+/* Disable -+#define ICU0_IM0_IER_I2C_I2C_ERR_INT_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_I2C_I2C_ERR_INT_EN 0x00001000 -+/** I2C Burst Data Transfer Request -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_I2C_BREQ_INT 0x00000800 -+/* Disable -+#define ICU0_IM0_IER_I2C_BREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_I2C_BREQ_INT_EN 0x00000800 -+/** I2C Last Burst Data Transfer Request -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_I2C_LBREQ_INT 0x00000400 -+/* Disable -+#define ICU0_IM0_IER_I2C_LBREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_I2C_LBREQ_INT_EN 0x00000400 -+/** I2C Single Data Transfer Request -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_I2C_SREQ_INT 0x00000200 -+/* Disable -+#define ICU0_IM0_IER_I2C_SREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_I2C_SREQ_INT_EN 0x00000200 -+/** I2C Last Single Data Transfer Request -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_I2C_LSREQ_INT 0x00000100 -+/* Disable -+#define ICU0_IM0_IER_I2C_LSREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_I2C_LSREQ_INT_EN 0x00000100 -+/** HOST IF Mailbox1 Transmit Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_HOST_MB1_TIR 0x00000010 -+/* Disable -+#define ICU0_IM0_IER_HOST_MB1_TIR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_HOST_MB1_TIR_EN 0x00000010 -+/** HOST IF Mailbox1 Receive Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_HOST_MB1_RIR 0x00000008 -+/* Disable -+#define ICU0_IM0_IER_HOST_MB1_RIR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_HOST_MB1_RIR_EN 0x00000008 -+/** HOST IF Mailbox0 Transmit Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_HOST_MB0_TIR 0x00000004 -+/* Disable -+#define ICU0_IM0_IER_HOST_MB0_TIR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_HOST_MB0_TIR_EN 0x00000004 -+/** HOST IF Mailbox0 Receive Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_HOST_MB0_RIR 0x00000002 -+/* Disable -+#define ICU0_IM0_IER_HOST_MB0_RIR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_HOST_MB0_RIR_EN 0x00000002 -+/** HOST IF Event Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_HOST_EIR 0x00000001 -+/* Disable -+#define ICU0_IM0_IER_HOST_EIR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_HOST_EIR_EN 0x00000001 -+ -+/* Fields of "IM0 Interrupt Output Status Register" */ -+/** PCM Transmit Crash Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_PCM_HW2_CRASH 0x80000000 -+/* Nothing -+#define ICU0_IM0_IOSR_PCM_HW2_CRASH_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_PCM_HW2_CRASH_INTOCC 0x80000000 -+/** PCM Transmit Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_PCM_TX 0x40000000 -+/* Nothing -+#define ICU0_IM0_IOSR_PCM_TX_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_PCM_TX_INTOCC 0x40000000 -+/** PCM Receive Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_PCM_RX 0x20000000 -+/* Nothing -+#define ICU0_IM0_IOSR_PCM_RX_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_PCM_RX_INTOCC 0x20000000 -+/** Secure Hash Algorithm Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_SHA1_HASH 0x10000000 -+/* Nothing -+#define ICU0_IM0_IOSR_SHA1_HASH_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_SHA1_HASH_INTOCC 0x10000000 -+/** Advanced Encryption Standard Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_AES_AES 0x08000000 -+/* Nothing -+#define ICU0_IM0_IOSR_AES_AES_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_AES_AES_INTOCC 0x08000000 -+/** SSC Frame Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_SSC0_F 0x00020000 -+/* Nothing -+#define ICU0_IM0_IOSR_SSC0_F_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_SSC0_F_INTOCC 0x00020000 -+/** SSC Error Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_SSC0_E 0x00010000 -+/* Nothing -+#define ICU0_IM0_IOSR_SSC0_E_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_SSC0_E_INTOCC 0x00010000 -+/** SSC Receive Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_SSC0_R 0x00008000 -+/* Nothing -+#define ICU0_IM0_IOSR_SSC0_R_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_SSC0_R_INTOCC 0x00008000 -+/** SSC Transmit Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_SSC0_T 0x00004000 -+/* Nothing -+#define ICU0_IM0_IOSR_SSC0_T_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_SSC0_T_INTOCC 0x00004000 -+/** I2C Peripheral Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_I2C_I2C_P_INT 0x00002000 -+/* Nothing -+#define ICU0_IM0_IOSR_I2C_I2C_P_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_I2C_I2C_P_INT_INTOCC 0x00002000 -+/** I2C Error Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT 0x00001000 -+/* Nothing -+#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT_INTOCC 0x00001000 -+/** I2C Burst Data Transfer Request -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_I2C_BREQ_INT 0x00000800 -+/* Nothing -+#define ICU0_IM0_IOSR_I2C_BREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_I2C_BREQ_INT_INTOCC 0x00000800 -+/** I2C Last Burst Data Transfer Request -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_I2C_LBREQ_INT 0x00000400 -+/* Nothing -+#define ICU0_IM0_IOSR_I2C_LBREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_I2C_LBREQ_INT_INTOCC 0x00000400 -+/** I2C Single Data Transfer Request -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_I2C_SREQ_INT 0x00000200 -+/* Nothing -+#define ICU0_IM0_IOSR_I2C_SREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_I2C_SREQ_INT_INTOCC 0x00000200 -+/** I2C Last Single Data Transfer Request -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_I2C_LSREQ_INT 0x00000100 -+/* Nothing -+#define ICU0_IM0_IOSR_I2C_LSREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_I2C_LSREQ_INT_INTOCC 0x00000100 -+/** HOST IF Mailbox1 Transmit Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_HOST_MB1_TIR 0x00000010 -+/* Nothing -+#define ICU0_IM0_IOSR_HOST_MB1_TIR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_HOST_MB1_TIR_INTOCC 0x00000010 -+/** HOST IF Mailbox1 Receive Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_HOST_MB1_RIR 0x00000008 -+/* Nothing -+#define ICU0_IM0_IOSR_HOST_MB1_RIR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_HOST_MB1_RIR_INTOCC 0x00000008 -+/** HOST IF Mailbox0 Transmit Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_HOST_MB0_TIR 0x00000004 -+/* Nothing -+#define ICU0_IM0_IOSR_HOST_MB0_TIR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_HOST_MB0_TIR_INTOCC 0x00000004 -+/** HOST IF Mailbox0 Receive Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_HOST_MB0_RIR 0x00000002 -+/* Nothing -+#define ICU0_IM0_IOSR_HOST_MB0_RIR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_HOST_MB0_RIR_INTOCC 0x00000002 -+/** HOST IF Event Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_HOST_EIR 0x00000001 -+/* Nothing -+#define ICU0_IM0_IOSR_HOST_EIR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_HOST_EIR_INTOCC 0x00000001 -+ -+/* Fields of "IM0 Interrupt Request Set Register" */ -+/** PCM Transmit Crash Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_PCM_HW2_CRASH 0x80000000 -+/** PCM Transmit Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_PCM_TX 0x40000000 -+/** PCM Receive Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_PCM_RX 0x20000000 -+/** Secure Hash Algorithm Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_SHA1_HASH 0x10000000 -+/** Advanced Encryption Standard Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_AES_AES 0x08000000 -+/** SSC Frame Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_SSC0_F 0x00020000 -+/** SSC Error Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_SSC0_E 0x00010000 -+/** SSC Receive Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_SSC0_R 0x00008000 -+/** SSC Transmit Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_SSC0_T 0x00004000 -+/** I2C Peripheral Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_I2C_I2C_P_INT 0x00002000 -+/** I2C Error Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_I2C_I2C_ERR_INT 0x00001000 -+/** I2C Burst Data Transfer Request -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_I2C_BREQ_INT 0x00000800 -+/** I2C Last Burst Data Transfer Request -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_I2C_LBREQ_INT 0x00000400 -+/** I2C Single Data Transfer Request -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_I2C_SREQ_INT 0x00000200 -+/** I2C Last Single Data Transfer Request -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_I2C_LSREQ_INT 0x00000100 -+/** HOST IF Mailbox1 Transmit Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_HOST_MB1_TIR 0x00000010 -+/** HOST IF Mailbox1 Receive Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_HOST_MB1_RIR 0x00000008 -+/** HOST IF Mailbox0 Transmit Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_HOST_MB0_TIR 0x00000004 -+/** HOST IF Mailbox0 Receive Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_HOST_MB0_RIR 0x00000002 -+/** HOST IF Event Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_HOST_EIR 0x00000001 -+ -+/* Fields of "IM0 Interrupt Mode Register" */ -+/** PCM Transmit Crash Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_PCM_HW2_CRASH 0x80000000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_PCM_HW2_CRASH_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_PCM_HW2_CRASH_DIR 0x80000000 -+/** PCM Transmit Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_PCM_TX 0x40000000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_PCM_TX_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_PCM_TX_DIR 0x40000000 -+/** PCM Receive Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_PCM_RX 0x20000000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_PCM_RX_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_PCM_RX_DIR 0x20000000 -+/** Secure Hash Algorithm Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_SHA1_HASH 0x10000000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_SHA1_HASH_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_SHA1_HASH_DIR 0x10000000 -+/** Advanced Encryption Standard Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_AES_AES 0x08000000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_AES_AES_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_AES_AES_DIR 0x08000000 -+/** SSC Frame Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_SSC0_F 0x00020000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_SSC0_F_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_SSC0_F_DIR 0x00020000 -+/** SSC Error Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_SSC0_E 0x00010000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_SSC0_E_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_SSC0_E_DIR 0x00010000 -+/** SSC Receive Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_SSC0_R 0x00008000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_SSC0_R_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_SSC0_R_DIR 0x00008000 -+/** SSC Transmit Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_SSC0_T 0x00004000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_SSC0_T_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_SSC0_T_DIR 0x00004000 -+/** I2C Peripheral Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_I2C_I2C_P_INT 0x00002000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_I2C_I2C_P_INT_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_I2C_I2C_P_INT_DIR 0x00002000 -+/** I2C Error Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_I2C_I2C_ERR_INT 0x00001000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_I2C_I2C_ERR_INT_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_I2C_I2C_ERR_INT_DIR 0x00001000 -+/** I2C Burst Data Transfer Request -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_I2C_BREQ_INT 0x00000800 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_I2C_BREQ_INT_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_I2C_BREQ_INT_DIR 0x00000800 -+/** I2C Last Burst Data Transfer Request -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_I2C_LBREQ_INT 0x00000400 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_I2C_LBREQ_INT_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_I2C_LBREQ_INT_DIR 0x00000400 -+/** I2C Single Data Transfer Request -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_I2C_SREQ_INT 0x00000200 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_I2C_SREQ_INT_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_I2C_SREQ_INT_DIR 0x00000200 -+/** I2C Last Single Data Transfer Request -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_I2C_LSREQ_INT 0x00000100 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_I2C_LSREQ_INT_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_I2C_LSREQ_INT_DIR 0x00000100 -+/** HOST IF Mailbox1 Transmit Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_HOST_MB1_TIR 0x00000010 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_HOST_MB1_TIR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_HOST_MB1_TIR_DIR 0x00000010 -+/** HOST IF Mailbox1 Receive Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_HOST_MB1_RIR 0x00000008 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_HOST_MB1_RIR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_HOST_MB1_RIR_DIR 0x00000008 -+/** HOST IF Mailbox0 Transmit Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_HOST_MB0_TIR 0x00000004 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_HOST_MB0_TIR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_HOST_MB0_TIR_DIR 0x00000004 -+/** HOST IF Mailbox0 Receive Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_HOST_MB0_RIR 0x00000002 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_HOST_MB0_RIR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_HOST_MB0_RIR_DIR 0x00000002 -+/** HOST IF Event Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_HOST_EIR 0x00000001 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_HOST_EIR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_HOST_EIR_DIR 0x00000001 -+ -+/* Fields of "IM1 Interrupt Status Register" */ -+/** Crossbar Error Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_XBAR_ERROR 0x80000000 -+/* Nothing -+#define ICU0_IM1_ISR_XBAR_ERROR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_XBAR_ERROR_INTACK 0x80000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_XBAR_ERROR_INTOCC 0x80000000 -+/** DDR Controller Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_DDR 0x40000000 -+/* Nothing -+#define ICU0_IM1_ISR_DDR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_DDR_INTACK 0x40000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_DDR_INTOCC 0x40000000 -+/** FPI Bus Control Unit Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM1_ISR_BCU0 0x20000000 -+/* Nothing -+#define ICU0_IM1_ISR_BCU0_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_BCU0_INTACK 0x20000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_BCU0_INTOCC 0x20000000 -+/** SBIU interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_SBIU0 0x08000000 -+/* Nothing -+#define ICU0_IM1_ISR_SBIU0_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_SBIU0_INTACK 0x08000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_SBIU0_INTOCC 0x08000000 -+/** Watchdog Prewarning Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_WDT_PIR 0x02000000 -+/* Nothing -+#define ICU0_IM1_ISR_WDT_PIR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_WDT_PIR_INTACK 0x02000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_WDT_PIR_INTOCC 0x02000000 -+/** Watchdog Access Error Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_WDT_AEIR 0x01000000 -+/* Nothing -+#define ICU0_IM1_ISR_WDT_AEIR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_WDT_AEIR_INTACK 0x01000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_WDT_AEIR_INTOCC 0x01000000 -+/** SYS GPE Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_SYS_GPE 0x00200000 -+/* Nothing -+#define ICU0_IM1_ISR_SYS_GPE_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_SYS_GPE_INTACK 0x00200000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_SYS_GPE_INTOCC 0x00200000 -+/** SYS1 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_SYS1 0x00100000 -+/* Nothing -+#define ICU0_IM1_ISR_SYS1_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_SYS1_INTACK 0x00100000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_SYS1_INTOCC 0x00100000 -+/** PMA Interrupt from IntNode of the RX Clk Domain -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_PMA_RX 0x00020000 -+/* Nothing -+#define ICU0_IM1_ISR_PMA_RX_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_PMA_RX_INTACK 0x00020000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_PMA_RX_INTOCC 0x00020000 -+/** PMA Interrupt from IntNode of the TX Clk Domain -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_PMA_TX 0x00010000 -+/* Nothing -+#define ICU0_IM1_ISR_PMA_TX_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_PMA_TX_INTACK 0x00010000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_PMA_TX_INTOCC 0x00010000 -+/** PMA Interrupt from IntNode of the 200MHz Domain -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_PMA_200M 0x00008000 -+/* Nothing -+#define ICU0_IM1_ISR_PMA_200M_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_PMA_200M_INTACK 0x00008000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_PMA_200M_INTOCC 0x00008000 -+/** Time of Day -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_TOD 0x00004000 -+/* Nothing -+#define ICU0_IM1_ISR_TOD_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_TOD_INTACK 0x00004000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_TOD_INTOCC 0x00004000 -+/** 8kHz root interrupt derived from GPON interface -+ This bit is a direct interrupt. */ -+#define ICU0_IM1_ISR_FSC_ROOT 0x00002000 -+/* Nothing -+#define ICU0_IM1_ISR_FSC_ROOT_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_FSC_ROOT_INTACK 0x00002000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_FSC_ROOT_INTOCC 0x00002000 -+/** FSC Timer Interrupt 1 -+ Delayed version of FSCROOT. This bit is a direct interrupt. */ -+#define ICU0_IM1_ISR_FSCT_CMP1 0x00001000 -+/* Nothing -+#define ICU0_IM1_ISR_FSCT_CMP1_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_FSCT_CMP1_INTACK 0x00001000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_FSCT_CMP1_INTOCC 0x00001000 -+/** FSC Timer Interrupt 0 -+ Delayed version of FSCROOT. This bit is a direct interrupt. */ -+#define ICU0_IM1_ISR_FSCT_CMP0 0x00000800 -+/* Nothing -+#define ICU0_IM1_ISR_FSCT_CMP0_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_FSCT_CMP0_INTACK 0x00000800 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_FSCT_CMP0_INTOCC 0x00000800 -+/** 8kHz backup interrupt derived from core-PLL -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_FSC_BKP 0x00000400 -+/* Nothing -+#define ICU0_IM1_ISR_FSC_BKP_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_FSC_BKP_INTACK 0x00000400 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_FSC_BKP_INTOCC 0x00000400 -+/** External Interrupt from GPIO P4 -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_P4 0x00000100 -+/* Nothing -+#define ICU0_IM1_ISR_P4_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_P4_INTACK 0x00000100 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_P4_INTOCC 0x00000100 -+/** External Interrupt from GPIO P3 -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_P3 0x00000080 -+/* Nothing -+#define ICU0_IM1_ISR_P3_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_P3_INTACK 0x00000080 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_P3_INTOCC 0x00000080 -+/** External Interrupt from GPIO P2 -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_P2 0x00000040 -+/* Nothing -+#define ICU0_IM1_ISR_P2_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_P2_INTACK 0x00000040 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_P2_INTOCC 0x00000040 -+/** External Interrupt from GPIO P1 -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_P1 0x00000020 -+/* Nothing -+#define ICU0_IM1_ISR_P1_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_P1_INTACK 0x00000020 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_P1_INTOCC 0x00000020 -+/** External Interrupt from GPIO P0 -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_P0 0x00000010 -+/* Nothing -+#define ICU0_IM1_ISR_P0_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_P0_INTACK 0x00000010 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_P0_INTOCC 0x00000010 -+/** EBU Serial Flash Busy -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_EBU_SF_BUSY 0x00000004 -+/* Nothing -+#define ICU0_IM1_ISR_EBU_SF_BUSY_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_EBU_SF_BUSY_INTACK 0x00000004 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_EBU_SF_BUSY_INTOCC 0x00000004 -+/** EBU Serial Flash Command Overwrite Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_EBU_SF_COVERR 0x00000002 -+/* Nothing -+#define ICU0_IM1_ISR_EBU_SF_COVERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_EBU_SF_COVERR_INTACK 0x00000002 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_EBU_SF_COVERR_INTOCC 0x00000002 -+/** EBU Serial Flash Command Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_EBU_SF_CMDERR 0x00000001 -+/* Nothing -+#define ICU0_IM1_ISR_EBU_SF_CMDERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_EBU_SF_CMDERR_INTACK 0x00000001 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_EBU_SF_CMDERR_INTOCC 0x00000001 -+ -+/* Fields of "IM1 Interrupt Enable Register" */ -+/** Crossbar Error Interrupt -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_XBAR_ERROR 0x80000000 -+/* Disable -+#define ICU0_IM1_IER_XBAR_ERROR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_XBAR_ERROR_EN 0x80000000 -+/** DDR Controller Interrupt -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_DDR 0x40000000 -+/* Disable -+#define ICU0_IM1_IER_DDR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_DDR_EN 0x40000000 -+/** FPI Bus Control Unit Interrupt -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_BCU0 0x20000000 -+/* Disable -+#define ICU0_IM1_IER_BCU0_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_BCU0_EN 0x20000000 -+/** SBIU interrupt -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_SBIU0 0x08000000 -+/* Disable -+#define ICU0_IM1_IER_SBIU0_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_SBIU0_EN 0x08000000 -+/** Watchdog Prewarning Interrupt -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_WDT_PIR 0x02000000 -+/* Disable -+#define ICU0_IM1_IER_WDT_PIR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_WDT_PIR_EN 0x02000000 -+/** Watchdog Access Error Interrupt -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_WDT_AEIR 0x01000000 -+/* Disable -+#define ICU0_IM1_IER_WDT_AEIR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_WDT_AEIR_EN 0x01000000 -+/** SYS GPE Interrupt -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_SYS_GPE 0x00200000 -+/* Disable -+#define ICU0_IM1_IER_SYS_GPE_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_SYS_GPE_EN 0x00200000 -+/** SYS1 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_SYS1 0x00100000 -+/* Disable -+#define ICU0_IM1_IER_SYS1_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_SYS1_EN 0x00100000 -+/** PMA Interrupt from IntNode of the RX Clk Domain -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_PMA_RX 0x00020000 -+/* Disable -+#define ICU0_IM1_IER_PMA_RX_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_PMA_RX_EN 0x00020000 -+/** PMA Interrupt from IntNode of the TX Clk Domain -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_PMA_TX 0x00010000 -+/* Disable -+#define ICU0_IM1_IER_PMA_TX_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_PMA_TX_EN 0x00010000 -+/** PMA Interrupt from IntNode of the 200MHz Domain -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_PMA_200M 0x00008000 -+/* Disable -+#define ICU0_IM1_IER_PMA_200M_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_PMA_200M_EN 0x00008000 -+/** Time of Day -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_TOD 0x00004000 -+/* Disable -+#define ICU0_IM1_IER_TOD_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_TOD_EN 0x00004000 -+/** 8kHz root interrupt derived from GPON interface -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_FSC_ROOT 0x00002000 -+/* Disable -+#define ICU0_IM1_IER_FSC_ROOT_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_FSC_ROOT_EN 0x00002000 -+/** FSC Timer Interrupt 1 -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_FSCT_CMP1 0x00001000 -+/* Disable -+#define ICU0_IM1_IER_FSCT_CMP1_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_FSCT_CMP1_EN 0x00001000 -+/** FSC Timer Interrupt 0 -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_FSCT_CMP0 0x00000800 -+/* Disable -+#define ICU0_IM1_IER_FSCT_CMP0_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_FSCT_CMP0_EN 0x00000800 -+/** 8kHz backup interrupt derived from core-PLL -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_FSC_BKP 0x00000400 -+/* Disable -+#define ICU0_IM1_IER_FSC_BKP_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_FSC_BKP_EN 0x00000400 -+/** External Interrupt from GPIO P4 -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_P4 0x00000100 -+/* Disable -+#define ICU0_IM1_IER_P4_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_P4_EN 0x00000100 -+/** External Interrupt from GPIO P3 -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_P3 0x00000080 -+/* Disable -+#define ICU0_IM1_IER_P3_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_P3_EN 0x00000080 -+/** External Interrupt from GPIO P2 -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_P2 0x00000040 -+/* Disable -+#define ICU0_IM1_IER_P2_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_P2_EN 0x00000040 -+/** External Interrupt from GPIO P1 -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_P1 0x00000020 -+/* Disable -+#define ICU0_IM1_IER_P1_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_P1_EN 0x00000020 -+/** External Interrupt from GPIO P0 -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_P0 0x00000010 -+/* Disable -+#define ICU0_IM1_IER_P0_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_P0_EN 0x00000010 -+/** EBU Serial Flash Busy -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_EBU_SF_BUSY 0x00000004 -+/* Disable -+#define ICU0_IM1_IER_EBU_SF_BUSY_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_EBU_SF_BUSY_EN 0x00000004 -+/** EBU Serial Flash Command Overwrite Error -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_EBU_SF_COVERR 0x00000002 -+/* Disable -+#define ICU0_IM1_IER_EBU_SF_COVERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_EBU_SF_COVERR_EN 0x00000002 -+/** EBU Serial Flash Command Error -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_EBU_SF_CMDERR 0x00000001 -+/* Disable -+#define ICU0_IM1_IER_EBU_SF_CMDERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_EBU_SF_CMDERR_EN 0x00000001 -+ -+/* Fields of "IM1 Interrupt Output Status Register" */ -+/** Crossbar Error Interrupt -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_XBAR_ERROR 0x80000000 -+/* Nothing -+#define ICU0_IM1_IOSR_XBAR_ERROR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_XBAR_ERROR_INTOCC 0x80000000 -+/** DDR Controller Interrupt -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_DDR 0x40000000 -+/* Nothing -+#define ICU0_IM1_IOSR_DDR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_DDR_INTOCC 0x40000000 -+/** FPI Bus Control Unit Interrupt -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_BCU0 0x20000000 -+/* Nothing -+#define ICU0_IM1_IOSR_BCU0_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_BCU0_INTOCC 0x20000000 -+/** SBIU interrupt -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_SBIU0 0x08000000 -+/* Nothing -+#define ICU0_IM1_IOSR_SBIU0_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_SBIU0_INTOCC 0x08000000 -+/** Watchdog Prewarning Interrupt -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_WDT_PIR 0x02000000 -+/* Nothing -+#define ICU0_IM1_IOSR_WDT_PIR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_WDT_PIR_INTOCC 0x02000000 -+/** Watchdog Access Error Interrupt -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_WDT_AEIR 0x01000000 -+/* Nothing -+#define ICU0_IM1_IOSR_WDT_AEIR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_WDT_AEIR_INTOCC 0x01000000 -+/** SYS GPE Interrupt -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_SYS_GPE 0x00200000 -+/* Nothing -+#define ICU0_IM1_IOSR_SYS_GPE_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_SYS_GPE_INTOCC 0x00200000 -+/** SYS1 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_SYS1 0x00100000 -+/* Nothing -+#define ICU0_IM1_IOSR_SYS1_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_SYS1_INTOCC 0x00100000 -+/** PMA Interrupt from IntNode of the RX Clk Domain -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_PMA_RX 0x00020000 -+/* Nothing -+#define ICU0_IM1_IOSR_PMA_RX_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_PMA_RX_INTOCC 0x00020000 -+/** PMA Interrupt from IntNode of the TX Clk Domain -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_PMA_TX 0x00010000 -+/* Nothing -+#define ICU0_IM1_IOSR_PMA_TX_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_PMA_TX_INTOCC 0x00010000 -+/** PMA Interrupt from IntNode of the 200MHz Domain -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_PMA_200M 0x00008000 -+/* Nothing -+#define ICU0_IM1_IOSR_PMA_200M_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_PMA_200M_INTOCC 0x00008000 -+/** Time of Day -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_TOD 0x00004000 -+/* Nothing -+#define ICU0_IM1_IOSR_TOD_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_TOD_INTOCC 0x00004000 -+/** 8kHz root interrupt derived from GPON interface -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_FSC_ROOT 0x00002000 -+/* Nothing -+#define ICU0_IM1_IOSR_FSC_ROOT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_FSC_ROOT_INTOCC 0x00002000 -+/** FSC Timer Interrupt 1 -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_FSCT_CMP1 0x00001000 -+/* Nothing -+#define ICU0_IM1_IOSR_FSCT_CMP1_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_FSCT_CMP1_INTOCC 0x00001000 -+/** FSC Timer Interrupt 0 -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_FSCT_CMP0 0x00000800 -+/* Nothing -+#define ICU0_IM1_IOSR_FSCT_CMP0_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_FSCT_CMP0_INTOCC 0x00000800 -+/** 8kHz backup interrupt derived from core-PLL -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_FSC_BKP 0x00000400 -+/* Nothing -+#define ICU0_IM1_IOSR_FSC_BKP_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_FSC_BKP_INTOCC 0x00000400 -+/** External Interrupt from GPIO P4 -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_P4 0x00000100 -+/* Nothing -+#define ICU0_IM1_IOSR_P4_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_P4_INTOCC 0x00000100 -+/** External Interrupt from GPIO P3 -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_P3 0x00000080 -+/* Nothing -+#define ICU0_IM1_IOSR_P3_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_P3_INTOCC 0x00000080 -+/** External Interrupt from GPIO P2 -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_P2 0x00000040 -+/* Nothing -+#define ICU0_IM1_IOSR_P2_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_P2_INTOCC 0x00000040 -+/** External Interrupt from GPIO P1 -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_P1 0x00000020 -+/* Nothing -+#define ICU0_IM1_IOSR_P1_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_P1_INTOCC 0x00000020 -+/** External Interrupt from GPIO P0 -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_P0 0x00000010 -+/* Nothing -+#define ICU0_IM1_IOSR_P0_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_P0_INTOCC 0x00000010 -+/** EBU Serial Flash Busy -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_EBU_SF_BUSY 0x00000004 -+/* Nothing -+#define ICU0_IM1_IOSR_EBU_SF_BUSY_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_EBU_SF_BUSY_INTOCC 0x00000004 -+/** EBU Serial Flash Command Overwrite Error -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_EBU_SF_COVERR 0x00000002 -+/* Nothing -+#define ICU0_IM1_IOSR_EBU_SF_COVERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_EBU_SF_COVERR_INTOCC 0x00000002 -+/** EBU Serial Flash Command Error -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_EBU_SF_CMDERR 0x00000001 -+/* Nothing -+#define ICU0_IM1_IOSR_EBU_SF_CMDERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_EBU_SF_CMDERR_INTOCC 0x00000001 -+ -+/* Fields of "IM1 Interrupt Request Set Register" */ -+/** Crossbar Error Interrupt -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_XBAR_ERROR 0x80000000 -+/** DDR Controller Interrupt -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_DDR 0x40000000 -+/** FPI Bus Control Unit Interrupt -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_BCU0 0x20000000 -+/** SBIU interrupt -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_SBIU0 0x08000000 -+/** Watchdog Prewarning Interrupt -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_WDT_PIR 0x02000000 -+/** Watchdog Access Error Interrupt -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_WDT_AEIR 0x01000000 -+/** SYS GPE Interrupt -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_SYS_GPE 0x00200000 -+/** SYS1 Interrupt -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_SYS1 0x00100000 -+/** PMA Interrupt from IntNode of the RX Clk Domain -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_PMA_RX 0x00020000 -+/** PMA Interrupt from IntNode of the TX Clk Domain -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_PMA_TX 0x00010000 -+/** PMA Interrupt from IntNode of the 200MHz Domain -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_PMA_200M 0x00008000 -+/** Time of Day -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_TOD 0x00004000 -+/** 8kHz root interrupt derived from GPON interface -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_FSC_ROOT 0x00002000 -+/** FSC Timer Interrupt 1 -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_FSCT_CMP1 0x00001000 -+/** FSC Timer Interrupt 0 -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_FSCT_CMP0 0x00000800 -+/** 8kHz backup interrupt derived from core-PLL -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_FSC_BKP 0x00000400 -+/** External Interrupt from GPIO P4 -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_P4 0x00000100 -+/** External Interrupt from GPIO P3 -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_P3 0x00000080 -+/** External Interrupt from GPIO P2 -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_P2 0x00000040 -+/** External Interrupt from GPIO P1 -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_P1 0x00000020 -+/** External Interrupt from GPIO P0 -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_P0 0x00000010 -+/** EBU Serial Flash Busy -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_EBU_SF_BUSY 0x00000004 -+/** EBU Serial Flash Command Overwrite Error -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_EBU_SF_COVERR 0x00000002 -+/** EBU Serial Flash Command Error -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_EBU_SF_CMDERR 0x00000001 -+ -+/* Fields of "IM1 Interrupt Mode Register" */ -+/** Crossbar Error Interrupt -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_XBAR_ERROR 0x80000000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_XBAR_ERROR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_XBAR_ERROR_DIR 0x80000000 -+/** DDR Controller Interrupt -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_DDR 0x40000000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_DDR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_DDR_DIR 0x40000000 -+/** FPI Bus Control Unit Interrupt -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_BCU0 0x20000000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_BCU0_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_BCU0_DIR 0x20000000 -+/** SBIU interrupt -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_SBIU0 0x08000000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_SBIU0_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_SBIU0_DIR 0x08000000 -+/** Watchdog Prewarning Interrupt -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_WDT_PIR 0x02000000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_WDT_PIR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_WDT_PIR_DIR 0x02000000 -+/** Watchdog Access Error Interrupt -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_WDT_AEIR 0x01000000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_WDT_AEIR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_WDT_AEIR_DIR 0x01000000 -+/** SYS GPE Interrupt -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_SYS_GPE 0x00200000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_SYS_GPE_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_SYS_GPE_DIR 0x00200000 -+/** SYS1 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_SYS1 0x00100000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_SYS1_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_SYS1_DIR 0x00100000 -+/** PMA Interrupt from IntNode of the RX Clk Domain -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_PMA_RX 0x00020000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_PMA_RX_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_PMA_RX_DIR 0x00020000 -+/** PMA Interrupt from IntNode of the TX Clk Domain -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_PMA_TX 0x00010000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_PMA_TX_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_PMA_TX_DIR 0x00010000 -+/** PMA Interrupt from IntNode of the 200MHz Domain -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_PMA_200M 0x00008000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_PMA_200M_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_PMA_200M_DIR 0x00008000 -+/** Time of Day -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_TOD 0x00004000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_TOD_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_TOD_DIR 0x00004000 -+/** 8kHz root interrupt derived from GPON interface -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_FSC_ROOT 0x00002000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_FSC_ROOT_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_FSC_ROOT_DIR 0x00002000 -+/** FSC Timer Interrupt 1 -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_FSCT_CMP1 0x00001000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_FSCT_CMP1_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_FSCT_CMP1_DIR 0x00001000 -+/** FSC Timer Interrupt 0 -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_FSCT_CMP0 0x00000800 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_FSCT_CMP0_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_FSCT_CMP0_DIR 0x00000800 -+/** 8kHz backup interrupt derived from core-PLL -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_FSC_BKP 0x00000400 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_FSC_BKP_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_FSC_BKP_DIR 0x00000400 -+/** External Interrupt from GPIO P4 -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_P4 0x00000100 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_P4_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_P4_DIR 0x00000100 -+/** External Interrupt from GPIO P3 -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_P3 0x00000080 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_P3_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_P3_DIR 0x00000080 -+/** External Interrupt from GPIO P2 -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_P2 0x00000040 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_P2_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_P2_DIR 0x00000040 -+/** External Interrupt from GPIO P1 -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_P1 0x00000020 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_P1_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_P1_DIR 0x00000020 -+/** External Interrupt from GPIO P0 -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_P0 0x00000010 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_P0_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_P0_DIR 0x00000010 -+/** EBU Serial Flash Busy -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_EBU_SF_BUSY 0x00000004 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_EBU_SF_BUSY_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_EBU_SF_BUSY_DIR 0x00000004 -+/** EBU Serial Flash Command Overwrite Error -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_EBU_SF_COVERR 0x00000002 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_EBU_SF_COVERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_EBU_SF_COVERR_DIR 0x00000002 -+/** EBU Serial Flash Command Error -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_EBU_SF_CMDERR 0x00000001 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_EBU_SF_CMDERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_EBU_SF_CMDERR_DIR 0x00000001 -+ -+/* Fields of "IM2 Interrupt Status Register" */ -+/** EIM Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_EIM 0x80000000 -+/* Nothing -+#define ICU0_IM2_ISR_EIM_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_EIM_INTACK 0x80000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_EIM_INTOCC 0x80000000 -+/** GTC Upstream Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_GTC_US 0x40000000 -+/* Nothing -+#define ICU0_IM2_ISR_GTC_US_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_GTC_US_INTACK 0x40000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_GTC_US_INTOCC 0x40000000 -+/** GTC Downstream Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_GTC_DS 0x20000000 -+/* Nothing -+#define ICU0_IM2_ISR_GTC_DS_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_GTC_DS_INTACK 0x20000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_GTC_DS_INTOCC 0x20000000 -+/** TBM Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_TBM 0x00400000 -+/* Nothing -+#define ICU0_IM2_ISR_TBM_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_TBM_INTACK 0x00400000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_TBM_INTOCC 0x00400000 -+/** Dispatcher Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_DISP 0x00200000 -+/* Nothing -+#define ICU0_IM2_ISR_DISP_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_DISP_INTACK 0x00200000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_DISP_INTOCC 0x00200000 -+/** CONFIG Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_CONFIG 0x00100000 -+/* Nothing -+#define ICU0_IM2_ISR_CONFIG_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_CONFIG_INTACK 0x00100000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_CONFIG_INTOCC 0x00100000 -+/** CONFIG Break Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_CONFIG_BREAK 0x00080000 -+/* Nothing -+#define ICU0_IM2_ISR_CONFIG_BREAK_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_CONFIG_BREAK_INTACK 0x00080000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_CONFIG_BREAK_INTOCC 0x00080000 -+/** OCTRLC Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_OCTRLC 0x00040000 -+/* Nothing -+#define ICU0_IM2_ISR_OCTRLC_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_OCTRLC_INTACK 0x00040000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_OCTRLC_INTOCC 0x00040000 -+/** ICTRLC 1 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_ICTRLC1 0x00020000 -+/* Nothing -+#define ICU0_IM2_ISR_ICTRLC1_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_ICTRLC1_INTACK 0x00020000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_ICTRLC1_INTOCC 0x00020000 -+/** ICTRLC 0 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_ICTRLC0 0x00010000 -+/* Nothing -+#define ICU0_IM2_ISR_ICTRLC0_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_ICTRLC0_INTACK 0x00010000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_ICTRLC0_INTOCC 0x00010000 -+/** LINK 1 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_LINK1 0x00004000 -+/* Nothing -+#define ICU0_IM2_ISR_LINK1_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_LINK1_INTACK 0x00004000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_LINK1_INTOCC 0x00004000 -+/** TMU Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_TMU 0x00001000 -+/* Nothing -+#define ICU0_IM2_ISR_TMU_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_TMU_INTACK 0x00001000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_TMU_INTOCC 0x00001000 -+/** FSQM Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_FSQM 0x00000800 -+/* Nothing -+#define ICU0_IM2_ISR_FSQM_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_FSQM_INTACK 0x00000800 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_FSQM_INTOCC 0x00000800 -+/** IQM Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_IQM 0x00000400 -+/* Nothing -+#define ICU0_IM2_ISR_IQM_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_IQM_INTACK 0x00000400 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_IQM_INTOCC 0x00000400 -+/** OCTRLG Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_OCTRLG 0x00000200 -+/* Nothing -+#define ICU0_IM2_ISR_OCTRLG_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_OCTRLG_INTACK 0x00000200 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_OCTRLG_INTOCC 0x00000200 -+/** OCTRLL 3 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_OCTRLL3 0x00000080 -+/* Nothing -+#define ICU0_IM2_ISR_OCTRLL3_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_OCTRLL3_INTACK 0x00000080 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_OCTRLL3_INTOCC 0x00000080 -+/** OCTRLL 2 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_OCTRLL2 0x00000040 -+/* Nothing -+#define ICU0_IM2_ISR_OCTRLL2_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_OCTRLL2_INTACK 0x00000040 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_OCTRLL2_INTOCC 0x00000040 -+/** OCTRLL 1 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_OCTRLL1 0x00000020 -+/* Nothing -+#define ICU0_IM2_ISR_OCTRLL1_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_OCTRLL1_INTACK 0x00000020 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_OCTRLL1_INTOCC 0x00000020 -+/** OCTRLL 0 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_OCTRLL0 0x00000010 -+/* Nothing -+#define ICU0_IM2_ISR_OCTRLL0_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_OCTRLL0_INTACK 0x00000010 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_OCTRLL0_INTOCC 0x00000010 -+/** ICTRLL 3 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_ICTRLL3 0x00000008 -+/* Nothing -+#define ICU0_IM2_ISR_ICTRLL3_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_ICTRLL3_INTACK 0x00000008 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_ICTRLL3_INTOCC 0x00000008 -+/** ICTRLL 2 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_ICTRLL2 0x00000004 -+/* Nothing -+#define ICU0_IM2_ISR_ICTRLL2_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_ICTRLL2_INTACK 0x00000004 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_ICTRLL2_INTOCC 0x00000004 -+/** ICTRLL 1 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_ICTRLL1 0x00000002 -+/* Nothing -+#define ICU0_IM2_ISR_ICTRLL1_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_ICTRLL1_INTACK 0x00000002 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_ICTRLL1_INTOCC 0x00000002 -+/** ICTRLL 0 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_ICTRLL0 0x00000001 -+/* Nothing -+#define ICU0_IM2_ISR_ICTRLL0_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_ICTRLL0_INTACK 0x00000001 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_ICTRLL0_INTOCC 0x00000001 -+ -+/* Fields of "IM2 Interrupt Enable Register" */ -+/** EIM Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_EIM 0x80000000 -+/* Disable -+#define ICU0_IM2_IER_EIM_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_EIM_EN 0x80000000 -+/** GTC Upstream Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_GTC_US 0x40000000 -+/* Disable -+#define ICU0_IM2_IER_GTC_US_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_GTC_US_EN 0x40000000 -+/** GTC Downstream Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_GTC_DS 0x20000000 -+/* Disable -+#define ICU0_IM2_IER_GTC_DS_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_GTC_DS_EN 0x20000000 -+/** TBM Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_TBM 0x00400000 -+/* Disable -+#define ICU0_IM2_IER_TBM_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_TBM_EN 0x00400000 -+/** Dispatcher Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_DISP 0x00200000 -+/* Disable -+#define ICU0_IM2_IER_DISP_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_DISP_EN 0x00200000 -+/** CONFIG Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_CONFIG 0x00100000 -+/* Disable -+#define ICU0_IM2_IER_CONFIG_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_CONFIG_EN 0x00100000 -+/** CONFIG Break Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_CONFIG_BREAK 0x00080000 -+/* Disable -+#define ICU0_IM2_IER_CONFIG_BREAK_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_CONFIG_BREAK_EN 0x00080000 -+/** OCTRLC Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_OCTRLC 0x00040000 -+/* Disable -+#define ICU0_IM2_IER_OCTRLC_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_OCTRLC_EN 0x00040000 -+/** ICTRLC 1 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_ICTRLC1 0x00020000 -+/* Disable -+#define ICU0_IM2_IER_ICTRLC1_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_ICTRLC1_EN 0x00020000 -+/** ICTRLC 0 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_ICTRLC0 0x00010000 -+/* Disable -+#define ICU0_IM2_IER_ICTRLC0_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_ICTRLC0_EN 0x00010000 -+/** LINK 1 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_LINK1 0x00004000 -+/* Disable -+#define ICU0_IM2_IER_LINK1_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_LINK1_EN 0x00004000 -+/** TMU Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_TMU 0x00001000 -+/* Disable -+#define ICU0_IM2_IER_TMU_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_TMU_EN 0x00001000 -+/** FSQM Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_FSQM 0x00000800 -+/* Disable -+#define ICU0_IM2_IER_FSQM_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_FSQM_EN 0x00000800 -+/** IQM Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_IQM 0x00000400 -+/* Disable -+#define ICU0_IM2_IER_IQM_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_IQM_EN 0x00000400 -+/** OCTRLG Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_OCTRLG 0x00000200 -+/* Disable -+#define ICU0_IM2_IER_OCTRLG_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_OCTRLG_EN 0x00000200 -+/** OCTRLL 3 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_OCTRLL3 0x00000080 -+/* Disable -+#define ICU0_IM2_IER_OCTRLL3_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_OCTRLL3_EN 0x00000080 -+/** OCTRLL 2 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_OCTRLL2 0x00000040 -+/* Disable -+#define ICU0_IM2_IER_OCTRLL2_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_OCTRLL2_EN 0x00000040 -+/** OCTRLL 1 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_OCTRLL1 0x00000020 -+/* Disable -+#define ICU0_IM2_IER_OCTRLL1_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_OCTRLL1_EN 0x00000020 -+/** OCTRLL 0 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_OCTRLL0 0x00000010 -+/* Disable -+#define ICU0_IM2_IER_OCTRLL0_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_OCTRLL0_EN 0x00000010 -+/** ICTRLL 3 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_ICTRLL3 0x00000008 -+/* Disable -+#define ICU0_IM2_IER_ICTRLL3_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_ICTRLL3_EN 0x00000008 -+/** ICTRLL 2 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_ICTRLL2 0x00000004 -+/* Disable -+#define ICU0_IM2_IER_ICTRLL2_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_ICTRLL2_EN 0x00000004 -+/** ICTRLL 1 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_ICTRLL1 0x00000002 -+/* Disable -+#define ICU0_IM2_IER_ICTRLL1_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_ICTRLL1_EN 0x00000002 -+/** ICTRLL 0 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_ICTRLL0 0x00000001 -+/* Disable -+#define ICU0_IM2_IER_ICTRLL0_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_ICTRLL0_EN 0x00000001 -+ -+/* Fields of "IM2 Interrupt Output Status Register" */ -+/** EIM Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_EIM 0x80000000 -+/* Nothing -+#define ICU0_IM2_IOSR_EIM_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_EIM_INTOCC 0x80000000 -+/** GTC Upstream Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_GTC_US 0x40000000 -+/* Nothing -+#define ICU0_IM2_IOSR_GTC_US_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_GTC_US_INTOCC 0x40000000 -+/** GTC Downstream Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_GTC_DS 0x20000000 -+/* Nothing -+#define ICU0_IM2_IOSR_GTC_DS_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_GTC_DS_INTOCC 0x20000000 -+/** TBM Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_TBM 0x00400000 -+/* Nothing -+#define ICU0_IM2_IOSR_TBM_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_TBM_INTOCC 0x00400000 -+/** Dispatcher Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_DISP 0x00200000 -+/* Nothing -+#define ICU0_IM2_IOSR_DISP_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_DISP_INTOCC 0x00200000 -+/** CONFIG Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_CONFIG 0x00100000 -+/* Nothing -+#define ICU0_IM2_IOSR_CONFIG_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_CONFIG_INTOCC 0x00100000 -+/** CONFIG Break Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_CONFIG_BREAK 0x00080000 -+/* Nothing -+#define ICU0_IM2_IOSR_CONFIG_BREAK_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_CONFIG_BREAK_INTOCC 0x00080000 -+/** OCTRLC Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_OCTRLC 0x00040000 -+/* Nothing -+#define ICU0_IM2_IOSR_OCTRLC_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_OCTRLC_INTOCC 0x00040000 -+/** ICTRLC 1 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_ICTRLC1 0x00020000 -+/* Nothing -+#define ICU0_IM2_IOSR_ICTRLC1_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_ICTRLC1_INTOCC 0x00020000 -+/** ICTRLC 0 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_ICTRLC0 0x00010000 -+/* Nothing -+#define ICU0_IM2_IOSR_ICTRLC0_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_ICTRLC0_INTOCC 0x00010000 -+/** LINK 1 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_LINK1 0x00004000 -+/* Nothing -+#define ICU0_IM2_IOSR_LINK1_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_LINK1_INTOCC 0x00004000 -+/** TMU Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_TMU 0x00001000 -+/* Nothing -+#define ICU0_IM2_IOSR_TMU_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_TMU_INTOCC 0x00001000 -+/** FSQM Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_FSQM 0x00000800 -+/* Nothing -+#define ICU0_IM2_IOSR_FSQM_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_FSQM_INTOCC 0x00000800 -+/** IQM Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_IQM 0x00000400 -+/* Nothing -+#define ICU0_IM2_IOSR_IQM_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_IQM_INTOCC 0x00000400 -+/** OCTRLG Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_OCTRLG 0x00000200 -+/* Nothing -+#define ICU0_IM2_IOSR_OCTRLG_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_OCTRLG_INTOCC 0x00000200 -+/** OCTRLL 3 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_OCTRLL3 0x00000080 -+/* Nothing -+#define ICU0_IM2_IOSR_OCTRLL3_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_OCTRLL3_INTOCC 0x00000080 -+/** OCTRLL 2 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_OCTRLL2 0x00000040 -+/* Nothing -+#define ICU0_IM2_IOSR_OCTRLL2_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_OCTRLL2_INTOCC 0x00000040 -+/** OCTRLL 1 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_OCTRLL1 0x00000020 -+/* Nothing -+#define ICU0_IM2_IOSR_OCTRLL1_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_OCTRLL1_INTOCC 0x00000020 -+/** OCTRLL 0 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_OCTRLL0 0x00000010 -+/* Nothing -+#define ICU0_IM2_IOSR_OCTRLL0_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_OCTRLL0_INTOCC 0x00000010 -+/** ICTRLL 3 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_ICTRLL3 0x00000008 -+/* Nothing -+#define ICU0_IM2_IOSR_ICTRLL3_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_ICTRLL3_INTOCC 0x00000008 -+/** ICTRLL 2 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_ICTRLL2 0x00000004 -+/* Nothing -+#define ICU0_IM2_IOSR_ICTRLL2_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_ICTRLL2_INTOCC 0x00000004 -+/** ICTRLL 1 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_ICTRLL1 0x00000002 -+/* Nothing -+#define ICU0_IM2_IOSR_ICTRLL1_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_ICTRLL1_INTOCC 0x00000002 -+/** ICTRLL 0 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_ICTRLL0 0x00000001 -+/* Nothing -+#define ICU0_IM2_IOSR_ICTRLL0_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_ICTRLL0_INTOCC 0x00000001 -+ -+/* Fields of "IM2 Interrupt Request Set Register" */ -+/** EIM Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_EIM 0x80000000 -+/** GTC Upstream Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_GTC_US 0x40000000 -+/** GTC Downstream Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_GTC_DS 0x20000000 -+/** TBM Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_TBM 0x00400000 -+/** Dispatcher Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_DISP 0x00200000 -+/** CONFIG Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_CONFIG 0x00100000 -+/** CONFIG Break Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_CONFIG_BREAK 0x00080000 -+/** OCTRLC Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_OCTRLC 0x00040000 -+/** ICTRLC 1 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_ICTRLC1 0x00020000 -+/** ICTRLC 0 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_ICTRLC0 0x00010000 -+/** LINK 1 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_LINK1 0x00004000 -+/** TMU Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_TMU 0x00001000 -+/** FSQM Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_FSQM 0x00000800 -+/** IQM Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_IQM 0x00000400 -+/** OCTRLG Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_OCTRLG 0x00000200 -+/** OCTRLL 3 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_OCTRLL3 0x00000080 -+/** OCTRLL 2 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_OCTRLL2 0x00000040 -+/** OCTRLL 1 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_OCTRLL1 0x00000020 -+/** OCTRLL 0 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_OCTRLL0 0x00000010 -+/** ICTRLL 3 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_ICTRLL3 0x00000008 -+/** ICTRLL 2 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_ICTRLL2 0x00000004 -+/** ICTRLL 1 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_ICTRLL1 0x00000002 -+/** ICTRLL 0 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_ICTRLL0 0x00000001 -+ -+/* Fields of "IM2 Interrupt Mode Register" */ -+/** EIM Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_EIM 0x80000000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_EIM_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_EIM_DIR 0x80000000 -+/** GTC Upstream Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_GTC_US 0x40000000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_GTC_US_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_GTC_US_DIR 0x40000000 -+/** GTC Downstream Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_GTC_DS 0x20000000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_GTC_DS_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_GTC_DS_DIR 0x20000000 -+/** TBM Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_TBM 0x00400000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_TBM_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_TBM_DIR 0x00400000 -+/** Dispatcher Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_DISP 0x00200000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_DISP_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_DISP_DIR 0x00200000 -+/** CONFIG Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_CONFIG 0x00100000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_CONFIG_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_CONFIG_DIR 0x00100000 -+/** CONFIG Break Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_CONFIG_BREAK 0x00080000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_CONFIG_BREAK_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_CONFIG_BREAK_DIR 0x00080000 -+/** OCTRLC Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_OCTRLC 0x00040000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_OCTRLC_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_OCTRLC_DIR 0x00040000 -+/** ICTRLC 1 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_ICTRLC1 0x00020000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_ICTRLC1_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_ICTRLC1_DIR 0x00020000 -+/** ICTRLC 0 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_ICTRLC0 0x00010000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_ICTRLC0_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_ICTRLC0_DIR 0x00010000 -+/** LINK 1 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_LINK1 0x00004000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_LINK1_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_LINK1_DIR 0x00004000 -+/** TMU Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_TMU 0x00001000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_TMU_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_TMU_DIR 0x00001000 -+/** FSQM Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_FSQM 0x00000800 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_FSQM_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_FSQM_DIR 0x00000800 -+/** IQM Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_IQM 0x00000400 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_IQM_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_IQM_DIR 0x00000400 -+/** OCTRLG Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_OCTRLG 0x00000200 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_OCTRLG_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_OCTRLG_DIR 0x00000200 -+/** OCTRLL 3 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_OCTRLL3 0x00000080 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_OCTRLL3_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_OCTRLL3_DIR 0x00000080 -+/** OCTRLL 2 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_OCTRLL2 0x00000040 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_OCTRLL2_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_OCTRLL2_DIR 0x00000040 -+/** OCTRLL 1 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_OCTRLL1 0x00000020 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_OCTRLL1_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_OCTRLL1_DIR 0x00000020 -+/** OCTRLL 0 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_OCTRLL0 0x00000010 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_OCTRLL0_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_OCTRLL0_DIR 0x00000010 -+/** ICTRLL 3 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_ICTRLL3 0x00000008 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_ICTRLL3_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_ICTRLL3_DIR 0x00000008 -+/** ICTRLL 2 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_ICTRLL2 0x00000004 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_ICTRLL2_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_ICTRLL2_DIR 0x00000004 -+/** ICTRLL 1 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_ICTRLL1 0x00000002 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_ICTRLL1_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_ICTRLL1_DIR 0x00000002 -+/** ICTRLL 0 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_ICTRLL0 0x00000001 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_ICTRLL0_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_ICTRLL0_DIR 0x00000001 -+ -+/* Fields of "IM3 Interrupt Status Register" */ -+/** DFEV0, Channel 0 General Purpose Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_1GP 0x80000000 -+/* Nothing -+#define ICU0_IM3_ISR_DFEV0_1GP_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_1GP_INTACK 0x80000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_DFEV0_1GP_INTOCC 0x80000000 -+/** DFEV0, Channel 0 Receive Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_1RX 0x40000000 -+/* Nothing -+#define ICU0_IM3_ISR_DFEV0_1RX_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_1RX_INTACK 0x40000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_DFEV0_1RX_INTOCC 0x40000000 -+/** DFEV0, Channel 0 Transmit Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_1TX 0x20000000 -+/* Nothing -+#define ICU0_IM3_ISR_DFEV0_1TX_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_1TX_INTACK 0x20000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_DFEV0_1TX_INTOCC 0x20000000 -+/** DFEV0, Channel 1 General Purpose Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_2GP 0x10000000 -+/* Nothing -+#define ICU0_IM3_ISR_DFEV0_2GP_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_2GP_INTACK 0x10000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_DFEV0_2GP_INTOCC 0x10000000 -+/** DFEV0, Channel 1 Receive Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_2RX 0x08000000 -+/* Nothing -+#define ICU0_IM3_ISR_DFEV0_2RX_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_2RX_INTACK 0x08000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_DFEV0_2RX_INTOCC 0x08000000 -+/** DFEV0, Channel 1 Transmit Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_2TX 0x04000000 -+/* Nothing -+#define ICU0_IM3_ISR_DFEV0_2TX_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_2TX_INTACK 0x04000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_DFEV0_2TX_INTOCC 0x04000000 -+/** GPTC Timer/Counter 3B Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC3B 0x00200000 -+/* Nothing -+#define ICU0_IM3_ISR_GPTC_TC3B_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC3B_INTACK 0x00200000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_GPTC_TC3B_INTOCC 0x00200000 -+/** GPTC Timer/Counter 3A Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC3A 0x00100000 -+/* Nothing -+#define ICU0_IM3_ISR_GPTC_TC3A_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC3A_INTACK 0x00100000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_GPTC_TC3A_INTOCC 0x00100000 -+/** GPTC Timer/Counter 2B Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC2B 0x00080000 -+/* Nothing -+#define ICU0_IM3_ISR_GPTC_TC2B_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC2B_INTACK 0x00080000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_GPTC_TC2B_INTOCC 0x00080000 -+/** GPTC Timer/Counter 2A Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC2A 0x00040000 -+/* Nothing -+#define ICU0_IM3_ISR_GPTC_TC2A_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC2A_INTACK 0x00040000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_GPTC_TC2A_INTOCC 0x00040000 -+/** GPTC Timer/Counter 1B Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC1B 0x00020000 -+/* Nothing -+#define ICU0_IM3_ISR_GPTC_TC1B_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC1B_INTACK 0x00020000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_GPTC_TC1B_INTOCC 0x00020000 -+/** GPTC Timer/Counter 1A Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC1A 0x00010000 -+/* Nothing -+#define ICU0_IM3_ISR_GPTC_TC1A_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC1A_INTACK 0x00010000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_GPTC_TC1A_INTOCC 0x00010000 -+/** ASC1 Soft Flow Control Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC1_SFC 0x00008000 -+/* Nothing -+#define ICU0_IM3_ISR_ASC1_SFC_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC1_SFC_INTACK 0x00008000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC1_SFC_INTOCC 0x00008000 -+/** ASC1 Modem Status Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC1_MS 0x00004000 -+/* Nothing -+#define ICU0_IM3_ISR_ASC1_MS_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC1_MS_INTACK 0x00004000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC1_MS_INTOCC 0x00004000 -+/** ASC1 Autobaud Detection Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC1_ABDET 0x00002000 -+/* Nothing -+#define ICU0_IM3_ISR_ASC1_ABDET_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC1_ABDET_INTACK 0x00002000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC1_ABDET_INTOCC 0x00002000 -+/** ASC1 Autobaud Start Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC1_ABST 0x00001000 -+/* Nothing -+#define ICU0_IM3_ISR_ASC1_ABST_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC1_ABST_INTACK 0x00001000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC1_ABST_INTOCC 0x00001000 -+/** ASC1 Transmit Buffer Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC1_TB 0x00000800 -+/* Nothing -+#define ICU0_IM3_ISR_ASC1_TB_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC1_TB_INTACK 0x00000800 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC1_TB_INTOCC 0x00000800 -+/** ASC1 Error Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC1_E 0x00000400 -+/* Nothing -+#define ICU0_IM3_ISR_ASC1_E_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC1_E_INTACK 0x00000400 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC1_E_INTOCC 0x00000400 -+/** ASC1 Receive Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC1_R 0x00000200 -+/* Nothing -+#define ICU0_IM3_ISR_ASC1_R_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC1_R_INTACK 0x00000200 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC1_R_INTOCC 0x00000200 -+/** ASC1 Transmit Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC1_T 0x00000100 -+/* Nothing -+#define ICU0_IM3_ISR_ASC1_T_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC1_T_INTACK 0x00000100 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC1_T_INTOCC 0x00000100 -+/** ASC0 Soft Flow Control Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC0_SFC 0x00000080 -+/* Nothing -+#define ICU0_IM3_ISR_ASC0_SFC_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC0_SFC_INTACK 0x00000080 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC0_SFC_INTOCC 0x00000080 -+/** ASC1 Modem Status Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC0_MS 0x00000040 -+/* Nothing -+#define ICU0_IM3_ISR_ASC0_MS_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC0_MS_INTACK 0x00000040 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC0_MS_INTOCC 0x00000040 -+/** ASC0 Autobaud Detection Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC0_ABDET 0x00000020 -+/* Nothing -+#define ICU0_IM3_ISR_ASC0_ABDET_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC0_ABDET_INTACK 0x00000020 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC0_ABDET_INTOCC 0x00000020 -+/** ASC0 Autobaud Start Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC0_ABST 0x00000010 -+/* Nothing -+#define ICU0_IM3_ISR_ASC0_ABST_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC0_ABST_INTACK 0x00000010 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC0_ABST_INTOCC 0x00000010 -+/** ASC0 Transmit Buffer Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC0_TB 0x00000008 -+/* Nothing -+#define ICU0_IM3_ISR_ASC0_TB_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC0_TB_INTACK 0x00000008 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC0_TB_INTOCC 0x00000008 -+/** ASC0 Error Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC0_E 0x00000004 -+/* Nothing -+#define ICU0_IM3_ISR_ASC0_E_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC0_E_INTACK 0x00000004 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC0_E_INTOCC 0x00000004 -+/** ASC0 Receive Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC0_R 0x00000002 -+/* Nothing -+#define ICU0_IM3_ISR_ASC0_R_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC0_R_INTACK 0x00000002 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC0_R_INTOCC 0x00000002 -+/** ASC0 Transmit Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC0_T 0x00000001 -+/* Nothing -+#define ICU0_IM3_ISR_ASC0_T_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC0_T_INTACK 0x00000001 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC0_T_INTOCC 0x00000001 -+ -+/* Fields of "IM3 Interrupt Enable Register" */ -+/** DFEV0, Channel 0 General Purpose Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_DFEV0_1GP 0x80000000 -+/* Disable -+#define ICU0_IM3_IER_DFEV0_1GP_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_DFEV0_1GP_EN 0x80000000 -+/** DFEV0, Channel 0 Receive Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_DFEV0_1RX 0x40000000 -+/* Disable -+#define ICU0_IM3_IER_DFEV0_1RX_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_DFEV0_1RX_EN 0x40000000 -+/** DFEV0, Channel 0 Transmit Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_DFEV0_1TX 0x20000000 -+/* Disable -+#define ICU0_IM3_IER_DFEV0_1TX_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_DFEV0_1TX_EN 0x20000000 -+/** DFEV0, Channel 1 General Purpose Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_DFEV0_2GP 0x10000000 -+/* Disable -+#define ICU0_IM3_IER_DFEV0_2GP_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_DFEV0_2GP_EN 0x10000000 -+/** DFEV0, Channel 1 Receive Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_DFEV0_2RX 0x08000000 -+/* Disable -+#define ICU0_IM3_IER_DFEV0_2RX_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_DFEV0_2RX_EN 0x08000000 -+/** DFEV0, Channel 1 Transmit Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_DFEV0_2TX 0x04000000 -+/* Disable -+#define ICU0_IM3_IER_DFEV0_2TX_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_DFEV0_2TX_EN 0x04000000 -+/** GPTC Timer/Counter 3B Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_GPTC_TC3B 0x00200000 -+/* Disable -+#define ICU0_IM3_IER_GPTC_TC3B_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_GPTC_TC3B_EN 0x00200000 -+/** GPTC Timer/Counter 3A Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_GPTC_TC3A 0x00100000 -+/* Disable -+#define ICU0_IM3_IER_GPTC_TC3A_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_GPTC_TC3A_EN 0x00100000 -+/** GPTC Timer/Counter 2B Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_GPTC_TC2B 0x00080000 -+/* Disable -+#define ICU0_IM3_IER_GPTC_TC2B_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_GPTC_TC2B_EN 0x00080000 -+/** GPTC Timer/Counter 2A Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_GPTC_TC2A 0x00040000 -+/* Disable -+#define ICU0_IM3_IER_GPTC_TC2A_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_GPTC_TC2A_EN 0x00040000 -+/** GPTC Timer/Counter 1B Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_GPTC_TC1B 0x00020000 -+/* Disable -+#define ICU0_IM3_IER_GPTC_TC1B_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_GPTC_TC1B_EN 0x00020000 -+/** GPTC Timer/Counter 1A Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_GPTC_TC1A 0x00010000 -+/* Disable -+#define ICU0_IM3_IER_GPTC_TC1A_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_GPTC_TC1A_EN 0x00010000 -+/** ASC1 Soft Flow Control Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC1_SFC 0x00008000 -+/* Disable -+#define ICU0_IM3_IER_ASC1_SFC_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC1_SFC_EN 0x00008000 -+/** ASC1 Modem Status Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC1_MS 0x00004000 -+/* Disable -+#define ICU0_IM3_IER_ASC1_MS_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC1_MS_EN 0x00004000 -+/** ASC1 Autobaud Detection Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC1_ABDET 0x00002000 -+/* Disable -+#define ICU0_IM3_IER_ASC1_ABDET_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC1_ABDET_EN 0x00002000 -+/** ASC1 Autobaud Start Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC1_ABST 0x00001000 -+/* Disable -+#define ICU0_IM3_IER_ASC1_ABST_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC1_ABST_EN 0x00001000 -+/** ASC1 Transmit Buffer Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC1_TB 0x00000800 -+/* Disable -+#define ICU0_IM3_IER_ASC1_TB_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC1_TB_EN 0x00000800 -+/** ASC1 Error Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC1_E 0x00000400 -+/* Disable -+#define ICU0_IM3_IER_ASC1_E_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC1_E_EN 0x00000400 -+/** ASC1 Receive Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC1_R 0x00000200 -+/* Disable -+#define ICU0_IM3_IER_ASC1_R_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC1_R_EN 0x00000200 -+/** ASC1 Transmit Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC1_T 0x00000100 -+/* Disable -+#define ICU0_IM3_IER_ASC1_T_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC1_T_EN 0x00000100 -+/** ASC0 Soft Flow Control Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC0_SFC 0x00000080 -+/* Disable -+#define ICU0_IM3_IER_ASC0_SFC_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC0_SFC_EN 0x00000080 -+/** ASC1 Modem Status Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC0_MS 0x00000040 -+/* Disable -+#define ICU0_IM3_IER_ASC0_MS_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC0_MS_EN 0x00000040 -+/** ASC0 Autobaud Detection Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC0_ABDET 0x00000020 -+/* Disable -+#define ICU0_IM3_IER_ASC0_ABDET_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC0_ABDET_EN 0x00000020 -+/** ASC0 Autobaud Start Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC0_ABST 0x00000010 -+/* Disable -+#define ICU0_IM3_IER_ASC0_ABST_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC0_ABST_EN 0x00000010 -+/** ASC0 Transmit Buffer Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC0_TB 0x00000008 -+/* Disable -+#define ICU0_IM3_IER_ASC0_TB_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC0_TB_EN 0x00000008 -+/** ASC0 Error Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC0_E 0x00000004 -+/* Disable -+#define ICU0_IM3_IER_ASC0_E_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC0_E_EN 0x00000004 -+/** ASC0 Receive Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC0_R 0x00000002 -+/* Disable -+#define ICU0_IM3_IER_ASC0_R_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC0_R_EN 0x00000002 -+/** ASC0 Transmit Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC0_T 0x00000001 -+/* Disable -+#define ICU0_IM3_IER_ASC0_T_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC0_T_EN 0x00000001 -+ -+/* Fields of "IM3 Interrupt Output Status Register" */ -+/** DFEV0, Channel 0 General Purpose Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_DFEV0_1GP 0x80000000 -+/* Nothing -+#define ICU0_IM3_IOSR_DFEV0_1GP_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_DFEV0_1GP_INTOCC 0x80000000 -+/** DFEV0, Channel 0 Receive Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_DFEV0_1RX 0x40000000 -+/* Nothing -+#define ICU0_IM3_IOSR_DFEV0_1RX_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_DFEV0_1RX_INTOCC 0x40000000 -+/** DFEV0, Channel 0 Transmit Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_DFEV0_1TX 0x20000000 -+/* Nothing -+#define ICU0_IM3_IOSR_DFEV0_1TX_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_DFEV0_1TX_INTOCC 0x20000000 -+/** DFEV0, Channel 1 General Purpose Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_DFEV0_2GP 0x10000000 -+/* Nothing -+#define ICU0_IM3_IOSR_DFEV0_2GP_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_DFEV0_2GP_INTOCC 0x10000000 -+/** DFEV0, Channel 1 Receive Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_DFEV0_2RX 0x08000000 -+/* Nothing -+#define ICU0_IM3_IOSR_DFEV0_2RX_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_DFEV0_2RX_INTOCC 0x08000000 -+/** DFEV0, Channel 1 Transmit Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_DFEV0_2TX 0x04000000 -+/* Nothing -+#define ICU0_IM3_IOSR_DFEV0_2TX_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_DFEV0_2TX_INTOCC 0x04000000 -+/** GPTC Timer/Counter 3B Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_GPTC_TC3B 0x00200000 -+/* Nothing -+#define ICU0_IM3_IOSR_GPTC_TC3B_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_GPTC_TC3B_INTOCC 0x00200000 -+/** GPTC Timer/Counter 3A Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_GPTC_TC3A 0x00100000 -+/* Nothing -+#define ICU0_IM3_IOSR_GPTC_TC3A_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_GPTC_TC3A_INTOCC 0x00100000 -+/** GPTC Timer/Counter 2B Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_GPTC_TC2B 0x00080000 -+/* Nothing -+#define ICU0_IM3_IOSR_GPTC_TC2B_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_GPTC_TC2B_INTOCC 0x00080000 -+/** GPTC Timer/Counter 2A Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_GPTC_TC2A 0x00040000 -+/* Nothing -+#define ICU0_IM3_IOSR_GPTC_TC2A_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_GPTC_TC2A_INTOCC 0x00040000 -+/** GPTC Timer/Counter 1B Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_GPTC_TC1B 0x00020000 -+/* Nothing -+#define ICU0_IM3_IOSR_GPTC_TC1B_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_GPTC_TC1B_INTOCC 0x00020000 -+/** GPTC Timer/Counter 1A Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_GPTC_TC1A 0x00010000 -+/* Nothing -+#define ICU0_IM3_IOSR_GPTC_TC1A_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_GPTC_TC1A_INTOCC 0x00010000 -+/** ASC1 Soft Flow Control Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC1_SFC 0x00008000 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC1_SFC_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC1_SFC_INTOCC 0x00008000 -+/** ASC1 Modem Status Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC1_MS 0x00004000 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC1_MS_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC1_MS_INTOCC 0x00004000 -+/** ASC1 Autobaud Detection Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC1_ABDET 0x00002000 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC1_ABDET_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC1_ABDET_INTOCC 0x00002000 -+/** ASC1 Autobaud Start Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC1_ABST 0x00001000 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC1_ABST_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC1_ABST_INTOCC 0x00001000 -+/** ASC1 Transmit Buffer Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC1_TB 0x00000800 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC1_TB_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC1_TB_INTOCC 0x00000800 -+/** ASC1 Error Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC1_E 0x00000400 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC1_E_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC1_E_INTOCC 0x00000400 -+/** ASC1 Receive Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC1_R 0x00000200 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC1_R_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC1_R_INTOCC 0x00000200 -+/** ASC1 Transmit Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC1_T 0x00000100 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC1_T_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC1_T_INTOCC 0x00000100 -+/** ASC0 Soft Flow Control Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC0_SFC 0x00000080 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC0_SFC_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC0_SFC_INTOCC 0x00000080 -+/** ASC1 Modem Status Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC0_MS 0x00000040 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC0_MS_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC0_MS_INTOCC 0x00000040 -+/** ASC0 Autobaud Detection Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC0_ABDET 0x00000020 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC0_ABDET_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC0_ABDET_INTOCC 0x00000020 -+/** ASC0 Autobaud Start Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC0_ABST 0x00000010 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC0_ABST_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC0_ABST_INTOCC 0x00000010 -+/** ASC0 Transmit Buffer Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC0_TB 0x00000008 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC0_TB_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC0_TB_INTOCC 0x00000008 -+/** ASC0 Error Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC0_E 0x00000004 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC0_E_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC0_E_INTOCC 0x00000004 -+/** ASC0 Receive Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC0_R 0x00000002 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC0_R_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC0_R_INTOCC 0x00000002 -+/** ASC0 Transmit Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC0_T 0x00000001 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC0_T_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC0_T_INTOCC 0x00000001 -+ -+/* Fields of "IM3 Interrupt Request Set Register" */ -+/** DFEV0, Channel 0 General Purpose Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_DFEV0_1GP 0x80000000 -+/** DFEV0, Channel 0 Receive Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_DFEV0_1RX 0x40000000 -+/** DFEV0, Channel 0 Transmit Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_DFEV0_1TX 0x20000000 -+/** DFEV0, Channel 1 General Purpose Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_DFEV0_2GP 0x10000000 -+/** DFEV0, Channel 1 Receive Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_DFEV0_2RX 0x08000000 -+/** DFEV0, Channel 1 Transmit Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_DFEV0_2TX 0x04000000 -+/** GPTC Timer/Counter 3B Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_GPTC_TC3B 0x00200000 -+/** GPTC Timer/Counter 3A Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_GPTC_TC3A 0x00100000 -+/** GPTC Timer/Counter 2B Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_GPTC_TC2B 0x00080000 -+/** GPTC Timer/Counter 2A Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_GPTC_TC2A 0x00040000 -+/** GPTC Timer/Counter 1B Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_GPTC_TC1B 0x00020000 -+/** GPTC Timer/Counter 1A Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_GPTC_TC1A 0x00010000 -+/** ASC1 Soft Flow Control Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC1_SFC 0x00008000 -+/** ASC1 Modem Status Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC1_MS 0x00004000 -+/** ASC1 Autobaud Detection Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC1_ABDET 0x00002000 -+/** ASC1 Autobaud Start Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC1_ABST 0x00001000 -+/** ASC1 Transmit Buffer Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC1_TB 0x00000800 -+/** ASC1 Error Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC1_E 0x00000400 -+/** ASC1 Receive Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC1_R 0x00000200 -+/** ASC1 Transmit Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC1_T 0x00000100 -+/** ASC0 Soft Flow Control Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC0_SFC 0x00000080 -+/** ASC1 Modem Status Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC0_MS 0x00000040 -+/** ASC0 Autobaud Detection Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC0_ABDET 0x00000020 -+/** ASC0 Autobaud Start Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC0_ABST 0x00000010 -+/** ASC0 Transmit Buffer Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC0_TB 0x00000008 -+/** ASC0 Error Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC0_E 0x00000004 -+/** ASC0 Receive Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC0_R 0x00000002 -+/** ASC0 Transmit Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC0_T 0x00000001 -+ -+/* Fields of "IM3 Interrupt Mode Register" */ -+/** DFEV0, Channel 0 General Purpose Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_1GP 0x80000000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_DFEV0_1GP_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_1GP_DIR 0x80000000 -+/** DFEV0, Channel 0 Receive Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_1RX 0x40000000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_DFEV0_1RX_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_1RX_DIR 0x40000000 -+/** DFEV0, Channel 0 Transmit Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_1TX 0x20000000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_DFEV0_1TX_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_1TX_DIR 0x20000000 -+/** DFEV0, Channel 1 General Purpose Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_2GP 0x10000000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_DFEV0_2GP_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_2GP_DIR 0x10000000 -+/** DFEV0, Channel 1 Receive Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_2RX 0x08000000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_DFEV0_2RX_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_2RX_DIR 0x08000000 -+/** DFEV0, Channel 1 Transmit Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_2TX 0x04000000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_DFEV0_2TX_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_2TX_DIR 0x04000000 -+/** GPTC Timer/Counter 3B Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC3B 0x00200000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_GPTC_TC3B_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC3B_DIR 0x00200000 -+/** GPTC Timer/Counter 3A Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC3A 0x00100000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_GPTC_TC3A_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC3A_DIR 0x00100000 -+/** GPTC Timer/Counter 2B Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC2B 0x00080000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_GPTC_TC2B_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC2B_DIR 0x00080000 -+/** GPTC Timer/Counter 2A Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC2A 0x00040000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_GPTC_TC2A_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC2A_DIR 0x00040000 -+/** GPTC Timer/Counter 1B Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC1B 0x00020000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_GPTC_TC1B_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC1B_DIR 0x00020000 -+/** GPTC Timer/Counter 1A Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC1A 0x00010000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_GPTC_TC1A_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC1A_DIR 0x00010000 -+/** ASC1 Soft Flow Control Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC1_SFC 0x00008000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC1_SFC_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC1_SFC_DIR 0x00008000 -+/** ASC1 Modem Status Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC1_MS 0x00004000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC1_MS_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC1_MS_DIR 0x00004000 -+/** ASC1 Autobaud Detection Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC1_ABDET 0x00002000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC1_ABDET_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC1_ABDET_DIR 0x00002000 -+/** ASC1 Autobaud Start Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC1_ABST 0x00001000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC1_ABST_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC1_ABST_DIR 0x00001000 -+/** ASC1 Transmit Buffer Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC1_TB 0x00000800 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC1_TB_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC1_TB_DIR 0x00000800 -+/** ASC1 Error Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC1_E 0x00000400 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC1_E_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC1_E_DIR 0x00000400 -+/** ASC1 Receive Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC1_R 0x00000200 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC1_R_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC1_R_DIR 0x00000200 -+/** ASC1 Transmit Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC1_T 0x00000100 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC1_T_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC1_T_DIR 0x00000100 -+/** ASC0 Soft Flow Control Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC0_SFC 0x00000080 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC0_SFC_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC0_SFC_DIR 0x00000080 -+/** ASC1 Modem Status Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC0_MS 0x00000040 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC0_MS_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC0_MS_DIR 0x00000040 -+/** ASC0 Autobaud Detection Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC0_ABDET 0x00000020 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC0_ABDET_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC0_ABDET_DIR 0x00000020 -+/** ASC0 Autobaud Start Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC0_ABST 0x00000010 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC0_ABST_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC0_ABST_DIR 0x00000010 -+/** ASC0 Transmit Buffer Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC0_TB 0x00000008 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC0_TB_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC0_TB_DIR 0x00000008 -+/** ASC0 Error Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC0_E 0x00000004 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC0_E_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC0_E_DIR 0x00000004 -+/** ASC0 Receive Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC0_R 0x00000002 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC0_R_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC0_R_DIR 0x00000002 -+/** ASC0 Transmit Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC0_T 0x00000001 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC0_T_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC0_T_DIR 0x00000001 -+ -+/* Fields of "IM4 Interrupt Status Register" */ -+/** VPE0 Performance Monitoring Counter Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_VPE0_PMCIR 0x80000000 -+/* Nothing -+#define ICU0_IM4_ISR_VPE0_PMCIR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_VPE0_PMCIR_INTACK 0x80000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_VPE0_PMCIR_INTOCC 0x80000000 -+/** VPE0 Error Level Flag Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_VPE0_ERL 0x40000000 -+/* Nothing -+#define ICU0_IM4_ISR_VPE0_ERL_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_VPE0_ERL_INTACK 0x40000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_VPE0_ERL_INTOCC 0x40000000 -+/** VPE0 Exception Level Flag Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_VPE0_EXL 0x20000000 -+/* Nothing -+#define ICU0_IM4_ISR_VPE0_EXL_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_VPE0_EXL_INTACK 0x20000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_VPE0_EXL_INTOCC 0x20000000 -+/** MPS Bin. Sem Interrupt to VPE0 -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR8 0x00400000 -+/* Nothing -+#define ICU0_IM4_ISR_MPS_IR8_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR8_INTACK 0x00400000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_MPS_IR8_INTOCC 0x00400000 -+/** MPS Global Interrupt to VPE0 -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR7 0x00200000 -+/* Nothing -+#define ICU0_IM4_ISR_MPS_IR7_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR7_INTACK 0x00200000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_MPS_IR7_INTOCC 0x00200000 -+/** MPS Status Interrupt #6 (VPE1 to VPE0) -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR6 0x00100000 -+/* Nothing -+#define ICU0_IM4_ISR_MPS_IR6_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR6_INTACK 0x00100000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_MPS_IR6_INTOCC 0x00100000 -+/** MPS Status Interrupt #5 (VPE1 to VPE0) -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR5 0x00080000 -+/* Nothing -+#define ICU0_IM4_ISR_MPS_IR5_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR5_INTACK 0x00080000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_MPS_IR5_INTOCC 0x00080000 -+/** MPS Status Interrupt #4 (VPE1 to VPE0) -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR4 0x00040000 -+/* Nothing -+#define ICU0_IM4_ISR_MPS_IR4_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR4_INTACK 0x00040000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_MPS_IR4_INTOCC 0x00040000 -+/** MPS Status Interrupt #3 (VPE1 to VPE0) -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR3 0x00020000 -+/* Nothing -+#define ICU0_IM4_ISR_MPS_IR3_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR3_INTACK 0x00020000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_MPS_IR3_INTOCC 0x00020000 -+/** MPS Status Interrupt #2 (VPE1 to VPE0) -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR2 0x00010000 -+/* Nothing -+#define ICU0_IM4_ISR_MPS_IR2_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR2_INTACK 0x00010000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_MPS_IR2_INTOCC 0x00010000 -+/** MPS Status Interrupt #1 (VPE1 to VPE0) -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR1 0x00008000 -+/* Nothing -+#define ICU0_IM4_ISR_MPS_IR1_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR1_INTACK 0x00008000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_MPS_IR1_INTOCC 0x00008000 -+/** MPS Status Interrupt #0 (VPE1 to VPE0) -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR0 0x00004000 -+/* Nothing -+#define ICU0_IM4_ISR_MPS_IR0_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR0_INTACK 0x00004000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_MPS_IR0_INTOCC 0x00004000 -+/** TMU Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_TMU_ERR 0x00001000 -+/* Nothing -+#define ICU0_IM4_ISR_TMU_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_TMU_ERR_INTACK 0x00001000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_TMU_ERR_INTOCC 0x00001000 -+/** FSQM Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_FSQM_ERR 0x00000800 -+/* Nothing -+#define ICU0_IM4_ISR_FSQM_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_FSQM_ERR_INTACK 0x00000800 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_FSQM_ERR_INTOCC 0x00000800 -+/** IQM Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_IQM_ERR 0x00000400 -+/* Nothing -+#define ICU0_IM4_ISR_IQM_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_IQM_ERR_INTACK 0x00000400 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_IQM_ERR_INTOCC 0x00000400 -+/** OCTRLG Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_OCTRLG_ERR 0x00000200 -+/* Nothing -+#define ICU0_IM4_ISR_OCTRLG_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_OCTRLG_ERR_INTACK 0x00000200 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_OCTRLG_ERR_INTOCC 0x00000200 -+/** ICTRLG Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_ICTRLG_ERR 0x00000100 -+/* Nothing -+#define ICU0_IM4_ISR_ICTRLG_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_ICTRLG_ERR_INTACK 0x00000100 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_ICTRLG_ERR_INTOCC 0x00000100 -+/** OCTRLL 3 Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_OCTRLL3_ERR 0x00000080 -+/* Nothing -+#define ICU0_IM4_ISR_OCTRLL3_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_OCTRLL3_ERR_INTACK 0x00000080 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_OCTRLL3_ERR_INTOCC 0x00000080 -+/** OCTRLL 2 Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_OCTRLL2_ERR 0x00000040 -+/* Nothing -+#define ICU0_IM4_ISR_OCTRLL2_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_OCTRLL2_ERR_INTACK 0x00000040 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_OCTRLL2_ERR_INTOCC 0x00000040 -+/** OCTRLL 1 Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_OCTRLL1_ERR 0x00000020 -+/* Nothing -+#define ICU0_IM4_ISR_OCTRLL1_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_OCTRLL1_ERR_INTACK 0x00000020 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_OCTRLL1_ERR_INTOCC 0x00000020 -+/** OCTRLL 0 Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_OCTRLL0_ERR 0x00000010 -+/* Nothing -+#define ICU0_IM4_ISR_OCTRLL0_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_OCTRLL0_ERR_INTACK 0x00000010 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_OCTRLL0_ERR_INTOCC 0x00000010 -+/** ICTRLL 3 Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_ICTRLL3_ERR 0x00000008 -+/* Nothing -+#define ICU0_IM4_ISR_ICTRLL3_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_ICTRLL3_ERR_INTACK 0x00000008 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_ICTRLL3_ERR_INTOCC 0x00000008 -+/** ICTRLL 2 Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_ICTRLL2_ERR 0x00000004 -+/* Nothing -+#define ICU0_IM4_ISR_ICTRLL2_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_ICTRLL2_ERR_INTACK 0x00000004 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_ICTRLL2_ERR_INTOCC 0x00000004 -+/** ICTRLL 1 Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_ICTRLL1_ERR 0x00000002 -+/* Nothing -+#define ICU0_IM4_ISR_ICTRLL1_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_ICTRLL1_ERR_INTACK 0x00000002 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_ICTRLL1_ERR_INTOCC 0x00000002 -+/** ICTRLL 0 Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_ICTRLL0_ERR 0x00000001 -+/* Nothing -+#define ICU0_IM4_ISR_ICTRLL0_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_ICTRLL0_ERR_INTACK 0x00000001 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_ICTRLL0_ERR_INTOCC 0x00000001 -+ -+/* Fields of "IM4 Interrupt Enable Register" */ -+/** VPE0 Performance Monitoring Counter Interrupt -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_VPE0_PMCIR 0x80000000 -+/* Disable -+#define ICU0_IM4_IER_VPE0_PMCIR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_VPE0_PMCIR_EN 0x80000000 -+/** VPE0 Error Level Flag Interrupt -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_VPE0_ERL 0x40000000 -+/* Disable -+#define ICU0_IM4_IER_VPE0_ERL_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_VPE0_ERL_EN 0x40000000 -+/** VPE0 Exception Level Flag Interrupt -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_VPE0_EXL 0x20000000 -+/* Disable -+#define ICU0_IM4_IER_VPE0_EXL_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_VPE0_EXL_EN 0x20000000 -+/** MPS Bin. Sem Interrupt to VPE0 -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_MPS_IR8 0x00400000 -+/* Disable -+#define ICU0_IM4_IER_MPS_IR8_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_MPS_IR8_EN 0x00400000 -+/** MPS Global Interrupt to VPE0 -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_MPS_IR7 0x00200000 -+/* Disable -+#define ICU0_IM4_IER_MPS_IR7_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_MPS_IR7_EN 0x00200000 -+/** MPS Status Interrupt #6 (VPE1 to VPE0) -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_MPS_IR6 0x00100000 -+/* Disable -+#define ICU0_IM4_IER_MPS_IR6_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_MPS_IR6_EN 0x00100000 -+/** MPS Status Interrupt #5 (VPE1 to VPE0) -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_MPS_IR5 0x00080000 -+/* Disable -+#define ICU0_IM4_IER_MPS_IR5_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_MPS_IR5_EN 0x00080000 -+/** MPS Status Interrupt #4 (VPE1 to VPE0) -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_MPS_IR4 0x00040000 -+/* Disable -+#define ICU0_IM4_IER_MPS_IR4_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_MPS_IR4_EN 0x00040000 -+/** MPS Status Interrupt #3 (VPE1 to VPE0) -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_MPS_IR3 0x00020000 -+/* Disable -+#define ICU0_IM4_IER_MPS_IR3_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_MPS_IR3_EN 0x00020000 -+/** MPS Status Interrupt #2 (VPE1 to VPE0) -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_MPS_IR2 0x00010000 -+/* Disable -+#define ICU0_IM4_IER_MPS_IR2_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_MPS_IR2_EN 0x00010000 -+/** MPS Status Interrupt #1 (VPE1 to VPE0) -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_MPS_IR1 0x00008000 -+/* Disable -+#define ICU0_IM4_IER_MPS_IR1_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_MPS_IR1_EN 0x00008000 -+/** MPS Status Interrupt #0 (VPE1 to VPE0) -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_MPS_IR0 0x00004000 -+/* Disable -+#define ICU0_IM4_IER_MPS_IR0_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_MPS_IR0_EN 0x00004000 -+/** TMU Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_TMU_ERR 0x00001000 -+/* Disable -+#define ICU0_IM4_IER_TMU_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_TMU_ERR_EN 0x00001000 -+/** FSQM Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_FSQM_ERR 0x00000800 -+/* Disable -+#define ICU0_IM4_IER_FSQM_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_FSQM_ERR_EN 0x00000800 -+/** IQM Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_IQM_ERR 0x00000400 -+/* Disable -+#define ICU0_IM4_IER_IQM_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_IQM_ERR_EN 0x00000400 -+/** OCTRLG Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_OCTRLG_ERR 0x00000200 -+/* Disable -+#define ICU0_IM4_IER_OCTRLG_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_OCTRLG_ERR_EN 0x00000200 -+/** ICTRLG Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_ICTRLG_ERR 0x00000100 -+/* Disable -+#define ICU0_IM4_IER_ICTRLG_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_ICTRLG_ERR_EN 0x00000100 -+/** OCTRLL 3 Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_OCTRLL3_ERR 0x00000080 -+/* Disable -+#define ICU0_IM4_IER_OCTRLL3_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_OCTRLL3_ERR_EN 0x00000080 -+/** OCTRLL 2 Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_OCTRLL2_ERR 0x00000040 -+/* Disable -+#define ICU0_IM4_IER_OCTRLL2_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_OCTRLL2_ERR_EN 0x00000040 -+/** OCTRLL 1 Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_OCTRLL1_ERR 0x00000020 -+/* Disable -+#define ICU0_IM4_IER_OCTRLL1_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_OCTRLL1_ERR_EN 0x00000020 -+/** OCTRLL 0 Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_OCTRLL0_ERR 0x00000010 -+/* Disable -+#define ICU0_IM4_IER_OCTRLL0_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_OCTRLL0_ERR_EN 0x00000010 -+/** ICTRLL 3 Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_ICTRLL3_ERR 0x00000008 -+/* Disable -+#define ICU0_IM4_IER_ICTRLL3_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_ICTRLL3_ERR_EN 0x00000008 -+/** ICTRLL 2 Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_ICTRLL2_ERR 0x00000004 -+/* Disable -+#define ICU0_IM4_IER_ICTRLL2_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_ICTRLL2_ERR_EN 0x00000004 -+/** ICTRLL 1 Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_ICTRLL1_ERR 0x00000002 -+/* Disable -+#define ICU0_IM4_IER_ICTRLL1_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_ICTRLL1_ERR_EN 0x00000002 -+/** ICTRLL 0 Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_ICTRLL0_ERR 0x00000001 -+/* Disable -+#define ICU0_IM4_IER_ICTRLL0_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_ICTRLL0_ERR_EN 0x00000001 -+ -+/* Fields of "IM4 Interrupt Output Status Register" */ -+/** VPE0 Performance Monitoring Counter Interrupt -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_VPE0_PMCIR 0x80000000 -+/* Nothing -+#define ICU0_IM4_IOSR_VPE0_PMCIR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_VPE0_PMCIR_INTOCC 0x80000000 -+/** VPE0 Error Level Flag Interrupt -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_VPE0_ERL 0x40000000 -+/* Nothing -+#define ICU0_IM4_IOSR_VPE0_ERL_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_VPE0_ERL_INTOCC 0x40000000 -+/** VPE0 Exception Level Flag Interrupt -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_VPE0_EXL 0x20000000 -+/* Nothing -+#define ICU0_IM4_IOSR_VPE0_EXL_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_VPE0_EXL_INTOCC 0x20000000 -+/** MPS Bin. Sem Interrupt to VPE0 -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_MPS_IR8 0x00400000 -+/* Nothing -+#define ICU0_IM4_IOSR_MPS_IR8_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_MPS_IR8_INTOCC 0x00400000 -+/** MPS Global Interrupt to VPE0 -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_MPS_IR7 0x00200000 -+/* Nothing -+#define ICU0_IM4_IOSR_MPS_IR7_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_MPS_IR7_INTOCC 0x00200000 -+/** MPS Status Interrupt #6 (VPE1 to VPE0) -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_MPS_IR6 0x00100000 -+/* Nothing -+#define ICU0_IM4_IOSR_MPS_IR6_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_MPS_IR6_INTOCC 0x00100000 -+/** MPS Status Interrupt #5 (VPE1 to VPE0) -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_MPS_IR5 0x00080000 -+/* Nothing -+#define ICU0_IM4_IOSR_MPS_IR5_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_MPS_IR5_INTOCC 0x00080000 -+/** MPS Status Interrupt #4 (VPE1 to VPE0) -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_MPS_IR4 0x00040000 -+/* Nothing -+#define ICU0_IM4_IOSR_MPS_IR4_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_MPS_IR4_INTOCC 0x00040000 -+/** MPS Status Interrupt #3 (VPE1 to VPE0) -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_MPS_IR3 0x00020000 -+/* Nothing -+#define ICU0_IM4_IOSR_MPS_IR3_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_MPS_IR3_INTOCC 0x00020000 -+/** MPS Status Interrupt #2 (VPE1 to VPE0) -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_MPS_IR2 0x00010000 -+/* Nothing -+#define ICU0_IM4_IOSR_MPS_IR2_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_MPS_IR2_INTOCC 0x00010000 -+/** MPS Status Interrupt #1 (VPE1 to VPE0) -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_MPS_IR1 0x00008000 -+/* Nothing -+#define ICU0_IM4_IOSR_MPS_IR1_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_MPS_IR1_INTOCC 0x00008000 -+/** MPS Status Interrupt #0 (VPE1 to VPE0) -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_MPS_IR0 0x00004000 -+/* Nothing -+#define ICU0_IM4_IOSR_MPS_IR0_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_MPS_IR0_INTOCC 0x00004000 -+/** TMU Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_TMU_ERR 0x00001000 -+/* Nothing -+#define ICU0_IM4_IOSR_TMU_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_TMU_ERR_INTOCC 0x00001000 -+/** FSQM Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_FSQM_ERR 0x00000800 -+/* Nothing -+#define ICU0_IM4_IOSR_FSQM_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_FSQM_ERR_INTOCC 0x00000800 -+/** IQM Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_IQM_ERR 0x00000400 -+/* Nothing -+#define ICU0_IM4_IOSR_IQM_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_IQM_ERR_INTOCC 0x00000400 -+/** OCTRLG Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_OCTRLG_ERR 0x00000200 -+/* Nothing -+#define ICU0_IM4_IOSR_OCTRLG_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_OCTRLG_ERR_INTOCC 0x00000200 -+/** ICTRLG Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_ICTRLG_ERR 0x00000100 -+/* Nothing -+#define ICU0_IM4_IOSR_ICTRLG_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_ICTRLG_ERR_INTOCC 0x00000100 -+/** OCTRLL 3 Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_OCTRLL3_ERR 0x00000080 -+/* Nothing -+#define ICU0_IM4_IOSR_OCTRLL3_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_OCTRLL3_ERR_INTOCC 0x00000080 -+/** OCTRLL 2 Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_OCTRLL2_ERR 0x00000040 -+/* Nothing -+#define ICU0_IM4_IOSR_OCTRLL2_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_OCTRLL2_ERR_INTOCC 0x00000040 -+/** OCTRLL 1 Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_OCTRLL1_ERR 0x00000020 -+/* Nothing -+#define ICU0_IM4_IOSR_OCTRLL1_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_OCTRLL1_ERR_INTOCC 0x00000020 -+/** OCTRLL 0 Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_OCTRLL0_ERR 0x00000010 -+/* Nothing -+#define ICU0_IM4_IOSR_OCTRLL0_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_OCTRLL0_ERR_INTOCC 0x00000010 -+/** ICTRLL 3 Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_ICTRLL3_ERR 0x00000008 -+/* Nothing -+#define ICU0_IM4_IOSR_ICTRLL3_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_ICTRLL3_ERR_INTOCC 0x00000008 -+/** ICTRLL 2 Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_ICTRLL2_ERR 0x00000004 -+/* Nothing -+#define ICU0_IM4_IOSR_ICTRLL2_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_ICTRLL2_ERR_INTOCC 0x00000004 -+/** ICTRLL 1 Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_ICTRLL1_ERR 0x00000002 -+/* Nothing -+#define ICU0_IM4_IOSR_ICTRLL1_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_ICTRLL1_ERR_INTOCC 0x00000002 -+/** ICTRLL 0 Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_ICTRLL0_ERR 0x00000001 -+/* Nothing -+#define ICU0_IM4_IOSR_ICTRLL0_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_ICTRLL0_ERR_INTOCC 0x00000001 -+ -+/* Fields of "IM4 Interrupt Request Set Register" */ -+/** VPE0 Performance Monitoring Counter Interrupt -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_VPE0_PMCIR 0x80000000 -+/** VPE0 Error Level Flag Interrupt -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_VPE0_ERL 0x40000000 -+/** VPE0 Exception Level Flag Interrupt -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_VPE0_EXL 0x20000000 -+/** MPS Bin. Sem Interrupt to VPE0 -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_MPS_IR8 0x00400000 -+/** MPS Global Interrupt to VPE0 -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_MPS_IR7 0x00200000 -+/** MPS Status Interrupt #6 (VPE1 to VPE0) -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_MPS_IR6 0x00100000 -+/** MPS Status Interrupt #5 (VPE1 to VPE0) -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_MPS_IR5 0x00080000 -+/** MPS Status Interrupt #4 (VPE1 to VPE0) -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_MPS_IR4 0x00040000 -+/** MPS Status Interrupt #3 (VPE1 to VPE0) -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_MPS_IR3 0x00020000 -+/** MPS Status Interrupt #2 (VPE1 to VPE0) -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_MPS_IR2 0x00010000 -+/** MPS Status Interrupt #1 (VPE1 to VPE0) -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_MPS_IR1 0x00008000 -+/** MPS Status Interrupt #0 (VPE1 to VPE0) -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_MPS_IR0 0x00004000 -+/** TMU Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_TMU_ERR 0x00001000 -+/** FSQM Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_FSQM_ERR 0x00000800 -+/** IQM Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_IQM_ERR 0x00000400 -+/** OCTRLG Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_OCTRLG_ERR 0x00000200 -+/** ICTRLG Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_ICTRLG_ERR 0x00000100 -+/** OCTRLL 3 Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_OCTRLL3_ERR 0x00000080 -+/** OCTRLL 2 Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_OCTRLL2_ERR 0x00000040 -+/** OCTRLL 1 Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_OCTRLL1_ERR 0x00000020 -+/** OCTRLL 0 Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_OCTRLL0_ERR 0x00000010 -+/** ICTRLL 3 Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_ICTRLL3_ERR 0x00000008 -+/** ICTRLL 2 Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_ICTRLL2_ERR 0x00000004 -+/** ICTRLL 1 Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_ICTRLL1_ERR 0x00000002 -+/** ICTRLL 0 Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_ICTRLL0_ERR 0x00000001 -+ -+/* Fields of "IM4 Interrupt Mode Register" */ -+/** VPE0 Performance Monitoring Counter Interrupt -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_VPE0_PMCIR 0x80000000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_VPE0_PMCIR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_VPE0_PMCIR_DIR 0x80000000 -+/** VPE0 Error Level Flag Interrupt -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_VPE0_ERL 0x40000000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_VPE0_ERL_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_VPE0_ERL_DIR 0x40000000 -+/** VPE0 Exception Level Flag Interrupt -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_VPE0_EXL 0x20000000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_VPE0_EXL_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_VPE0_EXL_DIR 0x20000000 -+/** MPS Bin. Sem Interrupt to VPE0 -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR8 0x00400000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_MPS_IR8_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR8_DIR 0x00400000 -+/** MPS Global Interrupt to VPE0 -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR7 0x00200000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_MPS_IR7_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR7_DIR 0x00200000 -+/** MPS Status Interrupt #6 (VPE1 to VPE0) -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR6 0x00100000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_MPS_IR6_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR6_DIR 0x00100000 -+/** MPS Status Interrupt #5 (VPE1 to VPE0) -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR5 0x00080000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_MPS_IR5_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR5_DIR 0x00080000 -+/** MPS Status Interrupt #4 (VPE1 to VPE0) -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR4 0x00040000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_MPS_IR4_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR4_DIR 0x00040000 -+/** MPS Status Interrupt #3 (VPE1 to VPE0) -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR3 0x00020000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_MPS_IR3_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR3_DIR 0x00020000 -+/** MPS Status Interrupt #2 (VPE1 to VPE0) -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR2 0x00010000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_MPS_IR2_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR2_DIR 0x00010000 -+/** MPS Status Interrupt #1 (VPE1 to VPE0) -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR1 0x00008000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_MPS_IR1_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR1_DIR 0x00008000 -+/** MPS Status Interrupt #0 (VPE1 to VPE0) -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR0 0x00004000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_MPS_IR0_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR0_DIR 0x00004000 -+/** TMU Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_TMU_ERR 0x00001000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_TMU_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_TMU_ERR_DIR 0x00001000 -+/** FSQM Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_FSQM_ERR 0x00000800 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_FSQM_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_FSQM_ERR_DIR 0x00000800 -+/** IQM Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_IQM_ERR 0x00000400 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_IQM_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_IQM_ERR_DIR 0x00000400 -+/** OCTRLG Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_OCTRLG_ERR 0x00000200 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_OCTRLG_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_OCTRLG_ERR_DIR 0x00000200 -+/** ICTRLG Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_ICTRLG_ERR 0x00000100 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_ICTRLG_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_ICTRLG_ERR_DIR 0x00000100 -+/** OCTRLL 3 Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_OCTRLL3_ERR 0x00000080 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_OCTRLL3_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_OCTRLL3_ERR_DIR 0x00000080 -+/** OCTRLL 2 Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_OCTRLL2_ERR 0x00000040 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_OCTRLL2_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_OCTRLL2_ERR_DIR 0x00000040 -+/** OCTRLL 1 Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_OCTRLL1_ERR 0x00000020 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_OCTRLL1_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_OCTRLL1_ERR_DIR 0x00000020 -+/** OCTRLL 0 Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_OCTRLL0_ERR 0x00000010 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_OCTRLL0_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_OCTRLL0_ERR_DIR 0x00000010 -+/** ICTRLL 3 Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_ICTRLL3_ERR 0x00000008 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_ICTRLL3_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_ICTRLL3_ERR_DIR 0x00000008 -+/** ICTRLL 2 Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_ICTRLL2_ERR 0x00000004 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_ICTRLL2_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_ICTRLL2_ERR_DIR 0x00000004 -+/** ICTRLL 1 Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_ICTRLL1_ERR 0x00000002 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_ICTRLL1_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_ICTRLL1_ERR_DIR 0x00000002 -+/** ICTRLL 0 Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_ICTRLL0_ERR 0x00000001 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_ICTRLL0_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_ICTRLL0_ERR_DIR 0x00000001 -+ -+/* Fields of "ICU Interrupt Vector Register (5 bit variant)" */ -+/** IM4 Interrupt Vector Value -+ Returns the highest priority pending interrupt vector. */ -+#define ICU0_ICU_IVEC_IM4_vec_MASK 0x01F00000 -+/** field offset */ -+#define ICU0_ICU_IVEC_IM4_vec_OFFSET 20 -+/** Interrupt pending at bit 31 or no pending interrupt */ -+#define ICU0_ICU_IVEC_IM4_vec_NOINTorBit31 0x00000000 -+/** Interrupt pending at bit 0. */ -+#define ICU0_ICU_IVEC_IM4_vec_BIT0 0x00100000 -+/** Interrupt pending at bit 1. */ -+#define ICU0_ICU_IVEC_IM4_vec_BIT1 0x00200000 -+/** Interrupt pending at bit 30. */ -+#define ICU0_ICU_IVEC_IM4_vec_BIT30 0x01F00000 -+/** IM3 Interrupt Vector Value -+ Returns the highest priority pending interrupt vector. */ -+#define ICU0_ICU_IVEC_IM3_vec_MASK 0x000F8000 -+/** field offset */ -+#define ICU0_ICU_IVEC_IM3_vec_OFFSET 15 -+/** Interrupt pending at bit 31 or no pending interrupt */ -+#define ICU0_ICU_IVEC_IM3_vec_NOINTorBit31 0x00000000 -+/** Interrupt pending at bit 0. */ -+#define ICU0_ICU_IVEC_IM3_vec_BIT0 0x00008000 -+/** Interrupt pending at bit 1. */ -+#define ICU0_ICU_IVEC_IM3_vec_BIT1 0x00010000 -+/** Interrupt pending at bit 30. */ -+#define ICU0_ICU_IVEC_IM3_vec_BIT30 0x000F8000 -+/** IM2 Interrupt Vector Value -+ Returns the highest priority pending interrupt vector. */ -+#define ICU0_ICU_IVEC_IM2_vec_MASK 0x00007C00 -+/** field offset */ -+#define ICU0_ICU_IVEC_IM2_vec_OFFSET 10 -+/** Interrupt pending at bit 31 or no pending interrupt */ -+#define ICU0_ICU_IVEC_IM2_vec_NOINTorBit31 0x00000000 -+/** Interrupt pending at bit 0. */ -+#define ICU0_ICU_IVEC_IM2_vec_BIT0 0x00000400 -+/** Interrupt pending at bit 1. */ -+#define ICU0_ICU_IVEC_IM2_vec_BIT1 0x00000800 -+/** Interrupt pending at bit 30. */ -+#define ICU0_ICU_IVEC_IM2_vec_BIT30 0x00007C00 -+/** IM1 Interrupt Vector Value -+ Returns the highest priority pending interrupt vector. */ -+#define ICU0_ICU_IVEC_IM1_vec_MASK 0x000003E0 -+/** field offset */ -+#define ICU0_ICU_IVEC_IM1_vec_OFFSET 5 -+/** Interrupt pending at bit 31 or no pending interrupt */ -+#define ICU0_ICU_IVEC_IM1_vec_NOINTorBit31 0x00000000 -+/** Interrupt pending at bit 0. */ -+#define ICU0_ICU_IVEC_IM1_vec_BIT0 0x00000020 -+/** Interrupt pending at bit 1. */ -+#define ICU0_ICU_IVEC_IM1_vec_BIT1 0x00000040 -+/** Interrupt pending at bit 30. */ -+#define ICU0_ICU_IVEC_IM1_vec_BIT30 0x000003E0 -+/** IM0 Interrupt Vector Value -+ Returns the highest priority pending interrupt vector. */ -+#define ICU0_ICU_IVEC_IM0_vec_MASK 0x0000001F -+/** field offset */ -+#define ICU0_ICU_IVEC_IM0_vec_OFFSET 0 -+/** Interrupt pending at bit 31 or no pending interrupt */ -+#define ICU0_ICU_IVEC_IM0_vec_NOINTorBit31 0x00000000 -+/** Interrupt pending at bit 0. */ -+#define ICU0_ICU_IVEC_IM0_vec_BIT0 0x00000001 -+/** Interrupt pending at bit 1. */ -+#define ICU0_ICU_IVEC_IM0_vec_BIT1 0x00000002 -+/** Interrupt pending at bit 30. */ -+#define ICU0_ICU_IVEC_IM0_vec_BIT30 0x0000001F -+ -+/* Fields of "ICU Interrupt Vector Register (6 bit variant)" */ -+/** IM4 Interrupt Vector Value -+ Returns the highest priority pending interrupt vector. */ -+#define ICU0_ICU_IVEC_6_IM4_vec_MASK 0x3F000000 -+/** field offset */ -+#define ICU0_ICU_IVEC_6_IM4_vec_OFFSET 24 -+/** No pending interrupt */ -+#define ICU0_ICU_IVEC_6_IM4_vec_NOINT 0x00000000 -+/** Interrupt pending at bit 0. */ -+#define ICU0_ICU_IVEC_6_IM4_vec_BIT0 0x01000000 -+/** Interrupt pending at bit 1. */ -+#define ICU0_ICU_IVEC_6_IM4_vec_BIT1 0x02000000 -+/** Interrupt pending at bit 30. */ -+#define ICU0_ICU_IVEC_6_IM4_vec_BIT30 0x1F000000 -+/** Interrupt pending at bit 31. */ -+#define ICU0_ICU_IVEC_6_IM4_vec_BIT31 0x20000000 -+/** IM3 Interrupt Vector Value -+ Returns the highest priority pending interrupt vector. */ -+#define ICU0_ICU_IVEC_6_IM3_vec_MASK 0x00FC0000 -+/** field offset */ -+#define ICU0_ICU_IVEC_6_IM3_vec_OFFSET 18 -+/** No pending interrupt */ -+#define ICU0_ICU_IVEC_6_IM3_vec_NOINT 0x00000000 -+/** Interrupt pending at bit 0. */ -+#define ICU0_ICU_IVEC_6_IM3_vec_BIT0 0x00040000 -+/** Interrupt pending at bit 1. */ -+#define ICU0_ICU_IVEC_6_IM3_vec_BIT1 0x00080000 -+/** Interrupt pending at bit 30. */ -+#define ICU0_ICU_IVEC_6_IM3_vec_BIT30 0x007C0000 -+/** Interrupt pending at bit 31. */ -+#define ICU0_ICU_IVEC_6_IM3_vec_BIT31 0x00800000 -+/** IM2 Interrupt Vector Value -+ Returns the highest priority pending interrupt vector. */ -+#define ICU0_ICU_IVEC_6_IM2_vec_MASK 0x0003F000 -+/** field offset */ -+#define ICU0_ICU_IVEC_6_IM2_vec_OFFSET 12 -+/** No pending interrupt */ -+#define ICU0_ICU_IVEC_6_IM2_vec_NOINT 0x00000000 -+/** Interrupt pending at bit 0. */ -+#define ICU0_ICU_IVEC_6_IM2_vec_BIT0 0x00001000 -+/** Interrupt pending at bit 1. */ -+#define ICU0_ICU_IVEC_6_IM2_vec_BIT1 0x00002000 -+/** Interrupt pending at bit 30. */ -+#define ICU0_ICU_IVEC_6_IM2_vec_BIT30 0x0001F000 -+/** Interrupt pending at bit 31. */ -+#define ICU0_ICU_IVEC_6_IM2_vec_BIT31 0x00020000 -+/** IM1 Interrupt Vector Value -+ Returns the highest priority pending interrupt vector. */ -+#define ICU0_ICU_IVEC_6_IM1_vec_MASK 0x00000FC0 -+/** field offset */ -+#define ICU0_ICU_IVEC_6_IM1_vec_OFFSET 6 -+/** No pending interrupt */ -+#define ICU0_ICU_IVEC_6_IM1_vec_NOINT 0x00000000 -+/** Interrupt pending at bit 0. */ -+#define ICU0_ICU_IVEC_6_IM1_vec_BIT0 0x00000040 -+/** Interrupt pending at bit 1. */ -+#define ICU0_ICU_IVEC_6_IM1_vec_BIT1 0x00000080 -+/** Interrupt pending at bit 30. */ -+#define ICU0_ICU_IVEC_6_IM1_vec_BIT30 0x000007C0 -+/** Interrupt pending at bit 31. */ -+#define ICU0_ICU_IVEC_6_IM1_vec_BIT31 0x00000800 -+/** IM0 Interrupt Vector Value -+ Returns the highest priority pending interrupt vector. */ -+#define ICU0_ICU_IVEC_6_IM0_vec_MASK 0x0000003F -+/** field offset */ -+#define ICU0_ICU_IVEC_6_IM0_vec_OFFSET 0 -+/** No pending interrupt */ -+#define ICU0_ICU_IVEC_6_IM0_vec_NOINT 0x00000000 -+/** Interrupt pending at bit 0. */ -+#define ICU0_ICU_IVEC_6_IM0_vec_BIT0 0x00000001 -+/** Interrupt pending at bit 1. */ -+#define ICU0_ICU_IVEC_6_IM0_vec_BIT1 0x00000002 -+/** Interrupt pending at bit 30. */ -+#define ICU0_ICU_IVEC_6_IM0_vec_BIT30 0x0000001F -+/** Interrupt pending at bit 31. */ -+#define ICU0_ICU_IVEC_6_IM0_vec_BIT31 0x00000020 -+ -+/*! @} */ /* ICU0_REGISTER */ -+ -+#endif /* _icu0_reg_h */ ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/status_reg.h -@@ -0,0 +1,529 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+ -+#ifndef _status_reg_h -+#define _status_reg_h -+ -+/** \addtogroup STATUS_REGISTER -+ @{ -+*/ -+/* access macros */ -+#define status_r32(reg) reg_r32(&status->reg) -+#define status_w32(val, reg) reg_w32(val, &status->reg) -+#define status_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &status->reg) -+#define status_r32_table(reg, idx) reg_r32_table(status->reg, idx) -+#define status_w32_table(val, reg, idx) reg_w32_table(val, status->reg, idx) -+#define status_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, status->reg, idx) -+#define status_adr_table(reg, idx) adr_table(status->reg, idx) -+ -+ -+/** STATUS register structure */ -+struct gpon_reg_status -+{ -+ /** Reserved */ -+ unsigned int res_0[3]; /* 0x00000000 */ -+ /** Chip Identification Register */ -+ unsigned int chipid; /* 0x0000000C */ -+ /** Chip Location Register -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int chiploc; /* 0x00000010 */ -+ /** Redundancy register -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int red0; /* 0x00000014 */ -+ /** Redundancy register -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int red1; /* 0x00000018 */ -+ /** Redundancy register -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int red2; /* 0x0000001C */ -+ /** Redundancy register -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int red3; /* 0x00000020 */ -+ /** Redundancy register -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int red4; /* 0x00000024 */ -+ /** Redundancy register -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int red5; /* 0x00000028 */ -+ /** Redundancy register -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int red6; /* 0x0000002C */ -+ /** Redundancy register -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int red7; /* 0x00000030 */ -+ /** Redundancy register -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int red8; /* 0x00000034 */ -+ /** SPARE fuse register 0 -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int fuse0; /* 0x00000038 */ -+ /** Fuses for Analog modules -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int analog; /* 0x0000003C */ -+ /** Configuration fuses for drivers and pll -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int config; /* 0x00000040 */ -+ /** SPARE fuse register 1 -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int fuse1; /* 0x00000044 */ -+ /** Configuration for sbs0 rambist */ -+ unsigned int mbcfg; /* 0x00000048 */ -+ /** sbs0 bist result and debug data */ -+ unsigned int mbdata; /* 0x0000004C */ -+ /** Reserved */ -+ unsigned int res_1[12]; /* 0x00000050 */ -+}; -+ -+ -+/* Fields of "Chip Identification Register" */ -+/** Chip Version Number -+ Version number */ -+#define STATUS_CHIPID_VERSION_MASK 0xF0000000 -+/** field offset */ -+#define STATUS_CHIPID_VERSION_OFFSET 28 -+/** Part Number, Constant Part -+ The Part Number is fixed to 016Bhex. */ -+#define STATUS_CHIPID_PARTNR_MASK 0x0FFFF000 -+/** field offset */ -+#define STATUS_CHIPID_PARTNR_OFFSET 12 -+/** Manufacturer ID -+ The value of bit field MANID is fixed to 41hex as configured in the JTAG ID register. The JEDEC normalized manufacturer code for Infineon Technologies is C1hex */ -+#define STATUS_CHIPID_MANID_MASK 0x00000FFE -+/** field offset */ -+#define STATUS_CHIPID_MANID_OFFSET 1 -+/** Constant bit -+ The value of bit field CONST1 is fixed to 1hex */ -+#define STATUS_CHIPID_CONST1 0x00000001 -+ -+/* Fields of "Chip Location Register" */ -+/** Chip Lot ID */ -+#define STATUS_CHIPLOC_CHIPLOT_MASK 0xFFFF0000 -+/** field offset */ -+#define STATUS_CHIPLOC_CHIPLOT_OFFSET 16 -+/** Chip X Coordinate */ -+#define STATUS_CHIPLOC_CHIPX_MASK 0x0000FF00 -+/** field offset */ -+#define STATUS_CHIPLOC_CHIPX_OFFSET 8 -+/** Chip Y Coordinate */ -+#define STATUS_CHIPLOC_CHIPY_MASK 0x000000FF -+/** field offset */ -+#define STATUS_CHIPLOC_CHIPY_OFFSET 0 -+ -+/* Fields of "Redundancy register" */ -+/** Redundancy -+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ -+#define STATUS_RED0_REDUNDANCY_MASK 0x0003FFFF -+/** field offset */ -+#define STATUS_RED0_REDUNDANCY_OFFSET 0 -+ -+/* Fields of "Redundancy register" */ -+/** Redundancy -+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ -+#define STATUS_RED1_REDUNDANCY_MASK 0x0003FFFF -+/** field offset */ -+#define STATUS_RED1_REDUNDANCY_OFFSET 0 -+ -+/* Fields of "Redundancy register" */ -+/** Redundancy -+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ -+#define STATUS_RED2_REDUNDANCY_MASK 0x0003FFFF -+/** field offset */ -+#define STATUS_RED2_REDUNDANCY_OFFSET 0 -+ -+/* Fields of "Redundancy register" */ -+/** Redundancy -+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ -+#define STATUS_RED3_REDUNDANCY_MASK 0x0003FFFF -+/** field offset */ -+#define STATUS_RED3_REDUNDANCY_OFFSET 0 -+ -+/* Fields of "Redundancy register" */ -+/** Redundancy -+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ -+#define STATUS_RED4_REDUNDANCY_MASK 0x0003FFFF -+/** field offset */ -+#define STATUS_RED4_REDUNDANCY_OFFSET 0 -+ -+/* Fields of "Redundancy register" */ -+/** Redundancy -+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ -+#define STATUS_RED5_REDUNDANCY_MASK 0x0003FFFF -+/** field offset */ -+#define STATUS_RED5_REDUNDANCY_OFFSET 0 -+ -+/* Fields of "Redundancy register" */ -+/** Redundancy -+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ -+#define STATUS_RED6_REDUNDANCY_MASK 0x0003FFFF -+/** field offset */ -+#define STATUS_RED6_REDUNDANCY_OFFSET 0 -+ -+/* Fields of "Redundancy register" */ -+/** Redundancy -+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ -+#define STATUS_RED7_REDUNDANCY_MASK 0x0003FFFF -+/** field offset */ -+#define STATUS_RED7_REDUNDANCY_OFFSET 0 -+ -+/* Fields of "Redundancy register" */ -+/** Redundancy -+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ -+#define STATUS_RED8_REDUNDANCY_MASK 0x0003FFFF -+/** field offset */ -+#define STATUS_RED8_REDUNDANCY_OFFSET 0 -+ -+/* Fields of "SPARE fuse register 0" */ -+/** Soft fuse control -+ Controls whether the status block is in its softfused state or not. In the softfused state the values written via software are active effective. */ -+#define STATUS_FUSE0_SFC 0x80000000 -+/* Not selected -+#define STATUS_FUSE0_SFC_NSEL 0x00000000 */ -+/** Selected */ -+#define STATUS_FUSE0_SFC_SEL 0x80000000 -+/** Soft control MBCFG -+ Controls whether mbist configuration can be overwritten or not from subsystem. If not selected jtag mbcfg register is source for software mbist configuration */ -+#define STATUS_FUSE0_SC_MBCFG 0x40000000 -+/* Not selected -+#define STATUS_FUSE0_SC_MBCFG_NSEL 0x00000000 */ -+/** Selected */ -+#define STATUS_FUSE0_SC_MBCFG_SEL 0x40000000 -+/** spare fuse0 -+ eFuses not assigned to hw/sw, can be used for future applications */ -+#define STATUS_FUSE0_F0_MASK 0x3C000000 -+/** field offset */ -+#define STATUS_FUSE0_F0_OFFSET 26 -+/** VCALMM20 Voltage Reference -+ Voltage Reference for calibration via R and constant current (20 uA) */ -+#define STATUS_FUSE0_VCALMM20_MASK 0x03F00000 -+/** field offset */ -+#define STATUS_FUSE0_VCALMM20_OFFSET 20 -+/** VCALMM100 Voltage Reference -+ Voltage Reference for calibration via R and constant current (100 uA) */ -+#define STATUS_FUSE0_VCALMM100_MASK 0x000FC000 -+/** field offset */ -+#define STATUS_FUSE0_VCALMM100_OFFSET 14 -+/** VCALMM400 Voltage Reference -+ Voltage Reference for calibration via R and constant current (400 uA) */ -+#define STATUS_FUSE0_VCALMM400_MASK 0x00003F00 -+/** field offset */ -+#define STATUS_FUSE0_VCALMM400_OFFSET 8 -+/** RCALMM R error correction -+ The resistance deviation from ideal R (1000 Ohm) */ -+#define STATUS_FUSE0_RCALMM_MASK 0x000000FF -+/** field offset */ -+#define STATUS_FUSE0_RCALMM_OFFSET 0 -+ -+/* Fields of "Fuses for Analog modules" */ -+/** reserved Analog eFuses -+ Reserved Register contains information stored in eFuses needed for the analog modules */ -+#define STATUS_ANALOG_A0_MASK 0xFF000000 -+/** field offset */ -+#define STATUS_ANALOG_A0_OFFSET 24 -+/** Absolut Temperature -+ Temperature ERROR */ -+#define STATUS_ANALOG_TEMPMM_MASK 0x00FC0000 -+/** field offset */ -+#define STATUS_ANALOG_TEMPMM_OFFSET 18 -+/** Bias Voltage Generation -+ temperature dependency */ -+#define STATUS_ANALOG_TBGP_MASK 0x00038000 -+/** field offset */ -+#define STATUS_ANALOG_TBGP_OFFSET 15 -+/** Bias Voltage Generation -+ voltage dependency */ -+#define STATUS_ANALOG_VBGP_MASK 0x00007000 -+/** field offset */ -+#define STATUS_ANALOG_VBGP_OFFSET 12 -+/** Bias Current Generation */ -+#define STATUS_ANALOG_IREFBGP_MASK 0x00000F00 -+/** field offset */ -+#define STATUS_ANALOG_IREFBGP_OFFSET 8 -+/** Drive DAC Gain */ -+#define STATUS_ANALOG_GAINDRIVEDAC_MASK 0x000000F0 -+/** field offset */ -+#define STATUS_ANALOG_GAINDRIVEDAC_OFFSET 4 -+/** BIAS DAC Gain */ -+#define STATUS_ANALOG_GAINBIASDAC_MASK 0x0000000F -+/** field offset */ -+#define STATUS_ANALOG_GAINBIASDAC_OFFSET 0 -+ -+/* Fields of "Configuration fuses for drivers and pll" */ -+/** ddr PU driver -+ ddr pullup driver strength adjustment */ -+#define STATUS_CONFIG_DDRPU_MASK 0xC0000000 -+/** field offset */ -+#define STATUS_CONFIG_DDRPU_OFFSET 30 -+/** ddr PD driver -+ ddr pulldown driver strength adjustment */ -+#define STATUS_CONFIG_DDRPD_MASK 0x30000000 -+/** field offset */ -+#define STATUS_CONFIG_DDRPD_OFFSET 28 -+/** Authentification Unit enable -+ This bit can only be set via eFuse and enables the authentification unit. */ -+#define STATUS_CONFIG_SHA1EN 0x08000000 -+/* Not selected -+#define STATUS_CONFIG_SHA1EN_NSEL 0x00000000 */ -+/** Selected */ -+#define STATUS_CONFIG_SHA1EN_SEL 0x08000000 -+/** Encryption Unit enable -+ This bit can only be set via eFuse and enables the encryption unit. */ -+#define STATUS_CONFIG_AESEN 0x04000000 -+/* Not selected -+#define STATUS_CONFIG_AESEN_NSEL 0x00000000 */ -+/** Selected */ -+#define STATUS_CONFIG_AESEN_SEL 0x04000000 -+/** Subversion Number -+ The subversion number has no direct effect on hardware functions. It is used to provide another chip version number that is fixed in hardware and can be read out by software. In this way different product packages consisting of GPON_MODEM and software can be defined for example */ -+#define STATUS_CONFIG_SUBVERS_MASK 0x03C00000 -+/** field offset */ -+#define STATUS_CONFIG_SUBVERS_OFFSET 22 -+/** PLL settings -+ PLL settings for infrastructure block */ -+#define STATUS_CONFIG_PLLINFRA_MASK 0x003FF000 -+/** field offset */ -+#define STATUS_CONFIG_PLLINFRA_OFFSET 12 -+/** GPE frequency selection -+ Scaling down the GPE frequency for debugging purpose */ -+#define STATUS_CONFIG_GPEFREQ_MASK 0x00000C00 -+/** field offset */ -+#define STATUS_CONFIG_GPEFREQ_OFFSET 10 -+/** RM enable -+ Activates the Read Margin Settings defined in the RM Field, for all VIRAGE Memories except GPE */ -+#define STATUS_CONFIG_RME 0x00000200 -+/* Not selected -+#define STATUS_CONFIG_RME_NSEL 0x00000000 */ -+/** Selected */ -+#define STATUS_CONFIG_RME_SEL 0x00000200 -+/** RM settings -+ Read Marging Settings for all VIRAGE Memories except GPE */ -+#define STATUS_CONFIG_RM_MASK 0x000001E0 -+/** field offset */ -+#define STATUS_CONFIG_RM_OFFSET 5 -+/** RM enable for GPE Memories -+ Activates the Read Margin Settings defined in the RM Field */ -+#define STATUS_CONFIG_RMEGPE 0x00000010 -+/* Not selected -+#define STATUS_CONFIG_RMEGPE_NSEL 0x00000000 */ -+/** Selected */ -+#define STATUS_CONFIG_RMEGPE_SEL 0x00000010 -+/** RM settings for GPE Memories -+ Read Marging Settings for VIRAGE Memories in GPE module */ -+#define STATUS_CONFIG_RMGPE_MASK 0x0000000F -+/** field offset */ -+#define STATUS_CONFIG_RMGPE_OFFSET 0 -+ -+/* Fields of "SPARE fuse register 1" */ -+/** spare fuse1 -+ eFuses not assigned to hw/sw, can be used for future applications */ -+#define STATUS_FUSE1_F1_MASK 0xFFF00000 -+/** field offset */ -+#define STATUS_FUSE1_F1_OFFSET 20 -+/** DCDC DDR OFFSET -+ offset error sense path */ -+#define STATUS_FUSE1_OFFSETDDRDCDC_MASK 0x000F0000 -+/** field offset */ -+#define STATUS_FUSE1_OFFSETDDRDCDC_OFFSET 16 -+/** DCDC DDR GAIN -+ gain error sense path */ -+#define STATUS_FUSE1_GAINDDRDCDC_MASK 0x0000FC00 -+/** field offset */ -+#define STATUS_FUSE1_GAINDDRDCDC_OFFSET 10 -+/** DCDC APD OFFSET -+ offset error sense path */ -+#define STATUS_FUSE1_OFFSETAPDDCDC_MASK 0x000003C0 -+/** field offset */ -+#define STATUS_FUSE1_OFFSETAPDDCDC_OFFSET 6 -+/** DCDC APD GAIN -+ gain error sense path */ -+#define STATUS_FUSE1_GAINAPDDCDC_MASK 0x0000003F -+/** field offset */ -+#define STATUS_FUSE1_GAINAPDDCDC_OFFSET 0 -+ -+/* Fields of "Configuration for sbs0 rambist" */ -+/** Disable asc monitoring during boot-up -+ Bit is used to avoid asc output for reducing pattern count on testsystem */ -+#define STATUS_MBCFG_ASC_DBGDIS 0x01000000 -+/* Disable -+#define STATUS_MBCFG_ASC_DBGDIS_DIS 0x00000000 */ -+/** Enable */ -+#define STATUS_MBCFG_ASC_DBGDIS_EN 0x01000000 -+/** Descrambling Enable/Disable -+ Enables Address and Data Descrambling for internal Memory Test */ -+#define STATUS_MBCFG_DSC 0x00800000 -+/* Disable -+#define STATUS_MBCFG_DSC_DIS 0x00000000 */ -+/** Enable */ -+#define STATUS_MBCFG_DSC_EN 0x00800000 -+/** Enable repair mode -+ When bit is set redundancy repair mode is activated */ -+#define STATUS_MBCFG_REPAIR 0x00400000 -+/* Disable -+#define STATUS_MBCFG_REPAIR_DIS 0x00000000 */ -+/** Enable */ -+#define STATUS_MBCFG_REPAIR_EN 0x00400000 -+/** DEBUG Mode */ -+#define STATUS_MBCFG_DBG 0x00200000 -+/* Disable -+#define STATUS_MBCFG_DBG_DIS 0x00000000 */ -+/** Enable */ -+#define STATUS_MBCFG_DBG_EN 0x00200000 -+/** Retention Time -+ Length oft the Retention Time */ -+#define STATUS_MBCFG_RTIME_MASK 0x001C0000 -+/** field offset */ -+#define STATUS_MBCFG_RTIME_OFFSET 18 -+/** retention mode is switched off */ -+#define STATUS_MBCFG_RTIME_RET0 0x00000000 -+/** Retention time 50 ms */ -+#define STATUS_MBCFG_RTIME_RET50 0x00040000 -+/** Retention time 60 ms */ -+#define STATUS_MBCFG_RTIME_RET60 0x00080000 -+/** Retention time 70 ms */ -+#define STATUS_MBCFG_RTIME_RET70 0x000C0000 -+/** Retention time 80 ms */ -+#define STATUS_MBCFG_RTIME_RET80 0x00100000 -+/** Retention time 90 ms */ -+#define STATUS_MBCFG_RTIME_RET90 0x00140000 -+/** Retention time 1000 ms */ -+#define STATUS_MBCFG_RTIME_RET1000 0x00180000 -+/** Test ID -+ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ -+#define STATUS_MBCFG_TID_5_MASK 0x00038000 -+/** field offset */ -+#define STATUS_MBCFG_TID_5_OFFSET 15 -+/** No test is performed */ -+#define STATUS_MBCFG_TID_5_NONE 0x00000000 -+/** March test */ -+#define STATUS_MBCFG_TID_5_MARCH 0x00008000 -+/** Checkerboard test */ -+#define STATUS_MBCFG_TID_5_CHCK 0x00010000 -+/** Hammer test */ -+#define STATUS_MBCFG_TID_5_HAM 0x00018000 -+/** Address decoder test */ -+#define STATUS_MBCFG_TID_5_ADEC 0x00020000 -+/** Write mask byte test */ -+#define STATUS_MBCFG_TID_5_WMBYTE 0x00028000 -+/** Reserved */ -+#define STATUS_MBCFG_TID_5_RES 0x00030000 -+/** Test ID -+ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ -+#define STATUS_MBCFG_TID_4_MASK 0x00007000 -+/** field offset */ -+#define STATUS_MBCFG_TID_4_OFFSET 12 -+/** No test is performed */ -+#define STATUS_MBCFG_TID_4_NONE 0x00000000 -+/** March test */ -+#define STATUS_MBCFG_TID_4_MARCH 0x00001000 -+/** Checkerboard test */ -+#define STATUS_MBCFG_TID_4_CHCK 0x00002000 -+/** Hammer test */ -+#define STATUS_MBCFG_TID_4_HAM 0x00003000 -+/** Address decoder test */ -+#define STATUS_MBCFG_TID_4_ADEC 0x00004000 -+/** Write mask byte test */ -+#define STATUS_MBCFG_TID_4_WMBYTE 0x00005000 -+/** Reserved */ -+#define STATUS_MBCFG_TID_4_RES 0x00006000 -+/** Test ID -+ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ -+#define STATUS_MBCFG_TID_3_MASK 0x00000E00 -+/** field offset */ -+#define STATUS_MBCFG_TID_3_OFFSET 9 -+/** No test is performed */ -+#define STATUS_MBCFG_TID_3_NONE 0x00000000 -+/** March test */ -+#define STATUS_MBCFG_TID_3_MARCH 0x00000200 -+/** Checkerboard test */ -+#define STATUS_MBCFG_TID_3_CHCK 0x00000400 -+/** Hammer test */ -+#define STATUS_MBCFG_TID_3_HAM 0x00000600 -+/** Address decoder test */ -+#define STATUS_MBCFG_TID_3_ADEC 0x00000800 -+/** Write mask byte test */ -+#define STATUS_MBCFG_TID_3_WMBYTE 0x00000A00 -+/** Reserved */ -+#define STATUS_MBCFG_TID_3_RES 0x00000C00 -+/** Test ID -+ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ -+#define STATUS_MBCFG_TID_2_MASK 0x000001C0 -+/** field offset */ -+#define STATUS_MBCFG_TID_2_OFFSET 6 -+/** No test is performed */ -+#define STATUS_MBCFG_TID_2_NONE 0x00000000 -+/** March test */ -+#define STATUS_MBCFG_TID_2_MARCH 0x00000040 -+/** Checkerboard test */ -+#define STATUS_MBCFG_TID_2_CHCK 0x00000080 -+/** Hammer test */ -+#define STATUS_MBCFG_TID_2_HAM 0x000000C0 -+/** Address decoder test */ -+#define STATUS_MBCFG_TID_2_ADEC 0x00000100 -+/** Write mask byte test */ -+#define STATUS_MBCFG_TID_2_WMBYTE 0x00000140 -+/** Reserved */ -+#define STATUS_MBCFG_TID_2_RES 0x00000180 -+/** Test ID -+ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ -+#define STATUS_MBCFG_TID_1_MASK 0x00000038 -+/** field offset */ -+#define STATUS_MBCFG_TID_1_OFFSET 3 -+/** No test is performed */ -+#define STATUS_MBCFG_TID_1_NONE 0x00000000 -+/** March test */ -+#define STATUS_MBCFG_TID_1_MARCH 0x00000008 -+/** Checkerboard test */ -+#define STATUS_MBCFG_TID_1_CHCK 0x00000010 -+/** Hammer test */ -+#define STATUS_MBCFG_TID_1_HAM 0x00000018 -+/** Address decoder test */ -+#define STATUS_MBCFG_TID_1_ADEC 0x00000020 -+/** Write mask byte test */ -+#define STATUS_MBCFG_TID_1_WMBYTE 0x00000028 -+/** Reserved */ -+#define STATUS_MBCFG_TID_1_RES 0x00000030 -+/** Test ID -+ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ -+#define STATUS_MBCFG_TID_0_MASK 0x00000007 -+/** field offset */ -+#define STATUS_MBCFG_TID_0_OFFSET 0 -+/** No test is performed */ -+#define STATUS_MBCFG_TID_0_NONE 0x00000000 -+/** March test */ -+#define STATUS_MBCFG_TID_0_MARCH 0x00000001 -+/** Checkerboard test */ -+#define STATUS_MBCFG_TID_0_CHCK 0x00000002 -+/** Hammer test */ -+#define STATUS_MBCFG_TID_0_HAM 0x00000003 -+/** Address decoder test */ -+#define STATUS_MBCFG_TID_0_ADEC 0x00000004 -+/** Write mask byte test */ -+#define STATUS_MBCFG_TID_0_WMBYTE 0x00000005 -+/** Reserved */ -+#define STATUS_MBCFG_TID_0_RES 0x00000006 -+ -+/* Fields of "sbs0 bist result and debug data" */ -+/** BIST result and debug data -+ Stores additional debug information */ -+#define STATUS_MBDATA_DATA_MASK 0xFFFFFFF8 -+/** field offset */ -+#define STATUS_MBDATA_DATA_OFFSET 3 -+/** MBIST NOGO -+ The BIST failed and cannot be repaired due to many failure locations */ -+#define STATUS_MBDATA_MBNOGO 0x00000004 -+/** MBIST FAILED -+ The BIST failed but can be repaired */ -+#define STATUS_MBDATA_MBFAIL 0x00000002 -+/** MBIST PASSED -+ The BIST passed without any Failures */ -+#define STATUS_MBDATA_MBPASS 0x00000001 -+ -+/*! @} */ /* STATUS_REGISTER */ -+ -+#endif /* _status_reg_h */ ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/sys1_reg.h -@@ -0,0 +1,2008 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+ -+#ifndef _sys1_reg_h -+#define _sys1_reg_h -+ -+/** \addtogroup SYS1_REGISTER -+ @{ -+*/ -+/* access macros */ -+#define sys1_r32(reg) reg_r32(&sys1->reg) -+#define sys1_w32(val, reg) reg_w32(val, &sys1->reg) -+#define sys1_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys1->reg) -+#define sys1_r32_table(reg, idx) reg_r32_table(sys1->reg, idx) -+#define sys1_w32_table(val, reg, idx) reg_w32_table(val, sys1->reg, idx) -+#define sys1_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys1->reg, idx) -+#define sys1_adr_table(reg, idx) adr_table(sys1->reg, idx) -+ -+ -+/** SYS1 register structure */ -+struct gpon_reg_sys1 -+{ -+ /** Clock Status Register */ -+ unsigned int clks; /* 0x00000000 */ -+ /** Clock Enable Register -+ Via this register the clocks for the domains can be enabled. */ -+ unsigned int clken; /* 0x00000004 */ -+ /** Clock Clear Register -+ Via this register the clocks for the domains can be disabled. */ -+ unsigned int clkclr; /* 0x00000008 */ -+ /** Reserved */ -+ unsigned int res_0[5]; /* 0x0000000C */ -+ /** Activation Status Register */ -+ unsigned int acts; /* 0x00000020 */ -+ /** Activation Register -+ Via this register the domains can be activated. */ -+ unsigned int act; /* 0x00000024 */ -+ /** Deactivation Register -+ Via this register the domains can be deactivated. */ -+ unsigned int deact; /* 0x00000028 */ -+ /** Reboot Trigger Register -+ Via this register the domains can be rebooted (sent through reset). */ -+ unsigned int rbt; /* 0x0000002C */ -+ /** Reserved */ -+ unsigned int res_1[4]; /* 0x00000030 */ -+ /** CPU0 Clock Control Register -+ Clock control register for CPU0 */ -+ unsigned int cpu0cc; /* 0x00000040 */ -+ /** Reserved */ -+ unsigned int res_2[7]; /* 0x00000044 */ -+ /** CPU0 Reset Source Register -+ Via this register the CPU can find the the root cause for the boot it currently goes through, and take the appropriate measures. */ -+ unsigned int cpu0rs; /* 0x00000060 */ -+ /** Reserved */ -+ unsigned int res_3[7]; /* 0x00000064 */ -+ /** CPU0 Wakeup Configuration Register -+ Controls the wakeup condition for CPU0. Note: The upper 16 bit of this register have to be set to the same value as the mask bits within the yield-resume interface block. If the yield-resume interface is not used at all, set the upper 16 bit to 0. */ -+ unsigned int cpu0wcfg; /* 0x00000080 */ -+ /** Reserved */ -+ unsigned int res_4[7]; /* 0x00000084 */ -+ /** Bootmode Control Register -+ Reflects the bootmode for the CPU and provides means to manipulate it. */ -+ unsigned int bmc; /* 0x000000A0 */ -+ /** Reserved */ -+ unsigned int res_5[3]; /* 0x000000A4 */ -+ /** Sleep Configuration Register */ -+ unsigned int scfg; /* 0x000000B0 */ -+ /** Power Down Configuration Register -+ Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be switched off. */ -+ unsigned int pdcfg; /* 0x000000B4 */ -+ /** CLKO Pad Control Register -+ Controls the behaviour of the CLKO pad/ball. */ -+ unsigned int clkoc; /* 0x000000B8 */ -+ /** Infrastructure Control Register -+ Controls the behaviour of the components of the infrastructure block. */ -+ unsigned int infrac; /* 0x000000BC */ -+ /** HRST_OUT_N Control Register -+ Controls the behaviour of the HRST_OUT_N pin. */ -+ unsigned int hrstoutc; /* 0x000000C0 */ -+ /** EBU Clock Control Register -+ Clock control register for the EBU. */ -+ unsigned int ebucc; /* 0x000000C4 */ -+ /** Reserved */ -+ unsigned int res_6[2]; /* 0x000000C8 */ -+ /** NMI Status Register -+ The Test NMI source is the GPTC counter 1A overflow bit. */ -+ unsigned int nmis; /* 0x000000D0 */ -+ /** NMI Set Register */ -+ unsigned int nmiset; /* 0x000000D4 */ -+ /** NMI Clear Register */ -+ unsigned int nmiclr; /* 0x000000D8 */ -+ /** NMI Test Configuration Register */ -+ unsigned int nmitcfg; /* 0x000000DC */ -+ /** NMI VPE1 Control Register */ -+ unsigned int nmivpe1c; /* 0x000000E0 */ -+ /** Reserved */ -+ unsigned int res_7[3]; /* 0x000000E4 */ -+ /** IRN Capture Register -+ This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNEN register. The interrupts can be acknowledged by a write operation. */ -+ unsigned int irncr; /* 0x000000F0 */ -+ /** IRN Interrupt Control Register -+ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ -+ unsigned int irnicr; /* 0x000000F4 */ -+ /** IRN Interrupt Enable Register -+ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCR register and are not signalled via the interrupt line towards the controller. */ -+ unsigned int irnen; /* 0x000000F8 */ -+ /** Reserved */ -+ unsigned int res_8; /* 0x000000FC */ -+}; -+ -+ -+/* Fields of "Clock Status Register" */ -+/** STATUS Clock Enable -+ Shows the clock enable bit for the STATUS domain. This domain contains the STATUS block. */ -+#define CLKS_STATUS 0x80000000 -+/* Disable -+#define CLKS_STATUS_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_STATUS_EN 0x80000000 -+/** SHA1 Clock Enable -+ Shows the clock enable bit for the SHA1 domain. This domain contains the SHA1 block. */ -+#define CLKS_SHA1 0x40000000 -+/* Disable -+#define CLKS_SHA1_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_SHA1_EN 0x40000000 -+/** AES Clock Enable -+ Shows the clock enable bit for the AES domain. This domain contains the AES block. */ -+#define CLKS_AES 0x20000000 -+/* Disable -+#define CLKS_AES_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_AES_EN 0x20000000 -+/** PCM Clock Enable -+ Shows the clock enable bit for the PCM domain. This domain contains the PCM interface block. */ -+#define CLKS_PCM 0x10000000 -+/* Disable -+#define CLKS_PCM_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_PCM_EN 0x10000000 -+/** FSCT Clock Enable -+ Shows the clock enable bit for the FSCT domain. This domain contains the FSCT block. */ -+#define CLKS_FSCT 0x08000000 -+/* Disable -+#define CLKS_FSCT_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_FSCT_EN 0x08000000 -+/** GPTC Clock Enable -+ Shows the clock enable bit for the GPTC domain. This domain contains the GPTC block. */ -+#define CLKS_GPTC 0x04000000 -+/* Disable -+#define CLKS_GPTC_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_GPTC_EN 0x04000000 -+/** MPS Clock Enable -+ Shows the clock enable bit for the MPS domain. This domain contains the MPS block. */ -+#define CLKS_MPS 0x02000000 -+/* Disable -+#define CLKS_MPS_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_MPS_EN 0x02000000 -+/** DFEV0 Clock Enable -+ Shows the clock enable bit for the DFEV0 domain. This domain contains the DFEV0 block. */ -+#define CLKS_DFEV0 0x01000000 -+/* Disable -+#define CLKS_DFEV0_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_DFEV0_EN 0x01000000 -+/** PADCTRL4 Clock Enable -+ Shows the clock enable bit for the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ -+#define CLKS_PADCTRL4 0x00400000 -+/* Disable -+#define CLKS_PADCTRL4_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_PADCTRL4_EN 0x00400000 -+/** PADCTRL3 Clock Enable -+ Shows the clock enable bit for the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ -+#define CLKS_PADCTRL3 0x00200000 -+/* Disable -+#define CLKS_PADCTRL3_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_PADCTRL3_EN 0x00200000 -+/** PADCTRL1 Clock Enable -+ Shows the clock enable bit for the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ -+#define CLKS_PADCTRL1 0x00100000 -+/* Disable -+#define CLKS_PADCTRL1_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_PADCTRL1_EN 0x00100000 -+/** P4 Clock Enable -+ Shows the clock enable bit for the P4 domain. This domain contains the P4 instance of the GPIO block. */ -+#define CLKS_P4 0x00040000 -+/* Disable -+#define CLKS_P4_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_P4_EN 0x00040000 -+/** P3 Clock Enable -+ Shows the clock enable bit for the P3 domain. This domain contains the P3 instance of the GPIO block. */ -+#define CLKS_P3 0x00020000 -+/* Disable -+#define CLKS_P3_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_P3_EN 0x00020000 -+/** P1 Clock Enable -+ Shows the clock enable bit for the P1 domain. This domain contains the P1 instance of the GPIO block. */ -+#define CLKS_P1 0x00010000 -+/* Disable -+#define CLKS_P1_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_P1_EN 0x00010000 -+/** HOST Clock Enable -+ Shows the clock enable bit for the HOST domain. This domain contains the HOST interface block. */ -+#define CLKS_HOST 0x00008000 -+/* Disable -+#define CLKS_HOST_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_HOST_EN 0x00008000 -+/** I2C Clock Enable -+ Shows the clock enable bit for the I2C domain. This domain contains the I2C interface block. */ -+#define CLKS_I2C 0x00004000 -+/* Disable -+#define CLKS_I2C_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_I2C_EN 0x00004000 -+/** SSC0 Clock Enable -+ Shows the clock enable bit for the SSC0 domain. This domain contains the SSC0 interface block. */ -+#define CLKS_SSC0 0x00002000 -+/* Disable -+#define CLKS_SSC0_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_SSC0_EN 0x00002000 -+/** ASC0 Clock Enable -+ Shows the clock enable bit for the ASC0 domain. This domain contains the ASC0 interface block. */ -+#define CLKS_ASC0 0x00001000 -+/* Disable -+#define CLKS_ASC0_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_ASC0_EN 0x00001000 -+/** ASC1 Clock Enable -+ Shows the clock enable bit for the ASC1 domain. This domain contains the ASC1 block. */ -+#define CLKS_ASC1 0x00000800 -+/* Disable -+#define CLKS_ASC1_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_ASC1_EN 0x00000800 -+/** DCDCAPD Clock Enable -+ Shows the clock enable bit for the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ -+#define CLKS_DCDCAPD 0x00000400 -+/* Disable -+#define CLKS_DCDCAPD_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_DCDCAPD_EN 0x00000400 -+/** DCDCDDR Clock Enable -+ Shows the clock enable bit for the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ -+#define CLKS_DCDCDDR 0x00000200 -+/* Disable -+#define CLKS_DCDCDDR_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_DCDCDDR_EN 0x00000200 -+/** DCDC1V0 Clock Enable -+ Shows the clock enable bit for the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ -+#define CLKS_DCDC1V0 0x00000100 -+/* Disable -+#define CLKS_DCDC1V0_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_DCDC1V0_EN 0x00000100 -+/** TRC2MEM Clock Enable -+ Shows the clock enable bit for the TRC2MEM domain. This domain contains the TRC2MEM block. */ -+#define CLKS_TRC2MEM 0x00000040 -+/* Disable -+#define CLKS_TRC2MEM_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_TRC2MEM_EN 0x00000040 -+/** DDR Clock Enable -+ Shows the clock enable bit for the DDR domain. This domain contains the DDR interface block. */ -+#define CLKS_DDR 0x00000020 -+/* Disable -+#define CLKS_DDR_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_DDR_EN 0x00000020 -+/** EBU Clock Enable -+ Shows the clock enable bit for the EBU domain. This domain contains the EBU interface block. */ -+#define CLKS_EBU 0x00000010 -+/* Disable -+#define CLKS_EBU_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_EBU_EN 0x00000010 -+ -+/* Fields of "Clock Enable Register" */ -+/** Set Clock Enable STATUS -+ Sets the clock enable bit of the STATUS domain. This domain contains the STATUS block. */ -+#define CLKEN_STATUS 0x80000000 -+/* No-Operation -+#define CLKEN_STATUS_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_STATUS_SET 0x80000000 -+/** Set Clock Enable SHA1 -+ Sets the clock enable bit of the SHA1 domain. This domain contains the SHA1 block. */ -+#define CLKEN_SHA1 0x40000000 -+/* No-Operation -+#define CLKEN_SHA1_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_SHA1_SET 0x40000000 -+/** Set Clock Enable AES -+ Sets the clock enable bit of the AES domain. This domain contains the AES block. */ -+#define CLKEN_AES 0x20000000 -+/* No-Operation -+#define CLKEN_AES_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_AES_SET 0x20000000 -+/** Set Clock Enable PCM -+ Sets the clock enable bit of the PCM domain. This domain contains the PCM interface block. */ -+#define CLKEN_PCM 0x10000000 -+/* No-Operation -+#define CLKEN_PCM_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_PCM_SET 0x10000000 -+/** Set Clock Enable FSCT -+ Sets the clock enable bit of the FSCT domain. This domain contains the FSCT block. */ -+#define CLKEN_FSCT 0x08000000 -+/* No-Operation -+#define CLKEN_FSCT_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_FSCT_SET 0x08000000 -+/** Set Clock Enable GPTC -+ Sets the clock enable bit of the GPTC domain. This domain contains the GPTC block. */ -+#define CLKEN_GPTC 0x04000000 -+/* No-Operation -+#define CLKEN_GPTC_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_GPTC_SET 0x04000000 -+/** Set Clock Enable MPS -+ Sets the clock enable bit of the MPS domain. This domain contains the MPS block. */ -+#define CLKEN_MPS 0x02000000 -+/* No-Operation -+#define CLKEN_MPS_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_MPS_SET 0x02000000 -+/** Set Clock Enable DFEV0 -+ Sets the clock enable bit of the DFEV0 domain. This domain contains the DFEV0 block. */ -+#define CLKEN_DFEV0 0x01000000 -+/* No-Operation -+#define CLKEN_DFEV0_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_DFEV0_SET 0x01000000 -+/** Set Clock Enable PADCTRL4 -+ Sets the clock enable bit of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ -+#define CLKEN_PADCTRL4 0x00400000 -+/* No-Operation -+#define CLKEN_PADCTRL4_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_PADCTRL4_SET 0x00400000 -+/** Set Clock Enable PADCTRL3 -+ Sets the clock enable bit of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ -+#define CLKEN_PADCTRL3 0x00200000 -+/* No-Operation -+#define CLKEN_PADCTRL3_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_PADCTRL3_SET 0x00200000 -+/** Set Clock Enable PADCTRL1 -+ Sets the clock enable bit of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ -+#define CLKEN_PADCTRL1 0x00100000 -+/* No-Operation -+#define CLKEN_PADCTRL1_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_PADCTRL1_SET 0x00100000 -+/** Set Clock Enable P4 -+ Sets the clock enable bit of the P4 domain. This domain contains the P4 instance of the GPIO block. */ -+#define CLKEN_P4 0x00040000 -+/* No-Operation -+#define CLKEN_P4_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_P4_SET 0x00040000 -+/** Set Clock Enable P3 -+ Sets the clock enable bit of the P3 domain. This domain contains the P3 instance of the GPIO block. */ -+#define CLKEN_P3 0x00020000 -+/* No-Operation -+#define CLKEN_P3_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_P3_SET 0x00020000 -+/** Set Clock Enable P1 -+ Sets the clock enable bit of the P1 domain. This domain contains the P1 instance of the GPIO block. */ -+#define CLKEN_P1 0x00010000 -+/* No-Operation -+#define CLKEN_P1_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_P1_SET 0x00010000 -+/** Set Clock Enable HOST -+ Sets the clock enable bit of the HOST domain. This domain contains the HOST interface block. */ -+#define CLKEN_HOST 0x00008000 -+/* No-Operation -+#define CLKEN_HOST_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_HOST_SET 0x00008000 -+/** Set Clock Enable I2C -+ Sets the clock enable bit of the I2C domain. This domain contains the I2C interface block. */ -+#define CLKEN_I2C 0x00004000 -+/* No-Operation -+#define CLKEN_I2C_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_I2C_SET 0x00004000 -+/** Set Clock Enable SSC0 -+ Sets the clock enable bit of the SSC0 domain. This domain contains the SSC0 interface block. */ -+#define CLKEN_SSC0 0x00002000 -+/* No-Operation -+#define CLKEN_SSC0_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_SSC0_SET 0x00002000 -+/** Set Clock Enable ASC0 -+ Sets the clock enable bit of the ASC0 domain. This domain contains the ASC0 interface block. */ -+#define CLKEN_ASC0 0x00001000 -+/* No-Operation -+#define CLKEN_ASC0_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_ASC0_SET 0x00001000 -+/** Set Clock Enable ASC1 -+ Sets the clock enable bit of the ASC1 domain. This domain contains the ASC1 block. */ -+#define CLKEN_ASC1 0x00000800 -+/* No-Operation -+#define CLKEN_ASC1_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_ASC1_SET 0x00000800 -+/** Set Clock Enable DCDCAPD -+ Sets the clock enable bit of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ -+#define CLKEN_DCDCAPD 0x00000400 -+/* No-Operation -+#define CLKEN_DCDCAPD_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_DCDCAPD_SET 0x00000400 -+/** Set Clock Enable DCDCDDR -+ Sets the clock enable bit of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ -+#define CLKEN_DCDCDDR 0x00000200 -+/* No-Operation -+#define CLKEN_DCDCDDR_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_DCDCDDR_SET 0x00000200 -+/** Set Clock Enable DCDC1V0 -+ Sets the clock enable bit of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ -+#define CLKEN_DCDC1V0 0x00000100 -+/* No-Operation -+#define CLKEN_DCDC1V0_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_DCDC1V0_SET 0x00000100 -+/** Set Clock Enable TRC2MEM -+ Sets the clock enable bit of the TRC2MEM domain. This domain contains the TRC2MEM block. */ -+#define CLKEN_TRC2MEM 0x00000040 -+/* No-Operation -+#define CLKEN_TRC2MEM_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_TRC2MEM_SET 0x00000040 -+/** Set Clock Enable DDR -+ Sets the clock enable bit of the DDR domain. This domain contains the DDR interface block. */ -+#define CLKEN_DDR 0x00000020 -+/* No-Operation -+#define CLKEN_DDR_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_DDR_SET 0x00000020 -+/** Set Clock Enable EBU -+ Sets the clock enable bit of the EBU domain. This domain contains the EBU interface block. */ -+#define CLKEN_EBU 0x00000010 -+/* No-Operation -+#define CLKEN_EBU_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_EBU_SET 0x00000010 -+ -+/* Fields of "Clock Clear Register" */ -+/** Clear Clock Enable STATUS -+ Clears the clock enable bit of the STATUS domain. This domain contains the STATUS block. */ -+#define CLKCLR_STATUS 0x80000000 -+/* No-Operation -+#define CLKCLR_STATUS_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_STATUS_CLR 0x80000000 -+/** Clear Clock Enable SHA1 -+ Clears the clock enable bit of the SHA1 domain. This domain contains the SHA1 block. */ -+#define CLKCLR_SHA1 0x40000000 -+/* No-Operation -+#define CLKCLR_SHA1_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_SHA1_CLR 0x40000000 -+/** Clear Clock Enable AES -+ Clears the clock enable bit of the AES domain. This domain contains the AES block. */ -+#define CLKCLR_AES 0x20000000 -+/* No-Operation -+#define CLKCLR_AES_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_AES_CLR 0x20000000 -+/** Clear Clock Enable PCM -+ Clears the clock enable bit of the PCM domain. This domain contains the PCM interface block. */ -+#define CLKCLR_PCM 0x10000000 -+/* No-Operation -+#define CLKCLR_PCM_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_PCM_CLR 0x10000000 -+/** Clear Clock Enable FSCT -+ Clears the clock enable bit of the FSCT domain. This domain contains the FSCT block. */ -+#define CLKCLR_FSCT 0x08000000 -+/* No-Operation -+#define CLKCLR_FSCT_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_FSCT_CLR 0x08000000 -+/** Clear Clock Enable GPTC -+ Clears the clock enable bit of the GPTC domain. This domain contains the GPTC block. */ -+#define CLKCLR_GPTC 0x04000000 -+/* No-Operation -+#define CLKCLR_GPTC_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_GPTC_CLR 0x04000000 -+/** Clear Clock Enable MPS -+ Clears the clock enable bit of the MPS domain. This domain contains the MPS block. */ -+#define CLKCLR_MPS 0x02000000 -+/* No-Operation -+#define CLKCLR_MPS_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_MPS_CLR 0x02000000 -+/** Clear Clock Enable DFEV0 -+ Clears the clock enable bit of the DFEV0 domain. This domain contains the DFEV0 block. */ -+#define CLKCLR_DFEV0 0x01000000 -+/* No-Operation -+#define CLKCLR_DFEV0_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_DFEV0_CLR 0x01000000 -+/** Clear Clock Enable PADCTRL4 -+ Clears the clock enable bit of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ -+#define CLKCLR_PADCTRL4 0x00400000 -+/* No-Operation -+#define CLKCLR_PADCTRL4_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_PADCTRL4_CLR 0x00400000 -+/** Clear Clock Enable PADCTRL3 -+ Clears the clock enable bit of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ -+#define CLKCLR_PADCTRL3 0x00200000 -+/* No-Operation -+#define CLKCLR_PADCTRL3_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_PADCTRL3_CLR 0x00200000 -+/** Clear Clock Enable PADCTRL1 -+ Clears the clock enable bit of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ -+#define CLKCLR_PADCTRL1 0x00100000 -+/* No-Operation -+#define CLKCLR_PADCTRL1_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_PADCTRL1_CLR 0x00100000 -+/** Clear Clock Enable P4 -+ Clears the clock enable bit of the P4 domain. This domain contains the P4 instance of the GPIO block. */ -+#define CLKCLR_P4 0x00040000 -+/* No-Operation -+#define CLKCLR_P4_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_P4_CLR 0x00040000 -+/** Clear Clock Enable P3 -+ Clears the clock enable bit of the P3 domain. This domain contains the P3 instance of the GPIO block. */ -+#define CLKCLR_P3 0x00020000 -+/* No-Operation -+#define CLKCLR_P3_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_P3_CLR 0x00020000 -+/** Clear Clock Enable P1 -+ Clears the clock enable bit of the P1 domain. This domain contains the P1 instance of the GPIO block. */ -+#define CLKCLR_P1 0x00010000 -+/* No-Operation -+#define CLKCLR_P1_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_P1_CLR 0x00010000 -+/** Clear Clock Enable HOST -+ Clears the clock enable bit of the HOST domain. This domain contains the HOST interface block. */ -+#define CLKCLR_HOST 0x00008000 -+/* No-Operation -+#define CLKCLR_HOST_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_HOST_CLR 0x00008000 -+/** Clear Clock Enable I2C -+ Clears the clock enable bit of the I2C domain. This domain contains the I2C interface block. */ -+#define CLKCLR_I2C 0x00004000 -+/* No-Operation -+#define CLKCLR_I2C_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_I2C_CLR 0x00004000 -+/** Clear Clock Enable SSC0 -+ Clears the clock enable bit of the SSC0 domain. This domain contains the SSC0 interface block. */ -+#define CLKCLR_SSC0 0x00002000 -+/* No-Operation -+#define CLKCLR_SSC0_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_SSC0_CLR 0x00002000 -+/** Clear Clock Enable ASC0 -+ Clears the clock enable bit of the ASC0 domain. This domain contains the ASC0 interface block. */ -+#define CLKCLR_ASC0 0x00001000 -+/* No-Operation -+#define CLKCLR_ASC0_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_ASC0_CLR 0x00001000 -+/** Clear Clock Enable ASC1 -+ Clears the clock enable bit of the ASC1 domain. This domain contains the ASC1 block. */ -+#define CLKCLR_ASC1 0x00000800 -+/* No-Operation -+#define CLKCLR_ASC1_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_ASC1_CLR 0x00000800 -+/** Clear Clock Enable DCDCAPD -+ Clears the clock enable bit of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ -+#define CLKCLR_DCDCAPD 0x00000400 -+/* No-Operation -+#define CLKCLR_DCDCAPD_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_DCDCAPD_CLR 0x00000400 -+/** Clear Clock Enable DCDCDDR -+ Clears the clock enable bit of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ -+#define CLKCLR_DCDCDDR 0x00000200 -+/* No-Operation -+#define CLKCLR_DCDCDDR_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_DCDCDDR_CLR 0x00000200 -+/** Clear Clock Enable DCDC1V0 -+ Clears the clock enable bit of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ -+#define CLKCLR_DCDC1V0 0x00000100 -+/* No-Operation -+#define CLKCLR_DCDC1V0_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_DCDC1V0_CLR 0x00000100 -+/** Clear Clock Enable TRC2MEM -+ Clears the clock enable bit of the TRC2MEM domain. This domain contains the TRC2MEM block. */ -+#define CLKCLR_TRC2MEM 0x00000040 -+/* No-Operation -+#define CLKCLR_TRC2MEM_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_TRC2MEM_CLR 0x00000040 -+/** Clear Clock Enable DDR -+ Clears the clock enable bit of the DDR domain. This domain contains the DDR interface block. */ -+#define CLKCLR_DDR 0x00000020 -+/* No-Operation -+#define CLKCLR_DDR_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_DDR_CLR 0x00000020 -+/** Clear Clock Enable EBU -+ Clears the clock enable bit of the EBU domain. This domain contains the EBU interface block. */ -+#define CLKCLR_EBU 0x00000010 -+/* No-Operation -+#define CLKCLR_EBU_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_EBU_CLR 0x00000010 -+ -+/* Fields of "Activation Status Register" */ -+/** STATUS Status -+ Shows the activation status of the STATUS domain. This domain contains the STATUS block. */ -+#define ACTS_STATUS 0x80000000 -+/* The block is inactive. -+#define ACTS_STATUS_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_STATUS_ACT 0x80000000 -+/** SHA1 Status -+ Shows the activation status of the SHA1 domain. This domain contains the SHA1 block. */ -+#define ACTS_SHA1 0x40000000 -+/* The block is inactive. -+#define ACTS_SHA1_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_SHA1_ACT 0x40000000 -+/** AES Status -+ Shows the activation status of the AES domain. This domain contains the AES block. */ -+#define ACTS_AES 0x20000000 -+/* The block is inactive. -+#define ACTS_AES_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_AES_ACT 0x20000000 -+/** PCM Status -+ Shows the activation status of the PCM domain. This domain contains the PCM interface block. */ -+#define ACTS_PCM 0x10000000 -+/* The block is inactive. -+#define ACTS_PCM_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_PCM_ACT 0x10000000 -+/** FSCT Status -+ Shows the activation status of the FSCT domain. This domain contains the FSCT block. */ -+#define ACTS_FSCT 0x08000000 -+/* The block is inactive. -+#define ACTS_FSCT_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_FSCT_ACT 0x08000000 -+/** GPTC Status -+ Shows the activation status of the GPTC domain. This domain contains the GPTC block. */ -+#define ACTS_GPTC 0x04000000 -+/* The block is inactive. -+#define ACTS_GPTC_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_GPTC_ACT 0x04000000 -+/** MPS Status -+ Shows the activation status of the MPS domain. This domain contains the MPS block. */ -+#define ACTS_MPS 0x02000000 -+/* The block is inactive. -+#define ACTS_MPS_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_MPS_ACT 0x02000000 -+/** DFEV0 Status -+ Shows the activation status of the DFEV0 domain. This domain contains the DFEV0 block. */ -+#define ACTS_DFEV0 0x01000000 -+/* The block is inactive. -+#define ACTS_DFEV0_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_DFEV0_ACT 0x01000000 -+/** PADCTRL4 Status -+ Shows the activation status of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ -+#define ACTS_PADCTRL4 0x00400000 -+/* The block is inactive. -+#define ACTS_PADCTRL4_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_PADCTRL4_ACT 0x00400000 -+/** PADCTRL3 Status -+ Shows the activation status of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ -+#define ACTS_PADCTRL3 0x00200000 -+/* The block is inactive. -+#define ACTS_PADCTRL3_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_PADCTRL3_ACT 0x00200000 -+/** PADCTRL1 Status -+ Shows the activation status of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ -+#define ACTS_PADCTRL1 0x00100000 -+/* The block is inactive. -+#define ACTS_PADCTRL1_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_PADCTRL1_ACT 0x00100000 -+/** P4 Status -+ Shows the activation status of the P4 domain. This domain contains the P4 instance of the GPIO block. */ -+#define ACTS_P4 0x00040000 -+/* The block is inactive. -+#define ACTS_P4_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_P4_ACT 0x00040000 -+/** P3 Status -+ Shows the activation status of the P3 domain. This domain contains the P3 instance of the GPIO block. */ -+#define ACTS_P3 0x00020000 -+/* The block is inactive. -+#define ACTS_P3_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_P3_ACT 0x00020000 -+/** P1 Status -+ Shows the activation status of the P1 domain. This domain contains the P1 instance of the GPIO block. */ -+#define ACTS_P1 0x00010000 -+/* The block is inactive. -+#define ACTS_P1_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_P1_ACT 0x00010000 -+/** HOST Status -+ Shows the activation status of the HOST domain. This domain contains the HOST interface block. */ -+#define ACTS_HOST 0x00008000 -+/* The block is inactive. -+#define ACTS_HOST_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_HOST_ACT 0x00008000 -+/** I2C Status -+ Shows the activation status of the I2C domain. This domain contains the I2C interface block. */ -+#define ACTS_I2C 0x00004000 -+/* The block is inactive. -+#define ACTS_I2C_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_I2C_ACT 0x00004000 -+/** SSC0 Status -+ Shows the activation status of the SSC0 domain. This domain contains the SSC0 interface block. */ -+#define ACTS_SSC0 0x00002000 -+/* The block is inactive. -+#define ACTS_SSC0_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_SSC0_ACT 0x00002000 -+/** ASC0 Status -+ Shows the activation status of the ASC0 domain. This domain contains the ASC0 interface block. */ -+#define ACTS_ASC0 0x00001000 -+/* The block is inactive. -+#define ACTS_ASC0_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_ASC0_ACT 0x00001000 -+/** ASC1 Status -+ Shows the activation status of the ASC1 domain. This domain contains the ASC1 block. */ -+#define ACTS_ASC1 0x00000800 -+/* The block is inactive. -+#define ACTS_ASC1_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_ASC1_ACT 0x00000800 -+/** DCDCAPD Status -+ Shows the activation status of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ -+#define ACTS_DCDCAPD 0x00000400 -+/* The block is inactive. -+#define ACTS_DCDCAPD_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_DCDCAPD_ACT 0x00000400 -+/** DCDCDDR Status -+ Shows the activation status of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ -+#define ACTS_DCDCDDR 0x00000200 -+/* The block is inactive. -+#define ACTS_DCDCDDR_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_DCDCDDR_ACT 0x00000200 -+/** DCDC1V0 Status -+ Shows the activation status of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ -+#define ACTS_DCDC1V0 0x00000100 -+/* The block is inactive. -+#define ACTS_DCDC1V0_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_DCDC1V0_ACT 0x00000100 -+/** TRC2MEM Status -+ Shows the activation status of the TRC2MEM domain. This domain contains the TRC2MEM block. */ -+#define ACTS_TRC2MEM 0x00000040 -+/* The block is inactive. -+#define ACTS_TRC2MEM_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_TRC2MEM_ACT 0x00000040 -+/** DDR Status -+ Shows the activation status of the DDR domain. This domain contains the DDR interface block. */ -+#define ACTS_DDR 0x00000020 -+/* The block is inactive. -+#define ACTS_DDR_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_DDR_ACT 0x00000020 -+/** EBU Status -+ Shows the activation status of the EBU domain. This domain contains the EBU interface block. */ -+#define ACTS_EBU 0x00000010 -+/* The block is inactive. -+#define ACTS_EBU_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_EBU_ACT 0x00000010 -+ -+/* Fields of "Activation Register" */ -+/** Activate STATUS -+ Sets the activation flag of the STATUS domain. This domain contains the STATUS block. */ -+#define ACT_STATUS 0x80000000 -+/* No-Operation -+#define ACT_STATUS_NOP 0x00000000 */ -+/** Set */ -+#define ACT_STATUS_SET 0x80000000 -+/** Activate SHA1 -+ Sets the activation flag of the SHA1 domain. This domain contains the SHA1 block. */ -+#define ACT_SHA1 0x40000000 -+/* No-Operation -+#define ACT_SHA1_NOP 0x00000000 */ -+/** Set */ -+#define ACT_SHA1_SET 0x40000000 -+/** Activate AES -+ Sets the activation flag of the AES domain. This domain contains the AES block. */ -+#define ACT_AES 0x20000000 -+/* No-Operation -+#define ACT_AES_NOP 0x00000000 */ -+/** Set */ -+#define ACT_AES_SET 0x20000000 -+/** Activate PCM -+ Sets the activation flag of the PCM domain. This domain contains the PCM interface block. */ -+#define ACT_PCM 0x10000000 -+/* No-Operation -+#define ACT_PCM_NOP 0x00000000 */ -+/** Set */ -+#define ACT_PCM_SET 0x10000000 -+/** Activate FSCT -+ Sets the activation flag of the FSCT domain. This domain contains the FSCT block. */ -+#define ACT_FSCT 0x08000000 -+/* No-Operation -+#define ACT_FSCT_NOP 0x00000000 */ -+/** Set */ -+#define ACT_FSCT_SET 0x08000000 -+/** Activate GPTC -+ Sets the activation flag of the GPTC domain. This domain contains the GPTC block. */ -+#define ACT_GPTC 0x04000000 -+/* No-Operation -+#define ACT_GPTC_NOP 0x00000000 */ -+/** Set */ -+#define ACT_GPTC_SET 0x04000000 -+/** Activate MPS -+ Sets the activation flag of the MPS domain. This domain contains the MPS block. */ -+#define ACT_MPS 0x02000000 -+/* No-Operation -+#define ACT_MPS_NOP 0x00000000 */ -+/** Set */ -+#define ACT_MPS_SET 0x02000000 -+/** Activate DFEV0 -+ Sets the activation flag of the DFEV0 domain. This domain contains the DFEV0 block. */ -+#define ACT_DFEV0 0x01000000 -+/* No-Operation -+#define ACT_DFEV0_NOP 0x00000000 */ -+/** Set */ -+#define ACT_DFEV0_SET 0x01000000 -+/** Activate PADCTRL4 -+ Sets the activation flag of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ -+#define ACT_PADCTRL4 0x00400000 -+/* No-Operation -+#define ACT_PADCTRL4_NOP 0x00000000 */ -+/** Set */ -+#define ACT_PADCTRL4_SET 0x00400000 -+/** Activate PADCTRL3 -+ Sets the activation flag of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ -+#define ACT_PADCTRL3 0x00200000 -+/* No-Operation -+#define ACT_PADCTRL3_NOP 0x00000000 */ -+/** Set */ -+#define ACT_PADCTRL3_SET 0x00200000 -+/** Activate PADCTRL1 -+ Sets the activation flag of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ -+#define ACT_PADCTRL1 0x00100000 -+/* No-Operation -+#define ACT_PADCTRL1_NOP 0x00000000 */ -+/** Set */ -+#define ACT_PADCTRL1_SET 0x00100000 -+/** Activate P4 -+ Sets the activation flag of the P4 domain. This domain contains the P4 instance of the GPIO block. */ -+#define ACT_P4 0x00040000 -+/* No-Operation -+#define ACT_P4_NOP 0x00000000 */ -+/** Set */ -+#define ACT_P4_SET 0x00040000 -+/** Activate P3 -+ Sets the activation flag of the P3 domain. This domain contains the P3 instance of the GPIO block. */ -+#define ACT_P3 0x00020000 -+/* No-Operation -+#define ACT_P3_NOP 0x00000000 */ -+/** Set */ -+#define ACT_P3_SET 0x00020000 -+/** Activate P1 -+ Sets the activation flag of the P1 domain. This domain contains the P1 instance of the GPIO block. */ -+#define ACT_P1 0x00010000 -+/* No-Operation -+#define ACT_P1_NOP 0x00000000 */ -+/** Set */ -+#define ACT_P1_SET 0x00010000 -+/** Activate HOST -+ Sets the activation flag of the HOST domain. This domain contains the HOST interface block. */ -+#define ACT_HOST 0x00008000 -+/* No-Operation -+#define ACT_HOST_NOP 0x00000000 */ -+/** Set */ -+#define ACT_HOST_SET 0x00008000 -+/** Activate I2C -+ Sets the activation flag of the I2C domain. This domain contains the I2C interface block. */ -+#define ACT_I2C 0x00004000 -+/* No-Operation -+#define ACT_I2C_NOP 0x00000000 */ -+/** Set */ -+#define ACT_I2C_SET 0x00004000 -+/** Activate SSC0 -+ Sets the activation flag of the SSC0 domain. This domain contains the SSC0 interface block. */ -+#define ACT_SSC0 0x00002000 -+/* No-Operation -+#define ACT_SSC0_NOP 0x00000000 */ -+/** Set */ -+#define ACT_SSC0_SET 0x00002000 -+/** Activate ASC0 -+ Sets the activation flag of the ASC0 domain. This domain contains the ASC0 interface block. */ -+#define ACT_ASC0 0x00001000 -+/* No-Operation -+#define ACT_ASC0_NOP 0x00000000 */ -+/** Set */ -+#define ACT_ASC0_SET 0x00001000 -+/** Activate ASC1 -+ Sets the activation flag of the ASC1 domain. This domain contains the ASC1 block. */ -+#define ACT_ASC1 0x00000800 -+/* No-Operation -+#define ACT_ASC1_NOP 0x00000000 */ -+/** Set */ -+#define ACT_ASC1_SET 0x00000800 -+/** Activate DCDCAPD -+ Sets the activation flag of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ -+#define ACT_DCDCAPD 0x00000400 -+/* No-Operation -+#define ACT_DCDCAPD_NOP 0x00000000 */ -+/** Set */ -+#define ACT_DCDCAPD_SET 0x00000400 -+/** Activate DCDCDDR -+ Sets the activation flag of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ -+#define ACT_DCDCDDR 0x00000200 -+/* No-Operation -+#define ACT_DCDCDDR_NOP 0x00000000 */ -+/** Set */ -+#define ACT_DCDCDDR_SET 0x00000200 -+/** Activate DCDC1V0 -+ Sets the activation flag of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ -+#define ACT_DCDC1V0 0x00000100 -+/* No-Operation -+#define ACT_DCDC1V0_NOP 0x00000000 */ -+/** Set */ -+#define ACT_DCDC1V0_SET 0x00000100 -+/** Activate TRC2MEM -+ Sets the activation flag of the TRC2MEM domain. This domain contains the TRC2MEM block. */ -+#define ACT_TRC2MEM 0x00000040 -+/* No-Operation -+#define ACT_TRC2MEM_NOP 0x00000000 */ -+/** Set */ -+#define ACT_TRC2MEM_SET 0x00000040 -+/** Activate DDR -+ Sets the activation flag of the DDR domain. This domain contains the DDR interface block. */ -+#define ACT_DDR 0x00000020 -+/* No-Operation -+#define ACT_DDR_NOP 0x00000000 */ -+/** Set */ -+#define ACT_DDR_SET 0x00000020 -+/** Activate EBU -+ Sets the activation flag of the EBU domain. This domain contains the EBU interface block. */ -+#define ACT_EBU 0x00000010 -+/* No-Operation -+#define ACT_EBU_NOP 0x00000000 */ -+/** Set */ -+#define ACT_EBU_SET 0x00000010 -+ -+/* Fields of "Deactivation Register" */ -+/** Deactivate STATUS -+ Clears the activation flag of the STATUS domain. This domain contains the STATUS block. */ -+#define DEACT_STATUS 0x80000000 -+/* No-Operation -+#define DEACT_STATUS_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_STATUS_CLR 0x80000000 -+/** Deactivate SHA1 -+ Clears the activation flag of the SHA1 domain. This domain contains the SHA1 block. */ -+#define DEACT_SHA1 0x40000000 -+/* No-Operation -+#define DEACT_SHA1_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_SHA1_CLR 0x40000000 -+/** Deactivate AES -+ Clears the activation flag of the AES domain. This domain contains the AES block. */ -+#define DEACT_AES 0x20000000 -+/* No-Operation -+#define DEACT_AES_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_AES_CLR 0x20000000 -+/** Deactivate PCM -+ Clears the activation flag of the PCM domain. This domain contains the PCM interface block. */ -+#define DEACT_PCM 0x10000000 -+/* No-Operation -+#define DEACT_PCM_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_PCM_CLR 0x10000000 -+/** Deactivate FSCT -+ Clears the activation flag of the FSCT domain. This domain contains the FSCT block. */ -+#define DEACT_FSCT 0x08000000 -+/* No-Operation -+#define DEACT_FSCT_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_FSCT_CLR 0x08000000 -+/** Deactivate GPTC -+ Clears the activation flag of the GPTC domain. This domain contains the GPTC block. */ -+#define DEACT_GPTC 0x04000000 -+/* No-Operation -+#define DEACT_GPTC_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_GPTC_CLR 0x04000000 -+/** Deactivate MPS -+ Clears the activation flag of the MPS domain. This domain contains the MPS block. */ -+#define DEACT_MPS 0x02000000 -+/* No-Operation -+#define DEACT_MPS_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_MPS_CLR 0x02000000 -+/** Deactivate DFEV0 -+ Clears the activation flag of the DFEV0 domain. This domain contains the DFEV0 block. */ -+#define DEACT_DFEV0 0x01000000 -+/* No-Operation -+#define DEACT_DFEV0_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_DFEV0_CLR 0x01000000 -+/** Deactivate PADCTRL4 -+ Clears the activation flag of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ -+#define DEACT_PADCTRL4 0x00400000 -+/* No-Operation -+#define DEACT_PADCTRL4_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_PADCTRL4_CLR 0x00400000 -+/** Deactivate PADCTRL3 -+ Clears the activation flag of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ -+#define DEACT_PADCTRL3 0x00200000 -+/* No-Operation -+#define DEACT_PADCTRL3_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_PADCTRL3_CLR 0x00200000 -+/** Deactivate PADCTRL1 -+ Clears the activation flag of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ -+#define DEACT_PADCTRL1 0x00100000 -+/* No-Operation -+#define DEACT_PADCTRL1_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_PADCTRL1_CLR 0x00100000 -+/** Deactivate P4 -+ Clears the activation flag of the P4 domain. This domain contains the P4 instance of the GPIO block. */ -+#define DEACT_P4 0x00040000 -+/* No-Operation -+#define DEACT_P4_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_P4_CLR 0x00040000 -+/** Deactivate P3 -+ Clears the activation flag of the P3 domain. This domain contains the P3 instance of the GPIO block. */ -+#define DEACT_P3 0x00020000 -+/* No-Operation -+#define DEACT_P3_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_P3_CLR 0x00020000 -+/** Deactivate P1 -+ Clears the activation flag of the P1 domain. This domain contains the P1 instance of the GPIO block. */ -+#define DEACT_P1 0x00010000 -+/* No-Operation -+#define DEACT_P1_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_P1_CLR 0x00010000 -+/** Deactivate HOST -+ Clears the activation flag of the HOST domain. This domain contains the HOST interface block. */ -+#define DEACT_HOST 0x00008000 -+/* No-Operation -+#define DEACT_HOST_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_HOST_CLR 0x00008000 -+/** Deactivate I2C -+ Clears the activation flag of the I2C domain. This domain contains the I2C interface block. */ -+#define DEACT_I2C 0x00004000 -+/* No-Operation -+#define DEACT_I2C_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_I2C_CLR 0x00004000 -+/** Deactivate SSC0 -+ Clears the activation flag of the SSC0 domain. This domain contains the SSC0 interface block. */ -+#define DEACT_SSC0 0x00002000 -+/* No-Operation -+#define DEACT_SSC0_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_SSC0_CLR 0x00002000 -+/** Deactivate ASC0 -+ Clears the activation flag of the ASC0 domain. This domain contains the ASC0 interface block. */ -+#define DEACT_ASC0 0x00001000 -+/* No-Operation -+#define DEACT_ASC0_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_ASC0_CLR 0x00001000 -+/** Deactivate ASC1 -+ Clears the activation flag of the ASC1 domain. This domain contains the ASC1 block. */ -+#define DEACT_ASC1 0x00000800 -+/* No-Operation -+#define DEACT_ASC1_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_ASC1_CLR 0x00000800 -+/** Deactivate DCDCAPD -+ Clears the activation flag of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ -+#define DEACT_DCDCAPD 0x00000400 -+/* No-Operation -+#define DEACT_DCDCAPD_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_DCDCAPD_CLR 0x00000400 -+/** Deactivate DCDCDDR -+ Clears the activation flag of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ -+#define DEACT_DCDCDDR 0x00000200 -+/* No-Operation -+#define DEACT_DCDCDDR_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_DCDCDDR_CLR 0x00000200 -+/** Deactivate DCDC1V0 -+ Clears the activation flag of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ -+#define DEACT_DCDC1V0 0x00000100 -+/* No-Operation -+#define DEACT_DCDC1V0_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_DCDC1V0_CLR 0x00000100 -+/** Deactivate TRC2MEM -+ Clears the activation flag of the TRC2MEM domain. This domain contains the TRC2MEM block. */ -+#define DEACT_TRC2MEM 0x00000040 -+/* No-Operation -+#define DEACT_TRC2MEM_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_TRC2MEM_CLR 0x00000040 -+/** Deactivate DDR -+ Clears the activation flag of the DDR domain. This domain contains the DDR interface block. */ -+#define DEACT_DDR 0x00000020 -+/* No-Operation -+#define DEACT_DDR_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_DDR_CLR 0x00000020 -+/** Deactivate EBU -+ Clears the activation flag of the EBU domain. This domain contains the EBU interface block. */ -+#define DEACT_EBU 0x00000010 -+/* No-Operation -+#define DEACT_EBU_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_EBU_CLR 0x00000010 -+ -+/* Fields of "Reboot Trigger Register" */ -+/** Reboot STATUS -+ Triggers a reboot of the STATUS domain. This domain contains the STATUS block. */ -+#define RBT_STATUS 0x80000000 -+/* No-Operation -+#define RBT_STATUS_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_STATUS_TRIG 0x80000000 -+/** Reboot SHA1 -+ Triggers a reboot of the SHA1 domain. This domain contains the SHA1 block. */ -+#define RBT_SHA1 0x40000000 -+/* No-Operation -+#define RBT_SHA1_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_SHA1_TRIG 0x40000000 -+/** Reboot AES -+ Triggers a reboot of the AES domain. This domain contains the AES block. */ -+#define RBT_AES 0x20000000 -+/* No-Operation -+#define RBT_AES_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_AES_TRIG 0x20000000 -+/** Reboot PCM -+ Triggers a reboot of the PCM domain. This domain contains the PCM interface block. */ -+#define RBT_PCM 0x10000000 -+/* No-Operation -+#define RBT_PCM_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_PCM_TRIG 0x10000000 -+/** Reboot FSCT -+ Triggers a reboot of the FSCT domain. This domain contains the FSCT block. */ -+#define RBT_FSCT 0x08000000 -+/* No-Operation -+#define RBT_FSCT_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_FSCT_TRIG 0x08000000 -+/** Reboot GPTC -+ Triggers a reboot of the GPTC domain. This domain contains the GPTC block. */ -+#define RBT_GPTC 0x04000000 -+/* No-Operation -+#define RBT_GPTC_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_GPTC_TRIG 0x04000000 -+/** Reboot MPS -+ Triggers a reboot of the MPS domain. This domain contains the MPS block. */ -+#define RBT_MPS 0x02000000 -+/* No-Operation -+#define RBT_MPS_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_MPS_TRIG 0x02000000 -+/** Reboot DFEV0 -+ Triggers a reboot of the DFEV0 domain. This domain contains the DFEV0 block. */ -+#define RBT_DFEV0 0x01000000 -+/* No-Operation -+#define RBT_DFEV0_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_DFEV0_TRIG 0x01000000 -+/** Reboot PADCTRL4 -+ Triggers a reboot of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ -+#define RBT_PADCTRL4 0x00400000 -+/* No-Operation -+#define RBT_PADCTRL4_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_PADCTRL4_TRIG 0x00400000 -+/** Reboot PADCTRL3 -+ Triggers a reboot of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ -+#define RBT_PADCTRL3 0x00200000 -+/* No-Operation -+#define RBT_PADCTRL3_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_PADCTRL3_TRIG 0x00200000 -+/** Reboot PADCTRL1 -+ Triggers a reboot of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ -+#define RBT_PADCTRL1 0x00100000 -+/* No-Operation -+#define RBT_PADCTRL1_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_PADCTRL1_TRIG 0x00100000 -+/** Reboot P4 -+ Triggers a reboot of the P4 domain. This domain contains the P4 instance of the GPIO block. */ -+#define RBT_P4 0x00040000 -+/* No-Operation -+#define RBT_P4_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_P4_TRIG 0x00040000 -+/** Reboot P3 -+ Triggers a reboot of the P3 domain. This domain contains the P3 instance of the GPIO block. */ -+#define RBT_P3 0x00020000 -+/* No-Operation -+#define RBT_P3_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_P3_TRIG 0x00020000 -+/** Reboot P1 -+ Triggers a reboot of the P1 domain. This domain contains the P1 instance of the GPIO block. */ -+#define RBT_P1 0x00010000 -+/* No-Operation -+#define RBT_P1_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_P1_TRIG 0x00010000 -+/** Reboot HOST -+ Triggers a reboot of the HOST domain. This domain contains the HOST interface block. */ -+#define RBT_HOST 0x00008000 -+/* No-Operation -+#define RBT_HOST_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_HOST_TRIG 0x00008000 -+/** Reboot I2C -+ Triggers a reboot of the I2C domain. This domain contains the I2C interface block. */ -+#define RBT_I2C 0x00004000 -+/* No-Operation -+#define RBT_I2C_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_I2C_TRIG 0x00004000 -+/** Reboot SSC0 -+ Triggers a reboot of the SSC0 domain. This domain contains the SSC0 interface block. */ -+#define RBT_SSC0 0x00002000 -+/* No-Operation -+#define RBT_SSC0_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_SSC0_TRIG 0x00002000 -+/** Reboot ASC0 -+ Triggers a reboot of the ASC0 domain. This domain contains the ASC0 interface block. */ -+#define RBT_ASC0 0x00001000 -+/* No-Operation -+#define RBT_ASC0_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_ASC0_TRIG 0x00001000 -+/** Reboot ASC1 -+ Triggers a reboot of the ASC1 domain. This domain contains the ASC1 block. */ -+#define RBT_ASC1 0x00000800 -+/* No-Operation -+#define RBT_ASC1_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_ASC1_TRIG 0x00000800 -+/** Reboot DCDCAPD -+ Triggers a reboot of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ -+#define RBT_DCDCAPD 0x00000400 -+/* No-Operation -+#define RBT_DCDCAPD_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_DCDCAPD_TRIG 0x00000400 -+/** Reboot DCDCDDR -+ Triggers a reboot of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ -+#define RBT_DCDCDDR 0x00000200 -+/* No-Operation -+#define RBT_DCDCDDR_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_DCDCDDR_TRIG 0x00000200 -+/** Reboot DCDC1V0 -+ Triggers a reboot of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ -+#define RBT_DCDC1V0 0x00000100 -+/* No-Operation -+#define RBT_DCDC1V0_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_DCDC1V0_TRIG 0x00000100 -+/** Reboot TRC2MEM -+ Triggers a reboot of the TRC2MEM domain. This domain contains the TRC2MEM block. */ -+#define RBT_TRC2MEM 0x00000040 -+/* No-Operation -+#define RBT_TRC2MEM_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_TRC2MEM_TRIG 0x00000040 -+/** Reboot DDR -+ Triggers a reboot of the DDR domain. This domain contains the DDR interface block. */ -+#define RBT_DDR 0x00000020 -+/* No-Operation -+#define RBT_DDR_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_DDR_TRIG 0x00000020 -+/** Reboot EBU -+ Triggers a reboot of the EBU domain. This domain contains the EBU interface block. */ -+#define RBT_EBU 0x00000010 -+/* No-Operation -+#define RBT_EBU_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_EBU_TRIG 0x00000010 -+/** Reboot XBAR -+ Triggers a reboot of the XBAR. */ -+#define RBT_XBAR 0x00000002 -+/* No-Operation -+#define RBT_XBAR_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_XBAR_TRIG 0x00000002 -+/** Reboot CPU -+ Triggers a reboot of the CPU. */ -+#define RBT_CPU 0x00000001 -+/* No-Operation -+#define RBT_CPU_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_CPU_TRIG 0x00000001 -+ -+/* Fields of "CPU0 Clock Control Register" */ -+/** CPU Clock Divider -+ Via this bit the divider and therefore the frequency of the clock of CPU0 can be selected. */ -+#define CPU0CC_CPUDIV 0x00000001 -+/* Frequency set to the nominal value. -+#define CPU0CC_CPUDIV_SELFNOM 0x00000000 */ -+/** Frequency set to half of its nominal value. */ -+#define CPU0CC_CPUDIV_SELFHALF 0x00000001 -+ -+/* Fields of "CPU0 Reset Source Register" */ -+/** Software Reboot Request Occurred -+ This bit can be acknowledged by a write operation. */ -+#define CPU0RS_SWRRO 0x00000004 -+/* Nothing -+#define CPU0RS_SWRRO_NULL 0x00000000 */ -+/** Write: Acknowledge the event. */ -+#define CPU0RS_SWRRO_EVACK 0x00000004 -+/** Read: Event occurred. */ -+#define CPU0RS_SWRRO_EVOCC 0x00000004 -+/** Hardware Reset Source -+ Reflects the root cause for the last hardware reset. The infrastructure-block is only reset in case of POR. For all other blocks there is no difference between the three HW-reset sources. */ -+#define CPU0RS_HWRS_MASK 0x00000003 -+/** field offset */ -+#define CPU0RS_HWRS_OFFSET 0 -+/** Power-on reset. */ -+#define CPU0RS_HWRS_POR 0x00000000 -+/** RST pin. */ -+#define CPU0RS_HWRS_RST 0x00000001 -+/** Watchdog reset request. */ -+#define CPU0RS_HWRS_WDT 0x00000002 -+ -+/* Fields of "CPU0 Wakeup Configuration Register" */ -+/** Wakeup Request Source Yield Resume 15 -+ Select the signal connected to the yield/resume interface pin 15 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR15 0x80000000 -+/* Not selected -+#define CPU0WCFG_WRSYR15_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR15_SEL 0x80000000 -+/** Wakeup Request Source Yield Resume 14 -+ Select the signal connected to the yield/resume interface pin 14 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR14 0x40000000 -+/* Not selected -+#define CPU0WCFG_WRSYR14_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR14_SEL 0x40000000 -+/** Wakeup Request Source Yield Resume 13 -+ Select the signal connected to the yield/resume interface pin 13 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR13 0x20000000 -+/* Not selected -+#define CPU0WCFG_WRSYR13_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR13_SEL 0x20000000 -+/** Wakeup Request Source Yield Resume 12 -+ Select the signal connected to the yield/resume interface pin 12 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR12 0x10000000 -+/* Not selected -+#define CPU0WCFG_WRSYR12_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR12_SEL 0x10000000 -+/** Wakeup Request Source Yield Resume 11 -+ Select the signal connected to the yield/resume interface pin 11 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR11 0x08000000 -+/* Not selected -+#define CPU0WCFG_WRSYR11_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR11_SEL 0x08000000 -+/** Wakeup Request Source Yield Resume 10 -+ Select the signal connected to the yield/resume interface pin 10 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR10 0x04000000 -+/* Not selected -+#define CPU0WCFG_WRSYR10_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR10_SEL 0x04000000 -+/** Wakeup Request Source Yield Resume 9 -+ Select the signal connected to the yield/resume interface pin 9 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR9 0x02000000 -+/* Not selected -+#define CPU0WCFG_WRSYR9_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR9_SEL 0x02000000 -+/** Wakeup Request Source Yield Resume 8 -+ Select the signal connected to the yield/resume interface pin 8 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR8 0x01000000 -+/* Not selected -+#define CPU0WCFG_WRSYR8_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR8_SEL 0x01000000 -+/** Wakeup Request Source Yield Resume 7 -+ Select the signal connected to the yield/resume interface pin 7 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR7 0x00800000 -+/* Not selected -+#define CPU0WCFG_WRSYR7_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR7_SEL 0x00800000 -+/** Wakeup Request Source Yield Resume 6 -+ Select the signal connected to the yield/resume interface pin 6 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR6 0x00400000 -+/* Not selected -+#define CPU0WCFG_WRSYR6_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR6_SEL 0x00400000 -+/** Wakeup Request Source Yield Resume 5 -+ Select the signal connected to the yield/resume interface pin 5 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR5 0x00200000 -+/* Not selected -+#define CPU0WCFG_WRSYR5_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR5_SEL 0x00200000 -+/** Wakeup Request Source Yield Resume 4 -+ Select the signal connected to the yield/resume interface pin 4 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR4 0x00100000 -+/* Not selected -+#define CPU0WCFG_WRSYR4_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR4_SEL 0x00100000 -+/** Wakeup Request Source Yield Resume 3 -+ Select the signal connected to the yield/resume interface pin 3 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR3 0x00080000 -+/* Not selected -+#define CPU0WCFG_WRSYR3_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR3_SEL 0x00080000 -+/** Wakeup Request Source Yield Resume 2 -+ Select the signal connected to the yield/resume interface pin 2 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR2 0x00040000 -+/* Not selected -+#define CPU0WCFG_WRSYR2_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR2_SEL 0x00040000 -+/** Wakeup Request Source Yield Resume 1 -+ Select the signal connected to the yield/resume interface pin 1 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR1 0x00020000 -+/* Not selected -+#define CPU0WCFG_WRSYR1_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR1_SEL 0x00020000 -+/** Wakeup Request Source Yield Resume 0 -+ Select the signal connected to the yield/resume interface pin 0 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR0 0x00010000 -+/* Not selected -+#define CPU0WCFG_WRSYR0_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR0_SEL 0x00010000 -+/** Wakeup Request Source Debug -+ Select signal EJ_DINT as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSDBG 0x00000100 -+/* Not selected -+#define CPU0WCFG_WRSDBG_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSDBG_SEL 0x00000100 -+/** Wakeup Request Source ICU of VPE1 -+ Select signal ICU_IRQ of VPE1 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSICUVPE1 0x00000002 -+/* Not selected -+#define CPU0WCFG_WRSICUVPE1_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSICUVPE1_SEL 0x00000002 -+/** Wakeup Request Source ICU of VPE0 -+ Select signal ICU_IRQ of VPE0 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSICUVPE0 0x00000001 -+/* Not selected -+#define CPU0WCFG_WRSICUVPE0_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSICUVPE0_SEL 0x00000001 -+ -+/* Fields of "Bootmode Control Register" */ -+/** Software Bootmode Select -+ Enables SW writing of Bootmode and shows whether or not the SW-programmed bootmode is reflected in field Bootmode instead of the hardware given value. */ -+#define BMC_BMSW 0x80000000 -+/* Disable -+#define BMC_BMSW_DIS 0x00000000 */ -+/** Enable */ -+#define BMC_BMSW_EN 0x80000000 -+/** Bootmode -+ Initially this field holds the value of the pinstraps LED_BMODEx on positions 5:0, and the value of the corresponding JTAG register bit on position 6. Writing is enabled by setting Software Bootmode Select to 1 during the write cycle. */ -+#define BMC_BM_MASK 0x0000007F -+/** field offset */ -+#define BMC_BM_OFFSET 0 -+ -+/* Fields of "Sleep Configuration Register" */ -+/** Enable XBAR Clockoff When All XBAR masters Clockoff -+ Enable XBAR clock shutdown in case all XBAR masters are in clockoff mode. This bit has no effect if bit CPU0 is not enabled. */ -+#define SCFG_XBAR 0x00010000 -+/* Disable -+#define SCFG_XBAR_DIS 0x00000000 */ -+/** Enable */ -+#define SCFG_XBAR_EN 0x00010000 -+/** CPU0 Clockoff On Sleep -+ Enable CPU0 clock shutdown in case its SI_SLEEP signal becomes active. */ -+#define SCFG_CPU0 0x00000001 -+/* Disable -+#define SCFG_CPU0_DIS 0x00000000 */ -+/** Enable */ -+#define SCFG_CPU0_EN 0x00000001 -+ -+/* Fields of "Power Down Configuration Register" */ -+/** Enable Power Down STATUS -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_STATUS 0x80000000 -+/* Disable -+#define PDCFG_STATUS_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_STATUS_EN 0x80000000 -+/** Enable Power Down SHA1 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_SHA1 0x40000000 -+/* Disable -+#define PDCFG_SHA1_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_SHA1_EN 0x40000000 -+/** Enable Power Down AES -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_AES 0x20000000 -+/* Disable -+#define PDCFG_AES_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_AES_EN 0x20000000 -+/** Enable Power Down PCM -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_PCM 0x10000000 -+/* Disable -+#define PDCFG_PCM_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_PCM_EN 0x10000000 -+/** Enable Power Down FSCT -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_FSCT 0x08000000 -+/* Disable -+#define PDCFG_FSCT_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_FSCT_EN 0x08000000 -+/** Enable Power Down GPTC -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_GPTC 0x04000000 -+/* Disable -+#define PDCFG_GPTC_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_GPTC_EN 0x04000000 -+/** Enable Power Down MPS -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_MPS 0x02000000 -+/* Disable -+#define PDCFG_MPS_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_MPS_EN 0x02000000 -+/** Enable Power Down DFEV0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_DFEV0 0x01000000 -+/* Disable -+#define PDCFG_DFEV0_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_DFEV0_EN 0x01000000 -+/** Enable Power Down PADCTRL4 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_PADCTRL4 0x00400000 -+/* Disable -+#define PDCFG_PADCTRL4_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_PADCTRL4_EN 0x00400000 -+/** Enable Power Down PADCTRL3 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_PADCTRL3 0x00200000 -+/* Disable -+#define PDCFG_PADCTRL3_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_PADCTRL3_EN 0x00200000 -+/** Enable Power Down PADCTRL1 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_PADCTRL1 0x00100000 -+/* Disable -+#define PDCFG_PADCTRL1_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_PADCTRL1_EN 0x00100000 -+/** Enable Power Down P4 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_P4 0x00040000 -+/* Disable -+#define PDCFG_P4_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_P4_EN 0x00040000 -+/** Enable Power Down P3 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_P3 0x00020000 -+/* Disable -+#define PDCFG_P3_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_P3_EN 0x00020000 -+/** Enable Power Down P1 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_P1 0x00010000 -+/* Disable -+#define PDCFG_P1_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_P1_EN 0x00010000 -+/** Enable Power Down HOST -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_HOST 0x00008000 -+/* Disable -+#define PDCFG_HOST_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_HOST_EN 0x00008000 -+/** Enable Power Down I2C -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_I2C 0x00004000 -+/* Disable -+#define PDCFG_I2C_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_I2C_EN 0x00004000 -+/** Enable Power Down SSC0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_SSC0 0x00002000 -+/* Disable -+#define PDCFG_SSC0_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_SSC0_EN 0x00002000 -+/** Enable Power Down ASC0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_ASC0 0x00001000 -+/* Disable -+#define PDCFG_ASC0_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_ASC0_EN 0x00001000 -+/** Enable Power Down ASC1 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_ASC1 0x00000800 -+/* Disable -+#define PDCFG_ASC1_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_ASC1_EN 0x00000800 -+/** Enable Power Down DCDCAPD -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_DCDCAPD 0x00000400 -+/* Disable -+#define PDCFG_DCDCAPD_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_DCDCAPD_EN 0x00000400 -+/** Enable Power Down DCDCDDR -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_DCDCDDR 0x00000200 -+/* Disable -+#define PDCFG_DCDCDDR_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_DCDCDDR_EN 0x00000200 -+/** Enable Power Down DCDC1V0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_DCDC1V0 0x00000100 -+/* Disable -+#define PDCFG_DCDC1V0_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_DCDC1V0_EN 0x00000100 -+/** Enable Power Down TRC2MEM -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_TRC2MEM 0x00000040 -+/* Disable -+#define PDCFG_TRC2MEM_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_TRC2MEM_EN 0x00000040 -+/** Enable Power Down DDR -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_DDR 0x00000020 -+/* Disable -+#define PDCFG_DDR_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_DDR_EN 0x00000020 -+/** Enable Power Down EBU -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_EBU 0x00000010 -+/* Disable -+#define PDCFG_EBU_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_EBU_EN 0x00000010 -+ -+/* Fields of "CLKO Pad Control Register" */ -+/** Ethernet Reference Clock CLKO Select -+ Selects the CLKO pad's input as source for the GPHY, SGMII PLLs. */ -+#define CLKOC_ETHREF 0x00000002 -+/* Not selected -+#define CLKOC_ETHREF_NSEL 0x00000000 */ -+/** Selected */ -+#define CLKOC_ETHREF_SEL 0x00000002 -+/** Output Enable -+ Enables the output driver of the CLKO pad. */ -+#define CLKOC_OEN 0x00000001 -+/* Disable -+#define CLKOC_OEN_DIS 0x00000000 */ -+/** Enable */ -+#define CLKOC_OEN_EN 0x00000001 -+ -+/* Fields of "Infrastructure Control Register" */ -+/** General Purpose Control -+ Backup bits. Currently they are connected as: bit 0 : connected to the configmode_on pin of the pinstrapping block. bit 1 : clock enable of the GPE primary clock. bits 3:2 : frequency select of the GPE primary clock. 00 = 769.2MHz, 01 = 625MHz, 10 = 555.6MHz, 11 = 500MHz All other bits are unconnected. */ -+#define INFRAC_GP_MASK 0x1F000000 -+/** field offset */ -+#define INFRAC_GP_OFFSET 24 -+/** CMOS2CML Ethernet Control -+ CMOS2CML Ethernet Control. */ -+#define INFRAC_CMOS2CML_GPON_MASK 0x0000F000 -+/** field offset */ -+#define INFRAC_CMOS2CML_GPON_OFFSET 12 -+/** CMOS2CML Ethernet Control -+ CMOS2CML Ethernet Control. */ -+#define INFRAC_CMOS2CML_ETH_MASK 0x00000F00 -+/** field offset */ -+#define INFRAC_CMOS2CML_ETH_OFFSET 8 -+/** Dying Gasp Enable -+ Enables the dying gasp detector. */ -+#define INFRAC_DGASPEN 0x00000040 -+/* Disable -+#define INFRAC_DGASPEN_DIS 0x00000000 */ -+/** Enable */ -+#define INFRAC_DGASPEN_EN 0x00000040 -+/** Dying Gasp Hysteresis Control -+ Dying Gasp Hysteresis Control. */ -+#define INFRAC_DGASPHYS_MASK 0x00000030 -+/** field offset */ -+#define INFRAC_DGASPHYS_OFFSET 4 -+/** Linear Regulator 1.5V Enable -+ Enables 1.5V linear regulator. */ -+#define INFRAC_LIN1V5EN 0x00000008 -+/* Disable -+#define INFRAC_LIN1V5EN_DIS 0x00000000 */ -+/** Enable */ -+#define INFRAC_LIN1V5EN_EN 0x00000008 -+/** Linear Regulator 1.5V Control -+ Linear regulator 1.5V control. */ -+#define INFRAC_LIN1V5C_MASK 0x00000007 -+/** field offset */ -+#define INFRAC_LIN1V5C_OFFSET 0 -+ -+/* Fields of "HRST_OUT_N Control Register" */ -+/** HRST_OUT_N Pin Value -+ Controls the value of the HRST_OUT_N pin. */ -+#define HRSTOUTC_VALUE 0x00000001 -+ -+/* Fields of "EBU Clock Control Register" */ -+/** EBU Clock Divider -+ Via this bit the frequency of the clock of the EBU can be selected. */ -+#define EBUCC_EBUDIV 0x00000001 -+/* Frequency set to 50MHz. -+#define EBUCC_EBUDIV_SELF50 0x00000000 */ -+/** Frequency set to 100MHz. */ -+#define EBUCC_EBUDIV_SELF100 0x00000001 -+ -+/* Fields of "NMI Status Register" */ -+/** NMI Status Flag TEST -+ Shows whether the event NMI TEST occurred. */ -+#define NMIS_TEST 0x00000100 -+/* Nothing -+#define NMIS_TEST_NULL 0x00000000 */ -+/** Read: Event occurred. */ -+#define NMIS_TEST_EVOCC 0x00000100 -+/** NMI Status Flag DGASP -+ Shows whether the event NMI DGASP occurred. */ -+#define NMIS_DGASP 0x00000004 -+/* Nothing -+#define NMIS_DGASP_NULL 0x00000000 */ -+/** Read: Event occurred. */ -+#define NMIS_DGASP_EVOCC 0x00000004 -+/** NMI Status Flag HOST -+ Shows whether the event NMI HOST occurred. */ -+#define NMIS_HOST 0x00000002 -+/* Nothing -+#define NMIS_HOST_NULL 0x00000000 */ -+/** Read: Event occurred. */ -+#define NMIS_HOST_EVOCC 0x00000002 -+/** NMI Status Flag PIN -+ Shows whether the event NMI PIN occurred. */ -+#define NMIS_PIN 0x00000001 -+/* Nothing -+#define NMIS_PIN_NULL 0x00000000 */ -+/** Read: Event occurred. */ -+#define NMIS_PIN_EVOCC 0x00000001 -+ -+/* Fields of "NMI Set Register" */ -+/** Set NMI Status Flag TEST -+ Sets the corresponding NMI status flag. */ -+#define NMISET_TEST 0x00000100 -+/* Nothing -+#define NMISET_TEST_NULL 0x00000000 */ -+/** Set */ -+#define NMISET_TEST_SET 0x00000100 -+/** Set NMI Status Flag DGASP -+ Sets the corresponding NMI status flag. */ -+#define NMISET_DGASP 0x00000004 -+/* Nothing -+#define NMISET_DGASP_NULL 0x00000000 */ -+/** Set */ -+#define NMISET_DGASP_SET 0x00000004 -+/** Set NMI Status Flag HOST -+ Sets the corresponding NMI status flag. */ -+#define NMISET_HOST 0x00000002 -+/* Nothing -+#define NMISET_HOST_NULL 0x00000000 */ -+/** Set */ -+#define NMISET_HOST_SET 0x00000002 -+/** Set NMI Status Flag PIN -+ Sets the corresponding NMI status flag. */ -+#define NMISET_PIN 0x00000001 -+/* Nothing -+#define NMISET_PIN_NULL 0x00000000 */ -+/** Set */ -+#define NMISET_PIN_SET 0x00000001 -+ -+/* Fields of "NMI Clear Register" */ -+/** Clear NMI Status Flag TEST -+ Clears the corresponding NMI status flag. */ -+#define NMICLR_TEST 0x00000100 -+/* Nothing -+#define NMICLR_TEST_NULL 0x00000000 */ -+/** Clear */ -+#define NMICLR_TEST_CLR 0x00000100 -+/** Clear NMI Status Flag DGASP -+ Clears the corresponding NMI status flag. */ -+#define NMICLR_DGASP 0x00000004 -+/* Nothing -+#define NMICLR_DGASP_NULL 0x00000000 */ -+/** Clear */ -+#define NMICLR_DGASP_CLR 0x00000004 -+/** Clear NMI Status Flag HOST -+ Clears the corresponding NMI status flag. */ -+#define NMICLR_HOST 0x00000002 -+/* Nothing -+#define NMICLR_HOST_NULL 0x00000000 */ -+/** Clear */ -+#define NMICLR_HOST_CLR 0x00000002 -+/** Clear NMI Status Flag PIN -+ Clears the corresponding NMI status flag. */ -+#define NMICLR_PIN 0x00000001 -+/* Nothing -+#define NMICLR_PIN_NULL 0x00000000 */ -+/** Clear */ -+#define NMICLR_PIN_CLR 0x00000001 -+ -+/* Fields of "NMI Test Configuration Register" */ -+/** Enable NMI Test Feature -+ Enables the operation of the NMI TEST flag. This is the mask for the Non-Maskable-Interrupt dedicated to SW tests. All others cannot be masked. */ -+#define NMITCFG_TEN 0x00000100 -+/* Disable -+#define NMITCFG_TEN_DIS 0x00000000 */ -+/** Enable */ -+#define NMITCFG_TEN_EN 0x00000100 -+ -+/* Fields of "NMI VPE1 Control Register" */ -+/** NMI VPE1 State -+ Reflects the state of the NMI signal towards VPE1. This bit is controlled by software only, there is no hardware NMI source dedicated to VPE1. So VPE0 could trigger an NMI at VPE1 using this bit in its own NMI-routine. */ -+#define NMIVPE1C_NMI 0x00000001 -+/* False -+#define NMIVPE1C_NMI_FALSE 0x00000000 */ -+/** True */ -+#define NMIVPE1C_NMI_TRUE 0x00000001 -+ -+/* Fields of "IRN Capture Register" */ -+/** DCDCAPD Alarm -+ The DCDC Converter for the APD Supply submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define IRNCR_DCDCAPD 0x00400000 -+/* Nothing -+#define IRNCR_DCDCAPD_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define IRNCR_DCDCAPD_INTACK 0x00400000 -+/** Read: Interrupt occurred. */ -+#define IRNCR_DCDCAPD_INTOCC 0x00400000 -+/** DCDCDDR Alarm -+ The DCDC Converter for the DDR Supply submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define IRNCR_DCDCDDR 0x00200000 -+/* Nothing -+#define IRNCR_DCDCDDR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define IRNCR_DCDCDDR_INTACK 0x00200000 -+/** Read: Interrupt occurred. */ -+#define IRNCR_DCDCDDR_INTOCC 0x00200000 -+/** DCDC1V0 Alarm -+ The DCDC Converter for the 1.0 Volts submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define IRNCR_DCDC1V0 0x00100000 -+/* Nothing -+#define IRNCR_DCDC1V0_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define IRNCR_DCDC1V0_INTACK 0x00100000 -+/** Read: Interrupt occurred. */ -+#define IRNCR_DCDC1V0_INTOCC 0x00100000 -+/** SIF0 wakeup request -+ SmartSlic Interface 0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define IRNCR_SIF0 0x00010000 -+/* Nothing -+#define IRNCR_SIF0_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define IRNCR_SIF0_INTACK 0x00010000 -+/** Read: Interrupt occurred. */ -+#define IRNCR_SIF0_INTOCC 0x00010000 -+ -+/* Fields of "IRN Interrupt Control Register" */ -+/** DCDCAPD Alarm -+ Interrupt control bit for the corresponding bit in the IRNCR register. */ -+#define IRNICR_DCDCAPD 0x00400000 -+/** DCDCDDR Alarm -+ Interrupt control bit for the corresponding bit in the IRNCR register. */ -+#define IRNICR_DCDCDDR 0x00200000 -+/** DCDC1V0 Alarm -+ Interrupt control bit for the corresponding bit in the IRNCR register. */ -+#define IRNICR_DCDC1V0 0x00100000 -+/** SIF0 wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCR register. */ -+#define IRNICR_SIF0 0x00010000 -+ -+/* Fields of "IRN Interrupt Enable Register" */ -+/** DCDCAPD Alarm -+ Interrupt enable bit for the corresponding bit in the IRNCR register. */ -+#define IRNEN_DCDCAPD 0x00400000 -+/* Disable -+#define IRNEN_DCDCAPD_DIS 0x00000000 */ -+/** Enable */ -+#define IRNEN_DCDCAPD_EN 0x00400000 -+/** DCDCDDR Alarm -+ Interrupt enable bit for the corresponding bit in the IRNCR register. */ -+#define IRNEN_DCDCDDR 0x00200000 -+/* Disable -+#define IRNEN_DCDCDDR_DIS 0x00000000 */ -+/** Enable */ -+#define IRNEN_DCDCDDR_EN 0x00200000 -+/** DCDC1V0 Alarm -+ Interrupt enable bit for the corresponding bit in the IRNCR register. */ -+#define IRNEN_DCDC1V0 0x00100000 -+/* Disable -+#define IRNEN_DCDC1V0_DIS 0x00000000 */ -+/** Enable */ -+#define IRNEN_DCDC1V0_EN 0x00100000 -+/** SIF0 wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCR register. */ -+#define IRNEN_SIF0 0x00010000 -+/* Disable -+#define IRNEN_SIF0_DIS 0x00000000 */ -+/** Enable */ -+#define IRNEN_SIF0_EN 0x00010000 -+ -+/*! @} */ /* SYS1_REGISTER */ -+ -+#endif /* _sys1_reg_h */ ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/sys_eth_reg.h -@@ -0,0 +1,1132 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+ -+#ifndef _sys_eth_reg_h -+#define _sys_eth_reg_h -+ -+/** \addtogroup SYS_ETH_REGISTER -+ @{ -+*/ -+/* access macros */ -+#define sys_eth_r32(reg) reg_r32(&sys_eth->reg) -+#define sys_eth_w32(val, reg) reg_w32(val, &sys_eth->reg) -+#define sys_eth_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys_eth->reg) -+#define sys_eth_r32_table(reg, idx) reg_r32_table(sys_eth->reg, idx) -+#define sys_eth_w32_table(val, reg, idx) reg_w32_table(val, sys_eth->reg, idx) -+#define sys_eth_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys_eth->reg, idx) -+#define sys_eth_adr_table(reg, idx) adr_table(sys_eth->reg, idx) -+ -+ -+/** SYS_ETH register structure */ -+struct gpon_reg_sys_eth -+{ -+ /** Clock Status Register */ -+ unsigned int clks; /* 0x00000000 */ -+ /** Clock Enable Register -+ Via this register the clocks for the domains can be enabled. */ -+ unsigned int clken; /* 0x00000004 */ -+ /** Clock Clear Register -+ Via this register the clocks for the domains can be disabled. */ -+ unsigned int clkclr; /* 0x00000008 */ -+ /** Reserved */ -+ unsigned int res_0[5]; /* 0x0000000C */ -+ /** Activation Status Register */ -+ unsigned int acts; /* 0x00000020 */ -+ /** Activation Register -+ Via this register the domains can be activated. */ -+ unsigned int act; /* 0x00000024 */ -+ /** Deactivation Register -+ Via this register the domains can be deactivated. */ -+ unsigned int deact; /* 0x00000028 */ -+ /** Reboot Trigger Register -+ Via this register the domains can be rebooted (sent through reset). */ -+ unsigned int rbt; /* 0x0000002C */ -+ /** Reserved */ -+ unsigned int res_1[32]; /* 0x00000030 */ -+ /** External PHY Control Register */ -+ unsigned int extphyc; /* 0x000000B0 */ -+ /** Power Down Configuration Register -+ Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be removed. */ -+ unsigned int pdcfg; /* 0x000000B4 */ -+ /** Datarate Control Register -+ Controls the datarate of the various physical layers. The contents of the writeable fields of this register shall not be changed during operation. */ -+ unsigned int drc; /* 0x000000B8 */ -+ /** GMAC Multiplexer Control Register -+ Controls the interconnect between GMACs and the various physical layers. All fields need to have a different content. If two GMACs are muxed to the same PHY unpredictable results may occur. The contents of this register shall not be changed during operation. */ -+ unsigned int gmuxc; /* 0x000000BC */ -+ /** Datarate Status Register -+ Shows the datarate of the GMACs. The datarate of a GMAC is derived from the datarate of the physical layer it is multiplexed to. This register is for debugging only. */ -+ unsigned int drs; /* 0x000000C0 */ -+ /** SGMII Control Register */ -+ unsigned int sgmiic; /* 0x000000C4 */ -+ /** Reserved */ -+ unsigned int res_2[14]; /* 0x000000C8 */ -+}; -+ -+ -+/* Fields of "Clock Status Register" */ -+/** GPHY1MII2 Clock Enable -+ Shows the clock enable bit for GPHY1MII2. */ -+#define SYS_ETH_CLKS_GPHY1MII2 0x02000000 -+/* Disable -+#define SYS_ETH_CLKS_GPHY1MII2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_GPHY1MII2_EN 0x02000000 -+/** GPHY0MII2 Clock Enable -+ Shows the clock enable bit for GPHY0MII2. */ -+#define SYS_ETH_CLKS_GPHY0MII2 0x01000000 -+/* Disable -+#define SYS_ETH_CLKS_GPHY0MII2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_GPHY0MII2_EN 0x01000000 -+/** PADCTRL2 Clock Enable -+ Shows the clock enable bit for the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ -+#define SYS_ETH_CLKS_PADCTRL2 0x00200000 -+/* Disable -+#define SYS_ETH_CLKS_PADCTRL2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_PADCTRL2_EN 0x00200000 -+/** PADCTRL0 Clock Enable -+ Shows the clock enable bit for the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ -+#define SYS_ETH_CLKS_PADCTRL0 0x00100000 -+/* Disable -+#define SYS_ETH_CLKS_PADCTRL0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_PADCTRL0_EN 0x00100000 -+/** P2 Clock Enable -+ Shows the clock enable bit for the P2 domain. This domain contains the P2 instance of the GPIO block. */ -+#define SYS_ETH_CLKS_P2 0x00020000 -+/* Disable -+#define SYS_ETH_CLKS_P2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_P2_EN 0x00020000 -+/** P0 Clock Enable -+ Shows the clock enable bit for the P0 domain. This domain contains the P0 instance of the GPIO block. */ -+#define SYS_ETH_CLKS_P0 0x00010000 -+/* Disable -+#define SYS_ETH_CLKS_P0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_P0_EN 0x00010000 -+/** xMII Clock Enable -+ Shows the clock enable bit for the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ -+#define SYS_ETH_CLKS_xMII 0x00000800 -+/* Disable -+#define SYS_ETH_CLKS_xMII_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_xMII_EN 0x00000800 -+/** SGMII Clock Enable -+ Shows the clock enable bit for the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_CLKS_SGMII 0x00000400 -+/* Disable -+#define SYS_ETH_CLKS_SGMII_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_SGMII_EN 0x00000400 -+/** GPHY1 Clock Enable -+ Shows the clock enable bit for the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_CLKS_GPHY1 0x00000200 -+/* Disable -+#define SYS_ETH_CLKS_GPHY1_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_GPHY1_EN 0x00000200 -+/** GPHY0 Clock Enable -+ Shows the clock enable bit for the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_CLKS_GPHY0 0x00000100 -+/* Disable -+#define SYS_ETH_CLKS_GPHY0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_GPHY0_EN 0x00000100 -+/** MDIO Clock Enable -+ Shows the clock enable bit for the MDIO domain. This domain contains the MDIO block. */ -+#define SYS_ETH_CLKS_MDIO 0x00000080 -+/* Disable -+#define SYS_ETH_CLKS_MDIO_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_MDIO_EN 0x00000080 -+/** GMAC3 Clock Enable -+ Shows the clock enable bit for the GMAC3 domain. This domain contains the GMAC3 block. */ -+#define SYS_ETH_CLKS_GMAC3 0x00000008 -+/* Disable -+#define SYS_ETH_CLKS_GMAC3_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_GMAC3_EN 0x00000008 -+/** GMAC2 Clock Enable -+ Shows the clock enable bit for the GMAC2 domain. This domain contains the GMAC2 block. */ -+#define SYS_ETH_CLKS_GMAC2 0x00000004 -+/* Disable -+#define SYS_ETH_CLKS_GMAC2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_GMAC2_EN 0x00000004 -+/** GMAC1 Clock Enable -+ Shows the clock enable bit for the GMAC1 domain. This domain contains the GMAC1 block. */ -+#define SYS_ETH_CLKS_GMAC1 0x00000002 -+/* Disable -+#define SYS_ETH_CLKS_GMAC1_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_GMAC1_EN 0x00000002 -+/** GMAC0 Clock Enable -+ Shows the clock enable bit for the GMAC0 domain. This domain contains the GMAC0 block. */ -+#define SYS_ETH_CLKS_GMAC0 0x00000001 -+/* Disable -+#define SYS_ETH_CLKS_GMAC0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_GMAC0_EN 0x00000001 -+ -+/* Fields of "Clock Enable Register" */ -+/** Set Clock Enable GPHY1MII2 -+ Sets the clock enable bit of the GPHY1MII2. */ -+#define SYS_ETH_CLKEN_GPHY1MII2 0x02000000 -+/* No-Operation -+#define SYS_ETH_CLKEN_GPHY1MII2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_GPHY1MII2_SET 0x02000000 -+/** Set Clock Enable GPHY0MII2 -+ Sets the clock enable bit of the GPHY0MII2. */ -+#define SYS_ETH_CLKEN_GPHY0MII2 0x01000000 -+/* No-Operation -+#define SYS_ETH_CLKEN_GPHY0MII2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_GPHY0MII2_SET 0x01000000 -+/** Set Clock Enable PADCTRL2 -+ Sets the clock enable bit of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ -+#define SYS_ETH_CLKEN_PADCTRL2 0x00200000 -+/* No-Operation -+#define SYS_ETH_CLKEN_PADCTRL2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_PADCTRL2_SET 0x00200000 -+/** Set Clock Enable PADCTRL0 -+ Sets the clock enable bit of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ -+#define SYS_ETH_CLKEN_PADCTRL0 0x00100000 -+/* No-Operation -+#define SYS_ETH_CLKEN_PADCTRL0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_PADCTRL0_SET 0x00100000 -+/** Set Clock Enable P2 -+ Sets the clock enable bit of the P2 domain. This domain contains the P2 instance of the GPIO block. */ -+#define SYS_ETH_CLKEN_P2 0x00020000 -+/* No-Operation -+#define SYS_ETH_CLKEN_P2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_P2_SET 0x00020000 -+/** Set Clock Enable P0 -+ Sets the clock enable bit of the P0 domain. This domain contains the P0 instance of the GPIO block. */ -+#define SYS_ETH_CLKEN_P0 0x00010000 -+/* No-Operation -+#define SYS_ETH_CLKEN_P0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_P0_SET 0x00010000 -+/** Set Clock Enable xMII -+ Sets the clock enable bit of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ -+#define SYS_ETH_CLKEN_xMII 0x00000800 -+/* No-Operation -+#define SYS_ETH_CLKEN_xMII_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_xMII_SET 0x00000800 -+/** Set Clock Enable SGMII -+ Sets the clock enable bit of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_CLKEN_SGMII 0x00000400 -+/* No-Operation -+#define SYS_ETH_CLKEN_SGMII_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_SGMII_SET 0x00000400 -+/** Set Clock Enable GPHY1 -+ Sets the clock enable bit of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_CLKEN_GPHY1 0x00000200 -+/* No-Operation -+#define SYS_ETH_CLKEN_GPHY1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_GPHY1_SET 0x00000200 -+/** Set Clock Enable GPHY0 -+ Sets the clock enable bit of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_CLKEN_GPHY0 0x00000100 -+/* No-Operation -+#define SYS_ETH_CLKEN_GPHY0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_GPHY0_SET 0x00000100 -+/** Set Clock Enable MDIO -+ Sets the clock enable bit of the MDIO domain. This domain contains the MDIO block. */ -+#define SYS_ETH_CLKEN_MDIO 0x00000080 -+/* No-Operation -+#define SYS_ETH_CLKEN_MDIO_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_MDIO_SET 0x00000080 -+/** Set Clock Enable GMAC3 -+ Sets the clock enable bit of the GMAC3 domain. This domain contains the GMAC3 block. */ -+#define SYS_ETH_CLKEN_GMAC3 0x00000008 -+/* No-Operation -+#define SYS_ETH_CLKEN_GMAC3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_GMAC3_SET 0x00000008 -+/** Set Clock Enable GMAC2 -+ Sets the clock enable bit of the GMAC2 domain. This domain contains the GMAC2 block. */ -+#define SYS_ETH_CLKEN_GMAC2 0x00000004 -+/* No-Operation -+#define SYS_ETH_CLKEN_GMAC2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_GMAC2_SET 0x00000004 -+/** Set Clock Enable GMAC1 -+ Sets the clock enable bit of the GMAC1 domain. This domain contains the GMAC1 block. */ -+#define SYS_ETH_CLKEN_GMAC1 0x00000002 -+/* No-Operation -+#define SYS_ETH_CLKEN_GMAC1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_GMAC1_SET 0x00000002 -+/** Set Clock Enable GMAC0 -+ Sets the clock enable bit of the GMAC0 domain. This domain contains the GMAC0 block. */ -+#define SYS_ETH_CLKEN_GMAC0 0x00000001 -+/* No-Operation -+#define SYS_ETH_CLKEN_GMAC0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_GMAC0_SET 0x00000001 -+ -+/* Fields of "Clock Clear Register" */ -+/** Clear Clock Enable GPHY1MII2 -+ Clears the clock enable bit of the GPHY1MII2. */ -+#define SYS_ETH_CLKCLR_GPHY1MII2 0x02000000 -+/* No-Operation -+#define SYS_ETH_CLKCLR_GPHY1MII2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_GPHY1MII2_CLR 0x02000000 -+/** Clear Clock Enable GPHY0MII2 -+ Clears the clock enable bit of the GPHY0MII2. */ -+#define SYS_ETH_CLKCLR_GPHY0MII2 0x01000000 -+/* No-Operation -+#define SYS_ETH_CLKCLR_GPHY0MII2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_GPHY0MII2_CLR 0x01000000 -+/** Clear Clock Enable PADCTRL2 -+ Clears the clock enable bit of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ -+#define SYS_ETH_CLKCLR_PADCTRL2 0x00200000 -+/* No-Operation -+#define SYS_ETH_CLKCLR_PADCTRL2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_PADCTRL2_CLR 0x00200000 -+/** Clear Clock Enable PADCTRL0 -+ Clears the clock enable bit of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ -+#define SYS_ETH_CLKCLR_PADCTRL0 0x00100000 -+/* No-Operation -+#define SYS_ETH_CLKCLR_PADCTRL0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_PADCTRL0_CLR 0x00100000 -+/** Clear Clock Enable P2 -+ Clears the clock enable bit of the P2 domain. This domain contains the P2 instance of the GPIO block. */ -+#define SYS_ETH_CLKCLR_P2 0x00020000 -+/* No-Operation -+#define SYS_ETH_CLKCLR_P2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_P2_CLR 0x00020000 -+/** Clear Clock Enable P0 -+ Clears the clock enable bit of the P0 domain. This domain contains the P0 instance of the GPIO block. */ -+#define SYS_ETH_CLKCLR_P0 0x00010000 -+/* No-Operation -+#define SYS_ETH_CLKCLR_P0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_P0_CLR 0x00010000 -+/** Clear Clock Enable xMII -+ Clears the clock enable bit of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ -+#define SYS_ETH_CLKCLR_xMII 0x00000800 -+/* No-Operation -+#define SYS_ETH_CLKCLR_xMII_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_xMII_CLR 0x00000800 -+/** Clear Clock Enable SGMII -+ Clears the clock enable bit of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_CLKCLR_SGMII 0x00000400 -+/* No-Operation -+#define SYS_ETH_CLKCLR_SGMII_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_SGMII_CLR 0x00000400 -+/** Clear Clock Enable GPHY1 -+ Clears the clock enable bit of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_CLKCLR_GPHY1 0x00000200 -+/* No-Operation -+#define SYS_ETH_CLKCLR_GPHY1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_GPHY1_CLR 0x00000200 -+/** Clear Clock Enable GPHY0 -+ Clears the clock enable bit of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_CLKCLR_GPHY0 0x00000100 -+/* No-Operation -+#define SYS_ETH_CLKCLR_GPHY0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_GPHY0_CLR 0x00000100 -+/** Clear Clock Enable MDIO -+ Clears the clock enable bit of the MDIO domain. This domain contains the MDIO block. */ -+#define SYS_ETH_CLKCLR_MDIO 0x00000080 -+/* No-Operation -+#define SYS_ETH_CLKCLR_MDIO_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_MDIO_CLR 0x00000080 -+/** Clear Clock Enable GMAC3 -+ Clears the clock enable bit of the GMAC3 domain. This domain contains the GMAC3 block. */ -+#define SYS_ETH_CLKCLR_GMAC3 0x00000008 -+/* No-Operation -+#define SYS_ETH_CLKCLR_GMAC3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_GMAC3_CLR 0x00000008 -+/** Clear Clock Enable GMAC2 -+ Clears the clock enable bit of the GMAC2 domain. This domain contains the GMAC2 block. */ -+#define SYS_ETH_CLKCLR_GMAC2 0x00000004 -+/* No-Operation -+#define SYS_ETH_CLKCLR_GMAC2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_GMAC2_CLR 0x00000004 -+/** Clear Clock Enable GMAC1 -+ Clears the clock enable bit of the GMAC1 domain. This domain contains the GMAC1 block. */ -+#define SYS_ETH_CLKCLR_GMAC1 0x00000002 -+/* No-Operation -+#define SYS_ETH_CLKCLR_GMAC1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_GMAC1_CLR 0x00000002 -+/** Clear Clock Enable GMAC0 -+ Clears the clock enable bit of the GMAC0 domain. This domain contains the GMAC0 block. */ -+#define SYS_ETH_CLKCLR_GMAC0 0x00000001 -+/* No-Operation -+#define SYS_ETH_CLKCLR_GMAC0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_GMAC0_CLR 0x00000001 -+ -+/* Fields of "Activation Status Register" */ -+/** PADCTRL2 Status -+ Shows the activation status of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ -+#define SYS_ETH_ACTS_PADCTRL2 0x00200000 -+/* The block is inactive. -+#define SYS_ETH_ACTS_PADCTRL2_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_PADCTRL2_ACT 0x00200000 -+/** PADCTRL0 Status -+ Shows the activation status of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ -+#define SYS_ETH_ACTS_PADCTRL0 0x00100000 -+/* The block is inactive. -+#define SYS_ETH_ACTS_PADCTRL0_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_PADCTRL0_ACT 0x00100000 -+/** P2 Status -+ Shows the activation status of the P2 domain. This domain contains the P2 instance of the GPIO block. */ -+#define SYS_ETH_ACTS_P2 0x00020000 -+/* The block is inactive. -+#define SYS_ETH_ACTS_P2_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_P2_ACT 0x00020000 -+/** P0 Status -+ Shows the activation status of the P0 domain. This domain contains the P0 instance of the GPIO block. */ -+#define SYS_ETH_ACTS_P0 0x00010000 -+/* The block is inactive. -+#define SYS_ETH_ACTS_P0_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_P0_ACT 0x00010000 -+/** xMII Status -+ Shows the activation status of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ -+#define SYS_ETH_ACTS_xMII 0x00000800 -+/* The block is inactive. -+#define SYS_ETH_ACTS_xMII_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_xMII_ACT 0x00000800 -+/** SGMII Status -+ Shows the activation status of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_ACTS_SGMII 0x00000400 -+/* The block is inactive. -+#define SYS_ETH_ACTS_SGMII_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_SGMII_ACT 0x00000400 -+/** GPHY1 Status -+ Shows the activation status of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_ACTS_GPHY1 0x00000200 -+/* The block is inactive. -+#define SYS_ETH_ACTS_GPHY1_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_GPHY1_ACT 0x00000200 -+/** GPHY0 Status -+ Shows the activation status of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_ACTS_GPHY0 0x00000100 -+/* The block is inactive. -+#define SYS_ETH_ACTS_GPHY0_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_GPHY0_ACT 0x00000100 -+/** MDIO Status -+ Shows the activation status of the MDIO domain. This domain contains the MDIO block. */ -+#define SYS_ETH_ACTS_MDIO 0x00000080 -+/* The block is inactive. -+#define SYS_ETH_ACTS_MDIO_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_MDIO_ACT 0x00000080 -+/** GMAC3 Status -+ Shows the activation status of the GMAC3 domain. This domain contains the GMAC3 block. */ -+#define SYS_ETH_ACTS_GMAC3 0x00000008 -+/* The block is inactive. -+#define SYS_ETH_ACTS_GMAC3_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_GMAC3_ACT 0x00000008 -+/** GMAC2 Status -+ Shows the activation status of the GMAC2 domain. This domain contains the GMAC2 block. */ -+#define SYS_ETH_ACTS_GMAC2 0x00000004 -+/* The block is inactive. -+#define SYS_ETH_ACTS_GMAC2_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_GMAC2_ACT 0x00000004 -+/** GMAC1 Status -+ Shows the activation status of the GMAC1 domain. This domain contains the GMAC1 block. */ -+#define SYS_ETH_ACTS_GMAC1 0x00000002 -+/* The block is inactive. -+#define SYS_ETH_ACTS_GMAC1_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_GMAC1_ACT 0x00000002 -+/** GMAC0 Status -+ Shows the activation status of the GMAC0 domain. This domain contains the GMAC0 block. */ -+#define SYS_ETH_ACTS_GMAC0 0x00000001 -+/* The block is inactive. -+#define SYS_ETH_ACTS_GMAC0_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_GMAC0_ACT 0x00000001 -+ -+/* Fields of "Activation Register" */ -+/** Activate PADCTRL2 -+ Sets the activation flag of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ -+#define SYS_ETH_ACT_PADCTRL2 0x00200000 -+/* No-Operation -+#define SYS_ETH_ACT_PADCTRL2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_PADCTRL2_SET 0x00200000 -+/** Activate PADCTRL0 -+ Sets the activation flag of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ -+#define SYS_ETH_ACT_PADCTRL0 0x00100000 -+/* No-Operation -+#define SYS_ETH_ACT_PADCTRL0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_PADCTRL0_SET 0x00100000 -+/** Activate P2 -+ Sets the activation flag of the P2 domain. This domain contains the P2 instance of the GPIO block. */ -+#define SYS_ETH_ACT_P2 0x00020000 -+/* No-Operation -+#define SYS_ETH_ACT_P2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_P2_SET 0x00020000 -+/** Activate P0 -+ Sets the activation flag of the P0 domain. This domain contains the P0 instance of the GPIO block. */ -+#define SYS_ETH_ACT_P0 0x00010000 -+/* No-Operation -+#define SYS_ETH_ACT_P0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_P0_SET 0x00010000 -+/** Activate xMII -+ Sets the activation flag of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ -+#define SYS_ETH_ACT_xMII 0x00000800 -+/* No-Operation -+#define SYS_ETH_ACT_xMII_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_xMII_SET 0x00000800 -+/** Activate SGMII -+ Sets the activation flag of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_ACT_SGMII 0x00000400 -+/* No-Operation -+#define SYS_ETH_ACT_SGMII_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_SGMII_SET 0x00000400 -+/** Activate GPHY1 -+ Sets the activation flag of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_ACT_GPHY1 0x00000200 -+/* No-Operation -+#define SYS_ETH_ACT_GPHY1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_GPHY1_SET 0x00000200 -+/** Activate GPHY0 -+ Sets the activation flag of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_ACT_GPHY0 0x00000100 -+/* No-Operation -+#define SYS_ETH_ACT_GPHY0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_GPHY0_SET 0x00000100 -+/** Activate MDIO -+ Sets the activation flag of the MDIO domain. This domain contains the MDIO block. */ -+#define SYS_ETH_ACT_MDIO 0x00000080 -+/* No-Operation -+#define SYS_ETH_ACT_MDIO_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_MDIO_SET 0x00000080 -+/** Activate GMAC3 -+ Sets the activation flag of the GMAC3 domain. This domain contains the GMAC3 block. */ -+#define SYS_ETH_ACT_GMAC3 0x00000008 -+/* No-Operation -+#define SYS_ETH_ACT_GMAC3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_GMAC3_SET 0x00000008 -+/** Activate GMAC2 -+ Sets the activation flag of the GMAC2 domain. This domain contains the GMAC2 block. */ -+#define SYS_ETH_ACT_GMAC2 0x00000004 -+/* No-Operation -+#define SYS_ETH_ACT_GMAC2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_GMAC2_SET 0x00000004 -+/** Activate GMAC1 -+ Sets the activation flag of the GMAC1 domain. This domain contains the GMAC1 block. */ -+#define SYS_ETH_ACT_GMAC1 0x00000002 -+/* No-Operation -+#define SYS_ETH_ACT_GMAC1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_GMAC1_SET 0x00000002 -+/** Activate GMAC0 -+ Sets the activation flag of the GMAC0 domain. This domain contains the GMAC0 block. */ -+#define SYS_ETH_ACT_GMAC0 0x00000001 -+/* No-Operation -+#define SYS_ETH_ACT_GMAC0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_GMAC0_SET 0x00000001 -+ -+/* Fields of "Deactivation Register" */ -+/** Deactivate PADCTRL2 -+ Clears the activation flag of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ -+#define SYS_ETH_DEACT_PADCTRL2 0x00200000 -+/* No-Operation -+#define SYS_ETH_DEACT_PADCTRL2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_PADCTRL2_CLR 0x00200000 -+/** Deactivate PADCTRL0 -+ Clears the activation flag of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ -+#define SYS_ETH_DEACT_PADCTRL0 0x00100000 -+/* No-Operation -+#define SYS_ETH_DEACT_PADCTRL0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_PADCTRL0_CLR 0x00100000 -+/** Deactivate P2 -+ Clears the activation flag of the P2 domain. This domain contains the P2 instance of the GPIO block. */ -+#define SYS_ETH_DEACT_P2 0x00020000 -+/* No-Operation -+#define SYS_ETH_DEACT_P2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_P2_CLR 0x00020000 -+/** Deactivate P0 -+ Clears the activation flag of the P0 domain. This domain contains the P0 instance of the GPIO block. */ -+#define SYS_ETH_DEACT_P0 0x00010000 -+/* No-Operation -+#define SYS_ETH_DEACT_P0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_P0_CLR 0x00010000 -+/** Deactivate xMII -+ Clears the activation flag of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ -+#define SYS_ETH_DEACT_xMII 0x00000800 -+/* No-Operation -+#define SYS_ETH_DEACT_xMII_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_xMII_CLR 0x00000800 -+/** Deactivate SGMII -+ Clears the activation flag of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_DEACT_SGMII 0x00000400 -+/* No-Operation -+#define SYS_ETH_DEACT_SGMII_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_SGMII_CLR 0x00000400 -+/** Deactivate GPHY1 -+ Clears the activation flag of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_DEACT_GPHY1 0x00000200 -+/* No-Operation -+#define SYS_ETH_DEACT_GPHY1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_GPHY1_CLR 0x00000200 -+/** Deactivate GPHY0 -+ Clears the activation flag of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_DEACT_GPHY0 0x00000100 -+/* No-Operation -+#define SYS_ETH_DEACT_GPHY0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_GPHY0_CLR 0x00000100 -+/** Deactivate MDIO -+ Clears the activation flag of the MDIO domain. This domain contains the MDIO block. */ -+#define SYS_ETH_DEACT_MDIO 0x00000080 -+/* No-Operation -+#define SYS_ETH_DEACT_MDIO_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_MDIO_CLR 0x00000080 -+/** Deactivate GMAC3 -+ Clears the activation flag of the GMAC3 domain. This domain contains the GMAC3 block. */ -+#define SYS_ETH_DEACT_GMAC3 0x00000008 -+/* No-Operation -+#define SYS_ETH_DEACT_GMAC3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_GMAC3_CLR 0x00000008 -+/** Deactivate GMAC2 -+ Clears the activation flag of the GMAC2 domain. This domain contains the GMAC2 block. */ -+#define SYS_ETH_DEACT_GMAC2 0x00000004 -+/* No-Operation -+#define SYS_ETH_DEACT_GMAC2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_GMAC2_CLR 0x00000004 -+/** Deactivate GMAC1 -+ Clears the activation flag of the GMAC1 domain. This domain contains the GMAC1 block. */ -+#define SYS_ETH_DEACT_GMAC1 0x00000002 -+/* No-Operation -+#define SYS_ETH_DEACT_GMAC1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_GMAC1_CLR 0x00000002 -+/** Deactivate GMAC0 -+ Clears the activation flag of the GMAC0 domain. This domain contains the GMAC0 block. */ -+#define SYS_ETH_DEACT_GMAC0 0x00000001 -+/* No-Operation -+#define SYS_ETH_DEACT_GMAC0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_GMAC0_CLR 0x00000001 -+ -+/* Fields of "Reboot Trigger Register" */ -+/** Reboot PADCTRL2 -+ Triggers a reboot of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ -+#define SYS_ETH_RBT_PADCTRL2 0x00200000 -+/* No-Operation -+#define SYS_ETH_RBT_PADCTRL2_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_PADCTRL2_TRIG 0x00200000 -+/** Reboot PADCTRL0 -+ Triggers a reboot of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ -+#define SYS_ETH_RBT_PADCTRL0 0x00100000 -+/* No-Operation -+#define SYS_ETH_RBT_PADCTRL0_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_PADCTRL0_TRIG 0x00100000 -+/** Reboot P2 -+ Triggers a reboot of the P2 domain. This domain contains the P2 instance of the GPIO block. */ -+#define SYS_ETH_RBT_P2 0x00020000 -+/* No-Operation -+#define SYS_ETH_RBT_P2_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_P2_TRIG 0x00020000 -+/** Reboot P0 -+ Triggers a reboot of the P0 domain. This domain contains the P0 instance of the GPIO block. */ -+#define SYS_ETH_RBT_P0 0x00010000 -+/* No-Operation -+#define SYS_ETH_RBT_P0_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_P0_TRIG 0x00010000 -+/** Reboot xMII -+ Triggers a reboot of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ -+#define SYS_ETH_RBT_xMII 0x00000800 -+/* No-Operation -+#define SYS_ETH_RBT_xMII_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_xMII_TRIG 0x00000800 -+/** Reboot SGMII -+ Triggers a reboot of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_RBT_SGMII 0x00000400 -+/* No-Operation -+#define SYS_ETH_RBT_SGMII_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_SGMII_TRIG 0x00000400 -+/** Reboot GPHY1 -+ Triggers a reboot of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_RBT_GPHY1 0x00000200 -+/* No-Operation -+#define SYS_ETH_RBT_GPHY1_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_GPHY1_TRIG 0x00000200 -+/** Reboot GPHY0 -+ Triggers a reboot of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_RBT_GPHY0 0x00000100 -+/* No-Operation -+#define SYS_ETH_RBT_GPHY0_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_GPHY0_TRIG 0x00000100 -+/** Reboot MDIO -+ Triggers a reboot of the MDIO domain. This domain contains the MDIO block. */ -+#define SYS_ETH_RBT_MDIO 0x00000080 -+/* No-Operation -+#define SYS_ETH_RBT_MDIO_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_MDIO_TRIG 0x00000080 -+/** Reboot GMAC3 -+ Triggers a reboot of the GMAC3 domain. This domain contains the GMAC3 block. */ -+#define SYS_ETH_RBT_GMAC3 0x00000008 -+/* No-Operation -+#define SYS_ETH_RBT_GMAC3_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_GMAC3_TRIG 0x00000008 -+/** Reboot GMAC2 -+ Triggers a reboot of the GMAC2 domain. This domain contains the GMAC2 block. */ -+#define SYS_ETH_RBT_GMAC2 0x00000004 -+/* No-Operation -+#define SYS_ETH_RBT_GMAC2_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_GMAC2_TRIG 0x00000004 -+/** Reboot GMAC1 -+ Triggers a reboot of the GMAC1 domain. This domain contains the GMAC1 block. */ -+#define SYS_ETH_RBT_GMAC1 0x00000002 -+/* No-Operation -+#define SYS_ETH_RBT_GMAC1_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_GMAC1_TRIG 0x00000002 -+/** Reboot GMAC0 -+ Triggers a reboot of the GMAC0 domain. This domain contains the GMAC0 block. */ -+#define SYS_ETH_RBT_GMAC0 0x00000001 -+/* No-Operation -+#define SYS_ETH_RBT_GMAC0_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_GMAC0_TRIG 0x00000001 -+ -+/* Fields of "External PHY Control Register" */ -+/** PHY_CLKO Output Enable -+ Enables the output driver of the PHY_CLKO pin. */ -+#define SYS_ETH_EXTPHYC_CLKEN 0x80000000 -+/* Disable -+#define SYS_ETH_EXTPHYC_CLKEN_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_EXTPHYC_CLKEN_EN 0x80000000 -+/** PHY_CLKO Frequency Select -+ Selects the frequency of the PHY_CLKO pin. */ -+#define SYS_ETH_EXTPHYC_CLKSEL_MASK 0x00000007 -+/** field offset */ -+#define SYS_ETH_EXTPHYC_CLKSEL_OFFSET 0 -+/** 25 MHz. */ -+#define SYS_ETH_EXTPHYC_CLKSEL_F25 0x00000001 -+/** 125 MHz. */ -+#define SYS_ETH_EXTPHYC_CLKSEL_F125 0x00000002 -+/** 50 MHz. */ -+#define SYS_ETH_EXTPHYC_CLKSEL_F50 0x00000005 -+ -+/* Fields of "Power Down Configuration Register" */ -+/** Enable Power Down PADCTRL2 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_PADCTRL2 0x00200000 -+/* Disable -+#define SYS_ETH_PDCFG_PADCTRL2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_PADCTRL2_EN 0x00200000 -+/** Enable Power Down PADCTRL0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_PADCTRL0 0x00100000 -+/* Disable -+#define SYS_ETH_PDCFG_PADCTRL0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_PADCTRL0_EN 0x00100000 -+/** Enable Power Down P2 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_P2 0x00020000 -+/* Disable -+#define SYS_ETH_PDCFG_P2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_P2_EN 0x00020000 -+/** Enable Power Down P0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_P0 0x00010000 -+/* Disable -+#define SYS_ETH_PDCFG_P0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_P0_EN 0x00010000 -+/** Enable Power Down xMII -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_xMII 0x00000800 -+/* Disable -+#define SYS_ETH_PDCFG_xMII_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_xMII_EN 0x00000800 -+/** Enable Power Down SGMII -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_SGMII 0x00000400 -+/* Disable -+#define SYS_ETH_PDCFG_SGMII_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_SGMII_EN 0x00000400 -+/** Enable Power Down GPHY1 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_GPHY1 0x00000200 -+/* Disable -+#define SYS_ETH_PDCFG_GPHY1_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_GPHY1_EN 0x00000200 -+/** Enable Power Down GPHY0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_GPHY0 0x00000100 -+/* Disable -+#define SYS_ETH_PDCFG_GPHY0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_GPHY0_EN 0x00000100 -+/** Enable Power Down MDIO -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_MDIO 0x00000080 -+/* Disable -+#define SYS_ETH_PDCFG_MDIO_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_MDIO_EN 0x00000080 -+/** Enable Power Down GMAC3 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_GMAC3 0x00000008 -+/* Disable -+#define SYS_ETH_PDCFG_GMAC3_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_GMAC3_EN 0x00000008 -+/** Enable Power Down GMAC2 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_GMAC2 0x00000004 -+/* Disable -+#define SYS_ETH_PDCFG_GMAC2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_GMAC2_EN 0x00000004 -+/** Enable Power Down GMAC1 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_GMAC1 0x00000002 -+/* Disable -+#define SYS_ETH_PDCFG_GMAC1_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_GMAC1_EN 0x00000002 -+/** Enable Power Down GMAC0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_GMAC0 0x00000001 -+/* Disable -+#define SYS_ETH_PDCFG_GMAC0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_GMAC0_EN 0x00000001 -+ -+/* Fields of "Datarate Control Register" */ -+/** MDC Clockrate -+ Selects the clockrate of the MDIO interface. */ -+#define SYS_ETH_DRC_MDC_MASK 0x30000000 -+/** field offset */ -+#define SYS_ETH_DRC_MDC_OFFSET 28 -+/** 312.5/128 = appr. 2.44 MHz. */ -+#define SYS_ETH_DRC_MDC_F2M44 0x00000000 -+/** 312.5/64 = appr. 4.88 MHz. */ -+#define SYS_ETH_DRC_MDC_F4M88 0x10000000 -+/** 312.5/32 = appr. 9.77 MHz. */ -+#define SYS_ETH_DRC_MDC_F9M77 0x20000000 -+/** 312.5/16 = appr. 19.5 MHz. */ -+#define SYS_ETH_DRC_MDC_F19M5 0x30000000 -+/** xMII1 Datarate -+ Selects the datarate of the xMII1 interface. */ -+#define SYS_ETH_DRC_xMII1_MASK 0x07000000 -+/** field offset */ -+#define SYS_ETH_DRC_xMII1_OFFSET 24 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRC_xMII1_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRC_xMII1_DR100 0x01000000 -+/** 1000 MBit/s. */ -+#define SYS_ETH_DRC_xMII1_DR1000 0x02000000 -+/** 200 MBit/s. */ -+#define SYS_ETH_DRC_xMII1_DR200 0x05000000 -+/** xMII0 Datarate -+ Selects the datarate of the xMII0 interface. */ -+#define SYS_ETH_DRC_xMII0_MASK 0x00700000 -+/** field offset */ -+#define SYS_ETH_DRC_xMII0_OFFSET 20 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRC_xMII0_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRC_xMII0_DR100 0x00100000 -+/** 1000 MBit/s. */ -+#define SYS_ETH_DRC_xMII0_DR1000 0x00200000 -+/** 200 MBit/s. */ -+#define SYS_ETH_DRC_xMII0_DR200 0x00500000 -+/** SGMII Datarate -+ Selects the datarate of the SGMII interface. */ -+#define SYS_ETH_DRC_SGMII_MASK 0x00070000 -+/** field offset */ -+#define SYS_ETH_DRC_SGMII_OFFSET 16 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRC_SGMII_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRC_SGMII_DR100 0x00010000 -+/** 1000 MBit/s. */ -+#define SYS_ETH_DRC_SGMII_DR1000 0x00020000 -+/** 2500 MBit/s. */ -+#define SYS_ETH_DRC_SGMII_DR2500 0x00040000 -+/** GPHY1_MII2 Datarate -+ Shows the datarate of the GPHY1_MII2 interface. */ -+#define SYS_ETH_DRC_GPHY1_MII2_MASK 0x00007000 -+/** field offset */ -+#define SYS_ETH_DRC_GPHY1_MII2_OFFSET 12 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRC_GPHY1_MII2_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRC_GPHY1_MII2_DR100 0x00001000 -+/** GPHY1_GMII Datarate -+ Shows the datarate of the GPHY1_GMII interface. */ -+#define SYS_ETH_DRC_GPHY1_GMII_MASK 0x00000700 -+/** field offset */ -+#define SYS_ETH_DRC_GPHY1_GMII_OFFSET 8 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRC_GPHY1_GMII_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRC_GPHY1_GMII_DR100 0x00000100 -+/** 1000 MBit/s. */ -+#define SYS_ETH_DRC_GPHY1_GMII_DR1000 0x00000200 -+/** GPHY0_MII2 Datarate -+ Shows the datarate of the GPHY0_MII2 interface. */ -+#define SYS_ETH_DRC_GPHY0_MII2_MASK 0x00000070 -+/** field offset */ -+#define SYS_ETH_DRC_GPHY0_MII2_OFFSET 4 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRC_GPHY0_MII2_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRC_GPHY0_MII2_DR100 0x00000010 -+/** GPHY0_GMII Datarate -+ Shows the datarate of the GPHY0_GMII interface. */ -+#define SYS_ETH_DRC_GPHY0_GMII_MASK 0x00000007 -+/** field offset */ -+#define SYS_ETH_DRC_GPHY0_GMII_OFFSET 0 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRC_GPHY0_GMII_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRC_GPHY0_GMII_DR100 0x00000001 -+/** 1000 MBit/s. */ -+#define SYS_ETH_DRC_GPHY0_GMII_DR1000 0x00000002 -+ -+/* Fields of "GMAC Multiplexer Control Register" */ -+/** GMAC 3 MUX setting -+ Selects the physical layer to be connected to GMAC3 */ -+#define SYS_ETH_GMUXC_GMAC3_MASK 0x00007000 -+/** field offset */ -+#define SYS_ETH_GMUXC_GMAC3_OFFSET 12 -+/** GMAC connects to GPHY0_GMII interface */ -+#define SYS_ETH_GMUXC_GMAC3_GPHY0_GMII 0x00000000 -+/** GMAC connects to GPHY0_MII2 interface */ -+#define SYS_ETH_GMUXC_GMAC3_GPHY0_MII2 0x00001000 -+/** GMAC connects to GPHY1_GMII interface */ -+#define SYS_ETH_GMUXC_GMAC3_GPHY1_GMII 0x00002000 -+/** GMAC connects to GPHY1_MII2 interface */ -+#define SYS_ETH_GMUXC_GMAC3_GPHY1_MII2 0x00003000 -+/** GMAC connects to SGMII interface */ -+#define SYS_ETH_GMUXC_GMAC3_SGMII 0x00004000 -+/** GMAC connects to xMII0 interface */ -+#define SYS_ETH_GMUXC_GMAC3_xMII0 0x00005000 -+/** GMAC connects to xMII1 interface */ -+#define SYS_ETH_GMUXC_GMAC3_xMII1 0x00006000 -+/** GMAC 2 MUX setting -+ Selects the physical layer to be connected to GMAC2 */ -+#define SYS_ETH_GMUXC_GMAC2_MASK 0x00000700 -+/** field offset */ -+#define SYS_ETH_GMUXC_GMAC2_OFFSET 8 -+/** GMAC connects to GPHY0_GMII interface */ -+#define SYS_ETH_GMUXC_GMAC2_GPHY0_GMII 0x00000000 -+/** GMAC connects to GPHY0_MII2 interface */ -+#define SYS_ETH_GMUXC_GMAC2_GPHY0_MII2 0x00000100 -+/** GMAC connects to GPHY1_GMII interface */ -+#define SYS_ETH_GMUXC_GMAC2_GPHY1_GMII 0x00000200 -+/** GMAC connects to GPHY1_MII2 interface */ -+#define SYS_ETH_GMUXC_GMAC2_GPHY1_MII2 0x00000300 -+/** GMAC connects to SGMII interface */ -+#define SYS_ETH_GMUXC_GMAC2_SGMII 0x00000400 -+/** GMAC connects to xMII0 interface */ -+#define SYS_ETH_GMUXC_GMAC2_xMII0 0x00000500 -+/** GMAC connects to xMII1 interface */ -+#define SYS_ETH_GMUXC_GMAC2_xMII1 0x00000600 -+/** GMAC 1 MUX setting -+ Selects the physical layer to be connected to GMAC1 */ -+#define SYS_ETH_GMUXC_GMAC1_MASK 0x00000070 -+/** field offset */ -+#define SYS_ETH_GMUXC_GMAC1_OFFSET 4 -+/** GMAC connects to GPHY0_GMII interface */ -+#define SYS_ETH_GMUXC_GMAC1_GPHY0_GMII 0x00000000 -+/** GMAC connects to GPHY0_MII2 interface */ -+#define SYS_ETH_GMUXC_GMAC1_GPHY0_MII2 0x00000010 -+/** GMAC connects to GPHY1_GMII interface */ -+#define SYS_ETH_GMUXC_GMAC1_GPHY1_GMII 0x00000020 -+/** GMAC connects to GPHY1_MII2 interface */ -+#define SYS_ETH_GMUXC_GMAC1_GPHY1_MII2 0x00000030 -+/** GMAC connects to SGMII interface */ -+#define SYS_ETH_GMUXC_GMAC1_SGMII 0x00000040 -+/** GMAC connects to xMII0 interface */ -+#define SYS_ETH_GMUXC_GMAC1_xMII0 0x00000050 -+/** GMAC connects to xMII1 interface */ -+#define SYS_ETH_GMUXC_GMAC1_xMII1 0x00000060 -+/** GMAC 0 MUX setting -+ Selects the physical layer to be connected to GMAC0 */ -+#define SYS_ETH_GMUXC_GMAC0_MASK 0x00000007 -+/** field offset */ -+#define SYS_ETH_GMUXC_GMAC0_OFFSET 0 -+/** GMAC connects to GPHY0_GMII interface */ -+#define SYS_ETH_GMUXC_GMAC0_GPHY0_GMII 0x00000000 -+/** GMAC connects to GPHY0_MII2 interface */ -+#define SYS_ETH_GMUXC_GMAC0_GPHY0_MII2 0x00000001 -+/** GMAC connects to GPHY1_GMII interface */ -+#define SYS_ETH_GMUXC_GMAC0_GPHY1_GMII 0x00000002 -+/** GMAC connects to GPHY1_MII2 interface */ -+#define SYS_ETH_GMUXC_GMAC0_GPHY1_MII2 0x00000003 -+/** GMAC connects to SGMII interface */ -+#define SYS_ETH_GMUXC_GMAC0_SGMII 0x00000004 -+/** GMAC connects to xMII0 interface */ -+#define SYS_ETH_GMUXC_GMAC0_xMII0 0x00000005 -+/** GMAC connects to xMII1 interface */ -+#define SYS_ETH_GMUXC_GMAC0_xMII1 0x00000006 -+ -+/* Fields of "Datarate Status Register" */ -+/** GMAC 3 datarate -+ Shows the datarate of GMAC3 */ -+#define SYS_ETH_DRS_GMAC3_MASK 0x00007000 -+/** field offset */ -+#define SYS_ETH_DRS_GMAC3_OFFSET 12 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRS_GMAC3_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRS_GMAC3_DR100 0x00001000 -+/** 1000 MBit/s. */ -+#define SYS_ETH_DRS_GMAC3_DR1000 0x00002000 -+/** 2500 MBit/s. */ -+#define SYS_ETH_DRS_GMAC3_DR2500 0x00004000 -+/** 200 MBit/s. */ -+#define SYS_ETH_DRS_GMAC3_DR200 0x00005000 -+/** GMAC 2 datarate -+ Shows the datarate of GMAC2 */ -+#define SYS_ETH_DRS_GMAC2_MASK 0x00000700 -+/** field offset */ -+#define SYS_ETH_DRS_GMAC2_OFFSET 8 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRS_GMAC2_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRS_GMAC2_DR100 0x00000100 -+/** 1000 MBit/s. */ -+#define SYS_ETH_DRS_GMAC2_DR1000 0x00000200 -+/** 2500 MBit/s. */ -+#define SYS_ETH_DRS_GMAC2_DR2500 0x00000400 -+/** 200 MBit/s. */ -+#define SYS_ETH_DRS_GMAC2_DR200 0x00000500 -+/** GMAC 1 datarate -+ Shows the datarate of GMAC1 */ -+#define SYS_ETH_DRS_GMAC1_MASK 0x00000070 -+/** field offset */ -+#define SYS_ETH_DRS_GMAC1_OFFSET 4 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRS_GMAC1_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRS_GMAC1_DR100 0x00000010 -+/** 1000 MBit/s. */ -+#define SYS_ETH_DRS_GMAC1_DR1000 0x00000020 -+/** 2500 MBit/s. */ -+#define SYS_ETH_DRS_GMAC1_DR2500 0x00000040 -+/** 200 MBit/s. */ -+#define SYS_ETH_DRS_GMAC1_DR200 0x00000050 -+/** GMAC 0 datarate -+ Shows the datarate of GMAC0 */ -+#define SYS_ETH_DRS_GMAC0_MASK 0x00000007 -+/** field offset */ -+#define SYS_ETH_DRS_GMAC0_OFFSET 0 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRS_GMAC0_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRS_GMAC0_DR100 0x00000001 -+/** 1000 MBit/s. */ -+#define SYS_ETH_DRS_GMAC0_DR1000 0x00000002 -+/** 2500 MBit/s. */ -+#define SYS_ETH_DRS_GMAC0_DR2500 0x00000004 -+/** 200 MBit/s. */ -+#define SYS_ETH_DRS_GMAC0_DR200 0x00000005 -+ -+/* Fields of "SGMII Control Register" */ -+/** Auto Negotiation Protocol -+ Selects the TBX/SGMII mode for the autonegotiation of the SGMII interface. */ -+#define SYS_ETH_SGMIIC_ANP 0x00000002 -+/* TBX Mode (IEEE 802.3 Clause 37 ANEG) -+#define SYS_ETH_SGMIIC_ANP_TBXM 0x00000000 */ -+/** SGMII Mode (Cisco Aneg) */ -+#define SYS_ETH_SGMIIC_ANP_SGMIIM 0x00000002 -+/** Auto Negotiation MAC/PHY -+ Selects the MAC/PHY mode for the autonegotiation of the SGMII interface. */ -+#define SYS_ETH_SGMIIC_ANMP 0x00000001 -+/* MAC Mode -+#define SYS_ETH_SGMIIC_ANMP_MAC 0x00000000 */ -+/** PHY Mode */ -+#define SYS_ETH_SGMIIC_ANMP_PHY 0x00000001 -+ -+/*! @} */ /* SYS_ETH_REGISTER */ -+ -+#endif /* _sys_eth_reg_h */ ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/sys_gpe_reg.h -@@ -0,0 +1,2829 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+ -+#ifndef _sys_gpe_reg_h -+#define _sys_gpe_reg_h -+ -+/** \addtogroup SYS_GPE_REGISTER -+ @{ -+*/ -+/* access macros */ -+#define sys_gpe_r32(reg) reg_r32(&sys_gpe->reg) -+#define sys_gpe_w32(val, reg) reg_w32(val, &sys_gpe->reg) -+#define sys_gpe_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys_gpe->reg) -+#define sys_gpe_r32_table(reg, idx) reg_r32_table(sys_gpe->reg, idx) -+#define sys_gpe_w32_table(val, reg, idx) reg_w32_table(val, sys_gpe->reg, idx) -+#define sys_gpe_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys_gpe->reg, idx) -+#define sys_gpe_adr_table(reg, idx) adr_table(sys_gpe->reg, idx) -+ -+ -+/** SYS_GPE register structure */ -+struct gpon_reg_sys_gpe -+{ -+ /** Clock Status Register -+ The clock status reflects the actual clocking mode as a function of the SW settings and the hardware sleep mode. */ -+ unsigned int clks; /* 0x00000000 */ -+ /** Clock Enable Register -+ Via this register the clocks for the domains can be enabled. */ -+ unsigned int clken; /* 0x00000004 */ -+ /** Clock Clear Register -+ Via this register the clocks for the domains can be disabled. */ -+ unsigned int clkclr; /* 0x00000008 */ -+ /** Reserved */ -+ unsigned int res_0[5]; /* 0x0000000C */ -+ /** Activation Status Register */ -+ unsigned int acts; /* 0x00000020 */ -+ /** Activation Register -+ Via this register the domains can be activated. */ -+ unsigned int act; /* 0x00000024 */ -+ /** Deactivation Register -+ Via this register the domains can be deactivated. */ -+ unsigned int deact; /* 0x00000028 */ -+ /** Reboot Trigger Register -+ Via this register the domains can be rebooted (sent through reset). */ -+ unsigned int rbt; /* 0x0000002C */ -+ /** Reserved */ -+ unsigned int res_1[33]; /* 0x00000030 */ -+ /** Power Down Configuration Register -+ Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be removed. */ -+ unsigned int pdcfg; /* 0x000000B4 */ -+ /** Sleep Source Configuration Register -+ All sleep/wakeup conditions selected in this register contribute to the generation of the hardware sleep/wakeup request. Unselected conditions are ignored for sleep and wakeup. If no bit is selected, HW sleep is disabled. */ -+ unsigned int sscfg; /* 0x000000B8 */ -+ /** Sleep Source Timer Register */ -+ unsigned int sst; /* 0x000000BC */ -+ /** Sleep Destination Status Register -+ Shows the status of the sleep destination vector. All clock domains selected in this register will be shutoff in case of a hardware sleep request. These clocks will be automatically reenabled in case of a hardware wakeup request. */ -+ unsigned int sds; /* 0x000000C0 */ -+ /** Sleep Destination Set Register -+ Via this register the the domains to be shutoff in case of a hardware sleep request can be selected. */ -+ unsigned int sdset; /* 0x000000C4 */ -+ /** Sleep Destination Clear Register -+ Via this register the the domains to be shutoff in case of a hardware sleep request can be deselected. */ -+ unsigned int sdclr; /* 0x000000C8 */ -+ /** Reserved */ -+ unsigned int res_2[9]; /* 0x000000CC */ -+ /** IRNCS Capture Register -+ This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNCSEN register. The interrupts can be acknowledged by a write operation. */ -+ unsigned int irncscr; /* 0x000000F0 */ -+ /** IRNCS Interrupt Control Register -+ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ -+ unsigned int irncsicr; /* 0x000000F4 */ -+ /** IRNCS Interrupt Enable Register -+ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCSCR register and are not signalled via the interrupt line towards the controller. */ -+ unsigned int irncsen; /* 0x000000F8 */ -+ /** Reserved */ -+ unsigned int res_3; /* 0x000000FC */ -+}; -+ -+ -+/* Fields of "Clock Status Register" */ -+/** COP7 Clock Enable -+ Shows the clock enable bit for the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ -+#define SYS_GPE_CLKS_COP7 0x80000000 -+/* Disable -+#define SYS_GPE_CLKS_COP7_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_COP7_EN 0x80000000 -+/** COP6 Clock Enable -+ Shows the clock enable bit for the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ -+#define SYS_GPE_CLKS_COP6 0x40000000 -+/* Disable -+#define SYS_GPE_CLKS_COP6_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_COP6_EN 0x40000000 -+/** COP5 Clock Enable -+ Shows the clock enable bit for the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ -+#define SYS_GPE_CLKS_COP5 0x20000000 -+/* Disable -+#define SYS_GPE_CLKS_COP5_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_COP5_EN 0x20000000 -+/** COP4 Clock Enable -+ Shows the clock enable bit for the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ -+#define SYS_GPE_CLKS_COP4 0x10000000 -+/* Disable -+#define SYS_GPE_CLKS_COP4_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_COP4_EN 0x10000000 -+/** COP3 Clock Enable -+ Shows the clock enable bit for the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ -+#define SYS_GPE_CLKS_COP3 0x08000000 -+/* Disable -+#define SYS_GPE_CLKS_COP3_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_COP3_EN 0x08000000 -+/** COP2 Clock Enable -+ Shows the clock enable bit for the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ -+#define SYS_GPE_CLKS_COP2 0x04000000 -+/* Disable -+#define SYS_GPE_CLKS_COP2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_COP2_EN 0x04000000 -+/** COP1 Clock Enable -+ Shows the clock enable bit for the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ -+#define SYS_GPE_CLKS_COP1 0x02000000 -+/* Disable -+#define SYS_GPE_CLKS_COP1_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_COP1_EN 0x02000000 -+/** COP0 Clock Enable -+ Shows the clock enable bit for the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ -+#define SYS_GPE_CLKS_COP0 0x01000000 -+/* Disable -+#define SYS_GPE_CLKS_COP0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_COP0_EN 0x01000000 -+/** PE5 Clock Enable -+ Shows the clock enable bit for the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ -+#define SYS_GPE_CLKS_PE5 0x00200000 -+/* Disable -+#define SYS_GPE_CLKS_PE5_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_PE5_EN 0x00200000 -+/** PE4 Clock Enable -+ Shows the clock enable bit for the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ -+#define SYS_GPE_CLKS_PE4 0x00100000 -+/* Disable -+#define SYS_GPE_CLKS_PE4_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_PE4_EN 0x00100000 -+/** PE3 Clock Enable -+ Shows the clock enable bit for the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ -+#define SYS_GPE_CLKS_PE3 0x00080000 -+/* Disable -+#define SYS_GPE_CLKS_PE3_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_PE3_EN 0x00080000 -+/** PE2 Clock Enable -+ Shows the clock enable bit for the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ -+#define SYS_GPE_CLKS_PE2 0x00040000 -+/* Disable -+#define SYS_GPE_CLKS_PE2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_PE2_EN 0x00040000 -+/** PE1 Clock Enable -+ Shows the clock enable bit for the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ -+#define SYS_GPE_CLKS_PE1 0x00020000 -+/* Disable -+#define SYS_GPE_CLKS_PE1_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_PE1_EN 0x00020000 -+/** PE0 Clock Enable -+ Shows the clock enable bit for the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ -+#define SYS_GPE_CLKS_PE0 0x00010000 -+/* Disable -+#define SYS_GPE_CLKS_PE0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_PE0_EN 0x00010000 -+/** ARB Clock Enable -+ Shows the clock enable bit for the ARB domain. This domain contains the Arbiter. */ -+#define SYS_GPE_CLKS_ARB 0x00002000 -+/* Disable -+#define SYS_GPE_CLKS_ARB_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_ARB_EN 0x00002000 -+/** FSQM Clock Enable -+ Shows the clock enable bit for the FSQM domain. This domain contains the FSQM. */ -+#define SYS_GPE_CLKS_FSQM 0x00001000 -+/* Disable -+#define SYS_GPE_CLKS_FSQM_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_FSQM_EN 0x00001000 -+/** TMU Clock Enable -+ Shows the clock enable bit for the TMU domain. This domain contains the TMU. */ -+#define SYS_GPE_CLKS_TMU 0x00000800 -+/* Disable -+#define SYS_GPE_CLKS_TMU_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_TMU_EN 0x00000800 -+/** MRG Clock Enable -+ Shows the clock enable bit for the MRG domain. This domain contains the Merger. */ -+#define SYS_GPE_CLKS_MRG 0x00000400 -+/* Disable -+#define SYS_GPE_CLKS_MRG_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_MRG_EN 0x00000400 -+/** DISP Clock Enable -+ Shows the clock enable bit for the DISP domain. This domain contains the Dispatcher. */ -+#define SYS_GPE_CLKS_DISP 0x00000200 -+/* Disable -+#define SYS_GPE_CLKS_DISP_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_DISP_EN 0x00000200 -+/** IQM Clock Enable -+ Shows the clock enable bit for the IQM domain. This domain contains the IQM. */ -+#define SYS_GPE_CLKS_IQM 0x00000100 -+/* Disable -+#define SYS_GPE_CLKS_IQM_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_IQM_EN 0x00000100 -+/** CPUE Clock Enable -+ Shows the clock enable bit for the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ -+#define SYS_GPE_CLKS_CPUE 0x00000080 -+/* Disable -+#define SYS_GPE_CLKS_CPUE_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_CPUE_EN 0x00000080 -+/** CPUI Clock Enable -+ Shows the clock enable bit for the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ -+#define SYS_GPE_CLKS_CPUI 0x00000040 -+/* Disable -+#define SYS_GPE_CLKS_CPUI_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_CPUI_EN 0x00000040 -+/** GPONE Clock Enable -+ Shows the clock enable bit for the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ -+#define SYS_GPE_CLKS_GPONE 0x00000020 -+/* Disable -+#define SYS_GPE_CLKS_GPONE_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_GPONE_EN 0x00000020 -+/** GPONI Clock Enable -+ Shows the clock enable bit for the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ -+#define SYS_GPE_CLKS_GPONI 0x00000010 -+/* Disable -+#define SYS_GPE_CLKS_GPONI_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_GPONI_EN 0x00000010 -+/** LAN3 Clock Enable -+ Shows the clock enable bit for the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ -+#define SYS_GPE_CLKS_LAN3 0x00000008 -+/* Disable -+#define SYS_GPE_CLKS_LAN3_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_LAN3_EN 0x00000008 -+/** LAN2 Clock Enable -+ Shows the clock enable bit for the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ -+#define SYS_GPE_CLKS_LAN2 0x00000004 -+/* Disable -+#define SYS_GPE_CLKS_LAN2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_LAN2_EN 0x00000004 -+/** LAN1 Clock Enable -+ Shows the clock enable bit for the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ -+#define SYS_GPE_CLKS_LAN1 0x00000002 -+/* Disable -+#define SYS_GPE_CLKS_LAN1_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_LAN1_EN 0x00000002 -+/** LAN0 Clock Enable -+ Shows the clock enable bit for the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ -+#define SYS_GPE_CLKS_LAN0 0x00000001 -+/* Disable -+#define SYS_GPE_CLKS_LAN0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_LAN0_EN 0x00000001 -+ -+/* Fields of "Clock Enable Register" */ -+/** Set Clock Enable COP7 -+ Sets the clock enable bit of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ -+#define SYS_GPE_CLKEN_COP7 0x80000000 -+/* No-Operation -+#define SYS_GPE_CLKEN_COP7_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_COP7_SET 0x80000000 -+/** Set Clock Enable COP6 -+ Sets the clock enable bit of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ -+#define SYS_GPE_CLKEN_COP6 0x40000000 -+/* No-Operation -+#define SYS_GPE_CLKEN_COP6_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_COP6_SET 0x40000000 -+/** Set Clock Enable COP5 -+ Sets the clock enable bit of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ -+#define SYS_GPE_CLKEN_COP5 0x20000000 -+/* No-Operation -+#define SYS_GPE_CLKEN_COP5_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_COP5_SET 0x20000000 -+/** Set Clock Enable COP4 -+ Sets the clock enable bit of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ -+#define SYS_GPE_CLKEN_COP4 0x10000000 -+/* No-Operation -+#define SYS_GPE_CLKEN_COP4_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_COP4_SET 0x10000000 -+/** Set Clock Enable COP3 -+ Sets the clock enable bit of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ -+#define SYS_GPE_CLKEN_COP3 0x08000000 -+/* No-Operation -+#define SYS_GPE_CLKEN_COP3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_COP3_SET 0x08000000 -+/** Set Clock Enable COP2 -+ Sets the clock enable bit of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ -+#define SYS_GPE_CLKEN_COP2 0x04000000 -+/* No-Operation -+#define SYS_GPE_CLKEN_COP2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_COP2_SET 0x04000000 -+/** Set Clock Enable COP1 -+ Sets the clock enable bit of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ -+#define SYS_GPE_CLKEN_COP1 0x02000000 -+/* No-Operation -+#define SYS_GPE_CLKEN_COP1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_COP1_SET 0x02000000 -+/** Set Clock Enable COP0 -+ Sets the clock enable bit of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ -+#define SYS_GPE_CLKEN_COP0 0x01000000 -+/* No-Operation -+#define SYS_GPE_CLKEN_COP0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_COP0_SET 0x01000000 -+/** Set Clock Enable PE5 -+ Sets the clock enable bit of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ -+#define SYS_GPE_CLKEN_PE5 0x00200000 -+/* No-Operation -+#define SYS_GPE_CLKEN_PE5_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_PE5_SET 0x00200000 -+/** Set Clock Enable PE4 -+ Sets the clock enable bit of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ -+#define SYS_GPE_CLKEN_PE4 0x00100000 -+/* No-Operation -+#define SYS_GPE_CLKEN_PE4_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_PE4_SET 0x00100000 -+/** Set Clock Enable PE3 -+ Sets the clock enable bit of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ -+#define SYS_GPE_CLKEN_PE3 0x00080000 -+/* No-Operation -+#define SYS_GPE_CLKEN_PE3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_PE3_SET 0x00080000 -+/** Set Clock Enable PE2 -+ Sets the clock enable bit of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ -+#define SYS_GPE_CLKEN_PE2 0x00040000 -+/* No-Operation -+#define SYS_GPE_CLKEN_PE2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_PE2_SET 0x00040000 -+/** Set Clock Enable PE1 -+ Sets the clock enable bit of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ -+#define SYS_GPE_CLKEN_PE1 0x00020000 -+/* No-Operation -+#define SYS_GPE_CLKEN_PE1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_PE1_SET 0x00020000 -+/** Set Clock Enable PE0 -+ Sets the clock enable bit of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ -+#define SYS_GPE_CLKEN_PE0 0x00010000 -+/* No-Operation -+#define SYS_GPE_CLKEN_PE0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_PE0_SET 0x00010000 -+/** Set Clock Enable ARB -+ Sets the clock enable bit of the ARB domain. This domain contains the Arbiter. */ -+#define SYS_GPE_CLKEN_ARB 0x00002000 -+/* No-Operation -+#define SYS_GPE_CLKEN_ARB_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_ARB_SET 0x00002000 -+/** Set Clock Enable FSQM -+ Sets the clock enable bit of the FSQM domain. This domain contains the FSQM. */ -+#define SYS_GPE_CLKEN_FSQM 0x00001000 -+/* No-Operation -+#define SYS_GPE_CLKEN_FSQM_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_FSQM_SET 0x00001000 -+/** Set Clock Enable TMU -+ Sets the clock enable bit of the TMU domain. This domain contains the TMU. */ -+#define SYS_GPE_CLKEN_TMU 0x00000800 -+/* No-Operation -+#define SYS_GPE_CLKEN_TMU_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_TMU_SET 0x00000800 -+/** Set Clock Enable MRG -+ Sets the clock enable bit of the MRG domain. This domain contains the Merger. */ -+#define SYS_GPE_CLKEN_MRG 0x00000400 -+/* No-Operation -+#define SYS_GPE_CLKEN_MRG_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_MRG_SET 0x00000400 -+/** Set Clock Enable DISP -+ Sets the clock enable bit of the DISP domain. This domain contains the Dispatcher. */ -+#define SYS_GPE_CLKEN_DISP 0x00000200 -+/* No-Operation -+#define SYS_GPE_CLKEN_DISP_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_DISP_SET 0x00000200 -+/** Set Clock Enable IQM -+ Sets the clock enable bit of the IQM domain. This domain contains the IQM. */ -+#define SYS_GPE_CLKEN_IQM 0x00000100 -+/* No-Operation -+#define SYS_GPE_CLKEN_IQM_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_IQM_SET 0x00000100 -+/** Set Clock Enable CPUE -+ Sets the clock enable bit of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ -+#define SYS_GPE_CLKEN_CPUE 0x00000080 -+/* No-Operation -+#define SYS_GPE_CLKEN_CPUE_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_CPUE_SET 0x00000080 -+/** Set Clock Enable CPUI -+ Sets the clock enable bit of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ -+#define SYS_GPE_CLKEN_CPUI 0x00000040 -+/* No-Operation -+#define SYS_GPE_CLKEN_CPUI_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_CPUI_SET 0x00000040 -+/** Set Clock Enable GPONE -+ Sets the clock enable bit of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ -+#define SYS_GPE_CLKEN_GPONE 0x00000020 -+/* No-Operation -+#define SYS_GPE_CLKEN_GPONE_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_GPONE_SET 0x00000020 -+/** Set Clock Enable GPONI -+ Sets the clock enable bit of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ -+#define SYS_GPE_CLKEN_GPONI 0x00000010 -+/* No-Operation -+#define SYS_GPE_CLKEN_GPONI_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_GPONI_SET 0x00000010 -+/** Set Clock Enable LAN3 -+ Sets the clock enable bit of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ -+#define SYS_GPE_CLKEN_LAN3 0x00000008 -+/* No-Operation -+#define SYS_GPE_CLKEN_LAN3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_LAN3_SET 0x00000008 -+/** Set Clock Enable LAN2 -+ Sets the clock enable bit of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ -+#define SYS_GPE_CLKEN_LAN2 0x00000004 -+/* No-Operation -+#define SYS_GPE_CLKEN_LAN2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_LAN2_SET 0x00000004 -+/** Set Clock Enable LAN1 -+ Sets the clock enable bit of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ -+#define SYS_GPE_CLKEN_LAN1 0x00000002 -+/* No-Operation -+#define SYS_GPE_CLKEN_LAN1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_LAN1_SET 0x00000002 -+/** Set Clock Enable LAN0 -+ Sets the clock enable bit of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ -+#define SYS_GPE_CLKEN_LAN0 0x00000001 -+/* No-Operation -+#define SYS_GPE_CLKEN_LAN0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_LAN0_SET 0x00000001 -+ -+/* Fields of "Clock Clear Register" */ -+/** Clear Clock Enable COP7 -+ Clears the clock enable bit of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ -+#define SYS_GPE_CLKCLR_COP7 0x80000000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_COP7_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_COP7_CLR 0x80000000 -+/** Clear Clock Enable COP6 -+ Clears the clock enable bit of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ -+#define SYS_GPE_CLKCLR_COP6 0x40000000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_COP6_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_COP6_CLR 0x40000000 -+/** Clear Clock Enable COP5 -+ Clears the clock enable bit of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ -+#define SYS_GPE_CLKCLR_COP5 0x20000000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_COP5_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_COP5_CLR 0x20000000 -+/** Clear Clock Enable COP4 -+ Clears the clock enable bit of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ -+#define SYS_GPE_CLKCLR_COP4 0x10000000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_COP4_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_COP4_CLR 0x10000000 -+/** Clear Clock Enable COP3 -+ Clears the clock enable bit of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ -+#define SYS_GPE_CLKCLR_COP3 0x08000000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_COP3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_COP3_CLR 0x08000000 -+/** Clear Clock Enable COP2 -+ Clears the clock enable bit of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ -+#define SYS_GPE_CLKCLR_COP2 0x04000000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_COP2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_COP2_CLR 0x04000000 -+/** Clear Clock Enable COP1 -+ Clears the clock enable bit of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ -+#define SYS_GPE_CLKCLR_COP1 0x02000000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_COP1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_COP1_CLR 0x02000000 -+/** Clear Clock Enable COP0 -+ Clears the clock enable bit of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ -+#define SYS_GPE_CLKCLR_COP0 0x01000000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_COP0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_COP0_CLR 0x01000000 -+/** Clear Clock Enable PE5 -+ Clears the clock enable bit of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ -+#define SYS_GPE_CLKCLR_PE5 0x00200000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_PE5_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_PE5_CLR 0x00200000 -+/** Clear Clock Enable PE4 -+ Clears the clock enable bit of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ -+#define SYS_GPE_CLKCLR_PE4 0x00100000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_PE4_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_PE4_CLR 0x00100000 -+/** Clear Clock Enable PE3 -+ Clears the clock enable bit of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ -+#define SYS_GPE_CLKCLR_PE3 0x00080000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_PE3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_PE3_CLR 0x00080000 -+/** Clear Clock Enable PE2 -+ Clears the clock enable bit of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ -+#define SYS_GPE_CLKCLR_PE2 0x00040000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_PE2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_PE2_CLR 0x00040000 -+/** Clear Clock Enable PE1 -+ Clears the clock enable bit of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ -+#define SYS_GPE_CLKCLR_PE1 0x00020000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_PE1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_PE1_CLR 0x00020000 -+/** Clear Clock Enable PE0 -+ Clears the clock enable bit of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ -+#define SYS_GPE_CLKCLR_PE0 0x00010000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_PE0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_PE0_CLR 0x00010000 -+/** Clear Clock Enable ARB -+ Clears the clock enable bit of the ARB domain. This domain contains the Arbiter. */ -+#define SYS_GPE_CLKCLR_ARB 0x00002000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_ARB_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_ARB_CLR 0x00002000 -+/** Clear Clock Enable FSQM -+ Clears the clock enable bit of the FSQM domain. This domain contains the FSQM. */ -+#define SYS_GPE_CLKCLR_FSQM 0x00001000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_FSQM_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_FSQM_CLR 0x00001000 -+/** Clear Clock Enable TMU -+ Clears the clock enable bit of the TMU domain. This domain contains the TMU. */ -+#define SYS_GPE_CLKCLR_TMU 0x00000800 -+/* No-Operation -+#define SYS_GPE_CLKCLR_TMU_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_TMU_CLR 0x00000800 -+/** Clear Clock Enable MRG -+ Clears the clock enable bit of the MRG domain. This domain contains the Merger. */ -+#define SYS_GPE_CLKCLR_MRG 0x00000400 -+/* No-Operation -+#define SYS_GPE_CLKCLR_MRG_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_MRG_CLR 0x00000400 -+/** Clear Clock Enable DISP -+ Clears the clock enable bit of the DISP domain. This domain contains the Dispatcher. */ -+#define SYS_GPE_CLKCLR_DISP 0x00000200 -+/* No-Operation -+#define SYS_GPE_CLKCLR_DISP_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_DISP_CLR 0x00000200 -+/** Clear Clock Enable IQM -+ Clears the clock enable bit of the IQM domain. This domain contains the IQM. */ -+#define SYS_GPE_CLKCLR_IQM 0x00000100 -+/* No-Operation -+#define SYS_GPE_CLKCLR_IQM_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_IQM_CLR 0x00000100 -+/** Clear Clock Enable CPUE -+ Clears the clock enable bit of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ -+#define SYS_GPE_CLKCLR_CPUE 0x00000080 -+/* No-Operation -+#define SYS_GPE_CLKCLR_CPUE_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_CPUE_CLR 0x00000080 -+/** Clear Clock Enable CPUI -+ Clears the clock enable bit of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ -+#define SYS_GPE_CLKCLR_CPUI 0x00000040 -+/* No-Operation -+#define SYS_GPE_CLKCLR_CPUI_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_CPUI_CLR 0x00000040 -+/** Clear Clock Enable GPONE -+ Clears the clock enable bit of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ -+#define SYS_GPE_CLKCLR_GPONE 0x00000020 -+/* No-Operation -+#define SYS_GPE_CLKCLR_GPONE_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_GPONE_CLR 0x00000020 -+/** Clear Clock Enable GPONI -+ Clears the clock enable bit of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ -+#define SYS_GPE_CLKCLR_GPONI 0x00000010 -+/* No-Operation -+#define SYS_GPE_CLKCLR_GPONI_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_GPONI_CLR 0x00000010 -+/** Clear Clock Enable LAN3 -+ Clears the clock enable bit of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ -+#define SYS_GPE_CLKCLR_LAN3 0x00000008 -+/* No-Operation -+#define SYS_GPE_CLKCLR_LAN3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_LAN3_CLR 0x00000008 -+/** Clear Clock Enable LAN2 -+ Clears the clock enable bit of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ -+#define SYS_GPE_CLKCLR_LAN2 0x00000004 -+/* No-Operation -+#define SYS_GPE_CLKCLR_LAN2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_LAN2_CLR 0x00000004 -+/** Clear Clock Enable LAN1 -+ Clears the clock enable bit of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ -+#define SYS_GPE_CLKCLR_LAN1 0x00000002 -+/* No-Operation -+#define SYS_GPE_CLKCLR_LAN1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_LAN1_CLR 0x00000002 -+/** Clear Clock Enable LAN0 -+ Clears the clock enable bit of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ -+#define SYS_GPE_CLKCLR_LAN0 0x00000001 -+/* No-Operation -+#define SYS_GPE_CLKCLR_LAN0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_LAN0_CLR 0x00000001 -+ -+/* Fields of "Activation Status Register" */ -+/** COP7 Status -+ Shows the activation status of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ -+#define SYS_GPE_ACTS_COP7 0x80000000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_COP7_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_COP7_ACT 0x80000000 -+/** COP6 Status -+ Shows the activation status of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ -+#define SYS_GPE_ACTS_COP6 0x40000000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_COP6_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_COP6_ACT 0x40000000 -+/** COP5 Status -+ Shows the activation status of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ -+#define SYS_GPE_ACTS_COP5 0x20000000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_COP5_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_COP5_ACT 0x20000000 -+/** COP4 Status -+ Shows the activation status of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ -+#define SYS_GPE_ACTS_COP4 0x10000000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_COP4_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_COP4_ACT 0x10000000 -+/** COP3 Status -+ Shows the activation status of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ -+#define SYS_GPE_ACTS_COP3 0x08000000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_COP3_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_COP3_ACT 0x08000000 -+/** COP2 Status -+ Shows the activation status of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ -+#define SYS_GPE_ACTS_COP2 0x04000000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_COP2_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_COP2_ACT 0x04000000 -+/** COP1 Status -+ Shows the activation status of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ -+#define SYS_GPE_ACTS_COP1 0x02000000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_COP1_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_COP1_ACT 0x02000000 -+/** COP0 Status -+ Shows the activation status of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ -+#define SYS_GPE_ACTS_COP0 0x01000000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_COP0_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_COP0_ACT 0x01000000 -+/** PE5 Status -+ Shows the activation status of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ -+#define SYS_GPE_ACTS_PE5 0x00200000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_PE5_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_PE5_ACT 0x00200000 -+/** PE4 Status -+ Shows the activation status of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ -+#define SYS_GPE_ACTS_PE4 0x00100000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_PE4_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_PE4_ACT 0x00100000 -+/** PE3 Status -+ Shows the activation status of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ -+#define SYS_GPE_ACTS_PE3 0x00080000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_PE3_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_PE3_ACT 0x00080000 -+/** PE2 Status -+ Shows the activation status of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ -+#define SYS_GPE_ACTS_PE2 0x00040000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_PE2_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_PE2_ACT 0x00040000 -+/** PE1 Status -+ Shows the activation status of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ -+#define SYS_GPE_ACTS_PE1 0x00020000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_PE1_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_PE1_ACT 0x00020000 -+/** PE0 Status -+ Shows the activation status of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ -+#define SYS_GPE_ACTS_PE0 0x00010000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_PE0_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_PE0_ACT 0x00010000 -+/** ARB Status -+ Shows the activation status of the ARB domain. This domain contains the Arbiter. */ -+#define SYS_GPE_ACTS_ARB 0x00002000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_ARB_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_ARB_ACT 0x00002000 -+/** FSQM Status -+ Shows the activation status of the FSQM domain. This domain contains the FSQM. */ -+#define SYS_GPE_ACTS_FSQM 0x00001000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_FSQM_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_FSQM_ACT 0x00001000 -+/** TMU Status -+ Shows the activation status of the TMU domain. This domain contains the TMU. */ -+#define SYS_GPE_ACTS_TMU 0x00000800 -+/* The block is inactive. -+#define SYS_GPE_ACTS_TMU_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_TMU_ACT 0x00000800 -+/** MRG Status -+ Shows the activation status of the MRG domain. This domain contains the Merger. */ -+#define SYS_GPE_ACTS_MRG 0x00000400 -+/* The block is inactive. -+#define SYS_GPE_ACTS_MRG_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_MRG_ACT 0x00000400 -+/** DISP Status -+ Shows the activation status of the DISP domain. This domain contains the Dispatcher. */ -+#define SYS_GPE_ACTS_DISP 0x00000200 -+/* The block is inactive. -+#define SYS_GPE_ACTS_DISP_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_DISP_ACT 0x00000200 -+/** IQM Status -+ Shows the activation status of the IQM domain. This domain contains the IQM. */ -+#define SYS_GPE_ACTS_IQM 0x00000100 -+/* The block is inactive. -+#define SYS_GPE_ACTS_IQM_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_IQM_ACT 0x00000100 -+/** CPUE Status -+ Shows the activation status of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ -+#define SYS_GPE_ACTS_CPUE 0x00000080 -+/* The block is inactive. -+#define SYS_GPE_ACTS_CPUE_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_CPUE_ACT 0x00000080 -+/** CPUI Status -+ Shows the activation status of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ -+#define SYS_GPE_ACTS_CPUI 0x00000040 -+/* The block is inactive. -+#define SYS_GPE_ACTS_CPUI_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_CPUI_ACT 0x00000040 -+/** GPONE Status -+ Shows the activation status of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ -+#define SYS_GPE_ACTS_GPONE 0x00000020 -+/* The block is inactive. -+#define SYS_GPE_ACTS_GPONE_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_GPONE_ACT 0x00000020 -+/** GPONI Status -+ Shows the activation status of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ -+#define SYS_GPE_ACTS_GPONI 0x00000010 -+/* The block is inactive. -+#define SYS_GPE_ACTS_GPONI_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_GPONI_ACT 0x00000010 -+/** LAN3 Status -+ Shows the activation status of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ -+#define SYS_GPE_ACTS_LAN3 0x00000008 -+/* The block is inactive. -+#define SYS_GPE_ACTS_LAN3_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_LAN3_ACT 0x00000008 -+/** LAN2 Status -+ Shows the activation status of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ -+#define SYS_GPE_ACTS_LAN2 0x00000004 -+/* The block is inactive. -+#define SYS_GPE_ACTS_LAN2_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_LAN2_ACT 0x00000004 -+/** LAN1 Status -+ Shows the activation status of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ -+#define SYS_GPE_ACTS_LAN1 0x00000002 -+/* The block is inactive. -+#define SYS_GPE_ACTS_LAN1_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_LAN1_ACT 0x00000002 -+/** LAN0 Status -+ Shows the activation status of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ -+#define SYS_GPE_ACTS_LAN0 0x00000001 -+/* The block is inactive. -+#define SYS_GPE_ACTS_LAN0_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_LAN0_ACT 0x00000001 -+ -+/* Fields of "Activation Register" */ -+/** Activate COP7 -+ Sets the activation flag of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ -+#define SYS_GPE_ACT_COP7 0x80000000 -+/* No-Operation -+#define SYS_GPE_ACT_COP7_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_COP7_SET 0x80000000 -+/** Activate COP6 -+ Sets the activation flag of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ -+#define SYS_GPE_ACT_COP6 0x40000000 -+/* No-Operation -+#define SYS_GPE_ACT_COP6_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_COP6_SET 0x40000000 -+/** Activate COP5 -+ Sets the activation flag of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ -+#define SYS_GPE_ACT_COP5 0x20000000 -+/* No-Operation -+#define SYS_GPE_ACT_COP5_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_COP5_SET 0x20000000 -+/** Activate COP4 -+ Sets the activation flag of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ -+#define SYS_GPE_ACT_COP4 0x10000000 -+/* No-Operation -+#define SYS_GPE_ACT_COP4_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_COP4_SET 0x10000000 -+/** Activate COP3 -+ Sets the activation flag of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ -+#define SYS_GPE_ACT_COP3 0x08000000 -+/* No-Operation -+#define SYS_GPE_ACT_COP3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_COP3_SET 0x08000000 -+/** Activate COP2 -+ Sets the activation flag of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ -+#define SYS_GPE_ACT_COP2 0x04000000 -+/* No-Operation -+#define SYS_GPE_ACT_COP2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_COP2_SET 0x04000000 -+/** Activate COP1 -+ Sets the activation flag of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ -+#define SYS_GPE_ACT_COP1 0x02000000 -+/* No-Operation -+#define SYS_GPE_ACT_COP1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_COP1_SET 0x02000000 -+/** Activate COP0 -+ Sets the activation flag of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ -+#define SYS_GPE_ACT_COP0 0x01000000 -+/* No-Operation -+#define SYS_GPE_ACT_COP0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_COP0_SET 0x01000000 -+/** Activate PE5 -+ Sets the activation flag of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ -+#define SYS_GPE_ACT_PE5 0x00200000 -+/* No-Operation -+#define SYS_GPE_ACT_PE5_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_PE5_SET 0x00200000 -+/** Activate PE4 -+ Sets the activation flag of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ -+#define SYS_GPE_ACT_PE4 0x00100000 -+/* No-Operation -+#define SYS_GPE_ACT_PE4_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_PE4_SET 0x00100000 -+/** Activate PE3 -+ Sets the activation flag of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ -+#define SYS_GPE_ACT_PE3 0x00080000 -+/* No-Operation -+#define SYS_GPE_ACT_PE3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_PE3_SET 0x00080000 -+/** Activate PE2 -+ Sets the activation flag of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ -+#define SYS_GPE_ACT_PE2 0x00040000 -+/* No-Operation -+#define SYS_GPE_ACT_PE2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_PE2_SET 0x00040000 -+/** Activate PE1 -+ Sets the activation flag of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ -+#define SYS_GPE_ACT_PE1 0x00020000 -+/* No-Operation -+#define SYS_GPE_ACT_PE1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_PE1_SET 0x00020000 -+/** Activate PE0 -+ Sets the activation flag of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ -+#define SYS_GPE_ACT_PE0 0x00010000 -+/* No-Operation -+#define SYS_GPE_ACT_PE0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_PE0_SET 0x00010000 -+/** Activate ARB -+ Sets the activation flag of the ARB domain. This domain contains the Arbiter. */ -+#define SYS_GPE_ACT_ARB 0x00002000 -+/* No-Operation -+#define SYS_GPE_ACT_ARB_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_ARB_SET 0x00002000 -+/** Activate FSQM -+ Sets the activation flag of the FSQM domain. This domain contains the FSQM. */ -+#define SYS_GPE_ACT_FSQM 0x00001000 -+/* No-Operation -+#define SYS_GPE_ACT_FSQM_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_FSQM_SET 0x00001000 -+/** Activate TMU -+ Sets the activation flag of the TMU domain. This domain contains the TMU. */ -+#define SYS_GPE_ACT_TMU 0x00000800 -+/* No-Operation -+#define SYS_GPE_ACT_TMU_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_TMU_SET 0x00000800 -+/** Activate MRG -+ Sets the activation flag of the MRG domain. This domain contains the Merger. */ -+#define SYS_GPE_ACT_MRG 0x00000400 -+/* No-Operation -+#define SYS_GPE_ACT_MRG_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_MRG_SET 0x00000400 -+/** Activate DISP -+ Sets the activation flag of the DISP domain. This domain contains the Dispatcher. */ -+#define SYS_GPE_ACT_DISP 0x00000200 -+/* No-Operation -+#define SYS_GPE_ACT_DISP_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_DISP_SET 0x00000200 -+/** Activate IQM -+ Sets the activation flag of the IQM domain. This domain contains the IQM. */ -+#define SYS_GPE_ACT_IQM 0x00000100 -+/* No-Operation -+#define SYS_GPE_ACT_IQM_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_IQM_SET 0x00000100 -+/** Activate CPUE -+ Sets the activation flag of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ -+#define SYS_GPE_ACT_CPUE 0x00000080 -+/* No-Operation -+#define SYS_GPE_ACT_CPUE_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_CPUE_SET 0x00000080 -+/** Activate CPUI -+ Sets the activation flag of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ -+#define SYS_GPE_ACT_CPUI 0x00000040 -+/* No-Operation -+#define SYS_GPE_ACT_CPUI_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_CPUI_SET 0x00000040 -+/** Activate GPONE -+ Sets the activation flag of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ -+#define SYS_GPE_ACT_GPONE 0x00000020 -+/* No-Operation -+#define SYS_GPE_ACT_GPONE_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_GPONE_SET 0x00000020 -+/** Activate GPONI -+ Sets the activation flag of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ -+#define SYS_GPE_ACT_GPONI 0x00000010 -+/* No-Operation -+#define SYS_GPE_ACT_GPONI_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_GPONI_SET 0x00000010 -+/** Activate LAN3 -+ Sets the activation flag of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ -+#define SYS_GPE_ACT_LAN3 0x00000008 -+/* No-Operation -+#define SYS_GPE_ACT_LAN3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_LAN3_SET 0x00000008 -+/** Activate LAN2 -+ Sets the activation flag of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ -+#define SYS_GPE_ACT_LAN2 0x00000004 -+/* No-Operation -+#define SYS_GPE_ACT_LAN2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_LAN2_SET 0x00000004 -+/** Activate LAN1 -+ Sets the activation flag of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ -+#define SYS_GPE_ACT_LAN1 0x00000002 -+/* No-Operation -+#define SYS_GPE_ACT_LAN1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_LAN1_SET 0x00000002 -+/** Activate LAN0 -+ Sets the activation flag of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ -+#define SYS_GPE_ACT_LAN0 0x00000001 -+/* No-Operation -+#define SYS_GPE_ACT_LAN0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_LAN0_SET 0x00000001 -+ -+/* Fields of "Deactivation Register" */ -+/** Deactivate COP7 -+ Clears the activation flag of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ -+#define SYS_GPE_DEACT_COP7 0x80000000 -+/* No-Operation -+#define SYS_GPE_DEACT_COP7_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_COP7_CLR 0x80000000 -+/** Deactivate COP6 -+ Clears the activation flag of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ -+#define SYS_GPE_DEACT_COP6 0x40000000 -+/* No-Operation -+#define SYS_GPE_DEACT_COP6_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_COP6_CLR 0x40000000 -+/** Deactivate COP5 -+ Clears the activation flag of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ -+#define SYS_GPE_DEACT_COP5 0x20000000 -+/* No-Operation -+#define SYS_GPE_DEACT_COP5_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_COP5_CLR 0x20000000 -+/** Deactivate COP4 -+ Clears the activation flag of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ -+#define SYS_GPE_DEACT_COP4 0x10000000 -+/* No-Operation -+#define SYS_GPE_DEACT_COP4_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_COP4_CLR 0x10000000 -+/** Deactivate COP3 -+ Clears the activation flag of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ -+#define SYS_GPE_DEACT_COP3 0x08000000 -+/* No-Operation -+#define SYS_GPE_DEACT_COP3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_COP3_CLR 0x08000000 -+/** Deactivate COP2 -+ Clears the activation flag of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ -+#define SYS_GPE_DEACT_COP2 0x04000000 -+/* No-Operation -+#define SYS_GPE_DEACT_COP2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_COP2_CLR 0x04000000 -+/** Deactivate COP1 -+ Clears the activation flag of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ -+#define SYS_GPE_DEACT_COP1 0x02000000 -+/* No-Operation -+#define SYS_GPE_DEACT_COP1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_COP1_CLR 0x02000000 -+/** Deactivate COP0 -+ Clears the activation flag of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ -+#define SYS_GPE_DEACT_COP0 0x01000000 -+/* No-Operation -+#define SYS_GPE_DEACT_COP0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_COP0_CLR 0x01000000 -+/** Deactivate PE5 -+ Clears the activation flag of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ -+#define SYS_GPE_DEACT_PE5 0x00200000 -+/* No-Operation -+#define SYS_GPE_DEACT_PE5_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_PE5_CLR 0x00200000 -+/** Deactivate PE4 -+ Clears the activation flag of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ -+#define SYS_GPE_DEACT_PE4 0x00100000 -+/* No-Operation -+#define SYS_GPE_DEACT_PE4_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_PE4_CLR 0x00100000 -+/** Deactivate PE3 -+ Clears the activation flag of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ -+#define SYS_GPE_DEACT_PE3 0x00080000 -+/* No-Operation -+#define SYS_GPE_DEACT_PE3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_PE3_CLR 0x00080000 -+/** Deactivate PE2 -+ Clears the activation flag of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ -+#define SYS_GPE_DEACT_PE2 0x00040000 -+/* No-Operation -+#define SYS_GPE_DEACT_PE2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_PE2_CLR 0x00040000 -+/** Deactivate PE1 -+ Clears the activation flag of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ -+#define SYS_GPE_DEACT_PE1 0x00020000 -+/* No-Operation -+#define SYS_GPE_DEACT_PE1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_PE1_CLR 0x00020000 -+/** Deactivate PE0 -+ Clears the activation flag of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ -+#define SYS_GPE_DEACT_PE0 0x00010000 -+/* No-Operation -+#define SYS_GPE_DEACT_PE0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_PE0_CLR 0x00010000 -+/** Deactivate ARB -+ Clears the activation flag of the ARB domain. This domain contains the Arbiter. */ -+#define SYS_GPE_DEACT_ARB 0x00002000 -+/* No-Operation -+#define SYS_GPE_DEACT_ARB_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_ARB_CLR 0x00002000 -+/** Deactivate FSQM -+ Clears the activation flag of the FSQM domain. This domain contains the FSQM. */ -+#define SYS_GPE_DEACT_FSQM 0x00001000 -+/* No-Operation -+#define SYS_GPE_DEACT_FSQM_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_FSQM_CLR 0x00001000 -+/** Deactivate TMU -+ Clears the activation flag of the TMU domain. This domain contains the TMU. */ -+#define SYS_GPE_DEACT_TMU 0x00000800 -+/* No-Operation -+#define SYS_GPE_DEACT_TMU_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_TMU_CLR 0x00000800 -+/** Deactivate MRG -+ Clears the activation flag of the MRG domain. This domain contains the Merger. */ -+#define SYS_GPE_DEACT_MRG 0x00000400 -+/* No-Operation -+#define SYS_GPE_DEACT_MRG_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_MRG_CLR 0x00000400 -+/** Deactivate DISP -+ Clears the activation flag of the DISP domain. This domain contains the Dispatcher. */ -+#define SYS_GPE_DEACT_DISP 0x00000200 -+/* No-Operation -+#define SYS_GPE_DEACT_DISP_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_DISP_CLR 0x00000200 -+/** Deactivate IQM -+ Clears the activation flag of the IQM domain. This domain contains the IQM. */ -+#define SYS_GPE_DEACT_IQM 0x00000100 -+/* No-Operation -+#define SYS_GPE_DEACT_IQM_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_IQM_CLR 0x00000100 -+/** Deactivate CPUE -+ Clears the activation flag of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ -+#define SYS_GPE_DEACT_CPUE 0x00000080 -+/* No-Operation -+#define SYS_GPE_DEACT_CPUE_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_CPUE_CLR 0x00000080 -+/** Deactivate CPUI -+ Clears the activation flag of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ -+#define SYS_GPE_DEACT_CPUI 0x00000040 -+/* No-Operation -+#define SYS_GPE_DEACT_CPUI_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_CPUI_CLR 0x00000040 -+/** Deactivate GPONE -+ Clears the activation flag of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ -+#define SYS_GPE_DEACT_GPONE 0x00000020 -+/* No-Operation -+#define SYS_GPE_DEACT_GPONE_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_GPONE_CLR 0x00000020 -+/** Deactivate GPONI -+ Clears the activation flag of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ -+#define SYS_GPE_DEACT_GPONI 0x00000010 -+/* No-Operation -+#define SYS_GPE_DEACT_GPONI_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_GPONI_CLR 0x00000010 -+/** Deactivate LAN3 -+ Clears the activation flag of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ -+#define SYS_GPE_DEACT_LAN3 0x00000008 -+/* No-Operation -+#define SYS_GPE_DEACT_LAN3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_LAN3_CLR 0x00000008 -+/** Deactivate LAN2 -+ Clears the activation flag of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ -+#define SYS_GPE_DEACT_LAN2 0x00000004 -+/* No-Operation -+#define SYS_GPE_DEACT_LAN2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_LAN2_CLR 0x00000004 -+/** Deactivate LAN1 -+ Clears the activation flag of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ -+#define SYS_GPE_DEACT_LAN1 0x00000002 -+/* No-Operation -+#define SYS_GPE_DEACT_LAN1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_LAN1_CLR 0x00000002 -+/** Deactivate LAN0 -+ Clears the activation flag of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ -+#define SYS_GPE_DEACT_LAN0 0x00000001 -+/* No-Operation -+#define SYS_GPE_DEACT_LAN0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_LAN0_CLR 0x00000001 -+ -+/* Fields of "Reboot Trigger Register" */ -+/** Reboot COP7 -+ Triggers a reboot of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ -+#define SYS_GPE_RBT_COP7 0x80000000 -+/* No-Operation -+#define SYS_GPE_RBT_COP7_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_COP7_TRIG 0x80000000 -+/** Reboot COP6 -+ Triggers a reboot of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ -+#define SYS_GPE_RBT_COP6 0x40000000 -+/* No-Operation -+#define SYS_GPE_RBT_COP6_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_COP6_TRIG 0x40000000 -+/** Reboot COP5 -+ Triggers a reboot of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ -+#define SYS_GPE_RBT_COP5 0x20000000 -+/* No-Operation -+#define SYS_GPE_RBT_COP5_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_COP5_TRIG 0x20000000 -+/** Reboot COP4 -+ Triggers a reboot of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ -+#define SYS_GPE_RBT_COP4 0x10000000 -+/* No-Operation -+#define SYS_GPE_RBT_COP4_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_COP4_TRIG 0x10000000 -+/** Reboot COP3 -+ Triggers a reboot of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ -+#define SYS_GPE_RBT_COP3 0x08000000 -+/* No-Operation -+#define SYS_GPE_RBT_COP3_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_COP3_TRIG 0x08000000 -+/** Reboot COP2 -+ Triggers a reboot of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ -+#define SYS_GPE_RBT_COP2 0x04000000 -+/* No-Operation -+#define SYS_GPE_RBT_COP2_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_COP2_TRIG 0x04000000 -+/** Reboot COP1 -+ Triggers a reboot of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ -+#define SYS_GPE_RBT_COP1 0x02000000 -+/* No-Operation -+#define SYS_GPE_RBT_COP1_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_COP1_TRIG 0x02000000 -+/** Reboot COP0 -+ Triggers a reboot of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ -+#define SYS_GPE_RBT_COP0 0x01000000 -+/* No-Operation -+#define SYS_GPE_RBT_COP0_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_COP0_TRIG 0x01000000 -+/** Reboot PE5 -+ Triggers a reboot of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ -+#define SYS_GPE_RBT_PE5 0x00200000 -+/* No-Operation -+#define SYS_GPE_RBT_PE5_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_PE5_TRIG 0x00200000 -+/** Reboot PE4 -+ Triggers a reboot of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ -+#define SYS_GPE_RBT_PE4 0x00100000 -+/* No-Operation -+#define SYS_GPE_RBT_PE4_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_PE4_TRIG 0x00100000 -+/** Reboot PE3 -+ Triggers a reboot of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ -+#define SYS_GPE_RBT_PE3 0x00080000 -+/* No-Operation -+#define SYS_GPE_RBT_PE3_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_PE3_TRIG 0x00080000 -+/** Reboot PE2 -+ Triggers a reboot of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ -+#define SYS_GPE_RBT_PE2 0x00040000 -+/* No-Operation -+#define SYS_GPE_RBT_PE2_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_PE2_TRIG 0x00040000 -+/** Reboot PE1 -+ Triggers a reboot of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ -+#define SYS_GPE_RBT_PE1 0x00020000 -+/* No-Operation -+#define SYS_GPE_RBT_PE1_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_PE1_TRIG 0x00020000 -+/** Reboot PE0 -+ Triggers a reboot of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ -+#define SYS_GPE_RBT_PE0 0x00010000 -+/* No-Operation -+#define SYS_GPE_RBT_PE0_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_PE0_TRIG 0x00010000 -+/** Reboot ARB -+ Triggers a reboot of the ARB domain. This domain contains the Arbiter. */ -+#define SYS_GPE_RBT_ARB 0x00002000 -+/* No-Operation -+#define SYS_GPE_RBT_ARB_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_ARB_TRIG 0x00002000 -+/** Reboot FSQM -+ Triggers a reboot of the FSQM domain. This domain contains the FSQM. */ -+#define SYS_GPE_RBT_FSQM 0x00001000 -+/* No-Operation -+#define SYS_GPE_RBT_FSQM_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_FSQM_TRIG 0x00001000 -+/** Reboot TMU -+ Triggers a reboot of the TMU domain. This domain contains the TMU. */ -+#define SYS_GPE_RBT_TMU 0x00000800 -+/* No-Operation -+#define SYS_GPE_RBT_TMU_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_TMU_TRIG 0x00000800 -+/** Reboot MRG -+ Triggers a reboot of the MRG domain. This domain contains the Merger. */ -+#define SYS_GPE_RBT_MRG 0x00000400 -+/* No-Operation -+#define SYS_GPE_RBT_MRG_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_MRG_TRIG 0x00000400 -+/** Reboot DISP -+ Triggers a reboot of the DISP domain. This domain contains the Dispatcher. */ -+#define SYS_GPE_RBT_DISP 0x00000200 -+/* No-Operation -+#define SYS_GPE_RBT_DISP_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_DISP_TRIG 0x00000200 -+/** Reboot IQM -+ Triggers a reboot of the IQM domain. This domain contains the IQM. */ -+#define SYS_GPE_RBT_IQM 0x00000100 -+/* No-Operation -+#define SYS_GPE_RBT_IQM_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_IQM_TRIG 0x00000100 -+/** Reboot CPUE -+ Triggers a reboot of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ -+#define SYS_GPE_RBT_CPUE 0x00000080 -+/* No-Operation -+#define SYS_GPE_RBT_CPUE_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_CPUE_TRIG 0x00000080 -+/** Reboot CPUI -+ Triggers a reboot of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ -+#define SYS_GPE_RBT_CPUI 0x00000040 -+/* No-Operation -+#define SYS_GPE_RBT_CPUI_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_CPUI_TRIG 0x00000040 -+/** Reboot GPONE -+ Triggers a reboot of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ -+#define SYS_GPE_RBT_GPONE 0x00000020 -+/* No-Operation -+#define SYS_GPE_RBT_GPONE_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_GPONE_TRIG 0x00000020 -+/** Reboot GPONI -+ Triggers a reboot of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ -+#define SYS_GPE_RBT_GPONI 0x00000010 -+/* No-Operation -+#define SYS_GPE_RBT_GPONI_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_GPONI_TRIG 0x00000010 -+/** Reboot LAN3 -+ Triggers a reboot of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ -+#define SYS_GPE_RBT_LAN3 0x00000008 -+/* No-Operation -+#define SYS_GPE_RBT_LAN3_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_LAN3_TRIG 0x00000008 -+/** Reboot LAN2 -+ Triggers a reboot of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ -+#define SYS_GPE_RBT_LAN2 0x00000004 -+/* No-Operation -+#define SYS_GPE_RBT_LAN2_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_LAN2_TRIG 0x00000004 -+/** Reboot LAN1 -+ Triggers a reboot of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ -+#define SYS_GPE_RBT_LAN1 0x00000002 -+/* No-Operation -+#define SYS_GPE_RBT_LAN1_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_LAN1_TRIG 0x00000002 -+/** Reboot LAN0 -+ Triggers a reboot of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ -+#define SYS_GPE_RBT_LAN0 0x00000001 -+/* No-Operation -+#define SYS_GPE_RBT_LAN0_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_LAN0_TRIG 0x00000001 -+ -+/* Fields of "Power Down Configuration Register" */ -+/** Enable Power Down COP7 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_COP7 0x80000000 -+/* Disable -+#define SYS_GPE_PDCFG_COP7_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_COP7_EN 0x80000000 -+/** Enable Power Down COP6 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_COP6 0x40000000 -+/* Disable -+#define SYS_GPE_PDCFG_COP6_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_COP6_EN 0x40000000 -+/** Enable Power Down COP5 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_COP5 0x20000000 -+/* Disable -+#define SYS_GPE_PDCFG_COP5_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_COP5_EN 0x20000000 -+/** Enable Power Down COP4 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_COP4 0x10000000 -+/* Disable -+#define SYS_GPE_PDCFG_COP4_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_COP4_EN 0x10000000 -+/** Enable Power Down COP3 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_COP3 0x08000000 -+/* Disable -+#define SYS_GPE_PDCFG_COP3_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_COP3_EN 0x08000000 -+/** Enable Power Down COP2 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_COP2 0x04000000 -+/* Disable -+#define SYS_GPE_PDCFG_COP2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_COP2_EN 0x04000000 -+/** Enable Power Down COP1 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_COP1 0x02000000 -+/* Disable -+#define SYS_GPE_PDCFG_COP1_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_COP1_EN 0x02000000 -+/** Enable Power Down COP0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_COP0 0x01000000 -+/* Disable -+#define SYS_GPE_PDCFG_COP0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_COP0_EN 0x01000000 -+/** Enable Power Down PE5 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_PE5 0x00200000 -+/* Disable -+#define SYS_GPE_PDCFG_PE5_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_PE5_EN 0x00200000 -+/** Enable Power Down PE4 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_PE4 0x00100000 -+/* Disable -+#define SYS_GPE_PDCFG_PE4_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_PE4_EN 0x00100000 -+/** Enable Power Down PE3 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_PE3 0x00080000 -+/* Disable -+#define SYS_GPE_PDCFG_PE3_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_PE3_EN 0x00080000 -+/** Enable Power Down PE2 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_PE2 0x00040000 -+/* Disable -+#define SYS_GPE_PDCFG_PE2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_PE2_EN 0x00040000 -+/** Enable Power Down PE1 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_PE1 0x00020000 -+/* Disable -+#define SYS_GPE_PDCFG_PE1_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_PE1_EN 0x00020000 -+/** Enable Power Down PE0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_PE0 0x00010000 -+/* Disable -+#define SYS_GPE_PDCFG_PE0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_PE0_EN 0x00010000 -+/** Enable Power Down ARB -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_ARB 0x00002000 -+/* Disable -+#define SYS_GPE_PDCFG_ARB_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_ARB_EN 0x00002000 -+/** Enable Power Down FSQM -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_FSQM 0x00001000 -+/* Disable -+#define SYS_GPE_PDCFG_FSQM_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_FSQM_EN 0x00001000 -+/** Enable Power Down TMU -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_TMU 0x00000800 -+/* Disable -+#define SYS_GPE_PDCFG_TMU_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_TMU_EN 0x00000800 -+/** Enable Power Down MRG -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_MRG 0x00000400 -+/* Disable -+#define SYS_GPE_PDCFG_MRG_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_MRG_EN 0x00000400 -+/** Enable Power Down DISP -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_DISP 0x00000200 -+/* Disable -+#define SYS_GPE_PDCFG_DISP_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_DISP_EN 0x00000200 -+/** Enable Power Down IQM -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_IQM 0x00000100 -+/* Disable -+#define SYS_GPE_PDCFG_IQM_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_IQM_EN 0x00000100 -+/** Enable Power Down CPUE -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_CPUE 0x00000080 -+/* Disable -+#define SYS_GPE_PDCFG_CPUE_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_CPUE_EN 0x00000080 -+/** Enable Power Down CPUI -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_CPUI 0x00000040 -+/* Disable -+#define SYS_GPE_PDCFG_CPUI_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_CPUI_EN 0x00000040 -+/** Enable Power Down GPONE -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_GPONE 0x00000020 -+/* Disable -+#define SYS_GPE_PDCFG_GPONE_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_GPONE_EN 0x00000020 -+/** Enable Power Down GPONI -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_GPONI 0x00000010 -+/* Disable -+#define SYS_GPE_PDCFG_GPONI_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_GPONI_EN 0x00000010 -+/** Enable Power Down LAN3 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_LAN3 0x00000008 -+/* Disable -+#define SYS_GPE_PDCFG_LAN3_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_LAN3_EN 0x00000008 -+/** Enable Power Down LAN2 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_LAN2 0x00000004 -+/* Disable -+#define SYS_GPE_PDCFG_LAN2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_LAN2_EN 0x00000004 -+/** Enable Power Down LAN1 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_LAN1 0x00000002 -+/* Disable -+#define SYS_GPE_PDCFG_LAN1_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_LAN1_EN 0x00000002 -+/** Enable Power Down LAN0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_LAN0 0x00000001 -+/* Disable -+#define SYS_GPE_PDCFG_LAN0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_LAN0_EN 0x00000001 -+ -+/* Fields of "Sleep Source Configuration Register" */ -+/** Sleep/Wakeup Source CPU -+ Selects the CPU access signal as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_CPU 0x00020000 -+/* Not selected -+#define SYS_GPE_SSCFG_CPU_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_CPU_SEL 0x00020000 -+/** Sleep/Wakeup Source FSQM -+ Selects the FSQM signal as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_FSQM 0x00008000 -+/* Not selected -+#define SYS_GPE_SSCFG_FSQM_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_FSQM_SEL 0x00008000 -+/** Sleep/Wakeup Source GPONT -+ Selects the FIFO empty signal of the TCONT Request FIFO of port GPON as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_GPONT 0x00002000 -+/* Not selected -+#define SYS_GPE_SSCFG_GPONT_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_GPONT_SEL 0x00002000 -+/** Sleep/Wakeup Source GPONE -+ Selects the FIFO empty signal of the EGRESS FIFO of port GPON as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_GPONE 0x00001000 -+/* Not selected -+#define SYS_GPE_SSCFG_GPONE_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_GPONE_SEL 0x00001000 -+/** Sleep/Wakeup Source LAN3E -+ Selects the FIFO empty signal of the EGRESS FIFO of port LAN3 as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_LAN3E 0x00000800 -+/* Not selected -+#define SYS_GPE_SSCFG_LAN3E_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_LAN3E_SEL 0x00000800 -+/** Sleep/Wakeup Source LAN2E -+ Selects the FIFO empty signal of the EGRESS FIFO of port LAN2 as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_LAN2E 0x00000400 -+/* Not selected -+#define SYS_GPE_SSCFG_LAN2E_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_LAN2E_SEL 0x00000400 -+/** Sleep/Wakeup Source LAN1E -+ Selects the FIFO empty signal of the EGRESS FIFO of port LAN1 as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_LAN1E 0x00000200 -+/* Not selected -+#define SYS_GPE_SSCFG_LAN1E_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_LAN1E_SEL 0x00000200 -+/** Sleep/Wakeup Source LAN0E -+ Selects the FIFO empty signal of the EGRESS FIFO of port LAN0 as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_LAN0E 0x00000100 -+/* Not selected -+#define SYS_GPE_SSCFG_LAN0E_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_LAN0E_SEL 0x00000100 -+/** Sleep/Wakeup Source GPONI -+ Selects the FIFO empty signal of the INGRESS FIFO of port GPON as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_GPONI 0x00000010 -+/* Not selected -+#define SYS_GPE_SSCFG_GPONI_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_GPONI_SEL 0x00000010 -+/** Sleep/Wakeup Source LAN3I -+ Selects the FIFO empty signal of the INGRESS FIFO of port LAN3 as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_LAN3I 0x00000008 -+/* Not selected -+#define SYS_GPE_SSCFG_LAN3I_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_LAN3I_SEL 0x00000008 -+/** Sleep/Wakeup Source LAN2I -+ Selects the FIFO empty signal of the INGRESS FIFO of port LAN2 as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_LAN2I 0x00000004 -+/* Not selected -+#define SYS_GPE_SSCFG_LAN2I_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_LAN2I_SEL 0x00000004 -+/** Sleep/Wakeup Source LAN1I -+ Selects the FIFO empty signal of the INGRESS FIFO of port LAN1 as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_LAN1I 0x00000002 -+/* Not selected -+#define SYS_GPE_SSCFG_LAN1I_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_LAN1I_SEL 0x00000002 -+/** Sleep/Wakeup Source LAN0I -+ Selects the FIFO empty signal of the INGRESS FIFO of port LAN0 as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_LAN0I 0x00000001 -+/* Not selected -+#define SYS_GPE_SSCFG_LAN0I_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_LAN0I_SEL 0x00000001 -+ -+/* Fields of "Sleep Source Timer Register" */ -+/** Sleep Delay Value -+ A HW sleep request is delayed by this value multiplied by 3.2ns before it takes effect. A wakeup request is not delayed but takes effect immediately. Values lower than 256 are limited to 256. */ -+#define SYS_GPE_SST_SDV_MASK 0x7FFFFFFF -+/** field offset */ -+#define SYS_GPE_SST_SDV_OFFSET 0 -+ -+/* Fields of "Sleep Destination Status Register" */ -+/** Shutoff COP7 on HW Sleep -+ If selected the domain COP7 is shutoff on a hardware sleep request. This domain contains the Coprocessor 7 of the SCE. */ -+#define SYS_GPE_SDS_COP7 0x80000000 -+/* Not selected -+#define SYS_GPE_SDS_COP7_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_COP7_SEL 0x80000000 -+/** Shutoff COP6 on HW Sleep -+ If selected the domain COP6 is shutoff on a hardware sleep request. This domain contains the Coprocessor 6 of the SCE. */ -+#define SYS_GPE_SDS_COP6 0x40000000 -+/* Not selected -+#define SYS_GPE_SDS_COP6_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_COP6_SEL 0x40000000 -+/** Shutoff COP5 on HW Sleep -+ If selected the domain COP5 is shutoff on a hardware sleep request. This domain contains the Coprocessor 5 of the SCE. */ -+#define SYS_GPE_SDS_COP5 0x20000000 -+/* Not selected -+#define SYS_GPE_SDS_COP5_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_COP5_SEL 0x20000000 -+/** Shutoff COP4 on HW Sleep -+ If selected the domain COP4 is shutoff on a hardware sleep request. This domain contains the Coprocessor 4 of the SCE. */ -+#define SYS_GPE_SDS_COP4 0x10000000 -+/* Not selected -+#define SYS_GPE_SDS_COP4_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_COP4_SEL 0x10000000 -+/** Shutoff COP3 on HW Sleep -+ If selected the domain COP3 is shutoff on a hardware sleep request. This domain contains the Coprocessor 3 of the SCE. */ -+#define SYS_GPE_SDS_COP3 0x08000000 -+/* Not selected -+#define SYS_GPE_SDS_COP3_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_COP3_SEL 0x08000000 -+/** Shutoff COP2 on HW Sleep -+ If selected the domain COP2 is shutoff on a hardware sleep request. This domain contains the Coprocessor 2 of the SCE. */ -+#define SYS_GPE_SDS_COP2 0x04000000 -+/* Not selected -+#define SYS_GPE_SDS_COP2_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_COP2_SEL 0x04000000 -+/** Shutoff COP1 on HW Sleep -+ If selected the domain COP1 is shutoff on a hardware sleep request. This domain contains the Coprocessor 1 of the SCE. */ -+#define SYS_GPE_SDS_COP1 0x02000000 -+/* Not selected -+#define SYS_GPE_SDS_COP1_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_COP1_SEL 0x02000000 -+/** Shutoff COP0 on HW Sleep -+ If selected the domain COP0 is shutoff on a hardware sleep request. This domain contains the Coprocessor 0 of the SCE. */ -+#define SYS_GPE_SDS_COP0 0x01000000 -+/* Not selected -+#define SYS_GPE_SDS_COP0_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_COP0_SEL 0x01000000 -+/** Shutoff PE5 on HW Sleep -+ If selected the domain PE5 is shutoff on a hardware sleep request. This domain contains the Processing Element 5 of the SCE. */ -+#define SYS_GPE_SDS_PE5 0x00200000 -+/* Not selected -+#define SYS_GPE_SDS_PE5_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_PE5_SEL 0x00200000 -+/** Shutoff PE4 on HW Sleep -+ If selected the domain PE4 is shutoff on a hardware sleep request. This domain contains the Processing Element 4 of the SCE. */ -+#define SYS_GPE_SDS_PE4 0x00100000 -+/* Not selected -+#define SYS_GPE_SDS_PE4_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_PE4_SEL 0x00100000 -+/** Shutoff PE3 on HW Sleep -+ If selected the domain PE3 is shutoff on a hardware sleep request. This domain contains the Processing Element 3 of the SCE. */ -+#define SYS_GPE_SDS_PE3 0x00080000 -+/* Not selected -+#define SYS_GPE_SDS_PE3_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_PE3_SEL 0x00080000 -+/** Shutoff PE2 on HW Sleep -+ If selected the domain PE2 is shutoff on a hardware sleep request. This domain contains the Processing Element 2 of the SCE. */ -+#define SYS_GPE_SDS_PE2 0x00040000 -+/* Not selected -+#define SYS_GPE_SDS_PE2_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_PE2_SEL 0x00040000 -+/** Shutoff PE1 on HW Sleep -+ If selected the domain PE1 is shutoff on a hardware sleep request. This domain contains the Processing Element 1 of the SCE. */ -+#define SYS_GPE_SDS_PE1 0x00020000 -+/* Not selected -+#define SYS_GPE_SDS_PE1_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_PE1_SEL 0x00020000 -+/** Shutoff PE0 on HW Sleep -+ If selected the domain PE0 is shutoff on a hardware sleep request. This domain contains the Processing Element 0 of the SCE. */ -+#define SYS_GPE_SDS_PE0 0x00010000 -+/* Not selected -+#define SYS_GPE_SDS_PE0_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_PE0_SEL 0x00010000 -+/** Shutoff ARB on HW Sleep -+ If selected the domain ARB is shutoff on a hardware sleep request. This domain contains the Arbiter. */ -+#define SYS_GPE_SDS_ARB 0x00002000 -+/* Not selected -+#define SYS_GPE_SDS_ARB_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_ARB_SEL 0x00002000 -+/** Shutoff FSQM on HW Sleep -+ If selected the domain FSQM is shutoff on a hardware sleep request. This domain contains the FSQM. */ -+#define SYS_GPE_SDS_FSQM 0x00001000 -+/* Not selected -+#define SYS_GPE_SDS_FSQM_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_FSQM_SEL 0x00001000 -+/** Shutoff TMU on HW Sleep -+ If selected the domain TMU is shutoff on a hardware sleep request. This domain contains the TMU. */ -+#define SYS_GPE_SDS_TMU 0x00000800 -+/* Not selected -+#define SYS_GPE_SDS_TMU_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_TMU_SEL 0x00000800 -+/** Shutoff MRG on HW Sleep -+ If selected the domain MRG is shutoff on a hardware sleep request. This domain contains the Merger. */ -+#define SYS_GPE_SDS_MRG 0x00000400 -+/* Not selected -+#define SYS_GPE_SDS_MRG_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_MRG_SEL 0x00000400 -+/** Shutoff DISP on HW Sleep -+ If selected the domain DISP is shutoff on a hardware sleep request. This domain contains the Dispatcher. */ -+#define SYS_GPE_SDS_DISP 0x00000200 -+/* Not selected -+#define SYS_GPE_SDS_DISP_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_DISP_SEL 0x00000200 -+/** Shutoff IQM on HW Sleep -+ If selected the domain IQM is shutoff on a hardware sleep request. This domain contains the IQM. */ -+#define SYS_GPE_SDS_IQM 0x00000100 -+/* Not selected -+#define SYS_GPE_SDS_IQM_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_IQM_SEL 0x00000100 -+/** Shutoff CPUE on HW Sleep -+ If selected the domain CPUE is shutoff on a hardware sleep request. This domain contains all parts related to the CPU EGRESS interface. */ -+#define SYS_GPE_SDS_CPUE 0x00000080 -+/* Not selected -+#define SYS_GPE_SDS_CPUE_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_CPUE_SEL 0x00000080 -+/** Shutoff CPUI on HW Sleep -+ If selected the domain CPUI is shutoff on a hardware sleep request. This domain contains all parts related to the CPU INGRESS interface. */ -+#define SYS_GPE_SDS_CPUI 0x00000040 -+/* Not selected -+#define SYS_GPE_SDS_CPUI_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_CPUI_SEL 0x00000040 -+/** Shutoff GPONE on HW Sleep -+ If selected the domain GPONE is shutoff on a hardware sleep request. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ -+#define SYS_GPE_SDS_GPONE 0x00000020 -+/* Not selected -+#define SYS_GPE_SDS_GPONE_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_GPONE_SEL 0x00000020 -+/** Shutoff GPONI on HW Sleep -+ If selected the domain GPONI is shutoff on a hardware sleep request. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ -+#define SYS_GPE_SDS_GPONI 0x00000010 -+/* Not selected -+#define SYS_GPE_SDS_GPONI_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_GPONI_SEL 0x00000010 -+/** Shutoff LAN3 on HW Sleep -+ If selected the domain LAN3 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN3 interface. */ -+#define SYS_GPE_SDS_LAN3 0x00000008 -+/* Not selected -+#define SYS_GPE_SDS_LAN3_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_LAN3_SEL 0x00000008 -+/** Shutoff LAN2 on HW Sleep -+ If selected the domain LAN2 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN2 interface. */ -+#define SYS_GPE_SDS_LAN2 0x00000004 -+/* Not selected -+#define SYS_GPE_SDS_LAN2_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_LAN2_SEL 0x00000004 -+/** Shutoff LAN1 on HW Sleep -+ If selected the domain LAN1 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN1 interface. */ -+#define SYS_GPE_SDS_LAN1 0x00000002 -+/* Not selected -+#define SYS_GPE_SDS_LAN1_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_LAN1_SEL 0x00000002 -+/** Shutoff LAN0 on HW Sleep -+ If selected the domain LAN0 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN0 interface. */ -+#define SYS_GPE_SDS_LAN0 0x00000001 -+/* Not selected -+#define SYS_GPE_SDS_LAN0_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_LAN0_SEL 0x00000001 -+ -+/* Fields of "Sleep Destination Set Register" */ -+/** Set Sleep Selection COP7 -+ Sets the selection bit for domain COP7This domain contains the Coprocessor 7 of the SCE. */ -+#define SYS_GPE_SDSET_COP7 0x80000000 -+/* No-Operation -+#define SYS_GPE_SDSET_COP7_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_COP7_SET 0x80000000 -+/** Set Sleep Selection COP6 -+ Sets the selection bit for domain COP6This domain contains the Coprocessor 6 of the SCE. */ -+#define SYS_GPE_SDSET_COP6 0x40000000 -+/* No-Operation -+#define SYS_GPE_SDSET_COP6_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_COP6_SET 0x40000000 -+/** Set Sleep Selection COP5 -+ Sets the selection bit for domain COP5This domain contains the Coprocessor 5 of the SCE. */ -+#define SYS_GPE_SDSET_COP5 0x20000000 -+/* No-Operation -+#define SYS_GPE_SDSET_COP5_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_COP5_SET 0x20000000 -+/** Set Sleep Selection COP4 -+ Sets the selection bit for domain COP4This domain contains the Coprocessor 4 of the SCE. */ -+#define SYS_GPE_SDSET_COP4 0x10000000 -+/* No-Operation -+#define SYS_GPE_SDSET_COP4_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_COP4_SET 0x10000000 -+/** Set Sleep Selection COP3 -+ Sets the selection bit for domain COP3This domain contains the Coprocessor 3 of the SCE. */ -+#define SYS_GPE_SDSET_COP3 0x08000000 -+/* No-Operation -+#define SYS_GPE_SDSET_COP3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_COP3_SET 0x08000000 -+/** Set Sleep Selection COP2 -+ Sets the selection bit for domain COP2This domain contains the Coprocessor 2 of the SCE. */ -+#define SYS_GPE_SDSET_COP2 0x04000000 -+/* No-Operation -+#define SYS_GPE_SDSET_COP2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_COP2_SET 0x04000000 -+/** Set Sleep Selection COP1 -+ Sets the selection bit for domain COP1This domain contains the Coprocessor 1 of the SCE. */ -+#define SYS_GPE_SDSET_COP1 0x02000000 -+/* No-Operation -+#define SYS_GPE_SDSET_COP1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_COP1_SET 0x02000000 -+/** Set Sleep Selection COP0 -+ Sets the selection bit for domain COP0This domain contains the Coprocessor 0 of the SCE. */ -+#define SYS_GPE_SDSET_COP0 0x01000000 -+/* No-Operation -+#define SYS_GPE_SDSET_COP0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_COP0_SET 0x01000000 -+/** Set Sleep Selection PE5 -+ Sets the selection bit for domain PE5This domain contains the Processing Element 5 of the SCE. */ -+#define SYS_GPE_SDSET_PE5 0x00200000 -+/* No-Operation -+#define SYS_GPE_SDSET_PE5_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_PE5_SET 0x00200000 -+/** Set Sleep Selection PE4 -+ Sets the selection bit for domain PE4This domain contains the Processing Element 4 of the SCE. */ -+#define SYS_GPE_SDSET_PE4 0x00100000 -+/* No-Operation -+#define SYS_GPE_SDSET_PE4_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_PE4_SET 0x00100000 -+/** Set Sleep Selection PE3 -+ Sets the selection bit for domain PE3This domain contains the Processing Element 3 of the SCE. */ -+#define SYS_GPE_SDSET_PE3 0x00080000 -+/* No-Operation -+#define SYS_GPE_SDSET_PE3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_PE3_SET 0x00080000 -+/** Set Sleep Selection PE2 -+ Sets the selection bit for domain PE2This domain contains the Processing Element 2 of the SCE. */ -+#define SYS_GPE_SDSET_PE2 0x00040000 -+/* No-Operation -+#define SYS_GPE_SDSET_PE2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_PE2_SET 0x00040000 -+/** Set Sleep Selection PE1 -+ Sets the selection bit for domain PE1This domain contains the Processing Element 1 of the SCE. */ -+#define SYS_GPE_SDSET_PE1 0x00020000 -+/* No-Operation -+#define SYS_GPE_SDSET_PE1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_PE1_SET 0x00020000 -+/** Set Sleep Selection PE0 -+ Sets the selection bit for domain PE0This domain contains the Processing Element 0 of the SCE. */ -+#define SYS_GPE_SDSET_PE0 0x00010000 -+/* No-Operation -+#define SYS_GPE_SDSET_PE0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_PE0_SET 0x00010000 -+/** Set Sleep Selection ARB -+ Sets the selection bit for domain ARBThis domain contains the Arbiter. */ -+#define SYS_GPE_SDSET_ARB 0x00002000 -+/* No-Operation -+#define SYS_GPE_SDSET_ARB_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_ARB_SET 0x00002000 -+/** Set Sleep Selection FSQM -+ Sets the selection bit for domain FSQMThis domain contains the FSQM. */ -+#define SYS_GPE_SDSET_FSQM 0x00001000 -+/* No-Operation -+#define SYS_GPE_SDSET_FSQM_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_FSQM_SET 0x00001000 -+/** Set Sleep Selection TMU -+ Sets the selection bit for domain TMUThis domain contains the TMU. */ -+#define SYS_GPE_SDSET_TMU 0x00000800 -+/* No-Operation -+#define SYS_GPE_SDSET_TMU_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_TMU_SET 0x00000800 -+/** Set Sleep Selection MRG -+ Sets the selection bit for domain MRGThis domain contains the Merger. */ -+#define SYS_GPE_SDSET_MRG 0x00000400 -+/* No-Operation -+#define SYS_GPE_SDSET_MRG_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_MRG_SET 0x00000400 -+/** Set Sleep Selection DISP -+ Sets the selection bit for domain DISPThis domain contains the Dispatcher. */ -+#define SYS_GPE_SDSET_DISP 0x00000200 -+/* No-Operation -+#define SYS_GPE_SDSET_DISP_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_DISP_SET 0x00000200 -+/** Set Sleep Selection IQM -+ Sets the selection bit for domain IQMThis domain contains the IQM. */ -+#define SYS_GPE_SDSET_IQM 0x00000100 -+/* No-Operation -+#define SYS_GPE_SDSET_IQM_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_IQM_SET 0x00000100 -+/** Set Sleep Selection CPUE -+ Sets the selection bit for domain CPUEThis domain contains all parts related to the CPU EGRESS interface. */ -+#define SYS_GPE_SDSET_CPUE 0x00000080 -+/* No-Operation -+#define SYS_GPE_SDSET_CPUE_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_CPUE_SET 0x00000080 -+/** Set Sleep Selection CPUI -+ Sets the selection bit for domain CPUIThis domain contains all parts related to the CPU INGRESS interface. */ -+#define SYS_GPE_SDSET_CPUI 0x00000040 -+/* No-Operation -+#define SYS_GPE_SDSET_CPUI_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_CPUI_SET 0x00000040 -+/** Set Sleep Selection GPONE -+ Sets the selection bit for domain GPONEThis domain contains all parts related to the GPON (GTC) EGRESS interface. */ -+#define SYS_GPE_SDSET_GPONE 0x00000020 -+/* No-Operation -+#define SYS_GPE_SDSET_GPONE_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_GPONE_SET 0x00000020 -+/** Set Sleep Selection GPONI -+ Sets the selection bit for domain GPONIThis domain contains all parts related to the GPON (GTC) INGRESS interface. */ -+#define SYS_GPE_SDSET_GPONI 0x00000010 -+/* No-Operation -+#define SYS_GPE_SDSET_GPONI_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_GPONI_SET 0x00000010 -+/** Set Sleep Selection LAN3 -+ Sets the selection bit for domain LAN3This domain contains all parts related to the LAN3 interface. */ -+#define SYS_GPE_SDSET_LAN3 0x00000008 -+/* No-Operation -+#define SYS_GPE_SDSET_LAN3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_LAN3_SET 0x00000008 -+/** Set Sleep Selection LAN2 -+ Sets the selection bit for domain LAN2This domain contains all parts related to the LAN2 interface. */ -+#define SYS_GPE_SDSET_LAN2 0x00000004 -+/* No-Operation -+#define SYS_GPE_SDSET_LAN2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_LAN2_SET 0x00000004 -+/** Set Sleep Selection LAN1 -+ Sets the selection bit for domain LAN1This domain contains all parts related to the LAN1 interface. */ -+#define SYS_GPE_SDSET_LAN1 0x00000002 -+/* No-Operation -+#define SYS_GPE_SDSET_LAN1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_LAN1_SET 0x00000002 -+/** Set Sleep Selection LAN0 -+ Sets the selection bit for domain LAN0This domain contains all parts related to the LAN0 interface. */ -+#define SYS_GPE_SDSET_LAN0 0x00000001 -+/* No-Operation -+#define SYS_GPE_SDSET_LAN0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_LAN0_SET 0x00000001 -+ -+/* Fields of "Sleep Destination Clear Register" */ -+/** Clear Sleep Selection COP7 -+ Clears the selection bit for domain COP7This domain contains the Coprocessor 7 of the SCE. */ -+#define SYS_GPE_SDCLR_COP7 0x80000000 -+/* No-Operation -+#define SYS_GPE_SDCLR_COP7_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_COP7_CLR 0x80000000 -+/** Clear Sleep Selection COP6 -+ Clears the selection bit for domain COP6This domain contains the Coprocessor 6 of the SCE. */ -+#define SYS_GPE_SDCLR_COP6 0x40000000 -+/* No-Operation -+#define SYS_GPE_SDCLR_COP6_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_COP6_CLR 0x40000000 -+/** Clear Sleep Selection COP5 -+ Clears the selection bit for domain COP5This domain contains the Coprocessor 5 of the SCE. */ -+#define SYS_GPE_SDCLR_COP5 0x20000000 -+/* No-Operation -+#define SYS_GPE_SDCLR_COP5_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_COP5_CLR 0x20000000 -+/** Clear Sleep Selection COP4 -+ Clears the selection bit for domain COP4This domain contains the Coprocessor 4 of the SCE. */ -+#define SYS_GPE_SDCLR_COP4 0x10000000 -+/* No-Operation -+#define SYS_GPE_SDCLR_COP4_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_COP4_CLR 0x10000000 -+/** Clear Sleep Selection COP3 -+ Clears the selection bit for domain COP3This domain contains the Coprocessor 3 of the SCE. */ -+#define SYS_GPE_SDCLR_COP3 0x08000000 -+/* No-Operation -+#define SYS_GPE_SDCLR_COP3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_COP3_CLR 0x08000000 -+/** Clear Sleep Selection COP2 -+ Clears the selection bit for domain COP2This domain contains the Coprocessor 2 of the SCE. */ -+#define SYS_GPE_SDCLR_COP2 0x04000000 -+/* No-Operation -+#define SYS_GPE_SDCLR_COP2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_COP2_CLR 0x04000000 -+/** Clear Sleep Selection COP1 -+ Clears the selection bit for domain COP1This domain contains the Coprocessor 1 of the SCE. */ -+#define SYS_GPE_SDCLR_COP1 0x02000000 -+/* No-Operation -+#define SYS_GPE_SDCLR_COP1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_COP1_CLR 0x02000000 -+/** Clear Sleep Selection COP0 -+ Clears the selection bit for domain COP0This domain contains the Coprocessor 0 of the SCE. */ -+#define SYS_GPE_SDCLR_COP0 0x01000000 -+/* No-Operation -+#define SYS_GPE_SDCLR_COP0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_COP0_CLR 0x01000000 -+/** Clear Sleep Selection PE5 -+ Clears the selection bit for domain PE5This domain contains the Processing Element 5 of the SCE. */ -+#define SYS_GPE_SDCLR_PE5 0x00200000 -+/* No-Operation -+#define SYS_GPE_SDCLR_PE5_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_PE5_CLR 0x00200000 -+/** Clear Sleep Selection PE4 -+ Clears the selection bit for domain PE4This domain contains the Processing Element 4 of the SCE. */ -+#define SYS_GPE_SDCLR_PE4 0x00100000 -+/* No-Operation -+#define SYS_GPE_SDCLR_PE4_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_PE4_CLR 0x00100000 -+/** Clear Sleep Selection PE3 -+ Clears the selection bit for domain PE3This domain contains the Processing Element 3 of the SCE. */ -+#define SYS_GPE_SDCLR_PE3 0x00080000 -+/* No-Operation -+#define SYS_GPE_SDCLR_PE3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_PE3_CLR 0x00080000 -+/** Clear Sleep Selection PE2 -+ Clears the selection bit for domain PE2This domain contains the Processing Element 2 of the SCE. */ -+#define SYS_GPE_SDCLR_PE2 0x00040000 -+/* No-Operation -+#define SYS_GPE_SDCLR_PE2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_PE2_CLR 0x00040000 -+/** Clear Sleep Selection PE1 -+ Clears the selection bit for domain PE1This domain contains the Processing Element 1 of the SCE. */ -+#define SYS_GPE_SDCLR_PE1 0x00020000 -+/* No-Operation -+#define SYS_GPE_SDCLR_PE1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_PE1_CLR 0x00020000 -+/** Clear Sleep Selection PE0 -+ Clears the selection bit for domain PE0This domain contains the Processing Element 0 of the SCE. */ -+#define SYS_GPE_SDCLR_PE0 0x00010000 -+/* No-Operation -+#define SYS_GPE_SDCLR_PE0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_PE0_CLR 0x00010000 -+/** Clear Sleep Selection ARB -+ Clears the selection bit for domain ARBThis domain contains the Arbiter. */ -+#define SYS_GPE_SDCLR_ARB 0x00002000 -+/* No-Operation -+#define SYS_GPE_SDCLR_ARB_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_ARB_CLR 0x00002000 -+/** Clear Sleep Selection FSQM -+ Clears the selection bit for domain FSQMThis domain contains the FSQM. */ -+#define SYS_GPE_SDCLR_FSQM 0x00001000 -+/* No-Operation -+#define SYS_GPE_SDCLR_FSQM_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_FSQM_CLR 0x00001000 -+/** Clear Sleep Selection TMU -+ Clears the selection bit for domain TMUThis domain contains the TMU. */ -+#define SYS_GPE_SDCLR_TMU 0x00000800 -+/* No-Operation -+#define SYS_GPE_SDCLR_TMU_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_TMU_CLR 0x00000800 -+/** Clear Sleep Selection MRG -+ Clears the selection bit for domain MRGThis domain contains the Merger. */ -+#define SYS_GPE_SDCLR_MRG 0x00000400 -+/* No-Operation -+#define SYS_GPE_SDCLR_MRG_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_MRG_CLR 0x00000400 -+/** Clear Sleep Selection DISP -+ Clears the selection bit for domain DISPThis domain contains the Dispatcher. */ -+#define SYS_GPE_SDCLR_DISP 0x00000200 -+/* No-Operation -+#define SYS_GPE_SDCLR_DISP_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_DISP_CLR 0x00000200 -+/** Clear Sleep Selection IQM -+ Clears the selection bit for domain IQMThis domain contains the IQM. */ -+#define SYS_GPE_SDCLR_IQM 0x00000100 -+/* No-Operation -+#define SYS_GPE_SDCLR_IQM_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_IQM_CLR 0x00000100 -+/** Clear Sleep Selection CPUE -+ Clears the selection bit for domain CPUEThis domain contains all parts related to the CPU EGRESS interface. */ -+#define SYS_GPE_SDCLR_CPUE 0x00000080 -+/* No-Operation -+#define SYS_GPE_SDCLR_CPUE_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_CPUE_CLR 0x00000080 -+/** Clear Sleep Selection CPUI -+ Clears the selection bit for domain CPUIThis domain contains all parts related to the CPU INGRESS interface. */ -+#define SYS_GPE_SDCLR_CPUI 0x00000040 -+/* No-Operation -+#define SYS_GPE_SDCLR_CPUI_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_CPUI_CLR 0x00000040 -+/** Clear Sleep Selection GPONE -+ Clears the selection bit for domain GPONEThis domain contains all parts related to the GPON (GTC) EGRESS interface. */ -+#define SYS_GPE_SDCLR_GPONE 0x00000020 -+/* No-Operation -+#define SYS_GPE_SDCLR_GPONE_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_GPONE_CLR 0x00000020 -+/** Clear Sleep Selection GPONI -+ Clears the selection bit for domain GPONIThis domain contains all parts related to the GPON (GTC) INGRESS interface. */ -+#define SYS_GPE_SDCLR_GPONI 0x00000010 -+/* No-Operation -+#define SYS_GPE_SDCLR_GPONI_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_GPONI_CLR 0x00000010 -+/** Clear Sleep Selection LAN3 -+ Clears the selection bit for domain LAN3This domain contains all parts related to the LAN3 interface. */ -+#define SYS_GPE_SDCLR_LAN3 0x00000008 -+/* No-Operation -+#define SYS_GPE_SDCLR_LAN3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_LAN3_CLR 0x00000008 -+/** Clear Sleep Selection LAN2 -+ Clears the selection bit for domain LAN2This domain contains all parts related to the LAN2 interface. */ -+#define SYS_GPE_SDCLR_LAN2 0x00000004 -+/* No-Operation -+#define SYS_GPE_SDCLR_LAN2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_LAN2_CLR 0x00000004 -+/** Clear Sleep Selection LAN1 -+ Clears the selection bit for domain LAN1This domain contains all parts related to the LAN1 interface. */ -+#define SYS_GPE_SDCLR_LAN1 0x00000002 -+/* No-Operation -+#define SYS_GPE_SDCLR_LAN1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_LAN1_CLR 0x00000002 -+/** Clear Sleep Selection LAN0 -+ Clears the selection bit for domain LAN0This domain contains all parts related to the LAN0 interface. */ -+#define SYS_GPE_SDCLR_LAN0 0x00000001 -+/* No-Operation -+#define SYS_GPE_SDCLR_LAN0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_LAN0_CLR 0x00000001 -+ -+/* Fields of "IRNCS Capture Register" */ -+/** FSQM wakeup request -+ The FSQM submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_FSQMWR 0x80000000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_FSQMWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_FSQMWR_INTACK 0x80000000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_FSQMWR_INTOCC 0x80000000 -+/** GPONT wakeup request -+ The TCONT Request FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONTWR 0x20000000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_GPONTWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONTWR_INTACK 0x20000000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_GPONTWR_INTOCC 0x20000000 -+/** GPONE wakeup request -+ The EGRESS FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONEWR 0x10000000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_GPONEWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONEWR_INTACK 0x10000000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_GPONEWR_INTOCC 0x10000000 -+/** LAN3E wakeup request -+ The EGRESS FIFO of port LAN3 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN3EWR 0x08000000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN3EWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN3EWR_INTACK 0x08000000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN3EWR_INTOCC 0x08000000 -+/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request. -+ This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN2EWR 0x04000000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN2EWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN2EWR_INTACK 0x04000000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN2EWR_INTOCC 0x04000000 -+/** LAN1E wakeup request -+ The EGRESS FIFO of port LAN1 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN1EWR 0x02000000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN1EWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN1EWR_INTACK 0x02000000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN1EWR_INTOCC 0x02000000 -+/** LAN0E wakeup request -+ The EGRESS FIFO of port LAN0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN0EWR 0x01000000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN0EWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN0EWR_INTACK 0x01000000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN0EWR_INTOCC 0x01000000 -+/** GPONI wakeup request -+ The INGRESS FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONIWR 0x00100000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_GPONIWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONIWR_INTACK 0x00100000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_GPONIWR_INTOCC 0x00100000 -+/** LAN3I wakeup request -+ The INGRESS FIFO of port LAN3 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN3IWR 0x00080000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN3IWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN3IWR_INTACK 0x00080000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN3IWR_INTOCC 0x00080000 -+/** LAN2I wakeup request -+ The INGRESS FIFO of port LAN2 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN2IWR 0x00040000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN2IWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN2IWR_INTACK 0x00040000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN2IWR_INTOCC 0x00040000 -+/** LAN1I wakeup request -+ The INGRESS FIFO of port LAN1 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN1IWR 0x00020000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN1IWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN1IWR_INTACK 0x00020000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN1IWR_INTOCC 0x00020000 -+/** LAN0I wakeup request -+ The INGRESS FIFO of port LAN0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN0IWR 0x00010000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN0IWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN0IWR_INTACK 0x00010000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN0IWR_INTOCC 0x00010000 -+/** FSQM sleep request -+ The FSQM submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_FSQMSR 0x00008000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_FSQMSR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_FSQMSR_INTACK 0x00008000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_FSQMSR_INTOCC 0x00008000 -+/** GPONT sleep request -+ The TCONT Request FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONTSR 0x00002000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_GPONTSR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONTSR_INTACK 0x00002000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_GPONTSR_INTOCC 0x00002000 -+/** GPONE sleep request -+ The EGRESS FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONESR 0x00001000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_GPONESR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONESR_INTACK 0x00001000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_GPONESR_INTOCC 0x00001000 -+/** LAN3E sleep request -+ The EGRESS FIFO of port LAN3 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN3ESR 0x00000800 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN3ESR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN3ESR_INTACK 0x00000800 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN3ESR_INTOCC 0x00000800 -+/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request. -+ This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN2ESR 0x00000400 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN2ESR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN2ESR_INTACK 0x00000400 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN2ESR_INTOCC 0x00000400 -+/** LAN1E sleep request -+ The EGRESS FIFO of port LAN1 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN1ESR 0x00000200 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN1ESR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN1ESR_INTACK 0x00000200 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN1ESR_INTOCC 0x00000200 -+/** LAN0E sleep request -+ The EGRESS FIFO of port LAN0 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN0ESR 0x00000100 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN0ESR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN0ESR_INTACK 0x00000100 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN0ESR_INTOCC 0x00000100 -+/** GPONI sleep request -+ The INGRESS FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONISR 0x00000010 -+/* Nothing -+#define SYS_GPE_IRNCSCR_GPONISR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONISR_INTACK 0x00000010 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_GPONISR_INTOCC 0x00000010 -+/** LAN3I sleep request -+ The INGRESS FIFO of port LAN3 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN3ISR 0x00000008 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN3ISR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN3ISR_INTACK 0x00000008 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN3ISR_INTOCC 0x00000008 -+/** LAN2I sleep request -+ The INGRESS FIFO of port LAN2 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN2ISR 0x00000004 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN2ISR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN2ISR_INTACK 0x00000004 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN2ISR_INTOCC 0x00000004 -+/** LAN1I sleep request -+ The INGRESS FIFO of port LAN1 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN1ISR 0x00000002 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN1ISR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN1ISR_INTACK 0x00000002 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN1ISR_INTOCC 0x00000002 -+/** LAN0I sleep request -+ The INGRESS FIFO of port LAN0 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN0ISR 0x00000001 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN0ISR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN0ISR_INTACK 0x00000001 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN0ISR_INTOCC 0x00000001 -+ -+/* Fields of "IRNCS Interrupt Control Register" */ -+/** FSQM wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_FSQMWR 0x80000000 -+/** GPONT wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_GPONTWR 0x20000000 -+/** GPONE wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_GPONEWR 0x10000000 -+/** LAN3E wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN3EWR 0x08000000 -+/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request. -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN2EWR 0x04000000 -+/** LAN1E wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN1EWR 0x02000000 -+/** LAN0E wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN0EWR 0x01000000 -+/** GPONI wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_GPONIWR 0x00100000 -+/** LAN3I wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN3IWR 0x00080000 -+/** LAN2I wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN2IWR 0x00040000 -+/** LAN1I wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN1IWR 0x00020000 -+/** LAN0I wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN0IWR 0x00010000 -+/** FSQM sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_FSQMSR 0x00008000 -+/** GPONT sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_GPONTSR 0x00002000 -+/** GPONE sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_GPONESR 0x00001000 -+/** LAN3E sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN3ESR 0x00000800 -+/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request. -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN2ESR 0x00000400 -+/** LAN1E sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN1ESR 0x00000200 -+/** LAN0E sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN0ESR 0x00000100 -+/** GPONI sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_GPONISR 0x00000010 -+/** LAN3I sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN3ISR 0x00000008 -+/** LAN2I sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN2ISR 0x00000004 -+/** LAN1I sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN1ISR 0x00000002 -+/** LAN0I sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN0ISR 0x00000001 -+ -+/* Fields of "IRNCS Interrupt Enable Register" */ -+/** FSQM wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_FSQMWR 0x80000000 -+/* Disable -+#define SYS_GPE_IRNCSEN_FSQMWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_FSQMWR_EN 0x80000000 -+/** GPONT wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_GPONTWR 0x20000000 -+/* Disable -+#define SYS_GPE_IRNCSEN_GPONTWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_GPONTWR_EN 0x20000000 -+/** GPONE wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_GPONEWR 0x10000000 -+/* Disable -+#define SYS_GPE_IRNCSEN_GPONEWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_GPONEWR_EN 0x10000000 -+/** LAN3E wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN3EWR 0x08000000 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN3EWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN3EWR_EN 0x08000000 -+/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request. -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN2EWR 0x04000000 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN2EWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN2EWR_EN 0x04000000 -+/** LAN1E wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN1EWR 0x02000000 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN1EWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN1EWR_EN 0x02000000 -+/** LAN0E wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN0EWR 0x01000000 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN0EWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN0EWR_EN 0x01000000 -+/** GPONI wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_GPONIWR 0x00100000 -+/* Disable -+#define SYS_GPE_IRNCSEN_GPONIWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_GPONIWR_EN 0x00100000 -+/** LAN3I wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN3IWR 0x00080000 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN3IWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN3IWR_EN 0x00080000 -+/** LAN2I wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN2IWR 0x00040000 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN2IWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN2IWR_EN 0x00040000 -+/** LAN1I wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN1IWR 0x00020000 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN1IWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN1IWR_EN 0x00020000 -+/** LAN0I wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN0IWR 0x00010000 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN0IWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN0IWR_EN 0x00010000 -+/** FSQM sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_FSQMSR 0x00008000 -+/* Disable -+#define SYS_GPE_IRNCSEN_FSQMSR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_FSQMSR_EN 0x00008000 -+/** GPONT sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_GPONTSR 0x00002000 -+/* Disable -+#define SYS_GPE_IRNCSEN_GPONTSR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_GPONTSR_EN 0x00002000 -+/** GPONE sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_GPONESR 0x00001000 -+/* Disable -+#define SYS_GPE_IRNCSEN_GPONESR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_GPONESR_EN 0x00001000 -+/** LAN3E sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN3ESR 0x00000800 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN3ESR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN3ESR_EN 0x00000800 -+/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request. -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN2ESR 0x00000400 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN2ESR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN2ESR_EN 0x00000400 -+/** LAN1E sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN1ESR 0x00000200 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN1ESR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN1ESR_EN 0x00000200 -+/** LAN0E sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN0ESR 0x00000100 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN0ESR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN0ESR_EN 0x00000100 -+/** GPONI sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_GPONISR 0x00000010 -+/* Disable -+#define SYS_GPE_IRNCSEN_GPONISR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_GPONISR_EN 0x00000010 -+/** LAN3I sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN3ISR 0x00000008 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN3ISR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN3ISR_EN 0x00000008 -+/** LAN2I sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN2ISR 0x00000004 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN2ISR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN2ISR_EN 0x00000004 -+/** LAN1I sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN1ISR 0x00000002 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN1ISR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN1ISR_EN 0x00000002 -+/** LAN0I sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN0ISR 0x00000001 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN0ISR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN0ISR_EN 0x00000001 -+ -+/*! @} */ /* SYS_GPE_REGISTER */ -+ -+#endif /* _sys_gpe_reg_h */ ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h -@@ -0,0 +1,58 @@ -+/* -+ * Lantiq FALCON specific CPU feature overrides -+ * -+ * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland -+ * -+ * This file was derived from: include/asm-mips/cpu-features.h -+ * Copyright (C) 2003, 2004 Ralf Baechle -+ * Copyright (C) 2004 Maciej W. Rozycki -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+#ifndef __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H -+#define __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H -+ -+#define cpu_has_tlb 1 -+#define cpu_has_4kex 1 -+#define cpu_has_3k_cache 0 -+#define cpu_has_4k_cache 1 -+#define cpu_has_tx39_cache 0 -+#define cpu_has_sb1_cache 0 -+#define cpu_has_fpu 0 -+#define cpu_has_32fpr 0 -+#define cpu_has_counter 1 -+#define cpu_has_watch 1 -+#define cpu_has_divec 1 -+ -+#define cpu_has_prefetch 1 -+#define cpu_has_ejtag 1 -+#define cpu_has_llsc 1 -+ -+#define cpu_has_mips16 1 -+#define cpu_has_mdmx 0 -+#define cpu_has_mips3d 0 -+#define cpu_has_smartmips 0 -+ -+#define cpu_has_mips32r1 1 -+#define cpu_has_mips32r2 1 -+#define cpu_has_mips64r1 0 -+#define cpu_has_mips64r2 0 -+ -+#define cpu_has_dsp 1 -+#define cpu_has_mipsmt 1 -+ -+#define cpu_has_vint 1 -+#define cpu_has_veic 1 -+ -+#define cpu_has_64bits 0 -+#define cpu_has_64bit_zero_reg 0 -+#define cpu_has_64bit_gp_regs 0 -+#define cpu_has_64bit_addresses 0 -+ -+#define cpu_dcache_line_size() 32 -+#define cpu_icache_line_size() 32 -+ -+#endif /* __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H */ ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/ebu_reg.h -@@ -0,0 +1,1520 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+ -+#ifndef _ebu_reg_h -+#define _ebu_reg_h -+ -+/** \addtogroup EBU_REGISTER -+ @{ -+*/ -+/* access macros */ -+#define ebu_r32(reg) reg_r32(&ebu->reg) -+#define ebu_w32(val, reg) reg_w32(val, &ebu->reg) -+#define ebu_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &ebu->reg) -+#define ebu_r32_table(reg, idx) reg_r32_table(ebu->reg, idx) -+#define ebu_w32_table(val, reg, idx) reg_w32_table(val, ebu->reg, idx) -+#define ebu_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, ebu->reg, idx) -+#define ebu_adr_table(reg, idx) adr_table(ebu->reg, idx) -+ -+ -+/** EBU register structure */ -+struct gpon_reg_ebu -+{ -+ /** Reserved */ -+ unsigned int res_0[2]; /* 0x00000000 */ -+ /** Module ID Register -+ Module type and version identifier */ -+ unsigned int modid; /* 0x00000008 */ -+ /** Module Control Register -+ This register contains general configuration information observed for all CS regions or dealing with EBU functionality that is not directly related to external memory access. */ -+ unsigned int modcon; /* 0x0000000C */ -+ /** Bus Read Configuration Register0 -+ Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */ -+ unsigned int busrcon0; /* 0x00000010 */ -+ /** Bus Read Parameters Register0 */ -+ unsigned int busrp0; /* 0x00000014 */ -+ /** Bus Write Configuration Register0 -+ Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */ -+ unsigned int buswcon0; /* 0x00000018 */ -+ /** Bus Write Parameters Register0 */ -+ unsigned int buswp0; /* 0x0000001C */ -+ /** Bus Read Configuration Register1 -+ Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */ -+ unsigned int busrcon1; /* 0x00000020 */ -+ /** Bus Read Parameters Register1 */ -+ unsigned int busrp1; /* 0x00000024 */ -+ /** Bus Write Configuration Register1 -+ Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */ -+ unsigned int buswcon1; /* 0x00000028 */ -+ /** Bus Write Parameters Register1 */ -+ unsigned int buswp1; /* 0x0000002C */ -+ /** Reserved */ -+ unsigned int res_1[8]; /* 0x00000030 */ -+ /** Bus Protocol Configuration Extension Register 0 */ -+ unsigned int busconext0; /* 0x00000050 */ -+ /** Bus Protocol Configuration Extension Register 1 */ -+ unsigned int busconext1; /* 0x00000054 */ -+ /** Reserved */ -+ unsigned int res_2[10]; /* 0x00000058 */ -+ /** Serial Flash Configuration Register -+ The content of this register configures the EBU's Serial Flash protocol engine. */ -+ unsigned int sfcon; /* 0x00000080 */ -+ /** Serial Flash Timing Register -+ This register defines the signal timing for the Serial Flash Access. See Section 3.18.3 on page 112 for details. */ -+ unsigned int sftime; /* 0x00000084 */ -+ /** Serial Flash Status Register -+ This register holds status information on the Serial Flash device(s) attached and the EBU's Serial Flash protocol engine. */ -+ unsigned int sfstat; /* 0x00000088 */ -+ /** Serial Flash Command Register -+ When writing to this register's opcode field, a command is started in the EBU's Serial Flash controller. */ -+ unsigned int sfcmd; /* 0x0000008C */ -+ /** Serial Flash Address Register -+ This register holds the address to be sent (if any) with accesses to/from a Serial Flash started by writing to EBU_SFCMD (Indirect Access Mode, see Section 3.18.2.4.1 on page 103). */ -+ unsigned int sfaddr; /* 0x00000090 */ -+ /** Serial Flash Data Register -+ This register holds the data being transferred (if any) with accesses to/from a Serial Flash started by writing to EBU_SFCMD (Indirect Access Mode, see Section 4.18.2.4.1 on page 116). */ -+ unsigned int sfdata; /* 0x00000094 */ -+ /** Serial Flash I/O Control Register -+ This register provides additional configuration for controlling the IO pads of the Serial Flash interface. */ -+ unsigned int sfio; /* 0x00000098 */ -+ /** Reserved */ -+ unsigned int res_3[25]; /* 0x0000009C */ -+}; -+ -+ -+/* Fields of "Module ID Register" */ -+/** Feature Select -+ This field indicates the types of external devices/protocols supported by the GPON version of the EBU. */ -+#define MODID_FSEL_MASK 0xE0000000 -+/** field offset */ -+#define MODID_FSEL_OFFSET 29 -+/** Support for SRAM, NAND/NOR/OneNand Flash and Cellular RAM is implemented. */ -+#define MODID_FSEL_SRAM_FLASH_CRAM 0x00000000 -+/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM and SDR SDRAM is implemented. */ -+#define MODID_FSEL_SRAM_FLASH_CRAM_SDR 0x20000000 -+/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM and SDR/DDR SDRAM is implemented. */ -+#define MODID_FSEL_SRAM_FLASH_CRAM_DDR 0x40000000 -+/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM, SDR/DDR SDRAM 0nd LPDDR-Flash is implemented. */ -+#define MODID_FSEL_SRAM_FLASH_CRAM_DDR_LPNVM 0x60000000 -+/** Serial Flash Support -+ Indicates whether or not the support of Serial Flash devices is available. */ -+#define MODID_SF 0x10000000 -+/* Not Available -+#define MODID_SF_NAV 0x00000000 */ -+/** Available */ -+#define MODID_SF_AV 0x10000000 -+/** AAD-mux Support -+ Indicates whether or not the GPON EBU supports AAD-mux protocol for Burst Flash and Cellular RAM. */ -+#define MODID_AAD 0x08000000 -+/* Not Available -+#define MODID_AAD_NAV 0x00000000 */ -+/** Available */ -+#define MODID_AAD_AV 0x08000000 -+/** Indicates whether or not the GPON EBU implements a DLL which is e.g. used for 50% duty cycle external clock generation. Note that a DLL is always implemented if DDR-SDRAM support is selected. */ -+#define MODID_DLL 0x04000000 -+/* Not Available -+#define MODID_DLL_NAV 0x00000000 */ -+/** Available */ -+#define MODID_DLL_AV 0x04000000 -+/** Pad Multiplexing Scheme */ -+#define MODID_PMS_MASK 0x03000000 -+/** field offset */ -+#define MODID_PMS_OFFSET 24 -+/** The EBU comprises of dedicated address pins A[EXTAW-1=:16]. */ -+#define MODID_PMS_PMS_CLASSIC 0x00000000 -+/** Revision -+ Revision Number */ -+#define MODID_REV_MASK 0x000F0000 -+/** field offset */ -+#define MODID_REV_OFFSET 16 -+/** Module ID -+ This field contains the EBU's unique peripheral ID. */ -+#define MODID_ID_MASK 0x0000FF00 -+/** field offset */ -+#define MODID_ID_OFFSET 8 -+/** Version -+ This field gives the EBU version number. */ -+#define MODID_VERSION_MASK 0x000000FF -+/** field offset */ -+#define MODID_VERSION_OFFSET 0 -+ -+/* Fields of "Module Control Register" */ -+/** Reserved */ -+#define MODCON_DLLUPDINT_MASK 0xC0000000 -+/** field offset */ -+#define MODCON_DLLUPDINT_OFFSET 30 -+/** Access Inhibit Acknowledge -+ After suspension of all accesses to the External Bus has been requested by setting bit acc_inh, acc_inh_ack acknowledges the request and inidcates that access suspension is now in effect. The bit is cleared when acc_inh gets deasserted. */ -+#define MODCON_AIA 0x02000000 -+/* no access restriction are active in the EBU subsystem -+#define MODCON_AIA_NO_INHIBIT 0x00000000 */ -+/** accesses are restricted to selected (configuration) system bus port(s) */ -+#define MODCON_AIA_INHIBIT 0x02000000 -+/** Access Inhibit request -+ Setting this bit will suspend all non-CPU system bus ports and the EBU itself from accessing the External Bus. This feature is usually used when the CPU needs to reconfigure protocol parameters in the EBU in order to avoid external accesses with invalid settings. The EBU acknowledges that the access suspension is in effect by asserting acc_inh_ack. */ -+#define MODCON_AI 0x01000000 -+/* no access restriction are active in the EBU subsystem -+#define MODCON_AI_NO_INHIBIT 0x00000000 */ -+/** accesses are restricted to selected (configuration) system bus port(s) */ -+#define MODCON_AI_INHIBIT 0x01000000 -+/** Lock Timeout */ -+#define MODCON_LTO_MASK 0x00FF0000 -+/** field offset */ -+#define MODCON_LTO_OFFSET 16 -+/** Reserved */ -+#define MODCON_DDREN 0x00008000 -+/** Pad Drive Control -+ Intended to be used to control the EBU pad''s drive strength. Refer to the GPON chip specification to see which drive strnegth options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */ -+#define MODCON_PEXT 0x00004000 -+/* Normal drive -+#define MODCON_PEXT_NORMAL 0x00000000 */ -+/** Strong drive */ -+#define MODCON_PEXT_STRONG 0x00004000 -+/** Pad Slew Falling Edge Control -+ Intended to be used to trim the External Bus pad's falling edge slew rate. Refer to the GPON chip specification to see which slew rate options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */ -+#define MODCON_SLF 0x00002000 -+/* Slow slew rate -+#define MODCON_SLF_SLOW 0x00000000 */ -+/** Fast slew rate */ -+#define MODCON_SLF_FAST 0x00002000 -+/** Pad Slew Rising Edge Control -+ Intended to be used to trim the External Bus pad's rising edge slew rate. Refer to the GPON chip specification to see which slew rate options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */ -+#define MODCON_SLR 0x00001000 -+/* Slow slew rate -+#define MODCON_SLR_SLOW 0x00000000 */ -+/** Fast slew rate */ -+#define MODCON_SLR_FAST 0x00001000 -+/** Write Buffering Mode -+ This bit controls when the EBU starts a new write burst transaction from the Memport interface. */ -+#define MODCON_WBM 0x00000040 -+/* The EBU starts a write transaction on the External Bus as early as possible, expecting that the n beats of the write burst will be transferred within n or n+1 clock cycles over the EBU's Memport interface. Use this mode if the EBU is clocked at the same or a slower frequency than the system bus interconnect. -+#define MODCON_WBM_START_WRITE_EARLY 0x00000000 */ -+/** The EBU start a write transaction only after all data of a write burst have been received over the EBU's Memport interface. Use this mode if the EBU is clocked at a higher frequency than the system bus interrconnect. */ -+#define MODCON_WBM_START_WRITE_LATE 0x00000040 -+/** Reserved */ -+#define MODCON_SDCLKEN 0x00000020 -+/** Standby Mode Enable -+ When set allows the EBU subsystem to enter standby mode in response to a rising edge on input signal standby_req_i. See Section 3.9.3 for details. */ -+#define MODCON_STBYEN 0x00000010 -+/* Disable -+#define MODCON_STBYEN_DIS 0x00000000 */ -+/** Enable */ -+#define MODCON_STBYEN_EN 0x00000010 -+/** Enable BFCLK1 -+ This field will enables or disables mirroring the clock that is output on BFCLKO_0 also on pad BFCLKO_1 to double the drive strength. See also Section 3.17.3) */ -+#define MODCON_BFCLK1EN 0x00000008 -+/* Disable -+#define MODCON_BFCLK1EN_DIS 0x00000000 */ -+/** Enable */ -+#define MODCON_BFCLK1EN_EN 0x00000008 -+/** Ready/Busy Status Edge -+ This is a read-only bit which shows a change of the logic level shown in the sts field since last read. It is reset by a read access. */ -+#define MODCON_STSEDGE 0x00000004 -+/** Ready/Busy Status -+ This is a read-only bit which reflects the current logic level present on the RDY/BSY or STS input pin which is (optionally) fed-in from a General Purpose I/O pad which is not part of the EBU via the EBU's input pin signal gpio_nand_rdy_ */ -+#define MODCON_STS 0x00000002 -+/** External Bus Arbitration Mode -+ This bit allows to disconnect the EBU from the External Bus. While EBU_MODCON.acc_inh_ack is 0, the value of arb_mode is forced to OWN_BUS. */ -+#define MODCON_AM 0x00000001 -+/* The EBU does not own the bus (multi-master) -+#define MODCON_AM_SHAREDBUS 0x00000000 */ -+/** The EBU owns the external bus. */ -+#define MODCON_AM_OWNBUS 0x00000001 -+ -+/* Fields of "Bus Read Configuration Register0" */ -+/** Device Type For Region -+ After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */ -+#define BUSRCON0_AGEN_MASK 0xF0000000 -+/** field offset */ -+#define BUSRCON0_AGEN_OFFSET 28 -+/** Muxed Asynchronous Type External Memory */ -+#define BUSRCON0_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000 -+/** Muxed Burst Type External Memory */ -+#define BUSRCON0_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000 -+/** NAND Flash (page optimised) */ -+#define BUSRCON0_AGEN_NAND_FLASH 0x20000000 -+/** Muxed Cellular RAM External Memory */ -+#define BUSRCON0_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000 -+/** Demuxed Asynchronous Type External Memory */ -+#define BUSRCON0_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000 -+/** Demuxed Burst Type External Memory */ -+#define BUSRCON0_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000 -+/** Demuxed Page Mode External Memory */ -+#define BUSRCON0_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000 -+/** Demuxed Cellular RAM External Memory */ -+#define BUSRCON0_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000 -+/** Serial Flash */ -+#define BUSRCON0_AGEN_SERIAL_FLASH 0xF0000000 -+/** Device Addressing Mode -+ t.b.d. */ -+#define BUSRCON0_PORTW_MASK 0x0C000000 -+/** field offset */ -+#define BUSRCON0_PORTW_OFFSET 26 -+/** 8-bit multiplexed */ -+#define BUSRCON0_PORTW_8_BIT_MUX 0x00000000 -+/** 16-bit multiplexed */ -+#define BUSRCON0_PORTW_16_BIT_MUX 0x04000000 -+/** Twin, 16-bit multiplexed */ -+#define BUSRCON0_PORTW_TWIN_16_BIT_MUX 0x08000000 -+/** 32-bit multiplexed */ -+#define BUSRCON0_PORTW_32_BIT_MUX 0x0C000000 -+/** External Wait Control -+ Function of the WAIT input. This is specific to the device type (i.e. the agen field). */ -+#define BUSRCON0_WAIT_MASK 0x03000000 -+/** field offset */ -+#define BUSRCON0_WAIT_OFFSET 24 -+/** WAIT is ignored (default after reset). */ -+#define BUSRCON0_WAIT_OFF 0x00000000 -+/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */ -+#define BUSRCON0_WAIT_EARLY_WAIT 0x01000000 -+/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */ -+#define BUSRCON0_WAIT_TWO_STAGE_SYNC 0x01000000 -+/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */ -+#define BUSRCON0_WAIT_WAIT_WITH_DATA 0x02000000 -+/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */ -+#define BUSRCON0_WAIT_SINGLE_STAGE_SYNC 0x02000000 -+/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */ -+#define BUSRCON0_WAIT_ABORT_AND_RETRY 0x03000000 -+/** Disable Burst Address Wrapping */ -+#define BUSRCON0_DBA 0x00800000 -+/** Reversed polarity at wait */ -+#define BUSRCON0_WAITINV 0x00400000 -+/* Low active. -+#define BUSRCON0_WAITINV_ACTLOW 0x00000000 */ -+/** High active */ -+#define BUSRCON0_WAITINV_ACTHI 0x00400000 -+/** Early ADV Enable for Synchronous Bursts */ -+#define BUSRCON0_EBSE 0x00200000 -+/* Low active. -+#define BUSRCON0_EBSE_DELAYED 0x00000000 */ -+/** High active */ -+#define BUSRCON0_EBSE_NOT_DELAYED 0x00200000 -+/** Early Control Signals for Synchronous Bursts */ -+#define BUSRCON0_ECSE 0x00100000 -+/* Low active. -+#define BUSRCON0_ECSE_DELAYED 0x00000000 */ -+/** High active */ -+#define BUSRCON0_ECSE_NOT_DELAYED 0x00100000 -+/** Synchronous Burst Buffer Mode Select */ -+#define BUSRCON0_FBBMSEL 0x00080000 -+/* FIXED_LENGTH -+#define BUSRCON0_FBBMSEL_FIXED_LENGTH 0x00000000 */ -+/** CONTINUOUS */ -+#define BUSRCON0_FBBMSEL_CONTINUOUS 0x00080000 -+/** Burst Length for Synchronous Burst */ -+#define BUSRCON0_FETBLEN_MASK 0x00070000 -+/** field offset */ -+#define BUSRCON0_FETBLEN_OFFSET 16 -+/** Up to 1 data cycle (default after reset). */ -+#define BUSRCON0_FETBLEN_SINGLE 0x00000000 -+/** Up to 2 data cycles. */ -+#define BUSRCON0_FETBLEN_BURST2 0x00010000 -+/** Up to 4 data cycles. */ -+#define BUSRCON0_FETBLEN_BURST4 0x00020000 -+/** Up to 8 data cycles. */ -+#define BUSRCON0_FETBLEN_BURST8 0x00030000 -+/** Up to 16 data cycles. */ -+#define BUSRCON0_FETBLEN_BURST16 0x00040000 -+/** Reserved -+ This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */ -+#define BUSRCON0_NANDAMAP_MASK 0x0000C000 -+/** field offset */ -+#define BUSRCON0_NANDAMAP_OFFSET 14 -+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ -+#define BUSRCON0_NANDAMAP_NAND_A17_16 0x00000000 -+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ -+#define BUSRCON0_NANDAMAP_NAND_WAIT_ADV 0x00004000 -+/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */ -+#define BUSRCON0_NANDAMAP_NAND_AD9_8 0x00008000 -+/** Reserved for future use. Do not use or unpredictable results may occur. */ -+#define BUSRCON0_NANDAMAP_NAND_RFU 0x0000C000 -+/** AAD-mux Protocol -+ If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */ -+#define BUSRCON0_AADMUX 0x00002000 -+/* Muxed device is write accessed in AD-mux mode. -+#define BUSRCON0_AADMUX_AD_MUX 0x00000000 */ -+/** Muxed device is write accessed in AAD-mux mode. */ -+#define BUSRCON0_AADMUX_AAD_MUX 0x00002000 -+/** Asynchronous Address Phase */ -+#define BUSRCON0_AAP 0x00001000 -+/* Clock is enabled at beginning of access. -+#define BUSRCON0_AAP_EARLY 0x00000000 */ -+/** Clock is enabled after address phase. */ -+#define BUSRCON0_AAP_LATE 0x00001000 -+/** Burst Flash Read Single Stage Synchronisation */ -+#define BUSRCON0_BFSSS 0x00000800 -+/* Two stages of synchronisation used. -+#define BUSRCON0_BFSSS_TWO_STAGE 0x00000000 */ -+/** Single stage of synchronisation used. */ -+#define BUSRCON0_BFSSS_SINGLE_STAGE 0x00000800 -+/** Burst Flash Clock Feedback Enable */ -+#define BUSRCON0_FDBKEN 0x00000400 -+/* Disable -+#define BUSRCON0_FDBKEN_DIS 0x00000000 */ -+/** Enable */ -+#define BUSRCON0_FDBKEN_EN 0x00000400 -+/** Auxiliary Chip Select Enable -+ Not supported in GPON-EBU, field must be set to 0. */ -+#define BUSRCON0_CSA 0x00000200 -+/* Disable -+#define BUSRCON0_CSA_DIS 0x00000000 */ -+/** Enable */ -+#define BUSRCON0_CSA_EN 0x00000200 -+/** Flash Non-Array Access Enable -+ Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */ -+#define BUSRCON0_NAA 0x00000100 -+/* Disable -+#define BUSRCON0_NAA_DIS 0x00000000 */ -+/** Enable */ -+#define BUSRCON0_NAA_EN 0x00000100 -+/** Module Enable */ -+#define BUSRCON0_ENABLE 0x00000001 -+/* Disable -+#define BUSRCON0_ENABLE_DIS 0x00000000 */ -+/** Enable */ -+#define BUSRCON0_ENABLE_EN 0x00000001 -+ -+/* Fields of "Bus Read Parameters Register0" */ -+/** Address Cycles -+ Number of cycles for address phase. */ -+#define BUSRP0_ADDRC_MASK 0xF0000000 -+/** field offset */ -+#define BUSRP0_ADDRC_OFFSET 28 -+/** Address Hold Cycles For Multiplexed Address -+ Number of address hold cycles during multiplexed accesses. */ -+#define BUSRP0_ADHOLC_MASK 0x0F000000 -+/** field offset */ -+#define BUSRP0_ADHOLC_OFFSET 24 -+/** Programmed Command Delay Cycles -+ Number of delay cycles during command delay phase. */ -+#define BUSRP0_CMDDELAY_MASK 0x00F00000 -+/** field offset */ -+#define BUSRP0_CMDDELAY_OFFSET 20 -+/** Extended Data */ -+#define BUSRP0_EXTDATA_MASK 0x000C0000 -+/** field offset */ -+#define BUSRP0_EXTDATA_OFFSET 18 -+/** External device outputs data every BFCLK cycle */ -+#define BUSRP0_EXTDATA_ONE 0x00000000 -+/** External device outputs data every 2nd BFCLK cycles */ -+#define BUSRP0_EXTDATA_TWO 0x00040000 -+/** External device outputs data every 4th BFCLK cycles */ -+#define BUSRP0_EXTDATA_FOUR 0x00080000 -+/** External device outputs data every 8th BFCLK cycles */ -+#define BUSRP0_EXTDATA_EIGHT 0x000C0000 -+/** Frequency of external clock at pin BFCLKO */ -+#define BUSRP0_EXTCLOCK_MASK 0x00030000 -+/** field offset */ -+#define BUSRP0_EXTCLOCK_OFFSET 16 -+/** Equal to ebu_clk frequency. */ -+#define BUSRP0_EXTCLOCK_ONE_TO_ONE 0x00000000 -+/** 1/2 of ebu_clk frequency. */ -+#define BUSRP0_EXTCLOCK_ONE_TO_TWO 0x00010000 -+/** 1/3 of ebu_clk frequency. */ -+#define BUSRP0_EXTCLOCK_ONE_TO_THREE 0x00020000 -+/** 1/4 of ebu_clk frequency (default after reset). */ -+#define BUSRP0_EXTCLOCK_ONE_TO_FOUR 0x00030000 -+/** Data Hold Cycles For read Accesses -+ Number of data hold cycles during read accesses. Applies to spinner support only where the address is guaranteed stable for datac clocks after RD high */ -+#define BUSRP0_DATAC_MASK 0x0000F000 -+/** field offset */ -+#define BUSRP0_DATAC_OFFSET 12 -+/** Programmed Wait States for read accesses -+ Number of programmed wait states for read accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */ -+#define BUSRP0_WAITRDC_MASK 0x00000F80 -+/** field offset */ -+#define BUSRP0_WAITRDC_OFFSET 7 -+/** Recovery Cycles After read Accesses, same CS -+ Number of idle cycles after read accesses when the next access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */ -+#define BUSRP0_RECOVC_MASK 0x00000070 -+/** field offset */ -+#define BUSRP0_RECOVC_OFFSET 4 -+/** Recovery Cycles After read Accesses, other CS -+ Number of idle cycles after read accesses when the next access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */ -+#define BUSRP0_DTACS_MASK 0x0000000F -+/** field offset */ -+#define BUSRP0_DTACS_OFFSET 0 -+ -+/* Fields of "Bus Write Configuration Register0" */ -+/** Device Type For Region -+ After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */ -+#define BUSWCON0_AGEN_MASK 0xF0000000 -+/** field offset */ -+#define BUSWCON0_AGEN_OFFSET 28 -+/** Muxed Asynchronous Type External Memory */ -+#define BUSWCON0_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000 -+/** Muxed Burst Type External Memory */ -+#define BUSWCON0_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000 -+/** NAND Flash (page optimised) */ -+#define BUSWCON0_AGEN_NAND_FLASH 0x20000000 -+/** Muxed Cellular RAM External Memory */ -+#define BUSWCON0_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000 -+/** Demuxed Asynchronous Type External Memory */ -+#define BUSWCON0_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000 -+/** Demuxed Burst Type External Memory */ -+#define BUSWCON0_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000 -+/** Demuxed Page Mode External Memory */ -+#define BUSWCON0_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000 -+/** Demuxed Cellular RAM External Memory */ -+#define BUSWCON0_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000 -+/** Serial Flash */ -+#define BUSWCON0_AGEN_SERIAL_FLASH 0xF0000000 -+/** Device Addressing Mode -+ t.b.d. */ -+#define BUSWCON0_PORTW_MASK 0x0C000000 -+/** field offset */ -+#define BUSWCON0_PORTW_OFFSET 26 -+/** External Wait Control -+ Function of the WAIT input. This is specific to the device type (i.e. the agen field). */ -+#define BUSWCON0_WAIT_MASK 0x03000000 -+/** field offset */ -+#define BUSWCON0_WAIT_OFFSET 24 -+/** WAIT is ignored (default after reset). */ -+#define BUSWCON0_WAIT_OFF 0x00000000 -+/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */ -+#define BUSWCON0_WAIT_EARLY_WAIT 0x01000000 -+/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */ -+#define BUSWCON0_WAIT_TWO_STAGE_SYNC 0x01000000 -+/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */ -+#define BUSWCON0_WAIT_WAIT_WITH_DATA 0x02000000 -+/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */ -+#define BUSWCON0_WAIT_SINGLE_STAGE_SYNC 0x02000000 -+/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */ -+#define BUSWCON0_WAIT_ABORT_AND_RETRY 0x03000000 -+/** Reserved */ -+#define BUSWCON0_LOCKCS 0x00800000 -+/** Reversed polarity at wait */ -+#define BUSWCON0_WAITINV 0x00400000 -+/* Low active. -+#define BUSWCON0_WAITINV_ACTLOW 0x00000000 */ -+/** High active */ -+#define BUSWCON0_WAITINV_ACTHI 0x00400000 -+/** Early ADV Enable for Synchronous Bursts */ -+#define BUSWCON0_EBSE 0x00200000 -+/* Low active. -+#define BUSWCON0_EBSE_DELAYED 0x00000000 */ -+/** High active */ -+#define BUSWCON0_EBSE_NOT_DELAYED 0x00200000 -+/** Early Control Signals for Synchronous Bursts */ -+#define BUSWCON0_ECSE 0x00100000 -+/* Low active. -+#define BUSWCON0_ECSE_DELAYED 0x00000000 */ -+/** High active */ -+#define BUSWCON0_ECSE_NOT_DELAYED 0x00100000 -+/** Synchronous Burst Buffer Mode Select */ -+#define BUSWCON0_FBBMSEL 0x00080000 -+/* FIXED_LENGTH -+#define BUSWCON0_FBBMSEL_FIXED_LENGTH 0x00000000 */ -+/** CONTINUOUS */ -+#define BUSWCON0_FBBMSEL_CONTINUOUS 0x00080000 -+/** Burst Length for Synchronous Burst */ -+#define BUSWCON0_FETBLEN_MASK 0x00070000 -+/** field offset */ -+#define BUSWCON0_FETBLEN_OFFSET 16 -+/** Up to 1 data cycle (default after reset). */ -+#define BUSWCON0_FETBLEN_SINGLE 0x00000000 -+/** Up to 2 data cycles. */ -+#define BUSWCON0_FETBLEN_BURST2 0x00010000 -+/** Up to 4 data cycles. */ -+#define BUSWCON0_FETBLEN_BURST4 0x00020000 -+/** Up to 8 data cycles. */ -+#define BUSWCON0_FETBLEN_BURST8 0x00030000 -+/** Up to 16 data cycles. */ -+#define BUSWCON0_FETBLEN_BURST16 0x00040000 -+/** Reserved -+ This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */ -+#define BUSWCON0_NANDAMAP_MASK 0x0000C000 -+/** field offset */ -+#define BUSWCON0_NANDAMAP_OFFSET 14 -+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ -+#define BUSWCON0_NANDAMAP_NAND_A17_16 0x00000000 -+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ -+#define BUSWCON0_NANDAMAP_NAND_WAIT_ADV 0x00004000 -+/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */ -+#define BUSWCON0_NANDAMAP_NAND_AD9_8 0x00008000 -+/** Reserved for future use. Do not use or unpredictable results may occur. */ -+#define BUSWCON0_NANDAMAP_NAND_RFU 0x0000C000 -+/** AAD-mux Protocol -+ If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */ -+#define BUSWCON0_AADMUX 0x00002000 -+/* Muxed device is write accessed in AD-mux mode. -+#define BUSWCON0_AADMUX_AD_MUX 0x00000000 */ -+/** Muxed device is write accessed in AAD-mux mode. */ -+#define BUSWCON0_AADMUX_AAD_MUX 0x00002000 -+/** Asynchronous Address Phase */ -+#define BUSWCON0_AAP 0x00001000 -+/* Clock is enabled at beginning of access. -+#define BUSWCON0_AAP_EARLY 0x00000000 */ -+/** Clock is enabled after address phase. */ -+#define BUSWCON0_AAP_LATE 0x00001000 -+/** Auxiliary Chip Select Enable -+ Not supported in GPON-EBU, field must be set to 0. */ -+#define BUSWCON0_CSA 0x00000200 -+/* Disable -+#define BUSWCON0_CSA_DIS 0x00000000 */ -+/** Enable */ -+#define BUSWCON0_CSA_EN 0x00000200 -+/** Flash Non-Array Access Enable -+ Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */ -+#define BUSWCON0_NAA 0x00000100 -+/* Disable -+#define BUSWCON0_NAA_DIS 0x00000000 */ -+/** Enable */ -+#define BUSWCON0_NAA_EN 0x00000100 -+/** Module Enable */ -+#define BUSWCON0_ENABLE 0x00000001 -+/* Disable -+#define BUSWCON0_ENABLE_DIS 0x00000000 */ -+/** Enable */ -+#define BUSWCON0_ENABLE_EN 0x00000001 -+ -+/* Fields of "Bus Write Parameters Register0" */ -+/** Address Cycles -+ Number of cycles for address phase. */ -+#define BUSWP0_ADDRC_MASK 0xF0000000 -+/** field offset */ -+#define BUSWP0_ADDRC_OFFSET 28 -+/** Address Hold Cycles For Multiplexed Address -+ Number of address hold cycles during multiplexed accesses. */ -+#define BUSWP0_ADHOLC_MASK 0x0F000000 -+/** field offset */ -+#define BUSWP0_ADHOLC_OFFSET 24 -+/** Programmed Command Delay Cycles -+ Number of delay cycles during command delay phase. */ -+#define BUSWP0_CMDDELAY_MASK 0x00F00000 -+/** field offset */ -+#define BUSWP0_CMDDELAY_OFFSET 20 -+/** Extended Data */ -+#define BUSWP0_EXTDATA_MASK 0x000C0000 -+/** field offset */ -+#define BUSWP0_EXTDATA_OFFSET 18 -+/** External device outputs data every BFCLK cycle */ -+#define BUSWP0_EXTDATA_ONE 0x00000000 -+/** External device outputs data every 2nd BFCLK cycles */ -+#define BUSWP0_EXTDATA_TWO 0x00040000 -+/** External device outputs data every 4th BFCLK cycles */ -+#define BUSWP0_EXTDATA_FOUR 0x00080000 -+/** External device outputs data every 8th BFCLK cycles */ -+#define BUSWP0_EXTDATA_EIGHT 0x000C0000 -+/** Frequency of external clock at pin BFCLKO */ -+#define BUSWP0_EXTCLOCK_MASK 0x00030000 -+/** field offset */ -+#define BUSWP0_EXTCLOCK_OFFSET 16 -+/** Equal to ebu_clk frequency. */ -+#define BUSWP0_EXTCLOCK_ONE_TO_ONE 0x00000000 -+/** 1/2 of ebu_clk frequency. */ -+#define BUSWP0_EXTCLOCK_ONE_TO_TWO 0x00010000 -+/** 1/3 of ebu_clk frequency. */ -+#define BUSWP0_EXTCLOCK_ONE_TO_THREE 0x00020000 -+/** 1/4 of ebu_clk frequency (default after reset). */ -+#define BUSWP0_EXTCLOCK_ONE_TO_FOUR 0x00030000 -+/** Data Hold Cycles For write Accesses -+ Number of data hold cycles during write accesses. */ -+#define BUSWP0_DATAC_MASK 0x0000F000 -+/** field offset */ -+#define BUSWP0_DATAC_OFFSET 12 -+/** Programmed Wait States For write Accesses -+ Number of programmed wait states for write accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */ -+#define BUSWP0_WAITWDC_MASK 0x00000F80 -+/** field offset */ -+#define BUSWP0_WAITWDC_OFFSET 7 -+/** Recovery Cycles After write Accesses, same CS -+ Number of idle cycles after write accesses when following access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */ -+#define BUSWP0_RECOVC_MASK 0x00000070 -+/** field offset */ -+#define BUSWP0_RECOVC_OFFSET 4 -+/** Recovery Cycles After write Accesses, other CS -+ Number of idle cycles after write accesses when the following access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */ -+#define BUSWP0_DTACS_MASK 0x0000000F -+/** field offset */ -+#define BUSWP0_DTACS_OFFSET 0 -+ -+/* Fields of "Bus Read Configuration Register1" */ -+/** Device Type For Region -+ After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */ -+#define BUSRCON1_AGEN_MASK 0xF0000000 -+/** field offset */ -+#define BUSRCON1_AGEN_OFFSET 28 -+/** Muxed Asynchronous Type External Memory */ -+#define BUSRCON1_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000 -+/** Muxed Burst Type External Memory */ -+#define BUSRCON1_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000 -+/** NAND Flash (page optimised) */ -+#define BUSRCON1_AGEN_NAND_FLASH 0x20000000 -+/** Muxed Cellular RAM External Memory */ -+#define BUSRCON1_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000 -+/** Demuxed Asynchronous Type External Memory */ -+#define BUSRCON1_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000 -+/** Demuxed Burst Type External Memory */ -+#define BUSRCON1_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000 -+/** Demuxed Page Mode External Memory */ -+#define BUSRCON1_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000 -+/** Demuxed Cellular RAM External Memory */ -+#define BUSRCON1_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000 -+/** Serial Flash */ -+#define BUSRCON1_AGEN_SERIAL_FLASH 0xF0000000 -+/** Device Addressing Mode -+ t.b.d. */ -+#define BUSRCON1_PORTW_MASK 0x0C000000 -+/** field offset */ -+#define BUSRCON1_PORTW_OFFSET 26 -+/** 8-bit multiplexed */ -+#define BUSRCON1_PORTW_8_BIT_MUX 0x00000000 -+/** 16-bit multiplexed */ -+#define BUSRCON1_PORTW_16_BIT_MUX 0x04000000 -+/** Twin, 16-bit multiplexed */ -+#define BUSRCON1_PORTW_TWIN_16_BIT_MUX 0x08000000 -+/** 32-bit multiplexed */ -+#define BUSRCON1_PORTW_32_BIT_MUX 0x0C000000 -+/** External Wait Control -+ Function of the WAIT input. This is specific to the device type (i.e. the agen field). */ -+#define BUSRCON1_WAIT_MASK 0x03000000 -+/** field offset */ -+#define BUSRCON1_WAIT_OFFSET 24 -+/** WAIT is ignored (default after reset). */ -+#define BUSRCON1_WAIT_OFF 0x00000000 -+/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */ -+#define BUSRCON1_WAIT_EARLY_WAIT 0x01000000 -+/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */ -+#define BUSRCON1_WAIT_TWO_STAGE_SYNC 0x01000000 -+/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */ -+#define BUSRCON1_WAIT_WAIT_WITH_DATA 0x02000000 -+/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */ -+#define BUSRCON1_WAIT_SINGLE_STAGE_SYNC 0x02000000 -+/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */ -+#define BUSRCON1_WAIT_ABORT_AND_RETRY 0x03000000 -+/** Disable Burst Address Wrapping */ -+#define BUSRCON1_DBA 0x00800000 -+/** Reversed polarity at wait */ -+#define BUSRCON1_WAITINV 0x00400000 -+/* Low active. -+#define BUSRCON1_WAITINV_ACTLOW 0x00000000 */ -+/** High active */ -+#define BUSRCON1_WAITINV_ACTHI 0x00400000 -+/** Early ADV Enable for Synchronous Bursts */ -+#define BUSRCON1_EBSE 0x00200000 -+/* Low active. -+#define BUSRCON1_EBSE_DELAYED 0x00000000 */ -+/** High active */ -+#define BUSRCON1_EBSE_NOT_DELAYED 0x00200000 -+/** Early Control Signals for Synchronous Bursts */ -+#define BUSRCON1_ECSE 0x00100000 -+/* Low active. -+#define BUSRCON1_ECSE_DELAYED 0x00000000 */ -+/** High active */ -+#define BUSRCON1_ECSE_NOT_DELAYED 0x00100000 -+/** Synchronous Burst Buffer Mode Select */ -+#define BUSRCON1_FBBMSEL 0x00080000 -+/* FIXED_LENGTH -+#define BUSRCON1_FBBMSEL_FIXED_LENGTH 0x00000000 */ -+/** CONTINUOUS */ -+#define BUSRCON1_FBBMSEL_CONTINUOUS 0x00080000 -+/** Burst Length for Synchronous Burst */ -+#define BUSRCON1_FETBLEN_MASK 0x00070000 -+/** field offset */ -+#define BUSRCON1_FETBLEN_OFFSET 16 -+/** Up to 1 data cycle (default after reset). */ -+#define BUSRCON1_FETBLEN_SINGLE 0x00000000 -+/** Up to 2 data cycles. */ -+#define BUSRCON1_FETBLEN_BURST2 0x00010000 -+/** Up to 4 data cycles. */ -+#define BUSRCON1_FETBLEN_BURST4 0x00020000 -+/** Up to 8 data cycles. */ -+#define BUSRCON1_FETBLEN_BURST8 0x00030000 -+/** Up to 16 data cycles. */ -+#define BUSRCON1_FETBLEN_BURST16 0x00040000 -+/** Reserved -+ This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */ -+#define BUSRCON1_NANDAMAP_MASK 0x0000C000 -+/** field offset */ -+#define BUSRCON1_NANDAMAP_OFFSET 14 -+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ -+#define BUSRCON1_NANDAMAP_NAND_A17_16 0x00000000 -+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ -+#define BUSRCON1_NANDAMAP_NAND_WAIT_ADV 0x00004000 -+/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */ -+#define BUSRCON1_NANDAMAP_NAND_AD9_8 0x00008000 -+/** Reserved for future use. Do not use or unpredictable results may occur. */ -+#define BUSRCON1_NANDAMAP_NAND_RFU 0x0000C000 -+/** AAD-mux Protocol -+ If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */ -+#define BUSRCON1_AADMUX 0x00002000 -+/* Muxed device is write accessed in AD-mux mode. -+#define BUSRCON1_AADMUX_AD_MUX 0x00000000 */ -+/** Muxed device is write accessed in AAD-mux mode. */ -+#define BUSRCON1_AADMUX_AAD_MUX 0x00002000 -+/** Asynchronous Address Phase */ -+#define BUSRCON1_AAP 0x00001000 -+/* Clock is enabled at beginning of access. -+#define BUSRCON1_AAP_EARLY 0x00000000 */ -+/** Clock is enabled after address phase. */ -+#define BUSRCON1_AAP_LATE 0x00001000 -+/** Burst Flash Read Single Stage Synchronisation */ -+#define BUSRCON1_BFSSS 0x00000800 -+/* Two stages of synchronisation used. -+#define BUSRCON1_BFSSS_TWO_STAGE 0x00000000 */ -+/** Single stage of synchronisation used. */ -+#define BUSRCON1_BFSSS_SINGLE_STAGE 0x00000800 -+/** Burst Flash Clock Feedback Enable */ -+#define BUSRCON1_FDBKEN 0x00000400 -+/* Disable -+#define BUSRCON1_FDBKEN_DIS 0x00000000 */ -+/** Enable */ -+#define BUSRCON1_FDBKEN_EN 0x00000400 -+/** Auxiliary Chip Select Enable -+ Not supported in GPON-EBU, field must be set to 0. */ -+#define BUSRCON1_CSA 0x00000200 -+/* Disable -+#define BUSRCON1_CSA_DIS 0x00000000 */ -+/** Enable */ -+#define BUSRCON1_CSA_EN 0x00000200 -+/** Flash Non-Array Access Enable -+ Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */ -+#define BUSRCON1_NAA 0x00000100 -+/* Disable -+#define BUSRCON1_NAA_DIS 0x00000000 */ -+/** Enable */ -+#define BUSRCON1_NAA_EN 0x00000100 -+/** Module Enable */ -+#define BUSRCON1_ENABLE 0x00000001 -+/* Disable -+#define BUSRCON1_ENABLE_DIS 0x00000000 */ -+/** Enable */ -+#define BUSRCON1_ENABLE_EN 0x00000001 -+ -+/* Fields of "Bus Read Parameters Register1" */ -+/** Address Cycles -+ Number of cycles for address phase. */ -+#define BUSRP1_ADDRC_MASK 0xF0000000 -+/** field offset */ -+#define BUSRP1_ADDRC_OFFSET 28 -+/** Address Hold Cycles For Multiplexed Address -+ Number of address hold cycles during multiplexed accesses. */ -+#define BUSRP1_ADHOLC_MASK 0x0F000000 -+/** field offset */ -+#define BUSRP1_ADHOLC_OFFSET 24 -+/** Programmed Command Delay Cycles -+ Number of delay cycles during command delay phase. */ -+#define BUSRP1_CMDDELAY_MASK 0x00F00000 -+/** field offset */ -+#define BUSRP1_CMDDELAY_OFFSET 20 -+/** Extended Data */ -+#define BUSRP1_EXTDATA_MASK 0x000C0000 -+/** field offset */ -+#define BUSRP1_EXTDATA_OFFSET 18 -+/** External device outputs data every BFCLK cycle */ -+#define BUSRP1_EXTDATA_ONE 0x00000000 -+/** External device outputs data every 2nd BFCLK cycles */ -+#define BUSRP1_EXTDATA_TWO 0x00040000 -+/** External device outputs data every 4th BFCLK cycles */ -+#define BUSRP1_EXTDATA_FOUR 0x00080000 -+/** External device outputs data every 8th BFCLK cycles */ -+#define BUSRP1_EXTDATA_EIGHT 0x000C0000 -+/** Frequency of external clock at pin BFCLKO */ -+#define BUSRP1_EXTCLOCK_MASK 0x00030000 -+/** field offset */ -+#define BUSRP1_EXTCLOCK_OFFSET 16 -+/** Equal to ebu_clk frequency. */ -+#define BUSRP1_EXTCLOCK_ONE_TO_ONE 0x00000000 -+/** 1/2 of ebu_clk frequency. */ -+#define BUSRP1_EXTCLOCK_ONE_TO_TWO 0x00010000 -+/** 1/3 of ebu_clk frequency. */ -+#define BUSRP1_EXTCLOCK_ONE_TO_THREE 0x00020000 -+/** 1/4 of ebu_clk frequency (default after reset). */ -+#define BUSRP1_EXTCLOCK_ONE_TO_FOUR 0x00030000 -+/** Data Hold Cycles For read Accesses -+ Number of data hold cycles during read accesses. Applies to spinner support only where the address is guaranteed stable for datac clocks after RD high */ -+#define BUSRP1_DATAC_MASK 0x0000F000 -+/** field offset */ -+#define BUSRP1_DATAC_OFFSET 12 -+/** Programmed Wait States for read accesses -+ Number of programmed wait states for read accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */ -+#define BUSRP1_WAITRDC_MASK 0x00000F80 -+/** field offset */ -+#define BUSRP1_WAITRDC_OFFSET 7 -+/** Recovery Cycles After read Accesses, same CS -+ Number of idle cycles after read accesses when the next access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */ -+#define BUSRP1_RECOVC_MASK 0x00000070 -+/** field offset */ -+#define BUSRP1_RECOVC_OFFSET 4 -+/** Recovery Cycles After read Accesses, other CS -+ Number of idle cycles after read accesses when the next access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */ -+#define BUSRP1_DTACS_MASK 0x0000000F -+/** field offset */ -+#define BUSRP1_DTACS_OFFSET 0 -+ -+/* Fields of "Bus Write Configuration Register1" */ -+/** Device Type For Region -+ After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */ -+#define BUSWCON1_AGEN_MASK 0xF0000000 -+/** field offset */ -+#define BUSWCON1_AGEN_OFFSET 28 -+/** Muxed Asynchronous Type External Memory */ -+#define BUSWCON1_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000 -+/** Muxed Burst Type External Memory */ -+#define BUSWCON1_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000 -+/** NAND Flash (page optimised) */ -+#define BUSWCON1_AGEN_NAND_FLASH 0x20000000 -+/** Muxed Cellular RAM External Memory */ -+#define BUSWCON1_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000 -+/** Demuxed Asynchronous Type External Memory */ -+#define BUSWCON1_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000 -+/** Demuxed Burst Type External Memory */ -+#define BUSWCON1_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000 -+/** Demuxed Page Mode External Memory */ -+#define BUSWCON1_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000 -+/** Demuxed Cellular RAM External Memory */ -+#define BUSWCON1_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000 -+/** Serial Flash */ -+#define BUSWCON1_AGEN_SERIAL_FLASH 0xF0000000 -+/** Device Addressing Mode -+ t.b.d. */ -+#define BUSWCON1_PORTW_MASK 0x0C000000 -+/** field offset */ -+#define BUSWCON1_PORTW_OFFSET 26 -+/** External Wait Control -+ Function of the WAIT input. This is specific to the device type (i.e. the agen field). */ -+#define BUSWCON1_WAIT_MASK 0x03000000 -+/** field offset */ -+#define BUSWCON1_WAIT_OFFSET 24 -+/** WAIT is ignored (default after reset). */ -+#define BUSWCON1_WAIT_OFF 0x00000000 -+/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */ -+#define BUSWCON1_WAIT_EARLY_WAIT 0x01000000 -+/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */ -+#define BUSWCON1_WAIT_TWO_STAGE_SYNC 0x01000000 -+/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */ -+#define BUSWCON1_WAIT_WAIT_WITH_DATA 0x02000000 -+/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */ -+#define BUSWCON1_WAIT_SINGLE_STAGE_SYNC 0x02000000 -+/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */ -+#define BUSWCON1_WAIT_ABORT_AND_RETRY 0x03000000 -+/** Reserved */ -+#define BUSWCON1_LOCKCS 0x00800000 -+/** Reversed polarity at wait */ -+#define BUSWCON1_WAITINV 0x00400000 -+/* Low active. -+#define BUSWCON1_WAITINV_ACTLOW 0x00000000 */ -+/** High active */ -+#define BUSWCON1_WAITINV_ACTHI 0x00400000 -+/** Early ADV Enable for Synchronous Bursts */ -+#define BUSWCON1_EBSE 0x00200000 -+/* Low active. -+#define BUSWCON1_EBSE_DELAYED 0x00000000 */ -+/** High active */ -+#define BUSWCON1_EBSE_NOT_DELAYED 0x00200000 -+/** Early Control Signals for Synchronous Bursts */ -+#define BUSWCON1_ECSE 0x00100000 -+/* Low active. -+#define BUSWCON1_ECSE_DELAYED 0x00000000 */ -+/** High active */ -+#define BUSWCON1_ECSE_NOT_DELAYED 0x00100000 -+/** Synchronous Burst Buffer Mode Select */ -+#define BUSWCON1_FBBMSEL 0x00080000 -+/* FIXED_LENGTH -+#define BUSWCON1_FBBMSEL_FIXED_LENGTH 0x00000000 */ -+/** CONTINUOUS */ -+#define BUSWCON1_FBBMSEL_CONTINUOUS 0x00080000 -+/** Burst Length for Synchronous Burst */ -+#define BUSWCON1_FETBLEN_MASK 0x00070000 -+/** field offset */ -+#define BUSWCON1_FETBLEN_OFFSET 16 -+/** Up to 1 data cycle (default after reset). */ -+#define BUSWCON1_FETBLEN_SINGLE 0x00000000 -+/** Up to 2 data cycles. */ -+#define BUSWCON1_FETBLEN_BURST2 0x00010000 -+/** Up to 4 data cycles. */ -+#define BUSWCON1_FETBLEN_BURST4 0x00020000 -+/** Up to 8 data cycles. */ -+#define BUSWCON1_FETBLEN_BURST8 0x00030000 -+/** Up to 16 data cycles. */ -+#define BUSWCON1_FETBLEN_BURST16 0x00040000 -+/** Reserved -+ This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */ -+#define BUSWCON1_NANDAMAP_MASK 0x0000C000 -+/** field offset */ -+#define BUSWCON1_NANDAMAP_OFFSET 14 -+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ -+#define BUSWCON1_NANDAMAP_NAND_A17_16 0x00000000 -+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ -+#define BUSWCON1_NANDAMAP_NAND_WAIT_ADV 0x00004000 -+/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */ -+#define BUSWCON1_NANDAMAP_NAND_AD9_8 0x00008000 -+/** Reserved for future use. Do not use or unpredictable results may occur. */ -+#define BUSWCON1_NANDAMAP_NAND_RFU 0x0000C000 -+/** AAD-mux Protocol -+ If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */ -+#define BUSWCON1_AADMUX 0x00002000 -+/* Muxed device is write accessed in AD-mux mode. -+#define BUSWCON1_AADMUX_AD_MUX 0x00000000 */ -+/** Muxed device is write accessed in AAD-mux mode. */ -+#define BUSWCON1_AADMUX_AAD_MUX 0x00002000 -+/** Asynchronous Address Phase */ -+#define BUSWCON1_AAP 0x00001000 -+/* Clock is enabled at beginning of access. -+#define BUSWCON1_AAP_EARLY 0x00000000 */ -+/** Clock is enabled after address phase. */ -+#define BUSWCON1_AAP_LATE 0x00001000 -+/** Auxiliary Chip Select Enable -+ Not supported in GPON-EBU, field must be set to 0. */ -+#define BUSWCON1_CSA 0x00000200 -+/* Disable -+#define BUSWCON1_CSA_DIS 0x00000000 */ -+/** Enable */ -+#define BUSWCON1_CSA_EN 0x00000200 -+/** Flash Non-Array Access Enable -+ Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */ -+#define BUSWCON1_NAA 0x00000100 -+/* Disable -+#define BUSWCON1_NAA_DIS 0x00000000 */ -+/** Enable */ -+#define BUSWCON1_NAA_EN 0x00000100 -+/** Module Enable */ -+#define BUSWCON1_ENABLE 0x00000001 -+/* Disable -+#define BUSWCON1_ENABLE_DIS 0x00000000 */ -+/** Enable */ -+#define BUSWCON1_ENABLE_EN 0x00000001 -+ -+/* Fields of "Bus Write Parameters Register1" */ -+/** Address Cycles -+ Number of cycles for address phase. */ -+#define BUSWP1_ADDRC_MASK 0xF0000000 -+/** field offset */ -+#define BUSWP1_ADDRC_OFFSET 28 -+/** Address Hold Cycles For Multiplexed Address -+ Number of address hold cycles during multiplexed accesses. */ -+#define BUSWP1_ADHOLC_MASK 0x0F000000 -+/** field offset */ -+#define BUSWP1_ADHOLC_OFFSET 24 -+/** Programmed Command Delay Cycles -+ Number of delay cycles during command delay phase. */ -+#define BUSWP1_CMDDELAY_MASK 0x00F00000 -+/** field offset */ -+#define BUSWP1_CMDDELAY_OFFSET 20 -+/** Extended Data */ -+#define BUSWP1_EXTDATA_MASK 0x000C0000 -+/** field offset */ -+#define BUSWP1_EXTDATA_OFFSET 18 -+/** External device outputs data every BFCLK cycle */ -+#define BUSWP1_EXTDATA_ONE 0x00000000 -+/** External device outputs data every 2nd BFCLK cycles */ -+#define BUSWP1_EXTDATA_TWO 0x00040000 -+/** External device outputs data every 4th BFCLK cycles */ -+#define BUSWP1_EXTDATA_FOUR 0x00080000 -+/** External device outputs data every 8th BFCLK cycles */ -+#define BUSWP1_EXTDATA_EIGHT 0x000C0000 -+/** Frequency of external clock at pin BFCLKO */ -+#define BUSWP1_EXTCLOCK_MASK 0x00030000 -+/** field offset */ -+#define BUSWP1_EXTCLOCK_OFFSET 16 -+/** Equal to ebu_clk frequency. */ -+#define BUSWP1_EXTCLOCK_ONE_TO_ONE 0x00000000 -+/** 1/2 of ebu_clk frequency. */ -+#define BUSWP1_EXTCLOCK_ONE_TO_TWO 0x00010000 -+/** 1/3 of ebu_clk frequency. */ -+#define BUSWP1_EXTCLOCK_ONE_TO_THREE 0x00020000 -+/** 1/4 of ebu_clk frequency (default after reset). */ -+#define BUSWP1_EXTCLOCK_ONE_TO_FOUR 0x00030000 -+/** Data Hold Cycles For write Accesses -+ Number of data hold cycles during write accesses. */ -+#define BUSWP1_DATAC_MASK 0x0000F000 -+/** field offset */ -+#define BUSWP1_DATAC_OFFSET 12 -+/** Programmed Wait States For write Accesses -+ Number of programmed wait states for write accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */ -+#define BUSWP1_WAITWDC_MASK 0x00000F80 -+/** field offset */ -+#define BUSWP1_WAITWDC_OFFSET 7 -+/** Recovery Cycles After write Accesses, same CS -+ Number of idle cycles after write accesses when following access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */ -+#define BUSWP1_RECOVC_MASK 0x00000070 -+/** field offset */ -+#define BUSWP1_RECOVC_OFFSET 4 -+/** Recovery Cycles After write Accesses, other CS -+ Number of idle cycles after write accesses when the following access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */ -+#define BUSWP1_DTACS_MASK 0x0000000F -+/** field offset */ -+#define BUSWP1_DTACS_OFFSET 0 -+ -+/* Fields of "Bus Protocol Configuration Extension Register 0" */ -+/** Byte Control Mapping -+ Remapping of byte enable signals on address lines is not supported in the GPON-EBU. */ -+#define BUSCONEXT0_BCMAP_MASK 0x00030000 -+/** field offset */ -+#define BUSCONEXT0_BCMAP_OFFSET 16 -+/** No mirroring of byte enables. */ -+#define BUSCONEXT0_BCMAP_NOBCMAP 0x00000000 -+/** Asynchronous Early Write -+ This bit is obsolete and must be set to 0 or unpredictable results may result. */ -+#define BUSCONEXT0_AEW 0x00008000 -+/** AAD-mux Consecutive Address Cycles -+ This bit selects whether ADV gets deasserted between the high and the low address phase of a synchronous AAD-mux access or the two address cycles are consecutive. See Figure 32 for a waveform example that results when acac is set. acac only takes effect if the CS region is configured for synchronous AADmux access (agen = 1 or 3, aadmux = 1) and is ignored otherwise. */ -+#define BUSCONEXT0_ACAC 0x00004000 -+/* ADV is deasserted between high and low address phase. -+#define BUSCONEXT0_ACAC_SEPERATED 0x00000000 */ -+/** ADV is not deasserted between high and low address phase. */ -+#define BUSCONEXT0_ACAC_CONSECUTIVE 0x00004000 -+/** AAD-mux Write Address-to-Address Delay -+ Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when writing to the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSWCON, fields agen and aadmux. */ -+#define BUSCONEXT0_WAAC_MASK 0x00003800 -+/** field offset */ -+#define BUSCONEXT0_WAAC_OFFSET 11 -+/** AAD-mux Read Address-to-Address Delay -+ Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when reading from the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSRCON, fields agen and aadmux. */ -+#define BUSCONEXT0_RAAC_MASK 0x00000700 -+/** field offset */ -+#define BUSCONEXT0_RAAC_OFFSET 8 -+/** AAD-mux Paging Enable for CS0 -+ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field selects whether or not to use paging. If paging is enabled, the EBU skips the high address cycle in case the upper address that would be sent are the same as in the most recent access to the device.configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */ -+#define BUSCONEXT0_PAGE_EN 0x00000080 -+/* Disable -+#define BUSCONEXT0_PAGE_EN_DIS 0x00000000 */ -+/** Enable */ -+#define BUSCONEXT0_PAGE_EN_EN 0x00000080 -+/** AAD-mux Address Extension Bit Generation Mode -+ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */ -+#define BUSCONEXT0_AEBM_MASK 0x00000070 -+/** field offset */ -+#define BUSCONEXT0_AEBM_OFFSET 4 -+/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 0 */ -+#define BUSCONEXT0_AEBM_AMAP_CRE_RFU0 0x00000000 -+/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 1 */ -+#define BUSCONEXT0_AEBM_AMAP_CRE_RFU1 0x00000010 -+/** A[15] in the high address cycle is set to AMemport[amsb+18], A[14] is set to AMemport[amsb+17] */ -+#define BUSCONEXT0_AEBM_AMAP_CRE_AND_RFU 0x00000020 -+/** Do not use */ -+#define BUSCONEXT0_AEBM_reserved 0x00000030 -+/** A[15:14] in the high address cycle is set to 00B. */ -+#define BUSCONEXT0_AEBM_DIRECT_00 0x00000040 -+/** A[15:14] in the high address cycle is set to 01B */ -+#define BUSCONEXT0_AEBM_DIRECT_01 0x00000050 -+/** A[15:14] in the high address cycle is set to 10B */ -+#define BUSCONEXT0_AEBM_DIRECT_10 0x00000060 -+/** A[15:14] in the high address cycle is set to 11B. */ -+#define BUSCONEXT0_AEBM_DIRECT_11 0x00000070 -+/** Most Significant Address Bit of External Device -+ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then for amsb < 14 the EBU always sets A[13:amsb] = 0 in the high address cycle of an access. The value of A[15:14] is defined in field aebm. A value of amsb > 13 therefore has no effect. It is recommended to set amsb that it matches the addressable range of the external device according to the following formula: amsb = n - 16 for a device with 2n addressable words. */ -+#define BUSCONEXT0_AMSB_MASK 0x0000000F -+/** field offset */ -+#define BUSCONEXT0_AMSB_OFFSET 0 -+ -+/* Fields of "Bus Protocol Configuration Extension Register 1" */ -+/** Byte Control Mapping -+ Remapping of byte enable signals on address lines is not supported in the GPON-EBU. */ -+#define BUSCONEXT1_BCMAP_MASK 0x00030000 -+/** field offset */ -+#define BUSCONEXT1_BCMAP_OFFSET 16 -+/** No mirroring of byte enables. */ -+#define BUSCONEXT1_BCMAP_NOBCMAP 0x00000000 -+/** Asynchronous Early Write -+ This bit is obsolete and must be set to 0 or unpredictable results may result. */ -+#define BUSCONEXT1_AEW 0x00008000 -+/** AAD-mux Consecutive Address Cycles -+ This bit selects whether ADV gets deasserted between the high and the low address phase of a synchronous AAD-mux access or the two address cycles are consecutive. See Figure 32 for a waveform example that results when acac is set. acac only takes effect if the CS region is configured for synchronous AADmux access (agen = 1 or 3, aadmux = 1) and is ignored otherwise. */ -+#define BUSCONEXT1_ACAC 0x00004000 -+/* ADV is deasserted between high and low address phase. -+#define BUSCONEXT1_ACAC_SEPERATED 0x00000000 */ -+/** ADV is not deasserted between high and low address phase. */ -+#define BUSCONEXT1_ACAC_CONSECUTIVE 0x00004000 -+/** AAD-mux Write Address-to-Address Delay -+ Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when writing to the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSWCON, fields agen and aadmux. */ -+#define BUSCONEXT1_WAAC_MASK 0x00003800 -+/** field offset */ -+#define BUSCONEXT1_WAAC_OFFSET 11 -+/** AAD-mux Read Address-to-Address Delay -+ Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when reading from the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSRCON, fields agen and aadmux. */ -+#define BUSCONEXT1_RAAC_MASK 0x00000700 -+/** field offset */ -+#define BUSCONEXT1_RAAC_OFFSET 8 -+/** AAD-mux Paging Enable for CS0 -+ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field selects whether or not to use paging. If paging is enabled, the EBU skips the high address cycle in case the upper address that would be sent are the same as in the most recent access to the device.configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */ -+#define BUSCONEXT1_PAGE_EN 0x00000080 -+/* Disable -+#define BUSCONEXT1_PAGE_EN_DIS 0x00000000 */ -+/** Enable */ -+#define BUSCONEXT1_PAGE_EN_EN 0x00000080 -+/** AAD-mux Address Extension Bit Generation Mode -+ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */ -+#define BUSCONEXT1_AEBM_MASK 0x00000070 -+/** field offset */ -+#define BUSCONEXT1_AEBM_OFFSET 4 -+/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 0 */ -+#define BUSCONEXT1_AEBM_AMAP_CRE_RFU0 0x00000000 -+/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 1 */ -+#define BUSCONEXT1_AEBM_AMAP_CRE_RFU1 0x00000010 -+/** A[15] in the high address cycle is set to AMemport[amsb+18], A[14] is set to AMemport[amsb+17] */ -+#define BUSCONEXT1_AEBM_AMAP_CRE_AND_RFU 0x00000020 -+/** Do not use */ -+#define BUSCONEXT1_AEBM_reserved 0x00000030 -+/** A[15:14] in the high address cycle is set to 00B. */ -+#define BUSCONEXT1_AEBM_DIRECT_00 0x00000040 -+/** A[15:14] in the high address cycle is set to 01B */ -+#define BUSCONEXT1_AEBM_DIRECT_01 0x00000050 -+/** A[15:14] in the high address cycle is set to 10B */ -+#define BUSCONEXT1_AEBM_DIRECT_10 0x00000060 -+/** A[15:14] in the high address cycle is set to 11B. */ -+#define BUSCONEXT1_AEBM_DIRECT_11 0x00000070 -+/** Most Significant Address Bit of External Device -+ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then for amsb < 14 the EBU always sets A[13:amsb] = 0 in the high address cycle of an access. The value of A[15:14] is defined in field aebm. A value of amsb > 13 therefore has no effect. It is recommended to set amsb that it matches the addressable range of the external device according to the following formula: amsb = n - 16 for a device with 2n addressable words. */ -+#define BUSCONEXT1_AMSB_MASK 0x0000000F -+/** field offset */ -+#define BUSCONEXT1_AMSB_OFFSET 0 -+ -+/* Fields of "Serial Flash Configuration Register" */ -+/** Direct Access Device Port Width -+ DA_PORTW Defines the number of signal lines to be used with direct read access from a Serial Flash as defined for the command with opcode rd_opc. Depending on thedevice type and/or command, the number of used signal lines might differbetween command, address, and data phase of the transaction. */ -+#define SFCON_DA_PORTW_MASK 0xE0000000 -+/** field offset */ -+#define SFCON_DA_PORTW_OFFSET 29 -+/** One signal line used in all phases of the transaction. */ -+#define SFCON_DA_PORTW_WIDTH_1_1_1 0x00000000 -+/** One signal line used in the COMMAND and ADDRESS phase of the transaction and two signal lines used in the DATA phase. */ -+#define SFCON_DA_PORTW_WIDTH_1_1_2 0x20000000 -+/** One signal used in the COMMAND phase of the transaction and two signal lines used in the ADDRESS/DUMMY phase and the DATA phase. */ -+#define SFCON_DA_PORTW_WIDTH_1_2_2 0x40000000 -+/** Two signal lines used in all phases of the transaction. */ -+#define SFCON_DA_PORTW_WIDTH_2_2_2 0x60000000 -+/** One signal line used in the COMMAND and ADDRESS phase of the transaction and four signal lines used in the DATA phase. */ -+#define SFCON_DA_PORTW_WIDTH_1_1_4 0x80000000 -+/** One signal used in the COMMAND phase of the transaction and four signal lines used in the ADDRESS/DUMMY phase and the DATA phase. */ -+#define SFCON_DA_PORTW_WIDTH_1_4_4 0xA0000000 -+/** Four signal lines used in all phases of the transaction. */ -+#define SFCON_DA_PORTW_WIDTH_4_4_4 0xC0000000 -+/** for future use. */ -+#define SFCON_DA_PORTW_WIDTH_reserved 0xE0000000 -+/** Read Abort Enable -+ If set, a read access from the external device can be aborted via signal sf_rd_abort_i. See Section 3.18.2.9 for details. */ -+#define SFCON_RD_ABORT_EN 0x10000000 -+/** Device Size -+ Defines the number of significant address bits for the Serial Flash device(s). All address bits above the MSB are forced to 0. The configuration in this field also defines for the address auto-increment feature when to wrap around from the upper most address to 0. */ -+#define SFCON_DEV_SIZE_MASK 0x0F000000 -+/** field offset */ -+#define SFCON_DEV_SIZE_OFFSET 24 -+/** 16 MBit device */ -+#define SFCON_DEV_SIZE_A20_0 0x00000000 -+/** 32 MBit device */ -+#define SFCON_DEV_SIZE_A21_0 0x01000000 -+/** 64 MBit device */ -+#define SFCON_DEV_SIZE_A22_0 0x02000000 -+/** 128 MBit device */ -+#define SFCON_DEV_SIZE_A23_0 0x03000000 -+/** 256 MBit device */ -+#define SFCON_DEV_SIZE_A24_0 0x04000000 -+/** 512 MBit device */ -+#define SFCON_DEV_SIZE_A25_0 0x05000000 -+/** 1 GBit device */ -+#define SFCON_DEV_SIZE_A26_0 0x06000000 -+/** 2 GBit device */ -+#define SFCON_DEV_SIZE_A27_0 0x07000000 -+/** 4 GBit device */ -+#define SFCON_DEV_SIZE_A28_0 0x08000000 -+/** 8 GBit device */ -+#define SFCON_DEV_SIZE_A29_0 0x09000000 -+/** 16 GBit device */ -+#define SFCON_DEV_SIZE_A30_0 0x0A000000 -+/** 32 GBit device */ -+#define SFCON_DEV_SIZE_A31_0 0x0B000000 -+/** Device Page Size -+ Defines the page size employed by all connected Serial Flash devices. The device page size is used to determine the address wrap-around for the write address auto-increment feature. */ -+#define SFCON_DPS_MASK 0x00C00000 -+/** field offset */ -+#define SFCON_DPS_OFFSET 22 -+/** Device page size is 256 Bytes */ -+#define SFCON_DPS_DPS_256 0x00000000 -+/** Device page size is 512 Bytes */ -+#define SFCON_DPS_DPS_512 0x00400000 -+/** Page Buffer Size -+ Defines the size of the EBU's page buffer used in Buffered Access. Page buffer size configured here must be less than or equal to the maximum page buffer size which is a built option of the EBU (256 Bytes for GPON). */ -+#define SFCON_PB_SIZE_MASK 0x00300000 -+/** field offset */ -+#define SFCON_PB_SIZE_OFFSET 20 -+/** No read buffer is available/used. */ -+#define SFCON_PB_SIZE_NONE 0x00000000 -+/** 128 Bytes */ -+#define SFCON_PB_SIZE_SIZE_128 0x00100000 -+/** 256 Bytes */ -+#define SFCON_PB_SIZE_SIZE_256 0x00200000 -+/** Bidirectional Data Bus -+ Defines whether the Serial Flash uses a unidirectional or a bidirectional data bus. */ -+#define SFCON_BIDIR 0x00080000 -+/* The Serial Flash interface uses a pair of two unidirectional busses (one for write, one for read) -+#define SFCON_BIDIR_UNIDIRECTIONAL 0x00000000 */ -+/** The Serial Flash interface uses a bidirectional data bus. */ -+#define SFCON_BIDIR_BIDIRECTIONAL 0x00080000 -+/** No Busy Error termination -+ By default, the EBU error-terminates all direct access to a Serial Flash while EBU_SFSTAT.busy is set. By setting NO_BUSY_ERR, the EBU can be configured to permit direct accesses to proceed to the Serial Flash, e.g. for devices that support a read-while-write functionality. */ -+#define SFCON_NO_BUSY_ERR 0x00040000 -+/** End-of-Busy Detection Mode -+ Defines how the EBU detects the end of a busy phase in the Serial Flash device. The current version of the EBU requires the software to explicitly poll the device's status register and then inform the EBU on the end of the busy status by clearing the corresponding bit in register EBU_SF_STAT. */ -+#define SFCON_EOBDM_MASK 0x00030000 -+/** field offset */ -+#define SFCON_EOBDM_OFFSET 16 -+/** No read buffer is available/used. */ -+#define SFCON_EOBDM_SOFTWARE 0x00000000 -+/** Poll device status register (not supported yet) */ -+#define SFCON_EOBDM_POLL_SR 0x00010000 -+/** Poll devices busy/ready pin fed into EBU via WAIT pin (not supported yet). */ -+#define SFCON_EOBDM_POLL_RDY 0x00020000 -+/** Same as POLL_RDY, but CS must be asserted to have the device output its busy/ready status (not supported yet). */ -+#define SFCON_EOBDM_POLL_RDY_WITH_CS 0x00030000 -+/** Direct Access Keep Chip Select -+ Defines whether the Serial Flash remains selected after a direct access transaction has been finished. */ -+#define SFCON_DA_KEEP_CS 0x00008000 -+/* After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address. -+#define SFCON_DA_KEEP_CS_DESELECT 0x00000000 */ -+/** Chip Select of device is kept active after direct read access so that device is ready for follow-up read of next sequential byte without the need to send command and address. If the next command is to another Chip Select, is a different command or accesses a different address, the EBU first deactivates the kept Chip Select before it starts the new transaction with sending the command opcode and address. */ -+#define SFCON_DA_KEEP_CS_KEEP_SELECTED 0x00008000 -+/** Early Read Abort Enable -+ When aborting a Serial Flash Read is enabled in bit EBU_SFCON.rd_abort_en, bit early_abort selects at what point in the protocol an external access might be aborted. Datasheets of many Serial Flash devices are not explicit on what happens (and whether it is allowed) when a read access is cut-short by deselecting the device during the CMD, ADDR or DUMMY phase of the protocol. */ -+#define SFCON_EARLY_ABORT 0x00004000 -+/* DISABLE Early abortion is disabled (default after reset). Once the EBU has started the access on the External Bus (first bit time slot), the EBU continues the external transfer until the first data byte has been received. After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address. -+#define SFCON_EARLY_ABORT_DISABLE 0x00000000 */ -+/** Early abortion is not yet supported in the current version of the EBU. Do not use. The feature is a late improvement to the EBU and could not be verified completely before the final release. After proven to work, it should be made officially available to reduce access latency after aborted Serial Flash reads. Setting early_abort to ENABLE alters the read abort handling in the following way: Once the EBU has started the access on the External Bus, the transfer is cut-short after transferring the CMD byte, the three address bytes, any DUMMY bits or at the end of the next data byte - whatever comes first. */ -+#define SFCON_EARLY_ABORT_ENABLE 0x00004000 -+/** Direct Access Address Length -+ Defines the number of address bytes to be sent (MSB first) to the device with a direct read access transaction. Other values than listed below are not supported and have unpredictable results. */ -+#define SFCON_DA_ALEN_MASK 0x00003000 -+/** field offset */ -+#define SFCON_DA_ALEN_OFFSET 12 -+/** 3 address bytes (bits 23:0 of the internal address) */ -+#define SFCON_DA_ALEN_THREE 0x00000000 -+/** Read Access Dummy Bytes -+ This field defines the number of dummy bytes to send between the last address byte before the EBU starts capturing read data from the bus for a direct read access. The number of dummy bytes depends on the data access command being used (see field), the clock frequency and the type of device being used. */ -+#define SFCON_RD_DUMLEN_MASK 0x00000F00 -+/** field offset */ -+#define SFCON_RD_DUMLEN_OFFSET 8 -+/** Direct Read Access Command Opcode -+ This byte defines the command opcode to send when performing a data read from the Serial Flash in Direct Access Mode. Any value can be set (the EBU does not interpret the value, but directly uses the contents of this register field in the command phase of the transaction). Common opcodes to be used and understood by most devices are READ (03H) and FAST_READ (0BH), but some devices might provide additional opcodes, e.g. to support higher clock frequencies requiring additional dummy bytes or to define a wider interface bus. */ -+#define SFCON_RD_OPC_MASK 0x000000FF -+/** field offset */ -+#define SFCON_RD_OPC_OFFSET 0 -+/** READ */ -+#define SFCON_RD_OPC_READ 0x00000003 -+/** FAST_READ */ -+#define SFCON_RD_OPC_FAST_READ 0x0000000B -+ -+/* Fields of "Serial Flash Timing Register" */ -+/** CS Idle time -+ This field defines the minimum time the device's Chip Select has to be deasserted in between accesses. Most devices require a minimum deselect time between 50 and 100 ns. See Table 43 for the encoding used in this field. */ -+#define SFTIME_CS_IDLE_MASK 0xF0000000 -+/** field offset */ -+#define SFTIME_CS_IDLE_OFFSET 28 -+/** 1 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_0 0x00000000 -+/** 2 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_1 0x10000000 -+/** 3 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_2 0x20000000 -+/** 4 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_3 0x30000000 -+/** 6 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_4 0x40000000 -+/** 8 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_5 0x50000000 -+/** 10 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_6 0x60000000 -+/** 12 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_7 0x70000000 -+/** 14 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_8 0x80000000 -+/** 16 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_9 0x90000000 -+/** 20 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_10 0xA0000000 -+/** 24 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_11 0xB0000000 -+/** 32 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_12 0xC0000000 -+/** 40 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_13 0xD0000000 -+/** 48 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_14 0xE0000000 -+/** 64 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_15 0xF0000000 -+/** CS Hold time -+ This field defines (in multiples of the EBU internal clock's period) the minimum time the device's Chip Select must remain asserted after transfer of the last bit of a write transaction. This CS hold time does not apply to read accesses */ -+#define SFTIME_CS_HOLD_MASK 0x0C000000 -+/** field offset */ -+#define SFTIME_CS_HOLD_OFFSET 26 -+/** CS Setup time -+ This field defines (in multiples of the EBU internal clock's period) when to assert the device's Chip Select before the first SCK clock period for transferring the command is started on the External Bus */ -+#define SFTIME_CS_SETUP_MASK 0x03000000 -+/** field offset */ -+#define SFTIME_CS_SETUP_OFFSET 24 -+/** Write-to-Read Pause -+ This field defines the length of the optional pause when switching from write to read direction in the transaction. During this pause, SCK is held stable. */ -+#define SFTIME_WR2RD_PAUSE_MASK 0x00300000 -+/** field offset */ -+#define SFTIME_WR2RD_PAUSE_OFFSET 20 -+/** Read Data Position -+ This field defines when to capture valid read data bit(s) (in multiples of half of the EBU internal clock's period) relative to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. RD_POS must be less than or equal to EBU_SFTIME.sck_per (not checked in hardware) or unpredictable results may occur. */ -+#define SFTIME_RD_POS_MASK 0x000F0000 -+/** field offset */ -+#define SFTIME_RD_POS_OFFSET 16 -+/** SCK Fall-edge Position -+ This field defines the positioning of the SCK fall edge (in multiples of half of the EBU internal clock's period) with respect to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. SCKF_POS must be less than or equal to SCK_PER (not checked in hardware) or unpredictable results may occur. If EBU_SFTIME.sck_inv is set, SCKF_POS defines the positioning of the falling instead of the rising edge of SCK. In the current version of the EBU, SCKF_POS must be set 0 or unpredictable results may occur. */ -+#define SFTIME_SCKF_POS_MASK 0x0000F000 -+/** field offset */ -+#define SFTIME_SCKF_POS_OFFSET 12 -+/** SCK Rise-edge Position -+ This field defines the positioning of the SCK rise edge (in multiples of half of the EBU internal clock's period) with respect to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. SCKR_POS must be less than EBU_SFTIME.sck_per (not checked in hardware) or unpredictable results may occur. If EBU_SFTIME.sck_inv is set, SCKR_POS defines the positioning of the falling instead of the rising edge of SCK. */ -+#define SFTIME_SCKR_POS_MASK 0x00000F00 -+/** field offset */ -+#define SFTIME_SCKR_POS_OFFSET 8 -+/** SCK Feedback Clock Inversion -+ If set, read data gets captured with the falling instead of the rising edge of SCK if clock feedback is enabled in EBU_SFTIME.sck_fdbk_en. */ -+#define SFTIME_SCK_FDBK_INV 0x00000040 -+/** SCK Clock Feedback -+ If set, read data is captured using the external SCK clock feedback into the chip instead of the EBU's internal clock. Using the feedback clock compensate for the high delay over the pads and its use is required at higher frequencies. A penalty for synchronizing the read data from the SCK into the ebu_clk domain applies to the read access latency. */ -+#define SFTIME_SCK_FDBK_EN 0x00000020 -+/** Inverted SCK -+ If set, the clock to the Serial Flash devices is inverted. This also results in SCK high while a Serial Flash remains selected between transactions (keep_cs feature). In the current version of the EBU, clock inversion is not supported. SCK_INV must be set to 0 or unpredictable results may occur. */ -+#define SFTIME_SCK_INV 0x00000010 -+/** SCK Period -+ This field defines the period of the SCK clock in multiples of half of the EBU clock period. The EBU supports values between 2 and 14, corresponding to a frequency ratio range from 1:1. to 1:7 between SCK and the internal clock. Other values are prohibited and result in unpredictable behaviour. In the current version of the EBU, odd values for SCK_PER are not supported. */ -+#define SFTIME_SCK_PER_MASK 0x0000000F -+/** field offset */ -+#define SFTIME_SCK_PER_OFFSET 0 -+ -+/* Fields of "Serial Flash Status Register" */ -+/** Command Overwrite Error -+ This bit is set on an attempt to start an indirect access while a previous indirect access has not finished. The bit remains unaltered when the software writes a '0' and is toggled when a '1' is written. This toggle-by-write-1 behavior allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit to clear after it has been set by the Serial Flash protocol engine. */ -+#define SFSTAT_CMD_OVWRT_ERR 0x40000000 -+/** Command Error -+ This bit is set when the EBU discards an indirect or direct access to/from a Serial Flash. The bit remains unaltered when the software writes a '0' and is toggled when a '1' is written. This toggle-by-write-1 behavior allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit to clear after it has been set by the Serial Flash protocol engine. */ -+#define SFSTAT_CMD_ERR 0x20000000 -+/** Access Command Pending -+ If set, indicates that access from/to a Serial Flash device has not finished yet. */ -+#define SFSTAT_CMD_PEND 0x00400000 -+/** External Device Selected -+ If set, indicates that the Chip Select of a Serial Flash device is currently active on the External Bus. */ -+#define SFSTAT_SELECTED 0x00200000 -+/** Protocol Engine Active -+ If set, indicates that the EBU's Serial Flash protocol engine is active. */ -+#define SFSTAT_ACTIVE 0x00100000 -+/** Page Buffer Invalidate -+ When writing a one to this bit, bits PB_VALID and PB_UPDATE are both cleared, thereby invalidating the page buffer for access to/from the Serial Flash device. After invalidating the buffer, PB_INVALID is automatically cleared so that it always reads as 0. */ -+#define SFSTAT_PB_INVALID 0x00010000 -+/** Page Buffer Update -+ This bit is set when data in the page buffer gets modified. It is cleared when new data gets loaded to the page buffer, when it is written back to the device (WRITE_PAGE command) or when PB_VALID gets cleared. */ -+#define SFSTAT_PB_UPDATE 0x00002000 -+/** Page Buffer Valid -+ This bit is set after the last data byte of a LOAD_PAGE command has been stored in the page buffer or when the page buffer is explicitely validated via a VALIDATE_PAGE special command. It remains set until the page buffer gets invalidated by writing a 1 to PB_INVALID or any of the LOAD_PAGE special commands. While PB_VALID is set, all accesses to the buffered address range are diverted to the page buffer with no access being performed on the External Bus. */ -+#define SFSTAT_PB_VALID 0x00001000 -+/** Page Buffer Busy -+ The bit is set when the EBU starts executing a LOAD_PAGE or a WRITE_PAGE command and cleared when the last byte of the requested page has been transferred from/to the external device. The inverted value of PB_BUSY is output on the EBU interface and may trigger a system interrupt. */ -+#define SFSTAT_PB_BUSY 0x00000100 -+/** Device Busy -+ This bit is set by the Serial Flash protocol engine when an indirect access is performed via register EBU_SFCMD with SET_BUSY being set. While busy is set, access to the Serial Flash is very limited and all transactions are error-terminated except when explicitly marked to ignore the busy status. If the EBU is configured in EBU_SFCON.EOBDM to automatically poll the busy status of the device, busy is cleared as soon as the device is found to be idle again. On a software write, busy remains unaltered when written with a '0' and is toggled when written with a '1', respectively.This toggle-by-write-1 behaviour allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit after it got set by the Serial Flash protocol engine and no automatic busy detection is configured in EBU_SFCON.EOBDM Then the software has to clear busy when it finds the device to be no longer busy by either polling the device's status register via the EBU or by waiting for the maximum busy time of the operation started in the device. */ -+#define SFSTAT_BUSY 0x00000001 -+ -+/* Fields of "Serial Flash Command Register" */ -+/** Command Type -+ This field is a qualifier of the command opcode in EBU_SFCMD.opc. Two types */ -+#define SFCMD_CMDTYPE 0x80000000 -+/* The opcode in EBU_SFCMD.opc is directly used in the command phase of a single transaction to the Serial Flash device. -+#define SFCMD_CMDTYPE_ACCESS_CMD 0x00000000 */ -+/** The opcode in EBU_SFCMD.opc is used to start a special command in the Serial Flash Controller which might include any number of external transactions to/from the Serial Flash device. */ -+#define SFCMD_CMDTYPE_SPECIAL_CMD 0x80000000 -+/** Device Port Width -+ Defines the number of signal lines to be used with direct read access from a Serial Flash as defined for the command with opcode opc. The encoding of this field is the same as forDA_PORTW. */ -+#define SFCMD_PORTW_MASK 0x70000000 -+/** field offset */ -+#define SFCMD_PORTW_OFFSET 28 -+/** Bidirectional Signal Lines -+ If set selects bidirectional signal lines to be used for the data transfer. */ -+#define SFCMD_BIDIR 0x08000000 -+/** Chip Select -+ This field selects which of the EBU's Chip Selects to activated for the command that is written to EBU_SFCMD.opc. A value between 0 and 3 selects one of the EBU's main CSs while 4 to 7 chooses one of the Auxiliary Chip Selects CSA[3:0], respectively. */ -+#define SFCMD_CS_MASK 0x07000000 -+/** field offset */ -+#define SFCMD_CS_OFFSET 24 -+/** Disable Auto Address Increment -+ By default, the address in register EBU_SFADDR is automatically incremented with each data byte being transferred. By setting this bit, the auto-increment can be disabled. */ -+#define SFCMD_DIS_AAI 0x00800000 -+/** Address Length -+ Defines the number of address bytes from register EBU_SFADDR to sent in the address phase of the transaction to/from the Serial Flash. Note: Address bytes are also sent when the command has no data. */ -+#define SFCMD_ALEN_MASK 0x00700000 -+/** field offset */ -+#define SFCMD_ALEN_OFFSET 20 -+/** Dummy Phase Length -+ Defines the number of dummy bytes to send to the device between the command/address phase and the data phase of a transaction. Note:Dummy bytes are also sent when the command has no address and/or no data. */ -+#define SFCMD_DUMLEN_MASK 0x000F0000 -+/** field offset */ -+#define SFCMD_DUMLEN_OFFSET 16 -+/** Keep Chip Select -+ Defines whether the Serial Flash remains selected after the indirect access transaction has been finished. */ -+#define SFCMD_KEEP_CS 0x00008000 -+/* After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address. -+#define SFCMD_KEEP_CS_DESELECT 0x00000000 */ -+/** Chip Select of device is kept active after direct read access so that device is ready for follow-up read of next sequential byte without the need to send command and address. If the next command is to another Chip Select, is a different command or accesses a different address, the EBU first deactivates the kept Chip Select before it starts the new transaction with sending the command opcode and address. */ -+#define SFCMD_KEEP_CS_KEEP_SELECTED 0x00008000 -+/** Set Busy Flag -+ If set, starting the command sets EBU_SFSTAT.busy. */ -+#define SFCMD_SET_BUSY 0x00004000 -+/** Ignore Busy -+ By default, the EBU error terminates all attempts to access a Serial Flash while EBU_SFSTAT.busy is set. Setting this bit overrules this error termination and permits the command written to EBU_SFCMD.opc to proceed to the External Bus. Normally, this bit is only set to execute a Read Status Register command to the Serial Flash, but may also be used for any other type of access the device is able to handle while it is busy. */ -+#define SFCMD_IGNORE_BUSY 0x00002000 -+/** Skip Opcode -+ If this bit is set, the opcode in field OPC is not sent to the External Bus, but the external transaction starts with sending the first address byte (if ALEN 0), the first dummy byte (if alen = 0 and DUMLEN 0), or directly with transferring the data bytes (if ALEN = DUMLEN = 0 and DLEN 0). Limiting the external transfer to just the data phase - together with the keep_cs feature - allow to transfer any number of data bytes for a device command sent via EBU_SFCMD by keeping the device selected between accesses and chaining multiple indirect access commands each transferring up to 4 data bytes from/to register EBU_SFDATA. */ -+#define SFCMD_SKIP_OPC 0x00001000 -+/** Data Length -+ This field defines the number of data bytes to transfer in the data phase of the command. For a read command, the data bytes are stored in register EBU_SFDATA, for a write transfer they are taken from that register. As the data register can hold at most 4 bytes, DLEN is restricted to the range [0..4]. */ -+#define SFCMD_DLEN_MASK 0x00000E00 -+/** field offset */ -+#define SFCMD_DLEN_OFFSET 9 -+/** Direction -+ Defines the direction of the data transfer (if any) in the data phase of the transaction to/from the serial bus. */ -+#define SFCMD_DIR 0x00000100 -+/* dlen bytes of data are read from the Serial Flash during the data phase of the transaction and stored in register EBU_SFDATA. -+#define SFCMD_DIR_READ 0x00000000 */ -+/** dlen bytes of data are read from register EBU_SFDATA and written to the Serial Flash during the data phase of the transactione */ -+#define SFCMD_DIR_WRITE 0x00000100 -+/** Command Opcode -+ A write access to this field starts an Indirect Access command in the EBU's Serial Flash controller. Two types of commands are supported (selected in EBU_SFCMD.cmdtype) and determine how the EBU interprets the opcode:- - For a ACCESS_CMD, a single transaction is executed to/from the Serial Flash device and the OPC is sent to the device in the command phase of the protocol. The number of address, dummy and data bytes to transfer with the command are given in fields ALEN, DUMLEN, and DLEN of register EBU_SFCMD, respectively. - For a SPECIAL_CMD, the EBU starts a complex operation that usually involves multiple transactions to/from the Serial Flash device. See Section 3.18.2.5 for an overview of the complex commands currently supported. */ -+#define SFCMD_OPC_MASK 0x000000FF -+/** field offset */ -+#define SFCMD_OPC_OFFSET 0 -+ -+/* Fields of "Serial Flash Address Register" */ -+/** Address -+ Before writing to register EBU_SFCMD to start a command that requires the transfer of an address, the address to use must be stored in this register. If not disabled in EBU_SFCMD.dis_aai, ADDR is incremented automatically with each data byte transferred between the EBU and the Serial Flash for an indirect access. Note:Register EBU_SFADDR is only used for access in Indirect Access Mode and is ignored/remains unaltered for all accesses in Direct Access Mode. */ -+#define SFADDR_ADDR_MASK 0xFFFFFFFF -+/** field offset */ -+#define SFADDR_ADDR_OFFSET 0 -+ -+/* Fields of "Serial Flash Data Register" */ -+/** Data Bytes -+ Before writing to register EBU_SFCMD to start a command that requires the transfer of data from the EBU to the Serial Flash device (write access), the data to send must be stored in this register. The data bytes have to be right-aligned in this register, that is, the last byte to send must be placed in bits DATA[7:0], the second-to-last byte in bits DATA[15:8], etc.. Similarly, for a read access with data being transferred from the Serial Flash to the EBU, this register collects the read data received from the device. The read data is right-aligned, that is, the last byte received gets placed in bits DATA[7:0], the second-to-last byte in bits DATA[15:8], etc... The number of data bytes to be transferred between EBU and the Serial Flash is defined in EBU_SFCMD.DLEN. Note:Register EBU_SFDATA is only used for accesses in Indirect Access Mode and is ignored/remains unaltered for all accesses in Direct Access Mode. */ -+#define SFDATA_DATA_MASK 0xFFFFFFFF -+/** field offset */ -+#define SFDATA_DATA_OFFSET 0 -+ -+/* Fields of "Serial Flash I/O Control Register" */ -+/** Start of Write Delay -+ By default, the EBU starts driving to AD[3:0] two EBU clock cycles before asserting the CS for an external Serial Flash access. For write accesses, this delay can be increased via field SOWD. */ -+#define SFIO_SOWD_MASK 0x0000F000 -+/** field offset */ -+#define SFIO_SOWD_OFFSET 12 -+/** End of Write Delay -+ This field defines the time (in number of EBU clock cycles) for which the EBU keeps driving the External Bus AD[3:0] after deassertion of the device's CS. */ -+#define SFIO_EOWD_MASK 0x00000F00 -+/** field offset */ -+#define SFIO_EOWD_OFFSET 8 -+/** Data Output -+ The EBU always controls the AD[3:0] pins while a CS for a Serial Flash device is asserted. Field UNUSED_WD defines the values being driven to these pins while the Serial Flash controller is not writing data to or is reading data from the device via the respective line. See Section 3.18.6 for details. */ -+#define SFIO_UNUSED_WD_MASK 0x0000000F -+/** field offset */ -+#define SFIO_UNUSED_WD_OFFSET 0 -+ -+/*! @} */ /* EBU_REGISTER */ -+ -+#endif /* _ebu_reg_h */ diff --git a/target/linux/lantiq/patches-3.3/101-sdk-compat.patch b/target/linux/lantiq/patches-3.3/101-sdk-compat.patch deleted file mode 100644 index ca8d92eda3..0000000000 --- a/target/linux/lantiq/patches-3.3/101-sdk-compat.patch +++ /dev/null @@ -1,63 +0,0 @@ ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/sysctrl.h -@@ -0,0 +1,60 @@ -+/* -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ * -+ * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland -+ */ -+ -+#ifndef __FALCON_SYSCTRL_H -+#define __FALCON_SYSCTRL_H -+ -+#include -+ -+static inline void sys1_hw_activate(u32 mask) -+{ ltq_sysctl_activate(SYSCTL_SYS1, mask); } -+static inline void sys1_hw_deactivate(u32 mask) -+{ ltq_sysctl_deactivate(SYSCTL_SYS1, mask); } -+static inline void sys1_hw_clk_enable(u32 mask) -+{ ltq_sysctl_clken(SYSCTL_SYS1, mask); } -+static inline void sys1_hw_clk_disable(u32 mask) -+{ ltq_sysctl_clkdis(SYSCTL_SYS1, mask); } -+static inline void sys1_hw_activate_or_reboot(u32 mask) -+{ ltq_sysctl_reboot(SYSCTL_SYS1, mask); } -+ -+static inline void sys_eth_hw_activate(u32 mask) -+{ ltq_sysctl_activate(SYSCTL_SYSETH, mask); } -+static inline void sys_eth_hw_deactivate(u32 mask) -+{ ltq_sysctl_deactivate(SYSCTL_SYSETH, mask); } -+static inline void sys_eth_hw_clk_enable(u32 mask) -+{ ltq_sysctl_clken(SYSCTL_SYSETH, mask); } -+static inline void sys_eth_hw_clk_disable(u32 mask) -+{ ltq_sysctl_clkdis(SYSCTL_SYSETH, mask); } -+static inline void sys_eth_hw_activate_or_reboot(u32 mask) -+{ ltq_sysctl_reboot(SYSCTL_SYSETH, mask); } -+ -+static inline void sys_gpe_hw_activate(u32 mask) -+{ ltq_sysctl_activate(SYSCTL_SYSGPE, mask); } -+static inline void sys_gpe_hw_deactivate(u32 mask) -+{ ltq_sysctl_deactivate(SYSCTL_SYSGPE, mask); } -+static inline void sys_gpe_hw_clk_enable(u32 mask) -+{ ltq_sysctl_clken(SYSCTL_SYSGPE, mask); } -+static inline void sys_gpe_hw_clk_disable(u32 mask) -+{ ltq_sysctl_clkdis(SYSCTL_SYSGPE, mask); } -+static inline void sys_gpe_hw_activate_or_reboot(u32 mask) -+{ ltq_sysctl_reboot(SYSCTL_SYSGPE, mask); } -+static inline int sys_gpe_hw_is_activated(u32 mask) -+{ return 1; } -+ -+#endif /* __FALCON_SYSCTRL_H */ diff --git a/target/linux/lantiq/patches-3.3/105-falcon_header_update.patch b/target/linux/lantiq/patches-3.3/105-falcon_header_update.patch deleted file mode 100644 index d428de860c..0000000000 --- a/target/linux/lantiq/patches-3.3/105-falcon_header_update.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h -+++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h -@@ -18,6 +18,8 @@ - #ifndef _FALCON_IRQ__ - #define _FALCON_IRQ__ - -+#define IM_NUM 5 -+ - #define INT_NUM_IRQ0 8 - #define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) - #define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32)diff --git a/target/linux/lantiq/patches-2.6.32/300-svip_header.patch b/target/linux/lantiq/patches-2.6.32/300-svip_header.patch diff --git a/target/linux/lantiq/patches-3.3/206-machtypes.patch b/target/linux/lantiq/patches-3.3/206-machtypes.patch deleted file mode 100644 index f6f24ea4b4..0000000000 --- a/target/linux/lantiq/patches-3.3/206-machtypes.patch +++ /dev/null @@ -1,321 +0,0 @@ ---- a/arch/mips/lantiq/machtypes.h -+++ b/arch/mips/lantiq/machtypes.h -@@ -20,6 +20,42 @@ enum lantiq_mach_type { - LANTIQ_MACH_EASY98000, /* Falcon Eval Board, NOR Flash */ - LANTIQ_MACH_EASY98000SF, /* Falcon Eval Board, Serial Flash */ - LANTIQ_MACH_EASY98000NAND, /* Falcon Eval Board, NAND Flash */ -+ LANTIQ_MACH_EASY98020, /* EASY98020 Eval Board */ -+ LANTIQ_MACH_EASY98020_1LAN, /* EASY98020 Eval Board (1 LAN port) */ -+ LANTIQ_MACH_EASY98020_2LAN, /* EASY98020 Eval Board (2 LAN port) */ -+ LANTIQ_MACH_95C3AM1, /* 95C3AM1 Eval Board */ -+ -+ /* Arcadyan */ -+ LANTIQ_MACH_ARV3527P, /* Arcor easybox a401 */ -+ LANTIQ_MACH_ARV4510PW, /* Wippies Homebox */ -+ LANTIQ_MACH_ARV4518PW, /* Airties WAV-221, SMC-7908A-ISP */ -+ LANTIQ_MACH_ARV4519PW, /* Vodafone, Pirelli */ -+ LANTIQ_MACH_ARV4520PW, /* Airties WAV-281, Arcor EasyboxA800 */ -+ LANTIQ_MACH_ARV452CPW, /* Arcor EasyboxA801 */ -+ LANTIQ_MACH_ARV4525PW, /* Speedport W502V */ -+ LANTIQ_MACH_ARV7525PW, /* Speedport W303V */ -+ LANTIQ_MACH_ARV752DPW, /* Arcor easybox a802 */ -+ LANTIQ_MACH_ARV752DPW22, /* Arcor easybox a803 */ -+ LANTIQ_MACH_ARV7518PW, /* ASTORIA */ -+ -+ /* Netgear */ -+ LANTIQ_MACH_DGN3500B, /* Netgear DGN3500 */ -+ -+ /* FRITZ!BOX */ -+ LANTIQ_MACH_FRITZ3370, /* FRITZ!BOX 3370 vdsl cpe */ -+ LANTIQ_MACH_FRITZ7320, /* FRITZ!BOX 7320 1&1 homeserver */ -+ -+ /* Gigaset */ -+ LANTIQ_MACH_GIGASX76X, /* Gigaset SX76x */ -+ -+ /* Buffalo */ -+ LANTIQ_MACH_WBMR, /* WBMR-HP-G300H */ -+ -+ /* ZyXEL */ -+ LANTIQ_MACH_P2601HNFX, /* ZyXEL P-2601HN-Fx */ -+ -+ /* ZTE */ -+ LANTIQ_MACH_H201L, /* ZTE ZXV10 H201L */ - }; - - #endif ---- a/arch/mips/lantiq/xway/Kconfig -+++ b/arch/mips/lantiq/xway/Kconfig -@@ -6,6 +6,38 @@ config LANTIQ_MACH_EASY50712 - bool "Easy50712 - Danube" - default y - -+config LANTIQ_MACH_ARV -+ bool "ARV" -+ default y -+ -+config LANTIQ_MACH_NETGEAR -+ bool "Netgear" -+ default y -+ -+config LANTIQ_MACH_GIGASX76X -+ bool "GIGASX76X" -+ default y -+ -+config LANTIQ_MACH_WBMR -+ bool "WBMR-HP-G300H" -+ default y -+ -+config LANTIQ_MACH_P2601HNFX -+ bool "P2601HNFX" -+ default y -+ -+config LANTIQ_MACH_H201L -+ bool "H201L" -+ default y -+ -+config LANTIQ_MACH_FRITZ_VR9 -+ bool "FRITZ3370" -+ default y -+ -+config LANTIQ_MACH_FRITZ_AR9 -+ bool "FRITZ7320" -+ default y -+ - endmenu - - choice ---- a/arch/mips/lantiq/xway/Makefile -+++ b/arch/mips/lantiq/xway/Makefile -@@ -2,3 +2,11 @@ obj-y := sysctrl.o reset.o gpio.o gpio_s - - obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o - obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o -+obj-$(CONFIG_LANTIQ_MACH_ARV) += mach-arv.o -+obj-$(CONFIG_LANTIQ_MACH_FRITZ_AR9) += mach-fritz_ar9.o -+obj-$(CONFIG_LANTIQ_MACH_FRITZ_VR9) += mach-fritz_vr9.o -+obj-$(CONFIG_LANTIQ_MACH_GIGASX76X) += mach-gigasx76x.o -+obj-$(CONFIG_LANTIQ_MACH_NETGEAR) += mach-netgear.o -+obj-$(CONFIG_LANTIQ_MACH_WBMR) += mach-wbmr.o -+obj-$(CONFIG_LANTIQ_MACH_P2601HNFX) += mach-p2601hnfx.o -+obj-$(CONFIG_LANTIQ_MACH_H201L) += mach-h201l.o ---- a/arch/mips/lantiq/falcon/Kconfig -+++ b/arch/mips/lantiq/falcon/Kconfig -@@ -6,6 +6,14 @@ config LANTIQ_MACH_EASY98000 - bool "Easy98000" - default y - -+config LANTIQ_MACH_EASY98020 -+ bool "Easy98020" -+ default y -+ -+config LANTIQ_MACH_95C3AM1 -+ bool "95C3AM1" -+ default y -+ - endmenu - - endif ---- a/arch/mips/lantiq/falcon/Makefile -+++ b/arch/mips/lantiq/falcon/Makefile -@@ -1,2 +1,6 @@ - obj-y := prom.o reset.o sysctrl.o devices.o gpio.o -+obj-$(CONFIG_LANTIQ_MACH_EASY98000) += addon-easy98000.o -+obj-$(CONFIG_LANTIQ_MACH_EASY98000) += dev-leds-easy98000-cpld.o - obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o -+obj-$(CONFIG_LANTIQ_MACH_EASY98020) += mach-easy98020.o -+obj-$(CONFIG_LANTIQ_MACH_95C3AM1) += mach-95C3AM1.o ---- a/arch/mips/lantiq/falcon/mach-easy98000.c -+++ b/arch/mips/lantiq/falcon/mach-easy98000.c -@@ -1,23 +1,38 @@ --/* -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License version 2 as published -- * by the Free Software Foundation. -- * -- * Copyright (C) 2011 Thomas Langer -- * Copyright (C) 2011 John Crispin -- */ -- -+#include - #include -+#include -+#include -+#include -+#include -+#include - #include -+#include -+#include -+#include -+#include -+#include -+#include - #include - #include - #include -+#include - - #include "../machtypes.h" - - #include "devices.h" -+#include "dev-leds-gpio.h" -+ -+#define EASY98000_GPIO_LED_0 9 -+#define EASY98000_GPIO_LED_1 10 -+#define EASY98000_GPIO_LED_2 11 -+#define EASY98000_GPIO_LED_3 12 -+#define EASY98000_GPIO_LED_4 13 -+#define EASY98000_GPIO_LED_5 14 - --static struct mtd_partition easy98000_nor_partitions[] = { -+extern unsigned char ltq_ethaddr[6]; -+ -+static struct mtd_partition easy98000_nor_partitions[] = -+{ - { - .name = "uboot", - .offset = 0x0, -@@ -35,7 +50,7 @@ static struct mtd_partition easy98000_no - }, - }; - --struct physmap_flash_data easy98000_nor_flash_data = { -+static struct physmap_flash_data easy98000_nor_flash_data = { - .nr_parts = ARRAY_SIZE(easy98000_nor_partitions), - .parts = easy98000_nor_partitions, - }; -@@ -55,12 +70,105 @@ static struct spi_board_info easy98000_s - .platform_data = &easy98000_spi_flash_platform_data - }; - -+static struct gpio_led easy98000_leds_gpio[] __initdata = { -+ { -+ .name = "easy98000:green:0", -+ .gpio = EASY98000_GPIO_LED_0, -+ .active_low = 0, -+ }, { -+ .name = "easy98000:green:1", -+ .gpio = EASY98000_GPIO_LED_1, -+ .active_low = 0, -+ }, { -+ .name = "easy98000:green:2", -+ .gpio = EASY98000_GPIO_LED_2, -+ .active_low = 0, -+ }, { -+ .name = "easy98000:green:3", -+ .gpio = EASY98000_GPIO_LED_3, -+ .active_low = 0, -+ }, { -+ .name = "easy98000:green:4", -+ .gpio = EASY98000_GPIO_LED_4, -+ .active_low = 0, -+ }, { -+ .name = "easy98000:green:5", -+ .gpio = EASY98000_GPIO_LED_5, -+ .active_low = 0, -+ } -+}; -+ -+#define CONFIG_DM9000_BASE 0x14000000 -+#define DM9000_IO (CONFIG_DM9000_BASE + 3) -+#define DM9000_DATA (CONFIG_DM9000_BASE + 1) -+ -+static struct dm9000_plat_data dm9000_plat_data = { -+ .flags = DM9000_PLATF_8BITONLY, -+ //.dev_addr = { }, /* possibility to provide an ethernet address for the chip */ -+}; -+ -+static struct resource dm9000_resources[] = { -+ MEM_RES("dm9000_io", DM9000_IO, DM9000_IO), -+ MEM_RES("dm9000_data", DM9000_DATA, DM9000_DATA), -+ [2] = { -+ /* with irq (210 -> gpio 110) the driver is very unreliable */ -+ .start = -1, /* use polling */ -+ .end = -1, -+ .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, -+ }, -+}; -+ -+static struct platform_device dm9000_platform = { -+ .name = "dm9000", -+ .id = 0, -+ .num_resources = ARRAY_SIZE(dm9000_resources), -+ .resource = dm9000_resources, -+ .dev = { -+ .platform_data = (void *) &dm9000_plat_data, -+ } -+}; -+ -+extern int easy98000_addon_has_dm9000(void); -+static void __init register_davicom(void) -+{ -+ if (!easy98000_addon_has_dm9000()) -+ return; -+ -+ if (!is_valid_ether_addr(ltq_ethaddr)) -+ random_ether_addr(dm9000_plat_data.dev_addr); -+ else { -+ memcpy(dm9000_plat_data.dev_addr, ltq_ethaddr, 6); -+ /* change to "Locally Administered Address" */ -+ dm9000_plat_data.dev_addr[0] |= 0x2; -+ } -+ platform_device_register(&dm9000_platform); -+} -+ -+static struct i2c_gpio_platform_data easy98000_i2c_gpio_data = { -+ .sda_pin = 107, -+ .scl_pin = 108, -+}; -+ -+static struct platform_device easy98000_i2c_gpio_device = { -+ .name = "i2c-gpio", -+ .id = 0, -+ .dev = { -+ .platform_data = &easy98000_i2c_gpio_data, -+ } -+}; -+ -+void __init register_easy98000_cpld(void) -+{ -+ platform_device_register_simple("easy98000_cpld_led", 0, NULL, 0); -+ platform_device_register_simple("easy98000_addon", 0, NULL, 0); -+} -+ - /* setup gpio based spi bus/device for access to the eeprom on the board */ --#define SPI_GPIO_MRST 102 --#define SPI_GPIO_MTSR 103 --#define SPI_GPIO_CLK 104 --#define SPI_GPIO_CS0 105 --#define SPI_GPIO_CS1 106 -+#define SPI_GPIO_MRST 102 -+#define SPI_GPIO_MTSR 103 -+#define SPI_GPIO_CLK 104 -+#define SPI_GPIO_CS0 105 -+#define SPI_GPIO_CS1 106 - #define SPI_GPIO_BUS_NUM 1 - - static struct spi_gpio_platform_data easy98000_spi_gpio_data = { -@@ -94,11 +202,22 @@ static struct spi_board_info easy98000_s - }; - - static void __init --easy98000_init_common(void) -+easy98000_spi_gpio_init(void) - { - spi_register_board_info(&easy98000_spi_gpio_devices, 1); - platform_device_register(&easy98000_spi_gpio_device); -+} -+ -+static void __init -+easy98000_init_common(void) -+{ - falcon_register_i2c(); -+ platform_device_register(&easy98000_i2c_gpio_device); -+ register_davicom(); -+ ltq_add_device_leds_gpio(-1, ARRAY_SIZE(easy98000_leds_gpio), -+ easy98000_leds_gpio); -+ register_easy98000_cpld(); -+ easy98000_spi_gpio_init(); - } - - static void __init diff --git a/target/linux/lantiq/patches-3.3/207-devices.patch b/target/linux/lantiq/patches-3.3/207-devices.patch deleted file mode 100644 index 693e361f4a..0000000000 --- a/target/linux/lantiq/patches-3.3/207-devices.patch +++ /dev/null @@ -1,191 +0,0 @@ ---- a/arch/mips/lantiq/devices.c -+++ b/arch/mips/lantiq/devices.c -@@ -18,6 +18,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -100,3 +101,20 @@ void __init ltq_register_pci(struct ltq_ - pr_err("kernel is compiled without PCI support\n"); - } - #endif -+ -+static unsigned int *cp1_base = 0; -+unsigned int* -+ltq_get_cp1_base(void) -+{ -+ return cp1_base; -+} -+EXPORT_SYMBOL(ltq_get_cp1_base); -+ -+void __init -+ltq_register_tapi(void) -+{ -+#define CP1_SIZE (1 << 20) -+ dma_addr_t dma; -+ cp1_base = -+ (void*)CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE, &dma, GFP_ATOMIC)); -+} ---- a/arch/mips/lantiq/devices.h -+++ b/arch/mips/lantiq/devices.h -@@ -23,5 +23,6 @@ extern void ltq_register_nor(struct phys - extern void ltq_register_wdt(void); - extern void ltq_register_asc(int port); - extern void ltq_register_pci(struct ltq_pci_data *data); -+extern void ltq_register_tapi(void); - - #endif ---- a/arch/mips/lantiq/xway/Makefile -+++ b/arch/mips/lantiq/xway/Makefile -@@ -1,5 +1,8 @@ - obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o prom.o nand.o timer.o dev-ifxhcd.o - -+obj-y += dev-dwc_otg.o -+obj-$(CONFIG_PCI) += dev-wifi-rt2x00.o dev-wifi-athxk.o pci-ath-fixup.o -+ - obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o - obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o - obj-$(CONFIG_LANTIQ_MACH_ARV) += mach-arv.o ---- a/arch/mips/lantiq/xway/devices.c -+++ b/arch/mips/lantiq/xway/devices.c -@@ -19,6 +19,7 @@ - #include - #include - #include -+#include - - #include - #include -@@ -119,3 +120,97 @@ ltq_register_vrx200(struct ltq_eth_data - ltq_vrx200.dev.platform_data = eth; - platform_device_register(<q_vrx200); - } -+ -+/* ebu */ -+static struct resource ltq_ebu_resource = -+{ -+ .name = "gpio_ebu", -+ .start = LTQ_EBU_GPIO_START, -+ .end = LTQ_EBU_GPIO_START + LTQ_EBU_GPIO_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+}; -+ -+static struct platform_device ltq_ebu = -+{ -+ .name = "ltq_ebu", -+ .resource = <q_ebu_resource, -+ .num_resources = 1, -+}; -+ -+void __init -+ltq_register_gpio_ebu(unsigned int value) -+{ -+ ltq_ebu.dev.platform_data = (void*) value; -+ platform_device_register(<q_ebu); -+} -+ -+/* gpio buttons */ -+static struct gpio_buttons_platform_data ltq_gpio_buttons_platform_data; -+ -+static struct platform_device ltq_gpio_buttons_platform_device = -+{ -+ .name = "gpio-buttons", -+ .id = 0, -+ .dev = { -+ .platform_data = (void *) <q_gpio_buttons_platform_data, -+ }, -+}; -+ -+void __init -+ltq_register_gpio_buttons(struct gpio_button *buttons, int cnt) -+{ -+ ltq_gpio_buttons_platform_data.buttons = buttons; -+ ltq_gpio_buttons_platform_data.nbuttons = cnt; -+ platform_device_register(<q_gpio_buttons_platform_device); -+} -+ -+static struct resource ltq_spi_resources[] = { -+ { -+ .start = LTQ_SSC_BASE_ADDR, -+ .end = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ IRQ_RES(spi_tx, LTQ_SSC_TIR), -+ IRQ_RES(spi_rx, LTQ_SSC_RIR), -+ IRQ_RES(spi_err, LTQ_SSC_EIR), -+}; -+ -+static struct resource ltq_spi_resources_ar9[] = { -+ { -+ .start = LTQ_SSC_BASE_ADDR, -+ .end = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ IRQ_RES(spi_tx, LTQ_SSC_TIR_AR9), -+ IRQ_RES(spi_rx, LTQ_SSC_RIR_AR9), -+ IRQ_RES(spi_err, LTQ_SSC_EIR), -+}; -+ -+static struct resource ltq_spi_resources_ase[] = { -+ { -+ .start = LTQ_SSC_BASE_ADDR, -+ .end = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ IRQ_RES(spi_tx, LTQ_SSC_TIR_ASE), -+ IRQ_RES(spi_rx, LTQ_SSC_RIR_ASE), -+ IRQ_RES(spi_err, LTQ_SSC_EIR_ASE), -+}; -+ -+static struct platform_device ltq_spi = { -+ .name = "ltq_spi", -+ .resource = ltq_spi_resources, -+ .num_resources = ARRAY_SIZE(ltq_spi_resources), -+}; -+ -+void __init ltq_register_spi(struct ltq_spi_platform_data *pdata, -+ struct spi_board_info const *info, unsigned n) -+{ -+ if (ltq_is_ar9()) -+ ltq_spi.resource = ltq_spi_resources_ar9; -+ else if (ltq_is_ase()) -+ ltq_spi.resource = ltq_spi_resources_ase; -+ spi_register_board_info(info, n); -+ ltq_spi.dev.platform_data = pdata; -+ platform_device_register(<q_spi); -+} ---- a/arch/mips/lantiq/xway/devices.h -+++ b/arch/mips/lantiq/xway/devices.h -@@ -11,6 +11,8 @@ - - #include "../devices.h" - #include -+#include -+#include - - extern void ltq_register_gpio(void); - extern void ltq_register_gpio_stp(void); -@@ -18,5 +20,9 @@ extern void ltq_register_ase_asc(void); - extern void ltq_register_etop(struct ltq_eth_data *eth); - extern void xway_register_nand(struct mtd_partition *parts, int count); - extern void ltq_register_vrx200(struct ltq_eth_data *eth); -+extern void ltq_register_gpio_ebu(unsigned int value); -+extern void ltq_register_spi(struct ltq_spi_platform_data *pdata, -+ struct spi_board_info const *info, unsigned n); -+extern void ltq_register_gpio_buttons(struct gpio_button *buttons, int cnt); - - #endif ---- a/arch/mips/lantiq/Makefile -+++ b/arch/mips/lantiq/Makefile -@@ -4,7 +4,7 @@ - # under the terms of the GNU General Public License version 2 as published - # by the Free Software Foundation. - --obj-y := irq.o setup.o clk.o prom.o devices.o -+obj-y := irq.o setup.o clk.o prom.o devices.o dev-gpio-leds.o dev-gpio-buttons.o - - obj-$(CONFIG_EARLY_PRINTK) += early_printk.o - diff --git a/target/linux/lantiq/patches-3.3/208-fix-mach-easy98000.patch b/target/linux/lantiq/patches-3.3/208-fix-mach-easy98000.patch deleted file mode 100644 index e1593bc755..0000000000 --- a/target/linux/lantiq/patches-3.3/208-fix-mach-easy98000.patch +++ /dev/null @@ -1,68 +0,0 @@ ---- a/arch/mips/lantiq/falcon/mach-easy98000.c -+++ b/arch/mips/lantiq/falcon/mach-easy98000.c -@@ -17,10 +17,11 @@ - #include - #include - -+#include -+ - #include "../machtypes.h" - - #include "devices.h" --#include "dev-leds-gpio.h" - - #define EASY98000_GPIO_LED_0 9 - #define EASY98000_GPIO_LED_1 10 -@@ -29,7 +30,16 @@ - #define EASY98000_GPIO_LED_4 13 - #define EASY98000_GPIO_LED_5 14 - --extern unsigned char ltq_ethaddr[6]; -+static unsigned char ltq_ethaddr[6] = {0}; -+ -+static int __init falcon_set_ethaddr(char *str) -+{ -+ sscanf(str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", -+ <q_ethaddr[0], <q_ethaddr[1], <q_ethaddr[2], -+ <q_ethaddr[3], <q_ethaddr[4], <q_ethaddr[5]); -+ return 0; -+} -+__setup("ethaddr=", falcon_set_ethaddr); - - static struct mtd_partition easy98000_nor_partitions[] = - { -@@ -70,7 +80,7 @@ static struct spi_board_info easy98000_s - .platform_data = &easy98000_spi_flash_platform_data - }; - --static struct gpio_led easy98000_leds_gpio[] __initdata = { -+static struct gpio_led easy98000_gpio_leds[] __initdata = { - { - .name = "easy98000:green:0", - .gpio = EASY98000_GPIO_LED_0, -@@ -104,12 +114,11 @@ static struct gpio_led easy98000_leds_gp - - static struct dm9000_plat_data dm9000_plat_data = { - .flags = DM9000_PLATF_8BITONLY, -- //.dev_addr = { }, /* possibility to provide an ethernet address for the chip */ - }; - - static struct resource dm9000_resources[] = { -- MEM_RES("dm9000_io", DM9000_IO, DM9000_IO), -- MEM_RES("dm9000_data", DM9000_DATA, DM9000_DATA), -+ MEM_RES("dm9000_io", DM9000_IO, 1), -+ MEM_RES("dm9000_data", DM9000_DATA, 1), - [2] = { - /* with irq (210 -> gpio 110) the driver is very unreliable */ - .start = -1, /* use polling */ -@@ -214,8 +223,8 @@ easy98000_init_common(void) - falcon_register_i2c(); - platform_device_register(&easy98000_i2c_gpio_device); - register_davicom(); -- ltq_add_device_leds_gpio(-1, ARRAY_SIZE(easy98000_leds_gpio), -- easy98000_leds_gpio); -+ ltq_add_device_gpio_leds(-1, ARRAY_SIZE(easy98000_gpio_leds), -+ easy98000_gpio_leds); - register_easy98000_cpld(); - easy98000_spi_gpio_init(); - } diff --git a/target/linux/lantiq/patches-3.3/300-svip_header.patch b/target/linux/lantiq/patches-3.3/300-svip_header.patch deleted file mode 100644 index 6c936134c0..0000000000 --- a/target/linux/lantiq/patches-3.3/300-svip_header.patch +++ /dev/null @@ -1,9518 +0,0 @@ -Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/irq.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/irq.h 2012-07-31 15:46:02.464476159 +0200 -@@ -0,0 +1,36 @@ -+/* -+ * arch/mips/include/asm/mach-lantiq/svip/irq.h -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. -+ * -+ * Copyright (C) 2010 Lantiq -+ * -+ */ -+ -+#ifndef __IRQ_H -+#define __IRQ_H -+ -+#include -+ -+#define NR_IRQS 264 -+ -+#include_next -+ -+/* Functions for EXINT handling */ -+extern int ifx_enable_external_int(u32 exint, u32 mode); -+extern int ifx_disable_external_int(u32 exint); -+extern int ifx_external_int_level(u32 exint); -+ -+#endif -Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/lantiq_soc.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/lantiq_soc.h 2012-07-31 15:58:41.312508597 +0200 -@@ -0,0 +1,71 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2010 John Crispin -+ */ -+ -+#ifndef _LTQ_SVIP_H__ -+#define _LTQ_SVIP_H__ -+ -+#ifdef CONFIG_SOC_SVIP -+ -+#include -+ -+/* Chip IDs */ -+#define SOC_ID_SVIP 0x169 -+ -+/* SoC Types */ -+#define SOC_TYPE_SVIP 0x01 -+ -+/* ASC0/1 - serial port */ -+#define LTQ_ASC0_BASE_ADDR 0x14100100 -+#define LTQ_ASC1_BASE_ADDR 0x14100200 -+#define LTQ_ASC_SIZE 0x100 -+#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR) -+ -+#define LTQ_ASC_TIR(x) (INT_NUM_IM0_IRL0 + (x * 8)) -+#define LTQ_ASC_RIR(x) (INT_NUM_IM0_IRL0 + (x * 8) + 2) -+#define LTQ_ASC_EIR(x) (INT_NUM_IM0_IRL0 + (x * 8) + 3) -+ -+/* ICU - interrupt control unit */ -+#define LTQ_ICU_BASE_ADDR 0x14106000 -+#define LTQ_ICU_BASE_ADDR1 0x14106028 -+#define LTQ_ICU_BASE_ADDR2 0x1E016000 -+#define LTQ_ICU_BASE_ADDR3 0x1E016028 -+#define LTQ_ICU_BASE_ADDR4 0x14106050 -+#define LTQ_ICU_BASE_ADDR5 0x14106078 -+#define LTQ_ICU_SIZE 0x100 -+ -+/* WDT */ -+#define LTQ_WDT_BASE_ADDR 0x1F8803F0 -+#define LTQ_WDT_SIZE 0x10 -+ -+/* Status */ -+#define LTQ_STATUS_BASE_ADDR (KSEG1 + 0x1E000500) -+#define LTQ_STATUS_CHIPID ((u32 *)(LTQ_STATUS_BASE_ADDR + 0x000C)) -+ -+#define LTQ_EIU_BASE_ADDR 0 -+ -+#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) -+#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) -+ -+extern __iomem void *ltq_ebu_membase; -+ -+extern void ltq_gpio_configure(int port, int pin, bool dirin, bool puen, -+ bool altsel0, bool altsel1); -+extern int ltq_port_get_dir(unsigned int port, unsigned int pin); -+extern int ltq_port_get_puden(unsigned int port, unsigned int pin); -+extern int ltq_port_get_altsel0(unsigned int port, unsigned int pin); -+extern int ltq_port_get_altsel1(unsigned int port, unsigned int pin); -+ -+#define ltq_is_ar9() 0 -+#define ltq_is_vr9() 0 -+#define ltq_is_falcon() 0 -+ -+#define BS_FLASH 0 -+#define LTQ_RST_CAUSE_WDTRST 0x2 -+ -+#endif /* CONFIG_SOC_SVIP */ -+#endif /* _LTQ_SVIP_H__ */ -Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h 2012-07-31 15:46:02.468476160 +0200 -@@ -0,0 +1,35 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. -+ * -+ * Copyright (C) 2010 Lantiq -+ */ -+#ifndef __SVIP_IRQ_H -+#define __SVIP_IRQ_H -+ -+#define IM_NUM 6 -+ -+#define INT_NUM_IRQ0 8 -+#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) -+#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32) -+#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32) -+#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32) -+#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32) -+#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32) -+#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0) -+ -+#define INT_NUM_IM5_IRL0 (INT_NUM_IRQ0 + 160) -+#define MIPS_CPU_TIMER_IRQ (INT_NUM_IM5_IRL0 + 2) -+ -+#endif -Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/base_reg.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/base_reg.h 2012-07-31 15:46:02.468476160 +0200 -@@ -0,0 +1,56 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2007 -+ Infineon Technologies AG -+ St. Martin Strasse 53; 81669 Munich, Germany -+ -+ Any use of this Software is subject to the conclusion of a respective -+ License Agreement. Without such a License Agreement no rights to the -+ Software are granted. -+ -+ ******************************************************************************/ -+ -+#ifndef __BASE_REG_H -+#define __BASE_REG_H -+ -+#ifndef KSEG1 -+#define KSEG1 0xA0000000 -+#endif -+ -+#define LTQ_EBU_SEG1_BASE (KSEG1 + 0x10000000) -+#define LTQ_EBU_SEG2_BASE (KSEG1 + 0x11000000) -+#define LTQ_EBU_SEG3_BASE (KSEG1 + 0x12000000) -+#define LTQ_EBU_SEG4_BASE (KSEG1 + 0x13000000) -+ -+#define LTQ_ASC0_BASE (KSEG1 + 0x14100100) -+#define LTQ_ASC1_BASE (KSEG1 + 0x14100200) -+ -+#define LTQ_SSC0_BASE (0x14100300) -+#define LTQ_SSC1_BASE (0x14100400) -+ -+#define LTQ_PORT_P0_BASE (KSEG1 + 0x14100600) -+#define LTQ_PORT_P1_BASE (KSEG1 + 0x14108100) -+#define LTQ_PORT_P2_BASE (KSEG1 + 0x14100800) -+#define LTQ_PORT_P3_BASE (KSEG1 + 0x14100900) -+#define LTQ_PORT_P4_BASE (KSEG1 + 0x1E000400) -+ -+#define LTQ_EBU_BASE (KSEG1 + 0x14102000) -+#define LTQ_DMA_BASE (KSEG1 + 0x14104000) -+ -+#define LTQ_ICU0_IM3_IM2_BASE (KSEG1 + 0x1E016000) -+#define LTQ_ICU0_IM5_IM4_IM1_IM0_BASE (KSEG1 + 0x14106000) -+ -+#define LTQ_ES_BASE (KSEG1 + 0x18000000) -+ -+#define LTQ_SYS0_BASE (KSEG1 + 0x1C000000) -+#define LTQ_SYS1_BASE (KSEG1 + 0x1C000800) -+#define LTQ_SYS2_BASE (KSEG1 + 0x1E400000) -+ -+#define LTQ_L2_SPRAM_BASE (KSEG1 + 0x1F1E8000) -+ -+#define LTQ_SWINT_BASE (KSEG1 + 0x1E000100) -+#define LTQ_MBS_BASE (KSEG1 + 0x1E000200) -+ -+#define LTQ_STATUS_BASE (KSEG1 + 0x1E000500) -+ -+#endif -Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/sys1_reg.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/sys1_reg.h 2012-07-31 15:46:02.468476160 +0200 -@@ -0,0 +1,370 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2007 -+ Infineon Technologies AG -+ St. Martin Strasse 53; 81669 Munich, Germany -+ -+ Any use of this Software is subject to the conclusion of a respective -+ License Agreement. Without such a License Agreement no rights to the -+ Software are granted. -+ -+ ******************************************************************************/ -+ -+#ifndef __SYS1_REG_H -+#define __SYS1_REG_H -+ -+#define sys1_r32(reg) ltq_r32(&sys1->reg) -+#define sys1_w32(val, reg) ltq_w32(val, &sys1->reg) -+#define sys1_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys1->reg) -+ -+/** SYS1 register structure */ -+struct svip_reg_sys1 { -+ unsigned long clksr; /* 0x0000 */ -+ unsigned long clkenr; /* 0x0004 */ -+ unsigned long clkclr; /* 0x0008 */ -+ unsigned long reserved0[1]; -+ unsigned long l2ccr; /* 0x0010 */ -+ unsigned long fpicr; /* 0x0014 */ -+ unsigned long wdtcr; /* 0x0018 */ -+ unsigned long reserved1[1]; -+ unsigned long cpucr[6]; /* 0x0020 */ -+ unsigned long reserved2[2]; -+ unsigned long rsr; /* 0x0040 */ -+ unsigned long rreqr; /* 0x0044 */ -+ unsigned long rrlsr; /* 0x0048 */ -+ unsigned long rbtr; /* 0x004c */ -+ unsigned long irncr; /* 0x0050 */ -+ unsigned long irnicr; /* 0x0054 */ -+ unsigned long irnen; /* 0x0058 */ -+ unsigned long reserved3[1]; -+ unsigned long cpursr[6]; /* 0x0060 */ -+ unsigned long reserved4[2]; -+ unsigned long cpusrssr[6]; /* 0x0080 */ -+ unsigned long reserved5[2]; -+ unsigned long cpuwrssr[6]; /* 0x00a0 */ -+}; -+ -+/******************************************************************************* -+ * SYS1 Clock Status Register -+ ******************************************************************************/ -+/* (r) Clock Enable for L2C */ -+#define SYS1_CLKSR_L2C (0x1 << 31) -+/* (r) Clock Enable for DDR2 */ -+#define SYS1_CLKSR_DDR2 (0x1 << 30) -+/* (r) Clock Enable for SMI2 */ -+#define SYS1_CLKSR_SMI2 (0x1 << 29) -+/* (r) Clock Enable for SMI1 */ -+#define SYS1_CLKSR_SMI1 (0x1 << 28) -+/* (r) Clock Enable for SMI0 */ -+#define SYS1_CLKSR_SMI0 (0x1 << 27) -+/* (r) Clock Enable for FMI0 */ -+#define SYS1_CLKSR_FMI0 (0x1 << 26) -+/* (r) Clock Enable for PORT0 */ -+#define SYS1_CLKSR_PORT0 (0x1 << 0) -+/* (r) Clock Enable for PCM3 */ -+#define SYS1_CLKSR_PCM3 (0x1 << 19) -+/* (r) Clock Enable for PCM2 */ -+#define SYS1_CLKSR_PCM2 (0x1 << 18) -+/* (r) Clock Enable for PCM1 */ -+#define SYS1_CLKSR_PCM1 (0x1 << 17) -+/* (r) Clock Enable for PCM0 */ -+#define SYS1_CLKSR_PCM0 (0x1 << 16) -+/* (r) Clock Enable for ASC1 */ -+#define SYS1_CLKSR_ASC1 (0x1 << 15) -+/* (r) Clock Enable for ASC0 */ -+#define SYS1_CLKSR_ASC0 (0x1 << 14) -+/* (r) Clock Enable for SSC2 */ -+#define SYS1_CLKSR_SSC2 (0x1 << 13) -+/* (r) Clock Enable for SSC1 */ -+#define SYS1_CLKSR_SSC1 (0x1 << 12) -+/* (r) Clock Enable for SSC0 */ -+#define SYS1_CLKSR_SSC0 (0x1 << 11) -+/* (r) Clock Enable for GPTC */ -+#define SYS1_CLKSR_GPTC (0x1 << 10) -+/* (r) Clock Enable for DMA */ -+#define SYS1_CLKSR_DMA (0x1 << 9) -+/* (r) Clock Enable for FSCT */ -+#define SYS1_CLKSR_FSCT (0x1 << 8) -+/* (r) Clock Enable for ETHSW */ -+#define SYS1_CLKSR_ETHSW (0x1 << 7) -+/* (r) Clock Enable for EBU */ -+#define SYS1_CLKSR_EBU (0x1 << 6) -+/* (r) Clock Enable for TRNG */ -+#define SYS1_CLKSR_TRNG (0x1 << 5) -+/* (r) Clock Enable for DEU */ -+#define SYS1_CLKSR_DEU (0x1 << 4) -+/* (r) Clock Enable for PORT3 */ -+#define SYS1_CLKSR_PORT3 (0x1 << 3) -+/* (r) Clock Enable for PORT2 */ -+#define SYS1_CLKSR_PORT2 (0x1 << 2) -+/* (r) Clock Enable for PORT1 */ -+#define SYS1_CLKSR_PORT1 (0x1 << 1) -+ -+/******************************************************************************* -+ * SYS1 Clock Enable Register -+ ******************************************************************************/ -+/* (w) Clock Enable Request for L2C */ -+#define SYS1_CLKENR_L2C (0x1 << 31) -+/* (w) Clock Enable Request for DDR2 */ -+#define SYS1_CLKENR_DDR2 (0x1 << 30) -+/* (w) Clock Enable Request for SMI2 */ -+#define SYS1_CLKENR_SMI2 (0x1 << 29) -+/* (w) Clock Enable Request for SMI1 */ -+#define SYS1_CLKENR_SMI1 (0x1 << 28) -+/* (w) Clock Enable Request for SMI0 */ -+#define SYS1_CLKENR_SMI0 (0x1 << 27) -+/* (w) Clock Enable Request for FMI0 */ -+#define SYS1_CLKENR_FMI0 (0x1 << 26) -+/* (w) Clock Enable Request for PORT0 */ -+#define SYS1_CLKENR_PORT0 (0x1 << 0) -+/* (w) Clock Enable Request for PCM3 */ -+#define SYS1_CLKENR_PCM3 (0x1 << 19) -+/* (w) Clock Enable Request for PCM2 */ -+#define SYS1_CLKENR_PCM2 (0x1 << 18) -+/* (w) Clock Enable Request for PCM1 */ -+#define SYS1_CLKENR_PCM1 (0x1 << 17) -+/* (w) Clock Enable Request for PCM0 */ -+#define SYS1_CLKENR_PCM0 (0x1 << 16) -+/* (w) Clock Enable Request for ASC1 */ -+#define SYS1_CLKENR_ASC1 (0x1 << 15) -+/* (w) Clock Enable Request for ASC0 */ -+#define SYS1_CLKENR_ASC0 (0x1 << 14) -+/* (w) Clock Enable Request for SSC2 */ -+#define SYS1_CLKENR_SSC2 (0x1 << 13) -+/* (w) Clock Enable Request for SSC1 */ -+#define SYS1_CLKENR_SSC1 (0x1 << 12) -+/* (w) Clock Enable Request for SSC0 */ -+#define SYS1_CLKENR_SSC0 (0x1 << 11) -+/* (w) Clock Enable Request for GPTC */ -+#define SYS1_CLKENR_GPTC (0x1 << 10) -+/* (w) Clock Enable Request for DMA */ -+#define SYS1_CLKENR_DMA (0x1 << 9) -+/* (w) Clock Enable Request for FSCT */ -+#define SYS1_CLKENR_FSCT (0x1 << 8) -+/* (w) Clock Enable Request for ETHSW */ -+#define SYS1_CLKENR_ETHSW (0x1 << 7) -+/* (w) Clock Enable Request for EBU */ -+#define SYS1_CLKENR_EBU (0x1 << 6) -+/* (w) Clock Enable Request for TRNG */ -+#define SYS1_CLKENR_TRNG (0x1 << 5) -+/* (w) Clock Enable Request for DEU */ -+#define SYS1_CLKENR_DEU (0x1 << 4) -+/* (w) Clock Enable Request for PORT3 */ -+#define SYS1_CLKENR_PORT3 (0x1 << 3) -+/* (w) Clock Enable Request for PORT2 */ -+#define SYS1_CLKENR_PORT2 (0x1 << 2) -+/* (w) Clock Enable Request for PORT1 */ -+#define SYS1_CLKENR_PORT1 (0x1 << 1) -+ -+/******************************************************************************* -+ * SYS1 Clock Clear Register -+ ******************************************************************************/ -+/* (w) Clock Disable Request for L2C */ -+#define SYS1_CLKCLR_L2C (0x1 << 31) -+/* (w) Clock Disable Request for DDR2 */ -+#define SYS1_CLKCLR_DDR2 (0x1 << 30) -+/* (w) Clock Disable Request for SMI2 */ -+#define SYS1_CLKCLR_SMI2 (0x1 << 29) -+/* (w) Clock Disable Request for SMI1 */ -+#define SYS1_CLKCLR_SMI1 (0x1 << 28) -+/* (w) Clock Disable Request for SMI0 */ -+#define SYS1_CLKCLR_SMI0 (0x1 << 27) -+/* (w) Clock Disable Request for FMI0 */ -+#define SYS1_CLKCLR_FMI0 (0x1 << 26) -+/* (w) Clock Disable Request for PORT0 */ -+#define SYS1_CLKCLR_PORT0 (0x1 << 0) -+/* (w) Clock Disable Request for PCM3 */ -+#define SYS1_CLKCLR_PCM3 (0x1 << 19) -+/* (w) Clock Disable Request for PCM2 */ -+#define SYS1_CLKCLR_PCM2 (0x1 << 18) -+/* (w) Clock Disable Request for PCM1 */ -+#define SYS1_CLKCLR_PCM1 (0x1 << 17) -+/* (w) Clock Disable Request for PCM0 */ -+#define SYS1_CLKCLR_PCM0 (0x1 << 16) -+/* (w) Clock Disable Request for ASC1 */ -+#define SYS1_CLKCLR_ASC1 (0x1 << 15) -+/* (w) Clock Disable Request for ASC0 */ -+#define SYS1_CLKCLR_ASC0 (0x1 << 14) -+/* (w) Clock Disable Request for SSC2 */ -+#define SYS1_CLKCLR_SSC2 (0x1 << 13) -+/* (w) Clock Disable Request for SSC1 */ -+#define SYS1_CLKCLR_SSC1 (0x1 << 12) -+/* (w) Clock Disable Request for SSC0 */ -+#define SYS1_CLKCLR_SSC0 (0x1 << 11) -+/* (w) Clock Disable Request for GPTC */ -+#define SYS1_CLKCLR_GPTC (0x1 << 10) -+/* (w) Clock Disable Request for DMA */ -+#define SYS1_CLKCLR_DMA (0x1 << 9) -+/* (w) Clock Disable Request for FSCT */ -+#define SYS1_CLKCLR_FSCT (0x1 << 8) -+/* (w) Clock Disable Request for ETHSW */ -+#define SYS1_CLKCLR_ETHSW (0x1 << 7) -+/* (w) Clock Disable Request for EBU */ -+#define SYS1_CLKCLR_EBU (0x1 << 6) -+/* (w) Clock Disable Request for TRNG */ -+#define SYS1_CLKCLR_TRNG (0x1 << 5) -+/* (w) Clock Disable Request for DEU */ -+#define SYS1_CLKCLR_DEU (0x1 << 4) -+/* (w) Clock Disable Request for PORT3 */ -+#define SYS1_CLKCLR_PORT3 (0x1 << 3) -+/* (w) Clock Disable Request for PORT2 */ -+#define SYS1_CLKCLR_PORT2 (0x1 << 2) -+/* (w) Clock Disable Request for PORT1 */ -+#define SYS1_CLKCLR_PORT1 (0x1 << 1) -+ -+/******************************************************************************* -+ * SYS1 FPI Control Register -+ ******************************************************************************/ -+ -+/* FPI Bus Clock divider (0) */ -+#define SYS1_FPICR_FPIDIV (0x1) -+#define SYS1_FPICR_FPIDIV_VAL(val) (((val) & 0x1) << 0) -+#define SYS1_FPICR_FPIDIV_GET(val) ((((val) & SYS1_FPICR_FPIDIV) >> 0) & 0x1) -+#define SYS1_FPICR_FPIDIV_SET(reg,val) (reg) = ((reg & ~SYS1_FPICR_FPIDIV) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * SYS1 Clock Control Register for CPUn -+ ******************************************************************************/ -+ -+/* Enable bit for clock of CPUn (1) */ -+#define SYS1_CPUCR_CPUCLKEN (0x1 << 1) -+#define SYS1_CPUCR_CPUCLKEN_VAL(val) (((val) & 0x1) << 1) -+#define SYS1_CPUCR_CPUCLKEN_GET(val) ((((val) & SYS1_CPUCR_CPUCLKEN) >> 1) & 0x1) -+#define SYS1_CPUCR_CPUCLKEN_SET(reg,val) (reg) = ((reg & ~SYS1_CPUCR_CPUCLKEN) | (((val) & 0x1) << 1)) -+/* Divider factor for clock of CPUn (0) */ -+#define SYS1_CPUCR_CPUDIV (0x1) -+#define SYS1_CPUCR_CPUDIV_VAL(val) (((val) & 0x1) << 0) -+#define SYS1_CPUCR_CPUDIV_GET(val) ((((val) & SYS1_CPUCR_CPUDIV) >> 0) & 0x1) -+#define SYS1_CPUCR_CPUDIV_SET(reg,val) (reg) = ((reg & ~SYS1_CPUCR_CPUDIV) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * SYS1 Reset Request Register -+ ******************************************************************************/ -+ -+/* HRSTOUT Reset Request (18) */ -+#define SYS1_RREQ_HRSTOUT (0x1 << 18) -+#define SYS1_RREQ_HRSTOUT_VAL(val) (((val) & 0x1) << 18) -+#define SYS1_RREQ_HRSTOUT_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_HRSTOUT) | (((val) & 1) << 18)) -+ /* FBS0 Reset Request (17) */ -+#define SYS1_RREQ_FBS0 (0x1 << 17) -+#define SYS1_RREQ_FBS0_VAL(val) (((val) & 0x1) << 17) -+#define SYS1_RREQ_FBS0_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_FBS0) | (((val) & 1) << 17)) -+ /* SUBSYS Reset Request (16) */ -+#define SYS1_RREQ_SUBSYS (0x1 << 16) -+#define SYS1_RREQ_SUBSYS_VAL(val) (((val) & 0x1) << 16) -+#define SYS1_RREQ_SUBSYS_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_SUBSYS) | (((val) & 1) << 16)) -+ /* Watchdog5 Reset Request (13) */ -+#define SYS1_RREQ_WDT5 (0x1 << 13) -+#define SYS1_RREQ_WDT5_VAL(val) (((val) & 0x1) << 13) -+#define SYS1_RREQ_WDT5_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT5) | (((val) & 1) << 13)) -+ /* Watchdog4 Reset Request (12) */ -+#define SYS1_RREQ_WDT4 (0x1 << 12) -+#define SYS1_RREQ_WDT4_VAL(val) (((val) & 0x1) << 12) -+#define SYS1_RREQ_WDT4_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT4) | (((val) & 1) << 12)) -+ /* Watchdog3 Reset Request (11) */ -+#define SYS1_RREQ_WDT3 (0x1 << 11) -+#define SYS1_RREQ_WDT3_VAL(val) (((val) & 0x1) << 11) -+#define SYS1_RREQ_WDT3_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT3) | (((val) & 1) << 11)) -+ /* Watchdog2 Reset Request (10) */ -+#define SYS1_RREQ_WDT2 (0x1 << 10) -+#define SYS1_RREQ_WDT2_VAL(val) (((val) & 0x1) << 10) -+#define SYS1_RREQ_WDT2_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT2) | (((val) & 1) << 10)) -+ /* Watchdog1 Reset Request (9) */ -+#define SYS1_RREQ_WDT1 (0x1 << 9) -+#define SYS1_RREQ_WDT1_VAL(val) (((val) & 0x1) << 9) -+#define SYS1_RREQ_WDT1_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT1) | (((val) & 1) << 9)) -+ /* Watchdog0 Reset Request (8) */ -+#define SYS1_RREQ_WDT0 (0x1 << 8) -+#define SYS1_RREQ_WDT0_VAL(val) (((val) & 0x1) << 8) -+#define SYS1_RREQ_WDT0_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT0) | (((val) & 1) << 8)) -+ /* CPU5 Reset Request (5) */ -+#define SYS1_RREQ_CPU5 (0x1 << 5) -+#define SYS1_RREQ_CPU5_VAL(val) (((val) & 0x1) << 5) -+#define SYS1_RREQ_CPU5_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU5) | (((val) & 1) << 5)) -+ /* CPU4 Reset Request (4) */ -+#define SYS1_RREQ_CPU4 (0x1 << 4) -+#define SYS1_RREQ_CPU4_VAL(val) (((val) & 0x1) << 4) -+#define SYS1_RREQ_CPU4_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU4) | (((val) & 1) << 4)) -+ /* CPU3 Reset Request (3) */ -+#define SYS1_RREQ_CPU3 (0x1 << 3) -+#define SYS1_RREQ_CPU3_VAL(val) (((val) & 0x1) << 3) -+#define SYS1_RREQ_CPU3_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU3) | (((val) & 1) << 3)) -+ /* CPU2 Reset Request (2) */ -+#define SYS1_RREQ_CPU2 (0x1 << 2) -+#define SYS1_RREQ_CPU2_VAL(val) (((val) & 0x1) << 2) -+#define SYS1_RREQ_CPU2_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU2) | (((val) & 1) << 2)) -+ /* CPU1 Reset Request (1) */ -+#define SYS1_RREQ_CPU1 (0x1 << 1) -+#define SYS1_RREQ_CPU1_VAL(val) (((val) & 0x1) << 1) -+#define SYS1_RREQ_CPU1_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU1) | (((val) & 1) << 1)) -+/* CPU0 Reset Request (0) */ -+#define SYS1_RREQ_CPU0 (0x1) -+#define SYS1_RREQ_CPU0_VAL(val) (((val) & 0x1) << 0) -+#define SYS1_RREQ_CPU0_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU0) | (((val) & 1) << 0)) -+ -+/******************************************************************************* -+ * SYS1 Reset Release Register -+ ******************************************************************************/ -+ -+/* HRSTOUT Reset Release (18) */ -+#define SYS1_RRLSR_HRSTOUT (0x1 << 18) -+#define SYS1_RRLSR_HRSTOUT_VAL(val) (((val) & 0x1) << 18) -+#define SYS1_RRLSR_HRSTOUT_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_HRSTOUT) | (((val) & 1) << 18)) -+/* FBS0 Reset Release (17) */ -+#define SYS1_RRLSR_FBS0 (0x1 << 17) -+#define SYS1_RRLSR_FBS0_VAL(val) (((val) & 0x1) << 17) -+#define SYS1_RRLSR_FBS0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_FBS0) | (((val) & 1) << 17)) -+/* SUBSYS Reset Release (16) */ -+#define SYS1_RRLSR_SUBSYS (0x1 << 16) -+#define SYS1_RRLSR_SUBSYS_VAL(val) (((val) & 0x1) << 16) -+#define SYS1_RRLSR_SUBSYS_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_SUBSYS) | (((val) & 1) << 16)) -+/* Watchdog5 Reset Release (13) */ -+#define SYS1_RRLSR_WDT5 (0x1 << 13) -+#define SYS1_RRLSR_WDT5_VAL(val) (((val) & 0x1) << 13) -+#define SYS1_RRLSR_WDT5_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT5) | (((val) & 1) << 13)) -+/* Watchdog4 Reset Release (12) */ -+#define SYS1_RRLSR_WDT4 (0x1 << 12) -+#define SYS1_RRLSR_WDT4_VAL(val) (((val) & 0x1) << 12) -+#define SYS1_RRLSR_WDT4_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT4) | (((val) & 1) << 12)) -+/* Watchdog3 Reset Release (11) */ -+#define SYS1_RRLSR_WDT3 (0x1 << 11) -+#define SYS1_RRLSR_WDT3_VAL(val) (((val) & 0x1) << 11) -+#define SYS1_RRLSR_WDT3_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT3) | (((val) & 1) << 11)) -+/* Watchdog2 Reset Release (10) */ -+#define SYS1_RRLSR_WDT2 (0x1 << 10) -+#define SYS1_RRLSR_WDT2_VAL(val) (((val) & 0x1) << 10) -+#define SYS1_RRLSR_WDT2_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT2) | (((val) & 1) << 10)) -+/* Watchdog1 Reset Release (9) */ -+#define SYS1_RRLSR_WDT1 (0x1 << 9) -+#define SYS1_RRLSR_WDT1_VAL(val) (((val) & 0x1) << 9) -+#define SYS1_RRLSR_WDT1_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT1) | (((val) & 1) << 9)) -+/* Watchdog0 Reset Release (8) */ -+#define SYS1_RRLSR_WDT0 (0x1 << 8) -+#define SYS1_RRLSR_WDT0_VAL(val) (((val) & 0x1) << 8) -+#define SYS1_RRLSR_WDT0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT0) | (((val) & 1) << 8)) -+/* CPU5 Reset Release (5) */ -+#define SYS1_RRLSR_CPU5 (0x1 << 5) -+#define SYS1_RRLSR_CPU5_VAL(val) (((val) & 0x1) << 5) -+#define SYS1_RRLSR_CPU5_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU5) | (((val) & 1) << 5)) -+/* CPU4 Reset Release (4) */ -+#define SYS1_RRLSR_CPU4 (0x1 << 4) -+#define SYS1_RRLSR_CPU4_VAL(val) (((val) & 0x1) << 4) -+#define SYS1_RRLSR_CPU4_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU4) | (((val) & 1) << 4)) -+/* CPU3 Reset Release (3) */ -+#define SYS1_RRLSR_CPU3 (0x1 << 3) -+#define SYS1_RRLSR_CPU3_VAL(val) (((val) & 0x1) << 3) -+#define SYS1_RRLSR_CPU3_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU3) | (((val) & 1) << 3)) -+/* CPU2 Reset Release (2) */ -+#define SYS1_RRLSR_CPU2 (0x1 << 2) -+#define SYS1_RRLSR_CPU2_VAL(val) (((val) & 0x1) << 2) -+#define SYS1_RRLSR_CPU2_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU2) | (((val) & 1) << 2)) -+/* CPU1 Reset Release (1) */ -+#define SYS1_RRLSR_CPU1 (0x1 << 1) -+#define SYS1_RRLSR_CPU1_VAL(val) (((val) & 0x1) << 1) -+#define SYS1_RRLSR_CPU1_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU1) | (((val) & 1) << 1)) -+/* CPU0 Reset Release (0) */ -+#define SYS1_RRLSR_CPU0 (0x1) -+#define SYS1_RRLSR_CPU0_VAL(val) (((val) & 0x1) << 0) -+#define SYS1_RRLSR_CPU0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU0) | (((val) & 1) << 0)) -+ -+#endif -Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/es_reg.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/es_reg.h 2012-07-31 15:46:02.476476158 +0200 -@@ -0,0 +1,2098 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2007 -+ Infineon Technologies AG -+ St. Martin Strasse 53; 81669 Munich, Germany -+ -+ Any use of this Software is subject to the conclusion of a respective -+ License Agreement. Without such a License Agreement no rights to the -+ Software are granted. -+ -+ ******************************************************************************/ -+ -+#ifndef __ES_REG_H -+#define __ES_REG_H -+ -+#define es_r32(reg) ltq_r32(&es->reg) -+#define es_w32(val, reg) ltq_w32(val, &es->reg) -+#define es_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &es->reg) -+ -+/** ES register structure */ -+struct svip_reg_es { -+ volatile unsigned long ps; /* 0x0000 */ -+ volatile unsigned long p0_ctl; /* 0x0004 */ -+ volatile unsigned long p1_ctl; /* 0x0008 */ -+ volatile unsigned long p2_ctl; /* 0x000C */ -+ volatile unsigned long p0_vlan; /* 0x0010 */ -+ volatile unsigned long p1_vlan; /* 0x0014 */ -+ volatile unsigned long p2_vlan; /* 0x0018 */ -+ volatile unsigned long reserved1[1]; /* 0x001C */ -+ volatile unsigned long p0_inctl; /* 0x0020 */ -+ volatile unsigned long p1_inctl; /* 0x0024 */ -+ volatile unsigned long p2_inctl; /* 0x0028 */ -+ volatile unsigned long reserved2[1]; /* 0x002C */ -+ volatile unsigned long p0_ecs_q32; /* 0x0030 */ -+ volatile unsigned long p0_ecs_q10; /* 0x0034 */ -+ volatile unsigned long p0_ecw_q32; /* 0x0038 */ -+ volatile unsigned long p0_ecw_q10; /* 0x003C */ -+ volatile unsigned long p1_ecs_q32; /* 0x0040 */ -+ volatile unsigned long p1_ecs_q10; /* 0x0044 */ -+ volatile unsigned long p1_ecw_q32; /* 0x0048 */ -+ volatile unsigned long p1_ecw_q10; /* 0x004C */ -+ volatile unsigned long p2_ecs_q32; /* 0x0050 */ -+ volatile unsigned long p2_ecs_q10; /* 0x0054 */ -+ volatile unsigned long p2_ecw_q32; /* 0x0058 */ -+ volatile unsigned long p2_ecw_q10; /* 0x005C */ -+ volatile unsigned long int_ena; /* 0x0060 */ -+ volatile unsigned long int_st; /* 0x0064 */ -+ volatile unsigned long sw_gctl0; /* 0x0068 */ -+ volatile unsigned long sw_gctl1; /* 0x006C */ -+ volatile unsigned long arp; /* 0x0070 */ -+ volatile unsigned long strm_ctl; /* 0x0074 */ -+ volatile unsigned long rgmii_ctl; /* 0x0078 */ -+ volatile unsigned long prt_1p; /* 0x007C */ -+ volatile unsigned long gbkt_szbs; /* 0x0080 */ -+ volatile unsigned long gbkt_szebs; /* 0x0084 */ -+ volatile unsigned long bf_th; /* 0x0088 */ -+ volatile unsigned long pmac_hd_ctl; /* 0x008C */ -+ volatile unsigned long pmac_sa1; /* 0x0090 */ -+ volatile unsigned long pmac_sa2; /* 0x0094 */ -+ volatile unsigned long pmac_da1; /* 0x0098 */ -+ volatile unsigned long pmac_da2; /* 0x009C */ -+ volatile unsigned long pmac_vlan; /* 0x00A0 */ -+ volatile unsigned long pmac_tx_ipg; /* 0x00A4 */ -+ volatile unsigned long pmac_rx_ipg; /* 0x00A8 */ -+ volatile unsigned long adr_tb_ctl0; /* 0x00AC */ -+ volatile unsigned long adr_tb_ctl1; /* 0x00B0 */ -+ volatile unsigned long adr_tb_ctl2; /* 0x00B4 */ -+ volatile unsigned long adr_tb_st0; /* 0x00B8 */ -+ volatile unsigned long adr_tb_st1; /* 0x00BC */ -+ volatile unsigned long adr_tb_st2; /* 0x00C0 */ -+ volatile unsigned long rmon_ctl; /* 0x00C4 */ -+ volatile unsigned long rmon_st; /* 0x00C8 */ -+ volatile unsigned long mdio_ctl; /* 0x00CC */ -+ volatile unsigned long mdio_data; /* 0x00D0 */ -+ volatile unsigned long tp_flt_act; /* 0x00D4 */ -+ volatile unsigned long prtcl_flt_act; /* 0x00D8 */ -+ volatile unsigned long reserved4[9]; /* 0xdc */ -+ volatile unsigned long vlan_flt0; /* 0x0100 */ -+ volatile unsigned long vlan_flt1; /* 0x0104 */ -+ volatile unsigned long vlan_flt2; /* 0x0108 */ -+ volatile unsigned long vlan_flt3; /* 0x010C */ -+ volatile unsigned long vlan_flt4; /* 0x0110 */ -+ volatile unsigned long vlan_flt5; /* 0x0114 */ -+ volatile unsigned long vlan_flt6; /* 0x0118 */ -+ volatile unsigned long vlan_flt7; /* 0x011C */ -+ volatile unsigned long vlan_flt8; /* 0x0120 */ -+ volatile unsigned long vlan_flt9; /* 0x0124 */ -+ volatile unsigned long vlan_flt10; /* 0x0128 */ -+ volatile unsigned long vlan_flt11; /* 0x012C */ -+ volatile unsigned long vlan_flt12; /* 0x0130 */ -+ volatile unsigned long vlan_flt13; /* 0x0134 */ -+ volatile unsigned long vlan_flt14; /* 0x0138 */ -+ volatile unsigned long vlan_flt15; /* 0x013C */ -+ volatile unsigned long tp_flt10; /* 0x0140 */ -+ volatile unsigned long tp_flt32; /* 0x0144 */ -+ volatile unsigned long tp_flt54; /* 0x0148 */ -+ volatile unsigned long tp_flt76; /* 0x014C */ -+ volatile unsigned long dfsrv_map0; /* 0x0150 */ -+ volatile unsigned long dfsrv_map1; /* 0x0154 */ -+ volatile unsigned long dfsrv_map2; /* 0x0158 */ -+ volatile unsigned long dfsrv_map3; /* 0x015C */ -+ volatile unsigned long tcp_pf0; /* 0x0160 */ -+ volatile unsigned long tcp_pf1; /* 0x0164 */ -+ volatile unsigned long tcp_pf2; /* 0x0168 */ -+ volatile unsigned long tcp_pf3; /* 0x016C */ -+ volatile unsigned long tcp_pf4; /* 0x0170 */ -+ volatile unsigned long tcp_pf5; /* 0x0174 */ -+ volatile unsigned long tcp_pf6; /* 0x0178 */ -+ volatile unsigned long tcp_pf7; /* 0x017C */ -+ volatile unsigned long ra_03_00; /* 0x0180 */ -+ volatile unsigned long ra_07_04; /* 0x0184 */ -+ volatile unsigned long ra_0b_08; /* 0x0188 */ -+ volatile unsigned long ra_0f_0c; /* 0x018C */ -+ volatile unsigned long ra_13_10; /* 0x0190 */ -+ volatile unsigned long ra_17_14; /* 0x0194 */ -+ volatile unsigned long ra_1b_18; /* 0x0198 */ -+ volatile unsigned long ra_1f_1c; /* 0x019C */ -+ volatile unsigned long ra_23_20; /* 0x01A0 */ -+ volatile unsigned long ra_27_24; /* 0x01A4 */ -+ volatile unsigned long ra_2b_28; /* 0x01A8 */ -+ volatile unsigned long ra_2f_2c; /* 0x01AC */ -+ volatile unsigned long prtcl_f0; /* 0x01B0 */ -+ volatile unsigned long prtcl_f1; /* 0x01B4 */ -+}; -+ -+/******************************************************************************* -+ * ES -+ ******************************************************************************/ -+#define LTQ_ES_PS_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0000)) -+#define LTQ_ES_P0_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0004)) -+#define LTQ_ES_P1_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0008)) -+#define LTQ_ES_P2_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x000C)) -+#define LTQ_ES_P0_VLAN_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0010)) -+#define LTQ_ES_P1_VLAN_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0014)) -+#define LTQ_ES_P2_VLAN_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0010)) -+#define LTQ_ES_P0_INCTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0020)) -+#define LTQ_ES_P1_INCTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0024)) -+#define LTQ_ES_P2_INCTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0028)) -+#define LTQ_ES_P0_ECS_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0030)) -+#define LTQ_ES_P0_ECS_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0034)) -+#define LTQ_ES_P0_ECW_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0038)) -+#define LTQ_ES_P0_ECW_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x003C)) -+#define LTQ_ES_P1_ECS_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0030)) -+#define LTQ_ES_P1_ECS_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0034)) -+#define LTQ_ES_P1_ECW_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0038)) -+#define LTQ_ES_P1_ECW_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x003C)) -+#define LTQ_ES_P2_ECS_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0030)) -+#define LTQ_ES_P2_ECS_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0034)) -+#define LTQ_ES_P2_ECW_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0038)) -+#define LTQ_ES_P2_ECW_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x003C)) -+#define LTQ_ES_INT_ENA_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0060)) -+#define LTQ_ES_INT_ST_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0064)) -+#define LTQ_ES_SW_GCTL0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0068)) -+#define LTQ_ES_SW_GCTL1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x006C)) -+#define LTQ_ES_ARP_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0070)) -+#define LTQ_ES_STRM_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0074)) -+#define LTQ_ES_RGMII_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0078)) -+#define LTQ_ES_PRT_1P_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x007C)) -+#define LTQ_ES_GBKT_SZBS_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0080)) -+#define LTQ_ES_GBKT_SZEBS_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0084)) -+#define LTQ_ES_BF_TH_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0088)) -+#define LTQ_ES_PMAC_HD_CTL ((volatile unsigned int*)(LTQ_ES_BASE + 0x008C)) -+#define LTQ_ES_PMAC_SA1 ((volatile unsigned int*)(LTQ_ES_BASE + 0x0090)) -+#define LTQ_ES_PMAC_SA2 ((volatile unsigned int*)(LTQ_ES_BASE + 0x0094)) -+#define LTQ_ES_PMAC_DA1 ((volatile unsigned int*)(LTQ_ES_BASE + 0x0098)) -+#define LTQ_ES_PMAC_DA2 ((volatile unsigned int*)(LTQ_ES_BASE + 0x009C)) -+#define LTQ_ES_PMAC_VLAN ((volatile unsigned int*)(LTQ_ES_BASE + 0x00A0)) -+#define LTQ_ES_PMAC_TX_IPG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00A4)) -+#define LTQ_ES_PMAC_RX_IPG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00A8)) -+#define LTQ_ES_ADR_TB_CTL0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00AC)) -+#define LTQ_ES_ADR_TB_CTL1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00B0)) -+#define LTQ_ES_ADR_TB_CTL2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00B4)) -+#define LTQ_ES_ADR_TB_ST0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00B8)) -+#define LTQ_ES_ADR_TB_ST1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00BC)) -+#define LTQ_ES_ADR_TB_ST2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00C0)) -+#define LTQ_ES_RMON_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00C4)) -+#define LTQ_ES_RMON_ST_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00C8)) -+#define LTQ_ES_MDIO_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00CC)) -+#define LTQ_ES_MDIO_DATA_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00D0)) -+#define LTQ_ES_TP_FLT_ACT_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00D4)) -+#define LTQ_ES_PRTCL_FLT_ACT_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00D8)) -+#define LTQ_ES_VLAN_FLT0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0100)) -+#define LTQ_ES_VLAN_FLT1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0104)) -+#define LTQ_ES_VLAN_FLT2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0108)) -+#define LTQ_ES_VLAN_FLT3_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x010C)) -+#define LTQ_ES_VLAN_FLT4_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0110)) -+#define LTQ_ES_VLAN_FLT5_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0114)) -+#define LTQ_ES_VLAN_FLT6_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0118)) -+#define LTQ_ES_VLAN_FLT7_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x011C)) -+#define LTQ_ES_VLAN_FLT8_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0120)) -+#define LTQ_ES_VLAN_FLT9_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0124)) -+#define LTQ_ES_VLAN_FLT10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0128)) -+#define LTQ_ES_VLAN_FLT11_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x012C)) -+#define LTQ_ES_VLAN_FLT12_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0130)) -+#define LTQ_ES_VLAN_FLT13_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0134)) -+#define LTQ_ES_VLAN_FLT14_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0138)) -+#define LTQ_ES_VLAN_FLT15_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x013C)) -+#define LTQ_ES_TP_FLT10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0140)) -+#define LTQ_ES_TP_FLT32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0144)) -+#define LTQ_ES_TP_FLT54_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0148)) -+#define LTQ_ES_TP_FLT76_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x014C)) -+#define LTQ_ES_DFSRV_MAP0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0150)) -+#define LTQ_ES_DFSRV_MAP1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0154)) -+#define LTQ_ES_DFSRV_MAP2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0158)) -+#define LTQ_ES_DFSRV_MAP3_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x015C)) -+#define LTQ_ES_TCP_PF0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0160)) -+#define LTQ_ES_TCP_PF1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0164)) -+#define LTQ_ES_TCP_PF2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0168)) -+#define LTQ_ES_TCP_PF3_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x016C)) -+#define LTQ_ES_TCP_PF4_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0170)) -+#define LTQ_ES_TCP_PF5_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0174)) -+#define LTQ_ES_TCP_PF6_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0178)) -+#define LTQ_ES_TCP_PF7_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x017C)) -+#define LTQ_ES_RA_03_00_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0180)) -+#define LTQ_ES_RA_07_04_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0184)) -+#define LTQ_ES_RA_0B_08_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0188)) -+#define LTQ_ES_RA_0F_0C_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x018C)) -+#define LTQ_ES_RA_13_10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0190)) -+#define LTQ_ES_RA_17_14_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0194)) -+#define LTQ_ES_RA_1B_18_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0198)) -+#define LTQ_ES_RA_1F_1C_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x019C)) -+#define LTQ_ES_RA_23_20_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01A0)) -+#define LTQ_ES_RA_27_24_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01A4)) -+#define LTQ_ES_RA_2B_28_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01A8)) -+#define LTQ_ES_RA_2F_2C_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01AC)) -+#define LTQ_ES_PRTCL_F0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01B0)) -+#define LTQ_ES_PRTCL_F1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01B4)) -+ -+/******************************************************************************* -+ * Port Status Register -+ ******************************************************************************/ -+ -+/* Port 1 Flow Control Status (12) */ -+#define LTQ_ES_PS_REG_P1FCS (0x1 << 12) -+#define LTQ_ES_PS_REG_P1FCS_GET(val) ((((val) & LTQ_ES_PS_REG_P1FCS) >> 12) & 0x1) -+/* Port 1 Duplex Status (11) */ -+#define LTQ_ES_PS_REG_P1DS (0x1 << 11) -+#define LTQ_ES_PS_REG_P1DS_GET(val) ((((val) & LTQ_ES_PS_REG_P1DS) >> 11) & 0x1) -+/* Port 1 Speed High Status (10) */ -+#define LTQ_ES_PS_REG_P1SHS (0x1 << 10) -+#define LTQ_ES_PS_REG_P1SHS_GET(val) ((((val) & LTQ_ES_PS_REG_P1SHS) >> 10) & 0x1) -+/* Port 1 Speed Status (9) */ -+#define LTQ_ES_PS_REG_P1SS (0x1 << 9) -+#define LTQ_ES_PS_REG_P1SS_GET(val) ((((val) & LTQ_ES_PS_REG_P1SS) >> 9) & 0x1) -+/* Port 1 Link Status (8) */ -+#define LTQ_ES_PS_REG_P1LS (0x1 << 8) -+#define LTQ_ES_PS_REG_P1LS_GET(val) ((((val) & LTQ_ES_PS_REG_P1LS) >> 8) & 0x1) -+/* Port 0 Flow Control Status (4) */ -+#define LTQ_ES_PS_REG_P0FCS (0x1 << 4) -+#define LTQ_ES_PS_REG_P0FCS_GET(val) ((((val) & LTQ_ES_PS_REG_P0FCS) >> 4) & 0x1) -+/* Port 0 Duplex Status (3) */ -+#define LTQ_ES_PS_REG_P0DS (0x1 << 3) -+#define LTQ_ES_PS_REG_P0DS_GET(val) ((((val) & LTQ_ES_PS_REG_P0DS) >> 3) & 0x1) -+/* Port 0 Speed High Status (2) */ -+#define LTQ_ES_PS_REG_P0SHS (0x1 << 2) -+#define LTQ_ES_PS_REG_P0SHS_GET(val) ((((val) & LTQ_ES_PS_REG_P0SHS) >> 2) & 0x1) -+/* Port 0 Speed Status (1) */ -+#define LTQ_ES_PS_REG_P0SS (0x1 << 1) -+#define LTQ_ES_PS_REG_P0SS_GET(val) ((((val) & LTQ_ES_PS_REG_P0SS) >> 1) & 0x1) -+/* Port 0 Link Status (0) */ -+#define LTQ_ES_PS_REG_P0LS (0x1) -+#define LTQ_ES_PS_REG_P0LS_GET(val) ((((val) & LTQ_ES_PS_REG_P0LS) >> 0) & 0x1) -+ -+/******************************************************************************* -+ * P0 Control Register -+ ******************************************************************************/ -+ -+/* STP/RSTP port state (31:30) */ -+#define LTQ_ES_P0_CTL_REG_SPS (0x3 << 30) -+#define LTQ_ES_P0_CTL_REG_SPS_VAL(val) (((val) & 0x3) << 30) -+#define LTQ_ES_P0_CTL_REG_SPS_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_SPS) >> 30) & 0x3) -+#define LTQ_ES_P0_CTL_REG_SPS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_SPS) | (((val) & 0x3) << 30)) -+/* TCP/UDP PRIEN (29) */ -+#define LTQ_ES_P0_CTL_REG_TCPE (0x1 << 29) -+#define LTQ_ES_P0_CTL_REG_TCPE_VAL(val) (((val) & 0x1) << 29) -+#define LTQ_ES_P0_CTL_REG_TCPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_TCPE) >> 29) & 0x1) -+#define LTQ_ES_P0_CTL_REG_TCPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_TCPE) | (((val) & 0x1) << 29)) -+/* IP over TCP/UDP (28) */ -+#define LTQ_ES_P0_CTL_REG_IPOVTU (0x1 << 28) -+#define LTQ_ES_P0_CTL_REG_IPOVTU_VAL(val) (((val) & 0x1) << 28) -+#define LTQ_ES_P0_CTL_REG_IPOVTU_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_IPOVTU) >> 28) & 0x1) -+#define LTQ_ES_P0_CTL_REG_IPOVTU_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_IPOVTU) | (((val) & 0x1) << 28)) -+/* VLAN Priority Enable (27) */ -+#define LTQ_ES_P0_CTL_REG_VPE (0x1 << 27) -+#define LTQ_ES_P0_CTL_REG_VPE_VAL(val) (((val) & 0x1) << 27) -+#define LTQ_ES_P0_CTL_REG_VPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_VPE) >> 27) & 0x1) -+#define LTQ_ES_P0_CTL_REG_VPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_VPE) | (((val) & 0x1) << 27)) -+/* Service Priority Enable (26) */ -+#define LTQ_ES_P0_CTL_REG_SPE (0x1 << 26) -+#define LTQ_ES_P0_CTL_REG_SPE_VAL(val) (((val) & 0x1) << 26) -+#define LTQ_ES_P0_CTL_REG_SPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_SPE) >> 26) & 0x1) -+#define LTQ_ES_P0_CTL_REG_SPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_SPE) | (((val) & 0x1) << 26)) -+/* IP over VLAN PRI (25) */ -+#define LTQ_ES_P0_CTL_REG_IPVLAN (0x1 << 25) -+#define LTQ_ES_P0_CTL_REG_IPVLAN_VAL(val) (((val) & 0x1) << 25) -+#define LTQ_ES_P0_CTL_REG_IPVLAN_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_IPVLAN) >> 25) & 0x1) -+#define LTQ_ES_P0_CTL_REG_IPVLAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_IPVLAN) | (((val) & 0x1) << 25)) -+/* Ether Type Priority Enable (24) */ -+#define LTQ_ES_P0_CTL_REG_TPE (0x1 << 24) -+#define LTQ_ES_P0_CTL_REG_TPE_VAL(val) (((val) & 0x1) << 24) -+#define LTQ_ES_P0_CTL_REG_TPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_TPE) >> 24) & 0x1) -+#define LTQ_ES_P0_CTL_REG_TPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_TPE) | (((val) & 0x1) << 24)) -+/* Force Link Up (18) */ -+#define LTQ_ES_P0_CTL_REG_FLP (0x1 << 18) -+#define LTQ_ES_P0_CTL_REG_FLP_VAL(val) (((val) & 0x1) << 18) -+#define LTQ_ES_P0_CTL_REG_FLP_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_FLP) >> 18) & 0x1) -+#define LTQ_ES_P0_CTL_REG_FLP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_FLP) | (((val) & 0x1) << 18)) -+/* Force Link Down (17) */ -+#define LTQ_ES_P0_CTL_REG_FLD (0x1 << 17) -+#define LTQ_ES_P0_CTL_REG_FLD_VAL(val) (((val) & 0x1) << 17) -+#define LTQ_ES_P0_CTL_REG_FLD_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_FLD) >> 17) & 0x1) -+#define LTQ_ES_P0_CTL_REG_FLD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_FLD) | (((val) & 0x1) << 17)) -+/* Ratio Mode for WFQ (16) */ -+#define LTQ_ES_P0_CTL_REG_RMWFQ (0x1 << 16) -+#define LTQ_ES_P0_CTL_REG_RMWFQ_VAL(val) (((val) & 0x1) << 16) -+#define LTQ_ES_P0_CTL_REG_RMWFQ_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_RMWFQ) >> 16) & 0x1) -+#define LTQ_ES_P0_CTL_REG_RMWFQ_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_RMWFQ) | (((val) & 0x1) << 16)) -+/* Aging Disable (15) */ -+#define LTQ_ES_P0_CTL_REG_AD (0x1 << 15) -+#define LTQ_ES_P0_CTL_REG_AD_VAL(val) (((val) & 0x1) << 15) -+#define LTQ_ES_P0_CTL_REG_AD_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_AD) >> 15) & 0x1) -+#define LTQ_ES_P0_CTL_REG_AD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_AD) | (((val) & 0x1) << 15)) -+/* Learning Disable (14) */ -+#define LTQ_ES_P0_CTL_REG_LD (0x1 << 14) -+#define LTQ_ES_P0_CTL_REG_LD_VAL(val) (((val) & 0x1) << 14) -+#define LTQ_ES_P0_CTL_REG_LD_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_LD) >> 14) & 0x1) -+#define LTQ_ES_P0_CTL_REG_LD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_LD) | (((val) & 0x1) << 14)) -+/* Maximum Number of Addresses (12:8) */ -+#define LTQ_ES_P0_CTL_REG_MNA024 (0x1f << 8) -+#define LTQ_ES_P0_CTL_REG_MNA024_VAL(val) (((val) & 0x1f) << 8) -+#define LTQ_ES_P0_CTL_REG_MNA024_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_MNA024) >> 8) & 0x1f) -+#define LTQ_ES_P0_CTL_REG_MNA024_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_MNA024) | (((val) & 0x1f) << 8)) -+/* PPPOE Port Only (7) */ -+#define LTQ_ES_P0_CTL_REG_PPPOEP (0x1 << 7) -+#define LTQ_ES_P0_CTL_REG_PPPOEP_VAL(val) (((val) & 0x1) << 7) -+#define LTQ_ES_P0_CTL_REG_PPPOEP_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_PPPOEP) >> 7) & 0x1) -+#define LTQ_ES_P0_CTL_REG_PPPOEP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_PPPOEP) | (((val) & 0x1) << 7)) -+/* PPPOE Manage (6) */ -+#define LTQ_ES_P0_CTL_REG_PM (0x1 << 6) -+#define LTQ_ES_P0_CTL_REG_PM_VAL(val) (((val) & 0x1) << 6) -+#define LTQ_ES_P0_CTL_REG_PM_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_PM) >> 6) & 0x1) -+#define LTQ_ES_P0_CTL_REG_PM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_PM) | (((val) & 0x1) << 6)) -+/* Port Mirror Option (5:4) */ -+#define LTQ_ES_P0_CTL_REG_IPMO (0x3 << 4) -+#define LTQ_ES_P0_CTL_REG_IPMO_VAL(val) (((val) & 0x3) << 4) -+#define LTQ_ES_P0_CTL_REG_IPMO_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_IPMO) >> 4) & 0x3) -+#define LTQ_ES_P0_CTL_REG_IPMO_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_IPMO) | (((val) & 0x3) << 4)) -+/* 802.1x Port Authorized state (3:2) */ -+#define LTQ_ES_P0_CTL_REG_PAS (0x3 << 2) -+#define LTQ_ES_P0_CTL_REG_PAS_VAL(val) (((val) & 0x3) << 2) -+#define LTQ_ES_P0_CTL_REG_PAS_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_PAS) >> 2) & 0x3) -+#define LTQ_ES_P0_CTL_REG_PAS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_PAS) | (((val) & 0x3) << 2)) -+/* Drop Scheme for voilation 802.1x (1) */ -+#define LTQ_ES_P0_CTL_REG_DSV8021X (0x1 << 1) -+#define LTQ_ES_P0_CTL_REG_DSV8021X_VAL(val) (((val) & 0x1) << 1) -+#define LTQ_ES_P0_CTL_REG_DSV8021X_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_DSV8021X) >> 1) & 0x1) -+#define LTQ_ES_P0_CTL_REG_DSV8021X_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_DSV8021X) | (((val) & 0x1) << 1)) -+/* ByPass Mode for Output (0) */ -+#define LTQ_ES_P0_CTL_REG_BYPASS (0x1) -+#define LTQ_ES_P0_CTL_REG_BYPASS_VAL(val) (((val) & 0x1) << 0) -+#define LTQ_ES_P0_CTL_REG_BYPASS_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_BYPASS) >> 0) & 0x1) -+#define LTQ_ES_P0_CTL_REG_BYPASS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_BYPASS) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Port 0 VLAN Control Register -+ ******************************************************************************/ -+ -+/* Default FID (31:30) */ -+#define LTQ_ES_P0_VLAN_REG_DFID (0x3 << 30) -+#define LTQ_ES_P0_VLAN_REG_DFID_VAL(val) (((val) & 0x3) << 30) -+#define LTQ_ES_P0_VLAN_REG_DFID_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_DFID) >> 30) & 0x3) -+#define LTQ_ES_P0_VLAN_REG_DFID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_DFID) | (((val) & 0x3) << 30)) -+/* Tagged Base VLAN Enable (29) */ -+#define LTQ_ES_P0_VLAN_REG_TBVE (0x1 << 29) -+#define LTQ_ES_P0_VLAN_REG_TBVE_VAL(val) (((val) & 0x1) << 29) -+#define LTQ_ES_P0_VLAN_REG_TBVE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_TBVE) >> 29) & 0x1) -+#define LTQ_ES_P0_VLAN_REG_TBVE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_TBVE) | (((val) & 0x1) << 29)) -+/* Input Force No TAG Enable (28) */ -+#define LTQ_ES_P0_VLAN_REG_IFNTE (0x1 << 28) -+#define LTQ_ES_P0_VLAN_REG_IFNTE_VAL(val) (((val) & 0x1) << 28) -+#define LTQ_ES_P0_VLAN_REG_IFNTE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_IFNTE) >> 28) & 0x1) -+#define LTQ_ES_P0_VLAN_REG_IFNTE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_IFNTE) | (((val) & 0x1) << 28)) -+/* VID Check with the VID table (27) */ -+#define LTQ_ES_P0_VLAN_REG_VC (0x1 << 27) -+#define LTQ_ES_P0_VLAN_REG_VC_VAL(val) (((val) & 0x1) << 27) -+#define LTQ_ES_P0_VLAN_REG_VC_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_VC) >> 27) & 0x1) -+#define LTQ_ES_P0_VLAN_REG_VC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_VC) | (((val) & 0x1) << 27)) -+/* VLAN Security Disable (26) */ -+#define LTQ_ES_P0_VLAN_REG_VSD (0x1 << 26) -+#define LTQ_ES_P0_VLAN_REG_VSD_VAL(val) (((val) & 0x1) << 26) -+#define LTQ_ES_P0_VLAN_REG_VSD_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_VSD) >> 26) & 0x1) -+#define LTQ_ES_P0_VLAN_REG_VSD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_VSD) | (((val) & 0x1) << 26)) -+/* Admit Only VLAN_Tagged Packet (25) */ -+#define LTQ_ES_P0_VLAN_REG_AOVTP (0x1 << 25) -+#define LTQ_ES_P0_VLAN_REG_AOVTP_VAL(val) (((val) & 0x1) << 25) -+#define LTQ_ES_P0_VLAN_REG_AOVTP_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_AOVTP) >> 25) & 0x1) -+#define LTQ_ES_P0_VLAN_REG_AOVTP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_AOVTP) | (((val) & 0x1) << 25)) -+/* VLAN Member Check Enable (24) */ -+#define LTQ_ES_P0_VLAN_REG_VMCE (0x1 << 24) -+#define LTQ_ES_P0_VLAN_REG_VMCE_VAL(val) (((val) & 0x1) << 24) -+#define LTQ_ES_P0_VLAN_REG_VMCE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_VMCE) >> 24) & 0x1) -+#define LTQ_ES_P0_VLAN_REG_VMCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_VMCE) | (((val) & 0x1) << 24)) -+/* Reserved (23:19) */ -+#define LTQ_ES_P0_VLAN_REG_RES (0x1f << 19) -+#define LTQ_ES_P0_VLAN_REG_RES_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_RES) >> 19) & 0x1f) -+/* Default VLAN Port Map (18:16) */ -+#define LTQ_ES_P0_VLAN_REG_DVPM (0x7 << 16) -+#define LTQ_ES_P0_VLAN_REG_DVPM_VAL(val) (((val) & 0x7) << 16) -+#define LTQ_ES_P0_VLAN_REG_DVPM_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_DVPM) >> 16) & 0x7) -+#define LTQ_ES_P0_VLAN_REG_DVPM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_DVPM) | (((val) & 0x7) << 16)) -+/* Port Priority (15:14) */ -+#define LTQ_ES_P0_VLAN_REG_PP (0x3 << 14) -+#define LTQ_ES_P0_VLAN_REG_PP_VAL(val) (((val) & 0x3) << 14) -+#define LTQ_ES_P0_VLAN_REG_PP_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PP) >> 14) & 0x3) -+#define LTQ_ES_P0_VLAN_REG_PP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PP) | (((val) & 0x3) << 14)) -+/* Port Priority Enable (13) */ -+#define LTQ_ES_P0_VLAN_REG_PPE (0x1 << 13) -+#define LTQ_ES_P0_VLAN_REG_PPE_VAL(val) (((val) & 0x1) << 13) -+#define LTQ_ES_P0_VLAN_REG_PPE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PPE) >> 13) & 0x1) -+#define LTQ_ES_P0_VLAN_REG_PPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PPE) | (((val) & 0x1) << 13)) -+/* Portbase VLAN tag member for Port 0 (12) */ -+#define LTQ_ES_P0_VLAN_REG_PVTAGMP (0x1 << 12) -+#define LTQ_ES_P0_VLAN_REG_PVTAGMP_VAL(val) (((val) & 0x1) << 12) -+#define LTQ_ES_P0_VLAN_REG_PVTAGMP_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PVTAGMP) >> 12) & 0x1) -+#define LTQ_ES_P0_VLAN_REG_PVTAGMP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PVTAGMP) | (((val) & 0x1) << 12)) -+/* PVID (11:0) */ -+#define LTQ_ES_P0_VLAN_REG_PVID (0xfff) -+#define LTQ_ES_P0_VLAN_REG_PVID_VAL(val) (((val) & 0xfff) << 0) -+#define LTQ_ES_P0_VLAN_REG_PVID_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PVID) >> 0) & 0xfff) -+#define LTQ_ES_P0_VLAN_REG_PVID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PVID) | (((val) & 0xfff) << 0)) -+ -+/******************************************************************************* -+ * Port 0 Ingress Control Register -+ ******************************************************************************/ -+ -+/* Reserved (31:13) */ -+#define LTQ_ES_P0_INCTL_REG_RES (0x7ffff << 13) -+#define LTQ_ES_P0_INCTL_REG_RES_GET(val) ((((val) & LTQ_ES_P0_INCTL_REG_RES) >> 13) & 0x7ffff) -+/* Port 0 Ingress/Egress Timer Tick T selection (12:11) */ -+#define LTQ_ES_P0_INCTL_REG_P0ITT (0x3 << 11) -+#define LTQ_ES_P0_INCTL_REG_P0ITT_VAL(val) (((val) & 0x3) << 11) -+#define LTQ_ES_P0_INCTL_REG_P0ITT_GET(val) ((((val) & LTQ_ES_P0_INCTL_REG_P0ITT) >> 11) & 0x3) -+#define LTQ_ES_P0_INCTL_REG_P0ITT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_INCTL_REG_P0ITT) | (((val) & 0x3) << 11)) -+/* Port 0 Igress Token R (10:0) */ -+#define LTQ_ES_P0_INCTL_REG_P0ITR (0x7ff) -+#define LTQ_ES_P0_INCTL_REG_P0ITR_VAL(val) (((val) & 0x7ff) << 0) -+#define LTQ_ES_P0_INCTL_REG_P0ITR_GET(val) ((((val) & LTQ_ES_P0_INCTL_REG_P0ITR) >> 0) & 0x7ff) -+#define LTQ_ES_P0_INCTL_REG_P0ITR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_INCTL_REG_P0ITR) | (((val) & 0x7ff) << 0)) -+ -+/******************************************************************************* -+ * Port 0 Egress Control for Strict Q32 Register -+ ******************************************************************************/ -+ -+/* Port 0 Egress Token R for Strict Priority Q3 (26:16) */ -+#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR (0x7ff << 16) -+#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR_VAL(val) (((val) & 0x7ff) << 16) -+#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR) >> 16) & 0x7ff) -+#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR) | (((val) & 0x7ff) << 16)) -+/* Port 0 Egress Token R for Strict Priority Q2 (10:0) */ -+#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR (0x7ff) -+#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR_VAL(val) (((val) & 0x7ff) << 0) -+#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR) >> 0) & 0x7ff) -+#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR) | (((val) & 0x7ff) << 0)) -+ -+/******************************************************************************* -+ * Port 0 Egress Control for Strict Q10 Register -+ ******************************************************************************/ -+ -+/* Reserved (31:27) */ -+#define LTQ_ES_P0_ECS_Q10_REG_RES (0x1f << 27) -+#define LTQ_ES_P0_ECS_Q10_REG_RES_GET(val) ((((val) & LTQ_ES_P0_ECS_Q10_REG_RES) >> 27) & 0x1f) -+/* Port 0 Egress Token R for Strict Priority Q1 (26:16) */ -+#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR (0x7ff << 16) -+#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR_VAL(val) (((val) & 0x7ff) << 16) -+#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR) >> 16) & 0x7ff) -+#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR) | (((val) & 0x7ff) << 16)) -+/* Port 0 Egress Token R for Strict Priority Q0 (10:0) */ -+#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR (0x7ff) -+#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR_VAL(val) (((val) & 0x7ff) << 0) -+#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR) >> 0) & 0x7ff) -+#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR) | (((val) & 0x7ff) << 0)) -+ -+/******************************************************************************* -+ * Port 0 Egress Control for WFQ Q32 Register -+ ******************************************************************************/ -+ -+/* Reserved (31:27) */ -+#define LTQ_ES_P0_ECW_Q32_REG_RES (0x1f << 27) -+#define LTQ_ES_P0_ECW_Q32_REG_RES_GET(val) ((((val) & LTQ_ES_P0_ECW_Q32_REG_RES) >> 27) & 0x1f) -+/* Port 0 Egress Token R for WFQ Q3 (26:16) */ -+#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR (0x7ff << 16) -+#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR_VAL(val) (((val) & 0x7ff) << 16) -+#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR) >> 16) & 0x7ff) -+#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR) | (((val) & 0x7ff) << 16)) -+/* Port 0 Egress Token R for WFQ Q2 (10:0) */ -+#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR (0x7ff) -+#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR_VAL(val) (((val) & 0x7ff) << 0) -+#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR) >> 0) & 0x7ff) -+#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR) | (((val) & 0x7ff) << 0)) -+ -+/******************************************************************************* -+ * Port 0 Egress Control for WFQ Q10 Register -+ ******************************************************************************/ -+ -+/* Reserved (31:27) */ -+#define LTQ_ES_P0_ECW_Q10_REG_RES (0x1f << 27) -+#define LTQ_ES_P0_ECW_Q10_REG_RES_GET(val) ((((val) & LTQ_ES_P0_ECW_Q10_REG_RES) >> 27) & 0x1f) -+/* Port 0 Egress Token R for WFQ Q1 (26:16) */ -+#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR (0x7ff << 16) -+#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR_VAL(val) (((val) & 0x7ff) << 16) -+#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR) >> 16) & 0x7ff) -+#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR) | (((val) & 0x7ff) << 16)) -+/* Port 0 Egress Token R for WFQ Q0 (10:0) */ -+#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR (0x7ff) -+#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR_VAL(val) (((val) & 0x7ff) << 0) -+#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR) >> 0) & 0x7ff) -+#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR) | (((val) & 0x7ff) << 0)) -+ -+/******************************************************************************* -+ * Interrupt Enable Register -+ ******************************************************************************/ -+ -+/* Reserved (31:8) */ -+#define LTQ_ES_INT_ENA_REG_RES (0xffffff << 8) -+#define LTQ_ES_INT_ENA_REG_RES_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_RES) >> 8) & 0xffffff) -+/* Data Buffer is Full Interrupt Enable (7) */ -+#define LTQ_ES_INT_ENA_REG_DBFIE (0x1 << 7) -+#define LTQ_ES_INT_ENA_REG_DBFIE_VAL(val) (((val) & 0x1) << 7) -+#define LTQ_ES_INT_ENA_REG_DBFIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_DBFIE) >> 7) & 0x1) -+#define LTQ_ES_INT_ENA_REG_DBFIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_DBFIE) | (((val) & 0x1) << 7)) -+/* Data Buffer is nearly Full Interrupt Enable (6) */ -+#define LTQ_ES_INT_ENA_REG_DBNFIE (0x1 << 6) -+#define LTQ_ES_INT_ENA_REG_DBNFIE_VAL(val) (((val) & 0x1) << 6) -+#define LTQ_ES_INT_ENA_REG_DBNFIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_DBNFIE) >> 6) & 0x1) -+#define LTQ_ES_INT_ENA_REG_DBNFIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_DBNFIE) | (((val) & 0x1) << 6)) -+/* Learning Table Full Interrupt Enable (5) */ -+#define LTQ_ES_INT_ENA_REG_LTFIE (0x1 << 5) -+#define LTQ_ES_INT_ENA_REG_LTFIE_VAL(val) (((val) & 0x1) << 5) -+#define LTQ_ES_INT_ENA_REG_LTFIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_LTFIE) >> 5) & 0x1) -+#define LTQ_ES_INT_ENA_REG_LTFIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_LTFIE) | (((val) & 0x1) << 5)) -+/* Leaning Table Access Done Interrupt Enable (4) */ -+#define LTQ_ES_INT_ENA_REG_LTADIE (0x1 << 4) -+#define LTQ_ES_INT_ENA_REG_LTADIE_VAL(val) (((val) & 0x1) << 4) -+#define LTQ_ES_INT_ENA_REG_LTADIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_LTADIE) >> 4) & 0x1) -+#define LTQ_ES_INT_ENA_REG_LTADIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_LTADIE) | (((val) & 0x1) << 4)) -+/* Port Security Violation Interrupt Enable (3:1) */ -+#define LTQ_ES_INT_ENA_REG_PSVIE (0x7 << 1) -+#define LTQ_ES_INT_ENA_REG_PSVIE_VAL(val) (((val) & 0x7) << 1) -+#define LTQ_ES_INT_ENA_REG_PSVIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_PSVIE) >> 1) & 0x7) -+#define LTQ_ES_INT_ENA_REG_PSVIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_PSVIE) | (((val) & 0x7) << 1)) -+/* Port Status Change Interrupt Enable (0) */ -+#define LTQ_ES_INT_ENA_REG_PSCIE (0x1) -+#define LTQ_ES_INT_ENA_REG_PSCIE_VAL(val) (((val) & 0x1) << 0) -+#define LTQ_ES_INT_ENA_REG_PSCIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_PSCIE) >> 0) & 0x1) -+#define LTQ_ES_INT_ENA_REG_PSCIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_PSCIE) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Interrupt Status Register -+ ******************************************************************************/ -+ -+/* Reserved (31:8) */ -+#define LTQ_ES_INT_ST_REG_RES (0xffffff << 8) -+#define LTQ_ES_INT_ST_REG_RES_GET(val) ((((val) & LTQ_ES_INT_ST_REG_RES) >> 8) & 0xffffff) -+/* Data Buffer is Full (7) */ -+#define LTQ_ES_INT_ST_REG_DBF (0x1 << 7) -+#define LTQ_ES_INT_ST_REG_DBF_GET(val) ((((val) & LTQ_ES_INT_ST_REG_DBF) >> 7) & 0x1) -+/* Data Buffer is nearly Full (6) */ -+#define LTQ_ES_INT_ST_REG_DBNF (0x1 << 6) -+#define LTQ_ES_INT_ST_REG_DBNF_GET(val) ((((val) & LTQ_ES_INT_ST_REG_DBNF) >> 6) & 0x1) -+/* Learning Table Full (5) */ -+#define LTQ_ES_INT_ST_REG_LTF (0x1 << 5) -+#define LTQ_ES_INT_ST_REG_LTF_GET(val) ((((val) & LTQ_ES_INT_ST_REG_LTF) >> 5) & 0x1) -+/* Leaning Table Access Done (4) */ -+#define LTQ_ES_INT_ST_REG_LTAD (0x1 << 4) -+#define LTQ_ES_INT_ST_REG_LTAD_GET(val) ((((val) & LTQ_ES_INT_ST_REG_LTAD) >> 4) & 0x1) -+/* Port Security Violation (3:1) */ -+#define LTQ_ES_INT_ST_REG_PSV (0x7 << 1) -+#define LTQ_ES_INT_ST_REG_PSV_GET(val) ((((val) & LTQ_ES_INT_ST_REG_PSV) >> 1) & 0x7) -+/* Port Status Change (0) */ -+#define LTQ_ES_INT_ST_REG_PSC (0x1) -+#define LTQ_ES_INT_ST_REG_PSC_GET(val) ((((val) & LTQ_ES_INT_ST_REG_PSC) >> 0) & 0x1) -+ -+/******************************************************************************* -+ * Switch Global Control Register 0 -+ ******************************************************************************/ -+ -+/* Switch Enable (31) */ -+#define LTQ_ES_SW_GCTL0_REG_SE (0x1 << 31) -+#define LTQ_ES_SW_GCTL0_REG_SE_VAL(val) (((val) & 0x1) << 31) -+#define LTQ_ES_SW_GCTL0_REG_SE_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_SE) >> 31) & 0x1) -+#define LTQ_ES_SW_GCTL0_REG_SE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_SE) | (((val) & 0x1) << 31)) -+/* CRC Check Disable (30) */ -+#define LTQ_ES_SW_GCTL0_REG_ICRCCD (0x1 << 30) -+#define LTQ_ES_SW_GCTL0_REG_ICRCCD_VAL(val) (((val) & 0x1) << 30) -+#define LTQ_ES_SW_GCTL0_REG_ICRCCD_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_ICRCCD) >> 30) & 0x1) -+#define LTQ_ES_SW_GCTL0_REG_ICRCCD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_ICRCCD) | (((val) & 0x1) << 30)) -+/* Replace VID0 (28) */ -+#define LTQ_ES_SW_GCTL0_REG_RVID0 (0x1 << 28) -+#define LTQ_ES_SW_GCTL0_REG_RVID0_VAL(val) (((val) & 0x1) << 28) -+#define LTQ_ES_SW_GCTL0_REG_RVID0_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_RVID0) >> 28) & 0x1) -+#define LTQ_ES_SW_GCTL0_REG_RVID0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_RVID0) | (((val) & 0x1) << 28)) -+/* Replace VID1 (27) */ -+#define LTQ_ES_SW_GCTL0_REG_RVID1 (0x1 << 27) -+#define LTQ_ES_SW_GCTL0_REG_RVID1_VAL(val) (((val) & 0x1) << 27) -+#define LTQ_ES_SW_GCTL0_REG_RVID1_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_RVID1) >> 27) & 0x1) -+#define LTQ_ES_SW_GCTL0_REG_RVID1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_RVID1) | (((val) & 0x1) << 27)) -+/* Replace VIDFFF (26) */ -+#define LTQ_ES_SW_GCTL0_REG_RVIDFFF (0x1 << 26) -+#define LTQ_ES_SW_GCTL0_REG_RVIDFFF_VAL(val) (((val) & 0x1) << 26) -+#define LTQ_ES_SW_GCTL0_REG_RVIDFFF_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_RVIDFFF) >> 26) & 0x1) -+#define LTQ_ES_SW_GCTL0_REG_RVIDFFF_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_RVIDFFF) | (((val) & 0x1) << 26)) -+/* Priority Change Rule (25) */ -+#define LTQ_ES_SW_GCTL0_REG_PCR (0x1 << 25) -+#define LTQ_ES_SW_GCTL0_REG_PCR_VAL(val) (((val) & 0x1) << 25) -+#define LTQ_ES_SW_GCTL0_REG_PCR_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_PCR) >> 25) & 0x1) -+#define LTQ_ES_SW_GCTL0_REG_PCR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_PCR) | (((val) & 0x1) << 25)) -+/* Priority Change Enable (24) */ -+#define LTQ_ES_SW_GCTL0_REG_PCE (0x1 << 24) -+#define LTQ_ES_SW_GCTL0_REG_PCE_VAL(val) (((val) & 0x1) << 24) -+#define LTQ_ES_SW_GCTL0_REG_PCE_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_PCE) >> 24) & 0x1) -+#define LTQ_ES_SW_GCTL0_REG_PCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_PCE) | (((val) & 0x1) << 24)) -+/* Transmit Short IPG Enable (23) */ -+#define LTQ_ES_SW_GCTL0_REG_TSIPGE (0x1 << 23) -+#define LTQ_ES_SW_GCTL0_REG_TSIPGE_VAL(val) (((val) & 0x1) << 23) -+#define LTQ_ES_SW_GCTL0_REG_TSIPGE_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_TSIPGE) >> 23) & 0x1) -+#define LTQ_ES_SW_GCTL0_REG_TSIPGE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_TSIPGE) | (((val) & 0x1) << 23)) -+/* PHY Base Address (22) */ -+#define LTQ_ES_SW_GCTL0_REG_PHYBA (0x1 << 22) -+#define LTQ_ES_SW_GCTL0_REG_PHYBA_VAL(val) (((val) & 0x1) << 22) -+#define LTQ_ES_SW_GCTL0_REG_PHYBA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_PHYBA) >> 22) & 0x1) -+#define LTQ_ES_SW_GCTL0_REG_PHYBA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_PHYBA) | (((val) & 0x1) << 22)) -+/* Drop Packet When Excessive Collision Happen (21) */ -+#define LTQ_ES_SW_GCTL0_REG_DPWECH (0x1 << 21) -+#define LTQ_ES_SW_GCTL0_REG_DPWECH_VAL(val) (((val) & 0x1) << 21) -+#define LTQ_ES_SW_GCTL0_REG_DPWECH_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DPWECH) >> 21) & 0x1) -+#define LTQ_ES_SW_GCTL0_REG_DPWECH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DPWECH) | (((val) & 0x1) << 21)) -+/* Aging Timer Select (20:18) */ -+#define LTQ_ES_SW_GCTL0_REG_ATS (0x7 << 18) -+#define LTQ_ES_SW_GCTL0_REG_ATS_VAL(val) (((val) & 0x7) << 18) -+#define LTQ_ES_SW_GCTL0_REG_ATS_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_ATS) >> 18) & 0x7) -+#define LTQ_ES_SW_GCTL0_REG_ATS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_ATS) | (((val) & 0x7) << 18)) -+/* Mirror CRC Also (17) */ -+#define LTQ_ES_SW_GCTL0_REG_MCA (0x1 << 17) -+#define LTQ_ES_SW_GCTL0_REG_MCA_VAL(val) (((val) & 0x1) << 17) -+#define LTQ_ES_SW_GCTL0_REG_MCA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MCA) >> 17) & 0x1) -+#define LTQ_ES_SW_GCTL0_REG_MCA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MCA) | (((val) & 0x1) << 17)) -+/* Mirror RXER Also (16) */ -+#define LTQ_ES_SW_GCTL0_REG_MRA (0x1 << 16) -+#define LTQ_ES_SW_GCTL0_REG_MRA_VAL(val) (((val) & 0x1) << 16) -+#define LTQ_ES_SW_GCTL0_REG_MRA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MRA) >> 16) & 0x1) -+#define LTQ_ES_SW_GCTL0_REG_MRA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MRA) | (((val) & 0x1) << 16)) -+/* Mirror PAUSE Also (15) */ -+#define LTQ_ES_SW_GCTL0_REG_MPA (0x1 << 15) -+#define LTQ_ES_SW_GCTL0_REG_MPA_VAL(val) (((val) & 0x1) << 15) -+#define LTQ_ES_SW_GCTL0_REG_MPA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MPA) >> 15) & 0x1) -+#define LTQ_ES_SW_GCTL0_REG_MPA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MPA) | (((val) & 0x1) << 15)) -+/* Mirror Long Also (14) */ -+#define LTQ_ES_SW_GCTL0_REG_MLA (0x1 << 14) -+#define LTQ_ES_SW_GCTL0_REG_MLA_VAL(val) (((val) & 0x1) << 14) -+#define LTQ_ES_SW_GCTL0_REG_MLA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MLA) >> 14) & 0x1) -+#define LTQ_ES_SW_GCTL0_REG_MLA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MLA) | (((val) & 0x1) << 14)) -+/* Mirror Short Also (13) */ -+#define LTQ_ES_SW_GCTL0_REG_MSA (0x1 << 13) -+#define LTQ_ES_SW_GCTL0_REG_MSA_VAL(val) (((val) & 0x1) << 13) -+#define LTQ_ES_SW_GCTL0_REG_MSA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MSA) >> 13) & 0x1) -+#define LTQ_ES_SW_GCTL0_REG_MSA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MSA) | (((val) & 0x1) << 13)) -+/* Sniffer port number (12:11) */ -+#define LTQ_ES_SW_GCTL0_REG_SNIFFPN (0x3 << 11) -+#define LTQ_ES_SW_GCTL0_REG_SNIFFPN_VAL(val) (((val) & 0x3) << 11) -+#define LTQ_ES_SW_GCTL0_REG_SNIFFPN_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_SNIFFPN) >> 11) & 0x3) -+#define LTQ_ES_SW_GCTL0_REG_SNIFFPN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_SNIFFPN) | (((val) & 0x3) << 11)) -+/* Max Packet Length (MAXPKTLEN) (9:8) */ -+#define LTQ_ES_SW_GCTL0_REG_MPL (0x3 << 8) -+#define LTQ_ES_SW_GCTL0_REG_MPL_VAL(val) (((val) & 0x3) << 8) -+#define LTQ_ES_SW_GCTL0_REG_MPL_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MPL) >> 8) & 0x3) -+#define LTQ_ES_SW_GCTL0_REG_MPL_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MPL) | (((val) & 0x3) << 8)) -+/* Discard Mode (Drop scheme for Packets Classified as Q3) (7:6) */ -+#define LTQ_ES_SW_GCTL0_REG_DMQ3 (0x3 << 6) -+#define LTQ_ES_SW_GCTL0_REG_DMQ3_VAL(val) (((val) & 0x3) << 6) -+#define LTQ_ES_SW_GCTL0_REG_DMQ3_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ3) >> 6) & 0x3) -+#define LTQ_ES_SW_GCTL0_REG_DMQ3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ3) | (((val) & 0x3) << 6)) -+/* Discard Mode (Drop scheme for Packets Classified as Q2) (5:4) */ -+#define LTQ_ES_SW_GCTL0_REG_DMQ2 (0x3 << 4) -+#define LTQ_ES_SW_GCTL0_REG_DMQ2_VAL(val) (((val) & 0x3) << 4) -+#define LTQ_ES_SW_GCTL0_REG_DMQ2_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ2) >> 4) & 0x3) -+#define LTQ_ES_SW_GCTL0_REG_DMQ2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ2) | (((val) & 0x3) << 4)) -+/* Discard Mode (Drop scheme for Packets Classified as Q1) (3:2) */ -+#define LTQ_ES_SW_GCTL0_REG_DMQ1 (0x3 << 2) -+#define LTQ_ES_SW_GCTL0_REG_DMQ1_VAL(val) (((val) & 0x3) << 2) -+#define LTQ_ES_SW_GCTL0_REG_DMQ1_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ1) >> 2) & 0x3) -+#define LTQ_ES_SW_GCTL0_REG_DMQ1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ1) | (((val) & 0x3) << 2)) -+/* Discard Mode (Drop scheme for Packets Classified as Q0) (1:0) */ -+#define LTQ_ES_SW_GCTL0_REG_DMQ0 (0x3) -+#define LTQ_ES_SW_GCTL0_REG_DMQ0_VAL(val) (((val) & 0x3) << 0) -+#define LTQ_ES_SW_GCTL0_REG_DMQ0_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ0) >> 0) & 0x3) -+#define LTQ_ES_SW_GCTL0_REG_DMQ0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ0) | (((val) & 0x3) << 0)) -+ -+/******************************************************************************* -+ * Switch Global Control Register 1 -+ ******************************************************************************/ -+ -+/* BIST Done (27) */ -+#define LTQ_ES_SW_GCTL1_REG_BISTDN (0x1 << 27) -+#define LTQ_ES_SW_GCTL1_REG_BISTDN_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_BISTDN) >> 27) & 0x1) -+/* Enable drop scheme of TX and RX (26) */ -+#define LTQ_ES_SW_GCTL1_REG_EDSTX (0x1 << 26) -+#define LTQ_ES_SW_GCTL1_REG_EDSTX_VAL(val) (((val) & 0x1) << 26) -+#define LTQ_ES_SW_GCTL1_REG_EDSTX_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_EDSTX) >> 26) & 0x1) -+#define LTQ_ES_SW_GCTL1_REG_EDSTX_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_EDSTX) | (((val) & 0x1) << 26)) -+/* Congestion threshold for TX queue (25:24) */ -+#define LTQ_ES_SW_GCTL1_REG_CTTX (0x3 << 24) -+#define LTQ_ES_SW_GCTL1_REG_CTTX_VAL(val) (((val) & 0x3) << 24) -+#define LTQ_ES_SW_GCTL1_REG_CTTX_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_CTTX) >> 24) & 0x3) -+#define LTQ_ES_SW_GCTL1_REG_CTTX_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_CTTX) | (((val) & 0x3) << 24)) -+/* Input Jam Threshold (23:21) */ -+#define LTQ_ES_SW_GCTL1_REG_IJT (0x7 << 21) -+#define LTQ_ES_SW_GCTL1_REG_IJT_VAL(val) (((val) & 0x7) << 21) -+#define LTQ_ES_SW_GCTL1_REG_IJT_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_IJT) >> 21) & 0x7) -+#define LTQ_ES_SW_GCTL1_REG_IJT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_IJT) | (((val) & 0x7) << 21)) -+/* Do not Identify VLAN after SNAP (20) */ -+#define LTQ_ES_SW_GCTL1_REG_DIVS (0x1 << 20) -+#define LTQ_ES_SW_GCTL1_REG_DIVS_VAL(val) (((val) & 0x1) << 20) -+#define LTQ_ES_SW_GCTL1_REG_DIVS_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIVS) >> 20) & 0x1) -+#define LTQ_ES_SW_GCTL1_REG_DIVS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIVS) | (((val) & 0x1) << 20)) -+/* Do not Identify IPV6 in PPPOE (19) */ -+#define LTQ_ES_SW_GCTL1_REG_DII6P (0x1 << 19) -+#define LTQ_ES_SW_GCTL1_REG_DII6P_VAL(val) (((val) & 0x1) << 19) -+#define LTQ_ES_SW_GCTL1_REG_DII6P_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DII6P) >> 19) & 0x1) -+#define LTQ_ES_SW_GCTL1_REG_DII6P_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DII6P) | (((val) & 0x1) << 19)) -+/* Do not Identify IP in PPPOE after SNAP (18) */ -+#define LTQ_ES_SW_GCTL1_REG_DIIPS (0x1 << 18) -+#define LTQ_ES_SW_GCTL1_REG_DIIPS_VAL(val) (((val) & 0x1) << 18) -+#define LTQ_ES_SW_GCTL1_REG_DIIPS_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIIPS) >> 18) & 0x1) -+#define LTQ_ES_SW_GCTL1_REG_DIIPS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIIPS) | (((val) & 0x1) << 18)) -+/* Do not Identify Ether-Type = 0x0800, IP VER = 6 as IPV6 packets (17) */ -+#define LTQ_ES_SW_GCTL1_REG_DIE (0x1 << 17) -+#define LTQ_ES_SW_GCTL1_REG_DIE_VAL(val) (((val) & 0x1) << 17) -+#define LTQ_ES_SW_GCTL1_REG_DIE_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIE) >> 17) & 0x1) -+#define LTQ_ES_SW_GCTL1_REG_DIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIE) | (((val) & 0x1) << 17)) -+/* Do not Identify IP in PPPOE (16) */ -+#define LTQ_ES_SW_GCTL1_REG_DIIP (0x1 << 16) -+#define LTQ_ES_SW_GCTL1_REG_DIIP_VAL(val) (((val) & 0x1) << 16) -+#define LTQ_ES_SW_GCTL1_REG_DIIP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIIP) >> 16) & 0x1) -+#define LTQ_ES_SW_GCTL1_REG_DIIP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIIP) | (((val) & 0x1) << 16)) -+/* Do not Identify SNAP (15) */ -+#define LTQ_ES_SW_GCTL1_REG_DIS (0x1 << 15) -+#define LTQ_ES_SW_GCTL1_REG_DIS_VAL(val) (((val) & 0x1) << 15) -+#define LTQ_ES_SW_GCTL1_REG_DIS_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIS) >> 15) & 0x1) -+#define LTQ_ES_SW_GCTL1_REG_DIS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIS) | (((val) & 0x1) << 15)) -+/* Unicast Portmap (14:12) */ -+#define LTQ_ES_SW_GCTL1_REG_UP (0x7 << 12) -+#define LTQ_ES_SW_GCTL1_REG_UP_VAL(val) (((val) & 0x7) << 12) -+#define LTQ_ES_SW_GCTL1_REG_UP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_UP) >> 12) & 0x7) -+#define LTQ_ES_SW_GCTL1_REG_UP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_UP) | (((val) & 0x7) << 12)) -+/* Broadcast Portmap (10:8) */ -+#define LTQ_ES_SW_GCTL1_REG_BP (0x7 << 8) -+#define LTQ_ES_SW_GCTL1_REG_BP_VAL(val) (((val) & 0x7) << 8) -+#define LTQ_ES_SW_GCTL1_REG_BP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_BP) >> 8) & 0x7) -+#define LTQ_ES_SW_GCTL1_REG_BP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_BP) | (((val) & 0x7) << 8)) -+/* Multicast Portmap (6:4) */ -+#define LTQ_ES_SW_GCTL1_REG_MP (0x7 << 4) -+#define LTQ_ES_SW_GCTL1_REG_MP_VAL(val) (((val) & 0x7) << 4) -+#define LTQ_ES_SW_GCTL1_REG_MP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_MP) >> 4) & 0x7) -+#define LTQ_ES_SW_GCTL1_REG_MP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_MP) | (((val) & 0x7) << 4)) -+/* Reserve Portmap (2:0) */ -+#define LTQ_ES_SW_GCTL1_REG_RP (0x7) -+#define LTQ_ES_SW_GCTL1_REG_RP_VAL(val) (((val) & 0x7) << 0) -+#define LTQ_ES_SW_GCTL1_REG_RP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_RP) >> 0) & 0x7) -+#define LTQ_ES_SW_GCTL1_REG_RP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_RP) | (((val) & 0x7) << 0)) -+ -+/******************************************************************************* -+ * ARP/RARP Register -+ ******************************************************************************/ -+ -+/* MAC Control Action (15:14) */ -+#define LTQ_ES_ARP_REG_MACA (0x3 << 14) -+#define LTQ_ES_ARP_REG_MACA_VAL(val) (((val) & 0x3) << 14) -+#define LTQ_ES_ARP_REG_MACA_GET(val) ((((val) & LTQ_ES_ARP_REG_MACA) >> 14) & 0x3) -+#define LTQ_ES_ARP_REG_MACA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_MACA) | (((val) & 0x3) << 14)) -+/* Unicast packet Treated as Cross_VLAN packet (13) */ -+#define LTQ_ES_ARP_REG_UPT (0x1 << 13) -+#define LTQ_ES_ARP_REG_UPT_VAL(val) (((val) & 0x1) << 13) -+#define LTQ_ES_ARP_REG_UPT_GET(val) ((((val) & LTQ_ES_ARP_REG_UPT) >> 13) & 0x1) -+#define LTQ_ES_ARP_REG_UPT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_UPT) | (((val) & 0x1) << 13)) -+/* RARP Packet Treated as Cross_VLAN Packet (12) */ -+#define LTQ_ES_ARP_REG_RPT (0x1 << 12) -+#define LTQ_ES_ARP_REG_RPT_VAL(val) (((val) & 0x1) << 12) -+#define LTQ_ES_ARP_REG_RPT_GET(val) ((((val) & LTQ_ES_ARP_REG_RPT) >> 12) & 0x1) -+#define LTQ_ES_ARP_REG_RPT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RPT) | (((val) & 0x1) << 12)) -+/* RARP/ARP Packet Action (11:10) */ -+#define LTQ_ES_ARP_REG_RAPA (0x3 << 10) -+#define LTQ_ES_ARP_REG_RAPA_VAL(val) (((val) & 0x3) << 10) -+#define LTQ_ES_ARP_REG_RAPA_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPA) >> 10) & 0x3) -+#define LTQ_ES_ARP_REG_RAPA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPA) | (((val) & 0x3) << 10)) -+/* RARP/ARP Packet Priority Enable (9) */ -+#define LTQ_ES_ARP_REG_RAPPE (0x1 << 9) -+#define LTQ_ES_ARP_REG_RAPPE_VAL(val) (((val) & 0x1) << 9) -+#define LTQ_ES_ARP_REG_RAPPE_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPPE) >> 9) & 0x1) -+#define LTQ_ES_ARP_REG_RAPPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPPE) | (((val) & 0x1) << 9)) -+/* RARP/ARP Packet Priority (8:7) */ -+#define LTQ_ES_ARP_REG_RAPP (0x3 << 7) -+#define LTQ_ES_ARP_REG_RAPP_VAL(val) (((val) & 0x3) << 7) -+#define LTQ_ES_ARP_REG_RAPP_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPP) >> 7) & 0x3) -+#define LTQ_ES_ARP_REG_RAPP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPP) | (((val) & 0x3) << 7)) -+/* RARP/ARP Packet Output Tag Handle (6:5) */ -+#define LTQ_ES_ARP_REG_RAPOTH (0x3 << 5) -+#define LTQ_ES_ARP_REG_RAPOTH_VAL(val) (((val) & 0x3) << 5) -+#define LTQ_ES_ARP_REG_RAPOTH_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPOTH) >> 5) & 0x3) -+#define LTQ_ES_ARP_REG_RAPOTH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPOTH) | (((val) & 0x3) << 5)) -+/* ARP Packet Treated as Cross _ VLAN Packet (4) */ -+#define LTQ_ES_ARP_REG_APT (0x1 << 4) -+#define LTQ_ES_ARP_REG_APT_VAL(val) (((val) & 0x1) << 4) -+#define LTQ_ES_ARP_REG_APT_GET(val) ((((val) & LTQ_ES_ARP_REG_APT) >> 4) & 0x1) -+#define LTQ_ES_ARP_REG_APT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_APT) | (((val) & 0x1) << 4)) -+/* RARP/ARP Packet Treated as Management Packet (3) */ -+#define LTQ_ES_ARP_REG_RAPTM (0x1 << 3) -+#define LTQ_ES_ARP_REG_RAPTM_VAL(val) (((val) & 0x1) << 3) -+#define LTQ_ES_ARP_REG_RAPTM_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPTM) >> 3) & 0x1) -+#define LTQ_ES_ARP_REG_RAPTM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPTM) | (((val) & 0x1) << 3)) -+/* RARP/ARP Packet Treated as Span Packet (2) */ -+#define LTQ_ES_ARP_REG_TAPTS (0x1 << 2) -+#define LTQ_ES_ARP_REG_TAPTS_VAL(val) (((val) & 0x1) << 2) -+#define LTQ_ES_ARP_REG_TAPTS_GET(val) ((((val) & LTQ_ES_ARP_REG_TAPTS) >> 2) & 0x1) -+#define LTQ_ES_ARP_REG_TAPTS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_TAPTS) | (((val) & 0x1) << 2)) -+/* Trap ARP Packet (1) */ -+#define LTQ_ES_ARP_REG_TAP (0x1 << 1) -+#define LTQ_ES_ARP_REG_TAP_VAL(val) (((val) & 0x1) << 1) -+#define LTQ_ES_ARP_REG_TAP_GET(val) ((((val) & LTQ_ES_ARP_REG_TAP) >> 1) & 0x1) -+#define LTQ_ES_ARP_REG_TAP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_TAP) | (((val) & 0x1) << 1)) -+/* Trap RARP Packet (0) */ -+#define LTQ_ES_ARP_REG_TRP (0x1) -+#define LTQ_ES_ARP_REG_TRP_VAL(val) (((val) & 0x1) << 0) -+#define LTQ_ES_ARP_REG_TRP_GET(val) ((((val) & LTQ_ES_ARP_REG_TRP) >> 0) & 0x1) -+#define LTQ_ES_ARP_REG_TRP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_TRP) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Storm control Register -+ ******************************************************************************/ -+ -+/* Reserved (31:29) */ -+#define LTQ_ES_STRM_CTL_REG_RES (0x7 << 29) -+#define LTQ_ES_STRM_CTL_REG_RES_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_RES) >> 29) & 0x7) -+/* 10M Threshold (28:16) */ -+#define LTQ_ES_STRM_CTL_REG_STORM_10_TH (0x1fff << 16) -+#define LTQ_ES_STRM_CTL_REG_STORM_10_TH_VAL(val) (((val) & 0x1fff) << 16) -+#define LTQ_ES_STRM_CTL_REG_STORM_10_TH_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_10_TH) >> 16) & 0x1fff) -+#define LTQ_ES_STRM_CTL_REG_STORM_10_TH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_10_TH) | (((val) & 0x1fff) << 16)) -+/* Storm Enable for Broadcast Packets (15) */ -+#define LTQ_ES_STRM_CTL_REG_STORM_B (0x1 << 15) -+#define LTQ_ES_STRM_CTL_REG_STORM_B_VAL(val) (((val) & 0x1) << 15) -+#define LTQ_ES_STRM_CTL_REG_STORM_B_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_B) >> 15) & 0x1) -+#define LTQ_ES_STRM_CTL_REG_STORM_B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_B) | (((val) & 0x1) << 15)) -+/* Storm Enable for Multicast Packets (14) */ -+#define LTQ_ES_STRM_CTL_REG_STORM_M (0x1 << 14) -+#define LTQ_ES_STRM_CTL_REG_STORM_M_VAL(val) (((val) & 0x1) << 14) -+#define LTQ_ES_STRM_CTL_REG_STORM_M_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_M) >> 14) & 0x1) -+#define LTQ_ES_STRM_CTL_REG_STORM_M_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_M) | (((val) & 0x1) << 14)) -+/* Storm Enable for Un-learned Unicast Packets (13) */ -+#define LTQ_ES_STRM_CTL_REG_STORM_U (0x1 << 13) -+#define LTQ_ES_STRM_CTL_REG_STORM_U_VAL(val) (((val) & 0x1) << 13) -+#define LTQ_ES_STRM_CTL_REG_STORM_U_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_U) >> 13) & 0x1) -+#define LTQ_ES_STRM_CTL_REG_STORM_U_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_U) | (((val) & 0x1) << 13)) -+/* 100M Threshold (12:0) */ -+#define LTQ_ES_STRM_CTL_REG_STORM_100_TH (0x1fff) -+#define LTQ_ES_STRM_CTL_REG_STORM_100_TH_VAL(val) (((val) & 0x1fff) << 0) -+#define LTQ_ES_STRM_CTL_REG_STORM_100_TH_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_100_TH) >> 0) & 0x1fff) -+#define LTQ_ES_STRM_CTL_REG_STORM_100_TH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_100_TH) | (((val) & 0x1fff) << 0)) -+ -+/******************************************************************************* -+ * RGMII/GMII Port Control Register -+ ******************************************************************************/ -+ -+/* Management Clock Select (31:24) */ -+#define LTQ_ES_RGMII_CTL_REG_MCS (0xff << 24) -+#define LTQ_ES_RGMII_CTL_REG_MCS_VAL(val) (((val) & 0xff) << 24) -+#define LTQ_ES_RGMII_CTL_REG_MCS_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_MCS) >> 24) & 0xff) -+#define LTQ_ES_RGMII_CTL_REG_MCS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_MCS) | (((val) & 0xff) << 24)) -+/* Interface Selection (19:18) */ -+#define LTQ_ES_RGMII_CTL_REG_IS (0x3 << 18) -+#define LTQ_ES_RGMII_CTL_REG_IS_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_IS) >> 18) & 0x3) -+/* Port 1 RGMII Rx Clock Delay (17:16) */ -+#define LTQ_ES_RGMII_CTL_REG_P1RDLY (0x3 << 16) -+#define LTQ_ES_RGMII_CTL_REG_P1RDLY_VAL(val) (((val) & 0x3) << 16) -+#define LTQ_ES_RGMII_CTL_REG_P1RDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1RDLY) >> 16) & 0x3) -+#define LTQ_ES_RGMII_CTL_REG_P1RDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1RDLY) | (((val) & 0x3) << 16)) -+/* Port 1 RGMII Tx Clock Delay (15:14) */ -+#define LTQ_ES_RGMII_CTL_REG_P1TDLY (0x3 << 14) -+#define LTQ_ES_RGMII_CTL_REG_P1TDLY_VAL(val) (((val) & 0x3) << 14) -+#define LTQ_ES_RGMII_CTL_REG_P1TDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1TDLY) >> 14) & 0x3) -+#define LTQ_ES_RGMII_CTL_REG_P1TDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1TDLY) | (((val) & 0x3) << 14)) -+/* Port 1 Speed (13:12) */ -+#define LTQ_ES_RGMII_CTL_REG_P1SPD (0x3 << 12) -+#define LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(val) (((val) & 0x3) << 12) -+#define LTQ_ES_RGMII_CTL_REG_P1SPD_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1SPD) >> 12) & 0x3) -+#define LTQ_ES_RGMII_CTL_REG_P1SPD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1SPD) | (((val) & 0x3) << 12)) -+/* Port 1 Duplex mode (11) */ -+#define LTQ_ES_RGMII_CTL_REG_P1DUP (0x1 << 11) -+#define LTQ_ES_RGMII_CTL_REG_P1DUP_VAL(val) (((val) & 0x1) << 11) -+#define LTQ_ES_RGMII_CTL_REG_P1DUP_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1DUP) >> 11) & 0x1) -+#define LTQ_ES_RGMII_CTL_REG_P1DUP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1DUP) | (((val) & 0x1) << 11)) -+/* Port 1 Flow Control Enable (10) */ -+#define LTQ_ES_RGMII_CTL_REG_P1FCE (0x1 << 10) -+#define LTQ_ES_RGMII_CTL_REG_P1FCE_VAL(val) (((val) & 0x1) << 10) -+#define LTQ_ES_RGMII_CTL_REG_P1FCE_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1FCE) >> 10) & 0x1) -+#define LTQ_ES_RGMII_CTL_REG_P1FCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1FCE) | (((val) & 0x1) << 10)) -+/* Port 0 RGMII Rx Clock Delay (7:6) */ -+#define LTQ_ES_RGMII_CTL_REG_P0RDLY (0x3 << 6) -+#define LTQ_ES_RGMII_CTL_REG_P0RDLY_VAL(val) (((val) & 0x3) << 6) -+#define LTQ_ES_RGMII_CTL_REG_P0RDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0RDLY) >> 6) & 0x3) -+#define LTQ_ES_RGMII_CTL_REG_P0RDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0RDLY) | (((val) & 0x3) << 6)) -+/* Port 0 RGMII Tx Clock Delay (5:4) */ -+#define LTQ_ES_RGMII_CTL_REG_P0TDLY (0x3 << 4) -+#define LTQ_ES_RGMII_CTL_REG_P0TDLY_VAL(val) (((val) & 0x3) << 4) -+#define LTQ_ES_RGMII_CTL_REG_P0TDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0TDLY) >> 4) & 0x3) -+#define LTQ_ES_RGMII_CTL_REG_P0TDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0TDLY) | (((val) & 0x3) << 4)) -+/* Port 0 Speed (3:2) */ -+#define LTQ_ES_RGMII_CTL_REG_P0SPD (0x3 << 2) -+#define LTQ_ES_RGMII_CTL_REG_P0SPD_VAL(val) (((val) & 0x3) << 2) -+#define LTQ_ES_RGMII_CTL_REG_P0SPD_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0SPD) >> 2) & 0x3) -+#define LTQ_ES_RGMII_CTL_REG_P0SPD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0SPD) | (((val) & 0x3) << 2)) -+/* Port 0 Duplex mode (1) */ -+#define LTQ_ES_RGMII_CTL_REG_P0DUP (0x1 << 1) -+#define LTQ_ES_RGMII_CTL_REG_P0DUP_VAL(val) (((val) & 0x1) << 1) -+#define LTQ_ES_RGMII_CTL_REG_P0DUP_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0DUP) >> 1) & 0x1) -+#define LTQ_ES_RGMII_CTL_REG_P0DUP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0DUP) | (((val) & 0x1) << 1)) -+/* Port 0 Flow Control Enable (0) */ -+#define LTQ_ES_RGMII_CTL_REG_P0FCE (0x1) -+#define LTQ_ES_RGMII_CTL_REG_P0FCE_VAL(val) (((val) & 0x1) << 0) -+#define LTQ_ES_RGMII_CTL_REG_P0FCE_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0FCE) >> 0) & 0x1) -+#define LTQ_ES_RGMII_CTL_REG_P0FCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0FCE) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * 802.1p Priority Map Register -+ ******************************************************************************/ -+ -+/* Priority Queue 7 (15:14) */ -+#define LTQ_ES_PRT_1P_REG_1PPQ7 (0x3 << 14) -+#define LTQ_ES_PRT_1P_REG_1PPQ7_VAL(val) (((val) & 0x3) << 14) -+#define LTQ_ES_PRT_1P_REG_1PPQ7_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ7) >> 14) & 0x3) -+#define LTQ_ES_PRT_1P_REG_1PPQ7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ7) | (((val) & 0x3) << 14)) -+/* Priority Queue 6 (13:12) */ -+#define LTQ_ES_PRT_1P_REG_1PPQ6 (0x3 << 12) -+#define LTQ_ES_PRT_1P_REG_1PPQ6_VAL(val) (((val) & 0x3) << 12) -+#define LTQ_ES_PRT_1P_REG_1PPQ6_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ6) >> 12) & 0x3) -+#define LTQ_ES_PRT_1P_REG_1PPQ6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ6) | (((val) & 0x3) << 12)) -+/* Priority Queue 5 (11:10) */ -+#define LTQ_ES_PRT_1P_REG_1PPQ5 (0x3 << 10) -+#define LTQ_ES_PRT_1P_REG_1PPQ5_VAL(val) (((val) & 0x3) << 10) -+#define LTQ_ES_PRT_1P_REG_1PPQ5_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ5) >> 10) & 0x3) -+#define LTQ_ES_PRT_1P_REG_1PPQ5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ5) | (((val) & 0x3) << 10)) -+/* Priority Queue 4 (9:8) */ -+#define LTQ_ES_PRT_1P_REG_1PPQ4 (0x3 << 8) -+#define LTQ_ES_PRT_1P_REG_1PPQ4_VAL(val) (((val) & 0x3) << 8) -+#define LTQ_ES_PRT_1P_REG_1PPQ4_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ4) >> 8) & 0x3) -+#define LTQ_ES_PRT_1P_REG_1PPQ4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ4) | (((val) & 0x3) << 8)) -+/* Priority Queue 3 (7:6) */ -+#define LTQ_ES_PRT_1P_REG_1PPQ3 (0x3 << 6) -+#define LTQ_ES_PRT_1P_REG_1PPQ3_VAL(val) (((val) & 0x3) << 6) -+#define LTQ_ES_PRT_1P_REG_1PPQ3_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ3) >> 6) & 0x3) -+#define LTQ_ES_PRT_1P_REG_1PPQ3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ3) | (((val) & 0x3) << 6)) -+/* Priority Queue 2 (5:4) */ -+#define LTQ_ES_PRT_1P_REG_1PPQ2 (0x3 << 4) -+#define LTQ_ES_PRT_1P_REG_1PPQ2_VAL(val) (((val) & 0x3) << 4) -+#define LTQ_ES_PRT_1P_REG_1PPQ2_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ2) >> 4) & 0x3) -+#define LTQ_ES_PRT_1P_REG_1PPQ2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ2) | (((val) & 0x3) << 4)) -+/* Priority Queue 1 (3:2) */ -+#define LTQ_ES_PRT_1P_REG_1PPQ1 (0x3 << 2) -+#define LTQ_ES_PRT_1P_REG_1PPQ1_VAL(val) (((val) & 0x3) << 2) -+#define LTQ_ES_PRT_1P_REG_1PPQ1_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ1) >> 2) & 0x3) -+#define LTQ_ES_PRT_1P_REG_1PPQ1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ1) | (((val) & 0x3) << 2)) -+/* Priority Queue 0 (1:0) */ -+#define LTQ_ES_PRT_1P_REG_1PPQ0 (0x3) -+#define LTQ_ES_PRT_1P_REG_1PPQ0_VAL(val) (((val) & 0x3) << 0) -+#define LTQ_ES_PRT_1P_REG_1PPQ0_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ0) >> 0) & 0x3) -+#define LTQ_ES_PRT_1P_REG_1PPQ0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ0) | (((val) & 0x3) << 0)) -+ -+/******************************************************************************* -+ * Global Bucket Size Base counter -+ ******************************************************************************/ -+ -+/* Reserved (31:18) */ -+#define LTQ_ES_GBKT_SZBS_REG_REV (0x3fff << 18) -+#define LTQ_ES_GBKT_SZBS_REG_REV_GET(val) ((((val) & LTQ_ES_GBKT_SZBS_REG_REV) >> 18) & 0x3fff) -+/* Base[17:0] (17:0) */ -+#define LTQ_ES_GBKT_SZBS_REG_BASE17_0 (0x3ffff) -+#define LTQ_ES_GBKT_SZBS_REG_BASE17_0_VAL(val) (((val) & 0x3ffff) << 0) -+#define LTQ_ES_GBKT_SZBS_REG_BASE17_0_GET(val) ((((val) & LTQ_ES_GBKT_SZBS_REG_BASE17_0) >> 0) & 0x3ffff) -+#define LTQ_ES_GBKT_SZBS_REG_BASE17_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_GBKT_SZBS_REG_BASE17_0) | (((val) & 0x3ffff) << 0)) -+ -+/******************************************************************************* -+ * Global Bucket Size Extend Base Counter -+ ******************************************************************************/ -+ -+/* Reserved (31:18) */ -+#define LTQ_ES_GBKT_SZEBS_REG_REV (0x3fff << 18) -+#define LTQ_ES_GBKT_SZEBS_REG_REV_GET(val) ((((val) & LTQ_ES_GBKT_SZEBS_REG_REV) >> 18) & 0x3fff) -+/* Extend Base[17:0] (17:0) */ -+#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0 (0x3ffff) -+#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0_VAL(val) (((val) & 0x3ffff) << 0) -+#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0_GET(val) ((((val) & LTQ_ES_GBKT_SZEBS_REG_EBASE17_0) >> 0) & 0x3ffff) -+#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_GBKT_SZEBS_REG_EBASE17_0) | (((val) & 0x3ffff) << 0)) -+ -+/******************************************************************************* -+ * Buffer Threshold Register -+ ******************************************************************************/ -+ -+/* Port Unfull Offset 3 (31:30) */ -+#define LTQ_ES_BF_TH_REG_PUO3 (0x3 << 30) -+#define LTQ_ES_BF_TH_REG_PUO3_VAL(val) (((val) & 0x3) << 30) -+#define LTQ_ES_BF_TH_REG_PUO3_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO3) >> 30) & 0x3) -+#define LTQ_ES_BF_TH_REG_PUO3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO3) | (((val) & 0x3) << 30)) -+/* Port Unfull Offset 2 (29:28) */ -+#define LTQ_ES_BF_TH_REG_PUO2 (0x3 << 28) -+#define LTQ_ES_BF_TH_REG_PUO2_VAL(val) (((val) & 0x3) << 28) -+#define LTQ_ES_BF_TH_REG_PUO2_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO2) >> 28) & 0x3) -+#define LTQ_ES_BF_TH_REG_PUO2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO2) | (((val) & 0x3) << 28)) -+/* Port Unfull Offset 1 (27:26) */ -+#define LTQ_ES_BF_TH_REG_PUO1 (0x3 << 26) -+#define LTQ_ES_BF_TH_REG_PUO1_VAL(val) (((val) & 0x3) << 26) -+#define LTQ_ES_BF_TH_REG_PUO1_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO1) >> 26) & 0x3) -+#define LTQ_ES_BF_TH_REG_PUO1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO1) | (((val) & 0x3) << 26)) -+/* Port Unfull Offset 0 (25:24) */ -+#define LTQ_ES_BF_TH_REG_PUO0 (0x3 << 24) -+#define LTQ_ES_BF_TH_REG_PUO0_VAL(val) (((val) & 0x3) << 24) -+#define LTQ_ES_BF_TH_REG_PUO0_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO0) >> 24) & 0x3) -+#define LTQ_ES_BF_TH_REG_PUO0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO0) | (((val) & 0x3) << 24)) -+/* Port Full Offset 3 (23:22) */ -+#define LTQ_ES_BF_TH_REG_PFO3 (0x3 << 22) -+#define LTQ_ES_BF_TH_REG_PFO3_VAL(val) (((val) & 0x3) << 22) -+#define LTQ_ES_BF_TH_REG_PFO3_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO3) >> 22) & 0x3) -+#define LTQ_ES_BF_TH_REG_PFO3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO3) | (((val) & 0x3) << 22)) -+/* Port Full Offset 2 (21:20) */ -+#define LTQ_ES_BF_TH_REG_PFO2 (0x3 << 20) -+#define LTQ_ES_BF_TH_REG_PFO2_VAL(val) (((val) & 0x3) << 20) -+#define LTQ_ES_BF_TH_REG_PFO2_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO2) >> 20) & 0x3) -+#define LTQ_ES_BF_TH_REG_PFO2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO2) | (((val) & 0x3) << 20)) -+/* Port Full Offset 1 (19:18) */ -+#define LTQ_ES_BF_TH_REG_PFO1 (0x3 << 18) -+#define LTQ_ES_BF_TH_REG_PFO1_VAL(val) (((val) & 0x3) << 18) -+#define LTQ_ES_BF_TH_REG_PFO1_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO1) >> 18) & 0x3) -+#define LTQ_ES_BF_TH_REG_PFO1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO1) | (((val) & 0x3) << 18)) -+/* Port Full Offset 0 (17:16) */ -+#define LTQ_ES_BF_TH_REG_PFO0 (0x3 << 16) -+#define LTQ_ES_BF_TH_REG_PFO0_VAL(val) (((val) & 0x3) << 16) -+#define LTQ_ES_BF_TH_REG_PFO0_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO0) >> 16) & 0x3) -+#define LTQ_ES_BF_TH_REG_PFO0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO0) | (((val) & 0x3) << 16)) -+/* Reserved (15:14) */ -+#define LTQ_ES_BF_TH_REG_RES (0x3 << 14) -+#define LTQ_ES_BF_TH_REG_RES_GET(val) ((((val) & LTQ_ES_BF_TH_REG_RES) >> 14) & 0x3) -+/* Total Low Add (13) */ -+#define LTQ_ES_BF_TH_REG_TLA (0x1 << 13) -+#define LTQ_ES_BF_TH_REG_TLA_VAL(val) (((val) & 0x1) << 13) -+#define LTQ_ES_BF_TH_REG_TLA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_TLA) >> 13) & 0x1) -+#define LTQ_ES_BF_TH_REG_TLA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_TLA) | (((val) & 0x1) << 13)) -+/* Total High Add (12) */ -+#define LTQ_ES_BF_TH_REG_THA (0x1 << 12) -+#define LTQ_ES_BF_TH_REG_THA_VAL(val) (((val) & 0x1) << 12) -+#define LTQ_ES_BF_TH_REG_THA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_THA) >> 12) & 0x1) -+#define LTQ_ES_BF_TH_REG_THA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_THA) | (((val) & 0x1) << 12)) -+/* Total Low Offset (11:10) */ -+#define LTQ_ES_BF_TH_REG_TLO (0x3 << 10) -+#define LTQ_ES_BF_TH_REG_TLO_VAL(val) (((val) & 0x3) << 10) -+#define LTQ_ES_BF_TH_REG_TLO_GET(val) ((((val) & LTQ_ES_BF_TH_REG_TLO) >> 10) & 0x3) -+#define LTQ_ES_BF_TH_REG_TLO_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_TLO) | (((val) & 0x3) << 10)) -+/* Total High Offset (9:8) */ -+#define LTQ_ES_BF_TH_REG_THO (0x3 << 8) -+#define LTQ_ES_BF_TH_REG_THO_VAL(val) (((val) & 0x3) << 8) -+#define LTQ_ES_BF_TH_REG_THO_GET(val) ((((val) & LTQ_ES_BF_TH_REG_THO) >> 8) & 0x3) -+#define LTQ_ES_BF_TH_REG_THO_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_THO) | (((val) & 0x3) << 8)) -+/* Port Unfull Add (7:4) */ -+#define LTQ_ES_BF_TH_REG_PUA (0xf << 4) -+#define LTQ_ES_BF_TH_REG_PUA_VAL(val) (((val) & 0xf) << 4) -+#define LTQ_ES_BF_TH_REG_PUA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUA) >> 4) & 0xf) -+#define LTQ_ES_BF_TH_REG_PUA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUA) | (((val) & 0xf) << 4)) -+/* Port Full Add (3:0) */ -+#define LTQ_ES_BF_TH_REG_PFA (0xf) -+#define LTQ_ES_BF_TH_REG_PFA_VAL(val) (((val) & 0xf) << 0) -+#define LTQ_ES_BF_TH_REG_PFA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFA) >> 0) & 0xf) -+#define LTQ_ES_BF_TH_REG_PFA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFA) | (((val) & 0xf) << 0)) -+ -+/******************************************************************************* -+ * PMAC Header Control Register -+ ******************************************************************************/ -+ -+/* Reserved (31:22) */ -+#define LTQ_ES_PMAC_HD_CTL_RES (0x3ff << 22) -+#define LTQ_ES_PMAC_HD_CTL_RES_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_RES) >> 22) & 0x3ff) -+/* Remove Layer-2 Header from Packets Going from PMAC to DMA (21) */ -+#define LTQ_ES_PMAC_HD_CTL_RL2 (0x1 << 21) -+#define LTQ_ES_PMAC_HD_CTL_RL2_VAL(val) (((val) & 0x1) << 21) -+#define LTQ_ES_PMAC_HD_CTL_RL2_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_RL2) >> 21) & 0x1) -+#define LTQ_ES_PMAC_HD_CTL_RL2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_RL2) | (((val) & 0x1) << 21)) -+/* Remove CRC from Packets Going from PMAC to DMA (20) */ -+#define LTQ_ES_PMAC_HD_CTL_RC (0x1 << 20) -+#define LTQ_ES_PMAC_HD_CTL_RC_VAL(val) (((val) & 0x1) << 20) -+#define LTQ_ES_PMAC_HD_CTL_RC_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_RC) >> 20) & 0x1) -+#define LTQ_ES_PMAC_HD_CTL_RC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_RC) | (((val) & 0x1) << 20)) -+/* Status Header for Packets from PMAC to DMA (19) */ -+#define LTQ_ES_PMAC_HD_CTL_AS (0x1 << 19) -+#define LTQ_ES_PMAC_HD_CTL_AS_VAL(val) (((val) & 0x1) << 19) -+#define LTQ_ES_PMAC_HD_CTL_AS_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_AS) >> 19) & 0x1) -+#define LTQ_ES_PMAC_HD_CTL_AS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_AS) | (((val) & 0x1) << 19)) -+/* Add CRC for packets from DMA to PMAC (18) */ -+#define LTQ_ES_PMAC_HD_CTL_AC (0x1 << 18) -+#define LTQ_ES_PMAC_HD_CTL_AC_VAL(val) (((val) & 0x1) << 18) -+#define LTQ_ES_PMAC_HD_CTL_AC_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_AC) >> 18) & 0x1) -+#define LTQ_ES_PMAC_HD_CTL_AC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_AC) | (((val) & 0x1) << 18)) -+/* Contains the length/type value to the added to packets from DMA to PMAC (17:2) */ -+#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN (0xffff << 2) -+#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN_VAL(val) (((val) & 0xffff) << 2) -+#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_TYPE_LEN) >> 2) & 0xffff) -+#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_TYPE_LEN) | (((val) & 0xffff) << 2)) -+/* Add TAG to Packets from DMA to PMAC (1) */ -+#define LTQ_ES_PMAC_HD_CTL_TAG (0x1 << 1) -+#define LTQ_ES_PMAC_HD_CTL_TAG_VAL(val) (((val) & 0x1) << 1) -+#define LTQ_ES_PMAC_HD_CTL_TAG_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_TAG) >> 1) & 0x1) -+#define LTQ_ES_PMAC_HD_CTL_TAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_TAG) | (((val) & 0x1) << 1)) -+/* ADD Header to Packets from DMA to PMAC (0) */ -+#define LTQ_ES_PMAC_HD_CTL_ADD (0x1) -+#define LTQ_ES_PMAC_HD_CTL_ADD_VAL(val) (((val) & 0x1) << 0) -+#define LTQ_ES_PMAC_HD_CTL_ADD_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_ADD) >> 0) & 0x1) -+#define LTQ_ES_PMAC_HD_CTL_ADD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_ADD) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * PMAC Source Address Register 1 -+ ******************************************************************************/ -+ -+/* Source Address to be inserted as a part of the Ethernet header. (15:0) */ -+#define LTQ_ES_PMAC_SA1_SA_47_32 (0xffff) -+#define LTQ_ES_PMAC_SA1_SA_47_32_VAL(val) (((val) & 0xffff) << 0) -+#define LTQ_ES_PMAC_SA1_SA_47_32_GET(val) ((((val) & LTQ_ES_PMAC_SA1_SA_47_32) >> 0) & 0xffff) -+#define LTQ_ES_PMAC_SA1_SA_47_32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_SA1_SA_47_32) | (((val) & 0xffff) << 0)) -+ -+/******************************************************************************* -+ * PMAC Source Address Register 2 -+ ******************************************************************************/ -+ -+/* Source Address (31:0) */ -+#define LTQ_ES_PMAC_SA2_SA_31_0 (0xFFFFFFFFL) -+#define LTQ_ES_PMAC_SA2_SA_31_0_VAL(val) (((val) & 0xFFFFFFFFL) << 0) -+#define LTQ_ES_PMAC_SA2_SA_31_0_GET(val) ((((val) & LTQ_ES_PMAC_SA2_SA_31_0) >> 0) & 0xFFFFFFFFL) -+#define LTQ_ES_PMAC_SA2_SA_31_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_SA2_SA_31_0) | (((val) & 0xFFFFFFFFL) << 0)) -+ -+/******************************************************************************* -+ * PMAC Destination Address Register 1 -+ ******************************************************************************/ -+ -+/* Destination Address (15:0) */ -+#define LTQ_ES_PMAC_DA1_DA_47_32 (0xffff) -+#define LTQ_ES_PMAC_DA1_DA_47_32_VAL(val) (((val) & 0xffff) << 0) -+#define LTQ_ES_PMAC_DA1_DA_47_32_GET(val) ((((val) & LTQ_ES_PMAC_DA1_DA_47_32) >> 0) & 0xffff) -+#define LTQ_ES_PMAC_DA1_DA_47_32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_DA1_DA_47_32) | (((val) & 0xffff) << 0)) -+ -+/******************************************************************************* -+ * PMAC Destination Address Register 2 -+ ******************************************************************************/ -+ -+/* Destination Address to be inserted as a part of the Ethernet header. (31:0) */ -+#define LTQ_ES_PMAC_DA2_DA_31_0 (0xFFFFFFFFL) -+#define LTQ_ES_PMAC_DA2_DA_31_0_VAL(val) (((val) & 0xFFFFFFFFL) << 0) -+#define LTQ_ES_PMAC_DA2_DA_31_0_GET(val) ((((val) & LTQ_ES_PMAC_DA2_DA_31_0) >> 0) & 0xFFFFFFFFL) -+#define LTQ_ES_PMAC_DA2_DA_31_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_DA2_DA_31_0) | (((val) & 0xFFFFFFFFL) << 0)) -+ -+/******************************************************************************* -+ * PMAC VLAN Register -+ ******************************************************************************/ -+ -+/* Priority to be inserted as a part of VLAN tag (15:13) */ -+#define LTQ_ES_PMAC_VLAN_PRI (0x7 << 13) -+#define LTQ_ES_PMAC_VLAN_PRI_VAL(val) (((val) & 0x7) << 13) -+#define LTQ_ES_PMAC_VLAN_PRI_GET(val) ((((val) & LTQ_ES_PMAC_VLAN_PRI) >> 13) & 0x7) -+#define LTQ_ES_PMAC_VLAN_PRI_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_VLAN_PRI) | (((val) & 0x7) << 13)) -+/* CFI bit to be inserted as a part of VLAN tag (12) */ -+#define LTQ_ES_PMAC_VLAN_CFI (0x1 << 12) -+#define LTQ_ES_PMAC_VLAN_CFI_VAL(val) (((val) & 0x1) << 12) -+#define LTQ_ES_PMAC_VLAN_CFI_GET(val) ((((val) & LTQ_ES_PMAC_VLAN_CFI) >> 12) & 0x1) -+#define LTQ_ES_PMAC_VLAN_CFI_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_VLAN_CFI) | (((val) & 0x1) << 12)) -+/* VLAN ID to be inserted as a part of VLAN tag (11:0) */ -+#define LTQ_ES_PMAC_VLAN_VLAN_ID (0xfff) -+#define LTQ_ES_PMAC_VLAN_VLAN_ID_VAL(val) (((val) & 0xfff) << 0) -+#define LTQ_ES_PMAC_VLAN_VLAN_ID_GET(val) ((((val) & LTQ_ES_PMAC_VLAN_VLAN_ID) >> 0) & 0xfff) -+#define LTQ_ES_PMAC_VLAN_VLAN_ID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_VLAN_VLAN ID) | (((val) & 0xfff) << 0)) -+ -+/******************************************************************************* -+ * PMAC TX IPG Counter Register -+ ******************************************************************************/ -+ -+/* IPG Counter (7:0) */ -+#define LTQ_ES_PMAC_TX_IPG_IPG_CNT (0xff) -+#define LTQ_ES_PMAC_TX_IPG_IPG_CNT_VAL(val) (((val) & 0xff) << 0) -+#define LTQ_ES_PMAC_TX_IPG_IPG_CNT_GET(val) ((((val) & LTQ_ES_PMAC_TX_IPG_IPG_CNT) >> 0) & 0xff) -+#define LTQ_ES_PMAC_TX_IPG_IPG_CNT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_TX_IPG_IPG_CNT) | (((val) & 0xff) << 0)) -+ -+/******************************************************************************* -+ * PMAC RX IPG Counter Register -+ ******************************************************************************/ -+ -+/* IPG Counter (7:0) */ -+#define LTQ_ES_PMAC_RX_IPG_IPG_CNT (0xff) -+#define LTQ_ES_PMAC_RX_IPG_IPG_CNT_VAL(val) (((val) & 0xff) << 0) -+#define LTQ_ES_PMAC_RX_IPG_IPG_CNT_GET(val) ((((val) & LTQ_ES_PMAC_RX_IPG_IPG_CNT) >> 0) & 0xff) -+#define LTQ_ES_PMAC_RX_IPG_IPG_CNT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_RX_IPG_IPG_CNT) | (((val) & 0xff) << 0)) -+ -+/******************************************************************************* -+ * Address Table Control 0 Register -+ ******************************************************************************/ -+ -+/* Address [31:0] (31:0) */ -+#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0 (0xFFFFFFFFL) -+#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0_VAL(val) (((val) & 0xFFFFFFFFL) << 0) -+#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0) >> 0) & 0xFFFFFFFFL) -+#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0) | (((val) & 0xFFFFFFFFL) << 0)) -+ -+/******************************************************************************* -+ * Address Table Control 1 Register -+ ******************************************************************************/ -+ -+/* Port Map (22:20) */ -+#define LTQ_ES_ADR_TB_CTL1_REG_PMAP (0x7 << 20) -+#define LTQ_ES_ADR_TB_CTL1_REG_PMAP_VAL(val) (((val) & 0x7) << 20) -+#define LTQ_ES_ADR_TB_CTL1_REG_PMAP_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL1_REG_PMAP) >> 20) & 0x7) -+#define LTQ_ES_ADR_TB_CTL1_REG_PMAP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL1_REG_PMAP) | (((val) & 0x7) << 20)) -+/* FID group (17:16) */ -+#define LTQ_ES_ADR_TB_CTL1_REG_FID (0x3 << 16) -+#define LTQ_ES_ADR_TB_CTL1_REG_FID_VAL(val) (((val) & 0x3) << 16) -+#define LTQ_ES_ADR_TB_CTL1_REG_FID_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL1_REG_FID) >> 16) & 0x3) -+#define LTQ_ES_ADR_TB_CTL1_REG_FID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL1_REG_FID) | (((val) & 0x3) << 16)) -+/* Address [47:32] (15:0) */ -+#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32 (0xffff) -+#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32_VAL(val) (((val) & 0xffff) << 0) -+#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32) >> 0) & 0xffff) -+#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32) | (((val) & 0xffff) << 0)) -+ -+/******************************************************************************* -+ * Address Table Control 2 Register -+ ******************************************************************************/ -+ -+/* Command (22:20) */ -+#define LTQ_ES_ADR_TB_CTL2_REG_CMD (0x7 << 20) -+#define LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(val) (((val) & 0x7) << 20) -+#define LTQ_ES_ADR_TB_CTL2_REG_CMD_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_CMD) >> 20) & 0x7) -+#define LTQ_ES_ADR_TB_CTL2_REG_CMD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_CMD) | (((val) & 0x7) << 20)) -+/* Access Control (19:16) */ -+#define LTQ_ES_ADR_TB_CTL2_REG_AC (0xf << 16) -+#define LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(val) (((val) & 0xf) << 16) -+#define LTQ_ES_ADR_TB_CTL2_REG_AC_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_AC) >> 16) & 0xf) -+#define LTQ_ES_ADR_TB_CTL2_REG_AC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_AC) | (((val) & 0xf) << 16)) -+/* Info Type: Static address (12) */ -+#define LTQ_ES_ADR_TB_CTL2_REG_INFOT (0x1 << 12) -+#define LTQ_ES_ADR_TB_CTL2_REG_INFOT_VAL(val) (((val) & 0x1) << 12) -+#define LTQ_ES_ADR_TB_CTL2_REG_INFOT_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_INFOT) >> 12) & 0x1) -+#define LTQ_ES_ADR_TB_CTL2_REG_INFOT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_INFOT) | (((val) & 0x1) << 12)) -+/* Info_Ctrl/Age Timer (10:0) */ -+#define LTQ_ES_ADR_TB_CTL2_REG_ITAT (0x7ff) -+#define LTQ_ES_ADR_TB_CTL2_REG_ITAT_VAL(val) (((val) & 0x7ff) << 0) -+#define LTQ_ES_ADR_TB_CTL2_REG_ITAT_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_ITAT) >> 0) & 0x7ff) -+#define LTQ_ES_ADR_TB_CTL2_REG_ITAT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_ITAT) | (((val) & 0x7ff) << 0)) -+ -+/******************************************************************************* -+ * Address Table Status 0 Register -+ ******************************************************************************/ -+ -+/* Address [31:0] (31:0) */ -+#define LTQ_ES_ADR_TB_ST0_REG_ADDRS31_0 (0xFFFFFFFFL) -+#define LTQ_ES_ADR_TB_ST0_REG_ADDRS31_0_GET(val) ((((val) & LTQ_ES_ADR_TB_ST0_REG_ADDRS31_0) >> 0) & 0xFFFFFFFFL) -+ -+/******************************************************************************* -+ * Address Table Status 1 Register -+ ******************************************************************************/ -+ -+/* Port Map (22:20) */ -+#define LTQ_ES_ADR_TB_ST1_REG_PMAPS (0x7 << 20) -+#define LTQ_ES_ADR_TB_ST1_REG_PMAPS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST1_REG_PMAPS) >> 20) & 0x7) -+/* FID group (17:16) */ -+#define LTQ_ES_ADR_TB_ST1_REG_FIDS (0x3 << 16) -+#define LTQ_ES_ADR_TB_ST1_REG_FIDS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST1_REG_FIDS) >> 16) & 0x3) -+/* Address [47:32] (15:0) */ -+#define LTQ_ES_ADR_TB_ST1_REG_ADDRS47_32 (0xffff) -+#define LTQ_ES_ADR_TB_ST1_REG_ADDRS47_32_GET(val) ((((val) & LTQ_ES_ADR_TB_ST1_REG_ADDRS47_32) >> 0) & 0xffff) -+ -+/******************************************************************************* -+ * Address Table Status 2 Register -+ ******************************************************************************/ -+ -+/* Busy (31) */ -+#define LTQ_ES_ADR_TB_ST2_REG_BUSY (0x1 << 31) -+#define LTQ_ES_ADR_TB_ST2_REG_BUSY_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_BUSY) >> 31) & 0x1) -+/* Result (30:28) */ -+#define LTQ_ES_ADR_TB_ST2_REG_RSLT (0x7 << 28) -+#define LTQ_ES_ADR_TB_ST2_REG_RSLT_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_RSLT) >> 28) & 0x7) -+/* Command (22:20) */ -+#define LTQ_ES_ADR_TB_ST2_REG_CMD (0x7 << 20) -+#define LTQ_ES_ADR_TB_ST2_REG_CMD_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_CMD) >> 20) & 0x7) -+/* Access Control (19:16) */ -+#define LTQ_ES_ADR_TB_ST2_REG_AC (0xf << 16) -+#define LTQ_ES_ADR_TB_ST2_REG_AC_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_AC) >> 16) & 0xf) -+/* Bad Status (14) */ -+#define LTQ_ES_ADR_TB_ST2_REG_BAD (0x1 << 14) -+#define LTQ_ES_ADR_TB_ST2_REG_BAD_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_BAD) >> 14) & 0x1) -+/* Occupy (13) */ -+#define LTQ_ES_ADR_TB_ST2_REG_OCP (0x1 << 13) -+#define LTQ_ES_ADR_TB_ST2_REG_OCP_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_OCP) >> 13) & 0x1) -+/* Info Type: Static address (12) */ -+#define LTQ_ES_ADR_TB_ST2_REG_INFOTS (0x1 << 12) -+#define LTQ_ES_ADR_TB_ST2_REG_INFOTS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_INFOTS) >> 12) & 0x1) -+/* Info_Ctrl/Age Timer Status (10:0) */ -+#define LTQ_ES_ADR_TB_ST2_REG_ITATS (0x7ff) -+#define LTQ_ES_ADR_TB_ST2_REG_ITATS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_ITATS) >> 0) & 0x7ff) -+ -+/******************************************************************************* -+ * RMON Counter Control Register -+ ******************************************************************************/ -+ -+/* Reserved (31:12) */ -+#define LTQ_ES_RMON_CTL_REG_RES (0xfffff << 12) -+#define LTQ_ES_RMON_CTL_REG_RES_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_RES) >> 12) & 0xfffff) -+/* Busy/Access Start (11) */ -+#define LTQ_ES_RMON_CTL_REG_BAS (0x1 << 11) -+#define LTQ_ES_RMON_CTL_REG_BAS_VAL(val) (((val) & 0x1) << 11) -+#define LTQ_ES_RMON_CTL_REG_BAS_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_BAS) >> 11) & 0x1) -+#define LTQ_ES_RMON_CTL_REG_BAS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_BAS) | (((val) & 0x1) << 11)) -+/* Command for access counter (10:9) */ -+#define LTQ_ES_RMON_CTL_REG_CAC (0x3 << 9) -+#define LTQ_ES_RMON_CTL_REG_CAC_VAL(val) (((val) & 0x3) << 9) -+#define LTQ_ES_RMON_CTL_REG_CAC_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_CAC) >> 9) & 0x3) -+#define LTQ_ES_RMON_CTL_REG_CAC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_CAC) | (((val) & 0x3) << 9)) -+/* Port (8:6) */ -+#define LTQ_ES_RMON_CTL_REG_PORTC (0x7 << 6) -+#define LTQ_ES_RMON_CTL_REG_PORTC_VAL(val) (((val) & 0x7) << 6) -+#define LTQ_ES_RMON_CTL_REG_PORTC_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_PORTC) >> 6) & 0x7) -+#define LTQ_ES_RMON_CTL_REG_PORTC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_PORTC) | (((val) & 0x7) << 6)) -+/* Counter Offset (5:0) */ -+#define LTQ_ES_RMON_CTL_REG_OFFSET (0x3f) -+#define LTQ_ES_RMON_CTL_REG_OFFSET_VAL(val) (((val) & 0x3f) << 0) -+#define LTQ_ES_RMON_CTL_REG_OFFSET_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_OFFSET) >> 0) & 0x3f) -+#define LTQ_ES_RMON_CTL_REG_OFFSET_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_OFFSET) | (((val) & 0x3f) << 0)) -+ -+/******************************************************************************* -+ * RMON Counter Status Register -+ ******************************************************************************/ -+ -+/* Counter [31:0] or Counter[63:32] for byte count (31:0) */ -+#define LTQ_ES_RMON_ST_REG_COUNTER (0xFFFFFFFFL) -+#define LTQ_ES_RMON_ST_REG_COUNTER_GET(val) ((((val) & LTQ_ES_RMON_ST_REG_COUNTER) >> 0) & 0xFFFFFFFFL) -+ -+/******************************************************************************* -+ * MDIO Indirect Access Control -+ ******************************************************************************/ -+ -+/* The Write Data to the MDIO register (31:16) */ -+#define LTQ_ES_MDIO_CTL_REG_WD (0xffff << 16) -+#define LTQ_ES_MDIO_CTL_REG_WD_VAL(val) (((val) & 0xffff) << 16) -+#define LTQ_ES_MDIO_CTL_REG_WD_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_WD) >> 16) & 0xffff) -+#define LTQ_ES_MDIO_CTL_REG_WD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_WD) | (((val) & 0xffff) << 16)) -+/* Busy state (15) */ -+#define LTQ_ES_MDIO_CTL_REG_MBUSY (0x1 << 15) -+#define LTQ_ES_MDIO_CTL_REG_MBUSY_VAL(val) (((val) & 0x1) << 15) -+#define LTQ_ES_MDIO_CTL_REG_MBUSY_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_MBUSY) >> 15) & 0x1) -+#define LTQ_ES_MDIO_CTL_REG_MBUSY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_MBUSY) | (((val) & 0x1) << 15)) -+/* Reserved (14:12) */ -+#define LTQ_ES_MDIO_CTL_REG_RES (0x7 << 12) -+#define LTQ_ES_MDIO_CTL_REG_RES_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_RES) >> 12) & 0x7) -+/* Operation Code (11:10) */ -+#define LTQ_ES_MDIO_CTL_REG_OP (0x3 << 10) -+#define LTQ_ES_MDIO_CTL_REG_OP_VAL(val) (((val) & 0x3) << 10) -+#define LTQ_ES_MDIO_CTL_REG_OP_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_OP) >> 10) & 0x3) -+#define LTQ_ES_MDIO_CTL_REG_OP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_OP) | (((val) & 0x3) << 10)) -+/* PHY Address (9:5) */ -+#define LTQ_ES_MDIO_CTL_REG_PHYAD (0x1f << 5) -+#define LTQ_ES_MDIO_CTL_REG_PHYAD_VAL(val) (((val) & 0x1f) << 5) -+#define LTQ_ES_MDIO_CTL_REG_PHYAD_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_PHYAD) >> 5) & 0x1f) -+#define LTQ_ES_MDIO_CTL_REG_PHYAD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_PHYAD) | (((val) & 0x1f) << 5)) -+/* Register Address (4:0) */ -+#define LTQ_ES_MDIO_CTL_REG_REGAD (0x1f) -+#define LTQ_ES_MDIO_CTL_REG_REGAD_VAL(val) (((val) & 0x1f) << 0) -+#define LTQ_ES_MDIO_CTL_REG_REGAD_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_REGAD) >> 0) & 0x1f) -+#define LTQ_ES_MDIO_CTL_REG_REGAD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_REGAD) | (((val) & 0x1f) << 0)) -+ -+/******************************************************************************* -+ * MDIO Indirect Read Data -+ ******************************************************************************/ -+ -+/* Reserved (31:16) */ -+#define LTQ_ES_MDIO_DATA_REG_RES (0xffff << 16) -+#define LTQ_ES_MDIO_DATA_REG_RES_GET(val) ((((val) & LTQ_ES_MDIO_DATA_REG_RES) >> 16) & 0xffff) -+/* The Read Data (15:0) */ -+#define LTQ_ES_MDIO_DATA_REG_RD (0xffff) -+#define LTQ_ES_MDIO_DATA_REG_RD_GET(val) ((((val) & LTQ_ES_MDIO_DATA_REG_RD) >> 0) & 0xffff) -+ -+/******************************************************************************* -+ * Type Filter Action -+ ******************************************************************************/ -+ -+/* Destination Queue for Type Filter 7 (31:30) */ -+#define LTQ_ES_TP_FLT_ACT_REG_QATF7 (0x3 << 30) -+#define LTQ_ES_TP_FLT_ACT_REG_QATF7_VAL(val) (((val) & 0x3) << 30) -+#define LTQ_ES_TP_FLT_ACT_REG_QATF7_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QATF7) >> 30) & 0x3) -+#define LTQ_ES_TP_FLT_ACT_REG_QATF7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QATF7) | (((val) & 0x3) << 30)) -+/* Destination Queue for Type Filter 6 (29:28) */ -+#define LTQ_ES_TP_FLT_ACT_REG_QATF6 (0x3 << 28) -+#define LTQ_ES_TP_FLT_ACT_REG_QATF6_VAL(val) (((val) & 0x3) << 28) -+#define LTQ_ES_TP_FLT_ACT_REG_QATF6_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QATF6) >> 28) & 0x3) -+#define LTQ_ES_TP_FLT_ACT_REG_QATF6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QATF6) | (((val) & 0x3) << 28)) -+/* Destination Queue for Type Filter 5 (27:26) */ -+#define LTQ_ES_TP_FLT_ACT_REG_QTF5 (0x3 << 26) -+#define LTQ_ES_TP_FLT_ACT_REG_QTF5_VAL(val) (((val) & 0x3) << 26) -+#define LTQ_ES_TP_FLT_ACT_REG_QTF5_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF5) >> 26) & 0x3) -+#define LTQ_ES_TP_FLT_ACT_REG_QTF5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF5) | (((val) & 0x3) << 26)) -+/* Destination Queue for Type Filter 4 (25:24) */ -+#define LTQ_ES_TP_FLT_ACT_REG_QTF4 (0x3 << 24) -+#define LTQ_ES_TP_FLT_ACT_REG_QTF4_VAL(val) (((val) & 0x3) << 24) -+#define LTQ_ES_TP_FLT_ACT_REG_QTF4_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF4) >> 24) & 0x3) -+#define LTQ_ES_TP_FLT_ACT_REG_QTF4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF4) | (((val) & 0x3) << 24)) -+/* Destination Queue for Type Filter 3 (23:22) */ -+#define LTQ_ES_TP_FLT_ACT_REG_QTF3 (0x3 << 22) -+#define LTQ_ES_TP_FLT_ACT_REG_QTF3_VAL(val) (((val) & 0x3) << 22) -+#define LTQ_ES_TP_FLT_ACT_REG_QTF3_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF3) >> 22) & 0x3) -+#define LTQ_ES_TP_FLT_ACT_REG_QTF3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF3) | (((val) & 0x3) << 22)) -+/* Destination Queue for Type Filter 2 (21:20) */ -+#define LTQ_ES_TP_FLT_ACT_REG_QTF2 (0x3 << 20) -+#define LTQ_ES_TP_FLT_ACT_REG_QTF2_VAL(val) (((val) & 0x3) << 20) -+#define LTQ_ES_TP_FLT_ACT_REG_QTF2_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF2) >> 20) & 0x3) -+#define LTQ_ES_TP_FLT_ACT_REG_QTF2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF2) | (((val) & 0x3) << 20)) -+/* Destination Queue for Type Filter 1 (19:18) */ -+#define LTQ_ES_TP_FLT_ACT_REG_QTF1 (0x3 << 18) -+#define LTQ_ES_TP_FLT_ACT_REG_QTF1_VAL(val) (((val) & 0x3) << 18) -+#define LTQ_ES_TP_FLT_ACT_REG_QTF1_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF1) >> 18) & 0x3) -+#define LTQ_ES_TP_FLT_ACT_REG_QTF1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF1) | (((val) & 0x3) << 18)) -+/* Destination Queue for Type Filter 0 (17:16) */ -+#define LTQ_ES_TP_FLT_ACT_REG_QTF0 (0x3 << 16) -+#define LTQ_ES_TP_FLT_ACT_REG_QTF0_VAL(val) (((val) & 0x3) << 16) -+#define LTQ_ES_TP_FLT_ACT_REG_QTF0_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF0) >> 16) & 0x3) -+#define LTQ_ES_TP_FLT_ACT_REG_QTF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF0) | (((val) & 0x3) << 16)) -+/* Action for Type Filter 7 (15:14) */ -+#define LTQ_ES_TP_FLT_ACT_REG_ATF7 (0x3 << 14) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF7_VAL(val) (((val) & 0x3) << 14) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF7_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF7) >> 14) & 0x3) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF7) | (((val) & 0x3) << 14)) -+/* Action for Type Filter 6 (13:12) */ -+#define LTQ_ES_TP_FLT_ACT_REG_ATF6 (0x3 << 12) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF6_VAL(val) (((val) & 0x3) << 12) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF6_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF6) >> 12) & 0x3) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF6) | (((val) & 0x3) << 12)) -+/* Action for Type Filter 5 (11:10) */ -+#define LTQ_ES_TP_FLT_ACT_REG_ATF5 (0x3 << 10) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF5_VAL(val) (((val) & 0x3) << 10) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF5_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF5) >> 10) & 0x3) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF5) | (((val) & 0x3) << 10)) -+/* Action for Type Filter 4 (9:8) */ -+#define LTQ_ES_TP_FLT_ACT_REG_ATF4 (0x3 << 8) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF4_VAL(val) (((val) & 0x3) << 8) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF4_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF4) >> 8) & 0x3) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF4) | (((val) & 0x3) << 8)) -+/* Action for Type Filter 3 (7:6) */ -+#define LTQ_ES_TP_FLT_ACT_REG_ATF3 (0x3 << 6) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF3_VAL(val) (((val) & 0x3) << 6) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF3_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF3) >> 6) & 0x3) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF3) | (((val) & 0x3) << 6)) -+/* Action for Type Filter 2 (5:4) */ -+#define LTQ_ES_TP_FLT_ACT_REG_ATF2 (0x3 << 4) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF2_VAL(val) (((val) & 0x3) << 4) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF2_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF2) >> 4) & 0x3) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF2) | (((val) & 0x3) << 4)) -+/* Action for Type Filter 1 (3:2) */ -+#define LTQ_ES_TP_FLT_ACT_REG_ATF1 (0x3 << 2) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF1_VAL(val) (((val) & 0x3) << 2) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF1_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF1) >> 2) & 0x3) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF1) | (((val) & 0x3) << 2)) -+/* Action for Type Filter 0 (1:0) */ -+#define LTQ_ES_TP_FLT_ACT_REG_ATF0 (0x3) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF0_VAL(val) (((val) & 0x3) << 0) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF0_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF0) >> 0) & 0x3) -+#define LTQ_ES_TP_FLT_ACT_REG_ATF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF0) | (((val) & 0x3) << 0)) -+ -+/******************************************************************************* -+ * Protocol Filter Action -+ ******************************************************************************/ -+ -+/* Action for Protocol Filter 7 (15:14) */ -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7 (0x3 << 14) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7_VAL(val) (((val) & 0x3) << 14) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF7) >> 14) & 0x3) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF7) | (((val) & 0x3) << 14)) -+/* Action for Protocol Filter 6 (13:12) */ -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6 (0x3 << 12) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6_VAL(val) (((val) & 0x3) << 12) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF6) >> 12) & 0x3) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF6) | (((val) & 0x3) << 12)) -+/* Action for Protocol Filter 5 (11:10) */ -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5 (0x3 << 10) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5_VAL(val) (((val) & 0x3) << 10) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF5) >> 10) & 0x3) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF5) | (((val) & 0x3) << 10)) -+/* Action for Protocol Filter 4 (9:8) */ -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4 (0x3 << 8) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4_VAL(val) (((val) & 0x3) << 8) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF4) >> 8) & 0x3) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF4) | (((val) & 0x3) << 8)) -+/* Action for Protocol Filter 3 (7:6) */ -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3 (0x3 << 6) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3_VAL(val) (((val) & 0x3) << 6) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF3) >> 6) & 0x3) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF3) | (((val) & 0x3) << 6)) -+/* Action for Protocol Filter 2 (5:4) */ -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2 (0x3 << 4) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2_VAL(val) (((val) & 0x3) << 4) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF2) >> 4) & 0x3) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF2) | (((val) & 0x3) << 4)) -+/* Action for Protocol Filter 1 (3:2) */ -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1 (0x3 << 2) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1_VAL(val) (((val) & 0x3) << 2) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF1) >> 2) & 0x3) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF1) | (((val) & 0x3) << 2)) -+/* Action for Protocol Filter 0 (1:0) */ -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0 (0x3) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0_VAL(val) (((val) & 0x3) << 0) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF0) >> 0) & 0x3) -+#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF0) | (((val) & 0x3) << 0)) -+ -+/******************************************************************************* -+ * VLAN Filter 0 -+ ******************************************************************************/ -+ -+/* Res (31:24) */ -+#define LTQ_ES_VLAN_FLT0_REG_RES (0xff << 24) -+#define LTQ_ES_VLAN_FLT0_REG_RES_VAL(val) (((val) & 0xff) << 24) -+#define LTQ_ES_VLAN_FLT0_REG_RES_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_RES) >> 24) & 0xff) -+#define LTQ_ES_VLAN_FLT0_REG_RES_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_RES) | (((val) & 0xff) << 24)) -+/* FID (23:22) */ -+#define LTQ_ES_VLAN_FLT0_REG_FID (0x3 << 22) -+#define LTQ_ES_VLAN_FLT0_REG_FID_VAL(val) (((val) & 0x3) << 22) -+#define LTQ_ES_VLAN_FLT0_REG_FID_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_FID) >> 22) & 0x3) -+#define LTQ_ES_VLAN_FLT0_REG_FID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_FID) | (((val) & 0x3) << 22)) -+/* Tagged Member (21:19) */ -+#define LTQ_ES_VLAN_FLT0_REG_TM (0x7 << 19) -+#define LTQ_ES_VLAN_FLT0_REG_TM_VAL(val) (((val) & 0x7) << 19) -+#define LTQ_ES_VLAN_FLT0_REG_TM_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_TM) >> 19) & 0x7) -+#define LTQ_ES_VLAN_FLT0_REG_TM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_TM) | (((val) & 0x7) << 19)) -+/* Member (18:16) */ -+#define LTQ_ES_VLAN_FLT0_REG_M (0x7 << 16) -+#define LTQ_ES_VLAN_FLT0_REG_M_VAL(val) (((val) & 0x7) << 16) -+#define LTQ_ES_VLAN_FLT0_REG_M_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_M) >> 16) & 0x7) -+#define LTQ_ES_VLAN_FLT0_REG_M_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_M) | (((val) & 0x7) << 16)) -+/* VLAN_Valid (15) */ -+#define LTQ_ES_VLAN_FLT0_REG_VV (0x1 << 15) -+#define LTQ_ES_VLAN_FLT0_REG_VV_VAL(val) (((val) & 0x1) << 15) -+#define LTQ_ES_VLAN_FLT0_REG_VV_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_VV) >> 15) & 0x1) -+#define LTQ_ES_VLAN_FLT0_REG_VV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_VV) | (((val) & 0x1) << 15)) -+/* VLAN PRI (14:12) */ -+#define LTQ_ES_VLAN_FLT0_REG_VP (0x7 << 12) -+#define LTQ_ES_VLAN_FLT0_REG_VP_VAL(val) (((val) & 0x7) << 12) -+#define LTQ_ES_VLAN_FLT0_REG_VP_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_VP) >> 12) & 0x7) -+#define LTQ_ES_VLAN_FLT0_REG_VP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_VP) | (((val) & 0x7) << 12)) -+/* VID (11:0) */ -+#define LTQ_ES_VLAN_FLT0_REG_VID (0xfff) -+#define LTQ_ES_VLAN_FLT0_REG_VID_VAL(val) (((val) & 0xfff) << 0) -+#define LTQ_ES_VLAN_FLT0_REG_VID_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_VID) >> 0) & 0xfff) -+#define LTQ_ES_VLAN_FLT0_REG_VID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_VID) | (((val) & 0xfff) << 0)) -+ -+/******************************************************************************* -+ * Type Filter 10 -+ ******************************************************************************/ -+ -+/* Value 1 Compared with Ether-Type (31:16) */ -+#define LTQ_ES_TP_FLT10_REG_VCET1 (0xffff << 16) -+#define LTQ_ES_TP_FLT10_REG_VCET1_VAL(val) (((val) & 0xffff) << 16) -+#define LTQ_ES_TP_FLT10_REG_VCET1_GET(val) ((((val) & LTQ_ES_TP_FLT10_REG_VCET1) >> 16) & 0xffff) -+#define LTQ_ES_TP_FLT10_REG_VCET1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT10_REG_VCET1) | (((val) & 0xffff) << 16)) -+/* Value 0 Compared with Ether-Type (15:0) */ -+#define LTQ_ES_TP_FLT10_REG_VCET0 (0xffff) -+#define LTQ_ES_TP_FLT10_REG_VCET0_VAL(val) (((val) & 0xffff) << 0) -+#define LTQ_ES_TP_FLT10_REG_VCET0_GET(val) ((((val) & LTQ_ES_TP_FLT10_REG_VCET0) >> 0) & 0xffff) -+#define LTQ_ES_TP_FLT10_REG_VCET0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT10_REG_VCET0) | (((val) & 0xffff) << 0)) -+ -+/******************************************************************************* -+ * DiffServMapping 0 -+ ******************************************************************************/ -+ -+/* Priority Queue F (31:30) */ -+#define LTQ_ES_DFSRV_MAP0_REG_PQF (0x3 << 30) -+#define LTQ_ES_DFSRV_MAP0_REG_PQF_VAL(val) (((val) & 0x3) << 30) -+#define LTQ_ES_DFSRV_MAP0_REG_PQF_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQF) >> 30) & 0x3) -+#define LTQ_ES_DFSRV_MAP0_REG_PQF_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQF) | (((val) & 0x3) << 30)) -+/* Priority Queue E (29:28) */ -+#define LTQ_ES_DFSRV_MAP0_REG_PQE (0x3 << 28) -+#define LTQ_ES_DFSRV_MAP0_REG_PQE_VAL(val) (((val) & 0x3) << 28) -+#define LTQ_ES_DFSRV_MAP0_REG_PQE_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQE) >> 28) & 0x3) -+#define LTQ_ES_DFSRV_MAP0_REG_PQE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQE) | (((val) & 0x3) << 28)) -+/* Priority Queue D (27:26) */ -+#define LTQ_ES_DFSRV_MAP0_REG_PQD (0x3 << 26) -+#define LTQ_ES_DFSRV_MAP0_REG_PQD_VAL(val) (((val) & 0x3) << 26) -+#define LTQ_ES_DFSRV_MAP0_REG_PQD_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQD) >> 26) & 0x3) -+#define LTQ_ES_DFSRV_MAP0_REG_PQD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQD) | (((val) & 0x3) << 26)) -+/* Priority Queue C (25:24) */ -+#define LTQ_ES_DFSRV_MAP0_REG_PQC (0x3 << 24) -+#define LTQ_ES_DFSRV_MAP0_REG_PQC_VAL(val) (((val) & 0x3) << 24) -+#define LTQ_ES_DFSRV_MAP0_REG_PQC_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQC) >> 24) & 0x3) -+#define LTQ_ES_DFSRV_MAP0_REG_PQC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQC) | (((val) & 0x3) << 24)) -+/* Priority Queue B (23:22) */ -+#define LTQ_ES_DFSRV_MAP0_REG_PQB (0x3 << 22) -+#define LTQ_ES_DFSRV_MAP0_REG_PQB_VAL(val) (((val) & 0x3) << 22) -+#define LTQ_ES_DFSRV_MAP0_REG_PQB_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQB) >> 22) & 0x3) -+#define LTQ_ES_DFSRV_MAP0_REG_PQB_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQB) | (((val) & 0x3) << 22)) -+/* Priority Queue A (21:20) */ -+#define LTQ_ES_DFSRV_MAP0_REG_PQA (0x3 << 20) -+#define LTQ_ES_DFSRV_MAP0_REG_PQA_VAL(val) (((val) & 0x3) << 20) -+#define LTQ_ES_DFSRV_MAP0_REG_PQA_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQA) >> 20) & 0x3) -+#define LTQ_ES_DFSRV_MAP0_REG_PQA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQA) | (((val) & 0x3) << 20)) -+/* Priority Queue 9 (19:18) */ -+#define LTQ_ES_DFSRV_MAP0_REG_PQ9 (0x3 << 18) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ9_VAL(val) (((val) & 0x3) << 18) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ9_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ9) >> 18) & 0x3) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ9_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ9) | (((val) & 0x3) << 18)) -+/* Priority Queue 8 (17:16) */ -+#define LTQ_ES_DFSRV_MAP0_REG_PQ8 (0x3 << 16) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ8_VAL(val) (((val) & 0x3) << 16) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ8_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ8) >> 16) & 0x3) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ8_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ8) | (((val) & 0x3) << 16)) -+/* Priority Queue 7 (15:14) */ -+#define LTQ_ES_DFSRV_MAP0_REG_PQ7 (0x3 << 14) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ7_VAL(val) (((val) & 0x3) << 14) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ7_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ7) >> 14) & 0x3) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ7) | (((val) & 0x3) << 14)) -+/* Priority Queue 6 (13:12) */ -+#define LTQ_ES_DFSRV_MAP0_REG_PQ6 (0x3 << 12) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ6_VAL(val) (((val) & 0x3) << 12) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ6_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ6) >> 12) & 0x3) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ6) | (((val) & 0x3) << 12)) -+/* Priority Queue 5 (11:10) */ -+#define LTQ_ES_DFSRV_MAP0_REG_PQ5 (0x3 << 10) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ5_VAL(val) (((val) & 0x3) << 10) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ5_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ5) >> 10) & 0x3) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ5) | (((val) & 0x3) << 10)) -+/* Priority Queue 4 (9:8) */ -+#define LTQ_ES_DFSRV_MAP0_REG_PQ4 (0x3 << 8) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ4_VAL(val) (((val) & 0x3) << 8) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ4_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ4) >> 8) & 0x3) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ4) | (((val) & 0x3) << 8)) -+/* Priority Queue 3 (7:6) */ -+#define LTQ_ES_DFSRV_MAP0_REG_PQ3 (0x3 << 6) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ3_VAL(val) (((val) & 0x3) << 6) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ3_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ3) >> 6) & 0x3) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ3) | (((val) & 0x3) << 6)) -+/* Priority Queue 2 (5:4) */ -+#define LTQ_ES_DFSRV_MAP0_REG_PQ2 (0x3 << 4) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ2_VAL(val) (((val) & 0x3) << 4) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ2_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ2) >> 4) & 0x3) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ2) | (((val) & 0x3) << 4)) -+/* Priority Queue 1 (3:2) */ -+#define LTQ_ES_DFSRV_MAP0_REG_PQ1 (0x3 << 2) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ1_VAL(val) (((val) & 0x3) << 2) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ1_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ1) >> 2) & 0x3) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ1) | (((val) & 0x3) << 2)) -+/* Priority Queue 0 (1:0) */ -+#define LTQ_ES_DFSRV_MAP0_REG_PQ0 (0x3) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ0_VAL(val) (((val) & 0x3) << 0) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ0_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ0) >> 0) & 0x3) -+#define LTQ_ES_DFSRV_MAP0_REG_PQ0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ0) | (((val) & 0x3) << 0)) -+ -+/******************************************************************************* -+ * DiffServMapping 1 -+ ******************************************************************************/ -+ -+/* Priority Queue 1F (31:30) */ -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1F (0x3 << 30) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1F_VAL(val) (((val) & 0x3) << 30) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1F_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1F) >> 30) & 0x3) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1F_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1F) | (((val) & 0x3) << 30)) -+/* Priority Queue 1E (29:28) */ -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1E (0x3 << 28) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1E_VAL(val) (((val) & 0x3) << 28) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1E_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1E) >> 28) & 0x3) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1E_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1E) | (((val) & 0x3) << 28)) -+/* Priority Queue 1D (27:26) */ -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1D (0x3 << 26) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1D_VAL(val) (((val) & 0x3) << 26) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1D_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1D) >> 26) & 0x3) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1D_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1D) | (((val) & 0x3) << 26)) -+/* Priority Queue 1C (25:24) */ -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1C (0x3 << 24) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1C_VAL(val) (((val) & 0x3) << 24) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1C_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1C) >> 24) & 0x3) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1C_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1C) | (((val) & 0x3) << 24)) -+/* Priority Queue 1B (23:22) */ -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1B (0x3 << 22) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1B_VAL(val) (((val) & 0x3) << 22) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1B_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1B) >> 22) & 0x3) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1B) | (((val) & 0x3) << 22)) -+/* Priority Queue 1A (21:20) */ -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1A (0x3 << 20) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1A_VAL(val) (((val) & 0x3) << 20) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1A_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1A) >> 20) & 0x3) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ1A_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1A) | (((val) & 0x3) << 20)) -+/* Priority Queue 19 (19:18) */ -+#define LTQ_ES_DFSRV_MAP1_REG_PQ19 (0x3 << 18) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ19_VAL(val) (((val) & 0x3) << 18) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ19_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ19) >> 18) & 0x3) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ19_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ19) | (((val) & 0x3) << 18)) -+/* Priority Queue 18 (17:16) */ -+#define LTQ_ES_DFSRV_MAP1_REG_PQ18 (0x3 << 16) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ18_VAL(val) (((val) & 0x3) << 16) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ18_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ18) >> 16) & 0x3) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ18_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ18) | (((val) & 0x3) << 16)) -+/* Priority Queue 17 (15:14) */ -+#define LTQ_ES_DFSRV_MAP1_REG_PQ17 (0x3 << 14) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ17_VAL(val) (((val) & 0x3) << 14) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ17_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ17) >> 14) & 0x3) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ17_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ17) | (((val) & 0x3) << 14)) -+/* Priority Queue 16 (13:12) */ -+#define LTQ_ES_DFSRV_MAP1_REG_PQ16 (0x3 << 12) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ16_VAL(val) (((val) & 0x3) << 12) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ16_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ16) >> 12) & 0x3) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ16_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ16) | (((val) & 0x3) << 12)) -+/* Priority Queue 15 (11:10) */ -+#define LTQ_ES_DFSRV_MAP1_REG_PQ15 (0x3 << 10) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ15_VAL(val) (((val) & 0x3) << 10) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ15_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ15) >> 10) & 0x3) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ15_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ15) | (((val) & 0x3) << 10)) -+/* Priority Queue 14 (9:8) */ -+#define LTQ_ES_DFSRV_MAP1_REG_PQ14 (0x3 << 8) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ14_VAL(val) (((val) & 0x3) << 8) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ14_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ14) >> 8) & 0x3) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ14_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ14) | (((val) & 0x3) << 8)) -+/* Priority Queue 13 (7:6) */ -+#define LTQ_ES_DFSRV_MAP1_REG_PQ13 (0x3 << 6) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ13_VAL(val) (((val) & 0x3) << 6) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ13_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ13) >> 6) & 0x3) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ13_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ13) | (((val) & 0x3) << 6)) -+/* Priority Queue 12 (5:4) */ -+#define LTQ_ES_DFSRV_MAP1_REG_PQ12 (0x3 << 4) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ12_VAL(val) (((val) & 0x3) << 4) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ12_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ12) >> 4) & 0x3) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ12_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ12) | (((val) & 0x3) << 4)) -+/* Priority Queue 11 (3:2) */ -+#define LTQ_ES_DFSRV_MAP1_REG_PQ11 (0x3 << 2) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ11_VAL(val) (((val) & 0x3) << 2) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ11_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ11) >> 2) & 0x3) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ11_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ11) | (((val) & 0x3) << 2)) -+/* Priority Queue 10 (1:0) */ -+#define LTQ_ES_DFSRV_MAP1_REG_PQ10 (0x3) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ10_VAL(val) (((val) & 0x3) << 0) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ10_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ10) >> 0) & 0x3) -+#define LTQ_ES_DFSRV_MAP1_REG_PQ10_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ10) | (((val) & 0x3) << 0)) -+ -+/******************************************************************************* -+ * DiffServMapping 2 -+ ******************************************************************************/ -+ -+/* Priority Queue 2F (31:30) */ -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2F (0x3 << 30) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2F_VAL(val) (((val) & 0x3) << 30) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2F_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2F) >> 30) & 0x3) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2F_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2F) | (((val) & 0x3) << 30)) -+/* Priority Queue 2E (29:28) */ -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2E (0x3 << 28) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2E_VAL(val) (((val) & 0x3) << 28) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2E_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2E) >> 28) & 0x3) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2E_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2E) | (((val) & 0x3) << 28)) -+/* Priority Queue 2D (27:26) */ -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2D (0x3 << 26) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2D_VAL(val) (((val) & 0x3) << 26) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2D_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2D) >> 26) & 0x3) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2D_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2D) | (((val) & 0x3) << 26)) -+/* Priority Queue 2C (25:24) */ -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2C (0x3 << 24) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2C_VAL(val) (((val) & 0x3) << 24) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2C_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2C) >> 24) & 0x3) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2C_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2C) | (((val) & 0x3) << 24)) -+/* Priority Queue 2B (23:22) */ -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2B (0x3 << 22) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2B_VAL(val) (((val) & 0x3) << 22) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2B_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2B) >> 22) & 0x3) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2B) | (((val) & 0x3) << 22)) -+/* Priority Queue 2A (21:20) */ -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2A (0x3 << 20) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2A_VAL(val) (((val) & 0x3) << 20) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2A_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2A) >> 20) & 0x3) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ2A_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2A) | (((val) & 0x3) << 20)) -+/* Priority Queue 29 (19:18) */ -+#define LTQ_ES_DFSRV_MAP2_REG_PQ29 (0x3 << 18) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ29_VAL(val) (((val) & 0x3) << 18) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ29_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ29) >> 18) & 0x3) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ29_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ29) | (((val) & 0x3) << 18)) -+/* Priority Queue 28 (17:16) */ -+#define LTQ_ES_DFSRV_MAP2_REG_PQ28 (0x3 << 16) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ28_VAL(val) (((val) & 0x3) << 16) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ28_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ28) >> 16) & 0x3) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ28_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ28) | (((val) & 0x3) << 16)) -+/* Priority Queue 27 (15:14) */ -+#define LTQ_ES_DFSRV_MAP2_REG_PQ27 (0x3 << 14) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ27_VAL(val) (((val) & 0x3) << 14) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ27_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ27) >> 14) & 0x3) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ27_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ27) | (((val) & 0x3) << 14)) -+/* Priority Queue 26 (13:12) */ -+#define LTQ_ES_DFSRV_MAP2_REG_PQ26 (0x3 << 12) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ26_VAL(val) (((val) & 0x3) << 12) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ26_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ26) >> 12) & 0x3) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ26_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ26) | (((val) & 0x3) << 12)) -+/* Priority Queue 25 (11:10) */ -+#define LTQ_ES_DFSRV_MAP2_REG_PQ25 (0x3 << 10) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ25_VAL(val) (((val) & 0x3) << 10) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ25_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ25) >> 10) & 0x3) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ25_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ25) | (((val) & 0x3) << 10)) -+/* Priority Queue 24 (9:8) */ -+#define LTQ_ES_DFSRV_MAP2_REG_PQ24 (0x3 << 8) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ24_VAL(val) (((val) & 0x3) << 8) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ24_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ24) >> 8) & 0x3) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ24_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ24) | (((val) & 0x3) << 8)) -+/* Priority Queue 23 (7:6) */ -+#define LTQ_ES_DFSRV_MAP2_REG_PQ23 (0x3 << 6) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ23_VAL(val) (((val) & 0x3) << 6) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ23_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ23) >> 6) & 0x3) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ23_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ23) | (((val) & 0x3) << 6)) -+/* Priority Queue 22 (5:4) */ -+#define LTQ_ES_DFSRV_MAP2_REG_PQ22 (0x3 << 4) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ22_VAL(val) (((val) & 0x3) << 4) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ22_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ22) >> 4) & 0x3) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ22_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ22) | (((val) & 0x3) << 4)) -+/* Priority Queue 21 (3:2) */ -+#define LTQ_ES_DFSRV_MAP2_REG_PQ21 (0x3 << 2) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ21_VAL(val) (((val) & 0x3) << 2) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ21_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ21) >> 2) & 0x3) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ21_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ21) | (((val) & 0x3) << 2)) -+/* Priority Queue 20 (1:0) */ -+#define LTQ_ES_DFSRV_MAP2_REG_PQ20 (0x3) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ20_VAL(val) (((val) & 0x3) << 0) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ20_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ20) >> 0) & 0x3) -+#define LTQ_ES_DFSRV_MAP2_REG_PQ20_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ20) | (((val) & 0x3) << 0)) -+ -+/******************************************************************************* -+ * DiffServMapping 3 -+ ******************************************************************************/ -+ -+/* Priority Queue 3F (31:30) */ -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3F (0x3 << 30) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3F_VAL(val) (((val) & 0x3) << 30) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3F_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3F) >> 30) & 0x3) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3F_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3F) | (((val) & 0x3) << 30)) -+/* Priority Queue 3E (29:28) */ -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3E (0x3 << 28) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3E_VAL(val) (((val) & 0x3) << 28) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3E_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3E) >> 28) & 0x3) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3E_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3E) | (((val) & 0x3) << 28)) -+/* Priority Queue 3D (27:26) */ -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3D (0x3 << 26) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3D_VAL(val) (((val) & 0x3) << 26) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3D_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3D) >> 26) & 0x3) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3D_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3D) | (((val) & 0x3) << 26)) -+/* Priority Queue 3C (25:24) */ -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3C (0x3 << 24) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3C_VAL(val) (((val) & 0x3) << 24) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3C_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3C) >> 24) & 0x3) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3C_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3C) | (((val) & 0x3) << 24)) -+/* Priority Queue 3B (23:22) */ -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3B (0x3 << 22) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3B_VAL(val) (((val) & 0x3) << 22) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3B_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3B) >> 22) & 0x3) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3B) | (((val) & 0x3) << 22)) -+/* Priority Queue 3A (21:20) */ -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3A (0x3 << 20) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3A_VAL(val) (((val) & 0x3) << 20) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3A_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3A) >> 20) & 0x3) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ3A_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3A) | (((val) & 0x3) << 20)) -+/* Priority Queue 39 (19:18) */ -+#define LTQ_ES_DFSRV_MAP3_REG_PQ39 (0x3 << 18) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ39_VAL(val) (((val) & 0x3) << 18) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ39_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ39) >> 18) & 0x3) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ39_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ39) | (((val) & 0x3) << 18)) -+/* Priority Queue 38 (17:16) */ -+#define LTQ_ES_DFSRV_MAP3_REG_PQ38 (0x3 << 16) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ38_VAL(val) (((val) & 0x3) << 16) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ38_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ38) >> 16) & 0x3) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ38_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ38) | (((val) & 0x3) << 16)) -+/* Priority Queue 37 (15:14) */ -+#define LTQ_ES_DFSRV_MAP3_REG_PQ37 (0x3 << 14) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ37_VAL(val) (((val) & 0x3) << 14) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ37_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ37) >> 14) & 0x3) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ37_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ37) | (((val) & 0x3) << 14)) -+/* Priority Queue 36 (13:12) */ -+#define LTQ_ES_DFSRV_MAP3_REG_PQ36 (0x3 << 12) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ36_VAL(val) (((val) & 0x3) << 12) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ36_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ36) >> 12) & 0x3) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ36_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ36) | (((val) & 0x3) << 12)) -+/* Priority Queue 35 (11:10) */ -+#define LTQ_ES_DFSRV_MAP3_REG_PQ35 (0x3 << 10) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ35_VAL(val) (((val) & 0x3) << 10) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ35_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ35) >> 10) & 0x3) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ35_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ35) | (((val) & 0x3) << 10)) -+/* Priority Queue 34 (9:8) */ -+#define LTQ_ES_DFSRV_MAP3_REG_PQ34 (0x3 << 8) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ34_VAL(val) (((val) & 0x3) << 8) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ34_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ34) >> 8) & 0x3) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ34_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ34) | (((val) & 0x3) << 8)) -+/* Priority Queue 33 (7:6) */ -+#define LTQ_ES_DFSRV_MAP3_REG_PQ33 (0x3 << 6) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ33_VAL(val) (((val) & 0x3) << 6) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ33_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ33) >> 6) & 0x3) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ33_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ33) | (((val) & 0x3) << 6)) -+/* Priority Queue 32 (5:4) */ -+#define LTQ_ES_DFSRV_MAP3_REG_PQ32 (0x3 << 4) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ32_VAL(val) (((val) & 0x3) << 4) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ32_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ32) >> 4) & 0x3) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ32) | (((val) & 0x3) << 4)) -+/* Priority Queue 31 (3:2) */ -+#define LTQ_ES_DFSRV_MAP3_REG_PQ31 (0x3 << 2) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ31_VAL(val) (((val) & 0x3) << 2) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ31_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ31) >> 2) & 0x3) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ31_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ31) | (((val) & 0x3) << 2)) -+/* Priority Queue 30 (1:0) */ -+#define LTQ_ES_DFSRV_MAP3_REG_PQ30 (0x3) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ30_VAL(val) (((val) & 0x3) << 0) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ30_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ30) >> 0) & 0x3) -+#define LTQ_ES_DFSRV_MAP3_REG_PQ30_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ30) | (((val) & 0x3) << 0)) -+ -+/******************************************************************************* -+ * TCP/UDP Port Filter 0 -+ ******************************************************************************/ -+ -+/* Reserved (31:30) */ -+#define LTQ_ES_TCP_PF0_REG_RES (0x3 << 30) -+#define LTQ_ES_TCP_PF0_REG_RES_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_RES) >> 30) & 0x3) -+/* Action for TCP/UDP Port Filter 0 (29:28) */ -+#define LTQ_ES_TCP_PF0_REG_ATUF0 (0x3 << 28) -+#define LTQ_ES_TCP_PF0_REG_ATUF0_VAL(val) (((val) & 0x3) << 28) -+#define LTQ_ES_TCP_PF0_REG_ATUF0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_ATUF0) >> 28) & 0x3) -+#define LTQ_ES_TCP_PF0_REG_ATUF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_ATUF0) | (((val) & 0x3) << 28)) -+/* TCP/UDP PRI for TCP/UDP Port Filter 0 (27:26) */ -+#define LTQ_ES_TCP_PF0_REG_TUPF0 (0x3 << 26) -+#define LTQ_ES_TCP_PF0_REG_TUPF0_VAL(val) (((val) & 0x3) << 26) -+#define LTQ_ES_TCP_PF0_REG_TUPF0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_TUPF0) >> 26) & 0x3) -+#define LTQ_ES_TCP_PF0_REG_TUPF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_TUPF0) | (((val) & 0x3) << 26)) -+/* Compare TCP/UDP Source Port or Destination Port (25:24) */ -+#define LTQ_ES_TCP_PF0_REG_COMP0 (0x3 << 24) -+#define LTQ_ES_TCP_PF0_REG_COMP0_VAL(val) (((val) & 0x3) << 24) -+#define LTQ_ES_TCP_PF0_REG_COMP0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_COMP0) >> 24) & 0x3) -+#define LTQ_ES_TCP_PF0_REG_COMP0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_COMP0) | (((val) & 0x3) << 24)) -+/* Port Range in TCP/UDP (23:16) */ -+#define LTQ_ES_TCP_PF0_REG_PRANGE0 (0xff << 16) -+#define LTQ_ES_TCP_PF0_REG_PRANGE0_VAL(val) (((val) & 0xff) << 16) -+#define LTQ_ES_TCP_PF0_REG_PRANGE0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_PRANGE0) >> 16) & 0xff) -+#define LTQ_ES_TCP_PF0_REG_PRANGE0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_PRANGE0) | (((val) & 0xff) << 16)) -+/* Base Port number 0 (15:0) */ -+#define LTQ_ES_TCP_PF0_REG_BASEPT0 (0xffff) -+#define LTQ_ES_TCP_PF0_REG_BASEPT0_VAL(val) (((val) & 0xffff) << 0) -+#define LTQ_ES_TCP_PF0_REG_BASEPT0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_BASEPT0) >> 0) & 0xffff) -+#define LTQ_ES_TCP_PF0_REG_BASEPT0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_BASEPT0) | (((val) & 0xffff) << 0)) -+ -+/******************************************************************************* -+ * Reserved DA(0180C2000003~0180C2000000) control register -+ ******************************************************************************/ -+ -+/* Valid bit for 0180C2000003 (31) */ -+#define LTQ_ES_RA_03_00_REG_RA03_VALID (0x1 << 31) -+#define LTQ_ES_RA_03_00_REG_RA03_VALID_VAL(val) (((val) & 0x1) << 31) -+#define LTQ_ES_RA_03_00_REG_RA03_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_VALID) >> 31) & 0x1) -+#define LTQ_ES_RA_03_00_REG_RA03_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_VALID) | (((val) & 0x1) << 31)) -+/* Span bit for 0180C2000003 (30) */ -+#define LTQ_ES_RA_03_00_REG_RA03_SPAN (0x1 << 30) -+#define LTQ_ES_RA_03_00_REG_RA03_SPAN_VAL(val) (((val) & 0x1) << 30) -+#define LTQ_ES_RA_03_00_REG_RA03_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_SPAN) >> 30) & 0x1) -+#define LTQ_ES_RA_03_00_REG_RA03_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_SPAN) | (((val) & 0x1) << 30)) -+/* Management bit for 0180C2000003 (29) */ -+#define LTQ_ES_RA_03_00_REG_RA03_MG (0x1 << 29) -+#define LTQ_ES_RA_03_00_REG_RA03_MG_VAL(val) (((val) & 0x1) << 29) -+#define LTQ_ES_RA_03_00_REG_RA03_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_MG) >> 29) & 0x1) -+#define LTQ_ES_RA_03_00_REG_RA03_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_MG) | (((val) & 0x1) << 29)) -+/* Cross_VLAN bit for 0180C2000003 (28) */ -+#define LTQ_ES_RA_03_00_REG_RA03_CV (0x1 << 28) -+#define LTQ_ES_RA_03_00_REG_RA03_CV_VAL(val) (((val) & 0x1) << 28) -+#define LTQ_ES_RA_03_00_REG_RA03_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_CV) >> 28) & 0x1) -+#define LTQ_ES_RA_03_00_REG_RA03_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_CV) | (((val) & 0x1) << 28)) -+/* TXTAG bit for 0180C2000003 (27:26) */ -+#define LTQ_ES_RA_03_00_REG_RA03_TXTAG (0x3 << 26) -+#define LTQ_ES_RA_03_00_REG_RA03_TXTAG_VAL(val) (((val) & 0x3) << 26) -+#define LTQ_ES_RA_03_00_REG_RA03_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_TXTAG) >> 26) & 0x3) -+#define LTQ_ES_RA_03_00_REG_RA03_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_TXTAG) | (((val) & 0x3) << 26)) -+/* Action bit for 0180C2000003 (25:24) */ -+#define LTQ_ES_RA_03_00_REG_RA03_ACT (0x3 << 24) -+#define LTQ_ES_RA_03_00_REG_RA03_ACT_VAL(val) (((val) & 0x3) << 24) -+#define LTQ_ES_RA_03_00_REG_RA03_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_ACT) >> 24) & 0x3) -+#define LTQ_ES_RA_03_00_REG_RA03_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_ACT) | (((val) & 0x3) << 24)) -+/* Valid bit for 0180C2000002 (23) */ -+#define LTQ_ES_RA_03_00_REG_RA02_VALID (0x1 << 23) -+#define LTQ_ES_RA_03_00_REG_RA02_VALID_VAL(val) (((val) & 0x1) << 23) -+#define LTQ_ES_RA_03_00_REG_RA02_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_VALID) >> 23) & 0x1) -+#define LTQ_ES_RA_03_00_REG_RA02_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_VALID) | (((val) & 0x1) << 23)) -+/* Span bit for 0180C2000002 (22) */ -+#define LTQ_ES_RA_03_00_REG_RA02_SPAN (0x1 << 22) -+#define LTQ_ES_RA_03_00_REG_RA02_SPAN_VAL(val) (((val) & 0x1) << 22) -+#define LTQ_ES_RA_03_00_REG_RA02_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_SPAN) >> 22) & 0x1) -+#define LTQ_ES_RA_03_00_REG_RA02_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_SPAN) | (((val) & 0x1) << 22)) -+/* Management bit for 0180C2000002 (21) */ -+#define LTQ_ES_RA_03_00_REG_RA02_MG (0x1 << 21) -+#define LTQ_ES_RA_03_00_REG_RA02_MG_VAL(val) (((val) & 0x1) << 21) -+#define LTQ_ES_RA_03_00_REG_RA02_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_MG) >> 21) & 0x1) -+#define LTQ_ES_RA_03_00_REG_RA02_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_MG) | (((val) & 0x1) << 21)) -+/* Cross_VLAN bit for 0180C2000002 (20) */ -+#define LTQ_ES_RA_03_00_REG_RA02_CV (0x1 << 20) -+#define LTQ_ES_RA_03_00_REG_RA02_CV_VAL(val) (((val) & 0x1) << 20) -+#define LTQ_ES_RA_03_00_REG_RA02_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_CV) >> 20) & 0x1) -+#define LTQ_ES_RA_03_00_REG_RA02_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_CV) | (((val) & 0x1) << 20)) -+/* TXTAG bit for 0180C2000002 (19:18) */ -+#define LTQ_ES_RA_03_00_REG_RA02_TXTAG (0x3 << 18) -+#define LTQ_ES_RA_03_00_REG_RA02_TXTAG_VAL(val) (((val) & 0x3) << 18) -+#define LTQ_ES_RA_03_00_REG_RA02_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_TXTAG) >> 18) & 0x3) -+#define LTQ_ES_RA_03_00_REG_RA02_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_TXTAG) | (((val) & 0x3) << 18)) -+/* Action bit for 0180C2000002 (17:16) */ -+#define LTQ_ES_RA_03_00_REG_RA02_ACT (0x3 << 16) -+#define LTQ_ES_RA_03_00_REG_RA02_ACT_VAL(val) (((val) & 0x3) << 16) -+#define LTQ_ES_RA_03_00_REG_RA02_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_ACT) >> 16) & 0x3) -+#define LTQ_ES_RA_03_00_REG_RA02_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_ACT) | (((val) & 0x3) << 16)) -+/* Valid bit for 0180C2000001 (15) */ -+#define LTQ_ES_RA_03_00_REG_RA01_VALID (0x1 << 15) -+#define LTQ_ES_RA_03_00_REG_RA01_VALID_VAL(val) (((val) & 0x1) << 15) -+#define LTQ_ES_RA_03_00_REG_RA01_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_VALID) >> 15) & 0x1) -+#define LTQ_ES_RA_03_00_REG_RA01_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_VALID) | (((val) & 0x1) << 15)) -+/* Span bit for 0180C2000001 (14) */ -+#define LTQ_ES_RA_03_00_REG_RA01_SPAN (0x1 << 14) -+#define LTQ_ES_RA_03_00_REG_RA01_SPAN_VAL(val) (((val) & 0x1) << 14) -+#define LTQ_ES_RA_03_00_REG_RA01_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_SPAN) >> 14) & 0x1) -+#define LTQ_ES_RA_03_00_REG_RA01_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_SPAN) | (((val) & 0x1) << 14)) -+/* Management bit for 0180C2000001 (13) */ -+#define LTQ_ES_RA_03_00_REG_RA01_MG (0x1 << 13) -+#define LTQ_ES_RA_03_00_REG_RA01_MG_VAL(val) (((val) & 0x1) << 13) -+#define LTQ_ES_RA_03_00_REG_RA01_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_MG) >> 13) & 0x1) -+#define LTQ_ES_RA_03_00_REG_RA01_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_MG) | (((val) & 0x1) << 13)) -+/* Cross_VLAN bit for 0180C2000001 (12) */ -+#define LTQ_ES_RA_03_00_REG_RA01_CV (0x1 << 12) -+#define LTQ_ES_RA_03_00_REG_RA01_CV_VAL(val) (((val) & 0x1) << 12) -+#define LTQ_ES_RA_03_00_REG_RA01_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_CV) >> 12) & 0x1) -+#define LTQ_ES_RA_03_00_REG_RA01_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_CV) | (((val) & 0x1) << 12)) -+/* TXTAG bit for 0180C2000001 (11:10) */ -+#define LTQ_ES_RA_03_00_REG_RA01_TXTAG (0x3 << 10) -+#define LTQ_ES_RA_03_00_REG_RA01_TXTAG_VAL(val) (((val) & 0x3) << 10) -+#define LTQ_ES_RA_03_00_REG_RA01_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_TXTAG) >> 10) & 0x3) -+#define LTQ_ES_RA_03_00_REG_RA01_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_TXTAG) | (((val) & 0x3) << 10)) -+/* Action bit for 0180C2000001 (9:8) */ -+#define LTQ_ES_RA_03_00_REG_RA01_ACT (0x3 << 8) -+#define LTQ_ES_RA_03_00_REG_RA01_ACT_VAL(val) (((val) & 0x3) << 8) -+#define LTQ_ES_RA_03_00_REG_RA01_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_ACT) >> 8) & 0x3) -+#define LTQ_ES_RA_03_00_REG_RA01_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_ACT) | (((val) & 0x3) << 8)) -+/* Valid bit for 0180C2000000 (7) */ -+#define LTQ_ES_RA_03_00_REG_RA00_VALID (0x1 << 7) -+#define LTQ_ES_RA_03_00_REG_RA00_VALID_VAL(val) (((val) & 0x1) << 7) -+#define LTQ_ES_RA_03_00_REG_RA00_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_VALID) >> 7) & 0x1) -+#define LTQ_ES_RA_03_00_REG_RA00_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_VALID) | (((val) & 0x1) << 7)) -+/* Span bit for 0180C2000000 (6) */ -+#define LTQ_ES_RA_03_00_REG_RA00_SPAN (0x1 << 6) -+#define LTQ_ES_RA_03_00_REG_RA00_SPAN_VAL(val) (((val) & 0x1) << 6) -+#define LTQ_ES_RA_03_00_REG_RA00_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_SPAN) >> 6) & 0x1) -+#define LTQ_ES_RA_03_00_REG_RA00_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_SPAN) | (((val) & 0x1) << 6)) -+/* Management bit for 0180C2000000 (5) */ -+#define LTQ_ES_RA_03_00_REG_RA00_MG (0x1 << 5) -+#define LTQ_ES_RA_03_00_REG_RA00_MG_VAL(val) (((val) & 0x1) << 5) -+#define LTQ_ES_RA_03_00_REG_RA00_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_MG) >> 5) & 0x1) -+#define LTQ_ES_RA_03_00_REG_RA00_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_MG) | (((val) & 0x1) << 5)) -+/* Cross_VLAN bit for 0180C2000000 (4) */ -+#define LTQ_ES_RA_03_00_REG_RA00_CV (0x1 << 4) -+#define LTQ_ES_RA_03_00_REG_RA00_CV_VAL(val) (((val) & 0x1) << 4) -+#define LTQ_ES_RA_03_00_REG_RA00_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_CV) >> 4) & 0x1) -+#define LTQ_ES_RA_03_00_REG_RA00_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_CV) | (((val) & 0x1) << 4)) -+/* TXTAG bit for 0180C2000000 (3:2) */ -+#define LTQ_ES_RA_03_00_REG_RA00_TXTAG (0x3 << 2) -+#define LTQ_ES_RA_03_00_REG_RA00_TXTAG_VAL(val) (((val) & 0x3) << 2) -+#define LTQ_ES_RA_03_00_REG_RA00_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_TXTAG) >> 2) & 0x3) -+#define LTQ_ES_RA_03_00_REG_RA00_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_TXTAG) | (((val) & 0x3) << 2)) -+/* Action bit for 0180C2000000 (1:0) */ -+#define LTQ_ES_RA_03_00_REG_RA00_ACT (0x3) -+#define LTQ_ES_RA_03_00_REG_RA00_ACT_VAL(val) (((val) & 0x3) << 0) -+#define LTQ_ES_RA_03_00_REG_RA00_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_ACT) >> 0) & 0x3) -+#define LTQ_ES_RA_03_00_REG_RA00_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_ACT) | (((val) & 0x3) << 0)) -+ -+/******************************************************************************* -+ * Protocol Filter 0 -+ ******************************************************************************/ -+ -+/* Value Compared with Protocol in IP Header (31:24) */ -+#define LTQ_ES_PRTCL_F0_REG_PFR3 (0xff << 24) -+#define LTQ_ES_PRTCL_F0_REG_PFR3_VAL(val) (((val) & 0xff) << 24) -+#define LTQ_ES_PRTCL_F0_REG_PFR3_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR3) >> 24) & 0xff) -+#define LTQ_ES_PRTCL_F0_REG_PFR3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR3) | (((val) & 0xff) << 24)) -+/* Value Compared with Protocol in IP Header (23:16) */ -+#define LTQ_ES_PRTCL_F0_REG_PFR2 (0xff << 16) -+#define LTQ_ES_PRTCL_F0_REG_PFR2_VAL(val) (((val) & 0xff) << 16) -+#define LTQ_ES_PRTCL_F0_REG_PFR2_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR2) >> 16) & 0xff) -+#define LTQ_ES_PRTCL_F0_REG_PFR2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR2) | (((val) & 0xff) << 16)) -+/* Value Compared with Protocol in IP Header (15:8) */ -+#define LTQ_ES_PRTCL_F0_REG_PFR1 (0xff << 8) -+#define LTQ_ES_PRTCL_F0_REG_PFR1_VAL(val) (((val) & 0xff) << 8) -+#define LTQ_ES_PRTCL_F0_REG_PFR1_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR1) >> 8) & 0xff) -+#define LTQ_ES_PRTCL_F0_REG_PFR1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR1) | (((val) & 0xff) << 8)) -+/* Value Compared with Protocol in IP Header (7:0) */ -+#define LTQ_ES_PRTCL_F0_REG_PFR0 (0xff) -+#define LTQ_ES_PRTCL_F0_REG_PFR0_VAL(val) (((val) & 0xff) << 0) -+#define LTQ_ES_PRTCL_F0_REG_PFR0_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR0) >> 0) & 0xff) -+#define LTQ_ES_PRTCL_F0_REG_PFR0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR0) | (((val) & 0xff) << 0)) -+ -+#endif -Index: linux-3.3.8/include/linux/svip_nat.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/include/linux/svip_nat.h 2012-07-31 15:46:02.476476158 +0200 -@@ -0,0 +1,37 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2007 -+ Infineon Technologies AG -+ Am Campeon 1-12; 81726 Munich, Germany -+ -+ THE DELIVERY OF THIS SOFTWARE AS WELL AS THE HEREBY GRANTED NON-EXCLUSIVE, -+ WORLDWIDE LICENSE TO USE, COPY, MODIFY, DISTRIBUTE AND SUBLICENSE THIS -+ SOFTWARE IS FREE OF CHARGE. -+ -+ THE LICENSED SOFTWARE IS PROVIDED "AS IS" AND INFINEON EXPRESSLY DISCLAIMS -+ ALL REPRESENTATIONS AND WARRANTIES, WHETHER EXPRESS OR IMPLIED, INCLUDING -+ WITHOUT LIMITATION, WARRANTIES OR REPRESENTATIONS OF WORKMANSHIP, -+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, DURABILITY, THAT THE -+ OPERATING OF THE LICENSED SOFTWARE WILL BE ERROR FREE OR FREE OF ANY THIRD -+ PARTY CLAIMS, INCLUDING WITHOUT LIMITATION CLAIMS OF THIRD PARTY INTELLECTUAL -+ PROPERTY INFRINGEMENT. -+ -+ EXCEPT FOR ANY LIABILITY DUE TO WILFUL ACTS OR GROSS NEGLIGENCE AND EXCEPT -+ FOR ANY PERSONAL INJURY INFINEON SHALL IN NO EVENT BE LIABLE FOR ANY CLAIM -+ OR DAMAGES OF ANY KIND, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -+ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -+ DEALINGS IN THE SOFTWARE. -+*******************************************************************************/ -+#ifndef _SVIP_NAT_H -+#define _SVIP_NAT_H -+ -+/* The declarations here have to be in a header file, because -+ * they need to be known both to the kernel module -+ * (in chardev.c) and the process calling ioctl (ioctl.c) -+ */ -+#include -+ -+#define SVIP_NAT_VERSION "3.1" -+extern int do_SVIP_NAT(struct sk_buff *); -+ -+#endif -Index: linux-3.3.8/include/linux/svip_nat_io.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/include/linux/svip_nat_io.h 2012-07-31 15:46:02.476476158 +0200 -@@ -0,0 +1,103 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2007 -+ Infineon Technologies AG -+ Am Campeon 1-12; 81726 Munich, Germany -+ -+ THE DELIVERY OF THIS SOFTWARE AS WELL AS THE HEREBY GRANTED NON-EXCLUSIVE, -+ WORLDWIDE LICENSE TO USE, COPY, MODIFY, DISTRIBUTE AND SUBLICENSE THIS -+ SOFTWARE IS FREE OF CHARGE. -+ -+ THE LICENSED SOFTWARE IS PROVIDED "AS IS" AND INFINEON EXPRESSLY DISCLAIMS -+ ALL REPRESENTATIONS AND WARRANTIES, WHETHER EXPRESS OR IMPLIED, INCLUDING -+ WITHOUT LIMITATION, WARRANTIES OR REPRESENTATIONS OF WORKMANSHIP, -+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, DURABILITY, THAT THE -+ OPERATING OF THE LICENSED SOFTWARE WILL BE ERROR FREE OR FREE OF ANY THIRD -+ PARTY CLAIMS, INCLUDING WITHOUT LIMITATION CLAIMS OF THIRD PARTY INTELLECTUAL -+ PROPERTY INFRINGEMENT. -+ -+ EXCEPT FOR ANY LIABILITY DUE TO WILFUL ACTS OR GROSS NEGLIGENCE AND EXCEPT -+ FOR ANY PERSONAL INJURY INFINEON SHALL IN NO EVENT BE LIABLE FOR ANY CLAIM -+ OR DAMAGES OF ANY KIND, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -+ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -+ DEALINGS IN THE SOFTWARE. -+ *******************************************************************************/ -+#ifndef _SVIP_NAT_IO_H_ -+#define _SVIP_NAT_IO_H_ -+ -+#include -+ -+#define SVIP_NAT_DEVICE_NAME "svip_nat" -+#define PATH_SVIP_NAT_DEVICE_NAME "/dev/"SVIP_NAT_DEVICE_NAME -+ -+#define MAJOR_NUM_SVIP_NAT 10 -+#define MINOR_NUM_SVIP_NAT 120 -+ -+/** maximum SVIP devices supported on a Line card system */ -+#define SVIP_SYS_NUM 12 -+ -+/** maximum voice packet channels possible per SVIP device */ -+#define SVIP_CODEC_NUM 16 -+ -+/** start UDP port number of the SVIP Linecard System */ -+#define SVIP_UDP_FROM 50000 -+ -+/** @defgroup SVIP_NATAPI SVIP Custom NAT ioctl interface. -+ An ioctl interface is provided to add a rule into the SVIP NAT table and -+ to respectively remove the rule form it. The ioctl interface is accessible -+ using the fd issued upon opening the special device node /dev/svip_nat. -+ @{ */ -+ -+/** Used to add a new rule to the SVIP Custom NAT table. If a rule already -+ exists for the target UDP port, that rule shall be overwritten. -+ -+ \param SVIP_NAT_IO_Rule_t* The parameter points to a -+ \ref SVIP_NAT_IO_Rule_t structure. -+ */ -+#define FIO_SVIP_NAT_RULE_ADD \ -+ _IOW(MAJOR_NUM_SVIP_NAT, 1, SVIP_NAT_IO_Rule_t) -+ -+/** Used to remove a rule from the SVIP Custom NAT table. No check is -+ performed whether the rule already exists or not. The remove operation is -+ performed as long as the target UDP port is within the defined port range. -+ -+ \param SVIP_NAT_IO_Rule_t* The parameter points to a -+ \ref SVIP_NAT_IO_Rule_t structure. -+ */ -+#define FIO_SVIP_NAT_RULE_REMOVE \ -+ _IOW(MAJOR_NUM_SVIP_NAT, 2, SVIP_NAT_IO_Rule_t) -+ -+/** Used to list all rules in the SVIP Custom NAT table. -+ -+ \param -+ */ -+#define FIO_SVIP_NAT_RULE_LIST \ -+ _IO(MAJOR_NUM_SVIP_NAT, 3) -+ -+/** IP address in network-byte order */ -+typedef u32 SVIP_IP_ADDR_t; -+/** UDP port in network-byte order */ -+typedef u16 SVIP_UDP_PORT_t; -+ -+#ifndef ETH_ALEN -+#define ETH_ALEN 6 /* Octets in one ethernet address */ -+#endif -+ -+/** NAT parameters part of the NAT table. -+ These paramters are configurable through the NAT API. */ -+typedef struct SVIP_NAT_IO_Rule -+{ -+ /** Remote peer, IP address */ -+ SVIP_IP_ADDR_t remIP; -+ /** Remote peer, MAC address */ -+ u8 remMAC[ETH_ALEN]; -+ /** Target SVIP, IP address (local peer) */ -+ SVIP_IP_ADDR_t locIP; -+ /** Target SVIP, MAC address */ -+ u8 locMAC[ETH_ALEN]; -+ /** Target SVIP, UDP port number */ -+ SVIP_UDP_PORT_t locUDP; -+} SVIP_NAT_IO_Rule_t; -+ -+/** @} */ -+#endif -Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/mps_reg.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/mps_reg.h 2012-07-31 15:46:02.476476158 +0200 -@@ -0,0 +1,242 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2007 -+ Infineon Technologies AG -+ St. Martin Strasse 53; 81669 Munich, Germany -+ -+ Any use of this Software is subject to the conclusion of a respective -+ License Agreement. Without such a License Agreement no rights to the -+ Software are granted. -+ -+ ******************************************************************************/ -+ -+#ifndef __MPS_REG_H -+#define __MPS_REG_H -+ -+#define mbs_r32(reg) ltq_r32(&mbs->reg) -+#define mbs_w32(val, reg) ltq_w32(val, &mbs->reg) -+#define mbs_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &mbs->reg) -+ -+/** MBS register structure */ -+struct svip_reg_mbs { -+ unsigned long reserved0[4]; -+ unsigned long mbsr0; /* 0x0010 */ -+ unsigned long mbsr1; /* 0x0014 */ -+ unsigned long mbsr2; /* 0x0018 */ -+ unsigned long mbsr3; /* 0x001c */ -+ unsigned long mbsr4; /* 0x0020 */ -+ unsigned long mbsr5; /* 0x0024 */ -+ unsigned long mbsr6; /* 0x0028 */ -+ unsigned long mbsr7; /* 0x002c */ -+ unsigned long mbsr8; /* 0x0030 */ -+ unsigned long mbsr9; /* 0x0034 */ -+ unsigned long mbsr10; /* 0x0038 */ -+ unsigned long mbsr11; /* 0x003c */ -+ unsigned long mbsr12; /* 0x0040 */ -+ unsigned long mbsr13; /* 0x0044 */ -+ unsigned long mbsr14; /* 0x0048 */ -+ unsigned long mbsr15; /* 0x004c */ -+ unsigned long mbsr16; /* 0x0050 */ -+ unsigned long mbsr17; /* 0x0054 */ -+ unsigned long mbsr18; /* 0x0058 */ -+ unsigned long mbsr19; /* 0x005c */ -+ unsigned long mbsr20; /* 0x0060 */ -+ unsigned long mbsr21; /* 0x0064 */ -+ unsigned long mbsr22; /* 0x0068 */ -+ unsigned long mbsr23; /* 0x006c */ -+ unsigned long mbsr24; /* 0x0070 */ -+ unsigned long mbsr25; /* 0x0074 */ -+ unsigned long mbsr26; /* 0x0078 */ -+ unsigned long mbsr27; /* 0x007c */ -+ unsigned long mbsr28; /* 0x0080 */ -+}; -+ -+/** MPS register structure */ -+struct svip_reg_mps { -+ volatile unsigned long mps_swirn0set; /* 0x0000 */ -+ volatile unsigned long mps_swirn0en; /* 0x0004 */ -+ volatile unsigned long mps_swirn0cr; /* 0x0008 */ -+ volatile unsigned long mps_swirn0icr; /* 0x000C */ -+ volatile unsigned long mps_swirn1set; /* 0x0010 */ -+ volatile unsigned long mps_swirn1en; /* 0x0014 */ -+ volatile unsigned long mps_swirn1cr; /* 0x0018 */ -+ volatile unsigned long mps_swirn1icr; /* 0x001C */ -+ volatile unsigned long mps_swirn2set; /* 0x0020 */ -+ volatile unsigned long mps_swirn2en; /* 0x0024 */ -+ volatile unsigned long mps_swirn2cr; /* 0x0028 */ -+ volatile unsigned long mps_swirn2icr; /* 0x002C */ -+ volatile unsigned long mps_swirn3set; /* 0x0030 */ -+ volatile unsigned long mps_swirn3en; /* 0x0034 */ -+ volatile unsigned long mps_swirn3cr; /* 0x0038 */ -+ volatile unsigned long mps_swirn3icr; /* 0x003C */ -+ volatile unsigned long mps_swirn4set; /* 0x0040 */ -+ volatile unsigned long mps_swirn4en; /* 0x0044 */ -+ volatile unsigned long mps_swirn4cr; /* 0x0048 */ -+ volatile unsigned long mps_swirn4icr; /* 0x004C */ -+ volatile unsigned long mps_swirn5set; /* 0x0050 */ -+ volatile unsigned long mps_swirn5en; /* 0x0054 */ -+ volatile unsigned long mps_swirn5cr; /* 0x0058 */ -+ volatile unsigned long mps_swirn5icr; /* 0x005C */ -+ volatile unsigned long mps_swirn6set; /* 0x0060 */ -+ volatile unsigned long mps_swirn6en; /* 0x0064 */ -+ volatile unsigned long mps_swirn6cr; /* 0x0068 */ -+ volatile unsigned long mps_swirn6icr; /* 0x006C */ -+ volatile unsigned long mps_swirn7set; /* 0x0070 */ -+ volatile unsigned long mps_swirn7en; /* 0x0074 */ -+ volatile unsigned long mps_swirn7cr; /* 0x0078 */ -+ volatile unsigned long mps_swirn7icr; /* 0x007C */ -+ volatile unsigned long mps_swirn8set; /* 0x0080 */ -+ volatile unsigned long mps_swirn8en; /* 0x0084 */ -+ volatile unsigned long mps_swirn8cr; /* 0x0088 */ -+ volatile unsigned long mps_swirn8icr; /* 0x008C */ -+}; -+ -+/* Software Interrupt */ -+#define IFX_MPS_SWIRN0SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0000)) -+#define IFX_MPS_SWIRN0EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0004)) -+#define IFX_MPS_SWIRN0CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0008)) -+#define IFX_MPS_SWIRN0ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x000C)) -+#define IFX_MPS_SWIRN1SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0010)) -+#define IFX_MPS_SWIRN1EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0014)) -+#define IFX_MPS_SWIRN1CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0018)) -+#define IFX_MPS_SWIRN1ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x001C)) -+#define IFX_MPS_SWIRN2SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0020)) -+#define IFX_MPS_SWIRN2EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0024)) -+#define IFX_MPS_SWIRN2CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0028)) -+#define IFX_MPS_SWIRN2ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x002C)) -+#define IFX_MPS_SWIRN3SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0030)) -+#define IFX_MPS_SWIRN3EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0034)) -+#define IFX_MPS_SWIRN3CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0038)) -+#define IFX_MPS_SWIRN3ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x003C)) -+#define IFX_MPS_SWIRN4SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0040)) -+#define IFX_MPS_SWIRN4EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0044)) -+#define IFX_MPS_SWIRN4CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0048)) -+#define IFX_MPS_SWIRN4ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x004C)) -+#define IFX_MPS_SWIRN5SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0050)) -+#define IFX_MPS_SWIRN5EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0054)) -+#define IFX_MPS_SWIRN5CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0058)) -+#define IFX_MPS_SWIRN5ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x005C)) -+#define IFX_MPS_SWIRN6SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0060)) -+#define IFX_MPS_SWIRN6EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0064)) -+#define IFX_MPS_SWIRN6CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0068)) -+#define IFX_MPS_SWIRN6ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x006C)) -+#define IFX_MPS_SWIRN7SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0070)) -+#define IFX_MPS_SWIRN7EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0074)) -+#define IFX_MPS_SWIRN7CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0078)) -+#define IFX_MPS_SWIRN7ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x007C)) -+#define IFX_MPS_SWIRN8SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0080)) -+#define IFX_MPS_SWIRN8EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0084)) -+#define IFX_MPS_SWIRN8ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x008C)) -+#define IFX_MPS_SWIRN8CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0088)) -+ -+/******************************************************************************* -+ * MPS_SWIRNSET Register -+ ******************************************************************************/ -+ -+/* Software Interrupt Request IR5 (5) */ -+#define IFX_MPS_SWIRNSET_IR5 (0x1 << 5) -+#define IFX_MPS_SWIRNSET_IR5_VAL(val) (((val) & 0x1) << 5) -+#define IFX_MPS_SWIRNSET_IR5_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR5) | (val) & 1) << 5) -+/* Software Interrupt Request IR4 (4) */ -+#define IFX_MPS_SWIRNSET_IR4 (0x1 << 4) -+#define IFX_MPS_SWIRNSET_IR4_VAL(val) (((val) & 0x1) << 4) -+#define IFX_MPS_SWIRNSET_IR4_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR4) | (val) & 1) << 4) -+/* Software Interrupt Request IR3 (3) */ -+#define IFX_MPS_SWIRNSET_IR3 (0x1 << 3) -+#define IFX_MPS_SWIRNSET_IR3_VAL(val) (((val) & 0x1) << 3) -+#define IFX_MPS_SWIRNSET_IR3_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR3) | (val) & 1) << 3) -+/* Software Interrupt Request IR2 (2) */ -+#define IFX_MPS_SWIRNSET_IR2 (0x1 << 2) -+#define IFX_MPS_SWIRNSET_IR2_VAL(val) (((val) & 0x1) << 2) -+#define IFX_MPS_SWIRNSET_IR2_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR2) | (val) & 1) << 2) -+/* Software Interrupt Request IR1 (1) */ -+#define IFX_MPS_SWIRNSET_IR1 (0x1 << 1) -+#define IFX_MPS_SWIRNSET_IR1_VAL(val) (((val) & 0x1) << 1) -+#define IFX_MPS_SWIRNSET_IR1_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR1) | (val) & 1) << 1) -+/* Software Interrupt Request IR0 (0) */ -+#define IFX_MPS_SWIRNSET_IR0 (0x1) -+#define IFX_MPS_SWIRNSET_IR0_VAL(val) (((val) & 0x1) << 0) -+#define IFX_MPS_SWIRNSET_IR0_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR0) | (val) & 1) << 0) -+ -+/******************************************************************************* -+ * MPS_SWIRNEN Register -+ ******************************************************************************/ -+ -+/* Software Interrupt Request IR5 (5) */ -+#define IFX_MPS_SWIRNEN_IR5 (0x1 << 5) -+#define IFX_MPS_SWIRNEN_IR5_VAL(val) (((val) & 0x1) << 5) -+#define IFX_MPS_SWIRNEN_IR5_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR5) >> 5) & 0x1) -+#define IFX_MPS_SWIRNEN_IR5_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR5) | (((val) & 0x1) << 5)) -+/* Software Interrupt Request IR4 (4) */ -+#define IFX_MPS_SWIRNEN_IR4 (0x1 << 4) -+#define IFX_MPS_SWIRNEN_IR4_VAL(val) (((val) & 0x1) << 4) -+#define IFX_MPS_SWIRNEN_IR4_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR4) >> 4) & 0x1) -+#define IFX_MPS_SWIRNEN_IR4_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR4) | (((val) & 0x1) << 4)) -+/* Software Interrupt Request IR3 (3) */ -+#define IFX_MPS_SWIRNEN_IR3 (0x1 << 3) -+#define IFX_MPS_SWIRNEN_IR3_VAL(val) (((val) & 0x1) << 3) -+#define IFX_MPS_SWIRNEN_IR3_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR3) >> 3) & 0x1) -+#define IFX_MPS_SWIRNEN_IR3_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR3) | (((val) & 0x1) << 3)) -+/* Software Interrupt Request IR2 (2) */ -+#define IFX_MPS_SWIRNEN_IR2 (0x1 << 2) -+#define IFX_MPS_SWIRNEN_IR2_VAL(val) (((val) & 0x1) << 2) -+#define IFX_MPS_SWIRNEN_IR2_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR2) >> 2) & 0x1) -+#define IFX_MPS_SWIRNEN_IR2_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR2) | (((val) & 0x1) << 2)) -+/* Software Interrupt Request IR1 (1) */ -+#define IFX_MPS_SWIRNEN_IR1 (0x1 << 1) -+#define IFX_MPS_SWIRNEN_IR1_VAL(val) (((val) & 0x1) << 1) -+#define IFX_MPS_SWIRNEN_IR1_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR1) >> 1) & 0x1) -+#define IFX_MPS_SWIRNEN_IR1_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR1) | (((val) & 0x1) << 1)) -+/* Software Interrupt Request IR0 (0) */ -+#define IFX_MPS_SWIRNEN_IR0 (0x1) -+#define IFX_MPS_SWIRNEN_IR0_VAL(val) (((val) & 0x1) << 0) -+#define IFX_MPS_SWIRNEN_IR0_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR0) >> 0) & 0x1) -+#define IFX_MPS_SWIRNEN_IR0_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR0) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * MPS_SWIRNICR Register -+ ******************************************************************************/ -+ -+/* Software Interrupt Request IR5 (5) */ -+#define IFX_MPS_SWIRNICR_IR5 (0x1 << 5) -+#define IFX_MPS_SWIRNICR_IR5_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR5) >> 5) & 0x1) -+/* Software Interrupt Request IR4 (4) */ -+#define IFX_MPS_SWIRNICR_IR4 (0x1 << 4) -+#define IFX_MPS_SWIRNICR_IR4_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR4) >> 4) & 0x1) -+/* Software Interrupt Request IR3 (3) */ -+#define IFX_MPS_SWIRNICR_IR3 (0x1 << 3) -+#define IFX_MPS_SWIRNICR_IR3_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR3) >> 3) & 0x1) -+/* Software Interrupt Request IR2 (2) */ -+#define IFX_MPS_SWIRNICR_IR2 (0x1 << 2) -+#define IFX_MPS_SWIRNICR_IR2_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR2) >> 2) & 0x1) -+/* Software Interrupt Request IR1 (1) */ -+#define IFX_MPS_SWIRNICR_IR1 (0x1 << 1) -+#define IFX_MPS_SWIRNICR_IR1_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR1) >> 1) & 0x1) -+/* Software Interrupt Request IR0 (0) */ -+#define IFX_MPS_SWIRNICR_IR0 (0x1) -+#define IFX_MPS_SWIRNICR_IR0_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR0) >> 0) & 0x1) -+ -+/******************************************************************************* -+ * MPS_SWIRNCR Register -+ ******************************************************************************/ -+ -+/* Software Interrupt Request IR5 (5) */ -+#define IFX_MPS_SWIRNCR_IR5 (0x1 << 5) -+#define IFX_MPS_SWIRNCR_IR5_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR5) >> 5) & 0x1) -+/* Software Interrupt Request IR4 (4) */ -+#define IFX_MPS_SWIRNCR_IR4 (0x1 << 4) -+#define IFX_MPS_SWIRNCR_IR4_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR4) >> 4) & 0x1) -+/* Software Interrupt Request IR3 (3) */ -+#define IFX_MPS_SWIRNCR_IR3 (0x1 << 3) -+#define IFX_MPS_SWIRNCR_IR3_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR3) >> 3) & 0x1) -+/* Software Interrupt Request IR2 (2) */ -+#define IFX_MPS_SWIRNCR_IR2 (0x1 << 2) -+#define IFX_MPS_SWIRNCR_IR2_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR2) >> 2) & 0x1) -+/* Software Interrupt Request IR1 (1) */ -+#define IFX_MPS_SWIRNCR_IR1 (0x1 << 1) -+#define IFX_MPS_SWIRNCR_IR1_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR1) >> 1) & 0x1) -+/* Software Interrupt Request IR0 (0) */ -+#define IFX_MPS_SWIRNCR_IR0 (0x1) -+#define IFX_MPS_SWIRNCR_IR0_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR0) >> 0) & 0x1) -+ -+#endif -Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/status_reg.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/status_reg.h 2012-07-31 15:46:02.476476158 +0200 -@@ -0,0 +1,130 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2007 -+ Infineon Technologies AG -+ St. Martin Strasse 53; 81669 Munich, Germany -+ -+ Any use of this Software is subject to the conclusion of a respective -+ License Agreement. Without such a License Agreement no rights to the -+ Software are granted. -+ -+ ******************************************************************************/ -+ -+#ifndef __STATUS_REG_H -+#define __STATUS_REG_H -+ -+#define status_r32(reg) ltq_r32(&status->reg) -+#define status_w32(val, reg) ltq_w32(val, &status->reg) -+#define status_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &status->reg) -+ -+/** STATUS register structure */ -+struct svip_reg_status { -+ unsigned long fuse_deu; /* 0x0000 */ -+ unsigned long fuse_cpu; /* 0x0004 */ -+ unsigned long fuse_pll; /* 0x0008 */ -+ unsigned long chipid; /* 0x000C */ -+ unsigned long config; /* 0x0010 */ -+ unsigned long chip_loc; /* 0x0014 */ -+ unsigned long fuse_spare; /* 0x0018 */ -+}; -+ -+/******************************************************************************* -+ * Fuse for DEU Settings -+ ******************************************************************************/ -+ -+/* Fuse for Enabling the TRNG (6) */ -+#define STATUS_FUSE_DEU_TRNG (0x1 << 6) -+#define STATUS_FUSE_DEU_TRNG_GET(val) ((((val) & STATUS_FUSE_DEU_TRNG) >> 6) & 0x1) -+/* Fuse for Enabling the DES Submodule (5) */ -+#define STATUS_FUSE_DEU_DES (0x1 << 5) -+#define STATUS_FUSE_DEU_DES_GET(val) ((((val) & STATUS_FUSE_DEU_DES) >> 5) & 0x1) -+/* Fuse for Enabling the 3DES Submodule (4) */ -+#define STATUS_FUSE_DEU_3DES (0x1 << 4) -+#define STATUS_FUSE_DEU_3DES_GET(val) ((((val) & STATUS_FUSE_DEU_3DES) >> 4) & 0x1) -+/* Fuse for Enabling the AES Submodule (3) */ -+#define STATUS_FUSE_DEU_AES (0x1 << 3) -+#define STATUS_FUSE_DEU_AES_GET(val) ((((val) & STATUS_FUSE_DEU_AES) >> 3) & 0x1) -+/* Fuse for Enabling the HASH Submodule (2) */ -+#define STATUS_FUSE_DEU_HASH (0x1 << 2) -+#define STATUS_FUSE_DEU_HASH_GET(val) ((((val) & STATUS_FUSE_DEU_HASH) >> 2) & 0x1) -+/* Fuse for Enabling the ARC4 Submodule (1) */ -+#define STATUS_FUSE_DEU_ARC4 (0x1 << 1) -+#define STATUS_FUSE_DEU_ARC4_GET(val) ((((val) & STATUS_FUSE_DEU_ARC4) >> 1) & 0x1) -+/* Fuse for Enabling the DEU Module (0) */ -+#define STATUS_FUSE_DEU_DEU (0x1) -+#define STATUS_FUSE_DEU_DEU_GET(val) ((((val) & STATUS_FUSE_DEU_DEU) >> 0) & 0x1) -+ -+/******************************************************************************* -+ * Fuse for CPU Settings -+ ******************************************************************************/ -+ -+/* Fuse for Enabling CPU5 (5) */ -+#define STATUS_FUSE_CPU_CPU5 (0x1 << 5) -+#define STATUS_FUSE_CPU_CPU5_GET(val) ((((val) & STATUS_FUSE_CPU_CPU5) >> 5) & 0x1) -+/* Fuse for Enabling the CPU4 (4) */ -+#define STATUS_FUSE_CPU_CPU4 (0x1 << 4) -+#define STATUS_FUSE_CPU_CPU4_GET(val) ((((val) & STATUS_FUSE_CPU_CPU4) >> 4) & 0x1) -+/* Fuse for Enabling the CPU3 (3) */ -+#define STATUS_FUSE_CPU_CPU3 (0x1 << 3) -+#define STATUS_FUSE_CPU_CPU3_GET(val) ((((val) & STATUS_FUSE_CPU_CPU3) >> 3) & 0x1) -+/* Fuse for Enabling the CPU2 (2) */ -+#define STATUS_FUSE_CPU_CPU2 (0x1 << 2) -+#define STATUS_FUSE_CPU_CPU2_GET(val) ((((val) & STATUS_FUSE_CPU_CPU2) >> 2) & 0x1) -+/* Fuse for Enabling the CPU1 (1) */ -+#define STATUS_FUSE_CPU_CPU1 (0x1 << 1) -+#define STATUS_FUSE_CPU_CPU1_GET(val) ((((val) & STATUS_FUSE_CPU_CPU1) >> 1) & 0x1) -+/* Fuse for Enabling the CPU0 (0) */ -+#define STATUS_FUSE_CPU_CPU0 (0x1) -+#define STATUS_FUSE_CPU_CPU0_GET(val) ((((val) & STATUS_FUSE_CPU_CPU0) >> 0) & 0x1) -+ -+/******************************************************************************* -+ * Fuse for PLL Settings -+ ******************************************************************************/ -+ -+/* Fuse for Enabling PLL (7:0) */ -+#define STATUS_FUSE_PLL_PLL (0xff) -+#define STATUS_FUSE_PLL_PLL_GET(val) ((((val) & STATUS_FUSE_PLL_PLL) >> 0) & 0xff) -+ -+/******************************************************************************* -+ * Chip Identification Register -+ ******************************************************************************/ -+ -+/* Chip Version Number (31:28) */ -+#define STATUS_CHIPID_VERSION (0xf << 28) -+#define STATUS_CHIPID_VERSION_GET(val) ((((val) & STATUS_CHIPID_VERSION) >> 28) & 0xf) -+/* Part Number (27:12) */ -+#define STATUS_CHIPID_PART_NUMBER (0xffff << 12) -+#define STATUS_CHIPID_PART_NUMBER_GET(val) ((((val) & STATUS_CHIPID_PART_NUMBER) >> 12) & 0xffff) -+/* Manufacturer ID (11:1) */ -+#define STATUS_CHIPID_MANID (0x7ff << 1) -+#define STATUS_CHIPID_MANID_GET(val) ((((val) & STATUS_CHIPID_MANID) >> 1) & 0x7ff) -+ -+/******************************************************************************* -+ * Chip Configuration Register -+ ******************************************************************************/ -+ -+/* Number of Analog Channels (8:5) */ -+#define STATUS_CONFIG_ANA_CHAN (0xf << 5) -+#define STATUS_CONFIG_ANA_CHAN_GET(val) ((((val) & STATUS_CONFIG_ANA_CHAN) >> 5) & 0xf) -+/* Clock Mode (4) */ -+#define STATUS_CONFIG_CLK_MODE (0x1 << 1) -+#define STATUS_CONFIG_CLK_MODE_GET(val) ((((val) & STATUS_CONFIG_CLK_MODE) >> 4) & 0x1) -+/* Subversion Number (3:0) */ -+#define STATUS_CONFIG_SUB_VERS (0xF) -+#define STATUS_CONFIG_SUB_VERS_GET(val) ((((val) & STATUS_SUBVER_SUB_VERS) >> 0) & 0xF) -+ -+/******************************************************************************* -+ * Chip Location Register -+ ******************************************************************************/ -+ -+/* Chip Lot ID (31:16) */ -+#define STATUS_CHIP_LOC_CHIP_LOT (0xffff << 16) -+#define STATUS_CHIP_LOC_CHIP_LOT_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_LOT) >> 16) & 0xffff) -+/* Chip X Coordinate (15:8) */ -+#define STATUS_CHIP_LOC_CHIP_X (0xff << 8) -+#define STATUS_CHIP_LOC_CHIP_X_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_X) >> 8) & 0xff) -+/* Chip Y Coordinate (7:0) */ -+#define STATUS_CHIP_LOC_CHIP_Y (0xff) -+#define STATUS_CHIP_LOC_CHIP_Y_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_Y) >> 0) & 0xff) -+ -+#endif -Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/boot_reg.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/boot_reg.h 2012-07-31 15:46:02.476476158 +0200 -@@ -0,0 +1,37 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2007 -+ Infineon Technologies AG -+ St. Martin Strasse 53; 81669 Munich, Germany -+ -+ Any use of this Software is subject to the conclusion of a respective -+ License Agreement. Without such a License Agreement no rights to the -+ Software are granted. -+ -+******************************************************************************/ -+ -+#ifndef __BOOT_REG_H -+#define __BOOT_REG_H -+ -+#define LTQ_BOOT_CPU_OFFSET 0x20 -+ -+#define LTQ_BOOT_RVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ -+ (cpu * LTQ_BOOT_CPU_OFFSET) + 0x00) -+#define LTQ_BOOT_NVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ -+ (cpu * LTQ_BOOT_CPU_OFFSET) + 0x04) -+#define LTQ_BOOT_EVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ -+ (cpu * LTQ_BOOT_CPU_OFFSET) + 0x08) -+#define LTQ_BOOT_CP0_STATUS(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ -+ (cpu * LTQ_BOOT_CPU_OFFSET) + 0x0C) -+#define LTQ_BOOT_CP0_EPC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ -+ (cpu * LTQ_BOOT_CPU_OFFSET) + 0x10) -+#define LTQ_BOOT_CP0_EEPC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ -+ (cpu * LTQ_BOOT_CPU_OFFSET) + 0x14) -+#define LTQ_BOOT_SIZE(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ -+ (cpu * LTQ_BOOT_CPU_OFFSET) + 0x18) /* only for CP1 */ -+#define LTQ_BOOT_RCU_SR(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ -+ (cpu * LTQ_BOOT_CPU_OFFSET) + 0x18) /* only for CP0 */ -+#define LTQ_BOOT_CFG_STAT(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ -+ (cpu * LTQ_BOOT_CPU_OFFSET) + 0x1C) -+ -+#endif -Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/sys0_reg.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/sys0_reg.h 2012-07-31 15:46:02.480476158 +0200 -@@ -0,0 +1,165 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2007 -+ Infineon Technologies AG -+ St. Martin Strasse 53; 81669 Munich, Germany -+ -+ Any use of this Software is subject to the conclusion of a respective -+ License Agreement. Without such a License Agreement no rights to the -+ Software are granted. -+ -+ ******************************************************************************/ -+ -+#ifndef __SYS0_REG_H -+#define __SYS0_REG_H -+ -+#define sys0_r32(reg) ltq_r32(&sys0->reg) -+#define sys0_w32(val, reg) ltq_w32(val, &sys0->reg) -+#define sys0_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys0->reg) -+ -+/** SYS0 register structure */ -+struct svip_reg_sys0 { -+ unsigned long sr; /* 0x0000 */ -+ unsigned long bcr; /* 0x0004 */ -+ unsigned long pll1cr; /* 0x0008 */ -+ unsigned long pll2cr; /* 0x000c */ -+ unsigned long tscr; /* 0x0010 */ -+ unsigned long phyclkr; /* 0x0014 */ -+}; -+ -+/******************************************************************************* -+ * SYS0 Status Register -+ ******************************************************************************/ -+ -+/* Endian select pin (31) */ -+#define SYS0_SR_ESEL (0x1 << 31) -+#define SYS0_SR_ESEL_GET(val) ((((val) & SYS0_SR_ESEL) >> 31) & 0x1) -+/* Boot mode pins (27:24) */ -+#define SYS0_SR_BMODE (0xf << 24) -+#define SYS0_SR_BMODE_GET(val) ((((val) & SYS0_SR_BMODE) >> 24) & 0xf) -+/* PLL2 Lock (18) */ -+#define SYS0_SR_PLL2LOCK (0x1 << 18) -+#define SYS0_SR_PLL2LOCK_GET(val) ((((val) & SYS0_SR_PLL2LOCK) >> 18) & 0x1) -+/* PLL1 Lock (17) */ -+#define SYS0_SR_PLL1LOCK (0x1 << 17) -+#define SYS0_SR_PLL1LOCK_GET(val) ((((val) & SYS0_SR_PLL1LOCK) >> 17) & 0x1) -+/* Discrete Timing Oscillator Lock (16) */ -+#define SYS0_SR_DTOLOCK (0x1 << 16) -+#define SYS0_SR_DTOLOCK_GET(val) ((((val) & SYS0_SR_DTOLOCK) >> 16) & 0x1) -+/* Hardware Reset Indication (1) */ -+#define SYS0_SR_HRSTIN (0x1 << 1) -+#define SYS0_SR_HRSTIN_VAL(val) (((val) & 0x1) << 1) -+#define SYS0_SR_HRSTIN_GET(val) ((((val) & SYS0_SR_HRSTIN) >> 1) & 0x1) -+#define SYS0_SR_HRSTIN_SET(reg,val) (reg) = ((reg & ~SYS0_SR_HRSTIN) | (((val) & 0x1) << 1)) -+/* Power-on Reset Indication (0) */ -+#define SYS0_SR_POR (0x1 << 0) -+#define SYS0_SR_POR_VAL(val) (((val) & 0x1) << 0) -+#define SYS0_SR_POR_GET(val) ((((val) & SYS0_SR_POR) >> 0) & 0x1) -+#define SYS0_SR_POR_SET(reg,val) (reg) = ((reg & ~SYS0_SR_POR) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * SYS0 Boot Control Register -+ ******************************************************************************/ -+ -+/* Configuration of Boot Source for CPU5 (25) */ -+#define SYS0_BCR_BMODECPU5 (0x1 << 25) -+#define SYS0_BCR_BMODECPU5_VAL(val) (((val) & 0x1) << 25) -+#define SYS0_BCR_BMODECPU5_GET(val) ((((val) & SYS0_BCR_BMODECPU5) >> 25) & 0x1) -+#define SYS0_BCR_BMODECPU5_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU5) | (((val) & 0x1) << 25)) -+/* Configuration of Boot Source for CPU4 (24) */ -+#define SYS0_BCR_BMODECPU4 (0x1 << 24) -+#define SYS0_BCR_BMODECPU4_VAL(val) (((val) & 0x1) << 24) -+#define SYS0_BCR_BMODECPU4_GET(val) ((((val) & SYS0_BCR_BMODECPU4) >> 24) & 0x1) -+#define SYS0_BCR_BMODECPU4_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU4) | (((val) & 0x1) << 24)) -+/* Configuration of Boot Source for CPU3 (23) */ -+#define SYS0_BCR_BMODECPU3 (0x1 << 23) -+#define SYS0_BCR_BMODECPU3_VAL(val) (((val) & 0x1) << 23) -+#define SYS0_BCR_BMODECPU3_GET(val) ((((val) & SYS0_BCR_BMODECPU3) >> 23) & 0x1) -+#define SYS0_BCR_BMODECPU3_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU3) | (((val) & 0x1) << 23)) -+/* Configuration of Boot Source for CPU2 (22) */ -+#define SYS0_BCR_BMODECPU2 (0x1 << 22) -+#define SYS0_BCR_BMODECPU2_VAL(val) (((val) & 0x1) << 22) -+#define SYS0_BCR_BMODECPU2_GET(val) ((((val) & SYS0_BCR_BMODECPU2) >> 22) & 0x1) -+#define SYS0_BCR_BMODECPU2_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU2) | (((val) & 0x1) << 22)) -+/* Configuration of Boot Source for CPU1 (21) */ -+#define SYS0_BCR_BMODECPU1 (0x1 << 21) -+#define SYS0_BCR_BMODECPU1_VAL(val) (((val) & 0x1) << 21) -+#define SYS0_BCR_BMODECPU1_GET(val) ((((val) & SYS0_BCR_BMODECPU1) >> 21) & 0x1) -+#define SYS0_BCR_BMODECPU1_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU1) | (((val) & 0x1) << 21)) -+/* Configuration of Boot Source for CPU0 (20:16) */ -+#define SYS0_BCR_BMODECPU0 (0x1f << 16) -+#define SYS0_BCR_BMODECPU0_VAL(val) (((val) & 0x1f) << 16) -+#define SYS0_BCR_BMODECPU0_GET(val) ((((val) & SYS0_BCR_BMODECPU0) >> 16) & 0x1f) -+#define SYS0_BCR_BMODECPU0_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU0) | (((val) & 0x1f) << 16)) -+/* Configuration of Endianess for CPU5 (5) */ -+#define SYS0_BCR_ESELCPU5 (0x1 << 5) -+#define SYS0_BCR_ESELCPU5_VAL(val) (((val) & 0x1) << 5) -+#define SYS0_BCR_ESELCPU5_GET(val) ((((val) & SYS0_BCR_ESELCPU5) >> 5) & 0x1) -+#define SYS0_BCR_ESELCPU5_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU5) | (((val) & 0x1) << 5)) -+/* Configuration of Endianess for CPU4 (4) */ -+#define SYS0_BCR_ESELCPU4 (0x1 << 4) -+#define SYS0_BCR_ESELCPU4_VAL(val) (((val) & 0x1) << 4) -+#define SYS0_BCR_ESELCPU4_GET(val) ((((val) & SYS0_BCR_ESELCPU4) >> 4) & 0x1) -+#define SYS0_BCR_ESELCPU4_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU4) | (((val) & 0x1) << 4)) -+/* Configuration of Endianess for CPU3 (3) */ -+#define SYS0_BCR_ESELCPU3 (0x1 << 3) -+#define SYS0_BCR_ESELCPU3_VAL(val) (((val) & 0x1) << 3) -+#define SYS0_BCR_ESELCPU3_GET(val) ((((val) & SYS0_BCR_ESELCPU3) >> 3) & 0x1) -+#define SYS0_BCR_ESELCPU3_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU3) | (((val) & 0x1) << 3)) -+/* Configuration of Endianess for CPU2 (2) */ -+#define SYS0_BCR_ESELCPU2 (0x1 << 2) -+#define SYS0_BCR_ESELCPU2_VAL(val) (((val) & 0x1) << 2) -+#define SYS0_BCR_ESELCPU2_GET(val) ((((val) & SYS0_BCR_ESELCPU2) >> 2) & 0x1) -+#define SYS0_BCR_ESELCPU2_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU2) | (((val) & 0x1) << 2)) -+/* Configuration of Endianess for CPU1 (1) */ -+#define SYS0_BCR_ESELCPU1 (0x1 << 1) -+#define SYS0_BCR_ESELCPU1_VAL(val) (((val) & 0x1) << 1) -+#define SYS0_BCR_ESELCPU1_GET(val) ((((val) & SYS0_BCR_ESELCPU1) >> 1) & 0x1) -+#define SYS0_BCR_ESELCPU1_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU1) | (((val) & 0x1) << 1)) -+/* Configuration of Endianess for CPU0 (0) */ -+#define SYS0_BCR_ESELCPU0 (0x1) -+#define SYS0_BCR_ESELCPU0_VAL(val) (((val) & 0x1) << 0) -+#define SYS0_BCR_ESELCPU0_GET(val) ((((val) & SYS0_BCR_ESELCPU0) >> 0) & 0x1) -+#define SYS0_BCR_ESELCPU0_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU0) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * PLL1 Control Register -+ ******************************************************************************/ -+ -+/* PLL1 Bypass Enable (31) */ -+#define SYS0_PLL1CR_OSCBYP (0x1 << 31) -+#define SYS0_PLL1CR_OSCBYP_VAL(val) (((val) & 0x1) << 31) -+#define SYS0_PLL1CR_OSCBYP_GET(val) ((((val) & SYS0_PLL1CR_OSCBYP) >> 31) & 0x1) -+#define SYS0_PLL1CR_OSCBYP_SET(reg,val) (reg) = ((reg & ~SYS0_PLL1CR_OSCBYP) | (((val) & 0x1) << 31)) -+/* PLL1 Divider Value (1:0) */ -+#define SYS0_PLL1CR_PLLDIV (0x3) -+#define SYS0_PLL1CR_PLLDIV_VAL(val) (((val) & 0x3) << 0) -+#define SYS0_PLL1CR_PLLDIV_GET(val) ((((val) & SYS0_PLL1CR_PLLDIV) >> 0) & 0x3) -+#define SYS0_PLL1CR_PLLDIV_SET(reg,val) (reg) = ((reg & ~SYS0_PLL1CR_PLLDIV) | (((val) & 0x3) << 0)) -+ -+/******************************************************************************* -+ * PLL2 Control Register -+ ******************************************************************************/ -+ -+/* PLL2 clear deepsleep (31) */ -+#define SYS0_PLL2CR_CLRDS (0x1 << 31) -+#define SYS0_PLL2CR_CLRDS_VAL(val) (((val) & 0x1) << 31) -+#define SYS0_PLL2CR_CLRDS_GET(val) ((((val) & SYS0_PLL2CR_CLRDS) >> 31) & 0x1) -+#define SYS0_PLL2CR_CLRDS_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_CLRDS) | (((val) & 0x1) << 31)) -+/* PLL2 set deepsleep (30) */ -+#define SYS0_PLL2CR_SETDS (0x1 << 30) -+#define SYS0_PLL2CR_SETDS_VAL(val) (((val) & 0x1) << 30) -+#define SYS0_PLL2CR_SETDS_GET(val) ((((val) & SYS0_PLL2CR_SETDS) >> 30) & 0x1) -+#define SYS0_PLL2CR_SETDS_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_SETDS) | (((val) & 0x1) << 30)) -+/* PLL2 Fractional division enable (16) */ -+#define SYS0_PLL2CR_FRACTEN (0x1 << 16) -+#define SYS0_PLL2CR_FRACTEN_VAL(val) (((val) & 0x1) << 16) -+#define SYS0_PLL2CR_FRACTEN_GET(val) ((((val) & SYS0_PLL2CR_FRACTEN) >> 16) & 0x1) -+#define SYS0_PLL2CR_FRACTEN_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_FRACTEN) | (((val) & 0x1) << 16)) -+/* PLL2 Fractional division value (9:0) */ -+#define SYS0_FRACTVAL (0x3f) -+#define SYS0_FRACTVAL_VAL(val) (((val) & 0x3f) << 0) -+#define SYS0_FRACTVAL_GET(val) ((((val) & SYS0_FRACTVAL) >> 0) & 0x3f) -+#define SYS0_FRACTVAL_SET(reg,val) (reg) = ((reg & ~SYS0_FRACTVAL) | (((val) & 0x3f) << 0)) -+ -+#endif -Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/dma_reg.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/dma_reg.h 2012-07-31 15:46:02.480476158 +0200 -@@ -0,0 +1,308 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2007 -+ Infineon Technologies AG -+ St. Martin Strasse 53; 81669 Munich, Germany -+ -+ Any use of this Software is subject to the conclusion of a respective -+ License Agreement. Without such a License Agreement no rights to the -+ Software are granted. -+ -+ ******************************************************************************/ -+ -+#ifndef __DMA_REG_H -+#define __DMA_REG_H -+ -+#define dma_r32(reg) ltq_r32(&dma->reg) -+#define dma_w32(val, reg) ltq_w32(val, &dma->reg) -+#define dma_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &dma->reg) -+ -+/** DMA register structure */ -+struct svip_reg_dma { -+ volatile unsigned long clc; /* 0x00 */ -+ volatile unsigned long reserved0; /* 0x04 */ -+ volatile unsigned long id; /* 0x08 */ -+ volatile unsigned long reserved1; /* 0x0c */ -+ volatile unsigned long ctrl; /* 0x10 */ -+ volatile unsigned long cpoll; /* 0x14 */ -+ volatile unsigned long cs; /* 0x18 */ -+ volatile unsigned long cctrl; /* 0x1C */ -+ volatile unsigned long cdba; /* 0x20 */ -+ volatile unsigned long cdlen; /* 0x24 */ -+ volatile unsigned long cis; /* 0x28 */ -+ volatile unsigned long cie; /* 0x2C */ -+ volatile unsigned long cgbl; /* 0x30 */ -+ volatile unsigned long reserved2[3]; /* 0x34 */ -+ volatile unsigned long ps; /* 0x40 */ -+ volatile unsigned long pctrl; /* 0x44 */ -+ volatile unsigned long reserved3[43]; /* 0x48 */ -+ volatile unsigned long irnen; /* 0xF4 */ -+ volatile unsigned long irncr; /* 0xF8 */ -+ volatile unsigned long irnicr; /* 0xFC */ -+}; -+ -+/******************************************************************************* -+ * CLC Register -+ ******************************************************************************/ -+ -+/* Fast Shut-Off Enable Bit (5) */ -+#define DMA_CLC_FSOE (0x1 << 5) -+#define DMA_CLC_FSOE_VAL(val) (((val) & 0x1) << 5) -+#define DMA_CLC_FSOE_GET(val) ((((val) & DMA_CLC_FSOE) >> 5) & 0x1) -+#define DMA_CLC_FSOE_SET(reg,val) (reg) = ((reg & ~DMA_CLC_FSOE) | (((val) & 0x1) << 5)) -+/* Suspend Bit Write Enable for OCDS (4) */ -+#define DMA_CLC_SBWE (0x1 << 4) -+#define DMA_CLC_SBWE_VAL(val) (((val) & 0x1) << 4) -+#define DMA_CLC_SBWE_SET(reg,val) (reg) = (((reg & ~DMA_CLC_SBWE) | (val) & 1) << 4) -+/* External Request Disable (3) */ -+#define DMA_CLC_EDIS (0x1 << 3) -+#define DMA_CLC_EDIS_VAL(val) (((val) & 0x1) << 3) -+#define DMA_CLC_EDIS_GET(val) ((((val) & DMA_CLC_EDIS) >> 3) & 0x1) -+#define DMA_CLC_EDIS_SET(reg,val) (reg) = ((reg & ~DMA_CLC_EDIS) | (((val) & 0x1) << 3)) -+/* Suspend Enable Bit for OCDS (2) */ -+#define DMA_CLC_SPEN (0x1 << 2) -+#define DMA_CLC_SPEN_VAL(val) (((val) & 0x1) << 2) -+#define DMA_CLC_SPEN_GET(val) ((((val) & DMA_CLC_SPEN) >> 2) & 0x1) -+#define DMA_CLC_SPEN_SET(reg,val) (reg) = ((reg & ~DMA_CLC_SPEN) | (((val) & 0x1) << 2)) -+/* Disable Status Bit (1) */ -+#define DMA_CLC_DISS (0x1 << 1) -+#define DMA_CLC_DISS_GET(val) ((((val) & DMA_CLC_DISS) >> 1) & 0x1) -+/* Disable Request Bit (0) */ -+#define DMA_CLC_DISR (0x1) -+#define DMA_CLC_DISR_VAL(val) (((val) & 0x1) << 0) -+#define DMA_CLC_DISR_GET(val) ((((val) & DMA_CLC_DISR) >> 0) & 0x1) -+#define DMA_CLC_DISR_SET(reg,val) (reg) = ((reg & ~DMA_CLC_DISR) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * ID Register -+ ******************************************************************************/ -+ -+/* Number of Channels (25:20) */ -+#define DMA_ID_CHNR (0x3f << 20) -+#define DMA_ID_CHNR_GET(val) ((((val) & DMA_ID_CHNR) >> 20) & 0x3f) -+/* Number of Ports (19:16) */ -+#define DMA_ID_PRTNR (0xf << 16) -+#define DMA_ID_PRTNR_GET(val) ((((val) & DMA_ID_PRTNR) >> 16) & 0xf) -+/* Module ID (15:8) */ -+#define DMA_ID_ID (0xff << 8) -+#define DMA_ID_ID_GET(val) ((((val) & DMA_ID_ID) >> 8) & 0xff) -+/* Revision (4:0) */ -+#define DMA_ID_REV (0x1f) -+#define DMA_ID_REV_GET(val) ((((val) & DMA_ID_REV) >> 0) & 0x1f) -+ -+/******************************************************************************* -+ * Control Register -+ ******************************************************************************/ -+ -+/* Global Software Reset (0) */ -+#define DMA_CTRL_RST (0x1) -+#define DMA_CTRL_RST_GET(val) ((((val) & DMA_CTRL_RST) >> 0) & 0x1) -+ -+/******************************************************************************* -+ * Channel Polling Register -+ ******************************************************************************/ -+ -+/* Enable (31) */ -+#define DMA_CPOLL_EN (0x1 << 31) -+#define DMA_CPOLL_EN_VAL(val) (((val) & 0x1) << 31) -+#define DMA_CPOLL_EN_GET(val) ((((val) & DMA_CPOLL_EN) >> 31) & 0x1) -+#define DMA_CPOLL_EN_SET(reg,val) (reg) = ((reg & ~DMA_CPOLL_EN) | (((val) & 0x1) << 31)) -+/* Counter (15:4) */ -+#define DMA_CPOLL_CNT (0xfff << 4) -+#define DMA_CPOLL_CNT_VAL(val) (((val) & 0xfff) << 4) -+#define DMA_CPOLL_CNT_GET(val) ((((val) & DMA_CPOLL_CNT) >> 4) & 0xfff) -+#define DMA_CPOLL_CNT_SET(reg,val) (reg) = ((reg & ~DMA_CPOLL_CNT) | (((val) & 0xfff) << 4)) -+ -+/******************************************************************************* -+ * Global Buffer Length Register -+ ******************************************************************************/ -+ -+/* Global Buffer Length (15:0) */ -+#define DMA_CGBL_GBL (0xffff) -+#define DMA_CGBL_GBL_VAL(val) (((val) & 0xffff) << 0) -+#define DMA_CGBL_GBL_GET(val) ((((val) & DMA_CGBL_GBL) >> 0) & 0xffff) -+#define DMA_CGBL_GBL_SET(reg,val) (reg) = ((reg & ~DMA_CGBL_GBL) | (((val) & 0xffff) << 0)) -+ -+/******************************************************************************* -+ * Channel Select Register -+ ******************************************************************************/ -+ -+/* Channel Selection (4:0) */ -+#define DMA_CS_CS (0x1f) -+#define DMA_CS_CS_VAL(val) (((val) & 0x1f) << 0) -+#define DMA_CS_CS_GET(val) ((((val) & DMA_CS_CS) >> 0) & 0x1f) -+#define DMA_CS_CS_SET(reg,val) (reg) = ((reg & ~DMA_CS_CS) | (((val) & 0x1f) << 0)) -+ -+/******************************************************************************* -+ * Channel Control Register -+ ******************************************************************************/ -+ -+/* Peripheral to Peripheral Copy (24) */ -+#define DMA_CCTRL_P2PCPY (0x1 << 24) -+#define DMA_CCTRL_P2PCPY_VAL(val) (((val) & 0x1) << 24) -+#define DMA_CCTRL_P2PCPY_GET(val) ((((val) & DMA_CCTRL_P2PCPY) >> 24) & 0x1) -+#define DMA_CCTRL_P2PCPY_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_P2PCPY) | (((val) & 0x1) << 24)) -+/* Channel Weight for Transmit Direction (17:16) */ -+#define DMA_CCTRL_TXWGT (0x3 << 16) -+#define DMA_CCTRL_TXWGT_VAL(val) (((val) & 0x3) << 16) -+#define DMA_CCTRL_TXWGT_GET(val) ((((val) & DMA_CCTRL_TXWGT) >> 16) & 0x3) -+#define DMA_CCTRL_TXWGT_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_TXWGT) | (((val) & 0x3) << 16)) -+/* Port Assignment (13:11) */ -+#define DMA_CCTRL_PRTNR (0x7 << 11) -+#define DMA_CCTRL_PRTNR_GET(val) ((((val) & DMA_CCTRL_PRTNR) >> 11) & 0x7) -+/* Class (10:9) */ -+#define DMA_CCTRL_CLASS (0x3 << 9) -+#define DMA_CCTRL_CLASS_VAL(val) (((val) & 0x3) << 9) -+#define DMA_CCTRL_CLASS_GET(val) ((((val) & DMA_CCTRL_CLASS) >> 9) & 0x3) -+#define DMA_CCTRL_CLASS_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_CLASS) | (((val) & 0x3) << 9)) -+/* Direction (8) */ -+#define DMA_CCTRL_DIR (0x1 << 8) -+#define DMA_CCTRL_DIR_GET(val) ((((val) & DMA_CCTRL_DIR) >> 8) & 0x1) -+/* Reset (1) */ -+#define DMA_CCTRL_RST (0x1 << 1) -+#define DMA_CCTRL_RST_VAL(val) (((val) & 0x1) << 1) -+#define DMA_CCTRL_RST_GET(val) ((((val) & DMA_CCTRL_RST) >> 1) & 0x1) -+#define DMA_CCTRL_RST_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_RST) | (((val) & 0x1) << 1)) -+/* Channel On or Off (0) */ -+#define DMA_CCTRL_ON_OFF (0x1) -+#define DMA_CCTRL_ON_OFF_VAL(val) (((val) & 0x1) << 0) -+#define DMA_CCTRL_ON_OFF_GET(val) ((((val) & DMA_CCTRL_ON_OFF) >> 0) & 0x1) -+#define DMA_CCTRL_ON_OFF_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_ON_OFF) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Channel Descriptor Base Address Register -+ ******************************************************************************/ -+ -+/* Channel Descriptor Base Address (29:3) */ -+#define DMA_CDBA_CDBA (0x7ffffff << 3) -+#define DMA_CDBA_CDBA_VAL(val) (((val) & 0x7ffffff) << 3) -+#define DMA_CDBA_CDBA_GET(val) ((((val) & DMA_CDBA_CDBA) >> 3) & 0x7ffffff) -+#define DMA_CDBA_CDBA_SET(reg,val) (reg) = ((reg & ~DMA_CDBA_CDBA) | (((val) & 0x7ffffff) << 3)) -+ -+/******************************************************************************* -+ * Channel Descriptor Length Register -+ ******************************************************************************/ -+ -+/* Channel Descriptor Length (7:0) */ -+#define DMA_CDLEN_CDLEN (0xff) -+#define DMA_CDLEN_CDLEN_VAL(val) (((val) & 0xff) << 0) -+#define DMA_CDLEN_CDLEN_GET(val) ((((val) & DMA_CDLEN_CDLEN) >> 0) & 0xff) -+#define DMA_CDLEN_CDLEN_SET(reg,val) (reg) = ((reg & ~DMA_CDLEN_CDLEN) | (((val) & 0xff) << 0)) -+ -+/******************************************************************************* -+ * Channel Interrupt Status Register -+ ******************************************************************************/ -+ -+/* SAI Read Error Interrupt (5) */ -+#define DMA_CIS_RDERR (0x1 << 5) -+#define DMA_CIS_RDERR_GET(val) ((((val) & DMA_CIS_RDERR) >> 5) & 0x1) -+/* Channel Off Interrupt (4) */ -+#define DMA_CIS_CHOFF (0x1 << 4) -+#define DMA_CIS_CHOFF_GET(val) ((((val) & DMA_CIS_CHOFF) >> 4) & 0x1) -+/* Descriptor Complete Interrupt (3) */ -+#define DMA_CIS_DESCPT (0x1 << 3) -+#define DMA_CIS_DESCPT_GET(val) ((((val) & DMA_CIS_DESCPT) >> 3) & 0x1) -+/* Descriptor Under-Run Interrupt (2) */ -+#define DMA_CIS_DUR (0x1 << 2) -+#define DMA_CIS_DUR_GET(val) ((((val) & DMA_CIS_DUR) >> 2) & 0x1) -+/* End of Packet Interrupt (1) */ -+#define DMA_CIS_EOP (0x1 << 1) -+#define DMA_CIS_EOP_GET(val) ((((val) & DMA_CIS_EOP) >> 1) & 0x1) -+ -+/******************************************************************************* -+ * Channel Interrupt Enable Register -+ ******************************************************************************/ -+ -+/* SAI Read Error Interrupt (5) */ -+#define DMA_CIE_RDERR (0x1 << 5) -+#define DMA_CIE_RDERR_GET(val) ((((val) & DMA_CIE_RDERR) >> 5) & 0x1) -+/* Channel Off Interrupt (4) */ -+#define DMA_CIE_CHOFF (0x1 << 4) -+#define DMA_CIE_CHOFF_GET(val) ((((val) & DMA_CIE_CHOFF) >> 4) & 0x1) -+/* Descriptor Complete Interrupt Enable (3) */ -+#define DMA_CIE_DESCPT (0x1 << 3) -+#define DMA_CIE_DESCPT_GET(val) ((((val) & DMA_CIE_DESCPT) >> 3) & 0x1) -+/* Descriptor Under Run Interrupt Enable (2) */ -+#define DMA_CIE_DUR (0x1 << 2) -+#define DMA_CIE_DUR_GET(val) ((((val) & DMA_CIE_DUR) >> 2) & 0x1) -+/* End of Packet Interrupt Enable (1) */ -+#define DMA_CIE_EOP (0x1 << 1) -+#define DMA_CIE_EOP_GET(val) ((((val) & DMA_CIE_EOP) >> 1) & 0x1) -+ -+/******************************************************************************* -+ * Port Select Register -+ ******************************************************************************/ -+ -+/* Port Selection (2:0) */ -+#define DMA_PS_PS (0x7) -+#define DMA_PS_PS_VAL(val) (((val) & 0x7) << 0) -+#define DMA_PS_PS_GET(val) ((((val) & DMA_PS_PS) >> 0) & 0x7) -+#define DMA_PS_PS_SET(reg,val) (reg) = ((reg & ~DMA_PS_PS) | (((val) & 0x7) << 0)) -+ -+/******************************************************************************* -+ * Port Control Register -+ ******************************************************************************/ -+ -+/* General Purpose Control (16) */ -+#define DMA_PCTRL_GPC (0x1 << 16) -+#define DMA_PCTRL_GPC_VAL(val) (((val) & 0x1) << 16) -+#define DMA_PCTRL_GPC_GET(val) ((((val) & DMA_PCTRL_GPC) >> 16) & 0x1) -+#define DMA_PCTRL_GPC_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_GPC) | (((val) & 0x1) << 16)) -+/* Port Weight for Transmit Direction (14:12) */ -+#define DMA_PCTRL_TXWGT (0x7 << 12) -+#define DMA_PCTRL_TXWGT_VAL(val) (((val) & 0x7) << 12) -+#define DMA_PCTRL_TXWGT_GET(val) ((((val) & DMA_PCTRL_TXWGT) >> 12) & 0x7) -+#define DMA_PCTRL_TXWGT_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXWGT) | (((val) & 0x7) << 12)) -+/* Endianness for Transmit Direction (11:10) */ -+#define DMA_PCTRL_TXENDI (0x3 << 10) -+#define DMA_PCTRL_TXENDI_VAL(val) (((val) & 0x3) << 10) -+#define DMA_PCTRL_TXENDI_GET(val) ((((val) & DMA_PCTRL_TXENDI) >> 10) & 0x3) -+#define DMA_PCTRL_TXENDI_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXENDI) | (((val) & 0x3) << 10)) -+/* Endianness for Receive Direction (9:8) */ -+#define DMA_PCTRL_RXENDI (0x3 << 8) -+#define DMA_PCTRL_RXENDI_VAL(val) (((val) & 0x3) << 8) -+#define DMA_PCTRL_RXENDI_GET(val) ((((val) & DMA_PCTRL_RXENDI) >> 8) & 0x3) -+#define DMA_PCTRL_RXENDI_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_RXENDI) | (((val) & 0x3) << 8)) -+/* Packet Drop Enable (6) */ -+#define DMA_PCTRL_PDEN (0x1 << 6) -+#define DMA_PCTRL_PDEN_VAL(val) (((val) & 0x1) << 6) -+#define DMA_PCTRL_PDEN_GET(val) ((((val) & DMA_PCTRL_PDEN) >> 6) & 0x1) -+#define DMA_PCTRL_PDEN_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_PDEN) | (((val) & 0x1) << 6)) -+/* Burst Length for Transmit Direction (5:4) */ -+#define DMA_PCTRL_TXBL (0x3 << 4) -+#define DMA_PCTRL_TXBL_VAL(val) (((val) & 0x3) << 4) -+#define DMA_PCTRL_TXBL_GET(val) ((((val) & DMA_PCTRL_TXBL) >> 4) & 0x3) -+#define DMA_PCTRL_TXBL_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXBL) | (((val) & 0x3) << 4)) -+/* Burst Length for Receive Direction (3:2) */ -+#define DMA_PCTRL_RXBL (0x3 << 2) -+#define DMA_PCTRL_RXBL_VAL(val) (((val) & 0x3) << 2) -+#define DMA_PCTRL_RXBL_GET(val) ((((val) & DMA_PCTRL_RXBL) >> 2) & 0x3) -+#define DMA_PCTRL_RXBL_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_RXBL) | (((val) & 0x3) << 2)) -+ -+/******************************************************************************* -+ * DMA_IRNEN Register -+ ******************************************************************************/ -+ -+/* Channel x Interrupt Request Enable (23) */ -+#define DMA_IRNEN_CH23 (0x1 << 23) -+#define DMA_IRNEN_CH23_VAL(val) (((val) & 0x1) << 23) -+#define DMA_IRNEN_CH23_GET(val) ((((val) & DMA_IRNEN_CH23) >> 23) & 0x1) -+#define DMA_IRNEN_CH23_SET(reg,val) (reg) = ((reg & ~DMA_IRNEN_CH23) | (((val) & 0x1) << 23)) -+ -+/******************************************************************************* -+ * DMA_IRNCR Register -+ ******************************************************************************/ -+ -+/* Channel x Interrupt (23) */ -+#define DMA_IRNCR_CH23 (0x1 << 23) -+#define DMA_IRNCR_CH23_GET(val) ((((val) & DMA_IRNCR_CH23) >> 23) & 0x1) -+ -+/******************************************************************************* -+ * DMA_IRNICR Register -+ ******************************************************************************/ -+ -+/* Channel x Interrupt Request (23) */ -+#define DMA_IRNICR_CH23 (0x1 << 23) -+#define DMA_IRNICR_CH23_GET(val) ((((val) & DMA_IRNICR_CH23) >> 23) & 0x1) -+ -+#endif -Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/svip_dma.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/svip_dma.h 2012-07-31 15:46:02.480476158 +0200 -@@ -0,0 +1,245 @@ -+/************************************************************************ -+ * -+ * Copyright (c) 2007 -+ * Infineon Technologies AG -+ * St. Martin Strasse 53; 81669 Muenchen; Germany -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ * -+ ************************************************************************/ -+ -+#ifndef __SVIP_DMA_H -+#define __SVIP_DMA_H -+ -+#define LTQ_DMA_CH_ON 1 -+#define LTQ_DMA_CH_OFF 0 -+#define LTQ_DMA_CH_DEFAULT_WEIGHT 100; -+ -+#define DMA_OWN 1 -+#define CPU_OWN 0 -+#define DMA_MAJOR 250 -+ -+/* Descriptors */ -+#define DMA_DESC_OWN_CPU 0x0 -+#define DMA_DESC_OWN_DMA 0x80000000 -+#define DMA_DESC_CPT_SET 0x40000000 -+#define DMA_DESC_SOP_SET 0x20000000 -+#define DMA_DESC_EOP_SET 0x10000000 -+ -+struct rx_desc { -+ union { -+ struct { -+#ifdef CONFIG_CPU_LITTLE_ENDIAN -+ volatile u32 data_length:16; -+ volatile u32 reserve2:7; -+ volatile u32 byte_offset:2; -+ volatile u32 reserve1:3; -+ volatile u32 eop:1; -+ volatile u32 sop:1; -+ volatile u32 c:1; -+ volatile u32 own:1; -+#else -+ volatile u32 own:1; -+ volatile u32 c:1; -+ volatile u32 sop:1; -+ volatile u32 eop:1; -+ volatile u32 reserve1:3; -+ volatile u32 byte_offset:2; -+ volatile u32 reserve2:7; -+ volatile u32 data_length:16; -+#endif -+ } field; -+ -+ volatile u32 word; -+ } status; -+ -+ volatile u32 data_pointer; -+}; -+ -+struct tx_desc { -+ union { -+ struct { -+#ifdef CONFIG_CPU_LITTLE_ENDIAN -+ volatile u32 data_length:16; -+ volatile u32 reserved:7; -+ volatile u32 byte_offset:5; -+ volatile u32 eop:1; -+ volatile u32 sop:1; -+ volatile u32 c:1; -+ volatile u32 own:1; -+#else -+ volatile u32 own:1; -+ volatile u32 c:1; -+ volatile u32 sop:1; -+ volatile u32 eop:1; -+ volatile u32 byte_offset:5; -+ volatile u32 reserved:7; -+ volatile u32 data_length:16; -+#endif -+ } field; -+ -+ volatile u32 word; -+ } status; -+ -+ volatile u32 data_pointer; -+}; -+ -+/* DMA pseudo interrupts notified to switch driver */ -+#define RCV_INT 0x01 -+#define TX_BUF_FULL_INT 0x02 -+#define TRANSMIT_CPT_INT 0x04 -+#define CHANNEL_CLOSED 0x10 -+ -+/* Parameters for switch DMA device */ -+#define DEFAULT_SW_CHANNEL_WEIGHT 3 -+#define DEFAULT_SW_PORT_WEIGHT 7 -+ -+#define DEFAULT_SW_TX_BURST_LEN 2 /* 2 words, 4 words, 8 words */ -+#define DEFAULT_SW_RX_BURST_LEN 2 /* 2 words, 4 words, 8 words */ -+ -+#define DEFAULT_SW_TX_CHANNEL_NUM 4 -+#define DEFAULT_SW_RX_CHANNEL_NUM 4 -+ -+#define DEFAULT_SW_TX_CHANNEL_DESCR_NUM 20 -+#define DEFAULT_SW_RX_CHANNEL_DESCR_NUM 20 -+ -+/* Parameters for SSC DMA device */ -+#define DEFAULT_SSC_CHANNEL_WEIGHT 3 -+#define DEFAULT_SSC_PORT_WEIGHT 7 -+ -+#define DEFAULT_SSC_TX_CHANNEL_CLASS 3 -+#define DEFAULT_SSC_RX_CHANNEL_CLASS 0 -+ -+#define DEFAULT_SSC_TX_BURST_LEN 2 /* 2 words, 4 words, 8 words */ -+#define DEFAULT_SSC_RX_BURST_LEN 2 /* 2 words, 4 words, 8 words */ -+ -+#define DEFAULT_SSC0_TX_CHANNEL_NUM 1 -+#define DEFAULT_SSC0_RX_CHANNEL_NUM 1 -+#define DEFAULT_SSC1_TX_CHANNEL_NUM 1 -+#define DEFAULT_SSC1_RX_CHANNEL_NUM 1 -+ -+#define DEFAULT_SSC_TX_CHANNEL_DESCR_NUM 10 -+#define DEFAULT_SSC_RX_CHANNEL_DESCR_NUM 10 -+ -+/* Parameters for memory DMA device */ -+#define DEFAULT_MEM_CHANNEL_WEIGHT 3 -+#define DEFAULT_MEM_PORT_WEIGHT 7 -+ -+#define DEFAULT_MEM_TX_BURST_LEN 4 /* 2 words, 4 words, 8 words */ -+#define DEFAULT_MEM_RX_BURST_LEN 4 /* 2 words, 4 words, 8 words */ -+ -+#define DEFAULT_MEM_TX_CHANNEL_NUM 1 -+#define DEFAULT_MEM_RX_CHANNEL_NUM 1 -+ -+#define DEFAULT_MEM_TX_CHANNEL_DESCR_NUM 2 -+#define DEFAULT_MEM_RX_CHANNEL_DESCR_NUM 2 -+ -+/* Parameters for DEU DMA device */ -+#define DEFAULT_DEU_CHANNEL_WEIGHT 1 -+#define DEFAULT_DEU_PORT_WEIGHT 1 -+ -+#define DEFAULT_DEU_TX_BURST_LEN 4 /* 2 words, 4 words, 8 words */ -+#define DEFAULT_DEU_RX_BURST_LEN 4 /* 2 words, 4 words, 8 words */ -+ -+#define DEFAULT_DEU_TX_CHANNEL_DESCR_NUM 20 -+#define DEFAULT_DEU_RX_CHANNEL_DESCR_NUM 20 -+ -+#define DMA_DESCR_NUM 30 /* number of descriptors per channel */ -+ -+enum dma_dir_t { -+ DIR_RX = 0, -+ DIR_TX = 1, -+}; -+ -+struct dma_device_info; -+ -+struct dma_channel_info { -+ /*Pointer to the peripheral device who is using this channel*/ -+ /*const*/ struct dma_device_info *dma_dev; -+ /*direction*/ -+ const enum dma_dir_t dir; /*RX or TX*/ -+ /*class for this channel for QoS*/ -+ int pri; -+ /*irq number*/ -+ const int irq; -+ /*relative channel number*/ -+ const int rel_chan_no; -+ /*absolute channel number*/ -+ int abs_chan_no; -+ -+ /*specify byte_offset*/ -+ int byte_offset; -+ int tx_weight; -+ -+ /*descriptor parameter*/ -+ int desc_base; -+ int desc_len; -+ int curr_desc; -+ int prev_desc;/*only used if it is a tx channel*/ -+ -+ /*weight setting for WFQ algorithm*/ -+ int weight; -+ int default_weight; -+ -+ int packet_size; -+ -+ /*status of this channel*/ -+ int control; /*on or off*/ -+ int xfer_cnt; -+ int dur; /*descriptor underrun*/ -+ -+ /**optional information for the upper layer devices*/ -+ void *opt[DMA_DESCR_NUM]; -+ -+ /*channel operations*/ -+ int (*open)(struct dma_channel_info *ch); -+ int (*close)(struct dma_channel_info *ch); -+ int (*reset)(struct dma_channel_info *ch); -+ void (*enable_irq)(struct dma_channel_info *ch); -+ void (*disable_irq)(struct dma_channel_info *ch); -+}; -+ -+ -+struct dma_device_info { -+ /*device name of this peripheral*/ -+ const char device_name[16]; -+ const int max_rx_chan_num; -+ const int max_tx_chan_num; -+ int drop_enable; -+ -+ int reserved; -+ -+ int tx_burst_len; -+ int rx_burst_len; -+ int tx_weight; -+ -+ int current_tx_chan; -+ int current_rx_chan; -+ int num_tx_chan; -+ int num_rx_chan; -+ int tx_endianness_mode; -+ int rx_endianness_mode; -+ struct dma_channel_info *tx_chan[4]; -+ struct dma_channel_info *rx_chan[4]; -+ -+ /*functions, optional*/ -+ u8 *(*buffer_alloc)(int len,int *offset, void **opt); -+ void (*buffer_free)(u8 *dataptr, void *opt); -+ int (*intr_handler)(struct dma_device_info *dma_dev, int status); -+ -+ /* used by peripheral driver only */ -+ void *priv; -+}; -+ -+struct dma_device_info *dma_device_reserve(char *dev_name); -+int dma_device_release(struct dma_device_info *dma_dev); -+int dma_device_register(struct dma_device_info *dma_dev); -+int dma_device_unregister(struct dma_device_info *dma_dev); -+int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt); -+int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, -+ int len, void *opt); -+ -+#endif -Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/ebu_reg.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/ebu_reg.h 2012-07-31 15:46:02.484476159 +0200 -@@ -0,0 +1,615 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2007 -+ Infineon Technologies AG -+ St. Martin Strasse 53; 81669 Munich, Germany -+ -+ Any use of this Software is subject to the conclusion of a respective -+ License Agreement. Without such a License Agreement no rights to the -+ Software are granted. -+ -+ ******************************************************************************/ -+ -+#ifndef __EBU_REG_H -+#define __EBU_REG_H -+ -+#define ebu_r32(reg) ltq_r32(&ebu->reg) -+#define ebu_w32(val, reg) ltq_w32(val, &ebu->reg) -+#define ebu_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &ebu->reg) -+ -+/** EBU register structure */ -+struct svip_reg_ebu { -+ volatile unsigned long clc; /* 0x0000 */ -+ volatile unsigned long reserved0; /* 0x04 */ -+ volatile unsigned long id; /* 0x0008 */ -+ volatile unsigned long reserved1; /* 0x0c */ -+ volatile unsigned long con; /* 0x0010 */ -+ volatile unsigned long reserved2[3]; /* 0x14 */ -+ volatile unsigned long addr_sel_0; /* 0x0020 */ -+ volatile unsigned long addr_sel_1; /* 0x0024 */ -+ volatile unsigned long addr_sel_2; /* 0x0028 */ -+ volatile unsigned long addr_sel_3; /* 0x002c */ -+ volatile unsigned long reserved3[12]; /* 0x30 */ -+ volatile unsigned long con_0; /* 0x0060 */ -+ volatile unsigned long con_1; /* 0x0064 */ -+ volatile unsigned long con_2; /* 0x0068 */ -+ volatile unsigned long con_3; /* 0x006c */ -+ volatile unsigned long reserved4[4]; /* 0x70 */ -+ volatile unsigned long emu_addr; /* 0x0080 */ -+ volatile unsigned long emu_bc; /* 0x0084 */ -+ volatile unsigned long emu_con; /* 0x0088 */ -+ volatile unsigned long reserved5; /* 0x8c */ -+ volatile unsigned long pcc_con; /* 0x0090 */ -+ volatile unsigned long pcc_stat; /* 0x0094 */ -+ volatile unsigned long reserved6[2]; /* 0x98 */ -+ volatile unsigned long pcc_istat; /* 0x00A0 */ -+ volatile unsigned long pcc_ien; /* 0x00A4 */ -+ volatile unsigned long pcc_int_out; /* 0x00A8 */ -+ volatile unsigned long pcc_irs; /* 0x00AC */ -+ volatile unsigned long nand_con; /* 0x00B0 */ -+ volatile unsigned long nand_wait; /* 0x00B4 */ -+ volatile unsigned long nand_ecc0; /* 0x00B8 */ -+ volatile unsigned long nand_ecc_ac; /* 0x00BC */ -+}; -+ -+/******************************************************************************* -+ * EBU -+ ******************************************************************************/ -+#define LTQ_EBU_CLC ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0000)) -+#define LTQ_EBU_ID ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0008)) -+#define LTQ_EBU_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0010)) -+#define LTQ_EBU_ADDR_SEL_0 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0020)) -+#define LTQ_EBU_ADDR_SEL_1 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0024)) -+#define LTQ_EBU_ADDR_SEL_2 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0028)) -+#define LTQ_EBU_ADDR_SEL_3 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x002c)) -+#define LTQ_EBU_CON_0 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0060)) -+#define LTQ_EBU_CON_1 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0064)) -+#define LTQ_EBU_CON_2 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0068)) -+#define LTQ_EBU_CON_3 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x006c)) -+#define LTQ_EBU_EMU_BC ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0084)) -+#define LTQ_EBU_PCC_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0090)) -+#define LTQ_EBU_PCC_STAT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0094)) -+#define LTQ_EBU_PCC_ISTAT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A0)) -+#define LTQ_EBU_PCC_IEN ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A4)) -+#define LTQ_EBU_PCC_INT_OUT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A8)) -+#define LTQ_EBU_PCC_IRS ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00AC)) -+#define LTQ_EBU_NAND_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B0)) -+#define LTQ_EBU_NAND_WAIT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B4)) -+#define LTQ_EBU_NAND_ECC0 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B8)) -+#define LTQ_EBU_NAND_ECC_AC ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00BC)) -+#define LTQ_EBU_EMU_ADDR ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0080)) -+#define LTQ_EBU_EMU_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0088)) -+ -+/******************************************************************************* -+ * EBU Clock Control Register -+ ******************************************************************************/ -+ -+/* EBU Disable Status Bit (1) */ -+#define LTQ_EBU_CLC_DISS (0x1 << 1) -+#define LTQ_EBU_CLC_DISS_GET(val) ((((val) & LTQ_EBU_CLC_DISS) >> 1) & 0x1) -+/* Used for Enable/disable Control of the EBU (0) */ -+#define LTQ_EBU_CLC_DISR (0x1) -+#define LTQ_EBU_CLC_DISR_VAL(val) (((val) & 0x1) << 0) -+#define LTQ_EBU_CLC_DISR_GET(val) ((((val) & LTQ_EBU_CLC_DISR) >> 0) & 0x1) -+#define LTQ_EBU_CLC_DISR_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CLC_DISR) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * EBU Identification Register (Internal) -+ ******************************************************************************/ -+ -+/* Module Number (31:8) */ -+#define LTQ_EBU_ID_MODNUM (0xffffff << 8) -+#define LTQ_EBU_ID_MODNUM_GET(val) ((((val) & LTQ_EBU_ID_MODNUM) >> 8) & 0xffffff) -+/* Revision Number (7:0) */ -+#define LTQ_EBU_ID_REVNUM (0xff) -+#define LTQ_EBU_ID_REVNUM_GET(val) ((((val) & LTQ_EBU_ID_REVNUM) >> 0) & 0xff) -+ -+/******************************************************************************* -+ * External Bus Unit Control Register -+ ******************************************************************************/ -+ -+/* Driver Turn-Around Control, Chip Select Triggered (22:20) */ -+#define LTQ_EBU_CON_DTACS (0x7 << 20) -+#define LTQ_EBU_CON_DTACS_VAL(val) (((val) & 0x7) << 20) -+#define LTQ_EBU_CON_DTACS_GET(val) ((((val) & LTQ_EBU_CON_DTACS) >> 20) & 0x7) -+#define LTQ_EBU_CON_DTACS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_DTACS) | (((val) & 0x7) << 20)) -+/* Driver Turn-Around Control, Read-write Triggered (18:16) */ -+#define LTQ_EBU_CON_DTARW (0x7 << 16) -+#define LTQ_EBU_CON_DTARW_VAL(val) (((val) & 0x7) << 16) -+#define LTQ_EBU_CON_DTARW_GET(val) ((((val) & LTQ_EBU_CON_DTARW) >> 16) & 0x7) -+#define LTQ_EBU_CON_DTARW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_DTARW) | (((val) & 0x7) << 16)) -+/* Time-Out Control (15:8) */ -+#define LTQ_EBU_CON_TOUTC (0xff << 8) -+#define LTQ_EBU_CON_TOUTC_VAL(val) (((val) & 0xff) << 8) -+#define LTQ_EBU_CON_TOUTC_GET(val) ((((val) & LTQ_EBU_CON_TOUTC) >> 8) & 0xff) -+#define LTQ_EBU_CON_TOUTC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_TOUTC) | (((val) & 0xff) << 8)) -+/* Arbitration Mode (7:6) */ -+#define LTQ_EBU_CON_ARBMODE (0x3 << 6) -+#define LTQ_EBU_CON_ARBMODE_VAL(val) (((val) & 0x3) << 6) -+#define LTQ_EBU_CON_ARBMODE_GET(val) ((((val) & LTQ_EBU_CON_ARBMODE) >> 6) & 0x3) -+#define LTQ_EBU_CON_ARBMODE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_ARBMODE) | (((val) & 0x3) << 6)) -+/* Arbitration Synchronization (5) */ -+#define LTQ_EBU_CON_ARBSYNC (0x1 << 5) -+#define LTQ_EBU_CON_ARBSYNC_VAL(val) (((val) & 0x1) << 5) -+#define LTQ_EBU_CON_ARBSYNC_GET(val) ((((val) & LTQ_EBU_CON_ARBSYNC) >> 5) & 0x1) -+#define LTQ_EBU_CON_ARBSYNC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_ARBSYNC) | (((val) & 0x1) << 5)) -+ -+/******************************************************************************* -+ * Address Select Registers -+ ******************************************************************************/ -+ -+/* Memory Region Base Address (31:12) */ -+#define LTQ_EBU_ADDR_SEL_0_BASE (0xfffff << 12) -+#define LTQ_EBU_ADDR_SEL_0_BASE_VAL(val) (((val) & 0xfffff) << 12) -+#define LTQ_EBU_ADDR_SEL_0_BASE_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_BASE) >> 12) & 0xfffff) -+#define LTQ_EBU_ADDR_SEL_0_BASE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_BASE) | (((val) & 0xfffff) << 12)) -+/* Memory Region Address Mask (7:4) */ -+#define LTQ_EBU_ADDR_SEL_0_MASK (0xf << 4) -+#define LTQ_EBU_ADDR_SEL_0_MASK_VAL(val) (((val) & 0xf) << 4) -+#define LTQ_EBU_ADDR_SEL_0_MASK_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_MASK) >> 4) & 0xf) -+#define LTQ_EBU_ADDR_SEL_0_MASK_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_MASK) | (((val) & 0xf) << 4)) -+/* Memory Region Mirror Enable Control (1) */ -+#define LTQ_EBU_ADDR_SEL_0_MRME (0x1 << 1) -+#define LTQ_EBU_ADDR_SEL_0_MRME_VAL(val) (((val) & 0x1) << 1) -+#define LTQ_EBU_ADDR_SEL_0_MRME_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_MRME) >> 1) & 0x1) -+#define LTQ_EBU_ADDR_SEL_0_MRME_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_MRME) | (((val) & 0x1) << 1)) -+/* Memory Region Enable Control (0) */ -+#define LTQ_EBU_ADDR_SEL_0_REGEN (0x1) -+#define LTQ_EBU_ADDR_SEL_0_REGEN_VAL(val) (((val) & 0x1) << 0) -+#define LTQ_EBU_ADDR_SEL_0_REGEN_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_REGEN) >> 0) & 0x1) -+#define LTQ_EBU_ADDR_SEL_0_REGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_REGEN) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Bus Configuration Registers -+ ******************************************************************************/ -+ -+/* Memory Region Write Protection (31) */ -+#define LTQ_EBU_CON_0_WRDIS (0x1 << 31) -+#define LTQ_EBU_CON_0_WRDIS_VAL(val) (((val) & 0x1) << 31) -+#define LTQ_EBU_CON_0_WRDIS_GET(val) ((((val) & LTQ_EBU_CON_0_WRDIS) >> 31) & 0x1) -+#define LTQ_EBU_CON_0_WRDIS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WRDIS) | (((val) & 0x1) << 31)) -+/* Address Swapping (30) */ -+#define LTQ_EBU_CON_0_ADSWP (0x1 << 30) -+#define LTQ_EBU_CON_0_ADSWP_VAL(val) (((val) & 0x1) << 30) -+#define LTQ_EBU_CON_0_ADSWP_GET(val) ((((val) & LTQ_EBU_CON_0_ADSWP) >> 30) & 0x1) -+#define LTQ_EBU_CON_0_ADSWP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_ADSWP) | (((val) & 0x1) << 30)) -+/* Address Generation Control (26:24) */ -+#define LTQ_EBU_CON_0_AGEN (0x7 << 24) -+#define LTQ_EBU_CON_0_AGEN_VAL(val) (((val) & 0x7) << 24) -+#define LTQ_EBU_CON_0_AGEN_GET(val) ((((val) & LTQ_EBU_CON_0_AGEN) >> 24) & 0x7) -+#define LTQ_EBU_CON_0_AGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_AGEN) | (((val) & 0x7) << 24)) -+/* Extended Address Setup Control (22) */ -+#define LTQ_EBU_CON_0_SETUP (0x1 << 22) -+#define LTQ_EBU_CON_0_SETUP_VAL(val) (((val) & 0x1) << 22) -+#define LTQ_EBU_CON_0_SETUP_GET(val) ((((val) & LTQ_EBU_CON_0_SETUP) >> 22) & 0x1) -+#define LTQ_EBU_CON_0_SETUP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_SETUP) | (((val) & 0x1) << 22)) -+/* Variable Wait-State Insertion Control (21:20) */ -+#define LTQ_EBU_CON_0_WAIT (0x3 << 20) -+#define LTQ_EBU_CON_0_WAIT_VAL(val) (((val) & 0x3) << 20) -+#define LTQ_EBU_CON_0_WAIT_GET(val) ((((val) & LTQ_EBU_CON_0_WAIT) >> 20) & 0x3) -+#define LTQ_EBU_CON_0_WAIT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAIT) | (((val) & 0x3) << 20)) -+/* Active WAIT Level Control (19) */ -+#define LTQ_EBU_CON_0_WINV (0x1 << 19) -+#define LTQ_EBU_CON_0_WINV_VAL(val) (((val) & 0x1) << 19) -+#define LTQ_EBU_CON_0_WINV_GET(val) ((((val) & LTQ_EBU_CON_0_WINV) >> 19) & 0x1) -+#define LTQ_EBU_CON_0_WINV_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WINV) | (((val) & 0x1) << 19)) -+/* External Device Data Width Control (17:16) */ -+#define LTQ_EBU_CON_0_PW (0x3 << 16) -+#define LTQ_EBU_CON_0_PW_VAL(val) (((val) & 0x3) << 16) -+#define LTQ_EBU_CON_0_PW_GET(val) ((((val) & LTQ_EBU_CON_0_PW) >> 16) & 0x3) -+#define LTQ_EBU_CON_0_PW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_PW) | (((val) & 0x3) << 16)) -+/* Address Latch Enable ALE Duration Control (15:14) */ -+#define LTQ_EBU_CON_0_ALEC (0x3 << 14) -+#define LTQ_EBU_CON_0_ALEC_VAL(val) (((val) & 0x3) << 14) -+#define LTQ_EBU_CON_0_ALEC_GET(val) ((((val) & LTQ_EBU_CON_0_ALEC) >> 14) & 0x3) -+#define LTQ_EBU_CON_0_ALEC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_ALEC) | (((val) & 0x3) << 14)) -+/* Byte Control Signal Timing Mode Control (13:12) */ -+#define LTQ_EBU_CON_0_BCGEN (0x3 << 12) -+#define LTQ_EBU_CON_0_BCGEN_VAL(val) (((val) & 0x3) << 12) -+#define LTQ_EBU_CON_0_BCGEN_GET(val) ((((val) & LTQ_EBU_CON_0_BCGEN) >> 12) & 0x3) -+#define LTQ_EBU_CON_0_BCGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_BCGEN) | (((val) & 0x3) << 12)) -+/* Write Access Wait-State Control (10:8) */ -+#define LTQ_EBU_CON_0_WAITWRC (0x7 << 8) -+#define LTQ_EBU_CON_0_WAITWRC_VAL(val) (((val) & 0x7) << 8) -+#define LTQ_EBU_CON_0_WAITWRC_GET(val) ((((val) & LTQ_EBU_CON_0_WAITWRC) >> 8) & 0x7) -+#define LTQ_EBU_CON_0_WAITWRC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAITWRC) | (((val) & 0x7) << 8)) -+/* Read Access Wait-State Control (7:6) */ -+#define LTQ_EBU_CON_0_WAITRDC (0x3 << 6) -+#define LTQ_EBU_CON_0_WAITRDC_VAL(val) (((val) & 0x3) << 6) -+#define LTQ_EBU_CON_0_WAITRDC_GET(val) ((((val) & LTQ_EBU_CON_0_WAITRDC) >> 6) & 0x3) -+#define LTQ_EBU_CON_0_WAITRDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAITRDC) | (((val) & 0x3) << 6)) -+/* Hold/Pause Cycle Control (5:4) */ -+#define LTQ_EBU_CON_0_HOLDC (0x3 << 4) -+#define LTQ_EBU_CON_0_HOLDC_VAL(val) (((val) & 0x3) << 4) -+#define LTQ_EBU_CON_0_HOLDC_GET(val) ((((val) & LTQ_EBU_CON_0_HOLDC) >> 4) & 0x3) -+#define LTQ_EBU_CON_0_HOLDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_HOLDC) | (((val) & 0x3) << 4)) -+/* Recovery Cycle Control (3:2) */ -+#define LTQ_EBU_CON_0_RECOVC (0x3 << 2) -+#define LTQ_EBU_CON_0_RECOVC_VAL(val) (((val) & 0x3) << 2) -+#define LTQ_EBU_CON_0_RECOVC_GET(val) ((((val) & LTQ_EBU_CON_0_RECOVC) >> 2) & 0x3) -+#define LTQ_EBU_CON_0_RECOVC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_RECOVC) | (((val) & 0x3) << 2)) -+/* Wait Cycle Multiplier Control (1:0) */ -+#define LTQ_EBU_CON_0_CMULT (0x3) -+#define LTQ_EBU_CON_0_CMULT_VAL(val) (((val) & 0x3) << 0) -+#define LTQ_EBU_CON_0_CMULT_GET(val) ((((val) & LTQ_EBU_CON_0_CMULT) >> 0) & 0x3) -+#define LTQ_EBU_CON_0_CMULT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_CMULT) | (((val) & 0x3) << 0)) -+ -+/******************************************************************************* -+ * External Bus Unit Emulator Bus Configuration Register -+ ******************************************************************************/ -+ -+/* Write Protection (31) */ -+#define LTQ_EBU_EMU_BC_WRITE (0x1 << 31) -+#define LTQ_EBU_EMU_BC_WRITE_VAL(val) (((val) & 0x1) << 31) -+#define LTQ_EBU_EMU_BC_WRITE_GET(val) ((((val) & LTQ_EBU_EMU_BC_WRITE) >> 31) & 0x1) -+#define LTQ_EBU_EMU_BC_WRITE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WRITE) | (((val) & 0x1) << 31)) -+/* Address Generation Control (26:24) */ -+#define LTQ_EBU_EMU_BC_AGEN (0x7 << 24) -+#define LTQ_EBU_EMU_BC_AGEN_VAL(val) (((val) & 0x7) << 24) -+#define LTQ_EBU_EMU_BC_AGEN_GET(val) ((((val) & LTQ_EBU_EMU_BC_AGEN) >> 24) & 0x7) -+#define LTQ_EBU_EMU_BC_AGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_AGEN) | (((val) & 0x7) << 24)) -+/* Extended Address Setup Control (22) */ -+#define LTQ_EBU_EMU_BC_SETUP (0x1 << 22) -+#define LTQ_EBU_EMU_BC_SETUP_VAL(val) (((val) & 0x1) << 22) -+#define LTQ_EBU_EMU_BC_SETUP_GET(val) ((((val) & LTQ_EBU_EMU_BC_SETUP) >> 22) & 0x1) -+#define LTQ_EBU_EMU_BC_SETUP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_SETUP) | (((val) & 0x1) << 22)) -+/* Variable Waitstate Insertion Control (21:20) */ -+#define LTQ_EBU_EMU_BC_WAIT (0x3 << 20) -+#define LTQ_EBU_EMU_BC_WAIT_VAL(val) (((val) & 0x3) << 20) -+#define LTQ_EBU_EMU_BC_WAIT_GET(val) ((((val) & LTQ_EBU_EMU_BC_WAIT) >> 20) & 0x3) -+#define LTQ_EBU_EMU_BC_WAIT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAIT) | (((val) & 0x3) << 20)) -+/* Active WAIT Level Control (19) */ -+#define LTQ_EBU_EMU_BC_WINV (0x1 << 19) -+#define LTQ_EBU_EMU_BC_WINV_VAL(val) (((val) & 0x1) << 19) -+#define LTQ_EBU_EMU_BC_WINV_GET(val) ((((val) & LTQ_EBU_EMU_BC_WINV) >> 19) & 0x1) -+#define LTQ_EBU_EMU_BC_WINV_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WINV) | (((val) & 0x1) << 19)) -+/* External Device Data Width Control (17:16) */ -+#define LTQ_EBU_EMU_BC_PORTW (0x3 << 16) -+#define LTQ_EBU_EMU_BC_PORTW_VAL(val) (((val) & 0x3) << 16) -+#define LTQ_EBU_EMU_BC_PORTW_GET(val) ((((val) & LTQ_EBU_EMU_BC_PORTW) >> 16) & 0x3) -+#define LTQ_EBU_EMU_BC_PORTW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_PORTW) | (((val) & 0x3) << 16)) -+/* Address Latch Enable Function (15:14) */ -+#define LTQ_EBU_EMU_BC_ALEC (0x3 << 14) -+#define LTQ_EBU_EMU_BC_ALEC_VAL(val) (((val) & 0x3) << 14) -+#define LTQ_EBU_EMU_BC_ALEC_GET(val) ((((val) & LTQ_EBU_EMU_BC_ALEC) >> 14) & 0x3) -+#define LTQ_EBU_EMU_BC_ALEC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_ALEC) | (((val) & 0x3) << 14)) -+/* Byte Control Signal Timing Mode (13:12) */ -+#define LTQ_EBU_EMU_BC_BCGEN (0x3 << 12) -+#define LTQ_EBU_EMU_BC_BCGEN_VAL(val) (((val) & 0x3) << 12) -+#define LTQ_EBU_EMU_BC_BCGEN_GET(val) ((((val) & LTQ_EBU_EMU_BC_BCGEN) >> 12) & 0x3) -+#define LTQ_EBU_EMU_BC_BCGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_BCGEN) | (((val) & 0x3) << 12)) -+/* Write Access Waitstate Control (10:8) */ -+#define LTQ_EBU_EMU_BC_WAITWRC (0x7 << 8) -+#define LTQ_EBU_EMU_BC_WAITWRC_VAL(val) (((val) & 0x7) << 8) -+#define LTQ_EBU_EMU_BC_WAITWRC_GET(val) ((((val) & LTQ_EBU_EMU_BC_WAITWRC) >> 8) & 0x7) -+#define LTQ_EBU_EMU_BC_WAITWRC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAITWRC) | (((val) & 0x7) << 8)) -+/* Read Access Waitstate Control (7:6) */ -+#define LTQ_EBU_EMU_BC_WAITRDC (0x3 << 6) -+#define LTQ_EBU_EMU_BC_WAITRDC_VAL(val) (((val) & 0x3) << 6) -+#define LTQ_EBU_EMU_BC_WAITRDC_GET(val) ((((val) & LTQ_EBU_EMU_BC_WAITRDC) >> 6) & 0x3) -+#define LTQ_EBU_EMU_BC_WAITRDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAITRDC) | (((val) & 0x3) << 6)) -+/* Hold/Pause Cycle Control (5:4) */ -+#define LTQ_EBU_EMU_BC_HOLDC (0x3 << 4) -+#define LTQ_EBU_EMU_BC_HOLDC_VAL(val) (((val) & 0x3) << 4) -+#define LTQ_EBU_EMU_BC_HOLDC_GET(val) ((((val) & LTQ_EBU_EMU_BC_HOLDC) >> 4) & 0x3) -+#define LTQ_EBU_EMU_BC_HOLDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_HOLDC) | (((val) & 0x3) << 4)) -+/* Recovery Cycles Control (3:2) */ -+#define LTQ_EBU_EMU_BC_RECOVC (0x3 << 2) -+#define LTQ_EBU_EMU_BC_RECOVC_VAL(val) (((val) & 0x3) << 2) -+#define LTQ_EBU_EMU_BC_RECOVC_GET(val) ((((val) & LTQ_EBU_EMU_BC_RECOVC) >> 2) & 0x3) -+#define LTQ_EBU_EMU_BC_RECOVC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_RECOVC) | (((val) & 0x3) << 2)) -+/* Cycle Multiplier Control (1:0) */ -+#define LTQ_EBU_EMU_BC_CMULT (0x3) -+#define LTQ_EBU_EMU_BC_CMULT_VAL(val) (((val) & 0x3) << 0) -+#define LTQ_EBU_EMU_BC_CMULT_GET(val) ((((val) & LTQ_EBU_EMU_BC_CMULT) >> 0) & 0x3) -+#define LTQ_EBU_EMU_BC_CMULT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_CMULT) | (((val) & 0x3) << 0)) -+ -+/******************************************************************************* -+ * PC-Card Control Register -+ ******************************************************************************/ -+ -+/* External Interrupt Input IREQ (3:1) */ -+#define LTQ_EBU_PCC_CON_IREQ (0x7 << 1) -+#define LTQ_EBU_PCC_CON_IREQ_VAL(val) (((val) & 0x7) << 1) -+#define LTQ_EBU_PCC_CON_IREQ_GET(val) ((((val) & LTQ_EBU_PCC_CON_IREQ) >> 1) & 0x7) -+#define LTQ_EBU_PCC_CON_IREQ_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_CON_IREQ) | (((val) & 0x7) << 1)) -+/* PC Card ON (0) */ -+#define LTQ_EBU_PCC_CON_ON (0x1) -+#define LTQ_EBU_PCC_CON_ON_VAL(val) (((val) & 0x1) << 0) -+#define LTQ_EBU_PCC_CON_ON_GET(val) ((((val) & LTQ_EBU_PCC_CON_ON) >> 0) & 0x1) -+#define LTQ_EBU_PCC_CON_ON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_CON_ON) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * PCC Status Register -+ ******************************************************************************/ -+ -+/* Interrupt Request (6) */ -+#define LTQ_EBU_PCC_STAT_IRQ (0x1 << 6) -+#define LTQ_EBU_PCC_STAT_IRQ_GET(val) ((((val) & LTQ_EBU_PCC_STAT_IRQ) >> 6) & 0x1) -+/* PC-Card Overcurrent (5) */ -+#define LTQ_EBU_PCC_STAT_OC (0x1 << 5) -+#define LTQ_EBU_PCC_STAT_OC_GET(val) ((((val) & LTQ_EBU_PCC_STAT_OC) >> 5) & 0x1) -+/* PC-Card Socket Power On (4) */ -+#define LTQ_EBU_PCC_STAT_SPON (0x1 << 4) -+#define LTQ_EBU_PCC_STAT_SPON_GET(val) ((((val) & LTQ_EBU_PCC_STAT_SPON) >> 4) & 0x1) -+/* Card Detect Status (1:0) */ -+#define LTQ_EBU_PCC_STAT_CD (0x3) -+#define LTQ_EBU_PCC_STAT_CD_GET(val) ((((val) & LTQ_EBU_PCC_STAT_CD) >> 0) & 0x3) -+ -+/******************************************************************************* -+ * PCC Interrupt Status Register -+ ******************************************************************************/ -+ -+/* Interrupt Request Active Interrupt (4) */ -+#define LTQ_EBU_PCC_ISTAT_IREQ (0x1 << 4) -+#define LTQ_EBU_PCC_ISTAT_IREQ_VAL(val) (((val) & 0x1) << 4) -+#define LTQ_EBU_PCC_ISTAT_IREQ_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_IREQ) >> 4) & 0x1) -+#define LTQ_EBU_PCC_ISTAT_IREQ_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_IREQ) | (((val) & 0x1) << 4)) -+/* Over Current Status Change Interrupt (3) */ -+#define LTQ_EBU_PCC_ISTAT_OC (0x1 << 3) -+#define LTQ_EBU_PCC_ISTAT_OC_VAL(val) (((val) & 0x1) << 3) -+#define LTQ_EBU_PCC_ISTAT_OC_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_OC) >> 3) & 0x1) -+#define LTQ_EBU_PCC_ISTAT_OC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_OC) | (((val) & 0x1) << 3)) -+/* Socket Power on Status Change Interrupt (2) */ -+#define LTQ_EBU_PCC_ISTAT_SPON (0x1 << 2) -+#define LTQ_EBU_PCC_ISTAT_SPON_VAL(val) (((val) & 0x1) << 2) -+#define LTQ_EBU_PCC_ISTAT_SPON_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_SPON) >> 2) & 0x1) -+#define LTQ_EBU_PCC_ISTAT_SPON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_SPON) | (((val) & 0x1) << 2)) -+/* Voltage Sense Status Change Interrupt (1) */ -+#define LTQ_EBU_PCC_ISTAT_VS (0x1 << 1) -+#define LTQ_EBU_PCC_ISTAT_VS_VAL(val) (((val) & 0x1) << 1) -+#define LTQ_EBU_PCC_ISTAT_VS_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_VS) >> 1) & 0x1) -+#define LTQ_EBU_PCC_ISTAT_VS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_VS) | (((val) & 0x1) << 1)) -+/* Card Detect Status Change Interrupt (0) */ -+#define LTQ_EBU_PCC_ISTAT_CD (0x1) -+#define LTQ_EBU_PCC_ISTAT_CD_VAL(val) (((val) & 0x1) << 0) -+#define LTQ_EBU_PCC_ISTAT_CD_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_CD) >> 0) & 0x1) -+#define LTQ_EBU_PCC_ISTAT_CD_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_CD) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * PCC Interrupt Enable Register -+ ******************************************************************************/ -+ -+/* Enable of Interrupt Request IR (4) */ -+#define LTQ_EBU_PCC_IEN_IR (0x1 << 4) -+#define LTQ_EBU_PCC_IEN_IR_VAL(val) (((val) & 0x1) << 4) -+#define LTQ_EBU_PCC_IEN_IR_GET(val) ((((val) & LTQ_EBU_PCC_IEN_IR) >> 4) & 0x1) -+#define LTQ_EBU_PCC_IEN_IR_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_IR) | (((val) & 0x1) << 4)) -+/* Enable of Interrupt Request OC event (3) */ -+#define LTQ_EBU_PCC_IEN_OC (0x1 << 3) -+#define LTQ_EBU_PCC_IEN_OC_VAL(val) (((val) & 0x1) << 3) -+#define LTQ_EBU_PCC_IEN_OC_GET(val) ((((val) & LTQ_EBU_PCC_IEN_OC) >> 3) & 0x1) -+#define LTQ_EBU_PCC_IEN_OC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_OC) | (((val) & 0x1) << 3)) -+/* Enable of Interrupt Request Socket Power On (2) */ -+#define LTQ_EBU_PCC_IEN_PWRON (0x1 << 2) -+#define LTQ_EBU_PCC_IEN_PWRON_VAL(val) (((val) & 0x1) << 2) -+#define LTQ_EBU_PCC_IEN_PWRON_GET(val) ((((val) & LTQ_EBU_PCC_IEN_PWRON) >> 2) & 0x1) -+#define LTQ_EBU_PCC_IEN_PWRON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_PWRON) | (((val) & 0x1) << 2)) -+/* Enable of Interrupt Request Voltage Sense (1) */ -+#define LTQ_EBU_PCC_IEN_VS (0x1 << 1) -+#define LTQ_EBU_PCC_IEN_VS_VAL(val) (((val) & 0x1) << 1) -+#define LTQ_EBU_PCC_IEN_VS_GET(val) ((((val) & LTQ_EBU_PCC_IEN_VS) >> 1) & 0x1) -+#define LTQ_EBU_PCC_IEN_VS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_VS) | (((val) & 0x1) << 1)) -+/* Enable of Interrupt Request Card Detect (0) */ -+#define LTQ_EBU_PCC_IEN_CD (0x1) -+#define LTQ_EBU_PCC_IEN_CD_VAL(val) (((val) & 0x1) << 0) -+#define LTQ_EBU_PCC_IEN_CD_GET(val) ((((val) & LTQ_EBU_PCC_IEN_CD) >> 0) & 0x1) -+#define LTQ_EBU_PCC_IEN_CD_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_CD) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * PCC Interrupt Output Status Register -+ ******************************************************************************/ -+ -+/* Status of Interrupt Request IR (4) */ -+#define LTQ_EBU_PCC_INT_OUT_IR (0x1 << 4) -+#define LTQ_EBU_PCC_INT_OUT_IR_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_IR) >> 4) & 0x1) -+/* Status of Interrupt Request OC (3) */ -+#define LTQ_EBU_PCC_INT_OUT_OC (0x1 << 3) -+#define LTQ_EBU_PCC_INT_OUT_OC_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_OC) >> 3) & 0x1) -+/* Status of Interrupt Request Socket Power On (2) */ -+#define LTQ_EBU_PCC_INT_OUT_PWRON (0x1 << 2) -+#define LTQ_EBU_PCC_INT_OUT_PWRON_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_PWRON) >> 2) & 0x1) -+/* Status of Interrupt Request Voltage Sense (1) */ -+#define LTQ_EBU_PCC_INT_OUT_VS (0x1 << 1) -+#define LTQ_EBU_PCC_INT_OUT_VS_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_VS) >> 1) & 0x1) -+/* Status of Interrupt Request Card Detect (0) */ -+#define LTQ_EBU_PCC_INT_OUT_CD (0x1) -+#define LTQ_EBU_PCC_INT_OUT_CD_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_CD) >> 0) & 0x1) -+ -+/******************************************************************************* -+ * PCC Interrupt Request Set Register -+ ******************************************************************************/ -+ -+/* Set Interrupt Request IR (4) */ -+#define LTQ_EBU_PCC_IRS_IR (0x1 << 4) -+#define LTQ_EBU_PCC_IRS_IR_VAL(val) (((val) & 0x1) << 4) -+#define LTQ_EBU_PCC_IRS_IR_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_IR) | (val) & 1) << 4) -+/* Set Interrupt Request OC (3) */ -+#define LTQ_EBU_PCC_IRS_OC (0x1 << 3) -+#define LTQ_EBU_PCC_IRS_OC_VAL(val) (((val) & 0x1) << 3) -+#define LTQ_EBU_PCC_IRS_OC_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_OC) | (val) & 1) << 3) -+/* Set Interrupt Request Socket Power On (2) */ -+#define LTQ_EBU_PCC_IRS_PWRON (0x1 << 2) -+#define LTQ_EBU_PCC_IRS_PWRON_VAL(val) (((val) & 0x1) << 2) -+#define LTQ_EBU_PCC_IRS_PWRON_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_PWRON) | (val) & 1) << 2) -+/* Set Interrupt Request Voltage Sense (1) */ -+#define LTQ_EBU_PCC_IRS_VS (0x1 << 1) -+#define LTQ_EBU_PCC_IRS_VS_VAL(val) (((val) & 0x1) << 1) -+#define LTQ_EBU_PCC_IRS_VS_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_VS) | (val) & 1) << 1) -+/* Set Interrupt Request Card Detect (0) */ -+#define LTQ_EBU_PCC_IRS_CD (0x1) -+#define LTQ_EBU_PCC_IRS_CD_VAL(val) (((val) & 0x1) << 0) -+#define LTQ_EBU_PCC_IRS_CD_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_CD) | (val) & 1) << 0) -+ -+/******************************************************************************* -+ * NAND Flash Control Register -+ ******************************************************************************/ -+ -+/* ECC Enabling (31) */ -+#define LTQ_EBU_NAND_CON_ECC_ON (0x1 << 31) -+#define LTQ_EBU_NAND_CON_ECC_ON_VAL(val) (((val) & 0x1) << 31) -+#define LTQ_EBU_NAND_CON_ECC_ON_GET(val) ((((val) & LTQ_EBU_NAND_CON_ECC_ON) >> 31) & 0x1) -+#define LTQ_EBU_NAND_CON_ECC_ON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_ECC_ON) | (((val) & 0x1) << 31)) -+/* Latch enable (23:18) */ -+#define LTQ_EBU_NAND_CON_LAT_EN (0x3f << 18) -+#define LTQ_EBU_NAND_CON_LAT_EN_VAL(val) (((val) & 0x3f) << 18) -+#define LTQ_EBU_NAND_CON_LAT_EN_GET(val) ((((val) & LTQ_EBU_NAND_CON_LAT_EN) >> 18) & 0x3f) -+#define LTQ_EBU_NAND_CON_LAT_EN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_LAT_EN) | (((val) & 0x3f) << 18)) -+/* Output ChipSelect# Selection (11:10) */ -+#define LTQ_EBU_NAND_CON_OUT_CS_S (0x3 << 10) -+#define LTQ_EBU_NAND_CON_OUT_CS_S_VAL(val) (((val) & 0x3) << 10) -+#define LTQ_EBU_NAND_CON_OUT_CS_S_GET(val) ((((val) & LTQ_EBU_NAND_CON_OUT_CS_S) >> 10) & 0x3) -+#define LTQ_EBU_NAND_CON_OUT_CS_S_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_OUT_CS_S) | (((val) & 0x3) << 10)) -+/* Input ChipSelect# Selection (9:8) */ -+#define LTQ_EBU_NAND_CON_IN_CS_S (0x3 << 8) -+#define LTQ_EBU_NAND_CON_IN_CS_S_VAL(val) (((val) & 0x3) << 8) -+#define LTQ_EBU_NAND_CON_IN_CS_S_GET(val) ((((val) & LTQ_EBU_NAND_CON_IN_CS_S) >> 8) & 0x3) -+#define LTQ_EBU_NAND_CON_IN_CS_S_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_IN_CS_S) | (((val) & 0x3) << 8)) -+/* Set PRE (7) */ -+#define LTQ_EBU_NAND_CON_PRE_P (0x1 << 7) -+#define LTQ_EBU_NAND_CON_PRE_P_VAL(val) (((val) & 0x1) << 7) -+#define LTQ_EBU_NAND_CON_PRE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_PRE_P) >> 7) & 0x1) -+#define LTQ_EBU_NAND_CON_PRE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_PRE_P) | (((val) & 0x1) << 7)) -+/* Set WP Active Polarity (6) */ -+#define LTQ_EBU_NAND_CON_WP_P (0x1 << 6) -+#define LTQ_EBU_NAND_CON_WP_P_VAL(val) (((val) & 0x1) << 6) -+#define LTQ_EBU_NAND_CON_WP_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_WP_P) >> 6) & 0x1) -+#define LTQ_EBU_NAND_CON_WP_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_WP_P) | (((val) & 0x1) << 6)) -+/* Set SE Active Polarity (5) */ -+#define LTQ_EBU_NAND_CON_SE_P (0x1 << 5) -+#define LTQ_EBU_NAND_CON_SE_P_VAL(val) (((val) & 0x1) << 5) -+#define LTQ_EBU_NAND_CON_SE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_SE_P) >> 5) & 0x1) -+#define LTQ_EBU_NAND_CON_SE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_SE_P) | (((val) & 0x1) << 5)) -+/* Set CS Active Polarity (4) */ -+#define LTQ_EBU_NAND_CON_CS_P (0x1 << 4) -+#define LTQ_EBU_NAND_CON_CS_P_VAL(val) (((val) & 0x1) << 4) -+#define LTQ_EBU_NAND_CON_CS_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_CS_P) >> 4) & 0x1) -+#define LTQ_EBU_NAND_CON_CS_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CS_P) | (((val) & 0x1) << 4)) -+/* Set CLE Active Polarity (3) */ -+#define LTQ_EBU_NAND_CON_CLE_P (0x1 << 3) -+#define LTQ_EBU_NAND_CON_CLE_P_VAL(val) (((val) & 0x1) << 3) -+#define LTQ_EBU_NAND_CON_CLE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_CLE_P) >> 3) & 0x1) -+#define LTQ_EBU_NAND_CON_CLE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CLE_P) | (((val) & 0x1) << 3)) -+/* Set ALE Active Polarity (2) */ -+#define LTQ_EBU_NAND_CON_ALE_P (0x1 << 2) -+#define LTQ_EBU_NAND_CON_ALE_P_VAL(val) (((val) & 0x1) << 2) -+#define LTQ_EBU_NAND_CON_ALE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_ALE_P) >> 2) & 0x1) -+#define LTQ_EBU_NAND_CON_ALE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_ALE_P) | (((val) & 0x1) << 2)) -+/* NAND CS Mux with EBU CS Enable (1) */ -+#define LTQ_EBU_NAND_CON_CSMUX_E (0x1 << 1) -+#define LTQ_EBU_NAND_CON_CSMUX_E_VAL(val) (((val) & 0x1) << 1) -+#define LTQ_EBU_NAND_CON_CSMUX_E_GET(val) ((((val) & LTQ_EBU_NAND_CON_CSMUX_E) >> 1) & 0x1) -+#define LTQ_EBU_NAND_CON_CSMUX_E_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CSMUX_E) | (((val) & 0x1) << 1)) -+/* NAND FLASH Mode Support (0) */ -+#define LTQ_EBU_NAND_CON_NANDMODE (0x1) -+#define LTQ_EBU_NAND_CON_NANDMODE_VAL(val) (((val) & 0x1) << 0) -+#define LTQ_EBU_NAND_CON_NANDMODE_GET(val) ((((val) & LTQ_EBU_NAND_CON_NANDMODE) >> 0) & 0x1) -+#define LTQ_EBU_NAND_CON_NANDMODE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_NANDMODE) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * NAND Flash State Register -+ ******************************************************************************/ -+ -+/* Reserved (31:3) */ -+#define LTQ_EBU_NAND_WAIT_RES (0x1fffffff << 3) -+#define LTQ_EBU_NAND_WAIT_RES_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_RES) >> 3) & 0x1fffffff) -+/* NAND Write Complete (3) */ -+#define LTQ_EBU_NAND_WAIT_WR_C (0x1 << 3) -+#define LTQ_EBU_NAND_WAIT_WR_C_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_WR_C) >> 3) & 0x1) -+/* Record the RD Edge (rising ) (2) */ -+#define LTQ_EBU_NAND_WAIT_RD_EDGE (0x1 << 2) -+#define LTQ_EBU_NAND_WAIT_RD_EDGE_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_RD_EDGE) >> 2) & 0x1) -+/* Record the BY# Edge (falling) (1) */ -+#define LTQ_EBU_NAND_WAIT_BY_EDGE (0x1 << 1) -+#define LTQ_EBU_NAND_WAIT_BY_EDGE_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_BY_EDGE) >> 1) & 0x1) -+/* Rd/BY# value (0) */ -+#define LTQ_EBU_NAND_WAIT_RDBY_VALUE (0x1) -+#define LTQ_EBU_NAND_WAIT_RDBY_VALUE_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_RDBY_VALUE) >> 0) & 0x1) -+ -+/******************************************************************************* -+ * NAND ECC Result Register 0 -+ ******************************************************************************/ -+ -+/* Reserved (31:24) */ -+#define LTQ_EBU_NAND_ECC0_RES (0xff << 24) -+#define LTQ_EBU_NAND_ECC0_RES_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_RES) >> 24) & 0xff) -+/* ECC value (23:16) */ -+#define LTQ_EBU_NAND_ECC0_ECC_B2 (0xff << 16) -+#define LTQ_EBU_NAND_ECC0_ECC_B2_VAL(val) (((val) & 0xff) << 16) -+#define LTQ_EBU_NAND_ECC0_ECC_B2_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_ECC_B2) >> 16) & 0xff) -+#define LTQ_EBU_NAND_ECC0_ECC_B2_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B2) | (((val) & 0xff) << 16)) -+/* ECC value (15:8) */ -+#define LTQ_EBU_NAND_ECC0_ECC_B1 (0xff << 8) -+#define LTQ_EBU_NAND_ECC0_ECC_B1_VAL(val) (((val) & 0xff) << 8) -+#define LTQ_EBU_NAND_ECC0_ECC_B1_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_ECC_B1) >> 8) & 0xff) -+#define LTQ_EBU_NAND_ECC0_ECC_B1_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B1) | (((val) & 0xff) << 8)) -+/* ECC value (7:0) */ -+#define LTQ_EBU_NAND_ECC0_ECC_B0 (0xff) -+#define LTQ_EBU_NAND_ECC0_ECC_B0_VAL(val) (((val) & 0xff) << 0) -+#define LTQ_EBU_NAND_ECC0_ECC_B0_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_ECC_B0) >> 0) & 0xff) -+#define LTQ_EBU_NAND_ECC0_ECC_B0_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B0) | (((val) & 0xff) << 0)) -+ -+/******************************************************************************* -+ * NAND ECC Address Counter Register -+ ******************************************************************************/ -+ -+/* Reserved (31:9) */ -+#define LTQ_EBU_NAND_ECC_AC_RES (0x7fffff << 9) -+#define LTQ_EBU_NAND_ECC_AC_RES_GET(val) ((((val) & LTQ_EBU_NAND_ECC_AC_RES) >> 9) & 0x7fffff) -+/* ECC address counter (8:0) */ -+#define LTQ_EBU_NAND_ECC_AC_ECC_AC (0x1ff) -+#define LTQ_EBU_NAND_ECC_AC_ECC_AC_VAL(val) (((val) & 0x1ff) << 0) -+#define LTQ_EBU_NAND_ECC_AC_ECC_AC_GET(val) ((((val) & LTQ_EBU_NAND_ECC_AC_ECC_AC) >> 0) & 0x1ff) -+#define LTQ_EBU_NAND_ECC_AC_ECC_AC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC_AC_ECC_AC) | (((val) & 0x1ff) << 0)) -+ -+/******************************************************************************* -+ * Internal Address Emulation Register -+ ******************************************************************************/ -+ -+/* Memory Region Base Address (31:12) */ -+#define LTQ_EBU_EMU_ADDR_BASE (0xfffff << 12) -+#define LTQ_EBU_EMU_ADDR_BASE_VAL(val) (((val) & 0xfffff) << 12) -+#define LTQ_EBU_EMU_ADDR_BASE_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_BASE) >> 12) & 0xfffff) -+#define LTQ_EBU_EMU_ADDR_BASE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_BASE) | (((val) & 0xfffff) << 12)) -+/* Memory Region Address Mask (7:4) */ -+#define LTQ_EBU_EMU_ADDR_MASK (0xf << 4) -+#define LTQ_EBU_EMU_ADDR_MASK_VAL(val) (((val) & 0xf) << 4) -+#define LTQ_EBU_EMU_ADDR_MASK_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_MASK) >> 4) & 0xf) -+#define LTQ_EBU_EMU_ADDR_MASK_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MASK) | (((val) & 0xf) << 4)) -+/* Memory Region Mirror Segment B Control (1) */ -+#define LTQ_EBU_EMU_ADDR_MRMB (0x1 << 1) -+#define LTQ_EBU_EMU_ADDR_MRMB_VAL(val) (((val) & 0x1) << 1) -+#define LTQ_EBU_EMU_ADDR_MRMB_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_MRMB) >> 1) & 0x1) -+#define LTQ_EBU_EMU_ADDR_MRMB_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MRMB) | (((val) & 0x1) << 1)) -+/* Memory Region Enable Control (0) */ -+#define LTQ_EBU_EMU_ADDR_MREC (0x1) -+#define LTQ_EBU_EMU_ADDR_MREC_VAL(val) (((val) & 0x1) << 0) -+#define LTQ_EBU_EMU_ADDR_MREC_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_MREC) >> 0) & 0x1) -+#define LTQ_EBU_EMU_ADDR_MREC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MREC) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * nternal Emulator Configuration Register -+ ******************************************************************************/ -+ -+/* Overlay Memory Control Region 3 (3) */ -+#define LTQ_EBU_EMU_CON_OVL3 (0x1 << 3) -+#define LTQ_EBU_EMU_CON_OVL3_VAL(val) (((val) & 0x1) << 3) -+#define LTQ_EBU_EMU_CON_OVL3_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL3) >> 3) & 0x1) -+#define LTQ_EBU_EMU_CON_OVL3_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL3) | (((val) & 0x1) << 3)) -+/* Overlay Memory Control Region 2 (2) */ -+#define LTQ_EBU_EMU_CON_OVL2 (0x1 << 2) -+#define LTQ_EBU_EMU_CON_OVL2_VAL(val) (((val) & 0x1) << 2) -+#define LTQ_EBU_EMU_CON_OVL2_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL2) >> 2) & 0x1) -+#define LTQ_EBU_EMU_CON_OVL2_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL2) | (((val) & 0x1) << 2)) -+/* Overlay Memory Control Region 1 (1) */ -+#define LTQ_EBU_EMU_CON_OVL1 (0x1 << 1) -+#define LTQ_EBU_EMU_CON_OVL1_VAL(val) (((val) & 0x1) << 1) -+#define LTQ_EBU_EMU_CON_OVL1_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL1) >> 1) & 0x1) -+#define LTQ_EBU_EMU_CON_OVL1_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL1) | (((val) & 0x1) << 1)) -+/* Overlay Memory Control Region 0 (0) */ -+#define LTQ_EBU_EMU_CON_OVL0 (0x1) -+#define LTQ_EBU_EMU_CON_OVL0_VAL(val) (((val) & 0x1) << 0) -+#define LTQ_EBU_EMU_CON_OVL0_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL0) >> 0) & 0x1) -+#define LTQ_EBU_EMU_CON_OVL0_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL0) | (((val) & 0x1) << 0)) -+ -+#endif /* __LTQ_EBU_H */ -Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/port_reg.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/port_reg.h 2012-07-31 15:46:02.484476159 +0200 -@@ -0,0 +1,3262 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2007 -+ Infineon Technologies AG -+ St. Martin Strasse 53; 81669 Munich, Germany -+ -+ Any use of this Software is subject to the conclusion of a respective -+ License Agreement. Without such a License Agreement no rights to the -+ Software are granted. -+ -+ ******************************************************************************/ -+ -+#ifndef __PORT_REG_H -+#define __PORT_REG_H -+ -+#define port_r32(reg) __raw_readl(®) -+#define port_w32(val, reg) __raw_writel(val, ®) -+ -+/** PORT register structure */ -+struct svip_reg_port { -+ volatile u32 out; /* 0x0000 */ -+ volatile u32 in; /* 0x0004 */ -+ volatile u32 dir; /* 0x0008 */ -+ volatile u32 altsel0; /* 0x000C */ -+ volatile u32 altsel1; /* 0x0010 */ -+ volatile u32 puen; /* 0x0014 */ -+ volatile u32 exintcr0; /* 0x0018 */ -+ volatile u32 exintcr1; /* 0x001C */ -+ volatile u32 irncr; /* 0x0020 */ -+ volatile u32 irnicr; /* 0x0024 */ -+ volatile u32 irnen; /* 0x0028 */ -+ volatile u32 irncfg; /* 0x002C */ -+ volatile u32 irnenset; /* 0x0030 */ -+ volatile u32 irnenclr; /* 0x0034 */ -+}; -+ -+/******************************************************************************* -+ * Port 0 Data Output Register -+ ******************************************************************************/ -+ -+/* Port 0 Pin # Output Value (19) */ -+#define PORT_P0_OUT_P19 (0x1 << 19) -+#define PORT_P0_OUT_P19_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P0_OUT_P19_GET(val) ((((val) & PORT_P0_OUT_P19) >> 19) & 0x1) -+#define PORT_P0_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P19) | (((val) & 0x1) << 19)) -+/* Port 0 Pin # Output Value (18) */ -+#define PORT_P0_OUT_P18 (0x1 << 18) -+#define PORT_P0_OUT_P18_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P0_OUT_P18_GET(val) ((((val) & PORT_P0_OUT_P18) >> 18) & 0x1) -+#define PORT_P0_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P18) | (((val) & 0x1) << 18)) -+/* Port 0 Pin # Output Value (17) */ -+#define PORT_P0_OUT_P17 (0x1 << 17) -+#define PORT_P0_OUT_P17_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P0_OUT_P17_GET(val) ((((val) & PORT_P0_OUT_P17) >> 17) & 0x1) -+#define PORT_P0_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P17) | (((val) & 0x1) << 17)) -+/* Port 0 Pin # Output Value (16) */ -+#define PORT_P0_OUT_P16 (0x1 << 16) -+#define PORT_P0_OUT_P16_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P0_OUT_P16_GET(val) ((((val) & PORT_P0_OUT_P16) >> 16) & 0x1) -+#define PORT_P0_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P16) | (((val) & 0x1) << 16)) -+/* Port 0 Pin # Output Value (15) */ -+#define PORT_P0_OUT_P15 (0x1 << 15) -+#define PORT_P0_OUT_P15_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P0_OUT_P15_GET(val) ((((val) & PORT_P0_OUT_P15) >> 15) & 0x1) -+#define PORT_P0_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P15) | (((val) & 0x1) << 15)) -+/* Port 0 Pin # Output Value (14) */ -+#define PORT_P0_OUT_P14 (0x1 << 14) -+#define PORT_P0_OUT_P14_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P0_OUT_P14_GET(val) ((((val) & PORT_P0_OUT_P14) >> 14) & 0x1) -+#define PORT_P0_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P14) | (((val) & 0x1) << 14)) -+/* Port 0 Pin # Output Value (13) */ -+#define PORT_P0_OUT_P13 (0x1 << 13) -+#define PORT_P0_OUT_P13_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P0_OUT_P13_GET(val) ((((val) & PORT_P0_OUT_P13) >> 13) & 0x1) -+#define PORT_P0_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P13) | (((val) & 0x1) << 13)) -+/* Port 0 Pin # Output Value (12) */ -+#define PORT_P0_OUT_P12 (0x1 << 12) -+#define PORT_P0_OUT_P12_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P0_OUT_P12_GET(val) ((((val) & PORT_P0_OUT_P12) >> 12) & 0x1) -+#define PORT_P0_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P12) | (((val) & 0x1) << 12)) -+/* Port 0 Pin # Output Value (11) */ -+#define PORT_P0_OUT_P11 (0x1 << 11) -+#define PORT_P0_OUT_P11_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P0_OUT_P11_GET(val) ((((val) & PORT_P0_OUT_P11) >> 11) & 0x1) -+#define PORT_P0_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P11) | (((val) & 0x1) << 11)) -+/* Port 0 Pin # Output Value (10) */ -+#define PORT_P0_OUT_P10 (0x1 << 10) -+#define PORT_P0_OUT_P10_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P0_OUT_P10_GET(val) ((((val) & PORT_P0_OUT_P10) >> 10) & 0x1) -+#define PORT_P0_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P10) | (((val) & 0x1) << 10)) -+/* Port 0 Pin # Output Value (9) */ -+#define PORT_P0_OUT_P9 (0x1 << 9) -+#define PORT_P0_OUT_P9_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P0_OUT_P9_GET(val) ((((val) & PORT_P0_OUT_P9) >> 9) & 0x1) -+#define PORT_P0_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P9) | (((val) & 0x1) << 9)) -+/* Port 0 Pin # Output Value (8) */ -+#define PORT_P0_OUT_P8 (0x1 << 8) -+#define PORT_P0_OUT_P8_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P0_OUT_P8_GET(val) ((((val) & PORT_P0_OUT_P8) >> 8) & 0x1) -+#define PORT_P0_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P8) | (((val) & 0x1) << 8)) -+/* Port 0 Pin # Output Value (7) */ -+#define PORT_P0_OUT_P7 (0x1 << 7) -+#define PORT_P0_OUT_P7_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P0_OUT_P7_GET(val) ((((val) & PORT_P0_OUT_P7) >> 7) & 0x1) -+#define PORT_P0_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P7) | (((val) & 0x1) << 7)) -+/* Port 0 Pin # Output Value (6) */ -+#define PORT_P0_OUT_P6 (0x1 << 6) -+#define PORT_P0_OUT_P6_VAL(val) (((val) & 0x1) << 6) -+#define PORT_P0_OUT_P6_GET(val) ((((val) & PORT_P0_OUT_P6) >> 6) & 0x1) -+#define PORT_P0_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P6) | (((val) & 0x1) << 6)) -+/* Port 0 Pin # Output Value (5) */ -+#define PORT_P0_OUT_P5 (0x1 << 5) -+#define PORT_P0_OUT_P5_VAL(val) (((val) & 0x1) << 5) -+#define PORT_P0_OUT_P5_GET(val) ((((val) & PORT_P0_OUT_P5) >> 5) & 0x1) -+#define PORT_P0_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P5) | (((val) & 0x1) << 5)) -+/* Port 0 Pin # Output Value (4) */ -+#define PORT_P0_OUT_P4 (0x1 << 4) -+#define PORT_P0_OUT_P4_VAL(val) (((val) & 0x1) << 4) -+#define PORT_P0_OUT_P4_GET(val) ((((val) & PORT_P0_OUT_P4) >> 4) & 0x1) -+#define PORT_P0_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P4) | (((val) & 0x1) << 4)) -+/* Port 0 Pin # Output Value (3) */ -+#define PORT_P0_OUT_P3 (0x1 << 3) -+#define PORT_P0_OUT_P3_VAL(val) (((val) & 0x1) << 3) -+#define PORT_P0_OUT_P3_GET(val) ((((val) & PORT_P0_OUT_P3) >> 3) & 0x1) -+#define PORT_P0_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P3) | (((val) & 0x1) << 3)) -+/* Port 0 Pin # Output Value (2) */ -+#define PORT_P0_OUT_P2 (0x1 << 2) -+#define PORT_P0_OUT_P2_VAL(val) (((val) & 0x1) << 2) -+#define PORT_P0_OUT_P2_GET(val) ((((val) & PORT_P0_OUT_P2) >> 2) & 0x1) -+#define PORT_P0_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P2) | (((val) & 0x1) << 2)) -+/* Port 0 Pin # Output Value (1) */ -+#define PORT_P0_OUT_P1 (0x1 << 1) -+#define PORT_P0_OUT_P1_VAL(val) (((val) & 0x1) << 1) -+#define PORT_P0_OUT_P1_GET(val) ((((val) & PORT_P0_OUT_P1) >> 1) & 0x1) -+#define PORT_P0_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P1) | (((val) & 0x1) << 1)) -+/* Port 0 Pin # Output Value (0) */ -+#define PORT_P0_OUT_P0 (0x1) -+#define PORT_P0_OUT_P0_VAL(val) (((val) & 0x1) << 0) -+#define PORT_P0_OUT_P0_GET(val) ((((val) & PORT_P0_OUT_P0) >> 0) & 0x1) -+#define PORT_P0_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P0) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Port 0 Data Input Register -+ ******************************************************************************/ -+ -+/* Port 0 Pin # Latched Input Value (19) */ -+#define PORT_P0_IN_P19 (0x1 << 19) -+#define PORT_P0_IN_P19_GET(val) ((((val) & PORT_P0_IN_P19) >> 19) & 0x1) -+/* Port 0 Pin # Latched Input Value (18) */ -+#define PORT_P0_IN_P18 (0x1 << 18) -+#define PORT_P0_IN_P18_GET(val) ((((val) & PORT_P0_IN_P18) >> 18) & 0x1) -+/* Port 0 Pin # Latched Input Value (17) */ -+#define PORT_P0_IN_P17 (0x1 << 17) -+#define PORT_P0_IN_P17_GET(val) ((((val) & PORT_P0_IN_P17) >> 17) & 0x1) -+/* Port 0 Pin # Latched Input Value (16) */ -+#define PORT_P0_IN_P16 (0x1 << 16) -+#define PORT_P0_IN_P16_GET(val) ((((val) & PORT_P0_IN_P16) >> 16) & 0x1) -+/* Port 0 Pin # Latched Input Value (15) */ -+#define PORT_P0_IN_P15 (0x1 << 15) -+#define PORT_P0_IN_P15_GET(val) ((((val) & PORT_P0_IN_P15) >> 15) & 0x1) -+/* Port 0 Pin # Latched Input Value (14) */ -+#define PORT_P0_IN_P14 (0x1 << 14) -+#define PORT_P0_IN_P14_GET(val) ((((val) & PORT_P0_IN_P14) >> 14) & 0x1) -+/* Port 0 Pin # Latched Input Value (13) */ -+#define PORT_P0_IN_P13 (0x1 << 13) -+#define PORT_P0_IN_P13_GET(val) ((((val) & PORT_P0_IN_P13) >> 13) & 0x1) -+/* Port 0 Pin # Latched Input Value (12) */ -+#define PORT_P0_IN_P12 (0x1 << 12) -+#define PORT_P0_IN_P12_GET(val) ((((val) & PORT_P0_IN_P12) >> 12) & 0x1) -+/* Port 0 Pin # Latched Input Value (11) */ -+#define PORT_P0_IN_P11 (0x1 << 11) -+#define PORT_P0_IN_P11_GET(val) ((((val) & PORT_P0_IN_P11) >> 11) & 0x1) -+/* Port 0 Pin # Latched Input Value (10) */ -+#define PORT_P0_IN_P10 (0x1 << 10) -+#define PORT_P0_IN_P10_GET(val) ((((val) & PORT_P0_IN_P10) >> 10) & 0x1) -+/* Port 0 Pin # Latched Input Value (9) */ -+#define PORT_P0_IN_P9 (0x1 << 9) -+#define PORT_P0_IN_P9_GET(val) ((((val) & PORT_P0_IN_P9) >> 9) & 0x1) -+/* Port 0 Pin # Latched Input Value (8) */ -+#define PORT_P0_IN_P8 (0x1 << 8) -+#define PORT_P0_IN_P8_GET(val) ((((val) & PORT_P0_IN_P8) >> 8) & 0x1) -+/* Port 0 Pin # Latched Input Value (7) */ -+#define PORT_P0_IN_P7 (0x1 << 7) -+#define PORT_P0_IN_P7_GET(val) ((((val) & PORT_P0_IN_P7) >> 7) & 0x1) -+/* Port 0 Pin # Latched Input Value (6) */ -+#define PORT_P0_IN_P6 (0x1 << 6) -+#define PORT_P0_IN_P6_GET(val) ((((val) & PORT_P0_IN_P6) >> 6) & 0x1) -+/* Port 0 Pin # Latched Input Value (5) */ -+#define PORT_P0_IN_P5 (0x1 << 5) -+#define PORT_P0_IN_P5_GET(val) ((((val) & PORT_P0_IN_P5) >> 5) & 0x1) -+/* Port 0 Pin # Latched Input Value (4) */ -+#define PORT_P0_IN_P4 (0x1 << 4) -+#define PORT_P0_IN_P4_GET(val) ((((val) & PORT_P0_IN_P4) >> 4) & 0x1) -+/* Port 0 Pin # Latched Input Value (3) */ -+#define PORT_P0_IN_P3 (0x1 << 3) -+#define PORT_P0_IN_P3_GET(val) ((((val) & PORT_P0_IN_P3) >> 3) & 0x1) -+/* Port 0 Pin # Latched Input Value (2) */ -+#define PORT_P0_IN_P2 (0x1 << 2) -+#define PORT_P0_IN_P2_GET(val) ((((val) & PORT_P0_IN_P2) >> 2) & 0x1) -+/* Port 0 Pin # Latched Input Value (1) */ -+#define PORT_P0_IN_P1 (0x1 << 1) -+#define PORT_P0_IN_P1_GET(val) ((((val) & PORT_P0_IN_P1) >> 1) & 0x1) -+/* Port 0 Pin # Latched Input Value (0) */ -+#define PORT_P0_IN_P0 (0x1) -+#define PORT_P0_IN_P0_GET(val) ((((val) & PORT_P0_IN_P0) >> 0) & 0x1) -+ -+/******************************************************************************* -+ * Port 0 Direction Register -+ ******************************************************************************/ -+ -+/* Port 0 Pin #Direction Control (19) */ -+#define PORT_P0_DIR_P19 (0x1 << 19) -+#define PORT_P0_DIR_P19_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P0_DIR_P19_GET(val) ((((val) & PORT_P0_DIR_P19) >> 19) & 0x1) -+#define PORT_P0_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P19) | (((val) & 0x1) << 19)) -+/* Port 0 Pin #Direction Control (18) */ -+#define PORT_P0_DIR_P18 (0x1 << 18) -+#define PORT_P0_DIR_P18_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P0_DIR_P18_GET(val) ((((val) & PORT_P0_DIR_P18) >> 18) & 0x1) -+#define PORT_P0_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P18) | (((val) & 0x1) << 18)) -+/* Port 0 Pin #Direction Control (17) */ -+#define PORT_P0_DIR_P17 (0x1 << 17) -+#define PORT_P0_DIR_P17_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P0_DIR_P17_GET(val) ((((val) & PORT_P0_DIR_P17) >> 17) & 0x1) -+#define PORT_P0_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P17) | (((val) & 0x1) << 17)) -+/* Port 0 Pin #Direction Control (16) */ -+#define PORT_P0_DIR_P16 (0x1 << 16) -+#define PORT_P0_DIR_P16_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P0_DIR_P16_GET(val) ((((val) & PORT_P0_DIR_P16) >> 16) & 0x1) -+#define PORT_P0_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P16) | (((val) & 0x1) << 16)) -+/* Port 0 Pin #Direction Control (15) */ -+#define PORT_P0_DIR_P15 (0x1 << 15) -+#define PORT_P0_DIR_P15_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P0_DIR_P15_GET(val) ((((val) & PORT_P0_DIR_P15) >> 15) & 0x1) -+#define PORT_P0_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P15) | (((val) & 0x1) << 15)) -+/* Port 0 Pin #Direction Control (14) */ -+#define PORT_P0_DIR_P14 (0x1 << 14) -+#define PORT_P0_DIR_P14_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P0_DIR_P14_GET(val) ((((val) & PORT_P0_DIR_P14) >> 14) & 0x1) -+#define PORT_P0_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P14) | (((val) & 0x1) << 14)) -+/* Port 0 Pin #Direction Control (13) */ -+#define PORT_P0_DIR_P13 (0x1 << 13) -+#define PORT_P0_DIR_P13_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P0_DIR_P13_GET(val) ((((val) & PORT_P0_DIR_P13) >> 13) & 0x1) -+#define PORT_P0_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P13) | (((val) & 0x1) << 13)) -+/* Port 0 Pin #Direction Control (12) */ -+#define PORT_P0_DIR_P12 (0x1 << 12) -+#define PORT_P0_DIR_P12_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P0_DIR_P12_GET(val) ((((val) & PORT_P0_DIR_P12) >> 12) & 0x1) -+#define PORT_P0_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P12) | (((val) & 0x1) << 12)) -+/* Port 0 Pin #Direction Control (11) */ -+#define PORT_P0_DIR_P11 (0x1 << 11) -+#define PORT_P0_DIR_P11_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P0_DIR_P11_GET(val) ((((val) & PORT_P0_DIR_P11) >> 11) & 0x1) -+#define PORT_P0_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P11) | (((val) & 0x1) << 11)) -+/* Port 0 Pin #Direction Control (10) */ -+#define PORT_P0_DIR_P10 (0x1 << 10) -+#define PORT_P0_DIR_P10_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P0_DIR_P10_GET(val) ((((val) & PORT_P0_DIR_P10) >> 10) & 0x1) -+#define PORT_P0_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P10) | (((val) & 0x1) << 10)) -+/* Port 0 Pin #Direction Control (9) */ -+#define PORT_P0_DIR_P9 (0x1 << 9) -+#define PORT_P0_DIR_P9_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P0_DIR_P9_GET(val) ((((val) & PORT_P0_DIR_P9) >> 9) & 0x1) -+#define PORT_P0_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P9) | (((val) & 0x1) << 9)) -+/* Port 0 Pin #Direction Control (8) */ -+#define PORT_P0_DIR_P8 (0x1 << 8) -+#define PORT_P0_DIR_P8_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P0_DIR_P8_GET(val) ((((val) & PORT_P0_DIR_P8) >> 8) & 0x1) -+#define PORT_P0_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P8) | (((val) & 0x1) << 8)) -+/* Port 0 Pin #Direction Control (7) */ -+#define PORT_P0_DIR_P7 (0x1 << 7) -+#define PORT_P0_DIR_P7_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P0_DIR_P7_GET(val) ((((val) & PORT_P0_DIR_P7) >> 7) & 0x1) -+#define PORT_P0_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P7) | (((val) & 0x1) << 7)) -+/* Port 0 Pin #Direction Control (6) */ -+#define PORT_P0_DIR_P6 (0x1 << 6) -+#define PORT_P0_DIR_P6_VAL(val) (((val) & 0x1) << 6) -+#define PORT_P0_DIR_P6_GET(val) ((((val) & PORT_P0_DIR_P6) >> 6) & 0x1) -+#define PORT_P0_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P6) | (((val) & 0x1) << 6)) -+/* Port 0 Pin #Direction Control (5) */ -+#define PORT_P0_DIR_P5 (0x1 << 5) -+#define PORT_P0_DIR_P5_VAL(val) (((val) & 0x1) << 5) -+#define PORT_P0_DIR_P5_GET(val) ((((val) & PORT_P0_DIR_P5) >> 5) & 0x1) -+#define PORT_P0_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P5) | (((val) & 0x1) << 5)) -+/* Port 0 Pin #Direction Control (4) */ -+#define PORT_P0_DIR_P4 (0x1 << 4) -+#define PORT_P0_DIR_P4_VAL(val) (((val) & 0x1) << 4) -+#define PORT_P0_DIR_P4_GET(val) ((((val) & PORT_P0_DIR_P4) >> 4) & 0x1) -+#define PORT_P0_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P4) | (((val) & 0x1) << 4)) -+/* Port 0 Pin #Direction Control (3) */ -+#define PORT_P0_DIR_P3 (0x1 << 3) -+#define PORT_P0_DIR_P3_VAL(val) (((val) & 0x1) << 3) -+#define PORT_P0_DIR_P3_GET(val) ((((val) & PORT_P0_DIR_P3) >> 3) & 0x1) -+#define PORT_P0_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P3) | (((val) & 0x1) << 3)) -+/* Port 0 Pin #Direction Control (2) */ -+#define PORT_P0_DIR_P2 (0x1 << 2) -+#define PORT_P0_DIR_P2_VAL(val) (((val) & 0x1) << 2) -+#define PORT_P0_DIR_P2_GET(val) ((((val) & PORT_P0_DIR_P2) >> 2) & 0x1) -+#define PORT_P0_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P2) | (((val) & 0x1) << 2)) -+/* Port 0 Pin #Direction Control (1) */ -+#define PORT_P0_DIR_P1 (0x1 << 1) -+#define PORT_P0_DIR_P1_VAL(val) (((val) & 0x1) << 1) -+#define PORT_P0_DIR_P1_GET(val) ((((val) & PORT_P0_DIR_P1) >> 1) & 0x1) -+#define PORT_P0_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P1) | (((val) & 0x1) << 1)) -+/* Port 0 Pin #Direction Control (0) */ -+#define PORT_P0_DIR_P0 (0x1) -+#define PORT_P0_DIR_P0_VAL(val) (((val) & 0x1) << 0) -+#define PORT_P0_DIR_P0_GET(val) ((((val) & PORT_P0_DIR_P0) >> 0) & 0x1) -+#define PORT_P0_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P0) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Port 0 Alternate Function Select Register 0 -+ ******************************************************************************/ -+ -+/* Alternate Function at Port 0 Bit # (19) */ -+#define PORT_P0_ALTSEL0_P19 (0x1 << 19) -+#define PORT_P0_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P0_ALTSEL0_P19_GET(val) ((((val) & PORT_P0_ALTSEL0_P19) >> 19) & 0x1) -+#define PORT_P0_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P19) | (((val) & 0x1) << 19)) -+/* Alternate Function at Port 0 Bit # (18) */ -+#define PORT_P0_ALTSEL0_P18 (0x1 << 18) -+#define PORT_P0_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P0_ALTSEL0_P18_GET(val) ((((val) & PORT_P0_ALTSEL0_P18) >> 18) & 0x1) -+#define PORT_P0_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P18) | (((val) & 0x1) << 18)) -+/* Alternate Function at Port 0 Bit # (17) */ -+#define PORT_P0_ALTSEL0_P17 (0x1 << 17) -+#define PORT_P0_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P0_ALTSEL0_P17_GET(val) ((((val) & PORT_P0_ALTSEL0_P17) >> 17) & 0x1) -+#define PORT_P0_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P17) | (((val) & 0x1) << 17)) -+/* Alternate Function at Port 0 Bit # (16) */ -+#define PORT_P0_ALTSEL0_P16 (0x1 << 16) -+#define PORT_P0_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P0_ALTSEL0_P16_GET(val) ((((val) & PORT_P0_ALTSEL0_P16) >> 16) & 0x1) -+#define PORT_P0_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P16) | (((val) & 0x1) << 16)) -+/* Alternate Function at Port 0 Bit # (15) */ -+#define PORT_P0_ALTSEL0_P15 (0x1 << 15) -+#define PORT_P0_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P0_ALTSEL0_P15_GET(val) ((((val) & PORT_P0_ALTSEL0_P15) >> 15) & 0x1) -+#define PORT_P0_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P15) | (((val) & 0x1) << 15)) -+/* Alternate Function at Port 0 Bit # (14) */ -+#define PORT_P0_ALTSEL0_P14 (0x1 << 14) -+#define PORT_P0_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P0_ALTSEL0_P14_GET(val) ((((val) & PORT_P0_ALTSEL0_P14) >> 14) & 0x1) -+#define PORT_P0_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P14) | (((val) & 0x1) << 14)) -+/* Alternate Function at Port 0 Bit # (13) */ -+#define PORT_P0_ALTSEL0_P13 (0x1 << 13) -+#define PORT_P0_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P0_ALTSEL0_P13_GET(val) ((((val) & PORT_P0_ALTSEL0_P13) >> 13) & 0x1) -+#define PORT_P0_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P13) | (((val) & 0x1) << 13)) -+/* Alternate Function at Port 0 Bit # (12) */ -+#define PORT_P0_ALTSEL0_P12 (0x1 << 12) -+#define PORT_P0_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P0_ALTSEL0_P12_GET(val) ((((val) & PORT_P0_ALTSEL0_P12) >> 12) & 0x1) -+#define PORT_P0_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P12) | (((val) & 0x1) << 12)) -+/* Alternate Function at Port 0 Bit # (11) */ -+#define PORT_P0_ALTSEL0_P11 (0x1 << 11) -+#define PORT_P0_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P0_ALTSEL0_P11_GET(val) ((((val) & PORT_P0_ALTSEL0_P11) >> 11) & 0x1) -+#define PORT_P0_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P11) | (((val) & 0x1) << 11)) -+/* Alternate Function at Port 0 Bit # (10) */ -+#define PORT_P0_ALTSEL0_P10 (0x1 << 10) -+#define PORT_P0_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P0_ALTSEL0_P10_GET(val) ((((val) & PORT_P0_ALTSEL0_P10) >> 10) & 0x1) -+#define PORT_P0_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P10) | (((val) & 0x1) << 10)) -+/* Alternate Function at Port 0 Bit # (9) */ -+#define PORT_P0_ALTSEL0_P9 (0x1 << 9) -+#define PORT_P0_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P0_ALTSEL0_P9_GET(val) ((((val) & PORT_P0_ALTSEL0_P9) >> 9) & 0x1) -+#define PORT_P0_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P9) | (((val) & 0x1) << 9)) -+/* Alternate Function at Port 0 Bit # (8) */ -+#define PORT_P0_ALTSEL0_P8 (0x1 << 8) -+#define PORT_P0_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P0_ALTSEL0_P8_GET(val) ((((val) & PORT_P0_ALTSEL0_P8) >> 8) & 0x1) -+#define PORT_P0_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P8) | (((val) & 0x1) << 8)) -+/* Alternate Function at Port 0 Bit # (7) */ -+#define PORT_P0_ALTSEL0_P7 (0x1 << 7) -+#define PORT_P0_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P0_ALTSEL0_P7_GET(val) ((((val) & PORT_P0_ALTSEL0_P7) >> 7) & 0x1) -+#define PORT_P0_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P7) | (((val) & 0x1) << 7)) -+/* Alternate Function at Port 0 Bit # (6) */ -+#define PORT_P0_ALTSEL0_P6 (0x1 << 6) -+#define PORT_P0_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) -+#define PORT_P0_ALTSEL0_P6_GET(val) ((((val) & PORT_P0_ALTSEL0_P6) >> 6) & 0x1) -+#define PORT_P0_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P6) | (((val) & 0x1) << 6)) -+/* Alternate Function at Port 0 Bit # (5) */ -+#define PORT_P0_ALTSEL0_P5 (0x1 << 5) -+#define PORT_P0_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) -+#define PORT_P0_ALTSEL0_P5_GET(val) ((((val) & PORT_P0_ALTSEL0_P5) >> 5) & 0x1) -+#define PORT_P0_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P5) | (((val) & 0x1) << 5)) -+/* Alternate Function at Port 0 Bit # (4) */ -+#define PORT_P0_ALTSEL0_P4 (0x1 << 4) -+#define PORT_P0_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) -+#define PORT_P0_ALTSEL0_P4_GET(val) ((((val) & PORT_P0_ALTSEL0_P4) >> 4) & 0x1) -+#define PORT_P0_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P4) | (((val) & 0x1) << 4)) -+/* Alternate Function at Port 0 Bit # (3) */ -+#define PORT_P0_ALTSEL0_P3 (0x1 << 3) -+#define PORT_P0_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) -+#define PORT_P0_ALTSEL0_P3_GET(val) ((((val) & PORT_P0_ALTSEL0_P3) >> 3) & 0x1) -+#define PORT_P0_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P3) | (((val) & 0x1) << 3)) -+/* Alternate Function at Port 0 Bit # (2) */ -+#define PORT_P0_ALTSEL0_P2 (0x1 << 2) -+#define PORT_P0_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) -+#define PORT_P0_ALTSEL0_P2_GET(val) ((((val) & PORT_P0_ALTSEL0_P2) >> 2) & 0x1) -+#define PORT_P0_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P2) | (((val) & 0x1) << 2)) -+/* Alternate Function at Port 0 Bit # (1) */ -+#define PORT_P0_ALTSEL0_P1 (0x1 << 1) -+#define PORT_P0_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) -+#define PORT_P0_ALTSEL0_P1_GET(val) ((((val) & PORT_P0_ALTSEL0_P1) >> 1) & 0x1) -+#define PORT_P0_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P1) | (((val) & 0x1) << 1)) -+/* Alternate Function at Port 0 Bit # (0) */ -+#define PORT_P0_ALTSEL0_P0 (0x1) -+#define PORT_P0_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) -+#define PORT_P0_ALTSEL0_P0_GET(val) ((((val) & PORT_P0_ALTSEL0_P0) >> 0) & 0x1) -+#define PORT_P0_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P0) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Port 0 Alternate Function Select Register 1 -+ ******************************************************************************/ -+ -+/* Alternate Function at Port 0 Bit # (13) */ -+#define PORT_P0_ALTSEL1_P13 (0x1 << 13) -+#define PORT_P0_ALTSEL1_P13_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P0_ALTSEL1_P13_GET(val) ((((val) & PORT_P0_ALTSEL1_P13) >> 13) & 0x1) -+#define PORT_P0_ALTSEL1_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P13) | (((val) & 0x1) << 13)) -+/* Alternate Function at Port 0 Bit # (12) */ -+#define PORT_P0_ALTSEL1_P12 (0x1 << 12) -+#define PORT_P0_ALTSEL1_P12_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P0_ALTSEL1_P12_GET(val) ((((val) & PORT_P0_ALTSEL1_P12) >> 12) & 0x1) -+#define PORT_P0_ALTSEL1_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P12) | (((val) & 0x1) << 12)) -+/* Alternate Function at Port 0 Bit # (11) */ -+#define PORT_P0_ALTSEL1_P11 (0x1 << 11) -+#define PORT_P0_ALTSEL1_P11_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P0_ALTSEL1_P11_GET(val) ((((val) & PORT_P0_ALTSEL1_P11) >> 11) & 0x1) -+#define PORT_P0_ALTSEL1_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P11) | (((val) & 0x1) << 11)) -+/* Alternate Function at Port 0 Bit # (10) */ -+#define PORT_P0_ALTSEL1_P10 (0x1 << 10) -+#define PORT_P0_ALTSEL1_P10_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P0_ALTSEL1_P10_GET(val) ((((val) & PORT_P0_ALTSEL1_P10) >> 10) & 0x1) -+#define PORT_P0_ALTSEL1_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P10) | (((val) & 0x1) << 10)) -+/* Alternate Function at Port 0 Bit # (9) */ -+#define PORT_P0_ALTSEL1_P9 (0x1 << 9) -+#define PORT_P0_ALTSEL1_P9_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P0_ALTSEL1_P9_GET(val) ((((val) & PORT_P0_ALTSEL1_P9) >> 9) & 0x1) -+#define PORT_P0_ALTSEL1_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P9) | (((val) & 0x1) << 9)) -+/* Alternate Function at Port 0 Bit # (8) */ -+#define PORT_P0_ALTSEL1_P8 (0x1 << 8) -+#define PORT_P0_ALTSEL1_P8_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P0_ALTSEL1_P8_GET(val) ((((val) & PORT_P0_ALTSEL1_P8) >> 8) & 0x1) -+#define PORT_P0_ALTSEL1_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P8) | (((val) & 0x1) << 8)) -+/* Alternate Function at Port 0 Bit # (7) */ -+#define PORT_P0_ALTSEL1_P7 (0x1 << 7) -+#define PORT_P0_ALTSEL1_P7_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P0_ALTSEL1_P7_GET(val) ((((val) & PORT_P0_ALTSEL1_P7) >> 7) & 0x1) -+#define PORT_P0_ALTSEL1_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P7) | (((val) & 0x1) << 7)) -+/* Alternate Function at Port 0 Bit # (6) */ -+#define PORT_P0_ALTSEL1_P6 (0x1 << 6) -+#define PORT_P0_ALTSEL1_P6_VAL(val) (((val) & 0x1) << 6) -+#define PORT_P0_ALTSEL1_P6_GET(val) ((((val) & PORT_P0_ALTSEL1_P6) >> 6) & 0x1) -+#define PORT_P0_ALTSEL1_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P6) | (((val) & 0x1) << 6)) -+/* Alternate Function at Port 0 Bit # (3) */ -+#define PORT_P0_ALTSEL1_P3 (0x1 << 3) -+#define PORT_P0_ALTSEL1_P3_VAL(val) (((val) & 0x1) << 3) -+#define PORT_P0_ALTSEL1_P3_GET(val) ((((val) & PORT_P0_ALTSEL1_P3) >> 3) & 0x1) -+#define PORT_P0_ALTSEL1_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P3) | (((val) & 0x1) << 3)) -+ -+/******************************************************************************* -+ * Port 0 Pull Up Enable Register -+ ******************************************************************************/ -+ -+/* Pull Up Device Enable at Port 0 Bit # (19) */ -+#define PORT_P0_PUEN_P19 (0x1 << 19) -+#define PORT_P0_PUEN_P19_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P0_PUEN_P19_GET(val) ((((val) & PORT_P0_PUEN_P19) >> 19) & 0x1) -+#define PORT_P0_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P19) | (((val) & 0x1) << 19)) -+/* Pull Up Device Enable at Port 0 Bit # (18) */ -+#define PORT_P0_PUEN_P18 (0x1 << 18) -+#define PORT_P0_PUEN_P18_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P0_PUEN_P18_GET(val) ((((val) & PORT_P0_PUEN_P18) >> 18) & 0x1) -+#define PORT_P0_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P18) | (((val) & 0x1) << 18)) -+/* Pull Up Device Enable at Port 0 Bit # (17) */ -+#define PORT_P0_PUEN_P17 (0x1 << 17) -+#define PORT_P0_PUEN_P17_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P0_PUEN_P17_GET(val) ((((val) & PORT_P0_PUEN_P17) >> 17) & 0x1) -+#define PORT_P0_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P17) | (((val) & 0x1) << 17)) -+/* Pull Up Device Enable at Port 0 Bit # (16) */ -+#define PORT_P0_PUEN_P16 (0x1 << 16) -+#define PORT_P0_PUEN_P16_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P0_PUEN_P16_GET(val) ((((val) & PORT_P0_PUEN_P16) >> 16) & 0x1) -+#define PORT_P0_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P16) | (((val) & 0x1) << 16)) -+/* Pull Up Device Enable at Port 0 Bit # (15) */ -+#define PORT_P0_PUEN_P15 (0x1 << 15) -+#define PORT_P0_PUEN_P15_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P0_PUEN_P15_GET(val) ((((val) & PORT_P0_PUEN_P15) >> 15) & 0x1) -+#define PORT_P0_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P15) | (((val) & 0x1) << 15)) -+/* Pull Up Device Enable at Port 0 Bit # (14) */ -+#define PORT_P0_PUEN_P14 (0x1 << 14) -+#define PORT_P0_PUEN_P14_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P0_PUEN_P14_GET(val) ((((val) & PORT_P0_PUEN_P14) >> 14) & 0x1) -+#define PORT_P0_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P14) | (((val) & 0x1) << 14)) -+/* Pull Up Device Enable at Port 0 Bit # (13) */ -+#define PORT_P0_PUEN_P13 (0x1 << 13) -+#define PORT_P0_PUEN_P13_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P0_PUEN_P13_GET(val) ((((val) & PORT_P0_PUEN_P13) >> 13) & 0x1) -+#define PORT_P0_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P13) | (((val) & 0x1) << 13)) -+/* Pull Up Device Enable at Port 0 Bit # (12) */ -+#define PORT_P0_PUEN_P12 (0x1 << 12) -+#define PORT_P0_PUEN_P12_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P0_PUEN_P12_GET(val) ((((val) & PORT_P0_PUEN_P12) >> 12) & 0x1) -+#define PORT_P0_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P12) | (((val) & 0x1) << 12)) -+/* Pull Up Device Enable at Port 0 Bit # (11) */ -+#define PORT_P0_PUEN_P11 (0x1 << 11) -+#define PORT_P0_PUEN_P11_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P0_PUEN_P11_GET(val) ((((val) & PORT_P0_PUEN_P11) >> 11) & 0x1) -+#define PORT_P0_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P11) | (((val) & 0x1) << 11)) -+/* Pull Up Device Enable at Port 0 Bit # (10) */ -+#define PORT_P0_PUEN_P10 (0x1 << 10) -+#define PORT_P0_PUEN_P10_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P0_PUEN_P10_GET(val) ((((val) & PORT_P0_PUEN_P10) >> 10) & 0x1) -+#define PORT_P0_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P10) | (((val) & 0x1) << 10)) -+/* Pull Up Device Enable at Port 0 Bit # (9) */ -+#define PORT_P0_PUEN_P9 (0x1 << 9) -+#define PORT_P0_PUEN_P9_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P0_PUEN_P9_GET(val) ((((val) & PORT_P0_PUEN_P9) >> 9) & 0x1) -+#define PORT_P0_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P9) | (((val) & 0x1) << 9)) -+/* Pull Up Device Enable at Port 0 Bit # (8) */ -+#define PORT_P0_PUEN_P8 (0x1 << 8) -+#define PORT_P0_PUEN_P8_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P0_PUEN_P8_GET(val) ((((val) & PORT_P0_PUEN_P8) >> 8) & 0x1) -+#define PORT_P0_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P8) | (((val) & 0x1) << 8)) -+/* Pull Up Device Enable at Port 0 Bit # (7) */ -+#define PORT_P0_PUEN_P7 (0x1 << 7) -+#define PORT_P0_PUEN_P7_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P0_PUEN_P7_GET(val) ((((val) & PORT_P0_PUEN_P7) >> 7) & 0x1) -+#define PORT_P0_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P7) | (((val) & 0x1) << 7)) -+/* Pull Up Device Enable at Port 0 Bit # (6) */ -+#define PORT_P0_PUEN_P6 (0x1 << 6) -+#define PORT_P0_PUEN_P6_VAL(val) (((val) & 0x1) << 6) -+#define PORT_P0_PUEN_P6_GET(val) ((((val) & PORT_P0_PUEN_P6) >> 6) & 0x1) -+#define PORT_P0_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P6) | (((val) & 0x1) << 6)) -+/* Pull Up Device Enable at Port 0 Bit # (5) */ -+#define PORT_P0_PUEN_P5 (0x1 << 5) -+#define PORT_P0_PUEN_P5_VAL(val) (((val) & 0x1) << 5) -+#define PORT_P0_PUEN_P5_GET(val) ((((val) & PORT_P0_PUEN_P5) >> 5) & 0x1) -+#define PORT_P0_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P5) | (((val) & 0x1) << 5)) -+/* Pull Up Device Enable at Port 0 Bit # (4) */ -+#define PORT_P0_PUEN_P4 (0x1 << 4) -+#define PORT_P0_PUEN_P4_VAL(val) (((val) & 0x1) << 4) -+#define PORT_P0_PUEN_P4_GET(val) ((((val) & PORT_P0_PUEN_P4) >> 4) & 0x1) -+#define PORT_P0_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P4) | (((val) & 0x1) << 4)) -+/* Pull Up Device Enable at Port 0 Bit # (3) */ -+#define PORT_P0_PUEN_P3 (0x1 << 3) -+#define PORT_P0_PUEN_P3_VAL(val) (((val) & 0x1) << 3) -+#define PORT_P0_PUEN_P3_GET(val) ((((val) & PORT_P0_PUEN_P3) >> 3) & 0x1) -+#define PORT_P0_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P3) | (((val) & 0x1) << 3)) -+/* Pull Up Device Enable at Port 0 Bit # (2) */ -+#define PORT_P0_PUEN_P2 (0x1 << 2) -+#define PORT_P0_PUEN_P2_VAL(val) (((val) & 0x1) << 2) -+#define PORT_P0_PUEN_P2_GET(val) ((((val) & PORT_P0_PUEN_P2) >> 2) & 0x1) -+#define PORT_P0_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P2) | (((val) & 0x1) << 2)) -+/* Pull Up Device Enable at Port 0 Bit # (1) */ -+#define PORT_P0_PUEN_P1 (0x1 << 1) -+#define PORT_P0_PUEN_P1_VAL(val) (((val) & 0x1) << 1) -+#define PORT_P0_PUEN_P1_GET(val) ((((val) & PORT_P0_PUEN_P1) >> 1) & 0x1) -+#define PORT_P0_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P1) | (((val) & 0x1) << 1)) -+/* Pull Up Device Enable at Port 0 Bit # (0) */ -+#define PORT_P0_PUEN_P0 (0x1) -+#define PORT_P0_PUEN_P0_VAL(val) (((val) & 0x1) << 0) -+#define PORT_P0_PUEN_P0_GET(val) ((((val) & PORT_P0_PUEN_P0) >> 0) & 0x1) -+#define PORT_P0_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P0) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * External Interrupt Control Register 0 -+ ******************************************************************************/ -+ -+/* Type of Level or Edge Detection of EXINT16 (19) */ -+#define PORT_P0_EXINTCR0_EXINT16 (0x1 << 19) -+#define PORT_P0_EXINTCR0_EXINT16_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P0_EXINTCR0_EXINT16_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT16) >> 19) & 0x1) -+#define PORT_P0_EXINTCR0_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT16) | (((val) & 0x1) << 19)) -+/* Type of Level or Edge Detection of EXINT10 (17) */ -+#define PORT_P0_EXINTCR0_EXINT10 (0x1 << 17) -+#define PORT_P0_EXINTCR0_EXINT10_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P0_EXINTCR0_EXINT10_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT10) >> 17) & 0x1) -+#define PORT_P0_EXINTCR0_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT10) | (((val) & 0x1) << 17)) -+/* Type of Level or Edge Detection of EXINT9 (16) */ -+#define PORT_P0_EXINTCR0_EXINT9 (0x1 << 16) -+#define PORT_P0_EXINTCR0_EXINT9_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P0_EXINTCR0_EXINT9_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT9) >> 16) & 0x1) -+#define PORT_P0_EXINTCR0_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT9) | (((val) & 0x1) << 16)) -+/* Type of Level or Edge Detection of EXINT8 (15) */ -+#define PORT_P0_EXINTCR0_EXINT8 (0x1 << 15) -+#define PORT_P0_EXINTCR0_EXINT8_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P0_EXINTCR0_EXINT8_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT8) >> 15) & 0x1) -+#define PORT_P0_EXINTCR0_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT8) | (((val) & 0x1) << 15)) -+/* Type of Level or Edge Detection of EXINT7 (14) */ -+#define PORT_P0_EXINTCR0_EXINT7 (0x1 << 14) -+#define PORT_P0_EXINTCR0_EXINT7_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P0_EXINTCR0_EXINT7_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT7) >> 14) & 0x1) -+#define PORT_P0_EXINTCR0_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT7) | (((val) & 0x1) << 14)) -+/* Type of Level or Edge Detection of EXINT6 (13) */ -+#define PORT_P0_EXINTCR0_EXINT6 (0x1 << 13) -+#define PORT_P0_EXINTCR0_EXINT6_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P0_EXINTCR0_EXINT6_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT6) >> 13) & 0x1) -+#define PORT_P0_EXINTCR0_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT6) | (((val) & 0x1) << 13)) -+/* Type of Level or Edge Detection of EXINT5 (12) */ -+#define PORT_P0_EXINTCR0_EXINT5 (0x1 << 12) -+#define PORT_P0_EXINTCR0_EXINT5_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P0_EXINTCR0_EXINT5_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT5) >> 12) & 0x1) -+#define PORT_P0_EXINTCR0_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT5) | (((val) & 0x1) << 12)) -+/* Type of Level or Edge Detection of EXINT4 (11) */ -+#define PORT_P0_EXINTCR0_EXINT4 (0x1 << 11) -+#define PORT_P0_EXINTCR0_EXINT4_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P0_EXINTCR0_EXINT4_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT4) >> 11) & 0x1) -+#define PORT_P0_EXINTCR0_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT4) | (((val) & 0x1) << 11)) -+/* Type of Level or Edge Detection of EXINT3 (10) */ -+#define PORT_P0_EXINTCR0_EXINT3 (0x1 << 10) -+#define PORT_P0_EXINTCR0_EXINT3_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P0_EXINTCR0_EXINT3_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT3) >> 10) & 0x1) -+#define PORT_P0_EXINTCR0_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT3) | (((val) & 0x1) << 10)) -+/* Type of Level or Edge Detection of EXINT2 (9) */ -+#define PORT_P0_EXINTCR0_EXINT2 (0x1 << 9) -+#define PORT_P0_EXINTCR0_EXINT2_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P0_EXINTCR0_EXINT2_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT2) >> 9) & 0x1) -+#define PORT_P0_EXINTCR0_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT2) | (((val) & 0x1) << 9)) -+/* Type of Level or Edge Detection of EXINT1 (8) */ -+#define PORT_P0_EXINTCR0_EXINT1 (0x1 << 8) -+#define PORT_P0_EXINTCR0_EXINT1_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P0_EXINTCR0_EXINT1_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT1) >> 8) & 0x1) -+#define PORT_P0_EXINTCR0_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT1) | (((val) & 0x1) << 8)) -+/* Type of Level or Edge Detection of EXINT0 (7) */ -+#define PORT_P0_EXINTCR0_EXINT0 (0x1 << 7) -+#define PORT_P0_EXINTCR0_EXINT0_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P0_EXINTCR0_EXINT0_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT0) >> 7) & 0x1) -+#define PORT_P0_EXINTCR0_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT0) | (((val) & 0x1) << 7)) -+ -+/******************************************************************************* -+ * External Interrupt Control Register 1 -+ ******************************************************************************/ -+ -+/* Type of Level or Edge Detection of EXINT16 (19) */ -+#define PORT_P0_EXINTCR1_EXINT16 (0x1 << 19) -+#define PORT_P0_EXINTCR1_EXINT16_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P0_EXINTCR1_EXINT16_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT16) >> 19) & 0x1) -+#define PORT_P0_EXINTCR1_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT16) | (((val) & 0x1) << 19)) -+/* Type of Level or Edge Detection of EXINT10 (17) */ -+#define PORT_P0_EXINTCR1_EXINT10 (0x1 << 17) -+#define PORT_P0_EXINTCR1_EXINT10_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P0_EXINTCR1_EXINT10_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT10) >> 17) & 0x1) -+#define PORT_P0_EXINTCR1_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT10) | (((val) & 0x1) << 17)) -+/* Type of Level or Edge Detection of EXINT9 (16) */ -+#define PORT_P0_EXINTCR1_EXINT9 (0x1 << 16) -+#define PORT_P0_EXINTCR1_EXINT9_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P0_EXINTCR1_EXINT9_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT9) >> 16) & 0x1) -+#define PORT_P0_EXINTCR1_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT9) | (((val) & 0x1) << 16)) -+/* Type of Level or Edge Detection of EXINT8 (15) */ -+#define PORT_P0_EXINTCR1_EXINT8 (0x1 << 15) -+#define PORT_P0_EXINTCR1_EXINT8_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P0_EXINTCR1_EXINT8_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT8) >> 15) & 0x1) -+#define PORT_P0_EXINTCR1_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT8) | (((val) & 0x1) << 15)) -+/* Type of Level or Edge Detection of EXINT7 (14) */ -+#define PORT_P0_EXINTCR1_EXINT7 (0x1 << 14) -+#define PORT_P0_EXINTCR1_EXINT7_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P0_EXINTCR1_EXINT7_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT7) >> 14) & 0x1) -+#define PORT_P0_EXINTCR1_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT7) | (((val) & 0x1) << 14)) -+/* Type of Level or Edge Detection of EXINT6 (13) */ -+#define PORT_P0_EXINTCR1_EXINT6 (0x1 << 13) -+#define PORT_P0_EXINTCR1_EXINT6_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P0_EXINTCR1_EXINT6_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT6) >> 13) & 0x1) -+#define PORT_P0_EXINTCR1_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT6) | (((val) & 0x1) << 13)) -+/* Type of Level or Edge Detection of EXINT5 (12) */ -+#define PORT_P0_EXINTCR1_EXINT5 (0x1 << 12) -+#define PORT_P0_EXINTCR1_EXINT5_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P0_EXINTCR1_EXINT5_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT5) >> 12) & 0x1) -+#define PORT_P0_EXINTCR1_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT5) | (((val) & 0x1) << 12)) -+/* Type of Level or Edge Detection of EXINT4 (11) */ -+#define PORT_P0_EXINTCR1_EXINT4 (0x1 << 11) -+#define PORT_P0_EXINTCR1_EXINT4_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P0_EXINTCR1_EXINT4_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT4) >> 11) & 0x1) -+#define PORT_P0_EXINTCR1_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT4) | (((val) & 0x1) << 11)) -+/* Type of Level or Edge Detection of EXINT3 (10) */ -+#define PORT_P0_EXINTCR1_EXINT3 (0x1 << 10) -+#define PORT_P0_EXINTCR1_EXINT3_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P0_EXINTCR1_EXINT3_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT3) >> 10) & 0x1) -+#define PORT_P0_EXINTCR1_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT3) | (((val) & 0x1) << 10)) -+/* Type of Level or Edge Detection of EXINT2 (9) */ -+#define PORT_P0_EXINTCR1_EXINT2 (0x1 << 9) -+#define PORT_P0_EXINTCR1_EXINT2_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P0_EXINTCR1_EXINT2_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT2) >> 9) & 0x1) -+#define PORT_P0_EXINTCR1_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT2) | (((val) & 0x1) << 9)) -+/* Type of Level or Edge Detection of EXINT1 (8) */ -+#define PORT_P0_EXINTCR1_EXINT1 (0x1 << 8) -+#define PORT_P0_EXINTCR1_EXINT1_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P0_EXINTCR1_EXINT1_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT1) >> 8) & 0x1) -+#define PORT_P0_EXINTCR1_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT1) | (((val) & 0x1) << 8)) -+/* Type of Level or Edge Detection of EXINT0 (7) */ -+#define PORT_P0_EXINTCR1_EXINT0 (0x1 << 7) -+#define PORT_P0_EXINTCR1_EXINT0_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P0_EXINTCR1_EXINT0_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT0) >> 7) & 0x1) -+#define PORT_P0_EXINTCR1_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT0) | (((val) & 0x1) << 7)) -+ -+/******************************************************************************* -+ * P0_IRNEN Register -+ ******************************************************************************/ -+ -+/* EXINT16 Interrupt Request Enable (19) */ -+#define PORT_P0_IRNEN_EXINT16 (0x1 << 19) -+#define PORT_P0_IRNEN_EXINT16_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P0_IRNEN_EXINT16_GET(val) ((((val) & PORT_P0_IRNEN_EXINT16) >> 19) & 0x1) -+#define PORT_P0_IRNEN_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT16) | (((val) & 0x1) << 19)) -+/* EXINT10 Interrupt Request Enable (17) */ -+#define PORT_P0_IRNEN_EXINT10 (0x1 << 17) -+#define PORT_P0_IRNEN_EXINT10_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P0_IRNEN_EXINT10_GET(val) ((((val) & PORT_P0_IRNEN_EXINT10) >> 17) & 0x1) -+#define PORT_P0_IRNEN_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT10) | (((val) & 0x1) << 17)) -+/* EXINT9 Interrupt Request Enable (16) */ -+#define PORT_P0_IRNEN_EXINT9 (0x1 << 16) -+#define PORT_P0_IRNEN_EXINT9_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P0_IRNEN_EXINT9_GET(val) ((((val) & PORT_P0_IRNEN_EXINT9) >> 16) & 0x1) -+#define PORT_P0_IRNEN_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT9) | (((val) & 0x1) << 16)) -+/* EXINT8 Interrupt Request Enable (15) */ -+#define PORT_P0_IRNEN_EXINT8 (0x1 << 15) -+#define PORT_P0_IRNEN_EXINT8_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P0_IRNEN_EXINT8_GET(val) ((((val) & PORT_P0_IRNEN_EXINT8) >> 15) & 0x1) -+#define PORT_P0_IRNEN_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT8) | (((val) & 0x1) << 15)) -+/* EXINT7 Interrupt Request Enable (14) */ -+#define PORT_P0_IRNEN_EXINT7 (0x1 << 14) -+#define PORT_P0_IRNEN_EXINT7_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P0_IRNEN_EXINT7_GET(val) ((((val) & PORT_P0_IRNEN_EXINT7) >> 14) & 0x1) -+#define PORT_P0_IRNEN_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT7) | (((val) & 0x1) << 14)) -+/* EXINT6 Interrupt Request Enable (13) */ -+#define PORT_P0_IRNEN_EXINT6 (0x1 << 13) -+#define PORT_P0_IRNEN_EXINT6_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P0_IRNEN_EXINT6_GET(val) ((((val) & PORT_P0_IRNEN_EXINT6) >> 13) & 0x1) -+#define PORT_P0_IRNEN_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT6) | (((val) & 0x1) << 13)) -+/* EXINT5 Interrupt Request Enable (12) */ -+#define PORT_P0_IRNEN_EXINT5 (0x1 << 12) -+#define PORT_P0_IRNEN_EXINT5_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P0_IRNEN_EXINT5_GET(val) ((((val) & PORT_P0_IRNEN_EXINT5) >> 12) & 0x1) -+#define PORT_P0_IRNEN_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT5) | (((val) & 0x1) << 12)) -+/* EXINT4 Interrupt Request Enable (11) */ -+#define PORT_P0_IRNEN_EXINT4 (0x1 << 11) -+#define PORT_P0_IRNEN_EXINT4_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P0_IRNEN_EXINT4_GET(val) ((((val) & PORT_P0_IRNEN_EXINT4) >> 11) & 0x1) -+#define PORT_P0_IRNEN_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT4) | (((val) & 0x1) << 11)) -+/* EXINT3 Interrupt Request Enable (10) */ -+#define PORT_P0_IRNEN_EXINT3 (0x1 << 10) -+#define PORT_P0_IRNEN_EXINT3_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P0_IRNEN_EXINT3_GET(val) ((((val) & PORT_P0_IRNEN_EXINT3) >> 10) & 0x1) -+#define PORT_P0_IRNEN_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT3) | (((val) & 0x1) << 10)) -+/* EXINT2 Interrupt Request Enable (9) */ -+#define PORT_P0_IRNEN_EXINT2 (0x1 << 9) -+#define PORT_P0_IRNEN_EXINT2_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P0_IRNEN_EXINT2_GET(val) ((((val) & PORT_P0_IRNEN_EXINT2) >> 9) & 0x1) -+#define PORT_P0_IRNEN_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT2) | (((val) & 0x1) << 9)) -+/* EXINT1 Interrupt Request Enable (8) */ -+#define PORT_P0_IRNEN_EXINT1 (0x1 << 8) -+#define PORT_P0_IRNEN_EXINT1_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P0_IRNEN_EXINT1_GET(val) ((((val) & PORT_P0_IRNEN_EXINT1) >> 8) & 0x1) -+#define PORT_P0_IRNEN_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT1) | (((val) & 0x1) << 8)) -+/* EXINT0 Interrupt Request Enable (7) */ -+#define PORT_P0_IRNEN_EXINT0 (0x1 << 7) -+#define PORT_P0_IRNEN_EXINT0_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P0_IRNEN_EXINT0_GET(val) ((((val) & PORT_P0_IRNEN_EXINT0) >> 7) & 0x1) -+#define PORT_P0_IRNEN_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT0) | (((val) & 0x1) << 7)) -+ -+/******************************************************************************* -+ * P0_IRNICR Register -+ ******************************************************************************/ -+ -+/* EXINT16 Interrupt Request (19) */ -+#define PORT_P0_IRNICR_EXINT16 (0x1 << 19) -+#define PORT_P0_IRNICR_EXINT16_GET(val) ((((val) & PORT_P0_IRNICR_EXINT16) >> 19) & 0x1) -+/* EXINT10 Interrupt Request (17) */ -+#define PORT_P0_IRNICR_EXINT10 (0x1 << 17) -+#define PORT_P0_IRNICR_EXINT10_GET(val) ((((val) & PORT_P0_IRNICR_EXINT10) >> 17) & 0x1) -+/* EXINT9 Interrupt Request (16) */ -+#define PORT_P0_IRNICR_EXINT9 (0x1 << 16) -+#define PORT_P0_IRNICR_EXINT9_GET(val) ((((val) & PORT_P0_IRNICR_EXINT9) >> 16) & 0x1) -+/* EXINT8 Interrupt Request (15) */ -+#define PORT_P0_IRNICR_EXINT8 (0x1 << 15) -+#define PORT_P0_IRNICR_EXINT8_GET(val) ((((val) & PORT_P0_IRNICR_EXINT8) >> 15) & 0x1) -+/* EXINT7 Interrupt Request (14) */ -+#define PORT_P0_IRNICR_EXINT7 (0x1 << 14) -+#define PORT_P0_IRNICR_EXINT7_GET(val) ((((val) & PORT_P0_IRNICR_EXINT7) >> 14) & 0x1) -+/* EXINT6 Interrupt Request (13) */ -+#define PORT_P0_IRNICR_EXINT6 (0x1 << 13) -+#define PORT_P0_IRNICR_EXINT6_GET(val) ((((val) & PORT_P0_IRNICR_EXINT6) >> 13) & 0x1) -+/* EXINT5 Interrupt Request (12) */ -+#define PORT_P0_IRNICR_EXINT5 (0x1 << 12) -+#define PORT_P0_IRNICR_EXINT5_GET(val) ((((val) & PORT_P0_IRNICR_EXINT5) >> 12) & 0x1) -+/* EXINT4 Interrupt Request (11) */ -+#define PORT_P0_IRNICR_EXINT4 (0x1 << 11) -+#define PORT_P0_IRNICR_EXINT4_GET(val) ((((val) & PORT_P0_IRNICR_EXINT4) >> 11) & 0x1) -+/* EXINT3 Interrupt Request (10) */ -+#define PORT_P0_IRNICR_EXINT3 (0x1 << 10) -+#define PORT_P0_IRNICR_EXINT3_GET(val) ((((val) & PORT_P0_IRNICR_EXINT3) >> 10) & 0x1) -+/* EXINT2 Interrupt Request (9) */ -+#define PORT_P0_IRNICR_EXINT2 (0x1 << 9) -+#define PORT_P0_IRNICR_EXINT2_GET(val) ((((val) & PORT_P0_IRNICR_EXINT2) >> 9) & 0x1) -+/* EXINT1 Interrupt Request (8) */ -+#define PORT_P0_IRNICR_EXINT1 (0x1 << 8) -+#define PORT_P0_IRNICR_EXINT1_GET(val) ((((val) & PORT_P0_IRNICR_EXINT1) >> 8) & 0x1) -+/* EXINT0 Interrupt Request (7) */ -+#define PORT_P0_IRNICR_EXINT0 (0x1 << 7) -+#define PORT_P0_IRNICR_EXINT0_GET(val) ((((val) & PORT_P0_IRNICR_EXINT0) >> 7) & 0x1) -+ -+/******************************************************************************* -+ * P0_IRNCR Register -+ ******************************************************************************/ -+ -+/* EXINT16 Interrupt Request (19) */ -+#define PORT_P0_IRNCR_EXINT16 (0x1 << 19) -+#define PORT_P0_IRNCR_EXINT16_GET(val) ((((val) & PORT_P0_IRNCR_EXINT16) >> 19) & 0x1) -+/* EXINT10 Interrupt Request (17) */ -+#define PORT_P0_IRNCR_EXINT10 (0x1 << 17) -+#define PORT_P0_IRNCR_EXINT10_GET(val) ((((val) & PORT_P0_IRNCR_EXINT10) >> 17) & 0x1) -+/* EXINT9 Interrupt Request (16) */ -+#define PORT_P0_IRNCR_EXINT9 (0x1 << 16) -+#define PORT_P0_IRNCR_EXINT9_GET(val) ((((val) & PORT_P0_IRNCR_EXINT9) >> 16) & 0x1) -+/* EXINT8 Interrupt Request (15) */ -+#define PORT_P0_IRNCR_EXINT8 (0x1 << 15) -+#define PORT_P0_IRNCR_EXINT8_GET(val) ((((val) & PORT_P0_IRNCR_EXINT8) >> 15) & 0x1) -+/* EXINT7 Interrupt Request (14) */ -+#define PORT_P0_IRNCR_EXINT7 (0x1 << 14) -+#define PORT_P0_IRNCR_EXINT7_GET(val) ((((val) & PORT_P0_IRNCR_EXINT7) >> 14) & 0x1) -+/* EXINT6 Interrupt Request (13) */ -+#define PORT_P0_IRNCR_EXINT6 (0x1 << 13) -+#define PORT_P0_IRNCR_EXINT6_GET(val) ((((val) & PORT_P0_IRNCR_EXINT6) >> 13) & 0x1) -+/* EXINT5 Interrupt Request (12) */ -+#define PORT_P0_IRNCR_EXINT5 (0x1 << 12) -+#define PORT_P0_IRNCR_EXINT5_GET(val) ((((val) & PORT_P0_IRNCR_EXINT5) >> 12) & 0x1) -+/* EXINT4 Interrupt Request (11) */ -+#define PORT_P0_IRNCR_EXINT4 (0x1 << 11) -+#define PORT_P0_IRNCR_EXINT4_GET(val) ((((val) & PORT_P0_IRNCR_EXINT4) >> 11) & 0x1) -+/* EXINT3 Interrupt Request (10) */ -+#define PORT_P0_IRNCR_EXINT3 (0x1 << 10) -+#define PORT_P0_IRNCR_EXINT3_GET(val) ((((val) & PORT_P0_IRNCR_EXINT3) >> 10) & 0x1) -+/* EXINT2 Interrupt Request (9) */ -+#define PORT_P0_IRNCR_EXINT2 (0x1 << 9) -+#define PORT_P0_IRNCR_EXINT2_GET(val) ((((val) & PORT_P0_IRNCR_EXINT2) >> 9) & 0x1) -+/* EXINT1 Interrupt Request (8) */ -+#define PORT_P0_IRNCR_EXINT1 (0x1 << 8) -+#define PORT_P0_IRNCR_EXINT1_GET(val) ((((val) & PORT_P0_IRNCR_EXINT1) >> 8) & 0x1) -+/* EXINT0 Interrupt Request (7) */ -+#define PORT_P0_IRNCR_EXINT0 (0x1 << 7) -+#define PORT_P0_IRNCR_EXINT0_GET(val) ((((val) & PORT_P0_IRNCR_EXINT0) >> 7) & 0x1) -+ -+/******************************************************************************* -+ * P0 External Event Detection Configuration Register -+ ******************************************************************************/ -+ -+/* EXINT16 configured for Edge or Level Detection (19) */ -+#define PORT_P0_IRNCFG_EXINT16 (0x1 << 19) -+#define PORT_P0_IRNCFG_EXINT16_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P0_IRNCFG_EXINT16_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT16) >> 19) & 0x1) -+#define PORT_P0_IRNCFG_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT16) | (((val) & 0x1) << 19)) -+/* EXINT10 configured for Edge or Level Detection (17) */ -+#define PORT_P0_IRNCFG_EXINT10 (0x1 << 17) -+#define PORT_P0_IRNCFG_EXINT10_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P0_IRNCFG_EXINT10_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT10) >> 17) & 0x1) -+#define PORT_P0_IRNCFG_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT10) | (((val) & 0x1) << 17)) -+/* EXINT9 configured for Edge or Level Detection (16) */ -+#define PORT_P0_IRNCFG_EXINT9 (0x1 << 16) -+#define PORT_P0_IRNCFG_EXINT9_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P0_IRNCFG_EXINT9_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT9) >> 16) & 0x1) -+#define PORT_P0_IRNCFG_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT9) | (((val) & 0x1) << 16)) -+/* EXINT8 configured for Edge or Level Detection (15) */ -+#define PORT_P0_IRNCFG_EXINT8 (0x1 << 15) -+#define PORT_P0_IRNCFG_EXINT8_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P0_IRNCFG_EXINT8_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT8) >> 15) & 0x1) -+#define PORT_P0_IRNCFG_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT8) | (((val) & 0x1) << 15)) -+/* EXINT7 configured for Edge or Level Detection (14) */ -+#define PORT_P0_IRNCFG_EXINT7 (0x1 << 14) -+#define PORT_P0_IRNCFG_EXINT7_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P0_IRNCFG_EXINT7_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT7) >> 14) & 0x1) -+#define PORT_P0_IRNCFG_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT7) | (((val) & 0x1) << 14)) -+/* EXINT6 configured for Edge or Level Detection (13) */ -+#define PORT_P0_IRNCFG_EXINT6 (0x1 << 13) -+#define PORT_P0_IRNCFG_EXINT6_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P0_IRNCFG_EXINT6_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT6) >> 13) & 0x1) -+#define PORT_P0_IRNCFG_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT6) | (((val) & 0x1) << 13)) -+/* EXINT5 configured for Edge or Level Detection (12) */ -+#define PORT_P0_IRNCFG_EXINT5 (0x1 << 12) -+#define PORT_P0_IRNCFG_EXINT5_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P0_IRNCFG_EXINT5_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT5) >> 12) & 0x1) -+#define PORT_P0_IRNCFG_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT5) | (((val) & 0x1) << 12)) -+/* EXINT4 configured for Edge or Level Detection (11) */ -+#define PORT_P0_IRNCFG_EXINT4 (0x1 << 11) -+#define PORT_P0_IRNCFG_EXINT4_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P0_IRNCFG_EXINT4_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT4) >> 11) & 0x1) -+#define PORT_P0_IRNCFG_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT4) | (((val) & 0x1) << 11)) -+/* EXINT3 configured for Edge or Level Detection (10) */ -+#define PORT_P0_IRNCFG_EXINT3 (0x1 << 10) -+#define PORT_P0_IRNCFG_EXINT3_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P0_IRNCFG_EXINT3_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT3) >> 10) & 0x1) -+#define PORT_P0_IRNCFG_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT3) | (((val) & 0x1) << 10)) -+/* EXINT2 configured for Edge or Level Detection (9) */ -+#define PORT_P0_IRNCFG_EXINT2 (0x1 << 9) -+#define PORT_P0_IRNCFG_EXINT2_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P0_IRNCFG_EXINT2_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT2) >> 9) & 0x1) -+#define PORT_P0_IRNCFG_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT2) | (((val) & 0x1) << 9)) -+/* EXINT1 configured for Edge or Level Detection (8) */ -+#define PORT_P0_IRNCFG_EXINT1 (0x1 << 8) -+#define PORT_P0_IRNCFG_EXINT1_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P0_IRNCFG_EXINT1_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT1) >> 8) & 0x1) -+#define PORT_P0_IRNCFG_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT1) | (((val) & 0x1) << 8)) -+/* EXINT0 configured for Edge or Level Detection (7) */ -+#define PORT_P0_IRNCFG_EXINT0 (0x1 << 7) -+#define PORT_P0_IRNCFG_EXINT0_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P0_IRNCFG_EXINT0_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT0) >> 7) & 0x1) -+#define PORT_P0_IRNCFG_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT0) | (((val) & 0x1) << 7)) -+ -+/******************************************************************************* -+ * P0_IRNENSET Register -+ ******************************************************************************/ -+ -+/* Set Interrupt Node Enable Flag EXINT16 (19) */ -+#define PORT_P0_IRNENSET_EXINT16 (0x1 << 19) -+#define PORT_P0_IRNENSET_EXINT16_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P0_IRNENSET_EXINT16_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT16) | (val) & 1) << 19) -+/* Set Interrupt Node Enable Flag EXINT10 (17) */ -+#define PORT_P0_IRNENSET_EXINT10 (0x1 << 17) -+#define PORT_P0_IRNENSET_EXINT10_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P0_IRNENSET_EXINT10_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT10) | (val) & 1) << 17) -+/* Set Interrupt Node Enable Flag EXINT9 (16) */ -+#define PORT_P0_IRNENSET_EXINT9 (0x1 << 16) -+#define PORT_P0_IRNENSET_EXINT9_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P0_IRNENSET_EXINT9_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT9) | (val) & 1) << 16) -+/* Set Interrupt Node Enable Flag EXINT8 (15) */ -+#define PORT_P0_IRNENSET_EXINT8 (0x1 << 15) -+#define PORT_P0_IRNENSET_EXINT8_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P0_IRNENSET_EXINT8_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT8) | (val) & 1) << 15) -+/* Set Interrupt Node Enable Flag EXINT7 (14) */ -+#define PORT_P0_IRNENSET_EXINT7 (0x1 << 14) -+#define PORT_P0_IRNENSET_EXINT7_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P0_IRNENSET_EXINT7_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT7) | (val) & 1) << 14) -+/* Set Interrupt Node Enable Flag EXINT6 (13) */ -+#define PORT_P0_IRNENSET_EXINT6 (0x1 << 13) -+#define PORT_P0_IRNENSET_EXINT6_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P0_IRNENSET_EXINT6_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT6) | (val) & 1) << 13) -+/* Set Interrupt Node Enable Flag EXINT5 (12) */ -+#define PORT_P0_IRNENSET_EXINT5 (0x1 << 12) -+#define PORT_P0_IRNENSET_EXINT5_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P0_IRNENSET_EXINT5_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT5) | (val) & 1) << 12) -+/* Set Interrupt Node Enable Flag EXINT4 (11) */ -+#define PORT_P0_IRNENSET_EXINT4 (0x1 << 11) -+#define PORT_P0_IRNENSET_EXINT4_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P0_IRNENSET_EXINT4_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT4) | (val) & 1) << 11) -+/* Set Interrupt Node Enable Flag EXINT3 (10) */ -+#define PORT_P0_IRNENSET_EXINT3 (0x1 << 10) -+#define PORT_P0_IRNENSET_EXINT3_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P0_IRNENSET_EXINT3_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT3) | (val) & 1) << 10) -+/* Set Interrupt Node Enable Flag EXINT2 (9) */ -+#define PORT_P0_IRNENSET_EXINT2 (0x1 << 9) -+#define PORT_P0_IRNENSET_EXINT2_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P0_IRNENSET_EXINT2_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT2) | (val) & 1) << 9) -+/* Set Interrupt Node Enable Flag EXINT1 (8) */ -+#define PORT_P0_IRNENSET_EXINT1 (0x1 << 8) -+#define PORT_P0_IRNENSET_EXINT1_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P0_IRNENSET_EXINT1_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT1) | (val) & 1) << 8) -+/* Set Interrupt Node Enable Flag EXINT0 (7) */ -+#define PORT_P0_IRNENSET_EXINT0 (0x1 << 7) -+#define PORT_P0_IRNENSET_EXINT0_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P0_IRNENSET_EXINT0_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT0) | (val) & 1) << 7) -+ -+/******************************************************************************* -+ * P0_IRNENCLR Register -+ ******************************************************************************/ -+ -+/* Clear Interrupt Node Enable Flag EXINT16 (19) */ -+#define PORT_P0_IRNENCLR_EXINT16 (0x1 << 19) -+#define PORT_P0_IRNENCLR_EXINT16_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P0_IRNENCLR_EXINT16_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT16) | (val) & 1) << 19) -+/* Clear Interrupt Node Enable Flag EXINT10 (17) */ -+#define PORT_P0_IRNENCLR_EXINT10 (0x1 << 17) -+#define PORT_P0_IRNENCLR_EXINT10_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P0_IRNENCLR_EXINT10_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT10) | (val) & 1) << 17) -+/* Clear Interrupt Node Enable Flag EXINT9 (16) */ -+#define PORT_P0_IRNENCLR_EXINT9 (0x1 << 16) -+#define PORT_P0_IRNENCLR_EXINT9_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P0_IRNENCLR_EXINT9_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT9) | (val) & 1) << 16) -+/* Clear Interrupt Node Enable Flag EXINT8 (15) */ -+#define PORT_P0_IRNENCLR_EXINT8 (0x1 << 15) -+#define PORT_P0_IRNENCLR_EXINT8_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P0_IRNENCLR_EXINT8_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT8) | (val) & 1) << 15) -+/* Clear Interrupt Node Enable Flag EXINT7 (14) */ -+#define PORT_P0_IRNENCLR_EXINT7 (0x1 << 14) -+#define PORT_P0_IRNENCLR_EXINT7_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P0_IRNENCLR_EXINT7_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT7) | (val) & 1) << 14) -+/* Clear Interrupt Node Enable Flag EXINT6 (13) */ -+#define PORT_P0_IRNENCLR_EXINT6 (0x1 << 13) -+#define PORT_P0_IRNENCLR_EXINT6_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P0_IRNENCLR_EXINT6_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT6) | (val) & 1) << 13) -+/* Clear Interrupt Node Enable Flag EXINT5 (12) */ -+#define PORT_P0_IRNENCLR_EXINT5 (0x1 << 12) -+#define PORT_P0_IRNENCLR_EXINT5_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P0_IRNENCLR_EXINT5_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT5) | (val) & 1) << 12) -+/* Clear Interrupt Node Enable Flag EXINT4 (11) */ -+#define PORT_P0_IRNENCLR_EXINT4 (0x1 << 11) -+#define PORT_P0_IRNENCLR_EXINT4_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P0_IRNENCLR_EXINT4_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT4) | (val) & 1) << 11) -+/* Clear Interrupt Node Enable Flag EXINT3 (10) */ -+#define PORT_P0_IRNENCLR_EXINT3 (0x1 << 10) -+#define PORT_P0_IRNENCLR_EXINT3_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P0_IRNENCLR_EXINT3_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT3) | (val) & 1) << 10) -+/* Clear Interrupt Node Enable Flag EXINT2 (9) */ -+#define PORT_P0_IRNENCLR_EXINT2 (0x1 << 9) -+#define PORT_P0_IRNENCLR_EXINT2_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P0_IRNENCLR_EXINT2_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT2) | (val) & 1) << 9) -+/* Clear Interrupt Node Enable Flag EXINT1 (8) */ -+#define PORT_P0_IRNENCLR_EXINT1 (0x1 << 8) -+#define PORT_P0_IRNENCLR_EXINT1_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P0_IRNENCLR_EXINT1_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT1) | (val) & 1) << 8) -+/* Clear Interrupt Node Enable Flag EXINT0 (7) */ -+#define PORT_P0_IRNENCLR_EXINT0 (0x1 << 7) -+#define PORT_P0_IRNENCLR_EXINT0_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P0_IRNENCLR_EXINT0_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT0) | (val) & 1) << 7) -+ -+/******************************************************************************* -+ * Port 1 Data Output Register -+ ******************************************************************************/ -+ -+/* Port 1 Pin # Output Value (19) */ -+#define PORT_P1_OUT_P19 (0x1 << 19) -+#define PORT_P1_OUT_P19_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P1_OUT_P19_GET(val) ((((val) & PORT_P1_OUT_P19) >> 19) & 0x1) -+#define PORT_P1_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P19) | (((val) & 0x1) << 19)) -+/* Port 1 Pin # Output Value (18) */ -+#define PORT_P1_OUT_P18 (0x1 << 18) -+#define PORT_P1_OUT_P18_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P1_OUT_P18_GET(val) ((((val) & PORT_P1_OUT_P18) >> 18) & 0x1) -+#define PORT_P1_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P18) | (((val) & 0x1) << 18)) -+/* Port 1 Pin # Output Value (17) */ -+#define PORT_P1_OUT_P17 (0x1 << 17) -+#define PORT_P1_OUT_P17_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P1_OUT_P17_GET(val) ((((val) & PORT_P1_OUT_P17) >> 17) & 0x1) -+#define PORT_P1_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P17) | (((val) & 0x1) << 17)) -+/* Port 1 Pin # Output Value (16) */ -+#define PORT_P1_OUT_P16 (0x1 << 16) -+#define PORT_P1_OUT_P16_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P1_OUT_P16_GET(val) ((((val) & PORT_P1_OUT_P16) >> 16) & 0x1) -+#define PORT_P1_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P16) | (((val) & 0x1) << 16)) -+/* Port 1 Pin # Output Value (15) */ -+#define PORT_P1_OUT_P15 (0x1 << 15) -+#define PORT_P1_OUT_P15_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P1_OUT_P15_GET(val) ((((val) & PORT_P1_OUT_P15) >> 15) & 0x1) -+#define PORT_P1_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P15) | (((val) & 0x1) << 15)) -+/* Port 1 Pin # Output Value (14) */ -+#define PORT_P1_OUT_P14 (0x1 << 14) -+#define PORT_P1_OUT_P14_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P1_OUT_P14_GET(val) ((((val) & PORT_P1_OUT_P14) >> 14) & 0x1) -+#define PORT_P1_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P14) | (((val) & 0x1) << 14)) -+/* Port 1 Pin # Output Value (13) */ -+#define PORT_P1_OUT_P13 (0x1 << 13) -+#define PORT_P1_OUT_P13_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P1_OUT_P13_GET(val) ((((val) & PORT_P1_OUT_P13) >> 13) & 0x1) -+#define PORT_P1_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P13) | (((val) & 0x1) << 13)) -+/* Port 1 Pin # Output Value (12) */ -+#define PORT_P1_OUT_P12 (0x1 << 12) -+#define PORT_P1_OUT_P12_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P1_OUT_P12_GET(val) ((((val) & PORT_P1_OUT_P12) >> 12) & 0x1) -+#define PORT_P1_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P12) | (((val) & 0x1) << 12)) -+/* Port 1 Pin # Output Value (11) */ -+#define PORT_P1_OUT_P11 (0x1 << 11) -+#define PORT_P1_OUT_P11_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P1_OUT_P11_GET(val) ((((val) & PORT_P1_OUT_P11) >> 11) & 0x1) -+#define PORT_P1_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P11) | (((val) & 0x1) << 11)) -+/* Port 1 Pin # Output Value (10) */ -+#define PORT_P1_OUT_P10 (0x1 << 10) -+#define PORT_P1_OUT_P10_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P1_OUT_P10_GET(val) ((((val) & PORT_P1_OUT_P10) >> 10) & 0x1) -+#define PORT_P1_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P10) | (((val) & 0x1) << 10)) -+/* Port 1 Pin # Output Value (9) */ -+#define PORT_P1_OUT_P9 (0x1 << 9) -+#define PORT_P1_OUT_P9_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P1_OUT_P9_GET(val) ((((val) & PORT_P1_OUT_P9) >> 9) & 0x1) -+#define PORT_P1_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P9) | (((val) & 0x1) << 9)) -+/* Port 1 Pin # Output Value (8) */ -+#define PORT_P1_OUT_P8 (0x1 << 8) -+#define PORT_P1_OUT_P8_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P1_OUT_P8_GET(val) ((((val) & PORT_P1_OUT_P8) >> 8) & 0x1) -+#define PORT_P1_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P8) | (((val) & 0x1) << 8)) -+/* Port 1 Pin # Output Value (7) */ -+#define PORT_P1_OUT_P7 (0x1 << 7) -+#define PORT_P1_OUT_P7_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P1_OUT_P7_GET(val) ((((val) & PORT_P1_OUT_P7) >> 7) & 0x1) -+#define PORT_P1_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P7) | (((val) & 0x1) << 7)) -+/* Port 1 Pin # Output Value (6) */ -+#define PORT_P1_OUT_P6 (0x1 << 6) -+#define PORT_P1_OUT_P6_VAL(val) (((val) & 0x1) << 6) -+#define PORT_P1_OUT_P6_GET(val) ((((val) & PORT_P1_OUT_P6) >> 6) & 0x1) -+#define PORT_P1_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P6) | (((val) & 0x1) << 6)) -+/* Port 1 Pin # Output Value (5) */ -+#define PORT_P1_OUT_P5 (0x1 << 5) -+#define PORT_P1_OUT_P5_VAL(val) (((val) & 0x1) << 5) -+#define PORT_P1_OUT_P5_GET(val) ((((val) & PORT_P1_OUT_P5) >> 5) & 0x1) -+#define PORT_P1_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P5) | (((val) & 0x1) << 5)) -+/* Port 1 Pin # Output Value (4) */ -+#define PORT_P1_OUT_P4 (0x1 << 4) -+#define PORT_P1_OUT_P4_VAL(val) (((val) & 0x1) << 4) -+#define PORT_P1_OUT_P4_GET(val) ((((val) & PORT_P1_OUT_P4) >> 4) & 0x1) -+#define PORT_P1_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P4) | (((val) & 0x1) << 4)) -+/* Port 1 Pin # Output Value (3) */ -+#define PORT_P1_OUT_P3 (0x1 << 3) -+#define PORT_P1_OUT_P3_VAL(val) (((val) & 0x1) << 3) -+#define PORT_P1_OUT_P3_GET(val) ((((val) & PORT_P1_OUT_P3) >> 3) & 0x1) -+#define PORT_P1_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P3) | (((val) & 0x1) << 3)) -+/* Port 1 Pin # Output Value (2) */ -+#define PORT_P1_OUT_P2 (0x1 << 2) -+#define PORT_P1_OUT_P2_VAL(val) (((val) & 0x1) << 2) -+#define PORT_P1_OUT_P2_GET(val) ((((val) & PORT_P1_OUT_P2) >> 2) & 0x1) -+#define PORT_P1_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P2) | (((val) & 0x1) << 2)) -+/* Port 1 Pin # Output Value (1) */ -+#define PORT_P1_OUT_P1 (0x1 << 1) -+#define PORT_P1_OUT_P1_VAL(val) (((val) & 0x1) << 1) -+#define PORT_P1_OUT_P1_GET(val) ((((val) & PORT_P1_OUT_P1) >> 1) & 0x1) -+#define PORT_P1_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P1) | (((val) & 0x1) << 1)) -+/* Port 1 Pin # Output Value (0) */ -+#define PORT_P1_OUT_P0 (0x1) -+#define PORT_P1_OUT_P0_VAL(val) (((val) & 0x1) << 0) -+#define PORT_P1_OUT_P0_GET(val) ((((val) & PORT_P1_OUT_P0) >> 0) & 0x1) -+#define PORT_P1_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P0) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Port 1 Data Input Register -+ ******************************************************************************/ -+ -+/* Port 1 Pin # Latched Input Value (19) */ -+#define PORT_P1_IN_P19 (0x1 << 19) -+#define PORT_P1_IN_P19_GET(val) ((((val) & PORT_P1_IN_P19) >> 19) & 0x1) -+/* Port 1 Pin # Latched Input Value (18) */ -+#define PORT_P1_IN_P18 (0x1 << 18) -+#define PORT_P1_IN_P18_GET(val) ((((val) & PORT_P1_IN_P18) >> 18) & 0x1) -+/* Port 1 Pin # Latched Input Value (17) */ -+#define PORT_P1_IN_P17 (0x1 << 17) -+#define PORT_P1_IN_P17_GET(val) ((((val) & PORT_P1_IN_P17) >> 17) & 0x1) -+/* Port 1 Pin # Latched Input Value (16) */ -+#define PORT_P1_IN_P16 (0x1 << 16) -+#define PORT_P1_IN_P16_GET(val) ((((val) & PORT_P1_IN_P16) >> 16) & 0x1) -+/* Port 1 Pin # Latched Input Value (15) */ -+#define PORT_P1_IN_P15 (0x1 << 15) -+#define PORT_P1_IN_P15_GET(val) ((((val) & PORT_P1_IN_P15) >> 15) & 0x1) -+/* Port 1 Pin # Latched Input Value (14) */ -+#define PORT_P1_IN_P14 (0x1 << 14) -+#define PORT_P1_IN_P14_GET(val) ((((val) & PORT_P1_IN_P14) >> 14) & 0x1) -+/* Port 1 Pin # Latched Input Value (13) */ -+#define PORT_P1_IN_P13 (0x1 << 13) -+#define PORT_P1_IN_P13_GET(val) ((((val) & PORT_P1_IN_P13) >> 13) & 0x1) -+/* Port 1 Pin # Latched Input Value (12) */ -+#define PORT_P1_IN_P12 (0x1 << 12) -+#define PORT_P1_IN_P12_GET(val) ((((val) & PORT_P1_IN_P12) >> 12) & 0x1) -+/* Port 1 Pin # Latched Input Value (11) */ -+#define PORT_P1_IN_P11 (0x1 << 11) -+#define PORT_P1_IN_P11_GET(val) ((((val) & PORT_P1_IN_P11) >> 11) & 0x1) -+/* Port 1 Pin # Latched Input Value (10) */ -+#define PORT_P1_IN_P10 (0x1 << 10) -+#define PORT_P1_IN_P10_GET(val) ((((val) & PORT_P1_IN_P10) >> 10) & 0x1) -+/* Port 1 Pin # Latched Input Value (9) */ -+#define PORT_P1_IN_P9 (0x1 << 9) -+#define PORT_P1_IN_P9_GET(val) ((((val) & PORT_P1_IN_P9) >> 9) & 0x1) -+/* Port 1 Pin # Latched Input Value (8) */ -+#define PORT_P1_IN_P8 (0x1 << 8) -+#define PORT_P1_IN_P8_GET(val) ((((val) & PORT_P1_IN_P8) >> 8) & 0x1) -+/* Port 1 Pin # Latched Input Value (7) */ -+#define PORT_P1_IN_P7 (0x1 << 7) -+#define PORT_P1_IN_P7_GET(val) ((((val) & PORT_P1_IN_P7) >> 7) & 0x1) -+/* Port 1 Pin # Latched Input Value (6) */ -+#define PORT_P1_IN_P6 (0x1 << 6) -+#define PORT_P1_IN_P6_GET(val) ((((val) & PORT_P1_IN_P6) >> 6) & 0x1) -+/* Port 1 Pin # Latched Input Value (5) */ -+#define PORT_P1_IN_P5 (0x1 << 5) -+#define PORT_P1_IN_P5_GET(val) ((((val) & PORT_P1_IN_P5) >> 5) & 0x1) -+/* Port 1 Pin # Latched Input Value (4) */ -+#define PORT_P1_IN_P4 (0x1 << 4) -+#define PORT_P1_IN_P4_GET(val) ((((val) & PORT_P1_IN_P4) >> 4) & 0x1) -+/* Port 1 Pin # Latched Input Value (3) */ -+#define PORT_P1_IN_P3 (0x1 << 3) -+#define PORT_P1_IN_P3_GET(val) ((((val) & PORT_P1_IN_P3) >> 3) & 0x1) -+/* Port 1 Pin # Latched Input Value (2) */ -+#define PORT_P1_IN_P2 (0x1 << 2) -+#define PORT_P1_IN_P2_GET(val) ((((val) & PORT_P1_IN_P2) >> 2) & 0x1) -+/* Port 1 Pin # Latched Input Value (1) */ -+#define PORT_P1_IN_P1 (0x1 << 1) -+#define PORT_P1_IN_P1_GET(val) ((((val) & PORT_P1_IN_P1) >> 1) & 0x1) -+/* Port 1 Pin # Latched Input Value (0) */ -+#define PORT_P1_IN_P0 (0x1) -+#define PORT_P1_IN_P0_GET(val) ((((val) & PORT_P1_IN_P0) >> 0) & 0x1) -+ -+/******************************************************************************* -+ * Port 1 Direction Register -+ ******************************************************************************/ -+ -+/* Port 1 Pin #Direction Control (19) */ -+#define PORT_P1_DIR_P19 (0x1 << 19) -+#define PORT_P1_DIR_P19_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P1_DIR_P19_GET(val) ((((val) & PORT_P1_DIR_P19) >> 19) & 0x1) -+#define PORT_P1_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P19) | (((val) & 0x1) << 19)) -+/* Port 1 Pin #Direction Control (18) */ -+#define PORT_P1_DIR_P18 (0x1 << 18) -+#define PORT_P1_DIR_P18_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P1_DIR_P18_GET(val) ((((val) & PORT_P1_DIR_P18) >> 18) & 0x1) -+#define PORT_P1_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P18) | (((val) & 0x1) << 18)) -+/* Port 1 Pin #Direction Control (17) */ -+#define PORT_P1_DIR_P17 (0x1 << 17) -+#define PORT_P1_DIR_P17_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P1_DIR_P17_GET(val) ((((val) & PORT_P1_DIR_P17) >> 17) & 0x1) -+#define PORT_P1_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P17) | (((val) & 0x1) << 17)) -+/* Port 1 Pin #Direction Control (16) */ -+#define PORT_P1_DIR_P16 (0x1 << 16) -+#define PORT_P1_DIR_P16_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P1_DIR_P16_GET(val) ((((val) & PORT_P1_DIR_P16) >> 16) & 0x1) -+#define PORT_P1_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P16) | (((val) & 0x1) << 16)) -+/* Port 1 Pin #Direction Control (15) */ -+#define PORT_P1_DIR_P15 (0x1 << 15) -+#define PORT_P1_DIR_P15_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P1_DIR_P15_GET(val) ((((val) & PORT_P1_DIR_P15) >> 15) & 0x1) -+#define PORT_P1_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P15) | (((val) & 0x1) << 15)) -+/* Port 1 Pin #Direction Control (14) */ -+#define PORT_P1_DIR_P14 (0x1 << 14) -+#define PORT_P1_DIR_P14_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P1_DIR_P14_GET(val) ((((val) & PORT_P1_DIR_P14) >> 14) & 0x1) -+#define PORT_P1_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P14) | (((val) & 0x1) << 14)) -+/* Port 1 Pin #Direction Control (13) */ -+#define PORT_P1_DIR_P13 (0x1 << 13) -+#define PORT_P1_DIR_P13_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P1_DIR_P13_GET(val) ((((val) & PORT_P1_DIR_P13) >> 13) & 0x1) -+#define PORT_P1_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P13) | (((val) & 0x1) << 13)) -+/* Port 1 Pin #Direction Control (12) */ -+#define PORT_P1_DIR_P12 (0x1 << 12) -+#define PORT_P1_DIR_P12_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P1_DIR_P12_GET(val) ((((val) & PORT_P1_DIR_P12) >> 12) & 0x1) -+#define PORT_P1_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P12) | (((val) & 0x1) << 12)) -+/* Port 1 Pin #Direction Control (11) */ -+#define PORT_P1_DIR_P11 (0x1 << 11) -+#define PORT_P1_DIR_P11_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P1_DIR_P11_GET(val) ((((val) & PORT_P1_DIR_P11) >> 11) & 0x1) -+#define PORT_P1_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P11) | (((val) & 0x1) << 11)) -+/* Port 1 Pin #Direction Control (10) */ -+#define PORT_P1_DIR_P10 (0x1 << 10) -+#define PORT_P1_DIR_P10_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P1_DIR_P10_GET(val) ((((val) & PORT_P1_DIR_P10) >> 10) & 0x1) -+#define PORT_P1_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P10) | (((val) & 0x1) << 10)) -+/* Port 1 Pin #Direction Control (9) */ -+#define PORT_P1_DIR_P9 (0x1 << 9) -+#define PORT_P1_DIR_P9_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P1_DIR_P9_GET(val) ((((val) & PORT_P1_DIR_P9) >> 9) & 0x1) -+#define PORT_P1_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P9) | (((val) & 0x1) << 9)) -+/* Port 1 Pin #Direction Control (8) */ -+#define PORT_P1_DIR_P8 (0x1 << 8) -+#define PORT_P1_DIR_P8_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P1_DIR_P8_GET(val) ((((val) & PORT_P1_DIR_P8) >> 8) & 0x1) -+#define PORT_P1_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P8) | (((val) & 0x1) << 8)) -+/* Port 1 Pin #Direction Control (7) */ -+#define PORT_P1_DIR_P7 (0x1 << 7) -+#define PORT_P1_DIR_P7_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P1_DIR_P7_GET(val) ((((val) & PORT_P1_DIR_P7) >> 7) & 0x1) -+#define PORT_P1_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P7) | (((val) & 0x1) << 7)) -+/* Port 1 Pin #Direction Control (6) */ -+#define PORT_P1_DIR_P6 (0x1 << 6) -+#define PORT_P1_DIR_P6_VAL(val) (((val) & 0x1) << 6) -+#define PORT_P1_DIR_P6_GET(val) ((((val) & PORT_P1_DIR_P6) >> 6) & 0x1) -+#define PORT_P1_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P6) | (((val) & 0x1) << 6)) -+/* Port 1 Pin #Direction Control (5) */ -+#define PORT_P1_DIR_P5 (0x1 << 5) -+#define PORT_P1_DIR_P5_VAL(val) (((val) & 0x1) << 5) -+#define PORT_P1_DIR_P5_GET(val) ((((val) & PORT_P1_DIR_P5) >> 5) & 0x1) -+#define PORT_P1_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P5) | (((val) & 0x1) << 5)) -+/* Port 1 Pin #Direction Control (4) */ -+#define PORT_P1_DIR_P4 (0x1 << 4) -+#define PORT_P1_DIR_P4_VAL(val) (((val) & 0x1) << 4) -+#define PORT_P1_DIR_P4_GET(val) ((((val) & PORT_P1_DIR_P4) >> 4) & 0x1) -+#define PORT_P1_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P4) | (((val) & 0x1) << 4)) -+/* Port 1 Pin #Direction Control (3) */ -+#define PORT_P1_DIR_P3 (0x1 << 3) -+#define PORT_P1_DIR_P3_VAL(val) (((val) & 0x1) << 3) -+#define PORT_P1_DIR_P3_GET(val) ((((val) & PORT_P1_DIR_P3) >> 3) & 0x1) -+#define PORT_P1_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P3) | (((val) & 0x1) << 3)) -+/* Port 1 Pin #Direction Control (2) */ -+#define PORT_P1_DIR_P2 (0x1 << 2) -+#define PORT_P1_DIR_P2_VAL(val) (((val) & 0x1) << 2) -+#define PORT_P1_DIR_P2_GET(val) ((((val) & PORT_P1_DIR_P2) >> 2) & 0x1) -+#define PORT_P1_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P2) | (((val) & 0x1) << 2)) -+/* Port 1 Pin #Direction Control (1) */ -+#define PORT_P1_DIR_P1 (0x1 << 1) -+#define PORT_P1_DIR_P1_VAL(val) (((val) & 0x1) << 1) -+#define PORT_P1_DIR_P1_GET(val) ((((val) & PORT_P1_DIR_P1) >> 1) & 0x1) -+#define PORT_P1_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P1) | (((val) & 0x1) << 1)) -+/* Port 1 Pin #Direction Control (0) */ -+#define PORT_P1_DIR_P0 (0x1) -+#define PORT_P1_DIR_P0_VAL(val) (((val) & 0x1) << 0) -+#define PORT_P1_DIR_P0_GET(val) ((((val) & PORT_P1_DIR_P0) >> 0) & 0x1) -+#define PORT_P1_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P0) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Port 1 Alternate Function Select Register 0 -+ ******************************************************************************/ -+ -+/* Alternate Function at Port 1 Bit # (19) */ -+#define PORT_P1_ALTSEL0_P19 (0x1 << 19) -+#define PORT_P1_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P1_ALTSEL0_P19_GET(val) ((((val) & PORT_P1_ALTSEL0_P19) >> 19) & 0x1) -+#define PORT_P1_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P19) | (((val) & 0x1) << 19)) -+/* Alternate Function at Port 1 Bit # (18) */ -+#define PORT_P1_ALTSEL0_P18 (0x1 << 18) -+#define PORT_P1_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P1_ALTSEL0_P18_GET(val) ((((val) & PORT_P1_ALTSEL0_P18) >> 18) & 0x1) -+#define PORT_P1_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P18) | (((val) & 0x1) << 18)) -+/* Alternate Function at Port 1 Bit # (17) */ -+#define PORT_P1_ALTSEL0_P17 (0x1 << 17) -+#define PORT_P1_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P1_ALTSEL0_P17_GET(val) ((((val) & PORT_P1_ALTSEL0_P17) >> 17) & 0x1) -+#define PORT_P1_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P17) | (((val) & 0x1) << 17)) -+/* Alternate Function at Port 1 Bit # (16) */ -+#define PORT_P1_ALTSEL0_P16 (0x1 << 16) -+#define PORT_P1_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P1_ALTSEL0_P16_GET(val) ((((val) & PORT_P1_ALTSEL0_P16) >> 16) & 0x1) -+#define PORT_P1_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P16) | (((val) & 0x1) << 16)) -+/* Alternate Function at Port 1 Bit # (15) */ -+#define PORT_P1_ALTSEL0_P15 (0x1 << 15) -+#define PORT_P1_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P1_ALTSEL0_P15_GET(val) ((((val) & PORT_P1_ALTSEL0_P15) >> 15) & 0x1) -+#define PORT_P1_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P15) | (((val) & 0x1) << 15)) -+/* Alternate Function at Port 1 Bit # (14) */ -+#define PORT_P1_ALTSEL0_P14 (0x1 << 14) -+#define PORT_P1_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P1_ALTSEL0_P14_GET(val) ((((val) & PORT_P1_ALTSEL0_P14) >> 14) & 0x1) -+#define PORT_P1_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P14) | (((val) & 0x1) << 14)) -+/* Alternate Function at Port 1 Bit # (13) */ -+#define PORT_P1_ALTSEL0_P13 (0x1 << 13) -+#define PORT_P1_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P1_ALTSEL0_P13_GET(val) ((((val) & PORT_P1_ALTSEL0_P13) >> 13) & 0x1) -+#define PORT_P1_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P13) | (((val) & 0x1) << 13)) -+/* Alternate Function at Port 1 Bit # (12) */ -+#define PORT_P1_ALTSEL0_P12 (0x1 << 12) -+#define PORT_P1_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P1_ALTSEL0_P12_GET(val) ((((val) & PORT_P1_ALTSEL0_P12) >> 12) & 0x1) -+#define PORT_P1_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P12) | (((val) & 0x1) << 12)) -+/* Alternate Function at Port 1 Bit # (11) */ -+#define PORT_P1_ALTSEL0_P11 (0x1 << 11) -+#define PORT_P1_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P1_ALTSEL0_P11_GET(val) ((((val) & PORT_P1_ALTSEL0_P11) >> 11) & 0x1) -+#define PORT_P1_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P11) | (((val) & 0x1) << 11)) -+/* Alternate Function at Port 1 Bit # (10) */ -+#define PORT_P1_ALTSEL0_P10 (0x1 << 10) -+#define PORT_P1_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P1_ALTSEL0_P10_GET(val) ((((val) & PORT_P1_ALTSEL0_P10) >> 10) & 0x1) -+#define PORT_P1_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P10) | (((val) & 0x1) << 10)) -+/* Alternate Function at Port 1 Bit # (9) */ -+#define PORT_P1_ALTSEL0_P9 (0x1 << 9) -+#define PORT_P1_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P1_ALTSEL0_P9_GET(val) ((((val) & PORT_P1_ALTSEL0_P9) >> 9) & 0x1) -+#define PORT_P1_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P9) | (((val) & 0x1) << 9)) -+/* Alternate Function at Port 1 Bit # (8) */ -+#define PORT_P1_ALTSEL0_P8 (0x1 << 8) -+#define PORT_P1_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P1_ALTSEL0_P8_GET(val) ((((val) & PORT_P1_ALTSEL0_P8) >> 8) & 0x1) -+#define PORT_P1_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P8) | (((val) & 0x1) << 8)) -+/* Alternate Function at Port 1 Bit # (7) */ -+#define PORT_P1_ALTSEL0_P7 (0x1 << 7) -+#define PORT_P1_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P1_ALTSEL0_P7_GET(val) ((((val) & PORT_P1_ALTSEL0_P7) >> 7) & 0x1) -+#define PORT_P1_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P7) | (((val) & 0x1) << 7)) -+/* Alternate Function at Port 1 Bit # (6) */ -+#define PORT_P1_ALTSEL0_P6 (0x1 << 6) -+#define PORT_P1_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) -+#define PORT_P1_ALTSEL0_P6_GET(val) ((((val) & PORT_P1_ALTSEL0_P6) >> 6) & 0x1) -+#define PORT_P1_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P6) | (((val) & 0x1) << 6)) -+/* Alternate Function at Port 1 Bit # (5) */ -+#define PORT_P1_ALTSEL0_P5 (0x1 << 5) -+#define PORT_P1_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) -+#define PORT_P1_ALTSEL0_P5_GET(val) ((((val) & PORT_P1_ALTSEL0_P5) >> 5) & 0x1) -+#define PORT_P1_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P5) | (((val) & 0x1) << 5)) -+/* Alternate Function at Port 1 Bit # (4) */ -+#define PORT_P1_ALTSEL0_P4 (0x1 << 4) -+#define PORT_P1_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) -+#define PORT_P1_ALTSEL0_P4_GET(val) ((((val) & PORT_P1_ALTSEL0_P4) >> 4) & 0x1) -+#define PORT_P1_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P4) | (((val) & 0x1) << 4)) -+/* Alternate Function at Port 1 Bit # (3) */ -+#define PORT_P1_ALTSEL0_P3 (0x1 << 3) -+#define PORT_P1_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) -+#define PORT_P1_ALTSEL0_P3_GET(val) ((((val) & PORT_P1_ALTSEL0_P3) >> 3) & 0x1) -+#define PORT_P1_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P3) | (((val) & 0x1) << 3)) -+/* Alternate Function at Port 1 Bit # (2) */ -+#define PORT_P1_ALTSEL0_P2 (0x1 << 2) -+#define PORT_P1_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) -+#define PORT_P1_ALTSEL0_P2_GET(val) ((((val) & PORT_P1_ALTSEL0_P2) >> 2) & 0x1) -+#define PORT_P1_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P2) | (((val) & 0x1) << 2)) -+/* Alternate Function at Port 1 Bit # (1) */ -+#define PORT_P1_ALTSEL0_P1 (0x1 << 1) -+#define PORT_P1_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) -+#define PORT_P1_ALTSEL0_P1_GET(val) ((((val) & PORT_P1_ALTSEL0_P1) >> 1) & 0x1) -+#define PORT_P1_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P1) | (((val) & 0x1) << 1)) -+/* Alternate Function at Port 1 Bit # (0) */ -+#define PORT_P1_ALTSEL0_P0 (0x1) -+#define PORT_P1_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) -+#define PORT_P1_ALTSEL0_P0_GET(val) ((((val) & PORT_P1_ALTSEL0_P0) >> 0) & 0x1) -+#define PORT_P1_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P0) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Port 1 Pull Up Device Enable Register -+ ******************************************************************************/ -+ -+/* Pull Up Device Enable at Port 1 Bit # (19) */ -+#define PORT_P1_PUEN_P19 (0x1 << 19) -+#define PORT_P1_PUEN_P19_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P1_PUEN_P19_GET(val) ((((val) & PORT_P1_PUEN_P19) >> 19) & 0x1) -+#define PORT_P1_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P19) | (((val) & 0x1) << 19)) -+/* Pull Up Device Enable at Port 1 Bit # (18) */ -+#define PORT_P1_PUEN_P18 (0x1 << 18) -+#define PORT_P1_PUEN_P18_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P1_PUEN_P18_GET(val) ((((val) & PORT_P1_PUEN_P18) >> 18) & 0x1) -+#define PORT_P1_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P18) | (((val) & 0x1) << 18)) -+/* Pull Up Device Enable at Port 1 Bit # (17) */ -+#define PORT_P1_PUEN_P17 (0x1 << 17) -+#define PORT_P1_PUEN_P17_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P1_PUEN_P17_GET(val) ((((val) & PORT_P1_PUEN_P17) >> 17) & 0x1) -+#define PORT_P1_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P17) | (((val) & 0x1) << 17)) -+/* Pull Up Device Enable at Port 1 Bit # (16) */ -+#define PORT_P1_PUEN_P16 (0x1 << 16) -+#define PORT_P1_PUEN_P16_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P1_PUEN_P16_GET(val) ((((val) & PORT_P1_PUEN_P16) >> 16) & 0x1) -+#define PORT_P1_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P16) | (((val) & 0x1) << 16)) -+/* Pull Up Device Enable at Port 1 Bit # (15) */ -+#define PORT_P1_PUEN_P15 (0x1 << 15) -+#define PORT_P1_PUEN_P15_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P1_PUEN_P15_GET(val) ((((val) & PORT_P1_PUEN_P15) >> 15) & 0x1) -+#define PORT_P1_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P15) | (((val) & 0x1) << 15)) -+/* Pull Up Device Enable at Port 1 Bit # (14) */ -+#define PORT_P1_PUEN_P14 (0x1 << 14) -+#define PORT_P1_PUEN_P14_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P1_PUEN_P14_GET(val) ((((val) & PORT_P1_PUEN_P14) >> 14) & 0x1) -+#define PORT_P1_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P14) | (((val) & 0x1) << 14)) -+/* Pull Up Device Enable at Port 1 Bit # (13) */ -+#define PORT_P1_PUEN_P13 (0x1 << 13) -+#define PORT_P1_PUEN_P13_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P1_PUEN_P13_GET(val) ((((val) & PORT_P1_PUEN_P13) >> 13) & 0x1) -+#define PORT_P1_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P13) | (((val) & 0x1) << 13)) -+/* Pull Up Device Enable at Port 1 Bit # (12) */ -+#define PORT_P1_PUEN_P12 (0x1 << 12) -+#define PORT_P1_PUEN_P12_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P1_PUEN_P12_GET(val) ((((val) & PORT_P1_PUEN_P12) >> 12) & 0x1) -+#define PORT_P1_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P12) | (((val) & 0x1) << 12)) -+/* Pull Up Device Enable at Port 1 Bit # (11) */ -+#define PORT_P1_PUEN_P11 (0x1 << 11) -+#define PORT_P1_PUEN_P11_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P1_PUEN_P11_GET(val) ((((val) & PORT_P1_PUEN_P11) >> 11) & 0x1) -+#define PORT_P1_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P11) | (((val) & 0x1) << 11)) -+/* Pull Up Device Enable at Port 1 Bit # (10) */ -+#define PORT_P1_PUEN_P10 (0x1 << 10) -+#define PORT_P1_PUEN_P10_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P1_PUEN_P10_GET(val) ((((val) & PORT_P1_PUEN_P10) >> 10) & 0x1) -+#define PORT_P1_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P10) | (((val) & 0x1) << 10)) -+/* Pull Up Device Enable at Port 1 Bit # (9) */ -+#define PORT_P1_PUEN_P9 (0x1 << 9) -+#define PORT_P1_PUEN_P9_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P1_PUEN_P9_GET(val) ((((val) & PORT_P1_PUEN_P9) >> 9) & 0x1) -+#define PORT_P1_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P9) | (((val) & 0x1) << 9)) -+/* Pull Up Device Enable at Port 1 Bit # (8) */ -+#define PORT_P1_PUEN_P8 (0x1 << 8) -+#define PORT_P1_PUEN_P8_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P1_PUEN_P8_GET(val) ((((val) & PORT_P1_PUEN_P8) >> 8) & 0x1) -+#define PORT_P1_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P8) | (((val) & 0x1) << 8)) -+/* Pull Up Device Enable at Port 1 Bit # (7) */ -+#define PORT_P1_PUEN_P7 (0x1 << 7) -+#define PORT_P1_PUEN_P7_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P1_PUEN_P7_GET(val) ((((val) & PORT_P1_PUEN_P7) >> 7) & 0x1) -+#define PORT_P1_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P7) | (((val) & 0x1) << 7)) -+/* Pull Up Device Enable at Port 1 Bit # (6) */ -+#define PORT_P1_PUEN_P6 (0x1 << 6) -+#define PORT_P1_PUEN_P6_VAL(val) (((val) & 0x1) << 6) -+#define PORT_P1_PUEN_P6_GET(val) ((((val) & PORT_P1_PUEN_P6) >> 6) & 0x1) -+#define PORT_P1_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P6) | (((val) & 0x1) << 6)) -+/* Pull Up Device Enable at Port 1 Bit # (5) */ -+#define PORT_P1_PUEN_P5 (0x1 << 5) -+#define PORT_P1_PUEN_P5_VAL(val) (((val) & 0x1) << 5) -+#define PORT_P1_PUEN_P5_GET(val) ((((val) & PORT_P1_PUEN_P5) >> 5) & 0x1) -+#define PORT_P1_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P5) | (((val) & 0x1) << 5)) -+/* Pull Up Device Enable at Port 1 Bit # (4) */ -+#define PORT_P1_PUEN_P4 (0x1 << 4) -+#define PORT_P1_PUEN_P4_VAL(val) (((val) & 0x1) << 4) -+#define PORT_P1_PUEN_P4_GET(val) ((((val) & PORT_P1_PUEN_P4) >> 4) & 0x1) -+#define PORT_P1_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P4) | (((val) & 0x1) << 4)) -+/* Pull Up Device Enable at Port 1 Bit # (3) */ -+#define PORT_P1_PUEN_P3 (0x1 << 3) -+#define PORT_P1_PUEN_P3_VAL(val) (((val) & 0x1) << 3) -+#define PORT_P1_PUEN_P3_GET(val) ((((val) & PORT_P1_PUEN_P3) >> 3) & 0x1) -+#define PORT_P1_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P3) | (((val) & 0x1) << 3)) -+/* Pull Up Device Enable at Port 1 Bit # (2) */ -+#define PORT_P1_PUEN_P2 (0x1 << 2) -+#define PORT_P1_PUEN_P2_VAL(val) (((val) & 0x1) << 2) -+#define PORT_P1_PUEN_P2_GET(val) ((((val) & PORT_P1_PUEN_P2) >> 2) & 0x1) -+#define PORT_P1_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P2) | (((val) & 0x1) << 2)) -+/* Pull Up Device Enable at Port 1 Bit # (1) */ -+#define PORT_P1_PUEN_P1 (0x1 << 1) -+#define PORT_P1_PUEN_P1_VAL(val) (((val) & 0x1) << 1) -+#define PORT_P1_PUEN_P1_GET(val) ((((val) & PORT_P1_PUEN_P1) >> 1) & 0x1) -+#define PORT_P1_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P1) | (((val) & 0x1) << 1)) -+/* Pull Up Device Enable at Port 1 Bit # (0) */ -+#define PORT_P1_PUEN_P0 (0x1) -+#define PORT_P1_PUEN_P0_VAL(val) (((val) & 0x1) << 0) -+#define PORT_P1_PUEN_P0_GET(val) ((((val) & PORT_P1_PUEN_P0) >> 0) & 0x1) -+#define PORT_P1_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P0) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * External Interrupt Control Register 0 -+ ******************************************************************************/ -+ -+/* Type of Level or Edge Detection of EXINT15 (19) */ -+#define PORT_P1_EXINTCR0_EXINT15 (0x1 << 19) -+#define PORT_P1_EXINTCR0_EXINT15_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P1_EXINTCR0_EXINT15_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT15) >> 19) & 0x1) -+#define PORT_P1_EXINTCR0_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT15) | (((val) & 0x1) << 19)) -+/* Type of Level or Edge Detection of EXINT11 (18) */ -+#define PORT_P1_EXINTCR0_EXINT11 (0x1 << 18) -+#define PORT_P1_EXINTCR0_EXINT11_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P1_EXINTCR0_EXINT11_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT11) >> 18) & 0x1) -+#define PORT_P1_EXINTCR0_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT11) | (((val) & 0x1) << 18)) -+/* Type of Level or Edge Detection of EXINT12 (17) */ -+#define PORT_P1_EXINTCR0_EXINT12 (0x1 << 17) -+#define PORT_P1_EXINTCR0_EXINT12_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P1_EXINTCR0_EXINT12_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT12) >> 17) & 0x1) -+#define PORT_P1_EXINTCR0_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT12) | (((val) & 0x1) << 17)) -+/* Type of Level or Edge Detection of EXINT13 (16) */ -+#define PORT_P1_EXINTCR0_EXINT13 (0x1 << 16) -+#define PORT_P1_EXINTCR0_EXINT13_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P1_EXINTCR0_EXINT13_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT13) >> 16) & 0x1) -+#define PORT_P1_EXINTCR0_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT13) | (((val) & 0x1) << 16)) -+/* Type of Level or Edge Detection of EXINT14 (15) */ -+#define PORT_P1_EXINTCR0_EXINT14 (0x1 << 15) -+#define PORT_P1_EXINTCR0_EXINT14_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P1_EXINTCR0_EXINT14_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT14) >> 15) & 0x1) -+#define PORT_P1_EXINTCR0_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT14) | (((val) & 0x1) << 15)) -+ -+/******************************************************************************* -+ * External Interrupt Control Register 1 -+ ******************************************************************************/ -+ -+/* Type of Level or Edge Detection of EXINT15 (19) */ -+#define PORT_P1_EXINTCR1_EXINT15 (0x1 << 19) -+#define PORT_P1_EXINTCR1_EXINT15_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P1_EXINTCR1_EXINT15_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT15) >> 19) & 0x1) -+#define PORT_P1_EXINTCR1_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT15) | (((val) & 0x1) << 19)) -+/* Type of Level or Edge Detection of EXINT11 (18) */ -+#define PORT_P1_EXINTCR1_EXINT11 (0x1 << 18) -+#define PORT_P1_EXINTCR1_EXINT11_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P1_EXINTCR1_EXINT11_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT11) >> 18) & 0x1) -+#define PORT_P1_EXINTCR1_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT11) | (((val) & 0x1) << 18)) -+/* Type of Level or Edge Detection of EXINT12 (17) */ -+#define PORT_P1_EXINTCR1_EXINT12 (0x1 << 17) -+#define PORT_P1_EXINTCR1_EXINT12_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P1_EXINTCR1_EXINT12_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT12) >> 17) & 0x1) -+#define PORT_P1_EXINTCR1_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT12) | (((val) & 0x1) << 17)) -+/* Type of Level or Edge Detection of EXINT13 (16) */ -+#define PORT_P1_EXINTCR1_EXINT13 (0x1 << 16) -+#define PORT_P1_EXINTCR1_EXINT13_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P1_EXINTCR1_EXINT13_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT13) >> 16) & 0x1) -+#define PORT_P1_EXINTCR1_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT13) | (((val) & 0x1) << 16)) -+/* Type of Level or Edge Detection of EXINT14 (15) */ -+#define PORT_P1_EXINTCR1_EXINT14 (0x1 << 15) -+#define PORT_P1_EXINTCR1_EXINT14_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P1_EXINTCR1_EXINT14_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT14) >> 15) & 0x1) -+#define PORT_P1_EXINTCR1_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT14) | (((val) & 0x1) << 15)) -+ -+/******************************************************************************* -+ * P1_IRNEN Register -+ ******************************************************************************/ -+ -+/* EXINT15 Interrupt Request Enable (19) */ -+#define PORT_P1_IRNEN_EXINT15 (0x1 << 19) -+#define PORT_P1_IRNEN_EXINT15_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P1_IRNEN_EXINT15_GET(val) ((((val) & PORT_P1_IRNEN_EXINT15) >> 19) & 0x1) -+#define PORT_P1_IRNEN_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT15) | (((val) & 0x1) << 19)) -+/* EXINT11 Interrupt Request Enable (18) */ -+#define PORT_P1_IRNEN_EXINT11 (0x1 << 18) -+#define PORT_P1_IRNEN_EXINT11_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P1_IRNEN_EXINT11_GET(val) ((((val) & PORT_P1_IRNEN_EXINT11) >> 18) & 0x1) -+#define PORT_P1_IRNEN_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT11) | (((val) & 0x1) << 18)) -+/* EXINT12 Interrupt Request Enable (17) */ -+#define PORT_P1_IRNEN_EXINT12 (0x1 << 17) -+#define PORT_P1_IRNEN_EXINT12_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P1_IRNEN_EXINT12_GET(val) ((((val) & PORT_P1_IRNEN_EXINT12) >> 17) & 0x1) -+#define PORT_P1_IRNEN_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT12) | (((val) & 0x1) << 17)) -+/* EXINT13 Interrupt Request Enable (16) */ -+#define PORT_P1_IRNEN_EXINT13 (0x1 << 16) -+#define PORT_P1_IRNEN_EXINT13_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P1_IRNEN_EXINT13_GET(val) ((((val) & PORT_P1_IRNEN_EXINT13) >> 16) & 0x1) -+#define PORT_P1_IRNEN_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT13) | (((val) & 0x1) << 16)) -+/* EXINT14 Interrupt Request Enable (15) */ -+#define PORT_P1_IRNEN_EXINT14 (0x1 << 15) -+#define PORT_P1_IRNEN_EXINT14_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P1_IRNEN_EXINT14_GET(val) ((((val) & PORT_P1_IRNEN_EXINT14) >> 15) & 0x1) -+#define PORT_P1_IRNEN_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT14) | (((val) & 0x1) << 15)) -+ -+/******************************************************************************* -+ * P1_IRNICR Register -+ ******************************************************************************/ -+ -+/* EXINT15 Interrupt Request (19) */ -+#define PORT_P1_IRNICR_EXINT15 (0x1 << 19) -+#define PORT_P1_IRNICR_EXINT15_GET(val) ((((val) & PORT_P1_IRNICR_EXINT15) >> 19) & 0x1) -+/* EXINT11 Interrupt Request (18) */ -+#define PORT_P1_IRNICR_EXINT11 (0x1 << 18) -+#define PORT_P1_IRNICR_EXINT11_GET(val) ((((val) & PORT_P1_IRNICR_EXINT11) >> 18) & 0x1) -+/* EXINT12 Interrupt Request (17) */ -+#define PORT_P1_IRNICR_EXINT12 (0x1 << 17) -+#define PORT_P1_IRNICR_EXINT12_GET(val) ((((val) & PORT_P1_IRNICR_EXINT12) >> 17) & 0x1) -+/* EXINT13 Interrupt Request (16) */ -+#define PORT_P1_IRNICR_EXINT13 (0x1 << 16) -+#define PORT_P1_IRNICR_EXINT13_GET(val) ((((val) & PORT_P1_IRNICR_EXINT13) >> 16) & 0x1) -+/* EXINT14 Interrupt Request (15) */ -+#define PORT_P1_IRNICR_EXINT14 (0x1 << 15) -+#define PORT_P1_IRNICR_EXINT14_GET(val) ((((val) & PORT_P1_IRNICR_EXINT14) >> 15) & 0x1) -+ -+/******************************************************************************* -+ * P1_IRNCR Register -+ ******************************************************************************/ -+ -+/* EXINT15 Interrupt Request (19) */ -+#define PORT_P1_IRNCR_EXINT15 (0x1 << 19) -+#define PORT_P1_IRNCR_EXINT15_GET(val) ((((val) & PORT_P1_IRNCR_EXINT15) >> 19) & 0x1) -+/* EXINT11 Interrupt Request (18) */ -+#define PORT_P1_IRNCR_EXINT11 (0x1 << 18) -+#define PORT_P1_IRNCR_EXINT11_GET(val) ((((val) & PORT_P1_IRNCR_EXINT11) >> 18) & 0x1) -+/* EXINT12 Interrupt Request (17) */ -+#define PORT_P1_IRNCR_EXINT12 (0x1 << 17) -+#define PORT_P1_IRNCR_EXINT12_GET(val) ((((val) & PORT_P1_IRNCR_EXINT12) >> 17) & 0x1) -+/* EXINT13 Interrupt Request (16) */ -+#define PORT_P1_IRNCR_EXINT13 (0x1 << 16) -+#define PORT_P1_IRNCR_EXINT13_GET(val) ((((val) & PORT_P1_IRNCR_EXINT13) >> 16) & 0x1) -+/* EXINT14 Interrupt Request (15) */ -+#define PORT_P1_IRNCR_EXINT14 (0x1 << 15) -+#define PORT_P1_IRNCR_EXINT14_GET(val) ((((val) & PORT_P1_IRNCR_EXINT14) >> 15) & 0x1) -+ -+/******************************************************************************* -+ * P1 External Event Detection Configuration Register -+ ******************************************************************************/ -+ -+/* EXINT15 configured for Edge or Level Detection (19) */ -+#define PORT_P1_IRNCFG_EXINT15 (0x1 << 19) -+#define PORT_P1_IRNCFG_EXINT15_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P1_IRNCFG_EXINT15_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT15) >> 19) & 0x1) -+#define PORT_P1_IRNCFG_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT15) | (((val) & 0x1) << 19)) -+/* EXINT11 configured for Edge or Level Detection (18) */ -+#define PORT_P1_IRNCFG_EXINT11 (0x1 << 18) -+#define PORT_P1_IRNCFG_EXINT11_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P1_IRNCFG_EXINT11_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT11) >> 18) & 0x1) -+#define PORT_P1_IRNCFG_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT11) | (((val) & 0x1) << 18)) -+/* EXINT12 configured for Edge or Level Detection (17) */ -+#define PORT_P1_IRNCFG_EXINT12 (0x1 << 17) -+#define PORT_P1_IRNCFG_EXINT12_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P1_IRNCFG_EXINT12_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT12) >> 17) & 0x1) -+#define PORT_P1_IRNCFG_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT12) | (((val) & 0x1) << 17)) -+/* EXINT13 configured for Edge or Level Detection (16) */ -+#define PORT_P1_IRNCFG_EXINT13 (0x1 << 16) -+#define PORT_P1_IRNCFG_EXINT13_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P1_IRNCFG_EXINT13_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT13) >> 16) & 0x1) -+#define PORT_P1_IRNCFG_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT13) | (((val) & 0x1) << 16)) -+/* EXINT14 configured for Edge or Level Detection (15) */ -+#define PORT_P1_IRNCFG_EXINT14 (0x1 << 15) -+#define PORT_P1_IRNCFG_EXINT14_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P1_IRNCFG_EXINT14_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT14) >> 15) & 0x1) -+#define PORT_P1_IRNCFG_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT14) | (((val) & 0x1) << 15)) -+ -+/******************************************************************************* -+ * P1_IRNENSET Register -+ ******************************************************************************/ -+ -+/* Set Interrupt Node Enable Flag EXINT15 (19) */ -+#define PORT_P1_IRNENSET_EXINT15 (0x1 << 19) -+#define PORT_P1_IRNENSET_EXINT15_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P1_IRNENSET_EXINT15_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT15) | (val) & 1) << 19) -+/* Set Interrupt Node Enable Flag EXINT11 (18) */ -+#define PORT_P1_IRNENSET_EXINT11 (0x1 << 18) -+#define PORT_P1_IRNENSET_EXINT11_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P1_IRNENSET_EXINT11_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT11) | (val) & 1) << 18) -+/* Set Interrupt Node Enable Flag EXINT12 (17) */ -+#define PORT_P1_IRNENSET_EXINT12 (0x1 << 17) -+#define PORT_P1_IRNENSET_EXINT12_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P1_IRNENSET_EXINT12_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT12) | (val) & 1) << 17) -+/* Set Interrupt Node Enable Flag EXINT13 (16) */ -+#define PORT_P1_IRNENSET_EXINT13 (0x1 << 16) -+#define PORT_P1_IRNENSET_EXINT13_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P1_IRNENSET_EXINT13_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT13) | (val) & 1) << 16) -+/* Set Interrupt Node Enable Flag EXINT14 (15) */ -+#define PORT_P1_IRNENSET_EXINT14 (0x1 << 15) -+#define PORT_P1_IRNENSET_EXINT14_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P1_IRNENSET_EXINT14_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT14) | (val) & 1) << 15) -+ -+/******************************************************************************* -+ * P1_IRNENCLR Register -+ ******************************************************************************/ -+ -+/* Clear Interrupt Node Enable Flag EXINT15 (19) */ -+#define PORT_P1_IRNENCLR_EXINT15 (0x1 << 19) -+#define PORT_P1_IRNENCLR_EXINT15_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P1_IRNENCLR_EXINT15_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT15) | (val) & 1) << 19) -+/* Clear Interrupt Node Enable Flag EXINT11 (18) */ -+#define PORT_P1_IRNENCLR_EXINT11 (0x1 << 18) -+#define PORT_P1_IRNENCLR_EXINT11_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P1_IRNENCLR_EXINT11_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT11) | (val) & 1) << 18) -+/* Clear Interrupt Node Enable Flag EXINT12 (17) */ -+#define PORT_P1_IRNENCLR_EXINT12 (0x1 << 17) -+#define PORT_P1_IRNENCLR_EXINT12_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P1_IRNENCLR_EXINT12_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT12) | (val) & 1) << 17) -+/* Clear Interrupt Node Enable Flag EXINT13 (16) */ -+#define PORT_P1_IRNENCLR_EXINT13 (0x1 << 16) -+#define PORT_P1_IRNENCLR_EXINT13_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P1_IRNENCLR_EXINT13_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT13) | (val) & 1) << 16) -+/* Clear Interrupt Node Enable Flag EXINT14 (15) */ -+#define PORT_P1_IRNENCLR_EXINT14 (0x1 << 15) -+#define PORT_P1_IRNENCLR_EXINT14_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P1_IRNENCLR_EXINT14_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT14) | (val) & 1) << 15) -+ -+/******************************************************************************* -+ * Port 2 Data Output Register -+ ******************************************************************************/ -+ -+/* Port 2 Pin # Output Value (19) */ -+#define PORT_P2_OUT_P19 (0x1 << 19) -+#define PORT_P2_OUT_P19_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P2_OUT_P19_GET(val) ((((val) & PORT_P2_OUT_P19) >> 19) & 0x1) -+#define PORT_P2_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P19) | (((val) & 0x1) << 19)) -+/* Port 2 Pin # Output Value (18) */ -+#define PORT_P2_OUT_P18 (0x1 << 18) -+#define PORT_P2_OUT_P18_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P2_OUT_P18_GET(val) ((((val) & PORT_P2_OUT_P18) >> 18) & 0x1) -+#define PORT_P2_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P18) | (((val) & 0x1) << 18)) -+/* Port 2 Pin # Output Value (17) */ -+#define PORT_P2_OUT_P17 (0x1 << 17) -+#define PORT_P2_OUT_P17_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P2_OUT_P17_GET(val) ((((val) & PORT_P2_OUT_P17) >> 17) & 0x1) -+#define PORT_P2_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P17) | (((val) & 0x1) << 17)) -+/* Port 2 Pin # Output Value (16) */ -+#define PORT_P2_OUT_P16 (0x1 << 16) -+#define PORT_P2_OUT_P16_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P2_OUT_P16_GET(val) ((((val) & PORT_P2_OUT_P16) >> 16) & 0x1) -+#define PORT_P2_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P16) | (((val) & 0x1) << 16)) -+/* Port 2 Pin # Output Value (15) */ -+#define PORT_P2_OUT_P15 (0x1 << 15) -+#define PORT_P2_OUT_P15_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P2_OUT_P15_GET(val) ((((val) & PORT_P2_OUT_P15) >> 15) & 0x1) -+#define PORT_P2_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P15) | (((val) & 0x1) << 15)) -+/* Port 2 Pin # Output Value (14) */ -+#define PORT_P2_OUT_P14 (0x1 << 14) -+#define PORT_P2_OUT_P14_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P2_OUT_P14_GET(val) ((((val) & PORT_P2_OUT_P14) >> 14) & 0x1) -+#define PORT_P2_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P14) | (((val) & 0x1) << 14)) -+/* Port 2 Pin # Output Value (13) */ -+#define PORT_P2_OUT_P13 (0x1 << 13) -+#define PORT_P2_OUT_P13_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P2_OUT_P13_GET(val) ((((val) & PORT_P2_OUT_P13) >> 13) & 0x1) -+#define PORT_P2_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P13) | (((val) & 0x1) << 13)) -+/* Port 2 Pin # Output Value (12) */ -+#define PORT_P2_OUT_P12 (0x1 << 12) -+#define PORT_P2_OUT_P12_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P2_OUT_P12_GET(val) ((((val) & PORT_P2_OUT_P12) >> 12) & 0x1) -+#define PORT_P2_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P12) | (((val) & 0x1) << 12)) -+/* Port 2 Pin # Output Value (11) */ -+#define PORT_P2_OUT_P11 (0x1 << 11) -+#define PORT_P2_OUT_P11_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P2_OUT_P11_GET(val) ((((val) & PORT_P2_OUT_P11) >> 11) & 0x1) -+#define PORT_P2_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P11) | (((val) & 0x1) << 11)) -+/* Port 2 Pin # Output Value (10) */ -+#define PORT_P2_OUT_P10 (0x1 << 10) -+#define PORT_P2_OUT_P10_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P2_OUT_P10_GET(val) ((((val) & PORT_P2_OUT_P10) >> 10) & 0x1) -+#define PORT_P2_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P10) | (((val) & 0x1) << 10)) -+/* Port 2 Pin # Output Value (9) */ -+#define PORT_P2_OUT_P9 (0x1 << 9) -+#define PORT_P2_OUT_P9_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P2_OUT_P9_GET(val) ((((val) & PORT_P2_OUT_P9) >> 9) & 0x1) -+#define PORT_P2_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P9) | (((val) & 0x1) << 9)) -+/* Port 2 Pin # Output Value (8) */ -+#define PORT_P2_OUT_P8 (0x1 << 8) -+#define PORT_P2_OUT_P8_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P2_OUT_P8_GET(val) ((((val) & PORT_P2_OUT_P8) >> 8) & 0x1) -+#define PORT_P2_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P8) | (((val) & 0x1) << 8)) -+/* Port 2 Pin # Output Value (7) */ -+#define PORT_P2_OUT_P7 (0x1 << 7) -+#define PORT_P2_OUT_P7_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P2_OUT_P7_GET(val) ((((val) & PORT_P2_OUT_P7) >> 7) & 0x1) -+#define PORT_P2_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P7) | (((val) & 0x1) << 7)) -+/* Port 2 Pin # Output Value (6) */ -+#define PORT_P2_OUT_P6 (0x1 << 6) -+#define PORT_P2_OUT_P6_VAL(val) (((val) & 0x1) << 6) -+#define PORT_P2_OUT_P6_GET(val) ((((val) & PORT_P2_OUT_P6) >> 6) & 0x1) -+#define PORT_P2_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P6) | (((val) & 0x1) << 6)) -+/* Port 2 Pin # Output Value (5) */ -+#define PORT_P2_OUT_P5 (0x1 << 5) -+#define PORT_P2_OUT_P5_VAL(val) (((val) & 0x1) << 5) -+#define PORT_P2_OUT_P5_GET(val) ((((val) & PORT_P2_OUT_P5) >> 5) & 0x1) -+#define PORT_P2_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P5) | (((val) & 0x1) << 5)) -+/* Port 2 Pin # Output Value (4) */ -+#define PORT_P2_OUT_P4 (0x1 << 4) -+#define PORT_P2_OUT_P4_VAL(val) (((val) & 0x1) << 4) -+#define PORT_P2_OUT_P4_GET(val) ((((val) & PORT_P2_OUT_P4) >> 4) & 0x1) -+#define PORT_P2_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P4) | (((val) & 0x1) << 4)) -+/* Port 2 Pin # Output Value (3) */ -+#define PORT_P2_OUT_P3 (0x1 << 3) -+#define PORT_P2_OUT_P3_VAL(val) (((val) & 0x1) << 3) -+#define PORT_P2_OUT_P3_GET(val) ((((val) & PORT_P2_OUT_P3) >> 3) & 0x1) -+#define PORT_P2_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P3) | (((val) & 0x1) << 3)) -+/* Port 2 Pin # Output Value (2) */ -+#define PORT_P2_OUT_P2 (0x1 << 2) -+#define PORT_P2_OUT_P2_VAL(val) (((val) & 0x1) << 2) -+#define PORT_P2_OUT_P2_GET(val) ((((val) & PORT_P2_OUT_P2) >> 2) & 0x1) -+#define PORT_P2_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P2) | (((val) & 0x1) << 2)) -+/* Port 2 Pin # Output Value (1) */ -+#define PORT_P2_OUT_P1 (0x1 << 1) -+#define PORT_P2_OUT_P1_VAL(val) (((val) & 0x1) << 1) -+#define PORT_P2_OUT_P1_GET(val) ((((val) & PORT_P2_OUT_P1) >> 1) & 0x1) -+#define PORT_P2_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P1) | (((val) & 0x1) << 1)) -+/* Port 2 Pin # Output Value (0) */ -+#define PORT_P2_OUT_P0 (0x1) -+#define PORT_P2_OUT_P0_VAL(val) (((val) & 0x1) << 0) -+#define PORT_P2_OUT_P0_GET(val) ((((val) & PORT_P2_OUT_P0) >> 0) & 0x1) -+#define PORT_P2_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P0) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Port 2 Data Input Register -+ ******************************************************************************/ -+ -+/* Port 2 Pin # Latched Input Value (19) */ -+#define PORT_P2_IN_P19 (0x1 << 19) -+#define PORT_P2_IN_P19_GET(val) ((((val) & PORT_P2_IN_P19) >> 19) & 0x1) -+/* Port 2 Pin # Latched Input Value (18) */ -+#define PORT_P2_IN_P18 (0x1 << 18) -+#define PORT_P2_IN_P18_GET(val) ((((val) & PORT_P2_IN_P18) >> 18) & 0x1) -+/* Port 2 Pin # Latched Input Value (17) */ -+#define PORT_P2_IN_P17 (0x1 << 17) -+#define PORT_P2_IN_P17_GET(val) ((((val) & PORT_P2_IN_P17) >> 17) & 0x1) -+/* Port 2 Pin # Latched Input Value (16) */ -+#define PORT_P2_IN_P16 (0x1 << 16) -+#define PORT_P2_IN_P16_GET(val) ((((val) & PORT_P2_IN_P16) >> 16) & 0x1) -+/* Port 2 Pin # Latched Input Value (15) */ -+#define PORT_P2_IN_P15 (0x1 << 15) -+#define PORT_P2_IN_P15_GET(val) ((((val) & PORT_P2_IN_P15) >> 15) & 0x1) -+/* Port 2 Pin # Latched Input Value (14) */ -+#define PORT_P2_IN_P14 (0x1 << 14) -+#define PORT_P2_IN_P14_GET(val) ((((val) & PORT_P2_IN_P14) >> 14) & 0x1) -+/* Port 2 Pin # Latched Input Value (13) */ -+#define PORT_P2_IN_P13 (0x1 << 13) -+#define PORT_P2_IN_P13_GET(val) ((((val) & PORT_P2_IN_P13) >> 13) & 0x1) -+/* Port 2 Pin # Latched Input Value (12) */ -+#define PORT_P2_IN_P12 (0x1 << 12) -+#define PORT_P2_IN_P12_GET(val) ((((val) & PORT_P2_IN_P12) >> 12) & 0x1) -+/* Port 2 Pin # Latched Input Value (11) */ -+#define PORT_P2_IN_P11 (0x1 << 11) -+#define PORT_P2_IN_P11_GET(val) ((((val) & PORT_P2_IN_P11) >> 11) & 0x1) -+/* Port 2 Pin # Latched Input Value (10) */ -+#define PORT_P2_IN_P10 (0x1 << 10) -+#define PORT_P2_IN_P10_GET(val) ((((val) & PORT_P2_IN_P10) >> 10) & 0x1) -+/* Port 2 Pin # Latched Input Value (9) */ -+#define PORT_P2_IN_P9 (0x1 << 9) -+#define PORT_P2_IN_P9_GET(val) ((((val) & PORT_P2_IN_P9) >> 9) & 0x1) -+/* Port 2 Pin # Latched Input Value (8) */ -+#define PORT_P2_IN_P8 (0x1 << 8) -+#define PORT_P2_IN_P8_GET(val) ((((val) & PORT_P2_IN_P8) >> 8) & 0x1) -+/* Port 2 Pin # Latched Input Value (7) */ -+#define PORT_P2_IN_P7 (0x1 << 7) -+#define PORT_P2_IN_P7_GET(val) ((((val) & PORT_P2_IN_P7) >> 7) & 0x1) -+/* Port 2 Pin # Latched Input Value (6) */ -+#define PORT_P2_IN_P6 (0x1 << 6) -+#define PORT_P2_IN_P6_GET(val) ((((val) & PORT_P2_IN_P6) >> 6) & 0x1) -+/* Port 2 Pin # Latched Input Value (5) */ -+#define PORT_P2_IN_P5 (0x1 << 5) -+#define PORT_P2_IN_P5_GET(val) ((((val) & PORT_P2_IN_P5) >> 5) & 0x1) -+/* Port 2 Pin # Latched Input Value (4) */ -+#define PORT_P2_IN_P4 (0x1 << 4) -+#define PORT_P2_IN_P4_GET(val) ((((val) & PORT_P2_IN_P4) >> 4) & 0x1) -+/* Port 2 Pin # Latched Input Value (3) */ -+#define PORT_P2_IN_P3 (0x1 << 3) -+#define PORT_P2_IN_P3_GET(val) ((((val) & PORT_P2_IN_P3) >> 3) & 0x1) -+/* Port 2 Pin # Latched Input Value (2) */ -+#define PORT_P2_IN_P2 (0x1 << 2) -+#define PORT_P2_IN_P2_GET(val) ((((val) & PORT_P2_IN_P2) >> 2) & 0x1) -+/* Port 2 Pin # Latched Input Value (1) */ -+#define PORT_P2_IN_P1 (0x1 << 1) -+#define PORT_P2_IN_P1_GET(val) ((((val) & PORT_P2_IN_P1) >> 1) & 0x1) -+/* Port 2 Pin # Latched Input Value (0) */ -+#define PORT_P2_IN_P0 (0x1) -+#define PORT_P2_IN_P0_GET(val) ((((val) & PORT_P2_IN_P0) >> 0) & 0x1) -+ -+/******************************************************************************* -+ * Port 2 Direction Register -+ ******************************************************************************/ -+ -+/* Port 2 Pin #Direction Control (19) */ -+#define PORT_P2_DIR_P19 (0x1 << 19) -+#define PORT_P2_DIR_P19_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P2_DIR_P19_GET(val) ((((val) & PORT_P2_DIR_P19) >> 19) & 0x1) -+#define PORT_P2_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P19) | (((val) & 0x1) << 19)) -+/* Port 2 Pin #Direction Control (18) */ -+#define PORT_P2_DIR_P18 (0x1 << 18) -+#define PORT_P2_DIR_P18_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P2_DIR_P18_GET(val) ((((val) & PORT_P2_DIR_P18) >> 18) & 0x1) -+#define PORT_P2_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P18) | (((val) & 0x1) << 18)) -+/* Port 2 Pin #Direction Control (17) */ -+#define PORT_P2_DIR_P17 (0x1 << 17) -+#define PORT_P2_DIR_P17_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P2_DIR_P17_GET(val) ((((val) & PORT_P2_DIR_P17) >> 17) & 0x1) -+#define PORT_P2_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P17) | (((val) & 0x1) << 17)) -+/* Port 2 Pin #Direction Control (16) */ -+#define PORT_P2_DIR_P16 (0x1 << 16) -+#define PORT_P2_DIR_P16_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P2_DIR_P16_GET(val) ((((val) & PORT_P2_DIR_P16) >> 16) & 0x1) -+#define PORT_P2_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P16) | (((val) & 0x1) << 16)) -+/* Port 2 Pin #Direction Control (15) */ -+#define PORT_P2_DIR_P15 (0x1 << 15) -+#define PORT_P2_DIR_P15_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P2_DIR_P15_GET(val) ((((val) & PORT_P2_DIR_P15) >> 15) & 0x1) -+#define PORT_P2_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P15) | (((val) & 0x1) << 15)) -+/* Port 2 Pin #Direction Control (14) */ -+#define PORT_P2_DIR_P14 (0x1 << 14) -+#define PORT_P2_DIR_P14_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P2_DIR_P14_GET(val) ((((val) & PORT_P2_DIR_P14) >> 14) & 0x1) -+#define PORT_P2_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P14) | (((val) & 0x1) << 14)) -+/* Port 2 Pin #Direction Control (13) */ -+#define PORT_P2_DIR_P13 (0x1 << 13) -+#define PORT_P2_DIR_P13_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P2_DIR_P13_GET(val) ((((val) & PORT_P2_DIR_P13) >> 13) & 0x1) -+#define PORT_P2_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P13) | (((val) & 0x1) << 13)) -+/* Port 2 Pin #Direction Control (12) */ -+#define PORT_P2_DIR_P12 (0x1 << 12) -+#define PORT_P2_DIR_P12_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P2_DIR_P12_GET(val) ((((val) & PORT_P2_DIR_P12) >> 12) & 0x1) -+#define PORT_P2_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P12) | (((val) & 0x1) << 12)) -+/* Port 2 Pin #Direction Control (11) */ -+#define PORT_P2_DIR_P11 (0x1 << 11) -+#define PORT_P2_DIR_P11_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P2_DIR_P11_GET(val) ((((val) & PORT_P2_DIR_P11) >> 11) & 0x1) -+#define PORT_P2_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P11) | (((val) & 0x1) << 11)) -+/* Port 2 Pin #Direction Control (10) */ -+#define PORT_P2_DIR_P10 (0x1 << 10) -+#define PORT_P2_DIR_P10_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P2_DIR_P10_GET(val) ((((val) & PORT_P2_DIR_P10) >> 10) & 0x1) -+#define PORT_P2_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P10) | (((val) & 0x1) << 10)) -+/* Port 2 Pin #Direction Control (9) */ -+#define PORT_P2_DIR_P9 (0x1 << 9) -+#define PORT_P2_DIR_P9_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P2_DIR_P9_GET(val) ((((val) & PORT_P2_DIR_P9) >> 9) & 0x1) -+#define PORT_P2_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P9) | (((val) & 0x1) << 9)) -+/* Port 2 Pin #Direction Control (8) */ -+#define PORT_P2_DIR_P8 (0x1 << 8) -+#define PORT_P2_DIR_P8_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P2_DIR_P8_GET(val) ((((val) & PORT_P2_DIR_P8) >> 8) & 0x1) -+#define PORT_P2_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P8) | (((val) & 0x1) << 8)) -+/* Port 2 Pin #Direction Control (7) */ -+#define PORT_P2_DIR_P7 (0x1 << 7) -+#define PORT_P2_DIR_P7_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P2_DIR_P7_GET(val) ((((val) & PORT_P2_DIR_P7) >> 7) & 0x1) -+#define PORT_P2_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P7) | (((val) & 0x1) << 7)) -+/* Port 2 Pin #Direction Control (6) */ -+#define PORT_P2_DIR_P6 (0x1 << 6) -+#define PORT_P2_DIR_P6_VAL(val) (((val) & 0x1) << 6) -+#define PORT_P2_DIR_P6_GET(val) ((((val) & PORT_P2_DIR_P6) >> 6) & 0x1) -+#define PORT_P2_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P6) | (((val) & 0x1) << 6)) -+/* Port 2 Pin #Direction Control (5) */ -+#define PORT_P2_DIR_P5 (0x1 << 5) -+#define PORT_P2_DIR_P5_VAL(val) (((val) & 0x1) << 5) -+#define PORT_P2_DIR_P5_GET(val) ((((val) & PORT_P2_DIR_P5) >> 5) & 0x1) -+#define PORT_P2_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P5) | (((val) & 0x1) << 5)) -+/* Port 2 Pin #Direction Control (4) */ -+#define PORT_P2_DIR_P4 (0x1 << 4) -+#define PORT_P2_DIR_P4_VAL(val) (((val) & 0x1) << 4) -+#define PORT_P2_DIR_P4_GET(val) ((((val) & PORT_P2_DIR_P4) >> 4) & 0x1) -+#define PORT_P2_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P4) | (((val) & 0x1) << 4)) -+/* Port 2 Pin #Direction Control (3) */ -+#define PORT_P2_DIR_P3 (0x1 << 3) -+#define PORT_P2_DIR_P3_VAL(val) (((val) & 0x1) << 3) -+#define PORT_P2_DIR_P3_GET(val) ((((val) & PORT_P2_DIR_P3) >> 3) & 0x1) -+#define PORT_P2_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P3) | (((val) & 0x1) << 3)) -+/* Port 2 Pin #Direction Control (2) */ -+#define PORT_P2_DIR_P2 (0x1 << 2) -+#define PORT_P2_DIR_P2_VAL(val) (((val) & 0x1) << 2) -+#define PORT_P2_DIR_P2_GET(val) ((((val) & PORT_P2_DIR_P2) >> 2) & 0x1) -+#define PORT_P2_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P2) | (((val) & 0x1) << 2)) -+/* Port 2 Pin #Direction Control (1) */ -+#define PORT_P2_DIR_P1 (0x1 << 1) -+#define PORT_P2_DIR_P1_VAL(val) (((val) & 0x1) << 1) -+#define PORT_P2_DIR_P1_GET(val) ((((val) & PORT_P2_DIR_P1) >> 1) & 0x1) -+#define PORT_P2_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P1) | (((val) & 0x1) << 1)) -+/* Port 2 Pin #Direction Control (0) */ -+#define PORT_P2_DIR_P0 (0x1) -+#define PORT_P2_DIR_P0_VAL(val) (((val) & 0x1) << 0) -+#define PORT_P2_DIR_P0_GET(val) ((((val) & PORT_P2_DIR_P0) >> 0) & 0x1) -+#define PORT_P2_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P0) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Port 2 Alternate Function Select Register 0 -+ ******************************************************************************/ -+ -+/* Alternate Function at Port 2 Bit # (19) */ -+#define PORT_P2_ALTSEL0_P19 (0x1 << 19) -+#define PORT_P2_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P2_ALTSEL0_P19_GET(val) ((((val) & PORT_P2_ALTSEL0_P19) >> 19) & 0x1) -+#define PORT_P2_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P19) | (((val) & 0x1) << 19)) -+/* Alternate Function at Port 2 Bit # (18) */ -+#define PORT_P2_ALTSEL0_P18 (0x1 << 18) -+#define PORT_P2_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P2_ALTSEL0_P18_GET(val) ((((val) & PORT_P2_ALTSEL0_P18) >> 18) & 0x1) -+#define PORT_P2_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P18) | (((val) & 0x1) << 18)) -+/* Alternate Function at Port 2 Bit # (17) */ -+#define PORT_P2_ALTSEL0_P17 (0x1 << 17) -+#define PORT_P2_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P2_ALTSEL0_P17_GET(val) ((((val) & PORT_P2_ALTSEL0_P17) >> 17) & 0x1) -+#define PORT_P2_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P17) | (((val) & 0x1) << 17)) -+/* Alternate Function at Port 2 Bit # (16) */ -+#define PORT_P2_ALTSEL0_P16 (0x1 << 16) -+#define PORT_P2_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P2_ALTSEL0_P16_GET(val) ((((val) & PORT_P2_ALTSEL0_P16) >> 16) & 0x1) -+#define PORT_P2_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P16) | (((val) & 0x1) << 16)) -+/* Alternate Function at Port 2 Bit # (15) */ -+#define PORT_P2_ALTSEL0_P15 (0x1 << 15) -+#define PORT_P2_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P2_ALTSEL0_P15_GET(val) ((((val) & PORT_P2_ALTSEL0_P15) >> 15) & 0x1) -+#define PORT_P2_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P15) | (((val) & 0x1) << 15)) -+/* Alternate Function at Port 2 Bit # (14) */ -+#define PORT_P2_ALTSEL0_P14 (0x1 << 14) -+#define PORT_P2_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P2_ALTSEL0_P14_GET(val) ((((val) & PORT_P2_ALTSEL0_P14) >> 14) & 0x1) -+#define PORT_P2_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P14) | (((val) & 0x1) << 14)) -+/* Alternate Function at Port 2 Bit # (13) */ -+#define PORT_P2_ALTSEL0_P13 (0x1 << 13) -+#define PORT_P2_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P2_ALTSEL0_P13_GET(val) ((((val) & PORT_P2_ALTSEL0_P13) >> 13) & 0x1) -+#define PORT_P2_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P13) | (((val) & 0x1) << 13)) -+/* Alternate Function at Port 2 Bit # (12) */ -+#define PORT_P2_ALTSEL0_P12 (0x1 << 12) -+#define PORT_P2_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P2_ALTSEL0_P12_GET(val) ((((val) & PORT_P2_ALTSEL0_P12) >> 12) & 0x1) -+#define PORT_P2_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P12) | (((val) & 0x1) << 12)) -+/* Alternate Function at Port 2 Bit # (11) */ -+#define PORT_P2_ALTSEL0_P11 (0x1 << 11) -+#define PORT_P2_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P2_ALTSEL0_P11_GET(val) ((((val) & PORT_P2_ALTSEL0_P11) >> 11) & 0x1) -+#define PORT_P2_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P11) | (((val) & 0x1) << 11)) -+/* Alternate Function at Port 2 Bit # (10) */ -+#define PORT_P2_ALTSEL0_P10 (0x1 << 10) -+#define PORT_P2_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P2_ALTSEL0_P10_GET(val) ((((val) & PORT_P2_ALTSEL0_P10) >> 10) & 0x1) -+#define PORT_P2_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P10) | (((val) & 0x1) << 10)) -+/* Alternate Function at Port 2 Bit # (9) */ -+#define PORT_P2_ALTSEL0_P9 (0x1 << 9) -+#define PORT_P2_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P2_ALTSEL0_P9_GET(val) ((((val) & PORT_P2_ALTSEL0_P9) >> 9) & 0x1) -+#define PORT_P2_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P9) | (((val) & 0x1) << 9)) -+/* Alternate Function at Port 2 Bit # (8) */ -+#define PORT_P2_ALTSEL0_P8 (0x1 << 8) -+#define PORT_P2_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P2_ALTSEL0_P8_GET(val) ((((val) & PORT_P2_ALTSEL0_P8) >> 8) & 0x1) -+#define PORT_P2_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P8) | (((val) & 0x1) << 8)) -+/* Alternate Function at Port 2 Bit # (7) */ -+#define PORT_P2_ALTSEL0_P7 (0x1 << 7) -+#define PORT_P2_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P2_ALTSEL0_P7_GET(val) ((((val) & PORT_P2_ALTSEL0_P7) >> 7) & 0x1) -+#define PORT_P2_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P7) | (((val) & 0x1) << 7)) -+/* Alternate Function at Port 2 Bit # (6) */ -+#define PORT_P2_ALTSEL0_P6 (0x1 << 6) -+#define PORT_P2_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) -+#define PORT_P2_ALTSEL0_P6_GET(val) ((((val) & PORT_P2_ALTSEL0_P6) >> 6) & 0x1) -+#define PORT_P2_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P6) | (((val) & 0x1) << 6)) -+/* Alternate Function at Port 2 Bit # (5) */ -+#define PORT_P2_ALTSEL0_P5 (0x1 << 5) -+#define PORT_P2_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) -+#define PORT_P2_ALTSEL0_P5_GET(val) ((((val) & PORT_P2_ALTSEL0_P5) >> 5) & 0x1) -+#define PORT_P2_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P5) | (((val) & 0x1) << 5)) -+/* Alternate Function at Port 2 Bit # (4) */ -+#define PORT_P2_ALTSEL0_P4 (0x1 << 4) -+#define PORT_P2_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) -+#define PORT_P2_ALTSEL0_P4_GET(val) ((((val) & PORT_P2_ALTSEL0_P4) >> 4) & 0x1) -+#define PORT_P2_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P4) | (((val) & 0x1) << 4)) -+/* Alternate Function at Port 2 Bit # (3) */ -+#define PORT_P2_ALTSEL0_P3 (0x1 << 3) -+#define PORT_P2_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) -+#define PORT_P2_ALTSEL0_P3_GET(val) ((((val) & PORT_P2_ALTSEL0_P3) >> 3) & 0x1) -+#define PORT_P2_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P3) | (((val) & 0x1) << 3)) -+/* Alternate Function at Port 2 Bit # (2) */ -+#define PORT_P2_ALTSEL0_P2 (0x1 << 2) -+#define PORT_P2_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) -+#define PORT_P2_ALTSEL0_P2_GET(val) ((((val) & PORT_P2_ALTSEL0_P2) >> 2) & 0x1) -+#define PORT_P2_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P2) | (((val) & 0x1) << 2)) -+/* Alternate Function at Port 2 Bit # (1) */ -+#define PORT_P2_ALTSEL0_P1 (0x1 << 1) -+#define PORT_P2_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) -+#define PORT_P2_ALTSEL0_P1_GET(val) ((((val) & PORT_P2_ALTSEL0_P1) >> 1) & 0x1) -+#define PORT_P2_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P1) | (((val) & 0x1) << 1)) -+/* Alternate Function at Port 2 Bit # (0) */ -+#define PORT_P2_ALTSEL0_P0 (0x1) -+#define PORT_P2_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) -+#define PORT_P2_ALTSEL0_P0_GET(val) ((((val) & PORT_P2_ALTSEL0_P0) >> 0) & 0x1) -+#define PORT_P2_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P0) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Port 2 Pull Up Device Enable Register -+ ******************************************************************************/ -+ -+/* Pull Up Device Enable at Port 2 Bit # (19) */ -+#define PORT_P2_PUEN_P19 (0x1 << 19) -+#define PORT_P2_PUEN_P19_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P2_PUEN_P19_GET(val) ((((val) & PORT_P2_PUEN_P19) >> 19) & 0x1) -+#define PORT_P2_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P19) | (((val) & 0x1) << 19)) -+/* Pull Up Device Enable at Port 2 Bit # (18) */ -+#define PORT_P2_PUEN_P18 (0x1 << 18) -+#define PORT_P2_PUEN_P18_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P2_PUEN_P18_GET(val) ((((val) & PORT_P2_PUEN_P18) >> 18) & 0x1) -+#define PORT_P2_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P18) | (((val) & 0x1) << 18)) -+/* Pull Up Device Enable at Port 2 Bit # (17) */ -+#define PORT_P2_PUEN_P17 (0x1 << 17) -+#define PORT_P2_PUEN_P17_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P2_PUEN_P17_GET(val) ((((val) & PORT_P2_PUEN_P17) >> 17) & 0x1) -+#define PORT_P2_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P17) | (((val) & 0x1) << 17)) -+/* Pull Up Device Enable at Port 2 Bit # (16) */ -+#define PORT_P2_PUEN_P16 (0x1 << 16) -+#define PORT_P2_PUEN_P16_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P2_PUEN_P16_GET(val) ((((val) & PORT_P2_PUEN_P16) >> 16) & 0x1) -+#define PORT_P2_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P16) | (((val) & 0x1) << 16)) -+/* Pull Up Device Enable at Port 2 Bit # (15) */ -+#define PORT_P2_PUEN_P15 (0x1 << 15) -+#define PORT_P2_PUEN_P15_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P2_PUEN_P15_GET(val) ((((val) & PORT_P2_PUEN_P15) >> 15) & 0x1) -+#define PORT_P2_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P15) | (((val) & 0x1) << 15)) -+/* Pull Up Device Enable at Port 2 Bit # (14) */ -+#define PORT_P2_PUEN_P14 (0x1 << 14) -+#define PORT_P2_PUEN_P14_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P2_PUEN_P14_GET(val) ((((val) & PORT_P2_PUEN_P14) >> 14) & 0x1) -+#define PORT_P2_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P14) | (((val) & 0x1) << 14)) -+/* Pull Up Device Enable at Port 2 Bit # (13) */ -+#define PORT_P2_PUEN_P13 (0x1 << 13) -+#define PORT_P2_PUEN_P13_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P2_PUEN_P13_GET(val) ((((val) & PORT_P2_PUEN_P13) >> 13) & 0x1) -+#define PORT_P2_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P13) | (((val) & 0x1) << 13)) -+/* Pull Up Device Enable at Port 2 Bit # (12) */ -+#define PORT_P2_PUEN_P12 (0x1 << 12) -+#define PORT_P2_PUEN_P12_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P2_PUEN_P12_GET(val) ((((val) & PORT_P2_PUEN_P12) >> 12) & 0x1) -+#define PORT_P2_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P12) | (((val) & 0x1) << 12)) -+/* Pull Up Device Enable at Port 2 Bit # (11) */ -+#define PORT_P2_PUEN_P11 (0x1 << 11) -+#define PORT_P2_PUEN_P11_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P2_PUEN_P11_GET(val) ((((val) & PORT_P2_PUEN_P11) >> 11) & 0x1) -+#define PORT_P2_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P11) | (((val) & 0x1) << 11)) -+/* Pull Up Device Enable at Port 2 Bit # (10) */ -+#define PORT_P2_PUEN_P10 (0x1 << 10) -+#define PORT_P2_PUEN_P10_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P2_PUEN_P10_GET(val) ((((val) & PORT_P2_PUEN_P10) >> 10) & 0x1) -+#define PORT_P2_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P10) | (((val) & 0x1) << 10)) -+/* Pull Up Device Enable at Port 2 Bit # (9) */ -+#define PORT_P2_PUEN_P9 (0x1 << 9) -+#define PORT_P2_PUEN_P9_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P2_PUEN_P9_GET(val) ((((val) & PORT_P2_PUEN_P9) >> 9) & 0x1) -+#define PORT_P2_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P9) | (((val) & 0x1) << 9)) -+/* Pull Up Device Enable at Port 2 Bit # (8) */ -+#define PORT_P2_PUEN_P8 (0x1 << 8) -+#define PORT_P2_PUEN_P8_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P2_PUEN_P8_GET(val) ((((val) & PORT_P2_PUEN_P8) >> 8) & 0x1) -+#define PORT_P2_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P8) | (((val) & 0x1) << 8)) -+/* Pull Up Device Enable at Port 2 Bit # (7) */ -+#define PORT_P2_PUEN_P7 (0x1 << 7) -+#define PORT_P2_PUEN_P7_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P2_PUEN_P7_GET(val) ((((val) & PORT_P2_PUEN_P7) >> 7) & 0x1) -+#define PORT_P2_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P7) | (((val) & 0x1) << 7)) -+/* Pull Up Device Enable at Port 2 Bit # (6) */ -+#define PORT_P2_PUEN_P6 (0x1 << 6) -+#define PORT_P2_PUEN_P6_VAL(val) (((val) & 0x1) << 6) -+#define PORT_P2_PUEN_P6_GET(val) ((((val) & PORT_P2_PUEN_P6) >> 6) & 0x1) -+#define PORT_P2_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P6) | (((val) & 0x1) << 6)) -+/* Pull Up Device Enable at Port 2 Bit # (5) */ -+#define PORT_P2_PUEN_P5 (0x1 << 5) -+#define PORT_P2_PUEN_P5_VAL(val) (((val) & 0x1) << 5) -+#define PORT_P2_PUEN_P5_GET(val) ((((val) & PORT_P2_PUEN_P5) >> 5) & 0x1) -+#define PORT_P2_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P5) | (((val) & 0x1) << 5)) -+/* Pull Up Device Enable at Port 2 Bit # (4) */ -+#define PORT_P2_PUEN_P4 (0x1 << 4) -+#define PORT_P2_PUEN_P4_VAL(val) (((val) & 0x1) << 4) -+#define PORT_P2_PUEN_P4_GET(val) ((((val) & PORT_P2_PUEN_P4) >> 4) & 0x1) -+#define PORT_P2_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P4) | (((val) & 0x1) << 4)) -+/* Pull Up Device Enable at Port 2 Bit # (3) */ -+#define PORT_P2_PUEN_P3 (0x1 << 3) -+#define PORT_P2_PUEN_P3_VAL(val) (((val) & 0x1) << 3) -+#define PORT_P2_PUEN_P3_GET(val) ((((val) & PORT_P2_PUEN_P3) >> 3) & 0x1) -+#define PORT_P2_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P3) | (((val) & 0x1) << 3)) -+/* Pull Up Device Enable at Port 2 Bit # (2) */ -+#define PORT_P2_PUEN_P2 (0x1 << 2) -+#define PORT_P2_PUEN_P2_VAL(val) (((val) & 0x1) << 2) -+#define PORT_P2_PUEN_P2_GET(val) ((((val) & PORT_P2_PUEN_P2) >> 2) & 0x1) -+#define PORT_P2_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P2) | (((val) & 0x1) << 2)) -+/* Pull Up Device Enable at Port 2 Bit # (1) */ -+#define PORT_P2_PUEN_P1 (0x1 << 1) -+#define PORT_P2_PUEN_P1_VAL(val) (((val) & 0x1) << 1) -+#define PORT_P2_PUEN_P1_GET(val) ((((val) & PORT_P2_PUEN_P1) >> 1) & 0x1) -+#define PORT_P2_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P1) | (((val) & 0x1) << 1)) -+/* Pull Up Device Enable at Port 2 Bit # (0) */ -+#define PORT_P2_PUEN_P0 (0x1) -+#define PORT_P2_PUEN_P0_VAL(val) (((val) & 0x1) << 0) -+#define PORT_P2_PUEN_P0_GET(val) ((((val) & PORT_P2_PUEN_P0) >> 0) & 0x1) -+#define PORT_P2_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P0) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Port 3 Data Output Register -+ ******************************************************************************/ -+ -+/* Port 3 Pin # Output Value (19) */ -+#define PORT_P3_OUT_P19 (0x1 << 19) -+#define PORT_P3_OUT_P19_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P3_OUT_P19_GET(val) ((((val) & PORT_P3_OUT_P19) >> 19) & 0x1) -+#define PORT_P3_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P19) | (((val) & 0x1) << 19)) -+/* Port 3 Pin # Output Value (18) */ -+#define PORT_P3_OUT_P18 (0x1 << 18) -+#define PORT_P3_OUT_P18_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P3_OUT_P18_GET(val) ((((val) & PORT_P3_OUT_P18) >> 18) & 0x1) -+#define PORT_P3_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P18) | (((val) & 0x1) << 18)) -+/* Port 3 Pin # Output Value (17) */ -+#define PORT_P3_OUT_P17 (0x1 << 17) -+#define PORT_P3_OUT_P17_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P3_OUT_P17_GET(val) ((((val) & PORT_P3_OUT_P17) >> 17) & 0x1) -+#define PORT_P3_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P17) | (((val) & 0x1) << 17)) -+/* Port 3 Pin # Output Value (16) */ -+#define PORT_P3_OUT_P16 (0x1 << 16) -+#define PORT_P3_OUT_P16_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P3_OUT_P16_GET(val) ((((val) & PORT_P3_OUT_P16) >> 16) & 0x1) -+#define PORT_P3_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P16) | (((val) & 0x1) << 16)) -+/* Port 3 Pin # Output Value (15) */ -+#define PORT_P3_OUT_P15 (0x1 << 15) -+#define PORT_P3_OUT_P15_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P3_OUT_P15_GET(val) ((((val) & PORT_P3_OUT_P15) >> 15) & 0x1) -+#define PORT_P3_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P15) | (((val) & 0x1) << 15)) -+/* Port 3 Pin # Output Value (14) */ -+#define PORT_P3_OUT_P14 (0x1 << 14) -+#define PORT_P3_OUT_P14_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P3_OUT_P14_GET(val) ((((val) & PORT_P3_OUT_P14) >> 14) & 0x1) -+#define PORT_P3_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P14) | (((val) & 0x1) << 14)) -+/* Port 3 Pin # Output Value (13) */ -+#define PORT_P3_OUT_P13 (0x1 << 13) -+#define PORT_P3_OUT_P13_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P3_OUT_P13_GET(val) ((((val) & PORT_P3_OUT_P13) >> 13) & 0x1) -+#define PORT_P3_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P13) | (((val) & 0x1) << 13)) -+/* Port 3 Pin # Output Value (12) */ -+#define PORT_P3_OUT_P12 (0x1 << 12) -+#define PORT_P3_OUT_P12_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P3_OUT_P12_GET(val) ((((val) & PORT_P3_OUT_P12) >> 12) & 0x1) -+#define PORT_P3_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P12) | (((val) & 0x1) << 12)) -+/* Port 3 Pin # Output Value (11) */ -+#define PORT_P3_OUT_P11 (0x1 << 11) -+#define PORT_P3_OUT_P11_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P3_OUT_P11_GET(val) ((((val) & PORT_P3_OUT_P11) >> 11) & 0x1) -+#define PORT_P3_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P11) | (((val) & 0x1) << 11)) -+/* Port 3 Pin # Output Value (10) */ -+#define PORT_P3_OUT_P10 (0x1 << 10) -+#define PORT_P3_OUT_P10_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P3_OUT_P10_GET(val) ((((val) & PORT_P3_OUT_P10) >> 10) & 0x1) -+#define PORT_P3_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P10) | (((val) & 0x1) << 10)) -+/* Port 3 Pin # Output Value (9) */ -+#define PORT_P3_OUT_P9 (0x1 << 9) -+#define PORT_P3_OUT_P9_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P3_OUT_P9_GET(val) ((((val) & PORT_P3_OUT_P9) >> 9) & 0x1) -+#define PORT_P3_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P9) | (((val) & 0x1) << 9)) -+/* Port 3 Pin # Output Value (8) */ -+#define PORT_P3_OUT_P8 (0x1 << 8) -+#define PORT_P3_OUT_P8_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P3_OUT_P8_GET(val) ((((val) & PORT_P3_OUT_P8) >> 8) & 0x1) -+#define PORT_P3_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P8) | (((val) & 0x1) << 8)) -+/* Port 3 Pin # Output Value (7) */ -+#define PORT_P3_OUT_P7 (0x1 << 7) -+#define PORT_P3_OUT_P7_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P3_OUT_P7_GET(val) ((((val) & PORT_P3_OUT_P7) >> 7) & 0x1) -+#define PORT_P3_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P7) | (((val) & 0x1) << 7)) -+/* Port 3 Pin # Output Value (6) */ -+#define PORT_P3_OUT_P6 (0x1 << 6) -+#define PORT_P3_OUT_P6_VAL(val) (((val) & 0x1) << 6) -+#define PORT_P3_OUT_P6_GET(val) ((((val) & PORT_P3_OUT_P6) >> 6) & 0x1) -+#define PORT_P3_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P6) | (((val) & 0x1) << 6)) -+/* Port 3 Pin # Output Value (5) */ -+#define PORT_P3_OUT_P5 (0x1 << 5) -+#define PORT_P3_OUT_P5_VAL(val) (((val) & 0x1) << 5) -+#define PORT_P3_OUT_P5_GET(val) ((((val) & PORT_P3_OUT_P5) >> 5) & 0x1) -+#define PORT_P3_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P5) | (((val) & 0x1) << 5)) -+/* Port 3 Pin # Output Value (4) */ -+#define PORT_P3_OUT_P4 (0x1 << 4) -+#define PORT_P3_OUT_P4_VAL(val) (((val) & 0x1) << 4) -+#define PORT_P3_OUT_P4_GET(val) ((((val) & PORT_P3_OUT_P4) >> 4) & 0x1) -+#define PORT_P3_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P4) | (((val) & 0x1) << 4)) -+/* Port 3 Pin # Output Value (3) */ -+#define PORT_P3_OUT_P3 (0x1 << 3) -+#define PORT_P3_OUT_P3_VAL(val) (((val) & 0x1) << 3) -+#define PORT_P3_OUT_P3_GET(val) ((((val) & PORT_P3_OUT_P3) >> 3) & 0x1) -+#define PORT_P3_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P3) | (((val) & 0x1) << 3)) -+/* Port 3 Pin # Output Value (2) */ -+#define PORT_P3_OUT_P2 (0x1 << 2) -+#define PORT_P3_OUT_P2_VAL(val) (((val) & 0x1) << 2) -+#define PORT_P3_OUT_P2_GET(val) ((((val) & PORT_P3_OUT_P2) >> 2) & 0x1) -+#define PORT_P3_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P2) | (((val) & 0x1) << 2)) -+/* Port 3 Pin # Output Value (1) */ -+#define PORT_P3_OUT_P1 (0x1 << 1) -+#define PORT_P3_OUT_P1_VAL(val) (((val) & 0x1) << 1) -+#define PORT_P3_OUT_P1_GET(val) ((((val) & PORT_P3_OUT_P1) >> 1) & 0x1) -+#define PORT_P3_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P1) | (((val) & 0x1) << 1)) -+/* Port 3 Pin # Output Value (0) */ -+#define PORT_P3_OUT_P0 (0x1) -+#define PORT_P3_OUT_P0_VAL(val) (((val) & 0x1) << 0) -+#define PORT_P3_OUT_P0_GET(val) ((((val) & PORT_P3_OUT_P0) >> 0) & 0x1) -+#define PORT_P3_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P0) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Port 3 Data Input Register -+ ******************************************************************************/ -+ -+/* Port 3 Pin # Latched Input Value (19) */ -+#define PORT_P3_IN_P19 (0x1 << 19) -+#define PORT_P3_IN_P19_GET(val) ((((val) & PORT_P3_IN_P19) >> 19) & 0x1) -+/* Port 3 Pin # Latched Input Value (18) */ -+#define PORT_P3_IN_P18 (0x1 << 18) -+#define PORT_P3_IN_P18_GET(val) ((((val) & PORT_P3_IN_P18) >> 18) & 0x1) -+/* Port 3 Pin # Latched Input Value (17) */ -+#define PORT_P3_IN_P17 (0x1 << 17) -+#define PORT_P3_IN_P17_GET(val) ((((val) & PORT_P3_IN_P17) >> 17) & 0x1) -+/* Port 3 Pin # Latched Input Value (16) */ -+#define PORT_P3_IN_P16 (0x1 << 16) -+#define PORT_P3_IN_P16_GET(val) ((((val) & PORT_P3_IN_P16) >> 16) & 0x1) -+/* Port 3 Pin # Latched Input Value (15) */ -+#define PORT_P3_IN_P15 (0x1 << 15) -+#define PORT_P3_IN_P15_GET(val) ((((val) & PORT_P3_IN_P15) >> 15) & 0x1) -+/* Port 3 Pin # Latched Input Value (14) */ -+#define PORT_P3_IN_P14 (0x1 << 14) -+#define PORT_P3_IN_P14_GET(val) ((((val) & PORT_P3_IN_P14) >> 14) & 0x1) -+/* Port 3 Pin # Latched Input Value (13) */ -+#define PORT_P3_IN_P13 (0x1 << 13) -+#define PORT_P3_IN_P13_GET(val) ((((val) & PORT_P3_IN_P13) >> 13) & 0x1) -+/* Port 3 Pin # Latched Input Value (12) */ -+#define PORT_P3_IN_P12 (0x1 << 12) -+#define PORT_P3_IN_P12_GET(val) ((((val) & PORT_P3_IN_P12) >> 12) & 0x1) -+/* Port 3 Pin # Latched Input Value (11) */ -+#define PORT_P3_IN_P11 (0x1 << 11) -+#define PORT_P3_IN_P11_GET(val) ((((val) & PORT_P3_IN_P11) >> 11) & 0x1) -+/* Port 3 Pin # Latched Input Value (10) */ -+#define PORT_P3_IN_P10 (0x1 << 10) -+#define PORT_P3_IN_P10_GET(val) ((((val) & PORT_P3_IN_P10) >> 10) & 0x1) -+/* Port 3 Pin # Latched Input Value (9) */ -+#define PORT_P3_IN_P9 (0x1 << 9) -+#define PORT_P3_IN_P9_GET(val) ((((val) & PORT_P3_IN_P9) >> 9) & 0x1) -+/* Port 3 Pin # Latched Input Value (8) */ -+#define PORT_P3_IN_P8 (0x1 << 8) -+#define PORT_P3_IN_P8_GET(val) ((((val) & PORT_P3_IN_P8) >> 8) & 0x1) -+/* Port 3 Pin # Latched Input Value (7) */ -+#define PORT_P3_IN_P7 (0x1 << 7) -+#define PORT_P3_IN_P7_GET(val) ((((val) & PORT_P3_IN_P7) >> 7) & 0x1) -+/* Port 3 Pin # Latched Input Value (6) */ -+#define PORT_P3_IN_P6 (0x1 << 6) -+#define PORT_P3_IN_P6_GET(val) ((((val) & PORT_P3_IN_P6) >> 6) & 0x1) -+/* Port 3 Pin # Latched Input Value (5) */ -+#define PORT_P3_IN_P5 (0x1 << 5) -+#define PORT_P3_IN_P5_GET(val) ((((val) & PORT_P3_IN_P5) >> 5) & 0x1) -+/* Port 3 Pin # Latched Input Value (4) */ -+#define PORT_P3_IN_P4 (0x1 << 4) -+#define PORT_P3_IN_P4_GET(val) ((((val) & PORT_P3_IN_P4) >> 4) & 0x1) -+/* Port 3 Pin # Latched Input Value (3) */ -+#define PORT_P3_IN_P3 (0x1 << 3) -+#define PORT_P3_IN_P3_GET(val) ((((val) & PORT_P3_IN_P3) >> 3) & 0x1) -+/* Port 3 Pin # Latched Input Value (2) */ -+#define PORT_P3_IN_P2 (0x1 << 2) -+#define PORT_P3_IN_P2_GET(val) ((((val) & PORT_P3_IN_P2) >> 2) & 0x1) -+/* Port 3 Pin # Latched Input Value (1) */ -+#define PORT_P3_IN_P1 (0x1 << 1) -+#define PORT_P3_IN_P1_GET(val) ((((val) & PORT_P3_IN_P1) >> 1) & 0x1) -+/* Port 3 Pin # Latched Input Value (0) */ -+#define PORT_P3_IN_P0 (0x1) -+#define PORT_P3_IN_P0_GET(val) ((((val) & PORT_P3_IN_P0) >> 0) & 0x1) -+ -+/******************************************************************************* -+ * Port 3 Direction Register -+ ******************************************************************************/ -+ -+/* Port 3 Pin #Direction Control (19) */ -+#define PORT_P3_DIR_P19 (0x1 << 19) -+#define PORT_P3_DIR_P19_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P3_DIR_P19_GET(val) ((((val) & PORT_P3_DIR_P19) >> 19) & 0x1) -+#define PORT_P3_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P19) | (((val) & 0x1) << 19)) -+/* Port 3 Pin #Direction Control (18) */ -+#define PORT_P3_DIR_P18 (0x1 << 18) -+#define PORT_P3_DIR_P18_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P3_DIR_P18_GET(val) ((((val) & PORT_P3_DIR_P18) >> 18) & 0x1) -+#define PORT_P3_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P18) | (((val) & 0x1) << 18)) -+/* Port 3 Pin #Direction Control (17) */ -+#define PORT_P3_DIR_P17 (0x1 << 17) -+#define PORT_P3_DIR_P17_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P3_DIR_P17_GET(val) ((((val) & PORT_P3_DIR_P17) >> 17) & 0x1) -+#define PORT_P3_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P17) | (((val) & 0x1) << 17)) -+/* Port 3 Pin #Direction Control (16) */ -+#define PORT_P3_DIR_P16 (0x1 << 16) -+#define PORT_P3_DIR_P16_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P3_DIR_P16_GET(val) ((((val) & PORT_P3_DIR_P16) >> 16) & 0x1) -+#define PORT_P3_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P16) | (((val) & 0x1) << 16)) -+/* Port 3 Pin #Direction Control (15) */ -+#define PORT_P3_DIR_P15 (0x1 << 15) -+#define PORT_P3_DIR_P15_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P3_DIR_P15_GET(val) ((((val) & PORT_P3_DIR_P15) >> 15) & 0x1) -+#define PORT_P3_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P15) | (((val) & 0x1) << 15)) -+/* Port 3 Pin #Direction Control (14) */ -+#define PORT_P3_DIR_P14 (0x1 << 14) -+#define PORT_P3_DIR_P14_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P3_DIR_P14_GET(val) ((((val) & PORT_P3_DIR_P14) >> 14) & 0x1) -+#define PORT_P3_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P14) | (((val) & 0x1) << 14)) -+/* Port 3 Pin #Direction Control (13) */ -+#define PORT_P3_DIR_P13 (0x1 << 13) -+#define PORT_P3_DIR_P13_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P3_DIR_P13_GET(val) ((((val) & PORT_P3_DIR_P13) >> 13) & 0x1) -+#define PORT_P3_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P13) | (((val) & 0x1) << 13)) -+/* Port 3 Pin #Direction Control (12) */ -+#define PORT_P3_DIR_P12 (0x1 << 12) -+#define PORT_P3_DIR_P12_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P3_DIR_P12_GET(val) ((((val) & PORT_P3_DIR_P12) >> 12) & 0x1) -+#define PORT_P3_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P12) | (((val) & 0x1) << 12)) -+/* Port 3 Pin #Direction Control (11) */ -+#define PORT_P3_DIR_P11 (0x1 << 11) -+#define PORT_P3_DIR_P11_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P3_DIR_P11_GET(val) ((((val) & PORT_P3_DIR_P11) >> 11) & 0x1) -+#define PORT_P3_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P11) | (((val) & 0x1) << 11)) -+/* Port 3 Pin #Direction Control (10) */ -+#define PORT_P3_DIR_P10 (0x1 << 10) -+#define PORT_P3_DIR_P10_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P3_DIR_P10_GET(val) ((((val) & PORT_P3_DIR_P10) >> 10) & 0x1) -+#define PORT_P3_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P10) | (((val) & 0x1) << 10)) -+/* Port 3 Pin #Direction Control (9) */ -+#define PORT_P3_DIR_P9 (0x1 << 9) -+#define PORT_P3_DIR_P9_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P3_DIR_P9_GET(val) ((((val) & PORT_P3_DIR_P9) >> 9) & 0x1) -+#define PORT_P3_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P9) | (((val) & 0x1) << 9)) -+/* Port 3 Pin #Direction Control (8) */ -+#define PORT_P3_DIR_P8 (0x1 << 8) -+#define PORT_P3_DIR_P8_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P3_DIR_P8_GET(val) ((((val) & PORT_P3_DIR_P8) >> 8) & 0x1) -+#define PORT_P3_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P8) | (((val) & 0x1) << 8)) -+/* Port 3 Pin #Direction Control (7) */ -+#define PORT_P3_DIR_P7 (0x1 << 7) -+#define PORT_P3_DIR_P7_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P3_DIR_P7_GET(val) ((((val) & PORT_P3_DIR_P7) >> 7) & 0x1) -+#define PORT_P3_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P7) | (((val) & 0x1) << 7)) -+/* Port 3 Pin #Direction Control (6) */ -+#define PORT_P3_DIR_P6 (0x1 << 6) -+#define PORT_P3_DIR_P6_VAL(val) (((val) & 0x1) << 6) -+#define PORT_P3_DIR_P6_GET(val) ((((val) & PORT_P3_DIR_P6) >> 6) & 0x1) -+#define PORT_P3_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P6) | (((val) & 0x1) << 6)) -+/* Port 3 Pin #Direction Control (5) */ -+#define PORT_P3_DIR_P5 (0x1 << 5) -+#define PORT_P3_DIR_P5_VAL(val) (((val) & 0x1) << 5) -+#define PORT_P3_DIR_P5_GET(val) ((((val) & PORT_P3_DIR_P5) >> 5) & 0x1) -+#define PORT_P3_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P5) | (((val) & 0x1) << 5)) -+/* Port 3 Pin #Direction Control (4) */ -+#define PORT_P3_DIR_P4 (0x1 << 4) -+#define PORT_P3_DIR_P4_VAL(val) (((val) & 0x1) << 4) -+#define PORT_P3_DIR_P4_GET(val) ((((val) & PORT_P3_DIR_P4) >> 4) & 0x1) -+#define PORT_P3_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P4) | (((val) & 0x1) << 4)) -+/* Port 3 Pin #Direction Control (3) */ -+#define PORT_P3_DIR_P3 (0x1 << 3) -+#define PORT_P3_DIR_P3_VAL(val) (((val) & 0x1) << 3) -+#define PORT_P3_DIR_P3_GET(val) ((((val) & PORT_P3_DIR_P3) >> 3) & 0x1) -+#define PORT_P3_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P3) | (((val) & 0x1) << 3)) -+/* Port 3 Pin #Direction Control (2) */ -+#define PORT_P3_DIR_P2 (0x1 << 2) -+#define PORT_P3_DIR_P2_VAL(val) (((val) & 0x1) << 2) -+#define PORT_P3_DIR_P2_GET(val) ((((val) & PORT_P3_DIR_P2) >> 2) & 0x1) -+#define PORT_P3_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P2) | (((val) & 0x1) << 2)) -+/* Port 3 Pin #Direction Control (1) */ -+#define PORT_P3_DIR_P1 (0x1 << 1) -+#define PORT_P3_DIR_P1_VAL(val) (((val) & 0x1) << 1) -+#define PORT_P3_DIR_P1_GET(val) ((((val) & PORT_P3_DIR_P1) >> 1) & 0x1) -+#define PORT_P3_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P1) | (((val) & 0x1) << 1)) -+/* Port 3 Pin #Direction Control (0) */ -+#define PORT_P3_DIR_P0 (0x1) -+#define PORT_P3_DIR_P0_VAL(val) (((val) & 0x1) << 0) -+#define PORT_P3_DIR_P0_GET(val) ((((val) & PORT_P3_DIR_P0) >> 0) & 0x1) -+#define PORT_P3_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P0) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Port 3 Alternate Function Select Register 0 -+ ******************************************************************************/ -+ -+/* Alternate Function at Port 3 Bit # (19) */ -+#define PORT_P3_ALTSEL0_P19 (0x1 << 19) -+#define PORT_P3_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P3_ALTSEL0_P19_GET(val) ((((val) & PORT_P3_ALTSEL0_P19) >> 19) & 0x1) -+#define PORT_P3_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P19) | (((val) & 0x1) << 19)) -+/* Alternate Function at Port 3 Bit # (18) */ -+#define PORT_P3_ALTSEL0_P18 (0x1 << 18) -+#define PORT_P3_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P3_ALTSEL0_P18_GET(val) ((((val) & PORT_P3_ALTSEL0_P18) >> 18) & 0x1) -+#define PORT_P3_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P18) | (((val) & 0x1) << 18)) -+/* Alternate Function at Port 3 Bit # (17) */ -+#define PORT_P3_ALTSEL0_P17 (0x1 << 17) -+#define PORT_P3_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P3_ALTSEL0_P17_GET(val) ((((val) & PORT_P3_ALTSEL0_P17) >> 17) & 0x1) -+#define PORT_P3_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P17) | (((val) & 0x1) << 17)) -+/* Alternate Function at Port 3 Bit # (16) */ -+#define PORT_P3_ALTSEL0_P16 (0x1 << 16) -+#define PORT_P3_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P3_ALTSEL0_P16_GET(val) ((((val) & PORT_P3_ALTSEL0_P16) >> 16) & 0x1) -+#define PORT_P3_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P16) | (((val) & 0x1) << 16)) -+/* Alternate Function at Port 3 Bit # (15) */ -+#define PORT_P3_ALTSEL0_P15 (0x1 << 15) -+#define PORT_P3_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P3_ALTSEL0_P15_GET(val) ((((val) & PORT_P3_ALTSEL0_P15) >> 15) & 0x1) -+#define PORT_P3_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P15) | (((val) & 0x1) << 15)) -+/* Alternate Function at Port 3 Bit # (14) */ -+#define PORT_P3_ALTSEL0_P14 (0x1 << 14) -+#define PORT_P3_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P3_ALTSEL0_P14_GET(val) ((((val) & PORT_P3_ALTSEL0_P14) >> 14) & 0x1) -+#define PORT_P3_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P14) | (((val) & 0x1) << 14)) -+/* Alternate Function at Port 3 Bit # (13) */ -+#define PORT_P3_ALTSEL0_P13 (0x1 << 13) -+#define PORT_P3_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P3_ALTSEL0_P13_GET(val) ((((val) & PORT_P3_ALTSEL0_P13) >> 13) & 0x1) -+#define PORT_P3_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P13) | (((val) & 0x1) << 13)) -+/* Alternate Function at Port 3 Bit # (12) */ -+#define PORT_P3_ALTSEL0_P12 (0x1 << 12) -+#define PORT_P3_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P3_ALTSEL0_P12_GET(val) ((((val) & PORT_P3_ALTSEL0_P12) >> 12) & 0x1) -+#define PORT_P3_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P12) | (((val) & 0x1) << 12)) -+/* Alternate Function at Port 3 Bit # (11) */ -+#define PORT_P3_ALTSEL0_P11 (0x1 << 11) -+#define PORT_P3_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P3_ALTSEL0_P11_GET(val) ((((val) & PORT_P3_ALTSEL0_P11) >> 11) & 0x1) -+#define PORT_P3_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P11) | (((val) & 0x1) << 11)) -+/* Alternate Function at Port 3 Bit # (10) */ -+#define PORT_P3_ALTSEL0_P10 (0x1 << 10) -+#define PORT_P3_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P3_ALTSEL0_P10_GET(val) ((((val) & PORT_P3_ALTSEL0_P10) >> 10) & 0x1) -+#define PORT_P3_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P10) | (((val) & 0x1) << 10)) -+/* Alternate Function at Port 3 Bit # (9) */ -+#define PORT_P3_ALTSEL0_P9 (0x1 << 9) -+#define PORT_P3_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P3_ALTSEL0_P9_GET(val) ((((val) & PORT_P3_ALTSEL0_P9) >> 9) & 0x1) -+#define PORT_P3_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P9) | (((val) & 0x1) << 9)) -+/* Alternate Function at Port 3 Bit # (8) */ -+#define PORT_P3_ALTSEL0_P8 (0x1 << 8) -+#define PORT_P3_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P3_ALTSEL0_P8_GET(val) ((((val) & PORT_P3_ALTSEL0_P8) >> 8) & 0x1) -+#define PORT_P3_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P8) | (((val) & 0x1) << 8)) -+/* Alternate Function at Port 3 Bit # (7) */ -+#define PORT_P3_ALTSEL0_P7 (0x1 << 7) -+#define PORT_P3_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P3_ALTSEL0_P7_GET(val) ((((val) & PORT_P3_ALTSEL0_P7) >> 7) & 0x1) -+#define PORT_P3_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P7) | (((val) & 0x1) << 7)) -+/* Alternate Function at Port 3 Bit # (6) */ -+#define PORT_P3_ALTSEL0_P6 (0x1 << 6) -+#define PORT_P3_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) -+#define PORT_P3_ALTSEL0_P6_GET(val) ((((val) & PORT_P3_ALTSEL0_P6) >> 6) & 0x1) -+#define PORT_P3_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P6) | (((val) & 0x1) << 6)) -+/* Alternate Function at Port 3 Bit # (5) */ -+#define PORT_P3_ALTSEL0_P5 (0x1 << 5) -+#define PORT_P3_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) -+#define PORT_P3_ALTSEL0_P5_GET(val) ((((val) & PORT_P3_ALTSEL0_P5) >> 5) & 0x1) -+#define PORT_P3_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P5) | (((val) & 0x1) << 5)) -+/* Alternate Function at Port 3 Bit # (4) */ -+#define PORT_P3_ALTSEL0_P4 (0x1 << 4) -+#define PORT_P3_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) -+#define PORT_P3_ALTSEL0_P4_GET(val) ((((val) & PORT_P3_ALTSEL0_P4) >> 4) & 0x1) -+#define PORT_P3_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P4) | (((val) & 0x1) << 4)) -+/* Alternate Function at Port 3 Bit # (3) */ -+#define PORT_P3_ALTSEL0_P3 (0x1 << 3) -+#define PORT_P3_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) -+#define PORT_P3_ALTSEL0_P3_GET(val) ((((val) & PORT_P3_ALTSEL0_P3) >> 3) & 0x1) -+#define PORT_P3_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P3) | (((val) & 0x1) << 3)) -+/* Alternate Function at Port 3 Bit # (2) */ -+#define PORT_P3_ALTSEL0_P2 (0x1 << 2) -+#define PORT_P3_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) -+#define PORT_P3_ALTSEL0_P2_GET(val) ((((val) & PORT_P3_ALTSEL0_P2) >> 2) & 0x1) -+#define PORT_P3_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P2) | (((val) & 0x1) << 2)) -+/* Alternate Function at Port 3 Bit # (1) */ -+#define PORT_P3_ALTSEL0_P1 (0x1 << 1) -+#define PORT_P3_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) -+#define PORT_P3_ALTSEL0_P1_GET(val) ((((val) & PORT_P3_ALTSEL0_P1) >> 1) & 0x1) -+#define PORT_P3_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P1) | (((val) & 0x1) << 1)) -+/* Alternate Function at Port 3 Bit # (0) */ -+#define PORT_P3_ALTSEL0_P0 (0x1) -+#define PORT_P3_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) -+#define PORT_P3_ALTSEL0_P0_GET(val) ((((val) & PORT_P3_ALTSEL0_P0) >> 0) & 0x1) -+#define PORT_P3_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P0) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Port 3 Pull Up Device Enable Register -+ ******************************************************************************/ -+ -+/* Pull Up Device Enable at Port 3 Bit # (19) */ -+#define PORT_P3_PUEN_P19 (0x1 << 19) -+#define PORT_P3_PUEN_P19_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P3_PUEN_P19_GET(val) ((((val) & PORT_P3_PUEN_P19) >> 19) & 0x1) -+#define PORT_P3_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P19) | (((val) & 0x1) << 19)) -+/* Pull Up Device Enable at Port 3 Bit # (18) */ -+#define PORT_P3_PUEN_P18 (0x1 << 18) -+#define PORT_P3_PUEN_P18_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P3_PUEN_P18_GET(val) ((((val) & PORT_P3_PUEN_P18) >> 18) & 0x1) -+#define PORT_P3_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P18) | (((val) & 0x1) << 18)) -+/* Pull Up Device Enable at Port 3 Bit # (17) */ -+#define PORT_P3_PUEN_P17 (0x1 << 17) -+#define PORT_P3_PUEN_P17_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P3_PUEN_P17_GET(val) ((((val) & PORT_P3_PUEN_P17) >> 17) & 0x1) -+#define PORT_P3_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P17) | (((val) & 0x1) << 17)) -+/* Pull Up Device Enable at Port 3 Bit # (16) */ -+#define PORT_P3_PUEN_P16 (0x1 << 16) -+#define PORT_P3_PUEN_P16_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P3_PUEN_P16_GET(val) ((((val) & PORT_P3_PUEN_P16) >> 16) & 0x1) -+#define PORT_P3_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P16) | (((val) & 0x1) << 16)) -+/* Pull Up Device Enable at Port 3 Bit # (15) */ -+#define PORT_P3_PUEN_P15 (0x1 << 15) -+#define PORT_P3_PUEN_P15_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P3_PUEN_P15_GET(val) ((((val) & PORT_P3_PUEN_P15) >> 15) & 0x1) -+#define PORT_P3_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P15) | (((val) & 0x1) << 15)) -+/* Pull Up Device Enable at Port 3 Bit # (14) */ -+#define PORT_P3_PUEN_P14 (0x1 << 14) -+#define PORT_P3_PUEN_P14_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P3_PUEN_P14_GET(val) ((((val) & PORT_P3_PUEN_P14) >> 14) & 0x1) -+#define PORT_P3_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P14) | (((val) & 0x1) << 14)) -+/* Pull Up Device Enable at Port 3 Bit # (13) */ -+#define PORT_P3_PUEN_P13 (0x1 << 13) -+#define PORT_P3_PUEN_P13_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P3_PUEN_P13_GET(val) ((((val) & PORT_P3_PUEN_P13) >> 13) & 0x1) -+#define PORT_P3_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P13) | (((val) & 0x1) << 13)) -+/* Pull Up Device Enable at Port 3 Bit # (12) */ -+#define PORT_P3_PUEN_P12 (0x1 << 12) -+#define PORT_P3_PUEN_P12_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P3_PUEN_P12_GET(val) ((((val) & PORT_P3_PUEN_P12) >> 12) & 0x1) -+#define PORT_P3_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P12) | (((val) & 0x1) << 12)) -+/* Pull Up Device Enable at Port 3 Bit # (11) */ -+#define PORT_P3_PUEN_P11 (0x1 << 11) -+#define PORT_P3_PUEN_P11_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P3_PUEN_P11_GET(val) ((((val) & PORT_P3_PUEN_P11) >> 11) & 0x1) -+#define PORT_P3_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P11) | (((val) & 0x1) << 11)) -+/* Pull Up Device Enable at Port 3 Bit # (10) */ -+#define PORT_P3_PUEN_P10 (0x1 << 10) -+#define PORT_P3_PUEN_P10_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P3_PUEN_P10_GET(val) ((((val) & PORT_P3_PUEN_P10) >> 10) & 0x1) -+#define PORT_P3_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P10) | (((val) & 0x1) << 10)) -+/* Pull Up Device Enable at Port 3 Bit # (9) */ -+#define PORT_P3_PUEN_P9 (0x1 << 9) -+#define PORT_P3_PUEN_P9_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P3_PUEN_P9_GET(val) ((((val) & PORT_P3_PUEN_P9) >> 9) & 0x1) -+#define PORT_P3_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P9) | (((val) & 0x1) << 9)) -+/* Pull Up Device Enable at Port 3 Bit # (8) */ -+#define PORT_P3_PUEN_P8 (0x1 << 8) -+#define PORT_P3_PUEN_P8_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P3_PUEN_P8_GET(val) ((((val) & PORT_P3_PUEN_P8) >> 8) & 0x1) -+#define PORT_P3_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P8) | (((val) & 0x1) << 8)) -+/* Pull Up Device Enable at Port 3 Bit # (7) */ -+#define PORT_P3_PUEN_P7 (0x1 << 7) -+#define PORT_P3_PUEN_P7_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P3_PUEN_P7_GET(val) ((((val) & PORT_P3_PUEN_P7) >> 7) & 0x1) -+#define PORT_P3_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P7) | (((val) & 0x1) << 7)) -+/* Pull Up Device Enable at Port 3 Bit # (6) */ -+#define PORT_P3_PUEN_P6 (0x1 << 6) -+#define PORT_P3_PUEN_P6_VAL(val) (((val) & 0x1) << 6) -+#define PORT_P3_PUEN_P6_GET(val) ((((val) & PORT_P3_PUEN_P6) >> 6) & 0x1) -+#define PORT_P3_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P6) | (((val) & 0x1) << 6)) -+/* Pull Up Device Enable at Port 3 Bit # (5) */ -+#define PORT_P3_PUEN_P5 (0x1 << 5) -+#define PORT_P3_PUEN_P5_VAL(val) (((val) & 0x1) << 5) -+#define PORT_P3_PUEN_P5_GET(val) ((((val) & PORT_P3_PUEN_P5) >> 5) & 0x1) -+#define PORT_P3_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P5) | (((val) & 0x1) << 5)) -+/* Pull Up Device Enable at Port 3 Bit # (4) */ -+#define PORT_P3_PUEN_P4 (0x1 << 4) -+#define PORT_P3_PUEN_P4_VAL(val) (((val) & 0x1) << 4) -+#define PORT_P3_PUEN_P4_GET(val) ((((val) & PORT_P3_PUEN_P4) >> 4) & 0x1) -+#define PORT_P3_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P4) | (((val) & 0x1) << 4)) -+/* Pull Up Device Enable at Port 3 Bit # (3) */ -+#define PORT_P3_PUEN_P3 (0x1 << 3) -+#define PORT_P3_PUEN_P3_VAL(val) (((val) & 0x1) << 3) -+#define PORT_P3_PUEN_P3_GET(val) ((((val) & PORT_P3_PUEN_P3) >> 3) & 0x1) -+#define PORT_P3_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P3) | (((val) & 0x1) << 3)) -+/* Pull Up Device Enable at Port 3 Bit # (2) */ -+#define PORT_P3_PUEN_P2 (0x1 << 2) -+#define PORT_P3_PUEN_P2_VAL(val) (((val) & 0x1) << 2) -+#define PORT_P3_PUEN_P2_GET(val) ((((val) & PORT_P3_PUEN_P2) >> 2) & 0x1) -+#define PORT_P3_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P2) | (((val) & 0x1) << 2)) -+/* Pull Up Device Enable at Port 3 Bit # (1) */ -+#define PORT_P3_PUEN_P1 (0x1 << 1) -+#define PORT_P3_PUEN_P1_VAL(val) (((val) & 0x1) << 1) -+#define PORT_P3_PUEN_P1_GET(val) ((((val) & PORT_P3_PUEN_P1) >> 1) & 0x1) -+#define PORT_P3_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P1) | (((val) & 0x1) << 1)) -+/* Pull Up Device Enable at Port 3 Bit # (0) */ -+#define PORT_P3_PUEN_P0 (0x1) -+#define PORT_P3_PUEN_P0_VAL(val) (((val) & 0x1) << 0) -+#define PORT_P3_PUEN_P0_GET(val) ((((val) & PORT_P3_PUEN_P0) >> 0) & 0x1) -+#define PORT_P3_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P0) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Port 4 Data Output Register -+ ******************************************************************************/ -+ -+/* Port 4 Pin # Output Value (23) */ -+#define PORT_P4_OUT_P23 (0x1 << 23) -+#define PORT_P4_OUT_P23_VAL(val) (((val) & 0x1) << 23) -+#define PORT_P4_OUT_P23_GET(val) ((((val) & PORT_P4_OUT_P23) >> 23) & 0x1) -+#define PORT_P4_OUT_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P23) | (((val) & 0x1) << 23)) -+/* Port 4 Pin # Output Value (22) */ -+#define PORT_P4_OUT_P22 (0x1 << 22) -+#define PORT_P4_OUT_P22_VAL(val) (((val) & 0x1) << 22) -+#define PORT_P4_OUT_P22_GET(val) ((((val) & PORT_P4_OUT_P22) >> 22) & 0x1) -+#define PORT_P4_OUT_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P22) | (((val) & 0x1) << 22)) -+/* Port 4 Pin # Output Value (21) */ -+#define PORT_P4_OUT_P21 (0x1 << 21) -+#define PORT_P4_OUT_P21_VAL(val) (((val) & 0x1) << 21) -+#define PORT_P4_OUT_P21_GET(val) ((((val) & PORT_P4_OUT_P21) >> 21) & 0x1) -+#define PORT_P4_OUT_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P21) | (((val) & 0x1) << 21)) -+/* Port 4 Pin # Output Value (20) */ -+#define PORT_P4_OUT_P20 (0x1 << 20) -+#define PORT_P4_OUT_P20_VAL(val) (((val) & 0x1) << 20) -+#define PORT_P4_OUT_P20_GET(val) ((((val) & PORT_P4_OUT_P20) >> 20) & 0x1) -+#define PORT_P4_OUT_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P20) | (((val) & 0x1) << 20)) -+/* Port 4 Pin # Output Value (19) */ -+#define PORT_P4_OUT_P19 (0x1 << 19) -+#define PORT_P4_OUT_P19_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P4_OUT_P19_GET(val) ((((val) & PORT_P4_OUT_P19) >> 19) & 0x1) -+#define PORT_P4_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P19) | (((val) & 0x1) << 19)) -+/* Port 4 Pin # Output Value (18) */ -+#define PORT_P4_OUT_P18 (0x1 << 18) -+#define PORT_P4_OUT_P18_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P4_OUT_P18_GET(val) ((((val) & PORT_P4_OUT_P18) >> 18) & 0x1) -+#define PORT_P4_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P18) | (((val) & 0x1) << 18)) -+/* Port 4 Pin # Output Value (17) */ -+#define PORT_P4_OUT_P17 (0x1 << 17) -+#define PORT_P4_OUT_P17_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P4_OUT_P17_GET(val) ((((val) & PORT_P4_OUT_P17) >> 17) & 0x1) -+#define PORT_P4_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P17) | (((val) & 0x1) << 17)) -+/* Port 4 Pin # Output Value (16) */ -+#define PORT_P4_OUT_P16 (0x1 << 16) -+#define PORT_P4_OUT_P16_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P4_OUT_P16_GET(val) ((((val) & PORT_P4_OUT_P16) >> 16) & 0x1) -+#define PORT_P4_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P16) | (((val) & 0x1) << 16)) -+/* Port 4 Pin # Output Value (15) */ -+#define PORT_P4_OUT_P15 (0x1 << 15) -+#define PORT_P4_OUT_P15_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P4_OUT_P15_GET(val) ((((val) & PORT_P4_OUT_P15) >> 15) & 0x1) -+#define PORT_P4_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P15) | (((val) & 0x1) << 15)) -+/* Port 4 Pin # Output Value (14) */ -+#define PORT_P4_OUT_P14 (0x1 << 14) -+#define PORT_P4_OUT_P14_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P4_OUT_P14_GET(val) ((((val) & PORT_P4_OUT_P14) >> 14) & 0x1) -+#define PORT_P4_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P14) | (((val) & 0x1) << 14)) -+/* Port 4 Pin # Output Value (13) */ -+#define PORT_P4_OUT_P13 (0x1 << 13) -+#define PORT_P4_OUT_P13_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P4_OUT_P13_GET(val) ((((val) & PORT_P4_OUT_P13) >> 13) & 0x1) -+#define PORT_P4_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P13) | (((val) & 0x1) << 13)) -+/* Port 4 Pin # Output Value (12) */ -+#define PORT_P4_OUT_P12 (0x1 << 12) -+#define PORT_P4_OUT_P12_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P4_OUT_P12_GET(val) ((((val) & PORT_P4_OUT_P12) >> 12) & 0x1) -+#define PORT_P4_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P12) | (((val) & 0x1) << 12)) -+/* Port 4 Pin # Output Value (11) */ -+#define PORT_P4_OUT_P11 (0x1 << 11) -+#define PORT_P4_OUT_P11_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P4_OUT_P11_GET(val) ((((val) & PORT_P4_OUT_P11) >> 11) & 0x1) -+#define PORT_P4_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P11) | (((val) & 0x1) << 11)) -+/* Port 4 Pin # Output Value (10) */ -+#define PORT_P4_OUT_P10 (0x1 << 10) -+#define PORT_P4_OUT_P10_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P4_OUT_P10_GET(val) ((((val) & PORT_P4_OUT_P10) >> 10) & 0x1) -+#define PORT_P4_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P10) | (((val) & 0x1) << 10)) -+/* Port 4 Pin # Output Value (9) */ -+#define PORT_P4_OUT_P9 (0x1 << 9) -+#define PORT_P4_OUT_P9_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P4_OUT_P9_GET(val) ((((val) & PORT_P4_OUT_P9) >> 9) & 0x1) -+#define PORT_P4_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P9) | (((val) & 0x1) << 9)) -+/* Port 4 Pin # Output Value (8) */ -+#define PORT_P4_OUT_P8 (0x1 << 8) -+#define PORT_P4_OUT_P8_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P4_OUT_P8_GET(val) ((((val) & PORT_P4_OUT_P8) >> 8) & 0x1) -+#define PORT_P4_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P8) | (((val) & 0x1) << 8)) -+/* Port 4 Pin # Output Value (7) */ -+#define PORT_P4_OUT_P7 (0x1 << 7) -+#define PORT_P4_OUT_P7_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P4_OUT_P7_GET(val) ((((val) & PORT_P4_OUT_P7) >> 7) & 0x1) -+#define PORT_P4_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P7) | (((val) & 0x1) << 7)) -+/* Port 4 Pin # Output Value (6) */ -+#define PORT_P4_OUT_P6 (0x1 << 6) -+#define PORT_P4_OUT_P6_VAL(val) (((val) & 0x1) << 6) -+#define PORT_P4_OUT_P6_GET(val) ((((val) & PORT_P4_OUT_P6) >> 6) & 0x1) -+#define PORT_P4_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P6) | (((val) & 0x1) << 6)) -+/* Port 4 Pin # Output Value (5) */ -+#define PORT_P4_OUT_P5 (0x1 << 5) -+#define PORT_P4_OUT_P5_VAL(val) (((val) & 0x1) << 5) -+#define PORT_P4_OUT_P5_GET(val) ((((val) & PORT_P4_OUT_P5) >> 5) & 0x1) -+#define PORT_P4_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P5) | (((val) & 0x1) << 5)) -+/* Port 4 Pin # Output Value (4) */ -+#define PORT_P4_OUT_P4 (0x1 << 4) -+#define PORT_P4_OUT_P4_VAL(val) (((val) & 0x1) << 4) -+#define PORT_P4_OUT_P4_GET(val) ((((val) & PORT_P4_OUT_P4) >> 4) & 0x1) -+#define PORT_P4_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P4) | (((val) & 0x1) << 4)) -+/* Port 4 Pin # Output Value (3) */ -+#define PORT_P4_OUT_P3 (0x1 << 3) -+#define PORT_P4_OUT_P3_VAL(val) (((val) & 0x1) << 3) -+#define PORT_P4_OUT_P3_GET(val) ((((val) & PORT_P4_OUT_P3) >> 3) & 0x1) -+#define PORT_P4_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P3) | (((val) & 0x1) << 3)) -+/* Port 4 Pin # Output Value (2) */ -+#define PORT_P4_OUT_P2 (0x1 << 2) -+#define PORT_P4_OUT_P2_VAL(val) (((val) & 0x1) << 2) -+#define PORT_P4_OUT_P2_GET(val) ((((val) & PORT_P4_OUT_P2) >> 2) & 0x1) -+#define PORT_P4_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P2) | (((val) & 0x1) << 2)) -+/* Port 4 Pin # Output Value (1) */ -+#define PORT_P4_OUT_P1 (0x1 << 1) -+#define PORT_P4_OUT_P1_VAL(val) (((val) & 0x1) << 1) -+#define PORT_P4_OUT_P1_GET(val) ((((val) & PORT_P4_OUT_P1) >> 1) & 0x1) -+#define PORT_P4_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P1) | (((val) & 0x1) << 1)) -+/* Port 4 Pin # Output Value (0) */ -+#define PORT_P4_OUT_P0 (0x1) -+#define PORT_P4_OUT_P0_VAL(val) (((val) & 0x1) << 0) -+#define PORT_P4_OUT_P0_GET(val) ((((val) & PORT_P4_OUT_P0) >> 0) & 0x1) -+#define PORT_P4_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P0) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Port 4 Data Input Register -+ ******************************************************************************/ -+ -+/* Port 4 Pin # Latched Input Value (23) */ -+#define PORT_P4_IN_P23 (0x1 << 23) -+#define PORT_P4_IN_P23_GET(val) ((((val) & PORT_P4_IN_P23) >> 23) & 0x1) -+/* Port 4 Pin # Latched Input Value (22) */ -+#define PORT_P4_IN_P22 (0x1 << 22) -+#define PORT_P4_IN_P22_GET(val) ((((val) & PORT_P4_IN_P22) >> 22) & 0x1) -+/* Port 4 Pin # Latched Input Value (21) */ -+#define PORT_P4_IN_P21 (0x1 << 21) -+#define PORT_P4_IN_P21_GET(val) ((((val) & PORT_P4_IN_P21) >> 21) & 0x1) -+/* Port 4 Pin # Latched Input Value (20) */ -+#define PORT_P4_IN_P20 (0x1 << 20) -+#define PORT_P4_IN_P20_GET(val) ((((val) & PORT_P4_IN_P20) >> 20) & 0x1) -+/* Port 4 Pin # Latched Input Value (19) */ -+#define PORT_P4_IN_P19 (0x1 << 19) -+#define PORT_P4_IN_P19_GET(val) ((((val) & PORT_P4_IN_P19) >> 19) & 0x1) -+/* Port 4 Pin # Latched Input Value (18) */ -+#define PORT_P4_IN_P18 (0x1 << 18) -+#define PORT_P4_IN_P18_GET(val) ((((val) & PORT_P4_IN_P18) >> 18) & 0x1) -+/* Port 4 Pin # Latched Input Value (17) */ -+#define PORT_P4_IN_P17 (0x1 << 17) -+#define PORT_P4_IN_P17_GET(val) ((((val) & PORT_P4_IN_P17) >> 17) & 0x1) -+/* Port 4 Pin # Latched Input Value (16) */ -+#define PORT_P4_IN_P16 (0x1 << 16) -+#define PORT_P4_IN_P16_GET(val) ((((val) & PORT_P4_IN_P16) >> 16) & 0x1) -+/* Port 4 Pin # Latched Input Value (15) */ -+#define PORT_P4_IN_P15 (0x1 << 15) -+#define PORT_P4_IN_P15_GET(val) ((((val) & PORT_P4_IN_P15) >> 15) & 0x1) -+/* Port 4 Pin # Latched Input Value (14) */ -+#define PORT_P4_IN_P14 (0x1 << 14) -+#define PORT_P4_IN_P14_GET(val) ((((val) & PORT_P4_IN_P14) >> 14) & 0x1) -+/* Port 4 Pin # Latched Input Value (13) */ -+#define PORT_P4_IN_P13 (0x1 << 13) -+#define PORT_P4_IN_P13_GET(val) ((((val) & PORT_P4_IN_P13) >> 13) & 0x1) -+/* Port 4 Pin # Latched Input Value (12) */ -+#define PORT_P4_IN_P12 (0x1 << 12) -+#define PORT_P4_IN_P12_GET(val) ((((val) & PORT_P4_IN_P12) >> 12) & 0x1) -+/* Port 4 Pin # Latched Input Value (11) */ -+#define PORT_P4_IN_P11 (0x1 << 11) -+#define PORT_P4_IN_P11_GET(val) ((((val) & PORT_P4_IN_P11) >> 11) & 0x1) -+/* Port 4 Pin # Latched Input Value (10) */ -+#define PORT_P4_IN_P10 (0x1 << 10) -+#define PORT_P4_IN_P10_GET(val) ((((val) & PORT_P4_IN_P10) >> 10) & 0x1) -+/* Port 4 Pin # Latched Input Value (9) */ -+#define PORT_P4_IN_P9 (0x1 << 9) -+#define PORT_P4_IN_P9_GET(val) ((((val) & PORT_P4_IN_P9) >> 9) & 0x1) -+/* Port 4 Pin # Latched Input Value (8) */ -+#define PORT_P4_IN_P8 (0x1 << 8) -+#define PORT_P4_IN_P8_GET(val) ((((val) & PORT_P4_IN_P8) >> 8) & 0x1) -+/* Port 4 Pin # Latched Input Value (7) */ -+#define PORT_P4_IN_P7 (0x1 << 7) -+#define PORT_P4_IN_P7_GET(val) ((((val) & PORT_P4_IN_P7) >> 7) & 0x1) -+/* Port 4 Pin # Latched Input Value (6) */ -+#define PORT_P4_IN_P6 (0x1 << 6) -+#define PORT_P4_IN_P6_GET(val) ((((val) & PORT_P4_IN_P6) >> 6) & 0x1) -+/* Port 4 Pin # Latched Input Value (5) */ -+#define PORT_P4_IN_P5 (0x1 << 5) -+#define PORT_P4_IN_P5_GET(val) ((((val) & PORT_P4_IN_P5) >> 5) & 0x1) -+/* Port 4 Pin # Latched Input Value (4) */ -+#define PORT_P4_IN_P4 (0x1 << 4) -+#define PORT_P4_IN_P4_GET(val) ((((val) & PORT_P4_IN_P4) >> 4) & 0x1) -+/* Port 4 Pin # Latched Input Value (3) */ -+#define PORT_P4_IN_P3 (0x1 << 3) -+#define PORT_P4_IN_P3_GET(val) ((((val) & PORT_P4_IN_P3) >> 3) & 0x1) -+/* Port 4 Pin # Latched Input Value (2) */ -+#define PORT_P4_IN_P2 (0x1 << 2) -+#define PORT_P4_IN_P2_GET(val) ((((val) & PORT_P4_IN_P2) >> 2) & 0x1) -+/* Port 4 Pin # Latched Input Value (1) */ -+#define PORT_P4_IN_P1 (0x1 << 1) -+#define PORT_P4_IN_P1_GET(val) ((((val) & PORT_P4_IN_P1) >> 1) & 0x1) -+/* Port 4 Pin # Latched Input Value (0) */ -+#define PORT_P4_IN_P0 (0x1) -+#define PORT_P4_IN_P0_GET(val) ((((val) & PORT_P4_IN_P0) >> 0) & 0x1) -+ -+/******************************************************************************* -+ * Port 4 Direction Register -+ ******************************************************************************/ -+ -+/* Port 4 Pin #Direction Control (23) */ -+#define PORT_P4_DIR_P23 (0x1 << 23) -+#define PORT_P4_DIR_P23_VAL(val) (((val) & 0x1) << 23) -+#define PORT_P4_DIR_P23_GET(val) ((((val) & PORT_P4_DIR_P23) >> 23) & 0x1) -+#define PORT_P4_DIR_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P23) | (((val) & 0x1) << 23)) -+/* Port 4 Pin #Direction Control (22) */ -+#define PORT_P4_DIR_P22 (0x1 << 22) -+#define PORT_P4_DIR_P22_VAL(val) (((val) & 0x1) << 22) -+#define PORT_P4_DIR_P22_GET(val) ((((val) & PORT_P4_DIR_P22) >> 22) & 0x1) -+#define PORT_P4_DIR_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P22) | (((val) & 0x1) << 22)) -+/* Port 4 Pin #Direction Control (21) */ -+#define PORT_P4_DIR_P21 (0x1 << 21) -+#define PORT_P4_DIR_P21_VAL(val) (((val) & 0x1) << 21) -+#define PORT_P4_DIR_P21_GET(val) ((((val) & PORT_P4_DIR_P21) >> 21) & 0x1) -+#define PORT_P4_DIR_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P21) | (((val) & 0x1) << 21)) -+/* Port 4 Pin #Direction Control (20) */ -+#define PORT_P4_DIR_P20 (0x1 << 20) -+#define PORT_P4_DIR_P20_VAL(val) (((val) & 0x1) << 20) -+#define PORT_P4_DIR_P20_GET(val) ((((val) & PORT_P4_DIR_P20) >> 20) & 0x1) -+#define PORT_P4_DIR_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P20) | (((val) & 0x1) << 20)) -+/* Port 4 Pin #Direction Control (19) */ -+#define PORT_P4_DIR_P19 (0x1 << 19) -+#define PORT_P4_DIR_P19_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P4_DIR_P19_GET(val) ((((val) & PORT_P4_DIR_P19) >> 19) & 0x1) -+#define PORT_P4_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P19) | (((val) & 0x1) << 19)) -+/* Port 4 Pin #Direction Control (18) */ -+#define PORT_P4_DIR_P18 (0x1 << 18) -+#define PORT_P4_DIR_P18_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P4_DIR_P18_GET(val) ((((val) & PORT_P4_DIR_P18) >> 18) & 0x1) -+#define PORT_P4_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P18) | (((val) & 0x1) << 18)) -+/* Port 4 Pin #Direction Control (17) */ -+#define PORT_P4_DIR_P17 (0x1 << 17) -+#define PORT_P4_DIR_P17_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P4_DIR_P17_GET(val) ((((val) & PORT_P4_DIR_P17) >> 17) & 0x1) -+#define PORT_P4_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P17) | (((val) & 0x1) << 17)) -+/* Port 4 Pin #Direction Control (16) */ -+#define PORT_P4_DIR_P16 (0x1 << 16) -+#define PORT_P4_DIR_P16_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P4_DIR_P16_GET(val) ((((val) & PORT_P4_DIR_P16) >> 16) & 0x1) -+#define PORT_P4_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P16) | (((val) & 0x1) << 16)) -+/* Port 4 Pin #Direction Control (15) */ -+#define PORT_P4_DIR_P15 (0x1 << 15) -+#define PORT_P4_DIR_P15_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P4_DIR_P15_GET(val) ((((val) & PORT_P4_DIR_P15) >> 15) & 0x1) -+#define PORT_P4_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P15) | (((val) & 0x1) << 15)) -+/* Port 4 Pin #Direction Control (14) */ -+#define PORT_P4_DIR_P14 (0x1 << 14) -+#define PORT_P4_DIR_P14_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P4_DIR_P14_GET(val) ((((val) & PORT_P4_DIR_P14) >> 14) & 0x1) -+#define PORT_P4_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P14) | (((val) & 0x1) << 14)) -+/* Port 4 Pin #Direction Control (13) */ -+#define PORT_P4_DIR_P13 (0x1 << 13) -+#define PORT_P4_DIR_P13_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P4_DIR_P13_GET(val) ((((val) & PORT_P4_DIR_P13) >> 13) & 0x1) -+#define PORT_P4_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P13) | (((val) & 0x1) << 13)) -+/* Port 4 Pin #Direction Control (12) */ -+#define PORT_P4_DIR_P12 (0x1 << 12) -+#define PORT_P4_DIR_P12_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P4_DIR_P12_GET(val) ((((val) & PORT_P4_DIR_P12) >> 12) & 0x1) -+#define PORT_P4_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P12) | (((val) & 0x1) << 12)) -+/* Port 4 Pin #Direction Control (11) */ -+#define PORT_P4_DIR_P11 (0x1 << 11) -+#define PORT_P4_DIR_P11_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P4_DIR_P11_GET(val) ((((val) & PORT_P4_DIR_P11) >> 11) & 0x1) -+#define PORT_P4_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P11) | (((val) & 0x1) << 11)) -+/* Port 4 Pin #Direction Control (10) */ -+#define PORT_P4_DIR_P10 (0x1 << 10) -+#define PORT_P4_DIR_P10_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P4_DIR_P10_GET(val) ((((val) & PORT_P4_DIR_P10) >> 10) & 0x1) -+#define PORT_P4_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P10) | (((val) & 0x1) << 10)) -+/* Port 4 Pin #Direction Control (9) */ -+#define PORT_P4_DIR_P9 (0x1 << 9) -+#define PORT_P4_DIR_P9_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P4_DIR_P9_GET(val) ((((val) & PORT_P4_DIR_P9) >> 9) & 0x1) -+#define PORT_P4_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P9) | (((val) & 0x1) << 9)) -+/* Port 4 Pin #Direction Control (8) */ -+#define PORT_P4_DIR_P8 (0x1 << 8) -+#define PORT_P4_DIR_P8_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P4_DIR_P8_GET(val) ((((val) & PORT_P4_DIR_P8) >> 8) & 0x1) -+#define PORT_P4_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P8) | (((val) & 0x1) << 8)) -+/* Port 4 Pin #Direction Control (7) */ -+#define PORT_P4_DIR_P7 (0x1 << 7) -+#define PORT_P4_DIR_P7_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P4_DIR_P7_GET(val) ((((val) & PORT_P4_DIR_P7) >> 7) & 0x1) -+#define PORT_P4_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P7) | (((val) & 0x1) << 7)) -+/* Port 4 Pin #Direction Control (6) */ -+#define PORT_P4_DIR_P6 (0x1 << 6) -+#define PORT_P4_DIR_P6_VAL(val) (((val) & 0x1) << 6) -+#define PORT_P4_DIR_P6_GET(val) ((((val) & PORT_P4_DIR_P6) >> 6) & 0x1) -+#define PORT_P4_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P6) | (((val) & 0x1) << 6)) -+/* Port 4 Pin #Direction Control (5) */ -+#define PORT_P4_DIR_P5 (0x1 << 5) -+#define PORT_P4_DIR_P5_VAL(val) (((val) & 0x1) << 5) -+#define PORT_P4_DIR_P5_GET(val) ((((val) & PORT_P4_DIR_P5) >> 5) & 0x1) -+#define PORT_P4_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P5) | (((val) & 0x1) << 5)) -+/* Port 4 Pin #Direction Control (4) */ -+#define PORT_P4_DIR_P4 (0x1 << 4) -+#define PORT_P4_DIR_P4_VAL(val) (((val) & 0x1) << 4) -+#define PORT_P4_DIR_P4_GET(val) ((((val) & PORT_P4_DIR_P4) >> 4) & 0x1) -+#define PORT_P4_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P4) | (((val) & 0x1) << 4)) -+/* Port 4 Pin #Direction Control (3) */ -+#define PORT_P4_DIR_P3 (0x1 << 3) -+#define PORT_P4_DIR_P3_VAL(val) (((val) & 0x1) << 3) -+#define PORT_P4_DIR_P3_GET(val) ((((val) & PORT_P4_DIR_P3) >> 3) & 0x1) -+#define PORT_P4_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P3) | (((val) & 0x1) << 3)) -+/* Port 4 Pin #Direction Control (2) */ -+#define PORT_P4_DIR_P2 (0x1 << 2) -+#define PORT_P4_DIR_P2_VAL(val) (((val) & 0x1) << 2) -+#define PORT_P4_DIR_P2_GET(val) ((((val) & PORT_P4_DIR_P2) >> 2) & 0x1) -+#define PORT_P4_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P2) | (((val) & 0x1) << 2)) -+/* Port 4 Pin #Direction Control (1) */ -+#define PORT_P4_DIR_P1 (0x1 << 1) -+#define PORT_P4_DIR_P1_VAL(val) (((val) & 0x1) << 1) -+#define PORT_P4_DIR_P1_GET(val) ((((val) & PORT_P4_DIR_P1) >> 1) & 0x1) -+#define PORT_P4_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P1) | (((val) & 0x1) << 1)) -+/* Port 4 Pin #Direction Control (0) */ -+#define PORT_P4_DIR_P0 (0x1) -+#define PORT_P4_DIR_P0_VAL(val) (((val) & 0x1) << 0) -+#define PORT_P4_DIR_P0_GET(val) ((((val) & PORT_P4_DIR_P0) >> 0) & 0x1) -+#define PORT_P4_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P0) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Port 4 Alternate Function Select Register 0 -+ ******************************************************************************/ -+ -+/* Alternate Function at Port 4 Bit # (23) */ -+#define PORT_P4_ALTSEL0_P23 (0x1 << 23) -+#define PORT_P4_ALTSEL0_P23_VAL(val) (((val) & 0x1) << 23) -+#define PORT_P4_ALTSEL0_P23_GET(val) ((((val) & PORT_P4_ALTSEL0_P23) >> 23) & 0x1) -+#define PORT_P4_ALTSEL0_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P23) | (((val) & 0x1) << 23)) -+/* Alternate Function at Port 4 Bit # (22) */ -+#define PORT_P4_ALTSEL0_P22 (0x1 << 22) -+#define PORT_P4_ALTSEL0_P22_VAL(val) (((val) & 0x1) << 22) -+#define PORT_P4_ALTSEL0_P22_GET(val) ((((val) & PORT_P4_ALTSEL0_P22) >> 22) & 0x1) -+#define PORT_P4_ALTSEL0_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P22) | (((val) & 0x1) << 22)) -+/* Alternate Function at Port 4 Bit # (21) */ -+#define PORT_P4_ALTSEL0_P21 (0x1 << 21) -+#define PORT_P4_ALTSEL0_P21_VAL(val) (((val) & 0x1) << 21) -+#define PORT_P4_ALTSEL0_P21_GET(val) ((((val) & PORT_P4_ALTSEL0_P21) >> 21) & 0x1) -+#define PORT_P4_ALTSEL0_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P21) | (((val) & 0x1) << 21)) -+/* Alternate Function at Port 4 Bit # (20) */ -+#define PORT_P4_ALTSEL0_P20 (0x1 << 20) -+#define PORT_P4_ALTSEL0_P20_VAL(val) (((val) & 0x1) << 20) -+#define PORT_P4_ALTSEL0_P20_GET(val) ((((val) & PORT_P4_ALTSEL0_P20) >> 20) & 0x1) -+#define PORT_P4_ALTSEL0_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P20) | (((val) & 0x1) << 20)) -+/* Alternate Function at Port 4 Bit # (19) */ -+#define PORT_P4_ALTSEL0_P19 (0x1 << 19) -+#define PORT_P4_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P4_ALTSEL0_P19_GET(val) ((((val) & PORT_P4_ALTSEL0_P19) >> 19) & 0x1) -+#define PORT_P4_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P19) | (((val) & 0x1) << 19)) -+/* Alternate Function at Port 4 Bit # (18) */ -+#define PORT_P4_ALTSEL0_P18 (0x1 << 18) -+#define PORT_P4_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P4_ALTSEL0_P18_GET(val) ((((val) & PORT_P4_ALTSEL0_P18) >> 18) & 0x1) -+#define PORT_P4_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P18) | (((val) & 0x1) << 18)) -+/* Alternate Function at Port 4 Bit # (17) */ -+#define PORT_P4_ALTSEL0_P17 (0x1 << 17) -+#define PORT_P4_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P4_ALTSEL0_P17_GET(val) ((((val) & PORT_P4_ALTSEL0_P17) >> 17) & 0x1) -+#define PORT_P4_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P17) | (((val) & 0x1) << 17)) -+/* Alternate Function at Port 4 Bit # (16) */ -+#define PORT_P4_ALTSEL0_P16 (0x1 << 16) -+#define PORT_P4_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P4_ALTSEL0_P16_GET(val) ((((val) & PORT_P4_ALTSEL0_P16) >> 16) & 0x1) -+#define PORT_P4_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P16) | (((val) & 0x1) << 16)) -+/* Alternate Function at Port 4 Bit # (15) */ -+#define PORT_P4_ALTSEL0_P15 (0x1 << 15) -+#define PORT_P4_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P4_ALTSEL0_P15_GET(val) ((((val) & PORT_P4_ALTSEL0_P15) >> 15) & 0x1) -+#define PORT_P4_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P15) | (((val) & 0x1) << 15)) -+/* Alternate Function at Port 4 Bit # (14) */ -+#define PORT_P4_ALTSEL0_P14 (0x1 << 14) -+#define PORT_P4_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P4_ALTSEL0_P14_GET(val) ((((val) & PORT_P4_ALTSEL0_P14) >> 14) & 0x1) -+#define PORT_P4_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P14) | (((val) & 0x1) << 14)) -+/* Alternate Function at Port 4 Bit # (13) */ -+#define PORT_P4_ALTSEL0_P13 (0x1 << 13) -+#define PORT_P4_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P4_ALTSEL0_P13_GET(val) ((((val) & PORT_P4_ALTSEL0_P13) >> 13) & 0x1) -+#define PORT_P4_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P13) | (((val) & 0x1) << 13)) -+/* Alternate Function at Port 4 Bit # (12) */ -+#define PORT_P4_ALTSEL0_P12 (0x1 << 12) -+#define PORT_P4_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P4_ALTSEL0_P12_GET(val) ((((val) & PORT_P4_ALTSEL0_P12) >> 12) & 0x1) -+#define PORT_P4_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P12) | (((val) & 0x1) << 12)) -+/* Alternate Function at Port 4 Bit # (11) */ -+#define PORT_P4_ALTSEL0_P11 (0x1 << 11) -+#define PORT_P4_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P4_ALTSEL0_P11_GET(val) ((((val) & PORT_P4_ALTSEL0_P11) >> 11) & 0x1) -+#define PORT_P4_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P11) | (((val) & 0x1) << 11)) -+/* Alternate Function at Port 4 Bit # (10) */ -+#define PORT_P4_ALTSEL0_P10 (0x1 << 10) -+#define PORT_P4_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P4_ALTSEL0_P10_GET(val) ((((val) & PORT_P4_ALTSEL0_P10) >> 10) & 0x1) -+#define PORT_P4_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P10) | (((val) & 0x1) << 10)) -+/* Alternate Function at Port 4 Bit # (9) */ -+#define PORT_P4_ALTSEL0_P9 (0x1 << 9) -+#define PORT_P4_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P4_ALTSEL0_P9_GET(val) ((((val) & PORT_P4_ALTSEL0_P9) >> 9) & 0x1) -+#define PORT_P4_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P9) | (((val) & 0x1) << 9)) -+/* Alternate Function at Port 4 Bit # (8) */ -+#define PORT_P4_ALTSEL0_P8 (0x1 << 8) -+#define PORT_P4_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P4_ALTSEL0_P8_GET(val) ((((val) & PORT_P4_ALTSEL0_P8) >> 8) & 0x1) -+#define PORT_P4_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P8) | (((val) & 0x1) << 8)) -+/* Alternate Function at Port 4 Bit # (7) */ -+#define PORT_P4_ALTSEL0_P7 (0x1 << 7) -+#define PORT_P4_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P4_ALTSEL0_P7_GET(val) ((((val) & PORT_P4_ALTSEL0_P7) >> 7) & 0x1) -+#define PORT_P4_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P7) | (((val) & 0x1) << 7)) -+/* Alternate Function at Port 4 Bit # (6) */ -+#define PORT_P4_ALTSEL0_P6 (0x1 << 6) -+#define PORT_P4_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) -+#define PORT_P4_ALTSEL0_P6_GET(val) ((((val) & PORT_P4_ALTSEL0_P6) >> 6) & 0x1) -+#define PORT_P4_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P6) | (((val) & 0x1) << 6)) -+/* Alternate Function at Port 4 Bit # (5) */ -+#define PORT_P4_ALTSEL0_P5 (0x1 << 5) -+#define PORT_P4_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) -+#define PORT_P4_ALTSEL0_P5_GET(val) ((((val) & PORT_P4_ALTSEL0_P5) >> 5) & 0x1) -+#define PORT_P4_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P5) | (((val) & 0x1) << 5)) -+/* Alternate Function at Port 4 Bit # (4) */ -+#define PORT_P4_ALTSEL0_P4 (0x1 << 4) -+#define PORT_P4_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) -+#define PORT_P4_ALTSEL0_P4_GET(val) ((((val) & PORT_P4_ALTSEL0_P4) >> 4) & 0x1) -+#define PORT_P4_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P4) | (((val) & 0x1) << 4)) -+/* Alternate Function at Port 4 Bit # (3) */ -+#define PORT_P4_ALTSEL0_P3 (0x1 << 3) -+#define PORT_P4_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) -+#define PORT_P4_ALTSEL0_P3_GET(val) ((((val) & PORT_P4_ALTSEL0_P3) >> 3) & 0x1) -+#define PORT_P4_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P3) | (((val) & 0x1) << 3)) -+/* Alternate Function at Port 4 Bit # (2) */ -+#define PORT_P4_ALTSEL0_P2 (0x1 << 2) -+#define PORT_P4_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) -+#define PORT_P4_ALTSEL0_P2_GET(val) ((((val) & PORT_P4_ALTSEL0_P2) >> 2) & 0x1) -+#define PORT_P4_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P2) | (((val) & 0x1) << 2)) -+/* Alternate Function at Port 4 Bit # (1) */ -+#define PORT_P4_ALTSEL0_P1 (0x1 << 1) -+#define PORT_P4_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) -+#define PORT_P4_ALTSEL0_P1_GET(val) ((((val) & PORT_P4_ALTSEL0_P1) >> 1) & 0x1) -+#define PORT_P4_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P1) | (((val) & 0x1) << 1)) -+/* Alternate Function at Port 4 Bit # (0) */ -+#define PORT_P4_ALTSEL0_P0 (0x1) -+#define PORT_P4_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) -+#define PORT_P4_ALTSEL0_P0_GET(val) ((((val) & PORT_P4_ALTSEL0_P0) >> 0) & 0x1) -+#define PORT_P4_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P0) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * Port 4 Pull Up Device Enable Register -+ ******************************************************************************/ -+ -+/* Pull Up Device Enable at Port 4 Bit # (23) */ -+#define PORT_P4_PUEN_P23 (0x1 << 23) -+#define PORT_P4_PUEN_P23_VAL(val) (((val) & 0x1) << 23) -+#define PORT_P4_PUEN_P23_GET(val) ((((val) & PORT_P4_PUEN_P23) >> 23) & 0x1) -+#define PORT_P4_PUEN_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P23) | (((val) & 0x1) << 23)) -+/* Pull Up Device Enable at Port 4 Bit # (22) */ -+#define PORT_P4_PUEN_P22 (0x1 << 22) -+#define PORT_P4_PUEN_P22_VAL(val) (((val) & 0x1) << 22) -+#define PORT_P4_PUEN_P22_GET(val) ((((val) & PORT_P4_PUEN_P22) >> 22) & 0x1) -+#define PORT_P4_PUEN_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P22) | (((val) & 0x1) << 22)) -+/* Pull Up Device Enable at Port 4 Bit # (21) */ -+#define PORT_P4_PUEN_P21 (0x1 << 21) -+#define PORT_P4_PUEN_P21_VAL(val) (((val) & 0x1) << 21) -+#define PORT_P4_PUEN_P21_GET(val) ((((val) & PORT_P4_PUEN_P21) >> 21) & 0x1) -+#define PORT_P4_PUEN_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P21) | (((val) & 0x1) << 21)) -+/* Pull Up Device Enable at Port 4 Bit # (20) */ -+#define PORT_P4_PUEN_P20 (0x1 << 20) -+#define PORT_P4_PUEN_P20_VAL(val) (((val) & 0x1) << 20) -+#define PORT_P4_PUEN_P20_GET(val) ((((val) & PORT_P4_PUEN_P20) >> 20) & 0x1) -+#define PORT_P4_PUEN_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P20) | (((val) & 0x1) << 20)) -+/* Pull Up Device Enable at Port 4 Bit # (19) */ -+#define PORT_P4_PUEN_P19 (0x1 << 19) -+#define PORT_P4_PUEN_P19_VAL(val) (((val) & 0x1) << 19) -+#define PORT_P4_PUEN_P19_GET(val) ((((val) & PORT_P4_PUEN_P19) >> 19) & 0x1) -+#define PORT_P4_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P19) | (((val) & 0x1) << 19)) -+/* Pull Up Device Enable at Port 4 Bit # (18) */ -+#define PORT_P4_PUEN_P18 (0x1 << 18) -+#define PORT_P4_PUEN_P18_VAL(val) (((val) & 0x1) << 18) -+#define PORT_P4_PUEN_P18_GET(val) ((((val) & PORT_P4_PUEN_P18) >> 18) & 0x1) -+#define PORT_P4_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P18) | (((val) & 0x1) << 18)) -+/* Pull Up Device Enable at Port 4 Bit # (17) */ -+#define PORT_P4_PUEN_P17 (0x1 << 17) -+#define PORT_P4_PUEN_P17_VAL(val) (((val) & 0x1) << 17) -+#define PORT_P4_PUEN_P17_GET(val) ((((val) & PORT_P4_PUEN_P17) >> 17) & 0x1) -+#define PORT_P4_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P17) | (((val) & 0x1) << 17)) -+/* Pull Up Device Enable at Port 4 Bit # (16) */ -+#define PORT_P4_PUEN_P16 (0x1 << 16) -+#define PORT_P4_PUEN_P16_VAL(val) (((val) & 0x1) << 16) -+#define PORT_P4_PUEN_P16_GET(val) ((((val) & PORT_P4_PUEN_P16) >> 16) & 0x1) -+#define PORT_P4_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P16) | (((val) & 0x1) << 16)) -+/* Pull Up Device Enable at Port 4 Bit # (15) */ -+#define PORT_P4_PUEN_P15 (0x1 << 15) -+#define PORT_P4_PUEN_P15_VAL(val) (((val) & 0x1) << 15) -+#define PORT_P4_PUEN_P15_GET(val) ((((val) & PORT_P4_PUEN_P15) >> 15) & 0x1) -+#define PORT_P4_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P15) | (((val) & 0x1) << 15)) -+/* Pull Up Device Enable at Port 4 Bit # (14) */ -+#define PORT_P4_PUEN_P14 (0x1 << 14) -+#define PORT_P4_PUEN_P14_VAL(val) (((val) & 0x1) << 14) -+#define PORT_P4_PUEN_P14_GET(val) ((((val) & PORT_P4_PUEN_P14) >> 14) & 0x1) -+#define PORT_P4_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P14) | (((val) & 0x1) << 14)) -+/* Pull Up Device Enable at Port 4 Bit # (13) */ -+#define PORT_P4_PUEN_P13 (0x1 << 13) -+#define PORT_P4_PUEN_P13_VAL(val) (((val) & 0x1) << 13) -+#define PORT_P4_PUEN_P13_GET(val) ((((val) & PORT_P4_PUEN_P13) >> 13) & 0x1) -+#define PORT_P4_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P13) | (((val) & 0x1) << 13)) -+/* Pull Up Device Enable at Port 4 Bit # (12) */ -+#define PORT_P4_PUEN_P12 (0x1 << 12) -+#define PORT_P4_PUEN_P12_VAL(val) (((val) & 0x1) << 12) -+#define PORT_P4_PUEN_P12_GET(val) ((((val) & PORT_P4_PUEN_P12) >> 12) & 0x1) -+#define PORT_P4_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P12) | (((val) & 0x1) << 12)) -+/* Pull Up Device Enable at Port 4 Bit # (11) */ -+#define PORT_P4_PUEN_P11 (0x1 << 11) -+#define PORT_P4_PUEN_P11_VAL(val) (((val) & 0x1) << 11) -+#define PORT_P4_PUEN_P11_GET(val) ((((val) & PORT_P4_PUEN_P11) >> 11) & 0x1) -+#define PORT_P4_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P11) | (((val) & 0x1) << 11)) -+/* Pull Up Device Enable at Port 4 Bit # (10) */ -+#define PORT_P4_PUEN_P10 (0x1 << 10) -+#define PORT_P4_PUEN_P10_VAL(val) (((val) & 0x1) << 10) -+#define PORT_P4_PUEN_P10_GET(val) ((((val) & PORT_P4_PUEN_P10) >> 10) & 0x1) -+#define PORT_P4_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P10) | (((val) & 0x1) << 10)) -+/* Pull Up Device Enable at Port 4 Bit # (9) */ -+#define PORT_P4_PUEN_P9 (0x1 << 9) -+#define PORT_P4_PUEN_P9_VAL(val) (((val) & 0x1) << 9) -+#define PORT_P4_PUEN_P9_GET(val) ((((val) & PORT_P4_PUEN_P9) >> 9) & 0x1) -+#define PORT_P4_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P9) | (((val) & 0x1) << 9)) -+/* Pull Up Device Enable at Port 4 Bit # (8) */ -+#define PORT_P4_PUEN_P8 (0x1 << 8) -+#define PORT_P4_PUEN_P8_VAL(val) (((val) & 0x1) << 8) -+#define PORT_P4_PUEN_P8_GET(val) ((((val) & PORT_P4_PUEN_P8) >> 8) & 0x1) -+#define PORT_P4_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P8) | (((val) & 0x1) << 8)) -+/* Pull Up Device Enable at Port 4 Bit # (7) */ -+#define PORT_P4_PUEN_P7 (0x1 << 7) -+#define PORT_P4_PUEN_P7_VAL(val) (((val) & 0x1) << 7) -+#define PORT_P4_PUEN_P7_GET(val) ((((val) & PORT_P4_PUEN_P7) >> 7) & 0x1) -+#define PORT_P4_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P7) | (((val) & 0x1) << 7)) -+/* Pull Up Device Enable at Port 4 Bit # (6) */ -+#define PORT_P4_PUEN_P6 (0x1 << 6) -+#define PORT_P4_PUEN_P6_VAL(val) (((val) & 0x1) << 6) -+#define PORT_P4_PUEN_P6_GET(val) ((((val) & PORT_P4_PUEN_P6) >> 6) & 0x1) -+#define PORT_P4_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P6) | (((val) & 0x1) << 6)) -+/* Pull Up Device Enable at Port 4 Bit # (5) */ -+#define PORT_P4_PUEN_P5 (0x1 << 5) -+#define PORT_P4_PUEN_P5_VAL(val) (((val) & 0x1) << 5) -+#define PORT_P4_PUEN_P5_GET(val) ((((val) & PORT_P4_PUEN_P5) >> 5) & 0x1) -+#define PORT_P4_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P5) | (((val) & 0x1) << 5)) -+/* Pull Up Device Enable at Port 4 Bit # (4) */ -+#define PORT_P4_PUEN_P4 (0x1 << 4) -+#define PORT_P4_PUEN_P4_VAL(val) (((val) & 0x1) << 4) -+#define PORT_P4_PUEN_P4_GET(val) ((((val) & PORT_P4_PUEN_P4) >> 4) & 0x1) -+#define PORT_P4_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P4) | (((val) & 0x1) << 4)) -+/* Pull Up Device Enable at Port 4 Bit # (3) */ -+#define PORT_P4_PUEN_P3 (0x1 << 3) -+#define PORT_P4_PUEN_P3_VAL(val) (((val) & 0x1) << 3) -+#define PORT_P4_PUEN_P3_GET(val) ((((val) & PORT_P4_PUEN_P3) >> 3) & 0x1) -+#define PORT_P4_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P3) | (((val) & 0x1) << 3)) -+/* Pull Up Device Enable at Port 4 Bit # (2) */ -+#define PORT_P4_PUEN_P2 (0x1 << 2) -+#define PORT_P4_PUEN_P2_VAL(val) (((val) & 0x1) << 2) -+#define PORT_P4_PUEN_P2_GET(val) ((((val) & PORT_P4_PUEN_P2) >> 2) & 0x1) -+#define PORT_P4_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P2) | (((val) & 0x1) << 2)) -+/* Pull Up Device Enable at Port 4 Bit # (1) */ -+#define PORT_P4_PUEN_P1 (0x1 << 1) -+#define PORT_P4_PUEN_P1_VAL(val) (((val) & 0x1) << 1) -+#define PORT_P4_PUEN_P1_GET(val) ((((val) & PORT_P4_PUEN_P1) >> 1) & 0x1) -+#define PORT_P4_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P1) | (((val) & 0x1) << 1)) -+/* Pull Up Device Enable at Port 4 Bit # (0) */ -+#define PORT_P4_PUEN_P0 (0x1) -+#define PORT_P4_PUEN_P0_VAL(val) (((val) & 0x1) << 0) -+#define PORT_P4_PUEN_P0_GET(val) ((((val) & PORT_P4_PUEN_P0) >> 0) & 0x1) -+#define PORT_P4_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P0) | (((val) & 0x1) << 0)) -+ -+#endif /* __PORT_H */ -Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/ssc_reg.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/ssc_reg.h 2012-07-31 15:46:02.484476159 +0200 -@@ -0,0 +1,624 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2007 -+ Infineon Technologies AG -+ St. Martin Strasse 53; 81669 Munich, Germany -+ -+ Any use of this Software is subject to the conclusion of a respective -+ License Agreement. Without such a License Agreement no rights to the -+ Software are granted. -+ -+ ******************************************************************************/ -+ -+#ifndef __SSC_REG_H -+#define __SSC_REG_H -+ -+/** SSC register structure */ -+struct svip_reg_ssc { -+ volatile unsigned long clc; /* 0x00 */ -+ volatile unsigned long pisel; /* 0x04 */ -+ volatile unsigned long id; /* 0x08 */ -+ volatile unsigned long reserved0; /* 0x0c */ -+ volatile unsigned long mcon; /* 0x10 */ -+ volatile unsigned long state; /* 0x14 */ -+ volatile unsigned long whbstate; /* 0x18 */ -+ volatile unsigned long reserved1; /* 0x1c */ -+ volatile unsigned long tb; /* 0x20 */ -+ volatile unsigned long rb; /* 0x24 */ -+ volatile unsigned long reserved2[2]; /* 0x28 */ -+ volatile unsigned long rxfcon; /* 0x30 */ -+ volatile unsigned long txfcon; /* 0x34 */ -+ volatile unsigned long fstat; /* 0x38 */ -+ volatile unsigned long reserved3; /* 0x3c */ -+ volatile unsigned long br; /* 0x40 */ -+ volatile unsigned long brstat; /* 0x44 */ -+ volatile unsigned long reserved4[6]; /* 0x48 */ -+ volatile unsigned long sfcon; /* 0x60 */ -+ volatile unsigned long sfstat; /* 0x64 */ -+ volatile unsigned long reserved5[2]; /* 0x68 */ -+ volatile unsigned long gpocon; /* 0x70 */ -+ volatile unsigned long gpostat; /* 0x74 */ -+ volatile unsigned long whbgpostat; /* 0x78 */ -+ volatile unsigned long reserved6; /* 0x7c */ -+ volatile unsigned long rxreq; /* 0x80 */ -+ volatile unsigned long rxcnt; /* 0x84 */ -+ volatile unsigned long reserved7[25]; /* 0x88 */ -+ volatile unsigned long dma_con; /* 0xEC */ -+ volatile unsigned long reserved8; /* 0xf0 */ -+ volatile unsigned long irnen; /* 0xF4 */ -+ volatile unsigned long irncr; /* 0xF8 */ -+ volatile unsigned long irnicr; /* 0xFC */ -+}; -+ -+/******************************************************************************* -+ * CLC Register -+ ******************************************************************************/ -+ -+/* Clock Divider for Sleep Mode (23:16) */ -+#define SSC_CLC_SMC (0xff << 16) -+#define SSC_CLC_SMC_VAL(val) (((val) & 0xff) << 16) -+#define SSC_CLC_SMC_GET(val) ((((val) & SSC_CLC_SMC) >> 16) & 0xff) -+#define SSC_CLC_SMC_SET(reg,val) (reg) = ((reg & ~SSC_CLC_SMC) | (((val) & 0xff) << 16)) -+/* Clock Divider for Normal Run Mode (15:8) */ -+#define SSC_CLC_RMC (0xff << 8) -+#define SSC_CLC_RMC_VAL(val) (((val) & 0xff) << 8) -+#define SSC_CLC_RMC_GET(val) ((((val) & SSC_CLC_RMC) >> 8) & 0xff) -+#define SSC_CLC_RMC_SET(reg,val) (reg) = ((reg & ~SSC_CLC_RMC) | (((val) & 0xff) << 8)) -+/* Fast Shut-Off Enable Bit (5) */ -+#define SSC_CLC_FSOE (0x1 << 5) -+#define SSC_CLC_FSOE_VAL(val) (((val) & 0x1) << 5) -+#define SSC_CLC_FSOE_GET(val) ((((val) & SSC_CLC_FSOE) >> 5) & 0x1) -+#define SSC_CLC_FSOE_SET(reg,val) (reg) = ((reg & ~SSC_CLC_FSOE) | (((val) & 0x1) << 5)) -+/* Suspend Bit Write Enable for OCDS (4) */ -+#define SSC_CLC_SBWE (0x1 << 4) -+#define SSC_CLC_SBWE_VAL(val) (((val) & 0x1) << 4) -+#define SSC_CLC_SBWE_SET(reg,val) (reg) = (((reg & ~SSC_CLC_SBWE) | (val) & 1) << 4) -+/* External Request Disable (3) */ -+#define SSC_CLC_EDIS (0x1 << 3) -+#define SSC_CLC_EDIS_VAL(val) (((val) & 0x1) << 3) -+#define SSC_CLC_EDIS_GET(val) ((((val) & SSC_CLC_EDIS) >> 3) & 0x1) -+#define SSC_CLC_EDIS_SET(reg,val) (reg) = ((reg & ~SSC_CLC_EDIS) | (((val) & 0x1) << 3)) -+/* Suspend Enable Bit for OCDS (2) */ -+#define SSC_CLC_SPEN (0x1 << 2) -+#define SSC_CLC_SPEN_VAL(val) (((val) & 0x1) << 2) -+#define SSC_CLC_SPEN_GET(val) ((((val) & SSC_CLC_SPEN) >> 2) & 0x1) -+#define SSC_CLC_SPEN_SET(reg,val) (reg) = ((reg & ~SSC_CLC_SPEN) | (((val) & 0x1) << 2)) -+/* Disable Status Bit (1) */ -+#define SSC_CLC_DISS (0x1 << 1) -+#define SSC_CLC_DISS_GET(val) ((((val) & SSC_CLC_DISS) >> 1) & 0x1) -+/* Disable Request Bit (0) */ -+#define SSC_CLC_DISR (0x1) -+#define SSC_CLC_DISR_VAL(val) (((val) & 0x1) << 0) -+#define SSC_CLC_DISR_GET(val) ((((val) & SSC_CLC_DISR) >> 0) & 0x1) -+#define SSC_CLC_DISR_SET(reg,val) (reg) = ((reg & ~SSC_CLC_DISR) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * ID Register -+ ******************************************************************************/ -+ -+/* Transmit FIFO Size (29:24) */ -+#define SSC_ID_TXFS (0x3f << 24) -+#define SSC_ID_TXFS_GET(val) ((((val) & SSC_ID_TXFS) >> 24) & 0x3f) -+/* Receive FIFO Size (21:16) */ -+#define SSC_ID_RXFS (0x3f << 16) -+#define SSC_ID_RXFS_GET(val) ((((val) & SSC_ID_RXFS) >> 16) & 0x3f) -+/* Module ID (15:8) */ -+#define SSC_ID_ID (0xff << 8) -+#define SSC_ID_ID_GET(val) ((((val) & SSC_ID_ID) >> 8) & 0xff) -+/* Configuration (5) */ -+#define SSC_ID_CFG (0x1 << 5) -+#define SSC_ID_CFG_GET(val) ((((val) & SSC_ID_CFG) >> 5) & 0x1) -+/* Revision (4:0) */ -+#define SSC_ID_REV (0x1f) -+#define SSC_ID_REV_GET(val) ((((val) & SSC_ID_REV) >> 0) & 0x1f) -+ -+/******************************************************************************* -+ * MCON Register -+ ******************************************************************************/ -+ -+/* Echo Mode (24) */ -+#define SSC_MCON_EM (0x1 << 24) -+#define SSC_MCON_EM_VAL(val) (((val) & 0x1) << 24) -+#define SSC_MCON_EM_GET(val) ((((val) & SSC_MCON_EM) >> 24) & 0x1) -+#define SSC_MCON_EM_SET(reg,val) (reg) = ((reg & ~SSC_MCON_EM) | (((val) & 0x1) << 24)) -+/* Idle Bit Value (23) */ -+#define SSC_MCON_IDLE (0x1 << 23) -+#define SSC_MCON_IDLE_VAL(val) (((val) & 0x1) << 23) -+#define SSC_MCON_IDLE_GET(val) ((((val) & SSC_MCON_IDLE) >> 23) & 0x1) -+#define SSC_MCON_IDLE_SET(reg,val) (reg) = ((reg & ~SSC_MCON_IDLE) | (((val) & 0x1) << 23)) -+/* Enable Byte Valid Control (22) */ -+#define SSC_MCON_ENBV (0x1 << 22) -+#define SSC_MCON_ENBV_VAL(val) (((val) & 0x1) << 22) -+#define SSC_MCON_ENBV_GET(val) ((((val) & SSC_MCON_ENBV) >> 22) & 0x1) -+#define SSC_MCON_ENBV_SET(reg,val) (reg) = ((reg & ~SSC_MCON_ENBV) | (((val) & 0x1) << 22)) -+/* Data Width Selection (20:16) */ -+#define SSC_MCON_BM (0x1f << 16) -+#define SSC_MCON_BM_VAL(val) (((val) & 0x1f) << 16) -+#define SSC_MCON_BM_GET(val) ((((val) & SSC_MCON_BM) >> 16) & 0x1f) -+#define SSC_MCON_BM_SET(reg,val) (reg) = ((reg & ~SSC_MCON_BM) | (((val) & 0x1f) << 16)) -+/* Receive Underflow Error Enable (12) */ -+#define SSC_MCON_RUEN (0x1 << 12) -+#define SSC_MCON_RUEN_VAL(val) (((val) & 0x1) << 12) -+#define SSC_MCON_RUEN_GET(val) ((((val) & SSC_MCON_RUEN) >> 12) & 0x1) -+#define SSC_MCON_RUEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_RUEN) | (((val) & 0x1) << 12)) -+/* Transmit Underflow Error Enable (11) */ -+#define SSC_MCON_TUEN (0x1 << 11) -+#define SSC_MCON_TUEN_VAL(val) (((val) & 0x1) << 11) -+#define SSC_MCON_TUEN_GET(val) ((((val) & SSC_MCON_TUEN) >> 11) & 0x1) -+#define SSC_MCON_TUEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TUEN) | (((val) & 0x1) << 11)) -+/* Abort Error Enable (10) */ -+#define SSC_MCON_AEN (0x1 << 10) -+#define SSC_MCON_AEN_VAL(val) (((val) & 0x1) << 10) -+#define SSC_MCON_AEN_GET(val) ((((val) & SSC_MCON_AEN) >> 10) & 0x1) -+#define SSC_MCON_AEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_AEN) | (((val) & 0x1) << 10)) -+/* Receive Overflow Error Enable (9) */ -+#define SSC_MCON_REN (0x1 << 9) -+#define SSC_MCON_REN_VAL(val) (((val) & 0x1) << 9) -+#define SSC_MCON_REN_GET(val) ((((val) & SSC_MCON_REN) >> 9) & 0x1) -+#define SSC_MCON_REN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_REN) | (((val) & 0x1) << 9)) -+/* Transmit Overflow Error Enable (8) */ -+#define SSC_MCON_TEN (0x1 << 8) -+#define SSC_MCON_TEN_VAL(val) (((val) & 0x1) << 8) -+#define SSC_MCON_TEN_GET(val) ((((val) & SSC_MCON_TEN) >> 8) & 0x1) -+#define SSC_MCON_TEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TEN) | (((val) & 0x1) << 8)) -+/* Loop Back Control (7) */ -+#define SSC_MCON_LB (0x1 << 7) -+#define SSC_MCON_LB_VAL(val) (((val) & 0x1) << 7) -+#define SSC_MCON_LB_GET(val) ((((val) & SSC_MCON_LB) >> 7) & 0x1) -+#define SSC_MCON_LB_SET(reg,val) (reg) = ((reg & ~SSC_MCON_LB) | (((val) & 0x1) << 7)) -+/* Clock Polarity Control (6) */ -+#define SSC_MCON_PO (0x1 << 6) -+#define SSC_MCON_PO_VAL(val) (((val) & 0x1) << 6) -+#define SSC_MCON_PO_GET(val) ((((val) & SSC_MCON_PO) >> 6) & 0x1) -+#define SSC_MCON_PO_SET(reg,val) (reg) = ((reg & ~SSC_MCON_PO) | (((val) & 0x1) << 6)) -+/* Clock Phase Control (5) */ -+#define SSC_MCON_PH (0x1 << 5) -+#define SSC_MCON_PH_VAL(val) (((val) & 0x1) << 5) -+#define SSC_MCON_PH_GET(val) ((((val) & SSC_MCON_PH) >> 5) & 0x1) -+#define SSC_MCON_PH_SET(reg,val) (reg) = ((reg & ~SSC_MCON_PH) | (((val) & 0x1) << 5)) -+/* Heading Control (4) */ -+#define SSC_MCON_HB (0x1 << 4) -+#define SSC_MCON_HB_VAL(val) (((val) & 0x1) << 4) -+#define SSC_MCON_HB_GET(val) ((((val) & SSC_MCON_HB) >> 4) & 0x1) -+#define SSC_MCON_HB_SET(reg,val) (reg) = ((reg & ~SSC_MCON_HB) | (((val) & 0x1) << 4)) -+/* Chip Select Enable (3) */ -+#define SSC_MCON_CSBEN (0x1 << 3) -+#define SSC_MCON_CSBEN_VAL(val) (((val) & 0x1) << 3) -+#define SSC_MCON_CSBEN_GET(val) ((((val) & SSC_MCON_CSBEN) >> 3) & 0x1) -+#define SSC_MCON_CSBEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_CSBEN) | (((val) & 0x1) << 3)) -+/* Chip Select Invert (2) */ -+#define SSC_MCON_CSBINV (0x1 << 2) -+#define SSC_MCON_CSBINV_VAL(val) (((val) & 0x1) << 2) -+#define SSC_MCON_CSBINV_GET(val) ((((val) & SSC_MCON_CSBINV) >> 2) & 0x1) -+#define SSC_MCON_CSBINV_SET(reg,val) (reg) = ((reg & ~SSC_MCON_CSBINV) | (((val) & 0x1) << 2)) -+/* Receive Off (1) */ -+#define SSC_MCON_RXOFF (0x1 << 1) -+#define SSC_MCON_RXOFF_VAL(val) (((val) & 0x1) << 1) -+#define SSC_MCON_RXOFF_GET(val) ((((val) & SSC_MCON_RXOFF) >> 1) & 0x1) -+#define SSC_MCON_RXOFF_SET(reg,val) (reg) = ((reg & ~SSC_MCON_RXOFF) | (((val) & 0x1) << 1)) -+/* Transmit Off (0) */ -+#define SSC_MCON_TXOFF (0x1) -+#define SSC_MCON_TXOFF_VAL(val) (((val) & 0x1) << 0) -+#define SSC_MCON_TXOFF_GET(val) ((((val) & SSC_MCON_TXOFF) >> 0) & 0x1) -+#define SSC_MCON_TXOFF_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TXOFF) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * STATE Register -+ ******************************************************************************/ -+ -+/* Receive End-of-Message (31) */ -+#define SSC_STATE_RXEOM (0x1 << 31) -+#define SSC_STATE_RXEOM_GET(val) ((((val) & SSC_STATE_RXEOM) >> 31) & 0x1) -+/* Receive Byte Valid (30:28) */ -+#define SSC_STATE_RXBV (0x7 << 28) -+#define SSC_STATE_RXBV_GET(val) ((((val) & SSC_STATE_RXBV) >> 28) & 0x7) -+/* Transmit End-of-Message (27) */ -+#define SSC_STATE_TXEOM (0x1 << 27) -+#define SSC_STATE_TXEOM_GET(val) ((((val) & SSC_STATE_TXEOM) >> 27) & 0x1) -+/* Transmit Byte Valid (26:24) */ -+#define SSC_STATE_TXBV (0x7 << 24) -+#define SSC_STATE_TXBV_GET(val) ((((val) & SSC_STATE_TXBV) >> 24) & 0x7) -+/* Bit Count Field (20:16) */ -+#define SSC_STATE_BC (0x1f << 16) -+#define SSC_STATE_BC_GET(val) ((((val) & SSC_STATE_BC) >> 16) & 0x1f) -+/* Busy Flag (13) */ -+#define SSC_STATE_BSY (0x1 << 13) -+#define SSC_STATE_BSY_GET(val) ((((val) & SSC_STATE_BSY) >> 13) & 0x1) -+/* Receive Underflow Error Flag (12) */ -+#define SSC_STATE_RUE (0x1 << 12) -+#define SSC_STATE_RUE_GET(val) ((((val) & SSC_STATE_RUE) >> 12) & 0x1) -+/* Transmit Underflow Error Flag (11) */ -+#define SSC_STATE_TUE (0x1 << 11) -+#define SSC_STATE_TUE_GET(val) ((((val) & SSC_STATE_TUE) >> 11) & 0x1) -+/* Abort Error Flag (10) */ -+#define SSC_STATE_AE (0x1 << 10) -+#define SSC_STATE_AE_GET(val) ((((val) & SSC_STATE_AE) >> 10) & 0x1) -+/* Receive Error Flag (9) */ -+#define SSC_STATE_RE (0x1 << 9) -+#define SSC_STATE_RE_GET(val) ((((val) & SSC_STATE_RE) >> 9) & 0x1) -+/* Transmit Error Flag (8) */ -+#define SSC_STATE_TE (0x1 << 8) -+#define SSC_STATE_TE_GET(val) ((((val) & SSC_STATE_TE) >> 8) & 0x1) -+/* Mode Error Flag (7) */ -+#define SSC_STATE_ME (0x1 << 7) -+#define SSC_STATE_ME_GET(val) ((((val) & SSC_STATE_ME) >> 7) & 0x1) -+/* Slave Selected (2) */ -+#define SSC_STATE_SSEL (0x1 << 2) -+#define SSC_STATE_SSEL_GET(val) ((((val) & SSC_STATE_SSEL) >> 2) & 0x1) -+/* Master Select Bit (1) */ -+#define SSC_STATE_MS (0x1 << 1) -+#define SSC_STATE_MS_GET(val) ((((val) & SSC_STATE_MS) >> 1) & 0x1) -+/* Enable Bit (0) */ -+#define SSC_STATE_EN (0x1) -+#define SSC_STATE_EN_GET(val) ((((val) & SSC_STATE_EN) >> 0) & 0x1) -+ -+/******************************************************************************* -+ * WHBSTATE Register -+ ******************************************************************************/ -+ -+/* Set Transmit Underflow Error Flag Bit (15) */ -+#define SSC_WHBSTATE_SETTUE (0x1 << 15) -+#define SSC_WHBSTATE_SETTUE_VAL(val) (((val) & 0x1) << 15) -+#define SSC_WHBSTATE_SETTUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETTUE) | (val) & 1) << 15) -+/* Set Abort Error Flag Bit (14) */ -+#define SSC_WHBSTATE_SETAE (0x1 << 14) -+#define SSC_WHBSTATE_SETAE_VAL(val) (((val) & 0x1) << 14) -+#define SSC_WHBSTATE_SETAE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETAE) | (val) & 1) << 14) -+/* Set Receive Error Flag Bit (13) */ -+#define SSC_WHBSTATE_SETRE (0x1 << 13) -+#define SSC_WHBSTATE_SETRE_VAL(val) (((val) & 0x1) << 13) -+#define SSC_WHBSTATE_SETRE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETRE) | (val) & 1) << 13) -+/* Set Transmit Error Flag Bit (12) */ -+#define SSC_WHBSTATE_SETTE (0x1 << 12) -+#define SSC_WHBSTATE_SETTE_VAL(val) (((val) & 0x1) << 12) -+#define SSC_WHBSTATE_SETTE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETTE) | (val) & 1) << 12) -+/* Clear Transmit Underflow Error Flag Bit (11) */ -+#define SSC_WHBSTATE_CLRTUE (0x1 << 11) -+#define SSC_WHBSTATE_CLRTUE_VAL(val) (((val) & 0x1) << 11) -+#define SSC_WHBSTATE_CLRTUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRTUE) | (val) & 1) << 11) -+/* Clear Abort Error Flag Bit (10) */ -+#define SSC_WHBSTATE_CLRAE (0x1 << 10) -+#define SSC_WHBSTATE_CLRAE_VAL(val) (((val) & 0x1) << 10) -+#define SSC_WHBSTATE_CLRAE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRAE) | (val) & 1) << 10) -+/* Clear Receive Error Flag Bit (9) */ -+#define SSC_WHBSTATE_CLRRE (0x1 << 9) -+#define SSC_WHBSTATE_CLRRE_VAL(val) (((val) & 0x1) << 9) -+#define SSC_WHBSTATE_CLRRE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRRE) | (val) & 1) << 9) -+/* Clear Transmit Error Flag Bit (8) */ -+#define SSC_WHBSTATE_CLRTE (0x1 << 8) -+#define SSC_WHBSTATE_CLRTE_VAL(val) (((val) & 0x1) << 8) -+#define SSC_WHBSTATE_CLRTE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRTE) | (val) & 1) << 8) -+/* Set Mode Error Flag Bit (7) */ -+#define SSC_WHBSTATE_SETME (0x1 << 7) -+#define SSC_WHBSTATE_SETME_VAL(val) (((val) & 0x1) << 7) -+#define SSC_WHBSTATE_SETME_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETME) | (val) & 1) << 7) -+/* Clear Mode Error Flag Bit (6) */ -+#define SSC_WHBSTATE_CLRME (0x1 << 6) -+#define SSC_WHBSTATE_CLRME_VAL(val) (((val) & 0x1) << 6) -+#define SSC_WHBSTATE_CLRME_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRME) | (val) & 1) << 6) -+/* Set Receive Underflow Error Bit (5) */ -+#define SSC_WHBSTATE_SETRUE (0x1 << 5) -+#define SSC_WHBSTATE_SETRUE_VAL(val) (((val) & 0x1) << 5) -+#define SSC_WHBSTATE_SETRUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETRUE) | (val) & 1) << 5) -+/* Clear Receive Underflow Error Bit (4) */ -+#define SSC_WHBSTATE_CLRRUE (0x1 << 4) -+#define SSC_WHBSTATE_CLRRUE_VAL(val) (((val) & 0x1) << 4) -+#define SSC_WHBSTATE_CLRRUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRRUE) | (val) & 1) << 4) -+/* Set Master Select Bit (3) */ -+#define SSC_WHBSTATE_SETMS (0x1 << 3) -+#define SSC_WHBSTATE_SETMS_VAL(val) (((val) & 0x1) << 3) -+#define SSC_WHBSTATE_SETMS_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETMS) | (val) & 1) << 3) -+/* Clear Master Select Bit (2) */ -+#define SSC_WHBSTATE_CLRMS (0x1 << 2) -+#define SSC_WHBSTATE_CLRMS_VAL(val) (((val) & 0x1) << 2) -+#define SSC_WHBSTATE_CLRMS_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRMS) | (val) & 1) << 2) -+/* Set Enable Bit (1) */ -+#define SSC_WHBSTATE_SETEN (0x1 << 1) -+#define SSC_WHBSTATE_SETEN_VAL(val) (((val) & 0x1) << 1) -+#define SSC_WHBSTATE_SETEN_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETEN) | (val) & 1) << 1) -+/* Clear Enable Bit (0) */ -+#define SSC_WHBSTATE_CLREN (0x1) -+#define SSC_WHBSTATE_CLREN_VAL(val) (((val) & 0x1) << 0) -+#define SSC_WHBSTATE_CLREN_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLREN) | (val) & 1) << 0) -+ -+/******************************************************************************* -+ * TB Register -+ ******************************************************************************/ -+ -+/* Transmit Data Register Value (31:0) */ -+#define SSC_TB_TB_VAL (0xFFFFFFFFL) -+#define SSC_TB_TB_VAL_VAL(val) (((val) & 0xFFFFFFFFL) << 0) -+#define SSC_TB_TB_VAL_GET(val) ((((val) & SSC_TB_TB_VAL) >> 0) & 0xFFFFFFFFL) -+#define SSC_TB_TB_VAL_SET(reg,val) (reg) = ((reg & ~SSC_TB_TB_VAL) | (((val) & 0xFFFFFFFFL) << 0)) -+ -+/******************************************************************************* -+ * RB Register -+ ******************************************************************************/ -+ -+/* Receive Data Register Value (31:0) */ -+#define SSC_RB_RB_VAL (0xFFFFFFFFL) -+#define SSC_RB_RB_VAL_GET(val) ((((val) & SSC_RB_RB_VAL) >> 0) & 0xFFFFFFFFL) -+ -+/******************************************************************************* -+ * FSTAT Register -+ ******************************************************************************/ -+ -+/* Transmit FIFO Filling Level (13:8) */ -+#define SSC_FSTAT_TXFFL (0x3f << 8) -+#define SSC_FSTAT_TXFFL_GET(val) ((((val) & SSC_FSTAT_TXFFL) >> 8) & 0x3f) -+/* Receive FIFO Filling Level (5:0) */ -+#define SSC_FSTAT_RXFFL (0x3f) -+#define SSC_FSTAT_RXFFL_GET(val) ((((val) & SSC_FSTAT_RXFFL) >> 0) & 0x3f) -+ -+/******************************************************************************* -+ * PISEL Register -+ ******************************************************************************/ -+ -+/* Slave Mode Clock Input Select (2) */ -+#define SSC_PISEL_CIS (0x1 << 2) -+#define SSC_PISEL_CIS_VAL(val) (((val) & 0x1) << 2) -+#define SSC_PISEL_CIS_GET(val) ((((val) & SSC_PISEL_CIS) >> 2) & 0x1) -+#define SSC_PISEL_CIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_CIS) | (((val) & 0x1) << 2)) -+/* Slave Mode Receiver Input Select (1) */ -+#define SSC_PISEL_SIS (0x1 << 1) -+#define SSC_PISEL_SIS_VAL(val) (((val) & 0x1) << 1) -+#define SSC_PISEL_SIS_GET(val) ((((val) & SSC_PISEL_SIS) >> 1) & 0x1) -+#define SSC_PISEL_SIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_SIS) | (((val) & 0x1) << 1)) -+/* Master Mode Receiver Input Select (0) */ -+#define SSC_PISEL_MIS (0x1) -+#define SSC_PISEL_MIS_VAL(val) (((val) & 0x1) << 0) -+#define SSC_PISEL_MIS_GET(val) ((((val) & SSC_PISEL_MIS) >> 0) & 0x1) -+#define SSC_PISEL_MIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_MIS) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * RXFCON Register -+ ******************************************************************************/ -+ -+/* Receive FIFO Interrupt Trigger Level (13:8) */ -+#define SSC_RXFCON_RXFITL (0x3f << 8) -+#define SSC_RXFCON_RXFITL_VAL(val) (((val) & 0x3f) << 8) -+#define SSC_RXFCON_RXFITL_GET(val) ((((val) & SSC_RXFCON_RXFITL) >> 8) & 0x3f) -+#define SSC_RXFCON_RXFITL_SET(reg,val) (reg) = ((reg & ~SSC_RXFCON_RXFITL) | (((val) & 0x3f) << 8)) -+/* Receive FIFO Flush (1) */ -+#define SSC_RXFCON_RXFLU (0x1 << 1) -+#define SSC_RXFCON_RXFLU_VAL(val) (((val) & 0x1) << 1) -+#define SSC_RXFCON_RXFLU_SET(reg,val) (reg) = (((reg & ~SSC_RXFCON_RXFLU) | (val) & 1) << 1) -+/* Receive FIFO Enable (0) */ -+#define SSC_RXFCON_RXFEN (0x1) -+#define SSC_RXFCON_RXFEN_VAL(val) (((val) & 0x1) << 0) -+#define SSC_RXFCON_RXFEN_GET(val) ((((val) & SSC_RXFCON_RXFEN) >> 0) & 0x1) -+#define SSC_RXFCON_RXFEN_SET(reg,val) (reg) = ((reg & ~SSC_RXFCON_RXFEN) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * TXFCON Register -+ ******************************************************************************/ -+ -+/* Transmit FIFO Interrupt Trigger Level (13:8) */ -+#define SSC_TXFCON_TXFITL (0x3f << 8) -+#define SSC_TXFCON_TXFITL_VAL(val) (((val) & 0x3f) << 8) -+#define SSC_TXFCON_TXFITL_GET(val) ((((val) & SSC_TXFCON_TXFITL) >> 8) & 0x3f) -+#define SSC_TXFCON_TXFITL_SET(reg,val) (reg) = ((reg & ~SSC_TXFCON_TXFITL) | (((val) & 0x3f) << 8)) -+/* Transmit FIFO Flush (1) */ -+#define SSC_TXFCON_TXFLU (0x1 << 1) -+#define SSC_TXFCON_TXFLU_VAL(val) (((val) & 0x1) << 1) -+#define SSC_TXFCON_TXFLU_SET(reg,val) (reg) = (((reg & ~SSC_TXFCON_TXFLU) | (val) & 1) << 1) -+/* Transmit FIFO Enable (0) */ -+#define SSC_TXFCON_TXFEN (0x1) -+#define SSC_TXFCON_TXFEN_VAL(val) (((val) & 0x1) << 0) -+#define SSC_TXFCON_TXFEN_GET(val) ((((val) & SSC_TXFCON_TXFEN) >> 0) & 0x1) -+#define SSC_TXFCON_TXFEN_SET(reg,val) (reg) = ((reg & ~SSC_TXFCON_TXFEN) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * BR Register -+ ******************************************************************************/ -+ -+/* Baudrate Timer Reload Register Value (15:0) */ -+#define SSC_BR_BR_VAL (0xffff) -+#define SSC_BR_BR_VAL_VAL(val) (((val) & 0xffff) << 0) -+#define SSC_BR_BR_VAL_GET(val) ((((val) & SSC_BR_BR_VAL) >> 0) & 0xffff) -+#define SSC_BR_BR_VAL_SET(reg,val) (reg) = ((reg & ~SSC_BR_BR_VAL) | (((val) & 0xffff) << 0)) -+ -+/******************************************************************************* -+ * BRSTAT Register -+ ******************************************************************************/ -+ -+/* Baudrate Timer Register Value (15:0) */ -+#define SSC_BRSTAT_BT_VAL (0xffff) -+#define SSC_BRSTAT_BT_VAL_GET(val) ((((val) & SSC_BRSTAT_BT_VAL) >> 0) & 0xffff) -+ -+/******************************************************************************* -+ * SFCON Register -+ ******************************************************************************/ -+ -+/* Pause Length (31:22) */ -+#define SSC_SFCON_PLEN (0x3ff << 22) -+#define SSC_SFCON_PLEN_VAL(val) (((val) & 0x3ff) << 22) -+#define SSC_SFCON_PLEN_GET(val) ((((val) & SSC_SFCON_PLEN) >> 22) & 0x3ff) -+#define SSC_SFCON_PLEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_PLEN) | (((val) & 0x3ff) << 22)) -+/* Stop After Pause (20) */ -+#define SSC_SFCON_STOP (0x1 << 20) -+#define SSC_SFCON_STOP_VAL(val) (((val) & 0x1) << 20) -+#define SSC_SFCON_STOP_GET(val) ((((val) & SSC_SFCON_STOP) >> 20) & 0x1) -+#define SSC_SFCON_STOP_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_STOP) | (((val) & 0x1) << 20)) -+/* Idle Clock Configuration (19:18) */ -+#define SSC_SFCON_ICLK (0x3 << 18) -+#define SSC_SFCON_ICLK_VAL(val) (((val) & 0x3) << 18) -+#define SSC_SFCON_ICLK_GET(val) ((((val) & SSC_SFCON_ICLK) >> 18) & 0x3) -+#define SSC_SFCON_ICLK_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_ICLK) | (((val) & 0x3) << 18)) -+/* Idle Data Configuration (17:16) */ -+#define SSC_SFCON_IDAT (0x3 << 16) -+#define SSC_SFCON_IDAT_VAL(val) (((val) & 0x3) << 16) -+#define SSC_SFCON_IDAT_GET(val) ((((val) & SSC_SFCON_IDAT) >> 16) & 0x3) -+#define SSC_SFCON_IDAT_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IDAT) | (((val) & 0x3) << 16)) -+/* Data Length (15:4) */ -+#define SSC_SFCON_DLEN (0xfff << 4) -+#define SSC_SFCON_DLEN_VAL(val) (((val) & 0xfff) << 4) -+#define SSC_SFCON_DLEN_GET(val) ((((val) & SSC_SFCON_DLEN) >> 4) & 0xfff) -+#define SSC_SFCON_DLEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_DLEN) | (((val) & 0xfff) << 4)) -+/* Enable Interrupt After Pause (3) */ -+#define SSC_SFCON_IAEN (0x1 << 3) -+#define SSC_SFCON_IAEN_VAL(val) (((val) & 0x1) << 3) -+#define SSC_SFCON_IAEN_GET(val) ((((val) & SSC_SFCON_IAEN) >> 3) & 0x1) -+#define SSC_SFCON_IAEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IAEN) | (((val) & 0x1) << 3)) -+/* Enable Interrupt Before Pause (2) */ -+#define SSC_SFCON_IBEN (0x1 << 2) -+#define SSC_SFCON_IBEN_VAL(val) (((val) & 0x1) << 2) -+#define SSC_SFCON_IBEN_GET(val) ((((val) & SSC_SFCON_IBEN) >> 2) & 0x1) -+#define SSC_SFCON_IBEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IBEN) | (((val) & 0x1) << 2)) -+/* Serial Frame Enable (0) */ -+#define SSC_SFCON_SFEN (0x1) -+#define SSC_SFCON_SFEN_VAL(val) (((val) & 0x1) << 0) -+#define SSC_SFCON_SFEN_GET(val) ((((val) & SSC_SFCON_SFEN) >> 0) & 0x1) -+#define SSC_SFCON_SFEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_SFEN) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * SFSTAT Register -+ ******************************************************************************/ -+ -+/* Pause Count (31:22) */ -+#define SSC_SFSTAT_PCNT (0x3ff << 22) -+#define SSC_SFSTAT_PCNT_GET(val) ((((val) & SSC_SFSTAT_PCNT) >> 22) & 0x3ff) -+/* Data Bit Count (15:4) */ -+#define SSC_SFSTAT_DCNT (0xfff << 4) -+#define SSC_SFSTAT_DCNT_GET(val) ((((val) & SSC_SFSTAT_DCNT) >> 4) & 0xfff) -+/* Pause Busy (1) */ -+#define SSC_SFSTAT_PBSY (0x1 << 1) -+#define SSC_SFSTAT_PBSY_GET(val) ((((val) & SSC_SFSTAT_PBSY) >> 1) & 0x1) -+/* Data Busy (0) */ -+#define SSC_SFSTAT_DBSY (0x1) -+#define SSC_SFSTAT_DBSY_GET(val) ((((val) & SSC_SFSTAT_DBSY) >> 0) & 0x1) -+ -+/******************************************************************************* -+ * GPOCON Register -+ ******************************************************************************/ -+ -+/* Output OUTn Is Chip Select (15:8) */ -+#define SSC_GPOCON_ISCSBN (0xff << 8) -+#define SSC_GPOCON_ISCSBN_VAL(val) (((val) & 0xff) << 8) -+#define SSC_GPOCON_ISCSBN_GET(val) ((((val) & SSC_GPOCON_ISCSBN) >> 8) & 0xff) -+#define SSC_GPOCON_ISCSBN_SET(reg,val) (reg) = ((reg & ~SSC_GPOCON_ISCSBN) | (((val) & 0xff) << 8)) -+/* Invert Output OUTn (7:0) */ -+#define SSC_GPOCON_INVOUTN (0xff) -+#define SSC_GPOCON_INVOUTN_VAL(val) (((val) & 0xff) << 0) -+#define SSC_GPOCON_INVOUTN_GET(val) ((((val) & SSC_GPOCON_INVOUTN) >> 0) & 0xff) -+#define SSC_GPOCON_INVOUTN_SET(reg,val) (reg) = ((reg & ~SSC_GPOCON_INVOUTN) | (((val) & 0xff) << 0)) -+ -+/******************************************************************************* -+ * GPOSTAT Register -+ ******************************************************************************/ -+ -+/* Output Register Bit n (7:0) */ -+#define SSC_GPOSTAT_OUTN (0xff) -+#define SSC_GPOSTAT_OUTN_GET(val) ((((val) & SSC_GPOSTAT_OUTN) >> 0) & 0xff) -+ -+/******************************************************************************* -+ * WHBGPOSTAT -+ ******************************************************************************/ -+ -+/* Set Output Register Bit n (15:8) */ -+#define SSC_WHBGPOSTAT_SETOUTN (0xff << 8) -+#define SSC_WHBGPOSTAT_SETOUTN_VAL(val) (((val) & 0xff) << 8) -+#define SSC_WHBGPOSTAT_SETOUTN_SET(reg,val) (reg) = (((reg & ~SSC_WHBGPOSTAT_SETOUTN) | (val) & 1) << 8) -+/* Clear Output Register Bit n (7:0) */ -+#define SSC_WHBGPOSTAT_CLROUTN (0xff) -+#define SSC_WHBGPOSTAT_CLROUTN_VAL(val) (((val) & 0xff) << 0) -+#define SSC_WHBGPOSTAT_CLROUTN_SET(reg,val) (reg) = (((reg & ~SSC_WHBGPOSTAT_CLROUTN) | (val) & 1) << 0) -+ -+/******************************************************************************* -+ * RXREQ Register -+ ******************************************************************************/ -+ -+/* Receive Count Value (15:0) */ -+#define SSC_RXREQ_RXCNT (0xffff) -+#define SSC_RXREQ_RXCNT_VAL(val) (((val) & 0xffff) << 0) -+#define SSC_RXREQ_RXCNT_GET(val) ((((val) & SSC_RXREQ_RXCNT) >> 0) & 0xffff) -+#define SSC_RXREQ_RXCNT_SET(reg,val) (reg) = ((reg & ~SSC_RXREQ_RXCNT) | (((val) & 0xffff) << 0)) -+ -+/******************************************************************************* -+ * RXCNT Register -+ ******************************************************************************/ -+ -+/* Receive To Do Value (15:0) */ -+#define SSC_RXCNT_TODO (0xffff) -+#define SSC_RXCNT_TODO_GET(val) ((((val) & SSC_RXCNT_TODO) >> 0) & 0xffff) -+ -+/******************************************************************************* -+ * DMA_CON Register -+ ******************************************************************************/ -+ -+/* Receive Class (3:2) */ -+#define SSC_DMA_CON_RXCLS (0x3 << 2) -+#define SSC_DMA_CON_RXCLS_VAL(val) (((val) & 0x3) << 2) -+#define SSC_DMA_CON_RXCLS_GET(val) ((((val) & SSC_DMA_CON_RXCLS) >> 2) & 0x3) -+#define SSC_DMA_CON_RXCLS_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_RXCLS) | (((val) & 0x3) << 2)) -+/* Transmit Path On (1) */ -+#define SSC_DMA_CON_TXON (0x1 << 1) -+#define SSC_DMA_CON_TXON_VAL(val) (((val) & 0x1) << 1) -+#define SSC_DMA_CON_TXON_GET(val) ((((val) & SSC_DMA_CON_TXON) >> 1) & 0x1) -+#define SSC_DMA_CON_TXON_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_TXON) | (((val) & 0x1) << 1)) -+/* Receive Path On (0) */ -+#define SSC_DMA_CON_RXON (0x1) -+#define SSC_DMA_CON_RXON_VAL(val) (((val) & 0x1) << 0) -+#define SSC_DMA_CON_RXON_GET(val) ((((val) & SSC_DMA_CON_RXON) >> 0) & 0x1) -+#define SSC_DMA_CON_RXON_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_RXON) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * IRNEN Register -+ ******************************************************************************/ -+ -+/* Frame End Interrupt Request Enable (3) */ -+#define SSC_IRNEN_F (0x1 << 3) -+#define SSC_IRNEN_F_VAL(val) (((val) & 0x1) << 3) -+#define SSC_IRNEN_F_GET(val) ((((val) & SSC_IRNEN_F) >> 3) & 0x1) -+#define SSC_IRNEN_F_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_F) | (((val) & 0x1) << 3)) -+/* Error Interrupt Request Enable (2) */ -+#define SSC_IRNEN_E (0x1 << 2) -+#define SSC_IRNEN_E_VAL(val) (((val) & 0x1) << 2) -+#define SSC_IRNEN_E_GET(val) ((((val) & SSC_IRNEN_E) >> 2) & 0x1) -+#define SSC_IRNEN_E_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_E) | (((val) & 0x1) << 2)) -+/* Receive Interrupt Request Enable (1) */ -+#define SSC_IRNEN_R (0x1 << 1) -+#define SSC_IRNEN_R_VAL(val) (((val) & 0x1) << 1) -+#define SSC_IRNEN_R_GET(val) ((((val) & SSC_IRNEN_R) >> 1) & 0x1) -+#define SSC_IRNEN_R_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_R) | (((val) & 0x1) << 1)) -+/* Transmit Interrupt Request Enable (0) */ -+#define SSC_IRNEN_T (0x1) -+#define SSC_IRNEN_T_VAL(val) (((val) & 0x1) << 0) -+#define SSC_IRNEN_T_GET(val) ((((val) & SSC_IRNEN_T) >> 0) & 0x1) -+#define SSC_IRNEN_T_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_T) | (((val) & 0x1) << 0)) -+ -+/******************************************************************************* -+ * IRNICR Register -+ ******************************************************************************/ -+ -+/* Frame End Interrupt Request (3) */ -+#define SSC_IRNICR_F (0x1 << 3) -+#define SSC_IRNICR_F_GET(val) ((((val) & SSC_IRNICR_F) >> 3) & 0x1) -+/* Error Interrupt Request (2) */ -+#define SSC_IRNICR_E (0x1 << 2) -+#define SSC_IRNICR_E_GET(val) ((((val) & SSC_IRNICR_E) >> 2) & 0x1) -+/* Receive Interrupt Request (1) */ -+#define SSC_IRNICR_R (0x1 << 1) -+#define SSC_IRNICR_R_GET(val) ((((val) & SSC_IRNICR_R) >> 1) & 0x1) -+/* Transmit Interrupt Request (0) */ -+#define SSC_IRNICR_T (0x1) -+#define SSC_IRNICR_T_GET(val) ((((val) & SSC_IRNICR_T) >> 0) & 0x1) -+ -+/******************************************************************************* -+ * IRNCR Register -+ ******************************************************************************/ -+ -+/* Frame End Interrupt Request (3) */ -+#define SSC_IRNCR_F (0x1 << 3) -+#define SSC_IRNCR_F_GET(val) ((((val) & SSC_IRNCR_F) >> 3) & 0x1) -+/* Error Interrupt Request (2) */ -+#define SSC_IRNCR_E (0x1 << 2) -+#define SSC_IRNCR_E_GET(val) ((((val) & SSC_IRNCR_E) >> 2) & 0x1) -+/* Receive Interrupt Request (1) */ -+#define SSC_IRNCR_R (0x1 << 1) -+#define SSC_IRNCR_R_GET(val) ((((val) & SSC_IRNCR_R) >> 1) & 0x1) -+/* Transmit Interrupt Request (0) */ -+#define SSC_IRNCR_T (0x1) -+#define SSC_IRNCR_T_GET(val) ((((val) & SSC_IRNCR_T) >> 0) & 0x1) -+ -+#endif /* __SSC_H */ -Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/svip_mux.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/svip_mux.h 2012-07-31 15:46:02.484476159 +0200 -@@ -0,0 +1,467 @@ -+/************************************************************************ -+ * -+ * Copyright (c) 2007 -+ * Infineon Technologies AG -+ * St. Martin Strasse 53; 81669 Muenchen; Germany -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ * -+ ************************************************************************/ -+ -+#ifndef __SVIP_MUX_H -+#define __SVIP_MUX_H -+ -+#define LTQ_MUX_P0_PINS 20 -+#define LTQ_MUX_P1_PINS 20 -+#define LTQ_MUX_P2_PINS 19 -+#define LTQ_MUX_P3_PINS 20 -+#define LTQ_MUX_P4_PINS 24 -+ -+struct ltq_mux_pin { -+ int dirin; -+ int puen; -+ int altsel0; -+ int altsel1; -+}; -+ -+struct ltq_mux_settings { -+ const struct ltq_mux_pin *mux_p0; -+ const struct ltq_mux_pin *mux_p1; -+ const struct ltq_mux_pin *mux_p2; -+ const struct ltq_mux_pin *mux_p3; -+ const struct ltq_mux_pin *mux_p4; -+}; -+ -+#define LTQ_MUX_P0_19_EXINT16 { 1, 0, 1, 0 } -+#define LTQ_MUX_P0_19 { 0, 0, 1, 0 } -+ -+#define LTQ_MUX_P0_18_EJ_BRKIN { 1, 0, 0, 0 } -+#define LTQ_MUX_P0_18 { 0, 0, 1, 0 } -+#define LTQ_MUX_P0_18_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P0_17_EXINT10 { 1, 0, 0, 0 } -+#define LTQ_MUX_P0_17 { 0, 0, 0, 0 } -+#define LTQ_MUX_P0_17_ASC1_RXD { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P0_16_EXINT9 { 1, 0, 0, 0 } -+#define LTQ_MUX_P0_16 { 0, 0, 0, 0 } -+#define LTQ_MUX_P0_16_ASC1_TXD { 0, 0, 1, 0 } -+ -+#define LTQ_MUX_P0_15_EXINT8 { 1, 0, 0, 0 } -+#define LTQ_MUX_P0_15 { 0, 0, 0, 0 } -+#define LTQ_MUX_P0_15_ASC0_RXD { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P0_14_EXINT7 { 1, 0, 0, 0 } -+#define LTQ_MUX_P0_14 { 0, 0, 0, 0 } -+#define LTQ_MUX_P0_14_ASC0_TXD { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P0_13_SSC0_CS7 { 0, 1, 0, 0 } -+#define LTQ_MUX_P0_13_EXINT6 { 0, 0, 1, 0 } -+#define LTQ_MUX_P0_13 { 1, 0, 1, 0 } -+#define LTQ_MUX_P0_13_SSC1_CS7 { 0, 0, 0, 1 } -+#define LTQ_MUX_P0_13_SSC1_INT { 0, 0, 1, 1 } -+ -+#define LTQ_MUX_P0_12_SSC0_CS6 { 0, 1, 0, 0 } -+#define LTQ_MUX_P0_12_EXINT5 { 0, 0, 1, 0 } -+#define LTQ_MUX_P0_12 { 1, 0, 1, 0 } -+#define LTQ_MUX_P0_12_SSC1_CS6 { 0, 0, 0, 1 } -+ -+#define LTQ_MUX_P0_11_SSC0_CS5 { 0, 1, 0, 0 } -+#define LTQ_MUX_P0_11_EXINT4 { 1, 0, 1, 0 } -+#define LTQ_MUX_P0_11 { 1, 0, 0, 0 } -+#define LTQ_MUX_P0_11_SSC1_CS5 { 0, 0, 0, 1 } -+ -+#define LTQ_MUX_P0_10_SSC0_CS4 { 0, 1, 0, 0 } -+#define LTQ_MUX_P0_10_EXINT3 { 1, 0, 1, 0 } -+#define LTQ_MUX_P0_10 { 0, 0, 1, 0 } -+#define LTQ_MUX_P0_10_SSC1_CS4 { 0, 0, 0, 1 } -+ -+#define LTQ_MUX_P0_9_SSC0_CS3 { 0, 1, 0, 0 } -+#define LTQ_MUX_P0_9_EXINT2 { 1, 0, 1, 0 } -+#define LTQ_MUX_P0_9 { 0, 0, 1, 0 } -+#define LTQ_MUX_P0_9_SSC1_CS3 { 0, 0, 0, 1 } -+ -+#define LTQ_MUX_P0_8_SSC0_CS2 { 0, 1, 0, 0 } -+#define LTQ_MUX_P0_8_EXINT1 { 1, 0, 1, 0 } -+#define LTQ_MUX_P0_8 { 0, 0, 1, 0 } -+#define LTQ_MUX_P0_8_SSC1_CS2 { 0, 0, 0, 1 } -+ -+#define LTQ_MUX_P0_7_SSC0_CS1 { 0, 1, 0, 0 } -+#define LTQ_MUX_P0_7_EXINT0 { 1, 0, 1, 0 } -+#define LTQ_MUX_P0_7 { 0, 0, 1, 0 } -+#define LTQ_MUX_P0_7_SSC1_CS1 { 0, 0, 0, 1 } -+#define LTQ_MUX_P0_7_SSC1_CS0 { 1, 0, 0, 1 } -+#define LTQ_MUX_P0_7_SSC2_CS0 { 1, 0, 1, 1 } -+ -+#define LTQ_MUX_P0_6_SSC0_CS0 { 0, 1, 0, 0 } -+#define LTQ_MUX_P0_6 { 0, 0, 1, 0 } -+#define LTQ_MUX_P0_6_IN { 1, 0, 1, 0 } -+#define LTQ_MUX_P0_6_SSC1_CS0 { 0, 0, 0, 1 } -+ -+#define LTQ_MUX_P0_5_SSC1_SCLK { 0, 0, 0, 0 } -+#define LTQ_MUX_P0_5 { 0, 0, 1, 0 } -+#define LTQ_MUX_P0_5_IN { 1, 0, 1, 0 } -+#define LTQ_MUX_P0_5_SSC2_CLK { 1, 0, 0, 1 } -+ -+#define LTQ_MUX_P0_4_SSC1_MRST { 1, 0, 0, 0 } -+#define LTQ_MUX_P0_4 { 0, 0, 1, 0 } -+#define LTQ_MUX_P0_4_IN { 1, 0, 1, 0 } -+#define LTQ_MUX_P0_4_SSC2_MRST { 0, 0, 0, 1 } -+ -+#define LTQ_MUX_P0_3_SSC1_MTSR { 0, 0, 0, 0 } -+#define LTQ_MUX_P0_3 { 0, 0, 1, 0 } -+#define LTQ_MUX_P0_3_IN { 1, 0, 1, 0 } -+#define LTQ_MUX_P0_3_SSC2_MTSR { 0, 0, 0, 1 } -+ -+#define LTQ_MUX_P0_2_SSC0_SCLK { 0, 0, 0, 0 } -+#define LTQ_MUX_P0_2 { 0, 0, 1, 0 } -+#define LTQ_MUX_P0_2_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P0_1_SSC0_MRST { 1, 0, 0, 0 } -+#define LTQ_MUX_P0_1 { 0, 0, 1, 0 } -+#define LTQ_MUX_P0_1_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P0_0_SSC0_MTSR { 0, 0, 0, 0 } -+#define LTQ_MUX_P0_0 { 0, 0, 1, 0 } -+#define LTQ_MUX_P0_0_IN { 1, 0, 1, 0 } -+ -+ -+#define LTQ_MUX_P1_19_PCM3_TC1 { 0, 0, 0, 0 } -+#define LTQ_MUX_P1_19_EXINT15 { 1, 0, 1, 0 } -+#define LTQ_MUX_P1_19 { 0, 0, 1, 0 } -+ -+#define LTQ_MUX_P1_18_PCM3_FSC { 0, 0, 0, 0 } -+#define LTQ_MUX_P1_18_EXINT11 { 1, 0, 1, 0 } -+#define LTQ_MUX_P1_18 { 0, 0, 1, 0 } -+ -+#define LTQ_MUX_P1_17_PCM3_PCL { 0, 0, 0, 0 } -+#define LTQ_MUX_P1_17_EXINT12 { 1, 0, 1, 0 } -+#define LTQ_MUX_P1_17 { 0, 0, 1, 0 } -+ -+#define LTQ_MUX_P1_16_PCM3_TX { 0, 0, 0, 0 } -+#define LTQ_MUX_P1_16_EXINT13 { 1, 0, 1, 0 } -+#define LTQ_MUX_P1_16 { 0, 0, 1, 0 } -+ -+#define LTQ_MUX_P1_15_PCM3_RX { 0, 0, 0, 0 } -+#define LTQ_MUX_P1_15_EXINT14 { 1, 0, 1, 0 } -+#define LTQ_MUX_P1_15 { 0, 0, 1, 0 } -+ -+#define LTQ_MUX_P1_14_PCM2_TC1 { 0, 0, 0, 0 } -+#define LTQ_MUX_P1_14 { 0, 0, 1, 0 } -+#define LTQ_MUX_P1_14_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P1_13_PCM2_FSC { 0, 0, 0, 0 } -+#define LTQ_MUX_P1_13 { 0, 0, 1, 0 } -+#define LTQ_MUX_P1_13_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P1_12_PCM2_PCL { 0, 0, 0, 0 } -+#define LTQ_MUX_P1_12 { 0, 0, 1, 0 } -+#define LTQ_MUX_P1_12_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P1_11_PCM2_TX { 0, 0, 0, 0 } -+#define LTQ_MUX_P1_11 { 0, 0, 1, 0 } -+#define LTQ_MUX_P1_11_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P1_10_PCM2_RX { 0, 0, 0, 0 } -+#define LTQ_MUX_P1_10 { 0, 0, 1, 0 } -+#define LTQ_MUX_P1_10_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P1_9_PCM1_TC1 { 0, 0, 0, 0 } -+#define LTQ_MUX_P1_9 { 0, 0, 1, 0 } -+#define LTQ_MUX_P1_9_IN { 0, 0, 1, 0 } -+ -+#define LTQ_MUX_P1_8_PCM1_FSC { 0, 0, 0, 0 } -+#define LTQ_MUX_P1_8 { 0, 0, 1, 0 } -+#define LTQ_MUX_P1_8_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P1_7_PCM1_PCL { 0, 0, 0, 0 } -+#define LTQ_MUX_P1_7 { 0, 0, 1, 0 } -+#define LTQ_MUX_P1_7_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P1_6_PCM1_TX { 0, 0, 0, 0 } -+#define LTQ_MUX_P1_6 { 0, 0, 1, 0 } -+#define LTQ_MUX_P1_6_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P1_5_PCM1_RX { 0, 0, 0, 0 } -+#define LTQ_MUX_P1_5 { 0, 0, 1, 0 } -+#define LTQ_MUX_P1_5_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P1_4_PCM0_TC1 { 0, 0, 0, 0 } -+#define LTQ_MUX_P1_4 { 0, 0, 1, 0 } -+#define LTQ_MUX_P1_4_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P1_3_PCM0_FSC { 0, 0, 0, 0 } -+#define LTQ_MUX_P1_3 { 0, 0, 1, 0 } -+#define LTQ_MUX_P1_3_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P1_2_PCM0_PCL { 0, 0, 0, 0 } -+#define LTQ_MUX_P1_2 { 0, 0, 1, 0 } -+#define LTQ_MUX_P1_2_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P1_1_PCM0_TX { 0, 0, 0, 0 } -+#define LTQ_MUX_P1_1 { 0, 0, 1, 0 } -+#define LTQ_MUX_P1_1_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P1_0_PCM0_RX { 0, 0, 0, 0 } -+#define LTQ_MUX_P1_0 { 0, 0, 1, 0 } -+#define LTQ_MUX_P1_0_IN { 1, 0, 1, 0 } -+ -+ -+#define LTQ_MUX_P2_18_EBU_BC1 { 0, 0, 0, 0 } -+#define LTQ_MUX_P2_18 { 0, 0, 1, 0 } -+#define LTQ_MUX_P2_18_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P2_17_EBU_BC0 { 0, 0, 0, 0 } -+#define LTQ_MUX_P2_17 { 0, 0, 1, 0 } -+#define LTQ_MUX_P2_17_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P2_16_EBU_RDBY { 1, 0, 0, 0 } -+#define LTQ_MUX_P2_16 { 0, 0, 1, 0 } -+#define LTQ_MUX_P2_16_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P2_15_EBU_WAIT { 1, 0, 0, 0 } -+#define LTQ_MUX_P2_15 { 0, 0, 1, 0 } -+#define LTQ_MUX_P2_15_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P2_14_EBU_ALE { 0, 0, 0, 0 } -+#define LTQ_MUX_P2_14 { 0, 0, 1, 0 } -+#define LTQ_MUX_P2_14_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P2_13_EBU_WR { 0, 0, 0, 0 } -+#define LTQ_MUX_P2_13 { 0, 0, 1, 0 } -+#define LTQ_MUX_P2_13_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P2_12_EBU_RD { 0, 0, 0, 0 } -+#define LTQ_MUX_P2_12 { 0, 0, 1, 0 } -+#define LTQ_MUX_P2_12_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P2_11_EBU_A11 { 0, 0, 0, 0 } -+#define LTQ_MUX_P2_11 { 0, 0, 1, 0 } -+#define LTQ_MUX_P2_11_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P2_10_EBU_A10 { 0, 0, 0, 0 } -+#define LTQ_MUX_P2_10 { 0, 0, 1, 0 } -+#define LTQ_MUX_P2_10_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P2_9_EBU_A9 { 0, 0, 0, 0 } -+#define LTQ_MUX_P2_9 { 0, 0, 1, 0 } -+#define LTQ_MUX_P2_9_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P2_8_EBU_A8 { 0, 0, 0, 0 } -+#define LTQ_MUX_P2_8 { 0, 0, 1, 0 } -+#define LTQ_MUX_P2_8_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P2_7_EBU_A7 { 0, 0, 0, 0 } -+#define LTQ_MUX_P2_7 { 0, 0, 1, 0 } -+#define LTQ_MUX_P2_7_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P2_6_EBU_A6 { 0, 0, 0, 0 } -+#define LTQ_MUX_P2_6 { 0, 0, 1, 0 } -+#define LTQ_MUX_P2_6_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P2_5_EBU_A5 { 0, 0, 0, 0 } -+#define LTQ_MUX_P2_5 { 0, 0, 1, 0 } -+#define LTQ_MUX_P2_5_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P2_4_EBU_A4 { 0, 0, 0, 0 } -+#define LTQ_MUX_P2_4 { 0, 0, 1, 0 } -+#define LTQ_MUX_P2_4_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P2_3_EBU_A3 { 0, 0, 0, 0 } -+#define LTQ_MUX_P2_3 { 0, 0, 1, 0 } -+#define LTQ_MUX_P2_3_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P2_2_EBU_A2 { 0, 0, 0, 0 } -+#define LTQ_MUX_P2_2 { 0, 0, 1, 0 } -+#define LTQ_MUX_P2_2_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P2_1_EBU_A1 { 0, 0, 0, 0 } -+#define LTQ_MUX_P2_1 { 0, 0, 1, 0 } -+#define LTQ_MUX_P2_1_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P2_0_EBU_A0 { 0, 0, 0, 0 } -+#define LTQ_MUX_P2_0 { 0, 0, 1, 0 } -+#define LTQ_MUX_P2_0_IN { 1, 0, 1, 0 } -+ -+ -+#define LTQ_MUX_P3_19_EBU_CS3 { 0, 0, 0, 0 } -+#define LTQ_MUX_P3_19 { 0, 0, 1, 0 } -+#define LTQ_MUX_P3_19_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P3_18_EBU_CS2 { 0, 0, 0, 0 } -+#define LTQ_MUX_P3_18 { 0, 0, 1, 0 } -+#define LTQ_MUX_P3_18_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P3_17_EBU_CS1 { 0, 0, 0, 0 } -+#define LTQ_MUX_P3_17 { 0, 0, 1, 0 } -+#define LTQ_MUX_P3_17_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P3_16_EBU_CS0 { 0, 0, 0, 0 } -+#define LTQ_MUX_P3_16 { 0, 0, 1, 0 } -+#define LTQ_MUX_P3_16_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P3_15_EBU_AD15 { 1, 0, 0, 0 } -+#define LTQ_MUX_P3_15 { 0, 0, 1, 0 } -+#define LTQ_MUX_P3_15_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P3_14_EBU_AD14 { 1, 0, 0, 0 } -+#define LTQ_MUX_P3_14 { 0, 0, 1, 0 } -+#define LTQ_MUX_P3_14_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P3_13_EBU_AD13 { 1, 0, 0, 0 } -+#define LTQ_MUX_P3_13 { 0, 0, 1, 0 } -+#define LTQ_MUX_P3_13_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P3_12_EBU_AD12 { 1, 0, 0, 0 } -+#define LTQ_MUX_P3_12 { 0, 0, 1, 0 } -+#define LTQ_MUX_P3_12_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P3_11_EBU_AD11 { 1, 0, 0, 0 } -+#define LTQ_MUX_P3_11 { 0, 0, 1, 0 } -+#define LTQ_MUX_P3_11_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P3_10_EBU_AD10 { 1, 0, 0, 0 } -+#define LTQ_MUX_P3_10 { 0, 0, 1, 0 } -+#define LTQ_MUX_P3_10_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P3_9_EBU_AD9 { 1, 0, 0, 0 } -+#define LTQ_MUX_P3_9 { 0, 0, 1, 0 } -+#define LTQ_MUX_P3_9_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P3_8_EBU_AD8 { 1, 0, 0, 0 } -+#define LTQ_MUX_P3_8 { 0, 0, 1, 0 } -+#define LTQ_MUX_P3_8_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P3_7_EBU_AD7 { 1, 0, 0, 0 } -+#define LTQ_MUX_P3_7 { 0, 0, 1, 0 } -+#define LTQ_MUX_P3_7_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P3_6_EBU_AD6 { 1, 0, 0, 0 } -+#define LTQ_MUX_P3_6 { 0, 0, 1, 0 } -+#define LTQ_MUX_P3_6_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P3_5_EBU_AD5 { 1, 0, 0, 0 } -+#define LTQ_MUX_P3_5 { 0, 0, 1, 0 } -+#define LTQ_MUX_P3_5_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P3_4_EBU_AD4 { 1, 0, 0, 0 } -+#define LTQ_MUX_P3_4 { 0, 0, 1, 0 } -+#define LTQ_MUX_P3_4_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P3_3_EBU_AD3 { 1, 0, 0, 0 } -+#define LTQ_MUX_P3_3 { 0, 0, 1, 0 } -+#define LTQ_MUX_P3_3_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P3_2_EBU_AD2 { 1, 0, 0, 0 } -+#define LTQ_MUX_P3_2 { 0, 0, 1, 0 } -+#define LTQ_MUX_P3_2_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P3_1_EBU_AD1 { 1, 0, 0, 0 } -+#define LTQ_MUX_P3_1 { 0, 0, 1, 0 } -+#define LTQ_MUX_P3_1_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P3_0_EBU_AD0 { 1, 0, 0, 0 } -+#define LTQ_MUX_P3_0 { 0, 0, 1, 0 } -+#define LTQ_MUX_P3_0_IN { 1, 0, 1, 0 } -+ -+ -+#define LTQ_MUX_P4_23_SSLIC7_CLK { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_23 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_23_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_22_SSLIC7_RX { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_22 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_22_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_21_SSLIC7_TX { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_21 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_21_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_20_SSLIC6_CLK { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_20 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_20_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_19_SSLIC6_RX { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_19 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_19_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_18_SSLIC6_TX { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_18 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_18_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_17_SSLIC5_CLK { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_17 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_17_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_16_SSLIC5_RX { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_16 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_16_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_15_SSLIC5_TX { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_15 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_15_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_14_SSLIC4_CLK { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_14 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_14_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_13_SSLIC4_RX { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_13 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_13_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_12_SSLIC4_TX { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_12 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_12_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_11_SSLIC3_CLK { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_11 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_11_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_10_SSLIC3_RX { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_10 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_10_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_9_SSLIC3_TX { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_9 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_9_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_8_SSLIC2_CLK { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_8 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_8_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_7_SSLIC2_RX { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_7 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_7_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_6_SSLIC2_TX { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_6 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_6_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_5_SSLIC1_CLK { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_5 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_5_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_4_SSLIC1_RX { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_4 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_4_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_3_SSLIC1_TX { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_3 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_3_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_2_SSLIC0_CLK { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_2 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_2_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_1_SSLIC0_RX { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_1 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_1_IN { 1, 0, 1, 0 } -+ -+#define LTQ_MUX_P4_0_SSLIC0_TX { 0, 0, 0, 0 } -+#define LTQ_MUX_P4_0 { 0, 0, 1, 0 } -+#define LTQ_MUX_P4_0_IN { 1, 0, 1, 0 } -+ -+#endif -Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/sys2_reg.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/sys2_reg.h 2012-07-31 15:46:02.484476159 +0200 -@@ -0,0 +1,494 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2007 -+ Infineon Technologies AG -+ St. Martin Strasse 53; 81669 Munich, Germany -+ -+ Any use of this Software is subject to the conclusion of a respective -+ License Agreement. Without such a License Agreement no rights to the -+ Software are granted. -+ -+ ******************************************************************************/ -+ -+#ifndef __SYS2_REG_H -+#define __SYS2_REG_H -+ -+#define sys2_r32(reg) ltq_r32(&sys2->reg) -+#define sys2_w32(val, reg) ltq_w32(val, &sys2->reg) -+#define sys2_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys2->reg) -+ -+/** SYS2 register structure */ -+struct svip_reg_sys2 { -+ volatile unsigned long clksr; /* 0x0000 */ -+ volatile unsigned long clkenr; /* 0x0004 */ -+ volatile unsigned long clkclr; /* 0x0008 */ -+ volatile unsigned long reserved0[1]; -+ volatile unsigned long rsr; /* 0x0010 */ -+ volatile unsigned long rreqr; /* 0x0014 */ -+ volatile unsigned long rrlsr; /* 0x0018 */ -+}; -+ -+/******************************************************************************* -+ * SYS2 Clock Status Register -+ ******************************************************************************/ -+ -+/* Clock Enable for PORT4 */ -+#define SYS2_CLKSR_PORT4 (0x1 << 27) -+#define SYS2_CLKSR_PORT4_VAL(val) (((val) & 0x1) << 27) -+#define SYS2_CLKSR_PORT4_GET(val) (((val) & SYS2_CLKSR_PORT4) >> 27) -+/* Clock Enable for HWSYNC */ -+#define SYS2_CLKSR_HWSYNC (0x1 << 26) -+#define SYS2_CLKSR_HWSYNC_VAL(val) (((val) & -+#define SYS2_CLKSR_HWSYNC_GET(val) (((val) & SYS2_CLKSR_HWSYNC) >> 26) -+ /* Clock Enable for MBS */ -+#define SYS2_CLKSR_MBS (0x1 << 25) -+#define SYS2_CLKSR_MBS_VAL(val) (((val) & 0x1) << 25) -+#define SYS2_CLKSR_MBS_GET(val) (((val) & SYS2_CLKSR_MBS) >> 25) -+ /* Clock Enable for SWINT */ -+#define SYS2_CLKSR_SWINT (0x1 << 24) -+#define SYS2_CLKSR_SWINT_VAL(val) (((val) & 0x1) << 24) -+#define SYS2_CLKSR_SWINT_GET(val) (((val) & SYS2_CLKSR_SWINT) >> 24) -+ /* Clock Enable for HWACC3 */ -+#define SYS2_CLKSR_HWACC3 (0x1 << 19) -+#define SYS2_CLKSR_HWACC3_VAL(val) (((val) & -+#define SYS2_CLKSR_HWACC3_GET(val) (((val) & SYS2_CLKSR_HWACC3) >> 19) -+ /* Clock Enable for HWACC2 */ -+#define SYS2_CLKSR_HWACC2 (0x1 << 18) -+#define SYS2_CLKSR_HWACC2_VAL(val) (((val) & -+#define SYS2_CLKSR_HWACC2_GET(val) (((val) & SYS2_CLKSR_HWACC2) >> 18) -+ /* Clock Enable for HWACC1 */ -+#define SYS2_CLKSR_HWACC1 (0x1 << 17) -+#define SYS2_CLKSR_HWACC1_VAL(val) (((val) & -+#define SYS2_CLKSR_HWACC1_GET(val) (((val) & SYS2_CLKSR_HWACC1) >> 17) -+ /* Clock Enable for HWACC0 */ -+#define SYS2_CLKSR_HWACC0 (0x1 << 16) -+#define SYS2_CLKSR_HWACC0_VAL(val) (((val) & -+#define SYS2_CLKSR_HWACC0_GET(val) (((val) & SYS2_CLKSR_HWACC0) >> 16) -+ /* Clock Enable for SIF7 */ -+#define SYS2_CLKSR_SIF7 (0x1 << 15) -+#define SYS2_CLKSR_SIF7_VAL(val) (((val) & 0x1) << 15) -+#define SYS2_CLKSR_SIF7_GET(val) (((val) & SYS2_CLKSR_SIF7) >> 15) -+ /* Clock Enable for SIF6 */ -+#define SYS2_CLKSR_SIF6 (0x1 << 14) -+#define SYS2_CLKSR_SIF6_VAL(val) (((val) & 0x1) << 14) -+#define SYS2_CLKSR_SIF6_GET(val) (((val) & SYS2_CLKSR_SIF6) >> 14) -+ /* Clock Enable for SIF5 */ -+#define SYS2_CLKSR_SIF5 (0x1 << 13) -+#define SYS2_CLKSR_SIF5_VAL(val) (((val) & 0x1) << 13) -+#define SYS2_CLKSR_SIF5_GET(val) (((val) & SYS2_CLKSR_SIF5) >> 13) -+ /* Clock Enable for SIF4 */ -+#define SYS2_CLKSR_SIF4 (0x1 << 12) -+#define SYS2_CLKSR_SIF4_VAL(val) (((val) & 0x1) << 12) -+#define SYS2_CLKSR_SIF4_GET(val) (((val) & SYS2_CLKSR_SIF4) >> 12) -+ /* Clock Enable for SIF3 */ -+#define SYS2_CLKSR_SIF3 (0x1 << 11) -+#define SYS2_CLKSR_SIF3_VAL(val) (((val) & 0x1) << 11) -+#define SYS2_CLKSR_SIF3_GET(val) (((val) & SYS2_CLKSR_SIF3) >> 11) -+/* Clock Enable for SIF2 */ -+#define SYS2_CLKSR_SIF2 (0x1 << 10) -+#define SYS2_CLKSR_SIF2_VAL(val) (((val) & 0x1) << 10) -+#define SYS2_CLKSR_SIF2_GET(val) (((val) & SYS2_CLKSR_SIF2) >> 10) -+/* Clock Enable for SIF1 */ -+#define SYS2_CLKSR_SIF1 (0x1 << 9) -+#define SYS2_CLKSR_SIF1_VAL(val) (((val) & 0x1) << 9) -+#define SYS2_CLKSR_SIF1_GET(val) (((val) & SYS2_CLKSR_SIF1) >> 9) -+/* Clock Enable for SIF0 */ -+#define SYS2_CLKSR_SIF0 (0x1 << 8) -+#define SYS2_CLKSR_SIF0_VAL(val) (((val) & 0x1) << 8) -+#define SYS2_CLKSR_SIF0_GET(val) (((val) & SYS2_CLKSR_SIF0) >> 8) -+/* Clock Enable for DFEV7 */ -+#define SYS2_CLKSR_DFEV7 (0x1 << 7) -+#define SYS2_CLKSR_DFEV7_VAL(val) (((val) & 0x1) << 7) -+#define SYS2_CLKSR_DFEV7_GET(val) (((val) & SYS2_CLKSR_DFEV7) >> 7) -+/* Clock Enable for DFEV6 */ -+#define SYS2_CLKSR_DFEV6 (0x1 << 6) -+#define SYS2_CLKSR_DFEV6_VAL(val) (((val) & 0x1) << 6) -+#define SYS2_CLKSR_DFEV6_GET(val) (((val) & SYS2_CLKSR_DFEV6) >> 6) -+/* Clock Enable for DFEV5 */ -+#define SYS2_CLKSR_DFEV5 (0x1 << 5) -+#define SYS2_CLKSR_DFEV5_VAL(val) (((val) & 0x1) << 5) -+#define SYS2_CLKSR_DFEV5_GET(val) (((val) & SYS2_CLKSR_DFEV5) >> 5) -+/* Clock Enable for DFEV4 */ -+#define SYS2_CLKSR_DFEV4 (0x1 << 4) -+#define SYS2_CLKSR_DFEV4_VAL(val) (((val) & 0x1) << 4) -+#define SYS2_CLKSR_DFEV4_GET(val) (((val) & SYS2_CLKSR_DFEV4) >> 4) -+/* Clock Enable for DFEV3 */ -+#define SYS2_CLKSR_DFEV3 (0x1 << 3) -+#define SYS2_CLKSR_DFEV3_VAL(val) (((val) & 0x1) << 3) -+#define SYS2_CLKSR_DFEV3_GET(val) (((val) & SYS2_CLKSR_DFEV3) >> 3) -+/* Clock Enable for DFEV2 */ -+#define SYS2_CLKSR_DFEV2 (0x1 << 2) -+#define SYS2_CLKSR_DFEV2_VAL(val) (((val) & 0x1) << 2) -+#define SYS2_CLKSR_DFEV2_GET(val) (((val) & SYS2_CLKSR_DFEV2) >> 2) -+/* Clock Enable for DFEV1 */ -+#define SYS2_CLKSR_DFEV1 (0x1 << 1) -+#define SYS2_CLKSR_DFEV1_VAL(val) (((val) & 0x1) << 1) -+#define SYS2_CLKSR_DFEV1_GET(val) (((val) & SYS2_CLKSR_DFEV1) >> 1) -+/* Clock Enable for DFEV0 */ -+#define SYS2_CLKSR_DFEV0 (0x1) -+#define SYS2_CLKSR_DFEV0_VAL(val) (((val) & 0x1)) -+#define SYS2_CLKSR_DFEV0_GET(val) ((val) & SYS2_CLKSR_DFEV0) -+ -+/******************************************************************************* -+ * SYS2 Clock Enable Register -+ ******************************************************************************/ -+ -+/* Clock Enable Request for PORT4 */ -+#define SYS2_CLKENR_PORT4 (0x1 << 27) -+#define SYS2_CLKENR_PORT4_VAL(val) (((val) & 0x1) << 27) -+#define SYS2_CLKENR_PORT4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_PORT4) | ((val & 0x1) << 27)) -+/* Clock Enable Request for HWSYNC */ -+#define SYS2_CLKENR_HWSYNC (0x1 << 26) -+#define SYS2_CLKENR_HWSYNC_VAL(val) (((val) & 0x1) << 26) -+#define SYS2_CLKENR_HWSYNC_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWSYNC) | ((val & 0x1) << 26)) -+/* Clock Enable Request for MBS */ -+#define SYS2_CLKENR_MBS (0x1 << 25) -+#define SYS2_CLKENR_MBS_VAL(val) (((val) & 0x1) << 25) -+#define SYS2_CLKENR_MBS_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_MBS) | ((val & 0x1) << 25)) -+/* Clock Enable Request for SWINT */ -+#define SYS2_CLKENR_SWINT (0x1 << 24) -+#define SYS2_CLKENR_SWINT_VAL(val) (((val) & 0x1) << 24) -+#define SYS2_CLKENR_SWINT_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SWINT) | ((val & 0x1) << 24)) -+/* Clock Enable Request for HWACC3 */ -+#define SYS2_CLKENR_HWACC3 (0x1 << 19) -+#define SYS2_CLKENR_HWACC3_VAL(val) (((val) & 0x1) << 19) -+#define SYS2_CLKENR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC3) | ((val & 0x1) << 19)) -+/* Clock Enable Request for HWACC2 */ -+#define SYS2_CLKENR_HWACC2 (0x1 << 18) -+#define SYS2_CLKENR_HWACC2_VAL(val) (((val) & 0x1) << 18) -+#define SYS2_CLKENR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC2) | ((val & 0x1) << 18)) -+/* Clock Enable Request for HWACC1 */ -+#define SYS2_CLKENR_HWACC1 (0x1 << 17) -+#define SYS2_CLKENR_HWACC1_VAL(val) (((val) & 0x1) << 17) -+#define SYS2_CLKENR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC1) | ((val & 0x1) << 17)) -+/* Clock Enable Request for HWACC0 */ -+#define SYS2_CLKENR_HWACC0 (0x1 << 16) -+#define SYS2_CLKENR_HWACC0_VAL(val) (((val) & 0x1) << 16) -+#define SYS2_CLKENR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC0) | ((val & 0x1) << 16)) -+/* Clock Enable Request for SIF7 */ -+#define SYS2_CLKENR_SIF7 (0x1 << 15) -+#define SYS2_CLKENR_SIF7_VAL(val) (((val) & 0x1) << 15) -+#define SYS2_CLKENR_SIF7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF7) | ((val & 0x1) << 15)) -+/* Clock Enable Request for SIF6 */ -+#define SYS2_CLKENR_SIF6 (0x1 << 14) -+#define SYS2_CLKENR_SIF6_VAL(val) (((val) & 0x1) << 14) -+#define SYS2_CLKENR_SIF6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF6) | ((val & 0x1) << 14)) -+/* Clock Enable Request for SIF5 */ -+#define SYS2_CLKENR_SIF5 (0x1 << 13) -+#define SYS2_CLKENR_SIF5_VAL(val) (((val) & 0x1) << 13) -+#define SYS2_CLKENR_SIF5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF5) | ((val & 0x1) << 13)) -+/* Clock Enable Request for SIF4 */ -+#define SYS2_CLKENR_SIF4 (0x1 << 12) -+#define SYS2_CLKENR_SIF4_VAL(val) (((val) & 0x1) << 12) -+#define SYS2_CLKENR_SIF4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF4) | ((val & 0x1) << 12)) -+/* Clock Enable Request for SIF3 */ -+#define SYS2_CLKENR_SIF3 (0x1 << 11) -+#define SYS2_CLKENR_SIF3_VAL(val) (((val) & 0x1) << 11) -+#define SYS2_CLKENR_SIF3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF3) | ((val & 0x1) << 11)) -+/* Clock Enable Request for SIF2 */ -+#define SYS2_CLKENR_SIF2 (0x1 << 10) -+#define SYS2_CLKENR_SIF2_VAL(val) (((val) & 0x1) << 10) -+#define SYS2_CLKENR_SIF2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF2) | ((val & 0x1) << 10)) -+/* Clock Enable Request for SIF1 */ -+#define SYS2_CLKENR_SIF1 (0x1 << 9) -+#define SYS2_CLKENR_SIF1_VAL(val) (((val) & 0x1) << 9) -+#define SYS2_CLKENR_SIF1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF1) | ((val & 0x1) << 9)) -+/* Clock Enable Request for SIF0 */ -+#define SYS2_CLKENR_SIF0 (0x1 << 8) -+#define SYS2_CLKENR_SIF0_VAL(val) (((val) & 0x1) << 8) -+#define SYS2_CLKENR_SIF0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF0) | ((val & 0x1) << 8)) -+/* Clock Enable Request for DFEV7 */ -+#define SYS2_CLKENR_DFEV7 (0x1 << 7) -+#define SYS2_CLKENR_DFEV7_VAL(val) (((val) & 0x1) << 7) -+#define SYS2_CLKENR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV7) | ((val & 0x1) << 7)) -+/* Clock Enable Request for DFEV6 */ -+#define SYS2_CLKENR_DFEV6 (0x1 << 6) -+#define SYS2_CLKENR_DFEV6_VAL(val) (((val) & 0x1) << 6) -+#define SYS2_CLKENR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV6) | ((val & 0x1) << 6)) -+/* Clock Enable Request for DFEV5 */ -+#define SYS2_CLKENR_DFEV5 (0x1 << 5) -+#define SYS2_CLKENR_DFEV5_VAL(val) (((val) & 0x1) << 5) -+#define SYS2_CLKENR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV5) | ((val & 0x1) << 5)) -+/* Clock Enable Request for DFEV4 */ -+#define SYS2_CLKENR_DFEV4 (0x1 << 4) -+#define SYS2_CLKENR_DFEV4_VAL(val) (((val) & 0x1) << 4) -+#define SYS2_CLKENR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV4) | ((val & 0x1) << 4)) -+/* Clock Enable Request for DFEV3 */ -+#define SYS2_CLKENR_DFEV3 (0x1 << 3) -+#define SYS2_CLKENR_DFEV3_VAL(val) (((val) & 0x1) << 3) -+#define SYS2_CLKENR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV3) | ((val & 0x1) << 3)) -+/* Clock Enable Request for DFEV2 */ -+#define SYS2_CLKENR_DFEV2 (0x1 << 2) -+#define SYS2_CLKENR_DFEV2_VAL(val) (((val) & 0x1) << 2) -+#define SYS2_CLKENR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV2) | ((val & 0x1) << 2)) -+/* Clock Enable Request for DFEV1 */ -+#define SYS2_CLKENR_DFEV1 (0x1 << 1) -+#define SYS2_CLKENR_DFEV1_VAL(val) (((val) & 0x1) << 1) -+#define SYS2_CLKENR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV1) | ((val & 0x1) << 1)) -+/* Clock Enable Request for DFEV0 */ -+#define SYS2_CLKENR_DFEV0 (0x1) -+#define SYS2_CLKENR_DFEV0_VAL(val) (((val) & 0x1)) -+#define SYS2_CLKENR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV0) | ((val & 0x1))) -+ -+/******************************************************************************* -+ * SYS2 Clock Clear Register -+ ******************************************************************************/ -+ -+/* Clock Disable Request for PORT4 */ -+#define SYS2_CLKCLR_PORT4 (0x1 << 27) -+#define SYS2_CLKCLR_PORT4_VAL(val) (((val) & 0x1) << 27) -+#define SYS2_CLKCLR_PORT4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_PORT4) | ((val & 0x1) << 27)) -+/* Clock Disable Request for HWSYNC */ -+#define SYS2_CLKCLR_HWSYNC (0x1 << 26) -+#define SYS2_CLKCLR_HWSYNC_VAL(val) (((val) & 0x1) << 26) -+#define SYS2_CLKCLR_HWSYNC_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWSYNC) | ((val & 0x1) << 26)) -+/* Clock Disable Request for MBS */ -+#define SYS2_CLKCLR_MBS (0x1 << 25) -+#define SYS2_CLKCLR_MBS_VAL(val) (((val) & 0x1) << 25) -+#define SYS2_CLKCLR_MBS_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_MBS) | ((val & 0x1) << 25)) -+/* Clock Disable Request for SWINT */ -+#define SYS2_CLKCLR_SWINT (0x1 << 24) -+#define SYS2_CLKCLR_SWINT_VAL(val) (((val) & 0x1) << 24) -+#define SYS2_CLKCLR_SWINT_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SWINT) | ((val & 0x1) << 24)) -+/* Clock Disable Request for HWACC3 */ -+#define SYS2_CLKCLR_HWACC3 (0x1 << 19) -+#define SYS2_CLKCLR_HWACC3_VAL(val) (((val) & 0x1) << 19) -+#define SYS2_CLKCLR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC3) | ((val & 0x1) << 19)) -+/* Clock Disable Request for HWACC2 */ -+#define SYS2_CLKCLR_HWACC2 (0x1 << 18) -+#define SYS2_CLKCLR_HWACC2_VAL(val) (((val) & 0x1) << 18) -+#define SYS2_CLKCLR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC2) | ((val & 0x1) << 18)) -+/* Clock Disable Request for HWACC1 */ -+#define SYS2_CLKCLR_HWACC1 (0x1 << 17) -+#define SYS2_CLKCLR_HWACC1_VAL(val) (((val) & 0x1) << 17) -+#define SYS2_CLKCLR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC1) | ((val & 0x1) << 17)) -+/* Clock Disable Request for HWACC0 */ -+#define SYS2_CLKCLR_HWACC0 (0x1 << 16) -+#define SYS2_CLKCLR_HWACC0_VAL(val) (((val) & 0x1) << 16) -+#define SYS2_CLKCLR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC0) | ((val & 0x1) << 16)) -+/* Clock Disable Request for SIF7 */ -+#define SYS2_CLKCLR_SIF7 (0x1 << 15) -+#define SYS2_CLKCLR_SIF7_VAL(val) (((val) & 0x1) << 15) -+#define SYS2_CLKCLR_SIF7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF7) | ((val & 0x1) << 15)) -+/* Clock Disable Request for SIF6 */ -+#define SYS2_CLKCLR_SIF6 (0x1 << 14) -+#define SYS2_CLKCLR_SIF6_VAL(val) (((val) & 0x1) << 14) -+#define SYS2_CLKCLR_SIF6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF6) | ((val & 0x1) << 14)) -+/* Clock Disable Request for SIF5 */ -+#define SYS2_CLKCLR_SIF5 (0x1 << 13) -+#define SYS2_CLKCLR_SIF5_VAL(val) (((val) & 0x1) << 13) -+#define SYS2_CLKCLR_SIF5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF5) | ((val & 0x1) << 13)) -+/* Clock Disable Request for SIF4 */ -+#define SYS2_CLKCLR_SIF4 (0x1 << 12) -+#define SYS2_CLKCLR_SIF4_VAL(val) (((val) & 0x1) << 12) -+#define SYS2_CLKCLR_SIF4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF4) | ((val & 0x1) << 12)) -+/* Clock Disable Request for SIF3 */ -+#define SYS2_CLKCLR_SIF3 (0x1 << 11) -+#define SYS2_CLKCLR_SIF3_VAL(val) (((val) & 0x1) << 11) -+#define SYS2_CLKCLR_SIF3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF3) | ((val & 0x1) << 11)) -+/* Clock Disable Request for SIF2 */ -+#define SYS2_CLKCLR_SIF2 (0x1 << 10) -+#define SYS2_CLKCLR_SIF2_VAL(val) (((val) & 0x1) << 10) -+#define SYS2_CLKCLR_SIF2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF2) | ((val & 0x1) << 10)) -+/* Clock Disable Request for SIF1 */ -+#define SYS2_CLKCLR_SIF1 (0x1 << 9) -+#define SYS2_CLKCLR_SIF1_VAL(val) (((val) & 0x1) << 9) -+#define SYS2_CLKCLR_SIF1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF1) | ((val & 0x1) << 9)) -+/* Clock Disable Request for SIF0 */ -+#define SYS2_CLKCLR_SIF0 (0x1 << 8) -+#define SYS2_CLKCLR_SIF0_VAL(val) (((val) & 0x1) << 8) -+#define SYS2_CLKCLR_SIF0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF0) | ((val & 0x1) << 8)) -+/* Clock Disable Request for DFEV7 */ -+#define SYS2_CLKCLR_DFEV7 (0x1 << 7) -+#define SYS2_CLKCLR_DFEV7_VAL(val) (((val) & 0x1) << 7) -+#define SYS2_CLKCLR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV7) | ((val & 0x1) << 7)) -+/* Clock Disable Request for DFEV6 */ -+#define SYS2_CLKCLR_DFEV6 (0x1 << 6) -+#define SYS2_CLKCLR_DFEV6_VAL(val) (((val) & 0x1) << 6) -+#define SYS2_CLKCLR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV6) | ((val & 0x1) << 6)) -+/* Clock Disable Request for DFEV5 */ -+#define SYS2_CLKCLR_DFEV5 (0x1 << 5) -+#define SYS2_CLKCLR_DFEV5_VAL(val) (((val) & 0x1) << 5) -+#define SYS2_CLKCLR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV5) | ((val & 0x1) << 5)) -+/* Clock Disable Request for DFEV4 */ -+#define SYS2_CLKCLR_DFEV4 (0x1 << 4) -+#define SYS2_CLKCLR_DFEV4_VAL(val) (((val) & 0x1) << 4) -+#define SYS2_CLKCLR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV4) | ((val & 0x1) << 4)) -+/* Clock Disable Request for DFEV3 */ -+#define SYS2_CLKCLR_DFEV3 (0x1 << 3) -+#define SYS2_CLKCLR_DFEV3_VAL(val) (((val) & 0x1) << 3) -+#define SYS2_CLKCLR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV3) | ((val & 0x1) << 3)) -+/* Clock Disable Request for DFEV2 */ -+#define SYS2_CLKCLR_DFEV2 (0x1 << 2) -+#define SYS2_CLKCLR_DFEV2_VAL(val) (((val) & 0x1) << 2) -+#define SYS2_CLKCLR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV2) | ((val & 0x1) << 2)) -+/* Clock Disable Request for DFEV1 */ -+#define SYS2_CLKCLR_DFEV1 (0x1 << 1) -+#define SYS2_CLKCLR_DFEV1_VAL(val) (((val) & 0x1) << 1) -+#define SYS2_CLKCLR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV1) | ((val & 0x1) << 1)) -+/* Clock Disable Request for DFEV0 */ -+#define SYS2_CLKCLR_DFEV0 (0x1) -+#define SYS2_CLKCLR_DFEV0_VAL(val) (((val) & 0x1)) -+#define SYS2_CLKCLR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV0) | ((val & 0x1))) -+ -+/******************************************************************************* -+ * SYS2 Reset Status Register -+ ******************************************************************************/ -+ -+/* HWACC3 Reset */ -+#define SYS2_RSR_HWACC3 (0x1 << 11) -+#define SYS2_RSR_HWACC3_VAL(val) (((val) & 0x1) << 11) -+#define SYS2_RSR_HWACC3_GET(val) (((val) & SYS2_RSR_HWACC3) >> 11) -+/* HWACC2 Reset */ -+#define SYS2_RSR_HWACC2 (0x1 << 10) -+#define SYS2_RSR_HWACC2_VAL(val) (((val) & 0x1) << 10) -+#define SYS2_RSR_HWACC2_GET(val) (((val) & SYS2_RSR_HWACC2) >> 10) -+/* HWACC1 Reset */ -+#define SYS2_RSR_HWACC1 (0x1 << 9) -+#define SYS2_RSR_HWACC1_VAL(val) (((val) & 0x1) << 9) -+#define SYS2_RSR_HWACC1_GET(val) (((val) & SYS2_RSR_HWACC1) >> 9) -+/* HWACC0 Reset */ -+#define SYS2_RSR_HWACC0 (0x1 << 8) -+#define SYS2_RSR_HWACC0_VAL(val) (((val) & 0x1) << 8) -+#define SYS2_RSR_HWACC0_GET(val) (((val) & SYS2_RSR_HWACC0) >> 8) -+/* DFEV7 Reset */ -+#define SYS2_RSR_DFEV7 (0x1 << 7) -+#define SYS2_RSR_DFEV7_VAL(val) (((val) & 0x1) << 7) -+#define SYS2_RSR_DFEV7_GET(val) (((val) & SYS2_RSR_DFEV7) >> 7) -+/* DFEV6 Reset */ -+#define SYS2_RSR_DFEV6 (0x1 << 6) -+#define SYS2_RSR_DFEV6_VAL(val) (((val) & 0x1) << 6) -+#define SYS2_RSR_DFEV6_GET(val) (((val) & SYS2_RSR_DFEV6) >> 6) -+/* DFEV5 Reset */ -+#define SYS2_RSR_DFEV5 (0x1 << 5) -+#define SYS2_RSR_DFEV5_VAL(val) (((val) & 0x1) << 5) -+#define SYS2_RSR_DFEV5_GET(val) (((val) & SYS2_RSR_DFEV5) >> 5) -+/* DFEV4 Reset */ -+#define SYS2_RSR_DFEV4 (0x1 << 4) -+#define SYS2_RSR_DFEV4_VAL(val) (((val) & 0x1) << 4) -+#define SYS2_RSR_DFEV4_GET(val) (((val) & SYS2_RSR_DFEV4) >> 4) -+/* DFEV3 Reset */ -+#define SYS2_RSR_DFEV3 (0x1 << 3) -+#define SYS2_RSR_DFEV3_VAL(val) (((val) & 0x1) << 3) -+#define SYS2_RSR_DFEV3_GET(val) (((val) & SYS2_RSR_DFEV3) >> 3) -+/* DFEV2 Reset */ -+#define SYS2_RSR_DFEV2 (0x1 << 2) -+#define SYS2_RSR_DFEV2_VAL(val) (((val) & 0x1) << 2) -+#define SYS2_RSR_DFEV2_GET(val) (((val) & SYS2_RSR_DFEV2) >> 2) -+/* DFEV1 Reset */ -+#define SYS2_RSR_DFEV1 (0x1 << 1) -+#define SYS2_RSR_DFEV1_VAL(val) (((val) & 0x1) << 1) -+#define SYS2_RSR_DFEV1_GET(val) (((val) & SYS2_RSR_DFEV1) >> 1) -+/* DFEV0 Reset */ -+#define SYS2_RSR_DFEV0 (0x1) -+#define SYS2_RSR_DFEV0_VAL(val) (((val) & 0x1)) -+#define SYS2_RSR_DFEV0_GET(val) ((val) & SYS2_RSR_DFEV0) -+ -+/****************************************************************************** -+ * SYS2 Reset Request Register -+ ******************************************************************************/ -+ -+/* HWACC3 Reset Request */ -+#define SYS2_RREQR_HWACC3 (0x1 << 11) -+#define SYS2_RREQR_HWACC3_VAL(val) (((val) & 0x1) << 11) -+#define SYS2_RREQR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC3) | ((val & 0x1) << 11)) -+/* HWACC2 Reset Request */ -+#define SYS2_RREQR_HWACC2 (0x1 << 10) -+#define SYS2_RREQR_HWACC2_VAL(val) (((val) & 0x1) << 10) -+#define SYS2_RREQR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC2) | ((val & 0x1) << 10)) -+/* HWACC1 Reset Request */ -+#define SYS2_RREQR_HWACC1 (0x1 << 9) -+#define SYS2_RREQR_HWACC1_VAL(val) (((val) & 0x1) << 9) -+#define SYS2_RREQR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC1) | ((val & 0x1) << 9)) -+/* HWACC0 Reset Request */ -+#define SYS2_RREQR_HWACC0 (0x1 << 8) -+#define SYS2_RREQR_HWACC0_VAL(val) (((val) & 0x1) << 8) -+#define SYS2_RREQR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC0) | ((val & 0x1) << 8)) -+/* DFEV7 Reset Request */ -+#define SYS2_RREQR_DFEV7 (0x1 << 7) -+#define SYS2_RREQR_DFEV7_VAL(val) (((val) & 0x1) << 7) -+#define SYS2_RREQR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV7) | ((val & 0x1) << 7)) -+/* DFEV6 Reset Request */ -+#define SYS2_RREQR_DFEV6 (0x1 << 6) -+#define SYS2_RREQR_DFEV6_VAL(val) (((val) & 0x1) << 6) -+#define SYS2_RREQR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV6) | ((val & 0x1) << 6)) -+/* DFEV5 Reset Request */ -+#define SYS2_RREQR_DFEV5 (0x1 << 5) -+#define SYS2_RREQR_DFEV5_VAL(val) (((val) & 0x1) << 5) -+#define SYS2_RREQR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV5) | ((val & 0x1) << 5)) -+/* DFEV4 Reset Request */ -+#define SYS2_RREQR_DFEV4 (0x1 << 4) -+#define SYS2_RREQR_DFEV4_VAL(val) (((val) & 0x1) << 4) -+#define SYS2_RREQR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV4) | ((val & 0x1) << 4)) -+/* DFEV3 Reset Request */ -+#define SYS2_RREQR_DFEV3 (0x1 << 3) -+#define SYS2_RREQR_DFEV3_VAL(val) (((val) & 0x1) << 3) -+#define SYS2_RREQR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV3) | ((val & 0x1) << 3)) -+/* DFEV2 Reset Request */ -+#define SYS2_RREQR_DFEV2 (0x1 << 2) -+#define SYS2_RREQR_DFEV2_VAL(val) (((val) & 0x1) << 2) -+#define SYS2_RREQR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV2) | ((val & 0x1) << 2)) -+/* DFEV1 Reset Request */ -+#define SYS2_RREQR_DFEV1 (0x1 << 1) -+#define SYS2_RREQR_DFEV1_VAL(val) (((val) & 0x1) << 1) -+#define SYS2_RREQR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV1) | ((val & 0x1) << 1)) -+/* DFEV0 Reset Request */ -+#define SYS2_RREQR_DFEV0 (0x1) -+#define SYS2_RREQR_DFEV0_VAL(val) (((val) & 0x1)) -+#define SYS2_RREQR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV0) | ((val & 0x1))) -+ -+/******************************************************************************* -+ * SYS2 Reset Release Register -+ ******************************************************************************/ -+ -+/* HWACC3 Reset Release */ -+#define SYS2_RRLSR_HWACC3 (0x1 << 11) -+#define SYS2_RRLSR_HWACC3_VAL(val) (((val) & 0x1) << 11) -+#define SYS2_RRLSR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC3) | ((val & 0x1) << 11)) -+/* HWACC2 Reset Release */ -+#define SYS2_RRLSR_HWACC2 (0x1 << 10) -+#define SYS2_RRLSR_HWACC2_VAL(val) (((val) & 0x1) << 10) -+#define SYS2_RRLSR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC2) | ((val & 0x1) << 10)) -+/* HWACC1 Reset Release */ -+#define SYS2_RRLSR_HWACC1 (0x1 << 9) -+#define SYS2_RRLSR_HWACC1_VAL(val) (((val) & 0x1) << 9) -+#define SYS2_RRLSR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC1) | ((val & 0x1) << 9)) -+/* HWACC0 Reset Release */ -+#define SYS2_RRLSR_HWACC0 (0x1 << 8) -+#define SYS2_RRLSR_HWACC0_VAL(val) (((val) & 0x1) << 8) -+#define SYS2_RRLSR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC0) | ((val & 0x1) << 8)) -+/* DFEV7 Reset Release */ -+#define SYS2_RRLSR_DFEV7 (0x1 << 7) -+#define SYS2_RRLSR_DFEV7_VAL(val) (((val) & 0x1) << 7) -+#define SYS2_RRLSR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV7) | ((val & 0x1) << 7)) -+/* DFEV6 Reset Release */ -+#define SYS2_RRLSR_DFEV6 (0x1 << 6) -+#define SYS2_RRLSR_DFEV6_VAL(val) (((val) & 0x1) << 6) -+#define SYS2_RRLSR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV6) | ((val & 0x1) << 6)) -+/* DFEV5 Reset Release */ -+#define SYS2_RRLSR_DFEV5 (0x1 << 5) -+#define SYS2_RRLSR_DFEV5_VAL(val) (((val) & 0x1) << 5) -+#define SYS2_RRLSR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV5) | ((val & 0x1) << 5)) -+/* DFEV4 Reset Release */ -+#define SYS2_RRLSR_DFEV4 (0x1 << 4) -+#define SYS2_RRLSR_DFEV4_VAL(val) (((val) & 0x1) << 4) -+#define SYS2_RRLSR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV4) | ((val & 0x1) << 4)) -+/* DFEV3 Reset Release */ -+#define SYS2_RRLSR_DFEV3 (0x1 << 3) -+#define SYS2_RRLSR_DFEV3_VAL(val) (((val) & 0x1) << 3) -+#define SYS2_RRLSR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV3) | ((val & 0x1) << 3)) -+/* DFEV2 Reset Release */ -+#define SYS2_RRLSR_DFEV2 (0x1 << 2) -+#define SYS2_RRLSR_DFEV2_VAL(val) (((val) & 0x1) << 2) -+#define SYS2_RRLSR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV2) | ((val & 0x1) << 2)) -+/* DFEV1 Reset Release */ -+#define SYS2_RRLSR_DFEV1 (0x1 << 1) -+#define SYS2_RRLSR_DFEV1_VAL(val) (((val) & 0x1) << 1) -+#define SYS2_RRLSR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV1) | ((val & 0x1) << 1)) -+/* DFEV0 Reset Release */ -+#define SYS2_RRLSR_DFEV0 (0x1) -+#define SYS2_RRLSR_DFEV0_VAL(val) (((val) & 0x1)) -+#define SYS2_RRLSR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV0) | ((val & 0x1))) -+ -+#endif /* __SYS2_H */ -+ -Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/svip_pms.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/svip_pms.h 2012-07-31 15:46:02.484476159 +0200 -@@ -0,0 +1,23 @@ -+/************************************************************************ -+ * -+ * Copyright (c) 2007 -+ * Infineon Technologies AG -+ * St. Martin Strasse 53; 81669 Muenchen; Germany -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ * -+ ************************************************************************/ -+ -+#ifndef __SVIP_PMS_H -+#define __SVIP_PMS_H -+ -+void svip_sys1_clk_enable(u32 mask); -+int svip_sys1_clk_is_enabled(u32 mask); -+ -+void svip_sys2_clk_enable(u32 mask); -+int svip_sys2_clk_is_enabled(u32 mask); -+ -+#endif diff --git a/target/linux/lantiq/patches-3.3/310-svip_board.patch b/target/linux/lantiq/patches-3.3/310-svip_board.patch deleted file mode 100644 index f817c94ee9..0000000000 --- a/target/linux/lantiq/patches-3.3/310-svip_board.patch +++ /dev/null @@ -1,7636 +0,0 @@ -Index: linux-3.3.8/arch/mips/lantiq/Kconfig -=================================================================== ---- linux-3.3.8.orig/arch/mips/lantiq/Kconfig 2012-07-31 19:51:33.349105884 +0200 -+++ linux-3.3.8/arch/mips/lantiq/Kconfig 2012-07-31 19:51:34.133105918 +0200 -@@ -20,9 +20,14 @@ - config SOC_FALCON - bool "FALCON" - -+config SOC_SVIP -+ bool "SVIP" -+ select MIPS_CPU_SCACHE -+ - endchoice - - source "arch/mips/lantiq/xway/Kconfig" - source "arch/mips/lantiq/falcon/Kconfig" -+source "arch/mips/lantiq/svip/Kconfig" - - endif -Index: linux-3.3.8/arch/mips/lantiq/svip/Kconfig -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/lantiq/svip/Kconfig 2012-07-31 19:51:34.133105918 +0200 -@@ -0,0 +1,16 @@ -+if SOC_SVIP -+ -+menu "Mips Machine" -+ -+config LANTIQ_MACH_EASY33016 -+ bool "Easy33016" -+ default y -+ -+config LANTIQ_MACH_EASY336 -+ select SYS_SUPPORTS_LITTLE_ENDIAN -+ bool "Easy336" -+ default y -+ -+endmenu -+ -+endif -Index: linux-3.3.8/arch/mips/lantiq/Makefile -=================================================================== ---- linux-3.3.8.orig/arch/mips/lantiq/Makefile 2012-07-31 19:51:34.017105912 +0200 -+++ linux-3.3.8/arch/mips/lantiq/Makefile 2012-07-31 19:51:34.133105918 +0200 -@@ -10,3 +10,4 @@ - - obj-$(CONFIG_SOC_TYPE_XWAY) += xway/ - obj-$(CONFIG_SOC_FALCON) += falcon/ -+obj-$(CONFIG_SOC_SVIP) += svip/ -Index: linux-3.3.8/arch/mips/lantiq/svip/Makefile -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/lantiq/svip/Makefile 2012-07-31 19:51:34.133105918 +0200 -@@ -0,0 +1,3 @@ -+obj-y := devices.o prom.o reset.o clk-svip.o gpio.o dma.o switchip_setup.o pms.o mux.o -+obj-$(CONFIG_LANTIQ_MACH_EASY33016) += mach-easy33016.o -+obj-$(CONFIG_LANTIQ_MACH_EASY336) += mach-easy336.o -Index: linux-3.3.8/arch/mips/lantiq/svip/devices.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/lantiq/svip/devices.c 2012-07-31 19:51:34.137105918 +0200 -@@ -0,0 +1,385 @@ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+ -+#include -+#include -+#include -+#include -+ -+#include "devices.h" -+ -+#include -+#include -+#include -+ -+/* ASC */ -+void __init svip_register_asc(int port) -+{ -+ switch (port) { -+ case 0: -+ ltq_register_asc(0); -+ svip_sys1_clk_enable(SYS1_CLKENR_ASC0); -+ break; -+ case 1: -+ ltq_register_asc(1); -+ svip_sys1_clk_enable(SYS1_CLKENR_ASC1); -+ break; -+ default: -+ break; -+ }; -+} -+ -+/* Ethernet */ -+static unsigned char svip_ethaddr[6] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; -+ -+static struct platform_device ltq_mii = { -+ .name = "ifxmips_mii0", -+ .dev = { -+ .platform_data = svip_ethaddr, -+ }, -+}; -+ -+static int __init svip_set_ethaddr(char *str) -+{ -+ sscanf(str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", -+ &svip_ethaddr[0], &svip_ethaddr[1], &svip_ethaddr[2], -+ &svip_ethaddr[3], &svip_ethaddr[4], &svip_ethaddr[5]); -+ return 0; -+} -+__setup("ethaddr=", svip_set_ethaddr); -+ -+void __init svip_register_eth(void) -+{ -+ if (!is_valid_ether_addr(svip_ethaddr)) -+ random_ether_addr(svip_ethaddr); -+ -+ platform_device_register(<q_mii); -+ svip_sys1_clk_enable(SYS1_CLKENR_ETHSW); -+} -+ -+/* Virtual Ethernet */ -+static struct platform_device ltq_ve = { -+ .name = "ifxmips_svip_ve", -+}; -+ -+void __init svip_register_virtual_eth(void) -+{ -+ platform_device_register(<q_ve); -+} -+ -+/* SPI */ -+static void __init ltq_register_ssc(int bus_num, unsigned long base, int irq_rx, -+ int irq_tx, int irq_err, int irq_frm) -+{ -+ struct resource res[] = { -+ { -+ .name = "regs", -+ .start = base, -+ .end = base + 0x20 - 1, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .name = "rx", -+ .start = irq_rx, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .name = "tx", -+ .start = irq_tx, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .name = "err", -+ .start = irq_err, -+ .flags = IORESOURCE_IRQ, -+ }, { -+ .name = "frm", -+ .start = irq_frm, -+ .flags = IORESOURCE_IRQ, -+ }, -+ }; -+ -+ platform_device_register_simple("ifx_ssc", bus_num, res, -+ ARRAY_SIZE(res)); -+} -+ -+static struct spi_board_info bdinfo[] __initdata = { -+ { -+ .modalias = "xt16", -+ .mode = SPI_MODE_3, -+ .irq = INT_NUM_IM5_IRL0 + 28, -+ .max_speed_hz = 1000000, -+ .bus_num = 0, -+ .chip_select = 1, -+ }, -+ { -+ .modalias = "xt16", -+ .mode = SPI_MODE_3, -+ .irq = INT_NUM_IM5_IRL0 + 19, -+ .max_speed_hz = 1000000, -+ .bus_num = 0, -+ .chip_select = 2, -+ }, -+ { -+ .modalias = "loop", -+ .mode = SPI_MODE_0 | SPI_LOOP, -+ .irq = -1, -+ .max_speed_hz = 10000000, -+ .bus_num = 0, -+ .chip_select = 3, -+ }, -+}; -+ -+void __init svip_register_spi(void) -+{ -+ -+ ltq_register_ssc(0, LTQ_SSC0_BASE, INT_NUM_IM1_IRL0 + 6, -+ INT_NUM_IM1_IRL0 + 7, INT_NUM_IM1_IRL0 + 8, -+ INT_NUM_IM1_IRL0 + 9); -+ -+ ltq_register_ssc(1, LTQ_SSC1_BASE, INT_NUM_IM1_IRL0 + 10, -+ INT_NUM_IM1_IRL0 + 11, INT_NUM_IM1_IRL0 + 12, -+ INT_NUM_IM1_IRL0 + 13); -+ -+ spi_register_board_info(bdinfo, ARRAY_SIZE(bdinfo)); -+ -+ svip_sys1_clk_enable(SYS1_CLKENR_SSC0 | SYS1_CLKENR_SSC1); -+} -+ -+void __init svip_register_spi_flash(struct spi_board_info *bdinfo) -+{ -+ spi_register_board_info(bdinfo, 1); -+} -+ -+/* GPIO */ -+static struct platform_device ltq_gpio = { -+ .name = "ifxmips_gpio", -+}; -+ -+static struct platform_device ltq_gpiodev = { -+ .name = "GPIODEV", -+}; -+ -+void __init svip_register_gpio(void) -+{ -+ platform_device_register(<q_gpio); -+ platform_device_register(<q_gpiodev); -+} -+ -+/* MUX */ -+static struct ltq_mux_settings ltq_mux_settings; -+ -+static struct platform_device ltq_mux = { -+ .name = "ltq_mux", -+ .dev = { -+ .platform_data = <q_mux_settings, -+ } -+}; -+ -+void __init svip_register_mux(const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS], -+ const struct ltq_mux_pin mux_p1[LTQ_MUX_P1_PINS], -+ const struct ltq_mux_pin mux_p2[LTQ_MUX_P2_PINS], -+ const struct ltq_mux_pin mux_p3[LTQ_MUX_P3_PINS], -+ const struct ltq_mux_pin mux_p4[LTQ_MUX_P4_PINS]) -+{ -+ ltq_mux_settings.mux_p0 = mux_p0; -+ ltq_mux_settings.mux_p1 = mux_p1; -+ ltq_mux_settings.mux_p2 = mux_p2; -+ ltq_mux_settings.mux_p3 = mux_p3; -+ ltq_mux_settings.mux_p4 = mux_p4; -+ -+ if (mux_p0) -+ svip_sys1_clk_enable(SYS1_CLKENR_PORT0); -+ -+ if (mux_p1) -+ svip_sys1_clk_enable(SYS1_CLKENR_PORT1); -+ -+ if (mux_p2) -+ svip_sys1_clk_enable(SYS1_CLKENR_PORT2); -+ -+ if (mux_p3) -+ svip_sys1_clk_enable(SYS1_CLKENR_PORT3); -+ -+ if (mux_p4) -+ svip_sys2_clk_enable(SYS2_CLKENR_PORT4); -+ -+ platform_device_register(<q_mux); -+} -+ -+/* NAND */ -+#define NAND_ADDR_REGION_BASE (LTQ_EBU_SEG1_BASE) -+#define NAND_CLE_BIT (1 << 3) -+#define NAND_ALE_BIT (1 << 2) -+ -+static struct svip_reg_ebu *const ebu = (struct svip_reg_ebu *)LTQ_EBU_BASE; -+ -+static int svip_nand_probe(struct platform_device *pdev) -+{ -+ ebu_w32(LTQ_EBU_ADDR_SEL_0_BASE_VAL(CPHYSADDR(NAND_ADDR_REGION_BASE) -+ >> 12) -+ | LTQ_EBU_ADDR_SEL_0_MASK_VAL(15) -+ | LTQ_EBU_ADDR_SEL_0_MRME_VAL(0) -+ | LTQ_EBU_ADDR_SEL_0_REGEN_VAL(1), -+ addr_sel_0); -+ -+ ebu_w32(LTQ_EBU_CON_0_WRDIS_VAL(0) -+ | LTQ_EBU_CON_0_ADSWP_VAL(1) -+ | LTQ_EBU_CON_0_AGEN_VAL(0x00) -+ | LTQ_EBU_CON_0_SETUP_VAL(1) -+ | LTQ_EBU_CON_0_WAIT_VAL(0x00) -+ | LTQ_EBU_CON_0_WINV_VAL(0) -+ | LTQ_EBU_CON_0_PW_VAL(0x00) -+ | LTQ_EBU_CON_0_ALEC_VAL(0) -+ | LTQ_EBU_CON_0_BCGEN_VAL(0x01) -+ | LTQ_EBU_CON_0_WAITWRC_VAL(1) -+ | LTQ_EBU_CON_0_WAITRDC_VAL(1) -+ | LTQ_EBU_CON_0_HOLDC_VAL(1) -+ | LTQ_EBU_CON_0_RECOVC_VAL(0) -+ | LTQ_EBU_CON_0_CMULT_VAL(0x01), -+ con_0); -+ -+ /* -+ * ECC disabled -+ * CLE, ALE and CS are pulse, all other signal are latches based -+ * CLE and ALE are active high, PRE, WP, SE and CS/CE are active low -+ * OUT_CS_S is disabled -+ * NAND mode is disabled -+ */ -+ ebu_w32(LTQ_EBU_NAND_CON_ECC_ON_VAL(0) -+ | LTQ_EBU_NAND_CON_LAT_EN_VAL(0x38) -+ | LTQ_EBU_NAND_CON_OUT_CS_S_VAL(0) -+ | LTQ_EBU_NAND_CON_IN_CS_S_VAL(0) -+ | LTQ_EBU_NAND_CON_PRE_P_VAL(1) -+ | LTQ_EBU_NAND_CON_WP_P_VAL(1) -+ | LTQ_EBU_NAND_CON_SE_P_VAL(1) -+ | LTQ_EBU_NAND_CON_CS_P_VAL(1) -+ | LTQ_EBU_NAND_CON_CLE_P_VAL(0) -+ | LTQ_EBU_NAND_CON_ALE_P_VAL(0) -+ | LTQ_EBU_NAND_CON_CSMUX_E_VAL(0) -+ | LTQ_EBU_NAND_CON_NANDMODE_VAL(0), -+ nand_con); -+ -+ return 0; -+} -+ -+static void svip_nand_hwcontrol(struct mtd_info *mtd, int cmd, -+ unsigned int ctrl) -+{ -+ struct nand_chip *this = mtd->priv; -+ -+ if (ctrl & NAND_CTRL_CHANGE) { -+ unsigned long adr; -+ /* Coming here means to change either the enable state or -+ * the address for controlling ALE or CLE */ -+ -+ /* NAND_NCE: Select the chip by setting nCE to low. -+ * This is done in CON register */ -+ if (ctrl & NAND_NCE) -+ ebu_w32_mask(0, LTQ_EBU_NAND_CON_NANDMODE_VAL(1), -+ nand_con); -+ else -+ ebu_w32_mask(LTQ_EBU_NAND_CON_NANDMODE_VAL(1), -+ 0, nand_con); -+ -+ /* The addressing of CLE or ALE is done via different addresses. -+ We are now changing the address depending on the given action -+ SVIPs NAND_CLE_BIT = (1 << 3), NAND_CLE = 0x02 -+ NAND_ALE_BIT = (1 << 2) = NAND_ALE (0x04) */ -+ adr = (unsigned long)this->IO_ADDR_W; -+ adr &= ~(NAND_CLE_BIT | NAND_ALE_BIT); -+ adr |= (ctrl & NAND_CLE) << 2 | (ctrl & NAND_ALE); -+ this->IO_ADDR_W = (void __iomem *)adr; -+ } -+ -+ if (cmd != NAND_CMD_NONE) -+ writeb(cmd, this->IO_ADDR_W); -+} -+ -+static int svip_nand_ready(struct mtd_info *mtd) -+{ -+ return (ebu_r32(nand_wait) & 0x01) == 0x01; -+} -+ -+static inline void svip_nand_wait(void) -+{ -+ static const int nops = 150; -+ int i; -+ -+ for (i = 0; i < nops; i++) -+ asm("nop"); -+} -+ -+static void svip_nand_write_buf(struct mtd_info *mtd, -+ const u_char *buf, int len) -+{ -+ int i; -+ struct nand_chip *this = mtd->priv; -+ -+ for (i = 0; i < len; i++) { -+ writeb(buf[i], this->IO_ADDR_W); -+ svip_nand_wait(); -+ } -+} -+ -+static void svip_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) -+{ -+ int i; -+ struct nand_chip *this = mtd->priv; -+ -+ for (i = 0; i < len; i++) { -+ buf[i] = readb(this->IO_ADDR_R); -+ svip_nand_wait(); -+ } -+} -+ -+static const char *part_probes[] = { "cmdlinepart", NULL }; -+ -+static struct platform_nand_data svip_flash_nand_data = { -+ .chip = { -+ .nr_chips = 1, -+ .part_probe_types = part_probes, -+ }, -+ .ctrl = { -+ .probe = svip_nand_probe, -+ .cmd_ctrl = svip_nand_hwcontrol, -+ .dev_ready = svip_nand_ready, -+ .write_buf = svip_nand_write_buf, -+ .read_buf = svip_nand_read_buf, -+ } -+}; -+ -+static struct resource svip_nand_resources[] = { -+ MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX), -+}; -+ -+static struct platform_device svip_flash_nand = { -+ .name = "gen_nand", -+ .id = -1, -+ .num_resources = ARRAY_SIZE(svip_nand_resources), -+ .resource = svip_nand_resources, -+ .dev = { -+ .platform_data = &svip_flash_nand_data, -+ }, -+}; -+ -+void __init svip_register_nand(void) -+{ -+ platform_device_register(&svip_flash_nand); -+} -Index: linux-3.3.8/arch/mips/lantiq/svip/clk-svip.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/lantiq/svip/clk-svip.c 2012-07-31 19:51:34.137105918 +0200 -@@ -0,0 +1,100 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * Copyright (C) 2010 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+static struct svip_reg_status *const status = -+(struct svip_reg_status *)LTQ_STATUS_BASE; -+static struct svip_reg_sys0 *const sys0 = (struct svip_reg_sys0 *)LTQ_SYS0_BASE; -+static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; -+ -+unsigned int ltq_svip_io_region_clock(void) -+{ -+ return 200000000; /* 200 MHz */ -+} -+EXPORT_SYMBOL(ltq_svip_io_region_clock); -+ -+unsigned int ltq_svip_cpu_hz(void) -+{ -+ /* Magic BootROM speed location... */ -+ if ((*(u32 *)0x9fc07ff0) == 1) -+ return *(u32 *)0x9fc07ff4; -+ -+ if (STATUS_CONFIG_CLK_MODE_GET(status_r32(config)) == 1) { -+ /* xT16 */ -+ return 393216000; -+ } else { -+ switch (SYS0_PLL1CR_PLLDIV_GET(sys0_r32(pll1cr))) { -+ case 3: -+ return 475000000; -+ case 2: -+ return 450000000; -+ case 1: -+ return 425000000; -+ default: -+ return 400000000; -+ } -+ } -+} -+EXPORT_SYMBOL(ltq_svip_cpu_hz); -+ -+unsigned int ltq_svip_fpi_hz(void) -+{ -+ u32 fbs0_div[2] = {4, 8}; -+ u32 div; -+ -+ div = SYS1_FPICR_FPIDIV_GET(sys1_r32(fpicr)); -+ return ltq_svip_cpu_hz()/fbs0_div[div]; -+} -+EXPORT_SYMBOL(ltq_svip_fpi_hz); -+ -+unsigned int ltq_get_ppl_hz(void) -+{ -+ /* Magic BootROM speed location... */ -+ if ((*(u32 *)0x9fc07ff0) == 1) -+ return *(u32 *)0x9fc07ff4; -+ -+ if (STATUS_CONFIG_CLK_MODE_GET(status_r32(config)) == 1) { -+ /* xT16 */ -+ return 393216000; -+ } else { -+ switch (SYS0_PLL1CR_PLLDIV_GET(sys0_r32(pll1cr))) { -+ case 3: -+ return 475000000; -+ case 2: -+ return 450000000; -+ case 1: -+ return 425000000; -+ default: -+ return 400000000; -+ } -+ } -+} -+ -+unsigned int ltq_get_fbs0_hz(void) -+{ -+ u32 fbs0_div[2] = {4, 8}; -+ u32 div; -+ -+ div = SYS1_FPICR_FPIDIV_GET(sys1_r32(fpicr)); -+ return ltq_get_ppl_hz()/fbs0_div[div]; -+} -+EXPORT_SYMBOL(ltq_get_fbs0_hz); -Index: linux-3.3.8/arch/mips/lantiq/svip/gpio.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/lantiq/svip/gpio.c 2012-07-31 19:51:34.137105918 +0200 -@@ -0,0 +1,553 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2010 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+#define DRV_NAME "ifxmips_gpio" -+ -+int gpio_to_irq(unsigned int gpio) -+{ -+ return -EINVAL; -+} -+EXPORT_SYMBOL(gpio_to_irq); -+ -+int irq_to_gpio(unsigned int gpio) -+{ -+ return -EINVAL; -+} -+EXPORT_SYMBOL(irq_to_gpio); -+ -+struct ltq_port_base { -+ struct svip_reg_port *base; -+ u32 pins; -+}; -+ -+/* Base addresses for ports */ -+static const struct ltq_port_base ltq_port_base[] = { -+ { (struct svip_reg_port *)LTQ_PORT_P0_BASE, 20 }, -+ { (struct svip_reg_port *)LTQ_PORT_P1_BASE, 20 }, -+ { (struct svip_reg_port *)LTQ_PORT_P2_BASE, 19 }, -+ { (struct svip_reg_port *)LTQ_PORT_P3_BASE, 20 }, -+ { (struct svip_reg_port *)LTQ_PORT_P4_BASE, 24 } -+}; -+ -+#define MAX_PORTS ARRAY_SIZE(ltq_port_base) -+#define PINS_PER_PORT(port) (ltq_port_base[port].pins) -+ -+static inline -+void ltq_port_set_exintcr0(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return; -+ -+ port_w32(port_r32(ltq_port_base[port].base->exintcr0) | (1 << pin), -+ ltq_port_base[port].base->exintcr0); -+} -+ -+static inline -+void ltq_port_clear_exintcr0(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return; -+ -+ port_w32(port_r32(ltq_port_base[port].base->exintcr0) & ~(1 << pin), -+ ltq_port_base[port].base->exintcr0); -+} -+ -+static inline -+void ltq_port_set_exintcr1(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return; -+ -+ port_w32(port_r32(ltq_port_base[port].base->exintcr1) | (1 << pin), -+ ltq_port_base[port].base->exintcr1); -+} -+ -+static inline -+void ltq_port_clear_exintcr1(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return; -+ -+ port_w32(port_r32(ltq_port_base[port].base->exintcr1) & ~(1 << pin), -+ ltq_port_base[port].base->exintcr1); -+} -+ -+static inline -+void ltq_port_set_irncfg(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return; -+ -+ port_w32(port_r32(ltq_port_base[port].base->irncfg) | (1 << pin), -+ ltq_port_base[port].base->irncfg); -+} -+ -+static inline -+void ltq_port_clear_irncfg(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return; -+ -+ port_w32(port_r32(ltq_port_base[port].base->irncfg) & ~(1 << pin), -+ ltq_port_base[port].base->irncfg); -+} -+ -+static inline -+void ltq_port_set_irnen(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return; -+ -+ port_w32(1 << pin, ltq_port_base[port].base->irnenset); -+} -+ -+static inline -+void ltq_port_clear_irnen(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return; -+ -+ port_w32(1 << pin, ltq_port_base[port].base->irnenclr); -+} -+ -+static inline -+void ltq_port_set_dir_out(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return; -+ -+ port_w32(port_r32(ltq_port_base[port].base->dir) | (1 << pin), -+ ltq_port_base[port].base->dir); -+} -+ -+static inline -+void ltq_port_set_dir_in(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return; -+ -+ port_w32(port_r32(ltq_port_base[port].base->dir) & ~(1 << pin), -+ ltq_port_base[port].base->dir); -+} -+ -+static inline -+void ltq_port_set_output(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return; -+ -+ port_w32(port_r32(ltq_port_base[port].base->out) | (1 << pin), -+ ltq_port_base[port].base->out); -+} -+ -+static inline -+void ltq_port_clear_output(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return; -+ -+ port_w32(port_r32(ltq_port_base[port].base->out) & ~(1 << pin), -+ ltq_port_base[port].base->out); -+} -+ -+static inline -+int ltq_port_get_input(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return -EINVAL; -+ -+ return (port_r32(ltq_port_base[port].base->in) & (1 << pin)) == 0; -+} -+ -+static inline -+void ltq_port_set_puen(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return; -+ -+ port_w32(port_r32(ltq_port_base[port].base->puen) | (1 << pin), -+ ltq_port_base[port].base->puen); -+} -+ -+static inline -+void ltq_port_clear_puen(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return; -+ -+ port_w32(port_r32(ltq_port_base[port].base->puen) & ~(1 << pin), -+ ltq_port_base[port].base->puen); -+} -+ -+static inline -+void ltq_port_set_altsel0(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return; -+ -+ port_w32(port_r32(ltq_port_base[port].base->altsel0) | (1 << pin), -+ ltq_port_base[port].base->altsel0); -+} -+ -+static inline -+void ltq_port_clear_altsel0(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return; -+ -+ port_w32(port_r32(ltq_port_base[port].base->altsel0) & ~(1 << pin), -+ ltq_port_base[port].base->altsel0); -+} -+ -+static inline -+void ltq_port_set_altsel1(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return; -+ -+ port_w32(port_r32(ltq_port_base[port].base->altsel1) | (1 << pin), -+ ltq_port_base[port].base->altsel1); -+} -+ -+static inline -+void ltq_port_clear_altsel1(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return; -+ -+ port_w32(port_r32(ltq_port_base[port].base->altsel1) & ~(1 << pin), -+ ltq_port_base[port].base->altsel1); -+} -+ -+void ltq_gpio_configure(int port, int pin, bool dirin, bool puen, -+ bool altsel0, bool altsel1) -+{ -+ if (dirin) -+ ltq_port_set_dir_in(port, pin); -+ else -+ ltq_port_set_dir_out(port, pin); -+ -+ if (puen) -+ ltq_port_set_puen(port, pin); -+ else -+ ltq_port_clear_puen(port, pin); -+ -+ if (altsel0) -+ ltq_port_set_altsel0(port, pin); -+ else -+ ltq_port_clear_altsel0(port, pin); -+ -+ if (altsel1) -+ ltq_port_set_altsel1(port, pin); -+ else -+ ltq_port_clear_altsel1(port, pin); -+} -+ -+int ltq_port_get_dir(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return -EINVAL; -+ -+ return (port_r32(ltq_port_base[port].base->dir) & (1 << pin)) != 0; -+} -+ -+int ltq_port_get_puden(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return -EINVAL; -+ -+ return (port_r32(ltq_port_base[port].base->puen) & (1 << pin)) != 0; -+} -+ -+int ltq_port_get_altsel0(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return -EINVAL; -+ -+ return (port_r32(ltq_port_base[port].base->altsel0) & (1 << pin)) != 0; -+} -+ -+int ltq_port_get_altsel1(unsigned int port, unsigned int pin) -+{ -+ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) -+ return -EINVAL; -+ -+ return (port_r32(ltq_port_base[port].base->altsel1) & (1 << pin)) != 0; -+} -+ -+struct ltq_gpio_port { -+ struct gpio_chip gpio_chip; -+ unsigned int irq_base; -+ unsigned int chained_irq; -+}; -+ -+static struct ltq_gpio_port ltq_gpio_port[MAX_PORTS]; -+ -+static int gpio_exported; -+static int __init gpio_export_setup(char *str) -+{ -+ get_option(&str, &gpio_exported); -+ return 1; -+} -+__setup("gpio_exported=", gpio_export_setup); -+ -+static inline unsigned int offset2port(unsigned int offset) -+{ -+ unsigned int i; -+ unsigned int prev = 0; -+ -+ for (i = 0; i < ARRAY_SIZE(ltq_port_base); i++) { -+ if (offset >= prev && -+ offset < prev + ltq_port_base[i].pins) -+ return i; -+ -+ prev = ltq_port_base[i].pins; -+ } -+ -+ return 0; -+} -+ -+static inline unsigned int offset2pin(unsigned int offset) -+{ -+ unsigned int i; -+ unsigned int prev = 0; -+ -+ for (i = 0; i < ARRAY_SIZE(ltq_port_base); i++) { -+ if (offset >= prev && -+ offset < prev + ltq_port_base[i].pins) -+ return offset - prev; -+ -+ prev = ltq_port_base[i].pins; -+ } -+ -+ return 0; -+} -+ -+static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) -+{ -+ ltq_port_set_dir_in(offset2port(offset), offset2pin(offset)); -+ return 0; -+} -+ -+static int ltq_gpio_direction_output(struct gpio_chip *chip, -+ unsigned int offset, int value) -+{ -+ ltq_port_set_dir_out(offset2port(offset), offset2pin(offset)); -+ return 0; -+} -+ -+static int ltq_gpio_get(struct gpio_chip *chip, unsigned int offset) -+{ -+ return ltq_port_get_input(offset2port(offset), offset2pin(offset)); -+} -+ -+static void ltq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) -+{ -+ if (value) -+ ltq_port_set_output(offset2port(offset), offset2pin(offset)); -+ else -+ ltq_port_clear_output(offset2port(offset), offset2pin(offset)); -+} -+ -+static int svip_gpio_request(struct gpio_chip *chip, unsigned offset) -+{ -+ return 0; -+} -+ -+static void ltq_gpio_free(struct gpio_chip *chip, unsigned offset) -+{ -+} -+ -+static int ltq_gpio_probe(struct platform_device *pdev) -+{ -+ int ret = 0; -+ struct ltq_gpio_port *gpio_port; -+ -+ if (pdev->id >= MAX_PORTS) -+ return -ENODEV; -+ -+ gpio_port = <q_gpio_port[pdev->id]; -+ gpio_port->gpio_chip.label = "ltq-gpio"; -+ -+ gpio_port->gpio_chip.direction_input = ltq_gpio_direction_input; -+ gpio_port->gpio_chip.direction_output = ltq_gpio_direction_output; -+ gpio_port->gpio_chip.get = ltq_gpio_get; -+ gpio_port->gpio_chip.set = ltq_gpio_set; -+ gpio_port->gpio_chip.request = svip_gpio_request; -+ gpio_port->gpio_chip.free = ltq_gpio_free; -+ gpio_port->gpio_chip.base = 100 * pdev->id; -+ gpio_port->gpio_chip.ngpio = 32; -+ gpio_port->gpio_chip.dev = &pdev->dev; -+ gpio_port->gpio_chip.exported = gpio_exported; -+ -+ ret = gpiochip_add(&gpio_port->gpio_chip); -+ if (ret < 0) { -+ dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n", -+ pdev->id, ret); -+ goto err; -+ } -+ platform_set_drvdata(pdev, gpio_port); -+ -+ return 0; -+ -+err: -+ return ret; -+} -+ -+static int ltq_gpio_remove(struct platform_device *pdev) -+{ -+ struct ltq_gpio_port *gpio_port = platform_get_drvdata(pdev); -+ int ret; -+ -+ ret = gpiochip_remove(&gpio_port->gpio_chip); -+ -+ return ret; -+} -+ -+static struct platform_driver ltq_gpio_driver = { -+ .probe = ltq_gpio_probe, -+ .remove = __devexit_p(ltq_gpio_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+int __init ltq_gpio_init(void) -+{ -+ int ret = platform_driver_register(<q_gpio_driver); -+ if (ret) -+ printk(KERN_INFO DRV_NAME -+ ": Error registering platform driver!"); -+ return ret; -+} -+ -+postcore_initcall(ltq_gpio_init); -+ -+/** -+ * Convert interrupt number to corresponding port/pin pair -+ * Returns the port/pin pair serving the selected external interrupt; -+ * needed since mapping not linear. -+ * -+ * \param exint External interrupt number -+ * \param port Pointer for resulting port -+ * \param pin Pointer for resutling pin -+ * \return -EINVAL Invalid exint -+ * \return 0 port/pin updated -+ * \ingroup API -+ */ -+static int ltq_exint2port(u32 exint, int *port, int *pin) -+{ -+ if ((exint >= 0) && (exint <= 10)) { -+ *port = 0; -+ *pin = exint + 7; -+ } else if ((exint >= 11) && (exint <= 14)) { -+ *port = 1; -+ *pin = 18 - (exint - 11) ; -+ } else if (exint == 15) { -+ *port = 1; -+ *pin = 19; -+ } else if (exint == 16) { -+ *port = 0; -+ *pin = 19; -+ } else { -+ return -EINVAL; -+ } -+ return 0; -+} -+ -+/** -+ * Enable external interrupt. -+ * This function enables an external interrupt and sets the given mode. -+ * valid values for mode are: -+ * - 0 = Interrupt generation disabled -+ * - 1 = Interrupt on rising edge -+ * - 2 = Interrupt on falling edge -+ * - 3 = Interrupt on rising and falling edge -+ * - 5 = Interrupt on high level detection -+ * - 6 = Interrupt on low level detection -+ * -+ * \param exint - Number of external interrupt -+ * \param mode - Trigger mode -+ * \return 0 on success -+ * \ingroup API -+ */ -+int ifx_enable_external_int(u32 exint, u32 mode) -+{ -+ int port; -+ int pin; -+ -+ if ((mode < 0) || (mode > 6)) -+ return -EINVAL; -+ -+ if (ltq_exint2port(exint, &port, &pin)) -+ return -EINVAL; -+ -+ ltq_port_clear_exintcr0(port, pin); -+ ltq_port_clear_exintcr1(port, pin); -+ ltq_port_clear_irncfg(port, pin); -+ -+ if (mode & 0x1) -+ ltq_port_set_exintcr0(port, pin); -+ if (mode & 0x2) -+ ltq_port_set_exintcr1(port, pin); -+ if (mode & 0x4) -+ ltq_port_set_irncfg(port, pin); -+ -+ ltq_port_set_irnen(port, pin); -+ return 0; -+} -+EXPORT_SYMBOL(ifx_enable_external_int); -+ -+/** -+ * Disable external interrupt. -+ * This function disables an external interrupt and sets mode to 0x00. -+ * -+ * \param exint - Number of external interrupt -+ * \return 0 on success -+ * \ingroup API -+ */ -+int ifx_disable_external_int(u32 exint) -+{ -+ int port; -+ int pin; -+ -+ if (ltq_exint2port(exint, &port, &pin)) -+ return -EINVAL; -+ -+ ltq_port_clear_irnen(port, pin); -+ return 0; -+} -+EXPORT_SYMBOL(ifx_disable_external_int); -Index: linux-3.3.8/arch/mips/lantiq/svip/prom.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/lantiq/svip/prom.c 2012-07-31 19:51:34.137105918 +0200 -@@ -0,0 +1,73 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * Copyright (C) 2010 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "../prom.h" -+#include "../clk.h" -+#include "../machtypes.h" -+ -+#include -+#include -+ -+#define SOC_SVIP "SVIP" -+ -+#define PART_SHIFT 12 -+#define PART_MASK 0x0FFFF000 -+#define REV_SHIFT 28 -+#define REV_MASK 0xF0000000 -+ -+static struct svip_reg_ebu *const ebu = (struct svip_reg_ebu *)LTQ_EBU_BASE; -+ -+void __init ltq_soc_init(void) -+{ -+ clkdev_add_static(ltq_svip_cpu_hz(), ltq_svip_fpi_hz(), -+ ltq_svip_io_region_clock()); -+} -+ -+void __init -+ltq_soc_setup(void) -+{ -+ if (mips_machtype == LANTIQ_MACH_EASY33016 || -+ mips_machtype == LANTIQ_MACH_EASY336) { -+ ebu_w32(0x120000f1, addr_sel_2); -+ ebu_w32(LTQ_EBU_CON_0_ADSWP | -+ LTQ_EBU_CON_0_SETUP | -+ LTQ_EBU_CON_0_BCGEN_VAL(0x02) | -+ LTQ_EBU_CON_0_WAITWRC_VAL(7) | -+ LTQ_EBU_CON_0_WAITRDC_VAL(3) | -+ LTQ_EBU_CON_0_HOLDC_VAL(3) | -+ LTQ_EBU_CON_0_RECOVC_VAL(3) | -+ LTQ_EBU_CON_0_CMULT_VAL(3), con_2); -+ } -+} -+ -+void __init -+ltq_soc_detect(struct ltq_soc_info *i) -+{ -+ i->partnum = (ltq_r32(LTQ_STATUS_CHIPID) & PART_MASK) >> PART_SHIFT; -+ i->rev = (ltq_r32(LTQ_STATUS_CHIPID) & REV_MASK) >> REV_SHIFT; -+ sprintf(i->rev_type, "1.%d", i->rev); -+ switch (i->partnum) { -+ case SOC_ID_SVIP: -+ i->name = SOC_SVIP; -+ i->type = SOC_TYPE_SVIP; -+ break; -+ -+ default: -+ printk(KERN_ERR "unknown partnum : 0x%08X\n", i->partnum); -+ while (1); -+ break; -+ } -+} -Index: linux-3.3.8/arch/mips/lantiq/svip/reset.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/lantiq/svip/reset.c 2012-07-31 19:51:34.137105918 +0200 -@@ -0,0 +1,95 @@ -+/* -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ * Copyright (C) 2010 John Crispin -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include "../machtypes.h" -+#include -+#include -+#include -+#include -+ -+static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; -+static struct svip_reg_ebu *const ebu = (struct svip_reg_ebu *)LTQ_EBU_BASE; -+ -+#define CPLD_CMDREG3 ((volatile unsigned char*)(KSEG1 + 0x120000f3)) -+extern void switchip_reset(void); -+ -+static void ltq_machine_restart(char *command) -+{ -+ printk(KERN_NOTICE "System restart\n"); -+ local_irq_disable(); -+ -+ if (mips_machtype == LANTIQ_MACH_EASY33016 || -+ mips_machtype == LANTIQ_MACH_EASY336) { -+ /* We just use the CPLD function to reset the entire system as a -+ workaround for the switch reset problem */ -+ local_irq_disable(); -+ ebu_w32(0x120000f1, addr_sel_2); -+ ebu_w32(0x404027ff, con_2); -+ -+ if (mips_machtype == LANTIQ_MACH_EASY336) -+ /* set bit 0 to reset SVIP */ -+ *CPLD_CMDREG3 = (1<<0); -+ else -+ /* set bit 7 to reset SVIP, set bit 3 to reset xT */ -+ *CPLD_CMDREG3 = (1<<7) | (1<<3); -+ } else { -+ *LTQ_BOOT_RVEC(0) = 0; -+ /* reset all except PER, SUBSYS and CPU0 */ -+ sys1_w32(0x00043F3E, rreqr); -+ /* release WDT0 reset */ -+ sys1_w32(0x00000100, rrlsr); -+ /* restore reset value for clock enables */ -+ sys1_w32(~0x0c000040, clkclr); -+ /* reset SUBSYS (incl. DDR2) and CPU0 */ -+ sys1_w32(0x00030001, rbtr); -+ } -+ -+ for (;;) -+ ; -+} -+ -+static void ltq_machine_halt(void) -+{ -+ printk(KERN_NOTICE "System halted.\n"); -+ local_irq_disable(); -+ for (;;) -+ ; -+} -+ -+static void ltq_machine_power_off(void) -+{ -+ printk(KERN_NOTICE "Please turn off the power now.\n"); -+ local_irq_disable(); -+ for (;;) -+ ; -+} -+ -+/* This function is used by the watchdog driver */ -+int ltq_reset_cause(void) -+{ -+ return 0; -+} -+EXPORT_SYMBOL_GPL(ltq_reset_cause); -+ -+static int __init mips_reboot_setup(void) -+{ -+ _machine_restart = ltq_machine_restart; -+ _machine_halt = ltq_machine_halt; -+ pm_power_off = ltq_machine_power_off; -+ return 0; -+} -+ -+arch_initcall(mips_reboot_setup); -Index: linux-3.3.8/arch/mips/lantiq/machtypes.h -=================================================================== ---- linux-3.3.8.orig/arch/mips/lantiq/machtypes.h 2012-07-31 19:51:33.989105912 +0200 -+++ linux-3.3.8/arch/mips/lantiq/machtypes.h 2012-07-31 19:51:34.137105918 +0200 -@@ -16,6 +16,12 @@ - LTQ_MACH_EASY50712, /* Danube evaluation board */ - LTQ_MACH_EASY50601, /* Amazon SE evaluation board */ - -+ /* SVIP */ -+ LANTIQ_MACH_EASY33016, /* SVIP Easy33016 */ -+ LANTIQ_MACH_EASY336, /* SVIP Easy336, NOR Flash */ -+ LANTIQ_MACH_EASY336SF, /* SVIP Easy336, Serial Flash */ -+ LANTIQ_MACH_EASY336NAND, /* SVIP Easy336, NAND Flash */ -+ - /* FALCON */ - LANTIQ_MACH_EASY98000, /* Falcon Eval Board, NOR Flash */ - LANTIQ_MACH_EASY98000SF, /* Falcon Eval Board, Serial Flash */ -Index: linux-3.3.8/arch/mips/lantiq/svip/mach-easy33016.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/lantiq/svip/mach-easy33016.c 2012-07-31 19:51:34.137105918 +0200 -@@ -0,0 +1,73 @@ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "../machtypes.h" -+ -+#include -+#include -+#include -+ -+#include "devices.h" -+ -+static const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS] = { -+ LTQ_MUX_P0_0_SSC0_MTSR, -+ LTQ_MUX_P0_1_SSC0_MRST, -+ LTQ_MUX_P0_2_SSC0_SCLK, -+ LTQ_MUX_P0_3_SSC1_MTSR, -+ LTQ_MUX_P0_4_SSC1_MRST, -+ LTQ_MUX_P0_5_SSC1_SCLK, -+ LTQ_MUX_P0_6_SSC0_CS0, -+ LTQ_MUX_P0_7_SSC0_CS1, -+ LTQ_MUX_P0_8_SSC0_CS2, -+ LTQ_MUX_P0_9, -+ LTQ_MUX_P0_10, -+ LTQ_MUX_P0_11_EXINT4, -+ LTQ_MUX_P0_12, -+ LTQ_MUX_P0_13, -+ LTQ_MUX_P0_14_ASC0_TXD, -+ LTQ_MUX_P0_15_ASC0_RXD, -+ LTQ_MUX_P0_16_EXINT9, -+ LTQ_MUX_P0_17_EXINT10, -+ LTQ_MUX_P0_18_EJ_BRKIN, -+ LTQ_MUX_P0_19_EXINT16 -+}; -+ -+static void __init easy33016_init(void) -+{ -+ svip_sys1_clk_enable(SYS1_CLKENR_L2C | -+ SYS1_CLKENR_DDR2 | -+ SYS1_CLKENR_SMI2 | -+ SYS1_CLKENR_SMI1 | -+ SYS1_CLKENR_SMI0 | -+ SYS1_CLKENR_FMI0 | -+ SYS1_CLKENR_DMA | -+ SYS1_CLKENR_SSC0 | -+ SYS1_CLKENR_SSC1 | -+ SYS1_CLKENR_EBU); -+ -+ svip_sys2_clk_enable(SYS2_CLKENR_HWSYNC | -+ SYS2_CLKENR_MBS | -+ SYS2_CLKENR_SWINT); -+ -+ svip_register_mux(mux_p0, NULL, NULL, NULL, NULL); -+ svip_register_asc(0); -+ svip_register_eth(); -+ svip_register_virtual_eth(); -+ ltq_register_wdt(); -+ svip_register_gpio(); -+ svip_register_spi(); -+ svip_register_nand(); -+} -+ -+MIPS_MACHINE(LANTIQ_MACH_EASY33016, -+ "EASY33016", -+ "EASY33016", -+ easy33016_init); -Index: linux-3.3.8/arch/mips/lantiq/svip/mach-easy336.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/lantiq/svip/mach-easy336.c 2012-07-31 19:51:34.141105918 +0200 -@@ -0,0 +1,221 @@ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include "../machtypes.h" -+ -+#include -+#include -+#include -+ -+#include "devices.h" -+ -+static struct mtd_partition easy336_sflash_partitions[] = { -+ { -+ .name = "SPI flash", -+ .size = MTDPART_SIZ_FULL, -+ .offset = 0, -+ }, -+}; -+ -+static struct flash_platform_data easy336_sflash_data = { -+ .name = "m25p32", -+ .parts = (void *)&easy336_sflash_partitions, -+ .nr_parts = ARRAY_SIZE(easy336_sflash_partitions), -+ .type = "m25p32", -+}; -+ -+static struct spi_board_info bdinfo[] __initdata = { -+ { -+ .modalias = "m25p80", -+ .platform_data = &easy336_sflash_data, -+ .mode = SPI_MODE_0, -+ .irq = -1, -+ .max_speed_hz = 25000000, -+ .bus_num = 0, -+ .chip_select = 0, -+ } -+}; -+ -+static struct mtd_partition easy336_partitions[] = { -+ { -+ .name = "uboot", -+ .offset = 0x0, -+ .size = 0x40000, -+ }, -+ { -+ .name = "uboot_env", -+ .offset = 0x40000, -+ .size = 0x20000, -+ }, -+ { -+ .name = "linux", -+ .offset = 0x60000, -+ .size = 0x1a0000, -+ }, -+ { -+ .name = "rootfs", -+ .offset = 0x200000, -+ .size = 0x500000, -+ }, -+}; -+ -+static struct physmap_flash_data easy336_flash_data = { -+ .nr_parts = ARRAY_SIZE(easy336_partitions), -+ .parts = easy336_partitions, -+}; -+ -+static const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS] = { -+ LTQ_MUX_P0_0_SSC0_MTSR, -+ LTQ_MUX_P0_1_SSC0_MRST, -+ LTQ_MUX_P0_2_SSC0_SCLK, -+ LTQ_MUX_P0_3_SSC1_MTSR, -+ LTQ_MUX_P0_4_SSC1_MRST, -+ LTQ_MUX_P0_5_SSC1_SCLK, -+ LTQ_MUX_P0_6_SSC0_CS0, -+ LTQ_MUX_P0_7_SSC0_CS1, -+ LTQ_MUX_P0_8_SSC0_CS2, -+ LTQ_MUX_P0_9_SSC0_CS3, -+ LTQ_MUX_P0_10_SSC0_CS4, -+ LTQ_MUX_P0_11_SSC0_CS5, -+ LTQ_MUX_P0_12_EXINT5, -+ LTQ_MUX_P0_13_EXINT6, -+ LTQ_MUX_P0_14_ASC0_TXD, -+ LTQ_MUX_P0_15_ASC0_RXD, -+ LTQ_MUX_P0_16_EXINT9, -+ LTQ_MUX_P0_17_EXINT10, -+ LTQ_MUX_P0_18_EJ_BRKIN, -+ LTQ_MUX_P0_19_EXINT16 -+}; -+ -+static const struct ltq_mux_pin mux_p2[LTQ_MUX_P2_PINS] = { -+ LTQ_MUX_P2_0_EBU_A0, -+ LTQ_MUX_P2_1_EBU_A1, -+ LTQ_MUX_P2_2_EBU_A2, -+ LTQ_MUX_P2_3_EBU_A3, -+ LTQ_MUX_P2_4_EBU_A4, -+ LTQ_MUX_P2_5_EBU_A5, -+ LTQ_MUX_P2_6_EBU_A6, -+ LTQ_MUX_P2_7_EBU_A7, -+ LTQ_MUX_P2_8_EBU_A8, -+ LTQ_MUX_P2_9_EBU_A9, -+ LTQ_MUX_P2_10_EBU_A10, -+ LTQ_MUX_P2_11_EBU_A11, -+ LTQ_MUX_P2_12_EBU_RD, -+ LTQ_MUX_P2_13_EBU_WR, -+ LTQ_MUX_P2_14_EBU_ALE, -+ LTQ_MUX_P2_15_EBU_WAIT, -+ LTQ_MUX_P2_16_EBU_RDBY, -+ LTQ_MUX_P2_17_EBU_BC0, -+ LTQ_MUX_P2_18_EBU_BC1 -+}; -+ -+static const struct ltq_mux_pin mux_p3[LTQ_MUX_P3_PINS] = { -+ LTQ_MUX_P3_0_EBU_AD0, -+ LTQ_MUX_P3_1_EBU_AD1, -+ LTQ_MUX_P3_2_EBU_AD2, -+ LTQ_MUX_P3_3_EBU_AD3, -+ LTQ_MUX_P3_4_EBU_AD4, -+ LTQ_MUX_P3_5_EBU_AD5, -+ LTQ_MUX_P3_6_EBU_AD6, -+ LTQ_MUX_P3_7_EBU_AD7, -+ LTQ_MUX_P3_8_EBU_AD8, -+ LTQ_MUX_P3_9_EBU_AD9, -+ LTQ_MUX_P3_10_EBU_AD10, -+ LTQ_MUX_P3_11_EBU_AD11, -+ LTQ_MUX_P3_12_EBU_AD12, -+ LTQ_MUX_P3_13_EBU_AD13, -+ LTQ_MUX_P3_14_EBU_AD14, -+ LTQ_MUX_P3_15_EBU_AD15, -+ LTQ_MUX_P3_16_EBU_CS0, -+ LTQ_MUX_P3_17_EBU_CS1, -+ LTQ_MUX_P3_18_EBU_CS2, -+ LTQ_MUX_P3_19_EBU_CS3 -+}; -+ -+static void __init easy336_init_common(void) -+{ -+ svip_sys1_clk_enable(SYS1_CLKENR_L2C | -+ SYS1_CLKENR_DDR2 | -+ SYS1_CLKENR_SMI2 | -+ SYS1_CLKENR_SMI1 | -+ SYS1_CLKENR_SMI0 | -+ SYS1_CLKENR_FMI0 | -+ SYS1_CLKENR_DMA | -+ SYS1_CLKENR_GPTC | -+ SYS1_CLKENR_EBU); -+ -+ svip_sys2_clk_enable(SYS2_CLKENR_HWSYNC | -+ SYS2_CLKENR_MBS | -+ SYS2_CLKENR_SWINT | -+ SYS2_CLKENR_HWACC3 | -+ SYS2_CLKENR_HWACC2 | -+ SYS2_CLKENR_HWACC1 | -+ SYS2_CLKENR_HWACC0 | -+ SYS2_CLKENR_SIF7 | -+ SYS2_CLKENR_SIF6 | -+ SYS2_CLKENR_SIF5 | -+ SYS2_CLKENR_SIF4 | -+ SYS2_CLKENR_SIF3 | -+ SYS2_CLKENR_SIF2 | -+ SYS2_CLKENR_SIF1 | -+ SYS2_CLKENR_SIF0 | -+ SYS2_CLKENR_DFEV7 | -+ SYS2_CLKENR_DFEV6 | -+ SYS2_CLKENR_DFEV5 | -+ SYS2_CLKENR_DFEV4 | -+ SYS2_CLKENR_DFEV3 | -+ SYS2_CLKENR_DFEV2 | -+ SYS2_CLKENR_DFEV1 | -+ SYS2_CLKENR_DFEV0); -+ -+ svip_register_mux(mux_p0, NULL, mux_p2, mux_p3, NULL); -+ svip_register_asc(0); -+ svip_register_eth(); -+ svip_register_virtual_eth(); -+ /* ltq_register_wdt(); - conflicts with lq_switch */ -+ svip_register_gpio(); -+ svip_register_spi(); -+ ltq_register_tapi(); -+} -+ -+static void __init easy336_init(void) -+{ -+ easy336_init_common(); -+ ltq_register_nor(&easy336_flash_data); -+} -+ -+static void __init easy336sf_init(void) -+{ -+ easy336_init_common(); -+ svip_register_spi_flash(bdinfo); -+} -+ -+static void __init easy336nand_init(void) -+{ -+ easy336_init_common(); -+ svip_register_nand(); -+} -+ -+MIPS_MACHINE(LANTIQ_MACH_EASY336, -+ "EASY336", -+ "EASY336", -+ easy336_init); -+ -+MIPS_MACHINE(LANTIQ_MACH_EASY336SF, -+ "EASY336SF", -+ "EASY336 (Serial Flash)", -+ easy336sf_init); -+ -+MIPS_MACHINE(LANTIQ_MACH_EASY336NAND, -+ "EASY336NAND", -+ "EASY336 (NAND Flash)", -+ easy336nand_init); -+ -Index: linux-3.3.8/drivers/net/ethernet/svip_virtual_eth.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/drivers/net/ethernet/svip_virtual_eth.c 2012-07-31 19:51:34.141105918 +0200 -@@ -0,0 +1,346 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2007 -+ Infineon Technologies AG -+ Am Campeon 1-12; 81726 Munich, Germany -+ -+ THE DELIVERY OF THIS SOFTWARE AS WELL AS THE HEREBY GRANTED NON-EXCLUSIVE, -+ WORLDWIDE LICENSE TO USE, COPY, MODIFY, DISTRIBUTE AND SUBLICENSE THIS -+ SOFTWARE IS FREE OF CHARGE. -+ -+ THE LICENSED SOFTWARE IS PROVIDED "AS IS" AND INFINEON EXPRESSLY DISCLAIMS -+ ALL REPRESENTATIONS AND WARRANTIES, WHETHER EXPRESS OR IMPLIED, INCLUDING -+ WITHOUT LIMITATION, WARRANTIES OR REPRESENTATIONS OF WORKMANSHIP, -+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, DURABILITY, THAT THE -+ OPERATING OF THE LICENSED SOFTWARE WILL BE ERROR FREE OR FREE OF ANY THIRD -+ PARTY CLAIMS, INCLUDING WITHOUT LIMITATION CLAIMS OF THIRD PARTY INTELLECTUAL -+ PROPERTY INFRINGEMENT. -+ -+ EXCEPT FOR ANY LIABILITY DUE TO WILFUL ACTS OR GROSS NEGLIGENCE AND EXCEPT -+ FOR ANY PERSONAL INJURY INFINEON SHALL IN NO EVENT BE LIABLE FOR ANY CLAIM -+ OR DAMAGES OF ANY KIND, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -+ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -+ DEALINGS IN THE SOFTWARE. -+ -+ **************************************************************************** -+Module : svip_virtual_eth.c -+ -+Description : This file contains network driver implementation for a -+Virtual Ethernet interface. The Virtual Ethernet interface -+is part of Infineon's VINETIC-SVIP Linux BSP. -+ *******************************************************************************/ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define SVIP_VETH_VER_STR "3.0" -+#define SVIP_VETH_INFO_STR \ -+ "@(#)SVIP virtual ethernet interface, version " SVIP_VETH_VER_STR -+ -+/****************************************************************************** -+ * Local define/macro definitions -+ ******************************************************************************/ -+struct svip_ve_priv -+{ -+ struct net_device_stats stats; -+}; -+ -+/****************************************************************************** -+ * Global function declarations -+ ******************************************************************************/ -+int svip_ve_rx(struct sk_buff *skb); -+ -+/****************************************************************************** -+ * Local variable declarations -+ ******************************************************************************/ -+static struct net_device *svip_ve_dev; -+static int watchdog_timeout = 10*HZ; -+static int (*svip_ve_mps_xmit)(struct sk_buff *skb) = NULL; -+ -+ -+/****************************************************************************** -+ * Global function declarations -+ ******************************************************************************/ -+ -+/** -+ * Called by MPS driver to register a transmit routine called for each outgoing -+ * VoFW0 message. -+ * -+ * \param mps_xmit pointer to transmit routine -+ * -+ * \return none -+ * -+ * \ingroup Internal -+ */ -+void register_mps_xmit_routine(int (*mps_xmit)(struct sk_buff *skb)) -+{ -+ svip_ve_mps_xmit = mps_xmit; -+} -+EXPORT_SYMBOL(register_mps_xmit_routine); -+ -+/** -+ * Returns a pointer to the routine used to deliver an incoming packet/message -+ * from the MPS mailbox to the networking layer. This routine is called by MPS -+ * driver during initialisation time. -+ * -+ * \param skb pointer to incoming socket buffer -+ * -+ * \return svip_ve_rx pointer to incoming messages delivering routine -+ * -+ * \ingroup Internal -+ */ -+int (*register_mps_recv_routine(void)) (struct sk_buff *skb) -+{ -+ return svip_ve_rx; -+} -+ -+/** -+ * Used to deliver outgoing packets to VoFW0 module through the MPS driver. -+ * Upon loading/initialisation the MPS driver is registering a transmitting -+ * routine, which is called here to deliver the packet to the VoFW0 module. -+ * -+ * \param skb pointer to skb containing outgoing data -+ * \param dev pointer to this networking device's data -+ * -+ * \return 0 on success -+ * \return non-zero on error -+ * -+ * \ingroup Internal -+ */ -+static int svip_ve_xmit(struct sk_buff *skb, struct net_device *dev) -+{ -+ int err; -+ struct svip_ve_priv *priv = netdev_priv(dev); -+ struct net_device_stats *stats = &priv->stats; -+ -+ stats->tx_packets++; -+ stats->tx_bytes += skb->len; -+ -+ if (svip_ve_mps_xmit) -+ { -+ err = svip_ve_mps_xmit(skb); -+ if (err) -+ stats->tx_errors++; -+ dev->trans_start = jiffies; -+ return err; -+ } -+ else -+ printk(KERN_ERR "%s: MPS driver not registered, outgoing packet not delivered\n", dev->name); -+ -+ dev_kfree_skb(skb); -+ -+ return -1; -+} -+ -+/** -+ * Called by MPS driver upon receipt of a new message from VoFW0 module in -+ * the data inbox. The packet is pushed up the IP module for further processing. -+ * -+ * \param skb pointer to skb containing the incoming message -+ * -+ * \return 0 on success -+ * \return non-zero on error -+ * -+ * \ingroup Internal -+ */ -+int svip_ve_rx(struct sk_buff *skb) -+{ -+ int err; -+ struct svip_ve_priv *priv = netdev_priv(svip_ve_dev); -+ struct net_device_stats *stats = &priv->stats; -+ -+ skb->dev = svip_ve_dev; -+ skb->protocol = eth_type_trans(skb, svip_ve_dev); -+ -+ stats->rx_packets++; -+ stats->rx_bytes += skb->len; -+ -+ err = netif_rx(skb); -+ switch (err) -+ { -+ case NET_RX_SUCCESS: -+ return 0; -+ break; -+ case NET_RX_DROP: -+ default: -+ stats->rx_dropped++; -+ break; -+ } -+ -+ return 1; -+} -+EXPORT_SYMBOL(svip_ve_rx); -+ -+/** -+ * Returns a pointer to the device's networking statistics data -+ * -+ * \param dev pointer to this networking device's data -+ * -+ * \return stats pointer to this network device's statistics data -+ * -+ * \ingroup Internal -+ */ -+static struct net_device_stats *svip_ve_get_stats(struct net_device *dev) -+{ -+ struct svip_ve_priv *priv = netdev_priv(dev); -+ -+ return &priv->stats; -+} -+ -+static void svip_ve_tx_timeout(struct net_device *dev) -+{ -+ struct svip_ve_priv *priv = netdev_priv(dev); -+ -+ priv->stats.tx_errors++; -+ netif_wake_queue(dev); -+} -+ -+/** -+ * Device open routine. Called e.g. upon setting of an IP address using, -+ * 'ifconfig veth0 YYY.YYY.YYY.YYY netmask ZZZ.ZZZ.ZZZ.ZZZ' or -+ * 'ifconfig veth0 up' -+ * -+ * \param dev pointer to this network device's data -+ * -+ * \return 0 on success -+ * \return non-zero on error -+ * -+ * \ingroup Internal -+ */ -+int svip_ve_open(struct net_device *dev) -+{ -+ netif_start_queue(dev); -+ return 0; -+} -+ -+/** -+ * Device close routine. Called e.g. upon calling -+ * 'ifconfig veth0 down' -+ * -+ * \param dev pointer to this network device's data -+ * -+ * \return 0 on success -+ * \return non-zero on error -+ * -+ * \ingroup Internal -+ */ -+ -+int svip_ve_release(struct net_device *dev) -+{ -+ netif_stop_queue(dev); -+ return 0; -+} -+ -+static int svip_ve_dev_init(struct net_device *dev); -+ -+static const struct net_device_ops svip_virtual_eth_netdev_ops = { -+ .ndo_init = svip_ve_dev_init, -+ .ndo_open = svip_ve_open, -+ .ndo_stop = svip_ve_release, -+ .ndo_start_xmit = svip_ve_xmit, -+ .ndo_get_stats = svip_ve_get_stats, -+ .ndo_tx_timeout = svip_ve_tx_timeout, -+}; -+ -+ -+/** -+ * Device initialisation routine which registers device interface routines. -+ * It is called upon execution of 'register_netdev' routine. -+ * -+ * \param dev pointer to this network device's data -+ * -+ * \return 0 on success -+ * \return non-zero on error -+ * -+ * \ingroup Internal -+ */ -+static int svip_ve_dev_init(struct net_device *dev) -+{ -+ ether_setup(dev); /* assign some of the fields */ -+ -+ dev->watchdog_timeo = watchdog_timeout; -+ memset(netdev_priv(dev), 0, sizeof(struct svip_ve_priv)); -+ dev->flags |= IFF_NOARP|IFF_PROMISC; -+ dev->flags &= ~IFF_MULTICAST; -+ -+ /* dedicated MAC address to veth0, 00:03:19:00:15:80 */ -+ dev->dev_addr[0] = 0x00; -+ dev->dev_addr[1] = 0x03; -+ dev->dev_addr[2] = 0x19; -+ dev->dev_addr[3] = 0x00; -+ dev->dev_addr[4] = 0x15; -+ dev->dev_addr[5] = 0x80; -+ -+ return 0; -+} -+ -+static int svip_ve_probe(struct platform_device *dev) -+{ -+ int result = 0; -+ -+ svip_ve_dev = alloc_etherdev(sizeof(struct svip_ve_priv)); -+ svip_ve_dev->netdev_ops = &svip_virtual_eth_netdev_ops; -+ -+ strcpy(svip_ve_dev->name, "veth%d"); -+ -+ result = register_netdev(svip_ve_dev); -+ if (result) -+ { -+ printk(KERN_INFO "error %i registering device \"%s\"\n", result, svip_ve_dev->name); -+ goto out; -+ } -+ -+ printk (KERN_INFO "%s, (c) 2009, Lantiq Deutschland GmbH\n", &SVIP_VETH_INFO_STR[4]); -+ -+out: -+ return result; -+} -+ -+static int svip_ve_remove(struct platform_device *dev) -+{ -+ unregister_netdev(svip_ve_dev); -+ free_netdev(svip_ve_dev); -+ -+ printk(KERN_INFO "%s removed\n", svip_ve_dev->name); -+ return 0; -+} -+ -+static struct platform_driver svip_ve_driver = { -+ .probe = svip_ve_probe, -+ .remove = svip_ve_remove, -+ .driver = { -+ .name = "ifxmips_svip_ve", -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+/** -+ * Module/driver entry routine -+ */ -+static int __init svip_ve_init_module(void) -+{ -+ int ret; -+ -+ ret = platform_driver_register(&svip_ve_driver); -+ if (ret) -+ printk(KERN_INFO "SVIP: error(%d) registering virtual Ethernet driver!\n", ret); -+ return ret; -+} -+ -+/** -+ * Module exit routine (never called for statically linked driver) -+ */ -+static void __exit svip_ve_cleanup_module(void) -+{ -+ platform_driver_unregister(&svip_ve_driver); -+} -+ -+module_init(svip_ve_init_module); -+module_exit(svip_ve_cleanup_module); -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("virtual ethernet driver for LANTIQ SVIP system"); -+ -+EXPORT_SYMBOL(register_mps_recv_routine); -Index: linux-3.3.8/arch/mips/kernel/cevt-r4k.c -=================================================================== ---- linux-3.3.8.orig/arch/mips/kernel/cevt-r4k.c 2012-06-01 09:16:13.000000000 +0200 -+++ linux-3.3.8/arch/mips/kernel/cevt-r4k.c 2012-07-31 19:51:34.141105918 +0200 -@@ -171,8 +171,10 @@ - if (!cpu_has_counter || !mips_hpt_frequency) - return -ENXIO; - -+#ifndef CONFIG_SOC_SVIP - if (!c0_compare_int_usable()) - return -ENXIO; -+#endif - - /* - * With vectored interrupts things are getting platform specific. -Index: linux-3.3.8/arch/mips/lantiq/clk.c -=================================================================== ---- linux-3.3.8.orig/arch/mips/lantiq/clk.c 2012-07-31 19:51:33.457105889 +0200 -+++ linux-3.3.8/arch/mips/lantiq/clk.c 2012-07-31 19:51:34.141105918 +0200 -@@ -149,7 +149,13 @@ - - clk = clk_get_cpu(); - mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution(); -+#ifdef CONFIG_SOC_SVIP -+ write_c0_count(0); -+ write_c0_compare(mips_hpt_frequency / HZ); -+ enable_irq(MIPS_CPU_TIMER_IRQ); -+#else - write_c0_compare(read_c0_count()); -+#endif - pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); - clk_put(clk); - } -Index: linux-3.3.8/arch/mips/lantiq/irq.c -=================================================================== ---- linux-3.3.8.orig/arch/mips/lantiq/irq.c 2012-07-31 19:51:33.897105907 +0200 -+++ linux-3.3.8/arch/mips/lantiq/irq.c 2012-07-31 19:51:34.141105918 +0200 -@@ -17,6 +17,10 @@ - - #include - #include -+#ifdef CONFIG_SOC_SVIP -+#include -+#include -+#endif - - /* register definitions */ - #define LTQ_ICU_IM0_ISR 0x0000 -@@ -175,7 +179,6 @@ - int irq_nr = d->irq - INT_NUM_IRQ0; - unsigned int im_nr; - -- irq_nr -= INT_NUM_IRQ0; - im_nr = (irq_nr / INT_NUM_IM_OFFSET); - irq_nr %= INT_NUM_IM_OFFSET; - -@@ -188,7 +191,6 @@ - int irq_nr = d->irq - INT_NUM_IRQ0; - unsigned int im_nr; - -- irq_nr -= INT_NUM_IRQ0; - im_nr = (irq_nr / INT_NUM_IM_OFFSET); - irq_nr %= INT_NUM_IM_OFFSET; - -@@ -200,7 +202,6 @@ - int irq_nr = d->irq - INT_NUM_IRQ0; - unsigned int im_nr; - -- irq_nr -= INT_NUM_IRQ0; - im_nr = (irq_nr / INT_NUM_IM_OFFSET); - irq_nr %= INT_NUM_IM_OFFSET; - -@@ -281,10 +282,12 @@ - irq = __fls(irq); - do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module)); - -+#ifndef CONFIG_SOC_SVIP - /* if this is a EBU irq, we need to ack it or get a deadlock */ - if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT) - ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10, - LTQ_EBU_PCC_ISTAT); -+#endif - } - - #define DEFINE_HWx_IRQDISPATCH(x) \ -@@ -298,10 +301,14 @@ - DEFINE_HWx_IRQDISPATCH(3) - DEFINE_HWx_IRQDISPATCH(4) - -+#if MIPS_CPU_TIMER_IRQ == 7 - static void ltq_hw5_irqdispatch(void) - { - do_IRQ(MIPS_CPU_TIMER_IRQ); - } -+#else -+DEFINE_HWx_IRQDISPATCH(5) -+#endif - - #ifdef CONFIG_MIPS_MT_SMP - void __init arch_init_ipiirq(int irq, struct irqaction *action) -@@ -349,11 +356,11 @@ - unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; - unsigned int i; - -- if (pending & CAUSEF_IP7) { -+ if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) { - do_IRQ(MIPS_CPU_TIMER_IRQ); - goto out; - } else { -- for (i = 0; i < 5; i++) { -+ for (i = 0; i < IM_NUM; i++) { - if (pending & (CAUSEF_IP2 << i)) { - ltq_hw_irqdispatch(i); - goto out; -@@ -389,15 +396,6 @@ - panic("Failed to remap icu memory\n"); - } - -- if (request_mem_region(ltq_icu_resource.start, -- resource_size(<q_icu_resource), "icu") < 0) -- panic("Failed to request icu memory"); -- -- ltq_icu_membase = ioremap_nocache(ltq_icu_resource.start, -- resource_size(<q_icu_resource)); -- if (!ltq_icu_membase) -- panic("Failed to remap icu memory"); -- - if (LTQ_EIU_BASE_ADDR) { - if (insert_resource(&iomem_resource, <q_eiu_resource) < 0) - panic("Failed to insert eiu memory\n"); -@@ -413,7 +411,7 @@ - } - - /* make sure all irqs are turned off by default */ -- for (i = 0; i < IM_NUM; i++) -+ for (i = 0; i < IM_NUM; i++) { - ltq_icu_w32(0, LTQ_ICU_IM0_IER, i); - /* clear all possibly pending interrupts */ - ltq_icu_w32(~0, LTQ_ICU_IM0_ISR, i); -@@ -421,8 +419,8 @@ - - mips_cpu_irq_init(); - -- for (i = 2; i <= 6; i++) -- setup_irq(i, &cascade); -+ for (i = 0; i < IM_NUM; i++) -+ setup_irq(i + 2, &cascade); - - if (cpu_has_vint) { - pr_info("Setting up vectored interrupts\n"); -@@ -435,7 +433,7 @@ - } - - for (i = INT_NUM_IRQ0; -- i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++) -+ i <= (INT_NUM_IRQ0 + (IM_NUM * INT_NUM_IM_OFFSET)); i++) - if (((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) || - (i == LTQ_EIU_IR2)) && LTQ_EIU_BASE_ADDR) - irq_set_chip_and_handler(i, <q_eiu_type, -@@ -473,5 +471,9 @@ - - unsigned int __cpuinit get_c0_compare_int(void) - { -+#ifdef CONFIG_SOC_SVIP -+ return MIPS_CPU_TIMER_IRQ; -+#else - return CP0_LEGACY_COMPARE_IRQ; -+#endif - } -Index: linux-3.3.8/arch/mips/lantiq/svip/devices.h -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/lantiq/svip/devices.h 2012-07-31 19:51:34.141105918 +0200 -@@ -0,0 +1,23 @@ -+#ifndef _SVIP_DEVICES_H__ -+#define _SVIP_DEVICES_H__ -+ -+#include -+#include -+#include -+#include -+#include "../devices.h" -+ -+extern void __init svip_register_asc(int port); -+extern void __init svip_register_eth(void); -+extern void __init svip_register_virtual_eth(void); -+extern void __init svip_register_spi(void); -+extern void __init svip_register_spi_flash(struct spi_board_info *bdinfo); -+extern void __init svip_register_gpio(void); -+extern void __init svip_register_mux(const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS], -+ const struct ltq_mux_pin mux_p1[LTQ_MUX_P1_PINS], -+ const struct ltq_mux_pin mux_p2[LTQ_MUX_P2_PINS], -+ const struct ltq_mux_pin mux_p3[LTQ_MUX_P3_PINS], -+ const struct ltq_mux_pin mux_p4[LTQ_MUX_P4_PINS]); -+extern void __init svip_register_nand(void); -+ -+#endif -Index: linux-3.3.8/arch/mips/mm/c-r4k.c -=================================================================== ---- linux-3.3.8.orig/arch/mips/mm/c-r4k.c 2012-07-31 19:51:33.433105887 +0200 -+++ linux-3.3.8/arch/mips/mm/c-r4k.c 2012-07-31 19:51:34.145105918 +0200 -@@ -1252,6 +1252,9 @@ - way_string[c->scache.ways], c->scache.linesz); - } - #else -+#ifdef CONFIG_SOC_SVIP -+ return; -+#endif - if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) - panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); - #endif -Index: linux-3.3.8/arch/mips/lantiq/svip/dma.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/lantiq/svip/dma.c 2012-07-31 20:45:23.245243957 +0200 -@@ -0,0 +1,1206 @@ -+/* -+ ** Copyright (C) 2005 Wu Qi Ming -+ ** -+ ** This program is free software; you can redistribute it and/or modify -+ ** it under the terms of the GNU General Public License as published by -+ ** the Free Software Foundation; either version 2 of the License, or -+ ** (at your option) any later version. -+ ** -+ ** This program is distributed in the hope that it will be useful, -+ ** but WITHOUT ANY WARRANTY; without even the implied warranty of -+ ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ ** GNU General Public License for more details. -+ ** -+ ** You should have received a copy of the GNU General Public License -+ ** along with this program; if not, write to the Free Software -+ ** Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -+ */ -+/* -+ * Description: -+ * Driver for SVIP DMA -+ * Author: Wu Qi Ming[Qi-Ming.Wu@infineon.com] -+ * Created: 26-September-2005 -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; -+static struct svip_reg_dma *const dma = (struct svip_reg_dma *)LTQ_DMA_BASE; -+static struct svip_reg_mbs *const mbs = (struct svip_reg_mbs *)LTQ_MBS_BASE; -+ -+#define DRV_NAME "ltq_dma" -+extern void ltq_mask_and_ack_irq(struct irq_data *data); -+extern void ltq_enable_irq(struct irq_data *data); -+ -+static inline void mask_and_ack_irq(unsigned int irq_nr) -+{ -+ static int i = 0; -+ struct irq_data data; -+ data.irq = irq_nr; -+ if ((i < 2) && (irq_nr == 137)) { -+ printk("eth delay hack\n"); -+ i++; -+ } -+ ltq_mask_and_ack_irq(&data); -+} -+ -+static inline void svip_enable_irq(unsigned int irq_nr) -+{ -+ struct irq_data data; -+ data.irq = irq_nr; -+ ltq_enable_irq(&data); -+} -+ -+#define DMA_EMSG(fmt, args...) \ -+ printk(KERN_ERR "%s: " fmt, __func__, ## args) -+ -+static inline void mbs_grab(void) -+{ -+ while (mbs_r32(mbsr0) != 0); -+} -+ -+static inline void mbs_release(void) -+{ -+ mbs_w32(0, mbsr0); -+ asm("sync"); -+} -+ -+/* max ports connecting to dma */ -+#define LTQ_MAX_DMA_DEVICE_NUM ARRAY_SIZE(dma_devices) -+/* max dma channels */ -+#define LTQ_MAX_DMA_CHANNEL_NUM ARRAY_SIZE(dma_chan) -+ -+/* bytes per descriptor */ -+#define DMA_DESCR_SIZE 8 -+ -+#define DMA_DESCR_CH_SIZE (DMA_DESCR_NUM * DMA_DESCR_SIZE) -+#define DMA_DESCR_TOTAL_SIZE (LTQ_MAX_DMA_CHANNEL_NUM * DMA_DESCR_CH_SIZE) -+#define DMA_DESCR_MEM_PAGES ((DMA_DESCR_TOTAL_SIZE / PAGE_SIZE) + \ -+ (((DMA_DESCR_TOTAL_SIZE % PAGE_SIZE) > 0))) -+ -+/* budget for interrupt handling */ -+#define DMA_INT_BUDGET 100 -+/* set the correct counter value here! */ -+#define DMA_POLL_COUNTER 32 -+ -+struct proc_dir_entry *g_dma_dir; -+ -+/* device_name | max_rx_chan_num | max_tx_chan_num | drop_enable */ -+struct dma_device_info dma_devices[] = { -+ { "SW", 4, 4, 0 }, -+ { "DEU", 1, 1, 0 }, -+ { "SSC0", 1, 1, 0 }, -+ { "SSC1", 1, 1, 0 }, -+ { "MCTRL", 1, 1, 0 }, -+ { "PCM0", 1, 1, 0 }, -+ { "PCM1", 1, 1, 0 }, -+ { "PCM2", 1, 1, 0 }, -+ { "PCM3", 1, 1, 0 } -+}; -+ -+/* *dma_dev | dir | pri | irq | rel_chan_no */ -+struct dma_channel_info dma_chan[] = { -+ { &dma_devices[0], DIR_RX, 0, INT_NUM_IM4_IRL0 + 0, 0 }, -+ { &dma_devices[0], DIR_TX, 0, INT_NUM_IM4_IRL0 + 1, 0 }, -+ { &dma_devices[0], DIR_RX, 1, INT_NUM_IM4_IRL0 + 2, 1 }, -+ { &dma_devices[0], DIR_TX, 1, INT_NUM_IM4_IRL0 + 3, 1 }, -+ { &dma_devices[0], DIR_RX, 2, INT_NUM_IM4_IRL0 + 4, 2 }, -+ { &dma_devices[0], DIR_TX, 2, INT_NUM_IM4_IRL0 + 5, 2 }, -+ { &dma_devices[0], DIR_RX, 3, INT_NUM_IM4_IRL0 + 6, 3 }, -+ { &dma_devices[0], DIR_TX, 3, INT_NUM_IM4_IRL0 + 7, 3 }, -+ { &dma_devices[1], DIR_RX, 0, INT_NUM_IM4_IRL0 + 8, 0 }, -+ { &dma_devices[1], DIR_TX, 0, INT_NUM_IM4_IRL0 + 9, 0 }, -+ { &dma_devices[2], DIR_RX, 0, INT_NUM_IM4_IRL0 + 10, 0 }, -+ { &dma_devices[2], DIR_TX, 0, INT_NUM_IM4_IRL0 + 11, 0 }, -+ { &dma_devices[3], DIR_RX, 0, INT_NUM_IM4_IRL0 + 12, 0 }, -+ { &dma_devices[3], DIR_TX, 0, INT_NUM_IM4_IRL0 + 13, 0 }, -+ { &dma_devices[4], DIR_RX, 0, INT_NUM_IM4_IRL0 + 14, 0 }, -+ { &dma_devices[4], DIR_TX, 0, INT_NUM_IM4_IRL0 + 15, 0 }, -+ { &dma_devices[5], DIR_RX, 0, INT_NUM_IM4_IRL0 + 16, 0 }, -+ { &dma_devices[5], DIR_TX, 0, INT_NUM_IM4_IRL0 + 17, 0 }, -+ { &dma_devices[6], DIR_RX, 1, INT_NUM_IM3_IRL0 + 18, 0 }, -+ { &dma_devices[6], DIR_TX, 1, INT_NUM_IM3_IRL0 + 19, 0 }, -+ { &dma_devices[7], DIR_RX, 2, INT_NUM_IM4_IRL0 + 20, 0 }, -+ { &dma_devices[7], DIR_TX, 2, INT_NUM_IM4_IRL0 + 21, 0 }, -+ { &dma_devices[8], DIR_RX, 3, INT_NUM_IM4_IRL0 + 22, 0 }, -+ { &dma_devices[8], DIR_TX, 3, INT_NUM_IM4_IRL0 + 23, 0 } -+}; -+ -+u64 *g_desc_list[DMA_DESCR_MEM_PAGES]; -+ -+volatile u32 g_dma_int_status = 0; -+ -+/* 0 - not in process, 1 - in process */ -+volatile int g_dma_in_process; -+ -+int ltq_dma_init(void); -+void do_dma_tasklet(unsigned long); -+DECLARE_TASKLET(dma_tasklet, do_dma_tasklet, 0); -+irqreturn_t dma_interrupt(int irq, void *dev_id); -+ -+u8 *common_buffer_alloc(int len, int *byte_offset, void **opt) -+{ -+ u8 *buffer = kmalloc(len * sizeof(u8), GFP_KERNEL); -+ *byte_offset = 0; -+ return buffer; -+} -+ -+void common_buffer_free(u8 *dataptr, void *opt) -+{ -+ kfree(dataptr); -+} -+ -+void enable_ch_irq(struct dma_channel_info *ch) -+{ -+ int chan_no = (int)(ch - dma_chan); -+ unsigned long flag; -+ u32 val; -+ -+ if (ch->dir == DIR_RX) -+ val = DMA_CIE_DESCPT | DMA_CIE_DUR; -+ else -+ val = DMA_CIE_DESCPT; -+ -+ local_irq_save(flag); -+ mbs_grab(); -+ dma_w32(chan_no, cs); -+ dma_w32(val, cie); -+ dma_w32_mask(0, 1 << chan_no, irnen); -+ mbs_release(); -+ local_irq_restore(flag); -+ -+ svip_enable_irq(ch->irq); -+} -+ -+void disable_ch_irq(struct dma_channel_info *ch) -+{ -+ unsigned long flag; -+ int chan_no = (int)(ch - dma_chan); -+ -+ local_irq_save(flag); -+ g_dma_int_status &= ~(1 << chan_no); -+ mbs_grab(); -+ dma_w32(chan_no, cs); -+ dma_w32(0, cie); -+ mbs_release(); -+ dma_w32_mask(1 << chan_no, 0, irnen); -+ local_irq_restore(flag); -+ -+ mask_and_ack_irq(ch->irq); -+} -+ -+int open_chan(struct dma_channel_info *ch) -+{ -+ unsigned long flag; -+ int j; -+ int chan_no = (int)(ch - dma_chan); -+ u8 *buffer; -+ int byte_offset; -+ struct rx_desc *rx_desc_p; -+ struct tx_desc *tx_desc_p; -+ -+ if (ch->control == LTQ_DMA_CH_ON) -+ return -1; -+ -+ if (ch->dir == DIR_RX) { -+ for (j = 0; j < ch->desc_len; j++) { -+ rx_desc_p = (struct rx_desc *)ch->desc_base+j; -+ buffer = ch->dma_dev->buffer_alloc(ch->packet_size, -+ &byte_offset, -+ (void *)&ch->opt[j]); -+ if (!buffer) -+ return -ENOBUFS; -+ -+ rx_desc_p->data_pointer = (u32)CPHYSADDR((u32)buffer); -+ rx_desc_p->status.word = 0; -+ rx_desc_p->status.field.byte_offset = byte_offset; -+ rx_desc_p->status.field.data_length = ch->packet_size; -+ rx_desc_p->status.field.own = DMA_OWN; -+ } -+ } else { -+ for (j = 0; j < ch->desc_len; j++) { -+ tx_desc_p = (struct tx_desc *)ch->desc_base + j; -+ tx_desc_p->data_pointer = 0; -+ tx_desc_p->status.word = 0; -+ } -+ } -+ ch->xfer_cnt = 0; -+ -+ local_irq_save(flag); -+ mbs_grab(); -+ dma_w32(chan_no, cs); -+ dma_w32(ch->desc_len, cdlen); -+ dma_w32(0x7e, cis); -+ dma_w32(DMA_CCTRL_TXWGT_VAL(ch->tx_weight) -+ | DMA_CCTRL_CLASS_VAL(ch->pri) -+ | (ch->dir == DIR_RX ? DMA_CCTRL_ON_OFF : 0), cctrl); -+ mbs_release(); -+ ch->control = LTQ_DMA_CH_ON; -+ local_irq_restore(flag); -+ -+ if (request_irq(ch->irq, dma_interrupt, -+ IRQF_DISABLED, "dma-core", (void *)ch) != 0) { -+ printk(KERN_ERR "error, cannot get dma_irq!\n"); -+ return -EFAULT; -+ } -+ -+ enable_ch_irq(ch); -+ return 0; -+} -+ -+int close_chan(struct dma_channel_info *ch) -+{ -+ unsigned long flag; -+ int j; -+ int chan_no = (int)(ch - dma_chan); -+ struct rx_desc *desc_p; -+ -+ if (ch->control == LTQ_DMA_CH_OFF) -+ return -1; -+ -+ local_irq_save(flag); -+ mbs_grab(); -+ dma_w32(chan_no, cs); -+ dma_w32_mask(DMA_CCTRL_ON_OFF, 0, cctrl); -+ mbs_release(); -+ disable_ch_irq(ch); -+ free_irq(ch->irq, (void *)ch); -+ ch->control = LTQ_DMA_CH_OFF; -+ local_irq_restore(flag); -+ -+ /* free descriptors in use */ -+ for (j = 0; j < ch->desc_len; j++) { -+ desc_p = (struct rx_desc *)ch->desc_base+j; -+ if ((desc_p->status.field.own == CPU_OWN && -+ desc_p->status.field.c) || -+ (desc_p->status.field.own == DMA_OWN)) { -+ if (desc_p->data_pointer) { -+ ch->dma_dev->buffer_free((u8 *)__va(desc_p->data_pointer), -+ (void *)ch->opt[j]); -+ desc_p->data_pointer = (u32)NULL; -+ } -+ } -+ } -+ -+ return 0; -+} -+ -+int reset_chan(struct dma_channel_info *ch) -+{ -+ unsigned long flag; -+ int val; -+ int chan_no = (int)(ch - dma_chan); -+ -+ close_chan(ch); -+ -+ local_irq_save(flag); -+ mbs_grab(); -+ dma_w32(chan_no, cs); -+ dma_w32_mask(0, DMA_CCTRL_RST, cctrl); -+ mbs_release(); -+ local_irq_restore(flag); -+ -+ do { -+ local_irq_save(flag); -+ mbs_grab(); -+ dma_w32(chan_no, cs); -+ val = dma_r32(cctrl); -+ mbs_release(); -+ local_irq_restore(flag); -+ } while (val & DMA_CCTRL_RST); -+ -+ return 0; -+} -+ -+static inline void rx_chan_intr_handler(int chan_no) -+{ -+ struct dma_device_info *dma_dev = (struct dma_device_info *) -+ dma_chan[chan_no].dma_dev; -+ struct dma_channel_info *ch = &dma_chan[chan_no]; -+ struct rx_desc *rx_desc_p; -+ unsigned long flag; -+ u32 val; -+ -+ local_irq_save(flag); -+ mbs_grab(); -+ dma_w32(chan_no, cs); -+ val = dma_r32(cis); -+ dma_w32(DMA_CIS_DESCPT, cis); -+ mbs_release(); -+ -+ /* handle command complete interrupt */ -+ rx_desc_p = (struct rx_desc *)ch->desc_base + ch->curr_desc; -+ if ((rx_desc_p->status.word & (DMA_DESC_OWN_DMA | DMA_DESC_CPT_SET)) == -+ DMA_DESC_CPT_SET) { -+ local_irq_restore(flag); -+ /* Every thing is correct, then we inform the upper layer */ -+ dma_dev->current_rx_chan = ch->rel_chan_no; -+ if (dma_dev->intr_handler) -+ dma_dev->intr_handler(dma_dev, RCV_INT); -+ ch->weight--; -+ } else { -+ g_dma_int_status &= ~(1 << chan_no); -+ local_irq_restore(flag); -+ svip_enable_irq(dma_chan[chan_no].irq); -+ } -+} -+ -+static inline void tx_chan_intr_handler(int chan_no) -+{ -+ struct dma_device_info *dma_dev = (struct dma_device_info *) -+ dma_chan[chan_no].dma_dev; -+ struct dma_channel_info *ch = &dma_chan[chan_no]; -+ struct tx_desc *tx_desc_p; -+ unsigned long flag; -+ -+ local_irq_save(flag); -+ mbs_grab(); -+ dma_w32(chan_no, cs); -+ dma_w32(DMA_CIS_DESCPT, cis); -+ mbs_release(); -+ -+ tx_desc_p = (struct tx_desc *)ch->desc_base+ch->prev_desc; -+ if ((tx_desc_p->status.word & (DMA_DESC_OWN_DMA | DMA_DESC_CPT_SET)) == -+ DMA_DESC_CPT_SET) { -+ local_irq_restore(flag); -+ -+ dma_dev->buffer_free((u8 *)__va(tx_desc_p->data_pointer), -+ ch->opt[ch->prev_desc]); -+ memset(tx_desc_p, 0, sizeof(struct tx_desc)); -+ dma_dev->current_tx_chan = ch->rel_chan_no; -+ if (dma_dev->intr_handler) -+ dma_dev->intr_handler(dma_dev, TRANSMIT_CPT_INT); -+ ch->weight--; -+ -+ ch->prev_desc = (ch->prev_desc + 1) % (ch->desc_len); -+ } else { -+ g_dma_int_status &= ~(1 << chan_no); -+ local_irq_restore(flag); -+ svip_enable_irq(dma_chan[chan_no].irq); -+ } -+} -+ -+void do_dma_tasklet(unsigned long unused) -+{ -+ int i; -+ int chan_no = 0; -+ int budget = DMA_INT_BUDGET; -+ int weight = 0; -+ unsigned long flag; -+ -+ while (g_dma_int_status) { -+ if (budget-- < 0) { -+ tasklet_schedule(&dma_tasklet); -+ return; -+ } -+ chan_no = -1; -+ weight = 0; -+ /* WFQ algorithm to select the channel */ -+ for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { -+ if (g_dma_int_status & (1 << i) && -+ dma_chan[i].weight > 0) { -+ if (dma_chan[i].weight > weight) { -+ chan_no = i; -+ weight = dma_chan[chan_no].weight; -+ } -+ } -+ } -+ if (chan_no >= 0) { -+ if (dma_chan[chan_no].dir == DIR_RX) -+ rx_chan_intr_handler(chan_no); -+ else -+ tx_chan_intr_handler(chan_no); -+ } else { -+ /* reset all the channels */ -+ for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) -+ dma_chan[i].weight = dma_chan[i].default_weight; -+ } -+ } -+ -+ local_irq_save(flag); -+ g_dma_in_process = 0; -+ if (g_dma_int_status) { -+ g_dma_in_process = 1; -+ tasklet_schedule(&dma_tasklet); -+ } -+ local_irq_restore(flag); -+} -+ -+irqreturn_t dma_interrupt(int irq, void *dev_id) -+{ -+ struct dma_channel_info *ch; -+ int chan_no = 0; -+ -+ ch = (struct dma_channel_info *)dev_id; -+ chan_no = (int)(ch - dma_chan); -+ -+ if ((unsigned)chan_no >= LTQ_MAX_DMA_CHANNEL_NUM) { -+ printk(KERN_ERR "error: dma_interrupt irq=%d chan_no=%d\n", -+ irq, chan_no); -+ } -+ -+ g_dma_int_status |= 1 << chan_no; -+ dma_w32(1 << chan_no, irncr); -+ mask_and_ack_irq(irq); -+ -+ if (!g_dma_in_process) { -+ g_dma_in_process = 1; -+ tasklet_schedule(&dma_tasklet); -+ } -+ -+ return IRQ_RETVAL(1); -+} -+ -+struct dma_device_info *dma_device_reserve(char *dev_name) -+{ -+ int i; -+ -+ ltq_dma_init(); -+ for (i = 0; i < LTQ_MAX_DMA_DEVICE_NUM; i++) { -+ if (strcmp(dev_name, dma_devices[i].device_name) == 0) { -+ if (dma_devices[i].reserved) -+ return NULL; -+ dma_devices[i].reserved = 1; -+ break; -+ } -+ } -+ -+ if (i == LTQ_MAX_DMA_DEVICE_NUM) -+ return NULL; -+ -+ return &dma_devices[i]; -+} -+EXPORT_SYMBOL(dma_device_reserve); -+ -+int dma_device_release(struct dma_device_info *dma_dev) -+{ -+ dma_dev->reserved = 0; -+ -+ return 0; -+} -+EXPORT_SYMBOL(dma_device_release); -+ -+int dma_device_register(struct dma_device_info *dma_dev) -+{ -+ int port_no = (int)(dma_dev - dma_devices); -+ int txbl, rxbl; -+ unsigned long flag; -+ -+ switch (dma_dev->tx_burst_len) { -+ case 8: -+ txbl = 3; -+ break; -+ case 4: -+ txbl = 2; -+ break; -+ default: -+ txbl = 1; -+ break; -+ } -+ -+ switch (dma_dev->rx_burst_len) { -+ case 8: -+ rxbl = 3; -+ break; -+ case 4: -+ rxbl = 2; -+ break; -+ default: -+ rxbl = 1; -+ } -+ -+ local_irq_save(flag); -+ mbs_grab(); -+ dma_w32(port_no, ps); -+ dma_w32(DMA_PCTRL_TXWGT_VAL(dma_dev->tx_weight) -+ | DMA_PCTRL_TXENDI_VAL(dma_dev->tx_endianness_mode) -+ | DMA_PCTRL_RXENDI_VAL(dma_dev->rx_endianness_mode) -+ | DMA_PCTRL_PDEN_VAL(dma_dev->drop_enable) -+ | DMA_PCTRL_TXBL_VAL(txbl) -+ | DMA_PCTRL_RXBL_VAL(rxbl), pctrl); -+ mbs_release(); -+ local_irq_restore(flag); -+ -+ return 0; -+} -+EXPORT_SYMBOL(dma_device_register); -+ -+int dma_device_unregister(struct dma_device_info *dma_dev) -+{ -+ int i; -+ int port_no = (int)(dma_dev - dma_devices); -+ unsigned long flag; -+ -+ /* flush memcopy module; has no effect for other ports */ -+ local_irq_save(flag); -+ mbs_grab(); -+ dma_w32(port_no, ps); -+ dma_w32_mask(0, DMA_PCTRL_GPC, pctrl); -+ mbs_release(); -+ local_irq_restore(flag); -+ -+ for (i = 0; i < dma_dev->max_tx_chan_num; i++) -+ reset_chan(dma_dev->tx_chan[i]); -+ -+ for (i = 0; i < dma_dev->max_rx_chan_num; i++) -+ reset_chan(dma_dev->rx_chan[i]); -+ -+ return 0; -+} -+EXPORT_SYMBOL(dma_device_unregister); -+ -+/** -+ * Read Packet from DMA Rx channel. -+ * The function gets the data from the current rx descriptor assigned -+ * to the passed DMA device and passes it back to the caller. -+ * The function is called in the context of DMA interrupt. -+ * In detail the following actions are done: -+ * - get current receive descriptor -+ * - allocate memory via allocation callback function -+ * - pass data from descriptor to allocated memory -+ * - update channel weight -+ * - release descriptor -+ * - update current descriptor position -+ * -+ * \param *dma_dev - pointer to DMA device structure -+ * \param **dataptr - pointer to received data -+ * \param **opt -+ * \return packet length - length of received data -+ * \ingroup Internal -+ */ -+int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt) -+{ -+ u8 *buf; -+ int len; -+ int byte_offset = 0; -+ void *p = NULL; -+ -+ struct dma_channel_info *ch = -+ dma_dev->rx_chan[dma_dev->current_rx_chan]; -+ -+ struct rx_desc *rx_desc_p; -+ -+ /* get the rx data first */ -+ rx_desc_p = (struct rx_desc *)ch->desc_base+ch->curr_desc; -+ buf = (u8 *)__va(rx_desc_p->data_pointer); -+ *(u32 *)dataptr = (u32)buf; -+ len = rx_desc_p->status.field.data_length; -+#ifndef CONFIG_MIPS_UNCACHED -+ dma_cache_inv((unsigned long)buf, len); -+#endif -+ if (opt) -+ *(int *)opt = (int)ch->opt[ch->curr_desc]; -+ -+ /* replace with a new allocated buffer */ -+ buf = dma_dev->buffer_alloc(ch->packet_size, &byte_offset, &p); -+ if (buf) { -+ ch->opt[ch->curr_desc] = p; -+ -+ wmb(); -+ rx_desc_p->data_pointer = (u32)CPHYSADDR((u32)buf); -+ rx_desc_p->status.word = (DMA_OWN << 31) \ -+ |(byte_offset << 23) \ -+ | ch->packet_size; -+ -+ wmb(); -+ } else { -+ *(u32 *)dataptr = 0; -+ if (opt) -+ *(int *)opt = 0; -+ } -+ -+ ch->xfer_cnt++; -+ /* increase the curr_desc pointer */ -+ ch->curr_desc++; -+ if (ch->curr_desc == ch->desc_len) -+ ch->curr_desc = 0; -+ /* return the length of the received packet */ -+ return len; -+} -+EXPORT_SYMBOL(dma_device_read); -+ -+/** -+ * Write Packet through DMA Tx channel to peripheral. -+ * -+ * \param *dma_dev - pointer to DMA device structure -+ * \param *dataptr - pointer to data to be sent -+ * \param len - amount of data bytes to be sent -+ * \param *opt -+ * \return len - length of transmitted data -+ * \ingroup Internal -+ */ -+int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, int len, -+ void *opt) -+{ -+ unsigned long flag; -+ u32 byte_offset; -+ struct dma_channel_info *ch; -+ int chan_no; -+ struct tx_desc *tx_desc_p; -+ local_irq_save(flag); -+ -+ ch = dma_dev->tx_chan[dma_dev->current_tx_chan]; -+ chan_no = (int)(ch - dma_chan); -+ -+ if (ch->control == LTQ_DMA_CH_OFF) { -+ local_irq_restore(flag); -+ printk(KERN_ERR "%s: dma channel %d not enabled!\n", -+ __func__, chan_no); -+ return 0; -+ } -+ -+ tx_desc_p = (struct tx_desc *)ch->desc_base+ch->curr_desc; -+ /* Check whether this descriptor is available */ -+ if (tx_desc_p->status.word & (DMA_DESC_OWN_DMA | DMA_DESC_CPT_SET)) { -+ /* if not , the tell the upper layer device */ -+ dma_dev->intr_handler(dma_dev, TX_BUF_FULL_INT); -+ local_irq_restore(flag); -+ return 0; -+ } -+ ch->opt[ch->curr_desc] = opt; -+ /* byte offset----to adjust the starting address of the data buffer, -+ * should be multiple of the burst length.*/ -+ byte_offset = ((u32)CPHYSADDR((u32)dataptr)) % -+ (dma_dev->tx_burst_len * 4); -+#ifndef CONFIG_MIPS_UNCACHED -+ dma_cache_wback((unsigned long)dataptr, len); -+ wmb(); -+#endif -+ tx_desc_p->data_pointer = (u32)CPHYSADDR((u32)dataptr) - byte_offset; -+ wmb(); -+ tx_desc_p->status.word = (DMA_OWN << 31) -+ | DMA_DESC_SOP_SET -+ | DMA_DESC_EOP_SET -+ | (byte_offset << 23) -+ | len; -+ wmb(); -+ -+ if (ch->xfer_cnt == 0) { -+ mbs_grab(); -+ dma_w32(chan_no, cs); -+ dma_w32_mask(0, DMA_CCTRL_ON_OFF, cctrl); -+ mbs_release(); -+ } -+ -+ ch->xfer_cnt++; -+ ch->curr_desc++; -+ if (ch->curr_desc == ch->desc_len) -+ ch->curr_desc = 0; -+ -+ local_irq_restore(flag); -+ return len; -+} -+EXPORT_SYMBOL(dma_device_write); -+ -+/** -+ * Display descriptor list via proc file -+ * -+ * \param chan_no - logical channel number -+ * \ingroup Internal -+ */ -+int desc_list_proc_read(char *buf, char **start, off_t offset, -+ int count, int *eof, void *data) -+{ -+ int len = 0; -+ int i; -+ static int chan_no; -+ u32 *p; -+ -+ if ((chan_no == 0) && (offset > count)) { -+ *eof = 1; -+ return 0; -+ } -+ -+ if (chan_no != 0) { -+ *start = buf; -+ } else { -+ buf = buf + offset; -+ *start = buf; -+ } -+ -+ p = (u32 *)dma_chan[chan_no].desc_base; -+ -+ if (dma_chan[chan_no].dir == DIR_RX) -+ len += sprintf(buf + len, -+ "channel %d %s Rx descriptor list:\n", -+ chan_no, dma_chan[chan_no].dma_dev->device_name); -+ else -+ len += sprintf(buf + len, -+ "channel %d %s Tx descriptor list:\n", -+ chan_no, dma_chan[chan_no].dma_dev->device_name); -+ len += sprintf(buf + len, -+ " no address data pointer command bits " -+ "(Own, Complete, SoP, EoP, Offset) \n"); -+ len += sprintf(buf + len, -+ "----------------------------------------------" -+ "-----------------------------------\n"); -+ for (i = 0; i < dma_chan[chan_no].desc_len; i++) { -+ len += sprintf(buf + len, "%3d ", i); -+ len += sprintf(buf + len, "0x%08x ", (u32)(p + (i * 2))); -+ len += sprintf(buf + len, "%08x ", *(p + (i * 2 + 1))); -+ len += sprintf(buf + len, "%08x ", *(p + (i * 2))); -+ -+ if (*(p + (i * 2)) & 0x80000000) -+ len += sprintf(buf + len, "D "); -+ else -+ len += sprintf(buf + len, "C "); -+ if (*(p + (i * 2)) & 0x40000000) -+ len += sprintf(buf + len, "C "); -+ else -+ len += sprintf(buf + len, "c "); -+ if (*(p + (i * 2)) & 0x20000000) -+ len += sprintf(buf + len, "S "); -+ else -+ len += sprintf(buf + len, "s "); -+ if (*(p + (i * 2)) & 0x10000000) -+ len += sprintf(buf + len, "E "); -+ else -+ len += sprintf(buf + len, "e "); -+ -+ /* byte offset is different for rx and tx descriptors*/ -+ if (dma_chan[chan_no].dir == DIR_RX) { -+ len += sprintf(buf + len, "%01x ", -+ (*(p + (i * 2)) & 0x01800000) >> 23); -+ } else { -+ len += sprintf(buf + len, "%02x ", -+ (*(p + (i * 2)) & 0x0F800000) >> 23); -+ } -+ -+ if (dma_chan[chan_no].curr_desc == i) -+ len += sprintf(buf + len, "<- CURR"); -+ -+ if (dma_chan[chan_no].prev_desc == i) -+ len += sprintf(buf + len, "<- PREV"); -+ -+ len += sprintf(buf + len, "\n"); -+ -+ } -+ -+ len += sprintf(buf + len, "\n"); -+ chan_no++; -+ if (chan_no > LTQ_MAX_DMA_CHANNEL_NUM - 1) -+ chan_no = 0; -+ -+ *eof = 1; -+ return len; -+} -+ -+/** -+ * Displays the weight of all DMA channels via proc file -+ * -+ * -+ * -+ * \param *buf -+ * \param **start -+ * \param offset -+ * \param count -+ * \param *eof -+ * \param *data -+ * \return len - amount of bytes written to file -+ */ -+int channel_weight_proc_read(char *buf, char **start, off_t offset, -+ int count, int *eof, void *data) -+{ -+ int i; -+ int len = 0; -+ len += sprintf(buf + len, "Qos dma channel weight list\n"); -+ len += sprintf(buf + len, "channel_num default_weight " -+ "current_weight device Tx/Rx\n"); -+ len += sprintf(buf + len, "---------------------------" -+ "---------------------------------\n"); -+ for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { -+ struct dma_channel_info *ch = &dma_chan[i]; -+ -+ if (ch->dir == DIR_RX) { -+ len += sprintf(buf + len, -+ " %2d %08x " -+ "%08x %10s Rx\n", -+ i, ch->default_weight, ch->weight, -+ ch->dma_dev->device_name); -+ } else { -+ len += sprintf(buf + len, -+ " %2d %08x " -+ "%08x %10s Tx\n", -+ i, ch->default_weight, ch->weight, -+ ch->dma_dev->device_name); -+ } -+ } -+ -+ return len; -+} -+ -+/** -+ * Provides DMA Register Content to proc file -+ * This function reads the content of general DMA Registers, DMA Channel -+ * Registers and DMA Port Registers and performs a structures output to the -+ * DMA proc file -+ * -+ * \param *buf -+ * \param **start -+ * \param offset -+ * \param count -+ * \param *eof -+ * \param *data -+ * \return len - amount of bytes written to file -+ */ -+int dma_register_proc_read(char *buf, char **start, off_t offset, -+ int count, int *eof, void *data) -+{ -+ int len = 0; -+ int i; -+ int limit = count; -+ unsigned long flags; -+ static int blockcount; -+ static int channel_no; -+ -+ if ((blockcount == 0) && (offset > count)) { -+ *eof = 1; -+ return 0; -+ } -+ -+ switch (blockcount) { -+ case 0: -+ len += sprintf(buf + len, "\nGeneral DMA Registers\n"); -+ len += sprintf(buf + len, "-------------------------" -+ "----------------\n"); -+ len += sprintf(buf + len, "CLC= %08x\n", dma_r32(clc)); -+ len += sprintf(buf + len, "ID= %08x\n", dma_r32(id)); -+ len += sprintf(buf + len, "DMA_CPOLL= %08x\n", dma_r32(cpoll)); -+ len += sprintf(buf + len, "DMA_CS= %08x\n", dma_r32(cs)); -+ len += sprintf(buf + len, "DMA_PS= %08x\n", dma_r32(ps)); -+ len += sprintf(buf + len, "DMA_IRNEN= %08x\n", dma_r32(irnen)); -+ len += sprintf(buf + len, "DMA_IRNCR= %08x\n", dma_r32(irncr)); -+ len += sprintf(buf + len, "DMA_IRNICR= %08x\n", -+ dma_r32(irnicr)); -+ len += sprintf(buf + len, "\nDMA Channel Registers\n"); -+ blockcount = 1; -+ return len; -+ break; -+ case 1: -+ /* If we had an overflow start at beginning of buffer -+ * otherwise use offset */ -+ if (channel_no != 0) { -+ *start = buf; -+ } else { -+ buf = buf + offset; -+ *start = buf; -+ } -+ -+ local_irq_save(flags); -+ for (i = channel_no; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { -+ struct dma_channel_info *ch = &dma_chan[i]; -+ -+ if (len + 300 > limit) { -+ local_irq_restore(flags); -+ channel_no = i; -+ blockcount = 1; -+ return len; -+ } -+ len += sprintf(buf + len, "----------------------" -+ "-------------------\n"); -+ if (ch->dir == DIR_RX) { -+ len += sprintf(buf + len, -+ "Channel %d - Device %s Rx\n", -+ i, ch->dma_dev->device_name); -+ } else { -+ len += sprintf(buf + len, -+ "Channel %d - Device %s Tx\n", -+ i, ch->dma_dev->device_name); -+ } -+ dma_w32(i, cs); -+ len += sprintf(buf + len, "DMA_CCTRL= %08x\n", -+ dma_r32(cctrl)); -+ len += sprintf(buf + len, "DMA_CDBA= %08x\n", -+ dma_r32(cdba)); -+ len += sprintf(buf + len, "DMA_CIE= %08x\n", -+ dma_r32(cie)); -+ len += sprintf(buf + len, "DMA_CIS= %08x\n", -+ dma_r32(cis)); -+ len += sprintf(buf + len, "DMA_CDLEN= %08x\n", -+ dma_r32(cdlen)); -+ } -+ local_irq_restore(flags); -+ blockcount = 2; -+ channel_no = 0; -+ return len; -+ break; -+ case 2: -+ *start = buf; -+ /* -+ * display port dependent registers -+ */ -+ len += sprintf(buf + len, "\nDMA Port Registers\n"); -+ len += sprintf(buf + len, -+ "-----------------------------------------\n"); -+ local_irq_save(flags); -+ for (i = 0; i < LTQ_MAX_DMA_DEVICE_NUM; i++) { -+ dma_w32(i, ps); -+ len += sprintf(buf + len, -+ "Port %d DMA_PCTRL= %08x\n", -+ i, dma_r32(pctrl)); -+ } -+ local_irq_restore(flags); -+ blockcount = 0; -+ *eof = 1; -+ return len; -+ break; -+ } -+ -+ blockcount = 0; -+ *eof = 1; -+ return 0; -+} -+ -+/** -+ * Open Method of DMA Device Driver -+ * This function increments the device driver's use counter. -+ * -+ * -+ * \param -+ * \return -+ */ -+static int dma_open(struct inode *inode, struct file *file) -+{ -+ return 0; -+} -+ -+/** -+ * Release Method of DMA Device driver. -+ * This function decrements the device driver's use counter. -+ * -+ * -+ * \param -+ * \return -+ */ -+static int dma_release(struct inode *inode, struct file *file) -+{ -+ /* release the resources */ -+ return 0; -+} -+ -+/** -+ * Ioctl Interface to DMA Module -+ * -+ * \param None -+ * \return 0 - initialization successful -+ * <0 - failed initialization -+ */ -+static long dma_ioctl(struct file *file, -+ unsigned int cmd, unsigned long arg) -+{ -+ int result = 0; -+ /* TODO: add some user controled functions here */ -+ return result; -+} -+ -+const static struct file_operations dma_fops = { -+ .owner = THIS_MODULE, -+ .open = dma_open, -+ .release = dma_release, -+ .unlocked_ioctl = dma_ioctl, -+}; -+ -+void map_dma_chan(struct dma_channel_info *map) -+{ -+ int i; -+ -+ /* assign default values for channel settings */ -+ for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { -+ dma_chan[i].byte_offset = 0; -+ dma_chan[i].open = &open_chan; -+ dma_chan[i].close = &close_chan; -+ dma_chan[i].reset = &reset_chan; -+ dma_chan[i].enable_irq = enable_ch_irq; -+ dma_chan[i].disable_irq = disable_ch_irq; -+ dma_chan[i].tx_weight = 1; -+ dma_chan[i].control = 0; -+ dma_chan[i].default_weight = LTQ_DMA_CH_DEFAULT_WEIGHT; -+ dma_chan[i].weight = dma_chan[i].default_weight; -+ dma_chan[i].curr_desc = 0; -+ dma_chan[i].prev_desc = 0; -+ } -+ -+ /* assign default values for port settings */ -+ for (i = 0; i < LTQ_MAX_DMA_DEVICE_NUM; i++) { -+ /*set default tx channel number to be one*/ -+ dma_devices[i].num_tx_chan = 1; -+ /*set default rx channel number to be one*/ -+ dma_devices[i].num_rx_chan = 1; -+ dma_devices[i].buffer_alloc = common_buffer_alloc; -+ dma_devices[i].buffer_free = common_buffer_free; -+ dma_devices[i].intr_handler = NULL; -+ dma_devices[i].tx_burst_len = 4; -+ dma_devices[i].rx_burst_len = 4; -+#ifdef CONFIG_CPU_LITTLE_ENDIAN -+ dma_devices[i].tx_endianness_mode = 0; -+ dma_devices[i].rx_endianness_mode = 0; -+#else -+ dma_devices[i].tx_endianness_mode = 3; -+ dma_devices[i].rx_endianness_mode = 3; -+#endif -+ } -+} -+ -+void dma_chip_init(void) -+{ -+ int i; -+ -+ sys1_w32(SYS1_CLKENR_DMA, clkenr); -+ wmb(); -+ /* reset DMA */ -+ dma_w32(DMA_CTRL_RST, ctrl); -+ wmb(); -+ /* disable all the interrupts first */ -+ dma_w32(0, irnen); -+ -+ /* enable polling for all channels */ -+ dma_w32(DMA_CPOLL_EN | DMA_CPOLL_CNT_VAL(DMA_POLL_COUNTER), cpoll); -+ -+ /****************************************************/ -+ for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) -+ disable_ch_irq(&dma_chan[i]); -+} -+ -+int ltq_dma_init(void) -+{ -+ int result = 0; -+ int i; -+ unsigned long flag; -+ static int dma_initialized; -+ -+ if (dma_initialized == 1) -+ return 0; -+ dma_initialized = 1; -+ -+ result = register_chrdev(DMA_MAJOR, "dma-core", &dma_fops); -+ if (result) { -+ DMA_EMSG("cannot register device dma-core!\n"); -+ return result; -+ } -+ -+ dma_chip_init(); -+ map_dma_chan(dma_chan); -+ -+ /* allocate DMA memory for buffer descriptors */ -+ for (i = 0; i < DMA_DESCR_MEM_PAGES; i++) { -+ g_desc_list[i] = (u64 *)__get_free_page(GFP_DMA); -+ if (g_desc_list[i] == NULL) { -+ DMA_EMSG("no memory for desriptor\n"); -+ return -ENOMEM; -+ } -+ g_desc_list[i] = (u64 *)KSEG1ADDR(g_desc_list[i]); -+ memset(g_desc_list[i], 0, PAGE_SIZE); -+ } -+ -+ for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { -+ int page_index, ch_per_page; -+ /* cross-link relative channels of a port to -+ * corresponding absolute channels */ -+ if (dma_chan[i].dir == DIR_RX) { -+ ((struct dma_device_info *)(dma_chan[i].dma_dev))-> -+ rx_chan[dma_chan[i].rel_chan_no] = &dma_chan[i]; -+ } else { -+ ((struct dma_device_info *)(dma_chan[i].dma_dev))-> -+ tx_chan[dma_chan[i].rel_chan_no] = &dma_chan[i]; -+ } -+ dma_chan[i].abs_chan_no = i; -+ -+ page_index = i * DMA_DESCR_CH_SIZE / PAGE_SIZE; -+ ch_per_page = PAGE_SIZE / DMA_DESCR_CH_SIZE + -+ ((PAGE_SIZE % DMA_DESCR_CH_SIZE) > 0); -+ dma_chan[i].desc_base = -+ (u32)g_desc_list[page_index] + -+ (i - page_index*ch_per_page) * DMA_DESCR_NUM*8; -+ dma_chan[i].curr_desc = 0; -+ dma_chan[i].desc_len = DMA_DESCR_NUM; -+ -+ local_irq_save(flag); -+ mbs_grab(); -+ dma_w32(i, cs); -+ dma_w32((u32)CPHYSADDR(dma_chan[i].desc_base), cdba); -+ mbs_release(); -+ local_irq_restore(flag); -+ } -+ -+ g_dma_dir = proc_mkdir("driver/" DRV_NAME, NULL); -+ -+ create_proc_read_entry("dma_register", -+ 0, -+ g_dma_dir, -+ dma_register_proc_read, -+ NULL); -+ -+ create_proc_read_entry("g_desc_list", -+ 0, -+ g_dma_dir, -+ desc_list_proc_read, -+ NULL); -+ -+ create_proc_read_entry("channel_weight", -+ 0, -+ g_dma_dir, -+ channel_weight_proc_read, -+ NULL); -+ -+ printk(KERN_NOTICE "SVIP DMA engine initialized\n"); -+ -+ return 0; -+} -+ -+/** -+ * Cleanup DMA device -+ * This function releases all resources used by the DMA device driver on -+ * module removal. -+ * -+ * -+ * \param None -+ * \return Nothing -+ */ -+void dma_cleanup(void) -+{ -+ int i; -+ unregister_chrdev(DMA_MAJOR, "dma-core"); -+ -+ for (i = 0; i < DMA_DESCR_MEM_PAGES; i++) -+ free_page(KSEG0ADDR((unsigned long)g_desc_list[i])); -+ remove_proc_entry("channel_weight", g_dma_dir); -+ remove_proc_entry("g_desc_list", g_dma_dir); -+ remove_proc_entry("dma_register", g_dma_dir); -+ remove_proc_entry("driver/" DRV_NAME, NULL); -+ /* release the resources */ -+ for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) -+ free_irq(dma_chan[i].irq, (void *)&dma_chan[i]); -+} -+ -+arch_initcall(ltq_dma_init); -+ -+MODULE_LICENSE("GPL"); -Index: linux-3.3.8/drivers/net/ethernet/svip_eth.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/drivers/net/ethernet/svip_eth.c 2012-07-31 20:14:58.881165968 +0200 -@@ -0,0 +1,636 @@ -+/************************************************************************ -+ * -+ * Copyright (c) 2005 -+ * Infineon Technologies AG -+ * St. Martin Strasse 53; 81669 Muenchen; Germany -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ * -+ ************************************************************************/ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#if 1 /** TODO: MOVE TO APPROPRIATE PLACE */ -+ -+#define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600 -+#define REV_MII_MODE 2 -+ -+#endif -+ -+#define DRV_NAME "ifxmips_mii0" -+ -+#include -+#include -+ -+#ifdef CONFIG_DEBUG_MINI_BOOT -+#define IKOS_MINI_BOOT -+#endif -+ -+/* debugging */ -+#undef INCAIP2_SW_DUMP -+ -+#define INCAIP2_SW_EMSG(fmt,args...) printk("%s: " fmt, __FUNCTION__ , ##args) -+ -+#define INCAIP2_SW_CHIP_NO 1 -+#define INCAIP2_SW_CHIP_ID 0 -+#define INCAIP2_SW_DEVICE_NO 1 -+ -+#ifdef INCAIP2_SW_DEBUG_MSG -+#define INCAIP2_SW_DMSG(fmt,args...) printk("%s: " fmt, __FUNCTION__ , ##args) -+#else -+#define INCAIP2_SW_DMSG(fmt,args...) -+#endif -+ -+/************************** Module Parameters *****************************/ -+static char *mode = "bridge"; -+module_param(mode, charp, 0000); -+MODULE_PARM_DESC(mode, ""); -+ -+#ifdef HAVE_TX_TIMEOUT -+static int timeout = 10*HZ; -+module_param(timeout, int, 0); -+MODULE_PARM_DESC(timeout, "Transmission watchdog timeout in seconds>"); -+#endif -+ -+#ifdef IKOS_MINI_BOOT -+#ifdef CONFIG_INCAIP2 -+extern s32 incaip2_sw_to_mbx(struct sk_buff* skb); -+#endif -+extern s32 svip_sw_to_mbx(struct sk_buff* skb); -+#endif -+ -+struct svip_mii_priv { -+ struct net_device_stats stats; -+ struct dma_device_info *dma_device; -+ struct sk_buff *skb; -+}; -+ -+static struct net_device *svip_mii0_dev; -+static unsigned char mac_addr[MAX_ADDR_LEN]; -+static unsigned char my_ethaddr[MAX_ADDR_LEN]; -+ -+/** -+ * Initialize MAC address. -+ * This function copies the ethernet address from kernel command line. -+ * -+ * \param line Pointer to parameter -+ * \return 0 OK -+ * \ingroup Internal -+ */ -+static int __init svip_eth_ethaddr_setup(char *line) -+{ -+ char *ep; -+ int i; -+ -+ memset(my_ethaddr, 0, MAX_ADDR_LEN); -+ /* there should really be routines to do this stuff */ -+ for (i = 0; i < 6; i++) -+ { -+ my_ethaddr[i] = line ? simple_strtoul(line, &ep, 16) : 0; -+ if (line) -+ line = (*ep) ? ep+1 : ep; -+ } -+ INCAIP2_SW_DMSG("mac address %2x-%2x-%2x-%2x-%2x-%2x \n" -+ ,my_ethaddr[0] -+ ,my_ethaddr[1] -+ ,my_ethaddr[2] -+ ,my_ethaddr[3] -+ ,my_ethaddr[4] -+ ,my_ethaddr[5]); -+ return 0; -+} -+__setup("ethaddr=", svip_eth_ethaddr_setup); -+ -+ -+/** -+ * Open RX DMA channels. -+ * This function opens all DMA rx channels. -+ * -+ * \param dma_dev pointer to DMA device information -+ * \ingroup Internal -+ */ -+static void svip_eth_open_rx_dma(struct dma_device_info *dma_dev) -+{ -+ int i; -+ -+ for(i=0; inum_rx_chan; i++) -+ { -+ dma_dev->rx_chan[i]->open(dma_dev->rx_chan[i]); -+ } -+} -+ -+ -+/** -+ * Open TX DMA channels. -+ * This function opens all DMA tx channels. -+ * -+ * \param dev pointer to net device structure that comprises -+ * DMA device information pointed to by it's priv field. -+ * \ingroup Internal -+ */ -+static void svip_eth_open_tx_dma(struct dma_device_info *dma_dev) -+{ -+ int i; -+ -+ for (i=0; inum_tx_chan; i++) -+ { -+ dma_dev->tx_chan[i]->open(dma_dev->tx_chan[i]); -+ } -+} -+ -+ -+#ifdef CONFIG_NET_HW_FLOWCONTROL -+/** -+ * Enable receiving DMA. -+ * This function enables the receiving DMA channel. -+ * -+ * \param dev pointer to net device structure that comprises -+ * DMA device information pointed to by it's priv field. -+ * \ingroup Internal -+ */ -+void svip_eth_xon(struct net_device *dev) -+{ -+ struct switch_priv *sw_dev = (struct switch_priv *)dev->priv; -+ struct dma_device_info* dma_dev = -+ (struct dma_device_info *)sw_dev->dma_device; -+ unsigned long flag; -+ -+ local_irq_save(flag); -+ -+ INCAIP2_SW_DMSG("wakeup\n"); -+ svip_eth_open_rx_dma(dma_dev); -+ -+ local_irq_restore(flag); -+} -+#endif /* CONFIG_NET_HW_FLOWCONTROL */ -+ -+ -+/** -+ * Open network device. -+ * This functions opens the network device and starts the interface queue. -+ * -+ * \param dev Device structure for Ethernet device -+ * \return 0 OK, device opened -+ * \return -1 Error, registering DMA device -+ * \ingroup API -+ */ -+int svip_mii_open(struct net_device *dev) -+{ -+ struct svip_mii_priv *priv = netdev_priv(dev); -+ struct dma_device_info *dma_dev = priv->dma_device; -+ -+ svip_eth_open_rx_dma(dma_dev); -+ svip_eth_open_tx_dma(dma_dev); -+ -+ netif_start_queue(dev); -+ return 0; -+} -+ -+ -+/** -+ * Close network device. -+ * This functions closes the network device, which will also stop the interface -+ * queue. -+ * -+ * \param dev Device structure for Ethernet device -+ * \return 0 OK, device closed (cannot fail) -+ * \ingroup API -+ */ -+int svip_mii_release(struct net_device *dev) -+{ -+ struct svip_mii_priv *priv = netdev_priv(dev); -+ struct dma_device_info *dma_dev = priv->dma_device; -+ int i; -+ -+ for (i = 0; i < dma_dev->max_rx_chan_num; i++) -+ dma_dev->rx_chan[i]->close(dma_dev->rx_chan[i]); -+ netif_stop_queue(dev); -+ return 0; -+} -+ -+ -+/** -+ * Read data from DMA device. -+ * This function reads data from the DMA device. The function is called by -+ * the switch/DMA pseudo interrupt handler dma_intr_handler on occurence of -+ * a DMA receive interrupt. -+ * -+ * \param dev Pointer to network device structure -+ * \param dma_dev Pointer to dma device structure -+ * \return OK In case of successful data reception from dma -+ * -EIO Incorrect opt pointer provided by device -+ * \ingroup Internal -+ */ -+int svip_mii_hw_receive(struct net_device *dev, struct dma_device_info *dma_dev) -+{ -+ struct svip_mii_priv *priv = netdev_priv(dev); -+ unsigned char *buf = NULL; -+ struct sk_buff *skb = NULL; -+ int len = 0; -+ -+ len = dma_device_read(dma_dev, &buf, (void **)&skb); -+ -+ if (len >= ETHERNET_PACKET_DMA_BUFFER_SIZE) { -+ printk(KERN_INFO DRV_NAME ": packet too large %d\n", len); -+ goto mii_hw_receive_err_exit; -+ } -+ -+ if (skb == NULL) { -+ printk(KERN_INFO DRV_NAME ": cannot restore pointer\n"); -+ goto mii_hw_receive_err_exit; -+ } -+ -+ if (len > (skb->end - skb->tail)) { -+ printk(KERN_INFO DRV_NAME ": BUG, len:%d end:%p tail:%p\n", -+ len, skb->end, skb->tail); -+ goto mii_hw_receive_err_exit; -+ } -+ -+ skb_put(skb, len); -+ skb->dev = dev; -+ skb->protocol = eth_type_trans(skb, dev); -+ netif_rx(skb); -+ -+ priv->stats.rx_packets++; -+ priv->stats.rx_bytes += len; -+ return 0; -+ -+mii_hw_receive_err_exit: -+ if (len == 0) { -+ if (skb) -+ dev_kfree_skb_any(skb); -+ priv->stats.rx_errors++; -+ priv->stats.rx_dropped++; -+ return -EIO; -+ } else { -+ return len; -+ } -+} -+ -+ -+/** -+ * Write data to Ethernet switch. -+ * This function writes the data comprised in skb structure via DMA to the -+ * Ethernet Switch. It is installed as the switch driver's hard_start_xmit -+ * method. -+ * -+ * \param skb Pointer to socket buffer structure that contains the data -+ * to be sent -+ * \param dev Pointer to network device structure which is used for -+ * data transmission -+ * \return 1 Transmission error -+ * \return 0 OK, successful data transmission -+ * \ingroup API -+ */ -+static int svip_mii_hw_tx(char *buf, int len, struct net_device *dev) -+{ -+ int ret = 0; -+ struct svip_mii_priv *priv = netdev_priv(dev); -+ struct dma_device_info *dma_dev = priv->dma_device; -+ ret = dma_device_write(dma_dev, buf, len, priv->skb); -+ return ret; -+} -+ -+static int svip_mii_tx(struct sk_buff *skb, struct net_device *dev) -+{ -+ int len; -+ char *data; -+ struct svip_mii_priv *priv = netdev_priv(dev); -+ struct dma_device_info *dma_dev = priv->dma_device; -+ -+ len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; -+ data = skb->data; -+ priv->skb = skb; -+ dev->trans_start = jiffies; -+ /* TODO: we got more than 1 dma channel, -+ so we should do something intelligent here to select one */ -+ dma_dev->current_tx_chan = 0; -+ -+ wmb(); -+ -+ if (svip_mii_hw_tx(data, len, dev) != len) { -+ dev_kfree_skb_any(skb); -+ priv->stats.tx_errors++; -+ priv->stats.tx_dropped++; -+ } else { -+ priv->stats.tx_packets++; -+ priv->stats.tx_bytes += len; -+ } -+ -+ return 0; -+} -+ -+ -+/** -+ * Transmission timeout callback. -+ * This functions is called when a trasmission timeout occurs. It will wake up -+ * the interface queue again. -+ * -+ * \param dev Device structure for Ethernet device -+ * \ingroup API -+ */ -+void svip_mii_tx_timeout(struct net_device *dev) -+{ -+ int i; -+ struct svip_mii_priv *priv = netdev_priv(dev); -+ -+ priv->stats.tx_errors++; -+ for (i = 0; i < priv->dma_device->max_tx_chan_num; i++) -+ priv->dma_device->tx_chan[i]->disable_irq(priv->dma_device->tx_chan[i]); -+ netif_wake_queue(dev); -+ return; -+} -+ -+ -+/** -+ * Get device statistics. -+ * This functions returns the device statistics, stored in the device structure. -+ * -+ * \param dev Device structure for Ethernet device -+ * \return stats Pointer to statistics structure -+ * \ingroup API -+ */ -+static struct net_device_stats *svip_get_stats(struct net_device *dev) -+{ -+ struct svip_mii_priv *priv = netdev_priv(dev); -+ return &priv->stats; -+} -+ -+ -+/** -+ * Pseudo Interrupt handler for DMA. -+ * This function processes DMA interrupts notified to the switch device driver. -+ * The function is installed at the DMA core as interrupt handler for the -+ * switch dma device. -+ * It handles the following DMA interrupts: -+ * passes received data to the upper layer in case of rx interrupt, -+ * In case of a dma receive interrupt the received data is passed to the upper layer. -+ * In case of a transmit buffer full interrupt the transmit queue is stopped. -+ * In case of a transmission complete interrupt the transmit queue is restarted. -+ * -+ * \param dma_dev pointer to dma device structure -+ * \param status type of interrupt being notified (RCV_INT: dma receive -+ * interrupt, TX_BUF_FULL_INT: transmit buffer full interrupt, -+ * TRANSMIT_CPT_INT: transmission complete interrupt) -+ * \return OK In case of successful data reception from dma -+ * \ingroup Internal -+ */ -+int dma_intr_handler(struct dma_device_info *dma_dev, int status) -+{ -+ int i; -+ -+ switch (status) { -+ case RCV_INT: -+ svip_mii_hw_receive(svip_mii0_dev, dma_dev); -+ break; -+ -+ case TX_BUF_FULL_INT: -+ printk(KERN_INFO DRV_NAME ": tx buffer full\n"); -+ netif_stop_queue(svip_mii0_dev); -+ for (i = 0; i < dma_dev->max_tx_chan_num; i++) { -+ if ((dma_dev->tx_chan[i])->control == LTQ_DMA_CH_ON) -+ dma_dev->tx_chan[i]->enable_irq(dma_dev->tx_chan[i]); -+ } -+ break; -+ -+ case TRANSMIT_CPT_INT: -+ -+#if 0 -+ for (i = 0; i < dma_dev->max_tx_chan_num; i++) -+#if 0 -+ dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i]); -+#else -+ dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i], (char *)__FUNCTION__); -+#endif -+ netif_wake_queue(svip_mii0_dev); -+#endif -+ break; -+ } -+ -+ return 0; -+} -+ -+ -+/** -+ * Allocates buffer sufficient for Ethernet Frame. -+ * This function is installed as DMA callback function to be called on DMA -+ * receive interrupt. -+ * -+ * \param len Unused -+ * \param *byte_offset Pointer to byte offset -+ * \param **opt pointer to skb structure -+ * \return NULL In case of buffer allocation fails -+ * buffer Pointer to allocated memory -+ * \ingroup Internal -+ */ -+unsigned char *svip_etop_dma_buffer_alloc(int len, int *byte_offset, void **opt) -+{ -+ unsigned char *buffer = NULL; -+ struct sk_buff *skb = NULL; -+ -+ skb = dev_alloc_skb(ETHERNET_PACKET_DMA_BUFFER_SIZE); -+ if (skb == NULL) -+ return NULL; -+ -+ buffer = (unsigned char *)(skb->data); -+ skb_reserve(skb, 2); -+ *(int *)opt = (int)skb; -+ *byte_offset = 2; -+ -+ return buffer; -+} -+ -+ -+/** -+ * Free DMA buffer. -+ * This function frees a buffer, which can be either a data buffer or an -+ * skb structure. -+ * -+ * \param *dataptr Pointer to data buffer -+ * \param *opt Pointer to skb structure -+ * \return 0 OK -+ * \ingroup Internal -+ */ -+void svip_etop_dma_buffer_free(unsigned char *dataptr, void *opt) -+{ -+ struct sk_buff *skb = NULL; -+ -+ if (opt == NULL) { -+ kfree(dataptr); -+ } else { -+ skb = (struct sk_buff *)opt; -+ dev_kfree_skb_any(skb); -+ } -+} -+ -+static int svip_mii_dev_init(struct net_device *dev); -+ -+static const struct net_device_ops svip_eth_netdev_ops = { -+ .ndo_init = svip_mii_dev_init, -+ .ndo_open = svip_mii_open, -+ .ndo_stop = svip_mii_release, -+ .ndo_start_xmit = svip_mii_tx, -+ .ndo_get_stats = svip_get_stats, -+ .ndo_tx_timeout = svip_mii_tx_timeout, -+}; -+ -+//#include -+ -+/** -+ * Initialize switch driver. -+ * This functions initializes the switch driver structures and registers the -+ * Ethernet device. -+ * -+ * \param dev Device structure for Ethernet device -+ * \return 0 OK -+ * \return ENOMEM No memory for structures available -+ * \return -1 Error during DMA init or Ethernet address configuration. -+ * \ingroup API -+ */ -+static int svip_mii_dev_init(struct net_device *dev) -+{ -+ int i; -+ struct svip_mii_priv *priv = netdev_priv(dev); -+ -+ -+ ether_setup(dev); -+ printk(KERN_INFO DRV_NAME ": %s is up\n", dev->name); -+ dev->watchdog_timeo = 10 * HZ; -+ memset(priv, 0, sizeof(*priv)); -+ priv->dma_device = dma_device_reserve("SW"); -+ if (!priv->dma_device) { -+ BUG(); -+ return -ENODEV; -+ } -+ priv->dma_device->buffer_alloc = svip_etop_dma_buffer_alloc; -+ priv->dma_device->buffer_free = svip_etop_dma_buffer_free; -+ priv->dma_device->intr_handler = dma_intr_handler; -+ -+ for (i = 0; i < priv->dma_device->max_rx_chan_num; i++) -+ priv->dma_device->rx_chan[i]->packet_size = -+ ETHERNET_PACKET_DMA_BUFFER_SIZE; -+ -+ for (i = 0; i < priv->dma_device->max_tx_chan_num; i++) { -+ priv->dma_device->tx_chan[i]->tx_weight=DEFAULT_SW_CHANNEL_WEIGHT; -+ priv->dma_device->tx_chan[i]->packet_size = -+ ETHERNET_PACKET_DMA_BUFFER_SIZE; -+ } -+ -+ dma_device_register(priv->dma_device); -+ -+ printk(KERN_INFO DRV_NAME ": using mac="); -+ -+ for (i = 0; i < 6; i++) { -+ dev->dev_addr[i] = mac_addr[i]; -+ printk("%02X%c", dev->dev_addr[i], (i == 5) ? ('\n') : (':')); -+ } -+ -+ return 0; -+} -+ -+static void svip_mii_chip_init(int mode) -+{ -+} -+ -+static int svip_mii_probe(struct platform_device *dev) -+{ -+ int result = 0; -+ unsigned char *mac = (unsigned char *)dev->dev.platform_data; -+ svip_mii0_dev = alloc_etherdev(sizeof(struct svip_mii_priv)); -+ svip_mii0_dev->netdev_ops = &svip_eth_netdev_ops; -+ memcpy(mac_addr, mac, 6); -+ strcpy(svip_mii0_dev->name, "eth%d"); -+ svip_mii_chip_init(REV_MII_MODE); -+ result = register_netdev(svip_mii0_dev); -+ if (result) { -+ printk(KERN_INFO DRV_NAME -+ ": error %i registering device \"%s\"\n", -+ result, svip_mii0_dev->name); -+ goto out; -+ } -+ printk(KERN_INFO DRV_NAME ": driver loaded!\n"); -+ -+out: -+ return result; -+} -+ -+static int svip_mii_remove(struct platform_device *dev) -+{ -+ struct svip_mii_priv *priv = netdev_priv(svip_mii0_dev); -+ -+ printk(KERN_INFO DRV_NAME ": cleanup\n"); -+ -+ dma_device_unregister(priv->dma_device); -+ dma_device_release(priv->dma_device); -+ kfree(priv->dma_device); -+ unregister_netdev(svip_mii0_dev); -+ free_netdev(svip_mii0_dev); -+ return 0; -+} -+ -+ -+static struct platform_driver svip_mii_driver = { -+ .probe = svip_mii_probe, -+ .remove = svip_mii_remove, -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+ -+/** -+ * Initialize switch driver as module. -+ * This functions initializes the switch driver structures and registers the -+ * Ethernet device for module usage. -+ * -+ * \return 0 OK -+ * \return ENODEV An error occured during initialization -+ * \ingroup API -+ */ -+int __init svip_mii_init(void) -+{ -+ int ret = platform_driver_register(&svip_mii_driver); -+ if (ret) -+ printk(KERN_INFO DRV_NAME -+ ": Error registering platfom driver!\n"); -+ return ret; -+} -+ -+ -+/** -+ * Remove driver module. -+ * This functions removes the driver and unregisters all devices. -+ * -+ * \ingroup API -+ */ -+static void __exit svip_mii_cleanup(void) -+{ -+ platform_driver_unregister(&svip_mii_driver); -+} -+ -+module_init(svip_mii_init); -+module_exit(svip_mii_cleanup); -+ -+MODULE_LICENSE("GPL"); -Index: linux-3.3.8/arch/mips/lantiq/svip/mux.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/lantiq/svip/mux.c 2012-07-31 19:51:34.149105918 +0200 -@@ -0,0 +1,187 @@ -+/************************************************************************ -+ * -+ * Copyright (c) 2007 -+ * Infineon Technologies AG -+ * St. Martin Strasse 53; 81669 Muenchen; Germany -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ * -+ ************************************************************************/ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#define DRV_NAME "ltq_mux" -+ -+static void ltq_mux_port_init(const int port, -+ const struct ltq_mux_pin *pins, -+ const int pin_max) -+{ -+ unsigned int i; -+ -+ for (i = 0; i < pin_max; i++) -+ ltq_gpio_configure(port, -+ i, -+ pins[i].dirin, -+ pins[i].puen, -+ pins[i].altsel0, -+ pins[i].altsel1); -+} -+ -+static int ltq_mux_probe(struct platform_device *pdev) -+{ -+ struct ltq_mux_settings *mux_settings = dev_get_platdata(&pdev->dev); -+ -+ if (mux_settings->mux_p0) -+ ltq_mux_port_init(0, -+ mux_settings->mux_p0, -+ LTQ_MUX_P0_PINS); -+ -+ if (mux_settings->mux_p1) -+ ltq_mux_port_init(1, -+ mux_settings->mux_p1, -+ LTQ_MUX_P1_PINS); -+ -+ if (mux_settings->mux_p2) -+ ltq_mux_port_init(2, -+ mux_settings->mux_p2, -+ LTQ_MUX_P2_PINS); -+ -+ if (mux_settings->mux_p3) -+ ltq_mux_port_init(3, -+ mux_settings->mux_p3, -+ LTQ_MUX_P3_PINS); -+ -+ if (mux_settings->mux_p4) -+ ltq_mux_port_init(4, -+ mux_settings->mux_p4, -+ LTQ_MUX_P4_PINS); -+ -+ return 0; -+} -+ -+int ltq_mux_read_procmem(char *buf, char **start, off_t offset, -+ int count, int *eof, void *data) -+{ -+ int len = 0; -+ int t = 0, i = 0; -+ u32 port_clk[5] = { -+ SYS1_CLKENR_PORT0, -+ SYS1_CLKENR_PORT1, -+ SYS1_CLKENR_PORT2, -+ SYS1_CLKENR_PORT3, -+ SYS2_CLKENR_PORT4, -+ }; -+ -+#define PROC_PRINT(fmt, args...) \ -+ do { \ -+ int c_len = 0; \ -+ c_len = snprintf(buf + len, count - len, fmt, ## args); \ -+ if (c_len <= 0) \ -+ goto out; \ -+ if (c_len >= (count - len)) { \ -+ len += (count - len); \ -+ goto out; \ -+ } \ -+ len += c_len; \ -+ if (offset > 0) { \ -+ if (len > offset) { \ -+ len -= offset; \ -+ memmove(buf, buf + offset, len); \ -+ offset = 0; \ -+ } else { \ -+ offset -= len; \ -+ len = 0; \ -+ } \ -+ } \ -+ } while (0) -+ -+ PROC_PRINT("\nVINETIC-SVIP Multiplex Settings\n"); -+ PROC_PRINT(" 3 2 1 0\n"); -+ PROC_PRINT(" 10987654321098765432109876543210\n"); -+ PROC_PRINT(" --------------------------------\n"); -+ -+ for (i = 0; i < ARRAY_SIZE(port_clk); i++) { -+ if (i < 4) { -+ if (!svip_sys1_clk_is_enabled(port_clk[i])) -+ continue; -+ } else { -+ if (!svip_sys2_clk_is_enabled(port_clk[i])) -+ continue; -+ } -+ -+ PROC_PRINT("P%d.%-10s", i, "DIR:"); -+ -+ for (t = 31; t != -1; t--) -+ PROC_PRINT("%d", ltq_port_get_dir(i, t) == 1 ? 1 : 0); -+ PROC_PRINT("\n"); -+ -+ PROC_PRINT("P%d.%-10s", i, "PUEN:"); -+ for (t = 31; t != -1; t--) -+ PROC_PRINT("%d", ltq_port_get_puden(i, t) == 1 ? 1 : 0); -+ PROC_PRINT("\n"); -+ -+ PROC_PRINT("P%d.%-10s", i, "ALTSEL0:"); -+ for (t = 31; t != -1; t--) -+ PROC_PRINT("%d", -+ ltq_port_get_altsel0(i, t) == 1 ? 1 : 0); -+ PROC_PRINT("\n"); -+ -+ PROC_PRINT("P%d.%-10s", i, "ALTSEL1:"); -+ for (t = 31; t != -1; t--) -+ PROC_PRINT("%d", -+ ltq_port_get_altsel1(i, t) == 1 ? 1 : 0); -+ PROC_PRINT("\n\n"); -+ } -+ -+out: -+ if (len < 0) { -+ len = 0; -+ *eof = 1; -+ } else if (len < count) { -+ *eof = 1; -+ } else { -+ len = count; -+ } -+ -+ *start = buf; -+ -+ return len; -+} -+ -+static struct platform_driver ltq_mux_driver = { -+ .probe = ltq_mux_probe, -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+int __init ltq_mux_init(void) -+{ -+ int ret = platform_driver_register(<q_mux_driver); -+ if (ret) { -+ printk(KERN_INFO DRV_NAME -+ ": Error registering platform driver!"); -+ return ret; -+ } -+ -+ return create_proc_read_entry("driver/ltq_mux", 0, NULL, -+ ltq_mux_read_procmem, NULL) == NULL; -+} -+ -+module_init(ltq_mux_init); -Index: linux-3.3.8/arch/mips/lantiq/svip/pms.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/lantiq/svip/pms.c 2012-07-31 19:51:34.149105918 +0200 -@@ -0,0 +1,101 @@ -+/************************************************************************ -+ * -+ * Copyright (c) 2007 -+ * Infineon Technologies AG -+ * St. Martin Strasse 53; 81669 Muenchen; Germany -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ * -+ ************************************************************************/ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+ -+static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; -+static struct svip_reg_sys2 *const sys2 = (struct svip_reg_sys2 *)LTQ_SYS2_BASE; -+ -+void svip_sys1_clk_enable(u32 mask) -+{ -+ sys1_w32(sys1_r32(clksr) | mask, clkenr); -+ asm("sync;"); -+} -+EXPORT_SYMBOL(svip_sys1_clk_enable); -+ -+int svip_sys1_clk_is_enabled(u32 mask) -+{ -+ return (sys1_r32(clksr) & mask) != 0; -+} -+EXPORT_SYMBOL(svip_sys1_clk_is_enabled); -+ -+void svip_sys2_clk_enable(u32 mask) -+{ -+ sys2_w32(sys2_r32(clksr) | mask, clkenr); -+ asm("sync;"); -+} -+EXPORT_SYMBOL(svip_sys2_clk_enable); -+ -+int svip_sys2_clk_is_enabled(u32 mask) -+{ -+ return (sys2_r32(clksr) & mask) != 0; -+} -+EXPORT_SYMBOL(svip_sys2_clk_is_enabled); -+ -+int ltq_pms_read_procmem(char *buf, char **start, off_t offset, -+ int count, int *eof, void *data) -+{ -+ long len = 0; -+ int t = 0; -+ u32 bit = 0; -+ u32 reg_tmp, bits_tmp; -+ -+ len = sprintf(buf, "\nSVIP PMS Settings\n"); -+ len = len + sprintf(buf + len, -+ " 3 2 1 0\n"); -+ len = len + sprintf(buf + len, -+ " 210987654321098765432109876543210\n"); -+ len = len + sprintf(buf + len, -+ "---------------------------------------------\n"); -+ len = len + sprintf(buf + len, -+ "SYS1_CLKSR: "); -+ reg_tmp = sys1_r32(clksr); -+ bit = 0x80000000; -+ for (t = 31; t != -1; t--) { -+ bits_tmp = (reg_tmp & bit) >> t; -+ len = len + sprintf(buf + len, "%d", bits_tmp); -+ bit = bit >> 1; -+ } -+ len = len + sprintf(buf + len, "\n\n"); -+ len = len + sprintf(buf + len, "SYS2_CLKSR: "); -+ reg_tmp = sys2_r32(clksr); -+ bit = 0x80000000; -+ for (t = 31; t != -1; t--) { -+ bits_tmp = (reg_tmp & bit) >> t; -+ len = len + sprintf(buf + len, "%d", bits_tmp); -+ bit = bit >> 1; -+ } -+ len = len + sprintf(buf + len, "\n\n"); -+ -+ *eof = 1; -+ -+ return len; -+} -+ -+int __init ltq_pms_init_proc(void) -+{ -+ return create_proc_read_entry("driver/ltq_pms", 0, NULL, -+ ltq_pms_read_procmem, NULL) == NULL; -+} -+ -+module_init(ltq_pms_init_proc); -Index: linux-3.3.8/drivers/spi/spi_svip.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/drivers/spi/spi_svip.c 2012-07-31 19:51:34.149105918 +0200 -@@ -0,0 +1,955 @@ -+/************************************************************************ -+ * -+ * Copyright (c) 2008 -+ * Infineon Technologies AG -+ * St. Martin Strasse 53; 81669 Muenchen; Germany -+ * -+ * Inspired by Atmel AT32/AT91 SPI Controller driver -+ * Copyright (c) 2006 Atmel Corporation -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ * -+ ************************************************************************/ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+#define SFRAME_SIZE 512 /* bytes */ -+#define FIFO_HEADROOM 2 /* words */ -+ -+#define SVIP_SSC_RFIFO_WORDS 8 -+ -+enum svip_ssc_dir { -+ SSC_RXTX, -+ SSC_RX, -+ SSC_TX, -+ SSC_UNDEF -+}; -+ -+/* -+ * The core SPI transfer engine just talks to a register bank to set up -+ * DMA transfers; transfer queue progress is driven by IRQs. The clock -+ * framework provides the base clock, subdivided for each spi_device. -+ */ -+struct svip_ssc_device { -+ struct svip_reg_ssc *regs; -+ enum svip_ssc_dir bus_dir; -+ struct spi_device *stay; -+ -+ u8 stopping; -+ struct list_head queue; -+ struct spi_transfer *current_transfer; -+ int remaining_bytes; -+ int rx_bytes; -+ int tx_bytes; -+ -+ char intname[4][16]; -+ -+ spinlock_t lock; -+}; -+ -+static int svip_ssc_setup(struct spi_device *spi); -+ -+extern unsigned int ltq_get_fbs0_hz(void); -+ -+static void cs_activate(struct svip_ssc_device *ssc_dev, struct spi_device *spi) -+{ -+ ssc_dev->regs->whbgpostat = 0x0001 << spi->chip_select; /* activate the chip select */ -+} -+ -+static void cs_deactivate(struct svip_ssc_device *ssc_dev, struct spi_device *spi) -+{ -+ ssc_dev->regs->whbgpostat = 0x0100 << spi->chip_select; /* deactivate the chip select */ -+} -+ -+/* -+ * "Normally" returns Byte Valid = 4. -+ * If the unaligned remainder of the packet is 3 bytes, these have to be -+ * transferred as a combination of a 16-bit and a 8-bit FPI transfer. For -+ * 2 or 1 remaining bytes a single 16-bit or 8-bit transfer will do. -+ */ -+static int inline _estimate_bv(int byte_pos, int bytelen) -+{ -+ int remainder = bytelen % 4; -+ -+ if (byte_pos < (bytelen - remainder)) -+ return 4; -+ -+ if (remainder == 3) -+ { -+ if (byte_pos == (bytelen - remainder)) -+ return 2; -+ else -+ return 1; -+ } -+ return remainder; -+} -+ -+/* -+ * Submit next transfer. -+ * lock is held, spi irq is blocked -+ */ -+static void svip_ssc_next_xfer(struct spi_master *master, -+ struct spi_message *msg) -+{ -+ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); -+ struct spi_transfer *xfer; -+ unsigned char *buf_ptr; -+ -+ xfer = ssc_dev->current_transfer; -+ if (!xfer || ssc_dev->remaining_bytes == 0) { -+ if (xfer) -+ xfer = list_entry(xfer->transfer_list.next, -+ struct spi_transfer, transfer_list); -+ else -+ xfer = list_entry(msg->transfers.next, -+ struct spi_transfer, transfer_list); -+ ssc_dev->remaining_bytes = xfer->len; -+ ssc_dev->rx_bytes = 0; -+ ssc_dev->tx_bytes = 0; -+ ssc_dev->current_transfer = xfer; -+ ssc_dev->regs->sfcon = 0; /* reset Serial Framing */ -+ -+ /* enable and flush RX/TX FIFO */ -+ ssc_dev->regs->rxfcon = -+ SSC_RXFCON_RXFITL_VAL(SVIP_SSC_RFIFO_WORDS-FIFO_HEADROOM) | -+ SSC_RXFCON_RXFLU | /* Receive FIFO Flush */ -+ SSC_RXFCON_RXFEN; /* Receive FIFO Enable */ -+ -+ ssc_dev->regs->txfcon = -+ SSC_TXFCON_TXFITL_VAL(FIFO_HEADROOM) | -+ SSC_TXFCON_TXFLU | /* Transmit FIFO Flush */ -+ SSC_TXFCON_TXFEN; /* Transmit FIFO Enable */ -+ -+ asm("sync"); -+ -+ /* select mode RXTX, RX or TX */ -+ if (xfer->rx_buf && xfer->tx_buf) /* RX and TX */ -+ { -+ if (ssc_dev->bus_dir != SSC_RXTX) -+ { -+ ssc_dev->regs->mcon &= ~(SSC_MCON_RXOFF | SSC_MCON_TXOFF); -+ ssc_dev->bus_dir = SSC_RXTX; -+ ssc_dev->regs->irnen = SSC_IRNEN_T | SSC_IRNEN_F | SSC_IRNEN_E; -+ } -+ ssc_dev->regs->sfcon = -+ SSC_SFCON_PLEN_VAL(0) | -+ SSC_SFCON_DLEN_VAL(((xfer->len-1)%SFRAME_SIZE)*8+7) | -+ SSC_SFCON_STOP | -+ SSC_SFCON_ICLK_VAL(2) | -+ SSC_SFCON_IDAT_VAL(2) | -+ SSC_SFCON_IAEN | -+ SSC_SFCON_SFEN; -+ -+ } -+ else if (xfer->rx_buf) /* RX only */ -+ { -+ if (ssc_dev->bus_dir != SSC_RX) -+ { -+ ssc_dev->regs->mcon = -+ (ssc_dev->regs->mcon | SSC_MCON_TXOFF) & ~SSC_MCON_RXOFF; -+ -+ ssc_dev->bus_dir = SSC_RX; -+ -+ ssc_dev->regs->irnen = SSC_IRNEN_R | SSC_IRNEN_E; -+ } -+ /* Initiate clock generation for Rx-Only Transfer. In case of RX-only transfer, -+ * rx_bytes represents the number of already requested bytes. -+ */ -+ ssc_dev->rx_bytes = min(xfer->len, (unsigned)(SVIP_SSC_RFIFO_WORDS*4)); -+ ssc_dev->regs->rxreq = ssc_dev->rx_bytes; -+ } -+ else /* TX only */ -+ { -+ if (ssc_dev->bus_dir != SSC_TX) -+ { -+ ssc_dev->regs->mcon = -+ (ssc_dev->regs->mcon | SSC_MCON_RXOFF) & ~SSC_MCON_TXOFF; -+ -+ ssc_dev->bus_dir = SSC_TX; -+ -+ ssc_dev->regs->irnen = -+ SSC_IRNEN_T | SSC_IRNEN_F | SSC_IRNEN_E; -+ } -+ ssc_dev->regs->sfcon = -+ SSC_SFCON_PLEN_VAL(0) | -+ SSC_SFCON_DLEN_VAL(((xfer->len-1)%SFRAME_SIZE)*8+7) | -+ SSC_SFCON_STOP | -+ SSC_SFCON_ICLK_VAL(2) | -+ SSC_SFCON_IDAT_VAL(2) | -+ SSC_SFCON_IAEN | -+ SSC_SFCON_SFEN; -+ } -+ } -+ -+ if (xfer->tx_buf) -+ { -+ int outstanding; -+ int i; -+ int fstat = ssc_dev->regs->fstat; -+ int txffl = SSC_FSTAT_TXFFL_GET(fstat); -+ int rxffl = SSC_FSTAT_RXFFL_GET(fstat); -+ -+ outstanding = txffl; -+ -+ if (xfer->rx_buf) -+ { -+ outstanding += rxffl; -+ if (SSC_STATE_BSY_GET(ssc_dev->regs->state)) -+ outstanding++; -+ -+ while (rxffl) /* is 0 in TX-Only mode */ -+ { -+ unsigned int rb; -+ int rxbv = _estimate_bv(ssc_dev->rx_bytes, xfer->len); -+ rb = ssc_dev->regs->rb; -+ for (i=0; irx_buf)[ssc_dev->rx_bytes] = -+ (rb >> ((rxbv-i-1)*8)) & 0xFF; -+ -+ ssc_dev->rx_bytes++; -+ } -+ rxffl--; -+ outstanding--; -+ } -+ ssc_dev->remaining_bytes = xfer->len - ssc_dev->rx_bytes; -+ } -+ -+ /* for last Tx cycle set TxFifo threshold to 0 */ -+ if ((xfer->len - ssc_dev->tx_bytes) <= -+ (4*(SVIP_SSC_RFIFO_WORDS-1-outstanding))) -+ { -+ ssc_dev->regs->txfcon = SSC_TXFCON_TXFITL_VAL(0) | -+ SSC_TXFCON_TXFEN; -+ } -+ -+ while ((ssc_dev->tx_bytes < xfer->len) && -+ (outstanding < (SVIP_SSC_RFIFO_WORDS-1))) -+ { -+ unsigned int tb = 0; -+ int txbv = _estimate_bv(ssc_dev->tx_bytes, xfer->len); -+ -+ for (i=0; itx_buf)[ssc_dev->tx_bytes] << -+ ((txbv-i-1)*8); -+ -+ ssc_dev->tx_bytes++; -+ } -+ switch(txbv) -+ { -+#ifdef __BIG_ENDIAN -+ case 1: -+ *((unsigned char *)(&(ssc_dev->regs->tb))+3) = tb & 0xFF; -+ break; -+ case 2: -+ *((unsigned short *)(&(ssc_dev->regs->tb))+1) = tb & 0xFFFF; -+ break; -+#else /* __LITTLE_ENDIAN */ -+ case 1: -+ *((unsigned char *)(&(ssc_dev->regs->tb))) = tb & 0xFF; -+ break; -+ case 2: -+ *((unsigned short *)(&(ssc_dev->regs->tb))) = tb & 0xFFFF; -+ break; -+#endif -+ default: -+ ssc_dev->regs->tb = tb; -+ } -+ outstanding++; -+ } -+ } -+ else /* xfer->tx_buf == NULL -> RX only! */ -+ { -+ int j; -+ int rxffl = SSC_FSTAT_RXFFL_GET(ssc_dev->regs->fstat); -+ int rxbv = 0; -+ unsigned int rbuf; -+ -+ buf_ptr = (unsigned char*)xfer->rx_buf + -+ (xfer->len - ssc_dev->remaining_bytes); -+ -+ for (j = 0; j < rxffl; j++) -+ { -+ rxbv = SSC_STATE_RXBV_GET(ssc_dev->regs->state); -+ rbuf = ssc_dev->regs->rb; -+ -+ if (rxbv == 4) -+ { -+ *((unsigned int*)buf_ptr+j) = ntohl(rbuf); -+ } -+ else -+ { -+ int b; -+#ifdef __BIG_ENDIAN -+ for (b = 0; b < rxbv; b++) -+ { -+ buf_ptr[4*j+b] = ((unsigned char*)(&rbuf))[4-rxbv+b]; -+ } -+#else /* __LITTLE_ENDIAN */ -+ for (b = 0; b < rxbv; b++) -+ { -+ buf_ptr[4*j+b] = ((unsigned char*)(&rbuf))[rxbv-1-b]; -+ } -+#endif -+ } -+ ssc_dev->remaining_bytes -= rxbv; -+ } -+ if ((ssc_dev->rx_bytes < xfer->len) && -+ !SSC_STATE_BSY_GET(ssc_dev->regs->state)) -+ { -+ int rxreq = min(xfer->len - ssc_dev->rx_bytes, -+ (unsigned)(SVIP_SSC_RFIFO_WORDS*4)); -+ -+ ssc_dev->rx_bytes += rxreq; -+ ssc_dev->regs->rxreq = rxreq; -+ } -+ -+ if (ssc_dev->remaining_bytes < 0) -+ { -+ printk("ssc_dev->remaining_bytes = %d! xfer->len = %d, " -+ "rxffl=%d, rxbv=%d\n", ssc_dev->remaining_bytes, xfer->len, -+ rxffl, rxbv); -+ -+ ssc_dev->remaining_bytes = 0; -+ } -+ } -+} -+ -+/* -+ * Submit next message. -+ * lock is held -+ */ -+static void svip_ssc_next_message(struct spi_master *master) -+{ -+ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); -+ struct spi_message *msg; -+ struct spi_device *spi; -+ -+ BUG_ON(ssc_dev->current_transfer); -+ -+ msg = list_entry(ssc_dev->queue.next, struct spi_message, queue); -+ spi = msg->spi; -+ -+ dev_dbg(master->dev.parent, "start message %p on %p\n", msg, spi); -+ -+ /* select chip if it's not still active */ -+ if (ssc_dev->stay) { -+ if (ssc_dev->stay != spi) { -+ cs_deactivate(ssc_dev, ssc_dev->stay); -+ svip_ssc_setup(spi); -+ cs_activate(ssc_dev, spi); -+ } -+ ssc_dev->stay = NULL; -+ } -+ else { -+ svip_ssc_setup(spi); -+ cs_activate(ssc_dev, spi); -+ } -+ -+ svip_ssc_next_xfer(master, msg); -+} -+ -+/* -+ * Report message completion. -+ * lock is held -+ */ -+static void -+svip_ssc_msg_done(struct spi_master *master, struct svip_ssc_device *ssc_dev, -+ struct spi_message *msg, int status, int stay) -+{ -+ if (!stay || status < 0) -+ cs_deactivate(ssc_dev, msg->spi); -+ else -+ ssc_dev->stay = msg->spi; -+ -+ list_del(&msg->queue); -+ msg->status = status; -+ -+ dev_dbg(master->dev.parent, -+ "xfer complete: %u bytes transferred\n", -+ msg->actual_length); -+ -+ spin_unlock(&ssc_dev->lock); -+ msg->complete(msg->context); -+ spin_lock(&ssc_dev->lock); -+ -+ ssc_dev->current_transfer = NULL; -+ -+ /* continue if needed */ -+ if (list_empty(&ssc_dev->queue) || ssc_dev->stopping) -+ ; /* TODO: disable hardware */ -+ else -+ svip_ssc_next_message(master); -+} -+ -+static irqreturn_t svip_ssc_eir_handler(int irq, void *dev_id) -+{ -+ struct platform_device *pdev = (struct platform_device*)dev_id; -+ struct spi_master *master = platform_get_drvdata(pdev); -+ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); -+ -+ dev_err (&pdev->dev, "ERROR: errirq. STATE = 0x%0lx\n", -+ ssc_dev->regs->state); -+ return IRQ_HANDLED; -+} -+ -+static irqreturn_t svip_ssc_rir_handler(int irq, void *dev_id) -+{ -+ struct platform_device *pdev = (struct platform_device*)dev_id; -+ struct spi_master *master = platform_get_drvdata(pdev); -+ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); -+ struct spi_message *msg; -+ struct spi_transfer *xfer; -+ -+ xfer = ssc_dev->current_transfer; -+ msg = list_entry(ssc_dev->queue.next, struct spi_message, queue); -+ -+ /* Tx and Rx Interrupts are fairly unpredictable. Just leave interrupt -+ * handler for spurious Interrupts! -+ */ -+ if (!xfer) { -+ dev_dbg(master->dev.parent, -+ "%s(%d): xfer = NULL\n", __FUNCTION__, irq); -+ goto out; -+ } -+ if ( !(xfer->rx_buf) ) { -+ dev_dbg(master->dev.parent, -+ "%s(%d): xfer->rx_buf = NULL\n", __FUNCTION__, irq); -+ goto out; -+ } -+ if (ssc_dev->remaining_bytes > 0) -+ { -+ /* -+ * Keep going, we still have data to send in -+ * the current transfer. -+ */ -+ svip_ssc_next_xfer(master, msg); -+ } -+ -+ if (ssc_dev->remaining_bytes == 0) -+ { -+ msg->actual_length += xfer->len; -+ -+ if (msg->transfers.prev == &xfer->transfer_list) { -+ /* report completed message */ -+ svip_ssc_msg_done(master, ssc_dev, msg, 0, -+ xfer->cs_change); -+ } -+ else { -+ if (xfer->cs_change) { -+ cs_deactivate(ssc_dev, msg->spi); -+ udelay(1); /* not nice in interrupt context */ -+ cs_activate(ssc_dev, msg->spi); -+ } -+ -+ /* Not done yet. Submit the next transfer. */ -+ svip_ssc_next_xfer(master, msg); -+ } -+ } -+out: -+ return IRQ_HANDLED; -+} -+ -+static irqreturn_t svip_ssc_tir_handler(int irq, void *dev_id) -+{ -+ struct platform_device *pdev = (struct platform_device*)dev_id; -+ struct spi_master *master = platform_get_drvdata(pdev); -+ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); -+ struct spi_message *msg; -+ struct spi_transfer *xfer; -+ int tx_remain; -+ -+ xfer = ssc_dev->current_transfer; -+ msg = list_entry(ssc_dev->queue.next, struct spi_message, queue); -+ -+ /* Tx and Rx Interrupts are fairly unpredictable. Just leave interrupt -+ * handler for spurious Interrupts! -+ */ -+ if (!xfer) { -+ dev_dbg(master->dev.parent, -+ "%s(%d): xfer = NULL\n", __FUNCTION__, irq); -+ goto out; -+ } -+ if ( !(xfer->tx_buf) ) { -+ dev_dbg(master->dev.parent, -+ "%s(%d): xfer->tx_buf = NULL\n", __FUNCTION__, irq); -+ goto out; -+ } -+ -+ if (ssc_dev->remaining_bytes > 0) -+ { -+ tx_remain = xfer->len - ssc_dev->tx_bytes; -+ if ( tx_remain == 0 ) -+ { -+ dev_dbg(master->dev.parent, -+ "%s(%d): tx_remain = 0\n", __FUNCTION__, irq); -+ } -+ else -+ /* -+ * Keep going, we still have data to send in -+ * the current transfer. -+ */ -+ svip_ssc_next_xfer(master, msg); -+ } -+out: -+ return IRQ_HANDLED; -+} -+ -+static irqreturn_t svip_ssc_fir_handler(int irq, void *dev_id) -+{ -+ struct platform_device *pdev = (struct platform_device*)dev_id; -+ struct spi_master *master = platform_get_drvdata(pdev); -+ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); -+ struct spi_message *msg; -+ struct spi_transfer *xfer; -+ -+ xfer = ssc_dev->current_transfer; -+ msg = list_entry(ssc_dev->queue.next, struct spi_message, queue); -+ -+ /* Tx and Rx Interrupts are fairly unpredictable. Just leave interrupt -+ * handler for spurious Interrupts! -+ */ -+ if (!xfer) { -+ dev_dbg(master->dev.parent, -+ "%s(%d): xfer = NULL\n", __FUNCTION__, irq); -+ goto out; -+ } -+ if ( !(xfer->tx_buf) ) { -+ dev_dbg(master->dev.parent, -+ "%s(%d): xfer->tx_buf = NULL\n", __FUNCTION__, irq); -+ goto out; -+ } -+ -+ if (ssc_dev->remaining_bytes > 0) -+ { -+ int tx_remain = xfer->len - ssc_dev->tx_bytes; -+ -+ if (tx_remain == 0) -+ { -+ /* Frame interrupt gets raised _before_ last Rx interrupt */ -+ if (xfer->rx_buf) -+ { -+ svip_ssc_next_xfer(master, msg); -+ if (ssc_dev->remaining_bytes) -+ printk("expected RXTX transfer to be complete!\n"); -+ } -+ ssc_dev->remaining_bytes = 0; -+ } -+ else -+ { -+ ssc_dev->regs->sfcon = SSC_SFCON_PLEN_VAL(0) | -+ SSC_SFCON_DLEN_VAL(SFRAME_SIZE*8-1) | -+ SSC_SFCON_STOP | -+ SSC_SFCON_ICLK_VAL(2) | -+ SSC_SFCON_IDAT_VAL(2) | -+ SSC_SFCON_IAEN | -+ SSC_SFCON_SFEN; -+ } -+ } -+ -+ if (ssc_dev->remaining_bytes == 0) -+ { -+ msg->actual_length += xfer->len; -+ -+ if (msg->transfers.prev == &xfer->transfer_list) { -+ /* report completed message */ -+ svip_ssc_msg_done(master, ssc_dev, msg, 0, -+ xfer->cs_change); -+ } -+ else { -+ if (xfer->cs_change) { -+ cs_deactivate(ssc_dev, msg->spi); -+ udelay(1); /* not nice in interrupt context */ -+ cs_activate(ssc_dev, msg->spi); -+ } -+ -+ /* Not done yet. Submit the next transfer. */ -+ svip_ssc_next_xfer(master, msg); -+ } -+ } -+ -+out: -+ return IRQ_HANDLED; -+} -+ -+/* the spi->mode bits understood by this driver: */ -+#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP) -+ -+static int svip_ssc_setup(struct spi_device *spi) -+{ -+ struct spi_master *master = spi->master; -+ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); -+ unsigned int bits = spi->bits_per_word; -+ unsigned int br, sck_hz = spi->max_speed_hz; -+ unsigned long flags; -+ -+ if (ssc_dev->stopping) -+ return -ESHUTDOWN; -+ -+ if (spi->chip_select >= master->num_chipselect) { -+ dev_dbg(&spi->dev, -+ "setup: invalid chipselect %u (%u defined)\n", -+ spi->chip_select, master->num_chipselect); -+ return -EINVAL; -+ } -+ -+ if (bits == 0) -+ bits = 8; -+ if (bits != 8) { -+ dev_dbg(&spi->dev, -+ "setup: invalid bits_per_word %u (expect 8)\n", -+ bits); -+ return -EINVAL; -+ } -+ -+ if (spi->mode & ~MODEBITS) { -+ dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", -+ spi->mode & ~MODEBITS); -+ return -EINVAL; -+ } -+ -+ /* Disable SSC */ -+ ssc_dev->regs->whbstate = SSC_WHBSTATE_CLREN; -+ -+ if (sck_hz == 0) -+ sck_hz = 10000; -+ -+ br = ltq_get_fbs0_hz()/(2 *sck_hz); -+ if (ltq_get_fbs0_hz()%(2 *sck_hz) == 0) -+ br = br -1; -+ ssc_dev->regs->br = br; -+ -+ /* set Control Register */ -+ ssc_dev->regs->mcon = SSC_MCON_ENBV | -+ SSC_MCON_RUEN | -+ SSC_MCON_TUEN | -+ SSC_MCON_AEN | -+ SSC_MCON_REN | -+ SSC_MCON_TEN | -+ (spi->mode & SPI_CPOL ? SSC_MCON_PO : 0) | /* Clock Polarity */ -+ (spi->mode & SPI_CPHA ? 0 : SSC_MCON_PH) | /* Tx on trailing edge */ -+ (spi->mode & SPI_LOOP ? SSC_MCON_LB : 0) | /* Loopback */ -+ (spi->mode & SPI_LSB_FIRST ? 0 : SSC_MCON_HB); /* MSB first */ -+ ssc_dev->bus_dir = SSC_UNDEF; -+ -+ /* Enable SSC */ -+ ssc_dev->regs->whbstate = SSC_WHBSTATE_SETEN; -+ asm("sync"); -+ -+ spin_lock_irqsave(&ssc_dev->lock, flags); -+ if (ssc_dev->stay == spi) -+ ssc_dev->stay = NULL; -+ cs_deactivate(ssc_dev, spi); -+ spin_unlock_irqrestore(&ssc_dev->lock, flags); -+ -+ dev_dbg(&spi->dev, -+ "setup: %u Hz bpw %u mode 0x%02x cs %u\n", -+ sck_hz, bits, spi->mode, spi->chip_select); -+ -+ return 0; -+} -+ -+static int svip_ssc_transfer(struct spi_device *spi, struct spi_message *msg) -+{ -+ struct spi_master *master = spi->master; -+ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); -+ struct spi_transfer *xfer; -+ unsigned long flags; -+ -+ dev_dbg(&spi->dev, "new message %p submitted\n", msg); -+ -+ if (unlikely(list_empty(&msg->transfers) -+ || !spi->max_speed_hz)) { -+ return -EINVAL; -+ } -+ -+ if (ssc_dev->stopping) -+ return -ESHUTDOWN; -+ -+ list_for_each_entry(xfer, &msg->transfers, transfer_list) { -+ if (!(xfer->tx_buf || xfer->rx_buf) || (xfer->len == 0)) { -+ dev_dbg(&spi->dev, "missing rx or tx buf\n"); -+ return -EINVAL; -+ } -+ -+ /* FIXME implement these protocol options!! */ -+ if (xfer->bits_per_word || xfer->speed_hz) { -+ dev_dbg(&spi->dev, "no protocol options yet\n"); -+ return -ENOPROTOOPT; -+ } -+ -+#ifdef VERBOSE -+ dev_dbg(spi->dev, -+ " xfer %p: len %u tx %p/%08x rx %p/%08x\n", -+ xfer, xfer->len, -+ xfer->tx_buf, xfer->tx_dma, -+ xfer->rx_buf, xfer->rx_dma); -+#endif -+ } -+ -+ msg->status = -EINPROGRESS; -+ msg->actual_length = 0; -+ -+ spin_lock_irqsave(&ssc_dev->lock, flags); -+ list_add_tail(&msg->queue, &ssc_dev->queue); -+ if (!ssc_dev->current_transfer) -+ { -+ /* start transmission machine, if not started yet */ -+ svip_ssc_next_message(master); -+ } -+ spin_unlock_irqrestore(&ssc_dev->lock, flags); -+ -+ return 0; -+} -+ -+static void svip_ssc_cleanup(struct spi_device *spi) -+{ -+ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(spi->master); -+ unsigned long flags; -+ -+ if (!spi->controller_state) -+ return; -+ -+ spin_lock_irqsave(&ssc_dev->lock, flags); -+ if (ssc_dev->stay == spi) { -+ ssc_dev->stay = NULL; -+ cs_deactivate(ssc_dev, spi); -+ } -+ spin_unlock_irqrestore(&ssc_dev->lock, flags); -+} -+ -+/*-------------------------------------------------------------------------*/ -+ -+static int __init svip_ssc_probe(struct platform_device *pdev) -+{ -+ int ret; -+ struct spi_master *master; -+ struct svip_ssc_device *ssc_dev; -+ struct resource *res_regs; -+ int irq; -+ -+ ret = -ENOMEM; -+ -+ /* setup spi core then atmel-specific driver state */ -+ master = spi_alloc_master(&pdev->dev, sizeof (*ssc_dev)); -+ if (!master) -+ { -+ dev_err (&pdev->dev, "ERROR: no memory for master spi\n"); -+ goto errout; -+ } -+ -+ ssc_dev = spi_master_get_devdata(master); -+ platform_set_drvdata(pdev, master); -+ -+ master->bus_num = pdev->id; -+ master->num_chipselect = 8; -+ master->mode_bits = MODEBITS; -+ master->setup = svip_ssc_setup; -+ master->transfer = svip_ssc_transfer; -+ master->cleanup = svip_ssc_cleanup; -+ -+ spin_lock_init(&ssc_dev->lock); -+ INIT_LIST_HEAD(&ssc_dev->queue); -+ -+ /* retrive register configration */ -+ res_regs = platform_get_resource_byname (pdev, IORESOURCE_MEM, "regs"); -+ if (NULL == res_regs) -+ { -+ dev_err (&pdev->dev, "ERROR: missed 'regs' resource\n"); -+ goto spierr; -+ } -+ -+ ssc_dev->regs = (struct svip_reg_ssc*)KSEG1ADDR(res_regs->start); -+ -+ irq = platform_get_irq_byname (pdev, "tx"); -+ if (irq < 0) -+ goto irqerr; -+ sprintf(ssc_dev->intname[0], "%s_tx", pdev->name); -+ ret = devm_request_irq(&pdev->dev, irq, svip_ssc_tir_handler, -+ IRQF_DISABLED, ssc_dev->intname[0], pdev); -+ if (ret != 0) -+ goto irqerr; -+ -+ irq = platform_get_irq_byname (pdev, "rx"); -+ if (irq < 0) -+ goto irqerr; -+ sprintf(ssc_dev->intname[1], "%s_rx", pdev->name); -+ ret = devm_request_irq(&pdev->dev, irq, svip_ssc_rir_handler, -+ IRQF_DISABLED, ssc_dev->intname[1], pdev); -+ if (ret != 0) -+ goto irqerr; -+ -+ irq = platform_get_irq_byname (pdev, "err"); -+ if (irq < 0) -+ goto irqerr; -+ sprintf(ssc_dev->intname[2], "%s_err", pdev->name); -+ ret = devm_request_irq(&pdev->dev, irq, svip_ssc_eir_handler, -+ IRQF_DISABLED, ssc_dev->intname[2], pdev); -+ if (ret != 0) -+ goto irqerr; -+ -+ irq = platform_get_irq_byname (pdev, "frm"); -+ if (irq < 0) -+ goto irqerr; -+ sprintf(ssc_dev->intname[3], "%s_frm", pdev->name); -+ ret = devm_request_irq(&pdev->dev, irq, svip_ssc_fir_handler, -+ IRQF_DISABLED, ssc_dev->intname[3], pdev); -+ if (ret != 0) -+ goto irqerr; -+ -+ /* -+ * Initialize the Hardware -+ */ -+ -+ /* Clear enable bit, i.e. put SSC into configuration mode */ -+ ssc_dev->regs->whbstate = SSC_WHBSTATE_CLREN; -+ /* enable SSC core to run at fpi clock */ -+ ssc_dev->regs->clc = SSC_CLC_RMC_VAL(1); -+ asm("sync"); -+ -+ /* GPIO CS */ -+ ssc_dev->regs->gpocon = SSC_GPOCON_ISCSBN_VAL(0xFF); -+ ssc_dev->regs->whbgpostat = SSC_WHBGPOSTAT_SETOUTN_VAL(0xFF); /* CS to high */ -+ -+ /* Set Master mode */ -+ ssc_dev->regs->whbstate = SSC_WHBSTATE_SETMS; -+ -+ /* enable and flush RX/TX FIFO */ -+ ssc_dev->regs->rxfcon = SSC_RXFCON_RXFITL_VAL(SVIP_SSC_RFIFO_WORDS-FIFO_HEADROOM) | -+ SSC_RXFCON_RXFLU | /* Receive FIFO Flush */ -+ SSC_RXFCON_RXFEN; /* Receive FIFO Enable */ -+ -+ ssc_dev->regs->txfcon = SSC_TXFCON_TXFITL_VAL(FIFO_HEADROOM) | -+ SSC_TXFCON_TXFLU | /* Transmit FIFO Flush */ -+ SSC_TXFCON_TXFEN; /* Transmit FIFO Enable */ -+ asm("sync"); -+ -+ /* enable IRQ */ -+ ssc_dev->regs->irnen = SSC_IRNEN_E; -+ -+ dev_info(&pdev->dev, "controller at 0x%08lx (irq %d)\n", -+ (unsigned long)ssc_dev->regs, platform_get_irq_byname (pdev, "rx")); -+ -+ ret = spi_register_master(master); -+ if (ret) -+ goto out_reset_hw; -+ -+ return 0; -+ -+out_reset_hw: -+ -+irqerr: -+ devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "tx"), pdev); -+ devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "rx"), pdev); -+ devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "err"), pdev); -+ devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "frm"), pdev); -+ -+spierr: -+ -+ spi_master_put(master); -+ -+errout: -+ return ret; -+} -+ -+static int __exit svip_ssc_remove(struct platform_device *pdev) -+{ -+ struct spi_master *master = platform_get_drvdata(pdev); -+ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); -+ struct spi_message *msg; -+ -+ /* reset the hardware and block queue progress */ -+ spin_lock_irq(&ssc_dev->lock); -+ ssc_dev->stopping = 1; -+ /* TODO: shutdown hardware */ -+ spin_unlock_irq(&ssc_dev->lock); -+ -+ /* Terminate remaining queued transfers */ -+ list_for_each_entry(msg, &ssc_dev->queue, queue) { -+ /* REVISIT unmapping the dma is a NOP on ARM and AVR32 -+ * but we shouldn't depend on that... -+ */ -+ msg->status = -ESHUTDOWN; -+ msg->complete(msg->context); -+ } -+ -+ devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "tx"), pdev); -+ devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "rx"), pdev); -+ devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "err"), pdev); -+ devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "frm"), pdev); -+ -+ spi_unregister_master(master); -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(master); -+ return 0; -+} -+ -+#ifdef CONFIG_PM -+static int svip_ssc_suspend(struct platform_device *pdev, pm_message_t mesg) -+{ -+ struct spi_master *master = platform_get_drvdata(pdev); -+ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); -+ -+ clk_disable(ssc_dev->clk); -+ return 0; -+} -+ -+static int svip_ssc_resume(struct platform_device *pdev) -+{ -+ struct spi_master *master = platform_get_drvdata(pdev); -+ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); -+ -+ clk_enable(ssc_dev->clk); -+ return 0; -+} -+#endif -+ -+static struct platform_driver svip_ssc_driver = { -+ .driver = { -+ .name = "ifx_ssc", -+ .owner = THIS_MODULE, -+ }, -+ .probe = svip_ssc_probe, -+#ifdef CONFIG_PM -+ .suspend = svip_ssc_suspend, -+ .resume = svip_ssc_resume, -+#endif -+ .remove = __exit_p(svip_ssc_remove) -+}; -+ -+int __init svip_ssc_init(void) -+{ -+ return platform_driver_register(&svip_ssc_driver); -+} -+ -+void __exit svip_ssc_exit(void) -+{ -+ platform_driver_unregister(&svip_ssc_driver); -+} -+ -+module_init(svip_ssc_init); -+module_exit(svip_ssc_exit); -+ -+MODULE_ALIAS("platform:ifx_ssc"); -+MODULE_DESCRIPTION("Lantiq SSC Controller driver"); -+MODULE_AUTHOR("Andreas Schmidt "); -+MODULE_AUTHOR("Jevgenijs Grigorjevs "); -+MODULE_LICENSE("GPL"); -Index: linux-3.3.8/net/ipv4/svip_nat.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/net/ipv4/svip_nat.c 2012-07-31 20:04:32.985139213 +0200 -@@ -0,0 +1,1569 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2009 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 81726 Munich, Germany -+ -+ THE DELIVERY OF THIS SOFTWARE AS WELL AS THE HEREBY GRANTED NON-EXCLUSIVE, -+ WORLDWIDE LICENSE TO USE, COPY, MODIFY, DISTRIBUTE AND SUBLICENSE THIS -+ SOFTWARE IS FREE OF CHARGE. -+ -+ THE LICENSED SOFTWARE IS PROVIDED "AS IS" AND INFINEON EXPRESSLY DISCLAIMS -+ ALL REPRESENTATIONS AND WARRANTIES, WHETHER EXPRESS OR IMPLIED, INCLUDING -+ WITHOUT LIMITATION, WARRANTIES OR REPRESENTATIONS OF WORKMANSHIP, -+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, DURABILITY, THAT THE -+ OPERATING OF THE LICENSED SOFTWARE WILL BE ERROR FREE OR FREE OF ANY THIRD -+ PARTY CLAIMS, INCLUDING WITHOUT LIMITATION CLAIMS OF THIRD PARTY INTELLECTUAL -+ PROPERTY INFRINGEMENT. -+ -+ EXCEPT FOR ANY LIABILITY DUE TO WILFUL ACTS OR GROSS NEGLIGENCE AND EXCEPT -+ FOR ANY PERSONAL INJURY INFINEON SHALL IN NO EVENT BE LIABLE FOR ANY CLAIM -+ OR DAMAGES OF ANY KIND, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, -+ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER -+ DEALINGS IN THE SOFTWARE. -+ -+ **************************************************************************** -+ -+Description : This file contains implementation of Custom NAT function -+for Infineon's VINETIC-SVIP16 -+ *******************************************************************************/ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include /* just to shut up a warning */ -+#include -+#include -+ -+#include -+ -+MODULE_AUTHOR("Lantiq Deutschland GmbH"); -+MODULE_DESCRIPTION("SVIP Network Address Translation module"); -+MODULE_LICENSE("GPL"); -+ -+#define SVIP_NAT_INFO_STR "@(#)SVIP NAT, version "SVIP_NAT_VERSION -+ -+/** maximum voice packet channels possible on the SVIP LC system -+ (equals maximum number of Codec channels possible) */ -+#define SVIP_SYS_CODEC_NUM ((SVIP_SYS_NUM) * (SVIP_CODEC_NUM)) -+ -+/** end UDP port number of the SVIP Linecard System */ -+#define SVIP_UDP_TO ((SVIP_UDP_FROM) + (SVIP_SYS_CODEC_NUM) - 1) -+ -+/** end UDP port number of the Master SVIP in SVIP Linecard System */ -+#define SVIP_UDP_TO_VOFW0 ((SVIP_UDP_FROM) + (SVIP_CODEC_NUM) - 1) -+ -+#define SVIP_PORT_INRANGE(nPort) \ -+ ((nPort) >= (SVIP_UDP_FROM) && (nPort) <= (SVIP_UDP_TO)) -+ -+#define SVIP_PORT_INDEX(nPort) (nPort - SVIP_UDP_FROM) -+ -+#define SVIP_NET_DEV_ETH0_IDX 0 -+#define SVIP_NET_DEV_VETH0_IDX 1 -+#define SVIP_NET_DEV_LO_IDX 2 -+ -+#define SVIP_NET_DEV_ETH0_NAME "eth0" -+#define SVIP_NET_DEV_ETH1_NAME "eth1" -+#define SVIP_NET_DEV_VETH1_NAME "veth0" -+#define SVIP_NET_DEV_LO_NAME "lo" -+ -+#define SVIP_NAT_STATS_LOC2REM 0 -+#define SVIP_NAT_STATS_REM2LOC 1 -+#define SVIP_NAT_STATS_TYPES 2 -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) -+#define SVIP_NAT_FOR_EACH_NETDEV(d) for_each_netdev(&init_net, dev) -+#define SVIP_NAT_IP_HDR(ethhdr) ip_hdr(ethhdr) -+#else -+#define SVIP_NAT_FOR_EACH_NETDEV(d) for(d=dev_base; dev; dev = dev->next) -+#define SVIP_NAT_IP_HDR(ethhdr) (ethhdr)->nh.iph -+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) */ -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+#define SVIP_NAT_SKB_MAC_HEADER(ethhdr) (ethhdr)->mac.ethernet -+#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) -+#define SVIP_NAT_SKB_MAC_HEADER(ethhdr) (ethhdr)->mac.raw -+#else -+#define SVIP_NAT_SKB_MAC_HEADER(ethhdr) skb_mac_header(ethhdr) -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) -+#define VLAN_DEV_REAL_DEV(dev) vlan_dev_real_dev(dev) -+#define VLAN_DEV_VLAN_ID(dev) vlan_dev_vlan_id(dev) -+#else -+#define VLAN_DEV_REAL_DEV(dev) (VLAN_DEV_INFO(dev)->real_dev) -+#define VLAN_DEV_VLAN_ID(dev) (VLAN_DEV_INFO(dev)->vlan_id) -+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) */ -+ -+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) -+#define MOD_INC_USE_COUNT -+#define MOD_DEC_USE_COUNT -+#endif -+ -+#if ! ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) && \ -+ (defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE))) -+#define VLAN_8021Q_UNUSED -+#endif -+ -+ -+extern spinlock_t vlan_group_lock; -+extern struct net_device *__vlan_find_dev_deep(struct net_device *real_dev, unsigned short VID); -+ -+typedef struct SVIP_NAT_stats -+{ -+ unsigned long inPackets; -+ unsigned long outPackets; -+ unsigned long outErrors; -+} SVIP_NAT_stats_t; -+ -+typedef struct SVIP_NAT_table_entry -+{ -+ SVIP_NAT_IO_Rule_t natRule; -+ SVIP_NAT_stats_t natStats[SVIP_NAT_STATS_TYPES]; -+} SVIP_NAT_table_entry_t; -+ -+/* pointer to the SVIP NAT table */ -+static SVIP_NAT_table_entry_t *pNatTable = NULL; -+ -+struct net_device *net_devs[3]; -+static u32 *paddr_eth0; -+static u32 *paddr_eth0_0; -+static u32 *paddr_veth0; -+static u32 *pmask_veth0; -+ -+static struct semaphore *sem_nat_tbl_access; -+static int proc_read_in_progress = 0; -+ -+static int nDeviceOpen = 0; -+ -+/* saves the NAT table index between subsequent invocation */ -+static int nProcReadIdx = 0; -+ -+static long SVIP_NAT_device_ioctl(struct file *,unsigned int ,unsigned long); -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0) -+static int SVIP_NAT_device_release (struct inode *,struct file *); -+#else -+static void SVIP_NAT_device_release (struct inode *,struct file *); -+#endif -+static int SVIP_NAT_device_open (struct inode *,struct file *); -+ -+/* This structure holds the interface functions supported by -+ the SVIP NAT configuration device. */ -+struct file_operations SVIP_NAT_Fops = { -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) -+owner: THIS_MODULE, -+#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) */ -+ llseek: NULL, /* seek */ -+ read: NULL, -+ write: NULL, -+ readdir: NULL, /* readdir */ -+ poll: NULL, /* select */ -+ unlocked_ioctl: SVIP_NAT_device_ioctl, /* ioctl */ -+ mmap: NULL, /* mmap */ -+ open: SVIP_NAT_device_open, /* open, */ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0) -+ flush: NULL, /* flush */ -+#endif -+ release: SVIP_NAT_device_release /* close */ -+}; -+ -+/** Structure holding MISC module operations */ -+static struct miscdevice SVIP_NAT_miscdev = -+{ -+minor: MINOR_NUM_SVIP_NAT, -+ name: SVIP_NAT_DEVICE_NAME, -+ fops: &SVIP_NAT_Fops -+}; -+ -+#ifdef CONFIG_SVIP_FW_PKT_SNIFFER -+int nSVIP_NAT_Sniffer; -+unsigned char pSVIP_NAT_SnifferMAC[ETH_ALEN]; -+int nSVIP_NAT_SnifferMacSet; -+#endif -+ -+/******************************************************************************/ -+/** -+ Function to read /proc/net/svip_nat/nat proc entry -+ -+ \arguments -+ page - pointer to page buffer -+ start - pointer to start address pointer -+ off - offset -+ count - maximum data length to read -+ eof - end of file flag -+ data - proc read data (provided by the function -+ pointed to by data) -+ -+ \return -+ length of read data -+ -+ \remarks: -+ Each call of this routine forces a copy_to_user of the data returned by -+ 'fn'. This routine will be called by the user until 'len = 0'. -+ ****************************************************************************/ -+static int SVIP_NAT_ProcRead (char *page, char **start, off_t off, -+ int count, int *eof, void *data) -+{ -+ unsigned long flags; -+ int (*fn)(char *buf, int size); -+ int len; -+ -+ /* If the NAT table index is negative, the reading has completed */ -+ if (nProcReadIdx < 0) -+ { -+ nProcReadIdx = 0; -+ *eof = 1; -+ proc_read_in_progress = 0; -+ up(sem_nat_tbl_access); -+ return 0; -+ } -+ -+ local_irq_save(flags); -+ if (!proc_read_in_progress) -+ { -+ proc_read_in_progress = 1; -+ local_irq_restore(flags); -+ /* we use this semaphore in order to ensure no other party(could be ioctl -+ FIO_SVIP_NAT_RULE_LIST), uses function SVIP_NAT_ProcReadNAT(), during -+ the time read of the proc file takes place */ -+ down(sem_nat_tbl_access); -+ } -+ else -+ { -+ local_irq_restore(flags); -+ } -+ -+ if (data != NULL) -+ { -+ fn = data; -+ len = fn (page, count); -+ /* In this setup each read of the proc entries returns the read data by -+ 'fn' to the user. The user keeps issuing read requests as long as the -+ returned value of 'len' is greater than zero. */ -+ *eof = 1; -+ *start = page; -+ } -+ else -+ { -+ len = 0; -+ } -+ -+ return len; -+} -+ -+#ifdef CONFIG_SVIP_FW_PKT_SNIFFER -+/** -+ Function to read remaining proc entries -+ */ -+static int SVIP_NAT_ProcReadGen (char *page, char **start, off_t off, -+ int count, int *eof, void *data) -+{ -+ int (*fn)(char *buf, int size); -+ int len = 0; -+ -+ MOD_INC_USE_COUNT; -+ -+ if (data == NULL) -+ { -+ MOD_DEC_USE_COUNT; -+ return 0; -+ } -+ -+ fn = data; -+ len = fn (page, count); -+ -+ if (len <= off + count) -+ { -+ *eof = 1; -+ } -+ *start = page + off; -+ len -= off; -+ if (len > count) -+ { -+ len = count; -+ } -+ if (len < 0) -+ { -+ len = 0; -+ } -+ -+ MOD_DEC_USE_COUNT; -+ -+ return len; -+} -+#endif -+ -+/******************************************************************************/ -+/** -+ Function for setting up /proc/net/svip_nat read data -+ -+ \arguments -+ buf - pointer to read buffer -+ count - size of read buffer -+ -+ \return -+ length of read data into buffer -+ -+ \remarks: -+ The global variable 'nProcReadIdx' is used to save the table index where -+ the reading of the NAT table stopped. Reading is stopped when the end of -+ the read buffer is approached. On the next itteration the reading continues -+ from the saved index. -+ *******************************************************************************/ -+static int SVIP_NAT_ProcReadNAT(char *buf, int count) -+{ -+ int i, j; -+ int len = 0; -+ SVIP_NAT_IO_Rule_t *pNatRule; -+ -+ if (nProcReadIdx == -1) -+ { -+ nProcReadIdx = 0; -+ return 0; -+ } -+ -+ if (nProcReadIdx == 0) -+ { -+ len = sprintf(buf+len, -+ "Remote host IP " /* 16 char */ -+ "Remote host MAC " /* 19 char */ -+ "Local host IP " /* 15 char */ -+ "Local host MAC " /* 19 char */ -+ "Local host UDP " /* 16 char */ -+ "Loc->Rem(in/out/err) " /* 22 char */ -+ "Rem->Loc(in/out/err)\n\r"); -+ } -+ -+ for (i = nProcReadIdx; i < SVIP_SYS_CODEC_NUM; i++) -+ { -+ int slen; -+ -+ pNatRule = &pNatTable[i].natRule; -+ -+ if (pNatRule->remIP != 0) -+ { -+ /* make sure not to overwrite the buffer */ -+ if (count < len+120) -+ break; -+ -+ /* remIP */ -+ slen = sprintf(buf+len, "%d.%d.%d.%d", -+ (int)((pNatRule->remIP >> 24) & 0xff), -+ (int)((pNatRule->remIP >> 16) & 0xff), -+ (int)((pNatRule->remIP >> 8) & 0xff), -+ (int)((pNatRule->remIP >> 0) & 0xff)); -+ len += slen; -+ for (j = 0; j < (16-slen); j++) -+ len += sprintf(buf+len, " "); -+ -+ /* remMAC */ -+ slen = 0; -+ for (j = 0; j < ETH_ALEN; j++) -+ { -+ slen += sprintf(buf+len+slen, "%02x%s", -+ pNatRule->remMAC[j], j < ETH_ALEN-1 ? ":" : " "); -+ } -+ len += slen; -+ for (j = 0; j < (19-slen); j++) -+ len += sprintf(buf+len, " "); -+ -+ /* locIP */ -+ slen = sprintf(buf+len, "%d.%d.%d.%d", -+ (int)((pNatRule->locIP >> 24) & 0xff), -+ (int)((pNatRule->locIP >> 16) & 0xff), -+ (int)((pNatRule->locIP >> 8) & 0xff), -+ (int)((pNatRule->locIP >> 0) & 0xff)); -+ len += slen; -+ for (j = 0; j < (15-slen); j++) -+ len += sprintf(buf+len, " "); -+ -+ /* locMAC */ -+ slen = 0; -+ for (j = 0; j < ETH_ALEN; j++) -+ { -+ slen += sprintf(buf+len+slen, "%02x%s", -+ pNatRule->locMAC[j], j < ETH_ALEN-1 ? ":" : " "); -+ } -+ len += slen; -+ for (j = 0; j < (19-slen); j++) -+ len += sprintf(buf+len, " "); -+ -+ /* locUDP */ -+ slen = sprintf(buf+len, "%d", pNatRule->locUDP); -+ len += slen; -+ for (j = 0; j < (16-slen); j++) -+ len += sprintf(buf+len, " "); -+ -+ /* NAT statistics, Local to Remote translation */ -+ slen = sprintf(buf+len, "(%ld/%ld/%ld)", -+ pNatTable[i].natStats[SVIP_NAT_STATS_LOC2REM].inPackets, -+ pNatTable[i].natStats[SVIP_NAT_STATS_LOC2REM].outPackets, -+ pNatTable[i].natStats[SVIP_NAT_STATS_LOC2REM].outErrors); -+ len += slen; -+ for (j = 0; j < (22-slen); j++) -+ len += sprintf(buf+len, " "); -+ -+ /* NAT statistics, Remote to Local translation */ -+ len += sprintf(buf+len, "(%ld/%ld/%ld)\n\r", -+ pNatTable[i].natStats[SVIP_NAT_STATS_REM2LOC].inPackets, -+ pNatTable[i].natStats[SVIP_NAT_STATS_REM2LOC].outPackets, -+ pNatTable[i].natStats[SVIP_NAT_STATS_REM2LOC].outErrors); -+ } -+ } -+ if (i == SVIP_SYS_CODEC_NUM) -+ nProcReadIdx = -1; /* reading completed */ -+ else -+ nProcReadIdx = i; /* reading still in process, buffer was full */ -+ -+ return len; -+} -+ -+#ifdef CONFIG_SVIP_FW_PKT_SNIFFER -+/** -+ Converts MAC address from ascii to hex respesentaion -+ */ -+static int SVIP_NAT_MacAsciiToHex(const char *pMacStr, unsigned char *pMacHex) -+{ -+ int i=0, c=0, b=0, n=0; -+ -+ memset(pMacHex, 0, ETH_ALEN); -+ while (pMacStr[i] != '\0') -+ { -+ if (n >= 0) -+ { -+ unsigned char nToHex = 0; -+ -+ /* check for hex digit */ -+ if (pMacStr[i] >= '0' && pMacStr[i] <= '9') -+ nToHex = 0x30; -+ else if (pMacStr[i] >= 'a' && pMacStr[i] <= 'f') -+ nToHex = 0x57; -+ else if (pMacStr[i] >= 'A' && pMacStr[i] <= 'F') -+ nToHex = 0x37; -+ else -+ { -+ if (n != 0) -+ { -+ printk(KERN_ERR "SVIP NAT: invalid MAC address format[%s]\n", pMacStr); -+ return -1; -+ } -+ i++; -+ continue; -+ } -+ n^=1; -+ pMacHex[b] |= ((pMacStr[i] - nToHex)&0xf) << (4*n); -+ if (n == 0) -+ { -+ /* advance to next byte, check if complete */ -+ if (++b >= ETH_ALEN) -+ return 0; -+ /* byte completed, next we expect a colon... */ -+ c = 1; -+ /* and, do not check for hex digit */ -+ n = -1; -+ } -+ i++; -+ continue; -+ } -+ if (c == 1) -+ { -+ if (pMacStr[i] == ':') -+ { -+ /* next we expect hex digit, again */ -+ n = 0; -+ } -+ else -+ { -+ printk(KERN_ERR "SVIP NAT: invalid MAC address format[%s]\n", pMacStr); -+ return -1; -+ } -+ } -+ i++; -+ } -+ return 0; -+} -+ -+/** -+ Used to set the destination MAC address of a host where incoming -+ SVIP VoFW packets are to be addressed. In case the address is set -+ to 00:00:00:00:00:00 (the default case), the packets will written -+ out to eth0 with its original MAC addess. -+ -+ \remark -+usage: 'echo "00:03:19:00:15:D1" > cat /proc/net/svip_nat/snifferMAC' -+*/ -+int SVIP_NAT_ProcWriteSnifferMAC (struct file *file, const char *buffer, -+ unsigned long count, void *data) -+{ -+ /* at least strlen("xx:xx:xx:xx:xx:xx") characters, followed by '\0' */ -+ if (count >= 18) -+ { -+ int ret; -+ -+ ret = SVIP_NAT_MacAsciiToHex(buffer, pSVIP_NAT_SnifferMAC); -+ -+ if (ret != 0) -+ return 0; -+ -+ if (!(pSVIP_NAT_SnifferMAC[0]==0 && pSVIP_NAT_SnifferMAC[1]==0 && -+ pSVIP_NAT_SnifferMAC[2]==0 && pSVIP_NAT_SnifferMAC[3]==0 && -+ pSVIP_NAT_SnifferMAC[4]==0 && pSVIP_NAT_SnifferMAC[5]==0)) -+ { -+ nSVIP_NAT_SnifferMacSet = 1; -+ } -+ } -+ return count; -+} -+ -+/** -+ Used to read the destination MAC address of a sniffer host -+ */ -+int SVIP_NAT_ProcReadSnifferMAC (char *buf, int count) -+{ -+ int len = 0; -+ -+ len = snprintf(buf, count, "%02x:%02x:%02x:%02x:%02x:%02x\n", -+ pSVIP_NAT_SnifferMAC[0], pSVIP_NAT_SnifferMAC[1], -+ pSVIP_NAT_SnifferMAC[2], pSVIP_NAT_SnifferMAC[3], -+ pSVIP_NAT_SnifferMAC[4], pSVIP_NAT_SnifferMAC[5]); -+ -+ if (len > count) -+ { -+ printk(KERN_ERR "SVIP NAT: Only part of the text could be put into the buffer\n"); -+ return count; -+ } -+ -+ return len; -+} -+ -+/** -+ Used to switch VoFW message sniffer on/off -+ -+ \remark -+usage: 'echo "1" > cat /proc/net/svip_nat/snifferOnOff' -+*/ -+int SVIP_NAT_ProcWriteSnifferOnOff (struct file *file, const char *buffer, -+ unsigned long count, void *data) -+{ -+ /* at least one digit expected, followed by '\0' */ -+ if (count >= 2) -+ { -+ int ret, nSnifferOnOff; -+ -+ ret = sscanf(buffer, "%d", &nSnifferOnOff); -+ -+ if (ret != 1) -+ return count; -+ -+ if (nSnifferOnOff > 0) -+ nSnifferOnOff = 1; -+ -+ nSVIP_NAT_Sniffer = nSnifferOnOff; -+ } -+ return count; -+} -+ -+/** -+ Used to read the VoFW message sniffer configuration (on/off) -+ */ -+int SVIP_NAT_ProcReadSnifferOnOff (char *buf, int count) -+{ -+ int len = 0; -+ -+ len = snprintf(buf, count, "%d\n", nSVIP_NAT_Sniffer); -+ -+ if (len > count) -+ { -+ printk(KERN_ERR "SVIP NAT: Only part of the text could be put into the buffer\n"); -+ return count; -+ } -+ -+ return len; -+} -+#endif -+ -+/******************************************************************************/ -+/** -+ Creates proc read/write entries -+ -+ \return -+ 0 on success, -1 on error -+ */ -+/******************************************************************************/ -+static int SVIP_NAT_ProcInstall(void) -+{ -+ struct proc_dir_entry *pProcParentDir, *pProcDir; -+ struct proc_dir_entry *pProcNode; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) -+ pProcParentDir = proc_net; -+#else -+ pProcParentDir = init_net.proc_net; -+#endif -+ pProcDir = proc_mkdir(SVIP_NAT_DEVICE_NAME, pProcParentDir); -+ if (pProcDir == NULL) -+ { -+ printk(KERN_ERR "SVIP NAT: cannot create proc dir %s/%s\n\r", -+ pProcParentDir->name, SVIP_NAT_DEVICE_NAME); -+ return -1; -+ } -+ -+ pProcNode = create_proc_read_entry("nat", S_IFREG|S_IRUGO, pProcDir, -+ SVIP_NAT_ProcRead, (void *)SVIP_NAT_ProcReadNAT); -+ if (pProcNode == NULL) -+ { -+ printk(KERN_ERR "SVIP NAT: cannot create proc entry %s/%s", -+ pProcDir->name, "nat"); -+ return -1; -+ } -+ -+#ifdef CONFIG_SVIP_FW_PKT_SNIFFER -+ nSVIP_NAT_Sniffer = 0; -+ /* creates proc entry for switching on/off sniffer to VoFW messages */ -+ pProcNode = create_proc_read_entry("snifferOnOff", S_IFREG|S_IRUGO|S_IWUGO, -+ pProcDir, SVIP_NAT_ProcReadGen, (void *)SVIP_NAT_ProcReadSnifferOnOff); -+ if (pProcNode == NULL) -+ { -+ printk(KERN_ERR "SVIP NAT: cannot create proc entry %s/%s\n\r", -+ pProcDir->name, "snifferOnOff"); -+ return -1; -+ } -+ pProcNode->write_proc = SVIP_NAT_ProcWriteSnifferOnOff; -+ -+ memset (pSVIP_NAT_SnifferMAC, 0, ETH_ALEN); -+ nSVIP_NAT_SnifferMacSet = 0; -+ /* creates proc entry for setting MAC address of sniffer host to VoFW messages */ -+ pProcNode = create_proc_read_entry("snifferMAC", S_IFREG|S_IRUGO|S_IWUGO, -+ pProcDir, SVIP_NAT_ProcReadGen, (void *)SVIP_NAT_ProcReadSnifferMAC); -+ if (pProcNode == NULL) -+ { -+ printk(KERN_ERR "SVIP NAT: cannot create proc entry %s/%s\n\r", -+ pProcDir->name, "snifferMAC"); -+ return -1; -+ } -+ pProcNode->write_proc = SVIP_NAT_ProcWriteSnifferMAC; -+#endif -+ -+ return 0; -+} -+ -+/******************************************************************************/ -+/** -+ No actions done here, simply a check is performed if an open has already -+ been performed. Currently only a single open is allowed as it is a sufficient -+ to have hat a single process configuring the SVIP NAT at one time. -+ -+ \arguments -+ inode - pointer to disk file data -+ file - pointer to device file data -+ -+ \return -+ 0 on success, else -1 -+ */ -+/******************************************************************************/ -+static int SVIP_NAT_device_open(struct inode *inode, struct file *file) -+{ -+ unsigned long flags; -+ struct in_device *in_dev; -+ struct in_ifaddr *ifa; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ local_irq_save(flags); -+#else -+ local_save_flags(flags); -+#endif -+ -+ if (nDeviceOpen) -+ { -+ MOD_INC_USE_COUNT; -+ local_irq_restore(flags); -+ nDeviceOpen++; -+ return 0; -+ } -+ -+ /* find pointer to IP address of eth0 */ -+ if ((in_dev=in_dev_get(net_devs[SVIP_NET_DEV_ETH0_IDX])) != NULL) -+ { -+ for (ifa = in_dev->ifa_list; ifa != NULL; ifa = ifa->ifa_next) -+ { -+ if (!paddr_eth0 && ifa->ifa_address != 0) -+ { -+ paddr_eth0 = &ifa->ifa_address; -+ continue; -+ } -+ if (paddr_eth0 && ifa->ifa_address != 0) -+ { -+ paddr_eth0_0 = &ifa->ifa_address; -+ break; -+ } -+ } -+ in_dev_put(in_dev); -+ } -+ if (paddr_eth0 == NULL || paddr_eth0_0 == NULL) -+ { -+ local_irq_restore(flags); -+ return -ENODATA; -+ } -+ -+ /* find pointer to IP address of veth0 */ -+ if ((in_dev=in_dev_get(net_devs[SVIP_NET_DEV_VETH0_IDX])) != NULL) -+ { -+ for (ifa = in_dev->ifa_list; ifa != NULL; ifa = ifa->ifa_next) -+ { -+ if (ifa->ifa_address != 0) -+ { -+ paddr_veth0 = &ifa->ifa_address; -+ pmask_veth0 = &ifa->ifa_mask; -+ break; -+ } -+ } -+ in_dev_put(in_dev); -+ } -+ if (paddr_veth0 == NULL) -+ { -+ local_irq_restore(flags); -+ return -ENODATA; -+ } -+ -+ MOD_INC_USE_COUNT; -+ nDeviceOpen++; -+ local_irq_restore(flags); -+ -+ return 0; -+} -+ -+ -+/******************************************************************************/ -+/** -+ This function is called when a process closes the SVIP NAT device file -+ -+ \arguments -+ inode - pointer to disk file data -+ file - pointer to device file data -+ -+ \return -+ 0 on success, else -1 -+ -+*/ -+/******************************************************************************/ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0) -+static int SVIP_NAT_device_release(struct inode *inode, -+ struct file *file) -+#else -+static void SVIP_NAT_device_release(struct inode *inode, -+ struct file *file) -+#endif -+{ -+ unsigned long flags; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ save_flags(flags); -+ cli(); -+#else -+ local_save_flags(flags); -+#endif -+ -+ /* The device can now be openned by the next caller */ -+ nDeviceOpen--; -+ -+ MOD_DEC_USE_COUNT; -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ restore_flags(flags); -+#else -+ local_irq_restore(flags); -+#endif -+ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0) -+ return 0; -+#endif -+} -+ -+ -+/******************************************************************************/ -+/** -+ This function is called when a process closes the SVIP NAT device file -+ -+ \arguments -+ inode - pointer to disk file data -+ file - pointer to device file data -+ ioctl_num - ioctl number requested -+ ioctl_param - pointer to data related to the ioctl number -+ -+ \return -+ 0 on success, else -1 -+ -+*/ -+/******************************************************************************/ -+long SVIP_NAT_device_ioctl (struct file *file, -+ unsigned int ioctl_num, unsigned long ioctl_param) -+{ -+ int ret = 0; -+ SVIP_NAT_IO_Rule_t *pNatRule, *pNatRuleIn; -+ SVIP_UDP_PORT_t nPort; -+ int nNatIdx; -+ int bWrite = 0; -+ int bRead = 0; -+ unsigned char *pData = 0; -+ int nSize; -+ -+ if (_IOC_DIR(ioctl_num) & _IOC_WRITE) -+ bWrite = 1; -+ if (_IOC_DIR(ioctl_num) & _IOC_READ) -+ bRead = 1; -+ nSize = _IOC_SIZE(ioctl_num); -+ -+ if (nSize > sizeof(int)) -+ { -+ if (bRead || bWrite) -+ { -+ pData = kmalloc (nSize, GFP_KERNEL); -+ if (bWrite) -+ { -+ if (copy_from_user ((void *)pData, (void *)ioctl_param, nSize) != 0) -+ { -+ printk(KERN_ERR "SVIP NAT: ioctl %x: copy_from_user() failed!\n", ioctl_num); -+ ret = -1; -+ goto error; -+ } -+ } -+ } -+ } -+ -+ switch (ioctl_num) -+ { -+ case FIO_SVIP_NAT_RULE_ADD: -+ -+ pNatRuleIn = (SVIP_NAT_IO_Rule_t *)pData; -+ -+ /* check if destination UDP port is within range */ -+ nPort = ntohs(pNatRuleIn->locUDP); -+ -+ if (!SVIP_PORT_INRANGE(nPort)) -+ { -+ printk(KERN_ERR "SVIP NAT: Error, UDP port(%d) is out of range(%d..%d)\n", -+ nPort, SVIP_UDP_FROM, SVIP_UDP_TO); -+ ret = -1; -+ goto error; -+ } -+ nNatIdx = SVIP_PORT_INDEX(nPort); -+ -+ down(sem_nat_tbl_access); -+ pNatRule = &pNatTable[nNatIdx].natRule; -+ -+ /* add rule to the NAT table */ -+ pNatRule->remIP = pNatRuleIn->remIP; -+ memcpy((char *)pNatRule->remMAC, (char *)pNatRuleIn->remMAC, ETH_ALEN); -+ pNatRule->locIP = pNatRuleIn->locIP; -+ memcpy((char *)pNatRule->locMAC, (char *)pNatRuleIn->locMAC, ETH_ALEN); -+ pNatRule->locUDP = pNatRuleIn->locUDP; -+ -+ memset(pNatTable[nNatIdx].natStats, 0, -+ sizeof(SVIP_NAT_stats_t)*SVIP_NAT_STATS_TYPES); -+ up(sem_nat_tbl_access); -+ break; -+ -+ case FIO_SVIP_NAT_RULE_REMOVE: -+ -+ pNatRuleIn = (SVIP_NAT_IO_Rule_t *)pData; -+ -+ /* check if destination UDP port is within range */ -+ nPort = ntohs(pNatRuleIn->locUDP); -+ if (!SVIP_PORT_INRANGE(nPort)) -+ { -+ printk(KERN_ERR "SVIP NAT: Error, UDP port(%d) is out of range(%d..%d)\n", -+ nPort, SVIP_UDP_FROM, SVIP_UDP_TO); -+ ret = -1; -+ goto error; -+ } -+ nNatIdx = SVIP_PORT_INDEX(nPort); -+ down(sem_nat_tbl_access); -+ /* remove rule from the NAT table */ -+ memset(&pNatTable[nNatIdx], 0, sizeof(SVIP_NAT_table_entry_t)); -+ up(sem_nat_tbl_access); -+ break; -+ -+ case FIO_SVIP_NAT_RULE_LIST: -+ { -+ int len; -+ char buf[256]; -+ -+ down(sem_nat_tbl_access); -+ while (nProcReadIdx != -1) -+ { -+ len = SVIP_NAT_ProcReadNAT(buf, 256); -+ if (len > 0) -+ printk("%s", buf); -+ } -+ nProcReadIdx = 0; -+ up(sem_nat_tbl_access); -+ break; -+ } -+ -+ default: -+ printk(KERN_ERR "SVIP NAT: unsupported ioctl (%x) command for device %s\n", -+ ioctl_num, PATH_SVIP_NAT_DEVICE_NAME); -+ ret = -1; -+ goto error; -+ } -+ -+ if (nSize > sizeof(int)) -+ { -+ if (bRead) -+ { -+ if (copy_to_user ((void *)ioctl_param, (void *)pData, nSize) != 0) -+ { -+ printk(KERN_ERR "SVIP NAT: ioctl %x: copy_to_user() failed!\n", ioctl_num); -+ ret = -1; -+ goto error; -+ } -+ } -+ } -+ -+error: -+ if (pData) -+ kfree(pData); -+ -+ return ret; -+} -+ -+#if 0 -+void dump_msg(unsigned char *pData, unsigned int nLen) -+{ -+ int i; -+ -+ for (i=0; i> 16) -+ sum = (sum & 0xffff)+((sum >> 16) & 0xffff); -+ -+ /* one's complement the result */ -+ sum = ~sum; -+ -+ return (u16)(sum & 0xffff); -+} -+ -+ -+/******************************************************************************/ -+/** -+ Returns a pointer to an ipv4 address assigned to device dev. The ipv4 -+ instance checked is pointed to by ifa_start. The function is suited for -+ itterative calls. -+ -+ \arguments -+ dev - pointer to network interface -+ ifa_start - pointer to ipv4 instance to return ipv4 address assigned -+ to, NULL for the first one -+ ppifa_addr - output parameter -+ -+ \return -+ pointer to the next ipv4 instance, which can be null if ifa_start was -+ the last instance present -+ */ -+/******************************************************************************/ -+static struct in_ifaddr *get_ifaddr(struct net_device *dev, -+ struct in_ifaddr *ifa_start, unsigned int **ppifa_addr) -+{ -+ struct in_device *in_dev; -+ struct in_ifaddr *ifa = NULL; -+ -+ if ((in_dev=in_dev_get(dev)) != NULL) -+ { -+ if (ifa_start == NULL) -+ ifa = in_dev->ifa_list; -+ else -+ ifa = ifa_start; -+ if (ifa) -+ { -+ *ppifa_addr = &ifa->ifa_address; -+ ifa = ifa->ifa_next; -+ } -+ in_dev_put(in_dev); -+ return ifa; -+ } -+ *ppifa_addr = NULL; -+ return NULL; -+} -+ -+/******************************************************************************/ -+/** -+ This function performs IP NAT for received packets satisfying the -+ following requirements: -+ -+ - packet is destined to local IP host -+ - transport protocol type is UDP -+ - destination UDP port is within range -+ -+ \arguments -+ skb - pointer to the receiving socket buffer -+ -+ \return -+ returns 1 on performed SVIP NAT, else returns 0 -+ -+ \remarks -+ When function returns 0, it indicates the caller to pass the -+ packet up the IP stack to make further decision about it -+ */ -+/******************************************************************************/ -+int do_SVIP_NAT (struct sk_buff *skb) -+{ -+ struct net_device *real_dev; -+ struct iphdr *iph; -+ struct udphdr *udph; -+ SVIP_NAT_IO_Rule_t *pNatRule; -+ int nNatIdx, in_eth0, nDir; -+#ifndef VLAN_8021Q_UNUSED -+ int vlan; -+ unsigned short vid; -+#endif /* ! VLAN_8021Q_UNUSED */ -+ SVIP_UDP_PORT_t nPort; -+ u32 orgSrcIp, orgDstIp, *pSrcIp, *pDstIp; -+ struct ethhdr *ethh; -+ -+ /* do not consider if SVIP NAT device not open. */ -+ if (!nDeviceOpen) -+ { -+ return 0; -+ } -+ -+ /* consider only UDP packets. */ -+ iph = SVIP_NAT_IP_HDR(skb); -+ if (iph->protocol != IPPROTO_UDP) -+ { -+ return 0; -+ } -+ -+ udph = (struct udphdr *)((u_int32_t *)iph + iph->ihl); -+ /* consider only packets which UDP port numbers reside within -+ the predefined SVIP NAT UDP port range. */ -+ if ((!SVIP_PORT_INRANGE(ntohs(udph->dest))) && -+ (!SVIP_PORT_INRANGE(ntohs(udph->source)))) -+ { -+ return 0; -+ } -+ -+#ifndef VLAN_8021Q_UNUSED -+ /* check if packet delivered over VLAN. VLAN packets will be routed over -+ the VLAN interfaces of the respective real Ethernet interface, if one -+ exists(VIDs must match). Else, the packet will be send out as IEEE 802.3 -+ Ethernet frame */ -+ if (skb->dev->priv_flags & IFF_802_1Q_VLAN) -+ { -+ vlan = 1; -+ vid = VLAN_DEV_VLAN_ID(skb->dev); -+ real_dev = VLAN_DEV_REAL_DEV(skb->dev); -+ } -+ else -+ { -+ vlan = 0; -+ vid = 0; -+ real_dev = skb->dev; -+ } -+#endif /* ! VLAN_8021Q_UNUSED */ -+ -+#ifdef CONFIG_SVIP_FW_PKT_SNIFFER -+ /** Debugging feature which can be enabled by writing, -+ 'echo 1 > /proc/net/svip_nat/snifferOnOff'. -+ It copies all packets received on veth0 and, sends them out over eth0. -+ When a destination MAC address is specified through -+ /proc/net/svip_nat/snifferMAC, this MAC addess will substitute the -+ original MAC address of the packet. -+ It is recommended to specify a MAC address of some host where Wireshark -+ runs and sniffs for this traffic, else you may flood your LAN with -+ undeliverable traffic. -+ -+NOTE: In case of VLAN traffic the VLAN header information is lost. */ -+ if (nSVIP_NAT_Sniffer) -+ { -+ if (real_dev == net_devs[SVIP_NET_DEV_VETH0_IDX]) -+ { -+ struct sk_buff *copied_skb; -+ -+ /* gain the Ethernet header from the skb */ -+ skb_push(skb, ETH_HLEN); -+ -+ copied_skb = skb_copy (skb, GFP_ATOMIC); -+ -+ if (nSVIP_NAT_SnifferMacSet == 1) -+ { -+ ethh = (struct ethhdr *)SVIP_NAT_SKB_MAC_HEADER(copied_skb); -+ memcpy((char *)ethh->h_dest, (char *)pSVIP_NAT_SnifferMAC, ETH_ALEN); -+ } -+ copied_skb->dev = net_devs[SVIP_NET_DEV_ETH0_IDX]; -+ dev_queue_xmit(copied_skb); -+ -+ /* skip the ETH header again */ -+ skb_pull(skb, ETH_HLEN); -+ } -+ } -+#endif -+ -+ -+ /* check if packet arrived on eth0 */ -+ if (real_dev == net_devs[SVIP_NET_DEV_ETH0_IDX]) -+ { -+ /* check if destination IP address equals the primary assigned IP address -+ of interface eth0. This is the case of packets originating from a -+ remote peer that are to be delivered to a channel residing on THIS -+ voice linecard system. This is typical SVIP NAT case, therefore this -+ rule is placed on top. */ -+ if (iph->daddr == *paddr_eth0) -+ { -+ nPort = ntohs(udph->dest); -+ nDir = SVIP_NAT_STATS_REM2LOC; -+ } -+ /* check if destination IP address equals the secondary assigned IP address -+ of interface eth0. This is not a typical SVIP NAT case. It is basically -+ there, as someone might like for debugging purpose to use the LCC to route -+ Slave SVIP packets which are part of voice/fax streaming. */ -+ else if (iph->daddr == *paddr_eth0_0) -+ { -+ nPort = ntohs(udph->source); -+ nDir = SVIP_NAT_STATS_LOC2REM; -+ } -+#ifndef VLAN_8021Q_UNUSED -+ /* when the packet did not hit the top two rules, here we check if the packet -+ has addressed any of the IP addresses assigned to the VLAN interface attached -+ to eth0. This is not recommended approach because of the CPU cost incurred. */ -+ else if (vlan) -+ { -+ unsigned int *pifa_addr; -+ struct in_ifaddr *ifa_start = NULL; -+ int i = 0; -+ -+ do -+ { -+ ifa_start = get_ifaddr(skb->dev, ifa_start, &pifa_addr); -+ if (!pifa_addr) -+ { -+ /* VLAN packet received on vlan interface attached to eth0, -+ however no IP address assigned to the interface. -+ The packet is ignored. */ -+ return 0; -+ } -+ if (iph->daddr == *pifa_addr) -+ { -+ /* packet destined to... */ -+ break; -+ } -+ if (!ifa_start) -+ { -+ return 0; -+ } -+ i++; -+ } while (ifa_start); -+ if (!i) -+ { -+ /* ...primary assigned IP address to the VLAN interface. */ -+ nPort = ntohs(udph->dest); -+ nDir = SVIP_NAT_STATS_REM2LOC; -+ } -+ else -+ { -+ /* ...secondary assigned IP address to the VLAN interface. */ -+ nPort = ntohs(udph->source); -+ nDir = SVIP_NAT_STATS_LOC2REM; -+ } -+ } -+#endif /* ! VLAN_8021Q_UNUSED */ -+ else -+ { -+ return 0; -+ } -+ in_eth0 = 1; -+ } -+ /* check if packet arrived on veth0 */ -+ else if (real_dev == net_devs[SVIP_NET_DEV_VETH0_IDX]) -+ { -+ nPort = ntohs(udph->source); -+ nDir = SVIP_NAT_STATS_LOC2REM; -+ in_eth0 = 0; -+ } -+ else -+ { -+ /* packet arrived neither on eth0, nor veth0 */ -+ return 0; -+ } -+ -+ /* calculate the respective index of the NAT table */ -+ nNatIdx = SVIP_PORT_INDEX(nPort); -+ /* process the packet if a respective NAT rule exists */ -+ pNatRule = &pNatTable[nNatIdx].natRule; -+ -+ ethh = (struct ethhdr *)SVIP_NAT_SKB_MAC_HEADER(skb); -+ -+ /* copy packet's original source and destination IP addresses to use -+ later on to perform efficient checksum recalculation */ -+ orgSrcIp = iph->saddr; -+ orgDstIp = iph->daddr; -+ -+ if (in_eth0) -+ { -+ u8 *pDstMac; -+ -+ /* Process packet arrived on eth0 */ -+ -+ if (nDir == SVIP_NAT_STATS_REM2LOC && iph->saddr == pNatRule->remIP) -+ { -+ pDstIp = &pNatRule->locIP; -+ pDstMac = pNatRule->locMAC; -+ } -+ else if (nDir == SVIP_NAT_STATS_LOC2REM && iph->saddr == pNatRule->locIP) -+ { -+ pDstIp = &pNatRule->remIP; -+ pDstMac = pNatRule->remMAC; -+ } -+ else -+ { -+ /* Rule check failed. The packet is passed up the layers, -+ it will be dropped by UDP */ -+ return 0; -+ } -+ -+ if ((*pDstIp & *pmask_veth0) == (*paddr_veth0 & *pmask_veth0)) -+ { -+#ifndef VLAN_8021Q_UNUSED -+ if (vlan) -+ { -+ struct net_device *vlan_dev; -+ -+ spin_lock_bh(&vlan_group_lock); -+ vlan_dev = __vlan_find_dev_deep(net_devs[SVIP_NET_DEV_VETH0_IDX], vid); -+ spin_unlock_bh(&vlan_group_lock); -+ if (vlan_dev) -+ { -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ struct vlan_ethhdr *vethh; -+ -+ skb_push(skb, VLAN_ETH_HLEN); -+ /* reconstruct the VLAN header. -+NOTE: priority information is lost */ -+ vethh = (struct vlan_ethhdr *)skb->data; -+ vethh->h_vlan_proto = htons(ETH_P_8021Q); -+ vethh->h_vlan_TCI = htons(vid); -+ vethh->h_vlan_encapsulated_proto = htons(ETH_P_IP); -+ ethh = (struct ethhdr *)vethh; -+#else -+ skb_push(skb, ETH_HLEN); -+#endif -+ skb->dev = vlan_dev; -+ } -+ else -+ { -+ skb->dev = net_devs[SVIP_NET_DEV_VETH0_IDX]; -+ skb_push(skb, ETH_HLEN); -+ } -+ } -+ else -+#endif /* ! VLAN_8021Q_UNUSED */ -+ { -+ skb->dev = net_devs[SVIP_NET_DEV_VETH0_IDX]; -+ skb_push(skb, ETH_HLEN); -+ } -+ pSrcIp = paddr_veth0; -+ } -+ else -+ { -+#ifndef VLAN_8021Q_UNUSED -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ if (vlan) -+ { -+ struct vlan_ethhdr *vethh; -+ -+ /* reconstruct the VLAN header. -+NOTE: priority information is lost */ -+ skb_push(skb, VLAN_ETH_HLEN); -+ vethh = (struct vlan_ethhdr *)skb->data; -+ vethh->h_vlan_proto = htons(ETH_P_8021Q); -+ vethh->h_vlan_TCI = htons(vid); -+ vethh->h_vlan_encapsulated_proto = htons(ETH_P_IP); -+ ethh = (struct ethhdr *)vethh; -+ } -+ else -+#endif -+#endif /* ! VLAN_8021Q_UNUSED */ -+ { -+ skb_push(skb, ETH_HLEN); -+ } -+ /* source IP address equals the destination IP address -+ of the incoming packet */ -+ pSrcIp = &iph->daddr; -+ } -+ iph->saddr = *pSrcIp; -+ memcpy((char *)ethh->h_source, (char *)skb->dev->dev_addr, ETH_ALEN); -+ iph->daddr = *pDstIp; -+ memcpy((char *)ethh->h_dest, (char *)pDstMac, ETH_ALEN); -+ } -+ else -+ { -+ /* Process packet arrived on veth0 */ -+ -+ if (iph->saddr != pNatRule->locIP) -+ { -+ /* Rule check failed. The packet is passed up the layers, -+ it will be dropped by UDP */ -+ return 0; -+ } -+ -+ if (!((pNatRule->remIP & *pmask_veth0) == (*paddr_veth0 & *pmask_veth0))) -+ { -+#ifndef VLAN_8021Q_UNUSED -+ if (vlan) -+ { -+ struct net_device *vlan_dev; -+ -+ spin_lock_bh(&vlan_group_lock); -+ vlan_dev = __vlan_find_dev_deep(net_devs[SVIP_NET_DEV_ETH0_IDX], vid); -+ spin_unlock_bh(&vlan_group_lock); -+ if (vlan_dev) -+ { -+ unsigned int *pifa_addr; -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ struct vlan_ethhdr *vethh; -+ -+ skb_push(skb, VLAN_ETH_HLEN); -+ /* construct the VLAN header, note priority information is lost */ -+ vethh = (struct vlan_ethhdr *)skb->data; -+ vethh->h_vlan_proto = htons(ETH_P_8021Q); -+ vethh->h_vlan_TCI = htons(vid); -+ vethh->h_vlan_encapsulated_proto = htons(ETH_P_IP); -+ ethh = (struct ethhdr *)vethh; -+#else -+ skb_push(skb, ETH_HLEN); -+#endif -+ skb->dev = vlan_dev; -+ -+ get_ifaddr(skb->dev, NULL, &pifa_addr); -+ if (pifa_addr) -+ { -+ pSrcIp = pifa_addr; -+ } -+ else -+ { -+ pSrcIp = paddr_eth0; -+ } -+ } -+ else -+ { -+ skb->dev = net_devs[SVIP_NET_DEV_ETH0_IDX]; -+ pSrcIp = paddr_eth0; -+ skb_push(skb, ETH_HLEN); -+ } -+ } -+ else -+#endif /* ! VLAN_8021Q_UNUSED */ -+ { -+ skb->dev = net_devs[SVIP_NET_DEV_ETH0_IDX]; -+ pSrcIp = paddr_eth0; -+ skb_push(skb, ETH_HLEN); -+ } -+ } -+ else -+ { -+ pSrcIp = paddr_veth0; -+#ifndef VLAN_8021Q_UNUSED -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) -+ if (vlan) -+ { -+ struct vlan_ethhdr *vethh; -+ -+ skb_push(skb, VLAN_ETH_HLEN); -+ /* reconstruct the VLAN header. -+NOTE: priority information is lost. */ -+ vethh = (struct vlan_ethhdr *)skb->data; -+ vethh->h_vlan_proto = htons(ETH_P_8021Q); -+ vethh->h_vlan_TCI = htons(vid); -+ vethh->h_vlan_encapsulated_proto = htons(ETH_P_IP); -+ ethh = (struct ethhdr *)vethh; -+ } -+ else -+#endif -+#endif /* ! VLAN_8021Q_UNUSED */ -+ { -+ skb_push(skb, ETH_HLEN); -+ } -+ } -+ iph->saddr = *pSrcIp; -+ memcpy((char *)ethh->h_source, (char *)skb->dev->dev_addr, ETH_ALEN); -+ iph->daddr = pNatRule->remIP; -+ memcpy((char *)ethh->h_dest, (char *)pNatRule->remMAC, ETH_ALEN); -+ } -+ pNatTable[nNatIdx].natStats[nDir].inPackets++; -+ -+ iph->check = ip_udp_quick_csum(iph->check, (u16 *)&orgSrcIp, (u16 *)&iph->saddr, -+ (u16 *)&orgDstIp, (u16 *)&iph->daddr); -+ if (udph->check != 0) -+ { -+ udph->check = ip_udp_quick_csum(udph->check, (u16 *)&orgSrcIp, (u16 *)&iph->saddr, -+ (u16 *)&orgDstIp, (u16 *)&iph->daddr); -+ } -+ -+ /* write the packet out, directly to the network device */ -+ if (dev_queue_xmit(skb) < 0) -+ pNatTable[nNatIdx].natStats[nDir].outErrors++; -+ else -+ pNatTable[nNatIdx].natStats[nDir].outPackets++; -+ -+ return 1; -+} -+ -+/******************************************************************************/ -+/** -+ Function executed upon unloading of the SVIP NAT module. It unregisters the -+ SVIP NAT configuration device and frees the memory used for the NAT table. -+ -+ \remarks: -+ Currently the SVIP NAT module is statically linked into the Linux kernel -+ therefore this routine cannot be executed. -+ *******************************************************************************/ -+static int __init init(void) -+{ -+ int ret = 0; -+ struct net_device *dev; -+ -+ if (misc_register(&SVIP_NAT_miscdev) != 0) -+ { -+ printk(KERN_ERR "%s: cannot register SVIP NAT device node.\n", -+ SVIP_NAT_miscdev.name); -+ return -EIO; -+ } -+ -+ /* allocation of memory for NAT table */ -+ pNatTable = (SVIP_NAT_table_entry_t *)kmalloc( -+ sizeof(SVIP_NAT_table_entry_t) * SVIP_SYS_CODEC_NUM, GFP_ATOMIC); -+ if (pNatTable == NULL) -+ { -+ printk (KERN_ERR "SVIP NAT: Error(%d), allocating memory for NAT table\n", ret); -+ return -1; -+ } -+ -+ /* clear the NAT table */ -+ memset((void *)pNatTable, 0, sizeof(SVIP_NAT_table_entry_t) * SVIP_SYS_CODEC_NUM); -+ -+ if ((sem_nat_tbl_access = kmalloc(sizeof(struct semaphore), GFP_KERNEL))) -+ { -+ sema_init(sem_nat_tbl_access, 1); -+ } -+ -+ SVIP_NAT_ProcInstall(); -+ -+ /* find pointers to 'struct net_device' of eth0 and veth0, respectevely */ -+ read_lock(&dev_base_lock); -+ SVIP_NAT_FOR_EACH_NETDEV(dev) -+ { -+ if (!strcmp(dev->name, SVIP_NET_DEV_ETH0_NAME)) -+ { -+ net_devs[SVIP_NET_DEV_ETH0_IDX] = dev; -+ } -+ if (!strcmp(dev->name, SVIP_NET_DEV_VETH1_NAME)) -+ { -+ net_devs[SVIP_NET_DEV_VETH0_IDX] = dev; -+ } -+ else if (!strcmp(dev->name, SVIP_NET_DEV_ETH1_NAME)) -+ { -+ net_devs[SVIP_NET_DEV_VETH0_IDX] = dev; -+ } -+ } -+ read_unlock(&dev_base_lock); -+ -+ if (net_devs[SVIP_NET_DEV_ETH0_IDX] == NULL || -+ net_devs[SVIP_NET_DEV_VETH0_IDX] == NULL) -+ { -+ printk (KERN_ERR "SVIP NAT: Error, unable to locate eth0 and veth0 interfaces\n"); -+ return -1; -+ } -+ -+ printk ("%s, (c) 2009, Lantiq Deutschland GmbH\n", &SVIP_NAT_INFO_STR[4]); -+ -+ return ret; -+} -+ -+/******************************************************************************/ -+/** -+ Function executed upon unloading of the SVIP NAT module. It unregisters the -+ SVIP NAT configuration device and frees the memory used for the NAT table. -+ -+ \remarks: -+ Currently the SVIP NAT module is statically linked into the Linux kernel -+ therefore this routine cannot be executed. -+ *******************************************************************************/ -+static void __exit fini(void) -+{ -+ MOD_DEC_USE_COUNT; -+ -+ /* unregister SVIP NAT configuration device */ -+ misc_deregister(&SVIP_NAT_miscdev); -+ -+ /* release memory of SVIP NAT table */ -+ if (pNatTable != NULL) -+ { -+ kfree (pNatTable); -+ } -+} -+ -+module_init(init); -+module_exit(fini); -Index: linux-3.3.8/drivers/spi/Kconfig -=================================================================== ---- linux-3.3.8.orig/drivers/spi/Kconfig 2012-07-31 19:51:33.077105873 +0200 -+++ linux-3.3.8/drivers/spi/Kconfig 2012-07-31 19:51:34.153105919 +0200 -@@ -366,6 +366,11 @@ - This driver also supports the ML7213/ML7223/ML7831, a companion chip - for the Atom E6xx series and compatible with the Intel EG20T PCH. - -+config SPI_SVIP -+ tristate "SVIP SPI controller" -+ depends on SOC_SVIP -+ default y -+ - config SPI_TXX9 - tristate "Toshiba TXx9 SPI controller" - depends on GENERIC_GPIO && CPU_TX49XX -Index: linux-3.3.8/drivers/spi/Makefile -=================================================================== ---- linux-3.3.8.orig/drivers/spi/Makefile 2012-07-31 19:51:33.077105873 +0200 -+++ linux-3.3.8/drivers/spi/Makefile 2012-07-31 19:51:34.153105919 +0200 -@@ -61,4 +61,5 @@ - obj-$(CONFIG_SPI_TXX9) += spi-txx9.o - obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o - obj-$(CONFIG_SPI_XWAY) += spi-xway.o -+obj-$(CONFIG_SPI_SVIP) += spi_svip.o - -Index: linux-3.3.8/net/ipv4/Kconfig -=================================================================== ---- linux-3.3.8.orig/net/ipv4/Kconfig 2012-06-01 09:16:13.000000000 +0200 -+++ linux-3.3.8/net/ipv4/Kconfig 2012-07-31 19:51:34.153105919 +0200 -@@ -630,3 +630,10 @@ - on the Internet. - - If unsure, say N. -+ -+config SVIP_NAT -+ bool "Include SVIP NAT" -+ depends on SOC_SVIP -+ default y -+ ---help--- -+ Include the SVIP NAT. -Index: linux-3.3.8/net/ipv4/Makefile -=================================================================== ---- linux-3.3.8.orig/net/ipv4/Makefile 2012-07-31 19:51:33.401105887 +0200 -+++ linux-3.3.8/net/ipv4/Makefile 2012-07-31 19:51:34.153105919 +0200 -@@ -56,3 +56,4 @@ - - obj-$(CONFIG_XFRM) += xfrm4_policy.o xfrm4_state.o xfrm4_input.o \ - xfrm4_output.o -+obj-$(CONFIG_SVIP_NAT) += svip_nat.o -Index: linux-3.3.8/arch/mips/lantiq/svip/switchip_setup.c -=================================================================== ---- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux-3.3.8/arch/mips/lantiq/svip/switchip_setup.c 2012-07-31 19:51:34.153105919 +0200 -@@ -0,0 +1,666 @@ -+/****************************************************************************** -+ Copyright (c) 2007, Infineon Technologies. All rights reserved. -+ -+ No Warranty -+ Because the program is licensed free of charge, there is no warranty for -+ the program, to the extent permitted by applicable law. Except when -+ otherwise stated in writing the copyright holders and/or other parties -+ provide the program "as is" without warranty of any kind, either -+ expressed or implied, including, but not limited to, the implied -+ warranties of merchantability and fitness for a particular purpose. The -+ entire risk as to the quality and performance of the program is with -+ you. should the program prove defective, you assume the cost of all -+ necessary servicing, repair or correction. -+ -+ In no event unless required by applicable law or agreed to in writing -+ will any copyright holder, or any other party who may modify and/or -+ redistribute the program as permitted above, be liable to you for -+ damages, including any general, special, incidental or consequential -+ damages arising out of the use or inability to use the program -+ (including but not limited to loss of data or data being rendered -+ inaccurate or losses sustained by you or third parties or a failure of -+ the program to operate with any other programs), even if such holder or -+ other party has been advised of the possibility of such damages. -+ ****************************************************************************** -+ Module : switchip_setup.c -+ Date : 2007-11-09 -+ Description : Basic setup of embedded ethernet switch "SwitchIP" -+ Remarks: andreas.schmidt@infineon.com -+ -+ *****************************************************************************/ -+ -+/* TODO: get rid of #ifdef CONFIG_LANTIQ_MACH_EASY336 */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+ -+static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; -+static struct svip_reg_es *const es = (struct svip_reg_es *)LTQ_ES_BASE; -+ -+/* PHY Organizationally Unique Identifier (OUI) */ -+#define PHY_OUI_PMC 0x00E004 -+#define PHY_OUI_VITESSE 0x008083 -+#define PHY_OUI_DEFAULT 0xFFFFFF -+ -+unsigned short switchip_phy_read(unsigned int phyaddr, unsigned int regaddr); -+void switchip_phy_write(unsigned int phyaddr, unsigned int regaddr, -+ unsigned short data); -+ -+static int phy_address[2] = {0, 1}; -+static u32 phy_oui; -+static void switchip_mdio_poll_init(void); -+static void _switchip_mdio_poll(struct work_struct *work); -+ -+/* struct workqueue_struct mdio_poll_task; */ -+static struct workqueue_struct *mdio_poll_workqueue; -+DECLARE_DELAYED_WORK(mdio_poll_work, _switchip_mdio_poll); -+static int old_link_status[2] = {-1, -1}; -+ -+/** -+ * Autonegotiation check. -+ * This funtion checks for link changes. If a link change has occured it will -+ * update certain switch registers. -+ */ -+static void _switchip_check_phy_status(int port) -+{ -+ int new_link_status; -+ unsigned short reg1; -+ -+ reg1 = switchip_phy_read(phy_address[port], 1); -+ if ((reg1 == 0xFFFF) || (reg1 == 0x0000)) -+ return; /* no PHY connected */ -+ -+ new_link_status = reg1 & 4; -+ if (old_link_status[port] ^ new_link_status) { -+ /* link status change */ -+ if (!new_link_status) { -+ if (port == 0) -+ es_w32_mask(LTQ_ES_P0_CTL_REG_FLP, 0, p0_ctl); -+ else -+ es_w32_mask(LTQ_ES_P0_CTL_REG_FLP, 0, p1_ctl); -+ -+ /* read again; link bit is latched low! */ -+ reg1 = switchip_phy_read(phy_address[port], 1); -+ new_link_status = reg1 & 4; -+ } -+ -+ if (new_link_status) { -+ unsigned short reg0, reg4, reg5, reg9, reg10; -+ int phy_pause, phy_speed, phy_duplex; -+ int aneg_enable, aneg_cmpt; -+ -+ reg0 = switchip_phy_read(phy_address[port], 0); -+ reg4 = switchip_phy_read(phy_address[port], 4); -+ aneg_enable = reg0 & 0x1000; -+ aneg_cmpt = reg1 & 0x20; -+ -+ if (aneg_enable && aneg_cmpt) { -+ reg5 = switchip_phy_read(phy_address[port], 5); -+ switch (phy_oui) { -+#ifdef CONFIG_LANTIQ_MACH_EASY336 -+ case PHY_OUI_PMC: -+ /* PMC Sierra supports 1Gigabit FD, -+ * only. On successful -+ * auto-negotiation, we are sure this -+ * is what the LP can. */ -+ phy_pause = ((reg4 & reg5) & 0x0080) >> 7; -+ phy_speed = 2; -+ phy_duplex = 1; -+ break; -+#endif -+ case PHY_OUI_VITESSE: -+ case PHY_OUI_DEFAULT: -+ reg9 = switchip_phy_read(phy_address[port], 9); -+ reg10 = switchip_phy_read(phy_address[port], 10); -+ -+ /* Check if advertise and partner -+ * agree on pause */ -+ phy_pause = ((reg4 & reg5) & 0x0400) >> 10; -+ -+ /* Find the best mode both partners -+ * support -+ * Priority: 1GB-FD, 1GB-HD, 100MB-FD, -+ * 100MB-HD, 10MB-FD, 10MB-HD */ -+ phy_speed = ((((reg9<<2) & reg10) -+ & 0x0c00) >> 6) | -+ (((reg4 & reg5) & 0x01e0) >> 5); -+ -+ if (phy_speed >= 0x0020) { -+ phy_speed = 2; -+ phy_duplex = 1; -+ } else if (phy_speed >= 0x0010) { -+ phy_speed = 2; -+ phy_duplex = 0; -+ } else if (phy_speed >= 0x0008) { -+ phy_speed = 1; -+ phy_duplex = 1; -+ } else if (phy_speed >= 0x0004) { -+ phy_speed = 1; -+ phy_duplex = 0; -+ } else if (phy_speed >= 0x0002) { -+ phy_speed = 0; -+ phy_duplex = 1; -+ } else { -+ phy_speed = 0; -+ phy_duplex = 0; -+ } -+ break; -+ default: -+ phy_pause = (reg4 & 0x0400) >> 10; -+ phy_speed = (reg0 & 0x40 ? 2 : (reg0 >> 13)&1); -+ phy_duplex = (reg0 >> 8)&1; -+ break; -+ } -+ } else { -+ /* parallel detection or fixed speed */ -+ phy_pause = (reg4 & 0x0400) >> 10; -+ phy_speed = (reg0 & 0x40 ? 2 : (reg0 >> 13)&1); -+ phy_duplex = (reg0 >> 8)&1; -+ } -+ -+ if (port == 0) { -+ es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0SPD, -+ LTQ_ES_RGMII_CTL_REG_P0SPD_VAL(phy_speed), -+ rgmii_ctl); -+ es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0DUP, -+ LTQ_ES_RGMII_CTL_REG_P0DUP_VAL(phy_duplex), -+ rgmii_ctl); -+ es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0FCE, -+ LTQ_ES_RGMII_CTL_REG_P0FCE_VAL(phy_pause), -+ rgmii_ctl); -+ -+ es_w32_mask(0, LTQ_ES_P0_CTL_REG_FLP, p0_ctl); -+ } else { -+ es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1SPD, -+ LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(phy_speed), -+ rgmii_ctl); -+ es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1DUP, -+ LTQ_ES_RGMII_CTL_REG_P1DUP_VAL(phy_duplex), -+ rgmii_ctl); -+ es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1FCE, -+ LTQ_ES_RGMII_CTL_REG_P0FCE_VAL(phy_pause), -+ rgmii_ctl); -+ -+ es_w32_mask(1, LTQ_ES_P0_CTL_REG_FLP, p1_ctl); -+ } -+ } -+ } -+ old_link_status[port] = new_link_status; -+} -+ -+static void _switchip_mdio_poll(struct work_struct *work) -+{ -+ if (es_r32(sw_gctl0) & LTQ_ES_SW_GCTL0_REG_SE) { -+ _switchip_check_phy_status(0); -+ _switchip_check_phy_status(1); -+ } -+ -+ queue_delayed_work(mdio_poll_workqueue, &mdio_poll_work, HZ/2); -+} -+ -+static void switchip_mdio_poll_init(void) -+{ -+ mdio_poll_workqueue = create_workqueue("SVIP MDIP poll"); -+ INIT_DELAYED_WORK(&mdio_poll_work, _switchip_mdio_poll); -+ -+ queue_delayed_work(mdio_poll_workqueue, &mdio_poll_work, HZ/2); -+ -+} -+ -+unsigned short switchip_phy_read(unsigned int phyaddr, unsigned int regaddr) -+{ -+ /* TODO: protect MDIO access with semaphore */ -+ es_w32(LTQ_ES_MDIO_CTL_REG_MBUSY -+ | LTQ_ES_MDIO_CTL_REG_OP_VAL(2) /* read operation */ -+ | LTQ_ES_MDIO_CTL_REG_PHYAD_VAL(phyaddr) -+ | LTQ_ES_MDIO_CTL_REG_REGAD_VAL(regaddr), mdio_ctl); -+ while (es_r32(mdio_ctl) & LTQ_ES_MDIO_CTL_REG_MBUSY); -+ -+ return es_r32(mdio_data) & 0xFFFF; -+} -+EXPORT_SYMBOL(switchip_phy_read); -+ -+void switchip_phy_write(unsigned int phyaddr, unsigned int regaddr, -+ unsigned short data) -+{ -+ /* TODO: protect MDIO access with semaphore */ -+ es_w32(LTQ_ES_MDIO_CTL_REG_WD_VAL(data) -+ | LTQ_ES_MDIO_CTL_REG_MBUSY -+ | LTQ_ES_MDIO_CTL_REG_OP_VAL(1) /* write operation */ -+ | LTQ_ES_MDIO_CTL_REG_PHYAD_VAL(phyaddr) -+ | LTQ_ES_MDIO_CTL_REG_REGAD_VAL(regaddr), mdio_ctl); -+ while (es_r32(mdio_ctl) & LTQ_ES_MDIO_CTL_REG_MBUSY); -+ -+ return; -+} -+EXPORT_SYMBOL(switchip_phy_write); -+ -+const static u32 switch_reset_offset_000[] = { -+ /*b8000000:*/ 0xffffffff, 0x00000001, 0x00000001, 0x00000003, -+ /*b8000010:*/ 0x04070001, 0x04070001, 0x04070001, 0xffffffff, -+ /*b8000020:*/ 0x00001be8, 0x00001be8, 0x00001be8, 0xffffffff, -+ /*b8000030:*/ 0x00000000, 0x00000000, 0x00080004, 0x00020001, -+ /*b8000040:*/ 0x00000000, 0x00000000, 0x00080004, 0x00020001, -+ /*b8000050:*/ 0x00000000, 0x00000000, 0x00080004, 0x00020001, -+ /*b8000060:*/ 0x00000000, 0x00000000, 0x00081000, 0x001f7777, -+ /*b8000070:*/ 0x00000000, 0x00000000, 0x0c00ac2b, 0x0000fa50, -+ /*b8000080:*/ 0x00001000, 0x00001800, 0x00000000, 0x00000000, -+ /*b8000090:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, -+ /*b80000a0:*/ 0x00000000, 0x00000050, 0x00000010, 0x00000000, -+ /*b80000b0:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, -+ /*b80000c0:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, -+ /*b80000d0:*/ 0xffffffff, 0x00000000, 0x00000000 -+}; -+const static u32 switch_reset_offset_100[] = { -+ /*b8000100:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, -+ /*b8000110:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, -+ /*b8000120:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, -+ /*b8000130:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, -+ /*b8000140:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, -+ /*b8000150:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, -+ /*b8000160:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, -+ /*b8000170:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, -+ /*b8000180:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, -+ /*b8000190:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, -+ /*b80001a0:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, -+ /*b80001b0:*/ 0x00000000, 0x00000000 -+}; -+ -+/* -+ * Switch Reset. -+ */ -+void switchip_reset(void) -+{ -+ volatile unsigned int *reg; -+ volatile unsigned int rdreg; -+ int i; -+ -+ sys1_w32(SYS1_CLKENR_ETHSW, clkenr); -+ asm("sync"); -+ -+ /* disable P0 */ -+ es_w32_mask(0, LTQ_ES_P0_CTL_REG_SPS_VAL(1), p0_ctl); -+ /* disable P1 */ -+ es_w32_mask(0, LTQ_ES_P0_CTL_REG_SPS_VAL(1), p1_ctl); -+ /* disable P2 */ -+ es_w32_mask(0, LTQ_ES_P0_CTL_REG_SPS_VAL(1), p2_ctl); -+ -+ /************************************** -+ * BEGIN: Procedure to clear MAC table -+ **************************************/ -+ for (i = 0; i < 3; i++) { -+ int result; -+ -+ /* check if access engine is available */ -+ while (es_r32(adr_tb_st2) & LTQ_ES_ADR_TB_ST2_REG_BUSY); -+ -+ /* initialise to first address */ -+ es_w32(LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(3) -+ | LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(0), adr_tb_ctl2); -+ -+ /* wait while busy */ -+ while (es_r32(adr_tb_st2) & LTQ_ES_ADR_TB_ST2_REG_BUSY); -+ -+ /* setup the portmap */ -+ es_w32_mask(0, LTQ_ES_ADR_TB_CTL1_REG_PMAP_VAL(1 << i), -+ adr_tb_ctl1); -+ -+ do { -+ /* search for addresses by port */ -+ es_w32(LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(2) -+ | LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(9), adr_tb_ctl2); -+ -+ /* wait while busy */ -+ while (es_r32(adr_tb_st2) & LTQ_ES_ADR_TB_ST2_REG_BUSY); -+ -+ result = LTQ_ES_ADR_TB_ST2_REG_RSLT_GET(es_r32(adr_tb_st2)); -+ if (result == 0x101) { -+ printk(KERN_ERR "%s, cmd error\n", __func__); -+ return; -+ } -+ /* if Command OK, address found... */ -+ if (result == 0) { -+ unsigned char mac[6]; -+ -+ mac[5] = (es_r32(adr_tb_st0) >> 0) & 0xff; -+ mac[4] = (es_r32(adr_tb_st0) >> 8) & 0xff; -+ mac[3] = (es_r32(adr_tb_st0) >> 16) & 0xff; -+ mac[2] = (es_r32(adr_tb_st0) >> 24) & 0xff; -+ mac[1] = (es_r32(adr_tb_st1) >> 0) & 0xff; -+ mac[0] = (es_r32(adr_tb_st1) >> 8) & 0xff; -+ -+ /* setup address */ -+ es_w32((mac[5] << 0) | -+ (mac[4] << 8) | -+ (mac[3] << 16) | -+ (mac[2] << 24), adr_tb_ctl0); -+ es_w32(LTQ_ES_ADR_TB_CTL1_REG_PMAP_VAL(1<= LTQ_ES_ADR_TB_CTL0_REG && -+ reg <= LTQ_ES_ADR_TB_ST2_REG)) -+ continue; -+ -+ if (switch_reset_offset_000[i] != 0xFFFFFFFF) { -+ /* write reset value to register */ -+ *reg = switch_reset_offset_000[i]; -+ /* read register value back */ -+ rdreg = *reg; -+ if (reg == LTQ_ES_SW_GCTL1_REG) -+ rdreg &= ~LTQ_ES_SW_GCTL1_REG_BISTDN; -+ /* compare read value with written one */ -+ if (rdreg != switch_reset_offset_000[i]) { -+ printk(KERN_ERR "%s,%d: reg %08x mismatch " -+ "[has:%08x, expect:%08x]\n", -+ __func__, __LINE__, -+ (unsigned int)reg, rdreg, -+ switch_reset_offset_000[i]); -+ } -+ } -+ reg++; -+ } -+ -+ reg = LTQ_ES_VLAN_FLT0_REG; -+ for (i = 0; i < ARRAY_SIZE(switch_reset_offset_100); i++) { -+ *reg = switch_reset_offset_100[i]; -+ rdreg = *reg; -+ if (rdreg != switch_reset_offset_100[i]) { -+ printk(KERN_ERR "%s,%d: reg %08x mismatch " -+ "[has:%08x, expect:%08x]\n", __func__, __LINE__, -+ (unsigned int)reg, rdreg, -+ switch_reset_offset_100[i]); -+ } -+ reg++; -+ } -+} -+EXPORT_SYMBOL(switchip_reset); -+ -+static u32 get_phy_oui(unsigned char phy_addr) -+{ -+ u32 oui; -+ int i, bit, byte, shift, w; -+ u16 reg_id[2]; -+ -+ /* read PHY identifier registers 1 and 2 */ -+ reg_id[0] = switchip_phy_read(phy_addr, 2); -+ reg_id[1] = switchip_phy_read(phy_addr, 3); -+ -+ oui = 0; -+ w = 1; -+ shift = 7; -+ byte = 1; -+ for (i = 0, bit = 10; i <= 21; i++, bit++) { -+ oui |= ((reg_id[w] & (1<

Parameter NameMeaning
otg_capSpecifies the OTG capabilities. The driver will automatically detect the -+ value for this parameter if none is specified. -+ - 0: HNP and SRP capable (default, if available) -+ - 1: SRP Only capable -+ - 2: No HNP/SRP capable -+
dma_enableSpecifies whether to use slave or DMA mode for accessing the data FIFOs. -+ The driver will automatically detect the value for this parameter if none is -+ specified. -+ - 0: Slave -+ - 1: DMA (default, if available) -+
dma_burst_sizeThe DMA Burst size (applicable only for External DMA Mode). -+ - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32) -+
speedSpecifies the maximum speed of operation in host and device mode. The -+ actual speed depends on the speed of the attached device and the value of -+ phy_type. -+ - 0: High Speed (default) -+ - 1: Full Speed -+
host_support_fs_ls_low_powerSpecifies whether low power mode is supported when attached to a Full -+ Speed or Low Speed device in host mode. -+ - 0: Don't support low power mode (default) -+ - 1: Support low power mode -+
host_ls_low_power_phy_clkSpecifies the PHY clock rate in low power mode when connected to a Low -+ Speed device in host mode. This parameter is applicable only if -+ HOST_SUPPORT_FS_LS_LOW_POWER is enabled. -+ - 0: 48 MHz (default) -+ - 1: 6 MHz -+
enable_dynamic_fifo Specifies whether FIFOs may be resized by the driver software. -+ - 0: Use cC FIFO size parameters -+ - 1: Allow dynamic FIFO sizing (default) -+
data_fifo_sizeTotal number of 4-byte words in the data FIFO memory. This memory -+ includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. -+ - Values: 32 to 32768 (default 8192) -+ -+ Note: The total FIFO memory depth in the FPGA configuration is 8192. -+
dev_rx_fifo_sizeNumber of 4-byte words in the Rx FIFO in device mode when dynamic -+ FIFO sizing is enabled. -+ - Values: 16 to 32768 (default 1064) -+
dev_nperio_tx_fifo_sizeNumber of 4-byte words in the non-periodic Tx FIFO in device mode when -+ dynamic FIFO sizing is enabled. -+ - Values: 16 to 32768 (default 1024) -+
dev_perio_tx_fifo_size_n (n = 1 to 15)Number of 4-byte words in each of the periodic Tx FIFOs in device mode -+ when dynamic FIFO sizing is enabled. -+ - Values: 4 to 768 (default 256) -+
host_rx_fifo_sizeNumber of 4-byte words in the Rx FIFO in host mode when dynamic FIFO -+ sizing is enabled. -+ - Values: 16 to 32768 (default 1024) -+
host_nperio_tx_fifo_sizeNumber of 4-byte words in the non-periodic Tx FIFO in host mode when -+ dynamic FIFO sizing is enabled in the core. -+ - Values: 16 to 32768 (default 1024) -+
host_perio_tx_fifo_sizeNumber of 4-byte words in the host periodic Tx FIFO when dynamic FIFO -+ sizing is enabled. -+ - Values: 16 to 32768 (default 1024) -+
max_transfer_sizeThe maximum transfer size supported in bytes. -+ - Values: 2047 to 65,535 (default 65,535) -+
max_packet_countThe maximum number of packets in a transfer. -+ - Values: 15 to 511 (default 511) -+
host_channelsThe number of host channel registers to use. -+ - Values: 1 to 16 (default 12) -+ -+ Note: The FPGA configuration supports a maximum of 12 host channels. -+
dev_endpointsThe number of endpoints in addition to EP0 available for device mode -+ operations. -+ - Values: 1 to 15 (default 6 IN and OUT) -+ -+ Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in -+ addition to EP0. -+
phy_typeSpecifies the type of PHY interface to use. By default, the driver will -+ automatically detect the phy_type. -+ - 0: Full Speed -+ - 1: UTMI+ (default, if available) -+ - 2: ULPI -+
phy_utmi_widthSpecifies the UTMI+ Data Width. This parameter is applicable for a -+ phy_type of UTMI+. Also, this parameter is applicable only if the -+ OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the -+ core has been configured to work at either data path width. -+ - Values: 8 or 16 bits (default 16) -+
phy_ulpi_ddrSpecifies whether the ULPI operates at double or single data rate. This -+ parameter is only applicable if phy_type is ULPI. -+ - 0: single data rate ULPI interface with 8 bit wide data bus (default) -+ - 1: double data rate ULPI interface with 4 bit wide data bus -+
i2c_enableSpecifies whether to use the I2C interface for full speed PHY. This -+ parameter is only applicable if PHY_TYPE is FS. -+ - 0: Disabled (default) -+ - 1: Enabled -+
otg_en_multiple_tx_fifoSpecifies whether dedicatedto tx fifos are enabled for non periodic IN EPs. -+ The driver will automatically detect the value for this parameter if none is -+ specified. -+ - 0: Disabled -+ - 1: Enabled (default, if available) -+
dev_tx_fifo_size_n (n = 1 to 15)Number of 4-byte words in each of the Tx FIFOs in device mode -+ when dynamic FIFO sizing is enabled. -+ - Values: 4 to 768 (default 256) -+