61 lines
1.6 KiB
Diff
61 lines
1.6 KiB
Diff
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From f281fdccbb3e762d293e6eef7f291a33b84e0f6a Mon Sep 17 00:00:00 2001
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From: Ralf Baechle <ralf@linux-mips.org>
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Date: Thu, 20 Jun 2013 14:56:17 +0200
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Subject: [PATCH 200/215] MIPS: Fix TLBR-use hazards for R2 cores in the TLB
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reload handlers
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MIPS R2 documents state that an execution hazard barrier is needed
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after a TLBR before reading EntryLo.
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Original patch by Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>.
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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Patchwork: https://patchwork.linux-mips.org/patch/5526/
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(cherry picked from commit 73acc7df534ff458a81435178dab3ea037ed6d78)
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---
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arch/mips/mm/tlbex.c | 26 ++++++++++++++++++++++++++
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1 file changed, 26 insertions(+)
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--- a/arch/mips/mm/tlbex.c
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+++ b/arch/mips/mm/tlbex.c
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@@ -1935,6 +1935,19 @@ static void __cpuinit build_r4000_tlb_lo
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uasm_i_nop(&p);
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uasm_i_tlbr(&p);
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+
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+ switch (current_cpu_type()) {
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+ default:
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+ if (cpu_has_mips_r2) {
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+ uasm_i_ehb(&p);
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+
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+ case CPU_CAVIUM_OCTEON:
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+ case CPU_CAVIUM_OCTEON_PLUS:
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+ case CPU_CAVIUM_OCTEON2:
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+ break;
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+ }
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+ }
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+
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/* Examine entrylo 0 or 1 based on ptr. */
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if (use_bbit_insns()) {
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uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
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@@ -1989,6 +2002,19 @@ static void __cpuinit build_r4000_tlb_lo
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uasm_i_nop(&p);
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uasm_i_tlbr(&p);
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+
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+ switch (current_cpu_type()) {
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+ default:
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+ if (cpu_has_mips_r2) {
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+ uasm_i_ehb(&p);
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+
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+ case CPU_CAVIUM_OCTEON:
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+ case CPU_CAVIUM_OCTEON_PLUS:
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+ case CPU_CAVIUM_OCTEON2:
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+ break;
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+ }
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+ }
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+
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/* Examine entrylo 0 or 1 based on ptr. */
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if (use_bbit_insns()) {
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uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
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