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ralink: refresh patches 

Signed-off-by: John Crispin <blogic@openwrt.org>

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@39949 3c298f89-4303-0410-b956-a3cf2f4a3e73
master
John Crispin 2014-03-18 19:21:56 +00:00
parent 694bc2270f
commit de51ae36be
79 changed files with 14550 additions and 7548 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
target/linux/ramips/dts/mt7621.dtsi
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@ -72,8 +72,8 @@
compatible = "ns16550a";
reg = <0xc00 0x100>;
/* interrupt-parent = <&gic>;
interrupts = <26>;*/
interrupt-parent = <&gic>;
interrupts = <26>;
reg-shift = <2>;
reg-io-width = <4>;

445
target/linux/ramips/files/drivers/usb/host/mtk-phy-7621.c
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@ -1,445 +0,0 @@
#include "mtk-phy.h"
#ifdef CONFIG_PROJECT_7621
#include "mtk-phy-7621.h"
//not used on SoC
PHY_INT32 phy_init(struct u3phy_info *info){
return PHY_TRUE;
}
//not used on SoC
PHY_INT32 phy_change_pipe_phase(struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase){
return PHY_TRUE;
}
//--------------------------------------------------------
// Function : fgEyeScanHelper_CheckPtInRegion()
// Description : Check if the test point is in a rectangle region.
// If it is in the rectangle, also check if this point
// is on the multiple of deltaX and deltaY.
// Parameter : strucScanRegion * prEye - the region
// BYTE bX
// BYTE bY
// Return : BYTE - TRUE : This point needs to be tested
// FALSE: This point will be omitted
// Note : First check within the rectangle.
// Secondly, use modulous to check if the point will be tested.
//--------------------------------------------------------
static PHY_INT8 fgEyeScanHelper_CheckPtInRegion(struct strucScanRegion * prEye, PHY_INT8 bX, PHY_INT8 bY)
{
PHY_INT8 fgValid = true;
/// Be careful, the axis origin is on the TOP-LEFT corner.
/// Therefore the top-left point has the minimum X and Y
/// Botton-right point is the maximum X and Y
if ( (prEye->bX_tl <= bX) && (bX <= prEye->bX_br)
&& (prEye->bY_tl <= bY) && (bY <= prEye->bX_br))
{
// With the region, now check whether or not the input test point is
// on the multiples of X and Y
// Do not have to worry about negative value, because we have already
// check the input bX, and bY is within the region.
if ( ((bX - prEye->bX_tl) % (prEye->bDeltaX))
|| ((bY - prEye->bY_tl) % (prEye->bDeltaY)) )
{
// if the division will have remainder, that means
// the input test point is on the multiples of X and Y
fgValid = false;
}
else
{
}
}
else
{
fgValid = false;
}
return fgValid;
}
//--------------------------------------------------------
// Function : EyeScanHelper_RunTest()
// Description : Enable the test, and wait til it is completed
// Parameter : None
// Return : None
// Note : None
//--------------------------------------------------------
static void EyeScanHelper_RunTest(struct u3phy_info *info)
{
DRV_UDELAY(100);
// Disable the test
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 0); //RG_SSUSB_RX_EYE_CNT_EN = 0
DRV_UDELAY(100);
// Run the test
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE_CNT_EN_OFST, RG_SSUSB_EQ_EYE_CNT_EN, 1); //RG_SSUSB_RX_EYE_CNT_EN = 1
DRV_UDELAY(100);
// Wait til it's done
//RGS_SSUSB_RX_EYE_CNT_RDY
while(!U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
, RGS_SSUSB_EQ_EYE_CNT_RDY_OFST, RGS_SSUSB_EQ_EYE_CNT_RDY));
}
//--------------------------------------------------------
// Function : fgEyeScanHelper_CalNextPoint()
// Description : Calcualte the test point for the measurement
// Parameter : None
// Return : BOOL - TRUE : the next point is within the
// boundaryof HW limit
// FALSE: the next point is out of the HW limit
// Note : The next point is obtained by calculating
// from the bottom left of the region rectangle
// and then scanning up until it reaches the upper
// limit. At this time, the x will increment, and
// start scanning downwards until the y hits the
// zero.
//--------------------------------------------------------
static PHY_INT8 fgEyeScanHelper_CalNextPoint(void)
{
if ( ((_bYcurr == MAX_Y) && (_eScanDir == SCAN_DN))
|| ((_bYcurr == MIN_Y) && (_eScanDir == SCAN_UP))
)
{
/// Reaches the limit of Y axis
/// Increment X
_bXcurr++;
_fgXChged = true;
_eScanDir = (_eScanDir == SCAN_UP) ? SCAN_DN : SCAN_UP;
if (_bXcurr > MAX_X)
{
return false;
}
}
else
{
_bYcurr = (_eScanDir == SCAN_DN) ? _bYcurr + 1 : _bYcurr - 1;
_fgXChged = false;
}
return PHY_TRUE;
}
PHY_INT32 eyescan_init(struct u3phy_info *info){
//initial PHY setting
U3PhyWriteField32(((PHY_UINT32)&info->u3phya_regs->rega)
, RG_SSUSB_CDR_EPEN_OFST, RG_SSUSB_CDR_EPEN, 1);
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->phyd_mix3)
, RG_SSUSB_FORCE_CDR_PI_PWD_OFST, RG_SSUSB_FORCE_CDR_PI_PWD, 1);
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
, RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
, RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
return PHY_TRUE;
}
PHY_INT32 phy_eyescan(struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y
, PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt){
PHY_INT32 cOfst = 0;
PHY_UINT8 bIdxX = 0;
PHY_UINT8 bIdxY = 0;
//PHY_INT8 bCnt = 0;
PHY_UINT8 bIdxCycCnt = 0;
PHY_INT8 fgValid;
PHY_INT8 cX;
PHY_INT8 cY;
PHY_UINT8 bExtendCnt;
PHY_INT8 isContinue;
//PHY_INT8 isBreak;
PHY_UINT32 wErr0 = 0, wErr1 = 0;
//PHY_UINT32 temp;
PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
_rEye1.bX_tl = x_t1;
_rEye1.bY_tl = y_t1;
_rEye1.bX_br = x_br;
_rEye1.bY_br = y_br;
_rEye1.bDeltaX = delta_x;
_rEye1.bDeltaY = delta_y;
_rEye2.bX_tl = x_t1;
_rEye2.bY_tl = y_t1;
_rEye2.bX_br = x_br;
_rEye2.bY_br = y_br;
_rEye2.bDeltaX = delta_x;
_rEye2.bDeltaY = delta_y;
_rTestCycle.wEyeCnt = eye_cnt;
_rTestCycle.bNumOfEyeCnt = num_cnt;
_rTestCycle.bNumOfIgnoreCnt = num_ignore_cnt;
_rTestCycle.bPICalEn = PI_cal_en;
_bXcurr = 0;
_bYcurr = 0;
_eScanDir = SCAN_DN;
_fgXChged = false;
printk("x_t1: %x, y_t1: %x, x_br: %x, y_br: %x, delta_x: %x, delta_y: %x, \
eye_cnt: %x, num_cnt: %x, PI_cal_en: %x, num_ignore_cnt: %x\n", \
x_t1, y_t1, x_br, y_br, delta_x, delta_y, eye_cnt, num_cnt, PI_cal_en, num_ignore_cnt);
//force SIGDET to OFF
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
, RG_SSUSB_RX_SIGDET_EN_SEL_OFST, RG_SSUSB_RX_SIGDET_EN_SEL, 1); //RG_SSUSB_RX_SIGDET_SEL = 1
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
, RG_SSUSB_RX_SIGDET_EN_OFST, RG_SSUSB_RX_SIGDET_EN, 0); //RG_SSUSB_RX_SIGDET_EN = 0
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
, RG_SSUSB_EQ_SIGDET_OFST, RG_SSUSB_EQ_SIGDET, 0); //RG_SSUSB_RX_SIGDET = 0
// RX_TRI_DET_EN to Disable
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq3)
, RG_SSUSB_EQ_TRI_DET_EN_OFST, RG_SSUSB_EQ_TRI_DET_EN, 0); //RG_SSUSB_RX_TRI_DET_EN = 0
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, 0); //RG_SSUSB_RX_EYE_XOFFSET = 0
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, 0); //RG_SSUSB_RX_EYE0_Y = 0
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, 0); //RG_SSUSB_RX_EYE1_Y = 0
if (PI_cal_en){
// PI Calibration
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
, RG_SSUSB_RX_PI_CAL_EN_SEL_OFST, RG_SSUSB_RX_PI_CAL_EN_SEL, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_SEL = 1
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
, RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
, RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 1); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 1
DRV_UDELAY(20);
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_bank2_regs->b2_phyd_misc0)
, RG_SSUSB_RX_PI_CAL_EN_OFST, RG_SSUSB_RX_PI_CAL_EN, 0); //RG_SSUSB_RX_PI_CAL_MANUAL_EN = 0
_bPIResult = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon5)
, RGS_SSUSB_EQ_PILPO_OFST, RGS_SSUSB_EQ_PILPO); //read RGS_SSUSB_RX_PILPO
printk(KERN_ERR "PI result: %d\n", _bPIResult);
}
// Read Initial DAC
// Set CYCLE
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye3)
,RG_SSUSB_EQ_EYE_CNT_OFST, RG_SSUSB_EQ_EYE_CNT, eye_cnt); //RG_SSUSB_RX_EYE_CNT
// Eye Monitor Feature
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye1)
, RG_SSUSB_EQ_EYE_MASK_OFST, RG_SSUSB_EQ_EYE_MASK, 0x3ff); //RG_SSUSB_RX_EYE_MASK = 0x3ff
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE_MON_EN_OFST, RG_SSUSB_EQ_EYE_MON_EN, 1); //RG_SSUSB_EYE_MON_EN = 1
// Move X,Y to the top-left corner
for (cOfst = 0; cOfst >= -64; cOfst--)
{
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
,RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
}
for (cOfst = 0; cOfst < 64; cOfst++)
{
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst); //RG_SSUSB_RX_EYE0_Y
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst); //RG_SSUSB_RX_EYE1_Y
}
//ClearErrorResult
for(bIdxCycCnt = 0; bIdxCycCnt < CYCLE_COUNT_MAX; bIdxCycCnt++){
for(bIdxX = 0; bIdxX < ERRCNT_MAX; bIdxX++)
{
for(bIdxY = 0; bIdxY < ERRCNT_MAX; bIdxY++){
pwErrCnt0[bIdxCycCnt][bIdxX][bIdxY] = 0;
pwErrCnt1[bIdxCycCnt][bIdxX][bIdxY] = 0;
}
}
}
isContinue = true;
while(isContinue){
//printk(KERN_ERR "_bXcurr: %d, _bYcurr: %d\n", _bXcurr, _bYcurr);
// The point is within the boundary, then let's check if it is within
// the testing region.
// The point is only test-able if one of the eye region
// includes this point.
fgValid = fgEyeScanHelper_CheckPtInRegion(&_rEye1, _bXcurr, _bYcurr)
|| fgEyeScanHelper_CheckPtInRegion(&_rEye2, _bXcurr, _bYcurr);
// Translate bX and bY to 2's complement from where the origin was on the
// top left corner.
// 0x40 and 0x3F needs a bit of thinking!!!! >"<
cX = (_bXcurr ^ 0x40);
cY = (_bYcurr ^ 0x3F);
// Set X if necessary
if (_fgXChged == true)
{
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cX); //RG_SSUSB_RX_EYE_XOFFSET
}
// Set Y
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cY); //RG_SSUSB_RX_EYE0_Y
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cY); //RG_SSUSB_RX_EYE1_Y
/// Test this point!
if (fgValid){
for (bExtendCnt = 0; bExtendCnt < num_ignore_cnt; bExtendCnt++)
{
//run test
EyeScanHelper_RunTest(info);
}
for (bExtendCnt = 0; bExtendCnt < num_cnt; bExtendCnt++)
{
EyeScanHelper_RunTest(info);
wErr0 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon3)
, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_0);
wErr1 = U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->phya_rx_mon4)
, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1_OFST, RGS_SSUSB_EQ_EYE_MONITOR_ERRCNT_1);
pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr] = wErr0;
pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr] = wErr1;
//EyeScanHelper_GetResult(&_rRes.pwErrCnt0[bCnt], &_rRes.pwErrCnt1[bCnt]);
// printk(KERN_ERR "cnt[%d] cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n"
// , bExtendCnt, _bXcurr, _bYcurr, cX, cY, pwErrCnt0[bExtendCnt][_bXcurr][_bYcurr], pwErrCnt1[bExtendCnt][_bXcurr][_bYcurr]);
}
//printk(KERN_ERR "cur_x,y [0x%x][0x%x], cX,cY [0x%x][0x%x], ErrCnt[%d][%d]\n", _bXcurr, _bYcurr, cX, cY, pwErrCnt0[0][_bXcurr][_bYcurr], pwErrCnt1[0][_bXcurr][_bYcurr]);
}
else{
}
if (fgEyeScanHelper_CalNextPoint() == false){
#if 0
printk(KERN_ERR "Xcurr [0x%x] Ycurr [0x%x]\n", _bXcurr, _bYcurr);
printk(KERN_ERR "XcurrREG [0x%x] YcurrREG [0x%x]\n", cX, cY);
#endif
printk(KERN_ERR "end of eye scan\n");
isContinue = false;
}
}
printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
, U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
, U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
// Move X,Y to the top-left corner
for (cOfst = 63; cOfst >= 0; cOfst--)
{
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET, cOfst); //RG_SSUSB_RX_EYE_XOFFSET
}
for (cOfst = 63; cOfst >= 0; cOfst--)
{
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y, cOfst);
U3PhyWriteField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0)
, RG_SSUSB_EQ_EYE1_Y_OFST, RG_SSUSB_EQ_EYE1_Y, cOfst);
}
printk(KERN_ERR "CurX [0x%x] CurY [0x%x]\n"
, U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE_XOFFSET_OFST, RG_SSUSB_EQ_EYE_XOFFSET)
, U3PhyReadField32(((PHY_UINT32)&info->u3phyd_regs->eq_eye0), RG_SSUSB_EQ_EYE0_Y_OFST, RG_SSUSB_EQ_EYE0_Y));
printk(KERN_ERR "PI result: %d\n", _bPIResult);
printk(KERN_ERR "pwErrCnt0 addr: 0x%x\n", (PHY_UINT32)pwErrCnt0);
printk(KERN_ERR "pwErrCnt1 addr: 0x%x\n", (PHY_UINT32)pwErrCnt1);
return PHY_TRUE;
}
//not used on SoC
PHY_INT32 u2_save_cur_en(struct u3phy_info *info){
return PHY_TRUE;
}
//not used on SoC
PHY_INT32 u2_save_cur_re(struct u3phy_info *info){
return PHY_TRUE;
}
PHY_INT32 u2_slew_rate_calibration(struct u3phy_info *info){
PHY_INT32 i=0;
//PHY_INT32 j=0;
//PHY_INT8 u1SrCalVal = 0;
//PHY_INT8 u1Reg_addr_HSTX_SRCAL_EN;
PHY_INT32 fgRet = 0;
PHY_INT32 u4FmOut = 0;
PHY_INT32 u4Tmp = 0;
//PHY_INT32 temp;
// => RG_USB20_HSTX_SRCAL_EN = 1
// enable HS TX SR calibration
U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
, RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0x1);
DRV_MSLEEP(1);
// => RG_FRCK_EN = 1
// Enable free run clock
U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
, RG_FRCK_EN_OFST, RG_FRCK_EN, 1);
// MT6290 HS signal quality patch
// => RG_CYCLECNT = 400
// Setting cyclecnt =400
U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
, RG_CYCLECNT_OFST, RG_CYCLECNT, 0x400);
// => RG_FREQDET_EN = 1
// Enable frequency meter
U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
, RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0x1);
// wait for FM detection done, set 10ms timeout
for(i=0; i<10; i++){
// => u4FmOut = USB_FM_OUT
// read FM_OUT
u4FmOut = U3PhyReadReg32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr0));
printk("FM_OUT value: u4FmOut = %d(0x%08X)\n", u4FmOut, u4FmOut);
// check if FM detection done
if (u4FmOut != 0)
{
fgRet = 0;
printk("FM detection done! loop = %d\n", i);
break;
}
fgRet = 1;
DRV_MSLEEP(1);
}
// => RG_FREQDET_EN = 0
// disable frequency meter
U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmcr0)
, RG_FREQDET_EN_OFST, RG_FREQDET_EN, 0);
// => RG_FRCK_EN = 0
// disable free run clock
U3PhyWriteField32(((PHY_UINT32)&info->sifslv_fm_regs->fmmonr1)
, RG_FRCK_EN_OFST, RG_FRCK_EN, 0);
// => RG_USB20_HSTX_SRCAL_EN = 0
// disable HS TX SR calibration
U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
, RG_USB20_HSTX_SRCAL_EN_OFST, RG_USB20_HSTX_SRCAL_EN, 0);
DRV_MSLEEP(1);
if(u4FmOut == 0){
U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
, RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, 0x4);
fgRet = 1;
}
else{
// set reg = (1024/FM_OUT) * 25 * 0.028 (round to the nearest digits)
u4Tmp = (((1024 * 25 * U2_SR_COEF_7621) / u4FmOut) + 500) / 1000;
printk("SR calibration value u1SrCalVal = %d\n", (PHY_UINT8)u4Tmp);
U3PhyWriteField32(((PHY_UINT32)&info->u2phy_regs->u2phyacr0)
, RG_USB20_HSTX_SRCTRL_OFST, RG_USB20_HSTX_SRCTRL, u4Tmp);
}
return fgRet;
}
#endif

2871
target/linux/ramips/files/drivers/usb/host/mtk-phy-7621.h
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File diff suppressed because it is too large Load Diff

58
target/linux/ramips/files/drivers/usb/host/mtk-phy-ahb.c
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@ -1,58 +0,0 @@
#include "mtk-phy.h"
#ifdef CONFIG_U3D_HAL_SUPPORT
#include "mu3d_hal_osal.h"
#endif
#ifdef CONFIG_U3_PHY_AHB_SUPPORT
#include <linux/gfp.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#ifndef CONFIG_U3D_HAL_SUPPORT
#define os_writel(addr,data) {\
(*((volatile PHY_UINT32*)(addr)) = data);\
}
#define os_readl(addr) *((volatile PHY_UINT32*)(addr))
#define os_writelmsk(addr, data, msk) \
{ os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk)))); \
}
#define os_setmsk(addr, msk) \
{ os_writel(addr, os_readl(addr) | msk); \
}
#define os_clrmsk(addr, msk) \
{ os_writel(addr, os_readl(addr) &~ msk); \
}
/*msk the data first, then umsk with the umsk.*/
#define os_writelmskumsk(addr, data, msk, umsk) \
{\
os_writel(addr, ((os_readl(addr) & ~(msk)) | ((data) & (msk))) & (umsk));\
}
#endif
PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data)
{
os_writel(addr, data);
return 0;
}
PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr)
{
return os_readl(addr);
}
PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data)
{
os_writelmsk(addr&0xfffffffc, data<<((addr%4)*8), 0xff<<((addr%4)*8));
return 0;
}
PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr)
{
return ((os_readl(addr)>>((addr%4)*8))&0xff);
}
#endif

102
target/linux/ramips/files/drivers/usb/host/mtk-phy.c
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@ -1,102 +0,0 @@
#include <linux/gfp.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#define U3_PHY_LIB
#include "mtk-phy.h"
#ifdef CONFIG_PROJECT_7621
#include "mtk-phy-7621.h"
#endif
#ifdef CONFIG_PROJECT_PHY
static struct u3phy_operator project_operators = {
.init = phy_init,
.change_pipe_phase = phy_change_pipe_phase,
.eyescan_init = eyescan_init,
.eyescan = phy_eyescan,
.u2_slew_rate_calibration = u2_slew_rate_calibration,
};
#endif
PHY_INT32 u3phy_init(){
#ifndef CONFIG_PROJECT_PHY
PHY_INT32 u3phy_version;
#endif
if(u3phy != NULL){
return PHY_TRUE;
}
u3phy = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
u3phy_p1 = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
#endif
#ifdef CONFIG_U3_PHY_GPIO_SUPPORT
u3phy->phyd_version_addr = 0x2000e4;
#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
u3phy_p1->phyd_version_addr = 0x2000e4;
#endif
#else
u3phy->phyd_version_addr = U3_PHYD_B2_BASE + 0xe4;
#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
u3phy_p1->phyd_version_addr = U3_PHYD_B2_BASE_P1 + 0xe4;
#endif
#endif
#ifdef CONFIG_PROJECT_PHY
u3phy->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE;
u3phy->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE;
u3phy->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE;
u3phy->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE;
u3phy->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE;
u3phy->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
u3phy->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
u3phy_ops = &project_operators;
#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
u3phy_p1->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE_P1;
u3phy_p1->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE_P1;
u3phy_p1->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE_P1;
u3phy_p1->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE_P1;
u3phy_p1->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE_P1;
u3phy_p1->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
u3phy_p1->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
#endif
#endif
return PHY_TRUE;
}
PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
PHY_INT8 cur_value;
PHY_INT8 new_value;
cur_value = U3PhyReadReg8(addr);
new_value = (cur_value & (~mask)) | (value << offset);
//udelay(i2cdelayus);
U3PhyWriteReg8(addr, new_value);
return PHY_TRUE;
}
PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
PHY_INT32 cur_value;
PHY_INT32 new_value;
cur_value = U3PhyReadReg32(addr);
new_value = (cur_value & (~mask)) | ((value << offset) & mask);
U3PhyWriteReg32(addr, new_value);
//DRV_MDELAY(100);
return PHY_TRUE;
}
PHY_INT32 U3PhyReadField8(PHY_INT32 addr,PHY_INT32 offset,PHY_INT32 mask){
return ((U3PhyReadReg8(addr) & mask) >> offset);
}
PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask){
return ((U3PhyReadReg32(addr) & mask) >> offset);
}

179
target/linux/ramips/files/drivers/usb/host/mtk-phy.h
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@ -1,179 +0,0 @@
#ifndef __MTK_PHY_NEW_H
#define __MTK_PHY_NEW_H
//#define CONFIG_U3D_HAL_SUPPORT
/* include system library */
#include <linux/gfp.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/delay.h>
/* Choose PHY R/W implementation */
//#define CONFIG_U3_PHY_GPIO_SUPPORT //SW I2C implemented by GPIO
#define CONFIG_U3_PHY_AHB_SUPPORT //AHB, only on SoC
/* Choose PHY version */
//Select your project by defining one of the followings
#define CONFIG_PROJECT_7621 //7621
#define CONFIG_PROJECT_PHY
/* BASE ADDRESS DEFINE, should define this on ASIC */
#define PHY_BASE 0xBE1D0000
#define SIFSLV_FM_FEG_BASE (PHY_BASE+0x100)
#define SIFSLV_CHIP_BASE (PHY_BASE+0x700)
#define U2_PHY_BASE (PHY_BASE+0x800)
#define U3_PHYD_BASE (PHY_BASE+0x900)
#define U3_PHYD_B2_BASE (PHY_BASE+0xa00)
#define U3_PHYA_BASE (PHY_BASE+0xb00)
#define U3_PHYA_DA_BASE (PHY_BASE+0xc00)
#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
#define SIFSLV_FM_FEG_BASE_P1 (PHY_BASE+0x100)
#define SIFSLV_CHIP_BASE_P1 (PHY_BASE+0x700)
#define U2_PHY_BASE_P1 (PHY_BASE+0x1000)
#define U3_PHYD_BASE_P1 (PHY_BASE+0x1100)
#define U3_PHYD_B2_BASE_P1 (PHY_BASE+0x1200)
#define U3_PHYA_BASE_P1 (PHY_BASE+0x1300)
#define U3_PHYA_DA_BASE_P1 (PHY_BASE+0x1400)
#endif
/*
0x00000100 MODULE ssusb_sifslv_fmreg ssusb_sifslv_fmreg
0x00000700 MODULE ssusb_sifslv_ippc ssusb_sifslv_ippc
0x00000800 MODULE ssusb_sifslv_u2phy_com ssusb_sifslv_u2_phy_com_T28
0x00000900 MODULE ssusb_sifslv_u3phyd ssusb_sifslv_u3phyd_T28
0x00000a00 MODULE ssusb_sifslv_u3phyd_bank2 ssusb_sifslv_u3phyd_bank2_T28
0x00000b00 MODULE ssusb_sifslv_u3phya ssusb_sifslv_u3phya_T28
0x00000c00 MODULE ssusb_sifslv_u3phya_da ssusb_sifslv_u3phya_da_T28
*/
/* TYPE DEFINE */
typedef unsigned int PHY_UINT32;
typedef int PHY_INT32;
typedef unsigned short PHY_UINT16;
typedef short PHY_INT16;
typedef unsigned char PHY_UINT8;
typedef char PHY_INT8;
typedef PHY_UINT32 __bitwise PHY_LE32;
/* CONSTANT DEFINE */
#define PHY_FALSE 0
#define PHY_TRUE 1
/* MACRO DEFINE */
#define DRV_WriteReg32(addr,data) ((*(volatile PHY_UINT32 *)(addr)) = (unsigned long)(data))
#define DRV_Reg32(addr) (*(volatile PHY_UINT32 *)(addr))
#define DRV_MDELAY mdelay
#define DRV_MSLEEP msleep
#define DRV_UDELAY udelay
#define DRV_USLEEP usleep
/* PHY FUNCTION DEFINE, implemented in platform files, ex. ahb, gpio */
PHY_INT32 U3PhyWriteReg32(PHY_UINT32 addr, PHY_UINT32 data);
PHY_INT32 U3PhyReadReg32(PHY_UINT32 addr);
PHY_INT32 U3PhyWriteReg8(PHY_UINT32 addr, PHY_UINT8 data);
PHY_INT8 U3PhyReadReg8(PHY_UINT32 addr);
/* PHY GENERAL USAGE FUNC, implemented in mtk-phy.c */
PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value);
PHY_INT32 U3PhyReadField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask);
struct u3phy_info {
PHY_INT32 phy_version;
PHY_INT32 phyd_version_addr;
#ifdef CONFIG_PROJECT_PHY
struct u2phy_reg *u2phy_regs;
struct u3phya_reg *u3phya_regs;
struct u3phya_da_reg *u3phya_da_regs;
struct u3phyd_reg *u3phyd_regs;
struct u3phyd_bank2_reg *u3phyd_bank2_regs;
struct sifslv_chip_reg *sifslv_chip_regs;
struct sifslv_fm_feg *sifslv_fm_regs;
#endif
};
struct u3phy_operator {
PHY_INT32 (*init) (struct u3phy_info *info);
PHY_INT32 (*change_pipe_phase) (struct u3phy_info *info, PHY_INT32 phy_drv, PHY_INT32 pipe_phase);
PHY_INT32 (*eyescan_init) (struct u3phy_info *info);
PHY_INT32 (*eyescan) (struct u3phy_info *info, PHY_INT32 x_t1, PHY_INT32 y_t1, PHY_INT32 x_br, PHY_INT32 y_br, PHY_INT32 delta_x, PHY_INT32 delta_y, PHY_INT32 eye_cnt, PHY_INT32 num_cnt, PHY_INT32 PI_cal_en, PHY_INT32 num_ignore_cnt);
PHY_INT32 (*u2_save_current_entry) (struct u3phy_info *info);
PHY_INT32 (*u2_save_current_recovery) (struct u3phy_info *info);
PHY_INT32 (*u2_slew_rate_calibration) (struct u3phy_info *info);
};
#ifdef U3_PHY_LIB
#define AUTOEXT
#else
#define AUTOEXT extern
#endif
AUTOEXT struct u3phy_info *u3phy;
AUTOEXT struct u3phy_info *u3phy_p1;
AUTOEXT struct u3phy_operator *u3phy_ops;
/*********eye scan required*********/
#define LO_BYTE(x) ((PHY_UINT8)((x) & 0xFF))
#define HI_BYTE(x) ((PHY_UINT8)(((x) & 0xFF00) >> 8))
typedef enum
{
SCAN_UP,
SCAN_DN
} enumScanDir;
struct strucScanRegion
{
PHY_INT8 bX_tl;
PHY_INT8 bY_tl;
PHY_INT8 bX_br;
PHY_INT8 bY_br;
PHY_INT8 bDeltaX;
PHY_INT8 bDeltaY;
};
struct strucTestCycle
{
PHY_UINT16 wEyeCnt;
PHY_INT8 bNumOfEyeCnt;
PHY_INT8 bPICalEn;
PHY_INT8 bNumOfIgnoreCnt;
};
#define ERRCNT_MAX 128
#define CYCLE_COUNT_MAX 15
/// the map resolution is 128 x 128 pts
#define MAX_X 127
#define MAX_Y 127
#define MIN_X 0
#define MIN_Y 0
PHY_INT32 u3phy_init(void);
AUTOEXT struct strucScanRegion _rEye1;
AUTOEXT struct strucScanRegion _rEye2;
AUTOEXT struct strucTestCycle _rTestCycle;
AUTOEXT PHY_UINT8 _bXcurr;
AUTOEXT PHY_UINT8 _bYcurr;
AUTOEXT enumScanDir _eScanDir;
AUTOEXT PHY_INT8 _fgXChged;
AUTOEXT PHY_INT8 _bPIResult;
/* use local variable instead to save memory use */
#if 0
AUTOEXT PHY_UINT32 pwErrCnt0[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
AUTOEXT PHY_UINT32 pwErrCnt1[CYCLE_COUNT_MAX][ERRCNT_MAX][ERRCNT_MAX];
#endif
/***********************************/
#endif

115
target/linux/ramips/files/drivers/usb/host/xhci-mtk-power.c
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@ -1,115 +0,0 @@
#include "xhci-mtk.h"
#include "xhci-mtk-power.h"
#include "xhci.h"
#include <linux/kernel.h> /* printk() */
#include <linux/slab.h>
#include <linux/delay.h>
static int g_num_u3_port;
static int g_num_u2_port;
void enableXhciAllPortPower(struct xhci_hcd *xhci){
int i;
u32 port_id, temp;
u32 __iomem *addr;
g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
for(i=1; i<=g_num_u3_port; i++){
port_id=i;
addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
temp = xhci_readl(xhci, addr);
temp = xhci_port_state_to_neutral(temp);
temp |= PORT_POWER;
xhci_writel(xhci, temp, addr);
}
for(i=1; i<=g_num_u2_port; i++){
port_id=i+g_num_u3_port;
addr = &xhci->op_regs->port_status_base + NUM_PORT_REGS*(port_id-1 & 0xff);
temp = xhci_readl(xhci, addr);
temp = xhci_port_state_to_neutral(temp);
temp |= PORT_POWER;
xhci_writel(xhci, temp, addr);
}
}
void enableAllClockPower(){
int i;
u32 temp;
g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
//2. Enable xHC
writel(readl(SSUSB_IP_PW_CTRL) | (SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
writel(readl(SSUSB_IP_PW_CTRL) & (~SSUSB_IP_SW_RST), SSUSB_IP_PW_CTRL);
writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
//1. Enable target ports
for(i=0; i<g_num_u3_port; i++){
temp = readl(SSUSB_U3_CTRL(i));
temp = temp & (~SSUSB_U3_PORT_PDN) & (~SSUSB_U3_PORT_DIS);
writel(temp, SSUSB_U3_CTRL(i));
}
for(i=0; i<g_num_u2_port; i++){
temp = readl(SSUSB_U2_CTRL(i));
temp = temp & (~SSUSB_U2_PORT_PDN) & (~SSUSB_U2_PORT_DIS);
writel(temp, SSUSB_U2_CTRL(i));
}
msleep(100);
}
//(X)disable clock/power of a port
//(X)if all ports are disabled, disable IP ctrl power
//disable all ports and IP clock/power, this is just mention HW that the power/clock of port
//and IP could be disable if suspended.
//If doesn't not disable all ports at first, the IP clock/power will never be disabled
//(some U2 and U3 ports are binded to the same connection, that is, they will never enter suspend at the same time
//port_index: port number
//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
void disablePortClockPower(void){
int i;
u32 temp;
g_num_u3_port = SSUSB_U3_PORT_NUM(readl(SSUSB_IP_CAP));
g_num_u2_port = SSUSB_U2_PORT_NUM(readl(SSUSB_IP_CAP));
for(i=0; i<g_num_u3_port; i++){
temp = readl(SSUSB_U3_CTRL(i));
temp = temp | (SSUSB_U3_PORT_PDN);
writel(temp, SSUSB_U3_CTRL(i));
}
for(i=0; i<g_num_u2_port; i++){
temp = readl(SSUSB_U2_CTRL(i));
temp = temp | (SSUSB_U2_PORT_PDN);
writel(temp, SSUSB_U2_CTRL(i));
}
writel(readl(SSUSB_IP_PW_CTRL_1) | (SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
}
//if IP ctrl power is disabled, enable it
//enable clock/power of a port
//port_index: port number
//port_rev: 0x2 - USB2.0, 0x3 - USB3.0 (SuperSpeed)
void enablePortClockPower(int port_index, int port_rev){
int i;
u32 temp;
writel(readl(SSUSB_IP_PW_CTRL_1) & (~SSUSB_IP_PDN), SSUSB_IP_PW_CTRL_1);
if(port_rev == 0x3){
temp = readl(SSUSB_U3_CTRL(port_index));
temp = temp & (~SSUSB_U3_PORT_PDN);
writel(temp, SSUSB_U3_CTRL(port_index));
}
else if(port_rev == 0x2){
temp = readl(SSUSB_U2_CTRL(port_index));
temp = temp & (~SSUSB_U2_PORT_PDN);
writel(temp, SSUSB_U2_CTRL(port_index));
}
}

13
target/linux/ramips/files/drivers/usb/host/xhci-mtk-power.h
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@ -1,13 +0,0 @@
#ifndef _XHCI_MTK_POWER_H
#define _XHCI_MTK_POWER_H
#include <linux/usb.h>
#include "xhci.h"
#include "xhci-mtk.h"
void enableXhciAllPortPower(struct xhci_hcd *xhci);
void enableAllClockPower(void);
void disablePortClockPower(void);
void enablePortClockPower(int port_index, int port_rev);
#endif

608
target/linux/ramips/files/drivers/usb/host/xhci-mtk-scheduler.c
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@ -1,608 +0,0 @@
#include "xhci-mtk-scheduler.h"
#include <linux/kernel.h> /* printk() */
static struct sch_ep **ss_out_eps[MAX_EP_NUM];
static struct sch_ep **ss_in_eps[MAX_EP_NUM];
static struct sch_ep **hs_eps[MAX_EP_NUM]; //including tt isoc
static struct sch_ep **tt_intr_eps[MAX_EP_NUM];
int mtk_xhci_scheduler_init(void){
int i;
for(i=0; i<MAX_EP_NUM; i++){
ss_out_eps[i] = NULL;
}
for(i=0; i<MAX_EP_NUM; i++){
ss_in_eps[i] = NULL;
}
for(i=0; i<MAX_EP_NUM; i++){
hs_eps[i] = NULL;
}
for(i=0; i<MAX_EP_NUM; i++){
tt_intr_eps[i] = NULL;
}
return 0;
}
int add_sch_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
, int mult, int offset, int repeat, int pkts, int cs_count, int burst_mode
, int bw_cost, mtk_u32 *ep, struct sch_ep *tmp_ep){
struct sch_ep **ep_array;
int i;
if(is_in && dev_speed == USB_SPEED_SUPER ){
ep_array = (struct sch_ep **)ss_in_eps;
}
else if(dev_speed == USB_SPEED_SUPER){
ep_array = (struct sch_ep **)ss_out_eps;
}
else if(dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)){
ep_array = (struct sch_ep **)hs_eps;
}
else{
ep_array = (struct sch_ep **)tt_intr_eps;
}
for(i=0; i<MAX_EP_NUM; i++){
if(ep_array[i] == NULL){
tmp_ep->dev_speed = dev_speed;
tmp_ep->isTT = isTT;
tmp_ep->is_in = is_in;
tmp_ep->ep_type = ep_type;
tmp_ep->maxp = maxp;
tmp_ep->interval = interval;
tmp_ep->burst = burst;
tmp_ep->mult = mult;
tmp_ep->offset = offset;
tmp_ep->repeat = repeat;
tmp_ep->pkts = pkts;
tmp_ep->cs_count = cs_count;
tmp_ep->burst_mode = burst_mode;
tmp_ep->bw_cost = bw_cost;
tmp_ep->ep = ep;
ep_array[i] = tmp_ep;
return SCH_SUCCESS;
}
}
return SCH_FAIL;
}
int count_ss_bw(int is_in, int ep_type, int maxp, int interval, int burst, int mult, int offset, int repeat
, int td_size){
int i, j, k;
int bw_required[3];
int final_bw_required;
int bw_required_per_repeat;
int tmp_bw_required;
struct sch_ep *cur_sch_ep;
struct sch_ep **ep_array;
int cur_offset;
int cur_ep_offset;
int tmp_offset;
int tmp_interval;
int ep_offset;
int ep_interval;
int ep_repeat;
int ep_mult;
if(is_in){
ep_array = (struct sch_ep **)ss_in_eps;
}
else{
ep_array = (struct sch_ep **)ss_out_eps;
}
bw_required[0] = 0;
bw_required[1] = 0;
bw_required[2] = 0;
if(repeat == 0){
final_bw_required = 0;
for(i=0; i<MAX_EP_NUM; i++){
cur_sch_ep = ep_array[i];
if(cur_sch_ep == NULL){
continue;
}
ep_interval = cur_sch_ep->interval;
ep_offset = cur_sch_ep->offset;
if(cur_sch_ep->repeat == 0){
if(ep_interval >= interval){
tmp_offset = ep_offset + ep_interval - offset;
tmp_interval = interval;
}
else{
tmp_offset = offset + interval - ep_offset;
tmp_interval = ep_interval;
}
if(tmp_offset % tmp_interval == 0){
final_bw_required += cur_sch_ep->bw_cost;
}
}
else{
ep_repeat = cur_sch_ep->repeat;
ep_mult = cur_sch_ep->mult;
for(k=0; k<=ep_mult; k++){
cur_ep_offset = ep_offset+(k*ep_mult);
if(ep_interval >= interval){
tmp_offset = cur_ep_offset + ep_interval - offset;
tmp_interval = interval;
}
else{
tmp_offset = offset + interval - cur_ep_offset;
tmp_interval = ep_interval;
}
if(tmp_offset % tmp_interval == 0){
final_bw_required += cur_sch_ep->bw_cost;
break;
}
}
}
}
final_bw_required += td_size;
}
else{
bw_required_per_repeat = maxp * (burst+1);
for(j=0; j<=mult; j++){
tmp_bw_required = 0;
cur_offset = offset+(j*repeat);
for(i=0; i<MAX_EP_NUM; i++){
cur_sch_ep = ep_array[i];
if(cur_sch_ep == NULL){
continue;
}
ep_interval = cur_sch_ep->interval;
ep_offset = cur_sch_ep->offset;
if(cur_sch_ep->repeat == 0){
if(ep_interval >= interval){
tmp_offset = ep_offset + ep_interval - cur_offset;
tmp_interval = interval;
}
else{
tmp_offset = cur_offset + interval - ep_offset;
tmp_interval = ep_interval;
}
if(tmp_offset % tmp_interval == 0){
tmp_bw_required += cur_sch_ep->bw_cost;
}
}
else{
ep_repeat = cur_sch_ep->repeat;
ep_mult = cur_sch_ep->mult;
for(k=0; k<=ep_mult; k++){
cur_ep_offset = ep_offset+(k*ep_repeat);
if(ep_interval >= interval){
tmp_offset = cur_ep_offset + ep_interval - cur_offset;
tmp_interval = interval;
}
else{
tmp_offset = cur_offset + interval - cur_ep_offset;
tmp_interval = ep_interval;
}
if(tmp_offset % tmp_interval == 0){
tmp_bw_required += cur_sch_ep->bw_cost;
break;
}
}
}
}
bw_required[j] = tmp_bw_required;
}
final_bw_required = SS_BW_BOUND;
for(j=0; j<=mult; j++){
if(bw_required[j] < final_bw_required){
final_bw_required = bw_required[j];
}
}
final_bw_required += bw_required_per_repeat;
}
return final_bw_required;
}
int count_hs_bw(int ep_type, int maxp, int interval, int offset, int td_size){
int i;
int bw_required;
struct sch_ep *cur_sch_ep;
int tmp_offset;
int tmp_interval;
int ep_offset;
int ep_interval;
int cur_tt_isoc_interval; //for isoc tt check
bw_required = 0;
for(i=0; i<MAX_EP_NUM; i++){
cur_sch_ep = (struct sch_ep *)hs_eps[i];
if(cur_sch_ep == NULL){
continue;
}
ep_offset = cur_sch_ep->offset;
ep_interval = cur_sch_ep->interval;
if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
cur_tt_isoc_interval = ep_interval<<3;
if(ep_interval >= interval){
tmp_offset = ep_offset + cur_tt_isoc_interval - offset;
tmp_interval = interval;
}
else{
tmp_offset = offset + interval - ep_offset;
tmp_interval = cur_tt_isoc_interval;
}
if(cur_sch_ep->is_in){
if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
bw_required += 188;
}
}
else{
if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
bw_required += 188;
}
}
}
else{
if(ep_interval >= interval){
tmp_offset = ep_offset + ep_interval - offset;
tmp_interval = interval;
}
else{
tmp_offset = offset + interval - ep_offset;
tmp_interval = ep_interval;
}
if(tmp_offset%tmp_interval == 0){
bw_required += cur_sch_ep->bw_cost;
}
}
}
bw_required += td_size;
return bw_required;
}
int count_tt_isoc_bw(int is_in, int maxp, int interval, int offset, int td_size){
char is_cs;
int mframe_idx, frame_idx, s_frame, s_mframe, cur_mframe;
int bw_required, max_bw;
int ss_cs_count;
int cs_mframe;
int max_frame;
int i,j;
struct sch_ep *cur_sch_ep;
int ep_offset;
int ep_interval;
int ep_cs_count;
int tt_isoc_interval; //for isoc tt check
int cur_tt_isoc_interval; //for isoc tt check
int tmp_offset;
int tmp_interval;
is_cs = 0;
tt_isoc_interval = interval<<3; //frame to mframe
if(is_in){
is_cs = 1;
}
s_frame = offset/8;
s_mframe = offset%8;
ss_cs_count = (maxp + (188 - 1))/188;
if(is_cs){
cs_mframe = offset%8 + 2 + ss_cs_count;
if (cs_mframe <= 6)
ss_cs_count += 2;
else if (cs_mframe == 7)
ss_cs_count++;
else if (cs_mframe > 8)
return -1;
}
max_bw = 0;
if(is_in){
i=2;
}
for(cur_mframe = offset+i; i<ss_cs_count; cur_mframe++, i++){
bw_required = 0;
for(j=0; j<MAX_EP_NUM; j++){
cur_sch_ep = (struct sch_ep *)hs_eps[j];
if(cur_sch_ep == NULL){
continue;
}
ep_offset = cur_sch_ep->offset;
ep_interval = cur_sch_ep->interval;
if(cur_sch_ep->isTT && cur_sch_ep->ep_type == USB_EP_ISOC){
//isoc tt
//check if mframe offset overlap
//if overlap, add 188 to the bw
cur_tt_isoc_interval = ep_interval<<3;
if(cur_tt_isoc_interval >= tt_isoc_interval){
tmp_offset = (ep_offset+cur_tt_isoc_interval) - cur_mframe;
tmp_interval = tt_isoc_interval;
}
else{
tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
tmp_interval = cur_tt_isoc_interval;
}
if(cur_sch_ep->is_in){
if((tmp_offset%tmp_interval >=2) && (tmp_offset%tmp_interval <= cur_sch_ep->cs_count)){
bw_required += 188;
}
}
else{
if(tmp_offset%tmp_interval <= cur_sch_ep->cs_count){
bw_required += 188;
}
}
}
else if(cur_sch_ep->ep_type == USB_EP_INT || cur_sch_ep->ep_type == USB_EP_ISOC){
//check if mframe
if(ep_interval >= tt_isoc_interval){
tmp_offset = (ep_offset+ep_interval) - cur_mframe;
tmp_interval = tt_isoc_interval;
}
else{
tmp_offset = (cur_mframe+tt_isoc_interval) - ep_offset;
tmp_interval = ep_interval;
}
if(tmp_offset%tmp_interval == 0){
bw_required += cur_sch_ep->bw_cost;
}
}
}
bw_required += 188;
if(bw_required > max_bw){
max_bw = bw_required;
}
}
return max_bw;
}
int count_tt_intr_bw(int interval, int frame_offset){
//check all eps in tt_intr_eps
int ret;
int i,j;
int ep_offset;
int ep_interval;
int tmp_offset;
int tmp_interval;
ret = SCH_SUCCESS;
struct sch_ep *cur_sch_ep;
for(i=0; i<MAX_EP_NUM; i++){
cur_sch_ep = (struct sch_ep *)tt_intr_eps[i];
if(cur_sch_ep == NULL){
continue;
}
ep_offset = cur_sch_ep->offset;
ep_interval = cur_sch_ep->interval;
if(ep_interval >= interval){
tmp_offset = ep_offset + ep_interval - frame_offset;
tmp_interval = interval;
}
else{
tmp_offset = frame_offset + interval - ep_offset;
tmp_interval = ep_interval;
}
if(tmp_offset%tmp_interval==0){
return SCH_FAIL;
}
}
return SCH_SUCCESS;
}
struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep){
int i;
struct sch_ep **ep_array;
struct sch_ep *cur_ep;
if (is_in && dev_speed == USB_SPEED_SUPER) {
ep_array = (struct sch_ep **)ss_in_eps;
}
else if (dev_speed == USB_SPEED_SUPER) {
ep_array = (struct sch_ep **)ss_out_eps;
}
else if (dev_speed == USB_SPEED_HIGH || (isTT && ep_type == USB_EP_ISOC)) {
ep_array = (struct sch_ep **)hs_eps;
}
else {
ep_array = (struct sch_ep **)tt_intr_eps;
}
for (i = 0; i < MAX_EP_NUM; i++) {
cur_ep = (struct sch_ep *)ep_array[i];
if(cur_ep != NULL && cur_ep->ep == ep){
ep_array[i] = NULL;
return cur_ep;
}
}
return NULL;
}
int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
, int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep){
mtk_u32 bPkts = 0;
mtk_u32 bCsCount = 0;
mtk_u32 bBm = 1;
mtk_u32 bOffset = 0;
mtk_u32 bRepeat = 0;
int ret;
struct mtk_xhci_ep_ctx *temp_ep_ctx;
int td_size;
int mframe_idx, frame_idx;
int bw_cost;
int cur_bw, best_bw, best_bw_idx,repeat, max_repeat, best_bw_repeat;
int cur_offset, cs_mframe;
int break_out;
int frame_interval;
printk(KERN_ERR "add_ep parameters, dev_speed %d, is_in %d, isTT %d, ep_type %d, maxp %d, interval %d, burst %d, mult %d, ep 0x%x, ep_ctx 0x%x, sch_ep 0x%x\n", dev_speed, is_in, isTT, ep_type, maxp
, interval, burst, mult, ep, ep_ctx, sch_ep);
if(isTT && ep_type == USB_EP_INT && ((dev_speed == USB_SPEED_LOW) || (dev_speed == USB_SPEED_FULL))){
frame_interval = interval >> 3;
for(frame_idx=0; frame_idx<frame_interval; frame_idx++){
printk(KERN_ERR "check tt_intr_bw interval %d, frame_idx %d\n", frame_interval, frame_idx);
if(count_tt_intr_bw(frame_interval, frame_idx) == SCH_SUCCESS){
printk(KERN_ERR "check OK............\n");
bOffset = frame_idx<<3;
bPkts = 1;
bCsCount = 3;
bw_cost = maxp;
bRepeat = 0;
if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, frame_interval, burst, mult
, bOffset, bRepeat, bPkts, bCsCount, bBm, maxp, ep, sch_ep) == SCH_FAIL){
return SCH_FAIL;
}
ret = SCH_SUCCESS;
break;
}
}
}
else if(isTT && ep_type == USB_EP_ISOC){
best_bw = HS_BW_BOUND;
best_bw_idx = -1;
cur_bw = 0;
td_size = maxp;
break_out = 0;
frame_interval = interval>>3;
for(frame_idx=0; frame_idx<frame_interval && !break_out; frame_idx++){
for(mframe_idx=0; mframe_idx<8; mframe_idx++){
cur_offset = (frame_idx*8) + mframe_idx;
cur_bw = count_tt_isoc_bw(is_in, maxp, frame_interval, cur_offset, td_size);
if(cur_bw > 0 && cur_bw < best_bw){
best_bw_idx = cur_offset;
best_bw = cur_bw;
if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
break_out = 1;
break;
}
}
}
}
if(best_bw_idx == -1){
return SCH_FAIL;
}
else{
bOffset = best_bw_idx;
bPkts = 1;
bCsCount = (maxp + (188 - 1)) / 188;
if(is_in){
cs_mframe = bOffset%8 + 2 + bCsCount;
if (cs_mframe <= 6)
bCsCount += 2;
else if (cs_mframe == 7)
bCsCount++;
}
bw_cost = 188;
bRepeat = 0;
if(add_sch_ep( dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
, bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
return SCH_FAIL;
}
ret = SCH_SUCCESS;
}
}
else if((dev_speed == USB_SPEED_FULL || dev_speed == USB_SPEED_LOW) && ep_type == USB_EP_INT){
bPkts = 1;
ret = SCH_SUCCESS;
}
else if(dev_speed == USB_SPEED_FULL && ep_type == USB_EP_ISOC){
bPkts = 1;
ret = SCH_SUCCESS;
}
else if(dev_speed == USB_SPEED_HIGH && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
best_bw = HS_BW_BOUND;
best_bw_idx = -1;
cur_bw = 0;
td_size = maxp*(burst+1);
for(cur_offset = 0; cur_offset<interval; cur_offset++){
cur_bw = count_hs_bw(ep_type, maxp, interval, cur_offset, td_size);
if(cur_bw > 0 && cur_bw < best_bw){
best_bw_idx = cur_offset;
best_bw = cur_bw;
if(cur_bw == td_size || cur_bw < (HS_BW_BOUND>>1)){
break;
}
}
}
if(best_bw_idx == -1){
return SCH_FAIL;
}
else{
bOffset = best_bw_idx;
bPkts = burst + 1;
bCsCount = 0;
bw_cost = td_size;
bRepeat = 0;
if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
, bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
return SCH_FAIL;
}
ret = SCH_SUCCESS;
}
}
else if(dev_speed == USB_SPEED_SUPER && (ep_type == USB_EP_INT || ep_type == USB_EP_ISOC)){
best_bw = SS_BW_BOUND;
best_bw_idx = -1;
cur_bw = 0;
td_size = maxp * (mult+1) * (burst+1);
if(mult == 0){
max_repeat = 0;
}
else{
max_repeat = (interval-1)/(mult+1);
}
break_out = 0;
for(frame_idx = 0; (frame_idx < interval) && !break_out; frame_idx++){
for(repeat = max_repeat; repeat >= 0; repeat--){
cur_bw = count_ss_bw(is_in, ep_type, maxp, interval, burst, mult, frame_idx
, repeat, td_size);
printk(KERN_ERR "count_ss_bw, frame_idx %d, repeat %d, td_size %d, result bw %d\n"
, frame_idx, repeat, td_size, cur_bw);
if(cur_bw > 0 && cur_bw < best_bw){
best_bw_idx = frame_idx;
best_bw_repeat = repeat;
best_bw = cur_bw;
if(cur_bw <= td_size || cur_bw < (HS_BW_BOUND>>1)){
break_out = 1;
break;
}
}
}
}
printk(KERN_ERR "final best idx %d, best repeat %d\n", best_bw_idx, best_bw_repeat);
if(best_bw_idx == -1){
return SCH_FAIL;
}
else{
bOffset = best_bw_idx;
bCsCount = 0;
bRepeat = best_bw_repeat;
if(bRepeat == 0){
bw_cost = (burst+1)*(mult+1)*maxp;
bPkts = (burst+1)*(mult+1);
}
else{
bw_cost = (burst+1)*maxp;
bPkts = (burst+1);
}
if(add_sch_ep(dev_speed, is_in, isTT, ep_type, maxp, interval, burst, mult
, bOffset, bRepeat, bPkts, bCsCount, bBm, bw_cost, ep, sch_ep) == SCH_FAIL){
return SCH_FAIL;
}
ret = SCH_SUCCESS;
}
}
else{
bPkts = 1;
ret = SCH_SUCCESS;
}
if(ret == SCH_SUCCESS){
temp_ep_ctx = (struct mtk_xhci_ep_ctx *)ep_ctx;
temp_ep_ctx->reserved[0] |= (BPKTS(bPkts) | BCSCOUNT(bCsCount) | BBM(bBm));
temp_ep_ctx->reserved[1] |= (BOFFSET(bOffset) | BREPEAT(bRepeat));
printk(KERN_DEBUG "[DBG] BPKTS: %x, BCSCOUNT: %x, BBM: %x\n", bPkts, bCsCount, bBm);
printk(KERN_DEBUG "[DBG] BOFFSET: %x, BREPEAT: %x\n", bOffset, bRepeat);
return SCH_SUCCESS;
}
else{
return SCH_FAIL;
}
}

77
target/linux/ramips/files/drivers/usb/host/xhci-mtk-scheduler.h
View File

@ -1,77 +0,0 @@
#ifndef _XHCI_MTK_SCHEDULER_H
#define _XHCI_MTK_SCHEDULER_H
#define MTK_SCH_NEW 1
#define SCH_SUCCESS 1
#define SCH_FAIL 0
#define MAX_EP_NUM 64
#define SS_BW_BOUND 51000
#define HS_BW_BOUND 6144
#define USB_EP_CONTROL 0
#define USB_EP_ISOC 1
#define USB_EP_BULK 2
#define USB_EP_INT 3
#define USB_SPEED_LOW 1
#define USB_SPEED_FULL 2
#define USB_SPEED_HIGH 3
#define USB_SPEED_SUPER 5
/* mtk scheduler bitmasks */
#define BPKTS(p) ((p) & 0x3f)
#define BCSCOUNT(p) (((p) & 0x7) << 8)
#define BBM(p) ((p) << 11)
#define BOFFSET(p) ((p) & 0x3fff)
#define BREPEAT(p) (((p) & 0x7fff) << 16)
#if 1
typedef unsigned int mtk_u32;
typedef unsigned long long mtk_u64;
#endif
#define NULL ((void *)0)
struct mtk_xhci_ep_ctx {
mtk_u32 ep_info;
mtk_u32 ep_info2;
mtk_u64 deq;
mtk_u32 tx_info;
/* offset 0x14 - 0x1f reserved for HC internal use */
mtk_u32 reserved[3];
};
struct sch_ep
{
//device info
int dev_speed;
int isTT;
//ep info
int is_in;
int ep_type;
int maxp;
int interval;
int burst;
int mult;
//scheduling info
int offset;
int repeat;
int pkts;
int cs_count;
int burst_mode;
//other
int bw_cost; //bandwidth cost in each repeat; including overhead
mtk_u32 *ep; //address of usb_endpoint pointer
};
int mtk_xhci_scheduler_init(void);
int mtk_xhci_scheduler_add_ep(int dev_speed, int is_in, int isTT, int ep_type, int maxp, int interval, int burst
, int mult, mtk_u32 *ep, mtk_u32 *ep_ctx, struct sch_ep *sch_ep);
struct sch_ep * mtk_xhci_scheduler_remove_ep(int dev_speed, int is_in, int isTT, int ep_type, mtk_u32 *ep);
#endif

265
target/linux/ramips/files/drivers/usb/host/xhci-mtk.c
View File

@ -1,265 +0,0 @@
#include "xhci-mtk.h"
#include "xhci-mtk-power.h"
#include "xhci.h"
#include "mtk-phy.h"
#ifdef CONFIG_C60802_SUPPORT
#include "mtk-phy-c60802.h"
#endif
#include "xhci-mtk-scheduler.h"
#include <linux/kernel.h> /* printk() */
#include <linux/slab.h>
#include <linux/delay.h>
#include <asm/uaccess.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
void setInitialReg(void )
{
__u32 __iomem *addr;
u32 temp;
/* set SSUSB DMA burst size to 128B */
addr = SSUSB_U3_XHCI_BASE + SSUSB_HDMA_CFG;
temp = SSUSB_HDMA_CFG_MT7621_VALUE;
writel(temp, addr);
/* extend U3 LTSSM Polling.LFPS timeout value */
addr = SSUSB_U3_XHCI_BASE + U3_LTSSM_TIMING_PARAMETER3;
temp = U3_LTSSM_TIMING_PARAMETER3_VALUE;
writel(temp, addr);
/* EOF */
addr = SSUSB_U3_XHCI_BASE + SYNC_HS_EOF;
temp = SYNC_HS_EOF_VALUE;
writel(temp, addr);
#if defined (CONFIG_PERIODIC_ENP)
/* HSCH_CFG1: SCH2_FIFO_DEPTH */
addr = SSUSB_U3_XHCI_BASE + HSCH_CFG1;
temp = readl(addr);
temp &= ~(0x3 << SCH2_FIFO_DEPTH_OFFSET);
writel(temp, addr);
#endif
/* Doorbell handling */
addr = SIFSLV_IPPC + SSUSB_IP_SPAR0;
temp = 0x1;
writel(temp, addr);
/* Set SW PLL Stable mode to 1 for U2 LPM device remote wakeup */
/* Port 0 */
addr = U2_PHY_BASE + U2_PHYD_CR1;
temp = readl(addr);
temp &= ~(0x3 << 18);
temp |= (1 << 18);
writel(temp, addr);
/* Port 1 */
addr = U2_PHY_BASE_P1 + U2_PHYD_CR1;
temp = readl(addr);
temp &= ~(0x3 << 18);
temp |= (1 << 18);
writel(temp, addr);
}
void setLatchSel(void){
__u32 __iomem *latch_sel_addr;
u32 latch_sel_value;
latch_sel_addr = U3_PIPE_LATCH_SEL_ADD;
latch_sel_value = ((U3_PIPE_LATCH_TX)<<2) | (U3_PIPE_LATCH_RX);
writel(latch_sel_value, latch_sel_addr);
}
void reinitIP(void){
__u32 __iomem *ip_reset_addr;
u32 ip_reset_value;
enableAllClockPower();
mtk_xhci_scheduler_init();
}
void dbg_prb_out(void){
mtk_probe_init(0x0f0f0f0f);
mtk_probe_out(0xffffffff);
mtk_probe_out(0x01010101);
mtk_probe_out(0x02020202);
mtk_probe_out(0x04040404);
mtk_probe_out(0x08080808);
mtk_probe_out(0x10101010);
mtk_probe_out(0x20202020);
mtk_probe_out(0x40404040);
mtk_probe_out(0x80808080);
mtk_probe_out(0x55555555);
mtk_probe_out(0xaaaaaaaa);
}
///////////////////////////////////////////////////////////////////////////////
#define RET_SUCCESS 0
#define RET_FAIL 1
static int dbg_u3w(int argc, char**argv)
{
int u4TimingValue;
char u1TimingValue;
int u4TimingAddress;
if (argc<3)
{
printk(KERN_ERR "Arg: address value\n");
return RET_FAIL;
}
u3phy_init();
u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
u4TimingValue = (int)simple_strtol(argv[2], &argv[2], 16);
u1TimingValue = u4TimingValue & 0xff;
/* access MMIO directly */
writel(u1TimingValue, u4TimingAddress);
printk(KERN_ERR "Write done\n");
return RET_SUCCESS;
}
static int dbg_u3r(int argc, char**argv)
{
char u1ReadTimingValue;
int u4TimingAddress;
if (argc<2)
{
printk(KERN_ERR "Arg: address\n");
return 0;
}
u3phy_init();
mdelay(500);
u4TimingAddress = (int)simple_strtol(argv[1], &argv[1], 16);
/* access MMIO directly */
u1ReadTimingValue = readl(u4TimingAddress);
printk(KERN_ERR "Value = 0x%x\n", u1ReadTimingValue);
return 0;
}
static int dbg_u3init(int argc, char**argv)
{
int ret;
ret = u3phy_init();
printk(KERN_ERR "phy registers and operations initial done\n");
if(u3phy_ops->u2_slew_rate_calibration){
u3phy_ops->u2_slew_rate_calibration(u3phy);
}
else{
printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
}
if(u3phy_ops->init(u3phy) == PHY_TRUE)
return RET_SUCCESS;
return RET_FAIL;
}
void dbg_setU1U2(int argc, char**argv){
struct xhci_hcd *xhci;
int u1_value;
int u2_value;
u32 port_id, temp;
u32 __iomem *addr;
if (argc<3)
{
printk(KERN_ERR "Arg: u1value u2value\n");
return RET_FAIL;
}
u1_value = (int)simple_strtol(argv[1], &argv[1], 10);
u2_value = (int)simple_strtol(argv[2], &argv[2], 10);
addr = (SSUSB_U3_XHCI_BASE + 0x424);
temp = readl(addr);
temp = temp & (~(0x0000ffff));
temp = temp | u1_value | (u2_value<<8);
writel(temp, addr);
}
///////////////////////////////////////////////////////////////////////////////
int call_function(char *buf)
{
int i;
int argc;
char *argv[80];
argc = 0;
do
{
argv[argc] = strsep(&buf, " ");
printk(KERN_DEBUG "[%d] %s\r\n", argc, argv[argc]);
argc++;
} while (buf);
if (!strcmp("dbg.r", argv[0]))
dbg_prb_out();
else if (!strcmp("dbg.u3w", argv[0]))
dbg_u3w(argc, argv);
else if (!strcmp("dbg.u3r", argv[0]))
dbg_u3r(argc, argv);
else if (!strcmp("dbg.u3i", argv[0]))
dbg_u3init(argc, argv);
else if (!strcmp("pw.u1u2", argv[0]))
dbg_setU1U2(argc, argv);
return 0;
}
long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
{
char w_buf[200];
char r_buf[200] = "this is a test";
int len = 200;
switch (cmd) {
case IOCTL_READ:
copy_to_user((char *) arg, r_buf, len);
printk(KERN_DEBUG "IOCTL_READ: %s\r\n", r_buf);
break;
case IOCTL_WRITE:
copy_from_user(w_buf, (char *) arg, len);
printk(KERN_DEBUG "IOCTL_WRITE: %s\r\n", w_buf);
//invoke function
return call_function(w_buf);
break;
default:
return -ENOTTY;
}
return len;
}
int xhci_mtk_test_open(struct inode *inode, struct file *file)
{
printk(KERN_DEBUG "xhci_mtk_test open: successful\n");
return 0;
}
int xhci_mtk_test_release(struct inode *inode, struct file *file)
{
printk(KERN_DEBUG "xhci_mtk_test release: successful\n");
return 0;
}
ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr)
{
printk(KERN_DEBUG "xhci_mtk_test read: returning zero bytes\n");
return 0;
}
ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos)
{
printk(KERN_DEBUG "xhci_mtk_test write: accepting zero bytes\n");
return 0;
}

120
target/linux/ramips/files/drivers/usb/host/xhci-mtk.h
View File

@ -1,120 +0,0 @@
#ifndef _XHCI_MTK_H
#define _XHCI_MTK_H
#include <linux/usb.h>
#include "xhci.h"
#define SSUSB_U3_XHCI_BASE 0xBE1C0000
#define SSUSB_U3_MAC_BASE 0xBE1C2400
#define SSUSB_U3_SYS_BASE 0xBE1C2600
#define SSUSB_U2_SYS_BASE 0xBE1C3400
#define SSUB_SIF_SLV_TOP 0xBE1D0000
#define SIFSLV_IPPC (SSUB_SIF_SLV_TOP + 0x700)
#define U3_PIPE_LATCH_SEL_ADD SSUSB_U3_MAC_BASE + 0x130
#define U3_PIPE_LATCH_TX 0
#define U3_PIPE_LATCH_RX 0
#define U3_UX_EXIT_LFPS_TIMING_PAR 0xa0
#define U3_REF_CK_PAR 0xb0
#define U3_RX_UX_EXIT_LFPS_REF_OFFSET 8
#define U3_RX_UX_EXIT_LFPS_REF 3
#define U3_REF_CK_VAL 10
#define U3_TIMING_PULSE_CTRL 0xb4
#define CNT_1US_VALUE 63 //62.5MHz:63, 70MHz:70, 80MHz:80, 100MHz:100, 125MHz:125
#define USB20_TIMING_PARAMETER 0x40
#define TIME_VALUE_1US 63 //62.5MHz:63, 80MHz:80, 100MHz:100, 125MHz:125
#define LINK_PM_TIMER 0x8
#define PM_LC_TIMEOUT_VALUE 3
#define XHCI_IMOD 0x624
#define XHCI_IMOD_MT7621_VALUE 0x10
#define SSUSB_HDMA_CFG 0x950
#define SSUSB_HDMA_CFG_MT7621_VALUE 0x10E0E0C
#define U3_LTSSM_TIMING_PARAMETER3 0x2514
#define U3_LTSSM_TIMING_PARAMETER3_VALUE 0x3E8012C
#define U2_PHYD_CR1 0x64
#define SSUSB_IP_SPAR0 0xC8
#define SYNC_HS_EOF 0x938
#define SYNC_HS_EOF_VALUE 0x201F3
#define HSCH_CFG1 0x960
#define SCH2_FIFO_DEPTH_OFFSET 16
#define SSUSB_IP_PW_CTRL (SIFSLV_IPPC+0x0)
#define SSUSB_IP_SW_RST (1<<0)
#define SSUSB_IP_PW_CTRL_1 (SIFSLV_IPPC+0x4)
#define SSUSB_IP_PDN (1<<0)
#define SSUSB_U3_CTRL(p) (SIFSLV_IPPC+0x30+(p*0x08))
#define SSUSB_U3_PORT_DIS (1<<0)
#define SSUSB_U3_PORT_PDN (1<<1)
#define SSUSB_U3_PORT_HOST_SEL (1<<2)
#define SSUSB_U3_PORT_CKBG_EN (1<<3)
#define SSUSB_U3_PORT_MAC_RST (1<<4)
#define SSUSB_U3_PORT_PHYD_RST (1<<5)
#define SSUSB_U2_CTRL(p) (SIFSLV_IPPC+(0x50)+(p*0x08))
#define SSUSB_U2_PORT_DIS (1<<0)
#define SSUSB_U2_PORT_PDN (1<<1)
#define SSUSB_U2_PORT_HOST_SEL (1<<2)
#define SSUSB_U2_PORT_CKBG_EN (1<<3)
#define SSUSB_U2_PORT_MAC_RST (1<<4)
#define SSUSB_U2_PORT_PHYD_RST (1<<5)
#define SSUSB_IP_CAP (SIFSLV_IPPC+0x024)
#define SSUSB_U3_PORT_NUM(p) (p & 0xff)
#define SSUSB_U2_PORT_NUM(p) ((p>>8) & 0xff)
#define XHCI_MTK_TEST_MAJOR 234
#define DEVICE_NAME "xhci_mtk_test"
#define CLI_MAGIC 'CLI'
#define IOCTL_READ _IOR(CLI_MAGIC, 0, int)
#define IOCTL_WRITE _IOW(CLI_MAGIC, 1, int)
void reinitIP(void);
void setInitialReg(void);
void dbg_prb_out(void);
int call_function(char *buf);
long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
int xhci_mtk_test_open(struct inode *inode, struct file *file);
int xhci_mtk_test_release(struct inode *inode, struct file *file);
ssize_t xhci_mtk_test_read(struct file *file, char *buf, size_t count, loff_t *ptr);
ssize_t xhci_mtk_test_write(struct file *file, const char *buf, size_t count, loff_t * ppos);
/*
mediatek probe out
*/
/************************************************************************************/
#define SW_PRB_OUT_ADDR (SIFSLV_IPPC+0xc0)
#define PRB_MODULE_SEL_ADDR (SIFSLV_IPPC+0xbc)
static inline void mtk_probe_init(const u32 byte){
__u32 __iomem *ptr = (__u32 __iomem *) PRB_MODULE_SEL_ADDR;
writel(byte, ptr);
}
static inline void mtk_probe_out(const u32 value){
__u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
writel(value, ptr);
}
static inline u32 mtk_probe_value(void){
__u32 __iomem *ptr = (__u32 __iomem *) SW_PRB_OUT_ADDR;
return readl(ptr);
}
#endif

33
target/linux/ramips/mt7621/config-3.10
View File

@ -1,6 +1,8 @@
# CONFIG_32B_DESC is not set
CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
CONFIG_ARCH_DISCARD_MEMBLOCK=y
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
@ -35,6 +37,14 @@ CONFIG_DMA_NONCOHERENT=y
CONFIG_DTB_RT_NONE=y
CONFIG_DTC=y
CONFIG_EARLY_PRINTK=y
CONFIG_ESW_DOUBLE_VLAN_TAG=y
# CONFIG_GE1_MII_AN is not set
# CONFIG_GE1_MII_FORCE_100 is not set
# CONFIG_GE1_RGMII_AN is not set
CONFIG_GE1_RGMII_FORCE_1000=y
# CONFIG_GE1_RGMII_NONE is not set
# CONFIG_GE1_RVMII_FORCE_100 is not set
# CONFIG_GE1_TRGMII_FORCE_1200 is not set
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
@ -88,6 +98,7 @@ CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_GIC=y
CONFIG_IRQ_WORK=y
# CONFIG_LAN_WAN_SUPPORT is not set
CONFIG_M25PXX_USE_FAST_READ=y
CONFIG_MDIO_BOARDINFO=y
# CONFIG_MII is not set
@ -105,6 +116,7 @@ CONFIG_MIPS_MT_SMP=y
CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
# CONFIG_MIPS_VPE_LOADER is not set
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MT7621_ASIC=y
# CONFIG_MT7621_WDT is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CMDLINE_PARTS=y
@ -137,6 +149,7 @@ CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_PCI=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
CONFIG_PDMA_NEW=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PHYLIB=y
# CONFIG_PINCONF is not set
@ -145,12 +158,30 @@ CONFIG_PINCTRL_RT2880=y
# CONFIG_PINCTRL_SINGLE is not set
CONFIG_PINMUX=y
# CONFIG_PREEMPT_RCU is not set
CONFIG_RAETH=y
CONFIG_RAETH_CHECKSUM_OFFLOAD=y
# CONFIG_RAETH_GMAC2 is not set
# CONFIG_RAETH_HW_VLAN_RX is not set
# CONFIG_RAETH_HW_VLAN_TX is not set
# CONFIG_RAETH_LRO is not set
# CONFIG_RAETH_NAPI is not set
# CONFIG_RAETH_QDMA is not set
CONFIG_RAETH_SCATTER_GATHER_RX_DMA=y
# CONFIG_RAETH_SKB_RECYCLE_2K is not set
# CONFIG_RAETH_SPECIAL_TAG is not set
# CONFIG_RAETH_TSO is not set
CONFIG_RALINK=y
CONFIG_RALINK_MT7621=y
CONFIG_RALINK_USBPHY=y
# CONFIG_RALINK_WDT is not set
CONFIG_RA_NAT_NONE=y
# CONFIG_RA_NETWORK_TASKLET_BH is not set
CONFIG_RA_NETWORK_WORKQUEUE_BH=y
CONFIG_RCU_STALL_COMMON=y
CONFIG_RESET_CONTROLLER=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RT_3052_ESW=y
# CONFIG_SAMSUNG_USB2PHY is not set
# CONFIG_SAMSUNG_USB3PHY is not set
# CONFIG_SAMSUNG_USBPHY is not set
@ -199,6 +230,8 @@ CONFIG_USB_XHCI_HCD=m
CONFIG_USB_XHCI_PLATFORM=y
CONFIG_USE_GENERIC_SMP_HELPERS=y
CONFIG_USE_OF=y
CONFIG_WAN_AT_P0=y
# CONFIG_WAN_AT_P4 is not set
CONFIG_WATCHDOG_CORE=y
CONFIG_WEAK_ORDERING=y
CONFIG_XPS=y

2
target/linux/ramips/mt7621/profiles/00-default.mk
View File

@ -8,7 +8,7 @@
define Profile/Default
NAME:=Default Profile
PACKAGES:=\
kmod-usb-core kmod-usb-dwc2 \
kmod-usb-core kmod-usb3 \
kmod-ledtrig-usbdev
endef

31
target/linux/ramips/patches-3.10/0100-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch
View File

@ -1,7 +1,7 @@
From cdc1b12b3debaf5b3894fd146e73221a8acd0152 Mon Sep 17 00:00:00 2001
From 1be15a87eea5f26fb24b6aac332530cd3e2d984e Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 14 Jul 2013 23:08:11 +0200
Subject: [PATCH 20/25] MIPS: use set_mode() to enable/disable the cevt-r4k
Subject: [PATCH 100/133] MIPS: use set_mode() to enable/disable the cevt-r4k
irq
Signed-off-by: John Crispin <blogic@openwrt.org>
@ -24,13 +24,14 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
int cp0_timer_irq_installed;
@@ -90,6 +84,32 @@ struct irqaction c0_compare_irqaction =
@@ -90,9 +84,38 @@ struct irqaction c0_compare_irqaction =
.name = "timer",
};
+void mips_set_clock_mode(enum clock_event_mode mode,
+ struct clock_event_device *evt)
+{
+#ifdef CONFIG_CEVT_SYSTICK_QUIRK
+ switch (mode) {
+ case CLOCK_EVT_MODE_ONESHOT:
+ if (cp0_timer_irq_installed)
@ -53,21 +54,27 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ pr_err("Unhandeled mips clock_mode\n");
+ break;
+ }
+#endif
+}
void mips_event_handler(struct clock_event_device *dev)
{
@@ -215,13 +235,6 @@ int __cpuinit r4k_clockevent_init(void)
+
}
/*
@@ -215,12 +238,14 @@ int __cpuinit r4k_clockevent_init(void)
#endif
clockevents_register_device(cd);
- if (cp0_timer_irq_installed)
- return 0;
-
- cp0_timer_irq_installed = 1;
-
- setup_irq(irq, &c0_compare_irqaction);
-
+#ifndef CONFIG_CEVT_SYSTICK_QUIRK
if (cp0_timer_irq_installed)
return 0;
cp0_timer_irq_installed = 1;
setup_irq(irq, &c0_compare_irqaction);
+#endif
return 0;
}

4
target/linux/ramips/patches-3.10/0102-MIPS-ralink-add-verbose-pmu-info.patch → target/linux/ramips/patches-3.10/0101-MIPS-ralink-add-verbose-pmu-info.patch
View File

@ -1,7 +1,7 @@
From 74339d6eab7a37f7c629b737bf686d30e5014ce2 Mon Sep 17 00:00:00 2001
From 5689333e7e4396a827a2cb6fa1242159e9af56de Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 20 May 2013 20:57:09 +0200
Subject: [PATCH 06/33] MIPS: ralink: add verbose pmu info
Subject: [PATCH 101/133] MIPS: ralink: add verbose pmu info
Print the PMU and LDO settings on boot.

4
target/linux/ramips/patches-3.10/0103-MIPS-ralink-adds-a-bootrom-dumper-module.patch → target/linux/ramips/patches-3.10/0102-MIPS-ralink-adds-a-bootrom-dumper-module.patch
View File

@ -1,7 +1,7 @@
From 71409a190a0c8e3597cae7d46321742e29d8994b Mon Sep 17 00:00:00 2001
From 23d18a1b3d0a7e5faa08b6bece6692667c930975 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 21 May 2013 15:50:31 +0200
Subject: [PATCH 07/33] MIPS: ralink: adds a bootrom dumper module
Subject: [PATCH 102/133] MIPS: ralink: adds a bootrom dumper module
This patch adds a trivial driver that allows userland to extract the bootrom of
a SoC via debugfs.

4
target/linux/ramips/patches-3.10/0104-MIPS-ralink-add-illegal-access-driver.patch → target/linux/ramips/patches-3.10/0103-MIPS-ralink-add-illegal-access-driver.patch
View File

@ -1,7 +1,7 @@
From 46446fcfc6e823005ebe71357b5995524e75542c Mon Sep 17 00:00:00 2001
From c5fe00f24f56b15f982dda355089986d57488b36 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 16 May 2013 23:28:23 +0200
Subject: [PATCH 08/33] MIPS: ralink: add illegal access driver
Subject: [PATCH 103/133] MIPS: ralink: add illegal access driver
Signed-off-by: John Crispin <blogic@openwrt.org>
---

4
target/linux/ramips/patches-3.10/0105-MIPS-ralink-workaround-DTB-memory-issue.patch → target/linux/ramips/patches-3.10/0104-MIPS-ralink-workaround-DTB-memory-issue.patch
View File

@ -1,7 +1,7 @@
From 070a389ae536a75b9184784f625949c215c533b6 Mon Sep 17 00:00:00 2001
From b83808826ac7a5c727f5314b5a3bf07fcd6ec929 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 23 May 2013 18:50:56 +0200
Subject: [PATCH 09/33] MIPS: ralink: workaround DTB memory issue
Subject: [PATCH 104/133] MIPS: ralink: workaround DTB memory issue
If the DTB is too big a bug happens on boot when init ram is freed.
This is a temporary fix until the real cause is found.

25
target/linux/ramips/patches-3.10/0105-MIPS-ralink-add-missing-clk_set_rate-to-clk.c.patch Normal file
View File

@ -0,0 +1,25 @@
From 6f72aea69951479b7daad1d38b506ede4f8a1676 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 16 Mar 2014 04:38:07 +0000
Subject: [PATCH 105/133] MIPS: ralink: add missing clk_set_rate() to clk.c
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/ralink/clk.c | 6 ++++++
1 file changed, 6 insertions(+)
--- a/arch/mips/ralink/clk.c
+++ b/arch/mips/ralink/clk.c
@@ -56,6 +56,12 @@ unsigned long clk_get_rate(struct clk *c
}
EXPORT_SYMBOL_GPL(clk_get_rate);
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ return -1;
+}
+EXPORT_SYMBOL_GPL(clk_set_rate);
+
void __init plat_time_init(void)
{
struct clk *clk;

15
target/linux/ramips/patches-3.10/999-mt7620n.patch → target/linux/ramips/patches-3.10/0106-MIPS-ralink-add-support-for-MT7620n.patch
View File

@ -1,3 +1,16 @@
From 45ba0675286e2a71f6a577833ab13b951bb7e31a Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 16 Mar 2014 04:40:02 +0000
Subject: [PATCH 106/133] MIPS: ralink: add support for MT7620n
This is the small version of MT7620a.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/include/asm/mach-ralink/mt7620.h | 7 ++-----
arch/mips/ralink/mt7620.c | 19 ++++++++++++-------
2 files changed, 14 insertions(+), 12 deletions(-)
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -24,11 +24,8 @@
@ -16,7 +29,7 @@
#define CHIP_REV_PKG_SHIFT 16
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -167,22 +167,27 @@ void prom_soc_init(struct ralink_soc_inf
@@ -226,22 +226,27 @@ void prom_soc_init(struct ralink_soc_inf
u32 cfg0;
u32 pmu0;
u32 pmu1;

19
target/linux/ramips/patches-3.10/0106-USB-dwc2.patch
View File

@ -1,19 +0,0 @@
--- a/drivers/staging/dwc2/hcd.c
+++ b/drivers/staging/dwc2/hcd.c
@@ -47,6 +47,7 @@
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/usb.h>
+#include <linux/reset.h>
#include <linux/usb/hcd.h>
#include <linux/usb/ch11.h>
@@ -2712,6 +2713,8 @@ int dwc2_hcd_init(struct dwc2_hsotg *hso
dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
+ device_reset(hsotg->dev);
+
/*
* Attempt to ensure this device is really a DWC_otg Controller.
* Read and verify the GSNPSID register contents. The value should be

45
target/linux/ramips/patches-3.10/0107-MIPS-ralink-allow-manual-memory-override.patch Normal file
View File

@ -0,0 +1,45 @@
From ee46d05eefefb0fb40b5682b4f6f3876b496044b Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 16 Mar 2014 04:40:48 +0000
Subject: [PATCH 107/133] MIPS: ralink: allow manual memory override
RT5350 relies on the bootloader setting up the memc correctly.
On sme boards the setup is incorrect leading to 32 MB being available but only 16 being recognized. Allow these boards to manually override the memory range
.
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/ralink/of.c | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
@@ -77,6 +77,17 @@ void __init device_tree_init(void)
//free_bootmem(base, size);
}
+static int memory_dtb;
+
+static int __init early_init_dt_find_memory(unsigned long node, const char *uname,
+ int depth, void *data)
+{
+ if (depth == 1 && !strcmp(uname, "memory@0"))
+ memory_dtb = 1;
+
+ return 0;
+}
+
void __init plat_mem_setup(void)
{
set_io_port_base(KSEG1);
@@ -87,7 +98,10 @@ void __init plat_mem_setup(void)
*/
__dt_setup_arch(&__dtb_start);
- if (soc_info.mem_size)
+ of_scan_flat_dt(early_init_dt_find_memory, NULL);
+ if (memory_dtb)
+ of_scan_flat_dt(early_init_dt_scan_memory, NULL);
+ else if (soc_info.mem_size)
add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M,
BOOT_MEM_RAM);
else

4
target/linux/ramips/patches-3.10/0121-MIPS-ralink-add-rt_sysc_m32-helper.patch → target/linux/ramips/patches-3.10/0108-MIPS-ralink-add-rt_sysc_m32-helper.patch
View File

@ -1,7 +1,7 @@
From 3af962f91035ae4500e63c758c49f1c067bdae09 Mon Sep 17 00:00:00 2001
From 1fe4d719d1c973c01f4b6a4c0de47bfac77e3eca Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 19 May 2013 00:42:23 +0200
Subject: [PATCH 04/33] MIPS: ralink: add rt_sysc_m32 helper
Subject: [PATCH 108/133] MIPS: ralink: add rt_sysc_m32 helper
Signed-off-by: John Crispin <blogic@openwrt.org>
---

6
target/linux/ramips/patches-3.10/0201-owrt-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on.patch → target/linux/ramips/patches-3.10/0109-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on-time.patch
View File

@ -1,8 +1,8 @@
From daf08289dc0ac69af0d8293dacd5ca6291400593 Mon Sep 17 00:00:00 2001
From ca21f813087ca5a8b02ec00efcd9c3f3fbf3bc1f Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 24 Mar 2013 17:17:17 +0100
Subject: [PATCH 30/33] owrt: MIPS: ralink: add pseudo pwm led trigger based
on timer0
Subject: [PATCH 109/133] MIPS: ralink: add pseudo pwm led trigger based on
timer0
Signed-off-by: John Crispin <blogic@openwrt.org>
---

23
target/linux/ramips/patches-3.10/0110-MIPS-ralink-add-a-helper-for-reading-the-ECO-version.patch Normal file
View File

@ -0,0 +1,23 @@
From f57edea9db0f7f437bc4f2ae408f6dd8bfbb9062 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 16 Mar 2014 04:53:02 +0000
Subject: [PATCH 110/133] MIPS: ralink: add a helper for reading the ECO
version
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/include/asm/mach-ralink/mt7620.h | 5 +++++
1 file changed, 5 insertions(+)
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -79,4 +79,9 @@
#define MT7620_GPIO_MODE_EPHY BIT(15)
#define MT7620_GPIO_MODE_WDT BIT(22)
+static inline int mt7620_get_eco(void)
+{
+ return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
+}
+
#endif

94
target/linux/ramips/patches-3.10/0300-DMA-add-rt2880-dma-engine.patch → target/linux/ramips/patches-3.10/0111-DMA-ralink-add-rt2880-dma-engine.patch
View File

@ -1,14 +1,16 @@
From 776726ff626249276936a7e1f865103ea4e1b7e9 Mon Sep 17 00:00:00 2001
From 2d7e32d4825e20e9db4f0dff6b3e3c25c8c7ad7d Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 3 Dec 2013 17:05:05 +0100
Subject: [PATCH] DMA: add rt2880 dma engine
Subject: [PATCH 111/133] DMA: ralink: add rt2880 dma engine
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/dma/Kconfig | 6 +
drivers/dma/Makefile | 1 +
drivers/dma/ralink-gdma.c | 596 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 603 insertions(+)
drivers/dma/dmaengine.c | 26 ++
drivers/dma/ralink-gdma.c | 577 +++++++++++++++++++++++++++++++++++++++++++++
include/linux/dmaengine.h | 1 +
5 files changed, 611 insertions(+)
create mode 100644 drivers/dma/ralink-gdma.c
--- a/drivers/dma/Kconfig
@ -26,6 +28,48 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
config DMA_ENGINE
bool
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -38,3 +38,4 @@ obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
obj-$(CONFIG_DMA_OMAP) += omap-dma.o
obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
+obj-$(CONFIG_DMA_RALINK) += ralink-gdma.o
--- a/drivers/dma/dmaengine.c
+++ b/drivers/dma/dmaengine.c
@@ -504,6 +504,32 @@ static struct dma_chan *private_candidat
}
/**
+ * dma_request_slave_channel - try to get specific channel exclusively
+ * @chan: target channel
+ */
+struct dma_chan *dma_get_slave_channel(struct dma_chan *chan)
+{
+ int err = -EBUSY;
+
+ /* lock against __dma_request_channel */
+ mutex_lock(&dma_list_mutex);
+
+ if (chan->client_count == 0) {
+ err = dma_chan_get(chan);
+ if (err)
+ pr_debug("%s: failed to get %s: (%d)\n",
+ __func__, dma_chan_name(chan), err);
+ } else
+ chan = NULL;
+
+ mutex_unlock(&dma_list_mutex);
+
+ return chan;
+}
+EXPORT_SYMBOL_GPL(dma_get_slave_channel);
+
+
+/**
* dma_request_channel - try to allocate an exclusive channel
* @mask: capabilities that the channel must satisfy
* @fn: optional callback to disposition available channels
--- /dev/null
+++ b/drivers/dma/ralink-gdma.c
@@ -0,0 +1,577 @@
@ -606,41 +650,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
+MODULE_DESCRIPTION("GDMA4740 DMA driver");
+MODULE_LICENSE("GPLv2");
--- a/drivers/dma/dmaengine.c
+++ b/drivers/dma/dmaengine.c
@@ -504,6 +504,32 @@ static struct dma_chan *private_candidat
}
/**
+ * dma_request_slave_channel - try to get specific channel exclusively
+ * @chan: target channel
+ */
+struct dma_chan *dma_get_slave_channel(struct dma_chan *chan)
+{
+ int err = -EBUSY;
+
+ /* lock against __dma_request_channel */
+ mutex_lock(&dma_list_mutex);
+
+ if (chan->client_count == 0) {
+ err = dma_chan_get(chan);
+ if (err)
+ pr_debug("%s: failed to get %s: (%d)\n",
+ __func__, dma_chan_name(chan), err);
+ } else
+ chan = NULL;
+
+ mutex_unlock(&dma_list_mutex);
+
+ return chan;
+}
+EXPORT_SYMBOL_GPL(dma_get_slave_channel);
+
+
+/**
* dma_request_channel - try to allocate an exclusive channel
* @mask: capabilities that the channel must satisfy
* @fn: optional callback to disposition available channels
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -999,6 +999,7 @@ static inline void dma_release_channel(s
@ -651,10 +660,3 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
struct dma_chan *net_dma_find_channel(void);
#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -38,3 +38,4 @@ obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
obj-$(CONFIG_DMA_OMAP) += omap-dma.o
obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
+obj-$(CONFIG_DMA_RALINK) += ralink-gdma.o

54
target/linux/ramips/patches-3.10/0301-asoc-add-mt7620-support.patch → target/linux/ramips/patches-3.10/0112-asoc-add-mt7620-support.patch
View File

@ -1,24 +1,42 @@
From c72bc41d018519de5d63ec7790965fbf4605276a Mon Sep 17 00:00:00 2001
From d4398d880eba386cb85d0a1a2ba39a336876dc0a Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Tue, 3 Dec 2013 20:18:13 +0100
Subject: [PATCH] asoc: add mt7620 support
Subject: [PATCH 112/133] asoc: add mt7620 support
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/ralink/of.c | 2 +
sound/soc/Kconfig | 1 +
sound/soc/Makefile | 1 +
sound/soc/ralink/Kconfig | 24 +++
sound/soc/ralink/Makefile | 13 ++
sound/soc/ralink/mt7620-i2s.c | 429 ++++++++++++++++++++++++++++++++++++++
sound/soc/ralink/mt7620-pcm.c | 77 +++++++
sound/soc/ralink/mt7620-wm8960.c | 124 +++++++++++
7 files changed, 669 insertions(+)
sound/soc/ralink/Kconfig | 15 ++
sound/soc/ralink/Makefile | 11 +
sound/soc/ralink/mt7620-i2s.c | 466 ++++++++++++++++++++++++++++++++++++++
sound/soc/ralink/mt7620-wm8960.c | 125 ++++++++++
sound/soc/soc-io.c | 10 -
8 files changed, 621 insertions(+), 10 deletions(-)
create mode 100644 sound/soc/ralink/Kconfig
create mode 100644 sound/soc/ralink/Makefile
create mode 100644 sound/soc/ralink/mt7620-i2s.c
create mode 100644 sound/soc/ralink/mt7620-pcm.c
create mode 100644 sound/soc/ralink/mt7620-wm8960.c
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
@@ -15,6 +15,7 @@
#include <linux/of_fdt.h>
#include <linux/kernel.h>
#include <linux/bootmem.h>
+#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
@@ -25,6 +26,7 @@
#include "common.h"
__iomem void *rt_sysc_membase;
+EXPORT_SYMBOL(rt_sysc_membase);
__iomem void *rt_memc_membase;
extern struct boot_param_header __dtb_start;
--- a/sound/soc/Kconfig
+++ b/sound/soc/Kconfig
@@ -48,6 +48,7 @@ source "sound/soc/kirkwood/Kconfig"
@ -668,24 +686,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+MODULE_DESCRIPTION("ALSA SoC QI LB60 Audio support");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:qi-lb60-audio");
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
@@ -15,6 +15,7 @@
#include <linux/of_fdt.h>
#include <linux/kernel.h>
#include <linux/bootmem.h>
+#include <linux/module.h>
#include <linux/of_platform.h>
#include <linux/of_address.h>
@@ -25,6 +26,7 @@
#include "common.h"
__iomem void *rt_sysc_membase;
+EXPORT_SYMBOL(rt_sysc_membase);
__iomem void *rt_memc_membase;
extern struct boot_param_header __dtb_start;
--- a/sound/soc/soc-io.c
+++ b/sound/soc/soc-io.c
@@ -19,7 +19,6 @@

1605
target/linux/ramips/patches-3.10/0122-pinmux.patch → target/linux/ramips/patches-3.10/0113-pinctrl-ralink-add-pinctrl-driver.patch
View File

File diff suppressed because it is too large Load Diff

4
target/linux/ramips/patches-3.10/0107-PCI-MIPS-adds-rt2880-pci-support.patch → target/linux/ramips/patches-3.10/0114-PCI-MIPS-adds-rt2880-pci-support.patch
View File

@ -1,7 +1,7 @@
From 5d57ace094803c95230643941a47d749ff81d022 Mon Sep 17 00:00:00 2001
From b7040c3ad7b8daf8309d083e9248cfa577075cfb Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 21 Mar 2013 18:27:29 +0100
Subject: [PATCH 11/33] PCI: MIPS: adds rt2880 pci support
Subject: [PATCH 114/133] PCI: MIPS: adds rt2880 pci support
Add support for the pci found on the rt2880 SoC.

24
target/linux/ramips/patches-3.10/0108-PCI-MIPS-adds-mt7620a-pcie-driver.patch → target/linux/ramips/patches-3.10/0115-PCI-MIPS-adds-mt7620a-pcie-driver.patch
View File

@ -1,7 +1,7 @@
From ded577553b06a85c12a89b8fbcfa2b51f30bc037 Mon Sep 17 00:00:00 2001
From 686f5642c74323f7e7eafb93c2b85df589cbf66e Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sat, 18 May 2013 22:06:15 +0200
Subject: [PATCH 13/33] PCI: MIPS: adds mt7620a pcie driver
Subject: [PATCH 115/133] PCI: MIPS: adds mt7620a pcie driver
Signed-off-by: John Crispin <blogic@openwrt.org>
---
@ -11,6 +11,16 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
3 files changed, 365 insertions(+)
create mode 100644 arch/mips/pci/pci-mt7620a.c
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1
obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
+obj-$(CONFIG_SOC_MT7620) += pci-mt7620a.o
obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o
obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
--- /dev/null
+++ b/arch/mips/pci/pci-mt7620a.c
@@ -0,0 +1,363 @@
@ -387,13 +397,3 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
endchoice
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1
obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
+obj-$(CONFIG_SOC_MT7620) += pci-mt7620a.o
obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o
obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o

4
target/linux/ramips/patches-3.10/0109-NET-multi-phy-support.patch → target/linux/ramips/patches-3.10/0116-NET-multi-phy-support.patch
View File

@ -1,7 +1,7 @@
From 7407b7d178e783074861a73da858b099f870270d Mon Sep 17 00:00:00 2001
From bed88d4cb806d2738528cb7d368d6df79d9c1424 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sat, 11 May 2013 23:40:19 +0200
Subject: [PATCH 14/33] NET: multi phy support
Subject: [PATCH 116/133] NET: multi phy support
Signed-off-by: John Crispin <blogic@openwrt.org>
---

4
target/linux/ramips/patches-3.10/0110-NET-add-of_get_mac_address_mtd.patch → target/linux/ramips/patches-3.10/0117-NET-add-of_get_mac_address_mtd.patch
View File

@ -1,7 +1,7 @@
From 2a41724b2d0af9b4444572c4302570a3af377715 Mon Sep 17 00:00:00 2001
From 1282a0da09e059288eb8b576998ea001680f6628 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 14 Jul 2013 23:26:15 +0200
Subject: [PATCH 15/33] NET: add of_get_mac_address_mtd()
Subject: [PATCH 117/133] NET: add of_get_mac_address_mtd()
Many embedded devices have information such as mac addresses stored inside mtd
devices. This patch allows us to add a property inside a node describing a

1019
target/linux/ramips/patches-3.10/0111-NET-MIPS-add-ralink-SoC-ethernet-driver.patch → target/linux/ramips/patches-3.10/0118-NET-MIPS-add-ralink-SoC-ethernet-driver.patch
View File

File diff suppressed because it is too large Load Diff

4
target/linux/ramips/patches-3.10/0112-USB-phy-add-ralink-SoC-driver.patch → target/linux/ramips/patches-3.10/0119-USB-phy-add-ralink-SoC-driver.patch
View File

@ -1,7 +1,7 @@
From c5f51197b13fd312324ac0486a46e530e163eade Mon Sep 17 00:00:00 2001
From 71e09658d3544143e46ae76e76da8a322cd73e1d Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 14 Jul 2013 23:31:19 +0200
Subject: [PATCH 18/33] USB: phy: add ralink SoC driver
Subject: [PATCH 119/133] USB: phy: add ralink SoC driver
Signed-off-by: John Crispin <blogic@openwrt.org>
---

9
target/linux/ramips/patches-3.10/0113-USB-add-OHCI-EHCI-OF-binding.patch → target/linux/ramips/patches-3.10/0120-USB-add-OHCI-EHCI-OF-binding.patch
View File

@ -1,17 +1,16 @@
From 40b9d3026ed0b3bcd59f90391195df5b2adabad2 Mon Sep 17 00:00:00 2001
From 08d438b69f3023f16b044b07eebee6b9c2302f60 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 14 Jul 2013 23:34:53 +0200
Subject: [PATCH 19/33] USB: add OHCI/EHCI OF binding
Subject: [PATCH 120/133] USB: add OHCI/EHCI OF binding
based on f3bc64d6d1f21c1b92d75f233a37b75d77af6963
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/ralink/Kconfig | 2 ++
drivers/usb/Makefile | 3 ++-
drivers/usb/host/ehci-platform.c | 19 +++++++++++++++----
drivers/usb/host/ehci-platform.c | 21 +++++++++++++++++----
drivers/usb/host/ohci-platform.c | 37 ++++++++++++++++++++++++++++++++-----
4 files changed, 51 insertions(+), 10 deletions(-)
3 files changed, 51 insertions(+), 10 deletions(-)
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile

4
target/linux/ramips/patches-3.10/0202-owrt-USB-adds-dwc_otg.patch → target/linux/ramips/patches-3.10/0121-USB-adds-dwc_otg.patch
View File

@ -1,7 +1,7 @@
From 1a44a003bdaf917193114d0d40534496c39644ba Mon Sep 17 00:00:00 2001
From b74db0e9bae6bbe14e9f725db855621db22e9984 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 15 Mar 2013 20:58:18 +0100
Subject: [PATCH 202/208] owrt: USB: adds dwc_otg
Subject: [PATCH 121/133] USB: adds dwc_otg
Signed-off-by: John Crispin <blogic@openwrt.org>
---

4
target/linux/ramips/patches-3.10/0114-serial-ralink-adds-mt7620-serial.patch → target/linux/ramips/patches-3.10/0122-serial-ralink-adds-mt7620-serial.patch
View File

@ -1,7 +1,7 @@
From 629a2ca61e0fbf331f88692038391d22f21b7c70 Mon Sep 17 00:00:00 2001
From 16f476a7528eefade4bd4ebee12d5aa2052bba8c Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 15 Mar 2013 18:16:01 +0100
Subject: [PATCH 20/33] serial: ralink: adds mt7620 serial
Subject: [PATCH 122/133] serial: ralink: adds mt7620 serial
Add the config symbol for Mediatek7620 SoC to SERIAL_8250_RT288X

22
target/linux/ramips/patches-3.10/0123-serial-ralink-the-core-has-a-size-of-0x100-and-not-0.patch Normal file
View File

@ -0,0 +1,22 @@
From 304c4f060cfa6b44370ad3fe6a16963cac35b10a Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 16 Mar 2014 04:52:01 +0000
Subject: [PATCH 123/133] serial: ralink: the core has a size of 0x100 and not
0x1000
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/tty/serial/8250/8250_core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/tty/serial/8250/8250_core.c
+++ b/drivers/tty/serial/8250/8250_core.c
@@ -2499,7 +2499,7 @@ serial8250_pm(struct uart_port *port, un
static unsigned int serial8250_port_size(struct uart_8250_port *pt)
{
if (pt->port.iotype == UPIO_AU)
- return 0x1000;
+ return 0x100;
if (is_omap1_8250(pt))
return 0x16 << pt->port.regshift;

4
target/linux/ramips/patches-3.10/0115-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch → target/linux/ramips/patches-3.10/0124-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch
View File

@ -1,7 +1,7 @@
From 53b934f796611b9a27b698429f1aaec0fe678693 Mon Sep 17 00:00:00 2001
From 3f70be332048f6a903dc35f73ff5381be3b8f12b Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 14 Jul 2013 23:18:57 +0200
Subject: [PATCH 21/33] serial: of: allow au1x00 and rt288x to load from OF
Subject: [PATCH 124/133] serial: of: allow au1x00 and rt288x to load from OF
In order to make serial_8250 loadable via OF on Au1x00 and Ralink WiSoC we need
to default the iotype to UPIO_AU.

4
target/linux/ramips/patches-3.10/0116-i2c-MIPS-adds-ralink-I2C-driver.patch → target/linux/ramips/patches-3.10/0125-i2c-MIPS-adds-ralink-I2C-driver.patch
View File

@ -1,7 +1,7 @@
From 4596818bca07e0928168970839e08875cf51b4cc Mon Sep 17 00:00:00 2001
From 701cd2fb0513d17f248048b3a6f2c7d1ea294681 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 29 Apr 2013 14:40:43 +0200
Subject: [PATCH 26/33] i2c: MIPS: adds ralink I2C driver
Subject: [PATCH 125/133] i2c: MIPS: adds ralink I2C driver
Signed-off-by: John Crispin <blogic@openwrt.org>
---

4
target/linux/ramips/patches-3.10/0120-spi-introduce-macros-to-set-bits_per_word_mask.patch → target/linux/ramips/patches-3.10/0126-spi-introduce-macros-to-set-bits_per_word_mask.patch
View File

@ -1,7 +1,7 @@
From 2922a8de996956893bb98e4aa91be9774c958336 Mon Sep 17 00:00:00 2001
From b07600f50efe84d7e3b431e6d10fe774bb00d573 Mon Sep 17 00:00:00 2001
From: Stephen Warren <swarren@wwwdotorg.org>
Date: Tue, 21 May 2013 20:36:34 -0600
Subject: [PATCH] spi: introduce macros to set bits_per_word_mask
Subject: [PATCH 126/133] spi: introduce macros to set bits_per_word_mask
Introduce two macros to make setting up spi_master.bits_per_word_mask
easier, and avoid mistakes like writing BIT(n) instead of BIT(n - 1).

4
target/linux/ramips/patches-3.10/0117-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch → target/linux/ramips/patches-3.10/0127-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
View File

@ -1,7 +1,7 @@
From de1defdad7554d6ba885a6d3dc55105e01e9a07e Mon Sep 17 00:00:00 2001
From 759e011e67792898799fb54340ba5bad944274a1 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 2 May 2013 14:59:01 +0200
Subject: [PATCH 27/33] mmc: MIPS: ralink: add sdhci for mt7620a SoC
Subject: [PATCH 127/133] mmc: MIPS: ralink: add sdhci for mt7620a SoC
Signed-off-by: John Crispin <blogic@openwrt.org>
---

4
target/linux/ramips/patches-3.10/0118-mtd-fix-cfi-cmdset-0002-erase-status-check.patch → target/linux/ramips/patches-3.10/0128-mtd-fix-cfi-cmdset-0002-erase-status-check.patch
View File

@ -1,7 +1,7 @@
From 413b2ed67d8e4dc1242edb9286ea3f634d10a6ba Mon Sep 17 00:00:00 2001
From 543f839e6fbeb325e6fa201e205ab18a46e37424 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 15 Jul 2013 00:38:51 +0200
Subject: [PATCH 32/33] mtd: fix cfi cmdset 0002 erase status check
Subject: [PATCH 128/133] mtd: fix cfi cmdset 0002 erase status check
---
drivers/mtd/chips/cfi_cmdset_0002.c | 4 ++--

4
target/linux/ramips/patches-3.10/0119-mtd-cfi-cmdset-0002-force-word-write.patch → target/linux/ramips/patches-3.10/0129-mtd-cfi-cmdset-0002-force-word-write.patch
View File

@ -1,7 +1,7 @@
From d5b094ea6d435817d295d554d652a97a5014c64f Mon Sep 17 00:00:00 2001
From 0ffe6cdf77793536a77b5c85cf41deb27cfc7632 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 15 Jul 2013 00:39:21 +0200
Subject: [PATCH 33/33] mtd: cfi cmdset 0002 force word write
Subject: [PATCH 129/133] mtd: cfi cmdset 0002 force word write
---
drivers/mtd/chips/cfi_cmdset_0002.c | 9 +++++++--

7
target/linux/ramips/patches-3.10/0250-nand-7620.patch → target/linux/ramips/patches-3.10/0130-mtd-ralink-add-mt7620-nand-driver.patch
View File

@ -1,7 +1,7 @@
From a5fc495c8dc199ffa997d43331693a5b7ee07270 Mon Sep 17 00:00:00 2001
From bea6f4b28443b7603e25b2404ad787a97f80fc59 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 17 Nov 2013 17:41:46 +0100
Subject: [PATCH] ralink: add mt7620 nand driver
Subject: [PATCH 130/133] mtd: ralink: add mt7620 nand driver
Signed-off-by: John Crispin <blogic@openwrt.org>
---
@ -9,8 +9,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
drivers/mtd/maps/Makefile | 2 +
drivers/mtd/maps/ralink_nand.c | 2136 ++++++++++++++++++++++++++++++++++++++++
drivers/mtd/maps/ralink_nand.h | 232 +++++
drivers/mtd/nand/Makefile | 2 +-
5 files changed, 2375 insertions(+), 1 deletion(-)
4 files changed, 2374 insertions(+)
create mode 100644 drivers/mtd/maps/ralink_nand.c
create mode 100644 drivers/mtd/maps/ralink_nand.h

4
target/linux/ramips/patches-3.10/0206-MTD-add-chunked-read-io-to-m25p80.patch → target/linux/ramips/patches-3.10/0131-mtd-add-chunked-read-io-to-m25p80.patch
View File

@ -1,7 +1,7 @@
From 926ae0ca5017a421709ab0478582683c29988b05 Mon Sep 17 00:00:00 2001
From f85e6dacdb7d7a9bc37f33cf8770006ab64286f7 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Wed, 27 Nov 2013 20:58:16 +0100
Subject: [PATCH 10/20] MTD: add chunked read io to m25p80
Subject: [PATCH 131/133] mtd: add chunked read io to m25p80
Signed-off-by: John Crispin <blogic@openwrt.org>
---

4
target/linux/ramips/patches-3.10/0200-owrt-GPIO-add-gpio_export_with_name.patch → target/linux/ramips/patches-3.10/0132-GPIO-add-gpio_export_with_name.patch
View File

@ -1,7 +1,7 @@
From 8f3ed1fffa35d18c2b20ebb866c71a22cc0589ff Mon Sep 17 00:00:00 2001
From def7e226d3e5c501180bdc2fc644ff924b5a275e Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 23 Jun 2013 00:16:22 +0200
Subject: [PATCH 29/33] owrt: GPIO: add gpio_export_with_name
Subject: [PATCH 132/133] GPIO: add gpio_export_with_name
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-November/133856.html

15
target/linux/ramips/patches-3.10/0205-uvc-add-iPassion-iP2970-support.patch → target/linux/ramips/patches-3.10/0133-uvc-add-iPassion-iP2970-support.patch
View File

@ -1,16 +1,15 @@
From be8d5b55f93b8ccb3a6b5cfb1e858a59aeca2d6c Mon Sep 17 00:00:00 2001
From 935815cd3b9690b86e70a18fb755f70becb57cc6 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Thu, 19 Sep 2013 01:50:59 +0200
Subject: [PATCH] uvc: add iPassion iP2970 support
Subject: [PATCH 133/133] uvc: add iPassion iP2970 support
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/media/usb/uvc/uvc_driver.c | 12 +++++++++
drivers/media/usb/uvc/uvc_status.c | 2 ++
drivers/media/usb/uvc/uvc_v4l2.c | 1 +
drivers/media/usb/uvc/uvc_video.c | 50 +++++++++++++++++++++++++++++++-----
drivers/media/usb/uvc/uvcvideo.h | 3 +++
5 files changed, 61 insertions(+), 7 deletions(-)
drivers/media/usb/uvc/uvc_driver.c | 14 ++++
drivers/media/usb/uvc/uvc_status.c | 2 +
drivers/media/usb/uvc/uvc_video.c | 147 ++++++++++++++++++++++++++++++++++++
drivers/media/usb/uvc/uvcvideo.h | 3 +
4 files changed, 166 insertions(+)
--- a/drivers/media/usb/uvc/uvc_driver.c
+++ b/drivers/media/usb/uvc/uvc_driver.c

0
target/linux/ramips/patches-3.10/0204-owrt-mtd-split-remove-padding.patch → target/linux/ramips/patches-3.10/0134-mtd-split-remove-padding.patch
View File

60
target/linux/ramips/patches-3.10/0200-MIPS-Fix-TLBR-use-hazards-for-R2-cores-in-the-TLB-re.patch Normal file
View File

@ -0,0 +1,60 @@
From f281fdccbb3e762d293e6eef7f291a33b84e0f6a Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Thu, 20 Jun 2013 14:56:17 +0200
Subject: [PATCH 200/215] MIPS: Fix TLBR-use hazards for R2 cores in the TLB
reload handlers
MIPS R2 documents state that an execution hazard barrier is needed
after a TLBR before reading EntryLo.
Original patch by Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/5526/
(cherry picked from commit 73acc7df534ff458a81435178dab3ea037ed6d78)
---
arch/mips/mm/tlbex.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -1935,6 +1935,19 @@ static void __cpuinit build_r4000_tlb_lo
uasm_i_nop(&p);
uasm_i_tlbr(&p);
+
+ switch (current_cpu_type()) {
+ default:
+ if (cpu_has_mips_r2) {
+ uasm_i_ehb(&p);
+
+ case CPU_CAVIUM_OCTEON:
+ case CPU_CAVIUM_OCTEON_PLUS:
+ case CPU_CAVIUM_OCTEON2:
+ break;
+ }
+ }
+
/* Examine entrylo 0 or 1 based on ptr. */
if (use_bbit_insns()) {
uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);
@@ -1989,6 +2002,19 @@ static void __cpuinit build_r4000_tlb_lo
uasm_i_nop(&p);
uasm_i_tlbr(&p);
+
+ switch (current_cpu_type()) {
+ default:
+ if (cpu_has_mips_r2) {
+ uasm_i_ehb(&p);
+
+ case CPU_CAVIUM_OCTEON:
+ case CPU_CAVIUM_OCTEON_PLUS:
+ case CPU_CAVIUM_OCTEON2:
+ break;
+ }
+ }
+
/* Examine entrylo 0 or 1 based on ptr. */
if (use_bbit_insns()) {
uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8);

4
target/linux/ramips/patches-3.10/0508-MIPS-GIC-Fix-gic_set_affinity-infinite-loop.patch → target/linux/ramips/patches-3.10/0201-MIPS-GIC-Fix-gic_set_affinity-infinite-loop.patch
View File

@ -1,7 +1,7 @@
From 553ddf4f3f20c28ab03f87ac8c3cde5edf714675 Mon Sep 17 00:00:00 2001
From cde59bef2f155fc38413e470ff0e4672623cdbec Mon Sep 17 00:00:00 2001
From: Tony Wu <tung7970@gmail.com>
Date: Fri, 21 Jun 2013 10:13:08 +0000
Subject: [PATCH 022/105] MIPS: GIC: Fix gic_set_affinity infinite loop
Subject: [PATCH 201/215] MIPS: GIC: Fix gic_set_affinity infinite loop
There is an infinite loop in gic_set_affinity. When irq_set_affinity
gets called on gic controller, it blocks forever.

4
target/linux/ramips/patches-3.10/0510-MIPS-Fix-SMP-core-calculations-when-using-MT-support.patch → target/linux/ramips/patches-3.10/0202-MIPS-Fix-SMP-core-calculations-when-using-MT-support.patch
View File

@ -1,7 +1,7 @@
From c4d621e75e865fa5374946515ad0c5e060b9c446 Mon Sep 17 00:00:00 2001
From 46b62174f655edf6a4befae7f9871c431146b1b6 Mon Sep 17 00:00:00 2001
From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Date: Wed, 11 Sep 2013 14:17:47 -0500
Subject: [PATCH 056/105] MIPS: Fix SMP core calculations when using MT
Subject: [PATCH 202/215] MIPS: Fix SMP core calculations when using MT
support.
The TCBIND register is only available if the core has MT support. It

84
target/linux/ramips/patches-3.10/0203-MIPS-Fix-accessing-to-per-cpu-data-when-flushing-the.patch Normal file
View File

@ -0,0 +1,84 @@
From 871d1be8c3ce46b8ef395b56cd0e37cede10e76a Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Tue, 17 Sep 2013 12:44:31 +0200
Subject: [PATCH 203/215] MIPS: Fix accessing to per-cpu data when flushing
the cache
This fixes the following issue
BUG: using smp_processor_id() in preemptible [00000000] code: kjournald/1761
caller is blast_dcache32+0x30/0x254
Call Trace:
[<8047f02c>] dump_stack+0x8/0x34
[<802e7e40>] debug_smp_processor_id+0xe0/0xf0
[<80114d94>] blast_dcache32+0x30/0x254
[<80118484>] r4k_dma_cache_wback_inv+0x200/0x288
[<80110ff0>] mips_dma_map_sg+0x108/0x180
[<80355098>] ide_dma_prepare+0xf0/0x1b8
[<8034eaa4>] do_rw_taskfile+0x1e8/0x33c
[<8035951c>] ide_do_rw_disk+0x298/0x3e4
[<8034a3c4>] do_ide_request+0x2e0/0x704
[<802bb0dc>] __blk_run_queue+0x44/0x64
[<802be000>] queue_unplugged.isra.36+0x1c/0x54
[<802beb94>] blk_flush_plug_list+0x18c/0x24c
[<802bec6c>] blk_finish_plug+0x18/0x48
[<8026554c>] journal_commit_transaction+0x3b8/0x151c
[<80269648>] kjournald+0xec/0x238
[<8014ac00>] kthread+0xb8/0xc0
[<8010268c>] ret_from_kernel_thread+0x14/0x1c
Caches in most systems are identical - but not always, so we can't avoid
the use of smp_call_function() by just looking at the boot CPU's data,
have to fiddle with preemption instead.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5835
(cherry picked from commit ff522058bd717506b2fa066fa564657f2b86477e)
---
arch/mips/mm/c-r4k.c | 5 +++++
1 file changed, 5 insertions(+)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -12,6 +12,7 @@
#include <linux/highmem.h>
#include <linux/kernel.h>
#include <linux/linkage.h>
+#include <linux/preempt.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/mm.h>
@@ -601,6 +602,7 @@ static void r4k_dma_cache_wback_inv(unsi
/* Catch bad driver code */
BUG_ON(size == 0);
+ preempt_disable();
if (cpu_has_inclusive_pcaches) {
if (size >= scache_size)
r4k_blast_scache();
@@ -621,6 +623,7 @@ static void r4k_dma_cache_wback_inv(unsi
R4600_HIT_CACHEOP_WAR_IMPL;
blast_dcache_range(addr, addr + size);
}
+ preempt_enable();
bc_wback_inv(addr, size);
__sync();
@@ -631,6 +634,7 @@ static void r4k_dma_cache_inv(unsigned l
/* Catch bad driver code */
BUG_ON(size == 0);
+ preempt_disable();
if (cpu_has_inclusive_pcaches) {
if (size >= scache_size)
r4k_blast_scache();
@@ -655,6 +659,7 @@ static void r4k_dma_cache_inv(unsigned l
R4600_HIT_CACHEOP_WAR_IMPL;
blast_inv_dcache_range(addr, addr + size);
}
+ preempt_enable();
bc_inv(addr, size);
__sync();

11
target/linux/ramips/patches-3.10/0203-serial-rt5350-fix-enable-uartf-kernel-panic.patch
View File

@ -1,11 +0,0 @@
--- a/drivers/tty/serial/8250/8250_core.c
+++ b/drivers/tty/serial/8250/8250_core.c
@@ -2499,7 +2499,7 @@ serial8250_pm(struct uart_port *port, un
static unsigned int serial8250_port_size(struct uart_8250_port *pt)
{
if (pt->port.iotype == UPIO_AU)
- return 0x1000;
+ return 0x100;
if (is_omap1_8250(pt))
return 0x16 << pt->port.regshift;

60
target/linux/ramips/patches-3.10/0204-MIPS-74K-1074K-Correct-erratum-workaround.patch Normal file
View File

@ -0,0 +1,60 @@
From 3da3528448850ccde412d52fb939575641ada80d Mon Sep 17 00:00:00 2001
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Wed, 18 Sep 2013 19:08:15 +0100
Subject: [PATCH 204/215] MIPS: 74K/1074K: Correct erratum workaround.
Make sure 74K revision numbers are not applied to the 1074K. Also catch
invalid usage.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5857/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
(cherry picked from commit 9213ad77070ea75fc3a5e43e3d9e9c4146e4930a)
---
arch/mips/mm/c-r4k.c | 26 ++++++++++++++++++--------
1 file changed, 18 insertions(+), 8 deletions(-)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -785,20 +785,30 @@ static inline void rm7k_erratum31(void)
static inline void alias_74k_erratum(struct cpuinfo_mips *c)
{
+ unsigned int imp = c->processor_id & 0xff00;
+ unsigned int rev = c->processor_id & PRID_REV_MASK;
+
/*
* Early versions of the 74K do not update the cache tags on a
* vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
* aliases. In this case it is better to treat the cache as always
* having aliases.
*/
- if ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(2, 4, 0))
- c->dcache.flags |= MIPS_CACHE_VTAG;
- if ((c->processor_id & 0xff) == PRID_REV_ENCODE_332(2, 4, 0))
- write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
- if (((c->processor_id & 0xff00) == PRID_IMP_1074K) &&
- ((c->processor_id & 0xff) <= PRID_REV_ENCODE_332(1, 1, 0))) {
- c->dcache.flags |= MIPS_CACHE_VTAG;
- write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+ switch (imp) {
+ case PRID_IMP_74K:
+ if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
+ c->dcache.flags |= MIPS_CACHE_VTAG;
+ if (rev == PRID_REV_ENCODE_332(2, 4, 0))
+ write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+ break;
+ case PRID_IMP_1074K:
+ if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
+ c->dcache.flags |= MIPS_CACHE_VTAG;
+ write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
+ }
+ break;
+ default:
+ BUG();
}
}

4
target/linux/ramips/patches-3.10/0511-MIPS-GIC-Send-IPIs-using-the-GIC.patch → target/linux/ramips/patches-3.10/0205-MIPS-GIC-Send-IPIs-using-the-GIC.patch
View File

@ -1,7 +1,7 @@
From 43334f8438704001deb258b6e7223699bd336c77 Mon Sep 17 00:00:00 2001
From 5a43b20db2fd18f8ea5f3a919d4bc9d9c2038c6c Mon Sep 17 00:00:00 2001
From: "Steven J. Hill" <Steven.Hill@imgtec.com>
Date: Wed, 25 Sep 2013 14:58:19 -0500
Subject: [PATCH 093/105] MIPS: GIC: Send IPIs using the GIC.
Subject: [PATCH 205/215] MIPS: GIC: Send IPIs using the GIC.
If a GIC present, then use it to send IPIs between the cores.

232
target/linux/ramips/patches-3.10/0502-MIPS-ralink-add-MT7621-support.patch → target/linux/ramips/patches-3.10/0206-MIPS-ralink-add-MT7621-support.patch
View File

@ -1,23 +1,39 @@
From 99342a0481d49b6e1ade90fdb02f597cb75f103f Mon Sep 17 00:00:00 2001
From 259ce690b20562aa5dfef711e72ed02a4f514ce4 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 2 Dec 2013 16:11:09 +0100
Subject: [PATCH 502/507] MIPS: ralink: add MT7621 support
Date: Sun, 16 Mar 2014 05:19:37 +0000
Subject: [PATCH 206/215] MIPS: ralink: add MT7621 support
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/include/asm/mach-ralink/mt7621.h | 39 +++++
arch/mips/include/asm/gic.h | 2 +
arch/mips/include/asm/mach-ralink/mt7621.h | 39 ++++
arch/mips/kernel/vmlinux.lds.S | 1 +
arch/mips/ralink/Kconfig | 18 ++
arch/mips/ralink/Makefile | 7 +-
arch/mips/ralink/Platform | 5 +
arch/mips/ralink/irq-gic.c | 255 ++++++++++++++++++++++++++++
arch/mips/ralink/Platform | 7 +
arch/mips/ralink/irq-gic.c | 271 ++++++++++++++++++++++++++++
arch/mips/ralink/malta-amon.c | 81 +++++++++
arch/mips/ralink/mt7621.c | 186 ++++++++++++++++++++
7 files changed, 590 insertions(+), 1 deletion(-)
arch/mips/ralink/mt7621.c | 183 +++++++++++++++++++
9 files changed, 608 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/include/asm/mach-ralink/mt7621.h
create mode 100644 arch/mips/ralink/irq-gic.c
create mode 100644 arch/mips/ralink/malta-amon.c
create mode 100644 arch/mips/ralink/mt7621.c
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -19,7 +19,11 @@
#define GIC_TRIG_EDGE 1
#define GIC_TRIG_LEVEL 0
+#define GIC_NUM_INTRS 64
+
+#ifndef GIC_NUM_INTRS
#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
+#endif
#define MSK(n) ((1 << (n)) - 1)
#define REG32(addr) (*(volatile unsigned int *) (addr))
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/mt7621.h
@@ -0,0 +1,39 @@
@ -60,19 +76,30 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
+
+#endif
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -51,6 +51,7 @@ SECTIONS
/* read-only */
_text = .; /* Text and read-only data */
.text : {
+ /*. = . + 0x8000; */
TEXT_TEXT
SCHED_TEXT
LOCK_TEXT
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -1,5 +1,10 @@
if RALINK
@@ -7,6 +7,11 @@ config CLKEVT_RT3352
select CLKSRC_OF
select CLKSRC_MMIO
+config IRQ_INTC
+ bool
+ default y
+ depends on !SOC_MT7621
+
config CLKEVT_RT3352
bool "Systick Clockevent source"
depends on SOC_RT305X || SOC_MT7620
choice
prompt "Ralink SoC selection"
default SOC_RT305X
@@ -35,6 +40,15 @@ choice
select USB_ARCH_HAS_EHCI
select HW_HAS_PCI
@ -102,20 +129,22 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
endif
--- a/arch/mips/ralink/Makefile
+++ b/arch/mips/ralink/Makefile
@@ -6,7 +6,11 @@
@@ -6,16 +6,21 @@
# Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
# Copyright (C) 2013 John Crispin <blogic@openwrt.org>
-obj-y := prom.o of.o reset.o clk.o irq.o timer.o
+obj-y := prom.o of.o reset.o clk.o timer.o
+
+obj-$(CONFIG_IRQ_INTC) += irq.o
+obj-$(CONFIG_IRQ_GIC) += irq-gic.o
+obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
@@ -16,6 +20,7 @@ obj-$(CONFIG_SOC_RT288X) += rt288x.o
obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
+obj-$(CONFIG_IRQ_INTC) += irq.o
+obj-$(CONFIG_IRQ_GIC) += irq-gic.o
+obj-$(CONFIG_MIPS_MT_SMP) += malta-amon.o
+
obj-$(CONFIG_SOC_RT288X) += rt288x.o
obj-$(CONFIG_SOC_RT305X) += rt305x.o
obj-$(CONFIG_SOC_RT3883) += rt3883.o
obj-$(CONFIG_SOC_MT7620) += mt7620.o
@ -138,7 +167,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+cflags-$(CONFIG_SOC_MT7620) += -I$(srctree)/arch/mips/include/asm/mach-ralink/mt7621
--- /dev/null
+++ b/arch/mips/ralink/irq-gic.c
@@ -0,0 +1,255 @@
@@ -0,0 +1,271 @@
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
@ -162,61 +191,20 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+
+#include <asm/mach-ralink/mt7621.h>
+
+static unsigned long _gcmp_base;
+unsigned long _gcmp_base;
+static int gic_resched_int_base = 56;
+static int gic_call_int_base = 60;
+static struct irq_chip *irq_gic;
+static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS];
+
+#if defined(CONFIG_MIPS_MT_SMP)
+static int gic_resched_int_base;
+static int gic_call_int_base;
+
+#define GIC_RESCHED_INT(cpu) (gic_resched_int_base+(cpu))
+#define GIC_CALL_INT(cpu) (gic_call_int_base+(cpu))
+
+static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //0
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+ { GIC_UNUSED },
+ { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //FE
+ { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //PCIE0
+ { GIC_UNUSED},
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //10
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+ { GIC_UNUSED },
+ { GIC_UNUSED },
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //20
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+ { GIC_UNUSED },
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, //25
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },//30
+ { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
+};
+
+static struct gic_intr_map ipi_intr_map[8] = {
+ { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
+ { 1, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
+ { 2, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
+ { 3, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
+ { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
+ { 1, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
+ { 2, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
+ { 3, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_EDGE, GIC_FLAG_IPI },
+};
+
+static irqreturn_t
+ipi_resched_interrupt(int irq, void *dev_id)
+static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
+{
+ scheduler_ipi();
+
@ -243,6 +231,43 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ .name = "ipi call"
+};
+
+#endif
+
+static void __init
+gic_fill_map(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(gic_intr_map); i++) {
+ gic_intr_map[i].cpunum = 0;
+ gic_intr_map[i].pin = GIC_CPU_INT0;
+ gic_intr_map[i].polarity = GIC_POL_POS;
+ gic_intr_map[i].trigtype = GIC_TRIG_LEVEL;
+ gic_intr_map[i].flags = GIC_FLAG_IPI;
+ }
+
+#if defined(CONFIG_MIPS_MT_SMP)
+ {
+ int cpu;
+
+ gic_call_int_base = ARRAY_SIZE(gic_intr_map) - nr_cpu_ids;
+ gic_resched_int_base = gic_call_int_base - nr_cpu_ids;
+
+ i = gic_resched_int_base;
+
+ for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
+ gic_intr_map[i + cpu].cpunum = cpu;
+ gic_intr_map[i + cpu].pin = GIC_CPU_INT1;
+ gic_intr_map[i + cpu].trigtype = GIC_TRIG_EDGE;
+
+ gic_intr_map[i + cpu + nr_cpu_ids].cpunum = cpu;
+ gic_intr_map[i + cpu + nr_cpu_ids].pin = GIC_CPU_INT2;
+ gic_intr_map[i + cpu + nr_cpu_ids].trigtype = GIC_TRIG_EDGE;
+ }
+ }
+#endif
+}
+
+void
+gic_irq_ack(struct irq_data *d)
+{
@ -267,12 +292,17 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+}
+
+static void
+vi_gic_irqdispatch(void)
+gic_irqdispatch(void)
+{
+ int irq = gic_get_int();
+ unsigned int irq = gic_get_int();
+
+ if (irq >= 0)
+ if (likely(irq < GIC_NUM_INTRS))
+ do_IRQ(MIPS_GIC_IRQ_BASE + irq);
+ else {
+ pr_err("Spurious GIC Interrupt!\n");
+ spurious_interrupt();
+ }
+
+}
+
+static void
@ -281,6 +311,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ do_IRQ(cp0_compare_irq);
+}
+
+#if defined(CONFIG_MIPS_MT_SMP)
+unsigned int
+plat_ipi_call_int_xlate(unsigned int cpu)
+{
@ -292,18 +323,23 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+{
+ return GIC_RESCHED_INT(cpu);
+}
+#endif
+
+asmlinkage void
+plat_irq_dispatch(void)
+{
+ unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
+
+ if (pending & CAUSEF_IP7)
+ do_IRQ(cp0_compare_irq);
+ else if (pending & (CAUSEF_IP4 | CAUSEF_IP3))
+ vi_gic_irqdispatch();
+ else
+ if (unlikely(!pending)) {
+ pr_err("Spurious CP0 Interrupt!\n");
+ spurious_interrupt();
+ } else {
+ if (pending & CAUSEF_IP7)
+ do_IRQ(cp0_compare_irq);
+
+ if (pending & (CAUSEF_IP4 | CAUSEF_IP3 | CAUSEF_IP2))
+ gic_irqdispatch();
+ }
+}
+
+unsigned int __cpuinit
@ -315,7 +351,12 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+static int
+gic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
+{
+ irq_set_chip_and_handler(irq, irq_gic, handle_percpu_irq);
+ irq_set_chip_and_handler(irq, irq_gic,
+#if defined(CONFIG_MIPS_MT_SMP)
+ (hw >= gic_resched_int_base) ?
+ handle_percpu_irq :
+#endif
+ handle_level_irq);
+
+ return 0;
+}
@ -356,12 +397,14 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ GCMPGCB(GICBA) = gic.start | GCMP_GCB_GICBA_EN_MSK;
+ gic_present = 1;
+ if (cpu_has_vint) {
+ set_vi_handler(3, vi_gic_irqdispatch);
+ set_vi_handler(4, vi_gic_irqdispatch);
+ set_vi_handler(2, gic_irqdispatch);
+ set_vi_handler(3, gic_irqdispatch);
+ set_vi_handler(4, gic_irqdispatch);
+ set_vi_handler(7, vi_timer_irqdispatch);
+ }
+
+ memcpy(&gic_intr_map[gic_resched_int_base], ipi_intr_map, sizeof(ipi_intr_map));
+ gic_fill_map();
+
+ gic_init(gic.start, resource_size(&gic), gic_intr_map,
+ ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
+
@ -373,13 +416,15 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ if (!domain)
+ panic("Failed to add irqdomain");
+
+ for (i = 0; i < NR_CPUS; i++) {
+#if defined(CONFIG_MIPS_MT_SMP)
+ for (i = 0; i < nr_cpu_ids; i++) {
+ setup_irq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
+ setup_irq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
+ }
+#endif
+
+ change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | STATUSF_IP6 |
+ STATUSF_IP7);
+ change_c0_status(ST0_IM, STATUSF_IP7 | STATUSF_IP4 | STATUSF_IP3 |
+ STATUSF_IP2);
+ return 0;
+}
+
@ -480,7 +525,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+}
--- /dev/null
+++ b/arch/mips/ralink/mt7621.c
@@ -0,0 +1,186 @@
@@ -0,0 +1,183 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
@ -499,6 +544,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+#include <asm/gcmpregs.h>
+
+#include <asm/mipsregs.h>
+#include <asm/smp-ops.h>
+#include <asm/mach-ralink/ralink_regs.h>
+#include <asm/mach-ralink/mt7621.h>
+
@ -597,22 +643,17 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ cpu_fdiv = ((clk_sts >> 8) & 0x1F);
+ cpu_ffrac = (clk_sts & 0x1F);
+ cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000;
+ printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ break;
+
+ case 1:
+ fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1;
+ syscfg = rt_sysc_r32(SYSC_REG_SYSCFG);
+ xtal_mode = (syscfg >> 6) & 0x7;
+ printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ if(xtal_mode >= 6) { //25Mhz Xtal
+ printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ cpu_clk = 25 * fbdiv * 1000 * 1000;
+ } else if(xtal_mode >=3) { //40Mhz Xtal
+ printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ cpu_clk = 40 * fbdiv * 1000 * 1000;
+ } else { // 20Mhz Xtal
+ printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
+ cpu_clk = 20 * fbdiv * 1000 * 1000;
+ }
+ break;
@ -621,6 +662,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ ralink_clk_add("cpu", cpu_clk);
+ ralink_clk_add("1e000b00.spi", 50000000);
+ ralink_clk_add("1e000c00.uartlite", 50000000);
+ ralink_clk_add("1e000d00.uart", 50000000);
+}
+
+void __init ralink_of_remap(void)
@ -667,3 +709,15 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+ if (register_cmp_smp_ops())
+ panic("failed to register_vsmp_smp_ops()");
+}
--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/irq.h
@@ -0,0 +1,9 @@
+#ifndef __ASM_MACH_RALINK_IRQ_H
+#define __ASM_MACH_RALINK_IRQ_H
+
+#define GIC_NUM_INTRS 64
+#define NR_IRQS 256
+
+#include_next <irq.h>
+
+#endif

211
target/linux/ramips/patches-3.10/0207-MIPS-ralink-add-MT7621-defconfig.patch Normal file
View File

@ -0,0 +1,211 @@
From 29b1c70ab171609fee58ef6642086d571c0ba0c2 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 27 Jan 2014 13:12:41 +0000
Subject: [PATCH 207/215] MIPS: ralink: add MT7621 defconfig
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/configs/mt7621_defconfig | 197 ++++++++++++++++++++++++++++++++++++
1 file changed, 197 insertions(+)
create mode 100644 arch/mips/configs/mt7621_defconfig
--- /dev/null
+++ b/arch/mips/configs/mt7621_defconfig
@@ -0,0 +1,197 @@
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_RCU_FANOUT=32
+CONFIG_UIDGID_STRICT_TYPE_CHECKS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="/openwrt/trunk/build_dir/target-mipsel_24kec+dsp_uClibc-0.9.33.2/root-ramips /openwrt/trunk/target/linux/generic/image/initramfs-base-files.txt"
+CONFIG_INITRAMFS_ROOT_UID=1000
+CONFIG_INITRAMFS_ROOT_GID=1000
+# CONFIG_RD_GZIP is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+# CONFIG_AIO is not set
+CONFIG_EMBEDDED=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_SMP=y
+CONFIG_NR_CPUS=4
+CONFIG_SCHED_SMT=y
+# CONFIG_COMPACTION is not set
+# CONFIG_CROSS_MEMORY_ATTACH is not set
+# CONFIG_SECCOMP is not set
+CONFIG_HZ_100=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
+CONFIG_ARPD=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+# CONFIG_TCP_CONG_BIC is not set
+# CONFIG_TCP_CONG_WESTWOOD is not set
+# CONFIG_TCP_CONG_HTCP is not set
+CONFIG_IPV6_PRIVACY=y
+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET6_XFRM_MODE_BEET is not set
+# CONFIG_IPV6_SIT is not set
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_NETFILTER=y
+# CONFIG_BRIDGE_NETFILTER is not set
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NETFILTER_XT_MARK=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NF_CONNTRACK_IPV4=m
+# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_NF_NAT_IPV4=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_RAW=m
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+CONFIG_BRIDGE=m
+# CONFIG_BRIDGE_IGMP_SNOOPING is not set
+CONFIG_VLAN_8021Q=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_FQ_CODEL=y
+CONFIG_HAMRADIO=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_EEPROM_93CX6=m
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_PHYLIB=y
+CONFIG_SWCONFIG=y
+CONFIG_PPP=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=m
+CONFIG_PPP_ASYNC=m
+CONFIG_ISDN=y
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SPI=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_VGA_ARB is not set
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USB_MT7621_XHCI_PLATFORM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_PHY=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_STAGING=y
+CONFIG_USB_DWC2=m
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_FIRMWARE_MEMMAP is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
+CONFIG_TMPFS_XATTR=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+# CONFIG_JFFS2_FS_POSIX_ACL is not set
+# CONFIG_JFFS2_FS_SECURITY is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+# CONFIG_JFFS2_ZLIB is not set
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_ZLIB is not set
+CONFIG_SQUASHFS_XZ=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_STRIP_ASM_SYMS=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_REDUCED=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+# CONFIG_FTRACE is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_VIRTUALIZATION is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32_SARWATE=y
+# CONFIG_XZ_DEC_X86 is not set
+CONFIG_AVERAGE=y

300
target/linux/ramips/patches-3.10/0208-MIPS-ralink-add-MT7621-dts-file.patch Normal file
View File

@ -0,0 +1,300 @@
From dd4f939bb7c30f9256a35d31de673241ead350ab Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Fri, 24 Jan 2014 17:01:22 +0100
Subject: [PATCH 208/215] MIPS: ralink: add MT7621 dts file
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/ralink/dts/Makefile | 1 +
arch/mips/ralink/dts/mt7621.dtsi | 257 ++++++++++++++++++++++++++++++++++
arch/mips/ralink/dts/mt7621_eval.dts | 16 +++
3 files changed, 274 insertions(+)
create mode 100644 arch/mips/ralink/dts/mt7621.dtsi
create mode 100644 arch/mips/ralink/dts/mt7621_eval.dts
--- a/arch/mips/ralink/dts/Makefile
+++ b/arch/mips/ralink/dts/Makefile
@@ -2,3 +2,4 @@ obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_
obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
obj-$(CONFIG_DTB_MT7620A_EVAL) := mt7620a_eval.dtb.o
+obj-$(CONFIG_DTB_MT7621_EVAL) := mt7621_eval.dtb.o
--- /dev/null
+++ b/arch/mips/ralink/dts/mt7621.dtsi
@@ -0,0 +1,257 @@
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ralink,mtk7620a-soc";
+
+ cpus {
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ };
+ };
+
+ cpuintc: cpuintc@0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ palmbus@1E000000 {
+ compatible = "palmbus";
+ reg = <0x1E000000 0x100000>;
+ ranges = <0x0 0x1E000000 0x0FFFFF>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sysc@0 {
+ compatible = "mtk,mt7621-sysc";
+ reg = <0x0 0x100>;
+ };
+
+ wdt@100 {
+ compatible = "mtk,mt7621-wdt";
+ reg = <0x100 0x100>;
+ };
+
+ gpio@600 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "mtk,mt7621-gpio";
+ reg = <0x600 0x100>;
+
+ gpio0: bank@0 {
+ reg = <0>;
+ compatible = "mtk,mt7621-gpio-bank";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio1: bank@1 {
+ reg = <1>;
+ compatible = "mtk,mt7621-gpio-bank";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ gpio2: bank@2 {
+ reg = <2>;
+ compatible = "mtk,mt7621-gpio-bank";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ memc@5000 {
+ compatible = "mtk,mt7621-memc";
+ reg = <0x300 0x100>;
+ };
+
+ uartlite@c00 {
+ compatible = "ns16550a";
+ reg = <0xc00 0x100>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <26>;
+
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ no-loopback-test;
+ };
+
+ uart@d00 {
+ compatible = "ns16550a";
+ reg = <0xd00 0x100>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <27>;
+
+ fifo-size = <16>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ no-loopback-test;
+ };
+
+ spi@b00 {
+ status = "okay";
+
+ compatible = "ralink,mt7621-spi";
+ reg = <0xb00 0x100>;
+
+ resets = <&rstctrl 18>;
+ reset-names = "spi";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+/* pinctrl-names = "default";
+ pinctrl-0 = <&spi_pins>;*/
+
+ m25p80@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "en25q64";
+ reg = <0 0>;
+ linux,modalias = "m25p80", "en25q64";
+ spi-max-frequency = <10000000>;
+
+ m25p,chunked-io;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x30000>;
+ read-only;
+ };
+
+ partition@30000 {
+ label = "u-boot-env";
+ reg = <0x30000 0x10000>;
+ read-only;
+ };
+
+ factory: partition@40000 {
+ label = "factory";
+ reg = <0x40000 0x10000>;
+ read-only;
+ };
+
+ partition@50000 {
+ label = "firmware";
+ reg = <0x50000 0x7a0000>;
+ };
+
+ partition@7f0000 {
+ label = "test";
+ reg = <0x7f0000 0x10000>;
+ };
+ };
+ };
+ };
+
+ rstctrl: rstctrl {
+ compatible = "ralink,rt2880-reset";
+ #reset-cells = <1>;
+ };
+
+ sdhci@1E130000 {
+ compatible = "ralink,mt7620a-sdhci";
+ reg = <0x1E130000 4000>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <20>;
+ };
+
+ xhci@1E1C0000 {
+ compatible = "xhci-platform";
+ reg = <0x1E1C0000 4000>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <22>;
+ };
+
+ gic: gic@1fbc0000 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "ralink,mt7621-gic";
+ reg = < 0x1fbc0000 0x80 /* gic */
+ 0x1fbf0000 0x8000 /* cpc */
+ 0x1fbf8000 0x8000 /* gpmc */
+ >;
+ };
+
+ nand@1e003000 {
+ compatible = "mtk,mt7621-nand";
+ bank-width = <2>;
+ reg = <0x1e003000 0x800
+ 0x1e003800 0x800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "uboot";
+ reg = <0x00000 0x80000>; /* 64 KB */
+ };
+ partition@80000 {
+ label = "uboot_env";
+ reg = <0x80000 0x80000>; /* 64 KB */
+ };
+ partition@100000 {
+ label = "factory";
+ reg = <0x100000 0x40000>;
+ };
+ partition@140000 {
+ label = "rootfs";
+ reg = <0x140000 0xec0000>;
+ };
+ };
+
+ ethernet@1e100000 {
+ compatible = "ralink,mt7621-eth";
+ reg = <0x1e100000 10000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ralink,port-map = "llllw";
+
+ interrupt-parent = <&gic>;
+ interrupts = <3>;
+
+/* resets = <&rstctrl 21 &rstctrl 23>;
+ reset-names = "fe", "esw";
+
+ port@4 {
+ compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
+ reg = <4>;
+
+ status = "disabled";
+ };
+
+ port@5 {
+ compatible = "ralink,mt7620a-gsw-port", "ralink,eth-port";
+ reg = <5>;
+
+ status = "disabled";
+ };
+*/
+ mdio-bus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy1f: ethernet-phy@1f {
+ reg = <0x1f>;
+ phy-mode = "rgmii";
+
+/* interrupt-parent = <&gic>;
+ interrupts = <23>;
+*/ };
+ };
+ };
+
+ gsw@1e110000 {
+ compatible = "ralink,mt7620a-gsw";
+ reg = <0x1e110000 8000>;
+ };
+};
--- /dev/null
+++ b/arch/mips/ralink/dts/mt7621_eval.dts
@@ -0,0 +1,16 @@
+/dts-v1/;
+
+/include/ "mt7621.dtsi"
+
+/ {
+ compatible = "ralink,mt7621-eval-board", "ralink,mt7621-soc";
+ model = "Ralink MT7621 evaluation board";
+
+ memory@0 {
+ reg = <0x0 0x2000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,57600";
+ };
+};

16
target/linux/ramips/patches-3.10/0503-MIPS-ralink-add-MT7621-early_printk-support.patch → target/linux/ramips/patches-3.10/0209-MIPS-ralink-add-MT7621-early_printk-support.patch
View File

@ -1,7 +1,7 @@
From 643e61b22155cd95ae6e18e57da50acd120da091 Mon Sep 17 00:00:00 2001
From a9d4390c6d27e737887388ccbb48f3767f9f89ef Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 2 Dec 2013 16:11:33 +0100
Subject: [PATCH 503/507] MIPS: ralink: add MT7621 early_printk support
Date: Fri, 24 Jan 2014 17:01:17 +0100
Subject: [PATCH 209/215] MIPS: ralink: add MT7621 early_printk support
Signed-off-by: John Crispin <blogic@openwrt.org>
---
@ -19,19 +19,19 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
#else
#define EARLY_UART_BASE 0x10000c00
#endif
@@ -40,9 +42,13 @@ static inline u32 uart_r32(unsigned reg)
@@ -40,9 +42,15 @@ static inline u32 uart_r32(unsigned reg)
void prom_putchar(unsigned char ch)
{
- while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
+#ifdef CONFIG_SOC_MT7621
+ uart_w32(ch, UART_TX);
+ while ((uart_r32(0x14) & UART_LSR_THRE) == 0)
;
- uart_w32(ch, UART_REG_TX);
+ ;
+#else
while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
;
+ uart_w32(ch, UART_REG_TX);
uart_w32(ch, UART_REG_TX);
while ((uart_r32(UART_REG_LSR) & UART_LSR_THRE) == 0)
;
+#endif
}

14
target/linux/ramips/patches-3.10/0504-MIPS-ralink-add-pcie-driver.patch → target/linux/ramips/patches-3.10/0210-MIPS-ralink-add-MT7621-pcie-driver.patch
View File

@ -1,7 +1,7 @@
From 50216a5b7b3cc269043e7123db4bea262e35364e Mon Sep 17 00:00:00 2001
From 6541090161342ef11cf319a7471aeb6769e20c2c Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 2 Dec 2013 16:13:40 +0100
Subject: [PATCH 504/507] MIPS: ralink: add pcie driver
Date: Sun, 16 Mar 2014 05:22:39 +0000
Subject: [PATCH 210/215] MIPS: ralink: add MT7621 pcie driver
Signed-off-by: John Crispin <blogic@openwrt.org>
---
@ -12,14 +12,14 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o
@@ -42,6 +42,7 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops
obj-$(CONFIG_LANTIQ) += fixup-lantiq.o
obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o
obj-$(CONFIG_SOC_MT7620) += pci-mt7620a.o
+obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o
obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o
+obj-$(CONFIG_SOC_MT7621) += pci-mt7621.o
obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
--- /dev/null
+++ b/arch/mips/pci/pci-mt7621.c
@@ -0,0 +1,797 @@

50
target/linux/ramips/patches-3.10/0505-watchdog-add-MT7621-support.patch → target/linux/ramips/patches-3.10/0211-watchdog-add-MT7621-support.patch
View File

@ -1,7 +1,7 @@
From eb50d97682d78af68388d24956a74de4ab751cf7 Mon Sep 17 00:00:00 2001
From 158f2deb6349046ee4406578a5d3146ce9870cb3 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 2 Dec 2013 16:18:36 +0100
Subject: [PATCH 505/507] watchdog: add MT7621 support
Date: Sun, 16 Mar 2014 05:24:42 +0000
Subject: [PATCH 211/215] watchdog: add MT7621 support
Signed-off-by: John Crispin <blogic@openwrt.org>
---
@ -11,27 +11,29 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
3 files changed, 193 insertions(+)
create mode 100644 drivers/watchdog/mt7621_wdt.c
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -1116,7 +1116,14 @@ config LANTIQ_WDT
config RALINK_WDT
tristate "Ralink SoC watchdog"
select WATCHDOG_CORE
- depends on RALINK
+ depends on RALINK && !SOC_MT7621
+ help
+ Hardware driver for the Ralink SoC Watchdog Timer.
+
+config MT7621_WDT
+ tristate "Mediatek SoC watchdog"
+ select WATCHDOG_CORE
+ depends on RALINK && SOC_MT7621
Index: linux-3.10.32/drivers/watchdog/Kconfig
===================================================================
--- linux-3.10.32.orig/drivers/watchdog/Kconfig 2014-03-18 11:00:30.629639835 +0000
+++ linux-3.10.32/drivers/watchdog/Kconfig 2014-03-18 11:02:35.141634769 +0000
@@ -1120,6 +1120,13 @@
help
Hardware driver for the Ralink SoC Watchdog Timer.
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -136,6 +136,7 @@ obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o
+config MT7621_WDT
+ tristate "Mediatek SoC watchdog"
+ select WATCHDOG_CORE
+ depends on SOC_MT7621
+ help
+ Hardware driver for the Ralink SoC Watchdog Timer.
+
# PARISC Architecture
# POWERPC Architecture
Index: linux-3.10.32/drivers/watchdog/Makefile
===================================================================
--- linux-3.10.32.orig/drivers/watchdog/Makefile 2014-03-18 11:00:30.629639835 +0000
+++ linux-3.10.32/drivers/watchdog/Makefile 2014-03-18 11:00:31.317639807 +0000
@@ -136,6 +136,7 @@
octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o
obj-$(CONFIG_LANTIQ_WDT) += lantiq_wdt.o
obj-$(CONFIG_RALINK_WDT) += rt2880_wdt.o
@ -39,8 +41,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
# PARISC Architecture
--- /dev/null
+++ b/drivers/watchdog/mt7621_wdt.c
Index: linux-3.10.32/drivers/watchdog/mt7621_wdt.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-3.10.32/drivers/watchdog/mt7621_wdt.c 2014-03-18 11:00:31.317639807 +0000
@@ -0,0 +1,185 @@
+/*
+ * Ralink RT288x/RT3xxx/MT76xx built-in hardware watchdog timer

50
target/linux/ramips/patches-3.10/0506-GPIO-ralink-add-mt7621-gpio-controller.patch → target/linux/ramips/patches-3.10/0212-GPIO-ralink-add-mt7621-gpio-controller.patch
View File

@ -1,41 +1,63 @@
From e19957560170d63c6a5f0b1d7ba63695e4d1f033 Mon Sep 17 00:00:00 2001
From 2a9b5a9fc1a0707b95dbe61dd1c30b9337cb457d Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 2 Dec 2013 16:14:28 +0100
Subject: [PATCH 506/507] GPIO: ralink: add mt7621 gpio controller
Date: Sun, 16 Mar 2014 05:26:34 +0000
Subject: [PATCH 212/215] GPIO: ralink: add mt7621 gpio controller
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/Kconfig | 1 +
arch/mips/Kconfig | 5 +-
drivers/gpio/Kconfig | 6 ++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-mt7621.c | 183 ++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 191 insertions(+)
4 files changed, 194 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpio/gpio-mt7621.c
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -710,6 +710,12 @@ config GPIO_MSIC
Index: linux-3.10.32/arch/mips/Kconfig
===================================================================
--- linux-3.10.32.orig/arch/mips/Kconfig 2014-03-18 11:00:30.945639822 +0000
+++ linux-3.10.32/arch/mips/Kconfig 2014-03-18 11:00:31.325639806 +0000
@@ -448,7 +448,10 @@
select ARCH_REQUIRE_GPIOLIB
select PINCTRL
select PINCTRL_RT2880
-
+ select ARCH_HAS_RESET_CONTROLLER
+ select RESET_CONTROLLER
+ select ARCH_REQUIRE_GPIOLIB
+
config SGI_IP22
bool "SGI IP22 (Indy/Indigo2)"
select FW_ARC
Index: linux-3.10.32/drivers/gpio/Kconfig
===================================================================
--- linux-3.10.32.orig/drivers/gpio/Kconfig 2014-03-18 11:00:30.653639834 +0000
+++ linux-3.10.32/drivers/gpio/Kconfig 2014-03-18 11:02:01.901636126 +0000
@@ -710,6 +710,12 @@
Enable support for GPIO on intel MSIC controllers found in
intel MID devices
+config GPIO_MT7621
+ bool "Mediatek GPIO Support"
+ depends on RALINK && SOC_MT7621
+ depends on SOC_MT7621
+ help
+ Say yes here to support the Mediatek SoC GPIO device
+
comment "USB GPIO expanders:"
config GPIO_VIPERBOARD
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -88,3 +88,4 @@ obj-$(CONFIG_GPIO_WM831X) += gpio-wm831x
Index: linux-3.10.32/drivers/gpio/Makefile
===================================================================
--- linux-3.10.32.orig/drivers/gpio/Makefile 2014-03-18 11:00:30.653639834 +0000
+++ linux-3.10.32/drivers/gpio/Makefile 2014-03-18 11:00:31.325639806 +0000
@@ -88,3 +88,4 @@
obj-$(CONFIG_GPIO_WM8350) += gpio-wm8350.o
obj-$(CONFIG_GPIO_WM8994) += gpio-wm8994.o
obj-$(CONFIG_GPIO_XILINX) += gpio-xilinx.o
+obj-$(CONFIG_GPIO_MT7621) += gpio-mt7621.o
--- /dev/null
+++ b/drivers/gpio/gpio-mt7621.c
Index: linux-3.10.32/drivers/gpio/gpio-mt7621.c
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
+++ linux-3.10.32/drivers/gpio/gpio-mt7621.c 2014-03-18 11:00:31.325639806 +0000
@@ -0,0 +1,183 @@
+/*
+ * This program is free software; you can redistribute it and/or modify it

34
target/linux/ramips/patches-3.10/0507-MTD-add-mt7621-nand-support.patch → target/linux/ramips/patches-3.10/0213-MTD-add-mt7621-nand-support.patch
View File

@ -1,7 +1,7 @@
From 203189714320fe43b4c0cf953efec9e28963c03b Mon Sep 17 00:00:00 2001
From 3598d232eb3456fa7aca78e6eeea64210b49c1fc Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 2 Dec 2013 16:23:57 +0100
Subject: [PATCH 507/507] MTD: add mt7621 nand support
Date: Fri, 24 Jan 2014 17:01:21 +0100
Subject: [PATCH 213/215] MTD: add mt7621 nand support
Signed-off-by: John Crispin <blogic@openwrt.org>
---
@ -14,11 +14,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
drivers/mtd/nand/mtk_nand.c | 2304 +++++++++++++++++++++++++++++++++++
drivers/mtd/nand/mtk_nand.h | 452 +++++++
drivers/mtd/nand/nand_base.c | 6 +-
drivers/mtd/nand/nand_bbt.c | 19 +
drivers/mtd/nand/nand_bbt.c | 41 +
drivers/mtd/nand/nand_def.h | 123 ++
drivers/mtd/nand/nand_device_list.h | 55 +
drivers/mtd/nand/partition.h | 115 ++
13 files changed, 4311 insertions(+), 3 deletions(-)
13 files changed, 4333 insertions(+), 3 deletions(-)
create mode 100644 drivers/mtd/nand/bmt.c
create mode 100644 drivers/mtd/nand/bmt.h
create mode 100644 drivers/mtd/nand/dev-nand.c
@ -4089,10 +4089,32 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
struct nand_chip *chip = mtd->priv;
--- a/drivers/mtd/nand/nand_bbt.c
+++ b/drivers/mtd/nand/nand_bbt.c
@@ -1378,6 +1378,25 @@ int nand_isbad_bbt(struct mtd_info *mtd,
@@ -1378,6 +1378,47 @@ int nand_isbad_bbt(struct mtd_info *mtd,
return 1;
}
+/**
+ * nand_markbad_bbt - [NAND Interface] Mark a block bad in the BBT
+ * @mtd: MTD device structure
+ * @offs: offset of the bad block
+ */
+int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs)
+{
+ struct nand_chip *this = mtd->priv;
+ int block, ret = 0;
+
+ block = (int)(offs >> this->bbt_erase_shift);
+
+ /* Mark bad block in memory */
+ bbt_mark_entry(this, block, BBT_BLOCK_WORN);
+
+ /* Update flash-based bad block table */
+ if (this->bbt_options & NAND_BBT_USE_FLASH)
+ ret = nand_update_bbt(mtd, offs);
+
+ return ret;
+}
+
+void nand_bbt_set(struct mtd_info *mtd, int page, int flag)
+{
+ struct nand_chip *this = mtd->priv;

5768
target/linux/ramips/patches-3.10/0214-usb-add-mt7621-xhci-support.patch Normal file
View File

File diff suppressed because it is too large Load Diff

38
target/linux/ramips/patches-3.10/0500-spi-mt7621.patch → target/linux/ramips/patches-3.10/0215-SPI-ralink-add-mt7621-support.patch
View File

@ -1,6 +1,16 @@
From 1a961f146e65e2716dbe9065baa4c0931fcb6b3e Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Sun, 16 Mar 2014 05:34:11 +0000
Subject: [PATCH 215/215] SPI: ralink: add mt7621 support
Signed-off-by: John Crispin <blogic@openwrt.org>
---
drivers/spi/spi-rt2880.c | 218 +++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 205 insertions(+), 13 deletions(-)
--- a/drivers/spi/spi-rt2880.c
+++ b/drivers/spi/spi-rt2880.c
@@ -21,8 +21,11 @@
@@ -21,8 +21,13 @@
#include <linux/io.h>
#include <linux/reset.h>
#include <linux/spi/spi.h>
@ -8,11 +18,13 @@
#include <linux/platform_device.h>
+#include <ralink_regs.h>
+
+#define SPI_BPW_MASK(bits) BIT((bits) - 1)
+
#define DRIVER_NAME "spi-rt2880"
/* only one slave is supported*/
#define RALINK_NUM_CHIPSELECTS 1
@@ -63,6 +66,25 @@
@@ -63,6 +68,25 @@
/* SPIFIFOSTAT register bit field */
#define SPIFIFOSTAT_TXFULL BIT(17)
@ -38,7 +50,7 @@
struct rt2880_spi {
struct spi_master *master;
void __iomem *base;
@@ -70,6 +92,8 @@ struct rt2880_spi {
@@ -70,6 +94,8 @@ struct rt2880_spi {
unsigned int speed;
struct clk *clk;
spinlock_t lock;
@ -47,7 +59,7 @@
};
static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
@@ -149,6 +173,17 @@ static int rt2880_spi_baudrate_set(struc
@@ -149,6 +175,17 @@ static int rt2880_spi_baudrate_set(struc
return 0;
}
@ -65,7 +77,7 @@
/*
* called only when no transfer is active on the bus
*/
@@ -164,7 +199,7 @@ rt2880_spi_setup_transfer(struct spi_dev
@@ -164,7 +201,7 @@ rt2880_spi_setup_transfer(struct spi_dev
if (rs->speed != speed) {
dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
@ -74,7 +86,7 @@
if (rc)
return rc;
}
@@ -180,6 +215,17 @@ static void rt2880_spi_set_cs(struct rt2
@@ -180,6 +217,17 @@ static void rt2880_spi_set_cs(struct rt2
rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
}
@ -92,7 +104,7 @@
static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
{
int i;
@@ -198,8 +244,26 @@ static inline int rt2880_spi_wait_till_r
@@ -198,8 +246,26 @@ static inline int rt2880_spi_wait_till_r
return -ETIMEDOUT;
}
@ -120,7 +132,7 @@
{
struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
unsigned count = 0;
@@ -239,6 +303,100 @@ out:
@@ -239,6 +305,100 @@ out:
return count;
}
@ -221,7 +233,7 @@
static int rt2880_spi_transfer_one_message(struct spi_master *master,
struct spi_message *m)
{
@@ -280,25 +438,25 @@ static int rt2880_spi_transfer_one_messa
@@ -280,25 +440,25 @@ static int rt2880_spi_transfer_one_messa
}
if (!cs_active) {
@ -251,7 +263,7 @@
m->status = status;
spi_finalize_current_message(master);
@@ -334,8 +492,41 @@ static void rt2880_spi_reset(struct rt28
@@ -334,8 +494,41 @@ static void rt2880_spi_reset(struct rt28
rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
}
@ -293,7 +305,7 @@
struct spi_master *master;
struct rt2880_spi *rs;
unsigned long flags;
@@ -344,6 +535,10 @@ static int rt2880_spi_probe(struct platf
@@ -344,6 +537,10 @@ static int rt2880_spi_probe(struct platf
int status = 0;
struct clk *clk;
@ -304,7 +316,7 @@
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&pdev->dev, r);
if (IS_ERR(base))
@@ -382,12 +577,13 @@ static int rt2880_spi_probe(struct platf
@@ -382,12 +579,13 @@ static int rt2880_spi_probe(struct platf
rs->clk = clk;
rs->master = master;
rs->sys_freq = clk_get_rate(rs->clk);
@ -319,7 +331,7 @@
return spi_register_master(master);
}
@@ -408,12 +604,6 @@ static int rt2880_spi_remove(struct plat
@@ -408,12 +606,6 @@ static int rt2880_spi_remove(struct plat
MODULE_ALIAS("platform:" DRIVER_NAME);

6045
target/linux/ramips/patches-3.10/0216-NET-ralink-add-mt7621-SDK-ethernet-driver.patch Normal file
View File

File diff suppressed because it is too large Load Diff

88
target/linux/ramips/patches-3.10/0217-pinmux-rt2880.patch Normal file
View File

@ -0,0 +1,88 @@
Index: linux-3.10.32/arch/mips/ralink/rt288x.c
===================================================================
--- linux-3.10.32.orig/arch/mips/ralink/rt288x.c 2014-02-22 20:41:54.000000000 +0000
+++ linux-3.10.32/arch/mips/ralink/rt288x.c 2014-03-18 11:18:06.689596876 +0000
@@ -17,46 +17,27 @@
#include <asm/mipsregs.h>
#include <asm/mach-ralink/ralink_regs.h>
#include <asm/mach-ralink/rt288x.h>
+#include <asm/mach-ralink/pinmux.h>
#include "common.h"
-static struct ralink_pinmux_grp mode_mux[] = {
- {
- .name = "i2c",
- .mask = RT2880_GPIO_MODE_I2C,
- .gpio_first = 1,
- .gpio_last = 2,
- }, {
- .name = "spi",
- .mask = RT2880_GPIO_MODE_SPI,
- .gpio_first = 3,
- .gpio_last = 6,
- }, {
- .name = "uartlite",
- .mask = RT2880_GPIO_MODE_UART0,
- .gpio_first = 7,
- .gpio_last = 14,
- }, {
- .name = "jtag",
- .mask = RT2880_GPIO_MODE_JTAG,
- .gpio_first = 17,
- .gpio_last = 21,
- }, {
- .name = "mdio",
- .mask = RT2880_GPIO_MODE_MDIO,
- .gpio_first = 22,
- .gpio_last = 23,
- }, {
- .name = "sdram",
- .mask = RT2880_GPIO_MODE_SDRAM,
- .gpio_first = 24,
- .gpio_last = 39,
- }, {
- .name = "pci",
- .mask = RT2880_GPIO_MODE_PCI,
- .gpio_first = 40,
- .gpio_last = 71,
- }, {0}
+static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
+static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 6) };
+static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 7, 14) };
+static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 21) };
+static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 23) };
+static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 39) };
+static struct rt2880_pmx_func pci_func[] = { FUNC("pci", 0, 40, 71) };
+
+static struct rt2880_pmx_group rt2880_pinmux_data_act[] = {
+ GRP("i2c", i2c_func, 1, RT2880_GPIO_MODE_I2C),
+ GRP("spi", spi_func, 1, RT2880_GPIO_MODE_SPI),
+ GRP("uartlite", uartlite_func, 1, RT2880_GPIO_MODE_UART0),
+ GRP("jtag", jtag_func, 1, RT2880_GPIO_MODE_JTAG),
+ GRP("mdio", mdio_func, 1, RT2880_GPIO_MODE_MDIO),
+ GRP("sdram", sdram_func, 1, RT2880_GPIO_MODE_SDRAM),
+ GRP("pci", pci_func, 1, RT2880_GPIO_MODE_PCI),
+ { 0 }
};
static void rt288x_wdt_reset(void)
@@ -69,11 +50,6 @@
rt_sysc_w32(t, SYSC_REG_CLKCFG);
}
-struct ralink_pinmux rt_gpio_pinmux = {
- .mode = mode_mux,
- .wdt_reset = rt288x_wdt_reset,
-};
-
void __init ralink_clk_init(void)
{
unsigned long cpu_rate;
@@ -140,4 +116,6 @@
soc_info->mem_base = RT2880_SDRAM_BASE;
soc_info->mem_size_min = RT2880_MEM_SIZE_MIN;
soc_info->mem_size_max = RT2880_MEM_SIZE_MAX;
+
+ rt2880_pinmux_data = rt2880_pinmux_data_act;
}

12
target/linux/ramips/patches-3.10/0203-owrt-MIPS-add-OWRTDTB-secion.patch → target/linux/ramips/patches-3.10/0300-MIPS-OWRTDTB.patch
View File

@ -24,7 +24,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
NESTED(kernel_entry, 16, sp) # kernel entry point
--- a/arch/mips/ralink/Makefile
+++ b/arch/mips/ralink/Makefile
@@ -21,4 +21,4 @@ obj-$(CONFIG_EARLY_PRINTK) += early_prin
@@ -26,4 +26,4 @@ obj-$(CONFIG_EARLY_PRINTK) += early_prin
obj-$(CONFIG_DEBUG_FS) += bootrom.o
@ -32,8 +32,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+#obj-y += dts/
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
@@ -77,6 +77,8 @@ void __init device_tree_init(void)
//free_bootmem(base, size);
@@ -90,6 +90,8 @@ static int __init early_init_dt_find_mem
return 0;
}
+extern struct boot_param_header __image_dtb;
@ -41,12 +41,12 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
void __init plat_mem_setup(void)
{
set_io_port_base(KSEG1);
@@ -85,7 +87,7 @@ void __init plat_mem_setup(void)
@@ -98,7 +100,7 @@ void __init plat_mem_setup(void)
* Load the builtin devicetree. This causes the chosen node to be
* parsed resulting in our memory appearing
*/
- __dt_setup_arch(&__dtb_start);
+ __dt_setup_arch(&__image_dtb);
if (soc_info.mem_size)
add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M,
of_scan_flat_dt(early_init_dt_find_memory, NULL);
if (memory_dtb)

21
target/linux/ramips/patches-3.10/0501-MIPS-increase-GIC_INTR_MAX.patch
View File

@ -1,21 +0,0 @@
From e5327a1c6969316370af5cae7cfe6b8163178575 Mon Sep 17 00:00:00 2001
From: John Crispin <blogic@openwrt.org>
Date: Mon, 2 Dec 2013 16:07:23 +0100
Subject: [PATCH 500/507] MIPS: increase GIC_INTR_MAX
Signed-off-by: John Crispin <blogic@openwrt.org>
---
arch/mips/include/asm/gic.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -19,7 +19,7 @@
#define GIC_TRIG_EDGE 1
#define GIC_TRIG_LEVEL 0
-#define GIC_NUM_INTRS (24 + NR_CPUS * 2)
+#define GIC_NUM_INTRS (56 + NR_CPUS * 2)
#define MSK(n) ((1 << (n)) - 1)
#define REG32(addr) (*(volatile unsigned int *) (addr))

52
target/linux/ramips/patches-3.10/0509-MIPS-Kconfig-CMP-support-needs-to-select-SMP-as-well.patch
View File

@ -1,52 +0,0 @@
From 184edf882ebb7885b49fa231a503205da94e78f0 Mon Sep 17 00:00:00 2001
From: Markos Chandras <markos.chandras@imgtec.com>
Date: Wed, 2 Oct 2013 12:40:26 -0500
Subject: [PATCH 065/105] MIPS: Kconfig: CMP support needs to select SMP as
well
The CMP code is only designed to work with SMP configurations.
Fixes multiple build problems on certain randconfigs:
In file included from arch/mips/kernel/smp-cmp.c:34:0:
arch/mips/include/asm/smp.h:28:0:
error: "raw_smp_processor_id" redefined [-Werror]
In file included from include/linux/sched.h:30:0,
from arch/mips/kernel/smp-cmp.c:22:
include/linux/smp.h:135:0: note: this is the location of the
previous definition
In file included from arch/mips/kernel/smp-cmp.c:34:0:
arch/mips/include/asm/smp.h:57:20:
error: redefinition of 'smp_send_reschedule'
In file included from include/linux/sched.h:30:0,
from arch/mips/kernel/smp-cmp.c:22:
include/linux/smp.h:179:20: note: previous
definition of 'smp_send_reschedule' was here
In file included from arch/mips/kernel/smp-cmp.c:34:0:
arch/mips/include/asm/smp.h: In function 'smp_send_reschedule':
arch/mips/include/asm/smp.h:61:8:
error: dereferencing pointer to incomplete type
[...]
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/5812/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
arch/mips/Kconfig | 1 +
1 file changed, 1 insertion(+)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2038,6 +2038,7 @@ config MIPS_VPE_APSP_API
config MIPS_CMP
bool "MIPS CMP framework support"
depends on SYS_SUPPORTS_MIPS_CMP
+ select SMP
select SYNC_R4K
select SYS_SUPPORTS_SMP
select SYS_SUPPORTS_SCHED_SMT if SMP

840
target/linux/ramips/patches-3.10/0512-USB-add-xhci-support-for-mt7621.patch
View File

@ -1,840 +0,0 @@
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -1254,7 +1254,7 @@ static void hub_quiesce(struct usb_hub *
if (type != HUB_SUSPEND) {
/* Disconnect all the children */
for (i = 0; i < hdev->maxchild; ++i) {
- if (hub->ports[i]->child)
+ if (hub->ports[i] && hub->ports[i]->child)
usb_disconnect(&hub->ports[i]->child);
}
}
--- a/drivers/usb/core/port.c
+++ b/drivers/usb/core/port.c
@@ -193,6 +193,7 @@ exit:
void usb_hub_remove_port_device(struct usb_hub *hub,
int port1)
{
- device_unregister(&hub->ports[port1 - 1]->dev);
+ if (hub->ports[port1 - 1])
+ device_unregister(&hub->ports[port1 - 1]->dev);
}
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -28,7 +28,11 @@ config USB_XHCI_HCD
if USB_XHCI_HCD
config USB_XHCI_PLATFORM
- tristate
+ bool "xHCI platform"
+
+config USB_MT7621_XHCI_PLATFORM
+ bool "MTK MT7621 xHCI"
+ depends on USB_XHCI_PLATFORM
config USB_XHCI_HCD_DEBUGGING
bool "Debugging for the xHCI host controller"
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -13,15 +13,23 @@ fhci-$(CONFIG_FHCI_DEBUG) += fhci-dbg.o
xhci-hcd-y := xhci.o xhci-mem.o
xhci-hcd-y += xhci-ring.o xhci-hub.o xhci-dbg.o
+ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
xhci-hcd-$(CONFIG_PCI) += xhci-pci.o
+endif
+
+ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
+xhci-hcd-y += mtk-phy.o xhci-mtk-scheduler.o xhci-mtk-power.o xhci-mtk.o mtk-phy-7621.o mtk-phy-ahb.o
+endif
ifneq ($(CONFIG_USB_XHCI_PLATFORM), )
- xhci-hcd-y += xhci-plat.o
+xhci-hcd-y += xhci-plat.o
endif
obj-$(CONFIG_USB_WHCI_HCD) += whci/
+ifndef CONFIG_USB_MT7621_XHCI_PLATFORM
obj-$(CONFIG_PCI) += pci-quirks.o
+endif
obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
obj-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
--- a/drivers/usb/host/pci-quirks.h
+++ b/drivers/usb/host/pci-quirks.h
@@ -1,7 +1,7 @@
#ifndef __LINUX_USB_PCI_QUIRKS_H
#define __LINUX_USB_PCI_QUIRKS_H
-#ifdef CONFIG_PCI
+#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
void uhci_reset_hc(struct pci_dev *pdev, unsigned long base);
int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base);
#endif /* CONFIG_PCI */
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -30,6 +30,16 @@
#include "xhci.h"
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+#include <asm/uaccess.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include "mtk-phy.h"
+#include "xhci-mtk-scheduler.h"
+#include "xhci-mtk-power.h"
+#include "xhci-mtk.h"
+#endif
+
#define DRIVER_AUTHOR "Sarah Sharp"
#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
@@ -38,6 +48,18 @@ static int link_quirk;
module_param(link_quirk, int, S_IRUGO | S_IWUSR);
MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+long xhci_mtk_test_unlock_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
+static struct file_operations xhci_mtk_test_fops = {
+ .owner = THIS_MODULE,
+ .read = xhci_mtk_test_read,
+ .write = xhci_mtk_test_write,
+ .unlocked_ioctl = xhci_mtk_test_unlock_ioctl,
+ .open = xhci_mtk_test_open,
+ .release = xhci_mtk_test_release,
+};
+#endif
+
/* TODO: copied from ehci-hcd.c - can this be refactored? */
/*
* xhci_handshake - spin reading hc until handshake completes or fails
@@ -189,7 +211,7 @@ int xhci_reset(struct xhci_hcd *xhci)
return ret;
}
-#ifdef CONFIG_PCI
+#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
static int xhci_free_msi(struct xhci_hcd *xhci)
{
int i;
@@ -389,6 +411,7 @@ static int xhci_try_enable_msi(struct us
return ret;
}
hcd->irq = pdev->irq;
+
return 0;
}
@@ -430,6 +453,11 @@ static void compliance_mode_recovery(uns
xhci_dbg(xhci, "Attempting compliance mode recovery\n");
hcd = xhci->shared_hcd;
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ temp |= (1 << 31);
+ xhci_writel(xhci, temp, xhci->usb3_ports[i]);
+#endif
+
if (hcd->state == HC_STATE_SUSPENDED)
usb_hcd_resume_root_hub(hcd);
@@ -478,6 +506,9 @@ bool xhci_compliance_mode_recovery_timer
{
const char *dmi_product_name, *dmi_sys_vendor;
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ return true;
+#endif
dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
if (!dmi_product_name || !dmi_sys_vendor)
@@ -521,6 +552,10 @@ int xhci_init(struct usb_hcd *hcd)
} else {
xhci_dbg(xhci, "xHCI doesn't need link TRB QUIRK\n");
}
+
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ mtk_xhci_scheduler_init();
+#endif
retval = xhci_mem_init(xhci, GFP_KERNEL);
xhci_dbg(xhci, "Finished xhci_init\n");
@@ -664,7 +699,11 @@ int xhci_run(struct usb_hcd *hcd)
xhci_dbg(xhci, "// Set the interrupt modulation register\n");
temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
temp &= ~ER_IRQ_INTERVAL_MASK;
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ temp |= (u32) 16;
+#else
temp |= (u32) 160;
+#endif
xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
/* Set the HCD state before we enable the irqs */
@@ -685,6 +724,9 @@ int xhci_run(struct usb_hcd *hcd)
xhci_queue_vendor_command(xhci, 0, 0, 0,
TRB_TYPE(TRB_NEC_GET_FW));
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ enableXhciAllPortPower(xhci);
+#endif
xhci_dbg(xhci, "Finished xhci_run for USB2 roothub\n");
return 0;
}
@@ -1002,7 +1044,6 @@ int xhci_resume(struct xhci_hcd *xhci, b
/* If restore operation fails, re-initialize the HC during resume */
if ((temp & STS_SRE) || hibernated) {
-
if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
!(xhci_all_ports_seen_u0(xhci))) {
del_timer_sync(&xhci->comp_mode_recovery_timer);
@@ -1586,6 +1627,13 @@ int xhci_drop_endpoint(struct usb_hcd *h
u32 drop_flag;
u32 new_add_flags, new_drop_flags, new_slot_info;
int ret;
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+#if MTK_SCH_NEW
+ struct sch_ep *sch_ep = NULL;
+ int isTT;
+ int ep_type;
+#endif
+#endif
ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
if (ret <= 0)
@@ -1637,6 +1685,40 @@ int xhci_drop_endpoint(struct usb_hcd *h
xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+#if MTK_SCH_NEW
+ slot_ctx = xhci_get_slot_ctx(xhci, xhci->devs[udev->slot_id]->out_ctx);
+ if ((slot_ctx->tt_info & 0xff) > 0) {
+ isTT = 1;
+ }
+ else {
+ isTT = 0;
+ }
+ if (usb_endpoint_xfer_int(&ep->desc)) {
+ ep_type = USB_EP_INT;
+ }
+ else if (usb_endpoint_xfer_isoc(&ep->desc)) {
+ ep_type = USB_EP_ISOC;
+ }
+ else if (usb_endpoint_xfer_bulk(&ep->desc)) {
+ ep_type = USB_EP_BULK;
+ }
+ else
+ ep_type = USB_EP_CONTROL;
+
+ sch_ep = mtk_xhci_scheduler_remove_ep(udev->speed, usb_endpoint_dir_in(&ep->desc)
+ , isTT, ep_type, (mtk_u32 *)ep);
+ if (sch_ep != NULL) {
+ kfree(sch_ep);
+ }
+ else {
+ xhci_dbg(xhci, "[MTK]Doesn't find ep_sch instance when removing endpoint\n");
+ }
+#else
+ mtk_xhci_scheduler_remove_ep(xhci, udev, ep);
+#endif
+#endif
+
xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
(unsigned int) ep->desc.bEndpointAddress,
udev->slot_id,
@@ -1672,6 +1754,18 @@ int xhci_add_endpoint(struct usb_hcd *hc
u32 new_add_flags, new_drop_flags, new_slot_info;
struct xhci_virt_device *virt_dev;
int ret = 0;
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ struct xhci_ep_ctx *in_ep_ctx;
+#if MTK_SCH_NEW
+ struct sch_ep *sch_ep;
+ int isTT;
+ int ep_type;
+ int maxp = 0;
+ int burst = 0;
+ int mult = 0;
+ int interval;
+#endif
+#endif
ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
if (ret <= 0) {
@@ -1734,6 +1828,56 @@ int xhci_add_endpoint(struct usb_hcd *hc
return -ENOMEM;
}
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
+#if MTK_SCH_NEW
+ slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
+ if ((slot_ctx->tt_info & 0xff) > 0) {
+ isTT = 1;
+ }
+ else {
+ isTT = 0;
+ }
+ if (usb_endpoint_xfer_int(&ep->desc)) {
+ ep_type = USB_EP_INT;
+ }
+ else if (usb_endpoint_xfer_isoc(&ep->desc)) {
+ ep_type = USB_EP_ISOC;
+ }
+ else if (usb_endpoint_xfer_bulk(&ep->desc)) {
+ ep_type = USB_EP_BULK;
+ }
+ else
+ ep_type = USB_EP_CONTROL;
+
+ if (udev->speed == USB_SPEED_FULL || udev->speed == USB_SPEED_HIGH
+ || udev->speed == USB_SPEED_LOW) {
+ maxp = ep->desc.wMaxPacketSize & 0x7FF;
+ burst = ep->desc.wMaxPacketSize >> 11;
+ mult = 0;
+ }
+ else if (udev->speed == USB_SPEED_SUPER) {
+ maxp = ep->desc.wMaxPacketSize & 0x7FF;
+ burst = ep->ss_ep_comp.bMaxBurst;
+ mult = ep->ss_ep_comp.bmAttributes & 0x3;
+ }
+ interval = (1 << ((in_ep_ctx->ep_info >> 16) & 0xff));
+ sch_ep = kmalloc(sizeof(struct sch_ep), GFP_KERNEL);
+ if (mtk_xhci_scheduler_add_ep(udev->speed, usb_endpoint_dir_in(&ep->desc),
+ isTT, ep_type, maxp, interval, burst, mult, (mtk_u32 *)ep
+ , (mtk_u32 *)in_ep_ctx, sch_ep) != SCH_SUCCESS) {
+ xhci_err(xhci, "[MTK] not enough bandwidth\n");
+
+ return -ENOSPC;
+ }
+#else
+ if (mtk_xhci_scheduler_add_ep(xhci, udev, ep, in_ep_ctx) != SCH_SUCCESS) {
+ xhci_err(xhci, "[MTK] not enough bandwidth\n");
+
+ return -ENOSPC;
+ }
+#endif
+#endif
ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
@@ -2697,7 +2841,7 @@ int xhci_check_bandwidth(struct usb_hcd
if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
ctrl_ctx->drop_flags == 0)
return 0;
-
+
xhci_dbg(xhci, "New Input Control Context:\n");
slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
xhci_dbg_ctx(xhci, virt_dev->in_ctx,
@@ -4233,10 +4377,14 @@ static u16 xhci_call_host_update_timeout
u16 *timeout)
{
if (state == USB3_LPM_U1) {
+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
if (xhci->quirks & XHCI_INTEL_HOST)
+#endif
return xhci_calculate_intel_u1_timeout(udev, desc);
} else {
+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
if (xhci->quirks & XHCI_INTEL_HOST)
+#endif
return xhci_calculate_intel_u2_timeout(udev, desc);
}
@@ -4662,7 +4810,9 @@ int xhci_gen_setup(struct usb_hcd *hcd,
/* Accept arbitrarily long scatter-gather lists */
hcd->self.sg_tablesize = ~0;
/* XHCI controllers don't stop the ep queue on short packets :| */
+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
hcd->self.no_stop_on_short = 1;
+#endif
if (usb_hcd_is_primary_hcd(hcd)) {
xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
@@ -4731,6 +4881,10 @@ int xhci_gen_setup(struct usb_hcd *hcd,
goto error;
xhci_dbg(xhci, "Reset complete\n");
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ setInitialReg();
+#endif
+
temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
if (HCC_64BIT_ADDR(temp)) {
xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
@@ -4755,8 +4909,21 @@ MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_LICENSE("GPL");
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+static struct platform_device xhci_platform_dev = {
+ .name = "xhci-hcd",
+ .id = -1,
+ .dev = {
+ .coherent_dma_mask = 0xffffffff,
+ },
+};
+#endif
+
static int __init xhci_hcd_init(void)
{
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ struct platform_device *pPlatformDev;
+#endif
int retval;
retval = xhci_register_pci();
@@ -4769,6 +4936,33 @@ static int __init xhci_hcd_init(void)
printk(KERN_DEBUG "Problem registering platform driver.");
goto unreg_pci;
}
+
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ retval = register_chrdev(XHCI_MTK_TEST_MAJOR, DEVICE_NAME, &xhci_mtk_test_fops);
+
+ u3phy_init();
+ if (u3phy_ops->u2_slew_rate_calibration) {
+ u3phy_ops->u2_slew_rate_calibration(u3phy);
+ u3phy_ops->u2_slew_rate_calibration(u3phy_p1);
+ }
+ else{
+ printk(KERN_ERR "WARN: PHY doesn't implement u2 slew rate calibration function\n");
+ }
+ u3phy_ops->init(u3phy);
+ reinitIP();
+
+ pPlatformDev = &xhci_platform_dev;
+ memset(pPlatformDev, 0, sizeof(struct platform_device));
+ pPlatformDev->name = "xhci-hcd";
+ pPlatformDev->id = -1;
+ pPlatformDev->dev.coherent_dma_mask = 0xffffffff;
+ pPlatformDev->dev.dma_mask = &pPlatformDev->dev.coherent_dma_mask;
+
+ retval = platform_device_register(&xhci_platform_dev);
+ if (retval < 0)
+ xhci_unregister_plat();
+#endif
+
/*
* Check the compiler generated sizes of structures that must be laid
* out in specific ways for hardware access.
@@ -4786,6 +4980,7 @@ static int __init xhci_hcd_init(void)
BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
/* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
+
return 0;
unreg_pci:
xhci_unregister_pci();
--- a/drivers/usb/host/xhci-dbg.c
+++ b/drivers/usb/host/xhci-dbg.c
@@ -21,6 +21,9 @@
*/
#include "xhci.h"
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+#include "xhci-mtk.h"
+#endif
#define XHCI_INIT_VALUE 0x0
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -29,9 +29,24 @@
#include <linux/usb/hcd.h>
/* Code sharing between pci-quirks and xhci hcd */
-#include "xhci-ext-caps.h"
+#include "xhci-ext-caps.h"
#include "pci-quirks.h"
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+#define XHC_IRQ (22 + 8)
+#define XHC_IO_START 0x1E1C0000
+#define XHC_IO_LENGTH 0x10000
+/* mtk scheduler bitmasks */
+#define BPKTS(p) ((p) & 0x3f)
+#define BCSCOUNT(p) (((p) & 0x7) << 8)
+#define BBM(p) ((p) << 11)
+#define BOFFSET(p) ((p) & 0x3fff)
+#define BREPEAT(p) (((p) & 0x7fff) << 16)
+#endif
+
+
+
+
/* xHCI PCI Configuration Registers */
#define XHCI_SBRN_OFFSET (0x60)
@@ -1536,8 +1551,12 @@ struct xhci_hcd {
/* Compliance Mode Recovery Data */
struct timer_list comp_mode_recovery_timer;
u32 port_status_u0;
+#ifdef CONFIG_USB_MT7621_XHCI_PLATFORM
+#define COMP_MODE_RCVRY_MSECS 5000
+#else
/* Compliance Mode Timer Triggered every 2 seconds */
#define COMP_MODE_RCVRY_MSECS 2000
+#endif
};
/* convert between an HCD pointer and the corresponding EHCI_HCD */
@@ -1703,7 +1722,7 @@ void xhci_urb_free_priv(struct xhci_hcd
void xhci_free_command(struct xhci_hcd *xhci,
struct xhci_command *command);
-#ifdef CONFIG_PCI
+#if defined (CONFIG_PCI) && !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
/* xHCI PCI glue */
int xhci_register_pci(void);
void xhci_unregister_pci(void);
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -65,6 +65,9 @@ static struct xhci_segment *xhci_segment
static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
{
+ if (!seg)
+ return;
+
if (seg->trbs) {
dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
seg->trbs = NULL;
@@ -1446,9 +1449,17 @@ int xhci_endpoint_init(struct xhci_hcd *
max_burst = (usb_endpoint_maxp(&ep->desc)
& 0x1800) >> 11;
}
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ if ((max_packet % 4 == 2) && (max_packet % 16 != 14) && (max_burst == 0) && usb_endpoint_dir_in(&ep->desc))
+ max_packet += 2;
+#endif
break;
case USB_SPEED_FULL:
case USB_SPEED_LOW:
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ if ((max_packet % 4 == 2) && (max_packet % 16 != 14) && (max_burst == 0) && usb_endpoint_dir_in(&ep->desc))
+ max_packet += 2;
+#endif
break;
default:
BUG();
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -25,6 +25,13 @@ static void xhci_plat_quirks(struct devi
* dev struct in order to setup MSI
*/
xhci->quirks |= XHCI_PLAT;
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ /* MTK host controller gives a spurious successful event after a
+ * short transfer. Ignore it.
+ */
+ xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
+ xhci->quirks |= XHCI_LPM_SUPPORT;
+#endif
}
/* called during probe() after chip reset completes */
@@ -96,20 +103,32 @@ static int xhci_plat_probe(struct platfo
driver = &xhci_plat_xhci_driver;
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ irq = XHC_IRQ;
+#else
irq = platform_get_irq(pdev, 0);
+#endif
+
if (irq < 0)
return -ENODEV;
+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENODEV;
+#endif
hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
if (!hcd)
return -ENOMEM;
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ hcd->rsrc_start = (uint32_t)XHC_IO_START;
+ hcd->rsrc_len = XHC_IO_LENGTH;
+#else
hcd->rsrc_start = res->start;
hcd->rsrc_len = resource_size(res);
+#endif
if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len,
driver->description)) {
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -236,7 +236,6 @@ static void inc_enq(struct xhci_hcd *xhc
*/
if (!chain && !more_trbs_coming)
break;
-
/* If we're not dealing with 0.95 hardware or
* isoc rings on AMD 0.96 host,
* carry over the chain bit of the previous TRB
@@ -273,16 +272,20 @@ static void inc_enq(struct xhci_hcd *xhc
static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
unsigned int num_trbs)
{
+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
int num_trbs_in_deq_seg;
+#endif
if (ring->num_trbs_free < num_trbs)
return 0;
+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
return 0;
}
+#endif
return 1;
}
@@ -2910,6 +2913,7 @@ static int prepare_ring(struct xhci_hcd
next = ring->enqueue;
while (last_trb(xhci, ring, ring->enq_seg, next)) {
+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
/* If we're not dealing with 0.95 hardware or isoc rings
* on AMD 0.96 host, clear the chain bit.
*/
@@ -2919,7 +2923,9 @@ static int prepare_ring(struct xhci_hcd
next->link.control &= cpu_to_le32(~TRB_CHAIN);
else
next->link.control |= cpu_to_le32(TRB_CHAIN);
-
+#else
+ next->link.control &= cpu_to_le32(~TRB_CHAIN);
+#endif
wmb();
next->link.control ^= cpu_to_le32(TRB_CYCLE);
@@ -3049,6 +3055,9 @@ static void giveback_first_trb(struct xh
start_trb->field[3] |= cpu_to_le32(start_cycle);
else
start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ wmb();
+#endif
xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
}
@@ -3108,6 +3117,29 @@ static u32 xhci_td_remainder(unsigned in
return (remainder >> 10) << 17;
}
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+static u32 mtk_xhci_td_remainder(unsigned int td_transfer_size, unsigned int td_running_total, unsigned int maxp, unsigned trb_buffer_length)
+{
+ u32 max = 31;
+ int remainder, td_packet_count, packet_transferred;
+
+ //0 for the last TRB
+ //FIXME: need to workaround if there is ZLP in this TD
+ if (td_running_total + trb_buffer_length == td_transfer_size)
+ return 0;
+
+ //FIXME: need to take care of high-bandwidth (MAX_ESIT)
+ packet_transferred = (td_running_total /*+ trb_buffer_length*/) / maxp;
+ td_packet_count = DIV_ROUND_UP(td_transfer_size, maxp);
+ remainder = td_packet_count - packet_transferred;
+
+ if (remainder > max)
+ return max << 17;
+ else
+ return remainder << 17;
+}
+#endif
+
/*
* For xHCI 1.0 host controllers, TD size is the number of max packet sized
* packets remaining in the TD (*not* including this TRB).
@@ -3245,6 +3277,7 @@ static int queue_bulk_sg_tx(struct xhci_
}
/* Set the TRB length, TD size, and interrupter fields. */
+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
if (xhci->hci_version < 0x100) {
remainder = xhci_td_remainder(
urb->transfer_buffer_length -
@@ -3254,6 +3287,13 @@ static int queue_bulk_sg_tx(struct xhci_
trb_buff_len, total_packet_count, urb,
num_trbs - 1);
}
+#else
+ if (num_trbs > 1)
+ remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length,
+ running_total, urb->ep->desc.wMaxPacketSize, trb_buff_len);
+#endif
+
+
length_field = TRB_LEN(trb_buff_len) |
remainder |
TRB_INTR_TARGET(0);
@@ -3316,6 +3356,9 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
int running_total, trb_buff_len, ret;
unsigned int total_packet_count;
u64 addr;
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ int max_packet;
+#endif
if (urb->num_sgs)
return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
@@ -3341,6 +3384,25 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
running_total += TRB_MAX_BUFF_SIZE;
}
/* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ switch(urb->dev->speed){
+ case USB_SPEED_SUPER:
+ max_packet = urb->ep->desc.wMaxPacketSize;
+ break;
+ case USB_SPEED_HIGH:
+ case USB_SPEED_FULL:
+ case USB_SPEED_LOW:
+ case USB_SPEED_WIRELESS:
+ case USB_SPEED_UNKNOWN:
+ default:
+ max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
+ break;
+ }
+ if((urb->transfer_flags & URB_ZERO_PACKET)
+ && ((urb->transfer_buffer_length % max_packet) == 0)){
+ num_trbs++;
+ }
+#endif
ret = prepare_transfer(xhci, xhci->devs[slot_id],
ep_index, urb->stream_id,
@@ -3400,6 +3462,7 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
field |= TRB_ISP;
/* Set the TRB length, TD size, and interrupter fields. */
+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
if (xhci->hci_version < 0x100) {
remainder = xhci_td_remainder(
urb->transfer_buffer_length -
@@ -3409,6 +3472,10 @@ int xhci_queue_bulk_tx(struct xhci_hcd *
trb_buff_len, total_packet_count, urb,
num_trbs - 1);
}
+#else
+ remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
+#endif
+
length_field = TRB_LEN(trb_buff_len) |
remainder |
TRB_INTR_TARGET(0);
@@ -3498,7 +3565,11 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
field |= 0x1;
/* xHCI 1.0 6.4.1.2.1: Transfer Type field */
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ if (1) {
+#else
if (xhci->hci_version == 0x100) {
+#endif
if (urb->transfer_buffer_length > 0) {
if (setup->bRequestType & USB_DIR_IN)
field |= TRB_TX_TYPE(TRB_DATA_IN);
@@ -3522,7 +3593,12 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
field = TRB_TYPE(TRB_DATA);
length_field = TRB_LEN(urb->transfer_buffer_length) |
+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
xhci_td_remainder(urb->transfer_buffer_length) |
+#else
+ //CC: MTK style, no scatter-gather for control transfer
+ 0 |
+#endif
TRB_INTR_TARGET(0);
if (urb->transfer_buffer_length > 0) {
if (setup->bRequestType & USB_DIR_IN)
@@ -3533,7 +3609,7 @@ int xhci_queue_ctrl_tx(struct xhci_hcd *
length_field,
field | ep_ring->cycle_state);
}
-
+
/* Save the DMA address of the last TRB in the TD */
td->last_trb = ep_ring->enqueue;
@@ -3645,6 +3721,9 @@ static int xhci_queue_isoc_tx(struct xhc
u64 start_addr, addr;
int i, j;
bool more_trbs_coming;
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ int max_packet;
+#endif
ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
@@ -3658,6 +3737,21 @@ static int xhci_queue_isoc_tx(struct xhc
start_trb = &ep_ring->enqueue->generic;
start_cycle = ep_ring->cycle_state;
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ switch(urb->dev->speed){
+ case USB_SPEED_SUPER:
+ max_packet = urb->ep->desc.wMaxPacketSize;
+ break;
+ case USB_SPEED_HIGH:
+ case USB_SPEED_FULL:
+ case USB_SPEED_LOW:
+ case USB_SPEED_WIRELESS:
+ case USB_SPEED_UNKNOWN:
+ max_packet = urb->ep->desc.wMaxPacketSize & 0x7ff;
+ break;
+ }
+#endif
+
urb_priv = urb->hcpriv;
/* Queue the first TRB, even if it's zero-length */
for (i = 0; i < num_tds; i++) {
@@ -3729,9 +3823,13 @@ static int xhci_queue_isoc_tx(struct xhc
} else {
td->last_trb = ep_ring->enqueue;
field |= TRB_IOC;
+#if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
+ if (!(xhci->quirks & XHCI_AVOID_BEI)) {
+#else
if (xhci->hci_version == 0x100 &&
!(xhci->quirks &
XHCI_AVOID_BEI)) {
+#endif
/* Set BEI bit except for the last td */
if (i < num_tds - 1)
field |= TRB_BEI;
@@ -3746,6 +3844,7 @@ static int xhci_queue_isoc_tx(struct xhc
trb_buff_len = td_remain_len;
/* Set the TRB length, TD size, & interrupter fields. */
+#if !defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
if (xhci->hci_version < 0x100) {
remainder = xhci_td_remainder(
td_len - running_total);
@@ -3755,6 +3854,10 @@ static int xhci_queue_isoc_tx(struct xhc
total_packet_count, urb,
(trbs_per_td - j - 1));
}
+#else
+ remainder = mtk_xhci_td_remainder(urb->transfer_buffer_length, running_total, max_packet, trb_buff_len);
+#endif
+
length_field = TRB_LEN(trb_buff_len) |
remainder |
TRB_INTR_TARGET(0);

12
target/linux/ramips/patches-3.10/800-eco.patch
View File

@ -1,12 +0,0 @@
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -101,4 +101,9 @@
#define MT7620_GPIO_MODE_EPHY 15
#define MT7620_GPIO_MODE_PA 20
+static inline int mt7620_get_eco(void)
+{
+ return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
+}
+
#endif

17
target/linux/ramips/patches-3.10/999-clk.patch
View File

@ -1,17 +0,0 @@
Index: linux-3.10.32/arch/mips/ralink/clk.c
===================================================================
--- linux-3.10.32.orig/arch/mips/ralink/clk.c 2014-03-12 03:04:05.468396764 +0000
+++ linux-3.10.32/arch/mips/ralink/clk.c 2014-03-12 03:29:00.220416177 +0000
@@ -56,6 +56,12 @@
}
EXPORT_SYMBOL_GPL(clk_get_rate);
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ return -1;
+}
+EXPORT_SYMBOL_GPL(clk_set_rate);
+
void __init plat_time_init(void)
{
struct clk *clk;

32
target/linux/ramips/patches-3.10/999-memory-detect.patch
View File

@ -1,32 +0,0 @@
--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
@@ -80,6 +80,16 @@ void __init device_tree_init(void)
}
extern struct boot_param_header __image_dtb;
+static int memory_dtb;
+
+static int __init early_init_dt_find_memory(unsigned long node, const char *uname,
+ int depth, void *data)
+{
+ if (depth == 1 && !strcmp(uname, "memory@0"))
+ memory_dtb = 1;
+
+ return 0;
+}
void __init plat_mem_setup(void)
{
@@ -90,8 +100,10 @@ void __init plat_mem_setup(void)
* parsed resulting in our memory appearing
*/
__dt_setup_arch(&__image_dtb);
-
- if (soc_info.mem_size)
+ of_scan_flat_dt(early_init_dt_find_memory, NULL);
+ if (memory_dtb)
+ of_scan_flat_dt(early_init_dt_scan_memory, NULL);
+ else if (soc_info.mem_size)
add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M,
BOOT_MEM_RAM);
else

33
target/linux/ramips/patches-3.10/999-pinctrl_fixes.patch
View File

@ -1,33 +0,0 @@
--- a/drivers/pinctrl/pinctrl-rt2880.c
+++ b/drivers/pinctrl/pinctrl-rt2880.c
@@ -204,6 +204,7 @@ static int rt2880_pmx_group_enable(struc
{
struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
u32 mode = 0;
+ int i;
/* dont allow double use */
if (p->groups[group].enabled) {
@@ -217,16 +218,16 @@ static int rt2880_pmx_group_enable(struc
mode = rt_sysc_r32(SYSC_REG_GPIO_MODE);
mode &= ~(p->groups[group].mask << p->groups[group].shift);
+ /* mark the pins as gpio */
+ for (i = 0; i < p->groups[group].func[0].pin_count; i++)
+ p->gpio[p->groups[group].func[0].pins[i]] = 1;
+
/* function 0 is gpio and needs special handling */
if (func == 0) {
- int i;
-
-
mode |= p->groups[group].gpio << p->groups[group].shift;
- /* mark the pins as gpio */
- for (i = 0; i < p->groups[group].func[0].pin_count; i++)
- p->gpio[p->groups[group].func[0].pins[i]] = 1;
} else {
+ for (i = 0; i < p->func[func]->pin_count; i++)
+ p->gpio[p->func[func]->pins[i]] = 0;
mode |= p->func[func]->value << p->groups[group].shift;
}
rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);

21
target/linux/ramips/patches-3.10/999-raeth_fixes.patch
View File

@ -1,21 +0,0 @@
--- a/drivers/net/ethernet/ralink/ralink_soc_eth.c
+++ b/drivers/net/ethernet/ralink/ralink_soc_eth.c
@@ -335,7 +335,7 @@ static int fe_start_xmit(struct sk_buff
if (priv->soc->tso)
fe_start_tso(skb, dev, nr_frags, tx);
- if (skb_shinfo(skb)->gso_segs > 1) {
+ if (priv->soc->tso && (skb_shinfo(skb)->gso_segs > 1)) {
struct iphdr *iph = NULL;
struct tcphdr *th = NULL;
struct ipv6hdr *ip6h = NULL;
@@ -741,8 +741,7 @@ static int fe_probe(struct platform_devi
dev_info(&pdev->dev, "Enabling TSO\n");
netdev->features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_IPV6_CSUM;
}
-
- netdev->hw_features = netdev->vlan_features = netdev->features;
+ netdev->hw_features = netdev->features;
netdev->irq = platform_get_irq(pdev, 0);
if (netdev->irq < 0) {

4
target/linux/ramips/rt288x/config-3.10
View File

@ -1,6 +1,7 @@
CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
CONFIG_ARCH_DISCARD_MEMBLOCK=y
CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
CONFIG_ARCH_HAS_RESET_CONTROLLER=y
CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
CONFIG_ARCH_REQUIRE_GPIOLIB=y
@ -82,6 +83,7 @@ CONFIG_IRQCHIP=y
CONFIG_IRQ_CPU=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_INTC=y
CONFIG_IRQ_WORK=y
CONFIG_M25PXX_USE_FAST_READ=y
CONFIG_MDIO_BOARDINFO=y
@ -127,6 +129,7 @@ CONFIG_PINMUX=y
# CONFIG_PREEMPT_RCU is not set
CONFIG_RALINK=y
CONFIG_RALINK_WDT=y
CONFIG_RA_NAT_NONE=y
# CONFIG_RCU_STALL_COMMON is not set
CONFIG_RESET_CONTROLLER=y
# CONFIG_SCSI_DMA is not set
@ -136,6 +139,7 @@ CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SOC_MT7620 is not set
# CONFIG_SOC_MT7621 is not set
CONFIG_SOC_RT288X=y
# CONFIG_SOC_RT305X is not set
# CONFIG_SOC_RT3883 is not set