mirror of https://github.com/hak5/openwrt.git
705 lines
17 KiB
C
705 lines
17 KiB
C
/*
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* OHCI HCD (Host Controller Driver) for USB.
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*
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* (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
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* (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
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*
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* This file is licenced under the GPL.
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*/
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#include <linux/irq.h>
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/*-------------------------------------------------------------------------*/
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/*
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* URB goes back to driver, and isn't reissued.
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* It's completely gone from HC data structures.
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* PRECONDITION: ahcd lock held, irqs blocked.
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*/
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static void
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finish_urb(struct admhcd *ahcd, struct urb *urb)
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__releases(ahcd->lock)
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__acquires(ahcd->lock)
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{
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urb_priv_free(ahcd, urb->hcpriv);
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urb->hcpriv = NULL;
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spin_lock(&urb->lock);
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if (likely(urb->status == -EINPROGRESS))
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urb->status = 0;
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/* report short control reads right even though the data TD always
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* has TD_R set. (much simpler, but creates the 1-td limit.)
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*/
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if (unlikely(urb->transfer_flags & URB_SHORT_NOT_OK)
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&& unlikely(usb_pipecontrol(urb->pipe))
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&& urb->actual_length < urb->transfer_buffer_length
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&& usb_pipein(urb->pipe)
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&& urb->status == 0) {
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urb->status = -EREMOTEIO;
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#ifdef ADMHC_VERBOSE_DEBUG
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urb_print(ahcd, urb, "SHORT", usb_pipeout (urb->pipe));
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#endif
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}
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spin_unlock(&urb->lock);
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switch (usb_pipetype(urb->pipe)) {
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case PIPE_ISOCHRONOUS:
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admhcd_to_hcd(ahcd)->self.bandwidth_isoc_reqs--;
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break;
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case PIPE_INTERRUPT:
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admhcd_to_hcd(ahcd)->self.bandwidth_int_reqs--;
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break;
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}
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#ifdef ADMHC_VERBOSE_DEBUG
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urb_print(ahcd, urb, "FINISH", 0);
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#endif
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/* urb->complete() can reenter this HCD */
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spin_unlock(&ahcd->lock);
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usb_hcd_giveback_urb(admhcd_to_hcd(ahcd), urb);
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spin_lock(&ahcd->lock);
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}
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/*-------------------------------------------------------------------------*
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* ED handling functions
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*-------------------------------------------------------------------------*/
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static struct ed *ed_create(struct admhcd *ahcd, unsigned int type, u32 info)
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{
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struct ed *ed;
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struct td *td;
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ed = ed_alloc(ahcd, GFP_ATOMIC);
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if (!ed)
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goto err;
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/* dummy td; end of td list for this ed */
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td = td_alloc(ahcd, GFP_ATOMIC);
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if (!td)
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goto err_free_ed;
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switch (type) {
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case PIPE_INTERRUPT:
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info |= ED_INT;
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break;
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case PIPE_ISOCHRONOUS:
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info |= ED_ISO;
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break;
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}
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ed->dummy = td;
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ed->state = ED_NEW;
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ed->type = type;
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ed->hwINFO = cpu_to_hc32(ahcd, info);
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ed->hwTailP = cpu_to_hc32(ahcd, td->td_dma);
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ed->hwHeadP = cpu_to_hc32(ahcd, td->td_dma);
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return ed;
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err_free_ed:
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ed_free(ahcd, ed);
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err:
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return NULL;
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}
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/* get and maybe (re)init an endpoint. init _should_ be done only as part
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* of enumeration, usb_set_configuration() or usb_set_interface().
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*/
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static struct ed *ed_get(struct admhcd *ahcd, struct usb_host_endpoint *ep,
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struct usb_device *udev, unsigned int pipe, int interval)
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{
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struct ed *ed;
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unsigned long flags;
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spin_lock_irqsave(&ahcd->lock, flags);
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ed = ep->hcpriv;
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if (!ed) {
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u32 info;
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/* FIXME: usbcore changes dev->devnum before SET_ADDRESS
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* suceeds ... otherwise we wouldn't need "pipe".
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*/
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info = usb_pipedevice(pipe);
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info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << ED_EN_SHIFT;
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info |= le16_to_cpu(ep->desc.wMaxPacketSize) << ED_MPS_SHIFT;
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if (udev->speed == USB_SPEED_FULL)
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info |= ED_SPEED_FULL;
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ed = ed_create(ahcd, usb_pipetype(pipe), info);
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if (ed)
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ep->hcpriv = ed;
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}
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spin_unlock_irqrestore(&ahcd->lock, flags);
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return ed;
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}
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/* link an ed into the HC chain */
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static int ed_schedule(struct admhcd *ahcd, struct ed *ed)
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{
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struct ed *old_tail;
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if (admhcd_to_hcd(ahcd)->state == HC_STATE_QUIESCING)
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return -EAGAIN;
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if (ed->state != ED_NEW)
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return 0;
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admhc_dump_ed(ahcd, "ED-SCHED", ed, 0);
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ed->state = ED_IDLE;
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ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP);
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old_tail = ahcd->ed_tails[ed->type];
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ed->ed_next = old_tail->ed_next;
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if (ed->ed_next) {
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ed->ed_next->ed_prev = ed;
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ed->hwNextED = cpu_to_hc32(ahcd, ed->ed_next->dma);
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}
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ed->ed_prev = old_tail;
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old_tail->ed_next = ed;
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old_tail->hwNextED = cpu_to_hc32(ahcd, ed->dma);
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ahcd->ed_tails[ed->type] = ed;
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admhc_intr_enable(ahcd, ADMHC_INTR_SOFI);
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return 0;
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}
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static void ed_deschedule(struct admhcd *ahcd, struct ed *ed)
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{
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admhc_dump_ed(ahcd, "ED-DESCHED", ed, 0);
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/* remove this ED from the HC list */
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ed->ed_prev->hwNextED = ed->hwNextED;
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/* and remove it from our list */
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ed->ed_prev->ed_next = ed->ed_next;
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if (ed->ed_next) {
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ed->ed_next->ed_prev = ed->ed_prev;
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ed->ed_next = NULL;
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}
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if (ahcd->ed_tails[ed->type] == ed)
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ahcd->ed_tails[ed->type] = ed->ed_prev;
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ed->state = ED_NEW;
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}
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static void ed_start_deschedule(struct admhcd *ahcd, struct ed *ed)
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{
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admhc_dump_ed(ahcd, "ED-UNLINK", ed, 0);
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ed->hwINFO |= cpu_to_hc32(ahcd, ED_SKIP);
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ed->state = ED_UNLINK;
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/* add this ED into the remove list */
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ed->ed_rm_next = ahcd->ed_rm_list;
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ahcd->ed_rm_list = ed;
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/* SOF interrupt might get delayed; record the frame counter value that
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* indicates when the HC isn't looking at it, so concurrent unlinks
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* behave. frame_no wraps every 2^16 msec, and changes right before
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* SOF is triggered.
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*/
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ed->tick = admhc_frame_no(ahcd) + 1;
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/* enable SOF interrupt */
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admhc_intr_enable(ahcd, ADMHC_INTR_SOFI);
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}
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/*-------------------------------------------------------------------------*
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* TD handling functions
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*-------------------------------------------------------------------------*/
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static void td_fill(struct admhcd *ahcd, u32 info, dma_addr_t data, int len,
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struct urb_priv *up)
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{
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struct td *td;
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u32 cbl = 0;
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if (up->td_idx >= up->td_cnt) {
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admhc_dbg(ahcd, "td_fill error, idx=%d, cnt=%d\n", up->td_idx,
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up->td_cnt);
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return;
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}
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td = up->td[up->td_idx];
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td->data_dma = data;
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if (!len)
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data = 0;
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#if 1
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if (up->td_idx == up->td_cnt-1)
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#endif
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cbl |= TD_IE;
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if (data)
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cbl |= (len & TD_BL_MASK);
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info |= TD_OWN;
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/* setup hardware specific fields */
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td->hwINFO = cpu_to_hc32(ahcd, info);
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td->hwDBP = cpu_to_hc32(ahcd, data);
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td->hwCBL = cpu_to_hc32(ahcd, cbl);
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if (up->td_idx > 0)
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up->td[up->td_idx-1]->hwNextTD = cpu_to_hc32(ahcd, td->td_dma);
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up->td_idx++;
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}
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/*-------------------------------------------------------------------------*/
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/* Prepare all TDs of a transfer, and queue them onto the ED.
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* Caller guarantees HC is active.
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* Usually the ED is already on the schedule, so TDs might be
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* processed as soon as they're queued.
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*/
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static void td_submit_urb(struct admhcd *ahcd, struct urb *urb)
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{
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struct urb_priv *urb_priv = urb->hcpriv;
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dma_addr_t data;
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int data_len = urb->transfer_buffer_length;
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int cnt = 0;
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u32 info = 0;
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int is_out = usb_pipeout(urb->pipe);
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u32 toggle = 0;
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/* OHCI handles the bulk/interrupt data toggles itself. We just
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* use the device toggle bits for resetting, and rely on the fact
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* that resetting toggle is meaningless if the endpoint is active.
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*/
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if (usb_gettoggle(urb->dev, usb_pipeendpoint(urb->pipe), is_out)) {
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toggle = TD_T_CARRY;
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} else {
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toggle = TD_T_DATA0;
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usb_settoggle(urb->dev, usb_pipeendpoint (urb->pipe),
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is_out, 1);
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}
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urb_priv->td_idx = 0;
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if (data_len)
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data = urb->transfer_dma;
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else
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data = 0;
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/* NOTE: TD_CC is set so we can tell which TDs the HC processed by
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* using TD_CC_GET, as well as by seeing them on the done list.
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* (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
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*/
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switch (urb_priv->ed->type) {
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case PIPE_INTERRUPT:
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info = is_out
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? TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_OUT
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: TD_T_CARRY | TD_SCC_NOTACCESSED | TD_DP_IN;
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/* setup service interval and starting frame number */
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info |= (urb->start_frame & TD_FN_MASK);
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info |= (urb->interval & TD_ISI_MASK) << TD_ISI_SHIFT;
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td_fill(ahcd, info, data, data_len, urb_priv);
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cnt++;
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admhcd_to_hcd(ahcd)->self.bandwidth_int_reqs++;
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break;
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case PIPE_BULK:
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info = is_out
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? TD_SCC_NOTACCESSED | TD_DP_OUT
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: TD_SCC_NOTACCESSED | TD_DP_IN;
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/* TDs _could_ transfer up to 8K each */
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while (data_len > TD_DATALEN_MAX) {
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td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle),
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data, TD_DATALEN_MAX, urb_priv);
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data += TD_DATALEN_MAX;
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data_len -= TD_DATALEN_MAX;
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cnt++;
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}
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td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle), data,
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data_len, urb_priv);
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cnt++;
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if ((urb->transfer_flags & URB_ZERO_PACKET)
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&& (cnt < urb_priv->td_cnt)) {
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td_fill(ahcd, info | ((cnt) ? TD_T_CARRY : toggle),
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0, 0, urb_priv);
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cnt++;
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}
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break;
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/* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
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* any DATA phase works normally, and the STATUS ack is special.
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*/
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case PIPE_CONTROL:
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/* fill a TD for the setup */
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info = TD_SCC_NOTACCESSED | TD_DP_SETUP | TD_T_DATA0;
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td_fill(ahcd, info, urb->setup_dma, 8, urb_priv);
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cnt++;
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if (data_len > 0) {
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/* fill a TD for the data */
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info = TD_SCC_NOTACCESSED | TD_T_DATA1;
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info |= is_out ? TD_DP_OUT : TD_DP_IN;
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/* NOTE: mishandles transfers >8K, some >4K */
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td_fill(ahcd, info, data, data_len, urb_priv);
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cnt++;
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}
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/* fill a TD for the ACK */
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info = (is_out || data_len == 0)
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? TD_SCC_NOTACCESSED | TD_DP_IN | TD_T_DATA1
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: TD_SCC_NOTACCESSED | TD_DP_OUT | TD_T_DATA1;
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td_fill(ahcd, info, data, 0, urb_priv);
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cnt++;
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break;
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/* ISO has no retransmit, so no toggle;
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* Each TD could handle multiple consecutive frames (interval 1);
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* we could often reduce the number of TDs here.
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*/
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case PIPE_ISOCHRONOUS:
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info = TD_SCC_NOTACCESSED;
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for (cnt = 0; cnt < urb->number_of_packets; cnt++) {
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int frame = urb->start_frame;
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frame += cnt * urb->interval;
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frame &= TD_FN_MASK;
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td_fill(ahcd, info | frame,
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data + urb->iso_frame_desc[cnt].offset,
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urb->iso_frame_desc[cnt].length,
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urb_priv);
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}
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admhcd_to_hcd(ahcd)->self.bandwidth_isoc_reqs++;
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break;
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}
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if (urb_priv->td_cnt != cnt)
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admhc_err(ahcd, "bad number of tds created for urb %p\n", urb);
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urb_priv->td_idx = 0;
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}
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/* calculate transfer length/status and update the urb
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* PRECONDITION: irqsafe (only for urb->status locking)
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*/
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static int td_done(struct admhcd *ahcd, struct urb *urb, struct td *td)
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{
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u32 info = hc32_to_cpup(ahcd, &td->hwINFO);
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u32 dbp = hc32_to_cpup(ahcd, &td->hwDBP);
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u32 cbl = TD_BL_GET(hc32_to_cpup(ahcd, &td->hwCBL));
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int type = usb_pipetype(urb->pipe);
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int cc;
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cc = TD_CC_GET(info);
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/* ISO ... drivers see per-TD length/status */
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if (type == PIPE_ISOCHRONOUS) {
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#if 0
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/* TODO */
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int dlen = 0;
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/* NOTE: assumes FC in tdINFO == 0, and that
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* only the first of 0..MAXPSW psws is used.
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*/
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cc = TD_CC_GET(td);
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if (tdINFO & TD_CC) /* hc didn't touch? */
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return;
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if (usb_pipeout (urb->pipe))
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dlen = urb->iso_frame_desc[td->index].length;
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else {
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/* short reads are always OK for ISO */
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if (cc == TD_DATAUNDERRUN)
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cc = TD_CC_NOERROR;
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dlen = tdPSW & 0x3ff;
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}
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urb->actual_length += dlen;
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urb->iso_frame_desc[td->index].actual_length = dlen;
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urb->iso_frame_desc[td->index].status = cc_to_error[cc];
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if (cc != TD_CC_NOERROR)
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admhc_vdbg (ahcd,
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"urb %p iso td %p (%d) len %d cc %d\n",
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urb, td, 1 + td->index, dlen, cc);
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#endif
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/* BULK, INT, CONTROL ... drivers see aggregate length/status,
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* except that "setup" bytes aren't counted and "short" transfers
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* might not be reported as errors.
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*/
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} else {
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admhc_dump_td(ahcd, "td_done", td);
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/* count all non-empty packets except control SETUP packet */
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if ((type != PIPE_CONTROL || td->index != 0) && dbp != 0) {
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urb->actual_length += dbp - td->data_dma + cbl;
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}
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}
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return cc;
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}
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/*-------------------------------------------------------------------------*/
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static inline struct td *
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ed_halted(struct admhcd *ahcd, struct td *td, int cc, struct td *rev)
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{
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#if 0
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struct urb *urb = td->urb;
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struct ed *ed = td->ed;
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struct list_head *tmp = td->td_list.next;
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__hc32 toggle = ed->hwHeadP & cpu_to_hc32 (ahcd, ED_C);
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admhc_dump_ed(ahcd, "ed halted", td->ed, 1);
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/* clear ed halt; this is the td that caused it, but keep it inactive
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* until its urb->complete() has a chance to clean up.
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*/
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ed->hwINFO |= cpu_to_hc32 (ahcd, ED_SKIP);
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wmb ();
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ed->hwHeadP &= ~cpu_to_hc32 (ahcd, ED_H);
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/* put any later tds from this urb onto the donelist, after 'td',
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* order won't matter here: no errors, and nothing was transferred.
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* also patch the ed so it looks as if those tds completed normally.
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*/
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while (tmp != &ed->td_list) {
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struct td *next;
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__hc32 info;
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next = list_entry(tmp, struct td, td_list);
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tmp = next->td_list.next;
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if (next->urb != urb)
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break;
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/* NOTE: if multi-td control DATA segments get supported,
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* this urb had one of them, this td wasn't the last td
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* in that segment (TD_R clear), this ed halted because
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* of a short read, _and_ URB_SHORT_NOT_OK is clear ...
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* then we need to leave the control STATUS packet queued
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* and clear ED_SKIP.
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*/
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info = next->hwINFO;
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#if 0 /* FIXME */
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info |= cpu_to_hc32 (ahcd, TD_DONE);
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info &= ~cpu_to_hc32 (ahcd, TD_CC);
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#endif
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next->hwINFO = info;
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|
|
next->next_dl_td = rev;
|
|
rev = next;
|
|
|
|
ed->hwHeadP = next->hwNextTD | toggle;
|
|
}
|
|
|
|
/* help for troubleshooting: report anything that
|
|
* looks odd ... that doesn't include protocol stalls
|
|
* (or maybe some other things)
|
|
*/
|
|
switch (cc) {
|
|
case TD_CC_DATAUNDERRUN:
|
|
if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
|
|
break;
|
|
/* fallthrough */
|
|
case TD_CC_STALL:
|
|
if (usb_pipecontrol (urb->pipe))
|
|
break;
|
|
/* fallthrough */
|
|
default:
|
|
admhc_dbg (ahcd,
|
|
"urb %p path %s ep%d%s %08x cc %d --> status %d\n",
|
|
urb, urb->dev->devpath,
|
|
usb_pipeendpoint (urb->pipe),
|
|
usb_pipein (urb->pipe) ? "in" : "out",
|
|
hc32_to_cpu(ahcd, td->hwINFO),
|
|
cc, cc_to_error [cc]);
|
|
}
|
|
|
|
return rev;
|
|
#else
|
|
return NULL;
|
|
#endif
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
static int ed_next_urb(struct admhcd *ahcd, struct ed *ed)
|
|
{
|
|
struct urb_priv *up;
|
|
u32 carry;
|
|
|
|
if (ed->state != ED_IDLE)
|
|
return 1;
|
|
|
|
if (ed->urb_active)
|
|
return 1;
|
|
|
|
if (list_empty(&ed->urb_pending))
|
|
return 0;
|
|
|
|
up = list_entry(ed->urb_pending.next, struct urb_priv, pending);
|
|
list_del(&up->pending);
|
|
ed->urb_active = up;
|
|
ed->state = ED_OPER;
|
|
|
|
#ifdef ADMHC_VERBOSE_DEBUG
|
|
urb_print(ahcd, up->urb, "NEXT", 0);
|
|
admhc_dump_ed(ahcd, " ", ed, 0);
|
|
#endif
|
|
|
|
up->td[up->td_cnt-1]->hwNextTD = cpu_to_hc32(ahcd, ed->dummy->td_dma);
|
|
|
|
carry = hc32_to_cpup(ahcd, &ed->hwHeadP) & ED_C;
|
|
ed->hwHeadP = cpu_to_hc32(ahcd, up->td[0]->td_dma | carry);
|
|
ed->hwINFO &= ~cpu_to_hc32(ahcd, ED_SKIP);
|
|
|
|
return 1;
|
|
}
|
|
|
|
static void ed_update(struct admhcd *ahcd, struct ed *ed, int partial)
|
|
{
|
|
struct urb_priv *up;
|
|
struct urb *urb;
|
|
int cc;
|
|
|
|
up = ed->urb_active;
|
|
if (!up)
|
|
return;
|
|
|
|
urb = up->urb;
|
|
|
|
#ifdef ADMHC_VERBOSE_DEBUG
|
|
urb_print(ahcd, urb, "UPDATE", 0);
|
|
#endif
|
|
admhc_dump_ed(ahcd, "ED-UPDATE", ed, 1);
|
|
|
|
cc = TD_CC_NOERROR;
|
|
for (; up->td_idx < up->td_cnt; up->td_idx++) {
|
|
struct td *td = up->td[up->td_idx];
|
|
|
|
if (hc32_to_cpup(ahcd, &td->hwINFO) & TD_OWN)
|
|
break;
|
|
|
|
cc = td_done(ahcd, urb, td);
|
|
if (cc != TD_CC_NOERROR) {
|
|
admhc_vdbg(ahcd,
|
|
"urb %p td %p (%d) cc %d, len=%d/%d\n",
|
|
urb, td, td->index, cc,
|
|
urb->actual_length,
|
|
urb->transfer_buffer_length);
|
|
|
|
up->td_idx = up->td_cnt;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if ((up->td_idx != up->td_cnt) && (!partial))
|
|
/* the URB is not completed yet */
|
|
return;
|
|
|
|
/* update packet status if needed (short is normally ok) */
|
|
if (cc == TD_CC_DATAUNDERRUN
|
|
&& !(urb->transfer_flags & URB_SHORT_NOT_OK))
|
|
cc = TD_CC_NOERROR;
|
|
|
|
if (cc != TD_CC_NOERROR && cc < TD_CC_HCD0) {
|
|
spin_lock(&urb->lock);
|
|
if (urb->status == -EINPROGRESS)
|
|
urb->status = cc_to_error[cc];
|
|
spin_unlock(&urb->lock);
|
|
}
|
|
|
|
finish_urb(ahcd, urb);
|
|
|
|
ed->urb_active = NULL;
|
|
ed->state = ED_IDLE;
|
|
}
|
|
|
|
/* there are some tds completed; called in_irq(), with HCD locked */
|
|
static void admhc_td_complete(struct admhcd *ahcd)
|
|
{
|
|
struct ed *ed;
|
|
|
|
for (ed = ahcd->ed_head; ed; ed = ed->ed_next) {
|
|
if (ed->state != ED_OPER)
|
|
continue;
|
|
|
|
if (hc32_to_cpup(ahcd, &ed->hwINFO) & ED_SKIP)
|
|
continue;
|
|
|
|
if (hc32_to_cpup(ahcd, &ed->hwHeadP) & ED_H) {
|
|
/* TODO */
|
|
continue;
|
|
}
|
|
|
|
ed_update(ahcd, ed, 0);
|
|
}
|
|
}
|
|
|
|
/* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
|
|
static void admhc_finish_unlinks(struct admhcd *ahcd, u16 tick)
|
|
{
|
|
struct ed *ed;
|
|
|
|
for (ed = ahcd->ed_head; ed; ed = ed->ed_next) {
|
|
if (ed->state != ED_UNLINK)
|
|
continue;
|
|
|
|
if (likely(HC_IS_RUNNING(admhcd_to_hcd(ahcd)->state)))
|
|
if (tick_before(tick, ed->tick))
|
|
continue;
|
|
|
|
/* process partial status */
|
|
ed_update(ahcd, ed, 1);
|
|
}
|
|
}
|
|
|
|
static void admhc_sof_refill(struct admhcd *ahcd)
|
|
{
|
|
struct ed *ed;
|
|
int disable_dma = 1;
|
|
|
|
for (ed = ahcd->ed_head; ed; ed = ed->ed_next) {
|
|
|
|
if (hc32_to_cpup(ahcd, &ed->hwHeadP) & ED_H) {
|
|
ed_update(ahcd, ed, 1);
|
|
ed->hwHeadP &= ~cpu_to_hc32 (ahcd, ED_H);
|
|
}
|
|
|
|
if (ed_next_urb(ahcd, ed)) {
|
|
disable_dma = 0;
|
|
} else {
|
|
struct ed *tmp;
|
|
tmp = ed->ed_prev;
|
|
ed_deschedule(ahcd, ed);
|
|
ed = tmp;
|
|
}
|
|
}
|
|
|
|
if (disable_dma) {
|
|
admhc_intr_disable(ahcd, ADMHC_INTR_SOFI);
|
|
admhc_dma_disable(ahcd);
|
|
} else {
|
|
admhc_intr_enable(ahcd, ADMHC_INTR_SOFI);
|
|
admhc_dma_enable(ahcd);
|
|
}
|
|
}
|