mirror of https://github.com/hak5/openwrt.git
ipq806x: fix "reboot" command
The watchdog driver already registers a restart notifier, we just have to enable it in the config and in the DT to fix the "reboot" command. This is done by integratin the following patch-set: https://lkml.org/lkml/2015/2/20/610 I'm copy-pasting the description below: qcom-wdt is currently assuming the presence of a dedicated node in DT to gets its configuration. However, on msm architecture, the watchdog is usually part of the timer block. So this patch-set is changing the driver and slightly enhancing the timer DT bindings to provide the relevant clocks and interrupts. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 44504lede-17.01
John Crispin
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5072954cd0
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565a6f2a27
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@ -0,0 +1,72 @@
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From fded70251b1b58f68de1d3757ece9965f0b75452 Mon Sep 17 00:00:00 2001
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From: Mathieu Olivari <mathieu@codeaurora.org>
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Date: Thu, 19 Feb 2015 20:19:30 -0800
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Subject: [PATCH 1/3] watchdog: qcom: use timer devicetree binding
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MSM watchdog configuration happens in the same register block as the
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timer, so we'll use the same binding as the existing timer.
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The qcom-wdt will now be probed when devicetree has an entry compatible
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with "qcom,kpss-timer" or "qcom-scss-timer".
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Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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---
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drivers/watchdog/qcom-wdt.c | 21 +++++++++++++++------
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1 file changed, 15 insertions(+), 6 deletions(-)
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diff --git a/drivers/watchdog/qcom-wdt.c b/drivers/watchdog/qcom-wdt.c
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index aa85618..aa03ca8 100644
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--- a/drivers/watchdog/qcom-wdt.c
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+++ b/drivers/watchdog/qcom-wdt.c
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@@ -20,9 +20,9 @@
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#include <linux/reboot.h>
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#include <linux/watchdog.h>
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-#define WDT_RST 0x0
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-#define WDT_EN 0x8
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-#define WDT_BITE_TIME 0x24
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+#define WDT_RST 0x38
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+#define WDT_EN 0x40
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+#define WDT_BITE_TIME 0x5C
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struct qcom_wdt {
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struct watchdog_device wdd;
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@@ -117,6 +117,8 @@ static int qcom_wdt_probe(struct platform_device *pdev)
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{
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struct qcom_wdt *wdt;
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struct resource *res;
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+ struct device_node *np = pdev->dev.of_node;
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+ u32 percpu_offset;
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int ret;
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wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
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@@ -124,6 +126,14 @@ static int qcom_wdt_probe(struct platform_device *pdev)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+
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+ /* We use CPU0's DGT for the watchdog */
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+ if (of_property_read_u32(np, "cpu-offset", &percpu_offset))
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+ percpu_offset = 0;
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+
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+ res->start += percpu_offset;
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+ res->end += percpu_offset;
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+
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wdt->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(wdt->base))
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return PTR_ERR(wdt->base);
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@@ -203,9 +213,8 @@ static int qcom_wdt_remove(struct platform_device *pdev)
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}
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static const struct of_device_id qcom_wdt_of_table[] = {
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- { .compatible = "qcom,kpss-wdt-msm8960", },
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- { .compatible = "qcom,kpss-wdt-apq8064", },
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- { .compatible = "qcom,kpss-wdt-ipq8064", },
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+ { .compatible = "qcom,kpss-timer" },
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+ { .compatible = "qcom,scss-timer" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, qcom_wdt_of_table);
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--
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1.9.1
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@ -0,0 +1,53 @@
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From 297cf8136ecd6a56520888fd28948393766b8ee7 Mon Sep 17 00:00:00 2001
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From: Mathieu Olivari <mathieu@codeaurora.org>
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Date: Thu, 19 Feb 2015 20:27:39 -0800
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Subject: [PATCH 2/3] ARM: qcom: add description of KPSS WDT for IPQ8064
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Add the watchdog related entries to the Krait Processor Sub-system
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(KPSS) timer IPQ8064 devicetree section. Also, add a fixed-clock
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description of SLEEP_CLK, which will do for now.
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Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
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Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-ipq8064.dtsi | 14 +++++++++++++-
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1 file changed, 13 insertions(+), 1 deletion(-)
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diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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index cb225da..d01f618 100644
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -60,6 +60,14 @@
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};
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};
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+ clocks {
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+ sleep_clk: sleep_clk {
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+ compatible = "fixed-clock";
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+ clock-frequency = <32768>;
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+ #clock-cells = <0>;
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+ };
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+ };
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+
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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@@ -89,10 +97,14 @@
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compatible = "qcom,kpss-timer", "qcom,msm-timer";
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interrupts = <1 1 0x301>,
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<1 2 0x301>,
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- <1 3 0x301>;
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+ <1 3 0x301>,
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+ <1 4 0x301>,
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+ <1 5 0x301>;
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reg = <0x0200a000 0x100>;
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clock-frequency = <25000000>,
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<32768>;
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+ clocks = <&sleep_clk>;
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+ clock-names = "sleep";
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cpu-offset = <0x80000>;
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};
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--
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1.9.1
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@ -0,0 +1,50 @@
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From e535f01dffb6dd9e09934fa219be52af3437a8f6 Mon Sep 17 00:00:00 2001
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From: Mathieu Olivari <mathieu@codeaurora.org>
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Date: Thu, 19 Feb 2015 20:36:27 -0800
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Subject: [PATCH 3/3] ARM: msm: add watchdog entries to DT timer binding doc
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The watchdog has been reworked to use the same DT node as the timer.
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This change is updating the device tree doc accordingly.
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Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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---
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Documentation/devicetree/bindings/arm/msm/timer.txt | 16 +++++++++++++---
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1 file changed, 13 insertions(+), 3 deletions(-)
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--- a/Documentation/devicetree/bindings/arm/msm/timer.txt
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+++ b/Documentation/devicetree/bindings/arm/msm/timer.txt
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@@ -9,11 +9,17 @@ Properties:
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"qcom,scss-timer" - scorpion subsystem
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- interrupts : Interrupts for the the debug timer, the first general purpose
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- timer, and optionally a second general purpose timer in that
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- order.
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+ timer, and optionally a second general purpose timer, and
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+ optionally as well, 2 watchdog interrupts, in that order.
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- reg : Specifies the base address of the timer registers.
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+- clocks: Reference to the parent clocks, one per output clock. The parents
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+ must appear in the same order as the clock names.
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+
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+- clock-names: The name of the clocks as free-form strings. They should be in
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+ the same order as the clocks.
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+
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- clock-frequency : The frequency of the debug timer and the general purpose
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timer(s) in Hz in that order.
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@@ -29,9 +35,13 @@ Example:
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compatible = "qcom,scss-timer", "qcom,msm-timer";
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interrupts = <1 1 0x301>,
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<1 2 0x301>,
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- <1 3 0x301>;
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+ <1 3 0x301>,
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+ <1 4 0x301>,
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+ <1 5 0x301>;
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reg = <0x0200a000 0x100>;
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clock-frequency = <19200000>,
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<32768>;
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+ clocks = <&sleep_clk>;
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+ clock-names = "sleep";
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cpu-offset = <0x40000>;
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};
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