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ar71xx: fix ethernet on wnr2000-v4 

Most people report broken ethernet with upstream. Last year, user "franz.flasch"
authored a working mach-file. His patch is outdated so I modernized it. Original
patch and user commentary on page 1:
https://forum.openwrt.org/viewtopic.php?pid=260861#p260861

I have figured out what the critical differences are between the two that caused
upstream ethernet to break.
  1) Both ath79_init_mac() functions calls must be invocated before any GMAC init
  2) must init GMAC0 before GMAC1

That was enough to get upstream to function, but I wanted to enjoy my confidence
having tested franz's patch for a week sucessfully, so I put his whole
function in, which only features more differences in order of function calls.

An expert should consider these changes, which could pose potential bugs/issues:
1) No longer using the flag AR934X_ETH_CFG_SW_PHY_SWAP in the
ath79_setup_ar934x_eth_cfg() call.

2) Possible consequence of no longer explicitly setting ethernet duplex/speed.

Review: With this patch, my ethernet and wireless works.

Signed-off-by: Michael J. Bazzinotti <mbazzinotti@gmail.com>

SVN-Revision: 45633
owl
Felix Fietkau 2015-05-08 12:23:45 +00:00
parent 5c5648f4b7
commit 6413f40e96
1 changed files with 12 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
target/linux/ar71xx/files/arch/mips/ath79/mach-wnr2000-v4.c
View File

@ -122,42 +122,32 @@ static struct gpio_keys_button wnr2000v4_gpio_keys[] __initdata = {
static void __init wnr_common_setup(void) static void __init wnr_common_setup(void)
{ {
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_register_m25p80(NULL);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE |
AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0); ath79_register_mdio(1, 0x0);
/* LAN */ ath79_register_usb();
ath79_init_mac(ath79_eth1_data.mac_addr, art+WNR2000V4_MAC0_OFFSET, 0);
/* GMAC1 is connected to the internal switch */ ath79_register_m25p80(NULL);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
/* WAN */ ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
ath79_init_mac(ath79_eth0_data.mac_addr, art+WNR2000V4_MAC1_OFFSET, 0);
/* GMAC0 is connected to the PHY0 of the internal switch */ ath79_init_mac(ath79_eth0_data.mac_addr, art+WNR2000V4_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art+WNR2000V4_MAC1_OFFSET, 0);
/* GMAC0 is connected to the PHY0 of the internal switch, GE0 */
ath79_switch_data.phy4_mii_en = 1; ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(4); ath79_switch_data.phy_poll_mask = BIT(4);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(4); ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev; ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_register_eth(0); ath79_register_eth(0);
/* WLAN */ /* GMAC1 is connected to the internal switch, GE1 */
ath79_register_wmac(ee, art+WNR2000V4_MAC0_OFFSET); ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
/* USB */ ath79_register_wmac(ee, art);
ath79_register_usb();
} }
static void __init wnr2000v4_setup(void) static void __init wnr2000v4_setup(void)