171 lines
6.2 KiB
Diff
171 lines
6.2 KiB
Diff
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
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+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
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@@ -20,22 +20,22 @@
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#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */
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#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */
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-#define CNS3XXX_SWITCH_BASE_VIRT 0xFFF00000
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+#define CNS3XXX_SWITCH_BASE_VIRT 0xFEF00000
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#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */
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-#define CNS3XXX_PPE_BASE_VIRT 0xFFF50000
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+#define CNS3XXX_PPE_BASE_VIRT 0xFEF50000
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#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */
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-#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFFF60000
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+#define CNS3XXX_EMBEDDED_SRAM_BASE_VIRT 0xFEF60000
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#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */
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-#define CNS3XXX_SSP_BASE_VIRT 0xFFF01000
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+#define CNS3XXX_SSP_BASE_VIRT 0xFEF01000
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#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */
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-#define CNS3XXX_DMC_BASE_VIRT 0xFFF02000
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+#define CNS3XXX_DMC_BASE_VIRT 0xFEF02000
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#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */
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-#define CNS3XXX_SMC_BASE_VIRT 0xFFF03000
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+#define CNS3XXX_SMC_BASE_VIRT 0xFEF03000
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#define SMC_MEMC_STATUS_OFFSET 0x000
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#define SMC_MEMIF_CFG_OFFSET 0x004
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@@ -74,13 +74,13 @@
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#define SMC_PCELL_ID_3_OFFSET 0xFFC
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#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */
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-#define CNS3XXX_GPIOA_BASE_VIRT 0xFFF04000
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+#define CNS3XXX_GPIOA_BASE_VIRT 0xFEF04000
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#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */
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-#define CNS3XXX_GPIOB_BASE_VIRT 0xFFF05000
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+#define CNS3XXX_GPIOB_BASE_VIRT 0xFEF05000
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#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */
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-#define CNS3XXX_RTC_BASE_VIRT 0xFFF06000
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+#define CNS3XXX_RTC_BASE_VIRT 0xFEF06000
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#define RTC_SEC_OFFSET 0x00
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#define RTC_MIN_OFFSET 0x04
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@@ -94,10 +94,10 @@
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#define RTC_INTR_STS_OFFSET 0x34
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#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */
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-#define CNS3XXX_MISC_BASE_VIRT 0xFB000000 /* Misc Control */
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+#define CNS3XXX_MISC_BASE_VIRT 0xFEF07000 /* Misc Control */
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#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */
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-#define CNS3XXX_PM_BASE_VIRT 0xFB001000
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+#define CNS3XXX_PM_BASE_VIRT 0xFEF08000
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#define PM_CLK_GATE_OFFSET 0x00
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#define PM_SOFT_RST_OFFSET 0x04
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@@ -109,28 +109,28 @@
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#define PM_PLL_HM_PD_OFFSET 0x1C
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#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */
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-#define CNS3XXX_UART0_BASE_VIRT 0xFB002000
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+#define CNS3XXX_UART0_BASE_VIRT 0xFEF09000
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#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */
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-#define CNS3XXX_UART1_BASE_VIRT 0xFFF0A000
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+#define CNS3XXX_UART1_BASE_VIRT 0xFEF0A000
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#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */
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-#define CNS3XXX_UART2_BASE_VIRT 0xFFF0B000
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+#define CNS3XXX_UART2_BASE_VIRT 0xFEF0B000
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#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */
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-#define CNS3XXX_DMAC_BASE_VIRT 0xFFF0D000
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+#define CNS3XXX_DMAC_BASE_VIRT 0xFEF0D000
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#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */
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-#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFFF0E000
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+#define CNS3XXX_CORESIGHT_BASE_VIRT 0xFEF0E000
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#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */
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-#define CNS3XXX_CRYPTO_BASE_VIRT 0xFFF0F000
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+#define CNS3XXX_CRYPTO_BASE_VIRT 0xFEF0F000
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#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */
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-#define CNS3XXX_I2S_BASE_VIRT 0xFFF10000
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+#define CNS3XXX_I2S_BASE_VIRT 0xFEF10000
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#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */
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-#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000
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+#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFEF10800
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#define TIMER1_COUNTER_OFFSET 0x00
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#define TIMER1_AUTO_RELOAD_OFFSET 0x04
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@@ -150,42 +150,42 @@
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#define TIMER_FREERUN_CONTROL_OFFSET 0x44
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#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */
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-#define CNS3XXX_HCIE_BASE_VIRT 0xFFF30000
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+#define CNS3XXX_HCIE_BASE_VIRT 0xFEF30000
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#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */
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-#define CNS3XXX_RAID_BASE_VIRT 0xFFF12000
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+#define CNS3XXX_RAID_BASE_VIRT 0xFEF12000
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#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */
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-#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFFF13000
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+#define CNS3XXX_AXI_IXC_BASE_VIRT 0xFEF13000
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#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */
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-#define CNS3XXX_CLCD_BASE_VIRT 0xFFF14000
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+#define CNS3XXX_CLCD_BASE_VIRT 0xFEF14000
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#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */
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-#define CNS3XXX_USBOTG_BASE_VIRT 0xFFF15000
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+#define CNS3XXX_USBOTG_BASE_VIRT 0xFEF15000
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#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */
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#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */
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#define CNS3XXX_SATA2_SIZE SZ_16M
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-#define CNS3XXX_SATA2_BASE_VIRT 0xFFF17000
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+#define CNS3XXX_SATA2_BASE_VIRT 0xFEF17000
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#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */
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-#define CNS3XXX_CAMERA_BASE_VIRT 0xFFF18000
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+#define CNS3XXX_CAMERA_BASE_VIRT 0xFEF18000
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#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */
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-#define CNS3XXX_SDIO_BASE_VIRT 0xFFF19000
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+#define CNS3XXX_SDIO_BASE_VIRT 0xFEF19000
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#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */
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-#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFFF1A000
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+#define CNS3XXX_I2S_TDM_BASE_VIRT 0xFEF1A000
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#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */
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-#define CNS3XXX_2DG_BASE_VIRT 0xFFF1B000
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+#define CNS3XXX_2DG_BASE_VIRT 0xFEF1B000
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#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */
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#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */
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-#define CNS3XXX_L2C_BASE_VIRT 0xFFF27000
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+#define CNS3XXX_L2C_BASE_VIRT 0xFEF27000
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#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */
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#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000
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@@ -227,7 +227,7 @@
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* Testchip peripheral and fpga gic regions
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*/
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#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */
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-#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFB004000
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+#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFEE00000
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#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */
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#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100)
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@@ -239,7 +239,7 @@
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#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000)
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#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */
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-#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFF002000
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+#define CNS3XXX_TC11MP_L220_BASE_VIRT 0xFEE02000
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/*
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* Misc block
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