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wifipineapple-openwrt/target/linux/au1000/patches-2.6.28/007-gpiolib.patch

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--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -134,3 +134,4 @@ config SOC_AU1X00
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_APM_EMULATION
+ select ARCH_REQUIRE_GPIOLIB
--- a/arch/mips/alchemy/common/gpio.c
+++ b/arch/mips/alchemy/common/gpio.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2007, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
+ * Copyright (C) 2007-2008, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
* Architecture specific GPIO support
*
* This program is free software; you can redistribute it and/or modify it
@@ -27,122 +27,222 @@
* others have a second one : GPIO2
*/
+#include <linux/kernel.h>
#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
#include <asm/mach-au1x00/au1000.h>
-#include <asm/gpio.h>
+#include <asm/mach-au1x00/gpio.h>
-#define gpio1 sys
-#if !defined(CONFIG_SOC_AU1000)
+struct au1000_gpio_chip {
+ struct gpio_chip chip;
+ void __iomem *regbase;
+};
-static struct au1x00_gpio2 *const gpio2 = (struct au1x00_gpio2 *) GPIO2_BASE;
+#if !defined(CONFIG_SOC_AU1000)
#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000
-static int au1xxx_gpio2_read(unsigned gpio)
+/*
+ * Return GPIO bank 2 level
+ */
+static int au1000_gpio2_get(struct gpio_chip *chip, unsigned offset)
{
- gpio -= AU1XXX_GPIO_BASE;
- return ((gpio2->pinstate >> gpio) & 0x01);
+ u32 mask = 1 << offset;
+ struct au1000_gpio_chip *gpch;
+
+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
+ return readl(gpch->regbase + AU1000_GPIO2_ST) & mask;
}
-static void au1xxx_gpio2_write(unsigned gpio, int value)
+/*
+ * Set output GPIO bank 2 level
+ */
+static void au1000_gpio2_set(struct gpio_chip *chip,
+ unsigned offset, int value)
{
- gpio -= AU1XXX_GPIO_BASE;
-
- gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio);
+ u32 mask = (!!value) << offset;
+ struct au1000_gpio_chip *gpch;
+ unsigned long flags;
+
+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
+
+ local_irq_save(flags);
+ writel((GPIO2_OUTPUT_ENABLE_MASK << offset) | mask,
+ gpch->regbase + AU1000_GPIO2_OUT);
+ local_irq_restore(flags);
}
-static int au1xxx_gpio2_direction_input(unsigned gpio)
+/*
+ * Set GPIO bank 2 direction to input
+ */
+static int au1000_gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
{
- gpio -= AU1XXX_GPIO_BASE;
- gpio2->dir &= ~(0x01 << gpio);
+ unsigned long flags;
+ u32 mask = 1 << offset;
+ u32 value;
+ struct au1000_gpio_chip *gpch;
+ void __iomem *gpdr;
+
+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
+ gpdr = gpch->regbase + AU1000_GPIO2_DIR;
+
+ local_irq_save(flags);
+ value = readl(gpdr);
+ value &= ~mask;
+ writel(value, gpdr);
+ local_irq_restore(flags);
+
return 0;
}
-static int au1xxx_gpio2_direction_output(unsigned gpio, int value)
+/*
+ * Set GPIO bank2 direction to output
+ */
+static int au1000_gpio2_direction_output(struct gpio_chip *chip,
+ unsigned offset, int value)
{
- gpio -= AU1XXX_GPIO_BASE;
- gpio2->dir |= 0x01 << gpio;
- gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio);
+ unsigned long flags;
+ u32 mask = 1 << offset;
+ u32 tmp;
+ struct au1000_gpio_chip *gpch;
+ void __iomem *gpdr;
+
+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
+ gpdr = gpch->regbase + AU1000_GPIO2_DIR;
+
+ local_irq_save(flags);
+ tmp = readl(gpdr);
+ tmp |= mask;
+ writel(tmp, gpdr);
+ mask = (!!value) << offset;
+ writel((GPIO2_OUTPUT_ENABLE_MASK << offset) | mask,
+ gpch->regbase + AU1000_GPIO2_OUT);
+ local_irq_restore(flags);
+
return 0;
}
-
#endif /* !defined(CONFIG_SOC_AU1000) */
-static int au1xxx_gpio1_read(unsigned gpio)
+/*
+ * Return GPIO bank 2 level
+ */
+static int au1000_gpio1_get(struct gpio_chip *chip, unsigned offset)
{
- return (gpio1->pinstaterd >> gpio) & 0x01;
+ u32 mask = 1 << offset;
+ struct au1000_gpio_chip *gpch;
+
+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
+ return readl(gpch->regbase + 0x0110) & mask;
}
-static void au1xxx_gpio1_write(unsigned gpio, int value)
+/*
+ * Set GPIO bank 1 level
+ */
+static void au1000_gpio1_set(struct gpio_chip *chip,
+ unsigned offset, int value)
{
+ unsigned long flags;
+ u32 mask = 1 << offset;
+ struct au1000_gpio_chip *gpch;
+
+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
+
+ local_irq_save(flags);
if (value)
- gpio1->outputset = (0x01 << gpio);
+ writel(mask, gpch->regbase + 0x0108);
else
- /* Output a zero */
- gpio1->outputclr = (0x01 << gpio);
+ writel(mask, gpch->regbase + 0x010C);
+ local_irq_restore(flags);
}
-static int au1xxx_gpio1_direction_input(unsigned gpio)
+/*
+ * Set GPIO bank 1 direction to input
+ */
+static int au1000_gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
{
- gpio1->pininputen = (0x01 << gpio);
- return 0;
-}
+ unsigned long flags;
+ u32 mask = 1 << offset;
+ u32 value;
+ struct au1000_gpio_chip *gpch;
+ void __iomem *gpdr;
+
+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
+ gpdr = gpch->regbase + 0x0110;
+
+ local_irq_save(flags);
+ value = readl(gpdr);
+ value |= mask;
+ writel(mask, gpdr);
+ local_irq_restore(flags);
-static int au1xxx_gpio1_direction_output(unsigned gpio, int value)
-{
- gpio1->trioutclr = (0x01 & gpio);
- au1xxx_gpio1_write(gpio, value);
return 0;
}
-int au1xxx_gpio_get_value(unsigned gpio)
+/*
+ * Set GPIO bank 1 direction to output
+ */
+static int au1000_gpio1_direction_output(struct gpio_chip *chip,
+ unsigned offset, int value)
{
- if (gpio >= AU1XXX_GPIO_BASE)
-#if defined(CONFIG_SOC_AU1000)
- return 0;
-#else
- return au1xxx_gpio2_read(gpio);
-#endif
+ unsigned long flags;
+ u32 mask = 1 << offset;
+ u32 tmp;
+ struct au1000_gpio_chip *gpch;
+ void __iomem *gpdr;
+
+ gpch = container_of(chip, struct au1000_gpio_chip, chip);
+ gpdr = gpch->regbase + 0x0100;
+
+ local_irq_save(flags);
+ tmp = readl(gpdr);
+ writel(tmp, gpdr);
+ if (value)
+ writel(mask, gpch->regbase + 0x0108);
else
- return au1xxx_gpio1_read(gpio);
-}
-EXPORT_SYMBOL(au1xxx_gpio_get_value);
+ writel(mask, gpch->regbase + 0x0108);
+ local_irq_restore(flags);
-void au1xxx_gpio_set_value(unsigned gpio, int value)
-{
- if (gpio >= AU1XXX_GPIO_BASE)
-#if defined(CONFIG_SOC_AU1000)
- ;
-#else
- au1xxx_gpio2_write(gpio, value);
-#endif
- else
- au1xxx_gpio1_write(gpio, value);
+ return 0;
}
-EXPORT_SYMBOL(au1xxx_gpio_set_value);
-int au1xxx_gpio_direction_input(unsigned gpio)
-{
- if (gpio >= AU1XXX_GPIO_BASE)
-#if defined(CONFIG_SOC_AU1000)
- return -ENODEV;
-#else
- return au1xxx_gpio2_direction_input(gpio);
+struct au1000_gpio_chip au1000_gpio_chip[] = {
+ [0] = {
+ .regbase = (void __iomem *)SYS_BASE,
+ .chip = {
+ .label = "au1000-gpio1",
+ .direction_input = au1000_gpio1_direction_input,
+ .direction_output = au1000_gpio1_direction_output,
+ .get = au1000_gpio1_get,
+ .set = au1000_gpio1_set,
+ .base = 0,
+ .ngpio = 32,
+ },
+ },
+#if !defined(CONFIG_SOC_AU1000)
+ [1] = {
+ .regbase = (void __iomem *)GPIO2_BASE,
+ .chip = {
+ .label = "au1000-gpio2",
+ .direction_input = au1000_gpio2_direction_input,
+ .direction_output = au1000_gpio2_direction_output,
+ .get = au1000_gpio2_get,
+ .set = au1000_gpio2_set,
+ .base = AU1XXX_GPIO_BASE,
+ .ngpio = 32,
+ },
+ },
#endif
+};
- return au1xxx_gpio1_direction_input(gpio);
-}
-EXPORT_SYMBOL(au1xxx_gpio_direction_input);
-
-int au1xxx_gpio_direction_output(unsigned gpio, int value)
+int __init au1000_gpio_init(void)
{
- if (gpio >= AU1XXX_GPIO_BASE)
-#if defined(CONFIG_SOC_AU1000)
- return -ENODEV;
-#else
- return au1xxx_gpio2_direction_output(gpio, value);
+ gpiochip_add(&au1000_gpio_chip[0].chip);
+#if !defined(CONFIG_SOC_AU1000)
+ gpiochip_add(&au1000_gpio_chip[1].chip);
#endif
- return au1xxx_gpio1_direction_output(gpio, value);
+ return 0;
}
-EXPORT_SYMBOL(au1xxx_gpio_direction_output);
+arch_initcall(au1000_gpio_init);
--- a/arch/mips/include/asm/mach-au1x00/gpio.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio.h
@@ -1,69 +1,21 @@
#ifndef _AU1XXX_GPIO_H_
#define _AU1XXX_GPIO_H_
-#include <linux/types.h>
-
#define AU1XXX_GPIO_BASE 200
-struct au1x00_gpio2 {
- u32 dir;
- u32 reserved;
- u32 output;
- u32 pinstate;
- u32 inten;
- u32 enable;
-};
-
-extern int au1xxx_gpio_get_value(unsigned gpio);
-extern void au1xxx_gpio_set_value(unsigned gpio, int value);
-extern int au1xxx_gpio_direction_input(unsigned gpio);
-extern int au1xxx_gpio_direction_output(unsigned gpio, int value);
-
-
-/* Wrappers for the arch-neutral GPIO API */
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
- /* Not yet implemented */
- return 0;
-}
-
-static inline void gpio_free(unsigned gpio)
-{
- /* Not yet implemented */
-}
-
-static inline int gpio_direction_input(unsigned gpio)
-{
- return au1xxx_gpio_direction_input(gpio);
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
- return au1xxx_gpio_direction_output(gpio, value);
-}
-
-static inline int gpio_get_value(unsigned gpio)
-{
- return au1xxx_gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
- au1xxx_gpio_set_value(gpio, value);
-}
-
-static inline int gpio_to_irq(unsigned gpio)
-{
- return gpio;
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
- return irq;
-}
+#define AU1000_GPIO2_DIR 0x00
+#define AU1000_GPIO2_RSVD 0x04
+#define AU1000_GPIO2_OUT 0x08
+#define AU1000_GPIO2_ST 0x0C
+#define AU1000_GPIO2_INT 0x10
+#define AU1000_GPIO2_EN 0x14
+
+#define gpio_get_value __gpio_get_value
+#define gpio_set_value __gpio_set_value
+
+#define gpio_to_irq(gpio) NULL
+#define irq_to_gpio(irq) NULL
-/* For cansleep */
#include <asm-generic/gpio.h>
#endif /* _AU1XXX_GPIO_H_ */
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