41 lines
1.4 KiB
Diff
41 lines
1.4 KiB
Diff
From 0566b74f93eaf6b2281d2605a63e06e6ba809334 Mon Sep 17 00:00:00 2001
|
|
From: Chen-Yu Tsai <wens@csie.org>
|
|
Date: Mon, 3 Feb 2014 09:51:40 +0800
|
|
Subject: [PATCH] clk: sunxi: get divs parent clock name from parent factor
|
|
clock
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
Divs clocks consist of a parent factor clock with multiple outputs,
|
|
and seperate clocks for each output. Get the name of the parent
|
|
clock from the parent factor clock, instead of the DT node name.
|
|
|
|
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
|
|
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
|
Acked-by: Mike Turquette <mturquette@linaro.org>
|
|
Signed-off-by: Emilio López <emilio@elopez.com.ar>
|
|
---
|
|
drivers/clk/sunxi/clk-sunxi.c | 3 ++-
|
|
1 file changed, 2 insertions(+), 1 deletion(-)
|
|
|
|
--- a/drivers/clk/sunxi/clk-sunxi.c
|
|
+++ b/drivers/clk/sunxi/clk-sunxi.c
|
|
@@ -940,7 +940,7 @@ static void __init sunxi_divs_clk_setup(
|
|
struct divs_data *data)
|
|
{
|
|
struct clk_onecell_data *clk_data;
|
|
- const char *parent = node->name;
|
|
+ const char *parent;
|
|
const char *clk_name;
|
|
struct clk **clks, *pclk;
|
|
struct clk_hw *gate_hw, *rate_hw;
|
|
@@ -954,6 +954,7 @@ static void __init sunxi_divs_clk_setup(
|
|
|
|
/* Set up factor clock that we will be dividing */
|
|
pclk = sunxi_factors_clk_setup(node, data->factors);
|
|
+ parent = __clk_get_name(pclk);
|
|
|
|
reg = of_iomap(node, 0);
|
|
|