95e0b242c2
Until a few years ago the page switch wait time was set to msleep(1) what was changed to usleep_range(1000, 2000) later. I can not imagine that a low-level operation like switching page on register level takes so much time. Most likely the value of 1ms was initially set to check whether it fixes an issue and then remained w/o further checking whether also a smaller value would be sufficient. Now the wait time is set to 5us and I successfully tested this on AR8327. IMHO 5us should be plenty of time for all supported chips. However I couldn't test this due to missing hardware. If other chips should need a longer wait time we can add the wait time as a parameter to the ar8xxx_chip struct. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@44103 3c298f89-4303-0410-b956-a3cf2f4a3e73 |
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| arch/mips/fw/myloader | ||
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