57 lines
1.6 KiB
Diff
57 lines
1.6 KiB
Diff
--- a/arch/mips/kernel/cevt-r4k.c
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+++ b/arch/mips/kernel/cevt-r4k.c
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@@ -16,6 +16,22 @@
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#include <asm/cevt-r4k.h>
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/*
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+ * Compare interrupt can be routed and latched outside the core,
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+ * so a single execution hazard barrier may not be enough to give
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+ * it time to clear as seen in the Cause register. 4 time the
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+ * pipeline depth seems reasonably conservative, and empirically
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+ * works better in configurations with high CPU/bus clock ratios.
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+ */
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+
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+#define compare_change_hazard() \
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+ do { \
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+ irq_disable_hazard(); \
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+ irq_disable_hazard(); \
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+ irq_disable_hazard(); \
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+ irq_disable_hazard(); \
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+ } while (0)
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+
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+/*
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* The SMTC Kernel for the 34K, 1004K, et. al. replaces several
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* of these routines with SMTC-specific variants.
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*/
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@@ -31,6 +47,7 @@ static int mips_next_event(unsigned long
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cnt = read_c0_count();
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cnt += delta;
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write_c0_compare(cnt);
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+ compare_change_hazard();
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res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
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return res;
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}
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@@ -100,22 +117,6 @@ static int c0_compare_int_pending(void)
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return (read_c0_cause() >> cp0_compare_irq_shift) & (1ul << CAUSEB_IP);
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}
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-/*
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- * Compare interrupt can be routed and latched outside the core,
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- * so a single execution hazard barrier may not be enough to give
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- * it time to clear as seen in the Cause register. 4 time the
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- * pipeline depth seems reasonably conservative, and empirically
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- * works better in configurations with high CPU/bus clock ratios.
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- */
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-
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-#define compare_change_hazard() \
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- do { \
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- irq_disable_hazard(); \
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- irq_disable_hazard(); \
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- irq_disable_hazard(); \
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- irq_disable_hazard(); \
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- } while (0)
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-
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int c0_compare_int_usable(void)
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{
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unsigned int delta;
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