119 lines
3.6 KiB
Diff
119 lines
3.6 KiB
Diff
From 23493b47d8caaa59b18627a01bf443c3b50bb530 Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jogo@openwrt.org>
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Date: Fri, 26 Apr 2013 12:06:03 +0200
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Subject: [PATCH 10/10] MIPS: BCM63XX: allow setting affinity for IPIC
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Wire up the set_affinity call for the internal PIC if booting on
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a cpu supporting it.
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Affinity is kept to boot cpu as default.
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Signed-off-by: Jonas Gorski <jogo@openwrt.org>
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---
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arch/mips/bcm63xx/irq.c | 46 ++++++++++++++++++++++++++++++++++++++++------
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1 file changed, 40 insertions(+), 6 deletions(-)
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--- a/arch/mips/bcm63xx/irq.c
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+++ b/arch/mips/bcm63xx/irq.c
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@@ -32,7 +32,7 @@ static unsigned int ext_irq_count;
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static unsigned int ext_irq_start, ext_irq_end;
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static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
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static void (*internal_irq_mask)(struct irq_data *d);
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-static void (*internal_irq_unmask)(struct irq_data *d);
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+static void (*internal_irq_unmask)(struct irq_data *d, const struct cpumask *m);
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static inline u32 get_ext_irq_perf_reg(int irq)
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@@ -51,6 +51,20 @@ static inline void handle_internal(int i
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do_IRQ(intbit + IRQ_INTERNAL_BASE);
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}
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+static inline int enable_irq_for_cpu(int cpu, struct irq_data *d,
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+ const struct cpumask *m)
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+{
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+ bool enable = cpu_online(cpu);
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+
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+#ifdef CONFIG_SMP
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+ if (m)
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+ enable &= cpu_isset(cpu, *m);
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+ else if (irqd_affinity_was_set(d))
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+ enable &= cpu_isset(cpu, *d->affinity);
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+#endif
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+ return enable;
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+}
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+
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/*
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* dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
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* prioritize any interrupt relatively to another. the static counter
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@@ -117,7 +131,8 @@ static void __internal_irq_mask_##width(
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spin_unlock_irqrestore(&ipic_lock, flags); \
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} \
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\
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-static void __internal_irq_unmask_##width(struct irq_data *d) \
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+static void __internal_irq_unmask_##width(struct irq_data *d, \
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+ const struct cpumask *m) \
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{ \
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u32 val; \
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unsigned irq = d->irq - IRQ_INTERNAL_BASE; \
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@@ -132,7 +147,7 @@ static void __internal_irq_unmask_##widt
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break; \
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\
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val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\
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- if (cpu_online(cpu)) \
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+ if (enable_irq_for_cpu(cpu, d, m)) \
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val |= (1 << bit); \
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else \
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val &= ~(1 << bit); \
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@@ -189,7 +204,7 @@ static void bcm63xx_internal_irq_mask(st
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static void bcm63xx_internal_irq_unmask(struct irq_data *d)
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{
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- internal_irq_unmask(d);
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+ internal_irq_unmask(d, NULL);
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}
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/*
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@@ -237,7 +252,8 @@ static void bcm63xx_external_irq_unmask(
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spin_unlock_irqrestore(&epic_lock, flags);
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if (is_ext_irq_cascaded)
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- internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start));
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+ internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start),
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+ NULL);
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}
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static void bcm63xx_external_irq_clear(struct irq_data *d)
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@@ -356,6 +372,18 @@ static int bcm63xx_external_irq_set_type
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return IRQ_SET_MASK_OK_NOCOPY;
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}
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+#ifdef CONFIG_SMP
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+static int bcm63xx_internal_set_affinity(struct irq_data *data,
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+ const struct cpumask *dest,
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+ bool force)
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+{
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+ if (!irqd_irq_disabled(data))
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+ internal_irq_unmask(data, dest);
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+
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+ return 0;
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+}
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+#endif
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+
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static struct irq_chip bcm63xx_internal_irq_chip = {
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.name = "bcm63xx_ipic",
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.irq_mask = bcm63xx_internal_irq_mask,
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@@ -523,7 +551,13 @@ void __init arch_init_irq(void)
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setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
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#ifdef CONFIG_SMP
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- if (is_ext_irq_cascaded)
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+ if (is_ext_irq_cascaded) {
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setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action);
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+ bcm63xx_internal_irq_chip.irq_set_affinity =
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+ bcm63xx_internal_set_affinity;
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+
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+ cpumask_clear(irq_default_affinity);
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+ cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
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+ }
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#endif
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}
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