147 lines
3.3 KiB
C
147 lines
3.3 KiB
C
#include <linux/irqdomain.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include "irqchip.h"
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struct rps_chip_data {
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void __iomem *base;
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struct irq_chip chip;
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struct irq_domain *domain;
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} rps_data;
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enum {
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RPS_IRQ_BASE = 64,
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RPS_IRQ_COUNT = 32,
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PRS_HWIRQ_BASE = 0,
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RPS_STATUS = 0,
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RPS_RAW_STATUS = 4,
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RPS_UNMASK = 8,
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RPS_MASK = 0xc,
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};
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/*
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* Routines to acknowledge, disable and enable interrupts
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*/
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static void rps_mask_irq(struct irq_data *d)
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{
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struct rps_chip_data *chip_data = irq_data_get_irq_chip_data(d);
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u32 mask = BIT(d->hwirq);
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iowrite32(mask, chip_data->base + RPS_MASK);
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}
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static void rps_unmask_irq(struct irq_data *d)
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{
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struct rps_chip_data *chip_data = irq_data_get_irq_chip_data(d);
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u32 mask = BIT(d->hwirq);
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iowrite32(mask, chip_data->base + RPS_UNMASK);
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}
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static struct irq_chip rps_chip = {
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.name = "RPS",
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.irq_mask = rps_mask_irq,
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.irq_unmask = rps_unmask_irq,
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};
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static int rps_irq_domain_xlate(struct irq_domain *d,
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struct device_node *controller,
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const u32 *intspec, unsigned int intsize,
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unsigned long *out_hwirq,
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unsigned int *out_type)
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{
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if (d->of_node != controller)
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return -EINVAL;
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if (intsize < 1)
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return -EINVAL;
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*out_hwirq = intspec[0];
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/* Honestly I do not know the type */
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*out_type = IRQ_TYPE_LEVEL_HIGH;
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return 0;
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}
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static int rps_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(irq, &rps_chip, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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irq_set_chip_data(irq, d->host_data);
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return 0;
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}
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const struct irq_domain_ops rps_irq_domain_ops = {
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.map = rps_irq_domain_map,
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.xlate = rps_irq_domain_xlate,
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};
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static void rps_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
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{
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struct rps_chip_data *chip_data = irq_get_handler_data(irq);
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struct irq_chip *chip = irq_get_chip(irq);
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unsigned int cascade_irq, rps_irq;
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u32 status;
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chained_irq_enter(chip, desc);
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status = ioread32(chip_data->base + RPS_STATUS);
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rps_irq = __ffs(status);
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cascade_irq = irq_find_mapping(chip_data->domain, rps_irq);
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if (unlikely(rps_irq >= RPS_IRQ_COUNT))
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handle_bad_irq(cascade_irq, desc);
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else
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generic_handle_irq(cascade_irq);
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chained_irq_exit(chip, desc);
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}
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#ifdef CONFIG_OF
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int __init rps_of_init(struct device_node *node, struct device_node *parent)
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{
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void __iomem *rps_base;
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int irq_start = RPS_IRQ_BASE;
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int irq_base;
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int irq;
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if (WARN_ON(!node))
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return -ENODEV;
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rps_base = of_iomap(node, 0);
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WARN(!rps_base, "unable to map rps registers\n");
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rps_data.base = rps_base;
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irq_base = irq_alloc_descs(irq_start, 0, RPS_IRQ_COUNT, numa_node_id());
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if (IS_ERR_VALUE(irq_base)) {
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WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
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irq_start);
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irq_base = irq_start;
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}
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rps_data.domain = irq_domain_add_legacy(node, RPS_IRQ_COUNT, irq_base,
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PRS_HWIRQ_BASE, &rps_irq_domain_ops, &rps_data);
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if (WARN_ON(!rps_data.domain))
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return -ENOMEM;
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if (parent) {
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irq = irq_of_parse_and_map(node, 0);
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if (irq_set_handler_data(irq, &rps_data) != 0)
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BUG();
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irq_set_chained_handler(irq, rps_handle_cascade_irq);
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}
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return 0;
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}
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IRQCHIP_DECLARE(nas782x, "plxtech,nas782x-rps", rps_of_init);
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#endif
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