323 lines
9.3 KiB
Diff
323 lines
9.3 KiB
Diff
From e2303161c93a90b966679b84c18838398b847d2c Mon Sep 17 00:00:00 2001
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From: Andrzej Zaborowski <balrog@zabor.org>
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Date: Wed, 2 Jul 2008 22:44:22 +0100
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Subject: [PATCH] From 119f4e02ba81cffe4dbc88d8ff667048ad28d925 Mon Sep 17 00:00:00 2001
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Subject: [PATCH] Hacky CONFIG_NO_IDLE_HZ (dyn-tick) support for S3C24xx.
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---
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arch/arm/plat-s3c24xx/time.c | 247 +++++++++++++++++++++++++++++++++++-------
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1 files changed, 209 insertions(+), 38 deletions(-)
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diff --git a/arch/arm/plat-s3c24xx/time.c b/arch/arm/plat-s3c24xx/time.c
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index 39fc33d..42d7111 100644
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--- a/arch/arm/plat-s3c24xx/time.c
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+++ b/arch/arm/plat-s3c24xx/time.c
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@@ -3,6 +3,8 @@
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* Copyright (C) 2003-2005 Simtec Electronics
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* Ben Dooks, <ben@simtec.co.uk>
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*
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+ * dyn_tick support by Andrzej Zaborowski based on omap_dyn_tick_timer.
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+ *
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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@@ -44,6 +46,9 @@ static unsigned long timer_startval;
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static unsigned long timer_usec_ticks;
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static struct work_struct resume_work;
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+unsigned long pclk;
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+struct clk *clk;
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+
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#define TIMER_USEC_SHIFT 16
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/* we use the shifted arithmetic to work out the ratio of timer ticks
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@@ -180,11 +185,7 @@ static void s3c2410_timer_setup (void)
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tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
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tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
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} else {
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- unsigned long pclk;
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- struct clk *clk;
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-
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- /* for the h1940 (and others), we use the pclk from the core
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- * to generate the timer values. since values around 50 to
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+ /* since values around 50 to
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* 70MHz are not values we can directly generate the timer
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* value from, we need to pre-scale and divide before using it.
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*
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@@ -192,20 +193,7 @@ static void s3c2410_timer_setup (void)
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* (8.45 ticks per usec)
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*/
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- /* this is used as default if no other timer can be found */
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-
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- clk = clk_get(NULL, "timers");
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- if (IS_ERR(clk))
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- panic("failed to get clock for system timer");
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-
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- clk_enable(clk);
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-
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- pclk = clk_get_rate(clk);
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-
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- printk("pclk = %lu\n", pclk);
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-
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/* configure clock tick */
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-
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timer_usec_ticks = timer_mask_usec_ticks(6, pclk);
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printk("timer_usec_ticks = %lu\n", timer_usec_ticks);
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@@ -216,11 +204,6 @@ static void s3c2410_timer_setup (void)
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tcfg0 |= ((6 - 1) / 2) << S3C2410_TCFG_PRESCALER1_SHIFT;
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tcnt = (pclk / 6) / HZ;
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-
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- /* start the timer running */
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- tcon |= S3C2410_TCON_T4START | S3C2410_TCON_T4RELOAD;
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- tcon &= ~S3C2410_TCON_T4MANUALUPD;
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- __raw_writel(tcon, S3C2410_TCON);
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}
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/* timers reload after counting zero, so reduce the count by 1 */
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@@ -262,27 +245,37 @@ static void s3c2410_timer_setup (void)
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}
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+struct sys_timer s3c24xx_timer;
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static void timer_resume_work(struct work_struct *work)
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{
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- s3c2410_timer_setup();
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-}
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-
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-/* ooh a nasty situation arises if we try to call s3c2410_timer_setup() from
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- * the resume handler. It is called in atomic context but the clock APIs
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- * try to lock a mutex which may sleep. We are in a bit of an unusual
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- * situation because we don't have a tick source right now, but it should be
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- * okay to try to schedule a work item... hopefully
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- */
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-
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-static void s3c2410_timer_resume_atomic(void)
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-{
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- int ret = schedule_work(&resume_work);
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- if (!ret)
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- printk(KERN_INFO"Failed to schedule_work tick ctr (%d)\n", ret);
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+ clk_enable(clk);
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+
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+#ifdef CONFIG_NO_IDLE_HZ
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+ if (s3c24xx_timer.dyn_tick->state & DYN_TICK_ENABLED)
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+ s3c24xx_timer.dyn_tick->enable();
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+ else
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+#endif
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+ s3c2410_timer_setup();
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}
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static void __init s3c2410_timer_init (void)
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{
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+ if (!use_tclk1_12()) {
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+ /* for the h1940 (and others), we use the pclk from the core
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+ * to generate the timer values.
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+ */
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+
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+ /* this is used as default if no other timer can be found */
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+ clk = clk_get(NULL, "timers");
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+ if (IS_ERR(clk))
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+ panic("failed to get clock for system timer");
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+
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+ clk_enable(clk);
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+
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+ pclk = clk_get_rate(clk);
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+ printk("pclk = %lu\n", pclk);
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+ }
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+
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INIT_WORK(&resume_work, timer_resume_work);
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s3c2410_timer_setup();
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setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
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@@ -304,8 +297,186 @@ static void s3c2410_timer_resume(void)
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"s3c2410_timer_resume_work already queued ???\n");
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}
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+#ifdef CONFIG_NO_IDLE_HZ
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+/*
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+ * We'll set a constant prescaler so we don't have to bother setting it
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+ * when reprogramming and so that we avoid costly divisions.
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+ *
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+ * (2 * HZ) << INPUT_FREQ_SHIFT is the desired frequency after prescaler.
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+ * At HZ == 200, HZ * 1024 should work for PCLKs of up to ~53.5 MHz.
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+ */
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+#define INPUT_FREQ_SHIFT 9
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+
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+static int ticks_last;
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+static int ticks_left;
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+static uint32_t tcnto_last;
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+
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+static inline int s3c24xx_timer_read(void)
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+{
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+ uint32_t tcnto = __raw_readl(S3C2410_TCNTO(4));
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+
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+ /*
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+ * WARNING: sometimes we get called before TCNTB has been
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+ * loaded into the counter and TCNTO then returns its previous
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+ * value and kill us, so don't do anything before counter is
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+ * reloaded.
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+ */
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+ if (unlikely(tcnto == tcnto_last))
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+ return ticks_last;
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+
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+ tcnto_last = -1;
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+ return tcnto <<
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+ ((__raw_readl(S3C2410_TCFG1) >> S3C2410_TCFG1_MUX4_SHIFT) & 3);
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+}
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+
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+static inline void s3c24xx_timer_program(int ticks)
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+{
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+ uint32_t tcon = __raw_readl(S3C2410_TCON) & ~(7 << 20);
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+ uint32_t tcfg1 = __raw_readl(S3C2410_TCFG1) & ~S3C2410_TCFG1_MUX4_MASK;
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+
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+ /* Just make sure the timer is stopped. */
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+ __raw_writel(tcon, S3C2410_TCON);
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+
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+ /* TODO: add likely()ies / unlikely()ies */
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+ if (ticks >> 18) {
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+ ticks_last = min(ticks, 0xffff << 3);
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+ ticks_left = ticks - ticks_last;
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+ __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV16, S3C2410_TCFG1);
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+ __raw_writel(ticks_last >> 3, S3C2410_TCNTB(4));
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+ } else if (ticks >> 17) {
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+ ticks_last = ticks;
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+ ticks_left = 0;
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+ __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV8, S3C2410_TCFG1);
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+ __raw_writel(ticks_last >> 2, S3C2410_TCNTB(4));
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+ } else if (ticks >> 16) {
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+ ticks_last = ticks;
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+ ticks_left = 0;
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+ __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV4, S3C2410_TCFG1);
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+ __raw_writel(ticks_last >> 1, S3C2410_TCNTB(4));
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+ } else {
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+ ticks_last = ticks;
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+ ticks_left = 0;
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+ __raw_writel(tcfg1 | S3C2410_TCFG1_MUX4_DIV2, S3C2410_TCFG1);
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+ __raw_writel(ticks_last >> 0, S3C2410_TCNTB(4));
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+ }
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+
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+ tcnto_last = __raw_readl(S3C2410_TCNTO(4));
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+ __raw_writel(tcon | S3C2410_TCON_T4MANUALUPD,
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+ S3C2410_TCON);
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+ __raw_writel(tcon | S3C2410_TCON_T4START,
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+ S3C2410_TCON);
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+}
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+
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+/*
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+ * If we have already waited all the time we were supposed to wait,
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+ * kick the timer, setting the longest allowed timeout value just
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+ * for time-keeping.
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+ */
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+static inline void s3c24xx_timer_program_idle(void)
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+{
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+ s3c24xx_timer_program(0xffff << 3);
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+}
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+
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+static inline void s3c24xx_timer_update(int restart)
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+{
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+ int ticks_cur = s3c24xx_timer_read();
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+ int jiffies_elapsed = (ticks_last - ticks_cur) >> INPUT_FREQ_SHIFT;
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+ int subjiffy = ticks_last - (jiffies_elapsed << INPUT_FREQ_SHIFT);
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+
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+ if (restart) {
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+ if (ticks_left >= (1 << INPUT_FREQ_SHIFT))
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+ s3c24xx_timer_program(ticks_left);
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+ else
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+ s3c24xx_timer_program_idle();
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+ ticks_last += subjiffy;
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+ } else
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+ ticks_last = subjiffy;
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+
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+ while (jiffies_elapsed --)
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+ timer_tick();
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+}
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+
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+/* Called when the timer expires. */
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+static irqreturn_t s3c24xx_timer_handler(int irq, void *dev_id)
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+{
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+ tcnto_last = -1;
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+ s3c24xx_timer_update(1);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+/* Called to update jiffies with time elapsed. */
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+static irqreturn_t s3c24xx_timer_handler_dyn_tick(int irq, void *dev_id)
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+{
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+ s3c24xx_timer_update(0);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+/*
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+ * Programs the next timer interrupt needed. Called when dynamic tick is
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+ * enabled, and to reprogram the ticks to skip from pm_idle. The CPU goes
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+ * to sleep directly after this.
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+ */
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+static void s3c24xx_timer_reprogram_dyn_tick(unsigned long next_jiffies)
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+{
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+ int subjiffy_left = ticks_last - s3c24xx_timer_read();
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+
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+ s3c24xx_timer_program(max((int) next_jiffies, 1) << INPUT_FREQ_SHIFT);
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+ ticks_last += subjiffy_left;
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+}
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+
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+static unsigned long s3c24xx_timer_offset_dyn_tick(void)
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+{
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+ /* TODO */
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+ return 0;
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+}
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+
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+static int s3c24xx_timer_enable_dyn_tick(void)
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+{
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+ /* Set our constant prescaler. */
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+ uint32_t tcfg0 = __raw_readl(S3C2410_TCFG0);
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+ int prescaler =
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+ max(min(256, (int) pclk / (HZ << (INPUT_FREQ_SHIFT + 1))), 1);
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+
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+ tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
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+ tcfg0 |= (prescaler - 1) << S3C2410_TCFG_PRESCALER1_SHIFT;
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+ __raw_writel(tcfg0, S3C2410_TCFG0);
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+
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+ /* Override handlers. */
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+ s3c2410_timer_irq.handler = s3c24xx_timer_handler;
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+ s3c24xx_timer.offset = s3c24xx_timer_offset_dyn_tick;
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+
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+ printk(KERN_INFO "dyn_tick enabled on s3c24xx timer 4, "
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+ "%li Hz pclk with prescaler %i\n", pclk, prescaler);
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+
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+ s3c24xx_timer_program_idle();
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+
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+ return 0;
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+}
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+
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+static int s3c24xx_timer_disable_dyn_tick(void)
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+{
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+ s3c2410_timer_irq.handler = s3c2410_timer_interrupt;
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+ s3c24xx_timer.offset = s3c2410_gettimeoffset;
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+ s3c2410_timer_setup();
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+
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+ return 0;
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+}
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+
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+static struct dyn_tick_timer s3c24xx_dyn_tick_timer = {
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+ .enable = s3c24xx_timer_enable_dyn_tick,
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+ .disable = s3c24xx_timer_disable_dyn_tick,
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+ .reprogram = s3c24xx_timer_reprogram_dyn_tick,
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+ .handler = s3c24xx_timer_handler_dyn_tick,
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+};
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+#endif /* CONFIG_NO_IDLE_HZ */
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+
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struct sys_timer s3c24xx_timer = {
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.init = s3c2410_timer_init,
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.offset = s3c2410_gettimeoffset,
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.resume = s3c2410_timer_resume,
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+#ifdef CONFIG_NO_IDLE_HZ
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+ .dyn_tick = &s3c24xx_dyn_tick_timer,
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+#endif
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};
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--
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1.5.6.5
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