126 lines
4.1 KiB
Diff
126 lines
4.1 KiB
Diff
From 8b9de04ef3aaa154f30baf1ac703a2d3b474ad4e Mon Sep 17 00:00:00 2001
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From: Andy Gross <agross@codeaurora.org>
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Date: Thu, 12 Jun 2014 14:34:12 -0500
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Subject: [PATCH 135/182] spi: qup: Add support for v1.1.1
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This patch adds support for v1.1.1 of the SPI QUP controller.
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Signed-off-by: Andy Gross <agross@codeaurora.org>
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---
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.../devicetree/bindings/spi/qcom,spi-qup.txt | 6 +++-
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drivers/spi/spi-qup.c | 36 ++++++++++++--------
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2 files changed, 27 insertions(+), 15 deletions(-)
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--- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
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+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
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@@ -7,7 +7,11 @@ SPI in master mode supports up to 50MHz,
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data path from 4 bits to 32 bits and numerous protocol variants.
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Required properties:
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-- compatible: Should contain "qcom,spi-qup-v2.1.1" or "qcom,spi-qup-v2.2.1"
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+- compatible: Should contain:
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+ "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
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+ "qcom,spi-qup-v2.1.1" for 8974 and later
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+ "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
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+
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- reg: Should contain base register location and length
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- interrupts: Interrupt number used by this controller
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--- a/drivers/spi/spi-qup.c
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+++ b/drivers/spi/spi-qup.c
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@@ -142,6 +142,7 @@ struct spi_qup {
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int w_size; /* bytes per SPI word */
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int tx_bytes;
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int rx_bytes;
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+ int qup_v1;
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};
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@@ -420,7 +421,9 @@ static int spi_qup_io_config(struct spi_
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config |= QUP_CONFIG_SPI_MODE;
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writel_relaxed(config, controller->base + QUP_CONFIG);
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- writel_relaxed(0, controller->base + QUP_OPERATIONAL_MASK);
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+ /* only write to OPERATIONAL_MASK when register is present */
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+ if (!controller->qup_v1)
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+ writel_relaxed(0, controller->base + QUP_OPERATIONAL_MASK);
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return 0;
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}
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@@ -486,7 +489,7 @@ static int spi_qup_probe(struct platform
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struct resource *res;
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struct device *dev;
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void __iomem *base;
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- u32 data, max_freq, iomode;
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+ u32 max_freq, iomode;
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int ret, irq, size;
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dev = &pdev->dev;
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@@ -529,15 +532,6 @@ static int spi_qup_probe(struct platform
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return ret;
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}
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- data = readl_relaxed(base + QUP_HW_VERSION);
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-
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- if (data < QUP_HW_VERSION_2_1_1) {
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- clk_disable_unprepare(cclk);
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- clk_disable_unprepare(iclk);
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- dev_err(dev, "v.%08x is not supported\n", data);
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- return -ENXIO;
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- }
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-
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master = spi_alloc_master(dev, sizeof(struct spi_qup));
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if (!master) {
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clk_disable_unprepare(cclk);
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@@ -570,6 +564,10 @@ static int spi_qup_probe(struct platform
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controller->cclk = cclk;
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controller->irq = irq;
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+ /* set v1 flag if device is version 1 */
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+ if (of_device_is_compatible(dev->of_node, "qcom,spi-qup-v1.1.1"))
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+ controller->qup_v1 = 1;
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+
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spin_lock_init(&controller->lock);
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init_completion(&controller->done);
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@@ -593,8 +591,8 @@ static int spi_qup_probe(struct platform
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size = QUP_IO_M_INPUT_FIFO_SIZE(iomode);
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controller->in_fifo_sz = controller->in_blk_sz * (2 << size);
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- dev_info(dev, "v.%08x IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
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- data, controller->in_blk_sz, controller->in_fifo_sz,
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+ dev_info(dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
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+ controller->in_blk_sz, controller->in_fifo_sz,
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controller->out_blk_sz, controller->out_fifo_sz);
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writel_relaxed(1, base + QUP_SW_RESET);
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@@ -607,10 +605,19 @@ static int spi_qup_probe(struct platform
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writel_relaxed(0, base + QUP_OPERATIONAL);
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writel_relaxed(0, base + QUP_IO_M_MODES);
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- writel_relaxed(0, base + QUP_OPERATIONAL_MASK);
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+
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+ if (!controller->qup_v1)
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+ writel_relaxed(0, base + QUP_OPERATIONAL_MASK);
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+
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writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN,
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base + SPI_ERROR_FLAGS_EN);
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+ /* if earlier version of the QUP, disable INPUT_OVERRUN */
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+ if (controller->qup_v1)
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+ writel_relaxed(QUP_ERROR_OUTPUT_OVER_RUN |
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+ QUP_ERROR_INPUT_UNDER_RUN | QUP_ERROR_OUTPUT_UNDER_RUN,
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+ base + QUP_ERROR_FLAGS_EN);
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+
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writel_relaxed(0, base + SPI_CONFIG);
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writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL);
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@@ -732,6 +739,7 @@ static int spi_qup_remove(struct platfor
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}
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static struct of_device_id spi_qup_dt_match[] = {
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+ { .compatible = "qcom,spi-qup-v1.1.1", },
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{ .compatible = "qcom,spi-qup-v2.1.1", },
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{ .compatible = "qcom,spi-qup-v2.2.1", },
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{ }
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