90 lines
3.0 KiB
Diff
90 lines
3.0 KiB
Diff
--- a/drivers/net/wireless/ath/ath5k/desc.c
|
|
+++ b/drivers/net/wireless/ath/ath5k/desc.c
|
|
@@ -184,6 +184,7 @@ static int ath5k_hw_setup_4word_tx_desc(
|
|
{
|
|
struct ath5k_hw_4w_tx_ctl *tx_ctl;
|
|
unsigned int frame_len;
|
|
+ u32 txctl0 = 0, txctl1 = 0, txctl2 = 0, txctl3 = 0;
|
|
|
|
tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
|
|
|
|
@@ -209,7 +210,8 @@ static int ath5k_hw_setup_4word_tx_desc(
|
|
tx_power = AR5K_TUNE_MAX_TXPOWER;
|
|
|
|
/* Clear descriptor */
|
|
- memset(&desc->ud.ds_tx5212, 0, sizeof(struct ath5k_hw_5212_tx_desc));
|
|
+ memset(&desc->ud.ds_tx5212.tx_stat, 0,
|
|
+ sizeof(desc->ud.ds_tx5212.tx_stat));
|
|
|
|
/* Setup control descriptor */
|
|
|
|
@@ -221,7 +223,7 @@ static int ath5k_hw_setup_4word_tx_desc(
|
|
if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
|
|
return -EINVAL;
|
|
|
|
- tx_ctl->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
|
|
+ txctl0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
|
|
|
|
/* Verify and set buffer length */
|
|
|
|
@@ -232,21 +234,17 @@ static int ath5k_hw_setup_4word_tx_desc(
|
|
if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
|
|
return -EINVAL;
|
|
|
|
- tx_ctl->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
|
|
+ txctl1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
|
|
|
|
- tx_ctl->tx_control_0 |=
|
|
- AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
|
|
- AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
|
|
- tx_ctl->tx_control_1 |= AR5K_REG_SM(type,
|
|
- AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
|
|
- tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0,
|
|
- AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
|
|
- tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
|
|
+ txctl0 |= AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
|
|
+ AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
|
|
+ txctl1 |= AR5K_REG_SM(type, AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
|
|
+ txctl2 = AR5K_REG_SM(tx_tries0, AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
|
|
+ txctl3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
|
|
|
|
#define _TX_FLAGS(_c, _flag) \
|
|
if (flags & AR5K_TXDESC_##_flag) { \
|
|
- tx_ctl->tx_control_##_c |= \
|
|
- AR5K_4W_TX_DESC_CTL##_c##_##_flag; \
|
|
+ txctl##_c |= AR5K_4W_TX_DESC_CTL##_c##_##_flag; \
|
|
}
|
|
|
|
_TX_FLAGS(0, CLRDMASK);
|
|
@@ -262,8 +260,8 @@ static int ath5k_hw_setup_4word_tx_desc(
|
|
* WEP crap
|
|
*/
|
|
if (key_index != AR5K_TXKEYIX_INVALID) {
|
|
- tx_ctl->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
|
|
- tx_ctl->tx_control_1 |= AR5K_REG_SM(key_index,
|
|
+ txctl0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
|
|
+ txctl1 |= AR5K_REG_SM(key_index,
|
|
AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_IDX);
|
|
}
|
|
|
|
@@ -274,12 +272,16 @@ static int ath5k_hw_setup_4word_tx_desc(
|
|
if ((flags & AR5K_TXDESC_RTSENA) &&
|
|
(flags & AR5K_TXDESC_CTSENA))
|
|
return -EINVAL;
|
|
- tx_ctl->tx_control_2 |= rtscts_duration &
|
|
- AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
|
|
- tx_ctl->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
|
|
+ txctl2 |= rtscts_duration & AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
|
|
+ txctl3 |= AR5K_REG_SM(rtscts_rate,
|
|
AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
|
|
}
|
|
|
|
+ tx_ctl->tx_control_0 = txctl0;
|
|
+ tx_ctl->tx_control_1 = txctl1;
|
|
+ tx_ctl->tx_control_2 = txctl2;
|
|
+ tx_ctl->tx_control_3 = txctl3;
|
|
+
|
|
return 0;
|
|
}
|
|
|