This will allow adding more modes without options conflict.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45443 3c298f89-4303-0410-b956-a3cf2f4a3e73
adds support for reading md5 sums of files
Signed-off-by: John Crispin <blogic@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45442 3c298f89-4303-0410-b956-a3cf2f4a3e73
fixes long writes when using polarssl
Signed-off-by: John Crispin <blogic@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45441 3c298f89-4303-0410-b956-a3cf2f4a3e73
fixes issues with semi-initialized overlay partitions during firstboot
Signed-off-by: John Crispin <blogic@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45440 3c298f89-4303-0410-b956-a3cf2f4a3e73
Open-Mesh OM5P-AN use a AT8035 (F1E) behind one of the ethernet ports. This PHY
requires special flags to work correctly. Otherwise massive packet loss happens
with active POE or when switching the link speed from gigabit ethernet to fast
ethernet. The generic PHY doesn't have support to change these settings.
Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45439 3c298f89-4303-0410-b956-a3cf2f4a3e73
The OM5P-AN boards are suffering from ethernet packet loss when booting with
some active POE setups or when switching to Fast Ethernet when previously
booted with Gigabit ethernet attached.
The cause of the problem is that the AR8035 PHYs requires special register
settings to work reliably on these boards. Enable the RGMII TX, RX delays and
disable SmartEE functionality of the AR8035 PHYs. Also enable the RXD and RDV
delay in the ETH_CFG register to fix the issue.
Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45438 3c298f89-4303-0410-b956-a3cf2f4a3e73
it has been non-functional for years and caused numerous memleaks and
crashes for people that tried to enable it.
it has no maintained upstream source, and it does not look like it's
going to be fixed any time soon
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45423 3c298f89-4303-0410-b956-a3cf2f4a3e73
If you can't find the firmware for you board, send proper patches.
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45413 3c298f89-4303-0410-b956-a3cf2f4a3e73
This has been done without having a board, but should work.
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45412 3c298f89-4303-0410-b956-a3cf2f4a3e73
left "broken" as I'm not sure if my only board is to blame.. testers welcomed
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45406 3c298f89-4303-0410-b956-a3cf2f4a3e73
To prevent future confusion around '/overlay' vs. 'overlay' simply reject
relative path specifications as mount points since such paths result in
undefined behaviour anyway.
Signed-off-by: Jo-Philipp Wich <jow@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45404 3c298f89-4303-0410-b956-a3cf2f4a3e73
It seems to have few ports connected to CPU (only for CPU sending data?)
as part of "SMP dual core 3 GMAC setup" feature.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45403 3c298f89-4303-0410-b956-a3cf2f4a3e73
On BCM5301X there are two different cases to handle: CPU port 8 vs. any
other one. Support for CPU port 8 was already partially implemented but
it lacked setting some extra bit for 2G speed. It also will need to be
extended to implement "SMP dual core 3 GMAC setup". That's the reason
for handling it in separated code block.
This patch also adds overriding CPU port state for port other than 8. It
requires using recently defined GMII_PORT registers.
It was tested for regressions on BCM53011 revs 2 & 3. It was also
confirmed to fix switch on some internal Broadcom board.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Jonas Gorski <jogo@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@45402 3c298f89-4303-0410-b956-a3cf2f4a3e73
Felix Fietkau
Rafał Miłecki
John Crispin
Steven Barth
Imre Kaloz
Luka Perkov
Jo-Philipp Wich