[PATCH 1/2] Add support for the ar8316 switch.
This patch enhances the ar8216 driver with ar8316 support and fixes some minor issues with the ar8216 driver itself. It should not break anything, but isn't tested on ar8216 devices. [PATCH 2/2] ar71xx: Add the ar8316 driver to rs pro/rb-450g. Add the ar8216 driver to the ar71xx target, and add network configurations for the RouterStation Pro and the RouterBoard RB-450G. git-svn-id: svn://svn.openwrt.org/openwrt/trunk@20722 3c298f89-4303-0410-b956-a3cf2f4a3e73master
Jo-Philipp Wich
parent
9e277d3878
commit
fd27f8a1d9
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@ -0,0 +1,26 @@
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config interface loopback
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option ifname lo
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option proto static
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option ipaddr 127.0.0.1
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option netmask 255.0.0.0
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config interface lan
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option ifname eth1
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option type bridge
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option proto static
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option ipaddr 192.168.1.1
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option netmask 255.255.255.0
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config interface wan
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option ifname eth0
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option proto dhcp
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config switch
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option name eth1
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option reset 1
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option enable_vlan 1
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config switch_vlan
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option device eth1
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option vlan 1
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option ports "0 1 2 3 4"
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@ -14,3 +14,13 @@ config interface lan
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config interface wan
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option ifname eth0
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option proto dhcp
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config switch
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option name eth1
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option reset 1
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option enable_vlan 1
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config switch_vlan
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option device eth1
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option vlan 1
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option ports "0 1 2 3 4"
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@ -44,6 +44,7 @@ CONFIG_AR71XX_MACH_WRT400N=y
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CONFIG_AR71XX_MACH_WZR_HP_G300NH=y
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CONFIG_AR71XX_NVRAM=y
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CONFIG_AR71XX_WDT=y
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CONFIG_AR8216_PHY=y
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# CONFIG_ARCH_HAS_ILOG2_U32 is not set
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# CONFIG_ARCH_HAS_ILOG2_U64 is not set
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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@ -44,6 +44,7 @@ CONFIG_AR71XX_MACH_WRT400N=y
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CONFIG_AR71XX_MACH_WZR_HP_G300NH=y
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CONFIG_AR71XX_NVRAM=y
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CONFIG_AR71XX_WDT=y
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CONFIG_AR8216_PHY=y
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# CONFIG_ARCH_HAS_ILOG2_U32 is not set
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# CONFIG_ARCH_HAS_ILOG2_U64 is not set
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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@ -43,6 +43,7 @@ CONFIG_AR71XX_MACH_WRT400N=y
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CONFIG_AR71XX_MACH_WZR_HP_G300NH=y
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CONFIG_AR71XX_NVRAM=y
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CONFIG_AR71XX_WDT=y
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CONFIG_AR8216_PHY=y
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# CONFIG_ARCH_HAS_ILOG2_U32 is not set
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# CONFIG_ARCH_HAS_ILOG2_U64 is not set
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CONFIG_ARCH_HIBERNATION_POSSIBLE=y
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@ -239,6 +239,7 @@ static void __init rb450_generic_setup(int gige)
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ar71xx_add_device_mdio(0xffffffe0);
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ar71xx_eth0_data.phy_if_mode = (gige) ? PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII;
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ar71xx_eth0_data.phy_mask = (gige) ? (1 << 0) : 0;
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ar71xx_eth0_data.speed = (gige) ? SPEED_1000 : SPEED_100;
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ar71xx_eth0_data.duplex = DUPLEX_FULL;
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@ -177,6 +177,7 @@ static void __init ubnt_rspro_setup(void)
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ar71xx_eth0_data.phy_mask = UBNT_RSPRO_WAN_PHYMASK;
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ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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ar71xx_eth1_data.phy_mask = UBNT_RSPRO_LAN_PHYMASK;
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ar71xx_eth1_data.speed = SPEED_1000;
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ar71xx_eth1_data.duplex = DUPLEX_FULL;
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@ -31,6 +31,8 @@
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#include <linux/etherdevice.h>
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#include "ar8216.h"
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/* size of the vlan table */
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#define AR8X16_MAX_VLANS 128
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struct ar8216_priv {
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struct switch_dev dev;
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@ -39,11 +41,13 @@ struct ar8216_priv {
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void (*write)(struct ar8216_priv *priv, int reg, u32 val);
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const struct net_device_ops *ndo_old;
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struct net_device_ops ndo;
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struct mutex reg_mutex;
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int chip;
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/* all fields below are cleared on reset */
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bool vlan;
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u16 vlan_id[AR8216_NUM_VLANS];
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u8 vlan_table[AR8216_NUM_VLANS];
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u16 vlan_id[AR8X16_MAX_VLANS];
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u8 vlan_table[AR8X16_MAX_VLANS];
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u8 vlan_tagged;
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u16 pvid[AR8216_NUM_PORTS];
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};
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@ -110,6 +114,30 @@ ar8216_rmw(struct ar8216_priv *priv, int reg, u32 mask, u32 val)
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return v;
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}
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static inline int
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ar8216_id_chip(struct ar8216_priv *priv)
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{
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u32 val;
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u16 id;
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val = ar8216_mii_read(priv, AR8216_REG_CTRL);
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id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
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switch (id) {
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case 0x0101:
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return AR8216;
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case 0x1001:
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return AR8316;
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default:
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printk(KERN_ERR
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"ar8216: Unknown Atheros device [ver=%d, rev=%d, phy_id=%04x%04x]\n",
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(int)(val >> AR8216_CTRL_VERSION_S),
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(int)(val & AR8216_CTRL_REVISION),
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priv->phy->bus->read(priv->phy->bus, priv->phy->addr, 2),
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priv->phy->bus->read(priv->phy->bus, priv->phy->addr, 3));
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return UNKNOWN;
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}
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}
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static int
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ar8216_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
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struct switch_val *val)
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@ -136,7 +164,7 @@ ar8216_set_pvid(struct switch_dev *dev, int port, int vlan)
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/* make sure no invalid PVIDs get set */
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if (vlan >= AR8216_NUM_VLANS)
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if (vlan >= dev->vlans)
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return -EINVAL;
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priv->pvid[port] = vlan;
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@ -336,7 +364,7 @@ ar8216_set_ports(struct switch_dev *dev, struct switch_val *val)
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/* make sure that an untagged port does not
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* appear in other vlans */
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for (j = 0; j < AR8216_NUM_VLANS; j++) {
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for (j = 0; j < AR8X16_MAX_VLANS; j++) {
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if (j == val->port_vlan)
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continue;
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priv->vlan_table[j] &= ~(1 << p->id);
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@ -383,6 +411,7 @@ ar8216_hw_apply(struct switch_dev *dev)
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u8 portmask[AR8216_NUM_PORTS];
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int i, j;
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mutex_lock(&priv->reg_mutex);
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/* flush all vlan translation unit entries */
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ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
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@ -390,7 +419,7 @@ ar8216_hw_apply(struct switch_dev *dev)
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if (priv->vlan) {
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/* calculate the port destination masks and load vlans
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* into the vlan translation unit */
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for (j = 0; j < AR8216_NUM_VLANS; j++) {
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for (j = 0; j < AR8X16_MAX_VLANS; j++) {
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u8 vp = priv->vlan_table[j];
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if (!vp)
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@ -446,7 +475,7 @@ ar8216_hw_apply(struct switch_dev *dev)
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AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
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AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
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AR8216_PORT_CTRL_LEARN |
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(priv->vlan && i == AR8216_PORT_CPU ?
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(priv->vlan && i == AR8216_PORT_CPU && (priv->chip == AR8216) ?
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AR8216_PORT_CTRL_HEADER : 0) |
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(egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
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(AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
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@ -458,7 +487,73 @@ ar8216_hw_apply(struct switch_dev *dev)
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(ingress << AR8216_PORT_VLAN_MODE_S) |
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(pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
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}
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mutex_unlock(&priv->reg_mutex);
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return 0;
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}
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static int
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ar8316_hw_init(struct ar8216_priv *priv) {
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static int initialized;
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int i;
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u32 val;
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struct mii_bus *bus;
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if (initialized)
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return 0;
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val = priv->read(priv, 0x8);
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if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
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/* value taken from Ubiquiti RouterStation Pro */
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if (val == 0x81461bea) {
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/* switch already intialized by bootloader */
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initialized = true;
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return 0;
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}
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priv->write(priv, 0x8, 0x81461bea);
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} else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
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/* value taken from AVM Fritz!Box 7390 sources */
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if (val == 0x010e5b71) {
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/* switch already initialized by bootloader */
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initialized = true;
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return 0;
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}
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priv->write(priv, 0x8, 0x010e5b71);
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} else {
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/* no known value for phy interface */
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printk(KERN_ERR "ar8316: unsupported mii mode: %d.\n",
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priv->phy->interface);
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return -EINVAL;
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}
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/* standard atheros magic */
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priv->write(priv, 0x38, 0xc000050e);
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/* Initialize the ports */
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bus = priv->phy->bus;
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for (i = 0; i < 5; i++) {
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if ((i == 4) &&
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priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
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/* work around for phy4 rgmii mode */
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bus->write(bus, i, MII_ATH_DBG_ADDR, 0x12);
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bus->write(bus, i, MII_ATH_DBG_DATA, 0x480c);
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/* rx delay */
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bus->write(bus, i, MII_ATH_DBG_ADDR, 0x0);
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bus->write(bus, i, MII_ATH_DBG_DATA, 0x824e);
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/* tx delay */
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bus->write(bus, i, MII_ATH_DBG_ADDR, 0x5);
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bus->write(bus, i, MII_ATH_DBG_DATA, 0x3d47);
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msleep(1000);
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}
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/* initialize the port itself */
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bus->write(bus, i, MII_ADVERTISE,
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ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
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bus->write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
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bus->write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
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msleep(1000);
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}
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initialized = true;
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return 0;
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}
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@ -468,9 +563,10 @@ ar8216_reset_switch(struct switch_dev *dev)
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struct ar8216_priv *priv = to_ar8216(dev);
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int i;
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mutex_lock(&priv->reg_mutex);
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memset(&priv->vlan, 0, sizeof(struct ar8216_priv) -
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offsetof(struct ar8216_priv, vlan));
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for (i = 0; i < AR8216_NUM_VLANS; i++) {
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for (i = 0; i < AR8X16_MAX_VLANS; i++) {
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priv->vlan_id[i] = i;
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}
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for (i = 0; i < AR8216_NUM_PORTS; i++) {
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@ -485,9 +581,12 @@ ar8216_reset_switch(struct switch_dev *dev)
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if (i == AR8216_PORT_CPU) {
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priv->write(priv, AR8216_REG_PORT_STATUS(i),
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AR8216_PORT_STATUS_LINK_UP |
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AR8216_PORT_SPEED_100M |
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((priv->chip == AR8316) ?
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AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
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AR8216_PORT_STATUS_TXMAC |
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AR8216_PORT_STATUS_RXMAC |
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((priv->chip == AR8316) ? AR8216_PORT_STATUS_RXFLOW : 0) |
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((priv->chip == AR8316) ? AR8216_PORT_STATUS_TXFLOW : 0) |
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AR8216_PORT_STATUS_DUPLEX);
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} else {
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priv->write(priv, AR8216_REG_PORT_STATUS(i),
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@ -497,9 +596,20 @@ ar8216_reset_switch(struct switch_dev *dev)
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/* XXX: undocumented magic from atheros, required! */
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priv->write(priv, 0x38, 0xc000050e);
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ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
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AR8216_GCTRL_MTU, 1518 + 8 + 2);
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if (priv->chip == AR8216) {
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ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
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AR8216_GCTRL_MTU, 1518 + 8 + 2);
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} else if (priv->chip == AR8316) {
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/* enable jumbo frames */
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ar8216_rmw(priv, AR8216_REG_GLOBAL_CTRL,
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AR8316_GCTRL_MTU, 9018 + 8 + 2);
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}
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if (priv->chip == AR8316) {
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/* enable cpu port to receive multicast and broadcast frames */
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priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
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}
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mutex_unlock(&priv->reg_mutex);
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return ar8216_hw_apply(dev);
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}
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@ -510,37 +620,74 @@ ar8216_config_init(struct phy_device *pdev)
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struct net_device *dev = pdev->attached_dev;
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int ret;
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printk("%s: AR8216 PHY driver attached.\n", pdev->attached_dev->name);
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pdev->supported = ADVERTISED_100baseT_Full;
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pdev->advertising = ADVERTISED_100baseT_Full;
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priv = kzalloc(sizeof(struct ar8216_priv), GFP_KERNEL);
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if (priv == NULL)
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return -ENOMEM;
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priv->phy = pdev;
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priv->chip = ar8216_id_chip(priv);
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printk(KERN_INFO "%s: AR%d PHY driver attached.\n",
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pdev->attached_dev->name, priv->chip);
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if (pdev->addr != 0) {
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if (priv->chip == AR8316) {
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pdev->supported |= SUPPORTED_1000baseT_Full;
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pdev->advertising |= ADVERTISED_1000baseT_Full;
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}
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kfree(priv);
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return 0;
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}
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pdev->supported = priv->chip == AR8316 ?
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SUPPORTED_1000baseT_Full : SUPPORTED_100baseT_Full;
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pdev->advertising = pdev->supported;
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mutex_init(&priv->reg_mutex);
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priv->read = ar8216_mii_read;
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priv->write = ar8216_mii_write;
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memcpy(&priv->dev, &athdev, sizeof(struct switch_dev));
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pdev->priv = priv;
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if (priv->chip == AR8316) {
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priv->dev.name = "Atheros AR8316";
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priv->dev.vlans = AR8X16_MAX_VLANS;
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/* port 5 connected to the other mac, therefore unusable */
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priv->dev.ports = (AR8216_NUM_PORTS - 1);
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}
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if ((ret = register_switch(&priv->dev, pdev->attached_dev)) < 0) {
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kfree(priv);
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goto done;
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}
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if (priv->chip == AR8316) {
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ret = ar8316_hw_init(priv);
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if (ret) {
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kfree(priv);
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goto done;
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}
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}
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ret = ar8216_reset_switch(&priv->dev);
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if (ret)
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if (ret) {
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kfree(priv);
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goto done;
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}
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dev->phy_ptr = priv;
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pdev->pkt_align = 2;
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pdev->netif_receive_skb = ar8216_netif_receive_skb;
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pdev->netif_rx = ar8216_netif_rx;
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priv->ndo_old = dev->netdev_ops;
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memcpy(&priv->ndo, priv->ndo_old, sizeof(struct net_device_ops));
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priv->ndo.ndo_start_xmit = ar8216_mangle_tx;
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dev->netdev_ops = &priv->ndo;
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/* VID fixup only needed on ar8216 */
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if (pdev->addr == 0 && priv->chip == AR8216) {
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pdev->pkt_align = 2;
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pdev->netif_receive_skb = ar8216_netif_receive_skb;
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pdev->netif_rx = ar8216_netif_rx;
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priv->ndo_old = dev->netdev_ops;
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memcpy(&priv->ndo, priv->ndo_old, sizeof(struct net_device_ops));
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priv->ndo.ndo_start_xmit = ar8216_mangle_tx;
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dev->netdev_ops = &priv->ndo;
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}
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done:
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return ret;
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@ -550,28 +697,39 @@ static int
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ar8216_read_status(struct phy_device *phydev)
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{
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struct ar8216_priv *priv = phydev->priv;
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int ret;
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if (phydev->addr != 0) {
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return genphy_read_status(phydev);
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}
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phydev->speed = SPEED_100;
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phydev->speed = priv->chip == AR8316 ? SPEED_1000 : SPEED_100;
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phydev->duplex = DUPLEX_FULL;
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phydev->link = 1;
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/* flush the address translation unit */
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if (ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0))
|
||||
return -ETIMEDOUT;
|
||||
mutex_lock(&priv->reg_mutex);
|
||||
ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
|
||||
|
||||
priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
|
||||
if (!ret)
|
||||
priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
|
||||
else
|
||||
ret = -ETIMEDOUT;
|
||||
mutex_unlock(&priv->reg_mutex);
|
||||
|
||||
phydev->state = PHY_RUNNING;
|
||||
netif_carrier_on(phydev->attached_dev);
|
||||
phydev->adjust_link(phydev->attached_dev);
|
||||
|
||||
return 0;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int
|
||||
ar8216_config_aneg(struct phy_device *phydev)
|
||||
{
|
||||
return 0;
|
||||
if (phydev->addr == 0)
|
||||
return 0;
|
||||
|
||||
return genphy_config_aneg(phydev);
|
||||
}
|
||||
|
||||
static int
|
||||
|
|
@ -579,16 +737,10 @@ ar8216_probe(struct phy_device *pdev)
|
|||
{
|
||||
struct ar8216_priv priv;
|
||||
|
||||
u8 id, rev;
|
||||
u32 val;
|
||||
|
||||
priv.phy = pdev;
|
||||
val = ar8216_mii_read(&priv, AR8216_REG_CTRL);
|
||||
rev = val & AR8216_CTRL_REVISION;
|
||||
id = (val & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
|
||||
if ((id != 1) || (rev != 1))
|
||||
if (ar8216_id_chip(&priv) == UNKNOWN) {
|
||||
return -ENODEV;
|
||||
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -603,7 +755,8 @@ ar8216_remove(struct phy_device *pdev)
|
|||
|
||||
if (priv->ndo_old && dev)
|
||||
dev->netdev_ops = priv->ndo_old;
|
||||
unregister_switch(&priv->dev);
|
||||
if (pdev->addr == 0)
|
||||
unregister_switch(&priv->dev);
|
||||
kfree(priv);
|
||||
}
|
||||
|
||||
|
|
@ -634,7 +787,9 @@ static struct switch_dev athdev = {
|
|||
};
|
||||
|
||||
static struct phy_driver ar8216_driver = {
|
||||
.name = "Atheros AR8216",
|
||||
.phy_id = 0x004d0000,
|
||||
.name = "Atheros AR8216/AR8316",
|
||||
.phy_id_mask = 0xffff0000,
|
||||
.features = PHY_BASIC_FEATURES,
|
||||
.probe = ar8216_probe,
|
||||
.remove = ar8216_remove,
|
||||
|
|
|
|||
|
|
@ -22,6 +22,11 @@
|
|||
#define AR8216_PORT_CPU 0
|
||||
#define AR8216_NUM_PORTS 6
|
||||
#define AR8216_NUM_VLANS 16
|
||||
#define AR8316_NUM_VLANS 4096
|
||||
|
||||
/* Atheros specific MII registers */
|
||||
#define MII_ATH_DBG_ADDR 0x1d
|
||||
#define MII_ATH_DBG_DATA 0x1e
|
||||
|
||||
#define AR8216_REG_CTRL 0x0000
|
||||
#define AR8216_CTRL_REVISION BITS(0, 8)
|
||||
|
|
@ -30,8 +35,13 @@
|
|||
#define AR8216_CTRL_VERSION_S 8
|
||||
#define AR8216_CTRL_RESET BIT(31)
|
||||
|
||||
#define AR8216_REG_FLOOD_MASK 0x002C
|
||||
#define AR8216_FM_UNI_DEST_PORTS BITS(0, 6)
|
||||
#define AR8216_FM_MULTI_DEST_PORTS BITS(16, 6)
|
||||
|
||||
#define AR8216_REG_GLOBAL_CTRL 0x0030
|
||||
#define AR8216_GCTRL_MTU BITS(0, 11)
|
||||
#define AR8316_GCTRL_MTU BITS(0, 14)
|
||||
|
||||
#define AR8216_REG_VTU 0x0040
|
||||
#define AR8216_VTU_OP BITS(0, 3)
|
||||
|
|
@ -75,6 +85,11 @@
|
|||
#define AR8216_ATU_ADDR1 BITS(16, 8)
|
||||
#define AR8216_ATU_ADDR0 BITS(24, 8)
|
||||
|
||||
#define AR8216_REG_ATU_CTRL 0x005C
|
||||
#define AR8216_ATU_CTRL_AGE_EN BIT(17)
|
||||
#define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16)
|
||||
#define AR8216_ATU_CTRL_AGE_TIME_S 0
|
||||
|
||||
#define AR8216_PORT_OFFSET(_i) (0x0100 * (_i + 1))
|
||||
#define AR8216_REG_PORT_STATUS(_i) (AR8216_PORT_OFFSET(_i) + 0x0000)
|
||||
#define AR8216_PORT_STATUS_SPEED BITS(0,2)
|
||||
|
|
@ -162,4 +177,11 @@ enum {
|
|||
AR8216_PORT_STATE_FORWARD = 4
|
||||
};
|
||||
|
||||
/* device */
|
||||
enum {
|
||||
UNKNOWN = 0,
|
||||
AR8216 = 8216,
|
||||
AR8316 = 8316
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue