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ar71xx: update early_printk code 

git-svn-id: svn://svn.openwrt.org/openwrt/trunk@27165 3c298f89-4303-0410-b956-a3cf2f4a3e73
master
Gabor Juhos 2011-06-13 08:12:38 +00:00
parent d6e5cf01d0
commit f6d3520a90
2 changed files with 111 additions and 43 deletions
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96
target/linux/ar71xx/files/arch/mips/ar71xx/early_printk.c
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@ -15,72 +15,82 @@
#include <asm/addrspace.h> #include <asm/addrspace.h>
#include <asm/mach-ar71xx/ar71xx.h> #include <asm/mach-ar71xx/ar71xx.h>
#include <asm/mach-ar71xx/ar933x_uart.h>
static void __iomem *prom_uart_base; static void (*_prom_putchar) (unsigned char);
static void (*_putchar)(unsigned char);
#define UART_READ(r) \ static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val)
__raw_readl(prom_uart_base + 4 * (r)) {
u32 t;
#define UART_WRITE(r, v) \ do {
__raw_writel((v), prom_uart_base + 4 * (r)) t = __raw_readl(reg);
if ((t & mask) == val)
break;
} while (1);
}
static void prom_putchar_ar71xx(unsigned char ch) static void prom_putchar_ar71xx(unsigned char ch)
{ {
while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0) void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE));
;
UART_WRITE(UART_TX, ch); prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0) __raw_writel(ch, base + UART_TX * 4);
; prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
} }
static void prom_putchar_ar933x(unsigned char ch) static void prom_putchar_ar933x(unsigned char ch)
{ {
while (((UART_READ(0)) & 0x200) == 0) void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE));
;
UART_WRITE(0, 0x200 | ch); prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
while (((UART_READ(0)) & 0x200) == 0) AR933X_UART_DATA_TX_CSR);
; __raw_writel(AR933X_UART_DATA_TX_CSR | ch, base + AR933X_UART_DATA_REG);
prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
AR933X_UART_DATA_TX_CSR);
} }
static int prom_putchar_init(void) static void prom_putchar_dummy(unsigned char ch)
{ {
if (_putchar) /* nothing to do */
return 0; }
switch(ar71xx_soc) { static void prom_putchar_init(void)
case AR71XX_SOC_AR7130: {
case AR71XX_SOC_AR7141: void __iomem *base;
case AR71XX_SOC_AR7161: u32 id;
case AR71XX_SOC_AR7240:
case AR71XX_SOC_AR7241: base = (void __iomem *)(KSEG1ADDR(AR71XX_RESET_BASE));
case AR71XX_SOC_AR7242: id = __raw_readl(base + AR71XX_RESET_REG_REV_ID);
case AR71XX_SOC_AR9130: id &= REV_ID_MAJOR_MASK;
case AR71XX_SOC_AR9132:
case AR71XX_SOC_AR9341: switch (id) {
case AR71XX_SOC_AR9342: case REV_ID_MAJOR_AR71XX:
case AR71XX_SOC_AR9344: case REV_ID_MAJOR_AR7240:
prom_uart_base = (void __iomem *) KSEG1ADDR(AR71XX_UART_BASE); case REV_ID_MAJOR_AR7241:
_putchar = prom_putchar_ar71xx; case REV_ID_MAJOR_AR7242:
case REV_ID_MAJOR_AR913X:
case REV_ID_MAJOR_AR9341:
case REV_ID_MAJOR_AR9342:
case REV_ID_MAJOR_AR9344:
_prom_putchar = prom_putchar_ar71xx;
break; break;
case AR71XX_SOC_AR9330: case REV_ID_MAJOR_AR9330:
case AR71XX_SOC_AR9331: case REV_ID_MAJOR_AR9331:
prom_uart_base = (void __iomem *) KSEG1ADDR(AR933X_UART_BASE); _prom_putchar = prom_putchar_ar933x;
_putchar = prom_putchar_ar933x;
break; break;
default: default:
return -ENODEV; _prom_putchar = prom_putchar_dummy;
break;
} }
return 0;
} }
void prom_putchar(unsigned char ch) void prom_putchar(unsigned char ch)
{ {
if (prom_putchar_init()) if (!_prom_putchar)
return; prom_putchar_init();
_putchar(ch); _prom_putchar(ch);
} }

58
target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar933x_uart.h Normal file
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@ -0,0 +1,58 @@
/*
* Atheros AR933X UART defines
*
* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef __AR933X_UART_H
#define __AR933X_UART_H
#define AR933X_UART_DATA_REG 0x00
#define AR933X_UART_CS_REG 0x04
#define AR933X_UART_CLOCK_REG 0x08
#define AR933X_UART_INT_REG 0x0c
#define AR933X_UART_INT_EN_REG 0x10
#define AR933X_UART_DATA_TX_RX_MASK 0xff
#define AR933X_UART_DATA_RX_CSR BIT(8)
#define AR933X_UART_DATA_TX_CSR BIT(9)
#define AR933X_UART_CS_PARITY_S 0
#define AR933X_UART_CS_PARITY_M 0x3
#define AR933X_UART_CS_PARITY_M 0x3
#define AR933X_UART_CS_IF_MODE_S 2
#define AR933X_UART_CS_IF_MODE_M 0x3
#define AR933X_UART_CS_FLOW_CTRL_S 4
#define AR933X_UART_CS_FLOW_CTRL_M 0x3
#define AR933X_UART_CS_DMA_EN BIT(6)
#define AR933X_UART_CS_TX_READY_ORIDE BIT(7)
#define AR933X_UART_CS_RX_READY_ORIDE BIT(8)
#define AR933X_UART_CS_TX_READY BIT(9)
#define AR933X_UART_CS_RX_BREAK BIT(10)
#define AR933X_UART_CS_TX_BREAK BIT(11)
#define AR933X_UART_CS_HOST_INT BIT(12)
#define AR933X_UART_CS_HOST_INT_EN BIT(13)
#define AR933X_UART_CS_TX_BUSY BIT(14)
#define AR933X_UART_CS_RX_BUSY BIT(15)
#define AR933X_UART_CLOCK_STEP_M 0xffff
#define AR933X_UART_CLOCK_SCALE_M 0xfff
#define AR933X_UART_CLCOK_SCALE_S 16
#define AR933X_UART_INT_RX_VALID BIT(0)
#define AR933X_UART_INT_TX_READY BIT(1)
#define AR933X_UART_INT_RX_FRAMING_ERR BIT(2)
#define AR933X_UART_INT_RX_OFLOW_ERR BIT(3)
#define AR933X_UART_INT_TX_OFLOW_ERR BIT(4)
#define AR933X_UART_INT_RX_PARITY_ERR BIT(5)
#define AR933X_UART_INT_RX_BREAK_ON BIT(6)
#define AR933X_UART_INT_RX_BREAK_OFF BIT(7)
#define AR933X_UART_INT_RX_FULL BIT(8)
#define AR933X_UART_INT_TX_EMPTY BIT(9)
#define AR933X_UART_INT_ALLINTS 0x3ff
#endif /* __AR933X_UART_H */