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Merge pull request #82 from ecsv/openmesh-cc 

OpenMesh MR1750(v2) and OM2P-HSv3 support for Chaos Calmer
master
Zoltan Herpai 2016-09-21 21:13:17 +02:00 committed by GitHub
parent 2a97364ad4 3411c9a885
commit d6b3ca24c5
25 changed files with 1012 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
package/boot/uboot-envtools/files/ar71xx
View File

@ -21,12 +21,16 @@ carambola2 | \
eap300v2 | \
hornet-ub | \
hornet-ub-x2 | \
mr1750 | \
mr1750v2 | \
mr600 | \
mr600v2 | \
mr900 | \
mr900v2 | \
nbg6716 | \
om5p-an | \
om5p-ac | \
om5p-acv2 | \
om5p | \
tube2h | \
wndr3700)
@ -38,6 +42,7 @@ om2p | \
om2pv2 | \
om2p-hs | \
om2p-hsv2 | \
om2p-hsv3 | \
om2p-lc)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x40000" "0x40000"
;;

7
package/kernel/om-watchdog/files/om-watchdog.init
View File

@ -13,7 +13,7 @@ boot() {
local board=$(ar71xx_board_name)
case "$board" in
"om2p"|"om2p-hs"|"om2p-hsv2")
"om2p"|"om2p-hs"|"om2p-hsv2"|"om2p-hsv3"|"om5p-acv2")
service_start /sbin/om-watchdog 12
;;
"om2pv2"|"om2p-lc")
@ -22,10 +22,13 @@ boot() {
"om5p"|"om5p-an")
service_start /sbin/om-watchdog 11
;;
"om5p-ac")
service_start /sbin/om-watchdog 17
;;
"mr600v2")
service_start /sbin/om-watchdog 15
;;
"mr900"|"mr900v2")
"mr900"|"mr900v2"|"mr1750"|"mr1750v2")
service_start /sbin/om-watchdog 16
;;
esac

11
scripts/om-fwupgradecfg-gen.sh
View File

@ -7,7 +7,7 @@
#
usage() {
echo "Usage: $0 <OM2P|OM5P|MR600|MR900> <out file path> <kernel path> <rootfs path>"
echo "Usage: $0 <OM2P|OM5P|OM5PAC|MR600|MR900|MR1750> <out file path> <kernel path> <rootfs path>"
rm -f $CFG_OUT
exit 1
}
@ -26,7 +26,7 @@ case $CE_TYPE in
FLASH_BS=262144
MD5_SKIP_BLOCKS=1
;;
OM5P|MR600|MR900)
OM5P|OM5PAC|MR600|MR900|MR1750)
MAX_PART_SIZE=7808
KERNEL_FLASH_ADDR=0xb0000
FLASH_BS=65536
@ -42,12 +42,15 @@ CHECK_BS=65536
KERNEL_SIZE=$(stat -c%s "$KERNEL_PATH")
KERNEL_MD5=$(md5=$(md5sum $KERNEL_PATH); echo ${md5%% *})
KERNEL_SHA256=$(openssl dgst -sha256 $KERNEL_PATH | awk '{print $2}')
KERNEL_PART_SIZE=$(size=$(($KERNEL_SIZE / $FLASH_BS)); [ $(($size * $FLASH_BS)) -lt $KERNEL_SIZE ] && size=$(($size + 1)); echo $(($size * $FLASH_BS / 1024)))
ROOTFS_FLASH_ADDR=$(addr=$(($KERNEL_FLASH_ADDR + ($KERNEL_PART_SIZE * 1024))); printf "0x%x" $addr)
ROOTFS_SIZE=$(stat -c%s "$ROOTFS_PATH")
ROOTFS_CHECK_BLOCKS=$((($ROOTFS_SIZE / $CHECK_BS) - $MD5_SKIP_BLOCKS))
ROOTFS_MD5=$(md5=$(dd if=$ROOTFS_PATH bs=$CHECK_BS count=$ROOTFS_CHECK_BLOCKS 2>&- | md5sum); echo ${md5%% *})
ROOTFS_MD5_FULL=$(md5=$(md5sum $ROOTFS_PATH); echo ${md5%% *})
ROOTFS_SHA256_FULL=$(openssl dgst -sha256 $ROOTFS_PATH | awk '{print $2}')
ROOTFS_CHECK_SIZE=$(printf '0x%x' $(($ROOTFS_CHECK_BLOCKS * $CHECK_BS)))
ROOTFS_PART_SIZE=$(($MAX_PART_SIZE - $KERNEL_PART_SIZE))
@ -55,6 +58,8 @@ cat << EOF > $CFG_OUT
[vmlinux]
filename=kernel
md5sum=$KERNEL_MD5
filemd5sum=$KERNEL_MD5
filesha256sum=$KERNEL_SHA256
flashaddr=$KERNEL_FLASH_ADDR
checksize=0x0
cmd_success=setenv bootseq 1,2; setenv kernel_size_1 $KERNEL_PART_SIZE; saveenv
@ -63,6 +68,8 @@ cmd_fail=reset
[rootfs]
filename=rootfs
md5sum=$ROOTFS_MD5
filemd5sum=$ROOTFS_MD5_FULL
filesha256sum=$ROOTFS_SHA256_FULL
flashaddr=$ROOTFS_FLASH_ADDR
checksize=$ROOTFS_CHECK_SIZE
cmd_success=setenv bootseq 1,2; setenv kernel_size_1 $KERNEL_PART_SIZE; setenv rootfs_size_1 $ROOTFS_PART_SIZE; saveenv

9
target/linux/ar71xx/base-files/etc/diag.sh
View File

@ -143,6 +143,10 @@ get_status_led() {
mr600v2)
status_led="mr600:blue:power"
;;
mr1750 | \
mr1750v2)
status_led="mr1750:blue:power"
;;
mr900 | \
mr900v2)
status_led="mr900:blue:power"
@ -168,6 +172,7 @@ get_status_led() {
om2pv2 | \
om2p-hs | \
om2p-hsv2 | \
om2p-hsv3 | \
om2p-lc)
status_led="om2p:blue:power"
;;
@ -175,6 +180,10 @@ get_status_led() {
om5p-an)
status_led="om5p:blue:power"
;;
om5p-ac | \
om5p-acv2)
status_led="om5pac:blue:power"
;;
onion-omega)
status_led="onion:amber:system"
;;

8
target/linux/ar71xx/base-files/etc/hotplug.d/firmware/11-ath10k-caldata
View File

@ -71,7 +71,9 @@ case "$FIRMWARE" in
ath10kcal_extract "caldata" 20480 2116
ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) +1)
;;
mr1750)
mr1750 | \
mr1750v2 | \
om5p-acv2)
ath10kcal_extract "ART" 20480 2116
ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) +16)
;;
@ -95,6 +97,10 @@ case "$FIRMWARE" in
rb-911g-5hpacd)
ath10kcal_from_file "/sys/firmware/routerboot/ext_wlan_data" 20480 2116
;;
om5p-ac)
ath10kcal_extract "ART" 20480 2116
ath10kcal_patch_mac $(macaddr_add $(cat /sys/class/net/eth0/address) +16)
;;
esac
;;
*)

13
target/linux/ar71xx/base-files/etc/uci-defaults/01_leds
View File

@ -239,6 +239,13 @@ mr600)
ucidef_set_led_wlan "wlan58" "WLAN58" "mr600:green:wlan58" "phy0tpt"
;;
mr1750 | \
mr1750v2)
ucidef_set_led_netdev "lan" "LAN" "mr1750:blue:wan" "eth0"
ucidef_set_led_wlan "wlan58" "WLAN58" "mr1750:blue:wlan58" "phy0tpt"
ucidef_set_led_wlan "wlan24" "WLAN24" "mr1750:blue:wlan24" "phy1tpt"
;;
mr900 | \
mr900v2)
ucidef_set_led_netdev "lan" "LAN" "mr900:blue:wan" "eth0"
@ -287,6 +294,7 @@ om2p | \
om2pv2 | \
om2p-hs | \
om2p-hsv2 | \
om2p-hsv3 | \
om2p-lc)
ucidef_set_led_netdev "port1" "port1" "om2p:blue:wan" "eth0"
ucidef_set_led_netdev "port2" "port2" "om2p:blue:lan" "eth1"
@ -298,6 +306,11 @@ om5p-an)
ucidef_set_led_netdev "port2" "port2" "om5p:blue:lan" "eth1"
;;
om5p-ac)
ucidef_set_led_netdev "port1" "port1" "om5pac:blue:lan" "eth0"
ucidef_set_led_netdev "port2" "port2" "om5pac:blue:wan" "eth1"
;;
qihoo-c301)
ucidef_set_led_wlan "wlan2g" "WLAN2G" "qihoo:red:status" "phy1tpt"
;;

2
target/linux/ar71xx/base-files/etc/uci-defaults/02_network
View File

@ -334,6 +334,8 @@ eap300v2 |\
eap7660d |\
el-mini |\
loco-m-xw |\
mr1750 |\
mr1750v2 |\
mr600 |\
mr600v2 |\
mr900 |\

15
target/linux/ar71xx/base-files/lib/ar71xx.sh
View File

@ -518,6 +518,12 @@ ar71xx_board_detect() {
*MR600v2)
name="mr600v2"
;;
*MR1750)
name="mr1750"
;;
*MR1750v2)
name="mr1750v2"
;;
*MR600)
name="mr600"
;;
@ -560,6 +566,9 @@ ar71xx_board_detect() {
*"OM2P HSv2")
name="om2p-hsv2"
;;
*"OM2P HSv3")
name="om2p-hsv3"
;;
*"OM2P LC")
name="om2p-lc"
;;
@ -569,6 +578,12 @@ ar71xx_board_detect() {
*"OM5P AN")
name="om5p-an"
;;
*"OM5P AC")
name="om5p-ac"
;;
*"OM5P ACv2")
name="om5p-acv2"
;;
*"Onion Omega")
name="onion-omega"
;;

15
target/linux/ar71xx/base-files/lib/upgrade/openmesh.sh
View File

@ -63,6 +63,7 @@ platform_check_image_openmesh()
[ "$board" = "om2p-lc" ] && break
[ "$board" = "om2p-hs" ] && break
[ "$board" = "om2p-hsv2" ] && break
[ "$board" = "om2p-hsv3" ] && break
echo "Invalid image board target ($img_board_target) for this platform: $board. Use the correct image for this platform"
return 1
;;
@ -72,6 +73,18 @@ platform_check_image_openmesh()
echo "Invalid image board target ($img_board_target) for this platform: $board. Use the correct image for this platform"
return 1
;;
OM5PAC)
[ "$board" = "om5p-ac" ] && break
[ "$board" = "om5p-acv2" ] && break
echo "Invalid image board target ($img_board_target) for this platform: $board. Use the correct image for this platform"
return 1
;;
MR1750)
[ "$board" = "mr1750" ] && break
[ "$board" = "mr1750v2" ] && break
echo "Invalid image board target ($img_board_target) for this platform: $board. Use the correct image for this platform"
return 1
;;
MR600)
[ "$board" = "mr600" ] && break
[ "$board" = "mr600v2" ] && break
@ -157,7 +170,7 @@ platform_do_upgrade_openmesh()
kernel_start_addr1=0x9f1c0000
kernel_start_addr2=0x9f8c0000
;;
OM5P|MR600|MR900)
OM5P|OM5PAC|MR600|MR900|MR1750)
block_size=$((64 * 1024))
total_size=7995392
kernel_start_addr1=0x9f0b0000

14
target/linux/ar71xx/base-files/lib/upgrade/platform.sh
View File

@ -290,6 +290,8 @@ platform_check_image() {
return 0;
;;
mr1750 | \
mr1750v2 | \
mr600 | \
mr600v2 | \
mr900 | \
@ -298,9 +300,12 @@ platform_check_image() {
om2pv2 | \
om2p-hs | \
om2p-hsv2 | \
om2p-hsv3 | \
om2p-lc | \
om5p | \
om5p-an)
om5p-an | \
om5p-ac | \
om5p-acv2)
platform_check_image_openmesh "$magic_long" "$1" && return 0
return 1
;;
@ -518,6 +523,8 @@ platform_do_upgrade() {
tew-673gru)
platform_do_upgrade_dir825b "$ARGV"
;;
mr1750 | \
mr1750v2 | \
mr600 | \
mr600v2 | \
mr900 | \
@ -526,9 +533,12 @@ platform_do_upgrade() {
om2pv2 | \
om2p-hs | \
om2p-hsv2 | \
om2p-hsv3 | \
om2p-lc | \
om5p | \
om5p-an)
om5p-an | \
om5p-ac | \
om5p-acv2)
platform_do_upgrade_openmesh "$ARGV"
;;
unifi-outdoor-plus | \

3
target/linux/ar71xx/config-3.18
View File

@ -79,6 +79,7 @@ CONFIG_ATH79_MACH_JWAP003=y
CONFIG_ATH79_MACH_MC_MAC1200R=y
CONFIG_ATH79_MACH_MR16=y
CONFIG_ATH79_MACH_MR12=y
CONFIG_ATH79_MACH_MR1750=y
CONFIG_ATH79_MACH_MR600=y
CONFIG_ATH79_MACH_MR900=y
CONFIG_ATH79_MACH_MYNET_N600=y
@ -90,6 +91,8 @@ CONFIG_ATH79_MACH_NBG460N=y
CONFIG_ATH79_MACH_NBG6716=y
CONFIG_ATH79_MACH_OM2P=y
CONFIG_ATH79_MACH_OM5P=y
CONFIG_ATH79_MACH_OM5P_AC=y
CONFIG_ATH79_MACH_OM5P_ACv2=y
CONFIG_ATH79_MACH_ONION_OMEGA=y
CONFIG_ATH79_MACH_PB42=y
CONFIG_ATH79_MACH_PB44=y

171
target/linux/ar71xx/files/arch/mips/ath79/mach-mr1750.c Normal file
View File

@ -0,0 +1,171 @@
/*
* MR1750 board support
*
* Copyright (c) 2012 Qualcomm Atheros
* Copyright (c) 2012-2013 Marek Lindner <marek@open-mesh.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
#include <linux/platform_device.h>
#include <linux/ar8216_platform.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include <linux/platform_data/phy-at803x.h>
#include "common.h"
#include "dev-ap9x-pci.h"
#include "dev-gpio-buttons.h"
#include "dev-eth.h"
#include "dev-leds-gpio.h"
#include "dev-m25p80.h"
#include "dev-wmac.h"
#include "machtypes.h"
#include "pci.h"
#define MR1750_GPIO_LED_LAN 12
#define MR1750_GPIO_LED_WLAN_2G 13
#define MR1750_GPIO_LED_STATUS_GREEN 19
#define MR1750_GPIO_LED_STATUS_RED 21
#define MR1750_GPIO_LED_POWER 22
#define MR1750_GPIO_LED_WLAN_5G 23
#define MR1750_GPIO_BTN_RESET 17
#define MR1750_KEYS_POLL_INTERVAL 20 /* msecs */
#define MR1750_KEYS_DEBOUNCE_INTERVAL (3 * MR1750_KEYS_POLL_INTERVAL)
#define MR1750_MAC0_OFFSET 0
#define MR1750_WMAC_CALDATA_OFFSET 0x1000
static struct gpio_led mr1750_leds_gpio[] __initdata = {
{
.name = "mr1750:blue:power",
.gpio = MR1750_GPIO_LED_POWER,
.active_low = 1,
},
{
.name = "mr1750:blue:wan",
.gpio = MR1750_GPIO_LED_LAN,
.active_low = 1,
},
{
.name = "mr1750:blue:wlan24",
.gpio = MR1750_GPIO_LED_WLAN_2G,
.active_low = 1,
},
{
.name = "mr1750:blue:wlan58",
.gpio = MR1750_GPIO_LED_WLAN_5G,
.active_low = 1,
},
{
.name = "mr1750:green:status",
.gpio = MR1750_GPIO_LED_STATUS_GREEN,
.active_low = 1,
},
{
.name = "mr1750:red:status",
.gpio = MR1750_GPIO_LED_STATUS_RED,
.active_low = 1,
},
};
static struct gpio_keys_button mr1750_gpio_keys[] __initdata = {
{
.desc = "Reset button",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = MR1750_KEYS_DEBOUNCE_INTERVAL,
.gpio = MR1750_GPIO_BTN_RESET,
.active_low = 1,
},
};
static struct at803x_platform_data mr1750_at803x_data = {
.disable_smarteee = 1,
.enable_rgmii_rx_delay = 1,
.enable_rgmii_tx_delay = 0,
.fixup_rgmii_tx_delay = 1,
};
static struct mdio_board_info mr1750_mdio0_info[] = {
{
.bus_id = "ag71xx-mdio.0",
.phy_addr = 5,
.platform_data = &mr1750_at803x_data,
},
};
static void __init mr1750_setup_qca955x_eth_cfg(u32 mask,
unsigned int rxd,
unsigned int rxdv,
unsigned int txd,
unsigned int txe)
{
void __iomem *base;
u32 t;
base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
t = mask;
t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
iounmap(base);
}
static void __init mr1750_setup(void)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
u8 mac[6];
ath79_eth0_pll_data.pll_1000 = 0xae000000;
ath79_eth0_pll_data.pll_100 = 0xa0000101;
ath79_eth0_pll_data.pll_10 = 0xa0001313;
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(mr1750_leds_gpio),
mr1750_leds_gpio);
ath79_register_gpio_keys_polled(-1, MR1750_KEYS_POLL_INTERVAL,
ARRAY_SIZE(mr1750_gpio_keys),
mr1750_gpio_keys);
ath79_init_mac(mac, art + MR1750_MAC0_OFFSET, 1);
ath79_register_wmac(art + MR1750_WMAC_CALDATA_OFFSET, mac);
ath79_register_pci();
mr1750_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(mr1750_mdio0_info,
ARRAY_SIZE(mr1750_mdio0_info));
ath79_init_mac(ath79_eth0_data.mac_addr, art + MR1750_MAC0_OFFSET, 0);
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(5);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_register_eth(0);
}
MIPS_MACHINE(ATH79_MACH_MR1750, "MR1750", "OpenMesh MR1750", mr1750_setup);
MIPS_MACHINE(ATH79_MACH_MR1750V2, "MR1750v2", "OpenMesh MR1750v2", mr1750_setup);

42
target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c
View File

@ -23,6 +23,7 @@
#include <linux/ath9k_platform.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include <linux/platform_data/phy-at803x.h>
#include "common.h"
#include "dev-ap9x-pci.h"
@ -94,18 +95,37 @@ static struct gpio_keys_button mr900_gpio_keys[] __initdata = {
},
};
static struct at803x_platform_data mr900_at803x_data = {
.disable_smarteee = 1,
.enable_rgmii_rx_delay = 1,
.enable_rgmii_tx_delay = 0,
.fixup_rgmii_tx_delay = 1,
};
static void __init mr900_gmac_setup(void)
static struct mdio_board_info mr900_mdio0_info[] = {
{
.bus_id = "ag71xx-mdio.0",
.phy_addr = 5,
.platform_data = &mr900_at803x_data,
},
};
static void __init mr900_setup_qca955x_eth_cfg(u32 mask,
unsigned int rxd,
unsigned int rxdv,
unsigned int txd,
unsigned int txe)
{
void __iomem *base;
u32 t;
base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
t |= QCA955X_ETH_CFG_RGMII_EN;
t = mask;
t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
@ -118,9 +138,9 @@ static void __init mr900_setup(void)
u8 mac[6], pcie_mac[6];
struct ath9k_platform_data *pdata;
ath79_eth0_pll_data.pll_1000 = 0xbe000101;
ath79_eth0_pll_data.pll_100 = 0x80000101;
ath79_eth0_pll_data.pll_10 = 0x80001313;
ath79_eth0_pll_data.pll_1000 = 0xae000000;
ath79_eth0_pll_data.pll_100 = 0xa0000101;
ath79_eth0_pll_data.pll_10 = 0xa0001313;
ath79_register_m25p80(NULL);
@ -141,10 +161,12 @@ static void __init mr900_setup(void)
}
pdata->use_eeprom = true;
mr900_gmac_setup();
mr900_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(mr900_mdio0_info,
ARRAY_SIZE(mr900_mdio0_info));
ath79_init_mac(ath79_eth0_data.mac_addr, art + MR900_MAC0_OFFSET, 0);
/* GMAC0 is connected to the RMGII interface */

1
target/linux/ar71xx/files/arch/mips/ath79/mach-om2p.c
View File

@ -223,3 +223,4 @@ static void __init om2p_hs_setup(void)
MIPS_MACHINE(ATH79_MACH_OM2P_HS, "OM2P-HS", "OpenMesh OM2P HS", om2p_hs_setup);
MIPS_MACHINE(ATH79_MACH_OM2P_HSv2, "OM2P-HSv2", "OpenMesh OM2P HSv2", om2p_hs_setup);
MIPS_MACHINE(ATH79_MACH_OM2P_HSv3, "OM2P-HSv3", "OpenMesh OM2P HSv3", om2p_hs_setup);

193
target/linux/ar71xx/files/arch/mips/ath79/mach-om5pac.c Normal file
View File

@ -0,0 +1,193 @@
/*
* OpenMesh OM5P-AC support
*
* Copyright (C) 2013 Marek Lindner <marek@open-mesh.com>
* Copyright (C) 2014 Sven Eckelmann <sven@open-mesh.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/i2c-gpio.h>
#include <linux/platform_data/phy-at803x.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include <asm/mach-ath79/ath79.h>
#include "common.h"
#include "dev-ap9x-pci.h"
#include "dev-eth.h"
#include "dev-leds-gpio.h"
#include "dev-m25p80.h"
#include "dev-wmac.h"
#include "machtypes.h"
#include "pci.h"
#define OM5PAC_GPIO_LED_POWER 18
#define OM5PAC_GPIO_LED_GREEN 21
#define OM5PAC_GPIO_LED_RED 23
#define OM5PAC_GPIO_LED_YELLOW 22
#define OM5PAC_GPIO_LED_LAN 20
#define OM5PAC_GPIO_LED_WAN 19
#define OM5PAC_GPIO_I2C_SCL 12
#define OM5PAC_GPIO_I2C_SDA 11
#define OM5PAC_KEYS_POLL_INTERVAL 20 /* msecs */
#define OM5PAC_KEYS_DEBOUNCE_INTERVAL (3 * OM5PAC_KEYS_POLL_INTERVAL)
#define OM5PAC_WMAC_CALDATA_OFFSET 0x1000
static struct gpio_led om5pac_leds_gpio[] __initdata = {
{
.name = "om5pac:blue:power",
.gpio = OM5PAC_GPIO_LED_POWER,
.active_low = 1,
}, {
.name = "om5pac:red:wifi",
.gpio = OM5PAC_GPIO_LED_RED,
.active_low = 1,
}, {
.name = "om5pac:yellow:wifi",
.gpio = OM5PAC_GPIO_LED_YELLOW,
.active_low = 1,
}, {
.name = "om5pac:green:wifi",
.gpio = OM5PAC_GPIO_LED_GREEN,
.active_low = 1,
}, {
.name = "om5pac:blue:lan",
.gpio = OM5PAC_GPIO_LED_LAN,
.active_low = 1,
}, {
.name = "om5pac:blue:wan",
.gpio = OM5PAC_GPIO_LED_WAN,
.active_low = 1,
}
};
static struct flash_platform_data om5pac_flash_data = {
.type = "mx25l12805d",
};
static struct i2c_gpio_platform_data om5pac_i2c_device_platdata = {
.sda_pin = OM5PAC_GPIO_I2C_SDA,
.scl_pin = OM5PAC_GPIO_I2C_SCL,
.udelay = 10,
.sda_is_open_drain = 1,
.scl_is_open_drain = 1,
};
static struct platform_device om5pac_i2c_device = {
.name = "i2c-gpio",
.id = 0,
.dev = {
.platform_data = &om5pac_i2c_device_platdata,
},
};
static struct i2c_board_info om5pac_i2c_devs[] __initdata = {
{
I2C_BOARD_INFO("tmp423", 0x4c),
},
};
static struct at803x_platform_data om5pac_at803x_data = {
.disable_smarteee = 1,
.enable_rgmii_rx_delay = 1,
.enable_rgmii_tx_delay = 1,
};
static struct mdio_board_info om5pac_mdio0_info[] = {
{
.bus_id = "ag71xx-mdio.0",
.phy_addr = 1,
.platform_data = &om5pac_at803x_data,
},
{
.bus_id = "ag71xx-mdio.0",
.phy_addr = 2,
.platform_data = &om5pac_at803x_data,
},
};
static void __init om5p_ac_setup_qca955x_eth_cfg(u32 mask,
unsigned int rxd,
unsigned int rxdv,
unsigned int txd,
unsigned int txe)
{
void __iomem *base;
u32 t;
base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
t = mask;
t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
iounmap(base);
}
static void __init om5p_ac_setup(void)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
u8 mac[6];
/* temperature sensor */
platform_device_register(&om5pac_i2c_device);
i2c_register_board_info(0, om5pac_i2c_devs,
ARRAY_SIZE(om5pac_i2c_devs));
ath79_gpio_output_select(OM5PAC_GPIO_LED_WAN, QCA955X_GPIO_OUT_GPIO);
ath79_register_m25p80(&om5pac_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(om5pac_leds_gpio),
om5pac_leds_gpio);
ath79_init_mac(mac, art, 0x02);
ath79_register_wmac(art + OM5PAC_WMAC_CALDATA_OFFSET, mac);
om5p_ac_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 3, 3, 0, 0);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(om5pac_mdio0_info,
ARRAY_SIZE(om5pac_mdio0_info));
ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00);
ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01);
/* GMAC0 is connected to the PHY1 */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_data.phy_mask = BIT(1);
ath79_eth0_pll_data.pll_1000 = 0x82000101;
ath79_eth0_pll_data.pll_100 = 0x80000101;
ath79_eth0_pll_data.pll_10 = 0x80001313;
ath79_register_eth(0);
/* GMAC1 is connected to MDIO1 in SGMII mode */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth1_data.phy_mask = BIT(2);
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_eth1_pll_data.pll_100 = 0x80000101;
ath79_eth1_pll_data.pll_10 = 0x80001313;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(1);
ath79_register_pci();
}
MIPS_MACHINE(ATH79_MACH_OM5P_AC, "OM5P-AC", "OpenMesh OM5P AC", om5p_ac_setup);

216
target/linux/ar71xx/files/arch/mips/ath79/mach-om5pacv2.c Normal file
View File

@ -0,0 +1,216 @@
/*
* OpenMesh OM5P-ACv2 support
*
* Copyright (C) 2013 Marek Lindner <marek@open-mesh.com>
* Copyright (C) 2014-2016 Sven Eckelmann <sven@open-mesh.com>
* Copyright (C) 2015 Open-Mesh - Jim Collar <jim.collar@eqware.net>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <linux/mdio-gpio.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/i2c-gpio.h>
#include <linux/platform_data/phy-at803x.h>
#include <asm/mach-ath79/ar71xx_regs.h>
#include <asm/mach-ath79/ath79.h>
#include "common.h"
#include "dev-ap9x-pci.h"
#include "dev-eth.h"
#include "dev-gpio-buttons.h"
#include "dev-leds-gpio.h"
#include "dev-m25p80.h"
#include "dev-wmac.h"
#include "machtypes.h"
#include "pci.h"
#define OM5PACV2_GPIO_LED_POWER 14
#define OM5PACV2_GPIO_LED_GREEN 13
#define OM5PACV2_GPIO_LED_RED 23
#define OM5PACV2_GPIO_LED_YELLOW 15
#define OM5PACV2_GPIO_BTN_RESET 1
#define OM5PACV2_GPIO_I2C_SCL 18
#define OM5PACV2_GPIO_I2C_SDA 19
#define OM5PACV2_GPIO_PA_DCDC 2
#define OM5PACV2_GPIO_PA_HIGH 16
#define OM5PACV2_KEYS_POLL_INTERVAL 20 /* msecs */
#define OM5PACV2_KEYS_DEBOUNCE_INTERVAL (3 * OM5PACV2_KEYS_POLL_INTERVAL)
#define OM5PACV2_WMAC_CALDATA_OFFSET 0x1000
static struct gpio_led om5pacv2_leds_gpio[] __initdata = {
{
.name = "om5pac:blue:power",
.gpio = OM5PACV2_GPIO_LED_POWER,
.active_low = 1,
}, {
.name = "om5pac:red:wifi",
.gpio = OM5PACV2_GPIO_LED_RED,
.active_low = 1,
}, {
.name = "om5pac:yellow:wifi",
.gpio = OM5PACV2_GPIO_LED_YELLOW,
.active_low = 1,
}, {
.name = "om5pac:green:wifi",
.gpio = OM5PACV2_GPIO_LED_GREEN,
.active_low = 1,
}
};
static struct gpio_keys_button om5pacv2_gpio_keys[] __initdata = {
{
.desc = "reset",
.type = EV_KEY,
.code = KEY_RESTART,
.debounce_interval = OM5PACV2_KEYS_DEBOUNCE_INTERVAL,
.gpio = OM5PACV2_GPIO_BTN_RESET,
.active_low = 1,
}
};
static struct i2c_gpio_platform_data om5pacv2_i2c_device_platdata = {
.sda_pin = OM5PACV2_GPIO_I2C_SDA,
.scl_pin = OM5PACV2_GPIO_I2C_SCL,
.udelay = 10,
.sda_is_open_drain = 1,
.scl_is_open_drain = 1,
};
static struct platform_device om5pacv2_i2c_device = {
.name = "i2c-gpio",
.id = 0,
.dev = {
.platform_data = &om5pacv2_i2c_device_platdata,
},
};
static struct i2c_board_info om5pacv2_i2c_devs[] __initdata = {
{
I2C_BOARD_INFO("tmp423", 0x4e),
},
};
static struct flash_platform_data om5pacv2_flash_data = {
.type = "mx25l12805d",
};
static struct at803x_platform_data om5pacv2_an_at803x_data = {
.disable_smarteee = 1,
.enable_rgmii_rx_delay = 1,
.enable_rgmii_tx_delay = 1,
};
static struct at803x_platform_data om5pacv2_an_at8031_data = {
.disable_smarteee = 1,
.enable_rgmii_rx_delay = 1,
.enable_rgmii_tx_delay = 1,
};
static struct mdio_board_info om5pacv2_an_mdio0_info[] = {
{
.bus_id = "ag71xx-mdio.0",
.phy_addr = 4,
.platform_data = &om5pacv2_an_at803x_data,
},
{
.bus_id = "ag71xx-mdio.1",
.phy_addr = 1,
.platform_data = &om5pacv2_an_at8031_data,
},
};
static void __init om5p_acv2_setup_qca955x_eth_cfg(u32 mask,
unsigned int rxd,
unsigned int rxdv,
unsigned int txd,
unsigned int txe)
{
void __iomem *base;
u32 t;
base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
t = mask;
t |= rxd << QCA955X_ETH_CFG_RXD_DELAY_SHIFT;
t |= rxdv << QCA955X_ETH_CFG_RDV_DELAY_SHIFT;
t |= txd << QCA955X_ETH_CFG_TXD_DELAY_SHIFT;
t |= txe << QCA955X_ETH_CFG_TXE_DELAY_SHIFT;
__raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
iounmap(base);
}
static void __init om5p_acv2_setup(void)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
u8 mac[6];
/* power amplifier high power, 4.2V at RFFM4203/4503 instead of 3.3 */
ath79_gpio_function_enable(QCA955X_GPIO_FUNC_JTAG_DISABLE);
ath79_gpio_output_select(OM5PACV2_GPIO_PA_DCDC, QCA955X_GPIO_OUT_GPIO);
ath79_gpio_output_select(OM5PACV2_GPIO_PA_HIGH, QCA955X_GPIO_OUT_GPIO);
gpio_request_one(OM5PACV2_GPIO_PA_DCDC, GPIOF_OUT_INIT_HIGH,
"PA DC/DC");
gpio_request_one(OM5PACV2_GPIO_PA_HIGH, GPIOF_OUT_INIT_HIGH, "PA HIGH");
/* temperature sensor */
platform_device_register(&om5pacv2_i2c_device);
i2c_register_board_info(0, om5pacv2_i2c_devs,
ARRAY_SIZE(om5pacv2_i2c_devs));
ath79_register_m25p80(&om5pacv2_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(om5pacv2_leds_gpio),
om5pacv2_leds_gpio);
ath79_register_gpio_keys_polled(-1, OM5PACV2_KEYS_POLL_INTERVAL,
ARRAY_SIZE(om5pacv2_gpio_keys),
om5pacv2_gpio_keys);
ath79_init_mac(mac, art, 0x02);
ath79_register_wmac(art + OM5PACV2_WMAC_CALDATA_OFFSET, mac);
om5p_acv2_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 2, 2, 0, 0);
ath79_register_mdio(0, 0x0);
ath79_register_mdio(1, 0x0);
mdiobus_register_board_info(om5pacv2_an_mdio0_info,
ARRAY_SIZE(om5pacv2_an_mdio0_info));
ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00);
ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01);
/* GMAC0 is connected to the PHY4 */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_pll_data.pll_1000 = 0x82000101;
ath79_eth0_pll_data.pll_100 = 0x80000101;
ath79_eth0_pll_data.pll_10 = 0x80001313;
ath79_register_eth(0);
/* GMAC1 is connected to MDIO1 in SGMII mode */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_eth1_data.phy_mask = BIT(1);
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_eth1_pll_data.pll_100 = 0x80000101;
ath79_eth1_pll_data.pll_10 = 0x80001313;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(1);
ath79_register_pci();
}
MIPS_MACHINE(ATH79_MACH_OM5P_ACv2, "OM5P-ACv2", "OpenMesh OM5P ACv2", om5p_acv2_setup);

28
target/linux/ar71xx/generic/profiles/openmesh.mk
View File

@ -6,12 +6,12 @@
#
define Profile/OM2P
NAME:=OpenMesh OM2P/OM2Pv2/OM2P-HS/OM2P-HSv2/OM2P-LC
NAME:=OpenMesh OM2P/OM2Pv2/OM2P-HS/OM2P-HSv2/OM2P-HSv3/OM2P-LC
PACKAGES:=kmod-ath9k om-watchdog
endef
define Profile/OM2P/Description
Package set optimized for the OpenMesh OM2P/OM2Pv2/OM2P-HS/OM2P-HSv2/OM2P-LC.
Package set optimized for the OpenMesh OM2P/OM2Pv2/OM2P-HS/OM2P-HSv2/OM2P-HSv3/OM2P-LC.
endef
$(eval $(call Profile,OM2P))
@ -27,6 +27,17 @@ endef
$(eval $(call Profile,OM5P))
define Profile/OM5PAC
NAME:=OpenMesh OM5P-AC/OM5P-ACv2
PACKAGES:=kmod-ath9k kmod-ath10k om-watchdog ath10k-firmware-qca988x
endef
define Profile/OM5PAC/Description
Package set optimized for the OpenMesh OM5P-AC/OM5P-ACv2.
endef
$(eval $(call Profile,OM5PAC))
define Profile/MR600
NAME:=OpenMesh MR600
PACKAGES:=kmod-ath9k om-watchdog
@ -49,9 +60,20 @@ endef
$(eval $(call Profile,MR900))
define Profile/MR1750
NAME:=OpenMesh MR1750/MR1750v2
PACKAGES:=kmod-ath9k kmod-ath10k ath10k-firmware-qca988x
endef
define Profile/MR1750/Description
Package set optimized for the OpenMesh MR1750/MR1750v2.
endef
$(eval $(call Profile,MR1750))
define Profile/OPENMESH
NAME:=OpenMesh products
PACKAGES:=kmod-ath9k om-watchdog
PACKAGES:=kmod-ath9k kmod-ath10k om-watchdog
endef
define Profile/OPENMESH/Description

7
target/linux/ar71xx/image/Makefile
View File

@ -1847,6 +1847,9 @@ define Image/Build/OpenMesh
"$(BUILD_DIR)/fwupgrade.cfg-$(4)" "fwupgrade.cfg" \
"$(KDIR_TMP)/vmlinux-$(2).uImage" "kernel" \
"$(KDIR)/root.$(1)" "rootfs"
if [ -e "$(call factoryname,$(1),$(2))" ]; then \
cp "$(call factoryname,$(1),$(2))" "$(call sysupname,$(1),$(2))"; \
fi
endef
@ -2010,8 +2013,10 @@ $(eval $(call SingleProfile,Netgear,64kraw,WPN824N,wpn824n,WPN824N,ttyS0,115200,
$(eval $(call SingleProfile,OpenMesh,squashfs-only,OM2P,om2p,,,,OM2P))
$(eval $(call SingleProfile,OpenMesh,squashfs-only,OM5P,om5p,,,,OM5P))
$(eval $(call SingleProfile,OpenMesh,squashfs-only,OM5PAC,om5pac,,,,OM5PAC))
$(eval $(call SingleProfile,OpenMesh,squashfs-only,MR600,mr600,,,,MR600))
$(eval $(call SingleProfile,OpenMesh,squashfs-only,MR900,mr900,,,,MR900))
$(eval $(call SingleProfile,OpenMesh,squashfs-only,MR1750,mr1750,,,,MR1750))
$(eval $(call SingleProfile,PB4X,128k,ALL0305,all0305,ALL0305,ttyS0,115200))
$(eval $(call SingleProfile,PB4X,128k,EAP7660D,eap7660d,EAP7660D,ttyS0,115200))
@ -2105,7 +2110,7 @@ $(eval $(call MultiProfile,AP121,AP121_2M AP121_4M))
$(eval $(call MultiProfile,DIR615IX,DIR615I1 DIR615I3))
$(eval $(call MultiProfile,AP136,AP136_010 AP136_020))
$(eval $(call MultiProfile,EWDORIN, EWDORINAP EWDORINRT EWDORIN16M))
$(eval $(call MultiProfile,OPENMESH,OM2P OM5P MR600 MR900))
$(eval $(call MultiProfile,OPENMESH,OM2P OM5P OM5PAC MR600 MR900 MR1750))
$(eval $(call MultiProfile,TEW652BRP,TEW652BRP_FW TEW652BRP_RECOVERY))
$(eval $(call MultiProfile,TLMR3220,TLMR3220V1))
$(eval $(call MultiProfile,TLMR3420,TLMR3420V1))

96
target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch
View File

@ -194,7 +194,7 @@
#define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
#define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
@@ -529,6 +626,12 @@
@@ -529,8 +626,22 @@
#define AR71XX_GPIO_REG_INT_ENABLE 0x24
#define AR71XX_GPIO_REG_FUNC 0x28
@ -206,8 +206,18 @@
+#define AR934X_GPIO_REG_OUT_FUNC5 0x40
#define AR934X_GPIO_REG_FUNC 0x6c
+#define QCA955X_GPIO_REG_OUT_FUNC0 0x2c
+#define QCA955X_GPIO_REG_OUT_FUNC1 0x30
+#define QCA955X_GPIO_REG_OUT_FUNC2 0x34
+#define QCA955X_GPIO_REG_OUT_FUNC3 0x38
+#define QCA955X_GPIO_REG_OUT_FUNC4 0x3c
+#define QCA955X_GPIO_REG_OUT_FUNC5 0x40
+#define QCA955X_GPIO_REG_FUNC 0x6c
+
#define AR71XX_GPIO_COUNT 16
@@ -560,4 +663,153 @@
#define AR7240_GPIO_COUNT 18
#define AR7241_GPIO_COUNT 20
@@ -560,4 +671,235 @@
#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
@ -288,6 +298,71 @@
+#define AR934X_GPIO_OUT_EXT_LNA0 46
+#define AR934X_GPIO_OUT_EXT_LNA1 47
+
+#define QCA955X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
+#define QCA955X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
+#define QCA955X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
+#define QCA955X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
+#define QCA955X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
+#define QCA955X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
+#define QCA955X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
+#define QCA955X_GPIO_FUNC_JTAG_DISABLE BIT(1)
+
+#define QCA955X_GPIO_OUT_GPIO 0
+#define QCA955X_MII_EXT_MDI 1
+#define QCA955X_SLIC_DATA_OUT 3
+#define QCA955X_SLIC_PCM_FS 4
+#define QCA955X_SLIC_PCM_CLK 5
+#define QCA955X_SPI_CLK 8
+#define QCA955X_SPI_CS_0 9
+#define QCA955X_SPI_CS_1 10
+#define QCA955X_SPI_CS_2 11
+#define QCA955X_SPI_MISO 12
+#define QCA955X_I2S_CLK 13
+#define QCA955X_I2S_WS 14
+#define QCA955X_I2S_SD 15
+#define QCA955X_I2S_MCK 16
+#define QCA955X_SPDIF_OUT 17
+#define QCA955X_UART1_TD 18
+#define QCA955X_UART1_RTS 19
+#define QCA955X_UART1_RD 20
+#define QCA955X_UART1_CTS 21
+#define QCA955X_UART0_SOUT 22
+#define QCA955X_SPDIF2_OUT 23
+#define QCA955X_LED_SGMII_SPEED0 24
+#define QCA955X_LED_SGMII_SPEED1 25
+#define QCA955X_LED_SGMII_DUPLEX 26
+#define QCA955X_LED_SGMII_LINK_UP 27
+#define QCA955X_SGMII_SPEED0_INVERT 28
+#define QCA955X_SGMII_SPEED1_INVERT 29
+#define QCA955X_SGMII_DUPLEX_INVERT 30
+#define QCA955X_SGMII_LINK_UP_INVERT 31
+#define QCA955X_GE1_MII_MDO 32
+#define QCA955X_GE1_MII_MDC 33
+#define QCA955X_SWCOM2 38
+#define QCA955X_SWCOM3 39
+#define QCA955X_MAC2_GPIO 40
+#define QCA955X_MAC3_GPIO 41
+#define QCA955X_ATT_LED 42
+#define QCA955X_PWR_LED 43
+#define QCA955X_TX_FRAME 44
+#define QCA955X_RX_CLEAR_EXTERNAL 45
+#define QCA955X_LED_NETWORK_EN 46
+#define QCA955X_LED_POWER_EN 47
+#define QCA955X_WMAC_GLUE_WOW 68
+#define QCA955X_RX_CLEAR_EXTENSION 70
+#define QCA955X_CP_NAND_CS1 73
+#define QCA955X_USB_SUSPEND 74
+#define QCA955X_ETH_TX_ERR 75
+#define QCA955X_DDR_DQ_OE 76
+#define QCA955X_CLKREQ_N_EP 77
+#define QCA955X_CLKREQ_N_RC 78
+#define QCA955X_CLK_OBS0 79
+#define QCA955X_CLK_OBS1 80
+#define QCA955X_CLK_OBS2 81
+#define QCA955X_CLK_OBS3 82
+#define QCA955X_CLK_OBS4 83
+#define QCA955X_CLK_OBS5 84
+
+/*
+ * MII_CTRL block
+ */
@ -358,6 +433,23 @@
+#define QCA955X_GMAC_REG_ETH_CFG 0x00
+
+#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
+#define QCA955X_ETH_CFG_MII_GE0 BIT(1)
+#define QCA955X_ETH_CFG_GMII_GE0 BIT(2)
+#define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3)
+#define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4)
+#define QCA955X_ETH_CFG_GE0_ERR_EN BIT(5)
+#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
+#define QCA955X_ETH_CFG_RMII_GE0 BIT(10)
+#define QCA955X_ETH_CFG_MII_CNTL_SPEED BIT(11)
+#define QCA955X_ETH_CFG_RMII_GE0_MASTER BIT(12)
+#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3
+#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14
+#define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
+#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3
+#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16
+#define QCA955X_ETH_CFG_TXD_DELAY_MASK 0x3
+#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT 18
+#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
+#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
+
#endif /* __ASM_MACH_AR71XX_REGS_H */

44
target/linux/ar71xx/patches-3.18/739-MIPS-ath79-add-gpio-func-register-for-QCA955x-SoC.patch Normal file
View File

@ -0,0 +1,44 @@
--- a/arch/mips/ath79/gpio.c
+++ b/arch/mips/ath79/gpio.c
@@ -146,7 +146,8 @@ static void __iomem *ath79_gpio_get_func
if (soc_is_ar71xx() ||
soc_is_ar724x() ||
soc_is_ar913x() ||
- soc_is_ar933x())
+ soc_is_ar933x() ||
+ soc_is_qca955x())
reg = AR71XX_GPIO_REG_FUNC;
else if (soc_is_ar934x() ||
soc_is_qca953x() || soc_is_qca956x())
@@ -185,15 +186,27 @@ void __init ath79_gpio_output_select(uns
{
void __iomem *base = ath79_gpio_base;
unsigned long flags;
- unsigned int reg;
+ unsigned int reg, reg_base;
+ unsigned long gpio_count;
u32 t, s;
- BUG_ON(!soc_is_ar934x() && !soc_is_qca953x());
+ if (soc_is_ar934x()) {
+ gpio_count = AR934X_GPIO_COUNT;
+ reg_base = AR934X_GPIO_REG_OUT_FUNC0;
+ } else if (soc_is_qca953x()) {
+ gpio_count = QCA953X_GPIO_COUNT;
+ reg_base = QCA953X_GPIO_REG_OUT_FUNC0;
+ } else if (soc_is_qca955x()) {
+ gpio_count = QCA955X_GPIO_COUNT;
+ reg_base = QCA955X_GPIO_REG_OUT_FUNC0;
+ } else {
+ BUG();
+ }
- if (gpio >= AR934X_GPIO_COUNT)
+ if (gpio >= gpio_count)
return;
- reg = AR934X_GPIO_REG_OUT_FUNC0 + 4 * (gpio / 4);
+ reg = reg_base + 4 * (gpio / 4);
s = 8 * (gpio % 4);
spin_lock_irqsave(&ath79_gpio_lock, flags);

39
target/linux/ar71xx/patches-3.18/815-MIPS-ath79-add-mr1750-support.patch Normal file
View File

@ -0,0 +1,39 @@
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
@@ -763,6 +763,16 @@ config ATH79_MACH_CAP4200AG
select ATH79_DEV_M25P80
select ATH79_DEV_WMAC
+config ATH79_MACH_MR1750
+ bool "OpenMesh MR1750 board support"
+ select SOC_QCA955X
+ select ATH79_DEV_AP9X_PCI if PCI
+ select ATH79_DEV_ETH
+ select ATH79_DEV_GPIO_BUTTONS
+ select ATH79_DEV_LEDS_GPIO
+ select ATH79_DEV_M25P80
+ select ATH79_DEV_WMAC
+
config ATH79_MACH_MR900
bool "OpenMesh MR900 board support"
select SOC_QCA955X
--- a/arch/mips/ath79/Makefile
+++ b/arch/mips/ath79/Makefile
@@ -80,6 +80,7 @@ obj-$(CONFIG_ATH79_MACH_HORNET_UB) += ma
obj-$(CONFIG_ATH79_MACH_MC_MAC1200R) += mach-mc-mac1200r.o
obj-$(CONFIG_ATH79_MACH_MR12) += mach-mr12.o
obj-$(CONFIG_ATH79_MACH_MR16) += mach-mr16.o
+obj-$(CONFIG_ATH79_MACH_MR1750) += mach-mr1750.o
obj-$(CONFIG_ATH79_MACH_MR600) += mach-mr600.o
obj-$(CONFIG_ATH79_MACH_MR900) += mach-mr900.o
obj-$(CONFIG_ATH79_MACH_MYNET_N600) += mach-mynet-n600.o
--- a/arch/mips/ath79/machtypes.h
+++ b/arch/mips/ath79/machtypes.h
@@ -69,6 +69,7 @@ enum ath79_mach_type {
ATH79_MACH_HORNET_UB, /* ALFA Networks Hornet-UB */
ATH79_MACH_MR12, /* Cisco Meraki MR12 */
ATH79_MACH_MR16, /* Cisco Meraki MR16 */
+ ATH79_MACH_MR1750, /* OpenMesh MR1750 */
ATH79_MACH_MR600V2, /* OpenMesh MR600v2 */
ATH79_MACH_MR600, /* OpenMesh MR600 */
ATH79_MACH_MR900, /* OpenMesh MR900 */

38
target/linux/ar71xx/patches-3.18/815-MIPS-ath79-add-om5pac-support.patch Normal file
View File

@ -0,0 +1,38 @@
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
@@ -799,6 +799,15 @@ config ATH79_MACH_OM5P
select ATH79_DEV_M25P80
select ATH79_DEV_WMAC
+config ATH79_MACH_OM5P_AC
+ bool "OpenMesh OM5P-AC board support"
+ select SOC_QCA955X
+ select ATH79_DEV_AP9X_PCI if PCI
+ select ATH79_DEV_ETH
+ select ATH79_DEV_LEDS_GPIO
+ select ATH79_DEV_M25P80
+ select ATH79_DEV_WMAC
+
config ATH79_MACH_ONION_OMEGA
bool "ONION OMEGA support"
select SOC_AR933X
--- a/arch/mips/ath79/Makefile
+++ b/arch/mips/ath79/Makefile
@@ -100,6 +100,7 @@ obj-$(CONFIG_ATH79_MACH_MZK_W300NH) += m
obj-$(CONFIG_ATH79_MACH_NBG460N) += mach-nbg460n.o
obj-$(CONFIG_ATH79_MACH_OM2P) += mach-om2p.o
obj-$(CONFIG_ATH79_MACH_OM5P) += mach-om5p.o
+obj-$(CONFIG_ATH79_MACH_OM5P_AC) += mach-om5pac.o
obj-$(CONFIG_ATH79_MACH_ONION_OMEGA) += mach-onion-omega.o
obj-$(CONFIG_ATH79_MACH_PB42) += mach-pb42.o
obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
--- a/arch/mips/ath79/machtypes.h
+++ b/arch/mips/ath79/machtypes.h
@@ -95,6 +95,7 @@ enum ath79_mach_type {
ATH79_MACH_OM2P_LC, /* OpenMesh OM2P-LC */
ATH79_MACH_OM2Pv2, /* OpenMesh OM2Pv2 */
ATH79_MACH_OM2P, /* OpenMesh OM2P */
+ ATH79_MACH_OM5P_AC, /* OpenMesh OM5P-AC */
ATH79_MACH_OM5P_AN, /* OpenMesh OM5P-AN */
ATH79_MACH_OM5P, /* OpenMesh OM5P */
ATH79_MACH_ONION_OMEGA, /* ONION OMEGA */

39
target/linux/ar71xx/patches-3.18/816-MIPS-ath79-add-om5pacv-support.patch Normal file
View File

@ -0,0 +1,39 @@
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
@@ -808,6 +808,16 @@ config ATH79_MACH_OM5P_AC
select ATH79_DEV_M25P80
select ATH79_DEV_WMAC
+config ATH79_MACH_OM5P_ACv2
+ bool "OpenMesh OM5P-ACv2 board support"
+ select SOC_QCA955X
+ select ATH79_DEV_AP9X_PCI if PCI
+ select ATH79_DEV_ETH
+ select ATH79_DEV_GPIO_BUTTONS
+ select ATH79_DEV_LEDS_GPIO
+ select ATH79_DEV_M25P80
+ select ATH79_DEV_WMAC
+
config ATH79_MACH_ONION_OMEGA
bool "ONION OMEGA support"
select SOC_AR933X
--- a/arch/mips/ath79/Makefile
+++ b/arch/mips/ath79/Makefile
@@ -101,6 +101,7 @@ obj-$(CONFIG_ATH79_MACH_NBG460N) += mach
obj-$(CONFIG_ATH79_MACH_OM2P) += mach-om2p.o
obj-$(CONFIG_ATH79_MACH_OM5P) += mach-om5p.o
obj-$(CONFIG_ATH79_MACH_OM5P_AC) += mach-om5pac.o
+obj-$(CONFIG_ATH79_MACH_OM5P_ACv2) += mach-om5pacv2.o
obj-$(CONFIG_ATH79_MACH_ONION_OMEGA) += mach-onion-omega.o
obj-$(CONFIG_ATH79_MACH_PB42) += mach-pb42.o
obj-$(CONFIG_ATH79_MACH_PB44) += mach-pb44.o
--- a/arch/mips/ath79/machtypes.h
+++ b/arch/mips/ath79/machtypes.h
@@ -96,6 +96,7 @@ enum ath79_mach_type {
ATH79_MACH_OM2Pv2, /* OpenMesh OM2Pv2 */
ATH79_MACH_OM2P, /* OpenMesh OM2P */
ATH79_MACH_OM5P_AC, /* OpenMesh OM5P-AC */
+ ATH79_MACH_OM5P_ACv2, /* OpenMesh OM5P-ACv2 */
ATH79_MACH_OM5P_AN, /* OpenMesh OM5P-AN */
ATH79_MACH_OM5P, /* OpenMesh OM5P */
ATH79_MACH_ONION_OMEGA, /* ONION OMEGA */

10
target/linux/ar71xx/patches-3.18/817-MIPS-ath79-add-om2phsv3-support.patch Normal file
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@ -0,0 +1,10 @@
--- a/arch/mips/ath79/machtypes.h
+++ b/arch/mips/ath79/machtypes.h
@@ -88,6 +88,7 @@ enum ath79_mach_type {
ATH79_MACH_NBG460N, /* Zyxel NBG460N/550N/550NH */
ATH79_MACH_NBG6716, /* Zyxel NBG6716 */
ATH79_MACH_OM2P_HSv2, /* OpenMesh OM2P-HSv2 */
+ ATH79_MACH_OM2P_HSv3, /* OpenMesh OM2P-HSv3 */
ATH79_MACH_OM2P_HS, /* OpenMesh OM2P-HS */
ATH79_MACH_OM2P_LC, /* OpenMesh OM2P-LC */
ATH79_MACH_OM2Pv2, /* OpenMesh OM2Pv2 */

10
target/linux/ar71xx/patches-3.18/818-MIPS-ath79-add-mr1750v2-support.patch Normal file
View File

@ -0,0 +1,10 @@
--- a/arch/mips/ath79/machtypes.h
+++ b/arch/mips/ath79/machtypes.h
@@ -76,6 +76,7 @@ enum ath79_mach_type {
ATH79_MACH_MR12, /* Cisco Meraki MR12 */
ATH79_MACH_MR16, /* Cisco Meraki MR16 */
ATH79_MACH_MR1750, /* OpenMesh MR1750 */
+ ATH79_MACH_MR1750V2, /* OpenMesh MR1750v2 */
ATH79_MACH_MR600V2, /* OpenMesh MR600v2 */
ATH79_MACH_MR600, /* OpenMesh MR600 */
ATH79_MACH_MR900, /* OpenMesh MR900 */