ramips: update v3.10 patches

Sync the patches with those sent upstream for v3.12. Signed-off-by: John Crispin <blogic@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@37778 3c298f89-4303-0410-b956-a3cf2f4a3e73
2013-08-14 18:15:15 +00:00 · 2013-08-14 18:15:15 +00:00 · b9aed7de86
parent 4e0f16aad4
commit b9aed7de86
59 changed files with 1904 additions and 25807 deletions
--- a/target/linux/ramips/mt7620a/config-3.10
+++ b/target/linux/ramips/mt7620a/config-3.10
@ -155,7 +155,7 @@ CONFIG_SOC_MT7620=y
 # CONFIG_SOC_RT3883 is not set
 CONFIG_SPI=y
 CONFIG_SPI_MASTER=y
-CONFIG_SPI_RALINK=y
+CONFIG_SPI_RT2880=y
 CONFIG_SWCONFIG=y
 CONFIG_SYS_HAS_CPU_MIPS32_R1=y
 CONFIG_SYS_HAS_CPU_MIPS32_R2=y
--- a/target/linux/ramips/mt7620a/config-3.9
+++ b/target/linux/ramips/mt7620a/config-3.9
@ -1,173 +0,0 @@
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKEVT_RT3352=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_MT7620A_EVAL is not set
-# CONFIG_DTB_MT7620A_MT7610E_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_RALINK=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_MACH_CLKDEV=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM=m
-CONFIG_IMAGE_CMDLINE_HACK=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_M25PXX_USE_FAST_READ=y
-CONFIG_MDIO_BOARDINFO=y
-# CONFIG_MII is not set
-CONFIG_MIPS=y
-# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_MT_DISABLED=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_MT7620=y
-# CONFIG_MMC_SDHCI_PCI is not set
-CONFIG_MMC_SDHCI_PLTFM=y
-# CONFIG_MMC_TIFM_SD is not set
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_OF_PARTS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_UIMAGE_SPLIT=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK=y
-CONFIG_NET_RALINK_GSW_MT7620=y
-CONFIG_NET_RALINK_MDIO=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DEVICE=y
-# CONFIG_OF_DISPLAY_TIMING is not set
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-# CONFIG_OF_VIDEOMODE is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_RALINK=y
-# CONFIG_RALINK_ILL_ACC is not set
-CONFIG_RALINK_USBPHY=y
-CONFIG_RALINK_WDT=y
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-CONFIG_SOC_MT7620=y
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_RALINK=y
-CONFIG_SWCONFIG=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_UIDGID_CONVERTED=y
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_USB_OTG_UTILS=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZONE_DMA_FLAG=0
--- a/target/linux/ramips/patches-3.10/0001-MTD-m25p80-allow-loading-mtd-name-from-OF.patch
+++ b/target/linux/ramips/patches-3.10/0001-MTD-m25p80-allow-loading-mtd-name-from-OF.patch
@ -0,0 +1,39 @@
+From d11f6e47eb748f27ba325bd843cc88bae3ad0e8a Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 29 Jan 2013 21:11:55 +0100
+Subject: [PATCH 01/25] MTD: m25p80: allow loading mtd name from OF
+
+In accordance with the physmap flash we should honour the linux,mtd-name
+property when deciding what name the mtd device has.
+
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mtd/devices/m25p80.c |    5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
+@@ -926,10 +926,13 @@ static int m25p_probe(struct spi_device
+ 	unsigned			i;
+ 	struct mtd_part_parser_data	ppdata;
+ 	struct device_node __maybe_unused *np = spi->dev.of_node;
+	const char __maybe_unused	*of_mtd_name = NULL;
+ 
+ #ifdef CONFIG_MTD_OF_PARTS
+ 	if (!of_device_is_available(np))
+ 		return -ENODEV;
+	of_property_read_string(spi->dev.of_node,
+					"linux,mtd-name", &of_mtd_name);
+ #endif
+ 
+ 	/* Platform data helps sort out which chip type we have, as
+@@ -1005,6 +1008,8 @@ static int m25p_probe(struct spi_device
+ 
+ 	if (data && data->name)
+ 		flash->mtd.name = data->name;
+	else if (of_mtd_name)
+		flash->mtd.name = of_mtd_name;
+ 	else
+ 		flash->mtd.name = dev_name(&spi->dev);
+ 
--- a/target/linux/ramips/patches-3.10/0002-reset-Fix-compile-when-reset-RESET_CONTROLLER-is-not.patch
+++ b/target/linux/ramips/patches-3.10/0002-reset-Fix-compile-when-reset-RESET_CONTROLLER-is-not.patch
@ -0,0 +1,105 @@
+From 080f1a0c539180a88066fb004a8c31eefdf74161 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 9 Aug 2013 18:47:27 +0200
+Subject: [PATCH 02/25] reset: Fix compile when reset RESET_CONTROLLER is not
+ selected
+
+Drivers need to protect their reset api calls with #ifdef to avoid compile
+errors.
+
+This patch adds dummy wrappers in the same way that linux/of.h does it.
+
+Cc: linux-kernel@vger.kernel.org
+Cc: Philipp Zabel <p.zabel@pengutronix.de>
+Cc: Gabor Juhos <juhosg@openwrt.org>
+---
+ include/linux/reset-controller.h |   16 ++++++++++++++
+ include/linux/reset.h            |   43 ++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 59 insertions(+)
+
+--- a/include/linux/reset-controller.h
+++ b/include/linux/reset-controller.h
+@@ -45,7 +45,23 @@ struct reset_controller_dev {
+ 	unsigned int nr_resets;
+ };
+ 
+#if defined(CONFIG_RESET_CONTROLLER)
+
+ int reset_controller_register(struct reset_controller_dev *rcdev);
+ void reset_controller_unregister(struct reset_controller_dev *rcdev);
+ 
+#else
+
+static inline int reset_controller_register(struct reset_controller_dev *rcdev)
+{
+	return -ENOSYS;
+}
+
+void reset_controller_unregister(struct reset_controller_dev *rcdev)
+{
+
+}
+
+#endif
+
+ #endif
+--- a/include/linux/reset.h
+++ b/include/linux/reset.h
+@@ -1,9 +1,13 @@
+ #ifndef _LINUX_RESET_H_
+ #define _LINUX_RESET_H_
+ 
+#include <linux/err.h>
+
+ struct device;
+ struct reset_control;
+ 
+#if defined(CONFIG_RESET_CONTROLLER)
+
+ int reset_control_reset(struct reset_control *rstc);
+ int reset_control_assert(struct reset_control *rstc);
+ int reset_control_deassert(struct reset_control *rstc);
+@@ -14,4 +18,43 @@ struct reset_control *devm_reset_control
+ 
+ int device_reset(struct device *dev);
+ 
+#else /* CONFIG_RESET_CONTROLLER */
+
+static inline int reset_control_reset(struct reset_control *rstc)
+{
+	return -ENOSYS;
+}
+
+static inline int reset_control_assert(struct reset_control *rstc)
+{
+	return -ENOSYS;
+}
+
+static inline int reset_control_deassert(struct reset_control *rstc)
+{
+	return -ENOSYS;
+}
+
+static inline struct reset_control *reset_control_get(struct device *dev, const char *id)
+{
+	return ERR_PTR(-ENOSYS);
+}
+
+static inline void reset_control_put(struct reset_control *rstc)
+{
+
+}
+
+static inline struct reset_control *devm_reset_control_get(struct device *dev, const char *id)
+{
+	return ERR_PTR(-ENOSYS);
+}
+
+static inline int device_reset(struct device *dev)
+{
+	return -ENOSYS;
+}
+
+#endif
+
+ #endif
--- a/target/linux/ramips/patches-3.10/0003-DT-Add-documentation-for-rt2880-wdt.patch
+++ b/target/linux/ramips/patches-3.10/0003-DT-Add-documentation-for-rt2880-wdt.patch
@ -0,0 +1,39 @@
+From 8b87087423057f8a06423702f3035634d6e8cd73 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 28 Jul 2013 19:57:20 +0200
+Subject: [PATCH 03/25] DT: Add documentation for rt2880-wdt
+
+This document describes the binding of the watchdog core found ralink wireless
+SoC.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Cc: linux-watchdog@vger.kernel.org
+Cc: linux-mips@linux-mips.org
+Cc: devicetree-discuss@lists.ozlabs.org
+---
+ .../devicetree/bindings/watchdog/rt2880-wdt.txt     |   19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/watchdog/rt2880-wdt.txt
+
+--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/rt2880-wdt.txt
+@@ -0,0 +1,19 @@
+Ralink Watchdog Timers
+
+Required properties :
+- compatible: must be "ralink,rt2880-wdt"
+- reg: physical base address of the controller and length of the register range
+
+Optional properties :
+- interrupt-parent: phandle to the INTC device node
+- interrupts: Specify the INTC interrupt number
+
+Example:
+
+	watchdog@120 {
+		compatible = "ralink,rt2880-wdt";
+		reg = <0x120 0x10>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <1>;
+	};
--- a/target/linux/ramips/patches-3.10/0004-watchdog-MIPS-add-ralink-watchdog-driver.patch
+++ b/target/linux/ramips/patches-3.10/0004-watchdog-MIPS-add-ralink-watchdog-driver.patch
@ -1,29 +1,20 @@
-From f51b3b84af840ea52170ae6444ddee26ec74f7a9 Mon Sep 17 00:00:00 2001
+From 78046b68c1fc757162e32c83f59c3a94e794bf2e Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
-Date: Mon, 22 Apr 2013 23:23:07 +0200
-Subject: [PATCH 25/33] watchdog: adds ralink wdt
+Date: Sun, 28 Jul 2013 13:51:58 +0200
+Subject: [PATCH 04/25] watchdog: MIPS: add ralink watchdog driver

-Adds the watchdog driver for ralink SoC.
+Add a driver for the watchdog timer found on Ralink SoC

 Signed-off-by: John Crispin <blogic@openwrt.org>
+Cc: linux-watchdog@vger.kernel.org
+Cc: linux-mips@linux-mips.org
 ---
- arch/mips/ralink/mt7620.c     |    1 +
 drivers/watchdog/Kconfig      |    7 ++
 drivers/watchdog/Makefile     |    1 +
- drivers/watchdog/rt2880_wdt.c |  207 +++++++++++++++++++++++++++++++++++++++++
- 4 files changed, 216 insertions(+)
+ drivers/watchdog/rt2880_wdt.c |  208 +++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 216 insertions(+)
 create mode 100644 drivers/watchdog/rt2880_wdt.c

--- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -182,6 +182,7 @@ void __init ralink_clk_init(void)
- 
- 	ralink_clk_add("cpu", cpu_rate);
- 	ralink_clk_add("10000100.timer", 40000000);
-+	ralink_clk_add("10000120.watchdog", 40000000);
- 	ralink_clk_add("10000500.uart", 40000000);
- 	ralink_clk_add("10000b00.spi", 40000000);
- 	ralink_clk_add("10000c00.uartlite", 40000000);
 --- a/drivers/watchdog/Kconfig
 +++ b/drivers/watchdog/Kconfig
@@ -1104,6 +1104,13 @@ config LANTIQ_WDT
@ -52,7 +43,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 
 --- /dev/null
 +++ b/drivers/watchdog/rt2880_wdt.c
-@@ -0,0 +1,207 @@
+@@ -0,0 +1,208 @@
 +/*
 + * Ralink RT288x/RT3xxx/MT76xx built-in hardware watchdog timer
 + *
@ -120,7 +111,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +
 +static int rt288x_wdt_ping(struct watchdog_device *w)
 +{
-+        rt_wdt_w32(TIMER_REG_TMR1LOAD, w->timeout * rt288x_wdt_freq);
+	rt_wdt_w32(TIMER_REG_TMR1LOAD, w->timeout * rt288x_wdt_freq);
 +
 +	return 0;
 +}
@ -199,7 +190,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	int ret;
 +
 +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+        rt288x_wdt_base = devm_request_and_ioremap(&pdev->dev, res);
+	rt288x_wdt_base = devm_request_and_ioremap(&pdev->dev, res);
 +	if (IS_ERR(rt288x_wdt_base))
 +		return PTR_ERR(rt288x_wdt_base);
 +
@ -214,7 +205,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	rt288x_wdt_dev.dev = &pdev->dev;
 +	rt288x_wdt_dev.bootstatus = rt288x_wdt_bootcause();
 +
-+	rt288x_wdt_dev.timeout = rt288x_wdt_dev.max_timeout = (0xfffful / rt288x_wdt_freq);
+	rt288x_wdt_dev.max_timeout = (0xfffful / rt288x_wdt_freq);
+	rt288x_wdt_dev.timeout = rt288x_wdt_dev.max_timeout;
 +
 +	watchdog_set_nowayout(&rt288x_wdt_dev, nowayout);
 +
--- a/target/linux/ramips/patches-3.10/0005-DT-Add-documentation-for-gpio-ralink.patch
+++ b/target/linux/ramips/patches-3.10/0005-DT-Add-documentation-for-gpio-ralink.patch
@ -0,0 +1,59 @@
+From ad68c2865b360f1b637432b4cbcaaf101d2687b9 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 28 Jul 2013 19:45:30 +0200
+Subject: [PATCH 05/25] DT: Add documentation for gpio-ralink
+
+Describe gpio-ralink binding.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: devicetree@vger.kernel.org
+Cc: linux-gpio@vger.kernel.org
+---
+ .../devicetree/bindings/gpio/gpio-ralink.txt       |   40 ++++++++++++++++++++
+ 1 file changed, 40 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/gpio/gpio-ralink.txt
+
+--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-ralink.txt
+@@ -0,0 +1,40 @@
+Ralink SoC GPIO controller bindings
+
+Required properties:
+- compatible:
+  - "ralink,rt2880-gpio" for Ralink controllers
+- #gpio-cells : Should be two.
+  - first cell is the pin number
+  - second cell is used to specify optional parameters (unused)
+- gpio-controller : Marks the device node as a GPIO controller
+- reg : Physical base address and length of the controller's registers
+- interrupt-parent: phandle to the INTC device node
+- interrupts : Specify the INTC interrupt number
+- ralink,num-gpios : Specify the number of GPIOs
+- ralink,register-map : The register layout depends on the GPIO bank and actual
+		SoC type. Register offsets need to be in this order.
+		[ INT, EDGE, RENA, FENA, DATA, DIR, POL, SET, RESET, TOGGLE ]
+
+Optional properties:
+- ralink,gpio-base : Specify the GPIO chips base number
+
+Example:
+
+	gpio0: gpio@600 {
+		compatible = "ralink,rt5350-gpio", "ralink,rt2880-gpio";
+
+		#gpio-cells = <2>;
+		gpio-controller;
+
+		reg = <0x600 0x34>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <6>;
+
+		ralink,gpio-base = <0>;
+		ralink,num-gpios = <24>;
+		ralink,register-map = [ 00 04 08 0c
+				20 24 28 2c
+				30 34 ];
+
+	};
--- a/target/linux/ramips/patches-3.10/0006-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch
+++ b/target/linux/ramips/patches-3.10/0006-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch
@ -1,27 +1,27 @@
-From 3af8b2904d2d4758f88bc96c7c9ecff4a708347f Mon Sep 17 00:00:00 2001
+From 55833373cf527dc94bc6c63b68d0f39591667a5d Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
-Date: Sun, 14 Jul 2013 23:17:27 +0200
-Subject: [PATCH 23/33] GPIO: MIPS: ralink: adds ralink gpio support
+Date: Sun, 28 Jul 2013 14:00:25 +0200
+Subject: [PATCH 06/25] GPIO: MIPS: ralink: add gpio driver for ralink SoC

 Add gpio driver for Ralink SoC. This driver makes the gpio core on
 RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.

 Signed-off-by: John Crispin <blogic@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: linux-gpio@vger.kernel.org
 ---
 arch/mips/Kconfig                        |    1 +
 arch/mips/include/asm/mach-ralink/gpio.h |   24 +++
 drivers/gpio/Kconfig                     |    6 +
 drivers/gpio/Makefile                    |    1 +
- drivers/gpio/gpio-ralink.c               |  326 ++++++++++++++++++++++++++++++
- 5 files changed, 358 insertions(+)
+ drivers/gpio/gpio-ralink.c               |  337 ++++++++++++++++++++++++++++++
+ 5 files changed, 369 insertions(+)
 create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
 create mode 100644 drivers/gpio/gpio-ralink.c

-Index: linux-3.10.3/arch/mips/Kconfig
-===================================================================
--- linux-3.10.3.orig/arch/mips/Kconfig	2013-07-27 10:24:36.376236698 +0200
-+++ linux-3.10.3/arch/mips/Kconfig	2013-07-27 11:11:09.804861224 +0200
-@@ -443,6 +443,7 @@
+--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
+@@ -443,6 +443,7 @@ config RALINK
 	select SYS_HAS_EARLY_PRINTK
 	select HAVE_MACH_CLKDEV
 	select CLKDEV_LOOKUP
@ -29,10 +29,8 @@ Index: linux-3.10.3/arch/mips/Kconfig
 
 config SGI_IP22
 	bool "SGI IP22 (Indy/Indigo2)"
-Index: linux-3.10.3/arch/mips/include/asm/mach-ralink/gpio.h
-===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-3.10.3/arch/mips/include/asm/mach-ralink/gpio.h	2013-07-27 10:24:40.532236797 +0200
+--- /dev/null
+++ b/arch/mips/include/asm/mach-ralink/gpio.h
@@ -0,0 +1,24 @@
 +/*
 + *  Ralink SoC GPIO API support
@ -58,11 +56,9 @@ Index: linux-3.10.3/arch/mips/include/asm/mach-ralink/gpio.h
 +#define gpio_to_irq	__gpio_to_irq
 +
 +#endif /* __ASM_MACH_RALINK_GPIO_H */
-Index: linux-3.10.3/drivers/gpio/Kconfig
-===================================================================
--- linux-3.10.3.orig/drivers/gpio/Kconfig	2013-07-26 00:16:45.000000000 +0200
-+++ linux-3.10.3/drivers/gpio/Kconfig	2013-07-27 10:24:40.532236797 +0200
-@@ -209,6 +209,12 @@
+--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
+@@ -209,6 +209,12 @@ config GPIO_RCAR
 	help
 	  Say yes here to support GPIO on Renesas R-Car SoCs.
 
@ -75,11 +71,9 @@ Index: linux-3.10.3/drivers/gpio/Kconfig
 config GPIO_SPEAR_SPICS
 	bool "ST SPEAr13xx SPI Chip Select as GPIO support"
 	depends on PLAT_SPEAR
-Index: linux-3.10.3/drivers/gpio/Makefile
-===================================================================
--- linux-3.10.3.orig/drivers/gpio/Makefile	2013-07-26 00:16:45.000000000 +0200
-+++ linux-3.10.3/drivers/gpio/Makefile	2013-07-27 10:24:40.536236797 +0200
-@@ -56,6 +56,7 @@
+--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
+@@ -56,6 +56,7 @@ obj-$(CONFIG_GPIO_PCF857X)	+= gpio-pcf85
 obj-$(CONFIG_GPIO_PCH)		+= gpio-pch.o
 obj-$(CONFIG_GPIO_PL061)	+= gpio-pl061.o
 obj-$(CONFIG_GPIO_PXA)		+= gpio-pxa.o
@ -87,11 +81,9 @@ Index: linux-3.10.3/drivers/gpio/Makefile
 obj-$(CONFIG_GPIO_RC5T583)	+= gpio-rc5t583.o
 obj-$(CONFIG_GPIO_RDC321X)	+= gpio-rdc321x.o
 obj-$(CONFIG_GPIO_RCAR)		+= gpio-rcar.o
-Index: linux-3.10.3/drivers/gpio/gpio-ralink.c
-===================================================================
--- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-3.10.3/drivers/gpio/gpio-ralink.c	2013-07-27 11:04:07.668851107 +0200
-@@ -0,0 +1,324 @@
+--- /dev/null
+++ b/drivers/gpio/gpio-ralink.c
+@@ -0,0 +1,337 @@
 +/*
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License version 2 as published
@ -223,10 +215,13 @@ Index: linux-3.10.3/drivers/gpio/gpio-ralink.c
 +
 +	for (i = 0; i < irq_map_count; i++) {
 +		struct irq_domain *domain = irq_map[i];
-+		struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) domain->host_data;
-+		unsigned long pending = rt_gpio_r32(rg, GPIO_REG_INT);
+		struct ralink_gpio_chip *rg;
+		unsigned long pending;
 +		int bit;
 +
+		rg = (struct ralink_gpio_chip *) domain->host_data;
+		pending = rt_gpio_r32(rg, GPIO_REG_INT);
+
 +		for_each_set_bit(bit, &pending, rg->chip.ngpio) {
 +			u32 map = irq_find_mapping(domain, bit);
 +			generic_handle_irq(map);
@ -237,9 +232,12 @@ Index: linux-3.10.3/drivers/gpio/gpio-ralink.c
 +
 +static void ralink_gpio_irq_unmask(struct irq_data *d)
 +{
-+	struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
-+	u32 val = rt_gpio_r32(rg, GPIO_REG_RENA);
+	struct ralink_gpio_chip *rg;
 +	unsigned long flags;
+	u32 val;
+
+	rg = (struct ralink_gpio_chip *) d->domain->host_data;
+	val = rt_gpio_r32(rg, GPIO_REG_RENA);
 +
 +	spin_lock_irqsave(&rg->lock, flags);
 +	rt_gpio_w32(rg, GPIO_REG_RENA, val | (BIT(d->hwirq) & rg->rising));
@ -249,9 +247,12 @@ Index: linux-3.10.3/drivers/gpio/gpio-ralink.c
 +
 +static void ralink_gpio_irq_mask(struct irq_data *d)
 +{
-+	struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
-+	u32 val = rt_gpio_r32(rg, GPIO_REG_RENA);
+	struct ralink_gpio_chip *rg;
 +	unsigned long flags;
+	u32 val;
+
+	rg = (struct ralink_gpio_chip *) d->domain->host_data;
+	val = rt_gpio_r32(rg, GPIO_REG_RENA);
 +
 +	spin_lock_irqsave(&rg->lock, flags);
 +	rt_gpio_w32(rg, GPIO_REG_FENA, val & ~BIT(d->hwirq));
@ -261,9 +262,11 @@ Index: linux-3.10.3/drivers/gpio/gpio-ralink.c
 +
 +static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
 +{
-+	struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
+	struct ralink_gpio_chip *rg;
 +	u32 mask = BIT(d->hwirq);
 +
+	rg = (struct ralink_gpio_chip *) d->domain->host_data;
+
 +	if (type == IRQ_TYPE_PROBE) {
 +		if ((rg->rising | rg->falling) & mask)
 +			return 0;
@ -305,7 +308,8 @@ Index: linux-3.10.3/drivers/gpio/gpio-ralink.c
 +	.map = gpio_map,
 +};
 +
-+static void ralink_gpio_irq_init(struct device_node *np, struct ralink_gpio_chip *rg)
+static void ralink_gpio_irq_init(struct device_node *np,
+				 struct ralink_gpio_chip *rg)
 +{
 +	if (irq_map_count >= MAP_MAX)
 +		return;
@ -314,7 +318,8 @@ Index: linux-3.10.3/drivers/gpio/gpio-ralink.c
 +	if (!rg->irq)
 +		return;
 +
-+	rg->domain = irq_domain_add_linear(np, rg->chip.ngpio, &irq_domain_ops, rg);
+	rg->domain = irq_domain_add_linear(np, rg->chip.ngpio,
+					   &irq_domain_ops, rg);
 +	if (!rg->domain) {
 +		dev_err(rg->chip.dev, "irq_domain_add_linear failed\n");
 +		return;
--- a/target/linux/ramips/patches-3.10/0007-serial-MIPS-lantiq-add-clk_enable-call-to-driver.patch
+++ b/target/linux/ramips/patches-3.10/0007-serial-MIPS-lantiq-add-clk_enable-call-to-driver.patch
@ -0,0 +1,25 @@
+From 0b78522f6e136fa5901e72cdbf4a44693d100826 Mon Sep 17 00:00:00 2001
+From: Thomas Langer <thomas.langer@lantiq.com>
+Date: Sun, 28 Jul 2013 14:44:44 +0200
+Subject: [PATCH 07/25] serial: MIPS: lantiq: add clk_enable() call to driver
+
+Enable the clock if one is present when setting up the console.
+
+Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
+Acked-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/tty/serial/lantiq.c |    3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/tty/serial/lantiq.c
+++ b/drivers/tty/serial/lantiq.c
+@@ -636,6 +636,9 @@ lqasc_console_setup(struct console *co,
+ 
+ 	port = &ltq_port->port;
+ 
+	if (!IS_ERR(ltq_port->clk))
+		clk_enable(ltq_port->clk);
+
+ 	port->uartclk = clk_get_rate(ltq_port->fpiclk);
+ 
+ 	if (options)
--- a/target/linux/ramips/patches-3.10/0008-serial-MIPS-lantiq-fix-clock-error-check.patch
+++ b/target/linux/ramips/patches-3.10/0008-serial-MIPS-lantiq-fix-clock-error-check.patch
@ -0,0 +1,32 @@
+From d94da02421c14fa9295feb218cd45fc01d0f470b Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 8 Aug 2013 17:19:42 +0200
+Subject: [PATCH 08/25] serial: MIPS: lantiq: fix clock error check
+
+The clk should be checked with the proper IS_ERR() api before accessing it.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/tty/serial/lantiq.c |    4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/tty/serial/lantiq.c
+++ b/drivers/tty/serial/lantiq.c
+@@ -318,7 +318,7 @@ lqasc_startup(struct uart_port *port)
+ 	struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
+ 	int retval;
+ 
+-	if (ltq_port->clk)
+	if (!IS_ERR(ltq_port->clk))
+ 		clk_enable(ltq_port->clk);
+ 	port->uartclk = clk_get_rate(ltq_port->fpiclk);
+ 
+@@ -386,7 +386,7 @@ lqasc_shutdown(struct uart_port *port)
+ 		port->membase + LTQ_ASC_RXFCON);
+ 	ltq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
+ 		port->membase + LTQ_ASC_TXFCON);
+-	if (ltq_port->clk)
+	if (!IS_ERR(ltq_port->clk))
+ 		clk_disable(ltq_port->clk);
+ }
+ 
--- a/target/linux/ramips/patches-3.10/0009-MIPS-ralink-add-support-for-reset-controller-API.patch
+++ b/target/linux/ramips/patches-3.10/0009-MIPS-ralink-add-support-for-reset-controller-API.patch
@ -0,0 +1,126 @@
+From 4e694014a11a407e309f62c7daade545ba71dcf1 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 28 Jul 2013 13:54:22 +0200
+Subject: [PATCH 09/25] MIPS: ralink: add support for reset-controller API
+
+Add a helper for reseting different devices on the SoC.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/Kconfig         |    1 +
+ arch/mips/ralink/common.h |    2 ++
+ arch/mips/ralink/of.c     |    3 +++
+ arch/mips/ralink/reset.c  |   62 +++++++++++++++++++++++++++++++++++++++++++++
+ 4 files changed, 68 insertions(+)
+
+--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
+@@ -373,6 +373,7 @@ config MACH_VR41XX
+ 	select CSRC_R4K
+ 	select SYS_HAS_CPU_VR41XX
+ 	select ARCH_REQUIRE_GPIOLIB
+	select ARCH_HAS_RESET_CONTROLLER
+ 
+ config NXP_STB220
+ 	bool "NXP STB220 board"
+--- a/arch/mips/ralink/common.h
+++ b/arch/mips/ralink/common.h
+@@ -46,6 +46,8 @@ extern void ralink_of_remap(void);
+ extern void ralink_clk_init(void);
+ extern void ralink_clk_add(const char *dev, unsigned long rate);
+ 
+extern void ralink_rst_init(void);
+
+ extern void prom_soc_init(struct ralink_soc_info *soc_info);
+ 
+ __iomem void *plat_of_remap_node(const char *node);
+--- a/arch/mips/ralink/of.c
+++ b/arch/mips/ralink/of.c
+@@ -110,6 +110,9 @@ static int __init plat_of_setup(void)
+ 	if (of_platform_populate(NULL, of_ids, NULL, NULL))
+ 		panic("failed to populate DT\n");
+ 
+	/* make sure ithat the reset controller is setup early */
+	ralink_rst_init();
+
+ 	return 0;
+ }
+ 
+--- a/arch/mips/ralink/reset.c
+++ b/arch/mips/ralink/reset.c
+@@ -10,6 +10,8 @@
+ 
+ #include <linux/pm.h>
+ #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/reset-controller.h>
+ 
+ #include <asm/reboot.h>
+ 
+@@ -19,6 +21,66 @@
+ #define SYSC_REG_RESET_CTRL     0x034
+ #define RSTCTL_RESET_SYSTEM     BIT(0)
+ 
+static int ralink_assert_device(struct reset_controller_dev *rcdev,
+				unsigned long id)
+{
+	u32 val;
+
+	if (id < 8)
+		return -1;
+
+	val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
+	val |= BIT(id);
+	rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
+
+	return 0;
+}
+
+static int ralink_deassert_device(struct reset_controller_dev *rcdev,
+				  unsigned long id)
+{
+	u32 val;
+
+	if (id < 8)
+		return -1;
+
+	val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
+	val &= ~BIT(id);
+	rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
+
+	return 0;
+}
+
+static int ralink_reset_device(struct reset_controller_dev *rcdev,
+			       unsigned long id)
+{
+	ralink_assert_device(rcdev, id);
+	return ralink_deassert_device(rcdev, id);
+}
+
+static struct reset_control_ops reset_ops = {
+	.reset = ralink_reset_device,
+	.assert = ralink_assert_device,
+	.deassert = ralink_deassert_device,
+};
+
+static struct reset_controller_dev reset_dev = {
+	.ops			= &reset_ops,
+	.owner			= THIS_MODULE,
+	.nr_resets		= 32,
+	.of_reset_n_cells	= 1,
+};
+
+void ralink_rst_init(void)
+{
+	reset_dev.of_node = of_find_compatible_node(NULL, NULL,
+						"ralink,rt2880-reset");
+	if (!reset_dev.of_node)
+		pr_err("Failed to find reset controller node");
+	else
+		reset_controller_register(&reset_dev);
+}
+
+ static void ralink_restart(char *command)
+ {
+ 	local_irq_disable();
--- a/target/linux/ramips/patches-3.10/0010-MIPS-ralink-add-support-for-periodic-timer-irq.patch
+++ b/target/linux/ramips/patches-3.10/0010-MIPS-ralink-add-support-for-periodic-timer-irq.patch
@ -1,15 +1,15 @@
-From 298e990777004a6a72b1c95af5a2cd984c56135d Mon Sep 17 00:00:00 2001
+From 1cd8a1dc8e942bd130dc40ff801f37ad296495e3 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
-Date: Sat, 23 Mar 2013 19:44:41 +0100
-Subject: [PATCH 03/33] MIPS: ralink: add support for periodic timer irq
+Date: Sun, 28 Jul 2013 13:41:04 +0200
+Subject: [PATCH 10/25] MIPS: ralink: add support for periodic timer irq

 Adds a driver for the periodic timer found on Ralink SoC.

 Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
 arch/mips/ralink/Makefile |    2 +-
- arch/mips/ralink/timer.c  |  192 +++++++++++++++++++++++++++++++++++++++++++++
- 2 files changed, 193 insertions(+), 1 deletion(-)
+ arch/mips/ralink/timer.c  |  185 +++++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 186 insertions(+), 1 deletion(-)
 create mode 100644 arch/mips/ralink/timer.c

 --- a/arch/mips/ralink/Makefile
@ -18,14 +18,14 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 
-obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o
-+obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o timer.o
+-obj-y := prom.o of.o reset.o clk.o irq.o
+obj-y := prom.o of.o reset.o clk.o irq.o timer.o
 
 obj-$(CONFIG_SOC_RT288X) += rt288x.o
 obj-$(CONFIG_SOC_RT305X) += rt305x.o
 --- /dev/null
 +++ b/arch/mips/ralink/timer.c
-@@ -0,0 +1,192 @@
+@@ -0,0 +1,185 @@
 +/*
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms of the GNU General Public License version 2 as published
@ -142,11 +142,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	struct rt_timer *rt;
 +	struct clk *clk;
 +
-+	if (!res) {
-+		dev_err(&pdev->dev, "no memory resource found\n");
-+		return -EINVAL;
-+	}
-+
 +	rt = devm_kzalloc(&pdev->dev, sizeof(*rt), GFP_KERNEL);
 +	if (!rt) {
 +		dev_err(&pdev->dev, "failed to allocate memory\n");
@ -160,10 +155,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	}
 +
 +	rt->membase = devm_request_and_ioremap(&pdev->dev, res);
-+	if (!rt->membase) {
-+		dev_err(&pdev->dev, "failed to ioremap\n");
-+		return -ENOMEM;
-+	}
+	if (IS_ERR(rt->membase))
+		return PTR_ERR(rt->membase);
 +
 +	clk = devm_clk_get(&pdev->dev, NULL);
 +	if (IS_ERR(clk)) {
--- a/target/linux/ramips/patches-3.10/0011-MIPS-ralink-add-support-for-systick-timer-found-on-n.patch
+++ b/target/linux/ramips/patches-3.10/0011-MIPS-ralink-add-support-for-systick-timer-found-on-n.patch
@ -1,73 +1,50 @@
-From 10cb446ac01be52c49b5143c8601524bc4f53051 Mon Sep 17 00:00:00 2001
+From 3b511d972b556712f89ccc68825c0ec8f398dc5c Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
-Date: Sun, 14 Jul 2013 23:11:05 +0200
-Subject: [PATCH 22/33] clocksource: MIPS: ralink: add support for systick
- timer found on newer ralink SoC
+Date: Sun, 28 Jul 2013 13:46:09 +0200
+Subject: [PATCH 11/25] MIPS: ralink: add support for systick timer found on
+ newer ralink SoC
+
+Newer Ralink SoC (MT7620x and RT5350) have a 50KHz clock that runs independent
+of the SoC master clock. If we want to automatic frequency scaling to work we
+need to use the systick timer as the clock source.

 Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
- arch/mips/ralink/Kconfig          |    2 +
- arch/mips/ralink/clk.c            |    1 +
- drivers/clocksource/Kconfig       |    6 ++
- drivers/clocksource/Makefile      |    1 +
- drivers/clocksource/cevt-rt3352.c |  162 +++++++++++++++++++++++++++++++++++++
- 5 files changed, 172 insertions(+)
- create mode 100644 drivers/clocksource/cevt-rt3352.c
+ arch/mips/ralink/Kconfig       |    7 ++
+ arch/mips/ralink/Makefile      |    2 +
+ arch/mips/ralink/cevt-rt3352.c |  145 ++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 154 insertions(+)
+ create mode 100644 arch/mips/ralink/cevt-rt3352.c

 --- a/arch/mips/ralink/Kconfig
 +++ b/arch/mips/ralink/Kconfig
-@@ -15,6 +15,7 @@ choice
- 		select USB_ARCH_HAS_HCD
- 		select USB_ARCH_HAS_OHCI
- 		select USB_ARCH_HAS_EHCI
-+		select CLKEVT_RT3352
- 
- 	config SOC_RT3883
- 		bool "RT3883"
-@@ -27,6 +28,7 @@ choice
- 		select USB_ARCH_HAS_OHCI
- 		select USB_ARCH_HAS_EHCI
- 		select HW_HAS_PCI
-+		select CLKEVT_RT3352
- 
- endchoice
- 
--- a/arch/mips/ralink/clk.c
-+++ b/arch/mips/ralink/clk.c
-@@ -69,4 +69,5 @@ void __init plat_time_init(void)
- 	pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
- 	mips_hpt_frequency = clk_get_rate(clk) / 2;
- 	clk_put(clk);
-+	clocksource_of_init();
- }
--- a/drivers/clocksource/Kconfig
-+++ b/drivers/clocksource/Kconfig
-@@ -7,6 +7,12 @@ config CLKSRC_I8253
- config CLKEVT_I8253
- 	bool
+@@ -1,5 +1,12 @@
+ if RALINK
 
 +config CLKEVT_RT3352
 +	bool
-+	depends on MIPS && RALINK
+	depends on SOC_RT305X || SOC_MT7620
+	default y
 +	select CLKSRC_OF
 +	select CLKSRC_MMIO
 +
- config I8253_LOCK
- 	bool
+ choice
+ 	prompt "Ralink SoC selection"
+ 	default SOC_RT305X
+--- a/arch/mips/ralink/Makefile
+++ b/arch/mips/ralink/Makefile
+@@ -8,6 +8,8 @@
 
--- a/drivers/clocksource/Makefile
-+++ b/drivers/clocksource/Makefile
-@@ -10,6 +10,7 @@ obj-$(CONFIG_SH_TIMER_TMU)	+= sh_tmu.o
- obj-$(CONFIG_EM_TIMER_STI)	+= em_sti.o
- obj-$(CONFIG_CLKBLD_I8253)	+= i8253.o
- obj-$(CONFIG_CLKSRC_MMIO)	+= mmio.o
-+obj-$(CONFIG_CLKEVT_RT3352)	+= cevt-rt3352.o
- obj-$(CONFIG_DW_APB_TIMER)	+= dw_apb_timer.o
- obj-$(CONFIG_DW_APB_TIMER_OF)	+= dw_apb_timer_of.o
- obj-$(CONFIG_CLKSRC_NOMADIK_MTU)	+= nomadik-mtu.o
+ obj-y := prom.o of.o reset.o clk.o irq.o timer.o
+ 
+obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
+
+ obj-$(CONFIG_SOC_RT288X) += rt288x.o
+ obj-$(CONFIG_SOC_RT305X) += rt305x.o
+ obj-$(CONFIG_SOC_RT3883) += rt3883.o
 --- /dev/null
-+++ b/drivers/clocksource/cevt-rt3352.c
-@@ -0,0 +1,162 @@
+++ b/arch/mips/ralink/cevt-rt3352.c
+@@ -0,0 +1,145 @@
 +/*
 + * This file is subject to the terms and conditions of the GNU General Public
 + * License.  See the file "COPYING" in the main directory of this archive
@ -81,23 +58,23 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#include <linux/interrupt.h>
 +#include <linux/reset.h>
 +#include <linux/init.h>
+#include <linux/time.h>
 +#include <linux/of.h>
 +#include <linux/of_irq.h>
 +#include <linux/of_address.h>
 +
 +#include <asm/mach-ralink/ralink_regs.h>
-+#include <asm/time.h>
 +
-+#define SYSTICK_FREQ	(50 * 1000)
+#define SYSTICK_FREQ		(50 * 1000)
 +
-+#define SYSTICK_CONFIG	0x00
-+#define SYSTICK_COMPARE	0x04
-+#define SYSTICK_COUNT	0x08
+#define SYSTICK_CONFIG		0x00
+#define SYSTICK_COMPARE		0x04
+#define SYSTICK_COUNT		0x08
 +
 +/* route systick irq to mips irq 7 instead of the r4k-timer */
-+#define CFG_EXT_STK_EN	0x2
+#define CFG_EXT_STK_EN		0x2
 +/* enable the counter */
-+#define CFG_CNT_EN	0x1
+#define CFG_CNT_EN		0x1
 +
 +struct systick_device {
 +	void __iomem *membase;
@ -112,9 +89,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +static int systick_next_event(unsigned long delta,
 +				struct clock_event_device *evt)
 +{
-+	struct systick_device *sdev = container_of(evt, struct systick_device, dev);
+	struct systick_device *sdev;
 +	u32 count;
 +
+	sdev = container_of(evt, struct systick_device, dev);
 +	count = ioread32(sdev->membase + SYSTICK_COUNT);
 +	count = (count + delta) % SYSTICK_FREQ;
 +	iowrite32(count + delta, sdev->membase + SYSTICK_COMPARE);
@ -138,7 +116,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +
 +static struct systick_device systick = {
 +	.dev = {
-+		/* cevt-r4k uses 300, make sure systick gets used if available */
+		/*
+		 * cevt-r4k uses 300, make sure systick
+		 * gets used if available
+		 */
 +		.rating		= 310,
 +		.features	= CLOCK_EVT_FEAT_ONESHOT,
 +		.set_next_event	= systick_next_event,
@ -153,47 +134,25 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	.dev_id = &systick.dev,
 +};
 +
-+/* ugly hack */
-+#ifdef CONFIG_SOC_MT7620
-+
-+#define CLK_LUT_CFG	0x40
-+#define SLEEP_EN	BIT(31)
-+
-+static inline void mt7620_freq_scaling(struct systick_device *sdev, int status)
-+{
-+	if (sdev->freq_scale == status)
-+		return;
-+
-+	sdev->freq_scale = status;
-+
-+	pr_info("%s: %s autosleep mode\n", systick.dev.name, (status) ? ("enable") : ("disable"));
-+	if (status)
-+		rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) | SLEEP_EN, CLK_LUT_CFG);
-+	else
-+		rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) & ~SLEEP_EN, CLK_LUT_CFG);
-+}
-+#else
-+static inline void mt7620_freq_scaling(struct systick_device *sdev, int status) {}
-+#endif
-+
 +static void systick_set_clock_mode(enum clock_event_mode mode,
 +				struct clock_event_device *evt)
 +{
-+	struct systick_device *sdev = container_of(evt, struct systick_device, dev);
+	struct systick_device *sdev;
+
+	sdev = container_of(evt, struct systick_device, dev);
 +
 +	switch (mode) {
 +	case CLOCK_EVT_MODE_ONESHOT:
 +		if (!sdev->irq_requested)
 +			setup_irq(systick.dev.irq, &systick_irqaction);
-+		mt7620_freq_scaling(sdev, 1);
 +		sdev->irq_requested = 1;
-+		iowrite32(CFG_EXT_STK_EN | CFG_CNT_EN, systick.membase + SYSTICK_CONFIG);
+		iowrite32(CFG_EXT_STK_EN | CFG_CNT_EN,
+				systick.membase + SYSTICK_CONFIG);
 +		break;
 +
 +	case CLOCK_EVT_MODE_SHUTDOWN:
 +		if (sdev->irq_requested)
 +			free_irq(systick.dev.irq, &systick_irqaction);
-+		mt7620_freq_scaling(sdev, 0);
 +		sdev->irq_requested = 0;
 +		iowrite32(0, systick.membase + SYSTICK_CONFIG);
 +		break;
@ -207,26 +166,27 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +static void __init ralink_systick_init(struct device_node *np)
 +{
 +	systick.membase = of_iomap(np, 0);
-+	if (!systick.membase) {
-+		pr_err("%s: of_iomap failed", np->name);
+	if (!systick.membase)
+		return;
+
+	systick_irqaction.name = np->name;
+	systick.dev.name = np->name;
+	clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60);
+	systick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev);
+	systick.dev.min_delta_ns = clockevent_delta2ns(0x3, &systick.dev);
+	systick.dev.irq = irq_of_parse_and_map(np, 0);
+	if (!systick.dev.irq) {
+		pr_err("%s: request_irq failed", np->name);
 +		return;
 +	}
 +
 +	clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,
 +			SYSTICK_FREQ, 301, 16, clocksource_mmio_readl_up);
 +
-+	systick_irqaction.name = np->name;
-+	systick.dev.name = np->name;
-+	clockevent_set_clock(&systick.dev, SYSTICK_FREQ);
-+	systick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev);
-+	systick.dev.min_delta_ns = clockevent_delta2ns(0x3, &systick.dev);
-+	systick.dev.irq = irq_of_parse_and_map(np, 0);
-+	if (!systick.dev.irq)
-+		panic("%s: request_irq failed", np->name);
-+
 +	clockevents_register_device(&systick.dev);
 +
-+	pr_info("%s: runing - mult: %d, shift: %d\n", np->name, systick.dev.mult, systick.dev.shift);
+	pr_info("%s: runing - mult: %d, shift: %d\n",
+			np->name, systick.dev.mult, systick.dev.shift);
 +}
 +
 +CLOCKSOURCE_OF_DECLARE(systick, "ralink,cevt-systick", ralink_systick_init);
--- a/target/linux/ramips/patches-3.10/0012-MIPS-ralink-probe-clocksources-from-OF.patch
+++ b/target/linux/ramips/patches-3.10/0012-MIPS-ralink-probe-clocksources-from-OF.patch
@ -0,0 +1,21 @@
+From c4d6a957efb0c8d919302598ae547bde05137461 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 28 Jul 2013 13:48:39 +0200
+Subject: [PATCH 12/25] MIPS: ralink: probe clocksources from OF
+
+Make plat_time_init() call clocksource_of_init() allowing the systick cevt
+to load.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/clk.c |    1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/mips/ralink/clk.c
+++ b/arch/mips/ralink/clk.c
+@@ -69,4 +69,5 @@ void __init plat_time_init(void)
+ 	pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
+ 	mips_hpt_frequency = clk_get_rate(clk) / 2;
+ 	clk_put(clk);
+	clocksource_of_init();
+ }
--- a/target/linux/ramips/patches-3.10/0005-MIPS-ralink-make-mt7620-ram-detect-verbose.patch
+++ b/target/linux/ramips/patches-3.10/0005-MIPS-ralink-make-mt7620-ram-detect-verbose.patch
@ -1,7 +1,7 @@
-From 3f6b346e1dd83c4f43d94aefa0520ffdfafd5f0b Mon Sep 17 00:00:00 2001
+From 2d17c793a9cd3f67351d1a15c099ef2464e81f47 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Mon, 20 May 2013 20:30:11 +0200
-Subject: [PATCH 05/33] MIPS: ralink: make mt7620 ram detect verbose
+Subject: [PATCH 13/25] MIPS: ralink: mt7620: add verbose ram info

 Make the code print which of SDRAM, DDR1 or DDR2 was detected.

--- a/target/linux/ramips/patches-3.10/0010-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch
+++ b/target/linux/ramips/patches-3.10/0010-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch
@ -1,7 +1,9 @@
-From 5340673ba16e3c8c9c1406d5ab84aca82e83e2ce Mon Sep 17 00:00:00 2001
+From d0da9f08ef37e9f639e3b7995d722684da2410a2 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Thu, 23 May 2013 18:46:25 +0200
-Subject: [PATCH 10/33] MIPS: ralink: add spi clock definition to mt7620a
+Subject: [PATCH 14/25] MIPS: ralink: mt7620: add spi clock definition
+
+The definition of the spi clock is missing.

 Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
@ -10,7 +12,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>

 --- a/arch/mips/ralink/mt7620.c
 +++ b/arch/mips/ralink/mt7620.c
-@@ -183,6 +183,7 @@ void __init ralink_clk_init(void)
+@@ -167,6 +167,7 @@ void __init ralink_clk_init(void)
 	ralink_clk_add("cpu", cpu_rate);
 	ralink_clk_add("10000100.timer", 40000000);
 	ralink_clk_add("10000500.uart", 40000000);
--- a/target/linux/ramips/patches-3.10/0015-MIPS-ralink-mt7620-add-wdt-clock-definition.patch
+++ b/target/linux/ramips/patches-3.10/0015-MIPS-ralink-mt7620-add-wdt-clock-definition.patch
@ -0,0 +1,22 @@
+From 51db62f58431d9a89c55f59f98879829dcfddcaf Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 28 Jul 2013 13:50:11 +0200
+Subject: [PATCH 15/25] MIPS: ralink: mt7620: add wdt clock definition
+
+The definition of the wdt clock is missing.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/mt7620.c |    1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
+@@ -166,6 +166,7 @@ void __init ralink_clk_init(void)
+ 
+ 	ralink_clk_add("cpu", cpu_rate);
+ 	ralink_clk_add("10000100.timer", 40000000);
+	ralink_clk_add("10000120.watchdog", 40000000);
+ 	ralink_clk_add("10000500.uart", 40000000);
+ 	ralink_clk_add("10000b00.spi", 40000000);
+ 	ralink_clk_add("10000c00.uartlite", 40000000);
--- a/target/linux/ramips/patches-3.10/0016-MIPS-ralink-mt7620-fix-usb-issue-during-frequency-sc.patch
+++ b/target/linux/ramips/patches-3.10/0016-MIPS-ralink-mt7620-fix-usb-issue-during-frequency-sc.patch
@ -0,0 +1,63 @@
+From 011f4bdba0dd4d1dff6d33b1a65541fc4f09c78e Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 24 May 2013 21:28:08 +0200
+Subject: [PATCH 16/25] MIPS: ralink: mt7620: fix usb issue during frequency
+ scaling
+
+If the USB HCD is running and the cpu is scaled too low, then the USB stops
+working. Increase the idle speed of the core to fix this if the kernel is
+built with USB support.
+
+The values are taken from the Ralink SDK Kernel.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-ralink/mt7620.h |    1 +
+ arch/mips/ralink/mt7620.c                  |   19 +++++++++++++++++++
+ 2 files changed, 20 insertions(+)
+
+--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
+@@ -20,6 +20,7 @@
+ #define SYSC_REG_CHIP_REV		0x0c
+ #define SYSC_REG_SYSTEM_CONFIG0		0x10
+ #define SYSC_REG_SYSTEM_CONFIG1		0x14
+#define SYSC_REG_CPU_SYS_CLKCFG		0x3c
+ #define SYSC_REG_CPLL_CONFIG0		0x54
+ #define SYSC_REG_CPLL_CONFIG1		0x58
+ 
+--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
+@@ -20,6 +20,12 @@
+ 
+ #include "common.h"
+ 
+/* clock scaling */
+#define CLKCFG_FDIV_MASK	0x1f00
+#define CLKCFG_FDIV_USB_VAL	0x0300
+#define CLKCFG_FFRAC_MASK	0x001f
+#define CLKCFG_FFRAC_USB_VAL	0x0003
+
+ /* does the board have sdram or ddram */
+ static int dram_type;
+ 
+@@ -170,6 +176,19 @@ void __init ralink_clk_init(void)
+ 	ralink_clk_add("10000500.uart", 40000000);
+ 	ralink_clk_add("10000b00.spi", 40000000);
+ 	ralink_clk_add("10000c00.uartlite", 40000000);
+
+	if (IS_ENABLED(CONFIG_USB)) {
+		/*
+		 * When the CPU goes into sleep mode, the BUS clock will be too low for
+		 * USB to function properly
+		 */
+		u32 val = rt_sysc_r32(SYSC_REG_CPU_SYS_CLKCFG);
+
+		val &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
+		val |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
+
+		rt_sysc_w32(val, SYSC_REG_CPU_SYS_CLKCFG);
+	}
+ }
+ 
+ void __init ralink_of_remap(void)
--- a/target/linux/ramips/patches-3.10/0017-MIPS-ralink-mt7620-this-SoC-has-ehci-and-ohci-hosts.patch
+++ b/target/linux/ramips/patches-3.10/0017-MIPS-ralink-mt7620-this-SoC-has-ehci-and-ohci-hosts.patch
@ -0,0 +1,23 @@
+From c16c0b66594cb0be44e150dbe3fda747817b873d Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 28 Jul 2013 17:50:53 +0200
+Subject: [PATCH 17/25] MIPS: ralink: mt7620: this SoC has ehci and ohci hosts
+
+Select the the EHCI and OHCI symbols.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/Kconfig |    2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
+@@ -29,6 +29,8 @@ choice
+ 
+ 	config SOC_MT7620
+ 		bool "MT7620"
+		select USB_ARCH_HAS_OHCI
+		select USB_ARCH_HAS_EHCI
+ 
+ endchoice
+ 
--- a/target/linux/ramips/patches-3.10/0017-USB-MIPS-ralink-fix-usb-issue-on-mt7620.patch
+++ b/target/linux/ramips/patches-3.10/0017-USB-MIPS-ralink-fix-usb-issue-on-mt7620.patch
@ -1,41 +0,0 @@
-From 3f40514a51b44171d274ef6a7d66dce9ae7c349d Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 24 May 2013 21:28:08 +0200
-Subject: [PATCH 17/33] USB: MIPS: ralink: fix usb issue on mt7620
-
-USB fails when frequency scaling is enabled. Increase the idle cpu speed when
-scaled.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
---
- arch/mips/include/asm/mach-ralink/mt7620.h |    1 +
- arch/mips/ralink/mt7620.c                  |    8 ++++++++
- 2 files changed, 9 insertions(+)
-
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
-+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
-@@ -20,6 +20,7 @@
- #define SYSC_REG_CHIP_REV		0x0c
- #define SYSC_REG_SYSTEM_CONFIG0		0x10
- #define SYSC_REG_SYSTEM_CONFIG1		0x14
-+#define SYSC_REG_CPU_SYS_CLKCFG		0x3c
- #define SYSC_REG_CPLL_CONFIG0		0x54
- #define SYSC_REG_CPLL_CONFIG1		0x58
- 
--- a/arch/mips/ralink/mt7620.c
-+++ b/arch/mips/ralink/mt7620.c
-@@ -185,6 +185,14 @@ void __init ralink_clk_init(void)
- 	ralink_clk_add("10000500.uart", 40000000);
- 	ralink_clk_add("10000b00.spi", 40000000);
- 	ralink_clk_add("10000c00.uartlite", 40000000);
-+
-+#ifdef CONFIG_USB
-+	/*
-+	 * When the CPU goes into sleep mode, the BUS clock will be too low for
-+	 * USB to function properly
-+	 */
-+	rt_sysc_m32(0x1f1f, 0x303, SYSC_REG_CPU_SYS_CLKCFG);
-+#endif
- }
- 
- void __init ralink_of_remap(void)
--- a/target/linux/ramips/patches-3.10/0018-DT-Add-documentation-for-spi-rt2880.patch
+++ b/target/linux/ramips/patches-3.10/0018-DT-Add-documentation-for-spi-rt2880.patch
@ -0,0 +1,44 @@
+From c464a54f9a4a959d09206583b11ae99740e0f267 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 9 Aug 2013 20:12:59 +0200
+Subject: [PATCH 18/25] DT: Add documentation for spi-rt2880
+
+Describe the SPI master found on the MIPS based Ralink RT2880 SoC.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ .../devicetree/bindings/spi/spi-rt2880.txt         |   28 ++++++++++++++++++++
+ 1 file changed, 28 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/spi/spi-rt2880.txt
+
+--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-rt2880.txt
+@@ -0,0 +1,28 @@
+Ralink SoC RT2880 SPI master controller.
+
+This SPI controller is found on most wireless SoCs made by ralink.
+
+Required properties:
+- compatible : "ralink,rt2880-spi"
+- reg : The register base for the controller.
+- #address-cells : <1>, as required by generic SPI binding.
+- #size-cells : <0>, also as required by generic SPI binding.
+
+Child nodes as per the generic SPI binding.
+
+Example:
+
+	spi@b00 {
+		compatible = "ralink,rt2880-spi";
+		reg = <0xb00 0x100>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		m25p80@0 {
+			compatible = "m25p80";
+			reg = <0>;
+			spi-max-frequency = <10000000>;
+		};
+	};
+
--- a/target/linux/ramips/patches-3.10/0019-SPI-ralink-add-Ralink-SoC-spi-driver.patch
+++ b/target/linux/ramips/patches-3.10/0019-SPI-ralink-add-Ralink-SoC-spi-driver.patch
@ -1,17 +1,18 @@
-From d345c53b941a3d791c26f900af6e85aa1bcaf8b6 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
+From 43c36279a0e822de608c1e825826bbac3238d8a2 Mon Sep 17 00:00:00 2001
+From: Gabor Juhos <juhosg@openwrt.org>
 Date: Mon, 22 Apr 2013 23:16:18 +0200
-Subject: [PATCH 24/33] SPI: ralink: add Ralink SoC spi driver
+Subject: [PATCH 19/25] SPI: ralink: add Ralink SoC spi driver

 Add the driver needed to make SPI work on Ralink SoC.

-Signed-off-by: John Crispin <blogic@openwrt.org>
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: John Crispin <blogic@openwrt.org>
 ---
 drivers/spi/Kconfig      |    6 +
 drivers/spi/Makefile     |    1 +
- drivers/spi/spi-ralink.c |  475 ++++++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 482 insertions(+)
- create mode 100644 drivers/spi/spi-ralink.c
+ drivers/spi/spi-rt2880.c |  450 ++++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 457 insertions(+)
+ create mode 100644 drivers/spi/spi-rt2880.c

 --- a/drivers/spi/Kconfig
 +++ b/drivers/spi/Kconfig
@ -19,9 +20,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 	help
 	  SPI driver for Renesas RSPI blocks.
 
-+config SPI_RALINK
-+	tristate "Ralink RT288x/RT305x/RT3662 SPI Controller"
-+	depends on (SOC_RT288X || SOC_RT305X || SOC_RT3883 || SOC_MT7620)
+config SPI_RT2880
+	tristate "Ralink RT288x SPI Controller"
+	depends on RALINK
 +	help
 +	  This selects a driver for the Ralink RT288x/RT305x SPI Controller.
 +
@ -34,15 +35,15 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 obj-$(CONFIG_SPI_PXA2XX)		+= spi-pxa2xx-platform.o
 obj-$(CONFIG_SPI_PXA2XX_PCI)		+= spi-pxa2xx-pci.o
 obj-$(CONFIG_SPI_RSPI)			+= spi-rspi.o
-+obj-$(CONFIG_SPI_RALINK)		+= spi-ralink.o
+obj-$(CONFIG_SPI_RT2880)		+= spi-rt2880.o
 obj-$(CONFIG_SPI_S3C24XX)		+= spi-s3c24xx-hw.o
 spi-s3c24xx-hw-y			:= spi-s3c24xx.o
 spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
 --- /dev/null
-+++ b/drivers/spi/spi-ralink.c
-@@ -0,0 +1,475 @@
+++ b/drivers/spi/spi-rt2880.c
+@@ -0,0 +1,432 @@
 +/*
-+ * spi-ralink.c -- Ralink RT288x/RT305x SPI controller driver
+ * spi-rt2880.c -- Ralink RT288x/RT305x SPI controller driver
 + *
 + * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
 + * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
@ -66,14 +67,17 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#include <linux/spi/spi.h>
 +#include <linux/platform_device.h>
 +
-+#define DRIVER_NAME			"spi-ralink"
-+#define RALINK_NUM_CHIPSELECTS		1 /* only one slave is supported*/
-+#define RALINK_SPI_WAIT_RDY_MAX_LOOP	2000 /* in usec */
+#define DRIVER_NAME			"spi-rt2880"
+/* only one slave is supported*/
+#define RALINK_NUM_CHIPSELECTS		1
+/* in usec */
+#define RALINK_SPI_WAIT_MAX_LOOP	2000
 +
 +#define RAMIPS_SPI_STAT			0x00
 +#define RAMIPS_SPI_CFG			0x10
 +#define RAMIPS_SPI_CTL			0x14
 +#define RAMIPS_SPI_DATA			0x20
+#define RAMIPS_SPI_FIFO_STAT		0x38
 +
 +/* SPISTAT register bit field */
 +#define SPISTAT_BUSY			BIT(0)
@ -100,72 +104,76 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#define SPICTL_STARTRD			BIT(1)
 +#define SPICTL_SPIENA			BIT(0)
 +
-+#ifdef DEBUG
-+#define spi_debug(args...) printk(args)
-+#else
-+#define spi_debug(args...)
-+#endif
+/* SPIFIFOSTAT register bit field */
+#define SPIFIFOSTAT_TXFULL		BIT(17)
 +
-+struct ralink_spi {
+struct rt2880_spi {
 +	struct spi_master	*master;
 +	void __iomem		*base;
 +	unsigned int		sys_freq;
 +	unsigned int		speed;
 +	struct clk		*clk;
+	spinlock_t		lock;
 +};
 +
-+static inline struct ralink_spi *spidev_to_ralink_spi(struct spi_device *spi)
+static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
 +{
 +	return spi_master_get_devdata(spi->master);
 +}
 +
-+static inline u32 ralink_spi_read(struct ralink_spi *rs, u32 reg)
+static inline u32 rt2880_spi_read(struct rt2880_spi *rs, u32 reg)
 +{
 +	return ioread32(rs->base + reg);
 +}
 +
-+static inline void ralink_spi_write(struct ralink_spi *rs, u32 reg, u32 val)
+static inline void rt2880_spi_write(struct rt2880_spi *rs, u32 reg, u32 val)
 +{
 +	iowrite32(val, rs->base + reg);
 +}
 +
-+static inline void ralink_spi_setbits(struct ralink_spi *rs, u32 reg, u32 mask)
+static inline void rt2880_spi_setbits(struct rt2880_spi *rs, u32 reg, u32 mask)
 +{
 +	void __iomem *addr = rs->base + reg;
+	unsigned long flags;
 +	u32 val;
 +
+	spin_lock_irqsave(&rs->lock, flags);
 +	val = ioread32(addr);
 +	val |= mask;
 +	iowrite32(val, addr);
+	spin_unlock_irqrestore(&rs->lock, flags);
 +}
 +
-+static inline void ralink_spi_clrbits(struct ralink_spi *rs, u32 reg, u32 mask)
+static inline void rt2880_spi_clrbits(struct rt2880_spi *rs, u32 reg, u32 mask)
 +{
 +	void __iomem *addr = rs->base + reg;
+	unsigned long flags;
 +	u32 val;
 +
+	spin_lock_irqsave(&rs->lock, flags);
 +	val = ioread32(addr);
 +	val &= ~mask;
 +	iowrite32(val, addr);
+	spin_unlock_irqrestore(&rs->lock, flags);
 +}
 +
-+static int ralink_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
+static int rt2880_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
 +{
-+	struct ralink_spi *rs = spidev_to_ralink_spi(spi);
+	struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 +	u32 rate;
 +	u32 prescale;
 +	u32 reg;
 +
-+	spi_debug("%s: speed:%u\n", __func__, speed);
+	dev_dbg(&spi->dev, "speed:%u\n", speed);
 +
 +	/*
 +	 * the supported rates are: 2, 4, 8, ... 128
 +	 * round up as we look for equal or less speed
 +	 */
 +	rate = DIV_ROUND_UP(rs->sys_freq, speed);
-+	spi_debug("%s: rate-1:%u\n", __func__, rate);
+	dev_dbg(&spi->dev, "rate-1:%u\n", rate);
 +	rate = roundup_pow_of_two(rate);
-+	spi_debug("%s: rate-2:%u\n", __func__, rate);
+	dev_dbg(&spi->dev, "rate-2:%u\n", rate);
 +
 +	/* check if requested speed is too small */
 +	if (rate > 128)
@ -175,12 +183,12 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +		rate = 2;
 +
 +	/* Convert the rate to SPI clock divisor value.	*/
-+	prescale = ilog2(rate/2);
-+	spi_debug("%s: prescale:%u\n", __func__, prescale);
+	prescale = ilog2(rate / 2);
+	dev_dbg(&spi->dev, "prescale:%u\n", prescale);
 +
-+	reg = ralink_spi_read(rs, RAMIPS_SPI_CFG);
+	reg = rt2880_spi_read(rs, RAMIPS_SPI_CFG);
 +	reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale);
-+	ralink_spi_write(rs, RAMIPS_SPI_CFG, reg);
+	rt2880_spi_write(rs, RAMIPS_SPI_CFG, reg);
 +	rs->speed = speed;
 +	return 0;
 +}
@ -189,54 +197,45 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 + * called only when no transfer is active on the bus
 + */
 +static int
-+ralink_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
+rt2880_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 +{
-+	struct ralink_spi *rs = spidev_to_ralink_spi(spi);
+	struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 +	unsigned int speed = spi->max_speed_hz;
 +	int rc;
-+	unsigned int bits_per_word = 8;
 +
 +	if ((t != NULL) && t->speed_hz)
 +		speed = t->speed_hz;
 +
-+	if ((t != NULL) && t->bits_per_word)
-+		bits_per_word = t->bits_per_word;
-+
 +	if (rs->speed != speed) {
-+		spi_debug("%s: speed_hz:%u\n", __func__, speed);
-+		rc = ralink_spi_baudrate_set(spi, speed);
+		dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
+		rc = rt2880_spi_baudrate_set(spi, speed);
 +		if (rc)
 +			return rc;
 +	}
 +
-+	if (bits_per_word != 8) {
-+		spi_debug("%s: bad bits_per_word: %u\n", __func__,
-+			  bits_per_word);
-+		return -EINVAL;
-+	}
-+
 +	return 0;
 +}
 +
-+static void ralink_spi_set_cs(struct ralink_spi *rs, int enable)
+static void rt2880_spi_set_cs(struct rt2880_spi *rs, int enable)
 +{
 +	if (enable)
-+		ralink_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
+		rt2880_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
 +	else
-+		ralink_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
+		rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
 +}
 +
-+static inline int ralink_spi_wait_till_ready(struct ralink_spi *rs)
+static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
 +{
 +	int i;
 +
-+	for (i = 0; i < RALINK_SPI_WAIT_RDY_MAX_LOOP; i++) {
+	for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
 +		u32 status;
 +
-+		status = ralink_spi_read(rs, RAMIPS_SPI_STAT);
+		status = rt2880_spi_read(rs, RAMIPS_SPI_STAT);
 +		if ((status & SPISTAT_BUSY) == 0)
 +			return 0;
 +
+		cpu_relax();
 +		udelay(1);
 +	}
 +
@ -244,23 +243,23 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +}
 +
 +static unsigned int
-+ralink_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
+rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
 +{
-+	struct ralink_spi *rs = spidev_to_ralink_spi(spi);
+	struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 +	unsigned count = 0;
 +	u8 *rx = xfer->rx_buf;
 +	const u8 *tx = xfer->tx_buf;
 +	int err;
 +
-+	spi_debug("%s(%d): %s %s\n", __func__, xfer->len,
+	dev_dbg(&spi->dev, "read (%d): %s %s\n", xfer->len,
 +		  (tx != NULL) ? "tx" : "  ",
 +		  (rx != NULL) ? "rx" : "  ");
 +
 +	if (tx) {
 +		for (count = 0; count < xfer->len; count++) {
-+			ralink_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
-+			ralink_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
-+			err = ralink_spi_wait_till_ready(rs);
+			rt2880_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
+			rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
+			err = rt2880_spi_wait_till_ready(rs);
 +			if (err) {
 +				dev_err(&spi->dev, "TX failed, err=%d\n", err);
 +				goto out;
@ -270,13 +269,13 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +
 +	if (rx) {
 +		for (count = 0; count < xfer->len; count++) {
-+			ralink_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
-+			err = ralink_spi_wait_till_ready(rs);
+			rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
+			err = rt2880_spi_wait_till_ready(rs);
 +			if (err) {
 +				dev_err(&spi->dev, "RX failed, err=%d\n", err);
 +				goto out;
 +			}
-+			rx[count] = (u8) ralink_spi_read(rs, RAMIPS_SPI_DATA);
+			rx[count] = (u8) rt2880_spi_read(rs, RAMIPS_SPI_DATA);
 +		}
 +	}
 +
@ -284,10 +283,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	return count;
 +}
 +
-+static int ralink_spi_transfer_one_message(struct spi_master *master,
+static int rt2880_spi_transfer_one_message(struct spi_master *master,
 +					   struct spi_message *m)
 +{
-+	struct ralink_spi *rs = spi_master_get_devdata(master);
+	struct rt2880_spi *rs = spi_master_get_devdata(master);
 +	struct spi_device *spi = m->spi;
 +	struct spi_transfer *t = NULL;
 +	int par_override = 0;
@ -295,13 +294,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	int cs_active = 0;
 +
 +	/* Load defaults */
-+	status = ralink_spi_setup_transfer(spi, NULL);
+	status = rt2880_spi_setup_transfer(spi, NULL);
 +	if (status < 0)
 +		goto msg_done;
 +
 +	list_for_each_entry(t, &m->transfers, transfer_list) {
-+		unsigned int bits_per_word = spi->bits_per_word;
-+
 +		if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 +			dev_err(&spi->dev,
 +				"message rejected: invalid transfer data buffers\n");
@ -309,17 +306,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +			goto msg_done;
 +		}
 +
-+		if (t->bits_per_word)
-+			bits_per_word = t->bits_per_word;
-+
-+		if (bits_per_word != 8) {
-+			dev_err(&spi->dev,
-+				"message rejected: invalid transfer bits_per_word (%d bits)\n",
-+				bits_per_word);
-+			status = -EIO;
-+			goto msg_done;
-+		}
-+
 +		if (t->speed_hz && t->speed_hz < (rs->sys_freq / 128)) {
 +			dev_err(&spi->dev,
 +				"message rejected: device min speed (%d Hz) exceeds required transfer speed (%d Hz)\n",
@ -330,7 +316,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +
 +		if (par_override || t->speed_hz || t->bits_per_word) {
 +			par_override = 1;
-+			status = ralink_spi_setup_transfer(spi, t);
+			status = rt2880_spi_setup_transfer(spi, t);
 +			if (status < 0)
 +				goto msg_done;
 +			if (!t->speed_hz && !t->bits_per_word)
@ -338,25 +324,25 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +		}
 +
 +		if (!cs_active) {
-+			ralink_spi_set_cs(rs, 1);
+			rt2880_spi_set_cs(rs, 1);
 +			cs_active = 1;
 +		}
 +
 +		if (t->len)
-+			m->actual_length += ralink_spi_write_read(spi, t);
+			m->actual_length += rt2880_spi_write_read(spi, t);
 +
 +		if (t->delay_usecs)
 +			udelay(t->delay_usecs);
 +
 +		if (t->cs_change) {
-+			ralink_spi_set_cs(rs, 0);
+			rt2880_spi_set_cs(rs, 0);
 +			cs_active = 0;
 +		}
 +	}
 +
 +msg_done:
 +	if (cs_active)
-+		ralink_spi_set_cs(rs, 0);
+		rt2880_spi_set_cs(rs, 0);
 +
 +	m->status = status;
 +	spi_finalize_current_message(master);
@ -364,9 +350,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	return 0;
 +}
 +
-+static int ralink_spi_setup(struct spi_device *spi)
+static int rt2880_spi_setup(struct spi_device *spi)
 +{
-+	struct ralink_spi *rs = spidev_to_ralink_spi(spi);
+	struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 +
 +	if ((spi->max_speed_hz == 0) ||
 +	    (spi->max_speed_hz > (rs->sys_freq / 2)))
@ -378,36 +364,45 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +		return -EINVAL;
 +	}
 +
-+	if (spi->bits_per_word != 0 && spi->bits_per_word != 8) {
-+		dev_err(&spi->dev,
-+			"setup: requested bits per words - os wrong %d bpw\n",
-+			spi->bits_per_word);
-+		return -EINVAL;
-+	}
-+
-+	if (spi->bits_per_word == 0)
-+		spi->bits_per_word = 8;
-+
 +	/*
-+	 * baudrate & width will be set ralink_spi_setup_transfer
+	 * baudrate & width will be set rt2880_spi_setup_transfer
 +	 */
 +	return 0;
 +}
 +
-+static void ralink_spi_reset(struct ralink_spi *rs)
+static void rt2880_spi_reset(struct rt2880_spi *rs)
 +{
-+	ralink_spi_write(rs, RAMIPS_SPI_CFG,
+	rt2880_spi_write(rs, RAMIPS_SPI_CFG,
 +			 SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
 +			 SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
-+	ralink_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
+	rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
 +}
 +
-+static int ralink_spi_probe(struct platform_device *pdev)
+static int rt2880_spi_probe(struct platform_device *pdev)
 +{
 +	struct spi_master *master;
-+	struct ralink_spi *rs;
+	struct rt2880_spi *rs;
+	unsigned long flags;
+	void __iomem *base;
 +	struct resource *r;
 +	int status = 0;
+	struct clk *clk;
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	base = devm_ioremap_resource(&pdev->dev, r);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	clk = devm_clk_get(&pdev->dev, NULL);
+	if (IS_ERR(clk)) {
+		dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
+			status);
+		return PTR_ERR(clk);
+	}
+
+	status = clk_prepare_enable(clk);
+	if (status)
+		return status;
 +
 +	master = spi_alloc_master(&pdev->dev, sizeof(*rs));
 +	if (master == NULL) {
@ -415,78 +410,41 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +		return -ENOMEM;
 +	}
 +
-+	//if (pdev->id != -1)
-+		master->bus_num = 0;
-+
 +	/* we support only mode 0, and no options */
 +	master->mode_bits = 0;
 +
-+	master->setup = ralink_spi_setup;
-+	master->transfer_one_message = ralink_spi_transfer_one_message;
+	master->setup = rt2880_spi_setup;
+	master->transfer_one_message = rt2880_spi_transfer_one_message;
 +	master->num_chipselect = RALINK_NUM_CHIPSELECTS;
+	master->bits_per_word_mask = SPI_BPW_MASK(8);
 +	master->dev.of_node = pdev->dev.of_node;
 +
 +	dev_set_drvdata(&pdev->dev, master);
 +
 +	rs = spi_master_get_devdata(master);
+	rs->base = base;
+	rs->clk = clk;
 +	rs->master = master;
-+
-+	rs->clk = clk_get(&pdev->dev, NULL);
-+	if (IS_ERR(rs->clk)) {
-+		status = PTR_ERR(rs->clk);
-+		dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
-+			status);
-+		goto out_put_master;
-+	}
-+
-+	status = clk_enable(rs->clk);
-+	if (status)
-+		goto out_put_clk;
-+
 +	rs->sys_freq = clk_get_rate(rs->clk);
-+	spi_debug("%s: sys_freq: %u\n", __func__, rs->sys_freq);
-+
-+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	if (r == NULL) {
-+		status = -ENODEV;
-+		goto out_disable_clk;
-+	}
-+
-+	rs->base = devm_request_and_ioremap(&pdev->dev, r);
-+	if (!rs->base) {
-+		status = -EADDRNOTAVAIL;
-+		goto out_disable_clk;
-+	}
+	dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
+	spin_lock_irqsave(&rs->lock, flags);
 +
 +	device_reset(&pdev->dev);
 +
-+	ralink_spi_reset(rs);
+	rt2880_spi_reset(rs);
 +
-+	status = spi_register_master(master);
-+	if (status)
-+		goto out_disable_clk;
-+
-+	return 0;
-+
-+out_disable_clk:
-+	clk_disable(rs->clk);
-+out_put_clk:
-+	clk_put(rs->clk);
-+out_put_master:
-+	spi_master_put(master);
-+	return status;
+	return spi_register_master(master);
 +}
 +
-+static int ralink_spi_remove(struct platform_device *pdev)
+static int rt2880_spi_remove(struct platform_device *pdev)
 +{
 +	struct spi_master *master;
-+	struct ralink_spi *rs;
+	struct rt2880_spi *rs;
 +
 +	master = dev_get_drvdata(&pdev->dev);
 +	rs = spi_master_get_devdata(master);
 +
 +	clk_disable(rs->clk);
-+	clk_put(rs->clk);
 +	spi_unregister_master(master);
 +
 +	return 0;
@ -494,23 +452,23 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +
 +MODULE_ALIAS("platform:" DRIVER_NAME);
 +
-+static const struct of_device_id ralink_spi_match[] = {
+static const struct of_device_id rt2880_spi_match[] = {
 +	{ .compatible = "ralink,rt2880-spi" },
 +	{},
 +};
-+MODULE_DEVICE_TABLE(of, ralink_spi_match);
+MODULE_DEVICE_TABLE(of, rt2880_spi_match);
 +
-+static struct platform_driver ralink_spi_driver = {
+static struct platform_driver rt2880_spi_driver = {
 +	.driver = {
 +		.name = DRIVER_NAME,
 +		.owner = THIS_MODULE,
-+		.of_match_table = ralink_spi_match,
+		.of_match_table = rt2880_spi_match,
 +	},
-+	.probe = ralink_spi_probe,
-+	.remove = ralink_spi_remove,
+	.probe = rt2880_spi_probe,
+	.remove = rt2880_spi_remove,
 +};
 +
-+module_platform_driver(ralink_spi_driver);
+module_platform_driver(rt2880_spi_driver);
 +
 +MODULE_DESCRIPTION("Ralink SPI driver");
 +MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
--- a/target/linux/ramips/patches-3.10/0020-MIPS-ralink-update-dts-files.patch
+++ b/target/linux/ramips/patches-3.10/0020-MIPS-ralink-update-dts-files.patch
@ -0,0 +1,629 @@
+From 5845a3aa53cf42893db05662aa9bb91387949ff6 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 12 Aug 2013 18:11:33 +0200
+Subject: [PATCH 22/25] MIPS: ralink: update dts files
+
+Add the devicetree nodes needed to make the newly merged drivers work.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/dts/mt7620a.dtsi |  135 +++++++++++++++++++++++
+ arch/mips/ralink/dts/rt3050.dtsi  |  156 ++++++++++++++++++++++++++
+ arch/mips/ralink/dts/rt3883.dtsi  |  219 +++++++++++++++++++++++++++++++++++++
+ 3 files changed, 510 insertions(+)
+
+--- a/arch/mips/ralink/dts/mt7620a.dtsi
+++ b/arch/mips/ralink/dts/mt7620a.dtsi
+@@ -29,10 +29,32 @@
+ 			reg = <0x0 0x100>;
+ 		};
+ 
+		timer@100 {
+			compatible = "ralink,mt7620a-timer", "ralink,rt2880-timer";
+			reg = <0x100 0x20>;
+
+			interrupt-parent = <&intc>;
+			interrupts = <1>;
+		};
+
+		watchdog@120 {
+			compatible = "ralink,mt7620a-wdt", "ralink,rt2880-wdt";
+			reg = <0x120 0x10>;
+
+			resets = <&rstctrl 8>;
+			reset-names = "wdt";
+
+			interrupt-parent = <&intc>;
+			interrupts = <1>;
+		};
+
+ 		intc: intc@200 {
+ 			compatible = "ralink,mt7620a-intc", "ralink,rt2880-intc";
+ 			reg = <0x200 0x100>;
+ 
+			resets = <&rstctrl 19>;
+			reset-names = "intc";
+
+ 			interrupt-controller;
+ 			#interrupt-cells = <1>;
+ 
+@@ -43,16 +65,129 @@
+ 		memc@300 {
+ 			compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
+ 			reg = <0x300 0x100>;
+
+			resets = <&rstctrl 20>;
+			reset-names = "mc";
+
+			interrupt-parent = <&intc>;
+			interrupts = <3>;
+		};
+
+		uart@500 {
+			compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
+			reg = <0x500 0x100>;
+
+			resets = <&rstctrl 12>;
+			reset-names = "uart";
+
+			interrupt-parent = <&intc>;
+			interrupts = <5>;
+
+			reg-shift = <2>;
+
+			status = "disabled";
+		};
+
+		gpio0: gpio@600 {
+			compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
+			reg = <0x600 0x34>;
+
+			resets = <&rstctrl 13>;
+			reset-names = "pio";
+
+			interrupt-parent = <&intc>;
+			interrupts = <6>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			ralink,gpio-base = <0>;
+			ralink,num-gpios = <24>;
+			ralink,register-map = [ 00 04 08 0c
+						20 24 28 2c
+						30 34 ];
+
+			status = "disabled";
+		};
+
+		gpio1: gpio@638 {
+			compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
+			reg = <0x638 0x24>;
+
+			interrupt-parent = <&intc>;
+			interrupts = <6>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			ralink,gpio-base = <24>;
+			ralink,num-gpios = <16>;
+			ralink,register-map = [ 00 04 08 0c
+						10 14 18 1c
+						20 24 ];
+
+			status = "disabled";
+		};
+
+		gpio2: gpio@660 {
+			compatible = "ralink,mt7620a-gpio", "ralink,rt2880-gpio";
+			reg = <0x660 0x24>;
+
+			interrupt-parent = <&intc>;
+			interrupts = <6>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			ralink,gpio-base = <40>;
+			ralink,num-gpios = <32>;
+			ralink,register-map = [ 00 04 08 0c
+						10 14 18 1c
+						20 24 ];
+
+			status = "disabled";
+		};
+
+		spi@b00 {
+			compatible = "ralink,mt7620a-spi", "ralink,rt2880-spi";
+			reg = <0xb00 0x100>;
+
+			resets = <&rstctrl 18>;
+			reset-names = "spi";
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			status = "disabled";
+ 		};
+ 
+ 		uartlite@c00 {
+ 			compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a";
+ 			reg = <0xc00 0x100>;
+ 
+			resets = <&rstctrl 19>;
+			reset-names = "uartl";
+
+ 			interrupt-parent = <&intc>;
+ 			interrupts = <12>;
+ 
+ 			reg-shift = <2>;
+ 		};
+
+		systick@d00 {
+			compatible = "ralink,mt7620a-systick", "ralink,cevt-systick";
+			reg = <0xd00 0x10>;
+
+			resets = <&rstctrl 28>;
+			reset-names = "intc";
+
+			interrupt-parent = <&cpuintc>;
+			interrupts = <7>;
+		};
+	};
+
+	rstctrl: rstctrl {
+		compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
+		#reset-cells = <1>;
+ 	};
+ };
+--- a/arch/mips/ralink/dts/rt3050.dtsi
+++ b/arch/mips/ralink/dts/rt3050.dtsi
+@@ -9,6 +9,10 @@
+ 		};
+ 	};
+ 
+	chosen {
+		bootargs = "console=ttyS0,57600";
+	};
+
+ 	cpuintc: cpuintc@0 {
+ 		#address-cells = <0>;
+ 		#interrupt-cells = <1>;
+@@ -29,10 +33,32 @@
+ 			reg = <0x0 0x100>;
+ 		};
+ 
+		timer@100 {
+			compatible = "ralink,rt3052-timer", "ralink,rt2880-timer";
+			reg = <0x100 0x20>;
+
+			interrupt-parent = <&intc>;
+			interrupts = <1>;
+		};
+
+		watchdog@120 {
+			compatible = "ralink,rt3052-wdt", "ralink,rt2880-wdt";
+			reg = <0x120 0x10>;
+
+			resets = <&rstctrl 8>;
+			reset-names = "wdt";
+
+			interrupt-parent = <&intc>;
+			interrupts = <1>;
+		};
+
+ 		intc: intc@200 {
+ 			compatible = "ralink,rt3052-intc", "ralink,rt2880-intc";
+ 			reg = <0x200 0x100>;
+ 
+			resets = <&rstctrl 19>;
+			reset-names = "intc";
+
+ 			interrupt-controller;
+ 			#interrupt-cells = <1>;
+ 
+@@ -43,17 +69,144 @@
+ 		memc@300 {
+ 			compatible = "ralink,rt3052-memc", "ralink,rt3050-memc";
+ 			reg = <0x300 0x100>;
+
+			resets = <&rstctrl 20>;
+			reset-names = "mc";
+
+			interrupt-parent = <&intc>;
+			interrupts = <3>;
+		};
+
+		uart@500 {
+			compatible = "ralink,rt5350-uart", "ralink,rt2880-uart", "ns16550a";
+			reg = <0x500 0x100>;
+
+			resets = <&rstctrl 12>;
+			reset-names = "uart";
+
+			interrupt-parent = <&intc>;
+			interrupts = <5>;
+
+			reg-shift = <2>;
+
+			status = "disabled";
+		};
+
+		gpio0: gpio@600 {
+			compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
+			reg = <0x600 0x34>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			ralink,gpio-base = <0>;
+			ralink,num-gpios = <24>;
+			ralink,register-map = [ 00 04 08 0c
+						20 24 28 2c
+						30 34 ];
+
+			resets = <&rstctrl 13>;
+			reset-names = "pio";
+
+			interrupt-parent = <&intc>;
+			interrupts = <6>;
+
+			status = "disabled";
+		};
+
+		gpio1: gpio@638 {
+			compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
+			reg = <0x638 0x24>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			ralink,gpio-base = <24>;
+			ralink,num-gpios = <16>;
+			ralink,register-map = [ 00 04 08 0c
+						10 14 18 1c
+						20 24 ];
+
+			status = "disabled";
+		};
+
+		gpio2: gpio@660 {
+			compatible = "ralink,rt3052-gpio", "ralink,rt2880-gpio";
+			reg = <0x660 0x24>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			ralink,gpio-base = <40>;
+			ralink,num-gpios = <12>;
+			ralink,register-map = [ 00 04 08 0c
+						10 14 18 1c
+						20 24 ];
+
+			status = "disabled";
+		};
+
+		spi@b00 {
+			compatible = "ralink,rt3050-spi", "ralink,rt2880-spi";
+			reg = <0xb00 0x100>;
+
+			resets = <&rstctrl 18>;
+			reset-names = "spi";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			status = "disabled";
+ 		};
+ 
+ 		uartlite@c00 {
+ 			compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a";
+ 			reg = <0xc00 0x100>;
+ 
+			resets = <&rstctrl 19>;
+			reset-names = "uartl";
+
+ 			interrupt-parent = <&intc>;
+ 			interrupts = <12>;
+ 
+ 			reg-shift = <2>;
+ 		};
+
+	};
+
+	rstctrl: rstctrl {
+		compatible = "ralink,rt3050-reset", "ralink,rt2880-reset";
+		#reset-cells = <1>;
+	};
+
+	ethernet@10100000 {
+		compatible = "ralink,rt3050-eth";
+		reg = <0x10100000 10000>;
+
+		interrupt-parent = <&cpuintc>;
+		interrupts = <5>;
+
+		status = "disabled";
+	};
+
+	esw@10110000 {
+		compatible = "ralink,rt3050-esw";
+		reg = <0x10110000 8000>;
+
+		interrupt-parent = <&intc>;
+		interrupts = <17>;
+
+		status = "disabled";
+	};
+
+	wmac@10180000 {
+		compatible = "ralink,rt3050-wmac", "ralink,rt2880-wmac";
+		reg = <0x10180000 40000>;
+
+		interrupt-parent = <&cpuintc>;
+		interrupts = <6>;
+
+		status = "disabled";
+ 	};
+ 
+ 	usb@101c0000 {
+@@ -63,6 +216,9 @@
+ 		interrupt-parent = <&intc>;
+ 		interrupts = <18>;
+ 
+		resets = <&rstctrl 22>;
+		reset-names = "otg";
+
+ 		status = "disabled";
+ 	};
+ };
+--- a/arch/mips/ralink/dts/rt3883.dtsi
+++ b/arch/mips/ralink/dts/rt3883.dtsi
+@@ -29,10 +29,32 @@
+ 			reg = <0x0 0x100>;
+ 		};
+ 
+		timer@100 {
+			compatible = "ralink,rt3883-timer", "ralink,rt2880-timer";
+			reg = <0x100 0x20>;
+
+			interrupt-parent = <&intc>;
+			interrupts = <1>;
+		};
+
+		watchdog@120 {
+			compatible = "ralink,rt3883-wdt", "ralink,rt2880-wdt";
+			reg = <0x120 0x10>;
+
+			resets = <&rstctrl 8>;
+			reset-names = "wdt";
+
+			interrupt-parent = <&intc>;
+			interrupts = <1>;
+		};
+
+ 		intc: intc@200 {
+ 			compatible = "ralink,rt3883-intc", "ralink,rt2880-intc";
+ 			reg = <0x200 0x100>;
+ 
+			resets = <&rstctrl 19>;
+			reset-names = "intc";
+
+ 			interrupt-controller;
+ 			#interrupt-cells = <1>;
+ 
+@@ -43,16 +65,213 @@
+ 		memc@300 {
+ 			compatible = "ralink,rt3883-memc", "ralink,rt3050-memc";
+ 			reg = <0x300 0x100>;
+
+			resets = <&rstctrl 20>;
+			reset-names = "mc";
+
+			interrupt-parent = <&intc>;
+			interrupts = <3>;
+		};
+
+		uart@500 {
+			compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
+			reg = <0x500 0x100>;
+
+			resets = <&rstctrl 12>;
+			reset-names = "uart";
+
+			interrupt-parent = <&intc>;
+			interrupts = <5>;
+
+			reg-shift = <2>;
+
+			status = "disabled";
+		};
+
+		gpio0: gpio@600 {
+			compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
+			reg = <0x600 0x34>;
+
+			resets = <&rstctrl 13>;
+			reset-names = "pio";
+
+			interrupt-parent = <&intc>;
+			interrupts = <6>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			ralink,gpio-base = <0>;
+			ralink,num-gpios = <24>;
+			ralink,register-map = [ 00 04 08 0c
+						20 24 28 2c
+						30 34 ];
+
+			status = "disabled";
+		};
+
+		gpio1: gpio@638 {
+			compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
+			reg = <0x638 0x24>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			ralink,gpio-base = <24>;
+			ralink,num-gpios = <16>;
+			ralink,register-map = [ 00 04 08 0c
+						10 14 18 1c
+						20 24 ];
+
+			status = "disabled";
+		};
+
+		gpio2: gpio@660 {
+			compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
+			reg = <0x660 0x24>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			ralink,gpio-base = <40>;
+			ralink,num-gpios = <32>;
+			ralink,register-map = [ 00 04 08 0c
+						10 14 18 1c
+						20 24 ];
+
+			status = "disabled";
+		};
+
+		gpio3: gpio@688 {
+			compatible = "ralink,rt3883-gpio", "ralink,rt2880-gpio";
+			reg = <0x688 0x24>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			ralink,gpio-base = <72>;
+			ralink,num-gpios = <24>;
+			ralink,register-map = [ 00 04 08 0c
+						10 14 18 1c
+						20 24 ];
+
+			status = "disabled";
+		};
+
+		spi0: spi@b00 {
+			compatible = "ralink,rt3883-spi", "ralink,rt2880-spi";
+			reg = <0xb00 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			resets = <&rstctrl 18>;
+			reset-names = "spi";
+
+			status = "disabled";
+ 		};
+ 
+ 		uartlite@c00 {
+ 			compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a";
+ 			reg = <0xc00 0x100>;
+ 
+			resets = <&rstctrl 19>;
+			reset-names = "uartl";
+
+ 			interrupt-parent = <&intc>;
+ 			interrupts = <12>;
+ 
+ 			reg-shift = <2>;
+ 		};
+ 	};
+
+	rstctrl: rstctrl {
+		compatible = "ralink,rt3883-reset", "ralink,rt2880-reset";
+		#reset-cells = <1>;
+	};
+
+	pci@10140000 {
+		compatible = "ralink,rt3883-pci";
+		reg = <0x10140000 0x20000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges; /* direct mapping */
+
+		status = "disabled";
+
+		pciintc: interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+
+			interrupt-parent = <&cpuintc>;
+			interrupts = <4>;
+		};
+
+		host-bridge {
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+
+			device_type = "pci";
+
+			bus-range = <0 255>;
+			ranges = <
+				0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
+				0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
+			>;
+
+			interrupt-map-mask = <0xf800 0 0 7>;
+			interrupt-map = <
+				/* IDSEL 17 */
+				0x8800 0 0 1 &pciintc 18
+				0x8800 0 0 2 &pciintc 18
+				0x8800 0 0 3 &pciintc 18
+				0x8800 0 0 4 &pciintc 18
+				/* IDSEL 18 */
+				0x9000 0 0 1 &pciintc 19
+				0x9000 0 0 2 &pciintc 19
+				0x9000 0 0 3 &pciintc 19
+				0x9000 0 0 4 &pciintc 19
+			>;
+
+			pci-bridge@1 {
+				reg = <0x0800 0 0 0 0>;
+				device_type = "pci";
+				#interrupt-cells = <1>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+
+				status = "disabled";
+
+				ralink,pci-slot = <1>;
+
+				interrupt-map-mask = <0x0 0 0 0>;
+				interrupt-map = <0x0 0 0 0 &pciintc 20>;
+			};
+
+			pci-slot@17 {
+				reg = <0x8800 0 0 0 0>;
+				device_type = "pci";
+				#interrupt-cells = <1>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+
+				ralink,pci-slot = <17>;
+
+				status = "disabled";
+			};
+
+			pci-slot@18 {
+				reg = <0x9000 0 0 0 0>;
+				device_type = "pci";
+				#interrupt-cells = <1>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+
+				ralink,pci-slot = <18>;
+
+				status = "disabled";
+			};
+		};
+	};
+ };
--- a/target/linux/ramips/patches-3.10/0021-MIPS-ralink-add-cpu-frequency-scaling.patch
+++ b/target/linux/ramips/patches-3.10/0021-MIPS-ralink-add-cpu-frequency-scaling.patch
@ -0,0 +1,95 @@
+From f6dc5d40c766e5ff9b18b93a1b6f7a576655f9c4 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 28 Jul 2013 16:26:41 +0200
+Subject: [PATCH 21/25] MIPS: ralink: add cpu frequency scaling
+
+This feature will break udelay() and cause the delay loop to have longer delays
+when the frequency is scaled causing a performance hit.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/cevt-rt3352.c |   36 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+--- a/arch/mips/ralink/cevt-rt3352.c
+++ b/arch/mips/ralink/cevt-rt3352.c
+@@ -29,6 +29,10 @@
+ /* enable the counter */
+ #define CFG_CNT_EN		0x1
+ 
+/* mt7620 frequency scaling defines */
+#define CLK_LUT_CFG	0x40
+#define SLEEP_EN	BIT(31)
+
+ struct systick_device {
+ 	void __iomem *membase;
+ 	struct clock_event_device dev;
+@@ -36,6 +40,8 @@ struct systick_device {
+ 	int freq_scale;
+ };
+ 
+static void (*systick_freq_scaling)(struct systick_device *sdev, int status);
+
+ static void systick_set_clock_mode(enum clock_event_mode mode,
+ 				struct clock_event_device *evt);
+ 
+@@ -87,6 +93,21 @@ static struct irqaction systick_irqactio
+ 	.dev_id = &systick.dev,
+ };
+ 
+static inline void mt7620_freq_scaling(struct systick_device *sdev, int status)
+{
+	if (sdev->freq_scale == status)
+		return;
+
+	sdev->freq_scale = status;
+
+	pr_info("%s: %s autosleep mode\n", systick.dev.name,
+			(status) ? ("enable") : ("disable"));
+	if (status)
+		rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) | SLEEP_EN, CLK_LUT_CFG);
+	else
+		rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) & ~SLEEP_EN, CLK_LUT_CFG);
+}
+
+ static void systick_set_clock_mode(enum clock_event_mode mode,
+ 				struct clock_event_device *evt)
+ {
+@@ -101,9 +122,13 @@ static void systick_set_clock_mode(enum
+ 		sdev->irq_requested = 1;
+ 		iowrite32(CFG_EXT_STK_EN | CFG_CNT_EN,
+ 				systick.membase + SYSTICK_CONFIG);
+		if (systick_freq_scaling)
+			systick_freq_scaling(sdev, 1);
+ 		break;
+ 
+ 	case CLOCK_EVT_MODE_SHUTDOWN:
+		if (systick_freq_scaling)
+			systick_freq_scaling(sdev, 0);
+ 		if (sdev->irq_requested)
+ 			free_irq(systick.dev.irq, &systick_irqaction);
+ 		sdev->irq_requested = 0;
+@@ -116,12 +141,23 @@ static void systick_set_clock_mode(enum
+ 	}
+ }
+ 
+static const struct of_device_id systick_match[] = {
+	{ .compatible = "ralink,mt7620-systick", .data = mt7620_freq_scaling},
+	{},
+};
+
+ static void __init ralink_systick_init(struct device_node *np)
+ {
+	const struct of_device_id *match;
+
+ 	systick.membase = of_iomap(np, 0);
+ 	if (!systick.membase)
+ 		return;
+ 
+	match = of_match_node(systick_match, np);
+	if (match)
+		systick_freq_scaling = match->data;
+
+ 	systick_irqaction.name = np->name;
+ 	systick.dev.name = np->name;
+ 	clockevents_calc_mult_shift(&systick.dev, SYSTICK_FREQ, 60);
--- a/target/linux/ramips/patches-3.10/0022-MIPS-add-driver-for-the-built-in-PCI-controller-of-the-RT3883-SoC.patch
+++ b/target/linux/ramips/patches-3.10/0022-MIPS-add-driver-for-the-built-in-PCI-controller-of-the-RT3883-SoC.patch
@ -1,31 +1,221 @@
-From b43e77699154356a39796d95ef316699dafe409d Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 21 Mar 2013 17:34:08 +0100
-Subject: [PATCH 12/33] PCI: MIPS: adds rt3883 pci support
+From patchwork Fri Aug  9 16:03:32 2013
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+Subject: MIPS: add driver for the built-in PCI controller of the RT3883 SoC
+From: Gabor Juhos <juhosg@openwrt.org>
+X-Patchwork-Id: 5687
+Message-Id: <1376064212-28415-1-git-send-email-juhosg@openwrt.org>
+To: Ralf Baechle <ralf@linux-mips.org>
+Cc: linux-mips@linux-mips.org, John Crispin <blogic@openwrt.org>,
+ Gabor Juhos <juhosg@openwrt.org>, devicetree@vger.kernel.org
+Date: Fri,  9 Aug 2013 18:03:32 +0200

-Add support for the pcie found on the rt3883 SoC.
+The Ralink RT3883 SoCs have a built-in PCI Host Controller
+device. The patch adds a platform driver and device tree
+binding documentation for that.
+
+The patch also enables the HW_HAS_PCI config option. This
+is required in order to be able to enable the PCI support.
+
+Cc: devicetree@vger.kernel.org
+Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
+Acked-by: John Crispin <blogic@openwrt.org>

-Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
- arch/mips/pci/Makefile     |    1 +
- arch/mips/pci/pci-rt3883.c |  640 ++++++++++++++++++++++++++++++++++++++++++++
- arch/mips/ralink/Kconfig   |    1 +
- 3 files changed, 642 insertions(+)
+.../devicetree/bindings/pci/ralink,rt3883-pci.txt  |  169 ++++++
+ arch/mips/pci/Makefile                             |    1 +
+ arch/mips/pci/pci-rt3883.c                         |  636 ++++++++++++++++++++
+ arch/mips/ralink/Kconfig                           |    1 +
+ 4 files changed, 807 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt
 create mode 100644 arch/mips/pci/pci-rt3883.c

+--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt
+@@ -0,0 +1,169 @@
+* Mediatek/Ralink RT3883 PCI controller
+
+1) Main node
+
+   Required properties:
+
+   - compatible: must be "ralink,rt3883-pci"
+
+   - reg: specifies the physical base address of the controller and
+     the length of the memory mapped region.
+
+   - #address-cells: specifies the number of cells needed to encode an
+     address. The value must be 1.
+
+   - #size-cells: specifies the number of cells used to represent the size
+     of an address. The value must be 1.
+
+   - ranges: specifies the translation between child address space and parent
+     address space
+
+   - status: either "disabled" or "okay"
+
+2) Child nodes
+
+   The main node must have two child nodes which describes the built-in
+   interrupt controller and the PCI host bridge.
+
+   a) Interrupt controller:
+
+   Required properties:
+
+   - interrupt-controller: identifies the node as an interrupt controller
+
+   - #address-cells: specifies the number of cells needed to encode an
+     address. The value must be 0. As such, 'interrupt-map' nodes do not
+     have to specify a parent unit address.
+
+   - #interrupt-cells: specifies the number of cells needed to encode an
+     interrupt source. The value must be 1.
+
+   - interrupt-parent: the phandle for the interrupt controller that
+     services interrupts for this device.
+
+   - interrupts: specifies the interrupt source of the parent interrupt
+     controller. The format of the interrupt specifier depends on the
+     parent interrupt controller.
+
+   b) PCI host bridge:
+
+   Required properties:
+
+   - #address-cells: specifies the number of cells needed to encode an
+     address. The value must be 0.
+
+   - #size-cells: specifies the number of cells used to represent the size
+     of an address. The value must be 2.
+
+   - #interrupt-cells: specifies the number of cells needed to encode an
+     interrupt source. The value must be 1.
+
+   - device_type: must be "pci"
+
+   - bus-range: PCI bus numbers covered
+
+   - ranges: specifies the ranges for the PCI memory and I/O regions
+
+   - interrupt-map-mask,
+   - interrupt-map: standard PCI properties to define the mapping of the
+     PCI interface to interrupt numbers.
+
+   The PCI host bridge node migh have additional sub-nodes representing
+   the onboard PCI devices/PCI slots. Each such sub-node must have the
+   following mandatory properties:
+
+     - reg: used only for interrupt mapping, so only the first four bytes
+       are used to refer to the correct bus number and device number.
+
+     - device_type: must be "pci"
+
+     - status: either "disabled" or "okay"
+
+   If a given sub-node represents a PCI bridge it must have following
+   mandatory properties as well:
+
+     - #address-cells: must be set to <3>
+
+     - #size-cells: must set to <2>
+
+     - #interrupt-cells: must be set to <1>
+
+     - interrupt-map-mask,
+     - interrupt-map: standard PCI properties to define the mapping of the
+       PCI interface to interrupt numbers.
+
+3) Example:
+
+	pci@10140000 {
+		compatible = "ralink,rt3883-pci";
+		reg = <0x10140000 0x20000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges; /* direct mapping */
+
+		status = "disabled";
+
+		pciintc: interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+
+			interrupt-parent = <&cpuintc>;
+			interrupts = <4>;
+		};
+
+		host-bridge {
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+
+			device_type = "pci";
+
+			bus-range = <0 255>;
+			ranges = <
+				0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
+				0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
+			>;
+
+			interrupt-map-mask = <0xf800 0 0 7>;
+			interrupt-map = <
+				/* IDSEL 17 */
+				0x8800 0 0 1 &pciintc 18
+				0x8800 0 0 2 &pciintc 18
+				0x8800 0 0 3 &pciintc 18
+				0x8800 0 0 4 &pciintc 18
+				/* IDSEL 18 */
+				0x9000 0 0 1 &pciintc 19
+				0x9000 0 0 2 &pciintc 19
+				0x9000 0 0 3 &pciintc 19
+				0x9000 0 0 4 &pciintc 19
+			>;
+
+			pci-bridge@1 {
+				reg = <0x0800 0 0 0 0>;
+				device_type = "pci";
+				#interrupt-cells = <1>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+
+				interrupt-map-mask = <0x0 0 0 0>;
+				interrupt-map = <0x0 0 0 0 &pciintc 20>;
+
+				status = "disabled";
+			};
+
+			pci-slot@17 {
+				reg = <0x8800 0 0 0 0>;
+				device_type = "pci";
+
+				status = "disabled";
+			};
+
+			pci-slot@18 {
+				reg = <0x9000 0 0 0 0>;
+				device_type = "pci";
+
+				status = "disabled";
+			};
+		};
+	};
 --- a/arch/mips/pci/Makefile
 +++ b/arch/mips/pci/Makefile
-@@ -42,6 +42,7 @@ obj-$(CONFIG_SNI_RM)		+= fixup-sni.o ops
+@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80)	+= pci-bcm1
+ obj-$(CONFIG_SNI_RM)		+= fixup-sni.o ops-sni.o
 obj-$(CONFIG_LANTIQ)		+= fixup-lantiq.o
 obj-$(CONFIG_PCI_LANTIQ)	+= pci-lantiq.o ops-lantiq.o
- obj-$(CONFIG_SOC_RT2880)	+= pci-rt2880.o
 +obj-$(CONFIG_SOC_RT3883)	+= pci-rt3883.o
 obj-$(CONFIG_TANBAC_TB0219)	+= fixup-tb0219.o
 obj-$(CONFIG_TANBAC_TB0226)	+= fixup-tb0226.o
 obj-$(CONFIG_TANBAC_TB0287)	+= fixup-tb0287.o
 --- /dev/null
 +++ b/arch/mips/pci/pci-rt3883.c
-@@ -0,0 +1,640 @@
+@@ -0,0 +1,636 @@
 +/*
 + *  Ralink RT3662/RT3883 SoC PCI support
 + *
@ -91,6 +281,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	void __iomem *base;
 +	spinlock_t lock;
 +
+	struct device_node *intc_of_node;
 +	struct irq_domain *irq_domain;
 +
 +	struct pci_controller pci_controller;
@ -98,7 +289,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	struct resource mem_res;
 +
 +	bool pcie_ready;
-+	unsigned char p2p_devnum;
 +};
 +
 +static inline struct rt3883_pci_controller *
@ -125,8 +315,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
 +					 unsigned int func, unsigned int where)
 +{
-+	return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
-+		0x80000000);
+	return (bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
+	       0x80000000;
 +}
 +
 +static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
@ -237,45 +427,31 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +static int rt3883_pci_irq_init(struct device *dev,
 +			       struct rt3883_pci_controller *rpc)
 +{
-+	struct device_node *np = dev->of_node;
-+	struct device_node *intc_np;
 +	int irq;
-+	int err;
 +
-+	intc_np = of_get_child_by_name(np, "interrupt-controller");
-+	if (!intc_np) {
-+		dev_err(dev, "no %s child node found", "interrupt-controller");
-+		return -ENODEV;
-+	}
-+
-+	irq = irq_of_parse_and_map(intc_np, 0);
+	irq = irq_of_parse_and_map(rpc->intc_of_node, 0);
 +	if (irq == 0) {
-+		dev_err(dev, "%s has no IRQ", of_node_full_name(intc_np));
-+		err = -EINVAL;
-+		goto err_put_intc;
+		dev_err(dev, "%s has no IRQ",
+			of_node_full_name(rpc->intc_of_node));
+		return -EINVAL;
 +	}
 +
 +	/* disable all interrupts */
 +	rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
 +
 +	rpc->irq_domain =
-+		irq_domain_add_linear(intc_np, RT3883_PCI_IRQ_COUNT,
+		irq_domain_add_linear(rpc->intc_of_node, RT3883_PCI_IRQ_COUNT,
 +				      &rt3883_pci_irq_domain_ops,
 +				      rpc);
 +	if (!rpc->irq_domain) {
 +		dev_err(dev, "unable to add IRQ domain\n");
-+		err = -ENODEV;
-+		goto err_put_intc;
+		return -ENODEV;
 +	}
 +
 +	irq_set_handler_data(irq, rpc);
 +	irq_set_chained_handler(irq, rt3883_pci_irq_handler);
 +
 +	return 0;
-+
-+err_put_intc:
-+	of_node_put(intc_np);
-+	return err;
 +}
 +
 +static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
@ -462,21 +638,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
 +}
 +
-+static inline void
-+rt3883_dump_pci_config(struct rt3883_pci_controller *rpc,
-+		       int bus, int slot)
-+{
-+	int i;
-+
-+	for (i = 0; i < 16; i++) {
-+		u32 val;
-+
-+		val = rt3883_pci_read_cfg32(rpc, bus, slot, 0, i << 2);
-+		pr_info("pci %02x:%02x.0 0x%02x = %08x\n",
-+		        bus, slot, i << 2, val);
-+	}
-+}
-+
 +static int rt3883_pci_probe(struct platform_device *pdev)
 +{
 +	struct rt3883_pci_controller *rpc;
@ -500,28 +661,53 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	if (IS_ERR(rpc->base))
 +		return PTR_ERR(rpc->base);
 +
-+	rpc->pci_controller.of_node = of_get_child_by_name(np, "host-bridge");
+	/* find the interrupt controller child node */
+	for_each_child_of_node(np, child) {
+		if (of_get_property(child, "interrupt-controller", NULL) &&
+		    of_node_get(child)) {
+			rpc->intc_of_node = child;
+			break;
+		}
+	}
+
+	if (!rpc->intc_of_node) {
+		dev_err(dev, "% has no %s child node",
+			of_node_full_name(rpc->intc_of_node),
+			"interrupt controller");
+		return -EINVAL;
+	}
+
+	/* find the PCI host bridge child node */
+	for_each_child_of_node(np, child) {
+		if (child->type &&
+		    of_node_cmp(child->type, "pci") == 0 &&
+		    of_node_get(child)) {
+			rpc->pci_controller.of_node = child;
+			break;
+		}
+	}
+
 +	if (!rpc->pci_controller.of_node) {
-+		dev_err(dev, "no %s child node found", "host-bridge");
-+		return -ENODEV;
+		dev_err(dev, "%s has no %s child node",
+			of_node_full_name(rpc->intc_of_node),
+			"PCI host bridge");
+		err = -EINVAL;
+		goto err_put_intc_node;
 +	}
 +
 +	mode = RT3883_PCI_MODE_NONE;
-+	for_each_child_of_node(rpc->pci_controller.of_node, child) {
-+		u32 slot;
+	for_each_available_child_of_node(rpc->pci_controller.of_node, child) {
+		int devfn;
 +
-+		if (!of_device_is_available(child))
+		if (!child->type ||
+		    of_node_cmp(child->type, "pci") != 0)
 +			continue;
 +
-+		if (of_property_read_u32(child, "ralink,pci-slot",
-+					 &slot)) {
-+			dev_err(dev, "no '%s' property found for %s\n",
-+				"ralink,pci-slot",
-+				of_node_full_name(child));
+		devfn = of_pci_get_devfn(child);
+		if (devfn < 0)
 +			continue;
-+		}
 +
-+		switch (slot) {
+		switch (PCI_SLOT(devfn)) {
 +		case 1:
 +			mode |= RT3883_PCI_MODE_PCIE;
 +			break;
@ -608,17 +794,17 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +
 +err_put_hb_node:
 +	of_node_put(rpc->pci_controller.of_node);
+err_put_intc_node:
+	of_node_put(rpc->intc_of_node);
 +	return err;
 +}
 +
 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 +{
-+	struct rt3883_pci_controller *rpc;
 +	struct of_irq dev_irq;
 +	int err;
 +	int irq;
 +
-+	rpc = pci_bus_to_rt3883_controller(dev->bus);
 +	err = of_irq_map_pci(dev, &dev_irq);
 +	if (err) {
 +		pr_err("pci %s: unable to get irq map, err=%d\n",
@ -668,7 +854,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +postcore_initcall(rt3883_pci_init);
 --- a/arch/mips/ralink/Kconfig
 +++ b/arch/mips/ralink/Kconfig
-@@ -20,6 +20,7 @@ choice
+@@ -26,6 +26,7 @@ choice
 		bool "RT3883"
 		select USB_ARCH_HAS_OHCI
 		select USB_ARCH_HAS_EHCI
--- a/target/linux/ramips/patches-3.10/0028-reset-MIPS-ralink-add-core-device-reset-wrapper.patch
+++ b/target/linux/ramips/patches-3.10/0028-reset-MIPS-ralink-add-core-device-reset-wrapper.patch
@ -1,126 +0,0 @@
-From 0cc20912b376305452cdc5c8e7b97e156ba90e93 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Wed, 8 May 2013 22:08:39 +0200
-Subject: [PATCH 28/33] reset: MIPS: ralink: add core/device reset wrapper
-
-Add a helper for reseting different devices ont he SoC.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
---
- arch/mips/Kconfig        |    1 +
- arch/mips/ralink/of.c    |   59 ++++++++++++++++++++++++++++++++++++++++++++++
- arch/mips/ralink/reset.c |    1 +
- 3 files changed, 61 insertions(+)
-
--- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -444,6 +444,7 @@ config RALINK
- 	select HAVE_MACH_CLKDEV
- 	select CLKDEV_LOOKUP
- 	select ARCH_REQUIRE_GPIOLIB
-+	select ARCH_HAS_RESET_CONTROLLER
- 
- config SGI_IP22
- 	bool "SGI IP22 (Indy/Indigo2)"
--- a/arch/mips/ralink/of.c
-+++ b/arch/mips/ralink/of.c
-@@ -14,16 +14,22 @@
- #include <linux/sizes.h>
- #include <linux/of_fdt.h>
- #include <linux/kernel.h>
-+#include <linux/module.h>
- #include <linux/bootmem.h>
- #include <linux/of_platform.h>
- #include <linux/of_address.h>
-+#include <linux/reset-controller.h>
- 
- #include <asm/reboot.h>
- #include <asm/bootinfo.h>
- #include <asm/addrspace.h>
- 
-+#include <asm/mach-ralink/ralink_regs.h>
-+
- #include "common.h"
- 
-+#define SYSC_REG_RESET_CTRL     0x034
-+
- __iomem void *rt_sysc_membase;
- __iomem void *rt_memc_membase;
- 
-@@ -96,6 +102,53 @@ void __init plat_mem_setup(void)
- 				     soc_info.mem_size_max * SZ_1M);
- }
- 
-+static int ralink_assert_device(struct reset_controller_dev *rcdev, unsigned long id)
-+{
-+	u32 val;
-+
-+	if (id < 8)
-+		return -1;
-+
-+	val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
-+	val |= BIT(id);
-+	rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
-+
-+	return 0;
-+}
-+
-+static int ralink_deassert_device(struct reset_controller_dev *rcdev, unsigned long id)
-+{
-+	u32 val;
-+
-+	if (id < 8)
-+		return -1;
-+
-+	val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
-+	val &= ~BIT(id);
-+	rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
-+
-+	return 0;
-+}
-+
-+static int ralink_reset_device(struct reset_controller_dev *rcdev, unsigned long id)
-+{
-+	ralink_assert_device(rcdev, id);
-+	return ralink_deassert_device(rcdev, id);
-+}
-+
-+static struct reset_control_ops reset_ops = {
-+	.reset = ralink_reset_device,
-+	.assert = ralink_assert_device,
-+	.deassert = ralink_deassert_device,
-+};
-+
-+static struct reset_controller_dev reset_dev = {
-+	.ops			= &reset_ops,
-+	.owner			= THIS_MODULE,
-+	.nr_resets		= 32,
-+	.of_reset_n_cells	= 1,
-+};
-+
- static int __init plat_of_setup(void)
- {
- 	static struct of_device_id of_ids[3];
-@@ -110,6 +163,12 @@ static int __init plat_of_setup(void)
- 	if (of_platform_populate(NULL, of_ids, NULL, NULL))
- 		panic("failed to populate DT\n");
- 
-+	reset_dev.of_node = of_find_compatible_node(NULL, NULL, "ralink,rt2880-reset");
-+	if (!reset_dev.of_node)
-+		panic("Failed to find reset controller node");
-+
-+	reset_controller_register(&reset_dev);
-+
- 	ralink_pinmux();
- 
- 	return 0;
--- a/arch/mips/ralink/reset.c
-+++ b/arch/mips/ralink/reset.c
-@@ -10,6 +10,7 @@
- 
- #include <linux/pm.h>
- #include <linux/io.h>
-+#include <linux/module.h>
- 
- #include <asm/reboot.h>
- 
--- a/target/linux/ramips/patches-3.10/0100-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch
+++ b/target/linux/ramips/patches-3.10/0100-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch
@ -1,10 +1,10 @@
-From a1f29e15505226c6bc3a714daf91edccfc3a9e13 Mon Sep 17 00:00:00 2001
+From cdc1b12b3debaf5b3894fd146e73221a8acd0152 Mon Sep 17 00:00:00 2001
 From: John Crispin <blogic@openwrt.org>
 Date: Sun, 14 Jul 2013 23:08:11 +0200
-Subject: [PATCH 01/33] MIPS: use set_mode() to enable/disable the cevt-r4k
+Subject: [PATCH 20/25] MIPS: use set_mode() to enable/disable the cevt-r4k
 irq

- Signed-off-by: John Crispin <blogic@openwrt.org>
+Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
 arch/mips/kernel/cevt-r4k.c |   39 ++++++++++++++++++++++++++-------------
 1 file changed, 26 insertions(+), 13 deletions(-)
--- a/target/linux/ramips/patches-3.10/0101-MIPS-ralink-add-pinmux-driver.patch
+++ b/target/linux/ramips/patches-3.10/0101-MIPS-ralink-add-pinmux-driver.patch
@ -22,14 +22,14 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 
-obj-y := prom.o of.o reset.o clk.o irq.o
-+obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o
+-obj-y := prom.o of.o reset.o clk.o irq.o timer.o
+obj-y := prom.o of.o reset.o clk.o irq.o timer.o pinmux.o
+ 
+ obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
 
- obj-$(CONFIG_SOC_RT288X) += rt288x.o
- obj-$(CONFIG_SOC_RT305X) += rt305x.o
 --- a/arch/mips/ralink/common.h
 +++ b/arch/mips/ralink/common.h
-@@ -50,4 +50,6 @@ extern void prom_soc_init(struct ralink_
+@@ -52,4 +52,6 @@ extern void prom_soc_init(struct ralink_
 
 __iomem void *plat_of_remap_node(const char *node);
 
@ -38,9 +38,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 #endif /* _RALINK_COMMON_H__ */
 --- a/arch/mips/ralink/of.c
 +++ b/arch/mips/ralink/of.c
-@@ -110,6 +110,8 @@ static int __init plat_of_setup(void)
- 	if (of_platform_populate(NULL, of_ids, NULL, NULL))
- 		panic("failed to populate DT\n");
+@@ -113,6 +113,8 @@ static int __init plat_of_setup(void)
+ 	/* make sure ithat the reset controller is setup early */
+ 	ralink_rst_init();
 
 +	ralink_pinmux();
 +
--- a/target/linux/ramips/patches-3.10/0102-MIPS-ralink-add-verbose-pmu-info.patch
+++ b/target/linux/ramips/patches-3.10/0102-MIPS-ralink-add-verbose-pmu-info.patch
@ -12,9 +12,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>

 --- a/arch/mips/ralink/mt7620.c
 +++ b/arch/mips/ralink/mt7620.c
-@@ -20,6 +20,22 @@
- 
- #include "common.h"
+@@ -26,6 +26,22 @@
+ #define CLKCFG_FFRAC_MASK	0x001f
+ #define CLKCFG_FFRAC_USB_VAL	0x0003
 
 +/* analog */
 +#define PMU0_CFG		0x88
@ -35,7 +35,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 /* does the board have sdram or ddram */
 static int dram_type;
 
-@@ -187,6 +203,8 @@ void prom_soc_init(struct ralink_soc_inf
+@@ -208,6 +224,8 @@ void prom_soc_init(struct ralink_soc_inf
 	u32 n1;
 	u32 rev;
 	u32 cfg0;
@ -44,7 +44,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 
 	n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
 	n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
-@@ -234,4 +252,12 @@ void prom_soc_init(struct ralink_soc_inf
+@@ -255,4 +273,12 @@ void prom_soc_init(struct ralink_soc_inf
 		BUG();
 	}
 	soc_info->mem_base = MT7620_DRAM_BASE;
--- a/target/linux/ramips/patches-3.10/0103-MIPS-ralink-adds-a-bootrom-dumper-module.patch
+++ b/target/linux/ramips/patches-3.10/0103-MIPS-ralink-adds-a-bootrom-dumper-module.patch
@ -15,7 +15,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>

 --- a/arch/mips/ralink/Makefile
 +++ b/arch/mips/ralink/Makefile
-@@ -15,4 +15,6 @@ obj-$(CONFIG_SOC_MT7620) += mt7620.o
+@@ -17,4 +17,6 @@ obj-$(CONFIG_SOC_MT7620) += mt7620.o
 
 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
 
--- a/target/linux/ramips/patches-3.10/0104-MIPS-ralink-add-illegal-access-driver.patch
+++ b/target/linux/ramips/patches-3.10/0104-MIPS-ralink-add-illegal-access-driver.patch
@ -12,9 +12,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>

 --- a/arch/mips/ralink/Makefile
 +++ b/arch/mips/ralink/Makefile
-@@ -8,6 +8,8 @@
+@@ -10,6 +10,8 @@ obj-y := prom.o of.o reset.o clk.o irq.o
 
- obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o timer.o
+ obj-$(CONFIG_CLKEVT_RT3352) += cevt-rt3352.o
 
 +obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
 +
--- a/target/linux/ramips/patches-3.10/0105-MIPS-ralink-workaround-DTB-memory-issue.patch
+++ b/target/linux/ramips/patches-3.10/0105-MIPS-ralink-workaround-DTB-memory-issue.patch
--- a/target/linux/ramips/patches-3.10/0106-USB-dwc2.patch
+++ b/target/linux/ramips/patches-3.10/0106-USB-dwc2.patch
--- a/target/linux/ramips/patches-3.10/0107-PCI-MIPS-adds-rt2880-pci-support.patch
+++ b/target/linux/ramips/patches-3.10/0107-PCI-MIPS-adds-rt2880-pci-support.patch
@ -20,9 +20,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 obj-$(CONFIG_LANTIQ)		+= fixup-lantiq.o
 obj-$(CONFIG_PCI_LANTIQ)	+= pci-lantiq.o ops-lantiq.o
 +obj-$(CONFIG_SOC_RT2880)	+= pci-rt2880.o
+ obj-$(CONFIG_SOC_RT3883)	+= pci-rt3883.o
 obj-$(CONFIG_TANBAC_TB0219)	+= fixup-tb0219.o
 obj-$(CONFIG_TANBAC_TB0226)	+= fixup-tb0226.o
- obj-$(CONFIG_TANBAC_TB0287)	+= fixup-tb0287.o
 --- /dev/null
 +++ b/arch/mips/pci/pci-rt2880.c
@@ -0,0 +1,281 @@
@ -309,7 +309,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +arch_initcall(pcibios_init);
 --- a/arch/mips/ralink/Kconfig
 +++ b/arch/mips/ralink/Kconfig
-@@ -8,6 +8,7 @@ choice
+@@ -15,6 +15,7 @@ choice
 
 	config SOC_RT288X
 		bool "RT288x"
--- a/target/linux/ramips/patches-3.10/0108-PCI-MIPS-adds-mt7620a-pcie-driver.patch
+++ b/target/linux/ramips/patches-3.10/0108-PCI-MIPS-adds-mt7620a-pcie-driver.patch
@ -11,16 +11,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 3 files changed, 365 insertions(+)
 create mode 100644 arch/mips/pci/pci-mt7620a.c

--- a/arch/mips/pci/Makefile
-+++ b/arch/mips/pci/Makefile
-@@ -43,6 +43,7 @@ obj-$(CONFIG_LANTIQ)		+= fixup-lantiq.o
- obj-$(CONFIG_PCI_LANTIQ)	+= pci-lantiq.o ops-lantiq.o
- obj-$(CONFIG_SOC_RT2880)	+= pci-rt2880.o
- obj-$(CONFIG_SOC_RT3883)	+= pci-rt3883.o
-+obj-$(CONFIG_SOC_MT7620)	+= pci-mt7620a.o
- obj-$(CONFIG_TANBAC_TB0219)	+= fixup-tb0219.o
- obj-$(CONFIG_TANBAC_TB0226)	+= fixup-tb0226.o
- obj-$(CONFIG_TANBAC_TB0287)	+= fixup-tb0287.o
 --- /dev/null
 +++ b/arch/mips/pci/pci-mt7620a.c
@@ -0,0 +1,363 @@
@ -389,11 +379,21 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +arch_initcall(mt7620a_pci_init);
 --- a/arch/mips/ralink/Kconfig
 +++ b/arch/mips/ralink/Kconfig
-@@ -24,6 +24,7 @@ choice
- 
- 	config SOC_MT7620
+@@ -33,6 +33,7 @@ choice
 		bool "MT7620"
+ 		select USB_ARCH_HAS_OHCI
+ 		select USB_ARCH_HAS_EHCI
 +		select HW_HAS_PCI
 
 endchoice
 
+--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
+@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80)	+= pci-bcm1
+ obj-$(CONFIG_SNI_RM)		+= fixup-sni.o ops-sni.o
+ obj-$(CONFIG_LANTIQ)		+= fixup-lantiq.o
+ obj-$(CONFIG_PCI_LANTIQ)	+= pci-lantiq.o ops-lantiq.o
+obj-$(CONFIG_SOC_MT7620)	+= pci-mt7620a.o
+ obj-$(CONFIG_SOC_RT2880)	+= pci-rt2880.o
+ obj-$(CONFIG_SOC_RT3883)	+= pci-rt3883.o
+ obj-$(CONFIG_TANBAC_TB0219)	+= fixup-tb0219.o
--- a/target/linux/ramips/patches-3.10/0109-NET-multi-phy-support.patch
+++ b/target/linux/ramips/patches-3.10/0109-NET-multi-phy-support.patch
--- a/target/linux/ramips/patches-3.10/0110-NET-add-of_get_mac_address_mtd.patch
+++ b/target/linux/ramips/patches-3.10/0110-NET-add-of_get_mac_address_mtd.patch
--- a/target/linux/ramips/patches-3.10/0111-NET-MIPS-add-ralink-SoC-ethernet-driver.patch
+++ b/target/linux/ramips/patches-3.10/0111-NET-MIPS-add-ralink-SoC-ethernet-driver.patch
--- a/target/linux/ramips/patches-3.10/0112-USB-phy-add-ralink-SoC-driver.patch
+++ b/target/linux/ramips/patches-3.10/0112-USB-phy-add-ralink-SoC-driver.patch
--- a/target/linux/ramips/patches-3.10/0113-USB-add-OHCI-EHCI-OF-binding.patch
+++ b/target/linux/ramips/patches-3.10/0113-USB-add-OHCI-EHCI-OF-binding.patch
@ -13,17 +13,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 drivers/usb/host/ohci-platform.c |   37 ++++++++++++++++++++++++++++++++-----
 4 files changed, 51 insertions(+), 10 deletions(-)

--- a/arch/mips/ralink/Kconfig
-+++ b/arch/mips/ralink/Kconfig
-@@ -24,6 +24,8 @@ choice
- 
- 	config SOC_MT7620
- 		bool "MT7620"
-+		select USB_ARCH_HAS_OHCI
-+		select USB_ARCH_HAS_EHCI
- 		select HW_HAS_PCI
- 
- endchoice
 --- a/drivers/usb/Makefile
 +++ b/drivers/usb/Makefile
@@ -10,6 +10,8 @@ obj-$(CONFIG_USB_DWC3)		+= dwc3/
--- a/target/linux/ramips/patches-3.10/0114-serial-ralink-adds-mt7620-serial.patch
+++ b/target/linux/ramips/patches-3.10/0114-serial-ralink-adds-mt7620-serial.patch
--- a/target/linux/ramips/patches-3.10/0115-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch
+++ b/target/linux/ramips/patches-3.10/0115-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch
--- a/target/linux/ramips/patches-3.10/0116-i2c-MIPS-adds-ralink-I2C-driver.patch
+++ b/target/linux/ramips/patches-3.10/0116-i2c-MIPS-adds-ralink-I2C-driver.patch
--- a/target/linux/ramips/patches-3.10/0117-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
+++ b/target/linux/ramips/patches-3.10/0117-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
--- a/target/linux/ramips/patches-3.10/0118-mtd-fix-cfi-cmdset-0002-erase-status-check.patch
+++ b/target/linux/ramips/patches-3.10/0118-mtd-fix-cfi-cmdset-0002-erase-status-check.patch
--- a/target/linux/ramips/patches-3.10/0119-mtd-cfi-cmdset-0002-force-word-write.patch
+++ b/target/linux/ramips/patches-3.10/0119-mtd-cfi-cmdset-0002-force-word-write.patch
--- a/target/linux/ramips/patches-3.10/0120-spi-introduce-macros-to-set-bits_per_word_mask.patch
+++ b/target/linux/ramips/patches-3.10/0120-spi-introduce-macros-to-set-bits_per_word_mask.patch
@ -0,0 +1,29 @@
+From 2922a8de996956893bb98e4aa91be9774c958336 Mon Sep 17 00:00:00 2001
+From: Stephen Warren <swarren@wwwdotorg.org>
+Date: Tue, 21 May 2013 20:36:34 -0600
+Subject: [PATCH] spi: introduce macros to set bits_per_word_mask
+
+Introduce two macros to make setting up spi_master.bits_per_word_mask
+easier, and avoid mistakes like writing BIT(n) instead of BIT(n - 1).
+
+SPI_BPW_MASK is for a single supported value of bits_per_word_mask.
+
+SPI_BPW_RANGE_MASK represents a contiguous set of bit lengths.
+
+Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
+Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
+---
+ include/linux/spi/spi.h |    2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
+@@ -308,6 +308,8 @@ struct spi_master {
+ 
+ 	/* bitmask of supported bits_per_word for transfers */
+ 	u32			bits_per_word_mask;
+#define SPI_BPW_MASK(bits) BIT((bits) - 1)
+#define SPI_BPW_RANGE_MASK(min, max) ((BIT(max) - 1) - (BIT(min) - 1))
+ 
+ 	/* other constraints relevant to this driver */
+ 	u16			flags;
--- a/target/linux/ramips/patches-3.10/0121-MIPS-ralink-add-rt_sysc_m32-helper.patch
+++ b/target/linux/ramips/patches-3.10/0121-MIPS-ralink-add-rt_sysc_m32-helper.patch
--- a/target/linux/ramips/patches-3.10/0200-owrt-GPIO-add-gpio_export_with_name.patch
+++ b/target/linux/ramips/patches-3.10/0200-owrt-GPIO-add-gpio_export_with_name.patch
--- a/target/linux/ramips/patches-3.10/0201-owrt-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on.patch
+++ b/target/linux/ramips/patches-3.10/0201-owrt-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on.patch
@ -248,9 +248,9 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 	struct clk *clk;
 +	int ret;
 
- 	if (!res) {
- 		dev_err(&pdev->dev, "no memory resource found\n");
-@@ -147,12 +310,29 @@ static int rt_timer_probe(struct platfor
+ 	rt = devm_kzalloc(&pdev->dev, sizeof(*rt), GFP_KERNEL);
+ 	if (!rt) {
+@@ -140,12 +303,29 @@ static int rt_timer_probe(struct platfor
 	if (!rt->timer_freq)
 		return -EINVAL;
 
@ -283,7 +283,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 
 	dev_info(&pdev->dev, "maximum frequncy is %luHz\n", rt->timer_freq);
 
-@@ -163,6 +343,7 @@ static int rt_timer_remove(struct platfo
+@@ -156,6 +336,7 @@ static int rt_timer_remove(struct platfo
 {
 	struct rt_timer *rt = platform_get_drvdata(pdev);
 
@ -291,7 +291,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 	rt_timer_disable(rt);
 	rt_timer_free(rt);
 
-@@ -187,6 +368,6 @@ static struct platform_driver rt_timer_d
+@@ -180,6 +361,6 @@ static struct platform_driver rt_timer_d
 
 module_platform_driver(rt_timer_driver);
 
--- a/target/linux/ramips/patches-3.10/0202-owrt-USB-adds-dwc_otg.patch
+++ b/target/linux/ramips/patches-3.10/0202-owrt-USB-adds-dwc_otg.patch
--- a/target/linux/ramips/patches-3.10/0203-owrt-MIPS-add-OWRTDTB-secion.patch
+++ b/target/linux/ramips/patches-3.10/0203-owrt-MIPS-add-OWRTDTB-secion.patch
@ -24,7 +24,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 NESTED(kernel_entry, 16, sp)			# kernel entry point
 --- a/arch/mips/ralink/Makefile
 +++ b/arch/mips/ralink/Makefile
-@@ -19,4 +19,4 @@ obj-$(CONFIG_EARLY_PRINTK) += early_prin
+@@ -21,4 +21,4 @@ obj-$(CONFIG_EARLY_PRINTK) += early_prin
 
 obj-$(CONFIG_DEBUG_FS) += bootrom.o
 
@ -32,7 +32,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#obj-y += dts/
 --- a/arch/mips/ralink/of.c
 +++ b/arch/mips/ralink/of.c
-@@ -83,6 +83,8 @@ void __init device_tree_init(void)
+@@ -77,6 +77,8 @@ void __init device_tree_init(void)
 	//free_bootmem(base, size);
 }
 
@ -41,7 +41,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 void __init plat_mem_setup(void)
 {
 	set_io_port_base(KSEG1);
-@@ -91,7 +93,7 @@ void __init plat_mem_setup(void)
+@@ -85,7 +87,7 @@ void __init plat_mem_setup(void)
 	 * Load the builtin devicetree. This causes the chosen node to be
 	 * parsed resulting in our memory appearing
 	 */
--- a/target/linux/ramips/patches-3.10/0204-owrt-mtd-split-remove-padding.patch
+++ b/target/linux/ramips/patches-3.10/0204-owrt-mtd-split-remove-padding.patch
--- a/target/linux/ramips/rt288x/config-3.10
+++ b/target/linux/ramips/rt288x/config-3.10
@ -138,7 +138,7 @@ CONFIG_SOC_RT288X=y
 # CONFIG_SOC_RT3883 is not set
 CONFIG_SPI=y
 CONFIG_SPI_MASTER=y
-CONFIG_SPI_RALINK=y
+CONFIG_SPI_RT2880=y
 CONFIG_SWCONFIG=y
 CONFIG_SYS_HAS_CPU_MIPS32_R1=y
 CONFIG_SYS_HAS_CPU_MIPS32_R2=y
--- a/target/linux/ramips/rt288x/config-3.9
+++ b/target/linux/ramips/rt288x/config-3.9
@ -1,158 +0,0 @@
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_RT2880_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_RALINK=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_MACH_CLKDEV=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM=m
-CONFIG_IMAGE_CMDLINE_HACK=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_M25PXX_USE_FAST_READ=y
-CONFIG_MDIO_BOARDINFO=y
-# CONFIG_MII is not set
-CONFIG_MIPS=y
-# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=4
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_MT_DISABLED=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_OF_PARTS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_UIMAGE_SPLIT=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK=y
-CONFIG_NET_RALINK_MDIO=y
-CONFIG_NET_RALINK_MDIO_RT2880=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DEVICE=y
-# CONFIG_OF_DISPLAY_TIMING is not set
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-# CONFIG_OF_VIDEOMODE is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-# CONFIG_PCI is not set
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_RALINK=y
-# CONFIG_RALINK_ILL_ACC is not set
-# CONFIG_RALINK_USBPHY is not set
-CONFIG_RALINK_WDT=y
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SOC_MT7620 is not set
-CONFIG_SOC_RT288X=y
-# CONFIG_SOC_RT305X is not set
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_RALINK=y
-CONFIG_SWCONFIG=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_UIDGID_CONVERTED=y
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-# CONFIG_USB_ARCH_HAS_HCD is not set
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_XHCI is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZONE_DMA_FLAG=0
--- a/target/linux/ramips/rt305x/config-3.10
+++ b/target/linux/ramips/rt305x/config-3.10
@ -140,7 +140,7 @@ CONFIG_SOC_RT305X=y
 # CONFIG_SOC_RT3883 is not set
 CONFIG_SPI=y
 CONFIG_SPI_MASTER=y
-CONFIG_SPI_RALINK=y
+CONFIG_SPI_RT2880=y
 CONFIG_SWCONFIG=y
 CONFIG_SYS_HAS_CPU_MIPS32_R1=y
 CONFIG_SYS_HAS_CPU_MIPS32_R2=y
--- a/target/linux/ramips/rt305x/config-3.9
+++ b/target/linux/ramips/rt305x/config-3.9
@ -1,158 +0,0 @@
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLKEVT_RT3352=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLKSRC_OF=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_RT305X_EVAL is not set
-# CONFIG_DTB_RT5350_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-# CONFIG_DWC_OTG is not set
-CONFIG_EARLY_PRINTK=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_RALINK=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_MACH_CLKDEV=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HW_RANDOM=m
-CONFIG_IMAGE_CMDLINE_HACK=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_M25PXX_USE_FAST_READ=y
-CONFIG_MDIO_BOARDINFO=y
-# CONFIG_MII is not set
-CONFIG_MIPS=y
-# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_MT_DISABLED=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_OF_PARTS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_UIMAGE_SPLIT=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK=y
-CONFIG_NET_RALINK_ESW_RT3052=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DEVICE=y
-# CONFIG_OF_DISPLAY_TIMING is not set
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-# CONFIG_OF_VIDEOMODE is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_RALINK=y
-# CONFIG_RALINK_ILL_ACC is not set
-CONFIG_RALINK_USBPHY=y
-CONFIG_RALINK_WDT=y
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_RESET_CONTROLLER=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SOC_MT7620 is not set
-# CONFIG_SOC_RT288X is not set
-CONFIG_SOC_RT305X=y
-# CONFIG_SOC_RT3883 is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_RALINK=y
-CONFIG_SWCONFIG=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_UIDGID_CONVERTED=y
-# CONFIG_USB_ARCH_HAS_XHCI is not set
-CONFIG_USB_OTG_UTILS=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZONE_DMA_FLAG=0
--- a/target/linux/ramips/rt3883/config-3.10
+++ b/target/linux/ramips/rt3883/config-3.10
@ -149,7 +149,7 @@ CONFIG_SLUB=y
 CONFIG_SOC_RT3883=y
 CONFIG_SPI=y
 CONFIG_SPI_MASTER=y
-CONFIG_SPI_RALINK=y
+CONFIG_SPI_RT2880=y
 CONFIG_SWCONFIG=y
 CONFIG_SYS_HAS_CPU_MIPS32_R1=y
 CONFIG_SYS_HAS_CPU_MIPS32_R2=y
--- a/target/linux/ramips/rt3883/config-3.9
+++ b/target/linux/ramips/rt3883/config-3.9
@ -1,166 +0,0 @@
-CONFIG_AR8216_PHY=y
-CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
-CONFIG_ARCH_DISCARD_MEMBLOCK=y
-CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
-CONFIG_ARCH_HAS_RESET_CONTROLLER=y
-CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKDEV_LOOKUP=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-# CONFIG_CPU_MIPS32_R1 is not set
-CONFIG_CPU_MIPS32_R2=y
-CONFIG_CPU_MIPSR2=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_R4K_FPU=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CSRC_R4K=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_DTB_RT3883_EVAL is not set
-CONFIG_DTB_RT_NONE=y
-CONFIG_DTC=y
-CONFIG_EARLY_PRINTK=y
-CONFIG_ETHERNET_PACKET_MANGLE=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_IO=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_DEVRES=y
-CONFIG_GPIO_RALINK=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
-CONFIG_HAVE_ARCH_JUMP_LABEL=y
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_C_RECORDMCOUNT=y
-CONFIG_HAVE_DEBUG_KMEMLEAK=y
-CONFIG_HAVE_DMA_API_DEBUG=y
-CONFIG_HAVE_DMA_ATTRS=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_GENERIC_HARDIRQS=y
-CONFIG_HAVE_IDE=y
-CONFIG_HAVE_MACH_CLKDEV=y
-CONFIG_HAVE_MEMBLOCK=y
-CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
-CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
-CONFIG_HAVE_NET_DSA=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_HW_HAS_PCI=y
-CONFIG_HW_RANDOM=m
-CONFIG_IMAGE_CMDLINE_HACK=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_CPU=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_M25PXX_USE_FAST_READ=y
-CONFIG_MDIO_BOARDINFO=y
-# CONFIG_MII is not set
-CONFIG_MIPS=y
-# CONFIG_MIPS_HUGE_TLB_SUPPORT is not set
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-# CONFIG_MIPS_MACHINE is not set
-CONFIG_MIPS_MT_DISABLED=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MTD_CFI_INTELEXT is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_OF_PARTS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_UIMAGE_SPLIT=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_RALINK=y
-CONFIG_NET_RALINK_MDIO=y
-CONFIG_NET_RALINK_MDIO_RT2880=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DEVICE=y
-# CONFIG_OF_DISPLAY_TIMING is not set
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_MDIO=y
-CONFIG_OF_MTD=y
-CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
-# CONFIG_OF_VIDEOMODE is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PHYLIB=y
-# CONFIG_PREEMPT_RCU is not set
-CONFIG_RALINK=y
-# CONFIG_RALINK_ILL_ACC is not set
-CONFIG_RALINK_USBPHY=y
-CONFIG_RALINK_WDT=y
-# CONFIG_RCU_STALL_COMMON is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RTL8366_SMI=y
-CONFIG_RTL8367B_PHY=y
-CONFIG_RTL8367_PHY=y
-# CONFIG_SCSI_DMA is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RT288X=y
-CONFIG_SERIAL_OF_PLATFORM=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SOC_MT7620 is not set
-# CONFIG_SOC_RT288X is not set
-# CONFIG_SOC_RT305X is not set
-CONFIG_SOC_RT3883=y
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_RALINK=y
-CONFIG_SWCONFIG=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_UIDGID_CONVERTED=y
-CONFIG_USB_ARCH_HAS_XHCI=y
-CONFIG_USB_OTG_UTILS=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_ZONE_DMA_FLAG=0